2006.168.08:41:30.10:Log Opened: Mark IV Field System Version 9.7.7 2006.168.08:41:30.10:location,TSUKUB32,-140.09,36.10,61.0 2006.168.08:41:30.11:horizon1,0.,5.,360. 2006.168.08:41:30.11:antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.168.08:41:30.11:equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.168.08:41:30.12:drivev11,330,270,no 2006.168.08:41:30.12:drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.168.08:41:30.12:drivev13,15.000,268,10.000,10.000,10.000 2006.168.08:41:30.13:drivev21,330,270,no 2006.168.08:41:30.13:drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.168.08:41:30.13:drivev23,15.000,268,10.000,10.000,10.000 2006.168.08:41:30.14:head10,all,all,all,odd,adaptive,no,5.0000,1 2006.168.08:41:30.19:head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.168.08:41:30.19:head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.168.08:41:30.19:head20,all,all,all,odd,adaptive,no,5.0000,1 2006.168.08:41:30.20:head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.168.08:41:30.20:head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.168.08:41:30.21:time,-0.364,101.533,rate 2006.168.08:41:30.21:flagr,200 2006.168.08:41:30.21:proc=k06169ts 2006.168.08:41:30.22:" k06169 2006 tsukub32 t ts 2006.168.08:41:30.22:" t tsukub32 azel .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 ts 108 2006.168.08:41:30.23:" ts tsukub32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.168.08:41:30.27:" 108 tsukub32 14 17400 2006.168.08:41:30.28:" drudg version 050216 compiled under fs 9.7.07 2006.168.08:41:30.28:" rack=k4-2/m4 recorder 1=k5 recorder 2=none 2006.168.08:41:30.28:!2006.169.07:19:50 2006.169.07:19:50.00:unstow 2006.169.07:19:50.00&unstow/antenna=e 2006.169.07:19:50.00&unstow/!+10s 2006.169.07:19:50.00&unstow/antenna=m2 2006.169.07:20:02.01:scan_name=169-0730,k06169,60 2006.169.07:20:02.01:source=3c371,180650.68,694928.1,2000.0,ccw 2006.169.07:20:02.01#antcn#PM 1 00019 2005 228 00 22 31 00 2006.169.07:20:02.01#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.169.07:20:02.01#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.169.07:20:02.01#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.169.07:20:02.01#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.169.07:20:02.01#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.169.07:20:03.14:ready_k5 2006.169.07:20:03.14&ready_k5/obsinfo=st 2006.169.07:20:03.14&ready_k5/autoobs=1 2006.169.07:20:03.14&ready_k5/autoobs=2 2006.169.07:20:03.14&ready_k5/autoobs=3 2006.169.07:20:03.14&ready_k5/autoobs=4 2006.169.07:20:03.14&ready_k5/obsinfo 2006.169.07:20:03.14/obsinfo=st/error_log.tmp was not found (or not removed). 2006.169.07:20:03.14#flagr#flagr/antenna,new-source 2006.169.07:20:06.34/autoobs//k5ts1/ autoobs started! 2006.169.07:20:09.47/autoobs//k5ts2/ autoobs started! 2006.169.07:20:34.57/autoobs//k5ts3?ERROR: timeout happened! //k5ts3?ERROR: timeout happened! 2006.169.07:20:37.71/autoobs//k5ts4/ autoobs started! 2006.169.07:20:37.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.07:20:37.85:4f8m12a=1 2006.169.07:20:37.85&4f8m12a/xlog=on 2006.169.07:20:37.85&4f8m12a/echo=on 2006.169.07:20:37.85&4f8m12a/pcalon 2006.169.07:20:37.85&4f8m12a/"tpicd=stop 2006.169.07:20:37.85&4f8m12a/vc4f8 2006.169.07:20:37.85&4f8m12a/ifd4f 2006.169.07:20:37.85&4f8m12a/"form=m,16.000,1:2 2006.169.07:20:37.85&4f8m12a/"tpicd 2006.169.07:20:37.85&4f8m12a/echo=off 2006.169.07:20:37.85&4f8m12a/xlog=off 2006.169.07:20:37.85$4f8m12a/echo=on 2006.169.07:20:37.85$4f8m12a/pcalon 2006.169.07:20:37.85&pcalon/"no phase cal control is implemented here 2006.169.07:20:37.85$pcalon/"no phase cal control is implemented here 2006.169.07:20:37.85$4f8m12a/"tpicd=stop 2006.169.07:20:37.85$4f8m12a/vc4f8 2006.169.07:20:37.85&vc4f8/valo=1,532.99 2006.169.07:20:37.85&vc4f8/va=1,8 2006.169.07:20:37.85&vc4f8/valo=2,572.99 2006.169.07:20:37.85&vc4f8/va=2,7 2006.169.07:20:37.85&vc4f8/valo=3,672.99 2006.169.07:20:37.85&vc4f8/va=3,6 2006.169.07:20:37.85&vc4f8/valo=4,832.99 2006.169.07:20:37.85&vc4f8/va=4,7 2006.169.07:20:37.85&vc4f8/valo=5,652.99 2006.169.07:20:37.85&vc4f8/va=5,7 2006.169.07:20:37.85&vc4f8/valo=6,772.99 2006.169.07:20:37.85&vc4f8/va=6,6 2006.169.07:20:37.85&vc4f8/valo=7,832.99 2006.169.07:20:37.85&vc4f8/va=7,6 2006.169.07:20:37.85&vc4f8/valo=8,852.99 2006.169.07:20:37.85&vc4f8/va=8,7 2006.169.07:20:37.85&vc4f8/vblo=1,632.99 2006.169.07:20:37.85&vc4f8/vb=1,4 2006.169.07:20:37.85&vc4f8/vblo=2,640.99 2006.169.07:20:37.85&vc4f8/vb=2,4 2006.169.07:20:37.85&vc4f8/vblo=3,656.99 2006.169.07:20:37.85&vc4f8/vb=3,4 2006.169.07:20:37.85&vc4f8/vblo=4,712.99 2006.169.07:20:37.85&vc4f8/vb=4,4 2006.169.07:20:37.85&vc4f8/vblo=5,744.99 2006.169.07:20:37.85&vc4f8/vb=5,4 2006.169.07:20:37.85&vc4f8/vblo=6,752.99 2006.169.07:20:37.86&vc4f8/vb=6,4 2006.169.07:20:37.86&vc4f8/vabw=wide 2006.169.07:20:37.86&vc4f8/vbbw=wide 2006.169.07:20:37.86$vc4f8/valo=1,532.99 2006.169.07:20:37.86#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.169.07:20:37.86#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.169.07:20:37.86#ibcon#ireg 17 cls_cnt 0 2006.169.07:20:37.86#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:20:37.86#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:20:37.86#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:20:37.86#ibcon#enter wrdev, iclass 28, count 0 2006.169.07:20:37.86#ibcon#first serial, iclass 28, count 0 2006.169.07:20:37.86#ibcon#enter sib2, iclass 28, count 0 2006.169.07:20:37.86#ibcon#flushed, iclass 28, count 0 2006.169.07:20:37.86#ibcon#about to write, iclass 28, count 0 2006.169.07:20:37.86#ibcon#wrote, iclass 28, count 0 2006.169.07:20:37.86#ibcon#about to read 3, iclass 28, count 0 2006.169.07:20:37.88#ibcon#read 3, iclass 28, count 0 2006.169.07:20:37.88#ibcon#about to read 4, iclass 28, count 0 2006.169.07:20:37.88#ibcon#read 4, iclass 28, count 0 2006.169.07:20:37.88#ibcon#about to read 5, iclass 28, count 0 2006.169.07:20:37.88#ibcon#read 5, iclass 28, count 0 2006.169.07:20:37.88#ibcon#about to read 6, iclass 28, count 0 2006.169.07:20:37.88#ibcon#read 6, iclass 28, count 0 2006.169.07:20:37.88#ibcon#end of sib2, iclass 28, count 0 2006.169.07:20:37.88#ibcon#*mode == 0, iclass 28, count 0 2006.169.07:20:37.88#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.169.07:20:37.88#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.07:20:37.88#ibcon#*before write, iclass 28, count 0 2006.169.07:20:37.88#ibcon#enter sib2, iclass 28, count 0 2006.169.07:20:37.88#ibcon#flushed, iclass 28, count 0 2006.169.07:20:37.88#ibcon#about to write, iclass 28, count 0 2006.169.07:20:37.88#ibcon#wrote, iclass 28, count 0 2006.169.07:20:37.88#ibcon#about to read 3, iclass 28, count 0 2006.169.07:20:37.94#ibcon#read 3, iclass 28, count 0 2006.169.07:20:37.94#ibcon#about to read 4, iclass 28, count 0 2006.169.07:20:37.94#ibcon#read 4, iclass 28, count 0 2006.169.07:20:37.94#ibcon#about to read 5, iclass 28, count 0 2006.169.07:20:37.94#ibcon#read 5, iclass 28, count 0 2006.169.07:20:37.94#ibcon#about to read 6, iclass 28, count 0 2006.169.07:20:37.94#ibcon#read 6, iclass 28, count 0 2006.169.07:20:37.94#ibcon#end of sib2, iclass 28, count 0 2006.169.07:20:37.94#ibcon#*after write, iclass 28, count 0 2006.169.07:20:37.94#ibcon#*before return 0, iclass 28, count 0 2006.169.07:20:37.94#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:20:37.94#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:20:37.94#ibcon#about to clear, iclass 28 cls_cnt 0 2006.169.07:20:37.94#ibcon#cleared, iclass 28 cls_cnt 0 2006.169.07:20:37.94$vc4f8/va=1,8 2006.169.07:20:37.94#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.169.07:20:37.94#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.169.07:20:37.94#ibcon#ireg 11 cls_cnt 2 2006.169.07:20:37.94#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:20:37.94#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:20:37.94#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:20:37.94#ibcon#enter wrdev, iclass 30, count 2 2006.169.07:20:37.94#ibcon#first serial, iclass 30, count 2 2006.169.07:20:37.94#ibcon#enter sib2, iclass 30, count 2 2006.169.07:20:37.94#ibcon#flushed, iclass 30, count 2 2006.169.07:20:37.94#ibcon#about to write, iclass 30, count 2 2006.169.07:20:37.94#ibcon#wrote, iclass 30, count 2 2006.169.07:20:37.94#ibcon#about to read 3, iclass 30, count 2 2006.169.07:20:37.95#ibcon#read 3, iclass 30, count 2 2006.169.07:20:37.95#ibcon#about to read 4, iclass 30, count 2 2006.169.07:20:37.95#ibcon#read 4, iclass 30, count 2 2006.169.07:20:37.95#ibcon#about to read 5, iclass 30, count 2 2006.169.07:20:37.95#ibcon#read 5, iclass 30, count 2 2006.169.07:20:37.95#ibcon#about to read 6, iclass 30, count 2 2006.169.07:20:37.95#ibcon#read 6, iclass 30, count 2 2006.169.07:20:37.95#ibcon#end of sib2, iclass 30, count 2 2006.169.07:20:37.95#ibcon#*mode == 0, iclass 30, count 2 2006.169.07:20:37.95#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.169.07:20:37.95#ibcon#[25=AT01-08\r\n] 2006.169.07:20:37.95#ibcon#*before write, iclass 30, count 2 2006.169.07:20:37.95#ibcon#enter sib2, iclass 30, count 2 2006.169.07:20:37.95#ibcon#flushed, iclass 30, count 2 2006.169.07:20:37.95#ibcon#about to write, iclass 30, count 2 2006.169.07:20:37.95#ibcon#wrote, iclass 30, count 2 2006.169.07:20:37.95#ibcon#about to read 3, iclass 30, count 2 2006.169.07:20:37.98#ibcon#read 3, iclass 30, count 2 2006.169.07:20:37.98#ibcon#about to read 4, iclass 30, count 2 2006.169.07:20:37.98#ibcon#read 4, iclass 30, count 2 2006.169.07:20:37.98#ibcon#about to read 5, iclass 30, count 2 2006.169.07:20:37.98#ibcon#read 5, iclass 30, count 2 2006.169.07:20:37.98#ibcon#about to read 6, iclass 30, count 2 2006.169.07:20:37.98#ibcon#read 6, iclass 30, count 2 2006.169.07:20:37.98#ibcon#end of sib2, iclass 30, count 2 2006.169.07:20:37.98#ibcon#*after write, iclass 30, count 2 2006.169.07:20:37.98#ibcon#*before return 0, iclass 30, count 2 2006.169.07:20:37.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:20:37.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:20:37.98#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.169.07:20:37.98#ibcon#ireg 7 cls_cnt 0 2006.169.07:20:37.98#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:20:38.10#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:20:38.10#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:20:38.10#ibcon#enter wrdev, iclass 30, count 0 2006.169.07:20:38.10#ibcon#first serial, iclass 30, count 0 2006.169.07:20:38.10#ibcon#enter sib2, iclass 30, count 0 2006.169.07:20:38.10#ibcon#flushed, iclass 30, count 0 2006.169.07:20:38.10#ibcon#about to write, iclass 30, count 0 2006.169.07:20:38.10#ibcon#wrote, iclass 30, count 0 2006.169.07:20:38.10#ibcon#about to read 3, iclass 30, count 0 2006.169.07:20:38.12#ibcon#read 3, iclass 30, count 0 2006.169.07:20:38.12#ibcon#about to read 4, iclass 30, count 0 2006.169.07:20:38.12#ibcon#read 4, iclass 30, count 0 2006.169.07:20:38.12#ibcon#about to read 5, iclass 30, count 0 2006.169.07:20:38.12#ibcon#read 5, iclass 30, count 0 2006.169.07:20:38.12#ibcon#about to read 6, iclass 30, count 0 2006.169.07:20:38.12#ibcon#read 6, iclass 30, count 0 2006.169.07:20:38.12#ibcon#end of sib2, iclass 30, count 0 2006.169.07:20:38.12#ibcon#*mode == 0, iclass 30, count 0 2006.169.07:20:38.12#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.169.07:20:38.12#ibcon#[25=USB\r\n] 2006.169.07:20:38.12#ibcon#*before write, iclass 30, count 0 2006.169.07:20:38.12#ibcon#enter sib2, iclass 30, count 0 2006.169.07:20:38.12#ibcon#flushed, iclass 30, count 0 2006.169.07:20:38.12#ibcon#about to write, iclass 30, count 0 2006.169.07:20:38.12#ibcon#wrote, iclass 30, count 0 2006.169.07:20:38.12#ibcon#about to read 3, iclass 30, count 0 2006.169.07:20:38.15#ibcon#read 3, iclass 30, count 0 2006.169.07:20:38.15#ibcon#about to read 4, iclass 30, count 0 2006.169.07:20:38.15#ibcon#read 4, iclass 30, count 0 2006.169.07:20:38.15#ibcon#about to read 5, iclass 30, count 0 2006.169.07:20:38.15#ibcon#read 5, iclass 30, count 0 2006.169.07:20:38.15#ibcon#about to read 6, iclass 30, count 0 2006.169.07:20:38.15#ibcon#read 6, iclass 30, count 0 2006.169.07:20:38.15#ibcon#end of sib2, iclass 30, count 0 2006.169.07:20:38.15#ibcon#*after write, iclass 30, count 0 2006.169.07:20:38.15#ibcon#*before return 0, iclass 30, count 0 2006.169.07:20:38.15#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:20:38.15#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:20:38.15#ibcon#about to clear, iclass 30 cls_cnt 0 2006.169.07:20:38.15#ibcon#cleared, iclass 30 cls_cnt 0 2006.169.07:20:38.15$vc4f8/valo=2,572.99 2006.169.07:20:38.15#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.169.07:20:38.15#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.169.07:20:38.15#ibcon#ireg 17 cls_cnt 0 2006.169.07:20:38.15#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:20:38.15#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:20:38.15#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:20:38.15#ibcon#enter wrdev, iclass 32, count 0 2006.169.07:20:38.15#ibcon#first serial, iclass 32, count 0 2006.169.07:20:38.15#ibcon#enter sib2, iclass 32, count 0 2006.169.07:20:38.15#ibcon#flushed, iclass 32, count 0 2006.169.07:20:38.15#ibcon#about to write, iclass 32, count 0 2006.169.07:20:38.15#ibcon#wrote, iclass 32, count 0 2006.169.07:20:38.15#ibcon#about to read 3, iclass 32, count 0 2006.169.07:20:38.18#ibcon#read 3, iclass 32, count 0 2006.169.07:20:38.18#ibcon#about to read 4, iclass 32, count 0 2006.169.07:20:38.18#ibcon#read 4, iclass 32, count 0 2006.169.07:20:38.18#ibcon#about to read 5, iclass 32, count 0 2006.169.07:20:38.18#ibcon#read 5, iclass 32, count 0 2006.169.07:20:38.18#ibcon#about to read 6, iclass 32, count 0 2006.169.07:20:38.18#ibcon#read 6, iclass 32, count 0 2006.169.07:20:38.18#ibcon#end of sib2, iclass 32, count 0 2006.169.07:20:38.18#ibcon#*mode == 0, iclass 32, count 0 2006.169.07:20:38.18#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.169.07:20:38.18#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.07:20:38.18#ibcon#*before write, iclass 32, count 0 2006.169.07:20:38.18#ibcon#enter sib2, iclass 32, count 0 2006.169.07:20:38.18#ibcon#flushed, iclass 32, count 0 2006.169.07:20:38.18#ibcon#about to write, iclass 32, count 0 2006.169.07:20:38.18#ibcon#wrote, iclass 32, count 0 2006.169.07:20:38.18#ibcon#about to read 3, iclass 32, count 0 2006.169.07:20:38.22#ibcon#read 3, iclass 32, count 0 2006.169.07:20:38.22#ibcon#about to read 4, iclass 32, count 0 2006.169.07:20:38.22#ibcon#read 4, iclass 32, count 0 2006.169.07:20:38.22#ibcon#about to read 5, iclass 32, count 0 2006.169.07:20:38.22#ibcon#read 5, iclass 32, count 0 2006.169.07:20:38.22#ibcon#about to read 6, iclass 32, count 0 2006.169.07:20:38.22#ibcon#read 6, iclass 32, count 0 2006.169.07:20:38.22#ibcon#end of sib2, iclass 32, count 0 2006.169.07:20:38.22#ibcon#*after write, iclass 32, count 0 2006.169.07:20:38.22#ibcon#*before return 0, iclass 32, count 0 2006.169.07:20:38.22#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:20:38.22#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:20:38.22#ibcon#about to clear, iclass 32 cls_cnt 0 2006.169.07:20:38.22#ibcon#cleared, iclass 32 cls_cnt 0 2006.169.07:20:38.22$vc4f8/va=2,7 2006.169.07:20:38.22#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.169.07:20:38.22#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.169.07:20:38.22#ibcon#ireg 11 cls_cnt 2 2006.169.07:20:38.22#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:20:38.27#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:20:38.27#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:20:38.27#ibcon#enter wrdev, iclass 35, count 2 2006.169.07:20:38.27#ibcon#first serial, iclass 35, count 2 2006.169.07:20:38.27#ibcon#enter sib2, iclass 35, count 2 2006.169.07:20:38.27#ibcon#flushed, iclass 35, count 2 2006.169.07:20:38.27#ibcon#about to write, iclass 35, count 2 2006.169.07:20:38.27#ibcon#wrote, iclass 35, count 2 2006.169.07:20:38.27#ibcon#about to read 3, iclass 35, count 2 2006.169.07:20:38.29#ibcon#read 3, iclass 35, count 2 2006.169.07:20:38.29#ibcon#about to read 4, iclass 35, count 2 2006.169.07:20:38.29#ibcon#read 4, iclass 35, count 2 2006.169.07:20:38.29#ibcon#about to read 5, iclass 35, count 2 2006.169.07:20:38.29#ibcon#read 5, iclass 35, count 2 2006.169.07:20:38.29#ibcon#about to read 6, iclass 35, count 2 2006.169.07:20:38.29#ibcon#read 6, iclass 35, count 2 2006.169.07:20:38.29#ibcon#end of sib2, iclass 35, count 2 2006.169.07:20:38.29#ibcon#*mode == 0, iclass 35, count 2 2006.169.07:20:38.29#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.169.07:20:38.29#ibcon#[25=AT02-07\r\n] 2006.169.07:20:38.29#ibcon#*before write, iclass 35, count 2 2006.169.07:20:38.29#ibcon#enter sib2, iclass 35, count 2 2006.169.07:20:38.29#ibcon#flushed, iclass 35, count 2 2006.169.07:20:38.29#ibcon#about to write, iclass 35, count 2 2006.169.07:20:38.29#ibcon#wrote, iclass 35, count 2 2006.169.07:20:38.29#ibcon#about to read 3, iclass 35, count 2 2006.169.07:20:38.32#ibcon#read 3, iclass 35, count 2 2006.169.07:20:38.32#ibcon#about to read 4, iclass 35, count 2 2006.169.07:20:38.32#ibcon#read 4, iclass 35, count 2 2006.169.07:20:38.32#ibcon#about to read 5, iclass 35, count 2 2006.169.07:20:38.32#ibcon#read 5, iclass 35, count 2 2006.169.07:20:38.32#ibcon#about to read 6, iclass 35, count 2 2006.169.07:20:38.32#ibcon#read 6, iclass 35, count 2 2006.169.07:20:38.32#ibcon#end of sib2, iclass 35, count 2 2006.169.07:20:38.32#ibcon#*after write, iclass 35, count 2 2006.169.07:20:38.32#ibcon#*before return 0, iclass 35, count 2 2006.169.07:20:38.32#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:20:38.32#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:20:38.32#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.169.07:20:38.32#ibcon#ireg 7 cls_cnt 0 2006.169.07:20:38.32#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:20:38.44#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:20:38.44#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:20:38.44#ibcon#enter wrdev, iclass 35, count 0 2006.169.07:20:38.44#ibcon#first serial, iclass 35, count 0 2006.169.07:20:38.44#ibcon#enter sib2, iclass 35, count 0 2006.169.07:20:38.44#ibcon#flushed, iclass 35, count 0 2006.169.07:20:38.44#ibcon#about to write, iclass 35, count 0 2006.169.07:20:38.44#ibcon#wrote, iclass 35, count 0 2006.169.07:20:38.44#ibcon#about to read 3, iclass 35, count 0 2006.169.07:20:38.46#ibcon#read 3, iclass 35, count 0 2006.169.07:20:38.46#ibcon#about to read 4, iclass 35, count 0 2006.169.07:20:38.46#ibcon#read 4, iclass 35, count 0 2006.169.07:20:38.46#ibcon#about to read 5, iclass 35, count 0 2006.169.07:20:38.46#ibcon#read 5, iclass 35, count 0 2006.169.07:20:38.46#ibcon#about to read 6, iclass 35, count 0 2006.169.07:20:38.46#ibcon#read 6, iclass 35, count 0 2006.169.07:20:38.46#ibcon#end of sib2, iclass 35, count 0 2006.169.07:20:38.46#ibcon#*mode == 0, iclass 35, count 0 2006.169.07:20:38.46#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.169.07:20:38.46#ibcon#[25=USB\r\n] 2006.169.07:20:38.46#ibcon#*before write, iclass 35, count 0 2006.169.07:20:38.46#ibcon#enter sib2, iclass 35, count 0 2006.169.07:20:38.46#ibcon#flushed, iclass 35, count 0 2006.169.07:20:38.46#ibcon#about to write, iclass 35, count 0 2006.169.07:20:38.46#ibcon#wrote, iclass 35, count 0 2006.169.07:20:38.46#ibcon#about to read 3, iclass 35, count 0 2006.169.07:20:38.49#ibcon#read 3, iclass 35, count 0 2006.169.07:20:38.49#ibcon#about to read 4, iclass 35, count 0 2006.169.07:20:38.49#ibcon#read 4, iclass 35, count 0 2006.169.07:20:38.49#ibcon#about to read 5, iclass 35, count 0 2006.169.07:20:38.49#ibcon#read 5, iclass 35, count 0 2006.169.07:20:38.49#ibcon#about to read 6, iclass 35, count 0 2006.169.07:20:38.49#ibcon#read 6, iclass 35, count 0 2006.169.07:20:38.49#ibcon#end of sib2, iclass 35, count 0 2006.169.07:20:38.49#ibcon#*after write, iclass 35, count 0 2006.169.07:20:38.49#ibcon#*before return 0, iclass 35, count 0 2006.169.07:20:38.49#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:20:38.49#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:20:38.49#ibcon#about to clear, iclass 35 cls_cnt 0 2006.169.07:20:38.49#ibcon#cleared, iclass 35 cls_cnt 0 2006.169.07:20:38.49$vc4f8/valo=3,672.99 2006.169.07:20:38.49#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.169.07:20:38.49#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.169.07:20:38.49#ibcon#ireg 17 cls_cnt 0 2006.169.07:20:38.49#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:20:38.49#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:20:38.49#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:20:38.49#ibcon#enter wrdev, iclass 37, count 0 2006.169.07:20:38.49#ibcon#first serial, iclass 37, count 0 2006.169.07:20:38.49#ibcon#enter sib2, iclass 37, count 0 2006.169.07:20:38.49#ibcon#flushed, iclass 37, count 0 2006.169.07:20:38.49#ibcon#about to write, iclass 37, count 0 2006.169.07:20:38.49#ibcon#wrote, iclass 37, count 0 2006.169.07:20:38.49#ibcon#about to read 3, iclass 37, count 0 2006.169.07:20:38.51#ibcon#read 3, iclass 37, count 0 2006.169.07:20:38.51#ibcon#about to read 4, iclass 37, count 0 2006.169.07:20:38.51#ibcon#read 4, iclass 37, count 0 2006.169.07:20:38.51#ibcon#about to read 5, iclass 37, count 0 2006.169.07:20:38.51#ibcon#read 5, iclass 37, count 0 2006.169.07:20:38.51#ibcon#about to read 6, iclass 37, count 0 2006.169.07:20:38.51#ibcon#read 6, iclass 37, count 0 2006.169.07:20:38.51#ibcon#end of sib2, iclass 37, count 0 2006.169.07:20:38.51#ibcon#*mode == 0, iclass 37, count 0 2006.169.07:20:38.51#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.169.07:20:38.51#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.07:20:38.51#ibcon#*before write, iclass 37, count 0 2006.169.07:20:38.51#ibcon#enter sib2, iclass 37, count 0 2006.169.07:20:38.51#ibcon#flushed, iclass 37, count 0 2006.169.07:20:38.51#ibcon#about to write, iclass 37, count 0 2006.169.07:20:38.51#ibcon#wrote, iclass 37, count 0 2006.169.07:20:38.51#ibcon#about to read 3, iclass 37, count 0 2006.169.07:20:38.55#ibcon#read 3, iclass 37, count 0 2006.169.07:20:38.55#ibcon#about to read 4, iclass 37, count 0 2006.169.07:20:38.55#ibcon#read 4, iclass 37, count 0 2006.169.07:20:38.55#ibcon#about to read 5, iclass 37, count 0 2006.169.07:20:38.55#ibcon#read 5, iclass 37, count 0 2006.169.07:20:38.55#ibcon#about to read 6, iclass 37, count 0 2006.169.07:20:38.55#ibcon#read 6, iclass 37, count 0 2006.169.07:20:38.55#ibcon#end of sib2, iclass 37, count 0 2006.169.07:20:38.55#ibcon#*after write, iclass 37, count 0 2006.169.07:20:38.55#ibcon#*before return 0, iclass 37, count 0 2006.169.07:20:38.55#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:20:38.55#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:20:38.55#ibcon#about to clear, iclass 37 cls_cnt 0 2006.169.07:20:38.55#ibcon#cleared, iclass 37 cls_cnt 0 2006.169.07:20:38.55$vc4f8/va=3,6 2006.169.07:20:38.55#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.169.07:20:38.55#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.169.07:20:38.55#ibcon#ireg 11 cls_cnt 2 2006.169.07:20:38.55#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:20:38.61#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:20:38.61#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:20:38.61#ibcon#enter wrdev, iclass 39, count 2 2006.169.07:20:38.61#ibcon#first serial, iclass 39, count 2 2006.169.07:20:38.61#ibcon#enter sib2, iclass 39, count 2 2006.169.07:20:38.61#ibcon#flushed, iclass 39, count 2 2006.169.07:20:38.61#ibcon#about to write, iclass 39, count 2 2006.169.07:20:38.61#ibcon#wrote, iclass 39, count 2 2006.169.07:20:38.61#ibcon#about to read 3, iclass 39, count 2 2006.169.07:20:38.64#ibcon#read 3, iclass 39, count 2 2006.169.07:20:38.64#ibcon#about to read 4, iclass 39, count 2 2006.169.07:20:38.64#ibcon#read 4, iclass 39, count 2 2006.169.07:20:38.64#ibcon#about to read 5, iclass 39, count 2 2006.169.07:20:38.64#ibcon#read 5, iclass 39, count 2 2006.169.07:20:38.64#ibcon#about to read 6, iclass 39, count 2 2006.169.07:20:38.64#ibcon#read 6, iclass 39, count 2 2006.169.07:20:38.64#ibcon#end of sib2, iclass 39, count 2 2006.169.07:20:38.64#ibcon#*mode == 0, iclass 39, count 2 2006.169.07:20:38.64#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.169.07:20:38.64#ibcon#[25=AT03-06\r\n] 2006.169.07:20:38.64#ibcon#*before write, iclass 39, count 2 2006.169.07:20:38.64#ibcon#enter sib2, iclass 39, count 2 2006.169.07:20:38.64#ibcon#flushed, iclass 39, count 2 2006.169.07:20:38.64#ibcon#about to write, iclass 39, count 2 2006.169.07:20:38.64#ibcon#wrote, iclass 39, count 2 2006.169.07:20:38.64#ibcon#about to read 3, iclass 39, count 2 2006.169.07:20:38.67#ibcon#read 3, iclass 39, count 2 2006.169.07:20:38.67#ibcon#about to read 4, iclass 39, count 2 2006.169.07:20:38.67#ibcon#read 4, iclass 39, count 2 2006.169.07:20:38.67#ibcon#about to read 5, iclass 39, count 2 2006.169.07:20:38.67#ibcon#read 5, iclass 39, count 2 2006.169.07:20:38.67#ibcon#about to read 6, iclass 39, count 2 2006.169.07:20:38.67#ibcon#read 6, iclass 39, count 2 2006.169.07:20:38.67#ibcon#end of sib2, iclass 39, count 2 2006.169.07:20:38.67#ibcon#*after write, iclass 39, count 2 2006.169.07:20:38.67#ibcon#*before return 0, iclass 39, count 2 2006.169.07:20:38.67#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:20:38.67#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:20:38.67#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.169.07:20:38.67#ibcon#ireg 7 cls_cnt 0 2006.169.07:20:38.67#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:20:38.79#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:20:38.79#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:20:38.79#ibcon#enter wrdev, iclass 39, count 0 2006.169.07:20:38.79#ibcon#first serial, iclass 39, count 0 2006.169.07:20:38.79#ibcon#enter sib2, iclass 39, count 0 2006.169.07:20:38.79#ibcon#flushed, iclass 39, count 0 2006.169.07:20:38.79#ibcon#about to write, iclass 39, count 0 2006.169.07:20:38.79#ibcon#wrote, iclass 39, count 0 2006.169.07:20:38.79#ibcon#about to read 3, iclass 39, count 0 2006.169.07:20:38.81#ibcon#read 3, iclass 39, count 0 2006.169.07:20:38.81#ibcon#about to read 4, iclass 39, count 0 2006.169.07:20:38.81#ibcon#read 4, iclass 39, count 0 2006.169.07:20:38.81#ibcon#about to read 5, iclass 39, count 0 2006.169.07:20:38.81#ibcon#read 5, iclass 39, count 0 2006.169.07:20:38.81#ibcon#about to read 6, iclass 39, count 0 2006.169.07:20:38.81#ibcon#read 6, iclass 39, count 0 2006.169.07:20:38.81#ibcon#end of sib2, iclass 39, count 0 2006.169.07:20:38.81#ibcon#*mode == 0, iclass 39, count 0 2006.169.07:20:38.81#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.169.07:20:38.81#ibcon#[25=USB\r\n] 2006.169.07:20:38.81#ibcon#*before write, iclass 39, count 0 2006.169.07:20:38.81#ibcon#enter sib2, iclass 39, count 0 2006.169.07:20:38.81#ibcon#flushed, iclass 39, count 0 2006.169.07:20:38.81#ibcon#about to write, iclass 39, count 0 2006.169.07:20:38.81#ibcon#wrote, iclass 39, count 0 2006.169.07:20:38.81#ibcon#about to read 3, iclass 39, count 0 2006.169.07:20:38.84#ibcon#read 3, iclass 39, count 0 2006.169.07:20:38.84#ibcon#about to read 4, iclass 39, count 0 2006.169.07:20:38.84#ibcon#read 4, iclass 39, count 0 2006.169.07:20:38.84#ibcon#about to read 5, iclass 39, count 0 2006.169.07:20:38.84#ibcon#read 5, iclass 39, count 0 2006.169.07:20:38.84#ibcon#about to read 6, iclass 39, count 0 2006.169.07:20:38.84#ibcon#read 6, iclass 39, count 0 2006.169.07:20:38.84#ibcon#end of sib2, iclass 39, count 0 2006.169.07:20:38.84#ibcon#*after write, iclass 39, count 0 2006.169.07:20:38.84#ibcon#*before return 0, iclass 39, count 0 2006.169.07:20:38.84#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:20:38.84#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:20:38.84#ibcon#about to clear, iclass 39 cls_cnt 0 2006.169.07:20:38.84#ibcon#cleared, iclass 39 cls_cnt 0 2006.169.07:20:38.84$vc4f8/valo=4,832.99 2006.169.07:20:38.84#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.169.07:20:38.84#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.169.07:20:38.84#ibcon#ireg 17 cls_cnt 0 2006.169.07:20:38.84#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:20:38.84#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:20:38.84#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:20:38.84#ibcon#enter wrdev, iclass 3, count 0 2006.169.07:20:38.84#ibcon#first serial, iclass 3, count 0 2006.169.07:20:38.84#ibcon#enter sib2, iclass 3, count 0 2006.169.07:20:38.84#ibcon#flushed, iclass 3, count 0 2006.169.07:20:38.84#ibcon#about to write, iclass 3, count 0 2006.169.07:20:38.84#ibcon#wrote, iclass 3, count 0 2006.169.07:20:38.84#ibcon#about to read 3, iclass 3, count 0 2006.169.07:20:38.86#ibcon#read 3, iclass 3, count 0 2006.169.07:20:38.86#ibcon#about to read 4, iclass 3, count 0 2006.169.07:20:38.86#ibcon#read 4, iclass 3, count 0 2006.169.07:20:38.86#ibcon#about to read 5, iclass 3, count 0 2006.169.07:20:38.86#ibcon#read 5, iclass 3, count 0 2006.169.07:20:38.86#ibcon#about to read 6, iclass 3, count 0 2006.169.07:20:38.86#ibcon#read 6, iclass 3, count 0 2006.169.07:20:38.86#ibcon#end of sib2, iclass 3, count 0 2006.169.07:20:38.86#ibcon#*mode == 0, iclass 3, count 0 2006.169.07:20:38.86#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.169.07:20:38.86#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.07:20:38.86#ibcon#*before write, iclass 3, count 0 2006.169.07:20:38.86#ibcon#enter sib2, iclass 3, count 0 2006.169.07:20:38.86#ibcon#flushed, iclass 3, count 0 2006.169.07:20:38.86#ibcon#about to write, iclass 3, count 0 2006.169.07:20:38.86#ibcon#wrote, iclass 3, count 0 2006.169.07:20:38.86#ibcon#about to read 3, iclass 3, count 0 2006.169.07:20:38.90#ibcon#read 3, iclass 3, count 0 2006.169.07:20:38.90#ibcon#about to read 4, iclass 3, count 0 2006.169.07:20:38.90#ibcon#read 4, iclass 3, count 0 2006.169.07:20:38.90#ibcon#about to read 5, iclass 3, count 0 2006.169.07:20:38.90#ibcon#read 5, iclass 3, count 0 2006.169.07:20:38.90#ibcon#about to read 6, iclass 3, count 0 2006.169.07:20:38.90#ibcon#read 6, iclass 3, count 0 2006.169.07:20:38.90#ibcon#end of sib2, iclass 3, count 0 2006.169.07:20:38.90#ibcon#*after write, iclass 3, count 0 2006.169.07:20:38.90#ibcon#*before return 0, iclass 3, count 0 2006.169.07:20:38.90#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:20:38.90#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:20:38.90#ibcon#about to clear, iclass 3 cls_cnt 0 2006.169.07:20:38.90#ibcon#cleared, iclass 3 cls_cnt 0 2006.169.07:20:38.90$vc4f8/va=4,7 2006.169.07:20:38.90#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.169.07:20:38.90#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.169.07:20:38.90#ibcon#ireg 11 cls_cnt 2 2006.169.07:20:38.90#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:20:38.96#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:20:38.96#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:20:38.96#ibcon#enter wrdev, iclass 5, count 2 2006.169.07:20:38.96#ibcon#first serial, iclass 5, count 2 2006.169.07:20:38.96#ibcon#enter sib2, iclass 5, count 2 2006.169.07:20:38.96#ibcon#flushed, iclass 5, count 2 2006.169.07:20:38.96#ibcon#about to write, iclass 5, count 2 2006.169.07:20:38.96#ibcon#wrote, iclass 5, count 2 2006.169.07:20:38.96#ibcon#about to read 3, iclass 5, count 2 2006.169.07:20:38.98#ibcon#read 3, iclass 5, count 2 2006.169.07:20:38.98#ibcon#about to read 4, iclass 5, count 2 2006.169.07:20:38.98#ibcon#read 4, iclass 5, count 2 2006.169.07:20:38.98#ibcon#about to read 5, iclass 5, count 2 2006.169.07:20:38.98#ibcon#read 5, iclass 5, count 2 2006.169.07:20:38.98#ibcon#about to read 6, iclass 5, count 2 2006.169.07:20:38.98#ibcon#read 6, iclass 5, count 2 2006.169.07:20:38.98#ibcon#end of sib2, iclass 5, count 2 2006.169.07:20:38.98#ibcon#*mode == 0, iclass 5, count 2 2006.169.07:20:38.98#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.169.07:20:38.98#ibcon#[25=AT04-07\r\n] 2006.169.07:20:38.98#ibcon#*before write, iclass 5, count 2 2006.169.07:20:38.98#ibcon#enter sib2, iclass 5, count 2 2006.169.07:20:38.98#ibcon#flushed, iclass 5, count 2 2006.169.07:20:38.98#ibcon#about to write, iclass 5, count 2 2006.169.07:20:38.98#ibcon#wrote, iclass 5, count 2 2006.169.07:20:38.98#ibcon#about to read 3, iclass 5, count 2 2006.169.07:20:39.01#ibcon#read 3, iclass 5, count 2 2006.169.07:20:39.01#ibcon#about to read 4, iclass 5, count 2 2006.169.07:20:39.01#ibcon#read 4, iclass 5, count 2 2006.169.07:20:39.01#ibcon#about to read 5, iclass 5, count 2 2006.169.07:20:39.01#ibcon#read 5, iclass 5, count 2 2006.169.07:20:39.01#ibcon#about to read 6, iclass 5, count 2 2006.169.07:20:39.01#ibcon#read 6, iclass 5, count 2 2006.169.07:20:39.01#ibcon#end of sib2, iclass 5, count 2 2006.169.07:20:39.01#ibcon#*after write, iclass 5, count 2 2006.169.07:20:39.01#ibcon#*before return 0, iclass 5, count 2 2006.169.07:20:39.01#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:20:39.01#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:20:39.01#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.169.07:20:39.01#ibcon#ireg 7 cls_cnt 0 2006.169.07:20:39.01#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:20:39.13#trakl#Source acquired 2006.169.07:20:39.13#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:20:39.13#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:20:39.13#ibcon#enter wrdev, iclass 5, count 0 2006.169.07:20:39.13#ibcon#first serial, iclass 5, count 0 2006.169.07:20:39.13#ibcon#enter sib2, iclass 5, count 0 2006.169.07:20:39.13#ibcon#flushed, iclass 5, count 0 2006.169.07:20:39.13#ibcon#about to write, iclass 5, count 0 2006.169.07:20:39.13#ibcon#wrote, iclass 5, count 0 2006.169.07:20:39.13#ibcon#about to read 3, iclass 5, count 0 2006.169.07:20:39.15#ibcon#read 3, iclass 5, count 0 2006.169.07:20:39.15#ibcon#about to read 4, iclass 5, count 0 2006.169.07:20:39.15#ibcon#read 4, iclass 5, count 0 2006.169.07:20:39.15#ibcon#about to read 5, iclass 5, count 0 2006.169.07:20:39.15#ibcon#read 5, iclass 5, count 0 2006.169.07:20:39.15#ibcon#about to read 6, iclass 5, count 0 2006.169.07:20:39.15#ibcon#read 6, iclass 5, count 0 2006.169.07:20:39.15#ibcon#end of sib2, iclass 5, count 0 2006.169.07:20:39.15#ibcon#*mode == 0, iclass 5, count 0 2006.169.07:20:39.15#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.169.07:20:39.15#ibcon#[25=USB\r\n] 2006.169.07:20:39.15#ibcon#*before write, iclass 5, count 0 2006.169.07:20:39.15#ibcon#enter sib2, iclass 5, count 0 2006.169.07:20:39.15#ibcon#flushed, iclass 5, count 0 2006.169.07:20:39.15#ibcon#about to write, iclass 5, count 0 2006.169.07:20:39.15#ibcon#wrote, iclass 5, count 0 2006.169.07:20:39.15#ibcon#about to read 3, iclass 5, count 0 2006.169.07:20:39.18#ibcon#read 3, iclass 5, count 0 2006.169.07:20:39.18#ibcon#about to read 4, iclass 5, count 0 2006.169.07:20:39.18#ibcon#read 4, iclass 5, count 0 2006.169.07:20:39.18#ibcon#about to read 5, iclass 5, count 0 2006.169.07:20:39.18#ibcon#read 5, iclass 5, count 0 2006.169.07:20:39.18#ibcon#about to read 6, iclass 5, count 0 2006.169.07:20:39.18#ibcon#read 6, iclass 5, count 0 2006.169.07:20:39.18#ibcon#end of sib2, iclass 5, count 0 2006.169.07:20:39.18#ibcon#*after write, iclass 5, count 0 2006.169.07:20:39.18#ibcon#*before return 0, iclass 5, count 0 2006.169.07:20:39.18#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:20:39.18#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:20:39.18#ibcon#about to clear, iclass 5 cls_cnt 0 2006.169.07:20:39.18#ibcon#cleared, iclass 5 cls_cnt 0 2006.169.07:20:39.18$vc4f8/valo=5,652.99 2006.169.07:20:39.18#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.169.07:20:39.18#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.169.07:20:39.18#ibcon#ireg 17 cls_cnt 0 2006.169.07:20:39.18#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:20:39.18#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:20:39.18#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:20:39.18#ibcon#enter wrdev, iclass 7, count 0 2006.169.07:20:39.18#ibcon#first serial, iclass 7, count 0 2006.169.07:20:39.18#ibcon#enter sib2, iclass 7, count 0 2006.169.07:20:39.18#ibcon#flushed, iclass 7, count 0 2006.169.07:20:39.18#ibcon#about to write, iclass 7, count 0 2006.169.07:20:39.18#ibcon#wrote, iclass 7, count 0 2006.169.07:20:39.18#ibcon#about to read 3, iclass 7, count 0 2006.169.07:20:39.20#ibcon#read 3, iclass 7, count 0 2006.169.07:20:39.20#ibcon#about to read 4, iclass 7, count 0 2006.169.07:20:39.20#ibcon#read 4, iclass 7, count 0 2006.169.07:20:39.20#ibcon#about to read 5, iclass 7, count 0 2006.169.07:20:39.20#ibcon#read 5, iclass 7, count 0 2006.169.07:20:39.20#ibcon#about to read 6, iclass 7, count 0 2006.169.07:20:39.20#ibcon#read 6, iclass 7, count 0 2006.169.07:20:39.20#ibcon#end of sib2, iclass 7, count 0 2006.169.07:20:39.20#ibcon#*mode == 0, iclass 7, count 0 2006.169.07:20:39.20#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.169.07:20:39.20#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.07:20:39.20#ibcon#*before write, iclass 7, count 0 2006.169.07:20:39.20#ibcon#enter sib2, iclass 7, count 0 2006.169.07:20:39.20#ibcon#flushed, iclass 7, count 0 2006.169.07:20:39.20#ibcon#about to write, iclass 7, count 0 2006.169.07:20:39.20#ibcon#wrote, iclass 7, count 0 2006.169.07:20:39.20#ibcon#about to read 3, iclass 7, count 0 2006.169.07:20:39.24#ibcon#read 3, iclass 7, count 0 2006.169.07:20:39.24#ibcon#about to read 4, iclass 7, count 0 2006.169.07:20:39.24#ibcon#read 4, iclass 7, count 0 2006.169.07:20:39.24#ibcon#about to read 5, iclass 7, count 0 2006.169.07:20:39.24#ibcon#read 5, iclass 7, count 0 2006.169.07:20:39.24#ibcon#about to read 6, iclass 7, count 0 2006.169.07:20:39.24#ibcon#read 6, iclass 7, count 0 2006.169.07:20:39.24#ibcon#end of sib2, iclass 7, count 0 2006.169.07:20:39.24#ibcon#*after write, iclass 7, count 0 2006.169.07:20:39.24#ibcon#*before return 0, iclass 7, count 0 2006.169.07:20:39.24#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:20:39.24#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:20:39.24#ibcon#about to clear, iclass 7 cls_cnt 0 2006.169.07:20:39.24#ibcon#cleared, iclass 7 cls_cnt 0 2006.169.07:20:39.24$vc4f8/va=5,7 2006.169.07:20:39.24#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.169.07:20:39.24#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.169.07:20:39.24#ibcon#ireg 11 cls_cnt 2 2006.169.07:20:39.24#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:20:39.30#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:20:39.30#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:20:39.30#ibcon#enter wrdev, iclass 11, count 2 2006.169.07:20:39.30#ibcon#first serial, iclass 11, count 2 2006.169.07:20:39.30#ibcon#enter sib2, iclass 11, count 2 2006.169.07:20:39.30#ibcon#flushed, iclass 11, count 2 2006.169.07:20:39.30#ibcon#about to write, iclass 11, count 2 2006.169.07:20:39.30#ibcon#wrote, iclass 11, count 2 2006.169.07:20:39.30#ibcon#about to read 3, iclass 11, count 2 2006.169.07:20:39.32#ibcon#read 3, iclass 11, count 2 2006.169.07:20:39.32#ibcon#about to read 4, iclass 11, count 2 2006.169.07:20:39.32#ibcon#read 4, iclass 11, count 2 2006.169.07:20:39.32#ibcon#about to read 5, iclass 11, count 2 2006.169.07:20:39.32#ibcon#read 5, iclass 11, count 2 2006.169.07:20:39.32#ibcon#about to read 6, iclass 11, count 2 2006.169.07:20:39.32#ibcon#read 6, iclass 11, count 2 2006.169.07:20:39.32#ibcon#end of sib2, iclass 11, count 2 2006.169.07:20:39.32#ibcon#*mode == 0, iclass 11, count 2 2006.169.07:20:39.32#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.169.07:20:39.32#ibcon#[25=AT05-07\r\n] 2006.169.07:20:39.32#ibcon#*before write, iclass 11, count 2 2006.169.07:20:39.32#ibcon#enter sib2, iclass 11, count 2 2006.169.07:20:39.32#ibcon#flushed, iclass 11, count 2 2006.169.07:20:39.32#ibcon#about to write, iclass 11, count 2 2006.169.07:20:39.32#ibcon#wrote, iclass 11, count 2 2006.169.07:20:39.32#ibcon#about to read 3, iclass 11, count 2 2006.169.07:20:39.35#ibcon#read 3, iclass 11, count 2 2006.169.07:20:39.35#ibcon#about to read 4, iclass 11, count 2 2006.169.07:20:39.35#ibcon#read 4, iclass 11, count 2 2006.169.07:20:39.35#ibcon#about to read 5, iclass 11, count 2 2006.169.07:20:39.35#ibcon#read 5, iclass 11, count 2 2006.169.07:20:39.35#ibcon#about to read 6, iclass 11, count 2 2006.169.07:20:39.35#ibcon#read 6, iclass 11, count 2 2006.169.07:20:39.35#ibcon#end of sib2, iclass 11, count 2 2006.169.07:20:39.35#ibcon#*after write, iclass 11, count 2 2006.169.07:20:39.35#ibcon#*before return 0, iclass 11, count 2 2006.169.07:20:39.35#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:20:39.35#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:20:39.35#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.169.07:20:39.35#ibcon#ireg 7 cls_cnt 0 2006.169.07:20:39.35#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:20:39.47#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:20:39.47#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:20:39.47#ibcon#enter wrdev, iclass 11, count 0 2006.169.07:20:39.47#ibcon#first serial, iclass 11, count 0 2006.169.07:20:39.47#ibcon#enter sib2, iclass 11, count 0 2006.169.07:20:39.47#ibcon#flushed, iclass 11, count 0 2006.169.07:20:39.47#ibcon#about to write, iclass 11, count 0 2006.169.07:20:39.47#ibcon#wrote, iclass 11, count 0 2006.169.07:20:39.47#ibcon#about to read 3, iclass 11, count 0 2006.169.07:20:39.49#ibcon#read 3, iclass 11, count 0 2006.169.07:20:39.49#ibcon#about to read 4, iclass 11, count 0 2006.169.07:20:39.49#ibcon#read 4, iclass 11, count 0 2006.169.07:20:39.49#ibcon#about to read 5, iclass 11, count 0 2006.169.07:20:39.49#ibcon#read 5, iclass 11, count 0 2006.169.07:20:39.49#ibcon#about to read 6, iclass 11, count 0 2006.169.07:20:39.49#ibcon#read 6, iclass 11, count 0 2006.169.07:20:39.49#ibcon#end of sib2, iclass 11, count 0 2006.169.07:20:39.49#ibcon#*mode == 0, iclass 11, count 0 2006.169.07:20:39.49#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.169.07:20:39.49#ibcon#[25=USB\r\n] 2006.169.07:20:39.49#ibcon#*before write, iclass 11, count 0 2006.169.07:20:39.49#ibcon#enter sib2, iclass 11, count 0 2006.169.07:20:39.49#ibcon#flushed, iclass 11, count 0 2006.169.07:20:39.49#ibcon#about to write, iclass 11, count 0 2006.169.07:20:39.49#ibcon#wrote, iclass 11, count 0 2006.169.07:20:39.49#ibcon#about to read 3, iclass 11, count 0 2006.169.07:20:39.52#ibcon#read 3, iclass 11, count 0 2006.169.07:20:39.52#ibcon#about to read 4, iclass 11, count 0 2006.169.07:20:39.52#ibcon#read 4, iclass 11, count 0 2006.169.07:20:39.52#ibcon#about to read 5, iclass 11, count 0 2006.169.07:20:39.52#ibcon#read 5, iclass 11, count 0 2006.169.07:20:39.52#ibcon#about to read 6, iclass 11, count 0 2006.169.07:20:39.52#ibcon#read 6, iclass 11, count 0 2006.169.07:20:39.52#ibcon#end of sib2, iclass 11, count 0 2006.169.07:20:39.52#ibcon#*after write, iclass 11, count 0 2006.169.07:20:39.52#ibcon#*before return 0, iclass 11, count 0 2006.169.07:20:39.52#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:20:39.52#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:20:39.52#ibcon#about to clear, iclass 11 cls_cnt 0 2006.169.07:20:39.52#ibcon#cleared, iclass 11 cls_cnt 0 2006.169.07:20:39.52$vc4f8/valo=6,772.99 2006.169.07:20:39.52#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.169.07:20:39.52#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.169.07:20:39.52#ibcon#ireg 17 cls_cnt 0 2006.169.07:20:39.52#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:20:39.52#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:20:39.52#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:20:39.52#ibcon#enter wrdev, iclass 13, count 0 2006.169.07:20:39.52#ibcon#first serial, iclass 13, count 0 2006.169.07:20:39.52#ibcon#enter sib2, iclass 13, count 0 2006.169.07:20:39.52#ibcon#flushed, iclass 13, count 0 2006.169.07:20:39.52#ibcon#about to write, iclass 13, count 0 2006.169.07:20:39.52#ibcon#wrote, iclass 13, count 0 2006.169.07:20:39.52#ibcon#about to read 3, iclass 13, count 0 2006.169.07:20:39.54#ibcon#read 3, iclass 13, count 0 2006.169.07:20:39.54#ibcon#about to read 4, iclass 13, count 0 2006.169.07:20:39.54#ibcon#read 4, iclass 13, count 0 2006.169.07:20:39.54#ibcon#about to read 5, iclass 13, count 0 2006.169.07:20:39.54#ibcon#read 5, iclass 13, count 0 2006.169.07:20:39.54#ibcon#about to read 6, iclass 13, count 0 2006.169.07:20:39.54#ibcon#read 6, iclass 13, count 0 2006.169.07:20:39.54#ibcon#end of sib2, iclass 13, count 0 2006.169.07:20:39.54#ibcon#*mode == 0, iclass 13, count 0 2006.169.07:20:39.54#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.07:20:39.54#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.07:20:39.54#ibcon#*before write, iclass 13, count 0 2006.169.07:20:39.54#ibcon#enter sib2, iclass 13, count 0 2006.169.07:20:39.54#ibcon#flushed, iclass 13, count 0 2006.169.07:20:39.54#ibcon#about to write, iclass 13, count 0 2006.169.07:20:39.54#ibcon#wrote, iclass 13, count 0 2006.169.07:20:39.54#ibcon#about to read 3, iclass 13, count 0 2006.169.07:20:39.58#ibcon#read 3, iclass 13, count 0 2006.169.07:20:39.58#ibcon#about to read 4, iclass 13, count 0 2006.169.07:20:39.58#ibcon#read 4, iclass 13, count 0 2006.169.07:20:39.58#ibcon#about to read 5, iclass 13, count 0 2006.169.07:20:39.58#ibcon#read 5, iclass 13, count 0 2006.169.07:20:39.58#ibcon#about to read 6, iclass 13, count 0 2006.169.07:20:39.58#ibcon#read 6, iclass 13, count 0 2006.169.07:20:39.58#ibcon#end of sib2, iclass 13, count 0 2006.169.07:20:39.58#ibcon#*after write, iclass 13, count 0 2006.169.07:20:39.58#ibcon#*before return 0, iclass 13, count 0 2006.169.07:20:39.58#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:20:39.58#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:20:39.58#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.07:20:39.58#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.07:20:39.58$vc4f8/va=6,6 2006.169.07:20:39.58#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.169.07:20:39.58#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.169.07:20:39.58#ibcon#ireg 11 cls_cnt 2 2006.169.07:20:39.58#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:20:39.64#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:20:39.64#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:20:39.64#ibcon#enter wrdev, iclass 15, count 2 2006.169.07:20:39.64#ibcon#first serial, iclass 15, count 2 2006.169.07:20:39.64#ibcon#enter sib2, iclass 15, count 2 2006.169.07:20:39.64#ibcon#flushed, iclass 15, count 2 2006.169.07:20:39.64#ibcon#about to write, iclass 15, count 2 2006.169.07:20:39.64#ibcon#wrote, iclass 15, count 2 2006.169.07:20:39.64#ibcon#about to read 3, iclass 15, count 2 2006.169.07:20:39.66#ibcon#read 3, iclass 15, count 2 2006.169.07:20:39.66#ibcon#about to read 4, iclass 15, count 2 2006.169.07:20:39.66#ibcon#read 4, iclass 15, count 2 2006.169.07:20:39.66#ibcon#about to read 5, iclass 15, count 2 2006.169.07:20:39.66#ibcon#read 5, iclass 15, count 2 2006.169.07:20:39.66#ibcon#about to read 6, iclass 15, count 2 2006.169.07:20:39.66#ibcon#read 6, iclass 15, count 2 2006.169.07:20:39.66#ibcon#end of sib2, iclass 15, count 2 2006.169.07:20:39.66#ibcon#*mode == 0, iclass 15, count 2 2006.169.07:20:39.66#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.169.07:20:39.66#ibcon#[25=AT06-06\r\n] 2006.169.07:20:39.66#ibcon#*before write, iclass 15, count 2 2006.169.07:20:39.66#ibcon#enter sib2, iclass 15, count 2 2006.169.07:20:39.66#ibcon#flushed, iclass 15, count 2 2006.169.07:20:39.66#ibcon#about to write, iclass 15, count 2 2006.169.07:20:39.66#ibcon#wrote, iclass 15, count 2 2006.169.07:20:39.66#ibcon#about to read 3, iclass 15, count 2 2006.169.07:20:39.69#ibcon#read 3, iclass 15, count 2 2006.169.07:20:39.69#ibcon#about to read 4, iclass 15, count 2 2006.169.07:20:39.69#ibcon#read 4, iclass 15, count 2 2006.169.07:20:39.69#ibcon#about to read 5, iclass 15, count 2 2006.169.07:20:39.69#ibcon#read 5, iclass 15, count 2 2006.169.07:20:39.69#ibcon#about to read 6, iclass 15, count 2 2006.169.07:20:39.69#ibcon#read 6, iclass 15, count 2 2006.169.07:20:39.69#ibcon#end of sib2, iclass 15, count 2 2006.169.07:20:39.69#ibcon#*after write, iclass 15, count 2 2006.169.07:20:39.69#ibcon#*before return 0, iclass 15, count 2 2006.169.07:20:39.69#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:20:39.69#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:20:39.69#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.169.07:20:39.69#ibcon#ireg 7 cls_cnt 0 2006.169.07:20:39.69#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:20:39.81#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:20:39.81#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:20:39.81#ibcon#enter wrdev, iclass 15, count 0 2006.169.07:20:39.81#ibcon#first serial, iclass 15, count 0 2006.169.07:20:39.81#ibcon#enter sib2, iclass 15, count 0 2006.169.07:20:39.81#ibcon#flushed, iclass 15, count 0 2006.169.07:20:39.81#ibcon#about to write, iclass 15, count 0 2006.169.07:20:39.81#ibcon#wrote, iclass 15, count 0 2006.169.07:20:39.81#ibcon#about to read 3, iclass 15, count 0 2006.169.07:20:39.83#ibcon#read 3, iclass 15, count 0 2006.169.07:20:39.83#ibcon#about to read 4, iclass 15, count 0 2006.169.07:20:39.83#ibcon#read 4, iclass 15, count 0 2006.169.07:20:39.83#ibcon#about to read 5, iclass 15, count 0 2006.169.07:20:39.83#ibcon#read 5, iclass 15, count 0 2006.169.07:20:39.83#ibcon#about to read 6, iclass 15, count 0 2006.169.07:20:39.83#ibcon#read 6, iclass 15, count 0 2006.169.07:20:39.83#ibcon#end of sib2, iclass 15, count 0 2006.169.07:20:39.83#ibcon#*mode == 0, iclass 15, count 0 2006.169.07:20:39.83#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.169.07:20:39.83#ibcon#[25=USB\r\n] 2006.169.07:20:39.83#ibcon#*before write, iclass 15, count 0 2006.169.07:20:39.83#ibcon#enter sib2, iclass 15, count 0 2006.169.07:20:39.83#ibcon#flushed, iclass 15, count 0 2006.169.07:20:39.83#ibcon#about to write, iclass 15, count 0 2006.169.07:20:39.83#ibcon#wrote, iclass 15, count 0 2006.169.07:20:39.83#ibcon#about to read 3, iclass 15, count 0 2006.169.07:20:39.86#ibcon#read 3, iclass 15, count 0 2006.169.07:20:39.86#ibcon#about to read 4, iclass 15, count 0 2006.169.07:20:39.86#ibcon#read 4, iclass 15, count 0 2006.169.07:20:39.86#ibcon#about to read 5, iclass 15, count 0 2006.169.07:20:39.86#ibcon#read 5, iclass 15, count 0 2006.169.07:20:39.86#ibcon#about to read 6, iclass 15, count 0 2006.169.07:20:39.86#ibcon#read 6, iclass 15, count 0 2006.169.07:20:39.86#ibcon#end of sib2, iclass 15, count 0 2006.169.07:20:39.86#ibcon#*after write, iclass 15, count 0 2006.169.07:20:39.86#ibcon#*before return 0, iclass 15, count 0 2006.169.07:20:39.86#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:20:39.86#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:20:39.86#ibcon#about to clear, iclass 15 cls_cnt 0 2006.169.07:20:39.86#ibcon#cleared, iclass 15 cls_cnt 0 2006.169.07:20:39.86$vc4f8/valo=7,832.99 2006.169.07:20:39.86#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.169.07:20:39.86#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.169.07:20:39.86#ibcon#ireg 17 cls_cnt 0 2006.169.07:20:39.86#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:20:39.86#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:20:39.86#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:20:39.86#ibcon#enter wrdev, iclass 17, count 0 2006.169.07:20:39.86#ibcon#first serial, iclass 17, count 0 2006.169.07:20:39.86#ibcon#enter sib2, iclass 17, count 0 2006.169.07:20:39.86#ibcon#flushed, iclass 17, count 0 2006.169.07:20:39.86#ibcon#about to write, iclass 17, count 0 2006.169.07:20:39.86#ibcon#wrote, iclass 17, count 0 2006.169.07:20:39.86#ibcon#about to read 3, iclass 17, count 0 2006.169.07:20:39.88#ibcon#read 3, iclass 17, count 0 2006.169.07:20:39.88#ibcon#about to read 4, iclass 17, count 0 2006.169.07:20:39.88#ibcon#read 4, iclass 17, count 0 2006.169.07:20:39.88#ibcon#about to read 5, iclass 17, count 0 2006.169.07:20:39.88#ibcon#read 5, iclass 17, count 0 2006.169.07:20:39.88#ibcon#about to read 6, iclass 17, count 0 2006.169.07:20:39.88#ibcon#read 6, iclass 17, count 0 2006.169.07:20:39.88#ibcon#end of sib2, iclass 17, count 0 2006.169.07:20:39.88#ibcon#*mode == 0, iclass 17, count 0 2006.169.07:20:39.88#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.169.07:20:39.88#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.07:20:39.88#ibcon#*before write, iclass 17, count 0 2006.169.07:20:39.88#ibcon#enter sib2, iclass 17, count 0 2006.169.07:20:39.88#ibcon#flushed, iclass 17, count 0 2006.169.07:20:39.88#ibcon#about to write, iclass 17, count 0 2006.169.07:20:39.88#ibcon#wrote, iclass 17, count 0 2006.169.07:20:39.88#ibcon#about to read 3, iclass 17, count 0 2006.169.07:20:39.92#ibcon#read 3, iclass 17, count 0 2006.169.07:20:39.92#ibcon#about to read 4, iclass 17, count 0 2006.169.07:20:39.92#ibcon#read 4, iclass 17, count 0 2006.169.07:20:39.92#ibcon#about to read 5, iclass 17, count 0 2006.169.07:20:39.92#ibcon#read 5, iclass 17, count 0 2006.169.07:20:39.92#ibcon#about to read 6, iclass 17, count 0 2006.169.07:20:39.92#ibcon#read 6, iclass 17, count 0 2006.169.07:20:39.92#ibcon#end of sib2, iclass 17, count 0 2006.169.07:20:39.92#ibcon#*after write, iclass 17, count 0 2006.169.07:20:39.92#ibcon#*before return 0, iclass 17, count 0 2006.169.07:20:39.92#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:20:39.92#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:20:39.92#ibcon#about to clear, iclass 17 cls_cnt 0 2006.169.07:20:39.92#ibcon#cleared, iclass 17 cls_cnt 0 2006.169.07:20:39.92$vc4f8/va=7,6 2006.169.07:20:39.92#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.169.07:20:39.92#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.169.07:20:39.92#ibcon#ireg 11 cls_cnt 2 2006.169.07:20:39.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:20:39.98#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:20:39.98#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:20:39.98#ibcon#enter wrdev, iclass 19, count 2 2006.169.07:20:39.98#ibcon#first serial, iclass 19, count 2 2006.169.07:20:39.98#ibcon#enter sib2, iclass 19, count 2 2006.169.07:20:39.98#ibcon#flushed, iclass 19, count 2 2006.169.07:20:39.98#ibcon#about to write, iclass 19, count 2 2006.169.07:20:39.98#ibcon#wrote, iclass 19, count 2 2006.169.07:20:39.98#ibcon#about to read 3, iclass 19, count 2 2006.169.07:20:40.00#ibcon#read 3, iclass 19, count 2 2006.169.07:20:40.00#ibcon#about to read 4, iclass 19, count 2 2006.169.07:20:40.00#ibcon#read 4, iclass 19, count 2 2006.169.07:20:40.00#ibcon#about to read 5, iclass 19, count 2 2006.169.07:20:40.00#ibcon#read 5, iclass 19, count 2 2006.169.07:20:40.00#ibcon#about to read 6, iclass 19, count 2 2006.169.07:20:40.00#ibcon#read 6, iclass 19, count 2 2006.169.07:20:40.00#ibcon#end of sib2, iclass 19, count 2 2006.169.07:20:40.00#ibcon#*mode == 0, iclass 19, count 2 2006.169.07:20:40.00#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.169.07:20:40.00#ibcon#[25=AT07-06\r\n] 2006.169.07:20:40.00#ibcon#*before write, iclass 19, count 2 2006.169.07:20:40.00#ibcon#enter sib2, iclass 19, count 2 2006.169.07:20:40.00#ibcon#flushed, iclass 19, count 2 2006.169.07:20:40.00#ibcon#about to write, iclass 19, count 2 2006.169.07:20:40.00#ibcon#wrote, iclass 19, count 2 2006.169.07:20:40.00#ibcon#about to read 3, iclass 19, count 2 2006.169.07:20:40.03#ibcon#read 3, iclass 19, count 2 2006.169.07:20:40.03#ibcon#about to read 4, iclass 19, count 2 2006.169.07:20:40.03#ibcon#read 4, iclass 19, count 2 2006.169.07:20:40.03#ibcon#about to read 5, iclass 19, count 2 2006.169.07:20:40.03#ibcon#read 5, iclass 19, count 2 2006.169.07:20:40.03#ibcon#about to read 6, iclass 19, count 2 2006.169.07:20:40.03#ibcon#read 6, iclass 19, count 2 2006.169.07:20:40.03#ibcon#end of sib2, iclass 19, count 2 2006.169.07:20:40.03#ibcon#*after write, iclass 19, count 2 2006.169.07:20:40.03#ibcon#*before return 0, iclass 19, count 2 2006.169.07:20:40.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:20:40.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:20:40.03#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.169.07:20:40.03#ibcon#ireg 7 cls_cnt 0 2006.169.07:20:40.03#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:20:40.15#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:20:40.15#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:20:40.15#ibcon#enter wrdev, iclass 19, count 0 2006.169.07:20:40.15#ibcon#first serial, iclass 19, count 0 2006.169.07:20:40.15#ibcon#enter sib2, iclass 19, count 0 2006.169.07:20:40.15#ibcon#flushed, iclass 19, count 0 2006.169.07:20:40.15#ibcon#about to write, iclass 19, count 0 2006.169.07:20:40.15#ibcon#wrote, iclass 19, count 0 2006.169.07:20:40.15#ibcon#about to read 3, iclass 19, count 0 2006.169.07:20:40.17#ibcon#read 3, iclass 19, count 0 2006.169.07:20:40.17#ibcon#about to read 4, iclass 19, count 0 2006.169.07:20:40.17#ibcon#read 4, iclass 19, count 0 2006.169.07:20:40.17#ibcon#about to read 5, iclass 19, count 0 2006.169.07:20:40.17#ibcon#read 5, iclass 19, count 0 2006.169.07:20:40.17#ibcon#about to read 6, iclass 19, count 0 2006.169.07:20:40.17#ibcon#read 6, iclass 19, count 0 2006.169.07:20:40.17#ibcon#end of sib2, iclass 19, count 0 2006.169.07:20:40.17#ibcon#*mode == 0, iclass 19, count 0 2006.169.07:20:40.17#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.169.07:20:40.17#ibcon#[25=USB\r\n] 2006.169.07:20:40.17#ibcon#*before write, iclass 19, count 0 2006.169.07:20:40.17#ibcon#enter sib2, iclass 19, count 0 2006.169.07:20:40.17#ibcon#flushed, iclass 19, count 0 2006.169.07:20:40.17#ibcon#about to write, iclass 19, count 0 2006.169.07:20:40.17#ibcon#wrote, iclass 19, count 0 2006.169.07:20:40.17#ibcon#about to read 3, iclass 19, count 0 2006.169.07:20:40.20#ibcon#read 3, iclass 19, count 0 2006.169.07:20:40.20#ibcon#about to read 4, iclass 19, count 0 2006.169.07:20:40.20#ibcon#read 4, iclass 19, count 0 2006.169.07:20:40.20#ibcon#about to read 5, iclass 19, count 0 2006.169.07:20:40.20#ibcon#read 5, iclass 19, count 0 2006.169.07:20:40.20#ibcon#about to read 6, iclass 19, count 0 2006.169.07:20:40.20#ibcon#read 6, iclass 19, count 0 2006.169.07:20:40.20#ibcon#end of sib2, iclass 19, count 0 2006.169.07:20:40.20#ibcon#*after write, iclass 19, count 0 2006.169.07:20:40.20#ibcon#*before return 0, iclass 19, count 0 2006.169.07:20:40.20#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:20:40.20#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:20:40.20#ibcon#about to clear, iclass 19 cls_cnt 0 2006.169.07:20:40.20#ibcon#cleared, iclass 19 cls_cnt 0 2006.169.07:20:40.20$vc4f8/valo=8,852.99 2006.169.07:20:40.20#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.169.07:20:40.20#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.169.07:20:40.20#ibcon#ireg 17 cls_cnt 0 2006.169.07:20:40.20#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:20:40.20#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:20:40.20#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:20:40.20#ibcon#enter wrdev, iclass 21, count 0 2006.169.07:20:40.20#ibcon#first serial, iclass 21, count 0 2006.169.07:20:40.20#ibcon#enter sib2, iclass 21, count 0 2006.169.07:20:40.20#ibcon#flushed, iclass 21, count 0 2006.169.07:20:40.20#ibcon#about to write, iclass 21, count 0 2006.169.07:20:40.20#ibcon#wrote, iclass 21, count 0 2006.169.07:20:40.20#ibcon#about to read 3, iclass 21, count 0 2006.169.07:20:40.22#ibcon#read 3, iclass 21, count 0 2006.169.07:20:40.22#ibcon#about to read 4, iclass 21, count 0 2006.169.07:20:40.22#ibcon#read 4, iclass 21, count 0 2006.169.07:20:40.22#ibcon#about to read 5, iclass 21, count 0 2006.169.07:20:40.22#ibcon#read 5, iclass 21, count 0 2006.169.07:20:40.22#ibcon#about to read 6, iclass 21, count 0 2006.169.07:20:40.22#ibcon#read 6, iclass 21, count 0 2006.169.07:20:40.22#ibcon#end of sib2, iclass 21, count 0 2006.169.07:20:40.22#ibcon#*mode == 0, iclass 21, count 0 2006.169.07:20:40.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.169.07:20:40.22#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.07:20:40.22#ibcon#*before write, iclass 21, count 0 2006.169.07:20:40.22#ibcon#enter sib2, iclass 21, count 0 2006.169.07:20:40.22#ibcon#flushed, iclass 21, count 0 2006.169.07:20:40.22#ibcon#about to write, iclass 21, count 0 2006.169.07:20:40.22#ibcon#wrote, iclass 21, count 0 2006.169.07:20:40.22#ibcon#about to read 3, iclass 21, count 0 2006.169.07:20:40.26#ibcon#read 3, iclass 21, count 0 2006.169.07:20:40.26#ibcon#about to read 4, iclass 21, count 0 2006.169.07:20:40.26#ibcon#read 4, iclass 21, count 0 2006.169.07:20:40.26#ibcon#about to read 5, iclass 21, count 0 2006.169.07:20:40.26#ibcon#read 5, iclass 21, count 0 2006.169.07:20:40.26#ibcon#about to read 6, iclass 21, count 0 2006.169.07:20:40.26#ibcon#read 6, iclass 21, count 0 2006.169.07:20:40.26#ibcon#end of sib2, iclass 21, count 0 2006.169.07:20:40.26#ibcon#*after write, iclass 21, count 0 2006.169.07:20:40.26#ibcon#*before return 0, iclass 21, count 0 2006.169.07:20:40.26#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:20:40.26#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:20:40.26#ibcon#about to clear, iclass 21 cls_cnt 0 2006.169.07:20:40.26#ibcon#cleared, iclass 21 cls_cnt 0 2006.169.07:20:40.26$vc4f8/va=8,7 2006.169.07:20:40.26#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.169.07:20:40.26#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.169.07:20:40.26#ibcon#ireg 11 cls_cnt 2 2006.169.07:20:40.26#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.169.07:20:40.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.169.07:20:40.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.169.07:20:40.32#ibcon#enter wrdev, iclass 23, count 2 2006.169.07:20:40.32#ibcon#first serial, iclass 23, count 2 2006.169.07:20:40.32#ibcon#enter sib2, iclass 23, count 2 2006.169.07:20:40.32#ibcon#flushed, iclass 23, count 2 2006.169.07:20:40.32#ibcon#about to write, iclass 23, count 2 2006.169.07:20:40.32#ibcon#wrote, iclass 23, count 2 2006.169.07:20:40.32#ibcon#about to read 3, iclass 23, count 2 2006.169.07:20:40.34#ibcon#read 3, iclass 23, count 2 2006.169.07:20:40.34#ibcon#about to read 4, iclass 23, count 2 2006.169.07:20:40.34#ibcon#read 4, iclass 23, count 2 2006.169.07:20:40.34#ibcon#about to read 5, iclass 23, count 2 2006.169.07:20:40.34#ibcon#read 5, iclass 23, count 2 2006.169.07:20:40.34#ibcon#about to read 6, iclass 23, count 2 2006.169.07:20:40.34#ibcon#read 6, iclass 23, count 2 2006.169.07:20:40.34#ibcon#end of sib2, iclass 23, count 2 2006.169.07:20:40.34#ibcon#*mode == 0, iclass 23, count 2 2006.169.07:20:40.34#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.169.07:20:40.34#ibcon#[25=AT08-07\r\n] 2006.169.07:20:40.34#ibcon#*before write, iclass 23, count 2 2006.169.07:20:40.34#ibcon#enter sib2, iclass 23, count 2 2006.169.07:20:40.34#ibcon#flushed, iclass 23, count 2 2006.169.07:20:40.34#ibcon#about to write, iclass 23, count 2 2006.169.07:20:40.34#ibcon#wrote, iclass 23, count 2 2006.169.07:20:40.34#ibcon#about to read 3, iclass 23, count 2 2006.169.07:20:40.37#ibcon#read 3, iclass 23, count 2 2006.169.07:20:40.37#ibcon#about to read 4, iclass 23, count 2 2006.169.07:20:40.37#ibcon#read 4, iclass 23, count 2 2006.169.07:20:40.37#ibcon#about to read 5, iclass 23, count 2 2006.169.07:20:40.37#ibcon#read 5, iclass 23, count 2 2006.169.07:20:40.37#ibcon#about to read 6, iclass 23, count 2 2006.169.07:20:40.37#ibcon#read 6, iclass 23, count 2 2006.169.07:20:40.37#ibcon#end of sib2, iclass 23, count 2 2006.169.07:20:40.37#ibcon#*after write, iclass 23, count 2 2006.169.07:20:40.37#ibcon#*before return 0, iclass 23, count 2 2006.169.07:20:40.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.169.07:20:40.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.169.07:20:40.37#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.169.07:20:40.37#ibcon#ireg 7 cls_cnt 0 2006.169.07:20:40.37#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.169.07:20:40.49#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.169.07:20:40.49#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.169.07:20:40.49#ibcon#enter wrdev, iclass 23, count 0 2006.169.07:20:40.49#ibcon#first serial, iclass 23, count 0 2006.169.07:20:40.49#ibcon#enter sib2, iclass 23, count 0 2006.169.07:20:40.49#ibcon#flushed, iclass 23, count 0 2006.169.07:20:40.49#ibcon#about to write, iclass 23, count 0 2006.169.07:20:40.49#ibcon#wrote, iclass 23, count 0 2006.169.07:20:40.49#ibcon#about to read 3, iclass 23, count 0 2006.169.07:20:40.51#ibcon#read 3, iclass 23, count 0 2006.169.07:20:40.51#ibcon#about to read 4, iclass 23, count 0 2006.169.07:20:40.51#ibcon#read 4, iclass 23, count 0 2006.169.07:20:40.51#ibcon#about to read 5, iclass 23, count 0 2006.169.07:20:40.51#ibcon#read 5, iclass 23, count 0 2006.169.07:20:40.51#ibcon#about to read 6, iclass 23, count 0 2006.169.07:20:40.51#ibcon#read 6, iclass 23, count 0 2006.169.07:20:40.51#ibcon#end of sib2, iclass 23, count 0 2006.169.07:20:40.51#ibcon#*mode == 0, iclass 23, count 0 2006.169.07:20:40.51#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.169.07:20:40.51#ibcon#[25=USB\r\n] 2006.169.07:20:40.51#ibcon#*before write, iclass 23, count 0 2006.169.07:20:40.51#ibcon#enter sib2, iclass 23, count 0 2006.169.07:20:40.51#ibcon#flushed, iclass 23, count 0 2006.169.07:20:40.51#ibcon#about to write, iclass 23, count 0 2006.169.07:20:40.51#ibcon#wrote, iclass 23, count 0 2006.169.07:20:40.51#ibcon#about to read 3, iclass 23, count 0 2006.169.07:20:40.54#ibcon#read 3, iclass 23, count 0 2006.169.07:20:40.54#ibcon#about to read 4, iclass 23, count 0 2006.169.07:20:40.54#ibcon#read 4, iclass 23, count 0 2006.169.07:20:40.54#ibcon#about to read 5, iclass 23, count 0 2006.169.07:20:40.54#ibcon#read 5, iclass 23, count 0 2006.169.07:20:40.54#ibcon#about to read 6, iclass 23, count 0 2006.169.07:20:40.54#ibcon#read 6, iclass 23, count 0 2006.169.07:20:40.54#ibcon#end of sib2, iclass 23, count 0 2006.169.07:20:40.54#ibcon#*after write, iclass 23, count 0 2006.169.07:20:40.54#ibcon#*before return 0, iclass 23, count 0 2006.169.07:20:40.54#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.169.07:20:40.54#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.169.07:20:40.54#ibcon#about to clear, iclass 23 cls_cnt 0 2006.169.07:20:40.54#ibcon#cleared, iclass 23 cls_cnt 0 2006.169.07:20:40.54$vc4f8/vblo=1,632.99 2006.169.07:20:40.54#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.169.07:20:40.54#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.169.07:20:40.54#ibcon#ireg 17 cls_cnt 0 2006.169.07:20:40.54#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:20:40.54#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:20:40.54#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:20:40.54#ibcon#enter wrdev, iclass 25, count 0 2006.169.07:20:40.54#ibcon#first serial, iclass 25, count 0 2006.169.07:20:40.54#ibcon#enter sib2, iclass 25, count 0 2006.169.07:20:40.54#ibcon#flushed, iclass 25, count 0 2006.169.07:20:40.54#ibcon#about to write, iclass 25, count 0 2006.169.07:20:40.54#ibcon#wrote, iclass 25, count 0 2006.169.07:20:40.54#ibcon#about to read 3, iclass 25, count 0 2006.169.07:20:40.56#ibcon#read 3, iclass 25, count 0 2006.169.07:20:40.56#ibcon#about to read 4, iclass 25, count 0 2006.169.07:20:40.56#ibcon#read 4, iclass 25, count 0 2006.169.07:20:40.56#ibcon#about to read 5, iclass 25, count 0 2006.169.07:20:40.56#ibcon#read 5, iclass 25, count 0 2006.169.07:20:40.56#ibcon#about to read 6, iclass 25, count 0 2006.169.07:20:40.56#ibcon#read 6, iclass 25, count 0 2006.169.07:20:40.56#ibcon#end of sib2, iclass 25, count 0 2006.169.07:20:40.56#ibcon#*mode == 0, iclass 25, count 0 2006.169.07:20:40.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.169.07:20:40.56#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.07:20:40.56#ibcon#*before write, iclass 25, count 0 2006.169.07:20:40.56#ibcon#enter sib2, iclass 25, count 0 2006.169.07:20:40.56#ibcon#flushed, iclass 25, count 0 2006.169.07:20:40.56#ibcon#about to write, iclass 25, count 0 2006.169.07:20:40.56#ibcon#wrote, iclass 25, count 0 2006.169.07:20:40.56#ibcon#about to read 3, iclass 25, count 0 2006.169.07:20:40.60#ibcon#read 3, iclass 25, count 0 2006.169.07:20:40.60#ibcon#about to read 4, iclass 25, count 0 2006.169.07:20:40.60#ibcon#read 4, iclass 25, count 0 2006.169.07:20:40.60#ibcon#about to read 5, iclass 25, count 0 2006.169.07:20:40.60#ibcon#read 5, iclass 25, count 0 2006.169.07:20:40.60#ibcon#about to read 6, iclass 25, count 0 2006.169.07:20:40.60#ibcon#read 6, iclass 25, count 0 2006.169.07:20:40.60#ibcon#end of sib2, iclass 25, count 0 2006.169.07:20:40.60#ibcon#*after write, iclass 25, count 0 2006.169.07:20:40.60#ibcon#*before return 0, iclass 25, count 0 2006.169.07:20:40.60#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:20:40.60#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:20:40.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.169.07:20:40.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.169.07:20:40.60$vc4f8/vb=1,4 2006.169.07:20:40.60#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.169.07:20:40.60#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.169.07:20:40.60#ibcon#ireg 11 cls_cnt 2 2006.169.07:20:40.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.169.07:20:40.60#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.169.07:20:40.60#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.169.07:20:40.60#ibcon#enter wrdev, iclass 27, count 2 2006.169.07:20:40.60#ibcon#first serial, iclass 27, count 2 2006.169.07:20:40.60#ibcon#enter sib2, iclass 27, count 2 2006.169.07:20:40.60#ibcon#flushed, iclass 27, count 2 2006.169.07:20:40.60#ibcon#about to write, iclass 27, count 2 2006.169.07:20:40.60#ibcon#wrote, iclass 27, count 2 2006.169.07:20:40.60#ibcon#about to read 3, iclass 27, count 2 2006.169.07:20:40.62#ibcon#read 3, iclass 27, count 2 2006.169.07:20:40.62#ibcon#about to read 4, iclass 27, count 2 2006.169.07:20:40.62#ibcon#read 4, iclass 27, count 2 2006.169.07:20:40.62#ibcon#about to read 5, iclass 27, count 2 2006.169.07:20:40.62#ibcon#read 5, iclass 27, count 2 2006.169.07:20:40.62#ibcon#about to read 6, iclass 27, count 2 2006.169.07:20:40.62#ibcon#read 6, iclass 27, count 2 2006.169.07:20:40.62#ibcon#end of sib2, iclass 27, count 2 2006.169.07:20:40.62#ibcon#*mode == 0, iclass 27, count 2 2006.169.07:20:40.62#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.169.07:20:40.62#ibcon#[27=AT01-04\r\n] 2006.169.07:20:40.62#ibcon#*before write, iclass 27, count 2 2006.169.07:20:40.62#ibcon#enter sib2, iclass 27, count 2 2006.169.07:20:40.62#ibcon#flushed, iclass 27, count 2 2006.169.07:20:40.62#ibcon#about to write, iclass 27, count 2 2006.169.07:20:40.62#ibcon#wrote, iclass 27, count 2 2006.169.07:20:40.62#ibcon#about to read 3, iclass 27, count 2 2006.169.07:20:40.65#ibcon#read 3, iclass 27, count 2 2006.169.07:20:40.65#ibcon#about to read 4, iclass 27, count 2 2006.169.07:20:40.65#ibcon#read 4, iclass 27, count 2 2006.169.07:20:40.65#ibcon#about to read 5, iclass 27, count 2 2006.169.07:20:40.65#ibcon#read 5, iclass 27, count 2 2006.169.07:20:40.65#ibcon#about to read 6, iclass 27, count 2 2006.169.07:20:40.65#ibcon#read 6, iclass 27, count 2 2006.169.07:20:40.65#ibcon#end of sib2, iclass 27, count 2 2006.169.07:20:40.65#ibcon#*after write, iclass 27, count 2 2006.169.07:20:40.65#ibcon#*before return 0, iclass 27, count 2 2006.169.07:20:40.65#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.169.07:20:40.65#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.169.07:20:40.65#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.169.07:20:40.65#ibcon#ireg 7 cls_cnt 0 2006.169.07:20:40.65#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.169.07:20:40.77#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.169.07:20:40.77#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.169.07:20:40.77#ibcon#enter wrdev, iclass 27, count 0 2006.169.07:20:40.77#ibcon#first serial, iclass 27, count 0 2006.169.07:20:40.77#ibcon#enter sib2, iclass 27, count 0 2006.169.07:20:40.77#ibcon#flushed, iclass 27, count 0 2006.169.07:20:40.77#ibcon#about to write, iclass 27, count 0 2006.169.07:20:40.77#ibcon#wrote, iclass 27, count 0 2006.169.07:20:40.77#ibcon#about to read 3, iclass 27, count 0 2006.169.07:20:40.79#ibcon#read 3, iclass 27, count 0 2006.169.07:20:40.79#ibcon#about to read 4, iclass 27, count 0 2006.169.07:20:40.79#ibcon#read 4, iclass 27, count 0 2006.169.07:20:40.79#ibcon#about to read 5, iclass 27, count 0 2006.169.07:20:40.79#ibcon#read 5, iclass 27, count 0 2006.169.07:20:40.79#ibcon#about to read 6, iclass 27, count 0 2006.169.07:20:40.79#ibcon#read 6, iclass 27, count 0 2006.169.07:20:40.79#ibcon#end of sib2, iclass 27, count 0 2006.169.07:20:40.79#ibcon#*mode == 0, iclass 27, count 0 2006.169.07:20:40.79#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.169.07:20:40.79#ibcon#[27=USB\r\n] 2006.169.07:20:40.79#ibcon#*before write, iclass 27, count 0 2006.169.07:20:40.79#ibcon#enter sib2, iclass 27, count 0 2006.169.07:20:40.79#ibcon#flushed, iclass 27, count 0 2006.169.07:20:40.79#ibcon#about to write, iclass 27, count 0 2006.169.07:20:40.79#ibcon#wrote, iclass 27, count 0 2006.169.07:20:40.79#ibcon#about to read 3, iclass 27, count 0 2006.169.07:20:40.82#ibcon#read 3, iclass 27, count 0 2006.169.07:20:40.82#ibcon#about to read 4, iclass 27, count 0 2006.169.07:20:40.82#ibcon#read 4, iclass 27, count 0 2006.169.07:20:40.82#ibcon#about to read 5, iclass 27, count 0 2006.169.07:20:40.82#ibcon#read 5, iclass 27, count 0 2006.169.07:20:40.82#ibcon#about to read 6, iclass 27, count 0 2006.169.07:20:40.82#ibcon#read 6, iclass 27, count 0 2006.169.07:20:40.82#ibcon#end of sib2, iclass 27, count 0 2006.169.07:20:40.82#ibcon#*after write, iclass 27, count 0 2006.169.07:20:40.82#ibcon#*before return 0, iclass 27, count 0 2006.169.07:20:40.82#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.169.07:20:40.82#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.169.07:20:40.82#ibcon#about to clear, iclass 27 cls_cnt 0 2006.169.07:20:40.82#ibcon#cleared, iclass 27 cls_cnt 0 2006.169.07:20:40.82$vc4f8/vblo=2,640.99 2006.169.07:20:40.82#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.169.07:20:40.82#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.169.07:20:40.82#ibcon#ireg 17 cls_cnt 0 2006.169.07:20:40.82#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.169.07:20:40.82#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.169.07:20:40.82#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.169.07:20:40.82#ibcon#enter wrdev, iclass 29, count 0 2006.169.07:20:40.82#ibcon#first serial, iclass 29, count 0 2006.169.07:20:40.82#ibcon#enter sib2, iclass 29, count 0 2006.169.07:20:40.82#ibcon#flushed, iclass 29, count 0 2006.169.07:20:40.82#ibcon#about to write, iclass 29, count 0 2006.169.07:20:40.82#ibcon#wrote, iclass 29, count 0 2006.169.07:20:40.82#ibcon#about to read 3, iclass 29, count 0 2006.169.07:20:40.84#ibcon#read 3, iclass 29, count 0 2006.169.07:20:40.84#ibcon#about to read 4, iclass 29, count 0 2006.169.07:20:40.84#ibcon#read 4, iclass 29, count 0 2006.169.07:20:40.84#ibcon#about to read 5, iclass 29, count 0 2006.169.07:20:40.84#ibcon#read 5, iclass 29, count 0 2006.169.07:20:40.84#ibcon#about to read 6, iclass 29, count 0 2006.169.07:20:40.84#ibcon#read 6, iclass 29, count 0 2006.169.07:20:40.84#ibcon#end of sib2, iclass 29, count 0 2006.169.07:20:40.84#ibcon#*mode == 0, iclass 29, count 0 2006.169.07:20:40.84#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.169.07:20:40.84#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.07:20:40.84#ibcon#*before write, iclass 29, count 0 2006.169.07:20:40.84#ibcon#enter sib2, iclass 29, count 0 2006.169.07:20:40.84#ibcon#flushed, iclass 29, count 0 2006.169.07:20:40.84#ibcon#about to write, iclass 29, count 0 2006.169.07:20:40.84#ibcon#wrote, iclass 29, count 0 2006.169.07:20:40.84#ibcon#about to read 3, iclass 29, count 0 2006.169.07:20:40.88#ibcon#read 3, iclass 29, count 0 2006.169.07:20:40.88#ibcon#about to read 4, iclass 29, count 0 2006.169.07:20:40.88#ibcon#read 4, iclass 29, count 0 2006.169.07:20:40.88#ibcon#about to read 5, iclass 29, count 0 2006.169.07:20:40.88#ibcon#read 5, iclass 29, count 0 2006.169.07:20:40.88#ibcon#about to read 6, iclass 29, count 0 2006.169.07:20:40.88#ibcon#read 6, iclass 29, count 0 2006.169.07:20:40.88#ibcon#end of sib2, iclass 29, count 0 2006.169.07:20:40.88#ibcon#*after write, iclass 29, count 0 2006.169.07:20:40.88#ibcon#*before return 0, iclass 29, count 0 2006.169.07:20:40.88#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.169.07:20:40.88#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.169.07:20:40.88#ibcon#about to clear, iclass 29 cls_cnt 0 2006.169.07:20:40.88#ibcon#cleared, iclass 29 cls_cnt 0 2006.169.07:20:40.88$vc4f8/vb=2,4 2006.169.07:20:40.88#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.169.07:20:40.88#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.169.07:20:40.88#ibcon#ireg 11 cls_cnt 2 2006.169.07:20:40.88#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.169.07:20:40.94#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.169.07:20:40.94#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.169.07:20:40.94#ibcon#enter wrdev, iclass 31, count 2 2006.169.07:20:40.94#ibcon#first serial, iclass 31, count 2 2006.169.07:20:40.94#ibcon#enter sib2, iclass 31, count 2 2006.169.07:20:40.94#ibcon#flushed, iclass 31, count 2 2006.169.07:20:40.94#ibcon#about to write, iclass 31, count 2 2006.169.07:20:40.94#ibcon#wrote, iclass 31, count 2 2006.169.07:20:40.94#ibcon#about to read 3, iclass 31, count 2 2006.169.07:20:40.96#ibcon#read 3, iclass 31, count 2 2006.169.07:20:40.96#ibcon#about to read 4, iclass 31, count 2 2006.169.07:20:40.96#ibcon#read 4, iclass 31, count 2 2006.169.07:20:40.96#ibcon#about to read 5, iclass 31, count 2 2006.169.07:20:40.96#ibcon#read 5, iclass 31, count 2 2006.169.07:20:40.96#ibcon#about to read 6, iclass 31, count 2 2006.169.07:20:40.96#ibcon#read 6, iclass 31, count 2 2006.169.07:20:40.96#ibcon#end of sib2, iclass 31, count 2 2006.169.07:20:40.96#ibcon#*mode == 0, iclass 31, count 2 2006.169.07:20:40.96#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.169.07:20:40.96#ibcon#[27=AT02-04\r\n] 2006.169.07:20:40.96#ibcon#*before write, iclass 31, count 2 2006.169.07:20:40.96#ibcon#enter sib2, iclass 31, count 2 2006.169.07:20:40.96#ibcon#flushed, iclass 31, count 2 2006.169.07:20:40.96#ibcon#about to write, iclass 31, count 2 2006.169.07:20:40.96#ibcon#wrote, iclass 31, count 2 2006.169.07:20:40.96#ibcon#about to read 3, iclass 31, count 2 2006.169.07:20:40.99#ibcon#read 3, iclass 31, count 2 2006.169.07:20:40.99#ibcon#about to read 4, iclass 31, count 2 2006.169.07:20:40.99#ibcon#read 4, iclass 31, count 2 2006.169.07:20:40.99#ibcon#about to read 5, iclass 31, count 2 2006.169.07:20:40.99#ibcon#read 5, iclass 31, count 2 2006.169.07:20:40.99#ibcon#about to read 6, iclass 31, count 2 2006.169.07:20:40.99#ibcon#read 6, iclass 31, count 2 2006.169.07:20:40.99#ibcon#end of sib2, iclass 31, count 2 2006.169.07:20:40.99#ibcon#*after write, iclass 31, count 2 2006.169.07:20:40.99#ibcon#*before return 0, iclass 31, count 2 2006.169.07:20:40.99#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.169.07:20:40.99#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.169.07:20:40.99#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.169.07:20:40.99#ibcon#ireg 7 cls_cnt 0 2006.169.07:20:40.99#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.169.07:20:41.11#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.169.07:20:41.11#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.169.07:20:41.11#ibcon#enter wrdev, iclass 31, count 0 2006.169.07:20:41.11#ibcon#first serial, iclass 31, count 0 2006.169.07:20:41.11#ibcon#enter sib2, iclass 31, count 0 2006.169.07:20:41.11#ibcon#flushed, iclass 31, count 0 2006.169.07:20:41.11#ibcon#about to write, iclass 31, count 0 2006.169.07:20:41.11#ibcon#wrote, iclass 31, count 0 2006.169.07:20:41.11#ibcon#about to read 3, iclass 31, count 0 2006.169.07:20:41.13#ibcon#read 3, iclass 31, count 0 2006.169.07:20:41.13#ibcon#about to read 4, iclass 31, count 0 2006.169.07:20:41.13#ibcon#read 4, iclass 31, count 0 2006.169.07:20:41.13#ibcon#about to read 5, iclass 31, count 0 2006.169.07:20:41.13#ibcon#read 5, iclass 31, count 0 2006.169.07:20:41.13#ibcon#about to read 6, iclass 31, count 0 2006.169.07:20:41.13#ibcon#read 6, iclass 31, count 0 2006.169.07:20:41.13#ibcon#end of sib2, iclass 31, count 0 2006.169.07:20:41.13#ibcon#*mode == 0, iclass 31, count 0 2006.169.07:20:41.13#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.169.07:20:41.13#ibcon#[27=USB\r\n] 2006.169.07:20:41.13#ibcon#*before write, iclass 31, count 0 2006.169.07:20:41.13#ibcon#enter sib2, iclass 31, count 0 2006.169.07:20:41.13#ibcon#flushed, iclass 31, count 0 2006.169.07:20:41.13#ibcon#about to write, iclass 31, count 0 2006.169.07:20:41.13#ibcon#wrote, iclass 31, count 0 2006.169.07:20:41.13#ibcon#about to read 3, iclass 31, count 0 2006.169.07:20:41.13#flagr#flagr/antenna,acquired 2006.169.07:20:41.16#ibcon#read 3, iclass 31, count 0 2006.169.07:20:41.16#ibcon#about to read 4, iclass 31, count 0 2006.169.07:20:41.16#ibcon#read 4, iclass 31, count 0 2006.169.07:20:41.16#ibcon#about to read 5, iclass 31, count 0 2006.169.07:20:41.16#ibcon#read 5, iclass 31, count 0 2006.169.07:20:41.16#ibcon#about to read 6, iclass 31, count 0 2006.169.07:20:41.16#ibcon#read 6, iclass 31, count 0 2006.169.07:20:41.16#ibcon#end of sib2, iclass 31, count 0 2006.169.07:20:41.16#ibcon#*after write, iclass 31, count 0 2006.169.07:20:41.16#ibcon#*before return 0, iclass 31, count 0 2006.169.07:20:41.16#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.169.07:20:41.16#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.169.07:20:41.16#ibcon#about to clear, iclass 31 cls_cnt 0 2006.169.07:20:41.16#ibcon#cleared, iclass 31 cls_cnt 0 2006.169.07:20:41.16$vc4f8/vblo=3,656.99 2006.169.07:20:41.16#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.169.07:20:41.16#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.169.07:20:41.16#ibcon#ireg 17 cls_cnt 0 2006.169.07:20:41.16#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:20:41.16#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:20:41.16#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:20:41.16#ibcon#enter wrdev, iclass 33, count 0 2006.169.07:20:41.16#ibcon#first serial, iclass 33, count 0 2006.169.07:20:41.16#ibcon#enter sib2, iclass 33, count 0 2006.169.07:20:41.16#ibcon#flushed, iclass 33, count 0 2006.169.07:20:41.16#ibcon#about to write, iclass 33, count 0 2006.169.07:20:41.16#ibcon#wrote, iclass 33, count 0 2006.169.07:20:41.16#ibcon#about to read 3, iclass 33, count 0 2006.169.07:20:41.19#ibcon#read 3, iclass 33, count 0 2006.169.07:20:41.19#ibcon#about to read 4, iclass 33, count 0 2006.169.07:20:41.19#ibcon#read 4, iclass 33, count 0 2006.169.07:20:41.19#ibcon#about to read 5, iclass 33, count 0 2006.169.07:20:41.19#ibcon#read 5, iclass 33, count 0 2006.169.07:20:41.19#ibcon#about to read 6, iclass 33, count 0 2006.169.07:20:41.19#ibcon#read 6, iclass 33, count 0 2006.169.07:20:41.19#ibcon#end of sib2, iclass 33, count 0 2006.169.07:20:41.19#ibcon#*mode == 0, iclass 33, count 0 2006.169.07:20:41.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.169.07:20:41.19#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.07:20:41.19#ibcon#*before write, iclass 33, count 0 2006.169.07:20:41.19#ibcon#enter sib2, iclass 33, count 0 2006.169.07:20:41.19#ibcon#flushed, iclass 33, count 0 2006.169.07:20:41.19#ibcon#about to write, iclass 33, count 0 2006.169.07:20:41.19#ibcon#wrote, iclass 33, count 0 2006.169.07:20:41.19#ibcon#about to read 3, iclass 33, count 0 2006.169.07:20:41.23#ibcon#read 3, iclass 33, count 0 2006.169.07:20:41.23#ibcon#about to read 4, iclass 33, count 0 2006.169.07:20:41.23#ibcon#read 4, iclass 33, count 0 2006.169.07:20:41.23#ibcon#about to read 5, iclass 33, count 0 2006.169.07:20:41.23#ibcon#read 5, iclass 33, count 0 2006.169.07:20:41.23#ibcon#about to read 6, iclass 33, count 0 2006.169.07:20:41.23#ibcon#read 6, iclass 33, count 0 2006.169.07:20:41.23#ibcon#end of sib2, iclass 33, count 0 2006.169.07:20:41.23#ibcon#*after write, iclass 33, count 0 2006.169.07:20:41.23#ibcon#*before return 0, iclass 33, count 0 2006.169.07:20:41.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:20:41.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:20:41.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.169.07:20:41.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.169.07:20:41.23$vc4f8/vb=3,4 2006.169.07:20:41.23#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.169.07:20:41.23#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.169.07:20:41.23#ibcon#ireg 11 cls_cnt 2 2006.169.07:20:41.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:20:41.28#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:20:41.28#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:20:41.28#ibcon#enter wrdev, iclass 35, count 2 2006.169.07:20:41.28#ibcon#first serial, iclass 35, count 2 2006.169.07:20:41.28#ibcon#enter sib2, iclass 35, count 2 2006.169.07:20:41.28#ibcon#flushed, iclass 35, count 2 2006.169.07:20:41.28#ibcon#about to write, iclass 35, count 2 2006.169.07:20:41.28#ibcon#wrote, iclass 35, count 2 2006.169.07:20:41.28#ibcon#about to read 3, iclass 35, count 2 2006.169.07:20:41.30#ibcon#read 3, iclass 35, count 2 2006.169.07:20:41.30#ibcon#about to read 4, iclass 35, count 2 2006.169.07:20:41.30#ibcon#read 4, iclass 35, count 2 2006.169.07:20:41.30#ibcon#about to read 5, iclass 35, count 2 2006.169.07:20:41.30#ibcon#read 5, iclass 35, count 2 2006.169.07:20:41.30#ibcon#about to read 6, iclass 35, count 2 2006.169.07:20:41.30#ibcon#read 6, iclass 35, count 2 2006.169.07:20:41.30#ibcon#end of sib2, iclass 35, count 2 2006.169.07:20:41.30#ibcon#*mode == 0, iclass 35, count 2 2006.169.07:20:41.30#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.169.07:20:41.30#ibcon#[27=AT03-04\r\n] 2006.169.07:20:41.30#ibcon#*before write, iclass 35, count 2 2006.169.07:20:41.30#ibcon#enter sib2, iclass 35, count 2 2006.169.07:20:41.30#ibcon#flushed, iclass 35, count 2 2006.169.07:20:41.30#ibcon#about to write, iclass 35, count 2 2006.169.07:20:41.30#ibcon#wrote, iclass 35, count 2 2006.169.07:20:41.30#ibcon#about to read 3, iclass 35, count 2 2006.169.07:20:41.33#ibcon#read 3, iclass 35, count 2 2006.169.07:20:41.33#ibcon#about to read 4, iclass 35, count 2 2006.169.07:20:41.33#ibcon#read 4, iclass 35, count 2 2006.169.07:20:41.33#ibcon#about to read 5, iclass 35, count 2 2006.169.07:20:41.33#ibcon#read 5, iclass 35, count 2 2006.169.07:20:41.33#ibcon#about to read 6, iclass 35, count 2 2006.169.07:20:41.33#ibcon#read 6, iclass 35, count 2 2006.169.07:20:41.33#ibcon#end of sib2, iclass 35, count 2 2006.169.07:20:41.33#ibcon#*after write, iclass 35, count 2 2006.169.07:20:41.33#ibcon#*before return 0, iclass 35, count 2 2006.169.07:20:41.33#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:20:41.33#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:20:41.33#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.169.07:20:41.33#ibcon#ireg 7 cls_cnt 0 2006.169.07:20:41.33#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:20:41.45#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:20:41.45#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:20:41.45#ibcon#enter wrdev, iclass 35, count 0 2006.169.07:20:41.45#ibcon#first serial, iclass 35, count 0 2006.169.07:20:41.45#ibcon#enter sib2, iclass 35, count 0 2006.169.07:20:41.45#ibcon#flushed, iclass 35, count 0 2006.169.07:20:41.45#ibcon#about to write, iclass 35, count 0 2006.169.07:20:41.45#ibcon#wrote, iclass 35, count 0 2006.169.07:20:41.45#ibcon#about to read 3, iclass 35, count 0 2006.169.07:20:41.47#ibcon#read 3, iclass 35, count 0 2006.169.07:20:41.47#ibcon#about to read 4, iclass 35, count 0 2006.169.07:20:41.47#ibcon#read 4, iclass 35, count 0 2006.169.07:20:41.47#ibcon#about to read 5, iclass 35, count 0 2006.169.07:20:41.47#ibcon#read 5, iclass 35, count 0 2006.169.07:20:41.47#ibcon#about to read 6, iclass 35, count 0 2006.169.07:20:41.47#ibcon#read 6, iclass 35, count 0 2006.169.07:20:41.47#ibcon#end of sib2, iclass 35, count 0 2006.169.07:20:41.47#ibcon#*mode == 0, iclass 35, count 0 2006.169.07:20:41.47#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.169.07:20:41.47#ibcon#[27=USB\r\n] 2006.169.07:20:41.47#ibcon#*before write, iclass 35, count 0 2006.169.07:20:41.47#ibcon#enter sib2, iclass 35, count 0 2006.169.07:20:41.47#ibcon#flushed, iclass 35, count 0 2006.169.07:20:41.47#ibcon#about to write, iclass 35, count 0 2006.169.07:20:41.47#ibcon#wrote, iclass 35, count 0 2006.169.07:20:41.47#ibcon#about to read 3, iclass 35, count 0 2006.169.07:20:41.50#ibcon#read 3, iclass 35, count 0 2006.169.07:20:41.50#ibcon#about to read 4, iclass 35, count 0 2006.169.07:20:41.50#ibcon#read 4, iclass 35, count 0 2006.169.07:20:41.50#ibcon#about to read 5, iclass 35, count 0 2006.169.07:20:41.50#ibcon#read 5, iclass 35, count 0 2006.169.07:20:41.50#ibcon#about to read 6, iclass 35, count 0 2006.169.07:20:41.50#ibcon#read 6, iclass 35, count 0 2006.169.07:20:41.50#ibcon#end of sib2, iclass 35, count 0 2006.169.07:20:41.50#ibcon#*after write, iclass 35, count 0 2006.169.07:20:41.50#ibcon#*before return 0, iclass 35, count 0 2006.169.07:20:41.50#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:20:41.50#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:20:41.50#ibcon#about to clear, iclass 35 cls_cnt 0 2006.169.07:20:41.50#ibcon#cleared, iclass 35 cls_cnt 0 2006.169.07:20:41.50$vc4f8/vblo=4,712.99 2006.169.07:20:41.50#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.169.07:20:41.50#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.169.07:20:41.50#ibcon#ireg 17 cls_cnt 0 2006.169.07:20:41.50#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:20:41.50#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:20:41.50#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:20:41.50#ibcon#enter wrdev, iclass 37, count 0 2006.169.07:20:41.50#ibcon#first serial, iclass 37, count 0 2006.169.07:20:41.50#ibcon#enter sib2, iclass 37, count 0 2006.169.07:20:41.50#ibcon#flushed, iclass 37, count 0 2006.169.07:20:41.50#ibcon#about to write, iclass 37, count 0 2006.169.07:20:41.50#ibcon#wrote, iclass 37, count 0 2006.169.07:20:41.50#ibcon#about to read 3, iclass 37, count 0 2006.169.07:20:41.52#ibcon#read 3, iclass 37, count 0 2006.169.07:20:41.52#ibcon#about to read 4, iclass 37, count 0 2006.169.07:20:41.52#ibcon#read 4, iclass 37, count 0 2006.169.07:20:41.52#ibcon#about to read 5, iclass 37, count 0 2006.169.07:20:41.52#ibcon#read 5, iclass 37, count 0 2006.169.07:20:41.52#ibcon#about to read 6, iclass 37, count 0 2006.169.07:20:41.52#ibcon#read 6, iclass 37, count 0 2006.169.07:20:41.52#ibcon#end of sib2, iclass 37, count 0 2006.169.07:20:41.52#ibcon#*mode == 0, iclass 37, count 0 2006.169.07:20:41.52#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.169.07:20:41.52#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.07:20:41.52#ibcon#*before write, iclass 37, count 0 2006.169.07:20:41.52#ibcon#enter sib2, iclass 37, count 0 2006.169.07:20:41.52#ibcon#flushed, iclass 37, count 0 2006.169.07:20:41.52#ibcon#about to write, iclass 37, count 0 2006.169.07:20:41.52#ibcon#wrote, iclass 37, count 0 2006.169.07:20:41.52#ibcon#about to read 3, iclass 37, count 0 2006.169.07:20:41.56#ibcon#read 3, iclass 37, count 0 2006.169.07:20:41.56#ibcon#about to read 4, iclass 37, count 0 2006.169.07:20:41.56#ibcon#read 4, iclass 37, count 0 2006.169.07:20:41.56#ibcon#about to read 5, iclass 37, count 0 2006.169.07:20:41.56#ibcon#read 5, iclass 37, count 0 2006.169.07:20:41.56#ibcon#about to read 6, iclass 37, count 0 2006.169.07:20:41.56#ibcon#read 6, iclass 37, count 0 2006.169.07:20:41.56#ibcon#end of sib2, iclass 37, count 0 2006.169.07:20:41.56#ibcon#*after write, iclass 37, count 0 2006.169.07:20:41.56#ibcon#*before return 0, iclass 37, count 0 2006.169.07:20:41.56#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:20:41.56#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:20:41.56#ibcon#about to clear, iclass 37 cls_cnt 0 2006.169.07:20:41.56#ibcon#cleared, iclass 37 cls_cnt 0 2006.169.07:20:41.56$vc4f8/vb=4,4 2006.169.07:20:41.56#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.169.07:20:41.56#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.169.07:20:41.56#ibcon#ireg 11 cls_cnt 2 2006.169.07:20:41.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:20:41.62#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:20:41.62#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:20:41.62#ibcon#enter wrdev, iclass 39, count 2 2006.169.07:20:41.62#ibcon#first serial, iclass 39, count 2 2006.169.07:20:41.62#ibcon#enter sib2, iclass 39, count 2 2006.169.07:20:41.62#ibcon#flushed, iclass 39, count 2 2006.169.07:20:41.62#ibcon#about to write, iclass 39, count 2 2006.169.07:20:41.62#ibcon#wrote, iclass 39, count 2 2006.169.07:20:41.62#ibcon#about to read 3, iclass 39, count 2 2006.169.07:20:41.64#ibcon#read 3, iclass 39, count 2 2006.169.07:20:41.64#ibcon#about to read 4, iclass 39, count 2 2006.169.07:20:41.64#ibcon#read 4, iclass 39, count 2 2006.169.07:20:41.64#ibcon#about to read 5, iclass 39, count 2 2006.169.07:20:41.64#ibcon#read 5, iclass 39, count 2 2006.169.07:20:41.64#ibcon#about to read 6, iclass 39, count 2 2006.169.07:20:41.64#ibcon#read 6, iclass 39, count 2 2006.169.07:20:41.64#ibcon#end of sib2, iclass 39, count 2 2006.169.07:20:41.64#ibcon#*mode == 0, iclass 39, count 2 2006.169.07:20:41.64#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.169.07:20:41.64#ibcon#[27=AT04-04\r\n] 2006.169.07:20:41.64#ibcon#*before write, iclass 39, count 2 2006.169.07:20:41.64#ibcon#enter sib2, iclass 39, count 2 2006.169.07:20:41.64#ibcon#flushed, iclass 39, count 2 2006.169.07:20:41.64#ibcon#about to write, iclass 39, count 2 2006.169.07:20:41.64#ibcon#wrote, iclass 39, count 2 2006.169.07:20:41.64#ibcon#about to read 3, iclass 39, count 2 2006.169.07:20:41.67#ibcon#read 3, iclass 39, count 2 2006.169.07:20:41.67#ibcon#about to read 4, iclass 39, count 2 2006.169.07:20:41.67#ibcon#read 4, iclass 39, count 2 2006.169.07:20:41.67#ibcon#about to read 5, iclass 39, count 2 2006.169.07:20:41.67#ibcon#read 5, iclass 39, count 2 2006.169.07:20:41.67#ibcon#about to read 6, iclass 39, count 2 2006.169.07:20:41.67#ibcon#read 6, iclass 39, count 2 2006.169.07:20:41.67#ibcon#end of sib2, iclass 39, count 2 2006.169.07:20:41.67#ibcon#*after write, iclass 39, count 2 2006.169.07:20:41.67#ibcon#*before return 0, iclass 39, count 2 2006.169.07:20:41.67#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:20:41.67#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:20:41.67#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.169.07:20:41.67#ibcon#ireg 7 cls_cnt 0 2006.169.07:20:41.67#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:20:41.79#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:20:41.79#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:20:41.79#ibcon#enter wrdev, iclass 39, count 0 2006.169.07:20:41.79#ibcon#first serial, iclass 39, count 0 2006.169.07:20:41.79#ibcon#enter sib2, iclass 39, count 0 2006.169.07:20:41.79#ibcon#flushed, iclass 39, count 0 2006.169.07:20:41.79#ibcon#about to write, iclass 39, count 0 2006.169.07:20:41.79#ibcon#wrote, iclass 39, count 0 2006.169.07:20:41.79#ibcon#about to read 3, iclass 39, count 0 2006.169.07:20:41.81#ibcon#read 3, iclass 39, count 0 2006.169.07:20:41.81#ibcon#about to read 4, iclass 39, count 0 2006.169.07:20:41.81#ibcon#read 4, iclass 39, count 0 2006.169.07:20:41.81#ibcon#about to read 5, iclass 39, count 0 2006.169.07:20:41.81#ibcon#read 5, iclass 39, count 0 2006.169.07:20:41.81#ibcon#about to read 6, iclass 39, count 0 2006.169.07:20:41.81#ibcon#read 6, iclass 39, count 0 2006.169.07:20:41.81#ibcon#end of sib2, iclass 39, count 0 2006.169.07:20:41.81#ibcon#*mode == 0, iclass 39, count 0 2006.169.07:20:41.81#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.169.07:20:41.81#ibcon#[27=USB\r\n] 2006.169.07:20:41.81#ibcon#*before write, iclass 39, count 0 2006.169.07:20:41.81#ibcon#enter sib2, iclass 39, count 0 2006.169.07:20:41.81#ibcon#flushed, iclass 39, count 0 2006.169.07:20:41.81#ibcon#about to write, iclass 39, count 0 2006.169.07:20:41.81#ibcon#wrote, iclass 39, count 0 2006.169.07:20:41.81#ibcon#about to read 3, iclass 39, count 0 2006.169.07:20:41.84#ibcon#read 3, iclass 39, count 0 2006.169.07:20:41.84#ibcon#about to read 4, iclass 39, count 0 2006.169.07:20:41.84#ibcon#read 4, iclass 39, count 0 2006.169.07:20:41.84#ibcon#about to read 5, iclass 39, count 0 2006.169.07:20:41.84#ibcon#read 5, iclass 39, count 0 2006.169.07:20:41.84#ibcon#about to read 6, iclass 39, count 0 2006.169.07:20:41.84#ibcon#read 6, iclass 39, count 0 2006.169.07:20:41.84#ibcon#end of sib2, iclass 39, count 0 2006.169.07:20:41.84#ibcon#*after write, iclass 39, count 0 2006.169.07:20:41.84#ibcon#*before return 0, iclass 39, count 0 2006.169.07:20:41.84#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:20:41.84#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:20:41.84#ibcon#about to clear, iclass 39 cls_cnt 0 2006.169.07:20:41.84#ibcon#cleared, iclass 39 cls_cnt 0 2006.169.07:20:41.84$vc4f8/vblo=5,744.99 2006.169.07:20:41.84#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.169.07:20:41.84#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.169.07:20:41.84#ibcon#ireg 17 cls_cnt 0 2006.169.07:20:41.84#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:20:41.84#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:20:41.84#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:20:41.84#ibcon#enter wrdev, iclass 3, count 0 2006.169.07:20:41.84#ibcon#first serial, iclass 3, count 0 2006.169.07:20:41.84#ibcon#enter sib2, iclass 3, count 0 2006.169.07:20:41.84#ibcon#flushed, iclass 3, count 0 2006.169.07:20:41.84#ibcon#about to write, iclass 3, count 0 2006.169.07:20:41.84#ibcon#wrote, iclass 3, count 0 2006.169.07:20:41.84#ibcon#about to read 3, iclass 3, count 0 2006.169.07:20:41.86#ibcon#read 3, iclass 3, count 0 2006.169.07:20:41.86#ibcon#about to read 4, iclass 3, count 0 2006.169.07:20:41.86#ibcon#read 4, iclass 3, count 0 2006.169.07:20:41.86#ibcon#about to read 5, iclass 3, count 0 2006.169.07:20:41.86#ibcon#read 5, iclass 3, count 0 2006.169.07:20:41.86#ibcon#about to read 6, iclass 3, count 0 2006.169.07:20:41.86#ibcon#read 6, iclass 3, count 0 2006.169.07:20:41.86#ibcon#end of sib2, iclass 3, count 0 2006.169.07:20:41.86#ibcon#*mode == 0, iclass 3, count 0 2006.169.07:20:41.86#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.169.07:20:41.86#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.07:20:41.86#ibcon#*before write, iclass 3, count 0 2006.169.07:20:41.86#ibcon#enter sib2, iclass 3, count 0 2006.169.07:20:41.86#ibcon#flushed, iclass 3, count 0 2006.169.07:20:41.86#ibcon#about to write, iclass 3, count 0 2006.169.07:20:41.86#ibcon#wrote, iclass 3, count 0 2006.169.07:20:41.86#ibcon#about to read 3, iclass 3, count 0 2006.169.07:20:41.90#ibcon#read 3, iclass 3, count 0 2006.169.07:20:41.90#ibcon#about to read 4, iclass 3, count 0 2006.169.07:20:41.90#ibcon#read 4, iclass 3, count 0 2006.169.07:20:41.90#ibcon#about to read 5, iclass 3, count 0 2006.169.07:20:41.90#ibcon#read 5, iclass 3, count 0 2006.169.07:20:41.90#ibcon#about to read 6, iclass 3, count 0 2006.169.07:20:41.90#ibcon#read 6, iclass 3, count 0 2006.169.07:20:41.90#ibcon#end of sib2, iclass 3, count 0 2006.169.07:20:41.90#ibcon#*after write, iclass 3, count 0 2006.169.07:20:41.90#ibcon#*before return 0, iclass 3, count 0 2006.169.07:20:41.90#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:20:41.90#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:20:41.90#ibcon#about to clear, iclass 3 cls_cnt 0 2006.169.07:20:41.90#ibcon#cleared, iclass 3 cls_cnt 0 2006.169.07:20:41.90$vc4f8/vb=5,4 2006.169.07:20:41.90#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.169.07:20:41.90#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.169.07:20:41.90#ibcon#ireg 11 cls_cnt 2 2006.169.07:20:41.90#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:20:41.96#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:20:41.96#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:20:41.96#ibcon#enter wrdev, iclass 5, count 2 2006.169.07:20:41.96#ibcon#first serial, iclass 5, count 2 2006.169.07:20:41.96#ibcon#enter sib2, iclass 5, count 2 2006.169.07:20:41.96#ibcon#flushed, iclass 5, count 2 2006.169.07:20:41.96#ibcon#about to write, iclass 5, count 2 2006.169.07:20:41.96#ibcon#wrote, iclass 5, count 2 2006.169.07:20:41.96#ibcon#about to read 3, iclass 5, count 2 2006.169.07:20:41.98#ibcon#read 3, iclass 5, count 2 2006.169.07:20:41.98#ibcon#about to read 4, iclass 5, count 2 2006.169.07:20:41.98#ibcon#read 4, iclass 5, count 2 2006.169.07:20:41.98#ibcon#about to read 5, iclass 5, count 2 2006.169.07:20:41.98#ibcon#read 5, iclass 5, count 2 2006.169.07:20:41.98#ibcon#about to read 6, iclass 5, count 2 2006.169.07:20:41.98#ibcon#read 6, iclass 5, count 2 2006.169.07:20:41.98#ibcon#end of sib2, iclass 5, count 2 2006.169.07:20:41.98#ibcon#*mode == 0, iclass 5, count 2 2006.169.07:20:41.98#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.169.07:20:41.98#ibcon#[27=AT05-04\r\n] 2006.169.07:20:41.98#ibcon#*before write, iclass 5, count 2 2006.169.07:20:41.98#ibcon#enter sib2, iclass 5, count 2 2006.169.07:20:41.98#ibcon#flushed, iclass 5, count 2 2006.169.07:20:41.98#ibcon#about to write, iclass 5, count 2 2006.169.07:20:41.98#ibcon#wrote, iclass 5, count 2 2006.169.07:20:41.98#ibcon#about to read 3, iclass 5, count 2 2006.169.07:20:42.01#ibcon#read 3, iclass 5, count 2 2006.169.07:20:42.01#ibcon#about to read 4, iclass 5, count 2 2006.169.07:20:42.01#ibcon#read 4, iclass 5, count 2 2006.169.07:20:42.01#ibcon#about to read 5, iclass 5, count 2 2006.169.07:20:42.01#ibcon#read 5, iclass 5, count 2 2006.169.07:20:42.01#ibcon#about to read 6, iclass 5, count 2 2006.169.07:20:42.01#ibcon#read 6, iclass 5, count 2 2006.169.07:20:42.01#ibcon#end of sib2, iclass 5, count 2 2006.169.07:20:42.01#ibcon#*after write, iclass 5, count 2 2006.169.07:20:42.01#ibcon#*before return 0, iclass 5, count 2 2006.169.07:20:42.01#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:20:42.01#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:20:42.01#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.169.07:20:42.01#ibcon#ireg 7 cls_cnt 0 2006.169.07:20:42.01#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:20:42.13#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:20:42.13#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:20:42.13#ibcon#enter wrdev, iclass 5, count 0 2006.169.07:20:42.13#ibcon#first serial, iclass 5, count 0 2006.169.07:20:42.13#ibcon#enter sib2, iclass 5, count 0 2006.169.07:20:42.13#ibcon#flushed, iclass 5, count 0 2006.169.07:20:42.13#ibcon#about to write, iclass 5, count 0 2006.169.07:20:42.13#ibcon#wrote, iclass 5, count 0 2006.169.07:20:42.13#ibcon#about to read 3, iclass 5, count 0 2006.169.07:20:42.15#ibcon#read 3, iclass 5, count 0 2006.169.07:20:42.15#ibcon#about to read 4, iclass 5, count 0 2006.169.07:20:42.15#ibcon#read 4, iclass 5, count 0 2006.169.07:20:42.15#ibcon#about to read 5, iclass 5, count 0 2006.169.07:20:42.15#ibcon#read 5, iclass 5, count 0 2006.169.07:20:42.15#ibcon#about to read 6, iclass 5, count 0 2006.169.07:20:42.15#ibcon#read 6, iclass 5, count 0 2006.169.07:20:42.15#ibcon#end of sib2, iclass 5, count 0 2006.169.07:20:42.15#ibcon#*mode == 0, iclass 5, count 0 2006.169.07:20:42.15#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.169.07:20:42.15#ibcon#[27=USB\r\n] 2006.169.07:20:42.15#ibcon#*before write, iclass 5, count 0 2006.169.07:20:42.15#ibcon#enter sib2, iclass 5, count 0 2006.169.07:20:42.15#ibcon#flushed, iclass 5, count 0 2006.169.07:20:42.15#ibcon#about to write, iclass 5, count 0 2006.169.07:20:42.15#ibcon#wrote, iclass 5, count 0 2006.169.07:20:42.15#ibcon#about to read 3, iclass 5, count 0 2006.169.07:20:42.18#ibcon#read 3, iclass 5, count 0 2006.169.07:20:42.18#ibcon#about to read 4, iclass 5, count 0 2006.169.07:20:42.18#ibcon#read 4, iclass 5, count 0 2006.169.07:20:42.18#ibcon#about to read 5, iclass 5, count 0 2006.169.07:20:42.18#ibcon#read 5, iclass 5, count 0 2006.169.07:20:42.18#ibcon#about to read 6, iclass 5, count 0 2006.169.07:20:42.18#ibcon#read 6, iclass 5, count 0 2006.169.07:20:42.18#ibcon#end of sib2, iclass 5, count 0 2006.169.07:20:42.18#ibcon#*after write, iclass 5, count 0 2006.169.07:20:42.18#ibcon#*before return 0, iclass 5, count 0 2006.169.07:20:42.18#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:20:42.18#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:20:42.18#ibcon#about to clear, iclass 5 cls_cnt 0 2006.169.07:20:42.18#ibcon#cleared, iclass 5 cls_cnt 0 2006.169.07:20:42.18$vc4f8/vblo=6,752.99 2006.169.07:20:42.18#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.169.07:20:42.18#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.169.07:20:42.18#ibcon#ireg 17 cls_cnt 0 2006.169.07:20:42.18#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:20:42.18#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:20:42.18#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:20:42.18#ibcon#enter wrdev, iclass 7, count 0 2006.169.07:20:42.18#ibcon#first serial, iclass 7, count 0 2006.169.07:20:42.18#ibcon#enter sib2, iclass 7, count 0 2006.169.07:20:42.18#ibcon#flushed, iclass 7, count 0 2006.169.07:20:42.18#ibcon#about to write, iclass 7, count 0 2006.169.07:20:42.18#ibcon#wrote, iclass 7, count 0 2006.169.07:20:42.18#ibcon#about to read 3, iclass 7, count 0 2006.169.07:20:42.20#ibcon#read 3, iclass 7, count 0 2006.169.07:20:42.20#ibcon#about to read 4, iclass 7, count 0 2006.169.07:20:42.20#ibcon#read 4, iclass 7, count 0 2006.169.07:20:42.20#ibcon#about to read 5, iclass 7, count 0 2006.169.07:20:42.20#ibcon#read 5, iclass 7, count 0 2006.169.07:20:42.20#ibcon#about to read 6, iclass 7, count 0 2006.169.07:20:42.20#ibcon#read 6, iclass 7, count 0 2006.169.07:20:42.20#ibcon#end of sib2, iclass 7, count 0 2006.169.07:20:42.20#ibcon#*mode == 0, iclass 7, count 0 2006.169.07:20:42.20#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.169.07:20:42.20#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.07:20:42.20#ibcon#*before write, iclass 7, count 0 2006.169.07:20:42.20#ibcon#enter sib2, iclass 7, count 0 2006.169.07:20:42.20#ibcon#flushed, iclass 7, count 0 2006.169.07:20:42.20#ibcon#about to write, iclass 7, count 0 2006.169.07:20:42.20#ibcon#wrote, iclass 7, count 0 2006.169.07:20:42.20#ibcon#about to read 3, iclass 7, count 0 2006.169.07:20:42.24#ibcon#read 3, iclass 7, count 0 2006.169.07:20:42.24#ibcon#about to read 4, iclass 7, count 0 2006.169.07:20:42.24#ibcon#read 4, iclass 7, count 0 2006.169.07:20:42.24#ibcon#about to read 5, iclass 7, count 0 2006.169.07:20:42.24#ibcon#read 5, iclass 7, count 0 2006.169.07:20:42.24#ibcon#about to read 6, iclass 7, count 0 2006.169.07:20:42.24#ibcon#read 6, iclass 7, count 0 2006.169.07:20:42.24#ibcon#end of sib2, iclass 7, count 0 2006.169.07:20:42.24#ibcon#*after write, iclass 7, count 0 2006.169.07:20:42.24#ibcon#*before return 0, iclass 7, count 0 2006.169.07:20:42.24#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:20:42.24#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:20:42.24#ibcon#about to clear, iclass 7 cls_cnt 0 2006.169.07:20:42.24#ibcon#cleared, iclass 7 cls_cnt 0 2006.169.07:20:42.24$vc4f8/vb=6,4 2006.169.07:20:42.24#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.169.07:20:42.24#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.169.07:20:42.24#ibcon#ireg 11 cls_cnt 2 2006.169.07:20:42.24#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:20:42.30#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:20:42.30#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:20:42.30#ibcon#enter wrdev, iclass 11, count 2 2006.169.07:20:42.30#ibcon#first serial, iclass 11, count 2 2006.169.07:20:42.30#ibcon#enter sib2, iclass 11, count 2 2006.169.07:20:42.30#ibcon#flushed, iclass 11, count 2 2006.169.07:20:42.30#ibcon#about to write, iclass 11, count 2 2006.169.07:20:42.30#ibcon#wrote, iclass 11, count 2 2006.169.07:20:42.30#ibcon#about to read 3, iclass 11, count 2 2006.169.07:20:42.32#ibcon#read 3, iclass 11, count 2 2006.169.07:20:42.32#ibcon#about to read 4, iclass 11, count 2 2006.169.07:20:42.32#ibcon#read 4, iclass 11, count 2 2006.169.07:20:42.32#ibcon#about to read 5, iclass 11, count 2 2006.169.07:20:42.32#ibcon#read 5, iclass 11, count 2 2006.169.07:20:42.32#ibcon#about to read 6, iclass 11, count 2 2006.169.07:20:42.32#ibcon#read 6, iclass 11, count 2 2006.169.07:20:42.32#ibcon#end of sib2, iclass 11, count 2 2006.169.07:20:42.32#ibcon#*mode == 0, iclass 11, count 2 2006.169.07:20:42.32#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.169.07:20:42.32#ibcon#[27=AT06-04\r\n] 2006.169.07:20:42.32#ibcon#*before write, iclass 11, count 2 2006.169.07:20:42.32#ibcon#enter sib2, iclass 11, count 2 2006.169.07:20:42.32#ibcon#flushed, iclass 11, count 2 2006.169.07:20:42.32#ibcon#about to write, iclass 11, count 2 2006.169.07:20:42.32#ibcon#wrote, iclass 11, count 2 2006.169.07:20:42.32#ibcon#about to read 3, iclass 11, count 2 2006.169.07:20:42.35#ibcon#read 3, iclass 11, count 2 2006.169.07:20:42.35#ibcon#about to read 4, iclass 11, count 2 2006.169.07:20:42.35#ibcon#read 4, iclass 11, count 2 2006.169.07:20:42.35#ibcon#about to read 5, iclass 11, count 2 2006.169.07:20:42.35#ibcon#read 5, iclass 11, count 2 2006.169.07:20:42.35#ibcon#about to read 6, iclass 11, count 2 2006.169.07:20:42.35#ibcon#read 6, iclass 11, count 2 2006.169.07:20:42.35#ibcon#end of sib2, iclass 11, count 2 2006.169.07:20:42.35#ibcon#*after write, iclass 11, count 2 2006.169.07:20:42.35#ibcon#*before return 0, iclass 11, count 2 2006.169.07:20:42.35#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:20:42.35#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:20:42.35#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.169.07:20:42.35#ibcon#ireg 7 cls_cnt 0 2006.169.07:20:42.35#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:20:42.47#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:20:42.47#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:20:42.47#ibcon#enter wrdev, iclass 11, count 0 2006.169.07:20:42.47#ibcon#first serial, iclass 11, count 0 2006.169.07:20:42.47#ibcon#enter sib2, iclass 11, count 0 2006.169.07:20:42.47#ibcon#flushed, iclass 11, count 0 2006.169.07:20:42.47#ibcon#about to write, iclass 11, count 0 2006.169.07:20:42.47#ibcon#wrote, iclass 11, count 0 2006.169.07:20:42.47#ibcon#about to read 3, iclass 11, count 0 2006.169.07:20:42.49#ibcon#read 3, iclass 11, count 0 2006.169.07:20:42.49#ibcon#about to read 4, iclass 11, count 0 2006.169.07:20:42.49#ibcon#read 4, iclass 11, count 0 2006.169.07:20:42.49#ibcon#about to read 5, iclass 11, count 0 2006.169.07:20:42.49#ibcon#read 5, iclass 11, count 0 2006.169.07:20:42.49#ibcon#about to read 6, iclass 11, count 0 2006.169.07:20:42.49#ibcon#read 6, iclass 11, count 0 2006.169.07:20:42.49#ibcon#end of sib2, iclass 11, count 0 2006.169.07:20:42.49#ibcon#*mode == 0, iclass 11, count 0 2006.169.07:20:42.49#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.169.07:20:42.49#ibcon#[27=USB\r\n] 2006.169.07:20:42.49#ibcon#*before write, iclass 11, count 0 2006.169.07:20:42.49#ibcon#enter sib2, iclass 11, count 0 2006.169.07:20:42.49#ibcon#flushed, iclass 11, count 0 2006.169.07:20:42.49#ibcon#about to write, iclass 11, count 0 2006.169.07:20:42.49#ibcon#wrote, iclass 11, count 0 2006.169.07:20:42.49#ibcon#about to read 3, iclass 11, count 0 2006.169.07:20:42.52#ibcon#read 3, iclass 11, count 0 2006.169.07:20:42.52#ibcon#about to read 4, iclass 11, count 0 2006.169.07:20:42.52#ibcon#read 4, iclass 11, count 0 2006.169.07:20:42.52#ibcon#about to read 5, iclass 11, count 0 2006.169.07:20:42.52#ibcon#read 5, iclass 11, count 0 2006.169.07:20:42.52#ibcon#about to read 6, iclass 11, count 0 2006.169.07:20:42.52#ibcon#read 6, iclass 11, count 0 2006.169.07:20:42.52#ibcon#end of sib2, iclass 11, count 0 2006.169.07:20:42.52#ibcon#*after write, iclass 11, count 0 2006.169.07:20:42.52#ibcon#*before return 0, iclass 11, count 0 2006.169.07:20:42.52#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:20:42.52#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:20:42.52#ibcon#about to clear, iclass 11 cls_cnt 0 2006.169.07:20:42.52#ibcon#cleared, iclass 11 cls_cnt 0 2006.169.07:20:42.52$vc4f8/vabw=wide 2006.169.07:20:42.52#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.169.07:20:42.52#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.169.07:20:42.52#ibcon#ireg 8 cls_cnt 0 2006.169.07:20:42.52#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:20:42.52#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:20:42.52#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:20:42.52#ibcon#enter wrdev, iclass 13, count 0 2006.169.07:20:42.52#ibcon#first serial, iclass 13, count 0 2006.169.07:20:42.52#ibcon#enter sib2, iclass 13, count 0 2006.169.07:20:42.52#ibcon#flushed, iclass 13, count 0 2006.169.07:20:42.52#ibcon#about to write, iclass 13, count 0 2006.169.07:20:42.52#ibcon#wrote, iclass 13, count 0 2006.169.07:20:42.52#ibcon#about to read 3, iclass 13, count 0 2006.169.07:20:42.54#ibcon#read 3, iclass 13, count 0 2006.169.07:20:42.54#ibcon#about to read 4, iclass 13, count 0 2006.169.07:20:42.54#ibcon#read 4, iclass 13, count 0 2006.169.07:20:42.54#ibcon#about to read 5, iclass 13, count 0 2006.169.07:20:42.54#ibcon#read 5, iclass 13, count 0 2006.169.07:20:42.54#ibcon#about to read 6, iclass 13, count 0 2006.169.07:20:42.54#ibcon#read 6, iclass 13, count 0 2006.169.07:20:42.54#ibcon#end of sib2, iclass 13, count 0 2006.169.07:20:42.54#ibcon#*mode == 0, iclass 13, count 0 2006.169.07:20:42.54#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.07:20:42.54#ibcon#[25=BW32\r\n] 2006.169.07:20:42.54#ibcon#*before write, iclass 13, count 0 2006.169.07:20:42.54#ibcon#enter sib2, iclass 13, count 0 2006.169.07:20:42.54#ibcon#flushed, iclass 13, count 0 2006.169.07:20:42.54#ibcon#about to write, iclass 13, count 0 2006.169.07:20:42.54#ibcon#wrote, iclass 13, count 0 2006.169.07:20:42.54#ibcon#about to read 3, iclass 13, count 0 2006.169.07:20:42.57#ibcon#read 3, iclass 13, count 0 2006.169.07:20:42.57#ibcon#about to read 4, iclass 13, count 0 2006.169.07:20:42.57#ibcon#read 4, iclass 13, count 0 2006.169.07:20:42.57#ibcon#about to read 5, iclass 13, count 0 2006.169.07:20:42.57#ibcon#read 5, iclass 13, count 0 2006.169.07:20:42.57#ibcon#about to read 6, iclass 13, count 0 2006.169.07:20:42.57#ibcon#read 6, iclass 13, count 0 2006.169.07:20:42.57#ibcon#end of sib2, iclass 13, count 0 2006.169.07:20:42.57#ibcon#*after write, iclass 13, count 0 2006.169.07:20:42.57#ibcon#*before return 0, iclass 13, count 0 2006.169.07:20:42.57#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:20:42.57#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:20:42.57#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.07:20:42.57#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.07:20:42.57$vc4f8/vbbw=wide 2006.169.07:20:42.57#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.169.07:20:42.57#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.169.07:20:42.57#ibcon#ireg 8 cls_cnt 0 2006.169.07:20:42.57#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:20:42.64#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:20:42.64#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:20:42.64#ibcon#enter wrdev, iclass 15, count 0 2006.169.07:20:42.64#ibcon#first serial, iclass 15, count 0 2006.169.07:20:42.64#ibcon#enter sib2, iclass 15, count 0 2006.169.07:20:42.64#ibcon#flushed, iclass 15, count 0 2006.169.07:20:42.64#ibcon#about to write, iclass 15, count 0 2006.169.07:20:42.64#ibcon#wrote, iclass 15, count 0 2006.169.07:20:42.64#ibcon#about to read 3, iclass 15, count 0 2006.169.07:20:42.66#ibcon#read 3, iclass 15, count 0 2006.169.07:20:42.66#ibcon#about to read 4, iclass 15, count 0 2006.169.07:20:42.66#ibcon#read 4, iclass 15, count 0 2006.169.07:20:42.66#ibcon#about to read 5, iclass 15, count 0 2006.169.07:20:42.66#ibcon#read 5, iclass 15, count 0 2006.169.07:20:42.66#ibcon#about to read 6, iclass 15, count 0 2006.169.07:20:42.66#ibcon#read 6, iclass 15, count 0 2006.169.07:20:42.66#ibcon#end of sib2, iclass 15, count 0 2006.169.07:20:42.66#ibcon#*mode == 0, iclass 15, count 0 2006.169.07:20:42.66#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.169.07:20:42.66#ibcon#[27=BW32\r\n] 2006.169.07:20:42.66#ibcon#*before write, iclass 15, count 0 2006.169.07:20:42.66#ibcon#enter sib2, iclass 15, count 0 2006.169.07:20:42.66#ibcon#flushed, iclass 15, count 0 2006.169.07:20:42.66#ibcon#about to write, iclass 15, count 0 2006.169.07:20:42.66#ibcon#wrote, iclass 15, count 0 2006.169.07:20:42.66#ibcon#about to read 3, iclass 15, count 0 2006.169.07:20:42.69#ibcon#read 3, iclass 15, count 0 2006.169.07:20:42.69#ibcon#about to read 4, iclass 15, count 0 2006.169.07:20:42.69#ibcon#read 4, iclass 15, count 0 2006.169.07:20:42.69#ibcon#about to read 5, iclass 15, count 0 2006.169.07:20:42.69#ibcon#read 5, iclass 15, count 0 2006.169.07:20:42.69#ibcon#about to read 6, iclass 15, count 0 2006.169.07:20:42.69#ibcon#read 6, iclass 15, count 0 2006.169.07:20:42.69#ibcon#end of sib2, iclass 15, count 0 2006.169.07:20:42.69#ibcon#*after write, iclass 15, count 0 2006.169.07:20:42.69#ibcon#*before return 0, iclass 15, count 0 2006.169.07:20:42.69#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:20:42.69#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:20:42.69#ibcon#about to clear, iclass 15 cls_cnt 0 2006.169.07:20:42.69#ibcon#cleared, iclass 15 cls_cnt 0 2006.169.07:20:42.69$4f8m12a/ifd4f 2006.169.07:20:42.69&ifd4f/lo= 2006.169.07:20:42.69&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.07:20:42.69&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.07:20:42.69&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.07:20:42.69&ifd4f/patch= 2006.169.07:20:42.69&ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.07:20:42.69&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.07:20:42.69&ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.07:20:42.69$ifd4f/lo= 2006.169.07:20:42.69$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.07:20:42.69$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.07:20:42.69$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.07:20:42.69$ifd4f/patch= 2006.169.07:20:42.69$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.07:20:42.69$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.07:20:42.69$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.07:20:42.69$4f8m12a/"form=m,16.000,1:2 2006.169.07:20:42.69$4f8m12a/"tpicd 2006.169.07:20:42.69$4f8m12a/echo=off 2006.169.07:20:42.69$4f8m12a/xlog=off 2006.169.07:20:42.69:!2006.169.07:29:50 2006.169.07:29:50.00:preob 2006.169.07:29:50.00&preob/onsource 2006.169.07:29:51.13/onsource/TRACKING 2006.169.07:29:51.13:!2006.169.07:30:00 2006.169.07:30:00.00:data_valid=on 2006.169.07:30:00.00:midob 2006.169.07:30:00.00&midob/onsource 2006.169.07:30:00.00&midob/wx 2006.169.07:30:00.00&midob/cable 2006.169.07:30:00.00&midob/va 2006.169.07:30:00.00&midob/valo 2006.169.07:30:00.00&midob/vb 2006.169.07:30:00.00&midob/vblo 2006.169.07:30:00.00&midob/vabw 2006.169.07:30:00.00&midob/vbbw 2006.169.07:30:00.00&midob/"form 2006.169.07:30:00.00&midob/xfe 2006.169.07:30:00.00&midob/ifatt 2006.169.07:30:00.00&midob/clockoff 2006.169.07:30:00.00&midob/sy=logmail 2006.169.07:30:00.00&midob/"sy=run setcl adapt & 2006.169.07:30:00.13/onsource/TRACKING 2006.169.07:30:00.13/wx/18.21,1003.8,100 2006.169.07:30:00.24/cable/+6.5241E-03 2006.169.07:30:01.33/va/01,08,usb,yes,51,53 2006.169.07:30:01.33/va/02,07,usb,yes,51,53 2006.169.07:30:01.33/va/03,06,usb,yes,54,55 2006.169.07:30:01.33/va/04,07,usb,yes,53,56 2006.169.07:30:01.33/va/05,07,usb,yes,58,61 2006.169.07:30:01.33/va/06,06,usb,yes,57,57 2006.169.07:30:01.33/va/07,06,usb,yes,58,57 2006.169.07:30:01.33/va/08,07,usb,yes,55,54 2006.169.07:30:01.56/valo/01,532.99,yes,locked 2006.169.07:30:01.56/valo/02,572.99,yes,locked 2006.169.07:30:01.56/valo/03,672.99,yes,locked 2006.169.07:30:01.56/valo/04,832.99,yes,locked 2006.169.07:30:01.56/valo/05,652.99,yes,locked 2006.169.07:30:01.56/valo/06,772.99,yes,locked 2006.169.07:30:01.56/valo/07,832.99,yes,locked 2006.169.07:30:01.56/valo/08,852.99,yes,locked 2006.169.07:30:02.65/vb/01,04,usb,yes,31,30 2006.169.07:30:02.65/vb/02,04,usb,yes,33,35 2006.169.07:30:02.65/vb/03,04,usb,yes,29,33 2006.169.07:30:02.65/vb/04,04,usb,yes,30,31 2006.169.07:30:02.65/vb/05,04,usb,yes,29,33 2006.169.07:30:02.65/vb/06,04,usb,yes,30,33 2006.169.07:30:02.65/vb/07,04,usb,yes,32,32 2006.169.07:30:02.65/vb/08,04,usb,yes,29,33 2006.169.07:30:02.88/vblo/01,632.99,yes,locked 2006.169.07:30:02.88/vblo/02,640.99,yes,locked 2006.169.07:30:02.88/vblo/03,656.99,yes,locked 2006.169.07:30:02.88/vblo/04,712.99,yes,locked 2006.169.07:30:02.88/vblo/05,744.99,yes,locked 2006.169.07:30:02.88/vblo/06,752.99,yes,locked 2006.169.07:30:02.88/vblo/07,734.99,yes,locked 2006.169.07:30:02.88/vblo/08,744.99,yes,locked 2006.169.07:30:03.03/vabw/8 2006.169.07:30:03.18/vbbw/8 2006.169.07:30:03.28/xfe/off,on,15.2 2006.169.07:30:03.72/ifatt/23,28,28,28 2006.169.07:30:03.72&clockoff/"gps-fmout=1p 2006.169.07:30:03.72&clockoff/fmout-gps=1p 2006.169.07:30:04.08/fmout-gps/S +4.16E-07 2006.169.07:30:04.16:!2006.169.07:31:00 2006.169.07:31:00.00:data_valid=off 2006.169.07:31:00.00:postob 2006.169.07:31:00.00&postob/cable 2006.169.07:31:00.01&postob/wx 2006.169.07:31:00.01&postob/clockoff 2006.169.07:31:00.16/cable/+6.5243E-03 2006.169.07:31:00.16/wx/18.21,1003.8,100 2006.169.07:31:01.08/fmout-gps/S +4.16E-07 2006.169.07:31:01.08:scan_name=169-0733,k06169,60 2006.169.07:31:01.08:source=0748+126,075052.05,123104.8,2000.0,ccw 2006.169.07:31:01.14#flagr#flagr/antenna,new-source 2006.169.07:31:02.14:checkk5 2006.169.07:31:02.14&checkk5/chk_autoobs=1 2006.169.07:31:02.15&checkk5/chk_autoobs=2 2006.169.07:31:02.15&checkk5/chk_autoobs=3 2006.169.07:31:02.15&checkk5/chk_autoobs=4 2006.169.07:31:02.16&checkk5/chk_obsdata=1 2006.169.07:31:02.16&checkk5/chk_obsdata=2 2006.169.07:31:02.16&checkk5/chk_obsdata=3 2006.169.07:31:02.17&checkk5/chk_obsdata=4 2006.169.07:31:02.17&checkk5/k5log=1 2006.169.07:31:02.17&checkk5/k5log=2 2006.169.07:31:02.22&checkk5/k5log=3 2006.169.07:31:02.23&checkk5/k5log=4 2006.169.07:31:02.23&checkk5/obsinfo 2006.169.07:31:02.61/chk_autoobs//k5ts1/ autoobs is running! 2006.169.07:31:02.98/chk_autoobs//k5ts2/ autoobs is running! 2006.169.07:31:07.00/chk_autoobs//k5ts3?ERROR: timeout happened! 2006.169.07:31:07.38/chk_autoobs//k5ts4/ autoobs is running! 2006.169.07:31:07.75/chk_obsdata//k5ts1/T1690730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:31:08.13/chk_obsdata//k5ts2/T1690730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:31:15.15/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.07:31:15.52/chk_obsdata//k5ts4/T1690730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:31:16.23/k5log//k5ts1_log_newline 2006.169.07:31:16.92/k5log//k5ts2_log_newline 2006.169.07:31:24.02/k5log//k5ts3?ERROR: timeout happened! 2006.169.07:31:24.71/k5log//k5ts4_log_newline 2006.169.07:31:24.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.07:31:24.89:4f8m12a=1 2006.169.07:31:24.89$4f8m12a/echo=on 2006.169.07:31:24.89$4f8m12a/pcalon 2006.169.07:31:24.89$pcalon/"no phase cal control is implemented here 2006.169.07:31:24.89$4f8m12a/"tpicd=stop 2006.169.07:31:24.89$4f8m12a/vc4f8 2006.169.07:31:24.89$vc4f8/valo=1,532.99 2006.169.07:31:24.90#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.169.07:31:24.90#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.169.07:31:24.90#ibcon#ireg 17 cls_cnt 0 2006.169.07:31:24.90#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:31:24.90#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:31:24.90#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:31:24.90#ibcon#enter wrdev, iclass 5, count 0 2006.169.07:31:24.90#ibcon#first serial, iclass 5, count 0 2006.169.07:31:24.90#ibcon#enter sib2, iclass 5, count 0 2006.169.07:31:24.90#ibcon#flushed, iclass 5, count 0 2006.169.07:31:24.90#ibcon#about to write, iclass 5, count 0 2006.169.07:31:24.90#ibcon#wrote, iclass 5, count 0 2006.169.07:31:24.90#ibcon#about to read 3, iclass 5, count 0 2006.169.07:31:24.92#ibcon#read 3, iclass 5, count 0 2006.169.07:31:24.92#ibcon#about to read 4, iclass 5, count 0 2006.169.07:31:24.92#ibcon#read 4, iclass 5, count 0 2006.169.07:31:24.92#ibcon#about to read 5, iclass 5, count 0 2006.169.07:31:24.92#ibcon#read 5, iclass 5, count 0 2006.169.07:31:24.92#ibcon#about to read 6, iclass 5, count 0 2006.169.07:31:24.92#ibcon#read 6, iclass 5, count 0 2006.169.07:31:24.92#ibcon#end of sib2, iclass 5, count 0 2006.169.07:31:24.92#ibcon#*mode == 0, iclass 5, count 0 2006.169.07:31:24.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.169.07:31:24.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.07:31:24.92#ibcon#*before write, iclass 5, count 0 2006.169.07:31:24.92#ibcon#enter sib2, iclass 5, count 0 2006.169.07:31:24.92#ibcon#flushed, iclass 5, count 0 2006.169.07:31:24.92#ibcon#about to write, iclass 5, count 0 2006.169.07:31:24.92#ibcon#wrote, iclass 5, count 0 2006.169.07:31:24.92#ibcon#about to read 3, iclass 5, count 0 2006.169.07:31:24.97#ibcon#read 3, iclass 5, count 0 2006.169.07:31:24.97#ibcon#about to read 4, iclass 5, count 0 2006.169.07:31:24.97#ibcon#read 4, iclass 5, count 0 2006.169.07:31:24.97#ibcon#about to read 5, iclass 5, count 0 2006.169.07:31:24.97#ibcon#read 5, iclass 5, count 0 2006.169.07:31:24.97#ibcon#about to read 6, iclass 5, count 0 2006.169.07:31:24.97#ibcon#read 6, iclass 5, count 0 2006.169.07:31:24.97#ibcon#end of sib2, iclass 5, count 0 2006.169.07:31:24.97#ibcon#*after write, iclass 5, count 0 2006.169.07:31:24.97#ibcon#*before return 0, iclass 5, count 0 2006.169.07:31:24.97#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:31:24.97#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:31:24.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.169.07:31:24.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.169.07:31:24.97$vc4f8/va=1,8 2006.169.07:31:24.97#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.169.07:31:24.97#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.169.07:31:24.97#ibcon#ireg 11 cls_cnt 2 2006.169.07:31:24.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:31:24.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:31:24.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:31:24.97#ibcon#enter wrdev, iclass 7, count 2 2006.169.07:31:24.97#ibcon#first serial, iclass 7, count 2 2006.169.07:31:24.97#ibcon#enter sib2, iclass 7, count 2 2006.169.07:31:24.97#ibcon#flushed, iclass 7, count 2 2006.169.07:31:24.97#ibcon#about to write, iclass 7, count 2 2006.169.07:31:24.97#ibcon#wrote, iclass 7, count 2 2006.169.07:31:24.97#ibcon#about to read 3, iclass 7, count 2 2006.169.07:31:24.99#ibcon#read 3, iclass 7, count 2 2006.169.07:31:24.99#ibcon#about to read 4, iclass 7, count 2 2006.169.07:31:24.99#ibcon#read 4, iclass 7, count 2 2006.169.07:31:24.99#ibcon#about to read 5, iclass 7, count 2 2006.169.07:31:24.99#ibcon#read 5, iclass 7, count 2 2006.169.07:31:24.99#ibcon#about to read 6, iclass 7, count 2 2006.169.07:31:24.99#ibcon#read 6, iclass 7, count 2 2006.169.07:31:24.99#ibcon#end of sib2, iclass 7, count 2 2006.169.07:31:24.99#ibcon#*mode == 0, iclass 7, count 2 2006.169.07:31:24.99#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.169.07:31:24.99#ibcon#[25=AT01-08\r\n] 2006.169.07:31:24.99#ibcon#*before write, iclass 7, count 2 2006.169.07:31:24.99#ibcon#enter sib2, iclass 7, count 2 2006.169.07:31:24.99#ibcon#flushed, iclass 7, count 2 2006.169.07:31:24.99#ibcon#about to write, iclass 7, count 2 2006.169.07:31:24.99#ibcon#wrote, iclass 7, count 2 2006.169.07:31:24.99#ibcon#about to read 3, iclass 7, count 2 2006.169.07:31:25.02#ibcon#read 3, iclass 7, count 2 2006.169.07:31:25.02#ibcon#about to read 4, iclass 7, count 2 2006.169.07:31:25.02#ibcon#read 4, iclass 7, count 2 2006.169.07:31:25.02#ibcon#about to read 5, iclass 7, count 2 2006.169.07:31:25.02#ibcon#read 5, iclass 7, count 2 2006.169.07:31:25.02#ibcon#about to read 6, iclass 7, count 2 2006.169.07:31:25.02#ibcon#read 6, iclass 7, count 2 2006.169.07:31:25.02#ibcon#end of sib2, iclass 7, count 2 2006.169.07:31:25.02#ibcon#*after write, iclass 7, count 2 2006.169.07:31:25.02#ibcon#*before return 0, iclass 7, count 2 2006.169.07:31:25.02#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:31:25.02#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:31:25.02#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.169.07:31:25.02#ibcon#ireg 7 cls_cnt 0 2006.169.07:31:25.02#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:31:25.08#abcon#<5=/05 3.3 5.4 18.211001003.8\r\n> 2006.169.07:31:25.10#abcon#{5=INTERFACE CLEAR} 2006.169.07:31:25.15#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:31:25.15#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:31:25.15#ibcon#enter wrdev, iclass 7, count 0 2006.169.07:31:25.15#ibcon#first serial, iclass 7, count 0 2006.169.07:31:25.15#ibcon#enter sib2, iclass 7, count 0 2006.169.07:31:25.15#ibcon#flushed, iclass 7, count 0 2006.169.07:31:25.15#ibcon#about to write, iclass 7, count 0 2006.169.07:31:25.15#ibcon#wrote, iclass 7, count 0 2006.169.07:31:25.15#ibcon#about to read 3, iclass 7, count 0 2006.169.07:31:25.17#ibcon#read 3, iclass 7, count 0 2006.169.07:31:25.17#ibcon#about to read 4, iclass 7, count 0 2006.169.07:31:25.17#ibcon#read 4, iclass 7, count 0 2006.169.07:31:25.17#ibcon#about to read 5, iclass 7, count 0 2006.169.07:31:25.17#ibcon#read 5, iclass 7, count 0 2006.169.07:31:25.17#ibcon#about to read 6, iclass 7, count 0 2006.169.07:31:25.17#ibcon#read 6, iclass 7, count 0 2006.169.07:31:25.17#ibcon#end of sib2, iclass 7, count 0 2006.169.07:31:25.17#ibcon#*mode == 0, iclass 7, count 0 2006.169.07:31:25.17#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.169.07:31:25.17#ibcon#[25=USB\r\n] 2006.169.07:31:25.17#ibcon#*before write, iclass 7, count 0 2006.169.07:31:25.17#ibcon#enter sib2, iclass 7, count 0 2006.169.07:31:25.17#ibcon#flushed, iclass 7, count 0 2006.169.07:31:25.17#ibcon#about to write, iclass 7, count 0 2006.169.07:31:25.17#ibcon#wrote, iclass 7, count 0 2006.169.07:31:25.17#ibcon#about to read 3, iclass 7, count 0 2006.169.07:31:25.17#abcon#[5=S1D000X0/0*\r\n] 2006.169.07:31:25.20#ibcon#read 3, iclass 7, count 0 2006.169.07:31:25.20#ibcon#about to read 4, iclass 7, count 0 2006.169.07:31:25.20#ibcon#read 4, iclass 7, count 0 2006.169.07:31:25.20#ibcon#about to read 5, iclass 7, count 0 2006.169.07:31:25.20#ibcon#read 5, iclass 7, count 0 2006.169.07:31:25.20#ibcon#about to read 6, iclass 7, count 0 2006.169.07:31:25.20#ibcon#read 6, iclass 7, count 0 2006.169.07:31:25.20#ibcon#end of sib2, iclass 7, count 0 2006.169.07:31:25.20#ibcon#*after write, iclass 7, count 0 2006.169.07:31:25.20#ibcon#*before return 0, iclass 7, count 0 2006.169.07:31:25.20#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:31:25.20#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:31:25.20#ibcon#about to clear, iclass 7 cls_cnt 0 2006.169.07:31:25.20#ibcon#cleared, iclass 7 cls_cnt 0 2006.169.07:31:25.20$vc4f8/valo=2,572.99 2006.169.07:31:25.20#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.169.07:31:25.20#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.169.07:31:25.20#ibcon#ireg 17 cls_cnt 0 2006.169.07:31:25.20#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:31:25.20#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:31:25.20#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:31:25.20#ibcon#enter wrdev, iclass 15, count 0 2006.169.07:31:25.20#ibcon#first serial, iclass 15, count 0 2006.169.07:31:25.20#ibcon#enter sib2, iclass 15, count 0 2006.169.07:31:25.20#ibcon#flushed, iclass 15, count 0 2006.169.07:31:25.20#ibcon#about to write, iclass 15, count 0 2006.169.07:31:25.20#ibcon#wrote, iclass 15, count 0 2006.169.07:31:25.20#ibcon#about to read 3, iclass 15, count 0 2006.169.07:31:25.22#ibcon#read 3, iclass 15, count 0 2006.169.07:31:25.22#ibcon#about to read 4, iclass 15, count 0 2006.169.07:31:25.22#ibcon#read 4, iclass 15, count 0 2006.169.07:31:25.22#ibcon#about to read 5, iclass 15, count 0 2006.169.07:31:25.22#ibcon#read 5, iclass 15, count 0 2006.169.07:31:25.22#ibcon#about to read 6, iclass 15, count 0 2006.169.07:31:25.22#ibcon#read 6, iclass 15, count 0 2006.169.07:31:25.22#ibcon#end of sib2, iclass 15, count 0 2006.169.07:31:25.22#ibcon#*mode == 0, iclass 15, count 0 2006.169.07:31:25.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.169.07:31:25.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.07:31:25.22#ibcon#*before write, iclass 15, count 0 2006.169.07:31:25.22#ibcon#enter sib2, iclass 15, count 0 2006.169.07:31:25.22#ibcon#flushed, iclass 15, count 0 2006.169.07:31:25.22#ibcon#about to write, iclass 15, count 0 2006.169.07:31:25.22#ibcon#wrote, iclass 15, count 0 2006.169.07:31:25.22#ibcon#about to read 3, iclass 15, count 0 2006.169.07:31:25.26#ibcon#read 3, iclass 15, count 0 2006.169.07:31:25.26#ibcon#about to read 4, iclass 15, count 0 2006.169.07:31:25.26#ibcon#read 4, iclass 15, count 0 2006.169.07:31:25.26#ibcon#about to read 5, iclass 15, count 0 2006.169.07:31:25.26#ibcon#read 5, iclass 15, count 0 2006.169.07:31:25.26#ibcon#about to read 6, iclass 15, count 0 2006.169.07:31:25.26#ibcon#read 6, iclass 15, count 0 2006.169.07:31:25.26#ibcon#end of sib2, iclass 15, count 0 2006.169.07:31:25.26#ibcon#*after write, iclass 15, count 0 2006.169.07:31:25.26#ibcon#*before return 0, iclass 15, count 0 2006.169.07:31:25.26#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:31:25.26#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:31:25.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.169.07:31:25.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.169.07:31:25.26$vc4f8/va=2,7 2006.169.07:31:25.26#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.169.07:31:25.26#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.169.07:31:25.26#ibcon#ireg 11 cls_cnt 2 2006.169.07:31:25.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.169.07:31:25.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.169.07:31:25.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.169.07:31:25.32#ibcon#enter wrdev, iclass 17, count 2 2006.169.07:31:25.32#ibcon#first serial, iclass 17, count 2 2006.169.07:31:25.32#ibcon#enter sib2, iclass 17, count 2 2006.169.07:31:25.32#ibcon#flushed, iclass 17, count 2 2006.169.07:31:25.32#ibcon#about to write, iclass 17, count 2 2006.169.07:31:25.32#ibcon#wrote, iclass 17, count 2 2006.169.07:31:25.32#ibcon#about to read 3, iclass 17, count 2 2006.169.07:31:25.34#ibcon#read 3, iclass 17, count 2 2006.169.07:31:25.34#ibcon#about to read 4, iclass 17, count 2 2006.169.07:31:25.34#ibcon#read 4, iclass 17, count 2 2006.169.07:31:25.34#ibcon#about to read 5, iclass 17, count 2 2006.169.07:31:25.34#ibcon#read 5, iclass 17, count 2 2006.169.07:31:25.34#ibcon#about to read 6, iclass 17, count 2 2006.169.07:31:25.34#ibcon#read 6, iclass 17, count 2 2006.169.07:31:25.34#ibcon#end of sib2, iclass 17, count 2 2006.169.07:31:25.34#ibcon#*mode == 0, iclass 17, count 2 2006.169.07:31:25.34#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.169.07:31:25.34#ibcon#[25=AT02-07\r\n] 2006.169.07:31:25.34#ibcon#*before write, iclass 17, count 2 2006.169.07:31:25.34#ibcon#enter sib2, iclass 17, count 2 2006.169.07:31:25.34#ibcon#flushed, iclass 17, count 2 2006.169.07:31:25.34#ibcon#about to write, iclass 17, count 2 2006.169.07:31:25.34#ibcon#wrote, iclass 17, count 2 2006.169.07:31:25.34#ibcon#about to read 3, iclass 17, count 2 2006.169.07:31:25.37#ibcon#read 3, iclass 17, count 2 2006.169.07:31:25.37#ibcon#about to read 4, iclass 17, count 2 2006.169.07:31:25.37#ibcon#read 4, iclass 17, count 2 2006.169.07:31:25.37#ibcon#about to read 5, iclass 17, count 2 2006.169.07:31:25.37#ibcon#read 5, iclass 17, count 2 2006.169.07:31:25.37#ibcon#about to read 6, iclass 17, count 2 2006.169.07:31:25.37#ibcon#read 6, iclass 17, count 2 2006.169.07:31:25.37#ibcon#end of sib2, iclass 17, count 2 2006.169.07:31:25.37#ibcon#*after write, iclass 17, count 2 2006.169.07:31:25.37#ibcon#*before return 0, iclass 17, count 2 2006.169.07:31:25.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.169.07:31:25.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.169.07:31:25.37#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.169.07:31:25.37#ibcon#ireg 7 cls_cnt 0 2006.169.07:31:25.37#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.169.07:31:25.49#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.169.07:31:25.49#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.169.07:31:25.49#ibcon#enter wrdev, iclass 17, count 0 2006.169.07:31:25.49#ibcon#first serial, iclass 17, count 0 2006.169.07:31:25.49#ibcon#enter sib2, iclass 17, count 0 2006.169.07:31:25.49#ibcon#flushed, iclass 17, count 0 2006.169.07:31:25.49#ibcon#about to write, iclass 17, count 0 2006.169.07:31:25.49#ibcon#wrote, iclass 17, count 0 2006.169.07:31:25.49#ibcon#about to read 3, iclass 17, count 0 2006.169.07:31:25.51#ibcon#read 3, iclass 17, count 0 2006.169.07:31:25.51#ibcon#about to read 4, iclass 17, count 0 2006.169.07:31:25.51#ibcon#read 4, iclass 17, count 0 2006.169.07:31:25.51#ibcon#about to read 5, iclass 17, count 0 2006.169.07:31:25.51#ibcon#read 5, iclass 17, count 0 2006.169.07:31:25.51#ibcon#about to read 6, iclass 17, count 0 2006.169.07:31:25.51#ibcon#read 6, iclass 17, count 0 2006.169.07:31:25.51#ibcon#end of sib2, iclass 17, count 0 2006.169.07:31:25.51#ibcon#*mode == 0, iclass 17, count 0 2006.169.07:31:25.51#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.169.07:31:25.51#ibcon#[25=USB\r\n] 2006.169.07:31:25.51#ibcon#*before write, iclass 17, count 0 2006.169.07:31:25.51#ibcon#enter sib2, iclass 17, count 0 2006.169.07:31:25.51#ibcon#flushed, iclass 17, count 0 2006.169.07:31:25.51#ibcon#about to write, iclass 17, count 0 2006.169.07:31:25.51#ibcon#wrote, iclass 17, count 0 2006.169.07:31:25.51#ibcon#about to read 3, iclass 17, count 0 2006.169.07:31:25.54#ibcon#read 3, iclass 17, count 0 2006.169.07:31:25.54#ibcon#about to read 4, iclass 17, count 0 2006.169.07:31:25.54#ibcon#read 4, iclass 17, count 0 2006.169.07:31:25.54#ibcon#about to read 5, iclass 17, count 0 2006.169.07:31:25.54#ibcon#read 5, iclass 17, count 0 2006.169.07:31:25.54#ibcon#about to read 6, iclass 17, count 0 2006.169.07:31:25.54#ibcon#read 6, iclass 17, count 0 2006.169.07:31:25.54#ibcon#end of sib2, iclass 17, count 0 2006.169.07:31:25.54#ibcon#*after write, iclass 17, count 0 2006.169.07:31:25.54#ibcon#*before return 0, iclass 17, count 0 2006.169.07:31:25.54#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.169.07:31:25.54#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.169.07:31:25.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.169.07:31:25.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.169.07:31:25.54$vc4f8/valo=3,672.99 2006.169.07:31:25.54#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.169.07:31:25.54#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.169.07:31:25.54#ibcon#ireg 17 cls_cnt 0 2006.169.07:31:25.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.169.07:31:25.54#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.169.07:31:25.54#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.169.07:31:25.54#ibcon#enter wrdev, iclass 19, count 0 2006.169.07:31:25.54#ibcon#first serial, iclass 19, count 0 2006.169.07:31:25.54#ibcon#enter sib2, iclass 19, count 0 2006.169.07:31:25.54#ibcon#flushed, iclass 19, count 0 2006.169.07:31:25.54#ibcon#about to write, iclass 19, count 0 2006.169.07:31:25.54#ibcon#wrote, iclass 19, count 0 2006.169.07:31:25.54#ibcon#about to read 3, iclass 19, count 0 2006.169.07:31:25.56#ibcon#read 3, iclass 19, count 0 2006.169.07:31:25.56#ibcon#about to read 4, iclass 19, count 0 2006.169.07:31:25.56#ibcon#read 4, iclass 19, count 0 2006.169.07:31:25.56#ibcon#about to read 5, iclass 19, count 0 2006.169.07:31:25.56#ibcon#read 5, iclass 19, count 0 2006.169.07:31:25.56#ibcon#about to read 6, iclass 19, count 0 2006.169.07:31:25.56#ibcon#read 6, iclass 19, count 0 2006.169.07:31:25.56#ibcon#end of sib2, iclass 19, count 0 2006.169.07:31:25.56#ibcon#*mode == 0, iclass 19, count 0 2006.169.07:31:25.56#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.169.07:31:25.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.07:31:25.56#ibcon#*before write, iclass 19, count 0 2006.169.07:31:25.56#ibcon#enter sib2, iclass 19, count 0 2006.169.07:31:25.56#ibcon#flushed, iclass 19, count 0 2006.169.07:31:25.56#ibcon#about to write, iclass 19, count 0 2006.169.07:31:25.56#ibcon#wrote, iclass 19, count 0 2006.169.07:31:25.56#ibcon#about to read 3, iclass 19, count 0 2006.169.07:31:25.60#ibcon#read 3, iclass 19, count 0 2006.169.07:31:25.60#ibcon#about to read 4, iclass 19, count 0 2006.169.07:31:25.60#ibcon#read 4, iclass 19, count 0 2006.169.07:31:25.60#ibcon#about to read 5, iclass 19, count 0 2006.169.07:31:25.60#ibcon#read 5, iclass 19, count 0 2006.169.07:31:25.60#ibcon#about to read 6, iclass 19, count 0 2006.169.07:31:25.60#ibcon#read 6, iclass 19, count 0 2006.169.07:31:25.60#ibcon#end of sib2, iclass 19, count 0 2006.169.07:31:25.60#ibcon#*after write, iclass 19, count 0 2006.169.07:31:25.60#ibcon#*before return 0, iclass 19, count 0 2006.169.07:31:25.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.169.07:31:25.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.169.07:31:25.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.169.07:31:25.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.169.07:31:25.60$vc4f8/va=3,6 2006.169.07:31:25.60#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.169.07:31:25.60#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.169.07:31:25.60#ibcon#ireg 11 cls_cnt 2 2006.169.07:31:25.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.169.07:31:25.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.169.07:31:25.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.169.07:31:25.66#ibcon#enter wrdev, iclass 21, count 2 2006.169.07:31:25.66#ibcon#first serial, iclass 21, count 2 2006.169.07:31:25.66#ibcon#enter sib2, iclass 21, count 2 2006.169.07:31:25.66#ibcon#flushed, iclass 21, count 2 2006.169.07:31:25.66#ibcon#about to write, iclass 21, count 2 2006.169.07:31:25.66#ibcon#wrote, iclass 21, count 2 2006.169.07:31:25.66#ibcon#about to read 3, iclass 21, count 2 2006.169.07:31:25.68#ibcon#read 3, iclass 21, count 2 2006.169.07:31:25.68#ibcon#about to read 4, iclass 21, count 2 2006.169.07:31:25.68#ibcon#read 4, iclass 21, count 2 2006.169.07:31:25.68#ibcon#about to read 5, iclass 21, count 2 2006.169.07:31:25.68#ibcon#read 5, iclass 21, count 2 2006.169.07:31:25.68#ibcon#about to read 6, iclass 21, count 2 2006.169.07:31:25.68#ibcon#read 6, iclass 21, count 2 2006.169.07:31:25.68#ibcon#end of sib2, iclass 21, count 2 2006.169.07:31:25.68#ibcon#*mode == 0, iclass 21, count 2 2006.169.07:31:25.68#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.169.07:31:25.68#ibcon#[25=AT03-06\r\n] 2006.169.07:31:25.68#ibcon#*before write, iclass 21, count 2 2006.169.07:31:25.68#ibcon#enter sib2, iclass 21, count 2 2006.169.07:31:25.68#ibcon#flushed, iclass 21, count 2 2006.169.07:31:25.68#ibcon#about to write, iclass 21, count 2 2006.169.07:31:25.68#ibcon#wrote, iclass 21, count 2 2006.169.07:31:25.68#ibcon#about to read 3, iclass 21, count 2 2006.169.07:31:25.71#ibcon#read 3, iclass 21, count 2 2006.169.07:31:25.71#ibcon#about to read 4, iclass 21, count 2 2006.169.07:31:25.71#ibcon#read 4, iclass 21, count 2 2006.169.07:31:25.71#ibcon#about to read 5, iclass 21, count 2 2006.169.07:31:25.71#ibcon#read 5, iclass 21, count 2 2006.169.07:31:25.71#ibcon#about to read 6, iclass 21, count 2 2006.169.07:31:25.71#ibcon#read 6, iclass 21, count 2 2006.169.07:31:25.71#ibcon#end of sib2, iclass 21, count 2 2006.169.07:31:25.71#ibcon#*after write, iclass 21, count 2 2006.169.07:31:25.71#ibcon#*before return 0, iclass 21, count 2 2006.169.07:31:25.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.169.07:31:25.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.169.07:31:25.71#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.169.07:31:25.71#ibcon#ireg 7 cls_cnt 0 2006.169.07:31:25.71#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.169.07:31:25.83#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.169.07:31:25.83#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.169.07:31:25.83#ibcon#enter wrdev, iclass 21, count 0 2006.169.07:31:25.83#ibcon#first serial, iclass 21, count 0 2006.169.07:31:25.83#ibcon#enter sib2, iclass 21, count 0 2006.169.07:31:25.83#ibcon#flushed, iclass 21, count 0 2006.169.07:31:25.83#ibcon#about to write, iclass 21, count 0 2006.169.07:31:25.83#ibcon#wrote, iclass 21, count 0 2006.169.07:31:25.83#ibcon#about to read 3, iclass 21, count 0 2006.169.07:31:25.85#ibcon#read 3, iclass 21, count 0 2006.169.07:31:25.85#ibcon#about to read 4, iclass 21, count 0 2006.169.07:31:25.85#ibcon#read 4, iclass 21, count 0 2006.169.07:31:25.85#ibcon#about to read 5, iclass 21, count 0 2006.169.07:31:25.85#ibcon#read 5, iclass 21, count 0 2006.169.07:31:25.85#ibcon#about to read 6, iclass 21, count 0 2006.169.07:31:25.85#ibcon#read 6, iclass 21, count 0 2006.169.07:31:25.85#ibcon#end of sib2, iclass 21, count 0 2006.169.07:31:25.85#ibcon#*mode == 0, iclass 21, count 0 2006.169.07:31:25.85#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.169.07:31:25.85#ibcon#[25=USB\r\n] 2006.169.07:31:25.85#ibcon#*before write, iclass 21, count 0 2006.169.07:31:25.85#ibcon#enter sib2, iclass 21, count 0 2006.169.07:31:25.85#ibcon#flushed, iclass 21, count 0 2006.169.07:31:25.85#ibcon#about to write, iclass 21, count 0 2006.169.07:31:25.85#ibcon#wrote, iclass 21, count 0 2006.169.07:31:25.85#ibcon#about to read 3, iclass 21, count 0 2006.169.07:31:25.88#ibcon#read 3, iclass 21, count 0 2006.169.07:31:25.88#ibcon#about to read 4, iclass 21, count 0 2006.169.07:31:25.88#ibcon#read 4, iclass 21, count 0 2006.169.07:31:25.88#ibcon#about to read 5, iclass 21, count 0 2006.169.07:31:25.88#ibcon#read 5, iclass 21, count 0 2006.169.07:31:25.88#ibcon#about to read 6, iclass 21, count 0 2006.169.07:31:25.88#ibcon#read 6, iclass 21, count 0 2006.169.07:31:25.88#ibcon#end of sib2, iclass 21, count 0 2006.169.07:31:25.88#ibcon#*after write, iclass 21, count 0 2006.169.07:31:25.88#ibcon#*before return 0, iclass 21, count 0 2006.169.07:31:25.88#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.169.07:31:25.88#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.169.07:31:25.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.169.07:31:25.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.169.07:31:25.88$vc4f8/valo=4,832.99 2006.169.07:31:25.88#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.169.07:31:25.88#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.169.07:31:25.88#ibcon#ireg 17 cls_cnt 0 2006.169.07:31:25.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.169.07:31:25.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.169.07:31:25.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.169.07:31:25.88#ibcon#enter wrdev, iclass 23, count 0 2006.169.07:31:25.88#ibcon#first serial, iclass 23, count 0 2006.169.07:31:25.88#ibcon#enter sib2, iclass 23, count 0 2006.169.07:31:25.88#ibcon#flushed, iclass 23, count 0 2006.169.07:31:25.88#ibcon#about to write, iclass 23, count 0 2006.169.07:31:25.88#ibcon#wrote, iclass 23, count 0 2006.169.07:31:25.88#ibcon#about to read 3, iclass 23, count 0 2006.169.07:31:25.90#ibcon#read 3, iclass 23, count 0 2006.169.07:31:25.90#ibcon#about to read 4, iclass 23, count 0 2006.169.07:31:25.90#ibcon#read 4, iclass 23, count 0 2006.169.07:31:25.90#ibcon#about to read 5, iclass 23, count 0 2006.169.07:31:25.90#ibcon#read 5, iclass 23, count 0 2006.169.07:31:25.90#ibcon#about to read 6, iclass 23, count 0 2006.169.07:31:25.90#ibcon#read 6, iclass 23, count 0 2006.169.07:31:25.90#ibcon#end of sib2, iclass 23, count 0 2006.169.07:31:25.90#ibcon#*mode == 0, iclass 23, count 0 2006.169.07:31:25.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.169.07:31:25.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.07:31:25.90#ibcon#*before write, iclass 23, count 0 2006.169.07:31:25.90#ibcon#enter sib2, iclass 23, count 0 2006.169.07:31:25.90#ibcon#flushed, iclass 23, count 0 2006.169.07:31:25.90#ibcon#about to write, iclass 23, count 0 2006.169.07:31:25.90#ibcon#wrote, iclass 23, count 0 2006.169.07:31:25.90#ibcon#about to read 3, iclass 23, count 0 2006.169.07:31:25.94#ibcon#read 3, iclass 23, count 0 2006.169.07:31:25.94#ibcon#about to read 4, iclass 23, count 0 2006.169.07:31:25.94#ibcon#read 4, iclass 23, count 0 2006.169.07:31:25.94#ibcon#about to read 5, iclass 23, count 0 2006.169.07:31:25.94#ibcon#read 5, iclass 23, count 0 2006.169.07:31:25.94#ibcon#about to read 6, iclass 23, count 0 2006.169.07:31:25.94#ibcon#read 6, iclass 23, count 0 2006.169.07:31:25.94#ibcon#end of sib2, iclass 23, count 0 2006.169.07:31:25.94#ibcon#*after write, iclass 23, count 0 2006.169.07:31:25.94#ibcon#*before return 0, iclass 23, count 0 2006.169.07:31:25.94#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.169.07:31:25.94#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.169.07:31:25.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.169.07:31:25.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.169.07:31:25.94$vc4f8/va=4,7 2006.169.07:31:25.94#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.169.07:31:25.94#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.169.07:31:25.94#ibcon#ireg 11 cls_cnt 2 2006.169.07:31:25.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.169.07:31:26.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.169.07:31:26.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.169.07:31:26.00#ibcon#enter wrdev, iclass 25, count 2 2006.169.07:31:26.00#ibcon#first serial, iclass 25, count 2 2006.169.07:31:26.00#ibcon#enter sib2, iclass 25, count 2 2006.169.07:31:26.00#ibcon#flushed, iclass 25, count 2 2006.169.07:31:26.00#ibcon#about to write, iclass 25, count 2 2006.169.07:31:26.00#ibcon#wrote, iclass 25, count 2 2006.169.07:31:26.00#ibcon#about to read 3, iclass 25, count 2 2006.169.07:31:26.02#ibcon#read 3, iclass 25, count 2 2006.169.07:31:26.02#ibcon#about to read 4, iclass 25, count 2 2006.169.07:31:26.02#ibcon#read 4, iclass 25, count 2 2006.169.07:31:26.02#ibcon#about to read 5, iclass 25, count 2 2006.169.07:31:26.02#ibcon#read 5, iclass 25, count 2 2006.169.07:31:26.02#ibcon#about to read 6, iclass 25, count 2 2006.169.07:31:26.02#ibcon#read 6, iclass 25, count 2 2006.169.07:31:26.02#ibcon#end of sib2, iclass 25, count 2 2006.169.07:31:26.02#ibcon#*mode == 0, iclass 25, count 2 2006.169.07:31:26.02#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.169.07:31:26.02#ibcon#[25=AT04-07\r\n] 2006.169.07:31:26.02#ibcon#*before write, iclass 25, count 2 2006.169.07:31:26.02#ibcon#enter sib2, iclass 25, count 2 2006.169.07:31:26.02#ibcon#flushed, iclass 25, count 2 2006.169.07:31:26.02#ibcon#about to write, iclass 25, count 2 2006.169.07:31:26.02#ibcon#wrote, iclass 25, count 2 2006.169.07:31:26.02#ibcon#about to read 3, iclass 25, count 2 2006.169.07:31:26.05#ibcon#read 3, iclass 25, count 2 2006.169.07:31:26.05#ibcon#about to read 4, iclass 25, count 2 2006.169.07:31:26.05#ibcon#read 4, iclass 25, count 2 2006.169.07:31:26.05#ibcon#about to read 5, iclass 25, count 2 2006.169.07:31:26.05#ibcon#read 5, iclass 25, count 2 2006.169.07:31:26.05#ibcon#about to read 6, iclass 25, count 2 2006.169.07:31:26.05#ibcon#read 6, iclass 25, count 2 2006.169.07:31:26.05#ibcon#end of sib2, iclass 25, count 2 2006.169.07:31:26.05#ibcon#*after write, iclass 25, count 2 2006.169.07:31:26.05#ibcon#*before return 0, iclass 25, count 2 2006.169.07:31:26.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.169.07:31:26.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.169.07:31:26.05#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.169.07:31:26.05#ibcon#ireg 7 cls_cnt 0 2006.169.07:31:26.05#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.169.07:31:26.17#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.169.07:31:26.17#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.169.07:31:26.17#ibcon#enter wrdev, iclass 25, count 0 2006.169.07:31:26.17#ibcon#first serial, iclass 25, count 0 2006.169.07:31:26.17#ibcon#enter sib2, iclass 25, count 0 2006.169.07:31:26.17#ibcon#flushed, iclass 25, count 0 2006.169.07:31:26.17#ibcon#about to write, iclass 25, count 0 2006.169.07:31:26.17#ibcon#wrote, iclass 25, count 0 2006.169.07:31:26.17#ibcon#about to read 3, iclass 25, count 0 2006.169.07:31:26.19#ibcon#read 3, iclass 25, count 0 2006.169.07:31:26.19#ibcon#about to read 4, iclass 25, count 0 2006.169.07:31:26.19#ibcon#read 4, iclass 25, count 0 2006.169.07:31:26.19#ibcon#about to read 5, iclass 25, count 0 2006.169.07:31:26.19#ibcon#read 5, iclass 25, count 0 2006.169.07:31:26.19#ibcon#about to read 6, iclass 25, count 0 2006.169.07:31:26.19#ibcon#read 6, iclass 25, count 0 2006.169.07:31:26.19#ibcon#end of sib2, iclass 25, count 0 2006.169.07:31:26.19#ibcon#*mode == 0, iclass 25, count 0 2006.169.07:31:26.19#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.169.07:31:26.19#ibcon#[25=USB\r\n] 2006.169.07:31:26.19#ibcon#*before write, iclass 25, count 0 2006.169.07:31:26.19#ibcon#enter sib2, iclass 25, count 0 2006.169.07:31:26.19#ibcon#flushed, iclass 25, count 0 2006.169.07:31:26.19#ibcon#about to write, iclass 25, count 0 2006.169.07:31:26.19#ibcon#wrote, iclass 25, count 0 2006.169.07:31:26.19#ibcon#about to read 3, iclass 25, count 0 2006.169.07:31:26.22#ibcon#read 3, iclass 25, count 0 2006.169.07:31:26.22#ibcon#about to read 4, iclass 25, count 0 2006.169.07:31:26.22#ibcon#read 4, iclass 25, count 0 2006.169.07:31:26.22#ibcon#about to read 5, iclass 25, count 0 2006.169.07:31:26.22#ibcon#read 5, iclass 25, count 0 2006.169.07:31:26.22#ibcon#about to read 6, iclass 25, count 0 2006.169.07:31:26.22#ibcon#read 6, iclass 25, count 0 2006.169.07:31:26.22#ibcon#end of sib2, iclass 25, count 0 2006.169.07:31:26.22#ibcon#*after write, iclass 25, count 0 2006.169.07:31:26.22#ibcon#*before return 0, iclass 25, count 0 2006.169.07:31:26.22#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.169.07:31:26.22#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.169.07:31:26.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.169.07:31:26.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.169.07:31:26.22$vc4f8/valo=5,652.99 2006.169.07:31:26.22#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.169.07:31:26.22#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.169.07:31:26.22#ibcon#ireg 17 cls_cnt 0 2006.169.07:31:26.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:31:26.22#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:31:26.22#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:31:26.22#ibcon#enter wrdev, iclass 27, count 0 2006.169.07:31:26.22#ibcon#first serial, iclass 27, count 0 2006.169.07:31:26.22#ibcon#enter sib2, iclass 27, count 0 2006.169.07:31:26.22#ibcon#flushed, iclass 27, count 0 2006.169.07:31:26.22#ibcon#about to write, iclass 27, count 0 2006.169.07:31:26.22#ibcon#wrote, iclass 27, count 0 2006.169.07:31:26.22#ibcon#about to read 3, iclass 27, count 0 2006.169.07:31:26.24#ibcon#read 3, iclass 27, count 0 2006.169.07:31:26.24#ibcon#about to read 4, iclass 27, count 0 2006.169.07:31:26.24#ibcon#read 4, iclass 27, count 0 2006.169.07:31:26.24#ibcon#about to read 5, iclass 27, count 0 2006.169.07:31:26.24#ibcon#read 5, iclass 27, count 0 2006.169.07:31:26.24#ibcon#about to read 6, iclass 27, count 0 2006.169.07:31:26.24#ibcon#read 6, iclass 27, count 0 2006.169.07:31:26.24#ibcon#end of sib2, iclass 27, count 0 2006.169.07:31:26.24#ibcon#*mode == 0, iclass 27, count 0 2006.169.07:31:26.24#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.169.07:31:26.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.07:31:26.24#ibcon#*before write, iclass 27, count 0 2006.169.07:31:26.24#ibcon#enter sib2, iclass 27, count 0 2006.169.07:31:26.24#ibcon#flushed, iclass 27, count 0 2006.169.07:31:26.24#ibcon#about to write, iclass 27, count 0 2006.169.07:31:26.24#ibcon#wrote, iclass 27, count 0 2006.169.07:31:26.24#ibcon#about to read 3, iclass 27, count 0 2006.169.07:31:26.28#ibcon#read 3, iclass 27, count 0 2006.169.07:31:26.28#ibcon#about to read 4, iclass 27, count 0 2006.169.07:31:26.28#ibcon#read 4, iclass 27, count 0 2006.169.07:31:26.28#ibcon#about to read 5, iclass 27, count 0 2006.169.07:31:26.28#ibcon#read 5, iclass 27, count 0 2006.169.07:31:26.28#ibcon#about to read 6, iclass 27, count 0 2006.169.07:31:26.28#ibcon#read 6, iclass 27, count 0 2006.169.07:31:26.28#ibcon#end of sib2, iclass 27, count 0 2006.169.07:31:26.28#ibcon#*after write, iclass 27, count 0 2006.169.07:31:26.28#ibcon#*before return 0, iclass 27, count 0 2006.169.07:31:26.28#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:31:26.28#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:31:26.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.169.07:31:26.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.169.07:31:26.28$vc4f8/va=5,7 2006.169.07:31:26.28#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.169.07:31:26.28#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.169.07:31:26.28#ibcon#ireg 11 cls_cnt 2 2006.169.07:31:26.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.169.07:31:26.34#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.169.07:31:26.34#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.169.07:31:26.34#ibcon#enter wrdev, iclass 29, count 2 2006.169.07:31:26.34#ibcon#first serial, iclass 29, count 2 2006.169.07:31:26.34#ibcon#enter sib2, iclass 29, count 2 2006.169.07:31:26.34#ibcon#flushed, iclass 29, count 2 2006.169.07:31:26.34#ibcon#about to write, iclass 29, count 2 2006.169.07:31:26.34#ibcon#wrote, iclass 29, count 2 2006.169.07:31:26.34#ibcon#about to read 3, iclass 29, count 2 2006.169.07:31:26.36#ibcon#read 3, iclass 29, count 2 2006.169.07:31:26.36#ibcon#about to read 4, iclass 29, count 2 2006.169.07:31:26.36#ibcon#read 4, iclass 29, count 2 2006.169.07:31:26.36#ibcon#about to read 5, iclass 29, count 2 2006.169.07:31:26.36#ibcon#read 5, iclass 29, count 2 2006.169.07:31:26.36#ibcon#about to read 6, iclass 29, count 2 2006.169.07:31:26.36#ibcon#read 6, iclass 29, count 2 2006.169.07:31:26.36#ibcon#end of sib2, iclass 29, count 2 2006.169.07:31:26.36#ibcon#*mode == 0, iclass 29, count 2 2006.169.07:31:26.36#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.169.07:31:26.36#ibcon#[25=AT05-07\r\n] 2006.169.07:31:26.36#ibcon#*before write, iclass 29, count 2 2006.169.07:31:26.36#ibcon#enter sib2, iclass 29, count 2 2006.169.07:31:26.36#ibcon#flushed, iclass 29, count 2 2006.169.07:31:26.36#ibcon#about to write, iclass 29, count 2 2006.169.07:31:26.36#ibcon#wrote, iclass 29, count 2 2006.169.07:31:26.36#ibcon#about to read 3, iclass 29, count 2 2006.169.07:31:26.39#ibcon#read 3, iclass 29, count 2 2006.169.07:31:26.39#ibcon#about to read 4, iclass 29, count 2 2006.169.07:31:26.39#ibcon#read 4, iclass 29, count 2 2006.169.07:31:26.39#ibcon#about to read 5, iclass 29, count 2 2006.169.07:31:26.39#ibcon#read 5, iclass 29, count 2 2006.169.07:31:26.39#ibcon#about to read 6, iclass 29, count 2 2006.169.07:31:26.39#ibcon#read 6, iclass 29, count 2 2006.169.07:31:26.39#ibcon#end of sib2, iclass 29, count 2 2006.169.07:31:26.39#ibcon#*after write, iclass 29, count 2 2006.169.07:31:26.39#ibcon#*before return 0, iclass 29, count 2 2006.169.07:31:26.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.169.07:31:26.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.169.07:31:26.39#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.169.07:31:26.39#ibcon#ireg 7 cls_cnt 0 2006.169.07:31:26.39#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.169.07:31:26.51#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.169.07:31:26.51#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.169.07:31:26.51#ibcon#enter wrdev, iclass 29, count 0 2006.169.07:31:26.51#ibcon#first serial, iclass 29, count 0 2006.169.07:31:26.51#ibcon#enter sib2, iclass 29, count 0 2006.169.07:31:26.51#ibcon#flushed, iclass 29, count 0 2006.169.07:31:26.51#ibcon#about to write, iclass 29, count 0 2006.169.07:31:26.51#ibcon#wrote, iclass 29, count 0 2006.169.07:31:26.51#ibcon#about to read 3, iclass 29, count 0 2006.169.07:31:26.53#ibcon#read 3, iclass 29, count 0 2006.169.07:31:26.53#ibcon#about to read 4, iclass 29, count 0 2006.169.07:31:26.53#ibcon#read 4, iclass 29, count 0 2006.169.07:31:26.53#ibcon#about to read 5, iclass 29, count 0 2006.169.07:31:26.53#ibcon#read 5, iclass 29, count 0 2006.169.07:31:26.53#ibcon#about to read 6, iclass 29, count 0 2006.169.07:31:26.53#ibcon#read 6, iclass 29, count 0 2006.169.07:31:26.53#ibcon#end of sib2, iclass 29, count 0 2006.169.07:31:26.53#ibcon#*mode == 0, iclass 29, count 0 2006.169.07:31:26.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.169.07:31:26.53#ibcon#[25=USB\r\n] 2006.169.07:31:26.53#ibcon#*before write, iclass 29, count 0 2006.169.07:31:26.53#ibcon#enter sib2, iclass 29, count 0 2006.169.07:31:26.53#ibcon#flushed, iclass 29, count 0 2006.169.07:31:26.53#ibcon#about to write, iclass 29, count 0 2006.169.07:31:26.53#ibcon#wrote, iclass 29, count 0 2006.169.07:31:26.53#ibcon#about to read 3, iclass 29, count 0 2006.169.07:31:26.56#ibcon#read 3, iclass 29, count 0 2006.169.07:31:26.56#ibcon#about to read 4, iclass 29, count 0 2006.169.07:31:26.56#ibcon#read 4, iclass 29, count 0 2006.169.07:31:26.56#ibcon#about to read 5, iclass 29, count 0 2006.169.07:31:26.56#ibcon#read 5, iclass 29, count 0 2006.169.07:31:26.56#ibcon#about to read 6, iclass 29, count 0 2006.169.07:31:26.56#ibcon#read 6, iclass 29, count 0 2006.169.07:31:26.56#ibcon#end of sib2, iclass 29, count 0 2006.169.07:31:26.56#ibcon#*after write, iclass 29, count 0 2006.169.07:31:26.56#ibcon#*before return 0, iclass 29, count 0 2006.169.07:31:26.56#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.169.07:31:26.56#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.169.07:31:26.56#ibcon#about to clear, iclass 29 cls_cnt 0 2006.169.07:31:26.56#ibcon#cleared, iclass 29 cls_cnt 0 2006.169.07:31:26.56$vc4f8/valo=6,772.99 2006.169.07:31:26.56#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.169.07:31:26.56#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.169.07:31:26.56#ibcon#ireg 17 cls_cnt 0 2006.169.07:31:26.56#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.169.07:31:26.56#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.169.07:31:26.56#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.169.07:31:26.56#ibcon#enter wrdev, iclass 31, count 0 2006.169.07:31:26.56#ibcon#first serial, iclass 31, count 0 2006.169.07:31:26.56#ibcon#enter sib2, iclass 31, count 0 2006.169.07:31:26.56#ibcon#flushed, iclass 31, count 0 2006.169.07:31:26.56#ibcon#about to write, iclass 31, count 0 2006.169.07:31:26.56#ibcon#wrote, iclass 31, count 0 2006.169.07:31:26.56#ibcon#about to read 3, iclass 31, count 0 2006.169.07:31:26.58#ibcon#read 3, iclass 31, count 0 2006.169.07:31:26.58#ibcon#about to read 4, iclass 31, count 0 2006.169.07:31:26.58#ibcon#read 4, iclass 31, count 0 2006.169.07:31:26.58#ibcon#about to read 5, iclass 31, count 0 2006.169.07:31:26.58#ibcon#read 5, iclass 31, count 0 2006.169.07:31:26.58#ibcon#about to read 6, iclass 31, count 0 2006.169.07:31:26.58#ibcon#read 6, iclass 31, count 0 2006.169.07:31:26.58#ibcon#end of sib2, iclass 31, count 0 2006.169.07:31:26.58#ibcon#*mode == 0, iclass 31, count 0 2006.169.07:31:26.58#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.169.07:31:26.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.07:31:26.58#ibcon#*before write, iclass 31, count 0 2006.169.07:31:26.58#ibcon#enter sib2, iclass 31, count 0 2006.169.07:31:26.58#ibcon#flushed, iclass 31, count 0 2006.169.07:31:26.58#ibcon#about to write, iclass 31, count 0 2006.169.07:31:26.58#ibcon#wrote, iclass 31, count 0 2006.169.07:31:26.58#ibcon#about to read 3, iclass 31, count 0 2006.169.07:31:26.62#ibcon#read 3, iclass 31, count 0 2006.169.07:31:26.62#ibcon#about to read 4, iclass 31, count 0 2006.169.07:31:26.62#ibcon#read 4, iclass 31, count 0 2006.169.07:31:26.62#ibcon#about to read 5, iclass 31, count 0 2006.169.07:31:26.62#ibcon#read 5, iclass 31, count 0 2006.169.07:31:26.62#ibcon#about to read 6, iclass 31, count 0 2006.169.07:31:26.62#ibcon#read 6, iclass 31, count 0 2006.169.07:31:26.62#ibcon#end of sib2, iclass 31, count 0 2006.169.07:31:26.62#ibcon#*after write, iclass 31, count 0 2006.169.07:31:26.62#ibcon#*before return 0, iclass 31, count 0 2006.169.07:31:26.62#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.169.07:31:26.62#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.169.07:31:26.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.169.07:31:26.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.169.07:31:26.62$vc4f8/va=6,6 2006.169.07:31:26.62#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.169.07:31:26.62#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.169.07:31:26.62#ibcon#ireg 11 cls_cnt 2 2006.169.07:31:26.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.169.07:31:26.68#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.169.07:31:26.68#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.169.07:31:26.68#ibcon#enter wrdev, iclass 33, count 2 2006.169.07:31:26.68#ibcon#first serial, iclass 33, count 2 2006.169.07:31:26.68#ibcon#enter sib2, iclass 33, count 2 2006.169.07:31:26.68#ibcon#flushed, iclass 33, count 2 2006.169.07:31:26.68#ibcon#about to write, iclass 33, count 2 2006.169.07:31:26.68#ibcon#wrote, iclass 33, count 2 2006.169.07:31:26.68#ibcon#about to read 3, iclass 33, count 2 2006.169.07:31:26.70#ibcon#read 3, iclass 33, count 2 2006.169.07:31:26.70#ibcon#about to read 4, iclass 33, count 2 2006.169.07:31:26.70#ibcon#read 4, iclass 33, count 2 2006.169.07:31:26.70#ibcon#about to read 5, iclass 33, count 2 2006.169.07:31:26.70#ibcon#read 5, iclass 33, count 2 2006.169.07:31:26.70#ibcon#about to read 6, iclass 33, count 2 2006.169.07:31:26.70#ibcon#read 6, iclass 33, count 2 2006.169.07:31:26.70#ibcon#end of sib2, iclass 33, count 2 2006.169.07:31:26.70#ibcon#*mode == 0, iclass 33, count 2 2006.169.07:31:26.70#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.169.07:31:26.70#ibcon#[25=AT06-06\r\n] 2006.169.07:31:26.70#ibcon#*before write, iclass 33, count 2 2006.169.07:31:26.70#ibcon#enter sib2, iclass 33, count 2 2006.169.07:31:26.70#ibcon#flushed, iclass 33, count 2 2006.169.07:31:26.70#ibcon#about to write, iclass 33, count 2 2006.169.07:31:26.70#ibcon#wrote, iclass 33, count 2 2006.169.07:31:26.70#ibcon#about to read 3, iclass 33, count 2 2006.169.07:31:26.73#ibcon#read 3, iclass 33, count 2 2006.169.07:31:26.73#ibcon#about to read 4, iclass 33, count 2 2006.169.07:31:26.73#ibcon#read 4, iclass 33, count 2 2006.169.07:31:26.73#ibcon#about to read 5, iclass 33, count 2 2006.169.07:31:26.73#ibcon#read 5, iclass 33, count 2 2006.169.07:31:26.73#ibcon#about to read 6, iclass 33, count 2 2006.169.07:31:26.73#ibcon#read 6, iclass 33, count 2 2006.169.07:31:26.73#ibcon#end of sib2, iclass 33, count 2 2006.169.07:31:26.73#ibcon#*after write, iclass 33, count 2 2006.169.07:31:26.73#ibcon#*before return 0, iclass 33, count 2 2006.169.07:31:26.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.169.07:31:26.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.169.07:31:26.73#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.169.07:31:26.73#ibcon#ireg 7 cls_cnt 0 2006.169.07:31:26.73#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.169.07:31:26.85#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.169.07:31:26.85#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.169.07:31:26.85#ibcon#enter wrdev, iclass 33, count 0 2006.169.07:31:26.85#ibcon#first serial, iclass 33, count 0 2006.169.07:31:26.85#ibcon#enter sib2, iclass 33, count 0 2006.169.07:31:26.85#ibcon#flushed, iclass 33, count 0 2006.169.07:31:26.85#ibcon#about to write, iclass 33, count 0 2006.169.07:31:26.85#ibcon#wrote, iclass 33, count 0 2006.169.07:31:26.85#ibcon#about to read 3, iclass 33, count 0 2006.169.07:31:26.87#ibcon#read 3, iclass 33, count 0 2006.169.07:31:26.87#ibcon#about to read 4, iclass 33, count 0 2006.169.07:31:26.87#ibcon#read 4, iclass 33, count 0 2006.169.07:31:26.87#ibcon#about to read 5, iclass 33, count 0 2006.169.07:31:26.87#ibcon#read 5, iclass 33, count 0 2006.169.07:31:26.87#ibcon#about to read 6, iclass 33, count 0 2006.169.07:31:26.87#ibcon#read 6, iclass 33, count 0 2006.169.07:31:26.87#ibcon#end of sib2, iclass 33, count 0 2006.169.07:31:26.87#ibcon#*mode == 0, iclass 33, count 0 2006.169.07:31:26.87#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.169.07:31:26.87#ibcon#[25=USB\r\n] 2006.169.07:31:26.87#ibcon#*before write, iclass 33, count 0 2006.169.07:31:26.87#ibcon#enter sib2, iclass 33, count 0 2006.169.07:31:26.87#ibcon#flushed, iclass 33, count 0 2006.169.07:31:26.87#ibcon#about to write, iclass 33, count 0 2006.169.07:31:26.87#ibcon#wrote, iclass 33, count 0 2006.169.07:31:26.87#ibcon#about to read 3, iclass 33, count 0 2006.169.07:31:26.90#ibcon#read 3, iclass 33, count 0 2006.169.07:31:26.90#ibcon#about to read 4, iclass 33, count 0 2006.169.07:31:26.90#ibcon#read 4, iclass 33, count 0 2006.169.07:31:26.90#ibcon#about to read 5, iclass 33, count 0 2006.169.07:31:26.90#ibcon#read 5, iclass 33, count 0 2006.169.07:31:26.90#ibcon#about to read 6, iclass 33, count 0 2006.169.07:31:26.90#ibcon#read 6, iclass 33, count 0 2006.169.07:31:26.90#ibcon#end of sib2, iclass 33, count 0 2006.169.07:31:26.90#ibcon#*after write, iclass 33, count 0 2006.169.07:31:26.90#ibcon#*before return 0, iclass 33, count 0 2006.169.07:31:26.90#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.169.07:31:26.90#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.169.07:31:26.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.169.07:31:26.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.169.07:31:26.90$vc4f8/valo=7,832.99 2006.169.07:31:26.90#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.169.07:31:26.90#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.169.07:31:26.90#ibcon#ireg 17 cls_cnt 0 2006.169.07:31:26.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.169.07:31:26.90#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.169.07:31:26.90#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.169.07:31:26.90#ibcon#enter wrdev, iclass 35, count 0 2006.169.07:31:26.90#ibcon#first serial, iclass 35, count 0 2006.169.07:31:26.90#ibcon#enter sib2, iclass 35, count 0 2006.169.07:31:26.90#ibcon#flushed, iclass 35, count 0 2006.169.07:31:26.90#ibcon#about to write, iclass 35, count 0 2006.169.07:31:26.90#ibcon#wrote, iclass 35, count 0 2006.169.07:31:26.90#ibcon#about to read 3, iclass 35, count 0 2006.169.07:31:26.92#ibcon#read 3, iclass 35, count 0 2006.169.07:31:26.92#ibcon#about to read 4, iclass 35, count 0 2006.169.07:31:26.92#ibcon#read 4, iclass 35, count 0 2006.169.07:31:26.92#ibcon#about to read 5, iclass 35, count 0 2006.169.07:31:26.92#ibcon#read 5, iclass 35, count 0 2006.169.07:31:26.92#ibcon#about to read 6, iclass 35, count 0 2006.169.07:31:26.92#ibcon#read 6, iclass 35, count 0 2006.169.07:31:26.92#ibcon#end of sib2, iclass 35, count 0 2006.169.07:31:26.92#ibcon#*mode == 0, iclass 35, count 0 2006.169.07:31:26.92#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.169.07:31:26.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.07:31:26.92#ibcon#*before write, iclass 35, count 0 2006.169.07:31:26.92#ibcon#enter sib2, iclass 35, count 0 2006.169.07:31:26.92#ibcon#flushed, iclass 35, count 0 2006.169.07:31:26.92#ibcon#about to write, iclass 35, count 0 2006.169.07:31:26.92#ibcon#wrote, iclass 35, count 0 2006.169.07:31:26.92#ibcon#about to read 3, iclass 35, count 0 2006.169.07:31:26.96#ibcon#read 3, iclass 35, count 0 2006.169.07:31:26.96#ibcon#about to read 4, iclass 35, count 0 2006.169.07:31:26.96#ibcon#read 4, iclass 35, count 0 2006.169.07:31:26.96#ibcon#about to read 5, iclass 35, count 0 2006.169.07:31:26.96#ibcon#read 5, iclass 35, count 0 2006.169.07:31:26.96#ibcon#about to read 6, iclass 35, count 0 2006.169.07:31:26.96#ibcon#read 6, iclass 35, count 0 2006.169.07:31:26.96#ibcon#end of sib2, iclass 35, count 0 2006.169.07:31:26.96#ibcon#*after write, iclass 35, count 0 2006.169.07:31:26.96#ibcon#*before return 0, iclass 35, count 0 2006.169.07:31:26.96#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.169.07:31:26.96#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.169.07:31:26.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.169.07:31:26.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.169.07:31:26.96$vc4f8/va=7,6 2006.169.07:31:26.96#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.169.07:31:26.96#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.169.07:31:26.96#ibcon#ireg 11 cls_cnt 2 2006.169.07:31:26.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.169.07:31:27.02#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.169.07:31:27.02#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.169.07:31:27.02#ibcon#enter wrdev, iclass 37, count 2 2006.169.07:31:27.02#ibcon#first serial, iclass 37, count 2 2006.169.07:31:27.02#ibcon#enter sib2, iclass 37, count 2 2006.169.07:31:27.02#ibcon#flushed, iclass 37, count 2 2006.169.07:31:27.02#ibcon#about to write, iclass 37, count 2 2006.169.07:31:27.02#ibcon#wrote, iclass 37, count 2 2006.169.07:31:27.02#ibcon#about to read 3, iclass 37, count 2 2006.169.07:31:27.04#ibcon#read 3, iclass 37, count 2 2006.169.07:31:27.04#ibcon#about to read 4, iclass 37, count 2 2006.169.07:31:27.04#ibcon#read 4, iclass 37, count 2 2006.169.07:31:27.04#ibcon#about to read 5, iclass 37, count 2 2006.169.07:31:27.04#ibcon#read 5, iclass 37, count 2 2006.169.07:31:27.04#ibcon#about to read 6, iclass 37, count 2 2006.169.07:31:27.04#ibcon#read 6, iclass 37, count 2 2006.169.07:31:27.04#ibcon#end of sib2, iclass 37, count 2 2006.169.07:31:27.04#ibcon#*mode == 0, iclass 37, count 2 2006.169.07:31:27.04#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.169.07:31:27.04#ibcon#[25=AT07-06\r\n] 2006.169.07:31:27.04#ibcon#*before write, iclass 37, count 2 2006.169.07:31:27.04#ibcon#enter sib2, iclass 37, count 2 2006.169.07:31:27.04#ibcon#flushed, iclass 37, count 2 2006.169.07:31:27.04#ibcon#about to write, iclass 37, count 2 2006.169.07:31:27.04#ibcon#wrote, iclass 37, count 2 2006.169.07:31:27.04#ibcon#about to read 3, iclass 37, count 2 2006.169.07:31:27.07#ibcon#read 3, iclass 37, count 2 2006.169.07:31:27.07#ibcon#about to read 4, iclass 37, count 2 2006.169.07:31:27.07#ibcon#read 4, iclass 37, count 2 2006.169.07:31:27.07#ibcon#about to read 5, iclass 37, count 2 2006.169.07:31:27.07#ibcon#read 5, iclass 37, count 2 2006.169.07:31:27.07#ibcon#about to read 6, iclass 37, count 2 2006.169.07:31:27.07#ibcon#read 6, iclass 37, count 2 2006.169.07:31:27.07#ibcon#end of sib2, iclass 37, count 2 2006.169.07:31:27.07#ibcon#*after write, iclass 37, count 2 2006.169.07:31:27.07#ibcon#*before return 0, iclass 37, count 2 2006.169.07:31:27.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.169.07:31:27.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.169.07:31:27.07#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.169.07:31:27.07#ibcon#ireg 7 cls_cnt 0 2006.169.07:31:27.07#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.169.07:31:27.19#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.169.07:31:27.19#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.169.07:31:27.19#ibcon#enter wrdev, iclass 37, count 0 2006.169.07:31:27.19#ibcon#first serial, iclass 37, count 0 2006.169.07:31:27.19#ibcon#enter sib2, iclass 37, count 0 2006.169.07:31:27.19#ibcon#flushed, iclass 37, count 0 2006.169.07:31:27.19#ibcon#about to write, iclass 37, count 0 2006.169.07:31:27.19#ibcon#wrote, iclass 37, count 0 2006.169.07:31:27.19#ibcon#about to read 3, iclass 37, count 0 2006.169.07:31:27.21#ibcon#read 3, iclass 37, count 0 2006.169.07:31:27.21#ibcon#about to read 4, iclass 37, count 0 2006.169.07:31:27.21#ibcon#read 4, iclass 37, count 0 2006.169.07:31:27.21#ibcon#about to read 5, iclass 37, count 0 2006.169.07:31:27.21#ibcon#read 5, iclass 37, count 0 2006.169.07:31:27.21#ibcon#about to read 6, iclass 37, count 0 2006.169.07:31:27.21#ibcon#read 6, iclass 37, count 0 2006.169.07:31:27.21#ibcon#end of sib2, iclass 37, count 0 2006.169.07:31:27.21#ibcon#*mode == 0, iclass 37, count 0 2006.169.07:31:27.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.169.07:31:27.21#ibcon#[25=USB\r\n] 2006.169.07:31:27.21#ibcon#*before write, iclass 37, count 0 2006.169.07:31:27.21#ibcon#enter sib2, iclass 37, count 0 2006.169.07:31:27.21#ibcon#flushed, iclass 37, count 0 2006.169.07:31:27.21#ibcon#about to write, iclass 37, count 0 2006.169.07:31:27.21#ibcon#wrote, iclass 37, count 0 2006.169.07:31:27.21#ibcon#about to read 3, iclass 37, count 0 2006.169.07:31:27.25#ibcon#read 3, iclass 37, count 0 2006.169.07:31:27.25#ibcon#about to read 4, iclass 37, count 0 2006.169.07:31:27.25#ibcon#read 4, iclass 37, count 0 2006.169.07:31:27.25#ibcon#about to read 5, iclass 37, count 0 2006.169.07:31:27.25#ibcon#read 5, iclass 37, count 0 2006.169.07:31:27.25#ibcon#about to read 6, iclass 37, count 0 2006.169.07:31:27.25#ibcon#read 6, iclass 37, count 0 2006.169.07:31:27.25#ibcon#end of sib2, iclass 37, count 0 2006.169.07:31:27.25#ibcon#*after write, iclass 37, count 0 2006.169.07:31:27.25#ibcon#*before return 0, iclass 37, count 0 2006.169.07:31:27.25#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.169.07:31:27.25#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.169.07:31:27.25#ibcon#about to clear, iclass 37 cls_cnt 0 2006.169.07:31:27.25#ibcon#cleared, iclass 37 cls_cnt 0 2006.169.07:31:27.25$vc4f8/valo=8,852.99 2006.169.07:31:27.25#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.169.07:31:27.25#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.169.07:31:27.25#ibcon#ireg 17 cls_cnt 0 2006.169.07:31:27.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.169.07:31:27.25#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.169.07:31:27.25#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.169.07:31:27.25#ibcon#enter wrdev, iclass 39, count 0 2006.169.07:31:27.25#ibcon#first serial, iclass 39, count 0 2006.169.07:31:27.25#ibcon#enter sib2, iclass 39, count 0 2006.169.07:31:27.25#ibcon#flushed, iclass 39, count 0 2006.169.07:31:27.25#ibcon#about to write, iclass 39, count 0 2006.169.07:31:27.25#ibcon#wrote, iclass 39, count 0 2006.169.07:31:27.25#ibcon#about to read 3, iclass 39, count 0 2006.169.07:31:27.26#ibcon#read 3, iclass 39, count 0 2006.169.07:31:27.26#ibcon#about to read 4, iclass 39, count 0 2006.169.07:31:27.26#ibcon#read 4, iclass 39, count 0 2006.169.07:31:27.26#ibcon#about to read 5, iclass 39, count 0 2006.169.07:31:27.26#ibcon#read 5, iclass 39, count 0 2006.169.07:31:27.26#ibcon#about to read 6, iclass 39, count 0 2006.169.07:31:27.26#ibcon#read 6, iclass 39, count 0 2006.169.07:31:27.26#ibcon#end of sib2, iclass 39, count 0 2006.169.07:31:27.26#ibcon#*mode == 0, iclass 39, count 0 2006.169.07:31:27.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.169.07:31:27.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.07:31:27.26#ibcon#*before write, iclass 39, count 0 2006.169.07:31:27.26#ibcon#enter sib2, iclass 39, count 0 2006.169.07:31:27.26#ibcon#flushed, iclass 39, count 0 2006.169.07:31:27.26#ibcon#about to write, iclass 39, count 0 2006.169.07:31:27.26#ibcon#wrote, iclass 39, count 0 2006.169.07:31:27.26#ibcon#about to read 3, iclass 39, count 0 2006.169.07:31:27.30#ibcon#read 3, iclass 39, count 0 2006.169.07:31:27.30#ibcon#about to read 4, iclass 39, count 0 2006.169.07:31:27.30#ibcon#read 4, iclass 39, count 0 2006.169.07:31:27.30#ibcon#about to read 5, iclass 39, count 0 2006.169.07:31:27.30#ibcon#read 5, iclass 39, count 0 2006.169.07:31:27.30#ibcon#about to read 6, iclass 39, count 0 2006.169.07:31:27.30#ibcon#read 6, iclass 39, count 0 2006.169.07:31:27.30#ibcon#end of sib2, iclass 39, count 0 2006.169.07:31:27.30#ibcon#*after write, iclass 39, count 0 2006.169.07:31:27.30#ibcon#*before return 0, iclass 39, count 0 2006.169.07:31:27.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.169.07:31:27.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.169.07:31:27.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.169.07:31:27.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.169.07:31:27.30$vc4f8/va=8,7 2006.169.07:31:27.30#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.169.07:31:27.30#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.169.07:31:27.30#ibcon#ireg 11 cls_cnt 2 2006.169.07:31:27.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.169.07:31:27.37#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.169.07:31:27.37#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.169.07:31:27.37#ibcon#enter wrdev, iclass 3, count 2 2006.169.07:31:27.37#ibcon#first serial, iclass 3, count 2 2006.169.07:31:27.37#ibcon#enter sib2, iclass 3, count 2 2006.169.07:31:27.37#ibcon#flushed, iclass 3, count 2 2006.169.07:31:27.37#ibcon#about to write, iclass 3, count 2 2006.169.07:31:27.37#ibcon#wrote, iclass 3, count 2 2006.169.07:31:27.37#ibcon#about to read 3, iclass 3, count 2 2006.169.07:31:27.39#ibcon#read 3, iclass 3, count 2 2006.169.07:31:27.39#ibcon#about to read 4, iclass 3, count 2 2006.169.07:31:27.39#ibcon#read 4, iclass 3, count 2 2006.169.07:31:27.39#ibcon#about to read 5, iclass 3, count 2 2006.169.07:31:27.39#ibcon#read 5, iclass 3, count 2 2006.169.07:31:27.39#ibcon#about to read 6, iclass 3, count 2 2006.169.07:31:27.39#ibcon#read 6, iclass 3, count 2 2006.169.07:31:27.39#ibcon#end of sib2, iclass 3, count 2 2006.169.07:31:27.39#ibcon#*mode == 0, iclass 3, count 2 2006.169.07:31:27.39#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.169.07:31:27.39#ibcon#[25=AT08-07\r\n] 2006.169.07:31:27.39#ibcon#*before write, iclass 3, count 2 2006.169.07:31:27.39#ibcon#enter sib2, iclass 3, count 2 2006.169.07:31:27.39#ibcon#flushed, iclass 3, count 2 2006.169.07:31:27.39#ibcon#about to write, iclass 3, count 2 2006.169.07:31:27.39#ibcon#wrote, iclass 3, count 2 2006.169.07:31:27.39#ibcon#about to read 3, iclass 3, count 2 2006.169.07:31:27.42#ibcon#read 3, iclass 3, count 2 2006.169.07:31:27.42#ibcon#about to read 4, iclass 3, count 2 2006.169.07:31:27.42#ibcon#read 4, iclass 3, count 2 2006.169.07:31:27.42#ibcon#about to read 5, iclass 3, count 2 2006.169.07:31:27.42#ibcon#read 5, iclass 3, count 2 2006.169.07:31:27.42#ibcon#about to read 6, iclass 3, count 2 2006.169.07:31:27.42#ibcon#read 6, iclass 3, count 2 2006.169.07:31:27.42#ibcon#end of sib2, iclass 3, count 2 2006.169.07:31:27.42#ibcon#*after write, iclass 3, count 2 2006.169.07:31:27.42#ibcon#*before return 0, iclass 3, count 2 2006.169.07:31:27.42#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.169.07:31:27.42#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.169.07:31:27.42#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.169.07:31:27.42#ibcon#ireg 7 cls_cnt 0 2006.169.07:31:27.42#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.169.07:31:27.54#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.169.07:31:27.54#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.169.07:31:27.54#ibcon#enter wrdev, iclass 3, count 0 2006.169.07:31:27.54#ibcon#first serial, iclass 3, count 0 2006.169.07:31:27.54#ibcon#enter sib2, iclass 3, count 0 2006.169.07:31:27.54#ibcon#flushed, iclass 3, count 0 2006.169.07:31:27.54#ibcon#about to write, iclass 3, count 0 2006.169.07:31:27.54#ibcon#wrote, iclass 3, count 0 2006.169.07:31:27.54#ibcon#about to read 3, iclass 3, count 0 2006.169.07:31:27.56#ibcon#read 3, iclass 3, count 0 2006.169.07:31:27.56#ibcon#about to read 4, iclass 3, count 0 2006.169.07:31:27.56#ibcon#read 4, iclass 3, count 0 2006.169.07:31:27.56#ibcon#about to read 5, iclass 3, count 0 2006.169.07:31:27.56#ibcon#read 5, iclass 3, count 0 2006.169.07:31:27.56#ibcon#about to read 6, iclass 3, count 0 2006.169.07:31:27.56#ibcon#read 6, iclass 3, count 0 2006.169.07:31:27.56#ibcon#end of sib2, iclass 3, count 0 2006.169.07:31:27.56#ibcon#*mode == 0, iclass 3, count 0 2006.169.07:31:27.56#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.169.07:31:27.56#ibcon#[25=USB\r\n] 2006.169.07:31:27.56#ibcon#*before write, iclass 3, count 0 2006.169.07:31:27.56#ibcon#enter sib2, iclass 3, count 0 2006.169.07:31:27.56#ibcon#flushed, iclass 3, count 0 2006.169.07:31:27.56#ibcon#about to write, iclass 3, count 0 2006.169.07:31:27.56#ibcon#wrote, iclass 3, count 0 2006.169.07:31:27.56#ibcon#about to read 3, iclass 3, count 0 2006.169.07:31:27.59#ibcon#read 3, iclass 3, count 0 2006.169.07:31:27.59#ibcon#about to read 4, iclass 3, count 0 2006.169.07:31:27.59#ibcon#read 4, iclass 3, count 0 2006.169.07:31:27.59#ibcon#about to read 5, iclass 3, count 0 2006.169.07:31:27.59#ibcon#read 5, iclass 3, count 0 2006.169.07:31:27.59#ibcon#about to read 6, iclass 3, count 0 2006.169.07:31:27.59#ibcon#read 6, iclass 3, count 0 2006.169.07:31:27.59#ibcon#end of sib2, iclass 3, count 0 2006.169.07:31:27.59#ibcon#*after write, iclass 3, count 0 2006.169.07:31:27.59#ibcon#*before return 0, iclass 3, count 0 2006.169.07:31:27.59#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.169.07:31:27.59#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.169.07:31:27.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.169.07:31:27.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.169.07:31:27.59$vc4f8/vblo=1,632.99 2006.169.07:31:27.59#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.169.07:31:27.59#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.169.07:31:27.59#ibcon#ireg 17 cls_cnt 0 2006.169.07:31:27.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:31:27.59#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:31:27.59#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:31:27.59#ibcon#enter wrdev, iclass 5, count 0 2006.169.07:31:27.59#ibcon#first serial, iclass 5, count 0 2006.169.07:31:27.59#ibcon#enter sib2, iclass 5, count 0 2006.169.07:31:27.59#ibcon#flushed, iclass 5, count 0 2006.169.07:31:27.59#ibcon#about to write, iclass 5, count 0 2006.169.07:31:27.59#ibcon#wrote, iclass 5, count 0 2006.169.07:31:27.59#ibcon#about to read 3, iclass 5, count 0 2006.169.07:31:27.61#ibcon#read 3, iclass 5, count 0 2006.169.07:31:27.61#ibcon#about to read 4, iclass 5, count 0 2006.169.07:31:27.61#ibcon#read 4, iclass 5, count 0 2006.169.07:31:27.61#ibcon#about to read 5, iclass 5, count 0 2006.169.07:31:27.61#ibcon#read 5, iclass 5, count 0 2006.169.07:31:27.61#ibcon#about to read 6, iclass 5, count 0 2006.169.07:31:27.61#ibcon#read 6, iclass 5, count 0 2006.169.07:31:27.61#ibcon#end of sib2, iclass 5, count 0 2006.169.07:31:27.61#ibcon#*mode == 0, iclass 5, count 0 2006.169.07:31:27.61#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.169.07:31:27.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.07:31:27.61#ibcon#*before write, iclass 5, count 0 2006.169.07:31:27.61#ibcon#enter sib2, iclass 5, count 0 2006.169.07:31:27.61#ibcon#flushed, iclass 5, count 0 2006.169.07:31:27.61#ibcon#about to write, iclass 5, count 0 2006.169.07:31:27.61#ibcon#wrote, iclass 5, count 0 2006.169.07:31:27.61#ibcon#about to read 3, iclass 5, count 0 2006.169.07:31:27.65#ibcon#read 3, iclass 5, count 0 2006.169.07:31:27.65#ibcon#about to read 4, iclass 5, count 0 2006.169.07:31:27.65#ibcon#read 4, iclass 5, count 0 2006.169.07:31:27.65#ibcon#about to read 5, iclass 5, count 0 2006.169.07:31:27.65#ibcon#read 5, iclass 5, count 0 2006.169.07:31:27.65#ibcon#about to read 6, iclass 5, count 0 2006.169.07:31:27.65#ibcon#read 6, iclass 5, count 0 2006.169.07:31:27.65#ibcon#end of sib2, iclass 5, count 0 2006.169.07:31:27.65#ibcon#*after write, iclass 5, count 0 2006.169.07:31:27.65#ibcon#*before return 0, iclass 5, count 0 2006.169.07:31:27.65#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:31:27.65#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:31:27.65#ibcon#about to clear, iclass 5 cls_cnt 0 2006.169.07:31:27.65#ibcon#cleared, iclass 5 cls_cnt 0 2006.169.07:31:27.65$vc4f8/vb=1,4 2006.169.07:31:27.65#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.169.07:31:27.65#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.169.07:31:27.65#ibcon#ireg 11 cls_cnt 2 2006.169.07:31:27.65#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:31:27.65#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:31:27.65#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:31:27.65#ibcon#enter wrdev, iclass 7, count 2 2006.169.07:31:27.65#ibcon#first serial, iclass 7, count 2 2006.169.07:31:27.65#ibcon#enter sib2, iclass 7, count 2 2006.169.07:31:27.65#ibcon#flushed, iclass 7, count 2 2006.169.07:31:27.65#ibcon#about to write, iclass 7, count 2 2006.169.07:31:27.65#ibcon#wrote, iclass 7, count 2 2006.169.07:31:27.65#ibcon#about to read 3, iclass 7, count 2 2006.169.07:31:27.67#ibcon#read 3, iclass 7, count 2 2006.169.07:31:27.67#ibcon#about to read 4, iclass 7, count 2 2006.169.07:31:27.67#ibcon#read 4, iclass 7, count 2 2006.169.07:31:27.67#ibcon#about to read 5, iclass 7, count 2 2006.169.07:31:27.67#ibcon#read 5, iclass 7, count 2 2006.169.07:31:27.67#ibcon#about to read 6, iclass 7, count 2 2006.169.07:31:27.67#ibcon#read 6, iclass 7, count 2 2006.169.07:31:27.67#ibcon#end of sib2, iclass 7, count 2 2006.169.07:31:27.67#ibcon#*mode == 0, iclass 7, count 2 2006.169.07:31:27.67#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.169.07:31:27.67#ibcon#[27=AT01-04\r\n] 2006.169.07:31:27.67#ibcon#*before write, iclass 7, count 2 2006.169.07:31:27.67#ibcon#enter sib2, iclass 7, count 2 2006.169.07:31:27.67#ibcon#flushed, iclass 7, count 2 2006.169.07:31:27.67#ibcon#about to write, iclass 7, count 2 2006.169.07:31:27.67#ibcon#wrote, iclass 7, count 2 2006.169.07:31:27.67#ibcon#about to read 3, iclass 7, count 2 2006.169.07:31:27.70#ibcon#read 3, iclass 7, count 2 2006.169.07:31:27.70#ibcon#about to read 4, iclass 7, count 2 2006.169.07:31:27.70#ibcon#read 4, iclass 7, count 2 2006.169.07:31:27.70#ibcon#about to read 5, iclass 7, count 2 2006.169.07:31:27.70#ibcon#read 5, iclass 7, count 2 2006.169.07:31:27.70#ibcon#about to read 6, iclass 7, count 2 2006.169.07:31:27.70#ibcon#read 6, iclass 7, count 2 2006.169.07:31:27.70#ibcon#end of sib2, iclass 7, count 2 2006.169.07:31:27.70#ibcon#*after write, iclass 7, count 2 2006.169.07:31:27.70#ibcon#*before return 0, iclass 7, count 2 2006.169.07:31:27.70#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:31:27.70#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:31:27.70#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.169.07:31:27.70#ibcon#ireg 7 cls_cnt 0 2006.169.07:31:27.70#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:31:27.82#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:31:27.82#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:31:27.82#ibcon#enter wrdev, iclass 7, count 0 2006.169.07:31:27.82#ibcon#first serial, iclass 7, count 0 2006.169.07:31:27.82#ibcon#enter sib2, iclass 7, count 0 2006.169.07:31:27.82#ibcon#flushed, iclass 7, count 0 2006.169.07:31:27.82#ibcon#about to write, iclass 7, count 0 2006.169.07:31:27.82#ibcon#wrote, iclass 7, count 0 2006.169.07:31:27.82#ibcon#about to read 3, iclass 7, count 0 2006.169.07:31:27.84#ibcon#read 3, iclass 7, count 0 2006.169.07:31:27.84#ibcon#about to read 4, iclass 7, count 0 2006.169.07:31:27.84#ibcon#read 4, iclass 7, count 0 2006.169.07:31:27.84#ibcon#about to read 5, iclass 7, count 0 2006.169.07:31:27.84#ibcon#read 5, iclass 7, count 0 2006.169.07:31:27.84#ibcon#about to read 6, iclass 7, count 0 2006.169.07:31:27.84#ibcon#read 6, iclass 7, count 0 2006.169.07:31:27.84#ibcon#end of sib2, iclass 7, count 0 2006.169.07:31:27.84#ibcon#*mode == 0, iclass 7, count 0 2006.169.07:31:27.84#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.169.07:31:27.84#ibcon#[27=USB\r\n] 2006.169.07:31:27.84#ibcon#*before write, iclass 7, count 0 2006.169.07:31:27.84#ibcon#enter sib2, iclass 7, count 0 2006.169.07:31:27.84#ibcon#flushed, iclass 7, count 0 2006.169.07:31:27.84#ibcon#about to write, iclass 7, count 0 2006.169.07:31:27.84#ibcon#wrote, iclass 7, count 0 2006.169.07:31:27.84#ibcon#about to read 3, iclass 7, count 0 2006.169.07:31:27.87#ibcon#read 3, iclass 7, count 0 2006.169.07:31:27.87#ibcon#about to read 4, iclass 7, count 0 2006.169.07:31:27.87#ibcon#read 4, iclass 7, count 0 2006.169.07:31:27.87#ibcon#about to read 5, iclass 7, count 0 2006.169.07:31:27.87#ibcon#read 5, iclass 7, count 0 2006.169.07:31:27.87#ibcon#about to read 6, iclass 7, count 0 2006.169.07:31:27.87#ibcon#read 6, iclass 7, count 0 2006.169.07:31:27.87#ibcon#end of sib2, iclass 7, count 0 2006.169.07:31:27.87#ibcon#*after write, iclass 7, count 0 2006.169.07:31:27.87#ibcon#*before return 0, iclass 7, count 0 2006.169.07:31:27.87#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:31:27.87#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:31:27.87#ibcon#about to clear, iclass 7 cls_cnt 0 2006.169.07:31:27.87#ibcon#cleared, iclass 7 cls_cnt 0 2006.169.07:31:27.87$vc4f8/vblo=2,640.99 2006.169.07:31:27.87#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.169.07:31:27.87#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.169.07:31:27.87#ibcon#ireg 17 cls_cnt 0 2006.169.07:31:27.87#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.169.07:31:27.87#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.169.07:31:27.87#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.169.07:31:27.87#ibcon#enter wrdev, iclass 11, count 0 2006.169.07:31:27.87#ibcon#first serial, iclass 11, count 0 2006.169.07:31:27.87#ibcon#enter sib2, iclass 11, count 0 2006.169.07:31:27.87#ibcon#flushed, iclass 11, count 0 2006.169.07:31:27.87#ibcon#about to write, iclass 11, count 0 2006.169.07:31:27.87#ibcon#wrote, iclass 11, count 0 2006.169.07:31:27.87#ibcon#about to read 3, iclass 11, count 0 2006.169.07:31:27.89#ibcon#read 3, iclass 11, count 0 2006.169.07:31:27.89#ibcon#about to read 4, iclass 11, count 0 2006.169.07:31:27.89#ibcon#read 4, iclass 11, count 0 2006.169.07:31:27.89#ibcon#about to read 5, iclass 11, count 0 2006.169.07:31:27.89#ibcon#read 5, iclass 11, count 0 2006.169.07:31:27.89#ibcon#about to read 6, iclass 11, count 0 2006.169.07:31:27.89#ibcon#read 6, iclass 11, count 0 2006.169.07:31:27.89#ibcon#end of sib2, iclass 11, count 0 2006.169.07:31:27.89#ibcon#*mode == 0, iclass 11, count 0 2006.169.07:31:27.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.169.07:31:27.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.07:31:27.89#ibcon#*before write, iclass 11, count 0 2006.169.07:31:27.89#ibcon#enter sib2, iclass 11, count 0 2006.169.07:31:27.89#ibcon#flushed, iclass 11, count 0 2006.169.07:31:27.89#ibcon#about to write, iclass 11, count 0 2006.169.07:31:27.89#ibcon#wrote, iclass 11, count 0 2006.169.07:31:27.89#ibcon#about to read 3, iclass 11, count 0 2006.169.07:31:27.93#ibcon#read 3, iclass 11, count 0 2006.169.07:31:27.93#ibcon#about to read 4, iclass 11, count 0 2006.169.07:31:27.93#ibcon#read 4, iclass 11, count 0 2006.169.07:31:27.93#ibcon#about to read 5, iclass 11, count 0 2006.169.07:31:27.93#ibcon#read 5, iclass 11, count 0 2006.169.07:31:27.93#ibcon#about to read 6, iclass 11, count 0 2006.169.07:31:27.93#ibcon#read 6, iclass 11, count 0 2006.169.07:31:27.93#ibcon#end of sib2, iclass 11, count 0 2006.169.07:31:27.93#ibcon#*after write, iclass 11, count 0 2006.169.07:31:27.93#ibcon#*before return 0, iclass 11, count 0 2006.169.07:31:27.93#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.169.07:31:27.93#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.169.07:31:27.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.169.07:31:27.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.169.07:31:27.93$vc4f8/vb=2,4 2006.169.07:31:27.93#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.169.07:31:27.93#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.169.07:31:27.93#ibcon#ireg 11 cls_cnt 2 2006.169.07:31:27.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.169.07:31:27.99#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.169.07:31:27.99#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.169.07:31:27.99#ibcon#enter wrdev, iclass 13, count 2 2006.169.07:31:27.99#ibcon#first serial, iclass 13, count 2 2006.169.07:31:27.99#ibcon#enter sib2, iclass 13, count 2 2006.169.07:31:27.99#ibcon#flushed, iclass 13, count 2 2006.169.07:31:27.99#ibcon#about to write, iclass 13, count 2 2006.169.07:31:27.99#ibcon#wrote, iclass 13, count 2 2006.169.07:31:27.99#ibcon#about to read 3, iclass 13, count 2 2006.169.07:31:28.01#ibcon#read 3, iclass 13, count 2 2006.169.07:31:28.01#ibcon#about to read 4, iclass 13, count 2 2006.169.07:31:28.01#ibcon#read 4, iclass 13, count 2 2006.169.07:31:28.01#ibcon#about to read 5, iclass 13, count 2 2006.169.07:31:28.01#ibcon#read 5, iclass 13, count 2 2006.169.07:31:28.01#ibcon#about to read 6, iclass 13, count 2 2006.169.07:31:28.01#ibcon#read 6, iclass 13, count 2 2006.169.07:31:28.01#ibcon#end of sib2, iclass 13, count 2 2006.169.07:31:28.01#ibcon#*mode == 0, iclass 13, count 2 2006.169.07:31:28.01#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.169.07:31:28.01#ibcon#[27=AT02-04\r\n] 2006.169.07:31:28.01#ibcon#*before write, iclass 13, count 2 2006.169.07:31:28.01#ibcon#enter sib2, iclass 13, count 2 2006.169.07:31:28.01#ibcon#flushed, iclass 13, count 2 2006.169.07:31:28.01#ibcon#about to write, iclass 13, count 2 2006.169.07:31:28.01#ibcon#wrote, iclass 13, count 2 2006.169.07:31:28.01#ibcon#about to read 3, iclass 13, count 2 2006.169.07:31:28.04#ibcon#read 3, iclass 13, count 2 2006.169.07:31:28.04#ibcon#about to read 4, iclass 13, count 2 2006.169.07:31:28.04#ibcon#read 4, iclass 13, count 2 2006.169.07:31:28.04#ibcon#about to read 5, iclass 13, count 2 2006.169.07:31:28.04#ibcon#read 5, iclass 13, count 2 2006.169.07:31:28.04#ibcon#about to read 6, iclass 13, count 2 2006.169.07:31:28.04#ibcon#read 6, iclass 13, count 2 2006.169.07:31:28.04#ibcon#end of sib2, iclass 13, count 2 2006.169.07:31:28.04#ibcon#*after write, iclass 13, count 2 2006.169.07:31:28.04#ibcon#*before return 0, iclass 13, count 2 2006.169.07:31:28.04#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.169.07:31:28.04#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.169.07:31:28.04#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.169.07:31:28.04#ibcon#ireg 7 cls_cnt 0 2006.169.07:31:28.04#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.169.07:31:28.16#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.169.07:31:28.16#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.169.07:31:28.16#ibcon#enter wrdev, iclass 13, count 0 2006.169.07:31:28.16#ibcon#first serial, iclass 13, count 0 2006.169.07:31:28.16#ibcon#enter sib2, iclass 13, count 0 2006.169.07:31:28.16#ibcon#flushed, iclass 13, count 0 2006.169.07:31:28.16#ibcon#about to write, iclass 13, count 0 2006.169.07:31:28.16#ibcon#wrote, iclass 13, count 0 2006.169.07:31:28.16#ibcon#about to read 3, iclass 13, count 0 2006.169.07:31:28.18#ibcon#read 3, iclass 13, count 0 2006.169.07:31:28.18#ibcon#about to read 4, iclass 13, count 0 2006.169.07:31:28.18#ibcon#read 4, iclass 13, count 0 2006.169.07:31:28.18#ibcon#about to read 5, iclass 13, count 0 2006.169.07:31:28.18#ibcon#read 5, iclass 13, count 0 2006.169.07:31:28.18#ibcon#about to read 6, iclass 13, count 0 2006.169.07:31:28.18#ibcon#read 6, iclass 13, count 0 2006.169.07:31:28.18#ibcon#end of sib2, iclass 13, count 0 2006.169.07:31:28.18#ibcon#*mode == 0, iclass 13, count 0 2006.169.07:31:28.18#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.07:31:28.18#ibcon#[27=USB\r\n] 2006.169.07:31:28.18#ibcon#*before write, iclass 13, count 0 2006.169.07:31:28.18#ibcon#enter sib2, iclass 13, count 0 2006.169.07:31:28.18#ibcon#flushed, iclass 13, count 0 2006.169.07:31:28.18#ibcon#about to write, iclass 13, count 0 2006.169.07:31:28.18#ibcon#wrote, iclass 13, count 0 2006.169.07:31:28.18#ibcon#about to read 3, iclass 13, count 0 2006.169.07:31:28.21#ibcon#read 3, iclass 13, count 0 2006.169.07:31:28.21#ibcon#about to read 4, iclass 13, count 0 2006.169.07:31:28.21#ibcon#read 4, iclass 13, count 0 2006.169.07:31:28.21#ibcon#about to read 5, iclass 13, count 0 2006.169.07:31:28.21#ibcon#read 5, iclass 13, count 0 2006.169.07:31:28.21#ibcon#about to read 6, iclass 13, count 0 2006.169.07:31:28.21#ibcon#read 6, iclass 13, count 0 2006.169.07:31:28.21#ibcon#end of sib2, iclass 13, count 0 2006.169.07:31:28.21#ibcon#*after write, iclass 13, count 0 2006.169.07:31:28.21#ibcon#*before return 0, iclass 13, count 0 2006.169.07:31:28.21#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.169.07:31:28.21#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.169.07:31:28.21#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.07:31:28.21#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.07:31:28.21$vc4f8/vblo=3,656.99 2006.169.07:31:28.21#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.169.07:31:28.21#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.169.07:31:28.21#ibcon#ireg 17 cls_cnt 0 2006.169.07:31:28.21#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:31:28.21#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:31:28.21#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:31:28.21#ibcon#enter wrdev, iclass 15, count 0 2006.169.07:31:28.21#ibcon#first serial, iclass 15, count 0 2006.169.07:31:28.21#ibcon#enter sib2, iclass 15, count 0 2006.169.07:31:28.21#ibcon#flushed, iclass 15, count 0 2006.169.07:31:28.21#ibcon#about to write, iclass 15, count 0 2006.169.07:31:28.21#ibcon#wrote, iclass 15, count 0 2006.169.07:31:28.21#ibcon#about to read 3, iclass 15, count 0 2006.169.07:31:28.23#ibcon#read 3, iclass 15, count 0 2006.169.07:31:28.23#ibcon#about to read 4, iclass 15, count 0 2006.169.07:31:28.23#ibcon#read 4, iclass 15, count 0 2006.169.07:31:28.23#ibcon#about to read 5, iclass 15, count 0 2006.169.07:31:28.23#ibcon#read 5, iclass 15, count 0 2006.169.07:31:28.23#ibcon#about to read 6, iclass 15, count 0 2006.169.07:31:28.23#ibcon#read 6, iclass 15, count 0 2006.169.07:31:28.23#ibcon#end of sib2, iclass 15, count 0 2006.169.07:31:28.23#ibcon#*mode == 0, iclass 15, count 0 2006.169.07:31:28.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.169.07:31:28.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.07:31:28.23#ibcon#*before write, iclass 15, count 0 2006.169.07:31:28.23#ibcon#enter sib2, iclass 15, count 0 2006.169.07:31:28.23#ibcon#flushed, iclass 15, count 0 2006.169.07:31:28.23#ibcon#about to write, iclass 15, count 0 2006.169.07:31:28.23#ibcon#wrote, iclass 15, count 0 2006.169.07:31:28.23#ibcon#about to read 3, iclass 15, count 0 2006.169.07:31:28.27#ibcon#read 3, iclass 15, count 0 2006.169.07:31:28.27#ibcon#about to read 4, iclass 15, count 0 2006.169.07:31:28.27#ibcon#read 4, iclass 15, count 0 2006.169.07:31:28.27#ibcon#about to read 5, iclass 15, count 0 2006.169.07:31:28.27#ibcon#read 5, iclass 15, count 0 2006.169.07:31:28.27#ibcon#about to read 6, iclass 15, count 0 2006.169.07:31:28.27#ibcon#read 6, iclass 15, count 0 2006.169.07:31:28.27#ibcon#end of sib2, iclass 15, count 0 2006.169.07:31:28.27#ibcon#*after write, iclass 15, count 0 2006.169.07:31:28.27#ibcon#*before return 0, iclass 15, count 0 2006.169.07:31:28.27#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:31:28.27#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:31:28.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.169.07:31:28.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.169.07:31:28.27$vc4f8/vb=3,4 2006.169.07:31:28.27#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.169.07:31:28.27#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.169.07:31:28.27#ibcon#ireg 11 cls_cnt 2 2006.169.07:31:28.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.169.07:31:28.33#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.169.07:31:28.33#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.169.07:31:28.33#ibcon#enter wrdev, iclass 17, count 2 2006.169.07:31:28.33#ibcon#first serial, iclass 17, count 2 2006.169.07:31:28.33#ibcon#enter sib2, iclass 17, count 2 2006.169.07:31:28.33#ibcon#flushed, iclass 17, count 2 2006.169.07:31:28.33#ibcon#about to write, iclass 17, count 2 2006.169.07:31:28.33#ibcon#wrote, iclass 17, count 2 2006.169.07:31:28.33#ibcon#about to read 3, iclass 17, count 2 2006.169.07:31:28.35#ibcon#read 3, iclass 17, count 2 2006.169.07:31:28.35#ibcon#about to read 4, iclass 17, count 2 2006.169.07:31:28.35#ibcon#read 4, iclass 17, count 2 2006.169.07:31:28.35#ibcon#about to read 5, iclass 17, count 2 2006.169.07:31:28.35#ibcon#read 5, iclass 17, count 2 2006.169.07:31:28.35#ibcon#about to read 6, iclass 17, count 2 2006.169.07:31:28.35#ibcon#read 6, iclass 17, count 2 2006.169.07:31:28.35#ibcon#end of sib2, iclass 17, count 2 2006.169.07:31:28.35#ibcon#*mode == 0, iclass 17, count 2 2006.169.07:31:28.35#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.169.07:31:28.35#ibcon#[27=AT03-04\r\n] 2006.169.07:31:28.35#ibcon#*before write, iclass 17, count 2 2006.169.07:31:28.35#ibcon#enter sib2, iclass 17, count 2 2006.169.07:31:28.35#ibcon#flushed, iclass 17, count 2 2006.169.07:31:28.35#ibcon#about to write, iclass 17, count 2 2006.169.07:31:28.35#ibcon#wrote, iclass 17, count 2 2006.169.07:31:28.35#ibcon#about to read 3, iclass 17, count 2 2006.169.07:31:28.38#ibcon#read 3, iclass 17, count 2 2006.169.07:31:28.38#ibcon#about to read 4, iclass 17, count 2 2006.169.07:31:28.38#ibcon#read 4, iclass 17, count 2 2006.169.07:31:28.38#ibcon#about to read 5, iclass 17, count 2 2006.169.07:31:28.38#ibcon#read 5, iclass 17, count 2 2006.169.07:31:28.38#ibcon#about to read 6, iclass 17, count 2 2006.169.07:31:28.38#ibcon#read 6, iclass 17, count 2 2006.169.07:31:28.38#ibcon#end of sib2, iclass 17, count 2 2006.169.07:31:28.38#ibcon#*after write, iclass 17, count 2 2006.169.07:31:28.38#ibcon#*before return 0, iclass 17, count 2 2006.169.07:31:28.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.169.07:31:28.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.169.07:31:28.38#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.169.07:31:28.38#ibcon#ireg 7 cls_cnt 0 2006.169.07:31:28.38#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.169.07:31:28.50#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.169.07:31:28.50#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.169.07:31:28.50#ibcon#enter wrdev, iclass 17, count 0 2006.169.07:31:28.50#ibcon#first serial, iclass 17, count 0 2006.169.07:31:28.50#ibcon#enter sib2, iclass 17, count 0 2006.169.07:31:28.50#ibcon#flushed, iclass 17, count 0 2006.169.07:31:28.50#ibcon#about to write, iclass 17, count 0 2006.169.07:31:28.50#ibcon#wrote, iclass 17, count 0 2006.169.07:31:28.50#ibcon#about to read 3, iclass 17, count 0 2006.169.07:31:28.52#ibcon#read 3, iclass 17, count 0 2006.169.07:31:28.52#ibcon#about to read 4, iclass 17, count 0 2006.169.07:31:28.52#ibcon#read 4, iclass 17, count 0 2006.169.07:31:28.52#ibcon#about to read 5, iclass 17, count 0 2006.169.07:31:28.52#ibcon#read 5, iclass 17, count 0 2006.169.07:31:28.52#ibcon#about to read 6, iclass 17, count 0 2006.169.07:31:28.52#ibcon#read 6, iclass 17, count 0 2006.169.07:31:28.52#ibcon#end of sib2, iclass 17, count 0 2006.169.07:31:28.52#ibcon#*mode == 0, iclass 17, count 0 2006.169.07:31:28.52#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.169.07:31:28.52#ibcon#[27=USB\r\n] 2006.169.07:31:28.52#ibcon#*before write, iclass 17, count 0 2006.169.07:31:28.52#ibcon#enter sib2, iclass 17, count 0 2006.169.07:31:28.52#ibcon#flushed, iclass 17, count 0 2006.169.07:31:28.52#ibcon#about to write, iclass 17, count 0 2006.169.07:31:28.52#ibcon#wrote, iclass 17, count 0 2006.169.07:31:28.52#ibcon#about to read 3, iclass 17, count 0 2006.169.07:31:28.55#ibcon#read 3, iclass 17, count 0 2006.169.07:31:28.55#ibcon#about to read 4, iclass 17, count 0 2006.169.07:31:28.55#ibcon#read 4, iclass 17, count 0 2006.169.07:31:28.55#ibcon#about to read 5, iclass 17, count 0 2006.169.07:31:28.55#ibcon#read 5, iclass 17, count 0 2006.169.07:31:28.55#ibcon#about to read 6, iclass 17, count 0 2006.169.07:31:28.55#ibcon#read 6, iclass 17, count 0 2006.169.07:31:28.55#ibcon#end of sib2, iclass 17, count 0 2006.169.07:31:28.55#ibcon#*after write, iclass 17, count 0 2006.169.07:31:28.55#ibcon#*before return 0, iclass 17, count 0 2006.169.07:31:28.55#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.169.07:31:28.55#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.169.07:31:28.55#ibcon#about to clear, iclass 17 cls_cnt 0 2006.169.07:31:28.55#ibcon#cleared, iclass 17 cls_cnt 0 2006.169.07:31:28.55$vc4f8/vblo=4,712.99 2006.169.07:31:28.55#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.169.07:31:28.55#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.169.07:31:28.55#ibcon#ireg 17 cls_cnt 0 2006.169.07:31:28.55#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.169.07:31:28.55#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.169.07:31:28.55#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.169.07:31:28.55#ibcon#enter wrdev, iclass 19, count 0 2006.169.07:31:28.55#ibcon#first serial, iclass 19, count 0 2006.169.07:31:28.55#ibcon#enter sib2, iclass 19, count 0 2006.169.07:31:28.55#ibcon#flushed, iclass 19, count 0 2006.169.07:31:28.55#ibcon#about to write, iclass 19, count 0 2006.169.07:31:28.55#ibcon#wrote, iclass 19, count 0 2006.169.07:31:28.55#ibcon#about to read 3, iclass 19, count 0 2006.169.07:31:28.57#ibcon#read 3, iclass 19, count 0 2006.169.07:31:28.57#ibcon#about to read 4, iclass 19, count 0 2006.169.07:31:28.57#ibcon#read 4, iclass 19, count 0 2006.169.07:31:28.57#ibcon#about to read 5, iclass 19, count 0 2006.169.07:31:28.57#ibcon#read 5, iclass 19, count 0 2006.169.07:31:28.57#ibcon#about to read 6, iclass 19, count 0 2006.169.07:31:28.57#ibcon#read 6, iclass 19, count 0 2006.169.07:31:28.57#ibcon#end of sib2, iclass 19, count 0 2006.169.07:31:28.57#ibcon#*mode == 0, iclass 19, count 0 2006.169.07:31:28.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.169.07:31:28.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.07:31:28.57#ibcon#*before write, iclass 19, count 0 2006.169.07:31:28.57#ibcon#enter sib2, iclass 19, count 0 2006.169.07:31:28.57#ibcon#flushed, iclass 19, count 0 2006.169.07:31:28.57#ibcon#about to write, iclass 19, count 0 2006.169.07:31:28.57#ibcon#wrote, iclass 19, count 0 2006.169.07:31:28.57#ibcon#about to read 3, iclass 19, count 0 2006.169.07:31:28.61#ibcon#read 3, iclass 19, count 0 2006.169.07:31:28.61#ibcon#about to read 4, iclass 19, count 0 2006.169.07:31:28.61#ibcon#read 4, iclass 19, count 0 2006.169.07:31:28.61#ibcon#about to read 5, iclass 19, count 0 2006.169.07:31:28.61#ibcon#read 5, iclass 19, count 0 2006.169.07:31:28.61#ibcon#about to read 6, iclass 19, count 0 2006.169.07:31:28.61#ibcon#read 6, iclass 19, count 0 2006.169.07:31:28.61#ibcon#end of sib2, iclass 19, count 0 2006.169.07:31:28.61#ibcon#*after write, iclass 19, count 0 2006.169.07:31:28.61#ibcon#*before return 0, iclass 19, count 0 2006.169.07:31:28.61#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.169.07:31:28.61#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.169.07:31:28.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.169.07:31:28.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.169.07:31:28.61$vc4f8/vb=4,4 2006.169.07:31:28.61#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.169.07:31:28.61#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.169.07:31:28.61#ibcon#ireg 11 cls_cnt 2 2006.169.07:31:28.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.169.07:31:28.67#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.169.07:31:28.67#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.169.07:31:28.67#ibcon#enter wrdev, iclass 21, count 2 2006.169.07:31:28.67#ibcon#first serial, iclass 21, count 2 2006.169.07:31:28.67#ibcon#enter sib2, iclass 21, count 2 2006.169.07:31:28.67#ibcon#flushed, iclass 21, count 2 2006.169.07:31:28.67#ibcon#about to write, iclass 21, count 2 2006.169.07:31:28.67#ibcon#wrote, iclass 21, count 2 2006.169.07:31:28.67#ibcon#about to read 3, iclass 21, count 2 2006.169.07:31:28.69#ibcon#read 3, iclass 21, count 2 2006.169.07:31:28.69#ibcon#about to read 4, iclass 21, count 2 2006.169.07:31:28.69#ibcon#read 4, iclass 21, count 2 2006.169.07:31:28.69#ibcon#about to read 5, iclass 21, count 2 2006.169.07:31:28.69#ibcon#read 5, iclass 21, count 2 2006.169.07:31:28.69#ibcon#about to read 6, iclass 21, count 2 2006.169.07:31:28.69#ibcon#read 6, iclass 21, count 2 2006.169.07:31:28.69#ibcon#end of sib2, iclass 21, count 2 2006.169.07:31:28.69#ibcon#*mode == 0, iclass 21, count 2 2006.169.07:31:28.69#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.169.07:31:28.69#ibcon#[27=AT04-04\r\n] 2006.169.07:31:28.69#ibcon#*before write, iclass 21, count 2 2006.169.07:31:28.69#ibcon#enter sib2, iclass 21, count 2 2006.169.07:31:28.69#ibcon#flushed, iclass 21, count 2 2006.169.07:31:28.69#ibcon#about to write, iclass 21, count 2 2006.169.07:31:28.69#ibcon#wrote, iclass 21, count 2 2006.169.07:31:28.69#ibcon#about to read 3, iclass 21, count 2 2006.169.07:31:28.72#ibcon#read 3, iclass 21, count 2 2006.169.07:31:28.72#ibcon#about to read 4, iclass 21, count 2 2006.169.07:31:28.72#ibcon#read 4, iclass 21, count 2 2006.169.07:31:28.72#ibcon#about to read 5, iclass 21, count 2 2006.169.07:31:28.72#ibcon#read 5, iclass 21, count 2 2006.169.07:31:28.72#ibcon#about to read 6, iclass 21, count 2 2006.169.07:31:28.72#ibcon#read 6, iclass 21, count 2 2006.169.07:31:28.72#ibcon#end of sib2, iclass 21, count 2 2006.169.07:31:28.72#ibcon#*after write, iclass 21, count 2 2006.169.07:31:28.72#ibcon#*before return 0, iclass 21, count 2 2006.169.07:31:28.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.169.07:31:28.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.169.07:31:28.72#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.169.07:31:28.72#ibcon#ireg 7 cls_cnt 0 2006.169.07:31:28.72#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.169.07:31:28.84#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.169.07:31:28.84#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.169.07:31:28.84#ibcon#enter wrdev, iclass 21, count 0 2006.169.07:31:28.84#ibcon#first serial, iclass 21, count 0 2006.169.07:31:28.84#ibcon#enter sib2, iclass 21, count 0 2006.169.07:31:28.84#ibcon#flushed, iclass 21, count 0 2006.169.07:31:28.84#ibcon#about to write, iclass 21, count 0 2006.169.07:31:28.84#ibcon#wrote, iclass 21, count 0 2006.169.07:31:28.84#ibcon#about to read 3, iclass 21, count 0 2006.169.07:31:28.86#ibcon#read 3, iclass 21, count 0 2006.169.07:31:28.86#ibcon#about to read 4, iclass 21, count 0 2006.169.07:31:28.86#ibcon#read 4, iclass 21, count 0 2006.169.07:31:28.86#ibcon#about to read 5, iclass 21, count 0 2006.169.07:31:28.86#ibcon#read 5, iclass 21, count 0 2006.169.07:31:28.86#ibcon#about to read 6, iclass 21, count 0 2006.169.07:31:28.86#ibcon#read 6, iclass 21, count 0 2006.169.07:31:28.86#ibcon#end of sib2, iclass 21, count 0 2006.169.07:31:28.86#ibcon#*mode == 0, iclass 21, count 0 2006.169.07:31:28.86#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.169.07:31:28.86#ibcon#[27=USB\r\n] 2006.169.07:31:28.86#ibcon#*before write, iclass 21, count 0 2006.169.07:31:28.86#ibcon#enter sib2, iclass 21, count 0 2006.169.07:31:28.86#ibcon#flushed, iclass 21, count 0 2006.169.07:31:28.86#ibcon#about to write, iclass 21, count 0 2006.169.07:31:28.86#ibcon#wrote, iclass 21, count 0 2006.169.07:31:28.86#ibcon#about to read 3, iclass 21, count 0 2006.169.07:31:28.89#ibcon#read 3, iclass 21, count 0 2006.169.07:31:28.89#ibcon#about to read 4, iclass 21, count 0 2006.169.07:31:28.89#ibcon#read 4, iclass 21, count 0 2006.169.07:31:28.89#ibcon#about to read 5, iclass 21, count 0 2006.169.07:31:28.89#ibcon#read 5, iclass 21, count 0 2006.169.07:31:28.89#ibcon#about to read 6, iclass 21, count 0 2006.169.07:31:28.89#ibcon#read 6, iclass 21, count 0 2006.169.07:31:28.89#ibcon#end of sib2, iclass 21, count 0 2006.169.07:31:28.89#ibcon#*after write, iclass 21, count 0 2006.169.07:31:28.89#ibcon#*before return 0, iclass 21, count 0 2006.169.07:31:28.89#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.169.07:31:28.89#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.169.07:31:28.89#ibcon#about to clear, iclass 21 cls_cnt 0 2006.169.07:31:28.89#ibcon#cleared, iclass 21 cls_cnt 0 2006.169.07:31:28.89$vc4f8/vblo=5,744.99 2006.169.07:31:28.89#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.169.07:31:28.89#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.169.07:31:28.89#ibcon#ireg 17 cls_cnt 0 2006.169.07:31:28.89#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.169.07:31:28.89#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.169.07:31:28.89#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.169.07:31:28.89#ibcon#enter wrdev, iclass 23, count 0 2006.169.07:31:28.89#ibcon#first serial, iclass 23, count 0 2006.169.07:31:28.89#ibcon#enter sib2, iclass 23, count 0 2006.169.07:31:28.89#ibcon#flushed, iclass 23, count 0 2006.169.07:31:28.89#ibcon#about to write, iclass 23, count 0 2006.169.07:31:28.89#ibcon#wrote, iclass 23, count 0 2006.169.07:31:28.89#ibcon#about to read 3, iclass 23, count 0 2006.169.07:31:28.91#ibcon#read 3, iclass 23, count 0 2006.169.07:31:28.91#ibcon#about to read 4, iclass 23, count 0 2006.169.07:31:28.91#ibcon#read 4, iclass 23, count 0 2006.169.07:31:28.91#ibcon#about to read 5, iclass 23, count 0 2006.169.07:31:28.91#ibcon#read 5, iclass 23, count 0 2006.169.07:31:28.91#ibcon#about to read 6, iclass 23, count 0 2006.169.07:31:28.91#ibcon#read 6, iclass 23, count 0 2006.169.07:31:28.91#ibcon#end of sib2, iclass 23, count 0 2006.169.07:31:28.91#ibcon#*mode == 0, iclass 23, count 0 2006.169.07:31:28.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.169.07:31:28.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.07:31:28.91#ibcon#*before write, iclass 23, count 0 2006.169.07:31:28.91#ibcon#enter sib2, iclass 23, count 0 2006.169.07:31:28.91#ibcon#flushed, iclass 23, count 0 2006.169.07:31:28.91#ibcon#about to write, iclass 23, count 0 2006.169.07:31:28.91#ibcon#wrote, iclass 23, count 0 2006.169.07:31:28.91#ibcon#about to read 3, iclass 23, count 0 2006.169.07:31:28.95#ibcon#read 3, iclass 23, count 0 2006.169.07:31:28.95#ibcon#about to read 4, iclass 23, count 0 2006.169.07:31:28.95#ibcon#read 4, iclass 23, count 0 2006.169.07:31:28.95#ibcon#about to read 5, iclass 23, count 0 2006.169.07:31:28.95#ibcon#read 5, iclass 23, count 0 2006.169.07:31:28.95#ibcon#about to read 6, iclass 23, count 0 2006.169.07:31:28.95#ibcon#read 6, iclass 23, count 0 2006.169.07:31:28.95#ibcon#end of sib2, iclass 23, count 0 2006.169.07:31:28.95#ibcon#*after write, iclass 23, count 0 2006.169.07:31:28.95#ibcon#*before return 0, iclass 23, count 0 2006.169.07:31:28.95#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.169.07:31:28.95#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.169.07:31:28.95#ibcon#about to clear, iclass 23 cls_cnt 0 2006.169.07:31:28.95#ibcon#cleared, iclass 23 cls_cnt 0 2006.169.07:31:28.95$vc4f8/vb=5,4 2006.169.07:31:28.95#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.169.07:31:28.95#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.169.07:31:28.95#ibcon#ireg 11 cls_cnt 2 2006.169.07:31:28.95#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.169.07:31:29.01#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.169.07:31:29.01#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.169.07:31:29.01#ibcon#enter wrdev, iclass 25, count 2 2006.169.07:31:29.01#ibcon#first serial, iclass 25, count 2 2006.169.07:31:29.01#ibcon#enter sib2, iclass 25, count 2 2006.169.07:31:29.01#ibcon#flushed, iclass 25, count 2 2006.169.07:31:29.01#ibcon#about to write, iclass 25, count 2 2006.169.07:31:29.01#ibcon#wrote, iclass 25, count 2 2006.169.07:31:29.01#ibcon#about to read 3, iclass 25, count 2 2006.169.07:31:29.03#ibcon#read 3, iclass 25, count 2 2006.169.07:31:29.03#ibcon#about to read 4, iclass 25, count 2 2006.169.07:31:29.03#ibcon#read 4, iclass 25, count 2 2006.169.07:31:29.03#ibcon#about to read 5, iclass 25, count 2 2006.169.07:31:29.03#ibcon#read 5, iclass 25, count 2 2006.169.07:31:29.03#ibcon#about to read 6, iclass 25, count 2 2006.169.07:31:29.03#ibcon#read 6, iclass 25, count 2 2006.169.07:31:29.03#ibcon#end of sib2, iclass 25, count 2 2006.169.07:31:29.03#ibcon#*mode == 0, iclass 25, count 2 2006.169.07:31:29.03#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.169.07:31:29.03#ibcon#[27=AT05-04\r\n] 2006.169.07:31:29.03#ibcon#*before write, iclass 25, count 2 2006.169.07:31:29.03#ibcon#enter sib2, iclass 25, count 2 2006.169.07:31:29.03#ibcon#flushed, iclass 25, count 2 2006.169.07:31:29.03#ibcon#about to write, iclass 25, count 2 2006.169.07:31:29.03#ibcon#wrote, iclass 25, count 2 2006.169.07:31:29.03#ibcon#about to read 3, iclass 25, count 2 2006.169.07:31:29.06#ibcon#read 3, iclass 25, count 2 2006.169.07:31:29.06#ibcon#about to read 4, iclass 25, count 2 2006.169.07:31:29.06#ibcon#read 4, iclass 25, count 2 2006.169.07:31:29.06#ibcon#about to read 5, iclass 25, count 2 2006.169.07:31:29.06#ibcon#read 5, iclass 25, count 2 2006.169.07:31:29.06#ibcon#about to read 6, iclass 25, count 2 2006.169.07:31:29.06#ibcon#read 6, iclass 25, count 2 2006.169.07:31:29.06#ibcon#end of sib2, iclass 25, count 2 2006.169.07:31:29.06#ibcon#*after write, iclass 25, count 2 2006.169.07:31:29.06#ibcon#*before return 0, iclass 25, count 2 2006.169.07:31:29.06#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.169.07:31:29.06#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.169.07:31:29.06#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.169.07:31:29.06#ibcon#ireg 7 cls_cnt 0 2006.169.07:31:29.06#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.169.07:31:29.18#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.169.07:31:29.18#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.169.07:31:29.18#ibcon#enter wrdev, iclass 25, count 0 2006.169.07:31:29.18#ibcon#first serial, iclass 25, count 0 2006.169.07:31:29.18#ibcon#enter sib2, iclass 25, count 0 2006.169.07:31:29.18#ibcon#flushed, iclass 25, count 0 2006.169.07:31:29.18#ibcon#about to write, iclass 25, count 0 2006.169.07:31:29.18#ibcon#wrote, iclass 25, count 0 2006.169.07:31:29.18#ibcon#about to read 3, iclass 25, count 0 2006.169.07:31:29.20#ibcon#read 3, iclass 25, count 0 2006.169.07:31:29.20#ibcon#about to read 4, iclass 25, count 0 2006.169.07:31:29.20#ibcon#read 4, iclass 25, count 0 2006.169.07:31:29.20#ibcon#about to read 5, iclass 25, count 0 2006.169.07:31:29.20#ibcon#read 5, iclass 25, count 0 2006.169.07:31:29.20#ibcon#about to read 6, iclass 25, count 0 2006.169.07:31:29.20#ibcon#read 6, iclass 25, count 0 2006.169.07:31:29.20#ibcon#end of sib2, iclass 25, count 0 2006.169.07:31:29.20#ibcon#*mode == 0, iclass 25, count 0 2006.169.07:31:29.20#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.169.07:31:29.20#ibcon#[27=USB\r\n] 2006.169.07:31:29.20#ibcon#*before write, iclass 25, count 0 2006.169.07:31:29.20#ibcon#enter sib2, iclass 25, count 0 2006.169.07:31:29.20#ibcon#flushed, iclass 25, count 0 2006.169.07:31:29.20#ibcon#about to write, iclass 25, count 0 2006.169.07:31:29.20#ibcon#wrote, iclass 25, count 0 2006.169.07:31:29.20#ibcon#about to read 3, iclass 25, count 0 2006.169.07:31:29.23#ibcon#read 3, iclass 25, count 0 2006.169.07:31:29.23#ibcon#about to read 4, iclass 25, count 0 2006.169.07:31:29.23#ibcon#read 4, iclass 25, count 0 2006.169.07:31:29.23#ibcon#about to read 5, iclass 25, count 0 2006.169.07:31:29.23#ibcon#read 5, iclass 25, count 0 2006.169.07:31:29.23#ibcon#about to read 6, iclass 25, count 0 2006.169.07:31:29.23#ibcon#read 6, iclass 25, count 0 2006.169.07:31:29.23#ibcon#end of sib2, iclass 25, count 0 2006.169.07:31:29.23#ibcon#*after write, iclass 25, count 0 2006.169.07:31:29.23#ibcon#*before return 0, iclass 25, count 0 2006.169.07:31:29.23#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.169.07:31:29.23#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.169.07:31:29.23#ibcon#about to clear, iclass 25 cls_cnt 0 2006.169.07:31:29.23#ibcon#cleared, iclass 25 cls_cnt 0 2006.169.07:31:29.23$vc4f8/vblo=6,752.99 2006.169.07:31:29.23#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.169.07:31:29.23#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.169.07:31:29.23#ibcon#ireg 17 cls_cnt 0 2006.169.07:31:29.23#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:31:29.23#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:31:29.23#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:31:29.23#ibcon#enter wrdev, iclass 27, count 0 2006.169.07:31:29.23#ibcon#first serial, iclass 27, count 0 2006.169.07:31:29.23#ibcon#enter sib2, iclass 27, count 0 2006.169.07:31:29.23#ibcon#flushed, iclass 27, count 0 2006.169.07:31:29.23#ibcon#about to write, iclass 27, count 0 2006.169.07:31:29.23#ibcon#wrote, iclass 27, count 0 2006.169.07:31:29.23#ibcon#about to read 3, iclass 27, count 0 2006.169.07:31:29.25#ibcon#read 3, iclass 27, count 0 2006.169.07:31:29.25#ibcon#about to read 4, iclass 27, count 0 2006.169.07:31:29.25#ibcon#read 4, iclass 27, count 0 2006.169.07:31:29.25#ibcon#about to read 5, iclass 27, count 0 2006.169.07:31:29.25#ibcon#read 5, iclass 27, count 0 2006.169.07:31:29.25#ibcon#about to read 6, iclass 27, count 0 2006.169.07:31:29.25#ibcon#read 6, iclass 27, count 0 2006.169.07:31:29.25#ibcon#end of sib2, iclass 27, count 0 2006.169.07:31:29.25#ibcon#*mode == 0, iclass 27, count 0 2006.169.07:31:29.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.169.07:31:29.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.07:31:29.25#ibcon#*before write, iclass 27, count 0 2006.169.07:31:29.25#ibcon#enter sib2, iclass 27, count 0 2006.169.07:31:29.25#ibcon#flushed, iclass 27, count 0 2006.169.07:31:29.25#ibcon#about to write, iclass 27, count 0 2006.169.07:31:29.25#ibcon#wrote, iclass 27, count 0 2006.169.07:31:29.25#ibcon#about to read 3, iclass 27, count 0 2006.169.07:31:29.29#ibcon#read 3, iclass 27, count 0 2006.169.07:31:29.29#ibcon#about to read 4, iclass 27, count 0 2006.169.07:31:29.29#ibcon#read 4, iclass 27, count 0 2006.169.07:31:29.29#ibcon#about to read 5, iclass 27, count 0 2006.169.07:31:29.29#ibcon#read 5, iclass 27, count 0 2006.169.07:31:29.29#ibcon#about to read 6, iclass 27, count 0 2006.169.07:31:29.29#ibcon#read 6, iclass 27, count 0 2006.169.07:31:29.29#ibcon#end of sib2, iclass 27, count 0 2006.169.07:31:29.29#ibcon#*after write, iclass 27, count 0 2006.169.07:31:29.29#ibcon#*before return 0, iclass 27, count 0 2006.169.07:31:29.29#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:31:29.29#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:31:29.29#ibcon#about to clear, iclass 27 cls_cnt 0 2006.169.07:31:29.29#ibcon#cleared, iclass 27 cls_cnt 0 2006.169.07:31:29.29$vc4f8/vb=6,4 2006.169.07:31:29.29#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.169.07:31:29.29#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.169.07:31:29.29#ibcon#ireg 11 cls_cnt 2 2006.169.07:31:29.29#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.169.07:31:29.35#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.169.07:31:29.35#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.169.07:31:29.35#ibcon#enter wrdev, iclass 29, count 2 2006.169.07:31:29.35#ibcon#first serial, iclass 29, count 2 2006.169.07:31:29.35#ibcon#enter sib2, iclass 29, count 2 2006.169.07:31:29.35#ibcon#flushed, iclass 29, count 2 2006.169.07:31:29.35#ibcon#about to write, iclass 29, count 2 2006.169.07:31:29.35#ibcon#wrote, iclass 29, count 2 2006.169.07:31:29.35#ibcon#about to read 3, iclass 29, count 2 2006.169.07:31:29.37#ibcon#read 3, iclass 29, count 2 2006.169.07:31:29.37#ibcon#about to read 4, iclass 29, count 2 2006.169.07:31:29.37#ibcon#read 4, iclass 29, count 2 2006.169.07:31:29.37#ibcon#about to read 5, iclass 29, count 2 2006.169.07:31:29.37#ibcon#read 5, iclass 29, count 2 2006.169.07:31:29.37#ibcon#about to read 6, iclass 29, count 2 2006.169.07:31:29.37#ibcon#read 6, iclass 29, count 2 2006.169.07:31:29.37#ibcon#end of sib2, iclass 29, count 2 2006.169.07:31:29.37#ibcon#*mode == 0, iclass 29, count 2 2006.169.07:31:29.37#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.169.07:31:29.37#ibcon#[27=AT06-04\r\n] 2006.169.07:31:29.37#ibcon#*before write, iclass 29, count 2 2006.169.07:31:29.37#ibcon#enter sib2, iclass 29, count 2 2006.169.07:31:29.37#ibcon#flushed, iclass 29, count 2 2006.169.07:31:29.37#ibcon#about to write, iclass 29, count 2 2006.169.07:31:29.37#ibcon#wrote, iclass 29, count 2 2006.169.07:31:29.37#ibcon#about to read 3, iclass 29, count 2 2006.169.07:31:29.40#ibcon#read 3, iclass 29, count 2 2006.169.07:31:29.40#ibcon#about to read 4, iclass 29, count 2 2006.169.07:31:29.40#ibcon#read 4, iclass 29, count 2 2006.169.07:31:29.40#ibcon#about to read 5, iclass 29, count 2 2006.169.07:31:29.40#ibcon#read 5, iclass 29, count 2 2006.169.07:31:29.40#ibcon#about to read 6, iclass 29, count 2 2006.169.07:31:29.40#ibcon#read 6, iclass 29, count 2 2006.169.07:31:29.40#ibcon#end of sib2, iclass 29, count 2 2006.169.07:31:29.40#ibcon#*after write, iclass 29, count 2 2006.169.07:31:29.40#ibcon#*before return 0, iclass 29, count 2 2006.169.07:31:29.40#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.169.07:31:29.40#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.169.07:31:29.40#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.169.07:31:29.40#ibcon#ireg 7 cls_cnt 0 2006.169.07:31:29.40#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.169.07:31:29.52#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.169.07:31:29.52#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.169.07:31:29.52#ibcon#enter wrdev, iclass 29, count 0 2006.169.07:31:29.52#ibcon#first serial, iclass 29, count 0 2006.169.07:31:29.52#ibcon#enter sib2, iclass 29, count 0 2006.169.07:31:29.52#ibcon#flushed, iclass 29, count 0 2006.169.07:31:29.52#ibcon#about to write, iclass 29, count 0 2006.169.07:31:29.52#ibcon#wrote, iclass 29, count 0 2006.169.07:31:29.52#ibcon#about to read 3, iclass 29, count 0 2006.169.07:31:29.54#ibcon#read 3, iclass 29, count 0 2006.169.07:31:29.54#ibcon#about to read 4, iclass 29, count 0 2006.169.07:31:29.54#ibcon#read 4, iclass 29, count 0 2006.169.07:31:29.54#ibcon#about to read 5, iclass 29, count 0 2006.169.07:31:29.54#ibcon#read 5, iclass 29, count 0 2006.169.07:31:29.54#ibcon#about to read 6, iclass 29, count 0 2006.169.07:31:29.54#ibcon#read 6, iclass 29, count 0 2006.169.07:31:29.54#ibcon#end of sib2, iclass 29, count 0 2006.169.07:31:29.54#ibcon#*mode == 0, iclass 29, count 0 2006.169.07:31:29.54#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.169.07:31:29.54#ibcon#[27=USB\r\n] 2006.169.07:31:29.54#ibcon#*before write, iclass 29, count 0 2006.169.07:31:29.54#ibcon#enter sib2, iclass 29, count 0 2006.169.07:31:29.54#ibcon#flushed, iclass 29, count 0 2006.169.07:31:29.54#ibcon#about to write, iclass 29, count 0 2006.169.07:31:29.54#ibcon#wrote, iclass 29, count 0 2006.169.07:31:29.54#ibcon#about to read 3, iclass 29, count 0 2006.169.07:31:29.57#ibcon#read 3, iclass 29, count 0 2006.169.07:31:29.57#ibcon#about to read 4, iclass 29, count 0 2006.169.07:31:29.57#ibcon#read 4, iclass 29, count 0 2006.169.07:31:29.57#ibcon#about to read 5, iclass 29, count 0 2006.169.07:31:29.57#ibcon#read 5, iclass 29, count 0 2006.169.07:31:29.57#ibcon#about to read 6, iclass 29, count 0 2006.169.07:31:29.57#ibcon#read 6, iclass 29, count 0 2006.169.07:31:29.57#ibcon#end of sib2, iclass 29, count 0 2006.169.07:31:29.57#ibcon#*after write, iclass 29, count 0 2006.169.07:31:29.57#ibcon#*before return 0, iclass 29, count 0 2006.169.07:31:29.57#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.169.07:31:29.57#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.169.07:31:29.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.169.07:31:29.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.169.07:31:29.57$vc4f8/vabw=wide 2006.169.07:31:29.57#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.169.07:31:29.57#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.169.07:31:29.57#ibcon#ireg 8 cls_cnt 0 2006.169.07:31:29.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.169.07:31:29.57#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.169.07:31:29.57#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.169.07:31:29.57#ibcon#enter wrdev, iclass 31, count 0 2006.169.07:31:29.57#ibcon#first serial, iclass 31, count 0 2006.169.07:31:29.57#ibcon#enter sib2, iclass 31, count 0 2006.169.07:31:29.57#ibcon#flushed, iclass 31, count 0 2006.169.07:31:29.57#ibcon#about to write, iclass 31, count 0 2006.169.07:31:29.57#ibcon#wrote, iclass 31, count 0 2006.169.07:31:29.57#ibcon#about to read 3, iclass 31, count 0 2006.169.07:31:29.59#ibcon#read 3, iclass 31, count 0 2006.169.07:31:29.59#ibcon#about to read 4, iclass 31, count 0 2006.169.07:31:29.59#ibcon#read 4, iclass 31, count 0 2006.169.07:31:29.59#ibcon#about to read 5, iclass 31, count 0 2006.169.07:31:29.59#ibcon#read 5, iclass 31, count 0 2006.169.07:31:29.59#ibcon#about to read 6, iclass 31, count 0 2006.169.07:31:29.59#ibcon#read 6, iclass 31, count 0 2006.169.07:31:29.59#ibcon#end of sib2, iclass 31, count 0 2006.169.07:31:29.59#ibcon#*mode == 0, iclass 31, count 0 2006.169.07:31:29.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.169.07:31:29.59#ibcon#[25=BW32\r\n] 2006.169.07:31:29.59#ibcon#*before write, iclass 31, count 0 2006.169.07:31:29.59#ibcon#enter sib2, iclass 31, count 0 2006.169.07:31:29.59#ibcon#flushed, iclass 31, count 0 2006.169.07:31:29.59#ibcon#about to write, iclass 31, count 0 2006.169.07:31:29.59#ibcon#wrote, iclass 31, count 0 2006.169.07:31:29.59#ibcon#about to read 3, iclass 31, count 0 2006.169.07:31:29.62#ibcon#read 3, iclass 31, count 0 2006.169.07:31:29.62#ibcon#about to read 4, iclass 31, count 0 2006.169.07:31:29.62#ibcon#read 4, iclass 31, count 0 2006.169.07:31:29.62#ibcon#about to read 5, iclass 31, count 0 2006.169.07:31:29.62#ibcon#read 5, iclass 31, count 0 2006.169.07:31:29.62#ibcon#about to read 6, iclass 31, count 0 2006.169.07:31:29.62#ibcon#read 6, iclass 31, count 0 2006.169.07:31:29.62#ibcon#end of sib2, iclass 31, count 0 2006.169.07:31:29.62#ibcon#*after write, iclass 31, count 0 2006.169.07:31:29.62#ibcon#*before return 0, iclass 31, count 0 2006.169.07:31:29.62#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.169.07:31:29.62#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.169.07:31:29.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.169.07:31:29.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.169.07:31:29.62$vc4f8/vbbw=wide 2006.169.07:31:29.62#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.169.07:31:29.62#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.169.07:31:29.62#ibcon#ireg 8 cls_cnt 0 2006.169.07:31:29.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:31:29.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:31:29.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:31:29.69#ibcon#enter wrdev, iclass 33, count 0 2006.169.07:31:29.69#ibcon#first serial, iclass 33, count 0 2006.169.07:31:29.69#ibcon#enter sib2, iclass 33, count 0 2006.169.07:31:29.69#ibcon#flushed, iclass 33, count 0 2006.169.07:31:29.69#ibcon#about to write, iclass 33, count 0 2006.169.07:31:29.69#ibcon#wrote, iclass 33, count 0 2006.169.07:31:29.69#ibcon#about to read 3, iclass 33, count 0 2006.169.07:31:29.71#ibcon#read 3, iclass 33, count 0 2006.169.07:31:29.71#ibcon#about to read 4, iclass 33, count 0 2006.169.07:31:29.71#ibcon#read 4, iclass 33, count 0 2006.169.07:31:29.71#ibcon#about to read 5, iclass 33, count 0 2006.169.07:31:29.71#ibcon#read 5, iclass 33, count 0 2006.169.07:31:29.71#ibcon#about to read 6, iclass 33, count 0 2006.169.07:31:29.71#ibcon#read 6, iclass 33, count 0 2006.169.07:31:29.71#ibcon#end of sib2, iclass 33, count 0 2006.169.07:31:29.71#ibcon#*mode == 0, iclass 33, count 0 2006.169.07:31:29.71#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.169.07:31:29.71#ibcon#[27=BW32\r\n] 2006.169.07:31:29.71#ibcon#*before write, iclass 33, count 0 2006.169.07:31:29.71#ibcon#enter sib2, iclass 33, count 0 2006.169.07:31:29.71#ibcon#flushed, iclass 33, count 0 2006.169.07:31:29.71#ibcon#about to write, iclass 33, count 0 2006.169.07:31:29.71#ibcon#wrote, iclass 33, count 0 2006.169.07:31:29.71#ibcon#about to read 3, iclass 33, count 0 2006.169.07:31:29.74#ibcon#read 3, iclass 33, count 0 2006.169.07:31:29.74#ibcon#about to read 4, iclass 33, count 0 2006.169.07:31:29.74#ibcon#read 4, iclass 33, count 0 2006.169.07:31:29.74#ibcon#about to read 5, iclass 33, count 0 2006.169.07:31:29.74#ibcon#read 5, iclass 33, count 0 2006.169.07:31:29.74#ibcon#about to read 6, iclass 33, count 0 2006.169.07:31:29.74#ibcon#read 6, iclass 33, count 0 2006.169.07:31:29.74#ibcon#end of sib2, iclass 33, count 0 2006.169.07:31:29.74#ibcon#*after write, iclass 33, count 0 2006.169.07:31:29.74#ibcon#*before return 0, iclass 33, count 0 2006.169.07:31:29.74#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:31:29.74#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:31:29.74#ibcon#about to clear, iclass 33 cls_cnt 0 2006.169.07:31:29.74#ibcon#cleared, iclass 33 cls_cnt 0 2006.169.07:31:29.74$4f8m12a/ifd4f 2006.169.07:31:29.74$ifd4f/lo= 2006.169.07:31:29.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.07:31:29.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.07:31:29.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.07:31:29.74$ifd4f/patch= 2006.169.07:31:29.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.07:31:29.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.07:31:29.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.07:31:29.74$4f8m12a/"form=m,16.000,1:2 2006.169.07:31:29.74$4f8m12a/"tpicd 2006.169.07:31:29.74$4f8m12a/echo=off 2006.169.07:31:29.74$4f8m12a/xlog=off 2006.169.07:31:29.74:!2006.169.07:33:20 2006.169.07:31:52.14#trakl#Source acquired 2006.169.07:31:52.14#flagr#flagr/antenna,acquired 2006.169.07:33:20.00:preob 2006.169.07:33:20.14/onsource/TRACKING 2006.169.07:33:20.14:!2006.169.07:33:30 2006.169.07:33:30.00:data_valid=on 2006.169.07:33:30.00:midob 2006.169.07:33:31.14/onsource/TRACKING 2006.169.07:33:31.14/wx/18.21,1003.8,100 2006.169.07:33:31.29/cable/+6.5284E-03 2006.169.07:33:32.38/va/01,08,usb,yes,50,53 2006.169.07:33:32.38/va/02,07,usb,yes,51,53 2006.169.07:33:32.38/va/03,06,usb,yes,54,54 2006.169.07:33:32.38/va/04,07,usb,yes,52,56 2006.169.07:33:32.38/va/05,07,usb,yes,57,60 2006.169.07:33:32.38/va/06,06,usb,yes,57,56 2006.169.07:33:32.38/va/07,06,usb,yes,57,57 2006.169.07:33:32.38/va/08,07,usb,yes,54,53 2006.169.07:33:32.61/valo/01,532.99,yes,locked 2006.169.07:33:32.61/valo/02,572.99,yes,locked 2006.169.07:33:32.61/valo/03,672.99,yes,locked 2006.169.07:33:32.61/valo/04,832.99,yes,locked 2006.169.07:33:32.61/valo/05,652.99,yes,locked 2006.169.07:33:32.61/valo/06,772.99,yes,locked 2006.169.07:33:32.61/valo/07,832.99,yes,locked 2006.169.07:33:32.61/valo/08,852.99,yes,locked 2006.169.07:33:33.70/vb/01,04,usb,yes,31,30 2006.169.07:33:33.70/vb/02,04,usb,yes,32,35 2006.169.07:33:33.70/vb/03,04,usb,yes,29,33 2006.169.07:33:33.70/vb/04,04,usb,yes,30,30 2006.169.07:33:33.70/vb/05,04,usb,yes,28,32 2006.169.07:33:33.70/vb/06,04,usb,yes,29,32 2006.169.07:33:33.70/vb/07,04,usb,yes,31,31 2006.169.07:33:33.70/vb/08,04,usb,yes,29,32 2006.169.07:33:33.93/vblo/01,632.99,yes,locked 2006.169.07:33:33.93/vblo/02,640.99,yes,locked 2006.169.07:33:33.93/vblo/03,656.99,yes,locked 2006.169.07:33:33.93/vblo/04,712.99,yes,locked 2006.169.07:33:33.93/vblo/05,744.99,yes,locked 2006.169.07:33:33.93/vblo/06,752.99,yes,locked 2006.169.07:33:33.93/vblo/07,734.99,yes,locked 2006.169.07:33:33.93/vblo/08,744.99,yes,locked 2006.169.07:33:34.08/vabw/8 2006.169.07:33:34.23/vbbw/8 2006.169.07:33:34.32/xfe/off,on,14.7 2006.169.07:33:34.72/ifatt/23,28,28,28 2006.169.07:33:35.07/fmout-gps/S +4.18E-07 2006.169.07:33:35.15:!2006.169.07:34:30 2006.169.07:34:30.00:data_valid=off 2006.169.07:34:30.00:postob 2006.169.07:34:30.10/cable/+6.5292E-03 2006.169.07:34:30.10/wx/18.20,1003.8,100 2006.169.07:34:31.08/fmout-gps/S +4.17E-07 2006.169.07:34:31.08:scan_name=169-0735,k06169,60 2006.169.07:34:31.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.169.07:34:31.14#flagr#flagr/antenna,new-source 2006.169.07:34:32.14:checkk5 2006.169.07:34:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.169.07:34:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.169.07:34:36.91/chk_autoobs//k5ts3?ERROR: timeout happened! 2006.169.07:34:37.28/chk_autoobs//k5ts4/ autoobs is running! 2006.169.07:34:37.66/chk_obsdata//k5ts1/T1690733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:34:38.02/chk_obsdata//k5ts2/T1690733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:34:45.05/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.07:34:45.42/chk_obsdata//k5ts4/T1690733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:34:46.11/k5log//k5ts1_log_newline 2006.169.07:34:46.80/k5log//k5ts2_log_newline 2006.169.07:34:53.14#trakl#Source acquired 2006.169.07:34:53.90/k5log//k5ts3?ERROR: timeout happened! 2006.169.07:34:54.58/k5log//k5ts4_log_newline 2006.169.07:34:54.76/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.07:34:54.76:4f8m12a=1 2006.169.07:34:54.76$4f8m12a/echo=on 2006.169.07:34:54.76$4f8m12a/pcalon 2006.169.07:34:54.76$pcalon/"no phase cal control is implemented here 2006.169.07:34:54.76$4f8m12a/"tpicd=stop 2006.169.07:34:54.76$4f8m12a/vc4f8 2006.169.07:34:54.76$vc4f8/valo=1,532.99 2006.169.07:34:54.77#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.169.07:34:54.77#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.169.07:34:54.77#ibcon#ireg 17 cls_cnt 0 2006.169.07:34:54.77#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:34:54.77#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:34:54.77#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:34:54.77#ibcon#enter wrdev, iclass 6, count 0 2006.169.07:34:54.77#ibcon#first serial, iclass 6, count 0 2006.169.07:34:54.77#ibcon#enter sib2, iclass 6, count 0 2006.169.07:34:54.77#ibcon#flushed, iclass 6, count 0 2006.169.07:34:54.77#ibcon#about to write, iclass 6, count 0 2006.169.07:34:54.77#ibcon#wrote, iclass 6, count 0 2006.169.07:34:54.77#ibcon#about to read 3, iclass 6, count 0 2006.169.07:34:54.79#ibcon#read 3, iclass 6, count 0 2006.169.07:34:54.79#ibcon#about to read 4, iclass 6, count 0 2006.169.07:34:54.79#ibcon#read 4, iclass 6, count 0 2006.169.07:34:54.79#ibcon#about to read 5, iclass 6, count 0 2006.169.07:34:54.79#ibcon#read 5, iclass 6, count 0 2006.169.07:34:54.79#ibcon#about to read 6, iclass 6, count 0 2006.169.07:34:54.79#ibcon#read 6, iclass 6, count 0 2006.169.07:34:54.79#ibcon#end of sib2, iclass 6, count 0 2006.169.07:34:54.79#ibcon#*mode == 0, iclass 6, count 0 2006.169.07:34:54.79#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.169.07:34:54.79#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.07:34:54.79#ibcon#*before write, iclass 6, count 0 2006.169.07:34:54.79#ibcon#enter sib2, iclass 6, count 0 2006.169.07:34:54.79#ibcon#flushed, iclass 6, count 0 2006.169.07:34:54.79#ibcon#about to write, iclass 6, count 0 2006.169.07:34:54.79#ibcon#wrote, iclass 6, count 0 2006.169.07:34:54.79#ibcon#about to read 3, iclass 6, count 0 2006.169.07:34:54.84#ibcon#read 3, iclass 6, count 0 2006.169.07:34:54.84#ibcon#about to read 4, iclass 6, count 0 2006.169.07:34:54.84#ibcon#read 4, iclass 6, count 0 2006.169.07:34:54.84#ibcon#about to read 5, iclass 6, count 0 2006.169.07:34:54.84#ibcon#read 5, iclass 6, count 0 2006.169.07:34:54.84#ibcon#about to read 6, iclass 6, count 0 2006.169.07:34:54.84#ibcon#read 6, iclass 6, count 0 2006.169.07:34:54.84#ibcon#end of sib2, iclass 6, count 0 2006.169.07:34:54.84#ibcon#*after write, iclass 6, count 0 2006.169.07:34:54.84#ibcon#*before return 0, iclass 6, count 0 2006.169.07:34:54.84#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:34:54.84#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:34:54.84#ibcon#about to clear, iclass 6 cls_cnt 0 2006.169.07:34:54.84#ibcon#cleared, iclass 6 cls_cnt 0 2006.169.07:34:54.84$vc4f8/va=1,8 2006.169.07:34:54.84#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.169.07:34:54.84#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.169.07:34:54.84#ibcon#ireg 11 cls_cnt 2 2006.169.07:34:54.84#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.169.07:34:54.84#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.169.07:34:54.84#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.169.07:34:54.84#ibcon#enter wrdev, iclass 10, count 2 2006.169.07:34:54.84#ibcon#first serial, iclass 10, count 2 2006.169.07:34:54.84#ibcon#enter sib2, iclass 10, count 2 2006.169.07:34:54.84#ibcon#flushed, iclass 10, count 2 2006.169.07:34:54.84#ibcon#about to write, iclass 10, count 2 2006.169.07:34:54.84#ibcon#wrote, iclass 10, count 2 2006.169.07:34:54.84#ibcon#about to read 3, iclass 10, count 2 2006.169.07:34:54.86#ibcon#read 3, iclass 10, count 2 2006.169.07:34:54.86#ibcon#about to read 4, iclass 10, count 2 2006.169.07:34:54.86#ibcon#read 4, iclass 10, count 2 2006.169.07:34:54.86#ibcon#about to read 5, iclass 10, count 2 2006.169.07:34:54.86#ibcon#read 5, iclass 10, count 2 2006.169.07:34:54.86#ibcon#about to read 6, iclass 10, count 2 2006.169.07:34:54.86#ibcon#read 6, iclass 10, count 2 2006.169.07:34:54.86#ibcon#end of sib2, iclass 10, count 2 2006.169.07:34:54.86#ibcon#*mode == 0, iclass 10, count 2 2006.169.07:34:54.86#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.169.07:34:54.86#ibcon#[25=AT01-08\r\n] 2006.169.07:34:54.86#ibcon#*before write, iclass 10, count 2 2006.169.07:34:54.86#ibcon#enter sib2, iclass 10, count 2 2006.169.07:34:54.86#ibcon#flushed, iclass 10, count 2 2006.169.07:34:54.86#ibcon#about to write, iclass 10, count 2 2006.169.07:34:54.86#ibcon#wrote, iclass 10, count 2 2006.169.07:34:54.86#ibcon#about to read 3, iclass 10, count 2 2006.169.07:34:54.89#ibcon#read 3, iclass 10, count 2 2006.169.07:34:54.89#ibcon#about to read 4, iclass 10, count 2 2006.169.07:34:54.89#ibcon#read 4, iclass 10, count 2 2006.169.07:34:54.89#ibcon#about to read 5, iclass 10, count 2 2006.169.07:34:54.89#ibcon#read 5, iclass 10, count 2 2006.169.07:34:54.89#ibcon#about to read 6, iclass 10, count 2 2006.169.07:34:54.89#ibcon#read 6, iclass 10, count 2 2006.169.07:34:54.89#ibcon#end of sib2, iclass 10, count 2 2006.169.07:34:54.89#ibcon#*after write, iclass 10, count 2 2006.169.07:34:54.89#ibcon#*before return 0, iclass 10, count 2 2006.169.07:34:54.89#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.169.07:34:54.89#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.169.07:34:54.89#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.169.07:34:54.89#ibcon#ireg 7 cls_cnt 0 2006.169.07:34:54.89#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.169.07:34:55.02#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.169.07:34:55.02#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.169.07:34:55.02#ibcon#enter wrdev, iclass 10, count 0 2006.169.07:34:55.02#ibcon#first serial, iclass 10, count 0 2006.169.07:34:55.02#ibcon#enter sib2, iclass 10, count 0 2006.169.07:34:55.02#ibcon#flushed, iclass 10, count 0 2006.169.07:34:55.02#ibcon#about to write, iclass 10, count 0 2006.169.07:34:55.02#ibcon#wrote, iclass 10, count 0 2006.169.07:34:55.02#ibcon#about to read 3, iclass 10, count 0 2006.169.07:34:55.04#ibcon#read 3, iclass 10, count 0 2006.169.07:34:55.04#ibcon#about to read 4, iclass 10, count 0 2006.169.07:34:55.04#ibcon#read 4, iclass 10, count 0 2006.169.07:34:55.04#ibcon#about to read 5, iclass 10, count 0 2006.169.07:34:55.04#ibcon#read 5, iclass 10, count 0 2006.169.07:34:55.04#ibcon#about to read 6, iclass 10, count 0 2006.169.07:34:55.04#ibcon#read 6, iclass 10, count 0 2006.169.07:34:55.04#ibcon#end of sib2, iclass 10, count 0 2006.169.07:34:55.04#ibcon#*mode == 0, iclass 10, count 0 2006.169.07:34:55.04#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.169.07:34:55.04#ibcon#[25=USB\r\n] 2006.169.07:34:55.04#ibcon#*before write, iclass 10, count 0 2006.169.07:34:55.04#ibcon#enter sib2, iclass 10, count 0 2006.169.07:34:55.04#ibcon#flushed, iclass 10, count 0 2006.169.07:34:55.04#ibcon#about to write, iclass 10, count 0 2006.169.07:34:55.04#ibcon#wrote, iclass 10, count 0 2006.169.07:34:55.04#ibcon#about to read 3, iclass 10, count 0 2006.169.07:34:55.07#ibcon#read 3, iclass 10, count 0 2006.169.07:34:55.07#ibcon#about to read 4, iclass 10, count 0 2006.169.07:34:55.07#ibcon#read 4, iclass 10, count 0 2006.169.07:34:55.07#ibcon#about to read 5, iclass 10, count 0 2006.169.07:34:55.07#ibcon#read 5, iclass 10, count 0 2006.169.07:34:55.07#ibcon#about to read 6, iclass 10, count 0 2006.169.07:34:55.07#ibcon#read 6, iclass 10, count 0 2006.169.07:34:55.07#ibcon#end of sib2, iclass 10, count 0 2006.169.07:34:55.07#ibcon#*after write, iclass 10, count 0 2006.169.07:34:55.07#ibcon#*before return 0, iclass 10, count 0 2006.169.07:34:55.07#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.169.07:34:55.07#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.169.07:34:55.07#ibcon#about to clear, iclass 10 cls_cnt 0 2006.169.07:34:55.07#ibcon#cleared, iclass 10 cls_cnt 0 2006.169.07:34:55.07$vc4f8/valo=2,572.99 2006.169.07:34:55.07#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.169.07:34:55.07#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.169.07:34:55.07#ibcon#ireg 17 cls_cnt 0 2006.169.07:34:55.07#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.169.07:34:55.07#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.169.07:34:55.07#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.169.07:34:55.07#ibcon#enter wrdev, iclass 12, count 0 2006.169.07:34:55.07#ibcon#first serial, iclass 12, count 0 2006.169.07:34:55.07#ibcon#enter sib2, iclass 12, count 0 2006.169.07:34:55.07#ibcon#flushed, iclass 12, count 0 2006.169.07:34:55.07#ibcon#about to write, iclass 12, count 0 2006.169.07:34:55.07#ibcon#wrote, iclass 12, count 0 2006.169.07:34:55.07#ibcon#about to read 3, iclass 12, count 0 2006.169.07:34:55.09#ibcon#read 3, iclass 12, count 0 2006.169.07:34:55.09#ibcon#about to read 4, iclass 12, count 0 2006.169.07:34:55.09#ibcon#read 4, iclass 12, count 0 2006.169.07:34:55.09#ibcon#about to read 5, iclass 12, count 0 2006.169.07:34:55.09#ibcon#read 5, iclass 12, count 0 2006.169.07:34:55.09#ibcon#about to read 6, iclass 12, count 0 2006.169.07:34:55.09#ibcon#read 6, iclass 12, count 0 2006.169.07:34:55.09#ibcon#end of sib2, iclass 12, count 0 2006.169.07:34:55.09#ibcon#*mode == 0, iclass 12, count 0 2006.169.07:34:55.09#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.169.07:34:55.09#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.07:34:55.09#ibcon#*before write, iclass 12, count 0 2006.169.07:34:55.09#ibcon#enter sib2, iclass 12, count 0 2006.169.07:34:55.09#ibcon#flushed, iclass 12, count 0 2006.169.07:34:55.09#ibcon#about to write, iclass 12, count 0 2006.169.07:34:55.09#ibcon#wrote, iclass 12, count 0 2006.169.07:34:55.09#ibcon#about to read 3, iclass 12, count 0 2006.169.07:34:55.13#ibcon#read 3, iclass 12, count 0 2006.169.07:34:55.13#ibcon#about to read 4, iclass 12, count 0 2006.169.07:34:55.13#ibcon#read 4, iclass 12, count 0 2006.169.07:34:55.13#ibcon#about to read 5, iclass 12, count 0 2006.169.07:34:55.13#ibcon#read 5, iclass 12, count 0 2006.169.07:34:55.13#ibcon#about to read 6, iclass 12, count 0 2006.169.07:34:55.13#ibcon#read 6, iclass 12, count 0 2006.169.07:34:55.13#ibcon#end of sib2, iclass 12, count 0 2006.169.07:34:55.13#ibcon#*after write, iclass 12, count 0 2006.169.07:34:55.13#ibcon#*before return 0, iclass 12, count 0 2006.169.07:34:55.13#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.169.07:34:55.13#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.169.07:34:55.13#ibcon#about to clear, iclass 12 cls_cnt 0 2006.169.07:34:55.13#ibcon#cleared, iclass 12 cls_cnt 0 2006.169.07:34:55.13$vc4f8/va=2,7 2006.169.07:34:55.13#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.169.07:34:55.13#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.169.07:34:55.13#ibcon#ireg 11 cls_cnt 2 2006.169.07:34:55.13#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.169.07:34:55.15#flagr#flagr/antenna,acquired 2006.169.07:34:55.19#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.169.07:34:55.19#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.169.07:34:55.19#ibcon#enter wrdev, iclass 14, count 2 2006.169.07:34:55.19#ibcon#first serial, iclass 14, count 2 2006.169.07:34:55.19#ibcon#enter sib2, iclass 14, count 2 2006.169.07:34:55.19#ibcon#flushed, iclass 14, count 2 2006.169.07:34:55.19#ibcon#about to write, iclass 14, count 2 2006.169.07:34:55.19#ibcon#wrote, iclass 14, count 2 2006.169.07:34:55.19#ibcon#about to read 3, iclass 14, count 2 2006.169.07:34:55.21#ibcon#read 3, iclass 14, count 2 2006.169.07:34:55.21#ibcon#about to read 4, iclass 14, count 2 2006.169.07:34:55.21#ibcon#read 4, iclass 14, count 2 2006.169.07:34:55.21#ibcon#about to read 5, iclass 14, count 2 2006.169.07:34:55.21#ibcon#read 5, iclass 14, count 2 2006.169.07:34:55.21#ibcon#about to read 6, iclass 14, count 2 2006.169.07:34:55.21#ibcon#read 6, iclass 14, count 2 2006.169.07:34:55.21#ibcon#end of sib2, iclass 14, count 2 2006.169.07:34:55.21#ibcon#*mode == 0, iclass 14, count 2 2006.169.07:34:55.21#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.169.07:34:55.21#ibcon#[25=AT02-07\r\n] 2006.169.07:34:55.21#ibcon#*before write, iclass 14, count 2 2006.169.07:34:55.21#ibcon#enter sib2, iclass 14, count 2 2006.169.07:34:55.21#ibcon#flushed, iclass 14, count 2 2006.169.07:34:55.21#ibcon#about to write, iclass 14, count 2 2006.169.07:34:55.21#ibcon#wrote, iclass 14, count 2 2006.169.07:34:55.21#ibcon#about to read 3, iclass 14, count 2 2006.169.07:34:55.25#ibcon#read 3, iclass 14, count 2 2006.169.07:34:55.25#ibcon#about to read 4, iclass 14, count 2 2006.169.07:34:55.25#ibcon#read 4, iclass 14, count 2 2006.169.07:34:55.25#ibcon#about to read 5, iclass 14, count 2 2006.169.07:34:55.25#ibcon#read 5, iclass 14, count 2 2006.169.07:34:55.25#ibcon#about to read 6, iclass 14, count 2 2006.169.07:34:55.25#ibcon#read 6, iclass 14, count 2 2006.169.07:34:55.25#ibcon#end of sib2, iclass 14, count 2 2006.169.07:34:55.25#ibcon#*after write, iclass 14, count 2 2006.169.07:34:55.25#ibcon#*before return 0, iclass 14, count 2 2006.169.07:34:55.25#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.169.07:34:55.25#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.169.07:34:55.25#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.169.07:34:55.25#ibcon#ireg 7 cls_cnt 0 2006.169.07:34:55.25#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.169.07:34:55.37#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.169.07:34:55.37#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.169.07:34:55.37#ibcon#enter wrdev, iclass 14, count 0 2006.169.07:34:55.37#ibcon#first serial, iclass 14, count 0 2006.169.07:34:55.37#ibcon#enter sib2, iclass 14, count 0 2006.169.07:34:55.37#ibcon#flushed, iclass 14, count 0 2006.169.07:34:55.37#ibcon#about to write, iclass 14, count 0 2006.169.07:34:55.37#ibcon#wrote, iclass 14, count 0 2006.169.07:34:55.37#ibcon#about to read 3, iclass 14, count 0 2006.169.07:34:55.39#ibcon#read 3, iclass 14, count 0 2006.169.07:34:55.39#ibcon#about to read 4, iclass 14, count 0 2006.169.07:34:55.39#ibcon#read 4, iclass 14, count 0 2006.169.07:34:55.39#ibcon#about to read 5, iclass 14, count 0 2006.169.07:34:55.39#ibcon#read 5, iclass 14, count 0 2006.169.07:34:55.39#ibcon#about to read 6, iclass 14, count 0 2006.169.07:34:55.39#ibcon#read 6, iclass 14, count 0 2006.169.07:34:55.39#ibcon#end of sib2, iclass 14, count 0 2006.169.07:34:55.39#ibcon#*mode == 0, iclass 14, count 0 2006.169.07:34:55.39#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.169.07:34:55.39#ibcon#[25=USB\r\n] 2006.169.07:34:55.39#ibcon#*before write, iclass 14, count 0 2006.169.07:34:55.39#ibcon#enter sib2, iclass 14, count 0 2006.169.07:34:55.39#ibcon#flushed, iclass 14, count 0 2006.169.07:34:55.39#ibcon#about to write, iclass 14, count 0 2006.169.07:34:55.39#ibcon#wrote, iclass 14, count 0 2006.169.07:34:55.39#ibcon#about to read 3, iclass 14, count 0 2006.169.07:34:55.42#ibcon#read 3, iclass 14, count 0 2006.169.07:34:55.42#ibcon#about to read 4, iclass 14, count 0 2006.169.07:34:55.42#ibcon#read 4, iclass 14, count 0 2006.169.07:34:55.42#ibcon#about to read 5, iclass 14, count 0 2006.169.07:34:55.42#ibcon#read 5, iclass 14, count 0 2006.169.07:34:55.42#ibcon#about to read 6, iclass 14, count 0 2006.169.07:34:55.42#ibcon#read 6, iclass 14, count 0 2006.169.07:34:55.42#ibcon#end of sib2, iclass 14, count 0 2006.169.07:34:55.42#ibcon#*after write, iclass 14, count 0 2006.169.07:34:55.42#ibcon#*before return 0, iclass 14, count 0 2006.169.07:34:55.42#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.169.07:34:55.42#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.169.07:34:55.42#ibcon#about to clear, iclass 14 cls_cnt 0 2006.169.07:34:55.42#ibcon#cleared, iclass 14 cls_cnt 0 2006.169.07:34:55.42$vc4f8/valo=3,672.99 2006.169.07:34:55.42#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.169.07:34:55.42#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.169.07:34:55.42#ibcon#ireg 17 cls_cnt 0 2006.169.07:34:55.42#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:34:55.42#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:34:55.42#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:34:55.42#ibcon#enter wrdev, iclass 16, count 0 2006.169.07:34:55.42#ibcon#first serial, iclass 16, count 0 2006.169.07:34:55.42#ibcon#enter sib2, iclass 16, count 0 2006.169.07:34:55.42#ibcon#flushed, iclass 16, count 0 2006.169.07:34:55.42#ibcon#about to write, iclass 16, count 0 2006.169.07:34:55.42#ibcon#wrote, iclass 16, count 0 2006.169.07:34:55.42#ibcon#about to read 3, iclass 16, count 0 2006.169.07:34:55.44#ibcon#read 3, iclass 16, count 0 2006.169.07:34:55.44#ibcon#about to read 4, iclass 16, count 0 2006.169.07:34:55.44#ibcon#read 4, iclass 16, count 0 2006.169.07:34:55.44#ibcon#about to read 5, iclass 16, count 0 2006.169.07:34:55.44#ibcon#read 5, iclass 16, count 0 2006.169.07:34:55.44#ibcon#about to read 6, iclass 16, count 0 2006.169.07:34:55.44#ibcon#read 6, iclass 16, count 0 2006.169.07:34:55.44#ibcon#end of sib2, iclass 16, count 0 2006.169.07:34:55.44#ibcon#*mode == 0, iclass 16, count 0 2006.169.07:34:55.44#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.169.07:34:55.44#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.07:34:55.44#ibcon#*before write, iclass 16, count 0 2006.169.07:34:55.44#ibcon#enter sib2, iclass 16, count 0 2006.169.07:34:55.44#ibcon#flushed, iclass 16, count 0 2006.169.07:34:55.44#ibcon#about to write, iclass 16, count 0 2006.169.07:34:55.44#ibcon#wrote, iclass 16, count 0 2006.169.07:34:55.44#ibcon#about to read 3, iclass 16, count 0 2006.169.07:34:55.48#ibcon#read 3, iclass 16, count 0 2006.169.07:34:55.48#ibcon#about to read 4, iclass 16, count 0 2006.169.07:34:55.48#ibcon#read 4, iclass 16, count 0 2006.169.07:34:55.48#ibcon#about to read 5, iclass 16, count 0 2006.169.07:34:55.48#ibcon#read 5, iclass 16, count 0 2006.169.07:34:55.48#ibcon#about to read 6, iclass 16, count 0 2006.169.07:34:55.48#ibcon#read 6, iclass 16, count 0 2006.169.07:34:55.48#ibcon#end of sib2, iclass 16, count 0 2006.169.07:34:55.48#ibcon#*after write, iclass 16, count 0 2006.169.07:34:55.48#ibcon#*before return 0, iclass 16, count 0 2006.169.07:34:55.48#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:34:55.48#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:34:55.48#ibcon#about to clear, iclass 16 cls_cnt 0 2006.169.07:34:55.48#ibcon#cleared, iclass 16 cls_cnt 0 2006.169.07:34:55.48$vc4f8/va=3,6 2006.169.07:34:55.48#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.169.07:34:55.48#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.169.07:34:55.48#ibcon#ireg 11 cls_cnt 2 2006.169.07:34:55.48#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.169.07:34:55.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.169.07:34:55.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.169.07:34:55.54#ibcon#enter wrdev, iclass 18, count 2 2006.169.07:34:55.54#ibcon#first serial, iclass 18, count 2 2006.169.07:34:55.54#ibcon#enter sib2, iclass 18, count 2 2006.169.07:34:55.54#ibcon#flushed, iclass 18, count 2 2006.169.07:34:55.54#ibcon#about to write, iclass 18, count 2 2006.169.07:34:55.54#ibcon#wrote, iclass 18, count 2 2006.169.07:34:55.54#ibcon#about to read 3, iclass 18, count 2 2006.169.07:34:55.56#ibcon#read 3, iclass 18, count 2 2006.169.07:34:55.56#ibcon#about to read 4, iclass 18, count 2 2006.169.07:34:55.56#ibcon#read 4, iclass 18, count 2 2006.169.07:34:55.56#ibcon#about to read 5, iclass 18, count 2 2006.169.07:34:55.56#ibcon#read 5, iclass 18, count 2 2006.169.07:34:55.56#ibcon#about to read 6, iclass 18, count 2 2006.169.07:34:55.56#ibcon#read 6, iclass 18, count 2 2006.169.07:34:55.56#ibcon#end of sib2, iclass 18, count 2 2006.169.07:34:55.56#ibcon#*mode == 0, iclass 18, count 2 2006.169.07:34:55.56#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.169.07:34:55.56#ibcon#[25=AT03-06\r\n] 2006.169.07:34:55.56#ibcon#*before write, iclass 18, count 2 2006.169.07:34:55.56#ibcon#enter sib2, iclass 18, count 2 2006.169.07:34:55.56#ibcon#flushed, iclass 18, count 2 2006.169.07:34:55.56#ibcon#about to write, iclass 18, count 2 2006.169.07:34:55.56#ibcon#wrote, iclass 18, count 2 2006.169.07:34:55.56#ibcon#about to read 3, iclass 18, count 2 2006.169.07:34:55.59#ibcon#read 3, iclass 18, count 2 2006.169.07:34:55.59#ibcon#about to read 4, iclass 18, count 2 2006.169.07:34:55.59#ibcon#read 4, iclass 18, count 2 2006.169.07:34:55.59#ibcon#about to read 5, iclass 18, count 2 2006.169.07:34:55.59#ibcon#read 5, iclass 18, count 2 2006.169.07:34:55.59#ibcon#about to read 6, iclass 18, count 2 2006.169.07:34:55.59#ibcon#read 6, iclass 18, count 2 2006.169.07:34:55.59#ibcon#end of sib2, iclass 18, count 2 2006.169.07:34:55.59#ibcon#*after write, iclass 18, count 2 2006.169.07:34:55.59#ibcon#*before return 0, iclass 18, count 2 2006.169.07:34:55.59#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.169.07:34:55.59#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.169.07:34:55.59#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.169.07:34:55.59#ibcon#ireg 7 cls_cnt 0 2006.169.07:34:55.59#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.169.07:34:55.71#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.169.07:34:55.71#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.169.07:34:55.71#ibcon#enter wrdev, iclass 18, count 0 2006.169.07:34:55.71#ibcon#first serial, iclass 18, count 0 2006.169.07:34:55.71#ibcon#enter sib2, iclass 18, count 0 2006.169.07:34:55.71#ibcon#flushed, iclass 18, count 0 2006.169.07:34:55.71#ibcon#about to write, iclass 18, count 0 2006.169.07:34:55.71#ibcon#wrote, iclass 18, count 0 2006.169.07:34:55.71#ibcon#about to read 3, iclass 18, count 0 2006.169.07:34:55.73#ibcon#read 3, iclass 18, count 0 2006.169.07:34:55.73#ibcon#about to read 4, iclass 18, count 0 2006.169.07:34:55.73#ibcon#read 4, iclass 18, count 0 2006.169.07:34:55.73#ibcon#about to read 5, iclass 18, count 0 2006.169.07:34:55.73#ibcon#read 5, iclass 18, count 0 2006.169.07:34:55.73#ibcon#about to read 6, iclass 18, count 0 2006.169.07:34:55.73#ibcon#read 6, iclass 18, count 0 2006.169.07:34:55.73#ibcon#end of sib2, iclass 18, count 0 2006.169.07:34:55.73#ibcon#*mode == 0, iclass 18, count 0 2006.169.07:34:55.73#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.169.07:34:55.73#ibcon#[25=USB\r\n] 2006.169.07:34:55.73#ibcon#*before write, iclass 18, count 0 2006.169.07:34:55.73#ibcon#enter sib2, iclass 18, count 0 2006.169.07:34:55.73#ibcon#flushed, iclass 18, count 0 2006.169.07:34:55.73#ibcon#about to write, iclass 18, count 0 2006.169.07:34:55.73#ibcon#wrote, iclass 18, count 0 2006.169.07:34:55.73#ibcon#about to read 3, iclass 18, count 0 2006.169.07:34:55.76#ibcon#read 3, iclass 18, count 0 2006.169.07:34:55.76#ibcon#about to read 4, iclass 18, count 0 2006.169.07:34:55.76#ibcon#read 4, iclass 18, count 0 2006.169.07:34:55.76#ibcon#about to read 5, iclass 18, count 0 2006.169.07:34:55.76#ibcon#read 5, iclass 18, count 0 2006.169.07:34:55.76#ibcon#about to read 6, iclass 18, count 0 2006.169.07:34:55.76#ibcon#read 6, iclass 18, count 0 2006.169.07:34:55.76#ibcon#end of sib2, iclass 18, count 0 2006.169.07:34:55.76#ibcon#*after write, iclass 18, count 0 2006.169.07:34:55.76#ibcon#*before return 0, iclass 18, count 0 2006.169.07:34:55.76#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.169.07:34:55.76#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.169.07:34:55.76#ibcon#about to clear, iclass 18 cls_cnt 0 2006.169.07:34:55.76#ibcon#cleared, iclass 18 cls_cnt 0 2006.169.07:34:55.76$vc4f8/valo=4,832.99 2006.169.07:34:55.76#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.169.07:34:55.76#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.169.07:34:55.76#ibcon#ireg 17 cls_cnt 0 2006.169.07:34:55.76#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.169.07:34:55.76#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.169.07:34:55.76#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.169.07:34:55.76#ibcon#enter wrdev, iclass 20, count 0 2006.169.07:34:55.76#ibcon#first serial, iclass 20, count 0 2006.169.07:34:55.76#ibcon#enter sib2, iclass 20, count 0 2006.169.07:34:55.76#ibcon#flushed, iclass 20, count 0 2006.169.07:34:55.76#ibcon#about to write, iclass 20, count 0 2006.169.07:34:55.76#ibcon#wrote, iclass 20, count 0 2006.169.07:34:55.76#ibcon#about to read 3, iclass 20, count 0 2006.169.07:34:55.78#ibcon#read 3, iclass 20, count 0 2006.169.07:34:55.78#ibcon#about to read 4, iclass 20, count 0 2006.169.07:34:55.78#ibcon#read 4, iclass 20, count 0 2006.169.07:34:55.78#ibcon#about to read 5, iclass 20, count 0 2006.169.07:34:55.78#ibcon#read 5, iclass 20, count 0 2006.169.07:34:55.78#ibcon#about to read 6, iclass 20, count 0 2006.169.07:34:55.78#ibcon#read 6, iclass 20, count 0 2006.169.07:34:55.78#ibcon#end of sib2, iclass 20, count 0 2006.169.07:34:55.78#ibcon#*mode == 0, iclass 20, count 0 2006.169.07:34:55.78#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.169.07:34:55.78#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.07:34:55.78#ibcon#*before write, iclass 20, count 0 2006.169.07:34:55.78#ibcon#enter sib2, iclass 20, count 0 2006.169.07:34:55.78#ibcon#flushed, iclass 20, count 0 2006.169.07:34:55.78#ibcon#about to write, iclass 20, count 0 2006.169.07:34:55.78#ibcon#wrote, iclass 20, count 0 2006.169.07:34:55.78#ibcon#about to read 3, iclass 20, count 0 2006.169.07:34:55.82#ibcon#read 3, iclass 20, count 0 2006.169.07:34:55.82#ibcon#about to read 4, iclass 20, count 0 2006.169.07:34:55.82#ibcon#read 4, iclass 20, count 0 2006.169.07:34:55.82#ibcon#about to read 5, iclass 20, count 0 2006.169.07:34:55.82#ibcon#read 5, iclass 20, count 0 2006.169.07:34:55.82#ibcon#about to read 6, iclass 20, count 0 2006.169.07:34:55.82#ibcon#read 6, iclass 20, count 0 2006.169.07:34:55.82#ibcon#end of sib2, iclass 20, count 0 2006.169.07:34:55.82#ibcon#*after write, iclass 20, count 0 2006.169.07:34:55.82#ibcon#*before return 0, iclass 20, count 0 2006.169.07:34:55.82#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.169.07:34:55.82#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.169.07:34:55.82#ibcon#about to clear, iclass 20 cls_cnt 0 2006.169.07:34:55.82#ibcon#cleared, iclass 20 cls_cnt 0 2006.169.07:34:55.82$vc4f8/va=4,7 2006.169.07:34:55.82#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.169.07:34:55.82#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.169.07:34:55.82#ibcon#ireg 11 cls_cnt 2 2006.169.07:34:55.82#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.169.07:34:55.88#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.169.07:34:55.88#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.169.07:34:55.88#ibcon#enter wrdev, iclass 22, count 2 2006.169.07:34:55.88#ibcon#first serial, iclass 22, count 2 2006.169.07:34:55.88#ibcon#enter sib2, iclass 22, count 2 2006.169.07:34:55.88#ibcon#flushed, iclass 22, count 2 2006.169.07:34:55.88#ibcon#about to write, iclass 22, count 2 2006.169.07:34:55.88#ibcon#wrote, iclass 22, count 2 2006.169.07:34:55.88#ibcon#about to read 3, iclass 22, count 2 2006.169.07:34:55.90#ibcon#read 3, iclass 22, count 2 2006.169.07:34:55.90#ibcon#about to read 4, iclass 22, count 2 2006.169.07:34:55.90#ibcon#read 4, iclass 22, count 2 2006.169.07:34:55.90#ibcon#about to read 5, iclass 22, count 2 2006.169.07:34:55.90#ibcon#read 5, iclass 22, count 2 2006.169.07:34:55.90#ibcon#about to read 6, iclass 22, count 2 2006.169.07:34:55.90#ibcon#read 6, iclass 22, count 2 2006.169.07:34:55.90#ibcon#end of sib2, iclass 22, count 2 2006.169.07:34:55.90#ibcon#*mode == 0, iclass 22, count 2 2006.169.07:34:55.90#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.169.07:34:55.90#ibcon#[25=AT04-07\r\n] 2006.169.07:34:55.90#ibcon#*before write, iclass 22, count 2 2006.169.07:34:55.90#ibcon#enter sib2, iclass 22, count 2 2006.169.07:34:55.90#ibcon#flushed, iclass 22, count 2 2006.169.07:34:55.90#ibcon#about to write, iclass 22, count 2 2006.169.07:34:55.90#ibcon#wrote, iclass 22, count 2 2006.169.07:34:55.90#ibcon#about to read 3, iclass 22, count 2 2006.169.07:34:55.93#ibcon#read 3, iclass 22, count 2 2006.169.07:34:55.93#ibcon#about to read 4, iclass 22, count 2 2006.169.07:34:55.93#ibcon#read 4, iclass 22, count 2 2006.169.07:34:55.93#ibcon#about to read 5, iclass 22, count 2 2006.169.07:34:55.93#ibcon#read 5, iclass 22, count 2 2006.169.07:34:55.93#ibcon#about to read 6, iclass 22, count 2 2006.169.07:34:55.93#ibcon#read 6, iclass 22, count 2 2006.169.07:34:55.93#ibcon#end of sib2, iclass 22, count 2 2006.169.07:34:55.93#ibcon#*after write, iclass 22, count 2 2006.169.07:34:55.93#ibcon#*before return 0, iclass 22, count 2 2006.169.07:34:55.93#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.169.07:34:55.93#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.169.07:34:55.93#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.169.07:34:55.93#ibcon#ireg 7 cls_cnt 0 2006.169.07:34:55.93#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.169.07:34:56.05#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.169.07:34:56.05#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.169.07:34:56.05#ibcon#enter wrdev, iclass 22, count 0 2006.169.07:34:56.05#ibcon#first serial, iclass 22, count 0 2006.169.07:34:56.05#ibcon#enter sib2, iclass 22, count 0 2006.169.07:34:56.05#ibcon#flushed, iclass 22, count 0 2006.169.07:34:56.05#ibcon#about to write, iclass 22, count 0 2006.169.07:34:56.05#ibcon#wrote, iclass 22, count 0 2006.169.07:34:56.05#ibcon#about to read 3, iclass 22, count 0 2006.169.07:34:56.07#ibcon#read 3, iclass 22, count 0 2006.169.07:34:56.07#ibcon#about to read 4, iclass 22, count 0 2006.169.07:34:56.07#ibcon#read 4, iclass 22, count 0 2006.169.07:34:56.07#ibcon#about to read 5, iclass 22, count 0 2006.169.07:34:56.07#ibcon#read 5, iclass 22, count 0 2006.169.07:34:56.07#ibcon#about to read 6, iclass 22, count 0 2006.169.07:34:56.07#ibcon#read 6, iclass 22, count 0 2006.169.07:34:56.07#ibcon#end of sib2, iclass 22, count 0 2006.169.07:34:56.07#ibcon#*mode == 0, iclass 22, count 0 2006.169.07:34:56.07#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.169.07:34:56.07#ibcon#[25=USB\r\n] 2006.169.07:34:56.07#ibcon#*before write, iclass 22, count 0 2006.169.07:34:56.07#ibcon#enter sib2, iclass 22, count 0 2006.169.07:34:56.07#ibcon#flushed, iclass 22, count 0 2006.169.07:34:56.07#ibcon#about to write, iclass 22, count 0 2006.169.07:34:56.07#ibcon#wrote, iclass 22, count 0 2006.169.07:34:56.07#ibcon#about to read 3, iclass 22, count 0 2006.169.07:34:56.10#ibcon#read 3, iclass 22, count 0 2006.169.07:34:56.10#ibcon#about to read 4, iclass 22, count 0 2006.169.07:34:56.10#ibcon#read 4, iclass 22, count 0 2006.169.07:34:56.10#ibcon#about to read 5, iclass 22, count 0 2006.169.07:34:56.10#ibcon#read 5, iclass 22, count 0 2006.169.07:34:56.10#ibcon#about to read 6, iclass 22, count 0 2006.169.07:34:56.10#ibcon#read 6, iclass 22, count 0 2006.169.07:34:56.10#ibcon#end of sib2, iclass 22, count 0 2006.169.07:34:56.10#ibcon#*after write, iclass 22, count 0 2006.169.07:34:56.10#ibcon#*before return 0, iclass 22, count 0 2006.169.07:34:56.10#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.169.07:34:56.10#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.169.07:34:56.10#ibcon#about to clear, iclass 22 cls_cnt 0 2006.169.07:34:56.10#ibcon#cleared, iclass 22 cls_cnt 0 2006.169.07:34:56.10$vc4f8/valo=5,652.99 2006.169.07:34:56.10#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.169.07:34:56.10#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.169.07:34:56.10#ibcon#ireg 17 cls_cnt 0 2006.169.07:34:56.10#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.169.07:34:56.10#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.169.07:34:56.10#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.169.07:34:56.10#ibcon#enter wrdev, iclass 24, count 0 2006.169.07:34:56.10#ibcon#first serial, iclass 24, count 0 2006.169.07:34:56.10#ibcon#enter sib2, iclass 24, count 0 2006.169.07:34:56.10#ibcon#flushed, iclass 24, count 0 2006.169.07:34:56.10#ibcon#about to write, iclass 24, count 0 2006.169.07:34:56.10#ibcon#wrote, iclass 24, count 0 2006.169.07:34:56.10#ibcon#about to read 3, iclass 24, count 0 2006.169.07:34:56.12#ibcon#read 3, iclass 24, count 0 2006.169.07:34:56.12#ibcon#about to read 4, iclass 24, count 0 2006.169.07:34:56.12#ibcon#read 4, iclass 24, count 0 2006.169.07:34:56.12#ibcon#about to read 5, iclass 24, count 0 2006.169.07:34:56.12#ibcon#read 5, iclass 24, count 0 2006.169.07:34:56.12#ibcon#about to read 6, iclass 24, count 0 2006.169.07:34:56.12#ibcon#read 6, iclass 24, count 0 2006.169.07:34:56.12#ibcon#end of sib2, iclass 24, count 0 2006.169.07:34:56.12#ibcon#*mode == 0, iclass 24, count 0 2006.169.07:34:56.12#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.169.07:34:56.12#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.07:34:56.12#ibcon#*before write, iclass 24, count 0 2006.169.07:34:56.12#ibcon#enter sib2, iclass 24, count 0 2006.169.07:34:56.12#ibcon#flushed, iclass 24, count 0 2006.169.07:34:56.12#ibcon#about to write, iclass 24, count 0 2006.169.07:34:56.12#ibcon#wrote, iclass 24, count 0 2006.169.07:34:56.12#ibcon#about to read 3, iclass 24, count 0 2006.169.07:34:56.16#ibcon#read 3, iclass 24, count 0 2006.169.07:34:56.16#ibcon#about to read 4, iclass 24, count 0 2006.169.07:34:56.16#ibcon#read 4, iclass 24, count 0 2006.169.07:34:56.16#ibcon#about to read 5, iclass 24, count 0 2006.169.07:34:56.16#ibcon#read 5, iclass 24, count 0 2006.169.07:34:56.16#ibcon#about to read 6, iclass 24, count 0 2006.169.07:34:56.16#ibcon#read 6, iclass 24, count 0 2006.169.07:34:56.16#ibcon#end of sib2, iclass 24, count 0 2006.169.07:34:56.16#ibcon#*after write, iclass 24, count 0 2006.169.07:34:56.16#ibcon#*before return 0, iclass 24, count 0 2006.169.07:34:56.16#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.169.07:34:56.16#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.169.07:34:56.16#ibcon#about to clear, iclass 24 cls_cnt 0 2006.169.07:34:56.16#ibcon#cleared, iclass 24 cls_cnt 0 2006.169.07:34:56.16$vc4f8/va=5,7 2006.169.07:34:56.16#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.169.07:34:56.16#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.169.07:34:56.16#ibcon#ireg 11 cls_cnt 2 2006.169.07:34:56.16#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.169.07:34:56.22#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.169.07:34:56.22#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.169.07:34:56.22#ibcon#enter wrdev, iclass 26, count 2 2006.169.07:34:56.22#ibcon#first serial, iclass 26, count 2 2006.169.07:34:56.22#ibcon#enter sib2, iclass 26, count 2 2006.169.07:34:56.22#ibcon#flushed, iclass 26, count 2 2006.169.07:34:56.22#ibcon#about to write, iclass 26, count 2 2006.169.07:34:56.22#ibcon#wrote, iclass 26, count 2 2006.169.07:34:56.22#ibcon#about to read 3, iclass 26, count 2 2006.169.07:34:56.24#ibcon#read 3, iclass 26, count 2 2006.169.07:34:56.24#ibcon#about to read 4, iclass 26, count 2 2006.169.07:34:56.24#ibcon#read 4, iclass 26, count 2 2006.169.07:34:56.24#ibcon#about to read 5, iclass 26, count 2 2006.169.07:34:56.24#ibcon#read 5, iclass 26, count 2 2006.169.07:34:56.24#ibcon#about to read 6, iclass 26, count 2 2006.169.07:34:56.24#ibcon#read 6, iclass 26, count 2 2006.169.07:34:56.24#ibcon#end of sib2, iclass 26, count 2 2006.169.07:34:56.24#ibcon#*mode == 0, iclass 26, count 2 2006.169.07:34:56.24#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.169.07:34:56.24#ibcon#[25=AT05-07\r\n] 2006.169.07:34:56.24#ibcon#*before write, iclass 26, count 2 2006.169.07:34:56.24#ibcon#enter sib2, iclass 26, count 2 2006.169.07:34:56.24#ibcon#flushed, iclass 26, count 2 2006.169.07:34:56.24#ibcon#about to write, iclass 26, count 2 2006.169.07:34:56.24#ibcon#wrote, iclass 26, count 2 2006.169.07:34:56.24#ibcon#about to read 3, iclass 26, count 2 2006.169.07:34:56.27#ibcon#read 3, iclass 26, count 2 2006.169.07:34:56.27#ibcon#about to read 4, iclass 26, count 2 2006.169.07:34:56.27#ibcon#read 4, iclass 26, count 2 2006.169.07:34:56.27#ibcon#about to read 5, iclass 26, count 2 2006.169.07:34:56.27#ibcon#read 5, iclass 26, count 2 2006.169.07:34:56.27#ibcon#about to read 6, iclass 26, count 2 2006.169.07:34:56.27#ibcon#read 6, iclass 26, count 2 2006.169.07:34:56.27#ibcon#end of sib2, iclass 26, count 2 2006.169.07:34:56.27#ibcon#*after write, iclass 26, count 2 2006.169.07:34:56.27#ibcon#*before return 0, iclass 26, count 2 2006.169.07:34:56.27#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.169.07:34:56.27#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.169.07:34:56.27#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.169.07:34:56.27#ibcon#ireg 7 cls_cnt 0 2006.169.07:34:56.27#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.169.07:34:56.40#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.169.07:34:56.40#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.169.07:34:56.40#ibcon#enter wrdev, iclass 26, count 0 2006.169.07:34:56.40#ibcon#first serial, iclass 26, count 0 2006.169.07:34:56.40#ibcon#enter sib2, iclass 26, count 0 2006.169.07:34:56.40#ibcon#flushed, iclass 26, count 0 2006.169.07:34:56.40#ibcon#about to write, iclass 26, count 0 2006.169.07:34:56.40#ibcon#wrote, iclass 26, count 0 2006.169.07:34:56.40#ibcon#about to read 3, iclass 26, count 0 2006.169.07:34:56.42#ibcon#read 3, iclass 26, count 0 2006.169.07:34:56.42#ibcon#about to read 4, iclass 26, count 0 2006.169.07:34:56.42#ibcon#read 4, iclass 26, count 0 2006.169.07:34:56.42#ibcon#about to read 5, iclass 26, count 0 2006.169.07:34:56.42#ibcon#read 5, iclass 26, count 0 2006.169.07:34:56.42#ibcon#about to read 6, iclass 26, count 0 2006.169.07:34:56.42#ibcon#read 6, iclass 26, count 0 2006.169.07:34:56.42#ibcon#end of sib2, iclass 26, count 0 2006.169.07:34:56.42#ibcon#*mode == 0, iclass 26, count 0 2006.169.07:34:56.42#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.169.07:34:56.42#ibcon#[25=USB\r\n] 2006.169.07:34:56.42#ibcon#*before write, iclass 26, count 0 2006.169.07:34:56.42#ibcon#enter sib2, iclass 26, count 0 2006.169.07:34:56.42#ibcon#flushed, iclass 26, count 0 2006.169.07:34:56.42#ibcon#about to write, iclass 26, count 0 2006.169.07:34:56.42#ibcon#wrote, iclass 26, count 0 2006.169.07:34:56.42#ibcon#about to read 3, iclass 26, count 0 2006.169.07:34:56.45#ibcon#read 3, iclass 26, count 0 2006.169.07:34:56.45#ibcon#about to read 4, iclass 26, count 0 2006.169.07:34:56.45#ibcon#read 4, iclass 26, count 0 2006.169.07:34:56.45#ibcon#about to read 5, iclass 26, count 0 2006.169.07:34:56.45#ibcon#read 5, iclass 26, count 0 2006.169.07:34:56.45#ibcon#about to read 6, iclass 26, count 0 2006.169.07:34:56.45#ibcon#read 6, iclass 26, count 0 2006.169.07:34:56.45#ibcon#end of sib2, iclass 26, count 0 2006.169.07:34:56.45#ibcon#*after write, iclass 26, count 0 2006.169.07:34:56.45#ibcon#*before return 0, iclass 26, count 0 2006.169.07:34:56.45#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.169.07:34:56.45#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.169.07:34:56.45#ibcon#about to clear, iclass 26 cls_cnt 0 2006.169.07:34:56.45#ibcon#cleared, iclass 26 cls_cnt 0 2006.169.07:34:56.45$vc4f8/valo=6,772.99 2006.169.07:34:56.45#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.169.07:34:56.45#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.169.07:34:56.45#ibcon#ireg 17 cls_cnt 0 2006.169.07:34:56.45#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:34:56.45#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:34:56.45#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:34:56.45#ibcon#enter wrdev, iclass 28, count 0 2006.169.07:34:56.45#ibcon#first serial, iclass 28, count 0 2006.169.07:34:56.45#ibcon#enter sib2, iclass 28, count 0 2006.169.07:34:56.45#ibcon#flushed, iclass 28, count 0 2006.169.07:34:56.45#ibcon#about to write, iclass 28, count 0 2006.169.07:34:56.45#ibcon#wrote, iclass 28, count 0 2006.169.07:34:56.45#ibcon#about to read 3, iclass 28, count 0 2006.169.07:34:56.47#ibcon#read 3, iclass 28, count 0 2006.169.07:34:56.47#ibcon#about to read 4, iclass 28, count 0 2006.169.07:34:56.47#ibcon#read 4, iclass 28, count 0 2006.169.07:34:56.47#ibcon#about to read 5, iclass 28, count 0 2006.169.07:34:56.47#ibcon#read 5, iclass 28, count 0 2006.169.07:34:56.47#ibcon#about to read 6, iclass 28, count 0 2006.169.07:34:56.47#ibcon#read 6, iclass 28, count 0 2006.169.07:34:56.47#ibcon#end of sib2, iclass 28, count 0 2006.169.07:34:56.47#ibcon#*mode == 0, iclass 28, count 0 2006.169.07:34:56.47#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.169.07:34:56.47#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.07:34:56.47#ibcon#*before write, iclass 28, count 0 2006.169.07:34:56.47#ibcon#enter sib2, iclass 28, count 0 2006.169.07:34:56.47#ibcon#flushed, iclass 28, count 0 2006.169.07:34:56.47#ibcon#about to write, iclass 28, count 0 2006.169.07:34:56.47#ibcon#wrote, iclass 28, count 0 2006.169.07:34:56.47#ibcon#about to read 3, iclass 28, count 0 2006.169.07:34:56.51#ibcon#read 3, iclass 28, count 0 2006.169.07:34:56.51#ibcon#about to read 4, iclass 28, count 0 2006.169.07:34:56.51#ibcon#read 4, iclass 28, count 0 2006.169.07:34:56.51#ibcon#about to read 5, iclass 28, count 0 2006.169.07:34:56.51#ibcon#read 5, iclass 28, count 0 2006.169.07:34:56.51#ibcon#about to read 6, iclass 28, count 0 2006.169.07:34:56.51#ibcon#read 6, iclass 28, count 0 2006.169.07:34:56.51#ibcon#end of sib2, iclass 28, count 0 2006.169.07:34:56.51#ibcon#*after write, iclass 28, count 0 2006.169.07:34:56.51#ibcon#*before return 0, iclass 28, count 0 2006.169.07:34:56.51#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:34:56.51#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:34:56.51#ibcon#about to clear, iclass 28 cls_cnt 0 2006.169.07:34:56.51#ibcon#cleared, iclass 28 cls_cnt 0 2006.169.07:34:56.51$vc4f8/va=6,6 2006.169.07:34:56.51#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.169.07:34:56.51#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.169.07:34:56.51#ibcon#ireg 11 cls_cnt 2 2006.169.07:34:56.51#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:34:56.57#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:34:56.57#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:34:56.57#ibcon#enter wrdev, iclass 30, count 2 2006.169.07:34:56.57#ibcon#first serial, iclass 30, count 2 2006.169.07:34:56.57#ibcon#enter sib2, iclass 30, count 2 2006.169.07:34:56.57#ibcon#flushed, iclass 30, count 2 2006.169.07:34:56.57#ibcon#about to write, iclass 30, count 2 2006.169.07:34:56.57#ibcon#wrote, iclass 30, count 2 2006.169.07:34:56.57#ibcon#about to read 3, iclass 30, count 2 2006.169.07:34:56.59#ibcon#read 3, iclass 30, count 2 2006.169.07:34:56.59#ibcon#about to read 4, iclass 30, count 2 2006.169.07:34:56.59#ibcon#read 4, iclass 30, count 2 2006.169.07:34:56.59#ibcon#about to read 5, iclass 30, count 2 2006.169.07:34:56.59#ibcon#read 5, iclass 30, count 2 2006.169.07:34:56.59#ibcon#about to read 6, iclass 30, count 2 2006.169.07:34:56.59#ibcon#read 6, iclass 30, count 2 2006.169.07:34:56.59#ibcon#end of sib2, iclass 30, count 2 2006.169.07:34:56.59#ibcon#*mode == 0, iclass 30, count 2 2006.169.07:34:56.59#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.169.07:34:56.59#ibcon#[25=AT06-06\r\n] 2006.169.07:34:56.59#ibcon#*before write, iclass 30, count 2 2006.169.07:34:56.59#ibcon#enter sib2, iclass 30, count 2 2006.169.07:34:56.59#ibcon#flushed, iclass 30, count 2 2006.169.07:34:56.59#ibcon#about to write, iclass 30, count 2 2006.169.07:34:56.59#ibcon#wrote, iclass 30, count 2 2006.169.07:34:56.59#ibcon#about to read 3, iclass 30, count 2 2006.169.07:34:56.62#ibcon#read 3, iclass 30, count 2 2006.169.07:34:56.62#ibcon#about to read 4, iclass 30, count 2 2006.169.07:34:56.62#ibcon#read 4, iclass 30, count 2 2006.169.07:34:56.62#ibcon#about to read 5, iclass 30, count 2 2006.169.07:34:56.62#ibcon#read 5, iclass 30, count 2 2006.169.07:34:56.62#ibcon#about to read 6, iclass 30, count 2 2006.169.07:34:56.62#ibcon#read 6, iclass 30, count 2 2006.169.07:34:56.62#ibcon#end of sib2, iclass 30, count 2 2006.169.07:34:56.62#ibcon#*after write, iclass 30, count 2 2006.169.07:34:56.62#ibcon#*before return 0, iclass 30, count 2 2006.169.07:34:56.62#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:34:56.62#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:34:56.62#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.169.07:34:56.62#ibcon#ireg 7 cls_cnt 0 2006.169.07:34:56.62#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:34:56.74#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:34:56.74#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:34:56.74#ibcon#enter wrdev, iclass 30, count 0 2006.169.07:34:56.74#ibcon#first serial, iclass 30, count 0 2006.169.07:34:56.74#ibcon#enter sib2, iclass 30, count 0 2006.169.07:34:56.74#ibcon#flushed, iclass 30, count 0 2006.169.07:34:56.74#ibcon#about to write, iclass 30, count 0 2006.169.07:34:56.74#ibcon#wrote, iclass 30, count 0 2006.169.07:34:56.74#ibcon#about to read 3, iclass 30, count 0 2006.169.07:34:56.76#ibcon#read 3, iclass 30, count 0 2006.169.07:34:56.76#ibcon#about to read 4, iclass 30, count 0 2006.169.07:34:56.76#ibcon#read 4, iclass 30, count 0 2006.169.07:34:56.76#ibcon#about to read 5, iclass 30, count 0 2006.169.07:34:56.76#ibcon#read 5, iclass 30, count 0 2006.169.07:34:56.76#ibcon#about to read 6, iclass 30, count 0 2006.169.07:34:56.76#ibcon#read 6, iclass 30, count 0 2006.169.07:34:56.76#ibcon#end of sib2, iclass 30, count 0 2006.169.07:34:56.76#ibcon#*mode == 0, iclass 30, count 0 2006.169.07:34:56.76#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.169.07:34:56.76#ibcon#[25=USB\r\n] 2006.169.07:34:56.76#ibcon#*before write, iclass 30, count 0 2006.169.07:34:56.76#ibcon#enter sib2, iclass 30, count 0 2006.169.07:34:56.76#ibcon#flushed, iclass 30, count 0 2006.169.07:34:56.76#ibcon#about to write, iclass 30, count 0 2006.169.07:34:56.76#ibcon#wrote, iclass 30, count 0 2006.169.07:34:56.76#ibcon#about to read 3, iclass 30, count 0 2006.169.07:34:56.79#ibcon#read 3, iclass 30, count 0 2006.169.07:34:56.79#ibcon#about to read 4, iclass 30, count 0 2006.169.07:34:56.79#ibcon#read 4, iclass 30, count 0 2006.169.07:34:56.79#ibcon#about to read 5, iclass 30, count 0 2006.169.07:34:56.79#ibcon#read 5, iclass 30, count 0 2006.169.07:34:56.79#ibcon#about to read 6, iclass 30, count 0 2006.169.07:34:56.79#ibcon#read 6, iclass 30, count 0 2006.169.07:34:56.79#ibcon#end of sib2, iclass 30, count 0 2006.169.07:34:56.79#ibcon#*after write, iclass 30, count 0 2006.169.07:34:56.79#ibcon#*before return 0, iclass 30, count 0 2006.169.07:34:56.79#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:34:56.79#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:34:56.79#ibcon#about to clear, iclass 30 cls_cnt 0 2006.169.07:34:56.79#ibcon#cleared, iclass 30 cls_cnt 0 2006.169.07:34:56.79$vc4f8/valo=7,832.99 2006.169.07:34:56.79#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.169.07:34:56.79#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.169.07:34:56.79#ibcon#ireg 17 cls_cnt 0 2006.169.07:34:56.79#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:34:56.79#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:34:56.79#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:34:56.79#ibcon#enter wrdev, iclass 32, count 0 2006.169.07:34:56.79#ibcon#first serial, iclass 32, count 0 2006.169.07:34:56.79#ibcon#enter sib2, iclass 32, count 0 2006.169.07:34:56.79#ibcon#flushed, iclass 32, count 0 2006.169.07:34:56.79#ibcon#about to write, iclass 32, count 0 2006.169.07:34:56.79#ibcon#wrote, iclass 32, count 0 2006.169.07:34:56.79#ibcon#about to read 3, iclass 32, count 0 2006.169.07:34:56.81#ibcon#read 3, iclass 32, count 0 2006.169.07:34:56.81#ibcon#about to read 4, iclass 32, count 0 2006.169.07:34:56.81#ibcon#read 4, iclass 32, count 0 2006.169.07:34:56.81#ibcon#about to read 5, iclass 32, count 0 2006.169.07:34:56.81#ibcon#read 5, iclass 32, count 0 2006.169.07:34:56.81#ibcon#about to read 6, iclass 32, count 0 2006.169.07:34:56.81#ibcon#read 6, iclass 32, count 0 2006.169.07:34:56.81#ibcon#end of sib2, iclass 32, count 0 2006.169.07:34:56.81#ibcon#*mode == 0, iclass 32, count 0 2006.169.07:34:56.81#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.169.07:34:56.81#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.07:34:56.81#ibcon#*before write, iclass 32, count 0 2006.169.07:34:56.81#ibcon#enter sib2, iclass 32, count 0 2006.169.07:34:56.81#ibcon#flushed, iclass 32, count 0 2006.169.07:34:56.81#ibcon#about to write, iclass 32, count 0 2006.169.07:34:56.81#ibcon#wrote, iclass 32, count 0 2006.169.07:34:56.81#ibcon#about to read 3, iclass 32, count 0 2006.169.07:34:56.85#ibcon#read 3, iclass 32, count 0 2006.169.07:34:56.85#ibcon#about to read 4, iclass 32, count 0 2006.169.07:34:56.85#ibcon#read 4, iclass 32, count 0 2006.169.07:34:56.85#ibcon#about to read 5, iclass 32, count 0 2006.169.07:34:56.85#ibcon#read 5, iclass 32, count 0 2006.169.07:34:56.85#ibcon#about to read 6, iclass 32, count 0 2006.169.07:34:56.85#ibcon#read 6, iclass 32, count 0 2006.169.07:34:56.85#ibcon#end of sib2, iclass 32, count 0 2006.169.07:34:56.85#ibcon#*after write, iclass 32, count 0 2006.169.07:34:56.85#ibcon#*before return 0, iclass 32, count 0 2006.169.07:34:56.85#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:34:56.85#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:34:56.85#ibcon#about to clear, iclass 32 cls_cnt 0 2006.169.07:34:56.85#ibcon#cleared, iclass 32 cls_cnt 0 2006.169.07:34:56.85$vc4f8/va=7,6 2006.169.07:34:56.85#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.169.07:34:56.85#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.169.07:34:56.85#ibcon#ireg 11 cls_cnt 2 2006.169.07:34:56.85#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.169.07:34:56.91#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.169.07:34:56.91#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.169.07:34:56.91#ibcon#enter wrdev, iclass 34, count 2 2006.169.07:34:56.91#ibcon#first serial, iclass 34, count 2 2006.169.07:34:56.91#ibcon#enter sib2, iclass 34, count 2 2006.169.07:34:56.91#ibcon#flushed, iclass 34, count 2 2006.169.07:34:56.91#ibcon#about to write, iclass 34, count 2 2006.169.07:34:56.91#ibcon#wrote, iclass 34, count 2 2006.169.07:34:56.91#ibcon#about to read 3, iclass 34, count 2 2006.169.07:34:56.93#ibcon#read 3, iclass 34, count 2 2006.169.07:34:56.93#ibcon#about to read 4, iclass 34, count 2 2006.169.07:34:56.93#ibcon#read 4, iclass 34, count 2 2006.169.07:34:56.93#ibcon#about to read 5, iclass 34, count 2 2006.169.07:34:56.93#ibcon#read 5, iclass 34, count 2 2006.169.07:34:56.93#ibcon#about to read 6, iclass 34, count 2 2006.169.07:34:56.93#ibcon#read 6, iclass 34, count 2 2006.169.07:34:56.93#ibcon#end of sib2, iclass 34, count 2 2006.169.07:34:56.93#ibcon#*mode == 0, iclass 34, count 2 2006.169.07:34:56.93#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.169.07:34:56.93#ibcon#[25=AT07-06\r\n] 2006.169.07:34:56.93#ibcon#*before write, iclass 34, count 2 2006.169.07:34:56.93#ibcon#enter sib2, iclass 34, count 2 2006.169.07:34:56.93#ibcon#flushed, iclass 34, count 2 2006.169.07:34:56.93#ibcon#about to write, iclass 34, count 2 2006.169.07:34:56.93#ibcon#wrote, iclass 34, count 2 2006.169.07:34:56.93#ibcon#about to read 3, iclass 34, count 2 2006.169.07:34:56.96#ibcon#read 3, iclass 34, count 2 2006.169.07:34:56.96#ibcon#about to read 4, iclass 34, count 2 2006.169.07:34:56.96#ibcon#read 4, iclass 34, count 2 2006.169.07:34:56.96#ibcon#about to read 5, iclass 34, count 2 2006.169.07:34:56.96#ibcon#read 5, iclass 34, count 2 2006.169.07:34:56.96#ibcon#about to read 6, iclass 34, count 2 2006.169.07:34:56.96#ibcon#read 6, iclass 34, count 2 2006.169.07:34:56.96#ibcon#end of sib2, iclass 34, count 2 2006.169.07:34:56.96#ibcon#*after write, iclass 34, count 2 2006.169.07:34:56.96#ibcon#*before return 0, iclass 34, count 2 2006.169.07:34:56.96#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.169.07:34:56.96#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.169.07:34:56.96#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.169.07:34:56.96#ibcon#ireg 7 cls_cnt 0 2006.169.07:34:56.96#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.169.07:34:57.08#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.169.07:34:57.08#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.169.07:34:57.08#ibcon#enter wrdev, iclass 34, count 0 2006.169.07:34:57.08#ibcon#first serial, iclass 34, count 0 2006.169.07:34:57.08#ibcon#enter sib2, iclass 34, count 0 2006.169.07:34:57.08#ibcon#flushed, iclass 34, count 0 2006.169.07:34:57.08#ibcon#about to write, iclass 34, count 0 2006.169.07:34:57.08#ibcon#wrote, iclass 34, count 0 2006.169.07:34:57.08#ibcon#about to read 3, iclass 34, count 0 2006.169.07:34:57.10#ibcon#read 3, iclass 34, count 0 2006.169.07:34:57.10#ibcon#about to read 4, iclass 34, count 0 2006.169.07:34:57.10#ibcon#read 4, iclass 34, count 0 2006.169.07:34:57.10#ibcon#about to read 5, iclass 34, count 0 2006.169.07:34:57.10#ibcon#read 5, iclass 34, count 0 2006.169.07:34:57.10#ibcon#about to read 6, iclass 34, count 0 2006.169.07:34:57.10#ibcon#read 6, iclass 34, count 0 2006.169.07:34:57.10#ibcon#end of sib2, iclass 34, count 0 2006.169.07:34:57.10#ibcon#*mode == 0, iclass 34, count 0 2006.169.07:34:57.10#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.169.07:34:57.10#ibcon#[25=USB\r\n] 2006.169.07:34:57.10#ibcon#*before write, iclass 34, count 0 2006.169.07:34:57.10#ibcon#enter sib2, iclass 34, count 0 2006.169.07:34:57.10#ibcon#flushed, iclass 34, count 0 2006.169.07:34:57.10#ibcon#about to write, iclass 34, count 0 2006.169.07:34:57.10#ibcon#wrote, iclass 34, count 0 2006.169.07:34:57.10#ibcon#about to read 3, iclass 34, count 0 2006.169.07:34:57.13#ibcon#read 3, iclass 34, count 0 2006.169.07:34:57.13#ibcon#about to read 4, iclass 34, count 0 2006.169.07:34:57.13#ibcon#read 4, iclass 34, count 0 2006.169.07:34:57.13#ibcon#about to read 5, iclass 34, count 0 2006.169.07:34:57.13#ibcon#read 5, iclass 34, count 0 2006.169.07:34:57.13#ibcon#about to read 6, iclass 34, count 0 2006.169.07:34:57.13#ibcon#read 6, iclass 34, count 0 2006.169.07:34:57.13#ibcon#end of sib2, iclass 34, count 0 2006.169.07:34:57.13#ibcon#*after write, iclass 34, count 0 2006.169.07:34:57.13#ibcon#*before return 0, iclass 34, count 0 2006.169.07:34:57.13#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.169.07:34:57.13#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.169.07:34:57.13#ibcon#about to clear, iclass 34 cls_cnt 0 2006.169.07:34:57.13#ibcon#cleared, iclass 34 cls_cnt 0 2006.169.07:34:57.13$vc4f8/valo=8,852.99 2006.169.07:34:57.13#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.169.07:34:57.13#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.169.07:34:57.13#ibcon#ireg 17 cls_cnt 0 2006.169.07:34:57.13#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.169.07:34:57.13#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.169.07:34:57.13#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.169.07:34:57.13#ibcon#enter wrdev, iclass 36, count 0 2006.169.07:34:57.13#ibcon#first serial, iclass 36, count 0 2006.169.07:34:57.13#ibcon#enter sib2, iclass 36, count 0 2006.169.07:34:57.13#ibcon#flushed, iclass 36, count 0 2006.169.07:34:57.13#ibcon#about to write, iclass 36, count 0 2006.169.07:34:57.13#ibcon#wrote, iclass 36, count 0 2006.169.07:34:57.13#ibcon#about to read 3, iclass 36, count 0 2006.169.07:34:57.15#ibcon#read 3, iclass 36, count 0 2006.169.07:34:57.15#ibcon#about to read 4, iclass 36, count 0 2006.169.07:34:57.15#ibcon#read 4, iclass 36, count 0 2006.169.07:34:57.15#ibcon#about to read 5, iclass 36, count 0 2006.169.07:34:57.15#ibcon#read 5, iclass 36, count 0 2006.169.07:34:57.15#ibcon#about to read 6, iclass 36, count 0 2006.169.07:34:57.15#ibcon#read 6, iclass 36, count 0 2006.169.07:34:57.15#ibcon#end of sib2, iclass 36, count 0 2006.169.07:34:57.15#ibcon#*mode == 0, iclass 36, count 0 2006.169.07:34:57.15#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.169.07:34:57.15#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.07:34:57.15#ibcon#*before write, iclass 36, count 0 2006.169.07:34:57.15#ibcon#enter sib2, iclass 36, count 0 2006.169.07:34:57.15#ibcon#flushed, iclass 36, count 0 2006.169.07:34:57.15#ibcon#about to write, iclass 36, count 0 2006.169.07:34:57.15#ibcon#wrote, iclass 36, count 0 2006.169.07:34:57.15#ibcon#about to read 3, iclass 36, count 0 2006.169.07:34:57.19#ibcon#read 3, iclass 36, count 0 2006.169.07:34:57.19#ibcon#about to read 4, iclass 36, count 0 2006.169.07:34:57.19#ibcon#read 4, iclass 36, count 0 2006.169.07:34:57.19#ibcon#about to read 5, iclass 36, count 0 2006.169.07:34:57.19#ibcon#read 5, iclass 36, count 0 2006.169.07:34:57.19#ibcon#about to read 6, iclass 36, count 0 2006.169.07:34:57.19#ibcon#read 6, iclass 36, count 0 2006.169.07:34:57.19#ibcon#end of sib2, iclass 36, count 0 2006.169.07:34:57.19#ibcon#*after write, iclass 36, count 0 2006.169.07:34:57.19#ibcon#*before return 0, iclass 36, count 0 2006.169.07:34:57.19#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.169.07:34:57.19#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.169.07:34:57.19#ibcon#about to clear, iclass 36 cls_cnt 0 2006.169.07:34:57.19#ibcon#cleared, iclass 36 cls_cnt 0 2006.169.07:34:57.19$vc4f8/va=8,7 2006.169.07:34:57.19#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.169.07:34:57.19#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.169.07:34:57.19#ibcon#ireg 11 cls_cnt 2 2006.169.07:34:57.19#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.169.07:34:57.25#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.169.07:34:57.25#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.169.07:34:57.25#ibcon#enter wrdev, iclass 38, count 2 2006.169.07:34:57.25#ibcon#first serial, iclass 38, count 2 2006.169.07:34:57.25#ibcon#enter sib2, iclass 38, count 2 2006.169.07:34:57.25#ibcon#flushed, iclass 38, count 2 2006.169.07:34:57.25#ibcon#about to write, iclass 38, count 2 2006.169.07:34:57.25#ibcon#wrote, iclass 38, count 2 2006.169.07:34:57.25#ibcon#about to read 3, iclass 38, count 2 2006.169.07:34:57.27#ibcon#read 3, iclass 38, count 2 2006.169.07:34:57.27#ibcon#about to read 4, iclass 38, count 2 2006.169.07:34:57.27#ibcon#read 4, iclass 38, count 2 2006.169.07:34:57.27#ibcon#about to read 5, iclass 38, count 2 2006.169.07:34:57.27#ibcon#read 5, iclass 38, count 2 2006.169.07:34:57.27#ibcon#about to read 6, iclass 38, count 2 2006.169.07:34:57.27#ibcon#read 6, iclass 38, count 2 2006.169.07:34:57.27#ibcon#end of sib2, iclass 38, count 2 2006.169.07:34:57.27#ibcon#*mode == 0, iclass 38, count 2 2006.169.07:34:57.27#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.169.07:34:57.27#ibcon#[25=AT08-07\r\n] 2006.169.07:34:57.27#ibcon#*before write, iclass 38, count 2 2006.169.07:34:57.27#ibcon#enter sib2, iclass 38, count 2 2006.169.07:34:57.27#ibcon#flushed, iclass 38, count 2 2006.169.07:34:57.27#ibcon#about to write, iclass 38, count 2 2006.169.07:34:57.27#ibcon#wrote, iclass 38, count 2 2006.169.07:34:57.27#ibcon#about to read 3, iclass 38, count 2 2006.169.07:34:57.30#ibcon#read 3, iclass 38, count 2 2006.169.07:34:57.30#ibcon#about to read 4, iclass 38, count 2 2006.169.07:34:57.30#ibcon#read 4, iclass 38, count 2 2006.169.07:34:57.30#ibcon#about to read 5, iclass 38, count 2 2006.169.07:34:57.30#ibcon#read 5, iclass 38, count 2 2006.169.07:34:57.30#ibcon#about to read 6, iclass 38, count 2 2006.169.07:34:57.30#ibcon#read 6, iclass 38, count 2 2006.169.07:34:57.30#ibcon#end of sib2, iclass 38, count 2 2006.169.07:34:57.30#ibcon#*after write, iclass 38, count 2 2006.169.07:34:57.30#ibcon#*before return 0, iclass 38, count 2 2006.169.07:34:57.30#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.169.07:34:57.30#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.169.07:34:57.30#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.169.07:34:57.30#ibcon#ireg 7 cls_cnt 0 2006.169.07:34:57.30#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.169.07:34:57.42#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.169.07:34:57.42#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.169.07:34:57.42#ibcon#enter wrdev, iclass 38, count 0 2006.169.07:34:57.42#ibcon#first serial, iclass 38, count 0 2006.169.07:34:57.42#ibcon#enter sib2, iclass 38, count 0 2006.169.07:34:57.42#ibcon#flushed, iclass 38, count 0 2006.169.07:34:57.42#ibcon#about to write, iclass 38, count 0 2006.169.07:34:57.42#ibcon#wrote, iclass 38, count 0 2006.169.07:34:57.42#ibcon#about to read 3, iclass 38, count 0 2006.169.07:34:57.44#ibcon#read 3, iclass 38, count 0 2006.169.07:34:57.44#ibcon#about to read 4, iclass 38, count 0 2006.169.07:34:57.44#ibcon#read 4, iclass 38, count 0 2006.169.07:34:57.44#ibcon#about to read 5, iclass 38, count 0 2006.169.07:34:57.44#ibcon#read 5, iclass 38, count 0 2006.169.07:34:57.44#ibcon#about to read 6, iclass 38, count 0 2006.169.07:34:57.44#ibcon#read 6, iclass 38, count 0 2006.169.07:34:57.44#ibcon#end of sib2, iclass 38, count 0 2006.169.07:34:57.44#ibcon#*mode == 0, iclass 38, count 0 2006.169.07:34:57.44#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.169.07:34:57.44#ibcon#[25=USB\r\n] 2006.169.07:34:57.44#ibcon#*before write, iclass 38, count 0 2006.169.07:34:57.44#ibcon#enter sib2, iclass 38, count 0 2006.169.07:34:57.44#ibcon#flushed, iclass 38, count 0 2006.169.07:34:57.44#ibcon#about to write, iclass 38, count 0 2006.169.07:34:57.44#ibcon#wrote, iclass 38, count 0 2006.169.07:34:57.44#ibcon#about to read 3, iclass 38, count 0 2006.169.07:34:57.47#ibcon#read 3, iclass 38, count 0 2006.169.07:34:57.47#ibcon#about to read 4, iclass 38, count 0 2006.169.07:34:57.47#ibcon#read 4, iclass 38, count 0 2006.169.07:34:57.47#ibcon#about to read 5, iclass 38, count 0 2006.169.07:34:57.47#ibcon#read 5, iclass 38, count 0 2006.169.07:34:57.47#ibcon#about to read 6, iclass 38, count 0 2006.169.07:34:57.47#ibcon#read 6, iclass 38, count 0 2006.169.07:34:57.47#ibcon#end of sib2, iclass 38, count 0 2006.169.07:34:57.47#ibcon#*after write, iclass 38, count 0 2006.169.07:34:57.47#ibcon#*before return 0, iclass 38, count 0 2006.169.07:34:57.47#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.169.07:34:57.47#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.169.07:34:57.47#ibcon#about to clear, iclass 38 cls_cnt 0 2006.169.07:34:57.47#ibcon#cleared, iclass 38 cls_cnt 0 2006.169.07:34:57.47$vc4f8/vblo=1,632.99 2006.169.07:34:57.47#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.169.07:34:57.47#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.169.07:34:57.47#ibcon#ireg 17 cls_cnt 0 2006.169.07:34:57.47#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:34:57.47#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:34:57.47#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:34:57.47#ibcon#enter wrdev, iclass 40, count 0 2006.169.07:34:57.47#ibcon#first serial, iclass 40, count 0 2006.169.07:34:57.47#ibcon#enter sib2, iclass 40, count 0 2006.169.07:34:57.47#ibcon#flushed, iclass 40, count 0 2006.169.07:34:57.47#ibcon#about to write, iclass 40, count 0 2006.169.07:34:57.47#ibcon#wrote, iclass 40, count 0 2006.169.07:34:57.47#ibcon#about to read 3, iclass 40, count 0 2006.169.07:34:57.49#ibcon#read 3, iclass 40, count 0 2006.169.07:34:57.49#ibcon#about to read 4, iclass 40, count 0 2006.169.07:34:57.49#ibcon#read 4, iclass 40, count 0 2006.169.07:34:57.49#ibcon#about to read 5, iclass 40, count 0 2006.169.07:34:57.49#ibcon#read 5, iclass 40, count 0 2006.169.07:34:57.49#ibcon#about to read 6, iclass 40, count 0 2006.169.07:34:57.49#ibcon#read 6, iclass 40, count 0 2006.169.07:34:57.49#ibcon#end of sib2, iclass 40, count 0 2006.169.07:34:57.49#ibcon#*mode == 0, iclass 40, count 0 2006.169.07:34:57.49#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.169.07:34:57.49#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.07:34:57.49#ibcon#*before write, iclass 40, count 0 2006.169.07:34:57.49#ibcon#enter sib2, iclass 40, count 0 2006.169.07:34:57.49#ibcon#flushed, iclass 40, count 0 2006.169.07:34:57.49#ibcon#about to write, iclass 40, count 0 2006.169.07:34:57.49#ibcon#wrote, iclass 40, count 0 2006.169.07:34:57.49#ibcon#about to read 3, iclass 40, count 0 2006.169.07:34:57.53#ibcon#read 3, iclass 40, count 0 2006.169.07:34:57.53#ibcon#about to read 4, iclass 40, count 0 2006.169.07:34:57.53#ibcon#read 4, iclass 40, count 0 2006.169.07:34:57.53#ibcon#about to read 5, iclass 40, count 0 2006.169.07:34:57.53#ibcon#read 5, iclass 40, count 0 2006.169.07:34:57.53#ibcon#about to read 6, iclass 40, count 0 2006.169.07:34:57.53#ibcon#read 6, iclass 40, count 0 2006.169.07:34:57.53#ibcon#end of sib2, iclass 40, count 0 2006.169.07:34:57.53#ibcon#*after write, iclass 40, count 0 2006.169.07:34:57.53#ibcon#*before return 0, iclass 40, count 0 2006.169.07:34:57.53#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:34:57.53#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:34:57.53#ibcon#about to clear, iclass 40 cls_cnt 0 2006.169.07:34:57.53#ibcon#cleared, iclass 40 cls_cnt 0 2006.169.07:34:57.53$vc4f8/vb=1,4 2006.169.07:34:57.53#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.169.07:34:57.53#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.169.07:34:57.53#ibcon#ireg 11 cls_cnt 2 2006.169.07:34:57.53#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.169.07:34:57.53#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.169.07:34:57.53#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.169.07:34:57.53#ibcon#enter wrdev, iclass 4, count 2 2006.169.07:34:57.53#ibcon#first serial, iclass 4, count 2 2006.169.07:34:57.53#ibcon#enter sib2, iclass 4, count 2 2006.169.07:34:57.53#ibcon#flushed, iclass 4, count 2 2006.169.07:34:57.53#ibcon#about to write, iclass 4, count 2 2006.169.07:34:57.53#ibcon#wrote, iclass 4, count 2 2006.169.07:34:57.53#ibcon#about to read 3, iclass 4, count 2 2006.169.07:34:57.55#ibcon#read 3, iclass 4, count 2 2006.169.07:34:57.55#ibcon#about to read 4, iclass 4, count 2 2006.169.07:34:57.55#ibcon#read 4, iclass 4, count 2 2006.169.07:34:57.55#ibcon#about to read 5, iclass 4, count 2 2006.169.07:34:57.55#ibcon#read 5, iclass 4, count 2 2006.169.07:34:57.55#ibcon#about to read 6, iclass 4, count 2 2006.169.07:34:57.55#ibcon#read 6, iclass 4, count 2 2006.169.07:34:57.55#ibcon#end of sib2, iclass 4, count 2 2006.169.07:34:57.55#ibcon#*mode == 0, iclass 4, count 2 2006.169.07:34:57.55#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.169.07:34:57.55#ibcon#[27=AT01-04\r\n] 2006.169.07:34:57.55#ibcon#*before write, iclass 4, count 2 2006.169.07:34:57.55#ibcon#enter sib2, iclass 4, count 2 2006.169.07:34:57.55#ibcon#flushed, iclass 4, count 2 2006.169.07:34:57.55#ibcon#about to write, iclass 4, count 2 2006.169.07:34:57.55#ibcon#wrote, iclass 4, count 2 2006.169.07:34:57.55#ibcon#about to read 3, iclass 4, count 2 2006.169.07:34:57.58#ibcon#read 3, iclass 4, count 2 2006.169.07:34:57.58#ibcon#about to read 4, iclass 4, count 2 2006.169.07:34:57.58#ibcon#read 4, iclass 4, count 2 2006.169.07:34:57.58#ibcon#about to read 5, iclass 4, count 2 2006.169.07:34:57.58#ibcon#read 5, iclass 4, count 2 2006.169.07:34:57.58#ibcon#about to read 6, iclass 4, count 2 2006.169.07:34:57.58#ibcon#read 6, iclass 4, count 2 2006.169.07:34:57.58#ibcon#end of sib2, iclass 4, count 2 2006.169.07:34:57.58#ibcon#*after write, iclass 4, count 2 2006.169.07:34:57.58#ibcon#*before return 0, iclass 4, count 2 2006.169.07:34:57.58#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.169.07:34:57.58#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.169.07:34:57.58#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.169.07:34:57.58#ibcon#ireg 7 cls_cnt 0 2006.169.07:34:57.58#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.169.07:34:57.70#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.169.07:34:57.70#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.169.07:34:57.70#ibcon#enter wrdev, iclass 4, count 0 2006.169.07:34:57.70#ibcon#first serial, iclass 4, count 0 2006.169.07:34:57.70#ibcon#enter sib2, iclass 4, count 0 2006.169.07:34:57.70#ibcon#flushed, iclass 4, count 0 2006.169.07:34:57.70#ibcon#about to write, iclass 4, count 0 2006.169.07:34:57.70#ibcon#wrote, iclass 4, count 0 2006.169.07:34:57.70#ibcon#about to read 3, iclass 4, count 0 2006.169.07:34:57.72#ibcon#read 3, iclass 4, count 0 2006.169.07:34:57.72#ibcon#about to read 4, iclass 4, count 0 2006.169.07:34:57.72#ibcon#read 4, iclass 4, count 0 2006.169.07:34:57.72#ibcon#about to read 5, iclass 4, count 0 2006.169.07:34:57.72#ibcon#read 5, iclass 4, count 0 2006.169.07:34:57.72#ibcon#about to read 6, iclass 4, count 0 2006.169.07:34:57.72#ibcon#read 6, iclass 4, count 0 2006.169.07:34:57.72#ibcon#end of sib2, iclass 4, count 0 2006.169.07:34:57.72#ibcon#*mode == 0, iclass 4, count 0 2006.169.07:34:57.72#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.169.07:34:57.72#ibcon#[27=USB\r\n] 2006.169.07:34:57.72#ibcon#*before write, iclass 4, count 0 2006.169.07:34:57.72#ibcon#enter sib2, iclass 4, count 0 2006.169.07:34:57.72#ibcon#flushed, iclass 4, count 0 2006.169.07:34:57.72#ibcon#about to write, iclass 4, count 0 2006.169.07:34:57.72#ibcon#wrote, iclass 4, count 0 2006.169.07:34:57.72#ibcon#about to read 3, iclass 4, count 0 2006.169.07:34:57.75#ibcon#read 3, iclass 4, count 0 2006.169.07:34:57.75#ibcon#about to read 4, iclass 4, count 0 2006.169.07:34:57.75#ibcon#read 4, iclass 4, count 0 2006.169.07:34:57.75#ibcon#about to read 5, iclass 4, count 0 2006.169.07:34:57.75#ibcon#read 5, iclass 4, count 0 2006.169.07:34:57.75#ibcon#about to read 6, iclass 4, count 0 2006.169.07:34:57.75#ibcon#read 6, iclass 4, count 0 2006.169.07:34:57.75#ibcon#end of sib2, iclass 4, count 0 2006.169.07:34:57.75#ibcon#*after write, iclass 4, count 0 2006.169.07:34:57.75#ibcon#*before return 0, iclass 4, count 0 2006.169.07:34:57.75#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.169.07:34:57.75#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.169.07:34:57.75#ibcon#about to clear, iclass 4 cls_cnt 0 2006.169.07:34:57.75#ibcon#cleared, iclass 4 cls_cnt 0 2006.169.07:34:57.75$vc4f8/vblo=2,640.99 2006.169.07:34:57.75#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.169.07:34:57.75#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.169.07:34:57.75#ibcon#ireg 17 cls_cnt 0 2006.169.07:34:57.75#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:34:57.75#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:34:57.75#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:34:57.75#ibcon#enter wrdev, iclass 6, count 0 2006.169.07:34:57.75#ibcon#first serial, iclass 6, count 0 2006.169.07:34:57.75#ibcon#enter sib2, iclass 6, count 0 2006.169.07:34:57.75#ibcon#flushed, iclass 6, count 0 2006.169.07:34:57.75#ibcon#about to write, iclass 6, count 0 2006.169.07:34:57.75#ibcon#wrote, iclass 6, count 0 2006.169.07:34:57.75#ibcon#about to read 3, iclass 6, count 0 2006.169.07:34:57.77#ibcon#read 3, iclass 6, count 0 2006.169.07:34:57.77#ibcon#about to read 4, iclass 6, count 0 2006.169.07:34:57.77#ibcon#read 4, iclass 6, count 0 2006.169.07:34:57.77#ibcon#about to read 5, iclass 6, count 0 2006.169.07:34:57.77#ibcon#read 5, iclass 6, count 0 2006.169.07:34:57.77#ibcon#about to read 6, iclass 6, count 0 2006.169.07:34:57.77#ibcon#read 6, iclass 6, count 0 2006.169.07:34:57.77#ibcon#end of sib2, iclass 6, count 0 2006.169.07:34:57.77#ibcon#*mode == 0, iclass 6, count 0 2006.169.07:34:57.77#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.169.07:34:57.77#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.07:34:57.77#ibcon#*before write, iclass 6, count 0 2006.169.07:34:57.77#ibcon#enter sib2, iclass 6, count 0 2006.169.07:34:57.77#ibcon#flushed, iclass 6, count 0 2006.169.07:34:57.77#ibcon#about to write, iclass 6, count 0 2006.169.07:34:57.77#ibcon#wrote, iclass 6, count 0 2006.169.07:34:57.77#ibcon#about to read 3, iclass 6, count 0 2006.169.07:34:57.81#ibcon#read 3, iclass 6, count 0 2006.169.07:34:57.81#ibcon#about to read 4, iclass 6, count 0 2006.169.07:34:57.81#ibcon#read 4, iclass 6, count 0 2006.169.07:34:57.81#ibcon#about to read 5, iclass 6, count 0 2006.169.07:34:57.81#ibcon#read 5, iclass 6, count 0 2006.169.07:34:57.81#ibcon#about to read 6, iclass 6, count 0 2006.169.07:34:57.81#ibcon#read 6, iclass 6, count 0 2006.169.07:34:57.81#ibcon#end of sib2, iclass 6, count 0 2006.169.07:34:57.81#ibcon#*after write, iclass 6, count 0 2006.169.07:34:57.81#ibcon#*before return 0, iclass 6, count 0 2006.169.07:34:57.81#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:34:57.81#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:34:57.81#ibcon#about to clear, iclass 6 cls_cnt 0 2006.169.07:34:57.81#ibcon#cleared, iclass 6 cls_cnt 0 2006.169.07:34:57.81$vc4f8/vb=2,4 2006.169.07:34:57.81#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.169.07:34:57.81#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.169.07:34:57.81#ibcon#ireg 11 cls_cnt 2 2006.169.07:34:57.81#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.169.07:34:57.87#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.169.07:34:57.87#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.169.07:34:57.87#ibcon#enter wrdev, iclass 10, count 2 2006.169.07:34:57.87#ibcon#first serial, iclass 10, count 2 2006.169.07:34:57.87#ibcon#enter sib2, iclass 10, count 2 2006.169.07:34:57.87#ibcon#flushed, iclass 10, count 2 2006.169.07:34:57.87#ibcon#about to write, iclass 10, count 2 2006.169.07:34:57.87#ibcon#wrote, iclass 10, count 2 2006.169.07:34:57.87#ibcon#about to read 3, iclass 10, count 2 2006.169.07:34:57.89#ibcon#read 3, iclass 10, count 2 2006.169.07:34:57.89#ibcon#about to read 4, iclass 10, count 2 2006.169.07:34:57.89#ibcon#read 4, iclass 10, count 2 2006.169.07:34:57.89#ibcon#about to read 5, iclass 10, count 2 2006.169.07:34:57.89#ibcon#read 5, iclass 10, count 2 2006.169.07:34:57.89#ibcon#about to read 6, iclass 10, count 2 2006.169.07:34:57.89#ibcon#read 6, iclass 10, count 2 2006.169.07:34:57.89#ibcon#end of sib2, iclass 10, count 2 2006.169.07:34:57.89#ibcon#*mode == 0, iclass 10, count 2 2006.169.07:34:57.89#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.169.07:34:57.89#ibcon#[27=AT02-04\r\n] 2006.169.07:34:57.89#ibcon#*before write, iclass 10, count 2 2006.169.07:34:57.89#ibcon#enter sib2, iclass 10, count 2 2006.169.07:34:57.89#ibcon#flushed, iclass 10, count 2 2006.169.07:34:57.89#ibcon#about to write, iclass 10, count 2 2006.169.07:34:57.89#ibcon#wrote, iclass 10, count 2 2006.169.07:34:57.89#ibcon#about to read 3, iclass 10, count 2 2006.169.07:34:57.92#ibcon#read 3, iclass 10, count 2 2006.169.07:34:57.92#ibcon#about to read 4, iclass 10, count 2 2006.169.07:34:57.92#ibcon#read 4, iclass 10, count 2 2006.169.07:34:57.92#ibcon#about to read 5, iclass 10, count 2 2006.169.07:34:57.92#ibcon#read 5, iclass 10, count 2 2006.169.07:34:57.92#ibcon#about to read 6, iclass 10, count 2 2006.169.07:34:57.92#ibcon#read 6, iclass 10, count 2 2006.169.07:34:57.92#ibcon#end of sib2, iclass 10, count 2 2006.169.07:34:57.92#ibcon#*after write, iclass 10, count 2 2006.169.07:34:57.92#ibcon#*before return 0, iclass 10, count 2 2006.169.07:34:57.92#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.169.07:34:57.92#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.169.07:34:57.92#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.169.07:34:57.92#ibcon#ireg 7 cls_cnt 0 2006.169.07:34:57.92#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.169.07:34:58.04#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.169.07:34:58.04#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.169.07:34:58.04#ibcon#enter wrdev, iclass 10, count 0 2006.169.07:34:58.04#ibcon#first serial, iclass 10, count 0 2006.169.07:34:58.04#ibcon#enter sib2, iclass 10, count 0 2006.169.07:34:58.04#ibcon#flushed, iclass 10, count 0 2006.169.07:34:58.04#ibcon#about to write, iclass 10, count 0 2006.169.07:34:58.04#ibcon#wrote, iclass 10, count 0 2006.169.07:34:58.04#ibcon#about to read 3, iclass 10, count 0 2006.169.07:34:58.06#ibcon#read 3, iclass 10, count 0 2006.169.07:34:58.06#ibcon#about to read 4, iclass 10, count 0 2006.169.07:34:58.06#ibcon#read 4, iclass 10, count 0 2006.169.07:34:58.06#ibcon#about to read 5, iclass 10, count 0 2006.169.07:34:58.06#ibcon#read 5, iclass 10, count 0 2006.169.07:34:58.06#ibcon#about to read 6, iclass 10, count 0 2006.169.07:34:58.06#ibcon#read 6, iclass 10, count 0 2006.169.07:34:58.06#ibcon#end of sib2, iclass 10, count 0 2006.169.07:34:58.06#ibcon#*mode == 0, iclass 10, count 0 2006.169.07:34:58.06#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.169.07:34:58.06#ibcon#[27=USB\r\n] 2006.169.07:34:58.06#ibcon#*before write, iclass 10, count 0 2006.169.07:34:58.06#ibcon#enter sib2, iclass 10, count 0 2006.169.07:34:58.06#ibcon#flushed, iclass 10, count 0 2006.169.07:34:58.06#ibcon#about to write, iclass 10, count 0 2006.169.07:34:58.06#ibcon#wrote, iclass 10, count 0 2006.169.07:34:58.06#ibcon#about to read 3, iclass 10, count 0 2006.169.07:34:58.09#ibcon#read 3, iclass 10, count 0 2006.169.07:34:58.09#ibcon#about to read 4, iclass 10, count 0 2006.169.07:34:58.09#ibcon#read 4, iclass 10, count 0 2006.169.07:34:58.09#ibcon#about to read 5, iclass 10, count 0 2006.169.07:34:58.09#ibcon#read 5, iclass 10, count 0 2006.169.07:34:58.09#ibcon#about to read 6, iclass 10, count 0 2006.169.07:34:58.09#ibcon#read 6, iclass 10, count 0 2006.169.07:34:58.09#ibcon#end of sib2, iclass 10, count 0 2006.169.07:34:58.09#ibcon#*after write, iclass 10, count 0 2006.169.07:34:58.09#ibcon#*before return 0, iclass 10, count 0 2006.169.07:34:58.09#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.169.07:34:58.09#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.169.07:34:58.09#ibcon#about to clear, iclass 10 cls_cnt 0 2006.169.07:34:58.09#ibcon#cleared, iclass 10 cls_cnt 0 2006.169.07:34:58.09$vc4f8/vblo=3,656.99 2006.169.07:34:58.09#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.169.07:34:58.09#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.169.07:34:58.09#ibcon#ireg 17 cls_cnt 0 2006.169.07:34:58.09#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.169.07:34:58.09#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.169.07:34:58.09#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.169.07:34:58.09#ibcon#enter wrdev, iclass 12, count 0 2006.169.07:34:58.09#ibcon#first serial, iclass 12, count 0 2006.169.07:34:58.09#ibcon#enter sib2, iclass 12, count 0 2006.169.07:34:58.09#ibcon#flushed, iclass 12, count 0 2006.169.07:34:58.09#ibcon#about to write, iclass 12, count 0 2006.169.07:34:58.09#ibcon#wrote, iclass 12, count 0 2006.169.07:34:58.09#ibcon#about to read 3, iclass 12, count 0 2006.169.07:34:58.11#ibcon#read 3, iclass 12, count 0 2006.169.07:34:58.11#ibcon#about to read 4, iclass 12, count 0 2006.169.07:34:58.11#ibcon#read 4, iclass 12, count 0 2006.169.07:34:58.11#ibcon#about to read 5, iclass 12, count 0 2006.169.07:34:58.11#ibcon#read 5, iclass 12, count 0 2006.169.07:34:58.11#ibcon#about to read 6, iclass 12, count 0 2006.169.07:34:58.11#ibcon#read 6, iclass 12, count 0 2006.169.07:34:58.11#ibcon#end of sib2, iclass 12, count 0 2006.169.07:34:58.11#ibcon#*mode == 0, iclass 12, count 0 2006.169.07:34:58.11#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.169.07:34:58.11#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.07:34:58.11#ibcon#*before write, iclass 12, count 0 2006.169.07:34:58.11#ibcon#enter sib2, iclass 12, count 0 2006.169.07:34:58.11#ibcon#flushed, iclass 12, count 0 2006.169.07:34:58.11#ibcon#about to write, iclass 12, count 0 2006.169.07:34:58.11#ibcon#wrote, iclass 12, count 0 2006.169.07:34:58.11#ibcon#about to read 3, iclass 12, count 0 2006.169.07:34:58.15#ibcon#read 3, iclass 12, count 0 2006.169.07:34:58.15#ibcon#about to read 4, iclass 12, count 0 2006.169.07:34:58.15#ibcon#read 4, iclass 12, count 0 2006.169.07:34:58.15#ibcon#about to read 5, iclass 12, count 0 2006.169.07:34:58.15#ibcon#read 5, iclass 12, count 0 2006.169.07:34:58.15#ibcon#about to read 6, iclass 12, count 0 2006.169.07:34:58.15#ibcon#read 6, iclass 12, count 0 2006.169.07:34:58.15#ibcon#end of sib2, iclass 12, count 0 2006.169.07:34:58.15#ibcon#*after write, iclass 12, count 0 2006.169.07:34:58.15#ibcon#*before return 0, iclass 12, count 0 2006.169.07:34:58.15#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.169.07:34:58.15#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.169.07:34:58.15#ibcon#about to clear, iclass 12 cls_cnt 0 2006.169.07:34:58.15#ibcon#cleared, iclass 12 cls_cnt 0 2006.169.07:34:58.15$vc4f8/vb=3,4 2006.169.07:34:58.15#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.169.07:34:58.15#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.169.07:34:58.15#ibcon#ireg 11 cls_cnt 2 2006.169.07:34:58.15#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.169.07:34:58.21#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.169.07:34:58.21#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.169.07:34:58.21#ibcon#enter wrdev, iclass 14, count 2 2006.169.07:34:58.21#ibcon#first serial, iclass 14, count 2 2006.169.07:34:58.21#ibcon#enter sib2, iclass 14, count 2 2006.169.07:34:58.21#ibcon#flushed, iclass 14, count 2 2006.169.07:34:58.21#ibcon#about to write, iclass 14, count 2 2006.169.07:34:58.21#ibcon#wrote, iclass 14, count 2 2006.169.07:34:58.21#ibcon#about to read 3, iclass 14, count 2 2006.169.07:34:58.23#ibcon#read 3, iclass 14, count 2 2006.169.07:34:58.23#ibcon#about to read 4, iclass 14, count 2 2006.169.07:34:58.23#ibcon#read 4, iclass 14, count 2 2006.169.07:34:58.23#ibcon#about to read 5, iclass 14, count 2 2006.169.07:34:58.23#ibcon#read 5, iclass 14, count 2 2006.169.07:34:58.23#ibcon#about to read 6, iclass 14, count 2 2006.169.07:34:58.23#ibcon#read 6, iclass 14, count 2 2006.169.07:34:58.23#ibcon#end of sib2, iclass 14, count 2 2006.169.07:34:58.23#ibcon#*mode == 0, iclass 14, count 2 2006.169.07:34:58.23#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.169.07:34:58.23#ibcon#[27=AT03-04\r\n] 2006.169.07:34:58.23#ibcon#*before write, iclass 14, count 2 2006.169.07:34:58.23#ibcon#enter sib2, iclass 14, count 2 2006.169.07:34:58.23#ibcon#flushed, iclass 14, count 2 2006.169.07:34:58.23#ibcon#about to write, iclass 14, count 2 2006.169.07:34:58.23#ibcon#wrote, iclass 14, count 2 2006.169.07:34:58.23#ibcon#about to read 3, iclass 14, count 2 2006.169.07:34:58.26#ibcon#read 3, iclass 14, count 2 2006.169.07:34:58.26#ibcon#about to read 4, iclass 14, count 2 2006.169.07:34:58.26#ibcon#read 4, iclass 14, count 2 2006.169.07:34:58.26#ibcon#about to read 5, iclass 14, count 2 2006.169.07:34:58.26#ibcon#read 5, iclass 14, count 2 2006.169.07:34:58.26#ibcon#about to read 6, iclass 14, count 2 2006.169.07:34:58.26#ibcon#read 6, iclass 14, count 2 2006.169.07:34:58.26#ibcon#end of sib2, iclass 14, count 2 2006.169.07:34:58.26#ibcon#*after write, iclass 14, count 2 2006.169.07:34:58.26#ibcon#*before return 0, iclass 14, count 2 2006.169.07:34:58.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.169.07:34:58.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.169.07:34:58.26#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.169.07:34:58.26#ibcon#ireg 7 cls_cnt 0 2006.169.07:34:58.26#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.169.07:34:58.38#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.169.07:34:58.38#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.169.07:34:58.38#ibcon#enter wrdev, iclass 14, count 0 2006.169.07:34:58.38#ibcon#first serial, iclass 14, count 0 2006.169.07:34:58.38#ibcon#enter sib2, iclass 14, count 0 2006.169.07:34:58.38#ibcon#flushed, iclass 14, count 0 2006.169.07:34:58.38#ibcon#about to write, iclass 14, count 0 2006.169.07:34:58.38#ibcon#wrote, iclass 14, count 0 2006.169.07:34:58.38#ibcon#about to read 3, iclass 14, count 0 2006.169.07:34:58.40#ibcon#read 3, iclass 14, count 0 2006.169.07:34:58.40#ibcon#about to read 4, iclass 14, count 0 2006.169.07:34:58.40#ibcon#read 4, iclass 14, count 0 2006.169.07:34:58.40#ibcon#about to read 5, iclass 14, count 0 2006.169.07:34:58.40#ibcon#read 5, iclass 14, count 0 2006.169.07:34:58.40#ibcon#about to read 6, iclass 14, count 0 2006.169.07:34:58.40#ibcon#read 6, iclass 14, count 0 2006.169.07:34:58.40#ibcon#end of sib2, iclass 14, count 0 2006.169.07:34:58.40#ibcon#*mode == 0, iclass 14, count 0 2006.169.07:34:58.40#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.169.07:34:58.40#ibcon#[27=USB\r\n] 2006.169.07:34:58.40#ibcon#*before write, iclass 14, count 0 2006.169.07:34:58.40#ibcon#enter sib2, iclass 14, count 0 2006.169.07:34:58.40#ibcon#flushed, iclass 14, count 0 2006.169.07:34:58.40#ibcon#about to write, iclass 14, count 0 2006.169.07:34:58.40#ibcon#wrote, iclass 14, count 0 2006.169.07:34:58.40#ibcon#about to read 3, iclass 14, count 0 2006.169.07:34:58.43#ibcon#read 3, iclass 14, count 0 2006.169.07:34:58.43#ibcon#about to read 4, iclass 14, count 0 2006.169.07:34:58.43#ibcon#read 4, iclass 14, count 0 2006.169.07:34:58.43#ibcon#about to read 5, iclass 14, count 0 2006.169.07:34:58.43#ibcon#read 5, iclass 14, count 0 2006.169.07:34:58.43#ibcon#about to read 6, iclass 14, count 0 2006.169.07:34:58.43#ibcon#read 6, iclass 14, count 0 2006.169.07:34:58.43#ibcon#end of sib2, iclass 14, count 0 2006.169.07:34:58.43#ibcon#*after write, iclass 14, count 0 2006.169.07:34:58.43#ibcon#*before return 0, iclass 14, count 0 2006.169.07:34:58.43#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.169.07:34:58.43#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.169.07:34:58.43#ibcon#about to clear, iclass 14 cls_cnt 0 2006.169.07:34:58.43#ibcon#cleared, iclass 14 cls_cnt 0 2006.169.07:34:58.43$vc4f8/vblo=4,712.99 2006.169.07:34:58.43#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.169.07:34:58.43#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.169.07:34:58.43#ibcon#ireg 17 cls_cnt 0 2006.169.07:34:58.43#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:34:58.43#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:34:58.43#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:34:58.43#ibcon#enter wrdev, iclass 16, count 0 2006.169.07:34:58.43#ibcon#first serial, iclass 16, count 0 2006.169.07:34:58.43#ibcon#enter sib2, iclass 16, count 0 2006.169.07:34:58.43#ibcon#flushed, iclass 16, count 0 2006.169.07:34:58.43#ibcon#about to write, iclass 16, count 0 2006.169.07:34:58.43#ibcon#wrote, iclass 16, count 0 2006.169.07:34:58.43#ibcon#about to read 3, iclass 16, count 0 2006.169.07:34:58.45#ibcon#read 3, iclass 16, count 0 2006.169.07:34:58.45#ibcon#about to read 4, iclass 16, count 0 2006.169.07:34:58.45#ibcon#read 4, iclass 16, count 0 2006.169.07:34:58.45#ibcon#about to read 5, iclass 16, count 0 2006.169.07:34:58.45#ibcon#read 5, iclass 16, count 0 2006.169.07:34:58.45#ibcon#about to read 6, iclass 16, count 0 2006.169.07:34:58.45#ibcon#read 6, iclass 16, count 0 2006.169.07:34:58.45#ibcon#end of sib2, iclass 16, count 0 2006.169.07:34:58.45#ibcon#*mode == 0, iclass 16, count 0 2006.169.07:34:58.45#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.169.07:34:58.45#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.07:34:58.45#ibcon#*before write, iclass 16, count 0 2006.169.07:34:58.45#ibcon#enter sib2, iclass 16, count 0 2006.169.07:34:58.45#ibcon#flushed, iclass 16, count 0 2006.169.07:34:58.45#ibcon#about to write, iclass 16, count 0 2006.169.07:34:58.45#ibcon#wrote, iclass 16, count 0 2006.169.07:34:58.45#ibcon#about to read 3, iclass 16, count 0 2006.169.07:34:58.49#ibcon#read 3, iclass 16, count 0 2006.169.07:34:58.49#ibcon#about to read 4, iclass 16, count 0 2006.169.07:34:58.49#ibcon#read 4, iclass 16, count 0 2006.169.07:34:58.49#ibcon#about to read 5, iclass 16, count 0 2006.169.07:34:58.49#ibcon#read 5, iclass 16, count 0 2006.169.07:34:58.49#ibcon#about to read 6, iclass 16, count 0 2006.169.07:34:58.49#ibcon#read 6, iclass 16, count 0 2006.169.07:34:58.49#ibcon#end of sib2, iclass 16, count 0 2006.169.07:34:58.49#ibcon#*after write, iclass 16, count 0 2006.169.07:34:58.49#ibcon#*before return 0, iclass 16, count 0 2006.169.07:34:58.49#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:34:58.49#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:34:58.49#ibcon#about to clear, iclass 16 cls_cnt 0 2006.169.07:34:58.49#ibcon#cleared, iclass 16 cls_cnt 0 2006.169.07:34:58.49$vc4f8/vb=4,4 2006.169.07:34:58.49#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.169.07:34:58.49#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.169.07:34:58.49#ibcon#ireg 11 cls_cnt 2 2006.169.07:34:58.49#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.169.07:34:58.55#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.169.07:34:58.55#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.169.07:34:58.55#ibcon#enter wrdev, iclass 18, count 2 2006.169.07:34:58.55#ibcon#first serial, iclass 18, count 2 2006.169.07:34:58.55#ibcon#enter sib2, iclass 18, count 2 2006.169.07:34:58.55#ibcon#flushed, iclass 18, count 2 2006.169.07:34:58.55#ibcon#about to write, iclass 18, count 2 2006.169.07:34:58.55#ibcon#wrote, iclass 18, count 2 2006.169.07:34:58.55#ibcon#about to read 3, iclass 18, count 2 2006.169.07:34:58.57#ibcon#read 3, iclass 18, count 2 2006.169.07:34:58.57#ibcon#about to read 4, iclass 18, count 2 2006.169.07:34:58.57#ibcon#read 4, iclass 18, count 2 2006.169.07:34:58.57#ibcon#about to read 5, iclass 18, count 2 2006.169.07:34:58.57#ibcon#read 5, iclass 18, count 2 2006.169.07:34:58.57#ibcon#about to read 6, iclass 18, count 2 2006.169.07:34:58.57#ibcon#read 6, iclass 18, count 2 2006.169.07:34:58.57#ibcon#end of sib2, iclass 18, count 2 2006.169.07:34:58.57#ibcon#*mode == 0, iclass 18, count 2 2006.169.07:34:58.57#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.169.07:34:58.57#ibcon#[27=AT04-04\r\n] 2006.169.07:34:58.57#ibcon#*before write, iclass 18, count 2 2006.169.07:34:58.57#ibcon#enter sib2, iclass 18, count 2 2006.169.07:34:58.57#ibcon#flushed, iclass 18, count 2 2006.169.07:34:58.57#ibcon#about to write, iclass 18, count 2 2006.169.07:34:58.57#ibcon#wrote, iclass 18, count 2 2006.169.07:34:58.57#ibcon#about to read 3, iclass 18, count 2 2006.169.07:34:58.60#ibcon#read 3, iclass 18, count 2 2006.169.07:34:58.60#ibcon#about to read 4, iclass 18, count 2 2006.169.07:34:58.60#ibcon#read 4, iclass 18, count 2 2006.169.07:34:58.60#ibcon#about to read 5, iclass 18, count 2 2006.169.07:34:58.60#ibcon#read 5, iclass 18, count 2 2006.169.07:34:58.60#ibcon#about to read 6, iclass 18, count 2 2006.169.07:34:58.60#ibcon#read 6, iclass 18, count 2 2006.169.07:34:58.60#ibcon#end of sib2, iclass 18, count 2 2006.169.07:34:58.60#ibcon#*after write, iclass 18, count 2 2006.169.07:34:58.60#ibcon#*before return 0, iclass 18, count 2 2006.169.07:34:58.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.169.07:34:58.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.169.07:34:58.60#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.169.07:34:58.60#ibcon#ireg 7 cls_cnt 0 2006.169.07:34:58.60#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.169.07:34:58.72#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.169.07:34:58.72#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.169.07:34:58.72#ibcon#enter wrdev, iclass 18, count 0 2006.169.07:34:58.72#ibcon#first serial, iclass 18, count 0 2006.169.07:34:58.72#ibcon#enter sib2, iclass 18, count 0 2006.169.07:34:58.72#ibcon#flushed, iclass 18, count 0 2006.169.07:34:58.72#ibcon#about to write, iclass 18, count 0 2006.169.07:34:58.72#ibcon#wrote, iclass 18, count 0 2006.169.07:34:58.72#ibcon#about to read 3, iclass 18, count 0 2006.169.07:34:58.74#ibcon#read 3, iclass 18, count 0 2006.169.07:34:58.74#ibcon#about to read 4, iclass 18, count 0 2006.169.07:34:58.74#ibcon#read 4, iclass 18, count 0 2006.169.07:34:58.74#ibcon#about to read 5, iclass 18, count 0 2006.169.07:34:58.74#ibcon#read 5, iclass 18, count 0 2006.169.07:34:58.74#ibcon#about to read 6, iclass 18, count 0 2006.169.07:34:58.74#ibcon#read 6, iclass 18, count 0 2006.169.07:34:58.74#ibcon#end of sib2, iclass 18, count 0 2006.169.07:34:58.74#ibcon#*mode == 0, iclass 18, count 0 2006.169.07:34:58.74#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.169.07:34:58.74#ibcon#[27=USB\r\n] 2006.169.07:34:58.74#ibcon#*before write, iclass 18, count 0 2006.169.07:34:58.74#ibcon#enter sib2, iclass 18, count 0 2006.169.07:34:58.74#ibcon#flushed, iclass 18, count 0 2006.169.07:34:58.74#ibcon#about to write, iclass 18, count 0 2006.169.07:34:58.74#ibcon#wrote, iclass 18, count 0 2006.169.07:34:58.74#ibcon#about to read 3, iclass 18, count 0 2006.169.07:34:58.77#ibcon#read 3, iclass 18, count 0 2006.169.07:34:58.77#ibcon#about to read 4, iclass 18, count 0 2006.169.07:34:58.77#ibcon#read 4, iclass 18, count 0 2006.169.07:34:58.77#ibcon#about to read 5, iclass 18, count 0 2006.169.07:34:58.77#ibcon#read 5, iclass 18, count 0 2006.169.07:34:58.77#ibcon#about to read 6, iclass 18, count 0 2006.169.07:34:58.77#ibcon#read 6, iclass 18, count 0 2006.169.07:34:58.77#ibcon#end of sib2, iclass 18, count 0 2006.169.07:34:58.77#ibcon#*after write, iclass 18, count 0 2006.169.07:34:58.77#ibcon#*before return 0, iclass 18, count 0 2006.169.07:34:58.77#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.169.07:34:58.77#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.169.07:34:58.77#ibcon#about to clear, iclass 18 cls_cnt 0 2006.169.07:34:58.77#ibcon#cleared, iclass 18 cls_cnt 0 2006.169.07:34:58.77$vc4f8/vblo=5,744.99 2006.169.07:34:58.77#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.169.07:34:58.77#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.169.07:34:58.77#ibcon#ireg 17 cls_cnt 0 2006.169.07:34:58.77#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.169.07:34:58.77#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.169.07:34:58.77#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.169.07:34:58.77#ibcon#enter wrdev, iclass 20, count 0 2006.169.07:34:58.77#ibcon#first serial, iclass 20, count 0 2006.169.07:34:58.77#ibcon#enter sib2, iclass 20, count 0 2006.169.07:34:58.77#ibcon#flushed, iclass 20, count 0 2006.169.07:34:58.77#ibcon#about to write, iclass 20, count 0 2006.169.07:34:58.77#ibcon#wrote, iclass 20, count 0 2006.169.07:34:58.77#ibcon#about to read 3, iclass 20, count 0 2006.169.07:34:58.79#ibcon#read 3, iclass 20, count 0 2006.169.07:34:58.79#ibcon#about to read 4, iclass 20, count 0 2006.169.07:34:58.79#ibcon#read 4, iclass 20, count 0 2006.169.07:34:58.79#ibcon#about to read 5, iclass 20, count 0 2006.169.07:34:58.79#ibcon#read 5, iclass 20, count 0 2006.169.07:34:58.79#ibcon#about to read 6, iclass 20, count 0 2006.169.07:34:58.79#ibcon#read 6, iclass 20, count 0 2006.169.07:34:58.79#ibcon#end of sib2, iclass 20, count 0 2006.169.07:34:58.79#ibcon#*mode == 0, iclass 20, count 0 2006.169.07:34:58.79#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.169.07:34:58.79#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.07:34:58.79#ibcon#*before write, iclass 20, count 0 2006.169.07:34:58.79#ibcon#enter sib2, iclass 20, count 0 2006.169.07:34:58.79#ibcon#flushed, iclass 20, count 0 2006.169.07:34:58.79#ibcon#about to write, iclass 20, count 0 2006.169.07:34:58.79#ibcon#wrote, iclass 20, count 0 2006.169.07:34:58.79#ibcon#about to read 3, iclass 20, count 0 2006.169.07:34:58.82#abcon#<5=/05 3.6 7.0 18.191001003.8\r\n> 2006.169.07:34:58.83#ibcon#read 3, iclass 20, count 0 2006.169.07:34:58.83#ibcon#about to read 4, iclass 20, count 0 2006.169.07:34:58.83#ibcon#read 4, iclass 20, count 0 2006.169.07:34:58.83#ibcon#about to read 5, iclass 20, count 0 2006.169.07:34:58.83#ibcon#read 5, iclass 20, count 0 2006.169.07:34:58.83#ibcon#about to read 6, iclass 20, count 0 2006.169.07:34:58.83#ibcon#read 6, iclass 20, count 0 2006.169.07:34:58.83#ibcon#end of sib2, iclass 20, count 0 2006.169.07:34:58.83#ibcon#*after write, iclass 20, count 0 2006.169.07:34:58.83#ibcon#*before return 0, iclass 20, count 0 2006.169.07:34:58.83#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.169.07:34:58.83#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.169.07:34:58.83#ibcon#about to clear, iclass 20 cls_cnt 0 2006.169.07:34:58.83#ibcon#cleared, iclass 20 cls_cnt 0 2006.169.07:34:58.83$vc4f8/vb=5,4 2006.169.07:34:58.83#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.169.07:34:58.83#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.169.07:34:58.83#ibcon#ireg 11 cls_cnt 2 2006.169.07:34:58.83#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.169.07:34:58.84#abcon#{5=INTERFACE CLEAR} 2006.169.07:34:58.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.169.07:34:58.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.169.07:34:58.89#ibcon#enter wrdev, iclass 25, count 2 2006.169.07:34:58.89#ibcon#first serial, iclass 25, count 2 2006.169.07:34:58.89#ibcon#enter sib2, iclass 25, count 2 2006.169.07:34:58.89#ibcon#flushed, iclass 25, count 2 2006.169.07:34:58.89#ibcon#about to write, iclass 25, count 2 2006.169.07:34:58.89#ibcon#wrote, iclass 25, count 2 2006.169.07:34:58.89#ibcon#about to read 3, iclass 25, count 2 2006.169.07:34:58.90#abcon#[5=S1D000X0/0*\r\n] 2006.169.07:34:58.91#ibcon#read 3, iclass 25, count 2 2006.169.07:34:58.91#ibcon#about to read 4, iclass 25, count 2 2006.169.07:34:58.91#ibcon#read 4, iclass 25, count 2 2006.169.07:34:58.91#ibcon#about to read 5, iclass 25, count 2 2006.169.07:34:58.91#ibcon#read 5, iclass 25, count 2 2006.169.07:34:58.91#ibcon#about to read 6, iclass 25, count 2 2006.169.07:34:58.91#ibcon#read 6, iclass 25, count 2 2006.169.07:34:58.91#ibcon#end of sib2, iclass 25, count 2 2006.169.07:34:58.91#ibcon#*mode == 0, iclass 25, count 2 2006.169.07:34:58.91#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.169.07:34:58.91#ibcon#[27=AT05-04\r\n] 2006.169.07:34:58.91#ibcon#*before write, iclass 25, count 2 2006.169.07:34:58.91#ibcon#enter sib2, iclass 25, count 2 2006.169.07:34:58.91#ibcon#flushed, iclass 25, count 2 2006.169.07:34:58.91#ibcon#about to write, iclass 25, count 2 2006.169.07:34:58.91#ibcon#wrote, iclass 25, count 2 2006.169.07:34:58.91#ibcon#about to read 3, iclass 25, count 2 2006.169.07:34:58.94#ibcon#read 3, iclass 25, count 2 2006.169.07:34:58.94#ibcon#about to read 4, iclass 25, count 2 2006.169.07:34:58.94#ibcon#read 4, iclass 25, count 2 2006.169.07:34:58.94#ibcon#about to read 5, iclass 25, count 2 2006.169.07:34:58.94#ibcon#read 5, iclass 25, count 2 2006.169.07:34:58.94#ibcon#about to read 6, iclass 25, count 2 2006.169.07:34:58.94#ibcon#read 6, iclass 25, count 2 2006.169.07:34:58.94#ibcon#end of sib2, iclass 25, count 2 2006.169.07:34:58.94#ibcon#*after write, iclass 25, count 2 2006.169.07:34:58.94#ibcon#*before return 0, iclass 25, count 2 2006.169.07:34:58.94#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.169.07:34:58.94#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.169.07:34:58.94#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.169.07:34:58.94#ibcon#ireg 7 cls_cnt 0 2006.169.07:34:58.94#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.169.07:34:59.06#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.169.07:34:59.06#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.169.07:34:59.06#ibcon#enter wrdev, iclass 25, count 0 2006.169.07:34:59.06#ibcon#first serial, iclass 25, count 0 2006.169.07:34:59.06#ibcon#enter sib2, iclass 25, count 0 2006.169.07:34:59.06#ibcon#flushed, iclass 25, count 0 2006.169.07:34:59.06#ibcon#about to write, iclass 25, count 0 2006.169.07:34:59.06#ibcon#wrote, iclass 25, count 0 2006.169.07:34:59.06#ibcon#about to read 3, iclass 25, count 0 2006.169.07:34:59.08#ibcon#read 3, iclass 25, count 0 2006.169.07:34:59.08#ibcon#about to read 4, iclass 25, count 0 2006.169.07:34:59.08#ibcon#read 4, iclass 25, count 0 2006.169.07:34:59.08#ibcon#about to read 5, iclass 25, count 0 2006.169.07:34:59.08#ibcon#read 5, iclass 25, count 0 2006.169.07:34:59.08#ibcon#about to read 6, iclass 25, count 0 2006.169.07:34:59.08#ibcon#read 6, iclass 25, count 0 2006.169.07:34:59.08#ibcon#end of sib2, iclass 25, count 0 2006.169.07:34:59.08#ibcon#*mode == 0, iclass 25, count 0 2006.169.07:34:59.08#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.169.07:34:59.08#ibcon#[27=USB\r\n] 2006.169.07:34:59.08#ibcon#*before write, iclass 25, count 0 2006.169.07:34:59.08#ibcon#enter sib2, iclass 25, count 0 2006.169.07:34:59.08#ibcon#flushed, iclass 25, count 0 2006.169.07:34:59.08#ibcon#about to write, iclass 25, count 0 2006.169.07:34:59.08#ibcon#wrote, iclass 25, count 0 2006.169.07:34:59.08#ibcon#about to read 3, iclass 25, count 0 2006.169.07:34:59.11#ibcon#read 3, iclass 25, count 0 2006.169.07:34:59.11#ibcon#about to read 4, iclass 25, count 0 2006.169.07:34:59.11#ibcon#read 4, iclass 25, count 0 2006.169.07:34:59.11#ibcon#about to read 5, iclass 25, count 0 2006.169.07:34:59.11#ibcon#read 5, iclass 25, count 0 2006.169.07:34:59.11#ibcon#about to read 6, iclass 25, count 0 2006.169.07:34:59.11#ibcon#read 6, iclass 25, count 0 2006.169.07:34:59.11#ibcon#end of sib2, iclass 25, count 0 2006.169.07:34:59.11#ibcon#*after write, iclass 25, count 0 2006.169.07:34:59.11#ibcon#*before return 0, iclass 25, count 0 2006.169.07:34:59.11#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.169.07:34:59.11#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.169.07:34:59.11#ibcon#about to clear, iclass 25 cls_cnt 0 2006.169.07:34:59.11#ibcon#cleared, iclass 25 cls_cnt 0 2006.169.07:34:59.11$vc4f8/vblo=6,752.99 2006.169.07:34:59.11#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.169.07:34:59.11#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.169.07:34:59.11#ibcon#ireg 17 cls_cnt 0 2006.169.07:34:59.11#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:34:59.11#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:34:59.11#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:34:59.11#ibcon#enter wrdev, iclass 28, count 0 2006.169.07:34:59.11#ibcon#first serial, iclass 28, count 0 2006.169.07:34:59.11#ibcon#enter sib2, iclass 28, count 0 2006.169.07:34:59.11#ibcon#flushed, iclass 28, count 0 2006.169.07:34:59.11#ibcon#about to write, iclass 28, count 0 2006.169.07:34:59.11#ibcon#wrote, iclass 28, count 0 2006.169.07:34:59.11#ibcon#about to read 3, iclass 28, count 0 2006.169.07:34:59.13#ibcon#read 3, iclass 28, count 0 2006.169.07:34:59.13#ibcon#about to read 4, iclass 28, count 0 2006.169.07:34:59.13#ibcon#read 4, iclass 28, count 0 2006.169.07:34:59.13#ibcon#about to read 5, iclass 28, count 0 2006.169.07:34:59.13#ibcon#read 5, iclass 28, count 0 2006.169.07:34:59.13#ibcon#about to read 6, iclass 28, count 0 2006.169.07:34:59.13#ibcon#read 6, iclass 28, count 0 2006.169.07:34:59.13#ibcon#end of sib2, iclass 28, count 0 2006.169.07:34:59.13#ibcon#*mode == 0, iclass 28, count 0 2006.169.07:34:59.13#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.169.07:34:59.13#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.07:34:59.13#ibcon#*before write, iclass 28, count 0 2006.169.07:34:59.13#ibcon#enter sib2, iclass 28, count 0 2006.169.07:34:59.13#ibcon#flushed, iclass 28, count 0 2006.169.07:34:59.13#ibcon#about to write, iclass 28, count 0 2006.169.07:34:59.13#ibcon#wrote, iclass 28, count 0 2006.169.07:34:59.13#ibcon#about to read 3, iclass 28, count 0 2006.169.07:34:59.17#ibcon#read 3, iclass 28, count 0 2006.169.07:34:59.17#ibcon#about to read 4, iclass 28, count 0 2006.169.07:34:59.17#ibcon#read 4, iclass 28, count 0 2006.169.07:34:59.17#ibcon#about to read 5, iclass 28, count 0 2006.169.07:34:59.17#ibcon#read 5, iclass 28, count 0 2006.169.07:34:59.17#ibcon#about to read 6, iclass 28, count 0 2006.169.07:34:59.17#ibcon#read 6, iclass 28, count 0 2006.169.07:34:59.17#ibcon#end of sib2, iclass 28, count 0 2006.169.07:34:59.17#ibcon#*after write, iclass 28, count 0 2006.169.07:34:59.17#ibcon#*before return 0, iclass 28, count 0 2006.169.07:34:59.17#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:34:59.17#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:34:59.17#ibcon#about to clear, iclass 28 cls_cnt 0 2006.169.07:34:59.17#ibcon#cleared, iclass 28 cls_cnt 0 2006.169.07:34:59.17$vc4f8/vb=6,4 2006.169.07:34:59.17#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.169.07:34:59.17#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.169.07:34:59.17#ibcon#ireg 11 cls_cnt 2 2006.169.07:34:59.17#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:34:59.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:34:59.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:34:59.23#ibcon#enter wrdev, iclass 30, count 2 2006.169.07:34:59.23#ibcon#first serial, iclass 30, count 2 2006.169.07:34:59.23#ibcon#enter sib2, iclass 30, count 2 2006.169.07:34:59.23#ibcon#flushed, iclass 30, count 2 2006.169.07:34:59.23#ibcon#about to write, iclass 30, count 2 2006.169.07:34:59.23#ibcon#wrote, iclass 30, count 2 2006.169.07:34:59.23#ibcon#about to read 3, iclass 30, count 2 2006.169.07:34:59.25#ibcon#read 3, iclass 30, count 2 2006.169.07:34:59.25#ibcon#about to read 4, iclass 30, count 2 2006.169.07:34:59.25#ibcon#read 4, iclass 30, count 2 2006.169.07:34:59.25#ibcon#about to read 5, iclass 30, count 2 2006.169.07:34:59.25#ibcon#read 5, iclass 30, count 2 2006.169.07:34:59.25#ibcon#about to read 6, iclass 30, count 2 2006.169.07:34:59.25#ibcon#read 6, iclass 30, count 2 2006.169.07:34:59.25#ibcon#end of sib2, iclass 30, count 2 2006.169.07:34:59.25#ibcon#*mode == 0, iclass 30, count 2 2006.169.07:34:59.25#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.169.07:34:59.25#ibcon#[27=AT06-04\r\n] 2006.169.07:34:59.25#ibcon#*before write, iclass 30, count 2 2006.169.07:34:59.25#ibcon#enter sib2, iclass 30, count 2 2006.169.07:34:59.25#ibcon#flushed, iclass 30, count 2 2006.169.07:34:59.25#ibcon#about to write, iclass 30, count 2 2006.169.07:34:59.25#ibcon#wrote, iclass 30, count 2 2006.169.07:34:59.25#ibcon#about to read 3, iclass 30, count 2 2006.169.07:34:59.28#ibcon#read 3, iclass 30, count 2 2006.169.07:34:59.28#ibcon#about to read 4, iclass 30, count 2 2006.169.07:34:59.28#ibcon#read 4, iclass 30, count 2 2006.169.07:34:59.28#ibcon#about to read 5, iclass 30, count 2 2006.169.07:34:59.28#ibcon#read 5, iclass 30, count 2 2006.169.07:34:59.28#ibcon#about to read 6, iclass 30, count 2 2006.169.07:34:59.28#ibcon#read 6, iclass 30, count 2 2006.169.07:34:59.28#ibcon#end of sib2, iclass 30, count 2 2006.169.07:34:59.28#ibcon#*after write, iclass 30, count 2 2006.169.07:34:59.28#ibcon#*before return 0, iclass 30, count 2 2006.169.07:34:59.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:34:59.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:34:59.28#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.169.07:34:59.28#ibcon#ireg 7 cls_cnt 0 2006.169.07:34:59.28#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:34:59.40#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:34:59.40#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:34:59.40#ibcon#enter wrdev, iclass 30, count 0 2006.169.07:34:59.40#ibcon#first serial, iclass 30, count 0 2006.169.07:34:59.40#ibcon#enter sib2, iclass 30, count 0 2006.169.07:34:59.40#ibcon#flushed, iclass 30, count 0 2006.169.07:34:59.40#ibcon#about to write, iclass 30, count 0 2006.169.07:34:59.40#ibcon#wrote, iclass 30, count 0 2006.169.07:34:59.40#ibcon#about to read 3, iclass 30, count 0 2006.169.07:34:59.42#ibcon#read 3, iclass 30, count 0 2006.169.07:34:59.42#ibcon#about to read 4, iclass 30, count 0 2006.169.07:34:59.42#ibcon#read 4, iclass 30, count 0 2006.169.07:34:59.42#ibcon#about to read 5, iclass 30, count 0 2006.169.07:34:59.42#ibcon#read 5, iclass 30, count 0 2006.169.07:34:59.42#ibcon#about to read 6, iclass 30, count 0 2006.169.07:34:59.42#ibcon#read 6, iclass 30, count 0 2006.169.07:34:59.42#ibcon#end of sib2, iclass 30, count 0 2006.169.07:34:59.42#ibcon#*mode == 0, iclass 30, count 0 2006.169.07:34:59.42#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.169.07:34:59.42#ibcon#[27=USB\r\n] 2006.169.07:34:59.42#ibcon#*before write, iclass 30, count 0 2006.169.07:34:59.42#ibcon#enter sib2, iclass 30, count 0 2006.169.07:34:59.42#ibcon#flushed, iclass 30, count 0 2006.169.07:34:59.42#ibcon#about to write, iclass 30, count 0 2006.169.07:34:59.42#ibcon#wrote, iclass 30, count 0 2006.169.07:34:59.42#ibcon#about to read 3, iclass 30, count 0 2006.169.07:34:59.45#ibcon#read 3, iclass 30, count 0 2006.169.07:34:59.45#ibcon#about to read 4, iclass 30, count 0 2006.169.07:34:59.45#ibcon#read 4, iclass 30, count 0 2006.169.07:34:59.45#ibcon#about to read 5, iclass 30, count 0 2006.169.07:34:59.45#ibcon#read 5, iclass 30, count 0 2006.169.07:34:59.45#ibcon#about to read 6, iclass 30, count 0 2006.169.07:34:59.45#ibcon#read 6, iclass 30, count 0 2006.169.07:34:59.45#ibcon#end of sib2, iclass 30, count 0 2006.169.07:34:59.45#ibcon#*after write, iclass 30, count 0 2006.169.07:34:59.45#ibcon#*before return 0, iclass 30, count 0 2006.169.07:34:59.45#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:34:59.45#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:34:59.45#ibcon#about to clear, iclass 30 cls_cnt 0 2006.169.07:34:59.45#ibcon#cleared, iclass 30 cls_cnt 0 2006.169.07:34:59.45$vc4f8/vabw=wide 2006.169.07:34:59.45#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.169.07:34:59.45#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.169.07:34:59.45#ibcon#ireg 8 cls_cnt 0 2006.169.07:34:59.45#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:34:59.45#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:34:59.45#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:34:59.45#ibcon#enter wrdev, iclass 32, count 0 2006.169.07:34:59.45#ibcon#first serial, iclass 32, count 0 2006.169.07:34:59.45#ibcon#enter sib2, iclass 32, count 0 2006.169.07:34:59.45#ibcon#flushed, iclass 32, count 0 2006.169.07:34:59.45#ibcon#about to write, iclass 32, count 0 2006.169.07:34:59.45#ibcon#wrote, iclass 32, count 0 2006.169.07:34:59.45#ibcon#about to read 3, iclass 32, count 0 2006.169.07:34:59.47#ibcon#read 3, iclass 32, count 0 2006.169.07:34:59.47#ibcon#about to read 4, iclass 32, count 0 2006.169.07:34:59.47#ibcon#read 4, iclass 32, count 0 2006.169.07:34:59.47#ibcon#about to read 5, iclass 32, count 0 2006.169.07:34:59.47#ibcon#read 5, iclass 32, count 0 2006.169.07:34:59.47#ibcon#about to read 6, iclass 32, count 0 2006.169.07:34:59.47#ibcon#read 6, iclass 32, count 0 2006.169.07:34:59.47#ibcon#end of sib2, iclass 32, count 0 2006.169.07:34:59.47#ibcon#*mode == 0, iclass 32, count 0 2006.169.07:34:59.47#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.169.07:34:59.47#ibcon#[25=BW32\r\n] 2006.169.07:34:59.47#ibcon#*before write, iclass 32, count 0 2006.169.07:34:59.47#ibcon#enter sib2, iclass 32, count 0 2006.169.07:34:59.47#ibcon#flushed, iclass 32, count 0 2006.169.07:34:59.47#ibcon#about to write, iclass 32, count 0 2006.169.07:34:59.47#ibcon#wrote, iclass 32, count 0 2006.169.07:34:59.47#ibcon#about to read 3, iclass 32, count 0 2006.169.07:34:59.50#ibcon#read 3, iclass 32, count 0 2006.169.07:34:59.50#ibcon#about to read 4, iclass 32, count 0 2006.169.07:34:59.50#ibcon#read 4, iclass 32, count 0 2006.169.07:34:59.50#ibcon#about to read 5, iclass 32, count 0 2006.169.07:34:59.50#ibcon#read 5, iclass 32, count 0 2006.169.07:34:59.50#ibcon#about to read 6, iclass 32, count 0 2006.169.07:34:59.50#ibcon#read 6, iclass 32, count 0 2006.169.07:34:59.50#ibcon#end of sib2, iclass 32, count 0 2006.169.07:34:59.50#ibcon#*after write, iclass 32, count 0 2006.169.07:34:59.50#ibcon#*before return 0, iclass 32, count 0 2006.169.07:34:59.50#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:34:59.50#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:34:59.50#ibcon#about to clear, iclass 32 cls_cnt 0 2006.169.07:34:59.50#ibcon#cleared, iclass 32 cls_cnt 0 2006.169.07:34:59.50$vc4f8/vbbw=wide 2006.169.07:34:59.50#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.169.07:34:59.50#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.169.07:34:59.50#ibcon#ireg 8 cls_cnt 0 2006.169.07:34:59.50#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:34:59.57#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:34:59.57#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:34:59.57#ibcon#enter wrdev, iclass 34, count 0 2006.169.07:34:59.57#ibcon#first serial, iclass 34, count 0 2006.169.07:34:59.57#ibcon#enter sib2, iclass 34, count 0 2006.169.07:34:59.57#ibcon#flushed, iclass 34, count 0 2006.169.07:34:59.57#ibcon#about to write, iclass 34, count 0 2006.169.07:34:59.57#ibcon#wrote, iclass 34, count 0 2006.169.07:34:59.57#ibcon#about to read 3, iclass 34, count 0 2006.169.07:34:59.59#ibcon#read 3, iclass 34, count 0 2006.169.07:34:59.59#ibcon#about to read 4, iclass 34, count 0 2006.169.07:34:59.59#ibcon#read 4, iclass 34, count 0 2006.169.07:34:59.59#ibcon#about to read 5, iclass 34, count 0 2006.169.07:34:59.59#ibcon#read 5, iclass 34, count 0 2006.169.07:34:59.59#ibcon#about to read 6, iclass 34, count 0 2006.169.07:34:59.59#ibcon#read 6, iclass 34, count 0 2006.169.07:34:59.59#ibcon#end of sib2, iclass 34, count 0 2006.169.07:34:59.59#ibcon#*mode == 0, iclass 34, count 0 2006.169.07:34:59.59#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.169.07:34:59.59#ibcon#[27=BW32\r\n] 2006.169.07:34:59.59#ibcon#*before write, iclass 34, count 0 2006.169.07:34:59.59#ibcon#enter sib2, iclass 34, count 0 2006.169.07:34:59.59#ibcon#flushed, iclass 34, count 0 2006.169.07:34:59.59#ibcon#about to write, iclass 34, count 0 2006.169.07:34:59.59#ibcon#wrote, iclass 34, count 0 2006.169.07:34:59.59#ibcon#about to read 3, iclass 34, count 0 2006.169.07:34:59.62#ibcon#read 3, iclass 34, count 0 2006.169.07:34:59.62#ibcon#about to read 4, iclass 34, count 0 2006.169.07:34:59.62#ibcon#read 4, iclass 34, count 0 2006.169.07:34:59.62#ibcon#about to read 5, iclass 34, count 0 2006.169.07:34:59.62#ibcon#read 5, iclass 34, count 0 2006.169.07:34:59.62#ibcon#about to read 6, iclass 34, count 0 2006.169.07:34:59.62#ibcon#read 6, iclass 34, count 0 2006.169.07:34:59.62#ibcon#end of sib2, iclass 34, count 0 2006.169.07:34:59.62#ibcon#*after write, iclass 34, count 0 2006.169.07:34:59.62#ibcon#*before return 0, iclass 34, count 0 2006.169.07:34:59.62#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:34:59.62#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:34:59.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.169.07:34:59.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.169.07:34:59.62$4f8m12a/ifd4f 2006.169.07:34:59.62$ifd4f/lo= 2006.169.07:34:59.62$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.07:34:59.62$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.07:34:59.62$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.07:34:59.62$ifd4f/patch= 2006.169.07:34:59.62$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.07:34:59.62$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.07:34:59.62$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.07:34:59.62$4f8m12a/"form=m,16.000,1:2 2006.169.07:34:59.62$4f8m12a/"tpicd 2006.169.07:34:59.62$4f8m12a/echo=off 2006.169.07:34:59.62$4f8m12a/xlog=off 2006.169.07:34:59.62:!2006.169.07:35:10 2006.169.07:35:10.00:preob 2006.169.07:35:11.14/onsource/TRACKING 2006.169.07:35:11.14:!2006.169.07:35:20 2006.169.07:35:20.00:data_valid=on 2006.169.07:35:20.00:midob 2006.169.07:35:20.14/onsource/TRACKING 2006.169.07:35:20.14/wx/18.18,1003.7,100 2006.169.07:35:20.22/cable/+6.5266E-03 2006.169.07:35:21.31/va/01,08,usb,yes,52,54 2006.169.07:35:21.31/va/02,07,usb,yes,53,55 2006.169.07:35:21.31/va/03,06,usb,yes,56,56 2006.169.07:35:21.31/va/04,07,usb,yes,54,58 2006.169.07:35:21.31/va/05,07,usb,yes,59,62 2006.169.07:35:21.31/va/06,06,usb,yes,58,58 2006.169.07:35:21.31/va/07,06,usb,yes,59,59 2006.169.07:35:21.31/va/08,07,usb,yes,56,55 2006.169.07:35:21.54/valo/01,532.99,yes,locked 2006.169.07:35:21.54/valo/02,572.99,yes,locked 2006.169.07:35:21.54/valo/03,672.99,yes,locked 2006.169.07:35:21.54/valo/04,832.99,yes,locked 2006.169.07:35:21.54/valo/05,652.99,yes,locked 2006.169.07:35:21.54/valo/06,772.99,yes,locked 2006.169.07:35:21.54/valo/07,832.99,yes,locked 2006.169.07:35:21.54/valo/08,852.99,yes,locked 2006.169.07:35:22.63/vb/01,04,usb,yes,31,29 2006.169.07:35:22.63/vb/02,04,usb,yes,33,34 2006.169.07:35:22.63/vb/03,04,usb,yes,29,33 2006.169.07:35:22.63/vb/04,04,usb,yes,30,30 2006.169.07:35:22.63/vb/05,04,usb,yes,28,33 2006.169.07:35:22.63/vb/06,04,usb,yes,30,32 2006.169.07:35:22.63/vb/07,04,usb,yes,32,31 2006.169.07:35:22.63/vb/08,04,usb,yes,29,33 2006.169.07:35:22.86/vblo/01,632.99,yes,locked 2006.169.07:35:22.86/vblo/02,640.99,yes,locked 2006.169.07:35:22.86/vblo/03,656.99,yes,locked 2006.169.07:35:22.86/vblo/04,712.99,yes,locked 2006.169.07:35:22.86/vblo/05,744.99,yes,locked 2006.169.07:35:22.86/vblo/06,752.99,yes,locked 2006.169.07:35:22.86/vblo/07,734.99,yes,locked 2006.169.07:35:22.86/vblo/08,744.99,yes,locked 2006.169.07:35:23.01/vabw/8 2006.169.07:35:23.16/vbbw/8 2006.169.07:35:23.25/xfe/off,on,14.7 2006.169.07:35:23.64/ifatt/23,28,28,28 2006.169.07:35:24.08/fmout-gps/S +4.17E-07 2006.169.07:35:24.16:!2006.169.07:36:20 2006.169.07:36:20.00:data_valid=off 2006.169.07:36:20.00:postob 2006.169.07:36:20.21/cable/+6.5274E-03 2006.169.07:36:20.21/wx/18.17,1003.7,100 2006.169.07:36:21.08/fmout-gps/S +4.18E-07 2006.169.07:36:21.08:scan_name=169-0737,k06169,60 2006.169.07:36:21.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.169.07:36:21.14#flagr#flagr/antenna,new-source 2006.169.07:36:22.14:checkk5 2006.169.07:36:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.169.07:36:22.90/chk_autoobs//k5ts2/ autoobs is running! 2006.169.07:36:26.93/chk_autoobs//k5ts3?ERROR: timeout happened! 2006.169.07:36:27.30/chk_autoobs//k5ts4/ autoobs is running! 2006.169.07:36:27.67/chk_obsdata//k5ts1/T1690735??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:36:28.04/chk_obsdata//k5ts2/T1690735??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:36:35.11/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.07:36:35.48/chk_obsdata//k5ts4/T1690735??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:36:36.17/k5log//k5ts1_log_newline 2006.169.07:36:36.85/k5log//k5ts2_log_newline 2006.169.07:36:43.95/k5log//k5ts3?ERROR: timeout happened! 2006.169.07:36:44.63/k5log//k5ts4_log_newline 2006.169.07:36:44.80/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.07:36:44.80:4f8m12a=1 2006.169.07:36:44.80$4f8m12a/echo=on 2006.169.07:36:44.80$4f8m12a/pcalon 2006.169.07:36:44.80$pcalon/"no phase cal control is implemented here 2006.169.07:36:44.80$4f8m12a/"tpicd=stop 2006.169.07:36:44.80$4f8m12a/vc4f8 2006.169.07:36:44.80$vc4f8/valo=1,532.99 2006.169.07:36:44.80#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.169.07:36:44.80#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.169.07:36:44.80#ibcon#ireg 17 cls_cnt 0 2006.169.07:36:44.80#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:36:44.80#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:36:44.80#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:36:44.80#ibcon#enter wrdev, iclass 3, count 0 2006.169.07:36:44.80#ibcon#first serial, iclass 3, count 0 2006.169.07:36:44.80#ibcon#enter sib2, iclass 3, count 0 2006.169.07:36:44.80#ibcon#flushed, iclass 3, count 0 2006.169.07:36:44.80#ibcon#about to write, iclass 3, count 0 2006.169.07:36:44.80#ibcon#wrote, iclass 3, count 0 2006.169.07:36:44.80#ibcon#about to read 3, iclass 3, count 0 2006.169.07:36:44.82#ibcon#read 3, iclass 3, count 0 2006.169.07:36:44.82#ibcon#about to read 4, iclass 3, count 0 2006.169.07:36:44.82#ibcon#read 4, iclass 3, count 0 2006.169.07:36:44.82#ibcon#about to read 5, iclass 3, count 0 2006.169.07:36:44.82#ibcon#read 5, iclass 3, count 0 2006.169.07:36:44.82#ibcon#about to read 6, iclass 3, count 0 2006.169.07:36:44.82#ibcon#read 6, iclass 3, count 0 2006.169.07:36:44.82#ibcon#end of sib2, iclass 3, count 0 2006.169.07:36:44.82#ibcon#*mode == 0, iclass 3, count 0 2006.169.07:36:44.82#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.169.07:36:44.82#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.07:36:44.82#ibcon#*before write, iclass 3, count 0 2006.169.07:36:44.82#ibcon#enter sib2, iclass 3, count 0 2006.169.07:36:44.82#ibcon#flushed, iclass 3, count 0 2006.169.07:36:44.82#ibcon#about to write, iclass 3, count 0 2006.169.07:36:44.82#ibcon#wrote, iclass 3, count 0 2006.169.07:36:44.82#ibcon#about to read 3, iclass 3, count 0 2006.169.07:36:44.87#ibcon#read 3, iclass 3, count 0 2006.169.07:36:44.87#ibcon#about to read 4, iclass 3, count 0 2006.169.07:36:44.87#ibcon#read 4, iclass 3, count 0 2006.169.07:36:44.87#ibcon#about to read 5, iclass 3, count 0 2006.169.07:36:44.87#ibcon#read 5, iclass 3, count 0 2006.169.07:36:44.87#ibcon#about to read 6, iclass 3, count 0 2006.169.07:36:44.87#ibcon#read 6, iclass 3, count 0 2006.169.07:36:44.87#ibcon#end of sib2, iclass 3, count 0 2006.169.07:36:44.87#ibcon#*after write, iclass 3, count 0 2006.169.07:36:44.87#ibcon#*before return 0, iclass 3, count 0 2006.169.07:36:44.87#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:36:44.87#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:36:44.87#ibcon#about to clear, iclass 3 cls_cnt 0 2006.169.07:36:44.87#ibcon#cleared, iclass 3 cls_cnt 0 2006.169.07:36:44.87$vc4f8/va=1,8 2006.169.07:36:44.87#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.169.07:36:44.87#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.169.07:36:44.87#ibcon#ireg 11 cls_cnt 2 2006.169.07:36:44.87#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:36:44.87#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:36:44.87#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:36:44.87#ibcon#enter wrdev, iclass 5, count 2 2006.169.07:36:44.87#ibcon#first serial, iclass 5, count 2 2006.169.07:36:44.87#ibcon#enter sib2, iclass 5, count 2 2006.169.07:36:44.87#ibcon#flushed, iclass 5, count 2 2006.169.07:36:44.87#ibcon#about to write, iclass 5, count 2 2006.169.07:36:44.87#ibcon#wrote, iclass 5, count 2 2006.169.07:36:44.87#ibcon#about to read 3, iclass 5, count 2 2006.169.07:36:44.89#ibcon#read 3, iclass 5, count 2 2006.169.07:36:44.89#ibcon#about to read 4, iclass 5, count 2 2006.169.07:36:44.89#ibcon#read 4, iclass 5, count 2 2006.169.07:36:44.89#ibcon#about to read 5, iclass 5, count 2 2006.169.07:36:44.89#ibcon#read 5, iclass 5, count 2 2006.169.07:36:44.89#ibcon#about to read 6, iclass 5, count 2 2006.169.07:36:44.89#ibcon#read 6, iclass 5, count 2 2006.169.07:36:44.89#ibcon#end of sib2, iclass 5, count 2 2006.169.07:36:44.89#ibcon#*mode == 0, iclass 5, count 2 2006.169.07:36:44.89#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.169.07:36:44.89#ibcon#[25=AT01-08\r\n] 2006.169.07:36:44.89#ibcon#*before write, iclass 5, count 2 2006.169.07:36:44.89#ibcon#enter sib2, iclass 5, count 2 2006.169.07:36:44.89#ibcon#flushed, iclass 5, count 2 2006.169.07:36:44.89#ibcon#about to write, iclass 5, count 2 2006.169.07:36:44.89#ibcon#wrote, iclass 5, count 2 2006.169.07:36:44.89#ibcon#about to read 3, iclass 5, count 2 2006.169.07:36:44.92#ibcon#read 3, iclass 5, count 2 2006.169.07:36:44.92#ibcon#about to read 4, iclass 5, count 2 2006.169.07:36:44.92#ibcon#read 4, iclass 5, count 2 2006.169.07:36:44.92#ibcon#about to read 5, iclass 5, count 2 2006.169.07:36:44.92#ibcon#read 5, iclass 5, count 2 2006.169.07:36:44.92#ibcon#about to read 6, iclass 5, count 2 2006.169.07:36:44.92#ibcon#read 6, iclass 5, count 2 2006.169.07:36:44.92#ibcon#end of sib2, iclass 5, count 2 2006.169.07:36:44.92#ibcon#*after write, iclass 5, count 2 2006.169.07:36:44.92#ibcon#*before return 0, iclass 5, count 2 2006.169.07:36:44.92#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:36:44.92#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:36:44.92#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.169.07:36:44.92#ibcon#ireg 7 cls_cnt 0 2006.169.07:36:44.92#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:36:45.04#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:36:45.04#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:36:45.04#ibcon#enter wrdev, iclass 5, count 0 2006.169.07:36:45.04#ibcon#first serial, iclass 5, count 0 2006.169.07:36:45.04#ibcon#enter sib2, iclass 5, count 0 2006.169.07:36:45.04#ibcon#flushed, iclass 5, count 0 2006.169.07:36:45.04#ibcon#about to write, iclass 5, count 0 2006.169.07:36:45.04#ibcon#wrote, iclass 5, count 0 2006.169.07:36:45.04#ibcon#about to read 3, iclass 5, count 0 2006.169.07:36:45.07#ibcon#read 3, iclass 5, count 0 2006.169.07:36:45.07#ibcon#about to read 4, iclass 5, count 0 2006.169.07:36:45.07#ibcon#read 4, iclass 5, count 0 2006.169.07:36:45.07#ibcon#about to read 5, iclass 5, count 0 2006.169.07:36:45.07#ibcon#read 5, iclass 5, count 0 2006.169.07:36:45.07#ibcon#about to read 6, iclass 5, count 0 2006.169.07:36:45.07#ibcon#read 6, iclass 5, count 0 2006.169.07:36:45.07#ibcon#end of sib2, iclass 5, count 0 2006.169.07:36:45.07#ibcon#*mode == 0, iclass 5, count 0 2006.169.07:36:45.07#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.169.07:36:45.07#ibcon#[25=USB\r\n] 2006.169.07:36:45.07#ibcon#*before write, iclass 5, count 0 2006.169.07:36:45.07#ibcon#enter sib2, iclass 5, count 0 2006.169.07:36:45.07#ibcon#flushed, iclass 5, count 0 2006.169.07:36:45.07#ibcon#about to write, iclass 5, count 0 2006.169.07:36:45.07#ibcon#wrote, iclass 5, count 0 2006.169.07:36:45.07#ibcon#about to read 3, iclass 5, count 0 2006.169.07:36:45.11#ibcon#read 3, iclass 5, count 0 2006.169.07:36:45.11#ibcon#about to read 4, iclass 5, count 0 2006.169.07:36:45.11#ibcon#read 4, iclass 5, count 0 2006.169.07:36:45.11#ibcon#about to read 5, iclass 5, count 0 2006.169.07:36:45.11#ibcon#read 5, iclass 5, count 0 2006.169.07:36:45.11#ibcon#about to read 6, iclass 5, count 0 2006.169.07:36:45.11#ibcon#read 6, iclass 5, count 0 2006.169.07:36:45.11#ibcon#end of sib2, iclass 5, count 0 2006.169.07:36:45.11#ibcon#*after write, iclass 5, count 0 2006.169.07:36:45.11#ibcon#*before return 0, iclass 5, count 0 2006.169.07:36:45.11#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:36:45.11#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:36:45.11#ibcon#about to clear, iclass 5 cls_cnt 0 2006.169.07:36:45.11#ibcon#cleared, iclass 5 cls_cnt 0 2006.169.07:36:45.11$vc4f8/valo=2,572.99 2006.169.07:36:45.11#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.169.07:36:45.11#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.169.07:36:45.11#ibcon#ireg 17 cls_cnt 0 2006.169.07:36:45.11#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:36:45.11#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:36:45.11#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:36:45.11#ibcon#enter wrdev, iclass 7, count 0 2006.169.07:36:45.11#ibcon#first serial, iclass 7, count 0 2006.169.07:36:45.11#ibcon#enter sib2, iclass 7, count 0 2006.169.07:36:45.11#ibcon#flushed, iclass 7, count 0 2006.169.07:36:45.11#ibcon#about to write, iclass 7, count 0 2006.169.07:36:45.11#ibcon#wrote, iclass 7, count 0 2006.169.07:36:45.11#ibcon#about to read 3, iclass 7, count 0 2006.169.07:36:45.13#ibcon#read 3, iclass 7, count 0 2006.169.07:36:45.13#ibcon#about to read 4, iclass 7, count 0 2006.169.07:36:45.13#ibcon#read 4, iclass 7, count 0 2006.169.07:36:45.13#ibcon#about to read 5, iclass 7, count 0 2006.169.07:36:45.13#ibcon#read 5, iclass 7, count 0 2006.169.07:36:45.13#ibcon#about to read 6, iclass 7, count 0 2006.169.07:36:45.13#ibcon#read 6, iclass 7, count 0 2006.169.07:36:45.13#ibcon#end of sib2, iclass 7, count 0 2006.169.07:36:45.13#ibcon#*mode == 0, iclass 7, count 0 2006.169.07:36:45.13#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.169.07:36:45.13#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.07:36:45.13#ibcon#*before write, iclass 7, count 0 2006.169.07:36:45.13#ibcon#enter sib2, iclass 7, count 0 2006.169.07:36:45.13#ibcon#flushed, iclass 7, count 0 2006.169.07:36:45.13#ibcon#about to write, iclass 7, count 0 2006.169.07:36:45.13#ibcon#wrote, iclass 7, count 0 2006.169.07:36:45.13#ibcon#about to read 3, iclass 7, count 0 2006.169.07:36:45.17#ibcon#read 3, iclass 7, count 0 2006.169.07:36:45.17#ibcon#about to read 4, iclass 7, count 0 2006.169.07:36:45.17#ibcon#read 4, iclass 7, count 0 2006.169.07:36:45.17#ibcon#about to read 5, iclass 7, count 0 2006.169.07:36:45.17#ibcon#read 5, iclass 7, count 0 2006.169.07:36:45.17#ibcon#about to read 6, iclass 7, count 0 2006.169.07:36:45.17#ibcon#read 6, iclass 7, count 0 2006.169.07:36:45.17#ibcon#end of sib2, iclass 7, count 0 2006.169.07:36:45.17#ibcon#*after write, iclass 7, count 0 2006.169.07:36:45.17#ibcon#*before return 0, iclass 7, count 0 2006.169.07:36:45.17#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:36:45.17#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:36:45.17#ibcon#about to clear, iclass 7 cls_cnt 0 2006.169.07:36:45.17#ibcon#cleared, iclass 7 cls_cnt 0 2006.169.07:36:45.17$vc4f8/va=2,7 2006.169.07:36:45.17#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.169.07:36:45.17#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.169.07:36:45.17#ibcon#ireg 11 cls_cnt 2 2006.169.07:36:45.17#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:36:45.23#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:36:45.23#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:36:45.23#ibcon#enter wrdev, iclass 11, count 2 2006.169.07:36:45.23#ibcon#first serial, iclass 11, count 2 2006.169.07:36:45.23#ibcon#enter sib2, iclass 11, count 2 2006.169.07:36:45.23#ibcon#flushed, iclass 11, count 2 2006.169.07:36:45.23#ibcon#about to write, iclass 11, count 2 2006.169.07:36:45.23#ibcon#wrote, iclass 11, count 2 2006.169.07:36:45.23#ibcon#about to read 3, iclass 11, count 2 2006.169.07:36:45.25#ibcon#read 3, iclass 11, count 2 2006.169.07:36:45.25#ibcon#about to read 4, iclass 11, count 2 2006.169.07:36:45.25#ibcon#read 4, iclass 11, count 2 2006.169.07:36:45.25#ibcon#about to read 5, iclass 11, count 2 2006.169.07:36:45.25#ibcon#read 5, iclass 11, count 2 2006.169.07:36:45.25#ibcon#about to read 6, iclass 11, count 2 2006.169.07:36:45.25#ibcon#read 6, iclass 11, count 2 2006.169.07:36:45.25#ibcon#end of sib2, iclass 11, count 2 2006.169.07:36:45.25#ibcon#*mode == 0, iclass 11, count 2 2006.169.07:36:45.25#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.169.07:36:45.25#ibcon#[25=AT02-07\r\n] 2006.169.07:36:45.25#ibcon#*before write, iclass 11, count 2 2006.169.07:36:45.25#ibcon#enter sib2, iclass 11, count 2 2006.169.07:36:45.25#ibcon#flushed, iclass 11, count 2 2006.169.07:36:45.25#ibcon#about to write, iclass 11, count 2 2006.169.07:36:45.25#ibcon#wrote, iclass 11, count 2 2006.169.07:36:45.25#ibcon#about to read 3, iclass 11, count 2 2006.169.07:36:45.28#ibcon#read 3, iclass 11, count 2 2006.169.07:36:45.28#ibcon#about to read 4, iclass 11, count 2 2006.169.07:36:45.28#ibcon#read 4, iclass 11, count 2 2006.169.07:36:45.28#ibcon#about to read 5, iclass 11, count 2 2006.169.07:36:45.28#ibcon#read 5, iclass 11, count 2 2006.169.07:36:45.28#ibcon#about to read 6, iclass 11, count 2 2006.169.07:36:45.28#ibcon#read 6, iclass 11, count 2 2006.169.07:36:45.28#ibcon#end of sib2, iclass 11, count 2 2006.169.07:36:45.28#ibcon#*after write, iclass 11, count 2 2006.169.07:36:45.28#ibcon#*before return 0, iclass 11, count 2 2006.169.07:36:45.28#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:36:45.28#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:36:45.28#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.169.07:36:45.28#ibcon#ireg 7 cls_cnt 0 2006.169.07:36:45.28#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:36:45.40#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:36:45.40#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:36:45.40#ibcon#enter wrdev, iclass 11, count 0 2006.169.07:36:45.40#ibcon#first serial, iclass 11, count 0 2006.169.07:36:45.40#ibcon#enter sib2, iclass 11, count 0 2006.169.07:36:45.40#ibcon#flushed, iclass 11, count 0 2006.169.07:36:45.40#ibcon#about to write, iclass 11, count 0 2006.169.07:36:45.40#ibcon#wrote, iclass 11, count 0 2006.169.07:36:45.40#ibcon#about to read 3, iclass 11, count 0 2006.169.07:36:45.42#ibcon#read 3, iclass 11, count 0 2006.169.07:36:45.42#ibcon#about to read 4, iclass 11, count 0 2006.169.07:36:45.42#ibcon#read 4, iclass 11, count 0 2006.169.07:36:45.42#ibcon#about to read 5, iclass 11, count 0 2006.169.07:36:45.42#ibcon#read 5, iclass 11, count 0 2006.169.07:36:45.42#ibcon#about to read 6, iclass 11, count 0 2006.169.07:36:45.42#ibcon#read 6, iclass 11, count 0 2006.169.07:36:45.42#ibcon#end of sib2, iclass 11, count 0 2006.169.07:36:45.42#ibcon#*mode == 0, iclass 11, count 0 2006.169.07:36:45.42#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.169.07:36:45.42#ibcon#[25=USB\r\n] 2006.169.07:36:45.42#ibcon#*before write, iclass 11, count 0 2006.169.07:36:45.42#ibcon#enter sib2, iclass 11, count 0 2006.169.07:36:45.42#ibcon#flushed, iclass 11, count 0 2006.169.07:36:45.42#ibcon#about to write, iclass 11, count 0 2006.169.07:36:45.42#ibcon#wrote, iclass 11, count 0 2006.169.07:36:45.42#ibcon#about to read 3, iclass 11, count 0 2006.169.07:36:45.45#ibcon#read 3, iclass 11, count 0 2006.169.07:36:45.45#ibcon#about to read 4, iclass 11, count 0 2006.169.07:36:45.45#ibcon#read 4, iclass 11, count 0 2006.169.07:36:45.45#ibcon#about to read 5, iclass 11, count 0 2006.169.07:36:45.45#ibcon#read 5, iclass 11, count 0 2006.169.07:36:45.45#ibcon#about to read 6, iclass 11, count 0 2006.169.07:36:45.45#ibcon#read 6, iclass 11, count 0 2006.169.07:36:45.45#ibcon#end of sib2, iclass 11, count 0 2006.169.07:36:45.45#ibcon#*after write, iclass 11, count 0 2006.169.07:36:45.45#ibcon#*before return 0, iclass 11, count 0 2006.169.07:36:45.45#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:36:45.45#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:36:45.45#ibcon#about to clear, iclass 11 cls_cnt 0 2006.169.07:36:45.45#ibcon#cleared, iclass 11 cls_cnt 0 2006.169.07:36:45.45$vc4f8/valo=3,672.99 2006.169.07:36:45.45#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.169.07:36:45.45#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.169.07:36:45.45#ibcon#ireg 17 cls_cnt 0 2006.169.07:36:45.45#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:36:45.45#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:36:45.45#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:36:45.45#ibcon#enter wrdev, iclass 13, count 0 2006.169.07:36:45.45#ibcon#first serial, iclass 13, count 0 2006.169.07:36:45.45#ibcon#enter sib2, iclass 13, count 0 2006.169.07:36:45.45#ibcon#flushed, iclass 13, count 0 2006.169.07:36:45.45#ibcon#about to write, iclass 13, count 0 2006.169.07:36:45.45#ibcon#wrote, iclass 13, count 0 2006.169.07:36:45.45#ibcon#about to read 3, iclass 13, count 0 2006.169.07:36:45.47#ibcon#read 3, iclass 13, count 0 2006.169.07:36:45.47#ibcon#about to read 4, iclass 13, count 0 2006.169.07:36:45.47#ibcon#read 4, iclass 13, count 0 2006.169.07:36:45.47#ibcon#about to read 5, iclass 13, count 0 2006.169.07:36:45.47#ibcon#read 5, iclass 13, count 0 2006.169.07:36:45.47#ibcon#about to read 6, iclass 13, count 0 2006.169.07:36:45.47#ibcon#read 6, iclass 13, count 0 2006.169.07:36:45.47#ibcon#end of sib2, iclass 13, count 0 2006.169.07:36:45.47#ibcon#*mode == 0, iclass 13, count 0 2006.169.07:36:45.47#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.07:36:45.47#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.07:36:45.47#ibcon#*before write, iclass 13, count 0 2006.169.07:36:45.47#ibcon#enter sib2, iclass 13, count 0 2006.169.07:36:45.47#ibcon#flushed, iclass 13, count 0 2006.169.07:36:45.47#ibcon#about to write, iclass 13, count 0 2006.169.07:36:45.47#ibcon#wrote, iclass 13, count 0 2006.169.07:36:45.47#ibcon#about to read 3, iclass 13, count 0 2006.169.07:36:45.51#ibcon#read 3, iclass 13, count 0 2006.169.07:36:45.51#ibcon#about to read 4, iclass 13, count 0 2006.169.07:36:45.51#ibcon#read 4, iclass 13, count 0 2006.169.07:36:45.51#ibcon#about to read 5, iclass 13, count 0 2006.169.07:36:45.51#ibcon#read 5, iclass 13, count 0 2006.169.07:36:45.51#ibcon#about to read 6, iclass 13, count 0 2006.169.07:36:45.51#ibcon#read 6, iclass 13, count 0 2006.169.07:36:45.51#ibcon#end of sib2, iclass 13, count 0 2006.169.07:36:45.51#ibcon#*after write, iclass 13, count 0 2006.169.07:36:45.51#ibcon#*before return 0, iclass 13, count 0 2006.169.07:36:45.51#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:36:45.51#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:36:45.51#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.07:36:45.51#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.07:36:45.51$vc4f8/va=3,6 2006.169.07:36:45.51#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.169.07:36:45.51#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.169.07:36:45.51#ibcon#ireg 11 cls_cnt 2 2006.169.07:36:45.51#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:36:45.57#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:36:45.57#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:36:45.57#ibcon#enter wrdev, iclass 15, count 2 2006.169.07:36:45.57#ibcon#first serial, iclass 15, count 2 2006.169.07:36:45.57#ibcon#enter sib2, iclass 15, count 2 2006.169.07:36:45.57#ibcon#flushed, iclass 15, count 2 2006.169.07:36:45.57#ibcon#about to write, iclass 15, count 2 2006.169.07:36:45.57#ibcon#wrote, iclass 15, count 2 2006.169.07:36:45.57#ibcon#about to read 3, iclass 15, count 2 2006.169.07:36:45.59#ibcon#read 3, iclass 15, count 2 2006.169.07:36:45.59#ibcon#about to read 4, iclass 15, count 2 2006.169.07:36:45.59#ibcon#read 4, iclass 15, count 2 2006.169.07:36:45.59#ibcon#about to read 5, iclass 15, count 2 2006.169.07:36:45.59#ibcon#read 5, iclass 15, count 2 2006.169.07:36:45.59#ibcon#about to read 6, iclass 15, count 2 2006.169.07:36:45.59#ibcon#read 6, iclass 15, count 2 2006.169.07:36:45.59#ibcon#end of sib2, iclass 15, count 2 2006.169.07:36:45.59#ibcon#*mode == 0, iclass 15, count 2 2006.169.07:36:45.59#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.169.07:36:45.59#ibcon#[25=AT03-06\r\n] 2006.169.07:36:45.59#ibcon#*before write, iclass 15, count 2 2006.169.07:36:45.59#ibcon#enter sib2, iclass 15, count 2 2006.169.07:36:45.59#ibcon#flushed, iclass 15, count 2 2006.169.07:36:45.59#ibcon#about to write, iclass 15, count 2 2006.169.07:36:45.59#ibcon#wrote, iclass 15, count 2 2006.169.07:36:45.59#ibcon#about to read 3, iclass 15, count 2 2006.169.07:36:45.62#ibcon#read 3, iclass 15, count 2 2006.169.07:36:45.62#ibcon#about to read 4, iclass 15, count 2 2006.169.07:36:45.62#ibcon#read 4, iclass 15, count 2 2006.169.07:36:45.62#ibcon#about to read 5, iclass 15, count 2 2006.169.07:36:45.62#ibcon#read 5, iclass 15, count 2 2006.169.07:36:45.62#ibcon#about to read 6, iclass 15, count 2 2006.169.07:36:45.62#ibcon#read 6, iclass 15, count 2 2006.169.07:36:45.62#ibcon#end of sib2, iclass 15, count 2 2006.169.07:36:45.62#ibcon#*after write, iclass 15, count 2 2006.169.07:36:45.62#ibcon#*before return 0, iclass 15, count 2 2006.169.07:36:45.62#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:36:45.62#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:36:45.62#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.169.07:36:45.62#ibcon#ireg 7 cls_cnt 0 2006.169.07:36:45.62#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:36:45.74#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:36:45.74#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:36:45.74#ibcon#enter wrdev, iclass 15, count 0 2006.169.07:36:45.74#ibcon#first serial, iclass 15, count 0 2006.169.07:36:45.74#ibcon#enter sib2, iclass 15, count 0 2006.169.07:36:45.74#ibcon#flushed, iclass 15, count 0 2006.169.07:36:45.74#ibcon#about to write, iclass 15, count 0 2006.169.07:36:45.74#ibcon#wrote, iclass 15, count 0 2006.169.07:36:45.74#ibcon#about to read 3, iclass 15, count 0 2006.169.07:36:45.76#ibcon#read 3, iclass 15, count 0 2006.169.07:36:45.76#ibcon#about to read 4, iclass 15, count 0 2006.169.07:36:45.76#ibcon#read 4, iclass 15, count 0 2006.169.07:36:45.76#ibcon#about to read 5, iclass 15, count 0 2006.169.07:36:45.76#ibcon#read 5, iclass 15, count 0 2006.169.07:36:45.76#ibcon#about to read 6, iclass 15, count 0 2006.169.07:36:45.76#ibcon#read 6, iclass 15, count 0 2006.169.07:36:45.76#ibcon#end of sib2, iclass 15, count 0 2006.169.07:36:45.76#ibcon#*mode == 0, iclass 15, count 0 2006.169.07:36:45.76#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.169.07:36:45.76#ibcon#[25=USB\r\n] 2006.169.07:36:45.76#ibcon#*before write, iclass 15, count 0 2006.169.07:36:45.76#ibcon#enter sib2, iclass 15, count 0 2006.169.07:36:45.76#ibcon#flushed, iclass 15, count 0 2006.169.07:36:45.76#ibcon#about to write, iclass 15, count 0 2006.169.07:36:45.76#ibcon#wrote, iclass 15, count 0 2006.169.07:36:45.76#ibcon#about to read 3, iclass 15, count 0 2006.169.07:36:45.79#ibcon#read 3, iclass 15, count 0 2006.169.07:36:45.79#ibcon#about to read 4, iclass 15, count 0 2006.169.07:36:45.79#ibcon#read 4, iclass 15, count 0 2006.169.07:36:45.79#ibcon#about to read 5, iclass 15, count 0 2006.169.07:36:45.79#ibcon#read 5, iclass 15, count 0 2006.169.07:36:45.79#ibcon#about to read 6, iclass 15, count 0 2006.169.07:36:45.79#ibcon#read 6, iclass 15, count 0 2006.169.07:36:45.79#ibcon#end of sib2, iclass 15, count 0 2006.169.07:36:45.79#ibcon#*after write, iclass 15, count 0 2006.169.07:36:45.79#ibcon#*before return 0, iclass 15, count 0 2006.169.07:36:45.79#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:36:45.79#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:36:45.79#ibcon#about to clear, iclass 15 cls_cnt 0 2006.169.07:36:45.79#ibcon#cleared, iclass 15 cls_cnt 0 2006.169.07:36:45.79$vc4f8/valo=4,832.99 2006.169.07:36:45.79#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.169.07:36:45.79#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.169.07:36:45.79#ibcon#ireg 17 cls_cnt 0 2006.169.07:36:45.79#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:36:45.79#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:36:45.79#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:36:45.79#ibcon#enter wrdev, iclass 17, count 0 2006.169.07:36:45.79#ibcon#first serial, iclass 17, count 0 2006.169.07:36:45.79#ibcon#enter sib2, iclass 17, count 0 2006.169.07:36:45.79#ibcon#flushed, iclass 17, count 0 2006.169.07:36:45.79#ibcon#about to write, iclass 17, count 0 2006.169.07:36:45.79#ibcon#wrote, iclass 17, count 0 2006.169.07:36:45.79#ibcon#about to read 3, iclass 17, count 0 2006.169.07:36:45.81#ibcon#read 3, iclass 17, count 0 2006.169.07:36:45.81#ibcon#about to read 4, iclass 17, count 0 2006.169.07:36:45.81#ibcon#read 4, iclass 17, count 0 2006.169.07:36:45.81#ibcon#about to read 5, iclass 17, count 0 2006.169.07:36:45.81#ibcon#read 5, iclass 17, count 0 2006.169.07:36:45.81#ibcon#about to read 6, iclass 17, count 0 2006.169.07:36:45.81#ibcon#read 6, iclass 17, count 0 2006.169.07:36:45.81#ibcon#end of sib2, iclass 17, count 0 2006.169.07:36:45.81#ibcon#*mode == 0, iclass 17, count 0 2006.169.07:36:45.81#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.169.07:36:45.81#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.07:36:45.81#ibcon#*before write, iclass 17, count 0 2006.169.07:36:45.81#ibcon#enter sib2, iclass 17, count 0 2006.169.07:36:45.81#ibcon#flushed, iclass 17, count 0 2006.169.07:36:45.81#ibcon#about to write, iclass 17, count 0 2006.169.07:36:45.81#ibcon#wrote, iclass 17, count 0 2006.169.07:36:45.81#ibcon#about to read 3, iclass 17, count 0 2006.169.07:36:45.85#ibcon#read 3, iclass 17, count 0 2006.169.07:36:45.85#ibcon#about to read 4, iclass 17, count 0 2006.169.07:36:45.85#ibcon#read 4, iclass 17, count 0 2006.169.07:36:45.85#ibcon#about to read 5, iclass 17, count 0 2006.169.07:36:45.85#ibcon#read 5, iclass 17, count 0 2006.169.07:36:45.85#ibcon#about to read 6, iclass 17, count 0 2006.169.07:36:45.85#ibcon#read 6, iclass 17, count 0 2006.169.07:36:45.85#ibcon#end of sib2, iclass 17, count 0 2006.169.07:36:45.85#ibcon#*after write, iclass 17, count 0 2006.169.07:36:45.85#ibcon#*before return 0, iclass 17, count 0 2006.169.07:36:45.85#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:36:45.85#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:36:45.85#ibcon#about to clear, iclass 17 cls_cnt 0 2006.169.07:36:45.85#ibcon#cleared, iclass 17 cls_cnt 0 2006.169.07:36:45.85$vc4f8/va=4,7 2006.169.07:36:45.85#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.169.07:36:45.85#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.169.07:36:45.85#ibcon#ireg 11 cls_cnt 2 2006.169.07:36:45.85#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:36:45.91#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:36:45.91#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:36:45.91#ibcon#enter wrdev, iclass 19, count 2 2006.169.07:36:45.91#ibcon#first serial, iclass 19, count 2 2006.169.07:36:45.91#ibcon#enter sib2, iclass 19, count 2 2006.169.07:36:45.91#ibcon#flushed, iclass 19, count 2 2006.169.07:36:45.91#ibcon#about to write, iclass 19, count 2 2006.169.07:36:45.91#ibcon#wrote, iclass 19, count 2 2006.169.07:36:45.91#ibcon#about to read 3, iclass 19, count 2 2006.169.07:36:45.93#ibcon#read 3, iclass 19, count 2 2006.169.07:36:45.93#ibcon#about to read 4, iclass 19, count 2 2006.169.07:36:45.93#ibcon#read 4, iclass 19, count 2 2006.169.07:36:45.93#ibcon#about to read 5, iclass 19, count 2 2006.169.07:36:45.93#ibcon#read 5, iclass 19, count 2 2006.169.07:36:45.93#ibcon#about to read 6, iclass 19, count 2 2006.169.07:36:45.93#ibcon#read 6, iclass 19, count 2 2006.169.07:36:45.93#ibcon#end of sib2, iclass 19, count 2 2006.169.07:36:45.93#ibcon#*mode == 0, iclass 19, count 2 2006.169.07:36:45.93#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.169.07:36:45.93#ibcon#[25=AT04-07\r\n] 2006.169.07:36:45.93#ibcon#*before write, iclass 19, count 2 2006.169.07:36:45.93#ibcon#enter sib2, iclass 19, count 2 2006.169.07:36:45.93#ibcon#flushed, iclass 19, count 2 2006.169.07:36:45.93#ibcon#about to write, iclass 19, count 2 2006.169.07:36:45.93#ibcon#wrote, iclass 19, count 2 2006.169.07:36:45.93#ibcon#about to read 3, iclass 19, count 2 2006.169.07:36:45.96#ibcon#read 3, iclass 19, count 2 2006.169.07:36:45.96#ibcon#about to read 4, iclass 19, count 2 2006.169.07:36:45.96#ibcon#read 4, iclass 19, count 2 2006.169.07:36:45.96#ibcon#about to read 5, iclass 19, count 2 2006.169.07:36:45.96#ibcon#read 5, iclass 19, count 2 2006.169.07:36:45.96#ibcon#about to read 6, iclass 19, count 2 2006.169.07:36:45.96#ibcon#read 6, iclass 19, count 2 2006.169.07:36:45.96#ibcon#end of sib2, iclass 19, count 2 2006.169.07:36:45.96#ibcon#*after write, iclass 19, count 2 2006.169.07:36:45.96#ibcon#*before return 0, iclass 19, count 2 2006.169.07:36:45.96#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:36:45.96#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:36:45.96#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.169.07:36:45.96#ibcon#ireg 7 cls_cnt 0 2006.169.07:36:45.96#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:36:46.08#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:36:46.08#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:36:46.08#ibcon#enter wrdev, iclass 19, count 0 2006.169.07:36:46.08#ibcon#first serial, iclass 19, count 0 2006.169.07:36:46.08#ibcon#enter sib2, iclass 19, count 0 2006.169.07:36:46.08#ibcon#flushed, iclass 19, count 0 2006.169.07:36:46.08#ibcon#about to write, iclass 19, count 0 2006.169.07:36:46.08#ibcon#wrote, iclass 19, count 0 2006.169.07:36:46.08#ibcon#about to read 3, iclass 19, count 0 2006.169.07:36:46.10#ibcon#read 3, iclass 19, count 0 2006.169.07:36:46.10#ibcon#about to read 4, iclass 19, count 0 2006.169.07:36:46.10#ibcon#read 4, iclass 19, count 0 2006.169.07:36:46.10#ibcon#about to read 5, iclass 19, count 0 2006.169.07:36:46.10#ibcon#read 5, iclass 19, count 0 2006.169.07:36:46.10#ibcon#about to read 6, iclass 19, count 0 2006.169.07:36:46.10#ibcon#read 6, iclass 19, count 0 2006.169.07:36:46.10#ibcon#end of sib2, iclass 19, count 0 2006.169.07:36:46.10#ibcon#*mode == 0, iclass 19, count 0 2006.169.07:36:46.10#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.169.07:36:46.10#ibcon#[25=USB\r\n] 2006.169.07:36:46.10#ibcon#*before write, iclass 19, count 0 2006.169.07:36:46.10#ibcon#enter sib2, iclass 19, count 0 2006.169.07:36:46.10#ibcon#flushed, iclass 19, count 0 2006.169.07:36:46.10#ibcon#about to write, iclass 19, count 0 2006.169.07:36:46.10#ibcon#wrote, iclass 19, count 0 2006.169.07:36:46.10#ibcon#about to read 3, iclass 19, count 0 2006.169.07:36:46.13#ibcon#read 3, iclass 19, count 0 2006.169.07:36:46.13#ibcon#about to read 4, iclass 19, count 0 2006.169.07:36:46.13#ibcon#read 4, iclass 19, count 0 2006.169.07:36:46.13#ibcon#about to read 5, iclass 19, count 0 2006.169.07:36:46.13#ibcon#read 5, iclass 19, count 0 2006.169.07:36:46.13#ibcon#about to read 6, iclass 19, count 0 2006.169.07:36:46.13#ibcon#read 6, iclass 19, count 0 2006.169.07:36:46.13#ibcon#end of sib2, iclass 19, count 0 2006.169.07:36:46.13#ibcon#*after write, iclass 19, count 0 2006.169.07:36:46.13#ibcon#*before return 0, iclass 19, count 0 2006.169.07:36:46.13#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:36:46.13#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:36:46.13#ibcon#about to clear, iclass 19 cls_cnt 0 2006.169.07:36:46.13#ibcon#cleared, iclass 19 cls_cnt 0 2006.169.07:36:46.13$vc4f8/valo=5,652.99 2006.169.07:36:46.13#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.169.07:36:46.13#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.169.07:36:46.13#ibcon#ireg 17 cls_cnt 0 2006.169.07:36:46.13#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:36:46.13#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:36:46.13#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:36:46.13#ibcon#enter wrdev, iclass 21, count 0 2006.169.07:36:46.13#ibcon#first serial, iclass 21, count 0 2006.169.07:36:46.13#ibcon#enter sib2, iclass 21, count 0 2006.169.07:36:46.13#ibcon#flushed, iclass 21, count 0 2006.169.07:36:46.13#ibcon#about to write, iclass 21, count 0 2006.169.07:36:46.13#ibcon#wrote, iclass 21, count 0 2006.169.07:36:46.13#ibcon#about to read 3, iclass 21, count 0 2006.169.07:36:46.15#ibcon#read 3, iclass 21, count 0 2006.169.07:36:46.15#ibcon#about to read 4, iclass 21, count 0 2006.169.07:36:46.15#ibcon#read 4, iclass 21, count 0 2006.169.07:36:46.15#ibcon#about to read 5, iclass 21, count 0 2006.169.07:36:46.15#ibcon#read 5, iclass 21, count 0 2006.169.07:36:46.15#ibcon#about to read 6, iclass 21, count 0 2006.169.07:36:46.15#ibcon#read 6, iclass 21, count 0 2006.169.07:36:46.15#ibcon#end of sib2, iclass 21, count 0 2006.169.07:36:46.15#ibcon#*mode == 0, iclass 21, count 0 2006.169.07:36:46.15#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.169.07:36:46.15#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.07:36:46.15#ibcon#*before write, iclass 21, count 0 2006.169.07:36:46.15#ibcon#enter sib2, iclass 21, count 0 2006.169.07:36:46.15#ibcon#flushed, iclass 21, count 0 2006.169.07:36:46.15#ibcon#about to write, iclass 21, count 0 2006.169.07:36:46.15#ibcon#wrote, iclass 21, count 0 2006.169.07:36:46.15#ibcon#about to read 3, iclass 21, count 0 2006.169.07:36:46.19#ibcon#read 3, iclass 21, count 0 2006.169.07:36:46.19#ibcon#about to read 4, iclass 21, count 0 2006.169.07:36:46.19#ibcon#read 4, iclass 21, count 0 2006.169.07:36:46.19#ibcon#about to read 5, iclass 21, count 0 2006.169.07:36:46.19#ibcon#read 5, iclass 21, count 0 2006.169.07:36:46.19#ibcon#about to read 6, iclass 21, count 0 2006.169.07:36:46.19#ibcon#read 6, iclass 21, count 0 2006.169.07:36:46.19#ibcon#end of sib2, iclass 21, count 0 2006.169.07:36:46.19#ibcon#*after write, iclass 21, count 0 2006.169.07:36:46.19#ibcon#*before return 0, iclass 21, count 0 2006.169.07:36:46.19#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:36:46.19#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:36:46.19#ibcon#about to clear, iclass 21 cls_cnt 0 2006.169.07:36:46.19#ibcon#cleared, iclass 21 cls_cnt 0 2006.169.07:36:46.19$vc4f8/va=5,7 2006.169.07:36:46.19#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.169.07:36:46.19#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.169.07:36:46.19#ibcon#ireg 11 cls_cnt 2 2006.169.07:36:46.19#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.169.07:36:46.25#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.169.07:36:46.25#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.169.07:36:46.25#ibcon#enter wrdev, iclass 23, count 2 2006.169.07:36:46.25#ibcon#first serial, iclass 23, count 2 2006.169.07:36:46.25#ibcon#enter sib2, iclass 23, count 2 2006.169.07:36:46.25#ibcon#flushed, iclass 23, count 2 2006.169.07:36:46.25#ibcon#about to write, iclass 23, count 2 2006.169.07:36:46.25#ibcon#wrote, iclass 23, count 2 2006.169.07:36:46.25#ibcon#about to read 3, iclass 23, count 2 2006.169.07:36:46.27#ibcon#read 3, iclass 23, count 2 2006.169.07:36:46.27#ibcon#about to read 4, iclass 23, count 2 2006.169.07:36:46.27#ibcon#read 4, iclass 23, count 2 2006.169.07:36:46.27#ibcon#about to read 5, iclass 23, count 2 2006.169.07:36:46.27#ibcon#read 5, iclass 23, count 2 2006.169.07:36:46.27#ibcon#about to read 6, iclass 23, count 2 2006.169.07:36:46.27#ibcon#read 6, iclass 23, count 2 2006.169.07:36:46.27#ibcon#end of sib2, iclass 23, count 2 2006.169.07:36:46.27#ibcon#*mode == 0, iclass 23, count 2 2006.169.07:36:46.27#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.169.07:36:46.27#ibcon#[25=AT05-07\r\n] 2006.169.07:36:46.27#ibcon#*before write, iclass 23, count 2 2006.169.07:36:46.27#ibcon#enter sib2, iclass 23, count 2 2006.169.07:36:46.27#ibcon#flushed, iclass 23, count 2 2006.169.07:36:46.27#ibcon#about to write, iclass 23, count 2 2006.169.07:36:46.27#ibcon#wrote, iclass 23, count 2 2006.169.07:36:46.27#ibcon#about to read 3, iclass 23, count 2 2006.169.07:36:46.30#ibcon#read 3, iclass 23, count 2 2006.169.07:36:46.30#ibcon#about to read 4, iclass 23, count 2 2006.169.07:36:46.30#ibcon#read 4, iclass 23, count 2 2006.169.07:36:46.30#ibcon#about to read 5, iclass 23, count 2 2006.169.07:36:46.30#ibcon#read 5, iclass 23, count 2 2006.169.07:36:46.30#ibcon#about to read 6, iclass 23, count 2 2006.169.07:36:46.30#ibcon#read 6, iclass 23, count 2 2006.169.07:36:46.30#ibcon#end of sib2, iclass 23, count 2 2006.169.07:36:46.30#ibcon#*after write, iclass 23, count 2 2006.169.07:36:46.30#ibcon#*before return 0, iclass 23, count 2 2006.169.07:36:46.30#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.169.07:36:46.30#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.169.07:36:46.30#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.169.07:36:46.30#ibcon#ireg 7 cls_cnt 0 2006.169.07:36:46.30#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.169.07:36:46.42#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.169.07:36:46.42#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.169.07:36:46.42#ibcon#enter wrdev, iclass 23, count 0 2006.169.07:36:46.42#ibcon#first serial, iclass 23, count 0 2006.169.07:36:46.42#ibcon#enter sib2, iclass 23, count 0 2006.169.07:36:46.42#ibcon#flushed, iclass 23, count 0 2006.169.07:36:46.42#ibcon#about to write, iclass 23, count 0 2006.169.07:36:46.42#ibcon#wrote, iclass 23, count 0 2006.169.07:36:46.42#ibcon#about to read 3, iclass 23, count 0 2006.169.07:36:46.44#ibcon#read 3, iclass 23, count 0 2006.169.07:36:46.44#ibcon#about to read 4, iclass 23, count 0 2006.169.07:36:46.44#ibcon#read 4, iclass 23, count 0 2006.169.07:36:46.44#ibcon#about to read 5, iclass 23, count 0 2006.169.07:36:46.44#ibcon#read 5, iclass 23, count 0 2006.169.07:36:46.44#ibcon#about to read 6, iclass 23, count 0 2006.169.07:36:46.44#ibcon#read 6, iclass 23, count 0 2006.169.07:36:46.44#ibcon#end of sib2, iclass 23, count 0 2006.169.07:36:46.44#ibcon#*mode == 0, iclass 23, count 0 2006.169.07:36:46.44#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.169.07:36:46.44#ibcon#[25=USB\r\n] 2006.169.07:36:46.44#ibcon#*before write, iclass 23, count 0 2006.169.07:36:46.44#ibcon#enter sib2, iclass 23, count 0 2006.169.07:36:46.44#ibcon#flushed, iclass 23, count 0 2006.169.07:36:46.44#ibcon#about to write, iclass 23, count 0 2006.169.07:36:46.44#ibcon#wrote, iclass 23, count 0 2006.169.07:36:46.44#ibcon#about to read 3, iclass 23, count 0 2006.169.07:36:46.47#ibcon#read 3, iclass 23, count 0 2006.169.07:36:46.47#ibcon#about to read 4, iclass 23, count 0 2006.169.07:36:46.47#ibcon#read 4, iclass 23, count 0 2006.169.07:36:46.47#ibcon#about to read 5, iclass 23, count 0 2006.169.07:36:46.47#ibcon#read 5, iclass 23, count 0 2006.169.07:36:46.47#ibcon#about to read 6, iclass 23, count 0 2006.169.07:36:46.47#ibcon#read 6, iclass 23, count 0 2006.169.07:36:46.47#ibcon#end of sib2, iclass 23, count 0 2006.169.07:36:46.47#ibcon#*after write, iclass 23, count 0 2006.169.07:36:46.47#ibcon#*before return 0, iclass 23, count 0 2006.169.07:36:46.47#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.169.07:36:46.47#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.169.07:36:46.47#ibcon#about to clear, iclass 23 cls_cnt 0 2006.169.07:36:46.47#ibcon#cleared, iclass 23 cls_cnt 0 2006.169.07:36:46.47$vc4f8/valo=6,772.99 2006.169.07:36:46.47#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.169.07:36:46.47#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.169.07:36:46.47#ibcon#ireg 17 cls_cnt 0 2006.169.07:36:46.47#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:36:46.47#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:36:46.47#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:36:46.47#ibcon#enter wrdev, iclass 25, count 0 2006.169.07:36:46.47#ibcon#first serial, iclass 25, count 0 2006.169.07:36:46.47#ibcon#enter sib2, iclass 25, count 0 2006.169.07:36:46.47#ibcon#flushed, iclass 25, count 0 2006.169.07:36:46.47#ibcon#about to write, iclass 25, count 0 2006.169.07:36:46.47#ibcon#wrote, iclass 25, count 0 2006.169.07:36:46.47#ibcon#about to read 3, iclass 25, count 0 2006.169.07:36:46.49#ibcon#read 3, iclass 25, count 0 2006.169.07:36:46.49#ibcon#about to read 4, iclass 25, count 0 2006.169.07:36:46.49#ibcon#read 4, iclass 25, count 0 2006.169.07:36:46.49#ibcon#about to read 5, iclass 25, count 0 2006.169.07:36:46.49#ibcon#read 5, iclass 25, count 0 2006.169.07:36:46.49#ibcon#about to read 6, iclass 25, count 0 2006.169.07:36:46.49#ibcon#read 6, iclass 25, count 0 2006.169.07:36:46.49#ibcon#end of sib2, iclass 25, count 0 2006.169.07:36:46.49#ibcon#*mode == 0, iclass 25, count 0 2006.169.07:36:46.49#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.169.07:36:46.49#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.07:36:46.49#ibcon#*before write, iclass 25, count 0 2006.169.07:36:46.49#ibcon#enter sib2, iclass 25, count 0 2006.169.07:36:46.49#ibcon#flushed, iclass 25, count 0 2006.169.07:36:46.49#ibcon#about to write, iclass 25, count 0 2006.169.07:36:46.49#ibcon#wrote, iclass 25, count 0 2006.169.07:36:46.49#ibcon#about to read 3, iclass 25, count 0 2006.169.07:36:46.53#ibcon#read 3, iclass 25, count 0 2006.169.07:36:46.53#ibcon#about to read 4, iclass 25, count 0 2006.169.07:36:46.53#ibcon#read 4, iclass 25, count 0 2006.169.07:36:46.53#ibcon#about to read 5, iclass 25, count 0 2006.169.07:36:46.53#ibcon#read 5, iclass 25, count 0 2006.169.07:36:46.53#ibcon#about to read 6, iclass 25, count 0 2006.169.07:36:46.53#ibcon#read 6, iclass 25, count 0 2006.169.07:36:46.53#ibcon#end of sib2, iclass 25, count 0 2006.169.07:36:46.53#ibcon#*after write, iclass 25, count 0 2006.169.07:36:46.53#ibcon#*before return 0, iclass 25, count 0 2006.169.07:36:46.53#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:36:46.53#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:36:46.53#ibcon#about to clear, iclass 25 cls_cnt 0 2006.169.07:36:46.53#ibcon#cleared, iclass 25 cls_cnt 0 2006.169.07:36:46.53$vc4f8/va=6,6 2006.169.07:36:46.53#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.169.07:36:46.53#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.169.07:36:46.53#ibcon#ireg 11 cls_cnt 2 2006.169.07:36:46.53#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.169.07:36:46.59#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.169.07:36:46.59#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.169.07:36:46.59#ibcon#enter wrdev, iclass 27, count 2 2006.169.07:36:46.59#ibcon#first serial, iclass 27, count 2 2006.169.07:36:46.59#ibcon#enter sib2, iclass 27, count 2 2006.169.07:36:46.59#ibcon#flushed, iclass 27, count 2 2006.169.07:36:46.59#ibcon#about to write, iclass 27, count 2 2006.169.07:36:46.59#ibcon#wrote, iclass 27, count 2 2006.169.07:36:46.59#ibcon#about to read 3, iclass 27, count 2 2006.169.07:36:46.61#ibcon#read 3, iclass 27, count 2 2006.169.07:36:46.61#ibcon#about to read 4, iclass 27, count 2 2006.169.07:36:46.61#ibcon#read 4, iclass 27, count 2 2006.169.07:36:46.61#ibcon#about to read 5, iclass 27, count 2 2006.169.07:36:46.61#ibcon#read 5, iclass 27, count 2 2006.169.07:36:46.61#ibcon#about to read 6, iclass 27, count 2 2006.169.07:36:46.61#ibcon#read 6, iclass 27, count 2 2006.169.07:36:46.61#ibcon#end of sib2, iclass 27, count 2 2006.169.07:36:46.61#ibcon#*mode == 0, iclass 27, count 2 2006.169.07:36:46.61#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.169.07:36:46.61#ibcon#[25=AT06-06\r\n] 2006.169.07:36:46.61#ibcon#*before write, iclass 27, count 2 2006.169.07:36:46.61#ibcon#enter sib2, iclass 27, count 2 2006.169.07:36:46.61#ibcon#flushed, iclass 27, count 2 2006.169.07:36:46.61#ibcon#about to write, iclass 27, count 2 2006.169.07:36:46.61#ibcon#wrote, iclass 27, count 2 2006.169.07:36:46.61#ibcon#about to read 3, iclass 27, count 2 2006.169.07:36:46.64#ibcon#read 3, iclass 27, count 2 2006.169.07:36:46.64#ibcon#about to read 4, iclass 27, count 2 2006.169.07:36:46.64#ibcon#read 4, iclass 27, count 2 2006.169.07:36:46.64#ibcon#about to read 5, iclass 27, count 2 2006.169.07:36:46.64#ibcon#read 5, iclass 27, count 2 2006.169.07:36:46.64#ibcon#about to read 6, iclass 27, count 2 2006.169.07:36:46.64#ibcon#read 6, iclass 27, count 2 2006.169.07:36:46.64#ibcon#end of sib2, iclass 27, count 2 2006.169.07:36:46.64#ibcon#*after write, iclass 27, count 2 2006.169.07:36:46.64#ibcon#*before return 0, iclass 27, count 2 2006.169.07:36:46.64#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.169.07:36:46.64#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.169.07:36:46.64#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.169.07:36:46.64#ibcon#ireg 7 cls_cnt 0 2006.169.07:36:46.64#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.169.07:36:46.76#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.169.07:36:46.76#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.169.07:36:46.76#ibcon#enter wrdev, iclass 27, count 0 2006.169.07:36:46.76#ibcon#first serial, iclass 27, count 0 2006.169.07:36:46.76#ibcon#enter sib2, iclass 27, count 0 2006.169.07:36:46.76#ibcon#flushed, iclass 27, count 0 2006.169.07:36:46.76#ibcon#about to write, iclass 27, count 0 2006.169.07:36:46.76#ibcon#wrote, iclass 27, count 0 2006.169.07:36:46.76#ibcon#about to read 3, iclass 27, count 0 2006.169.07:36:46.78#ibcon#read 3, iclass 27, count 0 2006.169.07:36:46.78#ibcon#about to read 4, iclass 27, count 0 2006.169.07:36:46.78#ibcon#read 4, iclass 27, count 0 2006.169.07:36:46.78#ibcon#about to read 5, iclass 27, count 0 2006.169.07:36:46.78#ibcon#read 5, iclass 27, count 0 2006.169.07:36:46.78#ibcon#about to read 6, iclass 27, count 0 2006.169.07:36:46.78#ibcon#read 6, iclass 27, count 0 2006.169.07:36:46.78#ibcon#end of sib2, iclass 27, count 0 2006.169.07:36:46.78#ibcon#*mode == 0, iclass 27, count 0 2006.169.07:36:46.78#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.169.07:36:46.78#ibcon#[25=USB\r\n] 2006.169.07:36:46.78#ibcon#*before write, iclass 27, count 0 2006.169.07:36:46.78#ibcon#enter sib2, iclass 27, count 0 2006.169.07:36:46.78#ibcon#flushed, iclass 27, count 0 2006.169.07:36:46.78#ibcon#about to write, iclass 27, count 0 2006.169.07:36:46.78#ibcon#wrote, iclass 27, count 0 2006.169.07:36:46.78#ibcon#about to read 3, iclass 27, count 0 2006.169.07:36:46.81#ibcon#read 3, iclass 27, count 0 2006.169.07:36:46.81#ibcon#about to read 4, iclass 27, count 0 2006.169.07:36:46.81#ibcon#read 4, iclass 27, count 0 2006.169.07:36:46.81#ibcon#about to read 5, iclass 27, count 0 2006.169.07:36:46.81#ibcon#read 5, iclass 27, count 0 2006.169.07:36:46.81#ibcon#about to read 6, iclass 27, count 0 2006.169.07:36:46.81#ibcon#read 6, iclass 27, count 0 2006.169.07:36:46.81#ibcon#end of sib2, iclass 27, count 0 2006.169.07:36:46.81#ibcon#*after write, iclass 27, count 0 2006.169.07:36:46.81#ibcon#*before return 0, iclass 27, count 0 2006.169.07:36:46.81#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.169.07:36:46.81#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.169.07:36:46.81#ibcon#about to clear, iclass 27 cls_cnt 0 2006.169.07:36:46.81#ibcon#cleared, iclass 27 cls_cnt 0 2006.169.07:36:46.81$vc4f8/valo=7,832.99 2006.169.07:36:46.81#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.169.07:36:46.81#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.169.07:36:46.81#ibcon#ireg 17 cls_cnt 0 2006.169.07:36:46.81#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.169.07:36:46.81#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.169.07:36:46.81#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.169.07:36:46.81#ibcon#enter wrdev, iclass 29, count 0 2006.169.07:36:46.81#ibcon#first serial, iclass 29, count 0 2006.169.07:36:46.81#ibcon#enter sib2, iclass 29, count 0 2006.169.07:36:46.81#ibcon#flushed, iclass 29, count 0 2006.169.07:36:46.81#ibcon#about to write, iclass 29, count 0 2006.169.07:36:46.81#ibcon#wrote, iclass 29, count 0 2006.169.07:36:46.81#ibcon#about to read 3, iclass 29, count 0 2006.169.07:36:46.83#ibcon#read 3, iclass 29, count 0 2006.169.07:36:46.83#ibcon#about to read 4, iclass 29, count 0 2006.169.07:36:46.83#ibcon#read 4, iclass 29, count 0 2006.169.07:36:46.83#ibcon#about to read 5, iclass 29, count 0 2006.169.07:36:46.83#ibcon#read 5, iclass 29, count 0 2006.169.07:36:46.83#ibcon#about to read 6, iclass 29, count 0 2006.169.07:36:46.83#ibcon#read 6, iclass 29, count 0 2006.169.07:36:46.83#ibcon#end of sib2, iclass 29, count 0 2006.169.07:36:46.83#ibcon#*mode == 0, iclass 29, count 0 2006.169.07:36:46.83#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.169.07:36:46.83#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.07:36:46.83#ibcon#*before write, iclass 29, count 0 2006.169.07:36:46.83#ibcon#enter sib2, iclass 29, count 0 2006.169.07:36:46.83#ibcon#flushed, iclass 29, count 0 2006.169.07:36:46.83#ibcon#about to write, iclass 29, count 0 2006.169.07:36:46.83#ibcon#wrote, iclass 29, count 0 2006.169.07:36:46.83#ibcon#about to read 3, iclass 29, count 0 2006.169.07:36:46.87#ibcon#read 3, iclass 29, count 0 2006.169.07:36:46.87#ibcon#about to read 4, iclass 29, count 0 2006.169.07:36:46.87#ibcon#read 4, iclass 29, count 0 2006.169.07:36:46.87#ibcon#about to read 5, iclass 29, count 0 2006.169.07:36:46.87#ibcon#read 5, iclass 29, count 0 2006.169.07:36:46.87#ibcon#about to read 6, iclass 29, count 0 2006.169.07:36:46.87#ibcon#read 6, iclass 29, count 0 2006.169.07:36:46.87#ibcon#end of sib2, iclass 29, count 0 2006.169.07:36:46.87#ibcon#*after write, iclass 29, count 0 2006.169.07:36:46.87#ibcon#*before return 0, iclass 29, count 0 2006.169.07:36:46.87#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.169.07:36:46.87#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.169.07:36:46.87#ibcon#about to clear, iclass 29 cls_cnt 0 2006.169.07:36:46.87#ibcon#cleared, iclass 29 cls_cnt 0 2006.169.07:36:46.87$vc4f8/va=7,6 2006.169.07:36:46.87#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.169.07:36:46.87#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.169.07:36:46.87#ibcon#ireg 11 cls_cnt 2 2006.169.07:36:46.87#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.169.07:36:46.93#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.169.07:36:46.93#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.169.07:36:46.93#ibcon#enter wrdev, iclass 31, count 2 2006.169.07:36:46.93#ibcon#first serial, iclass 31, count 2 2006.169.07:36:46.93#ibcon#enter sib2, iclass 31, count 2 2006.169.07:36:46.93#ibcon#flushed, iclass 31, count 2 2006.169.07:36:46.93#ibcon#about to write, iclass 31, count 2 2006.169.07:36:46.93#ibcon#wrote, iclass 31, count 2 2006.169.07:36:46.93#ibcon#about to read 3, iclass 31, count 2 2006.169.07:36:46.95#ibcon#read 3, iclass 31, count 2 2006.169.07:36:46.95#ibcon#about to read 4, iclass 31, count 2 2006.169.07:36:46.95#ibcon#read 4, iclass 31, count 2 2006.169.07:36:46.95#ibcon#about to read 5, iclass 31, count 2 2006.169.07:36:46.95#ibcon#read 5, iclass 31, count 2 2006.169.07:36:46.95#ibcon#about to read 6, iclass 31, count 2 2006.169.07:36:46.95#ibcon#read 6, iclass 31, count 2 2006.169.07:36:46.95#ibcon#end of sib2, iclass 31, count 2 2006.169.07:36:46.95#ibcon#*mode == 0, iclass 31, count 2 2006.169.07:36:46.95#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.169.07:36:46.95#ibcon#[25=AT07-06\r\n] 2006.169.07:36:46.95#ibcon#*before write, iclass 31, count 2 2006.169.07:36:46.95#ibcon#enter sib2, iclass 31, count 2 2006.169.07:36:46.95#ibcon#flushed, iclass 31, count 2 2006.169.07:36:46.95#ibcon#about to write, iclass 31, count 2 2006.169.07:36:46.95#ibcon#wrote, iclass 31, count 2 2006.169.07:36:46.95#ibcon#about to read 3, iclass 31, count 2 2006.169.07:36:46.98#ibcon#read 3, iclass 31, count 2 2006.169.07:36:46.98#ibcon#about to read 4, iclass 31, count 2 2006.169.07:36:46.98#ibcon#read 4, iclass 31, count 2 2006.169.07:36:46.98#ibcon#about to read 5, iclass 31, count 2 2006.169.07:36:46.98#ibcon#read 5, iclass 31, count 2 2006.169.07:36:46.98#ibcon#about to read 6, iclass 31, count 2 2006.169.07:36:46.98#ibcon#read 6, iclass 31, count 2 2006.169.07:36:46.98#ibcon#end of sib2, iclass 31, count 2 2006.169.07:36:46.98#ibcon#*after write, iclass 31, count 2 2006.169.07:36:46.98#ibcon#*before return 0, iclass 31, count 2 2006.169.07:36:46.98#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.169.07:36:46.98#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.169.07:36:46.98#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.169.07:36:46.98#ibcon#ireg 7 cls_cnt 0 2006.169.07:36:46.98#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.169.07:36:47.10#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.169.07:36:47.10#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.169.07:36:47.10#ibcon#enter wrdev, iclass 31, count 0 2006.169.07:36:47.10#ibcon#first serial, iclass 31, count 0 2006.169.07:36:47.10#ibcon#enter sib2, iclass 31, count 0 2006.169.07:36:47.10#ibcon#flushed, iclass 31, count 0 2006.169.07:36:47.10#ibcon#about to write, iclass 31, count 0 2006.169.07:36:47.10#ibcon#wrote, iclass 31, count 0 2006.169.07:36:47.10#ibcon#about to read 3, iclass 31, count 0 2006.169.07:36:47.12#ibcon#read 3, iclass 31, count 0 2006.169.07:36:47.12#ibcon#about to read 4, iclass 31, count 0 2006.169.07:36:47.12#ibcon#read 4, iclass 31, count 0 2006.169.07:36:47.12#ibcon#about to read 5, iclass 31, count 0 2006.169.07:36:47.12#ibcon#read 5, iclass 31, count 0 2006.169.07:36:47.12#ibcon#about to read 6, iclass 31, count 0 2006.169.07:36:47.12#ibcon#read 6, iclass 31, count 0 2006.169.07:36:47.12#ibcon#end of sib2, iclass 31, count 0 2006.169.07:36:47.12#ibcon#*mode == 0, iclass 31, count 0 2006.169.07:36:47.12#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.169.07:36:47.12#ibcon#[25=USB\r\n] 2006.169.07:36:47.12#ibcon#*before write, iclass 31, count 0 2006.169.07:36:47.12#ibcon#enter sib2, iclass 31, count 0 2006.169.07:36:47.12#ibcon#flushed, iclass 31, count 0 2006.169.07:36:47.12#ibcon#about to write, iclass 31, count 0 2006.169.07:36:47.12#ibcon#wrote, iclass 31, count 0 2006.169.07:36:47.12#ibcon#about to read 3, iclass 31, count 0 2006.169.07:36:47.14#trakl#Source acquired 2006.169.07:36:47.15#ibcon#read 3, iclass 31, count 0 2006.169.07:36:47.15#ibcon#about to read 4, iclass 31, count 0 2006.169.07:36:47.15#ibcon#read 4, iclass 31, count 0 2006.169.07:36:47.15#ibcon#about to read 5, iclass 31, count 0 2006.169.07:36:47.15#ibcon#read 5, iclass 31, count 0 2006.169.07:36:47.15#ibcon#about to read 6, iclass 31, count 0 2006.169.07:36:47.15#ibcon#read 6, iclass 31, count 0 2006.169.07:36:47.15#ibcon#end of sib2, iclass 31, count 0 2006.169.07:36:47.15#ibcon#*after write, iclass 31, count 0 2006.169.07:36:47.15#ibcon#*before return 0, iclass 31, count 0 2006.169.07:36:47.15#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.169.07:36:47.15#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.169.07:36:47.15#ibcon#about to clear, iclass 31 cls_cnt 0 2006.169.07:36:47.15#ibcon#cleared, iclass 31 cls_cnt 0 2006.169.07:36:47.15$vc4f8/valo=8,852.99 2006.169.07:36:47.15#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.169.07:36:47.15#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.169.07:36:47.15#ibcon#ireg 17 cls_cnt 0 2006.169.07:36:47.15#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:36:47.15#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:36:47.15#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:36:47.15#ibcon#enter wrdev, iclass 33, count 0 2006.169.07:36:47.15#ibcon#first serial, iclass 33, count 0 2006.169.07:36:47.15#ibcon#enter sib2, iclass 33, count 0 2006.169.07:36:47.15#ibcon#flushed, iclass 33, count 0 2006.169.07:36:47.15#ibcon#about to write, iclass 33, count 0 2006.169.07:36:47.15#ibcon#wrote, iclass 33, count 0 2006.169.07:36:47.15#ibcon#about to read 3, iclass 33, count 0 2006.169.07:36:47.17#ibcon#read 3, iclass 33, count 0 2006.169.07:36:47.17#ibcon#about to read 4, iclass 33, count 0 2006.169.07:36:47.17#ibcon#read 4, iclass 33, count 0 2006.169.07:36:47.17#ibcon#about to read 5, iclass 33, count 0 2006.169.07:36:47.17#ibcon#read 5, iclass 33, count 0 2006.169.07:36:47.17#ibcon#about to read 6, iclass 33, count 0 2006.169.07:36:47.17#ibcon#read 6, iclass 33, count 0 2006.169.07:36:47.17#ibcon#end of sib2, iclass 33, count 0 2006.169.07:36:47.17#ibcon#*mode == 0, iclass 33, count 0 2006.169.07:36:47.17#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.169.07:36:47.17#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.07:36:47.17#ibcon#*before write, iclass 33, count 0 2006.169.07:36:47.17#ibcon#enter sib2, iclass 33, count 0 2006.169.07:36:47.17#ibcon#flushed, iclass 33, count 0 2006.169.07:36:47.17#ibcon#about to write, iclass 33, count 0 2006.169.07:36:47.17#ibcon#wrote, iclass 33, count 0 2006.169.07:36:47.17#ibcon#about to read 3, iclass 33, count 0 2006.169.07:36:47.21#ibcon#read 3, iclass 33, count 0 2006.169.07:36:47.21#ibcon#about to read 4, iclass 33, count 0 2006.169.07:36:47.21#ibcon#read 4, iclass 33, count 0 2006.169.07:36:47.21#ibcon#about to read 5, iclass 33, count 0 2006.169.07:36:47.21#ibcon#read 5, iclass 33, count 0 2006.169.07:36:47.21#ibcon#about to read 6, iclass 33, count 0 2006.169.07:36:47.21#ibcon#read 6, iclass 33, count 0 2006.169.07:36:47.21#ibcon#end of sib2, iclass 33, count 0 2006.169.07:36:47.21#ibcon#*after write, iclass 33, count 0 2006.169.07:36:47.21#ibcon#*before return 0, iclass 33, count 0 2006.169.07:36:47.21#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:36:47.21#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:36:47.21#ibcon#about to clear, iclass 33 cls_cnt 0 2006.169.07:36:47.21#ibcon#cleared, iclass 33 cls_cnt 0 2006.169.07:36:47.21$vc4f8/va=8,7 2006.169.07:36:47.21#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.169.07:36:47.21#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.169.07:36:47.21#ibcon#ireg 11 cls_cnt 2 2006.169.07:36:47.21#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:36:47.27#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:36:47.27#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:36:47.27#ibcon#enter wrdev, iclass 35, count 2 2006.169.07:36:47.27#ibcon#first serial, iclass 35, count 2 2006.169.07:36:47.27#ibcon#enter sib2, iclass 35, count 2 2006.169.07:36:47.27#ibcon#flushed, iclass 35, count 2 2006.169.07:36:47.27#ibcon#about to write, iclass 35, count 2 2006.169.07:36:47.27#ibcon#wrote, iclass 35, count 2 2006.169.07:36:47.27#ibcon#about to read 3, iclass 35, count 2 2006.169.07:36:47.29#ibcon#read 3, iclass 35, count 2 2006.169.07:36:47.29#ibcon#about to read 4, iclass 35, count 2 2006.169.07:36:47.29#ibcon#read 4, iclass 35, count 2 2006.169.07:36:47.29#ibcon#about to read 5, iclass 35, count 2 2006.169.07:36:47.29#ibcon#read 5, iclass 35, count 2 2006.169.07:36:47.29#ibcon#about to read 6, iclass 35, count 2 2006.169.07:36:47.29#ibcon#read 6, iclass 35, count 2 2006.169.07:36:47.29#ibcon#end of sib2, iclass 35, count 2 2006.169.07:36:47.29#ibcon#*mode == 0, iclass 35, count 2 2006.169.07:36:47.29#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.169.07:36:47.29#ibcon#[25=AT08-07\r\n] 2006.169.07:36:47.29#ibcon#*before write, iclass 35, count 2 2006.169.07:36:47.29#ibcon#enter sib2, iclass 35, count 2 2006.169.07:36:47.29#ibcon#flushed, iclass 35, count 2 2006.169.07:36:47.29#ibcon#about to write, iclass 35, count 2 2006.169.07:36:47.29#ibcon#wrote, iclass 35, count 2 2006.169.07:36:47.29#ibcon#about to read 3, iclass 35, count 2 2006.169.07:36:47.32#ibcon#read 3, iclass 35, count 2 2006.169.07:36:47.32#ibcon#about to read 4, iclass 35, count 2 2006.169.07:36:47.32#ibcon#read 4, iclass 35, count 2 2006.169.07:36:47.32#ibcon#about to read 5, iclass 35, count 2 2006.169.07:36:47.32#ibcon#read 5, iclass 35, count 2 2006.169.07:36:47.32#ibcon#about to read 6, iclass 35, count 2 2006.169.07:36:47.32#ibcon#read 6, iclass 35, count 2 2006.169.07:36:47.32#ibcon#end of sib2, iclass 35, count 2 2006.169.07:36:47.32#ibcon#*after write, iclass 35, count 2 2006.169.07:36:47.32#ibcon#*before return 0, iclass 35, count 2 2006.169.07:36:47.32#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:36:47.32#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:36:47.32#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.169.07:36:47.32#ibcon#ireg 7 cls_cnt 0 2006.169.07:36:47.32#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:36:47.44#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:36:47.44#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:36:47.44#ibcon#enter wrdev, iclass 35, count 0 2006.169.07:36:47.44#ibcon#first serial, iclass 35, count 0 2006.169.07:36:47.44#ibcon#enter sib2, iclass 35, count 0 2006.169.07:36:47.44#ibcon#flushed, iclass 35, count 0 2006.169.07:36:47.44#ibcon#about to write, iclass 35, count 0 2006.169.07:36:47.44#ibcon#wrote, iclass 35, count 0 2006.169.07:36:47.44#ibcon#about to read 3, iclass 35, count 0 2006.169.07:36:47.46#ibcon#read 3, iclass 35, count 0 2006.169.07:36:47.46#ibcon#about to read 4, iclass 35, count 0 2006.169.07:36:47.46#ibcon#read 4, iclass 35, count 0 2006.169.07:36:47.46#ibcon#about to read 5, iclass 35, count 0 2006.169.07:36:47.46#ibcon#read 5, iclass 35, count 0 2006.169.07:36:47.46#ibcon#about to read 6, iclass 35, count 0 2006.169.07:36:47.46#ibcon#read 6, iclass 35, count 0 2006.169.07:36:47.46#ibcon#end of sib2, iclass 35, count 0 2006.169.07:36:47.46#ibcon#*mode == 0, iclass 35, count 0 2006.169.07:36:47.46#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.169.07:36:47.46#ibcon#[25=USB\r\n] 2006.169.07:36:47.46#ibcon#*before write, iclass 35, count 0 2006.169.07:36:47.46#ibcon#enter sib2, iclass 35, count 0 2006.169.07:36:47.46#ibcon#flushed, iclass 35, count 0 2006.169.07:36:47.46#ibcon#about to write, iclass 35, count 0 2006.169.07:36:47.46#ibcon#wrote, iclass 35, count 0 2006.169.07:36:47.46#ibcon#about to read 3, iclass 35, count 0 2006.169.07:36:47.49#ibcon#read 3, iclass 35, count 0 2006.169.07:36:47.49#ibcon#about to read 4, iclass 35, count 0 2006.169.07:36:47.49#ibcon#read 4, iclass 35, count 0 2006.169.07:36:47.49#ibcon#about to read 5, iclass 35, count 0 2006.169.07:36:47.49#ibcon#read 5, iclass 35, count 0 2006.169.07:36:47.49#ibcon#about to read 6, iclass 35, count 0 2006.169.07:36:47.49#ibcon#read 6, iclass 35, count 0 2006.169.07:36:47.49#ibcon#end of sib2, iclass 35, count 0 2006.169.07:36:47.49#ibcon#*after write, iclass 35, count 0 2006.169.07:36:47.49#ibcon#*before return 0, iclass 35, count 0 2006.169.07:36:47.49#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:36:47.49#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:36:47.49#ibcon#about to clear, iclass 35 cls_cnt 0 2006.169.07:36:47.49#ibcon#cleared, iclass 35 cls_cnt 0 2006.169.07:36:47.49$vc4f8/vblo=1,632.99 2006.169.07:36:47.49#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.169.07:36:47.49#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.169.07:36:47.49#ibcon#ireg 17 cls_cnt 0 2006.169.07:36:47.49#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:36:47.49#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:36:47.49#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:36:47.49#ibcon#enter wrdev, iclass 37, count 0 2006.169.07:36:47.49#ibcon#first serial, iclass 37, count 0 2006.169.07:36:47.49#ibcon#enter sib2, iclass 37, count 0 2006.169.07:36:47.49#ibcon#flushed, iclass 37, count 0 2006.169.07:36:47.49#ibcon#about to write, iclass 37, count 0 2006.169.07:36:47.49#ibcon#wrote, iclass 37, count 0 2006.169.07:36:47.49#ibcon#about to read 3, iclass 37, count 0 2006.169.07:36:47.51#ibcon#read 3, iclass 37, count 0 2006.169.07:36:47.51#ibcon#about to read 4, iclass 37, count 0 2006.169.07:36:47.51#ibcon#read 4, iclass 37, count 0 2006.169.07:36:47.51#ibcon#about to read 5, iclass 37, count 0 2006.169.07:36:47.51#ibcon#read 5, iclass 37, count 0 2006.169.07:36:47.51#ibcon#about to read 6, iclass 37, count 0 2006.169.07:36:47.51#ibcon#read 6, iclass 37, count 0 2006.169.07:36:47.51#ibcon#end of sib2, iclass 37, count 0 2006.169.07:36:47.51#ibcon#*mode == 0, iclass 37, count 0 2006.169.07:36:47.51#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.169.07:36:47.51#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.07:36:47.51#ibcon#*before write, iclass 37, count 0 2006.169.07:36:47.51#ibcon#enter sib2, iclass 37, count 0 2006.169.07:36:47.51#ibcon#flushed, iclass 37, count 0 2006.169.07:36:47.51#ibcon#about to write, iclass 37, count 0 2006.169.07:36:47.51#ibcon#wrote, iclass 37, count 0 2006.169.07:36:47.51#ibcon#about to read 3, iclass 37, count 0 2006.169.07:36:47.55#ibcon#read 3, iclass 37, count 0 2006.169.07:36:47.55#ibcon#about to read 4, iclass 37, count 0 2006.169.07:36:47.55#ibcon#read 4, iclass 37, count 0 2006.169.07:36:47.55#ibcon#about to read 5, iclass 37, count 0 2006.169.07:36:47.55#ibcon#read 5, iclass 37, count 0 2006.169.07:36:47.55#ibcon#about to read 6, iclass 37, count 0 2006.169.07:36:47.55#ibcon#read 6, iclass 37, count 0 2006.169.07:36:47.55#ibcon#end of sib2, iclass 37, count 0 2006.169.07:36:47.55#ibcon#*after write, iclass 37, count 0 2006.169.07:36:47.55#ibcon#*before return 0, iclass 37, count 0 2006.169.07:36:47.55#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:36:47.55#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:36:47.55#ibcon#about to clear, iclass 37 cls_cnt 0 2006.169.07:36:47.55#ibcon#cleared, iclass 37 cls_cnt 0 2006.169.07:36:47.55$vc4f8/vb=1,4 2006.169.07:36:47.55#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.169.07:36:47.55#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.169.07:36:47.55#ibcon#ireg 11 cls_cnt 2 2006.169.07:36:47.55#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:36:47.55#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:36:47.55#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:36:47.55#ibcon#enter wrdev, iclass 39, count 2 2006.169.07:36:47.55#ibcon#first serial, iclass 39, count 2 2006.169.07:36:47.55#ibcon#enter sib2, iclass 39, count 2 2006.169.07:36:47.55#ibcon#flushed, iclass 39, count 2 2006.169.07:36:47.55#ibcon#about to write, iclass 39, count 2 2006.169.07:36:47.55#ibcon#wrote, iclass 39, count 2 2006.169.07:36:47.55#ibcon#about to read 3, iclass 39, count 2 2006.169.07:36:47.57#ibcon#read 3, iclass 39, count 2 2006.169.07:36:47.57#ibcon#about to read 4, iclass 39, count 2 2006.169.07:36:47.57#ibcon#read 4, iclass 39, count 2 2006.169.07:36:47.57#ibcon#about to read 5, iclass 39, count 2 2006.169.07:36:47.57#ibcon#read 5, iclass 39, count 2 2006.169.07:36:47.57#ibcon#about to read 6, iclass 39, count 2 2006.169.07:36:47.57#ibcon#read 6, iclass 39, count 2 2006.169.07:36:47.57#ibcon#end of sib2, iclass 39, count 2 2006.169.07:36:47.57#ibcon#*mode == 0, iclass 39, count 2 2006.169.07:36:47.57#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.169.07:36:47.57#ibcon#[27=AT01-04\r\n] 2006.169.07:36:47.57#ibcon#*before write, iclass 39, count 2 2006.169.07:36:47.57#ibcon#enter sib2, iclass 39, count 2 2006.169.07:36:47.57#ibcon#flushed, iclass 39, count 2 2006.169.07:36:47.57#ibcon#about to write, iclass 39, count 2 2006.169.07:36:47.57#ibcon#wrote, iclass 39, count 2 2006.169.07:36:47.57#ibcon#about to read 3, iclass 39, count 2 2006.169.07:36:47.60#ibcon#read 3, iclass 39, count 2 2006.169.07:36:47.60#ibcon#about to read 4, iclass 39, count 2 2006.169.07:36:47.60#ibcon#read 4, iclass 39, count 2 2006.169.07:36:47.60#ibcon#about to read 5, iclass 39, count 2 2006.169.07:36:47.60#ibcon#read 5, iclass 39, count 2 2006.169.07:36:47.60#ibcon#about to read 6, iclass 39, count 2 2006.169.07:36:47.60#ibcon#read 6, iclass 39, count 2 2006.169.07:36:47.60#ibcon#end of sib2, iclass 39, count 2 2006.169.07:36:47.60#ibcon#*after write, iclass 39, count 2 2006.169.07:36:47.60#ibcon#*before return 0, iclass 39, count 2 2006.169.07:36:47.60#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:36:47.60#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:36:47.60#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.169.07:36:47.60#ibcon#ireg 7 cls_cnt 0 2006.169.07:36:47.60#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:36:47.72#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:36:47.72#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:36:47.72#ibcon#enter wrdev, iclass 39, count 0 2006.169.07:36:47.72#ibcon#first serial, iclass 39, count 0 2006.169.07:36:47.72#ibcon#enter sib2, iclass 39, count 0 2006.169.07:36:47.72#ibcon#flushed, iclass 39, count 0 2006.169.07:36:47.72#ibcon#about to write, iclass 39, count 0 2006.169.07:36:47.72#ibcon#wrote, iclass 39, count 0 2006.169.07:36:47.72#ibcon#about to read 3, iclass 39, count 0 2006.169.07:36:47.74#ibcon#read 3, iclass 39, count 0 2006.169.07:36:47.74#ibcon#about to read 4, iclass 39, count 0 2006.169.07:36:47.74#ibcon#read 4, iclass 39, count 0 2006.169.07:36:47.74#ibcon#about to read 5, iclass 39, count 0 2006.169.07:36:47.74#ibcon#read 5, iclass 39, count 0 2006.169.07:36:47.74#ibcon#about to read 6, iclass 39, count 0 2006.169.07:36:47.74#ibcon#read 6, iclass 39, count 0 2006.169.07:36:47.74#ibcon#end of sib2, iclass 39, count 0 2006.169.07:36:47.74#ibcon#*mode == 0, iclass 39, count 0 2006.169.07:36:47.74#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.169.07:36:47.74#ibcon#[27=USB\r\n] 2006.169.07:36:47.74#ibcon#*before write, iclass 39, count 0 2006.169.07:36:47.74#ibcon#enter sib2, iclass 39, count 0 2006.169.07:36:47.74#ibcon#flushed, iclass 39, count 0 2006.169.07:36:47.74#ibcon#about to write, iclass 39, count 0 2006.169.07:36:47.74#ibcon#wrote, iclass 39, count 0 2006.169.07:36:47.74#ibcon#about to read 3, iclass 39, count 0 2006.169.07:36:47.77#ibcon#read 3, iclass 39, count 0 2006.169.07:36:47.77#ibcon#about to read 4, iclass 39, count 0 2006.169.07:36:47.77#ibcon#read 4, iclass 39, count 0 2006.169.07:36:47.77#ibcon#about to read 5, iclass 39, count 0 2006.169.07:36:47.77#ibcon#read 5, iclass 39, count 0 2006.169.07:36:47.77#ibcon#about to read 6, iclass 39, count 0 2006.169.07:36:47.77#ibcon#read 6, iclass 39, count 0 2006.169.07:36:47.77#ibcon#end of sib2, iclass 39, count 0 2006.169.07:36:47.77#ibcon#*after write, iclass 39, count 0 2006.169.07:36:47.77#ibcon#*before return 0, iclass 39, count 0 2006.169.07:36:47.77#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:36:47.77#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:36:47.77#ibcon#about to clear, iclass 39 cls_cnt 0 2006.169.07:36:47.77#ibcon#cleared, iclass 39 cls_cnt 0 2006.169.07:36:47.77$vc4f8/vblo=2,640.99 2006.169.07:36:47.77#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.169.07:36:47.77#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.169.07:36:47.77#ibcon#ireg 17 cls_cnt 0 2006.169.07:36:47.77#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:36:47.77#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:36:47.77#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:36:47.77#ibcon#enter wrdev, iclass 3, count 0 2006.169.07:36:47.77#ibcon#first serial, iclass 3, count 0 2006.169.07:36:47.77#ibcon#enter sib2, iclass 3, count 0 2006.169.07:36:47.77#ibcon#flushed, iclass 3, count 0 2006.169.07:36:47.77#ibcon#about to write, iclass 3, count 0 2006.169.07:36:47.77#ibcon#wrote, iclass 3, count 0 2006.169.07:36:47.77#ibcon#about to read 3, iclass 3, count 0 2006.169.07:36:47.79#ibcon#read 3, iclass 3, count 0 2006.169.07:36:47.79#ibcon#about to read 4, iclass 3, count 0 2006.169.07:36:47.79#ibcon#read 4, iclass 3, count 0 2006.169.07:36:47.79#ibcon#about to read 5, iclass 3, count 0 2006.169.07:36:47.79#ibcon#read 5, iclass 3, count 0 2006.169.07:36:47.79#ibcon#about to read 6, iclass 3, count 0 2006.169.07:36:47.79#ibcon#read 6, iclass 3, count 0 2006.169.07:36:47.79#ibcon#end of sib2, iclass 3, count 0 2006.169.07:36:47.79#ibcon#*mode == 0, iclass 3, count 0 2006.169.07:36:47.79#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.169.07:36:47.79#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.07:36:47.79#ibcon#*before write, iclass 3, count 0 2006.169.07:36:47.79#ibcon#enter sib2, iclass 3, count 0 2006.169.07:36:47.79#ibcon#flushed, iclass 3, count 0 2006.169.07:36:47.79#ibcon#about to write, iclass 3, count 0 2006.169.07:36:47.79#ibcon#wrote, iclass 3, count 0 2006.169.07:36:47.79#ibcon#about to read 3, iclass 3, count 0 2006.169.07:36:47.83#ibcon#read 3, iclass 3, count 0 2006.169.07:36:47.83#ibcon#about to read 4, iclass 3, count 0 2006.169.07:36:47.83#ibcon#read 4, iclass 3, count 0 2006.169.07:36:47.83#ibcon#about to read 5, iclass 3, count 0 2006.169.07:36:47.83#ibcon#read 5, iclass 3, count 0 2006.169.07:36:47.83#ibcon#about to read 6, iclass 3, count 0 2006.169.07:36:47.83#ibcon#read 6, iclass 3, count 0 2006.169.07:36:47.83#ibcon#end of sib2, iclass 3, count 0 2006.169.07:36:47.83#ibcon#*after write, iclass 3, count 0 2006.169.07:36:47.83#ibcon#*before return 0, iclass 3, count 0 2006.169.07:36:47.83#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:36:47.83#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:36:47.83#ibcon#about to clear, iclass 3 cls_cnt 0 2006.169.07:36:47.83#ibcon#cleared, iclass 3 cls_cnt 0 2006.169.07:36:47.83$vc4f8/vb=2,4 2006.169.07:36:47.83#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.169.07:36:47.83#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.169.07:36:47.83#ibcon#ireg 11 cls_cnt 2 2006.169.07:36:47.83#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:36:47.89#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:36:47.89#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:36:47.89#ibcon#enter wrdev, iclass 5, count 2 2006.169.07:36:47.89#ibcon#first serial, iclass 5, count 2 2006.169.07:36:47.89#ibcon#enter sib2, iclass 5, count 2 2006.169.07:36:47.89#ibcon#flushed, iclass 5, count 2 2006.169.07:36:47.89#ibcon#about to write, iclass 5, count 2 2006.169.07:36:47.89#ibcon#wrote, iclass 5, count 2 2006.169.07:36:47.89#ibcon#about to read 3, iclass 5, count 2 2006.169.07:36:47.91#ibcon#read 3, iclass 5, count 2 2006.169.07:36:47.91#ibcon#about to read 4, iclass 5, count 2 2006.169.07:36:47.91#ibcon#read 4, iclass 5, count 2 2006.169.07:36:47.91#ibcon#about to read 5, iclass 5, count 2 2006.169.07:36:47.91#ibcon#read 5, iclass 5, count 2 2006.169.07:36:47.91#ibcon#about to read 6, iclass 5, count 2 2006.169.07:36:47.91#ibcon#read 6, iclass 5, count 2 2006.169.07:36:47.91#ibcon#end of sib2, iclass 5, count 2 2006.169.07:36:47.91#ibcon#*mode == 0, iclass 5, count 2 2006.169.07:36:47.91#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.169.07:36:47.91#ibcon#[27=AT02-04\r\n] 2006.169.07:36:47.91#ibcon#*before write, iclass 5, count 2 2006.169.07:36:47.91#ibcon#enter sib2, iclass 5, count 2 2006.169.07:36:47.91#ibcon#flushed, iclass 5, count 2 2006.169.07:36:47.91#ibcon#about to write, iclass 5, count 2 2006.169.07:36:47.91#ibcon#wrote, iclass 5, count 2 2006.169.07:36:47.91#ibcon#about to read 3, iclass 5, count 2 2006.169.07:36:47.94#ibcon#read 3, iclass 5, count 2 2006.169.07:36:47.94#ibcon#about to read 4, iclass 5, count 2 2006.169.07:36:47.94#ibcon#read 4, iclass 5, count 2 2006.169.07:36:47.94#ibcon#about to read 5, iclass 5, count 2 2006.169.07:36:47.94#ibcon#read 5, iclass 5, count 2 2006.169.07:36:47.94#ibcon#about to read 6, iclass 5, count 2 2006.169.07:36:47.94#ibcon#read 6, iclass 5, count 2 2006.169.07:36:47.94#ibcon#end of sib2, iclass 5, count 2 2006.169.07:36:47.94#ibcon#*after write, iclass 5, count 2 2006.169.07:36:47.94#ibcon#*before return 0, iclass 5, count 2 2006.169.07:36:47.94#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:36:47.94#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:36:47.94#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.169.07:36:47.94#ibcon#ireg 7 cls_cnt 0 2006.169.07:36:47.94#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:36:48.06#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:36:48.06#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:36:48.06#ibcon#enter wrdev, iclass 5, count 0 2006.169.07:36:48.06#ibcon#first serial, iclass 5, count 0 2006.169.07:36:48.06#ibcon#enter sib2, iclass 5, count 0 2006.169.07:36:48.06#ibcon#flushed, iclass 5, count 0 2006.169.07:36:48.06#ibcon#about to write, iclass 5, count 0 2006.169.07:36:48.06#ibcon#wrote, iclass 5, count 0 2006.169.07:36:48.06#ibcon#about to read 3, iclass 5, count 0 2006.169.07:36:48.08#ibcon#read 3, iclass 5, count 0 2006.169.07:36:48.08#ibcon#about to read 4, iclass 5, count 0 2006.169.07:36:48.08#ibcon#read 4, iclass 5, count 0 2006.169.07:36:48.08#ibcon#about to read 5, iclass 5, count 0 2006.169.07:36:48.08#ibcon#read 5, iclass 5, count 0 2006.169.07:36:48.08#ibcon#about to read 6, iclass 5, count 0 2006.169.07:36:48.08#ibcon#read 6, iclass 5, count 0 2006.169.07:36:48.08#ibcon#end of sib2, iclass 5, count 0 2006.169.07:36:48.08#ibcon#*mode == 0, iclass 5, count 0 2006.169.07:36:48.08#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.169.07:36:48.08#ibcon#[27=USB\r\n] 2006.169.07:36:48.08#ibcon#*before write, iclass 5, count 0 2006.169.07:36:48.08#ibcon#enter sib2, iclass 5, count 0 2006.169.07:36:48.08#ibcon#flushed, iclass 5, count 0 2006.169.07:36:48.08#ibcon#about to write, iclass 5, count 0 2006.169.07:36:48.08#ibcon#wrote, iclass 5, count 0 2006.169.07:36:48.08#ibcon#about to read 3, iclass 5, count 0 2006.169.07:36:48.11#ibcon#read 3, iclass 5, count 0 2006.169.07:36:48.11#ibcon#about to read 4, iclass 5, count 0 2006.169.07:36:48.11#ibcon#read 4, iclass 5, count 0 2006.169.07:36:48.11#ibcon#about to read 5, iclass 5, count 0 2006.169.07:36:48.11#ibcon#read 5, iclass 5, count 0 2006.169.07:36:48.11#ibcon#about to read 6, iclass 5, count 0 2006.169.07:36:48.11#ibcon#read 6, iclass 5, count 0 2006.169.07:36:48.11#ibcon#end of sib2, iclass 5, count 0 2006.169.07:36:48.11#ibcon#*after write, iclass 5, count 0 2006.169.07:36:48.11#ibcon#*before return 0, iclass 5, count 0 2006.169.07:36:48.11#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:36:48.11#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:36:48.11#ibcon#about to clear, iclass 5 cls_cnt 0 2006.169.07:36:48.11#ibcon#cleared, iclass 5 cls_cnt 0 2006.169.07:36:48.11$vc4f8/vblo=3,656.99 2006.169.07:36:48.11#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.169.07:36:48.11#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.169.07:36:48.11#ibcon#ireg 17 cls_cnt 0 2006.169.07:36:48.11#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:36:48.11#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:36:48.11#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:36:48.11#ibcon#enter wrdev, iclass 7, count 0 2006.169.07:36:48.11#ibcon#first serial, iclass 7, count 0 2006.169.07:36:48.11#ibcon#enter sib2, iclass 7, count 0 2006.169.07:36:48.11#ibcon#flushed, iclass 7, count 0 2006.169.07:36:48.11#ibcon#about to write, iclass 7, count 0 2006.169.07:36:48.11#ibcon#wrote, iclass 7, count 0 2006.169.07:36:48.11#ibcon#about to read 3, iclass 7, count 0 2006.169.07:36:48.13#ibcon#read 3, iclass 7, count 0 2006.169.07:36:48.13#ibcon#about to read 4, iclass 7, count 0 2006.169.07:36:48.13#ibcon#read 4, iclass 7, count 0 2006.169.07:36:48.13#ibcon#about to read 5, iclass 7, count 0 2006.169.07:36:48.13#ibcon#read 5, iclass 7, count 0 2006.169.07:36:48.13#ibcon#about to read 6, iclass 7, count 0 2006.169.07:36:48.13#ibcon#read 6, iclass 7, count 0 2006.169.07:36:48.13#ibcon#end of sib2, iclass 7, count 0 2006.169.07:36:48.13#ibcon#*mode == 0, iclass 7, count 0 2006.169.07:36:48.13#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.169.07:36:48.13#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.07:36:48.13#ibcon#*before write, iclass 7, count 0 2006.169.07:36:48.13#ibcon#enter sib2, iclass 7, count 0 2006.169.07:36:48.13#ibcon#flushed, iclass 7, count 0 2006.169.07:36:48.13#ibcon#about to write, iclass 7, count 0 2006.169.07:36:48.13#ibcon#wrote, iclass 7, count 0 2006.169.07:36:48.13#ibcon#about to read 3, iclass 7, count 0 2006.169.07:36:48.14#flagr#flagr/antenna,acquired 2006.169.07:36:48.17#ibcon#read 3, iclass 7, count 0 2006.169.07:36:48.17#ibcon#about to read 4, iclass 7, count 0 2006.169.07:36:48.17#ibcon#read 4, iclass 7, count 0 2006.169.07:36:48.17#ibcon#about to read 5, iclass 7, count 0 2006.169.07:36:48.17#ibcon#read 5, iclass 7, count 0 2006.169.07:36:48.17#ibcon#about to read 6, iclass 7, count 0 2006.169.07:36:48.17#ibcon#read 6, iclass 7, count 0 2006.169.07:36:48.17#ibcon#end of sib2, iclass 7, count 0 2006.169.07:36:48.17#ibcon#*after write, iclass 7, count 0 2006.169.07:36:48.17#ibcon#*before return 0, iclass 7, count 0 2006.169.07:36:48.17#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:36:48.17#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:36:48.17#ibcon#about to clear, iclass 7 cls_cnt 0 2006.169.07:36:48.17#ibcon#cleared, iclass 7 cls_cnt 0 2006.169.07:36:48.17$vc4f8/vb=3,4 2006.169.07:36:48.17#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.169.07:36:48.17#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.169.07:36:48.17#ibcon#ireg 11 cls_cnt 2 2006.169.07:36:48.17#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:36:48.23#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:36:48.23#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:36:48.23#ibcon#enter wrdev, iclass 11, count 2 2006.169.07:36:48.23#ibcon#first serial, iclass 11, count 2 2006.169.07:36:48.23#ibcon#enter sib2, iclass 11, count 2 2006.169.07:36:48.23#ibcon#flushed, iclass 11, count 2 2006.169.07:36:48.23#ibcon#about to write, iclass 11, count 2 2006.169.07:36:48.23#ibcon#wrote, iclass 11, count 2 2006.169.07:36:48.23#ibcon#about to read 3, iclass 11, count 2 2006.169.07:36:48.25#ibcon#read 3, iclass 11, count 2 2006.169.07:36:48.25#ibcon#about to read 4, iclass 11, count 2 2006.169.07:36:48.25#ibcon#read 4, iclass 11, count 2 2006.169.07:36:48.25#ibcon#about to read 5, iclass 11, count 2 2006.169.07:36:48.25#ibcon#read 5, iclass 11, count 2 2006.169.07:36:48.25#ibcon#about to read 6, iclass 11, count 2 2006.169.07:36:48.25#ibcon#read 6, iclass 11, count 2 2006.169.07:36:48.25#ibcon#end of sib2, iclass 11, count 2 2006.169.07:36:48.25#ibcon#*mode == 0, iclass 11, count 2 2006.169.07:36:48.25#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.169.07:36:48.25#ibcon#[27=AT03-04\r\n] 2006.169.07:36:48.25#ibcon#*before write, iclass 11, count 2 2006.169.07:36:48.25#ibcon#enter sib2, iclass 11, count 2 2006.169.07:36:48.25#ibcon#flushed, iclass 11, count 2 2006.169.07:36:48.25#ibcon#about to write, iclass 11, count 2 2006.169.07:36:48.25#ibcon#wrote, iclass 11, count 2 2006.169.07:36:48.25#ibcon#about to read 3, iclass 11, count 2 2006.169.07:36:48.28#ibcon#read 3, iclass 11, count 2 2006.169.07:36:48.28#ibcon#about to read 4, iclass 11, count 2 2006.169.07:36:48.28#ibcon#read 4, iclass 11, count 2 2006.169.07:36:48.28#ibcon#about to read 5, iclass 11, count 2 2006.169.07:36:48.28#ibcon#read 5, iclass 11, count 2 2006.169.07:36:48.28#ibcon#about to read 6, iclass 11, count 2 2006.169.07:36:48.28#ibcon#read 6, iclass 11, count 2 2006.169.07:36:48.28#ibcon#end of sib2, iclass 11, count 2 2006.169.07:36:48.28#ibcon#*after write, iclass 11, count 2 2006.169.07:36:48.28#ibcon#*before return 0, iclass 11, count 2 2006.169.07:36:48.28#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:36:48.28#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:36:48.28#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.169.07:36:48.28#ibcon#ireg 7 cls_cnt 0 2006.169.07:36:48.28#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:36:48.40#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:36:48.40#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:36:48.40#ibcon#enter wrdev, iclass 11, count 0 2006.169.07:36:48.40#ibcon#first serial, iclass 11, count 0 2006.169.07:36:48.40#ibcon#enter sib2, iclass 11, count 0 2006.169.07:36:48.40#ibcon#flushed, iclass 11, count 0 2006.169.07:36:48.40#ibcon#about to write, iclass 11, count 0 2006.169.07:36:48.40#ibcon#wrote, iclass 11, count 0 2006.169.07:36:48.40#ibcon#about to read 3, iclass 11, count 0 2006.169.07:36:48.42#ibcon#read 3, iclass 11, count 0 2006.169.07:36:48.42#ibcon#about to read 4, iclass 11, count 0 2006.169.07:36:48.42#ibcon#read 4, iclass 11, count 0 2006.169.07:36:48.42#ibcon#about to read 5, iclass 11, count 0 2006.169.07:36:48.42#ibcon#read 5, iclass 11, count 0 2006.169.07:36:48.42#ibcon#about to read 6, iclass 11, count 0 2006.169.07:36:48.42#ibcon#read 6, iclass 11, count 0 2006.169.07:36:48.42#ibcon#end of sib2, iclass 11, count 0 2006.169.07:36:48.42#ibcon#*mode == 0, iclass 11, count 0 2006.169.07:36:48.42#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.169.07:36:48.42#ibcon#[27=USB\r\n] 2006.169.07:36:48.42#ibcon#*before write, iclass 11, count 0 2006.169.07:36:48.42#ibcon#enter sib2, iclass 11, count 0 2006.169.07:36:48.42#ibcon#flushed, iclass 11, count 0 2006.169.07:36:48.42#ibcon#about to write, iclass 11, count 0 2006.169.07:36:48.42#ibcon#wrote, iclass 11, count 0 2006.169.07:36:48.42#ibcon#about to read 3, iclass 11, count 0 2006.169.07:36:48.45#ibcon#read 3, iclass 11, count 0 2006.169.07:36:48.45#ibcon#about to read 4, iclass 11, count 0 2006.169.07:36:48.45#ibcon#read 4, iclass 11, count 0 2006.169.07:36:48.45#ibcon#about to read 5, iclass 11, count 0 2006.169.07:36:48.45#ibcon#read 5, iclass 11, count 0 2006.169.07:36:48.45#ibcon#about to read 6, iclass 11, count 0 2006.169.07:36:48.45#ibcon#read 6, iclass 11, count 0 2006.169.07:36:48.45#ibcon#end of sib2, iclass 11, count 0 2006.169.07:36:48.45#ibcon#*after write, iclass 11, count 0 2006.169.07:36:48.45#ibcon#*before return 0, iclass 11, count 0 2006.169.07:36:48.45#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:36:48.45#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:36:48.45#ibcon#about to clear, iclass 11 cls_cnt 0 2006.169.07:36:48.45#ibcon#cleared, iclass 11 cls_cnt 0 2006.169.07:36:48.45$vc4f8/vblo=4,712.99 2006.169.07:36:48.45#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.169.07:36:48.45#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.169.07:36:48.45#ibcon#ireg 17 cls_cnt 0 2006.169.07:36:48.45#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:36:48.45#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:36:48.45#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:36:48.45#ibcon#enter wrdev, iclass 13, count 0 2006.169.07:36:48.45#ibcon#first serial, iclass 13, count 0 2006.169.07:36:48.45#ibcon#enter sib2, iclass 13, count 0 2006.169.07:36:48.45#ibcon#flushed, iclass 13, count 0 2006.169.07:36:48.45#ibcon#about to write, iclass 13, count 0 2006.169.07:36:48.45#ibcon#wrote, iclass 13, count 0 2006.169.07:36:48.45#ibcon#about to read 3, iclass 13, count 0 2006.169.07:36:48.47#ibcon#read 3, iclass 13, count 0 2006.169.07:36:48.47#ibcon#about to read 4, iclass 13, count 0 2006.169.07:36:48.47#ibcon#read 4, iclass 13, count 0 2006.169.07:36:48.47#ibcon#about to read 5, iclass 13, count 0 2006.169.07:36:48.47#ibcon#read 5, iclass 13, count 0 2006.169.07:36:48.47#ibcon#about to read 6, iclass 13, count 0 2006.169.07:36:48.47#ibcon#read 6, iclass 13, count 0 2006.169.07:36:48.47#ibcon#end of sib2, iclass 13, count 0 2006.169.07:36:48.47#ibcon#*mode == 0, iclass 13, count 0 2006.169.07:36:48.47#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.07:36:48.47#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.07:36:48.47#ibcon#*before write, iclass 13, count 0 2006.169.07:36:48.47#ibcon#enter sib2, iclass 13, count 0 2006.169.07:36:48.47#ibcon#flushed, iclass 13, count 0 2006.169.07:36:48.47#ibcon#about to write, iclass 13, count 0 2006.169.07:36:48.47#ibcon#wrote, iclass 13, count 0 2006.169.07:36:48.47#ibcon#about to read 3, iclass 13, count 0 2006.169.07:36:48.51#ibcon#read 3, iclass 13, count 0 2006.169.07:36:48.51#ibcon#about to read 4, iclass 13, count 0 2006.169.07:36:48.51#ibcon#read 4, iclass 13, count 0 2006.169.07:36:48.51#ibcon#about to read 5, iclass 13, count 0 2006.169.07:36:48.51#ibcon#read 5, iclass 13, count 0 2006.169.07:36:48.51#ibcon#about to read 6, iclass 13, count 0 2006.169.07:36:48.51#ibcon#read 6, iclass 13, count 0 2006.169.07:36:48.51#ibcon#end of sib2, iclass 13, count 0 2006.169.07:36:48.51#ibcon#*after write, iclass 13, count 0 2006.169.07:36:48.51#ibcon#*before return 0, iclass 13, count 0 2006.169.07:36:48.51#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:36:48.51#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:36:48.51#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.07:36:48.51#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.07:36:48.51$vc4f8/vb=4,4 2006.169.07:36:48.51#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.169.07:36:48.51#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.169.07:36:48.51#ibcon#ireg 11 cls_cnt 2 2006.169.07:36:48.51#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:36:48.57#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:36:48.57#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:36:48.57#ibcon#enter wrdev, iclass 15, count 2 2006.169.07:36:48.57#ibcon#first serial, iclass 15, count 2 2006.169.07:36:48.57#ibcon#enter sib2, iclass 15, count 2 2006.169.07:36:48.57#ibcon#flushed, iclass 15, count 2 2006.169.07:36:48.57#ibcon#about to write, iclass 15, count 2 2006.169.07:36:48.57#ibcon#wrote, iclass 15, count 2 2006.169.07:36:48.57#ibcon#about to read 3, iclass 15, count 2 2006.169.07:36:48.59#ibcon#read 3, iclass 15, count 2 2006.169.07:36:48.59#ibcon#about to read 4, iclass 15, count 2 2006.169.07:36:48.59#ibcon#read 4, iclass 15, count 2 2006.169.07:36:48.59#ibcon#about to read 5, iclass 15, count 2 2006.169.07:36:48.59#ibcon#read 5, iclass 15, count 2 2006.169.07:36:48.59#ibcon#about to read 6, iclass 15, count 2 2006.169.07:36:48.59#ibcon#read 6, iclass 15, count 2 2006.169.07:36:48.59#ibcon#end of sib2, iclass 15, count 2 2006.169.07:36:48.59#ibcon#*mode == 0, iclass 15, count 2 2006.169.07:36:48.59#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.169.07:36:48.59#ibcon#[27=AT04-04\r\n] 2006.169.07:36:48.59#ibcon#*before write, iclass 15, count 2 2006.169.07:36:48.59#ibcon#enter sib2, iclass 15, count 2 2006.169.07:36:48.59#ibcon#flushed, iclass 15, count 2 2006.169.07:36:48.59#ibcon#about to write, iclass 15, count 2 2006.169.07:36:48.59#ibcon#wrote, iclass 15, count 2 2006.169.07:36:48.59#ibcon#about to read 3, iclass 15, count 2 2006.169.07:36:48.62#ibcon#read 3, iclass 15, count 2 2006.169.07:36:48.62#ibcon#about to read 4, iclass 15, count 2 2006.169.07:36:48.62#ibcon#read 4, iclass 15, count 2 2006.169.07:36:48.62#ibcon#about to read 5, iclass 15, count 2 2006.169.07:36:48.62#ibcon#read 5, iclass 15, count 2 2006.169.07:36:48.62#ibcon#about to read 6, iclass 15, count 2 2006.169.07:36:48.62#ibcon#read 6, iclass 15, count 2 2006.169.07:36:48.62#ibcon#end of sib2, iclass 15, count 2 2006.169.07:36:48.62#ibcon#*after write, iclass 15, count 2 2006.169.07:36:48.62#ibcon#*before return 0, iclass 15, count 2 2006.169.07:36:48.62#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:36:48.62#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:36:48.62#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.169.07:36:48.62#ibcon#ireg 7 cls_cnt 0 2006.169.07:36:48.62#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:36:48.74#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:36:48.74#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:36:48.74#ibcon#enter wrdev, iclass 15, count 0 2006.169.07:36:48.74#ibcon#first serial, iclass 15, count 0 2006.169.07:36:48.74#ibcon#enter sib2, iclass 15, count 0 2006.169.07:36:48.74#ibcon#flushed, iclass 15, count 0 2006.169.07:36:48.74#ibcon#about to write, iclass 15, count 0 2006.169.07:36:48.74#ibcon#wrote, iclass 15, count 0 2006.169.07:36:48.74#ibcon#about to read 3, iclass 15, count 0 2006.169.07:36:48.76#ibcon#read 3, iclass 15, count 0 2006.169.07:36:48.76#ibcon#about to read 4, iclass 15, count 0 2006.169.07:36:48.76#ibcon#read 4, iclass 15, count 0 2006.169.07:36:48.76#ibcon#about to read 5, iclass 15, count 0 2006.169.07:36:48.76#ibcon#read 5, iclass 15, count 0 2006.169.07:36:48.76#ibcon#about to read 6, iclass 15, count 0 2006.169.07:36:48.76#ibcon#read 6, iclass 15, count 0 2006.169.07:36:48.76#ibcon#end of sib2, iclass 15, count 0 2006.169.07:36:48.76#ibcon#*mode == 0, iclass 15, count 0 2006.169.07:36:48.76#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.169.07:36:48.76#ibcon#[27=USB\r\n] 2006.169.07:36:48.76#ibcon#*before write, iclass 15, count 0 2006.169.07:36:48.76#ibcon#enter sib2, iclass 15, count 0 2006.169.07:36:48.76#ibcon#flushed, iclass 15, count 0 2006.169.07:36:48.76#ibcon#about to write, iclass 15, count 0 2006.169.07:36:48.76#ibcon#wrote, iclass 15, count 0 2006.169.07:36:48.76#ibcon#about to read 3, iclass 15, count 0 2006.169.07:36:48.79#ibcon#read 3, iclass 15, count 0 2006.169.07:36:48.79#ibcon#about to read 4, iclass 15, count 0 2006.169.07:36:48.79#ibcon#read 4, iclass 15, count 0 2006.169.07:36:48.79#ibcon#about to read 5, iclass 15, count 0 2006.169.07:36:48.79#ibcon#read 5, iclass 15, count 0 2006.169.07:36:48.79#ibcon#about to read 6, iclass 15, count 0 2006.169.07:36:48.79#ibcon#read 6, iclass 15, count 0 2006.169.07:36:48.79#ibcon#end of sib2, iclass 15, count 0 2006.169.07:36:48.79#ibcon#*after write, iclass 15, count 0 2006.169.07:36:48.79#ibcon#*before return 0, iclass 15, count 0 2006.169.07:36:48.79#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:36:48.79#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:36:48.79#ibcon#about to clear, iclass 15 cls_cnt 0 2006.169.07:36:48.79#ibcon#cleared, iclass 15 cls_cnt 0 2006.169.07:36:48.79$vc4f8/vblo=5,744.99 2006.169.07:36:48.79#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.169.07:36:48.79#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.169.07:36:48.79#ibcon#ireg 17 cls_cnt 0 2006.169.07:36:48.79#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:36:48.79#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:36:48.79#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:36:48.79#ibcon#enter wrdev, iclass 17, count 0 2006.169.07:36:48.79#ibcon#first serial, iclass 17, count 0 2006.169.07:36:48.79#ibcon#enter sib2, iclass 17, count 0 2006.169.07:36:48.79#ibcon#flushed, iclass 17, count 0 2006.169.07:36:48.79#ibcon#about to write, iclass 17, count 0 2006.169.07:36:48.79#ibcon#wrote, iclass 17, count 0 2006.169.07:36:48.79#ibcon#about to read 3, iclass 17, count 0 2006.169.07:36:48.81#ibcon#read 3, iclass 17, count 0 2006.169.07:36:48.81#ibcon#about to read 4, iclass 17, count 0 2006.169.07:36:48.81#ibcon#read 4, iclass 17, count 0 2006.169.07:36:48.81#ibcon#about to read 5, iclass 17, count 0 2006.169.07:36:48.81#ibcon#read 5, iclass 17, count 0 2006.169.07:36:48.81#ibcon#about to read 6, iclass 17, count 0 2006.169.07:36:48.81#ibcon#read 6, iclass 17, count 0 2006.169.07:36:48.81#ibcon#end of sib2, iclass 17, count 0 2006.169.07:36:48.81#ibcon#*mode == 0, iclass 17, count 0 2006.169.07:36:48.81#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.169.07:36:48.81#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.07:36:48.81#ibcon#*before write, iclass 17, count 0 2006.169.07:36:48.81#ibcon#enter sib2, iclass 17, count 0 2006.169.07:36:48.81#ibcon#flushed, iclass 17, count 0 2006.169.07:36:48.81#ibcon#about to write, iclass 17, count 0 2006.169.07:36:48.81#ibcon#wrote, iclass 17, count 0 2006.169.07:36:48.81#ibcon#about to read 3, iclass 17, count 0 2006.169.07:36:48.85#ibcon#read 3, iclass 17, count 0 2006.169.07:36:48.85#ibcon#about to read 4, iclass 17, count 0 2006.169.07:36:48.85#ibcon#read 4, iclass 17, count 0 2006.169.07:36:48.85#ibcon#about to read 5, iclass 17, count 0 2006.169.07:36:48.85#ibcon#read 5, iclass 17, count 0 2006.169.07:36:48.85#ibcon#about to read 6, iclass 17, count 0 2006.169.07:36:48.85#ibcon#read 6, iclass 17, count 0 2006.169.07:36:48.85#ibcon#end of sib2, iclass 17, count 0 2006.169.07:36:48.85#ibcon#*after write, iclass 17, count 0 2006.169.07:36:48.85#ibcon#*before return 0, iclass 17, count 0 2006.169.07:36:48.85#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:36:48.85#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:36:48.85#ibcon#about to clear, iclass 17 cls_cnt 0 2006.169.07:36:48.85#ibcon#cleared, iclass 17 cls_cnt 0 2006.169.07:36:48.85$vc4f8/vb=5,4 2006.169.07:36:48.85#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.169.07:36:48.85#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.169.07:36:48.85#ibcon#ireg 11 cls_cnt 2 2006.169.07:36:48.85#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:36:48.91#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:36:48.91#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:36:48.91#ibcon#enter wrdev, iclass 19, count 2 2006.169.07:36:48.91#ibcon#first serial, iclass 19, count 2 2006.169.07:36:48.91#ibcon#enter sib2, iclass 19, count 2 2006.169.07:36:48.91#ibcon#flushed, iclass 19, count 2 2006.169.07:36:48.91#ibcon#about to write, iclass 19, count 2 2006.169.07:36:48.91#ibcon#wrote, iclass 19, count 2 2006.169.07:36:48.91#ibcon#about to read 3, iclass 19, count 2 2006.169.07:36:48.93#ibcon#read 3, iclass 19, count 2 2006.169.07:36:48.93#ibcon#about to read 4, iclass 19, count 2 2006.169.07:36:48.93#ibcon#read 4, iclass 19, count 2 2006.169.07:36:48.93#ibcon#about to read 5, iclass 19, count 2 2006.169.07:36:48.93#ibcon#read 5, iclass 19, count 2 2006.169.07:36:48.93#ibcon#about to read 6, iclass 19, count 2 2006.169.07:36:48.93#ibcon#read 6, iclass 19, count 2 2006.169.07:36:48.93#ibcon#end of sib2, iclass 19, count 2 2006.169.07:36:48.93#ibcon#*mode == 0, iclass 19, count 2 2006.169.07:36:48.93#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.169.07:36:48.93#ibcon#[27=AT05-04\r\n] 2006.169.07:36:48.93#ibcon#*before write, iclass 19, count 2 2006.169.07:36:48.93#ibcon#enter sib2, iclass 19, count 2 2006.169.07:36:48.93#ibcon#flushed, iclass 19, count 2 2006.169.07:36:48.93#ibcon#about to write, iclass 19, count 2 2006.169.07:36:48.93#ibcon#wrote, iclass 19, count 2 2006.169.07:36:48.93#ibcon#about to read 3, iclass 19, count 2 2006.169.07:36:48.96#ibcon#read 3, iclass 19, count 2 2006.169.07:36:48.96#ibcon#about to read 4, iclass 19, count 2 2006.169.07:36:48.96#ibcon#read 4, iclass 19, count 2 2006.169.07:36:48.96#ibcon#about to read 5, iclass 19, count 2 2006.169.07:36:48.96#ibcon#read 5, iclass 19, count 2 2006.169.07:36:48.96#ibcon#about to read 6, iclass 19, count 2 2006.169.07:36:48.96#ibcon#read 6, iclass 19, count 2 2006.169.07:36:48.96#ibcon#end of sib2, iclass 19, count 2 2006.169.07:36:48.96#ibcon#*after write, iclass 19, count 2 2006.169.07:36:48.96#ibcon#*before return 0, iclass 19, count 2 2006.169.07:36:48.96#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:36:48.96#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:36:48.96#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.169.07:36:48.96#ibcon#ireg 7 cls_cnt 0 2006.169.07:36:48.96#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:36:49.08#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:36:49.08#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:36:49.08#ibcon#enter wrdev, iclass 19, count 0 2006.169.07:36:49.08#ibcon#first serial, iclass 19, count 0 2006.169.07:36:49.08#ibcon#enter sib2, iclass 19, count 0 2006.169.07:36:49.08#ibcon#flushed, iclass 19, count 0 2006.169.07:36:49.08#ibcon#about to write, iclass 19, count 0 2006.169.07:36:49.08#ibcon#wrote, iclass 19, count 0 2006.169.07:36:49.08#ibcon#about to read 3, iclass 19, count 0 2006.169.07:36:49.10#ibcon#read 3, iclass 19, count 0 2006.169.07:36:49.10#ibcon#about to read 4, iclass 19, count 0 2006.169.07:36:49.10#ibcon#read 4, iclass 19, count 0 2006.169.07:36:49.10#ibcon#about to read 5, iclass 19, count 0 2006.169.07:36:49.10#ibcon#read 5, iclass 19, count 0 2006.169.07:36:49.10#ibcon#about to read 6, iclass 19, count 0 2006.169.07:36:49.10#ibcon#read 6, iclass 19, count 0 2006.169.07:36:49.10#ibcon#end of sib2, iclass 19, count 0 2006.169.07:36:49.10#ibcon#*mode == 0, iclass 19, count 0 2006.169.07:36:49.10#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.169.07:36:49.10#ibcon#[27=USB\r\n] 2006.169.07:36:49.10#ibcon#*before write, iclass 19, count 0 2006.169.07:36:49.10#ibcon#enter sib2, iclass 19, count 0 2006.169.07:36:49.10#ibcon#flushed, iclass 19, count 0 2006.169.07:36:49.10#ibcon#about to write, iclass 19, count 0 2006.169.07:36:49.10#ibcon#wrote, iclass 19, count 0 2006.169.07:36:49.10#ibcon#about to read 3, iclass 19, count 0 2006.169.07:36:49.13#ibcon#read 3, iclass 19, count 0 2006.169.07:36:49.13#ibcon#about to read 4, iclass 19, count 0 2006.169.07:36:49.13#ibcon#read 4, iclass 19, count 0 2006.169.07:36:49.13#ibcon#about to read 5, iclass 19, count 0 2006.169.07:36:49.13#ibcon#read 5, iclass 19, count 0 2006.169.07:36:49.13#ibcon#about to read 6, iclass 19, count 0 2006.169.07:36:49.13#ibcon#read 6, iclass 19, count 0 2006.169.07:36:49.13#ibcon#end of sib2, iclass 19, count 0 2006.169.07:36:49.13#ibcon#*after write, iclass 19, count 0 2006.169.07:36:49.13#ibcon#*before return 0, iclass 19, count 0 2006.169.07:36:49.13#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:36:49.13#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:36:49.13#ibcon#about to clear, iclass 19 cls_cnt 0 2006.169.07:36:49.13#ibcon#cleared, iclass 19 cls_cnt 0 2006.169.07:36:49.13$vc4f8/vblo=6,752.99 2006.169.07:36:49.13#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.169.07:36:49.13#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.169.07:36:49.13#ibcon#ireg 17 cls_cnt 0 2006.169.07:36:49.13#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:36:49.13#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:36:49.13#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:36:49.13#ibcon#enter wrdev, iclass 21, count 0 2006.169.07:36:49.13#ibcon#first serial, iclass 21, count 0 2006.169.07:36:49.13#ibcon#enter sib2, iclass 21, count 0 2006.169.07:36:49.13#ibcon#flushed, iclass 21, count 0 2006.169.07:36:49.13#ibcon#about to write, iclass 21, count 0 2006.169.07:36:49.13#ibcon#wrote, iclass 21, count 0 2006.169.07:36:49.13#ibcon#about to read 3, iclass 21, count 0 2006.169.07:36:49.15#ibcon#read 3, iclass 21, count 0 2006.169.07:36:49.15#ibcon#about to read 4, iclass 21, count 0 2006.169.07:36:49.15#ibcon#read 4, iclass 21, count 0 2006.169.07:36:49.15#ibcon#about to read 5, iclass 21, count 0 2006.169.07:36:49.15#ibcon#read 5, iclass 21, count 0 2006.169.07:36:49.15#ibcon#about to read 6, iclass 21, count 0 2006.169.07:36:49.15#ibcon#read 6, iclass 21, count 0 2006.169.07:36:49.15#ibcon#end of sib2, iclass 21, count 0 2006.169.07:36:49.15#ibcon#*mode == 0, iclass 21, count 0 2006.169.07:36:49.15#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.169.07:36:49.15#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.07:36:49.15#ibcon#*before write, iclass 21, count 0 2006.169.07:36:49.15#ibcon#enter sib2, iclass 21, count 0 2006.169.07:36:49.15#ibcon#flushed, iclass 21, count 0 2006.169.07:36:49.15#ibcon#about to write, iclass 21, count 0 2006.169.07:36:49.15#ibcon#wrote, iclass 21, count 0 2006.169.07:36:49.15#ibcon#about to read 3, iclass 21, count 0 2006.169.07:36:49.19#ibcon#read 3, iclass 21, count 0 2006.169.07:36:49.19#ibcon#about to read 4, iclass 21, count 0 2006.169.07:36:49.19#ibcon#read 4, iclass 21, count 0 2006.169.07:36:49.19#ibcon#about to read 5, iclass 21, count 0 2006.169.07:36:49.19#ibcon#read 5, iclass 21, count 0 2006.169.07:36:49.19#ibcon#about to read 6, iclass 21, count 0 2006.169.07:36:49.19#ibcon#read 6, iclass 21, count 0 2006.169.07:36:49.19#ibcon#end of sib2, iclass 21, count 0 2006.169.07:36:49.19#ibcon#*after write, iclass 21, count 0 2006.169.07:36:49.19#ibcon#*before return 0, iclass 21, count 0 2006.169.07:36:49.19#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:36:49.19#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:36:49.19#ibcon#about to clear, iclass 21 cls_cnt 0 2006.169.07:36:49.19#ibcon#cleared, iclass 21 cls_cnt 0 2006.169.07:36:49.19$vc4f8/vb=6,4 2006.169.07:36:49.19#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.169.07:36:49.19#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.169.07:36:49.19#ibcon#ireg 11 cls_cnt 2 2006.169.07:36:49.19#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.169.07:36:49.25#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.169.07:36:49.25#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.169.07:36:49.25#ibcon#enter wrdev, iclass 23, count 2 2006.169.07:36:49.25#ibcon#first serial, iclass 23, count 2 2006.169.07:36:49.25#ibcon#enter sib2, iclass 23, count 2 2006.169.07:36:49.25#ibcon#flushed, iclass 23, count 2 2006.169.07:36:49.25#ibcon#about to write, iclass 23, count 2 2006.169.07:36:49.25#ibcon#wrote, iclass 23, count 2 2006.169.07:36:49.25#ibcon#about to read 3, iclass 23, count 2 2006.169.07:36:49.27#ibcon#read 3, iclass 23, count 2 2006.169.07:36:49.27#ibcon#about to read 4, iclass 23, count 2 2006.169.07:36:49.27#ibcon#read 4, iclass 23, count 2 2006.169.07:36:49.27#ibcon#about to read 5, iclass 23, count 2 2006.169.07:36:49.27#ibcon#read 5, iclass 23, count 2 2006.169.07:36:49.27#ibcon#about to read 6, iclass 23, count 2 2006.169.07:36:49.27#ibcon#read 6, iclass 23, count 2 2006.169.07:36:49.27#ibcon#end of sib2, iclass 23, count 2 2006.169.07:36:49.27#ibcon#*mode == 0, iclass 23, count 2 2006.169.07:36:49.27#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.169.07:36:49.27#ibcon#[27=AT06-04\r\n] 2006.169.07:36:49.27#ibcon#*before write, iclass 23, count 2 2006.169.07:36:49.27#ibcon#enter sib2, iclass 23, count 2 2006.169.07:36:49.27#ibcon#flushed, iclass 23, count 2 2006.169.07:36:49.27#ibcon#about to write, iclass 23, count 2 2006.169.07:36:49.27#ibcon#wrote, iclass 23, count 2 2006.169.07:36:49.27#ibcon#about to read 3, iclass 23, count 2 2006.169.07:36:49.30#ibcon#read 3, iclass 23, count 2 2006.169.07:36:49.30#ibcon#about to read 4, iclass 23, count 2 2006.169.07:36:49.30#ibcon#read 4, iclass 23, count 2 2006.169.07:36:49.30#ibcon#about to read 5, iclass 23, count 2 2006.169.07:36:49.30#ibcon#read 5, iclass 23, count 2 2006.169.07:36:49.30#ibcon#about to read 6, iclass 23, count 2 2006.169.07:36:49.30#ibcon#read 6, iclass 23, count 2 2006.169.07:36:49.30#ibcon#end of sib2, iclass 23, count 2 2006.169.07:36:49.30#ibcon#*after write, iclass 23, count 2 2006.169.07:36:49.30#ibcon#*before return 0, iclass 23, count 2 2006.169.07:36:49.30#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.169.07:36:49.30#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.169.07:36:49.30#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.169.07:36:49.30#ibcon#ireg 7 cls_cnt 0 2006.169.07:36:49.30#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.169.07:36:49.42#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.169.07:36:49.42#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.169.07:36:49.42#ibcon#enter wrdev, iclass 23, count 0 2006.169.07:36:49.42#ibcon#first serial, iclass 23, count 0 2006.169.07:36:49.42#ibcon#enter sib2, iclass 23, count 0 2006.169.07:36:49.42#ibcon#flushed, iclass 23, count 0 2006.169.07:36:49.42#ibcon#about to write, iclass 23, count 0 2006.169.07:36:49.42#ibcon#wrote, iclass 23, count 0 2006.169.07:36:49.42#ibcon#about to read 3, iclass 23, count 0 2006.169.07:36:49.44#ibcon#read 3, iclass 23, count 0 2006.169.07:36:49.44#ibcon#about to read 4, iclass 23, count 0 2006.169.07:36:49.44#ibcon#read 4, iclass 23, count 0 2006.169.07:36:49.44#ibcon#about to read 5, iclass 23, count 0 2006.169.07:36:49.44#ibcon#read 5, iclass 23, count 0 2006.169.07:36:49.44#ibcon#about to read 6, iclass 23, count 0 2006.169.07:36:49.44#ibcon#read 6, iclass 23, count 0 2006.169.07:36:49.44#ibcon#end of sib2, iclass 23, count 0 2006.169.07:36:49.44#ibcon#*mode == 0, iclass 23, count 0 2006.169.07:36:49.44#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.169.07:36:49.44#ibcon#[27=USB\r\n] 2006.169.07:36:49.44#ibcon#*before write, iclass 23, count 0 2006.169.07:36:49.44#ibcon#enter sib2, iclass 23, count 0 2006.169.07:36:49.44#ibcon#flushed, iclass 23, count 0 2006.169.07:36:49.44#ibcon#about to write, iclass 23, count 0 2006.169.07:36:49.44#ibcon#wrote, iclass 23, count 0 2006.169.07:36:49.44#ibcon#about to read 3, iclass 23, count 0 2006.169.07:36:49.47#ibcon#read 3, iclass 23, count 0 2006.169.07:36:49.47#ibcon#about to read 4, iclass 23, count 0 2006.169.07:36:49.47#ibcon#read 4, iclass 23, count 0 2006.169.07:36:49.47#ibcon#about to read 5, iclass 23, count 0 2006.169.07:36:49.47#ibcon#read 5, iclass 23, count 0 2006.169.07:36:49.47#ibcon#about to read 6, iclass 23, count 0 2006.169.07:36:49.47#ibcon#read 6, iclass 23, count 0 2006.169.07:36:49.47#ibcon#end of sib2, iclass 23, count 0 2006.169.07:36:49.47#ibcon#*after write, iclass 23, count 0 2006.169.07:36:49.47#ibcon#*before return 0, iclass 23, count 0 2006.169.07:36:49.47#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.169.07:36:49.47#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.169.07:36:49.47#ibcon#about to clear, iclass 23 cls_cnt 0 2006.169.07:36:49.47#ibcon#cleared, iclass 23 cls_cnt 0 2006.169.07:36:49.47$vc4f8/vabw=wide 2006.169.07:36:49.47#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.169.07:36:49.47#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.169.07:36:49.47#ibcon#ireg 8 cls_cnt 0 2006.169.07:36:49.47#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:36:49.47#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:36:49.47#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:36:49.47#ibcon#enter wrdev, iclass 25, count 0 2006.169.07:36:49.47#ibcon#first serial, iclass 25, count 0 2006.169.07:36:49.47#ibcon#enter sib2, iclass 25, count 0 2006.169.07:36:49.47#ibcon#flushed, iclass 25, count 0 2006.169.07:36:49.47#ibcon#about to write, iclass 25, count 0 2006.169.07:36:49.47#ibcon#wrote, iclass 25, count 0 2006.169.07:36:49.47#ibcon#about to read 3, iclass 25, count 0 2006.169.07:36:49.49#ibcon#read 3, iclass 25, count 0 2006.169.07:36:49.49#ibcon#about to read 4, iclass 25, count 0 2006.169.07:36:49.49#ibcon#read 4, iclass 25, count 0 2006.169.07:36:49.49#ibcon#about to read 5, iclass 25, count 0 2006.169.07:36:49.49#ibcon#read 5, iclass 25, count 0 2006.169.07:36:49.49#ibcon#about to read 6, iclass 25, count 0 2006.169.07:36:49.49#ibcon#read 6, iclass 25, count 0 2006.169.07:36:49.49#ibcon#end of sib2, iclass 25, count 0 2006.169.07:36:49.49#ibcon#*mode == 0, iclass 25, count 0 2006.169.07:36:49.49#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.169.07:36:49.49#ibcon#[25=BW32\r\n] 2006.169.07:36:49.49#ibcon#*before write, iclass 25, count 0 2006.169.07:36:49.49#ibcon#enter sib2, iclass 25, count 0 2006.169.07:36:49.49#ibcon#flushed, iclass 25, count 0 2006.169.07:36:49.49#ibcon#about to write, iclass 25, count 0 2006.169.07:36:49.49#ibcon#wrote, iclass 25, count 0 2006.169.07:36:49.49#ibcon#about to read 3, iclass 25, count 0 2006.169.07:36:49.52#ibcon#read 3, iclass 25, count 0 2006.169.07:36:49.52#ibcon#about to read 4, iclass 25, count 0 2006.169.07:36:49.52#ibcon#read 4, iclass 25, count 0 2006.169.07:36:49.52#ibcon#about to read 5, iclass 25, count 0 2006.169.07:36:49.52#ibcon#read 5, iclass 25, count 0 2006.169.07:36:49.52#ibcon#about to read 6, iclass 25, count 0 2006.169.07:36:49.52#ibcon#read 6, iclass 25, count 0 2006.169.07:36:49.52#ibcon#end of sib2, iclass 25, count 0 2006.169.07:36:49.52#ibcon#*after write, iclass 25, count 0 2006.169.07:36:49.52#ibcon#*before return 0, iclass 25, count 0 2006.169.07:36:49.52#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:36:49.52#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:36:49.52#ibcon#about to clear, iclass 25 cls_cnt 0 2006.169.07:36:49.52#ibcon#cleared, iclass 25 cls_cnt 0 2006.169.07:36:49.52$vc4f8/vbbw=wide 2006.169.07:36:49.52#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.169.07:36:49.52#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.169.07:36:49.52#ibcon#ireg 8 cls_cnt 0 2006.169.07:36:49.52#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:36:49.59#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:36:49.59#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:36:49.59#ibcon#enter wrdev, iclass 27, count 0 2006.169.07:36:49.59#ibcon#first serial, iclass 27, count 0 2006.169.07:36:49.59#ibcon#enter sib2, iclass 27, count 0 2006.169.07:36:49.59#ibcon#flushed, iclass 27, count 0 2006.169.07:36:49.59#ibcon#about to write, iclass 27, count 0 2006.169.07:36:49.59#ibcon#wrote, iclass 27, count 0 2006.169.07:36:49.59#ibcon#about to read 3, iclass 27, count 0 2006.169.07:36:49.61#ibcon#read 3, iclass 27, count 0 2006.169.07:36:49.61#ibcon#about to read 4, iclass 27, count 0 2006.169.07:36:49.61#ibcon#read 4, iclass 27, count 0 2006.169.07:36:49.61#ibcon#about to read 5, iclass 27, count 0 2006.169.07:36:49.61#ibcon#read 5, iclass 27, count 0 2006.169.07:36:49.61#ibcon#about to read 6, iclass 27, count 0 2006.169.07:36:49.61#ibcon#read 6, iclass 27, count 0 2006.169.07:36:49.61#ibcon#end of sib2, iclass 27, count 0 2006.169.07:36:49.61#ibcon#*mode == 0, iclass 27, count 0 2006.169.07:36:49.61#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.169.07:36:49.61#ibcon#[27=BW32\r\n] 2006.169.07:36:49.61#ibcon#*before write, iclass 27, count 0 2006.169.07:36:49.61#ibcon#enter sib2, iclass 27, count 0 2006.169.07:36:49.61#ibcon#flushed, iclass 27, count 0 2006.169.07:36:49.61#ibcon#about to write, iclass 27, count 0 2006.169.07:36:49.61#ibcon#wrote, iclass 27, count 0 2006.169.07:36:49.61#ibcon#about to read 3, iclass 27, count 0 2006.169.07:36:49.64#ibcon#read 3, iclass 27, count 0 2006.169.07:36:49.64#ibcon#about to read 4, iclass 27, count 0 2006.169.07:36:49.64#ibcon#read 4, iclass 27, count 0 2006.169.07:36:49.64#ibcon#about to read 5, iclass 27, count 0 2006.169.07:36:49.64#ibcon#read 5, iclass 27, count 0 2006.169.07:36:49.64#ibcon#about to read 6, iclass 27, count 0 2006.169.07:36:49.64#ibcon#read 6, iclass 27, count 0 2006.169.07:36:49.64#ibcon#end of sib2, iclass 27, count 0 2006.169.07:36:49.64#ibcon#*after write, iclass 27, count 0 2006.169.07:36:49.64#ibcon#*before return 0, iclass 27, count 0 2006.169.07:36:49.64#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:36:49.64#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:36:49.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.169.07:36:49.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.169.07:36:49.64$4f8m12a/ifd4f 2006.169.07:36:49.64$ifd4f/lo= 2006.169.07:36:49.64$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.07:36:49.64$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.07:36:49.64$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.07:36:49.64$ifd4f/patch= 2006.169.07:36:49.64$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.07:36:49.64$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.07:36:49.64$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.07:36:49.64$4f8m12a/"form=m,16.000,1:2 2006.169.07:36:49.64$4f8m12a/"tpicd 2006.169.07:36:49.64$4f8m12a/echo=off 2006.169.07:36:49.64$4f8m12a/xlog=off 2006.169.07:36:49.64:!2006.169.07:37:00 2006.169.07:37:00.00:preob 2006.169.07:37:01.14/onsource/TRACKING 2006.169.07:37:01.14:!2006.169.07:37:10 2006.169.07:37:10.00:data_valid=on 2006.169.07:37:10.00:midob 2006.169.07:37:10.13/onsource/TRACKING 2006.169.07:37:10.13/wx/18.17,1003.7,100 2006.169.07:37:10.26/cable/+6.5281E-03 2006.169.07:37:11.35/va/01,08,usb,yes,51,54 2006.169.07:37:11.35/va/02,07,usb,yes,52,54 2006.169.07:37:11.35/va/03,06,usb,yes,55,55 2006.169.07:37:11.35/va/04,07,usb,yes,53,57 2006.169.07:37:11.35/va/05,07,usb,yes,58,62 2006.169.07:37:11.35/va/06,06,usb,yes,58,57 2006.169.07:37:11.35/va/07,06,usb,yes,58,58 2006.169.07:37:11.35/va/08,07,usb,yes,56,55 2006.169.07:37:11.58/valo/01,532.99,yes,locked 2006.169.07:37:11.58/valo/02,572.99,yes,locked 2006.169.07:37:11.58/valo/03,672.99,yes,locked 2006.169.07:37:11.58/valo/04,832.99,yes,locked 2006.169.07:37:11.58/valo/05,652.99,yes,locked 2006.169.07:37:11.58/valo/06,772.99,yes,locked 2006.169.07:37:11.58/valo/07,832.99,yes,locked 2006.169.07:37:11.58/valo/08,852.99,yes,locked 2006.169.07:37:12.67/vb/01,04,usb,yes,31,30 2006.169.07:37:12.67/vb/02,04,usb,yes,33,35 2006.169.07:37:12.67/vb/03,04,usb,yes,29,33 2006.169.07:37:12.67/vb/04,04,usb,yes,30,30 2006.169.07:37:12.67/vb/05,04,usb,yes,29,33 2006.169.07:37:12.67/vb/06,04,usb,yes,30,33 2006.169.07:37:12.67/vb/07,04,usb,yes,32,32 2006.169.07:37:12.67/vb/08,04,usb,yes,29,33 2006.169.07:37:12.90/vblo/01,632.99,yes,locked 2006.169.07:37:12.90/vblo/02,640.99,yes,locked 2006.169.07:37:12.90/vblo/03,656.99,yes,locked 2006.169.07:37:12.90/vblo/04,712.99,yes,locked 2006.169.07:37:12.90/vblo/05,744.99,yes,locked 2006.169.07:37:12.90/vblo/06,752.99,yes,locked 2006.169.07:37:12.90/vblo/07,734.99,yes,locked 2006.169.07:37:12.90/vblo/08,744.99,yes,locked 2006.169.07:37:13.05/vabw/8 2006.169.07:37:13.20/vbbw/8 2006.169.07:37:13.41/xfe/off,on,14.2 2006.169.07:37:13.78/ifatt/23,28,28,28 2006.169.07:37:14.08/fmout-gps/S +4.18E-07 2006.169.07:37:14.12:!2006.169.07:38:10 2006.169.07:38:10.02:data_valid=off 2006.169.07:38:10.02:postob 2006.169.07:38:10.10/cable/+6.5265E-03 2006.169.07:38:10.11/wx/18.16,1003.8,100 2006.169.07:38:11.08/fmout-gps/S +4.18E-07 2006.169.07:38:11.08:scan_name=169-0739,k06169,60 2006.169.07:38:11.08:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.169.07:38:11.14#flagr#flagr/antenna,new-source 2006.169.07:38:12.14:checkk5 2006.169.07:38:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.169.07:38:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.169.07:38:16.92/chk_autoobs//k5ts3?ERROR: timeout happened! 2006.169.07:38:17.29/chk_autoobs//k5ts4/ autoobs is running! 2006.169.07:38:17.66/chk_obsdata//k5ts1/T1690737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:38:18.04/chk_obsdata//k5ts2/T1690737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:38:25.10/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.07:38:25.48/chk_obsdata//k5ts4/T1690737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:38:26.17/k5log//k5ts1_log_newline 2006.169.07:38:26.86/k5log//k5ts2_log_newline 2006.169.07:38:32.13#trakl#Source acquired 2006.169.07:38:32.14#flagr#flagr/antenna,acquired 2006.169.07:38:33.96/k5log//k5ts3?ERROR: timeout happened! 2006.169.07:38:34.64/k5log//k5ts4_log_newline 2006.169.07:38:34.80/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.07:38:34.80:4f8m12a=1 2006.169.07:38:34.80$4f8m12a/echo=on 2006.169.07:38:34.80$4f8m12a/pcalon 2006.169.07:38:34.80$pcalon/"no phase cal control is implemented here 2006.169.07:38:34.80$4f8m12a/"tpicd=stop 2006.169.07:38:34.80$4f8m12a/vc4f8 2006.169.07:38:34.80$vc4f8/valo=1,532.99 2006.169.07:38:34.80#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.169.07:38:34.80#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.169.07:38:34.80#ibcon#ireg 17 cls_cnt 0 2006.169.07:38:34.80#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:38:34.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:38:34.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:38:34.80#ibcon#enter wrdev, iclass 38, count 0 2006.169.07:38:34.80#ibcon#first serial, iclass 38, count 0 2006.169.07:38:34.80#ibcon#enter sib2, iclass 38, count 0 2006.169.07:38:34.80#ibcon#flushed, iclass 38, count 0 2006.169.07:38:34.80#ibcon#about to write, iclass 38, count 0 2006.169.07:38:34.80#ibcon#wrote, iclass 38, count 0 2006.169.07:38:34.80#ibcon#about to read 3, iclass 38, count 0 2006.169.07:38:34.82#ibcon#read 3, iclass 38, count 0 2006.169.07:38:34.82#ibcon#about to read 4, iclass 38, count 0 2006.169.07:38:34.82#ibcon#read 4, iclass 38, count 0 2006.169.07:38:34.82#ibcon#about to read 5, iclass 38, count 0 2006.169.07:38:34.82#ibcon#read 5, iclass 38, count 0 2006.169.07:38:34.82#ibcon#about to read 6, iclass 38, count 0 2006.169.07:38:34.82#ibcon#read 6, iclass 38, count 0 2006.169.07:38:34.82#ibcon#end of sib2, iclass 38, count 0 2006.169.07:38:34.82#ibcon#*mode == 0, iclass 38, count 0 2006.169.07:38:34.82#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.169.07:38:34.82#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.07:38:34.82#ibcon#*before write, iclass 38, count 0 2006.169.07:38:34.82#ibcon#enter sib2, iclass 38, count 0 2006.169.07:38:34.82#ibcon#flushed, iclass 38, count 0 2006.169.07:38:34.82#ibcon#about to write, iclass 38, count 0 2006.169.07:38:34.83#ibcon#wrote, iclass 38, count 0 2006.169.07:38:34.83#ibcon#about to read 3, iclass 38, count 0 2006.169.07:38:34.88#ibcon#read 3, iclass 38, count 0 2006.169.07:38:34.88#ibcon#about to read 4, iclass 38, count 0 2006.169.07:38:34.88#ibcon#read 4, iclass 38, count 0 2006.169.07:38:34.88#ibcon#about to read 5, iclass 38, count 0 2006.169.07:38:34.88#ibcon#read 5, iclass 38, count 0 2006.169.07:38:34.88#ibcon#about to read 6, iclass 38, count 0 2006.169.07:38:34.88#ibcon#read 6, iclass 38, count 0 2006.169.07:38:34.88#ibcon#end of sib2, iclass 38, count 0 2006.169.07:38:34.88#ibcon#*after write, iclass 38, count 0 2006.169.07:38:34.88#ibcon#*before return 0, iclass 38, count 0 2006.169.07:38:34.88#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:38:34.88#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:38:34.88#ibcon#about to clear, iclass 38 cls_cnt 0 2006.169.07:38:34.88#ibcon#cleared, iclass 38 cls_cnt 0 2006.169.07:38:34.88$vc4f8/va=1,8 2006.169.07:38:34.88#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.169.07:38:34.88#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.169.07:38:34.88#ibcon#ireg 11 cls_cnt 2 2006.169.07:38:34.88#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.169.07:38:34.88#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.169.07:38:34.88#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.169.07:38:34.88#ibcon#enter wrdev, iclass 40, count 2 2006.169.07:38:34.88#ibcon#first serial, iclass 40, count 2 2006.169.07:38:34.88#ibcon#enter sib2, iclass 40, count 2 2006.169.07:38:34.88#ibcon#flushed, iclass 40, count 2 2006.169.07:38:34.88#ibcon#about to write, iclass 40, count 2 2006.169.07:38:34.88#ibcon#wrote, iclass 40, count 2 2006.169.07:38:34.88#ibcon#about to read 3, iclass 40, count 2 2006.169.07:38:34.90#ibcon#read 3, iclass 40, count 2 2006.169.07:38:34.90#ibcon#about to read 4, iclass 40, count 2 2006.169.07:38:34.90#ibcon#read 4, iclass 40, count 2 2006.169.07:38:34.90#ibcon#about to read 5, iclass 40, count 2 2006.169.07:38:34.90#ibcon#read 5, iclass 40, count 2 2006.169.07:38:34.90#ibcon#about to read 6, iclass 40, count 2 2006.169.07:38:34.90#ibcon#read 6, iclass 40, count 2 2006.169.07:38:34.90#ibcon#end of sib2, iclass 40, count 2 2006.169.07:38:34.90#ibcon#*mode == 0, iclass 40, count 2 2006.169.07:38:34.90#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.169.07:38:34.90#ibcon#[25=AT01-08\r\n] 2006.169.07:38:34.90#ibcon#*before write, iclass 40, count 2 2006.169.07:38:34.90#ibcon#enter sib2, iclass 40, count 2 2006.169.07:38:34.90#ibcon#flushed, iclass 40, count 2 2006.169.07:38:34.90#ibcon#about to write, iclass 40, count 2 2006.169.07:38:34.90#ibcon#wrote, iclass 40, count 2 2006.169.07:38:34.90#ibcon#about to read 3, iclass 40, count 2 2006.169.07:38:34.92#ibcon#read 3, iclass 40, count 2 2006.169.07:38:34.92#ibcon#about to read 4, iclass 40, count 2 2006.169.07:38:34.92#ibcon#read 4, iclass 40, count 2 2006.169.07:38:34.92#ibcon#about to read 5, iclass 40, count 2 2006.169.07:38:34.92#ibcon#read 5, iclass 40, count 2 2006.169.07:38:34.92#ibcon#about to read 6, iclass 40, count 2 2006.169.07:38:34.92#ibcon#read 6, iclass 40, count 2 2006.169.07:38:34.92#ibcon#end of sib2, iclass 40, count 2 2006.169.07:38:34.92#ibcon#*after write, iclass 40, count 2 2006.169.07:38:34.92#ibcon#*before return 0, iclass 40, count 2 2006.169.07:38:34.92#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.169.07:38:34.92#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.169.07:38:34.92#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.169.07:38:34.92#ibcon#ireg 7 cls_cnt 0 2006.169.07:38:34.92#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.169.07:38:35.04#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.169.07:38:35.04#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.169.07:38:35.04#ibcon#enter wrdev, iclass 40, count 0 2006.169.07:38:35.04#ibcon#first serial, iclass 40, count 0 2006.169.07:38:35.04#ibcon#enter sib2, iclass 40, count 0 2006.169.07:38:35.04#ibcon#flushed, iclass 40, count 0 2006.169.07:38:35.04#ibcon#about to write, iclass 40, count 0 2006.169.07:38:35.04#ibcon#wrote, iclass 40, count 0 2006.169.07:38:35.04#ibcon#about to read 3, iclass 40, count 0 2006.169.07:38:35.08#ibcon#read 3, iclass 40, count 0 2006.169.07:38:35.08#ibcon#about to read 4, iclass 40, count 0 2006.169.07:38:35.08#ibcon#read 4, iclass 40, count 0 2006.169.07:38:35.08#ibcon#about to read 5, iclass 40, count 0 2006.169.07:38:35.08#ibcon#read 5, iclass 40, count 0 2006.169.07:38:35.08#ibcon#about to read 6, iclass 40, count 0 2006.169.07:38:35.08#ibcon#read 6, iclass 40, count 0 2006.169.07:38:35.08#ibcon#end of sib2, iclass 40, count 0 2006.169.07:38:35.08#ibcon#*mode == 0, iclass 40, count 0 2006.169.07:38:35.08#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.169.07:38:35.08#ibcon#[25=USB\r\n] 2006.169.07:38:35.08#ibcon#*before write, iclass 40, count 0 2006.169.07:38:35.08#ibcon#enter sib2, iclass 40, count 0 2006.169.07:38:35.08#ibcon#flushed, iclass 40, count 0 2006.169.07:38:35.08#ibcon#about to write, iclass 40, count 0 2006.169.07:38:35.08#ibcon#wrote, iclass 40, count 0 2006.169.07:38:35.08#ibcon#about to read 3, iclass 40, count 0 2006.169.07:38:35.11#ibcon#read 3, iclass 40, count 0 2006.169.07:38:35.11#ibcon#about to read 4, iclass 40, count 0 2006.169.07:38:35.11#ibcon#read 4, iclass 40, count 0 2006.169.07:38:35.11#ibcon#about to read 5, iclass 40, count 0 2006.169.07:38:35.11#ibcon#read 5, iclass 40, count 0 2006.169.07:38:35.11#ibcon#about to read 6, iclass 40, count 0 2006.169.07:38:35.11#ibcon#read 6, iclass 40, count 0 2006.169.07:38:35.11#ibcon#end of sib2, iclass 40, count 0 2006.169.07:38:35.11#ibcon#*after write, iclass 40, count 0 2006.169.07:38:35.11#ibcon#*before return 0, iclass 40, count 0 2006.169.07:38:35.11#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.169.07:38:35.11#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.169.07:38:35.11#ibcon#about to clear, iclass 40 cls_cnt 0 2006.169.07:38:35.11#ibcon#cleared, iclass 40 cls_cnt 0 2006.169.07:38:35.12$vc4f8/valo=2,572.99 2006.169.07:38:35.12#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.169.07:38:35.12#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.169.07:38:35.12#ibcon#ireg 17 cls_cnt 0 2006.169.07:38:35.12#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.169.07:38:35.12#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.169.07:38:35.12#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.169.07:38:35.12#ibcon#enter wrdev, iclass 4, count 0 2006.169.07:38:35.12#ibcon#first serial, iclass 4, count 0 2006.169.07:38:35.12#ibcon#enter sib2, iclass 4, count 0 2006.169.07:38:35.12#ibcon#flushed, iclass 4, count 0 2006.169.07:38:35.12#ibcon#about to write, iclass 4, count 0 2006.169.07:38:35.12#ibcon#wrote, iclass 4, count 0 2006.169.07:38:35.12#ibcon#about to read 3, iclass 4, count 0 2006.169.07:38:35.14#ibcon#read 3, iclass 4, count 0 2006.169.07:38:35.14#ibcon#about to read 4, iclass 4, count 0 2006.169.07:38:35.14#ibcon#read 4, iclass 4, count 0 2006.169.07:38:35.14#ibcon#about to read 5, iclass 4, count 0 2006.169.07:38:35.14#ibcon#read 5, iclass 4, count 0 2006.169.07:38:35.14#ibcon#about to read 6, iclass 4, count 0 2006.169.07:38:35.14#ibcon#read 6, iclass 4, count 0 2006.169.07:38:35.14#ibcon#end of sib2, iclass 4, count 0 2006.169.07:38:35.14#ibcon#*mode == 0, iclass 4, count 0 2006.169.07:38:35.14#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.169.07:38:35.14#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.07:38:35.14#ibcon#*before write, iclass 4, count 0 2006.169.07:38:35.14#ibcon#enter sib2, iclass 4, count 0 2006.169.07:38:35.14#ibcon#flushed, iclass 4, count 0 2006.169.07:38:35.14#ibcon#about to write, iclass 4, count 0 2006.169.07:38:35.14#ibcon#wrote, iclass 4, count 0 2006.169.07:38:35.14#ibcon#about to read 3, iclass 4, count 0 2006.169.07:38:35.17#ibcon#read 3, iclass 4, count 0 2006.169.07:38:35.17#ibcon#about to read 4, iclass 4, count 0 2006.169.07:38:35.17#ibcon#read 4, iclass 4, count 0 2006.169.07:38:35.17#ibcon#about to read 5, iclass 4, count 0 2006.169.07:38:35.17#ibcon#read 5, iclass 4, count 0 2006.169.07:38:35.17#ibcon#about to read 6, iclass 4, count 0 2006.169.07:38:35.17#ibcon#read 6, iclass 4, count 0 2006.169.07:38:35.17#ibcon#end of sib2, iclass 4, count 0 2006.169.07:38:35.17#ibcon#*after write, iclass 4, count 0 2006.169.07:38:35.17#ibcon#*before return 0, iclass 4, count 0 2006.169.07:38:35.18#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.169.07:38:35.18#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.169.07:38:35.18#ibcon#about to clear, iclass 4 cls_cnt 0 2006.169.07:38:35.18#ibcon#cleared, iclass 4 cls_cnt 0 2006.169.07:38:35.18$vc4f8/va=2,7 2006.169.07:38:35.18#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.169.07:38:35.18#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.169.07:38:35.18#ibcon#ireg 11 cls_cnt 2 2006.169.07:38:35.18#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.169.07:38:35.22#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.169.07:38:35.22#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.169.07:38:35.22#ibcon#enter wrdev, iclass 6, count 2 2006.169.07:38:35.22#ibcon#first serial, iclass 6, count 2 2006.169.07:38:35.22#ibcon#enter sib2, iclass 6, count 2 2006.169.07:38:35.22#ibcon#flushed, iclass 6, count 2 2006.169.07:38:35.22#ibcon#about to write, iclass 6, count 2 2006.169.07:38:35.22#ibcon#wrote, iclass 6, count 2 2006.169.07:38:35.22#ibcon#about to read 3, iclass 6, count 2 2006.169.07:38:35.24#ibcon#read 3, iclass 6, count 2 2006.169.07:38:35.24#ibcon#about to read 4, iclass 6, count 2 2006.169.07:38:35.24#ibcon#read 4, iclass 6, count 2 2006.169.07:38:35.24#ibcon#about to read 5, iclass 6, count 2 2006.169.07:38:35.24#ibcon#read 5, iclass 6, count 2 2006.169.07:38:35.24#ibcon#about to read 6, iclass 6, count 2 2006.169.07:38:35.24#ibcon#read 6, iclass 6, count 2 2006.169.07:38:35.24#ibcon#end of sib2, iclass 6, count 2 2006.169.07:38:35.24#ibcon#*mode == 0, iclass 6, count 2 2006.169.07:38:35.24#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.169.07:38:35.24#ibcon#[25=AT02-07\r\n] 2006.169.07:38:35.24#ibcon#*before write, iclass 6, count 2 2006.169.07:38:35.24#ibcon#enter sib2, iclass 6, count 2 2006.169.07:38:35.24#ibcon#flushed, iclass 6, count 2 2006.169.07:38:35.25#ibcon#about to write, iclass 6, count 2 2006.169.07:38:35.25#ibcon#wrote, iclass 6, count 2 2006.169.07:38:35.25#ibcon#about to read 3, iclass 6, count 2 2006.169.07:38:35.27#ibcon#read 3, iclass 6, count 2 2006.169.07:38:35.27#ibcon#about to read 4, iclass 6, count 2 2006.169.07:38:35.27#ibcon#read 4, iclass 6, count 2 2006.169.07:38:35.27#ibcon#about to read 5, iclass 6, count 2 2006.169.07:38:35.27#ibcon#read 5, iclass 6, count 2 2006.169.07:38:35.27#ibcon#about to read 6, iclass 6, count 2 2006.169.07:38:35.27#ibcon#read 6, iclass 6, count 2 2006.169.07:38:35.27#ibcon#end of sib2, iclass 6, count 2 2006.169.07:38:35.27#ibcon#*after write, iclass 6, count 2 2006.169.07:38:35.27#ibcon#*before return 0, iclass 6, count 2 2006.169.07:38:35.27#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.169.07:38:35.27#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.169.07:38:35.27#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.169.07:38:35.27#ibcon#ireg 7 cls_cnt 0 2006.169.07:38:35.27#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.169.07:38:35.40#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.169.07:38:35.40#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.169.07:38:35.40#ibcon#enter wrdev, iclass 6, count 0 2006.169.07:38:35.40#ibcon#first serial, iclass 6, count 0 2006.169.07:38:35.40#ibcon#enter sib2, iclass 6, count 0 2006.169.07:38:35.40#ibcon#flushed, iclass 6, count 0 2006.169.07:38:35.40#ibcon#about to write, iclass 6, count 0 2006.169.07:38:35.40#ibcon#wrote, iclass 6, count 0 2006.169.07:38:35.40#ibcon#about to read 3, iclass 6, count 0 2006.169.07:38:35.41#ibcon#read 3, iclass 6, count 0 2006.169.07:38:35.41#ibcon#about to read 4, iclass 6, count 0 2006.169.07:38:35.41#ibcon#read 4, iclass 6, count 0 2006.169.07:38:35.41#ibcon#about to read 5, iclass 6, count 0 2006.169.07:38:35.41#ibcon#read 5, iclass 6, count 0 2006.169.07:38:35.41#ibcon#about to read 6, iclass 6, count 0 2006.169.07:38:35.41#ibcon#read 6, iclass 6, count 0 2006.169.07:38:35.41#ibcon#end of sib2, iclass 6, count 0 2006.169.07:38:35.41#ibcon#*mode == 0, iclass 6, count 0 2006.169.07:38:35.41#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.169.07:38:35.41#ibcon#[25=USB\r\n] 2006.169.07:38:35.41#ibcon#*before write, iclass 6, count 0 2006.169.07:38:35.41#ibcon#enter sib2, iclass 6, count 0 2006.169.07:38:35.41#ibcon#flushed, iclass 6, count 0 2006.169.07:38:35.42#ibcon#about to write, iclass 6, count 0 2006.169.07:38:35.42#ibcon#wrote, iclass 6, count 0 2006.169.07:38:35.42#ibcon#about to read 3, iclass 6, count 0 2006.169.07:38:35.44#ibcon#read 3, iclass 6, count 0 2006.169.07:38:35.44#ibcon#about to read 4, iclass 6, count 0 2006.169.07:38:35.44#ibcon#read 4, iclass 6, count 0 2006.169.07:38:35.44#ibcon#about to read 5, iclass 6, count 0 2006.169.07:38:35.44#ibcon#read 5, iclass 6, count 0 2006.169.07:38:35.44#ibcon#about to read 6, iclass 6, count 0 2006.169.07:38:35.44#ibcon#read 6, iclass 6, count 0 2006.169.07:38:35.44#ibcon#end of sib2, iclass 6, count 0 2006.169.07:38:35.44#ibcon#*after write, iclass 6, count 0 2006.169.07:38:35.44#ibcon#*before return 0, iclass 6, count 0 2006.169.07:38:35.44#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.169.07:38:35.44#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.169.07:38:35.44#ibcon#about to clear, iclass 6 cls_cnt 0 2006.169.07:38:35.44#ibcon#cleared, iclass 6 cls_cnt 0 2006.169.07:38:35.45$vc4f8/valo=3,672.99 2006.169.07:38:35.45#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.169.07:38:35.45#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.169.07:38:35.45#ibcon#ireg 17 cls_cnt 0 2006.169.07:38:35.45#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.169.07:38:35.45#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.169.07:38:35.45#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.169.07:38:35.45#ibcon#enter wrdev, iclass 10, count 0 2006.169.07:38:35.45#ibcon#first serial, iclass 10, count 0 2006.169.07:38:35.45#ibcon#enter sib2, iclass 10, count 0 2006.169.07:38:35.45#ibcon#flushed, iclass 10, count 0 2006.169.07:38:35.45#ibcon#about to write, iclass 10, count 0 2006.169.07:38:35.45#ibcon#wrote, iclass 10, count 0 2006.169.07:38:35.45#ibcon#about to read 3, iclass 10, count 0 2006.169.07:38:35.46#ibcon#read 3, iclass 10, count 0 2006.169.07:38:35.46#ibcon#about to read 4, iclass 10, count 0 2006.169.07:38:35.46#ibcon#read 4, iclass 10, count 0 2006.169.07:38:35.46#ibcon#about to read 5, iclass 10, count 0 2006.169.07:38:35.46#ibcon#read 5, iclass 10, count 0 2006.169.07:38:35.46#ibcon#about to read 6, iclass 10, count 0 2006.169.07:38:35.46#ibcon#read 6, iclass 10, count 0 2006.169.07:38:35.46#ibcon#end of sib2, iclass 10, count 0 2006.169.07:38:35.46#ibcon#*mode == 0, iclass 10, count 0 2006.169.07:38:35.46#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.169.07:38:35.46#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.07:38:35.46#ibcon#*before write, iclass 10, count 0 2006.169.07:38:35.46#ibcon#enter sib2, iclass 10, count 0 2006.169.07:38:35.47#ibcon#flushed, iclass 10, count 0 2006.169.07:38:35.47#ibcon#about to write, iclass 10, count 0 2006.169.07:38:35.47#ibcon#wrote, iclass 10, count 0 2006.169.07:38:35.47#ibcon#about to read 3, iclass 10, count 0 2006.169.07:38:35.51#ibcon#read 3, iclass 10, count 0 2006.169.07:38:35.51#ibcon#about to read 4, iclass 10, count 0 2006.169.07:38:35.51#ibcon#read 4, iclass 10, count 0 2006.169.07:38:35.51#ibcon#about to read 5, iclass 10, count 0 2006.169.07:38:35.51#ibcon#read 5, iclass 10, count 0 2006.169.07:38:35.51#ibcon#about to read 6, iclass 10, count 0 2006.169.07:38:35.51#ibcon#read 6, iclass 10, count 0 2006.169.07:38:35.51#ibcon#end of sib2, iclass 10, count 0 2006.169.07:38:35.51#ibcon#*after write, iclass 10, count 0 2006.169.07:38:35.51#ibcon#*before return 0, iclass 10, count 0 2006.169.07:38:35.51#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.169.07:38:35.51#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.169.07:38:35.51#ibcon#about to clear, iclass 10 cls_cnt 0 2006.169.07:38:35.51#ibcon#cleared, iclass 10 cls_cnt 0 2006.169.07:38:35.51$vc4f8/va=3,6 2006.169.07:38:35.51#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.169.07:38:35.51#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.169.07:38:35.51#ibcon#ireg 11 cls_cnt 2 2006.169.07:38:35.51#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.169.07:38:35.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.169.07:38:35.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.169.07:38:35.55#ibcon#enter wrdev, iclass 12, count 2 2006.169.07:38:35.55#ibcon#first serial, iclass 12, count 2 2006.169.07:38:35.55#ibcon#enter sib2, iclass 12, count 2 2006.169.07:38:35.55#ibcon#flushed, iclass 12, count 2 2006.169.07:38:35.55#ibcon#about to write, iclass 12, count 2 2006.169.07:38:35.55#ibcon#wrote, iclass 12, count 2 2006.169.07:38:35.55#ibcon#about to read 3, iclass 12, count 2 2006.169.07:38:35.57#ibcon#read 3, iclass 12, count 2 2006.169.07:38:35.57#ibcon#about to read 4, iclass 12, count 2 2006.169.07:38:35.57#ibcon#read 4, iclass 12, count 2 2006.169.07:38:35.57#ibcon#about to read 5, iclass 12, count 2 2006.169.07:38:35.57#ibcon#read 5, iclass 12, count 2 2006.169.07:38:35.57#ibcon#about to read 6, iclass 12, count 2 2006.169.07:38:35.57#ibcon#read 6, iclass 12, count 2 2006.169.07:38:35.57#ibcon#end of sib2, iclass 12, count 2 2006.169.07:38:35.57#ibcon#*mode == 0, iclass 12, count 2 2006.169.07:38:35.57#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.169.07:38:35.57#ibcon#[25=AT03-06\r\n] 2006.169.07:38:35.57#ibcon#*before write, iclass 12, count 2 2006.169.07:38:35.57#ibcon#enter sib2, iclass 12, count 2 2006.169.07:38:35.57#ibcon#flushed, iclass 12, count 2 2006.169.07:38:35.57#ibcon#about to write, iclass 12, count 2 2006.169.07:38:35.57#ibcon#wrote, iclass 12, count 2 2006.169.07:38:35.58#ibcon#about to read 3, iclass 12, count 2 2006.169.07:38:35.60#ibcon#read 3, iclass 12, count 2 2006.169.07:38:35.60#ibcon#about to read 4, iclass 12, count 2 2006.169.07:38:35.60#ibcon#read 4, iclass 12, count 2 2006.169.07:38:35.60#ibcon#about to read 5, iclass 12, count 2 2006.169.07:38:35.60#ibcon#read 5, iclass 12, count 2 2006.169.07:38:35.60#ibcon#about to read 6, iclass 12, count 2 2006.169.07:38:35.60#ibcon#read 6, iclass 12, count 2 2006.169.07:38:35.60#ibcon#end of sib2, iclass 12, count 2 2006.169.07:38:35.60#ibcon#*after write, iclass 12, count 2 2006.169.07:38:35.60#ibcon#*before return 0, iclass 12, count 2 2006.169.07:38:35.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.169.07:38:35.60#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.169.07:38:35.60#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.169.07:38:35.60#ibcon#ireg 7 cls_cnt 0 2006.169.07:38:35.60#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.169.07:38:35.72#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.169.07:38:35.72#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.169.07:38:35.72#ibcon#enter wrdev, iclass 12, count 0 2006.169.07:38:35.72#ibcon#first serial, iclass 12, count 0 2006.169.07:38:35.72#ibcon#enter sib2, iclass 12, count 0 2006.169.07:38:35.72#ibcon#flushed, iclass 12, count 0 2006.169.07:38:35.72#ibcon#about to write, iclass 12, count 0 2006.169.07:38:35.72#ibcon#wrote, iclass 12, count 0 2006.169.07:38:35.72#ibcon#about to read 3, iclass 12, count 0 2006.169.07:38:35.74#ibcon#read 3, iclass 12, count 0 2006.169.07:38:35.74#ibcon#about to read 4, iclass 12, count 0 2006.169.07:38:35.74#ibcon#read 4, iclass 12, count 0 2006.169.07:38:35.74#ibcon#about to read 5, iclass 12, count 0 2006.169.07:38:35.74#ibcon#read 5, iclass 12, count 0 2006.169.07:38:35.74#ibcon#about to read 6, iclass 12, count 0 2006.169.07:38:35.74#ibcon#read 6, iclass 12, count 0 2006.169.07:38:35.74#ibcon#end of sib2, iclass 12, count 0 2006.169.07:38:35.74#ibcon#*mode == 0, iclass 12, count 0 2006.169.07:38:35.74#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.169.07:38:35.74#ibcon#[25=USB\r\n] 2006.169.07:38:35.74#ibcon#*before write, iclass 12, count 0 2006.169.07:38:35.74#ibcon#enter sib2, iclass 12, count 0 2006.169.07:38:35.74#ibcon#flushed, iclass 12, count 0 2006.169.07:38:35.74#ibcon#about to write, iclass 12, count 0 2006.169.07:38:35.74#ibcon#wrote, iclass 12, count 0 2006.169.07:38:35.75#ibcon#about to read 3, iclass 12, count 0 2006.169.07:38:35.77#ibcon#read 3, iclass 12, count 0 2006.169.07:38:35.77#ibcon#about to read 4, iclass 12, count 0 2006.169.07:38:35.77#ibcon#read 4, iclass 12, count 0 2006.169.07:38:35.77#ibcon#about to read 5, iclass 12, count 0 2006.169.07:38:35.77#ibcon#read 5, iclass 12, count 0 2006.169.07:38:35.77#ibcon#about to read 6, iclass 12, count 0 2006.169.07:38:35.77#ibcon#read 6, iclass 12, count 0 2006.169.07:38:35.77#ibcon#end of sib2, iclass 12, count 0 2006.169.07:38:35.77#ibcon#*after write, iclass 12, count 0 2006.169.07:38:35.77#ibcon#*before return 0, iclass 12, count 0 2006.169.07:38:35.77#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.169.07:38:35.77#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.169.07:38:35.77#ibcon#about to clear, iclass 12 cls_cnt 0 2006.169.07:38:35.77#ibcon#cleared, iclass 12 cls_cnt 0 2006.169.07:38:35.78$vc4f8/valo=4,832.99 2006.169.07:38:35.78#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.169.07:38:35.78#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.169.07:38:35.78#ibcon#ireg 17 cls_cnt 0 2006.169.07:38:35.78#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.169.07:38:35.78#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.169.07:38:35.78#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.169.07:38:35.78#ibcon#enter wrdev, iclass 14, count 0 2006.169.07:38:35.78#ibcon#first serial, iclass 14, count 0 2006.169.07:38:35.78#ibcon#enter sib2, iclass 14, count 0 2006.169.07:38:35.78#ibcon#flushed, iclass 14, count 0 2006.169.07:38:35.78#ibcon#about to write, iclass 14, count 0 2006.169.07:38:35.78#ibcon#wrote, iclass 14, count 0 2006.169.07:38:35.78#ibcon#about to read 3, iclass 14, count 0 2006.169.07:38:35.79#ibcon#read 3, iclass 14, count 0 2006.169.07:38:35.79#ibcon#about to read 4, iclass 14, count 0 2006.169.07:38:35.79#ibcon#read 4, iclass 14, count 0 2006.169.07:38:35.79#ibcon#about to read 5, iclass 14, count 0 2006.169.07:38:35.79#ibcon#read 5, iclass 14, count 0 2006.169.07:38:35.79#ibcon#about to read 6, iclass 14, count 0 2006.169.07:38:35.79#ibcon#read 6, iclass 14, count 0 2006.169.07:38:35.79#ibcon#end of sib2, iclass 14, count 0 2006.169.07:38:35.79#ibcon#*mode == 0, iclass 14, count 0 2006.169.07:38:35.79#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.169.07:38:35.79#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.07:38:35.79#ibcon#*before write, iclass 14, count 0 2006.169.07:38:35.79#ibcon#enter sib2, iclass 14, count 0 2006.169.07:38:35.79#ibcon#flushed, iclass 14, count 0 2006.169.07:38:35.79#ibcon#about to write, iclass 14, count 0 2006.169.07:38:35.79#ibcon#wrote, iclass 14, count 0 2006.169.07:38:35.80#ibcon#about to read 3, iclass 14, count 0 2006.169.07:38:35.83#ibcon#read 3, iclass 14, count 0 2006.169.07:38:35.83#ibcon#about to read 4, iclass 14, count 0 2006.169.07:38:35.83#ibcon#read 4, iclass 14, count 0 2006.169.07:38:35.83#ibcon#about to read 5, iclass 14, count 0 2006.169.07:38:35.83#ibcon#read 5, iclass 14, count 0 2006.169.07:38:35.83#ibcon#about to read 6, iclass 14, count 0 2006.169.07:38:35.83#ibcon#read 6, iclass 14, count 0 2006.169.07:38:35.83#ibcon#end of sib2, iclass 14, count 0 2006.169.07:38:35.83#ibcon#*after write, iclass 14, count 0 2006.169.07:38:35.83#ibcon#*before return 0, iclass 14, count 0 2006.169.07:38:35.83#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.169.07:38:35.83#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.169.07:38:35.83#ibcon#about to clear, iclass 14 cls_cnt 0 2006.169.07:38:35.83#ibcon#cleared, iclass 14 cls_cnt 0 2006.169.07:38:35.84$vc4f8/va=4,7 2006.169.07:38:35.84#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.169.07:38:35.84#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.169.07:38:35.84#ibcon#ireg 11 cls_cnt 2 2006.169.07:38:35.84#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.169.07:38:35.88#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.169.07:38:35.88#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.169.07:38:35.88#ibcon#enter wrdev, iclass 16, count 2 2006.169.07:38:35.88#ibcon#first serial, iclass 16, count 2 2006.169.07:38:35.88#ibcon#enter sib2, iclass 16, count 2 2006.169.07:38:35.88#ibcon#flushed, iclass 16, count 2 2006.169.07:38:35.88#ibcon#about to write, iclass 16, count 2 2006.169.07:38:35.88#ibcon#wrote, iclass 16, count 2 2006.169.07:38:35.88#ibcon#about to read 3, iclass 16, count 2 2006.169.07:38:35.90#ibcon#read 3, iclass 16, count 2 2006.169.07:38:35.90#ibcon#about to read 4, iclass 16, count 2 2006.169.07:38:35.90#ibcon#read 4, iclass 16, count 2 2006.169.07:38:35.90#ibcon#about to read 5, iclass 16, count 2 2006.169.07:38:35.90#ibcon#read 5, iclass 16, count 2 2006.169.07:38:35.90#ibcon#about to read 6, iclass 16, count 2 2006.169.07:38:35.90#ibcon#read 6, iclass 16, count 2 2006.169.07:38:35.90#ibcon#end of sib2, iclass 16, count 2 2006.169.07:38:35.90#ibcon#*mode == 0, iclass 16, count 2 2006.169.07:38:35.90#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.169.07:38:35.90#ibcon#[25=AT04-07\r\n] 2006.169.07:38:35.90#ibcon#*before write, iclass 16, count 2 2006.169.07:38:35.90#ibcon#enter sib2, iclass 16, count 2 2006.169.07:38:35.90#ibcon#flushed, iclass 16, count 2 2006.169.07:38:35.90#ibcon#about to write, iclass 16, count 2 2006.169.07:38:35.90#ibcon#wrote, iclass 16, count 2 2006.169.07:38:35.91#ibcon#about to read 3, iclass 16, count 2 2006.169.07:38:35.93#ibcon#read 3, iclass 16, count 2 2006.169.07:38:35.93#ibcon#about to read 4, iclass 16, count 2 2006.169.07:38:35.93#ibcon#read 4, iclass 16, count 2 2006.169.07:38:35.93#ibcon#about to read 5, iclass 16, count 2 2006.169.07:38:35.93#ibcon#read 5, iclass 16, count 2 2006.169.07:38:35.93#ibcon#about to read 6, iclass 16, count 2 2006.169.07:38:35.93#ibcon#read 6, iclass 16, count 2 2006.169.07:38:35.93#ibcon#end of sib2, iclass 16, count 2 2006.169.07:38:35.93#ibcon#*after write, iclass 16, count 2 2006.169.07:38:35.93#ibcon#*before return 0, iclass 16, count 2 2006.169.07:38:35.93#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.169.07:38:35.93#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.169.07:38:35.93#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.169.07:38:35.93#ibcon#ireg 7 cls_cnt 0 2006.169.07:38:35.93#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.169.07:38:36.05#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.169.07:38:36.05#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.169.07:38:36.05#ibcon#enter wrdev, iclass 16, count 0 2006.169.07:38:36.05#ibcon#first serial, iclass 16, count 0 2006.169.07:38:36.05#ibcon#enter sib2, iclass 16, count 0 2006.169.07:38:36.05#ibcon#flushed, iclass 16, count 0 2006.169.07:38:36.05#ibcon#about to write, iclass 16, count 0 2006.169.07:38:36.05#ibcon#wrote, iclass 16, count 0 2006.169.07:38:36.05#ibcon#about to read 3, iclass 16, count 0 2006.169.07:38:36.07#ibcon#read 3, iclass 16, count 0 2006.169.07:38:36.07#ibcon#about to read 4, iclass 16, count 0 2006.169.07:38:36.07#ibcon#read 4, iclass 16, count 0 2006.169.07:38:36.07#ibcon#about to read 5, iclass 16, count 0 2006.169.07:38:36.07#ibcon#read 5, iclass 16, count 0 2006.169.07:38:36.07#ibcon#about to read 6, iclass 16, count 0 2006.169.07:38:36.07#ibcon#read 6, iclass 16, count 0 2006.169.07:38:36.07#ibcon#end of sib2, iclass 16, count 0 2006.169.07:38:36.07#ibcon#*mode == 0, iclass 16, count 0 2006.169.07:38:36.07#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.169.07:38:36.07#ibcon#[25=USB\r\n] 2006.169.07:38:36.07#ibcon#*before write, iclass 16, count 0 2006.169.07:38:36.07#ibcon#enter sib2, iclass 16, count 0 2006.169.07:38:36.07#ibcon#flushed, iclass 16, count 0 2006.169.07:38:36.07#ibcon#about to write, iclass 16, count 0 2006.169.07:38:36.07#ibcon#wrote, iclass 16, count 0 2006.169.07:38:36.08#ibcon#about to read 3, iclass 16, count 0 2006.169.07:38:36.10#ibcon#read 3, iclass 16, count 0 2006.169.07:38:36.10#ibcon#about to read 4, iclass 16, count 0 2006.169.07:38:36.10#ibcon#read 4, iclass 16, count 0 2006.169.07:38:36.10#ibcon#about to read 5, iclass 16, count 0 2006.169.07:38:36.10#ibcon#read 5, iclass 16, count 0 2006.169.07:38:36.10#ibcon#about to read 6, iclass 16, count 0 2006.169.07:38:36.10#ibcon#read 6, iclass 16, count 0 2006.169.07:38:36.10#ibcon#end of sib2, iclass 16, count 0 2006.169.07:38:36.10#ibcon#*after write, iclass 16, count 0 2006.169.07:38:36.10#ibcon#*before return 0, iclass 16, count 0 2006.169.07:38:36.10#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.169.07:38:36.10#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.169.07:38:36.10#ibcon#about to clear, iclass 16 cls_cnt 0 2006.169.07:38:36.10#ibcon#cleared, iclass 16 cls_cnt 0 2006.169.07:38:36.11$vc4f8/valo=5,652.99 2006.169.07:38:36.11#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.169.07:38:36.11#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.169.07:38:36.11#ibcon#ireg 17 cls_cnt 0 2006.169.07:38:36.11#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:38:36.11#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:38:36.11#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:38:36.11#ibcon#enter wrdev, iclass 18, count 0 2006.169.07:38:36.11#ibcon#first serial, iclass 18, count 0 2006.169.07:38:36.11#ibcon#enter sib2, iclass 18, count 0 2006.169.07:38:36.11#ibcon#flushed, iclass 18, count 0 2006.169.07:38:36.11#ibcon#about to write, iclass 18, count 0 2006.169.07:38:36.11#ibcon#wrote, iclass 18, count 0 2006.169.07:38:36.11#ibcon#about to read 3, iclass 18, count 0 2006.169.07:38:36.12#ibcon#read 3, iclass 18, count 0 2006.169.07:38:36.12#ibcon#about to read 4, iclass 18, count 0 2006.169.07:38:36.12#ibcon#read 4, iclass 18, count 0 2006.169.07:38:36.12#ibcon#about to read 5, iclass 18, count 0 2006.169.07:38:36.12#ibcon#read 5, iclass 18, count 0 2006.169.07:38:36.12#ibcon#about to read 6, iclass 18, count 0 2006.169.07:38:36.12#ibcon#read 6, iclass 18, count 0 2006.169.07:38:36.12#ibcon#end of sib2, iclass 18, count 0 2006.169.07:38:36.12#ibcon#*mode == 0, iclass 18, count 0 2006.169.07:38:36.12#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.169.07:38:36.12#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.07:38:36.12#ibcon#*before write, iclass 18, count 0 2006.169.07:38:36.12#ibcon#enter sib2, iclass 18, count 0 2006.169.07:38:36.12#ibcon#flushed, iclass 18, count 0 2006.169.07:38:36.12#ibcon#about to write, iclass 18, count 0 2006.169.07:38:36.12#ibcon#wrote, iclass 18, count 0 2006.169.07:38:36.13#ibcon#about to read 3, iclass 18, count 0 2006.169.07:38:36.16#ibcon#read 3, iclass 18, count 0 2006.169.07:38:36.16#ibcon#about to read 4, iclass 18, count 0 2006.169.07:38:36.16#ibcon#read 4, iclass 18, count 0 2006.169.07:38:36.16#ibcon#about to read 5, iclass 18, count 0 2006.169.07:38:36.16#ibcon#read 5, iclass 18, count 0 2006.169.07:38:36.16#ibcon#about to read 6, iclass 18, count 0 2006.169.07:38:36.16#ibcon#read 6, iclass 18, count 0 2006.169.07:38:36.16#ibcon#end of sib2, iclass 18, count 0 2006.169.07:38:36.16#ibcon#*after write, iclass 18, count 0 2006.169.07:38:36.16#ibcon#*before return 0, iclass 18, count 0 2006.169.07:38:36.16#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:38:36.16#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:38:36.16#ibcon#about to clear, iclass 18 cls_cnt 0 2006.169.07:38:36.16#ibcon#cleared, iclass 18 cls_cnt 0 2006.169.07:38:36.17$vc4f8/va=5,7 2006.169.07:38:36.17#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.169.07:38:36.17#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.169.07:38:36.17#ibcon#ireg 11 cls_cnt 2 2006.169.07:38:36.17#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.169.07:38:36.21#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.169.07:38:36.21#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.169.07:38:36.21#ibcon#enter wrdev, iclass 20, count 2 2006.169.07:38:36.21#ibcon#first serial, iclass 20, count 2 2006.169.07:38:36.21#ibcon#enter sib2, iclass 20, count 2 2006.169.07:38:36.21#ibcon#flushed, iclass 20, count 2 2006.169.07:38:36.21#ibcon#about to write, iclass 20, count 2 2006.169.07:38:36.21#ibcon#wrote, iclass 20, count 2 2006.169.07:38:36.21#ibcon#about to read 3, iclass 20, count 2 2006.169.07:38:36.23#ibcon#read 3, iclass 20, count 2 2006.169.07:38:36.23#ibcon#about to read 4, iclass 20, count 2 2006.169.07:38:36.23#ibcon#read 4, iclass 20, count 2 2006.169.07:38:36.23#ibcon#about to read 5, iclass 20, count 2 2006.169.07:38:36.23#ibcon#read 5, iclass 20, count 2 2006.169.07:38:36.23#ibcon#about to read 6, iclass 20, count 2 2006.169.07:38:36.23#ibcon#read 6, iclass 20, count 2 2006.169.07:38:36.23#ibcon#end of sib2, iclass 20, count 2 2006.169.07:38:36.23#ibcon#*mode == 0, iclass 20, count 2 2006.169.07:38:36.23#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.169.07:38:36.23#ibcon#[25=AT05-07\r\n] 2006.169.07:38:36.23#ibcon#*before write, iclass 20, count 2 2006.169.07:38:36.23#ibcon#enter sib2, iclass 20, count 2 2006.169.07:38:36.23#ibcon#flushed, iclass 20, count 2 2006.169.07:38:36.24#ibcon#about to write, iclass 20, count 2 2006.169.07:38:36.24#ibcon#wrote, iclass 20, count 2 2006.169.07:38:36.24#ibcon#about to read 3, iclass 20, count 2 2006.169.07:38:36.26#ibcon#read 3, iclass 20, count 2 2006.169.07:38:36.26#ibcon#about to read 4, iclass 20, count 2 2006.169.07:38:36.26#ibcon#read 4, iclass 20, count 2 2006.169.07:38:36.26#ibcon#about to read 5, iclass 20, count 2 2006.169.07:38:36.26#ibcon#read 5, iclass 20, count 2 2006.169.07:38:36.26#ibcon#about to read 6, iclass 20, count 2 2006.169.07:38:36.26#ibcon#read 6, iclass 20, count 2 2006.169.07:38:36.26#ibcon#end of sib2, iclass 20, count 2 2006.169.07:38:36.26#ibcon#*after write, iclass 20, count 2 2006.169.07:38:36.26#ibcon#*before return 0, iclass 20, count 2 2006.169.07:38:36.26#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.169.07:38:36.26#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.169.07:38:36.27#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.169.07:38:36.27#ibcon#ireg 7 cls_cnt 0 2006.169.07:38:36.27#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.169.07:38:36.37#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.169.07:38:36.37#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.169.07:38:36.37#ibcon#enter wrdev, iclass 20, count 0 2006.169.07:38:36.37#ibcon#first serial, iclass 20, count 0 2006.169.07:38:36.37#ibcon#enter sib2, iclass 20, count 0 2006.169.07:38:36.37#ibcon#flushed, iclass 20, count 0 2006.169.07:38:36.37#ibcon#about to write, iclass 20, count 0 2006.169.07:38:36.37#ibcon#wrote, iclass 20, count 0 2006.169.07:38:36.37#ibcon#about to read 3, iclass 20, count 0 2006.169.07:38:36.39#ibcon#read 3, iclass 20, count 0 2006.169.07:38:36.39#ibcon#about to read 4, iclass 20, count 0 2006.169.07:38:36.39#ibcon#read 4, iclass 20, count 0 2006.169.07:38:36.39#ibcon#about to read 5, iclass 20, count 0 2006.169.07:38:36.39#ibcon#read 5, iclass 20, count 0 2006.169.07:38:36.39#ibcon#about to read 6, iclass 20, count 0 2006.169.07:38:36.39#ibcon#read 6, iclass 20, count 0 2006.169.07:38:36.39#ibcon#end of sib2, iclass 20, count 0 2006.169.07:38:36.39#ibcon#*mode == 0, iclass 20, count 0 2006.169.07:38:36.39#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.169.07:38:36.39#ibcon#[25=USB\r\n] 2006.169.07:38:36.39#ibcon#*before write, iclass 20, count 0 2006.169.07:38:36.39#ibcon#enter sib2, iclass 20, count 0 2006.169.07:38:36.39#ibcon#flushed, iclass 20, count 0 2006.169.07:38:36.39#ibcon#about to write, iclass 20, count 0 2006.169.07:38:36.39#ibcon#wrote, iclass 20, count 0 2006.169.07:38:36.40#ibcon#about to read 3, iclass 20, count 0 2006.169.07:38:36.42#ibcon#read 3, iclass 20, count 0 2006.169.07:38:36.42#ibcon#about to read 4, iclass 20, count 0 2006.169.07:38:36.42#ibcon#read 4, iclass 20, count 0 2006.169.07:38:36.42#ibcon#about to read 5, iclass 20, count 0 2006.169.07:38:36.42#ibcon#read 5, iclass 20, count 0 2006.169.07:38:36.42#ibcon#about to read 6, iclass 20, count 0 2006.169.07:38:36.42#ibcon#read 6, iclass 20, count 0 2006.169.07:38:36.42#ibcon#end of sib2, iclass 20, count 0 2006.169.07:38:36.42#ibcon#*after write, iclass 20, count 0 2006.169.07:38:36.42#ibcon#*before return 0, iclass 20, count 0 2006.169.07:38:36.42#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.169.07:38:36.42#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.169.07:38:36.42#ibcon#about to clear, iclass 20 cls_cnt 0 2006.169.07:38:36.42#ibcon#cleared, iclass 20 cls_cnt 0 2006.169.07:38:36.43$vc4f8/valo=6,772.99 2006.169.07:38:36.43#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.169.07:38:36.43#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.169.07:38:36.43#ibcon#ireg 17 cls_cnt 0 2006.169.07:38:36.43#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:38:36.43#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:38:36.43#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:38:36.43#ibcon#enter wrdev, iclass 22, count 0 2006.169.07:38:36.43#ibcon#first serial, iclass 22, count 0 2006.169.07:38:36.43#ibcon#enter sib2, iclass 22, count 0 2006.169.07:38:36.43#ibcon#flushed, iclass 22, count 0 2006.169.07:38:36.43#ibcon#about to write, iclass 22, count 0 2006.169.07:38:36.43#ibcon#wrote, iclass 22, count 0 2006.169.07:38:36.43#ibcon#about to read 3, iclass 22, count 0 2006.169.07:38:36.44#ibcon#read 3, iclass 22, count 0 2006.169.07:38:36.44#ibcon#about to read 4, iclass 22, count 0 2006.169.07:38:36.44#ibcon#read 4, iclass 22, count 0 2006.169.07:38:36.44#ibcon#about to read 5, iclass 22, count 0 2006.169.07:38:36.44#ibcon#read 5, iclass 22, count 0 2006.169.07:38:36.44#ibcon#about to read 6, iclass 22, count 0 2006.169.07:38:36.44#ibcon#read 6, iclass 22, count 0 2006.169.07:38:36.44#ibcon#end of sib2, iclass 22, count 0 2006.169.07:38:36.44#ibcon#*mode == 0, iclass 22, count 0 2006.169.07:38:36.44#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.169.07:38:36.44#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.07:38:36.44#ibcon#*before write, iclass 22, count 0 2006.169.07:38:36.44#ibcon#enter sib2, iclass 22, count 0 2006.169.07:38:36.44#ibcon#flushed, iclass 22, count 0 2006.169.07:38:36.44#ibcon#about to write, iclass 22, count 0 2006.169.07:38:36.45#ibcon#wrote, iclass 22, count 0 2006.169.07:38:36.45#ibcon#about to read 3, iclass 22, count 0 2006.169.07:38:36.48#ibcon#read 3, iclass 22, count 0 2006.169.07:38:36.48#ibcon#about to read 4, iclass 22, count 0 2006.169.07:38:36.48#ibcon#read 4, iclass 22, count 0 2006.169.07:38:36.48#ibcon#about to read 5, iclass 22, count 0 2006.169.07:38:36.48#ibcon#read 5, iclass 22, count 0 2006.169.07:38:36.48#ibcon#about to read 6, iclass 22, count 0 2006.169.07:38:36.48#ibcon#read 6, iclass 22, count 0 2006.169.07:38:36.48#ibcon#end of sib2, iclass 22, count 0 2006.169.07:38:36.48#ibcon#*after write, iclass 22, count 0 2006.169.07:38:36.48#ibcon#*before return 0, iclass 22, count 0 2006.169.07:38:36.48#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:38:36.48#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:38:36.48#ibcon#about to clear, iclass 22 cls_cnt 0 2006.169.07:38:36.48#ibcon#cleared, iclass 22 cls_cnt 0 2006.169.07:38:36.49$vc4f8/va=6,6 2006.169.07:38:36.49#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.169.07:38:36.49#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.169.07:38:36.49#ibcon#ireg 11 cls_cnt 2 2006.169.07:38:36.49#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.169.07:38:36.53#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.169.07:38:36.53#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.169.07:38:36.53#ibcon#enter wrdev, iclass 24, count 2 2006.169.07:38:36.53#ibcon#first serial, iclass 24, count 2 2006.169.07:38:36.53#ibcon#enter sib2, iclass 24, count 2 2006.169.07:38:36.53#ibcon#flushed, iclass 24, count 2 2006.169.07:38:36.53#ibcon#about to write, iclass 24, count 2 2006.169.07:38:36.53#ibcon#wrote, iclass 24, count 2 2006.169.07:38:36.53#ibcon#about to read 3, iclass 24, count 2 2006.169.07:38:36.55#ibcon#read 3, iclass 24, count 2 2006.169.07:38:36.55#ibcon#about to read 4, iclass 24, count 2 2006.169.07:38:36.55#ibcon#read 4, iclass 24, count 2 2006.169.07:38:36.55#ibcon#about to read 5, iclass 24, count 2 2006.169.07:38:36.55#ibcon#read 5, iclass 24, count 2 2006.169.07:38:36.55#ibcon#about to read 6, iclass 24, count 2 2006.169.07:38:36.55#ibcon#read 6, iclass 24, count 2 2006.169.07:38:36.55#ibcon#end of sib2, iclass 24, count 2 2006.169.07:38:36.55#ibcon#*mode == 0, iclass 24, count 2 2006.169.07:38:36.55#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.169.07:38:36.55#ibcon#[25=AT06-06\r\n] 2006.169.07:38:36.55#ibcon#*before write, iclass 24, count 2 2006.169.07:38:36.55#ibcon#enter sib2, iclass 24, count 2 2006.169.07:38:36.55#ibcon#flushed, iclass 24, count 2 2006.169.07:38:36.55#ibcon#about to write, iclass 24, count 2 2006.169.07:38:36.55#ibcon#wrote, iclass 24, count 2 2006.169.07:38:36.56#ibcon#about to read 3, iclass 24, count 2 2006.169.07:38:36.58#ibcon#read 3, iclass 24, count 2 2006.169.07:38:36.58#ibcon#about to read 4, iclass 24, count 2 2006.169.07:38:36.58#ibcon#read 4, iclass 24, count 2 2006.169.07:38:36.58#ibcon#about to read 5, iclass 24, count 2 2006.169.07:38:36.58#ibcon#read 5, iclass 24, count 2 2006.169.07:38:36.58#ibcon#about to read 6, iclass 24, count 2 2006.169.07:38:36.58#ibcon#read 6, iclass 24, count 2 2006.169.07:38:36.58#ibcon#end of sib2, iclass 24, count 2 2006.169.07:38:36.58#ibcon#*after write, iclass 24, count 2 2006.169.07:38:36.58#ibcon#*before return 0, iclass 24, count 2 2006.169.07:38:36.58#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.169.07:38:36.58#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.169.07:38:36.58#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.169.07:38:36.58#ibcon#ireg 7 cls_cnt 0 2006.169.07:38:36.58#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.169.07:38:36.70#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.169.07:38:36.70#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.169.07:38:36.70#ibcon#enter wrdev, iclass 24, count 0 2006.169.07:38:36.70#ibcon#first serial, iclass 24, count 0 2006.169.07:38:36.70#ibcon#enter sib2, iclass 24, count 0 2006.169.07:38:36.70#ibcon#flushed, iclass 24, count 0 2006.169.07:38:36.70#ibcon#about to write, iclass 24, count 0 2006.169.07:38:36.70#ibcon#wrote, iclass 24, count 0 2006.169.07:38:36.70#ibcon#about to read 3, iclass 24, count 0 2006.169.07:38:36.72#ibcon#read 3, iclass 24, count 0 2006.169.07:38:36.72#ibcon#about to read 4, iclass 24, count 0 2006.169.07:38:36.72#ibcon#read 4, iclass 24, count 0 2006.169.07:38:36.72#ibcon#about to read 5, iclass 24, count 0 2006.169.07:38:36.72#ibcon#read 5, iclass 24, count 0 2006.169.07:38:36.72#ibcon#about to read 6, iclass 24, count 0 2006.169.07:38:36.72#ibcon#read 6, iclass 24, count 0 2006.169.07:38:36.72#ibcon#end of sib2, iclass 24, count 0 2006.169.07:38:36.72#ibcon#*mode == 0, iclass 24, count 0 2006.169.07:38:36.72#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.169.07:38:36.72#ibcon#[25=USB\r\n] 2006.169.07:38:36.72#ibcon#*before write, iclass 24, count 0 2006.169.07:38:36.72#ibcon#enter sib2, iclass 24, count 0 2006.169.07:38:36.72#ibcon#flushed, iclass 24, count 0 2006.169.07:38:36.72#ibcon#about to write, iclass 24, count 0 2006.169.07:38:36.72#ibcon#wrote, iclass 24, count 0 2006.169.07:38:36.73#ibcon#about to read 3, iclass 24, count 0 2006.169.07:38:36.75#ibcon#read 3, iclass 24, count 0 2006.169.07:38:36.75#ibcon#about to read 4, iclass 24, count 0 2006.169.07:38:36.75#ibcon#read 4, iclass 24, count 0 2006.169.07:38:36.75#ibcon#about to read 5, iclass 24, count 0 2006.169.07:38:36.75#ibcon#read 5, iclass 24, count 0 2006.169.07:38:36.75#ibcon#about to read 6, iclass 24, count 0 2006.169.07:38:36.75#ibcon#read 6, iclass 24, count 0 2006.169.07:38:36.75#ibcon#end of sib2, iclass 24, count 0 2006.169.07:38:36.75#ibcon#*after write, iclass 24, count 0 2006.169.07:38:36.75#ibcon#*before return 0, iclass 24, count 0 2006.169.07:38:36.75#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.169.07:38:36.75#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.169.07:38:36.75#ibcon#about to clear, iclass 24 cls_cnt 0 2006.169.07:38:36.75#ibcon#cleared, iclass 24 cls_cnt 0 2006.169.07:38:36.76$vc4f8/valo=7,832.99 2006.169.07:38:36.76#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.169.07:38:36.76#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.169.07:38:36.76#ibcon#ireg 17 cls_cnt 0 2006.169.07:38:36.76#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:38:36.76#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:38:36.76#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:38:36.76#ibcon#enter wrdev, iclass 26, count 0 2006.169.07:38:36.76#ibcon#first serial, iclass 26, count 0 2006.169.07:38:36.76#ibcon#enter sib2, iclass 26, count 0 2006.169.07:38:36.76#ibcon#flushed, iclass 26, count 0 2006.169.07:38:36.76#ibcon#about to write, iclass 26, count 0 2006.169.07:38:36.76#ibcon#wrote, iclass 26, count 0 2006.169.07:38:36.76#ibcon#about to read 3, iclass 26, count 0 2006.169.07:38:36.77#ibcon#read 3, iclass 26, count 0 2006.169.07:38:36.77#ibcon#about to read 4, iclass 26, count 0 2006.169.07:38:36.77#ibcon#read 4, iclass 26, count 0 2006.169.07:38:36.77#ibcon#about to read 5, iclass 26, count 0 2006.169.07:38:36.77#ibcon#read 5, iclass 26, count 0 2006.169.07:38:36.77#ibcon#about to read 6, iclass 26, count 0 2006.169.07:38:36.77#ibcon#read 6, iclass 26, count 0 2006.169.07:38:36.77#ibcon#end of sib2, iclass 26, count 0 2006.169.07:38:36.77#ibcon#*mode == 0, iclass 26, count 0 2006.169.07:38:36.77#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.169.07:38:36.77#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.07:38:36.77#ibcon#*before write, iclass 26, count 0 2006.169.07:38:36.77#ibcon#enter sib2, iclass 26, count 0 2006.169.07:38:36.77#ibcon#flushed, iclass 26, count 0 2006.169.07:38:36.77#ibcon#about to write, iclass 26, count 0 2006.169.07:38:36.77#ibcon#wrote, iclass 26, count 0 2006.169.07:38:36.78#ibcon#about to read 3, iclass 26, count 0 2006.169.07:38:36.81#ibcon#read 3, iclass 26, count 0 2006.169.07:38:36.81#ibcon#about to read 4, iclass 26, count 0 2006.169.07:38:36.81#ibcon#read 4, iclass 26, count 0 2006.169.07:38:36.81#ibcon#about to read 5, iclass 26, count 0 2006.169.07:38:36.81#ibcon#read 5, iclass 26, count 0 2006.169.07:38:36.81#ibcon#about to read 6, iclass 26, count 0 2006.169.07:38:36.81#ibcon#read 6, iclass 26, count 0 2006.169.07:38:36.81#ibcon#end of sib2, iclass 26, count 0 2006.169.07:38:36.81#ibcon#*after write, iclass 26, count 0 2006.169.07:38:36.81#ibcon#*before return 0, iclass 26, count 0 2006.169.07:38:36.81#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:38:36.81#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:38:36.81#ibcon#about to clear, iclass 26 cls_cnt 0 2006.169.07:38:36.81#ibcon#cleared, iclass 26 cls_cnt 0 2006.169.07:38:36.82$vc4f8/va=7,6 2006.169.07:38:36.82#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.169.07:38:36.82#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.169.07:38:36.82#ibcon#ireg 11 cls_cnt 2 2006.169.07:38:36.82#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.169.07:38:36.86#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.169.07:38:36.86#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.169.07:38:36.86#ibcon#enter wrdev, iclass 28, count 2 2006.169.07:38:36.86#ibcon#first serial, iclass 28, count 2 2006.169.07:38:36.86#ibcon#enter sib2, iclass 28, count 2 2006.169.07:38:36.86#ibcon#flushed, iclass 28, count 2 2006.169.07:38:36.86#ibcon#about to write, iclass 28, count 2 2006.169.07:38:36.86#ibcon#wrote, iclass 28, count 2 2006.169.07:38:36.86#ibcon#about to read 3, iclass 28, count 2 2006.169.07:38:36.88#ibcon#read 3, iclass 28, count 2 2006.169.07:38:36.88#ibcon#about to read 4, iclass 28, count 2 2006.169.07:38:36.88#ibcon#read 4, iclass 28, count 2 2006.169.07:38:36.88#ibcon#about to read 5, iclass 28, count 2 2006.169.07:38:36.88#ibcon#read 5, iclass 28, count 2 2006.169.07:38:36.88#ibcon#about to read 6, iclass 28, count 2 2006.169.07:38:36.88#ibcon#read 6, iclass 28, count 2 2006.169.07:38:36.88#ibcon#end of sib2, iclass 28, count 2 2006.169.07:38:36.88#ibcon#*mode == 0, iclass 28, count 2 2006.169.07:38:36.88#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.169.07:38:36.88#ibcon#[25=AT07-06\r\n] 2006.169.07:38:36.88#ibcon#*before write, iclass 28, count 2 2006.169.07:38:36.88#ibcon#enter sib2, iclass 28, count 2 2006.169.07:38:36.88#ibcon#flushed, iclass 28, count 2 2006.169.07:38:36.88#ibcon#about to write, iclass 28, count 2 2006.169.07:38:36.88#ibcon#wrote, iclass 28, count 2 2006.169.07:38:36.89#ibcon#about to read 3, iclass 28, count 2 2006.169.07:38:36.91#ibcon#read 3, iclass 28, count 2 2006.169.07:38:36.91#ibcon#about to read 4, iclass 28, count 2 2006.169.07:38:36.91#ibcon#read 4, iclass 28, count 2 2006.169.07:38:36.91#ibcon#about to read 5, iclass 28, count 2 2006.169.07:38:36.91#ibcon#read 5, iclass 28, count 2 2006.169.07:38:36.91#ibcon#about to read 6, iclass 28, count 2 2006.169.07:38:36.91#ibcon#read 6, iclass 28, count 2 2006.169.07:38:36.91#ibcon#end of sib2, iclass 28, count 2 2006.169.07:38:36.91#ibcon#*after write, iclass 28, count 2 2006.169.07:38:36.91#ibcon#*before return 0, iclass 28, count 2 2006.169.07:38:36.91#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.169.07:38:36.91#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.169.07:38:36.91#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.169.07:38:36.91#ibcon#ireg 7 cls_cnt 0 2006.169.07:38:36.91#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.169.07:38:37.03#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.169.07:38:37.03#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.169.07:38:37.03#ibcon#enter wrdev, iclass 28, count 0 2006.169.07:38:37.03#ibcon#first serial, iclass 28, count 0 2006.169.07:38:37.03#ibcon#enter sib2, iclass 28, count 0 2006.169.07:38:37.03#ibcon#flushed, iclass 28, count 0 2006.169.07:38:37.03#ibcon#about to write, iclass 28, count 0 2006.169.07:38:37.03#ibcon#wrote, iclass 28, count 0 2006.169.07:38:37.03#ibcon#about to read 3, iclass 28, count 0 2006.169.07:38:37.05#ibcon#read 3, iclass 28, count 0 2006.169.07:38:37.05#ibcon#about to read 4, iclass 28, count 0 2006.169.07:38:37.05#ibcon#read 4, iclass 28, count 0 2006.169.07:38:37.05#ibcon#about to read 5, iclass 28, count 0 2006.169.07:38:37.05#ibcon#read 5, iclass 28, count 0 2006.169.07:38:37.05#ibcon#about to read 6, iclass 28, count 0 2006.169.07:38:37.05#ibcon#read 6, iclass 28, count 0 2006.169.07:38:37.05#ibcon#end of sib2, iclass 28, count 0 2006.169.07:38:37.05#ibcon#*mode == 0, iclass 28, count 0 2006.169.07:38:37.05#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.169.07:38:37.05#ibcon#[25=USB\r\n] 2006.169.07:38:37.05#ibcon#*before write, iclass 28, count 0 2006.169.07:38:37.05#ibcon#enter sib2, iclass 28, count 0 2006.169.07:38:37.05#ibcon#flushed, iclass 28, count 0 2006.169.07:38:37.05#ibcon#about to write, iclass 28, count 0 2006.169.07:38:37.05#ibcon#wrote, iclass 28, count 0 2006.169.07:38:37.06#ibcon#about to read 3, iclass 28, count 0 2006.169.07:38:37.08#ibcon#read 3, iclass 28, count 0 2006.169.07:38:37.08#ibcon#about to read 4, iclass 28, count 0 2006.169.07:38:37.08#ibcon#read 4, iclass 28, count 0 2006.169.07:38:37.08#ibcon#about to read 5, iclass 28, count 0 2006.169.07:38:37.08#ibcon#read 5, iclass 28, count 0 2006.169.07:38:37.08#ibcon#about to read 6, iclass 28, count 0 2006.169.07:38:37.08#ibcon#read 6, iclass 28, count 0 2006.169.07:38:37.08#ibcon#end of sib2, iclass 28, count 0 2006.169.07:38:37.08#ibcon#*after write, iclass 28, count 0 2006.169.07:38:37.08#ibcon#*before return 0, iclass 28, count 0 2006.169.07:38:37.08#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.169.07:38:37.08#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.169.07:38:37.08#ibcon#about to clear, iclass 28 cls_cnt 0 2006.169.07:38:37.08#ibcon#cleared, iclass 28 cls_cnt 0 2006.169.07:38:37.09$vc4f8/valo=8,852.99 2006.169.07:38:37.09#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.169.07:38:37.09#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.169.07:38:37.09#ibcon#ireg 17 cls_cnt 0 2006.169.07:38:37.09#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:38:37.09#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:38:37.09#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:38:37.09#ibcon#enter wrdev, iclass 30, count 0 2006.169.07:38:37.09#ibcon#first serial, iclass 30, count 0 2006.169.07:38:37.09#ibcon#enter sib2, iclass 30, count 0 2006.169.07:38:37.09#ibcon#flushed, iclass 30, count 0 2006.169.07:38:37.09#ibcon#about to write, iclass 30, count 0 2006.169.07:38:37.09#ibcon#wrote, iclass 30, count 0 2006.169.07:38:37.09#ibcon#about to read 3, iclass 30, count 0 2006.169.07:38:37.10#ibcon#read 3, iclass 30, count 0 2006.169.07:38:37.10#ibcon#about to read 4, iclass 30, count 0 2006.169.07:38:37.10#ibcon#read 4, iclass 30, count 0 2006.169.07:38:37.10#ibcon#about to read 5, iclass 30, count 0 2006.169.07:38:37.10#ibcon#read 5, iclass 30, count 0 2006.169.07:38:37.10#ibcon#about to read 6, iclass 30, count 0 2006.169.07:38:37.10#ibcon#read 6, iclass 30, count 0 2006.169.07:38:37.10#ibcon#end of sib2, iclass 30, count 0 2006.169.07:38:37.10#ibcon#*mode == 0, iclass 30, count 0 2006.169.07:38:37.10#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.169.07:38:37.10#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.07:38:37.10#ibcon#*before write, iclass 30, count 0 2006.169.07:38:37.10#ibcon#enter sib2, iclass 30, count 0 2006.169.07:38:37.10#ibcon#flushed, iclass 30, count 0 2006.169.07:38:37.10#ibcon#about to write, iclass 30, count 0 2006.169.07:38:37.10#ibcon#wrote, iclass 30, count 0 2006.169.07:38:37.11#ibcon#about to read 3, iclass 30, count 0 2006.169.07:38:37.15#ibcon#read 3, iclass 30, count 0 2006.169.07:38:37.15#ibcon#about to read 4, iclass 30, count 0 2006.169.07:38:37.15#ibcon#read 4, iclass 30, count 0 2006.169.07:38:37.15#ibcon#about to read 5, iclass 30, count 0 2006.169.07:38:37.15#ibcon#read 5, iclass 30, count 0 2006.169.07:38:37.15#ibcon#about to read 6, iclass 30, count 0 2006.169.07:38:37.15#ibcon#read 6, iclass 30, count 0 2006.169.07:38:37.15#ibcon#end of sib2, iclass 30, count 0 2006.169.07:38:37.15#ibcon#*after write, iclass 30, count 0 2006.169.07:38:37.15#ibcon#*before return 0, iclass 30, count 0 2006.169.07:38:37.15#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:38:37.15#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:38:37.15#ibcon#about to clear, iclass 30 cls_cnt 0 2006.169.07:38:37.15#ibcon#cleared, iclass 30 cls_cnt 0 2006.169.07:38:37.15$vc4f8/va=8,7 2006.169.07:38:37.15#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.169.07:38:37.15#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.169.07:38:37.15#ibcon#ireg 11 cls_cnt 2 2006.169.07:38:37.15#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:38:37.19#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:38:37.19#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:38:37.19#ibcon#enter wrdev, iclass 32, count 2 2006.169.07:38:37.19#ibcon#first serial, iclass 32, count 2 2006.169.07:38:37.19#ibcon#enter sib2, iclass 32, count 2 2006.169.07:38:37.19#ibcon#flushed, iclass 32, count 2 2006.169.07:38:37.19#ibcon#about to write, iclass 32, count 2 2006.169.07:38:37.19#ibcon#wrote, iclass 32, count 2 2006.169.07:38:37.19#ibcon#about to read 3, iclass 32, count 2 2006.169.07:38:37.21#ibcon#read 3, iclass 32, count 2 2006.169.07:38:37.21#ibcon#about to read 4, iclass 32, count 2 2006.169.07:38:37.21#ibcon#read 4, iclass 32, count 2 2006.169.07:38:37.21#ibcon#about to read 5, iclass 32, count 2 2006.169.07:38:37.21#ibcon#read 5, iclass 32, count 2 2006.169.07:38:37.21#ibcon#about to read 6, iclass 32, count 2 2006.169.07:38:37.21#ibcon#read 6, iclass 32, count 2 2006.169.07:38:37.21#ibcon#end of sib2, iclass 32, count 2 2006.169.07:38:37.21#ibcon#*mode == 0, iclass 32, count 2 2006.169.07:38:37.21#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.169.07:38:37.21#ibcon#[25=AT08-07\r\n] 2006.169.07:38:37.21#ibcon#*before write, iclass 32, count 2 2006.169.07:38:37.21#ibcon#enter sib2, iclass 32, count 2 2006.169.07:38:37.21#ibcon#flushed, iclass 32, count 2 2006.169.07:38:37.21#ibcon#about to write, iclass 32, count 2 2006.169.07:38:37.21#ibcon#wrote, iclass 32, count 2 2006.169.07:38:37.22#ibcon#about to read 3, iclass 32, count 2 2006.169.07:38:37.24#ibcon#read 3, iclass 32, count 2 2006.169.07:38:37.24#ibcon#about to read 4, iclass 32, count 2 2006.169.07:38:37.24#ibcon#read 4, iclass 32, count 2 2006.169.07:38:37.24#ibcon#about to read 5, iclass 32, count 2 2006.169.07:38:37.24#ibcon#read 5, iclass 32, count 2 2006.169.07:38:37.24#ibcon#about to read 6, iclass 32, count 2 2006.169.07:38:37.24#ibcon#read 6, iclass 32, count 2 2006.169.07:38:37.24#ibcon#end of sib2, iclass 32, count 2 2006.169.07:38:37.24#ibcon#*after write, iclass 32, count 2 2006.169.07:38:37.24#ibcon#*before return 0, iclass 32, count 2 2006.169.07:38:37.24#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:38:37.24#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:38:37.24#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.169.07:38:37.25#ibcon#ireg 7 cls_cnt 0 2006.169.07:38:37.25#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:38:37.35#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:38:37.35#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:38:37.35#ibcon#enter wrdev, iclass 32, count 0 2006.169.07:38:37.35#ibcon#first serial, iclass 32, count 0 2006.169.07:38:37.35#ibcon#enter sib2, iclass 32, count 0 2006.169.07:38:37.35#ibcon#flushed, iclass 32, count 0 2006.169.07:38:37.35#ibcon#about to write, iclass 32, count 0 2006.169.07:38:37.35#ibcon#wrote, iclass 32, count 0 2006.169.07:38:37.35#ibcon#about to read 3, iclass 32, count 0 2006.169.07:38:37.37#ibcon#read 3, iclass 32, count 0 2006.169.07:38:37.37#ibcon#about to read 4, iclass 32, count 0 2006.169.07:38:37.37#ibcon#read 4, iclass 32, count 0 2006.169.07:38:37.37#ibcon#about to read 5, iclass 32, count 0 2006.169.07:38:37.37#ibcon#read 5, iclass 32, count 0 2006.169.07:38:37.37#ibcon#about to read 6, iclass 32, count 0 2006.169.07:38:37.37#ibcon#read 6, iclass 32, count 0 2006.169.07:38:37.37#ibcon#end of sib2, iclass 32, count 0 2006.169.07:38:37.37#ibcon#*mode == 0, iclass 32, count 0 2006.169.07:38:37.37#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.169.07:38:37.37#ibcon#[25=USB\r\n] 2006.169.07:38:37.37#ibcon#*before write, iclass 32, count 0 2006.169.07:38:37.37#ibcon#enter sib2, iclass 32, count 0 2006.169.07:38:37.37#ibcon#flushed, iclass 32, count 0 2006.169.07:38:37.37#ibcon#about to write, iclass 32, count 0 2006.169.07:38:37.37#ibcon#wrote, iclass 32, count 0 2006.169.07:38:37.38#ibcon#about to read 3, iclass 32, count 0 2006.169.07:38:37.40#ibcon#read 3, iclass 32, count 0 2006.169.07:38:37.40#ibcon#about to read 4, iclass 32, count 0 2006.169.07:38:37.40#ibcon#read 4, iclass 32, count 0 2006.169.07:38:37.40#ibcon#about to read 5, iclass 32, count 0 2006.169.07:38:37.40#ibcon#read 5, iclass 32, count 0 2006.169.07:38:37.40#ibcon#about to read 6, iclass 32, count 0 2006.169.07:38:37.40#ibcon#read 6, iclass 32, count 0 2006.169.07:38:37.40#ibcon#end of sib2, iclass 32, count 0 2006.169.07:38:37.40#ibcon#*after write, iclass 32, count 0 2006.169.07:38:37.40#ibcon#*before return 0, iclass 32, count 0 2006.169.07:38:37.40#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:38:37.40#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:38:37.40#ibcon#about to clear, iclass 32 cls_cnt 0 2006.169.07:38:37.40#ibcon#cleared, iclass 32 cls_cnt 0 2006.169.07:38:37.41$vc4f8/vblo=1,632.99 2006.169.07:38:37.41#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.169.07:38:37.41#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.169.07:38:37.41#ibcon#ireg 17 cls_cnt 0 2006.169.07:38:37.41#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:38:37.41#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:38:37.41#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:38:37.41#ibcon#enter wrdev, iclass 34, count 0 2006.169.07:38:37.41#ibcon#first serial, iclass 34, count 0 2006.169.07:38:37.41#ibcon#enter sib2, iclass 34, count 0 2006.169.07:38:37.41#ibcon#flushed, iclass 34, count 0 2006.169.07:38:37.41#ibcon#about to write, iclass 34, count 0 2006.169.07:38:37.41#ibcon#wrote, iclass 34, count 0 2006.169.07:38:37.41#ibcon#about to read 3, iclass 34, count 0 2006.169.07:38:37.42#ibcon#read 3, iclass 34, count 0 2006.169.07:38:37.42#ibcon#about to read 4, iclass 34, count 0 2006.169.07:38:37.42#ibcon#read 4, iclass 34, count 0 2006.169.07:38:37.42#ibcon#about to read 5, iclass 34, count 0 2006.169.07:38:37.42#ibcon#read 5, iclass 34, count 0 2006.169.07:38:37.42#ibcon#about to read 6, iclass 34, count 0 2006.169.07:38:37.42#ibcon#read 6, iclass 34, count 0 2006.169.07:38:37.42#ibcon#end of sib2, iclass 34, count 0 2006.169.07:38:37.42#ibcon#*mode == 0, iclass 34, count 0 2006.169.07:38:37.42#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.169.07:38:37.42#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.07:38:37.42#ibcon#*before write, iclass 34, count 0 2006.169.07:38:37.42#ibcon#enter sib2, iclass 34, count 0 2006.169.07:38:37.42#ibcon#flushed, iclass 34, count 0 2006.169.07:38:37.42#ibcon#about to write, iclass 34, count 0 2006.169.07:38:37.42#ibcon#wrote, iclass 34, count 0 2006.169.07:38:37.43#ibcon#about to read 3, iclass 34, count 0 2006.169.07:38:37.46#ibcon#read 3, iclass 34, count 0 2006.169.07:38:37.46#ibcon#about to read 4, iclass 34, count 0 2006.169.07:38:37.46#ibcon#read 4, iclass 34, count 0 2006.169.07:38:37.46#ibcon#about to read 5, iclass 34, count 0 2006.169.07:38:37.46#ibcon#read 5, iclass 34, count 0 2006.169.07:38:37.46#ibcon#about to read 6, iclass 34, count 0 2006.169.07:38:37.46#ibcon#read 6, iclass 34, count 0 2006.169.07:38:37.46#ibcon#end of sib2, iclass 34, count 0 2006.169.07:38:37.46#ibcon#*after write, iclass 34, count 0 2006.169.07:38:37.46#ibcon#*before return 0, iclass 34, count 0 2006.169.07:38:37.46#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:38:37.46#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:38:37.46#ibcon#about to clear, iclass 34 cls_cnt 0 2006.169.07:38:37.46#ibcon#cleared, iclass 34 cls_cnt 0 2006.169.07:38:37.47$vc4f8/vb=1,4 2006.169.07:38:37.47#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.169.07:38:37.47#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.169.07:38:37.47#ibcon#ireg 11 cls_cnt 2 2006.169.07:38:37.47#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.169.07:38:37.47#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.169.07:38:37.47#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.169.07:38:37.47#ibcon#enter wrdev, iclass 36, count 2 2006.169.07:38:37.47#ibcon#first serial, iclass 36, count 2 2006.169.07:38:37.47#ibcon#enter sib2, iclass 36, count 2 2006.169.07:38:37.47#ibcon#flushed, iclass 36, count 2 2006.169.07:38:37.47#ibcon#about to write, iclass 36, count 2 2006.169.07:38:37.47#ibcon#wrote, iclass 36, count 2 2006.169.07:38:37.47#ibcon#about to read 3, iclass 36, count 2 2006.169.07:38:37.48#ibcon#read 3, iclass 36, count 2 2006.169.07:38:37.48#ibcon#about to read 4, iclass 36, count 2 2006.169.07:38:37.48#ibcon#read 4, iclass 36, count 2 2006.169.07:38:37.48#ibcon#about to read 5, iclass 36, count 2 2006.169.07:38:37.48#ibcon#read 5, iclass 36, count 2 2006.169.07:38:37.48#ibcon#about to read 6, iclass 36, count 2 2006.169.07:38:37.48#ibcon#read 6, iclass 36, count 2 2006.169.07:38:37.48#ibcon#end of sib2, iclass 36, count 2 2006.169.07:38:37.48#ibcon#*mode == 0, iclass 36, count 2 2006.169.07:38:37.48#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.169.07:38:37.48#ibcon#[27=AT01-04\r\n] 2006.169.07:38:37.48#ibcon#*before write, iclass 36, count 2 2006.169.07:38:37.48#ibcon#enter sib2, iclass 36, count 2 2006.169.07:38:37.48#ibcon#flushed, iclass 36, count 2 2006.169.07:38:37.48#ibcon#about to write, iclass 36, count 2 2006.169.07:38:37.48#ibcon#wrote, iclass 36, count 2 2006.169.07:38:37.49#ibcon#about to read 3, iclass 36, count 2 2006.169.07:38:37.51#ibcon#read 3, iclass 36, count 2 2006.169.07:38:37.51#ibcon#about to read 4, iclass 36, count 2 2006.169.07:38:37.51#ibcon#read 4, iclass 36, count 2 2006.169.07:38:37.51#ibcon#about to read 5, iclass 36, count 2 2006.169.07:38:37.51#ibcon#read 5, iclass 36, count 2 2006.169.07:38:37.51#ibcon#about to read 6, iclass 36, count 2 2006.169.07:38:37.51#ibcon#read 6, iclass 36, count 2 2006.169.07:38:37.51#ibcon#end of sib2, iclass 36, count 2 2006.169.07:38:37.51#ibcon#*after write, iclass 36, count 2 2006.169.07:38:37.51#ibcon#*before return 0, iclass 36, count 2 2006.169.07:38:37.51#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.169.07:38:37.51#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.169.07:38:37.51#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.169.07:38:37.51#ibcon#ireg 7 cls_cnt 0 2006.169.07:38:37.51#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.169.07:38:37.63#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.169.07:38:37.63#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.169.07:38:37.63#ibcon#enter wrdev, iclass 36, count 0 2006.169.07:38:37.63#ibcon#first serial, iclass 36, count 0 2006.169.07:38:37.63#ibcon#enter sib2, iclass 36, count 0 2006.169.07:38:37.63#ibcon#flushed, iclass 36, count 0 2006.169.07:38:37.63#ibcon#about to write, iclass 36, count 0 2006.169.07:38:37.63#ibcon#wrote, iclass 36, count 0 2006.169.07:38:37.63#ibcon#about to read 3, iclass 36, count 0 2006.169.07:38:37.65#ibcon#read 3, iclass 36, count 0 2006.169.07:38:37.65#ibcon#about to read 4, iclass 36, count 0 2006.169.07:38:37.65#ibcon#read 4, iclass 36, count 0 2006.169.07:38:37.65#ibcon#about to read 5, iclass 36, count 0 2006.169.07:38:37.65#ibcon#read 5, iclass 36, count 0 2006.169.07:38:37.65#ibcon#about to read 6, iclass 36, count 0 2006.169.07:38:37.65#ibcon#read 6, iclass 36, count 0 2006.169.07:38:37.65#ibcon#end of sib2, iclass 36, count 0 2006.169.07:38:37.65#ibcon#*mode == 0, iclass 36, count 0 2006.169.07:38:37.65#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.169.07:38:37.65#ibcon#[27=USB\r\n] 2006.169.07:38:37.65#ibcon#*before write, iclass 36, count 0 2006.169.07:38:37.65#ibcon#enter sib2, iclass 36, count 0 2006.169.07:38:37.65#ibcon#flushed, iclass 36, count 0 2006.169.07:38:37.65#ibcon#about to write, iclass 36, count 0 2006.169.07:38:37.65#ibcon#wrote, iclass 36, count 0 2006.169.07:38:37.65#ibcon#about to read 3, iclass 36, count 0 2006.169.07:38:37.68#ibcon#read 3, iclass 36, count 0 2006.169.07:38:37.68#ibcon#about to read 4, iclass 36, count 0 2006.169.07:38:37.68#ibcon#read 4, iclass 36, count 0 2006.169.07:38:37.68#ibcon#about to read 5, iclass 36, count 0 2006.169.07:38:37.68#ibcon#read 5, iclass 36, count 0 2006.169.07:38:37.68#ibcon#about to read 6, iclass 36, count 0 2006.169.07:38:37.68#ibcon#read 6, iclass 36, count 0 2006.169.07:38:37.68#ibcon#end of sib2, iclass 36, count 0 2006.169.07:38:37.68#ibcon#*after write, iclass 36, count 0 2006.169.07:38:37.68#ibcon#*before return 0, iclass 36, count 0 2006.169.07:38:37.68#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.169.07:38:37.68#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.169.07:38:37.68#ibcon#about to clear, iclass 36 cls_cnt 0 2006.169.07:38:37.69#ibcon#cleared, iclass 36 cls_cnt 0 2006.169.07:38:37.69$vc4f8/vblo=2,640.99 2006.169.07:38:37.69#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.169.07:38:37.69#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.169.07:38:37.69#ibcon#ireg 17 cls_cnt 0 2006.169.07:38:37.69#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:38:37.69#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:38:37.69#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:38:37.69#ibcon#enter wrdev, iclass 38, count 0 2006.169.07:38:37.69#ibcon#first serial, iclass 38, count 0 2006.169.07:38:37.69#ibcon#enter sib2, iclass 38, count 0 2006.169.07:38:37.69#ibcon#flushed, iclass 38, count 0 2006.169.07:38:37.69#ibcon#about to write, iclass 38, count 0 2006.169.07:38:37.69#ibcon#wrote, iclass 38, count 0 2006.169.07:38:37.69#ibcon#about to read 3, iclass 38, count 0 2006.169.07:38:37.70#ibcon#read 3, iclass 38, count 0 2006.169.07:38:37.70#ibcon#about to read 4, iclass 38, count 0 2006.169.07:38:37.70#ibcon#read 4, iclass 38, count 0 2006.169.07:38:37.70#ibcon#about to read 5, iclass 38, count 0 2006.169.07:38:37.70#ibcon#read 5, iclass 38, count 0 2006.169.07:38:37.70#ibcon#about to read 6, iclass 38, count 0 2006.169.07:38:37.70#ibcon#read 6, iclass 38, count 0 2006.169.07:38:37.70#ibcon#end of sib2, iclass 38, count 0 2006.169.07:38:37.70#ibcon#*mode == 0, iclass 38, count 0 2006.169.07:38:37.70#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.169.07:38:37.70#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.07:38:37.70#ibcon#*before write, iclass 38, count 0 2006.169.07:38:37.70#ibcon#enter sib2, iclass 38, count 0 2006.169.07:38:37.70#ibcon#flushed, iclass 38, count 0 2006.169.07:38:37.70#ibcon#about to write, iclass 38, count 0 2006.169.07:38:37.71#ibcon#wrote, iclass 38, count 0 2006.169.07:38:37.71#ibcon#about to read 3, iclass 38, count 0 2006.169.07:38:37.74#ibcon#read 3, iclass 38, count 0 2006.169.07:38:37.74#ibcon#about to read 4, iclass 38, count 0 2006.169.07:38:37.74#ibcon#read 4, iclass 38, count 0 2006.169.07:38:37.74#ibcon#about to read 5, iclass 38, count 0 2006.169.07:38:37.74#ibcon#read 5, iclass 38, count 0 2006.169.07:38:37.74#ibcon#about to read 6, iclass 38, count 0 2006.169.07:38:37.74#ibcon#read 6, iclass 38, count 0 2006.169.07:38:37.74#ibcon#end of sib2, iclass 38, count 0 2006.169.07:38:37.74#ibcon#*after write, iclass 38, count 0 2006.169.07:38:37.74#ibcon#*before return 0, iclass 38, count 0 2006.169.07:38:37.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:38:37.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:38:37.74#ibcon#about to clear, iclass 38 cls_cnt 0 2006.169.07:38:37.74#ibcon#cleared, iclass 38 cls_cnt 0 2006.169.07:38:37.75$vc4f8/vb=2,4 2006.169.07:38:37.75#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.169.07:38:37.75#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.169.07:38:37.75#ibcon#ireg 11 cls_cnt 2 2006.169.07:38:37.75#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.169.07:38:37.79#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.169.07:38:37.79#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.169.07:38:37.79#ibcon#enter wrdev, iclass 40, count 2 2006.169.07:38:37.79#ibcon#first serial, iclass 40, count 2 2006.169.07:38:37.79#ibcon#enter sib2, iclass 40, count 2 2006.169.07:38:37.79#ibcon#flushed, iclass 40, count 2 2006.169.07:38:37.79#ibcon#about to write, iclass 40, count 2 2006.169.07:38:37.79#ibcon#wrote, iclass 40, count 2 2006.169.07:38:37.79#ibcon#about to read 3, iclass 40, count 2 2006.169.07:38:37.81#ibcon#read 3, iclass 40, count 2 2006.169.07:38:37.81#ibcon#about to read 4, iclass 40, count 2 2006.169.07:38:37.81#ibcon#read 4, iclass 40, count 2 2006.169.07:38:37.81#ibcon#about to read 5, iclass 40, count 2 2006.169.07:38:37.81#ibcon#read 5, iclass 40, count 2 2006.169.07:38:37.81#ibcon#about to read 6, iclass 40, count 2 2006.169.07:38:37.81#ibcon#read 6, iclass 40, count 2 2006.169.07:38:37.81#ibcon#end of sib2, iclass 40, count 2 2006.169.07:38:37.81#ibcon#*mode == 0, iclass 40, count 2 2006.169.07:38:37.81#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.169.07:38:37.81#ibcon#[27=AT02-04\r\n] 2006.169.07:38:37.81#ibcon#*before write, iclass 40, count 2 2006.169.07:38:37.81#ibcon#enter sib2, iclass 40, count 2 2006.169.07:38:37.81#ibcon#flushed, iclass 40, count 2 2006.169.07:38:37.81#ibcon#about to write, iclass 40, count 2 2006.169.07:38:37.81#ibcon#wrote, iclass 40, count 2 2006.169.07:38:37.82#ibcon#about to read 3, iclass 40, count 2 2006.169.07:38:37.84#ibcon#read 3, iclass 40, count 2 2006.169.07:38:37.84#ibcon#about to read 4, iclass 40, count 2 2006.169.07:38:37.84#ibcon#read 4, iclass 40, count 2 2006.169.07:38:37.84#ibcon#about to read 5, iclass 40, count 2 2006.169.07:38:37.84#ibcon#read 5, iclass 40, count 2 2006.169.07:38:37.84#ibcon#about to read 6, iclass 40, count 2 2006.169.07:38:37.84#ibcon#read 6, iclass 40, count 2 2006.169.07:38:37.84#ibcon#end of sib2, iclass 40, count 2 2006.169.07:38:37.84#ibcon#*after write, iclass 40, count 2 2006.169.07:38:37.84#ibcon#*before return 0, iclass 40, count 2 2006.169.07:38:37.84#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.169.07:38:37.84#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.169.07:38:37.84#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.169.07:38:37.84#ibcon#ireg 7 cls_cnt 0 2006.169.07:38:37.84#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.169.07:38:37.96#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.169.07:38:37.96#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.169.07:38:37.96#ibcon#enter wrdev, iclass 40, count 0 2006.169.07:38:37.96#ibcon#first serial, iclass 40, count 0 2006.169.07:38:37.96#ibcon#enter sib2, iclass 40, count 0 2006.169.07:38:37.96#ibcon#flushed, iclass 40, count 0 2006.169.07:38:37.96#ibcon#about to write, iclass 40, count 0 2006.169.07:38:37.96#ibcon#wrote, iclass 40, count 0 2006.169.07:38:37.96#ibcon#about to read 3, iclass 40, count 0 2006.169.07:38:37.98#ibcon#read 3, iclass 40, count 0 2006.169.07:38:37.98#ibcon#about to read 4, iclass 40, count 0 2006.169.07:38:37.98#ibcon#read 4, iclass 40, count 0 2006.169.07:38:37.98#ibcon#about to read 5, iclass 40, count 0 2006.169.07:38:37.98#ibcon#read 5, iclass 40, count 0 2006.169.07:38:37.98#ibcon#about to read 6, iclass 40, count 0 2006.169.07:38:37.98#ibcon#read 6, iclass 40, count 0 2006.169.07:38:37.98#ibcon#end of sib2, iclass 40, count 0 2006.169.07:38:37.98#ibcon#*mode == 0, iclass 40, count 0 2006.169.07:38:37.98#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.169.07:38:37.98#ibcon#[27=USB\r\n] 2006.169.07:38:37.98#ibcon#*before write, iclass 40, count 0 2006.169.07:38:37.98#ibcon#enter sib2, iclass 40, count 0 2006.169.07:38:37.98#ibcon#flushed, iclass 40, count 0 2006.169.07:38:37.98#ibcon#about to write, iclass 40, count 0 2006.169.07:38:37.98#ibcon#wrote, iclass 40, count 0 2006.169.07:38:37.99#ibcon#about to read 3, iclass 40, count 0 2006.169.07:38:38.01#ibcon#read 3, iclass 40, count 0 2006.169.07:38:38.01#ibcon#about to read 4, iclass 40, count 0 2006.169.07:38:38.01#ibcon#read 4, iclass 40, count 0 2006.169.07:38:38.01#ibcon#about to read 5, iclass 40, count 0 2006.169.07:38:38.01#ibcon#read 5, iclass 40, count 0 2006.169.07:38:38.01#ibcon#about to read 6, iclass 40, count 0 2006.169.07:38:38.01#ibcon#read 6, iclass 40, count 0 2006.169.07:38:38.01#ibcon#end of sib2, iclass 40, count 0 2006.169.07:38:38.01#ibcon#*after write, iclass 40, count 0 2006.169.07:38:38.01#ibcon#*before return 0, iclass 40, count 0 2006.169.07:38:38.01#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.169.07:38:38.01#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.169.07:38:38.01#ibcon#about to clear, iclass 40 cls_cnt 0 2006.169.07:38:38.01#ibcon#cleared, iclass 40 cls_cnt 0 2006.169.07:38:38.02$vc4f8/vblo=3,656.99 2006.169.07:38:38.02#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.169.07:38:38.02#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.169.07:38:38.02#ibcon#ireg 17 cls_cnt 0 2006.169.07:38:38.02#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.169.07:38:38.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.169.07:38:38.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.169.07:38:38.02#ibcon#enter wrdev, iclass 4, count 0 2006.169.07:38:38.02#ibcon#first serial, iclass 4, count 0 2006.169.07:38:38.02#ibcon#enter sib2, iclass 4, count 0 2006.169.07:38:38.02#ibcon#flushed, iclass 4, count 0 2006.169.07:38:38.02#ibcon#about to write, iclass 4, count 0 2006.169.07:38:38.02#ibcon#wrote, iclass 4, count 0 2006.169.07:38:38.02#ibcon#about to read 3, iclass 4, count 0 2006.169.07:38:38.03#ibcon#read 3, iclass 4, count 0 2006.169.07:38:38.03#ibcon#about to read 4, iclass 4, count 0 2006.169.07:38:38.03#ibcon#read 4, iclass 4, count 0 2006.169.07:38:38.03#ibcon#about to read 5, iclass 4, count 0 2006.169.07:38:38.03#ibcon#read 5, iclass 4, count 0 2006.169.07:38:38.03#ibcon#about to read 6, iclass 4, count 0 2006.169.07:38:38.03#ibcon#read 6, iclass 4, count 0 2006.169.07:38:38.03#ibcon#end of sib2, iclass 4, count 0 2006.169.07:38:38.03#ibcon#*mode == 0, iclass 4, count 0 2006.169.07:38:38.03#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.169.07:38:38.03#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.07:38:38.03#ibcon#*before write, iclass 4, count 0 2006.169.07:38:38.03#ibcon#enter sib2, iclass 4, count 0 2006.169.07:38:38.03#ibcon#flushed, iclass 4, count 0 2006.169.07:38:38.03#ibcon#about to write, iclass 4, count 0 2006.169.07:38:38.03#ibcon#wrote, iclass 4, count 0 2006.169.07:38:38.03#ibcon#about to read 3, iclass 4, count 0 2006.169.07:38:38.07#ibcon#read 3, iclass 4, count 0 2006.169.07:38:38.07#ibcon#about to read 4, iclass 4, count 0 2006.169.07:38:38.07#ibcon#read 4, iclass 4, count 0 2006.169.07:38:38.07#ibcon#about to read 5, iclass 4, count 0 2006.169.07:38:38.07#ibcon#read 5, iclass 4, count 0 2006.169.07:38:38.07#ibcon#about to read 6, iclass 4, count 0 2006.169.07:38:38.07#ibcon#read 6, iclass 4, count 0 2006.169.07:38:38.07#ibcon#end of sib2, iclass 4, count 0 2006.169.07:38:38.07#ibcon#*after write, iclass 4, count 0 2006.169.07:38:38.07#ibcon#*before return 0, iclass 4, count 0 2006.169.07:38:38.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.169.07:38:38.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.169.07:38:38.07#ibcon#about to clear, iclass 4 cls_cnt 0 2006.169.07:38:38.07#ibcon#cleared, iclass 4 cls_cnt 0 2006.169.07:38:38.08$vc4f8/vb=3,4 2006.169.07:38:38.08#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.169.07:38:38.08#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.169.07:38:38.08#ibcon#ireg 11 cls_cnt 2 2006.169.07:38:38.08#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.169.07:38:38.12#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.169.07:38:38.12#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.169.07:38:38.12#ibcon#enter wrdev, iclass 6, count 2 2006.169.07:38:38.12#ibcon#first serial, iclass 6, count 2 2006.169.07:38:38.12#ibcon#enter sib2, iclass 6, count 2 2006.169.07:38:38.12#ibcon#flushed, iclass 6, count 2 2006.169.07:38:38.12#ibcon#about to write, iclass 6, count 2 2006.169.07:38:38.12#ibcon#wrote, iclass 6, count 2 2006.169.07:38:38.12#ibcon#about to read 3, iclass 6, count 2 2006.169.07:38:38.14#ibcon#read 3, iclass 6, count 2 2006.169.07:38:38.14#ibcon#about to read 4, iclass 6, count 2 2006.169.07:38:38.14#ibcon#read 4, iclass 6, count 2 2006.169.07:38:38.14#ibcon#about to read 5, iclass 6, count 2 2006.169.07:38:38.14#ibcon#read 5, iclass 6, count 2 2006.169.07:38:38.14#ibcon#about to read 6, iclass 6, count 2 2006.169.07:38:38.14#ibcon#read 6, iclass 6, count 2 2006.169.07:38:38.14#ibcon#end of sib2, iclass 6, count 2 2006.169.07:38:38.14#ibcon#*mode == 0, iclass 6, count 2 2006.169.07:38:38.14#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.169.07:38:38.14#ibcon#[27=AT03-04\r\n] 2006.169.07:38:38.14#ibcon#*before write, iclass 6, count 2 2006.169.07:38:38.14#ibcon#enter sib2, iclass 6, count 2 2006.169.07:38:38.14#ibcon#flushed, iclass 6, count 2 2006.169.07:38:38.14#ibcon#about to write, iclass 6, count 2 2006.169.07:38:38.14#ibcon#wrote, iclass 6, count 2 2006.169.07:38:38.15#ibcon#about to read 3, iclass 6, count 2 2006.169.07:38:38.17#ibcon#read 3, iclass 6, count 2 2006.169.07:38:38.17#ibcon#about to read 4, iclass 6, count 2 2006.169.07:38:38.17#ibcon#read 4, iclass 6, count 2 2006.169.07:38:38.17#ibcon#about to read 5, iclass 6, count 2 2006.169.07:38:38.17#ibcon#read 5, iclass 6, count 2 2006.169.07:38:38.17#ibcon#about to read 6, iclass 6, count 2 2006.169.07:38:38.17#ibcon#read 6, iclass 6, count 2 2006.169.07:38:38.17#ibcon#end of sib2, iclass 6, count 2 2006.169.07:38:38.17#ibcon#*after write, iclass 6, count 2 2006.169.07:38:38.17#ibcon#*before return 0, iclass 6, count 2 2006.169.07:38:38.17#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.169.07:38:38.17#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.169.07:38:38.17#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.169.07:38:38.18#ibcon#ireg 7 cls_cnt 0 2006.169.07:38:38.18#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.169.07:38:38.28#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.169.07:38:38.28#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.169.07:38:38.28#ibcon#enter wrdev, iclass 6, count 0 2006.169.07:38:38.28#ibcon#first serial, iclass 6, count 0 2006.169.07:38:38.28#ibcon#enter sib2, iclass 6, count 0 2006.169.07:38:38.28#ibcon#flushed, iclass 6, count 0 2006.169.07:38:38.28#ibcon#about to write, iclass 6, count 0 2006.169.07:38:38.28#ibcon#wrote, iclass 6, count 0 2006.169.07:38:38.28#ibcon#about to read 3, iclass 6, count 0 2006.169.07:38:38.30#ibcon#read 3, iclass 6, count 0 2006.169.07:38:38.30#ibcon#about to read 4, iclass 6, count 0 2006.169.07:38:38.30#ibcon#read 4, iclass 6, count 0 2006.169.07:38:38.30#ibcon#about to read 5, iclass 6, count 0 2006.169.07:38:38.30#ibcon#read 5, iclass 6, count 0 2006.169.07:38:38.30#ibcon#about to read 6, iclass 6, count 0 2006.169.07:38:38.30#ibcon#read 6, iclass 6, count 0 2006.169.07:38:38.30#ibcon#end of sib2, iclass 6, count 0 2006.169.07:38:38.30#ibcon#*mode == 0, iclass 6, count 0 2006.169.07:38:38.30#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.169.07:38:38.30#ibcon#[27=USB\r\n] 2006.169.07:38:38.30#ibcon#*before write, iclass 6, count 0 2006.169.07:38:38.30#ibcon#enter sib2, iclass 6, count 0 2006.169.07:38:38.30#ibcon#flushed, iclass 6, count 0 2006.169.07:38:38.30#ibcon#about to write, iclass 6, count 0 2006.169.07:38:38.31#ibcon#wrote, iclass 6, count 0 2006.169.07:38:38.31#ibcon#about to read 3, iclass 6, count 0 2006.169.07:38:38.33#ibcon#read 3, iclass 6, count 0 2006.169.07:38:38.33#ibcon#about to read 4, iclass 6, count 0 2006.169.07:38:38.33#ibcon#read 4, iclass 6, count 0 2006.169.07:38:38.33#ibcon#about to read 5, iclass 6, count 0 2006.169.07:38:38.33#ibcon#read 5, iclass 6, count 0 2006.169.07:38:38.33#ibcon#about to read 6, iclass 6, count 0 2006.169.07:38:38.33#ibcon#read 6, iclass 6, count 0 2006.169.07:38:38.33#ibcon#end of sib2, iclass 6, count 0 2006.169.07:38:38.33#ibcon#*after write, iclass 6, count 0 2006.169.07:38:38.33#ibcon#*before return 0, iclass 6, count 0 2006.169.07:38:38.33#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.169.07:38:38.33#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.169.07:38:38.33#ibcon#about to clear, iclass 6 cls_cnt 0 2006.169.07:38:38.33#ibcon#cleared, iclass 6 cls_cnt 0 2006.169.07:38:38.34$vc4f8/vblo=4,712.99 2006.169.07:38:38.34#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.169.07:38:38.34#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.169.07:38:38.34#ibcon#ireg 17 cls_cnt 0 2006.169.07:38:38.34#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.169.07:38:38.34#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.169.07:38:38.34#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.169.07:38:38.34#ibcon#enter wrdev, iclass 10, count 0 2006.169.07:38:38.34#ibcon#first serial, iclass 10, count 0 2006.169.07:38:38.34#ibcon#enter sib2, iclass 10, count 0 2006.169.07:38:38.34#ibcon#flushed, iclass 10, count 0 2006.169.07:38:38.34#ibcon#about to write, iclass 10, count 0 2006.169.07:38:38.34#ibcon#wrote, iclass 10, count 0 2006.169.07:38:38.34#ibcon#about to read 3, iclass 10, count 0 2006.169.07:38:38.35#ibcon#read 3, iclass 10, count 0 2006.169.07:38:38.35#ibcon#about to read 4, iclass 10, count 0 2006.169.07:38:38.35#ibcon#read 4, iclass 10, count 0 2006.169.07:38:38.35#ibcon#about to read 5, iclass 10, count 0 2006.169.07:38:38.35#ibcon#read 5, iclass 10, count 0 2006.169.07:38:38.35#ibcon#about to read 6, iclass 10, count 0 2006.169.07:38:38.35#ibcon#read 6, iclass 10, count 0 2006.169.07:38:38.35#ibcon#end of sib2, iclass 10, count 0 2006.169.07:38:38.35#ibcon#*mode == 0, iclass 10, count 0 2006.169.07:38:38.35#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.169.07:38:38.35#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.07:38:38.35#ibcon#*before write, iclass 10, count 0 2006.169.07:38:38.35#ibcon#enter sib2, iclass 10, count 0 2006.169.07:38:38.35#ibcon#flushed, iclass 10, count 0 2006.169.07:38:38.35#ibcon#about to write, iclass 10, count 0 2006.169.07:38:38.35#ibcon#wrote, iclass 10, count 0 2006.169.07:38:38.35#ibcon#about to read 3, iclass 10, count 0 2006.169.07:38:38.39#ibcon#read 3, iclass 10, count 0 2006.169.07:38:38.39#ibcon#about to read 4, iclass 10, count 0 2006.169.07:38:38.39#ibcon#read 4, iclass 10, count 0 2006.169.07:38:38.39#ibcon#about to read 5, iclass 10, count 0 2006.169.07:38:38.39#ibcon#read 5, iclass 10, count 0 2006.169.07:38:38.39#ibcon#about to read 6, iclass 10, count 0 2006.169.07:38:38.39#ibcon#read 6, iclass 10, count 0 2006.169.07:38:38.39#ibcon#end of sib2, iclass 10, count 0 2006.169.07:38:38.39#ibcon#*after write, iclass 10, count 0 2006.169.07:38:38.39#ibcon#*before return 0, iclass 10, count 0 2006.169.07:38:38.39#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.169.07:38:38.39#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.169.07:38:38.39#ibcon#about to clear, iclass 10 cls_cnt 0 2006.169.07:38:38.39#ibcon#cleared, iclass 10 cls_cnt 0 2006.169.07:38:38.40$vc4f8/vb=4,4 2006.169.07:38:38.40#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.169.07:38:38.40#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.169.07:38:38.40#ibcon#ireg 11 cls_cnt 2 2006.169.07:38:38.40#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.169.07:38:38.44#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.169.07:38:38.44#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.169.07:38:38.44#ibcon#enter wrdev, iclass 12, count 2 2006.169.07:38:38.44#ibcon#first serial, iclass 12, count 2 2006.169.07:38:38.44#ibcon#enter sib2, iclass 12, count 2 2006.169.07:38:38.44#ibcon#flushed, iclass 12, count 2 2006.169.07:38:38.44#ibcon#about to write, iclass 12, count 2 2006.169.07:38:38.44#ibcon#wrote, iclass 12, count 2 2006.169.07:38:38.44#ibcon#about to read 3, iclass 12, count 2 2006.169.07:38:38.46#ibcon#read 3, iclass 12, count 2 2006.169.07:38:38.46#ibcon#about to read 4, iclass 12, count 2 2006.169.07:38:38.46#ibcon#read 4, iclass 12, count 2 2006.169.07:38:38.46#ibcon#about to read 5, iclass 12, count 2 2006.169.07:38:38.46#ibcon#read 5, iclass 12, count 2 2006.169.07:38:38.46#ibcon#about to read 6, iclass 12, count 2 2006.169.07:38:38.46#ibcon#read 6, iclass 12, count 2 2006.169.07:38:38.46#ibcon#end of sib2, iclass 12, count 2 2006.169.07:38:38.46#ibcon#*mode == 0, iclass 12, count 2 2006.169.07:38:38.46#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.169.07:38:38.46#ibcon#[27=AT04-04\r\n] 2006.169.07:38:38.46#ibcon#*before write, iclass 12, count 2 2006.169.07:38:38.46#ibcon#enter sib2, iclass 12, count 2 2006.169.07:38:38.46#ibcon#flushed, iclass 12, count 2 2006.169.07:38:38.46#ibcon#about to write, iclass 12, count 2 2006.169.07:38:38.46#ibcon#wrote, iclass 12, count 2 2006.169.07:38:38.46#ibcon#about to read 3, iclass 12, count 2 2006.169.07:38:38.49#ibcon#read 3, iclass 12, count 2 2006.169.07:38:38.49#ibcon#about to read 4, iclass 12, count 2 2006.169.07:38:38.49#ibcon#read 4, iclass 12, count 2 2006.169.07:38:38.49#ibcon#about to read 5, iclass 12, count 2 2006.169.07:38:38.49#ibcon#read 5, iclass 12, count 2 2006.169.07:38:38.49#ibcon#about to read 6, iclass 12, count 2 2006.169.07:38:38.49#ibcon#read 6, iclass 12, count 2 2006.169.07:38:38.49#ibcon#end of sib2, iclass 12, count 2 2006.169.07:38:38.49#ibcon#*after write, iclass 12, count 2 2006.169.07:38:38.49#ibcon#*before return 0, iclass 12, count 2 2006.169.07:38:38.49#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.169.07:38:38.49#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.169.07:38:38.49#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.169.07:38:38.49#ibcon#ireg 7 cls_cnt 0 2006.169.07:38:38.49#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.169.07:38:38.61#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.169.07:38:38.61#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.169.07:38:38.61#ibcon#enter wrdev, iclass 12, count 0 2006.169.07:38:38.61#ibcon#first serial, iclass 12, count 0 2006.169.07:38:38.61#ibcon#enter sib2, iclass 12, count 0 2006.169.07:38:38.61#ibcon#flushed, iclass 12, count 0 2006.169.07:38:38.61#ibcon#about to write, iclass 12, count 0 2006.169.07:38:38.61#ibcon#wrote, iclass 12, count 0 2006.169.07:38:38.61#ibcon#about to read 3, iclass 12, count 0 2006.169.07:38:38.63#ibcon#read 3, iclass 12, count 0 2006.169.07:38:38.63#ibcon#about to read 4, iclass 12, count 0 2006.169.07:38:38.63#ibcon#read 4, iclass 12, count 0 2006.169.07:38:38.63#ibcon#about to read 5, iclass 12, count 0 2006.169.07:38:38.63#ibcon#read 5, iclass 12, count 0 2006.169.07:38:38.63#ibcon#about to read 6, iclass 12, count 0 2006.169.07:38:38.63#ibcon#read 6, iclass 12, count 0 2006.169.07:38:38.63#ibcon#end of sib2, iclass 12, count 0 2006.169.07:38:38.63#ibcon#*mode == 0, iclass 12, count 0 2006.169.07:38:38.63#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.169.07:38:38.63#ibcon#[27=USB\r\n] 2006.169.07:38:38.63#ibcon#*before write, iclass 12, count 0 2006.169.07:38:38.63#ibcon#enter sib2, iclass 12, count 0 2006.169.07:38:38.63#ibcon#flushed, iclass 12, count 0 2006.169.07:38:38.63#ibcon#about to write, iclass 12, count 0 2006.169.07:38:38.63#ibcon#wrote, iclass 12, count 0 2006.169.07:38:38.64#ibcon#about to read 3, iclass 12, count 0 2006.169.07:38:38.66#ibcon#read 3, iclass 12, count 0 2006.169.07:38:38.66#ibcon#about to read 4, iclass 12, count 0 2006.169.07:38:38.66#ibcon#read 4, iclass 12, count 0 2006.169.07:38:38.66#ibcon#about to read 5, iclass 12, count 0 2006.169.07:38:38.66#ibcon#read 5, iclass 12, count 0 2006.169.07:38:38.66#ibcon#about to read 6, iclass 12, count 0 2006.169.07:38:38.66#ibcon#read 6, iclass 12, count 0 2006.169.07:38:38.66#ibcon#end of sib2, iclass 12, count 0 2006.169.07:38:38.66#ibcon#*after write, iclass 12, count 0 2006.169.07:38:38.66#ibcon#*before return 0, iclass 12, count 0 2006.169.07:38:38.66#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.169.07:38:38.66#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.169.07:38:38.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.169.07:38:38.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.169.07:38:38.67$vc4f8/vblo=5,744.99 2006.169.07:38:38.67#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.169.07:38:38.67#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.169.07:38:38.67#ibcon#ireg 17 cls_cnt 0 2006.169.07:38:38.67#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.169.07:38:38.67#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.169.07:38:38.67#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.169.07:38:38.67#ibcon#enter wrdev, iclass 14, count 0 2006.169.07:38:38.67#ibcon#first serial, iclass 14, count 0 2006.169.07:38:38.67#ibcon#enter sib2, iclass 14, count 0 2006.169.07:38:38.67#ibcon#flushed, iclass 14, count 0 2006.169.07:38:38.67#ibcon#about to write, iclass 14, count 0 2006.169.07:38:38.67#ibcon#wrote, iclass 14, count 0 2006.169.07:38:38.67#ibcon#about to read 3, iclass 14, count 0 2006.169.07:38:38.68#ibcon#read 3, iclass 14, count 0 2006.169.07:38:38.68#ibcon#about to read 4, iclass 14, count 0 2006.169.07:38:38.68#ibcon#read 4, iclass 14, count 0 2006.169.07:38:38.68#ibcon#about to read 5, iclass 14, count 0 2006.169.07:38:38.68#ibcon#read 5, iclass 14, count 0 2006.169.07:38:38.68#ibcon#about to read 6, iclass 14, count 0 2006.169.07:38:38.68#ibcon#read 6, iclass 14, count 0 2006.169.07:38:38.68#ibcon#end of sib2, iclass 14, count 0 2006.169.07:38:38.68#ibcon#*mode == 0, iclass 14, count 0 2006.169.07:38:38.68#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.169.07:38:38.68#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.07:38:38.68#ibcon#*before write, iclass 14, count 0 2006.169.07:38:38.68#ibcon#enter sib2, iclass 14, count 0 2006.169.07:38:38.68#ibcon#flushed, iclass 14, count 0 2006.169.07:38:38.68#ibcon#about to write, iclass 14, count 0 2006.169.07:38:38.68#ibcon#wrote, iclass 14, count 0 2006.169.07:38:38.68#ibcon#about to read 3, iclass 14, count 0 2006.169.07:38:38.72#ibcon#read 3, iclass 14, count 0 2006.169.07:38:38.72#ibcon#about to read 4, iclass 14, count 0 2006.169.07:38:38.72#ibcon#read 4, iclass 14, count 0 2006.169.07:38:38.72#ibcon#about to read 5, iclass 14, count 0 2006.169.07:38:38.72#ibcon#read 5, iclass 14, count 0 2006.169.07:38:38.72#ibcon#about to read 6, iclass 14, count 0 2006.169.07:38:38.72#ibcon#read 6, iclass 14, count 0 2006.169.07:38:38.72#ibcon#end of sib2, iclass 14, count 0 2006.169.07:38:38.72#ibcon#*after write, iclass 14, count 0 2006.169.07:38:38.72#ibcon#*before return 0, iclass 14, count 0 2006.169.07:38:38.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.169.07:38:38.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.169.07:38:38.72#ibcon#about to clear, iclass 14 cls_cnt 0 2006.169.07:38:38.72#ibcon#cleared, iclass 14 cls_cnt 0 2006.169.07:38:38.73$vc4f8/vb=5,4 2006.169.07:38:38.73#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.169.07:38:38.73#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.169.07:38:38.73#ibcon#ireg 11 cls_cnt 2 2006.169.07:38:38.73#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.169.07:38:38.77#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.169.07:38:38.77#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.169.07:38:38.77#ibcon#enter wrdev, iclass 16, count 2 2006.169.07:38:38.77#ibcon#first serial, iclass 16, count 2 2006.169.07:38:38.77#ibcon#enter sib2, iclass 16, count 2 2006.169.07:38:38.77#ibcon#flushed, iclass 16, count 2 2006.169.07:38:38.77#ibcon#about to write, iclass 16, count 2 2006.169.07:38:38.77#ibcon#wrote, iclass 16, count 2 2006.169.07:38:38.77#ibcon#about to read 3, iclass 16, count 2 2006.169.07:38:38.79#ibcon#read 3, iclass 16, count 2 2006.169.07:38:38.79#ibcon#about to read 4, iclass 16, count 2 2006.169.07:38:38.79#ibcon#read 4, iclass 16, count 2 2006.169.07:38:38.79#ibcon#about to read 5, iclass 16, count 2 2006.169.07:38:38.79#ibcon#read 5, iclass 16, count 2 2006.169.07:38:38.79#ibcon#about to read 6, iclass 16, count 2 2006.169.07:38:38.79#ibcon#read 6, iclass 16, count 2 2006.169.07:38:38.79#ibcon#end of sib2, iclass 16, count 2 2006.169.07:38:38.79#ibcon#*mode == 0, iclass 16, count 2 2006.169.07:38:38.79#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.169.07:38:38.79#ibcon#[27=AT05-04\r\n] 2006.169.07:38:38.79#ibcon#*before write, iclass 16, count 2 2006.169.07:38:38.79#ibcon#enter sib2, iclass 16, count 2 2006.169.07:38:38.79#ibcon#flushed, iclass 16, count 2 2006.169.07:38:38.79#ibcon#about to write, iclass 16, count 2 2006.169.07:38:38.79#ibcon#wrote, iclass 16, count 2 2006.169.07:38:38.80#ibcon#about to read 3, iclass 16, count 2 2006.169.07:38:38.82#ibcon#read 3, iclass 16, count 2 2006.169.07:38:38.82#ibcon#about to read 4, iclass 16, count 2 2006.169.07:38:38.82#ibcon#read 4, iclass 16, count 2 2006.169.07:38:38.82#ibcon#about to read 5, iclass 16, count 2 2006.169.07:38:38.82#ibcon#read 5, iclass 16, count 2 2006.169.07:38:38.82#ibcon#about to read 6, iclass 16, count 2 2006.169.07:38:38.82#ibcon#read 6, iclass 16, count 2 2006.169.07:38:38.82#ibcon#end of sib2, iclass 16, count 2 2006.169.07:38:38.82#ibcon#*after write, iclass 16, count 2 2006.169.07:38:38.82#ibcon#*before return 0, iclass 16, count 2 2006.169.07:38:38.82#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.169.07:38:38.82#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.169.07:38:38.82#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.169.07:38:38.82#ibcon#ireg 7 cls_cnt 0 2006.169.07:38:38.82#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.169.07:38:38.94#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.169.07:38:38.94#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.169.07:38:38.94#ibcon#enter wrdev, iclass 16, count 0 2006.169.07:38:38.94#ibcon#first serial, iclass 16, count 0 2006.169.07:38:38.94#ibcon#enter sib2, iclass 16, count 0 2006.169.07:38:38.94#ibcon#flushed, iclass 16, count 0 2006.169.07:38:38.94#ibcon#about to write, iclass 16, count 0 2006.169.07:38:38.94#ibcon#wrote, iclass 16, count 0 2006.169.07:38:38.94#ibcon#about to read 3, iclass 16, count 0 2006.169.07:38:38.96#ibcon#read 3, iclass 16, count 0 2006.169.07:38:38.96#ibcon#about to read 4, iclass 16, count 0 2006.169.07:38:38.96#ibcon#read 4, iclass 16, count 0 2006.169.07:38:38.96#ibcon#about to read 5, iclass 16, count 0 2006.169.07:38:38.96#ibcon#read 5, iclass 16, count 0 2006.169.07:38:38.96#ibcon#about to read 6, iclass 16, count 0 2006.169.07:38:38.96#ibcon#read 6, iclass 16, count 0 2006.169.07:38:38.96#ibcon#end of sib2, iclass 16, count 0 2006.169.07:38:38.96#ibcon#*mode == 0, iclass 16, count 0 2006.169.07:38:38.96#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.169.07:38:38.96#ibcon#[27=USB\r\n] 2006.169.07:38:38.96#ibcon#*before write, iclass 16, count 0 2006.169.07:38:38.96#ibcon#enter sib2, iclass 16, count 0 2006.169.07:38:38.96#ibcon#flushed, iclass 16, count 0 2006.169.07:38:38.96#ibcon#about to write, iclass 16, count 0 2006.169.07:38:38.96#ibcon#wrote, iclass 16, count 0 2006.169.07:38:38.96#ibcon#about to read 3, iclass 16, count 0 2006.169.07:38:38.99#ibcon#read 3, iclass 16, count 0 2006.169.07:38:38.99#ibcon#about to read 4, iclass 16, count 0 2006.169.07:38:38.99#ibcon#read 4, iclass 16, count 0 2006.169.07:38:38.99#ibcon#about to read 5, iclass 16, count 0 2006.169.07:38:38.99#ibcon#read 5, iclass 16, count 0 2006.169.07:38:38.99#ibcon#about to read 6, iclass 16, count 0 2006.169.07:38:38.99#ibcon#read 6, iclass 16, count 0 2006.169.07:38:38.99#ibcon#end of sib2, iclass 16, count 0 2006.169.07:38:38.99#ibcon#*after write, iclass 16, count 0 2006.169.07:38:38.99#ibcon#*before return 0, iclass 16, count 0 2006.169.07:38:38.99#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.169.07:38:38.99#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.169.07:38:38.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.169.07:38:38.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.169.07:38:39.00$vc4f8/vblo=6,752.99 2006.169.07:38:39.00#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.169.07:38:39.00#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.169.07:38:39.00#ibcon#ireg 17 cls_cnt 0 2006.169.07:38:39.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:38:39.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:38:39.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:38:39.00#ibcon#enter wrdev, iclass 18, count 0 2006.169.07:38:39.00#ibcon#first serial, iclass 18, count 0 2006.169.07:38:39.00#ibcon#enter sib2, iclass 18, count 0 2006.169.07:38:39.00#ibcon#flushed, iclass 18, count 0 2006.169.07:38:39.00#ibcon#about to write, iclass 18, count 0 2006.169.07:38:39.00#ibcon#wrote, iclass 18, count 0 2006.169.07:38:39.00#ibcon#about to read 3, iclass 18, count 0 2006.169.07:38:39.01#ibcon#read 3, iclass 18, count 0 2006.169.07:38:39.01#ibcon#about to read 4, iclass 18, count 0 2006.169.07:38:39.01#ibcon#read 4, iclass 18, count 0 2006.169.07:38:39.01#ibcon#about to read 5, iclass 18, count 0 2006.169.07:38:39.01#ibcon#read 5, iclass 18, count 0 2006.169.07:38:39.01#ibcon#about to read 6, iclass 18, count 0 2006.169.07:38:39.01#ibcon#read 6, iclass 18, count 0 2006.169.07:38:39.01#ibcon#end of sib2, iclass 18, count 0 2006.169.07:38:39.01#ibcon#*mode == 0, iclass 18, count 0 2006.169.07:38:39.01#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.169.07:38:39.01#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.07:38:39.01#ibcon#*before write, iclass 18, count 0 2006.169.07:38:39.01#ibcon#enter sib2, iclass 18, count 0 2006.169.07:38:39.01#ibcon#flushed, iclass 18, count 0 2006.169.07:38:39.01#ibcon#about to write, iclass 18, count 0 2006.169.07:38:39.02#ibcon#wrote, iclass 18, count 0 2006.169.07:38:39.02#ibcon#about to read 3, iclass 18, count 0 2006.169.07:38:39.05#ibcon#read 3, iclass 18, count 0 2006.169.07:38:39.05#ibcon#about to read 4, iclass 18, count 0 2006.169.07:38:39.05#ibcon#read 4, iclass 18, count 0 2006.169.07:38:39.05#ibcon#about to read 5, iclass 18, count 0 2006.169.07:38:39.05#ibcon#read 5, iclass 18, count 0 2006.169.07:38:39.05#ibcon#about to read 6, iclass 18, count 0 2006.169.07:38:39.05#ibcon#read 6, iclass 18, count 0 2006.169.07:38:39.05#ibcon#end of sib2, iclass 18, count 0 2006.169.07:38:39.05#ibcon#*after write, iclass 18, count 0 2006.169.07:38:39.05#ibcon#*before return 0, iclass 18, count 0 2006.169.07:38:39.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:38:39.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:38:39.05#ibcon#about to clear, iclass 18 cls_cnt 0 2006.169.07:38:39.05#ibcon#cleared, iclass 18 cls_cnt 0 2006.169.07:38:39.06$vc4f8/vb=6,4 2006.169.07:38:39.06#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.169.07:38:39.06#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.169.07:38:39.06#ibcon#ireg 11 cls_cnt 2 2006.169.07:38:39.06#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.169.07:38:39.10#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.169.07:38:39.10#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.169.07:38:39.10#ibcon#enter wrdev, iclass 20, count 2 2006.169.07:38:39.10#ibcon#first serial, iclass 20, count 2 2006.169.07:38:39.10#ibcon#enter sib2, iclass 20, count 2 2006.169.07:38:39.10#ibcon#flushed, iclass 20, count 2 2006.169.07:38:39.10#ibcon#about to write, iclass 20, count 2 2006.169.07:38:39.10#ibcon#wrote, iclass 20, count 2 2006.169.07:38:39.10#ibcon#about to read 3, iclass 20, count 2 2006.169.07:38:39.12#ibcon#read 3, iclass 20, count 2 2006.169.07:38:39.12#ibcon#about to read 4, iclass 20, count 2 2006.169.07:38:39.12#ibcon#read 4, iclass 20, count 2 2006.169.07:38:39.12#ibcon#about to read 5, iclass 20, count 2 2006.169.07:38:39.12#ibcon#read 5, iclass 20, count 2 2006.169.07:38:39.12#ibcon#about to read 6, iclass 20, count 2 2006.169.07:38:39.12#ibcon#read 6, iclass 20, count 2 2006.169.07:38:39.12#ibcon#end of sib2, iclass 20, count 2 2006.169.07:38:39.12#ibcon#*mode == 0, iclass 20, count 2 2006.169.07:38:39.12#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.169.07:38:39.12#ibcon#[27=AT06-04\r\n] 2006.169.07:38:39.12#ibcon#*before write, iclass 20, count 2 2006.169.07:38:39.12#ibcon#enter sib2, iclass 20, count 2 2006.169.07:38:39.12#ibcon#flushed, iclass 20, count 2 2006.169.07:38:39.12#ibcon#about to write, iclass 20, count 2 2006.169.07:38:39.12#ibcon#wrote, iclass 20, count 2 2006.169.07:38:39.13#ibcon#about to read 3, iclass 20, count 2 2006.169.07:38:39.15#ibcon#read 3, iclass 20, count 2 2006.169.07:38:39.15#ibcon#about to read 4, iclass 20, count 2 2006.169.07:38:39.15#ibcon#read 4, iclass 20, count 2 2006.169.07:38:39.15#ibcon#about to read 5, iclass 20, count 2 2006.169.07:38:39.15#ibcon#read 5, iclass 20, count 2 2006.169.07:38:39.15#ibcon#about to read 6, iclass 20, count 2 2006.169.07:38:39.15#ibcon#read 6, iclass 20, count 2 2006.169.07:38:39.15#ibcon#end of sib2, iclass 20, count 2 2006.169.07:38:39.15#ibcon#*after write, iclass 20, count 2 2006.169.07:38:39.15#ibcon#*before return 0, iclass 20, count 2 2006.169.07:38:39.15#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.169.07:38:39.15#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.169.07:38:39.15#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.169.07:38:39.15#ibcon#ireg 7 cls_cnt 0 2006.169.07:38:39.15#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.169.07:38:39.27#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.169.07:38:39.27#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.169.07:38:39.27#ibcon#enter wrdev, iclass 20, count 0 2006.169.07:38:39.27#ibcon#first serial, iclass 20, count 0 2006.169.07:38:39.27#ibcon#enter sib2, iclass 20, count 0 2006.169.07:38:39.27#ibcon#flushed, iclass 20, count 0 2006.169.07:38:39.27#ibcon#about to write, iclass 20, count 0 2006.169.07:38:39.27#ibcon#wrote, iclass 20, count 0 2006.169.07:38:39.27#ibcon#about to read 3, iclass 20, count 0 2006.169.07:38:39.29#ibcon#read 3, iclass 20, count 0 2006.169.07:38:39.29#ibcon#about to read 4, iclass 20, count 0 2006.169.07:38:39.29#ibcon#read 4, iclass 20, count 0 2006.169.07:38:39.29#ibcon#about to read 5, iclass 20, count 0 2006.169.07:38:39.29#ibcon#read 5, iclass 20, count 0 2006.169.07:38:39.29#ibcon#about to read 6, iclass 20, count 0 2006.169.07:38:39.29#ibcon#read 6, iclass 20, count 0 2006.169.07:38:39.29#ibcon#end of sib2, iclass 20, count 0 2006.169.07:38:39.29#ibcon#*mode == 0, iclass 20, count 0 2006.169.07:38:39.29#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.169.07:38:39.29#ibcon#[27=USB\r\n] 2006.169.07:38:39.29#ibcon#*before write, iclass 20, count 0 2006.169.07:38:39.29#ibcon#enter sib2, iclass 20, count 0 2006.169.07:38:39.29#ibcon#flushed, iclass 20, count 0 2006.169.07:38:39.29#ibcon#about to write, iclass 20, count 0 2006.169.07:38:39.29#ibcon#wrote, iclass 20, count 0 2006.169.07:38:39.29#ibcon#about to read 3, iclass 20, count 0 2006.169.07:38:39.32#ibcon#read 3, iclass 20, count 0 2006.169.07:38:39.32#ibcon#about to read 4, iclass 20, count 0 2006.169.07:38:39.32#ibcon#read 4, iclass 20, count 0 2006.169.07:38:39.32#ibcon#about to read 5, iclass 20, count 0 2006.169.07:38:39.32#ibcon#read 5, iclass 20, count 0 2006.169.07:38:39.32#ibcon#about to read 6, iclass 20, count 0 2006.169.07:38:39.32#ibcon#read 6, iclass 20, count 0 2006.169.07:38:39.32#ibcon#end of sib2, iclass 20, count 0 2006.169.07:38:39.32#ibcon#*after write, iclass 20, count 0 2006.169.07:38:39.32#ibcon#*before return 0, iclass 20, count 0 2006.169.07:38:39.32#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.169.07:38:39.32#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.169.07:38:39.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.169.07:38:39.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.169.07:38:39.33$vc4f8/vabw=wide 2006.169.07:38:39.33#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.169.07:38:39.33#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.169.07:38:39.33#ibcon#ireg 8 cls_cnt 0 2006.169.07:38:39.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:38:39.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:38:39.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:38:39.33#ibcon#enter wrdev, iclass 22, count 0 2006.169.07:38:39.33#ibcon#first serial, iclass 22, count 0 2006.169.07:38:39.33#ibcon#enter sib2, iclass 22, count 0 2006.169.07:38:39.33#ibcon#flushed, iclass 22, count 0 2006.169.07:38:39.33#ibcon#about to write, iclass 22, count 0 2006.169.07:38:39.33#ibcon#wrote, iclass 22, count 0 2006.169.07:38:39.33#ibcon#about to read 3, iclass 22, count 0 2006.169.07:38:39.34#ibcon#read 3, iclass 22, count 0 2006.169.07:38:39.34#ibcon#about to read 4, iclass 22, count 0 2006.169.07:38:39.34#ibcon#read 4, iclass 22, count 0 2006.169.07:38:39.34#ibcon#about to read 5, iclass 22, count 0 2006.169.07:38:39.34#ibcon#read 5, iclass 22, count 0 2006.169.07:38:39.34#ibcon#about to read 6, iclass 22, count 0 2006.169.07:38:39.34#ibcon#read 6, iclass 22, count 0 2006.169.07:38:39.34#ibcon#end of sib2, iclass 22, count 0 2006.169.07:38:39.34#ibcon#*mode == 0, iclass 22, count 0 2006.169.07:38:39.34#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.169.07:38:39.34#ibcon#[25=BW32\r\n] 2006.169.07:38:39.34#ibcon#*before write, iclass 22, count 0 2006.169.07:38:39.34#ibcon#enter sib2, iclass 22, count 0 2006.169.07:38:39.34#ibcon#flushed, iclass 22, count 0 2006.169.07:38:39.34#ibcon#about to write, iclass 22, count 0 2006.169.07:38:39.34#ibcon#wrote, iclass 22, count 0 2006.169.07:38:39.34#ibcon#about to read 3, iclass 22, count 0 2006.169.07:38:39.37#ibcon#read 3, iclass 22, count 0 2006.169.07:38:39.37#ibcon#about to read 4, iclass 22, count 0 2006.169.07:38:39.37#ibcon#read 4, iclass 22, count 0 2006.169.07:38:39.37#ibcon#about to read 5, iclass 22, count 0 2006.169.07:38:39.37#ibcon#read 5, iclass 22, count 0 2006.169.07:38:39.37#ibcon#about to read 6, iclass 22, count 0 2006.169.07:38:39.37#ibcon#read 6, iclass 22, count 0 2006.169.07:38:39.37#ibcon#end of sib2, iclass 22, count 0 2006.169.07:38:39.37#ibcon#*after write, iclass 22, count 0 2006.169.07:38:39.37#ibcon#*before return 0, iclass 22, count 0 2006.169.07:38:39.37#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:38:39.37#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:38:39.37#ibcon#about to clear, iclass 22 cls_cnt 0 2006.169.07:38:39.37#ibcon#cleared, iclass 22 cls_cnt 0 2006.169.07:38:39.38$vc4f8/vbbw=wide 2006.169.07:38:39.38#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.169.07:38:39.38#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.169.07:38:39.38#ibcon#ireg 8 cls_cnt 0 2006.169.07:38:39.38#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.169.07:38:39.43#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.169.07:38:39.43#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.169.07:38:39.43#ibcon#enter wrdev, iclass 24, count 0 2006.169.07:38:39.43#ibcon#first serial, iclass 24, count 0 2006.169.07:38:39.43#ibcon#enter sib2, iclass 24, count 0 2006.169.07:38:39.43#ibcon#flushed, iclass 24, count 0 2006.169.07:38:39.43#ibcon#about to write, iclass 24, count 0 2006.169.07:38:39.43#ibcon#wrote, iclass 24, count 0 2006.169.07:38:39.43#ibcon#about to read 3, iclass 24, count 0 2006.169.07:38:39.45#ibcon#read 3, iclass 24, count 0 2006.169.07:38:39.45#ibcon#about to read 4, iclass 24, count 0 2006.169.07:38:39.45#ibcon#read 4, iclass 24, count 0 2006.169.07:38:39.45#ibcon#about to read 5, iclass 24, count 0 2006.169.07:38:39.45#ibcon#read 5, iclass 24, count 0 2006.169.07:38:39.45#ibcon#about to read 6, iclass 24, count 0 2006.169.07:38:39.45#ibcon#read 6, iclass 24, count 0 2006.169.07:38:39.45#ibcon#end of sib2, iclass 24, count 0 2006.169.07:38:39.45#ibcon#*mode == 0, iclass 24, count 0 2006.169.07:38:39.45#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.169.07:38:39.45#ibcon#[27=BW32\r\n] 2006.169.07:38:39.45#ibcon#*before write, iclass 24, count 0 2006.169.07:38:39.45#ibcon#enter sib2, iclass 24, count 0 2006.169.07:38:39.45#ibcon#flushed, iclass 24, count 0 2006.169.07:38:39.45#ibcon#about to write, iclass 24, count 0 2006.169.07:38:39.45#ibcon#wrote, iclass 24, count 0 2006.169.07:38:39.45#ibcon#about to read 3, iclass 24, count 0 2006.169.07:38:39.48#ibcon#read 3, iclass 24, count 0 2006.169.07:38:39.48#ibcon#about to read 4, iclass 24, count 0 2006.169.07:38:39.48#ibcon#read 4, iclass 24, count 0 2006.169.07:38:39.48#ibcon#about to read 5, iclass 24, count 0 2006.169.07:38:39.48#ibcon#read 5, iclass 24, count 0 2006.169.07:38:39.48#ibcon#about to read 6, iclass 24, count 0 2006.169.07:38:39.48#ibcon#read 6, iclass 24, count 0 2006.169.07:38:39.48#ibcon#end of sib2, iclass 24, count 0 2006.169.07:38:39.48#ibcon#*after write, iclass 24, count 0 2006.169.07:38:39.48#ibcon#*before return 0, iclass 24, count 0 2006.169.07:38:39.48#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.169.07:38:39.48#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.169.07:38:39.48#ibcon#about to clear, iclass 24 cls_cnt 0 2006.169.07:38:39.48#ibcon#cleared, iclass 24 cls_cnt 0 2006.169.07:38:39.49$4f8m12a/ifd4f 2006.169.07:38:39.49$ifd4f/lo= 2006.169.07:38:39.49$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.07:38:39.49$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.07:38:39.49$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.07:38:39.49$ifd4f/patch= 2006.169.07:38:39.49$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.07:38:39.49$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.07:38:39.49$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.07:38:39.49$4f8m12a/"form=m,16.000,1:2 2006.169.07:38:39.49$4f8m12a/"tpicd 2006.169.07:38:39.49$4f8m12a/echo=off 2006.169.07:38:39.49$4f8m12a/xlog=off 2006.169.07:38:39.49:!2006.169.07:38:50 2006.169.07:38:50.02:preob 2006.169.07:38:51.14/onsource/TRACKING 2006.169.07:38:51.14:!2006.169.07:39:00 2006.169.07:39:00.02:data_valid=on 2006.169.07:39:00.02:midob 2006.169.07:39:01.14/onsource/TRACKING 2006.169.07:39:01.14/wx/18.15,1003.8,100 2006.169.07:39:01.21/cable/+6.5275E-03 2006.169.07:39:02.30/va/01,08,usb,yes,48,50 2006.169.07:39:02.30/va/02,07,usb,yes,49,50 2006.169.07:39:02.30/va/03,06,usb,yes,51,51 2006.169.07:39:02.30/va/04,07,usb,yes,50,53 2006.169.07:39:02.30/va/05,07,usb,yes,54,57 2006.169.07:39:02.30/va/06,06,usb,yes,54,53 2006.169.07:39:02.30/va/07,06,usb,yes,54,54 2006.169.07:39:02.30/va/08,07,usb,yes,52,51 2006.169.07:39:02.53/valo/01,532.99,yes,locked 2006.169.07:39:02.53/valo/02,572.99,yes,locked 2006.169.07:39:02.53/valo/03,672.99,yes,locked 2006.169.07:39:02.53/valo/04,832.99,yes,locked 2006.169.07:39:02.53/valo/05,652.99,yes,locked 2006.169.07:39:02.53/valo/06,772.99,yes,locked 2006.169.07:39:02.53/valo/07,832.99,yes,locked 2006.169.07:39:02.53/valo/08,852.99,yes,locked 2006.169.07:39:03.62/vb/01,04,usb,yes,30,29 2006.169.07:39:03.62/vb/02,04,usb,yes,32,34 2006.169.07:39:03.62/vb/03,04,usb,yes,29,32 2006.169.07:39:03.62/vb/04,04,usb,yes,29,30 2006.169.07:39:03.62/vb/05,04,usb,yes,28,32 2006.169.07:39:03.62/vb/06,04,usb,yes,29,32 2006.169.07:39:03.62/vb/07,04,usb,yes,31,31 2006.169.07:39:03.62/vb/08,04,usb,yes,29,32 2006.169.07:39:03.85/vblo/01,632.99,yes,locked 2006.169.07:39:03.85/vblo/02,640.99,yes,locked 2006.169.07:39:03.85/vblo/03,656.99,yes,locked 2006.169.07:39:03.85/vblo/04,712.99,yes,locked 2006.169.07:39:03.85/vblo/05,744.99,yes,locked 2006.169.07:39:03.85/vblo/06,752.99,yes,locked 2006.169.07:39:03.85/vblo/07,734.99,yes,locked 2006.169.07:39:03.85/vblo/08,744.99,yes,locked 2006.169.07:39:04.00/vabw/8 2006.169.07:39:04.15/vbbw/8 2006.169.07:39:04.24/xfe/off,on,15.0 2006.169.07:39:04.63/ifatt/23,28,28,28 2006.169.07:39:05.07/fmout-gps/S +4.16E-07 2006.169.07:39:05.15:!2006.169.07:40:00 2006.169.07:40:00.02:data_valid=off 2006.169.07:40:00.02:postob 2006.169.07:40:00.13/cable/+6.5266E-03 2006.169.07:40:00.14/wx/18.15,1003.8,100 2006.169.07:40:01.07/fmout-gps/S +4.16E-07 2006.169.07:40:01.08:scan_name=169-0740,k06169,60 2006.169.07:40:01.08:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.169.07:40:02.15#flagr#flagr/antenna,new-source 2006.169.07:40:02.15:checkk5 2006.169.07:40:02.53/chk_autoobs//k5ts1/ autoobs is running! 2006.169.07:40:02.91/chk_autoobs//k5ts2/ autoobs is running! 2006.169.07:40:06.94/chk_autoobs//k5ts3?ERROR: timeout happened! 2006.169.07:40:07.31/chk_autoobs//k5ts4/ autoobs is running! 2006.169.07:40:07.68/chk_obsdata//k5ts1/T1690739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:40:08.06/chk_obsdata//k5ts2/T1690739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:40:15.08/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.07:40:15.45/chk_obsdata//k5ts4/T1690739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:40:16.14/k5log//k5ts1_log_newline 2006.169.07:40:16.83/k5log//k5ts2_log_newline 2006.169.07:40:23.94/k5log//k5ts3?ERROR: timeout happened! 2006.169.07:40:24.62/k5log//k5ts4_log_newline 2006.169.07:40:24.79/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.07:40:24.79:4f8m12a=1 2006.169.07:40:24.79$4f8m12a/echo=on 2006.169.07:40:24.79$4f8m12a/pcalon 2006.169.07:40:24.79$pcalon/"no phase cal control is implemented here 2006.169.07:40:24.79$4f8m12a/"tpicd=stop 2006.169.07:40:24.79$4f8m12a/vc4f8 2006.169.07:40:24.79$vc4f8/valo=1,532.99 2006.169.07:40:24.79#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.169.07:40:24.79#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.169.07:40:24.79#ibcon#ireg 17 cls_cnt 0 2006.169.07:40:24.79#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.169.07:40:24.79#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.169.07:40:24.79#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.169.07:40:24.79#ibcon#enter wrdev, iclass 35, count 0 2006.169.07:40:24.79#ibcon#first serial, iclass 35, count 0 2006.169.07:40:24.79#ibcon#enter sib2, iclass 35, count 0 2006.169.07:40:24.79#ibcon#flushed, iclass 35, count 0 2006.169.07:40:24.79#ibcon#about to write, iclass 35, count 0 2006.169.07:40:24.79#ibcon#wrote, iclass 35, count 0 2006.169.07:40:24.79#ibcon#about to read 3, iclass 35, count 0 2006.169.07:40:24.80#ibcon#read 3, iclass 35, count 0 2006.169.07:40:24.80#ibcon#about to read 4, iclass 35, count 0 2006.169.07:40:24.80#ibcon#read 4, iclass 35, count 0 2006.169.07:40:24.80#ibcon#about to read 5, iclass 35, count 0 2006.169.07:40:24.80#ibcon#read 5, iclass 35, count 0 2006.169.07:40:24.80#ibcon#about to read 6, iclass 35, count 0 2006.169.07:40:24.80#ibcon#read 6, iclass 35, count 0 2006.169.07:40:24.80#ibcon#end of sib2, iclass 35, count 0 2006.169.07:40:24.80#ibcon#*mode == 0, iclass 35, count 0 2006.169.07:40:24.80#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.169.07:40:24.80#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.07:40:24.80#ibcon#*before write, iclass 35, count 0 2006.169.07:40:24.80#ibcon#enter sib2, iclass 35, count 0 2006.169.07:40:24.80#ibcon#flushed, iclass 35, count 0 2006.169.07:40:24.80#ibcon#about to write, iclass 35, count 0 2006.169.07:40:24.80#ibcon#wrote, iclass 35, count 0 2006.169.07:40:24.80#ibcon#about to read 3, iclass 35, count 0 2006.169.07:40:24.85#ibcon#read 3, iclass 35, count 0 2006.169.07:40:24.85#ibcon#about to read 4, iclass 35, count 0 2006.169.07:40:24.85#ibcon#read 4, iclass 35, count 0 2006.169.07:40:24.85#ibcon#about to read 5, iclass 35, count 0 2006.169.07:40:24.85#ibcon#read 5, iclass 35, count 0 2006.169.07:40:24.85#ibcon#about to read 6, iclass 35, count 0 2006.169.07:40:24.85#ibcon#read 6, iclass 35, count 0 2006.169.07:40:24.85#ibcon#end of sib2, iclass 35, count 0 2006.169.07:40:24.85#ibcon#*after write, iclass 35, count 0 2006.169.07:40:24.85#ibcon#*before return 0, iclass 35, count 0 2006.169.07:40:24.85#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.169.07:40:24.86#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.169.07:40:24.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.169.07:40:24.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.169.07:40:24.86$vc4f8/va=1,8 2006.169.07:40:24.86#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.169.07:40:24.86#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.169.07:40:24.86#ibcon#ireg 11 cls_cnt 2 2006.169.07:40:24.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.169.07:40:24.86#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.169.07:40:24.86#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.169.07:40:24.86#ibcon#enter wrdev, iclass 37, count 2 2006.169.07:40:24.86#ibcon#first serial, iclass 37, count 2 2006.169.07:40:24.86#ibcon#enter sib2, iclass 37, count 2 2006.169.07:40:24.86#ibcon#flushed, iclass 37, count 2 2006.169.07:40:24.86#ibcon#about to write, iclass 37, count 2 2006.169.07:40:24.86#ibcon#wrote, iclass 37, count 2 2006.169.07:40:24.86#ibcon#about to read 3, iclass 37, count 2 2006.169.07:40:24.87#ibcon#read 3, iclass 37, count 2 2006.169.07:40:24.87#ibcon#about to read 4, iclass 37, count 2 2006.169.07:40:24.87#ibcon#read 4, iclass 37, count 2 2006.169.07:40:24.87#ibcon#about to read 5, iclass 37, count 2 2006.169.07:40:24.87#ibcon#read 5, iclass 37, count 2 2006.169.07:40:24.87#ibcon#about to read 6, iclass 37, count 2 2006.169.07:40:24.87#ibcon#read 6, iclass 37, count 2 2006.169.07:40:24.87#ibcon#end of sib2, iclass 37, count 2 2006.169.07:40:24.87#ibcon#*mode == 0, iclass 37, count 2 2006.169.07:40:24.87#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.169.07:40:24.87#ibcon#[25=AT01-08\r\n] 2006.169.07:40:24.87#ibcon#*before write, iclass 37, count 2 2006.169.07:40:24.87#ibcon#enter sib2, iclass 37, count 2 2006.169.07:40:24.87#ibcon#flushed, iclass 37, count 2 2006.169.07:40:24.87#ibcon#about to write, iclass 37, count 2 2006.169.07:40:24.87#ibcon#wrote, iclass 37, count 2 2006.169.07:40:24.87#ibcon#about to read 3, iclass 37, count 2 2006.169.07:40:24.90#ibcon#read 3, iclass 37, count 2 2006.169.07:40:24.90#ibcon#about to read 4, iclass 37, count 2 2006.169.07:40:24.90#ibcon#read 4, iclass 37, count 2 2006.169.07:40:24.90#ibcon#about to read 5, iclass 37, count 2 2006.169.07:40:24.90#ibcon#read 5, iclass 37, count 2 2006.169.07:40:24.90#ibcon#about to read 6, iclass 37, count 2 2006.169.07:40:24.90#ibcon#read 6, iclass 37, count 2 2006.169.07:40:24.90#ibcon#end of sib2, iclass 37, count 2 2006.169.07:40:24.90#ibcon#*after write, iclass 37, count 2 2006.169.07:40:24.90#ibcon#*before return 0, iclass 37, count 2 2006.169.07:40:24.90#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.169.07:40:24.90#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.169.07:40:24.90#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.169.07:40:24.90#ibcon#ireg 7 cls_cnt 0 2006.169.07:40:24.90#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.169.07:40:25.02#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.169.07:40:25.02#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.169.07:40:25.02#ibcon#enter wrdev, iclass 37, count 0 2006.169.07:40:25.02#ibcon#first serial, iclass 37, count 0 2006.169.07:40:25.02#ibcon#enter sib2, iclass 37, count 0 2006.169.07:40:25.02#ibcon#flushed, iclass 37, count 0 2006.169.07:40:25.02#ibcon#about to write, iclass 37, count 0 2006.169.07:40:25.02#ibcon#wrote, iclass 37, count 0 2006.169.07:40:25.02#ibcon#about to read 3, iclass 37, count 0 2006.169.07:40:25.04#ibcon#read 3, iclass 37, count 0 2006.169.07:40:25.04#ibcon#about to read 4, iclass 37, count 0 2006.169.07:40:25.04#ibcon#read 4, iclass 37, count 0 2006.169.07:40:25.04#ibcon#about to read 5, iclass 37, count 0 2006.169.07:40:25.04#ibcon#read 5, iclass 37, count 0 2006.169.07:40:25.04#ibcon#about to read 6, iclass 37, count 0 2006.169.07:40:25.04#ibcon#read 6, iclass 37, count 0 2006.169.07:40:25.04#ibcon#end of sib2, iclass 37, count 0 2006.169.07:40:25.04#ibcon#*mode == 0, iclass 37, count 0 2006.169.07:40:25.04#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.169.07:40:25.04#ibcon#[25=USB\r\n] 2006.169.07:40:25.04#ibcon#*before write, iclass 37, count 0 2006.169.07:40:25.04#ibcon#enter sib2, iclass 37, count 0 2006.169.07:40:25.04#ibcon#flushed, iclass 37, count 0 2006.169.07:40:25.04#ibcon#about to write, iclass 37, count 0 2006.169.07:40:25.04#ibcon#wrote, iclass 37, count 0 2006.169.07:40:25.04#ibcon#about to read 3, iclass 37, count 0 2006.169.07:40:25.08#ibcon#read 3, iclass 37, count 0 2006.169.07:40:25.08#ibcon#about to read 4, iclass 37, count 0 2006.169.07:40:25.08#ibcon#read 4, iclass 37, count 0 2006.169.07:40:25.08#ibcon#about to read 5, iclass 37, count 0 2006.169.07:40:25.08#ibcon#read 5, iclass 37, count 0 2006.169.07:40:25.08#ibcon#about to read 6, iclass 37, count 0 2006.169.07:40:25.08#ibcon#read 6, iclass 37, count 0 2006.169.07:40:25.08#ibcon#end of sib2, iclass 37, count 0 2006.169.07:40:25.08#ibcon#*after write, iclass 37, count 0 2006.169.07:40:25.08#ibcon#*before return 0, iclass 37, count 0 2006.169.07:40:25.08#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.169.07:40:25.08#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.169.07:40:25.08#ibcon#about to clear, iclass 37 cls_cnt 0 2006.169.07:40:25.08#ibcon#cleared, iclass 37 cls_cnt 0 2006.169.07:40:25.08$vc4f8/valo=2,572.99 2006.169.07:40:25.08#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.169.07:40:25.08#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.169.07:40:25.08#ibcon#ireg 17 cls_cnt 0 2006.169.07:40:25.08#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.169.07:40:25.08#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.169.07:40:25.08#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.169.07:40:25.08#ibcon#enter wrdev, iclass 39, count 0 2006.169.07:40:25.08#ibcon#first serial, iclass 39, count 0 2006.169.07:40:25.08#ibcon#enter sib2, iclass 39, count 0 2006.169.07:40:25.08#ibcon#flushed, iclass 39, count 0 2006.169.07:40:25.08#ibcon#about to write, iclass 39, count 0 2006.169.07:40:25.08#ibcon#wrote, iclass 39, count 0 2006.169.07:40:25.08#ibcon#about to read 3, iclass 39, count 0 2006.169.07:40:25.10#ibcon#read 3, iclass 39, count 0 2006.169.07:40:25.10#ibcon#about to read 4, iclass 39, count 0 2006.169.07:40:25.10#ibcon#read 4, iclass 39, count 0 2006.169.07:40:25.10#ibcon#about to read 5, iclass 39, count 0 2006.169.07:40:25.10#ibcon#read 5, iclass 39, count 0 2006.169.07:40:25.10#ibcon#about to read 6, iclass 39, count 0 2006.169.07:40:25.10#ibcon#read 6, iclass 39, count 0 2006.169.07:40:25.10#ibcon#end of sib2, iclass 39, count 0 2006.169.07:40:25.10#ibcon#*mode == 0, iclass 39, count 0 2006.169.07:40:25.10#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.169.07:40:25.10#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.07:40:25.10#ibcon#*before write, iclass 39, count 0 2006.169.07:40:25.10#ibcon#enter sib2, iclass 39, count 0 2006.169.07:40:25.10#ibcon#flushed, iclass 39, count 0 2006.169.07:40:25.10#ibcon#about to write, iclass 39, count 0 2006.169.07:40:25.10#ibcon#wrote, iclass 39, count 0 2006.169.07:40:25.10#ibcon#about to read 3, iclass 39, count 0 2006.169.07:40:25.13#ibcon#read 3, iclass 39, count 0 2006.169.07:40:25.13#ibcon#about to read 4, iclass 39, count 0 2006.169.07:40:25.13#ibcon#read 4, iclass 39, count 0 2006.169.07:40:25.13#ibcon#about to read 5, iclass 39, count 0 2006.169.07:40:25.13#ibcon#read 5, iclass 39, count 0 2006.169.07:40:25.13#ibcon#about to read 6, iclass 39, count 0 2006.169.07:40:25.13#ibcon#read 6, iclass 39, count 0 2006.169.07:40:25.13#ibcon#end of sib2, iclass 39, count 0 2006.169.07:40:25.13#ibcon#*after write, iclass 39, count 0 2006.169.07:40:25.13#ibcon#*before return 0, iclass 39, count 0 2006.169.07:40:25.13#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.169.07:40:25.13#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.169.07:40:25.13#ibcon#about to clear, iclass 39 cls_cnt 0 2006.169.07:40:25.13#ibcon#cleared, iclass 39 cls_cnt 0 2006.169.07:40:25.13$vc4f8/va=2,7 2006.169.07:40:25.13#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.169.07:40:25.13#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.169.07:40:25.13#ibcon#ireg 11 cls_cnt 2 2006.169.07:40:25.13#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.169.07:40:25.14#trakl#Source acquired 2006.169.07:40:25.14#flagr#flagr/antenna,acquired 2006.169.07:40:25.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.169.07:40:25.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.169.07:40:25.21#ibcon#enter wrdev, iclass 3, count 2 2006.169.07:40:25.21#ibcon#first serial, iclass 3, count 2 2006.169.07:40:25.21#ibcon#enter sib2, iclass 3, count 2 2006.169.07:40:25.21#ibcon#flushed, iclass 3, count 2 2006.169.07:40:25.21#ibcon#about to write, iclass 3, count 2 2006.169.07:40:25.21#ibcon#wrote, iclass 3, count 2 2006.169.07:40:25.21#ibcon#about to read 3, iclass 3, count 2 2006.169.07:40:25.22#ibcon#read 3, iclass 3, count 2 2006.169.07:40:25.22#ibcon#about to read 4, iclass 3, count 2 2006.169.07:40:25.22#ibcon#read 4, iclass 3, count 2 2006.169.07:40:25.22#ibcon#about to read 5, iclass 3, count 2 2006.169.07:40:25.22#ibcon#read 5, iclass 3, count 2 2006.169.07:40:25.22#ibcon#about to read 6, iclass 3, count 2 2006.169.07:40:25.22#ibcon#read 6, iclass 3, count 2 2006.169.07:40:25.22#ibcon#end of sib2, iclass 3, count 2 2006.169.07:40:25.22#ibcon#*mode == 0, iclass 3, count 2 2006.169.07:40:25.22#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.169.07:40:25.22#ibcon#[25=AT02-07\r\n] 2006.169.07:40:25.22#ibcon#*before write, iclass 3, count 2 2006.169.07:40:25.22#ibcon#enter sib2, iclass 3, count 2 2006.169.07:40:25.22#ibcon#flushed, iclass 3, count 2 2006.169.07:40:25.22#ibcon#about to write, iclass 3, count 2 2006.169.07:40:25.22#ibcon#wrote, iclass 3, count 2 2006.169.07:40:25.22#ibcon#about to read 3, iclass 3, count 2 2006.169.07:40:25.25#ibcon#read 3, iclass 3, count 2 2006.169.07:40:25.25#ibcon#about to read 4, iclass 3, count 2 2006.169.07:40:25.25#ibcon#read 4, iclass 3, count 2 2006.169.07:40:25.25#ibcon#about to read 5, iclass 3, count 2 2006.169.07:40:25.25#ibcon#read 5, iclass 3, count 2 2006.169.07:40:25.25#ibcon#about to read 6, iclass 3, count 2 2006.169.07:40:25.25#ibcon#read 6, iclass 3, count 2 2006.169.07:40:25.25#ibcon#end of sib2, iclass 3, count 2 2006.169.07:40:25.25#ibcon#*after write, iclass 3, count 2 2006.169.07:40:25.25#ibcon#*before return 0, iclass 3, count 2 2006.169.07:40:25.25#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.169.07:40:25.25#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.169.07:40:25.25#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.169.07:40:25.25#ibcon#ireg 7 cls_cnt 0 2006.169.07:40:25.25#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.169.07:40:25.38#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.169.07:40:25.38#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.169.07:40:25.38#ibcon#enter wrdev, iclass 3, count 0 2006.169.07:40:25.38#ibcon#first serial, iclass 3, count 0 2006.169.07:40:25.38#ibcon#enter sib2, iclass 3, count 0 2006.169.07:40:25.38#ibcon#flushed, iclass 3, count 0 2006.169.07:40:25.38#ibcon#about to write, iclass 3, count 0 2006.169.07:40:25.38#ibcon#wrote, iclass 3, count 0 2006.169.07:40:25.38#ibcon#about to read 3, iclass 3, count 0 2006.169.07:40:25.39#ibcon#read 3, iclass 3, count 0 2006.169.07:40:25.39#ibcon#about to read 4, iclass 3, count 0 2006.169.07:40:25.39#ibcon#read 4, iclass 3, count 0 2006.169.07:40:25.39#ibcon#about to read 5, iclass 3, count 0 2006.169.07:40:25.39#ibcon#read 5, iclass 3, count 0 2006.169.07:40:25.39#ibcon#about to read 6, iclass 3, count 0 2006.169.07:40:25.39#ibcon#read 6, iclass 3, count 0 2006.169.07:40:25.39#ibcon#end of sib2, iclass 3, count 0 2006.169.07:40:25.39#ibcon#*mode == 0, iclass 3, count 0 2006.169.07:40:25.39#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.169.07:40:25.39#ibcon#[25=USB\r\n] 2006.169.07:40:25.39#ibcon#*before write, iclass 3, count 0 2006.169.07:40:25.39#ibcon#enter sib2, iclass 3, count 0 2006.169.07:40:25.39#ibcon#flushed, iclass 3, count 0 2006.169.07:40:25.39#ibcon#about to write, iclass 3, count 0 2006.169.07:40:25.39#ibcon#wrote, iclass 3, count 0 2006.169.07:40:25.39#ibcon#about to read 3, iclass 3, count 0 2006.169.07:40:25.42#ibcon#read 3, iclass 3, count 0 2006.169.07:40:25.42#ibcon#about to read 4, iclass 3, count 0 2006.169.07:40:25.42#ibcon#read 4, iclass 3, count 0 2006.169.07:40:25.42#ibcon#about to read 5, iclass 3, count 0 2006.169.07:40:25.42#ibcon#read 5, iclass 3, count 0 2006.169.07:40:25.42#ibcon#about to read 6, iclass 3, count 0 2006.169.07:40:25.42#ibcon#read 6, iclass 3, count 0 2006.169.07:40:25.42#ibcon#end of sib2, iclass 3, count 0 2006.169.07:40:25.42#ibcon#*after write, iclass 3, count 0 2006.169.07:40:25.42#ibcon#*before return 0, iclass 3, count 0 2006.169.07:40:25.42#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.169.07:40:25.42#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.169.07:40:25.42#ibcon#about to clear, iclass 3 cls_cnt 0 2006.169.07:40:25.42#ibcon#cleared, iclass 3 cls_cnt 0 2006.169.07:40:25.42$vc4f8/valo=3,672.99 2006.169.07:40:25.42#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.169.07:40:25.42#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.169.07:40:25.42#ibcon#ireg 17 cls_cnt 0 2006.169.07:40:25.42#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:40:25.42#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:40:25.42#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:40:25.42#ibcon#enter wrdev, iclass 5, count 0 2006.169.07:40:25.42#ibcon#first serial, iclass 5, count 0 2006.169.07:40:25.43#ibcon#enter sib2, iclass 5, count 0 2006.169.07:40:25.43#ibcon#flushed, iclass 5, count 0 2006.169.07:40:25.43#ibcon#about to write, iclass 5, count 0 2006.169.07:40:25.43#ibcon#wrote, iclass 5, count 0 2006.169.07:40:25.43#ibcon#about to read 3, iclass 5, count 0 2006.169.07:40:25.45#ibcon#read 3, iclass 5, count 0 2006.169.07:40:25.45#ibcon#about to read 4, iclass 5, count 0 2006.169.07:40:25.45#ibcon#read 4, iclass 5, count 0 2006.169.07:40:25.45#ibcon#about to read 5, iclass 5, count 0 2006.169.07:40:25.45#ibcon#read 5, iclass 5, count 0 2006.169.07:40:25.45#ibcon#about to read 6, iclass 5, count 0 2006.169.07:40:25.45#ibcon#read 6, iclass 5, count 0 2006.169.07:40:25.45#ibcon#end of sib2, iclass 5, count 0 2006.169.07:40:25.45#ibcon#*mode == 0, iclass 5, count 0 2006.169.07:40:25.45#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.169.07:40:25.45#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.07:40:25.45#ibcon#*before write, iclass 5, count 0 2006.169.07:40:25.45#ibcon#enter sib2, iclass 5, count 0 2006.169.07:40:25.45#ibcon#flushed, iclass 5, count 0 2006.169.07:40:25.45#ibcon#about to write, iclass 5, count 0 2006.169.07:40:25.45#ibcon#wrote, iclass 5, count 0 2006.169.07:40:25.45#ibcon#about to read 3, iclass 5, count 0 2006.169.07:40:25.48#ibcon#read 3, iclass 5, count 0 2006.169.07:40:25.48#ibcon#about to read 4, iclass 5, count 0 2006.169.07:40:25.48#ibcon#read 4, iclass 5, count 0 2006.169.07:40:25.48#ibcon#about to read 5, iclass 5, count 0 2006.169.07:40:25.48#ibcon#read 5, iclass 5, count 0 2006.169.07:40:25.48#ibcon#about to read 6, iclass 5, count 0 2006.169.07:40:25.48#ibcon#read 6, iclass 5, count 0 2006.169.07:40:25.48#ibcon#end of sib2, iclass 5, count 0 2006.169.07:40:25.48#ibcon#*after write, iclass 5, count 0 2006.169.07:40:25.48#ibcon#*before return 0, iclass 5, count 0 2006.169.07:40:25.48#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:40:25.48#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:40:25.48#ibcon#about to clear, iclass 5 cls_cnt 0 2006.169.07:40:25.48#ibcon#cleared, iclass 5 cls_cnt 0 2006.169.07:40:25.48$vc4f8/va=3,6 2006.169.07:40:25.48#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.169.07:40:25.48#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.169.07:40:25.48#ibcon#ireg 11 cls_cnt 2 2006.169.07:40:25.48#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:40:25.54#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:40:25.54#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:40:25.54#ibcon#enter wrdev, iclass 7, count 2 2006.169.07:40:25.54#ibcon#first serial, iclass 7, count 2 2006.169.07:40:25.54#ibcon#enter sib2, iclass 7, count 2 2006.169.07:40:25.54#ibcon#flushed, iclass 7, count 2 2006.169.07:40:25.54#ibcon#about to write, iclass 7, count 2 2006.169.07:40:25.54#ibcon#wrote, iclass 7, count 2 2006.169.07:40:25.54#ibcon#about to read 3, iclass 7, count 2 2006.169.07:40:25.57#ibcon#read 3, iclass 7, count 2 2006.169.07:40:25.57#ibcon#about to read 4, iclass 7, count 2 2006.169.07:40:25.57#ibcon#read 4, iclass 7, count 2 2006.169.07:40:25.57#ibcon#about to read 5, iclass 7, count 2 2006.169.07:40:25.57#ibcon#read 5, iclass 7, count 2 2006.169.07:40:25.57#ibcon#about to read 6, iclass 7, count 2 2006.169.07:40:25.57#ibcon#read 6, iclass 7, count 2 2006.169.07:40:25.57#ibcon#end of sib2, iclass 7, count 2 2006.169.07:40:25.57#ibcon#*mode == 0, iclass 7, count 2 2006.169.07:40:25.57#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.169.07:40:25.57#ibcon#[25=AT03-06\r\n] 2006.169.07:40:25.57#ibcon#*before write, iclass 7, count 2 2006.169.07:40:25.57#ibcon#enter sib2, iclass 7, count 2 2006.169.07:40:25.57#ibcon#flushed, iclass 7, count 2 2006.169.07:40:25.57#ibcon#about to write, iclass 7, count 2 2006.169.07:40:25.57#ibcon#wrote, iclass 7, count 2 2006.169.07:40:25.57#ibcon#about to read 3, iclass 7, count 2 2006.169.07:40:25.60#ibcon#read 3, iclass 7, count 2 2006.169.07:40:25.60#ibcon#about to read 4, iclass 7, count 2 2006.169.07:40:25.60#ibcon#read 4, iclass 7, count 2 2006.169.07:40:25.60#ibcon#about to read 5, iclass 7, count 2 2006.169.07:40:25.60#ibcon#read 5, iclass 7, count 2 2006.169.07:40:25.60#ibcon#about to read 6, iclass 7, count 2 2006.169.07:40:25.60#ibcon#read 6, iclass 7, count 2 2006.169.07:40:25.60#ibcon#end of sib2, iclass 7, count 2 2006.169.07:40:25.60#ibcon#*after write, iclass 7, count 2 2006.169.07:40:25.60#ibcon#*before return 0, iclass 7, count 2 2006.169.07:40:25.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:40:25.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:40:25.60#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.169.07:40:25.60#ibcon#ireg 7 cls_cnt 0 2006.169.07:40:25.60#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:40:25.72#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:40:25.72#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:40:25.72#ibcon#enter wrdev, iclass 7, count 0 2006.169.07:40:25.72#ibcon#first serial, iclass 7, count 0 2006.169.07:40:25.72#ibcon#enter sib2, iclass 7, count 0 2006.169.07:40:25.72#ibcon#flushed, iclass 7, count 0 2006.169.07:40:25.72#ibcon#about to write, iclass 7, count 0 2006.169.07:40:25.72#ibcon#wrote, iclass 7, count 0 2006.169.07:40:25.72#ibcon#about to read 3, iclass 7, count 0 2006.169.07:40:25.74#ibcon#read 3, iclass 7, count 0 2006.169.07:40:25.74#ibcon#about to read 4, iclass 7, count 0 2006.169.07:40:25.74#ibcon#read 4, iclass 7, count 0 2006.169.07:40:25.74#ibcon#about to read 5, iclass 7, count 0 2006.169.07:40:25.74#ibcon#read 5, iclass 7, count 0 2006.169.07:40:25.74#ibcon#about to read 6, iclass 7, count 0 2006.169.07:40:25.74#ibcon#read 6, iclass 7, count 0 2006.169.07:40:25.74#ibcon#end of sib2, iclass 7, count 0 2006.169.07:40:25.74#ibcon#*mode == 0, iclass 7, count 0 2006.169.07:40:25.74#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.169.07:40:25.74#ibcon#[25=USB\r\n] 2006.169.07:40:25.74#ibcon#*before write, iclass 7, count 0 2006.169.07:40:25.74#ibcon#enter sib2, iclass 7, count 0 2006.169.07:40:25.74#ibcon#flushed, iclass 7, count 0 2006.169.07:40:25.74#ibcon#about to write, iclass 7, count 0 2006.169.07:40:25.74#ibcon#wrote, iclass 7, count 0 2006.169.07:40:25.74#ibcon#about to read 3, iclass 7, count 0 2006.169.07:40:25.77#ibcon#read 3, iclass 7, count 0 2006.169.07:40:25.77#ibcon#about to read 4, iclass 7, count 0 2006.169.07:40:25.77#ibcon#read 4, iclass 7, count 0 2006.169.07:40:25.77#ibcon#about to read 5, iclass 7, count 0 2006.169.07:40:25.77#ibcon#read 5, iclass 7, count 0 2006.169.07:40:25.77#ibcon#about to read 6, iclass 7, count 0 2006.169.07:40:25.77#ibcon#read 6, iclass 7, count 0 2006.169.07:40:25.77#ibcon#end of sib2, iclass 7, count 0 2006.169.07:40:25.77#ibcon#*after write, iclass 7, count 0 2006.169.07:40:25.77#ibcon#*before return 0, iclass 7, count 0 2006.169.07:40:25.77#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:40:25.77#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:40:25.77#ibcon#about to clear, iclass 7 cls_cnt 0 2006.169.07:40:25.77#ibcon#cleared, iclass 7 cls_cnt 0 2006.169.07:40:25.77$vc4f8/valo=4,832.99 2006.169.07:40:25.77#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.169.07:40:25.77#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.169.07:40:25.77#ibcon#ireg 17 cls_cnt 0 2006.169.07:40:25.77#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.169.07:40:25.77#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.169.07:40:25.77#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.169.07:40:25.77#ibcon#enter wrdev, iclass 11, count 0 2006.169.07:40:25.77#ibcon#first serial, iclass 11, count 0 2006.169.07:40:25.78#ibcon#enter sib2, iclass 11, count 0 2006.169.07:40:25.78#ibcon#flushed, iclass 11, count 0 2006.169.07:40:25.78#ibcon#about to write, iclass 11, count 0 2006.169.07:40:25.78#ibcon#wrote, iclass 11, count 0 2006.169.07:40:25.78#ibcon#about to read 3, iclass 11, count 0 2006.169.07:40:25.79#ibcon#read 3, iclass 11, count 0 2006.169.07:40:25.79#ibcon#about to read 4, iclass 11, count 0 2006.169.07:40:25.79#ibcon#read 4, iclass 11, count 0 2006.169.07:40:25.79#ibcon#about to read 5, iclass 11, count 0 2006.169.07:40:25.79#ibcon#read 5, iclass 11, count 0 2006.169.07:40:25.79#ibcon#about to read 6, iclass 11, count 0 2006.169.07:40:25.79#ibcon#read 6, iclass 11, count 0 2006.169.07:40:25.79#ibcon#end of sib2, iclass 11, count 0 2006.169.07:40:25.79#ibcon#*mode == 0, iclass 11, count 0 2006.169.07:40:25.79#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.169.07:40:25.79#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.07:40:25.79#ibcon#*before write, iclass 11, count 0 2006.169.07:40:25.79#ibcon#enter sib2, iclass 11, count 0 2006.169.07:40:25.79#ibcon#flushed, iclass 11, count 0 2006.169.07:40:25.79#ibcon#about to write, iclass 11, count 0 2006.169.07:40:25.79#ibcon#wrote, iclass 11, count 0 2006.169.07:40:25.79#ibcon#about to read 3, iclass 11, count 0 2006.169.07:40:25.83#ibcon#read 3, iclass 11, count 0 2006.169.07:40:25.83#ibcon#about to read 4, iclass 11, count 0 2006.169.07:40:25.83#ibcon#read 4, iclass 11, count 0 2006.169.07:40:25.83#ibcon#about to read 5, iclass 11, count 0 2006.169.07:40:25.83#ibcon#read 5, iclass 11, count 0 2006.169.07:40:25.83#ibcon#about to read 6, iclass 11, count 0 2006.169.07:40:25.83#ibcon#read 6, iclass 11, count 0 2006.169.07:40:25.83#ibcon#end of sib2, iclass 11, count 0 2006.169.07:40:25.83#ibcon#*after write, iclass 11, count 0 2006.169.07:40:25.83#ibcon#*before return 0, iclass 11, count 0 2006.169.07:40:25.83#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.169.07:40:25.83#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.169.07:40:25.83#ibcon#about to clear, iclass 11 cls_cnt 0 2006.169.07:40:25.83#ibcon#cleared, iclass 11 cls_cnt 0 2006.169.07:40:25.83$vc4f8/va=4,7 2006.169.07:40:25.83#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.169.07:40:25.83#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.169.07:40:25.83#ibcon#ireg 11 cls_cnt 2 2006.169.07:40:25.83#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.169.07:40:25.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.169.07:40:25.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.169.07:40:25.89#ibcon#enter wrdev, iclass 13, count 2 2006.169.07:40:25.89#ibcon#first serial, iclass 13, count 2 2006.169.07:40:25.89#ibcon#enter sib2, iclass 13, count 2 2006.169.07:40:25.89#ibcon#flushed, iclass 13, count 2 2006.169.07:40:25.89#ibcon#about to write, iclass 13, count 2 2006.169.07:40:25.89#ibcon#wrote, iclass 13, count 2 2006.169.07:40:25.89#ibcon#about to read 3, iclass 13, count 2 2006.169.07:40:25.91#ibcon#read 3, iclass 13, count 2 2006.169.07:40:25.91#ibcon#about to read 4, iclass 13, count 2 2006.169.07:40:25.91#ibcon#read 4, iclass 13, count 2 2006.169.07:40:25.91#ibcon#about to read 5, iclass 13, count 2 2006.169.07:40:25.91#ibcon#read 5, iclass 13, count 2 2006.169.07:40:25.91#ibcon#about to read 6, iclass 13, count 2 2006.169.07:40:25.91#ibcon#read 6, iclass 13, count 2 2006.169.07:40:25.91#ibcon#end of sib2, iclass 13, count 2 2006.169.07:40:25.91#ibcon#*mode == 0, iclass 13, count 2 2006.169.07:40:25.91#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.169.07:40:25.91#ibcon#[25=AT04-07\r\n] 2006.169.07:40:25.91#ibcon#*before write, iclass 13, count 2 2006.169.07:40:25.91#ibcon#enter sib2, iclass 13, count 2 2006.169.07:40:25.91#ibcon#flushed, iclass 13, count 2 2006.169.07:40:25.91#ibcon#about to write, iclass 13, count 2 2006.169.07:40:25.91#ibcon#wrote, iclass 13, count 2 2006.169.07:40:25.91#ibcon#about to read 3, iclass 13, count 2 2006.169.07:40:25.94#ibcon#read 3, iclass 13, count 2 2006.169.07:40:25.94#ibcon#about to read 4, iclass 13, count 2 2006.169.07:40:25.94#ibcon#read 4, iclass 13, count 2 2006.169.07:40:25.94#ibcon#about to read 5, iclass 13, count 2 2006.169.07:40:25.94#ibcon#read 5, iclass 13, count 2 2006.169.07:40:25.94#ibcon#about to read 6, iclass 13, count 2 2006.169.07:40:25.94#ibcon#read 6, iclass 13, count 2 2006.169.07:40:25.94#ibcon#end of sib2, iclass 13, count 2 2006.169.07:40:25.94#ibcon#*after write, iclass 13, count 2 2006.169.07:40:25.94#ibcon#*before return 0, iclass 13, count 2 2006.169.07:40:25.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.169.07:40:25.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.169.07:40:25.94#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.169.07:40:25.94#ibcon#ireg 7 cls_cnt 0 2006.169.07:40:25.94#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.169.07:40:26.06#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.169.07:40:26.06#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.169.07:40:26.06#ibcon#enter wrdev, iclass 13, count 0 2006.169.07:40:26.06#ibcon#first serial, iclass 13, count 0 2006.169.07:40:26.06#ibcon#enter sib2, iclass 13, count 0 2006.169.07:40:26.06#ibcon#flushed, iclass 13, count 0 2006.169.07:40:26.06#ibcon#about to write, iclass 13, count 0 2006.169.07:40:26.06#ibcon#wrote, iclass 13, count 0 2006.169.07:40:26.06#ibcon#about to read 3, iclass 13, count 0 2006.169.07:40:26.08#ibcon#read 3, iclass 13, count 0 2006.169.07:40:26.08#ibcon#about to read 4, iclass 13, count 0 2006.169.07:40:26.08#ibcon#read 4, iclass 13, count 0 2006.169.07:40:26.08#ibcon#about to read 5, iclass 13, count 0 2006.169.07:40:26.08#ibcon#read 5, iclass 13, count 0 2006.169.07:40:26.08#ibcon#about to read 6, iclass 13, count 0 2006.169.07:40:26.08#ibcon#read 6, iclass 13, count 0 2006.169.07:40:26.08#ibcon#end of sib2, iclass 13, count 0 2006.169.07:40:26.08#ibcon#*mode == 0, iclass 13, count 0 2006.169.07:40:26.08#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.07:40:26.08#ibcon#[25=USB\r\n] 2006.169.07:40:26.08#ibcon#*before write, iclass 13, count 0 2006.169.07:40:26.08#ibcon#enter sib2, iclass 13, count 0 2006.169.07:40:26.08#ibcon#flushed, iclass 13, count 0 2006.169.07:40:26.08#ibcon#about to write, iclass 13, count 0 2006.169.07:40:26.08#ibcon#wrote, iclass 13, count 0 2006.169.07:40:26.08#ibcon#about to read 3, iclass 13, count 0 2006.169.07:40:26.11#ibcon#read 3, iclass 13, count 0 2006.169.07:40:26.11#ibcon#about to read 4, iclass 13, count 0 2006.169.07:40:26.11#ibcon#read 4, iclass 13, count 0 2006.169.07:40:26.11#ibcon#about to read 5, iclass 13, count 0 2006.169.07:40:26.11#ibcon#read 5, iclass 13, count 0 2006.169.07:40:26.11#ibcon#about to read 6, iclass 13, count 0 2006.169.07:40:26.11#ibcon#read 6, iclass 13, count 0 2006.169.07:40:26.11#ibcon#end of sib2, iclass 13, count 0 2006.169.07:40:26.11#ibcon#*after write, iclass 13, count 0 2006.169.07:40:26.11#ibcon#*before return 0, iclass 13, count 0 2006.169.07:40:26.11#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.169.07:40:26.11#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.169.07:40:26.11#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.07:40:26.11#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.07:40:26.11$vc4f8/valo=5,652.99 2006.169.07:40:26.11#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.169.07:40:26.11#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.169.07:40:26.11#ibcon#ireg 17 cls_cnt 0 2006.169.07:40:26.11#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:40:26.11#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:40:26.11#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:40:26.11#ibcon#enter wrdev, iclass 15, count 0 2006.169.07:40:26.12#ibcon#first serial, iclass 15, count 0 2006.169.07:40:26.12#ibcon#enter sib2, iclass 15, count 0 2006.169.07:40:26.12#ibcon#flushed, iclass 15, count 0 2006.169.07:40:26.12#ibcon#about to write, iclass 15, count 0 2006.169.07:40:26.12#ibcon#wrote, iclass 15, count 0 2006.169.07:40:26.12#ibcon#about to read 3, iclass 15, count 0 2006.169.07:40:26.13#ibcon#read 3, iclass 15, count 0 2006.169.07:40:26.13#ibcon#about to read 4, iclass 15, count 0 2006.169.07:40:26.13#ibcon#read 4, iclass 15, count 0 2006.169.07:40:26.13#ibcon#about to read 5, iclass 15, count 0 2006.169.07:40:26.13#ibcon#read 5, iclass 15, count 0 2006.169.07:40:26.13#ibcon#about to read 6, iclass 15, count 0 2006.169.07:40:26.13#ibcon#read 6, iclass 15, count 0 2006.169.07:40:26.13#ibcon#end of sib2, iclass 15, count 0 2006.169.07:40:26.13#ibcon#*mode == 0, iclass 15, count 0 2006.169.07:40:26.13#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.169.07:40:26.13#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.07:40:26.13#ibcon#*before write, iclass 15, count 0 2006.169.07:40:26.13#ibcon#enter sib2, iclass 15, count 0 2006.169.07:40:26.13#ibcon#flushed, iclass 15, count 0 2006.169.07:40:26.13#ibcon#about to write, iclass 15, count 0 2006.169.07:40:26.13#ibcon#wrote, iclass 15, count 0 2006.169.07:40:26.13#ibcon#about to read 3, iclass 15, count 0 2006.169.07:40:26.17#ibcon#read 3, iclass 15, count 0 2006.169.07:40:26.17#ibcon#about to read 4, iclass 15, count 0 2006.169.07:40:26.17#ibcon#read 4, iclass 15, count 0 2006.169.07:40:26.17#ibcon#about to read 5, iclass 15, count 0 2006.169.07:40:26.17#ibcon#read 5, iclass 15, count 0 2006.169.07:40:26.17#ibcon#about to read 6, iclass 15, count 0 2006.169.07:40:26.17#ibcon#read 6, iclass 15, count 0 2006.169.07:40:26.17#ibcon#end of sib2, iclass 15, count 0 2006.169.07:40:26.17#ibcon#*after write, iclass 15, count 0 2006.169.07:40:26.17#ibcon#*before return 0, iclass 15, count 0 2006.169.07:40:26.17#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:40:26.17#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:40:26.17#ibcon#about to clear, iclass 15 cls_cnt 0 2006.169.07:40:26.17#ibcon#cleared, iclass 15 cls_cnt 0 2006.169.07:40:26.17$vc4f8/va=5,7 2006.169.07:40:26.17#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.169.07:40:26.17#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.169.07:40:26.17#ibcon#ireg 11 cls_cnt 2 2006.169.07:40:26.17#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.169.07:40:26.23#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.169.07:40:26.23#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.169.07:40:26.23#ibcon#enter wrdev, iclass 17, count 2 2006.169.07:40:26.23#ibcon#first serial, iclass 17, count 2 2006.169.07:40:26.23#ibcon#enter sib2, iclass 17, count 2 2006.169.07:40:26.23#ibcon#flushed, iclass 17, count 2 2006.169.07:40:26.23#ibcon#about to write, iclass 17, count 2 2006.169.07:40:26.23#ibcon#wrote, iclass 17, count 2 2006.169.07:40:26.23#ibcon#about to read 3, iclass 17, count 2 2006.169.07:40:26.25#ibcon#read 3, iclass 17, count 2 2006.169.07:40:26.25#ibcon#about to read 4, iclass 17, count 2 2006.169.07:40:26.25#ibcon#read 4, iclass 17, count 2 2006.169.07:40:26.25#ibcon#about to read 5, iclass 17, count 2 2006.169.07:40:26.25#ibcon#read 5, iclass 17, count 2 2006.169.07:40:26.25#ibcon#about to read 6, iclass 17, count 2 2006.169.07:40:26.25#ibcon#read 6, iclass 17, count 2 2006.169.07:40:26.25#ibcon#end of sib2, iclass 17, count 2 2006.169.07:40:26.25#ibcon#*mode == 0, iclass 17, count 2 2006.169.07:40:26.25#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.169.07:40:26.25#ibcon#[25=AT05-07\r\n] 2006.169.07:40:26.25#ibcon#*before write, iclass 17, count 2 2006.169.07:40:26.25#ibcon#enter sib2, iclass 17, count 2 2006.169.07:40:26.25#ibcon#flushed, iclass 17, count 2 2006.169.07:40:26.25#ibcon#about to write, iclass 17, count 2 2006.169.07:40:26.25#ibcon#wrote, iclass 17, count 2 2006.169.07:40:26.25#ibcon#about to read 3, iclass 17, count 2 2006.169.07:40:26.28#ibcon#read 3, iclass 17, count 2 2006.169.07:40:26.28#ibcon#about to read 4, iclass 17, count 2 2006.169.07:40:26.28#ibcon#read 4, iclass 17, count 2 2006.169.07:40:26.28#ibcon#about to read 5, iclass 17, count 2 2006.169.07:40:26.28#ibcon#read 5, iclass 17, count 2 2006.169.07:40:26.28#ibcon#about to read 6, iclass 17, count 2 2006.169.07:40:26.28#ibcon#read 6, iclass 17, count 2 2006.169.07:40:26.28#ibcon#end of sib2, iclass 17, count 2 2006.169.07:40:26.28#ibcon#*after write, iclass 17, count 2 2006.169.07:40:26.28#ibcon#*before return 0, iclass 17, count 2 2006.169.07:40:26.28#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.169.07:40:26.28#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.169.07:40:26.28#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.169.07:40:26.28#ibcon#ireg 7 cls_cnt 0 2006.169.07:40:26.28#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.169.07:40:26.40#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.169.07:40:26.40#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.169.07:40:26.40#ibcon#enter wrdev, iclass 17, count 0 2006.169.07:40:26.40#ibcon#first serial, iclass 17, count 0 2006.169.07:40:26.40#ibcon#enter sib2, iclass 17, count 0 2006.169.07:40:26.40#ibcon#flushed, iclass 17, count 0 2006.169.07:40:26.40#ibcon#about to write, iclass 17, count 0 2006.169.07:40:26.40#ibcon#wrote, iclass 17, count 0 2006.169.07:40:26.40#ibcon#about to read 3, iclass 17, count 0 2006.169.07:40:26.42#ibcon#read 3, iclass 17, count 0 2006.169.07:40:26.42#ibcon#about to read 4, iclass 17, count 0 2006.169.07:40:26.42#ibcon#read 4, iclass 17, count 0 2006.169.07:40:26.42#ibcon#about to read 5, iclass 17, count 0 2006.169.07:40:26.42#ibcon#read 5, iclass 17, count 0 2006.169.07:40:26.42#ibcon#about to read 6, iclass 17, count 0 2006.169.07:40:26.42#ibcon#read 6, iclass 17, count 0 2006.169.07:40:26.42#ibcon#end of sib2, iclass 17, count 0 2006.169.07:40:26.42#ibcon#*mode == 0, iclass 17, count 0 2006.169.07:40:26.42#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.169.07:40:26.42#ibcon#[25=USB\r\n] 2006.169.07:40:26.42#ibcon#*before write, iclass 17, count 0 2006.169.07:40:26.42#ibcon#enter sib2, iclass 17, count 0 2006.169.07:40:26.42#ibcon#flushed, iclass 17, count 0 2006.169.07:40:26.42#ibcon#about to write, iclass 17, count 0 2006.169.07:40:26.42#ibcon#wrote, iclass 17, count 0 2006.169.07:40:26.42#ibcon#about to read 3, iclass 17, count 0 2006.169.07:40:26.45#ibcon#read 3, iclass 17, count 0 2006.169.07:40:26.45#ibcon#about to read 4, iclass 17, count 0 2006.169.07:40:26.45#ibcon#read 4, iclass 17, count 0 2006.169.07:40:26.45#ibcon#about to read 5, iclass 17, count 0 2006.169.07:40:26.45#ibcon#read 5, iclass 17, count 0 2006.169.07:40:26.45#ibcon#about to read 6, iclass 17, count 0 2006.169.07:40:26.45#ibcon#read 6, iclass 17, count 0 2006.169.07:40:26.45#ibcon#end of sib2, iclass 17, count 0 2006.169.07:40:26.45#ibcon#*after write, iclass 17, count 0 2006.169.07:40:26.45#ibcon#*before return 0, iclass 17, count 0 2006.169.07:40:26.45#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.169.07:40:26.45#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.169.07:40:26.45#ibcon#about to clear, iclass 17 cls_cnt 0 2006.169.07:40:26.45#ibcon#cleared, iclass 17 cls_cnt 0 2006.169.07:40:26.45$vc4f8/valo=6,772.99 2006.169.07:40:26.45#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.169.07:40:26.45#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.169.07:40:26.45#ibcon#ireg 17 cls_cnt 0 2006.169.07:40:26.45#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.169.07:40:26.45#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.169.07:40:26.45#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.169.07:40:26.45#ibcon#enter wrdev, iclass 19, count 0 2006.169.07:40:26.45#ibcon#first serial, iclass 19, count 0 2006.169.07:40:26.46#ibcon#enter sib2, iclass 19, count 0 2006.169.07:40:26.46#ibcon#flushed, iclass 19, count 0 2006.169.07:40:26.46#ibcon#about to write, iclass 19, count 0 2006.169.07:40:26.46#ibcon#wrote, iclass 19, count 0 2006.169.07:40:26.46#ibcon#about to read 3, iclass 19, count 0 2006.169.07:40:26.47#ibcon#read 3, iclass 19, count 0 2006.169.07:40:26.47#ibcon#about to read 4, iclass 19, count 0 2006.169.07:40:26.47#ibcon#read 4, iclass 19, count 0 2006.169.07:40:26.47#ibcon#about to read 5, iclass 19, count 0 2006.169.07:40:26.47#ibcon#read 5, iclass 19, count 0 2006.169.07:40:26.47#ibcon#about to read 6, iclass 19, count 0 2006.169.07:40:26.47#ibcon#read 6, iclass 19, count 0 2006.169.07:40:26.47#ibcon#end of sib2, iclass 19, count 0 2006.169.07:40:26.47#ibcon#*mode == 0, iclass 19, count 0 2006.169.07:40:26.47#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.169.07:40:26.47#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.07:40:26.47#ibcon#*before write, iclass 19, count 0 2006.169.07:40:26.47#ibcon#enter sib2, iclass 19, count 0 2006.169.07:40:26.47#ibcon#flushed, iclass 19, count 0 2006.169.07:40:26.47#ibcon#about to write, iclass 19, count 0 2006.169.07:40:26.47#ibcon#wrote, iclass 19, count 0 2006.169.07:40:26.47#ibcon#about to read 3, iclass 19, count 0 2006.169.07:40:26.51#ibcon#read 3, iclass 19, count 0 2006.169.07:40:26.51#ibcon#about to read 4, iclass 19, count 0 2006.169.07:40:26.51#ibcon#read 4, iclass 19, count 0 2006.169.07:40:26.51#ibcon#about to read 5, iclass 19, count 0 2006.169.07:40:26.51#ibcon#read 5, iclass 19, count 0 2006.169.07:40:26.51#ibcon#about to read 6, iclass 19, count 0 2006.169.07:40:26.51#ibcon#read 6, iclass 19, count 0 2006.169.07:40:26.51#ibcon#end of sib2, iclass 19, count 0 2006.169.07:40:26.51#ibcon#*after write, iclass 19, count 0 2006.169.07:40:26.51#ibcon#*before return 0, iclass 19, count 0 2006.169.07:40:26.51#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.169.07:40:26.51#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.169.07:40:26.51#ibcon#about to clear, iclass 19 cls_cnt 0 2006.169.07:40:26.51#ibcon#cleared, iclass 19 cls_cnt 0 2006.169.07:40:26.51$vc4f8/va=6,6 2006.169.07:40:26.51#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.169.07:40:26.51#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.169.07:40:26.51#ibcon#ireg 11 cls_cnt 2 2006.169.07:40:26.51#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.169.07:40:26.57#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.169.07:40:26.57#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.169.07:40:26.57#ibcon#enter wrdev, iclass 21, count 2 2006.169.07:40:26.57#ibcon#first serial, iclass 21, count 2 2006.169.07:40:26.57#ibcon#enter sib2, iclass 21, count 2 2006.169.07:40:26.57#ibcon#flushed, iclass 21, count 2 2006.169.07:40:26.57#ibcon#about to write, iclass 21, count 2 2006.169.07:40:26.57#ibcon#wrote, iclass 21, count 2 2006.169.07:40:26.57#ibcon#about to read 3, iclass 21, count 2 2006.169.07:40:26.59#ibcon#read 3, iclass 21, count 2 2006.169.07:40:26.59#ibcon#about to read 4, iclass 21, count 2 2006.169.07:40:26.59#ibcon#read 4, iclass 21, count 2 2006.169.07:40:26.59#ibcon#about to read 5, iclass 21, count 2 2006.169.07:40:26.59#ibcon#read 5, iclass 21, count 2 2006.169.07:40:26.59#ibcon#about to read 6, iclass 21, count 2 2006.169.07:40:26.59#ibcon#read 6, iclass 21, count 2 2006.169.07:40:26.59#ibcon#end of sib2, iclass 21, count 2 2006.169.07:40:26.59#ibcon#*mode == 0, iclass 21, count 2 2006.169.07:40:26.59#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.169.07:40:26.59#ibcon#[25=AT06-06\r\n] 2006.169.07:40:26.59#ibcon#*before write, iclass 21, count 2 2006.169.07:40:26.59#ibcon#enter sib2, iclass 21, count 2 2006.169.07:40:26.59#ibcon#flushed, iclass 21, count 2 2006.169.07:40:26.59#ibcon#about to write, iclass 21, count 2 2006.169.07:40:26.59#ibcon#wrote, iclass 21, count 2 2006.169.07:40:26.59#ibcon#about to read 3, iclass 21, count 2 2006.169.07:40:26.62#ibcon#read 3, iclass 21, count 2 2006.169.07:40:26.62#ibcon#about to read 4, iclass 21, count 2 2006.169.07:40:26.62#ibcon#read 4, iclass 21, count 2 2006.169.07:40:26.62#ibcon#about to read 5, iclass 21, count 2 2006.169.07:40:26.62#ibcon#read 5, iclass 21, count 2 2006.169.07:40:26.62#ibcon#about to read 6, iclass 21, count 2 2006.169.07:40:26.62#ibcon#read 6, iclass 21, count 2 2006.169.07:40:26.62#ibcon#end of sib2, iclass 21, count 2 2006.169.07:40:26.62#ibcon#*after write, iclass 21, count 2 2006.169.07:40:26.62#ibcon#*before return 0, iclass 21, count 2 2006.169.07:40:26.62#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.169.07:40:26.62#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.169.07:40:26.62#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.169.07:40:26.62#ibcon#ireg 7 cls_cnt 0 2006.169.07:40:26.62#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.169.07:40:26.74#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.169.07:40:26.74#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.169.07:40:26.74#ibcon#enter wrdev, iclass 21, count 0 2006.169.07:40:26.74#ibcon#first serial, iclass 21, count 0 2006.169.07:40:26.74#ibcon#enter sib2, iclass 21, count 0 2006.169.07:40:26.74#ibcon#flushed, iclass 21, count 0 2006.169.07:40:26.74#ibcon#about to write, iclass 21, count 0 2006.169.07:40:26.74#ibcon#wrote, iclass 21, count 0 2006.169.07:40:26.74#ibcon#about to read 3, iclass 21, count 0 2006.169.07:40:26.76#ibcon#read 3, iclass 21, count 0 2006.169.07:40:26.76#ibcon#about to read 4, iclass 21, count 0 2006.169.07:40:26.76#ibcon#read 4, iclass 21, count 0 2006.169.07:40:26.76#ibcon#about to read 5, iclass 21, count 0 2006.169.07:40:26.76#ibcon#read 5, iclass 21, count 0 2006.169.07:40:26.76#ibcon#about to read 6, iclass 21, count 0 2006.169.07:40:26.76#ibcon#read 6, iclass 21, count 0 2006.169.07:40:26.76#ibcon#end of sib2, iclass 21, count 0 2006.169.07:40:26.76#ibcon#*mode == 0, iclass 21, count 0 2006.169.07:40:26.76#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.169.07:40:26.76#ibcon#[25=USB\r\n] 2006.169.07:40:26.76#ibcon#*before write, iclass 21, count 0 2006.169.07:40:26.76#ibcon#enter sib2, iclass 21, count 0 2006.169.07:40:26.76#ibcon#flushed, iclass 21, count 0 2006.169.07:40:26.76#ibcon#about to write, iclass 21, count 0 2006.169.07:40:26.76#ibcon#wrote, iclass 21, count 0 2006.169.07:40:26.76#ibcon#about to read 3, iclass 21, count 0 2006.169.07:40:26.79#ibcon#read 3, iclass 21, count 0 2006.169.07:40:26.79#ibcon#about to read 4, iclass 21, count 0 2006.169.07:40:26.79#ibcon#read 4, iclass 21, count 0 2006.169.07:40:26.79#ibcon#about to read 5, iclass 21, count 0 2006.169.07:40:26.79#ibcon#read 5, iclass 21, count 0 2006.169.07:40:26.79#ibcon#about to read 6, iclass 21, count 0 2006.169.07:40:26.79#ibcon#read 6, iclass 21, count 0 2006.169.07:40:26.79#ibcon#end of sib2, iclass 21, count 0 2006.169.07:40:26.79#ibcon#*after write, iclass 21, count 0 2006.169.07:40:26.79#ibcon#*before return 0, iclass 21, count 0 2006.169.07:40:26.79#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.169.07:40:26.79#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.169.07:40:26.79#ibcon#about to clear, iclass 21 cls_cnt 0 2006.169.07:40:26.79#ibcon#cleared, iclass 21 cls_cnt 0 2006.169.07:40:26.79$vc4f8/valo=7,832.99 2006.169.07:40:26.79#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.169.07:40:26.79#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.169.07:40:26.79#ibcon#ireg 17 cls_cnt 0 2006.169.07:40:26.79#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.169.07:40:26.79#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.169.07:40:26.79#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.169.07:40:26.79#ibcon#enter wrdev, iclass 23, count 0 2006.169.07:40:26.79#ibcon#first serial, iclass 23, count 0 2006.169.07:40:26.79#ibcon#enter sib2, iclass 23, count 0 2006.169.07:40:26.80#ibcon#flushed, iclass 23, count 0 2006.169.07:40:26.80#ibcon#about to write, iclass 23, count 0 2006.169.07:40:26.80#ibcon#wrote, iclass 23, count 0 2006.169.07:40:26.80#ibcon#about to read 3, iclass 23, count 0 2006.169.07:40:26.81#ibcon#read 3, iclass 23, count 0 2006.169.07:40:26.81#ibcon#about to read 4, iclass 23, count 0 2006.169.07:40:26.81#ibcon#read 4, iclass 23, count 0 2006.169.07:40:26.81#ibcon#about to read 5, iclass 23, count 0 2006.169.07:40:26.81#ibcon#read 5, iclass 23, count 0 2006.169.07:40:26.81#ibcon#about to read 6, iclass 23, count 0 2006.169.07:40:26.81#ibcon#read 6, iclass 23, count 0 2006.169.07:40:26.81#ibcon#end of sib2, iclass 23, count 0 2006.169.07:40:26.81#ibcon#*mode == 0, iclass 23, count 0 2006.169.07:40:26.81#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.169.07:40:26.81#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.07:40:26.81#ibcon#*before write, iclass 23, count 0 2006.169.07:40:26.81#ibcon#enter sib2, iclass 23, count 0 2006.169.07:40:26.81#ibcon#flushed, iclass 23, count 0 2006.169.07:40:26.81#ibcon#about to write, iclass 23, count 0 2006.169.07:40:26.81#ibcon#wrote, iclass 23, count 0 2006.169.07:40:26.81#ibcon#about to read 3, iclass 23, count 0 2006.169.07:40:26.85#ibcon#read 3, iclass 23, count 0 2006.169.07:40:26.85#ibcon#about to read 4, iclass 23, count 0 2006.169.07:40:26.85#ibcon#read 4, iclass 23, count 0 2006.169.07:40:26.85#ibcon#about to read 5, iclass 23, count 0 2006.169.07:40:26.85#ibcon#read 5, iclass 23, count 0 2006.169.07:40:26.85#ibcon#about to read 6, iclass 23, count 0 2006.169.07:40:26.85#ibcon#read 6, iclass 23, count 0 2006.169.07:40:26.85#ibcon#end of sib2, iclass 23, count 0 2006.169.07:40:26.85#ibcon#*after write, iclass 23, count 0 2006.169.07:40:26.85#ibcon#*before return 0, iclass 23, count 0 2006.169.07:40:26.85#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.169.07:40:26.85#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.169.07:40:26.85#ibcon#about to clear, iclass 23 cls_cnt 0 2006.169.07:40:26.85#ibcon#cleared, iclass 23 cls_cnt 0 2006.169.07:40:26.85$vc4f8/va=7,6 2006.169.07:40:26.85#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.169.07:40:26.85#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.169.07:40:26.85#ibcon#ireg 11 cls_cnt 2 2006.169.07:40:26.85#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.169.07:40:26.92#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.169.07:40:26.92#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.169.07:40:26.92#ibcon#enter wrdev, iclass 25, count 2 2006.169.07:40:26.92#ibcon#first serial, iclass 25, count 2 2006.169.07:40:26.92#ibcon#enter sib2, iclass 25, count 2 2006.169.07:40:26.92#ibcon#flushed, iclass 25, count 2 2006.169.07:40:26.92#ibcon#about to write, iclass 25, count 2 2006.169.07:40:26.92#ibcon#wrote, iclass 25, count 2 2006.169.07:40:26.92#ibcon#about to read 3, iclass 25, count 2 2006.169.07:40:26.94#ibcon#read 3, iclass 25, count 2 2006.169.07:40:26.94#ibcon#about to read 4, iclass 25, count 2 2006.169.07:40:26.94#ibcon#read 4, iclass 25, count 2 2006.169.07:40:26.94#ibcon#about to read 5, iclass 25, count 2 2006.169.07:40:26.94#ibcon#read 5, iclass 25, count 2 2006.169.07:40:26.94#ibcon#about to read 6, iclass 25, count 2 2006.169.07:40:26.94#ibcon#read 6, iclass 25, count 2 2006.169.07:40:26.94#ibcon#end of sib2, iclass 25, count 2 2006.169.07:40:26.94#ibcon#*mode == 0, iclass 25, count 2 2006.169.07:40:26.94#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.169.07:40:26.94#ibcon#[25=AT07-06\r\n] 2006.169.07:40:26.94#ibcon#*before write, iclass 25, count 2 2006.169.07:40:26.94#ibcon#enter sib2, iclass 25, count 2 2006.169.07:40:26.94#ibcon#flushed, iclass 25, count 2 2006.169.07:40:26.94#ibcon#about to write, iclass 25, count 2 2006.169.07:40:26.94#ibcon#wrote, iclass 25, count 2 2006.169.07:40:26.94#ibcon#about to read 3, iclass 25, count 2 2006.169.07:40:26.96#ibcon#read 3, iclass 25, count 2 2006.169.07:40:26.96#ibcon#about to read 4, iclass 25, count 2 2006.169.07:40:26.96#ibcon#read 4, iclass 25, count 2 2006.169.07:40:26.96#ibcon#about to read 5, iclass 25, count 2 2006.169.07:40:26.96#ibcon#read 5, iclass 25, count 2 2006.169.07:40:26.96#ibcon#about to read 6, iclass 25, count 2 2006.169.07:40:26.96#ibcon#read 6, iclass 25, count 2 2006.169.07:40:26.96#ibcon#end of sib2, iclass 25, count 2 2006.169.07:40:26.96#ibcon#*after write, iclass 25, count 2 2006.169.07:40:26.96#ibcon#*before return 0, iclass 25, count 2 2006.169.07:40:26.96#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.169.07:40:26.96#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.169.07:40:26.96#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.169.07:40:26.96#ibcon#ireg 7 cls_cnt 0 2006.169.07:40:26.96#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.169.07:40:27.08#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.169.07:40:27.08#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.169.07:40:27.08#ibcon#enter wrdev, iclass 25, count 0 2006.169.07:40:27.08#ibcon#first serial, iclass 25, count 0 2006.169.07:40:27.08#ibcon#enter sib2, iclass 25, count 0 2006.169.07:40:27.08#ibcon#flushed, iclass 25, count 0 2006.169.07:40:27.08#ibcon#about to write, iclass 25, count 0 2006.169.07:40:27.08#ibcon#wrote, iclass 25, count 0 2006.169.07:40:27.08#ibcon#about to read 3, iclass 25, count 0 2006.169.07:40:27.11#ibcon#read 3, iclass 25, count 0 2006.169.07:40:27.11#ibcon#about to read 4, iclass 25, count 0 2006.169.07:40:27.11#ibcon#read 4, iclass 25, count 0 2006.169.07:40:27.11#ibcon#about to read 5, iclass 25, count 0 2006.169.07:40:27.11#ibcon#read 5, iclass 25, count 0 2006.169.07:40:27.11#ibcon#about to read 6, iclass 25, count 0 2006.169.07:40:27.11#ibcon#read 6, iclass 25, count 0 2006.169.07:40:27.11#ibcon#end of sib2, iclass 25, count 0 2006.169.07:40:27.11#ibcon#*mode == 0, iclass 25, count 0 2006.169.07:40:27.11#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.169.07:40:27.11#ibcon#[25=USB\r\n] 2006.169.07:40:27.11#ibcon#*before write, iclass 25, count 0 2006.169.07:40:27.11#ibcon#enter sib2, iclass 25, count 0 2006.169.07:40:27.11#ibcon#flushed, iclass 25, count 0 2006.169.07:40:27.11#ibcon#about to write, iclass 25, count 0 2006.169.07:40:27.11#ibcon#wrote, iclass 25, count 0 2006.169.07:40:27.11#ibcon#about to read 3, iclass 25, count 0 2006.169.07:40:27.14#ibcon#read 3, iclass 25, count 0 2006.169.07:40:27.14#ibcon#about to read 4, iclass 25, count 0 2006.169.07:40:27.14#ibcon#read 4, iclass 25, count 0 2006.169.07:40:27.14#ibcon#about to read 5, iclass 25, count 0 2006.169.07:40:27.14#ibcon#read 5, iclass 25, count 0 2006.169.07:40:27.14#ibcon#about to read 6, iclass 25, count 0 2006.169.07:40:27.14#ibcon#read 6, iclass 25, count 0 2006.169.07:40:27.14#ibcon#end of sib2, iclass 25, count 0 2006.169.07:40:27.14#ibcon#*after write, iclass 25, count 0 2006.169.07:40:27.14#ibcon#*before return 0, iclass 25, count 0 2006.169.07:40:27.14#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.169.07:40:27.14#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.169.07:40:27.14#ibcon#about to clear, iclass 25 cls_cnt 0 2006.169.07:40:27.14#ibcon#cleared, iclass 25 cls_cnt 0 2006.169.07:40:27.14$vc4f8/valo=8,852.99 2006.169.07:40:27.14#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.169.07:40:27.14#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.169.07:40:27.14#ibcon#ireg 17 cls_cnt 0 2006.169.07:40:27.14#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:40:27.14#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:40:27.15#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:40:27.15#ibcon#enter wrdev, iclass 27, count 0 2006.169.07:40:27.15#ibcon#first serial, iclass 27, count 0 2006.169.07:40:27.15#ibcon#enter sib2, iclass 27, count 0 2006.169.07:40:27.15#ibcon#flushed, iclass 27, count 0 2006.169.07:40:27.15#ibcon#about to write, iclass 27, count 0 2006.169.07:40:27.15#ibcon#wrote, iclass 27, count 0 2006.169.07:40:27.15#ibcon#about to read 3, iclass 27, count 0 2006.169.07:40:27.16#ibcon#read 3, iclass 27, count 0 2006.169.07:40:27.16#ibcon#about to read 4, iclass 27, count 0 2006.169.07:40:27.16#ibcon#read 4, iclass 27, count 0 2006.169.07:40:27.16#ibcon#about to read 5, iclass 27, count 0 2006.169.07:40:27.16#ibcon#read 5, iclass 27, count 0 2006.169.07:40:27.16#ibcon#about to read 6, iclass 27, count 0 2006.169.07:40:27.16#ibcon#read 6, iclass 27, count 0 2006.169.07:40:27.16#ibcon#end of sib2, iclass 27, count 0 2006.169.07:40:27.16#ibcon#*mode == 0, iclass 27, count 0 2006.169.07:40:27.16#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.169.07:40:27.16#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.07:40:27.16#ibcon#*before write, iclass 27, count 0 2006.169.07:40:27.16#ibcon#enter sib2, iclass 27, count 0 2006.169.07:40:27.16#ibcon#flushed, iclass 27, count 0 2006.169.07:40:27.16#ibcon#about to write, iclass 27, count 0 2006.169.07:40:27.16#ibcon#wrote, iclass 27, count 0 2006.169.07:40:27.16#ibcon#about to read 3, iclass 27, count 0 2006.169.07:40:27.20#ibcon#read 3, iclass 27, count 0 2006.169.07:40:27.20#ibcon#about to read 4, iclass 27, count 0 2006.169.07:40:27.20#ibcon#read 4, iclass 27, count 0 2006.169.07:40:27.20#ibcon#about to read 5, iclass 27, count 0 2006.169.07:40:27.20#ibcon#read 5, iclass 27, count 0 2006.169.07:40:27.20#ibcon#about to read 6, iclass 27, count 0 2006.169.07:40:27.20#ibcon#read 6, iclass 27, count 0 2006.169.07:40:27.20#ibcon#end of sib2, iclass 27, count 0 2006.169.07:40:27.20#ibcon#*after write, iclass 27, count 0 2006.169.07:40:27.20#ibcon#*before return 0, iclass 27, count 0 2006.169.07:40:27.20#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:40:27.20#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:40:27.20#ibcon#about to clear, iclass 27 cls_cnt 0 2006.169.07:40:27.20#ibcon#cleared, iclass 27 cls_cnt 0 2006.169.07:40:27.20$vc4f8/va=8,7 2006.169.07:40:27.20#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.169.07:40:27.20#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.169.07:40:27.20#ibcon#ireg 11 cls_cnt 2 2006.169.07:40:27.20#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.169.07:40:27.26#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.169.07:40:27.26#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.169.07:40:27.26#ibcon#enter wrdev, iclass 29, count 2 2006.169.07:40:27.26#ibcon#first serial, iclass 29, count 2 2006.169.07:40:27.26#ibcon#enter sib2, iclass 29, count 2 2006.169.07:40:27.26#ibcon#flushed, iclass 29, count 2 2006.169.07:40:27.26#ibcon#about to write, iclass 29, count 2 2006.169.07:40:27.26#ibcon#wrote, iclass 29, count 2 2006.169.07:40:27.26#ibcon#about to read 3, iclass 29, count 2 2006.169.07:40:27.28#ibcon#read 3, iclass 29, count 2 2006.169.07:40:27.28#ibcon#about to read 4, iclass 29, count 2 2006.169.07:40:27.28#ibcon#read 4, iclass 29, count 2 2006.169.07:40:27.28#ibcon#about to read 5, iclass 29, count 2 2006.169.07:40:27.28#ibcon#read 5, iclass 29, count 2 2006.169.07:40:27.28#ibcon#about to read 6, iclass 29, count 2 2006.169.07:40:27.28#ibcon#read 6, iclass 29, count 2 2006.169.07:40:27.28#ibcon#end of sib2, iclass 29, count 2 2006.169.07:40:27.28#ibcon#*mode == 0, iclass 29, count 2 2006.169.07:40:27.28#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.169.07:40:27.28#ibcon#[25=AT08-07\r\n] 2006.169.07:40:27.28#ibcon#*before write, iclass 29, count 2 2006.169.07:40:27.28#ibcon#enter sib2, iclass 29, count 2 2006.169.07:40:27.28#ibcon#flushed, iclass 29, count 2 2006.169.07:40:27.28#ibcon#about to write, iclass 29, count 2 2006.169.07:40:27.28#ibcon#wrote, iclass 29, count 2 2006.169.07:40:27.28#ibcon#about to read 3, iclass 29, count 2 2006.169.07:40:27.31#ibcon#read 3, iclass 29, count 2 2006.169.07:40:27.31#ibcon#about to read 4, iclass 29, count 2 2006.169.07:40:27.31#ibcon#read 4, iclass 29, count 2 2006.169.07:40:27.31#ibcon#about to read 5, iclass 29, count 2 2006.169.07:40:27.31#ibcon#read 5, iclass 29, count 2 2006.169.07:40:27.31#ibcon#about to read 6, iclass 29, count 2 2006.169.07:40:27.31#ibcon#read 6, iclass 29, count 2 2006.169.07:40:27.31#ibcon#end of sib2, iclass 29, count 2 2006.169.07:40:27.31#ibcon#*after write, iclass 29, count 2 2006.169.07:40:27.31#ibcon#*before return 0, iclass 29, count 2 2006.169.07:40:27.31#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.169.07:40:27.31#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.169.07:40:27.31#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.169.07:40:27.31#ibcon#ireg 7 cls_cnt 0 2006.169.07:40:27.31#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.169.07:40:27.43#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.169.07:40:27.43#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.169.07:40:27.43#ibcon#enter wrdev, iclass 29, count 0 2006.169.07:40:27.43#ibcon#first serial, iclass 29, count 0 2006.169.07:40:27.43#ibcon#enter sib2, iclass 29, count 0 2006.169.07:40:27.43#ibcon#flushed, iclass 29, count 0 2006.169.07:40:27.43#ibcon#about to write, iclass 29, count 0 2006.169.07:40:27.43#ibcon#wrote, iclass 29, count 0 2006.169.07:40:27.43#ibcon#about to read 3, iclass 29, count 0 2006.169.07:40:27.45#ibcon#read 3, iclass 29, count 0 2006.169.07:40:27.45#ibcon#about to read 4, iclass 29, count 0 2006.169.07:40:27.45#ibcon#read 4, iclass 29, count 0 2006.169.07:40:27.45#ibcon#about to read 5, iclass 29, count 0 2006.169.07:40:27.45#ibcon#read 5, iclass 29, count 0 2006.169.07:40:27.45#ibcon#about to read 6, iclass 29, count 0 2006.169.07:40:27.45#ibcon#read 6, iclass 29, count 0 2006.169.07:40:27.45#ibcon#end of sib2, iclass 29, count 0 2006.169.07:40:27.45#ibcon#*mode == 0, iclass 29, count 0 2006.169.07:40:27.45#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.169.07:40:27.45#ibcon#[25=USB\r\n] 2006.169.07:40:27.45#ibcon#*before write, iclass 29, count 0 2006.169.07:40:27.45#ibcon#enter sib2, iclass 29, count 0 2006.169.07:40:27.45#ibcon#flushed, iclass 29, count 0 2006.169.07:40:27.45#ibcon#about to write, iclass 29, count 0 2006.169.07:40:27.45#ibcon#wrote, iclass 29, count 0 2006.169.07:40:27.45#ibcon#about to read 3, iclass 29, count 0 2006.169.07:40:27.48#ibcon#read 3, iclass 29, count 0 2006.169.07:40:27.48#ibcon#about to read 4, iclass 29, count 0 2006.169.07:40:27.48#ibcon#read 4, iclass 29, count 0 2006.169.07:40:27.48#ibcon#about to read 5, iclass 29, count 0 2006.169.07:40:27.48#ibcon#read 5, iclass 29, count 0 2006.169.07:40:27.48#ibcon#about to read 6, iclass 29, count 0 2006.169.07:40:27.48#ibcon#read 6, iclass 29, count 0 2006.169.07:40:27.48#ibcon#end of sib2, iclass 29, count 0 2006.169.07:40:27.48#ibcon#*after write, iclass 29, count 0 2006.169.07:40:27.48#ibcon#*before return 0, iclass 29, count 0 2006.169.07:40:27.48#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.169.07:40:27.48#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.169.07:40:27.48#ibcon#about to clear, iclass 29 cls_cnt 0 2006.169.07:40:27.48#ibcon#cleared, iclass 29 cls_cnt 0 2006.169.07:40:27.48$vc4f8/vblo=1,632.99 2006.169.07:40:27.48#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.169.07:40:27.48#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.169.07:40:27.48#ibcon#ireg 17 cls_cnt 0 2006.169.07:40:27.48#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.169.07:40:27.48#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.169.07:40:27.48#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.169.07:40:27.48#ibcon#enter wrdev, iclass 31, count 0 2006.169.07:40:27.49#ibcon#first serial, iclass 31, count 0 2006.169.07:40:27.49#ibcon#enter sib2, iclass 31, count 0 2006.169.07:40:27.49#ibcon#flushed, iclass 31, count 0 2006.169.07:40:27.49#ibcon#about to write, iclass 31, count 0 2006.169.07:40:27.49#ibcon#wrote, iclass 31, count 0 2006.169.07:40:27.49#ibcon#about to read 3, iclass 31, count 0 2006.169.07:40:27.50#ibcon#read 3, iclass 31, count 0 2006.169.07:40:27.50#ibcon#about to read 4, iclass 31, count 0 2006.169.07:40:27.50#ibcon#read 4, iclass 31, count 0 2006.169.07:40:27.50#ibcon#about to read 5, iclass 31, count 0 2006.169.07:40:27.50#ibcon#read 5, iclass 31, count 0 2006.169.07:40:27.50#ibcon#about to read 6, iclass 31, count 0 2006.169.07:40:27.50#ibcon#read 6, iclass 31, count 0 2006.169.07:40:27.50#ibcon#end of sib2, iclass 31, count 0 2006.169.07:40:27.50#ibcon#*mode == 0, iclass 31, count 0 2006.169.07:40:27.50#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.169.07:40:27.50#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.07:40:27.50#ibcon#*before write, iclass 31, count 0 2006.169.07:40:27.50#ibcon#enter sib2, iclass 31, count 0 2006.169.07:40:27.50#ibcon#flushed, iclass 31, count 0 2006.169.07:40:27.50#ibcon#about to write, iclass 31, count 0 2006.169.07:40:27.50#ibcon#wrote, iclass 31, count 0 2006.169.07:40:27.50#ibcon#about to read 3, iclass 31, count 0 2006.169.07:40:27.54#ibcon#read 3, iclass 31, count 0 2006.169.07:40:27.54#ibcon#about to read 4, iclass 31, count 0 2006.169.07:40:27.54#ibcon#read 4, iclass 31, count 0 2006.169.07:40:27.54#ibcon#about to read 5, iclass 31, count 0 2006.169.07:40:27.54#ibcon#read 5, iclass 31, count 0 2006.169.07:40:27.54#ibcon#about to read 6, iclass 31, count 0 2006.169.07:40:27.54#ibcon#read 6, iclass 31, count 0 2006.169.07:40:27.54#ibcon#end of sib2, iclass 31, count 0 2006.169.07:40:27.54#ibcon#*after write, iclass 31, count 0 2006.169.07:40:27.54#ibcon#*before return 0, iclass 31, count 0 2006.169.07:40:27.54#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.169.07:40:27.54#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.169.07:40:27.54#ibcon#about to clear, iclass 31 cls_cnt 0 2006.169.07:40:27.54#ibcon#cleared, iclass 31 cls_cnt 0 2006.169.07:40:27.54$vc4f8/vb=1,4 2006.169.07:40:27.54#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.169.07:40:27.54#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.169.07:40:27.54#ibcon#ireg 11 cls_cnt 2 2006.169.07:40:27.54#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.169.07:40:27.54#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.169.07:40:27.54#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.169.07:40:27.54#ibcon#enter wrdev, iclass 33, count 2 2006.169.07:40:27.54#ibcon#first serial, iclass 33, count 2 2006.169.07:40:27.54#ibcon#enter sib2, iclass 33, count 2 2006.169.07:40:27.55#ibcon#flushed, iclass 33, count 2 2006.169.07:40:27.55#ibcon#about to write, iclass 33, count 2 2006.169.07:40:27.55#ibcon#wrote, iclass 33, count 2 2006.169.07:40:27.55#ibcon#about to read 3, iclass 33, count 2 2006.169.07:40:27.56#ibcon#read 3, iclass 33, count 2 2006.169.07:40:27.56#ibcon#about to read 4, iclass 33, count 2 2006.169.07:40:27.56#ibcon#read 4, iclass 33, count 2 2006.169.07:40:27.56#ibcon#about to read 5, iclass 33, count 2 2006.169.07:40:27.56#ibcon#read 5, iclass 33, count 2 2006.169.07:40:27.56#ibcon#about to read 6, iclass 33, count 2 2006.169.07:40:27.56#ibcon#read 6, iclass 33, count 2 2006.169.07:40:27.56#ibcon#end of sib2, iclass 33, count 2 2006.169.07:40:27.56#ibcon#*mode == 0, iclass 33, count 2 2006.169.07:40:27.56#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.169.07:40:27.56#ibcon#[27=AT01-04\r\n] 2006.169.07:40:27.56#ibcon#*before write, iclass 33, count 2 2006.169.07:40:27.56#ibcon#enter sib2, iclass 33, count 2 2006.169.07:40:27.56#ibcon#flushed, iclass 33, count 2 2006.169.07:40:27.56#ibcon#about to write, iclass 33, count 2 2006.169.07:40:27.56#ibcon#wrote, iclass 33, count 2 2006.169.07:40:27.56#ibcon#about to read 3, iclass 33, count 2 2006.169.07:40:27.59#ibcon#read 3, iclass 33, count 2 2006.169.07:40:27.59#ibcon#about to read 4, iclass 33, count 2 2006.169.07:40:27.59#ibcon#read 4, iclass 33, count 2 2006.169.07:40:27.59#ibcon#about to read 5, iclass 33, count 2 2006.169.07:40:27.59#ibcon#read 5, iclass 33, count 2 2006.169.07:40:27.59#ibcon#about to read 6, iclass 33, count 2 2006.169.07:40:27.59#ibcon#read 6, iclass 33, count 2 2006.169.07:40:27.59#ibcon#end of sib2, iclass 33, count 2 2006.169.07:40:27.59#ibcon#*after write, iclass 33, count 2 2006.169.07:40:27.59#ibcon#*before return 0, iclass 33, count 2 2006.169.07:40:27.59#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.169.07:40:27.59#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.169.07:40:27.59#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.169.07:40:27.59#ibcon#ireg 7 cls_cnt 0 2006.169.07:40:27.59#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.169.07:40:27.71#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.169.07:40:27.71#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.169.07:40:27.71#ibcon#enter wrdev, iclass 33, count 0 2006.169.07:40:27.71#ibcon#first serial, iclass 33, count 0 2006.169.07:40:27.71#ibcon#enter sib2, iclass 33, count 0 2006.169.07:40:27.71#ibcon#flushed, iclass 33, count 0 2006.169.07:40:27.71#ibcon#about to write, iclass 33, count 0 2006.169.07:40:27.71#ibcon#wrote, iclass 33, count 0 2006.169.07:40:27.71#ibcon#about to read 3, iclass 33, count 0 2006.169.07:40:27.73#ibcon#read 3, iclass 33, count 0 2006.169.07:40:27.73#ibcon#about to read 4, iclass 33, count 0 2006.169.07:40:27.73#ibcon#read 4, iclass 33, count 0 2006.169.07:40:27.73#ibcon#about to read 5, iclass 33, count 0 2006.169.07:40:27.73#ibcon#read 5, iclass 33, count 0 2006.169.07:40:27.73#ibcon#about to read 6, iclass 33, count 0 2006.169.07:40:27.73#ibcon#read 6, iclass 33, count 0 2006.169.07:40:27.73#ibcon#end of sib2, iclass 33, count 0 2006.169.07:40:27.73#ibcon#*mode == 0, iclass 33, count 0 2006.169.07:40:27.73#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.169.07:40:27.73#ibcon#[27=USB\r\n] 2006.169.07:40:27.73#ibcon#*before write, iclass 33, count 0 2006.169.07:40:27.73#ibcon#enter sib2, iclass 33, count 0 2006.169.07:40:27.73#ibcon#flushed, iclass 33, count 0 2006.169.07:40:27.73#ibcon#about to write, iclass 33, count 0 2006.169.07:40:27.73#ibcon#wrote, iclass 33, count 0 2006.169.07:40:27.73#ibcon#about to read 3, iclass 33, count 0 2006.169.07:40:27.76#ibcon#read 3, iclass 33, count 0 2006.169.07:40:27.76#ibcon#about to read 4, iclass 33, count 0 2006.169.07:40:27.76#ibcon#read 4, iclass 33, count 0 2006.169.07:40:27.76#ibcon#about to read 5, iclass 33, count 0 2006.169.07:40:27.76#ibcon#read 5, iclass 33, count 0 2006.169.07:40:27.76#ibcon#about to read 6, iclass 33, count 0 2006.169.07:40:27.76#ibcon#read 6, iclass 33, count 0 2006.169.07:40:27.76#ibcon#end of sib2, iclass 33, count 0 2006.169.07:40:27.76#ibcon#*after write, iclass 33, count 0 2006.169.07:40:27.76#ibcon#*before return 0, iclass 33, count 0 2006.169.07:40:27.76#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.169.07:40:27.76#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.169.07:40:27.76#ibcon#about to clear, iclass 33 cls_cnt 0 2006.169.07:40:27.76#ibcon#cleared, iclass 33 cls_cnt 0 2006.169.07:40:27.76$vc4f8/vblo=2,640.99 2006.169.07:40:27.76#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.169.07:40:27.76#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.169.07:40:27.76#ibcon#ireg 17 cls_cnt 0 2006.169.07:40:27.76#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.169.07:40:27.76#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.169.07:40:27.76#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.169.07:40:27.76#ibcon#enter wrdev, iclass 35, count 0 2006.169.07:40:27.76#ibcon#first serial, iclass 35, count 0 2006.169.07:40:27.76#ibcon#enter sib2, iclass 35, count 0 2006.169.07:40:27.77#ibcon#flushed, iclass 35, count 0 2006.169.07:40:27.77#ibcon#about to write, iclass 35, count 0 2006.169.07:40:27.77#ibcon#wrote, iclass 35, count 0 2006.169.07:40:27.77#ibcon#about to read 3, iclass 35, count 0 2006.169.07:40:27.78#ibcon#read 3, iclass 35, count 0 2006.169.07:40:27.78#ibcon#about to read 4, iclass 35, count 0 2006.169.07:40:27.78#ibcon#read 4, iclass 35, count 0 2006.169.07:40:27.78#ibcon#about to read 5, iclass 35, count 0 2006.169.07:40:27.78#ibcon#read 5, iclass 35, count 0 2006.169.07:40:27.78#ibcon#about to read 6, iclass 35, count 0 2006.169.07:40:27.78#ibcon#read 6, iclass 35, count 0 2006.169.07:40:27.78#ibcon#end of sib2, iclass 35, count 0 2006.169.07:40:27.78#ibcon#*mode == 0, iclass 35, count 0 2006.169.07:40:27.78#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.169.07:40:27.78#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.07:40:27.78#ibcon#*before write, iclass 35, count 0 2006.169.07:40:27.78#ibcon#enter sib2, iclass 35, count 0 2006.169.07:40:27.78#ibcon#flushed, iclass 35, count 0 2006.169.07:40:27.78#ibcon#about to write, iclass 35, count 0 2006.169.07:40:27.78#ibcon#wrote, iclass 35, count 0 2006.169.07:40:27.78#ibcon#about to read 3, iclass 35, count 0 2006.169.07:40:27.82#ibcon#read 3, iclass 35, count 0 2006.169.07:40:27.82#ibcon#about to read 4, iclass 35, count 0 2006.169.07:40:27.82#ibcon#read 4, iclass 35, count 0 2006.169.07:40:27.82#ibcon#about to read 5, iclass 35, count 0 2006.169.07:40:27.82#ibcon#read 5, iclass 35, count 0 2006.169.07:40:27.82#ibcon#about to read 6, iclass 35, count 0 2006.169.07:40:27.82#ibcon#read 6, iclass 35, count 0 2006.169.07:40:27.82#ibcon#end of sib2, iclass 35, count 0 2006.169.07:40:27.82#ibcon#*after write, iclass 35, count 0 2006.169.07:40:27.82#ibcon#*before return 0, iclass 35, count 0 2006.169.07:40:27.82#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.169.07:40:27.82#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.169.07:40:27.82#ibcon#about to clear, iclass 35 cls_cnt 0 2006.169.07:40:27.82#ibcon#cleared, iclass 35 cls_cnt 0 2006.169.07:40:27.82$vc4f8/vb=2,4 2006.169.07:40:27.82#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.169.07:40:27.82#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.169.07:40:27.82#ibcon#ireg 11 cls_cnt 2 2006.169.07:40:27.82#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.169.07:40:27.88#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.169.07:40:27.88#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.169.07:40:27.88#ibcon#enter wrdev, iclass 37, count 2 2006.169.07:40:27.88#ibcon#first serial, iclass 37, count 2 2006.169.07:40:27.88#ibcon#enter sib2, iclass 37, count 2 2006.169.07:40:27.88#ibcon#flushed, iclass 37, count 2 2006.169.07:40:27.88#ibcon#about to write, iclass 37, count 2 2006.169.07:40:27.88#ibcon#wrote, iclass 37, count 2 2006.169.07:40:27.88#ibcon#about to read 3, iclass 37, count 2 2006.169.07:40:27.91#ibcon#read 3, iclass 37, count 2 2006.169.07:40:27.91#ibcon#about to read 4, iclass 37, count 2 2006.169.07:40:27.91#ibcon#read 4, iclass 37, count 2 2006.169.07:40:27.91#ibcon#about to read 5, iclass 37, count 2 2006.169.07:40:27.91#ibcon#read 5, iclass 37, count 2 2006.169.07:40:27.91#ibcon#about to read 6, iclass 37, count 2 2006.169.07:40:27.91#ibcon#read 6, iclass 37, count 2 2006.169.07:40:27.91#ibcon#end of sib2, iclass 37, count 2 2006.169.07:40:27.91#ibcon#*mode == 0, iclass 37, count 2 2006.169.07:40:27.91#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.169.07:40:27.91#ibcon#[27=AT02-04\r\n] 2006.169.07:40:27.91#ibcon#*before write, iclass 37, count 2 2006.169.07:40:27.91#ibcon#enter sib2, iclass 37, count 2 2006.169.07:40:27.91#ibcon#flushed, iclass 37, count 2 2006.169.07:40:27.91#ibcon#about to write, iclass 37, count 2 2006.169.07:40:27.91#ibcon#wrote, iclass 37, count 2 2006.169.07:40:27.91#ibcon#about to read 3, iclass 37, count 2 2006.169.07:40:27.94#ibcon#read 3, iclass 37, count 2 2006.169.07:40:27.94#ibcon#about to read 4, iclass 37, count 2 2006.169.07:40:27.94#ibcon#read 4, iclass 37, count 2 2006.169.07:40:27.94#ibcon#about to read 5, iclass 37, count 2 2006.169.07:40:27.94#ibcon#read 5, iclass 37, count 2 2006.169.07:40:27.94#ibcon#about to read 6, iclass 37, count 2 2006.169.07:40:27.94#ibcon#read 6, iclass 37, count 2 2006.169.07:40:27.94#ibcon#end of sib2, iclass 37, count 2 2006.169.07:40:27.94#ibcon#*after write, iclass 37, count 2 2006.169.07:40:27.94#ibcon#*before return 0, iclass 37, count 2 2006.169.07:40:27.94#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.169.07:40:27.94#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.169.07:40:27.94#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.169.07:40:27.94#ibcon#ireg 7 cls_cnt 0 2006.169.07:40:27.94#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.169.07:40:28.06#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.169.07:40:28.06#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.169.07:40:28.06#ibcon#enter wrdev, iclass 37, count 0 2006.169.07:40:28.06#ibcon#first serial, iclass 37, count 0 2006.169.07:40:28.06#ibcon#enter sib2, iclass 37, count 0 2006.169.07:40:28.06#ibcon#flushed, iclass 37, count 0 2006.169.07:40:28.06#ibcon#about to write, iclass 37, count 0 2006.169.07:40:28.06#ibcon#wrote, iclass 37, count 0 2006.169.07:40:28.06#ibcon#about to read 3, iclass 37, count 0 2006.169.07:40:28.08#ibcon#read 3, iclass 37, count 0 2006.169.07:40:28.08#ibcon#about to read 4, iclass 37, count 0 2006.169.07:40:28.08#ibcon#read 4, iclass 37, count 0 2006.169.07:40:28.08#ibcon#about to read 5, iclass 37, count 0 2006.169.07:40:28.08#ibcon#read 5, iclass 37, count 0 2006.169.07:40:28.08#ibcon#about to read 6, iclass 37, count 0 2006.169.07:40:28.08#ibcon#read 6, iclass 37, count 0 2006.169.07:40:28.08#ibcon#end of sib2, iclass 37, count 0 2006.169.07:40:28.08#ibcon#*mode == 0, iclass 37, count 0 2006.169.07:40:28.08#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.169.07:40:28.08#ibcon#[27=USB\r\n] 2006.169.07:40:28.08#ibcon#*before write, iclass 37, count 0 2006.169.07:40:28.08#ibcon#enter sib2, iclass 37, count 0 2006.169.07:40:28.08#ibcon#flushed, iclass 37, count 0 2006.169.07:40:28.08#ibcon#about to write, iclass 37, count 0 2006.169.07:40:28.08#ibcon#wrote, iclass 37, count 0 2006.169.07:40:28.08#ibcon#about to read 3, iclass 37, count 0 2006.169.07:40:28.11#ibcon#read 3, iclass 37, count 0 2006.169.07:40:28.11#ibcon#about to read 4, iclass 37, count 0 2006.169.07:40:28.11#ibcon#read 4, iclass 37, count 0 2006.169.07:40:28.11#ibcon#about to read 5, iclass 37, count 0 2006.169.07:40:28.11#ibcon#read 5, iclass 37, count 0 2006.169.07:40:28.11#ibcon#about to read 6, iclass 37, count 0 2006.169.07:40:28.11#ibcon#read 6, iclass 37, count 0 2006.169.07:40:28.11#ibcon#end of sib2, iclass 37, count 0 2006.169.07:40:28.11#ibcon#*after write, iclass 37, count 0 2006.169.07:40:28.11#ibcon#*before return 0, iclass 37, count 0 2006.169.07:40:28.11#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.169.07:40:28.11#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.169.07:40:28.11#ibcon#about to clear, iclass 37 cls_cnt 0 2006.169.07:40:28.11#ibcon#cleared, iclass 37 cls_cnt 0 2006.169.07:40:28.11$vc4f8/vblo=3,656.99 2006.169.07:40:28.11#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.169.07:40:28.11#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.169.07:40:28.11#ibcon#ireg 17 cls_cnt 0 2006.169.07:40:28.11#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.169.07:40:28.11#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.169.07:40:28.11#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.169.07:40:28.11#ibcon#enter wrdev, iclass 39, count 0 2006.169.07:40:28.11#ibcon#first serial, iclass 39, count 0 2006.169.07:40:28.11#ibcon#enter sib2, iclass 39, count 0 2006.169.07:40:28.11#ibcon#flushed, iclass 39, count 0 2006.169.07:40:28.12#ibcon#about to write, iclass 39, count 0 2006.169.07:40:28.12#ibcon#wrote, iclass 39, count 0 2006.169.07:40:28.12#ibcon#about to read 3, iclass 39, count 0 2006.169.07:40:28.13#ibcon#read 3, iclass 39, count 0 2006.169.07:40:28.13#ibcon#about to read 4, iclass 39, count 0 2006.169.07:40:28.13#ibcon#read 4, iclass 39, count 0 2006.169.07:40:28.13#ibcon#about to read 5, iclass 39, count 0 2006.169.07:40:28.13#ibcon#read 5, iclass 39, count 0 2006.169.07:40:28.13#ibcon#about to read 6, iclass 39, count 0 2006.169.07:40:28.13#ibcon#read 6, iclass 39, count 0 2006.169.07:40:28.13#ibcon#end of sib2, iclass 39, count 0 2006.169.07:40:28.13#ibcon#*mode == 0, iclass 39, count 0 2006.169.07:40:28.13#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.169.07:40:28.13#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.07:40:28.13#ibcon#*before write, iclass 39, count 0 2006.169.07:40:28.13#ibcon#enter sib2, iclass 39, count 0 2006.169.07:40:28.13#ibcon#flushed, iclass 39, count 0 2006.169.07:40:28.13#ibcon#about to write, iclass 39, count 0 2006.169.07:40:28.13#ibcon#wrote, iclass 39, count 0 2006.169.07:40:28.13#ibcon#about to read 3, iclass 39, count 0 2006.169.07:40:28.17#ibcon#read 3, iclass 39, count 0 2006.169.07:40:28.17#ibcon#about to read 4, iclass 39, count 0 2006.169.07:40:28.17#ibcon#read 4, iclass 39, count 0 2006.169.07:40:28.17#ibcon#about to read 5, iclass 39, count 0 2006.169.07:40:28.17#ibcon#read 5, iclass 39, count 0 2006.169.07:40:28.17#ibcon#about to read 6, iclass 39, count 0 2006.169.07:40:28.17#ibcon#read 6, iclass 39, count 0 2006.169.07:40:28.17#ibcon#end of sib2, iclass 39, count 0 2006.169.07:40:28.17#ibcon#*after write, iclass 39, count 0 2006.169.07:40:28.17#ibcon#*before return 0, iclass 39, count 0 2006.169.07:40:28.17#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.169.07:40:28.17#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.169.07:40:28.17#ibcon#about to clear, iclass 39 cls_cnt 0 2006.169.07:40:28.17#ibcon#cleared, iclass 39 cls_cnt 0 2006.169.07:40:28.17$vc4f8/vb=3,4 2006.169.07:40:28.17#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.169.07:40:28.17#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.169.07:40:28.17#ibcon#ireg 11 cls_cnt 2 2006.169.07:40:28.17#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.169.07:40:28.23#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.169.07:40:28.23#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.169.07:40:28.23#ibcon#enter wrdev, iclass 3, count 2 2006.169.07:40:28.23#ibcon#first serial, iclass 3, count 2 2006.169.07:40:28.23#ibcon#enter sib2, iclass 3, count 2 2006.169.07:40:28.23#ibcon#flushed, iclass 3, count 2 2006.169.07:40:28.23#ibcon#about to write, iclass 3, count 2 2006.169.07:40:28.23#ibcon#wrote, iclass 3, count 2 2006.169.07:40:28.23#ibcon#about to read 3, iclass 3, count 2 2006.169.07:40:28.25#ibcon#read 3, iclass 3, count 2 2006.169.07:40:28.25#ibcon#about to read 4, iclass 3, count 2 2006.169.07:40:28.25#ibcon#read 4, iclass 3, count 2 2006.169.07:40:28.25#ibcon#about to read 5, iclass 3, count 2 2006.169.07:40:28.25#ibcon#read 5, iclass 3, count 2 2006.169.07:40:28.25#ibcon#about to read 6, iclass 3, count 2 2006.169.07:40:28.25#ibcon#read 6, iclass 3, count 2 2006.169.07:40:28.25#ibcon#end of sib2, iclass 3, count 2 2006.169.07:40:28.25#ibcon#*mode == 0, iclass 3, count 2 2006.169.07:40:28.25#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.169.07:40:28.25#ibcon#[27=AT03-04\r\n] 2006.169.07:40:28.25#ibcon#*before write, iclass 3, count 2 2006.169.07:40:28.25#ibcon#enter sib2, iclass 3, count 2 2006.169.07:40:28.25#ibcon#flushed, iclass 3, count 2 2006.169.07:40:28.25#ibcon#about to write, iclass 3, count 2 2006.169.07:40:28.25#ibcon#wrote, iclass 3, count 2 2006.169.07:40:28.25#ibcon#about to read 3, iclass 3, count 2 2006.169.07:40:28.28#ibcon#read 3, iclass 3, count 2 2006.169.07:40:28.28#ibcon#about to read 4, iclass 3, count 2 2006.169.07:40:28.28#ibcon#read 4, iclass 3, count 2 2006.169.07:40:28.28#ibcon#about to read 5, iclass 3, count 2 2006.169.07:40:28.28#ibcon#read 5, iclass 3, count 2 2006.169.07:40:28.28#ibcon#about to read 6, iclass 3, count 2 2006.169.07:40:28.28#ibcon#read 6, iclass 3, count 2 2006.169.07:40:28.28#ibcon#end of sib2, iclass 3, count 2 2006.169.07:40:28.28#ibcon#*after write, iclass 3, count 2 2006.169.07:40:28.28#ibcon#*before return 0, iclass 3, count 2 2006.169.07:40:28.28#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.169.07:40:28.28#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.169.07:40:28.28#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.169.07:40:28.28#ibcon#ireg 7 cls_cnt 0 2006.169.07:40:28.28#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.169.07:40:28.40#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.169.07:40:28.40#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.169.07:40:28.40#ibcon#enter wrdev, iclass 3, count 0 2006.169.07:40:28.40#ibcon#first serial, iclass 3, count 0 2006.169.07:40:28.40#ibcon#enter sib2, iclass 3, count 0 2006.169.07:40:28.40#ibcon#flushed, iclass 3, count 0 2006.169.07:40:28.40#ibcon#about to write, iclass 3, count 0 2006.169.07:40:28.40#ibcon#wrote, iclass 3, count 0 2006.169.07:40:28.40#ibcon#about to read 3, iclass 3, count 0 2006.169.07:40:28.42#ibcon#read 3, iclass 3, count 0 2006.169.07:40:28.42#ibcon#about to read 4, iclass 3, count 0 2006.169.07:40:28.42#ibcon#read 4, iclass 3, count 0 2006.169.07:40:28.42#ibcon#about to read 5, iclass 3, count 0 2006.169.07:40:28.42#ibcon#read 5, iclass 3, count 0 2006.169.07:40:28.42#ibcon#about to read 6, iclass 3, count 0 2006.169.07:40:28.42#ibcon#read 6, iclass 3, count 0 2006.169.07:40:28.42#ibcon#end of sib2, iclass 3, count 0 2006.169.07:40:28.42#ibcon#*mode == 0, iclass 3, count 0 2006.169.07:40:28.42#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.169.07:40:28.42#ibcon#[27=USB\r\n] 2006.169.07:40:28.42#ibcon#*before write, iclass 3, count 0 2006.169.07:40:28.42#ibcon#enter sib2, iclass 3, count 0 2006.169.07:40:28.42#ibcon#flushed, iclass 3, count 0 2006.169.07:40:28.42#ibcon#about to write, iclass 3, count 0 2006.169.07:40:28.42#ibcon#wrote, iclass 3, count 0 2006.169.07:40:28.42#ibcon#about to read 3, iclass 3, count 0 2006.169.07:40:28.45#ibcon#read 3, iclass 3, count 0 2006.169.07:40:28.45#ibcon#about to read 4, iclass 3, count 0 2006.169.07:40:28.45#ibcon#read 4, iclass 3, count 0 2006.169.07:40:28.45#ibcon#about to read 5, iclass 3, count 0 2006.169.07:40:28.45#ibcon#read 5, iclass 3, count 0 2006.169.07:40:28.45#ibcon#about to read 6, iclass 3, count 0 2006.169.07:40:28.45#ibcon#read 6, iclass 3, count 0 2006.169.07:40:28.45#ibcon#end of sib2, iclass 3, count 0 2006.169.07:40:28.45#ibcon#*after write, iclass 3, count 0 2006.169.07:40:28.45#ibcon#*before return 0, iclass 3, count 0 2006.169.07:40:28.45#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.169.07:40:28.45#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.169.07:40:28.45#ibcon#about to clear, iclass 3 cls_cnt 0 2006.169.07:40:28.45#ibcon#cleared, iclass 3 cls_cnt 0 2006.169.07:40:28.45$vc4f8/vblo=4,712.99 2006.169.07:40:28.45#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.169.07:40:28.45#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.169.07:40:28.45#ibcon#ireg 17 cls_cnt 0 2006.169.07:40:28.45#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:40:28.45#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:40:28.45#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:40:28.45#ibcon#enter wrdev, iclass 5, count 0 2006.169.07:40:28.45#ibcon#first serial, iclass 5, count 0 2006.169.07:40:28.45#ibcon#enter sib2, iclass 5, count 0 2006.169.07:40:28.46#ibcon#flushed, iclass 5, count 0 2006.169.07:40:28.46#ibcon#about to write, iclass 5, count 0 2006.169.07:40:28.46#ibcon#wrote, iclass 5, count 0 2006.169.07:40:28.46#ibcon#about to read 3, iclass 5, count 0 2006.169.07:40:28.47#ibcon#read 3, iclass 5, count 0 2006.169.07:40:28.47#ibcon#about to read 4, iclass 5, count 0 2006.169.07:40:28.47#ibcon#read 4, iclass 5, count 0 2006.169.07:40:28.47#ibcon#about to read 5, iclass 5, count 0 2006.169.07:40:28.47#ibcon#read 5, iclass 5, count 0 2006.169.07:40:28.47#ibcon#about to read 6, iclass 5, count 0 2006.169.07:40:28.47#ibcon#read 6, iclass 5, count 0 2006.169.07:40:28.47#ibcon#end of sib2, iclass 5, count 0 2006.169.07:40:28.47#ibcon#*mode == 0, iclass 5, count 0 2006.169.07:40:28.47#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.169.07:40:28.47#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.07:40:28.47#ibcon#*before write, iclass 5, count 0 2006.169.07:40:28.47#ibcon#enter sib2, iclass 5, count 0 2006.169.07:40:28.47#ibcon#flushed, iclass 5, count 0 2006.169.07:40:28.47#ibcon#about to write, iclass 5, count 0 2006.169.07:40:28.47#ibcon#wrote, iclass 5, count 0 2006.169.07:40:28.47#ibcon#about to read 3, iclass 5, count 0 2006.169.07:40:28.51#ibcon#read 3, iclass 5, count 0 2006.169.07:40:28.51#ibcon#about to read 4, iclass 5, count 0 2006.169.07:40:28.51#ibcon#read 4, iclass 5, count 0 2006.169.07:40:28.51#ibcon#about to read 5, iclass 5, count 0 2006.169.07:40:28.51#ibcon#read 5, iclass 5, count 0 2006.169.07:40:28.51#ibcon#about to read 6, iclass 5, count 0 2006.169.07:40:28.51#ibcon#read 6, iclass 5, count 0 2006.169.07:40:28.51#ibcon#end of sib2, iclass 5, count 0 2006.169.07:40:28.51#ibcon#*after write, iclass 5, count 0 2006.169.07:40:28.51#ibcon#*before return 0, iclass 5, count 0 2006.169.07:40:28.51#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:40:28.51#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:40:28.51#ibcon#about to clear, iclass 5 cls_cnt 0 2006.169.07:40:28.51#ibcon#cleared, iclass 5 cls_cnt 0 2006.169.07:40:28.51$vc4f8/vb=4,4 2006.169.07:40:28.51#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.169.07:40:28.51#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.169.07:40:28.51#ibcon#ireg 11 cls_cnt 2 2006.169.07:40:28.51#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:40:28.57#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:40:28.57#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:40:28.57#ibcon#enter wrdev, iclass 7, count 2 2006.169.07:40:28.57#ibcon#first serial, iclass 7, count 2 2006.169.07:40:28.57#ibcon#enter sib2, iclass 7, count 2 2006.169.07:40:28.57#ibcon#flushed, iclass 7, count 2 2006.169.07:40:28.57#ibcon#about to write, iclass 7, count 2 2006.169.07:40:28.57#ibcon#wrote, iclass 7, count 2 2006.169.07:40:28.57#ibcon#about to read 3, iclass 7, count 2 2006.169.07:40:28.59#ibcon#read 3, iclass 7, count 2 2006.169.07:40:28.59#ibcon#about to read 4, iclass 7, count 2 2006.169.07:40:28.59#ibcon#read 4, iclass 7, count 2 2006.169.07:40:28.59#ibcon#about to read 5, iclass 7, count 2 2006.169.07:40:28.59#ibcon#read 5, iclass 7, count 2 2006.169.07:40:28.59#ibcon#about to read 6, iclass 7, count 2 2006.169.07:40:28.59#ibcon#read 6, iclass 7, count 2 2006.169.07:40:28.59#ibcon#end of sib2, iclass 7, count 2 2006.169.07:40:28.59#ibcon#*mode == 0, iclass 7, count 2 2006.169.07:40:28.59#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.169.07:40:28.59#ibcon#[27=AT04-04\r\n] 2006.169.07:40:28.59#ibcon#*before write, iclass 7, count 2 2006.169.07:40:28.59#ibcon#enter sib2, iclass 7, count 2 2006.169.07:40:28.59#ibcon#flushed, iclass 7, count 2 2006.169.07:40:28.59#ibcon#about to write, iclass 7, count 2 2006.169.07:40:28.59#ibcon#wrote, iclass 7, count 2 2006.169.07:40:28.59#ibcon#about to read 3, iclass 7, count 2 2006.169.07:40:28.62#ibcon#read 3, iclass 7, count 2 2006.169.07:40:28.62#ibcon#about to read 4, iclass 7, count 2 2006.169.07:40:28.62#ibcon#read 4, iclass 7, count 2 2006.169.07:40:28.62#ibcon#about to read 5, iclass 7, count 2 2006.169.07:40:28.62#ibcon#read 5, iclass 7, count 2 2006.169.07:40:28.62#ibcon#about to read 6, iclass 7, count 2 2006.169.07:40:28.62#ibcon#read 6, iclass 7, count 2 2006.169.07:40:28.62#ibcon#end of sib2, iclass 7, count 2 2006.169.07:40:28.62#ibcon#*after write, iclass 7, count 2 2006.169.07:40:28.62#ibcon#*before return 0, iclass 7, count 2 2006.169.07:40:28.62#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:40:28.62#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:40:28.62#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.169.07:40:28.62#ibcon#ireg 7 cls_cnt 0 2006.169.07:40:28.62#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:40:28.74#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:40:28.74#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:40:28.74#ibcon#enter wrdev, iclass 7, count 0 2006.169.07:40:28.74#ibcon#first serial, iclass 7, count 0 2006.169.07:40:28.74#ibcon#enter sib2, iclass 7, count 0 2006.169.07:40:28.74#ibcon#flushed, iclass 7, count 0 2006.169.07:40:28.74#ibcon#about to write, iclass 7, count 0 2006.169.07:40:28.74#ibcon#wrote, iclass 7, count 0 2006.169.07:40:28.74#ibcon#about to read 3, iclass 7, count 0 2006.169.07:40:28.76#ibcon#read 3, iclass 7, count 0 2006.169.07:40:28.76#ibcon#about to read 4, iclass 7, count 0 2006.169.07:40:28.76#ibcon#read 4, iclass 7, count 0 2006.169.07:40:28.76#ibcon#about to read 5, iclass 7, count 0 2006.169.07:40:28.76#ibcon#read 5, iclass 7, count 0 2006.169.07:40:28.76#ibcon#about to read 6, iclass 7, count 0 2006.169.07:40:28.76#ibcon#read 6, iclass 7, count 0 2006.169.07:40:28.76#ibcon#end of sib2, iclass 7, count 0 2006.169.07:40:28.76#ibcon#*mode == 0, iclass 7, count 0 2006.169.07:40:28.76#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.169.07:40:28.76#ibcon#[27=USB\r\n] 2006.169.07:40:28.76#ibcon#*before write, iclass 7, count 0 2006.169.07:40:28.76#ibcon#enter sib2, iclass 7, count 0 2006.169.07:40:28.76#ibcon#flushed, iclass 7, count 0 2006.169.07:40:28.76#ibcon#about to write, iclass 7, count 0 2006.169.07:40:28.76#ibcon#wrote, iclass 7, count 0 2006.169.07:40:28.76#ibcon#about to read 3, iclass 7, count 0 2006.169.07:40:28.79#ibcon#read 3, iclass 7, count 0 2006.169.07:40:28.79#ibcon#about to read 4, iclass 7, count 0 2006.169.07:40:28.79#ibcon#read 4, iclass 7, count 0 2006.169.07:40:28.79#ibcon#about to read 5, iclass 7, count 0 2006.169.07:40:28.79#ibcon#read 5, iclass 7, count 0 2006.169.07:40:28.79#ibcon#about to read 6, iclass 7, count 0 2006.169.07:40:28.79#ibcon#read 6, iclass 7, count 0 2006.169.07:40:28.79#ibcon#end of sib2, iclass 7, count 0 2006.169.07:40:28.79#ibcon#*after write, iclass 7, count 0 2006.169.07:40:28.79#ibcon#*before return 0, iclass 7, count 0 2006.169.07:40:28.79#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:40:28.79#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:40:28.79#ibcon#about to clear, iclass 7 cls_cnt 0 2006.169.07:40:28.79#ibcon#cleared, iclass 7 cls_cnt 0 2006.169.07:40:28.79$vc4f8/vblo=5,744.99 2006.169.07:40:28.79#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.169.07:40:28.79#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.169.07:40:28.79#ibcon#ireg 17 cls_cnt 0 2006.169.07:40:28.79#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.169.07:40:28.79#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.169.07:40:28.79#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.169.07:40:28.79#ibcon#enter wrdev, iclass 11, count 0 2006.169.07:40:28.79#ibcon#first serial, iclass 11, count 0 2006.169.07:40:28.80#ibcon#enter sib2, iclass 11, count 0 2006.169.07:40:28.80#ibcon#flushed, iclass 11, count 0 2006.169.07:40:28.80#ibcon#about to write, iclass 11, count 0 2006.169.07:40:28.80#ibcon#wrote, iclass 11, count 0 2006.169.07:40:28.80#ibcon#about to read 3, iclass 11, count 0 2006.169.07:40:28.81#ibcon#read 3, iclass 11, count 0 2006.169.07:40:28.81#ibcon#about to read 4, iclass 11, count 0 2006.169.07:40:28.81#ibcon#read 4, iclass 11, count 0 2006.169.07:40:28.81#ibcon#about to read 5, iclass 11, count 0 2006.169.07:40:28.81#ibcon#read 5, iclass 11, count 0 2006.169.07:40:28.81#ibcon#about to read 6, iclass 11, count 0 2006.169.07:40:28.81#ibcon#read 6, iclass 11, count 0 2006.169.07:40:28.81#ibcon#end of sib2, iclass 11, count 0 2006.169.07:40:28.81#ibcon#*mode == 0, iclass 11, count 0 2006.169.07:40:28.81#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.169.07:40:28.81#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.07:40:28.81#ibcon#*before write, iclass 11, count 0 2006.169.07:40:28.81#ibcon#enter sib2, iclass 11, count 0 2006.169.07:40:28.81#ibcon#flushed, iclass 11, count 0 2006.169.07:40:28.81#ibcon#about to write, iclass 11, count 0 2006.169.07:40:28.81#ibcon#wrote, iclass 11, count 0 2006.169.07:40:28.81#ibcon#about to read 3, iclass 11, count 0 2006.169.07:40:28.85#ibcon#read 3, iclass 11, count 0 2006.169.07:40:28.85#ibcon#about to read 4, iclass 11, count 0 2006.169.07:40:28.85#ibcon#read 4, iclass 11, count 0 2006.169.07:40:28.85#ibcon#about to read 5, iclass 11, count 0 2006.169.07:40:28.85#ibcon#read 5, iclass 11, count 0 2006.169.07:40:28.85#ibcon#about to read 6, iclass 11, count 0 2006.169.07:40:28.85#ibcon#read 6, iclass 11, count 0 2006.169.07:40:28.85#ibcon#end of sib2, iclass 11, count 0 2006.169.07:40:28.85#ibcon#*after write, iclass 11, count 0 2006.169.07:40:28.85#ibcon#*before return 0, iclass 11, count 0 2006.169.07:40:28.85#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.169.07:40:28.85#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.169.07:40:28.85#ibcon#about to clear, iclass 11 cls_cnt 0 2006.169.07:40:28.85#ibcon#cleared, iclass 11 cls_cnt 0 2006.169.07:40:28.85$vc4f8/vb=5,4 2006.169.07:40:28.85#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.169.07:40:28.85#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.169.07:40:28.85#ibcon#ireg 11 cls_cnt 2 2006.169.07:40:28.85#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.169.07:40:28.91#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.169.07:40:28.91#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.169.07:40:28.91#ibcon#enter wrdev, iclass 13, count 2 2006.169.07:40:28.91#ibcon#first serial, iclass 13, count 2 2006.169.07:40:28.91#ibcon#enter sib2, iclass 13, count 2 2006.169.07:40:28.91#ibcon#flushed, iclass 13, count 2 2006.169.07:40:28.91#ibcon#about to write, iclass 13, count 2 2006.169.07:40:28.91#ibcon#wrote, iclass 13, count 2 2006.169.07:40:28.91#ibcon#about to read 3, iclass 13, count 2 2006.169.07:40:28.93#ibcon#read 3, iclass 13, count 2 2006.169.07:40:28.93#ibcon#about to read 4, iclass 13, count 2 2006.169.07:40:28.93#ibcon#read 4, iclass 13, count 2 2006.169.07:40:28.93#ibcon#about to read 5, iclass 13, count 2 2006.169.07:40:28.93#ibcon#read 5, iclass 13, count 2 2006.169.07:40:28.93#ibcon#about to read 6, iclass 13, count 2 2006.169.07:40:28.93#ibcon#read 6, iclass 13, count 2 2006.169.07:40:28.93#ibcon#end of sib2, iclass 13, count 2 2006.169.07:40:28.93#ibcon#*mode == 0, iclass 13, count 2 2006.169.07:40:28.93#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.169.07:40:28.93#ibcon#[27=AT05-04\r\n] 2006.169.07:40:28.93#ibcon#*before write, iclass 13, count 2 2006.169.07:40:28.93#ibcon#enter sib2, iclass 13, count 2 2006.169.07:40:28.93#ibcon#flushed, iclass 13, count 2 2006.169.07:40:28.93#ibcon#about to write, iclass 13, count 2 2006.169.07:40:28.93#ibcon#wrote, iclass 13, count 2 2006.169.07:40:28.93#ibcon#about to read 3, iclass 13, count 2 2006.169.07:40:28.96#ibcon#read 3, iclass 13, count 2 2006.169.07:40:28.96#ibcon#about to read 4, iclass 13, count 2 2006.169.07:40:28.96#ibcon#read 4, iclass 13, count 2 2006.169.07:40:28.96#ibcon#about to read 5, iclass 13, count 2 2006.169.07:40:28.96#ibcon#read 5, iclass 13, count 2 2006.169.07:40:28.96#ibcon#about to read 6, iclass 13, count 2 2006.169.07:40:28.96#ibcon#read 6, iclass 13, count 2 2006.169.07:40:28.96#ibcon#end of sib2, iclass 13, count 2 2006.169.07:40:28.96#ibcon#*after write, iclass 13, count 2 2006.169.07:40:28.96#ibcon#*before return 0, iclass 13, count 2 2006.169.07:40:28.96#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.169.07:40:28.96#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.169.07:40:28.96#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.169.07:40:28.96#ibcon#ireg 7 cls_cnt 0 2006.169.07:40:28.96#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.169.07:40:29.08#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.169.07:40:29.08#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.169.07:40:29.08#ibcon#enter wrdev, iclass 13, count 0 2006.169.07:40:29.08#ibcon#first serial, iclass 13, count 0 2006.169.07:40:29.08#ibcon#enter sib2, iclass 13, count 0 2006.169.07:40:29.08#ibcon#flushed, iclass 13, count 0 2006.169.07:40:29.08#ibcon#about to write, iclass 13, count 0 2006.169.07:40:29.08#ibcon#wrote, iclass 13, count 0 2006.169.07:40:29.08#ibcon#about to read 3, iclass 13, count 0 2006.169.07:40:29.10#ibcon#read 3, iclass 13, count 0 2006.169.07:40:29.10#ibcon#about to read 4, iclass 13, count 0 2006.169.07:40:29.10#ibcon#read 4, iclass 13, count 0 2006.169.07:40:29.10#ibcon#about to read 5, iclass 13, count 0 2006.169.07:40:29.10#ibcon#read 5, iclass 13, count 0 2006.169.07:40:29.10#ibcon#about to read 6, iclass 13, count 0 2006.169.07:40:29.10#ibcon#read 6, iclass 13, count 0 2006.169.07:40:29.10#ibcon#end of sib2, iclass 13, count 0 2006.169.07:40:29.10#ibcon#*mode == 0, iclass 13, count 0 2006.169.07:40:29.10#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.07:40:29.10#ibcon#[27=USB\r\n] 2006.169.07:40:29.10#ibcon#*before write, iclass 13, count 0 2006.169.07:40:29.10#ibcon#enter sib2, iclass 13, count 0 2006.169.07:40:29.10#ibcon#flushed, iclass 13, count 0 2006.169.07:40:29.10#ibcon#about to write, iclass 13, count 0 2006.169.07:40:29.10#ibcon#wrote, iclass 13, count 0 2006.169.07:40:29.10#ibcon#about to read 3, iclass 13, count 0 2006.169.07:40:29.13#ibcon#read 3, iclass 13, count 0 2006.169.07:40:29.13#ibcon#about to read 4, iclass 13, count 0 2006.169.07:40:29.13#ibcon#read 4, iclass 13, count 0 2006.169.07:40:29.13#ibcon#about to read 5, iclass 13, count 0 2006.169.07:40:29.13#ibcon#read 5, iclass 13, count 0 2006.169.07:40:29.13#ibcon#about to read 6, iclass 13, count 0 2006.169.07:40:29.13#ibcon#read 6, iclass 13, count 0 2006.169.07:40:29.13#ibcon#end of sib2, iclass 13, count 0 2006.169.07:40:29.13#ibcon#*after write, iclass 13, count 0 2006.169.07:40:29.13#ibcon#*before return 0, iclass 13, count 0 2006.169.07:40:29.13#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.169.07:40:29.13#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.169.07:40:29.13#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.07:40:29.13#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.07:40:29.13$vc4f8/vblo=6,752.99 2006.169.07:40:29.13#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.169.07:40:29.13#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.169.07:40:29.13#ibcon#ireg 17 cls_cnt 0 2006.169.07:40:29.13#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:40:29.13#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:40:29.13#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:40:29.14#ibcon#enter wrdev, iclass 15, count 0 2006.169.07:40:29.14#ibcon#first serial, iclass 15, count 0 2006.169.07:40:29.14#ibcon#enter sib2, iclass 15, count 0 2006.169.07:40:29.14#ibcon#flushed, iclass 15, count 0 2006.169.07:40:29.14#ibcon#about to write, iclass 15, count 0 2006.169.07:40:29.14#ibcon#wrote, iclass 15, count 0 2006.169.07:40:29.14#ibcon#about to read 3, iclass 15, count 0 2006.169.07:40:29.15#ibcon#read 3, iclass 15, count 0 2006.169.07:40:29.15#ibcon#about to read 4, iclass 15, count 0 2006.169.07:40:29.15#ibcon#read 4, iclass 15, count 0 2006.169.07:40:29.15#ibcon#about to read 5, iclass 15, count 0 2006.169.07:40:29.15#ibcon#read 5, iclass 15, count 0 2006.169.07:40:29.15#ibcon#about to read 6, iclass 15, count 0 2006.169.07:40:29.15#ibcon#read 6, iclass 15, count 0 2006.169.07:40:29.15#ibcon#end of sib2, iclass 15, count 0 2006.169.07:40:29.15#ibcon#*mode == 0, iclass 15, count 0 2006.169.07:40:29.15#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.169.07:40:29.15#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.07:40:29.15#ibcon#*before write, iclass 15, count 0 2006.169.07:40:29.15#ibcon#enter sib2, iclass 15, count 0 2006.169.07:40:29.15#ibcon#flushed, iclass 15, count 0 2006.169.07:40:29.15#ibcon#about to write, iclass 15, count 0 2006.169.07:40:29.15#ibcon#wrote, iclass 15, count 0 2006.169.07:40:29.15#ibcon#about to read 3, iclass 15, count 0 2006.169.07:40:29.19#ibcon#read 3, iclass 15, count 0 2006.169.07:40:29.19#ibcon#about to read 4, iclass 15, count 0 2006.169.07:40:29.19#ibcon#read 4, iclass 15, count 0 2006.169.07:40:29.19#ibcon#about to read 5, iclass 15, count 0 2006.169.07:40:29.19#ibcon#read 5, iclass 15, count 0 2006.169.07:40:29.19#ibcon#about to read 6, iclass 15, count 0 2006.169.07:40:29.19#ibcon#read 6, iclass 15, count 0 2006.169.07:40:29.19#ibcon#end of sib2, iclass 15, count 0 2006.169.07:40:29.19#ibcon#*after write, iclass 15, count 0 2006.169.07:40:29.19#ibcon#*before return 0, iclass 15, count 0 2006.169.07:40:29.19#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:40:29.19#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:40:29.19#ibcon#about to clear, iclass 15 cls_cnt 0 2006.169.07:40:29.19#ibcon#cleared, iclass 15 cls_cnt 0 2006.169.07:40:29.19$vc4f8/vb=6,4 2006.169.07:40:29.19#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.169.07:40:29.19#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.169.07:40:29.19#ibcon#ireg 11 cls_cnt 2 2006.169.07:40:29.19#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.169.07:40:29.25#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.169.07:40:29.25#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.169.07:40:29.25#ibcon#enter wrdev, iclass 17, count 2 2006.169.07:40:29.25#ibcon#first serial, iclass 17, count 2 2006.169.07:40:29.25#ibcon#enter sib2, iclass 17, count 2 2006.169.07:40:29.25#ibcon#flushed, iclass 17, count 2 2006.169.07:40:29.25#ibcon#about to write, iclass 17, count 2 2006.169.07:40:29.25#ibcon#wrote, iclass 17, count 2 2006.169.07:40:29.25#ibcon#about to read 3, iclass 17, count 2 2006.169.07:40:29.27#ibcon#read 3, iclass 17, count 2 2006.169.07:40:29.27#ibcon#about to read 4, iclass 17, count 2 2006.169.07:40:29.27#ibcon#read 4, iclass 17, count 2 2006.169.07:40:29.27#ibcon#about to read 5, iclass 17, count 2 2006.169.07:40:29.27#ibcon#read 5, iclass 17, count 2 2006.169.07:40:29.27#ibcon#about to read 6, iclass 17, count 2 2006.169.07:40:29.27#ibcon#read 6, iclass 17, count 2 2006.169.07:40:29.27#ibcon#end of sib2, iclass 17, count 2 2006.169.07:40:29.27#ibcon#*mode == 0, iclass 17, count 2 2006.169.07:40:29.27#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.169.07:40:29.27#ibcon#[27=AT06-04\r\n] 2006.169.07:40:29.27#ibcon#*before write, iclass 17, count 2 2006.169.07:40:29.27#ibcon#enter sib2, iclass 17, count 2 2006.169.07:40:29.27#ibcon#flushed, iclass 17, count 2 2006.169.07:40:29.27#ibcon#about to write, iclass 17, count 2 2006.169.07:40:29.27#ibcon#wrote, iclass 17, count 2 2006.169.07:40:29.27#ibcon#about to read 3, iclass 17, count 2 2006.169.07:40:29.30#ibcon#read 3, iclass 17, count 2 2006.169.07:40:29.30#ibcon#about to read 4, iclass 17, count 2 2006.169.07:40:29.30#ibcon#read 4, iclass 17, count 2 2006.169.07:40:29.30#ibcon#about to read 5, iclass 17, count 2 2006.169.07:40:29.30#ibcon#read 5, iclass 17, count 2 2006.169.07:40:29.30#ibcon#about to read 6, iclass 17, count 2 2006.169.07:40:29.30#ibcon#read 6, iclass 17, count 2 2006.169.07:40:29.30#ibcon#end of sib2, iclass 17, count 2 2006.169.07:40:29.30#ibcon#*after write, iclass 17, count 2 2006.169.07:40:29.30#ibcon#*before return 0, iclass 17, count 2 2006.169.07:40:29.30#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.169.07:40:29.30#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.169.07:40:29.30#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.169.07:40:29.30#ibcon#ireg 7 cls_cnt 0 2006.169.07:40:29.30#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.169.07:40:29.42#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.169.07:40:29.42#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.169.07:40:29.42#ibcon#enter wrdev, iclass 17, count 0 2006.169.07:40:29.42#ibcon#first serial, iclass 17, count 0 2006.169.07:40:29.42#ibcon#enter sib2, iclass 17, count 0 2006.169.07:40:29.42#ibcon#flushed, iclass 17, count 0 2006.169.07:40:29.42#ibcon#about to write, iclass 17, count 0 2006.169.07:40:29.42#ibcon#wrote, iclass 17, count 0 2006.169.07:40:29.42#ibcon#about to read 3, iclass 17, count 0 2006.169.07:40:29.44#ibcon#read 3, iclass 17, count 0 2006.169.07:40:29.44#ibcon#about to read 4, iclass 17, count 0 2006.169.07:40:29.44#ibcon#read 4, iclass 17, count 0 2006.169.07:40:29.44#ibcon#about to read 5, iclass 17, count 0 2006.169.07:40:29.44#ibcon#read 5, iclass 17, count 0 2006.169.07:40:29.44#ibcon#about to read 6, iclass 17, count 0 2006.169.07:40:29.44#ibcon#read 6, iclass 17, count 0 2006.169.07:40:29.44#ibcon#end of sib2, iclass 17, count 0 2006.169.07:40:29.44#ibcon#*mode == 0, iclass 17, count 0 2006.169.07:40:29.44#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.169.07:40:29.44#ibcon#[27=USB\r\n] 2006.169.07:40:29.44#ibcon#*before write, iclass 17, count 0 2006.169.07:40:29.44#ibcon#enter sib2, iclass 17, count 0 2006.169.07:40:29.44#ibcon#flushed, iclass 17, count 0 2006.169.07:40:29.44#ibcon#about to write, iclass 17, count 0 2006.169.07:40:29.44#ibcon#wrote, iclass 17, count 0 2006.169.07:40:29.44#ibcon#about to read 3, iclass 17, count 0 2006.169.07:40:29.47#ibcon#read 3, iclass 17, count 0 2006.169.07:40:29.47#ibcon#about to read 4, iclass 17, count 0 2006.169.07:40:29.47#ibcon#read 4, iclass 17, count 0 2006.169.07:40:29.47#ibcon#about to read 5, iclass 17, count 0 2006.169.07:40:29.47#ibcon#read 5, iclass 17, count 0 2006.169.07:40:29.47#ibcon#about to read 6, iclass 17, count 0 2006.169.07:40:29.47#ibcon#read 6, iclass 17, count 0 2006.169.07:40:29.47#ibcon#end of sib2, iclass 17, count 0 2006.169.07:40:29.47#ibcon#*after write, iclass 17, count 0 2006.169.07:40:29.47#ibcon#*before return 0, iclass 17, count 0 2006.169.07:40:29.47#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.169.07:40:29.47#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.169.07:40:29.47#ibcon#about to clear, iclass 17 cls_cnt 0 2006.169.07:40:29.47#ibcon#cleared, iclass 17 cls_cnt 0 2006.169.07:40:29.47$vc4f8/vabw=wide 2006.169.07:40:29.47#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.169.07:40:29.47#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.169.07:40:29.47#ibcon#ireg 8 cls_cnt 0 2006.169.07:40:29.47#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.169.07:40:29.47#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.169.07:40:29.47#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.169.07:40:29.47#ibcon#enter wrdev, iclass 19, count 0 2006.169.07:40:29.47#ibcon#first serial, iclass 19, count 0 2006.169.07:40:29.47#ibcon#enter sib2, iclass 19, count 0 2006.169.07:40:29.47#ibcon#flushed, iclass 19, count 0 2006.169.07:40:29.47#ibcon#about to write, iclass 19, count 0 2006.169.07:40:29.48#ibcon#wrote, iclass 19, count 0 2006.169.07:40:29.48#ibcon#about to read 3, iclass 19, count 0 2006.169.07:40:29.49#ibcon#read 3, iclass 19, count 0 2006.169.07:40:29.49#ibcon#about to read 4, iclass 19, count 0 2006.169.07:40:29.49#ibcon#read 4, iclass 19, count 0 2006.169.07:40:29.49#ibcon#about to read 5, iclass 19, count 0 2006.169.07:40:29.49#ibcon#read 5, iclass 19, count 0 2006.169.07:40:29.49#ibcon#about to read 6, iclass 19, count 0 2006.169.07:40:29.49#ibcon#read 6, iclass 19, count 0 2006.169.07:40:29.49#ibcon#end of sib2, iclass 19, count 0 2006.169.07:40:29.49#ibcon#*mode == 0, iclass 19, count 0 2006.169.07:40:29.49#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.169.07:40:29.49#ibcon#[25=BW32\r\n] 2006.169.07:40:29.49#ibcon#*before write, iclass 19, count 0 2006.169.07:40:29.49#ibcon#enter sib2, iclass 19, count 0 2006.169.07:40:29.49#ibcon#flushed, iclass 19, count 0 2006.169.07:40:29.49#ibcon#about to write, iclass 19, count 0 2006.169.07:40:29.49#ibcon#wrote, iclass 19, count 0 2006.169.07:40:29.49#ibcon#about to read 3, iclass 19, count 0 2006.169.07:40:29.52#ibcon#read 3, iclass 19, count 0 2006.169.07:40:29.52#ibcon#about to read 4, iclass 19, count 0 2006.169.07:40:29.52#ibcon#read 4, iclass 19, count 0 2006.169.07:40:29.52#ibcon#about to read 5, iclass 19, count 0 2006.169.07:40:29.52#ibcon#read 5, iclass 19, count 0 2006.169.07:40:29.52#ibcon#about to read 6, iclass 19, count 0 2006.169.07:40:29.52#ibcon#read 6, iclass 19, count 0 2006.169.07:40:29.52#ibcon#end of sib2, iclass 19, count 0 2006.169.07:40:29.52#ibcon#*after write, iclass 19, count 0 2006.169.07:40:29.52#ibcon#*before return 0, iclass 19, count 0 2006.169.07:40:29.52#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.169.07:40:29.52#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.169.07:40:29.52#ibcon#about to clear, iclass 19 cls_cnt 0 2006.169.07:40:29.52#ibcon#cleared, iclass 19 cls_cnt 0 2006.169.07:40:29.52$vc4f8/vbbw=wide 2006.169.07:40:29.52#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.169.07:40:29.52#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.169.07:40:29.52#ibcon#ireg 8 cls_cnt 0 2006.169.07:40:29.52#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:40:29.59#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:40:29.59#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:40:29.59#ibcon#enter wrdev, iclass 21, count 0 2006.169.07:40:29.59#ibcon#first serial, iclass 21, count 0 2006.169.07:40:29.59#ibcon#enter sib2, iclass 21, count 0 2006.169.07:40:29.59#ibcon#flushed, iclass 21, count 0 2006.169.07:40:29.59#ibcon#about to write, iclass 21, count 0 2006.169.07:40:29.59#ibcon#wrote, iclass 21, count 0 2006.169.07:40:29.59#ibcon#about to read 3, iclass 21, count 0 2006.169.07:40:29.61#ibcon#read 3, iclass 21, count 0 2006.169.07:40:29.61#ibcon#about to read 4, iclass 21, count 0 2006.169.07:40:29.61#ibcon#read 4, iclass 21, count 0 2006.169.07:40:29.61#ibcon#about to read 5, iclass 21, count 0 2006.169.07:40:29.61#ibcon#read 5, iclass 21, count 0 2006.169.07:40:29.61#ibcon#about to read 6, iclass 21, count 0 2006.169.07:40:29.61#ibcon#read 6, iclass 21, count 0 2006.169.07:40:29.61#ibcon#end of sib2, iclass 21, count 0 2006.169.07:40:29.61#ibcon#*mode == 0, iclass 21, count 0 2006.169.07:40:29.61#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.169.07:40:29.61#ibcon#[27=BW32\r\n] 2006.169.07:40:29.61#ibcon#*before write, iclass 21, count 0 2006.169.07:40:29.61#ibcon#enter sib2, iclass 21, count 0 2006.169.07:40:29.61#ibcon#flushed, iclass 21, count 0 2006.169.07:40:29.61#ibcon#about to write, iclass 21, count 0 2006.169.07:40:29.61#ibcon#wrote, iclass 21, count 0 2006.169.07:40:29.61#ibcon#about to read 3, iclass 21, count 0 2006.169.07:40:29.64#ibcon#read 3, iclass 21, count 0 2006.169.07:40:29.64#ibcon#about to read 4, iclass 21, count 0 2006.169.07:40:29.64#ibcon#read 4, iclass 21, count 0 2006.169.07:40:29.64#ibcon#about to read 5, iclass 21, count 0 2006.169.07:40:29.64#ibcon#read 5, iclass 21, count 0 2006.169.07:40:29.64#ibcon#about to read 6, iclass 21, count 0 2006.169.07:40:29.64#ibcon#read 6, iclass 21, count 0 2006.169.07:40:29.64#ibcon#end of sib2, iclass 21, count 0 2006.169.07:40:29.64#ibcon#*after write, iclass 21, count 0 2006.169.07:40:29.64#ibcon#*before return 0, iclass 21, count 0 2006.169.07:40:29.64#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:40:29.64#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:40:29.64#ibcon#about to clear, iclass 21 cls_cnt 0 2006.169.07:40:29.64#ibcon#cleared, iclass 21 cls_cnt 0 2006.169.07:40:29.64$4f8m12a/ifd4f 2006.169.07:40:29.64$ifd4f/lo= 2006.169.07:40:29.65$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.07:40:29.65$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.07:40:29.65$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.07:40:29.65$ifd4f/patch= 2006.169.07:40:29.65$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.07:40:29.65$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.07:40:29.65$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.07:40:29.65$4f8m12a/"form=m,16.000,1:2 2006.169.07:40:29.65$4f8m12a/"tpicd 2006.169.07:40:29.65$4f8m12a/echo=off 2006.169.07:40:29.65$4f8m12a/xlog=off 2006.169.07:40:29.65:!2006.169.07:40:40 2006.169.07:40:40.01:preob 2006.169.07:40:41.14/onsource/TRACKING 2006.169.07:40:41.15:!2006.169.07:40:50 2006.169.07:40:50.01:data_valid=on 2006.169.07:40:50.02:midob 2006.169.07:40:51.14/onsource/TRACKING 2006.169.07:40:51.15/wx/18.14,1003.8,100 2006.169.07:40:51.28/cable/+6.5275E-03 2006.169.07:40:52.37/va/01,08,usb,yes,51,54 2006.169.07:40:52.37/va/02,07,usb,yes,52,54 2006.169.07:40:52.37/va/03,06,usb,yes,55,55 2006.169.07:40:52.37/va/04,07,usb,yes,53,57 2006.169.07:40:52.37/va/05,07,usb,yes,58,61 2006.169.07:40:52.37/va/06,06,usb,yes,58,57 2006.169.07:40:52.37/va/07,06,usb,yes,58,58 2006.169.07:40:52.37/va/08,07,usb,yes,55,54 2006.169.07:40:52.60/valo/01,532.99,yes,locked 2006.169.07:40:52.60/valo/02,572.99,yes,locked 2006.169.07:40:52.60/valo/03,672.99,yes,locked 2006.169.07:40:52.60/valo/04,832.99,yes,locked 2006.169.07:40:52.60/valo/05,652.99,yes,locked 2006.169.07:40:52.60/valo/06,772.99,yes,locked 2006.169.07:40:52.60/valo/07,832.99,yes,locked 2006.169.07:40:52.60/valo/08,852.99,yes,locked 2006.169.07:40:53.69/vb/01,04,usb,yes,33,32 2006.169.07:40:53.69/vb/02,04,usb,yes,35,37 2006.169.07:40:53.69/vb/03,04,usb,yes,31,36 2006.169.07:40:53.69/vb/04,04,usb,yes,33,33 2006.169.07:40:53.69/vb/05,04,usb,yes,31,35 2006.169.07:40:53.69/vb/06,04,usb,yes,32,35 2006.169.07:40:53.69/vb/07,04,usb,yes,34,34 2006.169.07:40:53.69/vb/08,04,usb,yes,32,35 2006.169.07:40:53.92/vblo/01,632.99,yes,locked 2006.169.07:40:53.92/vblo/02,640.99,yes,locked 2006.169.07:40:53.92/vblo/03,656.99,yes,locked 2006.169.07:40:53.92/vblo/04,712.99,yes,locked 2006.169.07:40:53.92/vblo/05,744.99,yes,locked 2006.169.07:40:53.92/vblo/06,752.99,yes,locked 2006.169.07:40:53.92/vblo/07,734.99,yes,locked 2006.169.07:40:53.92/vblo/08,744.99,yes,locked 2006.169.07:40:54.07/vabw/8 2006.169.07:40:54.22/vbbw/8 2006.169.07:40:54.31/xfe/off,on,15.5 2006.169.07:40:54.69/ifatt/23,28,28,28 2006.169.07:40:55.07/fmout-gps/S +4.17E-07 2006.169.07:40:55.12:!2006.169.07:41:50 2006.169.07:41:50.01:data_valid=off 2006.169.07:41:50.02:postob 2006.169.07:41:50.16/cable/+6.5280E-03 2006.169.07:41:50.16/wx/18.14,1003.8,100 2006.169.07:41:51.07/fmout-gps/S +4.16E-07 2006.169.07:41:51.07:scan_name=169-0742,k06169,60 2006.169.07:41:51.07:source=1357+769,135755.37,764321.1,2000.0,cw 2006.169.07:41:52.14#flagr#flagr/antenna,new-source 2006.169.07:41:52.15:checkk5 2006.169.07:41:52.57/chk_autoobs//k5ts1/ autoobs is running! 2006.169.07:41:52.94/chk_autoobs//k5ts2/ autoobs is running! 2006.169.07:41:56.96/chk_autoobs//k5ts3?ERROR: timeout happened! 2006.169.07:41:57.34/chk_autoobs//k5ts4/ autoobs is running! 2006.169.07:41:57.71/chk_obsdata//k5ts1/T1690740??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:41:58.08/chk_obsdata//k5ts2/T1690740??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:42:05.09/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.07:42:05.47/chk_obsdata//k5ts4/T1690740??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:42:06.16/k5log//k5ts1_log_newline 2006.169.07:42:06.85/k5log//k5ts2_log_newline 2006.169.07:42:13.95/k5log//k5ts3?ERROR: timeout happened! 2006.169.07:42:14.16#trakl#Source acquired 2006.169.07:42:14.69/k5log//k5ts4_log_newline 2006.169.07:42:14.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.07:42:14.85:4f8m12a=1 2006.169.07:42:14.85$4f8m12a/echo=on 2006.169.07:42:14.85$4f8m12a/pcalon 2006.169.07:42:14.85$pcalon/"no phase cal control is implemented here 2006.169.07:42:14.85$4f8m12a/"tpicd=stop 2006.169.07:42:14.85$4f8m12a/vc4f8 2006.169.07:42:14.85$vc4f8/valo=1,532.99 2006.169.07:42:14.86#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.169.07:42:14.86#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.169.07:42:14.86#ibcon#ireg 17 cls_cnt 0 2006.169.07:42:14.86#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:42:14.86#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:42:14.86#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:42:14.86#ibcon#enter wrdev, iclass 28, count 0 2006.169.07:42:14.86#ibcon#first serial, iclass 28, count 0 2006.169.07:42:14.86#ibcon#enter sib2, iclass 28, count 0 2006.169.07:42:14.86#ibcon#flushed, iclass 28, count 0 2006.169.07:42:14.86#ibcon#about to write, iclass 28, count 0 2006.169.07:42:14.86#ibcon#wrote, iclass 28, count 0 2006.169.07:42:14.86#ibcon#about to read 3, iclass 28, count 0 2006.169.07:42:14.87#ibcon#read 3, iclass 28, count 0 2006.169.07:42:14.87#ibcon#about to read 4, iclass 28, count 0 2006.169.07:42:14.87#ibcon#read 4, iclass 28, count 0 2006.169.07:42:14.87#ibcon#about to read 5, iclass 28, count 0 2006.169.07:42:14.87#ibcon#read 5, iclass 28, count 0 2006.169.07:42:14.87#ibcon#about to read 6, iclass 28, count 0 2006.169.07:42:14.87#ibcon#read 6, iclass 28, count 0 2006.169.07:42:14.87#ibcon#end of sib2, iclass 28, count 0 2006.169.07:42:14.87#ibcon#*mode == 0, iclass 28, count 0 2006.169.07:42:14.87#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.169.07:42:14.87#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.07:42:14.87#ibcon#*before write, iclass 28, count 0 2006.169.07:42:14.87#ibcon#enter sib2, iclass 28, count 0 2006.169.07:42:14.87#ibcon#flushed, iclass 28, count 0 2006.169.07:42:14.87#ibcon#about to write, iclass 28, count 0 2006.169.07:42:14.87#ibcon#wrote, iclass 28, count 0 2006.169.07:42:14.87#ibcon#about to read 3, iclass 28, count 0 2006.169.07:42:14.93#ibcon#read 3, iclass 28, count 0 2006.169.07:42:14.93#ibcon#about to read 4, iclass 28, count 0 2006.169.07:42:14.93#ibcon#read 4, iclass 28, count 0 2006.169.07:42:14.93#ibcon#about to read 5, iclass 28, count 0 2006.169.07:42:14.93#ibcon#read 5, iclass 28, count 0 2006.169.07:42:14.93#ibcon#about to read 6, iclass 28, count 0 2006.169.07:42:14.93#ibcon#read 6, iclass 28, count 0 2006.169.07:42:14.93#ibcon#end of sib2, iclass 28, count 0 2006.169.07:42:14.93#ibcon#*after write, iclass 28, count 0 2006.169.07:42:14.93#ibcon#*before return 0, iclass 28, count 0 2006.169.07:42:14.93#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:42:14.93#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:42:14.93#ibcon#about to clear, iclass 28 cls_cnt 0 2006.169.07:42:14.93#ibcon#cleared, iclass 28 cls_cnt 0 2006.169.07:42:14.93$vc4f8/va=1,8 2006.169.07:42:14.93#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.169.07:42:14.93#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.169.07:42:14.93#ibcon#ireg 11 cls_cnt 2 2006.169.07:42:14.93#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:42:14.93#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:42:14.93#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:42:14.93#ibcon#enter wrdev, iclass 30, count 2 2006.169.07:42:14.93#ibcon#first serial, iclass 30, count 2 2006.169.07:42:14.93#ibcon#enter sib2, iclass 30, count 2 2006.169.07:42:14.93#ibcon#flushed, iclass 30, count 2 2006.169.07:42:14.93#ibcon#about to write, iclass 30, count 2 2006.169.07:42:14.93#ibcon#wrote, iclass 30, count 2 2006.169.07:42:14.93#ibcon#about to read 3, iclass 30, count 2 2006.169.07:42:14.95#ibcon#read 3, iclass 30, count 2 2006.169.07:42:14.95#ibcon#about to read 4, iclass 30, count 2 2006.169.07:42:14.95#ibcon#read 4, iclass 30, count 2 2006.169.07:42:14.95#ibcon#about to read 5, iclass 30, count 2 2006.169.07:42:14.95#ibcon#read 5, iclass 30, count 2 2006.169.07:42:14.95#ibcon#about to read 6, iclass 30, count 2 2006.169.07:42:14.95#ibcon#read 6, iclass 30, count 2 2006.169.07:42:14.95#ibcon#end of sib2, iclass 30, count 2 2006.169.07:42:14.95#ibcon#*mode == 0, iclass 30, count 2 2006.169.07:42:14.95#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.169.07:42:14.95#ibcon#[25=AT01-08\r\n] 2006.169.07:42:14.95#ibcon#*before write, iclass 30, count 2 2006.169.07:42:14.95#ibcon#enter sib2, iclass 30, count 2 2006.169.07:42:14.95#ibcon#flushed, iclass 30, count 2 2006.169.07:42:14.95#ibcon#about to write, iclass 30, count 2 2006.169.07:42:14.95#ibcon#wrote, iclass 30, count 2 2006.169.07:42:14.95#ibcon#about to read 3, iclass 30, count 2 2006.169.07:42:14.97#ibcon#read 3, iclass 30, count 2 2006.169.07:42:14.97#ibcon#about to read 4, iclass 30, count 2 2006.169.07:42:14.97#ibcon#read 4, iclass 30, count 2 2006.169.07:42:14.97#ibcon#about to read 5, iclass 30, count 2 2006.169.07:42:14.97#ibcon#read 5, iclass 30, count 2 2006.169.07:42:14.97#ibcon#about to read 6, iclass 30, count 2 2006.169.07:42:14.97#ibcon#read 6, iclass 30, count 2 2006.169.07:42:14.97#ibcon#end of sib2, iclass 30, count 2 2006.169.07:42:14.97#ibcon#*after write, iclass 30, count 2 2006.169.07:42:14.97#ibcon#*before return 0, iclass 30, count 2 2006.169.07:42:14.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:42:14.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:42:14.97#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.169.07:42:14.97#ibcon#ireg 7 cls_cnt 0 2006.169.07:42:14.97#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:42:15.09#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:42:15.09#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:42:15.09#ibcon#enter wrdev, iclass 30, count 0 2006.169.07:42:15.09#ibcon#first serial, iclass 30, count 0 2006.169.07:42:15.09#ibcon#enter sib2, iclass 30, count 0 2006.169.07:42:15.09#ibcon#flushed, iclass 30, count 0 2006.169.07:42:15.09#ibcon#about to write, iclass 30, count 0 2006.169.07:42:15.09#ibcon#wrote, iclass 30, count 0 2006.169.07:42:15.09#ibcon#about to read 3, iclass 30, count 0 2006.169.07:42:15.13#ibcon#read 3, iclass 30, count 0 2006.169.07:42:15.13#ibcon#about to read 4, iclass 30, count 0 2006.169.07:42:15.13#ibcon#read 4, iclass 30, count 0 2006.169.07:42:15.13#ibcon#about to read 5, iclass 30, count 0 2006.169.07:42:15.13#ibcon#read 5, iclass 30, count 0 2006.169.07:42:15.13#ibcon#about to read 6, iclass 30, count 0 2006.169.07:42:15.13#ibcon#read 6, iclass 30, count 0 2006.169.07:42:15.13#ibcon#end of sib2, iclass 30, count 0 2006.169.07:42:15.13#ibcon#*mode == 0, iclass 30, count 0 2006.169.07:42:15.13#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.169.07:42:15.13#ibcon#[25=USB\r\n] 2006.169.07:42:15.13#ibcon#*before write, iclass 30, count 0 2006.169.07:42:15.13#ibcon#enter sib2, iclass 30, count 0 2006.169.07:42:15.13#ibcon#flushed, iclass 30, count 0 2006.169.07:42:15.13#ibcon#about to write, iclass 30, count 0 2006.169.07:42:15.13#ibcon#wrote, iclass 30, count 0 2006.169.07:42:15.13#ibcon#about to read 3, iclass 30, count 0 2006.169.07:42:15.14#flagr#flagr/antenna,acquired 2006.169.07:42:15.16#ibcon#read 3, iclass 30, count 0 2006.169.07:42:15.16#ibcon#about to read 4, iclass 30, count 0 2006.169.07:42:15.16#ibcon#read 4, iclass 30, count 0 2006.169.07:42:15.16#ibcon#about to read 5, iclass 30, count 0 2006.169.07:42:15.16#ibcon#read 5, iclass 30, count 0 2006.169.07:42:15.16#ibcon#about to read 6, iclass 30, count 0 2006.169.07:42:15.16#ibcon#read 6, iclass 30, count 0 2006.169.07:42:15.16#ibcon#end of sib2, iclass 30, count 0 2006.169.07:42:15.16#ibcon#*after write, iclass 30, count 0 2006.169.07:42:15.16#ibcon#*before return 0, iclass 30, count 0 2006.169.07:42:15.16#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:42:15.16#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:42:15.16#ibcon#about to clear, iclass 30 cls_cnt 0 2006.169.07:42:15.16#ibcon#cleared, iclass 30 cls_cnt 0 2006.169.07:42:15.16$vc4f8/valo=2,572.99 2006.169.07:42:15.16#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.169.07:42:15.16#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.169.07:42:15.16#ibcon#ireg 17 cls_cnt 0 2006.169.07:42:15.16#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:42:15.16#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:42:15.16#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:42:15.16#ibcon#enter wrdev, iclass 32, count 0 2006.169.07:42:15.16#ibcon#first serial, iclass 32, count 0 2006.169.07:42:15.16#ibcon#enter sib2, iclass 32, count 0 2006.169.07:42:15.16#ibcon#flushed, iclass 32, count 0 2006.169.07:42:15.16#ibcon#about to write, iclass 32, count 0 2006.169.07:42:15.16#ibcon#wrote, iclass 32, count 0 2006.169.07:42:15.16#ibcon#about to read 3, iclass 32, count 0 2006.169.07:42:15.19#ibcon#read 3, iclass 32, count 0 2006.169.07:42:15.19#ibcon#about to read 4, iclass 32, count 0 2006.169.07:42:15.19#ibcon#read 4, iclass 32, count 0 2006.169.07:42:15.19#ibcon#about to read 5, iclass 32, count 0 2006.169.07:42:15.19#ibcon#read 5, iclass 32, count 0 2006.169.07:42:15.19#ibcon#about to read 6, iclass 32, count 0 2006.169.07:42:15.19#ibcon#read 6, iclass 32, count 0 2006.169.07:42:15.19#ibcon#end of sib2, iclass 32, count 0 2006.169.07:42:15.19#ibcon#*mode == 0, iclass 32, count 0 2006.169.07:42:15.19#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.169.07:42:15.19#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.07:42:15.19#ibcon#*before write, iclass 32, count 0 2006.169.07:42:15.19#ibcon#enter sib2, iclass 32, count 0 2006.169.07:42:15.19#ibcon#flushed, iclass 32, count 0 2006.169.07:42:15.19#ibcon#about to write, iclass 32, count 0 2006.169.07:42:15.19#ibcon#wrote, iclass 32, count 0 2006.169.07:42:15.19#ibcon#about to read 3, iclass 32, count 0 2006.169.07:42:15.22#ibcon#read 3, iclass 32, count 0 2006.169.07:42:15.22#ibcon#about to read 4, iclass 32, count 0 2006.169.07:42:15.22#ibcon#read 4, iclass 32, count 0 2006.169.07:42:15.22#ibcon#about to read 5, iclass 32, count 0 2006.169.07:42:15.22#ibcon#read 5, iclass 32, count 0 2006.169.07:42:15.22#ibcon#about to read 6, iclass 32, count 0 2006.169.07:42:15.22#ibcon#read 6, iclass 32, count 0 2006.169.07:42:15.22#ibcon#end of sib2, iclass 32, count 0 2006.169.07:42:15.22#ibcon#*after write, iclass 32, count 0 2006.169.07:42:15.22#ibcon#*before return 0, iclass 32, count 0 2006.169.07:42:15.22#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:42:15.22#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:42:15.22#ibcon#about to clear, iclass 32 cls_cnt 0 2006.169.07:42:15.22#ibcon#cleared, iclass 32 cls_cnt 0 2006.169.07:42:15.22$vc4f8/va=2,7 2006.169.07:42:15.22#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.169.07:42:15.22#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.169.07:42:15.22#ibcon#ireg 11 cls_cnt 2 2006.169.07:42:15.22#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.169.07:42:15.28#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.169.07:42:15.28#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.169.07:42:15.28#ibcon#enter wrdev, iclass 34, count 2 2006.169.07:42:15.28#ibcon#first serial, iclass 34, count 2 2006.169.07:42:15.28#ibcon#enter sib2, iclass 34, count 2 2006.169.07:42:15.28#ibcon#flushed, iclass 34, count 2 2006.169.07:42:15.28#ibcon#about to write, iclass 34, count 2 2006.169.07:42:15.28#ibcon#wrote, iclass 34, count 2 2006.169.07:42:15.28#ibcon#about to read 3, iclass 34, count 2 2006.169.07:42:15.31#ibcon#read 3, iclass 34, count 2 2006.169.07:42:15.31#ibcon#about to read 4, iclass 34, count 2 2006.169.07:42:15.31#ibcon#read 4, iclass 34, count 2 2006.169.07:42:15.31#ibcon#about to read 5, iclass 34, count 2 2006.169.07:42:15.31#ibcon#read 5, iclass 34, count 2 2006.169.07:42:15.31#ibcon#about to read 6, iclass 34, count 2 2006.169.07:42:15.31#ibcon#read 6, iclass 34, count 2 2006.169.07:42:15.31#ibcon#end of sib2, iclass 34, count 2 2006.169.07:42:15.31#ibcon#*mode == 0, iclass 34, count 2 2006.169.07:42:15.31#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.169.07:42:15.31#ibcon#[25=AT02-07\r\n] 2006.169.07:42:15.31#ibcon#*before write, iclass 34, count 2 2006.169.07:42:15.31#ibcon#enter sib2, iclass 34, count 2 2006.169.07:42:15.31#ibcon#flushed, iclass 34, count 2 2006.169.07:42:15.31#ibcon#about to write, iclass 34, count 2 2006.169.07:42:15.31#ibcon#wrote, iclass 34, count 2 2006.169.07:42:15.31#ibcon#about to read 3, iclass 34, count 2 2006.169.07:42:15.34#ibcon#read 3, iclass 34, count 2 2006.169.07:42:15.34#ibcon#about to read 4, iclass 34, count 2 2006.169.07:42:15.34#ibcon#read 4, iclass 34, count 2 2006.169.07:42:15.34#ibcon#about to read 5, iclass 34, count 2 2006.169.07:42:15.34#ibcon#read 5, iclass 34, count 2 2006.169.07:42:15.34#ibcon#about to read 6, iclass 34, count 2 2006.169.07:42:15.34#ibcon#read 6, iclass 34, count 2 2006.169.07:42:15.34#ibcon#end of sib2, iclass 34, count 2 2006.169.07:42:15.34#ibcon#*after write, iclass 34, count 2 2006.169.07:42:15.34#ibcon#*before return 0, iclass 34, count 2 2006.169.07:42:15.34#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.169.07:42:15.34#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.169.07:42:15.34#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.169.07:42:15.34#ibcon#ireg 7 cls_cnt 0 2006.169.07:42:15.34#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.169.07:42:15.46#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.169.07:42:15.46#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.169.07:42:15.46#ibcon#enter wrdev, iclass 34, count 0 2006.169.07:42:15.46#ibcon#first serial, iclass 34, count 0 2006.169.07:42:15.46#ibcon#enter sib2, iclass 34, count 0 2006.169.07:42:15.46#ibcon#flushed, iclass 34, count 0 2006.169.07:42:15.46#ibcon#about to write, iclass 34, count 0 2006.169.07:42:15.46#ibcon#wrote, iclass 34, count 0 2006.169.07:42:15.46#ibcon#about to read 3, iclass 34, count 0 2006.169.07:42:15.48#ibcon#read 3, iclass 34, count 0 2006.169.07:42:15.48#ibcon#about to read 4, iclass 34, count 0 2006.169.07:42:15.48#ibcon#read 4, iclass 34, count 0 2006.169.07:42:15.48#ibcon#about to read 5, iclass 34, count 0 2006.169.07:42:15.48#ibcon#read 5, iclass 34, count 0 2006.169.07:42:15.48#ibcon#about to read 6, iclass 34, count 0 2006.169.07:42:15.48#ibcon#read 6, iclass 34, count 0 2006.169.07:42:15.48#ibcon#end of sib2, iclass 34, count 0 2006.169.07:42:15.48#ibcon#*mode == 0, iclass 34, count 0 2006.169.07:42:15.48#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.169.07:42:15.48#ibcon#[25=USB\r\n] 2006.169.07:42:15.48#ibcon#*before write, iclass 34, count 0 2006.169.07:42:15.48#ibcon#enter sib2, iclass 34, count 0 2006.169.07:42:15.48#ibcon#flushed, iclass 34, count 0 2006.169.07:42:15.48#ibcon#about to write, iclass 34, count 0 2006.169.07:42:15.48#ibcon#wrote, iclass 34, count 0 2006.169.07:42:15.48#ibcon#about to read 3, iclass 34, count 0 2006.169.07:42:15.51#ibcon#read 3, iclass 34, count 0 2006.169.07:42:15.51#ibcon#about to read 4, iclass 34, count 0 2006.169.07:42:15.51#ibcon#read 4, iclass 34, count 0 2006.169.07:42:15.51#ibcon#about to read 5, iclass 34, count 0 2006.169.07:42:15.51#ibcon#read 5, iclass 34, count 0 2006.169.07:42:15.51#ibcon#about to read 6, iclass 34, count 0 2006.169.07:42:15.51#ibcon#read 6, iclass 34, count 0 2006.169.07:42:15.51#ibcon#end of sib2, iclass 34, count 0 2006.169.07:42:15.51#ibcon#*after write, iclass 34, count 0 2006.169.07:42:15.51#ibcon#*before return 0, iclass 34, count 0 2006.169.07:42:15.51#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.169.07:42:15.51#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.169.07:42:15.51#ibcon#about to clear, iclass 34 cls_cnt 0 2006.169.07:42:15.51#ibcon#cleared, iclass 34 cls_cnt 0 2006.169.07:42:15.51$vc4f8/valo=3,672.99 2006.169.07:42:15.51#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.169.07:42:15.51#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.169.07:42:15.51#ibcon#ireg 17 cls_cnt 0 2006.169.07:42:15.51#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.169.07:42:15.51#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.169.07:42:15.51#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.169.07:42:15.51#ibcon#enter wrdev, iclass 36, count 0 2006.169.07:42:15.51#ibcon#first serial, iclass 36, count 0 2006.169.07:42:15.51#ibcon#enter sib2, iclass 36, count 0 2006.169.07:42:15.51#ibcon#flushed, iclass 36, count 0 2006.169.07:42:15.51#ibcon#about to write, iclass 36, count 0 2006.169.07:42:15.51#ibcon#wrote, iclass 36, count 0 2006.169.07:42:15.51#ibcon#about to read 3, iclass 36, count 0 2006.169.07:42:15.53#ibcon#read 3, iclass 36, count 0 2006.169.07:42:15.53#ibcon#about to read 4, iclass 36, count 0 2006.169.07:42:15.53#ibcon#read 4, iclass 36, count 0 2006.169.07:42:15.53#ibcon#about to read 5, iclass 36, count 0 2006.169.07:42:15.53#ibcon#read 5, iclass 36, count 0 2006.169.07:42:15.53#ibcon#about to read 6, iclass 36, count 0 2006.169.07:42:15.53#ibcon#read 6, iclass 36, count 0 2006.169.07:42:15.53#ibcon#end of sib2, iclass 36, count 0 2006.169.07:42:15.53#ibcon#*mode == 0, iclass 36, count 0 2006.169.07:42:15.53#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.169.07:42:15.53#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.07:42:15.53#ibcon#*before write, iclass 36, count 0 2006.169.07:42:15.53#ibcon#enter sib2, iclass 36, count 0 2006.169.07:42:15.53#ibcon#flushed, iclass 36, count 0 2006.169.07:42:15.53#ibcon#about to write, iclass 36, count 0 2006.169.07:42:15.53#ibcon#wrote, iclass 36, count 0 2006.169.07:42:15.53#ibcon#about to read 3, iclass 36, count 0 2006.169.07:42:15.57#ibcon#read 3, iclass 36, count 0 2006.169.07:42:15.57#ibcon#about to read 4, iclass 36, count 0 2006.169.07:42:15.57#ibcon#read 4, iclass 36, count 0 2006.169.07:42:15.57#ibcon#about to read 5, iclass 36, count 0 2006.169.07:42:15.57#ibcon#read 5, iclass 36, count 0 2006.169.07:42:15.57#ibcon#about to read 6, iclass 36, count 0 2006.169.07:42:15.57#ibcon#read 6, iclass 36, count 0 2006.169.07:42:15.57#ibcon#end of sib2, iclass 36, count 0 2006.169.07:42:15.57#ibcon#*after write, iclass 36, count 0 2006.169.07:42:15.57#ibcon#*before return 0, iclass 36, count 0 2006.169.07:42:15.57#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.169.07:42:15.57#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.169.07:42:15.57#ibcon#about to clear, iclass 36 cls_cnt 0 2006.169.07:42:15.57#ibcon#cleared, iclass 36 cls_cnt 0 2006.169.07:42:15.58$vc4f8/va=3,6 2006.169.07:42:15.58#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.169.07:42:15.58#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.169.07:42:15.58#ibcon#ireg 11 cls_cnt 2 2006.169.07:42:15.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.169.07:42:15.62#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.169.07:42:15.62#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.169.07:42:15.62#ibcon#enter wrdev, iclass 38, count 2 2006.169.07:42:15.62#ibcon#first serial, iclass 38, count 2 2006.169.07:42:15.62#ibcon#enter sib2, iclass 38, count 2 2006.169.07:42:15.62#ibcon#flushed, iclass 38, count 2 2006.169.07:42:15.62#ibcon#about to write, iclass 38, count 2 2006.169.07:42:15.62#ibcon#wrote, iclass 38, count 2 2006.169.07:42:15.62#ibcon#about to read 3, iclass 38, count 2 2006.169.07:42:15.65#ibcon#read 3, iclass 38, count 2 2006.169.07:42:15.65#ibcon#about to read 4, iclass 38, count 2 2006.169.07:42:15.65#ibcon#read 4, iclass 38, count 2 2006.169.07:42:15.65#ibcon#about to read 5, iclass 38, count 2 2006.169.07:42:15.65#ibcon#read 5, iclass 38, count 2 2006.169.07:42:15.65#ibcon#about to read 6, iclass 38, count 2 2006.169.07:42:15.65#ibcon#read 6, iclass 38, count 2 2006.169.07:42:15.65#ibcon#end of sib2, iclass 38, count 2 2006.169.07:42:15.65#ibcon#*mode == 0, iclass 38, count 2 2006.169.07:42:15.65#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.169.07:42:15.65#ibcon#[25=AT03-06\r\n] 2006.169.07:42:15.65#ibcon#*before write, iclass 38, count 2 2006.169.07:42:15.65#ibcon#enter sib2, iclass 38, count 2 2006.169.07:42:15.65#ibcon#flushed, iclass 38, count 2 2006.169.07:42:15.65#ibcon#about to write, iclass 38, count 2 2006.169.07:42:15.65#ibcon#wrote, iclass 38, count 2 2006.169.07:42:15.65#ibcon#about to read 3, iclass 38, count 2 2006.169.07:42:15.68#ibcon#read 3, iclass 38, count 2 2006.169.07:42:15.68#ibcon#about to read 4, iclass 38, count 2 2006.169.07:42:15.68#ibcon#read 4, iclass 38, count 2 2006.169.07:42:15.68#ibcon#about to read 5, iclass 38, count 2 2006.169.07:42:15.68#ibcon#read 5, iclass 38, count 2 2006.169.07:42:15.68#ibcon#about to read 6, iclass 38, count 2 2006.169.07:42:15.68#ibcon#read 6, iclass 38, count 2 2006.169.07:42:15.68#ibcon#end of sib2, iclass 38, count 2 2006.169.07:42:15.68#ibcon#*after write, iclass 38, count 2 2006.169.07:42:15.68#ibcon#*before return 0, iclass 38, count 2 2006.169.07:42:15.68#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.169.07:42:15.68#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.169.07:42:15.68#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.169.07:42:15.68#ibcon#ireg 7 cls_cnt 0 2006.169.07:42:15.68#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.169.07:42:15.80#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.169.07:42:15.80#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.169.07:42:15.80#ibcon#enter wrdev, iclass 38, count 0 2006.169.07:42:15.80#ibcon#first serial, iclass 38, count 0 2006.169.07:42:15.80#ibcon#enter sib2, iclass 38, count 0 2006.169.07:42:15.80#ibcon#flushed, iclass 38, count 0 2006.169.07:42:15.80#ibcon#about to write, iclass 38, count 0 2006.169.07:42:15.80#ibcon#wrote, iclass 38, count 0 2006.169.07:42:15.80#ibcon#about to read 3, iclass 38, count 0 2006.169.07:42:15.82#ibcon#read 3, iclass 38, count 0 2006.169.07:42:15.82#ibcon#about to read 4, iclass 38, count 0 2006.169.07:42:15.82#ibcon#read 4, iclass 38, count 0 2006.169.07:42:15.82#ibcon#about to read 5, iclass 38, count 0 2006.169.07:42:15.82#ibcon#read 5, iclass 38, count 0 2006.169.07:42:15.82#ibcon#about to read 6, iclass 38, count 0 2006.169.07:42:15.82#ibcon#read 6, iclass 38, count 0 2006.169.07:42:15.82#ibcon#end of sib2, iclass 38, count 0 2006.169.07:42:15.82#ibcon#*mode == 0, iclass 38, count 0 2006.169.07:42:15.82#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.169.07:42:15.82#ibcon#[25=USB\r\n] 2006.169.07:42:15.82#ibcon#*before write, iclass 38, count 0 2006.169.07:42:15.82#ibcon#enter sib2, iclass 38, count 0 2006.169.07:42:15.82#ibcon#flushed, iclass 38, count 0 2006.169.07:42:15.82#ibcon#about to write, iclass 38, count 0 2006.169.07:42:15.82#ibcon#wrote, iclass 38, count 0 2006.169.07:42:15.82#ibcon#about to read 3, iclass 38, count 0 2006.169.07:42:15.85#ibcon#read 3, iclass 38, count 0 2006.169.07:42:15.85#ibcon#about to read 4, iclass 38, count 0 2006.169.07:42:15.85#ibcon#read 4, iclass 38, count 0 2006.169.07:42:15.85#ibcon#about to read 5, iclass 38, count 0 2006.169.07:42:15.85#ibcon#read 5, iclass 38, count 0 2006.169.07:42:15.85#ibcon#about to read 6, iclass 38, count 0 2006.169.07:42:15.85#ibcon#read 6, iclass 38, count 0 2006.169.07:42:15.85#ibcon#end of sib2, iclass 38, count 0 2006.169.07:42:15.85#ibcon#*after write, iclass 38, count 0 2006.169.07:42:15.85#ibcon#*before return 0, iclass 38, count 0 2006.169.07:42:15.85#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.169.07:42:15.85#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.169.07:42:15.85#ibcon#about to clear, iclass 38 cls_cnt 0 2006.169.07:42:15.85#ibcon#cleared, iclass 38 cls_cnt 0 2006.169.07:42:15.85$vc4f8/valo=4,832.99 2006.169.07:42:15.85#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.169.07:42:15.85#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.169.07:42:15.85#ibcon#ireg 17 cls_cnt 0 2006.169.07:42:15.85#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:42:15.85#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:42:15.85#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:42:15.85#ibcon#enter wrdev, iclass 40, count 0 2006.169.07:42:15.85#ibcon#first serial, iclass 40, count 0 2006.169.07:42:15.85#ibcon#enter sib2, iclass 40, count 0 2006.169.07:42:15.85#ibcon#flushed, iclass 40, count 0 2006.169.07:42:15.85#ibcon#about to write, iclass 40, count 0 2006.169.07:42:15.85#ibcon#wrote, iclass 40, count 0 2006.169.07:42:15.85#ibcon#about to read 3, iclass 40, count 0 2006.169.07:42:15.87#ibcon#read 3, iclass 40, count 0 2006.169.07:42:15.87#ibcon#about to read 4, iclass 40, count 0 2006.169.07:42:15.87#ibcon#read 4, iclass 40, count 0 2006.169.07:42:15.87#ibcon#about to read 5, iclass 40, count 0 2006.169.07:42:15.87#ibcon#read 5, iclass 40, count 0 2006.169.07:42:15.87#ibcon#about to read 6, iclass 40, count 0 2006.169.07:42:15.87#ibcon#read 6, iclass 40, count 0 2006.169.07:42:15.87#ibcon#end of sib2, iclass 40, count 0 2006.169.07:42:15.87#ibcon#*mode == 0, iclass 40, count 0 2006.169.07:42:15.87#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.169.07:42:15.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.07:42:15.87#ibcon#*before write, iclass 40, count 0 2006.169.07:42:15.87#ibcon#enter sib2, iclass 40, count 0 2006.169.07:42:15.87#ibcon#flushed, iclass 40, count 0 2006.169.07:42:15.87#ibcon#about to write, iclass 40, count 0 2006.169.07:42:15.87#ibcon#wrote, iclass 40, count 0 2006.169.07:42:15.87#ibcon#about to read 3, iclass 40, count 0 2006.169.07:42:15.91#ibcon#read 3, iclass 40, count 0 2006.169.07:42:15.91#ibcon#about to read 4, iclass 40, count 0 2006.169.07:42:15.91#ibcon#read 4, iclass 40, count 0 2006.169.07:42:15.91#ibcon#about to read 5, iclass 40, count 0 2006.169.07:42:15.91#ibcon#read 5, iclass 40, count 0 2006.169.07:42:15.91#ibcon#about to read 6, iclass 40, count 0 2006.169.07:42:15.91#ibcon#read 6, iclass 40, count 0 2006.169.07:42:15.91#ibcon#end of sib2, iclass 40, count 0 2006.169.07:42:15.91#ibcon#*after write, iclass 40, count 0 2006.169.07:42:15.91#ibcon#*before return 0, iclass 40, count 0 2006.169.07:42:15.91#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:42:15.91#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:42:15.91#ibcon#about to clear, iclass 40 cls_cnt 0 2006.169.07:42:15.91#ibcon#cleared, iclass 40 cls_cnt 0 2006.169.07:42:15.91$vc4f8/va=4,7 2006.169.07:42:15.91#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.169.07:42:15.91#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.169.07:42:15.91#ibcon#ireg 11 cls_cnt 2 2006.169.07:42:15.91#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.169.07:42:15.97#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.169.07:42:15.97#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.169.07:42:15.97#ibcon#enter wrdev, iclass 4, count 2 2006.169.07:42:15.97#ibcon#first serial, iclass 4, count 2 2006.169.07:42:15.97#ibcon#enter sib2, iclass 4, count 2 2006.169.07:42:15.97#ibcon#flushed, iclass 4, count 2 2006.169.07:42:15.97#ibcon#about to write, iclass 4, count 2 2006.169.07:42:15.97#ibcon#wrote, iclass 4, count 2 2006.169.07:42:15.97#ibcon#about to read 3, iclass 4, count 2 2006.169.07:42:15.99#ibcon#read 3, iclass 4, count 2 2006.169.07:42:15.99#ibcon#about to read 4, iclass 4, count 2 2006.169.07:42:15.99#ibcon#read 4, iclass 4, count 2 2006.169.07:42:15.99#ibcon#about to read 5, iclass 4, count 2 2006.169.07:42:15.99#ibcon#read 5, iclass 4, count 2 2006.169.07:42:15.99#ibcon#about to read 6, iclass 4, count 2 2006.169.07:42:15.99#ibcon#read 6, iclass 4, count 2 2006.169.07:42:15.99#ibcon#end of sib2, iclass 4, count 2 2006.169.07:42:15.99#ibcon#*mode == 0, iclass 4, count 2 2006.169.07:42:15.99#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.169.07:42:15.99#ibcon#[25=AT04-07\r\n] 2006.169.07:42:15.99#ibcon#*before write, iclass 4, count 2 2006.169.07:42:15.99#ibcon#enter sib2, iclass 4, count 2 2006.169.07:42:15.99#ibcon#flushed, iclass 4, count 2 2006.169.07:42:15.99#ibcon#about to write, iclass 4, count 2 2006.169.07:42:15.99#ibcon#wrote, iclass 4, count 2 2006.169.07:42:15.99#ibcon#about to read 3, iclass 4, count 2 2006.169.07:42:16.02#ibcon#read 3, iclass 4, count 2 2006.169.07:42:16.02#ibcon#about to read 4, iclass 4, count 2 2006.169.07:42:16.02#ibcon#read 4, iclass 4, count 2 2006.169.07:42:16.02#ibcon#about to read 5, iclass 4, count 2 2006.169.07:42:16.02#ibcon#read 5, iclass 4, count 2 2006.169.07:42:16.02#ibcon#about to read 6, iclass 4, count 2 2006.169.07:42:16.02#ibcon#read 6, iclass 4, count 2 2006.169.07:42:16.02#ibcon#end of sib2, iclass 4, count 2 2006.169.07:42:16.02#ibcon#*after write, iclass 4, count 2 2006.169.07:42:16.02#ibcon#*before return 0, iclass 4, count 2 2006.169.07:42:16.02#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.169.07:42:16.02#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.169.07:42:16.02#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.169.07:42:16.02#ibcon#ireg 7 cls_cnt 0 2006.169.07:42:16.02#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.169.07:42:16.14#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.169.07:42:16.14#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.169.07:42:16.14#ibcon#enter wrdev, iclass 4, count 0 2006.169.07:42:16.14#ibcon#first serial, iclass 4, count 0 2006.169.07:42:16.14#ibcon#enter sib2, iclass 4, count 0 2006.169.07:42:16.14#ibcon#flushed, iclass 4, count 0 2006.169.07:42:16.14#ibcon#about to write, iclass 4, count 0 2006.169.07:42:16.14#ibcon#wrote, iclass 4, count 0 2006.169.07:42:16.14#ibcon#about to read 3, iclass 4, count 0 2006.169.07:42:16.16#ibcon#read 3, iclass 4, count 0 2006.169.07:42:16.16#ibcon#about to read 4, iclass 4, count 0 2006.169.07:42:16.16#ibcon#read 4, iclass 4, count 0 2006.169.07:42:16.16#ibcon#about to read 5, iclass 4, count 0 2006.169.07:42:16.16#ibcon#read 5, iclass 4, count 0 2006.169.07:42:16.16#ibcon#about to read 6, iclass 4, count 0 2006.169.07:42:16.16#ibcon#read 6, iclass 4, count 0 2006.169.07:42:16.16#ibcon#end of sib2, iclass 4, count 0 2006.169.07:42:16.16#ibcon#*mode == 0, iclass 4, count 0 2006.169.07:42:16.16#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.169.07:42:16.16#ibcon#[25=USB\r\n] 2006.169.07:42:16.16#ibcon#*before write, iclass 4, count 0 2006.169.07:42:16.16#ibcon#enter sib2, iclass 4, count 0 2006.169.07:42:16.16#ibcon#flushed, iclass 4, count 0 2006.169.07:42:16.16#ibcon#about to write, iclass 4, count 0 2006.169.07:42:16.16#ibcon#wrote, iclass 4, count 0 2006.169.07:42:16.16#ibcon#about to read 3, iclass 4, count 0 2006.169.07:42:16.19#ibcon#read 3, iclass 4, count 0 2006.169.07:42:16.19#ibcon#about to read 4, iclass 4, count 0 2006.169.07:42:16.19#ibcon#read 4, iclass 4, count 0 2006.169.07:42:16.19#ibcon#about to read 5, iclass 4, count 0 2006.169.07:42:16.19#ibcon#read 5, iclass 4, count 0 2006.169.07:42:16.19#ibcon#about to read 6, iclass 4, count 0 2006.169.07:42:16.19#ibcon#read 6, iclass 4, count 0 2006.169.07:42:16.19#ibcon#end of sib2, iclass 4, count 0 2006.169.07:42:16.19#ibcon#*after write, iclass 4, count 0 2006.169.07:42:16.19#ibcon#*before return 0, iclass 4, count 0 2006.169.07:42:16.19#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.169.07:42:16.19#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.169.07:42:16.19#ibcon#about to clear, iclass 4 cls_cnt 0 2006.169.07:42:16.19#ibcon#cleared, iclass 4 cls_cnt 0 2006.169.07:42:16.19$vc4f8/valo=5,652.99 2006.169.07:42:16.19#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.169.07:42:16.19#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.169.07:42:16.19#ibcon#ireg 17 cls_cnt 0 2006.169.07:42:16.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:42:16.19#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:42:16.19#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:42:16.19#ibcon#enter wrdev, iclass 7, count 0 2006.169.07:42:16.19#ibcon#first serial, iclass 7, count 0 2006.169.07:42:16.19#ibcon#enter sib2, iclass 7, count 0 2006.169.07:42:16.19#ibcon#flushed, iclass 7, count 0 2006.169.07:42:16.19#ibcon#about to write, iclass 7, count 0 2006.169.07:42:16.19#ibcon#wrote, iclass 7, count 0 2006.169.07:42:16.19#ibcon#about to read 3, iclass 7, count 0 2006.169.07:42:16.21#ibcon#read 3, iclass 7, count 0 2006.169.07:42:16.21#ibcon#about to read 4, iclass 7, count 0 2006.169.07:42:16.21#ibcon#read 4, iclass 7, count 0 2006.169.07:42:16.21#ibcon#about to read 5, iclass 7, count 0 2006.169.07:42:16.21#ibcon#read 5, iclass 7, count 0 2006.169.07:42:16.21#ibcon#about to read 6, iclass 7, count 0 2006.169.07:42:16.21#ibcon#read 6, iclass 7, count 0 2006.169.07:42:16.21#ibcon#end of sib2, iclass 7, count 0 2006.169.07:42:16.21#ibcon#*mode == 0, iclass 7, count 0 2006.169.07:42:16.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.169.07:42:16.21#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.07:42:16.21#ibcon#*before write, iclass 7, count 0 2006.169.07:42:16.21#ibcon#enter sib2, iclass 7, count 0 2006.169.07:42:16.21#ibcon#flushed, iclass 7, count 0 2006.169.07:42:16.21#ibcon#about to write, iclass 7, count 0 2006.169.07:42:16.21#ibcon#wrote, iclass 7, count 0 2006.169.07:42:16.21#ibcon#about to read 3, iclass 7, count 0 2006.169.07:42:16.21#abcon#<5=/05 3.6 7.0 18.131001003.8\r\n> 2006.169.07:42:16.23#abcon#{5=INTERFACE CLEAR} 2006.169.07:42:16.25#ibcon#read 3, iclass 7, count 0 2006.169.07:42:16.25#ibcon#about to read 4, iclass 7, count 0 2006.169.07:42:16.25#ibcon#read 4, iclass 7, count 0 2006.169.07:42:16.25#ibcon#about to read 5, iclass 7, count 0 2006.169.07:42:16.25#ibcon#read 5, iclass 7, count 0 2006.169.07:42:16.25#ibcon#about to read 6, iclass 7, count 0 2006.169.07:42:16.25#ibcon#read 6, iclass 7, count 0 2006.169.07:42:16.25#ibcon#end of sib2, iclass 7, count 0 2006.169.07:42:16.25#ibcon#*after write, iclass 7, count 0 2006.169.07:42:16.25#ibcon#*before return 0, iclass 7, count 0 2006.169.07:42:16.25#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:42:16.25#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:42:16.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.169.07:42:16.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.169.07:42:16.25$vc4f8/va=5,7 2006.169.07:42:16.25#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.169.07:42:16.25#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.169.07:42:16.25#ibcon#ireg 11 cls_cnt 2 2006.169.07:42:16.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.169.07:42:16.29#abcon#[5=S1D000X0/0*\r\n] 2006.169.07:42:16.31#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.169.07:42:16.31#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.169.07:42:16.31#ibcon#enter wrdev, iclass 13, count 2 2006.169.07:42:16.31#ibcon#first serial, iclass 13, count 2 2006.169.07:42:16.31#ibcon#enter sib2, iclass 13, count 2 2006.169.07:42:16.31#ibcon#flushed, iclass 13, count 2 2006.169.07:42:16.31#ibcon#about to write, iclass 13, count 2 2006.169.07:42:16.31#ibcon#wrote, iclass 13, count 2 2006.169.07:42:16.31#ibcon#about to read 3, iclass 13, count 2 2006.169.07:42:16.33#ibcon#read 3, iclass 13, count 2 2006.169.07:42:16.33#ibcon#about to read 4, iclass 13, count 2 2006.169.07:42:16.33#ibcon#read 4, iclass 13, count 2 2006.169.07:42:16.33#ibcon#about to read 5, iclass 13, count 2 2006.169.07:42:16.33#ibcon#read 5, iclass 13, count 2 2006.169.07:42:16.33#ibcon#about to read 6, iclass 13, count 2 2006.169.07:42:16.33#ibcon#read 6, iclass 13, count 2 2006.169.07:42:16.33#ibcon#end of sib2, iclass 13, count 2 2006.169.07:42:16.33#ibcon#*mode == 0, iclass 13, count 2 2006.169.07:42:16.33#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.169.07:42:16.33#ibcon#[25=AT05-07\r\n] 2006.169.07:42:16.33#ibcon#*before write, iclass 13, count 2 2006.169.07:42:16.33#ibcon#enter sib2, iclass 13, count 2 2006.169.07:42:16.33#ibcon#flushed, iclass 13, count 2 2006.169.07:42:16.33#ibcon#about to write, iclass 13, count 2 2006.169.07:42:16.33#ibcon#wrote, iclass 13, count 2 2006.169.07:42:16.33#ibcon#about to read 3, iclass 13, count 2 2006.169.07:42:16.36#ibcon#read 3, iclass 13, count 2 2006.169.07:42:16.36#ibcon#about to read 4, iclass 13, count 2 2006.169.07:42:16.36#ibcon#read 4, iclass 13, count 2 2006.169.07:42:16.36#ibcon#about to read 5, iclass 13, count 2 2006.169.07:42:16.36#ibcon#read 5, iclass 13, count 2 2006.169.07:42:16.36#ibcon#about to read 6, iclass 13, count 2 2006.169.07:42:16.36#ibcon#read 6, iclass 13, count 2 2006.169.07:42:16.36#ibcon#end of sib2, iclass 13, count 2 2006.169.07:42:16.36#ibcon#*after write, iclass 13, count 2 2006.169.07:42:16.36#ibcon#*before return 0, iclass 13, count 2 2006.169.07:42:16.36#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.169.07:42:16.36#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.169.07:42:16.36#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.169.07:42:16.36#ibcon#ireg 7 cls_cnt 0 2006.169.07:42:16.36#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.169.07:42:16.48#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.169.07:42:16.48#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.169.07:42:16.48#ibcon#enter wrdev, iclass 13, count 0 2006.169.07:42:16.48#ibcon#first serial, iclass 13, count 0 2006.169.07:42:16.48#ibcon#enter sib2, iclass 13, count 0 2006.169.07:42:16.48#ibcon#flushed, iclass 13, count 0 2006.169.07:42:16.48#ibcon#about to write, iclass 13, count 0 2006.169.07:42:16.48#ibcon#wrote, iclass 13, count 0 2006.169.07:42:16.48#ibcon#about to read 3, iclass 13, count 0 2006.169.07:42:16.50#ibcon#read 3, iclass 13, count 0 2006.169.07:42:16.50#ibcon#about to read 4, iclass 13, count 0 2006.169.07:42:16.50#ibcon#read 4, iclass 13, count 0 2006.169.07:42:16.50#ibcon#about to read 5, iclass 13, count 0 2006.169.07:42:16.50#ibcon#read 5, iclass 13, count 0 2006.169.07:42:16.50#ibcon#about to read 6, iclass 13, count 0 2006.169.07:42:16.50#ibcon#read 6, iclass 13, count 0 2006.169.07:42:16.50#ibcon#end of sib2, iclass 13, count 0 2006.169.07:42:16.50#ibcon#*mode == 0, iclass 13, count 0 2006.169.07:42:16.50#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.07:42:16.50#ibcon#[25=USB\r\n] 2006.169.07:42:16.50#ibcon#*before write, iclass 13, count 0 2006.169.07:42:16.50#ibcon#enter sib2, iclass 13, count 0 2006.169.07:42:16.50#ibcon#flushed, iclass 13, count 0 2006.169.07:42:16.50#ibcon#about to write, iclass 13, count 0 2006.169.07:42:16.50#ibcon#wrote, iclass 13, count 0 2006.169.07:42:16.50#ibcon#about to read 3, iclass 13, count 0 2006.169.07:42:16.53#ibcon#read 3, iclass 13, count 0 2006.169.07:42:16.53#ibcon#about to read 4, iclass 13, count 0 2006.169.07:42:16.53#ibcon#read 4, iclass 13, count 0 2006.169.07:42:16.53#ibcon#about to read 5, iclass 13, count 0 2006.169.07:42:16.53#ibcon#read 5, iclass 13, count 0 2006.169.07:42:16.53#ibcon#about to read 6, iclass 13, count 0 2006.169.07:42:16.53#ibcon#read 6, iclass 13, count 0 2006.169.07:42:16.53#ibcon#end of sib2, iclass 13, count 0 2006.169.07:42:16.53#ibcon#*after write, iclass 13, count 0 2006.169.07:42:16.53#ibcon#*before return 0, iclass 13, count 0 2006.169.07:42:16.53#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.169.07:42:16.53#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.169.07:42:16.53#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.07:42:16.53#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.07:42:16.53$vc4f8/valo=6,772.99 2006.169.07:42:16.53#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.169.07:42:16.53#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.169.07:42:16.53#ibcon#ireg 17 cls_cnt 0 2006.169.07:42:16.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:42:16.53#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:42:16.53#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:42:16.53#ibcon#enter wrdev, iclass 16, count 0 2006.169.07:42:16.53#ibcon#first serial, iclass 16, count 0 2006.169.07:42:16.53#ibcon#enter sib2, iclass 16, count 0 2006.169.07:42:16.53#ibcon#flushed, iclass 16, count 0 2006.169.07:42:16.53#ibcon#about to write, iclass 16, count 0 2006.169.07:42:16.53#ibcon#wrote, iclass 16, count 0 2006.169.07:42:16.53#ibcon#about to read 3, iclass 16, count 0 2006.169.07:42:16.55#ibcon#read 3, iclass 16, count 0 2006.169.07:42:16.55#ibcon#about to read 4, iclass 16, count 0 2006.169.07:42:16.55#ibcon#read 4, iclass 16, count 0 2006.169.07:42:16.55#ibcon#about to read 5, iclass 16, count 0 2006.169.07:42:16.55#ibcon#read 5, iclass 16, count 0 2006.169.07:42:16.55#ibcon#about to read 6, iclass 16, count 0 2006.169.07:42:16.55#ibcon#read 6, iclass 16, count 0 2006.169.07:42:16.55#ibcon#end of sib2, iclass 16, count 0 2006.169.07:42:16.55#ibcon#*mode == 0, iclass 16, count 0 2006.169.07:42:16.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.169.07:42:16.55#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.07:42:16.55#ibcon#*before write, iclass 16, count 0 2006.169.07:42:16.55#ibcon#enter sib2, iclass 16, count 0 2006.169.07:42:16.55#ibcon#flushed, iclass 16, count 0 2006.169.07:42:16.55#ibcon#about to write, iclass 16, count 0 2006.169.07:42:16.55#ibcon#wrote, iclass 16, count 0 2006.169.07:42:16.55#ibcon#about to read 3, iclass 16, count 0 2006.169.07:42:16.59#ibcon#read 3, iclass 16, count 0 2006.169.07:42:16.59#ibcon#about to read 4, iclass 16, count 0 2006.169.07:42:16.59#ibcon#read 4, iclass 16, count 0 2006.169.07:42:16.59#ibcon#about to read 5, iclass 16, count 0 2006.169.07:42:16.59#ibcon#read 5, iclass 16, count 0 2006.169.07:42:16.59#ibcon#about to read 6, iclass 16, count 0 2006.169.07:42:16.59#ibcon#read 6, iclass 16, count 0 2006.169.07:42:16.59#ibcon#end of sib2, iclass 16, count 0 2006.169.07:42:16.59#ibcon#*after write, iclass 16, count 0 2006.169.07:42:16.59#ibcon#*before return 0, iclass 16, count 0 2006.169.07:42:16.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:42:16.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:42:16.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.169.07:42:16.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.169.07:42:16.59$vc4f8/va=6,6 2006.169.07:42:16.59#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.169.07:42:16.59#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.169.07:42:16.59#ibcon#ireg 11 cls_cnt 2 2006.169.07:42:16.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.169.07:42:16.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.169.07:42:16.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.169.07:42:16.65#ibcon#enter wrdev, iclass 18, count 2 2006.169.07:42:16.65#ibcon#first serial, iclass 18, count 2 2006.169.07:42:16.65#ibcon#enter sib2, iclass 18, count 2 2006.169.07:42:16.65#ibcon#flushed, iclass 18, count 2 2006.169.07:42:16.65#ibcon#about to write, iclass 18, count 2 2006.169.07:42:16.65#ibcon#wrote, iclass 18, count 2 2006.169.07:42:16.65#ibcon#about to read 3, iclass 18, count 2 2006.169.07:42:16.67#ibcon#read 3, iclass 18, count 2 2006.169.07:42:16.67#ibcon#about to read 4, iclass 18, count 2 2006.169.07:42:16.67#ibcon#read 4, iclass 18, count 2 2006.169.07:42:16.67#ibcon#about to read 5, iclass 18, count 2 2006.169.07:42:16.67#ibcon#read 5, iclass 18, count 2 2006.169.07:42:16.67#ibcon#about to read 6, iclass 18, count 2 2006.169.07:42:16.67#ibcon#read 6, iclass 18, count 2 2006.169.07:42:16.67#ibcon#end of sib2, iclass 18, count 2 2006.169.07:42:16.67#ibcon#*mode == 0, iclass 18, count 2 2006.169.07:42:16.67#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.169.07:42:16.67#ibcon#[25=AT06-06\r\n] 2006.169.07:42:16.67#ibcon#*before write, iclass 18, count 2 2006.169.07:42:16.67#ibcon#enter sib2, iclass 18, count 2 2006.169.07:42:16.67#ibcon#flushed, iclass 18, count 2 2006.169.07:42:16.67#ibcon#about to write, iclass 18, count 2 2006.169.07:42:16.67#ibcon#wrote, iclass 18, count 2 2006.169.07:42:16.67#ibcon#about to read 3, iclass 18, count 2 2006.169.07:42:16.70#ibcon#read 3, iclass 18, count 2 2006.169.07:42:16.70#ibcon#about to read 4, iclass 18, count 2 2006.169.07:42:16.70#ibcon#read 4, iclass 18, count 2 2006.169.07:42:16.70#ibcon#about to read 5, iclass 18, count 2 2006.169.07:42:16.70#ibcon#read 5, iclass 18, count 2 2006.169.07:42:16.70#ibcon#about to read 6, iclass 18, count 2 2006.169.07:42:16.70#ibcon#read 6, iclass 18, count 2 2006.169.07:42:16.70#ibcon#end of sib2, iclass 18, count 2 2006.169.07:42:16.70#ibcon#*after write, iclass 18, count 2 2006.169.07:42:16.70#ibcon#*before return 0, iclass 18, count 2 2006.169.07:42:16.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.169.07:42:16.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.169.07:42:16.70#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.169.07:42:16.70#ibcon#ireg 7 cls_cnt 0 2006.169.07:42:16.70#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.169.07:42:16.82#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.169.07:42:16.82#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.169.07:42:16.82#ibcon#enter wrdev, iclass 18, count 0 2006.169.07:42:16.82#ibcon#first serial, iclass 18, count 0 2006.169.07:42:16.82#ibcon#enter sib2, iclass 18, count 0 2006.169.07:42:16.82#ibcon#flushed, iclass 18, count 0 2006.169.07:42:16.82#ibcon#about to write, iclass 18, count 0 2006.169.07:42:16.82#ibcon#wrote, iclass 18, count 0 2006.169.07:42:16.82#ibcon#about to read 3, iclass 18, count 0 2006.169.07:42:16.84#ibcon#read 3, iclass 18, count 0 2006.169.07:42:16.84#ibcon#about to read 4, iclass 18, count 0 2006.169.07:42:16.84#ibcon#read 4, iclass 18, count 0 2006.169.07:42:16.84#ibcon#about to read 5, iclass 18, count 0 2006.169.07:42:16.84#ibcon#read 5, iclass 18, count 0 2006.169.07:42:16.84#ibcon#about to read 6, iclass 18, count 0 2006.169.07:42:16.84#ibcon#read 6, iclass 18, count 0 2006.169.07:42:16.84#ibcon#end of sib2, iclass 18, count 0 2006.169.07:42:16.84#ibcon#*mode == 0, iclass 18, count 0 2006.169.07:42:16.84#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.169.07:42:16.84#ibcon#[25=USB\r\n] 2006.169.07:42:16.84#ibcon#*before write, iclass 18, count 0 2006.169.07:42:16.84#ibcon#enter sib2, iclass 18, count 0 2006.169.07:42:16.84#ibcon#flushed, iclass 18, count 0 2006.169.07:42:16.84#ibcon#about to write, iclass 18, count 0 2006.169.07:42:16.84#ibcon#wrote, iclass 18, count 0 2006.169.07:42:16.84#ibcon#about to read 3, iclass 18, count 0 2006.169.07:42:16.87#ibcon#read 3, iclass 18, count 0 2006.169.07:42:16.87#ibcon#about to read 4, iclass 18, count 0 2006.169.07:42:16.87#ibcon#read 4, iclass 18, count 0 2006.169.07:42:16.87#ibcon#about to read 5, iclass 18, count 0 2006.169.07:42:16.87#ibcon#read 5, iclass 18, count 0 2006.169.07:42:16.87#ibcon#about to read 6, iclass 18, count 0 2006.169.07:42:16.87#ibcon#read 6, iclass 18, count 0 2006.169.07:42:16.87#ibcon#end of sib2, iclass 18, count 0 2006.169.07:42:16.87#ibcon#*after write, iclass 18, count 0 2006.169.07:42:16.87#ibcon#*before return 0, iclass 18, count 0 2006.169.07:42:16.87#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.169.07:42:16.87#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.169.07:42:16.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.169.07:42:16.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.169.07:42:16.87$vc4f8/valo=7,832.99 2006.169.07:42:16.87#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.169.07:42:16.87#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.169.07:42:16.87#ibcon#ireg 17 cls_cnt 0 2006.169.07:42:16.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.169.07:42:16.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.169.07:42:16.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.169.07:42:16.87#ibcon#enter wrdev, iclass 20, count 0 2006.169.07:42:16.87#ibcon#first serial, iclass 20, count 0 2006.169.07:42:16.87#ibcon#enter sib2, iclass 20, count 0 2006.169.07:42:16.87#ibcon#flushed, iclass 20, count 0 2006.169.07:42:16.87#ibcon#about to write, iclass 20, count 0 2006.169.07:42:16.87#ibcon#wrote, iclass 20, count 0 2006.169.07:42:16.87#ibcon#about to read 3, iclass 20, count 0 2006.169.07:42:16.89#ibcon#read 3, iclass 20, count 0 2006.169.07:42:16.89#ibcon#about to read 4, iclass 20, count 0 2006.169.07:42:16.89#ibcon#read 4, iclass 20, count 0 2006.169.07:42:16.89#ibcon#about to read 5, iclass 20, count 0 2006.169.07:42:16.89#ibcon#read 5, iclass 20, count 0 2006.169.07:42:16.89#ibcon#about to read 6, iclass 20, count 0 2006.169.07:42:16.89#ibcon#read 6, iclass 20, count 0 2006.169.07:42:16.89#ibcon#end of sib2, iclass 20, count 0 2006.169.07:42:16.89#ibcon#*mode == 0, iclass 20, count 0 2006.169.07:42:16.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.169.07:42:16.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.07:42:16.89#ibcon#*before write, iclass 20, count 0 2006.169.07:42:16.89#ibcon#enter sib2, iclass 20, count 0 2006.169.07:42:16.89#ibcon#flushed, iclass 20, count 0 2006.169.07:42:16.89#ibcon#about to write, iclass 20, count 0 2006.169.07:42:16.89#ibcon#wrote, iclass 20, count 0 2006.169.07:42:16.89#ibcon#about to read 3, iclass 20, count 0 2006.169.07:42:16.93#ibcon#read 3, iclass 20, count 0 2006.169.07:42:16.93#ibcon#about to read 4, iclass 20, count 0 2006.169.07:42:16.93#ibcon#read 4, iclass 20, count 0 2006.169.07:42:16.93#ibcon#about to read 5, iclass 20, count 0 2006.169.07:42:16.93#ibcon#read 5, iclass 20, count 0 2006.169.07:42:16.93#ibcon#about to read 6, iclass 20, count 0 2006.169.07:42:16.93#ibcon#read 6, iclass 20, count 0 2006.169.07:42:16.93#ibcon#end of sib2, iclass 20, count 0 2006.169.07:42:16.93#ibcon#*after write, iclass 20, count 0 2006.169.07:42:16.93#ibcon#*before return 0, iclass 20, count 0 2006.169.07:42:16.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.169.07:42:16.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.169.07:42:16.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.169.07:42:16.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.169.07:42:16.93$vc4f8/va=7,6 2006.169.07:42:16.93#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.169.07:42:16.93#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.169.07:42:16.93#ibcon#ireg 11 cls_cnt 2 2006.169.07:42:16.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.169.07:42:16.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.169.07:42:16.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.169.07:42:16.99#ibcon#enter wrdev, iclass 22, count 2 2006.169.07:42:16.99#ibcon#first serial, iclass 22, count 2 2006.169.07:42:16.99#ibcon#enter sib2, iclass 22, count 2 2006.169.07:42:16.99#ibcon#flushed, iclass 22, count 2 2006.169.07:42:16.99#ibcon#about to write, iclass 22, count 2 2006.169.07:42:16.99#ibcon#wrote, iclass 22, count 2 2006.169.07:42:16.99#ibcon#about to read 3, iclass 22, count 2 2006.169.07:42:17.01#ibcon#read 3, iclass 22, count 2 2006.169.07:42:17.01#ibcon#about to read 4, iclass 22, count 2 2006.169.07:42:17.01#ibcon#read 4, iclass 22, count 2 2006.169.07:42:17.01#ibcon#about to read 5, iclass 22, count 2 2006.169.07:42:17.01#ibcon#read 5, iclass 22, count 2 2006.169.07:42:17.01#ibcon#about to read 6, iclass 22, count 2 2006.169.07:42:17.01#ibcon#read 6, iclass 22, count 2 2006.169.07:42:17.01#ibcon#end of sib2, iclass 22, count 2 2006.169.07:42:17.01#ibcon#*mode == 0, iclass 22, count 2 2006.169.07:42:17.01#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.169.07:42:17.01#ibcon#[25=AT07-06\r\n] 2006.169.07:42:17.01#ibcon#*before write, iclass 22, count 2 2006.169.07:42:17.01#ibcon#enter sib2, iclass 22, count 2 2006.169.07:42:17.01#ibcon#flushed, iclass 22, count 2 2006.169.07:42:17.01#ibcon#about to write, iclass 22, count 2 2006.169.07:42:17.01#ibcon#wrote, iclass 22, count 2 2006.169.07:42:17.01#ibcon#about to read 3, iclass 22, count 2 2006.169.07:42:17.04#ibcon#read 3, iclass 22, count 2 2006.169.07:42:17.04#ibcon#about to read 4, iclass 22, count 2 2006.169.07:42:17.04#ibcon#read 4, iclass 22, count 2 2006.169.07:42:17.04#ibcon#about to read 5, iclass 22, count 2 2006.169.07:42:17.04#ibcon#read 5, iclass 22, count 2 2006.169.07:42:17.04#ibcon#about to read 6, iclass 22, count 2 2006.169.07:42:17.04#ibcon#read 6, iclass 22, count 2 2006.169.07:42:17.04#ibcon#end of sib2, iclass 22, count 2 2006.169.07:42:17.04#ibcon#*after write, iclass 22, count 2 2006.169.07:42:17.04#ibcon#*before return 0, iclass 22, count 2 2006.169.07:42:17.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.169.07:42:17.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.169.07:42:17.04#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.169.07:42:17.04#ibcon#ireg 7 cls_cnt 0 2006.169.07:42:17.04#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.169.07:42:17.16#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.169.07:42:17.16#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.169.07:42:17.16#ibcon#enter wrdev, iclass 22, count 0 2006.169.07:42:17.16#ibcon#first serial, iclass 22, count 0 2006.169.07:42:17.16#ibcon#enter sib2, iclass 22, count 0 2006.169.07:42:17.16#ibcon#flushed, iclass 22, count 0 2006.169.07:42:17.16#ibcon#about to write, iclass 22, count 0 2006.169.07:42:17.16#ibcon#wrote, iclass 22, count 0 2006.169.07:42:17.16#ibcon#about to read 3, iclass 22, count 0 2006.169.07:42:17.18#ibcon#read 3, iclass 22, count 0 2006.169.07:42:17.18#ibcon#about to read 4, iclass 22, count 0 2006.169.07:42:17.18#ibcon#read 4, iclass 22, count 0 2006.169.07:42:17.18#ibcon#about to read 5, iclass 22, count 0 2006.169.07:42:17.18#ibcon#read 5, iclass 22, count 0 2006.169.07:42:17.18#ibcon#about to read 6, iclass 22, count 0 2006.169.07:42:17.18#ibcon#read 6, iclass 22, count 0 2006.169.07:42:17.18#ibcon#end of sib2, iclass 22, count 0 2006.169.07:42:17.18#ibcon#*mode == 0, iclass 22, count 0 2006.169.07:42:17.18#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.169.07:42:17.18#ibcon#[25=USB\r\n] 2006.169.07:42:17.18#ibcon#*before write, iclass 22, count 0 2006.169.07:42:17.18#ibcon#enter sib2, iclass 22, count 0 2006.169.07:42:17.18#ibcon#flushed, iclass 22, count 0 2006.169.07:42:17.18#ibcon#about to write, iclass 22, count 0 2006.169.07:42:17.18#ibcon#wrote, iclass 22, count 0 2006.169.07:42:17.18#ibcon#about to read 3, iclass 22, count 0 2006.169.07:42:17.21#ibcon#read 3, iclass 22, count 0 2006.169.07:42:17.21#ibcon#about to read 4, iclass 22, count 0 2006.169.07:42:17.21#ibcon#read 4, iclass 22, count 0 2006.169.07:42:17.21#ibcon#about to read 5, iclass 22, count 0 2006.169.07:42:17.21#ibcon#read 5, iclass 22, count 0 2006.169.07:42:17.21#ibcon#about to read 6, iclass 22, count 0 2006.169.07:42:17.21#ibcon#read 6, iclass 22, count 0 2006.169.07:42:17.21#ibcon#end of sib2, iclass 22, count 0 2006.169.07:42:17.21#ibcon#*after write, iclass 22, count 0 2006.169.07:42:17.21#ibcon#*before return 0, iclass 22, count 0 2006.169.07:42:17.21#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.169.07:42:17.21#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.169.07:42:17.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.169.07:42:17.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.169.07:42:17.21$vc4f8/valo=8,852.99 2006.169.07:42:17.21#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.169.07:42:17.21#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.169.07:42:17.21#ibcon#ireg 17 cls_cnt 0 2006.169.07:42:17.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.169.07:42:17.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.169.07:42:17.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.169.07:42:17.21#ibcon#enter wrdev, iclass 24, count 0 2006.169.07:42:17.21#ibcon#first serial, iclass 24, count 0 2006.169.07:42:17.21#ibcon#enter sib2, iclass 24, count 0 2006.169.07:42:17.21#ibcon#flushed, iclass 24, count 0 2006.169.07:42:17.21#ibcon#about to write, iclass 24, count 0 2006.169.07:42:17.21#ibcon#wrote, iclass 24, count 0 2006.169.07:42:17.21#ibcon#about to read 3, iclass 24, count 0 2006.169.07:42:17.23#ibcon#read 3, iclass 24, count 0 2006.169.07:42:17.23#ibcon#about to read 4, iclass 24, count 0 2006.169.07:42:17.23#ibcon#read 4, iclass 24, count 0 2006.169.07:42:17.23#ibcon#about to read 5, iclass 24, count 0 2006.169.07:42:17.23#ibcon#read 5, iclass 24, count 0 2006.169.07:42:17.23#ibcon#about to read 6, iclass 24, count 0 2006.169.07:42:17.23#ibcon#read 6, iclass 24, count 0 2006.169.07:42:17.23#ibcon#end of sib2, iclass 24, count 0 2006.169.07:42:17.23#ibcon#*mode == 0, iclass 24, count 0 2006.169.07:42:17.23#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.169.07:42:17.23#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.07:42:17.23#ibcon#*before write, iclass 24, count 0 2006.169.07:42:17.23#ibcon#enter sib2, iclass 24, count 0 2006.169.07:42:17.23#ibcon#flushed, iclass 24, count 0 2006.169.07:42:17.23#ibcon#about to write, iclass 24, count 0 2006.169.07:42:17.23#ibcon#wrote, iclass 24, count 0 2006.169.07:42:17.23#ibcon#about to read 3, iclass 24, count 0 2006.169.07:42:17.27#ibcon#read 3, iclass 24, count 0 2006.169.07:42:17.27#ibcon#about to read 4, iclass 24, count 0 2006.169.07:42:17.27#ibcon#read 4, iclass 24, count 0 2006.169.07:42:17.27#ibcon#about to read 5, iclass 24, count 0 2006.169.07:42:17.27#ibcon#read 5, iclass 24, count 0 2006.169.07:42:17.27#ibcon#about to read 6, iclass 24, count 0 2006.169.07:42:17.27#ibcon#read 6, iclass 24, count 0 2006.169.07:42:17.27#ibcon#end of sib2, iclass 24, count 0 2006.169.07:42:17.27#ibcon#*after write, iclass 24, count 0 2006.169.07:42:17.27#ibcon#*before return 0, iclass 24, count 0 2006.169.07:42:17.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.169.07:42:17.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.169.07:42:17.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.169.07:42:17.27#ibcon#cleared, iclass 24 cls_cnt 0 2006.169.07:42:17.27$vc4f8/va=8,7 2006.169.07:42:17.27#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.169.07:42:17.27#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.169.07:42:17.27#ibcon#ireg 11 cls_cnt 2 2006.169.07:42:17.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.169.07:42:17.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.169.07:42:17.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.169.07:42:17.33#ibcon#enter wrdev, iclass 26, count 2 2006.169.07:42:17.33#ibcon#first serial, iclass 26, count 2 2006.169.07:42:17.33#ibcon#enter sib2, iclass 26, count 2 2006.169.07:42:17.33#ibcon#flushed, iclass 26, count 2 2006.169.07:42:17.33#ibcon#about to write, iclass 26, count 2 2006.169.07:42:17.33#ibcon#wrote, iclass 26, count 2 2006.169.07:42:17.33#ibcon#about to read 3, iclass 26, count 2 2006.169.07:42:17.36#ibcon#read 3, iclass 26, count 2 2006.169.07:42:17.36#ibcon#about to read 4, iclass 26, count 2 2006.169.07:42:17.36#ibcon#read 4, iclass 26, count 2 2006.169.07:42:17.36#ibcon#about to read 5, iclass 26, count 2 2006.169.07:42:17.36#ibcon#read 5, iclass 26, count 2 2006.169.07:42:17.36#ibcon#about to read 6, iclass 26, count 2 2006.169.07:42:17.36#ibcon#read 6, iclass 26, count 2 2006.169.07:42:17.36#ibcon#end of sib2, iclass 26, count 2 2006.169.07:42:17.36#ibcon#*mode == 0, iclass 26, count 2 2006.169.07:42:17.36#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.169.07:42:17.36#ibcon#[25=AT08-07\r\n] 2006.169.07:42:17.36#ibcon#*before write, iclass 26, count 2 2006.169.07:42:17.36#ibcon#enter sib2, iclass 26, count 2 2006.169.07:42:17.36#ibcon#flushed, iclass 26, count 2 2006.169.07:42:17.36#ibcon#about to write, iclass 26, count 2 2006.169.07:42:17.36#ibcon#wrote, iclass 26, count 2 2006.169.07:42:17.36#ibcon#about to read 3, iclass 26, count 2 2006.169.07:42:17.38#ibcon#read 3, iclass 26, count 2 2006.169.07:42:17.38#ibcon#about to read 4, iclass 26, count 2 2006.169.07:42:17.38#ibcon#read 4, iclass 26, count 2 2006.169.07:42:17.38#ibcon#about to read 5, iclass 26, count 2 2006.169.07:42:17.38#ibcon#read 5, iclass 26, count 2 2006.169.07:42:17.38#ibcon#about to read 6, iclass 26, count 2 2006.169.07:42:17.38#ibcon#read 6, iclass 26, count 2 2006.169.07:42:17.38#ibcon#end of sib2, iclass 26, count 2 2006.169.07:42:17.38#ibcon#*after write, iclass 26, count 2 2006.169.07:42:17.38#ibcon#*before return 0, iclass 26, count 2 2006.169.07:42:17.38#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.169.07:42:17.38#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.169.07:42:17.38#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.169.07:42:17.38#ibcon#ireg 7 cls_cnt 0 2006.169.07:42:17.38#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.169.07:42:17.50#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.169.07:42:17.50#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.169.07:42:17.50#ibcon#enter wrdev, iclass 26, count 0 2006.169.07:42:17.50#ibcon#first serial, iclass 26, count 0 2006.169.07:42:17.50#ibcon#enter sib2, iclass 26, count 0 2006.169.07:42:17.50#ibcon#flushed, iclass 26, count 0 2006.169.07:42:17.50#ibcon#about to write, iclass 26, count 0 2006.169.07:42:17.50#ibcon#wrote, iclass 26, count 0 2006.169.07:42:17.50#ibcon#about to read 3, iclass 26, count 0 2006.169.07:42:17.52#ibcon#read 3, iclass 26, count 0 2006.169.07:42:17.52#ibcon#about to read 4, iclass 26, count 0 2006.169.07:42:17.52#ibcon#read 4, iclass 26, count 0 2006.169.07:42:17.52#ibcon#about to read 5, iclass 26, count 0 2006.169.07:42:17.52#ibcon#read 5, iclass 26, count 0 2006.169.07:42:17.52#ibcon#about to read 6, iclass 26, count 0 2006.169.07:42:17.52#ibcon#read 6, iclass 26, count 0 2006.169.07:42:17.52#ibcon#end of sib2, iclass 26, count 0 2006.169.07:42:17.52#ibcon#*mode == 0, iclass 26, count 0 2006.169.07:42:17.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.169.07:42:17.52#ibcon#[25=USB\r\n] 2006.169.07:42:17.52#ibcon#*before write, iclass 26, count 0 2006.169.07:42:17.52#ibcon#enter sib2, iclass 26, count 0 2006.169.07:42:17.52#ibcon#flushed, iclass 26, count 0 2006.169.07:42:17.52#ibcon#about to write, iclass 26, count 0 2006.169.07:42:17.52#ibcon#wrote, iclass 26, count 0 2006.169.07:42:17.52#ibcon#about to read 3, iclass 26, count 0 2006.169.07:42:17.55#ibcon#read 3, iclass 26, count 0 2006.169.07:42:17.55#ibcon#about to read 4, iclass 26, count 0 2006.169.07:42:17.55#ibcon#read 4, iclass 26, count 0 2006.169.07:42:17.55#ibcon#about to read 5, iclass 26, count 0 2006.169.07:42:17.55#ibcon#read 5, iclass 26, count 0 2006.169.07:42:17.55#ibcon#about to read 6, iclass 26, count 0 2006.169.07:42:17.55#ibcon#read 6, iclass 26, count 0 2006.169.07:42:17.55#ibcon#end of sib2, iclass 26, count 0 2006.169.07:42:17.55#ibcon#*after write, iclass 26, count 0 2006.169.07:42:17.55#ibcon#*before return 0, iclass 26, count 0 2006.169.07:42:17.55#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.169.07:42:17.55#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.169.07:42:17.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.169.07:42:17.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.169.07:42:17.55$vc4f8/vblo=1,632.99 2006.169.07:42:17.55#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.169.07:42:17.55#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.169.07:42:17.55#ibcon#ireg 17 cls_cnt 0 2006.169.07:42:17.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:42:17.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:42:17.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:42:17.55#ibcon#enter wrdev, iclass 28, count 0 2006.169.07:42:17.55#ibcon#first serial, iclass 28, count 0 2006.169.07:42:17.55#ibcon#enter sib2, iclass 28, count 0 2006.169.07:42:17.55#ibcon#flushed, iclass 28, count 0 2006.169.07:42:17.55#ibcon#about to write, iclass 28, count 0 2006.169.07:42:17.55#ibcon#wrote, iclass 28, count 0 2006.169.07:42:17.55#ibcon#about to read 3, iclass 28, count 0 2006.169.07:42:17.57#ibcon#read 3, iclass 28, count 0 2006.169.07:42:17.57#ibcon#about to read 4, iclass 28, count 0 2006.169.07:42:17.57#ibcon#read 4, iclass 28, count 0 2006.169.07:42:17.57#ibcon#about to read 5, iclass 28, count 0 2006.169.07:42:17.57#ibcon#read 5, iclass 28, count 0 2006.169.07:42:17.57#ibcon#about to read 6, iclass 28, count 0 2006.169.07:42:17.57#ibcon#read 6, iclass 28, count 0 2006.169.07:42:17.57#ibcon#end of sib2, iclass 28, count 0 2006.169.07:42:17.57#ibcon#*mode == 0, iclass 28, count 0 2006.169.07:42:17.57#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.169.07:42:17.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.07:42:17.57#ibcon#*before write, iclass 28, count 0 2006.169.07:42:17.57#ibcon#enter sib2, iclass 28, count 0 2006.169.07:42:17.57#ibcon#flushed, iclass 28, count 0 2006.169.07:42:17.57#ibcon#about to write, iclass 28, count 0 2006.169.07:42:17.57#ibcon#wrote, iclass 28, count 0 2006.169.07:42:17.57#ibcon#about to read 3, iclass 28, count 0 2006.169.07:42:17.61#ibcon#read 3, iclass 28, count 0 2006.169.07:42:17.61#ibcon#about to read 4, iclass 28, count 0 2006.169.07:42:17.61#ibcon#read 4, iclass 28, count 0 2006.169.07:42:17.61#ibcon#about to read 5, iclass 28, count 0 2006.169.07:42:17.61#ibcon#read 5, iclass 28, count 0 2006.169.07:42:17.61#ibcon#about to read 6, iclass 28, count 0 2006.169.07:42:17.61#ibcon#read 6, iclass 28, count 0 2006.169.07:42:17.61#ibcon#end of sib2, iclass 28, count 0 2006.169.07:42:17.61#ibcon#*after write, iclass 28, count 0 2006.169.07:42:17.61#ibcon#*before return 0, iclass 28, count 0 2006.169.07:42:17.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:42:17.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:42:17.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.169.07:42:17.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.169.07:42:17.61$vc4f8/vb=1,4 2006.169.07:42:17.61#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.169.07:42:17.61#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.169.07:42:17.61#ibcon#ireg 11 cls_cnt 2 2006.169.07:42:17.61#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:42:17.61#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:42:17.61#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:42:17.61#ibcon#enter wrdev, iclass 30, count 2 2006.169.07:42:17.61#ibcon#first serial, iclass 30, count 2 2006.169.07:42:17.61#ibcon#enter sib2, iclass 30, count 2 2006.169.07:42:17.61#ibcon#flushed, iclass 30, count 2 2006.169.07:42:17.61#ibcon#about to write, iclass 30, count 2 2006.169.07:42:17.61#ibcon#wrote, iclass 30, count 2 2006.169.07:42:17.61#ibcon#about to read 3, iclass 30, count 2 2006.169.07:42:17.63#ibcon#read 3, iclass 30, count 2 2006.169.07:42:17.63#ibcon#about to read 4, iclass 30, count 2 2006.169.07:42:17.63#ibcon#read 4, iclass 30, count 2 2006.169.07:42:17.63#ibcon#about to read 5, iclass 30, count 2 2006.169.07:42:17.63#ibcon#read 5, iclass 30, count 2 2006.169.07:42:17.63#ibcon#about to read 6, iclass 30, count 2 2006.169.07:42:17.63#ibcon#read 6, iclass 30, count 2 2006.169.07:42:17.63#ibcon#end of sib2, iclass 30, count 2 2006.169.07:42:17.63#ibcon#*mode == 0, iclass 30, count 2 2006.169.07:42:17.63#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.169.07:42:17.63#ibcon#[27=AT01-04\r\n] 2006.169.07:42:17.63#ibcon#*before write, iclass 30, count 2 2006.169.07:42:17.63#ibcon#enter sib2, iclass 30, count 2 2006.169.07:42:17.63#ibcon#flushed, iclass 30, count 2 2006.169.07:42:17.63#ibcon#about to write, iclass 30, count 2 2006.169.07:42:17.63#ibcon#wrote, iclass 30, count 2 2006.169.07:42:17.63#ibcon#about to read 3, iclass 30, count 2 2006.169.07:42:17.66#ibcon#read 3, iclass 30, count 2 2006.169.07:42:17.66#ibcon#about to read 4, iclass 30, count 2 2006.169.07:42:17.66#ibcon#read 4, iclass 30, count 2 2006.169.07:42:17.66#ibcon#about to read 5, iclass 30, count 2 2006.169.07:42:17.66#ibcon#read 5, iclass 30, count 2 2006.169.07:42:17.66#ibcon#about to read 6, iclass 30, count 2 2006.169.07:42:17.66#ibcon#read 6, iclass 30, count 2 2006.169.07:42:17.66#ibcon#end of sib2, iclass 30, count 2 2006.169.07:42:17.66#ibcon#*after write, iclass 30, count 2 2006.169.07:42:17.66#ibcon#*before return 0, iclass 30, count 2 2006.169.07:42:17.66#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:42:17.66#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:42:17.66#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.169.07:42:17.66#ibcon#ireg 7 cls_cnt 0 2006.169.07:42:17.66#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:42:17.78#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:42:17.78#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:42:17.78#ibcon#enter wrdev, iclass 30, count 0 2006.169.07:42:17.78#ibcon#first serial, iclass 30, count 0 2006.169.07:42:17.78#ibcon#enter sib2, iclass 30, count 0 2006.169.07:42:17.78#ibcon#flushed, iclass 30, count 0 2006.169.07:42:17.78#ibcon#about to write, iclass 30, count 0 2006.169.07:42:17.78#ibcon#wrote, iclass 30, count 0 2006.169.07:42:17.78#ibcon#about to read 3, iclass 30, count 0 2006.169.07:42:17.80#ibcon#read 3, iclass 30, count 0 2006.169.07:42:17.80#ibcon#about to read 4, iclass 30, count 0 2006.169.07:42:17.80#ibcon#read 4, iclass 30, count 0 2006.169.07:42:17.80#ibcon#about to read 5, iclass 30, count 0 2006.169.07:42:17.80#ibcon#read 5, iclass 30, count 0 2006.169.07:42:17.80#ibcon#about to read 6, iclass 30, count 0 2006.169.07:42:17.80#ibcon#read 6, iclass 30, count 0 2006.169.07:42:17.80#ibcon#end of sib2, iclass 30, count 0 2006.169.07:42:17.80#ibcon#*mode == 0, iclass 30, count 0 2006.169.07:42:17.80#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.169.07:42:17.80#ibcon#[27=USB\r\n] 2006.169.07:42:17.80#ibcon#*before write, iclass 30, count 0 2006.169.07:42:17.80#ibcon#enter sib2, iclass 30, count 0 2006.169.07:42:17.80#ibcon#flushed, iclass 30, count 0 2006.169.07:42:17.80#ibcon#about to write, iclass 30, count 0 2006.169.07:42:17.80#ibcon#wrote, iclass 30, count 0 2006.169.07:42:17.80#ibcon#about to read 3, iclass 30, count 0 2006.169.07:42:17.83#ibcon#read 3, iclass 30, count 0 2006.169.07:42:17.83#ibcon#about to read 4, iclass 30, count 0 2006.169.07:42:17.83#ibcon#read 4, iclass 30, count 0 2006.169.07:42:17.83#ibcon#about to read 5, iclass 30, count 0 2006.169.07:42:17.83#ibcon#read 5, iclass 30, count 0 2006.169.07:42:17.83#ibcon#about to read 6, iclass 30, count 0 2006.169.07:42:17.83#ibcon#read 6, iclass 30, count 0 2006.169.07:42:17.83#ibcon#end of sib2, iclass 30, count 0 2006.169.07:42:17.83#ibcon#*after write, iclass 30, count 0 2006.169.07:42:17.83#ibcon#*before return 0, iclass 30, count 0 2006.169.07:42:17.83#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:42:17.83#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:42:17.83#ibcon#about to clear, iclass 30 cls_cnt 0 2006.169.07:42:17.83#ibcon#cleared, iclass 30 cls_cnt 0 2006.169.07:42:17.83$vc4f8/vblo=2,640.99 2006.169.07:42:17.83#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.169.07:42:17.83#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.169.07:42:17.83#ibcon#ireg 17 cls_cnt 0 2006.169.07:42:17.83#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:42:17.83#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:42:17.83#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:42:17.83#ibcon#enter wrdev, iclass 32, count 0 2006.169.07:42:17.83#ibcon#first serial, iclass 32, count 0 2006.169.07:42:17.83#ibcon#enter sib2, iclass 32, count 0 2006.169.07:42:17.83#ibcon#flushed, iclass 32, count 0 2006.169.07:42:17.83#ibcon#about to write, iclass 32, count 0 2006.169.07:42:17.83#ibcon#wrote, iclass 32, count 0 2006.169.07:42:17.83#ibcon#about to read 3, iclass 32, count 0 2006.169.07:42:17.85#ibcon#read 3, iclass 32, count 0 2006.169.07:42:17.85#ibcon#about to read 4, iclass 32, count 0 2006.169.07:42:17.85#ibcon#read 4, iclass 32, count 0 2006.169.07:42:17.85#ibcon#about to read 5, iclass 32, count 0 2006.169.07:42:17.85#ibcon#read 5, iclass 32, count 0 2006.169.07:42:17.85#ibcon#about to read 6, iclass 32, count 0 2006.169.07:42:17.85#ibcon#read 6, iclass 32, count 0 2006.169.07:42:17.85#ibcon#end of sib2, iclass 32, count 0 2006.169.07:42:17.85#ibcon#*mode == 0, iclass 32, count 0 2006.169.07:42:17.85#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.169.07:42:17.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.07:42:17.85#ibcon#*before write, iclass 32, count 0 2006.169.07:42:17.85#ibcon#enter sib2, iclass 32, count 0 2006.169.07:42:17.85#ibcon#flushed, iclass 32, count 0 2006.169.07:42:17.85#ibcon#about to write, iclass 32, count 0 2006.169.07:42:17.85#ibcon#wrote, iclass 32, count 0 2006.169.07:42:17.85#ibcon#about to read 3, iclass 32, count 0 2006.169.07:42:17.89#ibcon#read 3, iclass 32, count 0 2006.169.07:42:17.89#ibcon#about to read 4, iclass 32, count 0 2006.169.07:42:17.89#ibcon#read 4, iclass 32, count 0 2006.169.07:42:17.89#ibcon#about to read 5, iclass 32, count 0 2006.169.07:42:17.89#ibcon#read 5, iclass 32, count 0 2006.169.07:42:17.89#ibcon#about to read 6, iclass 32, count 0 2006.169.07:42:17.89#ibcon#read 6, iclass 32, count 0 2006.169.07:42:17.89#ibcon#end of sib2, iclass 32, count 0 2006.169.07:42:17.89#ibcon#*after write, iclass 32, count 0 2006.169.07:42:17.89#ibcon#*before return 0, iclass 32, count 0 2006.169.07:42:17.89#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:42:17.89#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:42:17.89#ibcon#about to clear, iclass 32 cls_cnt 0 2006.169.07:42:17.89#ibcon#cleared, iclass 32 cls_cnt 0 2006.169.07:42:17.89$vc4f8/vb=2,4 2006.169.07:42:17.89#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.169.07:42:17.89#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.169.07:42:17.89#ibcon#ireg 11 cls_cnt 2 2006.169.07:42:17.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.169.07:42:17.95#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.169.07:42:17.95#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.169.07:42:17.95#ibcon#enter wrdev, iclass 34, count 2 2006.169.07:42:17.95#ibcon#first serial, iclass 34, count 2 2006.169.07:42:17.95#ibcon#enter sib2, iclass 34, count 2 2006.169.07:42:17.95#ibcon#flushed, iclass 34, count 2 2006.169.07:42:17.95#ibcon#about to write, iclass 34, count 2 2006.169.07:42:17.95#ibcon#wrote, iclass 34, count 2 2006.169.07:42:17.95#ibcon#about to read 3, iclass 34, count 2 2006.169.07:42:17.97#ibcon#read 3, iclass 34, count 2 2006.169.07:42:17.97#ibcon#about to read 4, iclass 34, count 2 2006.169.07:42:17.97#ibcon#read 4, iclass 34, count 2 2006.169.07:42:17.97#ibcon#about to read 5, iclass 34, count 2 2006.169.07:42:17.97#ibcon#read 5, iclass 34, count 2 2006.169.07:42:17.97#ibcon#about to read 6, iclass 34, count 2 2006.169.07:42:17.97#ibcon#read 6, iclass 34, count 2 2006.169.07:42:17.97#ibcon#end of sib2, iclass 34, count 2 2006.169.07:42:17.97#ibcon#*mode == 0, iclass 34, count 2 2006.169.07:42:17.97#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.169.07:42:17.97#ibcon#[27=AT02-04\r\n] 2006.169.07:42:17.97#ibcon#*before write, iclass 34, count 2 2006.169.07:42:17.97#ibcon#enter sib2, iclass 34, count 2 2006.169.07:42:17.97#ibcon#flushed, iclass 34, count 2 2006.169.07:42:17.97#ibcon#about to write, iclass 34, count 2 2006.169.07:42:17.97#ibcon#wrote, iclass 34, count 2 2006.169.07:42:17.97#ibcon#about to read 3, iclass 34, count 2 2006.169.07:42:18.00#ibcon#read 3, iclass 34, count 2 2006.169.07:42:18.00#ibcon#about to read 4, iclass 34, count 2 2006.169.07:42:18.00#ibcon#read 4, iclass 34, count 2 2006.169.07:42:18.00#ibcon#about to read 5, iclass 34, count 2 2006.169.07:42:18.00#ibcon#read 5, iclass 34, count 2 2006.169.07:42:18.00#ibcon#about to read 6, iclass 34, count 2 2006.169.07:42:18.00#ibcon#read 6, iclass 34, count 2 2006.169.07:42:18.00#ibcon#end of sib2, iclass 34, count 2 2006.169.07:42:18.00#ibcon#*after write, iclass 34, count 2 2006.169.07:42:18.00#ibcon#*before return 0, iclass 34, count 2 2006.169.07:42:18.00#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.169.07:42:18.00#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.169.07:42:18.00#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.169.07:42:18.00#ibcon#ireg 7 cls_cnt 0 2006.169.07:42:18.00#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.169.07:42:18.12#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.169.07:42:18.12#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.169.07:42:18.12#ibcon#enter wrdev, iclass 34, count 0 2006.169.07:42:18.12#ibcon#first serial, iclass 34, count 0 2006.169.07:42:18.12#ibcon#enter sib2, iclass 34, count 0 2006.169.07:42:18.12#ibcon#flushed, iclass 34, count 0 2006.169.07:42:18.12#ibcon#about to write, iclass 34, count 0 2006.169.07:42:18.12#ibcon#wrote, iclass 34, count 0 2006.169.07:42:18.12#ibcon#about to read 3, iclass 34, count 0 2006.169.07:42:18.14#ibcon#read 3, iclass 34, count 0 2006.169.07:42:18.14#ibcon#about to read 4, iclass 34, count 0 2006.169.07:42:18.14#ibcon#read 4, iclass 34, count 0 2006.169.07:42:18.14#ibcon#about to read 5, iclass 34, count 0 2006.169.07:42:18.14#ibcon#read 5, iclass 34, count 0 2006.169.07:42:18.14#ibcon#about to read 6, iclass 34, count 0 2006.169.07:42:18.14#ibcon#read 6, iclass 34, count 0 2006.169.07:42:18.14#ibcon#end of sib2, iclass 34, count 0 2006.169.07:42:18.14#ibcon#*mode == 0, iclass 34, count 0 2006.169.07:42:18.14#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.169.07:42:18.14#ibcon#[27=USB\r\n] 2006.169.07:42:18.14#ibcon#*before write, iclass 34, count 0 2006.169.07:42:18.14#ibcon#enter sib2, iclass 34, count 0 2006.169.07:42:18.14#ibcon#flushed, iclass 34, count 0 2006.169.07:42:18.14#ibcon#about to write, iclass 34, count 0 2006.169.07:42:18.14#ibcon#wrote, iclass 34, count 0 2006.169.07:42:18.14#ibcon#about to read 3, iclass 34, count 0 2006.169.07:42:18.17#ibcon#read 3, iclass 34, count 0 2006.169.07:42:18.17#ibcon#about to read 4, iclass 34, count 0 2006.169.07:42:18.17#ibcon#read 4, iclass 34, count 0 2006.169.07:42:18.17#ibcon#about to read 5, iclass 34, count 0 2006.169.07:42:18.17#ibcon#read 5, iclass 34, count 0 2006.169.07:42:18.17#ibcon#about to read 6, iclass 34, count 0 2006.169.07:42:18.17#ibcon#read 6, iclass 34, count 0 2006.169.07:42:18.17#ibcon#end of sib2, iclass 34, count 0 2006.169.07:42:18.17#ibcon#*after write, iclass 34, count 0 2006.169.07:42:18.17#ibcon#*before return 0, iclass 34, count 0 2006.169.07:42:18.17#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.169.07:42:18.17#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.169.07:42:18.17#ibcon#about to clear, iclass 34 cls_cnt 0 2006.169.07:42:18.17#ibcon#cleared, iclass 34 cls_cnt 0 2006.169.07:42:18.17$vc4f8/vblo=3,656.99 2006.169.07:42:18.17#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.169.07:42:18.17#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.169.07:42:18.17#ibcon#ireg 17 cls_cnt 0 2006.169.07:42:18.17#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.169.07:42:18.17#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.169.07:42:18.17#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.169.07:42:18.17#ibcon#enter wrdev, iclass 36, count 0 2006.169.07:42:18.17#ibcon#first serial, iclass 36, count 0 2006.169.07:42:18.17#ibcon#enter sib2, iclass 36, count 0 2006.169.07:42:18.17#ibcon#flushed, iclass 36, count 0 2006.169.07:42:18.17#ibcon#about to write, iclass 36, count 0 2006.169.07:42:18.17#ibcon#wrote, iclass 36, count 0 2006.169.07:42:18.17#ibcon#about to read 3, iclass 36, count 0 2006.169.07:42:18.20#ibcon#read 3, iclass 36, count 0 2006.169.07:42:18.20#ibcon#about to read 4, iclass 36, count 0 2006.169.07:42:18.20#ibcon#read 4, iclass 36, count 0 2006.169.07:42:18.20#ibcon#about to read 5, iclass 36, count 0 2006.169.07:42:18.20#ibcon#read 5, iclass 36, count 0 2006.169.07:42:18.20#ibcon#about to read 6, iclass 36, count 0 2006.169.07:42:18.20#ibcon#read 6, iclass 36, count 0 2006.169.07:42:18.20#ibcon#end of sib2, iclass 36, count 0 2006.169.07:42:18.20#ibcon#*mode == 0, iclass 36, count 0 2006.169.07:42:18.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.169.07:42:18.20#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.07:42:18.20#ibcon#*before write, iclass 36, count 0 2006.169.07:42:18.20#ibcon#enter sib2, iclass 36, count 0 2006.169.07:42:18.20#ibcon#flushed, iclass 36, count 0 2006.169.07:42:18.20#ibcon#about to write, iclass 36, count 0 2006.169.07:42:18.20#ibcon#wrote, iclass 36, count 0 2006.169.07:42:18.20#ibcon#about to read 3, iclass 36, count 0 2006.169.07:42:18.24#ibcon#read 3, iclass 36, count 0 2006.169.07:42:18.24#ibcon#about to read 4, iclass 36, count 0 2006.169.07:42:18.24#ibcon#read 4, iclass 36, count 0 2006.169.07:42:18.24#ibcon#about to read 5, iclass 36, count 0 2006.169.07:42:18.24#ibcon#read 5, iclass 36, count 0 2006.169.07:42:18.24#ibcon#about to read 6, iclass 36, count 0 2006.169.07:42:18.24#ibcon#read 6, iclass 36, count 0 2006.169.07:42:18.24#ibcon#end of sib2, iclass 36, count 0 2006.169.07:42:18.24#ibcon#*after write, iclass 36, count 0 2006.169.07:42:18.24#ibcon#*before return 0, iclass 36, count 0 2006.169.07:42:18.24#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.169.07:42:18.24#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.169.07:42:18.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.169.07:42:18.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.169.07:42:18.24$vc4f8/vb=3,4 2006.169.07:42:18.24#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.169.07:42:18.24#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.169.07:42:18.24#ibcon#ireg 11 cls_cnt 2 2006.169.07:42:18.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.169.07:42:18.29#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.169.07:42:18.29#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.169.07:42:18.29#ibcon#enter wrdev, iclass 38, count 2 2006.169.07:42:18.29#ibcon#first serial, iclass 38, count 2 2006.169.07:42:18.29#ibcon#enter sib2, iclass 38, count 2 2006.169.07:42:18.29#ibcon#flushed, iclass 38, count 2 2006.169.07:42:18.29#ibcon#about to write, iclass 38, count 2 2006.169.07:42:18.29#ibcon#wrote, iclass 38, count 2 2006.169.07:42:18.29#ibcon#about to read 3, iclass 38, count 2 2006.169.07:42:18.31#ibcon#read 3, iclass 38, count 2 2006.169.07:42:18.31#ibcon#about to read 4, iclass 38, count 2 2006.169.07:42:18.31#ibcon#read 4, iclass 38, count 2 2006.169.07:42:18.31#ibcon#about to read 5, iclass 38, count 2 2006.169.07:42:18.31#ibcon#read 5, iclass 38, count 2 2006.169.07:42:18.31#ibcon#about to read 6, iclass 38, count 2 2006.169.07:42:18.31#ibcon#read 6, iclass 38, count 2 2006.169.07:42:18.31#ibcon#end of sib2, iclass 38, count 2 2006.169.07:42:18.31#ibcon#*mode == 0, iclass 38, count 2 2006.169.07:42:18.31#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.169.07:42:18.31#ibcon#[27=AT03-04\r\n] 2006.169.07:42:18.31#ibcon#*before write, iclass 38, count 2 2006.169.07:42:18.31#ibcon#enter sib2, iclass 38, count 2 2006.169.07:42:18.31#ibcon#flushed, iclass 38, count 2 2006.169.07:42:18.31#ibcon#about to write, iclass 38, count 2 2006.169.07:42:18.31#ibcon#wrote, iclass 38, count 2 2006.169.07:42:18.31#ibcon#about to read 3, iclass 38, count 2 2006.169.07:42:18.34#ibcon#read 3, iclass 38, count 2 2006.169.07:42:18.34#ibcon#about to read 4, iclass 38, count 2 2006.169.07:42:18.34#ibcon#read 4, iclass 38, count 2 2006.169.07:42:18.34#ibcon#about to read 5, iclass 38, count 2 2006.169.07:42:18.34#ibcon#read 5, iclass 38, count 2 2006.169.07:42:18.34#ibcon#about to read 6, iclass 38, count 2 2006.169.07:42:18.34#ibcon#read 6, iclass 38, count 2 2006.169.07:42:18.34#ibcon#end of sib2, iclass 38, count 2 2006.169.07:42:18.34#ibcon#*after write, iclass 38, count 2 2006.169.07:42:18.34#ibcon#*before return 0, iclass 38, count 2 2006.169.07:42:18.34#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.169.07:42:18.34#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.169.07:42:18.34#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.169.07:42:18.34#ibcon#ireg 7 cls_cnt 0 2006.169.07:42:18.34#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.169.07:42:18.46#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.169.07:42:18.46#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.169.07:42:18.46#ibcon#enter wrdev, iclass 38, count 0 2006.169.07:42:18.46#ibcon#first serial, iclass 38, count 0 2006.169.07:42:18.46#ibcon#enter sib2, iclass 38, count 0 2006.169.07:42:18.46#ibcon#flushed, iclass 38, count 0 2006.169.07:42:18.46#ibcon#about to write, iclass 38, count 0 2006.169.07:42:18.46#ibcon#wrote, iclass 38, count 0 2006.169.07:42:18.46#ibcon#about to read 3, iclass 38, count 0 2006.169.07:42:18.48#ibcon#read 3, iclass 38, count 0 2006.169.07:42:18.48#ibcon#about to read 4, iclass 38, count 0 2006.169.07:42:18.48#ibcon#read 4, iclass 38, count 0 2006.169.07:42:18.48#ibcon#about to read 5, iclass 38, count 0 2006.169.07:42:18.48#ibcon#read 5, iclass 38, count 0 2006.169.07:42:18.48#ibcon#about to read 6, iclass 38, count 0 2006.169.07:42:18.48#ibcon#read 6, iclass 38, count 0 2006.169.07:42:18.48#ibcon#end of sib2, iclass 38, count 0 2006.169.07:42:18.48#ibcon#*mode == 0, iclass 38, count 0 2006.169.07:42:18.48#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.169.07:42:18.48#ibcon#[27=USB\r\n] 2006.169.07:42:18.48#ibcon#*before write, iclass 38, count 0 2006.169.07:42:18.48#ibcon#enter sib2, iclass 38, count 0 2006.169.07:42:18.48#ibcon#flushed, iclass 38, count 0 2006.169.07:42:18.48#ibcon#about to write, iclass 38, count 0 2006.169.07:42:18.48#ibcon#wrote, iclass 38, count 0 2006.169.07:42:18.48#ibcon#about to read 3, iclass 38, count 0 2006.169.07:42:18.51#ibcon#read 3, iclass 38, count 0 2006.169.07:42:18.51#ibcon#about to read 4, iclass 38, count 0 2006.169.07:42:18.51#ibcon#read 4, iclass 38, count 0 2006.169.07:42:18.51#ibcon#about to read 5, iclass 38, count 0 2006.169.07:42:18.51#ibcon#read 5, iclass 38, count 0 2006.169.07:42:18.51#ibcon#about to read 6, iclass 38, count 0 2006.169.07:42:18.51#ibcon#read 6, iclass 38, count 0 2006.169.07:42:18.51#ibcon#end of sib2, iclass 38, count 0 2006.169.07:42:18.51#ibcon#*after write, iclass 38, count 0 2006.169.07:42:18.51#ibcon#*before return 0, iclass 38, count 0 2006.169.07:42:18.51#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.169.07:42:18.51#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.169.07:42:18.51#ibcon#about to clear, iclass 38 cls_cnt 0 2006.169.07:42:18.51#ibcon#cleared, iclass 38 cls_cnt 0 2006.169.07:42:18.51$vc4f8/vblo=4,712.99 2006.169.07:42:18.51#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.169.07:42:18.51#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.169.07:42:18.51#ibcon#ireg 17 cls_cnt 0 2006.169.07:42:18.51#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:42:18.51#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:42:18.51#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:42:18.51#ibcon#enter wrdev, iclass 40, count 0 2006.169.07:42:18.51#ibcon#first serial, iclass 40, count 0 2006.169.07:42:18.51#ibcon#enter sib2, iclass 40, count 0 2006.169.07:42:18.51#ibcon#flushed, iclass 40, count 0 2006.169.07:42:18.51#ibcon#about to write, iclass 40, count 0 2006.169.07:42:18.51#ibcon#wrote, iclass 40, count 0 2006.169.07:42:18.51#ibcon#about to read 3, iclass 40, count 0 2006.169.07:42:18.53#ibcon#read 3, iclass 40, count 0 2006.169.07:42:18.53#ibcon#about to read 4, iclass 40, count 0 2006.169.07:42:18.53#ibcon#read 4, iclass 40, count 0 2006.169.07:42:18.53#ibcon#about to read 5, iclass 40, count 0 2006.169.07:42:18.53#ibcon#read 5, iclass 40, count 0 2006.169.07:42:18.53#ibcon#about to read 6, iclass 40, count 0 2006.169.07:42:18.53#ibcon#read 6, iclass 40, count 0 2006.169.07:42:18.53#ibcon#end of sib2, iclass 40, count 0 2006.169.07:42:18.53#ibcon#*mode == 0, iclass 40, count 0 2006.169.07:42:18.53#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.169.07:42:18.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.07:42:18.53#ibcon#*before write, iclass 40, count 0 2006.169.07:42:18.53#ibcon#enter sib2, iclass 40, count 0 2006.169.07:42:18.53#ibcon#flushed, iclass 40, count 0 2006.169.07:42:18.53#ibcon#about to write, iclass 40, count 0 2006.169.07:42:18.53#ibcon#wrote, iclass 40, count 0 2006.169.07:42:18.53#ibcon#about to read 3, iclass 40, count 0 2006.169.07:42:18.57#ibcon#read 3, iclass 40, count 0 2006.169.07:42:18.57#ibcon#about to read 4, iclass 40, count 0 2006.169.07:42:18.57#ibcon#read 4, iclass 40, count 0 2006.169.07:42:18.57#ibcon#about to read 5, iclass 40, count 0 2006.169.07:42:18.57#ibcon#read 5, iclass 40, count 0 2006.169.07:42:18.57#ibcon#about to read 6, iclass 40, count 0 2006.169.07:42:18.57#ibcon#read 6, iclass 40, count 0 2006.169.07:42:18.57#ibcon#end of sib2, iclass 40, count 0 2006.169.07:42:18.57#ibcon#*after write, iclass 40, count 0 2006.169.07:42:18.57#ibcon#*before return 0, iclass 40, count 0 2006.169.07:42:18.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:42:18.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:42:18.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.169.07:42:18.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.169.07:42:18.57$vc4f8/vb=4,4 2006.169.07:42:18.57#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.169.07:42:18.57#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.169.07:42:18.57#ibcon#ireg 11 cls_cnt 2 2006.169.07:42:18.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.169.07:42:18.63#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.169.07:42:18.63#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.169.07:42:18.63#ibcon#enter wrdev, iclass 4, count 2 2006.169.07:42:18.63#ibcon#first serial, iclass 4, count 2 2006.169.07:42:18.63#ibcon#enter sib2, iclass 4, count 2 2006.169.07:42:18.63#ibcon#flushed, iclass 4, count 2 2006.169.07:42:18.63#ibcon#about to write, iclass 4, count 2 2006.169.07:42:18.63#ibcon#wrote, iclass 4, count 2 2006.169.07:42:18.63#ibcon#about to read 3, iclass 4, count 2 2006.169.07:42:18.65#ibcon#read 3, iclass 4, count 2 2006.169.07:42:18.65#ibcon#about to read 4, iclass 4, count 2 2006.169.07:42:18.65#ibcon#read 4, iclass 4, count 2 2006.169.07:42:18.65#ibcon#about to read 5, iclass 4, count 2 2006.169.07:42:18.65#ibcon#read 5, iclass 4, count 2 2006.169.07:42:18.65#ibcon#about to read 6, iclass 4, count 2 2006.169.07:42:18.65#ibcon#read 6, iclass 4, count 2 2006.169.07:42:18.65#ibcon#end of sib2, iclass 4, count 2 2006.169.07:42:18.65#ibcon#*mode == 0, iclass 4, count 2 2006.169.07:42:18.65#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.169.07:42:18.65#ibcon#[27=AT04-04\r\n] 2006.169.07:42:18.65#ibcon#*before write, iclass 4, count 2 2006.169.07:42:18.65#ibcon#enter sib2, iclass 4, count 2 2006.169.07:42:18.65#ibcon#flushed, iclass 4, count 2 2006.169.07:42:18.65#ibcon#about to write, iclass 4, count 2 2006.169.07:42:18.65#ibcon#wrote, iclass 4, count 2 2006.169.07:42:18.65#ibcon#about to read 3, iclass 4, count 2 2006.169.07:42:18.68#ibcon#read 3, iclass 4, count 2 2006.169.07:42:18.68#ibcon#about to read 4, iclass 4, count 2 2006.169.07:42:18.68#ibcon#read 4, iclass 4, count 2 2006.169.07:42:18.68#ibcon#about to read 5, iclass 4, count 2 2006.169.07:42:18.68#ibcon#read 5, iclass 4, count 2 2006.169.07:42:18.68#ibcon#about to read 6, iclass 4, count 2 2006.169.07:42:18.68#ibcon#read 6, iclass 4, count 2 2006.169.07:42:18.68#ibcon#end of sib2, iclass 4, count 2 2006.169.07:42:18.68#ibcon#*after write, iclass 4, count 2 2006.169.07:42:18.68#ibcon#*before return 0, iclass 4, count 2 2006.169.07:42:18.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.169.07:42:18.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.169.07:42:18.68#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.169.07:42:18.68#ibcon#ireg 7 cls_cnt 0 2006.169.07:42:18.68#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.169.07:42:18.80#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.169.07:42:18.80#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.169.07:42:18.80#ibcon#enter wrdev, iclass 4, count 0 2006.169.07:42:18.80#ibcon#first serial, iclass 4, count 0 2006.169.07:42:18.80#ibcon#enter sib2, iclass 4, count 0 2006.169.07:42:18.80#ibcon#flushed, iclass 4, count 0 2006.169.07:42:18.80#ibcon#about to write, iclass 4, count 0 2006.169.07:42:18.80#ibcon#wrote, iclass 4, count 0 2006.169.07:42:18.80#ibcon#about to read 3, iclass 4, count 0 2006.169.07:42:18.82#ibcon#read 3, iclass 4, count 0 2006.169.07:42:18.82#ibcon#about to read 4, iclass 4, count 0 2006.169.07:42:18.82#ibcon#read 4, iclass 4, count 0 2006.169.07:42:18.82#ibcon#about to read 5, iclass 4, count 0 2006.169.07:42:18.82#ibcon#read 5, iclass 4, count 0 2006.169.07:42:18.82#ibcon#about to read 6, iclass 4, count 0 2006.169.07:42:18.82#ibcon#read 6, iclass 4, count 0 2006.169.07:42:18.82#ibcon#end of sib2, iclass 4, count 0 2006.169.07:42:18.82#ibcon#*mode == 0, iclass 4, count 0 2006.169.07:42:18.82#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.169.07:42:18.82#ibcon#[27=USB\r\n] 2006.169.07:42:18.82#ibcon#*before write, iclass 4, count 0 2006.169.07:42:18.82#ibcon#enter sib2, iclass 4, count 0 2006.169.07:42:18.82#ibcon#flushed, iclass 4, count 0 2006.169.07:42:18.82#ibcon#about to write, iclass 4, count 0 2006.169.07:42:18.82#ibcon#wrote, iclass 4, count 0 2006.169.07:42:18.82#ibcon#about to read 3, iclass 4, count 0 2006.169.07:42:18.85#ibcon#read 3, iclass 4, count 0 2006.169.07:42:18.85#ibcon#about to read 4, iclass 4, count 0 2006.169.07:42:18.85#ibcon#read 4, iclass 4, count 0 2006.169.07:42:18.85#ibcon#about to read 5, iclass 4, count 0 2006.169.07:42:18.85#ibcon#read 5, iclass 4, count 0 2006.169.07:42:18.85#ibcon#about to read 6, iclass 4, count 0 2006.169.07:42:18.85#ibcon#read 6, iclass 4, count 0 2006.169.07:42:18.85#ibcon#end of sib2, iclass 4, count 0 2006.169.07:42:18.85#ibcon#*after write, iclass 4, count 0 2006.169.07:42:18.85#ibcon#*before return 0, iclass 4, count 0 2006.169.07:42:18.85#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.169.07:42:18.85#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.169.07:42:18.85#ibcon#about to clear, iclass 4 cls_cnt 0 2006.169.07:42:18.85#ibcon#cleared, iclass 4 cls_cnt 0 2006.169.07:42:18.85$vc4f8/vblo=5,744.99 2006.169.07:42:18.85#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.169.07:42:18.85#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.169.07:42:18.85#ibcon#ireg 17 cls_cnt 0 2006.169.07:42:18.85#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:42:18.85#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:42:18.85#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:42:18.85#ibcon#enter wrdev, iclass 6, count 0 2006.169.07:42:18.85#ibcon#first serial, iclass 6, count 0 2006.169.07:42:18.85#ibcon#enter sib2, iclass 6, count 0 2006.169.07:42:18.85#ibcon#flushed, iclass 6, count 0 2006.169.07:42:18.85#ibcon#about to write, iclass 6, count 0 2006.169.07:42:18.85#ibcon#wrote, iclass 6, count 0 2006.169.07:42:18.85#ibcon#about to read 3, iclass 6, count 0 2006.169.07:42:18.87#ibcon#read 3, iclass 6, count 0 2006.169.07:42:18.87#ibcon#about to read 4, iclass 6, count 0 2006.169.07:42:18.87#ibcon#read 4, iclass 6, count 0 2006.169.07:42:18.87#ibcon#about to read 5, iclass 6, count 0 2006.169.07:42:18.87#ibcon#read 5, iclass 6, count 0 2006.169.07:42:18.87#ibcon#about to read 6, iclass 6, count 0 2006.169.07:42:18.87#ibcon#read 6, iclass 6, count 0 2006.169.07:42:18.87#ibcon#end of sib2, iclass 6, count 0 2006.169.07:42:18.87#ibcon#*mode == 0, iclass 6, count 0 2006.169.07:42:18.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.169.07:42:18.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.07:42:18.87#ibcon#*before write, iclass 6, count 0 2006.169.07:42:18.87#ibcon#enter sib2, iclass 6, count 0 2006.169.07:42:18.87#ibcon#flushed, iclass 6, count 0 2006.169.07:42:18.87#ibcon#about to write, iclass 6, count 0 2006.169.07:42:18.87#ibcon#wrote, iclass 6, count 0 2006.169.07:42:18.87#ibcon#about to read 3, iclass 6, count 0 2006.169.07:42:18.91#ibcon#read 3, iclass 6, count 0 2006.169.07:42:18.91#ibcon#about to read 4, iclass 6, count 0 2006.169.07:42:18.91#ibcon#read 4, iclass 6, count 0 2006.169.07:42:18.91#ibcon#about to read 5, iclass 6, count 0 2006.169.07:42:18.91#ibcon#read 5, iclass 6, count 0 2006.169.07:42:18.91#ibcon#about to read 6, iclass 6, count 0 2006.169.07:42:18.91#ibcon#read 6, iclass 6, count 0 2006.169.07:42:18.91#ibcon#end of sib2, iclass 6, count 0 2006.169.07:42:18.91#ibcon#*after write, iclass 6, count 0 2006.169.07:42:18.91#ibcon#*before return 0, iclass 6, count 0 2006.169.07:42:18.91#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:42:18.91#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:42:18.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.169.07:42:18.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.169.07:42:18.91$vc4f8/vb=5,4 2006.169.07:42:18.91#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.169.07:42:18.91#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.169.07:42:18.91#ibcon#ireg 11 cls_cnt 2 2006.169.07:42:18.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.169.07:42:18.97#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.169.07:42:18.97#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.169.07:42:18.97#ibcon#enter wrdev, iclass 10, count 2 2006.169.07:42:18.97#ibcon#first serial, iclass 10, count 2 2006.169.07:42:18.97#ibcon#enter sib2, iclass 10, count 2 2006.169.07:42:18.97#ibcon#flushed, iclass 10, count 2 2006.169.07:42:18.97#ibcon#about to write, iclass 10, count 2 2006.169.07:42:18.97#ibcon#wrote, iclass 10, count 2 2006.169.07:42:18.97#ibcon#about to read 3, iclass 10, count 2 2006.169.07:42:18.99#ibcon#read 3, iclass 10, count 2 2006.169.07:42:18.99#ibcon#about to read 4, iclass 10, count 2 2006.169.07:42:18.99#ibcon#read 4, iclass 10, count 2 2006.169.07:42:18.99#ibcon#about to read 5, iclass 10, count 2 2006.169.07:42:18.99#ibcon#read 5, iclass 10, count 2 2006.169.07:42:18.99#ibcon#about to read 6, iclass 10, count 2 2006.169.07:42:18.99#ibcon#read 6, iclass 10, count 2 2006.169.07:42:18.99#ibcon#end of sib2, iclass 10, count 2 2006.169.07:42:18.99#ibcon#*mode == 0, iclass 10, count 2 2006.169.07:42:18.99#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.169.07:42:18.99#ibcon#[27=AT05-04\r\n] 2006.169.07:42:18.99#ibcon#*before write, iclass 10, count 2 2006.169.07:42:18.99#ibcon#enter sib2, iclass 10, count 2 2006.169.07:42:18.99#ibcon#flushed, iclass 10, count 2 2006.169.07:42:18.99#ibcon#about to write, iclass 10, count 2 2006.169.07:42:18.99#ibcon#wrote, iclass 10, count 2 2006.169.07:42:18.99#ibcon#about to read 3, iclass 10, count 2 2006.169.07:42:19.02#ibcon#read 3, iclass 10, count 2 2006.169.07:42:19.02#ibcon#about to read 4, iclass 10, count 2 2006.169.07:42:19.02#ibcon#read 4, iclass 10, count 2 2006.169.07:42:19.02#ibcon#about to read 5, iclass 10, count 2 2006.169.07:42:19.02#ibcon#read 5, iclass 10, count 2 2006.169.07:42:19.02#ibcon#about to read 6, iclass 10, count 2 2006.169.07:42:19.02#ibcon#read 6, iclass 10, count 2 2006.169.07:42:19.02#ibcon#end of sib2, iclass 10, count 2 2006.169.07:42:19.02#ibcon#*after write, iclass 10, count 2 2006.169.07:42:19.02#ibcon#*before return 0, iclass 10, count 2 2006.169.07:42:19.02#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.169.07:42:19.02#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.169.07:42:19.02#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.169.07:42:19.02#ibcon#ireg 7 cls_cnt 0 2006.169.07:42:19.02#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.169.07:42:19.14#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.169.07:42:19.14#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.169.07:42:19.14#ibcon#enter wrdev, iclass 10, count 0 2006.169.07:42:19.14#ibcon#first serial, iclass 10, count 0 2006.169.07:42:19.14#ibcon#enter sib2, iclass 10, count 0 2006.169.07:42:19.14#ibcon#flushed, iclass 10, count 0 2006.169.07:42:19.14#ibcon#about to write, iclass 10, count 0 2006.169.07:42:19.14#ibcon#wrote, iclass 10, count 0 2006.169.07:42:19.14#ibcon#about to read 3, iclass 10, count 0 2006.169.07:42:19.16#ibcon#read 3, iclass 10, count 0 2006.169.07:42:19.16#ibcon#about to read 4, iclass 10, count 0 2006.169.07:42:19.16#ibcon#read 4, iclass 10, count 0 2006.169.07:42:19.16#ibcon#about to read 5, iclass 10, count 0 2006.169.07:42:19.16#ibcon#read 5, iclass 10, count 0 2006.169.07:42:19.16#ibcon#about to read 6, iclass 10, count 0 2006.169.07:42:19.16#ibcon#read 6, iclass 10, count 0 2006.169.07:42:19.16#ibcon#end of sib2, iclass 10, count 0 2006.169.07:42:19.16#ibcon#*mode == 0, iclass 10, count 0 2006.169.07:42:19.16#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.169.07:42:19.16#ibcon#[27=USB\r\n] 2006.169.07:42:19.16#ibcon#*before write, iclass 10, count 0 2006.169.07:42:19.16#ibcon#enter sib2, iclass 10, count 0 2006.169.07:42:19.16#ibcon#flushed, iclass 10, count 0 2006.169.07:42:19.16#ibcon#about to write, iclass 10, count 0 2006.169.07:42:19.16#ibcon#wrote, iclass 10, count 0 2006.169.07:42:19.16#ibcon#about to read 3, iclass 10, count 0 2006.169.07:42:19.19#ibcon#read 3, iclass 10, count 0 2006.169.07:42:19.19#ibcon#about to read 4, iclass 10, count 0 2006.169.07:42:19.19#ibcon#read 4, iclass 10, count 0 2006.169.07:42:19.19#ibcon#about to read 5, iclass 10, count 0 2006.169.07:42:19.19#ibcon#read 5, iclass 10, count 0 2006.169.07:42:19.19#ibcon#about to read 6, iclass 10, count 0 2006.169.07:42:19.19#ibcon#read 6, iclass 10, count 0 2006.169.07:42:19.19#ibcon#end of sib2, iclass 10, count 0 2006.169.07:42:19.19#ibcon#*after write, iclass 10, count 0 2006.169.07:42:19.19#ibcon#*before return 0, iclass 10, count 0 2006.169.07:42:19.19#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.169.07:42:19.19#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.169.07:42:19.19#ibcon#about to clear, iclass 10 cls_cnt 0 2006.169.07:42:19.19#ibcon#cleared, iclass 10 cls_cnt 0 2006.169.07:42:19.19$vc4f8/vblo=6,752.99 2006.169.07:42:19.19#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.169.07:42:19.19#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.169.07:42:19.19#ibcon#ireg 17 cls_cnt 0 2006.169.07:42:19.19#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.169.07:42:19.19#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.169.07:42:19.19#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.169.07:42:19.19#ibcon#enter wrdev, iclass 12, count 0 2006.169.07:42:19.19#ibcon#first serial, iclass 12, count 0 2006.169.07:42:19.19#ibcon#enter sib2, iclass 12, count 0 2006.169.07:42:19.19#ibcon#flushed, iclass 12, count 0 2006.169.07:42:19.19#ibcon#about to write, iclass 12, count 0 2006.169.07:42:19.19#ibcon#wrote, iclass 12, count 0 2006.169.07:42:19.19#ibcon#about to read 3, iclass 12, count 0 2006.169.07:42:19.21#ibcon#read 3, iclass 12, count 0 2006.169.07:42:19.21#ibcon#about to read 4, iclass 12, count 0 2006.169.07:42:19.21#ibcon#read 4, iclass 12, count 0 2006.169.07:42:19.21#ibcon#about to read 5, iclass 12, count 0 2006.169.07:42:19.21#ibcon#read 5, iclass 12, count 0 2006.169.07:42:19.21#ibcon#about to read 6, iclass 12, count 0 2006.169.07:42:19.21#ibcon#read 6, iclass 12, count 0 2006.169.07:42:19.21#ibcon#end of sib2, iclass 12, count 0 2006.169.07:42:19.21#ibcon#*mode == 0, iclass 12, count 0 2006.169.07:42:19.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.169.07:42:19.21#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.07:42:19.21#ibcon#*before write, iclass 12, count 0 2006.169.07:42:19.21#ibcon#enter sib2, iclass 12, count 0 2006.169.07:42:19.21#ibcon#flushed, iclass 12, count 0 2006.169.07:42:19.21#ibcon#about to write, iclass 12, count 0 2006.169.07:42:19.21#ibcon#wrote, iclass 12, count 0 2006.169.07:42:19.21#ibcon#about to read 3, iclass 12, count 0 2006.169.07:42:19.25#ibcon#read 3, iclass 12, count 0 2006.169.07:42:19.25#ibcon#about to read 4, iclass 12, count 0 2006.169.07:42:19.25#ibcon#read 4, iclass 12, count 0 2006.169.07:42:19.25#ibcon#about to read 5, iclass 12, count 0 2006.169.07:42:19.25#ibcon#read 5, iclass 12, count 0 2006.169.07:42:19.25#ibcon#about to read 6, iclass 12, count 0 2006.169.07:42:19.25#ibcon#read 6, iclass 12, count 0 2006.169.07:42:19.25#ibcon#end of sib2, iclass 12, count 0 2006.169.07:42:19.25#ibcon#*after write, iclass 12, count 0 2006.169.07:42:19.25#ibcon#*before return 0, iclass 12, count 0 2006.169.07:42:19.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.169.07:42:19.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.169.07:42:19.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.169.07:42:19.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.169.07:42:19.25$vc4f8/vb=6,4 2006.169.07:42:19.25#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.169.07:42:19.25#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.169.07:42:19.25#ibcon#ireg 11 cls_cnt 2 2006.169.07:42:19.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.169.07:42:19.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.169.07:42:19.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.169.07:42:19.31#ibcon#enter wrdev, iclass 14, count 2 2006.169.07:42:19.31#ibcon#first serial, iclass 14, count 2 2006.169.07:42:19.31#ibcon#enter sib2, iclass 14, count 2 2006.169.07:42:19.31#ibcon#flushed, iclass 14, count 2 2006.169.07:42:19.31#ibcon#about to write, iclass 14, count 2 2006.169.07:42:19.31#ibcon#wrote, iclass 14, count 2 2006.169.07:42:19.31#ibcon#about to read 3, iclass 14, count 2 2006.169.07:42:19.33#ibcon#read 3, iclass 14, count 2 2006.169.07:42:19.33#ibcon#about to read 4, iclass 14, count 2 2006.169.07:42:19.33#ibcon#read 4, iclass 14, count 2 2006.169.07:42:19.33#ibcon#about to read 5, iclass 14, count 2 2006.169.07:42:19.33#ibcon#read 5, iclass 14, count 2 2006.169.07:42:19.33#ibcon#about to read 6, iclass 14, count 2 2006.169.07:42:19.33#ibcon#read 6, iclass 14, count 2 2006.169.07:42:19.33#ibcon#end of sib2, iclass 14, count 2 2006.169.07:42:19.33#ibcon#*mode == 0, iclass 14, count 2 2006.169.07:42:19.33#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.169.07:42:19.33#ibcon#[27=AT06-04\r\n] 2006.169.07:42:19.33#ibcon#*before write, iclass 14, count 2 2006.169.07:42:19.33#ibcon#enter sib2, iclass 14, count 2 2006.169.07:42:19.33#ibcon#flushed, iclass 14, count 2 2006.169.07:42:19.33#ibcon#about to write, iclass 14, count 2 2006.169.07:42:19.33#ibcon#wrote, iclass 14, count 2 2006.169.07:42:19.33#ibcon#about to read 3, iclass 14, count 2 2006.169.07:42:19.36#ibcon#read 3, iclass 14, count 2 2006.169.07:42:19.36#ibcon#about to read 4, iclass 14, count 2 2006.169.07:42:19.36#ibcon#read 4, iclass 14, count 2 2006.169.07:42:19.36#ibcon#about to read 5, iclass 14, count 2 2006.169.07:42:19.36#ibcon#read 5, iclass 14, count 2 2006.169.07:42:19.36#ibcon#about to read 6, iclass 14, count 2 2006.169.07:42:19.36#ibcon#read 6, iclass 14, count 2 2006.169.07:42:19.36#ibcon#end of sib2, iclass 14, count 2 2006.169.07:42:19.36#ibcon#*after write, iclass 14, count 2 2006.169.07:42:19.36#ibcon#*before return 0, iclass 14, count 2 2006.169.07:42:19.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.169.07:42:19.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.169.07:42:19.36#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.169.07:42:19.36#ibcon#ireg 7 cls_cnt 0 2006.169.07:42:19.36#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.169.07:42:19.48#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.169.07:42:19.48#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.169.07:42:19.48#ibcon#enter wrdev, iclass 14, count 0 2006.169.07:42:19.48#ibcon#first serial, iclass 14, count 0 2006.169.07:42:19.48#ibcon#enter sib2, iclass 14, count 0 2006.169.07:42:19.48#ibcon#flushed, iclass 14, count 0 2006.169.07:42:19.48#ibcon#about to write, iclass 14, count 0 2006.169.07:42:19.48#ibcon#wrote, iclass 14, count 0 2006.169.07:42:19.48#ibcon#about to read 3, iclass 14, count 0 2006.169.07:42:19.50#ibcon#read 3, iclass 14, count 0 2006.169.07:42:19.50#ibcon#about to read 4, iclass 14, count 0 2006.169.07:42:19.50#ibcon#read 4, iclass 14, count 0 2006.169.07:42:19.50#ibcon#about to read 5, iclass 14, count 0 2006.169.07:42:19.50#ibcon#read 5, iclass 14, count 0 2006.169.07:42:19.50#ibcon#about to read 6, iclass 14, count 0 2006.169.07:42:19.50#ibcon#read 6, iclass 14, count 0 2006.169.07:42:19.50#ibcon#end of sib2, iclass 14, count 0 2006.169.07:42:19.50#ibcon#*mode == 0, iclass 14, count 0 2006.169.07:42:19.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.169.07:42:19.50#ibcon#[27=USB\r\n] 2006.169.07:42:19.50#ibcon#*before write, iclass 14, count 0 2006.169.07:42:19.50#ibcon#enter sib2, iclass 14, count 0 2006.169.07:42:19.50#ibcon#flushed, iclass 14, count 0 2006.169.07:42:19.50#ibcon#about to write, iclass 14, count 0 2006.169.07:42:19.50#ibcon#wrote, iclass 14, count 0 2006.169.07:42:19.50#ibcon#about to read 3, iclass 14, count 0 2006.169.07:42:19.53#ibcon#read 3, iclass 14, count 0 2006.169.07:42:19.53#ibcon#about to read 4, iclass 14, count 0 2006.169.07:42:19.53#ibcon#read 4, iclass 14, count 0 2006.169.07:42:19.53#ibcon#about to read 5, iclass 14, count 0 2006.169.07:42:19.53#ibcon#read 5, iclass 14, count 0 2006.169.07:42:19.53#ibcon#about to read 6, iclass 14, count 0 2006.169.07:42:19.53#ibcon#read 6, iclass 14, count 0 2006.169.07:42:19.53#ibcon#end of sib2, iclass 14, count 0 2006.169.07:42:19.53#ibcon#*after write, iclass 14, count 0 2006.169.07:42:19.53#ibcon#*before return 0, iclass 14, count 0 2006.169.07:42:19.53#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.169.07:42:19.53#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.169.07:42:19.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.169.07:42:19.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.169.07:42:19.53$vc4f8/vabw=wide 2006.169.07:42:19.53#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.169.07:42:19.53#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.169.07:42:19.53#ibcon#ireg 8 cls_cnt 0 2006.169.07:42:19.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:42:19.53#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:42:19.53#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:42:19.53#ibcon#enter wrdev, iclass 16, count 0 2006.169.07:42:19.53#ibcon#first serial, iclass 16, count 0 2006.169.07:42:19.53#ibcon#enter sib2, iclass 16, count 0 2006.169.07:42:19.53#ibcon#flushed, iclass 16, count 0 2006.169.07:42:19.53#ibcon#about to write, iclass 16, count 0 2006.169.07:42:19.53#ibcon#wrote, iclass 16, count 0 2006.169.07:42:19.53#ibcon#about to read 3, iclass 16, count 0 2006.169.07:42:19.55#ibcon#read 3, iclass 16, count 0 2006.169.07:42:19.55#ibcon#about to read 4, iclass 16, count 0 2006.169.07:42:19.55#ibcon#read 4, iclass 16, count 0 2006.169.07:42:19.55#ibcon#about to read 5, iclass 16, count 0 2006.169.07:42:19.55#ibcon#read 5, iclass 16, count 0 2006.169.07:42:19.55#ibcon#about to read 6, iclass 16, count 0 2006.169.07:42:19.55#ibcon#read 6, iclass 16, count 0 2006.169.07:42:19.55#ibcon#end of sib2, iclass 16, count 0 2006.169.07:42:19.55#ibcon#*mode == 0, iclass 16, count 0 2006.169.07:42:19.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.169.07:42:19.55#ibcon#[25=BW32\r\n] 2006.169.07:42:19.55#ibcon#*before write, iclass 16, count 0 2006.169.07:42:19.55#ibcon#enter sib2, iclass 16, count 0 2006.169.07:42:19.55#ibcon#flushed, iclass 16, count 0 2006.169.07:42:19.55#ibcon#about to write, iclass 16, count 0 2006.169.07:42:19.55#ibcon#wrote, iclass 16, count 0 2006.169.07:42:19.55#ibcon#about to read 3, iclass 16, count 0 2006.169.07:42:19.58#ibcon#read 3, iclass 16, count 0 2006.169.07:42:19.58#ibcon#about to read 4, iclass 16, count 0 2006.169.07:42:19.58#ibcon#read 4, iclass 16, count 0 2006.169.07:42:19.58#ibcon#about to read 5, iclass 16, count 0 2006.169.07:42:19.58#ibcon#read 5, iclass 16, count 0 2006.169.07:42:19.58#ibcon#about to read 6, iclass 16, count 0 2006.169.07:42:19.58#ibcon#read 6, iclass 16, count 0 2006.169.07:42:19.58#ibcon#end of sib2, iclass 16, count 0 2006.169.07:42:19.58#ibcon#*after write, iclass 16, count 0 2006.169.07:42:19.58#ibcon#*before return 0, iclass 16, count 0 2006.169.07:42:19.58#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:42:19.58#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:42:19.58#ibcon#about to clear, iclass 16 cls_cnt 0 2006.169.07:42:19.58#ibcon#cleared, iclass 16 cls_cnt 0 2006.169.07:42:19.58$vc4f8/vbbw=wide 2006.169.07:42:19.58#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.169.07:42:19.58#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.169.07:42:19.58#ibcon#ireg 8 cls_cnt 0 2006.169.07:42:19.58#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:42:19.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:42:19.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:42:19.65#ibcon#enter wrdev, iclass 18, count 0 2006.169.07:42:19.65#ibcon#first serial, iclass 18, count 0 2006.169.07:42:19.65#ibcon#enter sib2, iclass 18, count 0 2006.169.07:42:19.65#ibcon#flushed, iclass 18, count 0 2006.169.07:42:19.65#ibcon#about to write, iclass 18, count 0 2006.169.07:42:19.65#ibcon#wrote, iclass 18, count 0 2006.169.07:42:19.65#ibcon#about to read 3, iclass 18, count 0 2006.169.07:42:19.67#ibcon#read 3, iclass 18, count 0 2006.169.07:42:19.67#ibcon#about to read 4, iclass 18, count 0 2006.169.07:42:19.67#ibcon#read 4, iclass 18, count 0 2006.169.07:42:19.67#ibcon#about to read 5, iclass 18, count 0 2006.169.07:42:19.67#ibcon#read 5, iclass 18, count 0 2006.169.07:42:19.67#ibcon#about to read 6, iclass 18, count 0 2006.169.07:42:19.67#ibcon#read 6, iclass 18, count 0 2006.169.07:42:19.67#ibcon#end of sib2, iclass 18, count 0 2006.169.07:42:19.67#ibcon#*mode == 0, iclass 18, count 0 2006.169.07:42:19.67#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.169.07:42:19.67#ibcon#[27=BW32\r\n] 2006.169.07:42:19.67#ibcon#*before write, iclass 18, count 0 2006.169.07:42:19.67#ibcon#enter sib2, iclass 18, count 0 2006.169.07:42:19.67#ibcon#flushed, iclass 18, count 0 2006.169.07:42:19.67#ibcon#about to write, iclass 18, count 0 2006.169.07:42:19.67#ibcon#wrote, iclass 18, count 0 2006.169.07:42:19.67#ibcon#about to read 3, iclass 18, count 0 2006.169.07:42:19.70#ibcon#read 3, iclass 18, count 0 2006.169.07:42:19.70#ibcon#about to read 4, iclass 18, count 0 2006.169.07:42:19.70#ibcon#read 4, iclass 18, count 0 2006.169.07:42:19.70#ibcon#about to read 5, iclass 18, count 0 2006.169.07:42:19.70#ibcon#read 5, iclass 18, count 0 2006.169.07:42:19.70#ibcon#about to read 6, iclass 18, count 0 2006.169.07:42:19.70#ibcon#read 6, iclass 18, count 0 2006.169.07:42:19.70#ibcon#end of sib2, iclass 18, count 0 2006.169.07:42:19.70#ibcon#*after write, iclass 18, count 0 2006.169.07:42:19.70#ibcon#*before return 0, iclass 18, count 0 2006.169.07:42:19.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:42:19.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:42:19.70#ibcon#about to clear, iclass 18 cls_cnt 0 2006.169.07:42:19.70#ibcon#cleared, iclass 18 cls_cnt 0 2006.169.07:42:19.70$4f8m12a/ifd4f 2006.169.07:42:19.70$ifd4f/lo= 2006.169.07:42:19.70$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.07:42:19.70$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.07:42:19.70$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.07:42:19.71$ifd4f/patch= 2006.169.07:42:19.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.07:42:19.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.07:42:19.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.07:42:19.71$4f8m12a/"form=m,16.000,1:2 2006.169.07:42:19.71$4f8m12a/"tpicd 2006.169.07:42:19.71$4f8m12a/echo=off 2006.169.07:42:19.71$4f8m12a/xlog=off 2006.169.07:42:19.71:!2006.169.07:42:30 2006.169.07:42:30.01:preob 2006.169.07:42:31.14/onsource/TRACKING 2006.169.07:42:31.14:!2006.169.07:42:40 2006.169.07:42:40.00:data_valid=on 2006.169.07:42:40.00:midob 2006.169.07:42:40.14/onsource/TRACKING 2006.169.07:42:40.14/wx/18.13,1003.8,100 2006.169.07:42:40.20/cable/+6.5276E-03 2006.169.07:42:41.29/va/01,08,usb,yes,46,48 2006.169.07:42:41.29/va/02,07,usb,yes,47,48 2006.169.07:42:41.29/va/03,06,usb,yes,49,49 2006.169.07:42:41.29/va/04,07,usb,yes,48,51 2006.169.07:42:41.29/va/05,07,usb,yes,52,55 2006.169.07:42:41.29/va/06,06,usb,yes,52,51 2006.169.07:42:41.29/va/07,06,usb,yes,52,52 2006.169.07:42:41.29/va/08,07,usb,yes,49,49 2006.169.07:42:41.52/valo/01,532.99,yes,locked 2006.169.07:42:41.52/valo/02,572.99,yes,locked 2006.169.07:42:41.52/valo/03,672.99,yes,locked 2006.169.07:42:41.52/valo/04,832.99,yes,locked 2006.169.07:42:41.52/valo/05,652.99,yes,locked 2006.169.07:42:41.52/valo/06,772.99,yes,locked 2006.169.07:42:41.52/valo/07,832.99,yes,locked 2006.169.07:42:41.52/valo/08,852.99,yes,locked 2006.169.07:42:42.61/vb/01,04,usb,yes,30,28 2006.169.07:42:42.61/vb/02,04,usb,yes,32,33 2006.169.07:42:42.61/vb/03,04,usb,yes,28,32 2006.169.07:42:42.61/vb/04,04,usb,yes,29,29 2006.169.07:42:42.61/vb/05,04,usb,yes,28,31 2006.169.07:42:42.61/vb/06,04,usb,yes,29,31 2006.169.07:42:42.61/vb/07,04,usb,yes,31,30 2006.169.07:42:42.61/vb/08,04,usb,yes,28,31 2006.169.07:42:42.85/vblo/01,632.99,yes,locked 2006.169.07:42:42.85/vblo/02,640.99,yes,locked 2006.169.07:42:42.85/vblo/03,656.99,yes,locked 2006.169.07:42:42.85/vblo/04,712.99,yes,locked 2006.169.07:42:42.85/vblo/05,744.99,yes,locked 2006.169.07:42:42.85/vblo/06,752.99,yes,locked 2006.169.07:42:42.85/vblo/07,734.99,yes,locked 2006.169.07:42:42.85/vblo/08,744.99,yes,locked 2006.169.07:42:43.00/vabw/8 2006.169.07:42:43.15/vbbw/8 2006.169.07:42:43.24/xfe/off,on,15.5 2006.169.07:42:43.63/ifatt/23,28,28,28 2006.169.07:42:44.07/fmout-gps/S +4.17E-07 2006.169.07:42:44.15:!2006.169.07:43:40 2006.169.07:43:40.01:data_valid=off 2006.169.07:43:40.02:postob 2006.169.07:43:40.13/cable/+6.5265E-03 2006.169.07:43:40.14/wx/18.13,1003.8,100 2006.169.07:43:41.07/fmout-gps/S +4.17E-07 2006.169.07:43:41.08:scan_name=169-0744,k06169,60 2006.169.07:43:41.08:source=1418+546,141946.60,542314.8,2000.0,cw 2006.169.07:43:41.14#flagr#flagr/antenna,new-source 2006.169.07:43:42.14:checkk5 2006.169.07:43:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.169.07:43:42.90/chk_autoobs//k5ts2/ autoobs is running! 2006.169.07:43:46.92/chk_autoobs//k5ts3?ERROR: timeout happened! 2006.169.07:43:47.31/chk_autoobs//k5ts4/ autoobs is running! 2006.169.07:43:47.68/chk_obsdata//k5ts1/T1690742??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:43:48.05/chk_obsdata//k5ts2/T1690742??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:43:55.10/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.07:43:55.48/chk_obsdata//k5ts4/T1690742??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:43:56.17/k5log//k5ts1_log_newline 2006.169.07:43:56.86/k5log//k5ts2_log_newline 2006.169.07:44:02.14#trakl#Source acquired 2006.169.07:44:02.15#flagr#flagr/antenna,acquired 2006.169.07:44:03.95/k5log//k5ts3?ERROR: timeout happened! 2006.169.07:44:04.64/k5log//k5ts4_log_newline 2006.169.07:44:04.82/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.07:44:04.82:4f8m12a=1 2006.169.07:44:04.82$4f8m12a/echo=on 2006.169.07:44:04.82$4f8m12a/pcalon 2006.169.07:44:04.82$pcalon/"no phase cal control is implemented here 2006.169.07:44:04.82$4f8m12a/"tpicd=stop 2006.169.07:44:04.82$4f8m12a/vc4f8 2006.169.07:44:04.82$vc4f8/valo=1,532.99 2006.169.07:44:04.82#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.169.07:44:04.82#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.169.07:44:04.82#ibcon#ireg 17 cls_cnt 0 2006.169.07:44:04.82#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:44:04.82#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:44:04.82#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:44:04.82#ibcon#enter wrdev, iclass 25, count 0 2006.169.07:44:04.82#ibcon#first serial, iclass 25, count 0 2006.169.07:44:04.82#ibcon#enter sib2, iclass 25, count 0 2006.169.07:44:04.82#ibcon#flushed, iclass 25, count 0 2006.169.07:44:04.82#ibcon#about to write, iclass 25, count 0 2006.169.07:44:04.82#ibcon#wrote, iclass 25, count 0 2006.169.07:44:04.82#ibcon#about to read 3, iclass 25, count 0 2006.169.07:44:04.84#ibcon#read 3, iclass 25, count 0 2006.169.07:44:04.84#ibcon#about to read 4, iclass 25, count 0 2006.169.07:44:04.84#ibcon#read 4, iclass 25, count 0 2006.169.07:44:04.84#ibcon#about to read 5, iclass 25, count 0 2006.169.07:44:04.84#ibcon#read 5, iclass 25, count 0 2006.169.07:44:04.84#ibcon#about to read 6, iclass 25, count 0 2006.169.07:44:04.84#ibcon#read 6, iclass 25, count 0 2006.169.07:44:04.84#ibcon#end of sib2, iclass 25, count 0 2006.169.07:44:04.84#ibcon#*mode == 0, iclass 25, count 0 2006.169.07:44:04.84#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.169.07:44:04.84#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.07:44:04.84#ibcon#*before write, iclass 25, count 0 2006.169.07:44:04.84#ibcon#enter sib2, iclass 25, count 0 2006.169.07:44:04.84#ibcon#flushed, iclass 25, count 0 2006.169.07:44:04.84#ibcon#about to write, iclass 25, count 0 2006.169.07:44:04.84#ibcon#wrote, iclass 25, count 0 2006.169.07:44:04.84#ibcon#about to read 3, iclass 25, count 0 2006.169.07:44:04.89#ibcon#read 3, iclass 25, count 0 2006.169.07:44:04.89#ibcon#about to read 4, iclass 25, count 0 2006.169.07:44:04.89#ibcon#read 4, iclass 25, count 0 2006.169.07:44:04.89#ibcon#about to read 5, iclass 25, count 0 2006.169.07:44:04.89#ibcon#read 5, iclass 25, count 0 2006.169.07:44:04.89#ibcon#about to read 6, iclass 25, count 0 2006.169.07:44:04.89#ibcon#read 6, iclass 25, count 0 2006.169.07:44:04.89#ibcon#end of sib2, iclass 25, count 0 2006.169.07:44:04.89#ibcon#*after write, iclass 25, count 0 2006.169.07:44:04.89#ibcon#*before return 0, iclass 25, count 0 2006.169.07:44:04.89#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:44:04.89#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:44:04.89#ibcon#about to clear, iclass 25 cls_cnt 0 2006.169.07:44:04.89#ibcon#cleared, iclass 25 cls_cnt 0 2006.169.07:44:04.90$vc4f8/va=1,8 2006.169.07:44:04.90#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.169.07:44:04.90#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.169.07:44:04.90#ibcon#ireg 11 cls_cnt 2 2006.169.07:44:04.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.169.07:44:04.90#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.169.07:44:04.90#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.169.07:44:04.90#ibcon#enter wrdev, iclass 27, count 2 2006.169.07:44:04.90#ibcon#first serial, iclass 27, count 2 2006.169.07:44:04.90#ibcon#enter sib2, iclass 27, count 2 2006.169.07:44:04.90#ibcon#flushed, iclass 27, count 2 2006.169.07:44:04.90#ibcon#about to write, iclass 27, count 2 2006.169.07:44:04.90#ibcon#wrote, iclass 27, count 2 2006.169.07:44:04.90#ibcon#about to read 3, iclass 27, count 2 2006.169.07:44:04.92#ibcon#read 3, iclass 27, count 2 2006.169.07:44:04.92#ibcon#about to read 4, iclass 27, count 2 2006.169.07:44:04.92#ibcon#read 4, iclass 27, count 2 2006.169.07:44:04.92#ibcon#about to read 5, iclass 27, count 2 2006.169.07:44:04.92#ibcon#read 5, iclass 27, count 2 2006.169.07:44:04.92#ibcon#about to read 6, iclass 27, count 2 2006.169.07:44:04.92#ibcon#read 6, iclass 27, count 2 2006.169.07:44:04.92#ibcon#end of sib2, iclass 27, count 2 2006.169.07:44:04.92#ibcon#*mode == 0, iclass 27, count 2 2006.169.07:44:04.92#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.169.07:44:04.92#ibcon#[25=AT01-08\r\n] 2006.169.07:44:04.92#ibcon#*before write, iclass 27, count 2 2006.169.07:44:04.92#ibcon#enter sib2, iclass 27, count 2 2006.169.07:44:04.92#ibcon#flushed, iclass 27, count 2 2006.169.07:44:04.92#ibcon#about to write, iclass 27, count 2 2006.169.07:44:04.92#ibcon#wrote, iclass 27, count 2 2006.169.07:44:04.92#ibcon#about to read 3, iclass 27, count 2 2006.169.07:44:04.94#ibcon#read 3, iclass 27, count 2 2006.169.07:44:04.94#ibcon#about to read 4, iclass 27, count 2 2006.169.07:44:04.94#ibcon#read 4, iclass 27, count 2 2006.169.07:44:04.94#ibcon#about to read 5, iclass 27, count 2 2006.169.07:44:04.94#ibcon#read 5, iclass 27, count 2 2006.169.07:44:04.94#ibcon#about to read 6, iclass 27, count 2 2006.169.07:44:04.94#ibcon#read 6, iclass 27, count 2 2006.169.07:44:04.94#ibcon#end of sib2, iclass 27, count 2 2006.169.07:44:04.94#ibcon#*after write, iclass 27, count 2 2006.169.07:44:04.94#ibcon#*before return 0, iclass 27, count 2 2006.169.07:44:04.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.169.07:44:04.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.169.07:44:04.94#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.169.07:44:04.94#ibcon#ireg 7 cls_cnt 0 2006.169.07:44:04.94#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.169.07:44:05.06#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.169.07:44:05.06#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.169.07:44:05.06#ibcon#enter wrdev, iclass 27, count 0 2006.169.07:44:05.06#ibcon#first serial, iclass 27, count 0 2006.169.07:44:05.06#ibcon#enter sib2, iclass 27, count 0 2006.169.07:44:05.06#ibcon#flushed, iclass 27, count 0 2006.169.07:44:05.06#ibcon#about to write, iclass 27, count 0 2006.169.07:44:05.06#ibcon#wrote, iclass 27, count 0 2006.169.07:44:05.06#ibcon#about to read 3, iclass 27, count 0 2006.169.07:44:05.08#ibcon#read 3, iclass 27, count 0 2006.169.07:44:05.08#ibcon#about to read 4, iclass 27, count 0 2006.169.07:44:05.08#ibcon#read 4, iclass 27, count 0 2006.169.07:44:05.08#ibcon#about to read 5, iclass 27, count 0 2006.169.07:44:05.08#ibcon#read 5, iclass 27, count 0 2006.169.07:44:05.08#ibcon#about to read 6, iclass 27, count 0 2006.169.07:44:05.08#ibcon#read 6, iclass 27, count 0 2006.169.07:44:05.08#ibcon#end of sib2, iclass 27, count 0 2006.169.07:44:05.08#ibcon#*mode == 0, iclass 27, count 0 2006.169.07:44:05.08#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.169.07:44:05.08#ibcon#[25=USB\r\n] 2006.169.07:44:05.08#ibcon#*before write, iclass 27, count 0 2006.169.07:44:05.08#ibcon#enter sib2, iclass 27, count 0 2006.169.07:44:05.08#ibcon#flushed, iclass 27, count 0 2006.169.07:44:05.08#ibcon#about to write, iclass 27, count 0 2006.169.07:44:05.08#ibcon#wrote, iclass 27, count 0 2006.169.07:44:05.08#ibcon#about to read 3, iclass 27, count 0 2006.169.07:44:05.11#ibcon#read 3, iclass 27, count 0 2006.169.07:44:05.11#ibcon#about to read 4, iclass 27, count 0 2006.169.07:44:05.11#ibcon#read 4, iclass 27, count 0 2006.169.07:44:05.11#ibcon#about to read 5, iclass 27, count 0 2006.169.07:44:05.11#ibcon#read 5, iclass 27, count 0 2006.169.07:44:05.11#ibcon#about to read 6, iclass 27, count 0 2006.169.07:44:05.11#ibcon#read 6, iclass 27, count 0 2006.169.07:44:05.11#ibcon#end of sib2, iclass 27, count 0 2006.169.07:44:05.11#ibcon#*after write, iclass 27, count 0 2006.169.07:44:05.11#ibcon#*before return 0, iclass 27, count 0 2006.169.07:44:05.11#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.169.07:44:05.11#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.169.07:44:05.11#ibcon#about to clear, iclass 27 cls_cnt 0 2006.169.07:44:05.11#ibcon#cleared, iclass 27 cls_cnt 0 2006.169.07:44:05.11$vc4f8/valo=2,572.99 2006.169.07:44:05.11#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.169.07:44:05.11#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.169.07:44:05.11#ibcon#ireg 17 cls_cnt 0 2006.169.07:44:05.11#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.169.07:44:05.11#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.169.07:44:05.11#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.169.07:44:05.11#ibcon#enter wrdev, iclass 29, count 0 2006.169.07:44:05.11#ibcon#first serial, iclass 29, count 0 2006.169.07:44:05.11#ibcon#enter sib2, iclass 29, count 0 2006.169.07:44:05.11#ibcon#flushed, iclass 29, count 0 2006.169.07:44:05.11#ibcon#about to write, iclass 29, count 0 2006.169.07:44:05.11#ibcon#wrote, iclass 29, count 0 2006.169.07:44:05.11#ibcon#about to read 3, iclass 29, count 0 2006.169.07:44:05.13#ibcon#read 3, iclass 29, count 0 2006.169.07:44:05.13#ibcon#about to read 4, iclass 29, count 0 2006.169.07:44:05.13#ibcon#read 4, iclass 29, count 0 2006.169.07:44:05.13#ibcon#about to read 5, iclass 29, count 0 2006.169.07:44:05.13#ibcon#read 5, iclass 29, count 0 2006.169.07:44:05.13#ibcon#about to read 6, iclass 29, count 0 2006.169.07:44:05.13#ibcon#read 6, iclass 29, count 0 2006.169.07:44:05.13#ibcon#end of sib2, iclass 29, count 0 2006.169.07:44:05.13#ibcon#*mode == 0, iclass 29, count 0 2006.169.07:44:05.13#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.169.07:44:05.13#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.07:44:05.13#ibcon#*before write, iclass 29, count 0 2006.169.07:44:05.13#ibcon#enter sib2, iclass 29, count 0 2006.169.07:44:05.13#ibcon#flushed, iclass 29, count 0 2006.169.07:44:05.13#ibcon#about to write, iclass 29, count 0 2006.169.07:44:05.13#ibcon#wrote, iclass 29, count 0 2006.169.07:44:05.13#ibcon#about to read 3, iclass 29, count 0 2006.169.07:44:05.17#ibcon#read 3, iclass 29, count 0 2006.169.07:44:05.17#ibcon#about to read 4, iclass 29, count 0 2006.169.07:44:05.17#ibcon#read 4, iclass 29, count 0 2006.169.07:44:05.17#ibcon#about to read 5, iclass 29, count 0 2006.169.07:44:05.17#ibcon#read 5, iclass 29, count 0 2006.169.07:44:05.17#ibcon#about to read 6, iclass 29, count 0 2006.169.07:44:05.17#ibcon#read 6, iclass 29, count 0 2006.169.07:44:05.17#ibcon#end of sib2, iclass 29, count 0 2006.169.07:44:05.17#ibcon#*after write, iclass 29, count 0 2006.169.07:44:05.17#ibcon#*before return 0, iclass 29, count 0 2006.169.07:44:05.17#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.169.07:44:05.17#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.169.07:44:05.17#ibcon#about to clear, iclass 29 cls_cnt 0 2006.169.07:44:05.17#ibcon#cleared, iclass 29 cls_cnt 0 2006.169.07:44:05.17$vc4f8/va=2,7 2006.169.07:44:05.17#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.169.07:44:05.17#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.169.07:44:05.17#ibcon#ireg 11 cls_cnt 2 2006.169.07:44:05.17#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.169.07:44:05.23#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.169.07:44:05.23#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.169.07:44:05.23#ibcon#enter wrdev, iclass 31, count 2 2006.169.07:44:05.23#ibcon#first serial, iclass 31, count 2 2006.169.07:44:05.23#ibcon#enter sib2, iclass 31, count 2 2006.169.07:44:05.23#ibcon#flushed, iclass 31, count 2 2006.169.07:44:05.23#ibcon#about to write, iclass 31, count 2 2006.169.07:44:05.23#ibcon#wrote, iclass 31, count 2 2006.169.07:44:05.23#ibcon#about to read 3, iclass 31, count 2 2006.169.07:44:05.26#ibcon#read 3, iclass 31, count 2 2006.169.07:44:05.26#ibcon#about to read 4, iclass 31, count 2 2006.169.07:44:05.26#ibcon#read 4, iclass 31, count 2 2006.169.07:44:05.26#ibcon#about to read 5, iclass 31, count 2 2006.169.07:44:05.26#ibcon#read 5, iclass 31, count 2 2006.169.07:44:05.26#ibcon#about to read 6, iclass 31, count 2 2006.169.07:44:05.26#ibcon#read 6, iclass 31, count 2 2006.169.07:44:05.26#ibcon#end of sib2, iclass 31, count 2 2006.169.07:44:05.26#ibcon#*mode == 0, iclass 31, count 2 2006.169.07:44:05.26#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.169.07:44:05.26#ibcon#[25=AT02-07\r\n] 2006.169.07:44:05.26#ibcon#*before write, iclass 31, count 2 2006.169.07:44:05.26#ibcon#enter sib2, iclass 31, count 2 2006.169.07:44:05.26#ibcon#flushed, iclass 31, count 2 2006.169.07:44:05.26#ibcon#about to write, iclass 31, count 2 2006.169.07:44:05.26#ibcon#wrote, iclass 31, count 2 2006.169.07:44:05.26#ibcon#about to read 3, iclass 31, count 2 2006.169.07:44:05.28#ibcon#read 3, iclass 31, count 2 2006.169.07:44:05.28#ibcon#about to read 4, iclass 31, count 2 2006.169.07:44:05.28#ibcon#read 4, iclass 31, count 2 2006.169.07:44:05.28#ibcon#about to read 5, iclass 31, count 2 2006.169.07:44:05.28#ibcon#read 5, iclass 31, count 2 2006.169.07:44:05.28#ibcon#about to read 6, iclass 31, count 2 2006.169.07:44:05.28#ibcon#read 6, iclass 31, count 2 2006.169.07:44:05.28#ibcon#end of sib2, iclass 31, count 2 2006.169.07:44:05.28#ibcon#*after write, iclass 31, count 2 2006.169.07:44:05.28#ibcon#*before return 0, iclass 31, count 2 2006.169.07:44:05.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.169.07:44:05.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.169.07:44:05.28#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.169.07:44:05.28#ibcon#ireg 7 cls_cnt 0 2006.169.07:44:05.28#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.169.07:44:05.40#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.169.07:44:05.40#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.169.07:44:05.40#ibcon#enter wrdev, iclass 31, count 0 2006.169.07:44:05.40#ibcon#first serial, iclass 31, count 0 2006.169.07:44:05.40#ibcon#enter sib2, iclass 31, count 0 2006.169.07:44:05.40#ibcon#flushed, iclass 31, count 0 2006.169.07:44:05.40#ibcon#about to write, iclass 31, count 0 2006.169.07:44:05.40#ibcon#wrote, iclass 31, count 0 2006.169.07:44:05.40#ibcon#about to read 3, iclass 31, count 0 2006.169.07:44:05.42#ibcon#read 3, iclass 31, count 0 2006.169.07:44:05.42#ibcon#about to read 4, iclass 31, count 0 2006.169.07:44:05.42#ibcon#read 4, iclass 31, count 0 2006.169.07:44:05.42#ibcon#about to read 5, iclass 31, count 0 2006.169.07:44:05.42#ibcon#read 5, iclass 31, count 0 2006.169.07:44:05.42#ibcon#about to read 6, iclass 31, count 0 2006.169.07:44:05.42#ibcon#read 6, iclass 31, count 0 2006.169.07:44:05.42#ibcon#end of sib2, iclass 31, count 0 2006.169.07:44:05.42#ibcon#*mode == 0, iclass 31, count 0 2006.169.07:44:05.42#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.169.07:44:05.42#ibcon#[25=USB\r\n] 2006.169.07:44:05.42#ibcon#*before write, iclass 31, count 0 2006.169.07:44:05.42#ibcon#enter sib2, iclass 31, count 0 2006.169.07:44:05.42#ibcon#flushed, iclass 31, count 0 2006.169.07:44:05.42#ibcon#about to write, iclass 31, count 0 2006.169.07:44:05.42#ibcon#wrote, iclass 31, count 0 2006.169.07:44:05.42#ibcon#about to read 3, iclass 31, count 0 2006.169.07:44:05.45#ibcon#read 3, iclass 31, count 0 2006.169.07:44:05.45#ibcon#about to read 4, iclass 31, count 0 2006.169.07:44:05.45#ibcon#read 4, iclass 31, count 0 2006.169.07:44:05.45#ibcon#about to read 5, iclass 31, count 0 2006.169.07:44:05.45#ibcon#read 5, iclass 31, count 0 2006.169.07:44:05.45#ibcon#about to read 6, iclass 31, count 0 2006.169.07:44:05.45#ibcon#read 6, iclass 31, count 0 2006.169.07:44:05.45#ibcon#end of sib2, iclass 31, count 0 2006.169.07:44:05.45#ibcon#*after write, iclass 31, count 0 2006.169.07:44:05.45#ibcon#*before return 0, iclass 31, count 0 2006.169.07:44:05.45#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.169.07:44:05.45#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.169.07:44:05.45#ibcon#about to clear, iclass 31 cls_cnt 0 2006.169.07:44:05.45#ibcon#cleared, iclass 31 cls_cnt 0 2006.169.07:44:05.45$vc4f8/valo=3,672.99 2006.169.07:44:05.45#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.169.07:44:05.45#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.169.07:44:05.45#ibcon#ireg 17 cls_cnt 0 2006.169.07:44:05.45#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:44:05.45#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:44:05.45#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:44:05.45#ibcon#enter wrdev, iclass 33, count 0 2006.169.07:44:05.45#ibcon#first serial, iclass 33, count 0 2006.169.07:44:05.45#ibcon#enter sib2, iclass 33, count 0 2006.169.07:44:05.45#ibcon#flushed, iclass 33, count 0 2006.169.07:44:05.45#ibcon#about to write, iclass 33, count 0 2006.169.07:44:05.45#ibcon#wrote, iclass 33, count 0 2006.169.07:44:05.45#ibcon#about to read 3, iclass 33, count 0 2006.169.07:44:05.47#ibcon#read 3, iclass 33, count 0 2006.169.07:44:05.47#ibcon#about to read 4, iclass 33, count 0 2006.169.07:44:05.47#ibcon#read 4, iclass 33, count 0 2006.169.07:44:05.47#ibcon#about to read 5, iclass 33, count 0 2006.169.07:44:05.47#ibcon#read 5, iclass 33, count 0 2006.169.07:44:05.47#ibcon#about to read 6, iclass 33, count 0 2006.169.07:44:05.47#ibcon#read 6, iclass 33, count 0 2006.169.07:44:05.47#ibcon#end of sib2, iclass 33, count 0 2006.169.07:44:05.47#ibcon#*mode == 0, iclass 33, count 0 2006.169.07:44:05.47#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.169.07:44:05.47#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.07:44:05.47#ibcon#*before write, iclass 33, count 0 2006.169.07:44:05.47#ibcon#enter sib2, iclass 33, count 0 2006.169.07:44:05.47#ibcon#flushed, iclass 33, count 0 2006.169.07:44:05.47#ibcon#about to write, iclass 33, count 0 2006.169.07:44:05.47#ibcon#wrote, iclass 33, count 0 2006.169.07:44:05.47#ibcon#about to read 3, iclass 33, count 0 2006.169.07:44:05.51#ibcon#read 3, iclass 33, count 0 2006.169.07:44:05.51#ibcon#about to read 4, iclass 33, count 0 2006.169.07:44:05.51#ibcon#read 4, iclass 33, count 0 2006.169.07:44:05.51#ibcon#about to read 5, iclass 33, count 0 2006.169.07:44:05.51#ibcon#read 5, iclass 33, count 0 2006.169.07:44:05.51#ibcon#about to read 6, iclass 33, count 0 2006.169.07:44:05.51#ibcon#read 6, iclass 33, count 0 2006.169.07:44:05.51#ibcon#end of sib2, iclass 33, count 0 2006.169.07:44:05.51#ibcon#*after write, iclass 33, count 0 2006.169.07:44:05.51#ibcon#*before return 0, iclass 33, count 0 2006.169.07:44:05.51#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:44:05.51#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:44:05.51#ibcon#about to clear, iclass 33 cls_cnt 0 2006.169.07:44:05.51#ibcon#cleared, iclass 33 cls_cnt 0 2006.169.07:44:05.51$vc4f8/va=3,6 2006.169.07:44:05.51#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.169.07:44:05.51#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.169.07:44:05.51#ibcon#ireg 11 cls_cnt 2 2006.169.07:44:05.51#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:44:05.58#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:44:05.58#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:44:05.58#ibcon#enter wrdev, iclass 35, count 2 2006.169.07:44:05.58#ibcon#first serial, iclass 35, count 2 2006.169.07:44:05.58#ibcon#enter sib2, iclass 35, count 2 2006.169.07:44:05.58#ibcon#flushed, iclass 35, count 2 2006.169.07:44:05.58#ibcon#about to write, iclass 35, count 2 2006.169.07:44:05.58#ibcon#wrote, iclass 35, count 2 2006.169.07:44:05.58#ibcon#about to read 3, iclass 35, count 2 2006.169.07:44:05.60#ibcon#read 3, iclass 35, count 2 2006.169.07:44:05.60#ibcon#about to read 4, iclass 35, count 2 2006.169.07:44:05.60#ibcon#read 4, iclass 35, count 2 2006.169.07:44:05.60#ibcon#about to read 5, iclass 35, count 2 2006.169.07:44:05.60#ibcon#read 5, iclass 35, count 2 2006.169.07:44:05.60#ibcon#about to read 6, iclass 35, count 2 2006.169.07:44:05.60#ibcon#read 6, iclass 35, count 2 2006.169.07:44:05.60#ibcon#end of sib2, iclass 35, count 2 2006.169.07:44:05.60#ibcon#*mode == 0, iclass 35, count 2 2006.169.07:44:05.60#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.169.07:44:05.60#ibcon#[25=AT03-06\r\n] 2006.169.07:44:05.60#ibcon#*before write, iclass 35, count 2 2006.169.07:44:05.60#ibcon#enter sib2, iclass 35, count 2 2006.169.07:44:05.60#ibcon#flushed, iclass 35, count 2 2006.169.07:44:05.60#ibcon#about to write, iclass 35, count 2 2006.169.07:44:05.60#ibcon#wrote, iclass 35, count 2 2006.169.07:44:05.60#ibcon#about to read 3, iclass 35, count 2 2006.169.07:44:05.62#ibcon#read 3, iclass 35, count 2 2006.169.07:44:05.62#ibcon#about to read 4, iclass 35, count 2 2006.169.07:44:05.62#ibcon#read 4, iclass 35, count 2 2006.169.07:44:05.62#ibcon#about to read 5, iclass 35, count 2 2006.169.07:44:05.62#ibcon#read 5, iclass 35, count 2 2006.169.07:44:05.62#ibcon#about to read 6, iclass 35, count 2 2006.169.07:44:05.62#ibcon#read 6, iclass 35, count 2 2006.169.07:44:05.62#ibcon#end of sib2, iclass 35, count 2 2006.169.07:44:05.62#ibcon#*after write, iclass 35, count 2 2006.169.07:44:05.62#ibcon#*before return 0, iclass 35, count 2 2006.169.07:44:05.62#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:44:05.62#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:44:05.62#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.169.07:44:05.62#ibcon#ireg 7 cls_cnt 0 2006.169.07:44:05.62#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:44:05.74#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:44:05.74#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:44:05.74#ibcon#enter wrdev, iclass 35, count 0 2006.169.07:44:05.74#ibcon#first serial, iclass 35, count 0 2006.169.07:44:05.74#ibcon#enter sib2, iclass 35, count 0 2006.169.07:44:05.74#ibcon#flushed, iclass 35, count 0 2006.169.07:44:05.74#ibcon#about to write, iclass 35, count 0 2006.169.07:44:05.74#ibcon#wrote, iclass 35, count 0 2006.169.07:44:05.74#ibcon#about to read 3, iclass 35, count 0 2006.169.07:44:05.76#ibcon#read 3, iclass 35, count 0 2006.169.07:44:05.76#ibcon#about to read 4, iclass 35, count 0 2006.169.07:44:05.76#ibcon#read 4, iclass 35, count 0 2006.169.07:44:05.76#ibcon#about to read 5, iclass 35, count 0 2006.169.07:44:05.76#ibcon#read 5, iclass 35, count 0 2006.169.07:44:05.76#ibcon#about to read 6, iclass 35, count 0 2006.169.07:44:05.76#ibcon#read 6, iclass 35, count 0 2006.169.07:44:05.76#ibcon#end of sib2, iclass 35, count 0 2006.169.07:44:05.76#ibcon#*mode == 0, iclass 35, count 0 2006.169.07:44:05.76#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.169.07:44:05.76#ibcon#[25=USB\r\n] 2006.169.07:44:05.76#ibcon#*before write, iclass 35, count 0 2006.169.07:44:05.76#ibcon#enter sib2, iclass 35, count 0 2006.169.07:44:05.76#ibcon#flushed, iclass 35, count 0 2006.169.07:44:05.76#ibcon#about to write, iclass 35, count 0 2006.169.07:44:05.76#ibcon#wrote, iclass 35, count 0 2006.169.07:44:05.76#ibcon#about to read 3, iclass 35, count 0 2006.169.07:44:05.79#ibcon#read 3, iclass 35, count 0 2006.169.07:44:05.79#ibcon#about to read 4, iclass 35, count 0 2006.169.07:44:05.79#ibcon#read 4, iclass 35, count 0 2006.169.07:44:05.79#ibcon#about to read 5, iclass 35, count 0 2006.169.07:44:05.79#ibcon#read 5, iclass 35, count 0 2006.169.07:44:05.79#ibcon#about to read 6, iclass 35, count 0 2006.169.07:44:05.79#ibcon#read 6, iclass 35, count 0 2006.169.07:44:05.79#ibcon#end of sib2, iclass 35, count 0 2006.169.07:44:05.79#ibcon#*after write, iclass 35, count 0 2006.169.07:44:05.79#ibcon#*before return 0, iclass 35, count 0 2006.169.07:44:05.79#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:44:05.79#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:44:05.79#ibcon#about to clear, iclass 35 cls_cnt 0 2006.169.07:44:05.79#ibcon#cleared, iclass 35 cls_cnt 0 2006.169.07:44:05.79$vc4f8/valo=4,832.99 2006.169.07:44:05.79#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.169.07:44:05.79#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.169.07:44:05.79#ibcon#ireg 17 cls_cnt 0 2006.169.07:44:05.79#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:44:05.79#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:44:05.79#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:44:05.79#ibcon#enter wrdev, iclass 37, count 0 2006.169.07:44:05.79#ibcon#first serial, iclass 37, count 0 2006.169.07:44:05.79#ibcon#enter sib2, iclass 37, count 0 2006.169.07:44:05.79#ibcon#flushed, iclass 37, count 0 2006.169.07:44:05.79#ibcon#about to write, iclass 37, count 0 2006.169.07:44:05.79#ibcon#wrote, iclass 37, count 0 2006.169.07:44:05.79#ibcon#about to read 3, iclass 37, count 0 2006.169.07:44:05.81#ibcon#read 3, iclass 37, count 0 2006.169.07:44:05.81#ibcon#about to read 4, iclass 37, count 0 2006.169.07:44:05.81#ibcon#read 4, iclass 37, count 0 2006.169.07:44:05.81#ibcon#about to read 5, iclass 37, count 0 2006.169.07:44:05.81#ibcon#read 5, iclass 37, count 0 2006.169.07:44:05.81#ibcon#about to read 6, iclass 37, count 0 2006.169.07:44:05.81#ibcon#read 6, iclass 37, count 0 2006.169.07:44:05.81#ibcon#end of sib2, iclass 37, count 0 2006.169.07:44:05.81#ibcon#*mode == 0, iclass 37, count 0 2006.169.07:44:05.81#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.169.07:44:05.81#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.07:44:05.81#ibcon#*before write, iclass 37, count 0 2006.169.07:44:05.81#ibcon#enter sib2, iclass 37, count 0 2006.169.07:44:05.81#ibcon#flushed, iclass 37, count 0 2006.169.07:44:05.81#ibcon#about to write, iclass 37, count 0 2006.169.07:44:05.81#ibcon#wrote, iclass 37, count 0 2006.169.07:44:05.81#ibcon#about to read 3, iclass 37, count 0 2006.169.07:44:05.85#ibcon#read 3, iclass 37, count 0 2006.169.07:44:05.85#ibcon#about to read 4, iclass 37, count 0 2006.169.07:44:05.85#ibcon#read 4, iclass 37, count 0 2006.169.07:44:05.85#ibcon#about to read 5, iclass 37, count 0 2006.169.07:44:05.85#ibcon#read 5, iclass 37, count 0 2006.169.07:44:05.85#ibcon#about to read 6, iclass 37, count 0 2006.169.07:44:05.85#ibcon#read 6, iclass 37, count 0 2006.169.07:44:05.85#ibcon#end of sib2, iclass 37, count 0 2006.169.07:44:05.85#ibcon#*after write, iclass 37, count 0 2006.169.07:44:05.85#ibcon#*before return 0, iclass 37, count 0 2006.169.07:44:05.85#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:44:05.85#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:44:05.85#ibcon#about to clear, iclass 37 cls_cnt 0 2006.169.07:44:05.85#ibcon#cleared, iclass 37 cls_cnt 0 2006.169.07:44:05.85$vc4f8/va=4,7 2006.169.07:44:05.85#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.169.07:44:05.85#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.169.07:44:05.85#ibcon#ireg 11 cls_cnt 2 2006.169.07:44:05.85#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:44:05.91#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:44:05.91#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:44:05.91#ibcon#enter wrdev, iclass 39, count 2 2006.169.07:44:05.91#ibcon#first serial, iclass 39, count 2 2006.169.07:44:05.91#ibcon#enter sib2, iclass 39, count 2 2006.169.07:44:05.91#ibcon#flushed, iclass 39, count 2 2006.169.07:44:05.91#ibcon#about to write, iclass 39, count 2 2006.169.07:44:05.91#ibcon#wrote, iclass 39, count 2 2006.169.07:44:05.91#ibcon#about to read 3, iclass 39, count 2 2006.169.07:44:05.93#ibcon#read 3, iclass 39, count 2 2006.169.07:44:05.93#ibcon#about to read 4, iclass 39, count 2 2006.169.07:44:05.93#ibcon#read 4, iclass 39, count 2 2006.169.07:44:05.93#ibcon#about to read 5, iclass 39, count 2 2006.169.07:44:05.93#ibcon#read 5, iclass 39, count 2 2006.169.07:44:05.93#ibcon#about to read 6, iclass 39, count 2 2006.169.07:44:05.93#ibcon#read 6, iclass 39, count 2 2006.169.07:44:05.93#ibcon#end of sib2, iclass 39, count 2 2006.169.07:44:05.93#ibcon#*mode == 0, iclass 39, count 2 2006.169.07:44:05.93#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.169.07:44:05.93#ibcon#[25=AT04-07\r\n] 2006.169.07:44:05.93#ibcon#*before write, iclass 39, count 2 2006.169.07:44:05.93#ibcon#enter sib2, iclass 39, count 2 2006.169.07:44:05.93#ibcon#flushed, iclass 39, count 2 2006.169.07:44:05.93#ibcon#about to write, iclass 39, count 2 2006.169.07:44:05.93#ibcon#wrote, iclass 39, count 2 2006.169.07:44:05.93#ibcon#about to read 3, iclass 39, count 2 2006.169.07:44:05.96#ibcon#read 3, iclass 39, count 2 2006.169.07:44:05.96#ibcon#about to read 4, iclass 39, count 2 2006.169.07:44:05.96#ibcon#read 4, iclass 39, count 2 2006.169.07:44:05.96#ibcon#about to read 5, iclass 39, count 2 2006.169.07:44:05.96#ibcon#read 5, iclass 39, count 2 2006.169.07:44:05.96#ibcon#about to read 6, iclass 39, count 2 2006.169.07:44:05.96#ibcon#read 6, iclass 39, count 2 2006.169.07:44:05.96#ibcon#end of sib2, iclass 39, count 2 2006.169.07:44:05.96#ibcon#*after write, iclass 39, count 2 2006.169.07:44:05.96#ibcon#*before return 0, iclass 39, count 2 2006.169.07:44:05.96#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:44:05.96#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:44:05.96#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.169.07:44:05.96#ibcon#ireg 7 cls_cnt 0 2006.169.07:44:05.96#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:44:06.08#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:44:06.08#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:44:06.08#ibcon#enter wrdev, iclass 39, count 0 2006.169.07:44:06.08#ibcon#first serial, iclass 39, count 0 2006.169.07:44:06.08#ibcon#enter sib2, iclass 39, count 0 2006.169.07:44:06.08#ibcon#flushed, iclass 39, count 0 2006.169.07:44:06.08#ibcon#about to write, iclass 39, count 0 2006.169.07:44:06.08#ibcon#wrote, iclass 39, count 0 2006.169.07:44:06.08#ibcon#about to read 3, iclass 39, count 0 2006.169.07:44:06.10#ibcon#read 3, iclass 39, count 0 2006.169.07:44:06.10#ibcon#about to read 4, iclass 39, count 0 2006.169.07:44:06.10#ibcon#read 4, iclass 39, count 0 2006.169.07:44:06.10#ibcon#about to read 5, iclass 39, count 0 2006.169.07:44:06.10#ibcon#read 5, iclass 39, count 0 2006.169.07:44:06.10#ibcon#about to read 6, iclass 39, count 0 2006.169.07:44:06.10#ibcon#read 6, iclass 39, count 0 2006.169.07:44:06.10#ibcon#end of sib2, iclass 39, count 0 2006.169.07:44:06.10#ibcon#*mode == 0, iclass 39, count 0 2006.169.07:44:06.10#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.169.07:44:06.10#ibcon#[25=USB\r\n] 2006.169.07:44:06.10#ibcon#*before write, iclass 39, count 0 2006.169.07:44:06.10#ibcon#enter sib2, iclass 39, count 0 2006.169.07:44:06.10#ibcon#flushed, iclass 39, count 0 2006.169.07:44:06.10#ibcon#about to write, iclass 39, count 0 2006.169.07:44:06.10#ibcon#wrote, iclass 39, count 0 2006.169.07:44:06.10#ibcon#about to read 3, iclass 39, count 0 2006.169.07:44:06.13#ibcon#read 3, iclass 39, count 0 2006.169.07:44:06.13#ibcon#about to read 4, iclass 39, count 0 2006.169.07:44:06.13#ibcon#read 4, iclass 39, count 0 2006.169.07:44:06.13#ibcon#about to read 5, iclass 39, count 0 2006.169.07:44:06.13#ibcon#read 5, iclass 39, count 0 2006.169.07:44:06.13#ibcon#about to read 6, iclass 39, count 0 2006.169.07:44:06.13#ibcon#read 6, iclass 39, count 0 2006.169.07:44:06.13#ibcon#end of sib2, iclass 39, count 0 2006.169.07:44:06.13#ibcon#*after write, iclass 39, count 0 2006.169.07:44:06.13#ibcon#*before return 0, iclass 39, count 0 2006.169.07:44:06.13#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:44:06.13#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:44:06.13#ibcon#about to clear, iclass 39 cls_cnt 0 2006.169.07:44:06.13#ibcon#cleared, iclass 39 cls_cnt 0 2006.169.07:44:06.13$vc4f8/valo=5,652.99 2006.169.07:44:06.13#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.169.07:44:06.13#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.169.07:44:06.13#ibcon#ireg 17 cls_cnt 0 2006.169.07:44:06.13#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:44:06.13#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:44:06.13#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:44:06.13#ibcon#enter wrdev, iclass 3, count 0 2006.169.07:44:06.13#ibcon#first serial, iclass 3, count 0 2006.169.07:44:06.13#ibcon#enter sib2, iclass 3, count 0 2006.169.07:44:06.13#ibcon#flushed, iclass 3, count 0 2006.169.07:44:06.13#ibcon#about to write, iclass 3, count 0 2006.169.07:44:06.13#ibcon#wrote, iclass 3, count 0 2006.169.07:44:06.13#ibcon#about to read 3, iclass 3, count 0 2006.169.07:44:06.15#ibcon#read 3, iclass 3, count 0 2006.169.07:44:06.15#ibcon#about to read 4, iclass 3, count 0 2006.169.07:44:06.15#ibcon#read 4, iclass 3, count 0 2006.169.07:44:06.15#ibcon#about to read 5, iclass 3, count 0 2006.169.07:44:06.15#ibcon#read 5, iclass 3, count 0 2006.169.07:44:06.15#ibcon#about to read 6, iclass 3, count 0 2006.169.07:44:06.15#ibcon#read 6, iclass 3, count 0 2006.169.07:44:06.15#ibcon#end of sib2, iclass 3, count 0 2006.169.07:44:06.15#ibcon#*mode == 0, iclass 3, count 0 2006.169.07:44:06.15#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.169.07:44:06.15#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.07:44:06.15#ibcon#*before write, iclass 3, count 0 2006.169.07:44:06.15#ibcon#enter sib2, iclass 3, count 0 2006.169.07:44:06.15#ibcon#flushed, iclass 3, count 0 2006.169.07:44:06.15#ibcon#about to write, iclass 3, count 0 2006.169.07:44:06.15#ibcon#wrote, iclass 3, count 0 2006.169.07:44:06.15#ibcon#about to read 3, iclass 3, count 0 2006.169.07:44:06.19#ibcon#read 3, iclass 3, count 0 2006.169.07:44:06.19#ibcon#about to read 4, iclass 3, count 0 2006.169.07:44:06.19#ibcon#read 4, iclass 3, count 0 2006.169.07:44:06.19#ibcon#about to read 5, iclass 3, count 0 2006.169.07:44:06.19#ibcon#read 5, iclass 3, count 0 2006.169.07:44:06.19#ibcon#about to read 6, iclass 3, count 0 2006.169.07:44:06.19#ibcon#read 6, iclass 3, count 0 2006.169.07:44:06.19#ibcon#end of sib2, iclass 3, count 0 2006.169.07:44:06.19#ibcon#*after write, iclass 3, count 0 2006.169.07:44:06.19#ibcon#*before return 0, iclass 3, count 0 2006.169.07:44:06.19#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:44:06.19#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:44:06.19#ibcon#about to clear, iclass 3 cls_cnt 0 2006.169.07:44:06.19#ibcon#cleared, iclass 3 cls_cnt 0 2006.169.07:44:06.19$vc4f8/va=5,7 2006.169.07:44:06.19#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.169.07:44:06.19#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.169.07:44:06.19#ibcon#ireg 11 cls_cnt 2 2006.169.07:44:06.19#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:44:06.25#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:44:06.25#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:44:06.25#ibcon#enter wrdev, iclass 5, count 2 2006.169.07:44:06.25#ibcon#first serial, iclass 5, count 2 2006.169.07:44:06.25#ibcon#enter sib2, iclass 5, count 2 2006.169.07:44:06.25#ibcon#flushed, iclass 5, count 2 2006.169.07:44:06.25#ibcon#about to write, iclass 5, count 2 2006.169.07:44:06.25#ibcon#wrote, iclass 5, count 2 2006.169.07:44:06.25#ibcon#about to read 3, iclass 5, count 2 2006.169.07:44:06.27#ibcon#read 3, iclass 5, count 2 2006.169.07:44:06.27#ibcon#about to read 4, iclass 5, count 2 2006.169.07:44:06.27#ibcon#read 4, iclass 5, count 2 2006.169.07:44:06.27#ibcon#about to read 5, iclass 5, count 2 2006.169.07:44:06.27#ibcon#read 5, iclass 5, count 2 2006.169.07:44:06.27#ibcon#about to read 6, iclass 5, count 2 2006.169.07:44:06.27#ibcon#read 6, iclass 5, count 2 2006.169.07:44:06.27#ibcon#end of sib2, iclass 5, count 2 2006.169.07:44:06.27#ibcon#*mode == 0, iclass 5, count 2 2006.169.07:44:06.27#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.169.07:44:06.27#ibcon#[25=AT05-07\r\n] 2006.169.07:44:06.27#ibcon#*before write, iclass 5, count 2 2006.169.07:44:06.27#ibcon#enter sib2, iclass 5, count 2 2006.169.07:44:06.27#ibcon#flushed, iclass 5, count 2 2006.169.07:44:06.27#ibcon#about to write, iclass 5, count 2 2006.169.07:44:06.27#ibcon#wrote, iclass 5, count 2 2006.169.07:44:06.27#ibcon#about to read 3, iclass 5, count 2 2006.169.07:44:06.30#ibcon#read 3, iclass 5, count 2 2006.169.07:44:06.30#ibcon#about to read 4, iclass 5, count 2 2006.169.07:44:06.30#ibcon#read 4, iclass 5, count 2 2006.169.07:44:06.30#ibcon#about to read 5, iclass 5, count 2 2006.169.07:44:06.30#ibcon#read 5, iclass 5, count 2 2006.169.07:44:06.30#ibcon#about to read 6, iclass 5, count 2 2006.169.07:44:06.30#ibcon#read 6, iclass 5, count 2 2006.169.07:44:06.30#ibcon#end of sib2, iclass 5, count 2 2006.169.07:44:06.30#ibcon#*after write, iclass 5, count 2 2006.169.07:44:06.30#ibcon#*before return 0, iclass 5, count 2 2006.169.07:44:06.30#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:44:06.30#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:44:06.30#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.169.07:44:06.30#ibcon#ireg 7 cls_cnt 0 2006.169.07:44:06.30#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:44:06.42#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:44:06.42#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:44:06.42#ibcon#enter wrdev, iclass 5, count 0 2006.169.07:44:06.42#ibcon#first serial, iclass 5, count 0 2006.169.07:44:06.42#ibcon#enter sib2, iclass 5, count 0 2006.169.07:44:06.42#ibcon#flushed, iclass 5, count 0 2006.169.07:44:06.42#ibcon#about to write, iclass 5, count 0 2006.169.07:44:06.42#ibcon#wrote, iclass 5, count 0 2006.169.07:44:06.42#ibcon#about to read 3, iclass 5, count 0 2006.169.07:44:06.44#ibcon#read 3, iclass 5, count 0 2006.169.07:44:06.44#ibcon#about to read 4, iclass 5, count 0 2006.169.07:44:06.44#ibcon#read 4, iclass 5, count 0 2006.169.07:44:06.44#ibcon#about to read 5, iclass 5, count 0 2006.169.07:44:06.44#ibcon#read 5, iclass 5, count 0 2006.169.07:44:06.44#ibcon#about to read 6, iclass 5, count 0 2006.169.07:44:06.44#ibcon#read 6, iclass 5, count 0 2006.169.07:44:06.44#ibcon#end of sib2, iclass 5, count 0 2006.169.07:44:06.44#ibcon#*mode == 0, iclass 5, count 0 2006.169.07:44:06.44#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.169.07:44:06.44#ibcon#[25=USB\r\n] 2006.169.07:44:06.44#ibcon#*before write, iclass 5, count 0 2006.169.07:44:06.44#ibcon#enter sib2, iclass 5, count 0 2006.169.07:44:06.44#ibcon#flushed, iclass 5, count 0 2006.169.07:44:06.44#ibcon#about to write, iclass 5, count 0 2006.169.07:44:06.44#ibcon#wrote, iclass 5, count 0 2006.169.07:44:06.44#ibcon#about to read 3, iclass 5, count 0 2006.169.07:44:06.47#ibcon#read 3, iclass 5, count 0 2006.169.07:44:06.47#ibcon#about to read 4, iclass 5, count 0 2006.169.07:44:06.47#ibcon#read 4, iclass 5, count 0 2006.169.07:44:06.47#ibcon#about to read 5, iclass 5, count 0 2006.169.07:44:06.47#ibcon#read 5, iclass 5, count 0 2006.169.07:44:06.47#ibcon#about to read 6, iclass 5, count 0 2006.169.07:44:06.47#ibcon#read 6, iclass 5, count 0 2006.169.07:44:06.47#ibcon#end of sib2, iclass 5, count 0 2006.169.07:44:06.47#ibcon#*after write, iclass 5, count 0 2006.169.07:44:06.47#ibcon#*before return 0, iclass 5, count 0 2006.169.07:44:06.47#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:44:06.47#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:44:06.47#ibcon#about to clear, iclass 5 cls_cnt 0 2006.169.07:44:06.47#ibcon#cleared, iclass 5 cls_cnt 0 2006.169.07:44:06.47$vc4f8/valo=6,772.99 2006.169.07:44:06.47#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.169.07:44:06.47#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.169.07:44:06.47#ibcon#ireg 17 cls_cnt 0 2006.169.07:44:06.47#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:44:06.47#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:44:06.47#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:44:06.47#ibcon#enter wrdev, iclass 7, count 0 2006.169.07:44:06.47#ibcon#first serial, iclass 7, count 0 2006.169.07:44:06.47#ibcon#enter sib2, iclass 7, count 0 2006.169.07:44:06.47#ibcon#flushed, iclass 7, count 0 2006.169.07:44:06.47#ibcon#about to write, iclass 7, count 0 2006.169.07:44:06.47#ibcon#wrote, iclass 7, count 0 2006.169.07:44:06.47#ibcon#about to read 3, iclass 7, count 0 2006.169.07:44:06.49#ibcon#read 3, iclass 7, count 0 2006.169.07:44:06.49#ibcon#about to read 4, iclass 7, count 0 2006.169.07:44:06.49#ibcon#read 4, iclass 7, count 0 2006.169.07:44:06.49#ibcon#about to read 5, iclass 7, count 0 2006.169.07:44:06.49#ibcon#read 5, iclass 7, count 0 2006.169.07:44:06.49#ibcon#about to read 6, iclass 7, count 0 2006.169.07:44:06.49#ibcon#read 6, iclass 7, count 0 2006.169.07:44:06.49#ibcon#end of sib2, iclass 7, count 0 2006.169.07:44:06.49#ibcon#*mode == 0, iclass 7, count 0 2006.169.07:44:06.49#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.169.07:44:06.49#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.07:44:06.49#ibcon#*before write, iclass 7, count 0 2006.169.07:44:06.49#ibcon#enter sib2, iclass 7, count 0 2006.169.07:44:06.49#ibcon#flushed, iclass 7, count 0 2006.169.07:44:06.49#ibcon#about to write, iclass 7, count 0 2006.169.07:44:06.49#ibcon#wrote, iclass 7, count 0 2006.169.07:44:06.49#ibcon#about to read 3, iclass 7, count 0 2006.169.07:44:06.53#ibcon#read 3, iclass 7, count 0 2006.169.07:44:06.53#ibcon#about to read 4, iclass 7, count 0 2006.169.07:44:06.53#ibcon#read 4, iclass 7, count 0 2006.169.07:44:06.53#ibcon#about to read 5, iclass 7, count 0 2006.169.07:44:06.53#ibcon#read 5, iclass 7, count 0 2006.169.07:44:06.53#ibcon#about to read 6, iclass 7, count 0 2006.169.07:44:06.53#ibcon#read 6, iclass 7, count 0 2006.169.07:44:06.53#ibcon#end of sib2, iclass 7, count 0 2006.169.07:44:06.53#ibcon#*after write, iclass 7, count 0 2006.169.07:44:06.53#ibcon#*before return 0, iclass 7, count 0 2006.169.07:44:06.53#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:44:06.53#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:44:06.53#ibcon#about to clear, iclass 7 cls_cnt 0 2006.169.07:44:06.53#ibcon#cleared, iclass 7 cls_cnt 0 2006.169.07:44:06.53$vc4f8/va=6,6 2006.169.07:44:06.53#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.169.07:44:06.53#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.169.07:44:06.53#ibcon#ireg 11 cls_cnt 2 2006.169.07:44:06.53#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:44:06.59#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:44:06.59#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:44:06.59#ibcon#enter wrdev, iclass 11, count 2 2006.169.07:44:06.59#ibcon#first serial, iclass 11, count 2 2006.169.07:44:06.59#ibcon#enter sib2, iclass 11, count 2 2006.169.07:44:06.59#ibcon#flushed, iclass 11, count 2 2006.169.07:44:06.59#ibcon#about to write, iclass 11, count 2 2006.169.07:44:06.59#ibcon#wrote, iclass 11, count 2 2006.169.07:44:06.59#ibcon#about to read 3, iclass 11, count 2 2006.169.07:44:06.61#ibcon#read 3, iclass 11, count 2 2006.169.07:44:06.61#ibcon#about to read 4, iclass 11, count 2 2006.169.07:44:06.61#ibcon#read 4, iclass 11, count 2 2006.169.07:44:06.61#ibcon#about to read 5, iclass 11, count 2 2006.169.07:44:06.61#ibcon#read 5, iclass 11, count 2 2006.169.07:44:06.61#ibcon#about to read 6, iclass 11, count 2 2006.169.07:44:06.61#ibcon#read 6, iclass 11, count 2 2006.169.07:44:06.61#ibcon#end of sib2, iclass 11, count 2 2006.169.07:44:06.61#ibcon#*mode == 0, iclass 11, count 2 2006.169.07:44:06.61#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.169.07:44:06.61#ibcon#[25=AT06-06\r\n] 2006.169.07:44:06.61#ibcon#*before write, iclass 11, count 2 2006.169.07:44:06.61#ibcon#enter sib2, iclass 11, count 2 2006.169.07:44:06.61#ibcon#flushed, iclass 11, count 2 2006.169.07:44:06.61#ibcon#about to write, iclass 11, count 2 2006.169.07:44:06.61#ibcon#wrote, iclass 11, count 2 2006.169.07:44:06.61#ibcon#about to read 3, iclass 11, count 2 2006.169.07:44:06.64#ibcon#read 3, iclass 11, count 2 2006.169.07:44:06.64#ibcon#about to read 4, iclass 11, count 2 2006.169.07:44:06.64#ibcon#read 4, iclass 11, count 2 2006.169.07:44:06.64#ibcon#about to read 5, iclass 11, count 2 2006.169.07:44:06.64#ibcon#read 5, iclass 11, count 2 2006.169.07:44:06.64#ibcon#about to read 6, iclass 11, count 2 2006.169.07:44:06.64#ibcon#read 6, iclass 11, count 2 2006.169.07:44:06.64#ibcon#end of sib2, iclass 11, count 2 2006.169.07:44:06.64#ibcon#*after write, iclass 11, count 2 2006.169.07:44:06.64#ibcon#*before return 0, iclass 11, count 2 2006.169.07:44:06.64#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:44:06.64#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:44:06.64#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.169.07:44:06.64#ibcon#ireg 7 cls_cnt 0 2006.169.07:44:06.64#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:44:06.76#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:44:06.76#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:44:06.76#ibcon#enter wrdev, iclass 11, count 0 2006.169.07:44:06.76#ibcon#first serial, iclass 11, count 0 2006.169.07:44:06.76#ibcon#enter sib2, iclass 11, count 0 2006.169.07:44:06.76#ibcon#flushed, iclass 11, count 0 2006.169.07:44:06.76#ibcon#about to write, iclass 11, count 0 2006.169.07:44:06.76#ibcon#wrote, iclass 11, count 0 2006.169.07:44:06.76#ibcon#about to read 3, iclass 11, count 0 2006.169.07:44:06.78#ibcon#read 3, iclass 11, count 0 2006.169.07:44:06.78#ibcon#about to read 4, iclass 11, count 0 2006.169.07:44:06.78#ibcon#read 4, iclass 11, count 0 2006.169.07:44:06.78#ibcon#about to read 5, iclass 11, count 0 2006.169.07:44:06.78#ibcon#read 5, iclass 11, count 0 2006.169.07:44:06.78#ibcon#about to read 6, iclass 11, count 0 2006.169.07:44:06.78#ibcon#read 6, iclass 11, count 0 2006.169.07:44:06.78#ibcon#end of sib2, iclass 11, count 0 2006.169.07:44:06.78#ibcon#*mode == 0, iclass 11, count 0 2006.169.07:44:06.78#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.169.07:44:06.78#ibcon#[25=USB\r\n] 2006.169.07:44:06.78#ibcon#*before write, iclass 11, count 0 2006.169.07:44:06.78#ibcon#enter sib2, iclass 11, count 0 2006.169.07:44:06.78#ibcon#flushed, iclass 11, count 0 2006.169.07:44:06.78#ibcon#about to write, iclass 11, count 0 2006.169.07:44:06.78#ibcon#wrote, iclass 11, count 0 2006.169.07:44:06.78#ibcon#about to read 3, iclass 11, count 0 2006.169.07:44:06.81#ibcon#read 3, iclass 11, count 0 2006.169.07:44:06.81#ibcon#about to read 4, iclass 11, count 0 2006.169.07:44:06.81#ibcon#read 4, iclass 11, count 0 2006.169.07:44:06.81#ibcon#about to read 5, iclass 11, count 0 2006.169.07:44:06.81#ibcon#read 5, iclass 11, count 0 2006.169.07:44:06.81#ibcon#about to read 6, iclass 11, count 0 2006.169.07:44:06.81#ibcon#read 6, iclass 11, count 0 2006.169.07:44:06.81#ibcon#end of sib2, iclass 11, count 0 2006.169.07:44:06.81#ibcon#*after write, iclass 11, count 0 2006.169.07:44:06.81#ibcon#*before return 0, iclass 11, count 0 2006.169.07:44:06.81#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:44:06.81#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:44:06.81#ibcon#about to clear, iclass 11 cls_cnt 0 2006.169.07:44:06.81#ibcon#cleared, iclass 11 cls_cnt 0 2006.169.07:44:06.81$vc4f8/valo=7,832.99 2006.169.07:44:06.81#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.169.07:44:06.81#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.169.07:44:06.81#ibcon#ireg 17 cls_cnt 0 2006.169.07:44:06.81#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:44:06.81#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:44:06.81#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:44:06.81#ibcon#enter wrdev, iclass 13, count 0 2006.169.07:44:06.81#ibcon#first serial, iclass 13, count 0 2006.169.07:44:06.81#ibcon#enter sib2, iclass 13, count 0 2006.169.07:44:06.81#ibcon#flushed, iclass 13, count 0 2006.169.07:44:06.81#ibcon#about to write, iclass 13, count 0 2006.169.07:44:06.81#ibcon#wrote, iclass 13, count 0 2006.169.07:44:06.81#ibcon#about to read 3, iclass 13, count 0 2006.169.07:44:06.83#ibcon#read 3, iclass 13, count 0 2006.169.07:44:06.83#ibcon#about to read 4, iclass 13, count 0 2006.169.07:44:06.83#ibcon#read 4, iclass 13, count 0 2006.169.07:44:06.83#ibcon#about to read 5, iclass 13, count 0 2006.169.07:44:06.83#ibcon#read 5, iclass 13, count 0 2006.169.07:44:06.83#ibcon#about to read 6, iclass 13, count 0 2006.169.07:44:06.83#ibcon#read 6, iclass 13, count 0 2006.169.07:44:06.83#ibcon#end of sib2, iclass 13, count 0 2006.169.07:44:06.83#ibcon#*mode == 0, iclass 13, count 0 2006.169.07:44:06.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.07:44:06.83#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.07:44:06.83#ibcon#*before write, iclass 13, count 0 2006.169.07:44:06.83#ibcon#enter sib2, iclass 13, count 0 2006.169.07:44:06.83#ibcon#flushed, iclass 13, count 0 2006.169.07:44:06.83#ibcon#about to write, iclass 13, count 0 2006.169.07:44:06.83#ibcon#wrote, iclass 13, count 0 2006.169.07:44:06.83#ibcon#about to read 3, iclass 13, count 0 2006.169.07:44:06.87#ibcon#read 3, iclass 13, count 0 2006.169.07:44:06.87#ibcon#about to read 4, iclass 13, count 0 2006.169.07:44:06.87#ibcon#read 4, iclass 13, count 0 2006.169.07:44:06.87#ibcon#about to read 5, iclass 13, count 0 2006.169.07:44:06.87#ibcon#read 5, iclass 13, count 0 2006.169.07:44:06.87#ibcon#about to read 6, iclass 13, count 0 2006.169.07:44:06.87#ibcon#read 6, iclass 13, count 0 2006.169.07:44:06.87#ibcon#end of sib2, iclass 13, count 0 2006.169.07:44:06.87#ibcon#*after write, iclass 13, count 0 2006.169.07:44:06.87#ibcon#*before return 0, iclass 13, count 0 2006.169.07:44:06.87#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:44:06.87#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:44:06.87#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.07:44:06.87#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.07:44:06.87$vc4f8/va=7,6 2006.169.07:44:06.87#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.169.07:44:06.87#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.169.07:44:06.87#ibcon#ireg 11 cls_cnt 2 2006.169.07:44:06.87#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:44:06.93#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:44:06.93#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:44:06.93#ibcon#enter wrdev, iclass 15, count 2 2006.169.07:44:06.93#ibcon#first serial, iclass 15, count 2 2006.169.07:44:06.93#ibcon#enter sib2, iclass 15, count 2 2006.169.07:44:06.93#ibcon#flushed, iclass 15, count 2 2006.169.07:44:06.93#ibcon#about to write, iclass 15, count 2 2006.169.07:44:06.93#ibcon#wrote, iclass 15, count 2 2006.169.07:44:06.93#ibcon#about to read 3, iclass 15, count 2 2006.169.07:44:06.95#ibcon#read 3, iclass 15, count 2 2006.169.07:44:06.95#ibcon#about to read 4, iclass 15, count 2 2006.169.07:44:06.95#ibcon#read 4, iclass 15, count 2 2006.169.07:44:06.95#ibcon#about to read 5, iclass 15, count 2 2006.169.07:44:06.95#ibcon#read 5, iclass 15, count 2 2006.169.07:44:06.95#ibcon#about to read 6, iclass 15, count 2 2006.169.07:44:06.95#ibcon#read 6, iclass 15, count 2 2006.169.07:44:06.95#ibcon#end of sib2, iclass 15, count 2 2006.169.07:44:06.95#ibcon#*mode == 0, iclass 15, count 2 2006.169.07:44:06.95#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.169.07:44:06.95#ibcon#[25=AT07-06\r\n] 2006.169.07:44:06.95#ibcon#*before write, iclass 15, count 2 2006.169.07:44:06.95#ibcon#enter sib2, iclass 15, count 2 2006.169.07:44:06.95#ibcon#flushed, iclass 15, count 2 2006.169.07:44:06.95#ibcon#about to write, iclass 15, count 2 2006.169.07:44:06.95#ibcon#wrote, iclass 15, count 2 2006.169.07:44:06.95#ibcon#about to read 3, iclass 15, count 2 2006.169.07:44:06.98#ibcon#read 3, iclass 15, count 2 2006.169.07:44:06.98#ibcon#about to read 4, iclass 15, count 2 2006.169.07:44:06.98#ibcon#read 4, iclass 15, count 2 2006.169.07:44:06.98#ibcon#about to read 5, iclass 15, count 2 2006.169.07:44:06.98#ibcon#read 5, iclass 15, count 2 2006.169.07:44:06.98#ibcon#about to read 6, iclass 15, count 2 2006.169.07:44:06.98#ibcon#read 6, iclass 15, count 2 2006.169.07:44:06.98#ibcon#end of sib2, iclass 15, count 2 2006.169.07:44:06.98#ibcon#*after write, iclass 15, count 2 2006.169.07:44:06.98#ibcon#*before return 0, iclass 15, count 2 2006.169.07:44:06.98#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:44:06.98#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:44:06.98#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.169.07:44:06.98#ibcon#ireg 7 cls_cnt 0 2006.169.07:44:06.98#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:44:07.10#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:44:07.10#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:44:07.10#ibcon#enter wrdev, iclass 15, count 0 2006.169.07:44:07.10#ibcon#first serial, iclass 15, count 0 2006.169.07:44:07.10#ibcon#enter sib2, iclass 15, count 0 2006.169.07:44:07.10#ibcon#flushed, iclass 15, count 0 2006.169.07:44:07.10#ibcon#about to write, iclass 15, count 0 2006.169.07:44:07.10#ibcon#wrote, iclass 15, count 0 2006.169.07:44:07.10#ibcon#about to read 3, iclass 15, count 0 2006.169.07:44:07.12#ibcon#read 3, iclass 15, count 0 2006.169.07:44:07.12#ibcon#about to read 4, iclass 15, count 0 2006.169.07:44:07.12#ibcon#read 4, iclass 15, count 0 2006.169.07:44:07.12#ibcon#about to read 5, iclass 15, count 0 2006.169.07:44:07.12#ibcon#read 5, iclass 15, count 0 2006.169.07:44:07.12#ibcon#about to read 6, iclass 15, count 0 2006.169.07:44:07.12#ibcon#read 6, iclass 15, count 0 2006.169.07:44:07.12#ibcon#end of sib2, iclass 15, count 0 2006.169.07:44:07.12#ibcon#*mode == 0, iclass 15, count 0 2006.169.07:44:07.12#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.169.07:44:07.12#ibcon#[25=USB\r\n] 2006.169.07:44:07.12#ibcon#*before write, iclass 15, count 0 2006.169.07:44:07.12#ibcon#enter sib2, iclass 15, count 0 2006.169.07:44:07.12#ibcon#flushed, iclass 15, count 0 2006.169.07:44:07.12#ibcon#about to write, iclass 15, count 0 2006.169.07:44:07.12#ibcon#wrote, iclass 15, count 0 2006.169.07:44:07.12#ibcon#about to read 3, iclass 15, count 0 2006.169.07:44:07.15#ibcon#read 3, iclass 15, count 0 2006.169.07:44:07.15#ibcon#about to read 4, iclass 15, count 0 2006.169.07:44:07.15#ibcon#read 4, iclass 15, count 0 2006.169.07:44:07.15#ibcon#about to read 5, iclass 15, count 0 2006.169.07:44:07.15#ibcon#read 5, iclass 15, count 0 2006.169.07:44:07.15#ibcon#about to read 6, iclass 15, count 0 2006.169.07:44:07.15#ibcon#read 6, iclass 15, count 0 2006.169.07:44:07.15#ibcon#end of sib2, iclass 15, count 0 2006.169.07:44:07.15#ibcon#*after write, iclass 15, count 0 2006.169.07:44:07.15#ibcon#*before return 0, iclass 15, count 0 2006.169.07:44:07.15#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:44:07.15#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:44:07.15#ibcon#about to clear, iclass 15 cls_cnt 0 2006.169.07:44:07.15#ibcon#cleared, iclass 15 cls_cnt 0 2006.169.07:44:07.15$vc4f8/valo=8,852.99 2006.169.07:44:07.15#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.169.07:44:07.15#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.169.07:44:07.15#ibcon#ireg 17 cls_cnt 0 2006.169.07:44:07.15#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:44:07.15#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:44:07.15#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:44:07.15#ibcon#enter wrdev, iclass 17, count 0 2006.169.07:44:07.15#ibcon#first serial, iclass 17, count 0 2006.169.07:44:07.15#ibcon#enter sib2, iclass 17, count 0 2006.169.07:44:07.15#ibcon#flushed, iclass 17, count 0 2006.169.07:44:07.15#ibcon#about to write, iclass 17, count 0 2006.169.07:44:07.15#ibcon#wrote, iclass 17, count 0 2006.169.07:44:07.15#ibcon#about to read 3, iclass 17, count 0 2006.169.07:44:07.17#ibcon#read 3, iclass 17, count 0 2006.169.07:44:07.17#ibcon#about to read 4, iclass 17, count 0 2006.169.07:44:07.17#ibcon#read 4, iclass 17, count 0 2006.169.07:44:07.17#ibcon#about to read 5, iclass 17, count 0 2006.169.07:44:07.17#ibcon#read 5, iclass 17, count 0 2006.169.07:44:07.17#ibcon#about to read 6, iclass 17, count 0 2006.169.07:44:07.17#ibcon#read 6, iclass 17, count 0 2006.169.07:44:07.17#ibcon#end of sib2, iclass 17, count 0 2006.169.07:44:07.17#ibcon#*mode == 0, iclass 17, count 0 2006.169.07:44:07.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.169.07:44:07.17#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.07:44:07.17#ibcon#*before write, iclass 17, count 0 2006.169.07:44:07.17#ibcon#enter sib2, iclass 17, count 0 2006.169.07:44:07.17#ibcon#flushed, iclass 17, count 0 2006.169.07:44:07.17#ibcon#about to write, iclass 17, count 0 2006.169.07:44:07.17#ibcon#wrote, iclass 17, count 0 2006.169.07:44:07.17#ibcon#about to read 3, iclass 17, count 0 2006.169.07:44:07.21#ibcon#read 3, iclass 17, count 0 2006.169.07:44:07.21#ibcon#about to read 4, iclass 17, count 0 2006.169.07:44:07.21#ibcon#read 4, iclass 17, count 0 2006.169.07:44:07.21#ibcon#about to read 5, iclass 17, count 0 2006.169.07:44:07.21#ibcon#read 5, iclass 17, count 0 2006.169.07:44:07.21#ibcon#about to read 6, iclass 17, count 0 2006.169.07:44:07.21#ibcon#read 6, iclass 17, count 0 2006.169.07:44:07.21#ibcon#end of sib2, iclass 17, count 0 2006.169.07:44:07.21#ibcon#*after write, iclass 17, count 0 2006.169.07:44:07.21#ibcon#*before return 0, iclass 17, count 0 2006.169.07:44:07.21#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:44:07.21#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:44:07.21#ibcon#about to clear, iclass 17 cls_cnt 0 2006.169.07:44:07.21#ibcon#cleared, iclass 17 cls_cnt 0 2006.169.07:44:07.21$vc4f8/va=8,7 2006.169.07:44:07.21#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.169.07:44:07.21#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.169.07:44:07.21#ibcon#ireg 11 cls_cnt 2 2006.169.07:44:07.21#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:44:07.27#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:44:07.27#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:44:07.27#ibcon#enter wrdev, iclass 19, count 2 2006.169.07:44:07.27#ibcon#first serial, iclass 19, count 2 2006.169.07:44:07.27#ibcon#enter sib2, iclass 19, count 2 2006.169.07:44:07.27#ibcon#flushed, iclass 19, count 2 2006.169.07:44:07.27#ibcon#about to write, iclass 19, count 2 2006.169.07:44:07.27#ibcon#wrote, iclass 19, count 2 2006.169.07:44:07.27#ibcon#about to read 3, iclass 19, count 2 2006.169.07:44:07.29#ibcon#read 3, iclass 19, count 2 2006.169.07:44:07.29#ibcon#about to read 4, iclass 19, count 2 2006.169.07:44:07.29#ibcon#read 4, iclass 19, count 2 2006.169.07:44:07.29#ibcon#about to read 5, iclass 19, count 2 2006.169.07:44:07.29#ibcon#read 5, iclass 19, count 2 2006.169.07:44:07.29#ibcon#about to read 6, iclass 19, count 2 2006.169.07:44:07.29#ibcon#read 6, iclass 19, count 2 2006.169.07:44:07.29#ibcon#end of sib2, iclass 19, count 2 2006.169.07:44:07.29#ibcon#*mode == 0, iclass 19, count 2 2006.169.07:44:07.29#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.169.07:44:07.29#ibcon#[25=AT08-07\r\n] 2006.169.07:44:07.29#ibcon#*before write, iclass 19, count 2 2006.169.07:44:07.29#ibcon#enter sib2, iclass 19, count 2 2006.169.07:44:07.29#ibcon#flushed, iclass 19, count 2 2006.169.07:44:07.29#ibcon#about to write, iclass 19, count 2 2006.169.07:44:07.29#ibcon#wrote, iclass 19, count 2 2006.169.07:44:07.29#ibcon#about to read 3, iclass 19, count 2 2006.169.07:44:07.32#ibcon#read 3, iclass 19, count 2 2006.169.07:44:07.32#ibcon#about to read 4, iclass 19, count 2 2006.169.07:44:07.32#ibcon#read 4, iclass 19, count 2 2006.169.07:44:07.32#ibcon#about to read 5, iclass 19, count 2 2006.169.07:44:07.32#ibcon#read 5, iclass 19, count 2 2006.169.07:44:07.32#ibcon#about to read 6, iclass 19, count 2 2006.169.07:44:07.32#ibcon#read 6, iclass 19, count 2 2006.169.07:44:07.32#ibcon#end of sib2, iclass 19, count 2 2006.169.07:44:07.32#ibcon#*after write, iclass 19, count 2 2006.169.07:44:07.32#ibcon#*before return 0, iclass 19, count 2 2006.169.07:44:07.32#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:44:07.32#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:44:07.32#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.169.07:44:07.32#ibcon#ireg 7 cls_cnt 0 2006.169.07:44:07.32#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:44:07.44#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:44:07.44#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:44:07.44#ibcon#enter wrdev, iclass 19, count 0 2006.169.07:44:07.44#ibcon#first serial, iclass 19, count 0 2006.169.07:44:07.44#ibcon#enter sib2, iclass 19, count 0 2006.169.07:44:07.44#ibcon#flushed, iclass 19, count 0 2006.169.07:44:07.44#ibcon#about to write, iclass 19, count 0 2006.169.07:44:07.44#ibcon#wrote, iclass 19, count 0 2006.169.07:44:07.44#ibcon#about to read 3, iclass 19, count 0 2006.169.07:44:07.46#ibcon#read 3, iclass 19, count 0 2006.169.07:44:07.46#ibcon#about to read 4, iclass 19, count 0 2006.169.07:44:07.46#ibcon#read 4, iclass 19, count 0 2006.169.07:44:07.46#ibcon#about to read 5, iclass 19, count 0 2006.169.07:44:07.46#ibcon#read 5, iclass 19, count 0 2006.169.07:44:07.46#ibcon#about to read 6, iclass 19, count 0 2006.169.07:44:07.46#ibcon#read 6, iclass 19, count 0 2006.169.07:44:07.46#ibcon#end of sib2, iclass 19, count 0 2006.169.07:44:07.46#ibcon#*mode == 0, iclass 19, count 0 2006.169.07:44:07.46#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.169.07:44:07.46#ibcon#[25=USB\r\n] 2006.169.07:44:07.46#ibcon#*before write, iclass 19, count 0 2006.169.07:44:07.46#ibcon#enter sib2, iclass 19, count 0 2006.169.07:44:07.46#ibcon#flushed, iclass 19, count 0 2006.169.07:44:07.46#ibcon#about to write, iclass 19, count 0 2006.169.07:44:07.46#ibcon#wrote, iclass 19, count 0 2006.169.07:44:07.46#ibcon#about to read 3, iclass 19, count 0 2006.169.07:44:07.49#ibcon#read 3, iclass 19, count 0 2006.169.07:44:07.49#ibcon#about to read 4, iclass 19, count 0 2006.169.07:44:07.49#ibcon#read 4, iclass 19, count 0 2006.169.07:44:07.49#ibcon#about to read 5, iclass 19, count 0 2006.169.07:44:07.49#ibcon#read 5, iclass 19, count 0 2006.169.07:44:07.49#ibcon#about to read 6, iclass 19, count 0 2006.169.07:44:07.49#ibcon#read 6, iclass 19, count 0 2006.169.07:44:07.49#ibcon#end of sib2, iclass 19, count 0 2006.169.07:44:07.49#ibcon#*after write, iclass 19, count 0 2006.169.07:44:07.49#ibcon#*before return 0, iclass 19, count 0 2006.169.07:44:07.49#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:44:07.49#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:44:07.49#ibcon#about to clear, iclass 19 cls_cnt 0 2006.169.07:44:07.49#ibcon#cleared, iclass 19 cls_cnt 0 2006.169.07:44:07.49$vc4f8/vblo=1,632.99 2006.169.07:44:07.49#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.169.07:44:07.49#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.169.07:44:07.49#ibcon#ireg 17 cls_cnt 0 2006.169.07:44:07.49#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:44:07.49#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:44:07.49#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:44:07.49#ibcon#enter wrdev, iclass 21, count 0 2006.169.07:44:07.49#ibcon#first serial, iclass 21, count 0 2006.169.07:44:07.49#ibcon#enter sib2, iclass 21, count 0 2006.169.07:44:07.49#ibcon#flushed, iclass 21, count 0 2006.169.07:44:07.49#ibcon#about to write, iclass 21, count 0 2006.169.07:44:07.49#ibcon#wrote, iclass 21, count 0 2006.169.07:44:07.49#ibcon#about to read 3, iclass 21, count 0 2006.169.07:44:07.51#ibcon#read 3, iclass 21, count 0 2006.169.07:44:07.51#ibcon#about to read 4, iclass 21, count 0 2006.169.07:44:07.51#ibcon#read 4, iclass 21, count 0 2006.169.07:44:07.51#ibcon#about to read 5, iclass 21, count 0 2006.169.07:44:07.51#ibcon#read 5, iclass 21, count 0 2006.169.07:44:07.51#ibcon#about to read 6, iclass 21, count 0 2006.169.07:44:07.51#ibcon#read 6, iclass 21, count 0 2006.169.07:44:07.51#ibcon#end of sib2, iclass 21, count 0 2006.169.07:44:07.51#ibcon#*mode == 0, iclass 21, count 0 2006.169.07:44:07.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.169.07:44:07.51#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.07:44:07.51#ibcon#*before write, iclass 21, count 0 2006.169.07:44:07.51#ibcon#enter sib2, iclass 21, count 0 2006.169.07:44:07.51#ibcon#flushed, iclass 21, count 0 2006.169.07:44:07.51#ibcon#about to write, iclass 21, count 0 2006.169.07:44:07.51#ibcon#wrote, iclass 21, count 0 2006.169.07:44:07.51#ibcon#about to read 3, iclass 21, count 0 2006.169.07:44:07.55#ibcon#read 3, iclass 21, count 0 2006.169.07:44:07.55#ibcon#about to read 4, iclass 21, count 0 2006.169.07:44:07.55#ibcon#read 4, iclass 21, count 0 2006.169.07:44:07.55#ibcon#about to read 5, iclass 21, count 0 2006.169.07:44:07.55#ibcon#read 5, iclass 21, count 0 2006.169.07:44:07.55#ibcon#about to read 6, iclass 21, count 0 2006.169.07:44:07.55#ibcon#read 6, iclass 21, count 0 2006.169.07:44:07.55#ibcon#end of sib2, iclass 21, count 0 2006.169.07:44:07.55#ibcon#*after write, iclass 21, count 0 2006.169.07:44:07.55#ibcon#*before return 0, iclass 21, count 0 2006.169.07:44:07.55#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:44:07.55#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:44:07.55#ibcon#about to clear, iclass 21 cls_cnt 0 2006.169.07:44:07.55#ibcon#cleared, iclass 21 cls_cnt 0 2006.169.07:44:07.55$vc4f8/vb=1,4 2006.169.07:44:07.55#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.169.07:44:07.55#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.169.07:44:07.55#ibcon#ireg 11 cls_cnt 2 2006.169.07:44:07.55#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.169.07:44:07.55#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.169.07:44:07.55#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.169.07:44:07.55#ibcon#enter wrdev, iclass 23, count 2 2006.169.07:44:07.55#ibcon#first serial, iclass 23, count 2 2006.169.07:44:07.55#ibcon#enter sib2, iclass 23, count 2 2006.169.07:44:07.55#ibcon#flushed, iclass 23, count 2 2006.169.07:44:07.55#ibcon#about to write, iclass 23, count 2 2006.169.07:44:07.55#ibcon#wrote, iclass 23, count 2 2006.169.07:44:07.55#ibcon#about to read 3, iclass 23, count 2 2006.169.07:44:07.57#ibcon#read 3, iclass 23, count 2 2006.169.07:44:07.57#ibcon#about to read 4, iclass 23, count 2 2006.169.07:44:07.57#ibcon#read 4, iclass 23, count 2 2006.169.07:44:07.57#ibcon#about to read 5, iclass 23, count 2 2006.169.07:44:07.57#ibcon#read 5, iclass 23, count 2 2006.169.07:44:07.57#ibcon#about to read 6, iclass 23, count 2 2006.169.07:44:07.57#ibcon#read 6, iclass 23, count 2 2006.169.07:44:07.57#ibcon#end of sib2, iclass 23, count 2 2006.169.07:44:07.57#ibcon#*mode == 0, iclass 23, count 2 2006.169.07:44:07.57#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.169.07:44:07.57#ibcon#[27=AT01-04\r\n] 2006.169.07:44:07.57#ibcon#*before write, iclass 23, count 2 2006.169.07:44:07.57#ibcon#enter sib2, iclass 23, count 2 2006.169.07:44:07.57#ibcon#flushed, iclass 23, count 2 2006.169.07:44:07.57#ibcon#about to write, iclass 23, count 2 2006.169.07:44:07.57#ibcon#wrote, iclass 23, count 2 2006.169.07:44:07.57#ibcon#about to read 3, iclass 23, count 2 2006.169.07:44:07.60#ibcon#read 3, iclass 23, count 2 2006.169.07:44:07.60#ibcon#about to read 4, iclass 23, count 2 2006.169.07:44:07.60#ibcon#read 4, iclass 23, count 2 2006.169.07:44:07.60#ibcon#about to read 5, iclass 23, count 2 2006.169.07:44:07.60#ibcon#read 5, iclass 23, count 2 2006.169.07:44:07.60#ibcon#about to read 6, iclass 23, count 2 2006.169.07:44:07.60#ibcon#read 6, iclass 23, count 2 2006.169.07:44:07.60#ibcon#end of sib2, iclass 23, count 2 2006.169.07:44:07.60#ibcon#*after write, iclass 23, count 2 2006.169.07:44:07.60#ibcon#*before return 0, iclass 23, count 2 2006.169.07:44:07.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.169.07:44:07.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.169.07:44:07.60#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.169.07:44:07.60#ibcon#ireg 7 cls_cnt 0 2006.169.07:44:07.60#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.169.07:44:07.72#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.169.07:44:07.72#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.169.07:44:07.72#ibcon#enter wrdev, iclass 23, count 0 2006.169.07:44:07.72#ibcon#first serial, iclass 23, count 0 2006.169.07:44:07.72#ibcon#enter sib2, iclass 23, count 0 2006.169.07:44:07.72#ibcon#flushed, iclass 23, count 0 2006.169.07:44:07.72#ibcon#about to write, iclass 23, count 0 2006.169.07:44:07.72#ibcon#wrote, iclass 23, count 0 2006.169.07:44:07.72#ibcon#about to read 3, iclass 23, count 0 2006.169.07:44:07.74#ibcon#read 3, iclass 23, count 0 2006.169.07:44:07.74#ibcon#about to read 4, iclass 23, count 0 2006.169.07:44:07.74#ibcon#read 4, iclass 23, count 0 2006.169.07:44:07.74#ibcon#about to read 5, iclass 23, count 0 2006.169.07:44:07.74#ibcon#read 5, iclass 23, count 0 2006.169.07:44:07.74#ibcon#about to read 6, iclass 23, count 0 2006.169.07:44:07.74#ibcon#read 6, iclass 23, count 0 2006.169.07:44:07.74#ibcon#end of sib2, iclass 23, count 0 2006.169.07:44:07.74#ibcon#*mode == 0, iclass 23, count 0 2006.169.07:44:07.74#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.169.07:44:07.74#ibcon#[27=USB\r\n] 2006.169.07:44:07.74#ibcon#*before write, iclass 23, count 0 2006.169.07:44:07.74#ibcon#enter sib2, iclass 23, count 0 2006.169.07:44:07.74#ibcon#flushed, iclass 23, count 0 2006.169.07:44:07.74#ibcon#about to write, iclass 23, count 0 2006.169.07:44:07.74#ibcon#wrote, iclass 23, count 0 2006.169.07:44:07.74#ibcon#about to read 3, iclass 23, count 0 2006.169.07:44:07.77#ibcon#read 3, iclass 23, count 0 2006.169.07:44:07.77#ibcon#about to read 4, iclass 23, count 0 2006.169.07:44:07.77#ibcon#read 4, iclass 23, count 0 2006.169.07:44:07.77#ibcon#about to read 5, iclass 23, count 0 2006.169.07:44:07.77#ibcon#read 5, iclass 23, count 0 2006.169.07:44:07.77#ibcon#about to read 6, iclass 23, count 0 2006.169.07:44:07.77#ibcon#read 6, iclass 23, count 0 2006.169.07:44:07.77#ibcon#end of sib2, iclass 23, count 0 2006.169.07:44:07.77#ibcon#*after write, iclass 23, count 0 2006.169.07:44:07.77#ibcon#*before return 0, iclass 23, count 0 2006.169.07:44:07.77#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.169.07:44:07.77#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.169.07:44:07.77#ibcon#about to clear, iclass 23 cls_cnt 0 2006.169.07:44:07.77#ibcon#cleared, iclass 23 cls_cnt 0 2006.169.07:44:07.77$vc4f8/vblo=2,640.99 2006.169.07:44:07.77#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.169.07:44:07.77#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.169.07:44:07.77#ibcon#ireg 17 cls_cnt 0 2006.169.07:44:07.77#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:44:07.77#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:44:07.77#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:44:07.77#ibcon#enter wrdev, iclass 25, count 0 2006.169.07:44:07.77#ibcon#first serial, iclass 25, count 0 2006.169.07:44:07.77#ibcon#enter sib2, iclass 25, count 0 2006.169.07:44:07.77#ibcon#flushed, iclass 25, count 0 2006.169.07:44:07.77#ibcon#about to write, iclass 25, count 0 2006.169.07:44:07.77#ibcon#wrote, iclass 25, count 0 2006.169.07:44:07.77#ibcon#about to read 3, iclass 25, count 0 2006.169.07:44:07.79#ibcon#read 3, iclass 25, count 0 2006.169.07:44:07.79#ibcon#about to read 4, iclass 25, count 0 2006.169.07:44:07.79#ibcon#read 4, iclass 25, count 0 2006.169.07:44:07.79#ibcon#about to read 5, iclass 25, count 0 2006.169.07:44:07.79#ibcon#read 5, iclass 25, count 0 2006.169.07:44:07.79#ibcon#about to read 6, iclass 25, count 0 2006.169.07:44:07.79#ibcon#read 6, iclass 25, count 0 2006.169.07:44:07.79#ibcon#end of sib2, iclass 25, count 0 2006.169.07:44:07.79#ibcon#*mode == 0, iclass 25, count 0 2006.169.07:44:07.79#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.169.07:44:07.79#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.07:44:07.79#ibcon#*before write, iclass 25, count 0 2006.169.07:44:07.79#ibcon#enter sib2, iclass 25, count 0 2006.169.07:44:07.79#ibcon#flushed, iclass 25, count 0 2006.169.07:44:07.79#ibcon#about to write, iclass 25, count 0 2006.169.07:44:07.79#ibcon#wrote, iclass 25, count 0 2006.169.07:44:07.79#ibcon#about to read 3, iclass 25, count 0 2006.169.07:44:07.84#ibcon#read 3, iclass 25, count 0 2006.169.07:44:07.84#ibcon#about to read 4, iclass 25, count 0 2006.169.07:44:07.84#ibcon#read 4, iclass 25, count 0 2006.169.07:44:07.84#ibcon#about to read 5, iclass 25, count 0 2006.169.07:44:07.84#ibcon#read 5, iclass 25, count 0 2006.169.07:44:07.84#ibcon#about to read 6, iclass 25, count 0 2006.169.07:44:07.84#ibcon#read 6, iclass 25, count 0 2006.169.07:44:07.84#ibcon#end of sib2, iclass 25, count 0 2006.169.07:44:07.84#ibcon#*after write, iclass 25, count 0 2006.169.07:44:07.84#ibcon#*before return 0, iclass 25, count 0 2006.169.07:44:07.84#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:44:07.84#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:44:07.84#ibcon#about to clear, iclass 25 cls_cnt 0 2006.169.07:44:07.84#ibcon#cleared, iclass 25 cls_cnt 0 2006.169.07:44:07.84$vc4f8/vb=2,4 2006.169.07:44:07.84#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.169.07:44:07.84#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.169.07:44:07.84#ibcon#ireg 11 cls_cnt 2 2006.169.07:44:07.84#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.169.07:44:07.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.169.07:44:07.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.169.07:44:07.88#ibcon#enter wrdev, iclass 27, count 2 2006.169.07:44:07.88#ibcon#first serial, iclass 27, count 2 2006.169.07:44:07.88#ibcon#enter sib2, iclass 27, count 2 2006.169.07:44:07.88#ibcon#flushed, iclass 27, count 2 2006.169.07:44:07.88#ibcon#about to write, iclass 27, count 2 2006.169.07:44:07.88#ibcon#wrote, iclass 27, count 2 2006.169.07:44:07.88#ibcon#about to read 3, iclass 27, count 2 2006.169.07:44:07.90#ibcon#read 3, iclass 27, count 2 2006.169.07:44:07.90#ibcon#about to read 4, iclass 27, count 2 2006.169.07:44:07.90#ibcon#read 4, iclass 27, count 2 2006.169.07:44:07.90#ibcon#about to read 5, iclass 27, count 2 2006.169.07:44:07.90#ibcon#read 5, iclass 27, count 2 2006.169.07:44:07.90#ibcon#about to read 6, iclass 27, count 2 2006.169.07:44:07.90#ibcon#read 6, iclass 27, count 2 2006.169.07:44:07.90#ibcon#end of sib2, iclass 27, count 2 2006.169.07:44:07.90#ibcon#*mode == 0, iclass 27, count 2 2006.169.07:44:07.90#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.169.07:44:07.90#ibcon#[27=AT02-04\r\n] 2006.169.07:44:07.90#ibcon#*before write, iclass 27, count 2 2006.169.07:44:07.90#ibcon#enter sib2, iclass 27, count 2 2006.169.07:44:07.90#ibcon#flushed, iclass 27, count 2 2006.169.07:44:07.90#ibcon#about to write, iclass 27, count 2 2006.169.07:44:07.90#ibcon#wrote, iclass 27, count 2 2006.169.07:44:07.90#ibcon#about to read 3, iclass 27, count 2 2006.169.07:44:07.93#ibcon#read 3, iclass 27, count 2 2006.169.07:44:07.93#ibcon#about to read 4, iclass 27, count 2 2006.169.07:44:07.93#ibcon#read 4, iclass 27, count 2 2006.169.07:44:07.93#ibcon#about to read 5, iclass 27, count 2 2006.169.07:44:07.93#ibcon#read 5, iclass 27, count 2 2006.169.07:44:07.93#ibcon#about to read 6, iclass 27, count 2 2006.169.07:44:07.93#ibcon#read 6, iclass 27, count 2 2006.169.07:44:07.93#ibcon#end of sib2, iclass 27, count 2 2006.169.07:44:07.93#ibcon#*after write, iclass 27, count 2 2006.169.07:44:07.93#ibcon#*before return 0, iclass 27, count 2 2006.169.07:44:07.93#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.169.07:44:07.93#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.169.07:44:07.93#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.169.07:44:07.93#ibcon#ireg 7 cls_cnt 0 2006.169.07:44:07.93#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.169.07:44:08.05#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.169.07:44:08.05#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.169.07:44:08.05#ibcon#enter wrdev, iclass 27, count 0 2006.169.07:44:08.05#ibcon#first serial, iclass 27, count 0 2006.169.07:44:08.05#ibcon#enter sib2, iclass 27, count 0 2006.169.07:44:08.05#ibcon#flushed, iclass 27, count 0 2006.169.07:44:08.05#ibcon#about to write, iclass 27, count 0 2006.169.07:44:08.05#ibcon#wrote, iclass 27, count 0 2006.169.07:44:08.05#ibcon#about to read 3, iclass 27, count 0 2006.169.07:44:08.07#ibcon#read 3, iclass 27, count 0 2006.169.07:44:08.07#ibcon#about to read 4, iclass 27, count 0 2006.169.07:44:08.07#ibcon#read 4, iclass 27, count 0 2006.169.07:44:08.07#ibcon#about to read 5, iclass 27, count 0 2006.169.07:44:08.07#ibcon#read 5, iclass 27, count 0 2006.169.07:44:08.07#ibcon#about to read 6, iclass 27, count 0 2006.169.07:44:08.07#ibcon#read 6, iclass 27, count 0 2006.169.07:44:08.07#ibcon#end of sib2, iclass 27, count 0 2006.169.07:44:08.07#ibcon#*mode == 0, iclass 27, count 0 2006.169.07:44:08.07#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.169.07:44:08.07#ibcon#[27=USB\r\n] 2006.169.07:44:08.07#ibcon#*before write, iclass 27, count 0 2006.169.07:44:08.07#ibcon#enter sib2, iclass 27, count 0 2006.169.07:44:08.07#ibcon#flushed, iclass 27, count 0 2006.169.07:44:08.07#ibcon#about to write, iclass 27, count 0 2006.169.07:44:08.07#ibcon#wrote, iclass 27, count 0 2006.169.07:44:08.07#ibcon#about to read 3, iclass 27, count 0 2006.169.07:44:08.10#ibcon#read 3, iclass 27, count 0 2006.169.07:44:08.10#ibcon#about to read 4, iclass 27, count 0 2006.169.07:44:08.10#ibcon#read 4, iclass 27, count 0 2006.169.07:44:08.10#ibcon#about to read 5, iclass 27, count 0 2006.169.07:44:08.10#ibcon#read 5, iclass 27, count 0 2006.169.07:44:08.10#ibcon#about to read 6, iclass 27, count 0 2006.169.07:44:08.10#ibcon#read 6, iclass 27, count 0 2006.169.07:44:08.10#ibcon#end of sib2, iclass 27, count 0 2006.169.07:44:08.10#ibcon#*after write, iclass 27, count 0 2006.169.07:44:08.10#ibcon#*before return 0, iclass 27, count 0 2006.169.07:44:08.10#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.169.07:44:08.10#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.169.07:44:08.10#ibcon#about to clear, iclass 27 cls_cnt 0 2006.169.07:44:08.10#ibcon#cleared, iclass 27 cls_cnt 0 2006.169.07:44:08.10$vc4f8/vblo=3,656.99 2006.169.07:44:08.10#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.169.07:44:08.10#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.169.07:44:08.10#ibcon#ireg 17 cls_cnt 0 2006.169.07:44:08.10#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:44:08.10#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:44:08.10#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:44:08.10#ibcon#enter wrdev, iclass 30, count 0 2006.169.07:44:08.10#ibcon#first serial, iclass 30, count 0 2006.169.07:44:08.10#ibcon#enter sib2, iclass 30, count 0 2006.169.07:44:08.10#ibcon#flushed, iclass 30, count 0 2006.169.07:44:08.10#ibcon#about to write, iclass 30, count 0 2006.169.07:44:08.10#ibcon#wrote, iclass 30, count 0 2006.169.07:44:08.10#ibcon#about to read 3, iclass 30, count 0 2006.169.07:44:08.12#ibcon#read 3, iclass 30, count 0 2006.169.07:44:08.12#ibcon#about to read 4, iclass 30, count 0 2006.169.07:44:08.12#ibcon#read 4, iclass 30, count 0 2006.169.07:44:08.12#ibcon#about to read 5, iclass 30, count 0 2006.169.07:44:08.12#ibcon#read 5, iclass 30, count 0 2006.169.07:44:08.12#ibcon#about to read 6, iclass 30, count 0 2006.169.07:44:08.12#ibcon#read 6, iclass 30, count 0 2006.169.07:44:08.12#ibcon#end of sib2, iclass 30, count 0 2006.169.07:44:08.12#ibcon#*mode == 0, iclass 30, count 0 2006.169.07:44:08.12#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.169.07:44:08.12#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.07:44:08.12#ibcon#*before write, iclass 30, count 0 2006.169.07:44:08.12#ibcon#enter sib2, iclass 30, count 0 2006.169.07:44:08.12#ibcon#flushed, iclass 30, count 0 2006.169.07:44:08.12#ibcon#about to write, iclass 30, count 0 2006.169.07:44:08.12#ibcon#wrote, iclass 30, count 0 2006.169.07:44:08.12#ibcon#about to read 3, iclass 30, count 0 2006.169.07:44:08.16#ibcon#read 3, iclass 30, count 0 2006.169.07:44:08.16#ibcon#about to read 4, iclass 30, count 0 2006.169.07:44:08.16#ibcon#read 4, iclass 30, count 0 2006.169.07:44:08.16#ibcon#about to read 5, iclass 30, count 0 2006.169.07:44:08.16#ibcon#read 5, iclass 30, count 0 2006.169.07:44:08.16#ibcon#about to read 6, iclass 30, count 0 2006.169.07:44:08.16#ibcon#read 6, iclass 30, count 0 2006.169.07:44:08.16#ibcon#end of sib2, iclass 30, count 0 2006.169.07:44:08.16#ibcon#*after write, iclass 30, count 0 2006.169.07:44:08.16#ibcon#*before return 0, iclass 30, count 0 2006.169.07:44:08.16#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:44:08.16#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:44:08.16#ibcon#about to clear, iclass 30 cls_cnt 0 2006.169.07:44:08.16#ibcon#cleared, iclass 30 cls_cnt 0 2006.169.07:44:08.16$vc4f8/vb=3,4 2006.169.07:44:08.16#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.169.07:44:08.16#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.169.07:44:08.16#ibcon#ireg 11 cls_cnt 2 2006.169.07:44:08.16#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:44:08.22#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:44:08.22#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:44:08.22#ibcon#enter wrdev, iclass 32, count 2 2006.169.07:44:08.22#ibcon#first serial, iclass 32, count 2 2006.169.07:44:08.22#ibcon#enter sib2, iclass 32, count 2 2006.169.07:44:08.22#ibcon#flushed, iclass 32, count 2 2006.169.07:44:08.22#ibcon#about to write, iclass 32, count 2 2006.169.07:44:08.22#ibcon#wrote, iclass 32, count 2 2006.169.07:44:08.22#ibcon#about to read 3, iclass 32, count 2 2006.169.07:44:08.24#ibcon#read 3, iclass 32, count 2 2006.169.07:44:08.24#ibcon#about to read 4, iclass 32, count 2 2006.169.07:44:08.24#ibcon#read 4, iclass 32, count 2 2006.169.07:44:08.24#ibcon#about to read 5, iclass 32, count 2 2006.169.07:44:08.24#ibcon#read 5, iclass 32, count 2 2006.169.07:44:08.24#ibcon#about to read 6, iclass 32, count 2 2006.169.07:44:08.24#ibcon#read 6, iclass 32, count 2 2006.169.07:44:08.24#ibcon#end of sib2, iclass 32, count 2 2006.169.07:44:08.24#ibcon#*mode == 0, iclass 32, count 2 2006.169.07:44:08.24#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.169.07:44:08.24#ibcon#[27=AT03-04\r\n] 2006.169.07:44:08.24#ibcon#*before write, iclass 32, count 2 2006.169.07:44:08.24#ibcon#enter sib2, iclass 32, count 2 2006.169.07:44:08.24#ibcon#flushed, iclass 32, count 2 2006.169.07:44:08.24#ibcon#about to write, iclass 32, count 2 2006.169.07:44:08.24#ibcon#wrote, iclass 32, count 2 2006.169.07:44:08.24#ibcon#about to read 3, iclass 32, count 2 2006.169.07:44:08.27#ibcon#read 3, iclass 32, count 2 2006.169.07:44:08.27#ibcon#about to read 4, iclass 32, count 2 2006.169.07:44:08.27#ibcon#read 4, iclass 32, count 2 2006.169.07:44:08.27#ibcon#about to read 5, iclass 32, count 2 2006.169.07:44:08.27#ibcon#read 5, iclass 32, count 2 2006.169.07:44:08.27#ibcon#about to read 6, iclass 32, count 2 2006.169.07:44:08.27#ibcon#read 6, iclass 32, count 2 2006.169.07:44:08.27#ibcon#end of sib2, iclass 32, count 2 2006.169.07:44:08.27#ibcon#*after write, iclass 32, count 2 2006.169.07:44:08.27#ibcon#*before return 0, iclass 32, count 2 2006.169.07:44:08.27#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:44:08.27#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:44:08.27#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.169.07:44:08.27#ibcon#ireg 7 cls_cnt 0 2006.169.07:44:08.27#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:44:08.30#abcon#<5=/05 3.4 7.0 18.131001003.8\r\n> 2006.169.07:44:08.32#abcon#{5=INTERFACE CLEAR} 2006.169.07:44:08.38#abcon#[5=S1D000X0/0*\r\n] 2006.169.07:44:08.39#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:44:08.39#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:44:08.39#ibcon#enter wrdev, iclass 32, count 0 2006.169.07:44:08.39#ibcon#first serial, iclass 32, count 0 2006.169.07:44:08.39#ibcon#enter sib2, iclass 32, count 0 2006.169.07:44:08.39#ibcon#flushed, iclass 32, count 0 2006.169.07:44:08.39#ibcon#about to write, iclass 32, count 0 2006.169.07:44:08.39#ibcon#wrote, iclass 32, count 0 2006.169.07:44:08.39#ibcon#about to read 3, iclass 32, count 0 2006.169.07:44:08.41#ibcon#read 3, iclass 32, count 0 2006.169.07:44:08.41#ibcon#about to read 4, iclass 32, count 0 2006.169.07:44:08.41#ibcon#read 4, iclass 32, count 0 2006.169.07:44:08.41#ibcon#about to read 5, iclass 32, count 0 2006.169.07:44:08.41#ibcon#read 5, iclass 32, count 0 2006.169.07:44:08.41#ibcon#about to read 6, iclass 32, count 0 2006.169.07:44:08.41#ibcon#read 6, iclass 32, count 0 2006.169.07:44:08.41#ibcon#end of sib2, iclass 32, count 0 2006.169.07:44:08.41#ibcon#*mode == 0, iclass 32, count 0 2006.169.07:44:08.41#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.169.07:44:08.41#ibcon#[27=USB\r\n] 2006.169.07:44:08.41#ibcon#*before write, iclass 32, count 0 2006.169.07:44:08.41#ibcon#enter sib2, iclass 32, count 0 2006.169.07:44:08.41#ibcon#flushed, iclass 32, count 0 2006.169.07:44:08.41#ibcon#about to write, iclass 32, count 0 2006.169.07:44:08.41#ibcon#wrote, iclass 32, count 0 2006.169.07:44:08.41#ibcon#about to read 3, iclass 32, count 0 2006.169.07:44:08.44#ibcon#read 3, iclass 32, count 0 2006.169.07:44:08.44#ibcon#about to read 4, iclass 32, count 0 2006.169.07:44:08.44#ibcon#read 4, iclass 32, count 0 2006.169.07:44:08.44#ibcon#about to read 5, iclass 32, count 0 2006.169.07:44:08.44#ibcon#read 5, iclass 32, count 0 2006.169.07:44:08.44#ibcon#about to read 6, iclass 32, count 0 2006.169.07:44:08.44#ibcon#read 6, iclass 32, count 0 2006.169.07:44:08.44#ibcon#end of sib2, iclass 32, count 0 2006.169.07:44:08.44#ibcon#*after write, iclass 32, count 0 2006.169.07:44:08.44#ibcon#*before return 0, iclass 32, count 0 2006.169.07:44:08.44#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:44:08.44#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:44:08.44#ibcon#about to clear, iclass 32 cls_cnt 0 2006.169.07:44:08.44#ibcon#cleared, iclass 32 cls_cnt 0 2006.169.07:44:08.44$vc4f8/vblo=4,712.99 2006.169.07:44:08.44#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.169.07:44:08.44#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.169.07:44:08.44#ibcon#ireg 17 cls_cnt 0 2006.169.07:44:08.44#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:44:08.44#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:44:08.44#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:44:08.44#ibcon#enter wrdev, iclass 37, count 0 2006.169.07:44:08.44#ibcon#first serial, iclass 37, count 0 2006.169.07:44:08.44#ibcon#enter sib2, iclass 37, count 0 2006.169.07:44:08.44#ibcon#flushed, iclass 37, count 0 2006.169.07:44:08.44#ibcon#about to write, iclass 37, count 0 2006.169.07:44:08.44#ibcon#wrote, iclass 37, count 0 2006.169.07:44:08.44#ibcon#about to read 3, iclass 37, count 0 2006.169.07:44:08.46#ibcon#read 3, iclass 37, count 0 2006.169.07:44:08.46#ibcon#about to read 4, iclass 37, count 0 2006.169.07:44:08.46#ibcon#read 4, iclass 37, count 0 2006.169.07:44:08.46#ibcon#about to read 5, iclass 37, count 0 2006.169.07:44:08.46#ibcon#read 5, iclass 37, count 0 2006.169.07:44:08.46#ibcon#about to read 6, iclass 37, count 0 2006.169.07:44:08.46#ibcon#read 6, iclass 37, count 0 2006.169.07:44:08.46#ibcon#end of sib2, iclass 37, count 0 2006.169.07:44:08.46#ibcon#*mode == 0, iclass 37, count 0 2006.169.07:44:08.46#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.169.07:44:08.46#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.07:44:08.46#ibcon#*before write, iclass 37, count 0 2006.169.07:44:08.46#ibcon#enter sib2, iclass 37, count 0 2006.169.07:44:08.46#ibcon#flushed, iclass 37, count 0 2006.169.07:44:08.46#ibcon#about to write, iclass 37, count 0 2006.169.07:44:08.46#ibcon#wrote, iclass 37, count 0 2006.169.07:44:08.46#ibcon#about to read 3, iclass 37, count 0 2006.169.07:44:08.50#ibcon#read 3, iclass 37, count 0 2006.169.07:44:08.50#ibcon#about to read 4, iclass 37, count 0 2006.169.07:44:08.50#ibcon#read 4, iclass 37, count 0 2006.169.07:44:08.50#ibcon#about to read 5, iclass 37, count 0 2006.169.07:44:08.50#ibcon#read 5, iclass 37, count 0 2006.169.07:44:08.50#ibcon#about to read 6, iclass 37, count 0 2006.169.07:44:08.50#ibcon#read 6, iclass 37, count 0 2006.169.07:44:08.50#ibcon#end of sib2, iclass 37, count 0 2006.169.07:44:08.50#ibcon#*after write, iclass 37, count 0 2006.169.07:44:08.50#ibcon#*before return 0, iclass 37, count 0 2006.169.07:44:08.50#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:44:08.50#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:44:08.50#ibcon#about to clear, iclass 37 cls_cnt 0 2006.169.07:44:08.50#ibcon#cleared, iclass 37 cls_cnt 0 2006.169.07:44:08.50$vc4f8/vb=4,4 2006.169.07:44:08.50#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.169.07:44:08.50#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.169.07:44:08.50#ibcon#ireg 11 cls_cnt 2 2006.169.07:44:08.50#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:44:08.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:44:08.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:44:08.57#ibcon#enter wrdev, iclass 39, count 2 2006.169.07:44:08.57#ibcon#first serial, iclass 39, count 2 2006.169.07:44:08.57#ibcon#enter sib2, iclass 39, count 2 2006.169.07:44:08.57#ibcon#flushed, iclass 39, count 2 2006.169.07:44:08.57#ibcon#about to write, iclass 39, count 2 2006.169.07:44:08.57#ibcon#wrote, iclass 39, count 2 2006.169.07:44:08.57#ibcon#about to read 3, iclass 39, count 2 2006.169.07:44:08.58#ibcon#read 3, iclass 39, count 2 2006.169.07:44:08.58#ibcon#about to read 4, iclass 39, count 2 2006.169.07:44:08.58#ibcon#read 4, iclass 39, count 2 2006.169.07:44:08.58#ibcon#about to read 5, iclass 39, count 2 2006.169.07:44:08.58#ibcon#read 5, iclass 39, count 2 2006.169.07:44:08.58#ibcon#about to read 6, iclass 39, count 2 2006.169.07:44:08.58#ibcon#read 6, iclass 39, count 2 2006.169.07:44:08.58#ibcon#end of sib2, iclass 39, count 2 2006.169.07:44:08.58#ibcon#*mode == 0, iclass 39, count 2 2006.169.07:44:08.58#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.169.07:44:08.58#ibcon#[27=AT04-04\r\n] 2006.169.07:44:08.58#ibcon#*before write, iclass 39, count 2 2006.169.07:44:08.58#ibcon#enter sib2, iclass 39, count 2 2006.169.07:44:08.58#ibcon#flushed, iclass 39, count 2 2006.169.07:44:08.58#ibcon#about to write, iclass 39, count 2 2006.169.07:44:08.58#ibcon#wrote, iclass 39, count 2 2006.169.07:44:08.58#ibcon#about to read 3, iclass 39, count 2 2006.169.07:44:08.61#ibcon#read 3, iclass 39, count 2 2006.169.07:44:08.61#ibcon#about to read 4, iclass 39, count 2 2006.169.07:44:08.61#ibcon#read 4, iclass 39, count 2 2006.169.07:44:08.61#ibcon#about to read 5, iclass 39, count 2 2006.169.07:44:08.61#ibcon#read 5, iclass 39, count 2 2006.169.07:44:08.61#ibcon#about to read 6, iclass 39, count 2 2006.169.07:44:08.61#ibcon#read 6, iclass 39, count 2 2006.169.07:44:08.61#ibcon#end of sib2, iclass 39, count 2 2006.169.07:44:08.61#ibcon#*after write, iclass 39, count 2 2006.169.07:44:08.61#ibcon#*before return 0, iclass 39, count 2 2006.169.07:44:08.61#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:44:08.61#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:44:08.61#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.169.07:44:08.61#ibcon#ireg 7 cls_cnt 0 2006.169.07:44:08.61#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:44:08.73#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:44:08.73#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:44:08.73#ibcon#enter wrdev, iclass 39, count 0 2006.169.07:44:08.73#ibcon#first serial, iclass 39, count 0 2006.169.07:44:08.73#ibcon#enter sib2, iclass 39, count 0 2006.169.07:44:08.73#ibcon#flushed, iclass 39, count 0 2006.169.07:44:08.73#ibcon#about to write, iclass 39, count 0 2006.169.07:44:08.73#ibcon#wrote, iclass 39, count 0 2006.169.07:44:08.73#ibcon#about to read 3, iclass 39, count 0 2006.169.07:44:08.75#ibcon#read 3, iclass 39, count 0 2006.169.07:44:08.75#ibcon#about to read 4, iclass 39, count 0 2006.169.07:44:08.75#ibcon#read 4, iclass 39, count 0 2006.169.07:44:08.75#ibcon#about to read 5, iclass 39, count 0 2006.169.07:44:08.75#ibcon#read 5, iclass 39, count 0 2006.169.07:44:08.75#ibcon#about to read 6, iclass 39, count 0 2006.169.07:44:08.75#ibcon#read 6, iclass 39, count 0 2006.169.07:44:08.75#ibcon#end of sib2, iclass 39, count 0 2006.169.07:44:08.75#ibcon#*mode == 0, iclass 39, count 0 2006.169.07:44:08.75#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.169.07:44:08.75#ibcon#[27=USB\r\n] 2006.169.07:44:08.75#ibcon#*before write, iclass 39, count 0 2006.169.07:44:08.75#ibcon#enter sib2, iclass 39, count 0 2006.169.07:44:08.75#ibcon#flushed, iclass 39, count 0 2006.169.07:44:08.75#ibcon#about to write, iclass 39, count 0 2006.169.07:44:08.75#ibcon#wrote, iclass 39, count 0 2006.169.07:44:08.75#ibcon#about to read 3, iclass 39, count 0 2006.169.07:44:08.78#ibcon#read 3, iclass 39, count 0 2006.169.07:44:08.78#ibcon#about to read 4, iclass 39, count 0 2006.169.07:44:08.78#ibcon#read 4, iclass 39, count 0 2006.169.07:44:08.78#ibcon#about to read 5, iclass 39, count 0 2006.169.07:44:08.78#ibcon#read 5, iclass 39, count 0 2006.169.07:44:08.78#ibcon#about to read 6, iclass 39, count 0 2006.169.07:44:08.78#ibcon#read 6, iclass 39, count 0 2006.169.07:44:08.78#ibcon#end of sib2, iclass 39, count 0 2006.169.07:44:08.78#ibcon#*after write, iclass 39, count 0 2006.169.07:44:08.78#ibcon#*before return 0, iclass 39, count 0 2006.169.07:44:08.78#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:44:08.78#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:44:08.78#ibcon#about to clear, iclass 39 cls_cnt 0 2006.169.07:44:08.78#ibcon#cleared, iclass 39 cls_cnt 0 2006.169.07:44:08.78$vc4f8/vblo=5,744.99 2006.169.07:44:08.78#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.169.07:44:08.78#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.169.07:44:08.78#ibcon#ireg 17 cls_cnt 0 2006.169.07:44:08.78#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:44:08.78#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:44:08.78#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:44:08.78#ibcon#enter wrdev, iclass 3, count 0 2006.169.07:44:08.78#ibcon#first serial, iclass 3, count 0 2006.169.07:44:08.78#ibcon#enter sib2, iclass 3, count 0 2006.169.07:44:08.78#ibcon#flushed, iclass 3, count 0 2006.169.07:44:08.78#ibcon#about to write, iclass 3, count 0 2006.169.07:44:08.78#ibcon#wrote, iclass 3, count 0 2006.169.07:44:08.78#ibcon#about to read 3, iclass 3, count 0 2006.169.07:44:08.80#ibcon#read 3, iclass 3, count 0 2006.169.07:44:08.80#ibcon#about to read 4, iclass 3, count 0 2006.169.07:44:08.80#ibcon#read 4, iclass 3, count 0 2006.169.07:44:08.80#ibcon#about to read 5, iclass 3, count 0 2006.169.07:44:08.80#ibcon#read 5, iclass 3, count 0 2006.169.07:44:08.80#ibcon#about to read 6, iclass 3, count 0 2006.169.07:44:08.80#ibcon#read 6, iclass 3, count 0 2006.169.07:44:08.80#ibcon#end of sib2, iclass 3, count 0 2006.169.07:44:08.80#ibcon#*mode == 0, iclass 3, count 0 2006.169.07:44:08.80#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.169.07:44:08.80#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.07:44:08.80#ibcon#*before write, iclass 3, count 0 2006.169.07:44:08.80#ibcon#enter sib2, iclass 3, count 0 2006.169.07:44:08.80#ibcon#flushed, iclass 3, count 0 2006.169.07:44:08.80#ibcon#about to write, iclass 3, count 0 2006.169.07:44:08.80#ibcon#wrote, iclass 3, count 0 2006.169.07:44:08.80#ibcon#about to read 3, iclass 3, count 0 2006.169.07:44:08.84#ibcon#read 3, iclass 3, count 0 2006.169.07:44:08.84#ibcon#about to read 4, iclass 3, count 0 2006.169.07:44:08.84#ibcon#read 4, iclass 3, count 0 2006.169.07:44:08.84#ibcon#about to read 5, iclass 3, count 0 2006.169.07:44:08.84#ibcon#read 5, iclass 3, count 0 2006.169.07:44:08.84#ibcon#about to read 6, iclass 3, count 0 2006.169.07:44:08.84#ibcon#read 6, iclass 3, count 0 2006.169.07:44:08.84#ibcon#end of sib2, iclass 3, count 0 2006.169.07:44:08.84#ibcon#*after write, iclass 3, count 0 2006.169.07:44:08.84#ibcon#*before return 0, iclass 3, count 0 2006.169.07:44:08.84#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:44:08.84#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:44:08.84#ibcon#about to clear, iclass 3 cls_cnt 0 2006.169.07:44:08.84#ibcon#cleared, iclass 3 cls_cnt 0 2006.169.07:44:08.84$vc4f8/vb=5,4 2006.169.07:44:08.84#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.169.07:44:08.84#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.169.07:44:08.84#ibcon#ireg 11 cls_cnt 2 2006.169.07:44:08.84#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:44:08.90#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:44:08.90#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:44:08.90#ibcon#enter wrdev, iclass 5, count 2 2006.169.07:44:08.90#ibcon#first serial, iclass 5, count 2 2006.169.07:44:08.90#ibcon#enter sib2, iclass 5, count 2 2006.169.07:44:08.90#ibcon#flushed, iclass 5, count 2 2006.169.07:44:08.90#ibcon#about to write, iclass 5, count 2 2006.169.07:44:08.90#ibcon#wrote, iclass 5, count 2 2006.169.07:44:08.90#ibcon#about to read 3, iclass 5, count 2 2006.169.07:44:08.92#ibcon#read 3, iclass 5, count 2 2006.169.07:44:08.92#ibcon#about to read 4, iclass 5, count 2 2006.169.07:44:08.92#ibcon#read 4, iclass 5, count 2 2006.169.07:44:08.92#ibcon#about to read 5, iclass 5, count 2 2006.169.07:44:08.92#ibcon#read 5, iclass 5, count 2 2006.169.07:44:08.92#ibcon#about to read 6, iclass 5, count 2 2006.169.07:44:08.92#ibcon#read 6, iclass 5, count 2 2006.169.07:44:08.92#ibcon#end of sib2, iclass 5, count 2 2006.169.07:44:08.92#ibcon#*mode == 0, iclass 5, count 2 2006.169.07:44:08.92#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.169.07:44:08.92#ibcon#[27=AT05-04\r\n] 2006.169.07:44:08.92#ibcon#*before write, iclass 5, count 2 2006.169.07:44:08.92#ibcon#enter sib2, iclass 5, count 2 2006.169.07:44:08.92#ibcon#flushed, iclass 5, count 2 2006.169.07:44:08.92#ibcon#about to write, iclass 5, count 2 2006.169.07:44:08.92#ibcon#wrote, iclass 5, count 2 2006.169.07:44:08.92#ibcon#about to read 3, iclass 5, count 2 2006.169.07:44:08.95#ibcon#read 3, iclass 5, count 2 2006.169.07:44:08.95#ibcon#about to read 4, iclass 5, count 2 2006.169.07:44:08.95#ibcon#read 4, iclass 5, count 2 2006.169.07:44:08.95#ibcon#about to read 5, iclass 5, count 2 2006.169.07:44:08.95#ibcon#read 5, iclass 5, count 2 2006.169.07:44:08.95#ibcon#about to read 6, iclass 5, count 2 2006.169.07:44:08.95#ibcon#read 6, iclass 5, count 2 2006.169.07:44:08.95#ibcon#end of sib2, iclass 5, count 2 2006.169.07:44:08.95#ibcon#*after write, iclass 5, count 2 2006.169.07:44:08.95#ibcon#*before return 0, iclass 5, count 2 2006.169.07:44:08.95#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:44:08.95#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:44:08.95#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.169.07:44:08.95#ibcon#ireg 7 cls_cnt 0 2006.169.07:44:08.95#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:44:09.07#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:44:09.07#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:44:09.07#ibcon#enter wrdev, iclass 5, count 0 2006.169.07:44:09.07#ibcon#first serial, iclass 5, count 0 2006.169.07:44:09.07#ibcon#enter sib2, iclass 5, count 0 2006.169.07:44:09.07#ibcon#flushed, iclass 5, count 0 2006.169.07:44:09.07#ibcon#about to write, iclass 5, count 0 2006.169.07:44:09.07#ibcon#wrote, iclass 5, count 0 2006.169.07:44:09.07#ibcon#about to read 3, iclass 5, count 0 2006.169.07:44:09.09#ibcon#read 3, iclass 5, count 0 2006.169.07:44:09.09#ibcon#about to read 4, iclass 5, count 0 2006.169.07:44:09.09#ibcon#read 4, iclass 5, count 0 2006.169.07:44:09.09#ibcon#about to read 5, iclass 5, count 0 2006.169.07:44:09.09#ibcon#read 5, iclass 5, count 0 2006.169.07:44:09.09#ibcon#about to read 6, iclass 5, count 0 2006.169.07:44:09.09#ibcon#read 6, iclass 5, count 0 2006.169.07:44:09.09#ibcon#end of sib2, iclass 5, count 0 2006.169.07:44:09.09#ibcon#*mode == 0, iclass 5, count 0 2006.169.07:44:09.09#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.169.07:44:09.09#ibcon#[27=USB\r\n] 2006.169.07:44:09.09#ibcon#*before write, iclass 5, count 0 2006.169.07:44:09.09#ibcon#enter sib2, iclass 5, count 0 2006.169.07:44:09.09#ibcon#flushed, iclass 5, count 0 2006.169.07:44:09.09#ibcon#about to write, iclass 5, count 0 2006.169.07:44:09.09#ibcon#wrote, iclass 5, count 0 2006.169.07:44:09.09#ibcon#about to read 3, iclass 5, count 0 2006.169.07:44:09.12#ibcon#read 3, iclass 5, count 0 2006.169.07:44:09.12#ibcon#about to read 4, iclass 5, count 0 2006.169.07:44:09.12#ibcon#read 4, iclass 5, count 0 2006.169.07:44:09.12#ibcon#about to read 5, iclass 5, count 0 2006.169.07:44:09.12#ibcon#read 5, iclass 5, count 0 2006.169.07:44:09.12#ibcon#about to read 6, iclass 5, count 0 2006.169.07:44:09.12#ibcon#read 6, iclass 5, count 0 2006.169.07:44:09.12#ibcon#end of sib2, iclass 5, count 0 2006.169.07:44:09.12#ibcon#*after write, iclass 5, count 0 2006.169.07:44:09.12#ibcon#*before return 0, iclass 5, count 0 2006.169.07:44:09.12#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:44:09.12#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:44:09.12#ibcon#about to clear, iclass 5 cls_cnt 0 2006.169.07:44:09.12#ibcon#cleared, iclass 5 cls_cnt 0 2006.169.07:44:09.12$vc4f8/vblo=6,752.99 2006.169.07:44:09.12#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.169.07:44:09.12#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.169.07:44:09.12#ibcon#ireg 17 cls_cnt 0 2006.169.07:44:09.12#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:44:09.12#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:44:09.12#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:44:09.12#ibcon#enter wrdev, iclass 7, count 0 2006.169.07:44:09.12#ibcon#first serial, iclass 7, count 0 2006.169.07:44:09.12#ibcon#enter sib2, iclass 7, count 0 2006.169.07:44:09.12#ibcon#flushed, iclass 7, count 0 2006.169.07:44:09.12#ibcon#about to write, iclass 7, count 0 2006.169.07:44:09.12#ibcon#wrote, iclass 7, count 0 2006.169.07:44:09.12#ibcon#about to read 3, iclass 7, count 0 2006.169.07:44:09.14#ibcon#read 3, iclass 7, count 0 2006.169.07:44:09.14#ibcon#about to read 4, iclass 7, count 0 2006.169.07:44:09.14#ibcon#read 4, iclass 7, count 0 2006.169.07:44:09.14#ibcon#about to read 5, iclass 7, count 0 2006.169.07:44:09.14#ibcon#read 5, iclass 7, count 0 2006.169.07:44:09.14#ibcon#about to read 6, iclass 7, count 0 2006.169.07:44:09.14#ibcon#read 6, iclass 7, count 0 2006.169.07:44:09.14#ibcon#end of sib2, iclass 7, count 0 2006.169.07:44:09.14#ibcon#*mode == 0, iclass 7, count 0 2006.169.07:44:09.14#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.169.07:44:09.14#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.07:44:09.14#ibcon#*before write, iclass 7, count 0 2006.169.07:44:09.14#ibcon#enter sib2, iclass 7, count 0 2006.169.07:44:09.14#ibcon#flushed, iclass 7, count 0 2006.169.07:44:09.14#ibcon#about to write, iclass 7, count 0 2006.169.07:44:09.14#ibcon#wrote, iclass 7, count 0 2006.169.07:44:09.14#ibcon#about to read 3, iclass 7, count 0 2006.169.07:44:09.18#ibcon#read 3, iclass 7, count 0 2006.169.07:44:09.18#ibcon#about to read 4, iclass 7, count 0 2006.169.07:44:09.18#ibcon#read 4, iclass 7, count 0 2006.169.07:44:09.18#ibcon#about to read 5, iclass 7, count 0 2006.169.07:44:09.18#ibcon#read 5, iclass 7, count 0 2006.169.07:44:09.18#ibcon#about to read 6, iclass 7, count 0 2006.169.07:44:09.18#ibcon#read 6, iclass 7, count 0 2006.169.07:44:09.18#ibcon#end of sib2, iclass 7, count 0 2006.169.07:44:09.18#ibcon#*after write, iclass 7, count 0 2006.169.07:44:09.18#ibcon#*before return 0, iclass 7, count 0 2006.169.07:44:09.18#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:44:09.18#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:44:09.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.169.07:44:09.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.169.07:44:09.18$vc4f8/vb=6,4 2006.169.07:44:09.18#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.169.07:44:09.18#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.169.07:44:09.18#ibcon#ireg 11 cls_cnt 2 2006.169.07:44:09.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:44:09.24#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:44:09.24#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:44:09.24#ibcon#enter wrdev, iclass 11, count 2 2006.169.07:44:09.24#ibcon#first serial, iclass 11, count 2 2006.169.07:44:09.24#ibcon#enter sib2, iclass 11, count 2 2006.169.07:44:09.24#ibcon#flushed, iclass 11, count 2 2006.169.07:44:09.24#ibcon#about to write, iclass 11, count 2 2006.169.07:44:09.24#ibcon#wrote, iclass 11, count 2 2006.169.07:44:09.24#ibcon#about to read 3, iclass 11, count 2 2006.169.07:44:09.26#ibcon#read 3, iclass 11, count 2 2006.169.07:44:09.26#ibcon#about to read 4, iclass 11, count 2 2006.169.07:44:09.26#ibcon#read 4, iclass 11, count 2 2006.169.07:44:09.26#ibcon#about to read 5, iclass 11, count 2 2006.169.07:44:09.26#ibcon#read 5, iclass 11, count 2 2006.169.07:44:09.26#ibcon#about to read 6, iclass 11, count 2 2006.169.07:44:09.26#ibcon#read 6, iclass 11, count 2 2006.169.07:44:09.26#ibcon#end of sib2, iclass 11, count 2 2006.169.07:44:09.26#ibcon#*mode == 0, iclass 11, count 2 2006.169.07:44:09.26#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.169.07:44:09.26#ibcon#[27=AT06-04\r\n] 2006.169.07:44:09.26#ibcon#*before write, iclass 11, count 2 2006.169.07:44:09.26#ibcon#enter sib2, iclass 11, count 2 2006.169.07:44:09.26#ibcon#flushed, iclass 11, count 2 2006.169.07:44:09.26#ibcon#about to write, iclass 11, count 2 2006.169.07:44:09.26#ibcon#wrote, iclass 11, count 2 2006.169.07:44:09.26#ibcon#about to read 3, iclass 11, count 2 2006.169.07:44:09.29#ibcon#read 3, iclass 11, count 2 2006.169.07:44:09.29#ibcon#about to read 4, iclass 11, count 2 2006.169.07:44:09.29#ibcon#read 4, iclass 11, count 2 2006.169.07:44:09.29#ibcon#about to read 5, iclass 11, count 2 2006.169.07:44:09.29#ibcon#read 5, iclass 11, count 2 2006.169.07:44:09.29#ibcon#about to read 6, iclass 11, count 2 2006.169.07:44:09.29#ibcon#read 6, iclass 11, count 2 2006.169.07:44:09.29#ibcon#end of sib2, iclass 11, count 2 2006.169.07:44:09.29#ibcon#*after write, iclass 11, count 2 2006.169.07:44:09.29#ibcon#*before return 0, iclass 11, count 2 2006.169.07:44:09.29#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:44:09.29#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:44:09.29#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.169.07:44:09.29#ibcon#ireg 7 cls_cnt 0 2006.169.07:44:09.29#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:44:09.41#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:44:09.41#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:44:09.41#ibcon#enter wrdev, iclass 11, count 0 2006.169.07:44:09.41#ibcon#first serial, iclass 11, count 0 2006.169.07:44:09.41#ibcon#enter sib2, iclass 11, count 0 2006.169.07:44:09.41#ibcon#flushed, iclass 11, count 0 2006.169.07:44:09.41#ibcon#about to write, iclass 11, count 0 2006.169.07:44:09.41#ibcon#wrote, iclass 11, count 0 2006.169.07:44:09.41#ibcon#about to read 3, iclass 11, count 0 2006.169.07:44:09.43#ibcon#read 3, iclass 11, count 0 2006.169.07:44:09.43#ibcon#about to read 4, iclass 11, count 0 2006.169.07:44:09.43#ibcon#read 4, iclass 11, count 0 2006.169.07:44:09.43#ibcon#about to read 5, iclass 11, count 0 2006.169.07:44:09.43#ibcon#read 5, iclass 11, count 0 2006.169.07:44:09.43#ibcon#about to read 6, iclass 11, count 0 2006.169.07:44:09.43#ibcon#read 6, iclass 11, count 0 2006.169.07:44:09.43#ibcon#end of sib2, iclass 11, count 0 2006.169.07:44:09.43#ibcon#*mode == 0, iclass 11, count 0 2006.169.07:44:09.43#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.169.07:44:09.43#ibcon#[27=USB\r\n] 2006.169.07:44:09.43#ibcon#*before write, iclass 11, count 0 2006.169.07:44:09.43#ibcon#enter sib2, iclass 11, count 0 2006.169.07:44:09.43#ibcon#flushed, iclass 11, count 0 2006.169.07:44:09.43#ibcon#about to write, iclass 11, count 0 2006.169.07:44:09.43#ibcon#wrote, iclass 11, count 0 2006.169.07:44:09.43#ibcon#about to read 3, iclass 11, count 0 2006.169.07:44:09.46#ibcon#read 3, iclass 11, count 0 2006.169.07:44:09.46#ibcon#about to read 4, iclass 11, count 0 2006.169.07:44:09.46#ibcon#read 4, iclass 11, count 0 2006.169.07:44:09.46#ibcon#about to read 5, iclass 11, count 0 2006.169.07:44:09.46#ibcon#read 5, iclass 11, count 0 2006.169.07:44:09.46#ibcon#about to read 6, iclass 11, count 0 2006.169.07:44:09.46#ibcon#read 6, iclass 11, count 0 2006.169.07:44:09.46#ibcon#end of sib2, iclass 11, count 0 2006.169.07:44:09.46#ibcon#*after write, iclass 11, count 0 2006.169.07:44:09.46#ibcon#*before return 0, iclass 11, count 0 2006.169.07:44:09.46#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:44:09.46#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:44:09.46#ibcon#about to clear, iclass 11 cls_cnt 0 2006.169.07:44:09.46#ibcon#cleared, iclass 11 cls_cnt 0 2006.169.07:44:09.46$vc4f8/vabw=wide 2006.169.07:44:09.46#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.169.07:44:09.46#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.169.07:44:09.46#ibcon#ireg 8 cls_cnt 0 2006.169.07:44:09.46#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:44:09.46#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:44:09.46#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:44:09.46#ibcon#enter wrdev, iclass 13, count 0 2006.169.07:44:09.46#ibcon#first serial, iclass 13, count 0 2006.169.07:44:09.46#ibcon#enter sib2, iclass 13, count 0 2006.169.07:44:09.46#ibcon#flushed, iclass 13, count 0 2006.169.07:44:09.46#ibcon#about to write, iclass 13, count 0 2006.169.07:44:09.46#ibcon#wrote, iclass 13, count 0 2006.169.07:44:09.46#ibcon#about to read 3, iclass 13, count 0 2006.169.07:44:09.48#ibcon#read 3, iclass 13, count 0 2006.169.07:44:09.48#ibcon#about to read 4, iclass 13, count 0 2006.169.07:44:09.48#ibcon#read 4, iclass 13, count 0 2006.169.07:44:09.48#ibcon#about to read 5, iclass 13, count 0 2006.169.07:44:09.48#ibcon#read 5, iclass 13, count 0 2006.169.07:44:09.48#ibcon#about to read 6, iclass 13, count 0 2006.169.07:44:09.48#ibcon#read 6, iclass 13, count 0 2006.169.07:44:09.48#ibcon#end of sib2, iclass 13, count 0 2006.169.07:44:09.48#ibcon#*mode == 0, iclass 13, count 0 2006.169.07:44:09.48#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.07:44:09.48#ibcon#[25=BW32\r\n] 2006.169.07:44:09.48#ibcon#*before write, iclass 13, count 0 2006.169.07:44:09.48#ibcon#enter sib2, iclass 13, count 0 2006.169.07:44:09.48#ibcon#flushed, iclass 13, count 0 2006.169.07:44:09.48#ibcon#about to write, iclass 13, count 0 2006.169.07:44:09.48#ibcon#wrote, iclass 13, count 0 2006.169.07:44:09.48#ibcon#about to read 3, iclass 13, count 0 2006.169.07:44:09.51#ibcon#read 3, iclass 13, count 0 2006.169.07:44:09.51#ibcon#about to read 4, iclass 13, count 0 2006.169.07:44:09.51#ibcon#read 4, iclass 13, count 0 2006.169.07:44:09.51#ibcon#about to read 5, iclass 13, count 0 2006.169.07:44:09.51#ibcon#read 5, iclass 13, count 0 2006.169.07:44:09.51#ibcon#about to read 6, iclass 13, count 0 2006.169.07:44:09.51#ibcon#read 6, iclass 13, count 0 2006.169.07:44:09.51#ibcon#end of sib2, iclass 13, count 0 2006.169.07:44:09.51#ibcon#*after write, iclass 13, count 0 2006.169.07:44:09.51#ibcon#*before return 0, iclass 13, count 0 2006.169.07:44:09.51#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:44:09.51#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:44:09.51#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.07:44:09.51#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.07:44:09.51$vc4f8/vbbw=wide 2006.169.07:44:09.51#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.169.07:44:09.51#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.169.07:44:09.51#ibcon#ireg 8 cls_cnt 0 2006.169.07:44:09.51#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:44:09.58#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:44:09.58#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:44:09.58#ibcon#enter wrdev, iclass 15, count 0 2006.169.07:44:09.58#ibcon#first serial, iclass 15, count 0 2006.169.07:44:09.58#ibcon#enter sib2, iclass 15, count 0 2006.169.07:44:09.58#ibcon#flushed, iclass 15, count 0 2006.169.07:44:09.58#ibcon#about to write, iclass 15, count 0 2006.169.07:44:09.58#ibcon#wrote, iclass 15, count 0 2006.169.07:44:09.58#ibcon#about to read 3, iclass 15, count 0 2006.169.07:44:09.60#ibcon#read 3, iclass 15, count 0 2006.169.07:44:09.60#ibcon#about to read 4, iclass 15, count 0 2006.169.07:44:09.60#ibcon#read 4, iclass 15, count 0 2006.169.07:44:09.60#ibcon#about to read 5, iclass 15, count 0 2006.169.07:44:09.60#ibcon#read 5, iclass 15, count 0 2006.169.07:44:09.60#ibcon#about to read 6, iclass 15, count 0 2006.169.07:44:09.60#ibcon#read 6, iclass 15, count 0 2006.169.07:44:09.60#ibcon#end of sib2, iclass 15, count 0 2006.169.07:44:09.60#ibcon#*mode == 0, iclass 15, count 0 2006.169.07:44:09.60#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.169.07:44:09.60#ibcon#[27=BW32\r\n] 2006.169.07:44:09.60#ibcon#*before write, iclass 15, count 0 2006.169.07:44:09.60#ibcon#enter sib2, iclass 15, count 0 2006.169.07:44:09.60#ibcon#flushed, iclass 15, count 0 2006.169.07:44:09.60#ibcon#about to write, iclass 15, count 0 2006.169.07:44:09.60#ibcon#wrote, iclass 15, count 0 2006.169.07:44:09.60#ibcon#about to read 3, iclass 15, count 0 2006.169.07:44:09.63#ibcon#read 3, iclass 15, count 0 2006.169.07:44:09.63#ibcon#about to read 4, iclass 15, count 0 2006.169.07:44:09.63#ibcon#read 4, iclass 15, count 0 2006.169.07:44:09.63#ibcon#about to read 5, iclass 15, count 0 2006.169.07:44:09.63#ibcon#read 5, iclass 15, count 0 2006.169.07:44:09.63#ibcon#about to read 6, iclass 15, count 0 2006.169.07:44:09.63#ibcon#read 6, iclass 15, count 0 2006.169.07:44:09.63#ibcon#end of sib2, iclass 15, count 0 2006.169.07:44:09.63#ibcon#*after write, iclass 15, count 0 2006.169.07:44:09.63#ibcon#*before return 0, iclass 15, count 0 2006.169.07:44:09.63#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:44:09.63#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:44:09.63#ibcon#about to clear, iclass 15 cls_cnt 0 2006.169.07:44:09.63#ibcon#cleared, iclass 15 cls_cnt 0 2006.169.07:44:09.63$4f8m12a/ifd4f 2006.169.07:44:09.63$ifd4f/lo= 2006.169.07:44:09.63$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.07:44:09.63$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.07:44:09.63$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.07:44:09.63$ifd4f/patch= 2006.169.07:44:09.63$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.07:44:09.64$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.07:44:09.64$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.07:44:09.64$4f8m12a/"form=m,16.000,1:2 2006.169.07:44:09.64$4f8m12a/"tpicd 2006.169.07:44:09.64$4f8m12a/echo=off 2006.169.07:44:09.64$4f8m12a/xlog=off 2006.169.07:44:09.64:!2006.169.07:44:20 2006.169.07:44:20.01:preob 2006.169.07:44:21.14/onsource/TRACKING 2006.169.07:44:21.14:!2006.169.07:44:30 2006.169.07:44:30.00:data_valid=on 2006.169.07:44:30.00:midob 2006.169.07:44:30.14/onsource/TRACKING 2006.169.07:44:30.14/wx/18.13,1003.8,100 2006.169.07:44:30.23/cable/+6.5275E-03 2006.169.07:44:31.31/va/01,08,usb,yes,52,55 2006.169.07:44:31.31/va/02,07,usb,yes,53,55 2006.169.07:44:31.31/va/03,06,usb,yes,56,56 2006.169.07:44:31.31/va/04,07,usb,yes,54,58 2006.169.07:44:31.31/va/05,07,usb,yes,59,63 2006.169.07:44:31.31/va/06,06,usb,yes,59,59 2006.169.07:44:31.31/va/07,06,usb,yes,60,59 2006.169.07:44:31.31/va/08,07,usb,yes,57,56 2006.169.07:44:31.54/valo/01,532.99,yes,locked 2006.169.07:44:31.54/valo/02,572.99,yes,locked 2006.169.07:44:31.54/valo/03,672.99,yes,locked 2006.169.07:44:31.54/valo/04,832.99,yes,locked 2006.169.07:44:31.54/valo/05,652.99,yes,locked 2006.169.07:44:31.54/valo/06,772.99,yes,locked 2006.169.07:44:31.54/valo/07,832.99,yes,locked 2006.169.07:44:31.54/valo/08,852.99,yes,locked 2006.169.07:44:32.63/vb/01,04,usb,yes,31,30 2006.169.07:44:32.63/vb/02,04,usb,yes,33,34 2006.169.07:44:32.63/vb/03,04,usb,yes,29,33 2006.169.07:44:32.63/vb/04,04,usb,yes,30,30 2006.169.07:44:32.63/vb/05,04,usb,yes,29,33 2006.169.07:44:32.63/vb/06,04,usb,yes,30,33 2006.169.07:44:32.63/vb/07,04,usb,yes,32,32 2006.169.07:44:32.63/vb/08,04,usb,yes,30,33 2006.169.07:44:32.86/vblo/01,632.99,yes,locked 2006.169.07:44:32.86/vblo/02,640.99,yes,locked 2006.169.07:44:32.86/vblo/03,656.99,yes,locked 2006.169.07:44:32.86/vblo/04,712.99,yes,locked 2006.169.07:44:32.86/vblo/05,744.99,yes,locked 2006.169.07:44:32.86/vblo/06,752.99,yes,locked 2006.169.07:44:32.86/vblo/07,734.99,yes,locked 2006.169.07:44:32.86/vblo/08,744.99,yes,locked 2006.169.07:44:33.01/vabw/8 2006.169.07:44:33.16/vbbw/8 2006.169.07:44:33.25/xfe/off,on,16.0 2006.169.07:44:33.62/ifatt/23,28,28,28 2006.169.07:44:34.07/fmout-gps/S +4.17E-07 2006.169.07:44:34.12:!2006.169.07:45:30 2006.169.07:45:30.01:data_valid=off 2006.169.07:45:30.02:postob 2006.169.07:45:30.12/cable/+6.5276E-03 2006.169.07:45:30.13/wx/18.13,1003.8,100 2006.169.07:45:31.07/fmout-gps/S +4.17E-07 2006.169.07:45:31.08:scan_name=169-0747,k06169,130 2006.169.07:45:31.08:source=0722+145,072516.81,142513.7,2000.0,ccw 2006.169.07:45:31.13#flagr#flagr/antenna,new-source 2006.169.07:45:32.13:checkk5 2006.169.07:45:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.169.07:45:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.169.07:45:36.91/chk_autoobs//k5ts3?ERROR: timeout happened! 2006.169.07:45:37.30/chk_autoobs//k5ts4/ autoobs is running! 2006.169.07:45:37.67/chk_obsdata//k5ts1/T1690744??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:45:38.04/chk_obsdata//k5ts2/T1690744??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:45:45.09/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.07:45:45.47/chk_obsdata//k5ts4/T1690744??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:45:46.17/k5log//k5ts1_log_newline 2006.169.07:45:46.87/k5log//k5ts2_log_newline 2006.169.07:45:53.96/k5log//k5ts3?ERROR: timeout happened! 2006.169.07:45:54.67/k5log//k5ts4_log_newline 2006.169.07:45:54.84/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.07:45:54.84:4f8m12a=1 2006.169.07:45:54.84$4f8m12a/echo=on 2006.169.07:45:54.84$4f8m12a/pcalon 2006.169.07:45:54.84$pcalon/"no phase cal control is implemented here 2006.169.07:45:54.84$4f8m12a/"tpicd=stop 2006.169.07:45:54.84$4f8m12a/vc4f8 2006.169.07:45:54.84$vc4f8/valo=1,532.99 2006.169.07:45:54.85#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.169.07:45:54.85#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.169.07:45:54.85#ibcon#ireg 17 cls_cnt 0 2006.169.07:45:54.85#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:45:54.85#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:45:54.85#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:45:54.85#ibcon#enter wrdev, iclass 22, count 0 2006.169.07:45:54.85#ibcon#first serial, iclass 22, count 0 2006.169.07:45:54.85#ibcon#enter sib2, iclass 22, count 0 2006.169.07:45:54.85#ibcon#flushed, iclass 22, count 0 2006.169.07:45:54.85#ibcon#about to write, iclass 22, count 0 2006.169.07:45:54.85#ibcon#wrote, iclass 22, count 0 2006.169.07:45:54.85#ibcon#about to read 3, iclass 22, count 0 2006.169.07:45:54.86#ibcon#read 3, iclass 22, count 0 2006.169.07:45:54.86#ibcon#about to read 4, iclass 22, count 0 2006.169.07:45:54.86#ibcon#read 4, iclass 22, count 0 2006.169.07:45:54.86#ibcon#about to read 5, iclass 22, count 0 2006.169.07:45:54.86#ibcon#read 5, iclass 22, count 0 2006.169.07:45:54.86#ibcon#about to read 6, iclass 22, count 0 2006.169.07:45:54.86#ibcon#read 6, iclass 22, count 0 2006.169.07:45:54.86#ibcon#end of sib2, iclass 22, count 0 2006.169.07:45:54.86#ibcon#*mode == 0, iclass 22, count 0 2006.169.07:45:54.86#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.169.07:45:54.86#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.07:45:54.86#ibcon#*before write, iclass 22, count 0 2006.169.07:45:54.86#ibcon#enter sib2, iclass 22, count 0 2006.169.07:45:54.86#ibcon#flushed, iclass 22, count 0 2006.169.07:45:54.86#ibcon#about to write, iclass 22, count 0 2006.169.07:45:54.86#ibcon#wrote, iclass 22, count 0 2006.169.07:45:54.86#ibcon#about to read 3, iclass 22, count 0 2006.169.07:45:54.91#ibcon#read 3, iclass 22, count 0 2006.169.07:45:54.91#ibcon#about to read 4, iclass 22, count 0 2006.169.07:45:54.91#ibcon#read 4, iclass 22, count 0 2006.169.07:45:54.91#ibcon#about to read 5, iclass 22, count 0 2006.169.07:45:54.91#ibcon#read 5, iclass 22, count 0 2006.169.07:45:54.91#ibcon#about to read 6, iclass 22, count 0 2006.169.07:45:54.91#ibcon#read 6, iclass 22, count 0 2006.169.07:45:54.91#ibcon#end of sib2, iclass 22, count 0 2006.169.07:45:54.91#ibcon#*after write, iclass 22, count 0 2006.169.07:45:54.91#ibcon#*before return 0, iclass 22, count 0 2006.169.07:45:54.91#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:45:54.91#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:45:54.91#ibcon#about to clear, iclass 22 cls_cnt 0 2006.169.07:45:54.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.169.07:45:54.92$vc4f8/va=1,8 2006.169.07:45:54.92#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.169.07:45:54.92#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.169.07:45:54.92#ibcon#ireg 11 cls_cnt 2 2006.169.07:45:54.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.169.07:45:54.92#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.169.07:45:54.92#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.169.07:45:54.92#ibcon#enter wrdev, iclass 24, count 2 2006.169.07:45:54.92#ibcon#first serial, iclass 24, count 2 2006.169.07:45:54.92#ibcon#enter sib2, iclass 24, count 2 2006.169.07:45:54.92#ibcon#flushed, iclass 24, count 2 2006.169.07:45:54.92#ibcon#about to write, iclass 24, count 2 2006.169.07:45:54.92#ibcon#wrote, iclass 24, count 2 2006.169.07:45:54.92#ibcon#about to read 3, iclass 24, count 2 2006.169.07:45:54.93#ibcon#read 3, iclass 24, count 2 2006.169.07:45:54.93#ibcon#about to read 4, iclass 24, count 2 2006.169.07:45:54.93#ibcon#read 4, iclass 24, count 2 2006.169.07:45:54.93#ibcon#about to read 5, iclass 24, count 2 2006.169.07:45:54.93#ibcon#read 5, iclass 24, count 2 2006.169.07:45:54.93#ibcon#about to read 6, iclass 24, count 2 2006.169.07:45:54.93#ibcon#read 6, iclass 24, count 2 2006.169.07:45:54.93#ibcon#end of sib2, iclass 24, count 2 2006.169.07:45:54.93#ibcon#*mode == 0, iclass 24, count 2 2006.169.07:45:54.93#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.169.07:45:54.93#ibcon#[25=AT01-08\r\n] 2006.169.07:45:54.93#ibcon#*before write, iclass 24, count 2 2006.169.07:45:54.93#ibcon#enter sib2, iclass 24, count 2 2006.169.07:45:54.93#ibcon#flushed, iclass 24, count 2 2006.169.07:45:54.93#ibcon#about to write, iclass 24, count 2 2006.169.07:45:54.93#ibcon#wrote, iclass 24, count 2 2006.169.07:45:54.93#ibcon#about to read 3, iclass 24, count 2 2006.169.07:45:54.96#ibcon#read 3, iclass 24, count 2 2006.169.07:45:54.96#ibcon#about to read 4, iclass 24, count 2 2006.169.07:45:54.96#ibcon#read 4, iclass 24, count 2 2006.169.07:45:54.96#ibcon#about to read 5, iclass 24, count 2 2006.169.07:45:54.96#ibcon#read 5, iclass 24, count 2 2006.169.07:45:54.96#ibcon#about to read 6, iclass 24, count 2 2006.169.07:45:54.96#ibcon#read 6, iclass 24, count 2 2006.169.07:45:54.96#ibcon#end of sib2, iclass 24, count 2 2006.169.07:45:54.96#ibcon#*after write, iclass 24, count 2 2006.169.07:45:54.96#ibcon#*before return 0, iclass 24, count 2 2006.169.07:45:54.96#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.169.07:45:54.96#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.169.07:45:54.96#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.169.07:45:54.96#ibcon#ireg 7 cls_cnt 0 2006.169.07:45:54.96#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.169.07:45:55.08#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.169.07:45:55.08#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.169.07:45:55.08#ibcon#enter wrdev, iclass 24, count 0 2006.169.07:45:55.08#ibcon#first serial, iclass 24, count 0 2006.169.07:45:55.08#ibcon#enter sib2, iclass 24, count 0 2006.169.07:45:55.08#ibcon#flushed, iclass 24, count 0 2006.169.07:45:55.08#ibcon#about to write, iclass 24, count 0 2006.169.07:45:55.08#ibcon#wrote, iclass 24, count 0 2006.169.07:45:55.08#ibcon#about to read 3, iclass 24, count 0 2006.169.07:45:55.12#ibcon#read 3, iclass 24, count 0 2006.169.07:45:55.12#ibcon#about to read 4, iclass 24, count 0 2006.169.07:45:55.12#ibcon#read 4, iclass 24, count 0 2006.169.07:45:55.12#ibcon#about to read 5, iclass 24, count 0 2006.169.07:45:55.12#ibcon#read 5, iclass 24, count 0 2006.169.07:45:55.12#ibcon#about to read 6, iclass 24, count 0 2006.169.07:45:55.12#ibcon#read 6, iclass 24, count 0 2006.169.07:45:55.12#ibcon#end of sib2, iclass 24, count 0 2006.169.07:45:55.12#ibcon#*mode == 0, iclass 24, count 0 2006.169.07:45:55.12#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.169.07:45:55.12#ibcon#[25=USB\r\n] 2006.169.07:45:55.12#ibcon#*before write, iclass 24, count 0 2006.169.07:45:55.12#ibcon#enter sib2, iclass 24, count 0 2006.169.07:45:55.12#ibcon#flushed, iclass 24, count 0 2006.169.07:45:55.12#ibcon#about to write, iclass 24, count 0 2006.169.07:45:55.12#ibcon#wrote, iclass 24, count 0 2006.169.07:45:55.12#ibcon#about to read 3, iclass 24, count 0 2006.169.07:45:55.15#ibcon#read 3, iclass 24, count 0 2006.169.07:45:55.15#ibcon#about to read 4, iclass 24, count 0 2006.169.07:45:55.15#ibcon#read 4, iclass 24, count 0 2006.169.07:45:55.15#ibcon#about to read 5, iclass 24, count 0 2006.169.07:45:55.15#ibcon#read 5, iclass 24, count 0 2006.169.07:45:55.15#ibcon#about to read 6, iclass 24, count 0 2006.169.07:45:55.15#ibcon#read 6, iclass 24, count 0 2006.169.07:45:55.15#ibcon#end of sib2, iclass 24, count 0 2006.169.07:45:55.15#ibcon#*after write, iclass 24, count 0 2006.169.07:45:55.15#ibcon#*before return 0, iclass 24, count 0 2006.169.07:45:55.15#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.169.07:45:55.15#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.169.07:45:55.15#ibcon#about to clear, iclass 24 cls_cnt 0 2006.169.07:45:55.15#ibcon#cleared, iclass 24 cls_cnt 0 2006.169.07:45:55.15$vc4f8/valo=2,572.99 2006.169.07:45:55.15#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.169.07:45:55.15#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.169.07:45:55.15#ibcon#ireg 17 cls_cnt 0 2006.169.07:45:55.15#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:45:55.15#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:45:55.15#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:45:55.15#ibcon#enter wrdev, iclass 26, count 0 2006.169.07:45:55.15#ibcon#first serial, iclass 26, count 0 2006.169.07:45:55.15#ibcon#enter sib2, iclass 26, count 0 2006.169.07:45:55.15#ibcon#flushed, iclass 26, count 0 2006.169.07:45:55.15#ibcon#about to write, iclass 26, count 0 2006.169.07:45:55.15#ibcon#wrote, iclass 26, count 0 2006.169.07:45:55.15#ibcon#about to read 3, iclass 26, count 0 2006.169.07:45:55.18#ibcon#read 3, iclass 26, count 0 2006.169.07:45:55.18#ibcon#about to read 4, iclass 26, count 0 2006.169.07:45:55.18#ibcon#read 4, iclass 26, count 0 2006.169.07:45:55.18#ibcon#about to read 5, iclass 26, count 0 2006.169.07:45:55.18#ibcon#read 5, iclass 26, count 0 2006.169.07:45:55.18#ibcon#about to read 6, iclass 26, count 0 2006.169.07:45:55.18#ibcon#read 6, iclass 26, count 0 2006.169.07:45:55.18#ibcon#end of sib2, iclass 26, count 0 2006.169.07:45:55.18#ibcon#*mode == 0, iclass 26, count 0 2006.169.07:45:55.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.169.07:45:55.18#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.07:45:55.18#ibcon#*before write, iclass 26, count 0 2006.169.07:45:55.18#ibcon#enter sib2, iclass 26, count 0 2006.169.07:45:55.18#ibcon#flushed, iclass 26, count 0 2006.169.07:45:55.18#ibcon#about to write, iclass 26, count 0 2006.169.07:45:55.18#ibcon#wrote, iclass 26, count 0 2006.169.07:45:55.18#ibcon#about to read 3, iclass 26, count 0 2006.169.07:45:55.21#ibcon#read 3, iclass 26, count 0 2006.169.07:45:55.21#ibcon#about to read 4, iclass 26, count 0 2006.169.07:45:55.21#ibcon#read 4, iclass 26, count 0 2006.169.07:45:55.21#ibcon#about to read 5, iclass 26, count 0 2006.169.07:45:55.21#ibcon#read 5, iclass 26, count 0 2006.169.07:45:55.21#ibcon#about to read 6, iclass 26, count 0 2006.169.07:45:55.21#ibcon#read 6, iclass 26, count 0 2006.169.07:45:55.21#ibcon#end of sib2, iclass 26, count 0 2006.169.07:45:55.21#ibcon#*after write, iclass 26, count 0 2006.169.07:45:55.21#ibcon#*before return 0, iclass 26, count 0 2006.169.07:45:55.21#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:45:55.21#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:45:55.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.169.07:45:55.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.169.07:45:55.21$vc4f8/va=2,7 2006.169.07:45:55.21#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.169.07:45:55.21#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.169.07:45:55.21#ibcon#ireg 11 cls_cnt 2 2006.169.07:45:55.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.169.07:45:55.27#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.169.07:45:55.27#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.169.07:45:55.27#ibcon#enter wrdev, iclass 28, count 2 2006.169.07:45:55.27#ibcon#first serial, iclass 28, count 2 2006.169.07:45:55.27#ibcon#enter sib2, iclass 28, count 2 2006.169.07:45:55.27#ibcon#flushed, iclass 28, count 2 2006.169.07:45:55.27#ibcon#about to write, iclass 28, count 2 2006.169.07:45:55.27#ibcon#wrote, iclass 28, count 2 2006.169.07:45:55.27#ibcon#about to read 3, iclass 28, count 2 2006.169.07:45:55.30#ibcon#read 3, iclass 28, count 2 2006.169.07:45:55.30#ibcon#about to read 4, iclass 28, count 2 2006.169.07:45:55.30#ibcon#read 4, iclass 28, count 2 2006.169.07:45:55.30#ibcon#about to read 5, iclass 28, count 2 2006.169.07:45:55.30#ibcon#read 5, iclass 28, count 2 2006.169.07:45:55.30#ibcon#about to read 6, iclass 28, count 2 2006.169.07:45:55.30#ibcon#read 6, iclass 28, count 2 2006.169.07:45:55.30#ibcon#end of sib2, iclass 28, count 2 2006.169.07:45:55.30#ibcon#*mode == 0, iclass 28, count 2 2006.169.07:45:55.30#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.169.07:45:55.30#ibcon#[25=AT02-07\r\n] 2006.169.07:45:55.30#ibcon#*before write, iclass 28, count 2 2006.169.07:45:55.30#ibcon#enter sib2, iclass 28, count 2 2006.169.07:45:55.30#ibcon#flushed, iclass 28, count 2 2006.169.07:45:55.30#ibcon#about to write, iclass 28, count 2 2006.169.07:45:55.30#ibcon#wrote, iclass 28, count 2 2006.169.07:45:55.30#ibcon#about to read 3, iclass 28, count 2 2006.169.07:45:55.33#ibcon#read 3, iclass 28, count 2 2006.169.07:45:55.33#ibcon#about to read 4, iclass 28, count 2 2006.169.07:45:55.33#ibcon#read 4, iclass 28, count 2 2006.169.07:45:55.33#ibcon#about to read 5, iclass 28, count 2 2006.169.07:45:55.33#ibcon#read 5, iclass 28, count 2 2006.169.07:45:55.33#ibcon#about to read 6, iclass 28, count 2 2006.169.07:45:55.33#ibcon#read 6, iclass 28, count 2 2006.169.07:45:55.33#ibcon#end of sib2, iclass 28, count 2 2006.169.07:45:55.33#ibcon#*after write, iclass 28, count 2 2006.169.07:45:55.33#ibcon#*before return 0, iclass 28, count 2 2006.169.07:45:55.33#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.169.07:45:55.33#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.169.07:45:55.33#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.169.07:45:55.33#ibcon#ireg 7 cls_cnt 0 2006.169.07:45:55.33#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.169.07:45:55.45#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.169.07:45:55.45#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.169.07:45:55.45#ibcon#enter wrdev, iclass 28, count 0 2006.169.07:45:55.45#ibcon#first serial, iclass 28, count 0 2006.169.07:45:55.45#ibcon#enter sib2, iclass 28, count 0 2006.169.07:45:55.45#ibcon#flushed, iclass 28, count 0 2006.169.07:45:55.45#ibcon#about to write, iclass 28, count 0 2006.169.07:45:55.45#ibcon#wrote, iclass 28, count 0 2006.169.07:45:55.45#ibcon#about to read 3, iclass 28, count 0 2006.169.07:45:55.47#ibcon#read 3, iclass 28, count 0 2006.169.07:45:55.47#ibcon#about to read 4, iclass 28, count 0 2006.169.07:45:55.47#ibcon#read 4, iclass 28, count 0 2006.169.07:45:55.47#ibcon#about to read 5, iclass 28, count 0 2006.169.07:45:55.47#ibcon#read 5, iclass 28, count 0 2006.169.07:45:55.47#ibcon#about to read 6, iclass 28, count 0 2006.169.07:45:55.47#ibcon#read 6, iclass 28, count 0 2006.169.07:45:55.47#ibcon#end of sib2, iclass 28, count 0 2006.169.07:45:55.47#ibcon#*mode == 0, iclass 28, count 0 2006.169.07:45:55.47#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.169.07:45:55.47#ibcon#[25=USB\r\n] 2006.169.07:45:55.47#ibcon#*before write, iclass 28, count 0 2006.169.07:45:55.47#ibcon#enter sib2, iclass 28, count 0 2006.169.07:45:55.47#ibcon#flushed, iclass 28, count 0 2006.169.07:45:55.47#ibcon#about to write, iclass 28, count 0 2006.169.07:45:55.47#ibcon#wrote, iclass 28, count 0 2006.169.07:45:55.47#ibcon#about to read 3, iclass 28, count 0 2006.169.07:45:55.50#ibcon#read 3, iclass 28, count 0 2006.169.07:45:55.50#ibcon#about to read 4, iclass 28, count 0 2006.169.07:45:55.50#ibcon#read 4, iclass 28, count 0 2006.169.07:45:55.50#ibcon#about to read 5, iclass 28, count 0 2006.169.07:45:55.50#ibcon#read 5, iclass 28, count 0 2006.169.07:45:55.50#ibcon#about to read 6, iclass 28, count 0 2006.169.07:45:55.50#ibcon#read 6, iclass 28, count 0 2006.169.07:45:55.50#ibcon#end of sib2, iclass 28, count 0 2006.169.07:45:55.50#ibcon#*after write, iclass 28, count 0 2006.169.07:45:55.50#ibcon#*before return 0, iclass 28, count 0 2006.169.07:45:55.50#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.169.07:45:55.50#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.169.07:45:55.50#ibcon#about to clear, iclass 28 cls_cnt 0 2006.169.07:45:55.50#ibcon#cleared, iclass 28 cls_cnt 0 2006.169.07:45:55.50$vc4f8/valo=3,672.99 2006.169.07:45:55.50#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.169.07:45:55.50#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.169.07:45:55.50#ibcon#ireg 17 cls_cnt 0 2006.169.07:45:55.50#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:45:55.50#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:45:55.50#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:45:55.50#ibcon#enter wrdev, iclass 30, count 0 2006.169.07:45:55.50#ibcon#first serial, iclass 30, count 0 2006.169.07:45:55.50#ibcon#enter sib2, iclass 30, count 0 2006.169.07:45:55.50#ibcon#flushed, iclass 30, count 0 2006.169.07:45:55.50#ibcon#about to write, iclass 30, count 0 2006.169.07:45:55.50#ibcon#wrote, iclass 30, count 0 2006.169.07:45:55.50#ibcon#about to read 3, iclass 30, count 0 2006.169.07:45:55.52#ibcon#read 3, iclass 30, count 0 2006.169.07:45:55.52#ibcon#about to read 4, iclass 30, count 0 2006.169.07:45:55.52#ibcon#read 4, iclass 30, count 0 2006.169.07:45:55.52#ibcon#about to read 5, iclass 30, count 0 2006.169.07:45:55.52#ibcon#read 5, iclass 30, count 0 2006.169.07:45:55.52#ibcon#about to read 6, iclass 30, count 0 2006.169.07:45:55.52#ibcon#read 6, iclass 30, count 0 2006.169.07:45:55.52#ibcon#end of sib2, iclass 30, count 0 2006.169.07:45:55.52#ibcon#*mode == 0, iclass 30, count 0 2006.169.07:45:55.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.169.07:45:55.52#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.07:45:55.52#ibcon#*before write, iclass 30, count 0 2006.169.07:45:55.52#ibcon#enter sib2, iclass 30, count 0 2006.169.07:45:55.52#ibcon#flushed, iclass 30, count 0 2006.169.07:45:55.52#ibcon#about to write, iclass 30, count 0 2006.169.07:45:55.52#ibcon#wrote, iclass 30, count 0 2006.169.07:45:55.52#ibcon#about to read 3, iclass 30, count 0 2006.169.07:45:55.56#ibcon#read 3, iclass 30, count 0 2006.169.07:45:55.56#ibcon#about to read 4, iclass 30, count 0 2006.169.07:45:55.56#ibcon#read 4, iclass 30, count 0 2006.169.07:45:55.56#ibcon#about to read 5, iclass 30, count 0 2006.169.07:45:55.56#ibcon#read 5, iclass 30, count 0 2006.169.07:45:55.56#ibcon#about to read 6, iclass 30, count 0 2006.169.07:45:55.56#ibcon#read 6, iclass 30, count 0 2006.169.07:45:55.56#ibcon#end of sib2, iclass 30, count 0 2006.169.07:45:55.56#ibcon#*after write, iclass 30, count 0 2006.169.07:45:55.56#ibcon#*before return 0, iclass 30, count 0 2006.169.07:45:55.56#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:45:55.56#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:45:55.56#ibcon#about to clear, iclass 30 cls_cnt 0 2006.169.07:45:55.56#ibcon#cleared, iclass 30 cls_cnt 0 2006.169.07:45:55.56$vc4f8/va=3,6 2006.169.07:45:55.56#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.169.07:45:55.56#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.169.07:45:55.56#ibcon#ireg 11 cls_cnt 2 2006.169.07:45:55.56#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:45:55.62#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:45:55.62#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:45:55.62#ibcon#enter wrdev, iclass 32, count 2 2006.169.07:45:55.62#ibcon#first serial, iclass 32, count 2 2006.169.07:45:55.62#ibcon#enter sib2, iclass 32, count 2 2006.169.07:45:55.62#ibcon#flushed, iclass 32, count 2 2006.169.07:45:55.62#ibcon#about to write, iclass 32, count 2 2006.169.07:45:55.62#ibcon#wrote, iclass 32, count 2 2006.169.07:45:55.62#ibcon#about to read 3, iclass 32, count 2 2006.169.07:45:55.64#ibcon#read 3, iclass 32, count 2 2006.169.07:45:55.64#ibcon#about to read 4, iclass 32, count 2 2006.169.07:45:55.64#ibcon#read 4, iclass 32, count 2 2006.169.07:45:55.64#ibcon#about to read 5, iclass 32, count 2 2006.169.07:45:55.64#ibcon#read 5, iclass 32, count 2 2006.169.07:45:55.64#ibcon#about to read 6, iclass 32, count 2 2006.169.07:45:55.64#ibcon#read 6, iclass 32, count 2 2006.169.07:45:55.64#ibcon#end of sib2, iclass 32, count 2 2006.169.07:45:55.64#ibcon#*mode == 0, iclass 32, count 2 2006.169.07:45:55.64#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.169.07:45:55.64#ibcon#[25=AT03-06\r\n] 2006.169.07:45:55.64#ibcon#*before write, iclass 32, count 2 2006.169.07:45:55.64#ibcon#enter sib2, iclass 32, count 2 2006.169.07:45:55.64#ibcon#flushed, iclass 32, count 2 2006.169.07:45:55.64#ibcon#about to write, iclass 32, count 2 2006.169.07:45:55.64#ibcon#wrote, iclass 32, count 2 2006.169.07:45:55.64#ibcon#about to read 3, iclass 32, count 2 2006.169.07:45:55.67#ibcon#read 3, iclass 32, count 2 2006.169.07:45:55.67#ibcon#about to read 4, iclass 32, count 2 2006.169.07:45:55.67#ibcon#read 4, iclass 32, count 2 2006.169.07:45:55.67#ibcon#about to read 5, iclass 32, count 2 2006.169.07:45:55.67#ibcon#read 5, iclass 32, count 2 2006.169.07:45:55.67#ibcon#about to read 6, iclass 32, count 2 2006.169.07:45:55.67#ibcon#read 6, iclass 32, count 2 2006.169.07:45:55.67#ibcon#end of sib2, iclass 32, count 2 2006.169.07:45:55.67#ibcon#*after write, iclass 32, count 2 2006.169.07:45:55.67#ibcon#*before return 0, iclass 32, count 2 2006.169.07:45:55.67#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:45:55.67#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:45:55.67#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.169.07:45:55.67#ibcon#ireg 7 cls_cnt 0 2006.169.07:45:55.67#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:45:55.79#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:45:55.79#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:45:55.79#ibcon#enter wrdev, iclass 32, count 0 2006.169.07:45:55.79#ibcon#first serial, iclass 32, count 0 2006.169.07:45:55.79#ibcon#enter sib2, iclass 32, count 0 2006.169.07:45:55.79#ibcon#flushed, iclass 32, count 0 2006.169.07:45:55.79#ibcon#about to write, iclass 32, count 0 2006.169.07:45:55.79#ibcon#wrote, iclass 32, count 0 2006.169.07:45:55.79#ibcon#about to read 3, iclass 32, count 0 2006.169.07:45:55.81#ibcon#read 3, iclass 32, count 0 2006.169.07:45:55.81#ibcon#about to read 4, iclass 32, count 0 2006.169.07:45:55.81#ibcon#read 4, iclass 32, count 0 2006.169.07:45:55.81#ibcon#about to read 5, iclass 32, count 0 2006.169.07:45:55.81#ibcon#read 5, iclass 32, count 0 2006.169.07:45:55.81#ibcon#about to read 6, iclass 32, count 0 2006.169.07:45:55.81#ibcon#read 6, iclass 32, count 0 2006.169.07:45:55.81#ibcon#end of sib2, iclass 32, count 0 2006.169.07:45:55.81#ibcon#*mode == 0, iclass 32, count 0 2006.169.07:45:55.81#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.169.07:45:55.81#ibcon#[25=USB\r\n] 2006.169.07:45:55.81#ibcon#*before write, iclass 32, count 0 2006.169.07:45:55.81#ibcon#enter sib2, iclass 32, count 0 2006.169.07:45:55.81#ibcon#flushed, iclass 32, count 0 2006.169.07:45:55.81#ibcon#about to write, iclass 32, count 0 2006.169.07:45:55.81#ibcon#wrote, iclass 32, count 0 2006.169.07:45:55.81#ibcon#about to read 3, iclass 32, count 0 2006.169.07:45:55.84#ibcon#read 3, iclass 32, count 0 2006.169.07:45:55.84#ibcon#about to read 4, iclass 32, count 0 2006.169.07:45:55.84#ibcon#read 4, iclass 32, count 0 2006.169.07:45:55.84#ibcon#about to read 5, iclass 32, count 0 2006.169.07:45:55.84#ibcon#read 5, iclass 32, count 0 2006.169.07:45:55.84#ibcon#about to read 6, iclass 32, count 0 2006.169.07:45:55.84#ibcon#read 6, iclass 32, count 0 2006.169.07:45:55.84#ibcon#end of sib2, iclass 32, count 0 2006.169.07:45:55.84#ibcon#*after write, iclass 32, count 0 2006.169.07:45:55.84#ibcon#*before return 0, iclass 32, count 0 2006.169.07:45:55.84#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:45:55.84#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:45:55.84#ibcon#about to clear, iclass 32 cls_cnt 0 2006.169.07:45:55.84#ibcon#cleared, iclass 32 cls_cnt 0 2006.169.07:45:55.84$vc4f8/valo=4,832.99 2006.169.07:45:55.84#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.169.07:45:55.84#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.169.07:45:55.84#ibcon#ireg 17 cls_cnt 0 2006.169.07:45:55.84#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:45:55.84#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:45:55.84#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:45:55.84#ibcon#enter wrdev, iclass 34, count 0 2006.169.07:45:55.84#ibcon#first serial, iclass 34, count 0 2006.169.07:45:55.84#ibcon#enter sib2, iclass 34, count 0 2006.169.07:45:55.84#ibcon#flushed, iclass 34, count 0 2006.169.07:45:55.84#ibcon#about to write, iclass 34, count 0 2006.169.07:45:55.84#ibcon#wrote, iclass 34, count 0 2006.169.07:45:55.84#ibcon#about to read 3, iclass 34, count 0 2006.169.07:45:55.86#ibcon#read 3, iclass 34, count 0 2006.169.07:45:55.86#ibcon#about to read 4, iclass 34, count 0 2006.169.07:45:55.86#ibcon#read 4, iclass 34, count 0 2006.169.07:45:55.86#ibcon#about to read 5, iclass 34, count 0 2006.169.07:45:55.86#ibcon#read 5, iclass 34, count 0 2006.169.07:45:55.86#ibcon#about to read 6, iclass 34, count 0 2006.169.07:45:55.86#ibcon#read 6, iclass 34, count 0 2006.169.07:45:55.86#ibcon#end of sib2, iclass 34, count 0 2006.169.07:45:55.86#ibcon#*mode == 0, iclass 34, count 0 2006.169.07:45:55.86#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.169.07:45:55.86#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.07:45:55.86#ibcon#*before write, iclass 34, count 0 2006.169.07:45:55.86#ibcon#enter sib2, iclass 34, count 0 2006.169.07:45:55.86#ibcon#flushed, iclass 34, count 0 2006.169.07:45:55.86#ibcon#about to write, iclass 34, count 0 2006.169.07:45:55.86#ibcon#wrote, iclass 34, count 0 2006.169.07:45:55.86#ibcon#about to read 3, iclass 34, count 0 2006.169.07:45:55.90#ibcon#read 3, iclass 34, count 0 2006.169.07:45:55.90#ibcon#about to read 4, iclass 34, count 0 2006.169.07:45:55.90#ibcon#read 4, iclass 34, count 0 2006.169.07:45:55.90#ibcon#about to read 5, iclass 34, count 0 2006.169.07:45:55.90#ibcon#read 5, iclass 34, count 0 2006.169.07:45:55.90#ibcon#about to read 6, iclass 34, count 0 2006.169.07:45:55.90#ibcon#read 6, iclass 34, count 0 2006.169.07:45:55.90#ibcon#end of sib2, iclass 34, count 0 2006.169.07:45:55.90#ibcon#*after write, iclass 34, count 0 2006.169.07:45:55.90#ibcon#*before return 0, iclass 34, count 0 2006.169.07:45:55.90#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:45:55.90#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:45:55.90#ibcon#about to clear, iclass 34 cls_cnt 0 2006.169.07:45:55.90#ibcon#cleared, iclass 34 cls_cnt 0 2006.169.07:45:55.90$vc4f8/va=4,7 2006.169.07:45:55.90#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.169.07:45:55.90#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.169.07:45:55.90#ibcon#ireg 11 cls_cnt 2 2006.169.07:45:55.90#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.169.07:45:55.96#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.169.07:45:55.96#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.169.07:45:55.96#ibcon#enter wrdev, iclass 36, count 2 2006.169.07:45:55.96#ibcon#first serial, iclass 36, count 2 2006.169.07:45:55.96#ibcon#enter sib2, iclass 36, count 2 2006.169.07:45:55.96#ibcon#flushed, iclass 36, count 2 2006.169.07:45:55.96#ibcon#about to write, iclass 36, count 2 2006.169.07:45:55.96#ibcon#wrote, iclass 36, count 2 2006.169.07:45:55.96#ibcon#about to read 3, iclass 36, count 2 2006.169.07:45:55.98#ibcon#read 3, iclass 36, count 2 2006.169.07:45:55.98#ibcon#about to read 4, iclass 36, count 2 2006.169.07:45:55.98#ibcon#read 4, iclass 36, count 2 2006.169.07:45:55.98#ibcon#about to read 5, iclass 36, count 2 2006.169.07:45:55.98#ibcon#read 5, iclass 36, count 2 2006.169.07:45:55.98#ibcon#about to read 6, iclass 36, count 2 2006.169.07:45:55.98#ibcon#read 6, iclass 36, count 2 2006.169.07:45:55.98#ibcon#end of sib2, iclass 36, count 2 2006.169.07:45:55.98#ibcon#*mode == 0, iclass 36, count 2 2006.169.07:45:55.98#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.169.07:45:55.98#ibcon#[25=AT04-07\r\n] 2006.169.07:45:55.98#ibcon#*before write, iclass 36, count 2 2006.169.07:45:55.98#ibcon#enter sib2, iclass 36, count 2 2006.169.07:45:55.98#ibcon#flushed, iclass 36, count 2 2006.169.07:45:55.98#ibcon#about to write, iclass 36, count 2 2006.169.07:45:55.98#ibcon#wrote, iclass 36, count 2 2006.169.07:45:55.98#ibcon#about to read 3, iclass 36, count 2 2006.169.07:45:56.01#ibcon#read 3, iclass 36, count 2 2006.169.07:45:56.01#ibcon#about to read 4, iclass 36, count 2 2006.169.07:45:56.01#ibcon#read 4, iclass 36, count 2 2006.169.07:45:56.01#ibcon#about to read 5, iclass 36, count 2 2006.169.07:45:56.01#ibcon#read 5, iclass 36, count 2 2006.169.07:45:56.01#ibcon#about to read 6, iclass 36, count 2 2006.169.07:45:56.01#ibcon#read 6, iclass 36, count 2 2006.169.07:45:56.01#ibcon#end of sib2, iclass 36, count 2 2006.169.07:45:56.01#ibcon#*after write, iclass 36, count 2 2006.169.07:45:56.01#ibcon#*before return 0, iclass 36, count 2 2006.169.07:45:56.01#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.169.07:45:56.01#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.169.07:45:56.01#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.169.07:45:56.01#ibcon#ireg 7 cls_cnt 0 2006.169.07:45:56.01#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.169.07:45:56.13#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.169.07:45:56.13#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.169.07:45:56.13#ibcon#enter wrdev, iclass 36, count 0 2006.169.07:45:56.13#ibcon#first serial, iclass 36, count 0 2006.169.07:45:56.13#ibcon#enter sib2, iclass 36, count 0 2006.169.07:45:56.13#ibcon#flushed, iclass 36, count 0 2006.169.07:45:56.13#ibcon#about to write, iclass 36, count 0 2006.169.07:45:56.13#ibcon#wrote, iclass 36, count 0 2006.169.07:45:56.13#ibcon#about to read 3, iclass 36, count 0 2006.169.07:45:56.15#ibcon#read 3, iclass 36, count 0 2006.169.07:45:56.15#ibcon#about to read 4, iclass 36, count 0 2006.169.07:45:56.15#ibcon#read 4, iclass 36, count 0 2006.169.07:45:56.15#ibcon#about to read 5, iclass 36, count 0 2006.169.07:45:56.15#ibcon#read 5, iclass 36, count 0 2006.169.07:45:56.15#ibcon#about to read 6, iclass 36, count 0 2006.169.07:45:56.15#ibcon#read 6, iclass 36, count 0 2006.169.07:45:56.15#ibcon#end of sib2, iclass 36, count 0 2006.169.07:45:56.15#ibcon#*mode == 0, iclass 36, count 0 2006.169.07:45:56.15#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.169.07:45:56.15#ibcon#[25=USB\r\n] 2006.169.07:45:56.15#ibcon#*before write, iclass 36, count 0 2006.169.07:45:56.15#ibcon#enter sib2, iclass 36, count 0 2006.169.07:45:56.15#ibcon#flushed, iclass 36, count 0 2006.169.07:45:56.15#ibcon#about to write, iclass 36, count 0 2006.169.07:45:56.15#ibcon#wrote, iclass 36, count 0 2006.169.07:45:56.15#ibcon#about to read 3, iclass 36, count 0 2006.169.07:45:56.18#ibcon#read 3, iclass 36, count 0 2006.169.07:45:56.18#ibcon#about to read 4, iclass 36, count 0 2006.169.07:45:56.18#ibcon#read 4, iclass 36, count 0 2006.169.07:45:56.18#ibcon#about to read 5, iclass 36, count 0 2006.169.07:45:56.18#ibcon#read 5, iclass 36, count 0 2006.169.07:45:56.18#ibcon#about to read 6, iclass 36, count 0 2006.169.07:45:56.18#ibcon#read 6, iclass 36, count 0 2006.169.07:45:56.18#ibcon#end of sib2, iclass 36, count 0 2006.169.07:45:56.18#ibcon#*after write, iclass 36, count 0 2006.169.07:45:56.18#ibcon#*before return 0, iclass 36, count 0 2006.169.07:45:56.18#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.169.07:45:56.18#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.169.07:45:56.18#ibcon#about to clear, iclass 36 cls_cnt 0 2006.169.07:45:56.18#ibcon#cleared, iclass 36 cls_cnt 0 2006.169.07:45:56.18$vc4f8/valo=5,652.99 2006.169.07:45:56.18#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.169.07:45:56.18#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.169.07:45:56.18#ibcon#ireg 17 cls_cnt 0 2006.169.07:45:56.18#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:45:56.18#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:45:56.18#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:45:56.18#ibcon#enter wrdev, iclass 38, count 0 2006.169.07:45:56.18#ibcon#first serial, iclass 38, count 0 2006.169.07:45:56.18#ibcon#enter sib2, iclass 38, count 0 2006.169.07:45:56.18#ibcon#flushed, iclass 38, count 0 2006.169.07:45:56.18#ibcon#about to write, iclass 38, count 0 2006.169.07:45:56.18#ibcon#wrote, iclass 38, count 0 2006.169.07:45:56.18#ibcon#about to read 3, iclass 38, count 0 2006.169.07:45:56.20#ibcon#read 3, iclass 38, count 0 2006.169.07:45:56.20#ibcon#about to read 4, iclass 38, count 0 2006.169.07:45:56.20#ibcon#read 4, iclass 38, count 0 2006.169.07:45:56.20#ibcon#about to read 5, iclass 38, count 0 2006.169.07:45:56.20#ibcon#read 5, iclass 38, count 0 2006.169.07:45:56.20#ibcon#about to read 6, iclass 38, count 0 2006.169.07:45:56.20#ibcon#read 6, iclass 38, count 0 2006.169.07:45:56.20#ibcon#end of sib2, iclass 38, count 0 2006.169.07:45:56.20#ibcon#*mode == 0, iclass 38, count 0 2006.169.07:45:56.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.169.07:45:56.20#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.07:45:56.20#ibcon#*before write, iclass 38, count 0 2006.169.07:45:56.20#ibcon#enter sib2, iclass 38, count 0 2006.169.07:45:56.20#ibcon#flushed, iclass 38, count 0 2006.169.07:45:56.20#ibcon#about to write, iclass 38, count 0 2006.169.07:45:56.20#ibcon#wrote, iclass 38, count 0 2006.169.07:45:56.20#ibcon#about to read 3, iclass 38, count 0 2006.169.07:45:56.24#ibcon#read 3, iclass 38, count 0 2006.169.07:45:56.24#ibcon#about to read 4, iclass 38, count 0 2006.169.07:45:56.24#ibcon#read 4, iclass 38, count 0 2006.169.07:45:56.24#ibcon#about to read 5, iclass 38, count 0 2006.169.07:45:56.24#ibcon#read 5, iclass 38, count 0 2006.169.07:45:56.24#ibcon#about to read 6, iclass 38, count 0 2006.169.07:45:56.24#ibcon#read 6, iclass 38, count 0 2006.169.07:45:56.24#ibcon#end of sib2, iclass 38, count 0 2006.169.07:45:56.24#ibcon#*after write, iclass 38, count 0 2006.169.07:45:56.24#ibcon#*before return 0, iclass 38, count 0 2006.169.07:45:56.24#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:45:56.24#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:45:56.24#ibcon#about to clear, iclass 38 cls_cnt 0 2006.169.07:45:56.24#ibcon#cleared, iclass 38 cls_cnt 0 2006.169.07:45:56.24$vc4f8/va=5,7 2006.169.07:45:56.24#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.169.07:45:56.24#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.169.07:45:56.24#ibcon#ireg 11 cls_cnt 2 2006.169.07:45:56.24#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.169.07:45:56.30#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.169.07:45:56.30#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.169.07:45:56.30#ibcon#enter wrdev, iclass 40, count 2 2006.169.07:45:56.30#ibcon#first serial, iclass 40, count 2 2006.169.07:45:56.30#ibcon#enter sib2, iclass 40, count 2 2006.169.07:45:56.30#ibcon#flushed, iclass 40, count 2 2006.169.07:45:56.30#ibcon#about to write, iclass 40, count 2 2006.169.07:45:56.30#ibcon#wrote, iclass 40, count 2 2006.169.07:45:56.30#ibcon#about to read 3, iclass 40, count 2 2006.169.07:45:56.32#ibcon#read 3, iclass 40, count 2 2006.169.07:45:56.32#ibcon#about to read 4, iclass 40, count 2 2006.169.07:45:56.32#ibcon#read 4, iclass 40, count 2 2006.169.07:45:56.32#ibcon#about to read 5, iclass 40, count 2 2006.169.07:45:56.32#ibcon#read 5, iclass 40, count 2 2006.169.07:45:56.32#ibcon#about to read 6, iclass 40, count 2 2006.169.07:45:56.32#ibcon#read 6, iclass 40, count 2 2006.169.07:45:56.32#ibcon#end of sib2, iclass 40, count 2 2006.169.07:45:56.32#ibcon#*mode == 0, iclass 40, count 2 2006.169.07:45:56.32#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.169.07:45:56.32#ibcon#[25=AT05-07\r\n] 2006.169.07:45:56.32#ibcon#*before write, iclass 40, count 2 2006.169.07:45:56.32#ibcon#enter sib2, iclass 40, count 2 2006.169.07:45:56.32#ibcon#flushed, iclass 40, count 2 2006.169.07:45:56.32#ibcon#about to write, iclass 40, count 2 2006.169.07:45:56.32#ibcon#wrote, iclass 40, count 2 2006.169.07:45:56.32#ibcon#about to read 3, iclass 40, count 2 2006.169.07:45:56.35#ibcon#read 3, iclass 40, count 2 2006.169.07:45:56.35#ibcon#about to read 4, iclass 40, count 2 2006.169.07:45:56.35#ibcon#read 4, iclass 40, count 2 2006.169.07:45:56.35#ibcon#about to read 5, iclass 40, count 2 2006.169.07:45:56.35#ibcon#read 5, iclass 40, count 2 2006.169.07:45:56.35#ibcon#about to read 6, iclass 40, count 2 2006.169.07:45:56.35#ibcon#read 6, iclass 40, count 2 2006.169.07:45:56.35#ibcon#end of sib2, iclass 40, count 2 2006.169.07:45:56.35#ibcon#*after write, iclass 40, count 2 2006.169.07:45:56.35#ibcon#*before return 0, iclass 40, count 2 2006.169.07:45:56.35#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.169.07:45:56.35#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.169.07:45:56.35#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.169.07:45:56.35#ibcon#ireg 7 cls_cnt 0 2006.169.07:45:56.35#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.169.07:45:56.47#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.169.07:45:56.47#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.169.07:45:56.47#ibcon#enter wrdev, iclass 40, count 0 2006.169.07:45:56.47#ibcon#first serial, iclass 40, count 0 2006.169.07:45:56.47#ibcon#enter sib2, iclass 40, count 0 2006.169.07:45:56.47#ibcon#flushed, iclass 40, count 0 2006.169.07:45:56.47#ibcon#about to write, iclass 40, count 0 2006.169.07:45:56.47#ibcon#wrote, iclass 40, count 0 2006.169.07:45:56.47#ibcon#about to read 3, iclass 40, count 0 2006.169.07:45:56.49#ibcon#read 3, iclass 40, count 0 2006.169.07:45:56.49#ibcon#about to read 4, iclass 40, count 0 2006.169.07:45:56.49#ibcon#read 4, iclass 40, count 0 2006.169.07:45:56.49#ibcon#about to read 5, iclass 40, count 0 2006.169.07:45:56.49#ibcon#read 5, iclass 40, count 0 2006.169.07:45:56.49#ibcon#about to read 6, iclass 40, count 0 2006.169.07:45:56.49#ibcon#read 6, iclass 40, count 0 2006.169.07:45:56.49#ibcon#end of sib2, iclass 40, count 0 2006.169.07:45:56.49#ibcon#*mode == 0, iclass 40, count 0 2006.169.07:45:56.49#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.169.07:45:56.49#ibcon#[25=USB\r\n] 2006.169.07:45:56.49#ibcon#*before write, iclass 40, count 0 2006.169.07:45:56.49#ibcon#enter sib2, iclass 40, count 0 2006.169.07:45:56.49#ibcon#flushed, iclass 40, count 0 2006.169.07:45:56.49#ibcon#about to write, iclass 40, count 0 2006.169.07:45:56.49#ibcon#wrote, iclass 40, count 0 2006.169.07:45:56.49#ibcon#about to read 3, iclass 40, count 0 2006.169.07:45:56.52#ibcon#read 3, iclass 40, count 0 2006.169.07:45:56.52#ibcon#about to read 4, iclass 40, count 0 2006.169.07:45:56.52#ibcon#read 4, iclass 40, count 0 2006.169.07:45:56.52#ibcon#about to read 5, iclass 40, count 0 2006.169.07:45:56.52#ibcon#read 5, iclass 40, count 0 2006.169.07:45:56.52#ibcon#about to read 6, iclass 40, count 0 2006.169.07:45:56.52#ibcon#read 6, iclass 40, count 0 2006.169.07:45:56.52#ibcon#end of sib2, iclass 40, count 0 2006.169.07:45:56.52#ibcon#*after write, iclass 40, count 0 2006.169.07:45:56.52#ibcon#*before return 0, iclass 40, count 0 2006.169.07:45:56.52#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.169.07:45:56.52#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.169.07:45:56.52#ibcon#about to clear, iclass 40 cls_cnt 0 2006.169.07:45:56.52#ibcon#cleared, iclass 40 cls_cnt 0 2006.169.07:45:56.52$vc4f8/valo=6,772.99 2006.169.07:45:56.52#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.169.07:45:56.52#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.169.07:45:56.52#ibcon#ireg 17 cls_cnt 0 2006.169.07:45:56.52#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.169.07:45:56.52#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.169.07:45:56.52#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.169.07:45:56.52#ibcon#enter wrdev, iclass 4, count 0 2006.169.07:45:56.52#ibcon#first serial, iclass 4, count 0 2006.169.07:45:56.52#ibcon#enter sib2, iclass 4, count 0 2006.169.07:45:56.52#ibcon#flushed, iclass 4, count 0 2006.169.07:45:56.52#ibcon#about to write, iclass 4, count 0 2006.169.07:45:56.52#ibcon#wrote, iclass 4, count 0 2006.169.07:45:56.52#ibcon#about to read 3, iclass 4, count 0 2006.169.07:45:56.54#ibcon#read 3, iclass 4, count 0 2006.169.07:45:56.54#ibcon#about to read 4, iclass 4, count 0 2006.169.07:45:56.54#ibcon#read 4, iclass 4, count 0 2006.169.07:45:56.54#ibcon#about to read 5, iclass 4, count 0 2006.169.07:45:56.54#ibcon#read 5, iclass 4, count 0 2006.169.07:45:56.54#ibcon#about to read 6, iclass 4, count 0 2006.169.07:45:56.54#ibcon#read 6, iclass 4, count 0 2006.169.07:45:56.54#ibcon#end of sib2, iclass 4, count 0 2006.169.07:45:56.54#ibcon#*mode == 0, iclass 4, count 0 2006.169.07:45:56.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.169.07:45:56.54#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.07:45:56.54#ibcon#*before write, iclass 4, count 0 2006.169.07:45:56.54#ibcon#enter sib2, iclass 4, count 0 2006.169.07:45:56.54#ibcon#flushed, iclass 4, count 0 2006.169.07:45:56.54#ibcon#about to write, iclass 4, count 0 2006.169.07:45:56.54#ibcon#wrote, iclass 4, count 0 2006.169.07:45:56.54#ibcon#about to read 3, iclass 4, count 0 2006.169.07:45:56.58#ibcon#read 3, iclass 4, count 0 2006.169.07:45:56.58#ibcon#about to read 4, iclass 4, count 0 2006.169.07:45:56.58#ibcon#read 4, iclass 4, count 0 2006.169.07:45:56.58#ibcon#about to read 5, iclass 4, count 0 2006.169.07:45:56.58#ibcon#read 5, iclass 4, count 0 2006.169.07:45:56.58#ibcon#about to read 6, iclass 4, count 0 2006.169.07:45:56.58#ibcon#read 6, iclass 4, count 0 2006.169.07:45:56.58#ibcon#end of sib2, iclass 4, count 0 2006.169.07:45:56.58#ibcon#*after write, iclass 4, count 0 2006.169.07:45:56.58#ibcon#*before return 0, iclass 4, count 0 2006.169.07:45:56.58#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.169.07:45:56.58#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.169.07:45:56.58#ibcon#about to clear, iclass 4 cls_cnt 0 2006.169.07:45:56.58#ibcon#cleared, iclass 4 cls_cnt 0 2006.169.07:45:56.58$vc4f8/va=6,6 2006.169.07:45:56.58#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.169.07:45:56.58#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.169.07:45:56.58#ibcon#ireg 11 cls_cnt 2 2006.169.07:45:56.58#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.169.07:45:56.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.169.07:45:56.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.169.07:45:56.64#ibcon#enter wrdev, iclass 6, count 2 2006.169.07:45:56.64#ibcon#first serial, iclass 6, count 2 2006.169.07:45:56.64#ibcon#enter sib2, iclass 6, count 2 2006.169.07:45:56.64#ibcon#flushed, iclass 6, count 2 2006.169.07:45:56.64#ibcon#about to write, iclass 6, count 2 2006.169.07:45:56.64#ibcon#wrote, iclass 6, count 2 2006.169.07:45:56.64#ibcon#about to read 3, iclass 6, count 2 2006.169.07:45:56.66#ibcon#read 3, iclass 6, count 2 2006.169.07:45:56.66#ibcon#about to read 4, iclass 6, count 2 2006.169.07:45:56.66#ibcon#read 4, iclass 6, count 2 2006.169.07:45:56.66#ibcon#about to read 5, iclass 6, count 2 2006.169.07:45:56.66#ibcon#read 5, iclass 6, count 2 2006.169.07:45:56.66#ibcon#about to read 6, iclass 6, count 2 2006.169.07:45:56.66#ibcon#read 6, iclass 6, count 2 2006.169.07:45:56.66#ibcon#end of sib2, iclass 6, count 2 2006.169.07:45:56.66#ibcon#*mode == 0, iclass 6, count 2 2006.169.07:45:56.66#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.169.07:45:56.66#ibcon#[25=AT06-06\r\n] 2006.169.07:45:56.66#ibcon#*before write, iclass 6, count 2 2006.169.07:45:56.66#ibcon#enter sib2, iclass 6, count 2 2006.169.07:45:56.66#ibcon#flushed, iclass 6, count 2 2006.169.07:45:56.66#ibcon#about to write, iclass 6, count 2 2006.169.07:45:56.66#ibcon#wrote, iclass 6, count 2 2006.169.07:45:56.66#ibcon#about to read 3, iclass 6, count 2 2006.169.07:45:56.69#ibcon#read 3, iclass 6, count 2 2006.169.07:45:56.69#ibcon#about to read 4, iclass 6, count 2 2006.169.07:45:56.69#ibcon#read 4, iclass 6, count 2 2006.169.07:45:56.69#ibcon#about to read 5, iclass 6, count 2 2006.169.07:45:56.69#ibcon#read 5, iclass 6, count 2 2006.169.07:45:56.69#ibcon#about to read 6, iclass 6, count 2 2006.169.07:45:56.69#ibcon#read 6, iclass 6, count 2 2006.169.07:45:56.69#ibcon#end of sib2, iclass 6, count 2 2006.169.07:45:56.69#ibcon#*after write, iclass 6, count 2 2006.169.07:45:56.69#ibcon#*before return 0, iclass 6, count 2 2006.169.07:45:56.69#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.169.07:45:56.69#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.169.07:45:56.69#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.169.07:45:56.69#ibcon#ireg 7 cls_cnt 0 2006.169.07:45:56.69#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.169.07:45:56.81#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.169.07:45:56.81#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.169.07:45:56.81#ibcon#enter wrdev, iclass 6, count 0 2006.169.07:45:56.81#ibcon#first serial, iclass 6, count 0 2006.169.07:45:56.81#ibcon#enter sib2, iclass 6, count 0 2006.169.07:45:56.81#ibcon#flushed, iclass 6, count 0 2006.169.07:45:56.81#ibcon#about to write, iclass 6, count 0 2006.169.07:45:56.81#ibcon#wrote, iclass 6, count 0 2006.169.07:45:56.81#ibcon#about to read 3, iclass 6, count 0 2006.169.07:45:56.83#ibcon#read 3, iclass 6, count 0 2006.169.07:45:56.83#ibcon#about to read 4, iclass 6, count 0 2006.169.07:45:56.83#ibcon#read 4, iclass 6, count 0 2006.169.07:45:56.83#ibcon#about to read 5, iclass 6, count 0 2006.169.07:45:56.83#ibcon#read 5, iclass 6, count 0 2006.169.07:45:56.83#ibcon#about to read 6, iclass 6, count 0 2006.169.07:45:56.83#ibcon#read 6, iclass 6, count 0 2006.169.07:45:56.83#ibcon#end of sib2, iclass 6, count 0 2006.169.07:45:56.83#ibcon#*mode == 0, iclass 6, count 0 2006.169.07:45:56.83#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.169.07:45:56.83#ibcon#[25=USB\r\n] 2006.169.07:45:56.83#ibcon#*before write, iclass 6, count 0 2006.169.07:45:56.83#ibcon#enter sib2, iclass 6, count 0 2006.169.07:45:56.83#ibcon#flushed, iclass 6, count 0 2006.169.07:45:56.83#ibcon#about to write, iclass 6, count 0 2006.169.07:45:56.83#ibcon#wrote, iclass 6, count 0 2006.169.07:45:56.83#ibcon#about to read 3, iclass 6, count 0 2006.169.07:45:56.86#ibcon#read 3, iclass 6, count 0 2006.169.07:45:56.86#ibcon#about to read 4, iclass 6, count 0 2006.169.07:45:56.86#ibcon#read 4, iclass 6, count 0 2006.169.07:45:56.86#ibcon#about to read 5, iclass 6, count 0 2006.169.07:45:56.86#ibcon#read 5, iclass 6, count 0 2006.169.07:45:56.86#ibcon#about to read 6, iclass 6, count 0 2006.169.07:45:56.86#ibcon#read 6, iclass 6, count 0 2006.169.07:45:56.86#ibcon#end of sib2, iclass 6, count 0 2006.169.07:45:56.86#ibcon#*after write, iclass 6, count 0 2006.169.07:45:56.86#ibcon#*before return 0, iclass 6, count 0 2006.169.07:45:56.86#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.169.07:45:56.86#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.169.07:45:56.86#ibcon#about to clear, iclass 6 cls_cnt 0 2006.169.07:45:56.86#ibcon#cleared, iclass 6 cls_cnt 0 2006.169.07:45:56.86$vc4f8/valo=7,832.99 2006.169.07:45:56.86#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.169.07:45:56.86#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.169.07:45:56.86#ibcon#ireg 17 cls_cnt 0 2006.169.07:45:56.86#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.169.07:45:56.86#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.169.07:45:56.86#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.169.07:45:56.86#ibcon#enter wrdev, iclass 10, count 0 2006.169.07:45:56.86#ibcon#first serial, iclass 10, count 0 2006.169.07:45:56.86#ibcon#enter sib2, iclass 10, count 0 2006.169.07:45:56.86#ibcon#flushed, iclass 10, count 0 2006.169.07:45:56.86#ibcon#about to write, iclass 10, count 0 2006.169.07:45:56.86#ibcon#wrote, iclass 10, count 0 2006.169.07:45:56.86#ibcon#about to read 3, iclass 10, count 0 2006.169.07:45:56.88#ibcon#read 3, iclass 10, count 0 2006.169.07:45:56.88#ibcon#about to read 4, iclass 10, count 0 2006.169.07:45:56.88#ibcon#read 4, iclass 10, count 0 2006.169.07:45:56.88#ibcon#about to read 5, iclass 10, count 0 2006.169.07:45:56.88#ibcon#read 5, iclass 10, count 0 2006.169.07:45:56.88#ibcon#about to read 6, iclass 10, count 0 2006.169.07:45:56.88#ibcon#read 6, iclass 10, count 0 2006.169.07:45:56.88#ibcon#end of sib2, iclass 10, count 0 2006.169.07:45:56.88#ibcon#*mode == 0, iclass 10, count 0 2006.169.07:45:56.88#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.169.07:45:56.88#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.07:45:56.88#ibcon#*before write, iclass 10, count 0 2006.169.07:45:56.88#ibcon#enter sib2, iclass 10, count 0 2006.169.07:45:56.88#ibcon#flushed, iclass 10, count 0 2006.169.07:45:56.88#ibcon#about to write, iclass 10, count 0 2006.169.07:45:56.88#ibcon#wrote, iclass 10, count 0 2006.169.07:45:56.88#ibcon#about to read 3, iclass 10, count 0 2006.169.07:45:56.92#ibcon#read 3, iclass 10, count 0 2006.169.07:45:56.92#ibcon#about to read 4, iclass 10, count 0 2006.169.07:45:56.92#ibcon#read 4, iclass 10, count 0 2006.169.07:45:56.92#ibcon#about to read 5, iclass 10, count 0 2006.169.07:45:56.92#ibcon#read 5, iclass 10, count 0 2006.169.07:45:56.92#ibcon#about to read 6, iclass 10, count 0 2006.169.07:45:56.92#ibcon#read 6, iclass 10, count 0 2006.169.07:45:56.92#ibcon#end of sib2, iclass 10, count 0 2006.169.07:45:56.92#ibcon#*after write, iclass 10, count 0 2006.169.07:45:56.92#ibcon#*before return 0, iclass 10, count 0 2006.169.07:45:56.92#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.169.07:45:56.92#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.169.07:45:56.92#ibcon#about to clear, iclass 10 cls_cnt 0 2006.169.07:45:56.92#ibcon#cleared, iclass 10 cls_cnt 0 2006.169.07:45:56.92$vc4f8/va=7,6 2006.169.07:45:56.92#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.169.07:45:56.92#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.169.07:45:56.92#ibcon#ireg 11 cls_cnt 2 2006.169.07:45:56.92#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.169.07:45:56.98#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.169.07:45:56.98#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.169.07:45:56.98#ibcon#enter wrdev, iclass 12, count 2 2006.169.07:45:56.98#ibcon#first serial, iclass 12, count 2 2006.169.07:45:56.98#ibcon#enter sib2, iclass 12, count 2 2006.169.07:45:56.98#ibcon#flushed, iclass 12, count 2 2006.169.07:45:56.98#ibcon#about to write, iclass 12, count 2 2006.169.07:45:56.98#ibcon#wrote, iclass 12, count 2 2006.169.07:45:56.98#ibcon#about to read 3, iclass 12, count 2 2006.169.07:45:57.00#ibcon#read 3, iclass 12, count 2 2006.169.07:45:57.00#ibcon#about to read 4, iclass 12, count 2 2006.169.07:45:57.00#ibcon#read 4, iclass 12, count 2 2006.169.07:45:57.00#ibcon#about to read 5, iclass 12, count 2 2006.169.07:45:57.00#ibcon#read 5, iclass 12, count 2 2006.169.07:45:57.00#ibcon#about to read 6, iclass 12, count 2 2006.169.07:45:57.00#ibcon#read 6, iclass 12, count 2 2006.169.07:45:57.00#ibcon#end of sib2, iclass 12, count 2 2006.169.07:45:57.00#ibcon#*mode == 0, iclass 12, count 2 2006.169.07:45:57.00#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.169.07:45:57.00#ibcon#[25=AT07-06\r\n] 2006.169.07:45:57.00#ibcon#*before write, iclass 12, count 2 2006.169.07:45:57.00#ibcon#enter sib2, iclass 12, count 2 2006.169.07:45:57.00#ibcon#flushed, iclass 12, count 2 2006.169.07:45:57.00#ibcon#about to write, iclass 12, count 2 2006.169.07:45:57.00#ibcon#wrote, iclass 12, count 2 2006.169.07:45:57.00#ibcon#about to read 3, iclass 12, count 2 2006.169.07:45:57.03#ibcon#read 3, iclass 12, count 2 2006.169.07:45:57.03#ibcon#about to read 4, iclass 12, count 2 2006.169.07:45:57.03#ibcon#read 4, iclass 12, count 2 2006.169.07:45:57.03#ibcon#about to read 5, iclass 12, count 2 2006.169.07:45:57.03#ibcon#read 5, iclass 12, count 2 2006.169.07:45:57.03#ibcon#about to read 6, iclass 12, count 2 2006.169.07:45:57.03#ibcon#read 6, iclass 12, count 2 2006.169.07:45:57.03#ibcon#end of sib2, iclass 12, count 2 2006.169.07:45:57.03#ibcon#*after write, iclass 12, count 2 2006.169.07:45:57.03#ibcon#*before return 0, iclass 12, count 2 2006.169.07:45:57.03#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.169.07:45:57.03#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.169.07:45:57.03#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.169.07:45:57.03#ibcon#ireg 7 cls_cnt 0 2006.169.07:45:57.03#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.169.07:45:57.15#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.169.07:45:57.15#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.169.07:45:57.15#ibcon#enter wrdev, iclass 12, count 0 2006.169.07:45:57.15#ibcon#first serial, iclass 12, count 0 2006.169.07:45:57.15#ibcon#enter sib2, iclass 12, count 0 2006.169.07:45:57.15#ibcon#flushed, iclass 12, count 0 2006.169.07:45:57.15#ibcon#about to write, iclass 12, count 0 2006.169.07:45:57.15#ibcon#wrote, iclass 12, count 0 2006.169.07:45:57.15#ibcon#about to read 3, iclass 12, count 0 2006.169.07:45:57.17#ibcon#read 3, iclass 12, count 0 2006.169.07:45:57.17#ibcon#about to read 4, iclass 12, count 0 2006.169.07:45:57.17#ibcon#read 4, iclass 12, count 0 2006.169.07:45:57.17#ibcon#about to read 5, iclass 12, count 0 2006.169.07:45:57.17#ibcon#read 5, iclass 12, count 0 2006.169.07:45:57.17#ibcon#about to read 6, iclass 12, count 0 2006.169.07:45:57.17#ibcon#read 6, iclass 12, count 0 2006.169.07:45:57.17#ibcon#end of sib2, iclass 12, count 0 2006.169.07:45:57.17#ibcon#*mode == 0, iclass 12, count 0 2006.169.07:45:57.17#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.169.07:45:57.17#ibcon#[25=USB\r\n] 2006.169.07:45:57.17#ibcon#*before write, iclass 12, count 0 2006.169.07:45:57.17#ibcon#enter sib2, iclass 12, count 0 2006.169.07:45:57.17#ibcon#flushed, iclass 12, count 0 2006.169.07:45:57.17#ibcon#about to write, iclass 12, count 0 2006.169.07:45:57.17#ibcon#wrote, iclass 12, count 0 2006.169.07:45:57.17#ibcon#about to read 3, iclass 12, count 0 2006.169.07:45:57.20#ibcon#read 3, iclass 12, count 0 2006.169.07:45:57.20#ibcon#about to read 4, iclass 12, count 0 2006.169.07:45:57.20#ibcon#read 4, iclass 12, count 0 2006.169.07:45:57.20#ibcon#about to read 5, iclass 12, count 0 2006.169.07:45:57.20#ibcon#read 5, iclass 12, count 0 2006.169.07:45:57.20#ibcon#about to read 6, iclass 12, count 0 2006.169.07:45:57.20#ibcon#read 6, iclass 12, count 0 2006.169.07:45:57.20#ibcon#end of sib2, iclass 12, count 0 2006.169.07:45:57.20#ibcon#*after write, iclass 12, count 0 2006.169.07:45:57.20#ibcon#*before return 0, iclass 12, count 0 2006.169.07:45:57.20#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.169.07:45:57.20#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.169.07:45:57.20#ibcon#about to clear, iclass 12 cls_cnt 0 2006.169.07:45:57.20#ibcon#cleared, iclass 12 cls_cnt 0 2006.169.07:45:57.20$vc4f8/valo=8,852.99 2006.169.07:45:57.20#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.169.07:45:57.20#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.169.07:45:57.20#ibcon#ireg 17 cls_cnt 0 2006.169.07:45:57.20#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.169.07:45:57.20#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.169.07:45:57.20#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.169.07:45:57.20#ibcon#enter wrdev, iclass 14, count 0 2006.169.07:45:57.20#ibcon#first serial, iclass 14, count 0 2006.169.07:45:57.20#ibcon#enter sib2, iclass 14, count 0 2006.169.07:45:57.20#ibcon#flushed, iclass 14, count 0 2006.169.07:45:57.20#ibcon#about to write, iclass 14, count 0 2006.169.07:45:57.20#ibcon#wrote, iclass 14, count 0 2006.169.07:45:57.20#ibcon#about to read 3, iclass 14, count 0 2006.169.07:45:57.22#ibcon#read 3, iclass 14, count 0 2006.169.07:45:57.22#ibcon#about to read 4, iclass 14, count 0 2006.169.07:45:57.22#ibcon#read 4, iclass 14, count 0 2006.169.07:45:57.22#ibcon#about to read 5, iclass 14, count 0 2006.169.07:45:57.22#ibcon#read 5, iclass 14, count 0 2006.169.07:45:57.22#ibcon#about to read 6, iclass 14, count 0 2006.169.07:45:57.22#ibcon#read 6, iclass 14, count 0 2006.169.07:45:57.22#ibcon#end of sib2, iclass 14, count 0 2006.169.07:45:57.22#ibcon#*mode == 0, iclass 14, count 0 2006.169.07:45:57.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.169.07:45:57.22#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.07:45:57.22#ibcon#*before write, iclass 14, count 0 2006.169.07:45:57.22#ibcon#enter sib2, iclass 14, count 0 2006.169.07:45:57.22#ibcon#flushed, iclass 14, count 0 2006.169.07:45:57.22#ibcon#about to write, iclass 14, count 0 2006.169.07:45:57.22#ibcon#wrote, iclass 14, count 0 2006.169.07:45:57.22#ibcon#about to read 3, iclass 14, count 0 2006.169.07:45:57.26#ibcon#read 3, iclass 14, count 0 2006.169.07:45:57.26#ibcon#about to read 4, iclass 14, count 0 2006.169.07:45:57.26#ibcon#read 4, iclass 14, count 0 2006.169.07:45:57.26#ibcon#about to read 5, iclass 14, count 0 2006.169.07:45:57.26#ibcon#read 5, iclass 14, count 0 2006.169.07:45:57.26#ibcon#about to read 6, iclass 14, count 0 2006.169.07:45:57.26#ibcon#read 6, iclass 14, count 0 2006.169.07:45:57.26#ibcon#end of sib2, iclass 14, count 0 2006.169.07:45:57.26#ibcon#*after write, iclass 14, count 0 2006.169.07:45:57.26#ibcon#*before return 0, iclass 14, count 0 2006.169.07:45:57.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.169.07:45:57.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.169.07:45:57.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.169.07:45:57.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.169.07:45:57.26$vc4f8/va=8,7 2006.169.07:45:57.26#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.169.07:45:57.26#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.169.07:45:57.26#ibcon#ireg 11 cls_cnt 2 2006.169.07:45:57.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.169.07:45:57.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.169.07:45:57.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.169.07:45:57.32#ibcon#enter wrdev, iclass 16, count 2 2006.169.07:45:57.32#ibcon#first serial, iclass 16, count 2 2006.169.07:45:57.32#ibcon#enter sib2, iclass 16, count 2 2006.169.07:45:57.32#ibcon#flushed, iclass 16, count 2 2006.169.07:45:57.32#ibcon#about to write, iclass 16, count 2 2006.169.07:45:57.32#ibcon#wrote, iclass 16, count 2 2006.169.07:45:57.32#ibcon#about to read 3, iclass 16, count 2 2006.169.07:45:57.34#ibcon#read 3, iclass 16, count 2 2006.169.07:45:57.34#ibcon#about to read 4, iclass 16, count 2 2006.169.07:45:57.34#ibcon#read 4, iclass 16, count 2 2006.169.07:45:57.34#ibcon#about to read 5, iclass 16, count 2 2006.169.07:45:57.34#ibcon#read 5, iclass 16, count 2 2006.169.07:45:57.34#ibcon#about to read 6, iclass 16, count 2 2006.169.07:45:57.34#ibcon#read 6, iclass 16, count 2 2006.169.07:45:57.34#ibcon#end of sib2, iclass 16, count 2 2006.169.07:45:57.34#ibcon#*mode == 0, iclass 16, count 2 2006.169.07:45:57.34#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.169.07:45:57.34#ibcon#[25=AT08-07\r\n] 2006.169.07:45:57.34#ibcon#*before write, iclass 16, count 2 2006.169.07:45:57.34#ibcon#enter sib2, iclass 16, count 2 2006.169.07:45:57.34#ibcon#flushed, iclass 16, count 2 2006.169.07:45:57.34#ibcon#about to write, iclass 16, count 2 2006.169.07:45:57.34#ibcon#wrote, iclass 16, count 2 2006.169.07:45:57.34#ibcon#about to read 3, iclass 16, count 2 2006.169.07:45:57.37#ibcon#read 3, iclass 16, count 2 2006.169.07:45:57.37#ibcon#about to read 4, iclass 16, count 2 2006.169.07:45:57.37#ibcon#read 4, iclass 16, count 2 2006.169.07:45:57.37#ibcon#about to read 5, iclass 16, count 2 2006.169.07:45:57.37#ibcon#read 5, iclass 16, count 2 2006.169.07:45:57.37#ibcon#about to read 6, iclass 16, count 2 2006.169.07:45:57.37#ibcon#read 6, iclass 16, count 2 2006.169.07:45:57.37#ibcon#end of sib2, iclass 16, count 2 2006.169.07:45:57.37#ibcon#*after write, iclass 16, count 2 2006.169.07:45:57.37#ibcon#*before return 0, iclass 16, count 2 2006.169.07:45:57.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.169.07:45:57.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.169.07:45:57.37#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.169.07:45:57.37#ibcon#ireg 7 cls_cnt 0 2006.169.07:45:57.37#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.169.07:45:57.49#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.169.07:45:57.49#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.169.07:45:57.49#ibcon#enter wrdev, iclass 16, count 0 2006.169.07:45:57.49#ibcon#first serial, iclass 16, count 0 2006.169.07:45:57.49#ibcon#enter sib2, iclass 16, count 0 2006.169.07:45:57.49#ibcon#flushed, iclass 16, count 0 2006.169.07:45:57.49#ibcon#about to write, iclass 16, count 0 2006.169.07:45:57.49#ibcon#wrote, iclass 16, count 0 2006.169.07:45:57.49#ibcon#about to read 3, iclass 16, count 0 2006.169.07:45:57.51#ibcon#read 3, iclass 16, count 0 2006.169.07:45:57.51#ibcon#about to read 4, iclass 16, count 0 2006.169.07:45:57.51#ibcon#read 4, iclass 16, count 0 2006.169.07:45:57.51#ibcon#about to read 5, iclass 16, count 0 2006.169.07:45:57.51#ibcon#read 5, iclass 16, count 0 2006.169.07:45:57.51#ibcon#about to read 6, iclass 16, count 0 2006.169.07:45:57.51#ibcon#read 6, iclass 16, count 0 2006.169.07:45:57.51#ibcon#end of sib2, iclass 16, count 0 2006.169.07:45:57.51#ibcon#*mode == 0, iclass 16, count 0 2006.169.07:45:57.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.169.07:45:57.51#ibcon#[25=USB\r\n] 2006.169.07:45:57.51#ibcon#*before write, iclass 16, count 0 2006.169.07:45:57.51#ibcon#enter sib2, iclass 16, count 0 2006.169.07:45:57.51#ibcon#flushed, iclass 16, count 0 2006.169.07:45:57.51#ibcon#about to write, iclass 16, count 0 2006.169.07:45:57.51#ibcon#wrote, iclass 16, count 0 2006.169.07:45:57.51#ibcon#about to read 3, iclass 16, count 0 2006.169.07:45:57.54#ibcon#read 3, iclass 16, count 0 2006.169.07:45:57.54#ibcon#about to read 4, iclass 16, count 0 2006.169.07:45:57.54#ibcon#read 4, iclass 16, count 0 2006.169.07:45:57.54#ibcon#about to read 5, iclass 16, count 0 2006.169.07:45:57.54#ibcon#read 5, iclass 16, count 0 2006.169.07:45:57.54#ibcon#about to read 6, iclass 16, count 0 2006.169.07:45:57.54#ibcon#read 6, iclass 16, count 0 2006.169.07:45:57.54#ibcon#end of sib2, iclass 16, count 0 2006.169.07:45:57.54#ibcon#*after write, iclass 16, count 0 2006.169.07:45:57.54#ibcon#*before return 0, iclass 16, count 0 2006.169.07:45:57.54#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.169.07:45:57.54#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.169.07:45:57.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.169.07:45:57.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.169.07:45:57.54$vc4f8/vblo=1,632.99 2006.169.07:45:57.54#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.169.07:45:57.54#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.169.07:45:57.54#ibcon#ireg 17 cls_cnt 0 2006.169.07:45:57.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:45:57.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:45:57.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:45:57.54#ibcon#enter wrdev, iclass 18, count 0 2006.169.07:45:57.54#ibcon#first serial, iclass 18, count 0 2006.169.07:45:57.54#ibcon#enter sib2, iclass 18, count 0 2006.169.07:45:57.54#ibcon#flushed, iclass 18, count 0 2006.169.07:45:57.54#ibcon#about to write, iclass 18, count 0 2006.169.07:45:57.54#ibcon#wrote, iclass 18, count 0 2006.169.07:45:57.54#ibcon#about to read 3, iclass 18, count 0 2006.169.07:45:57.56#ibcon#read 3, iclass 18, count 0 2006.169.07:45:57.56#ibcon#about to read 4, iclass 18, count 0 2006.169.07:45:57.56#ibcon#read 4, iclass 18, count 0 2006.169.07:45:57.56#ibcon#about to read 5, iclass 18, count 0 2006.169.07:45:57.56#ibcon#read 5, iclass 18, count 0 2006.169.07:45:57.56#ibcon#about to read 6, iclass 18, count 0 2006.169.07:45:57.56#ibcon#read 6, iclass 18, count 0 2006.169.07:45:57.56#ibcon#end of sib2, iclass 18, count 0 2006.169.07:45:57.56#ibcon#*mode == 0, iclass 18, count 0 2006.169.07:45:57.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.169.07:45:57.56#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.07:45:57.56#ibcon#*before write, iclass 18, count 0 2006.169.07:45:57.56#ibcon#enter sib2, iclass 18, count 0 2006.169.07:45:57.56#ibcon#flushed, iclass 18, count 0 2006.169.07:45:57.56#ibcon#about to write, iclass 18, count 0 2006.169.07:45:57.56#ibcon#wrote, iclass 18, count 0 2006.169.07:45:57.56#ibcon#about to read 3, iclass 18, count 0 2006.169.07:45:57.60#ibcon#read 3, iclass 18, count 0 2006.169.07:45:57.60#ibcon#about to read 4, iclass 18, count 0 2006.169.07:45:57.60#ibcon#read 4, iclass 18, count 0 2006.169.07:45:57.60#ibcon#about to read 5, iclass 18, count 0 2006.169.07:45:57.60#ibcon#read 5, iclass 18, count 0 2006.169.07:45:57.60#ibcon#about to read 6, iclass 18, count 0 2006.169.07:45:57.60#ibcon#read 6, iclass 18, count 0 2006.169.07:45:57.60#ibcon#end of sib2, iclass 18, count 0 2006.169.07:45:57.60#ibcon#*after write, iclass 18, count 0 2006.169.07:45:57.60#ibcon#*before return 0, iclass 18, count 0 2006.169.07:45:57.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:45:57.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:45:57.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.169.07:45:57.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.169.07:45:57.60$vc4f8/vb=1,4 2006.169.07:45:57.60#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.169.07:45:57.60#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.169.07:45:57.60#ibcon#ireg 11 cls_cnt 2 2006.169.07:45:57.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.169.07:45:57.60#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.169.07:45:57.60#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.169.07:45:57.60#ibcon#enter wrdev, iclass 20, count 2 2006.169.07:45:57.60#ibcon#first serial, iclass 20, count 2 2006.169.07:45:57.60#ibcon#enter sib2, iclass 20, count 2 2006.169.07:45:57.60#ibcon#flushed, iclass 20, count 2 2006.169.07:45:57.60#ibcon#about to write, iclass 20, count 2 2006.169.07:45:57.60#ibcon#wrote, iclass 20, count 2 2006.169.07:45:57.60#ibcon#about to read 3, iclass 20, count 2 2006.169.07:45:57.62#ibcon#read 3, iclass 20, count 2 2006.169.07:45:57.62#ibcon#about to read 4, iclass 20, count 2 2006.169.07:45:57.62#ibcon#read 4, iclass 20, count 2 2006.169.07:45:57.62#ibcon#about to read 5, iclass 20, count 2 2006.169.07:45:57.62#ibcon#read 5, iclass 20, count 2 2006.169.07:45:57.62#ibcon#about to read 6, iclass 20, count 2 2006.169.07:45:57.62#ibcon#read 6, iclass 20, count 2 2006.169.07:45:57.62#ibcon#end of sib2, iclass 20, count 2 2006.169.07:45:57.62#ibcon#*mode == 0, iclass 20, count 2 2006.169.07:45:57.62#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.169.07:45:57.62#ibcon#[27=AT01-04\r\n] 2006.169.07:45:57.62#ibcon#*before write, iclass 20, count 2 2006.169.07:45:57.62#ibcon#enter sib2, iclass 20, count 2 2006.169.07:45:57.62#ibcon#flushed, iclass 20, count 2 2006.169.07:45:57.62#ibcon#about to write, iclass 20, count 2 2006.169.07:45:57.62#ibcon#wrote, iclass 20, count 2 2006.169.07:45:57.62#ibcon#about to read 3, iclass 20, count 2 2006.169.07:45:57.65#ibcon#read 3, iclass 20, count 2 2006.169.07:45:57.65#ibcon#about to read 4, iclass 20, count 2 2006.169.07:45:57.65#ibcon#read 4, iclass 20, count 2 2006.169.07:45:57.65#ibcon#about to read 5, iclass 20, count 2 2006.169.07:45:57.65#ibcon#read 5, iclass 20, count 2 2006.169.07:45:57.65#ibcon#about to read 6, iclass 20, count 2 2006.169.07:45:57.65#ibcon#read 6, iclass 20, count 2 2006.169.07:45:57.65#ibcon#end of sib2, iclass 20, count 2 2006.169.07:45:57.65#ibcon#*after write, iclass 20, count 2 2006.169.07:45:57.65#ibcon#*before return 0, iclass 20, count 2 2006.169.07:45:57.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.169.07:45:57.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.169.07:45:57.65#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.169.07:45:57.65#ibcon#ireg 7 cls_cnt 0 2006.169.07:45:57.65#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.169.07:45:57.77#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.169.07:45:57.77#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.169.07:45:57.77#ibcon#enter wrdev, iclass 20, count 0 2006.169.07:45:57.77#ibcon#first serial, iclass 20, count 0 2006.169.07:45:57.77#ibcon#enter sib2, iclass 20, count 0 2006.169.07:45:57.77#ibcon#flushed, iclass 20, count 0 2006.169.07:45:57.77#ibcon#about to write, iclass 20, count 0 2006.169.07:45:57.77#ibcon#wrote, iclass 20, count 0 2006.169.07:45:57.77#ibcon#about to read 3, iclass 20, count 0 2006.169.07:45:57.79#ibcon#read 3, iclass 20, count 0 2006.169.07:45:57.79#ibcon#about to read 4, iclass 20, count 0 2006.169.07:45:57.79#ibcon#read 4, iclass 20, count 0 2006.169.07:45:57.79#ibcon#about to read 5, iclass 20, count 0 2006.169.07:45:57.79#ibcon#read 5, iclass 20, count 0 2006.169.07:45:57.79#ibcon#about to read 6, iclass 20, count 0 2006.169.07:45:57.79#ibcon#read 6, iclass 20, count 0 2006.169.07:45:57.79#ibcon#end of sib2, iclass 20, count 0 2006.169.07:45:57.79#ibcon#*mode == 0, iclass 20, count 0 2006.169.07:45:57.79#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.169.07:45:57.79#ibcon#[27=USB\r\n] 2006.169.07:45:57.79#ibcon#*before write, iclass 20, count 0 2006.169.07:45:57.79#ibcon#enter sib2, iclass 20, count 0 2006.169.07:45:57.79#ibcon#flushed, iclass 20, count 0 2006.169.07:45:57.79#ibcon#about to write, iclass 20, count 0 2006.169.07:45:57.79#ibcon#wrote, iclass 20, count 0 2006.169.07:45:57.79#ibcon#about to read 3, iclass 20, count 0 2006.169.07:45:57.82#ibcon#read 3, iclass 20, count 0 2006.169.07:45:57.82#ibcon#about to read 4, iclass 20, count 0 2006.169.07:45:57.82#ibcon#read 4, iclass 20, count 0 2006.169.07:45:57.82#ibcon#about to read 5, iclass 20, count 0 2006.169.07:45:57.82#ibcon#read 5, iclass 20, count 0 2006.169.07:45:57.82#ibcon#about to read 6, iclass 20, count 0 2006.169.07:45:57.82#ibcon#read 6, iclass 20, count 0 2006.169.07:45:57.82#ibcon#end of sib2, iclass 20, count 0 2006.169.07:45:57.82#ibcon#*after write, iclass 20, count 0 2006.169.07:45:57.82#ibcon#*before return 0, iclass 20, count 0 2006.169.07:45:57.82#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.169.07:45:57.82#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.169.07:45:57.82#ibcon#about to clear, iclass 20 cls_cnt 0 2006.169.07:45:57.82#ibcon#cleared, iclass 20 cls_cnt 0 2006.169.07:45:57.82$vc4f8/vblo=2,640.99 2006.169.07:45:57.82#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.169.07:45:57.82#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.169.07:45:57.82#ibcon#ireg 17 cls_cnt 0 2006.169.07:45:57.82#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:45:57.82#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:45:57.82#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:45:57.82#ibcon#enter wrdev, iclass 22, count 0 2006.169.07:45:57.82#ibcon#first serial, iclass 22, count 0 2006.169.07:45:57.82#ibcon#enter sib2, iclass 22, count 0 2006.169.07:45:57.82#ibcon#flushed, iclass 22, count 0 2006.169.07:45:57.82#ibcon#about to write, iclass 22, count 0 2006.169.07:45:57.82#ibcon#wrote, iclass 22, count 0 2006.169.07:45:57.82#ibcon#about to read 3, iclass 22, count 0 2006.169.07:45:57.84#ibcon#read 3, iclass 22, count 0 2006.169.07:45:57.84#ibcon#about to read 4, iclass 22, count 0 2006.169.07:45:57.84#ibcon#read 4, iclass 22, count 0 2006.169.07:45:57.84#ibcon#about to read 5, iclass 22, count 0 2006.169.07:45:57.84#ibcon#read 5, iclass 22, count 0 2006.169.07:45:57.84#ibcon#about to read 6, iclass 22, count 0 2006.169.07:45:57.84#ibcon#read 6, iclass 22, count 0 2006.169.07:45:57.84#ibcon#end of sib2, iclass 22, count 0 2006.169.07:45:57.84#ibcon#*mode == 0, iclass 22, count 0 2006.169.07:45:57.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.169.07:45:57.84#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.07:45:57.84#ibcon#*before write, iclass 22, count 0 2006.169.07:45:57.84#ibcon#enter sib2, iclass 22, count 0 2006.169.07:45:57.84#ibcon#flushed, iclass 22, count 0 2006.169.07:45:57.84#ibcon#about to write, iclass 22, count 0 2006.169.07:45:57.84#ibcon#wrote, iclass 22, count 0 2006.169.07:45:57.84#ibcon#about to read 3, iclass 22, count 0 2006.169.07:45:57.88#ibcon#read 3, iclass 22, count 0 2006.169.07:45:57.88#ibcon#about to read 4, iclass 22, count 0 2006.169.07:45:57.88#ibcon#read 4, iclass 22, count 0 2006.169.07:45:57.88#ibcon#about to read 5, iclass 22, count 0 2006.169.07:45:57.88#ibcon#read 5, iclass 22, count 0 2006.169.07:45:57.88#ibcon#about to read 6, iclass 22, count 0 2006.169.07:45:57.88#ibcon#read 6, iclass 22, count 0 2006.169.07:45:57.88#ibcon#end of sib2, iclass 22, count 0 2006.169.07:45:57.88#ibcon#*after write, iclass 22, count 0 2006.169.07:45:57.88#ibcon#*before return 0, iclass 22, count 0 2006.169.07:45:57.88#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:45:57.88#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:45:57.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.169.07:45:57.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.169.07:45:57.88$vc4f8/vb=2,4 2006.169.07:45:57.88#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.169.07:45:57.88#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.169.07:45:57.88#ibcon#ireg 11 cls_cnt 2 2006.169.07:45:57.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.169.07:45:57.94#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.169.07:45:57.94#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.169.07:45:57.94#ibcon#enter wrdev, iclass 24, count 2 2006.169.07:45:57.94#ibcon#first serial, iclass 24, count 2 2006.169.07:45:57.94#ibcon#enter sib2, iclass 24, count 2 2006.169.07:45:57.94#ibcon#flushed, iclass 24, count 2 2006.169.07:45:57.94#ibcon#about to write, iclass 24, count 2 2006.169.07:45:57.94#ibcon#wrote, iclass 24, count 2 2006.169.07:45:57.94#ibcon#about to read 3, iclass 24, count 2 2006.169.07:45:57.96#ibcon#read 3, iclass 24, count 2 2006.169.07:45:57.96#ibcon#about to read 4, iclass 24, count 2 2006.169.07:45:57.96#ibcon#read 4, iclass 24, count 2 2006.169.07:45:57.96#ibcon#about to read 5, iclass 24, count 2 2006.169.07:45:57.96#ibcon#read 5, iclass 24, count 2 2006.169.07:45:57.96#ibcon#about to read 6, iclass 24, count 2 2006.169.07:45:57.96#ibcon#read 6, iclass 24, count 2 2006.169.07:45:57.96#ibcon#end of sib2, iclass 24, count 2 2006.169.07:45:57.96#ibcon#*mode == 0, iclass 24, count 2 2006.169.07:45:57.96#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.169.07:45:57.96#ibcon#[27=AT02-04\r\n] 2006.169.07:45:57.96#ibcon#*before write, iclass 24, count 2 2006.169.07:45:57.96#ibcon#enter sib2, iclass 24, count 2 2006.169.07:45:57.96#ibcon#flushed, iclass 24, count 2 2006.169.07:45:57.96#ibcon#about to write, iclass 24, count 2 2006.169.07:45:57.96#ibcon#wrote, iclass 24, count 2 2006.169.07:45:57.96#ibcon#about to read 3, iclass 24, count 2 2006.169.07:45:57.99#ibcon#read 3, iclass 24, count 2 2006.169.07:45:57.99#ibcon#about to read 4, iclass 24, count 2 2006.169.07:45:57.99#ibcon#read 4, iclass 24, count 2 2006.169.07:45:57.99#ibcon#about to read 5, iclass 24, count 2 2006.169.07:45:57.99#ibcon#read 5, iclass 24, count 2 2006.169.07:45:57.99#ibcon#about to read 6, iclass 24, count 2 2006.169.07:45:57.99#ibcon#read 6, iclass 24, count 2 2006.169.07:45:57.99#ibcon#end of sib2, iclass 24, count 2 2006.169.07:45:57.99#ibcon#*after write, iclass 24, count 2 2006.169.07:45:57.99#ibcon#*before return 0, iclass 24, count 2 2006.169.07:45:57.99#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.169.07:45:57.99#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.169.07:45:57.99#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.169.07:45:57.99#ibcon#ireg 7 cls_cnt 0 2006.169.07:45:57.99#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.169.07:45:58.11#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.169.07:45:58.11#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.169.07:45:58.11#ibcon#enter wrdev, iclass 24, count 0 2006.169.07:45:58.11#ibcon#first serial, iclass 24, count 0 2006.169.07:45:58.11#ibcon#enter sib2, iclass 24, count 0 2006.169.07:45:58.11#ibcon#flushed, iclass 24, count 0 2006.169.07:45:58.11#ibcon#about to write, iclass 24, count 0 2006.169.07:45:58.11#ibcon#wrote, iclass 24, count 0 2006.169.07:45:58.11#ibcon#about to read 3, iclass 24, count 0 2006.169.07:45:58.13#ibcon#read 3, iclass 24, count 0 2006.169.07:45:58.13#ibcon#about to read 4, iclass 24, count 0 2006.169.07:45:58.13#ibcon#read 4, iclass 24, count 0 2006.169.07:45:58.13#ibcon#about to read 5, iclass 24, count 0 2006.169.07:45:58.13#ibcon#read 5, iclass 24, count 0 2006.169.07:45:58.13#ibcon#about to read 6, iclass 24, count 0 2006.169.07:45:58.13#ibcon#read 6, iclass 24, count 0 2006.169.07:45:58.13#ibcon#end of sib2, iclass 24, count 0 2006.169.07:45:58.13#ibcon#*mode == 0, iclass 24, count 0 2006.169.07:45:58.13#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.169.07:45:58.13#ibcon#[27=USB\r\n] 2006.169.07:45:58.13#ibcon#*before write, iclass 24, count 0 2006.169.07:45:58.13#ibcon#enter sib2, iclass 24, count 0 2006.169.07:45:58.13#ibcon#flushed, iclass 24, count 0 2006.169.07:45:58.13#ibcon#about to write, iclass 24, count 0 2006.169.07:45:58.13#ibcon#wrote, iclass 24, count 0 2006.169.07:45:58.13#ibcon#about to read 3, iclass 24, count 0 2006.169.07:45:58.16#ibcon#read 3, iclass 24, count 0 2006.169.07:45:58.16#ibcon#about to read 4, iclass 24, count 0 2006.169.07:45:58.16#ibcon#read 4, iclass 24, count 0 2006.169.07:45:58.16#ibcon#about to read 5, iclass 24, count 0 2006.169.07:45:58.16#ibcon#read 5, iclass 24, count 0 2006.169.07:45:58.16#ibcon#about to read 6, iclass 24, count 0 2006.169.07:45:58.16#ibcon#read 6, iclass 24, count 0 2006.169.07:45:58.16#ibcon#end of sib2, iclass 24, count 0 2006.169.07:45:58.16#ibcon#*after write, iclass 24, count 0 2006.169.07:45:58.16#ibcon#*before return 0, iclass 24, count 0 2006.169.07:45:58.16#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.169.07:45:58.16#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.169.07:45:58.16#ibcon#about to clear, iclass 24 cls_cnt 0 2006.169.07:45:58.16#ibcon#cleared, iclass 24 cls_cnt 0 2006.169.07:45:58.16$vc4f8/vblo=3,656.99 2006.169.07:45:58.16#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.169.07:45:58.16#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.169.07:45:58.16#ibcon#ireg 17 cls_cnt 0 2006.169.07:45:58.16#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:45:58.16#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:45:58.16#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:45:58.16#ibcon#enter wrdev, iclass 26, count 0 2006.169.07:45:58.16#ibcon#first serial, iclass 26, count 0 2006.169.07:45:58.16#ibcon#enter sib2, iclass 26, count 0 2006.169.07:45:58.16#ibcon#flushed, iclass 26, count 0 2006.169.07:45:58.16#ibcon#about to write, iclass 26, count 0 2006.169.07:45:58.16#ibcon#wrote, iclass 26, count 0 2006.169.07:45:58.16#ibcon#about to read 3, iclass 26, count 0 2006.169.07:45:58.19#ibcon#read 3, iclass 26, count 0 2006.169.07:45:58.19#ibcon#about to read 4, iclass 26, count 0 2006.169.07:45:58.19#ibcon#read 4, iclass 26, count 0 2006.169.07:45:58.19#ibcon#about to read 5, iclass 26, count 0 2006.169.07:45:58.19#ibcon#read 5, iclass 26, count 0 2006.169.07:45:58.19#ibcon#about to read 6, iclass 26, count 0 2006.169.07:45:58.19#ibcon#read 6, iclass 26, count 0 2006.169.07:45:58.19#ibcon#end of sib2, iclass 26, count 0 2006.169.07:45:58.19#ibcon#*mode == 0, iclass 26, count 0 2006.169.07:45:58.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.169.07:45:58.19#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.07:45:58.19#ibcon#*before write, iclass 26, count 0 2006.169.07:45:58.19#ibcon#enter sib2, iclass 26, count 0 2006.169.07:45:58.19#ibcon#flushed, iclass 26, count 0 2006.169.07:45:58.19#ibcon#about to write, iclass 26, count 0 2006.169.07:45:58.19#ibcon#wrote, iclass 26, count 0 2006.169.07:45:58.19#ibcon#about to read 3, iclass 26, count 0 2006.169.07:45:58.23#ibcon#read 3, iclass 26, count 0 2006.169.07:45:58.23#ibcon#about to read 4, iclass 26, count 0 2006.169.07:45:58.23#ibcon#read 4, iclass 26, count 0 2006.169.07:45:58.23#ibcon#about to read 5, iclass 26, count 0 2006.169.07:45:58.23#ibcon#read 5, iclass 26, count 0 2006.169.07:45:58.23#ibcon#about to read 6, iclass 26, count 0 2006.169.07:45:58.23#ibcon#read 6, iclass 26, count 0 2006.169.07:45:58.23#ibcon#end of sib2, iclass 26, count 0 2006.169.07:45:58.23#ibcon#*after write, iclass 26, count 0 2006.169.07:45:58.23#ibcon#*before return 0, iclass 26, count 0 2006.169.07:45:58.23#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:45:58.23#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:45:58.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.169.07:45:58.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.169.07:45:58.23$vc4f8/vb=3,4 2006.169.07:45:58.23#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.169.07:45:58.23#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.169.07:45:58.23#ibcon#ireg 11 cls_cnt 2 2006.169.07:45:58.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.169.07:45:58.28#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.169.07:45:58.28#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.169.07:45:58.28#ibcon#enter wrdev, iclass 28, count 2 2006.169.07:45:58.28#ibcon#first serial, iclass 28, count 2 2006.169.07:45:58.28#ibcon#enter sib2, iclass 28, count 2 2006.169.07:45:58.28#ibcon#flushed, iclass 28, count 2 2006.169.07:45:58.28#ibcon#about to write, iclass 28, count 2 2006.169.07:45:58.28#ibcon#wrote, iclass 28, count 2 2006.169.07:45:58.28#ibcon#about to read 3, iclass 28, count 2 2006.169.07:45:58.30#ibcon#read 3, iclass 28, count 2 2006.169.07:45:58.30#ibcon#about to read 4, iclass 28, count 2 2006.169.07:45:58.30#ibcon#read 4, iclass 28, count 2 2006.169.07:45:58.30#ibcon#about to read 5, iclass 28, count 2 2006.169.07:45:58.30#ibcon#read 5, iclass 28, count 2 2006.169.07:45:58.30#ibcon#about to read 6, iclass 28, count 2 2006.169.07:45:58.30#ibcon#read 6, iclass 28, count 2 2006.169.07:45:58.30#ibcon#end of sib2, iclass 28, count 2 2006.169.07:45:58.30#ibcon#*mode == 0, iclass 28, count 2 2006.169.07:45:58.30#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.169.07:45:58.30#ibcon#[27=AT03-04\r\n] 2006.169.07:45:58.30#ibcon#*before write, iclass 28, count 2 2006.169.07:45:58.30#ibcon#enter sib2, iclass 28, count 2 2006.169.07:45:58.30#ibcon#flushed, iclass 28, count 2 2006.169.07:45:58.30#ibcon#about to write, iclass 28, count 2 2006.169.07:45:58.30#ibcon#wrote, iclass 28, count 2 2006.169.07:45:58.30#ibcon#about to read 3, iclass 28, count 2 2006.169.07:45:58.33#ibcon#read 3, iclass 28, count 2 2006.169.07:45:58.33#ibcon#about to read 4, iclass 28, count 2 2006.169.07:45:58.33#ibcon#read 4, iclass 28, count 2 2006.169.07:45:58.33#ibcon#about to read 5, iclass 28, count 2 2006.169.07:45:58.33#ibcon#read 5, iclass 28, count 2 2006.169.07:45:58.33#ibcon#about to read 6, iclass 28, count 2 2006.169.07:45:58.33#ibcon#read 6, iclass 28, count 2 2006.169.07:45:58.33#ibcon#end of sib2, iclass 28, count 2 2006.169.07:45:58.33#ibcon#*after write, iclass 28, count 2 2006.169.07:45:58.33#ibcon#*before return 0, iclass 28, count 2 2006.169.07:45:58.33#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.169.07:45:58.33#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.169.07:45:58.33#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.169.07:45:58.33#ibcon#ireg 7 cls_cnt 0 2006.169.07:45:58.33#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.169.07:45:58.45#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.169.07:45:58.45#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.169.07:45:58.45#ibcon#enter wrdev, iclass 28, count 0 2006.169.07:45:58.45#ibcon#first serial, iclass 28, count 0 2006.169.07:45:58.45#ibcon#enter sib2, iclass 28, count 0 2006.169.07:45:58.45#ibcon#flushed, iclass 28, count 0 2006.169.07:45:58.45#ibcon#about to write, iclass 28, count 0 2006.169.07:45:58.45#ibcon#wrote, iclass 28, count 0 2006.169.07:45:58.45#ibcon#about to read 3, iclass 28, count 0 2006.169.07:45:58.47#ibcon#read 3, iclass 28, count 0 2006.169.07:45:58.47#ibcon#about to read 4, iclass 28, count 0 2006.169.07:45:58.47#ibcon#read 4, iclass 28, count 0 2006.169.07:45:58.47#ibcon#about to read 5, iclass 28, count 0 2006.169.07:45:58.47#ibcon#read 5, iclass 28, count 0 2006.169.07:45:58.47#ibcon#about to read 6, iclass 28, count 0 2006.169.07:45:58.47#ibcon#read 6, iclass 28, count 0 2006.169.07:45:58.47#ibcon#end of sib2, iclass 28, count 0 2006.169.07:45:58.47#ibcon#*mode == 0, iclass 28, count 0 2006.169.07:45:58.47#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.169.07:45:58.47#ibcon#[27=USB\r\n] 2006.169.07:45:58.47#ibcon#*before write, iclass 28, count 0 2006.169.07:45:58.47#ibcon#enter sib2, iclass 28, count 0 2006.169.07:45:58.47#ibcon#flushed, iclass 28, count 0 2006.169.07:45:58.47#ibcon#about to write, iclass 28, count 0 2006.169.07:45:58.47#ibcon#wrote, iclass 28, count 0 2006.169.07:45:58.47#ibcon#about to read 3, iclass 28, count 0 2006.169.07:45:58.50#ibcon#read 3, iclass 28, count 0 2006.169.07:45:58.50#ibcon#about to read 4, iclass 28, count 0 2006.169.07:45:58.50#ibcon#read 4, iclass 28, count 0 2006.169.07:45:58.50#ibcon#about to read 5, iclass 28, count 0 2006.169.07:45:58.50#ibcon#read 5, iclass 28, count 0 2006.169.07:45:58.50#ibcon#about to read 6, iclass 28, count 0 2006.169.07:45:58.50#ibcon#read 6, iclass 28, count 0 2006.169.07:45:58.50#ibcon#end of sib2, iclass 28, count 0 2006.169.07:45:58.50#ibcon#*after write, iclass 28, count 0 2006.169.07:45:58.50#ibcon#*before return 0, iclass 28, count 0 2006.169.07:45:58.50#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.169.07:45:58.50#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.169.07:45:58.50#ibcon#about to clear, iclass 28 cls_cnt 0 2006.169.07:45:58.50#ibcon#cleared, iclass 28 cls_cnt 0 2006.169.07:45:58.50$vc4f8/vblo=4,712.99 2006.169.07:45:58.50#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.169.07:45:58.50#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.169.07:45:58.50#ibcon#ireg 17 cls_cnt 0 2006.169.07:45:58.50#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:45:58.50#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:45:58.50#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:45:58.50#ibcon#enter wrdev, iclass 30, count 0 2006.169.07:45:58.50#ibcon#first serial, iclass 30, count 0 2006.169.07:45:58.50#ibcon#enter sib2, iclass 30, count 0 2006.169.07:45:58.50#ibcon#flushed, iclass 30, count 0 2006.169.07:45:58.50#ibcon#about to write, iclass 30, count 0 2006.169.07:45:58.50#ibcon#wrote, iclass 30, count 0 2006.169.07:45:58.50#ibcon#about to read 3, iclass 30, count 0 2006.169.07:45:58.52#ibcon#read 3, iclass 30, count 0 2006.169.07:45:58.52#ibcon#about to read 4, iclass 30, count 0 2006.169.07:45:58.52#ibcon#read 4, iclass 30, count 0 2006.169.07:45:58.52#ibcon#about to read 5, iclass 30, count 0 2006.169.07:45:58.52#ibcon#read 5, iclass 30, count 0 2006.169.07:45:58.52#ibcon#about to read 6, iclass 30, count 0 2006.169.07:45:58.52#ibcon#read 6, iclass 30, count 0 2006.169.07:45:58.52#ibcon#end of sib2, iclass 30, count 0 2006.169.07:45:58.52#ibcon#*mode == 0, iclass 30, count 0 2006.169.07:45:58.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.169.07:45:58.52#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.07:45:58.52#ibcon#*before write, iclass 30, count 0 2006.169.07:45:58.52#ibcon#enter sib2, iclass 30, count 0 2006.169.07:45:58.52#ibcon#flushed, iclass 30, count 0 2006.169.07:45:58.52#ibcon#about to write, iclass 30, count 0 2006.169.07:45:58.52#ibcon#wrote, iclass 30, count 0 2006.169.07:45:58.52#ibcon#about to read 3, iclass 30, count 0 2006.169.07:45:58.56#ibcon#read 3, iclass 30, count 0 2006.169.07:45:58.56#ibcon#about to read 4, iclass 30, count 0 2006.169.07:45:58.56#ibcon#read 4, iclass 30, count 0 2006.169.07:45:58.56#ibcon#about to read 5, iclass 30, count 0 2006.169.07:45:58.56#ibcon#read 5, iclass 30, count 0 2006.169.07:45:58.56#ibcon#about to read 6, iclass 30, count 0 2006.169.07:45:58.56#ibcon#read 6, iclass 30, count 0 2006.169.07:45:58.56#ibcon#end of sib2, iclass 30, count 0 2006.169.07:45:58.56#ibcon#*after write, iclass 30, count 0 2006.169.07:45:58.56#ibcon#*before return 0, iclass 30, count 0 2006.169.07:45:58.56#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:45:58.56#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:45:58.56#ibcon#about to clear, iclass 30 cls_cnt 0 2006.169.07:45:58.56#ibcon#cleared, iclass 30 cls_cnt 0 2006.169.07:45:58.56$vc4f8/vb=4,4 2006.169.07:45:58.56#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.169.07:45:58.56#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.169.07:45:58.56#ibcon#ireg 11 cls_cnt 2 2006.169.07:45:58.56#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:45:58.62#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:45:58.62#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:45:58.62#ibcon#enter wrdev, iclass 32, count 2 2006.169.07:45:58.62#ibcon#first serial, iclass 32, count 2 2006.169.07:45:58.62#ibcon#enter sib2, iclass 32, count 2 2006.169.07:45:58.62#ibcon#flushed, iclass 32, count 2 2006.169.07:45:58.62#ibcon#about to write, iclass 32, count 2 2006.169.07:45:58.62#ibcon#wrote, iclass 32, count 2 2006.169.07:45:58.62#ibcon#about to read 3, iclass 32, count 2 2006.169.07:45:58.64#ibcon#read 3, iclass 32, count 2 2006.169.07:45:58.64#ibcon#about to read 4, iclass 32, count 2 2006.169.07:45:58.64#ibcon#read 4, iclass 32, count 2 2006.169.07:45:58.64#ibcon#about to read 5, iclass 32, count 2 2006.169.07:45:58.64#ibcon#read 5, iclass 32, count 2 2006.169.07:45:58.64#ibcon#about to read 6, iclass 32, count 2 2006.169.07:45:58.64#ibcon#read 6, iclass 32, count 2 2006.169.07:45:58.64#ibcon#end of sib2, iclass 32, count 2 2006.169.07:45:58.64#ibcon#*mode == 0, iclass 32, count 2 2006.169.07:45:58.64#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.169.07:45:58.64#ibcon#[27=AT04-04\r\n] 2006.169.07:45:58.64#ibcon#*before write, iclass 32, count 2 2006.169.07:45:58.64#ibcon#enter sib2, iclass 32, count 2 2006.169.07:45:58.64#ibcon#flushed, iclass 32, count 2 2006.169.07:45:58.64#ibcon#about to write, iclass 32, count 2 2006.169.07:45:58.64#ibcon#wrote, iclass 32, count 2 2006.169.07:45:58.64#ibcon#about to read 3, iclass 32, count 2 2006.169.07:45:58.67#ibcon#read 3, iclass 32, count 2 2006.169.07:45:58.67#ibcon#about to read 4, iclass 32, count 2 2006.169.07:45:58.67#ibcon#read 4, iclass 32, count 2 2006.169.07:45:58.67#ibcon#about to read 5, iclass 32, count 2 2006.169.07:45:58.67#ibcon#read 5, iclass 32, count 2 2006.169.07:45:58.67#ibcon#about to read 6, iclass 32, count 2 2006.169.07:45:58.67#ibcon#read 6, iclass 32, count 2 2006.169.07:45:58.67#ibcon#end of sib2, iclass 32, count 2 2006.169.07:45:58.67#ibcon#*after write, iclass 32, count 2 2006.169.07:45:58.67#ibcon#*before return 0, iclass 32, count 2 2006.169.07:45:58.67#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:45:58.67#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:45:58.67#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.169.07:45:58.67#ibcon#ireg 7 cls_cnt 0 2006.169.07:45:58.67#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:45:58.79#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:45:58.79#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:45:58.79#ibcon#enter wrdev, iclass 32, count 0 2006.169.07:45:58.79#ibcon#first serial, iclass 32, count 0 2006.169.07:45:58.79#ibcon#enter sib2, iclass 32, count 0 2006.169.07:45:58.79#ibcon#flushed, iclass 32, count 0 2006.169.07:45:58.79#ibcon#about to write, iclass 32, count 0 2006.169.07:45:58.79#ibcon#wrote, iclass 32, count 0 2006.169.07:45:58.79#ibcon#about to read 3, iclass 32, count 0 2006.169.07:45:58.81#ibcon#read 3, iclass 32, count 0 2006.169.07:45:58.81#ibcon#about to read 4, iclass 32, count 0 2006.169.07:45:58.81#ibcon#read 4, iclass 32, count 0 2006.169.07:45:58.81#ibcon#about to read 5, iclass 32, count 0 2006.169.07:45:58.81#ibcon#read 5, iclass 32, count 0 2006.169.07:45:58.81#ibcon#about to read 6, iclass 32, count 0 2006.169.07:45:58.81#ibcon#read 6, iclass 32, count 0 2006.169.07:45:58.81#ibcon#end of sib2, iclass 32, count 0 2006.169.07:45:58.81#ibcon#*mode == 0, iclass 32, count 0 2006.169.07:45:58.81#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.169.07:45:58.81#ibcon#[27=USB\r\n] 2006.169.07:45:58.81#ibcon#*before write, iclass 32, count 0 2006.169.07:45:58.81#ibcon#enter sib2, iclass 32, count 0 2006.169.07:45:58.81#ibcon#flushed, iclass 32, count 0 2006.169.07:45:58.81#ibcon#about to write, iclass 32, count 0 2006.169.07:45:58.81#ibcon#wrote, iclass 32, count 0 2006.169.07:45:58.81#ibcon#about to read 3, iclass 32, count 0 2006.169.07:45:58.84#ibcon#read 3, iclass 32, count 0 2006.169.07:45:58.84#ibcon#about to read 4, iclass 32, count 0 2006.169.07:45:58.84#ibcon#read 4, iclass 32, count 0 2006.169.07:45:58.84#ibcon#about to read 5, iclass 32, count 0 2006.169.07:45:58.84#ibcon#read 5, iclass 32, count 0 2006.169.07:45:58.84#ibcon#about to read 6, iclass 32, count 0 2006.169.07:45:58.84#ibcon#read 6, iclass 32, count 0 2006.169.07:45:58.84#ibcon#end of sib2, iclass 32, count 0 2006.169.07:45:58.84#ibcon#*after write, iclass 32, count 0 2006.169.07:45:58.84#ibcon#*before return 0, iclass 32, count 0 2006.169.07:45:58.84#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:45:58.84#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:45:58.84#ibcon#about to clear, iclass 32 cls_cnt 0 2006.169.07:45:58.84#ibcon#cleared, iclass 32 cls_cnt 0 2006.169.07:45:58.84$vc4f8/vblo=5,744.99 2006.169.07:45:58.84#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.169.07:45:58.84#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.169.07:45:58.84#ibcon#ireg 17 cls_cnt 0 2006.169.07:45:58.84#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:45:58.84#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:45:58.84#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:45:58.84#ibcon#enter wrdev, iclass 34, count 0 2006.169.07:45:58.84#ibcon#first serial, iclass 34, count 0 2006.169.07:45:58.84#ibcon#enter sib2, iclass 34, count 0 2006.169.07:45:58.84#ibcon#flushed, iclass 34, count 0 2006.169.07:45:58.84#ibcon#about to write, iclass 34, count 0 2006.169.07:45:58.84#ibcon#wrote, iclass 34, count 0 2006.169.07:45:58.84#ibcon#about to read 3, iclass 34, count 0 2006.169.07:45:58.86#ibcon#read 3, iclass 34, count 0 2006.169.07:45:58.86#ibcon#about to read 4, iclass 34, count 0 2006.169.07:45:58.86#ibcon#read 4, iclass 34, count 0 2006.169.07:45:58.86#ibcon#about to read 5, iclass 34, count 0 2006.169.07:45:58.86#ibcon#read 5, iclass 34, count 0 2006.169.07:45:58.86#ibcon#about to read 6, iclass 34, count 0 2006.169.07:45:58.86#ibcon#read 6, iclass 34, count 0 2006.169.07:45:58.86#ibcon#end of sib2, iclass 34, count 0 2006.169.07:45:58.86#ibcon#*mode == 0, iclass 34, count 0 2006.169.07:45:58.86#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.169.07:45:58.86#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.07:45:58.86#ibcon#*before write, iclass 34, count 0 2006.169.07:45:58.86#ibcon#enter sib2, iclass 34, count 0 2006.169.07:45:58.86#ibcon#flushed, iclass 34, count 0 2006.169.07:45:58.86#ibcon#about to write, iclass 34, count 0 2006.169.07:45:58.86#ibcon#wrote, iclass 34, count 0 2006.169.07:45:58.86#ibcon#about to read 3, iclass 34, count 0 2006.169.07:45:58.90#ibcon#read 3, iclass 34, count 0 2006.169.07:45:58.90#ibcon#about to read 4, iclass 34, count 0 2006.169.07:45:58.90#ibcon#read 4, iclass 34, count 0 2006.169.07:45:58.90#ibcon#about to read 5, iclass 34, count 0 2006.169.07:45:58.90#ibcon#read 5, iclass 34, count 0 2006.169.07:45:58.90#ibcon#about to read 6, iclass 34, count 0 2006.169.07:45:58.90#ibcon#read 6, iclass 34, count 0 2006.169.07:45:58.90#ibcon#end of sib2, iclass 34, count 0 2006.169.07:45:58.90#ibcon#*after write, iclass 34, count 0 2006.169.07:45:58.90#ibcon#*before return 0, iclass 34, count 0 2006.169.07:45:58.90#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:45:58.90#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:45:58.90#ibcon#about to clear, iclass 34 cls_cnt 0 2006.169.07:45:58.90#ibcon#cleared, iclass 34 cls_cnt 0 2006.169.07:45:58.90$vc4f8/vb=5,4 2006.169.07:45:58.90#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.169.07:45:58.90#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.169.07:45:58.90#ibcon#ireg 11 cls_cnt 2 2006.169.07:45:58.90#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.169.07:45:58.96#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.169.07:45:58.96#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.169.07:45:58.96#ibcon#enter wrdev, iclass 36, count 2 2006.169.07:45:58.96#ibcon#first serial, iclass 36, count 2 2006.169.07:45:58.96#ibcon#enter sib2, iclass 36, count 2 2006.169.07:45:58.96#ibcon#flushed, iclass 36, count 2 2006.169.07:45:58.96#ibcon#about to write, iclass 36, count 2 2006.169.07:45:58.96#ibcon#wrote, iclass 36, count 2 2006.169.07:45:58.96#ibcon#about to read 3, iclass 36, count 2 2006.169.07:45:58.98#ibcon#read 3, iclass 36, count 2 2006.169.07:45:58.98#ibcon#about to read 4, iclass 36, count 2 2006.169.07:45:58.98#ibcon#read 4, iclass 36, count 2 2006.169.07:45:58.98#ibcon#about to read 5, iclass 36, count 2 2006.169.07:45:58.98#ibcon#read 5, iclass 36, count 2 2006.169.07:45:58.98#ibcon#about to read 6, iclass 36, count 2 2006.169.07:45:58.98#ibcon#read 6, iclass 36, count 2 2006.169.07:45:58.98#ibcon#end of sib2, iclass 36, count 2 2006.169.07:45:58.98#ibcon#*mode == 0, iclass 36, count 2 2006.169.07:45:58.98#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.169.07:45:58.98#ibcon#[27=AT05-04\r\n] 2006.169.07:45:58.98#ibcon#*before write, iclass 36, count 2 2006.169.07:45:58.98#ibcon#enter sib2, iclass 36, count 2 2006.169.07:45:58.98#ibcon#flushed, iclass 36, count 2 2006.169.07:45:58.98#ibcon#about to write, iclass 36, count 2 2006.169.07:45:58.98#ibcon#wrote, iclass 36, count 2 2006.169.07:45:58.98#ibcon#about to read 3, iclass 36, count 2 2006.169.07:45:59.01#ibcon#read 3, iclass 36, count 2 2006.169.07:45:59.01#ibcon#about to read 4, iclass 36, count 2 2006.169.07:45:59.01#ibcon#read 4, iclass 36, count 2 2006.169.07:45:59.01#ibcon#about to read 5, iclass 36, count 2 2006.169.07:45:59.01#ibcon#read 5, iclass 36, count 2 2006.169.07:45:59.01#ibcon#about to read 6, iclass 36, count 2 2006.169.07:45:59.01#ibcon#read 6, iclass 36, count 2 2006.169.07:45:59.01#ibcon#end of sib2, iclass 36, count 2 2006.169.07:45:59.01#ibcon#*after write, iclass 36, count 2 2006.169.07:45:59.01#ibcon#*before return 0, iclass 36, count 2 2006.169.07:45:59.01#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.169.07:45:59.01#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.169.07:45:59.01#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.169.07:45:59.01#ibcon#ireg 7 cls_cnt 0 2006.169.07:45:59.01#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.169.07:45:59.13#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.169.07:45:59.13#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.169.07:45:59.13#ibcon#enter wrdev, iclass 36, count 0 2006.169.07:45:59.13#ibcon#first serial, iclass 36, count 0 2006.169.07:45:59.13#ibcon#enter sib2, iclass 36, count 0 2006.169.07:45:59.13#ibcon#flushed, iclass 36, count 0 2006.169.07:45:59.13#ibcon#about to write, iclass 36, count 0 2006.169.07:45:59.13#ibcon#wrote, iclass 36, count 0 2006.169.07:45:59.13#ibcon#about to read 3, iclass 36, count 0 2006.169.07:45:59.15#ibcon#read 3, iclass 36, count 0 2006.169.07:45:59.15#ibcon#about to read 4, iclass 36, count 0 2006.169.07:45:59.15#ibcon#read 4, iclass 36, count 0 2006.169.07:45:59.15#ibcon#about to read 5, iclass 36, count 0 2006.169.07:45:59.15#ibcon#read 5, iclass 36, count 0 2006.169.07:45:59.15#ibcon#about to read 6, iclass 36, count 0 2006.169.07:45:59.15#ibcon#read 6, iclass 36, count 0 2006.169.07:45:59.15#ibcon#end of sib2, iclass 36, count 0 2006.169.07:45:59.15#ibcon#*mode == 0, iclass 36, count 0 2006.169.07:45:59.15#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.169.07:45:59.15#ibcon#[27=USB\r\n] 2006.169.07:45:59.15#ibcon#*before write, iclass 36, count 0 2006.169.07:45:59.15#ibcon#enter sib2, iclass 36, count 0 2006.169.07:45:59.15#ibcon#flushed, iclass 36, count 0 2006.169.07:45:59.15#ibcon#about to write, iclass 36, count 0 2006.169.07:45:59.15#ibcon#wrote, iclass 36, count 0 2006.169.07:45:59.15#ibcon#about to read 3, iclass 36, count 0 2006.169.07:45:59.18#ibcon#read 3, iclass 36, count 0 2006.169.07:45:59.18#ibcon#about to read 4, iclass 36, count 0 2006.169.07:45:59.18#ibcon#read 4, iclass 36, count 0 2006.169.07:45:59.18#ibcon#about to read 5, iclass 36, count 0 2006.169.07:45:59.18#ibcon#read 5, iclass 36, count 0 2006.169.07:45:59.18#ibcon#about to read 6, iclass 36, count 0 2006.169.07:45:59.18#ibcon#read 6, iclass 36, count 0 2006.169.07:45:59.18#ibcon#end of sib2, iclass 36, count 0 2006.169.07:45:59.18#ibcon#*after write, iclass 36, count 0 2006.169.07:45:59.18#ibcon#*before return 0, iclass 36, count 0 2006.169.07:45:59.18#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.169.07:45:59.18#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.169.07:45:59.18#ibcon#about to clear, iclass 36 cls_cnt 0 2006.169.07:45:59.18#ibcon#cleared, iclass 36 cls_cnt 0 2006.169.07:45:59.18$vc4f8/vblo=6,752.99 2006.169.07:45:59.18#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.169.07:45:59.18#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.169.07:45:59.18#ibcon#ireg 17 cls_cnt 0 2006.169.07:45:59.18#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:45:59.18#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:45:59.18#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:45:59.18#ibcon#enter wrdev, iclass 38, count 0 2006.169.07:45:59.18#ibcon#first serial, iclass 38, count 0 2006.169.07:45:59.18#ibcon#enter sib2, iclass 38, count 0 2006.169.07:45:59.18#ibcon#flushed, iclass 38, count 0 2006.169.07:45:59.18#ibcon#about to write, iclass 38, count 0 2006.169.07:45:59.18#ibcon#wrote, iclass 38, count 0 2006.169.07:45:59.18#ibcon#about to read 3, iclass 38, count 0 2006.169.07:45:59.20#ibcon#read 3, iclass 38, count 0 2006.169.07:45:59.20#ibcon#about to read 4, iclass 38, count 0 2006.169.07:45:59.20#ibcon#read 4, iclass 38, count 0 2006.169.07:45:59.20#ibcon#about to read 5, iclass 38, count 0 2006.169.07:45:59.20#ibcon#read 5, iclass 38, count 0 2006.169.07:45:59.20#ibcon#about to read 6, iclass 38, count 0 2006.169.07:45:59.20#ibcon#read 6, iclass 38, count 0 2006.169.07:45:59.20#ibcon#end of sib2, iclass 38, count 0 2006.169.07:45:59.20#ibcon#*mode == 0, iclass 38, count 0 2006.169.07:45:59.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.169.07:45:59.20#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.07:45:59.20#ibcon#*before write, iclass 38, count 0 2006.169.07:45:59.20#ibcon#enter sib2, iclass 38, count 0 2006.169.07:45:59.20#ibcon#flushed, iclass 38, count 0 2006.169.07:45:59.20#ibcon#about to write, iclass 38, count 0 2006.169.07:45:59.20#ibcon#wrote, iclass 38, count 0 2006.169.07:45:59.20#ibcon#about to read 3, iclass 38, count 0 2006.169.07:45:59.24#ibcon#read 3, iclass 38, count 0 2006.169.07:45:59.24#ibcon#about to read 4, iclass 38, count 0 2006.169.07:45:59.24#ibcon#read 4, iclass 38, count 0 2006.169.07:45:59.24#ibcon#about to read 5, iclass 38, count 0 2006.169.07:45:59.24#ibcon#read 5, iclass 38, count 0 2006.169.07:45:59.24#ibcon#about to read 6, iclass 38, count 0 2006.169.07:45:59.24#ibcon#read 6, iclass 38, count 0 2006.169.07:45:59.24#ibcon#end of sib2, iclass 38, count 0 2006.169.07:45:59.24#ibcon#*after write, iclass 38, count 0 2006.169.07:45:59.24#ibcon#*before return 0, iclass 38, count 0 2006.169.07:45:59.24#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:45:59.24#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:45:59.24#ibcon#about to clear, iclass 38 cls_cnt 0 2006.169.07:45:59.24#ibcon#cleared, iclass 38 cls_cnt 0 2006.169.07:45:59.24$vc4f8/vb=6,4 2006.169.07:45:59.24#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.169.07:45:59.24#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.169.07:45:59.24#ibcon#ireg 11 cls_cnt 2 2006.169.07:45:59.24#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.169.07:45:59.30#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.169.07:45:59.30#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.169.07:45:59.30#ibcon#enter wrdev, iclass 40, count 2 2006.169.07:45:59.30#ibcon#first serial, iclass 40, count 2 2006.169.07:45:59.30#ibcon#enter sib2, iclass 40, count 2 2006.169.07:45:59.30#ibcon#flushed, iclass 40, count 2 2006.169.07:45:59.30#ibcon#about to write, iclass 40, count 2 2006.169.07:45:59.30#ibcon#wrote, iclass 40, count 2 2006.169.07:45:59.30#ibcon#about to read 3, iclass 40, count 2 2006.169.07:45:59.32#ibcon#read 3, iclass 40, count 2 2006.169.07:45:59.32#ibcon#about to read 4, iclass 40, count 2 2006.169.07:45:59.32#ibcon#read 4, iclass 40, count 2 2006.169.07:45:59.32#ibcon#about to read 5, iclass 40, count 2 2006.169.07:45:59.32#ibcon#read 5, iclass 40, count 2 2006.169.07:45:59.32#ibcon#about to read 6, iclass 40, count 2 2006.169.07:45:59.32#ibcon#read 6, iclass 40, count 2 2006.169.07:45:59.32#ibcon#end of sib2, iclass 40, count 2 2006.169.07:45:59.32#ibcon#*mode == 0, iclass 40, count 2 2006.169.07:45:59.32#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.169.07:45:59.32#ibcon#[27=AT06-04\r\n] 2006.169.07:45:59.32#ibcon#*before write, iclass 40, count 2 2006.169.07:45:59.32#ibcon#enter sib2, iclass 40, count 2 2006.169.07:45:59.32#ibcon#flushed, iclass 40, count 2 2006.169.07:45:59.32#ibcon#about to write, iclass 40, count 2 2006.169.07:45:59.32#ibcon#wrote, iclass 40, count 2 2006.169.07:45:59.32#ibcon#about to read 3, iclass 40, count 2 2006.169.07:45:59.35#ibcon#read 3, iclass 40, count 2 2006.169.07:45:59.35#ibcon#about to read 4, iclass 40, count 2 2006.169.07:45:59.35#ibcon#read 4, iclass 40, count 2 2006.169.07:45:59.35#ibcon#about to read 5, iclass 40, count 2 2006.169.07:45:59.35#ibcon#read 5, iclass 40, count 2 2006.169.07:45:59.35#ibcon#about to read 6, iclass 40, count 2 2006.169.07:45:59.35#ibcon#read 6, iclass 40, count 2 2006.169.07:45:59.35#ibcon#end of sib2, iclass 40, count 2 2006.169.07:45:59.35#ibcon#*after write, iclass 40, count 2 2006.169.07:45:59.35#ibcon#*before return 0, iclass 40, count 2 2006.169.07:45:59.35#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.169.07:45:59.35#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.169.07:45:59.35#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.169.07:45:59.35#ibcon#ireg 7 cls_cnt 0 2006.169.07:45:59.35#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.169.07:45:59.47#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.169.07:45:59.47#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.169.07:45:59.47#ibcon#enter wrdev, iclass 40, count 0 2006.169.07:45:59.47#ibcon#first serial, iclass 40, count 0 2006.169.07:45:59.47#ibcon#enter sib2, iclass 40, count 0 2006.169.07:45:59.47#ibcon#flushed, iclass 40, count 0 2006.169.07:45:59.47#ibcon#about to write, iclass 40, count 0 2006.169.07:45:59.47#ibcon#wrote, iclass 40, count 0 2006.169.07:45:59.47#ibcon#about to read 3, iclass 40, count 0 2006.169.07:45:59.49#ibcon#read 3, iclass 40, count 0 2006.169.07:45:59.49#ibcon#about to read 4, iclass 40, count 0 2006.169.07:45:59.49#ibcon#read 4, iclass 40, count 0 2006.169.07:45:59.49#ibcon#about to read 5, iclass 40, count 0 2006.169.07:45:59.49#ibcon#read 5, iclass 40, count 0 2006.169.07:45:59.49#ibcon#about to read 6, iclass 40, count 0 2006.169.07:45:59.49#ibcon#read 6, iclass 40, count 0 2006.169.07:45:59.49#ibcon#end of sib2, iclass 40, count 0 2006.169.07:45:59.49#ibcon#*mode == 0, iclass 40, count 0 2006.169.07:45:59.49#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.169.07:45:59.49#ibcon#[27=USB\r\n] 2006.169.07:45:59.49#ibcon#*before write, iclass 40, count 0 2006.169.07:45:59.49#ibcon#enter sib2, iclass 40, count 0 2006.169.07:45:59.49#ibcon#flushed, iclass 40, count 0 2006.169.07:45:59.49#ibcon#about to write, iclass 40, count 0 2006.169.07:45:59.49#ibcon#wrote, iclass 40, count 0 2006.169.07:45:59.49#ibcon#about to read 3, iclass 40, count 0 2006.169.07:45:59.52#ibcon#read 3, iclass 40, count 0 2006.169.07:45:59.52#ibcon#about to read 4, iclass 40, count 0 2006.169.07:45:59.52#ibcon#read 4, iclass 40, count 0 2006.169.07:45:59.52#ibcon#about to read 5, iclass 40, count 0 2006.169.07:45:59.52#ibcon#read 5, iclass 40, count 0 2006.169.07:45:59.52#ibcon#about to read 6, iclass 40, count 0 2006.169.07:45:59.52#ibcon#read 6, iclass 40, count 0 2006.169.07:45:59.52#ibcon#end of sib2, iclass 40, count 0 2006.169.07:45:59.52#ibcon#*after write, iclass 40, count 0 2006.169.07:45:59.52#ibcon#*before return 0, iclass 40, count 0 2006.169.07:45:59.52#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.169.07:45:59.52#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.169.07:45:59.52#ibcon#about to clear, iclass 40 cls_cnt 0 2006.169.07:45:59.52#ibcon#cleared, iclass 40 cls_cnt 0 2006.169.07:45:59.52$vc4f8/vabw=wide 2006.169.07:45:59.52#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.169.07:45:59.52#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.169.07:45:59.52#ibcon#ireg 8 cls_cnt 0 2006.169.07:45:59.52#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.169.07:45:59.52#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.169.07:45:59.52#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.169.07:45:59.52#ibcon#enter wrdev, iclass 4, count 0 2006.169.07:45:59.52#ibcon#first serial, iclass 4, count 0 2006.169.07:45:59.52#ibcon#enter sib2, iclass 4, count 0 2006.169.07:45:59.52#ibcon#flushed, iclass 4, count 0 2006.169.07:45:59.52#ibcon#about to write, iclass 4, count 0 2006.169.07:45:59.52#ibcon#wrote, iclass 4, count 0 2006.169.07:45:59.52#ibcon#about to read 3, iclass 4, count 0 2006.169.07:45:59.54#ibcon#read 3, iclass 4, count 0 2006.169.07:45:59.54#ibcon#about to read 4, iclass 4, count 0 2006.169.07:45:59.54#ibcon#read 4, iclass 4, count 0 2006.169.07:45:59.54#ibcon#about to read 5, iclass 4, count 0 2006.169.07:45:59.54#ibcon#read 5, iclass 4, count 0 2006.169.07:45:59.54#ibcon#about to read 6, iclass 4, count 0 2006.169.07:45:59.54#ibcon#read 6, iclass 4, count 0 2006.169.07:45:59.54#ibcon#end of sib2, iclass 4, count 0 2006.169.07:45:59.54#ibcon#*mode == 0, iclass 4, count 0 2006.169.07:45:59.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.169.07:45:59.54#ibcon#[25=BW32\r\n] 2006.169.07:45:59.54#ibcon#*before write, iclass 4, count 0 2006.169.07:45:59.54#ibcon#enter sib2, iclass 4, count 0 2006.169.07:45:59.54#ibcon#flushed, iclass 4, count 0 2006.169.07:45:59.54#ibcon#about to write, iclass 4, count 0 2006.169.07:45:59.54#ibcon#wrote, iclass 4, count 0 2006.169.07:45:59.54#ibcon#about to read 3, iclass 4, count 0 2006.169.07:45:59.57#ibcon#read 3, iclass 4, count 0 2006.169.07:45:59.57#ibcon#about to read 4, iclass 4, count 0 2006.169.07:45:59.57#ibcon#read 4, iclass 4, count 0 2006.169.07:45:59.57#ibcon#about to read 5, iclass 4, count 0 2006.169.07:45:59.57#ibcon#read 5, iclass 4, count 0 2006.169.07:45:59.57#ibcon#about to read 6, iclass 4, count 0 2006.169.07:45:59.57#ibcon#read 6, iclass 4, count 0 2006.169.07:45:59.57#ibcon#end of sib2, iclass 4, count 0 2006.169.07:45:59.57#ibcon#*after write, iclass 4, count 0 2006.169.07:45:59.57#ibcon#*before return 0, iclass 4, count 0 2006.169.07:45:59.57#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.169.07:45:59.57#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.169.07:45:59.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.169.07:45:59.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.169.07:45:59.57$vc4f8/vbbw=wide 2006.169.07:45:59.57#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.169.07:45:59.57#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.169.07:45:59.57#ibcon#ireg 8 cls_cnt 0 2006.169.07:45:59.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:45:59.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:45:59.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:45:59.64#ibcon#enter wrdev, iclass 6, count 0 2006.169.07:45:59.64#ibcon#first serial, iclass 6, count 0 2006.169.07:45:59.64#ibcon#enter sib2, iclass 6, count 0 2006.169.07:45:59.64#ibcon#flushed, iclass 6, count 0 2006.169.07:45:59.64#ibcon#about to write, iclass 6, count 0 2006.169.07:45:59.64#ibcon#wrote, iclass 6, count 0 2006.169.07:45:59.64#ibcon#about to read 3, iclass 6, count 0 2006.169.07:45:59.66#ibcon#read 3, iclass 6, count 0 2006.169.07:45:59.66#ibcon#about to read 4, iclass 6, count 0 2006.169.07:45:59.66#ibcon#read 4, iclass 6, count 0 2006.169.07:45:59.66#ibcon#about to read 5, iclass 6, count 0 2006.169.07:45:59.66#ibcon#read 5, iclass 6, count 0 2006.169.07:45:59.66#ibcon#about to read 6, iclass 6, count 0 2006.169.07:45:59.66#ibcon#read 6, iclass 6, count 0 2006.169.07:45:59.66#ibcon#end of sib2, iclass 6, count 0 2006.169.07:45:59.66#ibcon#*mode == 0, iclass 6, count 0 2006.169.07:45:59.66#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.169.07:45:59.66#ibcon#[27=BW32\r\n] 2006.169.07:45:59.66#ibcon#*before write, iclass 6, count 0 2006.169.07:45:59.66#ibcon#enter sib2, iclass 6, count 0 2006.169.07:45:59.66#ibcon#flushed, iclass 6, count 0 2006.169.07:45:59.66#ibcon#about to write, iclass 6, count 0 2006.169.07:45:59.66#ibcon#wrote, iclass 6, count 0 2006.169.07:45:59.66#ibcon#about to read 3, iclass 6, count 0 2006.169.07:45:59.69#ibcon#read 3, iclass 6, count 0 2006.169.07:45:59.69#ibcon#about to read 4, iclass 6, count 0 2006.169.07:45:59.69#ibcon#read 4, iclass 6, count 0 2006.169.07:45:59.69#ibcon#about to read 5, iclass 6, count 0 2006.169.07:45:59.69#ibcon#read 5, iclass 6, count 0 2006.169.07:45:59.69#ibcon#about to read 6, iclass 6, count 0 2006.169.07:45:59.69#ibcon#read 6, iclass 6, count 0 2006.169.07:45:59.69#ibcon#end of sib2, iclass 6, count 0 2006.169.07:45:59.69#ibcon#*after write, iclass 6, count 0 2006.169.07:45:59.69#ibcon#*before return 0, iclass 6, count 0 2006.169.07:45:59.69#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:45:59.69#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:45:59.69#ibcon#about to clear, iclass 6 cls_cnt 0 2006.169.07:45:59.69#ibcon#cleared, iclass 6 cls_cnt 0 2006.169.07:45:59.69$4f8m12a/ifd4f 2006.169.07:45:59.69$ifd4f/lo= 2006.169.07:45:59.69$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.07:45:59.69$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.07:45:59.69$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.07:45:59.69$ifd4f/patch= 2006.169.07:45:59.69$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.07:45:59.69$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.07:45:59.69$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.07:45:59.69$4f8m12a/"form=m,16.000,1:2 2006.169.07:45:59.69$4f8m12a/"tpicd 2006.169.07:45:59.70$4f8m12a/echo=off 2006.169.07:45:59.70$4f8m12a/xlog=off 2006.169.07:45:59.70:!2006.169.07:46:50 2006.169.07:46:27.13#trakl#Source acquired 2006.169.07:46:28.13#flagr#flagr/antenna,acquired 2006.169.07:46:50.01:preob 2006.169.07:46:51.13/onsource/TRACKING 2006.169.07:46:51.13:!2006.169.07:47:00 2006.169.07:47:00.00:data_valid=on 2006.169.07:47:00.00:midob 2006.169.07:47:00.13/onsource/TRACKING 2006.169.07:47:00.13/wx/18.12,1003.8,100 2006.169.07:47:00.21/cable/+6.5282E-03 2006.169.07:47:01.30/va/01,08,usb,yes,49,52 2006.169.07:47:01.30/va/02,07,usb,yes,50,52 2006.169.07:47:01.30/va/03,06,usb,yes,53,53 2006.169.07:47:01.30/va/04,07,usb,yes,51,55 2006.169.07:47:01.30/va/05,07,usb,yes,56,59 2006.169.07:47:01.30/va/06,06,usb,yes,55,55 2006.169.07:47:01.30/va/07,06,usb,yes,56,55 2006.169.07:47:01.30/va/08,07,usb,yes,53,52 2006.169.07:47:01.53/valo/01,532.99,yes,locked 2006.169.07:47:01.53/valo/02,572.99,yes,locked 2006.169.07:47:01.53/valo/03,672.99,yes,locked 2006.169.07:47:01.53/valo/04,832.99,yes,locked 2006.169.07:47:01.53/valo/05,652.99,yes,locked 2006.169.07:47:01.53/valo/06,772.99,yes,locked 2006.169.07:47:01.53/valo/07,832.99,yes,locked 2006.169.07:47:01.53/valo/08,852.99,yes,locked 2006.169.07:47:02.62/vb/01,04,usb,yes,31,29 2006.169.07:47:02.62/vb/02,04,usb,yes,32,34 2006.169.07:47:02.62/vb/03,04,usb,yes,29,32 2006.169.07:47:02.62/vb/04,04,usb,yes,30,30 2006.169.07:47:02.62/vb/05,04,usb,yes,29,32 2006.169.07:47:02.62/vb/06,04,usb,yes,30,32 2006.169.07:47:02.62/vb/07,04,usb,yes,31,31 2006.169.07:47:02.62/vb/08,04,usb,yes,29,32 2006.169.07:47:02.85/vblo/01,632.99,yes,locked 2006.169.07:47:02.85/vblo/02,640.99,yes,locked 2006.169.07:47:02.85/vblo/03,656.99,yes,locked 2006.169.07:47:02.85/vblo/04,712.99,yes,locked 2006.169.07:47:02.85/vblo/05,744.99,yes,locked 2006.169.07:47:02.85/vblo/06,752.99,yes,locked 2006.169.07:47:02.85/vblo/07,734.99,yes,locked 2006.169.07:47:02.85/vblo/08,744.99,yes,locked 2006.169.07:47:03.00/vabw/8 2006.169.07:47:03.15/vbbw/8 2006.169.07:47:03.24/xfe/off,on,14.7 2006.169.07:47:03.63/ifatt/23,28,28,28 2006.169.07:47:04.07/fmout-gps/S +4.17E-07 2006.169.07:47:04.15:!2006.169.07:49:10 2006.169.07:49:10.01:data_valid=off 2006.169.07:49:10.02:postob 2006.169.07:49:10.20/cable/+6.5298E-03 2006.169.07:49:10.21/wx/18.12,1003.8,100 2006.169.07:49:11.07/fmout-gps/S +4.17E-07 2006.169.07:49:11.08:scan_name=169-0750,k06169,60 2006.169.07:49:11.08:source=1300+580,130252.47,574837.6,2000.0,cw 2006.169.07:49:12.14#flagr#flagr/antenna,new-source 2006.169.07:49:12.15:checkk5 2006.169.07:49:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.169.07:49:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.169.07:49:16.91/chk_autoobs//k5ts3?ERROR: timeout happened! 2006.169.07:49:17.30/chk_autoobs//k5ts4/ autoobs is running! 2006.169.07:49:17.66/chk_obsdata//k5ts1/T1690747??a.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.169.07:49:18.04/chk_obsdata//k5ts2/T1690747??b.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.169.07:49:25.09/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.07:49:25.47/chk_obsdata//k5ts4/T1690747??d.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.169.07:49:26.16/k5log//k5ts1_log_newline 2006.169.07:49:26.86/k5log//k5ts2_log_newline 2006.169.07:49:33.95/k5log//k5ts3?ERROR: timeout happened! 2006.169.07:49:34.65/k5log//k5ts4_log_newline 2006.169.07:49:34.81/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.07:49:34.81:4f8m12a=1 2006.169.07:49:34.81$4f8m12a/echo=on 2006.169.07:49:34.81$4f8m12a/pcalon 2006.169.07:49:34.81$pcalon/"no phase cal control is implemented here 2006.169.07:49:34.81$4f8m12a/"tpicd=stop 2006.169.07:49:34.81$4f8m12a/vc4f8 2006.169.07:49:34.81$vc4f8/valo=1,532.99 2006.169.07:49:34.81#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.169.07:49:34.82#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.169.07:49:34.82#ibcon#ireg 17 cls_cnt 0 2006.169.07:49:34.82#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:49:34.82#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:49:34.82#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:49:34.82#ibcon#enter wrdev, iclass 27, count 0 2006.169.07:49:34.82#ibcon#first serial, iclass 27, count 0 2006.169.07:49:34.82#ibcon#enter sib2, iclass 27, count 0 2006.169.07:49:34.82#ibcon#flushed, iclass 27, count 0 2006.169.07:49:34.82#ibcon#about to write, iclass 27, count 0 2006.169.07:49:34.82#ibcon#wrote, iclass 27, count 0 2006.169.07:49:34.82#ibcon#about to read 3, iclass 27, count 0 2006.169.07:49:34.83#ibcon#read 3, iclass 27, count 0 2006.169.07:49:34.83#ibcon#about to read 4, iclass 27, count 0 2006.169.07:49:34.83#ibcon#read 4, iclass 27, count 0 2006.169.07:49:34.83#ibcon#about to read 5, iclass 27, count 0 2006.169.07:49:34.83#ibcon#read 5, iclass 27, count 0 2006.169.07:49:34.83#ibcon#about to read 6, iclass 27, count 0 2006.169.07:49:34.83#ibcon#read 6, iclass 27, count 0 2006.169.07:49:34.83#ibcon#end of sib2, iclass 27, count 0 2006.169.07:49:34.83#ibcon#*mode == 0, iclass 27, count 0 2006.169.07:49:34.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.169.07:49:34.83#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.07:49:34.83#ibcon#*before write, iclass 27, count 0 2006.169.07:49:34.83#ibcon#enter sib2, iclass 27, count 0 2006.169.07:49:34.83#ibcon#flushed, iclass 27, count 0 2006.169.07:49:34.83#ibcon#about to write, iclass 27, count 0 2006.169.07:49:34.83#ibcon#wrote, iclass 27, count 0 2006.169.07:49:34.83#ibcon#about to read 3, iclass 27, count 0 2006.169.07:49:34.89#ibcon#read 3, iclass 27, count 0 2006.169.07:49:34.89#ibcon#about to read 4, iclass 27, count 0 2006.169.07:49:34.89#ibcon#read 4, iclass 27, count 0 2006.169.07:49:34.89#ibcon#about to read 5, iclass 27, count 0 2006.169.07:49:34.89#ibcon#read 5, iclass 27, count 0 2006.169.07:49:34.89#ibcon#about to read 6, iclass 27, count 0 2006.169.07:49:34.89#ibcon#read 6, iclass 27, count 0 2006.169.07:49:34.89#ibcon#end of sib2, iclass 27, count 0 2006.169.07:49:34.89#ibcon#*after write, iclass 27, count 0 2006.169.07:49:34.89#ibcon#*before return 0, iclass 27, count 0 2006.169.07:49:34.89#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:49:34.89#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:49:34.89#ibcon#about to clear, iclass 27 cls_cnt 0 2006.169.07:49:34.89#ibcon#cleared, iclass 27 cls_cnt 0 2006.169.07:49:34.89$vc4f8/va=1,8 2006.169.07:49:34.89#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.169.07:49:34.89#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.169.07:49:34.89#ibcon#ireg 11 cls_cnt 2 2006.169.07:49:34.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.169.07:49:34.89#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.169.07:49:34.89#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.169.07:49:34.89#ibcon#enter wrdev, iclass 29, count 2 2006.169.07:49:34.89#ibcon#first serial, iclass 29, count 2 2006.169.07:49:34.89#ibcon#enter sib2, iclass 29, count 2 2006.169.07:49:34.89#ibcon#flushed, iclass 29, count 2 2006.169.07:49:34.89#ibcon#about to write, iclass 29, count 2 2006.169.07:49:34.89#ibcon#wrote, iclass 29, count 2 2006.169.07:49:34.89#ibcon#about to read 3, iclass 29, count 2 2006.169.07:49:34.90#ibcon#read 3, iclass 29, count 2 2006.169.07:49:34.90#ibcon#about to read 4, iclass 29, count 2 2006.169.07:49:34.90#ibcon#read 4, iclass 29, count 2 2006.169.07:49:34.90#ibcon#about to read 5, iclass 29, count 2 2006.169.07:49:34.90#ibcon#read 5, iclass 29, count 2 2006.169.07:49:34.90#ibcon#about to read 6, iclass 29, count 2 2006.169.07:49:34.90#ibcon#read 6, iclass 29, count 2 2006.169.07:49:34.90#ibcon#end of sib2, iclass 29, count 2 2006.169.07:49:34.90#ibcon#*mode == 0, iclass 29, count 2 2006.169.07:49:34.90#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.169.07:49:34.90#ibcon#[25=AT01-08\r\n] 2006.169.07:49:34.90#ibcon#*before write, iclass 29, count 2 2006.169.07:49:34.90#ibcon#enter sib2, iclass 29, count 2 2006.169.07:49:34.90#ibcon#flushed, iclass 29, count 2 2006.169.07:49:34.90#ibcon#about to write, iclass 29, count 2 2006.169.07:49:34.90#ibcon#wrote, iclass 29, count 2 2006.169.07:49:34.90#ibcon#about to read 3, iclass 29, count 2 2006.169.07:49:34.93#ibcon#read 3, iclass 29, count 2 2006.169.07:49:34.93#ibcon#about to read 4, iclass 29, count 2 2006.169.07:49:34.93#ibcon#read 4, iclass 29, count 2 2006.169.07:49:34.93#ibcon#about to read 5, iclass 29, count 2 2006.169.07:49:34.93#ibcon#read 5, iclass 29, count 2 2006.169.07:49:34.93#ibcon#about to read 6, iclass 29, count 2 2006.169.07:49:34.93#ibcon#read 6, iclass 29, count 2 2006.169.07:49:34.93#ibcon#end of sib2, iclass 29, count 2 2006.169.07:49:34.93#ibcon#*after write, iclass 29, count 2 2006.169.07:49:34.93#ibcon#*before return 0, iclass 29, count 2 2006.169.07:49:34.93#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.169.07:49:34.93#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.169.07:49:34.93#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.169.07:49:34.93#ibcon#ireg 7 cls_cnt 0 2006.169.07:49:34.93#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.169.07:49:35.05#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.169.07:49:35.05#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.169.07:49:35.05#ibcon#enter wrdev, iclass 29, count 0 2006.169.07:49:35.05#ibcon#first serial, iclass 29, count 0 2006.169.07:49:35.05#ibcon#enter sib2, iclass 29, count 0 2006.169.07:49:35.05#ibcon#flushed, iclass 29, count 0 2006.169.07:49:35.05#ibcon#about to write, iclass 29, count 0 2006.169.07:49:35.05#ibcon#wrote, iclass 29, count 0 2006.169.07:49:35.05#ibcon#about to read 3, iclass 29, count 0 2006.169.07:49:35.09#ibcon#read 3, iclass 29, count 0 2006.169.07:49:35.09#ibcon#about to read 4, iclass 29, count 0 2006.169.07:49:35.09#ibcon#read 4, iclass 29, count 0 2006.169.07:49:35.09#ibcon#about to read 5, iclass 29, count 0 2006.169.07:49:35.09#ibcon#read 5, iclass 29, count 0 2006.169.07:49:35.09#ibcon#about to read 6, iclass 29, count 0 2006.169.07:49:35.09#ibcon#read 6, iclass 29, count 0 2006.169.07:49:35.09#ibcon#end of sib2, iclass 29, count 0 2006.169.07:49:35.09#ibcon#*mode == 0, iclass 29, count 0 2006.169.07:49:35.09#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.169.07:49:35.09#ibcon#[25=USB\r\n] 2006.169.07:49:35.09#ibcon#*before write, iclass 29, count 0 2006.169.07:49:35.09#ibcon#enter sib2, iclass 29, count 0 2006.169.07:49:35.09#ibcon#flushed, iclass 29, count 0 2006.169.07:49:35.09#ibcon#about to write, iclass 29, count 0 2006.169.07:49:35.09#ibcon#wrote, iclass 29, count 0 2006.169.07:49:35.09#ibcon#about to read 3, iclass 29, count 0 2006.169.07:49:35.12#ibcon#read 3, iclass 29, count 0 2006.169.07:49:35.12#ibcon#about to read 4, iclass 29, count 0 2006.169.07:49:35.12#ibcon#read 4, iclass 29, count 0 2006.169.07:49:35.12#ibcon#about to read 5, iclass 29, count 0 2006.169.07:49:35.12#ibcon#read 5, iclass 29, count 0 2006.169.07:49:35.12#ibcon#about to read 6, iclass 29, count 0 2006.169.07:49:35.12#ibcon#read 6, iclass 29, count 0 2006.169.07:49:35.12#ibcon#end of sib2, iclass 29, count 0 2006.169.07:49:35.12#ibcon#*after write, iclass 29, count 0 2006.169.07:49:35.12#ibcon#*before return 0, iclass 29, count 0 2006.169.07:49:35.12#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.169.07:49:35.12#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.169.07:49:35.12#ibcon#about to clear, iclass 29 cls_cnt 0 2006.169.07:49:35.12#ibcon#cleared, iclass 29 cls_cnt 0 2006.169.07:49:35.12$vc4f8/valo=2,572.99 2006.169.07:49:35.12#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.169.07:49:35.12#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.169.07:49:35.12#ibcon#ireg 17 cls_cnt 0 2006.169.07:49:35.12#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.169.07:49:35.12#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.169.07:49:35.12#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.169.07:49:35.12#ibcon#enter wrdev, iclass 31, count 0 2006.169.07:49:35.12#ibcon#first serial, iclass 31, count 0 2006.169.07:49:35.12#ibcon#enter sib2, iclass 31, count 0 2006.169.07:49:35.12#ibcon#flushed, iclass 31, count 0 2006.169.07:49:35.12#ibcon#about to write, iclass 31, count 0 2006.169.07:49:35.12#ibcon#wrote, iclass 31, count 0 2006.169.07:49:35.12#ibcon#about to read 3, iclass 31, count 0 2006.169.07:49:35.15#ibcon#read 3, iclass 31, count 0 2006.169.07:49:35.15#ibcon#about to read 4, iclass 31, count 0 2006.169.07:49:35.15#ibcon#read 4, iclass 31, count 0 2006.169.07:49:35.15#ibcon#about to read 5, iclass 31, count 0 2006.169.07:49:35.15#ibcon#read 5, iclass 31, count 0 2006.169.07:49:35.15#ibcon#about to read 6, iclass 31, count 0 2006.169.07:49:35.15#ibcon#read 6, iclass 31, count 0 2006.169.07:49:35.15#ibcon#end of sib2, iclass 31, count 0 2006.169.07:49:35.15#ibcon#*mode == 0, iclass 31, count 0 2006.169.07:49:35.15#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.169.07:49:35.15#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.07:49:35.15#ibcon#*before write, iclass 31, count 0 2006.169.07:49:35.15#ibcon#enter sib2, iclass 31, count 0 2006.169.07:49:35.15#ibcon#flushed, iclass 31, count 0 2006.169.07:49:35.15#ibcon#about to write, iclass 31, count 0 2006.169.07:49:35.15#ibcon#wrote, iclass 31, count 0 2006.169.07:49:35.15#ibcon#about to read 3, iclass 31, count 0 2006.169.07:49:35.18#ibcon#read 3, iclass 31, count 0 2006.169.07:49:35.18#ibcon#about to read 4, iclass 31, count 0 2006.169.07:49:35.18#ibcon#read 4, iclass 31, count 0 2006.169.07:49:35.18#ibcon#about to read 5, iclass 31, count 0 2006.169.07:49:35.18#ibcon#read 5, iclass 31, count 0 2006.169.07:49:35.18#ibcon#about to read 6, iclass 31, count 0 2006.169.07:49:35.18#ibcon#read 6, iclass 31, count 0 2006.169.07:49:35.18#ibcon#end of sib2, iclass 31, count 0 2006.169.07:49:35.18#ibcon#*after write, iclass 31, count 0 2006.169.07:49:35.18#ibcon#*before return 0, iclass 31, count 0 2006.169.07:49:35.18#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.169.07:49:35.18#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.169.07:49:35.18#ibcon#about to clear, iclass 31 cls_cnt 0 2006.169.07:49:35.18#ibcon#cleared, iclass 31 cls_cnt 0 2006.169.07:49:35.18$vc4f8/va=2,7 2006.169.07:49:35.18#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.169.07:49:35.18#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.169.07:49:35.18#ibcon#ireg 11 cls_cnt 2 2006.169.07:49:35.18#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.169.07:49:35.24#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.169.07:49:35.24#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.169.07:49:35.24#ibcon#enter wrdev, iclass 33, count 2 2006.169.07:49:35.24#ibcon#first serial, iclass 33, count 2 2006.169.07:49:35.24#ibcon#enter sib2, iclass 33, count 2 2006.169.07:49:35.24#ibcon#flushed, iclass 33, count 2 2006.169.07:49:35.24#ibcon#about to write, iclass 33, count 2 2006.169.07:49:35.24#ibcon#wrote, iclass 33, count 2 2006.169.07:49:35.24#ibcon#about to read 3, iclass 33, count 2 2006.169.07:49:35.27#ibcon#read 3, iclass 33, count 2 2006.169.07:49:35.27#ibcon#about to read 4, iclass 33, count 2 2006.169.07:49:35.27#ibcon#read 4, iclass 33, count 2 2006.169.07:49:35.27#ibcon#about to read 5, iclass 33, count 2 2006.169.07:49:35.27#ibcon#read 5, iclass 33, count 2 2006.169.07:49:35.27#ibcon#about to read 6, iclass 33, count 2 2006.169.07:49:35.27#ibcon#read 6, iclass 33, count 2 2006.169.07:49:35.27#ibcon#end of sib2, iclass 33, count 2 2006.169.07:49:35.27#ibcon#*mode == 0, iclass 33, count 2 2006.169.07:49:35.27#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.169.07:49:35.27#ibcon#[25=AT02-07\r\n] 2006.169.07:49:35.27#ibcon#*before write, iclass 33, count 2 2006.169.07:49:35.27#ibcon#enter sib2, iclass 33, count 2 2006.169.07:49:35.27#ibcon#flushed, iclass 33, count 2 2006.169.07:49:35.27#ibcon#about to write, iclass 33, count 2 2006.169.07:49:35.27#ibcon#wrote, iclass 33, count 2 2006.169.07:49:35.27#ibcon#about to read 3, iclass 33, count 2 2006.169.07:49:35.30#ibcon#read 3, iclass 33, count 2 2006.169.07:49:35.30#ibcon#about to read 4, iclass 33, count 2 2006.169.07:49:35.30#ibcon#read 4, iclass 33, count 2 2006.169.07:49:35.30#ibcon#about to read 5, iclass 33, count 2 2006.169.07:49:35.30#ibcon#read 5, iclass 33, count 2 2006.169.07:49:35.30#ibcon#about to read 6, iclass 33, count 2 2006.169.07:49:35.30#ibcon#read 6, iclass 33, count 2 2006.169.07:49:35.30#ibcon#end of sib2, iclass 33, count 2 2006.169.07:49:35.30#ibcon#*after write, iclass 33, count 2 2006.169.07:49:35.30#ibcon#*before return 0, iclass 33, count 2 2006.169.07:49:35.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.169.07:49:35.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.169.07:49:35.30#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.169.07:49:35.30#ibcon#ireg 7 cls_cnt 0 2006.169.07:49:35.30#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.169.07:49:35.42#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.169.07:49:35.42#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.169.07:49:35.42#ibcon#enter wrdev, iclass 33, count 0 2006.169.07:49:35.42#ibcon#first serial, iclass 33, count 0 2006.169.07:49:35.42#ibcon#enter sib2, iclass 33, count 0 2006.169.07:49:35.42#ibcon#flushed, iclass 33, count 0 2006.169.07:49:35.42#ibcon#about to write, iclass 33, count 0 2006.169.07:49:35.42#ibcon#wrote, iclass 33, count 0 2006.169.07:49:35.42#ibcon#about to read 3, iclass 33, count 0 2006.169.07:49:35.44#ibcon#read 3, iclass 33, count 0 2006.169.07:49:35.44#ibcon#about to read 4, iclass 33, count 0 2006.169.07:49:35.44#ibcon#read 4, iclass 33, count 0 2006.169.07:49:35.44#ibcon#about to read 5, iclass 33, count 0 2006.169.07:49:35.44#ibcon#read 5, iclass 33, count 0 2006.169.07:49:35.44#ibcon#about to read 6, iclass 33, count 0 2006.169.07:49:35.44#ibcon#read 6, iclass 33, count 0 2006.169.07:49:35.44#ibcon#end of sib2, iclass 33, count 0 2006.169.07:49:35.44#ibcon#*mode == 0, iclass 33, count 0 2006.169.07:49:35.44#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.169.07:49:35.44#ibcon#[25=USB\r\n] 2006.169.07:49:35.44#ibcon#*before write, iclass 33, count 0 2006.169.07:49:35.44#ibcon#enter sib2, iclass 33, count 0 2006.169.07:49:35.44#ibcon#flushed, iclass 33, count 0 2006.169.07:49:35.44#ibcon#about to write, iclass 33, count 0 2006.169.07:49:35.44#ibcon#wrote, iclass 33, count 0 2006.169.07:49:35.44#ibcon#about to read 3, iclass 33, count 0 2006.169.07:49:35.47#ibcon#read 3, iclass 33, count 0 2006.169.07:49:35.47#ibcon#about to read 4, iclass 33, count 0 2006.169.07:49:35.47#ibcon#read 4, iclass 33, count 0 2006.169.07:49:35.47#ibcon#about to read 5, iclass 33, count 0 2006.169.07:49:35.47#ibcon#read 5, iclass 33, count 0 2006.169.07:49:35.47#ibcon#about to read 6, iclass 33, count 0 2006.169.07:49:35.47#ibcon#read 6, iclass 33, count 0 2006.169.07:49:35.47#ibcon#end of sib2, iclass 33, count 0 2006.169.07:49:35.47#ibcon#*after write, iclass 33, count 0 2006.169.07:49:35.47#ibcon#*before return 0, iclass 33, count 0 2006.169.07:49:35.47#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.169.07:49:35.47#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.169.07:49:35.47#ibcon#about to clear, iclass 33 cls_cnt 0 2006.169.07:49:35.47#ibcon#cleared, iclass 33 cls_cnt 0 2006.169.07:49:35.47$vc4f8/valo=3,672.99 2006.169.07:49:35.47#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.169.07:49:35.47#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.169.07:49:35.47#ibcon#ireg 17 cls_cnt 0 2006.169.07:49:35.47#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.169.07:49:35.47#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.169.07:49:35.47#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.169.07:49:35.47#ibcon#enter wrdev, iclass 35, count 0 2006.169.07:49:35.47#ibcon#first serial, iclass 35, count 0 2006.169.07:49:35.47#ibcon#enter sib2, iclass 35, count 0 2006.169.07:49:35.47#ibcon#flushed, iclass 35, count 0 2006.169.07:49:35.47#ibcon#about to write, iclass 35, count 0 2006.169.07:49:35.47#ibcon#wrote, iclass 35, count 0 2006.169.07:49:35.47#ibcon#about to read 3, iclass 35, count 0 2006.169.07:49:35.49#ibcon#read 3, iclass 35, count 0 2006.169.07:49:35.49#ibcon#about to read 4, iclass 35, count 0 2006.169.07:49:35.49#ibcon#read 4, iclass 35, count 0 2006.169.07:49:35.49#ibcon#about to read 5, iclass 35, count 0 2006.169.07:49:35.49#ibcon#read 5, iclass 35, count 0 2006.169.07:49:35.49#ibcon#about to read 6, iclass 35, count 0 2006.169.07:49:35.49#ibcon#read 6, iclass 35, count 0 2006.169.07:49:35.49#ibcon#end of sib2, iclass 35, count 0 2006.169.07:49:35.49#ibcon#*mode == 0, iclass 35, count 0 2006.169.07:49:35.49#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.169.07:49:35.49#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.07:49:35.49#ibcon#*before write, iclass 35, count 0 2006.169.07:49:35.49#ibcon#enter sib2, iclass 35, count 0 2006.169.07:49:35.49#ibcon#flushed, iclass 35, count 0 2006.169.07:49:35.49#ibcon#about to write, iclass 35, count 0 2006.169.07:49:35.49#ibcon#wrote, iclass 35, count 0 2006.169.07:49:35.49#ibcon#about to read 3, iclass 35, count 0 2006.169.07:49:35.53#ibcon#read 3, iclass 35, count 0 2006.169.07:49:35.53#ibcon#about to read 4, iclass 35, count 0 2006.169.07:49:35.53#ibcon#read 4, iclass 35, count 0 2006.169.07:49:35.53#ibcon#about to read 5, iclass 35, count 0 2006.169.07:49:35.53#ibcon#read 5, iclass 35, count 0 2006.169.07:49:35.53#ibcon#about to read 6, iclass 35, count 0 2006.169.07:49:35.53#ibcon#read 6, iclass 35, count 0 2006.169.07:49:35.53#ibcon#end of sib2, iclass 35, count 0 2006.169.07:49:35.53#ibcon#*after write, iclass 35, count 0 2006.169.07:49:35.53#ibcon#*before return 0, iclass 35, count 0 2006.169.07:49:35.53#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.169.07:49:35.53#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.169.07:49:35.53#ibcon#about to clear, iclass 35 cls_cnt 0 2006.169.07:49:35.53#ibcon#cleared, iclass 35 cls_cnt 0 2006.169.07:49:35.53$vc4f8/va=3,6 2006.169.07:49:35.53#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.169.07:49:35.53#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.169.07:49:35.53#ibcon#ireg 11 cls_cnt 2 2006.169.07:49:35.53#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.169.07:49:35.59#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.169.07:49:35.59#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.169.07:49:35.59#ibcon#enter wrdev, iclass 37, count 2 2006.169.07:49:35.59#ibcon#first serial, iclass 37, count 2 2006.169.07:49:35.59#ibcon#enter sib2, iclass 37, count 2 2006.169.07:49:35.59#ibcon#flushed, iclass 37, count 2 2006.169.07:49:35.59#ibcon#about to write, iclass 37, count 2 2006.169.07:49:35.59#ibcon#wrote, iclass 37, count 2 2006.169.07:49:35.59#ibcon#about to read 3, iclass 37, count 2 2006.169.07:49:35.61#ibcon#read 3, iclass 37, count 2 2006.169.07:49:35.61#ibcon#about to read 4, iclass 37, count 2 2006.169.07:49:35.61#ibcon#read 4, iclass 37, count 2 2006.169.07:49:35.61#ibcon#about to read 5, iclass 37, count 2 2006.169.07:49:35.61#ibcon#read 5, iclass 37, count 2 2006.169.07:49:35.61#ibcon#about to read 6, iclass 37, count 2 2006.169.07:49:35.61#ibcon#read 6, iclass 37, count 2 2006.169.07:49:35.61#ibcon#end of sib2, iclass 37, count 2 2006.169.07:49:35.61#ibcon#*mode == 0, iclass 37, count 2 2006.169.07:49:35.61#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.169.07:49:35.61#ibcon#[25=AT03-06\r\n] 2006.169.07:49:35.61#ibcon#*before write, iclass 37, count 2 2006.169.07:49:35.61#ibcon#enter sib2, iclass 37, count 2 2006.169.07:49:35.61#ibcon#flushed, iclass 37, count 2 2006.169.07:49:35.61#ibcon#about to write, iclass 37, count 2 2006.169.07:49:35.61#ibcon#wrote, iclass 37, count 2 2006.169.07:49:35.61#ibcon#about to read 3, iclass 37, count 2 2006.169.07:49:35.64#ibcon#read 3, iclass 37, count 2 2006.169.07:49:35.64#ibcon#about to read 4, iclass 37, count 2 2006.169.07:49:35.64#ibcon#read 4, iclass 37, count 2 2006.169.07:49:35.64#ibcon#about to read 5, iclass 37, count 2 2006.169.07:49:35.64#ibcon#read 5, iclass 37, count 2 2006.169.07:49:35.64#ibcon#about to read 6, iclass 37, count 2 2006.169.07:49:35.64#ibcon#read 6, iclass 37, count 2 2006.169.07:49:35.64#ibcon#end of sib2, iclass 37, count 2 2006.169.07:49:35.64#ibcon#*after write, iclass 37, count 2 2006.169.07:49:35.64#ibcon#*before return 0, iclass 37, count 2 2006.169.07:49:35.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.169.07:49:35.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.169.07:49:35.64#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.169.07:49:35.64#ibcon#ireg 7 cls_cnt 0 2006.169.07:49:35.64#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.169.07:49:35.76#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.169.07:49:35.76#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.169.07:49:35.76#ibcon#enter wrdev, iclass 37, count 0 2006.169.07:49:35.76#ibcon#first serial, iclass 37, count 0 2006.169.07:49:35.76#ibcon#enter sib2, iclass 37, count 0 2006.169.07:49:35.76#ibcon#flushed, iclass 37, count 0 2006.169.07:49:35.76#ibcon#about to write, iclass 37, count 0 2006.169.07:49:35.76#ibcon#wrote, iclass 37, count 0 2006.169.07:49:35.76#ibcon#about to read 3, iclass 37, count 0 2006.169.07:49:35.78#ibcon#read 3, iclass 37, count 0 2006.169.07:49:35.78#ibcon#about to read 4, iclass 37, count 0 2006.169.07:49:35.78#ibcon#read 4, iclass 37, count 0 2006.169.07:49:35.78#ibcon#about to read 5, iclass 37, count 0 2006.169.07:49:35.78#ibcon#read 5, iclass 37, count 0 2006.169.07:49:35.78#ibcon#about to read 6, iclass 37, count 0 2006.169.07:49:35.78#ibcon#read 6, iclass 37, count 0 2006.169.07:49:35.78#ibcon#end of sib2, iclass 37, count 0 2006.169.07:49:35.78#ibcon#*mode == 0, iclass 37, count 0 2006.169.07:49:35.78#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.169.07:49:35.78#ibcon#[25=USB\r\n] 2006.169.07:49:35.78#ibcon#*before write, iclass 37, count 0 2006.169.07:49:35.78#ibcon#enter sib2, iclass 37, count 0 2006.169.07:49:35.78#ibcon#flushed, iclass 37, count 0 2006.169.07:49:35.78#ibcon#about to write, iclass 37, count 0 2006.169.07:49:35.78#ibcon#wrote, iclass 37, count 0 2006.169.07:49:35.78#ibcon#about to read 3, iclass 37, count 0 2006.169.07:49:35.81#ibcon#read 3, iclass 37, count 0 2006.169.07:49:35.81#ibcon#about to read 4, iclass 37, count 0 2006.169.07:49:35.81#ibcon#read 4, iclass 37, count 0 2006.169.07:49:35.81#ibcon#about to read 5, iclass 37, count 0 2006.169.07:49:35.81#ibcon#read 5, iclass 37, count 0 2006.169.07:49:35.81#ibcon#about to read 6, iclass 37, count 0 2006.169.07:49:35.81#ibcon#read 6, iclass 37, count 0 2006.169.07:49:35.81#ibcon#end of sib2, iclass 37, count 0 2006.169.07:49:35.81#ibcon#*after write, iclass 37, count 0 2006.169.07:49:35.81#ibcon#*before return 0, iclass 37, count 0 2006.169.07:49:35.81#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.169.07:49:35.81#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.169.07:49:35.81#ibcon#about to clear, iclass 37 cls_cnt 0 2006.169.07:49:35.81#ibcon#cleared, iclass 37 cls_cnt 0 2006.169.07:49:35.81$vc4f8/valo=4,832.99 2006.169.07:49:35.81#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.169.07:49:35.81#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.169.07:49:35.81#ibcon#ireg 17 cls_cnt 0 2006.169.07:49:35.81#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.169.07:49:35.81#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.169.07:49:35.81#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.169.07:49:35.81#ibcon#enter wrdev, iclass 39, count 0 2006.169.07:49:35.81#ibcon#first serial, iclass 39, count 0 2006.169.07:49:35.81#ibcon#enter sib2, iclass 39, count 0 2006.169.07:49:35.81#ibcon#flushed, iclass 39, count 0 2006.169.07:49:35.81#ibcon#about to write, iclass 39, count 0 2006.169.07:49:35.81#ibcon#wrote, iclass 39, count 0 2006.169.07:49:35.81#ibcon#about to read 3, iclass 39, count 0 2006.169.07:49:35.83#ibcon#read 3, iclass 39, count 0 2006.169.07:49:35.83#ibcon#about to read 4, iclass 39, count 0 2006.169.07:49:35.83#ibcon#read 4, iclass 39, count 0 2006.169.07:49:35.83#ibcon#about to read 5, iclass 39, count 0 2006.169.07:49:35.83#ibcon#read 5, iclass 39, count 0 2006.169.07:49:35.83#ibcon#about to read 6, iclass 39, count 0 2006.169.07:49:35.83#ibcon#read 6, iclass 39, count 0 2006.169.07:49:35.83#ibcon#end of sib2, iclass 39, count 0 2006.169.07:49:35.83#ibcon#*mode == 0, iclass 39, count 0 2006.169.07:49:35.83#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.169.07:49:35.83#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.07:49:35.83#ibcon#*before write, iclass 39, count 0 2006.169.07:49:35.83#ibcon#enter sib2, iclass 39, count 0 2006.169.07:49:35.83#ibcon#flushed, iclass 39, count 0 2006.169.07:49:35.83#ibcon#about to write, iclass 39, count 0 2006.169.07:49:35.83#ibcon#wrote, iclass 39, count 0 2006.169.07:49:35.83#ibcon#about to read 3, iclass 39, count 0 2006.169.07:49:35.87#ibcon#read 3, iclass 39, count 0 2006.169.07:49:35.87#ibcon#about to read 4, iclass 39, count 0 2006.169.07:49:35.87#ibcon#read 4, iclass 39, count 0 2006.169.07:49:35.87#ibcon#about to read 5, iclass 39, count 0 2006.169.07:49:35.87#ibcon#read 5, iclass 39, count 0 2006.169.07:49:35.87#ibcon#about to read 6, iclass 39, count 0 2006.169.07:49:35.87#ibcon#read 6, iclass 39, count 0 2006.169.07:49:35.87#ibcon#end of sib2, iclass 39, count 0 2006.169.07:49:35.87#ibcon#*after write, iclass 39, count 0 2006.169.07:49:35.87#ibcon#*before return 0, iclass 39, count 0 2006.169.07:49:35.87#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.169.07:49:35.87#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.169.07:49:35.87#ibcon#about to clear, iclass 39 cls_cnt 0 2006.169.07:49:35.87#ibcon#cleared, iclass 39 cls_cnt 0 2006.169.07:49:35.87$vc4f8/va=4,7 2006.169.07:49:35.87#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.169.07:49:35.87#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.169.07:49:35.87#ibcon#ireg 11 cls_cnt 2 2006.169.07:49:35.87#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.169.07:49:35.93#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.169.07:49:35.93#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.169.07:49:35.93#ibcon#enter wrdev, iclass 3, count 2 2006.169.07:49:35.93#ibcon#first serial, iclass 3, count 2 2006.169.07:49:35.93#ibcon#enter sib2, iclass 3, count 2 2006.169.07:49:35.93#ibcon#flushed, iclass 3, count 2 2006.169.07:49:35.93#ibcon#about to write, iclass 3, count 2 2006.169.07:49:35.93#ibcon#wrote, iclass 3, count 2 2006.169.07:49:35.93#ibcon#about to read 3, iclass 3, count 2 2006.169.07:49:35.95#ibcon#read 3, iclass 3, count 2 2006.169.07:49:35.95#ibcon#about to read 4, iclass 3, count 2 2006.169.07:49:35.95#ibcon#read 4, iclass 3, count 2 2006.169.07:49:35.95#ibcon#about to read 5, iclass 3, count 2 2006.169.07:49:35.95#ibcon#read 5, iclass 3, count 2 2006.169.07:49:35.95#ibcon#about to read 6, iclass 3, count 2 2006.169.07:49:35.95#ibcon#read 6, iclass 3, count 2 2006.169.07:49:35.95#ibcon#end of sib2, iclass 3, count 2 2006.169.07:49:35.95#ibcon#*mode == 0, iclass 3, count 2 2006.169.07:49:35.95#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.169.07:49:35.95#ibcon#[25=AT04-07\r\n] 2006.169.07:49:35.95#ibcon#*before write, iclass 3, count 2 2006.169.07:49:35.95#ibcon#enter sib2, iclass 3, count 2 2006.169.07:49:35.95#ibcon#flushed, iclass 3, count 2 2006.169.07:49:35.95#ibcon#about to write, iclass 3, count 2 2006.169.07:49:35.95#ibcon#wrote, iclass 3, count 2 2006.169.07:49:35.95#ibcon#about to read 3, iclass 3, count 2 2006.169.07:49:35.98#ibcon#read 3, iclass 3, count 2 2006.169.07:49:35.98#ibcon#about to read 4, iclass 3, count 2 2006.169.07:49:35.98#ibcon#read 4, iclass 3, count 2 2006.169.07:49:35.98#ibcon#about to read 5, iclass 3, count 2 2006.169.07:49:35.98#ibcon#read 5, iclass 3, count 2 2006.169.07:49:35.98#ibcon#about to read 6, iclass 3, count 2 2006.169.07:49:35.98#ibcon#read 6, iclass 3, count 2 2006.169.07:49:35.98#ibcon#end of sib2, iclass 3, count 2 2006.169.07:49:35.98#ibcon#*after write, iclass 3, count 2 2006.169.07:49:35.98#ibcon#*before return 0, iclass 3, count 2 2006.169.07:49:35.98#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.169.07:49:35.98#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.169.07:49:35.98#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.169.07:49:35.98#ibcon#ireg 7 cls_cnt 0 2006.169.07:49:35.98#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.169.07:49:36.10#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.169.07:49:36.10#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.169.07:49:36.10#ibcon#enter wrdev, iclass 3, count 0 2006.169.07:49:36.10#ibcon#first serial, iclass 3, count 0 2006.169.07:49:36.10#ibcon#enter sib2, iclass 3, count 0 2006.169.07:49:36.10#ibcon#flushed, iclass 3, count 0 2006.169.07:49:36.10#ibcon#about to write, iclass 3, count 0 2006.169.07:49:36.10#ibcon#wrote, iclass 3, count 0 2006.169.07:49:36.10#ibcon#about to read 3, iclass 3, count 0 2006.169.07:49:36.12#ibcon#read 3, iclass 3, count 0 2006.169.07:49:36.12#ibcon#about to read 4, iclass 3, count 0 2006.169.07:49:36.12#ibcon#read 4, iclass 3, count 0 2006.169.07:49:36.12#ibcon#about to read 5, iclass 3, count 0 2006.169.07:49:36.12#ibcon#read 5, iclass 3, count 0 2006.169.07:49:36.12#ibcon#about to read 6, iclass 3, count 0 2006.169.07:49:36.12#ibcon#read 6, iclass 3, count 0 2006.169.07:49:36.12#ibcon#end of sib2, iclass 3, count 0 2006.169.07:49:36.12#ibcon#*mode == 0, iclass 3, count 0 2006.169.07:49:36.12#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.169.07:49:36.12#ibcon#[25=USB\r\n] 2006.169.07:49:36.12#ibcon#*before write, iclass 3, count 0 2006.169.07:49:36.12#ibcon#enter sib2, iclass 3, count 0 2006.169.07:49:36.12#ibcon#flushed, iclass 3, count 0 2006.169.07:49:36.12#ibcon#about to write, iclass 3, count 0 2006.169.07:49:36.12#ibcon#wrote, iclass 3, count 0 2006.169.07:49:36.12#ibcon#about to read 3, iclass 3, count 0 2006.169.07:49:36.15#ibcon#read 3, iclass 3, count 0 2006.169.07:49:36.15#ibcon#about to read 4, iclass 3, count 0 2006.169.07:49:36.15#ibcon#read 4, iclass 3, count 0 2006.169.07:49:36.15#ibcon#about to read 5, iclass 3, count 0 2006.169.07:49:36.15#ibcon#read 5, iclass 3, count 0 2006.169.07:49:36.15#ibcon#about to read 6, iclass 3, count 0 2006.169.07:49:36.15#ibcon#read 6, iclass 3, count 0 2006.169.07:49:36.15#ibcon#end of sib2, iclass 3, count 0 2006.169.07:49:36.15#ibcon#*after write, iclass 3, count 0 2006.169.07:49:36.15#ibcon#*before return 0, iclass 3, count 0 2006.169.07:49:36.15#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.169.07:49:36.15#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.169.07:49:36.15#ibcon#about to clear, iclass 3 cls_cnt 0 2006.169.07:49:36.15#ibcon#cleared, iclass 3 cls_cnt 0 2006.169.07:49:36.15$vc4f8/valo=5,652.99 2006.169.07:49:36.15#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.169.07:49:36.15#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.169.07:49:36.15#ibcon#ireg 17 cls_cnt 0 2006.169.07:49:36.15#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:49:36.15#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:49:36.15#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:49:36.15#ibcon#enter wrdev, iclass 5, count 0 2006.169.07:49:36.15#ibcon#first serial, iclass 5, count 0 2006.169.07:49:36.15#ibcon#enter sib2, iclass 5, count 0 2006.169.07:49:36.15#ibcon#flushed, iclass 5, count 0 2006.169.07:49:36.15#ibcon#about to write, iclass 5, count 0 2006.169.07:49:36.15#ibcon#wrote, iclass 5, count 0 2006.169.07:49:36.15#ibcon#about to read 3, iclass 5, count 0 2006.169.07:49:36.17#ibcon#read 3, iclass 5, count 0 2006.169.07:49:36.17#ibcon#about to read 4, iclass 5, count 0 2006.169.07:49:36.17#ibcon#read 4, iclass 5, count 0 2006.169.07:49:36.17#ibcon#about to read 5, iclass 5, count 0 2006.169.07:49:36.17#ibcon#read 5, iclass 5, count 0 2006.169.07:49:36.17#ibcon#about to read 6, iclass 5, count 0 2006.169.07:49:36.17#ibcon#read 6, iclass 5, count 0 2006.169.07:49:36.17#ibcon#end of sib2, iclass 5, count 0 2006.169.07:49:36.17#ibcon#*mode == 0, iclass 5, count 0 2006.169.07:49:36.17#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.169.07:49:36.17#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.07:49:36.17#ibcon#*before write, iclass 5, count 0 2006.169.07:49:36.17#ibcon#enter sib2, iclass 5, count 0 2006.169.07:49:36.17#ibcon#flushed, iclass 5, count 0 2006.169.07:49:36.17#ibcon#about to write, iclass 5, count 0 2006.169.07:49:36.17#ibcon#wrote, iclass 5, count 0 2006.169.07:49:36.17#ibcon#about to read 3, iclass 5, count 0 2006.169.07:49:36.21#ibcon#read 3, iclass 5, count 0 2006.169.07:49:36.21#ibcon#about to read 4, iclass 5, count 0 2006.169.07:49:36.21#ibcon#read 4, iclass 5, count 0 2006.169.07:49:36.21#ibcon#about to read 5, iclass 5, count 0 2006.169.07:49:36.21#ibcon#read 5, iclass 5, count 0 2006.169.07:49:36.21#ibcon#about to read 6, iclass 5, count 0 2006.169.07:49:36.21#ibcon#read 6, iclass 5, count 0 2006.169.07:49:36.21#ibcon#end of sib2, iclass 5, count 0 2006.169.07:49:36.21#ibcon#*after write, iclass 5, count 0 2006.169.07:49:36.21#ibcon#*before return 0, iclass 5, count 0 2006.169.07:49:36.21#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:49:36.21#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:49:36.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.169.07:49:36.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.169.07:49:36.21$vc4f8/va=5,7 2006.169.07:49:36.21#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.169.07:49:36.21#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.169.07:49:36.21#ibcon#ireg 11 cls_cnt 2 2006.169.07:49:36.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:49:36.27#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:49:36.27#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:49:36.27#ibcon#enter wrdev, iclass 7, count 2 2006.169.07:49:36.27#ibcon#first serial, iclass 7, count 2 2006.169.07:49:36.27#ibcon#enter sib2, iclass 7, count 2 2006.169.07:49:36.27#ibcon#flushed, iclass 7, count 2 2006.169.07:49:36.27#ibcon#about to write, iclass 7, count 2 2006.169.07:49:36.27#ibcon#wrote, iclass 7, count 2 2006.169.07:49:36.27#ibcon#about to read 3, iclass 7, count 2 2006.169.07:49:36.29#ibcon#read 3, iclass 7, count 2 2006.169.07:49:36.29#ibcon#about to read 4, iclass 7, count 2 2006.169.07:49:36.29#ibcon#read 4, iclass 7, count 2 2006.169.07:49:36.29#ibcon#about to read 5, iclass 7, count 2 2006.169.07:49:36.29#ibcon#read 5, iclass 7, count 2 2006.169.07:49:36.29#ibcon#about to read 6, iclass 7, count 2 2006.169.07:49:36.29#ibcon#read 6, iclass 7, count 2 2006.169.07:49:36.29#ibcon#end of sib2, iclass 7, count 2 2006.169.07:49:36.29#ibcon#*mode == 0, iclass 7, count 2 2006.169.07:49:36.29#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.169.07:49:36.29#ibcon#[25=AT05-07\r\n] 2006.169.07:49:36.29#ibcon#*before write, iclass 7, count 2 2006.169.07:49:36.29#ibcon#enter sib2, iclass 7, count 2 2006.169.07:49:36.29#ibcon#flushed, iclass 7, count 2 2006.169.07:49:36.29#ibcon#about to write, iclass 7, count 2 2006.169.07:49:36.29#ibcon#wrote, iclass 7, count 2 2006.169.07:49:36.29#ibcon#about to read 3, iclass 7, count 2 2006.169.07:49:36.32#ibcon#read 3, iclass 7, count 2 2006.169.07:49:36.32#ibcon#about to read 4, iclass 7, count 2 2006.169.07:49:36.32#ibcon#read 4, iclass 7, count 2 2006.169.07:49:36.32#ibcon#about to read 5, iclass 7, count 2 2006.169.07:49:36.32#ibcon#read 5, iclass 7, count 2 2006.169.07:49:36.32#ibcon#about to read 6, iclass 7, count 2 2006.169.07:49:36.32#ibcon#read 6, iclass 7, count 2 2006.169.07:49:36.32#ibcon#end of sib2, iclass 7, count 2 2006.169.07:49:36.32#ibcon#*after write, iclass 7, count 2 2006.169.07:49:36.32#ibcon#*before return 0, iclass 7, count 2 2006.169.07:49:36.32#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:49:36.32#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:49:36.32#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.169.07:49:36.32#ibcon#ireg 7 cls_cnt 0 2006.169.07:49:36.32#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:49:36.44#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:49:36.44#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:49:36.44#ibcon#enter wrdev, iclass 7, count 0 2006.169.07:49:36.44#ibcon#first serial, iclass 7, count 0 2006.169.07:49:36.44#ibcon#enter sib2, iclass 7, count 0 2006.169.07:49:36.44#ibcon#flushed, iclass 7, count 0 2006.169.07:49:36.44#ibcon#about to write, iclass 7, count 0 2006.169.07:49:36.44#ibcon#wrote, iclass 7, count 0 2006.169.07:49:36.44#ibcon#about to read 3, iclass 7, count 0 2006.169.07:49:36.46#ibcon#read 3, iclass 7, count 0 2006.169.07:49:36.46#ibcon#about to read 4, iclass 7, count 0 2006.169.07:49:36.46#ibcon#read 4, iclass 7, count 0 2006.169.07:49:36.46#ibcon#about to read 5, iclass 7, count 0 2006.169.07:49:36.46#ibcon#read 5, iclass 7, count 0 2006.169.07:49:36.46#ibcon#about to read 6, iclass 7, count 0 2006.169.07:49:36.46#ibcon#read 6, iclass 7, count 0 2006.169.07:49:36.46#ibcon#end of sib2, iclass 7, count 0 2006.169.07:49:36.46#ibcon#*mode == 0, iclass 7, count 0 2006.169.07:49:36.46#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.169.07:49:36.46#ibcon#[25=USB\r\n] 2006.169.07:49:36.46#ibcon#*before write, iclass 7, count 0 2006.169.07:49:36.46#ibcon#enter sib2, iclass 7, count 0 2006.169.07:49:36.46#ibcon#flushed, iclass 7, count 0 2006.169.07:49:36.46#ibcon#about to write, iclass 7, count 0 2006.169.07:49:36.46#ibcon#wrote, iclass 7, count 0 2006.169.07:49:36.46#ibcon#about to read 3, iclass 7, count 0 2006.169.07:49:36.49#ibcon#read 3, iclass 7, count 0 2006.169.07:49:36.49#ibcon#about to read 4, iclass 7, count 0 2006.169.07:49:36.49#ibcon#read 4, iclass 7, count 0 2006.169.07:49:36.49#ibcon#about to read 5, iclass 7, count 0 2006.169.07:49:36.49#ibcon#read 5, iclass 7, count 0 2006.169.07:49:36.49#ibcon#about to read 6, iclass 7, count 0 2006.169.07:49:36.49#ibcon#read 6, iclass 7, count 0 2006.169.07:49:36.49#ibcon#end of sib2, iclass 7, count 0 2006.169.07:49:36.49#ibcon#*after write, iclass 7, count 0 2006.169.07:49:36.49#ibcon#*before return 0, iclass 7, count 0 2006.169.07:49:36.49#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:49:36.49#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:49:36.49#ibcon#about to clear, iclass 7 cls_cnt 0 2006.169.07:49:36.49#ibcon#cleared, iclass 7 cls_cnt 0 2006.169.07:49:36.49$vc4f8/valo=6,772.99 2006.169.07:49:36.49#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.169.07:49:36.49#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.169.07:49:36.49#ibcon#ireg 17 cls_cnt 0 2006.169.07:49:36.49#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.169.07:49:36.49#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.169.07:49:36.49#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.169.07:49:36.49#ibcon#enter wrdev, iclass 11, count 0 2006.169.07:49:36.49#ibcon#first serial, iclass 11, count 0 2006.169.07:49:36.49#ibcon#enter sib2, iclass 11, count 0 2006.169.07:49:36.49#ibcon#flushed, iclass 11, count 0 2006.169.07:49:36.49#ibcon#about to write, iclass 11, count 0 2006.169.07:49:36.49#ibcon#wrote, iclass 11, count 0 2006.169.07:49:36.49#ibcon#about to read 3, iclass 11, count 0 2006.169.07:49:36.51#ibcon#read 3, iclass 11, count 0 2006.169.07:49:36.51#ibcon#about to read 4, iclass 11, count 0 2006.169.07:49:36.51#ibcon#read 4, iclass 11, count 0 2006.169.07:49:36.51#ibcon#about to read 5, iclass 11, count 0 2006.169.07:49:36.51#ibcon#read 5, iclass 11, count 0 2006.169.07:49:36.51#ibcon#about to read 6, iclass 11, count 0 2006.169.07:49:36.51#ibcon#read 6, iclass 11, count 0 2006.169.07:49:36.51#ibcon#end of sib2, iclass 11, count 0 2006.169.07:49:36.51#ibcon#*mode == 0, iclass 11, count 0 2006.169.07:49:36.51#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.169.07:49:36.51#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.07:49:36.51#ibcon#*before write, iclass 11, count 0 2006.169.07:49:36.51#ibcon#enter sib2, iclass 11, count 0 2006.169.07:49:36.51#ibcon#flushed, iclass 11, count 0 2006.169.07:49:36.51#ibcon#about to write, iclass 11, count 0 2006.169.07:49:36.51#ibcon#wrote, iclass 11, count 0 2006.169.07:49:36.51#ibcon#about to read 3, iclass 11, count 0 2006.169.07:49:36.55#ibcon#read 3, iclass 11, count 0 2006.169.07:49:36.55#ibcon#about to read 4, iclass 11, count 0 2006.169.07:49:36.55#ibcon#read 4, iclass 11, count 0 2006.169.07:49:36.55#ibcon#about to read 5, iclass 11, count 0 2006.169.07:49:36.55#ibcon#read 5, iclass 11, count 0 2006.169.07:49:36.55#ibcon#about to read 6, iclass 11, count 0 2006.169.07:49:36.55#ibcon#read 6, iclass 11, count 0 2006.169.07:49:36.55#ibcon#end of sib2, iclass 11, count 0 2006.169.07:49:36.55#ibcon#*after write, iclass 11, count 0 2006.169.07:49:36.55#ibcon#*before return 0, iclass 11, count 0 2006.169.07:49:36.55#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.169.07:49:36.55#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.169.07:49:36.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.169.07:49:36.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.169.07:49:36.55$vc4f8/va=6,6 2006.169.07:49:36.55#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.169.07:49:36.55#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.169.07:49:36.55#ibcon#ireg 11 cls_cnt 2 2006.169.07:49:36.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.169.07:49:36.61#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.169.07:49:36.61#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.169.07:49:36.61#ibcon#enter wrdev, iclass 13, count 2 2006.169.07:49:36.61#ibcon#first serial, iclass 13, count 2 2006.169.07:49:36.61#ibcon#enter sib2, iclass 13, count 2 2006.169.07:49:36.61#ibcon#flushed, iclass 13, count 2 2006.169.07:49:36.61#ibcon#about to write, iclass 13, count 2 2006.169.07:49:36.61#ibcon#wrote, iclass 13, count 2 2006.169.07:49:36.61#ibcon#about to read 3, iclass 13, count 2 2006.169.07:49:36.63#ibcon#read 3, iclass 13, count 2 2006.169.07:49:36.63#ibcon#about to read 4, iclass 13, count 2 2006.169.07:49:36.63#ibcon#read 4, iclass 13, count 2 2006.169.07:49:36.63#ibcon#about to read 5, iclass 13, count 2 2006.169.07:49:36.63#ibcon#read 5, iclass 13, count 2 2006.169.07:49:36.63#ibcon#about to read 6, iclass 13, count 2 2006.169.07:49:36.63#ibcon#read 6, iclass 13, count 2 2006.169.07:49:36.63#ibcon#end of sib2, iclass 13, count 2 2006.169.07:49:36.63#ibcon#*mode == 0, iclass 13, count 2 2006.169.07:49:36.63#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.169.07:49:36.63#ibcon#[25=AT06-06\r\n] 2006.169.07:49:36.63#ibcon#*before write, iclass 13, count 2 2006.169.07:49:36.63#ibcon#enter sib2, iclass 13, count 2 2006.169.07:49:36.63#ibcon#flushed, iclass 13, count 2 2006.169.07:49:36.63#ibcon#about to write, iclass 13, count 2 2006.169.07:49:36.63#ibcon#wrote, iclass 13, count 2 2006.169.07:49:36.63#ibcon#about to read 3, iclass 13, count 2 2006.169.07:49:36.66#ibcon#read 3, iclass 13, count 2 2006.169.07:49:36.66#ibcon#about to read 4, iclass 13, count 2 2006.169.07:49:36.66#ibcon#read 4, iclass 13, count 2 2006.169.07:49:36.66#ibcon#about to read 5, iclass 13, count 2 2006.169.07:49:36.66#ibcon#read 5, iclass 13, count 2 2006.169.07:49:36.66#ibcon#about to read 6, iclass 13, count 2 2006.169.07:49:36.66#ibcon#read 6, iclass 13, count 2 2006.169.07:49:36.66#ibcon#end of sib2, iclass 13, count 2 2006.169.07:49:36.66#ibcon#*after write, iclass 13, count 2 2006.169.07:49:36.66#ibcon#*before return 0, iclass 13, count 2 2006.169.07:49:36.66#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.169.07:49:36.66#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.169.07:49:36.66#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.169.07:49:36.66#ibcon#ireg 7 cls_cnt 0 2006.169.07:49:36.66#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.169.07:49:36.78#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.169.07:49:36.78#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.169.07:49:36.78#ibcon#enter wrdev, iclass 13, count 0 2006.169.07:49:36.78#ibcon#first serial, iclass 13, count 0 2006.169.07:49:36.78#ibcon#enter sib2, iclass 13, count 0 2006.169.07:49:36.78#ibcon#flushed, iclass 13, count 0 2006.169.07:49:36.78#ibcon#about to write, iclass 13, count 0 2006.169.07:49:36.78#ibcon#wrote, iclass 13, count 0 2006.169.07:49:36.78#ibcon#about to read 3, iclass 13, count 0 2006.169.07:49:36.80#ibcon#read 3, iclass 13, count 0 2006.169.07:49:36.80#ibcon#about to read 4, iclass 13, count 0 2006.169.07:49:36.80#ibcon#read 4, iclass 13, count 0 2006.169.07:49:36.80#ibcon#about to read 5, iclass 13, count 0 2006.169.07:49:36.80#ibcon#read 5, iclass 13, count 0 2006.169.07:49:36.80#ibcon#about to read 6, iclass 13, count 0 2006.169.07:49:36.80#ibcon#read 6, iclass 13, count 0 2006.169.07:49:36.80#ibcon#end of sib2, iclass 13, count 0 2006.169.07:49:36.80#ibcon#*mode == 0, iclass 13, count 0 2006.169.07:49:36.80#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.07:49:36.80#ibcon#[25=USB\r\n] 2006.169.07:49:36.80#ibcon#*before write, iclass 13, count 0 2006.169.07:49:36.80#ibcon#enter sib2, iclass 13, count 0 2006.169.07:49:36.80#ibcon#flushed, iclass 13, count 0 2006.169.07:49:36.80#ibcon#about to write, iclass 13, count 0 2006.169.07:49:36.80#ibcon#wrote, iclass 13, count 0 2006.169.07:49:36.80#ibcon#about to read 3, iclass 13, count 0 2006.169.07:49:36.83#ibcon#read 3, iclass 13, count 0 2006.169.07:49:36.83#ibcon#about to read 4, iclass 13, count 0 2006.169.07:49:36.83#ibcon#read 4, iclass 13, count 0 2006.169.07:49:36.83#ibcon#about to read 5, iclass 13, count 0 2006.169.07:49:36.83#ibcon#read 5, iclass 13, count 0 2006.169.07:49:36.83#ibcon#about to read 6, iclass 13, count 0 2006.169.07:49:36.83#ibcon#read 6, iclass 13, count 0 2006.169.07:49:36.83#ibcon#end of sib2, iclass 13, count 0 2006.169.07:49:36.83#ibcon#*after write, iclass 13, count 0 2006.169.07:49:36.83#ibcon#*before return 0, iclass 13, count 0 2006.169.07:49:36.83#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.169.07:49:36.83#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.169.07:49:36.83#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.07:49:36.83#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.07:49:36.83$vc4f8/valo=7,832.99 2006.169.07:49:36.83#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.169.07:49:36.83#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.169.07:49:36.83#ibcon#ireg 17 cls_cnt 0 2006.169.07:49:36.83#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:49:36.83#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:49:36.83#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:49:36.83#ibcon#enter wrdev, iclass 15, count 0 2006.169.07:49:36.83#ibcon#first serial, iclass 15, count 0 2006.169.07:49:36.83#ibcon#enter sib2, iclass 15, count 0 2006.169.07:49:36.83#ibcon#flushed, iclass 15, count 0 2006.169.07:49:36.83#ibcon#about to write, iclass 15, count 0 2006.169.07:49:36.83#ibcon#wrote, iclass 15, count 0 2006.169.07:49:36.83#ibcon#about to read 3, iclass 15, count 0 2006.169.07:49:36.85#ibcon#read 3, iclass 15, count 0 2006.169.07:49:36.85#ibcon#about to read 4, iclass 15, count 0 2006.169.07:49:36.85#ibcon#read 4, iclass 15, count 0 2006.169.07:49:36.85#ibcon#about to read 5, iclass 15, count 0 2006.169.07:49:36.85#ibcon#read 5, iclass 15, count 0 2006.169.07:49:36.85#ibcon#about to read 6, iclass 15, count 0 2006.169.07:49:36.85#ibcon#read 6, iclass 15, count 0 2006.169.07:49:36.85#ibcon#end of sib2, iclass 15, count 0 2006.169.07:49:36.85#ibcon#*mode == 0, iclass 15, count 0 2006.169.07:49:36.85#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.169.07:49:36.85#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.07:49:36.85#ibcon#*before write, iclass 15, count 0 2006.169.07:49:36.85#ibcon#enter sib2, iclass 15, count 0 2006.169.07:49:36.85#ibcon#flushed, iclass 15, count 0 2006.169.07:49:36.85#ibcon#about to write, iclass 15, count 0 2006.169.07:49:36.85#ibcon#wrote, iclass 15, count 0 2006.169.07:49:36.85#ibcon#about to read 3, iclass 15, count 0 2006.169.07:49:36.89#ibcon#read 3, iclass 15, count 0 2006.169.07:49:36.89#ibcon#about to read 4, iclass 15, count 0 2006.169.07:49:36.89#ibcon#read 4, iclass 15, count 0 2006.169.07:49:36.89#ibcon#about to read 5, iclass 15, count 0 2006.169.07:49:36.89#ibcon#read 5, iclass 15, count 0 2006.169.07:49:36.89#ibcon#about to read 6, iclass 15, count 0 2006.169.07:49:36.89#ibcon#read 6, iclass 15, count 0 2006.169.07:49:36.89#ibcon#end of sib2, iclass 15, count 0 2006.169.07:49:36.89#ibcon#*after write, iclass 15, count 0 2006.169.07:49:36.89#ibcon#*before return 0, iclass 15, count 0 2006.169.07:49:36.89#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:49:36.89#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.169.07:49:36.89#ibcon#about to clear, iclass 15 cls_cnt 0 2006.169.07:49:36.89#ibcon#cleared, iclass 15 cls_cnt 0 2006.169.07:49:36.89$vc4f8/va=7,6 2006.169.07:49:36.89#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.169.07:49:36.89#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.169.07:49:36.89#ibcon#ireg 11 cls_cnt 2 2006.169.07:49:36.89#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.169.07:49:36.95#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.169.07:49:36.95#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.169.07:49:36.95#ibcon#enter wrdev, iclass 17, count 2 2006.169.07:49:36.95#ibcon#first serial, iclass 17, count 2 2006.169.07:49:36.95#ibcon#enter sib2, iclass 17, count 2 2006.169.07:49:36.95#ibcon#flushed, iclass 17, count 2 2006.169.07:49:36.95#ibcon#about to write, iclass 17, count 2 2006.169.07:49:36.95#ibcon#wrote, iclass 17, count 2 2006.169.07:49:36.95#ibcon#about to read 3, iclass 17, count 2 2006.169.07:49:36.97#ibcon#read 3, iclass 17, count 2 2006.169.07:49:36.97#ibcon#about to read 4, iclass 17, count 2 2006.169.07:49:36.97#ibcon#read 4, iclass 17, count 2 2006.169.07:49:36.97#ibcon#about to read 5, iclass 17, count 2 2006.169.07:49:36.97#ibcon#read 5, iclass 17, count 2 2006.169.07:49:36.97#ibcon#about to read 6, iclass 17, count 2 2006.169.07:49:36.97#ibcon#read 6, iclass 17, count 2 2006.169.07:49:36.97#ibcon#end of sib2, iclass 17, count 2 2006.169.07:49:36.97#ibcon#*mode == 0, iclass 17, count 2 2006.169.07:49:36.97#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.169.07:49:36.97#ibcon#[25=AT07-06\r\n] 2006.169.07:49:36.97#ibcon#*before write, iclass 17, count 2 2006.169.07:49:36.97#ibcon#enter sib2, iclass 17, count 2 2006.169.07:49:36.97#ibcon#flushed, iclass 17, count 2 2006.169.07:49:36.97#ibcon#about to write, iclass 17, count 2 2006.169.07:49:36.97#ibcon#wrote, iclass 17, count 2 2006.169.07:49:36.97#ibcon#about to read 3, iclass 17, count 2 2006.169.07:49:37.00#ibcon#read 3, iclass 17, count 2 2006.169.07:49:37.00#ibcon#about to read 4, iclass 17, count 2 2006.169.07:49:37.00#ibcon#read 4, iclass 17, count 2 2006.169.07:49:37.00#ibcon#about to read 5, iclass 17, count 2 2006.169.07:49:37.00#ibcon#read 5, iclass 17, count 2 2006.169.07:49:37.00#ibcon#about to read 6, iclass 17, count 2 2006.169.07:49:37.00#ibcon#read 6, iclass 17, count 2 2006.169.07:49:37.00#ibcon#end of sib2, iclass 17, count 2 2006.169.07:49:37.00#ibcon#*after write, iclass 17, count 2 2006.169.07:49:37.00#ibcon#*before return 0, iclass 17, count 2 2006.169.07:49:37.00#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.169.07:49:37.00#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.169.07:49:37.00#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.169.07:49:37.00#ibcon#ireg 7 cls_cnt 0 2006.169.07:49:37.00#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.169.07:49:37.12#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.169.07:49:37.12#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.169.07:49:37.12#ibcon#enter wrdev, iclass 17, count 0 2006.169.07:49:37.12#ibcon#first serial, iclass 17, count 0 2006.169.07:49:37.12#ibcon#enter sib2, iclass 17, count 0 2006.169.07:49:37.12#ibcon#flushed, iclass 17, count 0 2006.169.07:49:37.12#ibcon#about to write, iclass 17, count 0 2006.169.07:49:37.12#ibcon#wrote, iclass 17, count 0 2006.169.07:49:37.12#ibcon#about to read 3, iclass 17, count 0 2006.169.07:49:37.14#ibcon#read 3, iclass 17, count 0 2006.169.07:49:37.14#ibcon#about to read 4, iclass 17, count 0 2006.169.07:49:37.14#ibcon#read 4, iclass 17, count 0 2006.169.07:49:37.14#ibcon#about to read 5, iclass 17, count 0 2006.169.07:49:37.14#ibcon#read 5, iclass 17, count 0 2006.169.07:49:37.14#ibcon#about to read 6, iclass 17, count 0 2006.169.07:49:37.14#ibcon#read 6, iclass 17, count 0 2006.169.07:49:37.14#ibcon#end of sib2, iclass 17, count 0 2006.169.07:49:37.14#ibcon#*mode == 0, iclass 17, count 0 2006.169.07:49:37.14#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.169.07:49:37.14#ibcon#[25=USB\r\n] 2006.169.07:49:37.14#ibcon#*before write, iclass 17, count 0 2006.169.07:49:37.14#ibcon#enter sib2, iclass 17, count 0 2006.169.07:49:37.14#ibcon#flushed, iclass 17, count 0 2006.169.07:49:37.14#ibcon#about to write, iclass 17, count 0 2006.169.07:49:37.14#ibcon#wrote, iclass 17, count 0 2006.169.07:49:37.14#ibcon#about to read 3, iclass 17, count 0 2006.169.07:49:37.17#ibcon#read 3, iclass 17, count 0 2006.169.07:49:37.17#ibcon#about to read 4, iclass 17, count 0 2006.169.07:49:37.17#ibcon#read 4, iclass 17, count 0 2006.169.07:49:37.17#ibcon#about to read 5, iclass 17, count 0 2006.169.07:49:37.17#ibcon#read 5, iclass 17, count 0 2006.169.07:49:37.17#ibcon#about to read 6, iclass 17, count 0 2006.169.07:49:37.17#ibcon#read 6, iclass 17, count 0 2006.169.07:49:37.17#ibcon#end of sib2, iclass 17, count 0 2006.169.07:49:37.17#ibcon#*after write, iclass 17, count 0 2006.169.07:49:37.17#ibcon#*before return 0, iclass 17, count 0 2006.169.07:49:37.17#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.169.07:49:37.17#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.169.07:49:37.17#ibcon#about to clear, iclass 17 cls_cnt 0 2006.169.07:49:37.17#ibcon#cleared, iclass 17 cls_cnt 0 2006.169.07:49:37.17$vc4f8/valo=8,852.99 2006.169.07:49:37.17#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.169.07:49:37.17#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.169.07:49:37.17#ibcon#ireg 17 cls_cnt 0 2006.169.07:49:37.17#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.169.07:49:37.17#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.169.07:49:37.17#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.169.07:49:37.17#ibcon#enter wrdev, iclass 19, count 0 2006.169.07:49:37.17#ibcon#first serial, iclass 19, count 0 2006.169.07:49:37.17#ibcon#enter sib2, iclass 19, count 0 2006.169.07:49:37.17#ibcon#flushed, iclass 19, count 0 2006.169.07:49:37.17#ibcon#about to write, iclass 19, count 0 2006.169.07:49:37.17#ibcon#wrote, iclass 19, count 0 2006.169.07:49:37.17#ibcon#about to read 3, iclass 19, count 0 2006.169.07:49:37.19#ibcon#read 3, iclass 19, count 0 2006.169.07:49:37.19#ibcon#about to read 4, iclass 19, count 0 2006.169.07:49:37.19#ibcon#read 4, iclass 19, count 0 2006.169.07:49:37.19#ibcon#about to read 5, iclass 19, count 0 2006.169.07:49:37.19#ibcon#read 5, iclass 19, count 0 2006.169.07:49:37.19#ibcon#about to read 6, iclass 19, count 0 2006.169.07:49:37.19#ibcon#read 6, iclass 19, count 0 2006.169.07:49:37.19#ibcon#end of sib2, iclass 19, count 0 2006.169.07:49:37.19#ibcon#*mode == 0, iclass 19, count 0 2006.169.07:49:37.19#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.169.07:49:37.19#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.07:49:37.19#ibcon#*before write, iclass 19, count 0 2006.169.07:49:37.19#ibcon#enter sib2, iclass 19, count 0 2006.169.07:49:37.19#ibcon#flushed, iclass 19, count 0 2006.169.07:49:37.19#ibcon#about to write, iclass 19, count 0 2006.169.07:49:37.19#ibcon#wrote, iclass 19, count 0 2006.169.07:49:37.19#ibcon#about to read 3, iclass 19, count 0 2006.169.07:49:37.23#ibcon#read 3, iclass 19, count 0 2006.169.07:49:37.23#ibcon#about to read 4, iclass 19, count 0 2006.169.07:49:37.23#ibcon#read 4, iclass 19, count 0 2006.169.07:49:37.23#ibcon#about to read 5, iclass 19, count 0 2006.169.07:49:37.23#ibcon#read 5, iclass 19, count 0 2006.169.07:49:37.23#ibcon#about to read 6, iclass 19, count 0 2006.169.07:49:37.23#ibcon#read 6, iclass 19, count 0 2006.169.07:49:37.23#ibcon#end of sib2, iclass 19, count 0 2006.169.07:49:37.23#ibcon#*after write, iclass 19, count 0 2006.169.07:49:37.23#ibcon#*before return 0, iclass 19, count 0 2006.169.07:49:37.23#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.169.07:49:37.23#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.169.07:49:37.23#ibcon#about to clear, iclass 19 cls_cnt 0 2006.169.07:49:37.23#ibcon#cleared, iclass 19 cls_cnt 0 2006.169.07:49:37.23$vc4f8/va=8,7 2006.169.07:49:37.23#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.169.07:49:37.23#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.169.07:49:37.23#ibcon#ireg 11 cls_cnt 2 2006.169.07:49:37.23#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.169.07:49:37.29#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.169.07:49:37.29#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.169.07:49:37.29#ibcon#enter wrdev, iclass 21, count 2 2006.169.07:49:37.29#ibcon#first serial, iclass 21, count 2 2006.169.07:49:37.29#ibcon#enter sib2, iclass 21, count 2 2006.169.07:49:37.29#ibcon#flushed, iclass 21, count 2 2006.169.07:49:37.29#ibcon#about to write, iclass 21, count 2 2006.169.07:49:37.29#ibcon#wrote, iclass 21, count 2 2006.169.07:49:37.29#ibcon#about to read 3, iclass 21, count 2 2006.169.07:49:37.31#ibcon#read 3, iclass 21, count 2 2006.169.07:49:37.31#ibcon#about to read 4, iclass 21, count 2 2006.169.07:49:37.31#ibcon#read 4, iclass 21, count 2 2006.169.07:49:37.31#ibcon#about to read 5, iclass 21, count 2 2006.169.07:49:37.31#ibcon#read 5, iclass 21, count 2 2006.169.07:49:37.31#ibcon#about to read 6, iclass 21, count 2 2006.169.07:49:37.31#ibcon#read 6, iclass 21, count 2 2006.169.07:49:37.31#ibcon#end of sib2, iclass 21, count 2 2006.169.07:49:37.31#ibcon#*mode == 0, iclass 21, count 2 2006.169.07:49:37.31#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.169.07:49:37.31#ibcon#[25=AT08-07\r\n] 2006.169.07:49:37.31#ibcon#*before write, iclass 21, count 2 2006.169.07:49:37.31#ibcon#enter sib2, iclass 21, count 2 2006.169.07:49:37.31#ibcon#flushed, iclass 21, count 2 2006.169.07:49:37.31#ibcon#about to write, iclass 21, count 2 2006.169.07:49:37.31#ibcon#wrote, iclass 21, count 2 2006.169.07:49:37.31#ibcon#about to read 3, iclass 21, count 2 2006.169.07:49:37.34#ibcon#read 3, iclass 21, count 2 2006.169.07:49:37.34#ibcon#about to read 4, iclass 21, count 2 2006.169.07:49:37.34#ibcon#read 4, iclass 21, count 2 2006.169.07:49:37.34#ibcon#about to read 5, iclass 21, count 2 2006.169.07:49:37.34#ibcon#read 5, iclass 21, count 2 2006.169.07:49:37.34#ibcon#about to read 6, iclass 21, count 2 2006.169.07:49:37.34#ibcon#read 6, iclass 21, count 2 2006.169.07:49:37.34#ibcon#end of sib2, iclass 21, count 2 2006.169.07:49:37.34#ibcon#*after write, iclass 21, count 2 2006.169.07:49:37.34#ibcon#*before return 0, iclass 21, count 2 2006.169.07:49:37.34#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.169.07:49:37.34#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.169.07:49:37.34#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.169.07:49:37.34#ibcon#ireg 7 cls_cnt 0 2006.169.07:49:37.34#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.169.07:49:37.46#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.169.07:49:37.46#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.169.07:49:37.46#ibcon#enter wrdev, iclass 21, count 0 2006.169.07:49:37.46#ibcon#first serial, iclass 21, count 0 2006.169.07:49:37.46#ibcon#enter sib2, iclass 21, count 0 2006.169.07:49:37.46#ibcon#flushed, iclass 21, count 0 2006.169.07:49:37.46#ibcon#about to write, iclass 21, count 0 2006.169.07:49:37.46#ibcon#wrote, iclass 21, count 0 2006.169.07:49:37.46#ibcon#about to read 3, iclass 21, count 0 2006.169.07:49:37.48#ibcon#read 3, iclass 21, count 0 2006.169.07:49:37.48#ibcon#about to read 4, iclass 21, count 0 2006.169.07:49:37.48#ibcon#read 4, iclass 21, count 0 2006.169.07:49:37.48#ibcon#about to read 5, iclass 21, count 0 2006.169.07:49:37.48#ibcon#read 5, iclass 21, count 0 2006.169.07:49:37.48#ibcon#about to read 6, iclass 21, count 0 2006.169.07:49:37.48#ibcon#read 6, iclass 21, count 0 2006.169.07:49:37.48#ibcon#end of sib2, iclass 21, count 0 2006.169.07:49:37.48#ibcon#*mode == 0, iclass 21, count 0 2006.169.07:49:37.48#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.169.07:49:37.48#ibcon#[25=USB\r\n] 2006.169.07:49:37.48#ibcon#*before write, iclass 21, count 0 2006.169.07:49:37.48#ibcon#enter sib2, iclass 21, count 0 2006.169.07:49:37.48#ibcon#flushed, iclass 21, count 0 2006.169.07:49:37.48#ibcon#about to write, iclass 21, count 0 2006.169.07:49:37.48#ibcon#wrote, iclass 21, count 0 2006.169.07:49:37.48#ibcon#about to read 3, iclass 21, count 0 2006.169.07:49:37.51#ibcon#read 3, iclass 21, count 0 2006.169.07:49:37.51#ibcon#about to read 4, iclass 21, count 0 2006.169.07:49:37.51#ibcon#read 4, iclass 21, count 0 2006.169.07:49:37.51#ibcon#about to read 5, iclass 21, count 0 2006.169.07:49:37.51#ibcon#read 5, iclass 21, count 0 2006.169.07:49:37.51#ibcon#about to read 6, iclass 21, count 0 2006.169.07:49:37.51#ibcon#read 6, iclass 21, count 0 2006.169.07:49:37.51#ibcon#end of sib2, iclass 21, count 0 2006.169.07:49:37.51#ibcon#*after write, iclass 21, count 0 2006.169.07:49:37.51#ibcon#*before return 0, iclass 21, count 0 2006.169.07:49:37.51#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.169.07:49:37.51#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.169.07:49:37.51#ibcon#about to clear, iclass 21 cls_cnt 0 2006.169.07:49:37.51#ibcon#cleared, iclass 21 cls_cnt 0 2006.169.07:49:37.51$vc4f8/vblo=1,632.99 2006.169.07:49:37.51#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.169.07:49:37.51#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.169.07:49:37.51#ibcon#ireg 17 cls_cnt 0 2006.169.07:49:37.51#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.169.07:49:37.51#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.169.07:49:37.51#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.169.07:49:37.51#ibcon#enter wrdev, iclass 23, count 0 2006.169.07:49:37.51#ibcon#first serial, iclass 23, count 0 2006.169.07:49:37.51#ibcon#enter sib2, iclass 23, count 0 2006.169.07:49:37.51#ibcon#flushed, iclass 23, count 0 2006.169.07:49:37.51#ibcon#about to write, iclass 23, count 0 2006.169.07:49:37.51#ibcon#wrote, iclass 23, count 0 2006.169.07:49:37.51#ibcon#about to read 3, iclass 23, count 0 2006.169.07:49:37.53#ibcon#read 3, iclass 23, count 0 2006.169.07:49:37.53#ibcon#about to read 4, iclass 23, count 0 2006.169.07:49:37.53#ibcon#read 4, iclass 23, count 0 2006.169.07:49:37.53#ibcon#about to read 5, iclass 23, count 0 2006.169.07:49:37.53#ibcon#read 5, iclass 23, count 0 2006.169.07:49:37.53#ibcon#about to read 6, iclass 23, count 0 2006.169.07:49:37.53#ibcon#read 6, iclass 23, count 0 2006.169.07:49:37.53#ibcon#end of sib2, iclass 23, count 0 2006.169.07:49:37.53#ibcon#*mode == 0, iclass 23, count 0 2006.169.07:49:37.53#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.169.07:49:37.53#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.07:49:37.53#ibcon#*before write, iclass 23, count 0 2006.169.07:49:37.53#ibcon#enter sib2, iclass 23, count 0 2006.169.07:49:37.53#ibcon#flushed, iclass 23, count 0 2006.169.07:49:37.53#ibcon#about to write, iclass 23, count 0 2006.169.07:49:37.53#ibcon#wrote, iclass 23, count 0 2006.169.07:49:37.53#ibcon#about to read 3, iclass 23, count 0 2006.169.07:49:37.57#ibcon#read 3, iclass 23, count 0 2006.169.07:49:37.57#ibcon#about to read 4, iclass 23, count 0 2006.169.07:49:37.57#ibcon#read 4, iclass 23, count 0 2006.169.07:49:37.57#ibcon#about to read 5, iclass 23, count 0 2006.169.07:49:37.57#ibcon#read 5, iclass 23, count 0 2006.169.07:49:37.57#ibcon#about to read 6, iclass 23, count 0 2006.169.07:49:37.57#ibcon#read 6, iclass 23, count 0 2006.169.07:49:37.57#ibcon#end of sib2, iclass 23, count 0 2006.169.07:49:37.57#ibcon#*after write, iclass 23, count 0 2006.169.07:49:37.57#ibcon#*before return 0, iclass 23, count 0 2006.169.07:49:37.57#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.169.07:49:37.57#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.169.07:49:37.57#ibcon#about to clear, iclass 23 cls_cnt 0 2006.169.07:49:37.57#ibcon#cleared, iclass 23 cls_cnt 0 2006.169.07:49:37.57$vc4f8/vb=1,4 2006.169.07:49:37.57#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.169.07:49:37.57#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.169.07:49:37.57#ibcon#ireg 11 cls_cnt 2 2006.169.07:49:37.57#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.169.07:49:37.57#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.169.07:49:37.57#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.169.07:49:37.57#ibcon#enter wrdev, iclass 25, count 2 2006.169.07:49:37.57#ibcon#first serial, iclass 25, count 2 2006.169.07:49:37.57#ibcon#enter sib2, iclass 25, count 2 2006.169.07:49:37.57#ibcon#flushed, iclass 25, count 2 2006.169.07:49:37.57#ibcon#about to write, iclass 25, count 2 2006.169.07:49:37.57#ibcon#wrote, iclass 25, count 2 2006.169.07:49:37.57#ibcon#about to read 3, iclass 25, count 2 2006.169.07:49:37.59#ibcon#read 3, iclass 25, count 2 2006.169.07:49:37.59#ibcon#about to read 4, iclass 25, count 2 2006.169.07:49:37.59#ibcon#read 4, iclass 25, count 2 2006.169.07:49:37.59#ibcon#about to read 5, iclass 25, count 2 2006.169.07:49:37.59#ibcon#read 5, iclass 25, count 2 2006.169.07:49:37.59#ibcon#about to read 6, iclass 25, count 2 2006.169.07:49:37.59#ibcon#read 6, iclass 25, count 2 2006.169.07:49:37.59#ibcon#end of sib2, iclass 25, count 2 2006.169.07:49:37.59#ibcon#*mode == 0, iclass 25, count 2 2006.169.07:49:37.59#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.169.07:49:37.59#ibcon#[27=AT01-04\r\n] 2006.169.07:49:37.59#ibcon#*before write, iclass 25, count 2 2006.169.07:49:37.59#ibcon#enter sib2, iclass 25, count 2 2006.169.07:49:37.59#ibcon#flushed, iclass 25, count 2 2006.169.07:49:37.59#ibcon#about to write, iclass 25, count 2 2006.169.07:49:37.59#ibcon#wrote, iclass 25, count 2 2006.169.07:49:37.59#ibcon#about to read 3, iclass 25, count 2 2006.169.07:49:37.62#ibcon#read 3, iclass 25, count 2 2006.169.07:49:37.62#ibcon#about to read 4, iclass 25, count 2 2006.169.07:49:37.62#ibcon#read 4, iclass 25, count 2 2006.169.07:49:37.62#ibcon#about to read 5, iclass 25, count 2 2006.169.07:49:37.62#ibcon#read 5, iclass 25, count 2 2006.169.07:49:37.62#ibcon#about to read 6, iclass 25, count 2 2006.169.07:49:37.62#ibcon#read 6, iclass 25, count 2 2006.169.07:49:37.62#ibcon#end of sib2, iclass 25, count 2 2006.169.07:49:37.62#ibcon#*after write, iclass 25, count 2 2006.169.07:49:37.62#ibcon#*before return 0, iclass 25, count 2 2006.169.07:49:37.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.169.07:49:37.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.169.07:49:37.62#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.169.07:49:37.62#ibcon#ireg 7 cls_cnt 0 2006.169.07:49:37.62#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.169.07:49:37.74#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.169.07:49:37.74#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.169.07:49:37.74#ibcon#enter wrdev, iclass 25, count 0 2006.169.07:49:37.74#ibcon#first serial, iclass 25, count 0 2006.169.07:49:37.74#ibcon#enter sib2, iclass 25, count 0 2006.169.07:49:37.74#ibcon#flushed, iclass 25, count 0 2006.169.07:49:37.74#ibcon#about to write, iclass 25, count 0 2006.169.07:49:37.74#ibcon#wrote, iclass 25, count 0 2006.169.07:49:37.74#ibcon#about to read 3, iclass 25, count 0 2006.169.07:49:37.76#ibcon#read 3, iclass 25, count 0 2006.169.07:49:37.76#ibcon#about to read 4, iclass 25, count 0 2006.169.07:49:37.76#ibcon#read 4, iclass 25, count 0 2006.169.07:49:37.76#ibcon#about to read 5, iclass 25, count 0 2006.169.07:49:37.76#ibcon#read 5, iclass 25, count 0 2006.169.07:49:37.76#ibcon#about to read 6, iclass 25, count 0 2006.169.07:49:37.76#ibcon#read 6, iclass 25, count 0 2006.169.07:49:37.76#ibcon#end of sib2, iclass 25, count 0 2006.169.07:49:37.76#ibcon#*mode == 0, iclass 25, count 0 2006.169.07:49:37.76#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.169.07:49:37.76#ibcon#[27=USB\r\n] 2006.169.07:49:37.76#ibcon#*before write, iclass 25, count 0 2006.169.07:49:37.76#ibcon#enter sib2, iclass 25, count 0 2006.169.07:49:37.76#ibcon#flushed, iclass 25, count 0 2006.169.07:49:37.76#ibcon#about to write, iclass 25, count 0 2006.169.07:49:37.76#ibcon#wrote, iclass 25, count 0 2006.169.07:49:37.76#ibcon#about to read 3, iclass 25, count 0 2006.169.07:49:37.79#ibcon#read 3, iclass 25, count 0 2006.169.07:49:37.79#ibcon#about to read 4, iclass 25, count 0 2006.169.07:49:37.79#ibcon#read 4, iclass 25, count 0 2006.169.07:49:37.79#ibcon#about to read 5, iclass 25, count 0 2006.169.07:49:37.79#ibcon#read 5, iclass 25, count 0 2006.169.07:49:37.79#ibcon#about to read 6, iclass 25, count 0 2006.169.07:49:37.79#ibcon#read 6, iclass 25, count 0 2006.169.07:49:37.79#ibcon#end of sib2, iclass 25, count 0 2006.169.07:49:37.79#ibcon#*after write, iclass 25, count 0 2006.169.07:49:37.79#ibcon#*before return 0, iclass 25, count 0 2006.169.07:49:37.79#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.169.07:49:37.79#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.169.07:49:37.79#ibcon#about to clear, iclass 25 cls_cnt 0 2006.169.07:49:37.79#ibcon#cleared, iclass 25 cls_cnt 0 2006.169.07:49:37.79$vc4f8/vblo=2,640.99 2006.169.07:49:37.79#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.169.07:49:37.79#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.169.07:49:37.79#ibcon#ireg 17 cls_cnt 0 2006.169.07:49:37.79#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:49:37.79#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:49:37.79#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:49:37.79#ibcon#enter wrdev, iclass 27, count 0 2006.169.07:49:37.79#ibcon#first serial, iclass 27, count 0 2006.169.07:49:37.79#ibcon#enter sib2, iclass 27, count 0 2006.169.07:49:37.79#ibcon#flushed, iclass 27, count 0 2006.169.07:49:37.79#ibcon#about to write, iclass 27, count 0 2006.169.07:49:37.79#ibcon#wrote, iclass 27, count 0 2006.169.07:49:37.79#ibcon#about to read 3, iclass 27, count 0 2006.169.07:49:37.81#ibcon#read 3, iclass 27, count 0 2006.169.07:49:37.81#ibcon#about to read 4, iclass 27, count 0 2006.169.07:49:37.81#ibcon#read 4, iclass 27, count 0 2006.169.07:49:37.81#ibcon#about to read 5, iclass 27, count 0 2006.169.07:49:37.81#ibcon#read 5, iclass 27, count 0 2006.169.07:49:37.81#ibcon#about to read 6, iclass 27, count 0 2006.169.07:49:37.81#ibcon#read 6, iclass 27, count 0 2006.169.07:49:37.81#ibcon#end of sib2, iclass 27, count 0 2006.169.07:49:37.81#ibcon#*mode == 0, iclass 27, count 0 2006.169.07:49:37.81#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.169.07:49:37.81#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.07:49:37.81#ibcon#*before write, iclass 27, count 0 2006.169.07:49:37.81#ibcon#enter sib2, iclass 27, count 0 2006.169.07:49:37.81#ibcon#flushed, iclass 27, count 0 2006.169.07:49:37.81#ibcon#about to write, iclass 27, count 0 2006.169.07:49:37.81#ibcon#wrote, iclass 27, count 0 2006.169.07:49:37.81#ibcon#about to read 3, iclass 27, count 0 2006.169.07:49:37.85#ibcon#read 3, iclass 27, count 0 2006.169.07:49:37.85#ibcon#about to read 4, iclass 27, count 0 2006.169.07:49:37.85#ibcon#read 4, iclass 27, count 0 2006.169.07:49:37.85#ibcon#about to read 5, iclass 27, count 0 2006.169.07:49:37.85#ibcon#read 5, iclass 27, count 0 2006.169.07:49:37.85#ibcon#about to read 6, iclass 27, count 0 2006.169.07:49:37.85#ibcon#read 6, iclass 27, count 0 2006.169.07:49:37.85#ibcon#end of sib2, iclass 27, count 0 2006.169.07:49:37.85#ibcon#*after write, iclass 27, count 0 2006.169.07:49:37.85#ibcon#*before return 0, iclass 27, count 0 2006.169.07:49:37.85#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:49:37.85#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.169.07:49:37.85#ibcon#about to clear, iclass 27 cls_cnt 0 2006.169.07:49:37.85#ibcon#cleared, iclass 27 cls_cnt 0 2006.169.07:49:37.85$vc4f8/vb=2,4 2006.169.07:49:37.85#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.169.07:49:37.85#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.169.07:49:37.85#ibcon#ireg 11 cls_cnt 2 2006.169.07:49:37.85#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.169.07:49:37.91#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.169.07:49:37.91#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.169.07:49:37.91#ibcon#enter wrdev, iclass 29, count 2 2006.169.07:49:37.91#ibcon#first serial, iclass 29, count 2 2006.169.07:49:37.91#ibcon#enter sib2, iclass 29, count 2 2006.169.07:49:37.91#ibcon#flushed, iclass 29, count 2 2006.169.07:49:37.91#ibcon#about to write, iclass 29, count 2 2006.169.07:49:37.91#ibcon#wrote, iclass 29, count 2 2006.169.07:49:37.91#ibcon#about to read 3, iclass 29, count 2 2006.169.07:49:37.93#ibcon#read 3, iclass 29, count 2 2006.169.07:49:37.93#ibcon#about to read 4, iclass 29, count 2 2006.169.07:49:37.93#ibcon#read 4, iclass 29, count 2 2006.169.07:49:37.93#ibcon#about to read 5, iclass 29, count 2 2006.169.07:49:37.93#ibcon#read 5, iclass 29, count 2 2006.169.07:49:37.93#ibcon#about to read 6, iclass 29, count 2 2006.169.07:49:37.93#ibcon#read 6, iclass 29, count 2 2006.169.07:49:37.93#ibcon#end of sib2, iclass 29, count 2 2006.169.07:49:37.93#ibcon#*mode == 0, iclass 29, count 2 2006.169.07:49:37.93#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.169.07:49:37.93#ibcon#[27=AT02-04\r\n] 2006.169.07:49:37.93#ibcon#*before write, iclass 29, count 2 2006.169.07:49:37.93#ibcon#enter sib2, iclass 29, count 2 2006.169.07:49:37.93#ibcon#flushed, iclass 29, count 2 2006.169.07:49:37.93#ibcon#about to write, iclass 29, count 2 2006.169.07:49:37.93#ibcon#wrote, iclass 29, count 2 2006.169.07:49:37.93#ibcon#about to read 3, iclass 29, count 2 2006.169.07:49:37.96#ibcon#read 3, iclass 29, count 2 2006.169.07:49:37.96#ibcon#about to read 4, iclass 29, count 2 2006.169.07:49:37.96#ibcon#read 4, iclass 29, count 2 2006.169.07:49:37.96#ibcon#about to read 5, iclass 29, count 2 2006.169.07:49:37.96#ibcon#read 5, iclass 29, count 2 2006.169.07:49:37.96#ibcon#about to read 6, iclass 29, count 2 2006.169.07:49:37.96#ibcon#read 6, iclass 29, count 2 2006.169.07:49:37.96#ibcon#end of sib2, iclass 29, count 2 2006.169.07:49:37.96#ibcon#*after write, iclass 29, count 2 2006.169.07:49:37.96#ibcon#*before return 0, iclass 29, count 2 2006.169.07:49:37.96#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.169.07:49:37.96#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.169.07:49:37.96#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.169.07:49:37.96#ibcon#ireg 7 cls_cnt 0 2006.169.07:49:37.96#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.169.07:49:38.08#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.169.07:49:38.08#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.169.07:49:38.08#ibcon#enter wrdev, iclass 29, count 0 2006.169.07:49:38.08#ibcon#first serial, iclass 29, count 0 2006.169.07:49:38.08#ibcon#enter sib2, iclass 29, count 0 2006.169.07:49:38.08#ibcon#flushed, iclass 29, count 0 2006.169.07:49:38.08#ibcon#about to write, iclass 29, count 0 2006.169.07:49:38.08#ibcon#wrote, iclass 29, count 0 2006.169.07:49:38.08#ibcon#about to read 3, iclass 29, count 0 2006.169.07:49:38.10#ibcon#read 3, iclass 29, count 0 2006.169.07:49:38.10#ibcon#about to read 4, iclass 29, count 0 2006.169.07:49:38.10#ibcon#read 4, iclass 29, count 0 2006.169.07:49:38.10#ibcon#about to read 5, iclass 29, count 0 2006.169.07:49:38.10#ibcon#read 5, iclass 29, count 0 2006.169.07:49:38.10#ibcon#about to read 6, iclass 29, count 0 2006.169.07:49:38.10#ibcon#read 6, iclass 29, count 0 2006.169.07:49:38.10#ibcon#end of sib2, iclass 29, count 0 2006.169.07:49:38.10#ibcon#*mode == 0, iclass 29, count 0 2006.169.07:49:38.10#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.169.07:49:38.10#ibcon#[27=USB\r\n] 2006.169.07:49:38.10#ibcon#*before write, iclass 29, count 0 2006.169.07:49:38.10#ibcon#enter sib2, iclass 29, count 0 2006.169.07:49:38.10#ibcon#flushed, iclass 29, count 0 2006.169.07:49:38.10#ibcon#about to write, iclass 29, count 0 2006.169.07:49:38.10#ibcon#wrote, iclass 29, count 0 2006.169.07:49:38.10#ibcon#about to read 3, iclass 29, count 0 2006.169.07:49:38.13#ibcon#read 3, iclass 29, count 0 2006.169.07:49:38.13#ibcon#about to read 4, iclass 29, count 0 2006.169.07:49:38.13#ibcon#read 4, iclass 29, count 0 2006.169.07:49:38.13#ibcon#about to read 5, iclass 29, count 0 2006.169.07:49:38.13#ibcon#read 5, iclass 29, count 0 2006.169.07:49:38.13#ibcon#about to read 6, iclass 29, count 0 2006.169.07:49:38.13#ibcon#read 6, iclass 29, count 0 2006.169.07:49:38.13#ibcon#end of sib2, iclass 29, count 0 2006.169.07:49:38.13#ibcon#*after write, iclass 29, count 0 2006.169.07:49:38.13#ibcon#*before return 0, iclass 29, count 0 2006.169.07:49:38.13#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.169.07:49:38.13#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.169.07:49:38.13#ibcon#about to clear, iclass 29 cls_cnt 0 2006.169.07:49:38.13#ibcon#cleared, iclass 29 cls_cnt 0 2006.169.07:49:38.13$vc4f8/vblo=3,656.99 2006.169.07:49:38.13#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.169.07:49:38.13#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.169.07:49:38.13#ibcon#ireg 17 cls_cnt 0 2006.169.07:49:38.13#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.169.07:49:38.13#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.169.07:49:38.13#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.169.07:49:38.13#ibcon#enter wrdev, iclass 31, count 0 2006.169.07:49:38.13#ibcon#first serial, iclass 31, count 0 2006.169.07:49:38.13#ibcon#enter sib2, iclass 31, count 0 2006.169.07:49:38.13#ibcon#flushed, iclass 31, count 0 2006.169.07:49:38.13#ibcon#about to write, iclass 31, count 0 2006.169.07:49:38.13#ibcon#wrote, iclass 31, count 0 2006.169.07:49:38.13#ibcon#about to read 3, iclass 31, count 0 2006.169.07:49:38.15#ibcon#read 3, iclass 31, count 0 2006.169.07:49:38.15#ibcon#about to read 4, iclass 31, count 0 2006.169.07:49:38.15#ibcon#read 4, iclass 31, count 0 2006.169.07:49:38.15#ibcon#about to read 5, iclass 31, count 0 2006.169.07:49:38.15#ibcon#read 5, iclass 31, count 0 2006.169.07:49:38.15#ibcon#about to read 6, iclass 31, count 0 2006.169.07:49:38.15#ibcon#read 6, iclass 31, count 0 2006.169.07:49:38.15#ibcon#end of sib2, iclass 31, count 0 2006.169.07:49:38.15#ibcon#*mode == 0, iclass 31, count 0 2006.169.07:49:38.15#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.169.07:49:38.15#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.07:49:38.15#ibcon#*before write, iclass 31, count 0 2006.169.07:49:38.15#ibcon#enter sib2, iclass 31, count 0 2006.169.07:49:38.15#ibcon#flushed, iclass 31, count 0 2006.169.07:49:38.15#ibcon#about to write, iclass 31, count 0 2006.169.07:49:38.15#ibcon#wrote, iclass 31, count 0 2006.169.07:49:38.15#ibcon#about to read 3, iclass 31, count 0 2006.169.07:49:38.19#ibcon#read 3, iclass 31, count 0 2006.169.07:49:38.19#ibcon#about to read 4, iclass 31, count 0 2006.169.07:49:38.19#ibcon#read 4, iclass 31, count 0 2006.169.07:49:38.19#ibcon#about to read 5, iclass 31, count 0 2006.169.07:49:38.19#ibcon#read 5, iclass 31, count 0 2006.169.07:49:38.19#ibcon#about to read 6, iclass 31, count 0 2006.169.07:49:38.19#ibcon#read 6, iclass 31, count 0 2006.169.07:49:38.19#ibcon#end of sib2, iclass 31, count 0 2006.169.07:49:38.19#ibcon#*after write, iclass 31, count 0 2006.169.07:49:38.19#ibcon#*before return 0, iclass 31, count 0 2006.169.07:49:38.19#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.169.07:49:38.19#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.169.07:49:38.19#ibcon#about to clear, iclass 31 cls_cnt 0 2006.169.07:49:38.19#ibcon#cleared, iclass 31 cls_cnt 0 2006.169.07:49:38.19$vc4f8/vb=3,4 2006.169.07:49:38.19#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.169.07:49:38.19#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.169.07:49:38.19#ibcon#ireg 11 cls_cnt 2 2006.169.07:49:38.19#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.169.07:49:38.25#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.169.07:49:38.25#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.169.07:49:38.25#ibcon#enter wrdev, iclass 33, count 2 2006.169.07:49:38.25#ibcon#first serial, iclass 33, count 2 2006.169.07:49:38.25#ibcon#enter sib2, iclass 33, count 2 2006.169.07:49:38.25#ibcon#flushed, iclass 33, count 2 2006.169.07:49:38.25#ibcon#about to write, iclass 33, count 2 2006.169.07:49:38.25#ibcon#wrote, iclass 33, count 2 2006.169.07:49:38.25#ibcon#about to read 3, iclass 33, count 2 2006.169.07:49:38.27#ibcon#read 3, iclass 33, count 2 2006.169.07:49:38.27#ibcon#about to read 4, iclass 33, count 2 2006.169.07:49:38.27#ibcon#read 4, iclass 33, count 2 2006.169.07:49:38.27#ibcon#about to read 5, iclass 33, count 2 2006.169.07:49:38.27#ibcon#read 5, iclass 33, count 2 2006.169.07:49:38.27#ibcon#about to read 6, iclass 33, count 2 2006.169.07:49:38.27#ibcon#read 6, iclass 33, count 2 2006.169.07:49:38.27#ibcon#end of sib2, iclass 33, count 2 2006.169.07:49:38.27#ibcon#*mode == 0, iclass 33, count 2 2006.169.07:49:38.27#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.169.07:49:38.27#ibcon#[27=AT03-04\r\n] 2006.169.07:49:38.27#ibcon#*before write, iclass 33, count 2 2006.169.07:49:38.27#ibcon#enter sib2, iclass 33, count 2 2006.169.07:49:38.27#ibcon#flushed, iclass 33, count 2 2006.169.07:49:38.27#ibcon#about to write, iclass 33, count 2 2006.169.07:49:38.27#ibcon#wrote, iclass 33, count 2 2006.169.07:49:38.27#ibcon#about to read 3, iclass 33, count 2 2006.169.07:49:38.30#ibcon#read 3, iclass 33, count 2 2006.169.07:49:38.30#ibcon#about to read 4, iclass 33, count 2 2006.169.07:49:38.30#ibcon#read 4, iclass 33, count 2 2006.169.07:49:38.30#ibcon#about to read 5, iclass 33, count 2 2006.169.07:49:38.30#ibcon#read 5, iclass 33, count 2 2006.169.07:49:38.30#ibcon#about to read 6, iclass 33, count 2 2006.169.07:49:38.30#ibcon#read 6, iclass 33, count 2 2006.169.07:49:38.30#ibcon#end of sib2, iclass 33, count 2 2006.169.07:49:38.30#ibcon#*after write, iclass 33, count 2 2006.169.07:49:38.30#ibcon#*before return 0, iclass 33, count 2 2006.169.07:49:38.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.169.07:49:38.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.169.07:49:38.30#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.169.07:49:38.30#ibcon#ireg 7 cls_cnt 0 2006.169.07:49:38.30#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.169.07:49:38.42#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.169.07:49:38.42#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.169.07:49:38.42#ibcon#enter wrdev, iclass 33, count 0 2006.169.07:49:38.42#ibcon#first serial, iclass 33, count 0 2006.169.07:49:38.42#ibcon#enter sib2, iclass 33, count 0 2006.169.07:49:38.42#ibcon#flushed, iclass 33, count 0 2006.169.07:49:38.42#ibcon#about to write, iclass 33, count 0 2006.169.07:49:38.42#ibcon#wrote, iclass 33, count 0 2006.169.07:49:38.42#ibcon#about to read 3, iclass 33, count 0 2006.169.07:49:38.44#ibcon#read 3, iclass 33, count 0 2006.169.07:49:38.44#ibcon#about to read 4, iclass 33, count 0 2006.169.07:49:38.44#ibcon#read 4, iclass 33, count 0 2006.169.07:49:38.44#ibcon#about to read 5, iclass 33, count 0 2006.169.07:49:38.44#ibcon#read 5, iclass 33, count 0 2006.169.07:49:38.44#ibcon#about to read 6, iclass 33, count 0 2006.169.07:49:38.44#ibcon#read 6, iclass 33, count 0 2006.169.07:49:38.44#ibcon#end of sib2, iclass 33, count 0 2006.169.07:49:38.44#ibcon#*mode == 0, iclass 33, count 0 2006.169.07:49:38.44#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.169.07:49:38.44#ibcon#[27=USB\r\n] 2006.169.07:49:38.44#ibcon#*before write, iclass 33, count 0 2006.169.07:49:38.44#ibcon#enter sib2, iclass 33, count 0 2006.169.07:49:38.44#ibcon#flushed, iclass 33, count 0 2006.169.07:49:38.44#ibcon#about to write, iclass 33, count 0 2006.169.07:49:38.44#ibcon#wrote, iclass 33, count 0 2006.169.07:49:38.44#ibcon#about to read 3, iclass 33, count 0 2006.169.07:49:38.47#ibcon#read 3, iclass 33, count 0 2006.169.07:49:38.47#ibcon#about to read 4, iclass 33, count 0 2006.169.07:49:38.47#ibcon#read 4, iclass 33, count 0 2006.169.07:49:38.47#ibcon#about to read 5, iclass 33, count 0 2006.169.07:49:38.47#ibcon#read 5, iclass 33, count 0 2006.169.07:49:38.47#ibcon#about to read 6, iclass 33, count 0 2006.169.07:49:38.47#ibcon#read 6, iclass 33, count 0 2006.169.07:49:38.47#ibcon#end of sib2, iclass 33, count 0 2006.169.07:49:38.47#ibcon#*after write, iclass 33, count 0 2006.169.07:49:38.47#ibcon#*before return 0, iclass 33, count 0 2006.169.07:49:38.47#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.169.07:49:38.47#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.169.07:49:38.47#ibcon#about to clear, iclass 33 cls_cnt 0 2006.169.07:49:38.47#ibcon#cleared, iclass 33 cls_cnt 0 2006.169.07:49:38.47$vc4f8/vblo=4,712.99 2006.169.07:49:38.47#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.169.07:49:38.47#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.169.07:49:38.47#ibcon#ireg 17 cls_cnt 0 2006.169.07:49:38.47#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.169.07:49:38.47#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.169.07:49:38.47#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.169.07:49:38.47#ibcon#enter wrdev, iclass 35, count 0 2006.169.07:49:38.47#ibcon#first serial, iclass 35, count 0 2006.169.07:49:38.47#ibcon#enter sib2, iclass 35, count 0 2006.169.07:49:38.47#ibcon#flushed, iclass 35, count 0 2006.169.07:49:38.47#ibcon#about to write, iclass 35, count 0 2006.169.07:49:38.47#ibcon#wrote, iclass 35, count 0 2006.169.07:49:38.47#ibcon#about to read 3, iclass 35, count 0 2006.169.07:49:38.49#ibcon#read 3, iclass 35, count 0 2006.169.07:49:38.49#ibcon#about to read 4, iclass 35, count 0 2006.169.07:49:38.49#ibcon#read 4, iclass 35, count 0 2006.169.07:49:38.49#ibcon#about to read 5, iclass 35, count 0 2006.169.07:49:38.49#ibcon#read 5, iclass 35, count 0 2006.169.07:49:38.49#ibcon#about to read 6, iclass 35, count 0 2006.169.07:49:38.49#ibcon#read 6, iclass 35, count 0 2006.169.07:49:38.49#ibcon#end of sib2, iclass 35, count 0 2006.169.07:49:38.49#ibcon#*mode == 0, iclass 35, count 0 2006.169.07:49:38.49#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.169.07:49:38.49#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.07:49:38.49#ibcon#*before write, iclass 35, count 0 2006.169.07:49:38.49#ibcon#enter sib2, iclass 35, count 0 2006.169.07:49:38.49#ibcon#flushed, iclass 35, count 0 2006.169.07:49:38.49#ibcon#about to write, iclass 35, count 0 2006.169.07:49:38.49#ibcon#wrote, iclass 35, count 0 2006.169.07:49:38.49#ibcon#about to read 3, iclass 35, count 0 2006.169.07:49:38.53#ibcon#read 3, iclass 35, count 0 2006.169.07:49:38.53#ibcon#about to read 4, iclass 35, count 0 2006.169.07:49:38.53#ibcon#read 4, iclass 35, count 0 2006.169.07:49:38.53#ibcon#about to read 5, iclass 35, count 0 2006.169.07:49:38.53#ibcon#read 5, iclass 35, count 0 2006.169.07:49:38.53#ibcon#about to read 6, iclass 35, count 0 2006.169.07:49:38.53#ibcon#read 6, iclass 35, count 0 2006.169.07:49:38.53#ibcon#end of sib2, iclass 35, count 0 2006.169.07:49:38.53#ibcon#*after write, iclass 35, count 0 2006.169.07:49:38.53#ibcon#*before return 0, iclass 35, count 0 2006.169.07:49:38.53#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.169.07:49:38.53#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.169.07:49:38.53#ibcon#about to clear, iclass 35 cls_cnt 0 2006.169.07:49:38.53#ibcon#cleared, iclass 35 cls_cnt 0 2006.169.07:49:38.53$vc4f8/vb=4,4 2006.169.07:49:38.53#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.169.07:49:38.53#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.169.07:49:38.53#ibcon#ireg 11 cls_cnt 2 2006.169.07:49:38.53#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.169.07:49:38.59#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.169.07:49:38.59#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.169.07:49:38.59#ibcon#enter wrdev, iclass 37, count 2 2006.169.07:49:38.59#ibcon#first serial, iclass 37, count 2 2006.169.07:49:38.59#ibcon#enter sib2, iclass 37, count 2 2006.169.07:49:38.59#ibcon#flushed, iclass 37, count 2 2006.169.07:49:38.59#ibcon#about to write, iclass 37, count 2 2006.169.07:49:38.59#ibcon#wrote, iclass 37, count 2 2006.169.07:49:38.59#ibcon#about to read 3, iclass 37, count 2 2006.169.07:49:38.61#ibcon#read 3, iclass 37, count 2 2006.169.07:49:38.61#ibcon#about to read 4, iclass 37, count 2 2006.169.07:49:38.61#ibcon#read 4, iclass 37, count 2 2006.169.07:49:38.61#ibcon#about to read 5, iclass 37, count 2 2006.169.07:49:38.61#ibcon#read 5, iclass 37, count 2 2006.169.07:49:38.61#ibcon#about to read 6, iclass 37, count 2 2006.169.07:49:38.61#ibcon#read 6, iclass 37, count 2 2006.169.07:49:38.61#ibcon#end of sib2, iclass 37, count 2 2006.169.07:49:38.61#ibcon#*mode == 0, iclass 37, count 2 2006.169.07:49:38.61#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.169.07:49:38.61#ibcon#[27=AT04-04\r\n] 2006.169.07:49:38.61#ibcon#*before write, iclass 37, count 2 2006.169.07:49:38.61#ibcon#enter sib2, iclass 37, count 2 2006.169.07:49:38.61#ibcon#flushed, iclass 37, count 2 2006.169.07:49:38.61#ibcon#about to write, iclass 37, count 2 2006.169.07:49:38.61#ibcon#wrote, iclass 37, count 2 2006.169.07:49:38.61#ibcon#about to read 3, iclass 37, count 2 2006.169.07:49:38.64#ibcon#read 3, iclass 37, count 2 2006.169.07:49:38.64#ibcon#about to read 4, iclass 37, count 2 2006.169.07:49:38.64#ibcon#read 4, iclass 37, count 2 2006.169.07:49:38.64#ibcon#about to read 5, iclass 37, count 2 2006.169.07:49:38.64#ibcon#read 5, iclass 37, count 2 2006.169.07:49:38.64#ibcon#about to read 6, iclass 37, count 2 2006.169.07:49:38.64#ibcon#read 6, iclass 37, count 2 2006.169.07:49:38.64#ibcon#end of sib2, iclass 37, count 2 2006.169.07:49:38.64#ibcon#*after write, iclass 37, count 2 2006.169.07:49:38.64#ibcon#*before return 0, iclass 37, count 2 2006.169.07:49:38.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.169.07:49:38.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.169.07:49:38.64#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.169.07:49:38.64#ibcon#ireg 7 cls_cnt 0 2006.169.07:49:38.64#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.169.07:49:38.76#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.169.07:49:38.76#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.169.07:49:38.76#ibcon#enter wrdev, iclass 37, count 0 2006.169.07:49:38.76#ibcon#first serial, iclass 37, count 0 2006.169.07:49:38.76#ibcon#enter sib2, iclass 37, count 0 2006.169.07:49:38.76#ibcon#flushed, iclass 37, count 0 2006.169.07:49:38.76#ibcon#about to write, iclass 37, count 0 2006.169.07:49:38.76#ibcon#wrote, iclass 37, count 0 2006.169.07:49:38.76#ibcon#about to read 3, iclass 37, count 0 2006.169.07:49:38.78#ibcon#read 3, iclass 37, count 0 2006.169.07:49:38.78#ibcon#about to read 4, iclass 37, count 0 2006.169.07:49:38.78#ibcon#read 4, iclass 37, count 0 2006.169.07:49:38.78#ibcon#about to read 5, iclass 37, count 0 2006.169.07:49:38.78#ibcon#read 5, iclass 37, count 0 2006.169.07:49:38.78#ibcon#about to read 6, iclass 37, count 0 2006.169.07:49:38.78#ibcon#read 6, iclass 37, count 0 2006.169.07:49:38.78#ibcon#end of sib2, iclass 37, count 0 2006.169.07:49:38.78#ibcon#*mode == 0, iclass 37, count 0 2006.169.07:49:38.78#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.169.07:49:38.78#ibcon#[27=USB\r\n] 2006.169.07:49:38.78#ibcon#*before write, iclass 37, count 0 2006.169.07:49:38.78#ibcon#enter sib2, iclass 37, count 0 2006.169.07:49:38.78#ibcon#flushed, iclass 37, count 0 2006.169.07:49:38.78#ibcon#about to write, iclass 37, count 0 2006.169.07:49:38.78#ibcon#wrote, iclass 37, count 0 2006.169.07:49:38.78#ibcon#about to read 3, iclass 37, count 0 2006.169.07:49:38.81#ibcon#read 3, iclass 37, count 0 2006.169.07:49:38.81#ibcon#about to read 4, iclass 37, count 0 2006.169.07:49:38.81#ibcon#read 4, iclass 37, count 0 2006.169.07:49:38.81#ibcon#about to read 5, iclass 37, count 0 2006.169.07:49:38.81#ibcon#read 5, iclass 37, count 0 2006.169.07:49:38.81#ibcon#about to read 6, iclass 37, count 0 2006.169.07:49:38.81#ibcon#read 6, iclass 37, count 0 2006.169.07:49:38.81#ibcon#end of sib2, iclass 37, count 0 2006.169.07:49:38.81#ibcon#*after write, iclass 37, count 0 2006.169.07:49:38.81#ibcon#*before return 0, iclass 37, count 0 2006.169.07:49:38.81#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.169.07:49:38.81#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.169.07:49:38.81#ibcon#about to clear, iclass 37 cls_cnt 0 2006.169.07:49:38.81#ibcon#cleared, iclass 37 cls_cnt 0 2006.169.07:49:38.81$vc4f8/vblo=5,744.99 2006.169.07:49:38.81#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.169.07:49:38.81#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.169.07:49:38.81#ibcon#ireg 17 cls_cnt 0 2006.169.07:49:38.81#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.169.07:49:38.81#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.169.07:49:38.81#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.169.07:49:38.81#ibcon#enter wrdev, iclass 39, count 0 2006.169.07:49:38.81#ibcon#first serial, iclass 39, count 0 2006.169.07:49:38.81#ibcon#enter sib2, iclass 39, count 0 2006.169.07:49:38.81#ibcon#flushed, iclass 39, count 0 2006.169.07:49:38.81#ibcon#about to write, iclass 39, count 0 2006.169.07:49:38.81#ibcon#wrote, iclass 39, count 0 2006.169.07:49:38.81#ibcon#about to read 3, iclass 39, count 0 2006.169.07:49:38.83#ibcon#read 3, iclass 39, count 0 2006.169.07:49:38.83#ibcon#about to read 4, iclass 39, count 0 2006.169.07:49:38.83#ibcon#read 4, iclass 39, count 0 2006.169.07:49:38.83#ibcon#about to read 5, iclass 39, count 0 2006.169.07:49:38.83#ibcon#read 5, iclass 39, count 0 2006.169.07:49:38.83#ibcon#about to read 6, iclass 39, count 0 2006.169.07:49:38.83#ibcon#read 6, iclass 39, count 0 2006.169.07:49:38.83#ibcon#end of sib2, iclass 39, count 0 2006.169.07:49:38.83#ibcon#*mode == 0, iclass 39, count 0 2006.169.07:49:38.83#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.169.07:49:38.83#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.07:49:38.83#ibcon#*before write, iclass 39, count 0 2006.169.07:49:38.83#ibcon#enter sib2, iclass 39, count 0 2006.169.07:49:38.83#ibcon#flushed, iclass 39, count 0 2006.169.07:49:38.83#ibcon#about to write, iclass 39, count 0 2006.169.07:49:38.83#ibcon#wrote, iclass 39, count 0 2006.169.07:49:38.83#ibcon#about to read 3, iclass 39, count 0 2006.169.07:49:38.87#ibcon#read 3, iclass 39, count 0 2006.169.07:49:38.87#ibcon#about to read 4, iclass 39, count 0 2006.169.07:49:38.87#ibcon#read 4, iclass 39, count 0 2006.169.07:49:38.87#ibcon#about to read 5, iclass 39, count 0 2006.169.07:49:38.87#ibcon#read 5, iclass 39, count 0 2006.169.07:49:38.87#ibcon#about to read 6, iclass 39, count 0 2006.169.07:49:38.87#ibcon#read 6, iclass 39, count 0 2006.169.07:49:38.87#ibcon#end of sib2, iclass 39, count 0 2006.169.07:49:38.87#ibcon#*after write, iclass 39, count 0 2006.169.07:49:38.87#ibcon#*before return 0, iclass 39, count 0 2006.169.07:49:38.87#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.169.07:49:38.87#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.169.07:49:38.87#ibcon#about to clear, iclass 39 cls_cnt 0 2006.169.07:49:38.87#ibcon#cleared, iclass 39 cls_cnt 0 2006.169.07:49:38.87$vc4f8/vb=5,4 2006.169.07:49:38.87#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.169.07:49:38.87#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.169.07:49:38.87#ibcon#ireg 11 cls_cnt 2 2006.169.07:49:38.87#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.169.07:49:38.93#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.169.07:49:38.93#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.169.07:49:38.93#ibcon#enter wrdev, iclass 3, count 2 2006.169.07:49:38.93#ibcon#first serial, iclass 3, count 2 2006.169.07:49:38.93#ibcon#enter sib2, iclass 3, count 2 2006.169.07:49:38.93#ibcon#flushed, iclass 3, count 2 2006.169.07:49:38.93#ibcon#about to write, iclass 3, count 2 2006.169.07:49:38.93#ibcon#wrote, iclass 3, count 2 2006.169.07:49:38.93#ibcon#about to read 3, iclass 3, count 2 2006.169.07:49:38.95#ibcon#read 3, iclass 3, count 2 2006.169.07:49:38.95#ibcon#about to read 4, iclass 3, count 2 2006.169.07:49:38.95#ibcon#read 4, iclass 3, count 2 2006.169.07:49:38.95#ibcon#about to read 5, iclass 3, count 2 2006.169.07:49:38.95#ibcon#read 5, iclass 3, count 2 2006.169.07:49:38.95#ibcon#about to read 6, iclass 3, count 2 2006.169.07:49:38.95#ibcon#read 6, iclass 3, count 2 2006.169.07:49:38.95#ibcon#end of sib2, iclass 3, count 2 2006.169.07:49:38.95#ibcon#*mode == 0, iclass 3, count 2 2006.169.07:49:38.95#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.169.07:49:38.95#ibcon#[27=AT05-04\r\n] 2006.169.07:49:38.95#ibcon#*before write, iclass 3, count 2 2006.169.07:49:38.95#ibcon#enter sib2, iclass 3, count 2 2006.169.07:49:38.95#ibcon#flushed, iclass 3, count 2 2006.169.07:49:38.95#ibcon#about to write, iclass 3, count 2 2006.169.07:49:38.95#ibcon#wrote, iclass 3, count 2 2006.169.07:49:38.95#ibcon#about to read 3, iclass 3, count 2 2006.169.07:49:38.98#ibcon#read 3, iclass 3, count 2 2006.169.07:49:38.98#ibcon#about to read 4, iclass 3, count 2 2006.169.07:49:38.98#ibcon#read 4, iclass 3, count 2 2006.169.07:49:38.98#ibcon#about to read 5, iclass 3, count 2 2006.169.07:49:38.98#ibcon#read 5, iclass 3, count 2 2006.169.07:49:38.98#ibcon#about to read 6, iclass 3, count 2 2006.169.07:49:38.98#ibcon#read 6, iclass 3, count 2 2006.169.07:49:38.98#ibcon#end of sib2, iclass 3, count 2 2006.169.07:49:38.98#ibcon#*after write, iclass 3, count 2 2006.169.07:49:38.98#ibcon#*before return 0, iclass 3, count 2 2006.169.07:49:38.98#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.169.07:49:38.98#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.169.07:49:38.98#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.169.07:49:38.98#ibcon#ireg 7 cls_cnt 0 2006.169.07:49:38.98#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.169.07:49:39.10#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.169.07:49:39.10#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.169.07:49:39.10#ibcon#enter wrdev, iclass 3, count 0 2006.169.07:49:39.10#ibcon#first serial, iclass 3, count 0 2006.169.07:49:39.10#ibcon#enter sib2, iclass 3, count 0 2006.169.07:49:39.10#ibcon#flushed, iclass 3, count 0 2006.169.07:49:39.10#ibcon#about to write, iclass 3, count 0 2006.169.07:49:39.10#ibcon#wrote, iclass 3, count 0 2006.169.07:49:39.10#ibcon#about to read 3, iclass 3, count 0 2006.169.07:49:39.12#ibcon#read 3, iclass 3, count 0 2006.169.07:49:39.12#ibcon#about to read 4, iclass 3, count 0 2006.169.07:49:39.12#ibcon#read 4, iclass 3, count 0 2006.169.07:49:39.12#ibcon#about to read 5, iclass 3, count 0 2006.169.07:49:39.12#ibcon#read 5, iclass 3, count 0 2006.169.07:49:39.12#ibcon#about to read 6, iclass 3, count 0 2006.169.07:49:39.12#ibcon#read 6, iclass 3, count 0 2006.169.07:49:39.12#ibcon#end of sib2, iclass 3, count 0 2006.169.07:49:39.12#ibcon#*mode == 0, iclass 3, count 0 2006.169.07:49:39.12#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.169.07:49:39.12#ibcon#[27=USB\r\n] 2006.169.07:49:39.12#ibcon#*before write, iclass 3, count 0 2006.169.07:49:39.12#ibcon#enter sib2, iclass 3, count 0 2006.169.07:49:39.12#ibcon#flushed, iclass 3, count 0 2006.169.07:49:39.12#ibcon#about to write, iclass 3, count 0 2006.169.07:49:39.12#ibcon#wrote, iclass 3, count 0 2006.169.07:49:39.12#ibcon#about to read 3, iclass 3, count 0 2006.169.07:49:39.15#ibcon#read 3, iclass 3, count 0 2006.169.07:49:39.15#ibcon#about to read 4, iclass 3, count 0 2006.169.07:49:39.15#ibcon#read 4, iclass 3, count 0 2006.169.07:49:39.15#ibcon#about to read 5, iclass 3, count 0 2006.169.07:49:39.15#ibcon#read 5, iclass 3, count 0 2006.169.07:49:39.15#ibcon#about to read 6, iclass 3, count 0 2006.169.07:49:39.15#ibcon#read 6, iclass 3, count 0 2006.169.07:49:39.15#ibcon#end of sib2, iclass 3, count 0 2006.169.07:49:39.15#ibcon#*after write, iclass 3, count 0 2006.169.07:49:39.15#ibcon#*before return 0, iclass 3, count 0 2006.169.07:49:39.15#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.169.07:49:39.15#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.169.07:49:39.15#ibcon#about to clear, iclass 3 cls_cnt 0 2006.169.07:49:39.15#ibcon#cleared, iclass 3 cls_cnt 0 2006.169.07:49:39.15$vc4f8/vblo=6,752.99 2006.169.07:49:39.15#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.169.07:49:39.15#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.169.07:49:39.15#ibcon#ireg 17 cls_cnt 0 2006.169.07:49:39.15#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:49:39.15#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:49:39.15#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:49:39.15#ibcon#enter wrdev, iclass 5, count 0 2006.169.07:49:39.15#ibcon#first serial, iclass 5, count 0 2006.169.07:49:39.15#ibcon#enter sib2, iclass 5, count 0 2006.169.07:49:39.15#ibcon#flushed, iclass 5, count 0 2006.169.07:49:39.15#ibcon#about to write, iclass 5, count 0 2006.169.07:49:39.15#ibcon#wrote, iclass 5, count 0 2006.169.07:49:39.15#ibcon#about to read 3, iclass 5, count 0 2006.169.07:49:39.17#ibcon#read 3, iclass 5, count 0 2006.169.07:49:39.17#ibcon#about to read 4, iclass 5, count 0 2006.169.07:49:39.17#ibcon#read 4, iclass 5, count 0 2006.169.07:49:39.17#ibcon#about to read 5, iclass 5, count 0 2006.169.07:49:39.17#ibcon#read 5, iclass 5, count 0 2006.169.07:49:39.17#ibcon#about to read 6, iclass 5, count 0 2006.169.07:49:39.17#ibcon#read 6, iclass 5, count 0 2006.169.07:49:39.17#ibcon#end of sib2, iclass 5, count 0 2006.169.07:49:39.17#ibcon#*mode == 0, iclass 5, count 0 2006.169.07:49:39.17#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.169.07:49:39.17#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.07:49:39.17#ibcon#*before write, iclass 5, count 0 2006.169.07:49:39.17#ibcon#enter sib2, iclass 5, count 0 2006.169.07:49:39.17#ibcon#flushed, iclass 5, count 0 2006.169.07:49:39.17#ibcon#about to write, iclass 5, count 0 2006.169.07:49:39.17#ibcon#wrote, iclass 5, count 0 2006.169.07:49:39.17#ibcon#about to read 3, iclass 5, count 0 2006.169.07:49:39.21#ibcon#read 3, iclass 5, count 0 2006.169.07:49:39.21#ibcon#about to read 4, iclass 5, count 0 2006.169.07:49:39.21#ibcon#read 4, iclass 5, count 0 2006.169.07:49:39.21#ibcon#about to read 5, iclass 5, count 0 2006.169.07:49:39.21#ibcon#read 5, iclass 5, count 0 2006.169.07:49:39.21#ibcon#about to read 6, iclass 5, count 0 2006.169.07:49:39.21#ibcon#read 6, iclass 5, count 0 2006.169.07:49:39.21#ibcon#end of sib2, iclass 5, count 0 2006.169.07:49:39.21#ibcon#*after write, iclass 5, count 0 2006.169.07:49:39.21#ibcon#*before return 0, iclass 5, count 0 2006.169.07:49:39.21#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:49:39.21#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.169.07:49:39.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.169.07:49:39.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.169.07:49:39.21$vc4f8/vb=6,4 2006.169.07:49:39.21#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.169.07:49:39.21#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.169.07:49:39.21#ibcon#ireg 11 cls_cnt 2 2006.169.07:49:39.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:49:39.27#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:49:39.27#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:49:39.27#ibcon#enter wrdev, iclass 7, count 2 2006.169.07:49:39.27#ibcon#first serial, iclass 7, count 2 2006.169.07:49:39.27#ibcon#enter sib2, iclass 7, count 2 2006.169.07:49:39.27#ibcon#flushed, iclass 7, count 2 2006.169.07:49:39.27#ibcon#about to write, iclass 7, count 2 2006.169.07:49:39.27#ibcon#wrote, iclass 7, count 2 2006.169.07:49:39.27#ibcon#about to read 3, iclass 7, count 2 2006.169.07:49:39.29#ibcon#read 3, iclass 7, count 2 2006.169.07:49:39.29#ibcon#about to read 4, iclass 7, count 2 2006.169.07:49:39.29#ibcon#read 4, iclass 7, count 2 2006.169.07:49:39.29#ibcon#about to read 5, iclass 7, count 2 2006.169.07:49:39.29#ibcon#read 5, iclass 7, count 2 2006.169.07:49:39.29#ibcon#about to read 6, iclass 7, count 2 2006.169.07:49:39.29#ibcon#read 6, iclass 7, count 2 2006.169.07:49:39.29#ibcon#end of sib2, iclass 7, count 2 2006.169.07:49:39.29#ibcon#*mode == 0, iclass 7, count 2 2006.169.07:49:39.29#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.169.07:49:39.29#ibcon#[27=AT06-04\r\n] 2006.169.07:49:39.29#ibcon#*before write, iclass 7, count 2 2006.169.07:49:39.29#ibcon#enter sib2, iclass 7, count 2 2006.169.07:49:39.29#ibcon#flushed, iclass 7, count 2 2006.169.07:49:39.29#ibcon#about to write, iclass 7, count 2 2006.169.07:49:39.29#ibcon#wrote, iclass 7, count 2 2006.169.07:49:39.29#ibcon#about to read 3, iclass 7, count 2 2006.169.07:49:39.32#ibcon#read 3, iclass 7, count 2 2006.169.07:49:39.32#ibcon#about to read 4, iclass 7, count 2 2006.169.07:49:39.32#ibcon#read 4, iclass 7, count 2 2006.169.07:49:39.32#ibcon#about to read 5, iclass 7, count 2 2006.169.07:49:39.32#ibcon#read 5, iclass 7, count 2 2006.169.07:49:39.32#ibcon#about to read 6, iclass 7, count 2 2006.169.07:49:39.32#ibcon#read 6, iclass 7, count 2 2006.169.07:49:39.32#ibcon#end of sib2, iclass 7, count 2 2006.169.07:49:39.32#ibcon#*after write, iclass 7, count 2 2006.169.07:49:39.32#ibcon#*before return 0, iclass 7, count 2 2006.169.07:49:39.32#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:49:39.32#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.169.07:49:39.32#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.169.07:49:39.32#ibcon#ireg 7 cls_cnt 0 2006.169.07:49:39.32#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:49:39.44#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:49:39.44#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:49:39.44#ibcon#enter wrdev, iclass 7, count 0 2006.169.07:49:39.44#ibcon#first serial, iclass 7, count 0 2006.169.07:49:39.44#ibcon#enter sib2, iclass 7, count 0 2006.169.07:49:39.44#ibcon#flushed, iclass 7, count 0 2006.169.07:49:39.44#ibcon#about to write, iclass 7, count 0 2006.169.07:49:39.44#ibcon#wrote, iclass 7, count 0 2006.169.07:49:39.44#ibcon#about to read 3, iclass 7, count 0 2006.169.07:49:39.46#ibcon#read 3, iclass 7, count 0 2006.169.07:49:39.46#ibcon#about to read 4, iclass 7, count 0 2006.169.07:49:39.46#ibcon#read 4, iclass 7, count 0 2006.169.07:49:39.46#ibcon#about to read 5, iclass 7, count 0 2006.169.07:49:39.46#ibcon#read 5, iclass 7, count 0 2006.169.07:49:39.46#ibcon#about to read 6, iclass 7, count 0 2006.169.07:49:39.46#ibcon#read 6, iclass 7, count 0 2006.169.07:49:39.46#ibcon#end of sib2, iclass 7, count 0 2006.169.07:49:39.46#ibcon#*mode == 0, iclass 7, count 0 2006.169.07:49:39.46#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.169.07:49:39.46#ibcon#[27=USB\r\n] 2006.169.07:49:39.46#ibcon#*before write, iclass 7, count 0 2006.169.07:49:39.46#ibcon#enter sib2, iclass 7, count 0 2006.169.07:49:39.46#ibcon#flushed, iclass 7, count 0 2006.169.07:49:39.46#ibcon#about to write, iclass 7, count 0 2006.169.07:49:39.46#ibcon#wrote, iclass 7, count 0 2006.169.07:49:39.46#ibcon#about to read 3, iclass 7, count 0 2006.169.07:49:39.49#ibcon#read 3, iclass 7, count 0 2006.169.07:49:39.49#ibcon#about to read 4, iclass 7, count 0 2006.169.07:49:39.49#ibcon#read 4, iclass 7, count 0 2006.169.07:49:39.49#ibcon#about to read 5, iclass 7, count 0 2006.169.07:49:39.49#ibcon#read 5, iclass 7, count 0 2006.169.07:49:39.49#ibcon#about to read 6, iclass 7, count 0 2006.169.07:49:39.49#ibcon#read 6, iclass 7, count 0 2006.169.07:49:39.49#ibcon#end of sib2, iclass 7, count 0 2006.169.07:49:39.49#ibcon#*after write, iclass 7, count 0 2006.169.07:49:39.49#ibcon#*before return 0, iclass 7, count 0 2006.169.07:49:39.49#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:49:39.49#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.169.07:49:39.49#ibcon#about to clear, iclass 7 cls_cnt 0 2006.169.07:49:39.49#ibcon#cleared, iclass 7 cls_cnt 0 2006.169.07:49:39.49$vc4f8/vabw=wide 2006.169.07:49:39.49#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.169.07:49:39.49#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.169.07:49:39.49#ibcon#ireg 8 cls_cnt 0 2006.169.07:49:39.49#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.169.07:49:39.49#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.169.07:49:39.49#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.169.07:49:39.49#ibcon#enter wrdev, iclass 11, count 0 2006.169.07:49:39.49#ibcon#first serial, iclass 11, count 0 2006.169.07:49:39.49#ibcon#enter sib2, iclass 11, count 0 2006.169.07:49:39.49#ibcon#flushed, iclass 11, count 0 2006.169.07:49:39.49#ibcon#about to write, iclass 11, count 0 2006.169.07:49:39.49#ibcon#wrote, iclass 11, count 0 2006.169.07:49:39.49#ibcon#about to read 3, iclass 11, count 0 2006.169.07:49:39.51#ibcon#read 3, iclass 11, count 0 2006.169.07:49:39.51#ibcon#about to read 4, iclass 11, count 0 2006.169.07:49:39.51#ibcon#read 4, iclass 11, count 0 2006.169.07:49:39.51#ibcon#about to read 5, iclass 11, count 0 2006.169.07:49:39.51#ibcon#read 5, iclass 11, count 0 2006.169.07:49:39.51#ibcon#about to read 6, iclass 11, count 0 2006.169.07:49:39.51#ibcon#read 6, iclass 11, count 0 2006.169.07:49:39.51#ibcon#end of sib2, iclass 11, count 0 2006.169.07:49:39.51#ibcon#*mode == 0, iclass 11, count 0 2006.169.07:49:39.51#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.169.07:49:39.51#ibcon#[25=BW32\r\n] 2006.169.07:49:39.51#ibcon#*before write, iclass 11, count 0 2006.169.07:49:39.51#ibcon#enter sib2, iclass 11, count 0 2006.169.07:49:39.51#ibcon#flushed, iclass 11, count 0 2006.169.07:49:39.51#ibcon#about to write, iclass 11, count 0 2006.169.07:49:39.51#ibcon#wrote, iclass 11, count 0 2006.169.07:49:39.51#ibcon#about to read 3, iclass 11, count 0 2006.169.07:49:39.54#ibcon#read 3, iclass 11, count 0 2006.169.07:49:39.54#ibcon#about to read 4, iclass 11, count 0 2006.169.07:49:39.54#ibcon#read 4, iclass 11, count 0 2006.169.07:49:39.54#ibcon#about to read 5, iclass 11, count 0 2006.169.07:49:39.54#ibcon#read 5, iclass 11, count 0 2006.169.07:49:39.54#ibcon#about to read 6, iclass 11, count 0 2006.169.07:49:39.54#ibcon#read 6, iclass 11, count 0 2006.169.07:49:39.54#ibcon#end of sib2, iclass 11, count 0 2006.169.07:49:39.54#ibcon#*after write, iclass 11, count 0 2006.169.07:49:39.54#ibcon#*before return 0, iclass 11, count 0 2006.169.07:49:39.54#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.169.07:49:39.54#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.169.07:49:39.54#ibcon#about to clear, iclass 11 cls_cnt 0 2006.169.07:49:39.54#ibcon#cleared, iclass 11 cls_cnt 0 2006.169.07:49:39.54$vc4f8/vbbw=wide 2006.169.07:49:39.54#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.169.07:49:39.54#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.169.07:49:39.54#ibcon#ireg 8 cls_cnt 0 2006.169.07:49:39.54#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:49:39.61#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:49:39.61#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:49:39.61#ibcon#enter wrdev, iclass 13, count 0 2006.169.07:49:39.61#ibcon#first serial, iclass 13, count 0 2006.169.07:49:39.61#ibcon#enter sib2, iclass 13, count 0 2006.169.07:49:39.61#ibcon#flushed, iclass 13, count 0 2006.169.07:49:39.61#ibcon#about to write, iclass 13, count 0 2006.169.07:49:39.61#ibcon#wrote, iclass 13, count 0 2006.169.07:49:39.61#ibcon#about to read 3, iclass 13, count 0 2006.169.07:49:39.63#ibcon#read 3, iclass 13, count 0 2006.169.07:49:39.63#ibcon#about to read 4, iclass 13, count 0 2006.169.07:49:39.63#ibcon#read 4, iclass 13, count 0 2006.169.07:49:39.63#ibcon#about to read 5, iclass 13, count 0 2006.169.07:49:39.63#ibcon#read 5, iclass 13, count 0 2006.169.07:49:39.63#ibcon#about to read 6, iclass 13, count 0 2006.169.07:49:39.63#ibcon#read 6, iclass 13, count 0 2006.169.07:49:39.63#ibcon#end of sib2, iclass 13, count 0 2006.169.07:49:39.63#ibcon#*mode == 0, iclass 13, count 0 2006.169.07:49:39.63#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.07:49:39.63#ibcon#[27=BW32\r\n] 2006.169.07:49:39.63#ibcon#*before write, iclass 13, count 0 2006.169.07:49:39.63#ibcon#enter sib2, iclass 13, count 0 2006.169.07:49:39.63#ibcon#flushed, iclass 13, count 0 2006.169.07:49:39.63#ibcon#about to write, iclass 13, count 0 2006.169.07:49:39.63#ibcon#wrote, iclass 13, count 0 2006.169.07:49:39.63#ibcon#about to read 3, iclass 13, count 0 2006.169.07:49:39.66#ibcon#read 3, iclass 13, count 0 2006.169.07:49:39.66#ibcon#about to read 4, iclass 13, count 0 2006.169.07:49:39.66#ibcon#read 4, iclass 13, count 0 2006.169.07:49:39.66#ibcon#about to read 5, iclass 13, count 0 2006.169.07:49:39.66#ibcon#read 5, iclass 13, count 0 2006.169.07:49:39.66#ibcon#about to read 6, iclass 13, count 0 2006.169.07:49:39.66#ibcon#read 6, iclass 13, count 0 2006.169.07:49:39.66#ibcon#end of sib2, iclass 13, count 0 2006.169.07:49:39.66#ibcon#*after write, iclass 13, count 0 2006.169.07:49:39.66#ibcon#*before return 0, iclass 13, count 0 2006.169.07:49:39.66#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:49:39.66#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:49:39.66#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.07:49:39.66#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.07:49:39.66$4f8m12a/ifd4f 2006.169.07:49:39.66$ifd4f/lo= 2006.169.07:49:39.66$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.07:49:39.66$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.07:49:39.66$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.07:49:39.66$ifd4f/patch= 2006.169.07:49:39.66$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.07:49:39.66$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.07:49:39.66$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.07:49:39.66$4f8m12a/"form=m,16.000,1:2 2006.169.07:49:39.66$4f8m12a/"tpicd 2006.169.07:49:39.66$4f8m12a/echo=off 2006.169.07:49:39.66$4f8m12a/xlog=off 2006.169.07:49:39.66:!2006.169.07:50:30 2006.169.07:50:03.14#trakl#Source acquired 2006.169.07:50:05.14#flagr#flagr/antenna,acquired 2006.169.07:50:30.00:preob 2006.169.07:50:30.14/onsource/TRACKING 2006.169.07:50:30.14:!2006.169.07:50:40 2006.169.07:50:40.00:data_valid=on 2006.169.07:50:40.00:midob 2006.169.07:50:41.14/onsource/TRACKING 2006.169.07:50:41.14/wx/18.11,1003.8,100 2006.169.07:50:41.32/cable/+6.5293E-03 2006.169.07:50:42.41/va/01,08,usb,yes,50,52 2006.169.07:50:42.41/va/02,07,usb,yes,51,53 2006.169.07:50:42.41/va/03,06,usb,yes,53,54 2006.169.07:50:42.41/va/04,07,usb,yes,52,56 2006.169.07:50:42.41/va/05,07,usb,yes,57,61 2006.169.07:50:42.41/va/06,06,usb,yes,57,56 2006.169.07:50:42.41/va/07,06,usb,yes,57,57 2006.169.07:50:42.41/va/08,07,usb,yes,54,54 2006.169.07:50:42.64/valo/01,532.99,yes,locked 2006.169.07:50:42.64/valo/02,572.99,yes,locked 2006.169.07:50:42.64/valo/03,672.99,yes,locked 2006.169.07:50:42.64/valo/04,832.99,yes,locked 2006.169.07:50:42.64/valo/05,652.99,yes,locked 2006.169.07:50:42.64/valo/06,772.99,yes,locked 2006.169.07:50:42.64/valo/07,832.99,yes,locked 2006.169.07:50:42.64/valo/08,852.99,yes,locked 2006.169.07:50:43.73/vb/01,04,usb,yes,30,29 2006.169.07:50:43.73/vb/02,04,usb,yes,32,34 2006.169.07:50:43.73/vb/03,04,usb,yes,29,32 2006.169.07:50:43.73/vb/04,04,usb,yes,30,30 2006.169.07:50:43.73/vb/05,04,usb,yes,28,32 2006.169.07:50:43.73/vb/06,04,usb,yes,29,32 2006.169.07:50:43.73/vb/07,04,usb,yes,31,31 2006.169.07:50:43.73/vb/08,04,usb,yes,29,32 2006.169.07:50:43.96/vblo/01,632.99,yes,locked 2006.169.07:50:43.96/vblo/02,640.99,yes,locked 2006.169.07:50:43.96/vblo/03,656.99,yes,locked 2006.169.07:50:43.96/vblo/04,712.99,yes,locked 2006.169.07:50:43.96/vblo/05,744.99,yes,locked 2006.169.07:50:43.96/vblo/06,752.99,yes,locked 2006.169.07:50:43.96/vblo/07,734.99,yes,locked 2006.169.07:50:43.96/vblo/08,744.99,yes,locked 2006.169.07:50:44.11/vabw/8 2006.169.07:50:44.26/vbbw/8 2006.169.07:50:44.35/xfe/off,on,14.2 2006.169.07:50:44.72/ifatt/23,28,28,28 2006.169.07:50:45.07/fmout-gps/S +4.18E-07 2006.169.07:50:45.15:!2006.169.07:51:40 2006.169.07:51:40.01:data_valid=off 2006.169.07:51:40.02:postob 2006.169.07:51:40.12/cable/+6.5273E-03 2006.169.07:51:40.13/wx/18.11,1003.9,100 2006.169.07:51:41.07/fmout-gps/S +4.16E-07 2006.169.07:51:41.08:scan_name=169-0752,k06169,60 2006.169.07:51:41.08:source=1803+784,180045.68,782804.0,2000.0,cw 2006.169.07:51:41.14#flagr#flagr/antenna,new-source 2006.169.07:51:42.14:checkk5 2006.169.07:51:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.169.07:51:42.90/chk_autoobs//k5ts2/ autoobs is running! 2006.169.07:51:46.91/chk_autoobs//k5ts3?ERROR: timeout happened! 2006.169.07:51:47.29/chk_autoobs//k5ts4/ autoobs is running! 2006.169.07:51:47.66/chk_obsdata//k5ts1/T1690750??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.169.07:51:48.03/chk_obsdata//k5ts2/T1690750??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.169.07:51:55.09/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.07:51:55.47/chk_obsdata//k5ts4/T1690750??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.169.07:51:56.16/k5log//k5ts1_log_newline 2006.169.07:51:56.86/k5log//k5ts2_log_newline 2006.169.07:52:03.14#trakl#Source acquired 2006.169.07:52:03.95/k5log//k5ts3?ERROR: timeout happened! 2006.169.07:52:04.65/k5log//k5ts4_log_newline 2006.169.07:52:04.82/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.07:52:04.82:4f8m12a=1 2006.169.07:52:04.82$4f8m12a/echo=on 2006.169.07:52:04.82$4f8m12a/pcalon 2006.169.07:52:04.82$pcalon/"no phase cal control is implemented here 2006.169.07:52:04.82$4f8m12a/"tpicd=stop 2006.169.07:52:04.82$4f8m12a/vc4f8 2006.169.07:52:04.82$vc4f8/valo=1,532.99 2006.169.07:52:04.83#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.169.07:52:04.83#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.169.07:52:04.83#ibcon#ireg 17 cls_cnt 0 2006.169.07:52:04.83#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.169.07:52:04.83#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.169.07:52:04.83#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.169.07:52:04.83#ibcon#enter wrdev, iclass 36, count 0 2006.169.07:52:04.83#ibcon#first serial, iclass 36, count 0 2006.169.07:52:04.83#ibcon#enter sib2, iclass 36, count 0 2006.169.07:52:04.83#ibcon#flushed, iclass 36, count 0 2006.169.07:52:04.83#ibcon#about to write, iclass 36, count 0 2006.169.07:52:04.83#ibcon#wrote, iclass 36, count 0 2006.169.07:52:04.83#ibcon#about to read 3, iclass 36, count 0 2006.169.07:52:04.84#ibcon#read 3, iclass 36, count 0 2006.169.07:52:04.84#ibcon#about to read 4, iclass 36, count 0 2006.169.07:52:04.84#ibcon#read 4, iclass 36, count 0 2006.169.07:52:04.84#ibcon#about to read 5, iclass 36, count 0 2006.169.07:52:04.84#ibcon#read 5, iclass 36, count 0 2006.169.07:52:04.84#ibcon#about to read 6, iclass 36, count 0 2006.169.07:52:04.84#ibcon#read 6, iclass 36, count 0 2006.169.07:52:04.84#ibcon#end of sib2, iclass 36, count 0 2006.169.07:52:04.84#ibcon#*mode == 0, iclass 36, count 0 2006.169.07:52:04.84#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.169.07:52:04.84#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.07:52:04.84#ibcon#*before write, iclass 36, count 0 2006.169.07:52:04.84#ibcon#enter sib2, iclass 36, count 0 2006.169.07:52:04.84#ibcon#flushed, iclass 36, count 0 2006.169.07:52:04.84#ibcon#about to write, iclass 36, count 0 2006.169.07:52:04.84#ibcon#wrote, iclass 36, count 0 2006.169.07:52:04.84#ibcon#about to read 3, iclass 36, count 0 2006.169.07:52:04.90#ibcon#read 3, iclass 36, count 0 2006.169.07:52:04.90#ibcon#about to read 4, iclass 36, count 0 2006.169.07:52:04.90#ibcon#read 4, iclass 36, count 0 2006.169.07:52:04.90#ibcon#about to read 5, iclass 36, count 0 2006.169.07:52:04.90#ibcon#read 5, iclass 36, count 0 2006.169.07:52:04.90#ibcon#about to read 6, iclass 36, count 0 2006.169.07:52:04.90#ibcon#read 6, iclass 36, count 0 2006.169.07:52:04.90#ibcon#end of sib2, iclass 36, count 0 2006.169.07:52:04.90#ibcon#*after write, iclass 36, count 0 2006.169.07:52:04.90#ibcon#*before return 0, iclass 36, count 0 2006.169.07:52:04.90#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.169.07:52:04.90#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.169.07:52:04.90#ibcon#about to clear, iclass 36 cls_cnt 0 2006.169.07:52:04.90#ibcon#cleared, iclass 36 cls_cnt 0 2006.169.07:52:04.90$vc4f8/va=1,8 2006.169.07:52:04.90#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.169.07:52:04.90#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.169.07:52:04.90#ibcon#ireg 11 cls_cnt 2 2006.169.07:52:04.90#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.169.07:52:04.90#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.169.07:52:04.90#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.169.07:52:04.90#ibcon#enter wrdev, iclass 38, count 2 2006.169.07:52:04.90#ibcon#first serial, iclass 38, count 2 2006.169.07:52:04.90#ibcon#enter sib2, iclass 38, count 2 2006.169.07:52:04.90#ibcon#flushed, iclass 38, count 2 2006.169.07:52:04.90#ibcon#about to write, iclass 38, count 2 2006.169.07:52:04.90#ibcon#wrote, iclass 38, count 2 2006.169.07:52:04.90#ibcon#about to read 3, iclass 38, count 2 2006.169.07:52:04.91#ibcon#read 3, iclass 38, count 2 2006.169.07:52:04.91#ibcon#about to read 4, iclass 38, count 2 2006.169.07:52:04.91#ibcon#read 4, iclass 38, count 2 2006.169.07:52:04.91#ibcon#about to read 5, iclass 38, count 2 2006.169.07:52:04.91#ibcon#read 5, iclass 38, count 2 2006.169.07:52:04.91#ibcon#about to read 6, iclass 38, count 2 2006.169.07:52:04.91#ibcon#read 6, iclass 38, count 2 2006.169.07:52:04.91#ibcon#end of sib2, iclass 38, count 2 2006.169.07:52:04.91#ibcon#*mode == 0, iclass 38, count 2 2006.169.07:52:04.91#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.169.07:52:04.91#ibcon#[25=AT01-08\r\n] 2006.169.07:52:04.91#ibcon#*before write, iclass 38, count 2 2006.169.07:52:04.91#ibcon#enter sib2, iclass 38, count 2 2006.169.07:52:04.91#ibcon#flushed, iclass 38, count 2 2006.169.07:52:04.91#ibcon#about to write, iclass 38, count 2 2006.169.07:52:04.91#ibcon#wrote, iclass 38, count 2 2006.169.07:52:04.91#ibcon#about to read 3, iclass 38, count 2 2006.169.07:52:04.94#ibcon#read 3, iclass 38, count 2 2006.169.07:52:04.94#ibcon#about to read 4, iclass 38, count 2 2006.169.07:52:04.94#ibcon#read 4, iclass 38, count 2 2006.169.07:52:04.94#ibcon#about to read 5, iclass 38, count 2 2006.169.07:52:04.94#ibcon#read 5, iclass 38, count 2 2006.169.07:52:04.94#ibcon#about to read 6, iclass 38, count 2 2006.169.07:52:04.94#ibcon#read 6, iclass 38, count 2 2006.169.07:52:04.94#ibcon#end of sib2, iclass 38, count 2 2006.169.07:52:04.94#ibcon#*after write, iclass 38, count 2 2006.169.07:52:04.94#ibcon#*before return 0, iclass 38, count 2 2006.169.07:52:04.94#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.169.07:52:04.94#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.169.07:52:04.94#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.169.07:52:04.94#ibcon#ireg 7 cls_cnt 0 2006.169.07:52:04.94#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.169.07:52:05.06#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.169.07:52:05.06#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.169.07:52:05.06#ibcon#enter wrdev, iclass 38, count 0 2006.169.07:52:05.06#ibcon#first serial, iclass 38, count 0 2006.169.07:52:05.06#ibcon#enter sib2, iclass 38, count 0 2006.169.07:52:05.06#ibcon#flushed, iclass 38, count 0 2006.169.07:52:05.06#ibcon#about to write, iclass 38, count 0 2006.169.07:52:05.06#ibcon#wrote, iclass 38, count 0 2006.169.07:52:05.06#ibcon#about to read 3, iclass 38, count 0 2006.169.07:52:05.10#ibcon#read 3, iclass 38, count 0 2006.169.07:52:05.10#ibcon#about to read 4, iclass 38, count 0 2006.169.07:52:05.10#ibcon#read 4, iclass 38, count 0 2006.169.07:52:05.10#ibcon#about to read 5, iclass 38, count 0 2006.169.07:52:05.10#ibcon#read 5, iclass 38, count 0 2006.169.07:52:05.10#ibcon#about to read 6, iclass 38, count 0 2006.169.07:52:05.10#ibcon#read 6, iclass 38, count 0 2006.169.07:52:05.10#ibcon#end of sib2, iclass 38, count 0 2006.169.07:52:05.10#ibcon#*mode == 0, iclass 38, count 0 2006.169.07:52:05.10#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.169.07:52:05.10#ibcon#[25=USB\r\n] 2006.169.07:52:05.10#ibcon#*before write, iclass 38, count 0 2006.169.07:52:05.10#ibcon#enter sib2, iclass 38, count 0 2006.169.07:52:05.10#ibcon#flushed, iclass 38, count 0 2006.169.07:52:05.10#ibcon#about to write, iclass 38, count 0 2006.169.07:52:05.10#ibcon#wrote, iclass 38, count 0 2006.169.07:52:05.10#ibcon#about to read 3, iclass 38, count 0 2006.169.07:52:05.13#ibcon#read 3, iclass 38, count 0 2006.169.07:52:05.13#ibcon#about to read 4, iclass 38, count 0 2006.169.07:52:05.13#ibcon#read 4, iclass 38, count 0 2006.169.07:52:05.13#ibcon#about to read 5, iclass 38, count 0 2006.169.07:52:05.13#ibcon#read 5, iclass 38, count 0 2006.169.07:52:05.13#ibcon#about to read 6, iclass 38, count 0 2006.169.07:52:05.13#ibcon#read 6, iclass 38, count 0 2006.169.07:52:05.13#ibcon#end of sib2, iclass 38, count 0 2006.169.07:52:05.13#ibcon#*after write, iclass 38, count 0 2006.169.07:52:05.13#ibcon#*before return 0, iclass 38, count 0 2006.169.07:52:05.13#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.169.07:52:05.13#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.169.07:52:05.13#ibcon#about to clear, iclass 38 cls_cnt 0 2006.169.07:52:05.13#ibcon#cleared, iclass 38 cls_cnt 0 2006.169.07:52:05.13$vc4f8/valo=2,572.99 2006.169.07:52:05.13#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.169.07:52:05.13#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.169.07:52:05.13#ibcon#ireg 17 cls_cnt 0 2006.169.07:52:05.13#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:52:05.13#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:52:05.13#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:52:05.13#ibcon#enter wrdev, iclass 40, count 0 2006.169.07:52:05.13#ibcon#first serial, iclass 40, count 0 2006.169.07:52:05.13#ibcon#enter sib2, iclass 40, count 0 2006.169.07:52:05.13#ibcon#flushed, iclass 40, count 0 2006.169.07:52:05.13#ibcon#about to write, iclass 40, count 0 2006.169.07:52:05.13#ibcon#wrote, iclass 40, count 0 2006.169.07:52:05.13#ibcon#about to read 3, iclass 40, count 0 2006.169.07:52:05.14#flagr#flagr/antenna,acquired 2006.169.07:52:05.15#ibcon#read 3, iclass 40, count 0 2006.169.07:52:05.15#ibcon#about to read 4, iclass 40, count 0 2006.169.07:52:05.15#ibcon#read 4, iclass 40, count 0 2006.169.07:52:05.15#ibcon#about to read 5, iclass 40, count 0 2006.169.07:52:05.15#ibcon#read 5, iclass 40, count 0 2006.169.07:52:05.15#ibcon#about to read 6, iclass 40, count 0 2006.169.07:52:05.15#ibcon#read 6, iclass 40, count 0 2006.169.07:52:05.15#ibcon#end of sib2, iclass 40, count 0 2006.169.07:52:05.15#ibcon#*mode == 0, iclass 40, count 0 2006.169.07:52:05.15#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.169.07:52:05.15#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.07:52:05.15#ibcon#*before write, iclass 40, count 0 2006.169.07:52:05.15#ibcon#enter sib2, iclass 40, count 0 2006.169.07:52:05.15#ibcon#flushed, iclass 40, count 0 2006.169.07:52:05.15#ibcon#about to write, iclass 40, count 0 2006.169.07:52:05.15#ibcon#wrote, iclass 40, count 0 2006.169.07:52:05.15#ibcon#about to read 3, iclass 40, count 0 2006.169.07:52:05.19#ibcon#read 3, iclass 40, count 0 2006.169.07:52:05.19#ibcon#about to read 4, iclass 40, count 0 2006.169.07:52:05.19#ibcon#read 4, iclass 40, count 0 2006.169.07:52:05.19#ibcon#about to read 5, iclass 40, count 0 2006.169.07:52:05.19#ibcon#read 5, iclass 40, count 0 2006.169.07:52:05.19#ibcon#about to read 6, iclass 40, count 0 2006.169.07:52:05.19#ibcon#read 6, iclass 40, count 0 2006.169.07:52:05.19#ibcon#end of sib2, iclass 40, count 0 2006.169.07:52:05.19#ibcon#*after write, iclass 40, count 0 2006.169.07:52:05.19#ibcon#*before return 0, iclass 40, count 0 2006.169.07:52:05.19#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:52:05.19#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:52:05.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.169.07:52:05.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.169.07:52:05.19$vc4f8/va=2,7 2006.169.07:52:05.19#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.169.07:52:05.19#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.169.07:52:05.19#ibcon#ireg 11 cls_cnt 2 2006.169.07:52:05.19#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.169.07:52:05.25#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.169.07:52:05.25#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.169.07:52:05.25#ibcon#enter wrdev, iclass 4, count 2 2006.169.07:52:05.25#ibcon#first serial, iclass 4, count 2 2006.169.07:52:05.25#ibcon#enter sib2, iclass 4, count 2 2006.169.07:52:05.25#ibcon#flushed, iclass 4, count 2 2006.169.07:52:05.25#ibcon#about to write, iclass 4, count 2 2006.169.07:52:05.25#ibcon#wrote, iclass 4, count 2 2006.169.07:52:05.25#ibcon#about to read 3, iclass 4, count 2 2006.169.07:52:05.28#ibcon#read 3, iclass 4, count 2 2006.169.07:52:05.28#ibcon#about to read 4, iclass 4, count 2 2006.169.07:52:05.28#ibcon#read 4, iclass 4, count 2 2006.169.07:52:05.28#ibcon#about to read 5, iclass 4, count 2 2006.169.07:52:05.28#ibcon#read 5, iclass 4, count 2 2006.169.07:52:05.28#ibcon#about to read 6, iclass 4, count 2 2006.169.07:52:05.28#ibcon#read 6, iclass 4, count 2 2006.169.07:52:05.28#ibcon#end of sib2, iclass 4, count 2 2006.169.07:52:05.28#ibcon#*mode == 0, iclass 4, count 2 2006.169.07:52:05.28#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.169.07:52:05.28#ibcon#[25=AT02-07\r\n] 2006.169.07:52:05.28#ibcon#*before write, iclass 4, count 2 2006.169.07:52:05.28#ibcon#enter sib2, iclass 4, count 2 2006.169.07:52:05.28#ibcon#flushed, iclass 4, count 2 2006.169.07:52:05.28#ibcon#about to write, iclass 4, count 2 2006.169.07:52:05.28#ibcon#wrote, iclass 4, count 2 2006.169.07:52:05.28#ibcon#about to read 3, iclass 4, count 2 2006.169.07:52:05.31#ibcon#read 3, iclass 4, count 2 2006.169.07:52:05.31#ibcon#about to read 4, iclass 4, count 2 2006.169.07:52:05.31#ibcon#read 4, iclass 4, count 2 2006.169.07:52:05.31#ibcon#about to read 5, iclass 4, count 2 2006.169.07:52:05.31#ibcon#read 5, iclass 4, count 2 2006.169.07:52:05.31#ibcon#about to read 6, iclass 4, count 2 2006.169.07:52:05.31#ibcon#read 6, iclass 4, count 2 2006.169.07:52:05.31#ibcon#end of sib2, iclass 4, count 2 2006.169.07:52:05.31#ibcon#*after write, iclass 4, count 2 2006.169.07:52:05.31#ibcon#*before return 0, iclass 4, count 2 2006.169.07:52:05.31#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.169.07:52:05.31#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.169.07:52:05.31#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.169.07:52:05.31#ibcon#ireg 7 cls_cnt 0 2006.169.07:52:05.31#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.169.07:52:05.43#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.169.07:52:05.43#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.169.07:52:05.43#ibcon#enter wrdev, iclass 4, count 0 2006.169.07:52:05.43#ibcon#first serial, iclass 4, count 0 2006.169.07:52:05.43#ibcon#enter sib2, iclass 4, count 0 2006.169.07:52:05.43#ibcon#flushed, iclass 4, count 0 2006.169.07:52:05.43#ibcon#about to write, iclass 4, count 0 2006.169.07:52:05.43#ibcon#wrote, iclass 4, count 0 2006.169.07:52:05.43#ibcon#about to read 3, iclass 4, count 0 2006.169.07:52:05.45#ibcon#read 3, iclass 4, count 0 2006.169.07:52:05.45#ibcon#about to read 4, iclass 4, count 0 2006.169.07:52:05.45#ibcon#read 4, iclass 4, count 0 2006.169.07:52:05.45#ibcon#about to read 5, iclass 4, count 0 2006.169.07:52:05.45#ibcon#read 5, iclass 4, count 0 2006.169.07:52:05.45#ibcon#about to read 6, iclass 4, count 0 2006.169.07:52:05.45#ibcon#read 6, iclass 4, count 0 2006.169.07:52:05.45#ibcon#end of sib2, iclass 4, count 0 2006.169.07:52:05.45#ibcon#*mode == 0, iclass 4, count 0 2006.169.07:52:05.45#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.169.07:52:05.45#ibcon#[25=USB\r\n] 2006.169.07:52:05.45#ibcon#*before write, iclass 4, count 0 2006.169.07:52:05.45#ibcon#enter sib2, iclass 4, count 0 2006.169.07:52:05.45#ibcon#flushed, iclass 4, count 0 2006.169.07:52:05.45#ibcon#about to write, iclass 4, count 0 2006.169.07:52:05.45#ibcon#wrote, iclass 4, count 0 2006.169.07:52:05.45#ibcon#about to read 3, iclass 4, count 0 2006.169.07:52:05.48#ibcon#read 3, iclass 4, count 0 2006.169.07:52:05.48#ibcon#about to read 4, iclass 4, count 0 2006.169.07:52:05.48#ibcon#read 4, iclass 4, count 0 2006.169.07:52:05.48#ibcon#about to read 5, iclass 4, count 0 2006.169.07:52:05.48#ibcon#read 5, iclass 4, count 0 2006.169.07:52:05.48#ibcon#about to read 6, iclass 4, count 0 2006.169.07:52:05.48#ibcon#read 6, iclass 4, count 0 2006.169.07:52:05.48#ibcon#end of sib2, iclass 4, count 0 2006.169.07:52:05.48#ibcon#*after write, iclass 4, count 0 2006.169.07:52:05.48#ibcon#*before return 0, iclass 4, count 0 2006.169.07:52:05.48#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.169.07:52:05.48#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.169.07:52:05.48#ibcon#about to clear, iclass 4 cls_cnt 0 2006.169.07:52:05.48#ibcon#cleared, iclass 4 cls_cnt 0 2006.169.07:52:05.48$vc4f8/valo=3,672.99 2006.169.07:52:05.48#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.169.07:52:05.48#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.169.07:52:05.48#ibcon#ireg 17 cls_cnt 0 2006.169.07:52:05.48#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:52:05.48#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:52:05.48#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:52:05.48#ibcon#enter wrdev, iclass 6, count 0 2006.169.07:52:05.48#ibcon#first serial, iclass 6, count 0 2006.169.07:52:05.48#ibcon#enter sib2, iclass 6, count 0 2006.169.07:52:05.48#ibcon#flushed, iclass 6, count 0 2006.169.07:52:05.48#ibcon#about to write, iclass 6, count 0 2006.169.07:52:05.48#ibcon#wrote, iclass 6, count 0 2006.169.07:52:05.48#ibcon#about to read 3, iclass 6, count 0 2006.169.07:52:05.50#ibcon#read 3, iclass 6, count 0 2006.169.07:52:05.50#ibcon#about to read 4, iclass 6, count 0 2006.169.07:52:05.50#ibcon#read 4, iclass 6, count 0 2006.169.07:52:05.50#ibcon#about to read 5, iclass 6, count 0 2006.169.07:52:05.50#ibcon#read 5, iclass 6, count 0 2006.169.07:52:05.50#ibcon#about to read 6, iclass 6, count 0 2006.169.07:52:05.50#ibcon#read 6, iclass 6, count 0 2006.169.07:52:05.50#ibcon#end of sib2, iclass 6, count 0 2006.169.07:52:05.50#ibcon#*mode == 0, iclass 6, count 0 2006.169.07:52:05.50#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.169.07:52:05.50#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.07:52:05.50#ibcon#*before write, iclass 6, count 0 2006.169.07:52:05.50#ibcon#enter sib2, iclass 6, count 0 2006.169.07:52:05.50#ibcon#flushed, iclass 6, count 0 2006.169.07:52:05.50#ibcon#about to write, iclass 6, count 0 2006.169.07:52:05.50#ibcon#wrote, iclass 6, count 0 2006.169.07:52:05.50#ibcon#about to read 3, iclass 6, count 0 2006.169.07:52:05.54#ibcon#read 3, iclass 6, count 0 2006.169.07:52:05.54#ibcon#about to read 4, iclass 6, count 0 2006.169.07:52:05.54#ibcon#read 4, iclass 6, count 0 2006.169.07:52:05.54#ibcon#about to read 5, iclass 6, count 0 2006.169.07:52:05.54#ibcon#read 5, iclass 6, count 0 2006.169.07:52:05.54#ibcon#about to read 6, iclass 6, count 0 2006.169.07:52:05.54#ibcon#read 6, iclass 6, count 0 2006.169.07:52:05.54#ibcon#end of sib2, iclass 6, count 0 2006.169.07:52:05.54#ibcon#*after write, iclass 6, count 0 2006.169.07:52:05.54#ibcon#*before return 0, iclass 6, count 0 2006.169.07:52:05.54#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:52:05.54#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:52:05.54#ibcon#about to clear, iclass 6 cls_cnt 0 2006.169.07:52:05.54#ibcon#cleared, iclass 6 cls_cnt 0 2006.169.07:52:05.54$vc4f8/va=3,6 2006.169.07:52:05.54#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.169.07:52:05.54#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.169.07:52:05.54#ibcon#ireg 11 cls_cnt 2 2006.169.07:52:05.54#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.169.07:52:05.61#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.169.07:52:05.61#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.169.07:52:05.61#ibcon#enter wrdev, iclass 10, count 2 2006.169.07:52:05.61#ibcon#first serial, iclass 10, count 2 2006.169.07:52:05.61#ibcon#enter sib2, iclass 10, count 2 2006.169.07:52:05.61#ibcon#flushed, iclass 10, count 2 2006.169.07:52:05.61#ibcon#about to write, iclass 10, count 2 2006.169.07:52:05.61#ibcon#wrote, iclass 10, count 2 2006.169.07:52:05.61#ibcon#about to read 3, iclass 10, count 2 2006.169.07:52:05.62#ibcon#read 3, iclass 10, count 2 2006.169.07:52:05.62#ibcon#about to read 4, iclass 10, count 2 2006.169.07:52:05.62#ibcon#read 4, iclass 10, count 2 2006.169.07:52:05.62#ibcon#about to read 5, iclass 10, count 2 2006.169.07:52:05.62#ibcon#read 5, iclass 10, count 2 2006.169.07:52:05.62#ibcon#about to read 6, iclass 10, count 2 2006.169.07:52:05.62#ibcon#read 6, iclass 10, count 2 2006.169.07:52:05.62#ibcon#end of sib2, iclass 10, count 2 2006.169.07:52:05.62#ibcon#*mode == 0, iclass 10, count 2 2006.169.07:52:05.62#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.169.07:52:05.62#ibcon#[25=AT03-06\r\n] 2006.169.07:52:05.62#ibcon#*before write, iclass 10, count 2 2006.169.07:52:05.62#ibcon#enter sib2, iclass 10, count 2 2006.169.07:52:05.62#ibcon#flushed, iclass 10, count 2 2006.169.07:52:05.62#ibcon#about to write, iclass 10, count 2 2006.169.07:52:05.62#ibcon#wrote, iclass 10, count 2 2006.169.07:52:05.62#ibcon#about to read 3, iclass 10, count 2 2006.169.07:52:05.65#ibcon#read 3, iclass 10, count 2 2006.169.07:52:05.65#ibcon#about to read 4, iclass 10, count 2 2006.169.07:52:05.65#ibcon#read 4, iclass 10, count 2 2006.169.07:52:05.65#ibcon#about to read 5, iclass 10, count 2 2006.169.07:52:05.65#ibcon#read 5, iclass 10, count 2 2006.169.07:52:05.65#ibcon#about to read 6, iclass 10, count 2 2006.169.07:52:05.65#ibcon#read 6, iclass 10, count 2 2006.169.07:52:05.65#ibcon#end of sib2, iclass 10, count 2 2006.169.07:52:05.65#ibcon#*after write, iclass 10, count 2 2006.169.07:52:05.65#ibcon#*before return 0, iclass 10, count 2 2006.169.07:52:05.65#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.169.07:52:05.65#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.169.07:52:05.65#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.169.07:52:05.65#ibcon#ireg 7 cls_cnt 0 2006.169.07:52:05.65#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.169.07:52:05.77#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.169.07:52:05.77#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.169.07:52:05.77#ibcon#enter wrdev, iclass 10, count 0 2006.169.07:52:05.77#ibcon#first serial, iclass 10, count 0 2006.169.07:52:05.77#ibcon#enter sib2, iclass 10, count 0 2006.169.07:52:05.77#ibcon#flushed, iclass 10, count 0 2006.169.07:52:05.77#ibcon#about to write, iclass 10, count 0 2006.169.07:52:05.77#ibcon#wrote, iclass 10, count 0 2006.169.07:52:05.77#ibcon#about to read 3, iclass 10, count 0 2006.169.07:52:05.79#ibcon#read 3, iclass 10, count 0 2006.169.07:52:05.79#ibcon#about to read 4, iclass 10, count 0 2006.169.07:52:05.79#ibcon#read 4, iclass 10, count 0 2006.169.07:52:05.79#ibcon#about to read 5, iclass 10, count 0 2006.169.07:52:05.79#ibcon#read 5, iclass 10, count 0 2006.169.07:52:05.79#ibcon#about to read 6, iclass 10, count 0 2006.169.07:52:05.79#ibcon#read 6, iclass 10, count 0 2006.169.07:52:05.79#ibcon#end of sib2, iclass 10, count 0 2006.169.07:52:05.79#ibcon#*mode == 0, iclass 10, count 0 2006.169.07:52:05.79#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.169.07:52:05.79#ibcon#[25=USB\r\n] 2006.169.07:52:05.79#ibcon#*before write, iclass 10, count 0 2006.169.07:52:05.79#ibcon#enter sib2, iclass 10, count 0 2006.169.07:52:05.79#ibcon#flushed, iclass 10, count 0 2006.169.07:52:05.79#ibcon#about to write, iclass 10, count 0 2006.169.07:52:05.79#ibcon#wrote, iclass 10, count 0 2006.169.07:52:05.79#ibcon#about to read 3, iclass 10, count 0 2006.169.07:52:05.82#ibcon#read 3, iclass 10, count 0 2006.169.07:52:05.82#ibcon#about to read 4, iclass 10, count 0 2006.169.07:52:05.82#ibcon#read 4, iclass 10, count 0 2006.169.07:52:05.82#ibcon#about to read 5, iclass 10, count 0 2006.169.07:52:05.82#ibcon#read 5, iclass 10, count 0 2006.169.07:52:05.82#ibcon#about to read 6, iclass 10, count 0 2006.169.07:52:05.82#ibcon#read 6, iclass 10, count 0 2006.169.07:52:05.82#ibcon#end of sib2, iclass 10, count 0 2006.169.07:52:05.82#ibcon#*after write, iclass 10, count 0 2006.169.07:52:05.82#ibcon#*before return 0, iclass 10, count 0 2006.169.07:52:05.82#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.169.07:52:05.82#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.169.07:52:05.82#ibcon#about to clear, iclass 10 cls_cnt 0 2006.169.07:52:05.82#ibcon#cleared, iclass 10 cls_cnt 0 2006.169.07:52:05.82$vc4f8/valo=4,832.99 2006.169.07:52:05.82#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.169.07:52:05.82#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.169.07:52:05.82#ibcon#ireg 17 cls_cnt 0 2006.169.07:52:05.82#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.169.07:52:05.82#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.169.07:52:05.82#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.169.07:52:05.82#ibcon#enter wrdev, iclass 12, count 0 2006.169.07:52:05.82#ibcon#first serial, iclass 12, count 0 2006.169.07:52:05.82#ibcon#enter sib2, iclass 12, count 0 2006.169.07:52:05.82#ibcon#flushed, iclass 12, count 0 2006.169.07:52:05.82#ibcon#about to write, iclass 12, count 0 2006.169.07:52:05.82#ibcon#wrote, iclass 12, count 0 2006.169.07:52:05.82#ibcon#about to read 3, iclass 12, count 0 2006.169.07:52:05.84#ibcon#read 3, iclass 12, count 0 2006.169.07:52:05.84#ibcon#about to read 4, iclass 12, count 0 2006.169.07:52:05.84#ibcon#read 4, iclass 12, count 0 2006.169.07:52:05.84#ibcon#about to read 5, iclass 12, count 0 2006.169.07:52:05.84#ibcon#read 5, iclass 12, count 0 2006.169.07:52:05.84#ibcon#about to read 6, iclass 12, count 0 2006.169.07:52:05.84#ibcon#read 6, iclass 12, count 0 2006.169.07:52:05.84#ibcon#end of sib2, iclass 12, count 0 2006.169.07:52:05.84#ibcon#*mode == 0, iclass 12, count 0 2006.169.07:52:05.84#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.169.07:52:05.84#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.07:52:05.84#ibcon#*before write, iclass 12, count 0 2006.169.07:52:05.84#ibcon#enter sib2, iclass 12, count 0 2006.169.07:52:05.84#ibcon#flushed, iclass 12, count 0 2006.169.07:52:05.84#ibcon#about to write, iclass 12, count 0 2006.169.07:52:05.84#ibcon#wrote, iclass 12, count 0 2006.169.07:52:05.84#ibcon#about to read 3, iclass 12, count 0 2006.169.07:52:05.88#ibcon#read 3, iclass 12, count 0 2006.169.07:52:05.88#ibcon#about to read 4, iclass 12, count 0 2006.169.07:52:05.88#ibcon#read 4, iclass 12, count 0 2006.169.07:52:05.88#ibcon#about to read 5, iclass 12, count 0 2006.169.07:52:05.88#ibcon#read 5, iclass 12, count 0 2006.169.07:52:05.88#ibcon#about to read 6, iclass 12, count 0 2006.169.07:52:05.88#ibcon#read 6, iclass 12, count 0 2006.169.07:52:05.88#ibcon#end of sib2, iclass 12, count 0 2006.169.07:52:05.88#ibcon#*after write, iclass 12, count 0 2006.169.07:52:05.88#ibcon#*before return 0, iclass 12, count 0 2006.169.07:52:05.88#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.169.07:52:05.88#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.169.07:52:05.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.169.07:52:05.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.169.07:52:05.88$vc4f8/va=4,7 2006.169.07:52:05.88#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.169.07:52:05.88#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.169.07:52:05.88#ibcon#ireg 11 cls_cnt 2 2006.169.07:52:05.88#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.169.07:52:05.94#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.169.07:52:05.94#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.169.07:52:05.94#ibcon#enter wrdev, iclass 14, count 2 2006.169.07:52:05.94#ibcon#first serial, iclass 14, count 2 2006.169.07:52:05.94#ibcon#enter sib2, iclass 14, count 2 2006.169.07:52:05.94#ibcon#flushed, iclass 14, count 2 2006.169.07:52:05.94#ibcon#about to write, iclass 14, count 2 2006.169.07:52:05.94#ibcon#wrote, iclass 14, count 2 2006.169.07:52:05.94#ibcon#about to read 3, iclass 14, count 2 2006.169.07:52:05.96#ibcon#read 3, iclass 14, count 2 2006.169.07:52:05.96#ibcon#about to read 4, iclass 14, count 2 2006.169.07:52:05.96#ibcon#read 4, iclass 14, count 2 2006.169.07:52:05.96#ibcon#about to read 5, iclass 14, count 2 2006.169.07:52:05.96#ibcon#read 5, iclass 14, count 2 2006.169.07:52:05.96#ibcon#about to read 6, iclass 14, count 2 2006.169.07:52:05.96#ibcon#read 6, iclass 14, count 2 2006.169.07:52:05.96#ibcon#end of sib2, iclass 14, count 2 2006.169.07:52:05.96#ibcon#*mode == 0, iclass 14, count 2 2006.169.07:52:05.96#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.169.07:52:05.96#ibcon#[25=AT04-07\r\n] 2006.169.07:52:05.96#ibcon#*before write, iclass 14, count 2 2006.169.07:52:05.96#ibcon#enter sib2, iclass 14, count 2 2006.169.07:52:05.96#ibcon#flushed, iclass 14, count 2 2006.169.07:52:05.96#ibcon#about to write, iclass 14, count 2 2006.169.07:52:05.96#ibcon#wrote, iclass 14, count 2 2006.169.07:52:05.96#ibcon#about to read 3, iclass 14, count 2 2006.169.07:52:05.99#ibcon#read 3, iclass 14, count 2 2006.169.07:52:05.99#ibcon#about to read 4, iclass 14, count 2 2006.169.07:52:05.99#ibcon#read 4, iclass 14, count 2 2006.169.07:52:05.99#ibcon#about to read 5, iclass 14, count 2 2006.169.07:52:05.99#ibcon#read 5, iclass 14, count 2 2006.169.07:52:05.99#ibcon#about to read 6, iclass 14, count 2 2006.169.07:52:05.99#ibcon#read 6, iclass 14, count 2 2006.169.07:52:05.99#ibcon#end of sib2, iclass 14, count 2 2006.169.07:52:05.99#ibcon#*after write, iclass 14, count 2 2006.169.07:52:05.99#ibcon#*before return 0, iclass 14, count 2 2006.169.07:52:05.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.169.07:52:05.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.169.07:52:05.99#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.169.07:52:05.99#ibcon#ireg 7 cls_cnt 0 2006.169.07:52:05.99#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.169.07:52:06.11#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.169.07:52:06.11#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.169.07:52:06.11#ibcon#enter wrdev, iclass 14, count 0 2006.169.07:52:06.11#ibcon#first serial, iclass 14, count 0 2006.169.07:52:06.11#ibcon#enter sib2, iclass 14, count 0 2006.169.07:52:06.11#ibcon#flushed, iclass 14, count 0 2006.169.07:52:06.11#ibcon#about to write, iclass 14, count 0 2006.169.07:52:06.11#ibcon#wrote, iclass 14, count 0 2006.169.07:52:06.11#ibcon#about to read 3, iclass 14, count 0 2006.169.07:52:06.13#ibcon#read 3, iclass 14, count 0 2006.169.07:52:06.13#ibcon#about to read 4, iclass 14, count 0 2006.169.07:52:06.13#ibcon#read 4, iclass 14, count 0 2006.169.07:52:06.13#ibcon#about to read 5, iclass 14, count 0 2006.169.07:52:06.13#ibcon#read 5, iclass 14, count 0 2006.169.07:52:06.13#ibcon#about to read 6, iclass 14, count 0 2006.169.07:52:06.13#ibcon#read 6, iclass 14, count 0 2006.169.07:52:06.13#ibcon#end of sib2, iclass 14, count 0 2006.169.07:52:06.13#ibcon#*mode == 0, iclass 14, count 0 2006.169.07:52:06.13#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.169.07:52:06.13#ibcon#[25=USB\r\n] 2006.169.07:52:06.13#ibcon#*before write, iclass 14, count 0 2006.169.07:52:06.13#ibcon#enter sib2, iclass 14, count 0 2006.169.07:52:06.13#ibcon#flushed, iclass 14, count 0 2006.169.07:52:06.13#ibcon#about to write, iclass 14, count 0 2006.169.07:52:06.13#ibcon#wrote, iclass 14, count 0 2006.169.07:52:06.13#ibcon#about to read 3, iclass 14, count 0 2006.169.07:52:06.16#ibcon#read 3, iclass 14, count 0 2006.169.07:52:06.16#ibcon#about to read 4, iclass 14, count 0 2006.169.07:52:06.16#ibcon#read 4, iclass 14, count 0 2006.169.07:52:06.16#ibcon#about to read 5, iclass 14, count 0 2006.169.07:52:06.16#ibcon#read 5, iclass 14, count 0 2006.169.07:52:06.16#ibcon#about to read 6, iclass 14, count 0 2006.169.07:52:06.16#ibcon#read 6, iclass 14, count 0 2006.169.07:52:06.16#ibcon#end of sib2, iclass 14, count 0 2006.169.07:52:06.16#ibcon#*after write, iclass 14, count 0 2006.169.07:52:06.16#ibcon#*before return 0, iclass 14, count 0 2006.169.07:52:06.16#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.169.07:52:06.16#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.169.07:52:06.16#ibcon#about to clear, iclass 14 cls_cnt 0 2006.169.07:52:06.16#ibcon#cleared, iclass 14 cls_cnt 0 2006.169.07:52:06.16$vc4f8/valo=5,652.99 2006.169.07:52:06.16#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.169.07:52:06.16#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.169.07:52:06.16#ibcon#ireg 17 cls_cnt 0 2006.169.07:52:06.16#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:52:06.16#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:52:06.16#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:52:06.16#ibcon#enter wrdev, iclass 16, count 0 2006.169.07:52:06.16#ibcon#first serial, iclass 16, count 0 2006.169.07:52:06.16#ibcon#enter sib2, iclass 16, count 0 2006.169.07:52:06.16#ibcon#flushed, iclass 16, count 0 2006.169.07:52:06.16#ibcon#about to write, iclass 16, count 0 2006.169.07:52:06.16#ibcon#wrote, iclass 16, count 0 2006.169.07:52:06.16#ibcon#about to read 3, iclass 16, count 0 2006.169.07:52:06.18#ibcon#read 3, iclass 16, count 0 2006.169.07:52:06.18#ibcon#about to read 4, iclass 16, count 0 2006.169.07:52:06.18#ibcon#read 4, iclass 16, count 0 2006.169.07:52:06.18#ibcon#about to read 5, iclass 16, count 0 2006.169.07:52:06.18#ibcon#read 5, iclass 16, count 0 2006.169.07:52:06.18#ibcon#about to read 6, iclass 16, count 0 2006.169.07:52:06.18#ibcon#read 6, iclass 16, count 0 2006.169.07:52:06.18#ibcon#end of sib2, iclass 16, count 0 2006.169.07:52:06.18#ibcon#*mode == 0, iclass 16, count 0 2006.169.07:52:06.18#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.169.07:52:06.18#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.07:52:06.18#ibcon#*before write, iclass 16, count 0 2006.169.07:52:06.18#ibcon#enter sib2, iclass 16, count 0 2006.169.07:52:06.18#ibcon#flushed, iclass 16, count 0 2006.169.07:52:06.18#ibcon#about to write, iclass 16, count 0 2006.169.07:52:06.18#ibcon#wrote, iclass 16, count 0 2006.169.07:52:06.18#ibcon#about to read 3, iclass 16, count 0 2006.169.07:52:06.22#ibcon#read 3, iclass 16, count 0 2006.169.07:52:06.22#ibcon#about to read 4, iclass 16, count 0 2006.169.07:52:06.22#ibcon#read 4, iclass 16, count 0 2006.169.07:52:06.22#ibcon#about to read 5, iclass 16, count 0 2006.169.07:52:06.22#ibcon#read 5, iclass 16, count 0 2006.169.07:52:06.22#ibcon#about to read 6, iclass 16, count 0 2006.169.07:52:06.22#ibcon#read 6, iclass 16, count 0 2006.169.07:52:06.22#ibcon#end of sib2, iclass 16, count 0 2006.169.07:52:06.22#ibcon#*after write, iclass 16, count 0 2006.169.07:52:06.22#ibcon#*before return 0, iclass 16, count 0 2006.169.07:52:06.22#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:52:06.22#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:52:06.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.169.07:52:06.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.169.07:52:06.22$vc4f8/va=5,7 2006.169.07:52:06.22#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.169.07:52:06.22#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.169.07:52:06.22#ibcon#ireg 11 cls_cnt 2 2006.169.07:52:06.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.169.07:52:06.29#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.169.07:52:06.29#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.169.07:52:06.29#ibcon#enter wrdev, iclass 18, count 2 2006.169.07:52:06.29#ibcon#first serial, iclass 18, count 2 2006.169.07:52:06.29#ibcon#enter sib2, iclass 18, count 2 2006.169.07:52:06.29#ibcon#flushed, iclass 18, count 2 2006.169.07:52:06.29#ibcon#about to write, iclass 18, count 2 2006.169.07:52:06.29#ibcon#wrote, iclass 18, count 2 2006.169.07:52:06.29#ibcon#about to read 3, iclass 18, count 2 2006.169.07:52:06.30#ibcon#read 3, iclass 18, count 2 2006.169.07:52:06.30#ibcon#about to read 4, iclass 18, count 2 2006.169.07:52:06.30#ibcon#read 4, iclass 18, count 2 2006.169.07:52:06.30#ibcon#about to read 5, iclass 18, count 2 2006.169.07:52:06.30#ibcon#read 5, iclass 18, count 2 2006.169.07:52:06.30#ibcon#about to read 6, iclass 18, count 2 2006.169.07:52:06.30#ibcon#read 6, iclass 18, count 2 2006.169.07:52:06.30#ibcon#end of sib2, iclass 18, count 2 2006.169.07:52:06.30#ibcon#*mode == 0, iclass 18, count 2 2006.169.07:52:06.30#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.169.07:52:06.30#ibcon#[25=AT05-07\r\n] 2006.169.07:52:06.30#ibcon#*before write, iclass 18, count 2 2006.169.07:52:06.30#ibcon#enter sib2, iclass 18, count 2 2006.169.07:52:06.30#ibcon#flushed, iclass 18, count 2 2006.169.07:52:06.30#ibcon#about to write, iclass 18, count 2 2006.169.07:52:06.30#ibcon#wrote, iclass 18, count 2 2006.169.07:52:06.30#ibcon#about to read 3, iclass 18, count 2 2006.169.07:52:06.33#ibcon#read 3, iclass 18, count 2 2006.169.07:52:06.33#ibcon#about to read 4, iclass 18, count 2 2006.169.07:52:06.33#ibcon#read 4, iclass 18, count 2 2006.169.07:52:06.33#ibcon#about to read 5, iclass 18, count 2 2006.169.07:52:06.33#ibcon#read 5, iclass 18, count 2 2006.169.07:52:06.33#ibcon#about to read 6, iclass 18, count 2 2006.169.07:52:06.33#ibcon#read 6, iclass 18, count 2 2006.169.07:52:06.33#ibcon#end of sib2, iclass 18, count 2 2006.169.07:52:06.33#ibcon#*after write, iclass 18, count 2 2006.169.07:52:06.33#ibcon#*before return 0, iclass 18, count 2 2006.169.07:52:06.33#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.169.07:52:06.33#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.169.07:52:06.33#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.169.07:52:06.33#ibcon#ireg 7 cls_cnt 0 2006.169.07:52:06.33#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.169.07:52:06.39#abcon#<5=/04 3.2 5.9 18.111001003.9\r\n> 2006.169.07:52:06.41#abcon#{5=INTERFACE CLEAR} 2006.169.07:52:06.45#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.169.07:52:06.45#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.169.07:52:06.45#ibcon#enter wrdev, iclass 18, count 0 2006.169.07:52:06.45#ibcon#first serial, iclass 18, count 0 2006.169.07:52:06.45#ibcon#enter sib2, iclass 18, count 0 2006.169.07:52:06.45#ibcon#flushed, iclass 18, count 0 2006.169.07:52:06.45#ibcon#about to write, iclass 18, count 0 2006.169.07:52:06.45#ibcon#wrote, iclass 18, count 0 2006.169.07:52:06.45#ibcon#about to read 3, iclass 18, count 0 2006.169.07:52:06.49#ibcon#read 3, iclass 18, count 0 2006.169.07:52:06.49#ibcon#about to read 4, iclass 18, count 0 2006.169.07:52:06.49#ibcon#read 4, iclass 18, count 0 2006.169.07:52:06.49#ibcon#about to read 5, iclass 18, count 0 2006.169.07:52:06.49#ibcon#read 5, iclass 18, count 0 2006.169.07:52:06.49#ibcon#about to read 6, iclass 18, count 0 2006.169.07:52:06.49#ibcon#read 6, iclass 18, count 0 2006.169.07:52:06.49#ibcon#end of sib2, iclass 18, count 0 2006.169.07:52:06.49#ibcon#*mode == 0, iclass 18, count 0 2006.169.07:52:06.49#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.169.07:52:06.49#ibcon#[25=USB\r\n] 2006.169.07:52:06.49#ibcon#*before write, iclass 18, count 0 2006.169.07:52:06.49#ibcon#enter sib2, iclass 18, count 0 2006.169.07:52:06.49#ibcon#flushed, iclass 18, count 0 2006.169.07:52:06.49#ibcon#about to write, iclass 18, count 0 2006.169.07:52:06.49#ibcon#wrote, iclass 18, count 0 2006.169.07:52:06.49#ibcon#about to read 3, iclass 18, count 0 2006.169.07:52:06.49#abcon#[5=S1D000X0/0*\r\n] 2006.169.07:52:06.52#ibcon#read 3, iclass 18, count 0 2006.169.07:52:06.52#ibcon#about to read 4, iclass 18, count 0 2006.169.07:52:06.52#ibcon#read 4, iclass 18, count 0 2006.169.07:52:06.52#ibcon#about to read 5, iclass 18, count 0 2006.169.07:52:06.52#ibcon#read 5, iclass 18, count 0 2006.169.07:52:06.52#ibcon#about to read 6, iclass 18, count 0 2006.169.07:52:06.52#ibcon#read 6, iclass 18, count 0 2006.169.07:52:06.52#ibcon#end of sib2, iclass 18, count 0 2006.169.07:52:06.52#ibcon#*after write, iclass 18, count 0 2006.169.07:52:06.52#ibcon#*before return 0, iclass 18, count 0 2006.169.07:52:06.52#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.169.07:52:06.52#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.169.07:52:06.52#ibcon#about to clear, iclass 18 cls_cnt 0 2006.169.07:52:06.52#ibcon#cleared, iclass 18 cls_cnt 0 2006.169.07:52:06.52$vc4f8/valo=6,772.99 2006.169.07:52:06.52#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.169.07:52:06.52#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.169.07:52:06.52#ibcon#ireg 17 cls_cnt 0 2006.169.07:52:06.52#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.169.07:52:06.52#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.169.07:52:06.52#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.169.07:52:06.52#ibcon#enter wrdev, iclass 24, count 0 2006.169.07:52:06.52#ibcon#first serial, iclass 24, count 0 2006.169.07:52:06.52#ibcon#enter sib2, iclass 24, count 0 2006.169.07:52:06.52#ibcon#flushed, iclass 24, count 0 2006.169.07:52:06.52#ibcon#about to write, iclass 24, count 0 2006.169.07:52:06.52#ibcon#wrote, iclass 24, count 0 2006.169.07:52:06.52#ibcon#about to read 3, iclass 24, count 0 2006.169.07:52:06.54#ibcon#read 3, iclass 24, count 0 2006.169.07:52:06.54#ibcon#about to read 4, iclass 24, count 0 2006.169.07:52:06.54#ibcon#read 4, iclass 24, count 0 2006.169.07:52:06.54#ibcon#about to read 5, iclass 24, count 0 2006.169.07:52:06.54#ibcon#read 5, iclass 24, count 0 2006.169.07:52:06.54#ibcon#about to read 6, iclass 24, count 0 2006.169.07:52:06.54#ibcon#read 6, iclass 24, count 0 2006.169.07:52:06.54#ibcon#end of sib2, iclass 24, count 0 2006.169.07:52:06.54#ibcon#*mode == 0, iclass 24, count 0 2006.169.07:52:06.54#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.169.07:52:06.54#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.07:52:06.54#ibcon#*before write, iclass 24, count 0 2006.169.07:52:06.54#ibcon#enter sib2, iclass 24, count 0 2006.169.07:52:06.54#ibcon#flushed, iclass 24, count 0 2006.169.07:52:06.54#ibcon#about to write, iclass 24, count 0 2006.169.07:52:06.54#ibcon#wrote, iclass 24, count 0 2006.169.07:52:06.54#ibcon#about to read 3, iclass 24, count 0 2006.169.07:52:06.58#ibcon#read 3, iclass 24, count 0 2006.169.07:52:06.58#ibcon#about to read 4, iclass 24, count 0 2006.169.07:52:06.58#ibcon#read 4, iclass 24, count 0 2006.169.07:52:06.58#ibcon#about to read 5, iclass 24, count 0 2006.169.07:52:06.58#ibcon#read 5, iclass 24, count 0 2006.169.07:52:06.58#ibcon#about to read 6, iclass 24, count 0 2006.169.07:52:06.58#ibcon#read 6, iclass 24, count 0 2006.169.07:52:06.58#ibcon#end of sib2, iclass 24, count 0 2006.169.07:52:06.58#ibcon#*after write, iclass 24, count 0 2006.169.07:52:06.58#ibcon#*before return 0, iclass 24, count 0 2006.169.07:52:06.58#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.169.07:52:06.58#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.169.07:52:06.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.169.07:52:06.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.169.07:52:06.58$vc4f8/va=6,6 2006.169.07:52:06.58#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.169.07:52:06.58#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.169.07:52:06.58#ibcon#ireg 11 cls_cnt 2 2006.169.07:52:06.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.169.07:52:06.64#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.169.07:52:06.64#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.169.07:52:06.64#ibcon#enter wrdev, iclass 26, count 2 2006.169.07:52:06.64#ibcon#first serial, iclass 26, count 2 2006.169.07:52:06.64#ibcon#enter sib2, iclass 26, count 2 2006.169.07:52:06.64#ibcon#flushed, iclass 26, count 2 2006.169.07:52:06.64#ibcon#about to write, iclass 26, count 2 2006.169.07:52:06.64#ibcon#wrote, iclass 26, count 2 2006.169.07:52:06.64#ibcon#about to read 3, iclass 26, count 2 2006.169.07:52:06.66#ibcon#read 3, iclass 26, count 2 2006.169.07:52:06.66#ibcon#about to read 4, iclass 26, count 2 2006.169.07:52:06.66#ibcon#read 4, iclass 26, count 2 2006.169.07:52:06.66#ibcon#about to read 5, iclass 26, count 2 2006.169.07:52:06.66#ibcon#read 5, iclass 26, count 2 2006.169.07:52:06.66#ibcon#about to read 6, iclass 26, count 2 2006.169.07:52:06.66#ibcon#read 6, iclass 26, count 2 2006.169.07:52:06.66#ibcon#end of sib2, iclass 26, count 2 2006.169.07:52:06.66#ibcon#*mode == 0, iclass 26, count 2 2006.169.07:52:06.66#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.169.07:52:06.66#ibcon#[25=AT06-06\r\n] 2006.169.07:52:06.66#ibcon#*before write, iclass 26, count 2 2006.169.07:52:06.66#ibcon#enter sib2, iclass 26, count 2 2006.169.07:52:06.66#ibcon#flushed, iclass 26, count 2 2006.169.07:52:06.66#ibcon#about to write, iclass 26, count 2 2006.169.07:52:06.66#ibcon#wrote, iclass 26, count 2 2006.169.07:52:06.66#ibcon#about to read 3, iclass 26, count 2 2006.169.07:52:06.69#ibcon#read 3, iclass 26, count 2 2006.169.07:52:06.69#ibcon#about to read 4, iclass 26, count 2 2006.169.07:52:06.69#ibcon#read 4, iclass 26, count 2 2006.169.07:52:06.69#ibcon#about to read 5, iclass 26, count 2 2006.169.07:52:06.69#ibcon#read 5, iclass 26, count 2 2006.169.07:52:06.69#ibcon#about to read 6, iclass 26, count 2 2006.169.07:52:06.69#ibcon#read 6, iclass 26, count 2 2006.169.07:52:06.69#ibcon#end of sib2, iclass 26, count 2 2006.169.07:52:06.69#ibcon#*after write, iclass 26, count 2 2006.169.07:52:06.69#ibcon#*before return 0, iclass 26, count 2 2006.169.07:52:06.69#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.169.07:52:06.69#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.169.07:52:06.69#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.169.07:52:06.69#ibcon#ireg 7 cls_cnt 0 2006.169.07:52:06.69#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.169.07:52:06.81#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.169.07:52:06.81#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.169.07:52:06.81#ibcon#enter wrdev, iclass 26, count 0 2006.169.07:52:06.81#ibcon#first serial, iclass 26, count 0 2006.169.07:52:06.81#ibcon#enter sib2, iclass 26, count 0 2006.169.07:52:06.81#ibcon#flushed, iclass 26, count 0 2006.169.07:52:06.81#ibcon#about to write, iclass 26, count 0 2006.169.07:52:06.81#ibcon#wrote, iclass 26, count 0 2006.169.07:52:06.81#ibcon#about to read 3, iclass 26, count 0 2006.169.07:52:06.83#ibcon#read 3, iclass 26, count 0 2006.169.07:52:06.83#ibcon#about to read 4, iclass 26, count 0 2006.169.07:52:06.83#ibcon#read 4, iclass 26, count 0 2006.169.07:52:06.83#ibcon#about to read 5, iclass 26, count 0 2006.169.07:52:06.83#ibcon#read 5, iclass 26, count 0 2006.169.07:52:06.83#ibcon#about to read 6, iclass 26, count 0 2006.169.07:52:06.83#ibcon#read 6, iclass 26, count 0 2006.169.07:52:06.83#ibcon#end of sib2, iclass 26, count 0 2006.169.07:52:06.83#ibcon#*mode == 0, iclass 26, count 0 2006.169.07:52:06.83#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.169.07:52:06.83#ibcon#[25=USB\r\n] 2006.169.07:52:06.83#ibcon#*before write, iclass 26, count 0 2006.169.07:52:06.83#ibcon#enter sib2, iclass 26, count 0 2006.169.07:52:06.83#ibcon#flushed, iclass 26, count 0 2006.169.07:52:06.83#ibcon#about to write, iclass 26, count 0 2006.169.07:52:06.83#ibcon#wrote, iclass 26, count 0 2006.169.07:52:06.83#ibcon#about to read 3, iclass 26, count 0 2006.169.07:52:06.86#ibcon#read 3, iclass 26, count 0 2006.169.07:52:06.86#ibcon#about to read 4, iclass 26, count 0 2006.169.07:52:06.86#ibcon#read 4, iclass 26, count 0 2006.169.07:52:06.86#ibcon#about to read 5, iclass 26, count 0 2006.169.07:52:06.86#ibcon#read 5, iclass 26, count 0 2006.169.07:52:06.86#ibcon#about to read 6, iclass 26, count 0 2006.169.07:52:06.86#ibcon#read 6, iclass 26, count 0 2006.169.07:52:06.86#ibcon#end of sib2, iclass 26, count 0 2006.169.07:52:06.86#ibcon#*after write, iclass 26, count 0 2006.169.07:52:06.86#ibcon#*before return 0, iclass 26, count 0 2006.169.07:52:06.86#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.169.07:52:06.86#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.169.07:52:06.86#ibcon#about to clear, iclass 26 cls_cnt 0 2006.169.07:52:06.86#ibcon#cleared, iclass 26 cls_cnt 0 2006.169.07:52:06.86$vc4f8/valo=7,832.99 2006.169.07:52:06.86#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.169.07:52:06.86#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.169.07:52:06.86#ibcon#ireg 17 cls_cnt 0 2006.169.07:52:06.86#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:52:06.86#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:52:06.86#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:52:06.86#ibcon#enter wrdev, iclass 28, count 0 2006.169.07:52:06.86#ibcon#first serial, iclass 28, count 0 2006.169.07:52:06.86#ibcon#enter sib2, iclass 28, count 0 2006.169.07:52:06.86#ibcon#flushed, iclass 28, count 0 2006.169.07:52:06.86#ibcon#about to write, iclass 28, count 0 2006.169.07:52:06.86#ibcon#wrote, iclass 28, count 0 2006.169.07:52:06.86#ibcon#about to read 3, iclass 28, count 0 2006.169.07:52:06.88#ibcon#read 3, iclass 28, count 0 2006.169.07:52:06.88#ibcon#about to read 4, iclass 28, count 0 2006.169.07:52:06.88#ibcon#read 4, iclass 28, count 0 2006.169.07:52:06.88#ibcon#about to read 5, iclass 28, count 0 2006.169.07:52:06.88#ibcon#read 5, iclass 28, count 0 2006.169.07:52:06.88#ibcon#about to read 6, iclass 28, count 0 2006.169.07:52:06.88#ibcon#read 6, iclass 28, count 0 2006.169.07:52:06.88#ibcon#end of sib2, iclass 28, count 0 2006.169.07:52:06.88#ibcon#*mode == 0, iclass 28, count 0 2006.169.07:52:06.88#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.169.07:52:06.88#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.07:52:06.88#ibcon#*before write, iclass 28, count 0 2006.169.07:52:06.88#ibcon#enter sib2, iclass 28, count 0 2006.169.07:52:06.88#ibcon#flushed, iclass 28, count 0 2006.169.07:52:06.88#ibcon#about to write, iclass 28, count 0 2006.169.07:52:06.88#ibcon#wrote, iclass 28, count 0 2006.169.07:52:06.88#ibcon#about to read 3, iclass 28, count 0 2006.169.07:52:06.92#ibcon#read 3, iclass 28, count 0 2006.169.07:52:06.92#ibcon#about to read 4, iclass 28, count 0 2006.169.07:52:06.92#ibcon#read 4, iclass 28, count 0 2006.169.07:52:06.92#ibcon#about to read 5, iclass 28, count 0 2006.169.07:52:06.92#ibcon#read 5, iclass 28, count 0 2006.169.07:52:06.92#ibcon#about to read 6, iclass 28, count 0 2006.169.07:52:06.92#ibcon#read 6, iclass 28, count 0 2006.169.07:52:06.92#ibcon#end of sib2, iclass 28, count 0 2006.169.07:52:06.92#ibcon#*after write, iclass 28, count 0 2006.169.07:52:06.92#ibcon#*before return 0, iclass 28, count 0 2006.169.07:52:06.92#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:52:06.92#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.169.07:52:06.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.169.07:52:06.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.169.07:52:06.92$vc4f8/va=7,6 2006.169.07:52:06.92#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.169.07:52:06.92#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.169.07:52:06.92#ibcon#ireg 11 cls_cnt 2 2006.169.07:52:06.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:52:06.98#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:52:06.98#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:52:06.98#ibcon#enter wrdev, iclass 30, count 2 2006.169.07:52:06.98#ibcon#first serial, iclass 30, count 2 2006.169.07:52:06.98#ibcon#enter sib2, iclass 30, count 2 2006.169.07:52:06.98#ibcon#flushed, iclass 30, count 2 2006.169.07:52:06.98#ibcon#about to write, iclass 30, count 2 2006.169.07:52:06.98#ibcon#wrote, iclass 30, count 2 2006.169.07:52:06.98#ibcon#about to read 3, iclass 30, count 2 2006.169.07:52:07.00#ibcon#read 3, iclass 30, count 2 2006.169.07:52:07.00#ibcon#about to read 4, iclass 30, count 2 2006.169.07:52:07.00#ibcon#read 4, iclass 30, count 2 2006.169.07:52:07.00#ibcon#about to read 5, iclass 30, count 2 2006.169.07:52:07.00#ibcon#read 5, iclass 30, count 2 2006.169.07:52:07.00#ibcon#about to read 6, iclass 30, count 2 2006.169.07:52:07.00#ibcon#read 6, iclass 30, count 2 2006.169.07:52:07.00#ibcon#end of sib2, iclass 30, count 2 2006.169.07:52:07.00#ibcon#*mode == 0, iclass 30, count 2 2006.169.07:52:07.00#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.169.07:52:07.00#ibcon#[25=AT07-06\r\n] 2006.169.07:52:07.00#ibcon#*before write, iclass 30, count 2 2006.169.07:52:07.00#ibcon#enter sib2, iclass 30, count 2 2006.169.07:52:07.00#ibcon#flushed, iclass 30, count 2 2006.169.07:52:07.00#ibcon#about to write, iclass 30, count 2 2006.169.07:52:07.00#ibcon#wrote, iclass 30, count 2 2006.169.07:52:07.00#ibcon#about to read 3, iclass 30, count 2 2006.169.07:52:07.03#ibcon#read 3, iclass 30, count 2 2006.169.07:52:07.03#ibcon#about to read 4, iclass 30, count 2 2006.169.07:52:07.03#ibcon#read 4, iclass 30, count 2 2006.169.07:52:07.03#ibcon#about to read 5, iclass 30, count 2 2006.169.07:52:07.03#ibcon#read 5, iclass 30, count 2 2006.169.07:52:07.03#ibcon#about to read 6, iclass 30, count 2 2006.169.07:52:07.03#ibcon#read 6, iclass 30, count 2 2006.169.07:52:07.03#ibcon#end of sib2, iclass 30, count 2 2006.169.07:52:07.03#ibcon#*after write, iclass 30, count 2 2006.169.07:52:07.03#ibcon#*before return 0, iclass 30, count 2 2006.169.07:52:07.03#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:52:07.03#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.169.07:52:07.03#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.169.07:52:07.03#ibcon#ireg 7 cls_cnt 0 2006.169.07:52:07.03#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:52:07.15#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:52:07.15#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:52:07.15#ibcon#enter wrdev, iclass 30, count 0 2006.169.07:52:07.15#ibcon#first serial, iclass 30, count 0 2006.169.07:52:07.15#ibcon#enter sib2, iclass 30, count 0 2006.169.07:52:07.15#ibcon#flushed, iclass 30, count 0 2006.169.07:52:07.15#ibcon#about to write, iclass 30, count 0 2006.169.07:52:07.15#ibcon#wrote, iclass 30, count 0 2006.169.07:52:07.15#ibcon#about to read 3, iclass 30, count 0 2006.169.07:52:07.17#ibcon#read 3, iclass 30, count 0 2006.169.07:52:07.17#ibcon#about to read 4, iclass 30, count 0 2006.169.07:52:07.17#ibcon#read 4, iclass 30, count 0 2006.169.07:52:07.17#ibcon#about to read 5, iclass 30, count 0 2006.169.07:52:07.17#ibcon#read 5, iclass 30, count 0 2006.169.07:52:07.17#ibcon#about to read 6, iclass 30, count 0 2006.169.07:52:07.17#ibcon#read 6, iclass 30, count 0 2006.169.07:52:07.17#ibcon#end of sib2, iclass 30, count 0 2006.169.07:52:07.17#ibcon#*mode == 0, iclass 30, count 0 2006.169.07:52:07.17#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.169.07:52:07.17#ibcon#[25=USB\r\n] 2006.169.07:52:07.17#ibcon#*before write, iclass 30, count 0 2006.169.07:52:07.17#ibcon#enter sib2, iclass 30, count 0 2006.169.07:52:07.17#ibcon#flushed, iclass 30, count 0 2006.169.07:52:07.17#ibcon#about to write, iclass 30, count 0 2006.169.07:52:07.17#ibcon#wrote, iclass 30, count 0 2006.169.07:52:07.17#ibcon#about to read 3, iclass 30, count 0 2006.169.07:52:07.20#ibcon#read 3, iclass 30, count 0 2006.169.07:52:07.21#ibcon#about to read 4, iclass 30, count 0 2006.169.07:52:07.21#ibcon#read 4, iclass 30, count 0 2006.169.07:52:07.21#ibcon#about to read 5, iclass 30, count 0 2006.169.07:52:07.21#ibcon#read 5, iclass 30, count 0 2006.169.07:52:07.21#ibcon#about to read 6, iclass 30, count 0 2006.169.07:52:07.21#ibcon#read 6, iclass 30, count 0 2006.169.07:52:07.21#ibcon#end of sib2, iclass 30, count 0 2006.169.07:52:07.21#ibcon#*after write, iclass 30, count 0 2006.169.07:52:07.21#ibcon#*before return 0, iclass 30, count 0 2006.169.07:52:07.21#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:52:07.21#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.169.07:52:07.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.169.07:52:07.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.169.07:52:07.21$vc4f8/valo=8,852.99 2006.169.07:52:07.21#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.169.07:52:07.21#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.169.07:52:07.21#ibcon#ireg 17 cls_cnt 0 2006.169.07:52:07.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:52:07.21#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:52:07.21#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:52:07.21#ibcon#enter wrdev, iclass 32, count 0 2006.169.07:52:07.21#ibcon#first serial, iclass 32, count 0 2006.169.07:52:07.21#ibcon#enter sib2, iclass 32, count 0 2006.169.07:52:07.21#ibcon#flushed, iclass 32, count 0 2006.169.07:52:07.21#ibcon#about to write, iclass 32, count 0 2006.169.07:52:07.21#ibcon#wrote, iclass 32, count 0 2006.169.07:52:07.21#ibcon#about to read 3, iclass 32, count 0 2006.169.07:52:07.22#ibcon#read 3, iclass 32, count 0 2006.169.07:52:07.22#ibcon#about to read 4, iclass 32, count 0 2006.169.07:52:07.22#ibcon#read 4, iclass 32, count 0 2006.169.07:52:07.22#ibcon#about to read 5, iclass 32, count 0 2006.169.07:52:07.22#ibcon#read 5, iclass 32, count 0 2006.169.07:52:07.22#ibcon#about to read 6, iclass 32, count 0 2006.169.07:52:07.22#ibcon#read 6, iclass 32, count 0 2006.169.07:52:07.22#ibcon#end of sib2, iclass 32, count 0 2006.169.07:52:07.22#ibcon#*mode == 0, iclass 32, count 0 2006.169.07:52:07.22#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.169.07:52:07.22#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.07:52:07.22#ibcon#*before write, iclass 32, count 0 2006.169.07:52:07.22#ibcon#enter sib2, iclass 32, count 0 2006.169.07:52:07.22#ibcon#flushed, iclass 32, count 0 2006.169.07:52:07.22#ibcon#about to write, iclass 32, count 0 2006.169.07:52:07.22#ibcon#wrote, iclass 32, count 0 2006.169.07:52:07.22#ibcon#about to read 3, iclass 32, count 0 2006.169.07:52:07.26#ibcon#read 3, iclass 32, count 0 2006.169.07:52:07.26#ibcon#about to read 4, iclass 32, count 0 2006.169.07:52:07.26#ibcon#read 4, iclass 32, count 0 2006.169.07:52:07.26#ibcon#about to read 5, iclass 32, count 0 2006.169.07:52:07.26#ibcon#read 5, iclass 32, count 0 2006.169.07:52:07.26#ibcon#about to read 6, iclass 32, count 0 2006.169.07:52:07.26#ibcon#read 6, iclass 32, count 0 2006.169.07:52:07.26#ibcon#end of sib2, iclass 32, count 0 2006.169.07:52:07.26#ibcon#*after write, iclass 32, count 0 2006.169.07:52:07.26#ibcon#*before return 0, iclass 32, count 0 2006.169.07:52:07.26#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:52:07.26#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.169.07:52:07.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.169.07:52:07.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.169.07:52:07.26$vc4f8/va=8,7 2006.169.07:52:07.26#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.169.07:52:07.26#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.169.07:52:07.26#ibcon#ireg 11 cls_cnt 2 2006.169.07:52:07.26#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.169.07:52:07.33#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.169.07:52:07.33#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.169.07:52:07.33#ibcon#enter wrdev, iclass 34, count 2 2006.169.07:52:07.33#ibcon#first serial, iclass 34, count 2 2006.169.07:52:07.33#ibcon#enter sib2, iclass 34, count 2 2006.169.07:52:07.33#ibcon#flushed, iclass 34, count 2 2006.169.07:52:07.33#ibcon#about to write, iclass 34, count 2 2006.169.07:52:07.33#ibcon#wrote, iclass 34, count 2 2006.169.07:52:07.33#ibcon#about to read 3, iclass 34, count 2 2006.169.07:52:07.35#ibcon#read 3, iclass 34, count 2 2006.169.07:52:07.35#ibcon#about to read 4, iclass 34, count 2 2006.169.07:52:07.35#ibcon#read 4, iclass 34, count 2 2006.169.07:52:07.35#ibcon#about to read 5, iclass 34, count 2 2006.169.07:52:07.35#ibcon#read 5, iclass 34, count 2 2006.169.07:52:07.35#ibcon#about to read 6, iclass 34, count 2 2006.169.07:52:07.35#ibcon#read 6, iclass 34, count 2 2006.169.07:52:07.35#ibcon#end of sib2, iclass 34, count 2 2006.169.07:52:07.35#ibcon#*mode == 0, iclass 34, count 2 2006.169.07:52:07.35#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.169.07:52:07.35#ibcon#[25=AT08-07\r\n] 2006.169.07:52:07.35#ibcon#*before write, iclass 34, count 2 2006.169.07:52:07.35#ibcon#enter sib2, iclass 34, count 2 2006.169.07:52:07.35#ibcon#flushed, iclass 34, count 2 2006.169.07:52:07.35#ibcon#about to write, iclass 34, count 2 2006.169.07:52:07.35#ibcon#wrote, iclass 34, count 2 2006.169.07:52:07.35#ibcon#about to read 3, iclass 34, count 2 2006.169.07:52:07.38#ibcon#read 3, iclass 34, count 2 2006.169.07:52:07.38#ibcon#about to read 4, iclass 34, count 2 2006.169.07:52:07.38#ibcon#read 4, iclass 34, count 2 2006.169.07:52:07.38#ibcon#about to read 5, iclass 34, count 2 2006.169.07:52:07.38#ibcon#read 5, iclass 34, count 2 2006.169.07:52:07.38#ibcon#about to read 6, iclass 34, count 2 2006.169.07:52:07.38#ibcon#read 6, iclass 34, count 2 2006.169.07:52:07.38#ibcon#end of sib2, iclass 34, count 2 2006.169.07:52:07.38#ibcon#*after write, iclass 34, count 2 2006.169.07:52:07.38#ibcon#*before return 0, iclass 34, count 2 2006.169.07:52:07.38#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.169.07:52:07.38#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.169.07:52:07.38#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.169.07:52:07.38#ibcon#ireg 7 cls_cnt 0 2006.169.07:52:07.38#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.169.07:52:07.50#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.169.07:52:07.50#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.169.07:52:07.50#ibcon#enter wrdev, iclass 34, count 0 2006.169.07:52:07.50#ibcon#first serial, iclass 34, count 0 2006.169.07:52:07.50#ibcon#enter sib2, iclass 34, count 0 2006.169.07:52:07.50#ibcon#flushed, iclass 34, count 0 2006.169.07:52:07.50#ibcon#about to write, iclass 34, count 0 2006.169.07:52:07.50#ibcon#wrote, iclass 34, count 0 2006.169.07:52:07.50#ibcon#about to read 3, iclass 34, count 0 2006.169.07:52:07.52#ibcon#read 3, iclass 34, count 0 2006.169.07:52:07.52#ibcon#about to read 4, iclass 34, count 0 2006.169.07:52:07.52#ibcon#read 4, iclass 34, count 0 2006.169.07:52:07.52#ibcon#about to read 5, iclass 34, count 0 2006.169.07:52:07.52#ibcon#read 5, iclass 34, count 0 2006.169.07:52:07.52#ibcon#about to read 6, iclass 34, count 0 2006.169.07:52:07.52#ibcon#read 6, iclass 34, count 0 2006.169.07:52:07.52#ibcon#end of sib2, iclass 34, count 0 2006.169.07:52:07.52#ibcon#*mode == 0, iclass 34, count 0 2006.169.07:52:07.52#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.169.07:52:07.52#ibcon#[25=USB\r\n] 2006.169.07:52:07.52#ibcon#*before write, iclass 34, count 0 2006.169.07:52:07.52#ibcon#enter sib2, iclass 34, count 0 2006.169.07:52:07.52#ibcon#flushed, iclass 34, count 0 2006.169.07:52:07.52#ibcon#about to write, iclass 34, count 0 2006.169.07:52:07.52#ibcon#wrote, iclass 34, count 0 2006.169.07:52:07.52#ibcon#about to read 3, iclass 34, count 0 2006.169.07:52:07.55#ibcon#read 3, iclass 34, count 0 2006.169.07:52:07.55#ibcon#about to read 4, iclass 34, count 0 2006.169.07:52:07.55#ibcon#read 4, iclass 34, count 0 2006.169.07:52:07.55#ibcon#about to read 5, iclass 34, count 0 2006.169.07:52:07.55#ibcon#read 5, iclass 34, count 0 2006.169.07:52:07.55#ibcon#about to read 6, iclass 34, count 0 2006.169.07:52:07.55#ibcon#read 6, iclass 34, count 0 2006.169.07:52:07.55#ibcon#end of sib2, iclass 34, count 0 2006.169.07:52:07.55#ibcon#*after write, iclass 34, count 0 2006.169.07:52:07.55#ibcon#*before return 0, iclass 34, count 0 2006.169.07:52:07.55#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.169.07:52:07.55#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.169.07:52:07.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.169.07:52:07.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.169.07:52:07.55$vc4f8/vblo=1,632.99 2006.169.07:52:07.55#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.169.07:52:07.55#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.169.07:52:07.55#ibcon#ireg 17 cls_cnt 0 2006.169.07:52:07.55#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.169.07:52:07.55#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.169.07:52:07.55#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.169.07:52:07.55#ibcon#enter wrdev, iclass 36, count 0 2006.169.07:52:07.55#ibcon#first serial, iclass 36, count 0 2006.169.07:52:07.55#ibcon#enter sib2, iclass 36, count 0 2006.169.07:52:07.55#ibcon#flushed, iclass 36, count 0 2006.169.07:52:07.55#ibcon#about to write, iclass 36, count 0 2006.169.07:52:07.55#ibcon#wrote, iclass 36, count 0 2006.169.07:52:07.55#ibcon#about to read 3, iclass 36, count 0 2006.169.07:52:07.57#ibcon#read 3, iclass 36, count 0 2006.169.07:52:07.57#ibcon#about to read 4, iclass 36, count 0 2006.169.07:52:07.57#ibcon#read 4, iclass 36, count 0 2006.169.07:52:07.57#ibcon#about to read 5, iclass 36, count 0 2006.169.07:52:07.57#ibcon#read 5, iclass 36, count 0 2006.169.07:52:07.57#ibcon#about to read 6, iclass 36, count 0 2006.169.07:52:07.57#ibcon#read 6, iclass 36, count 0 2006.169.07:52:07.57#ibcon#end of sib2, iclass 36, count 0 2006.169.07:52:07.57#ibcon#*mode == 0, iclass 36, count 0 2006.169.07:52:07.57#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.169.07:52:07.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.07:52:07.57#ibcon#*before write, iclass 36, count 0 2006.169.07:52:07.57#ibcon#enter sib2, iclass 36, count 0 2006.169.07:52:07.57#ibcon#flushed, iclass 36, count 0 2006.169.07:52:07.57#ibcon#about to write, iclass 36, count 0 2006.169.07:52:07.57#ibcon#wrote, iclass 36, count 0 2006.169.07:52:07.57#ibcon#about to read 3, iclass 36, count 0 2006.169.07:52:07.61#ibcon#read 3, iclass 36, count 0 2006.169.07:52:07.61#ibcon#about to read 4, iclass 36, count 0 2006.169.07:52:07.61#ibcon#read 4, iclass 36, count 0 2006.169.07:52:07.61#ibcon#about to read 5, iclass 36, count 0 2006.169.07:52:07.61#ibcon#read 5, iclass 36, count 0 2006.169.07:52:07.61#ibcon#about to read 6, iclass 36, count 0 2006.169.07:52:07.61#ibcon#read 6, iclass 36, count 0 2006.169.07:52:07.61#ibcon#end of sib2, iclass 36, count 0 2006.169.07:52:07.61#ibcon#*after write, iclass 36, count 0 2006.169.07:52:07.61#ibcon#*before return 0, iclass 36, count 0 2006.169.07:52:07.61#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.169.07:52:07.61#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.169.07:52:07.61#ibcon#about to clear, iclass 36 cls_cnt 0 2006.169.07:52:07.61#ibcon#cleared, iclass 36 cls_cnt 0 2006.169.07:52:07.61$vc4f8/vb=1,4 2006.169.07:52:07.61#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.169.07:52:07.61#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.169.07:52:07.61#ibcon#ireg 11 cls_cnt 2 2006.169.07:52:07.61#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.169.07:52:07.61#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.169.07:52:07.61#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.169.07:52:07.61#ibcon#enter wrdev, iclass 38, count 2 2006.169.07:52:07.61#ibcon#first serial, iclass 38, count 2 2006.169.07:52:07.61#ibcon#enter sib2, iclass 38, count 2 2006.169.07:52:07.61#ibcon#flushed, iclass 38, count 2 2006.169.07:52:07.61#ibcon#about to write, iclass 38, count 2 2006.169.07:52:07.61#ibcon#wrote, iclass 38, count 2 2006.169.07:52:07.61#ibcon#about to read 3, iclass 38, count 2 2006.169.07:52:07.63#ibcon#read 3, iclass 38, count 2 2006.169.07:52:07.63#ibcon#about to read 4, iclass 38, count 2 2006.169.07:52:07.63#ibcon#read 4, iclass 38, count 2 2006.169.07:52:07.63#ibcon#about to read 5, iclass 38, count 2 2006.169.07:52:07.63#ibcon#read 5, iclass 38, count 2 2006.169.07:52:07.63#ibcon#about to read 6, iclass 38, count 2 2006.169.07:52:07.63#ibcon#read 6, iclass 38, count 2 2006.169.07:52:07.63#ibcon#end of sib2, iclass 38, count 2 2006.169.07:52:07.63#ibcon#*mode == 0, iclass 38, count 2 2006.169.07:52:07.63#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.169.07:52:07.63#ibcon#[27=AT01-04\r\n] 2006.169.07:52:07.63#ibcon#*before write, iclass 38, count 2 2006.169.07:52:07.63#ibcon#enter sib2, iclass 38, count 2 2006.169.07:52:07.63#ibcon#flushed, iclass 38, count 2 2006.169.07:52:07.63#ibcon#about to write, iclass 38, count 2 2006.169.07:52:07.63#ibcon#wrote, iclass 38, count 2 2006.169.07:52:07.63#ibcon#about to read 3, iclass 38, count 2 2006.169.07:52:07.66#ibcon#read 3, iclass 38, count 2 2006.169.07:52:07.66#ibcon#about to read 4, iclass 38, count 2 2006.169.07:52:07.66#ibcon#read 4, iclass 38, count 2 2006.169.07:52:07.66#ibcon#about to read 5, iclass 38, count 2 2006.169.07:52:07.66#ibcon#read 5, iclass 38, count 2 2006.169.07:52:07.66#ibcon#about to read 6, iclass 38, count 2 2006.169.07:52:07.66#ibcon#read 6, iclass 38, count 2 2006.169.07:52:07.66#ibcon#end of sib2, iclass 38, count 2 2006.169.07:52:07.66#ibcon#*after write, iclass 38, count 2 2006.169.07:52:07.66#ibcon#*before return 0, iclass 38, count 2 2006.169.07:52:07.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.169.07:52:07.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.169.07:52:07.66#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.169.07:52:07.66#ibcon#ireg 7 cls_cnt 0 2006.169.07:52:07.66#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.169.07:52:07.78#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.169.07:52:07.78#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.169.07:52:07.78#ibcon#enter wrdev, iclass 38, count 0 2006.169.07:52:07.78#ibcon#first serial, iclass 38, count 0 2006.169.07:52:07.78#ibcon#enter sib2, iclass 38, count 0 2006.169.07:52:07.78#ibcon#flushed, iclass 38, count 0 2006.169.07:52:07.78#ibcon#about to write, iclass 38, count 0 2006.169.07:52:07.78#ibcon#wrote, iclass 38, count 0 2006.169.07:52:07.78#ibcon#about to read 3, iclass 38, count 0 2006.169.07:52:07.80#ibcon#read 3, iclass 38, count 0 2006.169.07:52:07.80#ibcon#about to read 4, iclass 38, count 0 2006.169.07:52:07.80#ibcon#read 4, iclass 38, count 0 2006.169.07:52:07.80#ibcon#about to read 5, iclass 38, count 0 2006.169.07:52:07.80#ibcon#read 5, iclass 38, count 0 2006.169.07:52:07.80#ibcon#about to read 6, iclass 38, count 0 2006.169.07:52:07.80#ibcon#read 6, iclass 38, count 0 2006.169.07:52:07.80#ibcon#end of sib2, iclass 38, count 0 2006.169.07:52:07.80#ibcon#*mode == 0, iclass 38, count 0 2006.169.07:52:07.80#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.169.07:52:07.80#ibcon#[27=USB\r\n] 2006.169.07:52:07.80#ibcon#*before write, iclass 38, count 0 2006.169.07:52:07.80#ibcon#enter sib2, iclass 38, count 0 2006.169.07:52:07.80#ibcon#flushed, iclass 38, count 0 2006.169.07:52:07.80#ibcon#about to write, iclass 38, count 0 2006.169.07:52:07.80#ibcon#wrote, iclass 38, count 0 2006.169.07:52:07.80#ibcon#about to read 3, iclass 38, count 0 2006.169.07:52:07.83#ibcon#read 3, iclass 38, count 0 2006.169.07:52:07.83#ibcon#about to read 4, iclass 38, count 0 2006.169.07:52:07.83#ibcon#read 4, iclass 38, count 0 2006.169.07:52:07.83#ibcon#about to read 5, iclass 38, count 0 2006.169.07:52:07.83#ibcon#read 5, iclass 38, count 0 2006.169.07:52:07.83#ibcon#about to read 6, iclass 38, count 0 2006.169.07:52:07.83#ibcon#read 6, iclass 38, count 0 2006.169.07:52:07.83#ibcon#end of sib2, iclass 38, count 0 2006.169.07:52:07.83#ibcon#*after write, iclass 38, count 0 2006.169.07:52:07.83#ibcon#*before return 0, iclass 38, count 0 2006.169.07:52:07.83#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.169.07:52:07.83#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.169.07:52:07.83#ibcon#about to clear, iclass 38 cls_cnt 0 2006.169.07:52:07.83#ibcon#cleared, iclass 38 cls_cnt 0 2006.169.07:52:07.83$vc4f8/vblo=2,640.99 2006.169.07:52:07.83#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.169.07:52:07.83#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.169.07:52:07.83#ibcon#ireg 17 cls_cnt 0 2006.169.07:52:07.83#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:52:07.83#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:52:07.83#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:52:07.83#ibcon#enter wrdev, iclass 40, count 0 2006.169.07:52:07.83#ibcon#first serial, iclass 40, count 0 2006.169.07:52:07.83#ibcon#enter sib2, iclass 40, count 0 2006.169.07:52:07.83#ibcon#flushed, iclass 40, count 0 2006.169.07:52:07.83#ibcon#about to write, iclass 40, count 0 2006.169.07:52:07.83#ibcon#wrote, iclass 40, count 0 2006.169.07:52:07.83#ibcon#about to read 3, iclass 40, count 0 2006.169.07:52:07.85#ibcon#read 3, iclass 40, count 0 2006.169.07:52:07.85#ibcon#about to read 4, iclass 40, count 0 2006.169.07:52:07.85#ibcon#read 4, iclass 40, count 0 2006.169.07:52:07.85#ibcon#about to read 5, iclass 40, count 0 2006.169.07:52:07.85#ibcon#read 5, iclass 40, count 0 2006.169.07:52:07.85#ibcon#about to read 6, iclass 40, count 0 2006.169.07:52:07.85#ibcon#read 6, iclass 40, count 0 2006.169.07:52:07.85#ibcon#end of sib2, iclass 40, count 0 2006.169.07:52:07.85#ibcon#*mode == 0, iclass 40, count 0 2006.169.07:52:07.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.169.07:52:07.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.07:52:07.85#ibcon#*before write, iclass 40, count 0 2006.169.07:52:07.85#ibcon#enter sib2, iclass 40, count 0 2006.169.07:52:07.85#ibcon#flushed, iclass 40, count 0 2006.169.07:52:07.85#ibcon#about to write, iclass 40, count 0 2006.169.07:52:07.85#ibcon#wrote, iclass 40, count 0 2006.169.07:52:07.85#ibcon#about to read 3, iclass 40, count 0 2006.169.07:52:07.89#ibcon#read 3, iclass 40, count 0 2006.169.07:52:07.89#ibcon#about to read 4, iclass 40, count 0 2006.169.07:52:07.89#ibcon#read 4, iclass 40, count 0 2006.169.07:52:07.89#ibcon#about to read 5, iclass 40, count 0 2006.169.07:52:07.89#ibcon#read 5, iclass 40, count 0 2006.169.07:52:07.89#ibcon#about to read 6, iclass 40, count 0 2006.169.07:52:07.89#ibcon#read 6, iclass 40, count 0 2006.169.07:52:07.89#ibcon#end of sib2, iclass 40, count 0 2006.169.07:52:07.89#ibcon#*after write, iclass 40, count 0 2006.169.07:52:07.89#ibcon#*before return 0, iclass 40, count 0 2006.169.07:52:07.89#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:52:07.89#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:52:07.89#ibcon#about to clear, iclass 40 cls_cnt 0 2006.169.07:52:07.89#ibcon#cleared, iclass 40 cls_cnt 0 2006.169.07:52:07.89$vc4f8/vb=2,4 2006.169.07:52:07.89#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.169.07:52:07.89#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.169.07:52:07.89#ibcon#ireg 11 cls_cnt 2 2006.169.07:52:07.89#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.169.07:52:07.96#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.169.07:52:07.96#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.169.07:52:07.96#ibcon#enter wrdev, iclass 4, count 2 2006.169.07:52:07.96#ibcon#first serial, iclass 4, count 2 2006.169.07:52:07.96#ibcon#enter sib2, iclass 4, count 2 2006.169.07:52:07.96#ibcon#flushed, iclass 4, count 2 2006.169.07:52:07.96#ibcon#about to write, iclass 4, count 2 2006.169.07:52:07.96#ibcon#wrote, iclass 4, count 2 2006.169.07:52:07.96#ibcon#about to read 3, iclass 4, count 2 2006.169.07:52:07.97#ibcon#read 3, iclass 4, count 2 2006.169.07:52:07.97#ibcon#about to read 4, iclass 4, count 2 2006.169.07:52:07.97#ibcon#read 4, iclass 4, count 2 2006.169.07:52:07.97#ibcon#about to read 5, iclass 4, count 2 2006.169.07:52:07.97#ibcon#read 5, iclass 4, count 2 2006.169.07:52:07.97#ibcon#about to read 6, iclass 4, count 2 2006.169.07:52:07.97#ibcon#read 6, iclass 4, count 2 2006.169.07:52:07.97#ibcon#end of sib2, iclass 4, count 2 2006.169.07:52:07.97#ibcon#*mode == 0, iclass 4, count 2 2006.169.07:52:07.97#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.169.07:52:07.97#ibcon#[27=AT02-04\r\n] 2006.169.07:52:07.97#ibcon#*before write, iclass 4, count 2 2006.169.07:52:07.97#ibcon#enter sib2, iclass 4, count 2 2006.169.07:52:07.97#ibcon#flushed, iclass 4, count 2 2006.169.07:52:07.97#ibcon#about to write, iclass 4, count 2 2006.169.07:52:07.97#ibcon#wrote, iclass 4, count 2 2006.169.07:52:07.97#ibcon#about to read 3, iclass 4, count 2 2006.169.07:52:08.00#ibcon#read 3, iclass 4, count 2 2006.169.07:52:08.00#ibcon#about to read 4, iclass 4, count 2 2006.169.07:52:08.00#ibcon#read 4, iclass 4, count 2 2006.169.07:52:08.00#ibcon#about to read 5, iclass 4, count 2 2006.169.07:52:08.00#ibcon#read 5, iclass 4, count 2 2006.169.07:52:08.00#ibcon#about to read 6, iclass 4, count 2 2006.169.07:52:08.00#ibcon#read 6, iclass 4, count 2 2006.169.07:52:08.00#ibcon#end of sib2, iclass 4, count 2 2006.169.07:52:08.00#ibcon#*after write, iclass 4, count 2 2006.169.07:52:08.00#ibcon#*before return 0, iclass 4, count 2 2006.169.07:52:08.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.169.07:52:08.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.169.07:52:08.00#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.169.07:52:08.00#ibcon#ireg 7 cls_cnt 0 2006.169.07:52:08.00#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.169.07:52:08.12#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.169.07:52:08.12#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.169.07:52:08.12#ibcon#enter wrdev, iclass 4, count 0 2006.169.07:52:08.12#ibcon#first serial, iclass 4, count 0 2006.169.07:52:08.12#ibcon#enter sib2, iclass 4, count 0 2006.169.07:52:08.12#ibcon#flushed, iclass 4, count 0 2006.169.07:52:08.12#ibcon#about to write, iclass 4, count 0 2006.169.07:52:08.12#ibcon#wrote, iclass 4, count 0 2006.169.07:52:08.12#ibcon#about to read 3, iclass 4, count 0 2006.169.07:52:08.14#ibcon#read 3, iclass 4, count 0 2006.169.07:52:08.14#ibcon#about to read 4, iclass 4, count 0 2006.169.07:52:08.14#ibcon#read 4, iclass 4, count 0 2006.169.07:52:08.14#ibcon#about to read 5, iclass 4, count 0 2006.169.07:52:08.14#ibcon#read 5, iclass 4, count 0 2006.169.07:52:08.14#ibcon#about to read 6, iclass 4, count 0 2006.169.07:52:08.14#ibcon#read 6, iclass 4, count 0 2006.169.07:52:08.14#ibcon#end of sib2, iclass 4, count 0 2006.169.07:52:08.14#ibcon#*mode == 0, iclass 4, count 0 2006.169.07:52:08.14#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.169.07:52:08.14#ibcon#[27=USB\r\n] 2006.169.07:52:08.14#ibcon#*before write, iclass 4, count 0 2006.169.07:52:08.14#ibcon#enter sib2, iclass 4, count 0 2006.169.07:52:08.14#ibcon#flushed, iclass 4, count 0 2006.169.07:52:08.14#ibcon#about to write, iclass 4, count 0 2006.169.07:52:08.14#ibcon#wrote, iclass 4, count 0 2006.169.07:52:08.14#ibcon#about to read 3, iclass 4, count 0 2006.169.07:52:08.17#ibcon#read 3, iclass 4, count 0 2006.169.07:52:08.17#ibcon#about to read 4, iclass 4, count 0 2006.169.07:52:08.17#ibcon#read 4, iclass 4, count 0 2006.169.07:52:08.17#ibcon#about to read 5, iclass 4, count 0 2006.169.07:52:08.17#ibcon#read 5, iclass 4, count 0 2006.169.07:52:08.17#ibcon#about to read 6, iclass 4, count 0 2006.169.07:52:08.17#ibcon#read 6, iclass 4, count 0 2006.169.07:52:08.17#ibcon#end of sib2, iclass 4, count 0 2006.169.07:52:08.17#ibcon#*after write, iclass 4, count 0 2006.169.07:52:08.17#ibcon#*before return 0, iclass 4, count 0 2006.169.07:52:08.17#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.169.07:52:08.17#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.169.07:52:08.17#ibcon#about to clear, iclass 4 cls_cnt 0 2006.169.07:52:08.17#ibcon#cleared, iclass 4 cls_cnt 0 2006.169.07:52:08.17$vc4f8/vblo=3,656.99 2006.169.07:52:08.17#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.169.07:52:08.17#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.169.07:52:08.17#ibcon#ireg 17 cls_cnt 0 2006.169.07:52:08.17#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:52:08.17#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:52:08.17#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:52:08.17#ibcon#enter wrdev, iclass 6, count 0 2006.169.07:52:08.17#ibcon#first serial, iclass 6, count 0 2006.169.07:52:08.17#ibcon#enter sib2, iclass 6, count 0 2006.169.07:52:08.17#ibcon#flushed, iclass 6, count 0 2006.169.07:52:08.17#ibcon#about to write, iclass 6, count 0 2006.169.07:52:08.17#ibcon#wrote, iclass 6, count 0 2006.169.07:52:08.17#ibcon#about to read 3, iclass 6, count 0 2006.169.07:52:08.19#ibcon#read 3, iclass 6, count 0 2006.169.07:52:08.19#ibcon#about to read 4, iclass 6, count 0 2006.169.07:52:08.19#ibcon#read 4, iclass 6, count 0 2006.169.07:52:08.19#ibcon#about to read 5, iclass 6, count 0 2006.169.07:52:08.19#ibcon#read 5, iclass 6, count 0 2006.169.07:52:08.19#ibcon#about to read 6, iclass 6, count 0 2006.169.07:52:08.19#ibcon#read 6, iclass 6, count 0 2006.169.07:52:08.19#ibcon#end of sib2, iclass 6, count 0 2006.169.07:52:08.19#ibcon#*mode == 0, iclass 6, count 0 2006.169.07:52:08.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.169.07:52:08.19#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.07:52:08.19#ibcon#*before write, iclass 6, count 0 2006.169.07:52:08.19#ibcon#enter sib2, iclass 6, count 0 2006.169.07:52:08.19#ibcon#flushed, iclass 6, count 0 2006.169.07:52:08.19#ibcon#about to write, iclass 6, count 0 2006.169.07:52:08.19#ibcon#wrote, iclass 6, count 0 2006.169.07:52:08.19#ibcon#about to read 3, iclass 6, count 0 2006.169.07:52:08.23#ibcon#read 3, iclass 6, count 0 2006.169.07:52:08.23#ibcon#about to read 4, iclass 6, count 0 2006.169.07:52:08.23#ibcon#read 4, iclass 6, count 0 2006.169.07:52:08.23#ibcon#about to read 5, iclass 6, count 0 2006.169.07:52:08.23#ibcon#read 5, iclass 6, count 0 2006.169.07:52:08.23#ibcon#about to read 6, iclass 6, count 0 2006.169.07:52:08.23#ibcon#read 6, iclass 6, count 0 2006.169.07:52:08.23#ibcon#end of sib2, iclass 6, count 0 2006.169.07:52:08.23#ibcon#*after write, iclass 6, count 0 2006.169.07:52:08.23#ibcon#*before return 0, iclass 6, count 0 2006.169.07:52:08.23#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:52:08.23#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.169.07:52:08.23#ibcon#about to clear, iclass 6 cls_cnt 0 2006.169.07:52:08.23#ibcon#cleared, iclass 6 cls_cnt 0 2006.169.07:52:08.23$vc4f8/vb=3,4 2006.169.07:52:08.23#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.169.07:52:08.23#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.169.07:52:08.23#ibcon#ireg 11 cls_cnt 2 2006.169.07:52:08.23#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.169.07:52:08.29#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.169.07:52:08.29#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.169.07:52:08.29#ibcon#enter wrdev, iclass 10, count 2 2006.169.07:52:08.29#ibcon#first serial, iclass 10, count 2 2006.169.07:52:08.29#ibcon#enter sib2, iclass 10, count 2 2006.169.07:52:08.29#ibcon#flushed, iclass 10, count 2 2006.169.07:52:08.29#ibcon#about to write, iclass 10, count 2 2006.169.07:52:08.29#ibcon#wrote, iclass 10, count 2 2006.169.07:52:08.29#ibcon#about to read 3, iclass 10, count 2 2006.169.07:52:08.31#ibcon#read 3, iclass 10, count 2 2006.169.07:52:08.31#ibcon#about to read 4, iclass 10, count 2 2006.169.07:52:08.31#ibcon#read 4, iclass 10, count 2 2006.169.07:52:08.31#ibcon#about to read 5, iclass 10, count 2 2006.169.07:52:08.31#ibcon#read 5, iclass 10, count 2 2006.169.07:52:08.31#ibcon#about to read 6, iclass 10, count 2 2006.169.07:52:08.31#ibcon#read 6, iclass 10, count 2 2006.169.07:52:08.31#ibcon#end of sib2, iclass 10, count 2 2006.169.07:52:08.31#ibcon#*mode == 0, iclass 10, count 2 2006.169.07:52:08.31#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.169.07:52:08.31#ibcon#[27=AT03-04\r\n] 2006.169.07:52:08.31#ibcon#*before write, iclass 10, count 2 2006.169.07:52:08.31#ibcon#enter sib2, iclass 10, count 2 2006.169.07:52:08.31#ibcon#flushed, iclass 10, count 2 2006.169.07:52:08.31#ibcon#about to write, iclass 10, count 2 2006.169.07:52:08.31#ibcon#wrote, iclass 10, count 2 2006.169.07:52:08.31#ibcon#about to read 3, iclass 10, count 2 2006.169.07:52:08.34#ibcon#read 3, iclass 10, count 2 2006.169.07:52:08.34#ibcon#about to read 4, iclass 10, count 2 2006.169.07:52:08.34#ibcon#read 4, iclass 10, count 2 2006.169.07:52:08.34#ibcon#about to read 5, iclass 10, count 2 2006.169.07:52:08.34#ibcon#read 5, iclass 10, count 2 2006.169.07:52:08.34#ibcon#about to read 6, iclass 10, count 2 2006.169.07:52:08.34#ibcon#read 6, iclass 10, count 2 2006.169.07:52:08.34#ibcon#end of sib2, iclass 10, count 2 2006.169.07:52:08.34#ibcon#*after write, iclass 10, count 2 2006.169.07:52:08.34#ibcon#*before return 0, iclass 10, count 2 2006.169.07:52:08.34#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.169.07:52:08.34#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.169.07:52:08.34#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.169.07:52:08.34#ibcon#ireg 7 cls_cnt 0 2006.169.07:52:08.34#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.169.07:52:08.46#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.169.07:52:08.46#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.169.07:52:08.46#ibcon#enter wrdev, iclass 10, count 0 2006.169.07:52:08.46#ibcon#first serial, iclass 10, count 0 2006.169.07:52:08.46#ibcon#enter sib2, iclass 10, count 0 2006.169.07:52:08.46#ibcon#flushed, iclass 10, count 0 2006.169.07:52:08.46#ibcon#about to write, iclass 10, count 0 2006.169.07:52:08.46#ibcon#wrote, iclass 10, count 0 2006.169.07:52:08.46#ibcon#about to read 3, iclass 10, count 0 2006.169.07:52:08.48#ibcon#read 3, iclass 10, count 0 2006.169.07:52:08.48#ibcon#about to read 4, iclass 10, count 0 2006.169.07:52:08.48#ibcon#read 4, iclass 10, count 0 2006.169.07:52:08.48#ibcon#about to read 5, iclass 10, count 0 2006.169.07:52:08.48#ibcon#read 5, iclass 10, count 0 2006.169.07:52:08.48#ibcon#about to read 6, iclass 10, count 0 2006.169.07:52:08.48#ibcon#read 6, iclass 10, count 0 2006.169.07:52:08.48#ibcon#end of sib2, iclass 10, count 0 2006.169.07:52:08.48#ibcon#*mode == 0, iclass 10, count 0 2006.169.07:52:08.48#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.169.07:52:08.48#ibcon#[27=USB\r\n] 2006.169.07:52:08.48#ibcon#*before write, iclass 10, count 0 2006.169.07:52:08.48#ibcon#enter sib2, iclass 10, count 0 2006.169.07:52:08.48#ibcon#flushed, iclass 10, count 0 2006.169.07:52:08.48#ibcon#about to write, iclass 10, count 0 2006.169.07:52:08.48#ibcon#wrote, iclass 10, count 0 2006.169.07:52:08.48#ibcon#about to read 3, iclass 10, count 0 2006.169.07:52:08.51#ibcon#read 3, iclass 10, count 0 2006.169.07:52:08.51#ibcon#about to read 4, iclass 10, count 0 2006.169.07:52:08.51#ibcon#read 4, iclass 10, count 0 2006.169.07:52:08.51#ibcon#about to read 5, iclass 10, count 0 2006.169.07:52:08.51#ibcon#read 5, iclass 10, count 0 2006.169.07:52:08.51#ibcon#about to read 6, iclass 10, count 0 2006.169.07:52:08.51#ibcon#read 6, iclass 10, count 0 2006.169.07:52:08.51#ibcon#end of sib2, iclass 10, count 0 2006.169.07:52:08.51#ibcon#*after write, iclass 10, count 0 2006.169.07:52:08.51#ibcon#*before return 0, iclass 10, count 0 2006.169.07:52:08.51#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.169.07:52:08.51#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.169.07:52:08.51#ibcon#about to clear, iclass 10 cls_cnt 0 2006.169.07:52:08.51#ibcon#cleared, iclass 10 cls_cnt 0 2006.169.07:52:08.51$vc4f8/vblo=4,712.99 2006.169.07:52:08.51#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.169.07:52:08.51#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.169.07:52:08.51#ibcon#ireg 17 cls_cnt 0 2006.169.07:52:08.51#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.169.07:52:08.51#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.169.07:52:08.51#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.169.07:52:08.51#ibcon#enter wrdev, iclass 12, count 0 2006.169.07:52:08.51#ibcon#first serial, iclass 12, count 0 2006.169.07:52:08.51#ibcon#enter sib2, iclass 12, count 0 2006.169.07:52:08.51#ibcon#flushed, iclass 12, count 0 2006.169.07:52:08.51#ibcon#about to write, iclass 12, count 0 2006.169.07:52:08.51#ibcon#wrote, iclass 12, count 0 2006.169.07:52:08.51#ibcon#about to read 3, iclass 12, count 0 2006.169.07:52:08.53#ibcon#read 3, iclass 12, count 0 2006.169.07:52:08.53#ibcon#about to read 4, iclass 12, count 0 2006.169.07:52:08.53#ibcon#read 4, iclass 12, count 0 2006.169.07:52:08.53#ibcon#about to read 5, iclass 12, count 0 2006.169.07:52:08.53#ibcon#read 5, iclass 12, count 0 2006.169.07:52:08.53#ibcon#about to read 6, iclass 12, count 0 2006.169.07:52:08.53#ibcon#read 6, iclass 12, count 0 2006.169.07:52:08.53#ibcon#end of sib2, iclass 12, count 0 2006.169.07:52:08.53#ibcon#*mode == 0, iclass 12, count 0 2006.169.07:52:08.53#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.169.07:52:08.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.07:52:08.53#ibcon#*before write, iclass 12, count 0 2006.169.07:52:08.53#ibcon#enter sib2, iclass 12, count 0 2006.169.07:52:08.53#ibcon#flushed, iclass 12, count 0 2006.169.07:52:08.53#ibcon#about to write, iclass 12, count 0 2006.169.07:52:08.53#ibcon#wrote, iclass 12, count 0 2006.169.07:52:08.53#ibcon#about to read 3, iclass 12, count 0 2006.169.07:52:08.57#ibcon#read 3, iclass 12, count 0 2006.169.07:52:08.57#ibcon#about to read 4, iclass 12, count 0 2006.169.07:52:08.57#ibcon#read 4, iclass 12, count 0 2006.169.07:52:08.57#ibcon#about to read 5, iclass 12, count 0 2006.169.07:52:08.57#ibcon#read 5, iclass 12, count 0 2006.169.07:52:08.57#ibcon#about to read 6, iclass 12, count 0 2006.169.07:52:08.57#ibcon#read 6, iclass 12, count 0 2006.169.07:52:08.57#ibcon#end of sib2, iclass 12, count 0 2006.169.07:52:08.57#ibcon#*after write, iclass 12, count 0 2006.169.07:52:08.57#ibcon#*before return 0, iclass 12, count 0 2006.169.07:52:08.57#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.169.07:52:08.57#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.169.07:52:08.57#ibcon#about to clear, iclass 12 cls_cnt 0 2006.169.07:52:08.57#ibcon#cleared, iclass 12 cls_cnt 0 2006.169.07:52:08.57$vc4f8/vb=4,4 2006.169.07:52:08.57#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.169.07:52:08.57#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.169.07:52:08.57#ibcon#ireg 11 cls_cnt 2 2006.169.07:52:08.57#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.169.07:52:08.64#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.169.07:52:08.64#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.169.07:52:08.64#ibcon#enter wrdev, iclass 14, count 2 2006.169.07:52:08.64#ibcon#first serial, iclass 14, count 2 2006.169.07:52:08.64#ibcon#enter sib2, iclass 14, count 2 2006.169.07:52:08.64#ibcon#flushed, iclass 14, count 2 2006.169.07:52:08.64#ibcon#about to write, iclass 14, count 2 2006.169.07:52:08.64#ibcon#wrote, iclass 14, count 2 2006.169.07:52:08.64#ibcon#about to read 3, iclass 14, count 2 2006.169.07:52:08.65#ibcon#read 3, iclass 14, count 2 2006.169.07:52:08.65#ibcon#about to read 4, iclass 14, count 2 2006.169.07:52:08.65#ibcon#read 4, iclass 14, count 2 2006.169.07:52:08.65#ibcon#about to read 5, iclass 14, count 2 2006.169.07:52:08.65#ibcon#read 5, iclass 14, count 2 2006.169.07:52:08.65#ibcon#about to read 6, iclass 14, count 2 2006.169.07:52:08.65#ibcon#read 6, iclass 14, count 2 2006.169.07:52:08.65#ibcon#end of sib2, iclass 14, count 2 2006.169.07:52:08.65#ibcon#*mode == 0, iclass 14, count 2 2006.169.07:52:08.65#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.169.07:52:08.65#ibcon#[27=AT04-04\r\n] 2006.169.07:52:08.65#ibcon#*before write, iclass 14, count 2 2006.169.07:52:08.65#ibcon#enter sib2, iclass 14, count 2 2006.169.07:52:08.65#ibcon#flushed, iclass 14, count 2 2006.169.07:52:08.65#ibcon#about to write, iclass 14, count 2 2006.169.07:52:08.65#ibcon#wrote, iclass 14, count 2 2006.169.07:52:08.65#ibcon#about to read 3, iclass 14, count 2 2006.169.07:52:08.68#ibcon#read 3, iclass 14, count 2 2006.169.07:52:08.68#ibcon#about to read 4, iclass 14, count 2 2006.169.07:52:08.68#ibcon#read 4, iclass 14, count 2 2006.169.07:52:08.68#ibcon#about to read 5, iclass 14, count 2 2006.169.07:52:08.68#ibcon#read 5, iclass 14, count 2 2006.169.07:52:08.68#ibcon#about to read 6, iclass 14, count 2 2006.169.07:52:08.68#ibcon#read 6, iclass 14, count 2 2006.169.07:52:08.68#ibcon#end of sib2, iclass 14, count 2 2006.169.07:52:08.68#ibcon#*after write, iclass 14, count 2 2006.169.07:52:08.68#ibcon#*before return 0, iclass 14, count 2 2006.169.07:52:08.68#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.169.07:52:08.68#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.169.07:52:08.68#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.169.07:52:08.68#ibcon#ireg 7 cls_cnt 0 2006.169.07:52:08.68#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.169.07:52:08.80#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.169.07:52:08.80#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.169.07:52:08.80#ibcon#enter wrdev, iclass 14, count 0 2006.169.07:52:08.80#ibcon#first serial, iclass 14, count 0 2006.169.07:52:08.80#ibcon#enter sib2, iclass 14, count 0 2006.169.07:52:08.80#ibcon#flushed, iclass 14, count 0 2006.169.07:52:08.80#ibcon#about to write, iclass 14, count 0 2006.169.07:52:08.80#ibcon#wrote, iclass 14, count 0 2006.169.07:52:08.80#ibcon#about to read 3, iclass 14, count 0 2006.169.07:52:08.82#ibcon#read 3, iclass 14, count 0 2006.169.07:52:08.82#ibcon#about to read 4, iclass 14, count 0 2006.169.07:52:08.82#ibcon#read 4, iclass 14, count 0 2006.169.07:52:08.82#ibcon#about to read 5, iclass 14, count 0 2006.169.07:52:08.82#ibcon#read 5, iclass 14, count 0 2006.169.07:52:08.82#ibcon#about to read 6, iclass 14, count 0 2006.169.07:52:08.82#ibcon#read 6, iclass 14, count 0 2006.169.07:52:08.82#ibcon#end of sib2, iclass 14, count 0 2006.169.07:52:08.82#ibcon#*mode == 0, iclass 14, count 0 2006.169.07:52:08.82#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.169.07:52:08.82#ibcon#[27=USB\r\n] 2006.169.07:52:08.82#ibcon#*before write, iclass 14, count 0 2006.169.07:52:08.82#ibcon#enter sib2, iclass 14, count 0 2006.169.07:52:08.82#ibcon#flushed, iclass 14, count 0 2006.169.07:52:08.82#ibcon#about to write, iclass 14, count 0 2006.169.07:52:08.82#ibcon#wrote, iclass 14, count 0 2006.169.07:52:08.82#ibcon#about to read 3, iclass 14, count 0 2006.169.07:52:08.85#ibcon#read 3, iclass 14, count 0 2006.169.07:52:08.85#ibcon#about to read 4, iclass 14, count 0 2006.169.07:52:08.85#ibcon#read 4, iclass 14, count 0 2006.169.07:52:08.85#ibcon#about to read 5, iclass 14, count 0 2006.169.07:52:08.85#ibcon#read 5, iclass 14, count 0 2006.169.07:52:08.85#ibcon#about to read 6, iclass 14, count 0 2006.169.07:52:08.85#ibcon#read 6, iclass 14, count 0 2006.169.07:52:08.85#ibcon#end of sib2, iclass 14, count 0 2006.169.07:52:08.85#ibcon#*after write, iclass 14, count 0 2006.169.07:52:08.85#ibcon#*before return 0, iclass 14, count 0 2006.169.07:52:08.85#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.169.07:52:08.85#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.169.07:52:08.85#ibcon#about to clear, iclass 14 cls_cnt 0 2006.169.07:52:08.85#ibcon#cleared, iclass 14 cls_cnt 0 2006.169.07:52:08.85$vc4f8/vblo=5,744.99 2006.169.07:52:08.85#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.169.07:52:08.85#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.169.07:52:08.85#ibcon#ireg 17 cls_cnt 0 2006.169.07:52:08.85#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:52:08.85#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:52:08.85#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:52:08.85#ibcon#enter wrdev, iclass 16, count 0 2006.169.07:52:08.85#ibcon#first serial, iclass 16, count 0 2006.169.07:52:08.85#ibcon#enter sib2, iclass 16, count 0 2006.169.07:52:08.85#ibcon#flushed, iclass 16, count 0 2006.169.07:52:08.85#ibcon#about to write, iclass 16, count 0 2006.169.07:52:08.85#ibcon#wrote, iclass 16, count 0 2006.169.07:52:08.85#ibcon#about to read 3, iclass 16, count 0 2006.169.07:52:08.87#ibcon#read 3, iclass 16, count 0 2006.169.07:52:08.87#ibcon#about to read 4, iclass 16, count 0 2006.169.07:52:08.87#ibcon#read 4, iclass 16, count 0 2006.169.07:52:08.87#ibcon#about to read 5, iclass 16, count 0 2006.169.07:52:08.87#ibcon#read 5, iclass 16, count 0 2006.169.07:52:08.87#ibcon#about to read 6, iclass 16, count 0 2006.169.07:52:08.87#ibcon#read 6, iclass 16, count 0 2006.169.07:52:08.87#ibcon#end of sib2, iclass 16, count 0 2006.169.07:52:08.87#ibcon#*mode == 0, iclass 16, count 0 2006.169.07:52:08.87#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.169.07:52:08.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.07:52:08.87#ibcon#*before write, iclass 16, count 0 2006.169.07:52:08.87#ibcon#enter sib2, iclass 16, count 0 2006.169.07:52:08.87#ibcon#flushed, iclass 16, count 0 2006.169.07:52:08.87#ibcon#about to write, iclass 16, count 0 2006.169.07:52:08.87#ibcon#wrote, iclass 16, count 0 2006.169.07:52:08.87#ibcon#about to read 3, iclass 16, count 0 2006.169.07:52:08.91#ibcon#read 3, iclass 16, count 0 2006.169.07:52:08.91#ibcon#about to read 4, iclass 16, count 0 2006.169.07:52:08.91#ibcon#read 4, iclass 16, count 0 2006.169.07:52:08.91#ibcon#about to read 5, iclass 16, count 0 2006.169.07:52:08.91#ibcon#read 5, iclass 16, count 0 2006.169.07:52:08.91#ibcon#about to read 6, iclass 16, count 0 2006.169.07:52:08.91#ibcon#read 6, iclass 16, count 0 2006.169.07:52:08.91#ibcon#end of sib2, iclass 16, count 0 2006.169.07:52:08.91#ibcon#*after write, iclass 16, count 0 2006.169.07:52:08.91#ibcon#*before return 0, iclass 16, count 0 2006.169.07:52:08.91#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:52:08.91#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.169.07:52:08.91#ibcon#about to clear, iclass 16 cls_cnt 0 2006.169.07:52:08.91#ibcon#cleared, iclass 16 cls_cnt 0 2006.169.07:52:08.91$vc4f8/vb=5,4 2006.169.07:52:08.91#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.169.07:52:08.91#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.169.07:52:08.91#ibcon#ireg 11 cls_cnt 2 2006.169.07:52:08.91#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.169.07:52:08.97#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.169.07:52:08.97#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.169.07:52:08.97#ibcon#enter wrdev, iclass 18, count 2 2006.169.07:52:08.97#ibcon#first serial, iclass 18, count 2 2006.169.07:52:08.97#ibcon#enter sib2, iclass 18, count 2 2006.169.07:52:08.97#ibcon#flushed, iclass 18, count 2 2006.169.07:52:08.97#ibcon#about to write, iclass 18, count 2 2006.169.07:52:08.97#ibcon#wrote, iclass 18, count 2 2006.169.07:52:08.97#ibcon#about to read 3, iclass 18, count 2 2006.169.07:52:08.99#ibcon#read 3, iclass 18, count 2 2006.169.07:52:08.99#ibcon#about to read 4, iclass 18, count 2 2006.169.07:52:08.99#ibcon#read 4, iclass 18, count 2 2006.169.07:52:08.99#ibcon#about to read 5, iclass 18, count 2 2006.169.07:52:08.99#ibcon#read 5, iclass 18, count 2 2006.169.07:52:08.99#ibcon#about to read 6, iclass 18, count 2 2006.169.07:52:08.99#ibcon#read 6, iclass 18, count 2 2006.169.07:52:08.99#ibcon#end of sib2, iclass 18, count 2 2006.169.07:52:08.99#ibcon#*mode == 0, iclass 18, count 2 2006.169.07:52:08.99#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.169.07:52:08.99#ibcon#[27=AT05-04\r\n] 2006.169.07:52:08.99#ibcon#*before write, iclass 18, count 2 2006.169.07:52:08.99#ibcon#enter sib2, iclass 18, count 2 2006.169.07:52:08.99#ibcon#flushed, iclass 18, count 2 2006.169.07:52:08.99#ibcon#about to write, iclass 18, count 2 2006.169.07:52:08.99#ibcon#wrote, iclass 18, count 2 2006.169.07:52:08.99#ibcon#about to read 3, iclass 18, count 2 2006.169.07:52:09.02#ibcon#read 3, iclass 18, count 2 2006.169.07:52:09.02#ibcon#about to read 4, iclass 18, count 2 2006.169.07:52:09.02#ibcon#read 4, iclass 18, count 2 2006.169.07:52:09.02#ibcon#about to read 5, iclass 18, count 2 2006.169.07:52:09.02#ibcon#read 5, iclass 18, count 2 2006.169.07:52:09.02#ibcon#about to read 6, iclass 18, count 2 2006.169.07:52:09.02#ibcon#read 6, iclass 18, count 2 2006.169.07:52:09.02#ibcon#end of sib2, iclass 18, count 2 2006.169.07:52:09.02#ibcon#*after write, iclass 18, count 2 2006.169.07:52:09.02#ibcon#*before return 0, iclass 18, count 2 2006.169.07:52:09.02#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.169.07:52:09.02#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.169.07:52:09.02#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.169.07:52:09.02#ibcon#ireg 7 cls_cnt 0 2006.169.07:52:09.02#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.169.07:52:09.14#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.169.07:52:09.14#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.169.07:52:09.14#ibcon#enter wrdev, iclass 18, count 0 2006.169.07:52:09.14#ibcon#first serial, iclass 18, count 0 2006.169.07:52:09.14#ibcon#enter sib2, iclass 18, count 0 2006.169.07:52:09.14#ibcon#flushed, iclass 18, count 0 2006.169.07:52:09.14#ibcon#about to write, iclass 18, count 0 2006.169.07:52:09.14#ibcon#wrote, iclass 18, count 0 2006.169.07:52:09.14#ibcon#about to read 3, iclass 18, count 0 2006.169.07:52:09.16#ibcon#read 3, iclass 18, count 0 2006.169.07:52:09.16#ibcon#about to read 4, iclass 18, count 0 2006.169.07:52:09.16#ibcon#read 4, iclass 18, count 0 2006.169.07:52:09.16#ibcon#about to read 5, iclass 18, count 0 2006.169.07:52:09.16#ibcon#read 5, iclass 18, count 0 2006.169.07:52:09.16#ibcon#about to read 6, iclass 18, count 0 2006.169.07:52:09.16#ibcon#read 6, iclass 18, count 0 2006.169.07:52:09.16#ibcon#end of sib2, iclass 18, count 0 2006.169.07:52:09.16#ibcon#*mode == 0, iclass 18, count 0 2006.169.07:52:09.16#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.169.07:52:09.16#ibcon#[27=USB\r\n] 2006.169.07:52:09.16#ibcon#*before write, iclass 18, count 0 2006.169.07:52:09.16#ibcon#enter sib2, iclass 18, count 0 2006.169.07:52:09.16#ibcon#flushed, iclass 18, count 0 2006.169.07:52:09.16#ibcon#about to write, iclass 18, count 0 2006.169.07:52:09.16#ibcon#wrote, iclass 18, count 0 2006.169.07:52:09.16#ibcon#about to read 3, iclass 18, count 0 2006.169.07:52:09.19#ibcon#read 3, iclass 18, count 0 2006.169.07:52:09.19#ibcon#about to read 4, iclass 18, count 0 2006.169.07:52:09.19#ibcon#read 4, iclass 18, count 0 2006.169.07:52:09.19#ibcon#about to read 5, iclass 18, count 0 2006.169.07:52:09.19#ibcon#read 5, iclass 18, count 0 2006.169.07:52:09.19#ibcon#about to read 6, iclass 18, count 0 2006.169.07:52:09.19#ibcon#read 6, iclass 18, count 0 2006.169.07:52:09.19#ibcon#end of sib2, iclass 18, count 0 2006.169.07:52:09.19#ibcon#*after write, iclass 18, count 0 2006.169.07:52:09.19#ibcon#*before return 0, iclass 18, count 0 2006.169.07:52:09.19#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.169.07:52:09.19#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.169.07:52:09.19#ibcon#about to clear, iclass 18 cls_cnt 0 2006.169.07:52:09.19#ibcon#cleared, iclass 18 cls_cnt 0 2006.169.07:52:09.19$vc4f8/vblo=6,752.99 2006.169.07:52:09.19#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.169.07:52:09.19#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.169.07:52:09.19#ibcon#ireg 17 cls_cnt 0 2006.169.07:52:09.19#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.169.07:52:09.19#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.169.07:52:09.19#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.169.07:52:09.19#ibcon#enter wrdev, iclass 20, count 0 2006.169.07:52:09.19#ibcon#first serial, iclass 20, count 0 2006.169.07:52:09.19#ibcon#enter sib2, iclass 20, count 0 2006.169.07:52:09.19#ibcon#flushed, iclass 20, count 0 2006.169.07:52:09.19#ibcon#about to write, iclass 20, count 0 2006.169.07:52:09.19#ibcon#wrote, iclass 20, count 0 2006.169.07:52:09.19#ibcon#about to read 3, iclass 20, count 0 2006.169.07:52:09.21#ibcon#read 3, iclass 20, count 0 2006.169.07:52:09.21#ibcon#about to read 4, iclass 20, count 0 2006.169.07:52:09.21#ibcon#read 4, iclass 20, count 0 2006.169.07:52:09.21#ibcon#about to read 5, iclass 20, count 0 2006.169.07:52:09.21#ibcon#read 5, iclass 20, count 0 2006.169.07:52:09.21#ibcon#about to read 6, iclass 20, count 0 2006.169.07:52:09.21#ibcon#read 6, iclass 20, count 0 2006.169.07:52:09.21#ibcon#end of sib2, iclass 20, count 0 2006.169.07:52:09.21#ibcon#*mode == 0, iclass 20, count 0 2006.169.07:52:09.21#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.169.07:52:09.21#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.07:52:09.21#ibcon#*before write, iclass 20, count 0 2006.169.07:52:09.21#ibcon#enter sib2, iclass 20, count 0 2006.169.07:52:09.21#ibcon#flushed, iclass 20, count 0 2006.169.07:52:09.21#ibcon#about to write, iclass 20, count 0 2006.169.07:52:09.21#ibcon#wrote, iclass 20, count 0 2006.169.07:52:09.21#ibcon#about to read 3, iclass 20, count 0 2006.169.07:52:09.25#ibcon#read 3, iclass 20, count 0 2006.169.07:52:09.25#ibcon#about to read 4, iclass 20, count 0 2006.169.07:52:09.25#ibcon#read 4, iclass 20, count 0 2006.169.07:52:09.25#ibcon#about to read 5, iclass 20, count 0 2006.169.07:52:09.25#ibcon#read 5, iclass 20, count 0 2006.169.07:52:09.25#ibcon#about to read 6, iclass 20, count 0 2006.169.07:52:09.25#ibcon#read 6, iclass 20, count 0 2006.169.07:52:09.25#ibcon#end of sib2, iclass 20, count 0 2006.169.07:52:09.25#ibcon#*after write, iclass 20, count 0 2006.169.07:52:09.25#ibcon#*before return 0, iclass 20, count 0 2006.169.07:52:09.25#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.169.07:52:09.25#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.169.07:52:09.25#ibcon#about to clear, iclass 20 cls_cnt 0 2006.169.07:52:09.25#ibcon#cleared, iclass 20 cls_cnt 0 2006.169.07:52:09.25$vc4f8/vb=6,4 2006.169.07:52:09.25#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.169.07:52:09.25#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.169.07:52:09.25#ibcon#ireg 11 cls_cnt 2 2006.169.07:52:09.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.169.07:52:09.31#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.169.07:52:09.31#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.169.07:52:09.31#ibcon#enter wrdev, iclass 22, count 2 2006.169.07:52:09.31#ibcon#first serial, iclass 22, count 2 2006.169.07:52:09.31#ibcon#enter sib2, iclass 22, count 2 2006.169.07:52:09.31#ibcon#flushed, iclass 22, count 2 2006.169.07:52:09.31#ibcon#about to write, iclass 22, count 2 2006.169.07:52:09.31#ibcon#wrote, iclass 22, count 2 2006.169.07:52:09.31#ibcon#about to read 3, iclass 22, count 2 2006.169.07:52:09.33#ibcon#read 3, iclass 22, count 2 2006.169.07:52:09.33#ibcon#about to read 4, iclass 22, count 2 2006.169.07:52:09.33#ibcon#read 4, iclass 22, count 2 2006.169.07:52:09.33#ibcon#about to read 5, iclass 22, count 2 2006.169.07:52:09.33#ibcon#read 5, iclass 22, count 2 2006.169.07:52:09.33#ibcon#about to read 6, iclass 22, count 2 2006.169.07:52:09.33#ibcon#read 6, iclass 22, count 2 2006.169.07:52:09.33#ibcon#end of sib2, iclass 22, count 2 2006.169.07:52:09.33#ibcon#*mode == 0, iclass 22, count 2 2006.169.07:52:09.33#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.169.07:52:09.33#ibcon#[27=AT06-04\r\n] 2006.169.07:52:09.33#ibcon#*before write, iclass 22, count 2 2006.169.07:52:09.33#ibcon#enter sib2, iclass 22, count 2 2006.169.07:52:09.33#ibcon#flushed, iclass 22, count 2 2006.169.07:52:09.33#ibcon#about to write, iclass 22, count 2 2006.169.07:52:09.33#ibcon#wrote, iclass 22, count 2 2006.169.07:52:09.33#ibcon#about to read 3, iclass 22, count 2 2006.169.07:52:09.36#ibcon#read 3, iclass 22, count 2 2006.169.07:52:09.36#ibcon#about to read 4, iclass 22, count 2 2006.169.07:52:09.36#ibcon#read 4, iclass 22, count 2 2006.169.07:52:09.36#ibcon#about to read 5, iclass 22, count 2 2006.169.07:52:09.36#ibcon#read 5, iclass 22, count 2 2006.169.07:52:09.36#ibcon#about to read 6, iclass 22, count 2 2006.169.07:52:09.36#ibcon#read 6, iclass 22, count 2 2006.169.07:52:09.36#ibcon#end of sib2, iclass 22, count 2 2006.169.07:52:09.36#ibcon#*after write, iclass 22, count 2 2006.169.07:52:09.36#ibcon#*before return 0, iclass 22, count 2 2006.169.07:52:09.36#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.169.07:52:09.36#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.169.07:52:09.36#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.169.07:52:09.36#ibcon#ireg 7 cls_cnt 0 2006.169.07:52:09.36#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.169.07:52:09.48#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.169.07:52:09.48#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.169.07:52:09.48#ibcon#enter wrdev, iclass 22, count 0 2006.169.07:52:09.48#ibcon#first serial, iclass 22, count 0 2006.169.07:52:09.48#ibcon#enter sib2, iclass 22, count 0 2006.169.07:52:09.48#ibcon#flushed, iclass 22, count 0 2006.169.07:52:09.48#ibcon#about to write, iclass 22, count 0 2006.169.07:52:09.48#ibcon#wrote, iclass 22, count 0 2006.169.07:52:09.48#ibcon#about to read 3, iclass 22, count 0 2006.169.07:52:09.50#ibcon#read 3, iclass 22, count 0 2006.169.07:52:09.50#ibcon#about to read 4, iclass 22, count 0 2006.169.07:52:09.50#ibcon#read 4, iclass 22, count 0 2006.169.07:52:09.50#ibcon#about to read 5, iclass 22, count 0 2006.169.07:52:09.50#ibcon#read 5, iclass 22, count 0 2006.169.07:52:09.50#ibcon#about to read 6, iclass 22, count 0 2006.169.07:52:09.50#ibcon#read 6, iclass 22, count 0 2006.169.07:52:09.50#ibcon#end of sib2, iclass 22, count 0 2006.169.07:52:09.50#ibcon#*mode == 0, iclass 22, count 0 2006.169.07:52:09.50#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.169.07:52:09.50#ibcon#[27=USB\r\n] 2006.169.07:52:09.50#ibcon#*before write, iclass 22, count 0 2006.169.07:52:09.50#ibcon#enter sib2, iclass 22, count 0 2006.169.07:52:09.50#ibcon#flushed, iclass 22, count 0 2006.169.07:52:09.50#ibcon#about to write, iclass 22, count 0 2006.169.07:52:09.50#ibcon#wrote, iclass 22, count 0 2006.169.07:52:09.50#ibcon#about to read 3, iclass 22, count 0 2006.169.07:52:09.53#ibcon#read 3, iclass 22, count 0 2006.169.07:52:09.53#ibcon#about to read 4, iclass 22, count 0 2006.169.07:52:09.53#ibcon#read 4, iclass 22, count 0 2006.169.07:52:09.53#ibcon#about to read 5, iclass 22, count 0 2006.169.07:52:09.53#ibcon#read 5, iclass 22, count 0 2006.169.07:52:09.53#ibcon#about to read 6, iclass 22, count 0 2006.169.07:52:09.53#ibcon#read 6, iclass 22, count 0 2006.169.07:52:09.53#ibcon#end of sib2, iclass 22, count 0 2006.169.07:52:09.53#ibcon#*after write, iclass 22, count 0 2006.169.07:52:09.53#ibcon#*before return 0, iclass 22, count 0 2006.169.07:52:09.53#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.169.07:52:09.53#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.169.07:52:09.53#ibcon#about to clear, iclass 22 cls_cnt 0 2006.169.07:52:09.53#ibcon#cleared, iclass 22 cls_cnt 0 2006.169.07:52:09.53$vc4f8/vabw=wide 2006.169.07:52:09.53#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.169.07:52:09.53#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.169.07:52:09.53#ibcon#ireg 8 cls_cnt 0 2006.169.07:52:09.53#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.169.07:52:09.53#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.169.07:52:09.53#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.169.07:52:09.53#ibcon#enter wrdev, iclass 24, count 0 2006.169.07:52:09.53#ibcon#first serial, iclass 24, count 0 2006.169.07:52:09.53#ibcon#enter sib2, iclass 24, count 0 2006.169.07:52:09.53#ibcon#flushed, iclass 24, count 0 2006.169.07:52:09.53#ibcon#about to write, iclass 24, count 0 2006.169.07:52:09.53#ibcon#wrote, iclass 24, count 0 2006.169.07:52:09.53#ibcon#about to read 3, iclass 24, count 0 2006.169.07:52:09.55#ibcon#read 3, iclass 24, count 0 2006.169.07:52:09.55#ibcon#about to read 4, iclass 24, count 0 2006.169.07:52:09.55#ibcon#read 4, iclass 24, count 0 2006.169.07:52:09.55#ibcon#about to read 5, iclass 24, count 0 2006.169.07:52:09.55#ibcon#read 5, iclass 24, count 0 2006.169.07:52:09.55#ibcon#about to read 6, iclass 24, count 0 2006.169.07:52:09.55#ibcon#read 6, iclass 24, count 0 2006.169.07:52:09.55#ibcon#end of sib2, iclass 24, count 0 2006.169.07:52:09.55#ibcon#*mode == 0, iclass 24, count 0 2006.169.07:52:09.55#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.169.07:52:09.55#ibcon#[25=BW32\r\n] 2006.169.07:52:09.55#ibcon#*before write, iclass 24, count 0 2006.169.07:52:09.55#ibcon#enter sib2, iclass 24, count 0 2006.169.07:52:09.55#ibcon#flushed, iclass 24, count 0 2006.169.07:52:09.55#ibcon#about to write, iclass 24, count 0 2006.169.07:52:09.55#ibcon#wrote, iclass 24, count 0 2006.169.07:52:09.55#ibcon#about to read 3, iclass 24, count 0 2006.169.07:52:09.58#ibcon#read 3, iclass 24, count 0 2006.169.07:52:09.58#ibcon#about to read 4, iclass 24, count 0 2006.169.07:52:09.58#ibcon#read 4, iclass 24, count 0 2006.169.07:52:09.58#ibcon#about to read 5, iclass 24, count 0 2006.169.07:52:09.58#ibcon#read 5, iclass 24, count 0 2006.169.07:52:09.58#ibcon#about to read 6, iclass 24, count 0 2006.169.07:52:09.58#ibcon#read 6, iclass 24, count 0 2006.169.07:52:09.58#ibcon#end of sib2, iclass 24, count 0 2006.169.07:52:09.58#ibcon#*after write, iclass 24, count 0 2006.169.07:52:09.58#ibcon#*before return 0, iclass 24, count 0 2006.169.07:52:09.58#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.169.07:52:09.58#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.169.07:52:09.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.169.07:52:09.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.169.07:52:09.58$vc4f8/vbbw=wide 2006.169.07:52:09.58#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.169.07:52:09.58#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.169.07:52:09.58#ibcon#ireg 8 cls_cnt 0 2006.169.07:52:09.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:52:09.65#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:52:09.65#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:52:09.65#ibcon#enter wrdev, iclass 26, count 0 2006.169.07:52:09.65#ibcon#first serial, iclass 26, count 0 2006.169.07:52:09.65#ibcon#enter sib2, iclass 26, count 0 2006.169.07:52:09.65#ibcon#flushed, iclass 26, count 0 2006.169.07:52:09.65#ibcon#about to write, iclass 26, count 0 2006.169.07:52:09.65#ibcon#wrote, iclass 26, count 0 2006.169.07:52:09.65#ibcon#about to read 3, iclass 26, count 0 2006.169.07:52:09.67#ibcon#read 3, iclass 26, count 0 2006.169.07:52:09.67#ibcon#about to read 4, iclass 26, count 0 2006.169.07:52:09.67#ibcon#read 4, iclass 26, count 0 2006.169.07:52:09.67#ibcon#about to read 5, iclass 26, count 0 2006.169.07:52:09.67#ibcon#read 5, iclass 26, count 0 2006.169.07:52:09.67#ibcon#about to read 6, iclass 26, count 0 2006.169.07:52:09.67#ibcon#read 6, iclass 26, count 0 2006.169.07:52:09.67#ibcon#end of sib2, iclass 26, count 0 2006.169.07:52:09.67#ibcon#*mode == 0, iclass 26, count 0 2006.169.07:52:09.67#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.169.07:52:09.67#ibcon#[27=BW32\r\n] 2006.169.07:52:09.67#ibcon#*before write, iclass 26, count 0 2006.169.07:52:09.67#ibcon#enter sib2, iclass 26, count 0 2006.169.07:52:09.67#ibcon#flushed, iclass 26, count 0 2006.169.07:52:09.67#ibcon#about to write, iclass 26, count 0 2006.169.07:52:09.67#ibcon#wrote, iclass 26, count 0 2006.169.07:52:09.67#ibcon#about to read 3, iclass 26, count 0 2006.169.07:52:09.70#ibcon#read 3, iclass 26, count 0 2006.169.07:52:09.70#ibcon#about to read 4, iclass 26, count 0 2006.169.07:52:09.70#ibcon#read 4, iclass 26, count 0 2006.169.07:52:09.70#ibcon#about to read 5, iclass 26, count 0 2006.169.07:52:09.70#ibcon#read 5, iclass 26, count 0 2006.169.07:52:09.70#ibcon#about to read 6, iclass 26, count 0 2006.169.07:52:09.70#ibcon#read 6, iclass 26, count 0 2006.169.07:52:09.70#ibcon#end of sib2, iclass 26, count 0 2006.169.07:52:09.70#ibcon#*after write, iclass 26, count 0 2006.169.07:52:09.70#ibcon#*before return 0, iclass 26, count 0 2006.169.07:52:09.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:52:09.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:52:09.70#ibcon#about to clear, iclass 26 cls_cnt 0 2006.169.07:52:09.70#ibcon#cleared, iclass 26 cls_cnt 0 2006.169.07:52:09.70$4f8m12a/ifd4f 2006.169.07:52:09.70$ifd4f/lo= 2006.169.07:52:09.70$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.07:52:09.70$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.07:52:09.70$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.07:52:09.70$ifd4f/patch= 2006.169.07:52:09.70$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.07:52:09.70$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.07:52:09.70$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.07:52:09.70$4f8m12a/"form=m,16.000,1:2 2006.169.07:52:09.70$4f8m12a/"tpicd 2006.169.07:52:09.70$4f8m12a/echo=off 2006.169.07:52:09.70$4f8m12a/xlog=off 2006.169.07:52:09.70:!2006.169.07:52:20 2006.169.07:52:20.00:preob 2006.169.07:52:21.14/onsource/TRACKING 2006.169.07:52:21.14:!2006.169.07:52:30 2006.169.07:52:30.00:data_valid=on 2006.169.07:52:30.00:midob 2006.169.07:52:30.14/onsource/TRACKING 2006.169.07:52:30.14/wx/18.12,1003.9,100 2006.169.07:52:30.20/cable/+6.5273E-03 2006.169.07:52:31.29/va/01,08,usb,yes,50,53 2006.169.07:52:31.29/va/02,07,usb,yes,51,53 2006.169.07:52:31.29/va/03,06,usb,yes,54,54 2006.169.07:52:31.29/va/04,07,usb,yes,52,56 2006.169.07:52:31.29/va/05,07,usb,yes,57,61 2006.169.07:52:31.29/va/06,06,usb,yes,57,56 2006.169.07:52:31.29/va/07,06,usb,yes,57,57 2006.169.07:52:31.29/va/08,07,usb,yes,54,54 2006.169.07:52:31.52/valo/01,532.99,yes,locked 2006.169.07:52:31.52/valo/02,572.99,yes,locked 2006.169.07:52:31.52/valo/03,672.99,yes,locked 2006.169.07:52:31.52/valo/04,832.99,yes,locked 2006.169.07:52:31.52/valo/05,652.99,yes,locked 2006.169.07:52:31.52/valo/06,772.99,yes,locked 2006.169.07:52:31.52/valo/07,832.99,yes,locked 2006.169.07:52:31.52/valo/08,852.99,yes,locked 2006.169.07:52:32.61/vb/01,04,usb,yes,31,29 2006.169.07:52:32.61/vb/02,04,usb,yes,33,34 2006.169.07:52:32.61/vb/03,04,usb,yes,29,33 2006.169.07:52:32.61/vb/04,04,usb,yes,30,30 2006.169.07:52:32.61/vb/05,04,usb,yes,28,33 2006.169.07:52:32.61/vb/06,04,usb,yes,30,32 2006.169.07:52:32.61/vb/07,04,usb,yes,32,31 2006.169.07:52:32.61/vb/08,04,usb,yes,29,33 2006.169.07:52:32.84/vblo/01,632.99,yes,locked 2006.169.07:52:32.84/vblo/02,640.99,yes,locked 2006.169.07:52:32.84/vblo/03,656.99,yes,locked 2006.169.07:52:32.84/vblo/04,712.99,yes,locked 2006.169.07:52:32.84/vblo/05,744.99,yes,locked 2006.169.07:52:32.84/vblo/06,752.99,yes,locked 2006.169.07:52:32.84/vblo/07,734.99,yes,locked 2006.169.07:52:32.84/vblo/08,744.99,yes,locked 2006.169.07:52:32.99/vabw/8 2006.169.07:52:33.14/vbbw/8 2006.169.07:52:33.23/xfe/off,on,14.2 2006.169.07:52:33.63/ifatt/23,28,28,28 2006.169.07:52:34.07/fmout-gps/S +4.17E-07 2006.169.07:52:34.11:!2006.169.07:53:30 2006.169.07:53:30.00:data_valid=off 2006.169.07:53:30.00:postob 2006.169.07:53:30.20/cable/+6.5280E-03 2006.169.07:53:30.20/wx/18.12,1003.9,100 2006.169.07:53:31.07/fmout-gps/S +4.16E-07 2006.169.07:53:31.07:scan_name=169-0755,k06169,60 2006.169.07:53:31.07:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.169.07:53:31.14#flagr#flagr/antenna,new-source 2006.169.07:53:32.14:checkk5 2006.169.07:53:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.169.07:53:32.90/chk_autoobs//k5ts2/ autoobs is running! 2006.169.07:53:36.91/chk_autoobs//k5ts3?ERROR: timeout happened! 2006.169.07:53:37.29/chk_autoobs//k5ts4/ autoobs is running! 2006.169.07:53:37.66/chk_obsdata//k5ts1/T1690752??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:53:38.03/chk_obsdata//k5ts2/T1690752??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:53:45.09/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.07:53:45.47/chk_obsdata//k5ts4/T1690752??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:53:46.16/k5log//k5ts1_log_newline 2006.169.07:53:46.85/k5log//k5ts2_log_newline 2006.169.07:53:53.94/k5log//k5ts3?ERROR: timeout happened! 2006.169.07:53:54.64/k5log//k5ts4_log_newline 2006.169.07:53:54.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.07:53:54.90:4f8m12a=2 2006.169.07:53:54.90$4f8m12a/echo=on 2006.169.07:53:54.91$4f8m12a/pcalon 2006.169.07:53:54.91$pcalon/"no phase cal control is implemented here 2006.169.07:53:54.91$4f8m12a/"tpicd=stop 2006.169.07:53:54.91$4f8m12a/vc4f8 2006.169.07:53:54.91$vc4f8/valo=1,532.99 2006.169.07:53:54.91#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.169.07:53:54.91#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.169.07:53:54.91#ibcon#ireg 17 cls_cnt 0 2006.169.07:53:54.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:53:54.91#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:53:54.91#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:53:54.91#ibcon#enter wrdev, iclass 33, count 0 2006.169.07:53:54.91#ibcon#first serial, iclass 33, count 0 2006.169.07:53:54.91#ibcon#enter sib2, iclass 33, count 0 2006.169.07:53:54.91#ibcon#flushed, iclass 33, count 0 2006.169.07:53:54.91#ibcon#about to write, iclass 33, count 0 2006.169.07:53:54.91#ibcon#wrote, iclass 33, count 0 2006.169.07:53:54.91#ibcon#about to read 3, iclass 33, count 0 2006.169.07:53:54.93#ibcon#read 3, iclass 33, count 0 2006.169.07:53:54.93#ibcon#about to read 4, iclass 33, count 0 2006.169.07:53:54.93#ibcon#read 4, iclass 33, count 0 2006.169.07:53:54.93#ibcon#about to read 5, iclass 33, count 0 2006.169.07:53:54.93#ibcon#read 5, iclass 33, count 0 2006.169.07:53:54.93#ibcon#about to read 6, iclass 33, count 0 2006.169.07:53:54.93#ibcon#read 6, iclass 33, count 0 2006.169.07:53:54.93#ibcon#end of sib2, iclass 33, count 0 2006.169.07:53:54.93#ibcon#*mode == 0, iclass 33, count 0 2006.169.07:53:54.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.169.07:53:54.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.07:53:54.93#ibcon#*before write, iclass 33, count 0 2006.169.07:53:54.93#ibcon#enter sib2, iclass 33, count 0 2006.169.07:53:54.93#ibcon#flushed, iclass 33, count 0 2006.169.07:53:54.93#ibcon#about to write, iclass 33, count 0 2006.169.07:53:54.93#ibcon#wrote, iclass 33, count 0 2006.169.07:53:54.93#ibcon#about to read 3, iclass 33, count 0 2006.169.07:53:54.98#ibcon#read 3, iclass 33, count 0 2006.169.07:53:54.98#ibcon#about to read 4, iclass 33, count 0 2006.169.07:53:54.98#ibcon#read 4, iclass 33, count 0 2006.169.07:53:54.98#ibcon#about to read 5, iclass 33, count 0 2006.169.07:53:54.98#ibcon#read 5, iclass 33, count 0 2006.169.07:53:54.98#ibcon#about to read 6, iclass 33, count 0 2006.169.07:53:54.98#ibcon#read 6, iclass 33, count 0 2006.169.07:53:54.98#ibcon#end of sib2, iclass 33, count 0 2006.169.07:53:54.98#ibcon#*after write, iclass 33, count 0 2006.169.07:53:54.98#ibcon#*before return 0, iclass 33, count 0 2006.169.07:53:54.98#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:53:54.98#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:53:54.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.169.07:53:54.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.169.07:53:54.98$vc4f8/va=1,8 2006.169.07:53:54.98#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.169.07:53:54.98#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.169.07:53:54.98#ibcon#ireg 11 cls_cnt 2 2006.169.07:53:54.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:53:54.98#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:53:54.98#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:53:54.98#ibcon#enter wrdev, iclass 35, count 2 2006.169.07:53:54.98#ibcon#first serial, iclass 35, count 2 2006.169.07:53:54.98#ibcon#enter sib2, iclass 35, count 2 2006.169.07:53:54.98#ibcon#flushed, iclass 35, count 2 2006.169.07:53:54.98#ibcon#about to write, iclass 35, count 2 2006.169.07:53:54.98#ibcon#wrote, iclass 35, count 2 2006.169.07:53:54.98#ibcon#about to read 3, iclass 35, count 2 2006.169.07:53:55.00#ibcon#read 3, iclass 35, count 2 2006.169.07:53:55.00#ibcon#about to read 4, iclass 35, count 2 2006.169.07:53:55.00#ibcon#read 4, iclass 35, count 2 2006.169.07:53:55.00#ibcon#about to read 5, iclass 35, count 2 2006.169.07:53:55.00#ibcon#read 5, iclass 35, count 2 2006.169.07:53:55.00#ibcon#about to read 6, iclass 35, count 2 2006.169.07:53:55.00#ibcon#read 6, iclass 35, count 2 2006.169.07:53:55.00#ibcon#end of sib2, iclass 35, count 2 2006.169.07:53:55.00#ibcon#*mode == 0, iclass 35, count 2 2006.169.07:53:55.00#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.169.07:53:55.00#ibcon#[25=AT01-08\r\n] 2006.169.07:53:55.00#ibcon#*before write, iclass 35, count 2 2006.169.07:53:55.00#ibcon#enter sib2, iclass 35, count 2 2006.169.07:53:55.00#ibcon#flushed, iclass 35, count 2 2006.169.07:53:55.00#ibcon#about to write, iclass 35, count 2 2006.169.07:53:55.00#ibcon#wrote, iclass 35, count 2 2006.169.07:53:55.00#ibcon#about to read 3, iclass 35, count 2 2006.169.07:53:55.03#ibcon#read 3, iclass 35, count 2 2006.169.07:53:55.03#ibcon#about to read 4, iclass 35, count 2 2006.169.07:53:55.03#ibcon#read 4, iclass 35, count 2 2006.169.07:53:55.03#ibcon#about to read 5, iclass 35, count 2 2006.169.07:53:55.03#ibcon#read 5, iclass 35, count 2 2006.169.07:53:55.03#ibcon#about to read 6, iclass 35, count 2 2006.169.07:53:55.03#ibcon#read 6, iclass 35, count 2 2006.169.07:53:55.03#ibcon#end of sib2, iclass 35, count 2 2006.169.07:53:55.03#ibcon#*after write, iclass 35, count 2 2006.169.07:53:55.03#ibcon#*before return 0, iclass 35, count 2 2006.169.07:53:55.03#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:53:55.03#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:53:55.03#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.169.07:53:55.03#ibcon#ireg 7 cls_cnt 0 2006.169.07:53:55.03#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:53:55.15#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:53:55.15#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:53:55.15#ibcon#enter wrdev, iclass 35, count 0 2006.169.07:53:55.15#ibcon#first serial, iclass 35, count 0 2006.169.07:53:55.15#ibcon#enter sib2, iclass 35, count 0 2006.169.07:53:55.15#ibcon#flushed, iclass 35, count 0 2006.169.07:53:55.15#ibcon#about to write, iclass 35, count 0 2006.169.07:53:55.15#ibcon#wrote, iclass 35, count 0 2006.169.07:53:55.15#ibcon#about to read 3, iclass 35, count 0 2006.169.07:53:55.17#ibcon#read 3, iclass 35, count 0 2006.169.07:53:55.17#ibcon#about to read 4, iclass 35, count 0 2006.169.07:53:55.17#ibcon#read 4, iclass 35, count 0 2006.169.07:53:55.17#ibcon#about to read 5, iclass 35, count 0 2006.169.07:53:55.17#ibcon#read 5, iclass 35, count 0 2006.169.07:53:55.17#ibcon#about to read 6, iclass 35, count 0 2006.169.07:53:55.17#ibcon#read 6, iclass 35, count 0 2006.169.07:53:55.17#ibcon#end of sib2, iclass 35, count 0 2006.169.07:53:55.17#ibcon#*mode == 0, iclass 35, count 0 2006.169.07:53:55.17#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.169.07:53:55.17#ibcon#[25=USB\r\n] 2006.169.07:53:55.17#ibcon#*before write, iclass 35, count 0 2006.169.07:53:55.17#ibcon#enter sib2, iclass 35, count 0 2006.169.07:53:55.17#ibcon#flushed, iclass 35, count 0 2006.169.07:53:55.17#ibcon#about to write, iclass 35, count 0 2006.169.07:53:55.17#ibcon#wrote, iclass 35, count 0 2006.169.07:53:55.17#ibcon#about to read 3, iclass 35, count 0 2006.169.07:53:55.20#ibcon#read 3, iclass 35, count 0 2006.169.07:53:55.20#ibcon#about to read 4, iclass 35, count 0 2006.169.07:53:55.20#ibcon#read 4, iclass 35, count 0 2006.169.07:53:55.20#ibcon#about to read 5, iclass 35, count 0 2006.169.07:53:55.20#ibcon#read 5, iclass 35, count 0 2006.169.07:53:55.20#ibcon#about to read 6, iclass 35, count 0 2006.169.07:53:55.20#ibcon#read 6, iclass 35, count 0 2006.169.07:53:55.20#ibcon#end of sib2, iclass 35, count 0 2006.169.07:53:55.20#ibcon#*after write, iclass 35, count 0 2006.169.07:53:55.20#ibcon#*before return 0, iclass 35, count 0 2006.169.07:53:55.20#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:53:55.20#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:53:55.20#ibcon#about to clear, iclass 35 cls_cnt 0 2006.169.07:53:55.20#ibcon#cleared, iclass 35 cls_cnt 0 2006.169.07:53:55.20$vc4f8/valo=2,572.99 2006.169.07:53:55.20#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.169.07:53:55.20#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.169.07:53:55.20#ibcon#ireg 17 cls_cnt 0 2006.169.07:53:55.20#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:53:55.20#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:53:55.20#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:53:55.20#ibcon#enter wrdev, iclass 37, count 0 2006.169.07:53:55.20#ibcon#first serial, iclass 37, count 0 2006.169.07:53:55.20#ibcon#enter sib2, iclass 37, count 0 2006.169.07:53:55.20#ibcon#flushed, iclass 37, count 0 2006.169.07:53:55.20#ibcon#about to write, iclass 37, count 0 2006.169.07:53:55.20#ibcon#wrote, iclass 37, count 0 2006.169.07:53:55.20#ibcon#about to read 3, iclass 37, count 0 2006.169.07:53:55.22#ibcon#read 3, iclass 37, count 0 2006.169.07:53:55.22#ibcon#about to read 4, iclass 37, count 0 2006.169.07:53:55.22#ibcon#read 4, iclass 37, count 0 2006.169.07:53:55.22#ibcon#about to read 5, iclass 37, count 0 2006.169.07:53:55.22#ibcon#read 5, iclass 37, count 0 2006.169.07:53:55.22#ibcon#about to read 6, iclass 37, count 0 2006.169.07:53:55.22#ibcon#read 6, iclass 37, count 0 2006.169.07:53:55.22#ibcon#end of sib2, iclass 37, count 0 2006.169.07:53:55.22#ibcon#*mode == 0, iclass 37, count 0 2006.169.07:53:55.22#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.169.07:53:55.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.07:53:55.22#ibcon#*before write, iclass 37, count 0 2006.169.07:53:55.22#ibcon#enter sib2, iclass 37, count 0 2006.169.07:53:55.22#ibcon#flushed, iclass 37, count 0 2006.169.07:53:55.22#ibcon#about to write, iclass 37, count 0 2006.169.07:53:55.22#ibcon#wrote, iclass 37, count 0 2006.169.07:53:55.22#ibcon#about to read 3, iclass 37, count 0 2006.169.07:53:55.26#ibcon#read 3, iclass 37, count 0 2006.169.07:53:55.26#ibcon#about to read 4, iclass 37, count 0 2006.169.07:53:55.26#ibcon#read 4, iclass 37, count 0 2006.169.07:53:55.26#ibcon#about to read 5, iclass 37, count 0 2006.169.07:53:55.26#ibcon#read 5, iclass 37, count 0 2006.169.07:53:55.26#ibcon#about to read 6, iclass 37, count 0 2006.169.07:53:55.26#ibcon#read 6, iclass 37, count 0 2006.169.07:53:55.26#ibcon#end of sib2, iclass 37, count 0 2006.169.07:53:55.26#ibcon#*after write, iclass 37, count 0 2006.169.07:53:55.26#ibcon#*before return 0, iclass 37, count 0 2006.169.07:53:55.26#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:53:55.26#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:53:55.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.169.07:53:55.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.169.07:53:55.26$vc4f8/va=2,7 2006.169.07:53:55.26#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.169.07:53:55.26#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.169.07:53:55.26#ibcon#ireg 11 cls_cnt 2 2006.169.07:53:55.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:53:55.32#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:53:55.32#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:53:55.32#ibcon#enter wrdev, iclass 39, count 2 2006.169.07:53:55.32#ibcon#first serial, iclass 39, count 2 2006.169.07:53:55.32#ibcon#enter sib2, iclass 39, count 2 2006.169.07:53:55.32#ibcon#flushed, iclass 39, count 2 2006.169.07:53:55.32#ibcon#about to write, iclass 39, count 2 2006.169.07:53:55.32#ibcon#wrote, iclass 39, count 2 2006.169.07:53:55.32#ibcon#about to read 3, iclass 39, count 2 2006.169.07:53:55.34#ibcon#read 3, iclass 39, count 2 2006.169.07:53:55.34#ibcon#about to read 4, iclass 39, count 2 2006.169.07:53:55.34#ibcon#read 4, iclass 39, count 2 2006.169.07:53:55.34#ibcon#about to read 5, iclass 39, count 2 2006.169.07:53:55.34#ibcon#read 5, iclass 39, count 2 2006.169.07:53:55.34#ibcon#about to read 6, iclass 39, count 2 2006.169.07:53:55.34#ibcon#read 6, iclass 39, count 2 2006.169.07:53:55.34#ibcon#end of sib2, iclass 39, count 2 2006.169.07:53:55.34#ibcon#*mode == 0, iclass 39, count 2 2006.169.07:53:55.34#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.169.07:53:55.34#ibcon#[25=AT02-07\r\n] 2006.169.07:53:55.34#ibcon#*before write, iclass 39, count 2 2006.169.07:53:55.34#ibcon#enter sib2, iclass 39, count 2 2006.169.07:53:55.34#ibcon#flushed, iclass 39, count 2 2006.169.07:53:55.34#ibcon#about to write, iclass 39, count 2 2006.169.07:53:55.34#ibcon#wrote, iclass 39, count 2 2006.169.07:53:55.34#ibcon#about to read 3, iclass 39, count 2 2006.169.07:53:55.37#ibcon#read 3, iclass 39, count 2 2006.169.07:53:55.37#ibcon#about to read 4, iclass 39, count 2 2006.169.07:53:55.37#ibcon#read 4, iclass 39, count 2 2006.169.07:53:55.37#ibcon#about to read 5, iclass 39, count 2 2006.169.07:53:55.37#ibcon#read 5, iclass 39, count 2 2006.169.07:53:55.37#ibcon#about to read 6, iclass 39, count 2 2006.169.07:53:55.37#ibcon#read 6, iclass 39, count 2 2006.169.07:53:55.37#ibcon#end of sib2, iclass 39, count 2 2006.169.07:53:55.37#ibcon#*after write, iclass 39, count 2 2006.169.07:53:55.37#ibcon#*before return 0, iclass 39, count 2 2006.169.07:53:55.37#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:53:55.37#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:53:55.37#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.169.07:53:55.37#ibcon#ireg 7 cls_cnt 0 2006.169.07:53:55.37#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:53:55.50#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:53:55.50#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:53:55.50#ibcon#enter wrdev, iclass 39, count 0 2006.169.07:53:55.50#ibcon#first serial, iclass 39, count 0 2006.169.07:53:55.50#ibcon#enter sib2, iclass 39, count 0 2006.169.07:53:55.50#ibcon#flushed, iclass 39, count 0 2006.169.07:53:55.50#ibcon#about to write, iclass 39, count 0 2006.169.07:53:55.50#ibcon#wrote, iclass 39, count 0 2006.169.07:53:55.50#ibcon#about to read 3, iclass 39, count 0 2006.169.07:53:55.52#ibcon#read 3, iclass 39, count 0 2006.169.07:53:55.52#ibcon#about to read 4, iclass 39, count 0 2006.169.07:53:55.52#ibcon#read 4, iclass 39, count 0 2006.169.07:53:55.52#ibcon#about to read 5, iclass 39, count 0 2006.169.07:53:55.52#ibcon#read 5, iclass 39, count 0 2006.169.07:53:55.52#ibcon#about to read 6, iclass 39, count 0 2006.169.07:53:55.52#ibcon#read 6, iclass 39, count 0 2006.169.07:53:55.52#ibcon#end of sib2, iclass 39, count 0 2006.169.07:53:55.52#ibcon#*mode == 0, iclass 39, count 0 2006.169.07:53:55.52#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.169.07:53:55.52#ibcon#[25=USB\r\n] 2006.169.07:53:55.52#ibcon#*before write, iclass 39, count 0 2006.169.07:53:55.52#ibcon#enter sib2, iclass 39, count 0 2006.169.07:53:55.52#ibcon#flushed, iclass 39, count 0 2006.169.07:53:55.52#ibcon#about to write, iclass 39, count 0 2006.169.07:53:55.52#ibcon#wrote, iclass 39, count 0 2006.169.07:53:55.52#ibcon#about to read 3, iclass 39, count 0 2006.169.07:53:55.55#ibcon#read 3, iclass 39, count 0 2006.169.07:53:55.55#ibcon#about to read 4, iclass 39, count 0 2006.169.07:53:55.55#ibcon#read 4, iclass 39, count 0 2006.169.07:53:55.55#ibcon#about to read 5, iclass 39, count 0 2006.169.07:53:55.55#ibcon#read 5, iclass 39, count 0 2006.169.07:53:55.55#ibcon#about to read 6, iclass 39, count 0 2006.169.07:53:55.55#ibcon#read 6, iclass 39, count 0 2006.169.07:53:55.55#ibcon#end of sib2, iclass 39, count 0 2006.169.07:53:55.55#ibcon#*after write, iclass 39, count 0 2006.169.07:53:55.55#ibcon#*before return 0, iclass 39, count 0 2006.169.07:53:55.55#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:53:55.55#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:53:55.55#ibcon#about to clear, iclass 39 cls_cnt 0 2006.169.07:53:55.55#ibcon#cleared, iclass 39 cls_cnt 0 2006.169.07:53:55.55$vc4f8/valo=3,672.99 2006.169.07:53:55.55#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.169.07:53:55.55#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.169.07:53:55.55#ibcon#ireg 17 cls_cnt 0 2006.169.07:53:55.55#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:53:55.55#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:53:55.55#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:53:55.55#ibcon#enter wrdev, iclass 3, count 0 2006.169.07:53:55.55#ibcon#first serial, iclass 3, count 0 2006.169.07:53:55.55#ibcon#enter sib2, iclass 3, count 0 2006.169.07:53:55.55#ibcon#flushed, iclass 3, count 0 2006.169.07:53:55.55#ibcon#about to write, iclass 3, count 0 2006.169.07:53:55.55#ibcon#wrote, iclass 3, count 0 2006.169.07:53:55.55#ibcon#about to read 3, iclass 3, count 0 2006.169.07:53:55.57#ibcon#read 3, iclass 3, count 0 2006.169.07:53:55.57#ibcon#about to read 4, iclass 3, count 0 2006.169.07:53:55.57#ibcon#read 4, iclass 3, count 0 2006.169.07:53:55.57#ibcon#about to read 5, iclass 3, count 0 2006.169.07:53:55.57#ibcon#read 5, iclass 3, count 0 2006.169.07:53:55.57#ibcon#about to read 6, iclass 3, count 0 2006.169.07:53:55.57#ibcon#read 6, iclass 3, count 0 2006.169.07:53:55.57#ibcon#end of sib2, iclass 3, count 0 2006.169.07:53:55.57#ibcon#*mode == 0, iclass 3, count 0 2006.169.07:53:55.57#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.169.07:53:55.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.07:53:55.57#ibcon#*before write, iclass 3, count 0 2006.169.07:53:55.57#ibcon#enter sib2, iclass 3, count 0 2006.169.07:53:55.57#ibcon#flushed, iclass 3, count 0 2006.169.07:53:55.57#ibcon#about to write, iclass 3, count 0 2006.169.07:53:55.57#ibcon#wrote, iclass 3, count 0 2006.169.07:53:55.57#ibcon#about to read 3, iclass 3, count 0 2006.169.07:53:55.61#ibcon#read 3, iclass 3, count 0 2006.169.07:53:55.61#ibcon#about to read 4, iclass 3, count 0 2006.169.07:53:55.61#ibcon#read 4, iclass 3, count 0 2006.169.07:53:55.61#ibcon#about to read 5, iclass 3, count 0 2006.169.07:53:55.61#ibcon#read 5, iclass 3, count 0 2006.169.07:53:55.61#ibcon#about to read 6, iclass 3, count 0 2006.169.07:53:55.61#ibcon#read 6, iclass 3, count 0 2006.169.07:53:55.61#ibcon#end of sib2, iclass 3, count 0 2006.169.07:53:55.61#ibcon#*after write, iclass 3, count 0 2006.169.07:53:55.61#ibcon#*before return 0, iclass 3, count 0 2006.169.07:53:55.61#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:53:55.61#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.169.07:53:55.61#ibcon#about to clear, iclass 3 cls_cnt 0 2006.169.07:53:55.61#ibcon#cleared, iclass 3 cls_cnt 0 2006.169.07:53:55.61$vc4f8/va=3,6 2006.169.07:53:55.61#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.169.07:53:55.61#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.169.07:53:55.61#ibcon#ireg 11 cls_cnt 2 2006.169.07:53:55.61#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:53:55.67#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:53:55.67#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:53:55.67#ibcon#enter wrdev, iclass 5, count 2 2006.169.07:53:55.67#ibcon#first serial, iclass 5, count 2 2006.169.07:53:55.67#ibcon#enter sib2, iclass 5, count 2 2006.169.07:53:55.67#ibcon#flushed, iclass 5, count 2 2006.169.07:53:55.67#ibcon#about to write, iclass 5, count 2 2006.169.07:53:55.67#ibcon#wrote, iclass 5, count 2 2006.169.07:53:55.67#ibcon#about to read 3, iclass 5, count 2 2006.169.07:53:55.69#ibcon#read 3, iclass 5, count 2 2006.169.07:53:55.69#ibcon#about to read 4, iclass 5, count 2 2006.169.07:53:55.69#ibcon#read 4, iclass 5, count 2 2006.169.07:53:55.69#ibcon#about to read 5, iclass 5, count 2 2006.169.07:53:55.69#ibcon#read 5, iclass 5, count 2 2006.169.07:53:55.69#ibcon#about to read 6, iclass 5, count 2 2006.169.07:53:55.69#ibcon#read 6, iclass 5, count 2 2006.169.07:53:55.69#ibcon#end of sib2, iclass 5, count 2 2006.169.07:53:55.69#ibcon#*mode == 0, iclass 5, count 2 2006.169.07:53:55.69#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.169.07:53:55.69#ibcon#[25=AT03-06\r\n] 2006.169.07:53:55.69#ibcon#*before write, iclass 5, count 2 2006.169.07:53:55.69#ibcon#enter sib2, iclass 5, count 2 2006.169.07:53:55.69#ibcon#flushed, iclass 5, count 2 2006.169.07:53:55.69#ibcon#about to write, iclass 5, count 2 2006.169.07:53:55.69#ibcon#wrote, iclass 5, count 2 2006.169.07:53:55.69#ibcon#about to read 3, iclass 5, count 2 2006.169.07:53:55.72#ibcon#read 3, iclass 5, count 2 2006.169.07:53:55.72#ibcon#about to read 4, iclass 5, count 2 2006.169.07:53:55.72#ibcon#read 4, iclass 5, count 2 2006.169.07:53:55.72#ibcon#about to read 5, iclass 5, count 2 2006.169.07:53:55.72#ibcon#read 5, iclass 5, count 2 2006.169.07:53:55.72#ibcon#about to read 6, iclass 5, count 2 2006.169.07:53:55.72#ibcon#read 6, iclass 5, count 2 2006.169.07:53:55.72#ibcon#end of sib2, iclass 5, count 2 2006.169.07:53:55.72#ibcon#*after write, iclass 5, count 2 2006.169.07:53:55.72#ibcon#*before return 0, iclass 5, count 2 2006.169.07:53:55.72#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:53:55.72#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.169.07:53:55.72#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.169.07:53:55.72#ibcon#ireg 7 cls_cnt 0 2006.169.07:53:55.72#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:53:55.84#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:53:55.84#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:53:55.84#ibcon#enter wrdev, iclass 5, count 0 2006.169.07:53:55.84#ibcon#first serial, iclass 5, count 0 2006.169.07:53:55.84#ibcon#enter sib2, iclass 5, count 0 2006.169.07:53:55.84#ibcon#flushed, iclass 5, count 0 2006.169.07:53:55.84#ibcon#about to write, iclass 5, count 0 2006.169.07:53:55.84#ibcon#wrote, iclass 5, count 0 2006.169.07:53:55.84#ibcon#about to read 3, iclass 5, count 0 2006.169.07:53:55.86#ibcon#read 3, iclass 5, count 0 2006.169.07:53:55.86#ibcon#about to read 4, iclass 5, count 0 2006.169.07:53:55.86#ibcon#read 4, iclass 5, count 0 2006.169.07:53:55.86#ibcon#about to read 5, iclass 5, count 0 2006.169.07:53:55.86#ibcon#read 5, iclass 5, count 0 2006.169.07:53:55.86#ibcon#about to read 6, iclass 5, count 0 2006.169.07:53:55.86#ibcon#read 6, iclass 5, count 0 2006.169.07:53:55.86#ibcon#end of sib2, iclass 5, count 0 2006.169.07:53:55.86#ibcon#*mode == 0, iclass 5, count 0 2006.169.07:53:55.86#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.169.07:53:55.86#ibcon#[25=USB\r\n] 2006.169.07:53:55.86#ibcon#*before write, iclass 5, count 0 2006.169.07:53:55.86#ibcon#enter sib2, iclass 5, count 0 2006.169.07:53:55.86#ibcon#flushed, iclass 5, count 0 2006.169.07:53:55.86#ibcon#about to write, iclass 5, count 0 2006.169.07:53:55.86#ibcon#wrote, iclass 5, count 0 2006.169.07:53:55.86#ibcon#about to read 3, iclass 5, count 0 2006.169.07:53:55.89#ibcon#read 3, iclass 5, count 0 2006.169.07:53:55.89#ibcon#about to read 4, iclass 5, count 0 2006.169.07:53:55.89#ibcon#read 4, iclass 5, count 0 2006.169.07:53:55.89#ibcon#about to read 5, iclass 5, count 0 2006.169.07:53:55.89#ibcon#read 5, iclass 5, count 0 2006.169.07:53:55.89#ibcon#about to read 6, iclass 5, count 0 2006.169.07:53:55.89#ibcon#read 6, iclass 5, count 0 2006.169.07:53:55.89#ibcon#end of sib2, iclass 5, count 0 2006.169.07:53:55.89#ibcon#*after write, iclass 5, count 0 2006.169.07:53:55.89#ibcon#*before return 0, iclass 5, count 0 2006.169.07:53:55.89#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:53:55.89#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.169.07:53:55.89#ibcon#about to clear, iclass 5 cls_cnt 0 2006.169.07:53:55.89#ibcon#cleared, iclass 5 cls_cnt 0 2006.169.07:53:55.89$vc4f8/valo=4,832.99 2006.169.07:53:55.89#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.169.07:53:55.89#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.169.07:53:55.89#ibcon#ireg 17 cls_cnt 0 2006.169.07:53:55.89#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:53:55.89#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:53:55.89#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:53:55.89#ibcon#enter wrdev, iclass 7, count 0 2006.169.07:53:55.89#ibcon#first serial, iclass 7, count 0 2006.169.07:53:55.89#ibcon#enter sib2, iclass 7, count 0 2006.169.07:53:55.89#ibcon#flushed, iclass 7, count 0 2006.169.07:53:55.89#ibcon#about to write, iclass 7, count 0 2006.169.07:53:55.89#ibcon#wrote, iclass 7, count 0 2006.169.07:53:55.89#ibcon#about to read 3, iclass 7, count 0 2006.169.07:53:55.91#ibcon#read 3, iclass 7, count 0 2006.169.07:53:55.91#ibcon#about to read 4, iclass 7, count 0 2006.169.07:53:55.91#ibcon#read 4, iclass 7, count 0 2006.169.07:53:55.91#ibcon#about to read 5, iclass 7, count 0 2006.169.07:53:55.91#ibcon#read 5, iclass 7, count 0 2006.169.07:53:55.91#ibcon#about to read 6, iclass 7, count 0 2006.169.07:53:55.91#ibcon#read 6, iclass 7, count 0 2006.169.07:53:55.91#ibcon#end of sib2, iclass 7, count 0 2006.169.07:53:55.91#ibcon#*mode == 0, iclass 7, count 0 2006.169.07:53:55.91#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.169.07:53:55.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.07:53:55.91#ibcon#*before write, iclass 7, count 0 2006.169.07:53:55.91#ibcon#enter sib2, iclass 7, count 0 2006.169.07:53:55.91#ibcon#flushed, iclass 7, count 0 2006.169.07:53:55.91#ibcon#about to write, iclass 7, count 0 2006.169.07:53:55.91#ibcon#wrote, iclass 7, count 0 2006.169.07:53:55.91#ibcon#about to read 3, iclass 7, count 0 2006.169.07:53:55.95#ibcon#read 3, iclass 7, count 0 2006.169.07:53:55.95#ibcon#about to read 4, iclass 7, count 0 2006.169.07:53:55.95#ibcon#read 4, iclass 7, count 0 2006.169.07:53:55.95#ibcon#about to read 5, iclass 7, count 0 2006.169.07:53:55.95#ibcon#read 5, iclass 7, count 0 2006.169.07:53:55.95#ibcon#about to read 6, iclass 7, count 0 2006.169.07:53:55.95#ibcon#read 6, iclass 7, count 0 2006.169.07:53:55.95#ibcon#end of sib2, iclass 7, count 0 2006.169.07:53:55.95#ibcon#*after write, iclass 7, count 0 2006.169.07:53:55.95#ibcon#*before return 0, iclass 7, count 0 2006.169.07:53:55.95#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:53:55.95#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:53:55.95#ibcon#about to clear, iclass 7 cls_cnt 0 2006.169.07:53:55.95#ibcon#cleared, iclass 7 cls_cnt 0 2006.169.07:53:55.95$vc4f8/va=4,7 2006.169.07:53:55.95#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.169.07:53:55.95#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.169.07:53:55.95#ibcon#ireg 11 cls_cnt 2 2006.169.07:53:55.95#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:53:56.01#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:53:56.01#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:53:56.01#ibcon#enter wrdev, iclass 11, count 2 2006.169.07:53:56.01#ibcon#first serial, iclass 11, count 2 2006.169.07:53:56.01#ibcon#enter sib2, iclass 11, count 2 2006.169.07:53:56.01#ibcon#flushed, iclass 11, count 2 2006.169.07:53:56.01#ibcon#about to write, iclass 11, count 2 2006.169.07:53:56.01#ibcon#wrote, iclass 11, count 2 2006.169.07:53:56.01#ibcon#about to read 3, iclass 11, count 2 2006.169.07:53:56.03#ibcon#read 3, iclass 11, count 2 2006.169.07:53:56.03#ibcon#about to read 4, iclass 11, count 2 2006.169.07:53:56.03#ibcon#read 4, iclass 11, count 2 2006.169.07:53:56.03#ibcon#about to read 5, iclass 11, count 2 2006.169.07:53:56.03#ibcon#read 5, iclass 11, count 2 2006.169.07:53:56.03#ibcon#about to read 6, iclass 11, count 2 2006.169.07:53:56.03#ibcon#read 6, iclass 11, count 2 2006.169.07:53:56.03#ibcon#end of sib2, iclass 11, count 2 2006.169.07:53:56.03#ibcon#*mode == 0, iclass 11, count 2 2006.169.07:53:56.03#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.169.07:53:56.03#ibcon#[25=AT04-07\r\n] 2006.169.07:53:56.03#ibcon#*before write, iclass 11, count 2 2006.169.07:53:56.03#ibcon#enter sib2, iclass 11, count 2 2006.169.07:53:56.03#ibcon#flushed, iclass 11, count 2 2006.169.07:53:56.03#ibcon#about to write, iclass 11, count 2 2006.169.07:53:56.03#ibcon#wrote, iclass 11, count 2 2006.169.07:53:56.03#ibcon#about to read 3, iclass 11, count 2 2006.169.07:53:56.06#ibcon#read 3, iclass 11, count 2 2006.169.07:53:56.06#ibcon#about to read 4, iclass 11, count 2 2006.169.07:53:56.06#ibcon#read 4, iclass 11, count 2 2006.169.07:53:56.06#ibcon#about to read 5, iclass 11, count 2 2006.169.07:53:56.06#ibcon#read 5, iclass 11, count 2 2006.169.07:53:56.06#ibcon#about to read 6, iclass 11, count 2 2006.169.07:53:56.06#ibcon#read 6, iclass 11, count 2 2006.169.07:53:56.06#ibcon#end of sib2, iclass 11, count 2 2006.169.07:53:56.06#ibcon#*after write, iclass 11, count 2 2006.169.07:53:56.06#ibcon#*before return 0, iclass 11, count 2 2006.169.07:53:56.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:53:56.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:53:56.06#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.169.07:53:56.06#ibcon#ireg 7 cls_cnt 0 2006.169.07:53:56.06#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:53:56.18#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:53:56.18#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:53:56.18#ibcon#enter wrdev, iclass 11, count 0 2006.169.07:53:56.18#ibcon#first serial, iclass 11, count 0 2006.169.07:53:56.18#ibcon#enter sib2, iclass 11, count 0 2006.169.07:53:56.18#ibcon#flushed, iclass 11, count 0 2006.169.07:53:56.18#ibcon#about to write, iclass 11, count 0 2006.169.07:53:56.18#ibcon#wrote, iclass 11, count 0 2006.169.07:53:56.18#ibcon#about to read 3, iclass 11, count 0 2006.169.07:53:56.20#ibcon#read 3, iclass 11, count 0 2006.169.07:53:56.20#ibcon#about to read 4, iclass 11, count 0 2006.169.07:53:56.20#ibcon#read 4, iclass 11, count 0 2006.169.07:53:56.20#ibcon#about to read 5, iclass 11, count 0 2006.169.07:53:56.20#ibcon#read 5, iclass 11, count 0 2006.169.07:53:56.20#ibcon#about to read 6, iclass 11, count 0 2006.169.07:53:56.20#ibcon#read 6, iclass 11, count 0 2006.169.07:53:56.20#ibcon#end of sib2, iclass 11, count 0 2006.169.07:53:56.20#ibcon#*mode == 0, iclass 11, count 0 2006.169.07:53:56.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.169.07:53:56.20#ibcon#[25=USB\r\n] 2006.169.07:53:56.20#ibcon#*before write, iclass 11, count 0 2006.169.07:53:56.20#ibcon#enter sib2, iclass 11, count 0 2006.169.07:53:56.20#ibcon#flushed, iclass 11, count 0 2006.169.07:53:56.20#ibcon#about to write, iclass 11, count 0 2006.169.07:53:56.20#ibcon#wrote, iclass 11, count 0 2006.169.07:53:56.20#ibcon#about to read 3, iclass 11, count 0 2006.169.07:53:56.23#ibcon#read 3, iclass 11, count 0 2006.169.07:53:56.23#ibcon#about to read 4, iclass 11, count 0 2006.169.07:53:56.23#ibcon#read 4, iclass 11, count 0 2006.169.07:53:56.23#ibcon#about to read 5, iclass 11, count 0 2006.169.07:53:56.23#ibcon#read 5, iclass 11, count 0 2006.169.07:53:56.23#ibcon#about to read 6, iclass 11, count 0 2006.169.07:53:56.23#ibcon#read 6, iclass 11, count 0 2006.169.07:53:56.23#ibcon#end of sib2, iclass 11, count 0 2006.169.07:53:56.23#ibcon#*after write, iclass 11, count 0 2006.169.07:53:56.23#ibcon#*before return 0, iclass 11, count 0 2006.169.07:53:56.23#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:53:56.23#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:53:56.23#ibcon#about to clear, iclass 11 cls_cnt 0 2006.169.07:53:56.23#ibcon#cleared, iclass 11 cls_cnt 0 2006.169.07:53:56.23$vc4f8/valo=5,652.99 2006.169.07:53:56.23#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.169.07:53:56.23#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.169.07:53:56.23#ibcon#ireg 17 cls_cnt 0 2006.169.07:53:56.23#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:53:56.23#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:53:56.23#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:53:56.23#ibcon#enter wrdev, iclass 13, count 0 2006.169.07:53:56.23#ibcon#first serial, iclass 13, count 0 2006.169.07:53:56.23#ibcon#enter sib2, iclass 13, count 0 2006.169.07:53:56.23#ibcon#flushed, iclass 13, count 0 2006.169.07:53:56.23#ibcon#about to write, iclass 13, count 0 2006.169.07:53:56.23#ibcon#wrote, iclass 13, count 0 2006.169.07:53:56.23#ibcon#about to read 3, iclass 13, count 0 2006.169.07:53:56.25#ibcon#read 3, iclass 13, count 0 2006.169.07:53:56.25#ibcon#about to read 4, iclass 13, count 0 2006.169.07:53:56.25#ibcon#read 4, iclass 13, count 0 2006.169.07:53:56.25#ibcon#about to read 5, iclass 13, count 0 2006.169.07:53:56.25#ibcon#read 5, iclass 13, count 0 2006.169.07:53:56.25#ibcon#about to read 6, iclass 13, count 0 2006.169.07:53:56.25#ibcon#read 6, iclass 13, count 0 2006.169.07:53:56.25#ibcon#end of sib2, iclass 13, count 0 2006.169.07:53:56.25#ibcon#*mode == 0, iclass 13, count 0 2006.169.07:53:56.25#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.07:53:56.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.07:53:56.25#ibcon#*before write, iclass 13, count 0 2006.169.07:53:56.25#ibcon#enter sib2, iclass 13, count 0 2006.169.07:53:56.25#ibcon#flushed, iclass 13, count 0 2006.169.07:53:56.25#ibcon#about to write, iclass 13, count 0 2006.169.07:53:56.25#ibcon#wrote, iclass 13, count 0 2006.169.07:53:56.25#ibcon#about to read 3, iclass 13, count 0 2006.169.07:53:56.29#ibcon#read 3, iclass 13, count 0 2006.169.07:53:56.29#ibcon#about to read 4, iclass 13, count 0 2006.169.07:53:56.29#ibcon#read 4, iclass 13, count 0 2006.169.07:53:56.29#ibcon#about to read 5, iclass 13, count 0 2006.169.07:53:56.29#ibcon#read 5, iclass 13, count 0 2006.169.07:53:56.29#ibcon#about to read 6, iclass 13, count 0 2006.169.07:53:56.29#ibcon#read 6, iclass 13, count 0 2006.169.07:53:56.29#ibcon#end of sib2, iclass 13, count 0 2006.169.07:53:56.29#ibcon#*after write, iclass 13, count 0 2006.169.07:53:56.29#ibcon#*before return 0, iclass 13, count 0 2006.169.07:53:56.29#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:53:56.29#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:53:56.29#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.07:53:56.29#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.07:53:56.29$vc4f8/va=5,7 2006.169.07:53:56.29#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.169.07:53:56.29#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.169.07:53:56.29#ibcon#ireg 11 cls_cnt 2 2006.169.07:53:56.29#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:53:56.35#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:53:56.35#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:53:56.35#ibcon#enter wrdev, iclass 15, count 2 2006.169.07:53:56.35#ibcon#first serial, iclass 15, count 2 2006.169.07:53:56.35#ibcon#enter sib2, iclass 15, count 2 2006.169.07:53:56.35#ibcon#flushed, iclass 15, count 2 2006.169.07:53:56.35#ibcon#about to write, iclass 15, count 2 2006.169.07:53:56.35#ibcon#wrote, iclass 15, count 2 2006.169.07:53:56.35#ibcon#about to read 3, iclass 15, count 2 2006.169.07:53:56.37#ibcon#read 3, iclass 15, count 2 2006.169.07:53:56.37#ibcon#about to read 4, iclass 15, count 2 2006.169.07:53:56.37#ibcon#read 4, iclass 15, count 2 2006.169.07:53:56.37#ibcon#about to read 5, iclass 15, count 2 2006.169.07:53:56.37#ibcon#read 5, iclass 15, count 2 2006.169.07:53:56.37#ibcon#about to read 6, iclass 15, count 2 2006.169.07:53:56.37#ibcon#read 6, iclass 15, count 2 2006.169.07:53:56.37#ibcon#end of sib2, iclass 15, count 2 2006.169.07:53:56.37#ibcon#*mode == 0, iclass 15, count 2 2006.169.07:53:56.37#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.169.07:53:56.37#ibcon#[25=AT05-07\r\n] 2006.169.07:53:56.37#ibcon#*before write, iclass 15, count 2 2006.169.07:53:56.37#ibcon#enter sib2, iclass 15, count 2 2006.169.07:53:56.37#ibcon#flushed, iclass 15, count 2 2006.169.07:53:56.37#ibcon#about to write, iclass 15, count 2 2006.169.07:53:56.37#ibcon#wrote, iclass 15, count 2 2006.169.07:53:56.37#ibcon#about to read 3, iclass 15, count 2 2006.169.07:53:56.40#ibcon#read 3, iclass 15, count 2 2006.169.07:53:56.40#ibcon#about to read 4, iclass 15, count 2 2006.169.07:53:56.40#ibcon#read 4, iclass 15, count 2 2006.169.07:53:56.40#ibcon#about to read 5, iclass 15, count 2 2006.169.07:53:56.40#ibcon#read 5, iclass 15, count 2 2006.169.07:53:56.40#ibcon#about to read 6, iclass 15, count 2 2006.169.07:53:56.40#ibcon#read 6, iclass 15, count 2 2006.169.07:53:56.40#ibcon#end of sib2, iclass 15, count 2 2006.169.07:53:56.40#ibcon#*after write, iclass 15, count 2 2006.169.07:53:56.40#ibcon#*before return 0, iclass 15, count 2 2006.169.07:53:56.40#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:53:56.40#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:53:56.40#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.169.07:53:56.40#ibcon#ireg 7 cls_cnt 0 2006.169.07:53:56.40#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:53:56.52#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:53:56.52#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:53:56.52#ibcon#enter wrdev, iclass 15, count 0 2006.169.07:53:56.52#ibcon#first serial, iclass 15, count 0 2006.169.07:53:56.52#ibcon#enter sib2, iclass 15, count 0 2006.169.07:53:56.52#ibcon#flushed, iclass 15, count 0 2006.169.07:53:56.52#ibcon#about to write, iclass 15, count 0 2006.169.07:53:56.52#ibcon#wrote, iclass 15, count 0 2006.169.07:53:56.52#ibcon#about to read 3, iclass 15, count 0 2006.169.07:53:56.54#ibcon#read 3, iclass 15, count 0 2006.169.07:53:56.54#ibcon#about to read 4, iclass 15, count 0 2006.169.07:53:56.54#ibcon#read 4, iclass 15, count 0 2006.169.07:53:56.54#ibcon#about to read 5, iclass 15, count 0 2006.169.07:53:56.54#ibcon#read 5, iclass 15, count 0 2006.169.07:53:56.54#ibcon#about to read 6, iclass 15, count 0 2006.169.07:53:56.54#ibcon#read 6, iclass 15, count 0 2006.169.07:53:56.54#ibcon#end of sib2, iclass 15, count 0 2006.169.07:53:56.54#ibcon#*mode == 0, iclass 15, count 0 2006.169.07:53:56.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.169.07:53:56.54#ibcon#[25=USB\r\n] 2006.169.07:53:56.54#ibcon#*before write, iclass 15, count 0 2006.169.07:53:56.54#ibcon#enter sib2, iclass 15, count 0 2006.169.07:53:56.54#ibcon#flushed, iclass 15, count 0 2006.169.07:53:56.54#ibcon#about to write, iclass 15, count 0 2006.169.07:53:56.54#ibcon#wrote, iclass 15, count 0 2006.169.07:53:56.54#ibcon#about to read 3, iclass 15, count 0 2006.169.07:53:56.57#ibcon#read 3, iclass 15, count 0 2006.169.07:53:56.57#ibcon#about to read 4, iclass 15, count 0 2006.169.07:53:56.57#ibcon#read 4, iclass 15, count 0 2006.169.07:53:56.57#ibcon#about to read 5, iclass 15, count 0 2006.169.07:53:56.57#ibcon#read 5, iclass 15, count 0 2006.169.07:53:56.57#ibcon#about to read 6, iclass 15, count 0 2006.169.07:53:56.57#ibcon#read 6, iclass 15, count 0 2006.169.07:53:56.57#ibcon#end of sib2, iclass 15, count 0 2006.169.07:53:56.57#ibcon#*after write, iclass 15, count 0 2006.169.07:53:56.57#ibcon#*before return 0, iclass 15, count 0 2006.169.07:53:56.57#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:53:56.57#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:53:56.57#ibcon#about to clear, iclass 15 cls_cnt 0 2006.169.07:53:56.57#ibcon#cleared, iclass 15 cls_cnt 0 2006.169.07:53:56.57$vc4f8/valo=6,772.99 2006.169.07:53:56.57#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.169.07:53:56.57#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.169.07:53:56.57#ibcon#ireg 17 cls_cnt 0 2006.169.07:53:56.57#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:53:56.57#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:53:56.57#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:53:56.57#ibcon#enter wrdev, iclass 17, count 0 2006.169.07:53:56.57#ibcon#first serial, iclass 17, count 0 2006.169.07:53:56.57#ibcon#enter sib2, iclass 17, count 0 2006.169.07:53:56.57#ibcon#flushed, iclass 17, count 0 2006.169.07:53:56.57#ibcon#about to write, iclass 17, count 0 2006.169.07:53:56.57#ibcon#wrote, iclass 17, count 0 2006.169.07:53:56.57#ibcon#about to read 3, iclass 17, count 0 2006.169.07:53:56.59#ibcon#read 3, iclass 17, count 0 2006.169.07:53:56.59#ibcon#about to read 4, iclass 17, count 0 2006.169.07:53:56.59#ibcon#read 4, iclass 17, count 0 2006.169.07:53:56.59#ibcon#about to read 5, iclass 17, count 0 2006.169.07:53:56.59#ibcon#read 5, iclass 17, count 0 2006.169.07:53:56.59#ibcon#about to read 6, iclass 17, count 0 2006.169.07:53:56.59#ibcon#read 6, iclass 17, count 0 2006.169.07:53:56.59#ibcon#end of sib2, iclass 17, count 0 2006.169.07:53:56.59#ibcon#*mode == 0, iclass 17, count 0 2006.169.07:53:56.59#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.169.07:53:56.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.07:53:56.59#ibcon#*before write, iclass 17, count 0 2006.169.07:53:56.59#ibcon#enter sib2, iclass 17, count 0 2006.169.07:53:56.59#ibcon#flushed, iclass 17, count 0 2006.169.07:53:56.59#ibcon#about to write, iclass 17, count 0 2006.169.07:53:56.59#ibcon#wrote, iclass 17, count 0 2006.169.07:53:56.59#ibcon#about to read 3, iclass 17, count 0 2006.169.07:53:56.63#ibcon#read 3, iclass 17, count 0 2006.169.07:53:56.63#ibcon#about to read 4, iclass 17, count 0 2006.169.07:53:56.63#ibcon#read 4, iclass 17, count 0 2006.169.07:53:56.63#ibcon#about to read 5, iclass 17, count 0 2006.169.07:53:56.63#ibcon#read 5, iclass 17, count 0 2006.169.07:53:56.63#ibcon#about to read 6, iclass 17, count 0 2006.169.07:53:56.63#ibcon#read 6, iclass 17, count 0 2006.169.07:53:56.63#ibcon#end of sib2, iclass 17, count 0 2006.169.07:53:56.63#ibcon#*after write, iclass 17, count 0 2006.169.07:53:56.63#ibcon#*before return 0, iclass 17, count 0 2006.169.07:53:56.63#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:53:56.63#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:53:56.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.169.07:53:56.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.169.07:53:56.63$vc4f8/va=6,6 2006.169.07:53:56.63#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.169.07:53:56.63#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.169.07:53:56.63#ibcon#ireg 11 cls_cnt 2 2006.169.07:53:56.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:53:56.69#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:53:56.69#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:53:56.69#ibcon#enter wrdev, iclass 19, count 2 2006.169.07:53:56.69#ibcon#first serial, iclass 19, count 2 2006.169.07:53:56.69#ibcon#enter sib2, iclass 19, count 2 2006.169.07:53:56.69#ibcon#flushed, iclass 19, count 2 2006.169.07:53:56.69#ibcon#about to write, iclass 19, count 2 2006.169.07:53:56.69#ibcon#wrote, iclass 19, count 2 2006.169.07:53:56.69#ibcon#about to read 3, iclass 19, count 2 2006.169.07:53:56.71#ibcon#read 3, iclass 19, count 2 2006.169.07:53:56.71#ibcon#about to read 4, iclass 19, count 2 2006.169.07:53:56.71#ibcon#read 4, iclass 19, count 2 2006.169.07:53:56.71#ibcon#about to read 5, iclass 19, count 2 2006.169.07:53:56.71#ibcon#read 5, iclass 19, count 2 2006.169.07:53:56.71#ibcon#about to read 6, iclass 19, count 2 2006.169.07:53:56.71#ibcon#read 6, iclass 19, count 2 2006.169.07:53:56.71#ibcon#end of sib2, iclass 19, count 2 2006.169.07:53:56.71#ibcon#*mode == 0, iclass 19, count 2 2006.169.07:53:56.71#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.169.07:53:56.71#ibcon#[25=AT06-06\r\n] 2006.169.07:53:56.71#ibcon#*before write, iclass 19, count 2 2006.169.07:53:56.71#ibcon#enter sib2, iclass 19, count 2 2006.169.07:53:56.71#ibcon#flushed, iclass 19, count 2 2006.169.07:53:56.71#ibcon#about to write, iclass 19, count 2 2006.169.07:53:56.71#ibcon#wrote, iclass 19, count 2 2006.169.07:53:56.71#ibcon#about to read 3, iclass 19, count 2 2006.169.07:53:56.74#ibcon#read 3, iclass 19, count 2 2006.169.07:53:56.74#ibcon#about to read 4, iclass 19, count 2 2006.169.07:53:56.74#ibcon#read 4, iclass 19, count 2 2006.169.07:53:56.74#ibcon#about to read 5, iclass 19, count 2 2006.169.07:53:56.74#ibcon#read 5, iclass 19, count 2 2006.169.07:53:56.74#ibcon#about to read 6, iclass 19, count 2 2006.169.07:53:56.74#ibcon#read 6, iclass 19, count 2 2006.169.07:53:56.74#ibcon#end of sib2, iclass 19, count 2 2006.169.07:53:56.74#ibcon#*after write, iclass 19, count 2 2006.169.07:53:56.74#ibcon#*before return 0, iclass 19, count 2 2006.169.07:53:56.74#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:53:56.74#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:53:56.74#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.169.07:53:56.74#ibcon#ireg 7 cls_cnt 0 2006.169.07:53:56.74#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:53:56.86#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:53:56.86#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:53:56.86#ibcon#enter wrdev, iclass 19, count 0 2006.169.07:53:56.86#ibcon#first serial, iclass 19, count 0 2006.169.07:53:56.86#ibcon#enter sib2, iclass 19, count 0 2006.169.07:53:56.86#ibcon#flushed, iclass 19, count 0 2006.169.07:53:56.86#ibcon#about to write, iclass 19, count 0 2006.169.07:53:56.86#ibcon#wrote, iclass 19, count 0 2006.169.07:53:56.86#ibcon#about to read 3, iclass 19, count 0 2006.169.07:53:56.88#ibcon#read 3, iclass 19, count 0 2006.169.07:53:56.88#ibcon#about to read 4, iclass 19, count 0 2006.169.07:53:56.88#ibcon#read 4, iclass 19, count 0 2006.169.07:53:56.88#ibcon#about to read 5, iclass 19, count 0 2006.169.07:53:56.88#ibcon#read 5, iclass 19, count 0 2006.169.07:53:56.88#ibcon#about to read 6, iclass 19, count 0 2006.169.07:53:56.88#ibcon#read 6, iclass 19, count 0 2006.169.07:53:56.88#ibcon#end of sib2, iclass 19, count 0 2006.169.07:53:56.88#ibcon#*mode == 0, iclass 19, count 0 2006.169.07:53:56.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.169.07:53:56.88#ibcon#[25=USB\r\n] 2006.169.07:53:56.88#ibcon#*before write, iclass 19, count 0 2006.169.07:53:56.88#ibcon#enter sib2, iclass 19, count 0 2006.169.07:53:56.88#ibcon#flushed, iclass 19, count 0 2006.169.07:53:56.88#ibcon#about to write, iclass 19, count 0 2006.169.07:53:56.88#ibcon#wrote, iclass 19, count 0 2006.169.07:53:56.88#ibcon#about to read 3, iclass 19, count 0 2006.169.07:53:56.91#ibcon#read 3, iclass 19, count 0 2006.169.07:53:56.91#ibcon#about to read 4, iclass 19, count 0 2006.169.07:53:56.91#ibcon#read 4, iclass 19, count 0 2006.169.07:53:56.91#ibcon#about to read 5, iclass 19, count 0 2006.169.07:53:56.91#ibcon#read 5, iclass 19, count 0 2006.169.07:53:56.91#ibcon#about to read 6, iclass 19, count 0 2006.169.07:53:56.91#ibcon#read 6, iclass 19, count 0 2006.169.07:53:56.91#ibcon#end of sib2, iclass 19, count 0 2006.169.07:53:56.91#ibcon#*after write, iclass 19, count 0 2006.169.07:53:56.91#ibcon#*before return 0, iclass 19, count 0 2006.169.07:53:56.91#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:53:56.91#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:53:56.91#ibcon#about to clear, iclass 19 cls_cnt 0 2006.169.07:53:56.91#ibcon#cleared, iclass 19 cls_cnt 0 2006.169.07:53:56.91$vc4f8/valo=7,832.99 2006.169.07:53:56.91#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.169.07:53:56.91#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.169.07:53:56.91#ibcon#ireg 17 cls_cnt 0 2006.169.07:53:56.91#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:53:56.91#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:53:56.91#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:53:56.91#ibcon#enter wrdev, iclass 21, count 0 2006.169.07:53:56.91#ibcon#first serial, iclass 21, count 0 2006.169.07:53:56.91#ibcon#enter sib2, iclass 21, count 0 2006.169.07:53:56.91#ibcon#flushed, iclass 21, count 0 2006.169.07:53:56.91#ibcon#about to write, iclass 21, count 0 2006.169.07:53:56.91#ibcon#wrote, iclass 21, count 0 2006.169.07:53:56.91#ibcon#about to read 3, iclass 21, count 0 2006.169.07:53:56.93#ibcon#read 3, iclass 21, count 0 2006.169.07:53:56.93#ibcon#about to read 4, iclass 21, count 0 2006.169.07:53:56.93#ibcon#read 4, iclass 21, count 0 2006.169.07:53:56.93#ibcon#about to read 5, iclass 21, count 0 2006.169.07:53:56.93#ibcon#read 5, iclass 21, count 0 2006.169.07:53:56.93#ibcon#about to read 6, iclass 21, count 0 2006.169.07:53:56.93#ibcon#read 6, iclass 21, count 0 2006.169.07:53:56.93#ibcon#end of sib2, iclass 21, count 0 2006.169.07:53:56.93#ibcon#*mode == 0, iclass 21, count 0 2006.169.07:53:56.93#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.169.07:53:56.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.07:53:56.93#ibcon#*before write, iclass 21, count 0 2006.169.07:53:56.93#ibcon#enter sib2, iclass 21, count 0 2006.169.07:53:56.93#ibcon#flushed, iclass 21, count 0 2006.169.07:53:56.93#ibcon#about to write, iclass 21, count 0 2006.169.07:53:56.93#ibcon#wrote, iclass 21, count 0 2006.169.07:53:56.93#ibcon#about to read 3, iclass 21, count 0 2006.169.07:53:56.97#ibcon#read 3, iclass 21, count 0 2006.169.07:53:56.97#ibcon#about to read 4, iclass 21, count 0 2006.169.07:53:56.97#ibcon#read 4, iclass 21, count 0 2006.169.07:53:56.97#ibcon#about to read 5, iclass 21, count 0 2006.169.07:53:56.97#ibcon#read 5, iclass 21, count 0 2006.169.07:53:56.97#ibcon#about to read 6, iclass 21, count 0 2006.169.07:53:56.97#ibcon#read 6, iclass 21, count 0 2006.169.07:53:56.97#ibcon#end of sib2, iclass 21, count 0 2006.169.07:53:56.97#ibcon#*after write, iclass 21, count 0 2006.169.07:53:56.97#ibcon#*before return 0, iclass 21, count 0 2006.169.07:53:56.97#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:53:56.97#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:53:56.97#ibcon#about to clear, iclass 21 cls_cnt 0 2006.169.07:53:56.97#ibcon#cleared, iclass 21 cls_cnt 0 2006.169.07:53:56.97$vc4f8/va=7,6 2006.169.07:53:56.97#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.169.07:53:56.97#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.169.07:53:56.97#ibcon#ireg 11 cls_cnt 2 2006.169.07:53:56.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.169.07:53:57.03#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.169.07:53:57.03#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.169.07:53:57.03#ibcon#enter wrdev, iclass 23, count 2 2006.169.07:53:57.03#ibcon#first serial, iclass 23, count 2 2006.169.07:53:57.03#ibcon#enter sib2, iclass 23, count 2 2006.169.07:53:57.03#ibcon#flushed, iclass 23, count 2 2006.169.07:53:57.03#ibcon#about to write, iclass 23, count 2 2006.169.07:53:57.03#ibcon#wrote, iclass 23, count 2 2006.169.07:53:57.03#ibcon#about to read 3, iclass 23, count 2 2006.169.07:53:57.05#ibcon#read 3, iclass 23, count 2 2006.169.07:53:57.05#ibcon#about to read 4, iclass 23, count 2 2006.169.07:53:57.05#ibcon#read 4, iclass 23, count 2 2006.169.07:53:57.05#ibcon#about to read 5, iclass 23, count 2 2006.169.07:53:57.05#ibcon#read 5, iclass 23, count 2 2006.169.07:53:57.05#ibcon#about to read 6, iclass 23, count 2 2006.169.07:53:57.05#ibcon#read 6, iclass 23, count 2 2006.169.07:53:57.05#ibcon#end of sib2, iclass 23, count 2 2006.169.07:53:57.05#ibcon#*mode == 0, iclass 23, count 2 2006.169.07:53:57.05#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.169.07:53:57.05#ibcon#[25=AT07-06\r\n] 2006.169.07:53:57.05#ibcon#*before write, iclass 23, count 2 2006.169.07:53:57.05#ibcon#enter sib2, iclass 23, count 2 2006.169.07:53:57.05#ibcon#flushed, iclass 23, count 2 2006.169.07:53:57.05#ibcon#about to write, iclass 23, count 2 2006.169.07:53:57.05#ibcon#wrote, iclass 23, count 2 2006.169.07:53:57.05#ibcon#about to read 3, iclass 23, count 2 2006.169.07:53:57.08#ibcon#read 3, iclass 23, count 2 2006.169.07:53:57.08#ibcon#about to read 4, iclass 23, count 2 2006.169.07:53:57.08#ibcon#read 4, iclass 23, count 2 2006.169.07:53:57.08#ibcon#about to read 5, iclass 23, count 2 2006.169.07:53:57.08#ibcon#read 5, iclass 23, count 2 2006.169.07:53:57.08#ibcon#about to read 6, iclass 23, count 2 2006.169.07:53:57.08#ibcon#read 6, iclass 23, count 2 2006.169.07:53:57.08#ibcon#end of sib2, iclass 23, count 2 2006.169.07:53:57.08#ibcon#*after write, iclass 23, count 2 2006.169.07:53:57.08#ibcon#*before return 0, iclass 23, count 2 2006.169.07:53:57.08#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.169.07:53:57.08#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.169.07:53:57.08#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.169.07:53:57.08#ibcon#ireg 7 cls_cnt 0 2006.169.07:53:57.08#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.169.07:53:57.13#trakl#Source acquired 2006.169.07:53:57.20#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.169.07:53:57.20#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.169.07:53:57.20#ibcon#enter wrdev, iclass 23, count 0 2006.169.07:53:57.20#ibcon#first serial, iclass 23, count 0 2006.169.07:53:57.20#ibcon#enter sib2, iclass 23, count 0 2006.169.07:53:57.20#ibcon#flushed, iclass 23, count 0 2006.169.07:53:57.20#ibcon#about to write, iclass 23, count 0 2006.169.07:53:57.20#ibcon#wrote, iclass 23, count 0 2006.169.07:53:57.20#ibcon#about to read 3, iclass 23, count 0 2006.169.07:53:57.22#ibcon#read 3, iclass 23, count 0 2006.169.07:53:57.22#ibcon#about to read 4, iclass 23, count 0 2006.169.07:53:57.22#ibcon#read 4, iclass 23, count 0 2006.169.07:53:57.22#ibcon#about to read 5, iclass 23, count 0 2006.169.07:53:57.22#ibcon#read 5, iclass 23, count 0 2006.169.07:53:57.22#ibcon#about to read 6, iclass 23, count 0 2006.169.07:53:57.22#ibcon#read 6, iclass 23, count 0 2006.169.07:53:57.22#ibcon#end of sib2, iclass 23, count 0 2006.169.07:53:57.22#ibcon#*mode == 0, iclass 23, count 0 2006.169.07:53:57.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.169.07:53:57.22#ibcon#[25=USB\r\n] 2006.169.07:53:57.22#ibcon#*before write, iclass 23, count 0 2006.169.07:53:57.22#ibcon#enter sib2, iclass 23, count 0 2006.169.07:53:57.22#ibcon#flushed, iclass 23, count 0 2006.169.07:53:57.22#ibcon#about to write, iclass 23, count 0 2006.169.07:53:57.22#ibcon#wrote, iclass 23, count 0 2006.169.07:53:57.22#ibcon#about to read 3, iclass 23, count 0 2006.169.07:53:57.25#ibcon#read 3, iclass 23, count 0 2006.169.07:53:57.25#ibcon#about to read 4, iclass 23, count 0 2006.169.07:53:57.25#ibcon#read 4, iclass 23, count 0 2006.169.07:53:57.25#ibcon#about to read 5, iclass 23, count 0 2006.169.07:53:57.25#ibcon#read 5, iclass 23, count 0 2006.169.07:53:57.25#ibcon#about to read 6, iclass 23, count 0 2006.169.07:53:57.25#ibcon#read 6, iclass 23, count 0 2006.169.07:53:57.25#ibcon#end of sib2, iclass 23, count 0 2006.169.07:53:57.25#ibcon#*after write, iclass 23, count 0 2006.169.07:53:57.25#ibcon#*before return 0, iclass 23, count 0 2006.169.07:53:57.25#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.169.07:53:57.25#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.169.07:53:57.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.169.07:53:57.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.169.07:53:57.25$vc4f8/valo=8,852.99 2006.169.07:53:57.25#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.169.07:53:57.25#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.169.07:53:57.25#ibcon#ireg 17 cls_cnt 0 2006.169.07:53:57.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:53:57.25#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:53:57.25#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:53:57.25#ibcon#enter wrdev, iclass 25, count 0 2006.169.07:53:57.25#ibcon#first serial, iclass 25, count 0 2006.169.07:53:57.25#ibcon#enter sib2, iclass 25, count 0 2006.169.07:53:57.25#ibcon#flushed, iclass 25, count 0 2006.169.07:53:57.25#ibcon#about to write, iclass 25, count 0 2006.169.07:53:57.25#ibcon#wrote, iclass 25, count 0 2006.169.07:53:57.25#ibcon#about to read 3, iclass 25, count 0 2006.169.07:53:57.27#ibcon#read 3, iclass 25, count 0 2006.169.07:53:57.27#ibcon#about to read 4, iclass 25, count 0 2006.169.07:53:57.27#ibcon#read 4, iclass 25, count 0 2006.169.07:53:57.27#ibcon#about to read 5, iclass 25, count 0 2006.169.07:53:57.27#ibcon#read 5, iclass 25, count 0 2006.169.07:53:57.27#ibcon#about to read 6, iclass 25, count 0 2006.169.07:53:57.27#ibcon#read 6, iclass 25, count 0 2006.169.07:53:57.27#ibcon#end of sib2, iclass 25, count 0 2006.169.07:53:57.27#ibcon#*mode == 0, iclass 25, count 0 2006.169.07:53:57.27#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.169.07:53:57.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.07:53:57.27#ibcon#*before write, iclass 25, count 0 2006.169.07:53:57.27#ibcon#enter sib2, iclass 25, count 0 2006.169.07:53:57.27#ibcon#flushed, iclass 25, count 0 2006.169.07:53:57.27#ibcon#about to write, iclass 25, count 0 2006.169.07:53:57.27#ibcon#wrote, iclass 25, count 0 2006.169.07:53:57.27#ibcon#about to read 3, iclass 25, count 0 2006.169.07:53:57.31#ibcon#read 3, iclass 25, count 0 2006.169.07:53:57.31#ibcon#about to read 4, iclass 25, count 0 2006.169.07:53:57.31#ibcon#read 4, iclass 25, count 0 2006.169.07:53:57.31#ibcon#about to read 5, iclass 25, count 0 2006.169.07:53:57.31#ibcon#read 5, iclass 25, count 0 2006.169.07:53:57.31#ibcon#about to read 6, iclass 25, count 0 2006.169.07:53:57.31#ibcon#read 6, iclass 25, count 0 2006.169.07:53:57.31#ibcon#end of sib2, iclass 25, count 0 2006.169.07:53:57.31#ibcon#*after write, iclass 25, count 0 2006.169.07:53:57.31#ibcon#*before return 0, iclass 25, count 0 2006.169.07:53:57.31#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:53:57.31#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.169.07:53:57.31#ibcon#about to clear, iclass 25 cls_cnt 0 2006.169.07:53:57.31#ibcon#cleared, iclass 25 cls_cnt 0 2006.169.07:53:57.31$vc4f8/va=8,7 2006.169.07:53:57.31#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.169.07:53:57.31#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.169.07:53:57.31#ibcon#ireg 11 cls_cnt 2 2006.169.07:53:57.31#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.169.07:53:57.37#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.169.07:53:57.37#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.169.07:53:57.37#ibcon#enter wrdev, iclass 27, count 2 2006.169.07:53:57.37#ibcon#first serial, iclass 27, count 2 2006.169.07:53:57.37#ibcon#enter sib2, iclass 27, count 2 2006.169.07:53:57.37#ibcon#flushed, iclass 27, count 2 2006.169.07:53:57.37#ibcon#about to write, iclass 27, count 2 2006.169.07:53:57.37#ibcon#wrote, iclass 27, count 2 2006.169.07:53:57.37#ibcon#about to read 3, iclass 27, count 2 2006.169.07:53:57.39#ibcon#read 3, iclass 27, count 2 2006.169.07:53:57.39#ibcon#about to read 4, iclass 27, count 2 2006.169.07:53:57.39#ibcon#read 4, iclass 27, count 2 2006.169.07:53:57.39#ibcon#about to read 5, iclass 27, count 2 2006.169.07:53:57.39#ibcon#read 5, iclass 27, count 2 2006.169.07:53:57.39#ibcon#about to read 6, iclass 27, count 2 2006.169.07:53:57.39#ibcon#read 6, iclass 27, count 2 2006.169.07:53:57.39#ibcon#end of sib2, iclass 27, count 2 2006.169.07:53:57.39#ibcon#*mode == 0, iclass 27, count 2 2006.169.07:53:57.39#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.169.07:53:57.39#ibcon#[25=AT08-07\r\n] 2006.169.07:53:57.39#ibcon#*before write, iclass 27, count 2 2006.169.07:53:57.39#ibcon#enter sib2, iclass 27, count 2 2006.169.07:53:57.39#ibcon#flushed, iclass 27, count 2 2006.169.07:53:57.39#ibcon#about to write, iclass 27, count 2 2006.169.07:53:57.39#ibcon#wrote, iclass 27, count 2 2006.169.07:53:57.39#ibcon#about to read 3, iclass 27, count 2 2006.169.07:53:57.42#ibcon#read 3, iclass 27, count 2 2006.169.07:53:57.42#ibcon#about to read 4, iclass 27, count 2 2006.169.07:53:57.42#ibcon#read 4, iclass 27, count 2 2006.169.07:53:57.42#ibcon#about to read 5, iclass 27, count 2 2006.169.07:53:57.42#ibcon#read 5, iclass 27, count 2 2006.169.07:53:57.42#ibcon#about to read 6, iclass 27, count 2 2006.169.07:53:57.42#ibcon#read 6, iclass 27, count 2 2006.169.07:53:57.42#ibcon#end of sib2, iclass 27, count 2 2006.169.07:53:57.42#ibcon#*after write, iclass 27, count 2 2006.169.07:53:57.42#ibcon#*before return 0, iclass 27, count 2 2006.169.07:53:57.42#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.169.07:53:57.42#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.169.07:53:57.42#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.169.07:53:57.42#ibcon#ireg 7 cls_cnt 0 2006.169.07:53:57.42#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.169.07:53:57.54#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.169.07:53:57.54#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.169.07:53:57.54#ibcon#enter wrdev, iclass 27, count 0 2006.169.07:53:57.54#ibcon#first serial, iclass 27, count 0 2006.169.07:53:57.54#ibcon#enter sib2, iclass 27, count 0 2006.169.07:53:57.54#ibcon#flushed, iclass 27, count 0 2006.169.07:53:57.54#ibcon#about to write, iclass 27, count 0 2006.169.07:53:57.54#ibcon#wrote, iclass 27, count 0 2006.169.07:53:57.54#ibcon#about to read 3, iclass 27, count 0 2006.169.07:53:57.56#ibcon#read 3, iclass 27, count 0 2006.169.07:53:57.56#ibcon#about to read 4, iclass 27, count 0 2006.169.07:53:57.56#ibcon#read 4, iclass 27, count 0 2006.169.07:53:57.56#ibcon#about to read 5, iclass 27, count 0 2006.169.07:53:57.56#ibcon#read 5, iclass 27, count 0 2006.169.07:53:57.56#ibcon#about to read 6, iclass 27, count 0 2006.169.07:53:57.56#ibcon#read 6, iclass 27, count 0 2006.169.07:53:57.56#ibcon#end of sib2, iclass 27, count 0 2006.169.07:53:57.56#ibcon#*mode == 0, iclass 27, count 0 2006.169.07:53:57.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.169.07:53:57.56#ibcon#[25=USB\r\n] 2006.169.07:53:57.56#ibcon#*before write, iclass 27, count 0 2006.169.07:53:57.56#ibcon#enter sib2, iclass 27, count 0 2006.169.07:53:57.56#ibcon#flushed, iclass 27, count 0 2006.169.07:53:57.56#ibcon#about to write, iclass 27, count 0 2006.169.07:53:57.56#ibcon#wrote, iclass 27, count 0 2006.169.07:53:57.56#ibcon#about to read 3, iclass 27, count 0 2006.169.07:53:57.59#ibcon#read 3, iclass 27, count 0 2006.169.07:53:57.59#ibcon#about to read 4, iclass 27, count 0 2006.169.07:53:57.59#ibcon#read 4, iclass 27, count 0 2006.169.07:53:57.59#ibcon#about to read 5, iclass 27, count 0 2006.169.07:53:57.59#ibcon#read 5, iclass 27, count 0 2006.169.07:53:57.59#ibcon#about to read 6, iclass 27, count 0 2006.169.07:53:57.59#ibcon#read 6, iclass 27, count 0 2006.169.07:53:57.59#ibcon#end of sib2, iclass 27, count 0 2006.169.07:53:57.59#ibcon#*after write, iclass 27, count 0 2006.169.07:53:57.59#ibcon#*before return 0, iclass 27, count 0 2006.169.07:53:57.59#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.169.07:53:57.59#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.169.07:53:57.59#ibcon#about to clear, iclass 27 cls_cnt 0 2006.169.07:53:57.59#ibcon#cleared, iclass 27 cls_cnt 0 2006.169.07:53:57.59$vc4f8/vblo=1,632.99 2006.169.07:53:57.59#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.169.07:53:57.59#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.169.07:53:57.59#ibcon#ireg 17 cls_cnt 0 2006.169.07:53:57.59#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.169.07:53:57.59#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.169.07:53:57.59#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.169.07:53:57.59#ibcon#enter wrdev, iclass 29, count 0 2006.169.07:53:57.59#ibcon#first serial, iclass 29, count 0 2006.169.07:53:57.59#ibcon#enter sib2, iclass 29, count 0 2006.169.07:53:57.59#ibcon#flushed, iclass 29, count 0 2006.169.07:53:57.59#ibcon#about to write, iclass 29, count 0 2006.169.07:53:57.59#ibcon#wrote, iclass 29, count 0 2006.169.07:53:57.59#ibcon#about to read 3, iclass 29, count 0 2006.169.07:53:57.61#ibcon#read 3, iclass 29, count 0 2006.169.07:53:57.61#ibcon#about to read 4, iclass 29, count 0 2006.169.07:53:57.61#ibcon#read 4, iclass 29, count 0 2006.169.07:53:57.61#ibcon#about to read 5, iclass 29, count 0 2006.169.07:53:57.61#ibcon#read 5, iclass 29, count 0 2006.169.07:53:57.61#ibcon#about to read 6, iclass 29, count 0 2006.169.07:53:57.61#ibcon#read 6, iclass 29, count 0 2006.169.07:53:57.61#ibcon#end of sib2, iclass 29, count 0 2006.169.07:53:57.61#ibcon#*mode == 0, iclass 29, count 0 2006.169.07:53:57.61#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.169.07:53:57.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.07:53:57.61#ibcon#*before write, iclass 29, count 0 2006.169.07:53:57.61#ibcon#enter sib2, iclass 29, count 0 2006.169.07:53:57.61#ibcon#flushed, iclass 29, count 0 2006.169.07:53:57.61#ibcon#about to write, iclass 29, count 0 2006.169.07:53:57.61#ibcon#wrote, iclass 29, count 0 2006.169.07:53:57.61#ibcon#about to read 3, iclass 29, count 0 2006.169.07:53:57.65#ibcon#read 3, iclass 29, count 0 2006.169.07:53:57.65#ibcon#about to read 4, iclass 29, count 0 2006.169.07:53:57.65#ibcon#read 4, iclass 29, count 0 2006.169.07:53:57.65#ibcon#about to read 5, iclass 29, count 0 2006.169.07:53:57.65#ibcon#read 5, iclass 29, count 0 2006.169.07:53:57.65#ibcon#about to read 6, iclass 29, count 0 2006.169.07:53:57.65#ibcon#read 6, iclass 29, count 0 2006.169.07:53:57.65#ibcon#end of sib2, iclass 29, count 0 2006.169.07:53:57.65#ibcon#*after write, iclass 29, count 0 2006.169.07:53:57.65#ibcon#*before return 0, iclass 29, count 0 2006.169.07:53:57.65#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.169.07:53:57.65#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.169.07:53:57.65#ibcon#about to clear, iclass 29 cls_cnt 0 2006.169.07:53:57.65#ibcon#cleared, iclass 29 cls_cnt 0 2006.169.07:53:57.65$vc4f8/vb=1,4 2006.169.07:53:57.65#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.169.07:53:57.65#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.169.07:53:57.65#ibcon#ireg 11 cls_cnt 2 2006.169.07:53:57.65#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.169.07:53:57.65#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.169.07:53:57.65#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.169.07:53:57.65#ibcon#enter wrdev, iclass 31, count 2 2006.169.07:53:57.65#ibcon#first serial, iclass 31, count 2 2006.169.07:53:57.65#ibcon#enter sib2, iclass 31, count 2 2006.169.07:53:57.65#ibcon#flushed, iclass 31, count 2 2006.169.07:53:57.65#ibcon#about to write, iclass 31, count 2 2006.169.07:53:57.65#ibcon#wrote, iclass 31, count 2 2006.169.07:53:57.65#ibcon#about to read 3, iclass 31, count 2 2006.169.07:53:57.67#ibcon#read 3, iclass 31, count 2 2006.169.07:53:57.67#ibcon#about to read 4, iclass 31, count 2 2006.169.07:53:57.67#ibcon#read 4, iclass 31, count 2 2006.169.07:53:57.67#ibcon#about to read 5, iclass 31, count 2 2006.169.07:53:57.67#ibcon#read 5, iclass 31, count 2 2006.169.07:53:57.67#ibcon#about to read 6, iclass 31, count 2 2006.169.07:53:57.67#ibcon#read 6, iclass 31, count 2 2006.169.07:53:57.67#ibcon#end of sib2, iclass 31, count 2 2006.169.07:53:57.67#ibcon#*mode == 0, iclass 31, count 2 2006.169.07:53:57.67#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.169.07:53:57.67#ibcon#[27=AT01-04\r\n] 2006.169.07:53:57.67#ibcon#*before write, iclass 31, count 2 2006.169.07:53:57.67#ibcon#enter sib2, iclass 31, count 2 2006.169.07:53:57.67#ibcon#flushed, iclass 31, count 2 2006.169.07:53:57.67#ibcon#about to write, iclass 31, count 2 2006.169.07:53:57.67#ibcon#wrote, iclass 31, count 2 2006.169.07:53:57.67#ibcon#about to read 3, iclass 31, count 2 2006.169.07:53:57.70#ibcon#read 3, iclass 31, count 2 2006.169.07:53:57.70#ibcon#about to read 4, iclass 31, count 2 2006.169.07:53:57.70#ibcon#read 4, iclass 31, count 2 2006.169.07:53:57.70#ibcon#about to read 5, iclass 31, count 2 2006.169.07:53:57.70#ibcon#read 5, iclass 31, count 2 2006.169.07:53:57.70#ibcon#about to read 6, iclass 31, count 2 2006.169.07:53:57.70#ibcon#read 6, iclass 31, count 2 2006.169.07:53:57.70#ibcon#end of sib2, iclass 31, count 2 2006.169.07:53:57.70#ibcon#*after write, iclass 31, count 2 2006.169.07:53:57.70#ibcon#*before return 0, iclass 31, count 2 2006.169.07:53:57.70#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.169.07:53:57.70#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.169.07:53:57.70#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.169.07:53:57.70#ibcon#ireg 7 cls_cnt 0 2006.169.07:53:57.70#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.169.07:53:57.82#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.169.07:53:57.82#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.169.07:53:57.82#ibcon#enter wrdev, iclass 31, count 0 2006.169.07:53:57.82#ibcon#first serial, iclass 31, count 0 2006.169.07:53:57.82#ibcon#enter sib2, iclass 31, count 0 2006.169.07:53:57.82#ibcon#flushed, iclass 31, count 0 2006.169.07:53:57.82#ibcon#about to write, iclass 31, count 0 2006.169.07:53:57.82#ibcon#wrote, iclass 31, count 0 2006.169.07:53:57.82#ibcon#about to read 3, iclass 31, count 0 2006.169.07:53:57.84#ibcon#read 3, iclass 31, count 0 2006.169.07:53:57.84#ibcon#about to read 4, iclass 31, count 0 2006.169.07:53:57.84#ibcon#read 4, iclass 31, count 0 2006.169.07:53:57.84#ibcon#about to read 5, iclass 31, count 0 2006.169.07:53:57.84#ibcon#read 5, iclass 31, count 0 2006.169.07:53:57.84#ibcon#about to read 6, iclass 31, count 0 2006.169.07:53:57.84#ibcon#read 6, iclass 31, count 0 2006.169.07:53:57.84#ibcon#end of sib2, iclass 31, count 0 2006.169.07:53:57.84#ibcon#*mode == 0, iclass 31, count 0 2006.169.07:53:57.84#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.169.07:53:57.84#ibcon#[27=USB\r\n] 2006.169.07:53:57.84#ibcon#*before write, iclass 31, count 0 2006.169.07:53:57.84#ibcon#enter sib2, iclass 31, count 0 2006.169.07:53:57.84#ibcon#flushed, iclass 31, count 0 2006.169.07:53:57.84#ibcon#about to write, iclass 31, count 0 2006.169.07:53:57.84#ibcon#wrote, iclass 31, count 0 2006.169.07:53:57.84#ibcon#about to read 3, iclass 31, count 0 2006.169.07:53:57.87#ibcon#read 3, iclass 31, count 0 2006.169.07:53:57.87#ibcon#about to read 4, iclass 31, count 0 2006.169.07:53:57.87#ibcon#read 4, iclass 31, count 0 2006.169.07:53:57.87#ibcon#about to read 5, iclass 31, count 0 2006.169.07:53:57.87#ibcon#read 5, iclass 31, count 0 2006.169.07:53:57.87#ibcon#about to read 6, iclass 31, count 0 2006.169.07:53:57.87#ibcon#read 6, iclass 31, count 0 2006.169.07:53:57.87#ibcon#end of sib2, iclass 31, count 0 2006.169.07:53:57.87#ibcon#*after write, iclass 31, count 0 2006.169.07:53:57.87#ibcon#*before return 0, iclass 31, count 0 2006.169.07:53:57.87#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.169.07:53:57.87#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.169.07:53:57.87#ibcon#about to clear, iclass 31 cls_cnt 0 2006.169.07:53:57.87#ibcon#cleared, iclass 31 cls_cnt 0 2006.169.07:53:57.87$vc4f8/vblo=2,640.99 2006.169.07:53:57.87#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.169.07:53:57.87#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.169.07:53:57.87#ibcon#ireg 17 cls_cnt 0 2006.169.07:53:57.87#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:53:57.87#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:53:57.87#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:53:57.87#ibcon#enter wrdev, iclass 33, count 0 2006.169.07:53:57.87#ibcon#first serial, iclass 33, count 0 2006.169.07:53:57.87#ibcon#enter sib2, iclass 33, count 0 2006.169.07:53:57.87#ibcon#flushed, iclass 33, count 0 2006.169.07:53:57.87#ibcon#about to write, iclass 33, count 0 2006.169.07:53:57.87#ibcon#wrote, iclass 33, count 0 2006.169.07:53:57.87#ibcon#about to read 3, iclass 33, count 0 2006.169.07:53:57.89#ibcon#read 3, iclass 33, count 0 2006.169.07:53:57.89#ibcon#about to read 4, iclass 33, count 0 2006.169.07:53:57.89#ibcon#read 4, iclass 33, count 0 2006.169.07:53:57.89#ibcon#about to read 5, iclass 33, count 0 2006.169.07:53:57.89#ibcon#read 5, iclass 33, count 0 2006.169.07:53:57.89#ibcon#about to read 6, iclass 33, count 0 2006.169.07:53:57.89#ibcon#read 6, iclass 33, count 0 2006.169.07:53:57.89#ibcon#end of sib2, iclass 33, count 0 2006.169.07:53:57.89#ibcon#*mode == 0, iclass 33, count 0 2006.169.07:53:57.89#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.169.07:53:57.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.07:53:57.89#ibcon#*before write, iclass 33, count 0 2006.169.07:53:57.89#ibcon#enter sib2, iclass 33, count 0 2006.169.07:53:57.89#ibcon#flushed, iclass 33, count 0 2006.169.07:53:57.89#ibcon#about to write, iclass 33, count 0 2006.169.07:53:57.89#ibcon#wrote, iclass 33, count 0 2006.169.07:53:57.89#ibcon#about to read 3, iclass 33, count 0 2006.169.07:53:57.93#ibcon#read 3, iclass 33, count 0 2006.169.07:53:57.93#ibcon#about to read 4, iclass 33, count 0 2006.169.07:53:57.93#ibcon#read 4, iclass 33, count 0 2006.169.07:53:57.93#ibcon#about to read 5, iclass 33, count 0 2006.169.07:53:57.93#ibcon#read 5, iclass 33, count 0 2006.169.07:53:57.93#ibcon#about to read 6, iclass 33, count 0 2006.169.07:53:57.93#ibcon#read 6, iclass 33, count 0 2006.169.07:53:57.93#ibcon#end of sib2, iclass 33, count 0 2006.169.07:53:57.93#ibcon#*after write, iclass 33, count 0 2006.169.07:53:57.93#ibcon#*before return 0, iclass 33, count 0 2006.169.07:53:57.93#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:53:57.93#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.169.07:53:57.93#ibcon#about to clear, iclass 33 cls_cnt 0 2006.169.07:53:57.93#ibcon#cleared, iclass 33 cls_cnt 0 2006.169.07:53:57.93$vc4f8/vb=2,4 2006.169.07:53:57.93#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.169.07:53:57.93#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.169.07:53:57.93#ibcon#ireg 11 cls_cnt 2 2006.169.07:53:57.93#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:53:57.99#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:53:57.99#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:53:57.99#ibcon#enter wrdev, iclass 35, count 2 2006.169.07:53:57.99#ibcon#first serial, iclass 35, count 2 2006.169.07:53:57.99#ibcon#enter sib2, iclass 35, count 2 2006.169.07:53:57.99#ibcon#flushed, iclass 35, count 2 2006.169.07:53:57.99#ibcon#about to write, iclass 35, count 2 2006.169.07:53:57.99#ibcon#wrote, iclass 35, count 2 2006.169.07:53:57.99#ibcon#about to read 3, iclass 35, count 2 2006.169.07:53:58.01#ibcon#read 3, iclass 35, count 2 2006.169.07:53:58.01#ibcon#about to read 4, iclass 35, count 2 2006.169.07:53:58.01#ibcon#read 4, iclass 35, count 2 2006.169.07:53:58.01#ibcon#about to read 5, iclass 35, count 2 2006.169.07:53:58.01#ibcon#read 5, iclass 35, count 2 2006.169.07:53:58.01#ibcon#about to read 6, iclass 35, count 2 2006.169.07:53:58.01#ibcon#read 6, iclass 35, count 2 2006.169.07:53:58.01#ibcon#end of sib2, iclass 35, count 2 2006.169.07:53:58.01#ibcon#*mode == 0, iclass 35, count 2 2006.169.07:53:58.01#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.169.07:53:58.01#ibcon#[27=AT02-04\r\n] 2006.169.07:53:58.01#ibcon#*before write, iclass 35, count 2 2006.169.07:53:58.01#ibcon#enter sib2, iclass 35, count 2 2006.169.07:53:58.01#ibcon#flushed, iclass 35, count 2 2006.169.07:53:58.01#ibcon#about to write, iclass 35, count 2 2006.169.07:53:58.01#ibcon#wrote, iclass 35, count 2 2006.169.07:53:58.01#ibcon#about to read 3, iclass 35, count 2 2006.169.07:53:58.04#ibcon#read 3, iclass 35, count 2 2006.169.07:53:58.04#ibcon#about to read 4, iclass 35, count 2 2006.169.07:53:58.04#ibcon#read 4, iclass 35, count 2 2006.169.07:53:58.04#ibcon#about to read 5, iclass 35, count 2 2006.169.07:53:58.04#ibcon#read 5, iclass 35, count 2 2006.169.07:53:58.04#ibcon#about to read 6, iclass 35, count 2 2006.169.07:53:58.04#ibcon#read 6, iclass 35, count 2 2006.169.07:53:58.04#ibcon#end of sib2, iclass 35, count 2 2006.169.07:53:58.04#ibcon#*after write, iclass 35, count 2 2006.169.07:53:58.04#ibcon#*before return 0, iclass 35, count 2 2006.169.07:53:58.04#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:53:58.04#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.169.07:53:58.04#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.169.07:53:58.04#ibcon#ireg 7 cls_cnt 0 2006.169.07:53:58.04#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:53:58.13#flagr#flagr/antenna,acquired 2006.169.07:53:58.16#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:53:58.16#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:53:58.16#ibcon#enter wrdev, iclass 35, count 0 2006.169.07:53:58.16#ibcon#first serial, iclass 35, count 0 2006.169.07:53:58.16#ibcon#enter sib2, iclass 35, count 0 2006.169.07:53:58.16#ibcon#flushed, iclass 35, count 0 2006.169.07:53:58.16#ibcon#about to write, iclass 35, count 0 2006.169.07:53:58.16#ibcon#wrote, iclass 35, count 0 2006.169.07:53:58.16#ibcon#about to read 3, iclass 35, count 0 2006.169.07:53:58.18#ibcon#read 3, iclass 35, count 0 2006.169.07:53:58.18#ibcon#about to read 4, iclass 35, count 0 2006.169.07:53:58.18#ibcon#read 4, iclass 35, count 0 2006.169.07:53:58.18#ibcon#about to read 5, iclass 35, count 0 2006.169.07:53:58.18#ibcon#read 5, iclass 35, count 0 2006.169.07:53:58.18#ibcon#about to read 6, iclass 35, count 0 2006.169.07:53:58.18#ibcon#read 6, iclass 35, count 0 2006.169.07:53:58.18#ibcon#end of sib2, iclass 35, count 0 2006.169.07:53:58.18#ibcon#*mode == 0, iclass 35, count 0 2006.169.07:53:58.18#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.169.07:53:58.18#ibcon#[27=USB\r\n] 2006.169.07:53:58.18#ibcon#*before write, iclass 35, count 0 2006.169.07:53:58.18#ibcon#enter sib2, iclass 35, count 0 2006.169.07:53:58.18#ibcon#flushed, iclass 35, count 0 2006.169.07:53:58.18#ibcon#about to write, iclass 35, count 0 2006.169.07:53:58.18#ibcon#wrote, iclass 35, count 0 2006.169.07:53:58.18#ibcon#about to read 3, iclass 35, count 0 2006.169.07:53:58.21#ibcon#read 3, iclass 35, count 0 2006.169.07:53:58.21#ibcon#about to read 4, iclass 35, count 0 2006.169.07:53:58.21#ibcon#read 4, iclass 35, count 0 2006.169.07:53:58.21#ibcon#about to read 5, iclass 35, count 0 2006.169.07:53:58.21#ibcon#read 5, iclass 35, count 0 2006.169.07:53:58.21#ibcon#about to read 6, iclass 35, count 0 2006.169.07:53:58.21#ibcon#read 6, iclass 35, count 0 2006.169.07:53:58.21#ibcon#end of sib2, iclass 35, count 0 2006.169.07:53:58.21#ibcon#*after write, iclass 35, count 0 2006.169.07:53:58.21#ibcon#*before return 0, iclass 35, count 0 2006.169.07:53:58.21#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:53:58.21#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.169.07:53:58.21#ibcon#about to clear, iclass 35 cls_cnt 0 2006.169.07:53:58.21#ibcon#cleared, iclass 35 cls_cnt 0 2006.169.07:53:58.21$vc4f8/vblo=3,656.99 2006.169.07:53:58.21#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.169.07:53:58.21#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.169.07:53:58.21#ibcon#ireg 17 cls_cnt 0 2006.169.07:53:58.21#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:53:58.21#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:53:58.21#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:53:58.21#ibcon#enter wrdev, iclass 37, count 0 2006.169.07:53:58.21#ibcon#first serial, iclass 37, count 0 2006.169.07:53:58.21#ibcon#enter sib2, iclass 37, count 0 2006.169.07:53:58.21#ibcon#flushed, iclass 37, count 0 2006.169.07:53:58.21#ibcon#about to write, iclass 37, count 0 2006.169.07:53:58.21#ibcon#wrote, iclass 37, count 0 2006.169.07:53:58.21#ibcon#about to read 3, iclass 37, count 0 2006.169.07:53:58.23#ibcon#read 3, iclass 37, count 0 2006.169.07:53:58.23#ibcon#about to read 4, iclass 37, count 0 2006.169.07:53:58.23#ibcon#read 4, iclass 37, count 0 2006.169.07:53:58.23#ibcon#about to read 5, iclass 37, count 0 2006.169.07:53:58.23#ibcon#read 5, iclass 37, count 0 2006.169.07:53:58.23#ibcon#about to read 6, iclass 37, count 0 2006.169.07:53:58.23#ibcon#read 6, iclass 37, count 0 2006.169.07:53:58.23#ibcon#end of sib2, iclass 37, count 0 2006.169.07:53:58.23#ibcon#*mode == 0, iclass 37, count 0 2006.169.07:53:58.23#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.169.07:53:58.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.07:53:58.23#ibcon#*before write, iclass 37, count 0 2006.169.07:53:58.23#ibcon#enter sib2, iclass 37, count 0 2006.169.07:53:58.23#ibcon#flushed, iclass 37, count 0 2006.169.07:53:58.23#ibcon#about to write, iclass 37, count 0 2006.169.07:53:58.23#ibcon#wrote, iclass 37, count 0 2006.169.07:53:58.23#ibcon#about to read 3, iclass 37, count 0 2006.169.07:53:58.27#ibcon#read 3, iclass 37, count 0 2006.169.07:53:58.27#ibcon#about to read 4, iclass 37, count 0 2006.169.07:53:58.27#ibcon#read 4, iclass 37, count 0 2006.169.07:53:58.27#ibcon#about to read 5, iclass 37, count 0 2006.169.07:53:58.27#ibcon#read 5, iclass 37, count 0 2006.169.07:53:58.27#ibcon#about to read 6, iclass 37, count 0 2006.169.07:53:58.27#ibcon#read 6, iclass 37, count 0 2006.169.07:53:58.27#ibcon#end of sib2, iclass 37, count 0 2006.169.07:53:58.27#ibcon#*after write, iclass 37, count 0 2006.169.07:53:58.27#ibcon#*before return 0, iclass 37, count 0 2006.169.07:53:58.27#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:53:58.27#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.169.07:53:58.27#ibcon#about to clear, iclass 37 cls_cnt 0 2006.169.07:53:58.27#ibcon#cleared, iclass 37 cls_cnt 0 2006.169.07:53:58.27$vc4f8/vb=3,4 2006.169.07:53:58.27#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.169.07:53:58.27#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.169.07:53:58.27#ibcon#ireg 11 cls_cnt 2 2006.169.07:53:58.27#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:53:58.33#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:53:58.33#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:53:58.33#ibcon#enter wrdev, iclass 39, count 2 2006.169.07:53:58.33#ibcon#first serial, iclass 39, count 2 2006.169.07:53:58.33#ibcon#enter sib2, iclass 39, count 2 2006.169.07:53:58.33#ibcon#flushed, iclass 39, count 2 2006.169.07:53:58.33#ibcon#about to write, iclass 39, count 2 2006.169.07:53:58.33#ibcon#wrote, iclass 39, count 2 2006.169.07:53:58.33#ibcon#about to read 3, iclass 39, count 2 2006.169.07:53:58.35#ibcon#read 3, iclass 39, count 2 2006.169.07:53:58.35#ibcon#about to read 4, iclass 39, count 2 2006.169.07:53:58.35#ibcon#read 4, iclass 39, count 2 2006.169.07:53:58.35#ibcon#about to read 5, iclass 39, count 2 2006.169.07:53:58.35#ibcon#read 5, iclass 39, count 2 2006.169.07:53:58.35#ibcon#about to read 6, iclass 39, count 2 2006.169.07:53:58.35#ibcon#read 6, iclass 39, count 2 2006.169.07:53:58.35#ibcon#end of sib2, iclass 39, count 2 2006.169.07:53:58.35#ibcon#*mode == 0, iclass 39, count 2 2006.169.07:53:58.35#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.169.07:53:58.35#ibcon#[27=AT03-04\r\n] 2006.169.07:53:58.35#ibcon#*before write, iclass 39, count 2 2006.169.07:53:58.35#ibcon#enter sib2, iclass 39, count 2 2006.169.07:53:58.35#ibcon#flushed, iclass 39, count 2 2006.169.07:53:58.35#ibcon#about to write, iclass 39, count 2 2006.169.07:53:58.35#ibcon#wrote, iclass 39, count 2 2006.169.07:53:58.35#ibcon#about to read 3, iclass 39, count 2 2006.169.07:53:58.38#ibcon#read 3, iclass 39, count 2 2006.169.07:53:58.38#ibcon#about to read 4, iclass 39, count 2 2006.169.07:53:58.38#ibcon#read 4, iclass 39, count 2 2006.169.07:53:58.38#ibcon#about to read 5, iclass 39, count 2 2006.169.07:53:58.38#ibcon#read 5, iclass 39, count 2 2006.169.07:53:58.38#ibcon#about to read 6, iclass 39, count 2 2006.169.07:53:58.38#ibcon#read 6, iclass 39, count 2 2006.169.07:53:58.38#ibcon#end of sib2, iclass 39, count 2 2006.169.07:53:58.38#ibcon#*after write, iclass 39, count 2 2006.169.07:53:58.38#ibcon#*before return 0, iclass 39, count 2 2006.169.07:53:58.38#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:53:58.38#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.169.07:53:58.38#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.169.07:53:58.38#ibcon#ireg 7 cls_cnt 0 2006.169.07:53:58.38#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:53:58.48#abcon#<5=/04 3.3 5.9 18.121001003.9\r\n> 2006.169.07:53:58.50#abcon#{5=INTERFACE CLEAR} 2006.169.07:53:58.50#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:53:58.50#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:53:58.50#ibcon#enter wrdev, iclass 39, count 0 2006.169.07:53:58.50#ibcon#first serial, iclass 39, count 0 2006.169.07:53:58.50#ibcon#enter sib2, iclass 39, count 0 2006.169.07:53:58.50#ibcon#flushed, iclass 39, count 0 2006.169.07:53:58.50#ibcon#about to write, iclass 39, count 0 2006.169.07:53:58.50#ibcon#wrote, iclass 39, count 0 2006.169.07:53:58.50#ibcon#about to read 3, iclass 39, count 0 2006.169.07:53:58.52#ibcon#read 3, iclass 39, count 0 2006.169.07:53:58.52#ibcon#about to read 4, iclass 39, count 0 2006.169.07:53:58.52#ibcon#read 4, iclass 39, count 0 2006.169.07:53:58.52#ibcon#about to read 5, iclass 39, count 0 2006.169.07:53:58.52#ibcon#read 5, iclass 39, count 0 2006.169.07:53:58.52#ibcon#about to read 6, iclass 39, count 0 2006.169.07:53:58.52#ibcon#read 6, iclass 39, count 0 2006.169.07:53:58.52#ibcon#end of sib2, iclass 39, count 0 2006.169.07:53:58.52#ibcon#*mode == 0, iclass 39, count 0 2006.169.07:53:58.52#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.169.07:53:58.52#ibcon#[27=USB\r\n] 2006.169.07:53:58.52#ibcon#*before write, iclass 39, count 0 2006.169.07:53:58.52#ibcon#enter sib2, iclass 39, count 0 2006.169.07:53:58.52#ibcon#flushed, iclass 39, count 0 2006.169.07:53:58.52#ibcon#about to write, iclass 39, count 0 2006.169.07:53:58.52#ibcon#wrote, iclass 39, count 0 2006.169.07:53:58.52#ibcon#about to read 3, iclass 39, count 0 2006.169.07:53:58.55#ibcon#read 3, iclass 39, count 0 2006.169.07:53:58.55#ibcon#about to read 4, iclass 39, count 0 2006.169.07:53:58.55#ibcon#read 4, iclass 39, count 0 2006.169.07:53:58.55#ibcon#about to read 5, iclass 39, count 0 2006.169.07:53:58.55#ibcon#read 5, iclass 39, count 0 2006.169.07:53:58.55#ibcon#about to read 6, iclass 39, count 0 2006.169.07:53:58.55#ibcon#read 6, iclass 39, count 0 2006.169.07:53:58.55#ibcon#end of sib2, iclass 39, count 0 2006.169.07:53:58.55#ibcon#*after write, iclass 39, count 0 2006.169.07:53:58.55#ibcon#*before return 0, iclass 39, count 0 2006.169.07:53:58.55#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:53:58.55#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.169.07:53:58.55#ibcon#about to clear, iclass 39 cls_cnt 0 2006.169.07:53:58.55#ibcon#cleared, iclass 39 cls_cnt 0 2006.169.07:53:58.55$vc4f8/vblo=4,712.99 2006.169.07:53:58.55#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.169.07:53:58.55#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.169.07:53:58.55#ibcon#ireg 17 cls_cnt 0 2006.169.07:53:58.55#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:53:58.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:53:58.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:53:58.55#ibcon#enter wrdev, iclass 7, count 0 2006.169.07:53:58.55#ibcon#first serial, iclass 7, count 0 2006.169.07:53:58.55#ibcon#enter sib2, iclass 7, count 0 2006.169.07:53:58.55#ibcon#flushed, iclass 7, count 0 2006.169.07:53:58.55#ibcon#about to write, iclass 7, count 0 2006.169.07:53:58.55#ibcon#wrote, iclass 7, count 0 2006.169.07:53:58.55#ibcon#about to read 3, iclass 7, count 0 2006.169.07:53:58.56#abcon#[5=S1D000X0/0*\r\n] 2006.169.07:53:58.57#ibcon#read 3, iclass 7, count 0 2006.169.07:53:58.57#ibcon#about to read 4, iclass 7, count 0 2006.169.07:53:58.57#ibcon#read 4, iclass 7, count 0 2006.169.07:53:58.57#ibcon#about to read 5, iclass 7, count 0 2006.169.07:53:58.57#ibcon#read 5, iclass 7, count 0 2006.169.07:53:58.57#ibcon#about to read 6, iclass 7, count 0 2006.169.07:53:58.57#ibcon#read 6, iclass 7, count 0 2006.169.07:53:58.57#ibcon#end of sib2, iclass 7, count 0 2006.169.07:53:58.57#ibcon#*mode == 0, iclass 7, count 0 2006.169.07:53:58.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.169.07:53:58.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.07:53:58.57#ibcon#*before write, iclass 7, count 0 2006.169.07:53:58.57#ibcon#enter sib2, iclass 7, count 0 2006.169.07:53:58.57#ibcon#flushed, iclass 7, count 0 2006.169.07:53:58.57#ibcon#about to write, iclass 7, count 0 2006.169.07:53:58.57#ibcon#wrote, iclass 7, count 0 2006.169.07:53:58.57#ibcon#about to read 3, iclass 7, count 0 2006.169.07:53:58.61#ibcon#read 3, iclass 7, count 0 2006.169.07:53:58.61#ibcon#about to read 4, iclass 7, count 0 2006.169.07:53:58.61#ibcon#read 4, iclass 7, count 0 2006.169.07:53:58.61#ibcon#about to read 5, iclass 7, count 0 2006.169.07:53:58.61#ibcon#read 5, iclass 7, count 0 2006.169.07:53:58.61#ibcon#about to read 6, iclass 7, count 0 2006.169.07:53:58.61#ibcon#read 6, iclass 7, count 0 2006.169.07:53:58.61#ibcon#end of sib2, iclass 7, count 0 2006.169.07:53:58.61#ibcon#*after write, iclass 7, count 0 2006.169.07:53:58.61#ibcon#*before return 0, iclass 7, count 0 2006.169.07:53:58.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:53:58.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.169.07:53:58.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.169.07:53:58.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.169.07:53:58.61$vc4f8/vb=4,4 2006.169.07:53:58.61#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.169.07:53:58.61#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.169.07:53:58.61#ibcon#ireg 11 cls_cnt 2 2006.169.07:53:58.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:53:58.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:53:58.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:53:58.67#ibcon#enter wrdev, iclass 11, count 2 2006.169.07:53:58.67#ibcon#first serial, iclass 11, count 2 2006.169.07:53:58.67#ibcon#enter sib2, iclass 11, count 2 2006.169.07:53:58.67#ibcon#flushed, iclass 11, count 2 2006.169.07:53:58.67#ibcon#about to write, iclass 11, count 2 2006.169.07:53:58.67#ibcon#wrote, iclass 11, count 2 2006.169.07:53:58.67#ibcon#about to read 3, iclass 11, count 2 2006.169.07:53:58.69#ibcon#read 3, iclass 11, count 2 2006.169.07:53:58.69#ibcon#about to read 4, iclass 11, count 2 2006.169.07:53:58.69#ibcon#read 4, iclass 11, count 2 2006.169.07:53:58.69#ibcon#about to read 5, iclass 11, count 2 2006.169.07:53:58.69#ibcon#read 5, iclass 11, count 2 2006.169.07:53:58.69#ibcon#about to read 6, iclass 11, count 2 2006.169.07:53:58.69#ibcon#read 6, iclass 11, count 2 2006.169.07:53:58.69#ibcon#end of sib2, iclass 11, count 2 2006.169.07:53:58.69#ibcon#*mode == 0, iclass 11, count 2 2006.169.07:53:58.69#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.169.07:53:58.69#ibcon#[27=AT04-04\r\n] 2006.169.07:53:58.69#ibcon#*before write, iclass 11, count 2 2006.169.07:53:58.69#ibcon#enter sib2, iclass 11, count 2 2006.169.07:53:58.69#ibcon#flushed, iclass 11, count 2 2006.169.07:53:58.69#ibcon#about to write, iclass 11, count 2 2006.169.07:53:58.69#ibcon#wrote, iclass 11, count 2 2006.169.07:53:58.69#ibcon#about to read 3, iclass 11, count 2 2006.169.07:53:58.72#ibcon#read 3, iclass 11, count 2 2006.169.07:53:58.72#ibcon#about to read 4, iclass 11, count 2 2006.169.07:53:58.72#ibcon#read 4, iclass 11, count 2 2006.169.07:53:58.72#ibcon#about to read 5, iclass 11, count 2 2006.169.07:53:58.72#ibcon#read 5, iclass 11, count 2 2006.169.07:53:58.72#ibcon#about to read 6, iclass 11, count 2 2006.169.07:53:58.72#ibcon#read 6, iclass 11, count 2 2006.169.07:53:58.72#ibcon#end of sib2, iclass 11, count 2 2006.169.07:53:58.72#ibcon#*after write, iclass 11, count 2 2006.169.07:53:58.72#ibcon#*before return 0, iclass 11, count 2 2006.169.07:53:58.72#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:53:58.72#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.169.07:53:58.72#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.169.07:53:58.72#ibcon#ireg 7 cls_cnt 0 2006.169.07:53:58.72#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:53:58.84#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:53:58.84#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:53:58.84#ibcon#enter wrdev, iclass 11, count 0 2006.169.07:53:58.84#ibcon#first serial, iclass 11, count 0 2006.169.07:53:58.84#ibcon#enter sib2, iclass 11, count 0 2006.169.07:53:58.84#ibcon#flushed, iclass 11, count 0 2006.169.07:53:58.84#ibcon#about to write, iclass 11, count 0 2006.169.07:53:58.84#ibcon#wrote, iclass 11, count 0 2006.169.07:53:58.84#ibcon#about to read 3, iclass 11, count 0 2006.169.07:53:58.86#ibcon#read 3, iclass 11, count 0 2006.169.07:53:58.86#ibcon#about to read 4, iclass 11, count 0 2006.169.07:53:58.86#ibcon#read 4, iclass 11, count 0 2006.169.07:53:58.86#ibcon#about to read 5, iclass 11, count 0 2006.169.07:53:58.86#ibcon#read 5, iclass 11, count 0 2006.169.07:53:58.86#ibcon#about to read 6, iclass 11, count 0 2006.169.07:53:58.86#ibcon#read 6, iclass 11, count 0 2006.169.07:53:58.86#ibcon#end of sib2, iclass 11, count 0 2006.169.07:53:58.86#ibcon#*mode == 0, iclass 11, count 0 2006.169.07:53:58.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.169.07:53:58.86#ibcon#[27=USB\r\n] 2006.169.07:53:58.86#ibcon#*before write, iclass 11, count 0 2006.169.07:53:58.86#ibcon#enter sib2, iclass 11, count 0 2006.169.07:53:58.86#ibcon#flushed, iclass 11, count 0 2006.169.07:53:58.86#ibcon#about to write, iclass 11, count 0 2006.169.07:53:58.86#ibcon#wrote, iclass 11, count 0 2006.169.07:53:58.86#ibcon#about to read 3, iclass 11, count 0 2006.169.07:53:58.89#ibcon#read 3, iclass 11, count 0 2006.169.07:53:58.89#ibcon#about to read 4, iclass 11, count 0 2006.169.07:53:58.89#ibcon#read 4, iclass 11, count 0 2006.169.07:53:58.89#ibcon#about to read 5, iclass 11, count 0 2006.169.07:53:58.89#ibcon#read 5, iclass 11, count 0 2006.169.07:53:58.89#ibcon#about to read 6, iclass 11, count 0 2006.169.07:53:58.89#ibcon#read 6, iclass 11, count 0 2006.169.07:53:58.89#ibcon#end of sib2, iclass 11, count 0 2006.169.07:53:58.89#ibcon#*after write, iclass 11, count 0 2006.169.07:53:58.89#ibcon#*before return 0, iclass 11, count 0 2006.169.07:53:58.89#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:53:58.89#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.169.07:53:58.89#ibcon#about to clear, iclass 11 cls_cnt 0 2006.169.07:53:58.89#ibcon#cleared, iclass 11 cls_cnt 0 2006.169.07:53:58.89$vc4f8/vblo=5,744.99 2006.169.07:53:58.89#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.169.07:53:58.89#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.169.07:53:58.89#ibcon#ireg 17 cls_cnt 0 2006.169.07:53:58.89#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:53:58.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:53:58.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:53:58.89#ibcon#enter wrdev, iclass 13, count 0 2006.169.07:53:58.89#ibcon#first serial, iclass 13, count 0 2006.169.07:53:58.89#ibcon#enter sib2, iclass 13, count 0 2006.169.07:53:58.89#ibcon#flushed, iclass 13, count 0 2006.169.07:53:58.89#ibcon#about to write, iclass 13, count 0 2006.169.07:53:58.89#ibcon#wrote, iclass 13, count 0 2006.169.07:53:58.89#ibcon#about to read 3, iclass 13, count 0 2006.169.07:53:58.91#ibcon#read 3, iclass 13, count 0 2006.169.07:53:58.91#ibcon#about to read 4, iclass 13, count 0 2006.169.07:53:58.91#ibcon#read 4, iclass 13, count 0 2006.169.07:53:58.91#ibcon#about to read 5, iclass 13, count 0 2006.169.07:53:58.91#ibcon#read 5, iclass 13, count 0 2006.169.07:53:58.91#ibcon#about to read 6, iclass 13, count 0 2006.169.07:53:58.91#ibcon#read 6, iclass 13, count 0 2006.169.07:53:58.91#ibcon#end of sib2, iclass 13, count 0 2006.169.07:53:58.91#ibcon#*mode == 0, iclass 13, count 0 2006.169.07:53:58.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.07:53:58.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.07:53:58.91#ibcon#*before write, iclass 13, count 0 2006.169.07:53:58.91#ibcon#enter sib2, iclass 13, count 0 2006.169.07:53:58.91#ibcon#flushed, iclass 13, count 0 2006.169.07:53:58.91#ibcon#about to write, iclass 13, count 0 2006.169.07:53:58.91#ibcon#wrote, iclass 13, count 0 2006.169.07:53:58.91#ibcon#about to read 3, iclass 13, count 0 2006.169.07:53:58.95#ibcon#read 3, iclass 13, count 0 2006.169.07:53:58.95#ibcon#about to read 4, iclass 13, count 0 2006.169.07:53:58.95#ibcon#read 4, iclass 13, count 0 2006.169.07:53:58.95#ibcon#about to read 5, iclass 13, count 0 2006.169.07:53:58.95#ibcon#read 5, iclass 13, count 0 2006.169.07:53:58.95#ibcon#about to read 6, iclass 13, count 0 2006.169.07:53:58.95#ibcon#read 6, iclass 13, count 0 2006.169.07:53:58.95#ibcon#end of sib2, iclass 13, count 0 2006.169.07:53:58.95#ibcon#*after write, iclass 13, count 0 2006.169.07:53:58.95#ibcon#*before return 0, iclass 13, count 0 2006.169.07:53:58.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:53:58.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.169.07:53:58.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.07:53:58.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.07:53:58.95$vc4f8/vb=5,4 2006.169.07:53:58.95#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.169.07:53:58.95#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.169.07:53:58.95#ibcon#ireg 11 cls_cnt 2 2006.169.07:53:58.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:53:59.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:53:59.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:53:59.01#ibcon#enter wrdev, iclass 15, count 2 2006.169.07:53:59.01#ibcon#first serial, iclass 15, count 2 2006.169.07:53:59.01#ibcon#enter sib2, iclass 15, count 2 2006.169.07:53:59.01#ibcon#flushed, iclass 15, count 2 2006.169.07:53:59.01#ibcon#about to write, iclass 15, count 2 2006.169.07:53:59.01#ibcon#wrote, iclass 15, count 2 2006.169.07:53:59.01#ibcon#about to read 3, iclass 15, count 2 2006.169.07:53:59.03#ibcon#read 3, iclass 15, count 2 2006.169.07:53:59.03#ibcon#about to read 4, iclass 15, count 2 2006.169.07:53:59.03#ibcon#read 4, iclass 15, count 2 2006.169.07:53:59.03#ibcon#about to read 5, iclass 15, count 2 2006.169.07:53:59.03#ibcon#read 5, iclass 15, count 2 2006.169.07:53:59.03#ibcon#about to read 6, iclass 15, count 2 2006.169.07:53:59.03#ibcon#read 6, iclass 15, count 2 2006.169.07:53:59.03#ibcon#end of sib2, iclass 15, count 2 2006.169.07:53:59.03#ibcon#*mode == 0, iclass 15, count 2 2006.169.07:53:59.03#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.169.07:53:59.03#ibcon#[27=AT05-04\r\n] 2006.169.07:53:59.03#ibcon#*before write, iclass 15, count 2 2006.169.07:53:59.03#ibcon#enter sib2, iclass 15, count 2 2006.169.07:53:59.03#ibcon#flushed, iclass 15, count 2 2006.169.07:53:59.03#ibcon#about to write, iclass 15, count 2 2006.169.07:53:59.03#ibcon#wrote, iclass 15, count 2 2006.169.07:53:59.03#ibcon#about to read 3, iclass 15, count 2 2006.169.07:53:59.06#ibcon#read 3, iclass 15, count 2 2006.169.07:53:59.06#ibcon#about to read 4, iclass 15, count 2 2006.169.07:53:59.06#ibcon#read 4, iclass 15, count 2 2006.169.07:53:59.06#ibcon#about to read 5, iclass 15, count 2 2006.169.07:53:59.06#ibcon#read 5, iclass 15, count 2 2006.169.07:53:59.06#ibcon#about to read 6, iclass 15, count 2 2006.169.07:53:59.06#ibcon#read 6, iclass 15, count 2 2006.169.07:53:59.06#ibcon#end of sib2, iclass 15, count 2 2006.169.07:53:59.06#ibcon#*after write, iclass 15, count 2 2006.169.07:53:59.06#ibcon#*before return 0, iclass 15, count 2 2006.169.07:53:59.06#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:53:59.06#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.169.07:53:59.06#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.169.07:53:59.06#ibcon#ireg 7 cls_cnt 0 2006.169.07:53:59.06#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:53:59.18#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:53:59.18#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:53:59.18#ibcon#enter wrdev, iclass 15, count 0 2006.169.07:53:59.18#ibcon#first serial, iclass 15, count 0 2006.169.07:53:59.18#ibcon#enter sib2, iclass 15, count 0 2006.169.07:53:59.18#ibcon#flushed, iclass 15, count 0 2006.169.07:53:59.18#ibcon#about to write, iclass 15, count 0 2006.169.07:53:59.18#ibcon#wrote, iclass 15, count 0 2006.169.07:53:59.18#ibcon#about to read 3, iclass 15, count 0 2006.169.07:53:59.20#ibcon#read 3, iclass 15, count 0 2006.169.07:53:59.20#ibcon#about to read 4, iclass 15, count 0 2006.169.07:53:59.20#ibcon#read 4, iclass 15, count 0 2006.169.07:53:59.20#ibcon#about to read 5, iclass 15, count 0 2006.169.07:53:59.20#ibcon#read 5, iclass 15, count 0 2006.169.07:53:59.20#ibcon#about to read 6, iclass 15, count 0 2006.169.07:53:59.20#ibcon#read 6, iclass 15, count 0 2006.169.07:53:59.20#ibcon#end of sib2, iclass 15, count 0 2006.169.07:53:59.20#ibcon#*mode == 0, iclass 15, count 0 2006.169.07:53:59.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.169.07:53:59.20#ibcon#[27=USB\r\n] 2006.169.07:53:59.20#ibcon#*before write, iclass 15, count 0 2006.169.07:53:59.20#ibcon#enter sib2, iclass 15, count 0 2006.169.07:53:59.20#ibcon#flushed, iclass 15, count 0 2006.169.07:53:59.20#ibcon#about to write, iclass 15, count 0 2006.169.07:53:59.20#ibcon#wrote, iclass 15, count 0 2006.169.07:53:59.20#ibcon#about to read 3, iclass 15, count 0 2006.169.07:53:59.23#ibcon#read 3, iclass 15, count 0 2006.169.07:53:59.23#ibcon#about to read 4, iclass 15, count 0 2006.169.07:53:59.23#ibcon#read 4, iclass 15, count 0 2006.169.07:53:59.23#ibcon#about to read 5, iclass 15, count 0 2006.169.07:53:59.23#ibcon#read 5, iclass 15, count 0 2006.169.07:53:59.23#ibcon#about to read 6, iclass 15, count 0 2006.169.07:53:59.23#ibcon#read 6, iclass 15, count 0 2006.169.07:53:59.23#ibcon#end of sib2, iclass 15, count 0 2006.169.07:53:59.23#ibcon#*after write, iclass 15, count 0 2006.169.07:53:59.23#ibcon#*before return 0, iclass 15, count 0 2006.169.07:53:59.23#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:53:59.23#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.169.07:53:59.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.169.07:53:59.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.169.07:53:59.23$vc4f8/vblo=6,752.99 2006.169.07:53:59.23#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.169.07:53:59.23#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.169.07:53:59.23#ibcon#ireg 17 cls_cnt 0 2006.169.07:53:59.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:53:59.23#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:53:59.23#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:53:59.23#ibcon#enter wrdev, iclass 17, count 0 2006.169.07:53:59.23#ibcon#first serial, iclass 17, count 0 2006.169.07:53:59.23#ibcon#enter sib2, iclass 17, count 0 2006.169.07:53:59.23#ibcon#flushed, iclass 17, count 0 2006.169.07:53:59.23#ibcon#about to write, iclass 17, count 0 2006.169.07:53:59.23#ibcon#wrote, iclass 17, count 0 2006.169.07:53:59.23#ibcon#about to read 3, iclass 17, count 0 2006.169.07:53:59.25#ibcon#read 3, iclass 17, count 0 2006.169.07:53:59.25#ibcon#about to read 4, iclass 17, count 0 2006.169.07:53:59.25#ibcon#read 4, iclass 17, count 0 2006.169.07:53:59.25#ibcon#about to read 5, iclass 17, count 0 2006.169.07:53:59.25#ibcon#read 5, iclass 17, count 0 2006.169.07:53:59.25#ibcon#about to read 6, iclass 17, count 0 2006.169.07:53:59.25#ibcon#read 6, iclass 17, count 0 2006.169.07:53:59.25#ibcon#end of sib2, iclass 17, count 0 2006.169.07:53:59.25#ibcon#*mode == 0, iclass 17, count 0 2006.169.07:53:59.25#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.169.07:53:59.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.07:53:59.25#ibcon#*before write, iclass 17, count 0 2006.169.07:53:59.25#ibcon#enter sib2, iclass 17, count 0 2006.169.07:53:59.25#ibcon#flushed, iclass 17, count 0 2006.169.07:53:59.25#ibcon#about to write, iclass 17, count 0 2006.169.07:53:59.25#ibcon#wrote, iclass 17, count 0 2006.169.07:53:59.25#ibcon#about to read 3, iclass 17, count 0 2006.169.07:53:59.29#ibcon#read 3, iclass 17, count 0 2006.169.07:53:59.29#ibcon#about to read 4, iclass 17, count 0 2006.169.07:53:59.29#ibcon#read 4, iclass 17, count 0 2006.169.07:53:59.29#ibcon#about to read 5, iclass 17, count 0 2006.169.07:53:59.29#ibcon#read 5, iclass 17, count 0 2006.169.07:53:59.29#ibcon#about to read 6, iclass 17, count 0 2006.169.07:53:59.29#ibcon#read 6, iclass 17, count 0 2006.169.07:53:59.29#ibcon#end of sib2, iclass 17, count 0 2006.169.07:53:59.29#ibcon#*after write, iclass 17, count 0 2006.169.07:53:59.29#ibcon#*before return 0, iclass 17, count 0 2006.169.07:53:59.29#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:53:59.29#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.169.07:53:59.29#ibcon#about to clear, iclass 17 cls_cnt 0 2006.169.07:53:59.29#ibcon#cleared, iclass 17 cls_cnt 0 2006.169.07:53:59.29$vc4f8/vb=6,4 2006.169.07:53:59.29#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.169.07:53:59.29#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.169.07:53:59.29#ibcon#ireg 11 cls_cnt 2 2006.169.07:53:59.29#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:53:59.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:53:59.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:53:59.35#ibcon#enter wrdev, iclass 19, count 2 2006.169.07:53:59.35#ibcon#first serial, iclass 19, count 2 2006.169.07:53:59.35#ibcon#enter sib2, iclass 19, count 2 2006.169.07:53:59.35#ibcon#flushed, iclass 19, count 2 2006.169.07:53:59.35#ibcon#about to write, iclass 19, count 2 2006.169.07:53:59.35#ibcon#wrote, iclass 19, count 2 2006.169.07:53:59.35#ibcon#about to read 3, iclass 19, count 2 2006.169.07:53:59.37#ibcon#read 3, iclass 19, count 2 2006.169.07:53:59.37#ibcon#about to read 4, iclass 19, count 2 2006.169.07:53:59.37#ibcon#read 4, iclass 19, count 2 2006.169.07:53:59.37#ibcon#about to read 5, iclass 19, count 2 2006.169.07:53:59.37#ibcon#read 5, iclass 19, count 2 2006.169.07:53:59.37#ibcon#about to read 6, iclass 19, count 2 2006.169.07:53:59.37#ibcon#read 6, iclass 19, count 2 2006.169.07:53:59.37#ibcon#end of sib2, iclass 19, count 2 2006.169.07:53:59.37#ibcon#*mode == 0, iclass 19, count 2 2006.169.07:53:59.37#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.169.07:53:59.37#ibcon#[27=AT06-04\r\n] 2006.169.07:53:59.37#ibcon#*before write, iclass 19, count 2 2006.169.07:53:59.37#ibcon#enter sib2, iclass 19, count 2 2006.169.07:53:59.37#ibcon#flushed, iclass 19, count 2 2006.169.07:53:59.37#ibcon#about to write, iclass 19, count 2 2006.169.07:53:59.37#ibcon#wrote, iclass 19, count 2 2006.169.07:53:59.37#ibcon#about to read 3, iclass 19, count 2 2006.169.07:53:59.40#ibcon#read 3, iclass 19, count 2 2006.169.07:53:59.40#ibcon#about to read 4, iclass 19, count 2 2006.169.07:53:59.40#ibcon#read 4, iclass 19, count 2 2006.169.07:53:59.40#ibcon#about to read 5, iclass 19, count 2 2006.169.07:53:59.40#ibcon#read 5, iclass 19, count 2 2006.169.07:53:59.40#ibcon#about to read 6, iclass 19, count 2 2006.169.07:53:59.40#ibcon#read 6, iclass 19, count 2 2006.169.07:53:59.40#ibcon#end of sib2, iclass 19, count 2 2006.169.07:53:59.40#ibcon#*after write, iclass 19, count 2 2006.169.07:53:59.40#ibcon#*before return 0, iclass 19, count 2 2006.169.07:53:59.40#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:53:59.40#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.169.07:53:59.40#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.169.07:53:59.40#ibcon#ireg 7 cls_cnt 0 2006.169.07:53:59.40#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:53:59.52#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:53:59.52#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:53:59.52#ibcon#enter wrdev, iclass 19, count 0 2006.169.07:53:59.52#ibcon#first serial, iclass 19, count 0 2006.169.07:53:59.52#ibcon#enter sib2, iclass 19, count 0 2006.169.07:53:59.52#ibcon#flushed, iclass 19, count 0 2006.169.07:53:59.52#ibcon#about to write, iclass 19, count 0 2006.169.07:53:59.52#ibcon#wrote, iclass 19, count 0 2006.169.07:53:59.52#ibcon#about to read 3, iclass 19, count 0 2006.169.07:53:59.54#ibcon#read 3, iclass 19, count 0 2006.169.07:53:59.54#ibcon#about to read 4, iclass 19, count 0 2006.169.07:53:59.54#ibcon#read 4, iclass 19, count 0 2006.169.07:53:59.54#ibcon#about to read 5, iclass 19, count 0 2006.169.07:53:59.54#ibcon#read 5, iclass 19, count 0 2006.169.07:53:59.54#ibcon#about to read 6, iclass 19, count 0 2006.169.07:53:59.54#ibcon#read 6, iclass 19, count 0 2006.169.07:53:59.54#ibcon#end of sib2, iclass 19, count 0 2006.169.07:53:59.54#ibcon#*mode == 0, iclass 19, count 0 2006.169.07:53:59.54#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.169.07:53:59.54#ibcon#[27=USB\r\n] 2006.169.07:53:59.54#ibcon#*before write, iclass 19, count 0 2006.169.07:53:59.54#ibcon#enter sib2, iclass 19, count 0 2006.169.07:53:59.54#ibcon#flushed, iclass 19, count 0 2006.169.07:53:59.54#ibcon#about to write, iclass 19, count 0 2006.169.07:53:59.54#ibcon#wrote, iclass 19, count 0 2006.169.07:53:59.54#ibcon#about to read 3, iclass 19, count 0 2006.169.07:53:59.57#ibcon#read 3, iclass 19, count 0 2006.169.07:53:59.57#ibcon#about to read 4, iclass 19, count 0 2006.169.07:53:59.57#ibcon#read 4, iclass 19, count 0 2006.169.07:53:59.57#ibcon#about to read 5, iclass 19, count 0 2006.169.07:53:59.57#ibcon#read 5, iclass 19, count 0 2006.169.07:53:59.57#ibcon#about to read 6, iclass 19, count 0 2006.169.07:53:59.57#ibcon#read 6, iclass 19, count 0 2006.169.07:53:59.57#ibcon#end of sib2, iclass 19, count 0 2006.169.07:53:59.57#ibcon#*after write, iclass 19, count 0 2006.169.07:53:59.57#ibcon#*before return 0, iclass 19, count 0 2006.169.07:53:59.57#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:53:59.57#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.169.07:53:59.57#ibcon#about to clear, iclass 19 cls_cnt 0 2006.169.07:53:59.57#ibcon#cleared, iclass 19 cls_cnt 0 2006.169.07:53:59.57$vc4f8/vabw=wide 2006.169.07:53:59.57#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.169.07:53:59.57#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.169.07:53:59.57#ibcon#ireg 8 cls_cnt 0 2006.169.07:53:59.57#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:53:59.57#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:53:59.57#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:53:59.57#ibcon#enter wrdev, iclass 21, count 0 2006.169.07:53:59.57#ibcon#first serial, iclass 21, count 0 2006.169.07:53:59.57#ibcon#enter sib2, iclass 21, count 0 2006.169.07:53:59.57#ibcon#flushed, iclass 21, count 0 2006.169.07:53:59.57#ibcon#about to write, iclass 21, count 0 2006.169.07:53:59.57#ibcon#wrote, iclass 21, count 0 2006.169.07:53:59.57#ibcon#about to read 3, iclass 21, count 0 2006.169.07:53:59.59#ibcon#read 3, iclass 21, count 0 2006.169.07:53:59.59#ibcon#about to read 4, iclass 21, count 0 2006.169.07:53:59.59#ibcon#read 4, iclass 21, count 0 2006.169.07:53:59.59#ibcon#about to read 5, iclass 21, count 0 2006.169.07:53:59.59#ibcon#read 5, iclass 21, count 0 2006.169.07:53:59.59#ibcon#about to read 6, iclass 21, count 0 2006.169.07:53:59.59#ibcon#read 6, iclass 21, count 0 2006.169.07:53:59.59#ibcon#end of sib2, iclass 21, count 0 2006.169.07:53:59.59#ibcon#*mode == 0, iclass 21, count 0 2006.169.07:53:59.59#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.169.07:53:59.59#ibcon#[25=BW32\r\n] 2006.169.07:53:59.59#ibcon#*before write, iclass 21, count 0 2006.169.07:53:59.59#ibcon#enter sib2, iclass 21, count 0 2006.169.07:53:59.59#ibcon#flushed, iclass 21, count 0 2006.169.07:53:59.59#ibcon#about to write, iclass 21, count 0 2006.169.07:53:59.59#ibcon#wrote, iclass 21, count 0 2006.169.07:53:59.59#ibcon#about to read 3, iclass 21, count 0 2006.169.07:53:59.62#ibcon#read 3, iclass 21, count 0 2006.169.07:53:59.62#ibcon#about to read 4, iclass 21, count 0 2006.169.07:53:59.62#ibcon#read 4, iclass 21, count 0 2006.169.07:53:59.62#ibcon#about to read 5, iclass 21, count 0 2006.169.07:53:59.62#ibcon#read 5, iclass 21, count 0 2006.169.07:53:59.62#ibcon#about to read 6, iclass 21, count 0 2006.169.07:53:59.62#ibcon#read 6, iclass 21, count 0 2006.169.07:53:59.62#ibcon#end of sib2, iclass 21, count 0 2006.169.07:53:59.62#ibcon#*after write, iclass 21, count 0 2006.169.07:53:59.62#ibcon#*before return 0, iclass 21, count 0 2006.169.07:53:59.62#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:53:59.62#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.169.07:53:59.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.169.07:53:59.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.169.07:53:59.62$vc4f8/vbbw=wide 2006.169.07:53:59.62#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.169.07:53:59.62#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.169.07:53:59.62#ibcon#ireg 8 cls_cnt 0 2006.169.07:53:59.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.169.07:53:59.69#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.169.07:53:59.69#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.169.07:53:59.69#ibcon#enter wrdev, iclass 23, count 0 2006.169.07:53:59.69#ibcon#first serial, iclass 23, count 0 2006.169.07:53:59.69#ibcon#enter sib2, iclass 23, count 0 2006.169.07:53:59.69#ibcon#flushed, iclass 23, count 0 2006.169.07:53:59.69#ibcon#about to write, iclass 23, count 0 2006.169.07:53:59.69#ibcon#wrote, iclass 23, count 0 2006.169.07:53:59.69#ibcon#about to read 3, iclass 23, count 0 2006.169.07:53:59.71#ibcon#read 3, iclass 23, count 0 2006.169.07:53:59.71#ibcon#about to read 4, iclass 23, count 0 2006.169.07:53:59.71#ibcon#read 4, iclass 23, count 0 2006.169.07:53:59.71#ibcon#about to read 5, iclass 23, count 0 2006.169.07:53:59.71#ibcon#read 5, iclass 23, count 0 2006.169.07:53:59.71#ibcon#about to read 6, iclass 23, count 0 2006.169.07:53:59.71#ibcon#read 6, iclass 23, count 0 2006.169.07:53:59.71#ibcon#end of sib2, iclass 23, count 0 2006.169.07:53:59.71#ibcon#*mode == 0, iclass 23, count 0 2006.169.07:53:59.71#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.169.07:53:59.71#ibcon#[27=BW32\r\n] 2006.169.07:53:59.71#ibcon#*before write, iclass 23, count 0 2006.169.07:53:59.71#ibcon#enter sib2, iclass 23, count 0 2006.169.07:53:59.71#ibcon#flushed, iclass 23, count 0 2006.169.07:53:59.71#ibcon#about to write, iclass 23, count 0 2006.169.07:53:59.71#ibcon#wrote, iclass 23, count 0 2006.169.07:53:59.71#ibcon#about to read 3, iclass 23, count 0 2006.169.07:53:59.74#ibcon#read 3, iclass 23, count 0 2006.169.07:53:59.74#ibcon#about to read 4, iclass 23, count 0 2006.169.07:53:59.74#ibcon#read 4, iclass 23, count 0 2006.169.07:53:59.74#ibcon#about to read 5, iclass 23, count 0 2006.169.07:53:59.74#ibcon#read 5, iclass 23, count 0 2006.169.07:53:59.74#ibcon#about to read 6, iclass 23, count 0 2006.169.07:53:59.74#ibcon#read 6, iclass 23, count 0 2006.169.07:53:59.74#ibcon#end of sib2, iclass 23, count 0 2006.169.07:53:59.74#ibcon#*after write, iclass 23, count 0 2006.169.07:53:59.74#ibcon#*before return 0, iclass 23, count 0 2006.169.07:53:59.74#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.169.07:53:59.74#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.169.07:53:59.74#ibcon#about to clear, iclass 23 cls_cnt 0 2006.169.07:53:59.74#ibcon#cleared, iclass 23 cls_cnt 0 2006.169.07:53:59.74$4f8m12a/ifd4f 2006.169.07:53:59.74$ifd4f/lo= 2006.169.07:53:59.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.07:53:59.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.07:53:59.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.07:53:59.74$ifd4f/patch= 2006.169.07:53:59.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.07:53:59.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.07:53:59.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.07:53:59.74$4f8m12a/"form=m,16.000,1:2 2006.169.07:53:59.74$4f8m12a/"tpicd 2006.169.07:53:59.74$4f8m12a/echo=off 2006.169.07:53:59.74$4f8m12a/xlog=off 2006.169.07:53:59.74:!2006.169.07:55:10 2006.169.07:55:10.00:preob 2006.169.07:55:11.13/onsource/TRACKING 2006.169.07:55:11.13:!2006.169.07:55:20 2006.169.07:55:20.00:data_valid=on 2006.169.07:55:20.00:midob 2006.169.07:55:20.13/onsource/TRACKING 2006.169.07:55:20.13/wx/18.12,1003.9,100 2006.169.07:55:20.24/cable/+6.5277E-03 2006.169.07:55:21.33/va/01,08,usb,yes,46,48 2006.169.07:55:21.33/va/02,07,usb,yes,47,49 2006.169.07:55:21.33/va/03,06,usb,yes,49,50 2006.169.07:55:21.33/va/04,07,usb,yes,48,51 2006.169.07:55:21.33/va/05,07,usb,yes,52,55 2006.169.07:55:21.33/va/06,06,usb,yes,52,51 2006.169.07:55:21.33/va/07,06,usb,yes,52,52 2006.169.07:55:21.33/va/08,07,usb,yes,50,49 2006.169.07:55:21.56/valo/01,532.99,yes,locked 2006.169.07:55:21.56/valo/02,572.99,yes,locked 2006.169.07:55:21.56/valo/03,672.99,yes,locked 2006.169.07:55:21.56/valo/04,832.99,yes,locked 2006.169.07:55:21.56/valo/05,652.99,yes,locked 2006.169.07:55:21.56/valo/06,772.99,yes,locked 2006.169.07:55:21.56/valo/07,832.99,yes,locked 2006.169.07:55:21.56/valo/08,852.99,yes,locked 2006.169.07:55:22.65/vb/01,04,usb,yes,30,29 2006.169.07:55:22.65/vb/02,04,usb,yes,32,34 2006.169.07:55:22.65/vb/03,04,usb,yes,28,32 2006.169.07:55:22.65/vb/04,04,usb,yes,29,29 2006.169.07:55:22.65/vb/05,04,usb,yes,28,32 2006.169.07:55:22.65/vb/06,04,usb,yes,29,32 2006.169.07:55:22.65/vb/07,04,usb,yes,31,31 2006.169.07:55:22.65/vb/08,04,usb,yes,28,32 2006.169.07:55:22.88/vblo/01,632.99,yes,locked 2006.169.07:55:22.88/vblo/02,640.99,yes,locked 2006.169.07:55:22.88/vblo/03,656.99,yes,locked 2006.169.07:55:22.88/vblo/04,712.99,yes,locked 2006.169.07:55:22.88/vblo/05,744.99,yes,locked 2006.169.07:55:22.88/vblo/06,752.99,yes,locked 2006.169.07:55:22.88/vblo/07,734.99,yes,locked 2006.169.07:55:22.88/vblo/08,744.99,yes,locked 2006.169.07:55:23.03/vabw/8 2006.169.07:55:23.18/vbbw/8 2006.169.07:55:23.27/xfe/off,on,15.5 2006.169.07:55:23.65/ifatt/23,28,28,28 2006.169.07:55:24.07/fmout-gps/S +4.17E-07 2006.169.07:55:24.15:!2006.169.07:56:20 2006.169.07:56:20.00:data_valid=off 2006.169.07:56:20.00:postob 2006.169.07:56:20.13/cable/+6.5302E-03 2006.169.07:56:20.13/wx/18.12,1003.9,100 2006.169.07:56:21.08/fmout-gps/S +4.17E-07 2006.169.07:56:21.08:scan_name=169-0758,k06169,60 2006.169.07:56:21.09:source=0748+126,075052.05,123104.8,2000.0,ccw 2006.169.07:56:21.14#flagr#flagr/antenna,new-source 2006.169.07:56:22.14:checkk5 2006.169.07:56:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.169.07:56:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.169.07:56:26.91/chk_autoobs//k5ts3?ERROR: timeout happened! 2006.169.07:56:27.28/chk_autoobs//k5ts4/ autoobs is running! 2006.169.07:56:27.66/chk_obsdata//k5ts1/T1690755??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:56:28.03/chk_obsdata//k5ts2/T1690755??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:56:35.09/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.07:56:35.47/chk_obsdata//k5ts4/T1690755??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:56:36.16/k5log//k5ts1_log_newline 2006.169.07:56:36.85/k5log//k5ts2_log_newline 2006.169.07:56:43.95/k5log//k5ts3?ERROR: timeout happened! 2006.169.07:56:44.65/k5log//k5ts4_log_newline 2006.169.07:56:44.81/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.07:56:44.81:4f8m12a=2 2006.169.07:56:44.81$4f8m12a/echo=on 2006.169.07:56:44.81$4f8m12a/pcalon 2006.169.07:56:44.81$pcalon/"no phase cal control is implemented here 2006.169.07:56:44.81$4f8m12a/"tpicd=stop 2006.169.07:56:44.81$4f8m12a/vc4f8 2006.169.07:56:44.81$vc4f8/valo=1,532.99 2006.169.07:56:44.81#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.169.07:56:44.81#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.169.07:56:44.81#ibcon#ireg 17 cls_cnt 0 2006.169.07:56:44.81#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:56:44.81#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:56:44.81#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:56:44.81#ibcon#enter wrdev, iclass 18, count 0 2006.169.07:56:44.81#ibcon#first serial, iclass 18, count 0 2006.169.07:56:44.81#ibcon#enter sib2, iclass 18, count 0 2006.169.07:56:44.81#ibcon#flushed, iclass 18, count 0 2006.169.07:56:44.81#ibcon#about to write, iclass 18, count 0 2006.169.07:56:44.81#ibcon#wrote, iclass 18, count 0 2006.169.07:56:44.81#ibcon#about to read 3, iclass 18, count 0 2006.169.07:56:44.83#ibcon#read 3, iclass 18, count 0 2006.169.07:56:44.83#ibcon#about to read 4, iclass 18, count 0 2006.169.07:56:44.83#ibcon#read 4, iclass 18, count 0 2006.169.07:56:44.83#ibcon#about to read 5, iclass 18, count 0 2006.169.07:56:44.83#ibcon#read 5, iclass 18, count 0 2006.169.07:56:44.83#ibcon#about to read 6, iclass 18, count 0 2006.169.07:56:44.83#ibcon#read 6, iclass 18, count 0 2006.169.07:56:44.83#ibcon#end of sib2, iclass 18, count 0 2006.169.07:56:44.83#ibcon#*mode == 0, iclass 18, count 0 2006.169.07:56:44.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.169.07:56:44.83#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.07:56:44.83#ibcon#*before write, iclass 18, count 0 2006.169.07:56:44.83#ibcon#enter sib2, iclass 18, count 0 2006.169.07:56:44.83#ibcon#flushed, iclass 18, count 0 2006.169.07:56:44.83#ibcon#about to write, iclass 18, count 0 2006.169.07:56:44.83#ibcon#wrote, iclass 18, count 0 2006.169.07:56:44.83#ibcon#about to read 3, iclass 18, count 0 2006.169.07:56:44.89#ibcon#read 3, iclass 18, count 0 2006.169.07:56:44.89#ibcon#about to read 4, iclass 18, count 0 2006.169.07:56:44.89#ibcon#read 4, iclass 18, count 0 2006.169.07:56:44.89#ibcon#about to read 5, iclass 18, count 0 2006.169.07:56:44.89#ibcon#read 5, iclass 18, count 0 2006.169.07:56:44.89#ibcon#about to read 6, iclass 18, count 0 2006.169.07:56:44.89#ibcon#read 6, iclass 18, count 0 2006.169.07:56:44.89#ibcon#end of sib2, iclass 18, count 0 2006.169.07:56:44.89#ibcon#*after write, iclass 18, count 0 2006.169.07:56:44.89#ibcon#*before return 0, iclass 18, count 0 2006.169.07:56:44.89#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:56:44.89#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:56:44.89#ibcon#about to clear, iclass 18 cls_cnt 0 2006.169.07:56:44.89#ibcon#cleared, iclass 18 cls_cnt 0 2006.169.07:56:44.89$vc4f8/va=1,8 2006.169.07:56:44.89#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.169.07:56:44.89#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.169.07:56:44.89#ibcon#ireg 11 cls_cnt 2 2006.169.07:56:44.89#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.169.07:56:44.89#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.169.07:56:44.89#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.169.07:56:44.89#ibcon#enter wrdev, iclass 20, count 2 2006.169.07:56:44.89#ibcon#first serial, iclass 20, count 2 2006.169.07:56:44.89#ibcon#enter sib2, iclass 20, count 2 2006.169.07:56:44.89#ibcon#flushed, iclass 20, count 2 2006.169.07:56:44.89#ibcon#about to write, iclass 20, count 2 2006.169.07:56:44.89#ibcon#wrote, iclass 20, count 2 2006.169.07:56:44.89#ibcon#about to read 3, iclass 20, count 2 2006.169.07:56:44.90#ibcon#read 3, iclass 20, count 2 2006.169.07:56:44.90#ibcon#about to read 4, iclass 20, count 2 2006.169.07:56:44.90#ibcon#read 4, iclass 20, count 2 2006.169.07:56:44.90#ibcon#about to read 5, iclass 20, count 2 2006.169.07:56:44.90#ibcon#read 5, iclass 20, count 2 2006.169.07:56:44.90#ibcon#about to read 6, iclass 20, count 2 2006.169.07:56:44.90#ibcon#read 6, iclass 20, count 2 2006.169.07:56:44.90#ibcon#end of sib2, iclass 20, count 2 2006.169.07:56:44.90#ibcon#*mode == 0, iclass 20, count 2 2006.169.07:56:44.90#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.169.07:56:44.90#ibcon#[25=AT01-08\r\n] 2006.169.07:56:44.90#ibcon#*before write, iclass 20, count 2 2006.169.07:56:44.90#ibcon#enter sib2, iclass 20, count 2 2006.169.07:56:44.90#ibcon#flushed, iclass 20, count 2 2006.169.07:56:44.90#ibcon#about to write, iclass 20, count 2 2006.169.07:56:44.90#ibcon#wrote, iclass 20, count 2 2006.169.07:56:44.90#ibcon#about to read 3, iclass 20, count 2 2006.169.07:56:44.93#ibcon#read 3, iclass 20, count 2 2006.169.07:56:44.93#ibcon#about to read 4, iclass 20, count 2 2006.169.07:56:44.93#ibcon#read 4, iclass 20, count 2 2006.169.07:56:44.93#ibcon#about to read 5, iclass 20, count 2 2006.169.07:56:44.93#ibcon#read 5, iclass 20, count 2 2006.169.07:56:44.93#ibcon#about to read 6, iclass 20, count 2 2006.169.07:56:44.93#ibcon#read 6, iclass 20, count 2 2006.169.07:56:44.93#ibcon#end of sib2, iclass 20, count 2 2006.169.07:56:44.93#ibcon#*after write, iclass 20, count 2 2006.169.07:56:44.93#ibcon#*before return 0, iclass 20, count 2 2006.169.07:56:44.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.169.07:56:44.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.169.07:56:44.93#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.169.07:56:44.93#ibcon#ireg 7 cls_cnt 0 2006.169.07:56:44.93#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.169.07:56:45.05#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.169.07:56:45.05#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.169.07:56:45.05#ibcon#enter wrdev, iclass 20, count 0 2006.169.07:56:45.05#ibcon#first serial, iclass 20, count 0 2006.169.07:56:45.05#ibcon#enter sib2, iclass 20, count 0 2006.169.07:56:45.05#ibcon#flushed, iclass 20, count 0 2006.169.07:56:45.05#ibcon#about to write, iclass 20, count 0 2006.169.07:56:45.05#ibcon#wrote, iclass 20, count 0 2006.169.07:56:45.05#ibcon#about to read 3, iclass 20, count 0 2006.169.07:56:45.09#ibcon#read 3, iclass 20, count 0 2006.169.07:56:45.09#ibcon#about to read 4, iclass 20, count 0 2006.169.07:56:45.09#ibcon#read 4, iclass 20, count 0 2006.169.07:56:45.09#ibcon#about to read 5, iclass 20, count 0 2006.169.07:56:45.09#ibcon#read 5, iclass 20, count 0 2006.169.07:56:45.09#ibcon#about to read 6, iclass 20, count 0 2006.169.07:56:45.09#ibcon#read 6, iclass 20, count 0 2006.169.07:56:45.09#ibcon#end of sib2, iclass 20, count 0 2006.169.07:56:45.09#ibcon#*mode == 0, iclass 20, count 0 2006.169.07:56:45.09#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.169.07:56:45.09#ibcon#[25=USB\r\n] 2006.169.07:56:45.09#ibcon#*before write, iclass 20, count 0 2006.169.07:56:45.09#ibcon#enter sib2, iclass 20, count 0 2006.169.07:56:45.09#ibcon#flushed, iclass 20, count 0 2006.169.07:56:45.09#ibcon#about to write, iclass 20, count 0 2006.169.07:56:45.09#ibcon#wrote, iclass 20, count 0 2006.169.07:56:45.09#ibcon#about to read 3, iclass 20, count 0 2006.169.07:56:45.12#ibcon#read 3, iclass 20, count 0 2006.169.07:56:45.12#ibcon#about to read 4, iclass 20, count 0 2006.169.07:56:45.12#ibcon#read 4, iclass 20, count 0 2006.169.07:56:45.12#ibcon#about to read 5, iclass 20, count 0 2006.169.07:56:45.12#ibcon#read 5, iclass 20, count 0 2006.169.07:56:45.12#ibcon#about to read 6, iclass 20, count 0 2006.169.07:56:45.12#ibcon#read 6, iclass 20, count 0 2006.169.07:56:45.12#ibcon#end of sib2, iclass 20, count 0 2006.169.07:56:45.12#ibcon#*after write, iclass 20, count 0 2006.169.07:56:45.12#ibcon#*before return 0, iclass 20, count 0 2006.169.07:56:45.12#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.169.07:56:45.12#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.169.07:56:45.12#ibcon#about to clear, iclass 20 cls_cnt 0 2006.169.07:56:45.12#ibcon#cleared, iclass 20 cls_cnt 0 2006.169.07:56:45.12$vc4f8/valo=2,572.99 2006.169.07:56:45.12#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.169.07:56:45.12#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.169.07:56:45.12#ibcon#ireg 17 cls_cnt 0 2006.169.07:56:45.12#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:56:45.12#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:56:45.12#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:56:45.12#ibcon#enter wrdev, iclass 22, count 0 2006.169.07:56:45.12#ibcon#first serial, iclass 22, count 0 2006.169.07:56:45.12#ibcon#enter sib2, iclass 22, count 0 2006.169.07:56:45.12#ibcon#flushed, iclass 22, count 0 2006.169.07:56:45.12#ibcon#about to write, iclass 22, count 0 2006.169.07:56:45.12#ibcon#wrote, iclass 22, count 0 2006.169.07:56:45.12#ibcon#about to read 3, iclass 22, count 0 2006.169.07:56:45.14#ibcon#read 3, iclass 22, count 0 2006.169.07:56:45.14#ibcon#about to read 4, iclass 22, count 0 2006.169.07:56:45.14#ibcon#read 4, iclass 22, count 0 2006.169.07:56:45.14#ibcon#about to read 5, iclass 22, count 0 2006.169.07:56:45.14#ibcon#read 5, iclass 22, count 0 2006.169.07:56:45.14#ibcon#about to read 6, iclass 22, count 0 2006.169.07:56:45.14#ibcon#read 6, iclass 22, count 0 2006.169.07:56:45.14#ibcon#end of sib2, iclass 22, count 0 2006.169.07:56:45.14#ibcon#*mode == 0, iclass 22, count 0 2006.169.07:56:45.14#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.169.07:56:45.14#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.07:56:45.14#ibcon#*before write, iclass 22, count 0 2006.169.07:56:45.14#ibcon#enter sib2, iclass 22, count 0 2006.169.07:56:45.14#ibcon#flushed, iclass 22, count 0 2006.169.07:56:45.14#ibcon#about to write, iclass 22, count 0 2006.169.07:56:45.14#ibcon#wrote, iclass 22, count 0 2006.169.07:56:45.14#ibcon#about to read 3, iclass 22, count 0 2006.169.07:56:45.18#ibcon#read 3, iclass 22, count 0 2006.169.07:56:45.18#ibcon#about to read 4, iclass 22, count 0 2006.169.07:56:45.18#ibcon#read 4, iclass 22, count 0 2006.169.07:56:45.18#ibcon#about to read 5, iclass 22, count 0 2006.169.07:56:45.18#ibcon#read 5, iclass 22, count 0 2006.169.07:56:45.18#ibcon#about to read 6, iclass 22, count 0 2006.169.07:56:45.18#ibcon#read 6, iclass 22, count 0 2006.169.07:56:45.18#ibcon#end of sib2, iclass 22, count 0 2006.169.07:56:45.18#ibcon#*after write, iclass 22, count 0 2006.169.07:56:45.18#ibcon#*before return 0, iclass 22, count 0 2006.169.07:56:45.18#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:56:45.18#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:56:45.18#ibcon#about to clear, iclass 22 cls_cnt 0 2006.169.07:56:45.18#ibcon#cleared, iclass 22 cls_cnt 0 2006.169.07:56:45.18$vc4f8/va=2,7 2006.169.07:56:45.18#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.169.07:56:45.18#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.169.07:56:45.18#ibcon#ireg 11 cls_cnt 2 2006.169.07:56:45.18#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.169.07:56:45.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.169.07:56:45.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.169.07:56:45.24#ibcon#enter wrdev, iclass 24, count 2 2006.169.07:56:45.24#ibcon#first serial, iclass 24, count 2 2006.169.07:56:45.24#ibcon#enter sib2, iclass 24, count 2 2006.169.07:56:45.24#ibcon#flushed, iclass 24, count 2 2006.169.07:56:45.24#ibcon#about to write, iclass 24, count 2 2006.169.07:56:45.24#ibcon#wrote, iclass 24, count 2 2006.169.07:56:45.24#ibcon#about to read 3, iclass 24, count 2 2006.169.07:56:45.27#ibcon#read 3, iclass 24, count 2 2006.169.07:56:45.27#ibcon#about to read 4, iclass 24, count 2 2006.169.07:56:45.27#ibcon#read 4, iclass 24, count 2 2006.169.07:56:45.27#ibcon#about to read 5, iclass 24, count 2 2006.169.07:56:45.27#ibcon#read 5, iclass 24, count 2 2006.169.07:56:45.27#ibcon#about to read 6, iclass 24, count 2 2006.169.07:56:45.27#ibcon#read 6, iclass 24, count 2 2006.169.07:56:45.27#ibcon#end of sib2, iclass 24, count 2 2006.169.07:56:45.27#ibcon#*mode == 0, iclass 24, count 2 2006.169.07:56:45.27#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.169.07:56:45.27#ibcon#[25=AT02-07\r\n] 2006.169.07:56:45.27#ibcon#*before write, iclass 24, count 2 2006.169.07:56:45.27#ibcon#enter sib2, iclass 24, count 2 2006.169.07:56:45.27#ibcon#flushed, iclass 24, count 2 2006.169.07:56:45.27#ibcon#about to write, iclass 24, count 2 2006.169.07:56:45.27#ibcon#wrote, iclass 24, count 2 2006.169.07:56:45.27#ibcon#about to read 3, iclass 24, count 2 2006.169.07:56:45.30#ibcon#read 3, iclass 24, count 2 2006.169.07:56:45.30#ibcon#about to read 4, iclass 24, count 2 2006.169.07:56:45.30#ibcon#read 4, iclass 24, count 2 2006.169.07:56:45.30#ibcon#about to read 5, iclass 24, count 2 2006.169.07:56:45.30#ibcon#read 5, iclass 24, count 2 2006.169.07:56:45.30#ibcon#about to read 6, iclass 24, count 2 2006.169.07:56:45.30#ibcon#read 6, iclass 24, count 2 2006.169.07:56:45.30#ibcon#end of sib2, iclass 24, count 2 2006.169.07:56:45.30#ibcon#*after write, iclass 24, count 2 2006.169.07:56:45.30#ibcon#*before return 0, iclass 24, count 2 2006.169.07:56:45.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.169.07:56:45.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.169.07:56:45.30#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.169.07:56:45.30#ibcon#ireg 7 cls_cnt 0 2006.169.07:56:45.30#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.169.07:56:45.42#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.169.07:56:45.42#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.169.07:56:45.42#ibcon#enter wrdev, iclass 24, count 0 2006.169.07:56:45.42#ibcon#first serial, iclass 24, count 0 2006.169.07:56:45.42#ibcon#enter sib2, iclass 24, count 0 2006.169.07:56:45.42#ibcon#flushed, iclass 24, count 0 2006.169.07:56:45.42#ibcon#about to write, iclass 24, count 0 2006.169.07:56:45.42#ibcon#wrote, iclass 24, count 0 2006.169.07:56:45.42#ibcon#about to read 3, iclass 24, count 0 2006.169.07:56:45.44#ibcon#read 3, iclass 24, count 0 2006.169.07:56:45.44#ibcon#about to read 4, iclass 24, count 0 2006.169.07:56:45.44#ibcon#read 4, iclass 24, count 0 2006.169.07:56:45.44#ibcon#about to read 5, iclass 24, count 0 2006.169.07:56:45.44#ibcon#read 5, iclass 24, count 0 2006.169.07:56:45.44#ibcon#about to read 6, iclass 24, count 0 2006.169.07:56:45.44#ibcon#read 6, iclass 24, count 0 2006.169.07:56:45.44#ibcon#end of sib2, iclass 24, count 0 2006.169.07:56:45.44#ibcon#*mode == 0, iclass 24, count 0 2006.169.07:56:45.44#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.169.07:56:45.44#ibcon#[25=USB\r\n] 2006.169.07:56:45.44#ibcon#*before write, iclass 24, count 0 2006.169.07:56:45.44#ibcon#enter sib2, iclass 24, count 0 2006.169.07:56:45.44#ibcon#flushed, iclass 24, count 0 2006.169.07:56:45.44#ibcon#about to write, iclass 24, count 0 2006.169.07:56:45.44#ibcon#wrote, iclass 24, count 0 2006.169.07:56:45.44#ibcon#about to read 3, iclass 24, count 0 2006.169.07:56:45.47#ibcon#read 3, iclass 24, count 0 2006.169.07:56:45.47#ibcon#about to read 4, iclass 24, count 0 2006.169.07:56:45.47#ibcon#read 4, iclass 24, count 0 2006.169.07:56:45.47#ibcon#about to read 5, iclass 24, count 0 2006.169.07:56:45.47#ibcon#read 5, iclass 24, count 0 2006.169.07:56:45.47#ibcon#about to read 6, iclass 24, count 0 2006.169.07:56:45.47#ibcon#read 6, iclass 24, count 0 2006.169.07:56:45.47#ibcon#end of sib2, iclass 24, count 0 2006.169.07:56:45.47#ibcon#*after write, iclass 24, count 0 2006.169.07:56:45.47#ibcon#*before return 0, iclass 24, count 0 2006.169.07:56:45.47#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.169.07:56:45.47#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.169.07:56:45.47#ibcon#about to clear, iclass 24 cls_cnt 0 2006.169.07:56:45.47#ibcon#cleared, iclass 24 cls_cnt 0 2006.169.07:56:45.47$vc4f8/valo=3,672.99 2006.169.07:56:45.47#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.169.07:56:45.47#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.169.07:56:45.47#ibcon#ireg 17 cls_cnt 0 2006.169.07:56:45.47#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:56:45.47#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:56:45.47#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:56:45.47#ibcon#enter wrdev, iclass 26, count 0 2006.169.07:56:45.47#ibcon#first serial, iclass 26, count 0 2006.169.07:56:45.47#ibcon#enter sib2, iclass 26, count 0 2006.169.07:56:45.47#ibcon#flushed, iclass 26, count 0 2006.169.07:56:45.47#ibcon#about to write, iclass 26, count 0 2006.169.07:56:45.47#ibcon#wrote, iclass 26, count 0 2006.169.07:56:45.47#ibcon#about to read 3, iclass 26, count 0 2006.169.07:56:45.49#ibcon#read 3, iclass 26, count 0 2006.169.07:56:45.49#ibcon#about to read 4, iclass 26, count 0 2006.169.07:56:45.49#ibcon#read 4, iclass 26, count 0 2006.169.07:56:45.49#ibcon#about to read 5, iclass 26, count 0 2006.169.07:56:45.49#ibcon#read 5, iclass 26, count 0 2006.169.07:56:45.49#ibcon#about to read 6, iclass 26, count 0 2006.169.07:56:45.49#ibcon#read 6, iclass 26, count 0 2006.169.07:56:45.49#ibcon#end of sib2, iclass 26, count 0 2006.169.07:56:45.49#ibcon#*mode == 0, iclass 26, count 0 2006.169.07:56:45.49#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.169.07:56:45.49#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.07:56:45.49#ibcon#*before write, iclass 26, count 0 2006.169.07:56:45.49#ibcon#enter sib2, iclass 26, count 0 2006.169.07:56:45.49#ibcon#flushed, iclass 26, count 0 2006.169.07:56:45.49#ibcon#about to write, iclass 26, count 0 2006.169.07:56:45.49#ibcon#wrote, iclass 26, count 0 2006.169.07:56:45.49#ibcon#about to read 3, iclass 26, count 0 2006.169.07:56:45.53#ibcon#read 3, iclass 26, count 0 2006.169.07:56:45.53#ibcon#about to read 4, iclass 26, count 0 2006.169.07:56:45.53#ibcon#read 4, iclass 26, count 0 2006.169.07:56:45.53#ibcon#about to read 5, iclass 26, count 0 2006.169.07:56:45.53#ibcon#read 5, iclass 26, count 0 2006.169.07:56:45.53#ibcon#about to read 6, iclass 26, count 0 2006.169.07:56:45.53#ibcon#read 6, iclass 26, count 0 2006.169.07:56:45.53#ibcon#end of sib2, iclass 26, count 0 2006.169.07:56:45.53#ibcon#*after write, iclass 26, count 0 2006.169.07:56:45.53#ibcon#*before return 0, iclass 26, count 0 2006.169.07:56:45.53#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:56:45.53#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:56:45.53#ibcon#about to clear, iclass 26 cls_cnt 0 2006.169.07:56:45.53#ibcon#cleared, iclass 26 cls_cnt 0 2006.169.07:56:45.53$vc4f8/va=3,6 2006.169.07:56:45.53#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.169.07:56:45.53#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.169.07:56:45.53#ibcon#ireg 11 cls_cnt 2 2006.169.07:56:45.53#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.169.07:56:45.59#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.169.07:56:45.59#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.169.07:56:45.59#ibcon#enter wrdev, iclass 28, count 2 2006.169.07:56:45.59#ibcon#first serial, iclass 28, count 2 2006.169.07:56:45.59#ibcon#enter sib2, iclass 28, count 2 2006.169.07:56:45.59#ibcon#flushed, iclass 28, count 2 2006.169.07:56:45.59#ibcon#about to write, iclass 28, count 2 2006.169.07:56:45.59#ibcon#wrote, iclass 28, count 2 2006.169.07:56:45.59#ibcon#about to read 3, iclass 28, count 2 2006.169.07:56:45.61#ibcon#read 3, iclass 28, count 2 2006.169.07:56:45.61#ibcon#about to read 4, iclass 28, count 2 2006.169.07:56:45.61#ibcon#read 4, iclass 28, count 2 2006.169.07:56:45.61#ibcon#about to read 5, iclass 28, count 2 2006.169.07:56:45.61#ibcon#read 5, iclass 28, count 2 2006.169.07:56:45.61#ibcon#about to read 6, iclass 28, count 2 2006.169.07:56:45.61#ibcon#read 6, iclass 28, count 2 2006.169.07:56:45.61#ibcon#end of sib2, iclass 28, count 2 2006.169.07:56:45.61#ibcon#*mode == 0, iclass 28, count 2 2006.169.07:56:45.61#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.169.07:56:45.61#ibcon#[25=AT03-06\r\n] 2006.169.07:56:45.61#ibcon#*before write, iclass 28, count 2 2006.169.07:56:45.61#ibcon#enter sib2, iclass 28, count 2 2006.169.07:56:45.61#ibcon#flushed, iclass 28, count 2 2006.169.07:56:45.61#ibcon#about to write, iclass 28, count 2 2006.169.07:56:45.61#ibcon#wrote, iclass 28, count 2 2006.169.07:56:45.61#ibcon#about to read 3, iclass 28, count 2 2006.169.07:56:45.64#ibcon#read 3, iclass 28, count 2 2006.169.07:56:45.64#ibcon#about to read 4, iclass 28, count 2 2006.169.07:56:45.64#ibcon#read 4, iclass 28, count 2 2006.169.07:56:45.64#ibcon#about to read 5, iclass 28, count 2 2006.169.07:56:45.64#ibcon#read 5, iclass 28, count 2 2006.169.07:56:45.64#ibcon#about to read 6, iclass 28, count 2 2006.169.07:56:45.64#ibcon#read 6, iclass 28, count 2 2006.169.07:56:45.64#ibcon#end of sib2, iclass 28, count 2 2006.169.07:56:45.64#ibcon#*after write, iclass 28, count 2 2006.169.07:56:45.64#ibcon#*before return 0, iclass 28, count 2 2006.169.07:56:45.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.169.07:56:45.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.169.07:56:45.64#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.169.07:56:45.64#ibcon#ireg 7 cls_cnt 0 2006.169.07:56:45.64#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.169.07:56:45.76#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.169.07:56:45.76#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.169.07:56:45.76#ibcon#enter wrdev, iclass 28, count 0 2006.169.07:56:45.76#ibcon#first serial, iclass 28, count 0 2006.169.07:56:45.76#ibcon#enter sib2, iclass 28, count 0 2006.169.07:56:45.76#ibcon#flushed, iclass 28, count 0 2006.169.07:56:45.76#ibcon#about to write, iclass 28, count 0 2006.169.07:56:45.76#ibcon#wrote, iclass 28, count 0 2006.169.07:56:45.76#ibcon#about to read 3, iclass 28, count 0 2006.169.07:56:45.78#ibcon#read 3, iclass 28, count 0 2006.169.07:56:45.78#ibcon#about to read 4, iclass 28, count 0 2006.169.07:56:45.78#ibcon#read 4, iclass 28, count 0 2006.169.07:56:45.78#ibcon#about to read 5, iclass 28, count 0 2006.169.07:56:45.78#ibcon#read 5, iclass 28, count 0 2006.169.07:56:45.78#ibcon#about to read 6, iclass 28, count 0 2006.169.07:56:45.78#ibcon#read 6, iclass 28, count 0 2006.169.07:56:45.78#ibcon#end of sib2, iclass 28, count 0 2006.169.07:56:45.78#ibcon#*mode == 0, iclass 28, count 0 2006.169.07:56:45.78#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.169.07:56:45.78#ibcon#[25=USB\r\n] 2006.169.07:56:45.78#ibcon#*before write, iclass 28, count 0 2006.169.07:56:45.78#ibcon#enter sib2, iclass 28, count 0 2006.169.07:56:45.78#ibcon#flushed, iclass 28, count 0 2006.169.07:56:45.78#ibcon#about to write, iclass 28, count 0 2006.169.07:56:45.78#ibcon#wrote, iclass 28, count 0 2006.169.07:56:45.78#ibcon#about to read 3, iclass 28, count 0 2006.169.07:56:45.81#ibcon#read 3, iclass 28, count 0 2006.169.07:56:45.81#ibcon#about to read 4, iclass 28, count 0 2006.169.07:56:45.81#ibcon#read 4, iclass 28, count 0 2006.169.07:56:45.81#ibcon#about to read 5, iclass 28, count 0 2006.169.07:56:45.81#ibcon#read 5, iclass 28, count 0 2006.169.07:56:45.81#ibcon#about to read 6, iclass 28, count 0 2006.169.07:56:45.81#ibcon#read 6, iclass 28, count 0 2006.169.07:56:45.81#ibcon#end of sib2, iclass 28, count 0 2006.169.07:56:45.81#ibcon#*after write, iclass 28, count 0 2006.169.07:56:45.81#ibcon#*before return 0, iclass 28, count 0 2006.169.07:56:45.81#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.169.07:56:45.81#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.169.07:56:45.81#ibcon#about to clear, iclass 28 cls_cnt 0 2006.169.07:56:45.81#ibcon#cleared, iclass 28 cls_cnt 0 2006.169.07:56:45.81$vc4f8/valo=4,832.99 2006.169.07:56:45.81#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.169.07:56:45.81#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.169.07:56:45.81#ibcon#ireg 17 cls_cnt 0 2006.169.07:56:45.81#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:56:45.81#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:56:45.81#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:56:45.81#ibcon#enter wrdev, iclass 30, count 0 2006.169.07:56:45.81#ibcon#first serial, iclass 30, count 0 2006.169.07:56:45.81#ibcon#enter sib2, iclass 30, count 0 2006.169.07:56:45.81#ibcon#flushed, iclass 30, count 0 2006.169.07:56:45.81#ibcon#about to write, iclass 30, count 0 2006.169.07:56:45.81#ibcon#wrote, iclass 30, count 0 2006.169.07:56:45.81#ibcon#about to read 3, iclass 30, count 0 2006.169.07:56:45.83#ibcon#read 3, iclass 30, count 0 2006.169.07:56:45.83#ibcon#about to read 4, iclass 30, count 0 2006.169.07:56:45.83#ibcon#read 4, iclass 30, count 0 2006.169.07:56:45.83#ibcon#about to read 5, iclass 30, count 0 2006.169.07:56:45.83#ibcon#read 5, iclass 30, count 0 2006.169.07:56:45.83#ibcon#about to read 6, iclass 30, count 0 2006.169.07:56:45.83#ibcon#read 6, iclass 30, count 0 2006.169.07:56:45.83#ibcon#end of sib2, iclass 30, count 0 2006.169.07:56:45.83#ibcon#*mode == 0, iclass 30, count 0 2006.169.07:56:45.83#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.169.07:56:45.83#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.07:56:45.83#ibcon#*before write, iclass 30, count 0 2006.169.07:56:45.83#ibcon#enter sib2, iclass 30, count 0 2006.169.07:56:45.83#ibcon#flushed, iclass 30, count 0 2006.169.07:56:45.83#ibcon#about to write, iclass 30, count 0 2006.169.07:56:45.83#ibcon#wrote, iclass 30, count 0 2006.169.07:56:45.83#ibcon#about to read 3, iclass 30, count 0 2006.169.07:56:45.87#ibcon#read 3, iclass 30, count 0 2006.169.07:56:45.87#ibcon#about to read 4, iclass 30, count 0 2006.169.07:56:45.87#ibcon#read 4, iclass 30, count 0 2006.169.07:56:45.87#ibcon#about to read 5, iclass 30, count 0 2006.169.07:56:45.87#ibcon#read 5, iclass 30, count 0 2006.169.07:56:45.87#ibcon#about to read 6, iclass 30, count 0 2006.169.07:56:45.87#ibcon#read 6, iclass 30, count 0 2006.169.07:56:45.87#ibcon#end of sib2, iclass 30, count 0 2006.169.07:56:45.87#ibcon#*after write, iclass 30, count 0 2006.169.07:56:45.87#ibcon#*before return 0, iclass 30, count 0 2006.169.07:56:45.87#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:56:45.87#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:56:45.87#ibcon#about to clear, iclass 30 cls_cnt 0 2006.169.07:56:45.87#ibcon#cleared, iclass 30 cls_cnt 0 2006.169.07:56:45.87$vc4f8/va=4,7 2006.169.07:56:45.87#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.169.07:56:45.87#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.169.07:56:45.87#ibcon#ireg 11 cls_cnt 2 2006.169.07:56:45.87#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:56:45.93#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:56:45.93#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:56:45.93#ibcon#enter wrdev, iclass 32, count 2 2006.169.07:56:45.93#ibcon#first serial, iclass 32, count 2 2006.169.07:56:45.93#ibcon#enter sib2, iclass 32, count 2 2006.169.07:56:45.93#ibcon#flushed, iclass 32, count 2 2006.169.07:56:45.93#ibcon#about to write, iclass 32, count 2 2006.169.07:56:45.93#ibcon#wrote, iclass 32, count 2 2006.169.07:56:45.93#ibcon#about to read 3, iclass 32, count 2 2006.169.07:56:45.95#ibcon#read 3, iclass 32, count 2 2006.169.07:56:45.95#ibcon#about to read 4, iclass 32, count 2 2006.169.07:56:45.95#ibcon#read 4, iclass 32, count 2 2006.169.07:56:45.95#ibcon#about to read 5, iclass 32, count 2 2006.169.07:56:45.95#ibcon#read 5, iclass 32, count 2 2006.169.07:56:45.95#ibcon#about to read 6, iclass 32, count 2 2006.169.07:56:45.95#ibcon#read 6, iclass 32, count 2 2006.169.07:56:45.95#ibcon#end of sib2, iclass 32, count 2 2006.169.07:56:45.95#ibcon#*mode == 0, iclass 32, count 2 2006.169.07:56:45.95#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.169.07:56:45.95#ibcon#[25=AT04-07\r\n] 2006.169.07:56:45.95#ibcon#*before write, iclass 32, count 2 2006.169.07:56:45.95#ibcon#enter sib2, iclass 32, count 2 2006.169.07:56:45.95#ibcon#flushed, iclass 32, count 2 2006.169.07:56:45.95#ibcon#about to write, iclass 32, count 2 2006.169.07:56:45.95#ibcon#wrote, iclass 32, count 2 2006.169.07:56:45.95#ibcon#about to read 3, iclass 32, count 2 2006.169.07:56:45.98#ibcon#read 3, iclass 32, count 2 2006.169.07:56:45.98#ibcon#about to read 4, iclass 32, count 2 2006.169.07:56:45.98#ibcon#read 4, iclass 32, count 2 2006.169.07:56:45.98#ibcon#about to read 5, iclass 32, count 2 2006.169.07:56:45.98#ibcon#read 5, iclass 32, count 2 2006.169.07:56:45.98#ibcon#about to read 6, iclass 32, count 2 2006.169.07:56:45.98#ibcon#read 6, iclass 32, count 2 2006.169.07:56:45.98#ibcon#end of sib2, iclass 32, count 2 2006.169.07:56:45.98#ibcon#*after write, iclass 32, count 2 2006.169.07:56:45.98#ibcon#*before return 0, iclass 32, count 2 2006.169.07:56:45.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:56:45.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:56:45.98#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.169.07:56:45.98#ibcon#ireg 7 cls_cnt 0 2006.169.07:56:45.98#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:56:46.10#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:56:46.10#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:56:46.10#ibcon#enter wrdev, iclass 32, count 0 2006.169.07:56:46.10#ibcon#first serial, iclass 32, count 0 2006.169.07:56:46.10#ibcon#enter sib2, iclass 32, count 0 2006.169.07:56:46.10#ibcon#flushed, iclass 32, count 0 2006.169.07:56:46.10#ibcon#about to write, iclass 32, count 0 2006.169.07:56:46.10#ibcon#wrote, iclass 32, count 0 2006.169.07:56:46.10#ibcon#about to read 3, iclass 32, count 0 2006.169.07:56:46.12#ibcon#read 3, iclass 32, count 0 2006.169.07:56:46.12#ibcon#about to read 4, iclass 32, count 0 2006.169.07:56:46.12#ibcon#read 4, iclass 32, count 0 2006.169.07:56:46.12#ibcon#about to read 5, iclass 32, count 0 2006.169.07:56:46.12#ibcon#read 5, iclass 32, count 0 2006.169.07:56:46.12#ibcon#about to read 6, iclass 32, count 0 2006.169.07:56:46.12#ibcon#read 6, iclass 32, count 0 2006.169.07:56:46.12#ibcon#end of sib2, iclass 32, count 0 2006.169.07:56:46.12#ibcon#*mode == 0, iclass 32, count 0 2006.169.07:56:46.12#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.169.07:56:46.12#ibcon#[25=USB\r\n] 2006.169.07:56:46.12#ibcon#*before write, iclass 32, count 0 2006.169.07:56:46.12#ibcon#enter sib2, iclass 32, count 0 2006.169.07:56:46.12#ibcon#flushed, iclass 32, count 0 2006.169.07:56:46.12#ibcon#about to write, iclass 32, count 0 2006.169.07:56:46.12#ibcon#wrote, iclass 32, count 0 2006.169.07:56:46.12#ibcon#about to read 3, iclass 32, count 0 2006.169.07:56:46.15#ibcon#read 3, iclass 32, count 0 2006.169.07:56:46.15#ibcon#about to read 4, iclass 32, count 0 2006.169.07:56:46.15#ibcon#read 4, iclass 32, count 0 2006.169.07:56:46.15#ibcon#about to read 5, iclass 32, count 0 2006.169.07:56:46.15#ibcon#read 5, iclass 32, count 0 2006.169.07:56:46.15#ibcon#about to read 6, iclass 32, count 0 2006.169.07:56:46.15#ibcon#read 6, iclass 32, count 0 2006.169.07:56:46.15#ibcon#end of sib2, iclass 32, count 0 2006.169.07:56:46.15#ibcon#*after write, iclass 32, count 0 2006.169.07:56:46.15#ibcon#*before return 0, iclass 32, count 0 2006.169.07:56:46.15#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:56:46.15#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:56:46.15#ibcon#about to clear, iclass 32 cls_cnt 0 2006.169.07:56:46.15#ibcon#cleared, iclass 32 cls_cnt 0 2006.169.07:56:46.15$vc4f8/valo=5,652.99 2006.169.07:56:46.15#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.169.07:56:46.15#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.169.07:56:46.15#ibcon#ireg 17 cls_cnt 0 2006.169.07:56:46.15#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:56:46.15#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:56:46.15#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:56:46.15#ibcon#enter wrdev, iclass 34, count 0 2006.169.07:56:46.15#ibcon#first serial, iclass 34, count 0 2006.169.07:56:46.15#ibcon#enter sib2, iclass 34, count 0 2006.169.07:56:46.15#ibcon#flushed, iclass 34, count 0 2006.169.07:56:46.15#ibcon#about to write, iclass 34, count 0 2006.169.07:56:46.15#ibcon#wrote, iclass 34, count 0 2006.169.07:56:46.15#ibcon#about to read 3, iclass 34, count 0 2006.169.07:56:46.17#ibcon#read 3, iclass 34, count 0 2006.169.07:56:46.17#ibcon#about to read 4, iclass 34, count 0 2006.169.07:56:46.17#ibcon#read 4, iclass 34, count 0 2006.169.07:56:46.17#ibcon#about to read 5, iclass 34, count 0 2006.169.07:56:46.17#ibcon#read 5, iclass 34, count 0 2006.169.07:56:46.17#ibcon#about to read 6, iclass 34, count 0 2006.169.07:56:46.17#ibcon#read 6, iclass 34, count 0 2006.169.07:56:46.17#ibcon#end of sib2, iclass 34, count 0 2006.169.07:56:46.17#ibcon#*mode == 0, iclass 34, count 0 2006.169.07:56:46.17#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.169.07:56:46.17#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.07:56:46.17#ibcon#*before write, iclass 34, count 0 2006.169.07:56:46.17#ibcon#enter sib2, iclass 34, count 0 2006.169.07:56:46.17#ibcon#flushed, iclass 34, count 0 2006.169.07:56:46.17#ibcon#about to write, iclass 34, count 0 2006.169.07:56:46.17#ibcon#wrote, iclass 34, count 0 2006.169.07:56:46.17#ibcon#about to read 3, iclass 34, count 0 2006.169.07:56:46.21#ibcon#read 3, iclass 34, count 0 2006.169.07:56:46.21#ibcon#about to read 4, iclass 34, count 0 2006.169.07:56:46.21#ibcon#read 4, iclass 34, count 0 2006.169.07:56:46.21#ibcon#about to read 5, iclass 34, count 0 2006.169.07:56:46.21#ibcon#read 5, iclass 34, count 0 2006.169.07:56:46.21#ibcon#about to read 6, iclass 34, count 0 2006.169.07:56:46.21#ibcon#read 6, iclass 34, count 0 2006.169.07:56:46.21#ibcon#end of sib2, iclass 34, count 0 2006.169.07:56:46.21#ibcon#*after write, iclass 34, count 0 2006.169.07:56:46.21#ibcon#*before return 0, iclass 34, count 0 2006.169.07:56:46.21#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:56:46.21#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:56:46.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.169.07:56:46.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.169.07:56:46.21$vc4f8/va=5,7 2006.169.07:56:46.21#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.169.07:56:46.21#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.169.07:56:46.21#ibcon#ireg 11 cls_cnt 2 2006.169.07:56:46.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.169.07:56:46.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.169.07:56:46.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.169.07:56:46.27#ibcon#enter wrdev, iclass 36, count 2 2006.169.07:56:46.27#ibcon#first serial, iclass 36, count 2 2006.169.07:56:46.27#ibcon#enter sib2, iclass 36, count 2 2006.169.07:56:46.27#ibcon#flushed, iclass 36, count 2 2006.169.07:56:46.27#ibcon#about to write, iclass 36, count 2 2006.169.07:56:46.27#ibcon#wrote, iclass 36, count 2 2006.169.07:56:46.27#ibcon#about to read 3, iclass 36, count 2 2006.169.07:56:46.29#ibcon#read 3, iclass 36, count 2 2006.169.07:56:46.29#ibcon#about to read 4, iclass 36, count 2 2006.169.07:56:46.29#ibcon#read 4, iclass 36, count 2 2006.169.07:56:46.29#ibcon#about to read 5, iclass 36, count 2 2006.169.07:56:46.29#ibcon#read 5, iclass 36, count 2 2006.169.07:56:46.29#ibcon#about to read 6, iclass 36, count 2 2006.169.07:56:46.29#ibcon#read 6, iclass 36, count 2 2006.169.07:56:46.29#ibcon#end of sib2, iclass 36, count 2 2006.169.07:56:46.29#ibcon#*mode == 0, iclass 36, count 2 2006.169.07:56:46.29#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.169.07:56:46.29#ibcon#[25=AT05-07\r\n] 2006.169.07:56:46.29#ibcon#*before write, iclass 36, count 2 2006.169.07:56:46.29#ibcon#enter sib2, iclass 36, count 2 2006.169.07:56:46.29#ibcon#flushed, iclass 36, count 2 2006.169.07:56:46.29#ibcon#about to write, iclass 36, count 2 2006.169.07:56:46.29#ibcon#wrote, iclass 36, count 2 2006.169.07:56:46.29#ibcon#about to read 3, iclass 36, count 2 2006.169.07:56:46.32#ibcon#read 3, iclass 36, count 2 2006.169.07:56:46.32#ibcon#about to read 4, iclass 36, count 2 2006.169.07:56:46.32#ibcon#read 4, iclass 36, count 2 2006.169.07:56:46.32#ibcon#about to read 5, iclass 36, count 2 2006.169.07:56:46.32#ibcon#read 5, iclass 36, count 2 2006.169.07:56:46.32#ibcon#about to read 6, iclass 36, count 2 2006.169.07:56:46.32#ibcon#read 6, iclass 36, count 2 2006.169.07:56:46.32#ibcon#end of sib2, iclass 36, count 2 2006.169.07:56:46.32#ibcon#*after write, iclass 36, count 2 2006.169.07:56:46.32#ibcon#*before return 0, iclass 36, count 2 2006.169.07:56:46.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.169.07:56:46.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.169.07:56:46.32#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.169.07:56:46.32#ibcon#ireg 7 cls_cnt 0 2006.169.07:56:46.32#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.169.07:56:46.44#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.169.07:56:46.44#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.169.07:56:46.44#ibcon#enter wrdev, iclass 36, count 0 2006.169.07:56:46.44#ibcon#first serial, iclass 36, count 0 2006.169.07:56:46.44#ibcon#enter sib2, iclass 36, count 0 2006.169.07:56:46.44#ibcon#flushed, iclass 36, count 0 2006.169.07:56:46.44#ibcon#about to write, iclass 36, count 0 2006.169.07:56:46.44#ibcon#wrote, iclass 36, count 0 2006.169.07:56:46.44#ibcon#about to read 3, iclass 36, count 0 2006.169.07:56:46.46#ibcon#read 3, iclass 36, count 0 2006.169.07:56:46.46#ibcon#about to read 4, iclass 36, count 0 2006.169.07:56:46.46#ibcon#read 4, iclass 36, count 0 2006.169.07:56:46.46#ibcon#about to read 5, iclass 36, count 0 2006.169.07:56:46.46#ibcon#read 5, iclass 36, count 0 2006.169.07:56:46.46#ibcon#about to read 6, iclass 36, count 0 2006.169.07:56:46.46#ibcon#read 6, iclass 36, count 0 2006.169.07:56:46.46#ibcon#end of sib2, iclass 36, count 0 2006.169.07:56:46.46#ibcon#*mode == 0, iclass 36, count 0 2006.169.07:56:46.46#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.169.07:56:46.46#ibcon#[25=USB\r\n] 2006.169.07:56:46.46#ibcon#*before write, iclass 36, count 0 2006.169.07:56:46.46#ibcon#enter sib2, iclass 36, count 0 2006.169.07:56:46.46#ibcon#flushed, iclass 36, count 0 2006.169.07:56:46.46#ibcon#about to write, iclass 36, count 0 2006.169.07:56:46.46#ibcon#wrote, iclass 36, count 0 2006.169.07:56:46.46#ibcon#about to read 3, iclass 36, count 0 2006.169.07:56:46.49#ibcon#read 3, iclass 36, count 0 2006.169.07:56:46.49#ibcon#about to read 4, iclass 36, count 0 2006.169.07:56:46.49#ibcon#read 4, iclass 36, count 0 2006.169.07:56:46.49#ibcon#about to read 5, iclass 36, count 0 2006.169.07:56:46.49#ibcon#read 5, iclass 36, count 0 2006.169.07:56:46.49#ibcon#about to read 6, iclass 36, count 0 2006.169.07:56:46.49#ibcon#read 6, iclass 36, count 0 2006.169.07:56:46.49#ibcon#end of sib2, iclass 36, count 0 2006.169.07:56:46.49#ibcon#*after write, iclass 36, count 0 2006.169.07:56:46.49#ibcon#*before return 0, iclass 36, count 0 2006.169.07:56:46.49#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.169.07:56:46.49#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.169.07:56:46.49#ibcon#about to clear, iclass 36 cls_cnt 0 2006.169.07:56:46.49#ibcon#cleared, iclass 36 cls_cnt 0 2006.169.07:56:46.49$vc4f8/valo=6,772.99 2006.169.07:56:46.49#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.169.07:56:46.49#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.169.07:56:46.49#ibcon#ireg 17 cls_cnt 0 2006.169.07:56:46.49#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:56:46.49#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:56:46.49#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:56:46.49#ibcon#enter wrdev, iclass 38, count 0 2006.169.07:56:46.49#ibcon#first serial, iclass 38, count 0 2006.169.07:56:46.49#ibcon#enter sib2, iclass 38, count 0 2006.169.07:56:46.49#ibcon#flushed, iclass 38, count 0 2006.169.07:56:46.49#ibcon#about to write, iclass 38, count 0 2006.169.07:56:46.49#ibcon#wrote, iclass 38, count 0 2006.169.07:56:46.49#ibcon#about to read 3, iclass 38, count 0 2006.169.07:56:46.51#ibcon#read 3, iclass 38, count 0 2006.169.07:56:46.51#ibcon#about to read 4, iclass 38, count 0 2006.169.07:56:46.51#ibcon#read 4, iclass 38, count 0 2006.169.07:56:46.51#ibcon#about to read 5, iclass 38, count 0 2006.169.07:56:46.51#ibcon#read 5, iclass 38, count 0 2006.169.07:56:46.51#ibcon#about to read 6, iclass 38, count 0 2006.169.07:56:46.51#ibcon#read 6, iclass 38, count 0 2006.169.07:56:46.51#ibcon#end of sib2, iclass 38, count 0 2006.169.07:56:46.51#ibcon#*mode == 0, iclass 38, count 0 2006.169.07:56:46.51#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.169.07:56:46.51#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.07:56:46.51#ibcon#*before write, iclass 38, count 0 2006.169.07:56:46.51#ibcon#enter sib2, iclass 38, count 0 2006.169.07:56:46.51#ibcon#flushed, iclass 38, count 0 2006.169.07:56:46.51#ibcon#about to write, iclass 38, count 0 2006.169.07:56:46.51#ibcon#wrote, iclass 38, count 0 2006.169.07:56:46.51#ibcon#about to read 3, iclass 38, count 0 2006.169.07:56:46.55#ibcon#read 3, iclass 38, count 0 2006.169.07:56:46.55#ibcon#about to read 4, iclass 38, count 0 2006.169.07:56:46.55#ibcon#read 4, iclass 38, count 0 2006.169.07:56:46.55#ibcon#about to read 5, iclass 38, count 0 2006.169.07:56:46.55#ibcon#read 5, iclass 38, count 0 2006.169.07:56:46.55#ibcon#about to read 6, iclass 38, count 0 2006.169.07:56:46.55#ibcon#read 6, iclass 38, count 0 2006.169.07:56:46.55#ibcon#end of sib2, iclass 38, count 0 2006.169.07:56:46.55#ibcon#*after write, iclass 38, count 0 2006.169.07:56:46.55#ibcon#*before return 0, iclass 38, count 0 2006.169.07:56:46.55#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:56:46.55#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:56:46.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.169.07:56:46.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.169.07:56:46.55$vc4f8/va=6,6 2006.169.07:56:46.55#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.169.07:56:46.55#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.169.07:56:46.55#ibcon#ireg 11 cls_cnt 2 2006.169.07:56:46.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.169.07:56:46.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.169.07:56:46.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.169.07:56:46.61#ibcon#enter wrdev, iclass 40, count 2 2006.169.07:56:46.61#ibcon#first serial, iclass 40, count 2 2006.169.07:56:46.61#ibcon#enter sib2, iclass 40, count 2 2006.169.07:56:46.61#ibcon#flushed, iclass 40, count 2 2006.169.07:56:46.61#ibcon#about to write, iclass 40, count 2 2006.169.07:56:46.61#ibcon#wrote, iclass 40, count 2 2006.169.07:56:46.61#ibcon#about to read 3, iclass 40, count 2 2006.169.07:56:46.63#ibcon#read 3, iclass 40, count 2 2006.169.07:56:46.63#ibcon#about to read 4, iclass 40, count 2 2006.169.07:56:46.63#ibcon#read 4, iclass 40, count 2 2006.169.07:56:46.63#ibcon#about to read 5, iclass 40, count 2 2006.169.07:56:46.63#ibcon#read 5, iclass 40, count 2 2006.169.07:56:46.63#ibcon#about to read 6, iclass 40, count 2 2006.169.07:56:46.63#ibcon#read 6, iclass 40, count 2 2006.169.07:56:46.63#ibcon#end of sib2, iclass 40, count 2 2006.169.07:56:46.63#ibcon#*mode == 0, iclass 40, count 2 2006.169.07:56:46.63#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.169.07:56:46.63#ibcon#[25=AT06-06\r\n] 2006.169.07:56:46.63#ibcon#*before write, iclass 40, count 2 2006.169.07:56:46.63#ibcon#enter sib2, iclass 40, count 2 2006.169.07:56:46.63#ibcon#flushed, iclass 40, count 2 2006.169.07:56:46.63#ibcon#about to write, iclass 40, count 2 2006.169.07:56:46.63#ibcon#wrote, iclass 40, count 2 2006.169.07:56:46.63#ibcon#about to read 3, iclass 40, count 2 2006.169.07:56:46.66#ibcon#read 3, iclass 40, count 2 2006.169.07:56:46.66#ibcon#about to read 4, iclass 40, count 2 2006.169.07:56:46.66#ibcon#read 4, iclass 40, count 2 2006.169.07:56:46.66#ibcon#about to read 5, iclass 40, count 2 2006.169.07:56:46.66#ibcon#read 5, iclass 40, count 2 2006.169.07:56:46.66#ibcon#about to read 6, iclass 40, count 2 2006.169.07:56:46.66#ibcon#read 6, iclass 40, count 2 2006.169.07:56:46.66#ibcon#end of sib2, iclass 40, count 2 2006.169.07:56:46.66#ibcon#*after write, iclass 40, count 2 2006.169.07:56:46.66#ibcon#*before return 0, iclass 40, count 2 2006.169.07:56:46.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.169.07:56:46.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.169.07:56:46.66#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.169.07:56:46.66#ibcon#ireg 7 cls_cnt 0 2006.169.07:56:46.66#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.169.07:56:46.78#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.169.07:56:46.78#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.169.07:56:46.78#ibcon#enter wrdev, iclass 40, count 0 2006.169.07:56:46.78#ibcon#first serial, iclass 40, count 0 2006.169.07:56:46.78#ibcon#enter sib2, iclass 40, count 0 2006.169.07:56:46.78#ibcon#flushed, iclass 40, count 0 2006.169.07:56:46.78#ibcon#about to write, iclass 40, count 0 2006.169.07:56:46.78#ibcon#wrote, iclass 40, count 0 2006.169.07:56:46.78#ibcon#about to read 3, iclass 40, count 0 2006.169.07:56:46.80#ibcon#read 3, iclass 40, count 0 2006.169.07:56:46.80#ibcon#about to read 4, iclass 40, count 0 2006.169.07:56:46.80#ibcon#read 4, iclass 40, count 0 2006.169.07:56:46.80#ibcon#about to read 5, iclass 40, count 0 2006.169.07:56:46.80#ibcon#read 5, iclass 40, count 0 2006.169.07:56:46.80#ibcon#about to read 6, iclass 40, count 0 2006.169.07:56:46.80#ibcon#read 6, iclass 40, count 0 2006.169.07:56:46.80#ibcon#end of sib2, iclass 40, count 0 2006.169.07:56:46.80#ibcon#*mode == 0, iclass 40, count 0 2006.169.07:56:46.80#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.169.07:56:46.80#ibcon#[25=USB\r\n] 2006.169.07:56:46.80#ibcon#*before write, iclass 40, count 0 2006.169.07:56:46.80#ibcon#enter sib2, iclass 40, count 0 2006.169.07:56:46.80#ibcon#flushed, iclass 40, count 0 2006.169.07:56:46.80#ibcon#about to write, iclass 40, count 0 2006.169.07:56:46.80#ibcon#wrote, iclass 40, count 0 2006.169.07:56:46.80#ibcon#about to read 3, iclass 40, count 0 2006.169.07:56:46.83#ibcon#read 3, iclass 40, count 0 2006.169.07:56:46.83#ibcon#about to read 4, iclass 40, count 0 2006.169.07:56:46.83#ibcon#read 4, iclass 40, count 0 2006.169.07:56:46.83#ibcon#about to read 5, iclass 40, count 0 2006.169.07:56:46.83#ibcon#read 5, iclass 40, count 0 2006.169.07:56:46.83#ibcon#about to read 6, iclass 40, count 0 2006.169.07:56:46.83#ibcon#read 6, iclass 40, count 0 2006.169.07:56:46.83#ibcon#end of sib2, iclass 40, count 0 2006.169.07:56:46.83#ibcon#*after write, iclass 40, count 0 2006.169.07:56:46.83#ibcon#*before return 0, iclass 40, count 0 2006.169.07:56:46.83#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.169.07:56:46.83#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.169.07:56:46.83#ibcon#about to clear, iclass 40 cls_cnt 0 2006.169.07:56:46.83#ibcon#cleared, iclass 40 cls_cnt 0 2006.169.07:56:46.83$vc4f8/valo=7,832.99 2006.169.07:56:46.83#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.169.07:56:46.83#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.169.07:56:46.83#ibcon#ireg 17 cls_cnt 0 2006.169.07:56:46.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.169.07:56:46.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.169.07:56:46.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.169.07:56:46.83#ibcon#enter wrdev, iclass 4, count 0 2006.169.07:56:46.83#ibcon#first serial, iclass 4, count 0 2006.169.07:56:46.83#ibcon#enter sib2, iclass 4, count 0 2006.169.07:56:46.83#ibcon#flushed, iclass 4, count 0 2006.169.07:56:46.83#ibcon#about to write, iclass 4, count 0 2006.169.07:56:46.83#ibcon#wrote, iclass 4, count 0 2006.169.07:56:46.83#ibcon#about to read 3, iclass 4, count 0 2006.169.07:56:46.85#ibcon#read 3, iclass 4, count 0 2006.169.07:56:46.85#ibcon#about to read 4, iclass 4, count 0 2006.169.07:56:46.85#ibcon#read 4, iclass 4, count 0 2006.169.07:56:46.85#ibcon#about to read 5, iclass 4, count 0 2006.169.07:56:46.85#ibcon#read 5, iclass 4, count 0 2006.169.07:56:46.85#ibcon#about to read 6, iclass 4, count 0 2006.169.07:56:46.85#ibcon#read 6, iclass 4, count 0 2006.169.07:56:46.85#ibcon#end of sib2, iclass 4, count 0 2006.169.07:56:46.85#ibcon#*mode == 0, iclass 4, count 0 2006.169.07:56:46.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.169.07:56:46.85#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.07:56:46.85#ibcon#*before write, iclass 4, count 0 2006.169.07:56:46.85#ibcon#enter sib2, iclass 4, count 0 2006.169.07:56:46.85#ibcon#flushed, iclass 4, count 0 2006.169.07:56:46.85#ibcon#about to write, iclass 4, count 0 2006.169.07:56:46.85#ibcon#wrote, iclass 4, count 0 2006.169.07:56:46.85#ibcon#about to read 3, iclass 4, count 0 2006.169.07:56:46.89#ibcon#read 3, iclass 4, count 0 2006.169.07:56:46.89#ibcon#about to read 4, iclass 4, count 0 2006.169.07:56:46.89#ibcon#read 4, iclass 4, count 0 2006.169.07:56:46.89#ibcon#about to read 5, iclass 4, count 0 2006.169.07:56:46.89#ibcon#read 5, iclass 4, count 0 2006.169.07:56:46.89#ibcon#about to read 6, iclass 4, count 0 2006.169.07:56:46.89#ibcon#read 6, iclass 4, count 0 2006.169.07:56:46.89#ibcon#end of sib2, iclass 4, count 0 2006.169.07:56:46.89#ibcon#*after write, iclass 4, count 0 2006.169.07:56:46.89#ibcon#*before return 0, iclass 4, count 0 2006.169.07:56:46.89#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.169.07:56:46.89#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.169.07:56:46.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.169.07:56:46.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.169.07:56:46.89$vc4f8/va=7,6 2006.169.07:56:46.89#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.169.07:56:46.89#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.169.07:56:46.89#ibcon#ireg 11 cls_cnt 2 2006.169.07:56:46.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.169.07:56:46.95#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.169.07:56:46.95#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.169.07:56:46.95#ibcon#enter wrdev, iclass 6, count 2 2006.169.07:56:46.95#ibcon#first serial, iclass 6, count 2 2006.169.07:56:46.95#ibcon#enter sib2, iclass 6, count 2 2006.169.07:56:46.95#ibcon#flushed, iclass 6, count 2 2006.169.07:56:46.95#ibcon#about to write, iclass 6, count 2 2006.169.07:56:46.95#ibcon#wrote, iclass 6, count 2 2006.169.07:56:46.95#ibcon#about to read 3, iclass 6, count 2 2006.169.07:56:46.97#ibcon#read 3, iclass 6, count 2 2006.169.07:56:46.97#ibcon#about to read 4, iclass 6, count 2 2006.169.07:56:46.97#ibcon#read 4, iclass 6, count 2 2006.169.07:56:46.97#ibcon#about to read 5, iclass 6, count 2 2006.169.07:56:46.97#ibcon#read 5, iclass 6, count 2 2006.169.07:56:46.97#ibcon#about to read 6, iclass 6, count 2 2006.169.07:56:46.97#ibcon#read 6, iclass 6, count 2 2006.169.07:56:46.97#ibcon#end of sib2, iclass 6, count 2 2006.169.07:56:46.97#ibcon#*mode == 0, iclass 6, count 2 2006.169.07:56:46.97#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.169.07:56:46.97#ibcon#[25=AT07-06\r\n] 2006.169.07:56:46.97#ibcon#*before write, iclass 6, count 2 2006.169.07:56:46.97#ibcon#enter sib2, iclass 6, count 2 2006.169.07:56:46.97#ibcon#flushed, iclass 6, count 2 2006.169.07:56:46.97#ibcon#about to write, iclass 6, count 2 2006.169.07:56:46.97#ibcon#wrote, iclass 6, count 2 2006.169.07:56:46.97#ibcon#about to read 3, iclass 6, count 2 2006.169.07:56:47.00#ibcon#read 3, iclass 6, count 2 2006.169.07:56:47.00#ibcon#about to read 4, iclass 6, count 2 2006.169.07:56:47.00#ibcon#read 4, iclass 6, count 2 2006.169.07:56:47.00#ibcon#about to read 5, iclass 6, count 2 2006.169.07:56:47.00#ibcon#read 5, iclass 6, count 2 2006.169.07:56:47.00#ibcon#about to read 6, iclass 6, count 2 2006.169.07:56:47.00#ibcon#read 6, iclass 6, count 2 2006.169.07:56:47.00#ibcon#end of sib2, iclass 6, count 2 2006.169.07:56:47.00#ibcon#*after write, iclass 6, count 2 2006.169.07:56:47.00#ibcon#*before return 0, iclass 6, count 2 2006.169.07:56:47.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.169.07:56:47.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.169.07:56:47.00#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.169.07:56:47.00#ibcon#ireg 7 cls_cnt 0 2006.169.07:56:47.00#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.169.07:56:47.12#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.169.07:56:47.12#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.169.07:56:47.12#ibcon#enter wrdev, iclass 6, count 0 2006.169.07:56:47.12#ibcon#first serial, iclass 6, count 0 2006.169.07:56:47.12#ibcon#enter sib2, iclass 6, count 0 2006.169.07:56:47.12#ibcon#flushed, iclass 6, count 0 2006.169.07:56:47.12#ibcon#about to write, iclass 6, count 0 2006.169.07:56:47.12#ibcon#wrote, iclass 6, count 0 2006.169.07:56:47.12#ibcon#about to read 3, iclass 6, count 0 2006.169.07:56:47.14#ibcon#read 3, iclass 6, count 0 2006.169.07:56:47.14#ibcon#about to read 4, iclass 6, count 0 2006.169.07:56:47.14#ibcon#read 4, iclass 6, count 0 2006.169.07:56:47.14#ibcon#about to read 5, iclass 6, count 0 2006.169.07:56:47.14#ibcon#read 5, iclass 6, count 0 2006.169.07:56:47.14#ibcon#about to read 6, iclass 6, count 0 2006.169.07:56:47.14#ibcon#read 6, iclass 6, count 0 2006.169.07:56:47.14#ibcon#end of sib2, iclass 6, count 0 2006.169.07:56:47.14#ibcon#*mode == 0, iclass 6, count 0 2006.169.07:56:47.14#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.169.07:56:47.14#ibcon#[25=USB\r\n] 2006.169.07:56:47.14#ibcon#*before write, iclass 6, count 0 2006.169.07:56:47.14#ibcon#enter sib2, iclass 6, count 0 2006.169.07:56:47.14#ibcon#flushed, iclass 6, count 0 2006.169.07:56:47.14#ibcon#about to write, iclass 6, count 0 2006.169.07:56:47.14#ibcon#wrote, iclass 6, count 0 2006.169.07:56:47.14#ibcon#about to read 3, iclass 6, count 0 2006.169.07:56:47.17#ibcon#read 3, iclass 6, count 0 2006.169.07:56:47.17#ibcon#about to read 4, iclass 6, count 0 2006.169.07:56:47.17#ibcon#read 4, iclass 6, count 0 2006.169.07:56:47.17#ibcon#about to read 5, iclass 6, count 0 2006.169.07:56:47.17#ibcon#read 5, iclass 6, count 0 2006.169.07:56:47.17#ibcon#about to read 6, iclass 6, count 0 2006.169.07:56:47.17#ibcon#read 6, iclass 6, count 0 2006.169.07:56:47.17#ibcon#end of sib2, iclass 6, count 0 2006.169.07:56:47.17#ibcon#*after write, iclass 6, count 0 2006.169.07:56:47.17#ibcon#*before return 0, iclass 6, count 0 2006.169.07:56:47.17#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.169.07:56:47.17#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.169.07:56:47.17#ibcon#about to clear, iclass 6 cls_cnt 0 2006.169.07:56:47.17#ibcon#cleared, iclass 6 cls_cnt 0 2006.169.07:56:47.17$vc4f8/valo=8,852.99 2006.169.07:56:47.17#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.169.07:56:47.17#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.169.07:56:47.17#ibcon#ireg 17 cls_cnt 0 2006.169.07:56:47.17#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.169.07:56:47.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.169.07:56:47.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.169.07:56:47.17#ibcon#enter wrdev, iclass 10, count 0 2006.169.07:56:47.17#ibcon#first serial, iclass 10, count 0 2006.169.07:56:47.17#ibcon#enter sib2, iclass 10, count 0 2006.169.07:56:47.17#ibcon#flushed, iclass 10, count 0 2006.169.07:56:47.17#ibcon#about to write, iclass 10, count 0 2006.169.07:56:47.17#ibcon#wrote, iclass 10, count 0 2006.169.07:56:47.17#ibcon#about to read 3, iclass 10, count 0 2006.169.07:56:47.20#ibcon#read 3, iclass 10, count 0 2006.169.07:56:47.20#ibcon#about to read 4, iclass 10, count 0 2006.169.07:56:47.20#ibcon#read 4, iclass 10, count 0 2006.169.07:56:47.20#ibcon#about to read 5, iclass 10, count 0 2006.169.07:56:47.20#ibcon#read 5, iclass 10, count 0 2006.169.07:56:47.20#ibcon#about to read 6, iclass 10, count 0 2006.169.07:56:47.20#ibcon#read 6, iclass 10, count 0 2006.169.07:56:47.20#ibcon#end of sib2, iclass 10, count 0 2006.169.07:56:47.20#ibcon#*mode == 0, iclass 10, count 0 2006.169.07:56:47.20#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.169.07:56:47.20#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.07:56:47.20#ibcon#*before write, iclass 10, count 0 2006.169.07:56:47.20#ibcon#enter sib2, iclass 10, count 0 2006.169.07:56:47.20#ibcon#flushed, iclass 10, count 0 2006.169.07:56:47.20#ibcon#about to write, iclass 10, count 0 2006.169.07:56:47.20#ibcon#wrote, iclass 10, count 0 2006.169.07:56:47.20#ibcon#about to read 3, iclass 10, count 0 2006.169.07:56:47.24#ibcon#read 3, iclass 10, count 0 2006.169.07:56:47.24#ibcon#about to read 4, iclass 10, count 0 2006.169.07:56:47.24#ibcon#read 4, iclass 10, count 0 2006.169.07:56:47.24#ibcon#about to read 5, iclass 10, count 0 2006.169.07:56:47.24#ibcon#read 5, iclass 10, count 0 2006.169.07:56:47.24#ibcon#about to read 6, iclass 10, count 0 2006.169.07:56:47.24#ibcon#read 6, iclass 10, count 0 2006.169.07:56:47.24#ibcon#end of sib2, iclass 10, count 0 2006.169.07:56:47.24#ibcon#*after write, iclass 10, count 0 2006.169.07:56:47.24#ibcon#*before return 0, iclass 10, count 0 2006.169.07:56:47.24#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.169.07:56:47.24#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.169.07:56:47.24#ibcon#about to clear, iclass 10 cls_cnt 0 2006.169.07:56:47.24#ibcon#cleared, iclass 10 cls_cnt 0 2006.169.07:56:47.24$vc4f8/va=8,7 2006.169.07:56:47.24#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.169.07:56:47.24#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.169.07:56:47.24#ibcon#ireg 11 cls_cnt 2 2006.169.07:56:47.24#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.169.07:56:47.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.169.07:56:47.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.169.07:56:47.29#ibcon#enter wrdev, iclass 12, count 2 2006.169.07:56:47.29#ibcon#first serial, iclass 12, count 2 2006.169.07:56:47.29#ibcon#enter sib2, iclass 12, count 2 2006.169.07:56:47.29#ibcon#flushed, iclass 12, count 2 2006.169.07:56:47.29#ibcon#about to write, iclass 12, count 2 2006.169.07:56:47.29#ibcon#wrote, iclass 12, count 2 2006.169.07:56:47.29#ibcon#about to read 3, iclass 12, count 2 2006.169.07:56:47.31#ibcon#read 3, iclass 12, count 2 2006.169.07:56:47.31#ibcon#about to read 4, iclass 12, count 2 2006.169.07:56:47.31#ibcon#read 4, iclass 12, count 2 2006.169.07:56:47.31#ibcon#about to read 5, iclass 12, count 2 2006.169.07:56:47.31#ibcon#read 5, iclass 12, count 2 2006.169.07:56:47.31#ibcon#about to read 6, iclass 12, count 2 2006.169.07:56:47.31#ibcon#read 6, iclass 12, count 2 2006.169.07:56:47.31#ibcon#end of sib2, iclass 12, count 2 2006.169.07:56:47.31#ibcon#*mode == 0, iclass 12, count 2 2006.169.07:56:47.31#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.169.07:56:47.31#ibcon#[25=AT08-07\r\n] 2006.169.07:56:47.31#ibcon#*before write, iclass 12, count 2 2006.169.07:56:47.31#ibcon#enter sib2, iclass 12, count 2 2006.169.07:56:47.31#ibcon#flushed, iclass 12, count 2 2006.169.07:56:47.31#ibcon#about to write, iclass 12, count 2 2006.169.07:56:47.31#ibcon#wrote, iclass 12, count 2 2006.169.07:56:47.31#ibcon#about to read 3, iclass 12, count 2 2006.169.07:56:47.34#ibcon#read 3, iclass 12, count 2 2006.169.07:56:47.34#ibcon#about to read 4, iclass 12, count 2 2006.169.07:56:47.34#ibcon#read 4, iclass 12, count 2 2006.169.07:56:47.34#ibcon#about to read 5, iclass 12, count 2 2006.169.07:56:47.34#ibcon#read 5, iclass 12, count 2 2006.169.07:56:47.34#ibcon#about to read 6, iclass 12, count 2 2006.169.07:56:47.34#ibcon#read 6, iclass 12, count 2 2006.169.07:56:47.34#ibcon#end of sib2, iclass 12, count 2 2006.169.07:56:47.34#ibcon#*after write, iclass 12, count 2 2006.169.07:56:47.34#ibcon#*before return 0, iclass 12, count 2 2006.169.07:56:47.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.169.07:56:47.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.169.07:56:47.34#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.169.07:56:47.34#ibcon#ireg 7 cls_cnt 0 2006.169.07:56:47.34#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.169.07:56:47.46#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.169.07:56:47.46#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.169.07:56:47.46#ibcon#enter wrdev, iclass 12, count 0 2006.169.07:56:47.46#ibcon#first serial, iclass 12, count 0 2006.169.07:56:47.46#ibcon#enter sib2, iclass 12, count 0 2006.169.07:56:47.46#ibcon#flushed, iclass 12, count 0 2006.169.07:56:47.46#ibcon#about to write, iclass 12, count 0 2006.169.07:56:47.46#ibcon#wrote, iclass 12, count 0 2006.169.07:56:47.46#ibcon#about to read 3, iclass 12, count 0 2006.169.07:56:47.48#ibcon#read 3, iclass 12, count 0 2006.169.07:56:47.48#ibcon#about to read 4, iclass 12, count 0 2006.169.07:56:47.48#ibcon#read 4, iclass 12, count 0 2006.169.07:56:47.48#ibcon#about to read 5, iclass 12, count 0 2006.169.07:56:47.48#ibcon#read 5, iclass 12, count 0 2006.169.07:56:47.48#ibcon#about to read 6, iclass 12, count 0 2006.169.07:56:47.48#ibcon#read 6, iclass 12, count 0 2006.169.07:56:47.48#ibcon#end of sib2, iclass 12, count 0 2006.169.07:56:47.48#ibcon#*mode == 0, iclass 12, count 0 2006.169.07:56:47.48#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.169.07:56:47.48#ibcon#[25=USB\r\n] 2006.169.07:56:47.48#ibcon#*before write, iclass 12, count 0 2006.169.07:56:47.48#ibcon#enter sib2, iclass 12, count 0 2006.169.07:56:47.48#ibcon#flushed, iclass 12, count 0 2006.169.07:56:47.48#ibcon#about to write, iclass 12, count 0 2006.169.07:56:47.48#ibcon#wrote, iclass 12, count 0 2006.169.07:56:47.48#ibcon#about to read 3, iclass 12, count 0 2006.169.07:56:47.51#ibcon#read 3, iclass 12, count 0 2006.169.07:56:47.51#ibcon#about to read 4, iclass 12, count 0 2006.169.07:56:47.51#ibcon#read 4, iclass 12, count 0 2006.169.07:56:47.51#ibcon#about to read 5, iclass 12, count 0 2006.169.07:56:47.51#ibcon#read 5, iclass 12, count 0 2006.169.07:56:47.51#ibcon#about to read 6, iclass 12, count 0 2006.169.07:56:47.51#ibcon#read 6, iclass 12, count 0 2006.169.07:56:47.51#ibcon#end of sib2, iclass 12, count 0 2006.169.07:56:47.51#ibcon#*after write, iclass 12, count 0 2006.169.07:56:47.51#ibcon#*before return 0, iclass 12, count 0 2006.169.07:56:47.51#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.169.07:56:47.51#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.169.07:56:47.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.169.07:56:47.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.169.07:56:47.51$vc4f8/vblo=1,632.99 2006.169.07:56:47.51#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.169.07:56:47.51#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.169.07:56:47.51#ibcon#ireg 17 cls_cnt 0 2006.169.07:56:47.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.169.07:56:47.51#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.169.07:56:47.51#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.169.07:56:47.51#ibcon#enter wrdev, iclass 14, count 0 2006.169.07:56:47.51#ibcon#first serial, iclass 14, count 0 2006.169.07:56:47.51#ibcon#enter sib2, iclass 14, count 0 2006.169.07:56:47.51#ibcon#flushed, iclass 14, count 0 2006.169.07:56:47.51#ibcon#about to write, iclass 14, count 0 2006.169.07:56:47.51#ibcon#wrote, iclass 14, count 0 2006.169.07:56:47.51#ibcon#about to read 3, iclass 14, count 0 2006.169.07:56:47.53#ibcon#read 3, iclass 14, count 0 2006.169.07:56:47.53#ibcon#about to read 4, iclass 14, count 0 2006.169.07:56:47.53#ibcon#read 4, iclass 14, count 0 2006.169.07:56:47.53#ibcon#about to read 5, iclass 14, count 0 2006.169.07:56:47.53#ibcon#read 5, iclass 14, count 0 2006.169.07:56:47.53#ibcon#about to read 6, iclass 14, count 0 2006.169.07:56:47.53#ibcon#read 6, iclass 14, count 0 2006.169.07:56:47.53#ibcon#end of sib2, iclass 14, count 0 2006.169.07:56:47.53#ibcon#*mode == 0, iclass 14, count 0 2006.169.07:56:47.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.169.07:56:47.53#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.07:56:47.53#ibcon#*before write, iclass 14, count 0 2006.169.07:56:47.53#ibcon#enter sib2, iclass 14, count 0 2006.169.07:56:47.53#ibcon#flushed, iclass 14, count 0 2006.169.07:56:47.53#ibcon#about to write, iclass 14, count 0 2006.169.07:56:47.53#ibcon#wrote, iclass 14, count 0 2006.169.07:56:47.53#ibcon#about to read 3, iclass 14, count 0 2006.169.07:56:47.57#ibcon#read 3, iclass 14, count 0 2006.169.07:56:47.57#ibcon#about to read 4, iclass 14, count 0 2006.169.07:56:47.57#ibcon#read 4, iclass 14, count 0 2006.169.07:56:47.57#ibcon#about to read 5, iclass 14, count 0 2006.169.07:56:47.57#ibcon#read 5, iclass 14, count 0 2006.169.07:56:47.57#ibcon#about to read 6, iclass 14, count 0 2006.169.07:56:47.57#ibcon#read 6, iclass 14, count 0 2006.169.07:56:47.57#ibcon#end of sib2, iclass 14, count 0 2006.169.07:56:47.57#ibcon#*after write, iclass 14, count 0 2006.169.07:56:47.57#ibcon#*before return 0, iclass 14, count 0 2006.169.07:56:47.57#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.169.07:56:47.57#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.169.07:56:47.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.169.07:56:47.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.169.07:56:47.57$vc4f8/vb=1,4 2006.169.07:56:47.57#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.169.07:56:47.57#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.169.07:56:47.57#ibcon#ireg 11 cls_cnt 2 2006.169.07:56:47.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.169.07:56:47.57#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.169.07:56:47.57#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.169.07:56:47.57#ibcon#enter wrdev, iclass 16, count 2 2006.169.07:56:47.57#ibcon#first serial, iclass 16, count 2 2006.169.07:56:47.57#ibcon#enter sib2, iclass 16, count 2 2006.169.07:56:47.57#ibcon#flushed, iclass 16, count 2 2006.169.07:56:47.57#ibcon#about to write, iclass 16, count 2 2006.169.07:56:47.57#ibcon#wrote, iclass 16, count 2 2006.169.07:56:47.57#ibcon#about to read 3, iclass 16, count 2 2006.169.07:56:47.59#ibcon#read 3, iclass 16, count 2 2006.169.07:56:47.59#ibcon#about to read 4, iclass 16, count 2 2006.169.07:56:47.59#ibcon#read 4, iclass 16, count 2 2006.169.07:56:47.59#ibcon#about to read 5, iclass 16, count 2 2006.169.07:56:47.59#ibcon#read 5, iclass 16, count 2 2006.169.07:56:47.59#ibcon#about to read 6, iclass 16, count 2 2006.169.07:56:47.59#ibcon#read 6, iclass 16, count 2 2006.169.07:56:47.59#ibcon#end of sib2, iclass 16, count 2 2006.169.07:56:47.59#ibcon#*mode == 0, iclass 16, count 2 2006.169.07:56:47.59#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.169.07:56:47.59#ibcon#[27=AT01-04\r\n] 2006.169.07:56:47.59#ibcon#*before write, iclass 16, count 2 2006.169.07:56:47.59#ibcon#enter sib2, iclass 16, count 2 2006.169.07:56:47.59#ibcon#flushed, iclass 16, count 2 2006.169.07:56:47.59#ibcon#about to write, iclass 16, count 2 2006.169.07:56:47.59#ibcon#wrote, iclass 16, count 2 2006.169.07:56:47.59#ibcon#about to read 3, iclass 16, count 2 2006.169.07:56:47.62#ibcon#read 3, iclass 16, count 2 2006.169.07:56:47.62#ibcon#about to read 4, iclass 16, count 2 2006.169.07:56:47.62#ibcon#read 4, iclass 16, count 2 2006.169.07:56:47.62#ibcon#about to read 5, iclass 16, count 2 2006.169.07:56:47.62#ibcon#read 5, iclass 16, count 2 2006.169.07:56:47.62#ibcon#about to read 6, iclass 16, count 2 2006.169.07:56:47.62#ibcon#read 6, iclass 16, count 2 2006.169.07:56:47.62#ibcon#end of sib2, iclass 16, count 2 2006.169.07:56:47.62#ibcon#*after write, iclass 16, count 2 2006.169.07:56:47.62#ibcon#*before return 0, iclass 16, count 2 2006.169.07:56:47.62#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.169.07:56:47.62#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.169.07:56:47.62#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.169.07:56:47.62#ibcon#ireg 7 cls_cnt 0 2006.169.07:56:47.62#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.169.07:56:47.74#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.169.07:56:47.74#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.169.07:56:47.74#ibcon#enter wrdev, iclass 16, count 0 2006.169.07:56:47.74#ibcon#first serial, iclass 16, count 0 2006.169.07:56:47.74#ibcon#enter sib2, iclass 16, count 0 2006.169.07:56:47.74#ibcon#flushed, iclass 16, count 0 2006.169.07:56:47.74#ibcon#about to write, iclass 16, count 0 2006.169.07:56:47.74#ibcon#wrote, iclass 16, count 0 2006.169.07:56:47.74#ibcon#about to read 3, iclass 16, count 0 2006.169.07:56:47.76#ibcon#read 3, iclass 16, count 0 2006.169.07:56:47.76#ibcon#about to read 4, iclass 16, count 0 2006.169.07:56:47.76#ibcon#read 4, iclass 16, count 0 2006.169.07:56:47.76#ibcon#about to read 5, iclass 16, count 0 2006.169.07:56:47.76#ibcon#read 5, iclass 16, count 0 2006.169.07:56:47.76#ibcon#about to read 6, iclass 16, count 0 2006.169.07:56:47.76#ibcon#read 6, iclass 16, count 0 2006.169.07:56:47.76#ibcon#end of sib2, iclass 16, count 0 2006.169.07:56:47.76#ibcon#*mode == 0, iclass 16, count 0 2006.169.07:56:47.76#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.169.07:56:47.76#ibcon#[27=USB\r\n] 2006.169.07:56:47.76#ibcon#*before write, iclass 16, count 0 2006.169.07:56:47.76#ibcon#enter sib2, iclass 16, count 0 2006.169.07:56:47.76#ibcon#flushed, iclass 16, count 0 2006.169.07:56:47.76#ibcon#about to write, iclass 16, count 0 2006.169.07:56:47.76#ibcon#wrote, iclass 16, count 0 2006.169.07:56:47.76#ibcon#about to read 3, iclass 16, count 0 2006.169.07:56:47.79#ibcon#read 3, iclass 16, count 0 2006.169.07:56:47.79#ibcon#about to read 4, iclass 16, count 0 2006.169.07:56:47.79#ibcon#read 4, iclass 16, count 0 2006.169.07:56:47.79#ibcon#about to read 5, iclass 16, count 0 2006.169.07:56:47.79#ibcon#read 5, iclass 16, count 0 2006.169.07:56:47.79#ibcon#about to read 6, iclass 16, count 0 2006.169.07:56:47.79#ibcon#read 6, iclass 16, count 0 2006.169.07:56:47.79#ibcon#end of sib2, iclass 16, count 0 2006.169.07:56:47.79#ibcon#*after write, iclass 16, count 0 2006.169.07:56:47.79#ibcon#*before return 0, iclass 16, count 0 2006.169.07:56:47.79#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.169.07:56:47.79#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.169.07:56:47.79#ibcon#about to clear, iclass 16 cls_cnt 0 2006.169.07:56:47.79#ibcon#cleared, iclass 16 cls_cnt 0 2006.169.07:56:47.79$vc4f8/vblo=2,640.99 2006.169.07:56:47.79#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.169.07:56:47.79#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.169.07:56:47.79#ibcon#ireg 17 cls_cnt 0 2006.169.07:56:47.79#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:56:47.79#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:56:47.79#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:56:47.79#ibcon#enter wrdev, iclass 18, count 0 2006.169.07:56:47.79#ibcon#first serial, iclass 18, count 0 2006.169.07:56:47.79#ibcon#enter sib2, iclass 18, count 0 2006.169.07:56:47.79#ibcon#flushed, iclass 18, count 0 2006.169.07:56:47.79#ibcon#about to write, iclass 18, count 0 2006.169.07:56:47.79#ibcon#wrote, iclass 18, count 0 2006.169.07:56:47.79#ibcon#about to read 3, iclass 18, count 0 2006.169.07:56:47.81#ibcon#read 3, iclass 18, count 0 2006.169.07:56:47.81#ibcon#about to read 4, iclass 18, count 0 2006.169.07:56:47.81#ibcon#read 4, iclass 18, count 0 2006.169.07:56:47.81#ibcon#about to read 5, iclass 18, count 0 2006.169.07:56:47.81#ibcon#read 5, iclass 18, count 0 2006.169.07:56:47.81#ibcon#about to read 6, iclass 18, count 0 2006.169.07:56:47.81#ibcon#read 6, iclass 18, count 0 2006.169.07:56:47.81#ibcon#end of sib2, iclass 18, count 0 2006.169.07:56:47.81#ibcon#*mode == 0, iclass 18, count 0 2006.169.07:56:47.81#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.169.07:56:47.81#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.07:56:47.81#ibcon#*before write, iclass 18, count 0 2006.169.07:56:47.81#ibcon#enter sib2, iclass 18, count 0 2006.169.07:56:47.81#ibcon#flushed, iclass 18, count 0 2006.169.07:56:47.81#ibcon#about to write, iclass 18, count 0 2006.169.07:56:47.81#ibcon#wrote, iclass 18, count 0 2006.169.07:56:47.81#ibcon#about to read 3, iclass 18, count 0 2006.169.07:56:47.85#ibcon#read 3, iclass 18, count 0 2006.169.07:56:47.85#ibcon#about to read 4, iclass 18, count 0 2006.169.07:56:47.85#ibcon#read 4, iclass 18, count 0 2006.169.07:56:47.85#ibcon#about to read 5, iclass 18, count 0 2006.169.07:56:47.85#ibcon#read 5, iclass 18, count 0 2006.169.07:56:47.85#ibcon#about to read 6, iclass 18, count 0 2006.169.07:56:47.85#ibcon#read 6, iclass 18, count 0 2006.169.07:56:47.85#ibcon#end of sib2, iclass 18, count 0 2006.169.07:56:47.85#ibcon#*after write, iclass 18, count 0 2006.169.07:56:47.85#ibcon#*before return 0, iclass 18, count 0 2006.169.07:56:47.85#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:56:47.85#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.169.07:56:47.85#ibcon#about to clear, iclass 18 cls_cnt 0 2006.169.07:56:47.85#ibcon#cleared, iclass 18 cls_cnt 0 2006.169.07:56:47.85$vc4f8/vb=2,4 2006.169.07:56:47.85#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.169.07:56:47.85#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.169.07:56:47.85#ibcon#ireg 11 cls_cnt 2 2006.169.07:56:47.85#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.169.07:56:47.91#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.169.07:56:47.91#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.169.07:56:47.91#ibcon#enter wrdev, iclass 20, count 2 2006.169.07:56:47.91#ibcon#first serial, iclass 20, count 2 2006.169.07:56:47.91#ibcon#enter sib2, iclass 20, count 2 2006.169.07:56:47.91#ibcon#flushed, iclass 20, count 2 2006.169.07:56:47.91#ibcon#about to write, iclass 20, count 2 2006.169.07:56:47.91#ibcon#wrote, iclass 20, count 2 2006.169.07:56:47.91#ibcon#about to read 3, iclass 20, count 2 2006.169.07:56:47.93#ibcon#read 3, iclass 20, count 2 2006.169.07:56:47.93#ibcon#about to read 4, iclass 20, count 2 2006.169.07:56:47.93#ibcon#read 4, iclass 20, count 2 2006.169.07:56:47.93#ibcon#about to read 5, iclass 20, count 2 2006.169.07:56:47.93#ibcon#read 5, iclass 20, count 2 2006.169.07:56:47.93#ibcon#about to read 6, iclass 20, count 2 2006.169.07:56:47.93#ibcon#read 6, iclass 20, count 2 2006.169.07:56:47.93#ibcon#end of sib2, iclass 20, count 2 2006.169.07:56:47.93#ibcon#*mode == 0, iclass 20, count 2 2006.169.07:56:47.93#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.169.07:56:47.93#ibcon#[27=AT02-04\r\n] 2006.169.07:56:47.93#ibcon#*before write, iclass 20, count 2 2006.169.07:56:47.93#ibcon#enter sib2, iclass 20, count 2 2006.169.07:56:47.93#ibcon#flushed, iclass 20, count 2 2006.169.07:56:47.93#ibcon#about to write, iclass 20, count 2 2006.169.07:56:47.93#ibcon#wrote, iclass 20, count 2 2006.169.07:56:47.93#ibcon#about to read 3, iclass 20, count 2 2006.169.07:56:47.96#ibcon#read 3, iclass 20, count 2 2006.169.07:56:47.96#ibcon#about to read 4, iclass 20, count 2 2006.169.07:56:47.96#ibcon#read 4, iclass 20, count 2 2006.169.07:56:47.96#ibcon#about to read 5, iclass 20, count 2 2006.169.07:56:47.96#ibcon#read 5, iclass 20, count 2 2006.169.07:56:47.96#ibcon#about to read 6, iclass 20, count 2 2006.169.07:56:47.96#ibcon#read 6, iclass 20, count 2 2006.169.07:56:47.96#ibcon#end of sib2, iclass 20, count 2 2006.169.07:56:47.96#ibcon#*after write, iclass 20, count 2 2006.169.07:56:47.96#ibcon#*before return 0, iclass 20, count 2 2006.169.07:56:47.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.169.07:56:47.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.169.07:56:47.96#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.169.07:56:47.96#ibcon#ireg 7 cls_cnt 0 2006.169.07:56:47.96#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.169.07:56:48.08#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.169.07:56:48.08#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.169.07:56:48.08#ibcon#enter wrdev, iclass 20, count 0 2006.169.07:56:48.08#ibcon#first serial, iclass 20, count 0 2006.169.07:56:48.08#ibcon#enter sib2, iclass 20, count 0 2006.169.07:56:48.08#ibcon#flushed, iclass 20, count 0 2006.169.07:56:48.08#ibcon#about to write, iclass 20, count 0 2006.169.07:56:48.08#ibcon#wrote, iclass 20, count 0 2006.169.07:56:48.08#ibcon#about to read 3, iclass 20, count 0 2006.169.07:56:48.10#ibcon#read 3, iclass 20, count 0 2006.169.07:56:48.10#ibcon#about to read 4, iclass 20, count 0 2006.169.07:56:48.10#ibcon#read 4, iclass 20, count 0 2006.169.07:56:48.10#ibcon#about to read 5, iclass 20, count 0 2006.169.07:56:48.10#ibcon#read 5, iclass 20, count 0 2006.169.07:56:48.10#ibcon#about to read 6, iclass 20, count 0 2006.169.07:56:48.10#ibcon#read 6, iclass 20, count 0 2006.169.07:56:48.10#ibcon#end of sib2, iclass 20, count 0 2006.169.07:56:48.10#ibcon#*mode == 0, iclass 20, count 0 2006.169.07:56:48.10#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.169.07:56:48.10#ibcon#[27=USB\r\n] 2006.169.07:56:48.10#ibcon#*before write, iclass 20, count 0 2006.169.07:56:48.10#ibcon#enter sib2, iclass 20, count 0 2006.169.07:56:48.10#ibcon#flushed, iclass 20, count 0 2006.169.07:56:48.10#ibcon#about to write, iclass 20, count 0 2006.169.07:56:48.10#ibcon#wrote, iclass 20, count 0 2006.169.07:56:48.10#ibcon#about to read 3, iclass 20, count 0 2006.169.07:56:48.13#ibcon#read 3, iclass 20, count 0 2006.169.07:56:48.13#ibcon#about to read 4, iclass 20, count 0 2006.169.07:56:48.13#ibcon#read 4, iclass 20, count 0 2006.169.07:56:48.13#ibcon#about to read 5, iclass 20, count 0 2006.169.07:56:48.13#ibcon#read 5, iclass 20, count 0 2006.169.07:56:48.13#ibcon#about to read 6, iclass 20, count 0 2006.169.07:56:48.13#ibcon#read 6, iclass 20, count 0 2006.169.07:56:48.13#ibcon#end of sib2, iclass 20, count 0 2006.169.07:56:48.13#ibcon#*after write, iclass 20, count 0 2006.169.07:56:48.13#ibcon#*before return 0, iclass 20, count 0 2006.169.07:56:48.13#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.169.07:56:48.13#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.169.07:56:48.13#ibcon#about to clear, iclass 20 cls_cnt 0 2006.169.07:56:48.13#ibcon#cleared, iclass 20 cls_cnt 0 2006.169.07:56:48.13$vc4f8/vblo=3,656.99 2006.169.07:56:48.13#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.169.07:56:48.13#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.169.07:56:48.13#ibcon#ireg 17 cls_cnt 0 2006.169.07:56:48.13#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:56:48.13#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:56:48.13#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:56:48.13#ibcon#enter wrdev, iclass 22, count 0 2006.169.07:56:48.13#ibcon#first serial, iclass 22, count 0 2006.169.07:56:48.13#ibcon#enter sib2, iclass 22, count 0 2006.169.07:56:48.13#ibcon#flushed, iclass 22, count 0 2006.169.07:56:48.13#ibcon#about to write, iclass 22, count 0 2006.169.07:56:48.13#ibcon#wrote, iclass 22, count 0 2006.169.07:56:48.13#ibcon#about to read 3, iclass 22, count 0 2006.169.07:56:48.15#ibcon#read 3, iclass 22, count 0 2006.169.07:56:48.15#ibcon#about to read 4, iclass 22, count 0 2006.169.07:56:48.15#ibcon#read 4, iclass 22, count 0 2006.169.07:56:48.15#ibcon#about to read 5, iclass 22, count 0 2006.169.07:56:48.15#ibcon#read 5, iclass 22, count 0 2006.169.07:56:48.15#ibcon#about to read 6, iclass 22, count 0 2006.169.07:56:48.15#ibcon#read 6, iclass 22, count 0 2006.169.07:56:48.15#ibcon#end of sib2, iclass 22, count 0 2006.169.07:56:48.15#ibcon#*mode == 0, iclass 22, count 0 2006.169.07:56:48.15#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.169.07:56:48.15#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.07:56:48.15#ibcon#*before write, iclass 22, count 0 2006.169.07:56:48.15#ibcon#enter sib2, iclass 22, count 0 2006.169.07:56:48.15#ibcon#flushed, iclass 22, count 0 2006.169.07:56:48.15#ibcon#about to write, iclass 22, count 0 2006.169.07:56:48.15#ibcon#wrote, iclass 22, count 0 2006.169.07:56:48.15#ibcon#about to read 3, iclass 22, count 0 2006.169.07:56:48.19#ibcon#read 3, iclass 22, count 0 2006.169.07:56:48.19#ibcon#about to read 4, iclass 22, count 0 2006.169.07:56:48.19#ibcon#read 4, iclass 22, count 0 2006.169.07:56:48.19#ibcon#about to read 5, iclass 22, count 0 2006.169.07:56:48.19#ibcon#read 5, iclass 22, count 0 2006.169.07:56:48.19#ibcon#about to read 6, iclass 22, count 0 2006.169.07:56:48.19#ibcon#read 6, iclass 22, count 0 2006.169.07:56:48.19#ibcon#end of sib2, iclass 22, count 0 2006.169.07:56:48.19#ibcon#*after write, iclass 22, count 0 2006.169.07:56:48.19#ibcon#*before return 0, iclass 22, count 0 2006.169.07:56:48.19#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:56:48.19#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.169.07:56:48.19#ibcon#about to clear, iclass 22 cls_cnt 0 2006.169.07:56:48.19#ibcon#cleared, iclass 22 cls_cnt 0 2006.169.07:56:48.19$vc4f8/vb=3,4 2006.169.07:56:48.19#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.169.07:56:48.19#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.169.07:56:48.19#ibcon#ireg 11 cls_cnt 2 2006.169.07:56:48.19#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.169.07:56:48.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.169.07:56:48.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.169.07:56:48.25#ibcon#enter wrdev, iclass 24, count 2 2006.169.07:56:48.25#ibcon#first serial, iclass 24, count 2 2006.169.07:56:48.25#ibcon#enter sib2, iclass 24, count 2 2006.169.07:56:48.25#ibcon#flushed, iclass 24, count 2 2006.169.07:56:48.25#ibcon#about to write, iclass 24, count 2 2006.169.07:56:48.25#ibcon#wrote, iclass 24, count 2 2006.169.07:56:48.25#ibcon#about to read 3, iclass 24, count 2 2006.169.07:56:48.27#ibcon#read 3, iclass 24, count 2 2006.169.07:56:48.27#ibcon#about to read 4, iclass 24, count 2 2006.169.07:56:48.27#ibcon#read 4, iclass 24, count 2 2006.169.07:56:48.27#ibcon#about to read 5, iclass 24, count 2 2006.169.07:56:48.27#ibcon#read 5, iclass 24, count 2 2006.169.07:56:48.27#ibcon#about to read 6, iclass 24, count 2 2006.169.07:56:48.27#ibcon#read 6, iclass 24, count 2 2006.169.07:56:48.27#ibcon#end of sib2, iclass 24, count 2 2006.169.07:56:48.27#ibcon#*mode == 0, iclass 24, count 2 2006.169.07:56:48.27#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.169.07:56:48.27#ibcon#[27=AT03-04\r\n] 2006.169.07:56:48.27#ibcon#*before write, iclass 24, count 2 2006.169.07:56:48.27#ibcon#enter sib2, iclass 24, count 2 2006.169.07:56:48.27#ibcon#flushed, iclass 24, count 2 2006.169.07:56:48.27#ibcon#about to write, iclass 24, count 2 2006.169.07:56:48.27#ibcon#wrote, iclass 24, count 2 2006.169.07:56:48.27#ibcon#about to read 3, iclass 24, count 2 2006.169.07:56:48.30#ibcon#read 3, iclass 24, count 2 2006.169.07:56:48.30#ibcon#about to read 4, iclass 24, count 2 2006.169.07:56:48.30#ibcon#read 4, iclass 24, count 2 2006.169.07:56:48.30#ibcon#about to read 5, iclass 24, count 2 2006.169.07:56:48.30#ibcon#read 5, iclass 24, count 2 2006.169.07:56:48.30#ibcon#about to read 6, iclass 24, count 2 2006.169.07:56:48.30#ibcon#read 6, iclass 24, count 2 2006.169.07:56:48.30#ibcon#end of sib2, iclass 24, count 2 2006.169.07:56:48.30#ibcon#*after write, iclass 24, count 2 2006.169.07:56:48.30#ibcon#*before return 0, iclass 24, count 2 2006.169.07:56:48.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.169.07:56:48.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.169.07:56:48.30#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.169.07:56:48.30#ibcon#ireg 7 cls_cnt 0 2006.169.07:56:48.30#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.169.07:56:48.42#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.169.07:56:48.42#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.169.07:56:48.42#ibcon#enter wrdev, iclass 24, count 0 2006.169.07:56:48.42#ibcon#first serial, iclass 24, count 0 2006.169.07:56:48.42#ibcon#enter sib2, iclass 24, count 0 2006.169.07:56:48.42#ibcon#flushed, iclass 24, count 0 2006.169.07:56:48.42#ibcon#about to write, iclass 24, count 0 2006.169.07:56:48.42#ibcon#wrote, iclass 24, count 0 2006.169.07:56:48.42#ibcon#about to read 3, iclass 24, count 0 2006.169.07:56:48.44#ibcon#read 3, iclass 24, count 0 2006.169.07:56:48.44#ibcon#about to read 4, iclass 24, count 0 2006.169.07:56:48.44#ibcon#read 4, iclass 24, count 0 2006.169.07:56:48.44#ibcon#about to read 5, iclass 24, count 0 2006.169.07:56:48.44#ibcon#read 5, iclass 24, count 0 2006.169.07:56:48.44#ibcon#about to read 6, iclass 24, count 0 2006.169.07:56:48.44#ibcon#read 6, iclass 24, count 0 2006.169.07:56:48.44#ibcon#end of sib2, iclass 24, count 0 2006.169.07:56:48.44#ibcon#*mode == 0, iclass 24, count 0 2006.169.07:56:48.44#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.169.07:56:48.44#ibcon#[27=USB\r\n] 2006.169.07:56:48.44#ibcon#*before write, iclass 24, count 0 2006.169.07:56:48.44#ibcon#enter sib2, iclass 24, count 0 2006.169.07:56:48.44#ibcon#flushed, iclass 24, count 0 2006.169.07:56:48.44#ibcon#about to write, iclass 24, count 0 2006.169.07:56:48.44#ibcon#wrote, iclass 24, count 0 2006.169.07:56:48.44#ibcon#about to read 3, iclass 24, count 0 2006.169.07:56:48.47#ibcon#read 3, iclass 24, count 0 2006.169.07:56:48.47#ibcon#about to read 4, iclass 24, count 0 2006.169.07:56:48.47#ibcon#read 4, iclass 24, count 0 2006.169.07:56:48.47#ibcon#about to read 5, iclass 24, count 0 2006.169.07:56:48.47#ibcon#read 5, iclass 24, count 0 2006.169.07:56:48.47#ibcon#about to read 6, iclass 24, count 0 2006.169.07:56:48.47#ibcon#read 6, iclass 24, count 0 2006.169.07:56:48.47#ibcon#end of sib2, iclass 24, count 0 2006.169.07:56:48.47#ibcon#*after write, iclass 24, count 0 2006.169.07:56:48.47#ibcon#*before return 0, iclass 24, count 0 2006.169.07:56:48.47#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.169.07:56:48.47#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.169.07:56:48.47#ibcon#about to clear, iclass 24 cls_cnt 0 2006.169.07:56:48.47#ibcon#cleared, iclass 24 cls_cnt 0 2006.169.07:56:48.47$vc4f8/vblo=4,712.99 2006.169.07:56:48.47#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.169.07:56:48.47#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.169.07:56:48.47#ibcon#ireg 17 cls_cnt 0 2006.169.07:56:48.47#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:56:48.47#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:56:48.47#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:56:48.47#ibcon#enter wrdev, iclass 26, count 0 2006.169.07:56:48.47#ibcon#first serial, iclass 26, count 0 2006.169.07:56:48.47#ibcon#enter sib2, iclass 26, count 0 2006.169.07:56:48.47#ibcon#flushed, iclass 26, count 0 2006.169.07:56:48.47#ibcon#about to write, iclass 26, count 0 2006.169.07:56:48.47#ibcon#wrote, iclass 26, count 0 2006.169.07:56:48.47#ibcon#about to read 3, iclass 26, count 0 2006.169.07:56:48.49#ibcon#read 3, iclass 26, count 0 2006.169.07:56:48.49#ibcon#about to read 4, iclass 26, count 0 2006.169.07:56:48.49#ibcon#read 4, iclass 26, count 0 2006.169.07:56:48.49#ibcon#about to read 5, iclass 26, count 0 2006.169.07:56:48.49#ibcon#read 5, iclass 26, count 0 2006.169.07:56:48.49#ibcon#about to read 6, iclass 26, count 0 2006.169.07:56:48.49#ibcon#read 6, iclass 26, count 0 2006.169.07:56:48.49#ibcon#end of sib2, iclass 26, count 0 2006.169.07:56:48.49#ibcon#*mode == 0, iclass 26, count 0 2006.169.07:56:48.49#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.169.07:56:48.49#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.07:56:48.49#ibcon#*before write, iclass 26, count 0 2006.169.07:56:48.49#ibcon#enter sib2, iclass 26, count 0 2006.169.07:56:48.49#ibcon#flushed, iclass 26, count 0 2006.169.07:56:48.49#ibcon#about to write, iclass 26, count 0 2006.169.07:56:48.49#ibcon#wrote, iclass 26, count 0 2006.169.07:56:48.49#ibcon#about to read 3, iclass 26, count 0 2006.169.07:56:48.53#ibcon#read 3, iclass 26, count 0 2006.169.07:56:48.53#ibcon#about to read 4, iclass 26, count 0 2006.169.07:56:48.53#ibcon#read 4, iclass 26, count 0 2006.169.07:56:48.53#ibcon#about to read 5, iclass 26, count 0 2006.169.07:56:48.53#ibcon#read 5, iclass 26, count 0 2006.169.07:56:48.53#ibcon#about to read 6, iclass 26, count 0 2006.169.07:56:48.53#ibcon#read 6, iclass 26, count 0 2006.169.07:56:48.53#ibcon#end of sib2, iclass 26, count 0 2006.169.07:56:48.53#ibcon#*after write, iclass 26, count 0 2006.169.07:56:48.53#ibcon#*before return 0, iclass 26, count 0 2006.169.07:56:48.53#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:56:48.53#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.169.07:56:48.53#ibcon#about to clear, iclass 26 cls_cnt 0 2006.169.07:56:48.53#ibcon#cleared, iclass 26 cls_cnt 0 2006.169.07:56:48.53$vc4f8/vb=4,4 2006.169.07:56:48.53#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.169.07:56:48.53#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.169.07:56:48.53#ibcon#ireg 11 cls_cnt 2 2006.169.07:56:48.53#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.169.07:56:48.59#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.169.07:56:48.59#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.169.07:56:48.59#ibcon#enter wrdev, iclass 28, count 2 2006.169.07:56:48.59#ibcon#first serial, iclass 28, count 2 2006.169.07:56:48.59#ibcon#enter sib2, iclass 28, count 2 2006.169.07:56:48.59#ibcon#flushed, iclass 28, count 2 2006.169.07:56:48.59#ibcon#about to write, iclass 28, count 2 2006.169.07:56:48.59#ibcon#wrote, iclass 28, count 2 2006.169.07:56:48.59#ibcon#about to read 3, iclass 28, count 2 2006.169.07:56:48.61#ibcon#read 3, iclass 28, count 2 2006.169.07:56:48.61#ibcon#about to read 4, iclass 28, count 2 2006.169.07:56:48.61#ibcon#read 4, iclass 28, count 2 2006.169.07:56:48.61#ibcon#about to read 5, iclass 28, count 2 2006.169.07:56:48.61#ibcon#read 5, iclass 28, count 2 2006.169.07:56:48.61#ibcon#about to read 6, iclass 28, count 2 2006.169.07:56:48.61#ibcon#read 6, iclass 28, count 2 2006.169.07:56:48.61#ibcon#end of sib2, iclass 28, count 2 2006.169.07:56:48.61#ibcon#*mode == 0, iclass 28, count 2 2006.169.07:56:48.61#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.169.07:56:48.61#ibcon#[27=AT04-04\r\n] 2006.169.07:56:48.61#ibcon#*before write, iclass 28, count 2 2006.169.07:56:48.61#ibcon#enter sib2, iclass 28, count 2 2006.169.07:56:48.61#ibcon#flushed, iclass 28, count 2 2006.169.07:56:48.61#ibcon#about to write, iclass 28, count 2 2006.169.07:56:48.61#ibcon#wrote, iclass 28, count 2 2006.169.07:56:48.61#ibcon#about to read 3, iclass 28, count 2 2006.169.07:56:48.64#ibcon#read 3, iclass 28, count 2 2006.169.07:56:48.64#ibcon#about to read 4, iclass 28, count 2 2006.169.07:56:48.64#ibcon#read 4, iclass 28, count 2 2006.169.07:56:48.64#ibcon#about to read 5, iclass 28, count 2 2006.169.07:56:48.64#ibcon#read 5, iclass 28, count 2 2006.169.07:56:48.64#ibcon#about to read 6, iclass 28, count 2 2006.169.07:56:48.64#ibcon#read 6, iclass 28, count 2 2006.169.07:56:48.64#ibcon#end of sib2, iclass 28, count 2 2006.169.07:56:48.64#ibcon#*after write, iclass 28, count 2 2006.169.07:56:48.64#ibcon#*before return 0, iclass 28, count 2 2006.169.07:56:48.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.169.07:56:48.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.169.07:56:48.64#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.169.07:56:48.64#ibcon#ireg 7 cls_cnt 0 2006.169.07:56:48.64#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.169.07:56:48.76#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.169.07:56:48.76#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.169.07:56:48.76#ibcon#enter wrdev, iclass 28, count 0 2006.169.07:56:48.76#ibcon#first serial, iclass 28, count 0 2006.169.07:56:48.76#ibcon#enter sib2, iclass 28, count 0 2006.169.07:56:48.76#ibcon#flushed, iclass 28, count 0 2006.169.07:56:48.76#ibcon#about to write, iclass 28, count 0 2006.169.07:56:48.76#ibcon#wrote, iclass 28, count 0 2006.169.07:56:48.76#ibcon#about to read 3, iclass 28, count 0 2006.169.07:56:48.78#ibcon#read 3, iclass 28, count 0 2006.169.07:56:48.78#ibcon#about to read 4, iclass 28, count 0 2006.169.07:56:48.78#ibcon#read 4, iclass 28, count 0 2006.169.07:56:48.78#ibcon#about to read 5, iclass 28, count 0 2006.169.07:56:48.78#ibcon#read 5, iclass 28, count 0 2006.169.07:56:48.78#ibcon#about to read 6, iclass 28, count 0 2006.169.07:56:48.78#ibcon#read 6, iclass 28, count 0 2006.169.07:56:48.78#ibcon#end of sib2, iclass 28, count 0 2006.169.07:56:48.78#ibcon#*mode == 0, iclass 28, count 0 2006.169.07:56:48.78#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.169.07:56:48.78#ibcon#[27=USB\r\n] 2006.169.07:56:48.78#ibcon#*before write, iclass 28, count 0 2006.169.07:56:48.78#ibcon#enter sib2, iclass 28, count 0 2006.169.07:56:48.78#ibcon#flushed, iclass 28, count 0 2006.169.07:56:48.78#ibcon#about to write, iclass 28, count 0 2006.169.07:56:48.78#ibcon#wrote, iclass 28, count 0 2006.169.07:56:48.78#ibcon#about to read 3, iclass 28, count 0 2006.169.07:56:48.81#ibcon#read 3, iclass 28, count 0 2006.169.07:56:48.81#ibcon#about to read 4, iclass 28, count 0 2006.169.07:56:48.81#ibcon#read 4, iclass 28, count 0 2006.169.07:56:48.81#ibcon#about to read 5, iclass 28, count 0 2006.169.07:56:48.81#ibcon#read 5, iclass 28, count 0 2006.169.07:56:48.81#ibcon#about to read 6, iclass 28, count 0 2006.169.07:56:48.81#ibcon#read 6, iclass 28, count 0 2006.169.07:56:48.81#ibcon#end of sib2, iclass 28, count 0 2006.169.07:56:48.81#ibcon#*after write, iclass 28, count 0 2006.169.07:56:48.81#ibcon#*before return 0, iclass 28, count 0 2006.169.07:56:48.81#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.169.07:56:48.81#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.169.07:56:48.81#ibcon#about to clear, iclass 28 cls_cnt 0 2006.169.07:56:48.81#ibcon#cleared, iclass 28 cls_cnt 0 2006.169.07:56:48.81$vc4f8/vblo=5,744.99 2006.169.07:56:48.81#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.169.07:56:48.81#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.169.07:56:48.81#ibcon#ireg 17 cls_cnt 0 2006.169.07:56:48.81#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:56:48.81#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:56:48.81#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:56:48.81#ibcon#enter wrdev, iclass 30, count 0 2006.169.07:56:48.81#ibcon#first serial, iclass 30, count 0 2006.169.07:56:48.81#ibcon#enter sib2, iclass 30, count 0 2006.169.07:56:48.81#ibcon#flushed, iclass 30, count 0 2006.169.07:56:48.81#ibcon#about to write, iclass 30, count 0 2006.169.07:56:48.81#ibcon#wrote, iclass 30, count 0 2006.169.07:56:48.81#ibcon#about to read 3, iclass 30, count 0 2006.169.07:56:48.83#ibcon#read 3, iclass 30, count 0 2006.169.07:56:48.83#ibcon#about to read 4, iclass 30, count 0 2006.169.07:56:48.83#ibcon#read 4, iclass 30, count 0 2006.169.07:56:48.83#ibcon#about to read 5, iclass 30, count 0 2006.169.07:56:48.83#ibcon#read 5, iclass 30, count 0 2006.169.07:56:48.83#ibcon#about to read 6, iclass 30, count 0 2006.169.07:56:48.83#ibcon#read 6, iclass 30, count 0 2006.169.07:56:48.83#ibcon#end of sib2, iclass 30, count 0 2006.169.07:56:48.83#ibcon#*mode == 0, iclass 30, count 0 2006.169.07:56:48.83#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.169.07:56:48.83#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.07:56:48.83#ibcon#*before write, iclass 30, count 0 2006.169.07:56:48.83#ibcon#enter sib2, iclass 30, count 0 2006.169.07:56:48.83#ibcon#flushed, iclass 30, count 0 2006.169.07:56:48.83#ibcon#about to write, iclass 30, count 0 2006.169.07:56:48.83#ibcon#wrote, iclass 30, count 0 2006.169.07:56:48.83#ibcon#about to read 3, iclass 30, count 0 2006.169.07:56:48.87#ibcon#read 3, iclass 30, count 0 2006.169.07:56:48.87#ibcon#about to read 4, iclass 30, count 0 2006.169.07:56:48.87#ibcon#read 4, iclass 30, count 0 2006.169.07:56:48.87#ibcon#about to read 5, iclass 30, count 0 2006.169.07:56:48.87#ibcon#read 5, iclass 30, count 0 2006.169.07:56:48.87#ibcon#about to read 6, iclass 30, count 0 2006.169.07:56:48.87#ibcon#read 6, iclass 30, count 0 2006.169.07:56:48.87#ibcon#end of sib2, iclass 30, count 0 2006.169.07:56:48.87#ibcon#*after write, iclass 30, count 0 2006.169.07:56:48.87#ibcon#*before return 0, iclass 30, count 0 2006.169.07:56:48.87#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:56:48.87#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.169.07:56:48.87#ibcon#about to clear, iclass 30 cls_cnt 0 2006.169.07:56:48.87#ibcon#cleared, iclass 30 cls_cnt 0 2006.169.07:56:48.87$vc4f8/vb=5,4 2006.169.07:56:48.87#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.169.07:56:48.87#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.169.07:56:48.87#ibcon#ireg 11 cls_cnt 2 2006.169.07:56:48.87#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:56:48.93#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:56:48.93#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:56:48.93#ibcon#enter wrdev, iclass 32, count 2 2006.169.07:56:48.93#ibcon#first serial, iclass 32, count 2 2006.169.07:56:48.93#ibcon#enter sib2, iclass 32, count 2 2006.169.07:56:48.93#ibcon#flushed, iclass 32, count 2 2006.169.07:56:48.93#ibcon#about to write, iclass 32, count 2 2006.169.07:56:48.93#ibcon#wrote, iclass 32, count 2 2006.169.07:56:48.93#ibcon#about to read 3, iclass 32, count 2 2006.169.07:56:48.95#ibcon#read 3, iclass 32, count 2 2006.169.07:56:48.95#ibcon#about to read 4, iclass 32, count 2 2006.169.07:56:48.95#ibcon#read 4, iclass 32, count 2 2006.169.07:56:48.95#ibcon#about to read 5, iclass 32, count 2 2006.169.07:56:48.95#ibcon#read 5, iclass 32, count 2 2006.169.07:56:48.95#ibcon#about to read 6, iclass 32, count 2 2006.169.07:56:48.95#ibcon#read 6, iclass 32, count 2 2006.169.07:56:48.95#ibcon#end of sib2, iclass 32, count 2 2006.169.07:56:48.95#ibcon#*mode == 0, iclass 32, count 2 2006.169.07:56:48.95#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.169.07:56:48.95#ibcon#[27=AT05-04\r\n] 2006.169.07:56:48.95#ibcon#*before write, iclass 32, count 2 2006.169.07:56:48.95#ibcon#enter sib2, iclass 32, count 2 2006.169.07:56:48.95#ibcon#flushed, iclass 32, count 2 2006.169.07:56:48.95#ibcon#about to write, iclass 32, count 2 2006.169.07:56:48.95#ibcon#wrote, iclass 32, count 2 2006.169.07:56:48.95#ibcon#about to read 3, iclass 32, count 2 2006.169.07:56:48.98#ibcon#read 3, iclass 32, count 2 2006.169.07:56:48.98#ibcon#about to read 4, iclass 32, count 2 2006.169.07:56:48.98#ibcon#read 4, iclass 32, count 2 2006.169.07:56:48.98#ibcon#about to read 5, iclass 32, count 2 2006.169.07:56:48.98#ibcon#read 5, iclass 32, count 2 2006.169.07:56:48.98#ibcon#about to read 6, iclass 32, count 2 2006.169.07:56:48.98#ibcon#read 6, iclass 32, count 2 2006.169.07:56:48.98#ibcon#end of sib2, iclass 32, count 2 2006.169.07:56:48.98#ibcon#*after write, iclass 32, count 2 2006.169.07:56:48.98#ibcon#*before return 0, iclass 32, count 2 2006.169.07:56:48.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:56:48.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.169.07:56:48.98#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.169.07:56:48.98#ibcon#ireg 7 cls_cnt 0 2006.169.07:56:48.98#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:56:49.10#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:56:49.10#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:56:49.10#ibcon#enter wrdev, iclass 32, count 0 2006.169.07:56:49.10#ibcon#first serial, iclass 32, count 0 2006.169.07:56:49.10#ibcon#enter sib2, iclass 32, count 0 2006.169.07:56:49.10#ibcon#flushed, iclass 32, count 0 2006.169.07:56:49.10#ibcon#about to write, iclass 32, count 0 2006.169.07:56:49.10#ibcon#wrote, iclass 32, count 0 2006.169.07:56:49.10#ibcon#about to read 3, iclass 32, count 0 2006.169.07:56:49.12#ibcon#read 3, iclass 32, count 0 2006.169.07:56:49.12#ibcon#about to read 4, iclass 32, count 0 2006.169.07:56:49.12#ibcon#read 4, iclass 32, count 0 2006.169.07:56:49.12#ibcon#about to read 5, iclass 32, count 0 2006.169.07:56:49.12#ibcon#read 5, iclass 32, count 0 2006.169.07:56:49.12#ibcon#about to read 6, iclass 32, count 0 2006.169.07:56:49.12#ibcon#read 6, iclass 32, count 0 2006.169.07:56:49.12#ibcon#end of sib2, iclass 32, count 0 2006.169.07:56:49.12#ibcon#*mode == 0, iclass 32, count 0 2006.169.07:56:49.12#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.169.07:56:49.12#ibcon#[27=USB\r\n] 2006.169.07:56:49.12#ibcon#*before write, iclass 32, count 0 2006.169.07:56:49.12#ibcon#enter sib2, iclass 32, count 0 2006.169.07:56:49.12#ibcon#flushed, iclass 32, count 0 2006.169.07:56:49.12#ibcon#about to write, iclass 32, count 0 2006.169.07:56:49.12#ibcon#wrote, iclass 32, count 0 2006.169.07:56:49.12#ibcon#about to read 3, iclass 32, count 0 2006.169.07:56:49.15#ibcon#read 3, iclass 32, count 0 2006.169.07:56:49.15#ibcon#about to read 4, iclass 32, count 0 2006.169.07:56:49.15#ibcon#read 4, iclass 32, count 0 2006.169.07:56:49.15#ibcon#about to read 5, iclass 32, count 0 2006.169.07:56:49.15#ibcon#read 5, iclass 32, count 0 2006.169.07:56:49.15#ibcon#about to read 6, iclass 32, count 0 2006.169.07:56:49.15#ibcon#read 6, iclass 32, count 0 2006.169.07:56:49.15#ibcon#end of sib2, iclass 32, count 0 2006.169.07:56:49.15#ibcon#*after write, iclass 32, count 0 2006.169.07:56:49.15#ibcon#*before return 0, iclass 32, count 0 2006.169.07:56:49.15#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:56:49.15#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.169.07:56:49.15#ibcon#about to clear, iclass 32 cls_cnt 0 2006.169.07:56:49.15#ibcon#cleared, iclass 32 cls_cnt 0 2006.169.07:56:49.15$vc4f8/vblo=6,752.99 2006.169.07:56:49.15#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.169.07:56:49.15#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.169.07:56:49.15#ibcon#ireg 17 cls_cnt 0 2006.169.07:56:49.15#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:56:49.15#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:56:49.15#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:56:49.15#ibcon#enter wrdev, iclass 34, count 0 2006.169.07:56:49.15#ibcon#first serial, iclass 34, count 0 2006.169.07:56:49.15#ibcon#enter sib2, iclass 34, count 0 2006.169.07:56:49.15#ibcon#flushed, iclass 34, count 0 2006.169.07:56:49.15#ibcon#about to write, iclass 34, count 0 2006.169.07:56:49.15#ibcon#wrote, iclass 34, count 0 2006.169.07:56:49.15#ibcon#about to read 3, iclass 34, count 0 2006.169.07:56:49.17#ibcon#read 3, iclass 34, count 0 2006.169.07:56:49.17#ibcon#about to read 4, iclass 34, count 0 2006.169.07:56:49.17#ibcon#read 4, iclass 34, count 0 2006.169.07:56:49.17#ibcon#about to read 5, iclass 34, count 0 2006.169.07:56:49.17#ibcon#read 5, iclass 34, count 0 2006.169.07:56:49.17#ibcon#about to read 6, iclass 34, count 0 2006.169.07:56:49.17#ibcon#read 6, iclass 34, count 0 2006.169.07:56:49.17#ibcon#end of sib2, iclass 34, count 0 2006.169.07:56:49.17#ibcon#*mode == 0, iclass 34, count 0 2006.169.07:56:49.17#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.169.07:56:49.17#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.07:56:49.17#ibcon#*before write, iclass 34, count 0 2006.169.07:56:49.17#ibcon#enter sib2, iclass 34, count 0 2006.169.07:56:49.17#ibcon#flushed, iclass 34, count 0 2006.169.07:56:49.17#ibcon#about to write, iclass 34, count 0 2006.169.07:56:49.17#ibcon#wrote, iclass 34, count 0 2006.169.07:56:49.17#ibcon#about to read 3, iclass 34, count 0 2006.169.07:56:49.21#ibcon#read 3, iclass 34, count 0 2006.169.07:56:49.21#ibcon#about to read 4, iclass 34, count 0 2006.169.07:56:49.21#ibcon#read 4, iclass 34, count 0 2006.169.07:56:49.21#ibcon#about to read 5, iclass 34, count 0 2006.169.07:56:49.21#ibcon#read 5, iclass 34, count 0 2006.169.07:56:49.21#ibcon#about to read 6, iclass 34, count 0 2006.169.07:56:49.21#ibcon#read 6, iclass 34, count 0 2006.169.07:56:49.21#ibcon#end of sib2, iclass 34, count 0 2006.169.07:56:49.21#ibcon#*after write, iclass 34, count 0 2006.169.07:56:49.21#ibcon#*before return 0, iclass 34, count 0 2006.169.07:56:49.21#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:56:49.21#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.169.07:56:49.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.169.07:56:49.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.169.07:56:49.21$vc4f8/vb=6,4 2006.169.07:56:49.21#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.169.07:56:49.21#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.169.07:56:49.21#ibcon#ireg 11 cls_cnt 2 2006.169.07:56:49.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.169.07:56:49.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.169.07:56:49.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.169.07:56:49.27#ibcon#enter wrdev, iclass 36, count 2 2006.169.07:56:49.27#ibcon#first serial, iclass 36, count 2 2006.169.07:56:49.27#ibcon#enter sib2, iclass 36, count 2 2006.169.07:56:49.27#ibcon#flushed, iclass 36, count 2 2006.169.07:56:49.27#ibcon#about to write, iclass 36, count 2 2006.169.07:56:49.27#ibcon#wrote, iclass 36, count 2 2006.169.07:56:49.27#ibcon#about to read 3, iclass 36, count 2 2006.169.07:56:49.29#ibcon#read 3, iclass 36, count 2 2006.169.07:56:49.29#ibcon#about to read 4, iclass 36, count 2 2006.169.07:56:49.29#ibcon#read 4, iclass 36, count 2 2006.169.07:56:49.29#ibcon#about to read 5, iclass 36, count 2 2006.169.07:56:49.29#ibcon#read 5, iclass 36, count 2 2006.169.07:56:49.29#ibcon#about to read 6, iclass 36, count 2 2006.169.07:56:49.29#ibcon#read 6, iclass 36, count 2 2006.169.07:56:49.29#ibcon#end of sib2, iclass 36, count 2 2006.169.07:56:49.29#ibcon#*mode == 0, iclass 36, count 2 2006.169.07:56:49.29#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.169.07:56:49.29#ibcon#[27=AT06-04\r\n] 2006.169.07:56:49.29#ibcon#*before write, iclass 36, count 2 2006.169.07:56:49.29#ibcon#enter sib2, iclass 36, count 2 2006.169.07:56:49.29#ibcon#flushed, iclass 36, count 2 2006.169.07:56:49.29#ibcon#about to write, iclass 36, count 2 2006.169.07:56:49.29#ibcon#wrote, iclass 36, count 2 2006.169.07:56:49.29#ibcon#about to read 3, iclass 36, count 2 2006.169.07:56:49.32#ibcon#read 3, iclass 36, count 2 2006.169.07:56:49.32#ibcon#about to read 4, iclass 36, count 2 2006.169.07:56:49.32#ibcon#read 4, iclass 36, count 2 2006.169.07:56:49.32#ibcon#about to read 5, iclass 36, count 2 2006.169.07:56:49.32#ibcon#read 5, iclass 36, count 2 2006.169.07:56:49.32#ibcon#about to read 6, iclass 36, count 2 2006.169.07:56:49.32#ibcon#read 6, iclass 36, count 2 2006.169.07:56:49.32#ibcon#end of sib2, iclass 36, count 2 2006.169.07:56:49.32#ibcon#*after write, iclass 36, count 2 2006.169.07:56:49.32#ibcon#*before return 0, iclass 36, count 2 2006.169.07:56:49.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.169.07:56:49.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.169.07:56:49.32#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.169.07:56:49.32#ibcon#ireg 7 cls_cnt 0 2006.169.07:56:49.32#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.169.07:56:49.44#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.169.07:56:49.44#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.169.07:56:49.44#ibcon#enter wrdev, iclass 36, count 0 2006.169.07:56:49.44#ibcon#first serial, iclass 36, count 0 2006.169.07:56:49.44#ibcon#enter sib2, iclass 36, count 0 2006.169.07:56:49.44#ibcon#flushed, iclass 36, count 0 2006.169.07:56:49.44#ibcon#about to write, iclass 36, count 0 2006.169.07:56:49.44#ibcon#wrote, iclass 36, count 0 2006.169.07:56:49.44#ibcon#about to read 3, iclass 36, count 0 2006.169.07:56:49.46#ibcon#read 3, iclass 36, count 0 2006.169.07:56:49.46#ibcon#about to read 4, iclass 36, count 0 2006.169.07:56:49.46#ibcon#read 4, iclass 36, count 0 2006.169.07:56:49.46#ibcon#about to read 5, iclass 36, count 0 2006.169.07:56:49.46#ibcon#read 5, iclass 36, count 0 2006.169.07:56:49.46#ibcon#about to read 6, iclass 36, count 0 2006.169.07:56:49.46#ibcon#read 6, iclass 36, count 0 2006.169.07:56:49.46#ibcon#end of sib2, iclass 36, count 0 2006.169.07:56:49.46#ibcon#*mode == 0, iclass 36, count 0 2006.169.07:56:49.46#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.169.07:56:49.46#ibcon#[27=USB\r\n] 2006.169.07:56:49.46#ibcon#*before write, iclass 36, count 0 2006.169.07:56:49.46#ibcon#enter sib2, iclass 36, count 0 2006.169.07:56:49.46#ibcon#flushed, iclass 36, count 0 2006.169.07:56:49.46#ibcon#about to write, iclass 36, count 0 2006.169.07:56:49.46#ibcon#wrote, iclass 36, count 0 2006.169.07:56:49.46#ibcon#about to read 3, iclass 36, count 0 2006.169.07:56:49.49#ibcon#read 3, iclass 36, count 0 2006.169.07:56:49.49#ibcon#about to read 4, iclass 36, count 0 2006.169.07:56:49.49#ibcon#read 4, iclass 36, count 0 2006.169.07:56:49.49#ibcon#about to read 5, iclass 36, count 0 2006.169.07:56:49.49#ibcon#read 5, iclass 36, count 0 2006.169.07:56:49.49#ibcon#about to read 6, iclass 36, count 0 2006.169.07:56:49.49#ibcon#read 6, iclass 36, count 0 2006.169.07:56:49.49#ibcon#end of sib2, iclass 36, count 0 2006.169.07:56:49.49#ibcon#*after write, iclass 36, count 0 2006.169.07:56:49.49#ibcon#*before return 0, iclass 36, count 0 2006.169.07:56:49.49#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.169.07:56:49.49#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.169.07:56:49.49#ibcon#about to clear, iclass 36 cls_cnt 0 2006.169.07:56:49.49#ibcon#cleared, iclass 36 cls_cnt 0 2006.169.07:56:49.49$vc4f8/vabw=wide 2006.169.07:56:49.49#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.169.07:56:49.49#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.169.07:56:49.49#ibcon#ireg 8 cls_cnt 0 2006.169.07:56:49.49#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:56:49.49#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:56:49.49#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:56:49.49#ibcon#enter wrdev, iclass 38, count 0 2006.169.07:56:49.49#ibcon#first serial, iclass 38, count 0 2006.169.07:56:49.49#ibcon#enter sib2, iclass 38, count 0 2006.169.07:56:49.49#ibcon#flushed, iclass 38, count 0 2006.169.07:56:49.49#ibcon#about to write, iclass 38, count 0 2006.169.07:56:49.49#ibcon#wrote, iclass 38, count 0 2006.169.07:56:49.49#ibcon#about to read 3, iclass 38, count 0 2006.169.07:56:49.51#ibcon#read 3, iclass 38, count 0 2006.169.07:56:49.51#ibcon#about to read 4, iclass 38, count 0 2006.169.07:56:49.51#ibcon#read 4, iclass 38, count 0 2006.169.07:56:49.51#ibcon#about to read 5, iclass 38, count 0 2006.169.07:56:49.51#ibcon#read 5, iclass 38, count 0 2006.169.07:56:49.51#ibcon#about to read 6, iclass 38, count 0 2006.169.07:56:49.51#ibcon#read 6, iclass 38, count 0 2006.169.07:56:49.51#ibcon#end of sib2, iclass 38, count 0 2006.169.07:56:49.51#ibcon#*mode == 0, iclass 38, count 0 2006.169.07:56:49.51#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.169.07:56:49.51#ibcon#[25=BW32\r\n] 2006.169.07:56:49.51#ibcon#*before write, iclass 38, count 0 2006.169.07:56:49.51#ibcon#enter sib2, iclass 38, count 0 2006.169.07:56:49.51#ibcon#flushed, iclass 38, count 0 2006.169.07:56:49.51#ibcon#about to write, iclass 38, count 0 2006.169.07:56:49.51#ibcon#wrote, iclass 38, count 0 2006.169.07:56:49.51#ibcon#about to read 3, iclass 38, count 0 2006.169.07:56:49.54#ibcon#read 3, iclass 38, count 0 2006.169.07:56:49.54#ibcon#about to read 4, iclass 38, count 0 2006.169.07:56:49.54#ibcon#read 4, iclass 38, count 0 2006.169.07:56:49.54#ibcon#about to read 5, iclass 38, count 0 2006.169.07:56:49.54#ibcon#read 5, iclass 38, count 0 2006.169.07:56:49.54#ibcon#about to read 6, iclass 38, count 0 2006.169.07:56:49.54#ibcon#read 6, iclass 38, count 0 2006.169.07:56:49.54#ibcon#end of sib2, iclass 38, count 0 2006.169.07:56:49.54#ibcon#*after write, iclass 38, count 0 2006.169.07:56:49.54#ibcon#*before return 0, iclass 38, count 0 2006.169.07:56:49.54#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:56:49.54#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.169.07:56:49.54#ibcon#about to clear, iclass 38 cls_cnt 0 2006.169.07:56:49.54#ibcon#cleared, iclass 38 cls_cnt 0 2006.169.07:56:49.54$vc4f8/vbbw=wide 2006.169.07:56:49.54#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.169.07:56:49.54#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.169.07:56:49.54#ibcon#ireg 8 cls_cnt 0 2006.169.07:56:49.54#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:56:49.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:56:49.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:56:49.61#ibcon#enter wrdev, iclass 40, count 0 2006.169.07:56:49.61#ibcon#first serial, iclass 40, count 0 2006.169.07:56:49.61#ibcon#enter sib2, iclass 40, count 0 2006.169.07:56:49.61#ibcon#flushed, iclass 40, count 0 2006.169.07:56:49.61#ibcon#about to write, iclass 40, count 0 2006.169.07:56:49.61#ibcon#wrote, iclass 40, count 0 2006.169.07:56:49.61#ibcon#about to read 3, iclass 40, count 0 2006.169.07:56:49.63#ibcon#read 3, iclass 40, count 0 2006.169.07:56:49.63#ibcon#about to read 4, iclass 40, count 0 2006.169.07:56:49.63#ibcon#read 4, iclass 40, count 0 2006.169.07:56:49.63#ibcon#about to read 5, iclass 40, count 0 2006.169.07:56:49.63#ibcon#read 5, iclass 40, count 0 2006.169.07:56:49.63#ibcon#about to read 6, iclass 40, count 0 2006.169.07:56:49.63#ibcon#read 6, iclass 40, count 0 2006.169.07:56:49.63#ibcon#end of sib2, iclass 40, count 0 2006.169.07:56:49.63#ibcon#*mode == 0, iclass 40, count 0 2006.169.07:56:49.63#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.169.07:56:49.63#ibcon#[27=BW32\r\n] 2006.169.07:56:49.63#ibcon#*before write, iclass 40, count 0 2006.169.07:56:49.63#ibcon#enter sib2, iclass 40, count 0 2006.169.07:56:49.63#ibcon#flushed, iclass 40, count 0 2006.169.07:56:49.63#ibcon#about to write, iclass 40, count 0 2006.169.07:56:49.63#ibcon#wrote, iclass 40, count 0 2006.169.07:56:49.63#ibcon#about to read 3, iclass 40, count 0 2006.169.07:56:49.66#ibcon#read 3, iclass 40, count 0 2006.169.07:56:49.66#ibcon#about to read 4, iclass 40, count 0 2006.169.07:56:49.66#ibcon#read 4, iclass 40, count 0 2006.169.07:56:49.66#ibcon#about to read 5, iclass 40, count 0 2006.169.07:56:49.66#ibcon#read 5, iclass 40, count 0 2006.169.07:56:49.66#ibcon#about to read 6, iclass 40, count 0 2006.169.07:56:49.66#ibcon#read 6, iclass 40, count 0 2006.169.07:56:49.66#ibcon#end of sib2, iclass 40, count 0 2006.169.07:56:49.66#ibcon#*after write, iclass 40, count 0 2006.169.07:56:49.66#ibcon#*before return 0, iclass 40, count 0 2006.169.07:56:49.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:56:49.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.169.07:56:49.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.169.07:56:49.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.169.07:56:49.66$4f8m12a/ifd4f 2006.169.07:56:49.66$ifd4f/lo= 2006.169.07:56:49.66$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.07:56:49.66$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.07:56:49.66$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.07:56:49.66$ifd4f/patch= 2006.169.07:56:49.66$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.07:56:49.66$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.07:56:49.66$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.07:56:49.66$4f8m12a/"form=m,16.000,1:2 2006.169.07:56:49.66$4f8m12a/"tpicd 2006.169.07:56:49.66$4f8m12a/echo=off 2006.169.07:56:49.66$4f8m12a/xlog=off 2006.169.07:56:49.66:!2006.169.07:58:40 2006.169.07:56:56.14#trakl#Source acquired 2006.169.07:56:57.14#flagr#flagr/antenna,acquired 2006.169.07:58:40.00:preob 2006.169.07:58:40.14/onsource/TRACKING 2006.169.07:58:40.14:!2006.169.07:58:50 2006.169.07:58:50.00:data_valid=on 2006.169.07:58:50.00:midob 2006.169.07:58:51.14/onsource/TRACKING 2006.169.07:58:51.14/wx/18.11,1004.0,100 2006.169.07:58:51.20/cable/+6.5293E-03 2006.169.07:58:52.29/va/01,08,usb,yes,46,48 2006.169.07:58:52.29/va/02,07,usb,yes,47,49 2006.169.07:58:52.29/va/03,06,usb,yes,49,50 2006.169.07:58:52.29/va/04,07,usb,yes,48,51 2006.169.07:58:52.29/va/05,07,usb,yes,52,55 2006.169.07:58:52.29/va/06,06,usb,yes,52,51 2006.169.07:58:52.29/va/07,06,usb,yes,52,52 2006.169.07:58:52.29/va/08,07,usb,yes,49,49 2006.169.07:58:52.52/valo/01,532.99,yes,locked 2006.169.07:58:52.52/valo/02,572.99,yes,locked 2006.169.07:58:52.52/valo/03,672.99,yes,locked 2006.169.07:58:52.52/valo/04,832.99,yes,locked 2006.169.07:58:52.52/valo/05,652.99,yes,locked 2006.169.07:58:52.52/valo/06,772.99,yes,locked 2006.169.07:58:52.52/valo/07,832.99,yes,locked 2006.169.07:58:52.52/valo/08,852.99,yes,locked 2006.169.07:58:53.61/vb/01,04,usb,yes,30,29 2006.169.07:58:53.61/vb/02,04,usb,yes,32,34 2006.169.07:58:53.61/vb/03,04,usb,yes,28,32 2006.169.07:58:53.61/vb/04,04,usb,yes,29,29 2006.169.07:58:53.61/vb/05,04,usb,yes,28,32 2006.169.07:58:53.61/vb/06,04,usb,yes,29,32 2006.169.07:58:53.61/vb/07,04,usb,yes,31,31 2006.169.07:58:53.61/vb/08,04,usb,yes,28,32 2006.169.07:58:53.85/vblo/01,632.99,yes,locked 2006.169.07:58:53.85/vblo/02,640.99,yes,locked 2006.169.07:58:53.85/vblo/03,656.99,yes,locked 2006.169.07:58:53.85/vblo/04,712.99,yes,locked 2006.169.07:58:53.85/vblo/05,744.99,yes,locked 2006.169.07:58:53.85/vblo/06,752.99,yes,locked 2006.169.07:58:53.85/vblo/07,734.99,yes,locked 2006.169.07:58:53.85/vblo/08,744.99,yes,locked 2006.169.07:58:54.00/vabw/8 2006.169.07:58:54.15/vbbw/8 2006.169.07:58:54.24/xfe/off,on,15.2 2006.169.07:58:54.61/ifatt/23,28,28,28 2006.169.07:58:55.07/fmout-gps/S +4.18E-07 2006.169.07:58:55.14:!2006.169.07:59:50 2006.169.07:59:50.01:data_valid=off 2006.169.07:59:50.01:postob 2006.169.07:59:50.12/cable/+6.5299E-03 2006.169.07:59:50.12/wx/18.11,1004.0,100 2006.169.07:59:51.07/fmout-gps/S +4.18E-07 2006.169.07:59:51.07:scan_name=169-0801,k06169,60 2006.169.07:59:51.08:source=1418+546,141946.60,542314.8,2000.0,cw 2006.169.07:59:51.14#flagr#flagr/antenna,new-source 2006.169.07:59:52.14:checkk5 2006.169.07:59:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.169.07:59:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.169.07:59:56.92/chk_autoobs//k5ts3?ERROR: timeout happened! 2006.169.07:59:57.31/chk_autoobs//k5ts4/ autoobs is running! 2006.169.07:59:57.67/chk_obsdata//k5ts1/T1690758??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.07:59:58.04/chk_obsdata//k5ts2/T1690758??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.08:00:05.10/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.08:00:05.47/chk_obsdata//k5ts4/T1690758??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.08:00:06.16/k5log//k5ts1_log_newline 2006.169.08:00:06.85/k5log//k5ts2_log_newline 2006.169.08:00:13.95/k5log//k5ts3?ERROR: timeout happened! 2006.169.08:00:14.64/k5log//k5ts4_log_newline 2006.169.08:00:14.82/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.08:00:14.82:4f8m12a=2 2006.169.08:00:14.82$4f8m12a/echo=on 2006.169.08:00:14.82$4f8m12a/pcalon 2006.169.08:00:14.82$pcalon/"no phase cal control is implemented here 2006.169.08:00:14.82$4f8m12a/"tpicd=stop 2006.169.08:00:14.82$4f8m12a/vc4f8 2006.169.08:00:14.82$vc4f8/valo=1,532.99 2006.169.08:00:14.82#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.169.08:00:14.82#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.169.08:00:14.82#ibcon#ireg 17 cls_cnt 0 2006.169.08:00:14.82#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:00:14.82#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:00:14.82#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:00:14.82#ibcon#enter wrdev, iclass 16, count 0 2006.169.08:00:14.82#ibcon#first serial, iclass 16, count 0 2006.169.08:00:14.82#ibcon#enter sib2, iclass 16, count 0 2006.169.08:00:14.82#ibcon#flushed, iclass 16, count 0 2006.169.08:00:14.82#ibcon#about to write, iclass 16, count 0 2006.169.08:00:14.82#ibcon#wrote, iclass 16, count 0 2006.169.08:00:14.82#ibcon#about to read 3, iclass 16, count 0 2006.169.08:00:14.84#ibcon#read 3, iclass 16, count 0 2006.169.08:00:14.84#ibcon#about to read 4, iclass 16, count 0 2006.169.08:00:14.84#ibcon#read 4, iclass 16, count 0 2006.169.08:00:14.84#ibcon#about to read 5, iclass 16, count 0 2006.169.08:00:14.84#ibcon#read 5, iclass 16, count 0 2006.169.08:00:14.84#ibcon#about to read 6, iclass 16, count 0 2006.169.08:00:14.84#ibcon#read 6, iclass 16, count 0 2006.169.08:00:14.84#ibcon#end of sib2, iclass 16, count 0 2006.169.08:00:14.84#ibcon#*mode == 0, iclass 16, count 0 2006.169.08:00:14.84#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.169.08:00:14.84#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.08:00:14.84#ibcon#*before write, iclass 16, count 0 2006.169.08:00:14.84#ibcon#enter sib2, iclass 16, count 0 2006.169.08:00:14.84#ibcon#flushed, iclass 16, count 0 2006.169.08:00:14.84#ibcon#about to write, iclass 16, count 0 2006.169.08:00:14.84#ibcon#wrote, iclass 16, count 0 2006.169.08:00:14.84#ibcon#about to read 3, iclass 16, count 0 2006.169.08:00:14.88#abcon#{5=INTERFACE CLEAR} 2006.169.08:00:14.90#ibcon#read 3, iclass 16, count 0 2006.169.08:00:14.90#ibcon#about to read 4, iclass 16, count 0 2006.169.08:00:14.90#ibcon#read 4, iclass 16, count 0 2006.169.08:00:14.90#ibcon#about to read 5, iclass 16, count 0 2006.169.08:00:14.90#ibcon#read 5, iclass 16, count 0 2006.169.08:00:14.90#ibcon#about to read 6, iclass 16, count 0 2006.169.08:00:14.90#ibcon#read 6, iclass 16, count 0 2006.169.08:00:14.90#ibcon#end of sib2, iclass 16, count 0 2006.169.08:00:14.90#ibcon#*after write, iclass 16, count 0 2006.169.08:00:14.90#ibcon#*before return 0, iclass 16, count 0 2006.169.08:00:14.90#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:00:14.90#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:00:14.90#ibcon#about to clear, iclass 16 cls_cnt 0 2006.169.08:00:14.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.169.08:00:14.90$vc4f8/va=1,8 2006.169.08:00:14.90#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.169.08:00:14.90#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.169.08:00:14.90#ibcon#ireg 11 cls_cnt 2 2006.169.08:00:14.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.169.08:00:14.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.169.08:00:14.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.169.08:00:14.90#ibcon#enter wrdev, iclass 20, count 2 2006.169.08:00:14.90#ibcon#first serial, iclass 20, count 2 2006.169.08:00:14.90#ibcon#enter sib2, iclass 20, count 2 2006.169.08:00:14.90#ibcon#flushed, iclass 20, count 2 2006.169.08:00:14.90#ibcon#about to write, iclass 20, count 2 2006.169.08:00:14.90#ibcon#wrote, iclass 20, count 2 2006.169.08:00:14.90#ibcon#about to read 3, iclass 20, count 2 2006.169.08:00:14.91#ibcon#read 3, iclass 20, count 2 2006.169.08:00:14.91#ibcon#about to read 4, iclass 20, count 2 2006.169.08:00:14.91#ibcon#read 4, iclass 20, count 2 2006.169.08:00:14.91#ibcon#about to read 5, iclass 20, count 2 2006.169.08:00:14.91#ibcon#read 5, iclass 20, count 2 2006.169.08:00:14.91#ibcon#about to read 6, iclass 20, count 2 2006.169.08:00:14.91#ibcon#read 6, iclass 20, count 2 2006.169.08:00:14.91#ibcon#end of sib2, iclass 20, count 2 2006.169.08:00:14.91#ibcon#*mode == 0, iclass 20, count 2 2006.169.08:00:14.91#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.169.08:00:14.91#ibcon#[25=AT01-08\r\n] 2006.169.08:00:14.91#ibcon#*before write, iclass 20, count 2 2006.169.08:00:14.91#ibcon#enter sib2, iclass 20, count 2 2006.169.08:00:14.91#ibcon#flushed, iclass 20, count 2 2006.169.08:00:14.91#ibcon#about to write, iclass 20, count 2 2006.169.08:00:14.91#ibcon#wrote, iclass 20, count 2 2006.169.08:00:14.91#ibcon#about to read 3, iclass 20, count 2 2006.169.08:00:14.94#abcon#[5=S1D000X0/0*\r\n] 2006.169.08:00:14.94#ibcon#read 3, iclass 20, count 2 2006.169.08:00:14.94#ibcon#about to read 4, iclass 20, count 2 2006.169.08:00:14.94#ibcon#read 4, iclass 20, count 2 2006.169.08:00:14.94#ibcon#about to read 5, iclass 20, count 2 2006.169.08:00:14.94#ibcon#read 5, iclass 20, count 2 2006.169.08:00:14.94#ibcon#about to read 6, iclass 20, count 2 2006.169.08:00:14.94#ibcon#read 6, iclass 20, count 2 2006.169.08:00:14.94#ibcon#end of sib2, iclass 20, count 2 2006.169.08:00:14.94#ibcon#*after write, iclass 20, count 2 2006.169.08:00:14.94#ibcon#*before return 0, iclass 20, count 2 2006.169.08:00:14.94#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.169.08:00:14.94#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.169.08:00:14.94#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.169.08:00:14.94#ibcon#ireg 7 cls_cnt 0 2006.169.08:00:14.94#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.169.08:00:15.06#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.169.08:00:15.06#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.169.08:00:15.06#ibcon#enter wrdev, iclass 20, count 0 2006.169.08:00:15.06#ibcon#first serial, iclass 20, count 0 2006.169.08:00:15.06#ibcon#enter sib2, iclass 20, count 0 2006.169.08:00:15.06#ibcon#flushed, iclass 20, count 0 2006.169.08:00:15.06#ibcon#about to write, iclass 20, count 0 2006.169.08:00:15.06#ibcon#wrote, iclass 20, count 0 2006.169.08:00:15.06#ibcon#about to read 3, iclass 20, count 0 2006.169.08:00:15.10#ibcon#read 3, iclass 20, count 0 2006.169.08:00:15.10#ibcon#about to read 4, iclass 20, count 0 2006.169.08:00:15.10#ibcon#read 4, iclass 20, count 0 2006.169.08:00:15.10#ibcon#about to read 5, iclass 20, count 0 2006.169.08:00:15.10#ibcon#read 5, iclass 20, count 0 2006.169.08:00:15.10#ibcon#about to read 6, iclass 20, count 0 2006.169.08:00:15.10#ibcon#read 6, iclass 20, count 0 2006.169.08:00:15.10#ibcon#end of sib2, iclass 20, count 0 2006.169.08:00:15.10#ibcon#*mode == 0, iclass 20, count 0 2006.169.08:00:15.10#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.169.08:00:15.10#ibcon#[25=USB\r\n] 2006.169.08:00:15.10#ibcon#*before write, iclass 20, count 0 2006.169.08:00:15.10#ibcon#enter sib2, iclass 20, count 0 2006.169.08:00:15.10#ibcon#flushed, iclass 20, count 0 2006.169.08:00:15.10#ibcon#about to write, iclass 20, count 0 2006.169.08:00:15.10#ibcon#wrote, iclass 20, count 0 2006.169.08:00:15.10#ibcon#about to read 3, iclass 20, count 0 2006.169.08:00:15.13#ibcon#read 3, iclass 20, count 0 2006.169.08:00:15.13#ibcon#about to read 4, iclass 20, count 0 2006.169.08:00:15.13#ibcon#read 4, iclass 20, count 0 2006.169.08:00:15.13#ibcon#about to read 5, iclass 20, count 0 2006.169.08:00:15.13#ibcon#read 5, iclass 20, count 0 2006.169.08:00:15.13#ibcon#about to read 6, iclass 20, count 0 2006.169.08:00:15.13#ibcon#read 6, iclass 20, count 0 2006.169.08:00:15.13#ibcon#end of sib2, iclass 20, count 0 2006.169.08:00:15.13#ibcon#*after write, iclass 20, count 0 2006.169.08:00:15.13#ibcon#*before return 0, iclass 20, count 0 2006.169.08:00:15.13#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.169.08:00:15.13#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.169.08:00:15.13#ibcon#about to clear, iclass 20 cls_cnt 0 2006.169.08:00:15.13#ibcon#cleared, iclass 20 cls_cnt 0 2006.169.08:00:15.13$vc4f8/valo=2,572.99 2006.169.08:00:15.13#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.169.08:00:15.13#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.169.08:00:15.13#ibcon#ireg 17 cls_cnt 0 2006.169.08:00:15.13#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:00:15.13#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:00:15.13#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:00:15.13#ibcon#enter wrdev, iclass 23, count 0 2006.169.08:00:15.13#ibcon#first serial, iclass 23, count 0 2006.169.08:00:15.13#ibcon#enter sib2, iclass 23, count 0 2006.169.08:00:15.13#ibcon#flushed, iclass 23, count 0 2006.169.08:00:15.13#ibcon#about to write, iclass 23, count 0 2006.169.08:00:15.13#ibcon#wrote, iclass 23, count 0 2006.169.08:00:15.13#ibcon#about to read 3, iclass 23, count 0 2006.169.08:00:15.15#ibcon#read 3, iclass 23, count 0 2006.169.08:00:15.15#ibcon#about to read 4, iclass 23, count 0 2006.169.08:00:15.15#ibcon#read 4, iclass 23, count 0 2006.169.08:00:15.15#ibcon#about to read 5, iclass 23, count 0 2006.169.08:00:15.15#ibcon#read 5, iclass 23, count 0 2006.169.08:00:15.15#ibcon#about to read 6, iclass 23, count 0 2006.169.08:00:15.15#ibcon#read 6, iclass 23, count 0 2006.169.08:00:15.15#ibcon#end of sib2, iclass 23, count 0 2006.169.08:00:15.15#ibcon#*mode == 0, iclass 23, count 0 2006.169.08:00:15.15#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.169.08:00:15.15#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.08:00:15.15#ibcon#*before write, iclass 23, count 0 2006.169.08:00:15.15#ibcon#enter sib2, iclass 23, count 0 2006.169.08:00:15.15#ibcon#flushed, iclass 23, count 0 2006.169.08:00:15.15#ibcon#about to write, iclass 23, count 0 2006.169.08:00:15.15#ibcon#wrote, iclass 23, count 0 2006.169.08:00:15.15#ibcon#about to read 3, iclass 23, count 0 2006.169.08:00:15.19#ibcon#read 3, iclass 23, count 0 2006.169.08:00:15.19#ibcon#about to read 4, iclass 23, count 0 2006.169.08:00:15.19#ibcon#read 4, iclass 23, count 0 2006.169.08:00:15.19#ibcon#about to read 5, iclass 23, count 0 2006.169.08:00:15.19#ibcon#read 5, iclass 23, count 0 2006.169.08:00:15.19#ibcon#about to read 6, iclass 23, count 0 2006.169.08:00:15.19#ibcon#read 6, iclass 23, count 0 2006.169.08:00:15.19#ibcon#end of sib2, iclass 23, count 0 2006.169.08:00:15.19#ibcon#*after write, iclass 23, count 0 2006.169.08:00:15.19#ibcon#*before return 0, iclass 23, count 0 2006.169.08:00:15.19#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:00:15.19#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:00:15.19#ibcon#about to clear, iclass 23 cls_cnt 0 2006.169.08:00:15.19#ibcon#cleared, iclass 23 cls_cnt 0 2006.169.08:00:15.19$vc4f8/va=2,7 2006.169.08:00:15.19#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.169.08:00:15.19#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.169.08:00:15.19#ibcon#ireg 11 cls_cnt 2 2006.169.08:00:15.19#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:00:15.25#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:00:15.25#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:00:15.25#ibcon#enter wrdev, iclass 25, count 2 2006.169.08:00:15.25#ibcon#first serial, iclass 25, count 2 2006.169.08:00:15.25#ibcon#enter sib2, iclass 25, count 2 2006.169.08:00:15.25#ibcon#flushed, iclass 25, count 2 2006.169.08:00:15.25#ibcon#about to write, iclass 25, count 2 2006.169.08:00:15.25#ibcon#wrote, iclass 25, count 2 2006.169.08:00:15.25#ibcon#about to read 3, iclass 25, count 2 2006.169.08:00:15.28#ibcon#read 3, iclass 25, count 2 2006.169.08:00:15.28#ibcon#about to read 4, iclass 25, count 2 2006.169.08:00:15.28#ibcon#read 4, iclass 25, count 2 2006.169.08:00:15.28#ibcon#about to read 5, iclass 25, count 2 2006.169.08:00:15.28#ibcon#read 5, iclass 25, count 2 2006.169.08:00:15.28#ibcon#about to read 6, iclass 25, count 2 2006.169.08:00:15.28#ibcon#read 6, iclass 25, count 2 2006.169.08:00:15.28#ibcon#end of sib2, iclass 25, count 2 2006.169.08:00:15.28#ibcon#*mode == 0, iclass 25, count 2 2006.169.08:00:15.28#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.169.08:00:15.28#ibcon#[25=AT02-07\r\n] 2006.169.08:00:15.28#ibcon#*before write, iclass 25, count 2 2006.169.08:00:15.28#ibcon#enter sib2, iclass 25, count 2 2006.169.08:00:15.28#ibcon#flushed, iclass 25, count 2 2006.169.08:00:15.28#ibcon#about to write, iclass 25, count 2 2006.169.08:00:15.28#ibcon#wrote, iclass 25, count 2 2006.169.08:00:15.28#ibcon#about to read 3, iclass 25, count 2 2006.169.08:00:15.31#ibcon#read 3, iclass 25, count 2 2006.169.08:00:15.31#ibcon#about to read 4, iclass 25, count 2 2006.169.08:00:15.31#ibcon#read 4, iclass 25, count 2 2006.169.08:00:15.31#ibcon#about to read 5, iclass 25, count 2 2006.169.08:00:15.31#ibcon#read 5, iclass 25, count 2 2006.169.08:00:15.31#ibcon#about to read 6, iclass 25, count 2 2006.169.08:00:15.31#ibcon#read 6, iclass 25, count 2 2006.169.08:00:15.31#ibcon#end of sib2, iclass 25, count 2 2006.169.08:00:15.31#ibcon#*after write, iclass 25, count 2 2006.169.08:00:15.31#ibcon#*before return 0, iclass 25, count 2 2006.169.08:00:15.31#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:00:15.31#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:00:15.31#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.169.08:00:15.31#ibcon#ireg 7 cls_cnt 0 2006.169.08:00:15.31#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:00:15.43#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:00:15.43#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:00:15.43#ibcon#enter wrdev, iclass 25, count 0 2006.169.08:00:15.43#ibcon#first serial, iclass 25, count 0 2006.169.08:00:15.43#ibcon#enter sib2, iclass 25, count 0 2006.169.08:00:15.43#ibcon#flushed, iclass 25, count 0 2006.169.08:00:15.43#ibcon#about to write, iclass 25, count 0 2006.169.08:00:15.43#ibcon#wrote, iclass 25, count 0 2006.169.08:00:15.43#ibcon#about to read 3, iclass 25, count 0 2006.169.08:00:15.45#ibcon#read 3, iclass 25, count 0 2006.169.08:00:15.45#ibcon#about to read 4, iclass 25, count 0 2006.169.08:00:15.45#ibcon#read 4, iclass 25, count 0 2006.169.08:00:15.45#ibcon#about to read 5, iclass 25, count 0 2006.169.08:00:15.45#ibcon#read 5, iclass 25, count 0 2006.169.08:00:15.45#ibcon#about to read 6, iclass 25, count 0 2006.169.08:00:15.45#ibcon#read 6, iclass 25, count 0 2006.169.08:00:15.45#ibcon#end of sib2, iclass 25, count 0 2006.169.08:00:15.45#ibcon#*mode == 0, iclass 25, count 0 2006.169.08:00:15.45#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.169.08:00:15.45#ibcon#[25=USB\r\n] 2006.169.08:00:15.45#ibcon#*before write, iclass 25, count 0 2006.169.08:00:15.45#ibcon#enter sib2, iclass 25, count 0 2006.169.08:00:15.45#ibcon#flushed, iclass 25, count 0 2006.169.08:00:15.45#ibcon#about to write, iclass 25, count 0 2006.169.08:00:15.45#ibcon#wrote, iclass 25, count 0 2006.169.08:00:15.45#ibcon#about to read 3, iclass 25, count 0 2006.169.08:00:15.48#ibcon#read 3, iclass 25, count 0 2006.169.08:00:15.48#ibcon#about to read 4, iclass 25, count 0 2006.169.08:00:15.48#ibcon#read 4, iclass 25, count 0 2006.169.08:00:15.48#ibcon#about to read 5, iclass 25, count 0 2006.169.08:00:15.48#ibcon#read 5, iclass 25, count 0 2006.169.08:00:15.48#ibcon#about to read 6, iclass 25, count 0 2006.169.08:00:15.48#ibcon#read 6, iclass 25, count 0 2006.169.08:00:15.48#ibcon#end of sib2, iclass 25, count 0 2006.169.08:00:15.48#ibcon#*after write, iclass 25, count 0 2006.169.08:00:15.48#ibcon#*before return 0, iclass 25, count 0 2006.169.08:00:15.48#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:00:15.48#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:00:15.48#ibcon#about to clear, iclass 25 cls_cnt 0 2006.169.08:00:15.48#ibcon#cleared, iclass 25 cls_cnt 0 2006.169.08:00:15.48$vc4f8/valo=3,672.99 2006.169.08:00:15.48#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.169.08:00:15.48#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.169.08:00:15.48#ibcon#ireg 17 cls_cnt 0 2006.169.08:00:15.48#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:00:15.48#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:00:15.48#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:00:15.48#ibcon#enter wrdev, iclass 27, count 0 2006.169.08:00:15.48#ibcon#first serial, iclass 27, count 0 2006.169.08:00:15.48#ibcon#enter sib2, iclass 27, count 0 2006.169.08:00:15.48#ibcon#flushed, iclass 27, count 0 2006.169.08:00:15.48#ibcon#about to write, iclass 27, count 0 2006.169.08:00:15.48#ibcon#wrote, iclass 27, count 0 2006.169.08:00:15.48#ibcon#about to read 3, iclass 27, count 0 2006.169.08:00:15.50#ibcon#read 3, iclass 27, count 0 2006.169.08:00:15.50#ibcon#about to read 4, iclass 27, count 0 2006.169.08:00:15.50#ibcon#read 4, iclass 27, count 0 2006.169.08:00:15.50#ibcon#about to read 5, iclass 27, count 0 2006.169.08:00:15.50#ibcon#read 5, iclass 27, count 0 2006.169.08:00:15.50#ibcon#about to read 6, iclass 27, count 0 2006.169.08:00:15.50#ibcon#read 6, iclass 27, count 0 2006.169.08:00:15.50#ibcon#end of sib2, iclass 27, count 0 2006.169.08:00:15.50#ibcon#*mode == 0, iclass 27, count 0 2006.169.08:00:15.50#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.169.08:00:15.50#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.08:00:15.50#ibcon#*before write, iclass 27, count 0 2006.169.08:00:15.50#ibcon#enter sib2, iclass 27, count 0 2006.169.08:00:15.50#ibcon#flushed, iclass 27, count 0 2006.169.08:00:15.50#ibcon#about to write, iclass 27, count 0 2006.169.08:00:15.50#ibcon#wrote, iclass 27, count 0 2006.169.08:00:15.50#ibcon#about to read 3, iclass 27, count 0 2006.169.08:00:15.54#ibcon#read 3, iclass 27, count 0 2006.169.08:00:15.54#ibcon#about to read 4, iclass 27, count 0 2006.169.08:00:15.54#ibcon#read 4, iclass 27, count 0 2006.169.08:00:15.54#ibcon#about to read 5, iclass 27, count 0 2006.169.08:00:15.54#ibcon#read 5, iclass 27, count 0 2006.169.08:00:15.54#ibcon#about to read 6, iclass 27, count 0 2006.169.08:00:15.54#ibcon#read 6, iclass 27, count 0 2006.169.08:00:15.54#ibcon#end of sib2, iclass 27, count 0 2006.169.08:00:15.54#ibcon#*after write, iclass 27, count 0 2006.169.08:00:15.54#ibcon#*before return 0, iclass 27, count 0 2006.169.08:00:15.54#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:00:15.54#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:00:15.54#ibcon#about to clear, iclass 27 cls_cnt 0 2006.169.08:00:15.54#ibcon#cleared, iclass 27 cls_cnt 0 2006.169.08:00:15.54$vc4f8/va=3,6 2006.169.08:00:15.54#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.169.08:00:15.54#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.169.08:00:15.54#ibcon#ireg 11 cls_cnt 2 2006.169.08:00:15.54#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:00:15.60#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:00:15.60#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:00:15.60#ibcon#enter wrdev, iclass 29, count 2 2006.169.08:00:15.60#ibcon#first serial, iclass 29, count 2 2006.169.08:00:15.60#ibcon#enter sib2, iclass 29, count 2 2006.169.08:00:15.60#ibcon#flushed, iclass 29, count 2 2006.169.08:00:15.60#ibcon#about to write, iclass 29, count 2 2006.169.08:00:15.60#ibcon#wrote, iclass 29, count 2 2006.169.08:00:15.60#ibcon#about to read 3, iclass 29, count 2 2006.169.08:00:15.62#ibcon#read 3, iclass 29, count 2 2006.169.08:00:15.62#ibcon#about to read 4, iclass 29, count 2 2006.169.08:00:15.62#ibcon#read 4, iclass 29, count 2 2006.169.08:00:15.62#ibcon#about to read 5, iclass 29, count 2 2006.169.08:00:15.62#ibcon#read 5, iclass 29, count 2 2006.169.08:00:15.62#ibcon#about to read 6, iclass 29, count 2 2006.169.08:00:15.62#ibcon#read 6, iclass 29, count 2 2006.169.08:00:15.62#ibcon#end of sib2, iclass 29, count 2 2006.169.08:00:15.62#ibcon#*mode == 0, iclass 29, count 2 2006.169.08:00:15.62#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.169.08:00:15.62#ibcon#[25=AT03-06\r\n] 2006.169.08:00:15.62#ibcon#*before write, iclass 29, count 2 2006.169.08:00:15.62#ibcon#enter sib2, iclass 29, count 2 2006.169.08:00:15.62#ibcon#flushed, iclass 29, count 2 2006.169.08:00:15.62#ibcon#about to write, iclass 29, count 2 2006.169.08:00:15.62#ibcon#wrote, iclass 29, count 2 2006.169.08:00:15.62#ibcon#about to read 3, iclass 29, count 2 2006.169.08:00:15.65#ibcon#read 3, iclass 29, count 2 2006.169.08:00:15.65#ibcon#about to read 4, iclass 29, count 2 2006.169.08:00:15.65#ibcon#read 4, iclass 29, count 2 2006.169.08:00:15.65#ibcon#about to read 5, iclass 29, count 2 2006.169.08:00:15.65#ibcon#read 5, iclass 29, count 2 2006.169.08:00:15.65#ibcon#about to read 6, iclass 29, count 2 2006.169.08:00:15.65#ibcon#read 6, iclass 29, count 2 2006.169.08:00:15.65#ibcon#end of sib2, iclass 29, count 2 2006.169.08:00:15.65#ibcon#*after write, iclass 29, count 2 2006.169.08:00:15.65#ibcon#*before return 0, iclass 29, count 2 2006.169.08:00:15.65#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:00:15.65#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:00:15.65#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.169.08:00:15.65#ibcon#ireg 7 cls_cnt 0 2006.169.08:00:15.65#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:00:15.77#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:00:15.77#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:00:15.77#ibcon#enter wrdev, iclass 29, count 0 2006.169.08:00:15.77#ibcon#first serial, iclass 29, count 0 2006.169.08:00:15.77#ibcon#enter sib2, iclass 29, count 0 2006.169.08:00:15.77#ibcon#flushed, iclass 29, count 0 2006.169.08:00:15.77#ibcon#about to write, iclass 29, count 0 2006.169.08:00:15.77#ibcon#wrote, iclass 29, count 0 2006.169.08:00:15.77#ibcon#about to read 3, iclass 29, count 0 2006.169.08:00:15.79#ibcon#read 3, iclass 29, count 0 2006.169.08:00:15.79#ibcon#about to read 4, iclass 29, count 0 2006.169.08:00:15.79#ibcon#read 4, iclass 29, count 0 2006.169.08:00:15.79#ibcon#about to read 5, iclass 29, count 0 2006.169.08:00:15.79#ibcon#read 5, iclass 29, count 0 2006.169.08:00:15.79#ibcon#about to read 6, iclass 29, count 0 2006.169.08:00:15.79#ibcon#read 6, iclass 29, count 0 2006.169.08:00:15.79#ibcon#end of sib2, iclass 29, count 0 2006.169.08:00:15.79#ibcon#*mode == 0, iclass 29, count 0 2006.169.08:00:15.79#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.169.08:00:15.79#ibcon#[25=USB\r\n] 2006.169.08:00:15.79#ibcon#*before write, iclass 29, count 0 2006.169.08:00:15.79#ibcon#enter sib2, iclass 29, count 0 2006.169.08:00:15.79#ibcon#flushed, iclass 29, count 0 2006.169.08:00:15.79#ibcon#about to write, iclass 29, count 0 2006.169.08:00:15.79#ibcon#wrote, iclass 29, count 0 2006.169.08:00:15.79#ibcon#about to read 3, iclass 29, count 0 2006.169.08:00:15.82#ibcon#read 3, iclass 29, count 0 2006.169.08:00:15.82#ibcon#about to read 4, iclass 29, count 0 2006.169.08:00:15.82#ibcon#read 4, iclass 29, count 0 2006.169.08:00:15.82#ibcon#about to read 5, iclass 29, count 0 2006.169.08:00:15.82#ibcon#read 5, iclass 29, count 0 2006.169.08:00:15.82#ibcon#about to read 6, iclass 29, count 0 2006.169.08:00:15.82#ibcon#read 6, iclass 29, count 0 2006.169.08:00:15.82#ibcon#end of sib2, iclass 29, count 0 2006.169.08:00:15.82#ibcon#*after write, iclass 29, count 0 2006.169.08:00:15.82#ibcon#*before return 0, iclass 29, count 0 2006.169.08:00:15.82#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:00:15.82#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:00:15.82#ibcon#about to clear, iclass 29 cls_cnt 0 2006.169.08:00:15.82#ibcon#cleared, iclass 29 cls_cnt 0 2006.169.08:00:15.82$vc4f8/valo=4,832.99 2006.169.08:00:15.82#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.169.08:00:15.82#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.169.08:00:15.82#ibcon#ireg 17 cls_cnt 0 2006.169.08:00:15.82#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:00:15.82#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:00:15.82#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:00:15.82#ibcon#enter wrdev, iclass 31, count 0 2006.169.08:00:15.82#ibcon#first serial, iclass 31, count 0 2006.169.08:00:15.82#ibcon#enter sib2, iclass 31, count 0 2006.169.08:00:15.82#ibcon#flushed, iclass 31, count 0 2006.169.08:00:15.82#ibcon#about to write, iclass 31, count 0 2006.169.08:00:15.82#ibcon#wrote, iclass 31, count 0 2006.169.08:00:15.82#ibcon#about to read 3, iclass 31, count 0 2006.169.08:00:15.84#ibcon#read 3, iclass 31, count 0 2006.169.08:00:15.84#ibcon#about to read 4, iclass 31, count 0 2006.169.08:00:15.84#ibcon#read 4, iclass 31, count 0 2006.169.08:00:15.84#ibcon#about to read 5, iclass 31, count 0 2006.169.08:00:15.84#ibcon#read 5, iclass 31, count 0 2006.169.08:00:15.84#ibcon#about to read 6, iclass 31, count 0 2006.169.08:00:15.84#ibcon#read 6, iclass 31, count 0 2006.169.08:00:15.84#ibcon#end of sib2, iclass 31, count 0 2006.169.08:00:15.84#ibcon#*mode == 0, iclass 31, count 0 2006.169.08:00:15.84#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.169.08:00:15.84#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.08:00:15.84#ibcon#*before write, iclass 31, count 0 2006.169.08:00:15.84#ibcon#enter sib2, iclass 31, count 0 2006.169.08:00:15.84#ibcon#flushed, iclass 31, count 0 2006.169.08:00:15.84#ibcon#about to write, iclass 31, count 0 2006.169.08:00:15.84#ibcon#wrote, iclass 31, count 0 2006.169.08:00:15.84#ibcon#about to read 3, iclass 31, count 0 2006.169.08:00:15.88#ibcon#read 3, iclass 31, count 0 2006.169.08:00:15.88#ibcon#about to read 4, iclass 31, count 0 2006.169.08:00:15.88#ibcon#read 4, iclass 31, count 0 2006.169.08:00:15.88#ibcon#about to read 5, iclass 31, count 0 2006.169.08:00:15.88#ibcon#read 5, iclass 31, count 0 2006.169.08:00:15.88#ibcon#about to read 6, iclass 31, count 0 2006.169.08:00:15.88#ibcon#read 6, iclass 31, count 0 2006.169.08:00:15.88#ibcon#end of sib2, iclass 31, count 0 2006.169.08:00:15.88#ibcon#*after write, iclass 31, count 0 2006.169.08:00:15.88#ibcon#*before return 0, iclass 31, count 0 2006.169.08:00:15.88#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:00:15.88#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:00:15.88#ibcon#about to clear, iclass 31 cls_cnt 0 2006.169.08:00:15.88#ibcon#cleared, iclass 31 cls_cnt 0 2006.169.08:00:15.88$vc4f8/va=4,7 2006.169.08:00:15.88#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.169.08:00:15.88#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.169.08:00:15.88#ibcon#ireg 11 cls_cnt 2 2006.169.08:00:15.88#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:00:15.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:00:15.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:00:15.94#ibcon#enter wrdev, iclass 33, count 2 2006.169.08:00:15.94#ibcon#first serial, iclass 33, count 2 2006.169.08:00:15.94#ibcon#enter sib2, iclass 33, count 2 2006.169.08:00:15.94#ibcon#flushed, iclass 33, count 2 2006.169.08:00:15.94#ibcon#about to write, iclass 33, count 2 2006.169.08:00:15.94#ibcon#wrote, iclass 33, count 2 2006.169.08:00:15.94#ibcon#about to read 3, iclass 33, count 2 2006.169.08:00:15.96#ibcon#read 3, iclass 33, count 2 2006.169.08:00:15.96#ibcon#about to read 4, iclass 33, count 2 2006.169.08:00:15.96#ibcon#read 4, iclass 33, count 2 2006.169.08:00:15.96#ibcon#about to read 5, iclass 33, count 2 2006.169.08:00:15.96#ibcon#read 5, iclass 33, count 2 2006.169.08:00:15.96#ibcon#about to read 6, iclass 33, count 2 2006.169.08:00:15.96#ibcon#read 6, iclass 33, count 2 2006.169.08:00:15.96#ibcon#end of sib2, iclass 33, count 2 2006.169.08:00:15.96#ibcon#*mode == 0, iclass 33, count 2 2006.169.08:00:15.96#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.169.08:00:15.96#ibcon#[25=AT04-07\r\n] 2006.169.08:00:15.96#ibcon#*before write, iclass 33, count 2 2006.169.08:00:15.96#ibcon#enter sib2, iclass 33, count 2 2006.169.08:00:15.96#ibcon#flushed, iclass 33, count 2 2006.169.08:00:15.96#ibcon#about to write, iclass 33, count 2 2006.169.08:00:15.96#ibcon#wrote, iclass 33, count 2 2006.169.08:00:15.96#ibcon#about to read 3, iclass 33, count 2 2006.169.08:00:15.99#ibcon#read 3, iclass 33, count 2 2006.169.08:00:15.99#ibcon#about to read 4, iclass 33, count 2 2006.169.08:00:15.99#ibcon#read 4, iclass 33, count 2 2006.169.08:00:15.99#ibcon#about to read 5, iclass 33, count 2 2006.169.08:00:15.99#ibcon#read 5, iclass 33, count 2 2006.169.08:00:15.99#ibcon#about to read 6, iclass 33, count 2 2006.169.08:00:15.99#ibcon#read 6, iclass 33, count 2 2006.169.08:00:15.99#ibcon#end of sib2, iclass 33, count 2 2006.169.08:00:15.99#ibcon#*after write, iclass 33, count 2 2006.169.08:00:15.99#ibcon#*before return 0, iclass 33, count 2 2006.169.08:00:15.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:00:15.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:00:15.99#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.169.08:00:15.99#ibcon#ireg 7 cls_cnt 0 2006.169.08:00:15.99#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:00:16.11#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:00:16.11#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:00:16.11#ibcon#enter wrdev, iclass 33, count 0 2006.169.08:00:16.11#ibcon#first serial, iclass 33, count 0 2006.169.08:00:16.11#ibcon#enter sib2, iclass 33, count 0 2006.169.08:00:16.11#ibcon#flushed, iclass 33, count 0 2006.169.08:00:16.11#ibcon#about to write, iclass 33, count 0 2006.169.08:00:16.11#ibcon#wrote, iclass 33, count 0 2006.169.08:00:16.11#ibcon#about to read 3, iclass 33, count 0 2006.169.08:00:16.13#ibcon#read 3, iclass 33, count 0 2006.169.08:00:16.13#ibcon#about to read 4, iclass 33, count 0 2006.169.08:00:16.13#ibcon#read 4, iclass 33, count 0 2006.169.08:00:16.13#ibcon#about to read 5, iclass 33, count 0 2006.169.08:00:16.13#ibcon#read 5, iclass 33, count 0 2006.169.08:00:16.13#ibcon#about to read 6, iclass 33, count 0 2006.169.08:00:16.13#ibcon#read 6, iclass 33, count 0 2006.169.08:00:16.13#ibcon#end of sib2, iclass 33, count 0 2006.169.08:00:16.13#ibcon#*mode == 0, iclass 33, count 0 2006.169.08:00:16.13#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.169.08:00:16.13#ibcon#[25=USB\r\n] 2006.169.08:00:16.13#ibcon#*before write, iclass 33, count 0 2006.169.08:00:16.13#ibcon#enter sib2, iclass 33, count 0 2006.169.08:00:16.13#ibcon#flushed, iclass 33, count 0 2006.169.08:00:16.13#ibcon#about to write, iclass 33, count 0 2006.169.08:00:16.13#ibcon#wrote, iclass 33, count 0 2006.169.08:00:16.13#ibcon#about to read 3, iclass 33, count 0 2006.169.08:00:16.16#ibcon#read 3, iclass 33, count 0 2006.169.08:00:16.16#ibcon#about to read 4, iclass 33, count 0 2006.169.08:00:16.16#ibcon#read 4, iclass 33, count 0 2006.169.08:00:16.16#ibcon#about to read 5, iclass 33, count 0 2006.169.08:00:16.16#ibcon#read 5, iclass 33, count 0 2006.169.08:00:16.16#ibcon#about to read 6, iclass 33, count 0 2006.169.08:00:16.16#ibcon#read 6, iclass 33, count 0 2006.169.08:00:16.16#ibcon#end of sib2, iclass 33, count 0 2006.169.08:00:16.16#ibcon#*after write, iclass 33, count 0 2006.169.08:00:16.16#ibcon#*before return 0, iclass 33, count 0 2006.169.08:00:16.16#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:00:16.16#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:00:16.16#ibcon#about to clear, iclass 33 cls_cnt 0 2006.169.08:00:16.16#ibcon#cleared, iclass 33 cls_cnt 0 2006.169.08:00:16.16$vc4f8/valo=5,652.99 2006.169.08:00:16.16#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.169.08:00:16.16#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.169.08:00:16.16#ibcon#ireg 17 cls_cnt 0 2006.169.08:00:16.16#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:00:16.16#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:00:16.16#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:00:16.16#ibcon#enter wrdev, iclass 35, count 0 2006.169.08:00:16.16#ibcon#first serial, iclass 35, count 0 2006.169.08:00:16.16#ibcon#enter sib2, iclass 35, count 0 2006.169.08:00:16.16#ibcon#flushed, iclass 35, count 0 2006.169.08:00:16.16#ibcon#about to write, iclass 35, count 0 2006.169.08:00:16.16#ibcon#wrote, iclass 35, count 0 2006.169.08:00:16.16#ibcon#about to read 3, iclass 35, count 0 2006.169.08:00:16.18#ibcon#read 3, iclass 35, count 0 2006.169.08:00:16.18#ibcon#about to read 4, iclass 35, count 0 2006.169.08:00:16.18#ibcon#read 4, iclass 35, count 0 2006.169.08:00:16.18#ibcon#about to read 5, iclass 35, count 0 2006.169.08:00:16.18#ibcon#read 5, iclass 35, count 0 2006.169.08:00:16.18#ibcon#about to read 6, iclass 35, count 0 2006.169.08:00:16.18#ibcon#read 6, iclass 35, count 0 2006.169.08:00:16.18#ibcon#end of sib2, iclass 35, count 0 2006.169.08:00:16.18#ibcon#*mode == 0, iclass 35, count 0 2006.169.08:00:16.18#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.169.08:00:16.18#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.08:00:16.18#ibcon#*before write, iclass 35, count 0 2006.169.08:00:16.18#ibcon#enter sib2, iclass 35, count 0 2006.169.08:00:16.18#ibcon#flushed, iclass 35, count 0 2006.169.08:00:16.18#ibcon#about to write, iclass 35, count 0 2006.169.08:00:16.18#ibcon#wrote, iclass 35, count 0 2006.169.08:00:16.18#ibcon#about to read 3, iclass 35, count 0 2006.169.08:00:16.22#ibcon#read 3, iclass 35, count 0 2006.169.08:00:16.22#ibcon#about to read 4, iclass 35, count 0 2006.169.08:00:16.22#ibcon#read 4, iclass 35, count 0 2006.169.08:00:16.22#ibcon#about to read 5, iclass 35, count 0 2006.169.08:00:16.22#ibcon#read 5, iclass 35, count 0 2006.169.08:00:16.22#ibcon#about to read 6, iclass 35, count 0 2006.169.08:00:16.22#ibcon#read 6, iclass 35, count 0 2006.169.08:00:16.22#ibcon#end of sib2, iclass 35, count 0 2006.169.08:00:16.22#ibcon#*after write, iclass 35, count 0 2006.169.08:00:16.22#ibcon#*before return 0, iclass 35, count 0 2006.169.08:00:16.22#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:00:16.22#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:00:16.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.169.08:00:16.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.169.08:00:16.22$vc4f8/va=5,7 2006.169.08:00:16.22#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.169.08:00:16.22#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.169.08:00:16.22#ibcon#ireg 11 cls_cnt 2 2006.169.08:00:16.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:00:16.28#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:00:16.28#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:00:16.28#ibcon#enter wrdev, iclass 37, count 2 2006.169.08:00:16.28#ibcon#first serial, iclass 37, count 2 2006.169.08:00:16.28#ibcon#enter sib2, iclass 37, count 2 2006.169.08:00:16.28#ibcon#flushed, iclass 37, count 2 2006.169.08:00:16.28#ibcon#about to write, iclass 37, count 2 2006.169.08:00:16.28#ibcon#wrote, iclass 37, count 2 2006.169.08:00:16.28#ibcon#about to read 3, iclass 37, count 2 2006.169.08:00:16.30#ibcon#read 3, iclass 37, count 2 2006.169.08:00:16.30#ibcon#about to read 4, iclass 37, count 2 2006.169.08:00:16.30#ibcon#read 4, iclass 37, count 2 2006.169.08:00:16.30#ibcon#about to read 5, iclass 37, count 2 2006.169.08:00:16.30#ibcon#read 5, iclass 37, count 2 2006.169.08:00:16.30#ibcon#about to read 6, iclass 37, count 2 2006.169.08:00:16.30#ibcon#read 6, iclass 37, count 2 2006.169.08:00:16.30#ibcon#end of sib2, iclass 37, count 2 2006.169.08:00:16.30#ibcon#*mode == 0, iclass 37, count 2 2006.169.08:00:16.30#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.169.08:00:16.30#ibcon#[25=AT05-07\r\n] 2006.169.08:00:16.30#ibcon#*before write, iclass 37, count 2 2006.169.08:00:16.30#ibcon#enter sib2, iclass 37, count 2 2006.169.08:00:16.30#ibcon#flushed, iclass 37, count 2 2006.169.08:00:16.30#ibcon#about to write, iclass 37, count 2 2006.169.08:00:16.30#ibcon#wrote, iclass 37, count 2 2006.169.08:00:16.30#ibcon#about to read 3, iclass 37, count 2 2006.169.08:00:16.33#ibcon#read 3, iclass 37, count 2 2006.169.08:00:16.33#ibcon#about to read 4, iclass 37, count 2 2006.169.08:00:16.33#ibcon#read 4, iclass 37, count 2 2006.169.08:00:16.33#ibcon#about to read 5, iclass 37, count 2 2006.169.08:00:16.33#ibcon#read 5, iclass 37, count 2 2006.169.08:00:16.33#ibcon#about to read 6, iclass 37, count 2 2006.169.08:00:16.33#ibcon#read 6, iclass 37, count 2 2006.169.08:00:16.33#ibcon#end of sib2, iclass 37, count 2 2006.169.08:00:16.33#ibcon#*after write, iclass 37, count 2 2006.169.08:00:16.33#ibcon#*before return 0, iclass 37, count 2 2006.169.08:00:16.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:00:16.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:00:16.33#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.169.08:00:16.33#ibcon#ireg 7 cls_cnt 0 2006.169.08:00:16.33#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:00:16.45#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:00:16.45#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:00:16.45#ibcon#enter wrdev, iclass 37, count 0 2006.169.08:00:16.45#ibcon#first serial, iclass 37, count 0 2006.169.08:00:16.45#ibcon#enter sib2, iclass 37, count 0 2006.169.08:00:16.45#ibcon#flushed, iclass 37, count 0 2006.169.08:00:16.45#ibcon#about to write, iclass 37, count 0 2006.169.08:00:16.45#ibcon#wrote, iclass 37, count 0 2006.169.08:00:16.45#ibcon#about to read 3, iclass 37, count 0 2006.169.08:00:16.47#ibcon#read 3, iclass 37, count 0 2006.169.08:00:16.47#ibcon#about to read 4, iclass 37, count 0 2006.169.08:00:16.47#ibcon#read 4, iclass 37, count 0 2006.169.08:00:16.47#ibcon#about to read 5, iclass 37, count 0 2006.169.08:00:16.47#ibcon#read 5, iclass 37, count 0 2006.169.08:00:16.47#ibcon#about to read 6, iclass 37, count 0 2006.169.08:00:16.47#ibcon#read 6, iclass 37, count 0 2006.169.08:00:16.47#ibcon#end of sib2, iclass 37, count 0 2006.169.08:00:16.47#ibcon#*mode == 0, iclass 37, count 0 2006.169.08:00:16.47#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.169.08:00:16.47#ibcon#[25=USB\r\n] 2006.169.08:00:16.47#ibcon#*before write, iclass 37, count 0 2006.169.08:00:16.47#ibcon#enter sib2, iclass 37, count 0 2006.169.08:00:16.47#ibcon#flushed, iclass 37, count 0 2006.169.08:00:16.47#ibcon#about to write, iclass 37, count 0 2006.169.08:00:16.47#ibcon#wrote, iclass 37, count 0 2006.169.08:00:16.47#ibcon#about to read 3, iclass 37, count 0 2006.169.08:00:16.50#ibcon#read 3, iclass 37, count 0 2006.169.08:00:16.50#ibcon#about to read 4, iclass 37, count 0 2006.169.08:00:16.50#ibcon#read 4, iclass 37, count 0 2006.169.08:00:16.50#ibcon#about to read 5, iclass 37, count 0 2006.169.08:00:16.50#ibcon#read 5, iclass 37, count 0 2006.169.08:00:16.50#ibcon#about to read 6, iclass 37, count 0 2006.169.08:00:16.50#ibcon#read 6, iclass 37, count 0 2006.169.08:00:16.50#ibcon#end of sib2, iclass 37, count 0 2006.169.08:00:16.50#ibcon#*after write, iclass 37, count 0 2006.169.08:00:16.50#ibcon#*before return 0, iclass 37, count 0 2006.169.08:00:16.50#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:00:16.50#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:00:16.50#ibcon#about to clear, iclass 37 cls_cnt 0 2006.169.08:00:16.50#ibcon#cleared, iclass 37 cls_cnt 0 2006.169.08:00:16.50$vc4f8/valo=6,772.99 2006.169.08:00:16.50#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.169.08:00:16.50#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.169.08:00:16.50#ibcon#ireg 17 cls_cnt 0 2006.169.08:00:16.50#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:00:16.50#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:00:16.50#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:00:16.50#ibcon#enter wrdev, iclass 39, count 0 2006.169.08:00:16.50#ibcon#first serial, iclass 39, count 0 2006.169.08:00:16.50#ibcon#enter sib2, iclass 39, count 0 2006.169.08:00:16.50#ibcon#flushed, iclass 39, count 0 2006.169.08:00:16.50#ibcon#about to write, iclass 39, count 0 2006.169.08:00:16.50#ibcon#wrote, iclass 39, count 0 2006.169.08:00:16.50#ibcon#about to read 3, iclass 39, count 0 2006.169.08:00:16.52#ibcon#read 3, iclass 39, count 0 2006.169.08:00:16.52#ibcon#about to read 4, iclass 39, count 0 2006.169.08:00:16.52#ibcon#read 4, iclass 39, count 0 2006.169.08:00:16.52#ibcon#about to read 5, iclass 39, count 0 2006.169.08:00:16.52#ibcon#read 5, iclass 39, count 0 2006.169.08:00:16.52#ibcon#about to read 6, iclass 39, count 0 2006.169.08:00:16.52#ibcon#read 6, iclass 39, count 0 2006.169.08:00:16.52#ibcon#end of sib2, iclass 39, count 0 2006.169.08:00:16.52#ibcon#*mode == 0, iclass 39, count 0 2006.169.08:00:16.52#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.169.08:00:16.52#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.08:00:16.52#ibcon#*before write, iclass 39, count 0 2006.169.08:00:16.52#ibcon#enter sib2, iclass 39, count 0 2006.169.08:00:16.52#ibcon#flushed, iclass 39, count 0 2006.169.08:00:16.52#ibcon#about to write, iclass 39, count 0 2006.169.08:00:16.52#ibcon#wrote, iclass 39, count 0 2006.169.08:00:16.52#ibcon#about to read 3, iclass 39, count 0 2006.169.08:00:16.56#ibcon#read 3, iclass 39, count 0 2006.169.08:00:16.56#ibcon#about to read 4, iclass 39, count 0 2006.169.08:00:16.56#ibcon#read 4, iclass 39, count 0 2006.169.08:00:16.56#ibcon#about to read 5, iclass 39, count 0 2006.169.08:00:16.56#ibcon#read 5, iclass 39, count 0 2006.169.08:00:16.56#ibcon#about to read 6, iclass 39, count 0 2006.169.08:00:16.56#ibcon#read 6, iclass 39, count 0 2006.169.08:00:16.56#ibcon#end of sib2, iclass 39, count 0 2006.169.08:00:16.56#ibcon#*after write, iclass 39, count 0 2006.169.08:00:16.56#ibcon#*before return 0, iclass 39, count 0 2006.169.08:00:16.56#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:00:16.56#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:00:16.56#ibcon#about to clear, iclass 39 cls_cnt 0 2006.169.08:00:16.56#ibcon#cleared, iclass 39 cls_cnt 0 2006.169.08:00:16.56$vc4f8/va=6,6 2006.169.08:00:16.56#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.169.08:00:16.56#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.169.08:00:16.56#ibcon#ireg 11 cls_cnt 2 2006.169.08:00:16.56#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:00:16.62#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:00:16.62#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:00:16.62#ibcon#enter wrdev, iclass 3, count 2 2006.169.08:00:16.62#ibcon#first serial, iclass 3, count 2 2006.169.08:00:16.62#ibcon#enter sib2, iclass 3, count 2 2006.169.08:00:16.62#ibcon#flushed, iclass 3, count 2 2006.169.08:00:16.62#ibcon#about to write, iclass 3, count 2 2006.169.08:00:16.62#ibcon#wrote, iclass 3, count 2 2006.169.08:00:16.62#ibcon#about to read 3, iclass 3, count 2 2006.169.08:00:16.64#ibcon#read 3, iclass 3, count 2 2006.169.08:00:16.64#ibcon#about to read 4, iclass 3, count 2 2006.169.08:00:16.64#ibcon#read 4, iclass 3, count 2 2006.169.08:00:16.64#ibcon#about to read 5, iclass 3, count 2 2006.169.08:00:16.64#ibcon#read 5, iclass 3, count 2 2006.169.08:00:16.64#ibcon#about to read 6, iclass 3, count 2 2006.169.08:00:16.64#ibcon#read 6, iclass 3, count 2 2006.169.08:00:16.64#ibcon#end of sib2, iclass 3, count 2 2006.169.08:00:16.64#ibcon#*mode == 0, iclass 3, count 2 2006.169.08:00:16.64#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.169.08:00:16.64#ibcon#[25=AT06-06\r\n] 2006.169.08:00:16.64#ibcon#*before write, iclass 3, count 2 2006.169.08:00:16.64#ibcon#enter sib2, iclass 3, count 2 2006.169.08:00:16.64#ibcon#flushed, iclass 3, count 2 2006.169.08:00:16.64#ibcon#about to write, iclass 3, count 2 2006.169.08:00:16.64#ibcon#wrote, iclass 3, count 2 2006.169.08:00:16.64#ibcon#about to read 3, iclass 3, count 2 2006.169.08:00:16.67#ibcon#read 3, iclass 3, count 2 2006.169.08:00:16.67#ibcon#about to read 4, iclass 3, count 2 2006.169.08:00:16.67#ibcon#read 4, iclass 3, count 2 2006.169.08:00:16.67#ibcon#about to read 5, iclass 3, count 2 2006.169.08:00:16.67#ibcon#read 5, iclass 3, count 2 2006.169.08:00:16.67#ibcon#about to read 6, iclass 3, count 2 2006.169.08:00:16.67#ibcon#read 6, iclass 3, count 2 2006.169.08:00:16.67#ibcon#end of sib2, iclass 3, count 2 2006.169.08:00:16.67#ibcon#*after write, iclass 3, count 2 2006.169.08:00:16.67#ibcon#*before return 0, iclass 3, count 2 2006.169.08:00:16.67#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:00:16.67#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:00:16.67#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.169.08:00:16.67#ibcon#ireg 7 cls_cnt 0 2006.169.08:00:16.67#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:00:16.79#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:00:16.79#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:00:16.79#ibcon#enter wrdev, iclass 3, count 0 2006.169.08:00:16.79#ibcon#first serial, iclass 3, count 0 2006.169.08:00:16.79#ibcon#enter sib2, iclass 3, count 0 2006.169.08:00:16.79#ibcon#flushed, iclass 3, count 0 2006.169.08:00:16.79#ibcon#about to write, iclass 3, count 0 2006.169.08:00:16.79#ibcon#wrote, iclass 3, count 0 2006.169.08:00:16.79#ibcon#about to read 3, iclass 3, count 0 2006.169.08:00:16.81#ibcon#read 3, iclass 3, count 0 2006.169.08:00:16.81#ibcon#about to read 4, iclass 3, count 0 2006.169.08:00:16.81#ibcon#read 4, iclass 3, count 0 2006.169.08:00:16.81#ibcon#about to read 5, iclass 3, count 0 2006.169.08:00:16.81#ibcon#read 5, iclass 3, count 0 2006.169.08:00:16.81#ibcon#about to read 6, iclass 3, count 0 2006.169.08:00:16.81#ibcon#read 6, iclass 3, count 0 2006.169.08:00:16.81#ibcon#end of sib2, iclass 3, count 0 2006.169.08:00:16.81#ibcon#*mode == 0, iclass 3, count 0 2006.169.08:00:16.81#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.169.08:00:16.81#ibcon#[25=USB\r\n] 2006.169.08:00:16.81#ibcon#*before write, iclass 3, count 0 2006.169.08:00:16.81#ibcon#enter sib2, iclass 3, count 0 2006.169.08:00:16.81#ibcon#flushed, iclass 3, count 0 2006.169.08:00:16.81#ibcon#about to write, iclass 3, count 0 2006.169.08:00:16.81#ibcon#wrote, iclass 3, count 0 2006.169.08:00:16.81#ibcon#about to read 3, iclass 3, count 0 2006.169.08:00:16.84#ibcon#read 3, iclass 3, count 0 2006.169.08:00:16.84#ibcon#about to read 4, iclass 3, count 0 2006.169.08:00:16.84#ibcon#read 4, iclass 3, count 0 2006.169.08:00:16.84#ibcon#about to read 5, iclass 3, count 0 2006.169.08:00:16.84#ibcon#read 5, iclass 3, count 0 2006.169.08:00:16.84#ibcon#about to read 6, iclass 3, count 0 2006.169.08:00:16.84#ibcon#read 6, iclass 3, count 0 2006.169.08:00:16.84#ibcon#end of sib2, iclass 3, count 0 2006.169.08:00:16.84#ibcon#*after write, iclass 3, count 0 2006.169.08:00:16.84#ibcon#*before return 0, iclass 3, count 0 2006.169.08:00:16.84#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:00:16.84#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:00:16.84#ibcon#about to clear, iclass 3 cls_cnt 0 2006.169.08:00:16.84#ibcon#cleared, iclass 3 cls_cnt 0 2006.169.08:00:16.84$vc4f8/valo=7,832.99 2006.169.08:00:16.84#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.169.08:00:16.84#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.169.08:00:16.84#ibcon#ireg 17 cls_cnt 0 2006.169.08:00:16.84#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:00:16.84#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:00:16.84#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:00:16.84#ibcon#enter wrdev, iclass 5, count 0 2006.169.08:00:16.84#ibcon#first serial, iclass 5, count 0 2006.169.08:00:16.84#ibcon#enter sib2, iclass 5, count 0 2006.169.08:00:16.84#ibcon#flushed, iclass 5, count 0 2006.169.08:00:16.84#ibcon#about to write, iclass 5, count 0 2006.169.08:00:16.84#ibcon#wrote, iclass 5, count 0 2006.169.08:00:16.84#ibcon#about to read 3, iclass 5, count 0 2006.169.08:00:16.86#ibcon#read 3, iclass 5, count 0 2006.169.08:00:16.86#ibcon#about to read 4, iclass 5, count 0 2006.169.08:00:16.86#ibcon#read 4, iclass 5, count 0 2006.169.08:00:16.86#ibcon#about to read 5, iclass 5, count 0 2006.169.08:00:16.86#ibcon#read 5, iclass 5, count 0 2006.169.08:00:16.86#ibcon#about to read 6, iclass 5, count 0 2006.169.08:00:16.86#ibcon#read 6, iclass 5, count 0 2006.169.08:00:16.86#ibcon#end of sib2, iclass 5, count 0 2006.169.08:00:16.86#ibcon#*mode == 0, iclass 5, count 0 2006.169.08:00:16.86#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.169.08:00:16.86#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.08:00:16.86#ibcon#*before write, iclass 5, count 0 2006.169.08:00:16.86#ibcon#enter sib2, iclass 5, count 0 2006.169.08:00:16.86#ibcon#flushed, iclass 5, count 0 2006.169.08:00:16.86#ibcon#about to write, iclass 5, count 0 2006.169.08:00:16.86#ibcon#wrote, iclass 5, count 0 2006.169.08:00:16.86#ibcon#about to read 3, iclass 5, count 0 2006.169.08:00:16.90#ibcon#read 3, iclass 5, count 0 2006.169.08:00:16.90#ibcon#about to read 4, iclass 5, count 0 2006.169.08:00:16.90#ibcon#read 4, iclass 5, count 0 2006.169.08:00:16.90#ibcon#about to read 5, iclass 5, count 0 2006.169.08:00:16.90#ibcon#read 5, iclass 5, count 0 2006.169.08:00:16.90#ibcon#about to read 6, iclass 5, count 0 2006.169.08:00:16.90#ibcon#read 6, iclass 5, count 0 2006.169.08:00:16.90#ibcon#end of sib2, iclass 5, count 0 2006.169.08:00:16.90#ibcon#*after write, iclass 5, count 0 2006.169.08:00:16.90#ibcon#*before return 0, iclass 5, count 0 2006.169.08:00:16.90#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:00:16.90#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:00:16.90#ibcon#about to clear, iclass 5 cls_cnt 0 2006.169.08:00:16.90#ibcon#cleared, iclass 5 cls_cnt 0 2006.169.08:00:16.90$vc4f8/va=7,6 2006.169.08:00:16.90#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.169.08:00:16.90#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.169.08:00:16.90#ibcon#ireg 11 cls_cnt 2 2006.169.08:00:16.90#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:00:16.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:00:16.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:00:16.96#ibcon#enter wrdev, iclass 7, count 2 2006.169.08:00:16.96#ibcon#first serial, iclass 7, count 2 2006.169.08:00:16.96#ibcon#enter sib2, iclass 7, count 2 2006.169.08:00:16.96#ibcon#flushed, iclass 7, count 2 2006.169.08:00:16.96#ibcon#about to write, iclass 7, count 2 2006.169.08:00:16.96#ibcon#wrote, iclass 7, count 2 2006.169.08:00:16.96#ibcon#about to read 3, iclass 7, count 2 2006.169.08:00:16.98#ibcon#read 3, iclass 7, count 2 2006.169.08:00:16.98#ibcon#about to read 4, iclass 7, count 2 2006.169.08:00:16.98#ibcon#read 4, iclass 7, count 2 2006.169.08:00:16.98#ibcon#about to read 5, iclass 7, count 2 2006.169.08:00:16.98#ibcon#read 5, iclass 7, count 2 2006.169.08:00:16.98#ibcon#about to read 6, iclass 7, count 2 2006.169.08:00:16.98#ibcon#read 6, iclass 7, count 2 2006.169.08:00:16.98#ibcon#end of sib2, iclass 7, count 2 2006.169.08:00:16.98#ibcon#*mode == 0, iclass 7, count 2 2006.169.08:00:16.98#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.169.08:00:16.98#ibcon#[25=AT07-06\r\n] 2006.169.08:00:16.98#ibcon#*before write, iclass 7, count 2 2006.169.08:00:16.98#ibcon#enter sib2, iclass 7, count 2 2006.169.08:00:16.98#ibcon#flushed, iclass 7, count 2 2006.169.08:00:16.98#ibcon#about to write, iclass 7, count 2 2006.169.08:00:16.98#ibcon#wrote, iclass 7, count 2 2006.169.08:00:16.98#ibcon#about to read 3, iclass 7, count 2 2006.169.08:00:17.01#ibcon#read 3, iclass 7, count 2 2006.169.08:00:17.01#ibcon#about to read 4, iclass 7, count 2 2006.169.08:00:17.01#ibcon#read 4, iclass 7, count 2 2006.169.08:00:17.01#ibcon#about to read 5, iclass 7, count 2 2006.169.08:00:17.01#ibcon#read 5, iclass 7, count 2 2006.169.08:00:17.01#ibcon#about to read 6, iclass 7, count 2 2006.169.08:00:17.01#ibcon#read 6, iclass 7, count 2 2006.169.08:00:17.01#ibcon#end of sib2, iclass 7, count 2 2006.169.08:00:17.01#ibcon#*after write, iclass 7, count 2 2006.169.08:00:17.01#ibcon#*before return 0, iclass 7, count 2 2006.169.08:00:17.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:00:17.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:00:17.01#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.169.08:00:17.01#ibcon#ireg 7 cls_cnt 0 2006.169.08:00:17.01#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:00:17.13#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:00:17.13#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:00:17.13#ibcon#enter wrdev, iclass 7, count 0 2006.169.08:00:17.13#ibcon#first serial, iclass 7, count 0 2006.169.08:00:17.13#ibcon#enter sib2, iclass 7, count 0 2006.169.08:00:17.13#ibcon#flushed, iclass 7, count 0 2006.169.08:00:17.13#ibcon#about to write, iclass 7, count 0 2006.169.08:00:17.13#ibcon#wrote, iclass 7, count 0 2006.169.08:00:17.13#ibcon#about to read 3, iclass 7, count 0 2006.169.08:00:17.15#ibcon#read 3, iclass 7, count 0 2006.169.08:00:17.15#ibcon#about to read 4, iclass 7, count 0 2006.169.08:00:17.15#ibcon#read 4, iclass 7, count 0 2006.169.08:00:17.15#ibcon#about to read 5, iclass 7, count 0 2006.169.08:00:17.15#ibcon#read 5, iclass 7, count 0 2006.169.08:00:17.15#ibcon#about to read 6, iclass 7, count 0 2006.169.08:00:17.15#ibcon#read 6, iclass 7, count 0 2006.169.08:00:17.15#ibcon#end of sib2, iclass 7, count 0 2006.169.08:00:17.15#ibcon#*mode == 0, iclass 7, count 0 2006.169.08:00:17.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.169.08:00:17.15#ibcon#[25=USB\r\n] 2006.169.08:00:17.15#ibcon#*before write, iclass 7, count 0 2006.169.08:00:17.15#ibcon#enter sib2, iclass 7, count 0 2006.169.08:00:17.15#ibcon#flushed, iclass 7, count 0 2006.169.08:00:17.15#ibcon#about to write, iclass 7, count 0 2006.169.08:00:17.15#ibcon#wrote, iclass 7, count 0 2006.169.08:00:17.15#ibcon#about to read 3, iclass 7, count 0 2006.169.08:00:17.18#ibcon#read 3, iclass 7, count 0 2006.169.08:00:17.18#ibcon#about to read 4, iclass 7, count 0 2006.169.08:00:17.18#ibcon#read 4, iclass 7, count 0 2006.169.08:00:17.18#ibcon#about to read 5, iclass 7, count 0 2006.169.08:00:17.18#ibcon#read 5, iclass 7, count 0 2006.169.08:00:17.18#ibcon#about to read 6, iclass 7, count 0 2006.169.08:00:17.18#ibcon#read 6, iclass 7, count 0 2006.169.08:00:17.18#ibcon#end of sib2, iclass 7, count 0 2006.169.08:00:17.18#ibcon#*after write, iclass 7, count 0 2006.169.08:00:17.18#ibcon#*before return 0, iclass 7, count 0 2006.169.08:00:17.18#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:00:17.18#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:00:17.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.169.08:00:17.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.169.08:00:17.18$vc4f8/valo=8,852.99 2006.169.08:00:17.18#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.169.08:00:17.18#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.169.08:00:17.18#ibcon#ireg 17 cls_cnt 0 2006.169.08:00:17.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:00:17.18#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:00:17.18#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:00:17.18#ibcon#enter wrdev, iclass 11, count 0 2006.169.08:00:17.18#ibcon#first serial, iclass 11, count 0 2006.169.08:00:17.18#ibcon#enter sib2, iclass 11, count 0 2006.169.08:00:17.18#ibcon#flushed, iclass 11, count 0 2006.169.08:00:17.18#ibcon#about to write, iclass 11, count 0 2006.169.08:00:17.18#ibcon#wrote, iclass 11, count 0 2006.169.08:00:17.18#ibcon#about to read 3, iclass 11, count 0 2006.169.08:00:17.20#ibcon#read 3, iclass 11, count 0 2006.169.08:00:17.20#ibcon#about to read 4, iclass 11, count 0 2006.169.08:00:17.20#ibcon#read 4, iclass 11, count 0 2006.169.08:00:17.20#ibcon#about to read 5, iclass 11, count 0 2006.169.08:00:17.20#ibcon#read 5, iclass 11, count 0 2006.169.08:00:17.20#ibcon#about to read 6, iclass 11, count 0 2006.169.08:00:17.20#ibcon#read 6, iclass 11, count 0 2006.169.08:00:17.20#ibcon#end of sib2, iclass 11, count 0 2006.169.08:00:17.20#ibcon#*mode == 0, iclass 11, count 0 2006.169.08:00:17.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.169.08:00:17.20#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.08:00:17.20#ibcon#*before write, iclass 11, count 0 2006.169.08:00:17.20#ibcon#enter sib2, iclass 11, count 0 2006.169.08:00:17.20#ibcon#flushed, iclass 11, count 0 2006.169.08:00:17.20#ibcon#about to write, iclass 11, count 0 2006.169.08:00:17.20#ibcon#wrote, iclass 11, count 0 2006.169.08:00:17.20#ibcon#about to read 3, iclass 11, count 0 2006.169.08:00:17.24#ibcon#read 3, iclass 11, count 0 2006.169.08:00:17.24#ibcon#about to read 4, iclass 11, count 0 2006.169.08:00:17.24#ibcon#read 4, iclass 11, count 0 2006.169.08:00:17.24#ibcon#about to read 5, iclass 11, count 0 2006.169.08:00:17.24#ibcon#read 5, iclass 11, count 0 2006.169.08:00:17.24#ibcon#about to read 6, iclass 11, count 0 2006.169.08:00:17.24#ibcon#read 6, iclass 11, count 0 2006.169.08:00:17.24#ibcon#end of sib2, iclass 11, count 0 2006.169.08:00:17.24#ibcon#*after write, iclass 11, count 0 2006.169.08:00:17.24#ibcon#*before return 0, iclass 11, count 0 2006.169.08:00:17.24#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:00:17.24#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:00:17.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.169.08:00:17.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.169.08:00:17.24$vc4f8/va=8,7 2006.169.08:00:17.24#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.169.08:00:17.24#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.169.08:00:17.24#ibcon#ireg 11 cls_cnt 2 2006.169.08:00:17.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:00:17.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:00:17.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:00:17.30#ibcon#enter wrdev, iclass 13, count 2 2006.169.08:00:17.30#ibcon#first serial, iclass 13, count 2 2006.169.08:00:17.30#ibcon#enter sib2, iclass 13, count 2 2006.169.08:00:17.30#ibcon#flushed, iclass 13, count 2 2006.169.08:00:17.30#ibcon#about to write, iclass 13, count 2 2006.169.08:00:17.30#ibcon#wrote, iclass 13, count 2 2006.169.08:00:17.30#ibcon#about to read 3, iclass 13, count 2 2006.169.08:00:17.32#ibcon#read 3, iclass 13, count 2 2006.169.08:00:17.32#ibcon#about to read 4, iclass 13, count 2 2006.169.08:00:17.32#ibcon#read 4, iclass 13, count 2 2006.169.08:00:17.32#ibcon#about to read 5, iclass 13, count 2 2006.169.08:00:17.32#ibcon#read 5, iclass 13, count 2 2006.169.08:00:17.32#ibcon#about to read 6, iclass 13, count 2 2006.169.08:00:17.32#ibcon#read 6, iclass 13, count 2 2006.169.08:00:17.32#ibcon#end of sib2, iclass 13, count 2 2006.169.08:00:17.32#ibcon#*mode == 0, iclass 13, count 2 2006.169.08:00:17.32#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.169.08:00:17.32#ibcon#[25=AT08-07\r\n] 2006.169.08:00:17.32#ibcon#*before write, iclass 13, count 2 2006.169.08:00:17.32#ibcon#enter sib2, iclass 13, count 2 2006.169.08:00:17.32#ibcon#flushed, iclass 13, count 2 2006.169.08:00:17.32#ibcon#about to write, iclass 13, count 2 2006.169.08:00:17.32#ibcon#wrote, iclass 13, count 2 2006.169.08:00:17.32#ibcon#about to read 3, iclass 13, count 2 2006.169.08:00:17.35#ibcon#read 3, iclass 13, count 2 2006.169.08:00:17.35#ibcon#about to read 4, iclass 13, count 2 2006.169.08:00:17.35#ibcon#read 4, iclass 13, count 2 2006.169.08:00:17.35#ibcon#about to read 5, iclass 13, count 2 2006.169.08:00:17.35#ibcon#read 5, iclass 13, count 2 2006.169.08:00:17.35#ibcon#about to read 6, iclass 13, count 2 2006.169.08:00:17.35#ibcon#read 6, iclass 13, count 2 2006.169.08:00:17.35#ibcon#end of sib2, iclass 13, count 2 2006.169.08:00:17.35#ibcon#*after write, iclass 13, count 2 2006.169.08:00:17.35#ibcon#*before return 0, iclass 13, count 2 2006.169.08:00:17.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:00:17.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:00:17.35#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.169.08:00:17.35#ibcon#ireg 7 cls_cnt 0 2006.169.08:00:17.35#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:00:17.47#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:00:17.47#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:00:17.47#ibcon#enter wrdev, iclass 13, count 0 2006.169.08:00:17.47#ibcon#first serial, iclass 13, count 0 2006.169.08:00:17.47#ibcon#enter sib2, iclass 13, count 0 2006.169.08:00:17.47#ibcon#flushed, iclass 13, count 0 2006.169.08:00:17.47#ibcon#about to write, iclass 13, count 0 2006.169.08:00:17.47#ibcon#wrote, iclass 13, count 0 2006.169.08:00:17.47#ibcon#about to read 3, iclass 13, count 0 2006.169.08:00:17.49#ibcon#read 3, iclass 13, count 0 2006.169.08:00:17.49#ibcon#about to read 4, iclass 13, count 0 2006.169.08:00:17.49#ibcon#read 4, iclass 13, count 0 2006.169.08:00:17.49#ibcon#about to read 5, iclass 13, count 0 2006.169.08:00:17.49#ibcon#read 5, iclass 13, count 0 2006.169.08:00:17.49#ibcon#about to read 6, iclass 13, count 0 2006.169.08:00:17.49#ibcon#read 6, iclass 13, count 0 2006.169.08:00:17.49#ibcon#end of sib2, iclass 13, count 0 2006.169.08:00:17.49#ibcon#*mode == 0, iclass 13, count 0 2006.169.08:00:17.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.08:00:17.49#ibcon#[25=USB\r\n] 2006.169.08:00:17.49#ibcon#*before write, iclass 13, count 0 2006.169.08:00:17.49#ibcon#enter sib2, iclass 13, count 0 2006.169.08:00:17.49#ibcon#flushed, iclass 13, count 0 2006.169.08:00:17.49#ibcon#about to write, iclass 13, count 0 2006.169.08:00:17.49#ibcon#wrote, iclass 13, count 0 2006.169.08:00:17.49#ibcon#about to read 3, iclass 13, count 0 2006.169.08:00:17.52#ibcon#read 3, iclass 13, count 0 2006.169.08:00:17.52#ibcon#about to read 4, iclass 13, count 0 2006.169.08:00:17.52#ibcon#read 4, iclass 13, count 0 2006.169.08:00:17.52#ibcon#about to read 5, iclass 13, count 0 2006.169.08:00:17.52#ibcon#read 5, iclass 13, count 0 2006.169.08:00:17.52#ibcon#about to read 6, iclass 13, count 0 2006.169.08:00:17.52#ibcon#read 6, iclass 13, count 0 2006.169.08:00:17.52#ibcon#end of sib2, iclass 13, count 0 2006.169.08:00:17.52#ibcon#*after write, iclass 13, count 0 2006.169.08:00:17.52#ibcon#*before return 0, iclass 13, count 0 2006.169.08:00:17.52#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:00:17.52#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:00:17.52#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.08:00:17.52#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.08:00:17.52$vc4f8/vblo=1,632.99 2006.169.08:00:17.52#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.169.08:00:17.52#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.169.08:00:17.52#ibcon#ireg 17 cls_cnt 0 2006.169.08:00:17.52#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:00:17.52#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:00:17.52#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:00:17.52#ibcon#enter wrdev, iclass 15, count 0 2006.169.08:00:17.52#ibcon#first serial, iclass 15, count 0 2006.169.08:00:17.52#ibcon#enter sib2, iclass 15, count 0 2006.169.08:00:17.52#ibcon#flushed, iclass 15, count 0 2006.169.08:00:17.52#ibcon#about to write, iclass 15, count 0 2006.169.08:00:17.52#ibcon#wrote, iclass 15, count 0 2006.169.08:00:17.52#ibcon#about to read 3, iclass 15, count 0 2006.169.08:00:17.54#ibcon#read 3, iclass 15, count 0 2006.169.08:00:17.54#ibcon#about to read 4, iclass 15, count 0 2006.169.08:00:17.54#ibcon#read 4, iclass 15, count 0 2006.169.08:00:17.54#ibcon#about to read 5, iclass 15, count 0 2006.169.08:00:17.54#ibcon#read 5, iclass 15, count 0 2006.169.08:00:17.54#ibcon#about to read 6, iclass 15, count 0 2006.169.08:00:17.54#ibcon#read 6, iclass 15, count 0 2006.169.08:00:17.54#ibcon#end of sib2, iclass 15, count 0 2006.169.08:00:17.54#ibcon#*mode == 0, iclass 15, count 0 2006.169.08:00:17.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.169.08:00:17.54#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.08:00:17.54#ibcon#*before write, iclass 15, count 0 2006.169.08:00:17.54#ibcon#enter sib2, iclass 15, count 0 2006.169.08:00:17.54#ibcon#flushed, iclass 15, count 0 2006.169.08:00:17.54#ibcon#about to write, iclass 15, count 0 2006.169.08:00:17.54#ibcon#wrote, iclass 15, count 0 2006.169.08:00:17.54#ibcon#about to read 3, iclass 15, count 0 2006.169.08:00:17.58#ibcon#read 3, iclass 15, count 0 2006.169.08:00:17.58#ibcon#about to read 4, iclass 15, count 0 2006.169.08:00:17.58#ibcon#read 4, iclass 15, count 0 2006.169.08:00:17.58#ibcon#about to read 5, iclass 15, count 0 2006.169.08:00:17.58#ibcon#read 5, iclass 15, count 0 2006.169.08:00:17.58#ibcon#about to read 6, iclass 15, count 0 2006.169.08:00:17.58#ibcon#read 6, iclass 15, count 0 2006.169.08:00:17.58#ibcon#end of sib2, iclass 15, count 0 2006.169.08:00:17.58#ibcon#*after write, iclass 15, count 0 2006.169.08:00:17.58#ibcon#*before return 0, iclass 15, count 0 2006.169.08:00:17.58#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:00:17.58#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:00:17.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.169.08:00:17.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.169.08:00:17.58$vc4f8/vb=1,4 2006.169.08:00:17.58#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.169.08:00:17.58#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.169.08:00:17.58#ibcon#ireg 11 cls_cnt 2 2006.169.08:00:17.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:00:17.58#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:00:17.58#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:00:17.58#ibcon#enter wrdev, iclass 17, count 2 2006.169.08:00:17.58#ibcon#first serial, iclass 17, count 2 2006.169.08:00:17.58#ibcon#enter sib2, iclass 17, count 2 2006.169.08:00:17.58#ibcon#flushed, iclass 17, count 2 2006.169.08:00:17.58#ibcon#about to write, iclass 17, count 2 2006.169.08:00:17.58#ibcon#wrote, iclass 17, count 2 2006.169.08:00:17.58#ibcon#about to read 3, iclass 17, count 2 2006.169.08:00:17.60#ibcon#read 3, iclass 17, count 2 2006.169.08:00:17.60#ibcon#about to read 4, iclass 17, count 2 2006.169.08:00:17.60#ibcon#read 4, iclass 17, count 2 2006.169.08:00:17.60#ibcon#about to read 5, iclass 17, count 2 2006.169.08:00:17.60#ibcon#read 5, iclass 17, count 2 2006.169.08:00:17.60#ibcon#about to read 6, iclass 17, count 2 2006.169.08:00:17.60#ibcon#read 6, iclass 17, count 2 2006.169.08:00:17.60#ibcon#end of sib2, iclass 17, count 2 2006.169.08:00:17.60#ibcon#*mode == 0, iclass 17, count 2 2006.169.08:00:17.60#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.169.08:00:17.60#ibcon#[27=AT01-04\r\n] 2006.169.08:00:17.60#ibcon#*before write, iclass 17, count 2 2006.169.08:00:17.60#ibcon#enter sib2, iclass 17, count 2 2006.169.08:00:17.60#ibcon#flushed, iclass 17, count 2 2006.169.08:00:17.60#ibcon#about to write, iclass 17, count 2 2006.169.08:00:17.60#ibcon#wrote, iclass 17, count 2 2006.169.08:00:17.60#ibcon#about to read 3, iclass 17, count 2 2006.169.08:00:17.63#ibcon#read 3, iclass 17, count 2 2006.169.08:00:17.63#ibcon#about to read 4, iclass 17, count 2 2006.169.08:00:17.63#ibcon#read 4, iclass 17, count 2 2006.169.08:00:17.63#ibcon#about to read 5, iclass 17, count 2 2006.169.08:00:17.63#ibcon#read 5, iclass 17, count 2 2006.169.08:00:17.63#ibcon#about to read 6, iclass 17, count 2 2006.169.08:00:17.63#ibcon#read 6, iclass 17, count 2 2006.169.08:00:17.63#ibcon#end of sib2, iclass 17, count 2 2006.169.08:00:17.63#ibcon#*after write, iclass 17, count 2 2006.169.08:00:17.63#ibcon#*before return 0, iclass 17, count 2 2006.169.08:00:17.63#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:00:17.63#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:00:17.63#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.169.08:00:17.63#ibcon#ireg 7 cls_cnt 0 2006.169.08:00:17.63#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:00:17.75#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:00:17.75#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:00:17.75#ibcon#enter wrdev, iclass 17, count 0 2006.169.08:00:17.75#ibcon#first serial, iclass 17, count 0 2006.169.08:00:17.75#ibcon#enter sib2, iclass 17, count 0 2006.169.08:00:17.75#ibcon#flushed, iclass 17, count 0 2006.169.08:00:17.75#ibcon#about to write, iclass 17, count 0 2006.169.08:00:17.75#ibcon#wrote, iclass 17, count 0 2006.169.08:00:17.75#ibcon#about to read 3, iclass 17, count 0 2006.169.08:00:17.77#ibcon#read 3, iclass 17, count 0 2006.169.08:00:17.77#ibcon#about to read 4, iclass 17, count 0 2006.169.08:00:17.77#ibcon#read 4, iclass 17, count 0 2006.169.08:00:17.77#ibcon#about to read 5, iclass 17, count 0 2006.169.08:00:17.77#ibcon#read 5, iclass 17, count 0 2006.169.08:00:17.77#ibcon#about to read 6, iclass 17, count 0 2006.169.08:00:17.77#ibcon#read 6, iclass 17, count 0 2006.169.08:00:17.77#ibcon#end of sib2, iclass 17, count 0 2006.169.08:00:17.77#ibcon#*mode == 0, iclass 17, count 0 2006.169.08:00:17.77#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.169.08:00:17.77#ibcon#[27=USB\r\n] 2006.169.08:00:17.77#ibcon#*before write, iclass 17, count 0 2006.169.08:00:17.77#ibcon#enter sib2, iclass 17, count 0 2006.169.08:00:17.77#ibcon#flushed, iclass 17, count 0 2006.169.08:00:17.77#ibcon#about to write, iclass 17, count 0 2006.169.08:00:17.77#ibcon#wrote, iclass 17, count 0 2006.169.08:00:17.77#ibcon#about to read 3, iclass 17, count 0 2006.169.08:00:17.80#ibcon#read 3, iclass 17, count 0 2006.169.08:00:17.80#ibcon#about to read 4, iclass 17, count 0 2006.169.08:00:17.80#ibcon#read 4, iclass 17, count 0 2006.169.08:00:17.80#ibcon#about to read 5, iclass 17, count 0 2006.169.08:00:17.80#ibcon#read 5, iclass 17, count 0 2006.169.08:00:17.80#ibcon#about to read 6, iclass 17, count 0 2006.169.08:00:17.80#ibcon#read 6, iclass 17, count 0 2006.169.08:00:17.80#ibcon#end of sib2, iclass 17, count 0 2006.169.08:00:17.80#ibcon#*after write, iclass 17, count 0 2006.169.08:00:17.80#ibcon#*before return 0, iclass 17, count 0 2006.169.08:00:17.80#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:00:17.80#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:00:17.80#ibcon#about to clear, iclass 17 cls_cnt 0 2006.169.08:00:17.80#ibcon#cleared, iclass 17 cls_cnt 0 2006.169.08:00:17.80$vc4f8/vblo=2,640.99 2006.169.08:00:17.80#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.169.08:00:17.80#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.169.08:00:17.80#ibcon#ireg 17 cls_cnt 0 2006.169.08:00:17.80#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.169.08:00:17.80#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.169.08:00:17.80#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.169.08:00:17.80#ibcon#enter wrdev, iclass 19, count 0 2006.169.08:00:17.80#ibcon#first serial, iclass 19, count 0 2006.169.08:00:17.80#ibcon#enter sib2, iclass 19, count 0 2006.169.08:00:17.80#ibcon#flushed, iclass 19, count 0 2006.169.08:00:17.80#ibcon#about to write, iclass 19, count 0 2006.169.08:00:17.80#ibcon#wrote, iclass 19, count 0 2006.169.08:00:17.80#ibcon#about to read 3, iclass 19, count 0 2006.169.08:00:17.82#ibcon#read 3, iclass 19, count 0 2006.169.08:00:17.82#ibcon#about to read 4, iclass 19, count 0 2006.169.08:00:17.82#ibcon#read 4, iclass 19, count 0 2006.169.08:00:17.82#ibcon#about to read 5, iclass 19, count 0 2006.169.08:00:17.82#ibcon#read 5, iclass 19, count 0 2006.169.08:00:17.82#ibcon#about to read 6, iclass 19, count 0 2006.169.08:00:17.82#ibcon#read 6, iclass 19, count 0 2006.169.08:00:17.82#ibcon#end of sib2, iclass 19, count 0 2006.169.08:00:17.82#ibcon#*mode == 0, iclass 19, count 0 2006.169.08:00:17.82#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.169.08:00:17.82#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.08:00:17.82#ibcon#*before write, iclass 19, count 0 2006.169.08:00:17.82#ibcon#enter sib2, iclass 19, count 0 2006.169.08:00:17.82#ibcon#flushed, iclass 19, count 0 2006.169.08:00:17.82#ibcon#about to write, iclass 19, count 0 2006.169.08:00:17.82#ibcon#wrote, iclass 19, count 0 2006.169.08:00:17.82#ibcon#about to read 3, iclass 19, count 0 2006.169.08:00:17.86#ibcon#read 3, iclass 19, count 0 2006.169.08:00:17.86#ibcon#about to read 4, iclass 19, count 0 2006.169.08:00:17.86#ibcon#read 4, iclass 19, count 0 2006.169.08:00:17.86#ibcon#about to read 5, iclass 19, count 0 2006.169.08:00:17.86#ibcon#read 5, iclass 19, count 0 2006.169.08:00:17.86#ibcon#about to read 6, iclass 19, count 0 2006.169.08:00:17.86#ibcon#read 6, iclass 19, count 0 2006.169.08:00:17.86#ibcon#end of sib2, iclass 19, count 0 2006.169.08:00:17.86#ibcon#*after write, iclass 19, count 0 2006.169.08:00:17.86#ibcon#*before return 0, iclass 19, count 0 2006.169.08:00:17.86#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.169.08:00:17.86#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.169.08:00:17.86#ibcon#about to clear, iclass 19 cls_cnt 0 2006.169.08:00:17.86#ibcon#cleared, iclass 19 cls_cnt 0 2006.169.08:00:17.86$vc4f8/vb=2,4 2006.169.08:00:17.86#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.169.08:00:17.86#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.169.08:00:17.86#ibcon#ireg 11 cls_cnt 2 2006.169.08:00:17.86#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.169.08:00:17.92#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.169.08:00:17.92#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.169.08:00:17.92#ibcon#enter wrdev, iclass 21, count 2 2006.169.08:00:17.92#ibcon#first serial, iclass 21, count 2 2006.169.08:00:17.92#ibcon#enter sib2, iclass 21, count 2 2006.169.08:00:17.92#ibcon#flushed, iclass 21, count 2 2006.169.08:00:17.92#ibcon#about to write, iclass 21, count 2 2006.169.08:00:17.92#ibcon#wrote, iclass 21, count 2 2006.169.08:00:17.92#ibcon#about to read 3, iclass 21, count 2 2006.169.08:00:17.94#ibcon#read 3, iclass 21, count 2 2006.169.08:00:17.94#ibcon#about to read 4, iclass 21, count 2 2006.169.08:00:17.94#ibcon#read 4, iclass 21, count 2 2006.169.08:00:17.94#ibcon#about to read 5, iclass 21, count 2 2006.169.08:00:17.94#ibcon#read 5, iclass 21, count 2 2006.169.08:00:17.94#ibcon#about to read 6, iclass 21, count 2 2006.169.08:00:17.94#ibcon#read 6, iclass 21, count 2 2006.169.08:00:17.94#ibcon#end of sib2, iclass 21, count 2 2006.169.08:00:17.94#ibcon#*mode == 0, iclass 21, count 2 2006.169.08:00:17.94#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.169.08:00:17.94#ibcon#[27=AT02-04\r\n] 2006.169.08:00:17.94#ibcon#*before write, iclass 21, count 2 2006.169.08:00:17.94#ibcon#enter sib2, iclass 21, count 2 2006.169.08:00:17.94#ibcon#flushed, iclass 21, count 2 2006.169.08:00:17.94#ibcon#about to write, iclass 21, count 2 2006.169.08:00:17.94#ibcon#wrote, iclass 21, count 2 2006.169.08:00:17.94#ibcon#about to read 3, iclass 21, count 2 2006.169.08:00:17.97#ibcon#read 3, iclass 21, count 2 2006.169.08:00:17.97#ibcon#about to read 4, iclass 21, count 2 2006.169.08:00:17.97#ibcon#read 4, iclass 21, count 2 2006.169.08:00:17.97#ibcon#about to read 5, iclass 21, count 2 2006.169.08:00:17.97#ibcon#read 5, iclass 21, count 2 2006.169.08:00:17.97#ibcon#about to read 6, iclass 21, count 2 2006.169.08:00:17.97#ibcon#read 6, iclass 21, count 2 2006.169.08:00:17.97#ibcon#end of sib2, iclass 21, count 2 2006.169.08:00:17.97#ibcon#*after write, iclass 21, count 2 2006.169.08:00:17.97#ibcon#*before return 0, iclass 21, count 2 2006.169.08:00:17.97#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.169.08:00:17.97#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.169.08:00:17.97#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.169.08:00:17.97#ibcon#ireg 7 cls_cnt 0 2006.169.08:00:17.97#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.169.08:00:18.09#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.169.08:00:18.09#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.169.08:00:18.09#ibcon#enter wrdev, iclass 21, count 0 2006.169.08:00:18.09#ibcon#first serial, iclass 21, count 0 2006.169.08:00:18.09#ibcon#enter sib2, iclass 21, count 0 2006.169.08:00:18.09#ibcon#flushed, iclass 21, count 0 2006.169.08:00:18.09#ibcon#about to write, iclass 21, count 0 2006.169.08:00:18.09#ibcon#wrote, iclass 21, count 0 2006.169.08:00:18.09#ibcon#about to read 3, iclass 21, count 0 2006.169.08:00:18.11#ibcon#read 3, iclass 21, count 0 2006.169.08:00:18.11#ibcon#about to read 4, iclass 21, count 0 2006.169.08:00:18.11#ibcon#read 4, iclass 21, count 0 2006.169.08:00:18.11#ibcon#about to read 5, iclass 21, count 0 2006.169.08:00:18.11#ibcon#read 5, iclass 21, count 0 2006.169.08:00:18.11#ibcon#about to read 6, iclass 21, count 0 2006.169.08:00:18.11#ibcon#read 6, iclass 21, count 0 2006.169.08:00:18.11#ibcon#end of sib2, iclass 21, count 0 2006.169.08:00:18.11#ibcon#*mode == 0, iclass 21, count 0 2006.169.08:00:18.11#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.169.08:00:18.11#ibcon#[27=USB\r\n] 2006.169.08:00:18.11#ibcon#*before write, iclass 21, count 0 2006.169.08:00:18.11#ibcon#enter sib2, iclass 21, count 0 2006.169.08:00:18.11#ibcon#flushed, iclass 21, count 0 2006.169.08:00:18.11#ibcon#about to write, iclass 21, count 0 2006.169.08:00:18.11#ibcon#wrote, iclass 21, count 0 2006.169.08:00:18.11#ibcon#about to read 3, iclass 21, count 0 2006.169.08:00:18.14#ibcon#read 3, iclass 21, count 0 2006.169.08:00:18.14#ibcon#about to read 4, iclass 21, count 0 2006.169.08:00:18.14#ibcon#read 4, iclass 21, count 0 2006.169.08:00:18.14#ibcon#about to read 5, iclass 21, count 0 2006.169.08:00:18.14#ibcon#read 5, iclass 21, count 0 2006.169.08:00:18.14#ibcon#about to read 6, iclass 21, count 0 2006.169.08:00:18.14#ibcon#read 6, iclass 21, count 0 2006.169.08:00:18.14#ibcon#end of sib2, iclass 21, count 0 2006.169.08:00:18.14#ibcon#*after write, iclass 21, count 0 2006.169.08:00:18.14#ibcon#*before return 0, iclass 21, count 0 2006.169.08:00:18.14#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.169.08:00:18.14#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.169.08:00:18.14#ibcon#about to clear, iclass 21 cls_cnt 0 2006.169.08:00:18.14#ibcon#cleared, iclass 21 cls_cnt 0 2006.169.08:00:18.14$vc4f8/vblo=3,656.99 2006.169.08:00:18.14#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.169.08:00:18.14#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.169.08:00:18.14#ibcon#ireg 17 cls_cnt 0 2006.169.08:00:18.14#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:00:18.14#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:00:18.14#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:00:18.14#ibcon#enter wrdev, iclass 23, count 0 2006.169.08:00:18.14#ibcon#first serial, iclass 23, count 0 2006.169.08:00:18.14#ibcon#enter sib2, iclass 23, count 0 2006.169.08:00:18.14#ibcon#flushed, iclass 23, count 0 2006.169.08:00:18.14#ibcon#about to write, iclass 23, count 0 2006.169.08:00:18.14#ibcon#wrote, iclass 23, count 0 2006.169.08:00:18.14#ibcon#about to read 3, iclass 23, count 0 2006.169.08:00:18.16#ibcon#read 3, iclass 23, count 0 2006.169.08:00:18.16#ibcon#about to read 4, iclass 23, count 0 2006.169.08:00:18.16#ibcon#read 4, iclass 23, count 0 2006.169.08:00:18.16#ibcon#about to read 5, iclass 23, count 0 2006.169.08:00:18.16#ibcon#read 5, iclass 23, count 0 2006.169.08:00:18.16#ibcon#about to read 6, iclass 23, count 0 2006.169.08:00:18.16#ibcon#read 6, iclass 23, count 0 2006.169.08:00:18.16#ibcon#end of sib2, iclass 23, count 0 2006.169.08:00:18.16#ibcon#*mode == 0, iclass 23, count 0 2006.169.08:00:18.16#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.169.08:00:18.16#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.08:00:18.16#ibcon#*before write, iclass 23, count 0 2006.169.08:00:18.16#ibcon#enter sib2, iclass 23, count 0 2006.169.08:00:18.16#ibcon#flushed, iclass 23, count 0 2006.169.08:00:18.16#ibcon#about to write, iclass 23, count 0 2006.169.08:00:18.16#ibcon#wrote, iclass 23, count 0 2006.169.08:00:18.16#ibcon#about to read 3, iclass 23, count 0 2006.169.08:00:18.20#ibcon#read 3, iclass 23, count 0 2006.169.08:00:18.20#ibcon#about to read 4, iclass 23, count 0 2006.169.08:00:18.20#ibcon#read 4, iclass 23, count 0 2006.169.08:00:18.20#ibcon#about to read 5, iclass 23, count 0 2006.169.08:00:18.20#ibcon#read 5, iclass 23, count 0 2006.169.08:00:18.20#ibcon#about to read 6, iclass 23, count 0 2006.169.08:00:18.20#ibcon#read 6, iclass 23, count 0 2006.169.08:00:18.20#ibcon#end of sib2, iclass 23, count 0 2006.169.08:00:18.20#ibcon#*after write, iclass 23, count 0 2006.169.08:00:18.20#ibcon#*before return 0, iclass 23, count 0 2006.169.08:00:18.20#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:00:18.20#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:00:18.20#ibcon#about to clear, iclass 23 cls_cnt 0 2006.169.08:00:18.20#ibcon#cleared, iclass 23 cls_cnt 0 2006.169.08:00:18.20$vc4f8/vb=3,4 2006.169.08:00:18.20#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.169.08:00:18.20#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.169.08:00:18.20#ibcon#ireg 11 cls_cnt 2 2006.169.08:00:18.20#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:00:18.26#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:00:18.26#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:00:18.26#ibcon#enter wrdev, iclass 25, count 2 2006.169.08:00:18.26#ibcon#first serial, iclass 25, count 2 2006.169.08:00:18.26#ibcon#enter sib2, iclass 25, count 2 2006.169.08:00:18.26#ibcon#flushed, iclass 25, count 2 2006.169.08:00:18.26#ibcon#about to write, iclass 25, count 2 2006.169.08:00:18.26#ibcon#wrote, iclass 25, count 2 2006.169.08:00:18.26#ibcon#about to read 3, iclass 25, count 2 2006.169.08:00:18.28#ibcon#read 3, iclass 25, count 2 2006.169.08:00:18.28#ibcon#about to read 4, iclass 25, count 2 2006.169.08:00:18.28#ibcon#read 4, iclass 25, count 2 2006.169.08:00:18.28#ibcon#about to read 5, iclass 25, count 2 2006.169.08:00:18.28#ibcon#read 5, iclass 25, count 2 2006.169.08:00:18.28#ibcon#about to read 6, iclass 25, count 2 2006.169.08:00:18.28#ibcon#read 6, iclass 25, count 2 2006.169.08:00:18.28#ibcon#end of sib2, iclass 25, count 2 2006.169.08:00:18.28#ibcon#*mode == 0, iclass 25, count 2 2006.169.08:00:18.28#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.169.08:00:18.28#ibcon#[27=AT03-04\r\n] 2006.169.08:00:18.28#ibcon#*before write, iclass 25, count 2 2006.169.08:00:18.28#ibcon#enter sib2, iclass 25, count 2 2006.169.08:00:18.28#ibcon#flushed, iclass 25, count 2 2006.169.08:00:18.28#ibcon#about to write, iclass 25, count 2 2006.169.08:00:18.28#ibcon#wrote, iclass 25, count 2 2006.169.08:00:18.28#ibcon#about to read 3, iclass 25, count 2 2006.169.08:00:18.31#ibcon#read 3, iclass 25, count 2 2006.169.08:00:18.31#ibcon#about to read 4, iclass 25, count 2 2006.169.08:00:18.31#ibcon#read 4, iclass 25, count 2 2006.169.08:00:18.31#ibcon#about to read 5, iclass 25, count 2 2006.169.08:00:18.31#ibcon#read 5, iclass 25, count 2 2006.169.08:00:18.31#ibcon#about to read 6, iclass 25, count 2 2006.169.08:00:18.31#ibcon#read 6, iclass 25, count 2 2006.169.08:00:18.31#ibcon#end of sib2, iclass 25, count 2 2006.169.08:00:18.31#ibcon#*after write, iclass 25, count 2 2006.169.08:00:18.31#ibcon#*before return 0, iclass 25, count 2 2006.169.08:00:18.31#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:00:18.31#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:00:18.31#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.169.08:00:18.31#ibcon#ireg 7 cls_cnt 0 2006.169.08:00:18.31#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:00:18.43#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:00:18.43#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:00:18.43#ibcon#enter wrdev, iclass 25, count 0 2006.169.08:00:18.43#ibcon#first serial, iclass 25, count 0 2006.169.08:00:18.43#ibcon#enter sib2, iclass 25, count 0 2006.169.08:00:18.43#ibcon#flushed, iclass 25, count 0 2006.169.08:00:18.43#ibcon#about to write, iclass 25, count 0 2006.169.08:00:18.43#ibcon#wrote, iclass 25, count 0 2006.169.08:00:18.43#ibcon#about to read 3, iclass 25, count 0 2006.169.08:00:18.45#ibcon#read 3, iclass 25, count 0 2006.169.08:00:18.45#ibcon#about to read 4, iclass 25, count 0 2006.169.08:00:18.45#ibcon#read 4, iclass 25, count 0 2006.169.08:00:18.45#ibcon#about to read 5, iclass 25, count 0 2006.169.08:00:18.45#ibcon#read 5, iclass 25, count 0 2006.169.08:00:18.45#ibcon#about to read 6, iclass 25, count 0 2006.169.08:00:18.45#ibcon#read 6, iclass 25, count 0 2006.169.08:00:18.45#ibcon#end of sib2, iclass 25, count 0 2006.169.08:00:18.45#ibcon#*mode == 0, iclass 25, count 0 2006.169.08:00:18.45#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.169.08:00:18.45#ibcon#[27=USB\r\n] 2006.169.08:00:18.45#ibcon#*before write, iclass 25, count 0 2006.169.08:00:18.45#ibcon#enter sib2, iclass 25, count 0 2006.169.08:00:18.45#ibcon#flushed, iclass 25, count 0 2006.169.08:00:18.45#ibcon#about to write, iclass 25, count 0 2006.169.08:00:18.45#ibcon#wrote, iclass 25, count 0 2006.169.08:00:18.45#ibcon#about to read 3, iclass 25, count 0 2006.169.08:00:18.48#ibcon#read 3, iclass 25, count 0 2006.169.08:00:18.48#ibcon#about to read 4, iclass 25, count 0 2006.169.08:00:18.48#ibcon#read 4, iclass 25, count 0 2006.169.08:00:18.48#ibcon#about to read 5, iclass 25, count 0 2006.169.08:00:18.48#ibcon#read 5, iclass 25, count 0 2006.169.08:00:18.48#ibcon#about to read 6, iclass 25, count 0 2006.169.08:00:18.48#ibcon#read 6, iclass 25, count 0 2006.169.08:00:18.48#ibcon#end of sib2, iclass 25, count 0 2006.169.08:00:18.48#ibcon#*after write, iclass 25, count 0 2006.169.08:00:18.48#ibcon#*before return 0, iclass 25, count 0 2006.169.08:00:18.48#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:00:18.48#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:00:18.48#ibcon#about to clear, iclass 25 cls_cnt 0 2006.169.08:00:18.48#ibcon#cleared, iclass 25 cls_cnt 0 2006.169.08:00:18.48$vc4f8/vblo=4,712.99 2006.169.08:00:18.48#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.169.08:00:18.48#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.169.08:00:18.48#ibcon#ireg 17 cls_cnt 0 2006.169.08:00:18.48#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:00:18.48#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:00:18.48#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:00:18.48#ibcon#enter wrdev, iclass 27, count 0 2006.169.08:00:18.48#ibcon#first serial, iclass 27, count 0 2006.169.08:00:18.48#ibcon#enter sib2, iclass 27, count 0 2006.169.08:00:18.48#ibcon#flushed, iclass 27, count 0 2006.169.08:00:18.48#ibcon#about to write, iclass 27, count 0 2006.169.08:00:18.48#ibcon#wrote, iclass 27, count 0 2006.169.08:00:18.48#ibcon#about to read 3, iclass 27, count 0 2006.169.08:00:18.50#ibcon#read 3, iclass 27, count 0 2006.169.08:00:18.50#ibcon#about to read 4, iclass 27, count 0 2006.169.08:00:18.50#ibcon#read 4, iclass 27, count 0 2006.169.08:00:18.50#ibcon#about to read 5, iclass 27, count 0 2006.169.08:00:18.50#ibcon#read 5, iclass 27, count 0 2006.169.08:00:18.50#ibcon#about to read 6, iclass 27, count 0 2006.169.08:00:18.50#ibcon#read 6, iclass 27, count 0 2006.169.08:00:18.50#ibcon#end of sib2, iclass 27, count 0 2006.169.08:00:18.50#ibcon#*mode == 0, iclass 27, count 0 2006.169.08:00:18.50#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.169.08:00:18.50#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.08:00:18.50#ibcon#*before write, iclass 27, count 0 2006.169.08:00:18.50#ibcon#enter sib2, iclass 27, count 0 2006.169.08:00:18.50#ibcon#flushed, iclass 27, count 0 2006.169.08:00:18.50#ibcon#about to write, iclass 27, count 0 2006.169.08:00:18.50#ibcon#wrote, iclass 27, count 0 2006.169.08:00:18.50#ibcon#about to read 3, iclass 27, count 0 2006.169.08:00:18.54#ibcon#read 3, iclass 27, count 0 2006.169.08:00:18.54#ibcon#about to read 4, iclass 27, count 0 2006.169.08:00:18.54#ibcon#read 4, iclass 27, count 0 2006.169.08:00:18.54#ibcon#about to read 5, iclass 27, count 0 2006.169.08:00:18.54#ibcon#read 5, iclass 27, count 0 2006.169.08:00:18.54#ibcon#about to read 6, iclass 27, count 0 2006.169.08:00:18.54#ibcon#read 6, iclass 27, count 0 2006.169.08:00:18.54#ibcon#end of sib2, iclass 27, count 0 2006.169.08:00:18.54#ibcon#*after write, iclass 27, count 0 2006.169.08:00:18.54#ibcon#*before return 0, iclass 27, count 0 2006.169.08:00:18.54#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:00:18.54#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:00:18.54#ibcon#about to clear, iclass 27 cls_cnt 0 2006.169.08:00:18.54#ibcon#cleared, iclass 27 cls_cnt 0 2006.169.08:00:18.54$vc4f8/vb=4,4 2006.169.08:00:18.54#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.169.08:00:18.54#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.169.08:00:18.54#ibcon#ireg 11 cls_cnt 2 2006.169.08:00:18.54#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:00:18.60#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:00:18.60#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:00:18.60#ibcon#enter wrdev, iclass 29, count 2 2006.169.08:00:18.60#ibcon#first serial, iclass 29, count 2 2006.169.08:00:18.60#ibcon#enter sib2, iclass 29, count 2 2006.169.08:00:18.60#ibcon#flushed, iclass 29, count 2 2006.169.08:00:18.60#ibcon#about to write, iclass 29, count 2 2006.169.08:00:18.60#ibcon#wrote, iclass 29, count 2 2006.169.08:00:18.60#ibcon#about to read 3, iclass 29, count 2 2006.169.08:00:18.62#ibcon#read 3, iclass 29, count 2 2006.169.08:00:18.62#ibcon#about to read 4, iclass 29, count 2 2006.169.08:00:18.62#ibcon#read 4, iclass 29, count 2 2006.169.08:00:18.62#ibcon#about to read 5, iclass 29, count 2 2006.169.08:00:18.62#ibcon#read 5, iclass 29, count 2 2006.169.08:00:18.62#ibcon#about to read 6, iclass 29, count 2 2006.169.08:00:18.62#ibcon#read 6, iclass 29, count 2 2006.169.08:00:18.62#ibcon#end of sib2, iclass 29, count 2 2006.169.08:00:18.62#ibcon#*mode == 0, iclass 29, count 2 2006.169.08:00:18.62#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.169.08:00:18.62#ibcon#[27=AT04-04\r\n] 2006.169.08:00:18.62#ibcon#*before write, iclass 29, count 2 2006.169.08:00:18.62#ibcon#enter sib2, iclass 29, count 2 2006.169.08:00:18.62#ibcon#flushed, iclass 29, count 2 2006.169.08:00:18.62#ibcon#about to write, iclass 29, count 2 2006.169.08:00:18.62#ibcon#wrote, iclass 29, count 2 2006.169.08:00:18.62#ibcon#about to read 3, iclass 29, count 2 2006.169.08:00:18.65#ibcon#read 3, iclass 29, count 2 2006.169.08:00:18.65#ibcon#about to read 4, iclass 29, count 2 2006.169.08:00:18.65#ibcon#read 4, iclass 29, count 2 2006.169.08:00:18.65#ibcon#about to read 5, iclass 29, count 2 2006.169.08:00:18.65#ibcon#read 5, iclass 29, count 2 2006.169.08:00:18.65#ibcon#about to read 6, iclass 29, count 2 2006.169.08:00:18.65#ibcon#read 6, iclass 29, count 2 2006.169.08:00:18.65#ibcon#end of sib2, iclass 29, count 2 2006.169.08:00:18.65#ibcon#*after write, iclass 29, count 2 2006.169.08:00:18.65#ibcon#*before return 0, iclass 29, count 2 2006.169.08:00:18.65#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:00:18.65#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:00:18.65#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.169.08:00:18.65#ibcon#ireg 7 cls_cnt 0 2006.169.08:00:18.65#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:00:18.77#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:00:18.77#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:00:18.77#ibcon#enter wrdev, iclass 29, count 0 2006.169.08:00:18.77#ibcon#first serial, iclass 29, count 0 2006.169.08:00:18.77#ibcon#enter sib2, iclass 29, count 0 2006.169.08:00:18.77#ibcon#flushed, iclass 29, count 0 2006.169.08:00:18.77#ibcon#about to write, iclass 29, count 0 2006.169.08:00:18.77#ibcon#wrote, iclass 29, count 0 2006.169.08:00:18.77#ibcon#about to read 3, iclass 29, count 0 2006.169.08:00:18.79#ibcon#read 3, iclass 29, count 0 2006.169.08:00:18.79#ibcon#about to read 4, iclass 29, count 0 2006.169.08:00:18.79#ibcon#read 4, iclass 29, count 0 2006.169.08:00:18.79#ibcon#about to read 5, iclass 29, count 0 2006.169.08:00:18.79#ibcon#read 5, iclass 29, count 0 2006.169.08:00:18.79#ibcon#about to read 6, iclass 29, count 0 2006.169.08:00:18.79#ibcon#read 6, iclass 29, count 0 2006.169.08:00:18.79#ibcon#end of sib2, iclass 29, count 0 2006.169.08:00:18.79#ibcon#*mode == 0, iclass 29, count 0 2006.169.08:00:18.79#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.169.08:00:18.79#ibcon#[27=USB\r\n] 2006.169.08:00:18.79#ibcon#*before write, iclass 29, count 0 2006.169.08:00:18.79#ibcon#enter sib2, iclass 29, count 0 2006.169.08:00:18.79#ibcon#flushed, iclass 29, count 0 2006.169.08:00:18.79#ibcon#about to write, iclass 29, count 0 2006.169.08:00:18.79#ibcon#wrote, iclass 29, count 0 2006.169.08:00:18.79#ibcon#about to read 3, iclass 29, count 0 2006.169.08:00:18.82#ibcon#read 3, iclass 29, count 0 2006.169.08:00:18.82#ibcon#about to read 4, iclass 29, count 0 2006.169.08:00:18.82#ibcon#read 4, iclass 29, count 0 2006.169.08:00:18.82#ibcon#about to read 5, iclass 29, count 0 2006.169.08:00:18.82#ibcon#read 5, iclass 29, count 0 2006.169.08:00:18.82#ibcon#about to read 6, iclass 29, count 0 2006.169.08:00:18.82#ibcon#read 6, iclass 29, count 0 2006.169.08:00:18.82#ibcon#end of sib2, iclass 29, count 0 2006.169.08:00:18.82#ibcon#*after write, iclass 29, count 0 2006.169.08:00:18.82#ibcon#*before return 0, iclass 29, count 0 2006.169.08:00:18.82#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:00:18.82#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:00:18.82#ibcon#about to clear, iclass 29 cls_cnt 0 2006.169.08:00:18.82#ibcon#cleared, iclass 29 cls_cnt 0 2006.169.08:00:18.82$vc4f8/vblo=5,744.99 2006.169.08:00:18.82#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.169.08:00:18.82#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.169.08:00:18.82#ibcon#ireg 17 cls_cnt 0 2006.169.08:00:18.82#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:00:18.82#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:00:18.82#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:00:18.82#ibcon#enter wrdev, iclass 31, count 0 2006.169.08:00:18.82#ibcon#first serial, iclass 31, count 0 2006.169.08:00:18.82#ibcon#enter sib2, iclass 31, count 0 2006.169.08:00:18.82#ibcon#flushed, iclass 31, count 0 2006.169.08:00:18.82#ibcon#about to write, iclass 31, count 0 2006.169.08:00:18.82#ibcon#wrote, iclass 31, count 0 2006.169.08:00:18.82#ibcon#about to read 3, iclass 31, count 0 2006.169.08:00:18.84#ibcon#read 3, iclass 31, count 0 2006.169.08:00:18.84#ibcon#about to read 4, iclass 31, count 0 2006.169.08:00:18.84#ibcon#read 4, iclass 31, count 0 2006.169.08:00:18.84#ibcon#about to read 5, iclass 31, count 0 2006.169.08:00:18.84#ibcon#read 5, iclass 31, count 0 2006.169.08:00:18.84#ibcon#about to read 6, iclass 31, count 0 2006.169.08:00:18.84#ibcon#read 6, iclass 31, count 0 2006.169.08:00:18.84#ibcon#end of sib2, iclass 31, count 0 2006.169.08:00:18.84#ibcon#*mode == 0, iclass 31, count 0 2006.169.08:00:18.84#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.169.08:00:18.84#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.08:00:18.84#ibcon#*before write, iclass 31, count 0 2006.169.08:00:18.84#ibcon#enter sib2, iclass 31, count 0 2006.169.08:00:18.84#ibcon#flushed, iclass 31, count 0 2006.169.08:00:18.84#ibcon#about to write, iclass 31, count 0 2006.169.08:00:18.84#ibcon#wrote, iclass 31, count 0 2006.169.08:00:18.84#ibcon#about to read 3, iclass 31, count 0 2006.169.08:00:18.88#ibcon#read 3, iclass 31, count 0 2006.169.08:00:18.88#ibcon#about to read 4, iclass 31, count 0 2006.169.08:00:18.88#ibcon#read 4, iclass 31, count 0 2006.169.08:00:18.88#ibcon#about to read 5, iclass 31, count 0 2006.169.08:00:18.88#ibcon#read 5, iclass 31, count 0 2006.169.08:00:18.88#ibcon#about to read 6, iclass 31, count 0 2006.169.08:00:18.88#ibcon#read 6, iclass 31, count 0 2006.169.08:00:18.88#ibcon#end of sib2, iclass 31, count 0 2006.169.08:00:18.88#ibcon#*after write, iclass 31, count 0 2006.169.08:00:18.88#ibcon#*before return 0, iclass 31, count 0 2006.169.08:00:18.88#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:00:18.88#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:00:18.88#ibcon#about to clear, iclass 31 cls_cnt 0 2006.169.08:00:18.88#ibcon#cleared, iclass 31 cls_cnt 0 2006.169.08:00:18.88$vc4f8/vb=5,4 2006.169.08:00:18.88#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.169.08:00:18.88#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.169.08:00:18.88#ibcon#ireg 11 cls_cnt 2 2006.169.08:00:18.88#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:00:18.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:00:18.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:00:18.94#ibcon#enter wrdev, iclass 33, count 2 2006.169.08:00:18.94#ibcon#first serial, iclass 33, count 2 2006.169.08:00:18.94#ibcon#enter sib2, iclass 33, count 2 2006.169.08:00:18.94#ibcon#flushed, iclass 33, count 2 2006.169.08:00:18.94#ibcon#about to write, iclass 33, count 2 2006.169.08:00:18.94#ibcon#wrote, iclass 33, count 2 2006.169.08:00:18.94#ibcon#about to read 3, iclass 33, count 2 2006.169.08:00:18.96#ibcon#read 3, iclass 33, count 2 2006.169.08:00:18.96#ibcon#about to read 4, iclass 33, count 2 2006.169.08:00:18.96#ibcon#read 4, iclass 33, count 2 2006.169.08:00:18.96#ibcon#about to read 5, iclass 33, count 2 2006.169.08:00:18.96#ibcon#read 5, iclass 33, count 2 2006.169.08:00:18.96#ibcon#about to read 6, iclass 33, count 2 2006.169.08:00:18.96#ibcon#read 6, iclass 33, count 2 2006.169.08:00:18.96#ibcon#end of sib2, iclass 33, count 2 2006.169.08:00:18.96#ibcon#*mode == 0, iclass 33, count 2 2006.169.08:00:18.96#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.169.08:00:18.96#ibcon#[27=AT05-04\r\n] 2006.169.08:00:18.96#ibcon#*before write, iclass 33, count 2 2006.169.08:00:18.96#ibcon#enter sib2, iclass 33, count 2 2006.169.08:00:18.96#ibcon#flushed, iclass 33, count 2 2006.169.08:00:18.96#ibcon#about to write, iclass 33, count 2 2006.169.08:00:18.96#ibcon#wrote, iclass 33, count 2 2006.169.08:00:18.96#ibcon#about to read 3, iclass 33, count 2 2006.169.08:00:18.99#ibcon#read 3, iclass 33, count 2 2006.169.08:00:18.99#ibcon#about to read 4, iclass 33, count 2 2006.169.08:00:18.99#ibcon#read 4, iclass 33, count 2 2006.169.08:00:18.99#ibcon#about to read 5, iclass 33, count 2 2006.169.08:00:18.99#ibcon#read 5, iclass 33, count 2 2006.169.08:00:18.99#ibcon#about to read 6, iclass 33, count 2 2006.169.08:00:18.99#ibcon#read 6, iclass 33, count 2 2006.169.08:00:18.99#ibcon#end of sib2, iclass 33, count 2 2006.169.08:00:18.99#ibcon#*after write, iclass 33, count 2 2006.169.08:00:18.99#ibcon#*before return 0, iclass 33, count 2 2006.169.08:00:18.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:00:18.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:00:18.99#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.169.08:00:18.99#ibcon#ireg 7 cls_cnt 0 2006.169.08:00:18.99#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:00:19.11#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:00:19.11#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:00:19.11#ibcon#enter wrdev, iclass 33, count 0 2006.169.08:00:19.11#ibcon#first serial, iclass 33, count 0 2006.169.08:00:19.11#ibcon#enter sib2, iclass 33, count 0 2006.169.08:00:19.11#ibcon#flushed, iclass 33, count 0 2006.169.08:00:19.11#ibcon#about to write, iclass 33, count 0 2006.169.08:00:19.11#ibcon#wrote, iclass 33, count 0 2006.169.08:00:19.11#ibcon#about to read 3, iclass 33, count 0 2006.169.08:00:19.13#ibcon#read 3, iclass 33, count 0 2006.169.08:00:19.13#ibcon#about to read 4, iclass 33, count 0 2006.169.08:00:19.13#ibcon#read 4, iclass 33, count 0 2006.169.08:00:19.13#ibcon#about to read 5, iclass 33, count 0 2006.169.08:00:19.13#ibcon#read 5, iclass 33, count 0 2006.169.08:00:19.13#ibcon#about to read 6, iclass 33, count 0 2006.169.08:00:19.13#ibcon#read 6, iclass 33, count 0 2006.169.08:00:19.13#ibcon#end of sib2, iclass 33, count 0 2006.169.08:00:19.13#ibcon#*mode == 0, iclass 33, count 0 2006.169.08:00:19.13#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.169.08:00:19.13#ibcon#[27=USB\r\n] 2006.169.08:00:19.13#ibcon#*before write, iclass 33, count 0 2006.169.08:00:19.13#ibcon#enter sib2, iclass 33, count 0 2006.169.08:00:19.13#ibcon#flushed, iclass 33, count 0 2006.169.08:00:19.13#ibcon#about to write, iclass 33, count 0 2006.169.08:00:19.13#ibcon#wrote, iclass 33, count 0 2006.169.08:00:19.13#ibcon#about to read 3, iclass 33, count 0 2006.169.08:00:19.16#ibcon#read 3, iclass 33, count 0 2006.169.08:00:19.16#ibcon#about to read 4, iclass 33, count 0 2006.169.08:00:19.16#ibcon#read 4, iclass 33, count 0 2006.169.08:00:19.16#ibcon#about to read 5, iclass 33, count 0 2006.169.08:00:19.16#ibcon#read 5, iclass 33, count 0 2006.169.08:00:19.16#ibcon#about to read 6, iclass 33, count 0 2006.169.08:00:19.16#ibcon#read 6, iclass 33, count 0 2006.169.08:00:19.16#ibcon#end of sib2, iclass 33, count 0 2006.169.08:00:19.16#ibcon#*after write, iclass 33, count 0 2006.169.08:00:19.16#ibcon#*before return 0, iclass 33, count 0 2006.169.08:00:19.16#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:00:19.16#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:00:19.16#ibcon#about to clear, iclass 33 cls_cnt 0 2006.169.08:00:19.16#ibcon#cleared, iclass 33 cls_cnt 0 2006.169.08:00:19.16$vc4f8/vblo=6,752.99 2006.169.08:00:19.16#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.169.08:00:19.16#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.169.08:00:19.16#ibcon#ireg 17 cls_cnt 0 2006.169.08:00:19.16#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:00:19.16#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:00:19.16#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:00:19.16#ibcon#enter wrdev, iclass 35, count 0 2006.169.08:00:19.16#ibcon#first serial, iclass 35, count 0 2006.169.08:00:19.16#ibcon#enter sib2, iclass 35, count 0 2006.169.08:00:19.16#ibcon#flushed, iclass 35, count 0 2006.169.08:00:19.16#ibcon#about to write, iclass 35, count 0 2006.169.08:00:19.16#ibcon#wrote, iclass 35, count 0 2006.169.08:00:19.16#ibcon#about to read 3, iclass 35, count 0 2006.169.08:00:19.18#ibcon#read 3, iclass 35, count 0 2006.169.08:00:19.18#ibcon#about to read 4, iclass 35, count 0 2006.169.08:00:19.18#ibcon#read 4, iclass 35, count 0 2006.169.08:00:19.18#ibcon#about to read 5, iclass 35, count 0 2006.169.08:00:19.18#ibcon#read 5, iclass 35, count 0 2006.169.08:00:19.18#ibcon#about to read 6, iclass 35, count 0 2006.169.08:00:19.18#ibcon#read 6, iclass 35, count 0 2006.169.08:00:19.18#ibcon#end of sib2, iclass 35, count 0 2006.169.08:00:19.18#ibcon#*mode == 0, iclass 35, count 0 2006.169.08:00:19.18#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.169.08:00:19.18#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.08:00:19.18#ibcon#*before write, iclass 35, count 0 2006.169.08:00:19.18#ibcon#enter sib2, iclass 35, count 0 2006.169.08:00:19.18#ibcon#flushed, iclass 35, count 0 2006.169.08:00:19.18#ibcon#about to write, iclass 35, count 0 2006.169.08:00:19.18#ibcon#wrote, iclass 35, count 0 2006.169.08:00:19.18#ibcon#about to read 3, iclass 35, count 0 2006.169.08:00:19.22#ibcon#read 3, iclass 35, count 0 2006.169.08:00:19.22#ibcon#about to read 4, iclass 35, count 0 2006.169.08:00:19.22#ibcon#read 4, iclass 35, count 0 2006.169.08:00:19.22#ibcon#about to read 5, iclass 35, count 0 2006.169.08:00:19.22#ibcon#read 5, iclass 35, count 0 2006.169.08:00:19.22#ibcon#about to read 6, iclass 35, count 0 2006.169.08:00:19.22#ibcon#read 6, iclass 35, count 0 2006.169.08:00:19.22#ibcon#end of sib2, iclass 35, count 0 2006.169.08:00:19.22#ibcon#*after write, iclass 35, count 0 2006.169.08:00:19.22#ibcon#*before return 0, iclass 35, count 0 2006.169.08:00:19.22#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:00:19.22#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:00:19.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.169.08:00:19.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.169.08:00:19.22$vc4f8/vb=6,4 2006.169.08:00:19.22#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.169.08:00:19.22#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.169.08:00:19.22#ibcon#ireg 11 cls_cnt 2 2006.169.08:00:19.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:00:19.28#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:00:19.28#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:00:19.28#ibcon#enter wrdev, iclass 37, count 2 2006.169.08:00:19.28#ibcon#first serial, iclass 37, count 2 2006.169.08:00:19.28#ibcon#enter sib2, iclass 37, count 2 2006.169.08:00:19.28#ibcon#flushed, iclass 37, count 2 2006.169.08:00:19.28#ibcon#about to write, iclass 37, count 2 2006.169.08:00:19.28#ibcon#wrote, iclass 37, count 2 2006.169.08:00:19.28#ibcon#about to read 3, iclass 37, count 2 2006.169.08:00:19.30#ibcon#read 3, iclass 37, count 2 2006.169.08:00:19.30#ibcon#about to read 4, iclass 37, count 2 2006.169.08:00:19.30#ibcon#read 4, iclass 37, count 2 2006.169.08:00:19.30#ibcon#about to read 5, iclass 37, count 2 2006.169.08:00:19.30#ibcon#read 5, iclass 37, count 2 2006.169.08:00:19.30#ibcon#about to read 6, iclass 37, count 2 2006.169.08:00:19.30#ibcon#read 6, iclass 37, count 2 2006.169.08:00:19.30#ibcon#end of sib2, iclass 37, count 2 2006.169.08:00:19.30#ibcon#*mode == 0, iclass 37, count 2 2006.169.08:00:19.30#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.169.08:00:19.30#ibcon#[27=AT06-04\r\n] 2006.169.08:00:19.30#ibcon#*before write, iclass 37, count 2 2006.169.08:00:19.30#ibcon#enter sib2, iclass 37, count 2 2006.169.08:00:19.30#ibcon#flushed, iclass 37, count 2 2006.169.08:00:19.30#ibcon#about to write, iclass 37, count 2 2006.169.08:00:19.30#ibcon#wrote, iclass 37, count 2 2006.169.08:00:19.30#ibcon#about to read 3, iclass 37, count 2 2006.169.08:00:19.33#ibcon#read 3, iclass 37, count 2 2006.169.08:00:19.33#ibcon#about to read 4, iclass 37, count 2 2006.169.08:00:19.33#ibcon#read 4, iclass 37, count 2 2006.169.08:00:19.33#ibcon#about to read 5, iclass 37, count 2 2006.169.08:00:19.33#ibcon#read 5, iclass 37, count 2 2006.169.08:00:19.33#ibcon#about to read 6, iclass 37, count 2 2006.169.08:00:19.33#ibcon#read 6, iclass 37, count 2 2006.169.08:00:19.33#ibcon#end of sib2, iclass 37, count 2 2006.169.08:00:19.33#ibcon#*after write, iclass 37, count 2 2006.169.08:00:19.33#ibcon#*before return 0, iclass 37, count 2 2006.169.08:00:19.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:00:19.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:00:19.33#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.169.08:00:19.33#ibcon#ireg 7 cls_cnt 0 2006.169.08:00:19.33#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:00:19.45#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:00:19.45#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:00:19.45#ibcon#enter wrdev, iclass 37, count 0 2006.169.08:00:19.45#ibcon#first serial, iclass 37, count 0 2006.169.08:00:19.45#ibcon#enter sib2, iclass 37, count 0 2006.169.08:00:19.45#ibcon#flushed, iclass 37, count 0 2006.169.08:00:19.45#ibcon#about to write, iclass 37, count 0 2006.169.08:00:19.45#ibcon#wrote, iclass 37, count 0 2006.169.08:00:19.45#ibcon#about to read 3, iclass 37, count 0 2006.169.08:00:19.47#ibcon#read 3, iclass 37, count 0 2006.169.08:00:19.47#ibcon#about to read 4, iclass 37, count 0 2006.169.08:00:19.47#ibcon#read 4, iclass 37, count 0 2006.169.08:00:19.47#ibcon#about to read 5, iclass 37, count 0 2006.169.08:00:19.47#ibcon#read 5, iclass 37, count 0 2006.169.08:00:19.47#ibcon#about to read 6, iclass 37, count 0 2006.169.08:00:19.47#ibcon#read 6, iclass 37, count 0 2006.169.08:00:19.47#ibcon#end of sib2, iclass 37, count 0 2006.169.08:00:19.47#ibcon#*mode == 0, iclass 37, count 0 2006.169.08:00:19.47#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.169.08:00:19.47#ibcon#[27=USB\r\n] 2006.169.08:00:19.47#ibcon#*before write, iclass 37, count 0 2006.169.08:00:19.47#ibcon#enter sib2, iclass 37, count 0 2006.169.08:00:19.47#ibcon#flushed, iclass 37, count 0 2006.169.08:00:19.47#ibcon#about to write, iclass 37, count 0 2006.169.08:00:19.47#ibcon#wrote, iclass 37, count 0 2006.169.08:00:19.47#ibcon#about to read 3, iclass 37, count 0 2006.169.08:00:19.50#ibcon#read 3, iclass 37, count 0 2006.169.08:00:19.50#ibcon#about to read 4, iclass 37, count 0 2006.169.08:00:19.50#ibcon#read 4, iclass 37, count 0 2006.169.08:00:19.50#ibcon#about to read 5, iclass 37, count 0 2006.169.08:00:19.50#ibcon#read 5, iclass 37, count 0 2006.169.08:00:19.50#ibcon#about to read 6, iclass 37, count 0 2006.169.08:00:19.50#ibcon#read 6, iclass 37, count 0 2006.169.08:00:19.50#ibcon#end of sib2, iclass 37, count 0 2006.169.08:00:19.50#ibcon#*after write, iclass 37, count 0 2006.169.08:00:19.50#ibcon#*before return 0, iclass 37, count 0 2006.169.08:00:19.50#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:00:19.50#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:00:19.50#ibcon#about to clear, iclass 37 cls_cnt 0 2006.169.08:00:19.50#ibcon#cleared, iclass 37 cls_cnt 0 2006.169.08:00:19.50$vc4f8/vabw=wide 2006.169.08:00:19.50#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.169.08:00:19.50#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.169.08:00:19.50#ibcon#ireg 8 cls_cnt 0 2006.169.08:00:19.50#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:00:19.50#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:00:19.50#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:00:19.50#ibcon#enter wrdev, iclass 39, count 0 2006.169.08:00:19.50#ibcon#first serial, iclass 39, count 0 2006.169.08:00:19.50#ibcon#enter sib2, iclass 39, count 0 2006.169.08:00:19.50#ibcon#flushed, iclass 39, count 0 2006.169.08:00:19.50#ibcon#about to write, iclass 39, count 0 2006.169.08:00:19.50#ibcon#wrote, iclass 39, count 0 2006.169.08:00:19.50#ibcon#about to read 3, iclass 39, count 0 2006.169.08:00:19.52#ibcon#read 3, iclass 39, count 0 2006.169.08:00:19.52#ibcon#about to read 4, iclass 39, count 0 2006.169.08:00:19.52#ibcon#read 4, iclass 39, count 0 2006.169.08:00:19.52#ibcon#about to read 5, iclass 39, count 0 2006.169.08:00:19.52#ibcon#read 5, iclass 39, count 0 2006.169.08:00:19.52#ibcon#about to read 6, iclass 39, count 0 2006.169.08:00:19.52#ibcon#read 6, iclass 39, count 0 2006.169.08:00:19.52#ibcon#end of sib2, iclass 39, count 0 2006.169.08:00:19.52#ibcon#*mode == 0, iclass 39, count 0 2006.169.08:00:19.52#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.169.08:00:19.52#ibcon#[25=BW32\r\n] 2006.169.08:00:19.52#ibcon#*before write, iclass 39, count 0 2006.169.08:00:19.52#ibcon#enter sib2, iclass 39, count 0 2006.169.08:00:19.52#ibcon#flushed, iclass 39, count 0 2006.169.08:00:19.52#ibcon#about to write, iclass 39, count 0 2006.169.08:00:19.52#ibcon#wrote, iclass 39, count 0 2006.169.08:00:19.52#ibcon#about to read 3, iclass 39, count 0 2006.169.08:00:19.55#ibcon#read 3, iclass 39, count 0 2006.169.08:00:19.55#ibcon#about to read 4, iclass 39, count 0 2006.169.08:00:19.55#ibcon#read 4, iclass 39, count 0 2006.169.08:00:19.55#ibcon#about to read 5, iclass 39, count 0 2006.169.08:00:19.55#ibcon#read 5, iclass 39, count 0 2006.169.08:00:19.55#ibcon#about to read 6, iclass 39, count 0 2006.169.08:00:19.55#ibcon#read 6, iclass 39, count 0 2006.169.08:00:19.55#ibcon#end of sib2, iclass 39, count 0 2006.169.08:00:19.55#ibcon#*after write, iclass 39, count 0 2006.169.08:00:19.55#ibcon#*before return 0, iclass 39, count 0 2006.169.08:00:19.55#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:00:19.55#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:00:19.55#ibcon#about to clear, iclass 39 cls_cnt 0 2006.169.08:00:19.55#ibcon#cleared, iclass 39 cls_cnt 0 2006.169.08:00:19.55$vc4f8/vbbw=wide 2006.169.08:00:19.55#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.169.08:00:19.55#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.169.08:00:19.55#ibcon#ireg 8 cls_cnt 0 2006.169.08:00:19.55#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.169.08:00:19.62#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.169.08:00:19.62#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.169.08:00:19.62#ibcon#enter wrdev, iclass 3, count 0 2006.169.08:00:19.62#ibcon#first serial, iclass 3, count 0 2006.169.08:00:19.62#ibcon#enter sib2, iclass 3, count 0 2006.169.08:00:19.62#ibcon#flushed, iclass 3, count 0 2006.169.08:00:19.62#ibcon#about to write, iclass 3, count 0 2006.169.08:00:19.62#ibcon#wrote, iclass 3, count 0 2006.169.08:00:19.62#ibcon#about to read 3, iclass 3, count 0 2006.169.08:00:19.64#ibcon#read 3, iclass 3, count 0 2006.169.08:00:19.64#ibcon#about to read 4, iclass 3, count 0 2006.169.08:00:19.64#ibcon#read 4, iclass 3, count 0 2006.169.08:00:19.64#ibcon#about to read 5, iclass 3, count 0 2006.169.08:00:19.64#ibcon#read 5, iclass 3, count 0 2006.169.08:00:19.64#ibcon#about to read 6, iclass 3, count 0 2006.169.08:00:19.64#ibcon#read 6, iclass 3, count 0 2006.169.08:00:19.64#ibcon#end of sib2, iclass 3, count 0 2006.169.08:00:19.64#ibcon#*mode == 0, iclass 3, count 0 2006.169.08:00:19.64#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.169.08:00:19.64#ibcon#[27=BW32\r\n] 2006.169.08:00:19.64#ibcon#*before write, iclass 3, count 0 2006.169.08:00:19.64#ibcon#enter sib2, iclass 3, count 0 2006.169.08:00:19.64#ibcon#flushed, iclass 3, count 0 2006.169.08:00:19.64#ibcon#about to write, iclass 3, count 0 2006.169.08:00:19.64#ibcon#wrote, iclass 3, count 0 2006.169.08:00:19.64#ibcon#about to read 3, iclass 3, count 0 2006.169.08:00:19.67#ibcon#read 3, iclass 3, count 0 2006.169.08:00:19.67#ibcon#about to read 4, iclass 3, count 0 2006.169.08:00:19.67#ibcon#read 4, iclass 3, count 0 2006.169.08:00:19.67#ibcon#about to read 5, iclass 3, count 0 2006.169.08:00:19.67#ibcon#read 5, iclass 3, count 0 2006.169.08:00:19.67#ibcon#about to read 6, iclass 3, count 0 2006.169.08:00:19.67#ibcon#read 6, iclass 3, count 0 2006.169.08:00:19.67#ibcon#end of sib2, iclass 3, count 0 2006.169.08:00:19.67#ibcon#*after write, iclass 3, count 0 2006.169.08:00:19.67#ibcon#*before return 0, iclass 3, count 0 2006.169.08:00:19.67#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.169.08:00:19.67#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.169.08:00:19.67#ibcon#about to clear, iclass 3 cls_cnt 0 2006.169.08:00:19.67#ibcon#cleared, iclass 3 cls_cnt 0 2006.169.08:00:19.67$4f8m12a/ifd4f 2006.169.08:00:19.67$ifd4f/lo= 2006.169.08:00:19.67$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.08:00:19.67$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.08:00:19.67$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.08:00:19.67$ifd4f/patch= 2006.169.08:00:19.67$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.08:00:19.67$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.08:00:19.67$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.08:00:19.67$4f8m12a/"form=m,16.000,1:2 2006.169.08:00:19.67$4f8m12a/"tpicd 2006.169.08:00:19.67$4f8m12a/echo=off 2006.169.08:00:19.67$4f8m12a/xlog=off 2006.169.08:00:19.67:!2006.169.08:01:10 2006.169.08:00:48.14#trakl#Source acquired 2006.169.08:00:48.14#flagr#flagr/antenna,acquired 2006.169.08:01:10.00:preob 2006.169.08:01:10.14/onsource/TRACKING 2006.169.08:01:10.14:!2006.169.08:01:20 2006.169.08:01:20.00:data_valid=on 2006.169.08:01:20.00:midob 2006.169.08:01:21.14/onsource/TRACKING 2006.169.08:01:21.14/wx/18.11,1004.0,100 2006.169.08:01:21.25/cable/+6.5292E-03 2006.169.08:01:22.34/va/01,08,usb,yes,47,49 2006.169.08:01:22.34/va/02,07,usb,yes,48,50 2006.169.08:01:22.34/va/03,06,usb,yes,50,51 2006.169.08:01:22.34/va/04,07,usb,yes,49,52 2006.169.08:01:22.34/va/05,07,usb,yes,54,57 2006.169.08:01:22.34/va/06,06,usb,yes,54,53 2006.169.08:01:22.34/va/07,06,usb,yes,54,54 2006.169.08:01:22.34/va/08,07,usb,yes,51,50 2006.169.08:01:22.57/valo/01,532.99,yes,locked 2006.169.08:01:22.57/valo/02,572.99,yes,locked 2006.169.08:01:22.57/valo/03,672.99,yes,locked 2006.169.08:01:22.57/valo/04,832.99,yes,locked 2006.169.08:01:22.57/valo/05,652.99,yes,locked 2006.169.08:01:22.57/valo/06,772.99,yes,locked 2006.169.08:01:22.57/valo/07,832.99,yes,locked 2006.169.08:01:22.57/valo/08,852.99,yes,locked 2006.169.08:01:23.66/vb/01,04,usb,yes,30,29 2006.169.08:01:23.66/vb/02,04,usb,yes,32,33 2006.169.08:01:23.66/vb/03,04,usb,yes,28,32 2006.169.08:01:23.66/vb/04,04,usb,yes,29,30 2006.169.08:01:23.66/vb/05,04,usb,yes,28,32 2006.169.08:01:23.66/vb/06,04,usb,yes,29,32 2006.169.08:01:23.66/vb/07,04,usb,yes,31,31 2006.169.08:01:23.66/vb/08,04,usb,yes,28,32 2006.169.08:01:23.89/vblo/01,632.99,yes,locked 2006.169.08:01:23.89/vblo/02,640.99,yes,locked 2006.169.08:01:23.89/vblo/03,656.99,yes,locked 2006.169.08:01:23.89/vblo/04,712.99,yes,locked 2006.169.08:01:23.89/vblo/05,744.99,yes,locked 2006.169.08:01:23.89/vblo/06,752.99,yes,locked 2006.169.08:01:23.89/vblo/07,734.99,yes,locked 2006.169.08:01:23.89/vblo/08,744.99,yes,locked 2006.169.08:01:24.04/vabw/8 2006.169.08:01:24.19/vbbw/8 2006.169.08:01:24.28/xfe/off,on,15.0 2006.169.08:01:24.65/ifatt/23,28,28,28 2006.169.08:01:25.08/fmout-gps/S +4.18E-07 2006.169.08:01:25.16:!2006.169.08:02:20 2006.169.08:02:20.00:data_valid=off 2006.169.08:02:20.00:postob 2006.169.08:02:20.20/cable/+6.5286E-03 2006.169.08:02:20.20/wx/18.11,1004.0,100 2006.169.08:02:21.08/fmout-gps/S +4.17E-07 2006.169.08:02:21.08:scan_name=169-0803,k06169,60 2006.169.08:02:21.09:source=1739+522,174036.98,521143.4,2000.0,cw 2006.169.08:02:21.13#flagr#flagr/antenna,new-source 2006.169.08:02:22.13:checkk5 2006.169.08:02:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.169.08:02:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.169.08:02:26.91/chk_autoobs//k5ts3?ERROR: timeout happened! 2006.169.08:02:27.32/chk_autoobs//k5ts4/ autoobs is running! 2006.169.08:02:27.69/chk_obsdata//k5ts1/T1690801??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.08:02:28.06/chk_obsdata//k5ts2/T1690801??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.08:02:35.08/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.08:02:35.45/chk_obsdata//k5ts4/T1690801??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.08:02:36.18/k5log//k5ts1_log_newline 2006.169.08:02:36.87/k5log//k5ts2_log_newline 2006.169.08:02:43.97/k5log//k5ts3?ERROR: timeout happened! 2006.169.08:02:44.14#trakl#Source acquired 2006.169.08:02:44.66/k5log//k5ts4_log_newline 2006.169.08:02:44.82/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.08:02:44.82:4f8m12a=2 2006.169.08:02:44.82$4f8m12a/echo=on 2006.169.08:02:44.82$4f8m12a/pcalon 2006.169.08:02:44.82$pcalon/"no phase cal control is implemented here 2006.169.08:02:44.82$4f8m12a/"tpicd=stop 2006.169.08:02:44.82$4f8m12a/vc4f8 2006.169.08:02:44.82$vc4f8/valo=1,532.99 2006.169.08:02:44.83#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.169.08:02:44.83#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.169.08:02:44.83#ibcon#ireg 17 cls_cnt 0 2006.169.08:02:44.83#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:02:44.83#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:02:44.83#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:02:44.83#ibcon#enter wrdev, iclass 28, count 0 2006.169.08:02:44.83#ibcon#first serial, iclass 28, count 0 2006.169.08:02:44.83#ibcon#enter sib2, iclass 28, count 0 2006.169.08:02:44.83#ibcon#flushed, iclass 28, count 0 2006.169.08:02:44.83#ibcon#about to write, iclass 28, count 0 2006.169.08:02:44.83#ibcon#wrote, iclass 28, count 0 2006.169.08:02:44.83#ibcon#about to read 3, iclass 28, count 0 2006.169.08:02:44.85#ibcon#read 3, iclass 28, count 0 2006.169.08:02:44.85#ibcon#about to read 4, iclass 28, count 0 2006.169.08:02:44.85#ibcon#read 4, iclass 28, count 0 2006.169.08:02:44.85#ibcon#about to read 5, iclass 28, count 0 2006.169.08:02:44.85#ibcon#read 5, iclass 28, count 0 2006.169.08:02:44.85#ibcon#about to read 6, iclass 28, count 0 2006.169.08:02:44.85#ibcon#read 6, iclass 28, count 0 2006.169.08:02:44.85#ibcon#end of sib2, iclass 28, count 0 2006.169.08:02:44.85#ibcon#*mode == 0, iclass 28, count 0 2006.169.08:02:44.85#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.169.08:02:44.85#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.08:02:44.85#ibcon#*before write, iclass 28, count 0 2006.169.08:02:44.85#ibcon#enter sib2, iclass 28, count 0 2006.169.08:02:44.85#ibcon#flushed, iclass 28, count 0 2006.169.08:02:44.85#ibcon#about to write, iclass 28, count 0 2006.169.08:02:44.85#ibcon#wrote, iclass 28, count 0 2006.169.08:02:44.85#ibcon#about to read 3, iclass 28, count 0 2006.169.08:02:44.90#ibcon#read 3, iclass 28, count 0 2006.169.08:02:44.90#ibcon#about to read 4, iclass 28, count 0 2006.169.08:02:44.90#ibcon#read 4, iclass 28, count 0 2006.169.08:02:44.90#ibcon#about to read 5, iclass 28, count 0 2006.169.08:02:44.90#ibcon#read 5, iclass 28, count 0 2006.169.08:02:44.90#ibcon#about to read 6, iclass 28, count 0 2006.169.08:02:44.90#ibcon#read 6, iclass 28, count 0 2006.169.08:02:44.90#ibcon#end of sib2, iclass 28, count 0 2006.169.08:02:44.90#ibcon#*after write, iclass 28, count 0 2006.169.08:02:44.90#ibcon#*before return 0, iclass 28, count 0 2006.169.08:02:44.90#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:02:44.90#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:02:44.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.169.08:02:44.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.169.08:02:44.90$vc4f8/va=1,8 2006.169.08:02:44.90#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.169.08:02:44.90#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.169.08:02:44.90#ibcon#ireg 11 cls_cnt 2 2006.169.08:02:44.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:02:44.90#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:02:44.90#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:02:44.90#ibcon#enter wrdev, iclass 30, count 2 2006.169.08:02:44.90#ibcon#first serial, iclass 30, count 2 2006.169.08:02:44.90#ibcon#enter sib2, iclass 30, count 2 2006.169.08:02:44.90#ibcon#flushed, iclass 30, count 2 2006.169.08:02:44.90#ibcon#about to write, iclass 30, count 2 2006.169.08:02:44.90#ibcon#wrote, iclass 30, count 2 2006.169.08:02:44.90#ibcon#about to read 3, iclass 30, count 2 2006.169.08:02:44.92#ibcon#read 3, iclass 30, count 2 2006.169.08:02:44.92#ibcon#about to read 4, iclass 30, count 2 2006.169.08:02:44.92#ibcon#read 4, iclass 30, count 2 2006.169.08:02:44.92#ibcon#about to read 5, iclass 30, count 2 2006.169.08:02:44.92#ibcon#read 5, iclass 30, count 2 2006.169.08:02:44.92#ibcon#about to read 6, iclass 30, count 2 2006.169.08:02:44.92#ibcon#read 6, iclass 30, count 2 2006.169.08:02:44.92#ibcon#end of sib2, iclass 30, count 2 2006.169.08:02:44.92#ibcon#*mode == 0, iclass 30, count 2 2006.169.08:02:44.92#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.169.08:02:44.92#ibcon#[25=AT01-08\r\n] 2006.169.08:02:44.92#ibcon#*before write, iclass 30, count 2 2006.169.08:02:44.92#ibcon#enter sib2, iclass 30, count 2 2006.169.08:02:44.92#ibcon#flushed, iclass 30, count 2 2006.169.08:02:44.92#ibcon#about to write, iclass 30, count 2 2006.169.08:02:44.92#ibcon#wrote, iclass 30, count 2 2006.169.08:02:44.92#ibcon#about to read 3, iclass 30, count 2 2006.169.08:02:44.95#ibcon#read 3, iclass 30, count 2 2006.169.08:02:44.95#ibcon#about to read 4, iclass 30, count 2 2006.169.08:02:44.95#ibcon#read 4, iclass 30, count 2 2006.169.08:02:44.95#ibcon#about to read 5, iclass 30, count 2 2006.169.08:02:44.95#ibcon#read 5, iclass 30, count 2 2006.169.08:02:44.95#ibcon#about to read 6, iclass 30, count 2 2006.169.08:02:44.95#ibcon#read 6, iclass 30, count 2 2006.169.08:02:44.95#ibcon#end of sib2, iclass 30, count 2 2006.169.08:02:44.95#ibcon#*after write, iclass 30, count 2 2006.169.08:02:44.95#ibcon#*before return 0, iclass 30, count 2 2006.169.08:02:44.95#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:02:44.95#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:02:44.95#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.169.08:02:44.95#ibcon#ireg 7 cls_cnt 0 2006.169.08:02:44.95#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:02:45.07#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:02:45.07#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:02:45.07#ibcon#enter wrdev, iclass 30, count 0 2006.169.08:02:45.07#ibcon#first serial, iclass 30, count 0 2006.169.08:02:45.07#ibcon#enter sib2, iclass 30, count 0 2006.169.08:02:45.07#ibcon#flushed, iclass 30, count 0 2006.169.08:02:45.07#ibcon#about to write, iclass 30, count 0 2006.169.08:02:45.07#ibcon#wrote, iclass 30, count 0 2006.169.08:02:45.07#ibcon#about to read 3, iclass 30, count 0 2006.169.08:02:45.09#ibcon#read 3, iclass 30, count 0 2006.169.08:02:45.09#ibcon#about to read 4, iclass 30, count 0 2006.169.08:02:45.09#ibcon#read 4, iclass 30, count 0 2006.169.08:02:45.09#ibcon#about to read 5, iclass 30, count 0 2006.169.08:02:45.09#ibcon#read 5, iclass 30, count 0 2006.169.08:02:45.09#ibcon#about to read 6, iclass 30, count 0 2006.169.08:02:45.09#ibcon#read 6, iclass 30, count 0 2006.169.08:02:45.09#ibcon#end of sib2, iclass 30, count 0 2006.169.08:02:45.09#ibcon#*mode == 0, iclass 30, count 0 2006.169.08:02:45.09#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.169.08:02:45.09#ibcon#[25=USB\r\n] 2006.169.08:02:45.09#ibcon#*before write, iclass 30, count 0 2006.169.08:02:45.09#ibcon#enter sib2, iclass 30, count 0 2006.169.08:02:45.09#ibcon#flushed, iclass 30, count 0 2006.169.08:02:45.09#ibcon#about to write, iclass 30, count 0 2006.169.08:02:45.09#ibcon#wrote, iclass 30, count 0 2006.169.08:02:45.09#ibcon#about to read 3, iclass 30, count 0 2006.169.08:02:45.12#ibcon#read 3, iclass 30, count 0 2006.169.08:02:45.12#ibcon#about to read 4, iclass 30, count 0 2006.169.08:02:45.12#ibcon#read 4, iclass 30, count 0 2006.169.08:02:45.12#ibcon#about to read 5, iclass 30, count 0 2006.169.08:02:45.12#ibcon#read 5, iclass 30, count 0 2006.169.08:02:45.12#ibcon#about to read 6, iclass 30, count 0 2006.169.08:02:45.12#ibcon#read 6, iclass 30, count 0 2006.169.08:02:45.12#ibcon#end of sib2, iclass 30, count 0 2006.169.08:02:45.12#ibcon#*after write, iclass 30, count 0 2006.169.08:02:45.12#ibcon#*before return 0, iclass 30, count 0 2006.169.08:02:45.12#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:02:45.12#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:02:45.12#ibcon#about to clear, iclass 30 cls_cnt 0 2006.169.08:02:45.12#ibcon#cleared, iclass 30 cls_cnt 0 2006.169.08:02:45.12$vc4f8/valo=2,572.99 2006.169.08:02:45.12#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.169.08:02:45.12#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.169.08:02:45.12#ibcon#ireg 17 cls_cnt 0 2006.169.08:02:45.12#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:02:45.12#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:02:45.12#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:02:45.12#ibcon#enter wrdev, iclass 32, count 0 2006.169.08:02:45.12#ibcon#first serial, iclass 32, count 0 2006.169.08:02:45.12#ibcon#enter sib2, iclass 32, count 0 2006.169.08:02:45.12#ibcon#flushed, iclass 32, count 0 2006.169.08:02:45.12#ibcon#about to write, iclass 32, count 0 2006.169.08:02:45.12#ibcon#wrote, iclass 32, count 0 2006.169.08:02:45.12#ibcon#about to read 3, iclass 32, count 0 2006.169.08:02:45.14#ibcon#read 3, iclass 32, count 0 2006.169.08:02:45.14#ibcon#about to read 4, iclass 32, count 0 2006.169.08:02:45.14#ibcon#read 4, iclass 32, count 0 2006.169.08:02:45.14#ibcon#about to read 5, iclass 32, count 0 2006.169.08:02:45.14#ibcon#read 5, iclass 32, count 0 2006.169.08:02:45.14#ibcon#about to read 6, iclass 32, count 0 2006.169.08:02:45.14#ibcon#read 6, iclass 32, count 0 2006.169.08:02:45.14#ibcon#end of sib2, iclass 32, count 0 2006.169.08:02:45.14#ibcon#*mode == 0, iclass 32, count 0 2006.169.08:02:45.14#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.169.08:02:45.14#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.08:02:45.14#ibcon#*before write, iclass 32, count 0 2006.169.08:02:45.14#ibcon#enter sib2, iclass 32, count 0 2006.169.08:02:45.14#ibcon#flushed, iclass 32, count 0 2006.169.08:02:45.14#ibcon#about to write, iclass 32, count 0 2006.169.08:02:45.14#ibcon#wrote, iclass 32, count 0 2006.169.08:02:45.14#ibcon#about to read 3, iclass 32, count 0 2006.169.08:02:45.14#flagr#flagr/antenna,acquired 2006.169.08:02:45.18#ibcon#read 3, iclass 32, count 0 2006.169.08:02:45.18#ibcon#about to read 4, iclass 32, count 0 2006.169.08:02:45.18#ibcon#read 4, iclass 32, count 0 2006.169.08:02:45.18#ibcon#about to read 5, iclass 32, count 0 2006.169.08:02:45.18#ibcon#read 5, iclass 32, count 0 2006.169.08:02:45.18#ibcon#about to read 6, iclass 32, count 0 2006.169.08:02:45.18#ibcon#read 6, iclass 32, count 0 2006.169.08:02:45.18#ibcon#end of sib2, iclass 32, count 0 2006.169.08:02:45.18#ibcon#*after write, iclass 32, count 0 2006.169.08:02:45.18#ibcon#*before return 0, iclass 32, count 0 2006.169.08:02:45.18#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:02:45.18#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:02:45.18#ibcon#about to clear, iclass 32 cls_cnt 0 2006.169.08:02:45.18#ibcon#cleared, iclass 32 cls_cnt 0 2006.169.08:02:45.18$vc4f8/va=2,7 2006.169.08:02:45.18#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.169.08:02:45.18#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.169.08:02:45.18#ibcon#ireg 11 cls_cnt 2 2006.169.08:02:45.18#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:02:45.24#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:02:45.24#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:02:45.24#ibcon#enter wrdev, iclass 34, count 2 2006.169.08:02:45.24#ibcon#first serial, iclass 34, count 2 2006.169.08:02:45.24#ibcon#enter sib2, iclass 34, count 2 2006.169.08:02:45.24#ibcon#flushed, iclass 34, count 2 2006.169.08:02:45.24#ibcon#about to write, iclass 34, count 2 2006.169.08:02:45.24#ibcon#wrote, iclass 34, count 2 2006.169.08:02:45.24#ibcon#about to read 3, iclass 34, count 2 2006.169.08:02:45.26#ibcon#read 3, iclass 34, count 2 2006.169.08:02:45.26#ibcon#about to read 4, iclass 34, count 2 2006.169.08:02:45.26#ibcon#read 4, iclass 34, count 2 2006.169.08:02:45.26#ibcon#about to read 5, iclass 34, count 2 2006.169.08:02:45.26#ibcon#read 5, iclass 34, count 2 2006.169.08:02:45.26#ibcon#about to read 6, iclass 34, count 2 2006.169.08:02:45.26#ibcon#read 6, iclass 34, count 2 2006.169.08:02:45.26#ibcon#end of sib2, iclass 34, count 2 2006.169.08:02:45.26#ibcon#*mode == 0, iclass 34, count 2 2006.169.08:02:45.26#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.169.08:02:45.26#ibcon#[25=AT02-07\r\n] 2006.169.08:02:45.26#ibcon#*before write, iclass 34, count 2 2006.169.08:02:45.26#ibcon#enter sib2, iclass 34, count 2 2006.169.08:02:45.26#ibcon#flushed, iclass 34, count 2 2006.169.08:02:45.26#ibcon#about to write, iclass 34, count 2 2006.169.08:02:45.26#ibcon#wrote, iclass 34, count 2 2006.169.08:02:45.26#ibcon#about to read 3, iclass 34, count 2 2006.169.08:02:45.29#ibcon#read 3, iclass 34, count 2 2006.169.08:02:45.29#ibcon#about to read 4, iclass 34, count 2 2006.169.08:02:45.29#ibcon#read 4, iclass 34, count 2 2006.169.08:02:45.29#ibcon#about to read 5, iclass 34, count 2 2006.169.08:02:45.29#ibcon#read 5, iclass 34, count 2 2006.169.08:02:45.29#ibcon#about to read 6, iclass 34, count 2 2006.169.08:02:45.29#ibcon#read 6, iclass 34, count 2 2006.169.08:02:45.29#ibcon#end of sib2, iclass 34, count 2 2006.169.08:02:45.29#ibcon#*after write, iclass 34, count 2 2006.169.08:02:45.29#ibcon#*before return 0, iclass 34, count 2 2006.169.08:02:45.29#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:02:45.29#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:02:45.29#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.169.08:02:45.29#ibcon#ireg 7 cls_cnt 0 2006.169.08:02:45.29#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:02:45.41#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:02:45.41#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:02:45.41#ibcon#enter wrdev, iclass 34, count 0 2006.169.08:02:45.41#ibcon#first serial, iclass 34, count 0 2006.169.08:02:45.41#ibcon#enter sib2, iclass 34, count 0 2006.169.08:02:45.41#ibcon#flushed, iclass 34, count 0 2006.169.08:02:45.41#ibcon#about to write, iclass 34, count 0 2006.169.08:02:45.41#ibcon#wrote, iclass 34, count 0 2006.169.08:02:45.41#ibcon#about to read 3, iclass 34, count 0 2006.169.08:02:45.43#ibcon#read 3, iclass 34, count 0 2006.169.08:02:45.43#ibcon#about to read 4, iclass 34, count 0 2006.169.08:02:45.43#ibcon#read 4, iclass 34, count 0 2006.169.08:02:45.43#ibcon#about to read 5, iclass 34, count 0 2006.169.08:02:45.43#ibcon#read 5, iclass 34, count 0 2006.169.08:02:45.43#ibcon#about to read 6, iclass 34, count 0 2006.169.08:02:45.43#ibcon#read 6, iclass 34, count 0 2006.169.08:02:45.43#ibcon#end of sib2, iclass 34, count 0 2006.169.08:02:45.43#ibcon#*mode == 0, iclass 34, count 0 2006.169.08:02:45.43#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.169.08:02:45.43#ibcon#[25=USB\r\n] 2006.169.08:02:45.43#ibcon#*before write, iclass 34, count 0 2006.169.08:02:45.43#ibcon#enter sib2, iclass 34, count 0 2006.169.08:02:45.43#ibcon#flushed, iclass 34, count 0 2006.169.08:02:45.43#ibcon#about to write, iclass 34, count 0 2006.169.08:02:45.43#ibcon#wrote, iclass 34, count 0 2006.169.08:02:45.43#ibcon#about to read 3, iclass 34, count 0 2006.169.08:02:45.46#ibcon#read 3, iclass 34, count 0 2006.169.08:02:45.46#ibcon#about to read 4, iclass 34, count 0 2006.169.08:02:45.46#ibcon#read 4, iclass 34, count 0 2006.169.08:02:45.46#ibcon#about to read 5, iclass 34, count 0 2006.169.08:02:45.46#ibcon#read 5, iclass 34, count 0 2006.169.08:02:45.46#ibcon#about to read 6, iclass 34, count 0 2006.169.08:02:45.46#ibcon#read 6, iclass 34, count 0 2006.169.08:02:45.46#ibcon#end of sib2, iclass 34, count 0 2006.169.08:02:45.46#ibcon#*after write, iclass 34, count 0 2006.169.08:02:45.46#ibcon#*before return 0, iclass 34, count 0 2006.169.08:02:45.46#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:02:45.46#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:02:45.46#ibcon#about to clear, iclass 34 cls_cnt 0 2006.169.08:02:45.46#ibcon#cleared, iclass 34 cls_cnt 0 2006.169.08:02:45.46$vc4f8/valo=3,672.99 2006.169.08:02:45.46#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.169.08:02:45.46#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.169.08:02:45.46#ibcon#ireg 17 cls_cnt 0 2006.169.08:02:45.46#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:02:45.46#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:02:45.46#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:02:45.46#ibcon#enter wrdev, iclass 36, count 0 2006.169.08:02:45.46#ibcon#first serial, iclass 36, count 0 2006.169.08:02:45.46#ibcon#enter sib2, iclass 36, count 0 2006.169.08:02:45.46#ibcon#flushed, iclass 36, count 0 2006.169.08:02:45.46#ibcon#about to write, iclass 36, count 0 2006.169.08:02:45.46#ibcon#wrote, iclass 36, count 0 2006.169.08:02:45.46#ibcon#about to read 3, iclass 36, count 0 2006.169.08:02:45.48#ibcon#read 3, iclass 36, count 0 2006.169.08:02:45.48#ibcon#about to read 4, iclass 36, count 0 2006.169.08:02:45.48#ibcon#read 4, iclass 36, count 0 2006.169.08:02:45.48#ibcon#about to read 5, iclass 36, count 0 2006.169.08:02:45.48#ibcon#read 5, iclass 36, count 0 2006.169.08:02:45.48#ibcon#about to read 6, iclass 36, count 0 2006.169.08:02:45.48#ibcon#read 6, iclass 36, count 0 2006.169.08:02:45.48#ibcon#end of sib2, iclass 36, count 0 2006.169.08:02:45.48#ibcon#*mode == 0, iclass 36, count 0 2006.169.08:02:45.48#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.169.08:02:45.48#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.08:02:45.48#ibcon#*before write, iclass 36, count 0 2006.169.08:02:45.48#ibcon#enter sib2, iclass 36, count 0 2006.169.08:02:45.48#ibcon#flushed, iclass 36, count 0 2006.169.08:02:45.48#ibcon#about to write, iclass 36, count 0 2006.169.08:02:45.48#ibcon#wrote, iclass 36, count 0 2006.169.08:02:45.48#ibcon#about to read 3, iclass 36, count 0 2006.169.08:02:45.52#ibcon#read 3, iclass 36, count 0 2006.169.08:02:45.52#ibcon#about to read 4, iclass 36, count 0 2006.169.08:02:45.52#ibcon#read 4, iclass 36, count 0 2006.169.08:02:45.52#ibcon#about to read 5, iclass 36, count 0 2006.169.08:02:45.52#ibcon#read 5, iclass 36, count 0 2006.169.08:02:45.52#ibcon#about to read 6, iclass 36, count 0 2006.169.08:02:45.52#ibcon#read 6, iclass 36, count 0 2006.169.08:02:45.52#ibcon#end of sib2, iclass 36, count 0 2006.169.08:02:45.52#ibcon#*after write, iclass 36, count 0 2006.169.08:02:45.52#ibcon#*before return 0, iclass 36, count 0 2006.169.08:02:45.52#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:02:45.52#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:02:45.52#ibcon#about to clear, iclass 36 cls_cnt 0 2006.169.08:02:45.52#ibcon#cleared, iclass 36 cls_cnt 0 2006.169.08:02:45.52$vc4f8/va=3,6 2006.169.08:02:45.52#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.169.08:02:45.52#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.169.08:02:45.52#ibcon#ireg 11 cls_cnt 2 2006.169.08:02:45.52#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:02:45.59#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:02:45.59#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:02:45.59#ibcon#enter wrdev, iclass 38, count 2 2006.169.08:02:45.59#ibcon#first serial, iclass 38, count 2 2006.169.08:02:45.59#ibcon#enter sib2, iclass 38, count 2 2006.169.08:02:45.59#ibcon#flushed, iclass 38, count 2 2006.169.08:02:45.59#ibcon#about to write, iclass 38, count 2 2006.169.08:02:45.59#ibcon#wrote, iclass 38, count 2 2006.169.08:02:45.59#ibcon#about to read 3, iclass 38, count 2 2006.169.08:02:45.60#ibcon#read 3, iclass 38, count 2 2006.169.08:02:45.60#ibcon#about to read 4, iclass 38, count 2 2006.169.08:02:45.60#ibcon#read 4, iclass 38, count 2 2006.169.08:02:45.60#ibcon#about to read 5, iclass 38, count 2 2006.169.08:02:45.60#ibcon#read 5, iclass 38, count 2 2006.169.08:02:45.60#ibcon#about to read 6, iclass 38, count 2 2006.169.08:02:45.60#ibcon#read 6, iclass 38, count 2 2006.169.08:02:45.60#ibcon#end of sib2, iclass 38, count 2 2006.169.08:02:45.60#ibcon#*mode == 0, iclass 38, count 2 2006.169.08:02:45.60#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.169.08:02:45.60#ibcon#[25=AT03-06\r\n] 2006.169.08:02:45.60#ibcon#*before write, iclass 38, count 2 2006.169.08:02:45.60#ibcon#enter sib2, iclass 38, count 2 2006.169.08:02:45.60#ibcon#flushed, iclass 38, count 2 2006.169.08:02:45.60#ibcon#about to write, iclass 38, count 2 2006.169.08:02:45.60#ibcon#wrote, iclass 38, count 2 2006.169.08:02:45.60#ibcon#about to read 3, iclass 38, count 2 2006.169.08:02:45.63#ibcon#read 3, iclass 38, count 2 2006.169.08:02:45.63#ibcon#about to read 4, iclass 38, count 2 2006.169.08:02:45.63#ibcon#read 4, iclass 38, count 2 2006.169.08:02:45.63#ibcon#about to read 5, iclass 38, count 2 2006.169.08:02:45.63#ibcon#read 5, iclass 38, count 2 2006.169.08:02:45.63#ibcon#about to read 6, iclass 38, count 2 2006.169.08:02:45.63#ibcon#read 6, iclass 38, count 2 2006.169.08:02:45.63#ibcon#end of sib2, iclass 38, count 2 2006.169.08:02:45.63#ibcon#*after write, iclass 38, count 2 2006.169.08:02:45.63#ibcon#*before return 0, iclass 38, count 2 2006.169.08:02:45.63#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:02:45.63#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:02:45.63#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.169.08:02:45.63#ibcon#ireg 7 cls_cnt 0 2006.169.08:02:45.63#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:02:45.75#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:02:45.75#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:02:45.75#ibcon#enter wrdev, iclass 38, count 0 2006.169.08:02:45.75#ibcon#first serial, iclass 38, count 0 2006.169.08:02:45.75#ibcon#enter sib2, iclass 38, count 0 2006.169.08:02:45.75#ibcon#flushed, iclass 38, count 0 2006.169.08:02:45.75#ibcon#about to write, iclass 38, count 0 2006.169.08:02:45.75#ibcon#wrote, iclass 38, count 0 2006.169.08:02:45.75#ibcon#about to read 3, iclass 38, count 0 2006.169.08:02:45.77#ibcon#read 3, iclass 38, count 0 2006.169.08:02:45.77#ibcon#about to read 4, iclass 38, count 0 2006.169.08:02:45.77#ibcon#read 4, iclass 38, count 0 2006.169.08:02:45.77#ibcon#about to read 5, iclass 38, count 0 2006.169.08:02:45.77#ibcon#read 5, iclass 38, count 0 2006.169.08:02:45.77#ibcon#about to read 6, iclass 38, count 0 2006.169.08:02:45.77#ibcon#read 6, iclass 38, count 0 2006.169.08:02:45.77#ibcon#end of sib2, iclass 38, count 0 2006.169.08:02:45.77#ibcon#*mode == 0, iclass 38, count 0 2006.169.08:02:45.77#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.169.08:02:45.77#ibcon#[25=USB\r\n] 2006.169.08:02:45.77#ibcon#*before write, iclass 38, count 0 2006.169.08:02:45.77#ibcon#enter sib2, iclass 38, count 0 2006.169.08:02:45.77#ibcon#flushed, iclass 38, count 0 2006.169.08:02:45.77#ibcon#about to write, iclass 38, count 0 2006.169.08:02:45.77#ibcon#wrote, iclass 38, count 0 2006.169.08:02:45.77#ibcon#about to read 3, iclass 38, count 0 2006.169.08:02:45.80#ibcon#read 3, iclass 38, count 0 2006.169.08:02:45.80#ibcon#about to read 4, iclass 38, count 0 2006.169.08:02:45.80#ibcon#read 4, iclass 38, count 0 2006.169.08:02:45.80#ibcon#about to read 5, iclass 38, count 0 2006.169.08:02:45.80#ibcon#read 5, iclass 38, count 0 2006.169.08:02:45.80#ibcon#about to read 6, iclass 38, count 0 2006.169.08:02:45.80#ibcon#read 6, iclass 38, count 0 2006.169.08:02:45.80#ibcon#end of sib2, iclass 38, count 0 2006.169.08:02:45.80#ibcon#*after write, iclass 38, count 0 2006.169.08:02:45.80#ibcon#*before return 0, iclass 38, count 0 2006.169.08:02:45.80#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:02:45.80#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:02:45.80#ibcon#about to clear, iclass 38 cls_cnt 0 2006.169.08:02:45.80#ibcon#cleared, iclass 38 cls_cnt 0 2006.169.08:02:45.80$vc4f8/valo=4,832.99 2006.169.08:02:45.80#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.169.08:02:45.80#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.169.08:02:45.80#ibcon#ireg 17 cls_cnt 0 2006.169.08:02:45.80#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:02:45.80#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:02:45.80#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:02:45.80#ibcon#enter wrdev, iclass 40, count 0 2006.169.08:02:45.80#ibcon#first serial, iclass 40, count 0 2006.169.08:02:45.80#ibcon#enter sib2, iclass 40, count 0 2006.169.08:02:45.80#ibcon#flushed, iclass 40, count 0 2006.169.08:02:45.80#ibcon#about to write, iclass 40, count 0 2006.169.08:02:45.80#ibcon#wrote, iclass 40, count 0 2006.169.08:02:45.80#ibcon#about to read 3, iclass 40, count 0 2006.169.08:02:45.82#ibcon#read 3, iclass 40, count 0 2006.169.08:02:45.82#ibcon#about to read 4, iclass 40, count 0 2006.169.08:02:45.82#ibcon#read 4, iclass 40, count 0 2006.169.08:02:45.82#ibcon#about to read 5, iclass 40, count 0 2006.169.08:02:45.82#ibcon#read 5, iclass 40, count 0 2006.169.08:02:45.82#ibcon#about to read 6, iclass 40, count 0 2006.169.08:02:45.82#ibcon#read 6, iclass 40, count 0 2006.169.08:02:45.82#ibcon#end of sib2, iclass 40, count 0 2006.169.08:02:45.82#ibcon#*mode == 0, iclass 40, count 0 2006.169.08:02:45.82#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.169.08:02:45.82#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.08:02:45.82#ibcon#*before write, iclass 40, count 0 2006.169.08:02:45.82#ibcon#enter sib2, iclass 40, count 0 2006.169.08:02:45.82#ibcon#flushed, iclass 40, count 0 2006.169.08:02:45.82#ibcon#about to write, iclass 40, count 0 2006.169.08:02:45.82#ibcon#wrote, iclass 40, count 0 2006.169.08:02:45.82#ibcon#about to read 3, iclass 40, count 0 2006.169.08:02:45.86#ibcon#read 3, iclass 40, count 0 2006.169.08:02:45.86#ibcon#about to read 4, iclass 40, count 0 2006.169.08:02:45.86#ibcon#read 4, iclass 40, count 0 2006.169.08:02:45.86#ibcon#about to read 5, iclass 40, count 0 2006.169.08:02:45.86#ibcon#read 5, iclass 40, count 0 2006.169.08:02:45.86#ibcon#about to read 6, iclass 40, count 0 2006.169.08:02:45.86#ibcon#read 6, iclass 40, count 0 2006.169.08:02:45.86#ibcon#end of sib2, iclass 40, count 0 2006.169.08:02:45.86#ibcon#*after write, iclass 40, count 0 2006.169.08:02:45.86#ibcon#*before return 0, iclass 40, count 0 2006.169.08:02:45.86#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:02:45.86#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:02:45.86#ibcon#about to clear, iclass 40 cls_cnt 0 2006.169.08:02:45.86#ibcon#cleared, iclass 40 cls_cnt 0 2006.169.08:02:45.86$vc4f8/va=4,7 2006.169.08:02:45.86#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.169.08:02:45.86#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.169.08:02:45.86#ibcon#ireg 11 cls_cnt 2 2006.169.08:02:45.86#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:02:45.92#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:02:45.92#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:02:45.92#ibcon#enter wrdev, iclass 4, count 2 2006.169.08:02:45.92#ibcon#first serial, iclass 4, count 2 2006.169.08:02:45.92#ibcon#enter sib2, iclass 4, count 2 2006.169.08:02:45.92#ibcon#flushed, iclass 4, count 2 2006.169.08:02:45.92#ibcon#about to write, iclass 4, count 2 2006.169.08:02:45.92#ibcon#wrote, iclass 4, count 2 2006.169.08:02:45.92#ibcon#about to read 3, iclass 4, count 2 2006.169.08:02:45.94#ibcon#read 3, iclass 4, count 2 2006.169.08:02:45.94#ibcon#about to read 4, iclass 4, count 2 2006.169.08:02:45.94#ibcon#read 4, iclass 4, count 2 2006.169.08:02:45.94#ibcon#about to read 5, iclass 4, count 2 2006.169.08:02:45.94#ibcon#read 5, iclass 4, count 2 2006.169.08:02:45.94#ibcon#about to read 6, iclass 4, count 2 2006.169.08:02:45.94#ibcon#read 6, iclass 4, count 2 2006.169.08:02:45.94#ibcon#end of sib2, iclass 4, count 2 2006.169.08:02:45.94#ibcon#*mode == 0, iclass 4, count 2 2006.169.08:02:45.94#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.169.08:02:45.94#ibcon#[25=AT04-07\r\n] 2006.169.08:02:45.94#ibcon#*before write, iclass 4, count 2 2006.169.08:02:45.94#ibcon#enter sib2, iclass 4, count 2 2006.169.08:02:45.94#ibcon#flushed, iclass 4, count 2 2006.169.08:02:45.94#ibcon#about to write, iclass 4, count 2 2006.169.08:02:45.94#ibcon#wrote, iclass 4, count 2 2006.169.08:02:45.94#ibcon#about to read 3, iclass 4, count 2 2006.169.08:02:45.97#ibcon#read 3, iclass 4, count 2 2006.169.08:02:45.97#ibcon#about to read 4, iclass 4, count 2 2006.169.08:02:45.97#ibcon#read 4, iclass 4, count 2 2006.169.08:02:45.97#ibcon#about to read 5, iclass 4, count 2 2006.169.08:02:45.97#ibcon#read 5, iclass 4, count 2 2006.169.08:02:45.97#ibcon#about to read 6, iclass 4, count 2 2006.169.08:02:45.97#ibcon#read 6, iclass 4, count 2 2006.169.08:02:45.97#ibcon#end of sib2, iclass 4, count 2 2006.169.08:02:45.97#ibcon#*after write, iclass 4, count 2 2006.169.08:02:45.97#ibcon#*before return 0, iclass 4, count 2 2006.169.08:02:45.97#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:02:45.97#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:02:45.97#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.169.08:02:45.97#ibcon#ireg 7 cls_cnt 0 2006.169.08:02:45.97#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:02:46.09#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:02:46.09#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:02:46.09#ibcon#enter wrdev, iclass 4, count 0 2006.169.08:02:46.09#ibcon#first serial, iclass 4, count 0 2006.169.08:02:46.09#ibcon#enter sib2, iclass 4, count 0 2006.169.08:02:46.09#ibcon#flushed, iclass 4, count 0 2006.169.08:02:46.09#ibcon#about to write, iclass 4, count 0 2006.169.08:02:46.09#ibcon#wrote, iclass 4, count 0 2006.169.08:02:46.09#ibcon#about to read 3, iclass 4, count 0 2006.169.08:02:46.11#ibcon#read 3, iclass 4, count 0 2006.169.08:02:46.11#ibcon#about to read 4, iclass 4, count 0 2006.169.08:02:46.11#ibcon#read 4, iclass 4, count 0 2006.169.08:02:46.11#ibcon#about to read 5, iclass 4, count 0 2006.169.08:02:46.11#ibcon#read 5, iclass 4, count 0 2006.169.08:02:46.11#ibcon#about to read 6, iclass 4, count 0 2006.169.08:02:46.11#ibcon#read 6, iclass 4, count 0 2006.169.08:02:46.11#ibcon#end of sib2, iclass 4, count 0 2006.169.08:02:46.11#ibcon#*mode == 0, iclass 4, count 0 2006.169.08:02:46.11#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.169.08:02:46.11#ibcon#[25=USB\r\n] 2006.169.08:02:46.11#ibcon#*before write, iclass 4, count 0 2006.169.08:02:46.11#ibcon#enter sib2, iclass 4, count 0 2006.169.08:02:46.11#ibcon#flushed, iclass 4, count 0 2006.169.08:02:46.11#ibcon#about to write, iclass 4, count 0 2006.169.08:02:46.11#ibcon#wrote, iclass 4, count 0 2006.169.08:02:46.11#ibcon#about to read 3, iclass 4, count 0 2006.169.08:02:46.14#ibcon#read 3, iclass 4, count 0 2006.169.08:02:46.14#ibcon#about to read 4, iclass 4, count 0 2006.169.08:02:46.14#ibcon#read 4, iclass 4, count 0 2006.169.08:02:46.14#ibcon#about to read 5, iclass 4, count 0 2006.169.08:02:46.14#ibcon#read 5, iclass 4, count 0 2006.169.08:02:46.14#ibcon#about to read 6, iclass 4, count 0 2006.169.08:02:46.14#ibcon#read 6, iclass 4, count 0 2006.169.08:02:46.14#ibcon#end of sib2, iclass 4, count 0 2006.169.08:02:46.14#ibcon#*after write, iclass 4, count 0 2006.169.08:02:46.14#ibcon#*before return 0, iclass 4, count 0 2006.169.08:02:46.14#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:02:46.14#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:02:46.14#ibcon#about to clear, iclass 4 cls_cnt 0 2006.169.08:02:46.14#ibcon#cleared, iclass 4 cls_cnt 0 2006.169.08:02:46.14$vc4f8/valo=5,652.99 2006.169.08:02:46.14#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.169.08:02:46.14#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.169.08:02:46.14#ibcon#ireg 17 cls_cnt 0 2006.169.08:02:46.14#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:02:46.14#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:02:46.14#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:02:46.14#ibcon#enter wrdev, iclass 6, count 0 2006.169.08:02:46.14#ibcon#first serial, iclass 6, count 0 2006.169.08:02:46.14#ibcon#enter sib2, iclass 6, count 0 2006.169.08:02:46.14#ibcon#flushed, iclass 6, count 0 2006.169.08:02:46.14#ibcon#about to write, iclass 6, count 0 2006.169.08:02:46.14#ibcon#wrote, iclass 6, count 0 2006.169.08:02:46.14#ibcon#about to read 3, iclass 6, count 0 2006.169.08:02:46.16#ibcon#read 3, iclass 6, count 0 2006.169.08:02:46.16#ibcon#about to read 4, iclass 6, count 0 2006.169.08:02:46.16#ibcon#read 4, iclass 6, count 0 2006.169.08:02:46.16#ibcon#about to read 5, iclass 6, count 0 2006.169.08:02:46.16#ibcon#read 5, iclass 6, count 0 2006.169.08:02:46.16#ibcon#about to read 6, iclass 6, count 0 2006.169.08:02:46.16#ibcon#read 6, iclass 6, count 0 2006.169.08:02:46.16#ibcon#end of sib2, iclass 6, count 0 2006.169.08:02:46.16#ibcon#*mode == 0, iclass 6, count 0 2006.169.08:02:46.16#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.169.08:02:46.16#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.08:02:46.16#ibcon#*before write, iclass 6, count 0 2006.169.08:02:46.16#ibcon#enter sib2, iclass 6, count 0 2006.169.08:02:46.16#ibcon#flushed, iclass 6, count 0 2006.169.08:02:46.16#ibcon#about to write, iclass 6, count 0 2006.169.08:02:46.16#ibcon#wrote, iclass 6, count 0 2006.169.08:02:46.16#ibcon#about to read 3, iclass 6, count 0 2006.169.08:02:46.20#ibcon#read 3, iclass 6, count 0 2006.169.08:02:46.20#ibcon#about to read 4, iclass 6, count 0 2006.169.08:02:46.20#ibcon#read 4, iclass 6, count 0 2006.169.08:02:46.20#ibcon#about to read 5, iclass 6, count 0 2006.169.08:02:46.20#ibcon#read 5, iclass 6, count 0 2006.169.08:02:46.20#ibcon#about to read 6, iclass 6, count 0 2006.169.08:02:46.20#ibcon#read 6, iclass 6, count 0 2006.169.08:02:46.20#ibcon#end of sib2, iclass 6, count 0 2006.169.08:02:46.20#ibcon#*after write, iclass 6, count 0 2006.169.08:02:46.20#ibcon#*before return 0, iclass 6, count 0 2006.169.08:02:46.20#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:02:46.20#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:02:46.20#ibcon#about to clear, iclass 6 cls_cnt 0 2006.169.08:02:46.20#ibcon#cleared, iclass 6 cls_cnt 0 2006.169.08:02:46.20$vc4f8/va=5,7 2006.169.08:02:46.20#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.169.08:02:46.20#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.169.08:02:46.20#ibcon#ireg 11 cls_cnt 2 2006.169.08:02:46.20#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:02:46.26#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:02:46.26#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:02:46.26#ibcon#enter wrdev, iclass 10, count 2 2006.169.08:02:46.26#ibcon#first serial, iclass 10, count 2 2006.169.08:02:46.26#ibcon#enter sib2, iclass 10, count 2 2006.169.08:02:46.26#ibcon#flushed, iclass 10, count 2 2006.169.08:02:46.26#ibcon#about to write, iclass 10, count 2 2006.169.08:02:46.26#ibcon#wrote, iclass 10, count 2 2006.169.08:02:46.26#ibcon#about to read 3, iclass 10, count 2 2006.169.08:02:46.28#ibcon#read 3, iclass 10, count 2 2006.169.08:02:46.28#ibcon#about to read 4, iclass 10, count 2 2006.169.08:02:46.28#ibcon#read 4, iclass 10, count 2 2006.169.08:02:46.28#ibcon#about to read 5, iclass 10, count 2 2006.169.08:02:46.28#ibcon#read 5, iclass 10, count 2 2006.169.08:02:46.28#ibcon#about to read 6, iclass 10, count 2 2006.169.08:02:46.28#ibcon#read 6, iclass 10, count 2 2006.169.08:02:46.28#ibcon#end of sib2, iclass 10, count 2 2006.169.08:02:46.28#ibcon#*mode == 0, iclass 10, count 2 2006.169.08:02:46.28#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.169.08:02:46.28#ibcon#[25=AT05-07\r\n] 2006.169.08:02:46.28#ibcon#*before write, iclass 10, count 2 2006.169.08:02:46.28#ibcon#enter sib2, iclass 10, count 2 2006.169.08:02:46.28#ibcon#flushed, iclass 10, count 2 2006.169.08:02:46.28#ibcon#about to write, iclass 10, count 2 2006.169.08:02:46.28#ibcon#wrote, iclass 10, count 2 2006.169.08:02:46.28#ibcon#about to read 3, iclass 10, count 2 2006.169.08:02:46.31#ibcon#read 3, iclass 10, count 2 2006.169.08:02:46.31#ibcon#about to read 4, iclass 10, count 2 2006.169.08:02:46.31#ibcon#read 4, iclass 10, count 2 2006.169.08:02:46.31#ibcon#about to read 5, iclass 10, count 2 2006.169.08:02:46.31#ibcon#read 5, iclass 10, count 2 2006.169.08:02:46.31#ibcon#about to read 6, iclass 10, count 2 2006.169.08:02:46.31#ibcon#read 6, iclass 10, count 2 2006.169.08:02:46.31#ibcon#end of sib2, iclass 10, count 2 2006.169.08:02:46.31#ibcon#*after write, iclass 10, count 2 2006.169.08:02:46.31#ibcon#*before return 0, iclass 10, count 2 2006.169.08:02:46.31#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:02:46.31#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:02:46.31#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.169.08:02:46.31#ibcon#ireg 7 cls_cnt 0 2006.169.08:02:46.31#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:02:46.43#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:02:46.43#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:02:46.43#ibcon#enter wrdev, iclass 10, count 0 2006.169.08:02:46.43#ibcon#first serial, iclass 10, count 0 2006.169.08:02:46.43#ibcon#enter sib2, iclass 10, count 0 2006.169.08:02:46.43#ibcon#flushed, iclass 10, count 0 2006.169.08:02:46.43#ibcon#about to write, iclass 10, count 0 2006.169.08:02:46.43#ibcon#wrote, iclass 10, count 0 2006.169.08:02:46.43#ibcon#about to read 3, iclass 10, count 0 2006.169.08:02:46.45#ibcon#read 3, iclass 10, count 0 2006.169.08:02:46.45#ibcon#about to read 4, iclass 10, count 0 2006.169.08:02:46.45#ibcon#read 4, iclass 10, count 0 2006.169.08:02:46.45#ibcon#about to read 5, iclass 10, count 0 2006.169.08:02:46.45#ibcon#read 5, iclass 10, count 0 2006.169.08:02:46.45#ibcon#about to read 6, iclass 10, count 0 2006.169.08:02:46.45#ibcon#read 6, iclass 10, count 0 2006.169.08:02:46.45#ibcon#end of sib2, iclass 10, count 0 2006.169.08:02:46.45#ibcon#*mode == 0, iclass 10, count 0 2006.169.08:02:46.45#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.169.08:02:46.45#ibcon#[25=USB\r\n] 2006.169.08:02:46.45#ibcon#*before write, iclass 10, count 0 2006.169.08:02:46.45#ibcon#enter sib2, iclass 10, count 0 2006.169.08:02:46.45#ibcon#flushed, iclass 10, count 0 2006.169.08:02:46.45#ibcon#about to write, iclass 10, count 0 2006.169.08:02:46.45#ibcon#wrote, iclass 10, count 0 2006.169.08:02:46.45#ibcon#about to read 3, iclass 10, count 0 2006.169.08:02:46.48#ibcon#read 3, iclass 10, count 0 2006.169.08:02:46.48#ibcon#about to read 4, iclass 10, count 0 2006.169.08:02:46.48#ibcon#read 4, iclass 10, count 0 2006.169.08:02:46.48#ibcon#about to read 5, iclass 10, count 0 2006.169.08:02:46.48#ibcon#read 5, iclass 10, count 0 2006.169.08:02:46.48#ibcon#about to read 6, iclass 10, count 0 2006.169.08:02:46.48#ibcon#read 6, iclass 10, count 0 2006.169.08:02:46.48#ibcon#end of sib2, iclass 10, count 0 2006.169.08:02:46.48#ibcon#*after write, iclass 10, count 0 2006.169.08:02:46.48#ibcon#*before return 0, iclass 10, count 0 2006.169.08:02:46.48#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:02:46.48#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:02:46.48#ibcon#about to clear, iclass 10 cls_cnt 0 2006.169.08:02:46.48#ibcon#cleared, iclass 10 cls_cnt 0 2006.169.08:02:46.48$vc4f8/valo=6,772.99 2006.169.08:02:46.48#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.169.08:02:46.48#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.169.08:02:46.48#ibcon#ireg 17 cls_cnt 0 2006.169.08:02:46.48#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:02:46.48#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:02:46.48#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:02:46.48#ibcon#enter wrdev, iclass 12, count 0 2006.169.08:02:46.48#ibcon#first serial, iclass 12, count 0 2006.169.08:02:46.48#ibcon#enter sib2, iclass 12, count 0 2006.169.08:02:46.48#ibcon#flushed, iclass 12, count 0 2006.169.08:02:46.48#ibcon#about to write, iclass 12, count 0 2006.169.08:02:46.48#ibcon#wrote, iclass 12, count 0 2006.169.08:02:46.48#ibcon#about to read 3, iclass 12, count 0 2006.169.08:02:46.50#ibcon#read 3, iclass 12, count 0 2006.169.08:02:46.50#ibcon#about to read 4, iclass 12, count 0 2006.169.08:02:46.50#ibcon#read 4, iclass 12, count 0 2006.169.08:02:46.50#ibcon#about to read 5, iclass 12, count 0 2006.169.08:02:46.50#ibcon#read 5, iclass 12, count 0 2006.169.08:02:46.50#ibcon#about to read 6, iclass 12, count 0 2006.169.08:02:46.50#ibcon#read 6, iclass 12, count 0 2006.169.08:02:46.50#ibcon#end of sib2, iclass 12, count 0 2006.169.08:02:46.50#ibcon#*mode == 0, iclass 12, count 0 2006.169.08:02:46.50#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.169.08:02:46.50#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.08:02:46.50#ibcon#*before write, iclass 12, count 0 2006.169.08:02:46.50#ibcon#enter sib2, iclass 12, count 0 2006.169.08:02:46.50#ibcon#flushed, iclass 12, count 0 2006.169.08:02:46.50#ibcon#about to write, iclass 12, count 0 2006.169.08:02:46.50#ibcon#wrote, iclass 12, count 0 2006.169.08:02:46.50#ibcon#about to read 3, iclass 12, count 0 2006.169.08:02:46.54#ibcon#read 3, iclass 12, count 0 2006.169.08:02:46.54#ibcon#about to read 4, iclass 12, count 0 2006.169.08:02:46.54#ibcon#read 4, iclass 12, count 0 2006.169.08:02:46.54#ibcon#about to read 5, iclass 12, count 0 2006.169.08:02:46.54#ibcon#read 5, iclass 12, count 0 2006.169.08:02:46.54#ibcon#about to read 6, iclass 12, count 0 2006.169.08:02:46.54#ibcon#read 6, iclass 12, count 0 2006.169.08:02:46.54#ibcon#end of sib2, iclass 12, count 0 2006.169.08:02:46.54#ibcon#*after write, iclass 12, count 0 2006.169.08:02:46.54#ibcon#*before return 0, iclass 12, count 0 2006.169.08:02:46.54#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:02:46.54#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:02:46.54#ibcon#about to clear, iclass 12 cls_cnt 0 2006.169.08:02:46.54#ibcon#cleared, iclass 12 cls_cnt 0 2006.169.08:02:46.54$vc4f8/va=6,6 2006.169.08:02:46.54#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.169.08:02:46.54#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.169.08:02:46.54#ibcon#ireg 11 cls_cnt 2 2006.169.08:02:46.54#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.169.08:02:46.60#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.169.08:02:46.60#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.169.08:02:46.60#ibcon#enter wrdev, iclass 14, count 2 2006.169.08:02:46.60#ibcon#first serial, iclass 14, count 2 2006.169.08:02:46.60#ibcon#enter sib2, iclass 14, count 2 2006.169.08:02:46.60#ibcon#flushed, iclass 14, count 2 2006.169.08:02:46.60#ibcon#about to write, iclass 14, count 2 2006.169.08:02:46.60#ibcon#wrote, iclass 14, count 2 2006.169.08:02:46.60#ibcon#about to read 3, iclass 14, count 2 2006.169.08:02:46.62#ibcon#read 3, iclass 14, count 2 2006.169.08:02:46.62#ibcon#about to read 4, iclass 14, count 2 2006.169.08:02:46.62#ibcon#read 4, iclass 14, count 2 2006.169.08:02:46.62#ibcon#about to read 5, iclass 14, count 2 2006.169.08:02:46.62#ibcon#read 5, iclass 14, count 2 2006.169.08:02:46.62#ibcon#about to read 6, iclass 14, count 2 2006.169.08:02:46.62#ibcon#read 6, iclass 14, count 2 2006.169.08:02:46.62#ibcon#end of sib2, iclass 14, count 2 2006.169.08:02:46.62#ibcon#*mode == 0, iclass 14, count 2 2006.169.08:02:46.62#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.169.08:02:46.62#ibcon#[25=AT06-06\r\n] 2006.169.08:02:46.62#ibcon#*before write, iclass 14, count 2 2006.169.08:02:46.62#ibcon#enter sib2, iclass 14, count 2 2006.169.08:02:46.62#ibcon#flushed, iclass 14, count 2 2006.169.08:02:46.62#ibcon#about to write, iclass 14, count 2 2006.169.08:02:46.62#ibcon#wrote, iclass 14, count 2 2006.169.08:02:46.62#ibcon#about to read 3, iclass 14, count 2 2006.169.08:02:46.65#ibcon#read 3, iclass 14, count 2 2006.169.08:02:46.65#ibcon#about to read 4, iclass 14, count 2 2006.169.08:02:46.65#ibcon#read 4, iclass 14, count 2 2006.169.08:02:46.65#ibcon#about to read 5, iclass 14, count 2 2006.169.08:02:46.65#ibcon#read 5, iclass 14, count 2 2006.169.08:02:46.65#ibcon#about to read 6, iclass 14, count 2 2006.169.08:02:46.65#ibcon#read 6, iclass 14, count 2 2006.169.08:02:46.65#ibcon#end of sib2, iclass 14, count 2 2006.169.08:02:46.65#ibcon#*after write, iclass 14, count 2 2006.169.08:02:46.65#ibcon#*before return 0, iclass 14, count 2 2006.169.08:02:46.65#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.169.08:02:46.65#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.169.08:02:46.65#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.169.08:02:46.65#ibcon#ireg 7 cls_cnt 0 2006.169.08:02:46.65#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.169.08:02:46.77#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.169.08:02:46.77#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.169.08:02:46.77#ibcon#enter wrdev, iclass 14, count 0 2006.169.08:02:46.77#ibcon#first serial, iclass 14, count 0 2006.169.08:02:46.77#ibcon#enter sib2, iclass 14, count 0 2006.169.08:02:46.77#ibcon#flushed, iclass 14, count 0 2006.169.08:02:46.77#ibcon#about to write, iclass 14, count 0 2006.169.08:02:46.77#ibcon#wrote, iclass 14, count 0 2006.169.08:02:46.77#ibcon#about to read 3, iclass 14, count 0 2006.169.08:02:46.79#ibcon#read 3, iclass 14, count 0 2006.169.08:02:46.79#ibcon#about to read 4, iclass 14, count 0 2006.169.08:02:46.79#ibcon#read 4, iclass 14, count 0 2006.169.08:02:46.79#ibcon#about to read 5, iclass 14, count 0 2006.169.08:02:46.79#ibcon#read 5, iclass 14, count 0 2006.169.08:02:46.79#ibcon#about to read 6, iclass 14, count 0 2006.169.08:02:46.79#ibcon#read 6, iclass 14, count 0 2006.169.08:02:46.79#ibcon#end of sib2, iclass 14, count 0 2006.169.08:02:46.79#ibcon#*mode == 0, iclass 14, count 0 2006.169.08:02:46.79#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.169.08:02:46.79#ibcon#[25=USB\r\n] 2006.169.08:02:46.79#ibcon#*before write, iclass 14, count 0 2006.169.08:02:46.79#ibcon#enter sib2, iclass 14, count 0 2006.169.08:02:46.79#ibcon#flushed, iclass 14, count 0 2006.169.08:02:46.79#ibcon#about to write, iclass 14, count 0 2006.169.08:02:46.79#ibcon#wrote, iclass 14, count 0 2006.169.08:02:46.79#ibcon#about to read 3, iclass 14, count 0 2006.169.08:02:46.82#ibcon#read 3, iclass 14, count 0 2006.169.08:02:46.82#ibcon#about to read 4, iclass 14, count 0 2006.169.08:02:46.82#ibcon#read 4, iclass 14, count 0 2006.169.08:02:46.82#ibcon#about to read 5, iclass 14, count 0 2006.169.08:02:46.82#ibcon#read 5, iclass 14, count 0 2006.169.08:02:46.82#ibcon#about to read 6, iclass 14, count 0 2006.169.08:02:46.82#ibcon#read 6, iclass 14, count 0 2006.169.08:02:46.82#ibcon#end of sib2, iclass 14, count 0 2006.169.08:02:46.82#ibcon#*after write, iclass 14, count 0 2006.169.08:02:46.82#ibcon#*before return 0, iclass 14, count 0 2006.169.08:02:46.82#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.169.08:02:46.82#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.169.08:02:46.82#ibcon#about to clear, iclass 14 cls_cnt 0 2006.169.08:02:46.82#ibcon#cleared, iclass 14 cls_cnt 0 2006.169.08:02:46.82$vc4f8/valo=7,832.99 2006.169.08:02:46.82#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.169.08:02:46.82#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.169.08:02:46.82#ibcon#ireg 17 cls_cnt 0 2006.169.08:02:46.82#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:02:46.82#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:02:46.82#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:02:46.82#ibcon#enter wrdev, iclass 16, count 0 2006.169.08:02:46.82#ibcon#first serial, iclass 16, count 0 2006.169.08:02:46.82#ibcon#enter sib2, iclass 16, count 0 2006.169.08:02:46.82#ibcon#flushed, iclass 16, count 0 2006.169.08:02:46.82#ibcon#about to write, iclass 16, count 0 2006.169.08:02:46.82#ibcon#wrote, iclass 16, count 0 2006.169.08:02:46.82#ibcon#about to read 3, iclass 16, count 0 2006.169.08:02:46.84#ibcon#read 3, iclass 16, count 0 2006.169.08:02:46.84#ibcon#about to read 4, iclass 16, count 0 2006.169.08:02:46.84#ibcon#read 4, iclass 16, count 0 2006.169.08:02:46.84#ibcon#about to read 5, iclass 16, count 0 2006.169.08:02:46.84#ibcon#read 5, iclass 16, count 0 2006.169.08:02:46.84#ibcon#about to read 6, iclass 16, count 0 2006.169.08:02:46.84#ibcon#read 6, iclass 16, count 0 2006.169.08:02:46.84#ibcon#end of sib2, iclass 16, count 0 2006.169.08:02:46.84#ibcon#*mode == 0, iclass 16, count 0 2006.169.08:02:46.84#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.169.08:02:46.84#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.08:02:46.84#ibcon#*before write, iclass 16, count 0 2006.169.08:02:46.84#ibcon#enter sib2, iclass 16, count 0 2006.169.08:02:46.84#ibcon#flushed, iclass 16, count 0 2006.169.08:02:46.84#ibcon#about to write, iclass 16, count 0 2006.169.08:02:46.84#ibcon#wrote, iclass 16, count 0 2006.169.08:02:46.84#ibcon#about to read 3, iclass 16, count 0 2006.169.08:02:46.88#ibcon#read 3, iclass 16, count 0 2006.169.08:02:46.88#ibcon#about to read 4, iclass 16, count 0 2006.169.08:02:46.88#ibcon#read 4, iclass 16, count 0 2006.169.08:02:46.88#ibcon#about to read 5, iclass 16, count 0 2006.169.08:02:46.88#ibcon#read 5, iclass 16, count 0 2006.169.08:02:46.88#ibcon#about to read 6, iclass 16, count 0 2006.169.08:02:46.88#ibcon#read 6, iclass 16, count 0 2006.169.08:02:46.88#ibcon#end of sib2, iclass 16, count 0 2006.169.08:02:46.88#ibcon#*after write, iclass 16, count 0 2006.169.08:02:46.88#ibcon#*before return 0, iclass 16, count 0 2006.169.08:02:46.88#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:02:46.88#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:02:46.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.169.08:02:46.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.169.08:02:46.88$vc4f8/va=7,6 2006.169.08:02:46.88#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.169.08:02:46.88#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.169.08:02:46.88#ibcon#ireg 11 cls_cnt 2 2006.169.08:02:46.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.169.08:02:46.94#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.169.08:02:46.94#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.169.08:02:46.94#ibcon#enter wrdev, iclass 18, count 2 2006.169.08:02:46.94#ibcon#first serial, iclass 18, count 2 2006.169.08:02:46.94#ibcon#enter sib2, iclass 18, count 2 2006.169.08:02:46.94#ibcon#flushed, iclass 18, count 2 2006.169.08:02:46.94#ibcon#about to write, iclass 18, count 2 2006.169.08:02:46.94#ibcon#wrote, iclass 18, count 2 2006.169.08:02:46.94#ibcon#about to read 3, iclass 18, count 2 2006.169.08:02:46.96#ibcon#read 3, iclass 18, count 2 2006.169.08:02:46.96#ibcon#about to read 4, iclass 18, count 2 2006.169.08:02:46.96#ibcon#read 4, iclass 18, count 2 2006.169.08:02:46.96#ibcon#about to read 5, iclass 18, count 2 2006.169.08:02:46.96#ibcon#read 5, iclass 18, count 2 2006.169.08:02:46.96#ibcon#about to read 6, iclass 18, count 2 2006.169.08:02:46.96#ibcon#read 6, iclass 18, count 2 2006.169.08:02:46.96#ibcon#end of sib2, iclass 18, count 2 2006.169.08:02:46.96#ibcon#*mode == 0, iclass 18, count 2 2006.169.08:02:46.96#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.169.08:02:46.96#ibcon#[25=AT07-06\r\n] 2006.169.08:02:46.96#ibcon#*before write, iclass 18, count 2 2006.169.08:02:46.96#ibcon#enter sib2, iclass 18, count 2 2006.169.08:02:46.96#ibcon#flushed, iclass 18, count 2 2006.169.08:02:46.96#ibcon#about to write, iclass 18, count 2 2006.169.08:02:46.96#ibcon#wrote, iclass 18, count 2 2006.169.08:02:46.96#ibcon#about to read 3, iclass 18, count 2 2006.169.08:02:46.99#ibcon#read 3, iclass 18, count 2 2006.169.08:02:46.99#ibcon#about to read 4, iclass 18, count 2 2006.169.08:02:46.99#ibcon#read 4, iclass 18, count 2 2006.169.08:02:46.99#ibcon#about to read 5, iclass 18, count 2 2006.169.08:02:46.99#ibcon#read 5, iclass 18, count 2 2006.169.08:02:46.99#ibcon#about to read 6, iclass 18, count 2 2006.169.08:02:46.99#ibcon#read 6, iclass 18, count 2 2006.169.08:02:46.99#ibcon#end of sib2, iclass 18, count 2 2006.169.08:02:46.99#ibcon#*after write, iclass 18, count 2 2006.169.08:02:46.99#ibcon#*before return 0, iclass 18, count 2 2006.169.08:02:46.99#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.169.08:02:46.99#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.169.08:02:46.99#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.169.08:02:46.99#ibcon#ireg 7 cls_cnt 0 2006.169.08:02:46.99#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.169.08:02:47.11#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.169.08:02:47.11#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.169.08:02:47.11#ibcon#enter wrdev, iclass 18, count 0 2006.169.08:02:47.11#ibcon#first serial, iclass 18, count 0 2006.169.08:02:47.11#ibcon#enter sib2, iclass 18, count 0 2006.169.08:02:47.11#ibcon#flushed, iclass 18, count 0 2006.169.08:02:47.11#ibcon#about to write, iclass 18, count 0 2006.169.08:02:47.11#ibcon#wrote, iclass 18, count 0 2006.169.08:02:47.11#ibcon#about to read 3, iclass 18, count 0 2006.169.08:02:47.13#ibcon#read 3, iclass 18, count 0 2006.169.08:02:47.13#ibcon#about to read 4, iclass 18, count 0 2006.169.08:02:47.13#ibcon#read 4, iclass 18, count 0 2006.169.08:02:47.13#ibcon#about to read 5, iclass 18, count 0 2006.169.08:02:47.13#ibcon#read 5, iclass 18, count 0 2006.169.08:02:47.13#ibcon#about to read 6, iclass 18, count 0 2006.169.08:02:47.13#ibcon#read 6, iclass 18, count 0 2006.169.08:02:47.13#ibcon#end of sib2, iclass 18, count 0 2006.169.08:02:47.13#ibcon#*mode == 0, iclass 18, count 0 2006.169.08:02:47.13#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.169.08:02:47.13#ibcon#[25=USB\r\n] 2006.169.08:02:47.13#ibcon#*before write, iclass 18, count 0 2006.169.08:02:47.13#ibcon#enter sib2, iclass 18, count 0 2006.169.08:02:47.13#ibcon#flushed, iclass 18, count 0 2006.169.08:02:47.13#ibcon#about to write, iclass 18, count 0 2006.169.08:02:47.13#ibcon#wrote, iclass 18, count 0 2006.169.08:02:47.13#ibcon#about to read 3, iclass 18, count 0 2006.169.08:02:47.16#ibcon#read 3, iclass 18, count 0 2006.169.08:02:47.16#ibcon#about to read 4, iclass 18, count 0 2006.169.08:02:47.16#ibcon#read 4, iclass 18, count 0 2006.169.08:02:47.16#ibcon#about to read 5, iclass 18, count 0 2006.169.08:02:47.16#ibcon#read 5, iclass 18, count 0 2006.169.08:02:47.16#ibcon#about to read 6, iclass 18, count 0 2006.169.08:02:47.16#ibcon#read 6, iclass 18, count 0 2006.169.08:02:47.16#ibcon#end of sib2, iclass 18, count 0 2006.169.08:02:47.16#ibcon#*after write, iclass 18, count 0 2006.169.08:02:47.16#ibcon#*before return 0, iclass 18, count 0 2006.169.08:02:47.16#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.169.08:02:47.16#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.169.08:02:47.16#ibcon#about to clear, iclass 18 cls_cnt 0 2006.169.08:02:47.16#ibcon#cleared, iclass 18 cls_cnt 0 2006.169.08:02:47.16$vc4f8/valo=8,852.99 2006.169.08:02:47.16#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.169.08:02:47.16#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.169.08:02:47.16#ibcon#ireg 17 cls_cnt 0 2006.169.08:02:47.16#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:02:47.16#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:02:47.16#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:02:47.16#ibcon#enter wrdev, iclass 20, count 0 2006.169.08:02:47.16#ibcon#first serial, iclass 20, count 0 2006.169.08:02:47.16#ibcon#enter sib2, iclass 20, count 0 2006.169.08:02:47.16#ibcon#flushed, iclass 20, count 0 2006.169.08:02:47.16#ibcon#about to write, iclass 20, count 0 2006.169.08:02:47.16#ibcon#wrote, iclass 20, count 0 2006.169.08:02:47.16#ibcon#about to read 3, iclass 20, count 0 2006.169.08:02:47.18#ibcon#read 3, iclass 20, count 0 2006.169.08:02:47.18#ibcon#about to read 4, iclass 20, count 0 2006.169.08:02:47.18#ibcon#read 4, iclass 20, count 0 2006.169.08:02:47.18#ibcon#about to read 5, iclass 20, count 0 2006.169.08:02:47.18#ibcon#read 5, iclass 20, count 0 2006.169.08:02:47.18#ibcon#about to read 6, iclass 20, count 0 2006.169.08:02:47.18#ibcon#read 6, iclass 20, count 0 2006.169.08:02:47.18#ibcon#end of sib2, iclass 20, count 0 2006.169.08:02:47.18#ibcon#*mode == 0, iclass 20, count 0 2006.169.08:02:47.18#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.169.08:02:47.18#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.08:02:47.18#ibcon#*before write, iclass 20, count 0 2006.169.08:02:47.18#ibcon#enter sib2, iclass 20, count 0 2006.169.08:02:47.18#ibcon#flushed, iclass 20, count 0 2006.169.08:02:47.18#ibcon#about to write, iclass 20, count 0 2006.169.08:02:47.18#ibcon#wrote, iclass 20, count 0 2006.169.08:02:47.18#ibcon#about to read 3, iclass 20, count 0 2006.169.08:02:47.22#ibcon#read 3, iclass 20, count 0 2006.169.08:02:47.22#ibcon#about to read 4, iclass 20, count 0 2006.169.08:02:47.22#ibcon#read 4, iclass 20, count 0 2006.169.08:02:47.22#ibcon#about to read 5, iclass 20, count 0 2006.169.08:02:47.22#ibcon#read 5, iclass 20, count 0 2006.169.08:02:47.22#ibcon#about to read 6, iclass 20, count 0 2006.169.08:02:47.22#ibcon#read 6, iclass 20, count 0 2006.169.08:02:47.22#ibcon#end of sib2, iclass 20, count 0 2006.169.08:02:47.22#ibcon#*after write, iclass 20, count 0 2006.169.08:02:47.22#ibcon#*before return 0, iclass 20, count 0 2006.169.08:02:47.22#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:02:47.22#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:02:47.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.169.08:02:47.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.169.08:02:47.22$vc4f8/va=8,7 2006.169.08:02:47.22#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.169.08:02:47.22#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.169.08:02:47.22#ibcon#ireg 11 cls_cnt 2 2006.169.08:02:47.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:02:47.28#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:02:47.28#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:02:47.28#ibcon#enter wrdev, iclass 22, count 2 2006.169.08:02:47.28#ibcon#first serial, iclass 22, count 2 2006.169.08:02:47.28#ibcon#enter sib2, iclass 22, count 2 2006.169.08:02:47.28#ibcon#flushed, iclass 22, count 2 2006.169.08:02:47.28#ibcon#about to write, iclass 22, count 2 2006.169.08:02:47.28#ibcon#wrote, iclass 22, count 2 2006.169.08:02:47.28#ibcon#about to read 3, iclass 22, count 2 2006.169.08:02:47.30#ibcon#read 3, iclass 22, count 2 2006.169.08:02:47.30#ibcon#about to read 4, iclass 22, count 2 2006.169.08:02:47.30#ibcon#read 4, iclass 22, count 2 2006.169.08:02:47.30#ibcon#about to read 5, iclass 22, count 2 2006.169.08:02:47.30#ibcon#read 5, iclass 22, count 2 2006.169.08:02:47.30#ibcon#about to read 6, iclass 22, count 2 2006.169.08:02:47.30#ibcon#read 6, iclass 22, count 2 2006.169.08:02:47.30#ibcon#end of sib2, iclass 22, count 2 2006.169.08:02:47.30#ibcon#*mode == 0, iclass 22, count 2 2006.169.08:02:47.30#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.169.08:02:47.30#ibcon#[25=AT08-07\r\n] 2006.169.08:02:47.30#ibcon#*before write, iclass 22, count 2 2006.169.08:02:47.30#ibcon#enter sib2, iclass 22, count 2 2006.169.08:02:47.30#ibcon#flushed, iclass 22, count 2 2006.169.08:02:47.30#ibcon#about to write, iclass 22, count 2 2006.169.08:02:47.30#ibcon#wrote, iclass 22, count 2 2006.169.08:02:47.30#ibcon#about to read 3, iclass 22, count 2 2006.169.08:02:47.33#ibcon#read 3, iclass 22, count 2 2006.169.08:02:47.33#ibcon#about to read 4, iclass 22, count 2 2006.169.08:02:47.33#ibcon#read 4, iclass 22, count 2 2006.169.08:02:47.33#ibcon#about to read 5, iclass 22, count 2 2006.169.08:02:47.33#ibcon#read 5, iclass 22, count 2 2006.169.08:02:47.33#ibcon#about to read 6, iclass 22, count 2 2006.169.08:02:47.33#ibcon#read 6, iclass 22, count 2 2006.169.08:02:47.33#ibcon#end of sib2, iclass 22, count 2 2006.169.08:02:47.33#ibcon#*after write, iclass 22, count 2 2006.169.08:02:47.33#ibcon#*before return 0, iclass 22, count 2 2006.169.08:02:47.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:02:47.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:02:47.33#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.169.08:02:47.33#ibcon#ireg 7 cls_cnt 0 2006.169.08:02:47.33#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:02:47.41#abcon#<5=/04 3.1 5.9 18.121001004.0\r\n> 2006.169.08:02:47.43#abcon#{5=INTERFACE CLEAR} 2006.169.08:02:47.45#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:02:47.45#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:02:47.45#ibcon#enter wrdev, iclass 22, count 0 2006.169.08:02:47.45#ibcon#first serial, iclass 22, count 0 2006.169.08:02:47.45#ibcon#enter sib2, iclass 22, count 0 2006.169.08:02:47.45#ibcon#flushed, iclass 22, count 0 2006.169.08:02:47.45#ibcon#about to write, iclass 22, count 0 2006.169.08:02:47.45#ibcon#wrote, iclass 22, count 0 2006.169.08:02:47.45#ibcon#about to read 3, iclass 22, count 0 2006.169.08:02:47.47#ibcon#read 3, iclass 22, count 0 2006.169.08:02:47.47#ibcon#about to read 4, iclass 22, count 0 2006.169.08:02:47.47#ibcon#read 4, iclass 22, count 0 2006.169.08:02:47.47#ibcon#about to read 5, iclass 22, count 0 2006.169.08:02:47.47#ibcon#read 5, iclass 22, count 0 2006.169.08:02:47.47#ibcon#about to read 6, iclass 22, count 0 2006.169.08:02:47.47#ibcon#read 6, iclass 22, count 0 2006.169.08:02:47.47#ibcon#end of sib2, iclass 22, count 0 2006.169.08:02:47.47#ibcon#*mode == 0, iclass 22, count 0 2006.169.08:02:47.47#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.169.08:02:47.47#ibcon#[25=USB\r\n] 2006.169.08:02:47.47#ibcon#*before write, iclass 22, count 0 2006.169.08:02:47.47#ibcon#enter sib2, iclass 22, count 0 2006.169.08:02:47.47#ibcon#flushed, iclass 22, count 0 2006.169.08:02:47.47#ibcon#about to write, iclass 22, count 0 2006.169.08:02:47.47#ibcon#wrote, iclass 22, count 0 2006.169.08:02:47.47#ibcon#about to read 3, iclass 22, count 0 2006.169.08:02:47.49#abcon#[5=S1D000X0/0*\r\n] 2006.169.08:02:47.50#ibcon#read 3, iclass 22, count 0 2006.169.08:02:47.50#ibcon#about to read 4, iclass 22, count 0 2006.169.08:02:47.50#ibcon#read 4, iclass 22, count 0 2006.169.08:02:47.50#ibcon#about to read 5, iclass 22, count 0 2006.169.08:02:47.50#ibcon#read 5, iclass 22, count 0 2006.169.08:02:47.50#ibcon#about to read 6, iclass 22, count 0 2006.169.08:02:47.50#ibcon#read 6, iclass 22, count 0 2006.169.08:02:47.50#ibcon#end of sib2, iclass 22, count 0 2006.169.08:02:47.50#ibcon#*after write, iclass 22, count 0 2006.169.08:02:47.50#ibcon#*before return 0, iclass 22, count 0 2006.169.08:02:47.50#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:02:47.50#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:02:47.50#ibcon#about to clear, iclass 22 cls_cnt 0 2006.169.08:02:47.50#ibcon#cleared, iclass 22 cls_cnt 0 2006.169.08:02:47.50$vc4f8/vblo=1,632.99 2006.169.08:02:47.50#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.169.08:02:47.50#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.169.08:02:47.50#ibcon#ireg 17 cls_cnt 0 2006.169.08:02:47.50#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:02:47.50#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:02:47.50#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:02:47.50#ibcon#enter wrdev, iclass 28, count 0 2006.169.08:02:47.50#ibcon#first serial, iclass 28, count 0 2006.169.08:02:47.50#ibcon#enter sib2, iclass 28, count 0 2006.169.08:02:47.50#ibcon#flushed, iclass 28, count 0 2006.169.08:02:47.50#ibcon#about to write, iclass 28, count 0 2006.169.08:02:47.50#ibcon#wrote, iclass 28, count 0 2006.169.08:02:47.50#ibcon#about to read 3, iclass 28, count 0 2006.169.08:02:47.52#ibcon#read 3, iclass 28, count 0 2006.169.08:02:47.52#ibcon#about to read 4, iclass 28, count 0 2006.169.08:02:47.52#ibcon#read 4, iclass 28, count 0 2006.169.08:02:47.52#ibcon#about to read 5, iclass 28, count 0 2006.169.08:02:47.52#ibcon#read 5, iclass 28, count 0 2006.169.08:02:47.52#ibcon#about to read 6, iclass 28, count 0 2006.169.08:02:47.52#ibcon#read 6, iclass 28, count 0 2006.169.08:02:47.52#ibcon#end of sib2, iclass 28, count 0 2006.169.08:02:47.52#ibcon#*mode == 0, iclass 28, count 0 2006.169.08:02:47.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.169.08:02:47.52#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.08:02:47.52#ibcon#*before write, iclass 28, count 0 2006.169.08:02:47.52#ibcon#enter sib2, iclass 28, count 0 2006.169.08:02:47.52#ibcon#flushed, iclass 28, count 0 2006.169.08:02:47.52#ibcon#about to write, iclass 28, count 0 2006.169.08:02:47.52#ibcon#wrote, iclass 28, count 0 2006.169.08:02:47.52#ibcon#about to read 3, iclass 28, count 0 2006.169.08:02:47.56#ibcon#read 3, iclass 28, count 0 2006.169.08:02:47.56#ibcon#about to read 4, iclass 28, count 0 2006.169.08:02:47.56#ibcon#read 4, iclass 28, count 0 2006.169.08:02:47.56#ibcon#about to read 5, iclass 28, count 0 2006.169.08:02:47.56#ibcon#read 5, iclass 28, count 0 2006.169.08:02:47.56#ibcon#about to read 6, iclass 28, count 0 2006.169.08:02:47.56#ibcon#read 6, iclass 28, count 0 2006.169.08:02:47.56#ibcon#end of sib2, iclass 28, count 0 2006.169.08:02:47.56#ibcon#*after write, iclass 28, count 0 2006.169.08:02:47.56#ibcon#*before return 0, iclass 28, count 0 2006.169.08:02:47.56#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:02:47.56#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:02:47.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.169.08:02:47.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.169.08:02:47.56$vc4f8/vb=1,4 2006.169.08:02:47.56#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.169.08:02:47.56#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.169.08:02:47.56#ibcon#ireg 11 cls_cnt 2 2006.169.08:02:47.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:02:47.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:02:47.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:02:47.56#ibcon#enter wrdev, iclass 30, count 2 2006.169.08:02:47.56#ibcon#first serial, iclass 30, count 2 2006.169.08:02:47.56#ibcon#enter sib2, iclass 30, count 2 2006.169.08:02:47.56#ibcon#flushed, iclass 30, count 2 2006.169.08:02:47.56#ibcon#about to write, iclass 30, count 2 2006.169.08:02:47.56#ibcon#wrote, iclass 30, count 2 2006.169.08:02:47.56#ibcon#about to read 3, iclass 30, count 2 2006.169.08:02:47.58#ibcon#read 3, iclass 30, count 2 2006.169.08:02:47.58#ibcon#about to read 4, iclass 30, count 2 2006.169.08:02:47.58#ibcon#read 4, iclass 30, count 2 2006.169.08:02:47.58#ibcon#about to read 5, iclass 30, count 2 2006.169.08:02:47.58#ibcon#read 5, iclass 30, count 2 2006.169.08:02:47.58#ibcon#about to read 6, iclass 30, count 2 2006.169.08:02:47.58#ibcon#read 6, iclass 30, count 2 2006.169.08:02:47.58#ibcon#end of sib2, iclass 30, count 2 2006.169.08:02:47.58#ibcon#*mode == 0, iclass 30, count 2 2006.169.08:02:47.58#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.169.08:02:47.58#ibcon#[27=AT01-04\r\n] 2006.169.08:02:47.58#ibcon#*before write, iclass 30, count 2 2006.169.08:02:47.58#ibcon#enter sib2, iclass 30, count 2 2006.169.08:02:47.58#ibcon#flushed, iclass 30, count 2 2006.169.08:02:47.58#ibcon#about to write, iclass 30, count 2 2006.169.08:02:47.58#ibcon#wrote, iclass 30, count 2 2006.169.08:02:47.58#ibcon#about to read 3, iclass 30, count 2 2006.169.08:02:47.61#ibcon#read 3, iclass 30, count 2 2006.169.08:02:47.61#ibcon#about to read 4, iclass 30, count 2 2006.169.08:02:47.61#ibcon#read 4, iclass 30, count 2 2006.169.08:02:47.61#ibcon#about to read 5, iclass 30, count 2 2006.169.08:02:47.61#ibcon#read 5, iclass 30, count 2 2006.169.08:02:47.61#ibcon#about to read 6, iclass 30, count 2 2006.169.08:02:47.61#ibcon#read 6, iclass 30, count 2 2006.169.08:02:47.61#ibcon#end of sib2, iclass 30, count 2 2006.169.08:02:47.61#ibcon#*after write, iclass 30, count 2 2006.169.08:02:47.61#ibcon#*before return 0, iclass 30, count 2 2006.169.08:02:47.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:02:47.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:02:47.61#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.169.08:02:47.61#ibcon#ireg 7 cls_cnt 0 2006.169.08:02:47.61#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:02:47.73#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:02:47.73#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:02:47.73#ibcon#enter wrdev, iclass 30, count 0 2006.169.08:02:47.73#ibcon#first serial, iclass 30, count 0 2006.169.08:02:47.73#ibcon#enter sib2, iclass 30, count 0 2006.169.08:02:47.73#ibcon#flushed, iclass 30, count 0 2006.169.08:02:47.73#ibcon#about to write, iclass 30, count 0 2006.169.08:02:47.73#ibcon#wrote, iclass 30, count 0 2006.169.08:02:47.73#ibcon#about to read 3, iclass 30, count 0 2006.169.08:02:47.75#ibcon#read 3, iclass 30, count 0 2006.169.08:02:47.75#ibcon#about to read 4, iclass 30, count 0 2006.169.08:02:47.75#ibcon#read 4, iclass 30, count 0 2006.169.08:02:47.75#ibcon#about to read 5, iclass 30, count 0 2006.169.08:02:47.75#ibcon#read 5, iclass 30, count 0 2006.169.08:02:47.75#ibcon#about to read 6, iclass 30, count 0 2006.169.08:02:47.75#ibcon#read 6, iclass 30, count 0 2006.169.08:02:47.75#ibcon#end of sib2, iclass 30, count 0 2006.169.08:02:47.75#ibcon#*mode == 0, iclass 30, count 0 2006.169.08:02:47.75#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.169.08:02:47.75#ibcon#[27=USB\r\n] 2006.169.08:02:47.75#ibcon#*before write, iclass 30, count 0 2006.169.08:02:47.75#ibcon#enter sib2, iclass 30, count 0 2006.169.08:02:47.75#ibcon#flushed, iclass 30, count 0 2006.169.08:02:47.75#ibcon#about to write, iclass 30, count 0 2006.169.08:02:47.75#ibcon#wrote, iclass 30, count 0 2006.169.08:02:47.75#ibcon#about to read 3, iclass 30, count 0 2006.169.08:02:47.78#ibcon#read 3, iclass 30, count 0 2006.169.08:02:47.78#ibcon#about to read 4, iclass 30, count 0 2006.169.08:02:47.78#ibcon#read 4, iclass 30, count 0 2006.169.08:02:47.78#ibcon#about to read 5, iclass 30, count 0 2006.169.08:02:47.78#ibcon#read 5, iclass 30, count 0 2006.169.08:02:47.78#ibcon#about to read 6, iclass 30, count 0 2006.169.08:02:47.78#ibcon#read 6, iclass 30, count 0 2006.169.08:02:47.78#ibcon#end of sib2, iclass 30, count 0 2006.169.08:02:47.78#ibcon#*after write, iclass 30, count 0 2006.169.08:02:47.78#ibcon#*before return 0, iclass 30, count 0 2006.169.08:02:47.78#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:02:47.78#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:02:47.78#ibcon#about to clear, iclass 30 cls_cnt 0 2006.169.08:02:47.78#ibcon#cleared, iclass 30 cls_cnt 0 2006.169.08:02:47.78$vc4f8/vblo=2,640.99 2006.169.08:02:47.78#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.169.08:02:47.78#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.169.08:02:47.78#ibcon#ireg 17 cls_cnt 0 2006.169.08:02:47.78#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:02:47.78#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:02:47.78#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:02:47.78#ibcon#enter wrdev, iclass 32, count 0 2006.169.08:02:47.78#ibcon#first serial, iclass 32, count 0 2006.169.08:02:47.78#ibcon#enter sib2, iclass 32, count 0 2006.169.08:02:47.78#ibcon#flushed, iclass 32, count 0 2006.169.08:02:47.78#ibcon#about to write, iclass 32, count 0 2006.169.08:02:47.78#ibcon#wrote, iclass 32, count 0 2006.169.08:02:47.78#ibcon#about to read 3, iclass 32, count 0 2006.169.08:02:47.80#ibcon#read 3, iclass 32, count 0 2006.169.08:02:47.80#ibcon#about to read 4, iclass 32, count 0 2006.169.08:02:47.80#ibcon#read 4, iclass 32, count 0 2006.169.08:02:47.80#ibcon#about to read 5, iclass 32, count 0 2006.169.08:02:47.80#ibcon#read 5, iclass 32, count 0 2006.169.08:02:47.80#ibcon#about to read 6, iclass 32, count 0 2006.169.08:02:47.80#ibcon#read 6, iclass 32, count 0 2006.169.08:02:47.80#ibcon#end of sib2, iclass 32, count 0 2006.169.08:02:47.80#ibcon#*mode == 0, iclass 32, count 0 2006.169.08:02:47.80#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.169.08:02:47.80#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.08:02:47.80#ibcon#*before write, iclass 32, count 0 2006.169.08:02:47.80#ibcon#enter sib2, iclass 32, count 0 2006.169.08:02:47.80#ibcon#flushed, iclass 32, count 0 2006.169.08:02:47.80#ibcon#about to write, iclass 32, count 0 2006.169.08:02:47.80#ibcon#wrote, iclass 32, count 0 2006.169.08:02:47.80#ibcon#about to read 3, iclass 32, count 0 2006.169.08:02:47.84#ibcon#read 3, iclass 32, count 0 2006.169.08:02:47.84#ibcon#about to read 4, iclass 32, count 0 2006.169.08:02:47.84#ibcon#read 4, iclass 32, count 0 2006.169.08:02:47.84#ibcon#about to read 5, iclass 32, count 0 2006.169.08:02:47.84#ibcon#read 5, iclass 32, count 0 2006.169.08:02:47.84#ibcon#about to read 6, iclass 32, count 0 2006.169.08:02:47.84#ibcon#read 6, iclass 32, count 0 2006.169.08:02:47.84#ibcon#end of sib2, iclass 32, count 0 2006.169.08:02:47.84#ibcon#*after write, iclass 32, count 0 2006.169.08:02:47.84#ibcon#*before return 0, iclass 32, count 0 2006.169.08:02:47.84#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:02:47.84#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:02:47.84#ibcon#about to clear, iclass 32 cls_cnt 0 2006.169.08:02:47.84#ibcon#cleared, iclass 32 cls_cnt 0 2006.169.08:02:47.84$vc4f8/vb=2,4 2006.169.08:02:47.84#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.169.08:02:47.84#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.169.08:02:47.84#ibcon#ireg 11 cls_cnt 2 2006.169.08:02:47.84#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:02:47.91#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:02:47.91#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:02:47.91#ibcon#enter wrdev, iclass 34, count 2 2006.169.08:02:47.91#ibcon#first serial, iclass 34, count 2 2006.169.08:02:47.91#ibcon#enter sib2, iclass 34, count 2 2006.169.08:02:47.91#ibcon#flushed, iclass 34, count 2 2006.169.08:02:47.91#ibcon#about to write, iclass 34, count 2 2006.169.08:02:47.91#ibcon#wrote, iclass 34, count 2 2006.169.08:02:47.91#ibcon#about to read 3, iclass 34, count 2 2006.169.08:02:47.92#ibcon#read 3, iclass 34, count 2 2006.169.08:02:47.92#ibcon#about to read 4, iclass 34, count 2 2006.169.08:02:47.92#ibcon#read 4, iclass 34, count 2 2006.169.08:02:47.92#ibcon#about to read 5, iclass 34, count 2 2006.169.08:02:47.92#ibcon#read 5, iclass 34, count 2 2006.169.08:02:47.92#ibcon#about to read 6, iclass 34, count 2 2006.169.08:02:47.92#ibcon#read 6, iclass 34, count 2 2006.169.08:02:47.92#ibcon#end of sib2, iclass 34, count 2 2006.169.08:02:47.92#ibcon#*mode == 0, iclass 34, count 2 2006.169.08:02:47.92#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.169.08:02:47.92#ibcon#[27=AT02-04\r\n] 2006.169.08:02:47.92#ibcon#*before write, iclass 34, count 2 2006.169.08:02:47.92#ibcon#enter sib2, iclass 34, count 2 2006.169.08:02:47.92#ibcon#flushed, iclass 34, count 2 2006.169.08:02:47.92#ibcon#about to write, iclass 34, count 2 2006.169.08:02:47.92#ibcon#wrote, iclass 34, count 2 2006.169.08:02:47.92#ibcon#about to read 3, iclass 34, count 2 2006.169.08:02:47.95#ibcon#read 3, iclass 34, count 2 2006.169.08:02:47.95#ibcon#about to read 4, iclass 34, count 2 2006.169.08:02:47.95#ibcon#read 4, iclass 34, count 2 2006.169.08:02:47.95#ibcon#about to read 5, iclass 34, count 2 2006.169.08:02:47.95#ibcon#read 5, iclass 34, count 2 2006.169.08:02:47.95#ibcon#about to read 6, iclass 34, count 2 2006.169.08:02:47.95#ibcon#read 6, iclass 34, count 2 2006.169.08:02:47.95#ibcon#end of sib2, iclass 34, count 2 2006.169.08:02:47.95#ibcon#*after write, iclass 34, count 2 2006.169.08:02:47.95#ibcon#*before return 0, iclass 34, count 2 2006.169.08:02:47.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:02:47.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:02:47.95#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.169.08:02:47.95#ibcon#ireg 7 cls_cnt 0 2006.169.08:02:47.95#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:02:48.07#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:02:48.07#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:02:48.07#ibcon#enter wrdev, iclass 34, count 0 2006.169.08:02:48.07#ibcon#first serial, iclass 34, count 0 2006.169.08:02:48.07#ibcon#enter sib2, iclass 34, count 0 2006.169.08:02:48.07#ibcon#flushed, iclass 34, count 0 2006.169.08:02:48.07#ibcon#about to write, iclass 34, count 0 2006.169.08:02:48.07#ibcon#wrote, iclass 34, count 0 2006.169.08:02:48.07#ibcon#about to read 3, iclass 34, count 0 2006.169.08:02:48.09#ibcon#read 3, iclass 34, count 0 2006.169.08:02:48.09#ibcon#about to read 4, iclass 34, count 0 2006.169.08:02:48.09#ibcon#read 4, iclass 34, count 0 2006.169.08:02:48.09#ibcon#about to read 5, iclass 34, count 0 2006.169.08:02:48.09#ibcon#read 5, iclass 34, count 0 2006.169.08:02:48.09#ibcon#about to read 6, iclass 34, count 0 2006.169.08:02:48.09#ibcon#read 6, iclass 34, count 0 2006.169.08:02:48.09#ibcon#end of sib2, iclass 34, count 0 2006.169.08:02:48.09#ibcon#*mode == 0, iclass 34, count 0 2006.169.08:02:48.09#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.169.08:02:48.09#ibcon#[27=USB\r\n] 2006.169.08:02:48.09#ibcon#*before write, iclass 34, count 0 2006.169.08:02:48.09#ibcon#enter sib2, iclass 34, count 0 2006.169.08:02:48.09#ibcon#flushed, iclass 34, count 0 2006.169.08:02:48.09#ibcon#about to write, iclass 34, count 0 2006.169.08:02:48.09#ibcon#wrote, iclass 34, count 0 2006.169.08:02:48.09#ibcon#about to read 3, iclass 34, count 0 2006.169.08:02:48.12#ibcon#read 3, iclass 34, count 0 2006.169.08:02:48.12#ibcon#about to read 4, iclass 34, count 0 2006.169.08:02:48.12#ibcon#read 4, iclass 34, count 0 2006.169.08:02:48.12#ibcon#about to read 5, iclass 34, count 0 2006.169.08:02:48.12#ibcon#read 5, iclass 34, count 0 2006.169.08:02:48.12#ibcon#about to read 6, iclass 34, count 0 2006.169.08:02:48.12#ibcon#read 6, iclass 34, count 0 2006.169.08:02:48.12#ibcon#end of sib2, iclass 34, count 0 2006.169.08:02:48.12#ibcon#*after write, iclass 34, count 0 2006.169.08:02:48.12#ibcon#*before return 0, iclass 34, count 0 2006.169.08:02:48.12#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:02:48.12#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:02:48.12#ibcon#about to clear, iclass 34 cls_cnt 0 2006.169.08:02:48.12#ibcon#cleared, iclass 34 cls_cnt 0 2006.169.08:02:48.12$vc4f8/vblo=3,656.99 2006.169.08:02:48.12#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.169.08:02:48.12#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.169.08:02:48.12#ibcon#ireg 17 cls_cnt 0 2006.169.08:02:48.12#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:02:48.12#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:02:48.12#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:02:48.12#ibcon#enter wrdev, iclass 36, count 0 2006.169.08:02:48.12#ibcon#first serial, iclass 36, count 0 2006.169.08:02:48.12#ibcon#enter sib2, iclass 36, count 0 2006.169.08:02:48.12#ibcon#flushed, iclass 36, count 0 2006.169.08:02:48.12#ibcon#about to write, iclass 36, count 0 2006.169.08:02:48.12#ibcon#wrote, iclass 36, count 0 2006.169.08:02:48.12#ibcon#about to read 3, iclass 36, count 0 2006.169.08:02:48.14#ibcon#read 3, iclass 36, count 0 2006.169.08:02:48.14#ibcon#about to read 4, iclass 36, count 0 2006.169.08:02:48.14#ibcon#read 4, iclass 36, count 0 2006.169.08:02:48.14#ibcon#about to read 5, iclass 36, count 0 2006.169.08:02:48.14#ibcon#read 5, iclass 36, count 0 2006.169.08:02:48.14#ibcon#about to read 6, iclass 36, count 0 2006.169.08:02:48.14#ibcon#read 6, iclass 36, count 0 2006.169.08:02:48.14#ibcon#end of sib2, iclass 36, count 0 2006.169.08:02:48.14#ibcon#*mode == 0, iclass 36, count 0 2006.169.08:02:48.14#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.169.08:02:48.14#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.08:02:48.14#ibcon#*before write, iclass 36, count 0 2006.169.08:02:48.14#ibcon#enter sib2, iclass 36, count 0 2006.169.08:02:48.14#ibcon#flushed, iclass 36, count 0 2006.169.08:02:48.14#ibcon#about to write, iclass 36, count 0 2006.169.08:02:48.14#ibcon#wrote, iclass 36, count 0 2006.169.08:02:48.14#ibcon#about to read 3, iclass 36, count 0 2006.169.08:02:48.18#ibcon#read 3, iclass 36, count 0 2006.169.08:02:48.18#ibcon#about to read 4, iclass 36, count 0 2006.169.08:02:48.18#ibcon#read 4, iclass 36, count 0 2006.169.08:02:48.18#ibcon#about to read 5, iclass 36, count 0 2006.169.08:02:48.18#ibcon#read 5, iclass 36, count 0 2006.169.08:02:48.18#ibcon#about to read 6, iclass 36, count 0 2006.169.08:02:48.18#ibcon#read 6, iclass 36, count 0 2006.169.08:02:48.18#ibcon#end of sib2, iclass 36, count 0 2006.169.08:02:48.18#ibcon#*after write, iclass 36, count 0 2006.169.08:02:48.18#ibcon#*before return 0, iclass 36, count 0 2006.169.08:02:48.18#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:02:48.18#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:02:48.18#ibcon#about to clear, iclass 36 cls_cnt 0 2006.169.08:02:48.18#ibcon#cleared, iclass 36 cls_cnt 0 2006.169.08:02:48.18$vc4f8/vb=3,4 2006.169.08:02:48.18#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.169.08:02:48.18#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.169.08:02:48.18#ibcon#ireg 11 cls_cnt 2 2006.169.08:02:48.18#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:02:48.24#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:02:48.24#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:02:48.24#ibcon#enter wrdev, iclass 38, count 2 2006.169.08:02:48.24#ibcon#first serial, iclass 38, count 2 2006.169.08:02:48.24#ibcon#enter sib2, iclass 38, count 2 2006.169.08:02:48.24#ibcon#flushed, iclass 38, count 2 2006.169.08:02:48.24#ibcon#about to write, iclass 38, count 2 2006.169.08:02:48.24#ibcon#wrote, iclass 38, count 2 2006.169.08:02:48.24#ibcon#about to read 3, iclass 38, count 2 2006.169.08:02:48.26#ibcon#read 3, iclass 38, count 2 2006.169.08:02:48.26#ibcon#about to read 4, iclass 38, count 2 2006.169.08:02:48.26#ibcon#read 4, iclass 38, count 2 2006.169.08:02:48.26#ibcon#about to read 5, iclass 38, count 2 2006.169.08:02:48.26#ibcon#read 5, iclass 38, count 2 2006.169.08:02:48.26#ibcon#about to read 6, iclass 38, count 2 2006.169.08:02:48.26#ibcon#read 6, iclass 38, count 2 2006.169.08:02:48.26#ibcon#end of sib2, iclass 38, count 2 2006.169.08:02:48.26#ibcon#*mode == 0, iclass 38, count 2 2006.169.08:02:48.26#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.169.08:02:48.26#ibcon#[27=AT03-04\r\n] 2006.169.08:02:48.26#ibcon#*before write, iclass 38, count 2 2006.169.08:02:48.26#ibcon#enter sib2, iclass 38, count 2 2006.169.08:02:48.26#ibcon#flushed, iclass 38, count 2 2006.169.08:02:48.26#ibcon#about to write, iclass 38, count 2 2006.169.08:02:48.26#ibcon#wrote, iclass 38, count 2 2006.169.08:02:48.26#ibcon#about to read 3, iclass 38, count 2 2006.169.08:02:48.29#ibcon#read 3, iclass 38, count 2 2006.169.08:02:48.29#ibcon#about to read 4, iclass 38, count 2 2006.169.08:02:48.29#ibcon#read 4, iclass 38, count 2 2006.169.08:02:48.29#ibcon#about to read 5, iclass 38, count 2 2006.169.08:02:48.29#ibcon#read 5, iclass 38, count 2 2006.169.08:02:48.29#ibcon#about to read 6, iclass 38, count 2 2006.169.08:02:48.29#ibcon#read 6, iclass 38, count 2 2006.169.08:02:48.29#ibcon#end of sib2, iclass 38, count 2 2006.169.08:02:48.29#ibcon#*after write, iclass 38, count 2 2006.169.08:02:48.29#ibcon#*before return 0, iclass 38, count 2 2006.169.08:02:48.29#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:02:48.29#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:02:48.29#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.169.08:02:48.29#ibcon#ireg 7 cls_cnt 0 2006.169.08:02:48.29#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:02:48.41#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:02:48.41#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:02:48.41#ibcon#enter wrdev, iclass 38, count 0 2006.169.08:02:48.41#ibcon#first serial, iclass 38, count 0 2006.169.08:02:48.41#ibcon#enter sib2, iclass 38, count 0 2006.169.08:02:48.41#ibcon#flushed, iclass 38, count 0 2006.169.08:02:48.41#ibcon#about to write, iclass 38, count 0 2006.169.08:02:48.41#ibcon#wrote, iclass 38, count 0 2006.169.08:02:48.41#ibcon#about to read 3, iclass 38, count 0 2006.169.08:02:48.43#ibcon#read 3, iclass 38, count 0 2006.169.08:02:48.43#ibcon#about to read 4, iclass 38, count 0 2006.169.08:02:48.43#ibcon#read 4, iclass 38, count 0 2006.169.08:02:48.43#ibcon#about to read 5, iclass 38, count 0 2006.169.08:02:48.43#ibcon#read 5, iclass 38, count 0 2006.169.08:02:48.43#ibcon#about to read 6, iclass 38, count 0 2006.169.08:02:48.43#ibcon#read 6, iclass 38, count 0 2006.169.08:02:48.43#ibcon#end of sib2, iclass 38, count 0 2006.169.08:02:48.43#ibcon#*mode == 0, iclass 38, count 0 2006.169.08:02:48.43#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.169.08:02:48.43#ibcon#[27=USB\r\n] 2006.169.08:02:48.43#ibcon#*before write, iclass 38, count 0 2006.169.08:02:48.43#ibcon#enter sib2, iclass 38, count 0 2006.169.08:02:48.43#ibcon#flushed, iclass 38, count 0 2006.169.08:02:48.43#ibcon#about to write, iclass 38, count 0 2006.169.08:02:48.43#ibcon#wrote, iclass 38, count 0 2006.169.08:02:48.43#ibcon#about to read 3, iclass 38, count 0 2006.169.08:02:48.46#ibcon#read 3, iclass 38, count 0 2006.169.08:02:48.46#ibcon#about to read 4, iclass 38, count 0 2006.169.08:02:48.46#ibcon#read 4, iclass 38, count 0 2006.169.08:02:48.46#ibcon#about to read 5, iclass 38, count 0 2006.169.08:02:48.46#ibcon#read 5, iclass 38, count 0 2006.169.08:02:48.46#ibcon#about to read 6, iclass 38, count 0 2006.169.08:02:48.46#ibcon#read 6, iclass 38, count 0 2006.169.08:02:48.46#ibcon#end of sib2, iclass 38, count 0 2006.169.08:02:48.46#ibcon#*after write, iclass 38, count 0 2006.169.08:02:48.46#ibcon#*before return 0, iclass 38, count 0 2006.169.08:02:48.46#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:02:48.46#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:02:48.46#ibcon#about to clear, iclass 38 cls_cnt 0 2006.169.08:02:48.46#ibcon#cleared, iclass 38 cls_cnt 0 2006.169.08:02:48.46$vc4f8/vblo=4,712.99 2006.169.08:02:48.46#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.169.08:02:48.46#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.169.08:02:48.46#ibcon#ireg 17 cls_cnt 0 2006.169.08:02:48.46#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:02:48.46#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:02:48.46#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:02:48.46#ibcon#enter wrdev, iclass 40, count 0 2006.169.08:02:48.46#ibcon#first serial, iclass 40, count 0 2006.169.08:02:48.46#ibcon#enter sib2, iclass 40, count 0 2006.169.08:02:48.46#ibcon#flushed, iclass 40, count 0 2006.169.08:02:48.46#ibcon#about to write, iclass 40, count 0 2006.169.08:02:48.46#ibcon#wrote, iclass 40, count 0 2006.169.08:02:48.46#ibcon#about to read 3, iclass 40, count 0 2006.169.08:02:48.48#ibcon#read 3, iclass 40, count 0 2006.169.08:02:48.48#ibcon#about to read 4, iclass 40, count 0 2006.169.08:02:48.48#ibcon#read 4, iclass 40, count 0 2006.169.08:02:48.48#ibcon#about to read 5, iclass 40, count 0 2006.169.08:02:48.48#ibcon#read 5, iclass 40, count 0 2006.169.08:02:48.48#ibcon#about to read 6, iclass 40, count 0 2006.169.08:02:48.48#ibcon#read 6, iclass 40, count 0 2006.169.08:02:48.48#ibcon#end of sib2, iclass 40, count 0 2006.169.08:02:48.48#ibcon#*mode == 0, iclass 40, count 0 2006.169.08:02:48.48#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.169.08:02:48.48#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.08:02:48.48#ibcon#*before write, iclass 40, count 0 2006.169.08:02:48.48#ibcon#enter sib2, iclass 40, count 0 2006.169.08:02:48.48#ibcon#flushed, iclass 40, count 0 2006.169.08:02:48.48#ibcon#about to write, iclass 40, count 0 2006.169.08:02:48.48#ibcon#wrote, iclass 40, count 0 2006.169.08:02:48.48#ibcon#about to read 3, iclass 40, count 0 2006.169.08:02:48.52#ibcon#read 3, iclass 40, count 0 2006.169.08:02:48.52#ibcon#about to read 4, iclass 40, count 0 2006.169.08:02:48.52#ibcon#read 4, iclass 40, count 0 2006.169.08:02:48.52#ibcon#about to read 5, iclass 40, count 0 2006.169.08:02:48.52#ibcon#read 5, iclass 40, count 0 2006.169.08:02:48.52#ibcon#about to read 6, iclass 40, count 0 2006.169.08:02:48.52#ibcon#read 6, iclass 40, count 0 2006.169.08:02:48.52#ibcon#end of sib2, iclass 40, count 0 2006.169.08:02:48.52#ibcon#*after write, iclass 40, count 0 2006.169.08:02:48.52#ibcon#*before return 0, iclass 40, count 0 2006.169.08:02:48.52#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:02:48.52#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:02:48.52#ibcon#about to clear, iclass 40 cls_cnt 0 2006.169.08:02:48.52#ibcon#cleared, iclass 40 cls_cnt 0 2006.169.08:02:48.52$vc4f8/vb=4,4 2006.169.08:02:48.52#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.169.08:02:48.52#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.169.08:02:48.52#ibcon#ireg 11 cls_cnt 2 2006.169.08:02:48.52#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:02:48.58#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:02:48.58#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:02:48.58#ibcon#enter wrdev, iclass 4, count 2 2006.169.08:02:48.58#ibcon#first serial, iclass 4, count 2 2006.169.08:02:48.58#ibcon#enter sib2, iclass 4, count 2 2006.169.08:02:48.58#ibcon#flushed, iclass 4, count 2 2006.169.08:02:48.58#ibcon#about to write, iclass 4, count 2 2006.169.08:02:48.58#ibcon#wrote, iclass 4, count 2 2006.169.08:02:48.58#ibcon#about to read 3, iclass 4, count 2 2006.169.08:02:48.60#ibcon#read 3, iclass 4, count 2 2006.169.08:02:48.60#ibcon#about to read 4, iclass 4, count 2 2006.169.08:02:48.60#ibcon#read 4, iclass 4, count 2 2006.169.08:02:48.60#ibcon#about to read 5, iclass 4, count 2 2006.169.08:02:48.60#ibcon#read 5, iclass 4, count 2 2006.169.08:02:48.60#ibcon#about to read 6, iclass 4, count 2 2006.169.08:02:48.60#ibcon#read 6, iclass 4, count 2 2006.169.08:02:48.60#ibcon#end of sib2, iclass 4, count 2 2006.169.08:02:48.60#ibcon#*mode == 0, iclass 4, count 2 2006.169.08:02:48.60#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.169.08:02:48.60#ibcon#[27=AT04-04\r\n] 2006.169.08:02:48.60#ibcon#*before write, iclass 4, count 2 2006.169.08:02:48.60#ibcon#enter sib2, iclass 4, count 2 2006.169.08:02:48.60#ibcon#flushed, iclass 4, count 2 2006.169.08:02:48.60#ibcon#about to write, iclass 4, count 2 2006.169.08:02:48.60#ibcon#wrote, iclass 4, count 2 2006.169.08:02:48.60#ibcon#about to read 3, iclass 4, count 2 2006.169.08:02:48.63#ibcon#read 3, iclass 4, count 2 2006.169.08:02:48.63#ibcon#about to read 4, iclass 4, count 2 2006.169.08:02:48.63#ibcon#read 4, iclass 4, count 2 2006.169.08:02:48.63#ibcon#about to read 5, iclass 4, count 2 2006.169.08:02:48.63#ibcon#read 5, iclass 4, count 2 2006.169.08:02:48.63#ibcon#about to read 6, iclass 4, count 2 2006.169.08:02:48.63#ibcon#read 6, iclass 4, count 2 2006.169.08:02:48.63#ibcon#end of sib2, iclass 4, count 2 2006.169.08:02:48.63#ibcon#*after write, iclass 4, count 2 2006.169.08:02:48.63#ibcon#*before return 0, iclass 4, count 2 2006.169.08:02:48.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:02:48.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:02:48.63#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.169.08:02:48.63#ibcon#ireg 7 cls_cnt 0 2006.169.08:02:48.63#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:02:48.75#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:02:48.75#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:02:48.75#ibcon#enter wrdev, iclass 4, count 0 2006.169.08:02:48.75#ibcon#first serial, iclass 4, count 0 2006.169.08:02:48.75#ibcon#enter sib2, iclass 4, count 0 2006.169.08:02:48.75#ibcon#flushed, iclass 4, count 0 2006.169.08:02:48.75#ibcon#about to write, iclass 4, count 0 2006.169.08:02:48.75#ibcon#wrote, iclass 4, count 0 2006.169.08:02:48.75#ibcon#about to read 3, iclass 4, count 0 2006.169.08:02:48.77#ibcon#read 3, iclass 4, count 0 2006.169.08:02:48.77#ibcon#about to read 4, iclass 4, count 0 2006.169.08:02:48.77#ibcon#read 4, iclass 4, count 0 2006.169.08:02:48.77#ibcon#about to read 5, iclass 4, count 0 2006.169.08:02:48.77#ibcon#read 5, iclass 4, count 0 2006.169.08:02:48.77#ibcon#about to read 6, iclass 4, count 0 2006.169.08:02:48.77#ibcon#read 6, iclass 4, count 0 2006.169.08:02:48.77#ibcon#end of sib2, iclass 4, count 0 2006.169.08:02:48.77#ibcon#*mode == 0, iclass 4, count 0 2006.169.08:02:48.77#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.169.08:02:48.77#ibcon#[27=USB\r\n] 2006.169.08:02:48.77#ibcon#*before write, iclass 4, count 0 2006.169.08:02:48.77#ibcon#enter sib2, iclass 4, count 0 2006.169.08:02:48.77#ibcon#flushed, iclass 4, count 0 2006.169.08:02:48.77#ibcon#about to write, iclass 4, count 0 2006.169.08:02:48.77#ibcon#wrote, iclass 4, count 0 2006.169.08:02:48.77#ibcon#about to read 3, iclass 4, count 0 2006.169.08:02:48.80#ibcon#read 3, iclass 4, count 0 2006.169.08:02:48.80#ibcon#about to read 4, iclass 4, count 0 2006.169.08:02:48.80#ibcon#read 4, iclass 4, count 0 2006.169.08:02:48.80#ibcon#about to read 5, iclass 4, count 0 2006.169.08:02:48.80#ibcon#read 5, iclass 4, count 0 2006.169.08:02:48.80#ibcon#about to read 6, iclass 4, count 0 2006.169.08:02:48.80#ibcon#read 6, iclass 4, count 0 2006.169.08:02:48.80#ibcon#end of sib2, iclass 4, count 0 2006.169.08:02:48.80#ibcon#*after write, iclass 4, count 0 2006.169.08:02:48.80#ibcon#*before return 0, iclass 4, count 0 2006.169.08:02:48.80#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:02:48.80#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:02:48.80#ibcon#about to clear, iclass 4 cls_cnt 0 2006.169.08:02:48.80#ibcon#cleared, iclass 4 cls_cnt 0 2006.169.08:02:48.80$vc4f8/vblo=5,744.99 2006.169.08:02:48.80#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.169.08:02:48.80#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.169.08:02:48.80#ibcon#ireg 17 cls_cnt 0 2006.169.08:02:48.80#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:02:48.80#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:02:48.80#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:02:48.80#ibcon#enter wrdev, iclass 6, count 0 2006.169.08:02:48.80#ibcon#first serial, iclass 6, count 0 2006.169.08:02:48.80#ibcon#enter sib2, iclass 6, count 0 2006.169.08:02:48.80#ibcon#flushed, iclass 6, count 0 2006.169.08:02:48.80#ibcon#about to write, iclass 6, count 0 2006.169.08:02:48.80#ibcon#wrote, iclass 6, count 0 2006.169.08:02:48.80#ibcon#about to read 3, iclass 6, count 0 2006.169.08:02:48.82#ibcon#read 3, iclass 6, count 0 2006.169.08:02:48.82#ibcon#about to read 4, iclass 6, count 0 2006.169.08:02:48.82#ibcon#read 4, iclass 6, count 0 2006.169.08:02:48.82#ibcon#about to read 5, iclass 6, count 0 2006.169.08:02:48.82#ibcon#read 5, iclass 6, count 0 2006.169.08:02:48.82#ibcon#about to read 6, iclass 6, count 0 2006.169.08:02:48.82#ibcon#read 6, iclass 6, count 0 2006.169.08:02:48.82#ibcon#end of sib2, iclass 6, count 0 2006.169.08:02:48.82#ibcon#*mode == 0, iclass 6, count 0 2006.169.08:02:48.82#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.169.08:02:48.82#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.08:02:48.82#ibcon#*before write, iclass 6, count 0 2006.169.08:02:48.82#ibcon#enter sib2, iclass 6, count 0 2006.169.08:02:48.82#ibcon#flushed, iclass 6, count 0 2006.169.08:02:48.82#ibcon#about to write, iclass 6, count 0 2006.169.08:02:48.82#ibcon#wrote, iclass 6, count 0 2006.169.08:02:48.82#ibcon#about to read 3, iclass 6, count 0 2006.169.08:02:48.86#ibcon#read 3, iclass 6, count 0 2006.169.08:02:48.86#ibcon#about to read 4, iclass 6, count 0 2006.169.08:02:48.86#ibcon#read 4, iclass 6, count 0 2006.169.08:02:48.86#ibcon#about to read 5, iclass 6, count 0 2006.169.08:02:48.86#ibcon#read 5, iclass 6, count 0 2006.169.08:02:48.86#ibcon#about to read 6, iclass 6, count 0 2006.169.08:02:48.86#ibcon#read 6, iclass 6, count 0 2006.169.08:02:48.86#ibcon#end of sib2, iclass 6, count 0 2006.169.08:02:48.86#ibcon#*after write, iclass 6, count 0 2006.169.08:02:48.86#ibcon#*before return 0, iclass 6, count 0 2006.169.08:02:48.86#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:02:48.86#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:02:48.86#ibcon#about to clear, iclass 6 cls_cnt 0 2006.169.08:02:48.86#ibcon#cleared, iclass 6 cls_cnt 0 2006.169.08:02:48.86$vc4f8/vb=5,4 2006.169.08:02:48.86#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.169.08:02:48.86#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.169.08:02:48.86#ibcon#ireg 11 cls_cnt 2 2006.169.08:02:48.86#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:02:48.92#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:02:48.92#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:02:48.92#ibcon#enter wrdev, iclass 10, count 2 2006.169.08:02:48.92#ibcon#first serial, iclass 10, count 2 2006.169.08:02:48.92#ibcon#enter sib2, iclass 10, count 2 2006.169.08:02:48.92#ibcon#flushed, iclass 10, count 2 2006.169.08:02:48.92#ibcon#about to write, iclass 10, count 2 2006.169.08:02:48.92#ibcon#wrote, iclass 10, count 2 2006.169.08:02:48.92#ibcon#about to read 3, iclass 10, count 2 2006.169.08:02:48.94#ibcon#read 3, iclass 10, count 2 2006.169.08:02:48.94#ibcon#about to read 4, iclass 10, count 2 2006.169.08:02:48.94#ibcon#read 4, iclass 10, count 2 2006.169.08:02:48.94#ibcon#about to read 5, iclass 10, count 2 2006.169.08:02:48.94#ibcon#read 5, iclass 10, count 2 2006.169.08:02:48.94#ibcon#about to read 6, iclass 10, count 2 2006.169.08:02:48.94#ibcon#read 6, iclass 10, count 2 2006.169.08:02:48.94#ibcon#end of sib2, iclass 10, count 2 2006.169.08:02:48.94#ibcon#*mode == 0, iclass 10, count 2 2006.169.08:02:48.94#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.169.08:02:48.94#ibcon#[27=AT05-04\r\n] 2006.169.08:02:48.94#ibcon#*before write, iclass 10, count 2 2006.169.08:02:48.94#ibcon#enter sib2, iclass 10, count 2 2006.169.08:02:48.94#ibcon#flushed, iclass 10, count 2 2006.169.08:02:48.94#ibcon#about to write, iclass 10, count 2 2006.169.08:02:48.94#ibcon#wrote, iclass 10, count 2 2006.169.08:02:48.94#ibcon#about to read 3, iclass 10, count 2 2006.169.08:02:48.97#ibcon#read 3, iclass 10, count 2 2006.169.08:02:48.97#ibcon#about to read 4, iclass 10, count 2 2006.169.08:02:48.97#ibcon#read 4, iclass 10, count 2 2006.169.08:02:48.97#ibcon#about to read 5, iclass 10, count 2 2006.169.08:02:48.97#ibcon#read 5, iclass 10, count 2 2006.169.08:02:48.97#ibcon#about to read 6, iclass 10, count 2 2006.169.08:02:48.97#ibcon#read 6, iclass 10, count 2 2006.169.08:02:48.97#ibcon#end of sib2, iclass 10, count 2 2006.169.08:02:48.97#ibcon#*after write, iclass 10, count 2 2006.169.08:02:48.97#ibcon#*before return 0, iclass 10, count 2 2006.169.08:02:48.97#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:02:48.97#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:02:48.97#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.169.08:02:48.97#ibcon#ireg 7 cls_cnt 0 2006.169.08:02:48.97#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:02:49.09#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:02:49.09#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:02:49.09#ibcon#enter wrdev, iclass 10, count 0 2006.169.08:02:49.09#ibcon#first serial, iclass 10, count 0 2006.169.08:02:49.09#ibcon#enter sib2, iclass 10, count 0 2006.169.08:02:49.09#ibcon#flushed, iclass 10, count 0 2006.169.08:02:49.09#ibcon#about to write, iclass 10, count 0 2006.169.08:02:49.09#ibcon#wrote, iclass 10, count 0 2006.169.08:02:49.09#ibcon#about to read 3, iclass 10, count 0 2006.169.08:02:49.11#ibcon#read 3, iclass 10, count 0 2006.169.08:02:49.11#ibcon#about to read 4, iclass 10, count 0 2006.169.08:02:49.11#ibcon#read 4, iclass 10, count 0 2006.169.08:02:49.11#ibcon#about to read 5, iclass 10, count 0 2006.169.08:02:49.11#ibcon#read 5, iclass 10, count 0 2006.169.08:02:49.11#ibcon#about to read 6, iclass 10, count 0 2006.169.08:02:49.11#ibcon#read 6, iclass 10, count 0 2006.169.08:02:49.11#ibcon#end of sib2, iclass 10, count 0 2006.169.08:02:49.11#ibcon#*mode == 0, iclass 10, count 0 2006.169.08:02:49.11#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.169.08:02:49.11#ibcon#[27=USB\r\n] 2006.169.08:02:49.11#ibcon#*before write, iclass 10, count 0 2006.169.08:02:49.11#ibcon#enter sib2, iclass 10, count 0 2006.169.08:02:49.11#ibcon#flushed, iclass 10, count 0 2006.169.08:02:49.11#ibcon#about to write, iclass 10, count 0 2006.169.08:02:49.11#ibcon#wrote, iclass 10, count 0 2006.169.08:02:49.11#ibcon#about to read 3, iclass 10, count 0 2006.169.08:02:49.14#ibcon#read 3, iclass 10, count 0 2006.169.08:02:49.14#ibcon#about to read 4, iclass 10, count 0 2006.169.08:02:49.14#ibcon#read 4, iclass 10, count 0 2006.169.08:02:49.14#ibcon#about to read 5, iclass 10, count 0 2006.169.08:02:49.14#ibcon#read 5, iclass 10, count 0 2006.169.08:02:49.14#ibcon#about to read 6, iclass 10, count 0 2006.169.08:02:49.14#ibcon#read 6, iclass 10, count 0 2006.169.08:02:49.14#ibcon#end of sib2, iclass 10, count 0 2006.169.08:02:49.14#ibcon#*after write, iclass 10, count 0 2006.169.08:02:49.14#ibcon#*before return 0, iclass 10, count 0 2006.169.08:02:49.14#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:02:49.14#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:02:49.14#ibcon#about to clear, iclass 10 cls_cnt 0 2006.169.08:02:49.14#ibcon#cleared, iclass 10 cls_cnt 0 2006.169.08:02:49.14$vc4f8/vblo=6,752.99 2006.169.08:02:49.14#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.169.08:02:49.14#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.169.08:02:49.14#ibcon#ireg 17 cls_cnt 0 2006.169.08:02:49.14#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:02:49.14#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:02:49.14#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:02:49.14#ibcon#enter wrdev, iclass 12, count 0 2006.169.08:02:49.14#ibcon#first serial, iclass 12, count 0 2006.169.08:02:49.14#ibcon#enter sib2, iclass 12, count 0 2006.169.08:02:49.14#ibcon#flushed, iclass 12, count 0 2006.169.08:02:49.14#ibcon#about to write, iclass 12, count 0 2006.169.08:02:49.14#ibcon#wrote, iclass 12, count 0 2006.169.08:02:49.14#ibcon#about to read 3, iclass 12, count 0 2006.169.08:02:49.16#ibcon#read 3, iclass 12, count 0 2006.169.08:02:49.16#ibcon#about to read 4, iclass 12, count 0 2006.169.08:02:49.16#ibcon#read 4, iclass 12, count 0 2006.169.08:02:49.16#ibcon#about to read 5, iclass 12, count 0 2006.169.08:02:49.16#ibcon#read 5, iclass 12, count 0 2006.169.08:02:49.16#ibcon#about to read 6, iclass 12, count 0 2006.169.08:02:49.16#ibcon#read 6, iclass 12, count 0 2006.169.08:02:49.16#ibcon#end of sib2, iclass 12, count 0 2006.169.08:02:49.16#ibcon#*mode == 0, iclass 12, count 0 2006.169.08:02:49.16#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.169.08:02:49.16#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.08:02:49.16#ibcon#*before write, iclass 12, count 0 2006.169.08:02:49.16#ibcon#enter sib2, iclass 12, count 0 2006.169.08:02:49.16#ibcon#flushed, iclass 12, count 0 2006.169.08:02:49.16#ibcon#about to write, iclass 12, count 0 2006.169.08:02:49.16#ibcon#wrote, iclass 12, count 0 2006.169.08:02:49.16#ibcon#about to read 3, iclass 12, count 0 2006.169.08:02:49.20#ibcon#read 3, iclass 12, count 0 2006.169.08:02:49.20#ibcon#about to read 4, iclass 12, count 0 2006.169.08:02:49.20#ibcon#read 4, iclass 12, count 0 2006.169.08:02:49.20#ibcon#about to read 5, iclass 12, count 0 2006.169.08:02:49.20#ibcon#read 5, iclass 12, count 0 2006.169.08:02:49.20#ibcon#about to read 6, iclass 12, count 0 2006.169.08:02:49.20#ibcon#read 6, iclass 12, count 0 2006.169.08:02:49.20#ibcon#end of sib2, iclass 12, count 0 2006.169.08:02:49.20#ibcon#*after write, iclass 12, count 0 2006.169.08:02:49.20#ibcon#*before return 0, iclass 12, count 0 2006.169.08:02:49.20#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:02:49.20#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:02:49.20#ibcon#about to clear, iclass 12 cls_cnt 0 2006.169.08:02:49.20#ibcon#cleared, iclass 12 cls_cnt 0 2006.169.08:02:49.20$vc4f8/vb=6,4 2006.169.08:02:49.20#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.169.08:02:49.20#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.169.08:02:49.20#ibcon#ireg 11 cls_cnt 2 2006.169.08:02:49.20#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.169.08:02:49.26#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.169.08:02:49.26#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.169.08:02:49.26#ibcon#enter wrdev, iclass 14, count 2 2006.169.08:02:49.26#ibcon#first serial, iclass 14, count 2 2006.169.08:02:49.26#ibcon#enter sib2, iclass 14, count 2 2006.169.08:02:49.26#ibcon#flushed, iclass 14, count 2 2006.169.08:02:49.26#ibcon#about to write, iclass 14, count 2 2006.169.08:02:49.26#ibcon#wrote, iclass 14, count 2 2006.169.08:02:49.26#ibcon#about to read 3, iclass 14, count 2 2006.169.08:02:49.28#ibcon#read 3, iclass 14, count 2 2006.169.08:02:49.28#ibcon#about to read 4, iclass 14, count 2 2006.169.08:02:49.28#ibcon#read 4, iclass 14, count 2 2006.169.08:02:49.28#ibcon#about to read 5, iclass 14, count 2 2006.169.08:02:49.28#ibcon#read 5, iclass 14, count 2 2006.169.08:02:49.28#ibcon#about to read 6, iclass 14, count 2 2006.169.08:02:49.28#ibcon#read 6, iclass 14, count 2 2006.169.08:02:49.28#ibcon#end of sib2, iclass 14, count 2 2006.169.08:02:49.28#ibcon#*mode == 0, iclass 14, count 2 2006.169.08:02:49.28#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.169.08:02:49.28#ibcon#[27=AT06-04\r\n] 2006.169.08:02:49.28#ibcon#*before write, iclass 14, count 2 2006.169.08:02:49.28#ibcon#enter sib2, iclass 14, count 2 2006.169.08:02:49.28#ibcon#flushed, iclass 14, count 2 2006.169.08:02:49.28#ibcon#about to write, iclass 14, count 2 2006.169.08:02:49.28#ibcon#wrote, iclass 14, count 2 2006.169.08:02:49.28#ibcon#about to read 3, iclass 14, count 2 2006.169.08:02:49.31#ibcon#read 3, iclass 14, count 2 2006.169.08:02:49.31#ibcon#about to read 4, iclass 14, count 2 2006.169.08:02:49.31#ibcon#read 4, iclass 14, count 2 2006.169.08:02:49.31#ibcon#about to read 5, iclass 14, count 2 2006.169.08:02:49.31#ibcon#read 5, iclass 14, count 2 2006.169.08:02:49.31#ibcon#about to read 6, iclass 14, count 2 2006.169.08:02:49.31#ibcon#read 6, iclass 14, count 2 2006.169.08:02:49.31#ibcon#end of sib2, iclass 14, count 2 2006.169.08:02:49.31#ibcon#*after write, iclass 14, count 2 2006.169.08:02:49.31#ibcon#*before return 0, iclass 14, count 2 2006.169.08:02:49.31#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.169.08:02:49.31#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.169.08:02:49.31#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.169.08:02:49.31#ibcon#ireg 7 cls_cnt 0 2006.169.08:02:49.31#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.169.08:02:49.43#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.169.08:02:49.43#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.169.08:02:49.43#ibcon#enter wrdev, iclass 14, count 0 2006.169.08:02:49.43#ibcon#first serial, iclass 14, count 0 2006.169.08:02:49.43#ibcon#enter sib2, iclass 14, count 0 2006.169.08:02:49.43#ibcon#flushed, iclass 14, count 0 2006.169.08:02:49.43#ibcon#about to write, iclass 14, count 0 2006.169.08:02:49.43#ibcon#wrote, iclass 14, count 0 2006.169.08:02:49.43#ibcon#about to read 3, iclass 14, count 0 2006.169.08:02:49.45#ibcon#read 3, iclass 14, count 0 2006.169.08:02:49.45#ibcon#about to read 4, iclass 14, count 0 2006.169.08:02:49.45#ibcon#read 4, iclass 14, count 0 2006.169.08:02:49.45#ibcon#about to read 5, iclass 14, count 0 2006.169.08:02:49.45#ibcon#read 5, iclass 14, count 0 2006.169.08:02:49.45#ibcon#about to read 6, iclass 14, count 0 2006.169.08:02:49.45#ibcon#read 6, iclass 14, count 0 2006.169.08:02:49.45#ibcon#end of sib2, iclass 14, count 0 2006.169.08:02:49.45#ibcon#*mode == 0, iclass 14, count 0 2006.169.08:02:49.45#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.169.08:02:49.45#ibcon#[27=USB\r\n] 2006.169.08:02:49.45#ibcon#*before write, iclass 14, count 0 2006.169.08:02:49.45#ibcon#enter sib2, iclass 14, count 0 2006.169.08:02:49.45#ibcon#flushed, iclass 14, count 0 2006.169.08:02:49.45#ibcon#about to write, iclass 14, count 0 2006.169.08:02:49.45#ibcon#wrote, iclass 14, count 0 2006.169.08:02:49.45#ibcon#about to read 3, iclass 14, count 0 2006.169.08:02:49.48#ibcon#read 3, iclass 14, count 0 2006.169.08:02:49.48#ibcon#about to read 4, iclass 14, count 0 2006.169.08:02:49.48#ibcon#read 4, iclass 14, count 0 2006.169.08:02:49.48#ibcon#about to read 5, iclass 14, count 0 2006.169.08:02:49.48#ibcon#read 5, iclass 14, count 0 2006.169.08:02:49.48#ibcon#about to read 6, iclass 14, count 0 2006.169.08:02:49.48#ibcon#read 6, iclass 14, count 0 2006.169.08:02:49.48#ibcon#end of sib2, iclass 14, count 0 2006.169.08:02:49.48#ibcon#*after write, iclass 14, count 0 2006.169.08:02:49.48#ibcon#*before return 0, iclass 14, count 0 2006.169.08:02:49.48#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.169.08:02:49.48#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.169.08:02:49.48#ibcon#about to clear, iclass 14 cls_cnt 0 2006.169.08:02:49.48#ibcon#cleared, iclass 14 cls_cnt 0 2006.169.08:02:49.48$vc4f8/vabw=wide 2006.169.08:02:49.48#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.169.08:02:49.48#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.169.08:02:49.48#ibcon#ireg 8 cls_cnt 0 2006.169.08:02:49.48#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:02:49.48#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:02:49.48#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:02:49.48#ibcon#enter wrdev, iclass 16, count 0 2006.169.08:02:49.48#ibcon#first serial, iclass 16, count 0 2006.169.08:02:49.48#ibcon#enter sib2, iclass 16, count 0 2006.169.08:02:49.48#ibcon#flushed, iclass 16, count 0 2006.169.08:02:49.48#ibcon#about to write, iclass 16, count 0 2006.169.08:02:49.48#ibcon#wrote, iclass 16, count 0 2006.169.08:02:49.48#ibcon#about to read 3, iclass 16, count 0 2006.169.08:02:49.50#ibcon#read 3, iclass 16, count 0 2006.169.08:02:49.50#ibcon#about to read 4, iclass 16, count 0 2006.169.08:02:49.50#ibcon#read 4, iclass 16, count 0 2006.169.08:02:49.50#ibcon#about to read 5, iclass 16, count 0 2006.169.08:02:49.50#ibcon#read 5, iclass 16, count 0 2006.169.08:02:49.50#ibcon#about to read 6, iclass 16, count 0 2006.169.08:02:49.50#ibcon#read 6, iclass 16, count 0 2006.169.08:02:49.50#ibcon#end of sib2, iclass 16, count 0 2006.169.08:02:49.50#ibcon#*mode == 0, iclass 16, count 0 2006.169.08:02:49.50#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.169.08:02:49.50#ibcon#[25=BW32\r\n] 2006.169.08:02:49.50#ibcon#*before write, iclass 16, count 0 2006.169.08:02:49.50#ibcon#enter sib2, iclass 16, count 0 2006.169.08:02:49.50#ibcon#flushed, iclass 16, count 0 2006.169.08:02:49.50#ibcon#about to write, iclass 16, count 0 2006.169.08:02:49.50#ibcon#wrote, iclass 16, count 0 2006.169.08:02:49.50#ibcon#about to read 3, iclass 16, count 0 2006.169.08:02:49.53#ibcon#read 3, iclass 16, count 0 2006.169.08:02:49.53#ibcon#about to read 4, iclass 16, count 0 2006.169.08:02:49.53#ibcon#read 4, iclass 16, count 0 2006.169.08:02:49.53#ibcon#about to read 5, iclass 16, count 0 2006.169.08:02:49.53#ibcon#read 5, iclass 16, count 0 2006.169.08:02:49.53#ibcon#about to read 6, iclass 16, count 0 2006.169.08:02:49.53#ibcon#read 6, iclass 16, count 0 2006.169.08:02:49.53#ibcon#end of sib2, iclass 16, count 0 2006.169.08:02:49.53#ibcon#*after write, iclass 16, count 0 2006.169.08:02:49.53#ibcon#*before return 0, iclass 16, count 0 2006.169.08:02:49.53#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:02:49.53#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:02:49.53#ibcon#about to clear, iclass 16 cls_cnt 0 2006.169.08:02:49.53#ibcon#cleared, iclass 16 cls_cnt 0 2006.169.08:02:49.53$vc4f8/vbbw=wide 2006.169.08:02:49.53#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.169.08:02:49.53#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.169.08:02:49.53#ibcon#ireg 8 cls_cnt 0 2006.169.08:02:49.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:02:49.60#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:02:49.60#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:02:49.60#ibcon#enter wrdev, iclass 18, count 0 2006.169.08:02:49.60#ibcon#first serial, iclass 18, count 0 2006.169.08:02:49.60#ibcon#enter sib2, iclass 18, count 0 2006.169.08:02:49.60#ibcon#flushed, iclass 18, count 0 2006.169.08:02:49.60#ibcon#about to write, iclass 18, count 0 2006.169.08:02:49.60#ibcon#wrote, iclass 18, count 0 2006.169.08:02:49.60#ibcon#about to read 3, iclass 18, count 0 2006.169.08:02:49.62#ibcon#read 3, iclass 18, count 0 2006.169.08:02:49.62#ibcon#about to read 4, iclass 18, count 0 2006.169.08:02:49.62#ibcon#read 4, iclass 18, count 0 2006.169.08:02:49.62#ibcon#about to read 5, iclass 18, count 0 2006.169.08:02:49.62#ibcon#read 5, iclass 18, count 0 2006.169.08:02:49.62#ibcon#about to read 6, iclass 18, count 0 2006.169.08:02:49.62#ibcon#read 6, iclass 18, count 0 2006.169.08:02:49.62#ibcon#end of sib2, iclass 18, count 0 2006.169.08:02:49.62#ibcon#*mode == 0, iclass 18, count 0 2006.169.08:02:49.62#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.169.08:02:49.62#ibcon#[27=BW32\r\n] 2006.169.08:02:49.62#ibcon#*before write, iclass 18, count 0 2006.169.08:02:49.62#ibcon#enter sib2, iclass 18, count 0 2006.169.08:02:49.62#ibcon#flushed, iclass 18, count 0 2006.169.08:02:49.62#ibcon#about to write, iclass 18, count 0 2006.169.08:02:49.62#ibcon#wrote, iclass 18, count 0 2006.169.08:02:49.62#ibcon#about to read 3, iclass 18, count 0 2006.169.08:02:49.65#ibcon#read 3, iclass 18, count 0 2006.169.08:02:49.65#ibcon#about to read 4, iclass 18, count 0 2006.169.08:02:49.65#ibcon#read 4, iclass 18, count 0 2006.169.08:02:49.65#ibcon#about to read 5, iclass 18, count 0 2006.169.08:02:49.65#ibcon#read 5, iclass 18, count 0 2006.169.08:02:49.65#ibcon#about to read 6, iclass 18, count 0 2006.169.08:02:49.65#ibcon#read 6, iclass 18, count 0 2006.169.08:02:49.65#ibcon#end of sib2, iclass 18, count 0 2006.169.08:02:49.65#ibcon#*after write, iclass 18, count 0 2006.169.08:02:49.65#ibcon#*before return 0, iclass 18, count 0 2006.169.08:02:49.65#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:02:49.65#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:02:49.65#ibcon#about to clear, iclass 18 cls_cnt 0 2006.169.08:02:49.65#ibcon#cleared, iclass 18 cls_cnt 0 2006.169.08:02:49.65$4f8m12a/ifd4f 2006.169.08:02:49.65$ifd4f/lo= 2006.169.08:02:49.65$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.08:02:49.65$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.08:02:49.65$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.08:02:49.65$ifd4f/patch= 2006.169.08:02:49.65$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.08:02:49.65$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.08:02:49.65$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.08:02:49.65$4f8m12a/"form=m,16.000,1:2 2006.169.08:02:49.65$4f8m12a/"tpicd 2006.169.08:02:49.65$4f8m12a/echo=off 2006.169.08:02:49.65$4f8m12a/xlog=off 2006.169.08:02:49.65:!2006.169.08:03:00 2006.169.08:03:00.00:preob 2006.169.08:03:01.13/onsource/TRACKING 2006.169.08:03:01.13:!2006.169.08:03:10 2006.169.08:03:10.00:data_valid=on 2006.169.08:03:10.00:midob 2006.169.08:03:10.13/onsource/TRACKING 2006.169.08:03:10.13/wx/18.12,1004.0,100 2006.169.08:03:10.22/cable/+6.5298E-03 2006.169.08:03:11.31/va/01,08,usb,yes,48,50 2006.169.08:03:11.31/va/02,07,usb,yes,49,51 2006.169.08:03:11.31/va/03,06,usb,yes,51,52 2006.169.08:03:11.31/va/04,07,usb,yes,50,54 2006.169.08:03:11.31/va/05,07,usb,yes,55,58 2006.169.08:03:11.31/va/06,06,usb,yes,55,54 2006.169.08:03:11.31/va/07,06,usb,yes,55,55 2006.169.08:03:11.31/va/08,07,usb,yes,52,52 2006.169.08:03:11.54/valo/01,532.99,yes,locked 2006.169.08:03:11.54/valo/02,572.99,yes,locked 2006.169.08:03:11.54/valo/03,672.99,yes,locked 2006.169.08:03:11.54/valo/04,832.99,yes,locked 2006.169.08:03:11.54/valo/05,652.99,yes,locked 2006.169.08:03:11.54/valo/06,772.99,yes,locked 2006.169.08:03:11.54/valo/07,832.99,yes,locked 2006.169.08:03:11.54/valo/08,852.99,yes,locked 2006.169.08:03:12.63/vb/01,04,usb,yes,31,30 2006.169.08:03:12.63/vb/02,04,usb,yes,33,34 2006.169.08:03:12.63/vb/03,04,usb,yes,29,33 2006.169.08:03:12.63/vb/04,04,usb,yes,30,30 2006.169.08:03:12.63/vb/05,04,usb,yes,29,33 2006.169.08:03:12.63/vb/06,04,usb,yes,30,33 2006.169.08:03:12.63/vb/07,04,usb,yes,32,32 2006.169.08:03:12.63/vb/08,04,usb,yes,29,33 2006.169.08:03:12.86/vblo/01,632.99,yes,locked 2006.169.08:03:12.86/vblo/02,640.99,yes,locked 2006.169.08:03:12.86/vblo/03,656.99,yes,locked 2006.169.08:03:12.86/vblo/04,712.99,yes,locked 2006.169.08:03:12.86/vblo/05,744.99,yes,locked 2006.169.08:03:12.86/vblo/06,752.99,yes,locked 2006.169.08:03:12.86/vblo/07,734.99,yes,locked 2006.169.08:03:12.86/vblo/08,744.99,yes,locked 2006.169.08:03:13.01/vabw/8 2006.169.08:03:13.16/vbbw/8 2006.169.08:03:13.25/xfe/off,on,14.7 2006.169.08:03:13.64/ifatt/23,28,28,28 2006.169.08:03:14.08/fmout-gps/S +4.18E-07 2006.169.08:03:14.16:!2006.169.08:04:10 2006.169.08:04:10.00:data_valid=off 2006.169.08:04:10.00:postob 2006.169.08:04:10.09/cable/+6.5277E-03 2006.169.08:04:10.09/wx/18.12,1003.9,100 2006.169.08:04:11.08/fmout-gps/S +4.18E-07 2006.169.08:04:11.08:scan_name=169-0805,k06169,60 2006.169.08:04:11.09:source=1357+769,135755.37,764321.1,2000.0,cw 2006.169.08:04:11.13#flagr#flagr/antenna,new-source 2006.169.08:04:12.14:checkk5 2006.169.08:04:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.169.08:04:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.169.08:04:16.91/chk_autoobs//k5ts3?ERROR: timeout happened! 2006.169.08:04:17.29/chk_autoobs//k5ts4/ autoobs is running! 2006.169.08:04:17.66/chk_obsdata//k5ts1/T1690803??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.08:04:18.03/chk_obsdata//k5ts2/T1690803??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.08:04:25.09/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.08:04:25.46/chk_obsdata//k5ts4/T1690803??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.08:04:26.15/k5log//k5ts1_log_newline 2006.169.08:04:26.84/k5log//k5ts2_log_newline 2006.169.08:04:31.14#trakl#Source acquired 2006.169.08:04:32.14#flagr#flagr/antenna,acquired 2006.169.08:04:33.94/k5log//k5ts3?ERROR: timeout happened! 2006.169.08:04:34.63/k5log//k5ts4_log_newline 2006.169.08:04:34.79/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.08:04:34.79:4f8m12a=2 2006.169.08:04:34.79$4f8m12a/echo=on 2006.169.08:04:34.79$4f8m12a/pcalon 2006.169.08:04:34.79$pcalon/"no phase cal control is implemented here 2006.169.08:04:34.79$4f8m12a/"tpicd=stop 2006.169.08:04:34.79$4f8m12a/vc4f8 2006.169.08:04:34.79$vc4f8/valo=1,532.99 2006.169.08:04:34.80#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.169.08:04:34.80#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.169.08:04:34.80#ibcon#ireg 17 cls_cnt 0 2006.169.08:04:34.80#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:04:34.80#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:04:34.80#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:04:34.80#ibcon#enter wrdev, iclass 20, count 0 2006.169.08:04:34.80#ibcon#first serial, iclass 20, count 0 2006.169.08:04:34.80#ibcon#enter sib2, iclass 20, count 0 2006.169.08:04:34.80#ibcon#flushed, iclass 20, count 0 2006.169.08:04:34.80#ibcon#about to write, iclass 20, count 0 2006.169.08:04:34.80#ibcon#wrote, iclass 20, count 0 2006.169.08:04:34.80#ibcon#about to read 3, iclass 20, count 0 2006.169.08:04:34.82#ibcon#read 3, iclass 20, count 0 2006.169.08:04:34.82#ibcon#about to read 4, iclass 20, count 0 2006.169.08:04:34.82#ibcon#read 4, iclass 20, count 0 2006.169.08:04:34.82#ibcon#about to read 5, iclass 20, count 0 2006.169.08:04:34.82#ibcon#read 5, iclass 20, count 0 2006.169.08:04:34.82#ibcon#about to read 6, iclass 20, count 0 2006.169.08:04:34.82#ibcon#read 6, iclass 20, count 0 2006.169.08:04:34.82#ibcon#end of sib2, iclass 20, count 0 2006.169.08:04:34.82#ibcon#*mode == 0, iclass 20, count 0 2006.169.08:04:34.82#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.169.08:04:34.82#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.08:04:34.82#ibcon#*before write, iclass 20, count 0 2006.169.08:04:34.82#ibcon#enter sib2, iclass 20, count 0 2006.169.08:04:34.82#ibcon#flushed, iclass 20, count 0 2006.169.08:04:34.82#ibcon#about to write, iclass 20, count 0 2006.169.08:04:34.82#ibcon#wrote, iclass 20, count 0 2006.169.08:04:34.82#ibcon#about to read 3, iclass 20, count 0 2006.169.08:04:34.87#ibcon#read 3, iclass 20, count 0 2006.169.08:04:34.87#ibcon#about to read 4, iclass 20, count 0 2006.169.08:04:34.87#ibcon#read 4, iclass 20, count 0 2006.169.08:04:34.87#ibcon#about to read 5, iclass 20, count 0 2006.169.08:04:34.87#ibcon#read 5, iclass 20, count 0 2006.169.08:04:34.87#ibcon#about to read 6, iclass 20, count 0 2006.169.08:04:34.87#ibcon#read 6, iclass 20, count 0 2006.169.08:04:34.87#ibcon#end of sib2, iclass 20, count 0 2006.169.08:04:34.87#ibcon#*after write, iclass 20, count 0 2006.169.08:04:34.87#ibcon#*before return 0, iclass 20, count 0 2006.169.08:04:34.87#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:04:34.87#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:04:34.87#ibcon#about to clear, iclass 20 cls_cnt 0 2006.169.08:04:34.87#ibcon#cleared, iclass 20 cls_cnt 0 2006.169.08:04:34.87$vc4f8/va=1,8 2006.169.08:04:34.87#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.169.08:04:34.87#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.169.08:04:34.87#ibcon#ireg 11 cls_cnt 2 2006.169.08:04:34.87#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:04:34.87#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:04:34.87#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:04:34.87#ibcon#enter wrdev, iclass 22, count 2 2006.169.08:04:34.87#ibcon#first serial, iclass 22, count 2 2006.169.08:04:34.87#ibcon#enter sib2, iclass 22, count 2 2006.169.08:04:34.87#ibcon#flushed, iclass 22, count 2 2006.169.08:04:34.87#ibcon#about to write, iclass 22, count 2 2006.169.08:04:34.87#ibcon#wrote, iclass 22, count 2 2006.169.08:04:34.87#ibcon#about to read 3, iclass 22, count 2 2006.169.08:04:34.89#ibcon#read 3, iclass 22, count 2 2006.169.08:04:34.89#ibcon#about to read 4, iclass 22, count 2 2006.169.08:04:34.89#ibcon#read 4, iclass 22, count 2 2006.169.08:04:34.89#ibcon#about to read 5, iclass 22, count 2 2006.169.08:04:34.89#ibcon#read 5, iclass 22, count 2 2006.169.08:04:34.89#ibcon#about to read 6, iclass 22, count 2 2006.169.08:04:34.89#ibcon#read 6, iclass 22, count 2 2006.169.08:04:34.89#ibcon#end of sib2, iclass 22, count 2 2006.169.08:04:34.89#ibcon#*mode == 0, iclass 22, count 2 2006.169.08:04:34.89#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.169.08:04:34.89#ibcon#[25=AT01-08\r\n] 2006.169.08:04:34.89#ibcon#*before write, iclass 22, count 2 2006.169.08:04:34.89#ibcon#enter sib2, iclass 22, count 2 2006.169.08:04:34.89#ibcon#flushed, iclass 22, count 2 2006.169.08:04:34.89#ibcon#about to write, iclass 22, count 2 2006.169.08:04:34.89#ibcon#wrote, iclass 22, count 2 2006.169.08:04:34.89#ibcon#about to read 3, iclass 22, count 2 2006.169.08:04:34.92#ibcon#read 3, iclass 22, count 2 2006.169.08:04:34.92#ibcon#about to read 4, iclass 22, count 2 2006.169.08:04:34.92#ibcon#read 4, iclass 22, count 2 2006.169.08:04:34.92#ibcon#about to read 5, iclass 22, count 2 2006.169.08:04:34.92#ibcon#read 5, iclass 22, count 2 2006.169.08:04:34.92#ibcon#about to read 6, iclass 22, count 2 2006.169.08:04:34.92#ibcon#read 6, iclass 22, count 2 2006.169.08:04:34.92#ibcon#end of sib2, iclass 22, count 2 2006.169.08:04:34.92#ibcon#*after write, iclass 22, count 2 2006.169.08:04:34.92#ibcon#*before return 0, iclass 22, count 2 2006.169.08:04:34.92#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:04:34.92#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:04:34.92#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.169.08:04:34.92#ibcon#ireg 7 cls_cnt 0 2006.169.08:04:34.92#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:04:35.04#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:04:35.04#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:04:35.04#ibcon#enter wrdev, iclass 22, count 0 2006.169.08:04:35.04#ibcon#first serial, iclass 22, count 0 2006.169.08:04:35.04#ibcon#enter sib2, iclass 22, count 0 2006.169.08:04:35.04#ibcon#flushed, iclass 22, count 0 2006.169.08:04:35.04#ibcon#about to write, iclass 22, count 0 2006.169.08:04:35.04#ibcon#wrote, iclass 22, count 0 2006.169.08:04:35.04#ibcon#about to read 3, iclass 22, count 0 2006.169.08:04:35.08#ibcon#read 3, iclass 22, count 0 2006.169.08:04:35.08#ibcon#about to read 4, iclass 22, count 0 2006.169.08:04:35.08#ibcon#read 4, iclass 22, count 0 2006.169.08:04:35.08#ibcon#about to read 5, iclass 22, count 0 2006.169.08:04:35.08#ibcon#read 5, iclass 22, count 0 2006.169.08:04:35.08#ibcon#about to read 6, iclass 22, count 0 2006.169.08:04:35.08#ibcon#read 6, iclass 22, count 0 2006.169.08:04:35.08#ibcon#end of sib2, iclass 22, count 0 2006.169.08:04:35.08#ibcon#*mode == 0, iclass 22, count 0 2006.169.08:04:35.08#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.169.08:04:35.08#ibcon#[25=USB\r\n] 2006.169.08:04:35.08#ibcon#*before write, iclass 22, count 0 2006.169.08:04:35.08#ibcon#enter sib2, iclass 22, count 0 2006.169.08:04:35.08#ibcon#flushed, iclass 22, count 0 2006.169.08:04:35.08#ibcon#about to write, iclass 22, count 0 2006.169.08:04:35.08#ibcon#wrote, iclass 22, count 0 2006.169.08:04:35.08#ibcon#about to read 3, iclass 22, count 0 2006.169.08:04:35.11#ibcon#read 3, iclass 22, count 0 2006.169.08:04:35.11#ibcon#about to read 4, iclass 22, count 0 2006.169.08:04:35.11#ibcon#read 4, iclass 22, count 0 2006.169.08:04:35.11#ibcon#about to read 5, iclass 22, count 0 2006.169.08:04:35.11#ibcon#read 5, iclass 22, count 0 2006.169.08:04:35.11#ibcon#about to read 6, iclass 22, count 0 2006.169.08:04:35.11#ibcon#read 6, iclass 22, count 0 2006.169.08:04:35.11#ibcon#end of sib2, iclass 22, count 0 2006.169.08:04:35.11#ibcon#*after write, iclass 22, count 0 2006.169.08:04:35.11#ibcon#*before return 0, iclass 22, count 0 2006.169.08:04:35.11#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:04:35.11#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:04:35.11#ibcon#about to clear, iclass 22 cls_cnt 0 2006.169.08:04:35.11#ibcon#cleared, iclass 22 cls_cnt 0 2006.169.08:04:35.11$vc4f8/valo=2,572.99 2006.169.08:04:35.11#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.169.08:04:35.11#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.169.08:04:35.11#ibcon#ireg 17 cls_cnt 0 2006.169.08:04:35.11#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:04:35.11#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:04:35.11#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:04:35.11#ibcon#enter wrdev, iclass 24, count 0 2006.169.08:04:35.11#ibcon#first serial, iclass 24, count 0 2006.169.08:04:35.11#ibcon#enter sib2, iclass 24, count 0 2006.169.08:04:35.11#ibcon#flushed, iclass 24, count 0 2006.169.08:04:35.11#ibcon#about to write, iclass 24, count 0 2006.169.08:04:35.11#ibcon#wrote, iclass 24, count 0 2006.169.08:04:35.11#ibcon#about to read 3, iclass 24, count 0 2006.169.08:04:35.13#ibcon#read 3, iclass 24, count 0 2006.169.08:04:35.13#ibcon#about to read 4, iclass 24, count 0 2006.169.08:04:35.13#ibcon#read 4, iclass 24, count 0 2006.169.08:04:35.13#ibcon#about to read 5, iclass 24, count 0 2006.169.08:04:35.13#ibcon#read 5, iclass 24, count 0 2006.169.08:04:35.13#ibcon#about to read 6, iclass 24, count 0 2006.169.08:04:35.13#ibcon#read 6, iclass 24, count 0 2006.169.08:04:35.13#ibcon#end of sib2, iclass 24, count 0 2006.169.08:04:35.13#ibcon#*mode == 0, iclass 24, count 0 2006.169.08:04:35.13#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.169.08:04:35.13#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.08:04:35.13#ibcon#*before write, iclass 24, count 0 2006.169.08:04:35.13#ibcon#enter sib2, iclass 24, count 0 2006.169.08:04:35.13#ibcon#flushed, iclass 24, count 0 2006.169.08:04:35.13#ibcon#about to write, iclass 24, count 0 2006.169.08:04:35.13#ibcon#wrote, iclass 24, count 0 2006.169.08:04:35.13#ibcon#about to read 3, iclass 24, count 0 2006.169.08:04:35.17#ibcon#read 3, iclass 24, count 0 2006.169.08:04:35.17#ibcon#about to read 4, iclass 24, count 0 2006.169.08:04:35.17#ibcon#read 4, iclass 24, count 0 2006.169.08:04:35.17#ibcon#about to read 5, iclass 24, count 0 2006.169.08:04:35.17#ibcon#read 5, iclass 24, count 0 2006.169.08:04:35.17#ibcon#about to read 6, iclass 24, count 0 2006.169.08:04:35.17#ibcon#read 6, iclass 24, count 0 2006.169.08:04:35.17#ibcon#end of sib2, iclass 24, count 0 2006.169.08:04:35.17#ibcon#*after write, iclass 24, count 0 2006.169.08:04:35.17#ibcon#*before return 0, iclass 24, count 0 2006.169.08:04:35.17#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:04:35.17#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:04:35.17#ibcon#about to clear, iclass 24 cls_cnt 0 2006.169.08:04:35.17#ibcon#cleared, iclass 24 cls_cnt 0 2006.169.08:04:35.17$vc4f8/va=2,7 2006.169.08:04:35.17#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.169.08:04:35.17#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.169.08:04:35.17#ibcon#ireg 11 cls_cnt 2 2006.169.08:04:35.17#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.169.08:04:35.23#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.169.08:04:35.23#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.169.08:04:35.23#ibcon#enter wrdev, iclass 26, count 2 2006.169.08:04:35.23#ibcon#first serial, iclass 26, count 2 2006.169.08:04:35.23#ibcon#enter sib2, iclass 26, count 2 2006.169.08:04:35.23#ibcon#flushed, iclass 26, count 2 2006.169.08:04:35.23#ibcon#about to write, iclass 26, count 2 2006.169.08:04:35.23#ibcon#wrote, iclass 26, count 2 2006.169.08:04:35.23#ibcon#about to read 3, iclass 26, count 2 2006.169.08:04:35.25#ibcon#read 3, iclass 26, count 2 2006.169.08:04:35.25#ibcon#about to read 4, iclass 26, count 2 2006.169.08:04:35.25#ibcon#read 4, iclass 26, count 2 2006.169.08:04:35.25#ibcon#about to read 5, iclass 26, count 2 2006.169.08:04:35.25#ibcon#read 5, iclass 26, count 2 2006.169.08:04:35.25#ibcon#about to read 6, iclass 26, count 2 2006.169.08:04:35.25#ibcon#read 6, iclass 26, count 2 2006.169.08:04:35.25#ibcon#end of sib2, iclass 26, count 2 2006.169.08:04:35.25#ibcon#*mode == 0, iclass 26, count 2 2006.169.08:04:35.25#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.169.08:04:35.25#ibcon#[25=AT02-07\r\n] 2006.169.08:04:35.25#ibcon#*before write, iclass 26, count 2 2006.169.08:04:35.25#ibcon#enter sib2, iclass 26, count 2 2006.169.08:04:35.25#ibcon#flushed, iclass 26, count 2 2006.169.08:04:35.25#ibcon#about to write, iclass 26, count 2 2006.169.08:04:35.25#ibcon#wrote, iclass 26, count 2 2006.169.08:04:35.25#ibcon#about to read 3, iclass 26, count 2 2006.169.08:04:35.29#ibcon#read 3, iclass 26, count 2 2006.169.08:04:35.29#ibcon#about to read 4, iclass 26, count 2 2006.169.08:04:35.29#ibcon#read 4, iclass 26, count 2 2006.169.08:04:35.29#ibcon#about to read 5, iclass 26, count 2 2006.169.08:04:35.29#ibcon#read 5, iclass 26, count 2 2006.169.08:04:35.29#ibcon#about to read 6, iclass 26, count 2 2006.169.08:04:35.29#ibcon#read 6, iclass 26, count 2 2006.169.08:04:35.29#ibcon#end of sib2, iclass 26, count 2 2006.169.08:04:35.29#ibcon#*after write, iclass 26, count 2 2006.169.08:04:35.29#ibcon#*before return 0, iclass 26, count 2 2006.169.08:04:35.29#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.169.08:04:35.29#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.169.08:04:35.29#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.169.08:04:35.29#ibcon#ireg 7 cls_cnt 0 2006.169.08:04:35.29#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.169.08:04:35.41#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.169.08:04:35.41#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.169.08:04:35.41#ibcon#enter wrdev, iclass 26, count 0 2006.169.08:04:35.41#ibcon#first serial, iclass 26, count 0 2006.169.08:04:35.41#ibcon#enter sib2, iclass 26, count 0 2006.169.08:04:35.41#ibcon#flushed, iclass 26, count 0 2006.169.08:04:35.41#ibcon#about to write, iclass 26, count 0 2006.169.08:04:35.41#ibcon#wrote, iclass 26, count 0 2006.169.08:04:35.41#ibcon#about to read 3, iclass 26, count 0 2006.169.08:04:35.43#ibcon#read 3, iclass 26, count 0 2006.169.08:04:35.43#ibcon#about to read 4, iclass 26, count 0 2006.169.08:04:35.43#ibcon#read 4, iclass 26, count 0 2006.169.08:04:35.43#ibcon#about to read 5, iclass 26, count 0 2006.169.08:04:35.43#ibcon#read 5, iclass 26, count 0 2006.169.08:04:35.43#ibcon#about to read 6, iclass 26, count 0 2006.169.08:04:35.43#ibcon#read 6, iclass 26, count 0 2006.169.08:04:35.43#ibcon#end of sib2, iclass 26, count 0 2006.169.08:04:35.43#ibcon#*mode == 0, iclass 26, count 0 2006.169.08:04:35.43#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.169.08:04:35.43#ibcon#[25=USB\r\n] 2006.169.08:04:35.43#ibcon#*before write, iclass 26, count 0 2006.169.08:04:35.43#ibcon#enter sib2, iclass 26, count 0 2006.169.08:04:35.43#ibcon#flushed, iclass 26, count 0 2006.169.08:04:35.43#ibcon#about to write, iclass 26, count 0 2006.169.08:04:35.43#ibcon#wrote, iclass 26, count 0 2006.169.08:04:35.43#ibcon#about to read 3, iclass 26, count 0 2006.169.08:04:35.46#ibcon#read 3, iclass 26, count 0 2006.169.08:04:35.46#ibcon#about to read 4, iclass 26, count 0 2006.169.08:04:35.46#ibcon#read 4, iclass 26, count 0 2006.169.08:04:35.46#ibcon#about to read 5, iclass 26, count 0 2006.169.08:04:35.46#ibcon#read 5, iclass 26, count 0 2006.169.08:04:35.46#ibcon#about to read 6, iclass 26, count 0 2006.169.08:04:35.46#ibcon#read 6, iclass 26, count 0 2006.169.08:04:35.46#ibcon#end of sib2, iclass 26, count 0 2006.169.08:04:35.46#ibcon#*after write, iclass 26, count 0 2006.169.08:04:35.46#ibcon#*before return 0, iclass 26, count 0 2006.169.08:04:35.46#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.169.08:04:35.46#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.169.08:04:35.46#ibcon#about to clear, iclass 26 cls_cnt 0 2006.169.08:04:35.46#ibcon#cleared, iclass 26 cls_cnt 0 2006.169.08:04:35.46$vc4f8/valo=3,672.99 2006.169.08:04:35.46#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.169.08:04:35.46#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.169.08:04:35.46#ibcon#ireg 17 cls_cnt 0 2006.169.08:04:35.46#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:04:35.46#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:04:35.46#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:04:35.46#ibcon#enter wrdev, iclass 28, count 0 2006.169.08:04:35.46#ibcon#first serial, iclass 28, count 0 2006.169.08:04:35.46#ibcon#enter sib2, iclass 28, count 0 2006.169.08:04:35.46#ibcon#flushed, iclass 28, count 0 2006.169.08:04:35.46#ibcon#about to write, iclass 28, count 0 2006.169.08:04:35.46#ibcon#wrote, iclass 28, count 0 2006.169.08:04:35.46#ibcon#about to read 3, iclass 28, count 0 2006.169.08:04:35.48#ibcon#read 3, iclass 28, count 0 2006.169.08:04:35.48#ibcon#about to read 4, iclass 28, count 0 2006.169.08:04:35.48#ibcon#read 4, iclass 28, count 0 2006.169.08:04:35.48#ibcon#about to read 5, iclass 28, count 0 2006.169.08:04:35.48#ibcon#read 5, iclass 28, count 0 2006.169.08:04:35.48#ibcon#about to read 6, iclass 28, count 0 2006.169.08:04:35.48#ibcon#read 6, iclass 28, count 0 2006.169.08:04:35.48#ibcon#end of sib2, iclass 28, count 0 2006.169.08:04:35.48#ibcon#*mode == 0, iclass 28, count 0 2006.169.08:04:35.48#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.169.08:04:35.48#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.08:04:35.48#ibcon#*before write, iclass 28, count 0 2006.169.08:04:35.48#ibcon#enter sib2, iclass 28, count 0 2006.169.08:04:35.48#ibcon#flushed, iclass 28, count 0 2006.169.08:04:35.48#ibcon#about to write, iclass 28, count 0 2006.169.08:04:35.48#ibcon#wrote, iclass 28, count 0 2006.169.08:04:35.48#ibcon#about to read 3, iclass 28, count 0 2006.169.08:04:35.52#ibcon#read 3, iclass 28, count 0 2006.169.08:04:35.52#ibcon#about to read 4, iclass 28, count 0 2006.169.08:04:35.52#ibcon#read 4, iclass 28, count 0 2006.169.08:04:35.52#ibcon#about to read 5, iclass 28, count 0 2006.169.08:04:35.52#ibcon#read 5, iclass 28, count 0 2006.169.08:04:35.52#ibcon#about to read 6, iclass 28, count 0 2006.169.08:04:35.52#ibcon#read 6, iclass 28, count 0 2006.169.08:04:35.52#ibcon#end of sib2, iclass 28, count 0 2006.169.08:04:35.52#ibcon#*after write, iclass 28, count 0 2006.169.08:04:35.52#ibcon#*before return 0, iclass 28, count 0 2006.169.08:04:35.52#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:04:35.52#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:04:35.52#ibcon#about to clear, iclass 28 cls_cnt 0 2006.169.08:04:35.52#ibcon#cleared, iclass 28 cls_cnt 0 2006.169.08:04:35.52$vc4f8/va=3,6 2006.169.08:04:35.52#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.169.08:04:35.52#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.169.08:04:35.52#ibcon#ireg 11 cls_cnt 2 2006.169.08:04:35.52#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:04:35.58#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:04:35.58#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:04:35.58#ibcon#enter wrdev, iclass 30, count 2 2006.169.08:04:35.58#ibcon#first serial, iclass 30, count 2 2006.169.08:04:35.58#ibcon#enter sib2, iclass 30, count 2 2006.169.08:04:35.58#ibcon#flushed, iclass 30, count 2 2006.169.08:04:35.58#ibcon#about to write, iclass 30, count 2 2006.169.08:04:35.58#ibcon#wrote, iclass 30, count 2 2006.169.08:04:35.58#ibcon#about to read 3, iclass 30, count 2 2006.169.08:04:35.60#ibcon#read 3, iclass 30, count 2 2006.169.08:04:35.60#ibcon#about to read 4, iclass 30, count 2 2006.169.08:04:35.60#ibcon#read 4, iclass 30, count 2 2006.169.08:04:35.60#ibcon#about to read 5, iclass 30, count 2 2006.169.08:04:35.60#ibcon#read 5, iclass 30, count 2 2006.169.08:04:35.60#ibcon#about to read 6, iclass 30, count 2 2006.169.08:04:35.60#ibcon#read 6, iclass 30, count 2 2006.169.08:04:35.60#ibcon#end of sib2, iclass 30, count 2 2006.169.08:04:35.60#ibcon#*mode == 0, iclass 30, count 2 2006.169.08:04:35.60#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.169.08:04:35.60#ibcon#[25=AT03-06\r\n] 2006.169.08:04:35.60#ibcon#*before write, iclass 30, count 2 2006.169.08:04:35.60#ibcon#enter sib2, iclass 30, count 2 2006.169.08:04:35.60#ibcon#flushed, iclass 30, count 2 2006.169.08:04:35.60#ibcon#about to write, iclass 30, count 2 2006.169.08:04:35.60#ibcon#wrote, iclass 30, count 2 2006.169.08:04:35.60#ibcon#about to read 3, iclass 30, count 2 2006.169.08:04:35.63#ibcon#read 3, iclass 30, count 2 2006.169.08:04:35.63#ibcon#about to read 4, iclass 30, count 2 2006.169.08:04:35.63#ibcon#read 4, iclass 30, count 2 2006.169.08:04:35.63#ibcon#about to read 5, iclass 30, count 2 2006.169.08:04:35.63#ibcon#read 5, iclass 30, count 2 2006.169.08:04:35.63#ibcon#about to read 6, iclass 30, count 2 2006.169.08:04:35.63#ibcon#read 6, iclass 30, count 2 2006.169.08:04:35.63#ibcon#end of sib2, iclass 30, count 2 2006.169.08:04:35.63#ibcon#*after write, iclass 30, count 2 2006.169.08:04:35.63#ibcon#*before return 0, iclass 30, count 2 2006.169.08:04:35.63#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:04:35.63#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:04:35.63#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.169.08:04:35.63#ibcon#ireg 7 cls_cnt 0 2006.169.08:04:35.63#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:04:35.75#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:04:35.75#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:04:35.75#ibcon#enter wrdev, iclass 30, count 0 2006.169.08:04:35.75#ibcon#first serial, iclass 30, count 0 2006.169.08:04:35.75#ibcon#enter sib2, iclass 30, count 0 2006.169.08:04:35.75#ibcon#flushed, iclass 30, count 0 2006.169.08:04:35.75#ibcon#about to write, iclass 30, count 0 2006.169.08:04:35.75#ibcon#wrote, iclass 30, count 0 2006.169.08:04:35.75#ibcon#about to read 3, iclass 30, count 0 2006.169.08:04:35.77#ibcon#read 3, iclass 30, count 0 2006.169.08:04:35.77#ibcon#about to read 4, iclass 30, count 0 2006.169.08:04:35.77#ibcon#read 4, iclass 30, count 0 2006.169.08:04:35.77#ibcon#about to read 5, iclass 30, count 0 2006.169.08:04:35.77#ibcon#read 5, iclass 30, count 0 2006.169.08:04:35.77#ibcon#about to read 6, iclass 30, count 0 2006.169.08:04:35.77#ibcon#read 6, iclass 30, count 0 2006.169.08:04:35.77#ibcon#end of sib2, iclass 30, count 0 2006.169.08:04:35.77#ibcon#*mode == 0, iclass 30, count 0 2006.169.08:04:35.77#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.169.08:04:35.77#ibcon#[25=USB\r\n] 2006.169.08:04:35.77#ibcon#*before write, iclass 30, count 0 2006.169.08:04:35.77#ibcon#enter sib2, iclass 30, count 0 2006.169.08:04:35.77#ibcon#flushed, iclass 30, count 0 2006.169.08:04:35.77#ibcon#about to write, iclass 30, count 0 2006.169.08:04:35.77#ibcon#wrote, iclass 30, count 0 2006.169.08:04:35.77#ibcon#about to read 3, iclass 30, count 0 2006.169.08:04:35.80#ibcon#read 3, iclass 30, count 0 2006.169.08:04:35.80#ibcon#about to read 4, iclass 30, count 0 2006.169.08:04:35.80#ibcon#read 4, iclass 30, count 0 2006.169.08:04:35.80#ibcon#about to read 5, iclass 30, count 0 2006.169.08:04:35.80#ibcon#read 5, iclass 30, count 0 2006.169.08:04:35.80#ibcon#about to read 6, iclass 30, count 0 2006.169.08:04:35.80#ibcon#read 6, iclass 30, count 0 2006.169.08:04:35.80#ibcon#end of sib2, iclass 30, count 0 2006.169.08:04:35.80#ibcon#*after write, iclass 30, count 0 2006.169.08:04:35.80#ibcon#*before return 0, iclass 30, count 0 2006.169.08:04:35.80#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:04:35.80#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:04:35.80#ibcon#about to clear, iclass 30 cls_cnt 0 2006.169.08:04:35.80#ibcon#cleared, iclass 30 cls_cnt 0 2006.169.08:04:35.80$vc4f8/valo=4,832.99 2006.169.08:04:35.80#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.169.08:04:35.80#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.169.08:04:35.80#ibcon#ireg 17 cls_cnt 0 2006.169.08:04:35.80#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:04:35.80#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:04:35.80#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:04:35.80#ibcon#enter wrdev, iclass 32, count 0 2006.169.08:04:35.80#ibcon#first serial, iclass 32, count 0 2006.169.08:04:35.80#ibcon#enter sib2, iclass 32, count 0 2006.169.08:04:35.80#ibcon#flushed, iclass 32, count 0 2006.169.08:04:35.80#ibcon#about to write, iclass 32, count 0 2006.169.08:04:35.80#ibcon#wrote, iclass 32, count 0 2006.169.08:04:35.80#ibcon#about to read 3, iclass 32, count 0 2006.169.08:04:35.82#ibcon#read 3, iclass 32, count 0 2006.169.08:04:35.82#ibcon#about to read 4, iclass 32, count 0 2006.169.08:04:35.82#ibcon#read 4, iclass 32, count 0 2006.169.08:04:35.82#ibcon#about to read 5, iclass 32, count 0 2006.169.08:04:35.82#ibcon#read 5, iclass 32, count 0 2006.169.08:04:35.82#ibcon#about to read 6, iclass 32, count 0 2006.169.08:04:35.82#ibcon#read 6, iclass 32, count 0 2006.169.08:04:35.82#ibcon#end of sib2, iclass 32, count 0 2006.169.08:04:35.82#ibcon#*mode == 0, iclass 32, count 0 2006.169.08:04:35.82#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.169.08:04:35.82#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.08:04:35.82#ibcon#*before write, iclass 32, count 0 2006.169.08:04:35.82#ibcon#enter sib2, iclass 32, count 0 2006.169.08:04:35.82#ibcon#flushed, iclass 32, count 0 2006.169.08:04:35.82#ibcon#about to write, iclass 32, count 0 2006.169.08:04:35.82#ibcon#wrote, iclass 32, count 0 2006.169.08:04:35.82#ibcon#about to read 3, iclass 32, count 0 2006.169.08:04:35.86#ibcon#read 3, iclass 32, count 0 2006.169.08:04:35.86#ibcon#about to read 4, iclass 32, count 0 2006.169.08:04:35.86#ibcon#read 4, iclass 32, count 0 2006.169.08:04:35.86#ibcon#about to read 5, iclass 32, count 0 2006.169.08:04:35.86#ibcon#read 5, iclass 32, count 0 2006.169.08:04:35.86#ibcon#about to read 6, iclass 32, count 0 2006.169.08:04:35.86#ibcon#read 6, iclass 32, count 0 2006.169.08:04:35.86#ibcon#end of sib2, iclass 32, count 0 2006.169.08:04:35.86#ibcon#*after write, iclass 32, count 0 2006.169.08:04:35.86#ibcon#*before return 0, iclass 32, count 0 2006.169.08:04:35.86#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:04:35.86#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:04:35.86#ibcon#about to clear, iclass 32 cls_cnt 0 2006.169.08:04:35.86#ibcon#cleared, iclass 32 cls_cnt 0 2006.169.08:04:35.86$vc4f8/va=4,7 2006.169.08:04:35.86#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.169.08:04:35.86#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.169.08:04:35.86#ibcon#ireg 11 cls_cnt 2 2006.169.08:04:35.86#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:04:35.92#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:04:35.92#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:04:35.92#ibcon#enter wrdev, iclass 34, count 2 2006.169.08:04:35.92#ibcon#first serial, iclass 34, count 2 2006.169.08:04:35.92#ibcon#enter sib2, iclass 34, count 2 2006.169.08:04:35.92#ibcon#flushed, iclass 34, count 2 2006.169.08:04:35.92#ibcon#about to write, iclass 34, count 2 2006.169.08:04:35.92#ibcon#wrote, iclass 34, count 2 2006.169.08:04:35.92#ibcon#about to read 3, iclass 34, count 2 2006.169.08:04:35.94#ibcon#read 3, iclass 34, count 2 2006.169.08:04:35.94#ibcon#about to read 4, iclass 34, count 2 2006.169.08:04:35.94#ibcon#read 4, iclass 34, count 2 2006.169.08:04:35.94#ibcon#about to read 5, iclass 34, count 2 2006.169.08:04:35.94#ibcon#read 5, iclass 34, count 2 2006.169.08:04:35.94#ibcon#about to read 6, iclass 34, count 2 2006.169.08:04:35.94#ibcon#read 6, iclass 34, count 2 2006.169.08:04:35.94#ibcon#end of sib2, iclass 34, count 2 2006.169.08:04:35.94#ibcon#*mode == 0, iclass 34, count 2 2006.169.08:04:35.94#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.169.08:04:35.94#ibcon#[25=AT04-07\r\n] 2006.169.08:04:35.94#ibcon#*before write, iclass 34, count 2 2006.169.08:04:35.94#ibcon#enter sib2, iclass 34, count 2 2006.169.08:04:35.94#ibcon#flushed, iclass 34, count 2 2006.169.08:04:35.94#ibcon#about to write, iclass 34, count 2 2006.169.08:04:35.94#ibcon#wrote, iclass 34, count 2 2006.169.08:04:35.94#ibcon#about to read 3, iclass 34, count 2 2006.169.08:04:35.97#ibcon#read 3, iclass 34, count 2 2006.169.08:04:35.97#ibcon#about to read 4, iclass 34, count 2 2006.169.08:04:35.97#ibcon#read 4, iclass 34, count 2 2006.169.08:04:35.97#ibcon#about to read 5, iclass 34, count 2 2006.169.08:04:35.97#ibcon#read 5, iclass 34, count 2 2006.169.08:04:35.97#ibcon#about to read 6, iclass 34, count 2 2006.169.08:04:35.97#ibcon#read 6, iclass 34, count 2 2006.169.08:04:35.97#ibcon#end of sib2, iclass 34, count 2 2006.169.08:04:35.97#ibcon#*after write, iclass 34, count 2 2006.169.08:04:35.97#ibcon#*before return 0, iclass 34, count 2 2006.169.08:04:35.97#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:04:35.97#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:04:35.97#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.169.08:04:35.97#ibcon#ireg 7 cls_cnt 0 2006.169.08:04:35.97#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:04:36.09#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:04:36.09#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:04:36.09#ibcon#enter wrdev, iclass 34, count 0 2006.169.08:04:36.09#ibcon#first serial, iclass 34, count 0 2006.169.08:04:36.09#ibcon#enter sib2, iclass 34, count 0 2006.169.08:04:36.09#ibcon#flushed, iclass 34, count 0 2006.169.08:04:36.09#ibcon#about to write, iclass 34, count 0 2006.169.08:04:36.09#ibcon#wrote, iclass 34, count 0 2006.169.08:04:36.09#ibcon#about to read 3, iclass 34, count 0 2006.169.08:04:36.11#ibcon#read 3, iclass 34, count 0 2006.169.08:04:36.11#ibcon#about to read 4, iclass 34, count 0 2006.169.08:04:36.11#ibcon#read 4, iclass 34, count 0 2006.169.08:04:36.11#ibcon#about to read 5, iclass 34, count 0 2006.169.08:04:36.11#ibcon#read 5, iclass 34, count 0 2006.169.08:04:36.11#ibcon#about to read 6, iclass 34, count 0 2006.169.08:04:36.11#ibcon#read 6, iclass 34, count 0 2006.169.08:04:36.11#ibcon#end of sib2, iclass 34, count 0 2006.169.08:04:36.11#ibcon#*mode == 0, iclass 34, count 0 2006.169.08:04:36.11#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.169.08:04:36.11#ibcon#[25=USB\r\n] 2006.169.08:04:36.11#ibcon#*before write, iclass 34, count 0 2006.169.08:04:36.11#ibcon#enter sib2, iclass 34, count 0 2006.169.08:04:36.11#ibcon#flushed, iclass 34, count 0 2006.169.08:04:36.11#ibcon#about to write, iclass 34, count 0 2006.169.08:04:36.11#ibcon#wrote, iclass 34, count 0 2006.169.08:04:36.11#ibcon#about to read 3, iclass 34, count 0 2006.169.08:04:36.14#ibcon#read 3, iclass 34, count 0 2006.169.08:04:36.14#ibcon#about to read 4, iclass 34, count 0 2006.169.08:04:36.14#ibcon#read 4, iclass 34, count 0 2006.169.08:04:36.14#ibcon#about to read 5, iclass 34, count 0 2006.169.08:04:36.14#ibcon#read 5, iclass 34, count 0 2006.169.08:04:36.14#ibcon#about to read 6, iclass 34, count 0 2006.169.08:04:36.14#ibcon#read 6, iclass 34, count 0 2006.169.08:04:36.14#ibcon#end of sib2, iclass 34, count 0 2006.169.08:04:36.14#ibcon#*after write, iclass 34, count 0 2006.169.08:04:36.14#ibcon#*before return 0, iclass 34, count 0 2006.169.08:04:36.14#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:04:36.14#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:04:36.14#ibcon#about to clear, iclass 34 cls_cnt 0 2006.169.08:04:36.14#ibcon#cleared, iclass 34 cls_cnt 0 2006.169.08:04:36.14$vc4f8/valo=5,652.99 2006.169.08:04:36.14#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.169.08:04:36.14#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.169.08:04:36.14#ibcon#ireg 17 cls_cnt 0 2006.169.08:04:36.14#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:04:36.14#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:04:36.14#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:04:36.14#ibcon#enter wrdev, iclass 36, count 0 2006.169.08:04:36.14#ibcon#first serial, iclass 36, count 0 2006.169.08:04:36.14#ibcon#enter sib2, iclass 36, count 0 2006.169.08:04:36.14#ibcon#flushed, iclass 36, count 0 2006.169.08:04:36.14#ibcon#about to write, iclass 36, count 0 2006.169.08:04:36.14#ibcon#wrote, iclass 36, count 0 2006.169.08:04:36.14#ibcon#about to read 3, iclass 36, count 0 2006.169.08:04:36.16#ibcon#read 3, iclass 36, count 0 2006.169.08:04:36.16#ibcon#about to read 4, iclass 36, count 0 2006.169.08:04:36.16#ibcon#read 4, iclass 36, count 0 2006.169.08:04:36.16#ibcon#about to read 5, iclass 36, count 0 2006.169.08:04:36.16#ibcon#read 5, iclass 36, count 0 2006.169.08:04:36.16#ibcon#about to read 6, iclass 36, count 0 2006.169.08:04:36.16#ibcon#read 6, iclass 36, count 0 2006.169.08:04:36.16#ibcon#end of sib2, iclass 36, count 0 2006.169.08:04:36.16#ibcon#*mode == 0, iclass 36, count 0 2006.169.08:04:36.16#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.169.08:04:36.16#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.08:04:36.16#ibcon#*before write, iclass 36, count 0 2006.169.08:04:36.16#ibcon#enter sib2, iclass 36, count 0 2006.169.08:04:36.16#ibcon#flushed, iclass 36, count 0 2006.169.08:04:36.16#ibcon#about to write, iclass 36, count 0 2006.169.08:04:36.16#ibcon#wrote, iclass 36, count 0 2006.169.08:04:36.16#ibcon#about to read 3, iclass 36, count 0 2006.169.08:04:36.20#ibcon#read 3, iclass 36, count 0 2006.169.08:04:36.20#ibcon#about to read 4, iclass 36, count 0 2006.169.08:04:36.20#ibcon#read 4, iclass 36, count 0 2006.169.08:04:36.20#ibcon#about to read 5, iclass 36, count 0 2006.169.08:04:36.20#ibcon#read 5, iclass 36, count 0 2006.169.08:04:36.20#ibcon#about to read 6, iclass 36, count 0 2006.169.08:04:36.20#ibcon#read 6, iclass 36, count 0 2006.169.08:04:36.20#ibcon#end of sib2, iclass 36, count 0 2006.169.08:04:36.20#ibcon#*after write, iclass 36, count 0 2006.169.08:04:36.20#ibcon#*before return 0, iclass 36, count 0 2006.169.08:04:36.20#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:04:36.20#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:04:36.20#ibcon#about to clear, iclass 36 cls_cnt 0 2006.169.08:04:36.20#ibcon#cleared, iclass 36 cls_cnt 0 2006.169.08:04:36.20$vc4f8/va=5,7 2006.169.08:04:36.20#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.169.08:04:36.20#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.169.08:04:36.20#ibcon#ireg 11 cls_cnt 2 2006.169.08:04:36.20#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:04:36.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:04:36.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:04:36.26#ibcon#enter wrdev, iclass 38, count 2 2006.169.08:04:36.26#ibcon#first serial, iclass 38, count 2 2006.169.08:04:36.26#ibcon#enter sib2, iclass 38, count 2 2006.169.08:04:36.26#ibcon#flushed, iclass 38, count 2 2006.169.08:04:36.26#ibcon#about to write, iclass 38, count 2 2006.169.08:04:36.26#ibcon#wrote, iclass 38, count 2 2006.169.08:04:36.26#ibcon#about to read 3, iclass 38, count 2 2006.169.08:04:36.28#ibcon#read 3, iclass 38, count 2 2006.169.08:04:36.28#ibcon#about to read 4, iclass 38, count 2 2006.169.08:04:36.28#ibcon#read 4, iclass 38, count 2 2006.169.08:04:36.28#ibcon#about to read 5, iclass 38, count 2 2006.169.08:04:36.28#ibcon#read 5, iclass 38, count 2 2006.169.08:04:36.28#ibcon#about to read 6, iclass 38, count 2 2006.169.08:04:36.28#ibcon#read 6, iclass 38, count 2 2006.169.08:04:36.28#ibcon#end of sib2, iclass 38, count 2 2006.169.08:04:36.28#ibcon#*mode == 0, iclass 38, count 2 2006.169.08:04:36.28#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.169.08:04:36.28#ibcon#[25=AT05-07\r\n] 2006.169.08:04:36.28#ibcon#*before write, iclass 38, count 2 2006.169.08:04:36.28#ibcon#enter sib2, iclass 38, count 2 2006.169.08:04:36.28#ibcon#flushed, iclass 38, count 2 2006.169.08:04:36.28#ibcon#about to write, iclass 38, count 2 2006.169.08:04:36.28#ibcon#wrote, iclass 38, count 2 2006.169.08:04:36.28#ibcon#about to read 3, iclass 38, count 2 2006.169.08:04:36.31#ibcon#read 3, iclass 38, count 2 2006.169.08:04:36.31#ibcon#about to read 4, iclass 38, count 2 2006.169.08:04:36.31#ibcon#read 4, iclass 38, count 2 2006.169.08:04:36.31#ibcon#about to read 5, iclass 38, count 2 2006.169.08:04:36.31#ibcon#read 5, iclass 38, count 2 2006.169.08:04:36.31#ibcon#about to read 6, iclass 38, count 2 2006.169.08:04:36.31#ibcon#read 6, iclass 38, count 2 2006.169.08:04:36.31#ibcon#end of sib2, iclass 38, count 2 2006.169.08:04:36.31#ibcon#*after write, iclass 38, count 2 2006.169.08:04:36.31#ibcon#*before return 0, iclass 38, count 2 2006.169.08:04:36.31#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:04:36.31#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:04:36.31#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.169.08:04:36.31#ibcon#ireg 7 cls_cnt 0 2006.169.08:04:36.31#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:04:36.43#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:04:36.43#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:04:36.43#ibcon#enter wrdev, iclass 38, count 0 2006.169.08:04:36.43#ibcon#first serial, iclass 38, count 0 2006.169.08:04:36.43#ibcon#enter sib2, iclass 38, count 0 2006.169.08:04:36.43#ibcon#flushed, iclass 38, count 0 2006.169.08:04:36.43#ibcon#about to write, iclass 38, count 0 2006.169.08:04:36.43#ibcon#wrote, iclass 38, count 0 2006.169.08:04:36.43#ibcon#about to read 3, iclass 38, count 0 2006.169.08:04:36.45#ibcon#read 3, iclass 38, count 0 2006.169.08:04:36.45#ibcon#about to read 4, iclass 38, count 0 2006.169.08:04:36.45#ibcon#read 4, iclass 38, count 0 2006.169.08:04:36.45#ibcon#about to read 5, iclass 38, count 0 2006.169.08:04:36.45#ibcon#read 5, iclass 38, count 0 2006.169.08:04:36.45#ibcon#about to read 6, iclass 38, count 0 2006.169.08:04:36.45#ibcon#read 6, iclass 38, count 0 2006.169.08:04:36.45#ibcon#end of sib2, iclass 38, count 0 2006.169.08:04:36.45#ibcon#*mode == 0, iclass 38, count 0 2006.169.08:04:36.45#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.169.08:04:36.45#ibcon#[25=USB\r\n] 2006.169.08:04:36.45#ibcon#*before write, iclass 38, count 0 2006.169.08:04:36.45#ibcon#enter sib2, iclass 38, count 0 2006.169.08:04:36.45#ibcon#flushed, iclass 38, count 0 2006.169.08:04:36.45#ibcon#about to write, iclass 38, count 0 2006.169.08:04:36.45#ibcon#wrote, iclass 38, count 0 2006.169.08:04:36.45#ibcon#about to read 3, iclass 38, count 0 2006.169.08:04:36.48#ibcon#read 3, iclass 38, count 0 2006.169.08:04:36.48#ibcon#about to read 4, iclass 38, count 0 2006.169.08:04:36.48#ibcon#read 4, iclass 38, count 0 2006.169.08:04:36.48#ibcon#about to read 5, iclass 38, count 0 2006.169.08:04:36.48#ibcon#read 5, iclass 38, count 0 2006.169.08:04:36.48#ibcon#about to read 6, iclass 38, count 0 2006.169.08:04:36.48#ibcon#read 6, iclass 38, count 0 2006.169.08:04:36.48#ibcon#end of sib2, iclass 38, count 0 2006.169.08:04:36.48#ibcon#*after write, iclass 38, count 0 2006.169.08:04:36.48#ibcon#*before return 0, iclass 38, count 0 2006.169.08:04:36.48#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:04:36.48#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:04:36.48#ibcon#about to clear, iclass 38 cls_cnt 0 2006.169.08:04:36.48#ibcon#cleared, iclass 38 cls_cnt 0 2006.169.08:04:36.48$vc4f8/valo=6,772.99 2006.169.08:04:36.48#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.169.08:04:36.48#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.169.08:04:36.48#ibcon#ireg 17 cls_cnt 0 2006.169.08:04:36.48#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:04:36.48#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:04:36.48#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:04:36.48#ibcon#enter wrdev, iclass 40, count 0 2006.169.08:04:36.48#ibcon#first serial, iclass 40, count 0 2006.169.08:04:36.48#ibcon#enter sib2, iclass 40, count 0 2006.169.08:04:36.48#ibcon#flushed, iclass 40, count 0 2006.169.08:04:36.48#ibcon#about to write, iclass 40, count 0 2006.169.08:04:36.48#ibcon#wrote, iclass 40, count 0 2006.169.08:04:36.48#ibcon#about to read 3, iclass 40, count 0 2006.169.08:04:36.50#ibcon#read 3, iclass 40, count 0 2006.169.08:04:36.50#ibcon#about to read 4, iclass 40, count 0 2006.169.08:04:36.50#ibcon#read 4, iclass 40, count 0 2006.169.08:04:36.50#ibcon#about to read 5, iclass 40, count 0 2006.169.08:04:36.50#ibcon#read 5, iclass 40, count 0 2006.169.08:04:36.50#ibcon#about to read 6, iclass 40, count 0 2006.169.08:04:36.50#ibcon#read 6, iclass 40, count 0 2006.169.08:04:36.50#ibcon#end of sib2, iclass 40, count 0 2006.169.08:04:36.50#ibcon#*mode == 0, iclass 40, count 0 2006.169.08:04:36.50#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.169.08:04:36.50#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.08:04:36.50#ibcon#*before write, iclass 40, count 0 2006.169.08:04:36.50#ibcon#enter sib2, iclass 40, count 0 2006.169.08:04:36.50#ibcon#flushed, iclass 40, count 0 2006.169.08:04:36.50#ibcon#about to write, iclass 40, count 0 2006.169.08:04:36.50#ibcon#wrote, iclass 40, count 0 2006.169.08:04:36.50#ibcon#about to read 3, iclass 40, count 0 2006.169.08:04:36.54#ibcon#read 3, iclass 40, count 0 2006.169.08:04:36.54#ibcon#about to read 4, iclass 40, count 0 2006.169.08:04:36.54#ibcon#read 4, iclass 40, count 0 2006.169.08:04:36.54#ibcon#about to read 5, iclass 40, count 0 2006.169.08:04:36.54#ibcon#read 5, iclass 40, count 0 2006.169.08:04:36.54#ibcon#about to read 6, iclass 40, count 0 2006.169.08:04:36.54#ibcon#read 6, iclass 40, count 0 2006.169.08:04:36.54#ibcon#end of sib2, iclass 40, count 0 2006.169.08:04:36.54#ibcon#*after write, iclass 40, count 0 2006.169.08:04:36.54#ibcon#*before return 0, iclass 40, count 0 2006.169.08:04:36.54#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:04:36.54#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:04:36.54#ibcon#about to clear, iclass 40 cls_cnt 0 2006.169.08:04:36.54#ibcon#cleared, iclass 40 cls_cnt 0 2006.169.08:04:36.54$vc4f8/va=6,6 2006.169.08:04:36.54#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.169.08:04:36.54#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.169.08:04:36.54#ibcon#ireg 11 cls_cnt 2 2006.169.08:04:36.54#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:04:36.60#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:04:36.60#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:04:36.60#ibcon#enter wrdev, iclass 4, count 2 2006.169.08:04:36.60#ibcon#first serial, iclass 4, count 2 2006.169.08:04:36.60#ibcon#enter sib2, iclass 4, count 2 2006.169.08:04:36.60#ibcon#flushed, iclass 4, count 2 2006.169.08:04:36.60#ibcon#about to write, iclass 4, count 2 2006.169.08:04:36.60#ibcon#wrote, iclass 4, count 2 2006.169.08:04:36.60#ibcon#about to read 3, iclass 4, count 2 2006.169.08:04:36.62#ibcon#read 3, iclass 4, count 2 2006.169.08:04:36.62#ibcon#about to read 4, iclass 4, count 2 2006.169.08:04:36.62#ibcon#read 4, iclass 4, count 2 2006.169.08:04:36.62#ibcon#about to read 5, iclass 4, count 2 2006.169.08:04:36.62#ibcon#read 5, iclass 4, count 2 2006.169.08:04:36.62#ibcon#about to read 6, iclass 4, count 2 2006.169.08:04:36.62#ibcon#read 6, iclass 4, count 2 2006.169.08:04:36.62#ibcon#end of sib2, iclass 4, count 2 2006.169.08:04:36.62#ibcon#*mode == 0, iclass 4, count 2 2006.169.08:04:36.62#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.169.08:04:36.62#ibcon#[25=AT06-06\r\n] 2006.169.08:04:36.62#ibcon#*before write, iclass 4, count 2 2006.169.08:04:36.62#ibcon#enter sib2, iclass 4, count 2 2006.169.08:04:36.62#ibcon#flushed, iclass 4, count 2 2006.169.08:04:36.62#ibcon#about to write, iclass 4, count 2 2006.169.08:04:36.62#ibcon#wrote, iclass 4, count 2 2006.169.08:04:36.62#ibcon#about to read 3, iclass 4, count 2 2006.169.08:04:36.65#ibcon#read 3, iclass 4, count 2 2006.169.08:04:36.65#ibcon#about to read 4, iclass 4, count 2 2006.169.08:04:36.65#ibcon#read 4, iclass 4, count 2 2006.169.08:04:36.65#ibcon#about to read 5, iclass 4, count 2 2006.169.08:04:36.65#ibcon#read 5, iclass 4, count 2 2006.169.08:04:36.65#ibcon#about to read 6, iclass 4, count 2 2006.169.08:04:36.65#ibcon#read 6, iclass 4, count 2 2006.169.08:04:36.65#ibcon#end of sib2, iclass 4, count 2 2006.169.08:04:36.65#ibcon#*after write, iclass 4, count 2 2006.169.08:04:36.65#ibcon#*before return 0, iclass 4, count 2 2006.169.08:04:36.65#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:04:36.65#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:04:36.65#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.169.08:04:36.65#ibcon#ireg 7 cls_cnt 0 2006.169.08:04:36.65#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:04:36.77#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:04:36.77#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:04:36.77#ibcon#enter wrdev, iclass 4, count 0 2006.169.08:04:36.77#ibcon#first serial, iclass 4, count 0 2006.169.08:04:36.77#ibcon#enter sib2, iclass 4, count 0 2006.169.08:04:36.77#ibcon#flushed, iclass 4, count 0 2006.169.08:04:36.77#ibcon#about to write, iclass 4, count 0 2006.169.08:04:36.77#ibcon#wrote, iclass 4, count 0 2006.169.08:04:36.77#ibcon#about to read 3, iclass 4, count 0 2006.169.08:04:36.79#ibcon#read 3, iclass 4, count 0 2006.169.08:04:36.79#ibcon#about to read 4, iclass 4, count 0 2006.169.08:04:36.79#ibcon#read 4, iclass 4, count 0 2006.169.08:04:36.79#ibcon#about to read 5, iclass 4, count 0 2006.169.08:04:36.79#ibcon#read 5, iclass 4, count 0 2006.169.08:04:36.79#ibcon#about to read 6, iclass 4, count 0 2006.169.08:04:36.79#ibcon#read 6, iclass 4, count 0 2006.169.08:04:36.79#ibcon#end of sib2, iclass 4, count 0 2006.169.08:04:36.79#ibcon#*mode == 0, iclass 4, count 0 2006.169.08:04:36.79#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.169.08:04:36.79#ibcon#[25=USB\r\n] 2006.169.08:04:36.79#ibcon#*before write, iclass 4, count 0 2006.169.08:04:36.79#ibcon#enter sib2, iclass 4, count 0 2006.169.08:04:36.79#ibcon#flushed, iclass 4, count 0 2006.169.08:04:36.79#ibcon#about to write, iclass 4, count 0 2006.169.08:04:36.79#ibcon#wrote, iclass 4, count 0 2006.169.08:04:36.79#ibcon#about to read 3, iclass 4, count 0 2006.169.08:04:36.82#ibcon#read 3, iclass 4, count 0 2006.169.08:04:36.82#ibcon#about to read 4, iclass 4, count 0 2006.169.08:04:36.82#ibcon#read 4, iclass 4, count 0 2006.169.08:04:36.82#ibcon#about to read 5, iclass 4, count 0 2006.169.08:04:36.82#ibcon#read 5, iclass 4, count 0 2006.169.08:04:36.82#ibcon#about to read 6, iclass 4, count 0 2006.169.08:04:36.82#ibcon#read 6, iclass 4, count 0 2006.169.08:04:36.82#ibcon#end of sib2, iclass 4, count 0 2006.169.08:04:36.82#ibcon#*after write, iclass 4, count 0 2006.169.08:04:36.82#ibcon#*before return 0, iclass 4, count 0 2006.169.08:04:36.82#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:04:36.82#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:04:36.82#ibcon#about to clear, iclass 4 cls_cnt 0 2006.169.08:04:36.82#ibcon#cleared, iclass 4 cls_cnt 0 2006.169.08:04:36.82$vc4f8/valo=7,832.99 2006.169.08:04:36.82#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.169.08:04:36.82#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.169.08:04:36.82#ibcon#ireg 17 cls_cnt 0 2006.169.08:04:36.82#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:04:36.82#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:04:36.82#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:04:36.82#ibcon#enter wrdev, iclass 6, count 0 2006.169.08:04:36.82#ibcon#first serial, iclass 6, count 0 2006.169.08:04:36.82#ibcon#enter sib2, iclass 6, count 0 2006.169.08:04:36.82#ibcon#flushed, iclass 6, count 0 2006.169.08:04:36.82#ibcon#about to write, iclass 6, count 0 2006.169.08:04:36.82#ibcon#wrote, iclass 6, count 0 2006.169.08:04:36.82#ibcon#about to read 3, iclass 6, count 0 2006.169.08:04:36.84#ibcon#read 3, iclass 6, count 0 2006.169.08:04:36.84#ibcon#about to read 4, iclass 6, count 0 2006.169.08:04:36.84#ibcon#read 4, iclass 6, count 0 2006.169.08:04:36.84#ibcon#about to read 5, iclass 6, count 0 2006.169.08:04:36.84#ibcon#read 5, iclass 6, count 0 2006.169.08:04:36.84#ibcon#about to read 6, iclass 6, count 0 2006.169.08:04:36.84#ibcon#read 6, iclass 6, count 0 2006.169.08:04:36.84#ibcon#end of sib2, iclass 6, count 0 2006.169.08:04:36.84#ibcon#*mode == 0, iclass 6, count 0 2006.169.08:04:36.84#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.169.08:04:36.84#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.08:04:36.84#ibcon#*before write, iclass 6, count 0 2006.169.08:04:36.84#ibcon#enter sib2, iclass 6, count 0 2006.169.08:04:36.84#ibcon#flushed, iclass 6, count 0 2006.169.08:04:36.84#ibcon#about to write, iclass 6, count 0 2006.169.08:04:36.84#ibcon#wrote, iclass 6, count 0 2006.169.08:04:36.84#ibcon#about to read 3, iclass 6, count 0 2006.169.08:04:36.88#ibcon#read 3, iclass 6, count 0 2006.169.08:04:36.88#ibcon#about to read 4, iclass 6, count 0 2006.169.08:04:36.88#ibcon#read 4, iclass 6, count 0 2006.169.08:04:36.88#ibcon#about to read 5, iclass 6, count 0 2006.169.08:04:36.88#ibcon#read 5, iclass 6, count 0 2006.169.08:04:36.88#ibcon#about to read 6, iclass 6, count 0 2006.169.08:04:36.88#ibcon#read 6, iclass 6, count 0 2006.169.08:04:36.88#ibcon#end of sib2, iclass 6, count 0 2006.169.08:04:36.88#ibcon#*after write, iclass 6, count 0 2006.169.08:04:36.88#ibcon#*before return 0, iclass 6, count 0 2006.169.08:04:36.88#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:04:36.88#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:04:36.88#ibcon#about to clear, iclass 6 cls_cnt 0 2006.169.08:04:36.88#ibcon#cleared, iclass 6 cls_cnt 0 2006.169.08:04:36.88$vc4f8/va=7,6 2006.169.08:04:36.88#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.169.08:04:36.88#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.169.08:04:36.88#ibcon#ireg 11 cls_cnt 2 2006.169.08:04:36.88#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:04:36.94#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:04:36.94#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:04:36.94#ibcon#enter wrdev, iclass 10, count 2 2006.169.08:04:36.94#ibcon#first serial, iclass 10, count 2 2006.169.08:04:36.94#ibcon#enter sib2, iclass 10, count 2 2006.169.08:04:36.94#ibcon#flushed, iclass 10, count 2 2006.169.08:04:36.94#ibcon#about to write, iclass 10, count 2 2006.169.08:04:36.94#ibcon#wrote, iclass 10, count 2 2006.169.08:04:36.94#ibcon#about to read 3, iclass 10, count 2 2006.169.08:04:36.96#ibcon#read 3, iclass 10, count 2 2006.169.08:04:36.96#ibcon#about to read 4, iclass 10, count 2 2006.169.08:04:36.96#ibcon#read 4, iclass 10, count 2 2006.169.08:04:36.96#ibcon#about to read 5, iclass 10, count 2 2006.169.08:04:36.96#ibcon#read 5, iclass 10, count 2 2006.169.08:04:36.96#ibcon#about to read 6, iclass 10, count 2 2006.169.08:04:36.96#ibcon#read 6, iclass 10, count 2 2006.169.08:04:36.96#ibcon#end of sib2, iclass 10, count 2 2006.169.08:04:36.96#ibcon#*mode == 0, iclass 10, count 2 2006.169.08:04:36.96#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.169.08:04:36.96#ibcon#[25=AT07-06\r\n] 2006.169.08:04:36.96#ibcon#*before write, iclass 10, count 2 2006.169.08:04:36.96#ibcon#enter sib2, iclass 10, count 2 2006.169.08:04:36.96#ibcon#flushed, iclass 10, count 2 2006.169.08:04:36.96#ibcon#about to write, iclass 10, count 2 2006.169.08:04:36.96#ibcon#wrote, iclass 10, count 2 2006.169.08:04:36.96#ibcon#about to read 3, iclass 10, count 2 2006.169.08:04:36.99#ibcon#read 3, iclass 10, count 2 2006.169.08:04:36.99#ibcon#about to read 4, iclass 10, count 2 2006.169.08:04:36.99#ibcon#read 4, iclass 10, count 2 2006.169.08:04:36.99#ibcon#about to read 5, iclass 10, count 2 2006.169.08:04:36.99#ibcon#read 5, iclass 10, count 2 2006.169.08:04:36.99#ibcon#about to read 6, iclass 10, count 2 2006.169.08:04:36.99#ibcon#read 6, iclass 10, count 2 2006.169.08:04:36.99#ibcon#end of sib2, iclass 10, count 2 2006.169.08:04:36.99#ibcon#*after write, iclass 10, count 2 2006.169.08:04:36.99#ibcon#*before return 0, iclass 10, count 2 2006.169.08:04:36.99#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:04:36.99#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:04:36.99#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.169.08:04:36.99#ibcon#ireg 7 cls_cnt 0 2006.169.08:04:36.99#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:04:37.11#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:04:37.11#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:04:37.11#ibcon#enter wrdev, iclass 10, count 0 2006.169.08:04:37.11#ibcon#first serial, iclass 10, count 0 2006.169.08:04:37.11#ibcon#enter sib2, iclass 10, count 0 2006.169.08:04:37.11#ibcon#flushed, iclass 10, count 0 2006.169.08:04:37.11#ibcon#about to write, iclass 10, count 0 2006.169.08:04:37.11#ibcon#wrote, iclass 10, count 0 2006.169.08:04:37.11#ibcon#about to read 3, iclass 10, count 0 2006.169.08:04:37.13#ibcon#read 3, iclass 10, count 0 2006.169.08:04:37.13#ibcon#about to read 4, iclass 10, count 0 2006.169.08:04:37.13#ibcon#read 4, iclass 10, count 0 2006.169.08:04:37.13#ibcon#about to read 5, iclass 10, count 0 2006.169.08:04:37.13#ibcon#read 5, iclass 10, count 0 2006.169.08:04:37.13#ibcon#about to read 6, iclass 10, count 0 2006.169.08:04:37.13#ibcon#read 6, iclass 10, count 0 2006.169.08:04:37.13#ibcon#end of sib2, iclass 10, count 0 2006.169.08:04:37.13#ibcon#*mode == 0, iclass 10, count 0 2006.169.08:04:37.13#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.169.08:04:37.13#ibcon#[25=USB\r\n] 2006.169.08:04:37.13#ibcon#*before write, iclass 10, count 0 2006.169.08:04:37.13#ibcon#enter sib2, iclass 10, count 0 2006.169.08:04:37.13#ibcon#flushed, iclass 10, count 0 2006.169.08:04:37.13#ibcon#about to write, iclass 10, count 0 2006.169.08:04:37.13#ibcon#wrote, iclass 10, count 0 2006.169.08:04:37.13#ibcon#about to read 3, iclass 10, count 0 2006.169.08:04:37.16#ibcon#read 3, iclass 10, count 0 2006.169.08:04:37.16#ibcon#about to read 4, iclass 10, count 0 2006.169.08:04:37.16#ibcon#read 4, iclass 10, count 0 2006.169.08:04:37.16#ibcon#about to read 5, iclass 10, count 0 2006.169.08:04:37.16#ibcon#read 5, iclass 10, count 0 2006.169.08:04:37.16#ibcon#about to read 6, iclass 10, count 0 2006.169.08:04:37.16#ibcon#read 6, iclass 10, count 0 2006.169.08:04:37.16#ibcon#end of sib2, iclass 10, count 0 2006.169.08:04:37.16#ibcon#*after write, iclass 10, count 0 2006.169.08:04:37.16#ibcon#*before return 0, iclass 10, count 0 2006.169.08:04:37.16#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:04:37.16#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:04:37.16#ibcon#about to clear, iclass 10 cls_cnt 0 2006.169.08:04:37.16#ibcon#cleared, iclass 10 cls_cnt 0 2006.169.08:04:37.16$vc4f8/valo=8,852.99 2006.169.08:04:37.16#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.169.08:04:37.16#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.169.08:04:37.16#ibcon#ireg 17 cls_cnt 0 2006.169.08:04:37.16#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:04:37.16#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:04:37.16#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:04:37.16#ibcon#enter wrdev, iclass 12, count 0 2006.169.08:04:37.16#ibcon#first serial, iclass 12, count 0 2006.169.08:04:37.16#ibcon#enter sib2, iclass 12, count 0 2006.169.08:04:37.16#ibcon#flushed, iclass 12, count 0 2006.169.08:04:37.16#ibcon#about to write, iclass 12, count 0 2006.169.08:04:37.16#ibcon#wrote, iclass 12, count 0 2006.169.08:04:37.16#ibcon#about to read 3, iclass 12, count 0 2006.169.08:04:37.18#ibcon#read 3, iclass 12, count 0 2006.169.08:04:37.18#ibcon#about to read 4, iclass 12, count 0 2006.169.08:04:37.18#ibcon#read 4, iclass 12, count 0 2006.169.08:04:37.18#ibcon#about to read 5, iclass 12, count 0 2006.169.08:04:37.18#ibcon#read 5, iclass 12, count 0 2006.169.08:04:37.18#ibcon#about to read 6, iclass 12, count 0 2006.169.08:04:37.18#ibcon#read 6, iclass 12, count 0 2006.169.08:04:37.18#ibcon#end of sib2, iclass 12, count 0 2006.169.08:04:37.18#ibcon#*mode == 0, iclass 12, count 0 2006.169.08:04:37.18#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.169.08:04:37.18#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.08:04:37.18#ibcon#*before write, iclass 12, count 0 2006.169.08:04:37.18#ibcon#enter sib2, iclass 12, count 0 2006.169.08:04:37.18#ibcon#flushed, iclass 12, count 0 2006.169.08:04:37.18#ibcon#about to write, iclass 12, count 0 2006.169.08:04:37.18#ibcon#wrote, iclass 12, count 0 2006.169.08:04:37.18#ibcon#about to read 3, iclass 12, count 0 2006.169.08:04:37.22#ibcon#read 3, iclass 12, count 0 2006.169.08:04:37.22#ibcon#about to read 4, iclass 12, count 0 2006.169.08:04:37.22#ibcon#read 4, iclass 12, count 0 2006.169.08:04:37.22#ibcon#about to read 5, iclass 12, count 0 2006.169.08:04:37.22#ibcon#read 5, iclass 12, count 0 2006.169.08:04:37.22#ibcon#about to read 6, iclass 12, count 0 2006.169.08:04:37.22#ibcon#read 6, iclass 12, count 0 2006.169.08:04:37.22#ibcon#end of sib2, iclass 12, count 0 2006.169.08:04:37.22#ibcon#*after write, iclass 12, count 0 2006.169.08:04:37.22#ibcon#*before return 0, iclass 12, count 0 2006.169.08:04:37.22#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:04:37.22#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:04:37.22#ibcon#about to clear, iclass 12 cls_cnt 0 2006.169.08:04:37.22#ibcon#cleared, iclass 12 cls_cnt 0 2006.169.08:04:37.22$vc4f8/va=8,7 2006.169.08:04:37.22#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.169.08:04:37.22#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.169.08:04:37.22#ibcon#ireg 11 cls_cnt 2 2006.169.08:04:37.22#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.169.08:04:37.28#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.169.08:04:37.28#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.169.08:04:37.28#ibcon#enter wrdev, iclass 14, count 2 2006.169.08:04:37.28#ibcon#first serial, iclass 14, count 2 2006.169.08:04:37.28#ibcon#enter sib2, iclass 14, count 2 2006.169.08:04:37.28#ibcon#flushed, iclass 14, count 2 2006.169.08:04:37.28#ibcon#about to write, iclass 14, count 2 2006.169.08:04:37.28#ibcon#wrote, iclass 14, count 2 2006.169.08:04:37.28#ibcon#about to read 3, iclass 14, count 2 2006.169.08:04:37.30#ibcon#read 3, iclass 14, count 2 2006.169.08:04:37.30#ibcon#about to read 4, iclass 14, count 2 2006.169.08:04:37.30#ibcon#read 4, iclass 14, count 2 2006.169.08:04:37.30#ibcon#about to read 5, iclass 14, count 2 2006.169.08:04:37.30#ibcon#read 5, iclass 14, count 2 2006.169.08:04:37.30#ibcon#about to read 6, iclass 14, count 2 2006.169.08:04:37.30#ibcon#read 6, iclass 14, count 2 2006.169.08:04:37.30#ibcon#end of sib2, iclass 14, count 2 2006.169.08:04:37.30#ibcon#*mode == 0, iclass 14, count 2 2006.169.08:04:37.30#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.169.08:04:37.30#ibcon#[25=AT08-07\r\n] 2006.169.08:04:37.30#ibcon#*before write, iclass 14, count 2 2006.169.08:04:37.30#ibcon#enter sib2, iclass 14, count 2 2006.169.08:04:37.30#ibcon#flushed, iclass 14, count 2 2006.169.08:04:37.30#ibcon#about to write, iclass 14, count 2 2006.169.08:04:37.30#ibcon#wrote, iclass 14, count 2 2006.169.08:04:37.30#ibcon#about to read 3, iclass 14, count 2 2006.169.08:04:37.33#ibcon#read 3, iclass 14, count 2 2006.169.08:04:37.33#ibcon#about to read 4, iclass 14, count 2 2006.169.08:04:37.33#ibcon#read 4, iclass 14, count 2 2006.169.08:04:37.33#ibcon#about to read 5, iclass 14, count 2 2006.169.08:04:37.33#ibcon#read 5, iclass 14, count 2 2006.169.08:04:37.33#ibcon#about to read 6, iclass 14, count 2 2006.169.08:04:37.33#ibcon#read 6, iclass 14, count 2 2006.169.08:04:37.33#ibcon#end of sib2, iclass 14, count 2 2006.169.08:04:37.33#ibcon#*after write, iclass 14, count 2 2006.169.08:04:37.33#ibcon#*before return 0, iclass 14, count 2 2006.169.08:04:37.33#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.169.08:04:37.33#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.169.08:04:37.33#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.169.08:04:37.33#ibcon#ireg 7 cls_cnt 0 2006.169.08:04:37.33#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.169.08:04:37.45#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.169.08:04:37.45#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.169.08:04:37.45#ibcon#enter wrdev, iclass 14, count 0 2006.169.08:04:37.45#ibcon#first serial, iclass 14, count 0 2006.169.08:04:37.45#ibcon#enter sib2, iclass 14, count 0 2006.169.08:04:37.45#ibcon#flushed, iclass 14, count 0 2006.169.08:04:37.45#ibcon#about to write, iclass 14, count 0 2006.169.08:04:37.45#ibcon#wrote, iclass 14, count 0 2006.169.08:04:37.45#ibcon#about to read 3, iclass 14, count 0 2006.169.08:04:37.47#ibcon#read 3, iclass 14, count 0 2006.169.08:04:37.47#ibcon#about to read 4, iclass 14, count 0 2006.169.08:04:37.47#ibcon#read 4, iclass 14, count 0 2006.169.08:04:37.47#ibcon#about to read 5, iclass 14, count 0 2006.169.08:04:37.47#ibcon#read 5, iclass 14, count 0 2006.169.08:04:37.47#ibcon#about to read 6, iclass 14, count 0 2006.169.08:04:37.47#ibcon#read 6, iclass 14, count 0 2006.169.08:04:37.47#ibcon#end of sib2, iclass 14, count 0 2006.169.08:04:37.47#ibcon#*mode == 0, iclass 14, count 0 2006.169.08:04:37.47#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.169.08:04:37.47#ibcon#[25=USB\r\n] 2006.169.08:04:37.47#ibcon#*before write, iclass 14, count 0 2006.169.08:04:37.47#ibcon#enter sib2, iclass 14, count 0 2006.169.08:04:37.47#ibcon#flushed, iclass 14, count 0 2006.169.08:04:37.47#ibcon#about to write, iclass 14, count 0 2006.169.08:04:37.47#ibcon#wrote, iclass 14, count 0 2006.169.08:04:37.47#ibcon#about to read 3, iclass 14, count 0 2006.169.08:04:37.50#ibcon#read 3, iclass 14, count 0 2006.169.08:04:37.50#ibcon#about to read 4, iclass 14, count 0 2006.169.08:04:37.50#ibcon#read 4, iclass 14, count 0 2006.169.08:04:37.50#ibcon#about to read 5, iclass 14, count 0 2006.169.08:04:37.50#ibcon#read 5, iclass 14, count 0 2006.169.08:04:37.50#ibcon#about to read 6, iclass 14, count 0 2006.169.08:04:37.50#ibcon#read 6, iclass 14, count 0 2006.169.08:04:37.50#ibcon#end of sib2, iclass 14, count 0 2006.169.08:04:37.50#ibcon#*after write, iclass 14, count 0 2006.169.08:04:37.50#ibcon#*before return 0, iclass 14, count 0 2006.169.08:04:37.50#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.169.08:04:37.50#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.169.08:04:37.50#ibcon#about to clear, iclass 14 cls_cnt 0 2006.169.08:04:37.50#ibcon#cleared, iclass 14 cls_cnt 0 2006.169.08:04:37.50$vc4f8/vblo=1,632.99 2006.169.08:04:37.50#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.169.08:04:37.50#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.169.08:04:37.50#ibcon#ireg 17 cls_cnt 0 2006.169.08:04:37.50#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:04:37.50#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:04:37.50#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:04:37.50#ibcon#enter wrdev, iclass 16, count 0 2006.169.08:04:37.50#ibcon#first serial, iclass 16, count 0 2006.169.08:04:37.50#ibcon#enter sib2, iclass 16, count 0 2006.169.08:04:37.50#ibcon#flushed, iclass 16, count 0 2006.169.08:04:37.50#ibcon#about to write, iclass 16, count 0 2006.169.08:04:37.50#ibcon#wrote, iclass 16, count 0 2006.169.08:04:37.50#ibcon#about to read 3, iclass 16, count 0 2006.169.08:04:37.52#ibcon#read 3, iclass 16, count 0 2006.169.08:04:37.52#ibcon#about to read 4, iclass 16, count 0 2006.169.08:04:37.52#ibcon#read 4, iclass 16, count 0 2006.169.08:04:37.52#ibcon#about to read 5, iclass 16, count 0 2006.169.08:04:37.52#ibcon#read 5, iclass 16, count 0 2006.169.08:04:37.52#ibcon#about to read 6, iclass 16, count 0 2006.169.08:04:37.52#ibcon#read 6, iclass 16, count 0 2006.169.08:04:37.52#ibcon#end of sib2, iclass 16, count 0 2006.169.08:04:37.52#ibcon#*mode == 0, iclass 16, count 0 2006.169.08:04:37.52#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.169.08:04:37.52#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.08:04:37.52#ibcon#*before write, iclass 16, count 0 2006.169.08:04:37.52#ibcon#enter sib2, iclass 16, count 0 2006.169.08:04:37.52#ibcon#flushed, iclass 16, count 0 2006.169.08:04:37.52#ibcon#about to write, iclass 16, count 0 2006.169.08:04:37.52#ibcon#wrote, iclass 16, count 0 2006.169.08:04:37.52#ibcon#about to read 3, iclass 16, count 0 2006.169.08:04:37.56#ibcon#read 3, iclass 16, count 0 2006.169.08:04:37.56#ibcon#about to read 4, iclass 16, count 0 2006.169.08:04:37.56#ibcon#read 4, iclass 16, count 0 2006.169.08:04:37.56#ibcon#about to read 5, iclass 16, count 0 2006.169.08:04:37.56#ibcon#read 5, iclass 16, count 0 2006.169.08:04:37.56#ibcon#about to read 6, iclass 16, count 0 2006.169.08:04:37.56#ibcon#read 6, iclass 16, count 0 2006.169.08:04:37.56#ibcon#end of sib2, iclass 16, count 0 2006.169.08:04:37.56#ibcon#*after write, iclass 16, count 0 2006.169.08:04:37.56#ibcon#*before return 0, iclass 16, count 0 2006.169.08:04:37.56#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:04:37.56#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:04:37.56#ibcon#about to clear, iclass 16 cls_cnt 0 2006.169.08:04:37.56#ibcon#cleared, iclass 16 cls_cnt 0 2006.169.08:04:37.56$vc4f8/vb=1,4 2006.169.08:04:37.56#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.169.08:04:37.56#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.169.08:04:37.56#ibcon#ireg 11 cls_cnt 2 2006.169.08:04:37.56#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.169.08:04:37.56#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.169.08:04:37.56#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.169.08:04:37.56#ibcon#enter wrdev, iclass 18, count 2 2006.169.08:04:37.56#ibcon#first serial, iclass 18, count 2 2006.169.08:04:37.56#ibcon#enter sib2, iclass 18, count 2 2006.169.08:04:37.56#ibcon#flushed, iclass 18, count 2 2006.169.08:04:37.56#ibcon#about to write, iclass 18, count 2 2006.169.08:04:37.56#ibcon#wrote, iclass 18, count 2 2006.169.08:04:37.56#ibcon#about to read 3, iclass 18, count 2 2006.169.08:04:37.58#ibcon#read 3, iclass 18, count 2 2006.169.08:04:37.58#ibcon#about to read 4, iclass 18, count 2 2006.169.08:04:37.58#ibcon#read 4, iclass 18, count 2 2006.169.08:04:37.58#ibcon#about to read 5, iclass 18, count 2 2006.169.08:04:37.58#ibcon#read 5, iclass 18, count 2 2006.169.08:04:37.58#ibcon#about to read 6, iclass 18, count 2 2006.169.08:04:37.58#ibcon#read 6, iclass 18, count 2 2006.169.08:04:37.58#ibcon#end of sib2, iclass 18, count 2 2006.169.08:04:37.58#ibcon#*mode == 0, iclass 18, count 2 2006.169.08:04:37.58#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.169.08:04:37.58#ibcon#[27=AT01-04\r\n] 2006.169.08:04:37.58#ibcon#*before write, iclass 18, count 2 2006.169.08:04:37.58#ibcon#enter sib2, iclass 18, count 2 2006.169.08:04:37.58#ibcon#flushed, iclass 18, count 2 2006.169.08:04:37.58#ibcon#about to write, iclass 18, count 2 2006.169.08:04:37.58#ibcon#wrote, iclass 18, count 2 2006.169.08:04:37.58#ibcon#about to read 3, iclass 18, count 2 2006.169.08:04:37.61#ibcon#read 3, iclass 18, count 2 2006.169.08:04:37.61#ibcon#about to read 4, iclass 18, count 2 2006.169.08:04:37.61#ibcon#read 4, iclass 18, count 2 2006.169.08:04:37.61#ibcon#about to read 5, iclass 18, count 2 2006.169.08:04:37.61#ibcon#read 5, iclass 18, count 2 2006.169.08:04:37.61#ibcon#about to read 6, iclass 18, count 2 2006.169.08:04:37.61#ibcon#read 6, iclass 18, count 2 2006.169.08:04:37.61#ibcon#end of sib2, iclass 18, count 2 2006.169.08:04:37.61#ibcon#*after write, iclass 18, count 2 2006.169.08:04:37.61#ibcon#*before return 0, iclass 18, count 2 2006.169.08:04:37.61#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.169.08:04:37.61#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.169.08:04:37.61#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.169.08:04:37.61#ibcon#ireg 7 cls_cnt 0 2006.169.08:04:37.61#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.169.08:04:37.73#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.169.08:04:37.73#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.169.08:04:37.73#ibcon#enter wrdev, iclass 18, count 0 2006.169.08:04:37.73#ibcon#first serial, iclass 18, count 0 2006.169.08:04:37.73#ibcon#enter sib2, iclass 18, count 0 2006.169.08:04:37.73#ibcon#flushed, iclass 18, count 0 2006.169.08:04:37.73#ibcon#about to write, iclass 18, count 0 2006.169.08:04:37.73#ibcon#wrote, iclass 18, count 0 2006.169.08:04:37.73#ibcon#about to read 3, iclass 18, count 0 2006.169.08:04:37.75#ibcon#read 3, iclass 18, count 0 2006.169.08:04:37.75#ibcon#about to read 4, iclass 18, count 0 2006.169.08:04:37.75#ibcon#read 4, iclass 18, count 0 2006.169.08:04:37.75#ibcon#about to read 5, iclass 18, count 0 2006.169.08:04:37.75#ibcon#read 5, iclass 18, count 0 2006.169.08:04:37.75#ibcon#about to read 6, iclass 18, count 0 2006.169.08:04:37.75#ibcon#read 6, iclass 18, count 0 2006.169.08:04:37.75#ibcon#end of sib2, iclass 18, count 0 2006.169.08:04:37.75#ibcon#*mode == 0, iclass 18, count 0 2006.169.08:04:37.75#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.169.08:04:37.75#ibcon#[27=USB\r\n] 2006.169.08:04:37.75#ibcon#*before write, iclass 18, count 0 2006.169.08:04:37.75#ibcon#enter sib2, iclass 18, count 0 2006.169.08:04:37.75#ibcon#flushed, iclass 18, count 0 2006.169.08:04:37.75#ibcon#about to write, iclass 18, count 0 2006.169.08:04:37.75#ibcon#wrote, iclass 18, count 0 2006.169.08:04:37.75#ibcon#about to read 3, iclass 18, count 0 2006.169.08:04:37.78#ibcon#read 3, iclass 18, count 0 2006.169.08:04:37.78#ibcon#about to read 4, iclass 18, count 0 2006.169.08:04:37.78#ibcon#read 4, iclass 18, count 0 2006.169.08:04:37.78#ibcon#about to read 5, iclass 18, count 0 2006.169.08:04:37.78#ibcon#read 5, iclass 18, count 0 2006.169.08:04:37.78#ibcon#about to read 6, iclass 18, count 0 2006.169.08:04:37.78#ibcon#read 6, iclass 18, count 0 2006.169.08:04:37.78#ibcon#end of sib2, iclass 18, count 0 2006.169.08:04:37.78#ibcon#*after write, iclass 18, count 0 2006.169.08:04:37.78#ibcon#*before return 0, iclass 18, count 0 2006.169.08:04:37.78#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.169.08:04:37.78#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.169.08:04:37.78#ibcon#about to clear, iclass 18 cls_cnt 0 2006.169.08:04:37.78#ibcon#cleared, iclass 18 cls_cnt 0 2006.169.08:04:37.78$vc4f8/vblo=2,640.99 2006.169.08:04:37.78#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.169.08:04:37.78#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.169.08:04:37.78#ibcon#ireg 17 cls_cnt 0 2006.169.08:04:37.78#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:04:37.78#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:04:37.78#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:04:37.78#ibcon#enter wrdev, iclass 20, count 0 2006.169.08:04:37.78#ibcon#first serial, iclass 20, count 0 2006.169.08:04:37.78#ibcon#enter sib2, iclass 20, count 0 2006.169.08:04:37.78#ibcon#flushed, iclass 20, count 0 2006.169.08:04:37.78#ibcon#about to write, iclass 20, count 0 2006.169.08:04:37.78#ibcon#wrote, iclass 20, count 0 2006.169.08:04:37.78#ibcon#about to read 3, iclass 20, count 0 2006.169.08:04:37.80#ibcon#read 3, iclass 20, count 0 2006.169.08:04:37.80#ibcon#about to read 4, iclass 20, count 0 2006.169.08:04:37.80#ibcon#read 4, iclass 20, count 0 2006.169.08:04:37.80#ibcon#about to read 5, iclass 20, count 0 2006.169.08:04:37.80#ibcon#read 5, iclass 20, count 0 2006.169.08:04:37.80#ibcon#about to read 6, iclass 20, count 0 2006.169.08:04:37.80#ibcon#read 6, iclass 20, count 0 2006.169.08:04:37.80#ibcon#end of sib2, iclass 20, count 0 2006.169.08:04:37.80#ibcon#*mode == 0, iclass 20, count 0 2006.169.08:04:37.80#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.169.08:04:37.80#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.08:04:37.80#ibcon#*before write, iclass 20, count 0 2006.169.08:04:37.80#ibcon#enter sib2, iclass 20, count 0 2006.169.08:04:37.80#ibcon#flushed, iclass 20, count 0 2006.169.08:04:37.80#ibcon#about to write, iclass 20, count 0 2006.169.08:04:37.80#ibcon#wrote, iclass 20, count 0 2006.169.08:04:37.80#ibcon#about to read 3, iclass 20, count 0 2006.169.08:04:37.84#ibcon#read 3, iclass 20, count 0 2006.169.08:04:37.84#ibcon#about to read 4, iclass 20, count 0 2006.169.08:04:37.84#ibcon#read 4, iclass 20, count 0 2006.169.08:04:37.84#ibcon#about to read 5, iclass 20, count 0 2006.169.08:04:37.84#ibcon#read 5, iclass 20, count 0 2006.169.08:04:37.84#ibcon#about to read 6, iclass 20, count 0 2006.169.08:04:37.84#ibcon#read 6, iclass 20, count 0 2006.169.08:04:37.84#ibcon#end of sib2, iclass 20, count 0 2006.169.08:04:37.84#ibcon#*after write, iclass 20, count 0 2006.169.08:04:37.84#ibcon#*before return 0, iclass 20, count 0 2006.169.08:04:37.84#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:04:37.84#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:04:37.84#ibcon#about to clear, iclass 20 cls_cnt 0 2006.169.08:04:37.84#ibcon#cleared, iclass 20 cls_cnt 0 2006.169.08:04:37.84$vc4f8/vb=2,4 2006.169.08:04:37.84#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.169.08:04:37.84#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.169.08:04:37.84#ibcon#ireg 11 cls_cnt 2 2006.169.08:04:37.84#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:04:37.90#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:04:37.90#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:04:37.90#ibcon#enter wrdev, iclass 22, count 2 2006.169.08:04:37.90#ibcon#first serial, iclass 22, count 2 2006.169.08:04:37.90#ibcon#enter sib2, iclass 22, count 2 2006.169.08:04:37.90#ibcon#flushed, iclass 22, count 2 2006.169.08:04:37.90#ibcon#about to write, iclass 22, count 2 2006.169.08:04:37.90#ibcon#wrote, iclass 22, count 2 2006.169.08:04:37.90#ibcon#about to read 3, iclass 22, count 2 2006.169.08:04:37.92#ibcon#read 3, iclass 22, count 2 2006.169.08:04:37.92#ibcon#about to read 4, iclass 22, count 2 2006.169.08:04:37.92#ibcon#read 4, iclass 22, count 2 2006.169.08:04:37.92#ibcon#about to read 5, iclass 22, count 2 2006.169.08:04:37.92#ibcon#read 5, iclass 22, count 2 2006.169.08:04:37.92#ibcon#about to read 6, iclass 22, count 2 2006.169.08:04:37.92#ibcon#read 6, iclass 22, count 2 2006.169.08:04:37.92#ibcon#end of sib2, iclass 22, count 2 2006.169.08:04:37.92#ibcon#*mode == 0, iclass 22, count 2 2006.169.08:04:37.92#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.169.08:04:37.92#ibcon#[27=AT02-04\r\n] 2006.169.08:04:37.92#ibcon#*before write, iclass 22, count 2 2006.169.08:04:37.92#ibcon#enter sib2, iclass 22, count 2 2006.169.08:04:37.92#ibcon#flushed, iclass 22, count 2 2006.169.08:04:37.92#ibcon#about to write, iclass 22, count 2 2006.169.08:04:37.92#ibcon#wrote, iclass 22, count 2 2006.169.08:04:37.92#ibcon#about to read 3, iclass 22, count 2 2006.169.08:04:37.95#ibcon#read 3, iclass 22, count 2 2006.169.08:04:37.95#ibcon#about to read 4, iclass 22, count 2 2006.169.08:04:37.95#ibcon#read 4, iclass 22, count 2 2006.169.08:04:37.95#ibcon#about to read 5, iclass 22, count 2 2006.169.08:04:37.95#ibcon#read 5, iclass 22, count 2 2006.169.08:04:37.95#ibcon#about to read 6, iclass 22, count 2 2006.169.08:04:37.95#ibcon#read 6, iclass 22, count 2 2006.169.08:04:37.95#ibcon#end of sib2, iclass 22, count 2 2006.169.08:04:37.95#ibcon#*after write, iclass 22, count 2 2006.169.08:04:37.95#ibcon#*before return 0, iclass 22, count 2 2006.169.08:04:37.95#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:04:37.95#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:04:37.95#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.169.08:04:37.95#ibcon#ireg 7 cls_cnt 0 2006.169.08:04:37.95#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:04:38.07#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:04:38.07#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:04:38.07#ibcon#enter wrdev, iclass 22, count 0 2006.169.08:04:38.07#ibcon#first serial, iclass 22, count 0 2006.169.08:04:38.07#ibcon#enter sib2, iclass 22, count 0 2006.169.08:04:38.07#ibcon#flushed, iclass 22, count 0 2006.169.08:04:38.07#ibcon#about to write, iclass 22, count 0 2006.169.08:04:38.07#ibcon#wrote, iclass 22, count 0 2006.169.08:04:38.07#ibcon#about to read 3, iclass 22, count 0 2006.169.08:04:38.09#ibcon#read 3, iclass 22, count 0 2006.169.08:04:38.09#ibcon#about to read 4, iclass 22, count 0 2006.169.08:04:38.09#ibcon#read 4, iclass 22, count 0 2006.169.08:04:38.09#ibcon#about to read 5, iclass 22, count 0 2006.169.08:04:38.09#ibcon#read 5, iclass 22, count 0 2006.169.08:04:38.09#ibcon#about to read 6, iclass 22, count 0 2006.169.08:04:38.09#ibcon#read 6, iclass 22, count 0 2006.169.08:04:38.09#ibcon#end of sib2, iclass 22, count 0 2006.169.08:04:38.09#ibcon#*mode == 0, iclass 22, count 0 2006.169.08:04:38.09#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.169.08:04:38.09#ibcon#[27=USB\r\n] 2006.169.08:04:38.09#ibcon#*before write, iclass 22, count 0 2006.169.08:04:38.09#ibcon#enter sib2, iclass 22, count 0 2006.169.08:04:38.09#ibcon#flushed, iclass 22, count 0 2006.169.08:04:38.09#ibcon#about to write, iclass 22, count 0 2006.169.08:04:38.09#ibcon#wrote, iclass 22, count 0 2006.169.08:04:38.09#ibcon#about to read 3, iclass 22, count 0 2006.169.08:04:38.12#ibcon#read 3, iclass 22, count 0 2006.169.08:04:38.12#ibcon#about to read 4, iclass 22, count 0 2006.169.08:04:38.12#ibcon#read 4, iclass 22, count 0 2006.169.08:04:38.12#ibcon#about to read 5, iclass 22, count 0 2006.169.08:04:38.12#ibcon#read 5, iclass 22, count 0 2006.169.08:04:38.12#ibcon#about to read 6, iclass 22, count 0 2006.169.08:04:38.12#ibcon#read 6, iclass 22, count 0 2006.169.08:04:38.12#ibcon#end of sib2, iclass 22, count 0 2006.169.08:04:38.12#ibcon#*after write, iclass 22, count 0 2006.169.08:04:38.12#ibcon#*before return 0, iclass 22, count 0 2006.169.08:04:38.12#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:04:38.12#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:04:38.12#ibcon#about to clear, iclass 22 cls_cnt 0 2006.169.08:04:38.12#ibcon#cleared, iclass 22 cls_cnt 0 2006.169.08:04:38.12$vc4f8/vblo=3,656.99 2006.169.08:04:38.12#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.169.08:04:38.12#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.169.08:04:38.12#ibcon#ireg 17 cls_cnt 0 2006.169.08:04:38.12#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:04:38.12#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:04:38.12#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:04:38.12#ibcon#enter wrdev, iclass 24, count 0 2006.169.08:04:38.12#ibcon#first serial, iclass 24, count 0 2006.169.08:04:38.12#ibcon#enter sib2, iclass 24, count 0 2006.169.08:04:38.12#ibcon#flushed, iclass 24, count 0 2006.169.08:04:38.12#ibcon#about to write, iclass 24, count 0 2006.169.08:04:38.12#ibcon#wrote, iclass 24, count 0 2006.169.08:04:38.12#ibcon#about to read 3, iclass 24, count 0 2006.169.08:04:38.14#ibcon#read 3, iclass 24, count 0 2006.169.08:04:38.14#ibcon#about to read 4, iclass 24, count 0 2006.169.08:04:38.14#ibcon#read 4, iclass 24, count 0 2006.169.08:04:38.14#ibcon#about to read 5, iclass 24, count 0 2006.169.08:04:38.14#ibcon#read 5, iclass 24, count 0 2006.169.08:04:38.14#ibcon#about to read 6, iclass 24, count 0 2006.169.08:04:38.14#ibcon#read 6, iclass 24, count 0 2006.169.08:04:38.14#ibcon#end of sib2, iclass 24, count 0 2006.169.08:04:38.14#ibcon#*mode == 0, iclass 24, count 0 2006.169.08:04:38.14#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.169.08:04:38.14#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.08:04:38.14#ibcon#*before write, iclass 24, count 0 2006.169.08:04:38.14#ibcon#enter sib2, iclass 24, count 0 2006.169.08:04:38.14#ibcon#flushed, iclass 24, count 0 2006.169.08:04:38.14#ibcon#about to write, iclass 24, count 0 2006.169.08:04:38.14#ibcon#wrote, iclass 24, count 0 2006.169.08:04:38.14#ibcon#about to read 3, iclass 24, count 0 2006.169.08:04:38.18#ibcon#read 3, iclass 24, count 0 2006.169.08:04:38.18#ibcon#about to read 4, iclass 24, count 0 2006.169.08:04:38.18#ibcon#read 4, iclass 24, count 0 2006.169.08:04:38.18#ibcon#about to read 5, iclass 24, count 0 2006.169.08:04:38.18#ibcon#read 5, iclass 24, count 0 2006.169.08:04:38.18#ibcon#about to read 6, iclass 24, count 0 2006.169.08:04:38.18#ibcon#read 6, iclass 24, count 0 2006.169.08:04:38.18#ibcon#end of sib2, iclass 24, count 0 2006.169.08:04:38.18#ibcon#*after write, iclass 24, count 0 2006.169.08:04:38.18#ibcon#*before return 0, iclass 24, count 0 2006.169.08:04:38.18#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:04:38.18#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:04:38.18#ibcon#about to clear, iclass 24 cls_cnt 0 2006.169.08:04:38.18#ibcon#cleared, iclass 24 cls_cnt 0 2006.169.08:04:38.18$vc4f8/vb=3,4 2006.169.08:04:38.18#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.169.08:04:38.18#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.169.08:04:38.18#ibcon#ireg 11 cls_cnt 2 2006.169.08:04:38.18#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.169.08:04:38.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.169.08:04:38.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.169.08:04:38.24#ibcon#enter wrdev, iclass 26, count 2 2006.169.08:04:38.24#ibcon#first serial, iclass 26, count 2 2006.169.08:04:38.24#ibcon#enter sib2, iclass 26, count 2 2006.169.08:04:38.24#ibcon#flushed, iclass 26, count 2 2006.169.08:04:38.24#ibcon#about to write, iclass 26, count 2 2006.169.08:04:38.24#ibcon#wrote, iclass 26, count 2 2006.169.08:04:38.24#ibcon#about to read 3, iclass 26, count 2 2006.169.08:04:38.26#ibcon#read 3, iclass 26, count 2 2006.169.08:04:38.26#ibcon#about to read 4, iclass 26, count 2 2006.169.08:04:38.26#ibcon#read 4, iclass 26, count 2 2006.169.08:04:38.26#ibcon#about to read 5, iclass 26, count 2 2006.169.08:04:38.26#ibcon#read 5, iclass 26, count 2 2006.169.08:04:38.26#ibcon#about to read 6, iclass 26, count 2 2006.169.08:04:38.26#ibcon#read 6, iclass 26, count 2 2006.169.08:04:38.26#ibcon#end of sib2, iclass 26, count 2 2006.169.08:04:38.26#ibcon#*mode == 0, iclass 26, count 2 2006.169.08:04:38.26#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.169.08:04:38.26#ibcon#[27=AT03-04\r\n] 2006.169.08:04:38.26#ibcon#*before write, iclass 26, count 2 2006.169.08:04:38.26#ibcon#enter sib2, iclass 26, count 2 2006.169.08:04:38.26#ibcon#flushed, iclass 26, count 2 2006.169.08:04:38.26#ibcon#about to write, iclass 26, count 2 2006.169.08:04:38.26#ibcon#wrote, iclass 26, count 2 2006.169.08:04:38.26#ibcon#about to read 3, iclass 26, count 2 2006.169.08:04:38.29#ibcon#read 3, iclass 26, count 2 2006.169.08:04:38.29#ibcon#about to read 4, iclass 26, count 2 2006.169.08:04:38.29#ibcon#read 4, iclass 26, count 2 2006.169.08:04:38.29#ibcon#about to read 5, iclass 26, count 2 2006.169.08:04:38.29#ibcon#read 5, iclass 26, count 2 2006.169.08:04:38.29#ibcon#about to read 6, iclass 26, count 2 2006.169.08:04:38.29#ibcon#read 6, iclass 26, count 2 2006.169.08:04:38.29#ibcon#end of sib2, iclass 26, count 2 2006.169.08:04:38.29#ibcon#*after write, iclass 26, count 2 2006.169.08:04:38.29#ibcon#*before return 0, iclass 26, count 2 2006.169.08:04:38.29#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.169.08:04:38.29#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.169.08:04:38.29#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.169.08:04:38.29#ibcon#ireg 7 cls_cnt 0 2006.169.08:04:38.29#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.169.08:04:38.41#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.169.08:04:38.41#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.169.08:04:38.41#ibcon#enter wrdev, iclass 26, count 0 2006.169.08:04:38.41#ibcon#first serial, iclass 26, count 0 2006.169.08:04:38.41#ibcon#enter sib2, iclass 26, count 0 2006.169.08:04:38.41#ibcon#flushed, iclass 26, count 0 2006.169.08:04:38.41#ibcon#about to write, iclass 26, count 0 2006.169.08:04:38.41#ibcon#wrote, iclass 26, count 0 2006.169.08:04:38.41#ibcon#about to read 3, iclass 26, count 0 2006.169.08:04:38.43#ibcon#read 3, iclass 26, count 0 2006.169.08:04:38.43#ibcon#about to read 4, iclass 26, count 0 2006.169.08:04:38.43#ibcon#read 4, iclass 26, count 0 2006.169.08:04:38.43#ibcon#about to read 5, iclass 26, count 0 2006.169.08:04:38.43#ibcon#read 5, iclass 26, count 0 2006.169.08:04:38.43#ibcon#about to read 6, iclass 26, count 0 2006.169.08:04:38.43#ibcon#read 6, iclass 26, count 0 2006.169.08:04:38.43#ibcon#end of sib2, iclass 26, count 0 2006.169.08:04:38.43#ibcon#*mode == 0, iclass 26, count 0 2006.169.08:04:38.43#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.169.08:04:38.43#ibcon#[27=USB\r\n] 2006.169.08:04:38.43#ibcon#*before write, iclass 26, count 0 2006.169.08:04:38.43#ibcon#enter sib2, iclass 26, count 0 2006.169.08:04:38.43#ibcon#flushed, iclass 26, count 0 2006.169.08:04:38.43#ibcon#about to write, iclass 26, count 0 2006.169.08:04:38.43#ibcon#wrote, iclass 26, count 0 2006.169.08:04:38.43#ibcon#about to read 3, iclass 26, count 0 2006.169.08:04:38.46#ibcon#read 3, iclass 26, count 0 2006.169.08:04:38.46#ibcon#about to read 4, iclass 26, count 0 2006.169.08:04:38.46#ibcon#read 4, iclass 26, count 0 2006.169.08:04:38.46#ibcon#about to read 5, iclass 26, count 0 2006.169.08:04:38.46#ibcon#read 5, iclass 26, count 0 2006.169.08:04:38.46#ibcon#about to read 6, iclass 26, count 0 2006.169.08:04:38.46#ibcon#read 6, iclass 26, count 0 2006.169.08:04:38.46#ibcon#end of sib2, iclass 26, count 0 2006.169.08:04:38.46#ibcon#*after write, iclass 26, count 0 2006.169.08:04:38.46#ibcon#*before return 0, iclass 26, count 0 2006.169.08:04:38.46#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.169.08:04:38.46#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.169.08:04:38.46#ibcon#about to clear, iclass 26 cls_cnt 0 2006.169.08:04:38.46#ibcon#cleared, iclass 26 cls_cnt 0 2006.169.08:04:38.46$vc4f8/vblo=4,712.99 2006.169.08:04:38.46#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.169.08:04:38.46#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.169.08:04:38.46#ibcon#ireg 17 cls_cnt 0 2006.169.08:04:38.46#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:04:38.46#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:04:38.46#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:04:38.46#ibcon#enter wrdev, iclass 28, count 0 2006.169.08:04:38.46#ibcon#first serial, iclass 28, count 0 2006.169.08:04:38.46#ibcon#enter sib2, iclass 28, count 0 2006.169.08:04:38.46#ibcon#flushed, iclass 28, count 0 2006.169.08:04:38.46#ibcon#about to write, iclass 28, count 0 2006.169.08:04:38.46#ibcon#wrote, iclass 28, count 0 2006.169.08:04:38.46#ibcon#about to read 3, iclass 28, count 0 2006.169.08:04:38.48#ibcon#read 3, iclass 28, count 0 2006.169.08:04:38.48#ibcon#about to read 4, iclass 28, count 0 2006.169.08:04:38.48#ibcon#read 4, iclass 28, count 0 2006.169.08:04:38.48#ibcon#about to read 5, iclass 28, count 0 2006.169.08:04:38.48#ibcon#read 5, iclass 28, count 0 2006.169.08:04:38.48#ibcon#about to read 6, iclass 28, count 0 2006.169.08:04:38.48#ibcon#read 6, iclass 28, count 0 2006.169.08:04:38.48#ibcon#end of sib2, iclass 28, count 0 2006.169.08:04:38.48#ibcon#*mode == 0, iclass 28, count 0 2006.169.08:04:38.48#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.169.08:04:38.48#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.08:04:38.48#ibcon#*before write, iclass 28, count 0 2006.169.08:04:38.48#ibcon#enter sib2, iclass 28, count 0 2006.169.08:04:38.48#ibcon#flushed, iclass 28, count 0 2006.169.08:04:38.48#ibcon#about to write, iclass 28, count 0 2006.169.08:04:38.48#ibcon#wrote, iclass 28, count 0 2006.169.08:04:38.48#ibcon#about to read 3, iclass 28, count 0 2006.169.08:04:38.52#ibcon#read 3, iclass 28, count 0 2006.169.08:04:38.52#ibcon#about to read 4, iclass 28, count 0 2006.169.08:04:38.52#ibcon#read 4, iclass 28, count 0 2006.169.08:04:38.52#ibcon#about to read 5, iclass 28, count 0 2006.169.08:04:38.52#ibcon#read 5, iclass 28, count 0 2006.169.08:04:38.52#ibcon#about to read 6, iclass 28, count 0 2006.169.08:04:38.52#ibcon#read 6, iclass 28, count 0 2006.169.08:04:38.52#ibcon#end of sib2, iclass 28, count 0 2006.169.08:04:38.52#ibcon#*after write, iclass 28, count 0 2006.169.08:04:38.52#ibcon#*before return 0, iclass 28, count 0 2006.169.08:04:38.52#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:04:38.52#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:04:38.52#ibcon#about to clear, iclass 28 cls_cnt 0 2006.169.08:04:38.52#ibcon#cleared, iclass 28 cls_cnt 0 2006.169.08:04:38.52$vc4f8/vb=4,4 2006.169.08:04:38.52#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.169.08:04:38.52#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.169.08:04:38.52#ibcon#ireg 11 cls_cnt 2 2006.169.08:04:38.52#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:04:38.58#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:04:38.58#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:04:38.58#ibcon#enter wrdev, iclass 30, count 2 2006.169.08:04:38.58#ibcon#first serial, iclass 30, count 2 2006.169.08:04:38.58#ibcon#enter sib2, iclass 30, count 2 2006.169.08:04:38.58#ibcon#flushed, iclass 30, count 2 2006.169.08:04:38.58#ibcon#about to write, iclass 30, count 2 2006.169.08:04:38.58#ibcon#wrote, iclass 30, count 2 2006.169.08:04:38.58#ibcon#about to read 3, iclass 30, count 2 2006.169.08:04:38.60#ibcon#read 3, iclass 30, count 2 2006.169.08:04:38.60#ibcon#about to read 4, iclass 30, count 2 2006.169.08:04:38.60#ibcon#read 4, iclass 30, count 2 2006.169.08:04:38.60#ibcon#about to read 5, iclass 30, count 2 2006.169.08:04:38.60#ibcon#read 5, iclass 30, count 2 2006.169.08:04:38.60#ibcon#about to read 6, iclass 30, count 2 2006.169.08:04:38.60#ibcon#read 6, iclass 30, count 2 2006.169.08:04:38.60#ibcon#end of sib2, iclass 30, count 2 2006.169.08:04:38.60#ibcon#*mode == 0, iclass 30, count 2 2006.169.08:04:38.60#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.169.08:04:38.60#ibcon#[27=AT04-04\r\n] 2006.169.08:04:38.60#ibcon#*before write, iclass 30, count 2 2006.169.08:04:38.60#ibcon#enter sib2, iclass 30, count 2 2006.169.08:04:38.60#ibcon#flushed, iclass 30, count 2 2006.169.08:04:38.60#ibcon#about to write, iclass 30, count 2 2006.169.08:04:38.60#ibcon#wrote, iclass 30, count 2 2006.169.08:04:38.60#ibcon#about to read 3, iclass 30, count 2 2006.169.08:04:38.63#ibcon#read 3, iclass 30, count 2 2006.169.08:04:38.63#ibcon#about to read 4, iclass 30, count 2 2006.169.08:04:38.63#ibcon#read 4, iclass 30, count 2 2006.169.08:04:38.63#ibcon#about to read 5, iclass 30, count 2 2006.169.08:04:38.63#ibcon#read 5, iclass 30, count 2 2006.169.08:04:38.63#ibcon#about to read 6, iclass 30, count 2 2006.169.08:04:38.63#ibcon#read 6, iclass 30, count 2 2006.169.08:04:38.63#ibcon#end of sib2, iclass 30, count 2 2006.169.08:04:38.63#ibcon#*after write, iclass 30, count 2 2006.169.08:04:38.63#ibcon#*before return 0, iclass 30, count 2 2006.169.08:04:38.63#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:04:38.63#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:04:38.63#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.169.08:04:38.63#ibcon#ireg 7 cls_cnt 0 2006.169.08:04:38.63#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:04:38.75#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:04:38.75#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:04:38.75#ibcon#enter wrdev, iclass 30, count 0 2006.169.08:04:38.75#ibcon#first serial, iclass 30, count 0 2006.169.08:04:38.75#ibcon#enter sib2, iclass 30, count 0 2006.169.08:04:38.75#ibcon#flushed, iclass 30, count 0 2006.169.08:04:38.75#ibcon#about to write, iclass 30, count 0 2006.169.08:04:38.75#ibcon#wrote, iclass 30, count 0 2006.169.08:04:38.75#ibcon#about to read 3, iclass 30, count 0 2006.169.08:04:38.77#ibcon#read 3, iclass 30, count 0 2006.169.08:04:38.77#ibcon#about to read 4, iclass 30, count 0 2006.169.08:04:38.77#ibcon#read 4, iclass 30, count 0 2006.169.08:04:38.77#ibcon#about to read 5, iclass 30, count 0 2006.169.08:04:38.77#ibcon#read 5, iclass 30, count 0 2006.169.08:04:38.77#ibcon#about to read 6, iclass 30, count 0 2006.169.08:04:38.77#ibcon#read 6, iclass 30, count 0 2006.169.08:04:38.77#ibcon#end of sib2, iclass 30, count 0 2006.169.08:04:38.77#ibcon#*mode == 0, iclass 30, count 0 2006.169.08:04:38.77#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.169.08:04:38.77#ibcon#[27=USB\r\n] 2006.169.08:04:38.77#ibcon#*before write, iclass 30, count 0 2006.169.08:04:38.77#ibcon#enter sib2, iclass 30, count 0 2006.169.08:04:38.77#ibcon#flushed, iclass 30, count 0 2006.169.08:04:38.77#ibcon#about to write, iclass 30, count 0 2006.169.08:04:38.77#ibcon#wrote, iclass 30, count 0 2006.169.08:04:38.77#ibcon#about to read 3, iclass 30, count 0 2006.169.08:04:38.80#ibcon#read 3, iclass 30, count 0 2006.169.08:04:38.80#ibcon#about to read 4, iclass 30, count 0 2006.169.08:04:38.80#ibcon#read 4, iclass 30, count 0 2006.169.08:04:38.80#ibcon#about to read 5, iclass 30, count 0 2006.169.08:04:38.80#ibcon#read 5, iclass 30, count 0 2006.169.08:04:38.80#ibcon#about to read 6, iclass 30, count 0 2006.169.08:04:38.80#ibcon#read 6, iclass 30, count 0 2006.169.08:04:38.80#ibcon#end of sib2, iclass 30, count 0 2006.169.08:04:38.80#ibcon#*after write, iclass 30, count 0 2006.169.08:04:38.80#ibcon#*before return 0, iclass 30, count 0 2006.169.08:04:38.80#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:04:38.80#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:04:38.80#ibcon#about to clear, iclass 30 cls_cnt 0 2006.169.08:04:38.80#ibcon#cleared, iclass 30 cls_cnt 0 2006.169.08:04:38.80$vc4f8/vblo=5,744.99 2006.169.08:04:38.80#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.169.08:04:38.80#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.169.08:04:38.80#ibcon#ireg 17 cls_cnt 0 2006.169.08:04:38.80#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:04:38.80#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:04:38.80#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:04:38.80#ibcon#enter wrdev, iclass 32, count 0 2006.169.08:04:38.80#ibcon#first serial, iclass 32, count 0 2006.169.08:04:38.80#ibcon#enter sib2, iclass 32, count 0 2006.169.08:04:38.80#ibcon#flushed, iclass 32, count 0 2006.169.08:04:38.80#ibcon#about to write, iclass 32, count 0 2006.169.08:04:38.80#ibcon#wrote, iclass 32, count 0 2006.169.08:04:38.80#ibcon#about to read 3, iclass 32, count 0 2006.169.08:04:38.82#ibcon#read 3, iclass 32, count 0 2006.169.08:04:38.82#ibcon#about to read 4, iclass 32, count 0 2006.169.08:04:38.82#ibcon#read 4, iclass 32, count 0 2006.169.08:04:38.82#ibcon#about to read 5, iclass 32, count 0 2006.169.08:04:38.82#ibcon#read 5, iclass 32, count 0 2006.169.08:04:38.82#ibcon#about to read 6, iclass 32, count 0 2006.169.08:04:38.82#ibcon#read 6, iclass 32, count 0 2006.169.08:04:38.82#ibcon#end of sib2, iclass 32, count 0 2006.169.08:04:38.82#ibcon#*mode == 0, iclass 32, count 0 2006.169.08:04:38.82#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.169.08:04:38.82#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.08:04:38.82#ibcon#*before write, iclass 32, count 0 2006.169.08:04:38.82#ibcon#enter sib2, iclass 32, count 0 2006.169.08:04:38.82#ibcon#flushed, iclass 32, count 0 2006.169.08:04:38.82#ibcon#about to write, iclass 32, count 0 2006.169.08:04:38.82#ibcon#wrote, iclass 32, count 0 2006.169.08:04:38.82#ibcon#about to read 3, iclass 32, count 0 2006.169.08:04:38.86#ibcon#read 3, iclass 32, count 0 2006.169.08:04:38.86#ibcon#about to read 4, iclass 32, count 0 2006.169.08:04:38.86#ibcon#read 4, iclass 32, count 0 2006.169.08:04:38.86#ibcon#about to read 5, iclass 32, count 0 2006.169.08:04:38.86#ibcon#read 5, iclass 32, count 0 2006.169.08:04:38.86#ibcon#about to read 6, iclass 32, count 0 2006.169.08:04:38.86#ibcon#read 6, iclass 32, count 0 2006.169.08:04:38.86#ibcon#end of sib2, iclass 32, count 0 2006.169.08:04:38.86#ibcon#*after write, iclass 32, count 0 2006.169.08:04:38.86#ibcon#*before return 0, iclass 32, count 0 2006.169.08:04:38.86#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:04:38.86#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:04:38.86#ibcon#about to clear, iclass 32 cls_cnt 0 2006.169.08:04:38.86#ibcon#cleared, iclass 32 cls_cnt 0 2006.169.08:04:38.86$vc4f8/vb=5,4 2006.169.08:04:38.86#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.169.08:04:38.86#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.169.08:04:38.86#ibcon#ireg 11 cls_cnt 2 2006.169.08:04:38.86#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:04:38.92#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:04:38.92#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:04:38.92#ibcon#enter wrdev, iclass 34, count 2 2006.169.08:04:38.92#ibcon#first serial, iclass 34, count 2 2006.169.08:04:38.92#ibcon#enter sib2, iclass 34, count 2 2006.169.08:04:38.92#ibcon#flushed, iclass 34, count 2 2006.169.08:04:38.92#ibcon#about to write, iclass 34, count 2 2006.169.08:04:38.92#ibcon#wrote, iclass 34, count 2 2006.169.08:04:38.92#ibcon#about to read 3, iclass 34, count 2 2006.169.08:04:38.94#ibcon#read 3, iclass 34, count 2 2006.169.08:04:38.94#ibcon#about to read 4, iclass 34, count 2 2006.169.08:04:38.94#ibcon#read 4, iclass 34, count 2 2006.169.08:04:38.94#ibcon#about to read 5, iclass 34, count 2 2006.169.08:04:38.94#ibcon#read 5, iclass 34, count 2 2006.169.08:04:38.94#ibcon#about to read 6, iclass 34, count 2 2006.169.08:04:38.94#ibcon#read 6, iclass 34, count 2 2006.169.08:04:38.94#ibcon#end of sib2, iclass 34, count 2 2006.169.08:04:38.94#ibcon#*mode == 0, iclass 34, count 2 2006.169.08:04:38.94#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.169.08:04:38.94#ibcon#[27=AT05-04\r\n] 2006.169.08:04:38.94#ibcon#*before write, iclass 34, count 2 2006.169.08:04:38.94#ibcon#enter sib2, iclass 34, count 2 2006.169.08:04:38.94#ibcon#flushed, iclass 34, count 2 2006.169.08:04:38.94#ibcon#about to write, iclass 34, count 2 2006.169.08:04:38.94#ibcon#wrote, iclass 34, count 2 2006.169.08:04:38.94#ibcon#about to read 3, iclass 34, count 2 2006.169.08:04:38.97#ibcon#read 3, iclass 34, count 2 2006.169.08:04:38.97#ibcon#about to read 4, iclass 34, count 2 2006.169.08:04:38.97#ibcon#read 4, iclass 34, count 2 2006.169.08:04:38.97#ibcon#about to read 5, iclass 34, count 2 2006.169.08:04:38.97#ibcon#read 5, iclass 34, count 2 2006.169.08:04:38.97#ibcon#about to read 6, iclass 34, count 2 2006.169.08:04:38.97#ibcon#read 6, iclass 34, count 2 2006.169.08:04:38.97#ibcon#end of sib2, iclass 34, count 2 2006.169.08:04:38.97#ibcon#*after write, iclass 34, count 2 2006.169.08:04:38.97#ibcon#*before return 0, iclass 34, count 2 2006.169.08:04:38.97#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:04:38.97#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:04:38.97#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.169.08:04:38.97#ibcon#ireg 7 cls_cnt 0 2006.169.08:04:38.97#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:04:39.09#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:04:39.09#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:04:39.09#ibcon#enter wrdev, iclass 34, count 0 2006.169.08:04:39.09#ibcon#first serial, iclass 34, count 0 2006.169.08:04:39.09#ibcon#enter sib2, iclass 34, count 0 2006.169.08:04:39.09#ibcon#flushed, iclass 34, count 0 2006.169.08:04:39.09#ibcon#about to write, iclass 34, count 0 2006.169.08:04:39.09#ibcon#wrote, iclass 34, count 0 2006.169.08:04:39.09#ibcon#about to read 3, iclass 34, count 0 2006.169.08:04:39.11#ibcon#read 3, iclass 34, count 0 2006.169.08:04:39.11#ibcon#about to read 4, iclass 34, count 0 2006.169.08:04:39.11#ibcon#read 4, iclass 34, count 0 2006.169.08:04:39.11#ibcon#about to read 5, iclass 34, count 0 2006.169.08:04:39.11#ibcon#read 5, iclass 34, count 0 2006.169.08:04:39.11#ibcon#about to read 6, iclass 34, count 0 2006.169.08:04:39.11#ibcon#read 6, iclass 34, count 0 2006.169.08:04:39.11#ibcon#end of sib2, iclass 34, count 0 2006.169.08:04:39.11#ibcon#*mode == 0, iclass 34, count 0 2006.169.08:04:39.11#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.169.08:04:39.11#ibcon#[27=USB\r\n] 2006.169.08:04:39.11#ibcon#*before write, iclass 34, count 0 2006.169.08:04:39.11#ibcon#enter sib2, iclass 34, count 0 2006.169.08:04:39.11#ibcon#flushed, iclass 34, count 0 2006.169.08:04:39.11#ibcon#about to write, iclass 34, count 0 2006.169.08:04:39.11#ibcon#wrote, iclass 34, count 0 2006.169.08:04:39.11#ibcon#about to read 3, iclass 34, count 0 2006.169.08:04:39.14#ibcon#read 3, iclass 34, count 0 2006.169.08:04:39.14#ibcon#about to read 4, iclass 34, count 0 2006.169.08:04:39.14#ibcon#read 4, iclass 34, count 0 2006.169.08:04:39.14#ibcon#about to read 5, iclass 34, count 0 2006.169.08:04:39.14#ibcon#read 5, iclass 34, count 0 2006.169.08:04:39.14#ibcon#about to read 6, iclass 34, count 0 2006.169.08:04:39.14#ibcon#read 6, iclass 34, count 0 2006.169.08:04:39.14#ibcon#end of sib2, iclass 34, count 0 2006.169.08:04:39.14#ibcon#*after write, iclass 34, count 0 2006.169.08:04:39.14#ibcon#*before return 0, iclass 34, count 0 2006.169.08:04:39.14#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:04:39.14#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:04:39.14#ibcon#about to clear, iclass 34 cls_cnt 0 2006.169.08:04:39.14#ibcon#cleared, iclass 34 cls_cnt 0 2006.169.08:04:39.14$vc4f8/vblo=6,752.99 2006.169.08:04:39.14#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.169.08:04:39.14#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.169.08:04:39.14#ibcon#ireg 17 cls_cnt 0 2006.169.08:04:39.14#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:04:39.14#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:04:39.14#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:04:39.14#ibcon#enter wrdev, iclass 36, count 0 2006.169.08:04:39.14#ibcon#first serial, iclass 36, count 0 2006.169.08:04:39.14#ibcon#enter sib2, iclass 36, count 0 2006.169.08:04:39.14#ibcon#flushed, iclass 36, count 0 2006.169.08:04:39.14#ibcon#about to write, iclass 36, count 0 2006.169.08:04:39.14#ibcon#wrote, iclass 36, count 0 2006.169.08:04:39.14#ibcon#about to read 3, iclass 36, count 0 2006.169.08:04:39.16#ibcon#read 3, iclass 36, count 0 2006.169.08:04:39.16#ibcon#about to read 4, iclass 36, count 0 2006.169.08:04:39.16#ibcon#read 4, iclass 36, count 0 2006.169.08:04:39.16#ibcon#about to read 5, iclass 36, count 0 2006.169.08:04:39.16#ibcon#read 5, iclass 36, count 0 2006.169.08:04:39.16#ibcon#about to read 6, iclass 36, count 0 2006.169.08:04:39.16#ibcon#read 6, iclass 36, count 0 2006.169.08:04:39.16#ibcon#end of sib2, iclass 36, count 0 2006.169.08:04:39.16#ibcon#*mode == 0, iclass 36, count 0 2006.169.08:04:39.16#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.169.08:04:39.16#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.08:04:39.16#ibcon#*before write, iclass 36, count 0 2006.169.08:04:39.16#ibcon#enter sib2, iclass 36, count 0 2006.169.08:04:39.16#ibcon#flushed, iclass 36, count 0 2006.169.08:04:39.16#ibcon#about to write, iclass 36, count 0 2006.169.08:04:39.16#ibcon#wrote, iclass 36, count 0 2006.169.08:04:39.16#ibcon#about to read 3, iclass 36, count 0 2006.169.08:04:39.20#ibcon#read 3, iclass 36, count 0 2006.169.08:04:39.20#ibcon#about to read 4, iclass 36, count 0 2006.169.08:04:39.20#ibcon#read 4, iclass 36, count 0 2006.169.08:04:39.20#ibcon#about to read 5, iclass 36, count 0 2006.169.08:04:39.20#ibcon#read 5, iclass 36, count 0 2006.169.08:04:39.20#ibcon#about to read 6, iclass 36, count 0 2006.169.08:04:39.20#ibcon#read 6, iclass 36, count 0 2006.169.08:04:39.20#ibcon#end of sib2, iclass 36, count 0 2006.169.08:04:39.20#ibcon#*after write, iclass 36, count 0 2006.169.08:04:39.20#ibcon#*before return 0, iclass 36, count 0 2006.169.08:04:39.20#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:04:39.20#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:04:39.20#ibcon#about to clear, iclass 36 cls_cnt 0 2006.169.08:04:39.20#ibcon#cleared, iclass 36 cls_cnt 0 2006.169.08:04:39.20$vc4f8/vb=6,4 2006.169.08:04:39.20#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.169.08:04:39.20#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.169.08:04:39.20#ibcon#ireg 11 cls_cnt 2 2006.169.08:04:39.20#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:04:39.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:04:39.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:04:39.26#ibcon#enter wrdev, iclass 38, count 2 2006.169.08:04:39.26#ibcon#first serial, iclass 38, count 2 2006.169.08:04:39.26#ibcon#enter sib2, iclass 38, count 2 2006.169.08:04:39.26#ibcon#flushed, iclass 38, count 2 2006.169.08:04:39.26#ibcon#about to write, iclass 38, count 2 2006.169.08:04:39.26#ibcon#wrote, iclass 38, count 2 2006.169.08:04:39.26#ibcon#about to read 3, iclass 38, count 2 2006.169.08:04:39.28#ibcon#read 3, iclass 38, count 2 2006.169.08:04:39.28#ibcon#about to read 4, iclass 38, count 2 2006.169.08:04:39.28#ibcon#read 4, iclass 38, count 2 2006.169.08:04:39.28#ibcon#about to read 5, iclass 38, count 2 2006.169.08:04:39.28#ibcon#read 5, iclass 38, count 2 2006.169.08:04:39.28#ibcon#about to read 6, iclass 38, count 2 2006.169.08:04:39.28#ibcon#read 6, iclass 38, count 2 2006.169.08:04:39.28#ibcon#end of sib2, iclass 38, count 2 2006.169.08:04:39.28#ibcon#*mode == 0, iclass 38, count 2 2006.169.08:04:39.28#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.169.08:04:39.28#ibcon#[27=AT06-04\r\n] 2006.169.08:04:39.28#ibcon#*before write, iclass 38, count 2 2006.169.08:04:39.28#ibcon#enter sib2, iclass 38, count 2 2006.169.08:04:39.28#ibcon#flushed, iclass 38, count 2 2006.169.08:04:39.28#ibcon#about to write, iclass 38, count 2 2006.169.08:04:39.28#ibcon#wrote, iclass 38, count 2 2006.169.08:04:39.28#ibcon#about to read 3, iclass 38, count 2 2006.169.08:04:39.31#ibcon#read 3, iclass 38, count 2 2006.169.08:04:39.31#ibcon#about to read 4, iclass 38, count 2 2006.169.08:04:39.31#ibcon#read 4, iclass 38, count 2 2006.169.08:04:39.31#ibcon#about to read 5, iclass 38, count 2 2006.169.08:04:39.31#ibcon#read 5, iclass 38, count 2 2006.169.08:04:39.31#ibcon#about to read 6, iclass 38, count 2 2006.169.08:04:39.31#ibcon#read 6, iclass 38, count 2 2006.169.08:04:39.31#ibcon#end of sib2, iclass 38, count 2 2006.169.08:04:39.31#ibcon#*after write, iclass 38, count 2 2006.169.08:04:39.31#ibcon#*before return 0, iclass 38, count 2 2006.169.08:04:39.31#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:04:39.31#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:04:39.31#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.169.08:04:39.31#ibcon#ireg 7 cls_cnt 0 2006.169.08:04:39.31#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:04:39.43#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:04:39.43#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:04:39.43#ibcon#enter wrdev, iclass 38, count 0 2006.169.08:04:39.43#ibcon#first serial, iclass 38, count 0 2006.169.08:04:39.43#ibcon#enter sib2, iclass 38, count 0 2006.169.08:04:39.43#ibcon#flushed, iclass 38, count 0 2006.169.08:04:39.43#ibcon#about to write, iclass 38, count 0 2006.169.08:04:39.43#ibcon#wrote, iclass 38, count 0 2006.169.08:04:39.43#ibcon#about to read 3, iclass 38, count 0 2006.169.08:04:39.45#ibcon#read 3, iclass 38, count 0 2006.169.08:04:39.45#ibcon#about to read 4, iclass 38, count 0 2006.169.08:04:39.45#ibcon#read 4, iclass 38, count 0 2006.169.08:04:39.45#ibcon#about to read 5, iclass 38, count 0 2006.169.08:04:39.45#ibcon#read 5, iclass 38, count 0 2006.169.08:04:39.45#ibcon#about to read 6, iclass 38, count 0 2006.169.08:04:39.45#ibcon#read 6, iclass 38, count 0 2006.169.08:04:39.45#ibcon#end of sib2, iclass 38, count 0 2006.169.08:04:39.45#ibcon#*mode == 0, iclass 38, count 0 2006.169.08:04:39.45#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.169.08:04:39.45#ibcon#[27=USB\r\n] 2006.169.08:04:39.45#ibcon#*before write, iclass 38, count 0 2006.169.08:04:39.45#ibcon#enter sib2, iclass 38, count 0 2006.169.08:04:39.45#ibcon#flushed, iclass 38, count 0 2006.169.08:04:39.45#ibcon#about to write, iclass 38, count 0 2006.169.08:04:39.45#ibcon#wrote, iclass 38, count 0 2006.169.08:04:39.45#ibcon#about to read 3, iclass 38, count 0 2006.169.08:04:39.48#ibcon#read 3, iclass 38, count 0 2006.169.08:04:39.48#ibcon#about to read 4, iclass 38, count 0 2006.169.08:04:39.48#ibcon#read 4, iclass 38, count 0 2006.169.08:04:39.48#ibcon#about to read 5, iclass 38, count 0 2006.169.08:04:39.48#ibcon#read 5, iclass 38, count 0 2006.169.08:04:39.48#ibcon#about to read 6, iclass 38, count 0 2006.169.08:04:39.48#ibcon#read 6, iclass 38, count 0 2006.169.08:04:39.48#ibcon#end of sib2, iclass 38, count 0 2006.169.08:04:39.48#ibcon#*after write, iclass 38, count 0 2006.169.08:04:39.48#ibcon#*before return 0, iclass 38, count 0 2006.169.08:04:39.48#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:04:39.48#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:04:39.48#ibcon#about to clear, iclass 38 cls_cnt 0 2006.169.08:04:39.48#ibcon#cleared, iclass 38 cls_cnt 0 2006.169.08:04:39.48$vc4f8/vabw=wide 2006.169.08:04:39.48#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.169.08:04:39.48#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.169.08:04:39.48#ibcon#ireg 8 cls_cnt 0 2006.169.08:04:39.48#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:04:39.48#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:04:39.48#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:04:39.48#ibcon#enter wrdev, iclass 40, count 0 2006.169.08:04:39.48#ibcon#first serial, iclass 40, count 0 2006.169.08:04:39.48#ibcon#enter sib2, iclass 40, count 0 2006.169.08:04:39.48#ibcon#flushed, iclass 40, count 0 2006.169.08:04:39.48#ibcon#about to write, iclass 40, count 0 2006.169.08:04:39.48#ibcon#wrote, iclass 40, count 0 2006.169.08:04:39.48#ibcon#about to read 3, iclass 40, count 0 2006.169.08:04:39.50#ibcon#read 3, iclass 40, count 0 2006.169.08:04:39.50#ibcon#about to read 4, iclass 40, count 0 2006.169.08:04:39.50#ibcon#read 4, iclass 40, count 0 2006.169.08:04:39.50#ibcon#about to read 5, iclass 40, count 0 2006.169.08:04:39.50#ibcon#read 5, iclass 40, count 0 2006.169.08:04:39.50#ibcon#about to read 6, iclass 40, count 0 2006.169.08:04:39.50#ibcon#read 6, iclass 40, count 0 2006.169.08:04:39.50#ibcon#end of sib2, iclass 40, count 0 2006.169.08:04:39.50#ibcon#*mode == 0, iclass 40, count 0 2006.169.08:04:39.50#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.169.08:04:39.50#ibcon#[25=BW32\r\n] 2006.169.08:04:39.50#ibcon#*before write, iclass 40, count 0 2006.169.08:04:39.50#ibcon#enter sib2, iclass 40, count 0 2006.169.08:04:39.50#ibcon#flushed, iclass 40, count 0 2006.169.08:04:39.50#ibcon#about to write, iclass 40, count 0 2006.169.08:04:39.50#ibcon#wrote, iclass 40, count 0 2006.169.08:04:39.50#ibcon#about to read 3, iclass 40, count 0 2006.169.08:04:39.53#ibcon#read 3, iclass 40, count 0 2006.169.08:04:39.53#ibcon#about to read 4, iclass 40, count 0 2006.169.08:04:39.53#ibcon#read 4, iclass 40, count 0 2006.169.08:04:39.53#ibcon#about to read 5, iclass 40, count 0 2006.169.08:04:39.53#ibcon#read 5, iclass 40, count 0 2006.169.08:04:39.53#ibcon#about to read 6, iclass 40, count 0 2006.169.08:04:39.53#ibcon#read 6, iclass 40, count 0 2006.169.08:04:39.53#ibcon#end of sib2, iclass 40, count 0 2006.169.08:04:39.53#ibcon#*after write, iclass 40, count 0 2006.169.08:04:39.53#ibcon#*before return 0, iclass 40, count 0 2006.169.08:04:39.53#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:04:39.53#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:04:39.53#ibcon#about to clear, iclass 40 cls_cnt 0 2006.169.08:04:39.53#ibcon#cleared, iclass 40 cls_cnt 0 2006.169.08:04:39.53$vc4f8/vbbw=wide 2006.169.08:04:39.53#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.169.08:04:39.53#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.169.08:04:39.53#ibcon#ireg 8 cls_cnt 0 2006.169.08:04:39.53#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:04:39.60#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:04:39.60#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:04:39.60#ibcon#enter wrdev, iclass 4, count 0 2006.169.08:04:39.60#ibcon#first serial, iclass 4, count 0 2006.169.08:04:39.60#ibcon#enter sib2, iclass 4, count 0 2006.169.08:04:39.60#ibcon#flushed, iclass 4, count 0 2006.169.08:04:39.60#ibcon#about to write, iclass 4, count 0 2006.169.08:04:39.60#ibcon#wrote, iclass 4, count 0 2006.169.08:04:39.60#ibcon#about to read 3, iclass 4, count 0 2006.169.08:04:39.62#ibcon#read 3, iclass 4, count 0 2006.169.08:04:39.62#ibcon#about to read 4, iclass 4, count 0 2006.169.08:04:39.62#ibcon#read 4, iclass 4, count 0 2006.169.08:04:39.62#ibcon#about to read 5, iclass 4, count 0 2006.169.08:04:39.62#ibcon#read 5, iclass 4, count 0 2006.169.08:04:39.62#ibcon#about to read 6, iclass 4, count 0 2006.169.08:04:39.62#ibcon#read 6, iclass 4, count 0 2006.169.08:04:39.62#ibcon#end of sib2, iclass 4, count 0 2006.169.08:04:39.62#ibcon#*mode == 0, iclass 4, count 0 2006.169.08:04:39.62#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.169.08:04:39.62#ibcon#[27=BW32\r\n] 2006.169.08:04:39.62#ibcon#*before write, iclass 4, count 0 2006.169.08:04:39.62#ibcon#enter sib2, iclass 4, count 0 2006.169.08:04:39.62#ibcon#flushed, iclass 4, count 0 2006.169.08:04:39.62#ibcon#about to write, iclass 4, count 0 2006.169.08:04:39.62#ibcon#wrote, iclass 4, count 0 2006.169.08:04:39.62#ibcon#about to read 3, iclass 4, count 0 2006.169.08:04:39.65#ibcon#read 3, iclass 4, count 0 2006.169.08:04:39.65#ibcon#about to read 4, iclass 4, count 0 2006.169.08:04:39.65#ibcon#read 4, iclass 4, count 0 2006.169.08:04:39.65#ibcon#about to read 5, iclass 4, count 0 2006.169.08:04:39.65#ibcon#read 5, iclass 4, count 0 2006.169.08:04:39.65#ibcon#about to read 6, iclass 4, count 0 2006.169.08:04:39.65#ibcon#read 6, iclass 4, count 0 2006.169.08:04:39.65#ibcon#end of sib2, iclass 4, count 0 2006.169.08:04:39.65#ibcon#*after write, iclass 4, count 0 2006.169.08:04:39.65#ibcon#*before return 0, iclass 4, count 0 2006.169.08:04:39.65#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:04:39.65#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:04:39.65#ibcon#about to clear, iclass 4 cls_cnt 0 2006.169.08:04:39.65#ibcon#cleared, iclass 4 cls_cnt 0 2006.169.08:04:39.65$4f8m12a/ifd4f 2006.169.08:04:39.65$ifd4f/lo= 2006.169.08:04:39.65$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.08:04:39.65$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.08:04:39.65$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.08:04:39.65$ifd4f/patch= 2006.169.08:04:39.65$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.08:04:39.65$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.08:04:39.65$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.08:04:39.65$4f8m12a/"form=m,16.000,1:2 2006.169.08:04:39.65$4f8m12a/"tpicd 2006.169.08:04:39.65$4f8m12a/echo=off 2006.169.08:04:39.65$4f8m12a/xlog=off 2006.169.08:04:39.65:!2006.169.08:04:50 2006.169.08:04:50.00:preob 2006.169.08:04:51.14/onsource/TRACKING 2006.169.08:04:51.14:!2006.169.08:05:00 2006.169.08:05:00.00:data_valid=on 2006.169.08:05:00.00:midob 2006.169.08:05:00.14/onsource/TRACKING 2006.169.08:05:00.14/wx/18.12,1003.9,100 2006.169.08:05:00.22/cable/+6.5298E-03 2006.169.08:05:01.31/va/01,08,usb,yes,45,47 2006.169.08:05:01.31/va/02,07,usb,yes,45,47 2006.169.08:05:01.31/va/03,06,usb,yes,48,48 2006.169.08:05:01.31/va/04,07,usb,yes,47,50 2006.169.08:05:01.31/va/05,07,usb,yes,51,54 2006.169.08:05:01.31/va/06,06,usb,yes,50,50 2006.169.08:05:01.31/va/07,06,usb,yes,51,51 2006.169.08:05:01.31/va/08,07,usb,yes,48,48 2006.169.08:05:01.54/valo/01,532.99,yes,locked 2006.169.08:05:01.54/valo/02,572.99,yes,locked 2006.169.08:05:01.54/valo/03,672.99,yes,locked 2006.169.08:05:01.54/valo/04,832.99,yes,locked 2006.169.08:05:01.54/valo/05,652.99,yes,locked 2006.169.08:05:01.54/valo/06,772.99,yes,locked 2006.169.08:05:01.54/valo/07,832.99,yes,locked 2006.169.08:05:01.54/valo/08,852.99,yes,locked 2006.169.08:05:02.63/vb/01,04,usb,yes,30,28 2006.169.08:05:02.63/vb/02,04,usb,yes,31,33 2006.169.08:05:02.63/vb/03,04,usb,yes,28,32 2006.169.08:05:02.63/vb/04,04,usb,yes,29,29 2006.169.08:05:02.63/vb/05,04,usb,yes,27,31 2006.169.08:05:02.63/vb/06,04,usb,yes,28,31 2006.169.08:05:02.63/vb/07,04,usb,yes,30,30 2006.169.08:05:02.63/vb/08,04,usb,yes,28,31 2006.169.08:05:02.86/vblo/01,632.99,yes,locked 2006.169.08:05:02.86/vblo/02,640.99,yes,locked 2006.169.08:05:02.86/vblo/03,656.99,yes,locked 2006.169.08:05:02.86/vblo/04,712.99,yes,locked 2006.169.08:05:02.86/vblo/05,744.99,yes,locked 2006.169.08:05:02.86/vblo/06,752.99,yes,locked 2006.169.08:05:02.86/vblo/07,734.99,yes,locked 2006.169.08:05:02.86/vblo/08,744.99,yes,locked 2006.169.08:05:03.01/vabw/8 2006.169.08:05:03.16/vbbw/8 2006.169.08:05:03.31/xfe/off,on,14.2 2006.169.08:05:03.70/ifatt/23,28,28,28 2006.169.08:05:04.07/fmout-gps/S +4.18E-07 2006.169.08:05:04.15:!2006.169.08:06:00 2006.169.08:06:00.00:data_valid=off 2006.169.08:06:00.00:postob 2006.169.08:06:00.16/cable/+6.5290E-03 2006.169.08:06:00.16/wx/18.12,1003.9,100 2006.169.08:06:01.07/fmout-gps/S +4.18E-07 2006.169.08:06:01.07:scan_name=169-0806,k06169,60 2006.169.08:06:01.08:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.169.08:06:01.14#flagr#flagr/antenna,new-source 2006.169.08:06:02.14:checkk5 2006.169.08:06:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.169.08:06:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.169.08:06:06.91/chk_autoobs//k5ts3?ERROR: timeout happened! 2006.169.08:06:07.29/chk_autoobs//k5ts4/ autoobs is running! 2006.169.08:06:07.66/chk_obsdata//k5ts1/T1690805??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.169.08:06:08.03/chk_obsdata//k5ts2/T1690805??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.169.08:06:15.10/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.08:06:15.47/chk_obsdata//k5ts4/T1690805??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.169.08:06:16.16/k5log//k5ts1_log_newline 2006.169.08:06:16.85/k5log//k5ts2_log_newline 2006.169.08:06:23.95/k5log//k5ts3?ERROR: timeout happened! 2006.169.08:06:24.64/k5log//k5ts4_log_newline 2006.169.08:06:24.82/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.08:06:24.82:4f8m12a=2 2006.169.08:06:24.83$4f8m12a/echo=on 2006.169.08:06:24.83$4f8m12a/pcalon 2006.169.08:06:24.83$pcalon/"no phase cal control is implemented here 2006.169.08:06:24.83$4f8m12a/"tpicd=stop 2006.169.08:06:24.83$4f8m12a/vc4f8 2006.169.08:06:24.83$vc4f8/valo=1,532.99 2006.169.08:06:24.83#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.169.08:06:24.83#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.169.08:06:24.83#ibcon#ireg 17 cls_cnt 0 2006.169.08:06:24.83#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:06:24.83#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:06:24.83#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:06:24.83#ibcon#enter wrdev, iclass 17, count 0 2006.169.08:06:24.83#ibcon#first serial, iclass 17, count 0 2006.169.08:06:24.83#ibcon#enter sib2, iclass 17, count 0 2006.169.08:06:24.83#ibcon#flushed, iclass 17, count 0 2006.169.08:06:24.83#ibcon#about to write, iclass 17, count 0 2006.169.08:06:24.83#ibcon#wrote, iclass 17, count 0 2006.169.08:06:24.83#ibcon#about to read 3, iclass 17, count 0 2006.169.08:06:24.85#ibcon#read 3, iclass 17, count 0 2006.169.08:06:24.85#ibcon#about to read 4, iclass 17, count 0 2006.169.08:06:24.85#ibcon#read 4, iclass 17, count 0 2006.169.08:06:24.85#ibcon#about to read 5, iclass 17, count 0 2006.169.08:06:24.85#ibcon#read 5, iclass 17, count 0 2006.169.08:06:24.85#ibcon#about to read 6, iclass 17, count 0 2006.169.08:06:24.85#ibcon#read 6, iclass 17, count 0 2006.169.08:06:24.85#ibcon#end of sib2, iclass 17, count 0 2006.169.08:06:24.85#ibcon#*mode == 0, iclass 17, count 0 2006.169.08:06:24.85#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.169.08:06:24.85#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.08:06:24.85#ibcon#*before write, iclass 17, count 0 2006.169.08:06:24.85#ibcon#enter sib2, iclass 17, count 0 2006.169.08:06:24.85#ibcon#flushed, iclass 17, count 0 2006.169.08:06:24.85#ibcon#about to write, iclass 17, count 0 2006.169.08:06:24.85#ibcon#wrote, iclass 17, count 0 2006.169.08:06:24.85#ibcon#about to read 3, iclass 17, count 0 2006.169.08:06:24.90#ibcon#read 3, iclass 17, count 0 2006.169.08:06:24.90#ibcon#about to read 4, iclass 17, count 0 2006.169.08:06:24.90#ibcon#read 4, iclass 17, count 0 2006.169.08:06:24.90#ibcon#about to read 5, iclass 17, count 0 2006.169.08:06:24.90#ibcon#read 5, iclass 17, count 0 2006.169.08:06:24.90#ibcon#about to read 6, iclass 17, count 0 2006.169.08:06:24.90#ibcon#read 6, iclass 17, count 0 2006.169.08:06:24.90#ibcon#end of sib2, iclass 17, count 0 2006.169.08:06:24.90#ibcon#*after write, iclass 17, count 0 2006.169.08:06:24.90#ibcon#*before return 0, iclass 17, count 0 2006.169.08:06:24.90#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:06:24.90#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:06:24.90#ibcon#about to clear, iclass 17 cls_cnt 0 2006.169.08:06:24.90#ibcon#cleared, iclass 17 cls_cnt 0 2006.169.08:06:24.90$vc4f8/va=1,8 2006.169.08:06:24.90#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.169.08:06:24.90#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.169.08:06:24.90#ibcon#ireg 11 cls_cnt 2 2006.169.08:06:24.90#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.169.08:06:24.90#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.169.08:06:24.90#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.169.08:06:24.90#ibcon#enter wrdev, iclass 19, count 2 2006.169.08:06:24.90#ibcon#first serial, iclass 19, count 2 2006.169.08:06:24.90#ibcon#enter sib2, iclass 19, count 2 2006.169.08:06:24.90#ibcon#flushed, iclass 19, count 2 2006.169.08:06:24.90#ibcon#about to write, iclass 19, count 2 2006.169.08:06:24.90#ibcon#wrote, iclass 19, count 2 2006.169.08:06:24.90#ibcon#about to read 3, iclass 19, count 2 2006.169.08:06:24.92#ibcon#read 3, iclass 19, count 2 2006.169.08:06:24.92#ibcon#about to read 4, iclass 19, count 2 2006.169.08:06:24.92#ibcon#read 4, iclass 19, count 2 2006.169.08:06:24.92#ibcon#about to read 5, iclass 19, count 2 2006.169.08:06:24.92#ibcon#read 5, iclass 19, count 2 2006.169.08:06:24.92#ibcon#about to read 6, iclass 19, count 2 2006.169.08:06:24.92#ibcon#read 6, iclass 19, count 2 2006.169.08:06:24.92#ibcon#end of sib2, iclass 19, count 2 2006.169.08:06:24.92#ibcon#*mode == 0, iclass 19, count 2 2006.169.08:06:24.92#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.169.08:06:24.92#ibcon#[25=AT01-08\r\n] 2006.169.08:06:24.92#ibcon#*before write, iclass 19, count 2 2006.169.08:06:24.92#ibcon#enter sib2, iclass 19, count 2 2006.169.08:06:24.92#ibcon#flushed, iclass 19, count 2 2006.169.08:06:24.92#ibcon#about to write, iclass 19, count 2 2006.169.08:06:24.92#ibcon#wrote, iclass 19, count 2 2006.169.08:06:24.92#ibcon#about to read 3, iclass 19, count 2 2006.169.08:06:24.95#ibcon#read 3, iclass 19, count 2 2006.169.08:06:24.95#ibcon#about to read 4, iclass 19, count 2 2006.169.08:06:24.95#ibcon#read 4, iclass 19, count 2 2006.169.08:06:24.95#ibcon#about to read 5, iclass 19, count 2 2006.169.08:06:24.95#ibcon#read 5, iclass 19, count 2 2006.169.08:06:24.95#ibcon#about to read 6, iclass 19, count 2 2006.169.08:06:24.95#ibcon#read 6, iclass 19, count 2 2006.169.08:06:24.95#ibcon#end of sib2, iclass 19, count 2 2006.169.08:06:24.95#ibcon#*after write, iclass 19, count 2 2006.169.08:06:24.95#ibcon#*before return 0, iclass 19, count 2 2006.169.08:06:24.95#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.169.08:06:24.95#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.169.08:06:24.95#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.169.08:06:24.95#ibcon#ireg 7 cls_cnt 0 2006.169.08:06:24.95#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.169.08:06:25.07#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.169.08:06:25.07#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.169.08:06:25.07#ibcon#enter wrdev, iclass 19, count 0 2006.169.08:06:25.07#ibcon#first serial, iclass 19, count 0 2006.169.08:06:25.07#ibcon#enter sib2, iclass 19, count 0 2006.169.08:06:25.07#ibcon#flushed, iclass 19, count 0 2006.169.08:06:25.07#ibcon#about to write, iclass 19, count 0 2006.169.08:06:25.07#ibcon#wrote, iclass 19, count 0 2006.169.08:06:25.07#ibcon#about to read 3, iclass 19, count 0 2006.169.08:06:25.10#ibcon#read 3, iclass 19, count 0 2006.169.08:06:25.10#ibcon#about to read 4, iclass 19, count 0 2006.169.08:06:25.10#ibcon#read 4, iclass 19, count 0 2006.169.08:06:25.10#ibcon#about to read 5, iclass 19, count 0 2006.169.08:06:25.10#ibcon#read 5, iclass 19, count 0 2006.169.08:06:25.10#ibcon#about to read 6, iclass 19, count 0 2006.169.08:06:25.10#ibcon#read 6, iclass 19, count 0 2006.169.08:06:25.10#ibcon#end of sib2, iclass 19, count 0 2006.169.08:06:25.10#ibcon#*mode == 0, iclass 19, count 0 2006.169.08:06:25.10#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.169.08:06:25.11#ibcon#[25=USB\r\n] 2006.169.08:06:25.11#ibcon#*before write, iclass 19, count 0 2006.169.08:06:25.11#ibcon#enter sib2, iclass 19, count 0 2006.169.08:06:25.11#ibcon#flushed, iclass 19, count 0 2006.169.08:06:25.11#ibcon#about to write, iclass 19, count 0 2006.169.08:06:25.11#ibcon#wrote, iclass 19, count 0 2006.169.08:06:25.11#ibcon#about to read 3, iclass 19, count 0 2006.169.08:06:25.14#ibcon#read 3, iclass 19, count 0 2006.169.08:06:25.14#ibcon#about to read 4, iclass 19, count 0 2006.169.08:06:25.14#ibcon#read 4, iclass 19, count 0 2006.169.08:06:25.14#ibcon#about to read 5, iclass 19, count 0 2006.169.08:06:25.14#ibcon#read 5, iclass 19, count 0 2006.169.08:06:25.14#ibcon#about to read 6, iclass 19, count 0 2006.169.08:06:25.14#ibcon#read 6, iclass 19, count 0 2006.169.08:06:25.14#ibcon#end of sib2, iclass 19, count 0 2006.169.08:06:25.14#ibcon#*after write, iclass 19, count 0 2006.169.08:06:25.14#ibcon#*before return 0, iclass 19, count 0 2006.169.08:06:25.14#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.169.08:06:25.14#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.169.08:06:25.14#ibcon#about to clear, iclass 19 cls_cnt 0 2006.169.08:06:25.14#ibcon#cleared, iclass 19 cls_cnt 0 2006.169.08:06:25.14$vc4f8/valo=2,572.99 2006.169.08:06:25.14#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.169.08:06:25.14#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.169.08:06:25.14#ibcon#ireg 17 cls_cnt 0 2006.169.08:06:25.14#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.169.08:06:25.14#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.169.08:06:25.14#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.169.08:06:25.14#ibcon#enter wrdev, iclass 21, count 0 2006.169.08:06:25.14#ibcon#first serial, iclass 21, count 0 2006.169.08:06:25.14#ibcon#enter sib2, iclass 21, count 0 2006.169.08:06:25.14#ibcon#flushed, iclass 21, count 0 2006.169.08:06:25.14#ibcon#about to write, iclass 21, count 0 2006.169.08:06:25.14#ibcon#wrote, iclass 21, count 0 2006.169.08:06:25.14#ibcon#about to read 3, iclass 21, count 0 2006.169.08:06:25.14#trakl#Source acquired 2006.169.08:06:25.14#flagr#flagr/antenna,acquired 2006.169.08:06:25.16#ibcon#read 3, iclass 21, count 0 2006.169.08:06:25.16#ibcon#about to read 4, iclass 21, count 0 2006.169.08:06:25.16#ibcon#read 4, iclass 21, count 0 2006.169.08:06:25.16#ibcon#about to read 5, iclass 21, count 0 2006.169.08:06:25.16#ibcon#read 5, iclass 21, count 0 2006.169.08:06:25.16#ibcon#about to read 6, iclass 21, count 0 2006.169.08:06:25.16#ibcon#read 6, iclass 21, count 0 2006.169.08:06:25.16#ibcon#end of sib2, iclass 21, count 0 2006.169.08:06:25.16#ibcon#*mode == 0, iclass 21, count 0 2006.169.08:06:25.16#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.169.08:06:25.16#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.08:06:25.16#ibcon#*before write, iclass 21, count 0 2006.169.08:06:25.16#ibcon#enter sib2, iclass 21, count 0 2006.169.08:06:25.16#ibcon#flushed, iclass 21, count 0 2006.169.08:06:25.16#ibcon#about to write, iclass 21, count 0 2006.169.08:06:25.16#ibcon#wrote, iclass 21, count 0 2006.169.08:06:25.16#ibcon#about to read 3, iclass 21, count 0 2006.169.08:06:25.20#ibcon#read 3, iclass 21, count 0 2006.169.08:06:25.20#ibcon#about to read 4, iclass 21, count 0 2006.169.08:06:25.20#ibcon#read 4, iclass 21, count 0 2006.169.08:06:25.20#ibcon#about to read 5, iclass 21, count 0 2006.169.08:06:25.20#ibcon#read 5, iclass 21, count 0 2006.169.08:06:25.20#ibcon#about to read 6, iclass 21, count 0 2006.169.08:06:25.20#ibcon#read 6, iclass 21, count 0 2006.169.08:06:25.20#ibcon#end of sib2, iclass 21, count 0 2006.169.08:06:25.20#ibcon#*after write, iclass 21, count 0 2006.169.08:06:25.20#ibcon#*before return 0, iclass 21, count 0 2006.169.08:06:25.20#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.169.08:06:25.20#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.169.08:06:25.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.169.08:06:25.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.169.08:06:25.20$vc4f8/va=2,7 2006.169.08:06:25.20#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.169.08:06:25.20#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.169.08:06:25.20#ibcon#ireg 11 cls_cnt 2 2006.169.08:06:25.20#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.169.08:06:25.26#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.169.08:06:25.26#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.169.08:06:25.26#ibcon#enter wrdev, iclass 23, count 2 2006.169.08:06:25.26#ibcon#first serial, iclass 23, count 2 2006.169.08:06:25.26#ibcon#enter sib2, iclass 23, count 2 2006.169.08:06:25.26#ibcon#flushed, iclass 23, count 2 2006.169.08:06:25.26#ibcon#about to write, iclass 23, count 2 2006.169.08:06:25.26#ibcon#wrote, iclass 23, count 2 2006.169.08:06:25.26#ibcon#about to read 3, iclass 23, count 2 2006.169.08:06:25.28#ibcon#read 3, iclass 23, count 2 2006.169.08:06:25.28#ibcon#about to read 4, iclass 23, count 2 2006.169.08:06:25.28#ibcon#read 4, iclass 23, count 2 2006.169.08:06:25.28#ibcon#about to read 5, iclass 23, count 2 2006.169.08:06:25.28#ibcon#read 5, iclass 23, count 2 2006.169.08:06:25.28#ibcon#about to read 6, iclass 23, count 2 2006.169.08:06:25.28#ibcon#read 6, iclass 23, count 2 2006.169.08:06:25.28#ibcon#end of sib2, iclass 23, count 2 2006.169.08:06:25.28#ibcon#*mode == 0, iclass 23, count 2 2006.169.08:06:25.28#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.169.08:06:25.28#ibcon#[25=AT02-07\r\n] 2006.169.08:06:25.28#ibcon#*before write, iclass 23, count 2 2006.169.08:06:25.28#ibcon#enter sib2, iclass 23, count 2 2006.169.08:06:25.28#ibcon#flushed, iclass 23, count 2 2006.169.08:06:25.28#ibcon#about to write, iclass 23, count 2 2006.169.08:06:25.28#ibcon#wrote, iclass 23, count 2 2006.169.08:06:25.28#ibcon#about to read 3, iclass 23, count 2 2006.169.08:06:25.32#ibcon#read 3, iclass 23, count 2 2006.169.08:06:25.32#ibcon#about to read 4, iclass 23, count 2 2006.169.08:06:25.32#ibcon#read 4, iclass 23, count 2 2006.169.08:06:25.32#ibcon#about to read 5, iclass 23, count 2 2006.169.08:06:25.32#ibcon#read 5, iclass 23, count 2 2006.169.08:06:25.32#ibcon#about to read 6, iclass 23, count 2 2006.169.08:06:25.32#ibcon#read 6, iclass 23, count 2 2006.169.08:06:25.32#ibcon#end of sib2, iclass 23, count 2 2006.169.08:06:25.32#ibcon#*after write, iclass 23, count 2 2006.169.08:06:25.32#ibcon#*before return 0, iclass 23, count 2 2006.169.08:06:25.32#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.169.08:06:25.32#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.169.08:06:25.32#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.169.08:06:25.32#ibcon#ireg 7 cls_cnt 0 2006.169.08:06:25.32#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.169.08:06:25.44#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.169.08:06:25.44#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.169.08:06:25.44#ibcon#enter wrdev, iclass 23, count 0 2006.169.08:06:25.44#ibcon#first serial, iclass 23, count 0 2006.169.08:06:25.44#ibcon#enter sib2, iclass 23, count 0 2006.169.08:06:25.44#ibcon#flushed, iclass 23, count 0 2006.169.08:06:25.44#ibcon#about to write, iclass 23, count 0 2006.169.08:06:25.44#ibcon#wrote, iclass 23, count 0 2006.169.08:06:25.44#ibcon#about to read 3, iclass 23, count 0 2006.169.08:06:25.46#ibcon#read 3, iclass 23, count 0 2006.169.08:06:25.46#ibcon#about to read 4, iclass 23, count 0 2006.169.08:06:25.46#ibcon#read 4, iclass 23, count 0 2006.169.08:06:25.46#ibcon#about to read 5, iclass 23, count 0 2006.169.08:06:25.46#ibcon#read 5, iclass 23, count 0 2006.169.08:06:25.46#ibcon#about to read 6, iclass 23, count 0 2006.169.08:06:25.46#ibcon#read 6, iclass 23, count 0 2006.169.08:06:25.46#ibcon#end of sib2, iclass 23, count 0 2006.169.08:06:25.46#ibcon#*mode == 0, iclass 23, count 0 2006.169.08:06:25.46#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.169.08:06:25.46#ibcon#[25=USB\r\n] 2006.169.08:06:25.46#ibcon#*before write, iclass 23, count 0 2006.169.08:06:25.46#ibcon#enter sib2, iclass 23, count 0 2006.169.08:06:25.46#ibcon#flushed, iclass 23, count 0 2006.169.08:06:25.46#ibcon#about to write, iclass 23, count 0 2006.169.08:06:25.46#ibcon#wrote, iclass 23, count 0 2006.169.08:06:25.46#ibcon#about to read 3, iclass 23, count 0 2006.169.08:06:25.49#ibcon#read 3, iclass 23, count 0 2006.169.08:06:25.49#ibcon#about to read 4, iclass 23, count 0 2006.169.08:06:25.49#ibcon#read 4, iclass 23, count 0 2006.169.08:06:25.49#ibcon#about to read 5, iclass 23, count 0 2006.169.08:06:25.49#ibcon#read 5, iclass 23, count 0 2006.169.08:06:25.49#ibcon#about to read 6, iclass 23, count 0 2006.169.08:06:25.49#ibcon#read 6, iclass 23, count 0 2006.169.08:06:25.49#ibcon#end of sib2, iclass 23, count 0 2006.169.08:06:25.49#ibcon#*after write, iclass 23, count 0 2006.169.08:06:25.49#ibcon#*before return 0, iclass 23, count 0 2006.169.08:06:25.49#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.169.08:06:25.49#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.169.08:06:25.49#ibcon#about to clear, iclass 23 cls_cnt 0 2006.169.08:06:25.49#ibcon#cleared, iclass 23 cls_cnt 0 2006.169.08:06:25.49$vc4f8/valo=3,672.99 2006.169.08:06:25.49#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.169.08:06:25.49#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.169.08:06:25.49#ibcon#ireg 17 cls_cnt 0 2006.169.08:06:25.49#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.169.08:06:25.49#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.169.08:06:25.49#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.169.08:06:25.49#ibcon#enter wrdev, iclass 25, count 0 2006.169.08:06:25.49#ibcon#first serial, iclass 25, count 0 2006.169.08:06:25.49#ibcon#enter sib2, iclass 25, count 0 2006.169.08:06:25.49#ibcon#flushed, iclass 25, count 0 2006.169.08:06:25.49#ibcon#about to write, iclass 25, count 0 2006.169.08:06:25.49#ibcon#wrote, iclass 25, count 0 2006.169.08:06:25.49#ibcon#about to read 3, iclass 25, count 0 2006.169.08:06:25.51#ibcon#read 3, iclass 25, count 0 2006.169.08:06:25.51#ibcon#about to read 4, iclass 25, count 0 2006.169.08:06:25.51#ibcon#read 4, iclass 25, count 0 2006.169.08:06:25.51#ibcon#about to read 5, iclass 25, count 0 2006.169.08:06:25.51#ibcon#read 5, iclass 25, count 0 2006.169.08:06:25.51#ibcon#about to read 6, iclass 25, count 0 2006.169.08:06:25.51#ibcon#read 6, iclass 25, count 0 2006.169.08:06:25.51#ibcon#end of sib2, iclass 25, count 0 2006.169.08:06:25.51#ibcon#*mode == 0, iclass 25, count 0 2006.169.08:06:25.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.169.08:06:25.51#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.08:06:25.51#ibcon#*before write, iclass 25, count 0 2006.169.08:06:25.51#ibcon#enter sib2, iclass 25, count 0 2006.169.08:06:25.51#ibcon#flushed, iclass 25, count 0 2006.169.08:06:25.51#ibcon#about to write, iclass 25, count 0 2006.169.08:06:25.51#ibcon#wrote, iclass 25, count 0 2006.169.08:06:25.51#ibcon#about to read 3, iclass 25, count 0 2006.169.08:06:25.55#ibcon#read 3, iclass 25, count 0 2006.169.08:06:25.55#ibcon#about to read 4, iclass 25, count 0 2006.169.08:06:25.55#ibcon#read 4, iclass 25, count 0 2006.169.08:06:25.55#ibcon#about to read 5, iclass 25, count 0 2006.169.08:06:25.55#ibcon#read 5, iclass 25, count 0 2006.169.08:06:25.55#ibcon#about to read 6, iclass 25, count 0 2006.169.08:06:25.55#ibcon#read 6, iclass 25, count 0 2006.169.08:06:25.55#ibcon#end of sib2, iclass 25, count 0 2006.169.08:06:25.55#ibcon#*after write, iclass 25, count 0 2006.169.08:06:25.55#ibcon#*before return 0, iclass 25, count 0 2006.169.08:06:25.55#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.169.08:06:25.55#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.169.08:06:25.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.169.08:06:25.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.169.08:06:25.55$vc4f8/va=3,6 2006.169.08:06:25.55#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.169.08:06:25.55#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.169.08:06:25.55#ibcon#ireg 11 cls_cnt 2 2006.169.08:06:25.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.169.08:06:25.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.169.08:06:25.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.169.08:06:25.61#ibcon#enter wrdev, iclass 27, count 2 2006.169.08:06:25.61#ibcon#first serial, iclass 27, count 2 2006.169.08:06:25.61#ibcon#enter sib2, iclass 27, count 2 2006.169.08:06:25.61#ibcon#flushed, iclass 27, count 2 2006.169.08:06:25.61#ibcon#about to write, iclass 27, count 2 2006.169.08:06:25.61#ibcon#wrote, iclass 27, count 2 2006.169.08:06:25.61#ibcon#about to read 3, iclass 27, count 2 2006.169.08:06:25.63#ibcon#read 3, iclass 27, count 2 2006.169.08:06:25.63#ibcon#about to read 4, iclass 27, count 2 2006.169.08:06:25.63#ibcon#read 4, iclass 27, count 2 2006.169.08:06:25.63#ibcon#about to read 5, iclass 27, count 2 2006.169.08:06:25.63#ibcon#read 5, iclass 27, count 2 2006.169.08:06:25.63#ibcon#about to read 6, iclass 27, count 2 2006.169.08:06:25.63#ibcon#read 6, iclass 27, count 2 2006.169.08:06:25.63#ibcon#end of sib2, iclass 27, count 2 2006.169.08:06:25.63#ibcon#*mode == 0, iclass 27, count 2 2006.169.08:06:25.63#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.169.08:06:25.63#ibcon#[25=AT03-06\r\n] 2006.169.08:06:25.63#ibcon#*before write, iclass 27, count 2 2006.169.08:06:25.63#ibcon#enter sib2, iclass 27, count 2 2006.169.08:06:25.63#ibcon#flushed, iclass 27, count 2 2006.169.08:06:25.63#ibcon#about to write, iclass 27, count 2 2006.169.08:06:25.63#ibcon#wrote, iclass 27, count 2 2006.169.08:06:25.63#ibcon#about to read 3, iclass 27, count 2 2006.169.08:06:25.66#ibcon#read 3, iclass 27, count 2 2006.169.08:06:25.66#ibcon#about to read 4, iclass 27, count 2 2006.169.08:06:25.66#ibcon#read 4, iclass 27, count 2 2006.169.08:06:25.66#ibcon#about to read 5, iclass 27, count 2 2006.169.08:06:25.66#ibcon#read 5, iclass 27, count 2 2006.169.08:06:25.66#ibcon#about to read 6, iclass 27, count 2 2006.169.08:06:25.66#ibcon#read 6, iclass 27, count 2 2006.169.08:06:25.66#ibcon#end of sib2, iclass 27, count 2 2006.169.08:06:25.66#ibcon#*after write, iclass 27, count 2 2006.169.08:06:25.66#ibcon#*before return 0, iclass 27, count 2 2006.169.08:06:25.66#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.169.08:06:25.66#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.169.08:06:25.66#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.169.08:06:25.66#ibcon#ireg 7 cls_cnt 0 2006.169.08:06:25.66#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.169.08:06:25.78#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.169.08:06:25.78#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.169.08:06:25.78#ibcon#enter wrdev, iclass 27, count 0 2006.169.08:06:25.78#ibcon#first serial, iclass 27, count 0 2006.169.08:06:25.78#ibcon#enter sib2, iclass 27, count 0 2006.169.08:06:25.78#ibcon#flushed, iclass 27, count 0 2006.169.08:06:25.78#ibcon#about to write, iclass 27, count 0 2006.169.08:06:25.78#ibcon#wrote, iclass 27, count 0 2006.169.08:06:25.78#ibcon#about to read 3, iclass 27, count 0 2006.169.08:06:25.80#ibcon#read 3, iclass 27, count 0 2006.169.08:06:25.80#ibcon#about to read 4, iclass 27, count 0 2006.169.08:06:25.80#ibcon#read 4, iclass 27, count 0 2006.169.08:06:25.80#ibcon#about to read 5, iclass 27, count 0 2006.169.08:06:25.80#ibcon#read 5, iclass 27, count 0 2006.169.08:06:25.80#ibcon#about to read 6, iclass 27, count 0 2006.169.08:06:25.80#ibcon#read 6, iclass 27, count 0 2006.169.08:06:25.80#ibcon#end of sib2, iclass 27, count 0 2006.169.08:06:25.80#ibcon#*mode == 0, iclass 27, count 0 2006.169.08:06:25.80#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.169.08:06:25.80#ibcon#[25=USB\r\n] 2006.169.08:06:25.80#ibcon#*before write, iclass 27, count 0 2006.169.08:06:25.80#ibcon#enter sib2, iclass 27, count 0 2006.169.08:06:25.80#ibcon#flushed, iclass 27, count 0 2006.169.08:06:25.80#ibcon#about to write, iclass 27, count 0 2006.169.08:06:25.80#ibcon#wrote, iclass 27, count 0 2006.169.08:06:25.80#ibcon#about to read 3, iclass 27, count 0 2006.169.08:06:25.83#ibcon#read 3, iclass 27, count 0 2006.169.08:06:25.83#ibcon#about to read 4, iclass 27, count 0 2006.169.08:06:25.83#ibcon#read 4, iclass 27, count 0 2006.169.08:06:25.83#ibcon#about to read 5, iclass 27, count 0 2006.169.08:06:25.83#ibcon#read 5, iclass 27, count 0 2006.169.08:06:25.83#ibcon#about to read 6, iclass 27, count 0 2006.169.08:06:25.83#ibcon#read 6, iclass 27, count 0 2006.169.08:06:25.83#ibcon#end of sib2, iclass 27, count 0 2006.169.08:06:25.83#ibcon#*after write, iclass 27, count 0 2006.169.08:06:25.83#ibcon#*before return 0, iclass 27, count 0 2006.169.08:06:25.83#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.169.08:06:25.83#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.169.08:06:25.83#ibcon#about to clear, iclass 27 cls_cnt 0 2006.169.08:06:25.83#ibcon#cleared, iclass 27 cls_cnt 0 2006.169.08:06:25.83$vc4f8/valo=4,832.99 2006.169.08:06:25.83#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.169.08:06:25.83#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.169.08:06:25.83#ibcon#ireg 17 cls_cnt 0 2006.169.08:06:25.83#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.169.08:06:25.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.169.08:06:25.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.169.08:06:25.83#ibcon#enter wrdev, iclass 29, count 0 2006.169.08:06:25.83#ibcon#first serial, iclass 29, count 0 2006.169.08:06:25.83#ibcon#enter sib2, iclass 29, count 0 2006.169.08:06:25.83#ibcon#flushed, iclass 29, count 0 2006.169.08:06:25.83#ibcon#about to write, iclass 29, count 0 2006.169.08:06:25.83#ibcon#wrote, iclass 29, count 0 2006.169.08:06:25.83#ibcon#about to read 3, iclass 29, count 0 2006.169.08:06:25.85#ibcon#read 3, iclass 29, count 0 2006.169.08:06:25.85#ibcon#about to read 4, iclass 29, count 0 2006.169.08:06:25.85#ibcon#read 4, iclass 29, count 0 2006.169.08:06:25.85#ibcon#about to read 5, iclass 29, count 0 2006.169.08:06:25.85#ibcon#read 5, iclass 29, count 0 2006.169.08:06:25.85#ibcon#about to read 6, iclass 29, count 0 2006.169.08:06:25.85#ibcon#read 6, iclass 29, count 0 2006.169.08:06:25.85#ibcon#end of sib2, iclass 29, count 0 2006.169.08:06:25.85#ibcon#*mode == 0, iclass 29, count 0 2006.169.08:06:25.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.169.08:06:25.85#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.08:06:25.85#ibcon#*before write, iclass 29, count 0 2006.169.08:06:25.85#ibcon#enter sib2, iclass 29, count 0 2006.169.08:06:25.85#ibcon#flushed, iclass 29, count 0 2006.169.08:06:25.85#ibcon#about to write, iclass 29, count 0 2006.169.08:06:25.85#ibcon#wrote, iclass 29, count 0 2006.169.08:06:25.85#ibcon#about to read 3, iclass 29, count 0 2006.169.08:06:25.89#ibcon#read 3, iclass 29, count 0 2006.169.08:06:25.89#ibcon#about to read 4, iclass 29, count 0 2006.169.08:06:25.89#ibcon#read 4, iclass 29, count 0 2006.169.08:06:25.89#ibcon#about to read 5, iclass 29, count 0 2006.169.08:06:25.89#ibcon#read 5, iclass 29, count 0 2006.169.08:06:25.89#ibcon#about to read 6, iclass 29, count 0 2006.169.08:06:25.89#ibcon#read 6, iclass 29, count 0 2006.169.08:06:25.89#ibcon#end of sib2, iclass 29, count 0 2006.169.08:06:25.89#ibcon#*after write, iclass 29, count 0 2006.169.08:06:25.89#ibcon#*before return 0, iclass 29, count 0 2006.169.08:06:25.89#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.169.08:06:25.89#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.169.08:06:25.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.169.08:06:25.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.169.08:06:25.89$vc4f8/va=4,7 2006.169.08:06:25.89#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.169.08:06:25.89#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.169.08:06:25.89#ibcon#ireg 11 cls_cnt 2 2006.169.08:06:25.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.169.08:06:25.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.169.08:06:25.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.169.08:06:25.95#ibcon#enter wrdev, iclass 31, count 2 2006.169.08:06:25.95#ibcon#first serial, iclass 31, count 2 2006.169.08:06:25.95#ibcon#enter sib2, iclass 31, count 2 2006.169.08:06:25.95#ibcon#flushed, iclass 31, count 2 2006.169.08:06:25.95#ibcon#about to write, iclass 31, count 2 2006.169.08:06:25.95#ibcon#wrote, iclass 31, count 2 2006.169.08:06:25.95#ibcon#about to read 3, iclass 31, count 2 2006.169.08:06:25.97#ibcon#read 3, iclass 31, count 2 2006.169.08:06:25.97#ibcon#about to read 4, iclass 31, count 2 2006.169.08:06:25.97#ibcon#read 4, iclass 31, count 2 2006.169.08:06:25.97#ibcon#about to read 5, iclass 31, count 2 2006.169.08:06:25.97#ibcon#read 5, iclass 31, count 2 2006.169.08:06:25.97#ibcon#about to read 6, iclass 31, count 2 2006.169.08:06:25.97#ibcon#read 6, iclass 31, count 2 2006.169.08:06:25.97#ibcon#end of sib2, iclass 31, count 2 2006.169.08:06:25.97#ibcon#*mode == 0, iclass 31, count 2 2006.169.08:06:25.97#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.169.08:06:25.97#ibcon#[25=AT04-07\r\n] 2006.169.08:06:25.97#ibcon#*before write, iclass 31, count 2 2006.169.08:06:25.97#ibcon#enter sib2, iclass 31, count 2 2006.169.08:06:25.97#ibcon#flushed, iclass 31, count 2 2006.169.08:06:25.97#ibcon#about to write, iclass 31, count 2 2006.169.08:06:25.97#ibcon#wrote, iclass 31, count 2 2006.169.08:06:25.97#ibcon#about to read 3, iclass 31, count 2 2006.169.08:06:26.00#ibcon#read 3, iclass 31, count 2 2006.169.08:06:26.00#ibcon#about to read 4, iclass 31, count 2 2006.169.08:06:26.00#ibcon#read 4, iclass 31, count 2 2006.169.08:06:26.00#ibcon#about to read 5, iclass 31, count 2 2006.169.08:06:26.00#ibcon#read 5, iclass 31, count 2 2006.169.08:06:26.00#ibcon#about to read 6, iclass 31, count 2 2006.169.08:06:26.00#ibcon#read 6, iclass 31, count 2 2006.169.08:06:26.00#ibcon#end of sib2, iclass 31, count 2 2006.169.08:06:26.00#ibcon#*after write, iclass 31, count 2 2006.169.08:06:26.00#ibcon#*before return 0, iclass 31, count 2 2006.169.08:06:26.00#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.169.08:06:26.00#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.169.08:06:26.00#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.169.08:06:26.00#ibcon#ireg 7 cls_cnt 0 2006.169.08:06:26.00#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.169.08:06:26.12#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.169.08:06:26.12#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.169.08:06:26.12#ibcon#enter wrdev, iclass 31, count 0 2006.169.08:06:26.12#ibcon#first serial, iclass 31, count 0 2006.169.08:06:26.12#ibcon#enter sib2, iclass 31, count 0 2006.169.08:06:26.12#ibcon#flushed, iclass 31, count 0 2006.169.08:06:26.12#ibcon#about to write, iclass 31, count 0 2006.169.08:06:26.12#ibcon#wrote, iclass 31, count 0 2006.169.08:06:26.12#ibcon#about to read 3, iclass 31, count 0 2006.169.08:06:26.14#ibcon#read 3, iclass 31, count 0 2006.169.08:06:26.14#ibcon#about to read 4, iclass 31, count 0 2006.169.08:06:26.14#ibcon#read 4, iclass 31, count 0 2006.169.08:06:26.14#ibcon#about to read 5, iclass 31, count 0 2006.169.08:06:26.14#ibcon#read 5, iclass 31, count 0 2006.169.08:06:26.14#ibcon#about to read 6, iclass 31, count 0 2006.169.08:06:26.14#ibcon#read 6, iclass 31, count 0 2006.169.08:06:26.14#ibcon#end of sib2, iclass 31, count 0 2006.169.08:06:26.14#ibcon#*mode == 0, iclass 31, count 0 2006.169.08:06:26.14#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.169.08:06:26.14#ibcon#[25=USB\r\n] 2006.169.08:06:26.14#ibcon#*before write, iclass 31, count 0 2006.169.08:06:26.14#ibcon#enter sib2, iclass 31, count 0 2006.169.08:06:26.14#ibcon#flushed, iclass 31, count 0 2006.169.08:06:26.14#ibcon#about to write, iclass 31, count 0 2006.169.08:06:26.14#ibcon#wrote, iclass 31, count 0 2006.169.08:06:26.14#ibcon#about to read 3, iclass 31, count 0 2006.169.08:06:26.17#ibcon#read 3, iclass 31, count 0 2006.169.08:06:26.17#ibcon#about to read 4, iclass 31, count 0 2006.169.08:06:26.17#ibcon#read 4, iclass 31, count 0 2006.169.08:06:26.17#ibcon#about to read 5, iclass 31, count 0 2006.169.08:06:26.17#ibcon#read 5, iclass 31, count 0 2006.169.08:06:26.17#ibcon#about to read 6, iclass 31, count 0 2006.169.08:06:26.17#ibcon#read 6, iclass 31, count 0 2006.169.08:06:26.17#ibcon#end of sib2, iclass 31, count 0 2006.169.08:06:26.17#ibcon#*after write, iclass 31, count 0 2006.169.08:06:26.17#ibcon#*before return 0, iclass 31, count 0 2006.169.08:06:26.17#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.169.08:06:26.17#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.169.08:06:26.17#ibcon#about to clear, iclass 31 cls_cnt 0 2006.169.08:06:26.17#ibcon#cleared, iclass 31 cls_cnt 0 2006.169.08:06:26.17$vc4f8/valo=5,652.99 2006.169.08:06:26.17#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.169.08:06:26.17#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.169.08:06:26.17#ibcon#ireg 17 cls_cnt 0 2006.169.08:06:26.17#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:06:26.17#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:06:26.17#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:06:26.17#ibcon#enter wrdev, iclass 33, count 0 2006.169.08:06:26.17#ibcon#first serial, iclass 33, count 0 2006.169.08:06:26.17#ibcon#enter sib2, iclass 33, count 0 2006.169.08:06:26.17#ibcon#flushed, iclass 33, count 0 2006.169.08:06:26.17#ibcon#about to write, iclass 33, count 0 2006.169.08:06:26.17#ibcon#wrote, iclass 33, count 0 2006.169.08:06:26.17#ibcon#about to read 3, iclass 33, count 0 2006.169.08:06:26.19#ibcon#read 3, iclass 33, count 0 2006.169.08:06:26.19#ibcon#about to read 4, iclass 33, count 0 2006.169.08:06:26.19#ibcon#read 4, iclass 33, count 0 2006.169.08:06:26.19#ibcon#about to read 5, iclass 33, count 0 2006.169.08:06:26.19#ibcon#read 5, iclass 33, count 0 2006.169.08:06:26.19#ibcon#about to read 6, iclass 33, count 0 2006.169.08:06:26.19#ibcon#read 6, iclass 33, count 0 2006.169.08:06:26.19#ibcon#end of sib2, iclass 33, count 0 2006.169.08:06:26.19#ibcon#*mode == 0, iclass 33, count 0 2006.169.08:06:26.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.169.08:06:26.19#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.08:06:26.19#ibcon#*before write, iclass 33, count 0 2006.169.08:06:26.19#ibcon#enter sib2, iclass 33, count 0 2006.169.08:06:26.19#ibcon#flushed, iclass 33, count 0 2006.169.08:06:26.19#ibcon#about to write, iclass 33, count 0 2006.169.08:06:26.19#ibcon#wrote, iclass 33, count 0 2006.169.08:06:26.19#ibcon#about to read 3, iclass 33, count 0 2006.169.08:06:26.23#ibcon#read 3, iclass 33, count 0 2006.169.08:06:26.23#ibcon#about to read 4, iclass 33, count 0 2006.169.08:06:26.23#ibcon#read 4, iclass 33, count 0 2006.169.08:06:26.23#ibcon#about to read 5, iclass 33, count 0 2006.169.08:06:26.23#ibcon#read 5, iclass 33, count 0 2006.169.08:06:26.23#ibcon#about to read 6, iclass 33, count 0 2006.169.08:06:26.23#ibcon#read 6, iclass 33, count 0 2006.169.08:06:26.23#ibcon#end of sib2, iclass 33, count 0 2006.169.08:06:26.23#ibcon#*after write, iclass 33, count 0 2006.169.08:06:26.23#ibcon#*before return 0, iclass 33, count 0 2006.169.08:06:26.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:06:26.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:06:26.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.169.08:06:26.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.169.08:06:26.23$vc4f8/va=5,7 2006.169.08:06:26.23#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.169.08:06:26.23#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.169.08:06:26.23#ibcon#ireg 11 cls_cnt 2 2006.169.08:06:26.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.169.08:06:26.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.169.08:06:26.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.169.08:06:26.29#ibcon#enter wrdev, iclass 35, count 2 2006.169.08:06:26.29#ibcon#first serial, iclass 35, count 2 2006.169.08:06:26.29#ibcon#enter sib2, iclass 35, count 2 2006.169.08:06:26.29#ibcon#flushed, iclass 35, count 2 2006.169.08:06:26.29#ibcon#about to write, iclass 35, count 2 2006.169.08:06:26.29#ibcon#wrote, iclass 35, count 2 2006.169.08:06:26.29#ibcon#about to read 3, iclass 35, count 2 2006.169.08:06:26.31#ibcon#read 3, iclass 35, count 2 2006.169.08:06:26.31#ibcon#about to read 4, iclass 35, count 2 2006.169.08:06:26.31#ibcon#read 4, iclass 35, count 2 2006.169.08:06:26.31#ibcon#about to read 5, iclass 35, count 2 2006.169.08:06:26.31#ibcon#read 5, iclass 35, count 2 2006.169.08:06:26.31#ibcon#about to read 6, iclass 35, count 2 2006.169.08:06:26.31#ibcon#read 6, iclass 35, count 2 2006.169.08:06:26.31#ibcon#end of sib2, iclass 35, count 2 2006.169.08:06:26.31#ibcon#*mode == 0, iclass 35, count 2 2006.169.08:06:26.31#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.169.08:06:26.31#ibcon#[25=AT05-07\r\n] 2006.169.08:06:26.31#ibcon#*before write, iclass 35, count 2 2006.169.08:06:26.31#ibcon#enter sib2, iclass 35, count 2 2006.169.08:06:26.31#ibcon#flushed, iclass 35, count 2 2006.169.08:06:26.31#ibcon#about to write, iclass 35, count 2 2006.169.08:06:26.31#ibcon#wrote, iclass 35, count 2 2006.169.08:06:26.31#ibcon#about to read 3, iclass 35, count 2 2006.169.08:06:26.34#ibcon#read 3, iclass 35, count 2 2006.169.08:06:26.34#ibcon#about to read 4, iclass 35, count 2 2006.169.08:06:26.34#ibcon#read 4, iclass 35, count 2 2006.169.08:06:26.34#ibcon#about to read 5, iclass 35, count 2 2006.169.08:06:26.34#ibcon#read 5, iclass 35, count 2 2006.169.08:06:26.34#ibcon#about to read 6, iclass 35, count 2 2006.169.08:06:26.34#ibcon#read 6, iclass 35, count 2 2006.169.08:06:26.34#ibcon#end of sib2, iclass 35, count 2 2006.169.08:06:26.34#ibcon#*after write, iclass 35, count 2 2006.169.08:06:26.34#ibcon#*before return 0, iclass 35, count 2 2006.169.08:06:26.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.169.08:06:26.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.169.08:06:26.34#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.169.08:06:26.34#ibcon#ireg 7 cls_cnt 0 2006.169.08:06:26.34#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.169.08:06:26.46#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.169.08:06:26.46#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.169.08:06:26.46#ibcon#enter wrdev, iclass 35, count 0 2006.169.08:06:26.46#ibcon#first serial, iclass 35, count 0 2006.169.08:06:26.46#ibcon#enter sib2, iclass 35, count 0 2006.169.08:06:26.46#ibcon#flushed, iclass 35, count 0 2006.169.08:06:26.46#ibcon#about to write, iclass 35, count 0 2006.169.08:06:26.46#ibcon#wrote, iclass 35, count 0 2006.169.08:06:26.46#ibcon#about to read 3, iclass 35, count 0 2006.169.08:06:26.48#ibcon#read 3, iclass 35, count 0 2006.169.08:06:26.48#ibcon#about to read 4, iclass 35, count 0 2006.169.08:06:26.48#ibcon#read 4, iclass 35, count 0 2006.169.08:06:26.48#ibcon#about to read 5, iclass 35, count 0 2006.169.08:06:26.48#ibcon#read 5, iclass 35, count 0 2006.169.08:06:26.48#ibcon#about to read 6, iclass 35, count 0 2006.169.08:06:26.48#ibcon#read 6, iclass 35, count 0 2006.169.08:06:26.48#ibcon#end of sib2, iclass 35, count 0 2006.169.08:06:26.48#ibcon#*mode == 0, iclass 35, count 0 2006.169.08:06:26.48#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.169.08:06:26.48#ibcon#[25=USB\r\n] 2006.169.08:06:26.48#ibcon#*before write, iclass 35, count 0 2006.169.08:06:26.48#ibcon#enter sib2, iclass 35, count 0 2006.169.08:06:26.48#ibcon#flushed, iclass 35, count 0 2006.169.08:06:26.48#ibcon#about to write, iclass 35, count 0 2006.169.08:06:26.48#ibcon#wrote, iclass 35, count 0 2006.169.08:06:26.48#ibcon#about to read 3, iclass 35, count 0 2006.169.08:06:26.51#ibcon#read 3, iclass 35, count 0 2006.169.08:06:26.51#ibcon#about to read 4, iclass 35, count 0 2006.169.08:06:26.51#ibcon#read 4, iclass 35, count 0 2006.169.08:06:26.51#ibcon#about to read 5, iclass 35, count 0 2006.169.08:06:26.51#ibcon#read 5, iclass 35, count 0 2006.169.08:06:26.51#ibcon#about to read 6, iclass 35, count 0 2006.169.08:06:26.51#ibcon#read 6, iclass 35, count 0 2006.169.08:06:26.51#ibcon#end of sib2, iclass 35, count 0 2006.169.08:06:26.51#ibcon#*after write, iclass 35, count 0 2006.169.08:06:26.51#ibcon#*before return 0, iclass 35, count 0 2006.169.08:06:26.51#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.169.08:06:26.51#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.169.08:06:26.51#ibcon#about to clear, iclass 35 cls_cnt 0 2006.169.08:06:26.51#ibcon#cleared, iclass 35 cls_cnt 0 2006.169.08:06:26.51$vc4f8/valo=6,772.99 2006.169.08:06:26.51#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.169.08:06:26.51#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.169.08:06:26.51#ibcon#ireg 17 cls_cnt 0 2006.169.08:06:26.51#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:06:26.51#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:06:26.51#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:06:26.51#ibcon#enter wrdev, iclass 37, count 0 2006.169.08:06:26.51#ibcon#first serial, iclass 37, count 0 2006.169.08:06:26.51#ibcon#enter sib2, iclass 37, count 0 2006.169.08:06:26.51#ibcon#flushed, iclass 37, count 0 2006.169.08:06:26.51#ibcon#about to write, iclass 37, count 0 2006.169.08:06:26.51#ibcon#wrote, iclass 37, count 0 2006.169.08:06:26.51#ibcon#about to read 3, iclass 37, count 0 2006.169.08:06:26.53#ibcon#read 3, iclass 37, count 0 2006.169.08:06:26.53#ibcon#about to read 4, iclass 37, count 0 2006.169.08:06:26.53#ibcon#read 4, iclass 37, count 0 2006.169.08:06:26.53#ibcon#about to read 5, iclass 37, count 0 2006.169.08:06:26.53#ibcon#read 5, iclass 37, count 0 2006.169.08:06:26.53#ibcon#about to read 6, iclass 37, count 0 2006.169.08:06:26.53#ibcon#read 6, iclass 37, count 0 2006.169.08:06:26.53#ibcon#end of sib2, iclass 37, count 0 2006.169.08:06:26.53#ibcon#*mode == 0, iclass 37, count 0 2006.169.08:06:26.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.169.08:06:26.53#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.08:06:26.53#ibcon#*before write, iclass 37, count 0 2006.169.08:06:26.53#ibcon#enter sib2, iclass 37, count 0 2006.169.08:06:26.53#ibcon#flushed, iclass 37, count 0 2006.169.08:06:26.53#ibcon#about to write, iclass 37, count 0 2006.169.08:06:26.53#ibcon#wrote, iclass 37, count 0 2006.169.08:06:26.53#ibcon#about to read 3, iclass 37, count 0 2006.169.08:06:26.57#ibcon#read 3, iclass 37, count 0 2006.169.08:06:26.57#ibcon#about to read 4, iclass 37, count 0 2006.169.08:06:26.57#ibcon#read 4, iclass 37, count 0 2006.169.08:06:26.57#ibcon#about to read 5, iclass 37, count 0 2006.169.08:06:26.57#ibcon#read 5, iclass 37, count 0 2006.169.08:06:26.57#ibcon#about to read 6, iclass 37, count 0 2006.169.08:06:26.57#ibcon#read 6, iclass 37, count 0 2006.169.08:06:26.57#ibcon#end of sib2, iclass 37, count 0 2006.169.08:06:26.57#ibcon#*after write, iclass 37, count 0 2006.169.08:06:26.57#ibcon#*before return 0, iclass 37, count 0 2006.169.08:06:26.57#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:06:26.57#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:06:26.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.169.08:06:26.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.169.08:06:26.57$vc4f8/va=6,6 2006.169.08:06:26.57#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.169.08:06:26.57#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.169.08:06:26.57#ibcon#ireg 11 cls_cnt 2 2006.169.08:06:26.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.169.08:06:26.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.169.08:06:26.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.169.08:06:26.63#ibcon#enter wrdev, iclass 39, count 2 2006.169.08:06:26.63#ibcon#first serial, iclass 39, count 2 2006.169.08:06:26.63#ibcon#enter sib2, iclass 39, count 2 2006.169.08:06:26.63#ibcon#flushed, iclass 39, count 2 2006.169.08:06:26.63#ibcon#about to write, iclass 39, count 2 2006.169.08:06:26.63#ibcon#wrote, iclass 39, count 2 2006.169.08:06:26.63#ibcon#about to read 3, iclass 39, count 2 2006.169.08:06:26.65#ibcon#read 3, iclass 39, count 2 2006.169.08:06:26.65#ibcon#about to read 4, iclass 39, count 2 2006.169.08:06:26.65#ibcon#read 4, iclass 39, count 2 2006.169.08:06:26.65#ibcon#about to read 5, iclass 39, count 2 2006.169.08:06:26.65#ibcon#read 5, iclass 39, count 2 2006.169.08:06:26.65#ibcon#about to read 6, iclass 39, count 2 2006.169.08:06:26.65#ibcon#read 6, iclass 39, count 2 2006.169.08:06:26.65#ibcon#end of sib2, iclass 39, count 2 2006.169.08:06:26.65#ibcon#*mode == 0, iclass 39, count 2 2006.169.08:06:26.65#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.169.08:06:26.65#ibcon#[25=AT06-06\r\n] 2006.169.08:06:26.65#ibcon#*before write, iclass 39, count 2 2006.169.08:06:26.65#ibcon#enter sib2, iclass 39, count 2 2006.169.08:06:26.65#ibcon#flushed, iclass 39, count 2 2006.169.08:06:26.65#ibcon#about to write, iclass 39, count 2 2006.169.08:06:26.65#ibcon#wrote, iclass 39, count 2 2006.169.08:06:26.65#ibcon#about to read 3, iclass 39, count 2 2006.169.08:06:26.68#ibcon#read 3, iclass 39, count 2 2006.169.08:06:26.68#ibcon#about to read 4, iclass 39, count 2 2006.169.08:06:26.68#ibcon#read 4, iclass 39, count 2 2006.169.08:06:26.68#ibcon#about to read 5, iclass 39, count 2 2006.169.08:06:26.68#ibcon#read 5, iclass 39, count 2 2006.169.08:06:26.68#ibcon#about to read 6, iclass 39, count 2 2006.169.08:06:26.68#ibcon#read 6, iclass 39, count 2 2006.169.08:06:26.68#ibcon#end of sib2, iclass 39, count 2 2006.169.08:06:26.68#ibcon#*after write, iclass 39, count 2 2006.169.08:06:26.68#ibcon#*before return 0, iclass 39, count 2 2006.169.08:06:26.68#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.169.08:06:26.68#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.169.08:06:26.68#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.169.08:06:26.68#ibcon#ireg 7 cls_cnt 0 2006.169.08:06:26.68#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.169.08:06:26.80#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.169.08:06:26.80#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.169.08:06:26.80#ibcon#enter wrdev, iclass 39, count 0 2006.169.08:06:26.80#ibcon#first serial, iclass 39, count 0 2006.169.08:06:26.80#ibcon#enter sib2, iclass 39, count 0 2006.169.08:06:26.80#ibcon#flushed, iclass 39, count 0 2006.169.08:06:26.80#ibcon#about to write, iclass 39, count 0 2006.169.08:06:26.80#ibcon#wrote, iclass 39, count 0 2006.169.08:06:26.80#ibcon#about to read 3, iclass 39, count 0 2006.169.08:06:26.82#ibcon#read 3, iclass 39, count 0 2006.169.08:06:26.82#ibcon#about to read 4, iclass 39, count 0 2006.169.08:06:26.82#ibcon#read 4, iclass 39, count 0 2006.169.08:06:26.82#ibcon#about to read 5, iclass 39, count 0 2006.169.08:06:26.82#ibcon#read 5, iclass 39, count 0 2006.169.08:06:26.82#ibcon#about to read 6, iclass 39, count 0 2006.169.08:06:26.82#ibcon#read 6, iclass 39, count 0 2006.169.08:06:26.82#ibcon#end of sib2, iclass 39, count 0 2006.169.08:06:26.82#ibcon#*mode == 0, iclass 39, count 0 2006.169.08:06:26.82#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.169.08:06:26.82#ibcon#[25=USB\r\n] 2006.169.08:06:26.82#ibcon#*before write, iclass 39, count 0 2006.169.08:06:26.82#ibcon#enter sib2, iclass 39, count 0 2006.169.08:06:26.82#ibcon#flushed, iclass 39, count 0 2006.169.08:06:26.82#ibcon#about to write, iclass 39, count 0 2006.169.08:06:26.82#ibcon#wrote, iclass 39, count 0 2006.169.08:06:26.82#ibcon#about to read 3, iclass 39, count 0 2006.169.08:06:26.85#ibcon#read 3, iclass 39, count 0 2006.169.08:06:26.85#ibcon#about to read 4, iclass 39, count 0 2006.169.08:06:26.85#ibcon#read 4, iclass 39, count 0 2006.169.08:06:26.85#ibcon#about to read 5, iclass 39, count 0 2006.169.08:06:26.85#ibcon#read 5, iclass 39, count 0 2006.169.08:06:26.85#ibcon#about to read 6, iclass 39, count 0 2006.169.08:06:26.85#ibcon#read 6, iclass 39, count 0 2006.169.08:06:26.85#ibcon#end of sib2, iclass 39, count 0 2006.169.08:06:26.85#ibcon#*after write, iclass 39, count 0 2006.169.08:06:26.85#ibcon#*before return 0, iclass 39, count 0 2006.169.08:06:26.85#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.169.08:06:26.85#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.169.08:06:26.85#ibcon#about to clear, iclass 39 cls_cnt 0 2006.169.08:06:26.85#ibcon#cleared, iclass 39 cls_cnt 0 2006.169.08:06:26.85$vc4f8/valo=7,832.99 2006.169.08:06:26.85#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.169.08:06:26.85#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.169.08:06:26.85#ibcon#ireg 17 cls_cnt 0 2006.169.08:06:26.85#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.169.08:06:26.85#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.169.08:06:26.85#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.169.08:06:26.85#ibcon#enter wrdev, iclass 3, count 0 2006.169.08:06:26.85#ibcon#first serial, iclass 3, count 0 2006.169.08:06:26.85#ibcon#enter sib2, iclass 3, count 0 2006.169.08:06:26.85#ibcon#flushed, iclass 3, count 0 2006.169.08:06:26.85#ibcon#about to write, iclass 3, count 0 2006.169.08:06:26.85#ibcon#wrote, iclass 3, count 0 2006.169.08:06:26.85#ibcon#about to read 3, iclass 3, count 0 2006.169.08:06:26.87#ibcon#read 3, iclass 3, count 0 2006.169.08:06:26.87#ibcon#about to read 4, iclass 3, count 0 2006.169.08:06:26.87#ibcon#read 4, iclass 3, count 0 2006.169.08:06:26.87#ibcon#about to read 5, iclass 3, count 0 2006.169.08:06:26.87#ibcon#read 5, iclass 3, count 0 2006.169.08:06:26.87#ibcon#about to read 6, iclass 3, count 0 2006.169.08:06:26.87#ibcon#read 6, iclass 3, count 0 2006.169.08:06:26.87#ibcon#end of sib2, iclass 3, count 0 2006.169.08:06:26.87#ibcon#*mode == 0, iclass 3, count 0 2006.169.08:06:26.87#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.169.08:06:26.87#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.08:06:26.87#ibcon#*before write, iclass 3, count 0 2006.169.08:06:26.87#ibcon#enter sib2, iclass 3, count 0 2006.169.08:06:26.87#ibcon#flushed, iclass 3, count 0 2006.169.08:06:26.87#ibcon#about to write, iclass 3, count 0 2006.169.08:06:26.87#ibcon#wrote, iclass 3, count 0 2006.169.08:06:26.87#ibcon#about to read 3, iclass 3, count 0 2006.169.08:06:26.91#ibcon#read 3, iclass 3, count 0 2006.169.08:06:26.91#ibcon#about to read 4, iclass 3, count 0 2006.169.08:06:26.91#ibcon#read 4, iclass 3, count 0 2006.169.08:06:26.91#ibcon#about to read 5, iclass 3, count 0 2006.169.08:06:26.91#ibcon#read 5, iclass 3, count 0 2006.169.08:06:26.91#ibcon#about to read 6, iclass 3, count 0 2006.169.08:06:26.91#ibcon#read 6, iclass 3, count 0 2006.169.08:06:26.91#ibcon#end of sib2, iclass 3, count 0 2006.169.08:06:26.91#ibcon#*after write, iclass 3, count 0 2006.169.08:06:26.91#ibcon#*before return 0, iclass 3, count 0 2006.169.08:06:26.91#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.169.08:06:26.91#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.169.08:06:26.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.169.08:06:26.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.169.08:06:26.91$vc4f8/va=7,6 2006.169.08:06:26.91#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.169.08:06:26.91#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.169.08:06:26.91#ibcon#ireg 11 cls_cnt 2 2006.169.08:06:26.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.169.08:06:26.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.169.08:06:26.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.169.08:06:26.97#ibcon#enter wrdev, iclass 5, count 2 2006.169.08:06:26.97#ibcon#first serial, iclass 5, count 2 2006.169.08:06:26.97#ibcon#enter sib2, iclass 5, count 2 2006.169.08:06:26.97#ibcon#flushed, iclass 5, count 2 2006.169.08:06:26.97#ibcon#about to write, iclass 5, count 2 2006.169.08:06:26.97#ibcon#wrote, iclass 5, count 2 2006.169.08:06:26.97#ibcon#about to read 3, iclass 5, count 2 2006.169.08:06:26.99#ibcon#read 3, iclass 5, count 2 2006.169.08:06:26.99#ibcon#about to read 4, iclass 5, count 2 2006.169.08:06:26.99#ibcon#read 4, iclass 5, count 2 2006.169.08:06:26.99#ibcon#about to read 5, iclass 5, count 2 2006.169.08:06:26.99#ibcon#read 5, iclass 5, count 2 2006.169.08:06:26.99#ibcon#about to read 6, iclass 5, count 2 2006.169.08:06:26.99#ibcon#read 6, iclass 5, count 2 2006.169.08:06:26.99#ibcon#end of sib2, iclass 5, count 2 2006.169.08:06:26.99#ibcon#*mode == 0, iclass 5, count 2 2006.169.08:06:26.99#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.169.08:06:26.99#ibcon#[25=AT07-06\r\n] 2006.169.08:06:26.99#ibcon#*before write, iclass 5, count 2 2006.169.08:06:26.99#ibcon#enter sib2, iclass 5, count 2 2006.169.08:06:26.99#ibcon#flushed, iclass 5, count 2 2006.169.08:06:26.99#ibcon#about to write, iclass 5, count 2 2006.169.08:06:26.99#ibcon#wrote, iclass 5, count 2 2006.169.08:06:26.99#ibcon#about to read 3, iclass 5, count 2 2006.169.08:06:27.02#ibcon#read 3, iclass 5, count 2 2006.169.08:06:27.02#ibcon#about to read 4, iclass 5, count 2 2006.169.08:06:27.02#ibcon#read 4, iclass 5, count 2 2006.169.08:06:27.02#ibcon#about to read 5, iclass 5, count 2 2006.169.08:06:27.02#ibcon#read 5, iclass 5, count 2 2006.169.08:06:27.02#ibcon#about to read 6, iclass 5, count 2 2006.169.08:06:27.02#ibcon#read 6, iclass 5, count 2 2006.169.08:06:27.02#ibcon#end of sib2, iclass 5, count 2 2006.169.08:06:27.02#ibcon#*after write, iclass 5, count 2 2006.169.08:06:27.02#ibcon#*before return 0, iclass 5, count 2 2006.169.08:06:27.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.169.08:06:27.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.169.08:06:27.02#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.169.08:06:27.02#ibcon#ireg 7 cls_cnt 0 2006.169.08:06:27.02#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.169.08:06:27.14#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.169.08:06:27.14#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.169.08:06:27.14#ibcon#enter wrdev, iclass 5, count 0 2006.169.08:06:27.14#ibcon#first serial, iclass 5, count 0 2006.169.08:06:27.14#ibcon#enter sib2, iclass 5, count 0 2006.169.08:06:27.14#ibcon#flushed, iclass 5, count 0 2006.169.08:06:27.14#ibcon#about to write, iclass 5, count 0 2006.169.08:06:27.14#ibcon#wrote, iclass 5, count 0 2006.169.08:06:27.14#ibcon#about to read 3, iclass 5, count 0 2006.169.08:06:27.16#ibcon#read 3, iclass 5, count 0 2006.169.08:06:27.16#ibcon#about to read 4, iclass 5, count 0 2006.169.08:06:27.16#ibcon#read 4, iclass 5, count 0 2006.169.08:06:27.16#ibcon#about to read 5, iclass 5, count 0 2006.169.08:06:27.16#ibcon#read 5, iclass 5, count 0 2006.169.08:06:27.16#ibcon#about to read 6, iclass 5, count 0 2006.169.08:06:27.16#ibcon#read 6, iclass 5, count 0 2006.169.08:06:27.16#ibcon#end of sib2, iclass 5, count 0 2006.169.08:06:27.16#ibcon#*mode == 0, iclass 5, count 0 2006.169.08:06:27.16#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.169.08:06:27.16#ibcon#[25=USB\r\n] 2006.169.08:06:27.16#ibcon#*before write, iclass 5, count 0 2006.169.08:06:27.16#ibcon#enter sib2, iclass 5, count 0 2006.169.08:06:27.16#ibcon#flushed, iclass 5, count 0 2006.169.08:06:27.16#ibcon#about to write, iclass 5, count 0 2006.169.08:06:27.16#ibcon#wrote, iclass 5, count 0 2006.169.08:06:27.16#ibcon#about to read 3, iclass 5, count 0 2006.169.08:06:27.19#ibcon#read 3, iclass 5, count 0 2006.169.08:06:27.19#ibcon#about to read 4, iclass 5, count 0 2006.169.08:06:27.19#ibcon#read 4, iclass 5, count 0 2006.169.08:06:27.19#ibcon#about to read 5, iclass 5, count 0 2006.169.08:06:27.19#ibcon#read 5, iclass 5, count 0 2006.169.08:06:27.19#ibcon#about to read 6, iclass 5, count 0 2006.169.08:06:27.19#ibcon#read 6, iclass 5, count 0 2006.169.08:06:27.19#ibcon#end of sib2, iclass 5, count 0 2006.169.08:06:27.19#ibcon#*after write, iclass 5, count 0 2006.169.08:06:27.19#ibcon#*before return 0, iclass 5, count 0 2006.169.08:06:27.19#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.169.08:06:27.19#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.169.08:06:27.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.169.08:06:27.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.169.08:06:27.19$vc4f8/valo=8,852.99 2006.169.08:06:27.19#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.169.08:06:27.19#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.169.08:06:27.19#ibcon#ireg 17 cls_cnt 0 2006.169.08:06:27.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.169.08:06:27.19#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.169.08:06:27.19#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.169.08:06:27.19#ibcon#enter wrdev, iclass 7, count 0 2006.169.08:06:27.19#ibcon#first serial, iclass 7, count 0 2006.169.08:06:27.19#ibcon#enter sib2, iclass 7, count 0 2006.169.08:06:27.19#ibcon#flushed, iclass 7, count 0 2006.169.08:06:27.19#ibcon#about to write, iclass 7, count 0 2006.169.08:06:27.19#ibcon#wrote, iclass 7, count 0 2006.169.08:06:27.19#ibcon#about to read 3, iclass 7, count 0 2006.169.08:06:27.21#ibcon#read 3, iclass 7, count 0 2006.169.08:06:27.21#ibcon#about to read 4, iclass 7, count 0 2006.169.08:06:27.21#ibcon#read 4, iclass 7, count 0 2006.169.08:06:27.21#ibcon#about to read 5, iclass 7, count 0 2006.169.08:06:27.21#ibcon#read 5, iclass 7, count 0 2006.169.08:06:27.21#ibcon#about to read 6, iclass 7, count 0 2006.169.08:06:27.21#ibcon#read 6, iclass 7, count 0 2006.169.08:06:27.21#ibcon#end of sib2, iclass 7, count 0 2006.169.08:06:27.21#ibcon#*mode == 0, iclass 7, count 0 2006.169.08:06:27.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.169.08:06:27.21#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.08:06:27.21#ibcon#*before write, iclass 7, count 0 2006.169.08:06:27.21#ibcon#enter sib2, iclass 7, count 0 2006.169.08:06:27.21#ibcon#flushed, iclass 7, count 0 2006.169.08:06:27.21#ibcon#about to write, iclass 7, count 0 2006.169.08:06:27.21#ibcon#wrote, iclass 7, count 0 2006.169.08:06:27.21#ibcon#about to read 3, iclass 7, count 0 2006.169.08:06:27.25#ibcon#read 3, iclass 7, count 0 2006.169.08:06:27.25#ibcon#about to read 4, iclass 7, count 0 2006.169.08:06:27.25#ibcon#read 4, iclass 7, count 0 2006.169.08:06:27.25#ibcon#about to read 5, iclass 7, count 0 2006.169.08:06:27.25#ibcon#read 5, iclass 7, count 0 2006.169.08:06:27.25#ibcon#about to read 6, iclass 7, count 0 2006.169.08:06:27.25#ibcon#read 6, iclass 7, count 0 2006.169.08:06:27.25#ibcon#end of sib2, iclass 7, count 0 2006.169.08:06:27.25#ibcon#*after write, iclass 7, count 0 2006.169.08:06:27.25#ibcon#*before return 0, iclass 7, count 0 2006.169.08:06:27.25#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.169.08:06:27.25#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.169.08:06:27.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.169.08:06:27.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.169.08:06:27.25$vc4f8/va=8,7 2006.169.08:06:27.25#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.169.08:06:27.25#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.169.08:06:27.25#ibcon#ireg 11 cls_cnt 2 2006.169.08:06:27.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.169.08:06:27.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.169.08:06:27.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.169.08:06:27.31#ibcon#enter wrdev, iclass 11, count 2 2006.169.08:06:27.31#ibcon#first serial, iclass 11, count 2 2006.169.08:06:27.31#ibcon#enter sib2, iclass 11, count 2 2006.169.08:06:27.31#ibcon#flushed, iclass 11, count 2 2006.169.08:06:27.31#ibcon#about to write, iclass 11, count 2 2006.169.08:06:27.31#ibcon#wrote, iclass 11, count 2 2006.169.08:06:27.31#ibcon#about to read 3, iclass 11, count 2 2006.169.08:06:27.33#ibcon#read 3, iclass 11, count 2 2006.169.08:06:27.33#ibcon#about to read 4, iclass 11, count 2 2006.169.08:06:27.33#ibcon#read 4, iclass 11, count 2 2006.169.08:06:27.33#ibcon#about to read 5, iclass 11, count 2 2006.169.08:06:27.33#ibcon#read 5, iclass 11, count 2 2006.169.08:06:27.33#ibcon#about to read 6, iclass 11, count 2 2006.169.08:06:27.33#ibcon#read 6, iclass 11, count 2 2006.169.08:06:27.33#ibcon#end of sib2, iclass 11, count 2 2006.169.08:06:27.33#ibcon#*mode == 0, iclass 11, count 2 2006.169.08:06:27.33#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.169.08:06:27.33#ibcon#[25=AT08-07\r\n] 2006.169.08:06:27.33#ibcon#*before write, iclass 11, count 2 2006.169.08:06:27.33#ibcon#enter sib2, iclass 11, count 2 2006.169.08:06:27.33#ibcon#flushed, iclass 11, count 2 2006.169.08:06:27.33#ibcon#about to write, iclass 11, count 2 2006.169.08:06:27.33#ibcon#wrote, iclass 11, count 2 2006.169.08:06:27.33#ibcon#about to read 3, iclass 11, count 2 2006.169.08:06:27.36#ibcon#read 3, iclass 11, count 2 2006.169.08:06:27.36#ibcon#about to read 4, iclass 11, count 2 2006.169.08:06:27.36#ibcon#read 4, iclass 11, count 2 2006.169.08:06:27.36#ibcon#about to read 5, iclass 11, count 2 2006.169.08:06:27.36#ibcon#read 5, iclass 11, count 2 2006.169.08:06:27.36#ibcon#about to read 6, iclass 11, count 2 2006.169.08:06:27.36#ibcon#read 6, iclass 11, count 2 2006.169.08:06:27.36#ibcon#end of sib2, iclass 11, count 2 2006.169.08:06:27.36#ibcon#*after write, iclass 11, count 2 2006.169.08:06:27.36#ibcon#*before return 0, iclass 11, count 2 2006.169.08:06:27.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.169.08:06:27.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.169.08:06:27.36#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.169.08:06:27.36#ibcon#ireg 7 cls_cnt 0 2006.169.08:06:27.36#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.169.08:06:27.48#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.169.08:06:27.48#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.169.08:06:27.48#ibcon#enter wrdev, iclass 11, count 0 2006.169.08:06:27.48#ibcon#first serial, iclass 11, count 0 2006.169.08:06:27.48#ibcon#enter sib2, iclass 11, count 0 2006.169.08:06:27.48#ibcon#flushed, iclass 11, count 0 2006.169.08:06:27.48#ibcon#about to write, iclass 11, count 0 2006.169.08:06:27.48#ibcon#wrote, iclass 11, count 0 2006.169.08:06:27.48#ibcon#about to read 3, iclass 11, count 0 2006.169.08:06:27.50#ibcon#read 3, iclass 11, count 0 2006.169.08:06:27.50#ibcon#about to read 4, iclass 11, count 0 2006.169.08:06:27.50#ibcon#read 4, iclass 11, count 0 2006.169.08:06:27.50#ibcon#about to read 5, iclass 11, count 0 2006.169.08:06:27.50#ibcon#read 5, iclass 11, count 0 2006.169.08:06:27.50#ibcon#about to read 6, iclass 11, count 0 2006.169.08:06:27.50#ibcon#read 6, iclass 11, count 0 2006.169.08:06:27.50#ibcon#end of sib2, iclass 11, count 0 2006.169.08:06:27.50#ibcon#*mode == 0, iclass 11, count 0 2006.169.08:06:27.50#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.169.08:06:27.50#ibcon#[25=USB\r\n] 2006.169.08:06:27.50#ibcon#*before write, iclass 11, count 0 2006.169.08:06:27.50#ibcon#enter sib2, iclass 11, count 0 2006.169.08:06:27.50#ibcon#flushed, iclass 11, count 0 2006.169.08:06:27.50#ibcon#about to write, iclass 11, count 0 2006.169.08:06:27.50#ibcon#wrote, iclass 11, count 0 2006.169.08:06:27.50#ibcon#about to read 3, iclass 11, count 0 2006.169.08:06:27.53#ibcon#read 3, iclass 11, count 0 2006.169.08:06:27.53#ibcon#about to read 4, iclass 11, count 0 2006.169.08:06:27.53#ibcon#read 4, iclass 11, count 0 2006.169.08:06:27.53#ibcon#about to read 5, iclass 11, count 0 2006.169.08:06:27.53#ibcon#read 5, iclass 11, count 0 2006.169.08:06:27.53#ibcon#about to read 6, iclass 11, count 0 2006.169.08:06:27.53#ibcon#read 6, iclass 11, count 0 2006.169.08:06:27.53#ibcon#end of sib2, iclass 11, count 0 2006.169.08:06:27.53#ibcon#*after write, iclass 11, count 0 2006.169.08:06:27.53#ibcon#*before return 0, iclass 11, count 0 2006.169.08:06:27.53#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.169.08:06:27.53#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.169.08:06:27.53#ibcon#about to clear, iclass 11 cls_cnt 0 2006.169.08:06:27.53#ibcon#cleared, iclass 11 cls_cnt 0 2006.169.08:06:27.53$vc4f8/vblo=1,632.99 2006.169.08:06:27.53#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.169.08:06:27.53#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.169.08:06:27.53#ibcon#ireg 17 cls_cnt 0 2006.169.08:06:27.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:06:27.53#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:06:27.53#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:06:27.53#ibcon#enter wrdev, iclass 13, count 0 2006.169.08:06:27.53#ibcon#first serial, iclass 13, count 0 2006.169.08:06:27.53#ibcon#enter sib2, iclass 13, count 0 2006.169.08:06:27.53#ibcon#flushed, iclass 13, count 0 2006.169.08:06:27.53#ibcon#about to write, iclass 13, count 0 2006.169.08:06:27.53#ibcon#wrote, iclass 13, count 0 2006.169.08:06:27.53#ibcon#about to read 3, iclass 13, count 0 2006.169.08:06:27.55#ibcon#read 3, iclass 13, count 0 2006.169.08:06:27.55#ibcon#about to read 4, iclass 13, count 0 2006.169.08:06:27.55#ibcon#read 4, iclass 13, count 0 2006.169.08:06:27.55#ibcon#about to read 5, iclass 13, count 0 2006.169.08:06:27.55#ibcon#read 5, iclass 13, count 0 2006.169.08:06:27.55#ibcon#about to read 6, iclass 13, count 0 2006.169.08:06:27.55#ibcon#read 6, iclass 13, count 0 2006.169.08:06:27.55#ibcon#end of sib2, iclass 13, count 0 2006.169.08:06:27.55#ibcon#*mode == 0, iclass 13, count 0 2006.169.08:06:27.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.08:06:27.55#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.08:06:27.55#ibcon#*before write, iclass 13, count 0 2006.169.08:06:27.55#ibcon#enter sib2, iclass 13, count 0 2006.169.08:06:27.55#ibcon#flushed, iclass 13, count 0 2006.169.08:06:27.55#ibcon#about to write, iclass 13, count 0 2006.169.08:06:27.55#ibcon#wrote, iclass 13, count 0 2006.169.08:06:27.55#ibcon#about to read 3, iclass 13, count 0 2006.169.08:06:27.59#ibcon#read 3, iclass 13, count 0 2006.169.08:06:27.59#ibcon#about to read 4, iclass 13, count 0 2006.169.08:06:27.59#ibcon#read 4, iclass 13, count 0 2006.169.08:06:27.59#ibcon#about to read 5, iclass 13, count 0 2006.169.08:06:27.59#ibcon#read 5, iclass 13, count 0 2006.169.08:06:27.59#ibcon#about to read 6, iclass 13, count 0 2006.169.08:06:27.59#ibcon#read 6, iclass 13, count 0 2006.169.08:06:27.59#ibcon#end of sib2, iclass 13, count 0 2006.169.08:06:27.59#ibcon#*after write, iclass 13, count 0 2006.169.08:06:27.59#ibcon#*before return 0, iclass 13, count 0 2006.169.08:06:27.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:06:27.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:06:27.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.08:06:27.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.08:06:27.59$vc4f8/vb=1,4 2006.169.08:06:27.59#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.169.08:06:27.59#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.169.08:06:27.59#ibcon#ireg 11 cls_cnt 2 2006.169.08:06:27.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.169.08:06:27.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.169.08:06:27.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.169.08:06:27.59#ibcon#enter wrdev, iclass 15, count 2 2006.169.08:06:27.59#ibcon#first serial, iclass 15, count 2 2006.169.08:06:27.59#ibcon#enter sib2, iclass 15, count 2 2006.169.08:06:27.59#ibcon#flushed, iclass 15, count 2 2006.169.08:06:27.59#ibcon#about to write, iclass 15, count 2 2006.169.08:06:27.59#ibcon#wrote, iclass 15, count 2 2006.169.08:06:27.59#ibcon#about to read 3, iclass 15, count 2 2006.169.08:06:27.61#ibcon#read 3, iclass 15, count 2 2006.169.08:06:27.61#ibcon#about to read 4, iclass 15, count 2 2006.169.08:06:27.61#ibcon#read 4, iclass 15, count 2 2006.169.08:06:27.61#ibcon#about to read 5, iclass 15, count 2 2006.169.08:06:27.61#ibcon#read 5, iclass 15, count 2 2006.169.08:06:27.61#ibcon#about to read 6, iclass 15, count 2 2006.169.08:06:27.61#ibcon#read 6, iclass 15, count 2 2006.169.08:06:27.61#ibcon#end of sib2, iclass 15, count 2 2006.169.08:06:27.61#ibcon#*mode == 0, iclass 15, count 2 2006.169.08:06:27.61#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.169.08:06:27.61#ibcon#[27=AT01-04\r\n] 2006.169.08:06:27.61#ibcon#*before write, iclass 15, count 2 2006.169.08:06:27.61#ibcon#enter sib2, iclass 15, count 2 2006.169.08:06:27.61#ibcon#flushed, iclass 15, count 2 2006.169.08:06:27.61#ibcon#about to write, iclass 15, count 2 2006.169.08:06:27.61#ibcon#wrote, iclass 15, count 2 2006.169.08:06:27.61#ibcon#about to read 3, iclass 15, count 2 2006.169.08:06:27.64#ibcon#read 3, iclass 15, count 2 2006.169.08:06:27.64#ibcon#about to read 4, iclass 15, count 2 2006.169.08:06:27.64#ibcon#read 4, iclass 15, count 2 2006.169.08:06:27.64#ibcon#about to read 5, iclass 15, count 2 2006.169.08:06:27.64#ibcon#read 5, iclass 15, count 2 2006.169.08:06:27.64#ibcon#about to read 6, iclass 15, count 2 2006.169.08:06:27.64#ibcon#read 6, iclass 15, count 2 2006.169.08:06:27.64#ibcon#end of sib2, iclass 15, count 2 2006.169.08:06:27.64#ibcon#*after write, iclass 15, count 2 2006.169.08:06:27.64#ibcon#*before return 0, iclass 15, count 2 2006.169.08:06:27.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.169.08:06:27.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.169.08:06:27.64#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.169.08:06:27.64#ibcon#ireg 7 cls_cnt 0 2006.169.08:06:27.64#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.169.08:06:27.76#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.169.08:06:27.76#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.169.08:06:27.76#ibcon#enter wrdev, iclass 15, count 0 2006.169.08:06:27.76#ibcon#first serial, iclass 15, count 0 2006.169.08:06:27.76#ibcon#enter sib2, iclass 15, count 0 2006.169.08:06:27.76#ibcon#flushed, iclass 15, count 0 2006.169.08:06:27.76#ibcon#about to write, iclass 15, count 0 2006.169.08:06:27.76#ibcon#wrote, iclass 15, count 0 2006.169.08:06:27.76#ibcon#about to read 3, iclass 15, count 0 2006.169.08:06:27.78#ibcon#read 3, iclass 15, count 0 2006.169.08:06:27.78#ibcon#about to read 4, iclass 15, count 0 2006.169.08:06:27.78#ibcon#read 4, iclass 15, count 0 2006.169.08:06:27.78#ibcon#about to read 5, iclass 15, count 0 2006.169.08:06:27.78#ibcon#read 5, iclass 15, count 0 2006.169.08:06:27.78#ibcon#about to read 6, iclass 15, count 0 2006.169.08:06:27.78#ibcon#read 6, iclass 15, count 0 2006.169.08:06:27.78#ibcon#end of sib2, iclass 15, count 0 2006.169.08:06:27.78#ibcon#*mode == 0, iclass 15, count 0 2006.169.08:06:27.78#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.169.08:06:27.78#ibcon#[27=USB\r\n] 2006.169.08:06:27.78#ibcon#*before write, iclass 15, count 0 2006.169.08:06:27.78#ibcon#enter sib2, iclass 15, count 0 2006.169.08:06:27.78#ibcon#flushed, iclass 15, count 0 2006.169.08:06:27.78#ibcon#about to write, iclass 15, count 0 2006.169.08:06:27.78#ibcon#wrote, iclass 15, count 0 2006.169.08:06:27.78#ibcon#about to read 3, iclass 15, count 0 2006.169.08:06:27.81#ibcon#read 3, iclass 15, count 0 2006.169.08:06:27.81#ibcon#about to read 4, iclass 15, count 0 2006.169.08:06:27.81#ibcon#read 4, iclass 15, count 0 2006.169.08:06:27.81#ibcon#about to read 5, iclass 15, count 0 2006.169.08:06:27.81#ibcon#read 5, iclass 15, count 0 2006.169.08:06:27.81#ibcon#about to read 6, iclass 15, count 0 2006.169.08:06:27.81#ibcon#read 6, iclass 15, count 0 2006.169.08:06:27.81#ibcon#end of sib2, iclass 15, count 0 2006.169.08:06:27.81#ibcon#*after write, iclass 15, count 0 2006.169.08:06:27.81#ibcon#*before return 0, iclass 15, count 0 2006.169.08:06:27.81#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.169.08:06:27.81#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.169.08:06:27.81#ibcon#about to clear, iclass 15 cls_cnt 0 2006.169.08:06:27.81#ibcon#cleared, iclass 15 cls_cnt 0 2006.169.08:06:27.81$vc4f8/vblo=2,640.99 2006.169.08:06:27.81#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.169.08:06:27.81#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.169.08:06:27.81#ibcon#ireg 17 cls_cnt 0 2006.169.08:06:27.81#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:06:27.81#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:06:27.81#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:06:27.81#ibcon#enter wrdev, iclass 17, count 0 2006.169.08:06:27.81#ibcon#first serial, iclass 17, count 0 2006.169.08:06:27.81#ibcon#enter sib2, iclass 17, count 0 2006.169.08:06:27.81#ibcon#flushed, iclass 17, count 0 2006.169.08:06:27.81#ibcon#about to write, iclass 17, count 0 2006.169.08:06:27.81#ibcon#wrote, iclass 17, count 0 2006.169.08:06:27.81#ibcon#about to read 3, iclass 17, count 0 2006.169.08:06:27.83#ibcon#read 3, iclass 17, count 0 2006.169.08:06:27.83#ibcon#about to read 4, iclass 17, count 0 2006.169.08:06:27.83#ibcon#read 4, iclass 17, count 0 2006.169.08:06:27.83#ibcon#about to read 5, iclass 17, count 0 2006.169.08:06:27.83#ibcon#read 5, iclass 17, count 0 2006.169.08:06:27.83#ibcon#about to read 6, iclass 17, count 0 2006.169.08:06:27.83#ibcon#read 6, iclass 17, count 0 2006.169.08:06:27.83#ibcon#end of sib2, iclass 17, count 0 2006.169.08:06:27.83#ibcon#*mode == 0, iclass 17, count 0 2006.169.08:06:27.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.169.08:06:27.83#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.08:06:27.83#ibcon#*before write, iclass 17, count 0 2006.169.08:06:27.83#ibcon#enter sib2, iclass 17, count 0 2006.169.08:06:27.83#ibcon#flushed, iclass 17, count 0 2006.169.08:06:27.83#ibcon#about to write, iclass 17, count 0 2006.169.08:06:27.83#ibcon#wrote, iclass 17, count 0 2006.169.08:06:27.83#ibcon#about to read 3, iclass 17, count 0 2006.169.08:06:27.87#ibcon#read 3, iclass 17, count 0 2006.169.08:06:27.87#ibcon#about to read 4, iclass 17, count 0 2006.169.08:06:27.87#ibcon#read 4, iclass 17, count 0 2006.169.08:06:27.87#ibcon#about to read 5, iclass 17, count 0 2006.169.08:06:27.87#ibcon#read 5, iclass 17, count 0 2006.169.08:06:27.87#ibcon#about to read 6, iclass 17, count 0 2006.169.08:06:27.87#ibcon#read 6, iclass 17, count 0 2006.169.08:06:27.87#ibcon#end of sib2, iclass 17, count 0 2006.169.08:06:27.87#ibcon#*after write, iclass 17, count 0 2006.169.08:06:27.87#ibcon#*before return 0, iclass 17, count 0 2006.169.08:06:27.87#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:06:27.87#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:06:27.87#ibcon#about to clear, iclass 17 cls_cnt 0 2006.169.08:06:27.87#ibcon#cleared, iclass 17 cls_cnt 0 2006.169.08:06:27.87$vc4f8/vb=2,4 2006.169.08:06:27.87#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.169.08:06:27.87#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.169.08:06:27.87#ibcon#ireg 11 cls_cnt 2 2006.169.08:06:27.87#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.169.08:06:27.93#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.169.08:06:27.93#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.169.08:06:27.93#ibcon#enter wrdev, iclass 19, count 2 2006.169.08:06:27.93#ibcon#first serial, iclass 19, count 2 2006.169.08:06:27.93#ibcon#enter sib2, iclass 19, count 2 2006.169.08:06:27.93#ibcon#flushed, iclass 19, count 2 2006.169.08:06:27.93#ibcon#about to write, iclass 19, count 2 2006.169.08:06:27.93#ibcon#wrote, iclass 19, count 2 2006.169.08:06:27.93#ibcon#about to read 3, iclass 19, count 2 2006.169.08:06:27.95#ibcon#read 3, iclass 19, count 2 2006.169.08:06:27.95#ibcon#about to read 4, iclass 19, count 2 2006.169.08:06:27.95#ibcon#read 4, iclass 19, count 2 2006.169.08:06:27.95#ibcon#about to read 5, iclass 19, count 2 2006.169.08:06:27.95#ibcon#read 5, iclass 19, count 2 2006.169.08:06:27.95#ibcon#about to read 6, iclass 19, count 2 2006.169.08:06:27.95#ibcon#read 6, iclass 19, count 2 2006.169.08:06:27.95#ibcon#end of sib2, iclass 19, count 2 2006.169.08:06:27.95#ibcon#*mode == 0, iclass 19, count 2 2006.169.08:06:27.95#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.169.08:06:27.95#ibcon#[27=AT02-04\r\n] 2006.169.08:06:27.95#ibcon#*before write, iclass 19, count 2 2006.169.08:06:27.95#ibcon#enter sib2, iclass 19, count 2 2006.169.08:06:27.95#ibcon#flushed, iclass 19, count 2 2006.169.08:06:27.95#ibcon#about to write, iclass 19, count 2 2006.169.08:06:27.95#ibcon#wrote, iclass 19, count 2 2006.169.08:06:27.95#ibcon#about to read 3, iclass 19, count 2 2006.169.08:06:27.98#ibcon#read 3, iclass 19, count 2 2006.169.08:06:27.98#ibcon#about to read 4, iclass 19, count 2 2006.169.08:06:27.98#ibcon#read 4, iclass 19, count 2 2006.169.08:06:27.98#ibcon#about to read 5, iclass 19, count 2 2006.169.08:06:27.98#ibcon#read 5, iclass 19, count 2 2006.169.08:06:27.98#ibcon#about to read 6, iclass 19, count 2 2006.169.08:06:27.98#ibcon#read 6, iclass 19, count 2 2006.169.08:06:27.98#ibcon#end of sib2, iclass 19, count 2 2006.169.08:06:27.98#ibcon#*after write, iclass 19, count 2 2006.169.08:06:27.98#ibcon#*before return 0, iclass 19, count 2 2006.169.08:06:27.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.169.08:06:27.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.169.08:06:27.98#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.169.08:06:27.98#ibcon#ireg 7 cls_cnt 0 2006.169.08:06:27.98#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.169.08:06:28.10#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.169.08:06:28.10#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.169.08:06:28.10#ibcon#enter wrdev, iclass 19, count 0 2006.169.08:06:28.10#ibcon#first serial, iclass 19, count 0 2006.169.08:06:28.10#ibcon#enter sib2, iclass 19, count 0 2006.169.08:06:28.10#ibcon#flushed, iclass 19, count 0 2006.169.08:06:28.10#ibcon#about to write, iclass 19, count 0 2006.169.08:06:28.10#ibcon#wrote, iclass 19, count 0 2006.169.08:06:28.10#ibcon#about to read 3, iclass 19, count 0 2006.169.08:06:28.12#ibcon#read 3, iclass 19, count 0 2006.169.08:06:28.12#ibcon#about to read 4, iclass 19, count 0 2006.169.08:06:28.12#ibcon#read 4, iclass 19, count 0 2006.169.08:06:28.12#ibcon#about to read 5, iclass 19, count 0 2006.169.08:06:28.12#ibcon#read 5, iclass 19, count 0 2006.169.08:06:28.12#ibcon#about to read 6, iclass 19, count 0 2006.169.08:06:28.12#ibcon#read 6, iclass 19, count 0 2006.169.08:06:28.12#ibcon#end of sib2, iclass 19, count 0 2006.169.08:06:28.12#ibcon#*mode == 0, iclass 19, count 0 2006.169.08:06:28.12#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.169.08:06:28.12#ibcon#[27=USB\r\n] 2006.169.08:06:28.12#ibcon#*before write, iclass 19, count 0 2006.169.08:06:28.12#ibcon#enter sib2, iclass 19, count 0 2006.169.08:06:28.12#ibcon#flushed, iclass 19, count 0 2006.169.08:06:28.12#ibcon#about to write, iclass 19, count 0 2006.169.08:06:28.12#ibcon#wrote, iclass 19, count 0 2006.169.08:06:28.12#ibcon#about to read 3, iclass 19, count 0 2006.169.08:06:28.15#ibcon#read 3, iclass 19, count 0 2006.169.08:06:28.15#ibcon#about to read 4, iclass 19, count 0 2006.169.08:06:28.15#ibcon#read 4, iclass 19, count 0 2006.169.08:06:28.15#ibcon#about to read 5, iclass 19, count 0 2006.169.08:06:28.15#ibcon#read 5, iclass 19, count 0 2006.169.08:06:28.15#ibcon#about to read 6, iclass 19, count 0 2006.169.08:06:28.15#ibcon#read 6, iclass 19, count 0 2006.169.08:06:28.15#ibcon#end of sib2, iclass 19, count 0 2006.169.08:06:28.15#ibcon#*after write, iclass 19, count 0 2006.169.08:06:28.15#ibcon#*before return 0, iclass 19, count 0 2006.169.08:06:28.15#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.169.08:06:28.15#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.169.08:06:28.15#ibcon#about to clear, iclass 19 cls_cnt 0 2006.169.08:06:28.15#ibcon#cleared, iclass 19 cls_cnt 0 2006.169.08:06:28.15$vc4f8/vblo=3,656.99 2006.169.08:06:28.15#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.169.08:06:28.15#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.169.08:06:28.15#ibcon#ireg 17 cls_cnt 0 2006.169.08:06:28.15#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.169.08:06:28.15#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.169.08:06:28.15#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.169.08:06:28.15#ibcon#enter wrdev, iclass 21, count 0 2006.169.08:06:28.15#ibcon#first serial, iclass 21, count 0 2006.169.08:06:28.15#ibcon#enter sib2, iclass 21, count 0 2006.169.08:06:28.15#ibcon#flushed, iclass 21, count 0 2006.169.08:06:28.15#ibcon#about to write, iclass 21, count 0 2006.169.08:06:28.15#ibcon#wrote, iclass 21, count 0 2006.169.08:06:28.15#ibcon#about to read 3, iclass 21, count 0 2006.169.08:06:28.17#ibcon#read 3, iclass 21, count 0 2006.169.08:06:28.17#ibcon#about to read 4, iclass 21, count 0 2006.169.08:06:28.17#ibcon#read 4, iclass 21, count 0 2006.169.08:06:28.17#ibcon#about to read 5, iclass 21, count 0 2006.169.08:06:28.17#ibcon#read 5, iclass 21, count 0 2006.169.08:06:28.17#ibcon#about to read 6, iclass 21, count 0 2006.169.08:06:28.17#ibcon#read 6, iclass 21, count 0 2006.169.08:06:28.17#ibcon#end of sib2, iclass 21, count 0 2006.169.08:06:28.17#ibcon#*mode == 0, iclass 21, count 0 2006.169.08:06:28.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.169.08:06:28.17#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.08:06:28.17#ibcon#*before write, iclass 21, count 0 2006.169.08:06:28.17#ibcon#enter sib2, iclass 21, count 0 2006.169.08:06:28.17#ibcon#flushed, iclass 21, count 0 2006.169.08:06:28.17#ibcon#about to write, iclass 21, count 0 2006.169.08:06:28.17#ibcon#wrote, iclass 21, count 0 2006.169.08:06:28.17#ibcon#about to read 3, iclass 21, count 0 2006.169.08:06:28.21#ibcon#read 3, iclass 21, count 0 2006.169.08:06:28.21#ibcon#about to read 4, iclass 21, count 0 2006.169.08:06:28.21#ibcon#read 4, iclass 21, count 0 2006.169.08:06:28.21#ibcon#about to read 5, iclass 21, count 0 2006.169.08:06:28.21#ibcon#read 5, iclass 21, count 0 2006.169.08:06:28.21#ibcon#about to read 6, iclass 21, count 0 2006.169.08:06:28.21#ibcon#read 6, iclass 21, count 0 2006.169.08:06:28.21#ibcon#end of sib2, iclass 21, count 0 2006.169.08:06:28.21#ibcon#*after write, iclass 21, count 0 2006.169.08:06:28.21#ibcon#*before return 0, iclass 21, count 0 2006.169.08:06:28.21#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.169.08:06:28.21#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.169.08:06:28.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.169.08:06:28.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.169.08:06:28.21$vc4f8/vb=3,4 2006.169.08:06:28.21#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.169.08:06:28.21#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.169.08:06:28.21#ibcon#ireg 11 cls_cnt 2 2006.169.08:06:28.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.169.08:06:28.27#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.169.08:06:28.27#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.169.08:06:28.27#ibcon#enter wrdev, iclass 23, count 2 2006.169.08:06:28.27#ibcon#first serial, iclass 23, count 2 2006.169.08:06:28.27#ibcon#enter sib2, iclass 23, count 2 2006.169.08:06:28.27#ibcon#flushed, iclass 23, count 2 2006.169.08:06:28.27#ibcon#about to write, iclass 23, count 2 2006.169.08:06:28.27#ibcon#wrote, iclass 23, count 2 2006.169.08:06:28.27#ibcon#about to read 3, iclass 23, count 2 2006.169.08:06:28.29#ibcon#read 3, iclass 23, count 2 2006.169.08:06:28.29#ibcon#about to read 4, iclass 23, count 2 2006.169.08:06:28.29#ibcon#read 4, iclass 23, count 2 2006.169.08:06:28.29#ibcon#about to read 5, iclass 23, count 2 2006.169.08:06:28.29#ibcon#read 5, iclass 23, count 2 2006.169.08:06:28.29#ibcon#about to read 6, iclass 23, count 2 2006.169.08:06:28.29#ibcon#read 6, iclass 23, count 2 2006.169.08:06:28.29#ibcon#end of sib2, iclass 23, count 2 2006.169.08:06:28.29#ibcon#*mode == 0, iclass 23, count 2 2006.169.08:06:28.29#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.169.08:06:28.29#ibcon#[27=AT03-04\r\n] 2006.169.08:06:28.29#ibcon#*before write, iclass 23, count 2 2006.169.08:06:28.29#ibcon#enter sib2, iclass 23, count 2 2006.169.08:06:28.29#ibcon#flushed, iclass 23, count 2 2006.169.08:06:28.29#ibcon#about to write, iclass 23, count 2 2006.169.08:06:28.29#ibcon#wrote, iclass 23, count 2 2006.169.08:06:28.29#ibcon#about to read 3, iclass 23, count 2 2006.169.08:06:28.32#ibcon#read 3, iclass 23, count 2 2006.169.08:06:28.32#ibcon#about to read 4, iclass 23, count 2 2006.169.08:06:28.32#ibcon#read 4, iclass 23, count 2 2006.169.08:06:28.32#ibcon#about to read 5, iclass 23, count 2 2006.169.08:06:28.32#ibcon#read 5, iclass 23, count 2 2006.169.08:06:28.32#ibcon#about to read 6, iclass 23, count 2 2006.169.08:06:28.32#ibcon#read 6, iclass 23, count 2 2006.169.08:06:28.32#ibcon#end of sib2, iclass 23, count 2 2006.169.08:06:28.32#ibcon#*after write, iclass 23, count 2 2006.169.08:06:28.32#ibcon#*before return 0, iclass 23, count 2 2006.169.08:06:28.32#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.169.08:06:28.32#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.169.08:06:28.32#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.169.08:06:28.32#ibcon#ireg 7 cls_cnt 0 2006.169.08:06:28.32#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.169.08:06:28.44#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.169.08:06:28.44#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.169.08:06:28.44#ibcon#enter wrdev, iclass 23, count 0 2006.169.08:06:28.44#ibcon#first serial, iclass 23, count 0 2006.169.08:06:28.44#ibcon#enter sib2, iclass 23, count 0 2006.169.08:06:28.44#ibcon#flushed, iclass 23, count 0 2006.169.08:06:28.44#ibcon#about to write, iclass 23, count 0 2006.169.08:06:28.44#ibcon#wrote, iclass 23, count 0 2006.169.08:06:28.44#ibcon#about to read 3, iclass 23, count 0 2006.169.08:06:28.46#ibcon#read 3, iclass 23, count 0 2006.169.08:06:28.46#ibcon#about to read 4, iclass 23, count 0 2006.169.08:06:28.46#ibcon#read 4, iclass 23, count 0 2006.169.08:06:28.46#ibcon#about to read 5, iclass 23, count 0 2006.169.08:06:28.46#ibcon#read 5, iclass 23, count 0 2006.169.08:06:28.46#ibcon#about to read 6, iclass 23, count 0 2006.169.08:06:28.46#ibcon#read 6, iclass 23, count 0 2006.169.08:06:28.46#ibcon#end of sib2, iclass 23, count 0 2006.169.08:06:28.46#ibcon#*mode == 0, iclass 23, count 0 2006.169.08:06:28.46#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.169.08:06:28.46#ibcon#[27=USB\r\n] 2006.169.08:06:28.46#ibcon#*before write, iclass 23, count 0 2006.169.08:06:28.46#ibcon#enter sib2, iclass 23, count 0 2006.169.08:06:28.46#ibcon#flushed, iclass 23, count 0 2006.169.08:06:28.46#ibcon#about to write, iclass 23, count 0 2006.169.08:06:28.46#ibcon#wrote, iclass 23, count 0 2006.169.08:06:28.46#ibcon#about to read 3, iclass 23, count 0 2006.169.08:06:28.49#ibcon#read 3, iclass 23, count 0 2006.169.08:06:28.49#ibcon#about to read 4, iclass 23, count 0 2006.169.08:06:28.49#ibcon#read 4, iclass 23, count 0 2006.169.08:06:28.49#ibcon#about to read 5, iclass 23, count 0 2006.169.08:06:28.49#ibcon#read 5, iclass 23, count 0 2006.169.08:06:28.49#ibcon#about to read 6, iclass 23, count 0 2006.169.08:06:28.49#ibcon#read 6, iclass 23, count 0 2006.169.08:06:28.49#ibcon#end of sib2, iclass 23, count 0 2006.169.08:06:28.49#ibcon#*after write, iclass 23, count 0 2006.169.08:06:28.49#ibcon#*before return 0, iclass 23, count 0 2006.169.08:06:28.49#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.169.08:06:28.49#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.169.08:06:28.49#ibcon#about to clear, iclass 23 cls_cnt 0 2006.169.08:06:28.49#ibcon#cleared, iclass 23 cls_cnt 0 2006.169.08:06:28.49$vc4f8/vblo=4,712.99 2006.169.08:06:28.49#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.169.08:06:28.49#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.169.08:06:28.49#ibcon#ireg 17 cls_cnt 0 2006.169.08:06:28.49#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.169.08:06:28.49#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.169.08:06:28.49#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.169.08:06:28.49#ibcon#enter wrdev, iclass 25, count 0 2006.169.08:06:28.49#ibcon#first serial, iclass 25, count 0 2006.169.08:06:28.49#ibcon#enter sib2, iclass 25, count 0 2006.169.08:06:28.49#ibcon#flushed, iclass 25, count 0 2006.169.08:06:28.49#ibcon#about to write, iclass 25, count 0 2006.169.08:06:28.49#ibcon#wrote, iclass 25, count 0 2006.169.08:06:28.49#ibcon#about to read 3, iclass 25, count 0 2006.169.08:06:28.51#ibcon#read 3, iclass 25, count 0 2006.169.08:06:28.51#ibcon#about to read 4, iclass 25, count 0 2006.169.08:06:28.51#ibcon#read 4, iclass 25, count 0 2006.169.08:06:28.51#ibcon#about to read 5, iclass 25, count 0 2006.169.08:06:28.51#ibcon#read 5, iclass 25, count 0 2006.169.08:06:28.51#ibcon#about to read 6, iclass 25, count 0 2006.169.08:06:28.51#ibcon#read 6, iclass 25, count 0 2006.169.08:06:28.51#ibcon#end of sib2, iclass 25, count 0 2006.169.08:06:28.51#ibcon#*mode == 0, iclass 25, count 0 2006.169.08:06:28.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.169.08:06:28.51#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.08:06:28.51#ibcon#*before write, iclass 25, count 0 2006.169.08:06:28.51#ibcon#enter sib2, iclass 25, count 0 2006.169.08:06:28.51#ibcon#flushed, iclass 25, count 0 2006.169.08:06:28.51#ibcon#about to write, iclass 25, count 0 2006.169.08:06:28.51#ibcon#wrote, iclass 25, count 0 2006.169.08:06:28.51#ibcon#about to read 3, iclass 25, count 0 2006.169.08:06:28.55#ibcon#read 3, iclass 25, count 0 2006.169.08:06:28.55#ibcon#about to read 4, iclass 25, count 0 2006.169.08:06:28.55#ibcon#read 4, iclass 25, count 0 2006.169.08:06:28.55#ibcon#about to read 5, iclass 25, count 0 2006.169.08:06:28.55#ibcon#read 5, iclass 25, count 0 2006.169.08:06:28.55#ibcon#about to read 6, iclass 25, count 0 2006.169.08:06:28.55#ibcon#read 6, iclass 25, count 0 2006.169.08:06:28.55#ibcon#end of sib2, iclass 25, count 0 2006.169.08:06:28.55#ibcon#*after write, iclass 25, count 0 2006.169.08:06:28.55#ibcon#*before return 0, iclass 25, count 0 2006.169.08:06:28.55#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.169.08:06:28.55#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.169.08:06:28.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.169.08:06:28.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.169.08:06:28.55$vc4f8/vb=4,4 2006.169.08:06:28.55#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.169.08:06:28.55#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.169.08:06:28.55#ibcon#ireg 11 cls_cnt 2 2006.169.08:06:28.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.169.08:06:28.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.169.08:06:28.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.169.08:06:28.61#ibcon#enter wrdev, iclass 27, count 2 2006.169.08:06:28.61#ibcon#first serial, iclass 27, count 2 2006.169.08:06:28.61#ibcon#enter sib2, iclass 27, count 2 2006.169.08:06:28.61#ibcon#flushed, iclass 27, count 2 2006.169.08:06:28.61#ibcon#about to write, iclass 27, count 2 2006.169.08:06:28.61#ibcon#wrote, iclass 27, count 2 2006.169.08:06:28.61#ibcon#about to read 3, iclass 27, count 2 2006.169.08:06:28.63#ibcon#read 3, iclass 27, count 2 2006.169.08:06:28.63#ibcon#about to read 4, iclass 27, count 2 2006.169.08:06:28.63#ibcon#read 4, iclass 27, count 2 2006.169.08:06:28.63#ibcon#about to read 5, iclass 27, count 2 2006.169.08:06:28.63#ibcon#read 5, iclass 27, count 2 2006.169.08:06:28.63#ibcon#about to read 6, iclass 27, count 2 2006.169.08:06:28.63#ibcon#read 6, iclass 27, count 2 2006.169.08:06:28.63#ibcon#end of sib2, iclass 27, count 2 2006.169.08:06:28.63#ibcon#*mode == 0, iclass 27, count 2 2006.169.08:06:28.63#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.169.08:06:28.63#ibcon#[27=AT04-04\r\n] 2006.169.08:06:28.63#ibcon#*before write, iclass 27, count 2 2006.169.08:06:28.63#ibcon#enter sib2, iclass 27, count 2 2006.169.08:06:28.63#ibcon#flushed, iclass 27, count 2 2006.169.08:06:28.63#ibcon#about to write, iclass 27, count 2 2006.169.08:06:28.63#ibcon#wrote, iclass 27, count 2 2006.169.08:06:28.63#ibcon#about to read 3, iclass 27, count 2 2006.169.08:06:28.66#ibcon#read 3, iclass 27, count 2 2006.169.08:06:28.66#ibcon#about to read 4, iclass 27, count 2 2006.169.08:06:28.66#ibcon#read 4, iclass 27, count 2 2006.169.08:06:28.66#ibcon#about to read 5, iclass 27, count 2 2006.169.08:06:28.66#ibcon#read 5, iclass 27, count 2 2006.169.08:06:28.66#ibcon#about to read 6, iclass 27, count 2 2006.169.08:06:28.66#ibcon#read 6, iclass 27, count 2 2006.169.08:06:28.66#ibcon#end of sib2, iclass 27, count 2 2006.169.08:06:28.66#ibcon#*after write, iclass 27, count 2 2006.169.08:06:28.66#ibcon#*before return 0, iclass 27, count 2 2006.169.08:06:28.66#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.169.08:06:28.66#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.169.08:06:28.66#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.169.08:06:28.66#ibcon#ireg 7 cls_cnt 0 2006.169.08:06:28.66#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.169.08:06:28.78#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.169.08:06:28.78#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.169.08:06:28.78#ibcon#enter wrdev, iclass 27, count 0 2006.169.08:06:28.78#ibcon#first serial, iclass 27, count 0 2006.169.08:06:28.78#ibcon#enter sib2, iclass 27, count 0 2006.169.08:06:28.78#ibcon#flushed, iclass 27, count 0 2006.169.08:06:28.78#ibcon#about to write, iclass 27, count 0 2006.169.08:06:28.78#ibcon#wrote, iclass 27, count 0 2006.169.08:06:28.78#ibcon#about to read 3, iclass 27, count 0 2006.169.08:06:28.80#ibcon#read 3, iclass 27, count 0 2006.169.08:06:28.80#ibcon#about to read 4, iclass 27, count 0 2006.169.08:06:28.80#ibcon#read 4, iclass 27, count 0 2006.169.08:06:28.80#ibcon#about to read 5, iclass 27, count 0 2006.169.08:06:28.80#ibcon#read 5, iclass 27, count 0 2006.169.08:06:28.80#ibcon#about to read 6, iclass 27, count 0 2006.169.08:06:28.80#ibcon#read 6, iclass 27, count 0 2006.169.08:06:28.80#ibcon#end of sib2, iclass 27, count 0 2006.169.08:06:28.80#ibcon#*mode == 0, iclass 27, count 0 2006.169.08:06:28.80#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.169.08:06:28.80#ibcon#[27=USB\r\n] 2006.169.08:06:28.80#ibcon#*before write, iclass 27, count 0 2006.169.08:06:28.80#ibcon#enter sib2, iclass 27, count 0 2006.169.08:06:28.80#ibcon#flushed, iclass 27, count 0 2006.169.08:06:28.80#ibcon#about to write, iclass 27, count 0 2006.169.08:06:28.80#ibcon#wrote, iclass 27, count 0 2006.169.08:06:28.80#ibcon#about to read 3, iclass 27, count 0 2006.169.08:06:28.83#ibcon#read 3, iclass 27, count 0 2006.169.08:06:28.83#ibcon#about to read 4, iclass 27, count 0 2006.169.08:06:28.83#ibcon#read 4, iclass 27, count 0 2006.169.08:06:28.83#ibcon#about to read 5, iclass 27, count 0 2006.169.08:06:28.83#ibcon#read 5, iclass 27, count 0 2006.169.08:06:28.83#ibcon#about to read 6, iclass 27, count 0 2006.169.08:06:28.83#ibcon#read 6, iclass 27, count 0 2006.169.08:06:28.83#ibcon#end of sib2, iclass 27, count 0 2006.169.08:06:28.83#ibcon#*after write, iclass 27, count 0 2006.169.08:06:28.83#ibcon#*before return 0, iclass 27, count 0 2006.169.08:06:28.83#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.169.08:06:28.83#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.169.08:06:28.83#ibcon#about to clear, iclass 27 cls_cnt 0 2006.169.08:06:28.83#ibcon#cleared, iclass 27 cls_cnt 0 2006.169.08:06:28.83$vc4f8/vblo=5,744.99 2006.169.08:06:28.83#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.169.08:06:28.83#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.169.08:06:28.83#ibcon#ireg 17 cls_cnt 0 2006.169.08:06:28.83#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.169.08:06:28.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.169.08:06:28.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.169.08:06:28.83#ibcon#enter wrdev, iclass 29, count 0 2006.169.08:06:28.83#ibcon#first serial, iclass 29, count 0 2006.169.08:06:28.83#ibcon#enter sib2, iclass 29, count 0 2006.169.08:06:28.83#ibcon#flushed, iclass 29, count 0 2006.169.08:06:28.83#ibcon#about to write, iclass 29, count 0 2006.169.08:06:28.83#ibcon#wrote, iclass 29, count 0 2006.169.08:06:28.83#ibcon#about to read 3, iclass 29, count 0 2006.169.08:06:28.85#ibcon#read 3, iclass 29, count 0 2006.169.08:06:28.85#ibcon#about to read 4, iclass 29, count 0 2006.169.08:06:28.85#ibcon#read 4, iclass 29, count 0 2006.169.08:06:28.85#ibcon#about to read 5, iclass 29, count 0 2006.169.08:06:28.85#ibcon#read 5, iclass 29, count 0 2006.169.08:06:28.85#ibcon#about to read 6, iclass 29, count 0 2006.169.08:06:28.85#ibcon#read 6, iclass 29, count 0 2006.169.08:06:28.85#ibcon#end of sib2, iclass 29, count 0 2006.169.08:06:28.85#ibcon#*mode == 0, iclass 29, count 0 2006.169.08:06:28.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.169.08:06:28.85#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.08:06:28.85#ibcon#*before write, iclass 29, count 0 2006.169.08:06:28.85#ibcon#enter sib2, iclass 29, count 0 2006.169.08:06:28.85#ibcon#flushed, iclass 29, count 0 2006.169.08:06:28.85#ibcon#about to write, iclass 29, count 0 2006.169.08:06:28.85#ibcon#wrote, iclass 29, count 0 2006.169.08:06:28.85#ibcon#about to read 3, iclass 29, count 0 2006.169.08:06:28.89#ibcon#read 3, iclass 29, count 0 2006.169.08:06:28.89#ibcon#about to read 4, iclass 29, count 0 2006.169.08:06:28.89#ibcon#read 4, iclass 29, count 0 2006.169.08:06:28.89#ibcon#about to read 5, iclass 29, count 0 2006.169.08:06:28.89#ibcon#read 5, iclass 29, count 0 2006.169.08:06:28.89#ibcon#about to read 6, iclass 29, count 0 2006.169.08:06:28.89#ibcon#read 6, iclass 29, count 0 2006.169.08:06:28.89#ibcon#end of sib2, iclass 29, count 0 2006.169.08:06:28.89#ibcon#*after write, iclass 29, count 0 2006.169.08:06:28.89#ibcon#*before return 0, iclass 29, count 0 2006.169.08:06:28.89#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.169.08:06:28.89#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.169.08:06:28.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.169.08:06:28.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.169.08:06:28.89$vc4f8/vb=5,4 2006.169.08:06:28.89#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.169.08:06:28.89#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.169.08:06:28.89#ibcon#ireg 11 cls_cnt 2 2006.169.08:06:28.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.169.08:06:28.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.169.08:06:28.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.169.08:06:28.95#ibcon#enter wrdev, iclass 31, count 2 2006.169.08:06:28.95#ibcon#first serial, iclass 31, count 2 2006.169.08:06:28.95#ibcon#enter sib2, iclass 31, count 2 2006.169.08:06:28.95#ibcon#flushed, iclass 31, count 2 2006.169.08:06:28.95#ibcon#about to write, iclass 31, count 2 2006.169.08:06:28.95#ibcon#wrote, iclass 31, count 2 2006.169.08:06:28.95#ibcon#about to read 3, iclass 31, count 2 2006.169.08:06:28.97#ibcon#read 3, iclass 31, count 2 2006.169.08:06:28.97#ibcon#about to read 4, iclass 31, count 2 2006.169.08:06:28.97#ibcon#read 4, iclass 31, count 2 2006.169.08:06:28.97#ibcon#about to read 5, iclass 31, count 2 2006.169.08:06:28.97#ibcon#read 5, iclass 31, count 2 2006.169.08:06:28.97#ibcon#about to read 6, iclass 31, count 2 2006.169.08:06:28.97#ibcon#read 6, iclass 31, count 2 2006.169.08:06:28.97#ibcon#end of sib2, iclass 31, count 2 2006.169.08:06:28.97#ibcon#*mode == 0, iclass 31, count 2 2006.169.08:06:28.97#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.169.08:06:28.97#ibcon#[27=AT05-04\r\n] 2006.169.08:06:28.97#ibcon#*before write, iclass 31, count 2 2006.169.08:06:28.97#ibcon#enter sib2, iclass 31, count 2 2006.169.08:06:28.97#ibcon#flushed, iclass 31, count 2 2006.169.08:06:28.97#ibcon#about to write, iclass 31, count 2 2006.169.08:06:28.97#ibcon#wrote, iclass 31, count 2 2006.169.08:06:28.97#ibcon#about to read 3, iclass 31, count 2 2006.169.08:06:29.00#ibcon#read 3, iclass 31, count 2 2006.169.08:06:29.00#ibcon#about to read 4, iclass 31, count 2 2006.169.08:06:29.00#ibcon#read 4, iclass 31, count 2 2006.169.08:06:29.00#ibcon#about to read 5, iclass 31, count 2 2006.169.08:06:29.00#ibcon#read 5, iclass 31, count 2 2006.169.08:06:29.00#ibcon#about to read 6, iclass 31, count 2 2006.169.08:06:29.00#ibcon#read 6, iclass 31, count 2 2006.169.08:06:29.00#ibcon#end of sib2, iclass 31, count 2 2006.169.08:06:29.00#ibcon#*after write, iclass 31, count 2 2006.169.08:06:29.00#ibcon#*before return 0, iclass 31, count 2 2006.169.08:06:29.00#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.169.08:06:29.00#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.169.08:06:29.00#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.169.08:06:29.00#ibcon#ireg 7 cls_cnt 0 2006.169.08:06:29.00#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.169.08:06:29.12#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.169.08:06:29.12#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.169.08:06:29.12#ibcon#enter wrdev, iclass 31, count 0 2006.169.08:06:29.12#ibcon#first serial, iclass 31, count 0 2006.169.08:06:29.12#ibcon#enter sib2, iclass 31, count 0 2006.169.08:06:29.12#ibcon#flushed, iclass 31, count 0 2006.169.08:06:29.12#ibcon#about to write, iclass 31, count 0 2006.169.08:06:29.12#ibcon#wrote, iclass 31, count 0 2006.169.08:06:29.12#ibcon#about to read 3, iclass 31, count 0 2006.169.08:06:29.14#ibcon#read 3, iclass 31, count 0 2006.169.08:06:29.14#ibcon#about to read 4, iclass 31, count 0 2006.169.08:06:29.14#ibcon#read 4, iclass 31, count 0 2006.169.08:06:29.14#ibcon#about to read 5, iclass 31, count 0 2006.169.08:06:29.14#ibcon#read 5, iclass 31, count 0 2006.169.08:06:29.14#ibcon#about to read 6, iclass 31, count 0 2006.169.08:06:29.14#ibcon#read 6, iclass 31, count 0 2006.169.08:06:29.14#ibcon#end of sib2, iclass 31, count 0 2006.169.08:06:29.14#ibcon#*mode == 0, iclass 31, count 0 2006.169.08:06:29.14#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.169.08:06:29.14#ibcon#[27=USB\r\n] 2006.169.08:06:29.14#ibcon#*before write, iclass 31, count 0 2006.169.08:06:29.14#ibcon#enter sib2, iclass 31, count 0 2006.169.08:06:29.14#ibcon#flushed, iclass 31, count 0 2006.169.08:06:29.14#ibcon#about to write, iclass 31, count 0 2006.169.08:06:29.14#ibcon#wrote, iclass 31, count 0 2006.169.08:06:29.14#ibcon#about to read 3, iclass 31, count 0 2006.169.08:06:29.17#ibcon#read 3, iclass 31, count 0 2006.169.08:06:29.17#ibcon#about to read 4, iclass 31, count 0 2006.169.08:06:29.17#ibcon#read 4, iclass 31, count 0 2006.169.08:06:29.17#ibcon#about to read 5, iclass 31, count 0 2006.169.08:06:29.17#ibcon#read 5, iclass 31, count 0 2006.169.08:06:29.17#ibcon#about to read 6, iclass 31, count 0 2006.169.08:06:29.17#ibcon#read 6, iclass 31, count 0 2006.169.08:06:29.17#ibcon#end of sib2, iclass 31, count 0 2006.169.08:06:29.17#ibcon#*after write, iclass 31, count 0 2006.169.08:06:29.17#ibcon#*before return 0, iclass 31, count 0 2006.169.08:06:29.17#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.169.08:06:29.17#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.169.08:06:29.17#ibcon#about to clear, iclass 31 cls_cnt 0 2006.169.08:06:29.17#ibcon#cleared, iclass 31 cls_cnt 0 2006.169.08:06:29.17$vc4f8/vblo=6,752.99 2006.169.08:06:29.17#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.169.08:06:29.17#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.169.08:06:29.17#ibcon#ireg 17 cls_cnt 0 2006.169.08:06:29.17#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:06:29.17#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:06:29.17#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:06:29.17#ibcon#enter wrdev, iclass 33, count 0 2006.169.08:06:29.17#ibcon#first serial, iclass 33, count 0 2006.169.08:06:29.17#ibcon#enter sib2, iclass 33, count 0 2006.169.08:06:29.17#ibcon#flushed, iclass 33, count 0 2006.169.08:06:29.17#ibcon#about to write, iclass 33, count 0 2006.169.08:06:29.17#ibcon#wrote, iclass 33, count 0 2006.169.08:06:29.17#ibcon#about to read 3, iclass 33, count 0 2006.169.08:06:29.19#ibcon#read 3, iclass 33, count 0 2006.169.08:06:29.19#ibcon#about to read 4, iclass 33, count 0 2006.169.08:06:29.19#ibcon#read 4, iclass 33, count 0 2006.169.08:06:29.19#ibcon#about to read 5, iclass 33, count 0 2006.169.08:06:29.19#ibcon#read 5, iclass 33, count 0 2006.169.08:06:29.19#ibcon#about to read 6, iclass 33, count 0 2006.169.08:06:29.19#ibcon#read 6, iclass 33, count 0 2006.169.08:06:29.19#ibcon#end of sib2, iclass 33, count 0 2006.169.08:06:29.19#ibcon#*mode == 0, iclass 33, count 0 2006.169.08:06:29.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.169.08:06:29.19#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.08:06:29.19#ibcon#*before write, iclass 33, count 0 2006.169.08:06:29.19#ibcon#enter sib2, iclass 33, count 0 2006.169.08:06:29.19#ibcon#flushed, iclass 33, count 0 2006.169.08:06:29.19#ibcon#about to write, iclass 33, count 0 2006.169.08:06:29.19#ibcon#wrote, iclass 33, count 0 2006.169.08:06:29.19#ibcon#about to read 3, iclass 33, count 0 2006.169.08:06:29.23#ibcon#read 3, iclass 33, count 0 2006.169.08:06:29.23#ibcon#about to read 4, iclass 33, count 0 2006.169.08:06:29.23#ibcon#read 4, iclass 33, count 0 2006.169.08:06:29.23#ibcon#about to read 5, iclass 33, count 0 2006.169.08:06:29.23#ibcon#read 5, iclass 33, count 0 2006.169.08:06:29.23#ibcon#about to read 6, iclass 33, count 0 2006.169.08:06:29.23#ibcon#read 6, iclass 33, count 0 2006.169.08:06:29.23#ibcon#end of sib2, iclass 33, count 0 2006.169.08:06:29.23#ibcon#*after write, iclass 33, count 0 2006.169.08:06:29.23#ibcon#*before return 0, iclass 33, count 0 2006.169.08:06:29.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:06:29.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:06:29.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.169.08:06:29.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.169.08:06:29.23$vc4f8/vb=6,4 2006.169.08:06:29.23#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.169.08:06:29.23#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.169.08:06:29.23#ibcon#ireg 11 cls_cnt 2 2006.169.08:06:29.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.169.08:06:29.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.169.08:06:29.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.169.08:06:29.29#ibcon#enter wrdev, iclass 35, count 2 2006.169.08:06:29.29#ibcon#first serial, iclass 35, count 2 2006.169.08:06:29.29#ibcon#enter sib2, iclass 35, count 2 2006.169.08:06:29.29#ibcon#flushed, iclass 35, count 2 2006.169.08:06:29.29#ibcon#about to write, iclass 35, count 2 2006.169.08:06:29.29#ibcon#wrote, iclass 35, count 2 2006.169.08:06:29.29#ibcon#about to read 3, iclass 35, count 2 2006.169.08:06:29.31#ibcon#read 3, iclass 35, count 2 2006.169.08:06:29.31#ibcon#about to read 4, iclass 35, count 2 2006.169.08:06:29.31#ibcon#read 4, iclass 35, count 2 2006.169.08:06:29.31#ibcon#about to read 5, iclass 35, count 2 2006.169.08:06:29.31#ibcon#read 5, iclass 35, count 2 2006.169.08:06:29.31#ibcon#about to read 6, iclass 35, count 2 2006.169.08:06:29.31#ibcon#read 6, iclass 35, count 2 2006.169.08:06:29.31#ibcon#end of sib2, iclass 35, count 2 2006.169.08:06:29.31#ibcon#*mode == 0, iclass 35, count 2 2006.169.08:06:29.31#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.169.08:06:29.31#ibcon#[27=AT06-04\r\n] 2006.169.08:06:29.31#ibcon#*before write, iclass 35, count 2 2006.169.08:06:29.31#ibcon#enter sib2, iclass 35, count 2 2006.169.08:06:29.31#ibcon#flushed, iclass 35, count 2 2006.169.08:06:29.31#ibcon#about to write, iclass 35, count 2 2006.169.08:06:29.31#ibcon#wrote, iclass 35, count 2 2006.169.08:06:29.31#ibcon#about to read 3, iclass 35, count 2 2006.169.08:06:29.34#ibcon#read 3, iclass 35, count 2 2006.169.08:06:29.34#ibcon#about to read 4, iclass 35, count 2 2006.169.08:06:29.34#ibcon#read 4, iclass 35, count 2 2006.169.08:06:29.34#ibcon#about to read 5, iclass 35, count 2 2006.169.08:06:29.34#ibcon#read 5, iclass 35, count 2 2006.169.08:06:29.34#ibcon#about to read 6, iclass 35, count 2 2006.169.08:06:29.34#ibcon#read 6, iclass 35, count 2 2006.169.08:06:29.34#ibcon#end of sib2, iclass 35, count 2 2006.169.08:06:29.34#ibcon#*after write, iclass 35, count 2 2006.169.08:06:29.34#ibcon#*before return 0, iclass 35, count 2 2006.169.08:06:29.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.169.08:06:29.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.169.08:06:29.34#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.169.08:06:29.34#ibcon#ireg 7 cls_cnt 0 2006.169.08:06:29.34#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.169.08:06:29.46#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.169.08:06:29.46#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.169.08:06:29.46#ibcon#enter wrdev, iclass 35, count 0 2006.169.08:06:29.46#ibcon#first serial, iclass 35, count 0 2006.169.08:06:29.46#ibcon#enter sib2, iclass 35, count 0 2006.169.08:06:29.46#ibcon#flushed, iclass 35, count 0 2006.169.08:06:29.46#ibcon#about to write, iclass 35, count 0 2006.169.08:06:29.46#ibcon#wrote, iclass 35, count 0 2006.169.08:06:29.46#ibcon#about to read 3, iclass 35, count 0 2006.169.08:06:29.48#ibcon#read 3, iclass 35, count 0 2006.169.08:06:29.48#ibcon#about to read 4, iclass 35, count 0 2006.169.08:06:29.48#ibcon#read 4, iclass 35, count 0 2006.169.08:06:29.48#ibcon#about to read 5, iclass 35, count 0 2006.169.08:06:29.48#ibcon#read 5, iclass 35, count 0 2006.169.08:06:29.48#ibcon#about to read 6, iclass 35, count 0 2006.169.08:06:29.48#ibcon#read 6, iclass 35, count 0 2006.169.08:06:29.48#ibcon#end of sib2, iclass 35, count 0 2006.169.08:06:29.48#ibcon#*mode == 0, iclass 35, count 0 2006.169.08:06:29.48#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.169.08:06:29.48#ibcon#[27=USB\r\n] 2006.169.08:06:29.48#ibcon#*before write, iclass 35, count 0 2006.169.08:06:29.48#ibcon#enter sib2, iclass 35, count 0 2006.169.08:06:29.48#ibcon#flushed, iclass 35, count 0 2006.169.08:06:29.48#ibcon#about to write, iclass 35, count 0 2006.169.08:06:29.48#ibcon#wrote, iclass 35, count 0 2006.169.08:06:29.48#ibcon#about to read 3, iclass 35, count 0 2006.169.08:06:29.51#ibcon#read 3, iclass 35, count 0 2006.169.08:06:29.51#ibcon#about to read 4, iclass 35, count 0 2006.169.08:06:29.51#ibcon#read 4, iclass 35, count 0 2006.169.08:06:29.51#ibcon#about to read 5, iclass 35, count 0 2006.169.08:06:29.51#ibcon#read 5, iclass 35, count 0 2006.169.08:06:29.51#ibcon#about to read 6, iclass 35, count 0 2006.169.08:06:29.51#ibcon#read 6, iclass 35, count 0 2006.169.08:06:29.51#ibcon#end of sib2, iclass 35, count 0 2006.169.08:06:29.51#ibcon#*after write, iclass 35, count 0 2006.169.08:06:29.51#ibcon#*before return 0, iclass 35, count 0 2006.169.08:06:29.51#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.169.08:06:29.51#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.169.08:06:29.51#ibcon#about to clear, iclass 35 cls_cnt 0 2006.169.08:06:29.51#ibcon#cleared, iclass 35 cls_cnt 0 2006.169.08:06:29.51$vc4f8/vabw=wide 2006.169.08:06:29.51#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.169.08:06:29.51#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.169.08:06:29.51#ibcon#ireg 8 cls_cnt 0 2006.169.08:06:29.51#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:06:29.51#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:06:29.51#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:06:29.51#ibcon#enter wrdev, iclass 37, count 0 2006.169.08:06:29.51#ibcon#first serial, iclass 37, count 0 2006.169.08:06:29.51#ibcon#enter sib2, iclass 37, count 0 2006.169.08:06:29.51#ibcon#flushed, iclass 37, count 0 2006.169.08:06:29.51#ibcon#about to write, iclass 37, count 0 2006.169.08:06:29.51#ibcon#wrote, iclass 37, count 0 2006.169.08:06:29.51#ibcon#about to read 3, iclass 37, count 0 2006.169.08:06:29.53#ibcon#read 3, iclass 37, count 0 2006.169.08:06:29.53#ibcon#about to read 4, iclass 37, count 0 2006.169.08:06:29.53#ibcon#read 4, iclass 37, count 0 2006.169.08:06:29.53#ibcon#about to read 5, iclass 37, count 0 2006.169.08:06:29.53#ibcon#read 5, iclass 37, count 0 2006.169.08:06:29.53#ibcon#about to read 6, iclass 37, count 0 2006.169.08:06:29.53#ibcon#read 6, iclass 37, count 0 2006.169.08:06:29.53#ibcon#end of sib2, iclass 37, count 0 2006.169.08:06:29.53#ibcon#*mode == 0, iclass 37, count 0 2006.169.08:06:29.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.169.08:06:29.53#ibcon#[25=BW32\r\n] 2006.169.08:06:29.53#ibcon#*before write, iclass 37, count 0 2006.169.08:06:29.53#ibcon#enter sib2, iclass 37, count 0 2006.169.08:06:29.53#ibcon#flushed, iclass 37, count 0 2006.169.08:06:29.53#ibcon#about to write, iclass 37, count 0 2006.169.08:06:29.53#ibcon#wrote, iclass 37, count 0 2006.169.08:06:29.53#ibcon#about to read 3, iclass 37, count 0 2006.169.08:06:29.56#ibcon#read 3, iclass 37, count 0 2006.169.08:06:29.56#ibcon#about to read 4, iclass 37, count 0 2006.169.08:06:29.56#ibcon#read 4, iclass 37, count 0 2006.169.08:06:29.56#ibcon#about to read 5, iclass 37, count 0 2006.169.08:06:29.56#ibcon#read 5, iclass 37, count 0 2006.169.08:06:29.56#ibcon#about to read 6, iclass 37, count 0 2006.169.08:06:29.56#ibcon#read 6, iclass 37, count 0 2006.169.08:06:29.56#ibcon#end of sib2, iclass 37, count 0 2006.169.08:06:29.56#ibcon#*after write, iclass 37, count 0 2006.169.08:06:29.56#ibcon#*before return 0, iclass 37, count 0 2006.169.08:06:29.56#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:06:29.56#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:06:29.56#ibcon#about to clear, iclass 37 cls_cnt 0 2006.169.08:06:29.56#ibcon#cleared, iclass 37 cls_cnt 0 2006.169.08:06:29.56$vc4f8/vbbw=wide 2006.169.08:06:29.56#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.169.08:06:29.56#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.169.08:06:29.56#ibcon#ireg 8 cls_cnt 0 2006.169.08:06:29.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:06:29.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:06:29.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:06:29.63#ibcon#enter wrdev, iclass 39, count 0 2006.169.08:06:29.63#ibcon#first serial, iclass 39, count 0 2006.169.08:06:29.63#ibcon#enter sib2, iclass 39, count 0 2006.169.08:06:29.63#ibcon#flushed, iclass 39, count 0 2006.169.08:06:29.63#ibcon#about to write, iclass 39, count 0 2006.169.08:06:29.63#ibcon#wrote, iclass 39, count 0 2006.169.08:06:29.63#ibcon#about to read 3, iclass 39, count 0 2006.169.08:06:29.65#ibcon#read 3, iclass 39, count 0 2006.169.08:06:29.65#ibcon#about to read 4, iclass 39, count 0 2006.169.08:06:29.65#ibcon#read 4, iclass 39, count 0 2006.169.08:06:29.65#ibcon#about to read 5, iclass 39, count 0 2006.169.08:06:29.65#ibcon#read 5, iclass 39, count 0 2006.169.08:06:29.65#ibcon#about to read 6, iclass 39, count 0 2006.169.08:06:29.65#ibcon#read 6, iclass 39, count 0 2006.169.08:06:29.65#ibcon#end of sib2, iclass 39, count 0 2006.169.08:06:29.65#ibcon#*mode == 0, iclass 39, count 0 2006.169.08:06:29.65#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.169.08:06:29.65#ibcon#[27=BW32\r\n] 2006.169.08:06:29.65#ibcon#*before write, iclass 39, count 0 2006.169.08:06:29.65#ibcon#enter sib2, iclass 39, count 0 2006.169.08:06:29.65#ibcon#flushed, iclass 39, count 0 2006.169.08:06:29.65#ibcon#about to write, iclass 39, count 0 2006.169.08:06:29.65#ibcon#wrote, iclass 39, count 0 2006.169.08:06:29.65#ibcon#about to read 3, iclass 39, count 0 2006.169.08:06:29.68#ibcon#read 3, iclass 39, count 0 2006.169.08:06:29.68#ibcon#about to read 4, iclass 39, count 0 2006.169.08:06:29.68#ibcon#read 4, iclass 39, count 0 2006.169.08:06:29.68#ibcon#about to read 5, iclass 39, count 0 2006.169.08:06:29.68#ibcon#read 5, iclass 39, count 0 2006.169.08:06:29.68#ibcon#about to read 6, iclass 39, count 0 2006.169.08:06:29.68#ibcon#read 6, iclass 39, count 0 2006.169.08:06:29.68#ibcon#end of sib2, iclass 39, count 0 2006.169.08:06:29.68#ibcon#*after write, iclass 39, count 0 2006.169.08:06:29.68#ibcon#*before return 0, iclass 39, count 0 2006.169.08:06:29.68#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:06:29.68#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:06:29.68#ibcon#about to clear, iclass 39 cls_cnt 0 2006.169.08:06:29.68#ibcon#cleared, iclass 39 cls_cnt 0 2006.169.08:06:29.68$4f8m12a/ifd4f 2006.169.08:06:29.68$ifd4f/lo= 2006.169.08:06:29.68$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.08:06:29.68$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.08:06:29.68$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.08:06:29.68$ifd4f/patch= 2006.169.08:06:29.68$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.08:06:29.68$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.08:06:29.68$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.08:06:29.68$4f8m12a/"form=m,16.000,1:2 2006.169.08:06:29.68$4f8m12a/"tpicd 2006.169.08:06:29.68$4f8m12a/echo=off 2006.169.08:06:29.68$4f8m12a/xlog=off 2006.169.08:06:29.68:!2006.169.08:06:40 2006.169.08:06:40.00:preob 2006.169.08:06:41.14/onsource/TRACKING 2006.169.08:06:41.14:!2006.169.08:06:50 2006.169.08:06:50.00:data_valid=on 2006.169.08:06:50.00:midob 2006.169.08:06:50.14/onsource/TRACKING 2006.169.08:06:50.14/wx/18.12,1003.9,100 2006.169.08:06:50.33/cable/+6.5291E-03 2006.169.08:06:51.42/va/01,08,usb,yes,45,47 2006.169.08:06:51.42/va/02,07,usb,yes,45,47 2006.169.08:06:51.42/va/03,06,usb,yes,48,48 2006.169.08:06:51.42/va/04,07,usb,yes,47,50 2006.169.08:06:51.42/va/05,07,usb,yes,51,54 2006.169.08:06:51.42/va/06,06,usb,yes,50,50 2006.169.08:06:51.42/va/07,06,usb,yes,51,51 2006.169.08:06:51.42/va/08,07,usb,yes,48,47 2006.169.08:06:51.65/valo/01,532.99,yes,locked 2006.169.08:06:51.65/valo/02,572.99,yes,locked 2006.169.08:06:51.65/valo/03,672.99,yes,locked 2006.169.08:06:51.65/valo/04,832.99,yes,locked 2006.169.08:06:51.65/valo/05,652.99,yes,locked 2006.169.08:06:51.65/valo/06,772.99,yes,locked 2006.169.08:06:51.65/valo/07,832.99,yes,locked 2006.169.08:06:51.65/valo/08,852.99,yes,locked 2006.169.08:06:52.74/vb/01,04,usb,yes,30,29 2006.169.08:06:52.74/vb/02,04,usb,yes,32,33 2006.169.08:06:52.74/vb/03,04,usb,yes,28,32 2006.169.08:06:52.74/vb/04,04,usb,yes,29,29 2006.169.08:06:52.74/vb/05,04,usb,yes,28,32 2006.169.08:06:52.74/vb/06,04,usb,yes,29,32 2006.169.08:06:52.74/vb/07,04,usb,yes,31,31 2006.169.08:06:52.74/vb/08,04,usb,yes,28,32 2006.169.08:06:52.98/vblo/01,632.99,yes,locked 2006.169.08:06:52.98/vblo/02,640.99,yes,locked 2006.169.08:06:52.98/vblo/03,656.99,yes,locked 2006.169.08:06:52.98/vblo/04,712.99,yes,locked 2006.169.08:06:52.98/vblo/05,744.99,yes,locked 2006.169.08:06:52.98/vblo/06,752.99,yes,locked 2006.169.08:06:52.98/vblo/07,734.99,yes,locked 2006.169.08:06:52.98/vblo/08,744.99,yes,locked 2006.169.08:06:53.13/vabw/8 2006.169.08:06:53.28/vbbw/8 2006.169.08:06:53.37/xfe/off,on,14.5 2006.169.08:06:53.74/ifatt/23,28,28,28 2006.169.08:06:54.07/fmout-gps/S +4.20E-07 2006.169.08:06:54.11:!2006.169.08:07:50 2006.169.08:07:50.00:data_valid=off 2006.169.08:07:50.00:postob 2006.169.08:07:50.16/cable/+6.5300E-03 2006.169.08:07:50.16/wx/18.13,1003.9,100 2006.169.08:07:51.08/fmout-gps/S +4.20E-07 2006.169.08:07:51.08:scan_name=169-0808,k06169,60 2006.169.08:07:51.09:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.169.08:07:51.14#flagr#flagr/antenna,new-source 2006.169.08:07:52.14:checkk5 2006.169.08:07:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.169.08:07:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.169.08:07:56.91/chk_autoobs//k5ts3?ERROR: timeout happened! 2006.169.08:07:57.29/chk_autoobs//k5ts4/ autoobs is running! 2006.169.08:07:57.66/chk_obsdata//k5ts1/T1690806??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.08:07:58.03/chk_obsdata//k5ts2/T1690806??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.08:08:05.10/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.08:08:05.47/chk_obsdata//k5ts4/T1690806??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.08:08:06.17/k5log//k5ts1_log_newline 2006.169.08:08:06.85/k5log//k5ts2_log_newline 2006.169.08:08:12.14#trakl#Source acquired 2006.169.08:08:12.14#flagr#flagr/antenna,acquired 2006.169.08:08:13.95/k5log//k5ts3?ERROR: timeout happened! 2006.169.08:08:14.64/k5log//k5ts4_log_newline 2006.169.08:08:14.81/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.08:08:14.81:4f8m12a=2 2006.169.08:08:14.81$4f8m12a/echo=on 2006.169.08:08:14.81$4f8m12a/pcalon 2006.169.08:08:14.81$pcalon/"no phase cal control is implemented here 2006.169.08:08:14.81$4f8m12a/"tpicd=stop 2006.169.08:08:14.81$4f8m12a/vc4f8 2006.169.08:08:14.81$vc4f8/valo=1,532.99 2006.169.08:08:14.81#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.169.08:08:14.81#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.169.08:08:14.81#ibcon#ireg 17 cls_cnt 0 2006.169.08:08:14.81#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.169.08:08:14.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.169.08:08:14.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.169.08:08:14.82#ibcon#enter wrdev, iclass 10, count 0 2006.169.08:08:14.82#ibcon#first serial, iclass 10, count 0 2006.169.08:08:14.82#ibcon#enter sib2, iclass 10, count 0 2006.169.08:08:14.82#ibcon#flushed, iclass 10, count 0 2006.169.08:08:14.82#ibcon#about to write, iclass 10, count 0 2006.169.08:08:14.82#ibcon#wrote, iclass 10, count 0 2006.169.08:08:14.82#ibcon#about to read 3, iclass 10, count 0 2006.169.08:08:14.83#ibcon#read 3, iclass 10, count 0 2006.169.08:08:14.83#ibcon#about to read 4, iclass 10, count 0 2006.169.08:08:14.83#ibcon#read 4, iclass 10, count 0 2006.169.08:08:14.83#ibcon#about to read 5, iclass 10, count 0 2006.169.08:08:14.83#ibcon#read 5, iclass 10, count 0 2006.169.08:08:14.83#ibcon#about to read 6, iclass 10, count 0 2006.169.08:08:14.83#ibcon#read 6, iclass 10, count 0 2006.169.08:08:14.83#ibcon#end of sib2, iclass 10, count 0 2006.169.08:08:14.83#ibcon#*mode == 0, iclass 10, count 0 2006.169.08:08:14.83#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.169.08:08:14.83#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.08:08:14.83#ibcon#*before write, iclass 10, count 0 2006.169.08:08:14.83#ibcon#enter sib2, iclass 10, count 0 2006.169.08:08:14.83#ibcon#flushed, iclass 10, count 0 2006.169.08:08:14.83#ibcon#about to write, iclass 10, count 0 2006.169.08:08:14.83#ibcon#wrote, iclass 10, count 0 2006.169.08:08:14.83#ibcon#about to read 3, iclass 10, count 0 2006.169.08:08:14.88#ibcon#read 3, iclass 10, count 0 2006.169.08:08:14.88#ibcon#about to read 4, iclass 10, count 0 2006.169.08:08:14.88#ibcon#read 4, iclass 10, count 0 2006.169.08:08:14.88#ibcon#about to read 5, iclass 10, count 0 2006.169.08:08:14.88#ibcon#read 5, iclass 10, count 0 2006.169.08:08:14.88#ibcon#about to read 6, iclass 10, count 0 2006.169.08:08:14.88#ibcon#read 6, iclass 10, count 0 2006.169.08:08:14.88#ibcon#end of sib2, iclass 10, count 0 2006.169.08:08:14.88#ibcon#*after write, iclass 10, count 0 2006.169.08:08:14.88#ibcon#*before return 0, iclass 10, count 0 2006.169.08:08:14.88#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.169.08:08:14.88#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.169.08:08:14.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.169.08:08:14.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.169.08:08:14.88$vc4f8/va=1,8 2006.169.08:08:14.88#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.169.08:08:14.88#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.169.08:08:14.88#ibcon#ireg 11 cls_cnt 2 2006.169.08:08:14.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.169.08:08:14.88#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.169.08:08:14.88#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.169.08:08:14.88#ibcon#enter wrdev, iclass 12, count 2 2006.169.08:08:14.88#ibcon#first serial, iclass 12, count 2 2006.169.08:08:14.88#ibcon#enter sib2, iclass 12, count 2 2006.169.08:08:14.88#ibcon#flushed, iclass 12, count 2 2006.169.08:08:14.88#ibcon#about to write, iclass 12, count 2 2006.169.08:08:14.88#ibcon#wrote, iclass 12, count 2 2006.169.08:08:14.88#ibcon#about to read 3, iclass 12, count 2 2006.169.08:08:14.90#ibcon#read 3, iclass 12, count 2 2006.169.08:08:14.90#ibcon#about to read 4, iclass 12, count 2 2006.169.08:08:14.90#ibcon#read 4, iclass 12, count 2 2006.169.08:08:14.90#ibcon#about to read 5, iclass 12, count 2 2006.169.08:08:14.90#ibcon#read 5, iclass 12, count 2 2006.169.08:08:14.90#ibcon#about to read 6, iclass 12, count 2 2006.169.08:08:14.90#ibcon#read 6, iclass 12, count 2 2006.169.08:08:14.90#ibcon#end of sib2, iclass 12, count 2 2006.169.08:08:14.90#ibcon#*mode == 0, iclass 12, count 2 2006.169.08:08:14.90#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.169.08:08:14.90#ibcon#[25=AT01-08\r\n] 2006.169.08:08:14.90#ibcon#*before write, iclass 12, count 2 2006.169.08:08:14.90#ibcon#enter sib2, iclass 12, count 2 2006.169.08:08:14.90#ibcon#flushed, iclass 12, count 2 2006.169.08:08:14.90#ibcon#about to write, iclass 12, count 2 2006.169.08:08:14.90#ibcon#wrote, iclass 12, count 2 2006.169.08:08:14.90#ibcon#about to read 3, iclass 12, count 2 2006.169.08:08:14.93#ibcon#read 3, iclass 12, count 2 2006.169.08:08:14.93#ibcon#about to read 4, iclass 12, count 2 2006.169.08:08:14.93#ibcon#read 4, iclass 12, count 2 2006.169.08:08:14.93#ibcon#about to read 5, iclass 12, count 2 2006.169.08:08:14.93#ibcon#read 5, iclass 12, count 2 2006.169.08:08:14.93#ibcon#about to read 6, iclass 12, count 2 2006.169.08:08:14.93#ibcon#read 6, iclass 12, count 2 2006.169.08:08:14.93#ibcon#end of sib2, iclass 12, count 2 2006.169.08:08:14.93#ibcon#*after write, iclass 12, count 2 2006.169.08:08:14.93#ibcon#*before return 0, iclass 12, count 2 2006.169.08:08:14.93#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.169.08:08:14.93#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.169.08:08:14.93#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.169.08:08:14.93#ibcon#ireg 7 cls_cnt 0 2006.169.08:08:14.93#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.169.08:08:15.05#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.169.08:08:15.05#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.169.08:08:15.05#ibcon#enter wrdev, iclass 12, count 0 2006.169.08:08:15.05#ibcon#first serial, iclass 12, count 0 2006.169.08:08:15.05#ibcon#enter sib2, iclass 12, count 0 2006.169.08:08:15.05#ibcon#flushed, iclass 12, count 0 2006.169.08:08:15.05#ibcon#about to write, iclass 12, count 0 2006.169.08:08:15.05#ibcon#wrote, iclass 12, count 0 2006.169.08:08:15.05#ibcon#about to read 3, iclass 12, count 0 2006.169.08:08:15.08#ibcon#read 3, iclass 12, count 0 2006.169.08:08:15.08#ibcon#about to read 4, iclass 12, count 0 2006.169.08:08:15.08#ibcon#read 4, iclass 12, count 0 2006.169.08:08:15.08#ibcon#about to read 5, iclass 12, count 0 2006.169.08:08:15.08#ibcon#read 5, iclass 12, count 0 2006.169.08:08:15.08#ibcon#about to read 6, iclass 12, count 0 2006.169.08:08:15.08#ibcon#read 6, iclass 12, count 0 2006.169.08:08:15.08#ibcon#end of sib2, iclass 12, count 0 2006.169.08:08:15.08#ibcon#*mode == 0, iclass 12, count 0 2006.169.08:08:15.08#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.169.08:08:15.08#ibcon#[25=USB\r\n] 2006.169.08:08:15.08#ibcon#*before write, iclass 12, count 0 2006.169.08:08:15.08#ibcon#enter sib2, iclass 12, count 0 2006.169.08:08:15.08#ibcon#flushed, iclass 12, count 0 2006.169.08:08:15.08#ibcon#about to write, iclass 12, count 0 2006.169.08:08:15.08#ibcon#wrote, iclass 12, count 0 2006.169.08:08:15.08#ibcon#about to read 3, iclass 12, count 0 2006.169.08:08:15.12#ibcon#read 3, iclass 12, count 0 2006.169.08:08:15.12#ibcon#about to read 4, iclass 12, count 0 2006.169.08:08:15.12#ibcon#read 4, iclass 12, count 0 2006.169.08:08:15.12#ibcon#about to read 5, iclass 12, count 0 2006.169.08:08:15.12#ibcon#read 5, iclass 12, count 0 2006.169.08:08:15.12#ibcon#about to read 6, iclass 12, count 0 2006.169.08:08:15.12#ibcon#read 6, iclass 12, count 0 2006.169.08:08:15.12#ibcon#end of sib2, iclass 12, count 0 2006.169.08:08:15.12#ibcon#*after write, iclass 12, count 0 2006.169.08:08:15.12#ibcon#*before return 0, iclass 12, count 0 2006.169.08:08:15.12#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.169.08:08:15.12#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.169.08:08:15.12#ibcon#about to clear, iclass 12 cls_cnt 0 2006.169.08:08:15.12#ibcon#cleared, iclass 12 cls_cnt 0 2006.169.08:08:15.12$vc4f8/valo=2,572.99 2006.169.08:08:15.12#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.169.08:08:15.12#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.169.08:08:15.12#ibcon#ireg 17 cls_cnt 0 2006.169.08:08:15.12#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:08:15.12#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:08:15.12#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:08:15.12#ibcon#enter wrdev, iclass 14, count 0 2006.169.08:08:15.12#ibcon#first serial, iclass 14, count 0 2006.169.08:08:15.12#ibcon#enter sib2, iclass 14, count 0 2006.169.08:08:15.12#ibcon#flushed, iclass 14, count 0 2006.169.08:08:15.12#ibcon#about to write, iclass 14, count 0 2006.169.08:08:15.12#ibcon#wrote, iclass 14, count 0 2006.169.08:08:15.12#ibcon#about to read 3, iclass 14, count 0 2006.169.08:08:15.14#ibcon#read 3, iclass 14, count 0 2006.169.08:08:15.14#ibcon#about to read 4, iclass 14, count 0 2006.169.08:08:15.14#ibcon#read 4, iclass 14, count 0 2006.169.08:08:15.14#ibcon#about to read 5, iclass 14, count 0 2006.169.08:08:15.14#ibcon#read 5, iclass 14, count 0 2006.169.08:08:15.14#ibcon#about to read 6, iclass 14, count 0 2006.169.08:08:15.14#ibcon#read 6, iclass 14, count 0 2006.169.08:08:15.14#ibcon#end of sib2, iclass 14, count 0 2006.169.08:08:15.14#ibcon#*mode == 0, iclass 14, count 0 2006.169.08:08:15.14#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.169.08:08:15.14#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.08:08:15.14#ibcon#*before write, iclass 14, count 0 2006.169.08:08:15.14#ibcon#enter sib2, iclass 14, count 0 2006.169.08:08:15.14#ibcon#flushed, iclass 14, count 0 2006.169.08:08:15.14#ibcon#about to write, iclass 14, count 0 2006.169.08:08:15.14#ibcon#wrote, iclass 14, count 0 2006.169.08:08:15.14#ibcon#about to read 3, iclass 14, count 0 2006.169.08:08:15.18#ibcon#read 3, iclass 14, count 0 2006.169.08:08:15.18#ibcon#about to read 4, iclass 14, count 0 2006.169.08:08:15.18#ibcon#read 4, iclass 14, count 0 2006.169.08:08:15.18#ibcon#about to read 5, iclass 14, count 0 2006.169.08:08:15.18#ibcon#read 5, iclass 14, count 0 2006.169.08:08:15.18#ibcon#about to read 6, iclass 14, count 0 2006.169.08:08:15.18#ibcon#read 6, iclass 14, count 0 2006.169.08:08:15.18#ibcon#end of sib2, iclass 14, count 0 2006.169.08:08:15.18#ibcon#*after write, iclass 14, count 0 2006.169.08:08:15.18#ibcon#*before return 0, iclass 14, count 0 2006.169.08:08:15.18#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:08:15.18#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:08:15.18#ibcon#about to clear, iclass 14 cls_cnt 0 2006.169.08:08:15.18#ibcon#cleared, iclass 14 cls_cnt 0 2006.169.08:08:15.18$vc4f8/va=2,7 2006.169.08:08:15.18#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.169.08:08:15.18#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.169.08:08:15.18#ibcon#ireg 11 cls_cnt 2 2006.169.08:08:15.18#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.169.08:08:15.24#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.169.08:08:15.24#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.169.08:08:15.24#ibcon#enter wrdev, iclass 16, count 2 2006.169.08:08:15.24#ibcon#first serial, iclass 16, count 2 2006.169.08:08:15.24#ibcon#enter sib2, iclass 16, count 2 2006.169.08:08:15.24#ibcon#flushed, iclass 16, count 2 2006.169.08:08:15.24#ibcon#about to write, iclass 16, count 2 2006.169.08:08:15.24#ibcon#wrote, iclass 16, count 2 2006.169.08:08:15.24#ibcon#about to read 3, iclass 16, count 2 2006.169.08:08:15.26#ibcon#read 3, iclass 16, count 2 2006.169.08:08:15.26#ibcon#about to read 4, iclass 16, count 2 2006.169.08:08:15.26#ibcon#read 4, iclass 16, count 2 2006.169.08:08:15.26#ibcon#about to read 5, iclass 16, count 2 2006.169.08:08:15.26#ibcon#read 5, iclass 16, count 2 2006.169.08:08:15.26#ibcon#about to read 6, iclass 16, count 2 2006.169.08:08:15.26#ibcon#read 6, iclass 16, count 2 2006.169.08:08:15.26#ibcon#end of sib2, iclass 16, count 2 2006.169.08:08:15.26#ibcon#*mode == 0, iclass 16, count 2 2006.169.08:08:15.26#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.169.08:08:15.26#ibcon#[25=AT02-07\r\n] 2006.169.08:08:15.26#ibcon#*before write, iclass 16, count 2 2006.169.08:08:15.26#ibcon#enter sib2, iclass 16, count 2 2006.169.08:08:15.26#ibcon#flushed, iclass 16, count 2 2006.169.08:08:15.26#ibcon#about to write, iclass 16, count 2 2006.169.08:08:15.26#ibcon#wrote, iclass 16, count 2 2006.169.08:08:15.26#ibcon#about to read 3, iclass 16, count 2 2006.169.08:08:15.30#ibcon#read 3, iclass 16, count 2 2006.169.08:08:15.30#ibcon#about to read 4, iclass 16, count 2 2006.169.08:08:15.30#ibcon#read 4, iclass 16, count 2 2006.169.08:08:15.30#ibcon#about to read 5, iclass 16, count 2 2006.169.08:08:15.30#ibcon#read 5, iclass 16, count 2 2006.169.08:08:15.30#ibcon#about to read 6, iclass 16, count 2 2006.169.08:08:15.30#ibcon#read 6, iclass 16, count 2 2006.169.08:08:15.30#ibcon#end of sib2, iclass 16, count 2 2006.169.08:08:15.30#ibcon#*after write, iclass 16, count 2 2006.169.08:08:15.30#ibcon#*before return 0, iclass 16, count 2 2006.169.08:08:15.30#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.169.08:08:15.30#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.169.08:08:15.30#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.169.08:08:15.30#ibcon#ireg 7 cls_cnt 0 2006.169.08:08:15.30#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.169.08:08:15.42#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.169.08:08:15.42#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.169.08:08:15.42#ibcon#enter wrdev, iclass 16, count 0 2006.169.08:08:15.42#ibcon#first serial, iclass 16, count 0 2006.169.08:08:15.42#ibcon#enter sib2, iclass 16, count 0 2006.169.08:08:15.42#ibcon#flushed, iclass 16, count 0 2006.169.08:08:15.42#ibcon#about to write, iclass 16, count 0 2006.169.08:08:15.42#ibcon#wrote, iclass 16, count 0 2006.169.08:08:15.42#ibcon#about to read 3, iclass 16, count 0 2006.169.08:08:15.44#ibcon#read 3, iclass 16, count 0 2006.169.08:08:15.44#ibcon#about to read 4, iclass 16, count 0 2006.169.08:08:15.44#ibcon#read 4, iclass 16, count 0 2006.169.08:08:15.44#ibcon#about to read 5, iclass 16, count 0 2006.169.08:08:15.44#ibcon#read 5, iclass 16, count 0 2006.169.08:08:15.44#ibcon#about to read 6, iclass 16, count 0 2006.169.08:08:15.44#ibcon#read 6, iclass 16, count 0 2006.169.08:08:15.44#ibcon#end of sib2, iclass 16, count 0 2006.169.08:08:15.44#ibcon#*mode == 0, iclass 16, count 0 2006.169.08:08:15.44#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.169.08:08:15.44#ibcon#[25=USB\r\n] 2006.169.08:08:15.44#ibcon#*before write, iclass 16, count 0 2006.169.08:08:15.44#ibcon#enter sib2, iclass 16, count 0 2006.169.08:08:15.44#ibcon#flushed, iclass 16, count 0 2006.169.08:08:15.44#ibcon#about to write, iclass 16, count 0 2006.169.08:08:15.44#ibcon#wrote, iclass 16, count 0 2006.169.08:08:15.44#ibcon#about to read 3, iclass 16, count 0 2006.169.08:08:15.47#ibcon#read 3, iclass 16, count 0 2006.169.08:08:15.47#ibcon#about to read 4, iclass 16, count 0 2006.169.08:08:15.47#ibcon#read 4, iclass 16, count 0 2006.169.08:08:15.47#ibcon#about to read 5, iclass 16, count 0 2006.169.08:08:15.47#ibcon#read 5, iclass 16, count 0 2006.169.08:08:15.47#ibcon#about to read 6, iclass 16, count 0 2006.169.08:08:15.47#ibcon#read 6, iclass 16, count 0 2006.169.08:08:15.47#ibcon#end of sib2, iclass 16, count 0 2006.169.08:08:15.47#ibcon#*after write, iclass 16, count 0 2006.169.08:08:15.47#ibcon#*before return 0, iclass 16, count 0 2006.169.08:08:15.47#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.169.08:08:15.47#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.169.08:08:15.47#ibcon#about to clear, iclass 16 cls_cnt 0 2006.169.08:08:15.47#ibcon#cleared, iclass 16 cls_cnt 0 2006.169.08:08:15.47$vc4f8/valo=3,672.99 2006.169.08:08:15.47#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.169.08:08:15.47#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.169.08:08:15.47#ibcon#ireg 17 cls_cnt 0 2006.169.08:08:15.47#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:08:15.47#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:08:15.47#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:08:15.47#ibcon#enter wrdev, iclass 18, count 0 2006.169.08:08:15.47#ibcon#first serial, iclass 18, count 0 2006.169.08:08:15.47#ibcon#enter sib2, iclass 18, count 0 2006.169.08:08:15.47#ibcon#flushed, iclass 18, count 0 2006.169.08:08:15.47#ibcon#about to write, iclass 18, count 0 2006.169.08:08:15.47#ibcon#wrote, iclass 18, count 0 2006.169.08:08:15.47#ibcon#about to read 3, iclass 18, count 0 2006.169.08:08:15.49#ibcon#read 3, iclass 18, count 0 2006.169.08:08:15.49#ibcon#about to read 4, iclass 18, count 0 2006.169.08:08:15.49#ibcon#read 4, iclass 18, count 0 2006.169.08:08:15.49#ibcon#about to read 5, iclass 18, count 0 2006.169.08:08:15.49#ibcon#read 5, iclass 18, count 0 2006.169.08:08:15.49#ibcon#about to read 6, iclass 18, count 0 2006.169.08:08:15.49#ibcon#read 6, iclass 18, count 0 2006.169.08:08:15.49#ibcon#end of sib2, iclass 18, count 0 2006.169.08:08:15.49#ibcon#*mode == 0, iclass 18, count 0 2006.169.08:08:15.49#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.169.08:08:15.49#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.08:08:15.49#ibcon#*before write, iclass 18, count 0 2006.169.08:08:15.49#ibcon#enter sib2, iclass 18, count 0 2006.169.08:08:15.49#ibcon#flushed, iclass 18, count 0 2006.169.08:08:15.49#ibcon#about to write, iclass 18, count 0 2006.169.08:08:15.49#ibcon#wrote, iclass 18, count 0 2006.169.08:08:15.49#ibcon#about to read 3, iclass 18, count 0 2006.169.08:08:15.53#ibcon#read 3, iclass 18, count 0 2006.169.08:08:15.53#ibcon#about to read 4, iclass 18, count 0 2006.169.08:08:15.53#ibcon#read 4, iclass 18, count 0 2006.169.08:08:15.53#ibcon#about to read 5, iclass 18, count 0 2006.169.08:08:15.53#ibcon#read 5, iclass 18, count 0 2006.169.08:08:15.53#ibcon#about to read 6, iclass 18, count 0 2006.169.08:08:15.53#ibcon#read 6, iclass 18, count 0 2006.169.08:08:15.53#ibcon#end of sib2, iclass 18, count 0 2006.169.08:08:15.53#ibcon#*after write, iclass 18, count 0 2006.169.08:08:15.53#ibcon#*before return 0, iclass 18, count 0 2006.169.08:08:15.53#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:08:15.53#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:08:15.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.169.08:08:15.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.169.08:08:15.53$vc4f8/va=3,6 2006.169.08:08:15.53#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.169.08:08:15.53#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.169.08:08:15.53#ibcon#ireg 11 cls_cnt 2 2006.169.08:08:15.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.169.08:08:15.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.169.08:08:15.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.169.08:08:15.59#ibcon#enter wrdev, iclass 20, count 2 2006.169.08:08:15.59#ibcon#first serial, iclass 20, count 2 2006.169.08:08:15.59#ibcon#enter sib2, iclass 20, count 2 2006.169.08:08:15.59#ibcon#flushed, iclass 20, count 2 2006.169.08:08:15.59#ibcon#about to write, iclass 20, count 2 2006.169.08:08:15.59#ibcon#wrote, iclass 20, count 2 2006.169.08:08:15.59#ibcon#about to read 3, iclass 20, count 2 2006.169.08:08:15.61#ibcon#read 3, iclass 20, count 2 2006.169.08:08:15.61#ibcon#about to read 4, iclass 20, count 2 2006.169.08:08:15.61#ibcon#read 4, iclass 20, count 2 2006.169.08:08:15.61#ibcon#about to read 5, iclass 20, count 2 2006.169.08:08:15.61#ibcon#read 5, iclass 20, count 2 2006.169.08:08:15.61#ibcon#about to read 6, iclass 20, count 2 2006.169.08:08:15.61#ibcon#read 6, iclass 20, count 2 2006.169.08:08:15.61#ibcon#end of sib2, iclass 20, count 2 2006.169.08:08:15.61#ibcon#*mode == 0, iclass 20, count 2 2006.169.08:08:15.61#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.169.08:08:15.61#ibcon#[25=AT03-06\r\n] 2006.169.08:08:15.61#ibcon#*before write, iclass 20, count 2 2006.169.08:08:15.61#ibcon#enter sib2, iclass 20, count 2 2006.169.08:08:15.61#ibcon#flushed, iclass 20, count 2 2006.169.08:08:15.61#ibcon#about to write, iclass 20, count 2 2006.169.08:08:15.61#ibcon#wrote, iclass 20, count 2 2006.169.08:08:15.61#ibcon#about to read 3, iclass 20, count 2 2006.169.08:08:15.64#ibcon#read 3, iclass 20, count 2 2006.169.08:08:15.64#ibcon#about to read 4, iclass 20, count 2 2006.169.08:08:15.64#ibcon#read 4, iclass 20, count 2 2006.169.08:08:15.64#ibcon#about to read 5, iclass 20, count 2 2006.169.08:08:15.64#ibcon#read 5, iclass 20, count 2 2006.169.08:08:15.64#ibcon#about to read 6, iclass 20, count 2 2006.169.08:08:15.64#ibcon#read 6, iclass 20, count 2 2006.169.08:08:15.64#ibcon#end of sib2, iclass 20, count 2 2006.169.08:08:15.64#ibcon#*after write, iclass 20, count 2 2006.169.08:08:15.64#ibcon#*before return 0, iclass 20, count 2 2006.169.08:08:15.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.169.08:08:15.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.169.08:08:15.64#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.169.08:08:15.64#ibcon#ireg 7 cls_cnt 0 2006.169.08:08:15.64#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.169.08:08:15.72#abcon#<5=/04 3.0 5.7 18.131001003.8\r\n> 2006.169.08:08:15.74#abcon#{5=INTERFACE CLEAR} 2006.169.08:08:15.76#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.169.08:08:15.76#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.169.08:08:15.76#ibcon#enter wrdev, iclass 20, count 0 2006.169.08:08:15.76#ibcon#first serial, iclass 20, count 0 2006.169.08:08:15.76#ibcon#enter sib2, iclass 20, count 0 2006.169.08:08:15.76#ibcon#flushed, iclass 20, count 0 2006.169.08:08:15.76#ibcon#about to write, iclass 20, count 0 2006.169.08:08:15.76#ibcon#wrote, iclass 20, count 0 2006.169.08:08:15.76#ibcon#about to read 3, iclass 20, count 0 2006.169.08:08:15.78#ibcon#read 3, iclass 20, count 0 2006.169.08:08:15.78#ibcon#about to read 4, iclass 20, count 0 2006.169.08:08:15.78#ibcon#read 4, iclass 20, count 0 2006.169.08:08:15.78#ibcon#about to read 5, iclass 20, count 0 2006.169.08:08:15.78#ibcon#read 5, iclass 20, count 0 2006.169.08:08:15.78#ibcon#about to read 6, iclass 20, count 0 2006.169.08:08:15.78#ibcon#read 6, iclass 20, count 0 2006.169.08:08:15.78#ibcon#end of sib2, iclass 20, count 0 2006.169.08:08:15.78#ibcon#*mode == 0, iclass 20, count 0 2006.169.08:08:15.78#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.169.08:08:15.78#ibcon#[25=USB\r\n] 2006.169.08:08:15.78#ibcon#*before write, iclass 20, count 0 2006.169.08:08:15.78#ibcon#enter sib2, iclass 20, count 0 2006.169.08:08:15.78#ibcon#flushed, iclass 20, count 0 2006.169.08:08:15.78#ibcon#about to write, iclass 20, count 0 2006.169.08:08:15.78#ibcon#wrote, iclass 20, count 0 2006.169.08:08:15.78#ibcon#about to read 3, iclass 20, count 0 2006.169.08:08:15.80#abcon#[5=S1D000X0/0*\r\n] 2006.169.08:08:15.81#ibcon#read 3, iclass 20, count 0 2006.169.08:08:15.81#ibcon#about to read 4, iclass 20, count 0 2006.169.08:08:15.81#ibcon#read 4, iclass 20, count 0 2006.169.08:08:15.81#ibcon#about to read 5, iclass 20, count 0 2006.169.08:08:15.81#ibcon#read 5, iclass 20, count 0 2006.169.08:08:15.81#ibcon#about to read 6, iclass 20, count 0 2006.169.08:08:15.81#ibcon#read 6, iclass 20, count 0 2006.169.08:08:15.81#ibcon#end of sib2, iclass 20, count 0 2006.169.08:08:15.81#ibcon#*after write, iclass 20, count 0 2006.169.08:08:15.81#ibcon#*before return 0, iclass 20, count 0 2006.169.08:08:15.81#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.169.08:08:15.81#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.169.08:08:15.81#ibcon#about to clear, iclass 20 cls_cnt 0 2006.169.08:08:15.81#ibcon#cleared, iclass 20 cls_cnt 0 2006.169.08:08:15.81$vc4f8/valo=4,832.99 2006.169.08:08:15.81#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.169.08:08:15.81#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.169.08:08:15.81#ibcon#ireg 17 cls_cnt 0 2006.169.08:08:15.81#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:08:15.81#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:08:15.81#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:08:15.81#ibcon#enter wrdev, iclass 26, count 0 2006.169.08:08:15.81#ibcon#first serial, iclass 26, count 0 2006.169.08:08:15.81#ibcon#enter sib2, iclass 26, count 0 2006.169.08:08:15.81#ibcon#flushed, iclass 26, count 0 2006.169.08:08:15.81#ibcon#about to write, iclass 26, count 0 2006.169.08:08:15.81#ibcon#wrote, iclass 26, count 0 2006.169.08:08:15.81#ibcon#about to read 3, iclass 26, count 0 2006.169.08:08:15.83#ibcon#read 3, iclass 26, count 0 2006.169.08:08:15.83#ibcon#about to read 4, iclass 26, count 0 2006.169.08:08:15.83#ibcon#read 4, iclass 26, count 0 2006.169.08:08:15.83#ibcon#about to read 5, iclass 26, count 0 2006.169.08:08:15.83#ibcon#read 5, iclass 26, count 0 2006.169.08:08:15.83#ibcon#about to read 6, iclass 26, count 0 2006.169.08:08:15.83#ibcon#read 6, iclass 26, count 0 2006.169.08:08:15.83#ibcon#end of sib2, iclass 26, count 0 2006.169.08:08:15.83#ibcon#*mode == 0, iclass 26, count 0 2006.169.08:08:15.83#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.169.08:08:15.83#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.08:08:15.83#ibcon#*before write, iclass 26, count 0 2006.169.08:08:15.83#ibcon#enter sib2, iclass 26, count 0 2006.169.08:08:15.83#ibcon#flushed, iclass 26, count 0 2006.169.08:08:15.83#ibcon#about to write, iclass 26, count 0 2006.169.08:08:15.83#ibcon#wrote, iclass 26, count 0 2006.169.08:08:15.83#ibcon#about to read 3, iclass 26, count 0 2006.169.08:08:15.87#ibcon#read 3, iclass 26, count 0 2006.169.08:08:15.87#ibcon#about to read 4, iclass 26, count 0 2006.169.08:08:15.87#ibcon#read 4, iclass 26, count 0 2006.169.08:08:15.87#ibcon#about to read 5, iclass 26, count 0 2006.169.08:08:15.87#ibcon#read 5, iclass 26, count 0 2006.169.08:08:15.87#ibcon#about to read 6, iclass 26, count 0 2006.169.08:08:15.87#ibcon#read 6, iclass 26, count 0 2006.169.08:08:15.87#ibcon#end of sib2, iclass 26, count 0 2006.169.08:08:15.87#ibcon#*after write, iclass 26, count 0 2006.169.08:08:15.87#ibcon#*before return 0, iclass 26, count 0 2006.169.08:08:15.87#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:08:15.87#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:08:15.87#ibcon#about to clear, iclass 26 cls_cnt 0 2006.169.08:08:15.87#ibcon#cleared, iclass 26 cls_cnt 0 2006.169.08:08:15.87$vc4f8/va=4,7 2006.169.08:08:15.87#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.169.08:08:15.87#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.169.08:08:15.87#ibcon#ireg 11 cls_cnt 2 2006.169.08:08:15.87#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.169.08:08:15.93#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.169.08:08:15.93#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.169.08:08:15.93#ibcon#enter wrdev, iclass 28, count 2 2006.169.08:08:15.93#ibcon#first serial, iclass 28, count 2 2006.169.08:08:15.93#ibcon#enter sib2, iclass 28, count 2 2006.169.08:08:15.93#ibcon#flushed, iclass 28, count 2 2006.169.08:08:15.93#ibcon#about to write, iclass 28, count 2 2006.169.08:08:15.93#ibcon#wrote, iclass 28, count 2 2006.169.08:08:15.93#ibcon#about to read 3, iclass 28, count 2 2006.169.08:08:15.95#ibcon#read 3, iclass 28, count 2 2006.169.08:08:15.95#ibcon#about to read 4, iclass 28, count 2 2006.169.08:08:15.95#ibcon#read 4, iclass 28, count 2 2006.169.08:08:15.95#ibcon#about to read 5, iclass 28, count 2 2006.169.08:08:15.95#ibcon#read 5, iclass 28, count 2 2006.169.08:08:15.95#ibcon#about to read 6, iclass 28, count 2 2006.169.08:08:15.95#ibcon#read 6, iclass 28, count 2 2006.169.08:08:15.95#ibcon#end of sib2, iclass 28, count 2 2006.169.08:08:15.95#ibcon#*mode == 0, iclass 28, count 2 2006.169.08:08:15.95#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.169.08:08:15.95#ibcon#[25=AT04-07\r\n] 2006.169.08:08:15.95#ibcon#*before write, iclass 28, count 2 2006.169.08:08:15.95#ibcon#enter sib2, iclass 28, count 2 2006.169.08:08:15.95#ibcon#flushed, iclass 28, count 2 2006.169.08:08:15.95#ibcon#about to write, iclass 28, count 2 2006.169.08:08:15.95#ibcon#wrote, iclass 28, count 2 2006.169.08:08:15.95#ibcon#about to read 3, iclass 28, count 2 2006.169.08:08:15.98#ibcon#read 3, iclass 28, count 2 2006.169.08:08:15.98#ibcon#about to read 4, iclass 28, count 2 2006.169.08:08:15.98#ibcon#read 4, iclass 28, count 2 2006.169.08:08:15.98#ibcon#about to read 5, iclass 28, count 2 2006.169.08:08:15.98#ibcon#read 5, iclass 28, count 2 2006.169.08:08:15.98#ibcon#about to read 6, iclass 28, count 2 2006.169.08:08:15.98#ibcon#read 6, iclass 28, count 2 2006.169.08:08:15.98#ibcon#end of sib2, iclass 28, count 2 2006.169.08:08:15.98#ibcon#*after write, iclass 28, count 2 2006.169.08:08:15.98#ibcon#*before return 0, iclass 28, count 2 2006.169.08:08:15.98#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.169.08:08:15.98#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.169.08:08:15.98#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.169.08:08:15.98#ibcon#ireg 7 cls_cnt 0 2006.169.08:08:15.98#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.169.08:08:16.10#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.169.08:08:16.10#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.169.08:08:16.10#ibcon#enter wrdev, iclass 28, count 0 2006.169.08:08:16.10#ibcon#first serial, iclass 28, count 0 2006.169.08:08:16.10#ibcon#enter sib2, iclass 28, count 0 2006.169.08:08:16.10#ibcon#flushed, iclass 28, count 0 2006.169.08:08:16.10#ibcon#about to write, iclass 28, count 0 2006.169.08:08:16.10#ibcon#wrote, iclass 28, count 0 2006.169.08:08:16.10#ibcon#about to read 3, iclass 28, count 0 2006.169.08:08:16.12#ibcon#read 3, iclass 28, count 0 2006.169.08:08:16.12#ibcon#about to read 4, iclass 28, count 0 2006.169.08:08:16.12#ibcon#read 4, iclass 28, count 0 2006.169.08:08:16.12#ibcon#about to read 5, iclass 28, count 0 2006.169.08:08:16.12#ibcon#read 5, iclass 28, count 0 2006.169.08:08:16.12#ibcon#about to read 6, iclass 28, count 0 2006.169.08:08:16.12#ibcon#read 6, iclass 28, count 0 2006.169.08:08:16.12#ibcon#end of sib2, iclass 28, count 0 2006.169.08:08:16.12#ibcon#*mode == 0, iclass 28, count 0 2006.169.08:08:16.12#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.169.08:08:16.12#ibcon#[25=USB\r\n] 2006.169.08:08:16.12#ibcon#*before write, iclass 28, count 0 2006.169.08:08:16.12#ibcon#enter sib2, iclass 28, count 0 2006.169.08:08:16.12#ibcon#flushed, iclass 28, count 0 2006.169.08:08:16.12#ibcon#about to write, iclass 28, count 0 2006.169.08:08:16.12#ibcon#wrote, iclass 28, count 0 2006.169.08:08:16.12#ibcon#about to read 3, iclass 28, count 0 2006.169.08:08:16.15#ibcon#read 3, iclass 28, count 0 2006.169.08:08:16.15#ibcon#about to read 4, iclass 28, count 0 2006.169.08:08:16.15#ibcon#read 4, iclass 28, count 0 2006.169.08:08:16.15#ibcon#about to read 5, iclass 28, count 0 2006.169.08:08:16.15#ibcon#read 5, iclass 28, count 0 2006.169.08:08:16.15#ibcon#about to read 6, iclass 28, count 0 2006.169.08:08:16.15#ibcon#read 6, iclass 28, count 0 2006.169.08:08:16.15#ibcon#end of sib2, iclass 28, count 0 2006.169.08:08:16.15#ibcon#*after write, iclass 28, count 0 2006.169.08:08:16.15#ibcon#*before return 0, iclass 28, count 0 2006.169.08:08:16.15#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.169.08:08:16.15#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.169.08:08:16.15#ibcon#about to clear, iclass 28 cls_cnt 0 2006.169.08:08:16.15#ibcon#cleared, iclass 28 cls_cnt 0 2006.169.08:08:16.15$vc4f8/valo=5,652.99 2006.169.08:08:16.15#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.169.08:08:16.15#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.169.08:08:16.15#ibcon#ireg 17 cls_cnt 0 2006.169.08:08:16.15#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.169.08:08:16.15#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.169.08:08:16.15#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.169.08:08:16.15#ibcon#enter wrdev, iclass 30, count 0 2006.169.08:08:16.15#ibcon#first serial, iclass 30, count 0 2006.169.08:08:16.15#ibcon#enter sib2, iclass 30, count 0 2006.169.08:08:16.15#ibcon#flushed, iclass 30, count 0 2006.169.08:08:16.15#ibcon#about to write, iclass 30, count 0 2006.169.08:08:16.15#ibcon#wrote, iclass 30, count 0 2006.169.08:08:16.15#ibcon#about to read 3, iclass 30, count 0 2006.169.08:08:16.17#ibcon#read 3, iclass 30, count 0 2006.169.08:08:16.17#ibcon#about to read 4, iclass 30, count 0 2006.169.08:08:16.17#ibcon#read 4, iclass 30, count 0 2006.169.08:08:16.17#ibcon#about to read 5, iclass 30, count 0 2006.169.08:08:16.17#ibcon#read 5, iclass 30, count 0 2006.169.08:08:16.17#ibcon#about to read 6, iclass 30, count 0 2006.169.08:08:16.17#ibcon#read 6, iclass 30, count 0 2006.169.08:08:16.17#ibcon#end of sib2, iclass 30, count 0 2006.169.08:08:16.17#ibcon#*mode == 0, iclass 30, count 0 2006.169.08:08:16.17#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.169.08:08:16.17#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.08:08:16.17#ibcon#*before write, iclass 30, count 0 2006.169.08:08:16.17#ibcon#enter sib2, iclass 30, count 0 2006.169.08:08:16.17#ibcon#flushed, iclass 30, count 0 2006.169.08:08:16.17#ibcon#about to write, iclass 30, count 0 2006.169.08:08:16.17#ibcon#wrote, iclass 30, count 0 2006.169.08:08:16.17#ibcon#about to read 3, iclass 30, count 0 2006.169.08:08:16.21#ibcon#read 3, iclass 30, count 0 2006.169.08:08:16.21#ibcon#about to read 4, iclass 30, count 0 2006.169.08:08:16.21#ibcon#read 4, iclass 30, count 0 2006.169.08:08:16.21#ibcon#about to read 5, iclass 30, count 0 2006.169.08:08:16.21#ibcon#read 5, iclass 30, count 0 2006.169.08:08:16.21#ibcon#about to read 6, iclass 30, count 0 2006.169.08:08:16.21#ibcon#read 6, iclass 30, count 0 2006.169.08:08:16.21#ibcon#end of sib2, iclass 30, count 0 2006.169.08:08:16.21#ibcon#*after write, iclass 30, count 0 2006.169.08:08:16.21#ibcon#*before return 0, iclass 30, count 0 2006.169.08:08:16.21#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.169.08:08:16.21#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.169.08:08:16.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.169.08:08:16.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.169.08:08:16.21$vc4f8/va=5,7 2006.169.08:08:16.21#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.169.08:08:16.21#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.169.08:08:16.21#ibcon#ireg 11 cls_cnt 2 2006.169.08:08:16.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.169.08:08:16.27#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.169.08:08:16.27#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.169.08:08:16.27#ibcon#enter wrdev, iclass 32, count 2 2006.169.08:08:16.27#ibcon#first serial, iclass 32, count 2 2006.169.08:08:16.27#ibcon#enter sib2, iclass 32, count 2 2006.169.08:08:16.27#ibcon#flushed, iclass 32, count 2 2006.169.08:08:16.27#ibcon#about to write, iclass 32, count 2 2006.169.08:08:16.27#ibcon#wrote, iclass 32, count 2 2006.169.08:08:16.27#ibcon#about to read 3, iclass 32, count 2 2006.169.08:08:16.29#ibcon#read 3, iclass 32, count 2 2006.169.08:08:16.29#ibcon#about to read 4, iclass 32, count 2 2006.169.08:08:16.29#ibcon#read 4, iclass 32, count 2 2006.169.08:08:16.29#ibcon#about to read 5, iclass 32, count 2 2006.169.08:08:16.29#ibcon#read 5, iclass 32, count 2 2006.169.08:08:16.29#ibcon#about to read 6, iclass 32, count 2 2006.169.08:08:16.29#ibcon#read 6, iclass 32, count 2 2006.169.08:08:16.29#ibcon#end of sib2, iclass 32, count 2 2006.169.08:08:16.29#ibcon#*mode == 0, iclass 32, count 2 2006.169.08:08:16.29#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.169.08:08:16.29#ibcon#[25=AT05-07\r\n] 2006.169.08:08:16.29#ibcon#*before write, iclass 32, count 2 2006.169.08:08:16.29#ibcon#enter sib2, iclass 32, count 2 2006.169.08:08:16.29#ibcon#flushed, iclass 32, count 2 2006.169.08:08:16.29#ibcon#about to write, iclass 32, count 2 2006.169.08:08:16.29#ibcon#wrote, iclass 32, count 2 2006.169.08:08:16.29#ibcon#about to read 3, iclass 32, count 2 2006.169.08:08:16.32#ibcon#read 3, iclass 32, count 2 2006.169.08:08:16.32#ibcon#about to read 4, iclass 32, count 2 2006.169.08:08:16.32#ibcon#read 4, iclass 32, count 2 2006.169.08:08:16.32#ibcon#about to read 5, iclass 32, count 2 2006.169.08:08:16.32#ibcon#read 5, iclass 32, count 2 2006.169.08:08:16.32#ibcon#about to read 6, iclass 32, count 2 2006.169.08:08:16.32#ibcon#read 6, iclass 32, count 2 2006.169.08:08:16.32#ibcon#end of sib2, iclass 32, count 2 2006.169.08:08:16.32#ibcon#*after write, iclass 32, count 2 2006.169.08:08:16.32#ibcon#*before return 0, iclass 32, count 2 2006.169.08:08:16.32#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.169.08:08:16.32#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.169.08:08:16.32#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.169.08:08:16.32#ibcon#ireg 7 cls_cnt 0 2006.169.08:08:16.32#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.169.08:08:16.44#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.169.08:08:16.44#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.169.08:08:16.44#ibcon#enter wrdev, iclass 32, count 0 2006.169.08:08:16.44#ibcon#first serial, iclass 32, count 0 2006.169.08:08:16.44#ibcon#enter sib2, iclass 32, count 0 2006.169.08:08:16.44#ibcon#flushed, iclass 32, count 0 2006.169.08:08:16.44#ibcon#about to write, iclass 32, count 0 2006.169.08:08:16.44#ibcon#wrote, iclass 32, count 0 2006.169.08:08:16.44#ibcon#about to read 3, iclass 32, count 0 2006.169.08:08:16.46#ibcon#read 3, iclass 32, count 0 2006.169.08:08:16.46#ibcon#about to read 4, iclass 32, count 0 2006.169.08:08:16.46#ibcon#read 4, iclass 32, count 0 2006.169.08:08:16.46#ibcon#about to read 5, iclass 32, count 0 2006.169.08:08:16.46#ibcon#read 5, iclass 32, count 0 2006.169.08:08:16.46#ibcon#about to read 6, iclass 32, count 0 2006.169.08:08:16.46#ibcon#read 6, iclass 32, count 0 2006.169.08:08:16.46#ibcon#end of sib2, iclass 32, count 0 2006.169.08:08:16.46#ibcon#*mode == 0, iclass 32, count 0 2006.169.08:08:16.46#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.169.08:08:16.46#ibcon#[25=USB\r\n] 2006.169.08:08:16.46#ibcon#*before write, iclass 32, count 0 2006.169.08:08:16.46#ibcon#enter sib2, iclass 32, count 0 2006.169.08:08:16.46#ibcon#flushed, iclass 32, count 0 2006.169.08:08:16.46#ibcon#about to write, iclass 32, count 0 2006.169.08:08:16.46#ibcon#wrote, iclass 32, count 0 2006.169.08:08:16.46#ibcon#about to read 3, iclass 32, count 0 2006.169.08:08:16.49#ibcon#read 3, iclass 32, count 0 2006.169.08:08:16.49#ibcon#about to read 4, iclass 32, count 0 2006.169.08:08:16.49#ibcon#read 4, iclass 32, count 0 2006.169.08:08:16.49#ibcon#about to read 5, iclass 32, count 0 2006.169.08:08:16.49#ibcon#read 5, iclass 32, count 0 2006.169.08:08:16.49#ibcon#about to read 6, iclass 32, count 0 2006.169.08:08:16.49#ibcon#read 6, iclass 32, count 0 2006.169.08:08:16.49#ibcon#end of sib2, iclass 32, count 0 2006.169.08:08:16.49#ibcon#*after write, iclass 32, count 0 2006.169.08:08:16.49#ibcon#*before return 0, iclass 32, count 0 2006.169.08:08:16.49#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.169.08:08:16.49#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.169.08:08:16.49#ibcon#about to clear, iclass 32 cls_cnt 0 2006.169.08:08:16.49#ibcon#cleared, iclass 32 cls_cnt 0 2006.169.08:08:16.49$vc4f8/valo=6,772.99 2006.169.08:08:16.49#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.169.08:08:16.49#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.169.08:08:16.49#ibcon#ireg 17 cls_cnt 0 2006.169.08:08:16.49#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:08:16.49#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:08:16.49#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:08:16.49#ibcon#enter wrdev, iclass 34, count 0 2006.169.08:08:16.49#ibcon#first serial, iclass 34, count 0 2006.169.08:08:16.49#ibcon#enter sib2, iclass 34, count 0 2006.169.08:08:16.49#ibcon#flushed, iclass 34, count 0 2006.169.08:08:16.49#ibcon#about to write, iclass 34, count 0 2006.169.08:08:16.49#ibcon#wrote, iclass 34, count 0 2006.169.08:08:16.49#ibcon#about to read 3, iclass 34, count 0 2006.169.08:08:16.51#ibcon#read 3, iclass 34, count 0 2006.169.08:08:16.51#ibcon#about to read 4, iclass 34, count 0 2006.169.08:08:16.51#ibcon#read 4, iclass 34, count 0 2006.169.08:08:16.51#ibcon#about to read 5, iclass 34, count 0 2006.169.08:08:16.51#ibcon#read 5, iclass 34, count 0 2006.169.08:08:16.51#ibcon#about to read 6, iclass 34, count 0 2006.169.08:08:16.51#ibcon#read 6, iclass 34, count 0 2006.169.08:08:16.51#ibcon#end of sib2, iclass 34, count 0 2006.169.08:08:16.51#ibcon#*mode == 0, iclass 34, count 0 2006.169.08:08:16.51#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.169.08:08:16.51#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.08:08:16.51#ibcon#*before write, iclass 34, count 0 2006.169.08:08:16.51#ibcon#enter sib2, iclass 34, count 0 2006.169.08:08:16.51#ibcon#flushed, iclass 34, count 0 2006.169.08:08:16.51#ibcon#about to write, iclass 34, count 0 2006.169.08:08:16.51#ibcon#wrote, iclass 34, count 0 2006.169.08:08:16.51#ibcon#about to read 3, iclass 34, count 0 2006.169.08:08:16.55#ibcon#read 3, iclass 34, count 0 2006.169.08:08:16.55#ibcon#about to read 4, iclass 34, count 0 2006.169.08:08:16.55#ibcon#read 4, iclass 34, count 0 2006.169.08:08:16.55#ibcon#about to read 5, iclass 34, count 0 2006.169.08:08:16.55#ibcon#read 5, iclass 34, count 0 2006.169.08:08:16.55#ibcon#about to read 6, iclass 34, count 0 2006.169.08:08:16.55#ibcon#read 6, iclass 34, count 0 2006.169.08:08:16.55#ibcon#end of sib2, iclass 34, count 0 2006.169.08:08:16.55#ibcon#*after write, iclass 34, count 0 2006.169.08:08:16.55#ibcon#*before return 0, iclass 34, count 0 2006.169.08:08:16.55#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:08:16.55#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:08:16.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.169.08:08:16.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.169.08:08:16.55$vc4f8/va=6,6 2006.169.08:08:16.55#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.169.08:08:16.55#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.169.08:08:16.55#ibcon#ireg 11 cls_cnt 2 2006.169.08:08:16.55#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.169.08:08:16.61#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.169.08:08:16.61#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.169.08:08:16.61#ibcon#enter wrdev, iclass 36, count 2 2006.169.08:08:16.61#ibcon#first serial, iclass 36, count 2 2006.169.08:08:16.61#ibcon#enter sib2, iclass 36, count 2 2006.169.08:08:16.61#ibcon#flushed, iclass 36, count 2 2006.169.08:08:16.61#ibcon#about to write, iclass 36, count 2 2006.169.08:08:16.61#ibcon#wrote, iclass 36, count 2 2006.169.08:08:16.61#ibcon#about to read 3, iclass 36, count 2 2006.169.08:08:16.63#ibcon#read 3, iclass 36, count 2 2006.169.08:08:16.63#ibcon#about to read 4, iclass 36, count 2 2006.169.08:08:16.63#ibcon#read 4, iclass 36, count 2 2006.169.08:08:16.63#ibcon#about to read 5, iclass 36, count 2 2006.169.08:08:16.63#ibcon#read 5, iclass 36, count 2 2006.169.08:08:16.63#ibcon#about to read 6, iclass 36, count 2 2006.169.08:08:16.63#ibcon#read 6, iclass 36, count 2 2006.169.08:08:16.63#ibcon#end of sib2, iclass 36, count 2 2006.169.08:08:16.63#ibcon#*mode == 0, iclass 36, count 2 2006.169.08:08:16.63#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.169.08:08:16.63#ibcon#[25=AT06-06\r\n] 2006.169.08:08:16.63#ibcon#*before write, iclass 36, count 2 2006.169.08:08:16.63#ibcon#enter sib2, iclass 36, count 2 2006.169.08:08:16.63#ibcon#flushed, iclass 36, count 2 2006.169.08:08:16.63#ibcon#about to write, iclass 36, count 2 2006.169.08:08:16.63#ibcon#wrote, iclass 36, count 2 2006.169.08:08:16.63#ibcon#about to read 3, iclass 36, count 2 2006.169.08:08:16.66#ibcon#read 3, iclass 36, count 2 2006.169.08:08:16.66#ibcon#about to read 4, iclass 36, count 2 2006.169.08:08:16.66#ibcon#read 4, iclass 36, count 2 2006.169.08:08:16.66#ibcon#about to read 5, iclass 36, count 2 2006.169.08:08:16.66#ibcon#read 5, iclass 36, count 2 2006.169.08:08:16.66#ibcon#about to read 6, iclass 36, count 2 2006.169.08:08:16.66#ibcon#read 6, iclass 36, count 2 2006.169.08:08:16.66#ibcon#end of sib2, iclass 36, count 2 2006.169.08:08:16.66#ibcon#*after write, iclass 36, count 2 2006.169.08:08:16.66#ibcon#*before return 0, iclass 36, count 2 2006.169.08:08:16.66#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.169.08:08:16.66#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.169.08:08:16.66#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.169.08:08:16.66#ibcon#ireg 7 cls_cnt 0 2006.169.08:08:16.66#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.169.08:08:16.78#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.169.08:08:16.78#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.169.08:08:16.78#ibcon#enter wrdev, iclass 36, count 0 2006.169.08:08:16.78#ibcon#first serial, iclass 36, count 0 2006.169.08:08:16.78#ibcon#enter sib2, iclass 36, count 0 2006.169.08:08:16.78#ibcon#flushed, iclass 36, count 0 2006.169.08:08:16.78#ibcon#about to write, iclass 36, count 0 2006.169.08:08:16.78#ibcon#wrote, iclass 36, count 0 2006.169.08:08:16.78#ibcon#about to read 3, iclass 36, count 0 2006.169.08:08:16.80#ibcon#read 3, iclass 36, count 0 2006.169.08:08:16.80#ibcon#about to read 4, iclass 36, count 0 2006.169.08:08:16.80#ibcon#read 4, iclass 36, count 0 2006.169.08:08:16.80#ibcon#about to read 5, iclass 36, count 0 2006.169.08:08:16.80#ibcon#read 5, iclass 36, count 0 2006.169.08:08:16.80#ibcon#about to read 6, iclass 36, count 0 2006.169.08:08:16.80#ibcon#read 6, iclass 36, count 0 2006.169.08:08:16.80#ibcon#end of sib2, iclass 36, count 0 2006.169.08:08:16.80#ibcon#*mode == 0, iclass 36, count 0 2006.169.08:08:16.80#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.169.08:08:16.80#ibcon#[25=USB\r\n] 2006.169.08:08:16.80#ibcon#*before write, iclass 36, count 0 2006.169.08:08:16.80#ibcon#enter sib2, iclass 36, count 0 2006.169.08:08:16.80#ibcon#flushed, iclass 36, count 0 2006.169.08:08:16.80#ibcon#about to write, iclass 36, count 0 2006.169.08:08:16.80#ibcon#wrote, iclass 36, count 0 2006.169.08:08:16.80#ibcon#about to read 3, iclass 36, count 0 2006.169.08:08:16.83#ibcon#read 3, iclass 36, count 0 2006.169.08:08:16.83#ibcon#about to read 4, iclass 36, count 0 2006.169.08:08:16.83#ibcon#read 4, iclass 36, count 0 2006.169.08:08:16.83#ibcon#about to read 5, iclass 36, count 0 2006.169.08:08:16.83#ibcon#read 5, iclass 36, count 0 2006.169.08:08:16.83#ibcon#about to read 6, iclass 36, count 0 2006.169.08:08:16.83#ibcon#read 6, iclass 36, count 0 2006.169.08:08:16.83#ibcon#end of sib2, iclass 36, count 0 2006.169.08:08:16.83#ibcon#*after write, iclass 36, count 0 2006.169.08:08:16.83#ibcon#*before return 0, iclass 36, count 0 2006.169.08:08:16.83#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.169.08:08:16.83#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.169.08:08:16.83#ibcon#about to clear, iclass 36 cls_cnt 0 2006.169.08:08:16.83#ibcon#cleared, iclass 36 cls_cnt 0 2006.169.08:08:16.83$vc4f8/valo=7,832.99 2006.169.08:08:16.83#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.169.08:08:16.83#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.169.08:08:16.83#ibcon#ireg 17 cls_cnt 0 2006.169.08:08:16.83#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.169.08:08:16.83#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.169.08:08:16.83#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.169.08:08:16.83#ibcon#enter wrdev, iclass 38, count 0 2006.169.08:08:16.83#ibcon#first serial, iclass 38, count 0 2006.169.08:08:16.83#ibcon#enter sib2, iclass 38, count 0 2006.169.08:08:16.83#ibcon#flushed, iclass 38, count 0 2006.169.08:08:16.83#ibcon#about to write, iclass 38, count 0 2006.169.08:08:16.83#ibcon#wrote, iclass 38, count 0 2006.169.08:08:16.83#ibcon#about to read 3, iclass 38, count 0 2006.169.08:08:16.85#ibcon#read 3, iclass 38, count 0 2006.169.08:08:16.85#ibcon#about to read 4, iclass 38, count 0 2006.169.08:08:16.85#ibcon#read 4, iclass 38, count 0 2006.169.08:08:16.85#ibcon#about to read 5, iclass 38, count 0 2006.169.08:08:16.85#ibcon#read 5, iclass 38, count 0 2006.169.08:08:16.85#ibcon#about to read 6, iclass 38, count 0 2006.169.08:08:16.85#ibcon#read 6, iclass 38, count 0 2006.169.08:08:16.85#ibcon#end of sib2, iclass 38, count 0 2006.169.08:08:16.85#ibcon#*mode == 0, iclass 38, count 0 2006.169.08:08:16.85#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.169.08:08:16.85#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.08:08:16.85#ibcon#*before write, iclass 38, count 0 2006.169.08:08:16.85#ibcon#enter sib2, iclass 38, count 0 2006.169.08:08:16.85#ibcon#flushed, iclass 38, count 0 2006.169.08:08:16.85#ibcon#about to write, iclass 38, count 0 2006.169.08:08:16.85#ibcon#wrote, iclass 38, count 0 2006.169.08:08:16.85#ibcon#about to read 3, iclass 38, count 0 2006.169.08:08:16.89#ibcon#read 3, iclass 38, count 0 2006.169.08:08:16.89#ibcon#about to read 4, iclass 38, count 0 2006.169.08:08:16.89#ibcon#read 4, iclass 38, count 0 2006.169.08:08:16.89#ibcon#about to read 5, iclass 38, count 0 2006.169.08:08:16.89#ibcon#read 5, iclass 38, count 0 2006.169.08:08:16.89#ibcon#about to read 6, iclass 38, count 0 2006.169.08:08:16.89#ibcon#read 6, iclass 38, count 0 2006.169.08:08:16.89#ibcon#end of sib2, iclass 38, count 0 2006.169.08:08:16.89#ibcon#*after write, iclass 38, count 0 2006.169.08:08:16.89#ibcon#*before return 0, iclass 38, count 0 2006.169.08:08:16.89#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.169.08:08:16.89#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.169.08:08:16.89#ibcon#about to clear, iclass 38 cls_cnt 0 2006.169.08:08:16.89#ibcon#cleared, iclass 38 cls_cnt 0 2006.169.08:08:16.89$vc4f8/va=7,6 2006.169.08:08:16.89#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.169.08:08:16.89#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.169.08:08:16.89#ibcon#ireg 11 cls_cnt 2 2006.169.08:08:16.89#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.169.08:08:16.95#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.169.08:08:16.95#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.169.08:08:16.95#ibcon#enter wrdev, iclass 40, count 2 2006.169.08:08:16.95#ibcon#first serial, iclass 40, count 2 2006.169.08:08:16.95#ibcon#enter sib2, iclass 40, count 2 2006.169.08:08:16.95#ibcon#flushed, iclass 40, count 2 2006.169.08:08:16.95#ibcon#about to write, iclass 40, count 2 2006.169.08:08:16.95#ibcon#wrote, iclass 40, count 2 2006.169.08:08:16.95#ibcon#about to read 3, iclass 40, count 2 2006.169.08:08:16.97#ibcon#read 3, iclass 40, count 2 2006.169.08:08:16.97#ibcon#about to read 4, iclass 40, count 2 2006.169.08:08:16.97#ibcon#read 4, iclass 40, count 2 2006.169.08:08:16.97#ibcon#about to read 5, iclass 40, count 2 2006.169.08:08:16.97#ibcon#read 5, iclass 40, count 2 2006.169.08:08:16.97#ibcon#about to read 6, iclass 40, count 2 2006.169.08:08:16.97#ibcon#read 6, iclass 40, count 2 2006.169.08:08:16.97#ibcon#end of sib2, iclass 40, count 2 2006.169.08:08:16.97#ibcon#*mode == 0, iclass 40, count 2 2006.169.08:08:16.97#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.169.08:08:16.97#ibcon#[25=AT07-06\r\n] 2006.169.08:08:16.97#ibcon#*before write, iclass 40, count 2 2006.169.08:08:16.97#ibcon#enter sib2, iclass 40, count 2 2006.169.08:08:16.97#ibcon#flushed, iclass 40, count 2 2006.169.08:08:16.97#ibcon#about to write, iclass 40, count 2 2006.169.08:08:16.97#ibcon#wrote, iclass 40, count 2 2006.169.08:08:16.97#ibcon#about to read 3, iclass 40, count 2 2006.169.08:08:17.00#ibcon#read 3, iclass 40, count 2 2006.169.08:08:17.00#ibcon#about to read 4, iclass 40, count 2 2006.169.08:08:17.00#ibcon#read 4, iclass 40, count 2 2006.169.08:08:17.00#ibcon#about to read 5, iclass 40, count 2 2006.169.08:08:17.00#ibcon#read 5, iclass 40, count 2 2006.169.08:08:17.00#ibcon#about to read 6, iclass 40, count 2 2006.169.08:08:17.00#ibcon#read 6, iclass 40, count 2 2006.169.08:08:17.00#ibcon#end of sib2, iclass 40, count 2 2006.169.08:08:17.00#ibcon#*after write, iclass 40, count 2 2006.169.08:08:17.00#ibcon#*before return 0, iclass 40, count 2 2006.169.08:08:17.00#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.169.08:08:17.00#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.169.08:08:17.00#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.169.08:08:17.00#ibcon#ireg 7 cls_cnt 0 2006.169.08:08:17.00#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.169.08:08:17.12#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.169.08:08:17.12#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.169.08:08:17.12#ibcon#enter wrdev, iclass 40, count 0 2006.169.08:08:17.12#ibcon#first serial, iclass 40, count 0 2006.169.08:08:17.12#ibcon#enter sib2, iclass 40, count 0 2006.169.08:08:17.12#ibcon#flushed, iclass 40, count 0 2006.169.08:08:17.12#ibcon#about to write, iclass 40, count 0 2006.169.08:08:17.12#ibcon#wrote, iclass 40, count 0 2006.169.08:08:17.12#ibcon#about to read 3, iclass 40, count 0 2006.169.08:08:17.14#ibcon#read 3, iclass 40, count 0 2006.169.08:08:17.14#ibcon#about to read 4, iclass 40, count 0 2006.169.08:08:17.14#ibcon#read 4, iclass 40, count 0 2006.169.08:08:17.14#ibcon#about to read 5, iclass 40, count 0 2006.169.08:08:17.14#ibcon#read 5, iclass 40, count 0 2006.169.08:08:17.14#ibcon#about to read 6, iclass 40, count 0 2006.169.08:08:17.14#ibcon#read 6, iclass 40, count 0 2006.169.08:08:17.14#ibcon#end of sib2, iclass 40, count 0 2006.169.08:08:17.14#ibcon#*mode == 0, iclass 40, count 0 2006.169.08:08:17.14#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.169.08:08:17.14#ibcon#[25=USB\r\n] 2006.169.08:08:17.14#ibcon#*before write, iclass 40, count 0 2006.169.08:08:17.14#ibcon#enter sib2, iclass 40, count 0 2006.169.08:08:17.14#ibcon#flushed, iclass 40, count 0 2006.169.08:08:17.14#ibcon#about to write, iclass 40, count 0 2006.169.08:08:17.14#ibcon#wrote, iclass 40, count 0 2006.169.08:08:17.14#ibcon#about to read 3, iclass 40, count 0 2006.169.08:08:17.17#ibcon#read 3, iclass 40, count 0 2006.169.08:08:17.17#ibcon#about to read 4, iclass 40, count 0 2006.169.08:08:17.17#ibcon#read 4, iclass 40, count 0 2006.169.08:08:17.17#ibcon#about to read 5, iclass 40, count 0 2006.169.08:08:17.17#ibcon#read 5, iclass 40, count 0 2006.169.08:08:17.17#ibcon#about to read 6, iclass 40, count 0 2006.169.08:08:17.17#ibcon#read 6, iclass 40, count 0 2006.169.08:08:17.17#ibcon#end of sib2, iclass 40, count 0 2006.169.08:08:17.17#ibcon#*after write, iclass 40, count 0 2006.169.08:08:17.17#ibcon#*before return 0, iclass 40, count 0 2006.169.08:08:17.17#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.169.08:08:17.17#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.169.08:08:17.17#ibcon#about to clear, iclass 40 cls_cnt 0 2006.169.08:08:17.17#ibcon#cleared, iclass 40 cls_cnt 0 2006.169.08:08:17.17$vc4f8/valo=8,852.99 2006.169.08:08:17.17#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.169.08:08:17.17#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.169.08:08:17.17#ibcon#ireg 17 cls_cnt 0 2006.169.08:08:17.17#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:08:17.17#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:08:17.17#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:08:17.17#ibcon#enter wrdev, iclass 4, count 0 2006.169.08:08:17.17#ibcon#first serial, iclass 4, count 0 2006.169.08:08:17.17#ibcon#enter sib2, iclass 4, count 0 2006.169.08:08:17.17#ibcon#flushed, iclass 4, count 0 2006.169.08:08:17.17#ibcon#about to write, iclass 4, count 0 2006.169.08:08:17.17#ibcon#wrote, iclass 4, count 0 2006.169.08:08:17.17#ibcon#about to read 3, iclass 4, count 0 2006.169.08:08:17.19#ibcon#read 3, iclass 4, count 0 2006.169.08:08:17.19#ibcon#about to read 4, iclass 4, count 0 2006.169.08:08:17.19#ibcon#read 4, iclass 4, count 0 2006.169.08:08:17.19#ibcon#about to read 5, iclass 4, count 0 2006.169.08:08:17.19#ibcon#read 5, iclass 4, count 0 2006.169.08:08:17.19#ibcon#about to read 6, iclass 4, count 0 2006.169.08:08:17.19#ibcon#read 6, iclass 4, count 0 2006.169.08:08:17.19#ibcon#end of sib2, iclass 4, count 0 2006.169.08:08:17.19#ibcon#*mode == 0, iclass 4, count 0 2006.169.08:08:17.19#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.169.08:08:17.19#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.08:08:17.19#ibcon#*before write, iclass 4, count 0 2006.169.08:08:17.19#ibcon#enter sib2, iclass 4, count 0 2006.169.08:08:17.19#ibcon#flushed, iclass 4, count 0 2006.169.08:08:17.19#ibcon#about to write, iclass 4, count 0 2006.169.08:08:17.19#ibcon#wrote, iclass 4, count 0 2006.169.08:08:17.19#ibcon#about to read 3, iclass 4, count 0 2006.169.08:08:17.23#ibcon#read 3, iclass 4, count 0 2006.169.08:08:17.23#ibcon#about to read 4, iclass 4, count 0 2006.169.08:08:17.23#ibcon#read 4, iclass 4, count 0 2006.169.08:08:17.23#ibcon#about to read 5, iclass 4, count 0 2006.169.08:08:17.23#ibcon#read 5, iclass 4, count 0 2006.169.08:08:17.23#ibcon#about to read 6, iclass 4, count 0 2006.169.08:08:17.23#ibcon#read 6, iclass 4, count 0 2006.169.08:08:17.23#ibcon#end of sib2, iclass 4, count 0 2006.169.08:08:17.23#ibcon#*after write, iclass 4, count 0 2006.169.08:08:17.23#ibcon#*before return 0, iclass 4, count 0 2006.169.08:08:17.23#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:08:17.23#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:08:17.23#ibcon#about to clear, iclass 4 cls_cnt 0 2006.169.08:08:17.23#ibcon#cleared, iclass 4 cls_cnt 0 2006.169.08:08:17.23$vc4f8/va=8,7 2006.169.08:08:17.23#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.169.08:08:17.23#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.169.08:08:17.23#ibcon#ireg 11 cls_cnt 2 2006.169.08:08:17.23#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.169.08:08:17.29#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.169.08:08:17.29#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.169.08:08:17.29#ibcon#enter wrdev, iclass 6, count 2 2006.169.08:08:17.29#ibcon#first serial, iclass 6, count 2 2006.169.08:08:17.29#ibcon#enter sib2, iclass 6, count 2 2006.169.08:08:17.29#ibcon#flushed, iclass 6, count 2 2006.169.08:08:17.29#ibcon#about to write, iclass 6, count 2 2006.169.08:08:17.29#ibcon#wrote, iclass 6, count 2 2006.169.08:08:17.29#ibcon#about to read 3, iclass 6, count 2 2006.169.08:08:17.31#ibcon#read 3, iclass 6, count 2 2006.169.08:08:17.31#ibcon#about to read 4, iclass 6, count 2 2006.169.08:08:17.31#ibcon#read 4, iclass 6, count 2 2006.169.08:08:17.31#ibcon#about to read 5, iclass 6, count 2 2006.169.08:08:17.31#ibcon#read 5, iclass 6, count 2 2006.169.08:08:17.31#ibcon#about to read 6, iclass 6, count 2 2006.169.08:08:17.31#ibcon#read 6, iclass 6, count 2 2006.169.08:08:17.31#ibcon#end of sib2, iclass 6, count 2 2006.169.08:08:17.31#ibcon#*mode == 0, iclass 6, count 2 2006.169.08:08:17.31#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.169.08:08:17.31#ibcon#[25=AT08-07\r\n] 2006.169.08:08:17.31#ibcon#*before write, iclass 6, count 2 2006.169.08:08:17.31#ibcon#enter sib2, iclass 6, count 2 2006.169.08:08:17.31#ibcon#flushed, iclass 6, count 2 2006.169.08:08:17.31#ibcon#about to write, iclass 6, count 2 2006.169.08:08:17.31#ibcon#wrote, iclass 6, count 2 2006.169.08:08:17.31#ibcon#about to read 3, iclass 6, count 2 2006.169.08:08:17.34#ibcon#read 3, iclass 6, count 2 2006.169.08:08:17.34#ibcon#about to read 4, iclass 6, count 2 2006.169.08:08:17.34#ibcon#read 4, iclass 6, count 2 2006.169.08:08:17.34#ibcon#about to read 5, iclass 6, count 2 2006.169.08:08:17.34#ibcon#read 5, iclass 6, count 2 2006.169.08:08:17.34#ibcon#about to read 6, iclass 6, count 2 2006.169.08:08:17.34#ibcon#read 6, iclass 6, count 2 2006.169.08:08:17.34#ibcon#end of sib2, iclass 6, count 2 2006.169.08:08:17.34#ibcon#*after write, iclass 6, count 2 2006.169.08:08:17.34#ibcon#*before return 0, iclass 6, count 2 2006.169.08:08:17.34#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.169.08:08:17.34#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.169.08:08:17.34#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.169.08:08:17.34#ibcon#ireg 7 cls_cnt 0 2006.169.08:08:17.34#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.169.08:08:17.46#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.169.08:08:17.46#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.169.08:08:17.46#ibcon#enter wrdev, iclass 6, count 0 2006.169.08:08:17.46#ibcon#first serial, iclass 6, count 0 2006.169.08:08:17.46#ibcon#enter sib2, iclass 6, count 0 2006.169.08:08:17.46#ibcon#flushed, iclass 6, count 0 2006.169.08:08:17.46#ibcon#about to write, iclass 6, count 0 2006.169.08:08:17.46#ibcon#wrote, iclass 6, count 0 2006.169.08:08:17.46#ibcon#about to read 3, iclass 6, count 0 2006.169.08:08:17.48#ibcon#read 3, iclass 6, count 0 2006.169.08:08:17.48#ibcon#about to read 4, iclass 6, count 0 2006.169.08:08:17.48#ibcon#read 4, iclass 6, count 0 2006.169.08:08:17.48#ibcon#about to read 5, iclass 6, count 0 2006.169.08:08:17.48#ibcon#read 5, iclass 6, count 0 2006.169.08:08:17.48#ibcon#about to read 6, iclass 6, count 0 2006.169.08:08:17.48#ibcon#read 6, iclass 6, count 0 2006.169.08:08:17.48#ibcon#end of sib2, iclass 6, count 0 2006.169.08:08:17.48#ibcon#*mode == 0, iclass 6, count 0 2006.169.08:08:17.48#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.169.08:08:17.48#ibcon#[25=USB\r\n] 2006.169.08:08:17.48#ibcon#*before write, iclass 6, count 0 2006.169.08:08:17.48#ibcon#enter sib2, iclass 6, count 0 2006.169.08:08:17.48#ibcon#flushed, iclass 6, count 0 2006.169.08:08:17.48#ibcon#about to write, iclass 6, count 0 2006.169.08:08:17.48#ibcon#wrote, iclass 6, count 0 2006.169.08:08:17.48#ibcon#about to read 3, iclass 6, count 0 2006.169.08:08:17.51#ibcon#read 3, iclass 6, count 0 2006.169.08:08:17.51#ibcon#about to read 4, iclass 6, count 0 2006.169.08:08:17.51#ibcon#read 4, iclass 6, count 0 2006.169.08:08:17.51#ibcon#about to read 5, iclass 6, count 0 2006.169.08:08:17.51#ibcon#read 5, iclass 6, count 0 2006.169.08:08:17.51#ibcon#about to read 6, iclass 6, count 0 2006.169.08:08:17.51#ibcon#read 6, iclass 6, count 0 2006.169.08:08:17.51#ibcon#end of sib2, iclass 6, count 0 2006.169.08:08:17.51#ibcon#*after write, iclass 6, count 0 2006.169.08:08:17.51#ibcon#*before return 0, iclass 6, count 0 2006.169.08:08:17.51#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.169.08:08:17.51#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.169.08:08:17.51#ibcon#about to clear, iclass 6 cls_cnt 0 2006.169.08:08:17.51#ibcon#cleared, iclass 6 cls_cnt 0 2006.169.08:08:17.51$vc4f8/vblo=1,632.99 2006.169.08:08:17.51#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.169.08:08:17.51#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.169.08:08:17.51#ibcon#ireg 17 cls_cnt 0 2006.169.08:08:17.51#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.169.08:08:17.51#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.169.08:08:17.51#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.169.08:08:17.51#ibcon#enter wrdev, iclass 10, count 0 2006.169.08:08:17.51#ibcon#first serial, iclass 10, count 0 2006.169.08:08:17.51#ibcon#enter sib2, iclass 10, count 0 2006.169.08:08:17.51#ibcon#flushed, iclass 10, count 0 2006.169.08:08:17.51#ibcon#about to write, iclass 10, count 0 2006.169.08:08:17.51#ibcon#wrote, iclass 10, count 0 2006.169.08:08:17.51#ibcon#about to read 3, iclass 10, count 0 2006.169.08:08:17.53#ibcon#read 3, iclass 10, count 0 2006.169.08:08:17.53#ibcon#about to read 4, iclass 10, count 0 2006.169.08:08:17.53#ibcon#read 4, iclass 10, count 0 2006.169.08:08:17.53#ibcon#about to read 5, iclass 10, count 0 2006.169.08:08:17.53#ibcon#read 5, iclass 10, count 0 2006.169.08:08:17.53#ibcon#about to read 6, iclass 10, count 0 2006.169.08:08:17.53#ibcon#read 6, iclass 10, count 0 2006.169.08:08:17.53#ibcon#end of sib2, iclass 10, count 0 2006.169.08:08:17.53#ibcon#*mode == 0, iclass 10, count 0 2006.169.08:08:17.53#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.169.08:08:17.53#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.08:08:17.53#ibcon#*before write, iclass 10, count 0 2006.169.08:08:17.53#ibcon#enter sib2, iclass 10, count 0 2006.169.08:08:17.53#ibcon#flushed, iclass 10, count 0 2006.169.08:08:17.53#ibcon#about to write, iclass 10, count 0 2006.169.08:08:17.53#ibcon#wrote, iclass 10, count 0 2006.169.08:08:17.53#ibcon#about to read 3, iclass 10, count 0 2006.169.08:08:17.57#ibcon#read 3, iclass 10, count 0 2006.169.08:08:17.57#ibcon#about to read 4, iclass 10, count 0 2006.169.08:08:17.57#ibcon#read 4, iclass 10, count 0 2006.169.08:08:17.57#ibcon#about to read 5, iclass 10, count 0 2006.169.08:08:17.57#ibcon#read 5, iclass 10, count 0 2006.169.08:08:17.57#ibcon#about to read 6, iclass 10, count 0 2006.169.08:08:17.57#ibcon#read 6, iclass 10, count 0 2006.169.08:08:17.57#ibcon#end of sib2, iclass 10, count 0 2006.169.08:08:17.57#ibcon#*after write, iclass 10, count 0 2006.169.08:08:17.57#ibcon#*before return 0, iclass 10, count 0 2006.169.08:08:17.57#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.169.08:08:17.57#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.169.08:08:17.57#ibcon#about to clear, iclass 10 cls_cnt 0 2006.169.08:08:17.57#ibcon#cleared, iclass 10 cls_cnt 0 2006.169.08:08:17.57$vc4f8/vb=1,4 2006.169.08:08:17.57#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.169.08:08:17.57#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.169.08:08:17.57#ibcon#ireg 11 cls_cnt 2 2006.169.08:08:17.57#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.169.08:08:17.57#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.169.08:08:17.57#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.169.08:08:17.57#ibcon#enter wrdev, iclass 12, count 2 2006.169.08:08:17.57#ibcon#first serial, iclass 12, count 2 2006.169.08:08:17.57#ibcon#enter sib2, iclass 12, count 2 2006.169.08:08:17.57#ibcon#flushed, iclass 12, count 2 2006.169.08:08:17.57#ibcon#about to write, iclass 12, count 2 2006.169.08:08:17.57#ibcon#wrote, iclass 12, count 2 2006.169.08:08:17.57#ibcon#about to read 3, iclass 12, count 2 2006.169.08:08:17.59#ibcon#read 3, iclass 12, count 2 2006.169.08:08:17.59#ibcon#about to read 4, iclass 12, count 2 2006.169.08:08:17.59#ibcon#read 4, iclass 12, count 2 2006.169.08:08:17.59#ibcon#about to read 5, iclass 12, count 2 2006.169.08:08:17.59#ibcon#read 5, iclass 12, count 2 2006.169.08:08:17.59#ibcon#about to read 6, iclass 12, count 2 2006.169.08:08:17.59#ibcon#read 6, iclass 12, count 2 2006.169.08:08:17.59#ibcon#end of sib2, iclass 12, count 2 2006.169.08:08:17.59#ibcon#*mode == 0, iclass 12, count 2 2006.169.08:08:17.59#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.169.08:08:17.59#ibcon#[27=AT01-04\r\n] 2006.169.08:08:17.59#ibcon#*before write, iclass 12, count 2 2006.169.08:08:17.59#ibcon#enter sib2, iclass 12, count 2 2006.169.08:08:17.59#ibcon#flushed, iclass 12, count 2 2006.169.08:08:17.59#ibcon#about to write, iclass 12, count 2 2006.169.08:08:17.59#ibcon#wrote, iclass 12, count 2 2006.169.08:08:17.59#ibcon#about to read 3, iclass 12, count 2 2006.169.08:08:17.62#ibcon#read 3, iclass 12, count 2 2006.169.08:08:17.62#ibcon#about to read 4, iclass 12, count 2 2006.169.08:08:17.62#ibcon#read 4, iclass 12, count 2 2006.169.08:08:17.62#ibcon#about to read 5, iclass 12, count 2 2006.169.08:08:17.62#ibcon#read 5, iclass 12, count 2 2006.169.08:08:17.62#ibcon#about to read 6, iclass 12, count 2 2006.169.08:08:17.62#ibcon#read 6, iclass 12, count 2 2006.169.08:08:17.62#ibcon#end of sib2, iclass 12, count 2 2006.169.08:08:17.62#ibcon#*after write, iclass 12, count 2 2006.169.08:08:17.62#ibcon#*before return 0, iclass 12, count 2 2006.169.08:08:17.62#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.169.08:08:17.62#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.169.08:08:17.62#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.169.08:08:17.62#ibcon#ireg 7 cls_cnt 0 2006.169.08:08:17.62#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.169.08:08:17.74#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.169.08:08:17.74#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.169.08:08:17.74#ibcon#enter wrdev, iclass 12, count 0 2006.169.08:08:17.74#ibcon#first serial, iclass 12, count 0 2006.169.08:08:17.74#ibcon#enter sib2, iclass 12, count 0 2006.169.08:08:17.74#ibcon#flushed, iclass 12, count 0 2006.169.08:08:17.74#ibcon#about to write, iclass 12, count 0 2006.169.08:08:17.74#ibcon#wrote, iclass 12, count 0 2006.169.08:08:17.74#ibcon#about to read 3, iclass 12, count 0 2006.169.08:08:17.76#ibcon#read 3, iclass 12, count 0 2006.169.08:08:17.76#ibcon#about to read 4, iclass 12, count 0 2006.169.08:08:17.76#ibcon#read 4, iclass 12, count 0 2006.169.08:08:17.76#ibcon#about to read 5, iclass 12, count 0 2006.169.08:08:17.76#ibcon#read 5, iclass 12, count 0 2006.169.08:08:17.76#ibcon#about to read 6, iclass 12, count 0 2006.169.08:08:17.76#ibcon#read 6, iclass 12, count 0 2006.169.08:08:17.76#ibcon#end of sib2, iclass 12, count 0 2006.169.08:08:17.76#ibcon#*mode == 0, iclass 12, count 0 2006.169.08:08:17.76#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.169.08:08:17.76#ibcon#[27=USB\r\n] 2006.169.08:08:17.76#ibcon#*before write, iclass 12, count 0 2006.169.08:08:17.76#ibcon#enter sib2, iclass 12, count 0 2006.169.08:08:17.76#ibcon#flushed, iclass 12, count 0 2006.169.08:08:17.76#ibcon#about to write, iclass 12, count 0 2006.169.08:08:17.76#ibcon#wrote, iclass 12, count 0 2006.169.08:08:17.76#ibcon#about to read 3, iclass 12, count 0 2006.169.08:08:17.79#ibcon#read 3, iclass 12, count 0 2006.169.08:08:17.79#ibcon#about to read 4, iclass 12, count 0 2006.169.08:08:17.79#ibcon#read 4, iclass 12, count 0 2006.169.08:08:17.79#ibcon#about to read 5, iclass 12, count 0 2006.169.08:08:17.79#ibcon#read 5, iclass 12, count 0 2006.169.08:08:17.79#ibcon#about to read 6, iclass 12, count 0 2006.169.08:08:17.79#ibcon#read 6, iclass 12, count 0 2006.169.08:08:17.79#ibcon#end of sib2, iclass 12, count 0 2006.169.08:08:17.79#ibcon#*after write, iclass 12, count 0 2006.169.08:08:17.79#ibcon#*before return 0, iclass 12, count 0 2006.169.08:08:17.79#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.169.08:08:17.79#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.169.08:08:17.79#ibcon#about to clear, iclass 12 cls_cnt 0 2006.169.08:08:17.79#ibcon#cleared, iclass 12 cls_cnt 0 2006.169.08:08:17.79$vc4f8/vblo=2,640.99 2006.169.08:08:17.79#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.169.08:08:17.79#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.169.08:08:17.79#ibcon#ireg 17 cls_cnt 0 2006.169.08:08:17.79#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:08:17.79#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:08:17.79#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:08:17.79#ibcon#enter wrdev, iclass 14, count 0 2006.169.08:08:17.79#ibcon#first serial, iclass 14, count 0 2006.169.08:08:17.79#ibcon#enter sib2, iclass 14, count 0 2006.169.08:08:17.79#ibcon#flushed, iclass 14, count 0 2006.169.08:08:17.79#ibcon#about to write, iclass 14, count 0 2006.169.08:08:17.79#ibcon#wrote, iclass 14, count 0 2006.169.08:08:17.79#ibcon#about to read 3, iclass 14, count 0 2006.169.08:08:17.81#ibcon#read 3, iclass 14, count 0 2006.169.08:08:17.81#ibcon#about to read 4, iclass 14, count 0 2006.169.08:08:17.81#ibcon#read 4, iclass 14, count 0 2006.169.08:08:17.81#ibcon#about to read 5, iclass 14, count 0 2006.169.08:08:17.81#ibcon#read 5, iclass 14, count 0 2006.169.08:08:17.81#ibcon#about to read 6, iclass 14, count 0 2006.169.08:08:17.81#ibcon#read 6, iclass 14, count 0 2006.169.08:08:17.81#ibcon#end of sib2, iclass 14, count 0 2006.169.08:08:17.81#ibcon#*mode == 0, iclass 14, count 0 2006.169.08:08:17.81#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.169.08:08:17.81#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.08:08:17.81#ibcon#*before write, iclass 14, count 0 2006.169.08:08:17.81#ibcon#enter sib2, iclass 14, count 0 2006.169.08:08:17.81#ibcon#flushed, iclass 14, count 0 2006.169.08:08:17.81#ibcon#about to write, iclass 14, count 0 2006.169.08:08:17.81#ibcon#wrote, iclass 14, count 0 2006.169.08:08:17.81#ibcon#about to read 3, iclass 14, count 0 2006.169.08:08:17.85#ibcon#read 3, iclass 14, count 0 2006.169.08:08:17.85#ibcon#about to read 4, iclass 14, count 0 2006.169.08:08:17.85#ibcon#read 4, iclass 14, count 0 2006.169.08:08:17.85#ibcon#about to read 5, iclass 14, count 0 2006.169.08:08:17.85#ibcon#read 5, iclass 14, count 0 2006.169.08:08:17.85#ibcon#about to read 6, iclass 14, count 0 2006.169.08:08:17.85#ibcon#read 6, iclass 14, count 0 2006.169.08:08:17.85#ibcon#end of sib2, iclass 14, count 0 2006.169.08:08:17.85#ibcon#*after write, iclass 14, count 0 2006.169.08:08:17.85#ibcon#*before return 0, iclass 14, count 0 2006.169.08:08:17.85#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:08:17.85#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:08:17.85#ibcon#about to clear, iclass 14 cls_cnt 0 2006.169.08:08:17.85#ibcon#cleared, iclass 14 cls_cnt 0 2006.169.08:08:17.85$vc4f8/vb=2,4 2006.169.08:08:17.85#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.169.08:08:17.85#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.169.08:08:17.85#ibcon#ireg 11 cls_cnt 2 2006.169.08:08:17.85#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.169.08:08:17.91#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.169.08:08:17.91#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.169.08:08:17.91#ibcon#enter wrdev, iclass 16, count 2 2006.169.08:08:17.91#ibcon#first serial, iclass 16, count 2 2006.169.08:08:17.91#ibcon#enter sib2, iclass 16, count 2 2006.169.08:08:17.91#ibcon#flushed, iclass 16, count 2 2006.169.08:08:17.91#ibcon#about to write, iclass 16, count 2 2006.169.08:08:17.91#ibcon#wrote, iclass 16, count 2 2006.169.08:08:17.91#ibcon#about to read 3, iclass 16, count 2 2006.169.08:08:17.93#ibcon#read 3, iclass 16, count 2 2006.169.08:08:17.93#ibcon#about to read 4, iclass 16, count 2 2006.169.08:08:17.93#ibcon#read 4, iclass 16, count 2 2006.169.08:08:17.93#ibcon#about to read 5, iclass 16, count 2 2006.169.08:08:17.93#ibcon#read 5, iclass 16, count 2 2006.169.08:08:17.93#ibcon#about to read 6, iclass 16, count 2 2006.169.08:08:17.93#ibcon#read 6, iclass 16, count 2 2006.169.08:08:17.93#ibcon#end of sib2, iclass 16, count 2 2006.169.08:08:17.93#ibcon#*mode == 0, iclass 16, count 2 2006.169.08:08:17.93#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.169.08:08:17.93#ibcon#[27=AT02-04\r\n] 2006.169.08:08:17.93#ibcon#*before write, iclass 16, count 2 2006.169.08:08:17.93#ibcon#enter sib2, iclass 16, count 2 2006.169.08:08:17.93#ibcon#flushed, iclass 16, count 2 2006.169.08:08:17.93#ibcon#about to write, iclass 16, count 2 2006.169.08:08:17.93#ibcon#wrote, iclass 16, count 2 2006.169.08:08:17.93#ibcon#about to read 3, iclass 16, count 2 2006.169.08:08:17.96#ibcon#read 3, iclass 16, count 2 2006.169.08:08:17.96#ibcon#about to read 4, iclass 16, count 2 2006.169.08:08:17.96#ibcon#read 4, iclass 16, count 2 2006.169.08:08:17.96#ibcon#about to read 5, iclass 16, count 2 2006.169.08:08:17.96#ibcon#read 5, iclass 16, count 2 2006.169.08:08:17.96#ibcon#about to read 6, iclass 16, count 2 2006.169.08:08:17.96#ibcon#read 6, iclass 16, count 2 2006.169.08:08:17.96#ibcon#end of sib2, iclass 16, count 2 2006.169.08:08:17.96#ibcon#*after write, iclass 16, count 2 2006.169.08:08:17.96#ibcon#*before return 0, iclass 16, count 2 2006.169.08:08:17.96#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.169.08:08:17.96#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.169.08:08:17.96#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.169.08:08:17.96#ibcon#ireg 7 cls_cnt 0 2006.169.08:08:17.96#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.169.08:08:18.08#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.169.08:08:18.08#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.169.08:08:18.08#ibcon#enter wrdev, iclass 16, count 0 2006.169.08:08:18.08#ibcon#first serial, iclass 16, count 0 2006.169.08:08:18.08#ibcon#enter sib2, iclass 16, count 0 2006.169.08:08:18.08#ibcon#flushed, iclass 16, count 0 2006.169.08:08:18.08#ibcon#about to write, iclass 16, count 0 2006.169.08:08:18.08#ibcon#wrote, iclass 16, count 0 2006.169.08:08:18.08#ibcon#about to read 3, iclass 16, count 0 2006.169.08:08:18.10#ibcon#read 3, iclass 16, count 0 2006.169.08:08:18.10#ibcon#about to read 4, iclass 16, count 0 2006.169.08:08:18.10#ibcon#read 4, iclass 16, count 0 2006.169.08:08:18.10#ibcon#about to read 5, iclass 16, count 0 2006.169.08:08:18.10#ibcon#read 5, iclass 16, count 0 2006.169.08:08:18.10#ibcon#about to read 6, iclass 16, count 0 2006.169.08:08:18.10#ibcon#read 6, iclass 16, count 0 2006.169.08:08:18.10#ibcon#end of sib2, iclass 16, count 0 2006.169.08:08:18.10#ibcon#*mode == 0, iclass 16, count 0 2006.169.08:08:18.10#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.169.08:08:18.10#ibcon#[27=USB\r\n] 2006.169.08:08:18.10#ibcon#*before write, iclass 16, count 0 2006.169.08:08:18.10#ibcon#enter sib2, iclass 16, count 0 2006.169.08:08:18.10#ibcon#flushed, iclass 16, count 0 2006.169.08:08:18.10#ibcon#about to write, iclass 16, count 0 2006.169.08:08:18.10#ibcon#wrote, iclass 16, count 0 2006.169.08:08:18.10#ibcon#about to read 3, iclass 16, count 0 2006.169.08:08:18.13#ibcon#read 3, iclass 16, count 0 2006.169.08:08:18.13#ibcon#about to read 4, iclass 16, count 0 2006.169.08:08:18.13#ibcon#read 4, iclass 16, count 0 2006.169.08:08:18.13#ibcon#about to read 5, iclass 16, count 0 2006.169.08:08:18.13#ibcon#read 5, iclass 16, count 0 2006.169.08:08:18.13#ibcon#about to read 6, iclass 16, count 0 2006.169.08:08:18.13#ibcon#read 6, iclass 16, count 0 2006.169.08:08:18.13#ibcon#end of sib2, iclass 16, count 0 2006.169.08:08:18.13#ibcon#*after write, iclass 16, count 0 2006.169.08:08:18.13#ibcon#*before return 0, iclass 16, count 0 2006.169.08:08:18.13#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.169.08:08:18.13#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.169.08:08:18.13#ibcon#about to clear, iclass 16 cls_cnt 0 2006.169.08:08:18.13#ibcon#cleared, iclass 16 cls_cnt 0 2006.169.08:08:18.13$vc4f8/vblo=3,656.99 2006.169.08:08:18.13#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.169.08:08:18.13#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.169.08:08:18.13#ibcon#ireg 17 cls_cnt 0 2006.169.08:08:18.13#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:08:18.13#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:08:18.13#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:08:18.13#ibcon#enter wrdev, iclass 18, count 0 2006.169.08:08:18.13#ibcon#first serial, iclass 18, count 0 2006.169.08:08:18.13#ibcon#enter sib2, iclass 18, count 0 2006.169.08:08:18.13#ibcon#flushed, iclass 18, count 0 2006.169.08:08:18.13#ibcon#about to write, iclass 18, count 0 2006.169.08:08:18.13#ibcon#wrote, iclass 18, count 0 2006.169.08:08:18.13#ibcon#about to read 3, iclass 18, count 0 2006.169.08:08:18.15#ibcon#read 3, iclass 18, count 0 2006.169.08:08:18.15#ibcon#about to read 4, iclass 18, count 0 2006.169.08:08:18.15#ibcon#read 4, iclass 18, count 0 2006.169.08:08:18.15#ibcon#about to read 5, iclass 18, count 0 2006.169.08:08:18.15#ibcon#read 5, iclass 18, count 0 2006.169.08:08:18.15#ibcon#about to read 6, iclass 18, count 0 2006.169.08:08:18.15#ibcon#read 6, iclass 18, count 0 2006.169.08:08:18.15#ibcon#end of sib2, iclass 18, count 0 2006.169.08:08:18.15#ibcon#*mode == 0, iclass 18, count 0 2006.169.08:08:18.15#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.169.08:08:18.15#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.08:08:18.15#ibcon#*before write, iclass 18, count 0 2006.169.08:08:18.15#ibcon#enter sib2, iclass 18, count 0 2006.169.08:08:18.15#ibcon#flushed, iclass 18, count 0 2006.169.08:08:18.15#ibcon#about to write, iclass 18, count 0 2006.169.08:08:18.15#ibcon#wrote, iclass 18, count 0 2006.169.08:08:18.15#ibcon#about to read 3, iclass 18, count 0 2006.169.08:08:18.19#ibcon#read 3, iclass 18, count 0 2006.169.08:08:18.19#ibcon#about to read 4, iclass 18, count 0 2006.169.08:08:18.19#ibcon#read 4, iclass 18, count 0 2006.169.08:08:18.19#ibcon#about to read 5, iclass 18, count 0 2006.169.08:08:18.19#ibcon#read 5, iclass 18, count 0 2006.169.08:08:18.19#ibcon#about to read 6, iclass 18, count 0 2006.169.08:08:18.19#ibcon#read 6, iclass 18, count 0 2006.169.08:08:18.19#ibcon#end of sib2, iclass 18, count 0 2006.169.08:08:18.19#ibcon#*after write, iclass 18, count 0 2006.169.08:08:18.19#ibcon#*before return 0, iclass 18, count 0 2006.169.08:08:18.19#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:08:18.19#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:08:18.19#ibcon#about to clear, iclass 18 cls_cnt 0 2006.169.08:08:18.19#ibcon#cleared, iclass 18 cls_cnt 0 2006.169.08:08:18.19$vc4f8/vb=3,4 2006.169.08:08:18.19#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.169.08:08:18.19#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.169.08:08:18.19#ibcon#ireg 11 cls_cnt 2 2006.169.08:08:18.19#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.169.08:08:18.25#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.169.08:08:18.25#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.169.08:08:18.25#ibcon#enter wrdev, iclass 20, count 2 2006.169.08:08:18.25#ibcon#first serial, iclass 20, count 2 2006.169.08:08:18.25#ibcon#enter sib2, iclass 20, count 2 2006.169.08:08:18.25#ibcon#flushed, iclass 20, count 2 2006.169.08:08:18.25#ibcon#about to write, iclass 20, count 2 2006.169.08:08:18.25#ibcon#wrote, iclass 20, count 2 2006.169.08:08:18.25#ibcon#about to read 3, iclass 20, count 2 2006.169.08:08:18.27#ibcon#read 3, iclass 20, count 2 2006.169.08:08:18.27#ibcon#about to read 4, iclass 20, count 2 2006.169.08:08:18.27#ibcon#read 4, iclass 20, count 2 2006.169.08:08:18.27#ibcon#about to read 5, iclass 20, count 2 2006.169.08:08:18.27#ibcon#read 5, iclass 20, count 2 2006.169.08:08:18.27#ibcon#about to read 6, iclass 20, count 2 2006.169.08:08:18.27#ibcon#read 6, iclass 20, count 2 2006.169.08:08:18.27#ibcon#end of sib2, iclass 20, count 2 2006.169.08:08:18.27#ibcon#*mode == 0, iclass 20, count 2 2006.169.08:08:18.27#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.169.08:08:18.27#ibcon#[27=AT03-04\r\n] 2006.169.08:08:18.27#ibcon#*before write, iclass 20, count 2 2006.169.08:08:18.27#ibcon#enter sib2, iclass 20, count 2 2006.169.08:08:18.27#ibcon#flushed, iclass 20, count 2 2006.169.08:08:18.27#ibcon#about to write, iclass 20, count 2 2006.169.08:08:18.27#ibcon#wrote, iclass 20, count 2 2006.169.08:08:18.27#ibcon#about to read 3, iclass 20, count 2 2006.169.08:08:18.30#ibcon#read 3, iclass 20, count 2 2006.169.08:08:18.30#ibcon#about to read 4, iclass 20, count 2 2006.169.08:08:18.30#ibcon#read 4, iclass 20, count 2 2006.169.08:08:18.30#ibcon#about to read 5, iclass 20, count 2 2006.169.08:08:18.30#ibcon#read 5, iclass 20, count 2 2006.169.08:08:18.30#ibcon#about to read 6, iclass 20, count 2 2006.169.08:08:18.30#ibcon#read 6, iclass 20, count 2 2006.169.08:08:18.30#ibcon#end of sib2, iclass 20, count 2 2006.169.08:08:18.30#ibcon#*after write, iclass 20, count 2 2006.169.08:08:18.30#ibcon#*before return 0, iclass 20, count 2 2006.169.08:08:18.30#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.169.08:08:18.30#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.169.08:08:18.30#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.169.08:08:18.30#ibcon#ireg 7 cls_cnt 0 2006.169.08:08:18.30#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.169.08:08:18.42#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.169.08:08:18.42#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.169.08:08:18.42#ibcon#enter wrdev, iclass 20, count 0 2006.169.08:08:18.42#ibcon#first serial, iclass 20, count 0 2006.169.08:08:18.42#ibcon#enter sib2, iclass 20, count 0 2006.169.08:08:18.42#ibcon#flushed, iclass 20, count 0 2006.169.08:08:18.42#ibcon#about to write, iclass 20, count 0 2006.169.08:08:18.42#ibcon#wrote, iclass 20, count 0 2006.169.08:08:18.42#ibcon#about to read 3, iclass 20, count 0 2006.169.08:08:18.44#ibcon#read 3, iclass 20, count 0 2006.169.08:08:18.44#ibcon#about to read 4, iclass 20, count 0 2006.169.08:08:18.44#ibcon#read 4, iclass 20, count 0 2006.169.08:08:18.44#ibcon#about to read 5, iclass 20, count 0 2006.169.08:08:18.44#ibcon#read 5, iclass 20, count 0 2006.169.08:08:18.44#ibcon#about to read 6, iclass 20, count 0 2006.169.08:08:18.44#ibcon#read 6, iclass 20, count 0 2006.169.08:08:18.44#ibcon#end of sib2, iclass 20, count 0 2006.169.08:08:18.44#ibcon#*mode == 0, iclass 20, count 0 2006.169.08:08:18.44#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.169.08:08:18.44#ibcon#[27=USB\r\n] 2006.169.08:08:18.44#ibcon#*before write, iclass 20, count 0 2006.169.08:08:18.44#ibcon#enter sib2, iclass 20, count 0 2006.169.08:08:18.44#ibcon#flushed, iclass 20, count 0 2006.169.08:08:18.44#ibcon#about to write, iclass 20, count 0 2006.169.08:08:18.44#ibcon#wrote, iclass 20, count 0 2006.169.08:08:18.44#ibcon#about to read 3, iclass 20, count 0 2006.169.08:08:18.47#ibcon#read 3, iclass 20, count 0 2006.169.08:08:18.47#ibcon#about to read 4, iclass 20, count 0 2006.169.08:08:18.47#ibcon#read 4, iclass 20, count 0 2006.169.08:08:18.47#ibcon#about to read 5, iclass 20, count 0 2006.169.08:08:18.47#ibcon#read 5, iclass 20, count 0 2006.169.08:08:18.47#ibcon#about to read 6, iclass 20, count 0 2006.169.08:08:18.47#ibcon#read 6, iclass 20, count 0 2006.169.08:08:18.47#ibcon#end of sib2, iclass 20, count 0 2006.169.08:08:18.47#ibcon#*after write, iclass 20, count 0 2006.169.08:08:18.47#ibcon#*before return 0, iclass 20, count 0 2006.169.08:08:18.47#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.169.08:08:18.47#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.169.08:08:18.47#ibcon#about to clear, iclass 20 cls_cnt 0 2006.169.08:08:18.47#ibcon#cleared, iclass 20 cls_cnt 0 2006.169.08:08:18.47$vc4f8/vblo=4,712.99 2006.169.08:08:18.47#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.169.08:08:18.47#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.169.08:08:18.47#ibcon#ireg 17 cls_cnt 0 2006.169.08:08:18.47#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.169.08:08:18.47#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.169.08:08:18.47#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.169.08:08:18.47#ibcon#enter wrdev, iclass 22, count 0 2006.169.08:08:18.47#ibcon#first serial, iclass 22, count 0 2006.169.08:08:18.47#ibcon#enter sib2, iclass 22, count 0 2006.169.08:08:18.47#ibcon#flushed, iclass 22, count 0 2006.169.08:08:18.47#ibcon#about to write, iclass 22, count 0 2006.169.08:08:18.47#ibcon#wrote, iclass 22, count 0 2006.169.08:08:18.47#ibcon#about to read 3, iclass 22, count 0 2006.169.08:08:18.49#ibcon#read 3, iclass 22, count 0 2006.169.08:08:18.49#ibcon#about to read 4, iclass 22, count 0 2006.169.08:08:18.49#ibcon#read 4, iclass 22, count 0 2006.169.08:08:18.49#ibcon#about to read 5, iclass 22, count 0 2006.169.08:08:18.49#ibcon#read 5, iclass 22, count 0 2006.169.08:08:18.49#ibcon#about to read 6, iclass 22, count 0 2006.169.08:08:18.49#ibcon#read 6, iclass 22, count 0 2006.169.08:08:18.49#ibcon#end of sib2, iclass 22, count 0 2006.169.08:08:18.49#ibcon#*mode == 0, iclass 22, count 0 2006.169.08:08:18.49#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.169.08:08:18.49#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.08:08:18.49#ibcon#*before write, iclass 22, count 0 2006.169.08:08:18.49#ibcon#enter sib2, iclass 22, count 0 2006.169.08:08:18.49#ibcon#flushed, iclass 22, count 0 2006.169.08:08:18.49#ibcon#about to write, iclass 22, count 0 2006.169.08:08:18.49#ibcon#wrote, iclass 22, count 0 2006.169.08:08:18.49#ibcon#about to read 3, iclass 22, count 0 2006.169.08:08:18.53#ibcon#read 3, iclass 22, count 0 2006.169.08:08:18.53#ibcon#about to read 4, iclass 22, count 0 2006.169.08:08:18.53#ibcon#read 4, iclass 22, count 0 2006.169.08:08:18.53#ibcon#about to read 5, iclass 22, count 0 2006.169.08:08:18.53#ibcon#read 5, iclass 22, count 0 2006.169.08:08:18.53#ibcon#about to read 6, iclass 22, count 0 2006.169.08:08:18.53#ibcon#read 6, iclass 22, count 0 2006.169.08:08:18.53#ibcon#end of sib2, iclass 22, count 0 2006.169.08:08:18.53#ibcon#*after write, iclass 22, count 0 2006.169.08:08:18.53#ibcon#*before return 0, iclass 22, count 0 2006.169.08:08:18.53#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.169.08:08:18.53#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.169.08:08:18.53#ibcon#about to clear, iclass 22 cls_cnt 0 2006.169.08:08:18.53#ibcon#cleared, iclass 22 cls_cnt 0 2006.169.08:08:18.53$vc4f8/vb=4,4 2006.169.08:08:18.53#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.169.08:08:18.53#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.169.08:08:18.53#ibcon#ireg 11 cls_cnt 2 2006.169.08:08:18.53#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.169.08:08:18.59#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.169.08:08:18.59#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.169.08:08:18.59#ibcon#enter wrdev, iclass 24, count 2 2006.169.08:08:18.59#ibcon#first serial, iclass 24, count 2 2006.169.08:08:18.59#ibcon#enter sib2, iclass 24, count 2 2006.169.08:08:18.59#ibcon#flushed, iclass 24, count 2 2006.169.08:08:18.59#ibcon#about to write, iclass 24, count 2 2006.169.08:08:18.59#ibcon#wrote, iclass 24, count 2 2006.169.08:08:18.59#ibcon#about to read 3, iclass 24, count 2 2006.169.08:08:18.61#ibcon#read 3, iclass 24, count 2 2006.169.08:08:18.61#ibcon#about to read 4, iclass 24, count 2 2006.169.08:08:18.61#ibcon#read 4, iclass 24, count 2 2006.169.08:08:18.61#ibcon#about to read 5, iclass 24, count 2 2006.169.08:08:18.61#ibcon#read 5, iclass 24, count 2 2006.169.08:08:18.61#ibcon#about to read 6, iclass 24, count 2 2006.169.08:08:18.61#ibcon#read 6, iclass 24, count 2 2006.169.08:08:18.61#ibcon#end of sib2, iclass 24, count 2 2006.169.08:08:18.61#ibcon#*mode == 0, iclass 24, count 2 2006.169.08:08:18.61#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.169.08:08:18.61#ibcon#[27=AT04-04\r\n] 2006.169.08:08:18.61#ibcon#*before write, iclass 24, count 2 2006.169.08:08:18.61#ibcon#enter sib2, iclass 24, count 2 2006.169.08:08:18.61#ibcon#flushed, iclass 24, count 2 2006.169.08:08:18.61#ibcon#about to write, iclass 24, count 2 2006.169.08:08:18.61#ibcon#wrote, iclass 24, count 2 2006.169.08:08:18.61#ibcon#about to read 3, iclass 24, count 2 2006.169.08:08:18.64#ibcon#read 3, iclass 24, count 2 2006.169.08:08:18.64#ibcon#about to read 4, iclass 24, count 2 2006.169.08:08:18.64#ibcon#read 4, iclass 24, count 2 2006.169.08:08:18.64#ibcon#about to read 5, iclass 24, count 2 2006.169.08:08:18.64#ibcon#read 5, iclass 24, count 2 2006.169.08:08:18.64#ibcon#about to read 6, iclass 24, count 2 2006.169.08:08:18.64#ibcon#read 6, iclass 24, count 2 2006.169.08:08:18.64#ibcon#end of sib2, iclass 24, count 2 2006.169.08:08:18.64#ibcon#*after write, iclass 24, count 2 2006.169.08:08:18.64#ibcon#*before return 0, iclass 24, count 2 2006.169.08:08:18.64#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.169.08:08:18.64#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.169.08:08:18.64#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.169.08:08:18.64#ibcon#ireg 7 cls_cnt 0 2006.169.08:08:18.64#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.169.08:08:18.76#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.169.08:08:18.76#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.169.08:08:18.76#ibcon#enter wrdev, iclass 24, count 0 2006.169.08:08:18.76#ibcon#first serial, iclass 24, count 0 2006.169.08:08:18.76#ibcon#enter sib2, iclass 24, count 0 2006.169.08:08:18.76#ibcon#flushed, iclass 24, count 0 2006.169.08:08:18.76#ibcon#about to write, iclass 24, count 0 2006.169.08:08:18.76#ibcon#wrote, iclass 24, count 0 2006.169.08:08:18.76#ibcon#about to read 3, iclass 24, count 0 2006.169.08:08:18.78#ibcon#read 3, iclass 24, count 0 2006.169.08:08:18.78#ibcon#about to read 4, iclass 24, count 0 2006.169.08:08:18.78#ibcon#read 4, iclass 24, count 0 2006.169.08:08:18.78#ibcon#about to read 5, iclass 24, count 0 2006.169.08:08:18.78#ibcon#read 5, iclass 24, count 0 2006.169.08:08:18.78#ibcon#about to read 6, iclass 24, count 0 2006.169.08:08:18.78#ibcon#read 6, iclass 24, count 0 2006.169.08:08:18.78#ibcon#end of sib2, iclass 24, count 0 2006.169.08:08:18.78#ibcon#*mode == 0, iclass 24, count 0 2006.169.08:08:18.78#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.169.08:08:18.78#ibcon#[27=USB\r\n] 2006.169.08:08:18.78#ibcon#*before write, iclass 24, count 0 2006.169.08:08:18.78#ibcon#enter sib2, iclass 24, count 0 2006.169.08:08:18.78#ibcon#flushed, iclass 24, count 0 2006.169.08:08:18.78#ibcon#about to write, iclass 24, count 0 2006.169.08:08:18.78#ibcon#wrote, iclass 24, count 0 2006.169.08:08:18.78#ibcon#about to read 3, iclass 24, count 0 2006.169.08:08:18.81#ibcon#read 3, iclass 24, count 0 2006.169.08:08:18.81#ibcon#about to read 4, iclass 24, count 0 2006.169.08:08:18.81#ibcon#read 4, iclass 24, count 0 2006.169.08:08:18.81#ibcon#about to read 5, iclass 24, count 0 2006.169.08:08:18.81#ibcon#read 5, iclass 24, count 0 2006.169.08:08:18.81#ibcon#about to read 6, iclass 24, count 0 2006.169.08:08:18.81#ibcon#read 6, iclass 24, count 0 2006.169.08:08:18.81#ibcon#end of sib2, iclass 24, count 0 2006.169.08:08:18.81#ibcon#*after write, iclass 24, count 0 2006.169.08:08:18.81#ibcon#*before return 0, iclass 24, count 0 2006.169.08:08:18.81#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.169.08:08:18.81#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.169.08:08:18.81#ibcon#about to clear, iclass 24 cls_cnt 0 2006.169.08:08:18.81#ibcon#cleared, iclass 24 cls_cnt 0 2006.169.08:08:18.81$vc4f8/vblo=5,744.99 2006.169.08:08:18.81#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.169.08:08:18.81#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.169.08:08:18.81#ibcon#ireg 17 cls_cnt 0 2006.169.08:08:18.81#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:08:18.81#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:08:18.81#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:08:18.81#ibcon#enter wrdev, iclass 26, count 0 2006.169.08:08:18.81#ibcon#first serial, iclass 26, count 0 2006.169.08:08:18.81#ibcon#enter sib2, iclass 26, count 0 2006.169.08:08:18.81#ibcon#flushed, iclass 26, count 0 2006.169.08:08:18.81#ibcon#about to write, iclass 26, count 0 2006.169.08:08:18.81#ibcon#wrote, iclass 26, count 0 2006.169.08:08:18.81#ibcon#about to read 3, iclass 26, count 0 2006.169.08:08:18.83#ibcon#read 3, iclass 26, count 0 2006.169.08:08:18.83#ibcon#about to read 4, iclass 26, count 0 2006.169.08:08:18.83#ibcon#read 4, iclass 26, count 0 2006.169.08:08:18.83#ibcon#about to read 5, iclass 26, count 0 2006.169.08:08:18.83#ibcon#read 5, iclass 26, count 0 2006.169.08:08:18.83#ibcon#about to read 6, iclass 26, count 0 2006.169.08:08:18.83#ibcon#read 6, iclass 26, count 0 2006.169.08:08:18.83#ibcon#end of sib2, iclass 26, count 0 2006.169.08:08:18.83#ibcon#*mode == 0, iclass 26, count 0 2006.169.08:08:18.83#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.169.08:08:18.83#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.08:08:18.83#ibcon#*before write, iclass 26, count 0 2006.169.08:08:18.83#ibcon#enter sib2, iclass 26, count 0 2006.169.08:08:18.83#ibcon#flushed, iclass 26, count 0 2006.169.08:08:18.83#ibcon#about to write, iclass 26, count 0 2006.169.08:08:18.83#ibcon#wrote, iclass 26, count 0 2006.169.08:08:18.83#ibcon#about to read 3, iclass 26, count 0 2006.169.08:08:18.87#ibcon#read 3, iclass 26, count 0 2006.169.08:08:18.87#ibcon#about to read 4, iclass 26, count 0 2006.169.08:08:18.87#ibcon#read 4, iclass 26, count 0 2006.169.08:08:18.87#ibcon#about to read 5, iclass 26, count 0 2006.169.08:08:18.87#ibcon#read 5, iclass 26, count 0 2006.169.08:08:18.87#ibcon#about to read 6, iclass 26, count 0 2006.169.08:08:18.87#ibcon#read 6, iclass 26, count 0 2006.169.08:08:18.87#ibcon#end of sib2, iclass 26, count 0 2006.169.08:08:18.87#ibcon#*after write, iclass 26, count 0 2006.169.08:08:18.87#ibcon#*before return 0, iclass 26, count 0 2006.169.08:08:18.87#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:08:18.87#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:08:18.87#ibcon#about to clear, iclass 26 cls_cnt 0 2006.169.08:08:18.87#ibcon#cleared, iclass 26 cls_cnt 0 2006.169.08:08:18.87$vc4f8/vb=5,4 2006.169.08:08:18.87#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.169.08:08:18.87#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.169.08:08:18.87#ibcon#ireg 11 cls_cnt 2 2006.169.08:08:18.87#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.169.08:08:18.93#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.169.08:08:18.93#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.169.08:08:18.93#ibcon#enter wrdev, iclass 28, count 2 2006.169.08:08:18.93#ibcon#first serial, iclass 28, count 2 2006.169.08:08:18.93#ibcon#enter sib2, iclass 28, count 2 2006.169.08:08:18.93#ibcon#flushed, iclass 28, count 2 2006.169.08:08:18.93#ibcon#about to write, iclass 28, count 2 2006.169.08:08:18.93#ibcon#wrote, iclass 28, count 2 2006.169.08:08:18.93#ibcon#about to read 3, iclass 28, count 2 2006.169.08:08:18.95#ibcon#read 3, iclass 28, count 2 2006.169.08:08:18.95#ibcon#about to read 4, iclass 28, count 2 2006.169.08:08:18.95#ibcon#read 4, iclass 28, count 2 2006.169.08:08:18.95#ibcon#about to read 5, iclass 28, count 2 2006.169.08:08:18.95#ibcon#read 5, iclass 28, count 2 2006.169.08:08:18.95#ibcon#about to read 6, iclass 28, count 2 2006.169.08:08:18.95#ibcon#read 6, iclass 28, count 2 2006.169.08:08:18.95#ibcon#end of sib2, iclass 28, count 2 2006.169.08:08:18.95#ibcon#*mode == 0, iclass 28, count 2 2006.169.08:08:18.95#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.169.08:08:18.95#ibcon#[27=AT05-04\r\n] 2006.169.08:08:18.95#ibcon#*before write, iclass 28, count 2 2006.169.08:08:18.95#ibcon#enter sib2, iclass 28, count 2 2006.169.08:08:18.95#ibcon#flushed, iclass 28, count 2 2006.169.08:08:18.95#ibcon#about to write, iclass 28, count 2 2006.169.08:08:18.95#ibcon#wrote, iclass 28, count 2 2006.169.08:08:18.95#ibcon#about to read 3, iclass 28, count 2 2006.169.08:08:18.98#ibcon#read 3, iclass 28, count 2 2006.169.08:08:18.98#ibcon#about to read 4, iclass 28, count 2 2006.169.08:08:18.98#ibcon#read 4, iclass 28, count 2 2006.169.08:08:18.98#ibcon#about to read 5, iclass 28, count 2 2006.169.08:08:18.98#ibcon#read 5, iclass 28, count 2 2006.169.08:08:18.98#ibcon#about to read 6, iclass 28, count 2 2006.169.08:08:18.98#ibcon#read 6, iclass 28, count 2 2006.169.08:08:18.98#ibcon#end of sib2, iclass 28, count 2 2006.169.08:08:18.98#ibcon#*after write, iclass 28, count 2 2006.169.08:08:18.98#ibcon#*before return 0, iclass 28, count 2 2006.169.08:08:18.98#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.169.08:08:18.98#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.169.08:08:18.98#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.169.08:08:18.98#ibcon#ireg 7 cls_cnt 0 2006.169.08:08:18.98#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.169.08:08:19.10#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.169.08:08:19.10#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.169.08:08:19.10#ibcon#enter wrdev, iclass 28, count 0 2006.169.08:08:19.10#ibcon#first serial, iclass 28, count 0 2006.169.08:08:19.10#ibcon#enter sib2, iclass 28, count 0 2006.169.08:08:19.10#ibcon#flushed, iclass 28, count 0 2006.169.08:08:19.10#ibcon#about to write, iclass 28, count 0 2006.169.08:08:19.10#ibcon#wrote, iclass 28, count 0 2006.169.08:08:19.10#ibcon#about to read 3, iclass 28, count 0 2006.169.08:08:19.12#ibcon#read 3, iclass 28, count 0 2006.169.08:08:19.12#ibcon#about to read 4, iclass 28, count 0 2006.169.08:08:19.12#ibcon#read 4, iclass 28, count 0 2006.169.08:08:19.12#ibcon#about to read 5, iclass 28, count 0 2006.169.08:08:19.12#ibcon#read 5, iclass 28, count 0 2006.169.08:08:19.12#ibcon#about to read 6, iclass 28, count 0 2006.169.08:08:19.12#ibcon#read 6, iclass 28, count 0 2006.169.08:08:19.12#ibcon#end of sib2, iclass 28, count 0 2006.169.08:08:19.12#ibcon#*mode == 0, iclass 28, count 0 2006.169.08:08:19.12#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.169.08:08:19.12#ibcon#[27=USB\r\n] 2006.169.08:08:19.12#ibcon#*before write, iclass 28, count 0 2006.169.08:08:19.12#ibcon#enter sib2, iclass 28, count 0 2006.169.08:08:19.12#ibcon#flushed, iclass 28, count 0 2006.169.08:08:19.12#ibcon#about to write, iclass 28, count 0 2006.169.08:08:19.12#ibcon#wrote, iclass 28, count 0 2006.169.08:08:19.12#ibcon#about to read 3, iclass 28, count 0 2006.169.08:08:19.15#ibcon#read 3, iclass 28, count 0 2006.169.08:08:19.15#ibcon#about to read 4, iclass 28, count 0 2006.169.08:08:19.15#ibcon#read 4, iclass 28, count 0 2006.169.08:08:19.15#ibcon#about to read 5, iclass 28, count 0 2006.169.08:08:19.15#ibcon#read 5, iclass 28, count 0 2006.169.08:08:19.15#ibcon#about to read 6, iclass 28, count 0 2006.169.08:08:19.15#ibcon#read 6, iclass 28, count 0 2006.169.08:08:19.15#ibcon#end of sib2, iclass 28, count 0 2006.169.08:08:19.15#ibcon#*after write, iclass 28, count 0 2006.169.08:08:19.15#ibcon#*before return 0, iclass 28, count 0 2006.169.08:08:19.15#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.169.08:08:19.15#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.169.08:08:19.15#ibcon#about to clear, iclass 28 cls_cnt 0 2006.169.08:08:19.15#ibcon#cleared, iclass 28 cls_cnt 0 2006.169.08:08:19.15$vc4f8/vblo=6,752.99 2006.169.08:08:19.15#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.169.08:08:19.15#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.169.08:08:19.15#ibcon#ireg 17 cls_cnt 0 2006.169.08:08:19.15#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.169.08:08:19.15#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.169.08:08:19.15#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.169.08:08:19.15#ibcon#enter wrdev, iclass 30, count 0 2006.169.08:08:19.15#ibcon#first serial, iclass 30, count 0 2006.169.08:08:19.15#ibcon#enter sib2, iclass 30, count 0 2006.169.08:08:19.15#ibcon#flushed, iclass 30, count 0 2006.169.08:08:19.15#ibcon#about to write, iclass 30, count 0 2006.169.08:08:19.15#ibcon#wrote, iclass 30, count 0 2006.169.08:08:19.15#ibcon#about to read 3, iclass 30, count 0 2006.169.08:08:19.17#ibcon#read 3, iclass 30, count 0 2006.169.08:08:19.17#ibcon#about to read 4, iclass 30, count 0 2006.169.08:08:19.17#ibcon#read 4, iclass 30, count 0 2006.169.08:08:19.17#ibcon#about to read 5, iclass 30, count 0 2006.169.08:08:19.17#ibcon#read 5, iclass 30, count 0 2006.169.08:08:19.17#ibcon#about to read 6, iclass 30, count 0 2006.169.08:08:19.17#ibcon#read 6, iclass 30, count 0 2006.169.08:08:19.17#ibcon#end of sib2, iclass 30, count 0 2006.169.08:08:19.17#ibcon#*mode == 0, iclass 30, count 0 2006.169.08:08:19.17#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.169.08:08:19.17#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.08:08:19.17#ibcon#*before write, iclass 30, count 0 2006.169.08:08:19.17#ibcon#enter sib2, iclass 30, count 0 2006.169.08:08:19.17#ibcon#flushed, iclass 30, count 0 2006.169.08:08:19.17#ibcon#about to write, iclass 30, count 0 2006.169.08:08:19.17#ibcon#wrote, iclass 30, count 0 2006.169.08:08:19.17#ibcon#about to read 3, iclass 30, count 0 2006.169.08:08:19.21#ibcon#read 3, iclass 30, count 0 2006.169.08:08:19.21#ibcon#about to read 4, iclass 30, count 0 2006.169.08:08:19.21#ibcon#read 4, iclass 30, count 0 2006.169.08:08:19.21#ibcon#about to read 5, iclass 30, count 0 2006.169.08:08:19.21#ibcon#read 5, iclass 30, count 0 2006.169.08:08:19.21#ibcon#about to read 6, iclass 30, count 0 2006.169.08:08:19.21#ibcon#read 6, iclass 30, count 0 2006.169.08:08:19.21#ibcon#end of sib2, iclass 30, count 0 2006.169.08:08:19.21#ibcon#*after write, iclass 30, count 0 2006.169.08:08:19.21#ibcon#*before return 0, iclass 30, count 0 2006.169.08:08:19.21#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.169.08:08:19.21#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.169.08:08:19.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.169.08:08:19.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.169.08:08:19.21$vc4f8/vb=6,4 2006.169.08:08:19.21#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.169.08:08:19.21#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.169.08:08:19.21#ibcon#ireg 11 cls_cnt 2 2006.169.08:08:19.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.169.08:08:19.27#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.169.08:08:19.27#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.169.08:08:19.27#ibcon#enter wrdev, iclass 32, count 2 2006.169.08:08:19.27#ibcon#first serial, iclass 32, count 2 2006.169.08:08:19.27#ibcon#enter sib2, iclass 32, count 2 2006.169.08:08:19.27#ibcon#flushed, iclass 32, count 2 2006.169.08:08:19.27#ibcon#about to write, iclass 32, count 2 2006.169.08:08:19.27#ibcon#wrote, iclass 32, count 2 2006.169.08:08:19.27#ibcon#about to read 3, iclass 32, count 2 2006.169.08:08:19.29#ibcon#read 3, iclass 32, count 2 2006.169.08:08:19.29#ibcon#about to read 4, iclass 32, count 2 2006.169.08:08:19.29#ibcon#read 4, iclass 32, count 2 2006.169.08:08:19.29#ibcon#about to read 5, iclass 32, count 2 2006.169.08:08:19.29#ibcon#read 5, iclass 32, count 2 2006.169.08:08:19.29#ibcon#about to read 6, iclass 32, count 2 2006.169.08:08:19.29#ibcon#read 6, iclass 32, count 2 2006.169.08:08:19.29#ibcon#end of sib2, iclass 32, count 2 2006.169.08:08:19.29#ibcon#*mode == 0, iclass 32, count 2 2006.169.08:08:19.29#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.169.08:08:19.29#ibcon#[27=AT06-04\r\n] 2006.169.08:08:19.29#ibcon#*before write, iclass 32, count 2 2006.169.08:08:19.29#ibcon#enter sib2, iclass 32, count 2 2006.169.08:08:19.29#ibcon#flushed, iclass 32, count 2 2006.169.08:08:19.29#ibcon#about to write, iclass 32, count 2 2006.169.08:08:19.29#ibcon#wrote, iclass 32, count 2 2006.169.08:08:19.29#ibcon#about to read 3, iclass 32, count 2 2006.169.08:08:19.32#ibcon#read 3, iclass 32, count 2 2006.169.08:08:19.32#ibcon#about to read 4, iclass 32, count 2 2006.169.08:08:19.32#ibcon#read 4, iclass 32, count 2 2006.169.08:08:19.32#ibcon#about to read 5, iclass 32, count 2 2006.169.08:08:19.32#ibcon#read 5, iclass 32, count 2 2006.169.08:08:19.32#ibcon#about to read 6, iclass 32, count 2 2006.169.08:08:19.32#ibcon#read 6, iclass 32, count 2 2006.169.08:08:19.32#ibcon#end of sib2, iclass 32, count 2 2006.169.08:08:19.32#ibcon#*after write, iclass 32, count 2 2006.169.08:08:19.32#ibcon#*before return 0, iclass 32, count 2 2006.169.08:08:19.32#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.169.08:08:19.32#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.169.08:08:19.32#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.169.08:08:19.32#ibcon#ireg 7 cls_cnt 0 2006.169.08:08:19.32#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.169.08:08:19.44#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.169.08:08:19.44#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.169.08:08:19.44#ibcon#enter wrdev, iclass 32, count 0 2006.169.08:08:19.44#ibcon#first serial, iclass 32, count 0 2006.169.08:08:19.44#ibcon#enter sib2, iclass 32, count 0 2006.169.08:08:19.44#ibcon#flushed, iclass 32, count 0 2006.169.08:08:19.44#ibcon#about to write, iclass 32, count 0 2006.169.08:08:19.44#ibcon#wrote, iclass 32, count 0 2006.169.08:08:19.44#ibcon#about to read 3, iclass 32, count 0 2006.169.08:08:19.46#ibcon#read 3, iclass 32, count 0 2006.169.08:08:19.46#ibcon#about to read 4, iclass 32, count 0 2006.169.08:08:19.46#ibcon#read 4, iclass 32, count 0 2006.169.08:08:19.46#ibcon#about to read 5, iclass 32, count 0 2006.169.08:08:19.46#ibcon#read 5, iclass 32, count 0 2006.169.08:08:19.46#ibcon#about to read 6, iclass 32, count 0 2006.169.08:08:19.46#ibcon#read 6, iclass 32, count 0 2006.169.08:08:19.46#ibcon#end of sib2, iclass 32, count 0 2006.169.08:08:19.46#ibcon#*mode == 0, iclass 32, count 0 2006.169.08:08:19.46#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.169.08:08:19.46#ibcon#[27=USB\r\n] 2006.169.08:08:19.46#ibcon#*before write, iclass 32, count 0 2006.169.08:08:19.46#ibcon#enter sib2, iclass 32, count 0 2006.169.08:08:19.46#ibcon#flushed, iclass 32, count 0 2006.169.08:08:19.46#ibcon#about to write, iclass 32, count 0 2006.169.08:08:19.46#ibcon#wrote, iclass 32, count 0 2006.169.08:08:19.46#ibcon#about to read 3, iclass 32, count 0 2006.169.08:08:19.49#ibcon#read 3, iclass 32, count 0 2006.169.08:08:19.49#ibcon#about to read 4, iclass 32, count 0 2006.169.08:08:19.49#ibcon#read 4, iclass 32, count 0 2006.169.08:08:19.49#ibcon#about to read 5, iclass 32, count 0 2006.169.08:08:19.49#ibcon#read 5, iclass 32, count 0 2006.169.08:08:19.49#ibcon#about to read 6, iclass 32, count 0 2006.169.08:08:19.49#ibcon#read 6, iclass 32, count 0 2006.169.08:08:19.49#ibcon#end of sib2, iclass 32, count 0 2006.169.08:08:19.49#ibcon#*after write, iclass 32, count 0 2006.169.08:08:19.49#ibcon#*before return 0, iclass 32, count 0 2006.169.08:08:19.49#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.169.08:08:19.49#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.169.08:08:19.49#ibcon#about to clear, iclass 32 cls_cnt 0 2006.169.08:08:19.49#ibcon#cleared, iclass 32 cls_cnt 0 2006.169.08:08:19.49$vc4f8/vabw=wide 2006.169.08:08:19.49#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.169.08:08:19.49#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.169.08:08:19.49#ibcon#ireg 8 cls_cnt 0 2006.169.08:08:19.49#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:08:19.49#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:08:19.49#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:08:19.49#ibcon#enter wrdev, iclass 34, count 0 2006.169.08:08:19.49#ibcon#first serial, iclass 34, count 0 2006.169.08:08:19.49#ibcon#enter sib2, iclass 34, count 0 2006.169.08:08:19.49#ibcon#flushed, iclass 34, count 0 2006.169.08:08:19.49#ibcon#about to write, iclass 34, count 0 2006.169.08:08:19.49#ibcon#wrote, iclass 34, count 0 2006.169.08:08:19.49#ibcon#about to read 3, iclass 34, count 0 2006.169.08:08:19.51#ibcon#read 3, iclass 34, count 0 2006.169.08:08:19.51#ibcon#about to read 4, iclass 34, count 0 2006.169.08:08:19.51#ibcon#read 4, iclass 34, count 0 2006.169.08:08:19.51#ibcon#about to read 5, iclass 34, count 0 2006.169.08:08:19.51#ibcon#read 5, iclass 34, count 0 2006.169.08:08:19.51#ibcon#about to read 6, iclass 34, count 0 2006.169.08:08:19.51#ibcon#read 6, iclass 34, count 0 2006.169.08:08:19.51#ibcon#end of sib2, iclass 34, count 0 2006.169.08:08:19.51#ibcon#*mode == 0, iclass 34, count 0 2006.169.08:08:19.51#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.169.08:08:19.51#ibcon#[25=BW32\r\n] 2006.169.08:08:19.51#ibcon#*before write, iclass 34, count 0 2006.169.08:08:19.51#ibcon#enter sib2, iclass 34, count 0 2006.169.08:08:19.51#ibcon#flushed, iclass 34, count 0 2006.169.08:08:19.51#ibcon#about to write, iclass 34, count 0 2006.169.08:08:19.51#ibcon#wrote, iclass 34, count 0 2006.169.08:08:19.51#ibcon#about to read 3, iclass 34, count 0 2006.169.08:08:19.54#ibcon#read 3, iclass 34, count 0 2006.169.08:08:19.54#ibcon#about to read 4, iclass 34, count 0 2006.169.08:08:19.54#ibcon#read 4, iclass 34, count 0 2006.169.08:08:19.54#ibcon#about to read 5, iclass 34, count 0 2006.169.08:08:19.54#ibcon#read 5, iclass 34, count 0 2006.169.08:08:19.54#ibcon#about to read 6, iclass 34, count 0 2006.169.08:08:19.54#ibcon#read 6, iclass 34, count 0 2006.169.08:08:19.54#ibcon#end of sib2, iclass 34, count 0 2006.169.08:08:19.54#ibcon#*after write, iclass 34, count 0 2006.169.08:08:19.54#ibcon#*before return 0, iclass 34, count 0 2006.169.08:08:19.54#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:08:19.54#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:08:19.54#ibcon#about to clear, iclass 34 cls_cnt 0 2006.169.08:08:19.54#ibcon#cleared, iclass 34 cls_cnt 0 2006.169.08:08:19.54$vc4f8/vbbw=wide 2006.169.08:08:19.54#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.169.08:08:19.54#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.169.08:08:19.54#ibcon#ireg 8 cls_cnt 0 2006.169.08:08:19.54#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:08:19.61#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:08:19.61#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:08:19.61#ibcon#enter wrdev, iclass 36, count 0 2006.169.08:08:19.61#ibcon#first serial, iclass 36, count 0 2006.169.08:08:19.61#ibcon#enter sib2, iclass 36, count 0 2006.169.08:08:19.61#ibcon#flushed, iclass 36, count 0 2006.169.08:08:19.61#ibcon#about to write, iclass 36, count 0 2006.169.08:08:19.61#ibcon#wrote, iclass 36, count 0 2006.169.08:08:19.61#ibcon#about to read 3, iclass 36, count 0 2006.169.08:08:19.63#ibcon#read 3, iclass 36, count 0 2006.169.08:08:19.63#ibcon#about to read 4, iclass 36, count 0 2006.169.08:08:19.63#ibcon#read 4, iclass 36, count 0 2006.169.08:08:19.63#ibcon#about to read 5, iclass 36, count 0 2006.169.08:08:19.63#ibcon#read 5, iclass 36, count 0 2006.169.08:08:19.63#ibcon#about to read 6, iclass 36, count 0 2006.169.08:08:19.63#ibcon#read 6, iclass 36, count 0 2006.169.08:08:19.63#ibcon#end of sib2, iclass 36, count 0 2006.169.08:08:19.63#ibcon#*mode == 0, iclass 36, count 0 2006.169.08:08:19.63#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.169.08:08:19.63#ibcon#[27=BW32\r\n] 2006.169.08:08:19.63#ibcon#*before write, iclass 36, count 0 2006.169.08:08:19.63#ibcon#enter sib2, iclass 36, count 0 2006.169.08:08:19.63#ibcon#flushed, iclass 36, count 0 2006.169.08:08:19.63#ibcon#about to write, iclass 36, count 0 2006.169.08:08:19.63#ibcon#wrote, iclass 36, count 0 2006.169.08:08:19.63#ibcon#about to read 3, iclass 36, count 0 2006.169.08:08:19.66#ibcon#read 3, iclass 36, count 0 2006.169.08:08:19.66#ibcon#about to read 4, iclass 36, count 0 2006.169.08:08:19.66#ibcon#read 4, iclass 36, count 0 2006.169.08:08:19.66#ibcon#about to read 5, iclass 36, count 0 2006.169.08:08:19.66#ibcon#read 5, iclass 36, count 0 2006.169.08:08:19.66#ibcon#about to read 6, iclass 36, count 0 2006.169.08:08:19.66#ibcon#read 6, iclass 36, count 0 2006.169.08:08:19.66#ibcon#end of sib2, iclass 36, count 0 2006.169.08:08:19.66#ibcon#*after write, iclass 36, count 0 2006.169.08:08:19.66#ibcon#*before return 0, iclass 36, count 0 2006.169.08:08:19.66#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:08:19.66#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:08:19.66#ibcon#about to clear, iclass 36 cls_cnt 0 2006.169.08:08:19.66#ibcon#cleared, iclass 36 cls_cnt 0 2006.169.08:08:19.66$4f8m12a/ifd4f 2006.169.08:08:19.66$ifd4f/lo= 2006.169.08:08:19.66$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.08:08:19.66$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.08:08:19.66$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.08:08:19.66$ifd4f/patch= 2006.169.08:08:19.66$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.08:08:19.66$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.08:08:19.66$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.08:08:19.66$4f8m12a/"form=m,16.000,1:2 2006.169.08:08:19.66$4f8m12a/"tpicd 2006.169.08:08:19.66$4f8m12a/echo=off 2006.169.08:08:19.66$4f8m12a/xlog=off 2006.169.08:08:19.66:!2006.169.08:08:30 2006.169.08:08:30.00:preob 2006.169.08:08:31.14/onsource/TRACKING 2006.169.08:08:31.14:!2006.169.08:08:40 2006.169.08:08:40.00:data_valid=on 2006.169.08:08:40.00:midob 2006.169.08:08:40.14/onsource/TRACKING 2006.169.08:08:40.14/wx/18.13,1003.8,100 2006.169.08:08:40.21/cable/+6.5295E-03 2006.169.08:08:41.30/va/01,08,usb,yes,44,46 2006.169.08:08:41.30/va/02,07,usb,yes,44,46 2006.169.08:08:41.30/va/03,06,usb,yes,47,47 2006.169.08:08:41.30/va/04,07,usb,yes,45,49 2006.169.08:08:41.30/va/05,07,usb,yes,50,53 2006.169.08:08:41.30/va/06,06,usb,yes,49,49 2006.169.08:08:41.30/va/07,06,usb,yes,50,49 2006.169.08:08:41.30/va/08,07,usb,yes,47,46 2006.169.08:08:41.53/valo/01,532.99,yes,locked 2006.169.08:08:41.53/valo/02,572.99,yes,locked 2006.169.08:08:41.53/valo/03,672.99,yes,locked 2006.169.08:08:41.53/valo/04,832.99,yes,locked 2006.169.08:08:41.53/valo/05,652.99,yes,locked 2006.169.08:08:41.53/valo/06,772.99,yes,locked 2006.169.08:08:41.53/valo/07,832.99,yes,locked 2006.169.08:08:41.53/valo/08,852.99,yes,locked 2006.169.08:08:42.62/vb/01,04,usb,yes,30,29 2006.169.08:08:42.62/vb/02,04,usb,yes,32,34 2006.169.08:08:42.62/vb/03,04,usb,yes,29,32 2006.169.08:08:42.62/vb/04,04,usb,yes,29,30 2006.169.08:08:42.62/vb/05,04,usb,yes,28,32 2006.169.08:08:42.62/vb/06,04,usb,yes,29,32 2006.169.08:08:42.62/vb/07,04,usb,yes,31,31 2006.169.08:08:42.62/vb/08,04,usb,yes,29,32 2006.169.08:08:42.86/vblo/01,632.99,yes,locked 2006.169.08:08:42.86/vblo/02,640.99,yes,locked 2006.169.08:08:42.86/vblo/03,656.99,yes,locked 2006.169.08:08:42.86/vblo/04,712.99,yes,locked 2006.169.08:08:42.86/vblo/05,744.99,yes,locked 2006.169.08:08:42.86/vblo/06,752.99,yes,locked 2006.169.08:08:42.86/vblo/07,734.99,yes,locked 2006.169.08:08:42.86/vblo/08,744.99,yes,locked 2006.169.08:08:43.01/vabw/8 2006.169.08:08:43.16/vbbw/8 2006.169.08:08:43.25/xfe/off,on,15.2 2006.169.08:08:43.65/ifatt/23,28,28,28 2006.169.08:08:44.08/fmout-gps/S +4.19E-07 2006.169.08:08:44.16:!2006.169.08:09:40 2006.169.08:09:40.00:data_valid=off 2006.169.08:09:40.00:postob 2006.169.08:09:40.17/cable/+6.5297E-03 2006.169.08:09:40.17/wx/18.13,1003.8,100 2006.169.08:09:41.08/fmout-gps/S +4.18E-07 2006.169.08:09:41.08:scan_name=169-0810,k06169,60 2006.169.08:09:41.08:source=0743+259,074625.87,254902.1,2000.0,ccw 2006.169.08:09:41.15#flagr#flagr/antenna,new-source 2006.169.08:09:42.14:checkk5 2006.169.08:09:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.169.08:09:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.169.08:09:46.91/chk_autoobs//k5ts3?ERROR: timeout happened! 2006.169.08:09:47.29/chk_autoobs//k5ts4/ autoobs is running! 2006.169.08:09:47.66/chk_obsdata//k5ts1/T1690808??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.08:09:48.02/chk_obsdata//k5ts2/T1690808??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.08:09:55.09/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.08:09:55.46/chk_obsdata//k5ts4/T1690808??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.08:09:56.15/k5log//k5ts1_log_newline 2006.169.08:09:56.85/k5log//k5ts2_log_newline 2006.169.08:10:01.14#trakl#Source acquired 2006.169.08:10:02.14#flagr#flagr/antenna,acquired 2006.169.08:10:03.95/k5log//k5ts3?ERROR: timeout happened! 2006.169.08:10:04.64/k5log//k5ts4_log_newline 2006.169.08:10:04.80/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.08:10:04.80:4f8m12a=2 2006.169.08:10:04.80$4f8m12a/echo=on 2006.169.08:10:04.80$4f8m12a/pcalon 2006.169.08:10:04.80$pcalon/"no phase cal control is implemented here 2006.169.08:10:04.80$4f8m12a/"tpicd=stop 2006.169.08:10:04.80$4f8m12a/vc4f8 2006.169.08:10:04.80$vc4f8/valo=1,532.99 2006.169.08:10:04.81#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.169.08:10:04.81#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.169.08:10:04.81#ibcon#ireg 17 cls_cnt 0 2006.169.08:10:04.81#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:10:04.81#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:10:04.81#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:10:04.81#ibcon#enter wrdev, iclass 5, count 0 2006.169.08:10:04.81#ibcon#first serial, iclass 5, count 0 2006.169.08:10:04.81#ibcon#enter sib2, iclass 5, count 0 2006.169.08:10:04.81#ibcon#flushed, iclass 5, count 0 2006.169.08:10:04.81#ibcon#about to write, iclass 5, count 0 2006.169.08:10:04.81#ibcon#wrote, iclass 5, count 0 2006.169.08:10:04.81#ibcon#about to read 3, iclass 5, count 0 2006.169.08:10:04.83#ibcon#read 3, iclass 5, count 0 2006.169.08:10:04.83#ibcon#about to read 4, iclass 5, count 0 2006.169.08:10:04.83#ibcon#read 4, iclass 5, count 0 2006.169.08:10:04.83#ibcon#about to read 5, iclass 5, count 0 2006.169.08:10:04.83#ibcon#read 5, iclass 5, count 0 2006.169.08:10:04.83#ibcon#about to read 6, iclass 5, count 0 2006.169.08:10:04.83#ibcon#read 6, iclass 5, count 0 2006.169.08:10:04.83#ibcon#end of sib2, iclass 5, count 0 2006.169.08:10:04.83#ibcon#*mode == 0, iclass 5, count 0 2006.169.08:10:04.83#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.169.08:10:04.83#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.08:10:04.83#ibcon#*before write, iclass 5, count 0 2006.169.08:10:04.83#ibcon#enter sib2, iclass 5, count 0 2006.169.08:10:04.83#ibcon#flushed, iclass 5, count 0 2006.169.08:10:04.83#ibcon#about to write, iclass 5, count 0 2006.169.08:10:04.83#ibcon#wrote, iclass 5, count 0 2006.169.08:10:04.83#ibcon#about to read 3, iclass 5, count 0 2006.169.08:10:04.88#ibcon#read 3, iclass 5, count 0 2006.169.08:10:04.88#ibcon#about to read 4, iclass 5, count 0 2006.169.08:10:04.88#ibcon#read 4, iclass 5, count 0 2006.169.08:10:04.88#ibcon#about to read 5, iclass 5, count 0 2006.169.08:10:04.88#ibcon#read 5, iclass 5, count 0 2006.169.08:10:04.88#ibcon#about to read 6, iclass 5, count 0 2006.169.08:10:04.88#ibcon#read 6, iclass 5, count 0 2006.169.08:10:04.88#ibcon#end of sib2, iclass 5, count 0 2006.169.08:10:04.88#ibcon#*after write, iclass 5, count 0 2006.169.08:10:04.88#ibcon#*before return 0, iclass 5, count 0 2006.169.08:10:04.88#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:10:04.88#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:10:04.88#ibcon#about to clear, iclass 5 cls_cnt 0 2006.169.08:10:04.88#ibcon#cleared, iclass 5 cls_cnt 0 2006.169.08:10:04.88$vc4f8/va=1,8 2006.169.08:10:04.88#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.169.08:10:04.88#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.169.08:10:04.88#ibcon#ireg 11 cls_cnt 2 2006.169.08:10:04.88#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:10:04.88#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:10:04.88#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:10:04.88#ibcon#enter wrdev, iclass 7, count 2 2006.169.08:10:04.88#ibcon#first serial, iclass 7, count 2 2006.169.08:10:04.88#ibcon#enter sib2, iclass 7, count 2 2006.169.08:10:04.88#ibcon#flushed, iclass 7, count 2 2006.169.08:10:04.88#ibcon#about to write, iclass 7, count 2 2006.169.08:10:04.88#ibcon#wrote, iclass 7, count 2 2006.169.08:10:04.88#ibcon#about to read 3, iclass 7, count 2 2006.169.08:10:04.90#ibcon#read 3, iclass 7, count 2 2006.169.08:10:04.90#ibcon#about to read 4, iclass 7, count 2 2006.169.08:10:04.90#ibcon#read 4, iclass 7, count 2 2006.169.08:10:04.90#ibcon#about to read 5, iclass 7, count 2 2006.169.08:10:04.90#ibcon#read 5, iclass 7, count 2 2006.169.08:10:04.90#ibcon#about to read 6, iclass 7, count 2 2006.169.08:10:04.90#ibcon#read 6, iclass 7, count 2 2006.169.08:10:04.90#ibcon#end of sib2, iclass 7, count 2 2006.169.08:10:04.90#ibcon#*mode == 0, iclass 7, count 2 2006.169.08:10:04.90#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.169.08:10:04.90#ibcon#[25=AT01-08\r\n] 2006.169.08:10:04.90#ibcon#*before write, iclass 7, count 2 2006.169.08:10:04.90#ibcon#enter sib2, iclass 7, count 2 2006.169.08:10:04.90#ibcon#flushed, iclass 7, count 2 2006.169.08:10:04.90#ibcon#about to write, iclass 7, count 2 2006.169.08:10:04.90#ibcon#wrote, iclass 7, count 2 2006.169.08:10:04.90#ibcon#about to read 3, iclass 7, count 2 2006.169.08:10:04.93#ibcon#read 3, iclass 7, count 2 2006.169.08:10:04.93#ibcon#about to read 4, iclass 7, count 2 2006.169.08:10:04.93#ibcon#read 4, iclass 7, count 2 2006.169.08:10:04.93#ibcon#about to read 5, iclass 7, count 2 2006.169.08:10:04.93#ibcon#read 5, iclass 7, count 2 2006.169.08:10:04.93#ibcon#about to read 6, iclass 7, count 2 2006.169.08:10:04.93#ibcon#read 6, iclass 7, count 2 2006.169.08:10:04.93#ibcon#end of sib2, iclass 7, count 2 2006.169.08:10:04.93#ibcon#*after write, iclass 7, count 2 2006.169.08:10:04.93#ibcon#*before return 0, iclass 7, count 2 2006.169.08:10:04.93#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:10:04.93#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:10:04.93#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.169.08:10:04.93#ibcon#ireg 7 cls_cnt 0 2006.169.08:10:04.93#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:10:05.06#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:10:05.06#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:10:05.06#ibcon#enter wrdev, iclass 7, count 0 2006.169.08:10:05.06#ibcon#first serial, iclass 7, count 0 2006.169.08:10:05.06#ibcon#enter sib2, iclass 7, count 0 2006.169.08:10:05.06#ibcon#flushed, iclass 7, count 0 2006.169.08:10:05.06#ibcon#about to write, iclass 7, count 0 2006.169.08:10:05.06#ibcon#wrote, iclass 7, count 0 2006.169.08:10:05.06#ibcon#about to read 3, iclass 7, count 0 2006.169.08:10:05.08#ibcon#read 3, iclass 7, count 0 2006.169.08:10:05.08#ibcon#about to read 4, iclass 7, count 0 2006.169.08:10:05.08#ibcon#read 4, iclass 7, count 0 2006.169.08:10:05.08#ibcon#about to read 5, iclass 7, count 0 2006.169.08:10:05.08#ibcon#read 5, iclass 7, count 0 2006.169.08:10:05.08#ibcon#about to read 6, iclass 7, count 0 2006.169.08:10:05.08#ibcon#read 6, iclass 7, count 0 2006.169.08:10:05.08#ibcon#end of sib2, iclass 7, count 0 2006.169.08:10:05.08#ibcon#*mode == 0, iclass 7, count 0 2006.169.08:10:05.08#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.169.08:10:05.08#ibcon#[25=USB\r\n] 2006.169.08:10:05.08#ibcon#*before write, iclass 7, count 0 2006.169.08:10:05.08#ibcon#enter sib2, iclass 7, count 0 2006.169.08:10:05.08#ibcon#flushed, iclass 7, count 0 2006.169.08:10:05.08#ibcon#about to write, iclass 7, count 0 2006.169.08:10:05.08#ibcon#wrote, iclass 7, count 0 2006.169.08:10:05.08#ibcon#about to read 3, iclass 7, count 0 2006.169.08:10:05.11#ibcon#read 3, iclass 7, count 0 2006.169.08:10:05.11#ibcon#about to read 4, iclass 7, count 0 2006.169.08:10:05.11#ibcon#read 4, iclass 7, count 0 2006.169.08:10:05.11#ibcon#about to read 5, iclass 7, count 0 2006.169.08:10:05.11#ibcon#read 5, iclass 7, count 0 2006.169.08:10:05.11#ibcon#about to read 6, iclass 7, count 0 2006.169.08:10:05.11#ibcon#read 6, iclass 7, count 0 2006.169.08:10:05.11#ibcon#end of sib2, iclass 7, count 0 2006.169.08:10:05.11#ibcon#*after write, iclass 7, count 0 2006.169.08:10:05.11#ibcon#*before return 0, iclass 7, count 0 2006.169.08:10:05.11#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:10:05.11#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:10:05.11#ibcon#about to clear, iclass 7 cls_cnt 0 2006.169.08:10:05.11#ibcon#cleared, iclass 7 cls_cnt 0 2006.169.08:10:05.11$vc4f8/valo=2,572.99 2006.169.08:10:05.11#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.169.08:10:05.11#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.169.08:10:05.11#ibcon#ireg 17 cls_cnt 0 2006.169.08:10:05.11#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:10:05.11#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:10:05.11#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:10:05.11#ibcon#enter wrdev, iclass 11, count 0 2006.169.08:10:05.11#ibcon#first serial, iclass 11, count 0 2006.169.08:10:05.11#ibcon#enter sib2, iclass 11, count 0 2006.169.08:10:05.11#ibcon#flushed, iclass 11, count 0 2006.169.08:10:05.11#ibcon#about to write, iclass 11, count 0 2006.169.08:10:05.11#ibcon#wrote, iclass 11, count 0 2006.169.08:10:05.11#ibcon#about to read 3, iclass 11, count 0 2006.169.08:10:05.13#ibcon#read 3, iclass 11, count 0 2006.169.08:10:05.13#ibcon#about to read 4, iclass 11, count 0 2006.169.08:10:05.13#ibcon#read 4, iclass 11, count 0 2006.169.08:10:05.13#ibcon#about to read 5, iclass 11, count 0 2006.169.08:10:05.13#ibcon#read 5, iclass 11, count 0 2006.169.08:10:05.13#ibcon#about to read 6, iclass 11, count 0 2006.169.08:10:05.13#ibcon#read 6, iclass 11, count 0 2006.169.08:10:05.13#ibcon#end of sib2, iclass 11, count 0 2006.169.08:10:05.13#ibcon#*mode == 0, iclass 11, count 0 2006.169.08:10:05.13#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.169.08:10:05.13#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.08:10:05.13#ibcon#*before write, iclass 11, count 0 2006.169.08:10:05.13#ibcon#enter sib2, iclass 11, count 0 2006.169.08:10:05.13#ibcon#flushed, iclass 11, count 0 2006.169.08:10:05.13#ibcon#about to write, iclass 11, count 0 2006.169.08:10:05.13#ibcon#wrote, iclass 11, count 0 2006.169.08:10:05.13#ibcon#about to read 3, iclass 11, count 0 2006.169.08:10:05.17#ibcon#read 3, iclass 11, count 0 2006.169.08:10:05.17#ibcon#about to read 4, iclass 11, count 0 2006.169.08:10:05.17#ibcon#read 4, iclass 11, count 0 2006.169.08:10:05.17#ibcon#about to read 5, iclass 11, count 0 2006.169.08:10:05.17#ibcon#read 5, iclass 11, count 0 2006.169.08:10:05.17#ibcon#about to read 6, iclass 11, count 0 2006.169.08:10:05.17#ibcon#read 6, iclass 11, count 0 2006.169.08:10:05.17#ibcon#end of sib2, iclass 11, count 0 2006.169.08:10:05.17#ibcon#*after write, iclass 11, count 0 2006.169.08:10:05.17#ibcon#*before return 0, iclass 11, count 0 2006.169.08:10:05.17#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:10:05.17#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:10:05.17#ibcon#about to clear, iclass 11 cls_cnt 0 2006.169.08:10:05.17#ibcon#cleared, iclass 11 cls_cnt 0 2006.169.08:10:05.17$vc4f8/va=2,7 2006.169.08:10:05.17#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.169.08:10:05.17#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.169.08:10:05.17#ibcon#ireg 11 cls_cnt 2 2006.169.08:10:05.17#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:10:05.23#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:10:05.23#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:10:05.23#ibcon#enter wrdev, iclass 13, count 2 2006.169.08:10:05.23#ibcon#first serial, iclass 13, count 2 2006.169.08:10:05.23#ibcon#enter sib2, iclass 13, count 2 2006.169.08:10:05.23#ibcon#flushed, iclass 13, count 2 2006.169.08:10:05.23#ibcon#about to write, iclass 13, count 2 2006.169.08:10:05.23#ibcon#wrote, iclass 13, count 2 2006.169.08:10:05.23#ibcon#about to read 3, iclass 13, count 2 2006.169.08:10:05.25#ibcon#read 3, iclass 13, count 2 2006.169.08:10:05.25#ibcon#about to read 4, iclass 13, count 2 2006.169.08:10:05.25#ibcon#read 4, iclass 13, count 2 2006.169.08:10:05.25#ibcon#about to read 5, iclass 13, count 2 2006.169.08:10:05.25#ibcon#read 5, iclass 13, count 2 2006.169.08:10:05.25#ibcon#about to read 6, iclass 13, count 2 2006.169.08:10:05.25#ibcon#read 6, iclass 13, count 2 2006.169.08:10:05.25#ibcon#end of sib2, iclass 13, count 2 2006.169.08:10:05.25#ibcon#*mode == 0, iclass 13, count 2 2006.169.08:10:05.25#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.169.08:10:05.25#ibcon#[25=AT02-07\r\n] 2006.169.08:10:05.25#ibcon#*before write, iclass 13, count 2 2006.169.08:10:05.25#ibcon#enter sib2, iclass 13, count 2 2006.169.08:10:05.25#ibcon#flushed, iclass 13, count 2 2006.169.08:10:05.25#ibcon#about to write, iclass 13, count 2 2006.169.08:10:05.25#ibcon#wrote, iclass 13, count 2 2006.169.08:10:05.25#ibcon#about to read 3, iclass 13, count 2 2006.169.08:10:05.29#ibcon#read 3, iclass 13, count 2 2006.169.08:10:05.29#ibcon#about to read 4, iclass 13, count 2 2006.169.08:10:05.29#ibcon#read 4, iclass 13, count 2 2006.169.08:10:05.29#ibcon#about to read 5, iclass 13, count 2 2006.169.08:10:05.29#ibcon#read 5, iclass 13, count 2 2006.169.08:10:05.29#ibcon#about to read 6, iclass 13, count 2 2006.169.08:10:05.29#ibcon#read 6, iclass 13, count 2 2006.169.08:10:05.29#ibcon#end of sib2, iclass 13, count 2 2006.169.08:10:05.29#ibcon#*after write, iclass 13, count 2 2006.169.08:10:05.29#ibcon#*before return 0, iclass 13, count 2 2006.169.08:10:05.29#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:10:05.29#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:10:05.29#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.169.08:10:05.29#ibcon#ireg 7 cls_cnt 0 2006.169.08:10:05.29#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:10:05.41#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:10:05.41#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:10:05.41#ibcon#enter wrdev, iclass 13, count 0 2006.169.08:10:05.41#ibcon#first serial, iclass 13, count 0 2006.169.08:10:05.41#ibcon#enter sib2, iclass 13, count 0 2006.169.08:10:05.41#ibcon#flushed, iclass 13, count 0 2006.169.08:10:05.41#ibcon#about to write, iclass 13, count 0 2006.169.08:10:05.41#ibcon#wrote, iclass 13, count 0 2006.169.08:10:05.41#ibcon#about to read 3, iclass 13, count 0 2006.169.08:10:05.43#ibcon#read 3, iclass 13, count 0 2006.169.08:10:05.43#ibcon#about to read 4, iclass 13, count 0 2006.169.08:10:05.43#ibcon#read 4, iclass 13, count 0 2006.169.08:10:05.43#ibcon#about to read 5, iclass 13, count 0 2006.169.08:10:05.43#ibcon#read 5, iclass 13, count 0 2006.169.08:10:05.43#ibcon#about to read 6, iclass 13, count 0 2006.169.08:10:05.43#ibcon#read 6, iclass 13, count 0 2006.169.08:10:05.43#ibcon#end of sib2, iclass 13, count 0 2006.169.08:10:05.43#ibcon#*mode == 0, iclass 13, count 0 2006.169.08:10:05.43#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.08:10:05.43#ibcon#[25=USB\r\n] 2006.169.08:10:05.43#ibcon#*before write, iclass 13, count 0 2006.169.08:10:05.43#ibcon#enter sib2, iclass 13, count 0 2006.169.08:10:05.43#ibcon#flushed, iclass 13, count 0 2006.169.08:10:05.43#ibcon#about to write, iclass 13, count 0 2006.169.08:10:05.43#ibcon#wrote, iclass 13, count 0 2006.169.08:10:05.43#ibcon#about to read 3, iclass 13, count 0 2006.169.08:10:05.46#ibcon#read 3, iclass 13, count 0 2006.169.08:10:05.46#ibcon#about to read 4, iclass 13, count 0 2006.169.08:10:05.46#ibcon#read 4, iclass 13, count 0 2006.169.08:10:05.46#ibcon#about to read 5, iclass 13, count 0 2006.169.08:10:05.46#ibcon#read 5, iclass 13, count 0 2006.169.08:10:05.46#ibcon#about to read 6, iclass 13, count 0 2006.169.08:10:05.46#ibcon#read 6, iclass 13, count 0 2006.169.08:10:05.46#ibcon#end of sib2, iclass 13, count 0 2006.169.08:10:05.46#ibcon#*after write, iclass 13, count 0 2006.169.08:10:05.46#ibcon#*before return 0, iclass 13, count 0 2006.169.08:10:05.46#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:10:05.46#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:10:05.46#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.08:10:05.46#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.08:10:05.46$vc4f8/valo=3,672.99 2006.169.08:10:05.46#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.169.08:10:05.46#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.169.08:10:05.46#ibcon#ireg 17 cls_cnt 0 2006.169.08:10:05.46#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:10:05.46#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:10:05.46#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:10:05.46#ibcon#enter wrdev, iclass 15, count 0 2006.169.08:10:05.46#ibcon#first serial, iclass 15, count 0 2006.169.08:10:05.46#ibcon#enter sib2, iclass 15, count 0 2006.169.08:10:05.46#ibcon#flushed, iclass 15, count 0 2006.169.08:10:05.46#ibcon#about to write, iclass 15, count 0 2006.169.08:10:05.46#ibcon#wrote, iclass 15, count 0 2006.169.08:10:05.46#ibcon#about to read 3, iclass 15, count 0 2006.169.08:10:05.48#ibcon#read 3, iclass 15, count 0 2006.169.08:10:05.48#ibcon#about to read 4, iclass 15, count 0 2006.169.08:10:05.48#ibcon#read 4, iclass 15, count 0 2006.169.08:10:05.48#ibcon#about to read 5, iclass 15, count 0 2006.169.08:10:05.48#ibcon#read 5, iclass 15, count 0 2006.169.08:10:05.48#ibcon#about to read 6, iclass 15, count 0 2006.169.08:10:05.48#ibcon#read 6, iclass 15, count 0 2006.169.08:10:05.48#ibcon#end of sib2, iclass 15, count 0 2006.169.08:10:05.48#ibcon#*mode == 0, iclass 15, count 0 2006.169.08:10:05.48#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.169.08:10:05.48#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.08:10:05.48#ibcon#*before write, iclass 15, count 0 2006.169.08:10:05.48#ibcon#enter sib2, iclass 15, count 0 2006.169.08:10:05.48#ibcon#flushed, iclass 15, count 0 2006.169.08:10:05.48#ibcon#about to write, iclass 15, count 0 2006.169.08:10:05.48#ibcon#wrote, iclass 15, count 0 2006.169.08:10:05.48#ibcon#about to read 3, iclass 15, count 0 2006.169.08:10:05.52#ibcon#read 3, iclass 15, count 0 2006.169.08:10:05.52#ibcon#about to read 4, iclass 15, count 0 2006.169.08:10:05.52#ibcon#read 4, iclass 15, count 0 2006.169.08:10:05.52#ibcon#about to read 5, iclass 15, count 0 2006.169.08:10:05.52#ibcon#read 5, iclass 15, count 0 2006.169.08:10:05.52#ibcon#about to read 6, iclass 15, count 0 2006.169.08:10:05.52#ibcon#read 6, iclass 15, count 0 2006.169.08:10:05.52#ibcon#end of sib2, iclass 15, count 0 2006.169.08:10:05.52#ibcon#*after write, iclass 15, count 0 2006.169.08:10:05.52#ibcon#*before return 0, iclass 15, count 0 2006.169.08:10:05.52#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:10:05.52#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:10:05.52#ibcon#about to clear, iclass 15 cls_cnt 0 2006.169.08:10:05.52#ibcon#cleared, iclass 15 cls_cnt 0 2006.169.08:10:05.52$vc4f8/va=3,6 2006.169.08:10:05.52#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.169.08:10:05.52#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.169.08:10:05.52#ibcon#ireg 11 cls_cnt 2 2006.169.08:10:05.52#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:10:05.58#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:10:05.58#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:10:05.58#ibcon#enter wrdev, iclass 17, count 2 2006.169.08:10:05.58#ibcon#first serial, iclass 17, count 2 2006.169.08:10:05.58#ibcon#enter sib2, iclass 17, count 2 2006.169.08:10:05.58#ibcon#flushed, iclass 17, count 2 2006.169.08:10:05.58#ibcon#about to write, iclass 17, count 2 2006.169.08:10:05.58#ibcon#wrote, iclass 17, count 2 2006.169.08:10:05.58#ibcon#about to read 3, iclass 17, count 2 2006.169.08:10:05.60#ibcon#read 3, iclass 17, count 2 2006.169.08:10:05.60#ibcon#about to read 4, iclass 17, count 2 2006.169.08:10:05.60#ibcon#read 4, iclass 17, count 2 2006.169.08:10:05.60#ibcon#about to read 5, iclass 17, count 2 2006.169.08:10:05.60#ibcon#read 5, iclass 17, count 2 2006.169.08:10:05.60#ibcon#about to read 6, iclass 17, count 2 2006.169.08:10:05.60#ibcon#read 6, iclass 17, count 2 2006.169.08:10:05.60#ibcon#end of sib2, iclass 17, count 2 2006.169.08:10:05.60#ibcon#*mode == 0, iclass 17, count 2 2006.169.08:10:05.60#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.169.08:10:05.60#ibcon#[25=AT03-06\r\n] 2006.169.08:10:05.60#ibcon#*before write, iclass 17, count 2 2006.169.08:10:05.60#ibcon#enter sib2, iclass 17, count 2 2006.169.08:10:05.60#ibcon#flushed, iclass 17, count 2 2006.169.08:10:05.60#ibcon#about to write, iclass 17, count 2 2006.169.08:10:05.60#ibcon#wrote, iclass 17, count 2 2006.169.08:10:05.60#ibcon#about to read 3, iclass 17, count 2 2006.169.08:10:05.63#ibcon#read 3, iclass 17, count 2 2006.169.08:10:05.63#ibcon#about to read 4, iclass 17, count 2 2006.169.08:10:05.63#ibcon#read 4, iclass 17, count 2 2006.169.08:10:05.63#ibcon#about to read 5, iclass 17, count 2 2006.169.08:10:05.63#ibcon#read 5, iclass 17, count 2 2006.169.08:10:05.63#ibcon#about to read 6, iclass 17, count 2 2006.169.08:10:05.63#ibcon#read 6, iclass 17, count 2 2006.169.08:10:05.63#ibcon#end of sib2, iclass 17, count 2 2006.169.08:10:05.63#ibcon#*after write, iclass 17, count 2 2006.169.08:10:05.63#ibcon#*before return 0, iclass 17, count 2 2006.169.08:10:05.63#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:10:05.63#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:10:05.63#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.169.08:10:05.63#ibcon#ireg 7 cls_cnt 0 2006.169.08:10:05.63#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:10:05.75#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:10:05.75#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:10:05.75#ibcon#enter wrdev, iclass 17, count 0 2006.169.08:10:05.75#ibcon#first serial, iclass 17, count 0 2006.169.08:10:05.75#ibcon#enter sib2, iclass 17, count 0 2006.169.08:10:05.75#ibcon#flushed, iclass 17, count 0 2006.169.08:10:05.75#ibcon#about to write, iclass 17, count 0 2006.169.08:10:05.75#ibcon#wrote, iclass 17, count 0 2006.169.08:10:05.75#ibcon#about to read 3, iclass 17, count 0 2006.169.08:10:05.77#ibcon#read 3, iclass 17, count 0 2006.169.08:10:05.77#ibcon#about to read 4, iclass 17, count 0 2006.169.08:10:05.77#ibcon#read 4, iclass 17, count 0 2006.169.08:10:05.77#ibcon#about to read 5, iclass 17, count 0 2006.169.08:10:05.77#ibcon#read 5, iclass 17, count 0 2006.169.08:10:05.77#ibcon#about to read 6, iclass 17, count 0 2006.169.08:10:05.77#ibcon#read 6, iclass 17, count 0 2006.169.08:10:05.77#ibcon#end of sib2, iclass 17, count 0 2006.169.08:10:05.77#ibcon#*mode == 0, iclass 17, count 0 2006.169.08:10:05.77#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.169.08:10:05.77#ibcon#[25=USB\r\n] 2006.169.08:10:05.77#ibcon#*before write, iclass 17, count 0 2006.169.08:10:05.77#ibcon#enter sib2, iclass 17, count 0 2006.169.08:10:05.77#ibcon#flushed, iclass 17, count 0 2006.169.08:10:05.77#ibcon#about to write, iclass 17, count 0 2006.169.08:10:05.77#ibcon#wrote, iclass 17, count 0 2006.169.08:10:05.77#ibcon#about to read 3, iclass 17, count 0 2006.169.08:10:05.80#ibcon#read 3, iclass 17, count 0 2006.169.08:10:05.80#ibcon#about to read 4, iclass 17, count 0 2006.169.08:10:05.80#ibcon#read 4, iclass 17, count 0 2006.169.08:10:05.80#ibcon#about to read 5, iclass 17, count 0 2006.169.08:10:05.80#ibcon#read 5, iclass 17, count 0 2006.169.08:10:05.80#ibcon#about to read 6, iclass 17, count 0 2006.169.08:10:05.80#ibcon#read 6, iclass 17, count 0 2006.169.08:10:05.80#ibcon#end of sib2, iclass 17, count 0 2006.169.08:10:05.80#ibcon#*after write, iclass 17, count 0 2006.169.08:10:05.80#ibcon#*before return 0, iclass 17, count 0 2006.169.08:10:05.80#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:10:05.80#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:10:05.80#ibcon#about to clear, iclass 17 cls_cnt 0 2006.169.08:10:05.80#ibcon#cleared, iclass 17 cls_cnt 0 2006.169.08:10:05.80$vc4f8/valo=4,832.99 2006.169.08:10:05.80#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.169.08:10:05.80#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.169.08:10:05.80#ibcon#ireg 17 cls_cnt 0 2006.169.08:10:05.80#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.169.08:10:05.80#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.169.08:10:05.80#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.169.08:10:05.80#ibcon#enter wrdev, iclass 19, count 0 2006.169.08:10:05.80#ibcon#first serial, iclass 19, count 0 2006.169.08:10:05.80#ibcon#enter sib2, iclass 19, count 0 2006.169.08:10:05.80#ibcon#flushed, iclass 19, count 0 2006.169.08:10:05.80#ibcon#about to write, iclass 19, count 0 2006.169.08:10:05.80#ibcon#wrote, iclass 19, count 0 2006.169.08:10:05.80#ibcon#about to read 3, iclass 19, count 0 2006.169.08:10:05.82#ibcon#read 3, iclass 19, count 0 2006.169.08:10:05.82#ibcon#about to read 4, iclass 19, count 0 2006.169.08:10:05.82#ibcon#read 4, iclass 19, count 0 2006.169.08:10:05.82#ibcon#about to read 5, iclass 19, count 0 2006.169.08:10:05.82#ibcon#read 5, iclass 19, count 0 2006.169.08:10:05.82#ibcon#about to read 6, iclass 19, count 0 2006.169.08:10:05.82#ibcon#read 6, iclass 19, count 0 2006.169.08:10:05.82#ibcon#end of sib2, iclass 19, count 0 2006.169.08:10:05.82#ibcon#*mode == 0, iclass 19, count 0 2006.169.08:10:05.82#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.169.08:10:05.82#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.08:10:05.82#ibcon#*before write, iclass 19, count 0 2006.169.08:10:05.82#ibcon#enter sib2, iclass 19, count 0 2006.169.08:10:05.82#ibcon#flushed, iclass 19, count 0 2006.169.08:10:05.82#ibcon#about to write, iclass 19, count 0 2006.169.08:10:05.82#ibcon#wrote, iclass 19, count 0 2006.169.08:10:05.82#ibcon#about to read 3, iclass 19, count 0 2006.169.08:10:05.86#ibcon#read 3, iclass 19, count 0 2006.169.08:10:05.86#ibcon#about to read 4, iclass 19, count 0 2006.169.08:10:05.86#ibcon#read 4, iclass 19, count 0 2006.169.08:10:05.86#ibcon#about to read 5, iclass 19, count 0 2006.169.08:10:05.86#ibcon#read 5, iclass 19, count 0 2006.169.08:10:05.86#ibcon#about to read 6, iclass 19, count 0 2006.169.08:10:05.86#ibcon#read 6, iclass 19, count 0 2006.169.08:10:05.86#ibcon#end of sib2, iclass 19, count 0 2006.169.08:10:05.86#ibcon#*after write, iclass 19, count 0 2006.169.08:10:05.86#ibcon#*before return 0, iclass 19, count 0 2006.169.08:10:05.86#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.169.08:10:05.86#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.169.08:10:05.86#ibcon#about to clear, iclass 19 cls_cnt 0 2006.169.08:10:05.86#ibcon#cleared, iclass 19 cls_cnt 0 2006.169.08:10:05.86$vc4f8/va=4,7 2006.169.08:10:05.86#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.169.08:10:05.86#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.169.08:10:05.86#ibcon#ireg 11 cls_cnt 2 2006.169.08:10:05.86#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.169.08:10:05.92#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.169.08:10:05.92#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.169.08:10:05.92#ibcon#enter wrdev, iclass 21, count 2 2006.169.08:10:05.92#ibcon#first serial, iclass 21, count 2 2006.169.08:10:05.92#ibcon#enter sib2, iclass 21, count 2 2006.169.08:10:05.92#ibcon#flushed, iclass 21, count 2 2006.169.08:10:05.92#ibcon#about to write, iclass 21, count 2 2006.169.08:10:05.92#ibcon#wrote, iclass 21, count 2 2006.169.08:10:05.92#ibcon#about to read 3, iclass 21, count 2 2006.169.08:10:05.94#ibcon#read 3, iclass 21, count 2 2006.169.08:10:05.94#ibcon#about to read 4, iclass 21, count 2 2006.169.08:10:05.94#ibcon#read 4, iclass 21, count 2 2006.169.08:10:05.94#ibcon#about to read 5, iclass 21, count 2 2006.169.08:10:05.94#ibcon#read 5, iclass 21, count 2 2006.169.08:10:05.94#ibcon#about to read 6, iclass 21, count 2 2006.169.08:10:05.94#ibcon#read 6, iclass 21, count 2 2006.169.08:10:05.94#ibcon#end of sib2, iclass 21, count 2 2006.169.08:10:05.94#ibcon#*mode == 0, iclass 21, count 2 2006.169.08:10:05.94#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.169.08:10:05.94#ibcon#[25=AT04-07\r\n] 2006.169.08:10:05.94#ibcon#*before write, iclass 21, count 2 2006.169.08:10:05.94#ibcon#enter sib2, iclass 21, count 2 2006.169.08:10:05.94#ibcon#flushed, iclass 21, count 2 2006.169.08:10:05.94#ibcon#about to write, iclass 21, count 2 2006.169.08:10:05.94#ibcon#wrote, iclass 21, count 2 2006.169.08:10:05.94#ibcon#about to read 3, iclass 21, count 2 2006.169.08:10:05.97#ibcon#read 3, iclass 21, count 2 2006.169.08:10:05.97#ibcon#about to read 4, iclass 21, count 2 2006.169.08:10:05.97#ibcon#read 4, iclass 21, count 2 2006.169.08:10:05.97#ibcon#about to read 5, iclass 21, count 2 2006.169.08:10:05.97#ibcon#read 5, iclass 21, count 2 2006.169.08:10:05.97#ibcon#about to read 6, iclass 21, count 2 2006.169.08:10:05.97#ibcon#read 6, iclass 21, count 2 2006.169.08:10:05.97#ibcon#end of sib2, iclass 21, count 2 2006.169.08:10:05.97#ibcon#*after write, iclass 21, count 2 2006.169.08:10:05.97#ibcon#*before return 0, iclass 21, count 2 2006.169.08:10:05.97#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.169.08:10:05.97#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.169.08:10:05.97#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.169.08:10:05.97#ibcon#ireg 7 cls_cnt 0 2006.169.08:10:05.97#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.169.08:10:06.09#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.169.08:10:06.09#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.169.08:10:06.09#ibcon#enter wrdev, iclass 21, count 0 2006.169.08:10:06.09#ibcon#first serial, iclass 21, count 0 2006.169.08:10:06.09#ibcon#enter sib2, iclass 21, count 0 2006.169.08:10:06.09#ibcon#flushed, iclass 21, count 0 2006.169.08:10:06.09#ibcon#about to write, iclass 21, count 0 2006.169.08:10:06.09#ibcon#wrote, iclass 21, count 0 2006.169.08:10:06.09#ibcon#about to read 3, iclass 21, count 0 2006.169.08:10:06.11#ibcon#read 3, iclass 21, count 0 2006.169.08:10:06.11#ibcon#about to read 4, iclass 21, count 0 2006.169.08:10:06.11#ibcon#read 4, iclass 21, count 0 2006.169.08:10:06.11#ibcon#about to read 5, iclass 21, count 0 2006.169.08:10:06.11#ibcon#read 5, iclass 21, count 0 2006.169.08:10:06.11#ibcon#about to read 6, iclass 21, count 0 2006.169.08:10:06.11#ibcon#read 6, iclass 21, count 0 2006.169.08:10:06.11#ibcon#end of sib2, iclass 21, count 0 2006.169.08:10:06.11#ibcon#*mode == 0, iclass 21, count 0 2006.169.08:10:06.11#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.169.08:10:06.11#ibcon#[25=USB\r\n] 2006.169.08:10:06.11#ibcon#*before write, iclass 21, count 0 2006.169.08:10:06.11#ibcon#enter sib2, iclass 21, count 0 2006.169.08:10:06.11#ibcon#flushed, iclass 21, count 0 2006.169.08:10:06.11#ibcon#about to write, iclass 21, count 0 2006.169.08:10:06.11#ibcon#wrote, iclass 21, count 0 2006.169.08:10:06.11#ibcon#about to read 3, iclass 21, count 0 2006.169.08:10:06.14#ibcon#read 3, iclass 21, count 0 2006.169.08:10:06.14#ibcon#about to read 4, iclass 21, count 0 2006.169.08:10:06.14#ibcon#read 4, iclass 21, count 0 2006.169.08:10:06.14#ibcon#about to read 5, iclass 21, count 0 2006.169.08:10:06.14#ibcon#read 5, iclass 21, count 0 2006.169.08:10:06.14#ibcon#about to read 6, iclass 21, count 0 2006.169.08:10:06.14#ibcon#read 6, iclass 21, count 0 2006.169.08:10:06.14#ibcon#end of sib2, iclass 21, count 0 2006.169.08:10:06.14#ibcon#*after write, iclass 21, count 0 2006.169.08:10:06.14#ibcon#*before return 0, iclass 21, count 0 2006.169.08:10:06.14#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.169.08:10:06.14#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.169.08:10:06.14#ibcon#about to clear, iclass 21 cls_cnt 0 2006.169.08:10:06.14#ibcon#cleared, iclass 21 cls_cnt 0 2006.169.08:10:06.14$vc4f8/valo=5,652.99 2006.169.08:10:06.14#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.169.08:10:06.14#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.169.08:10:06.14#ibcon#ireg 17 cls_cnt 0 2006.169.08:10:06.14#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:10:06.14#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:10:06.14#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:10:06.14#ibcon#enter wrdev, iclass 23, count 0 2006.169.08:10:06.14#ibcon#first serial, iclass 23, count 0 2006.169.08:10:06.14#ibcon#enter sib2, iclass 23, count 0 2006.169.08:10:06.14#ibcon#flushed, iclass 23, count 0 2006.169.08:10:06.14#ibcon#about to write, iclass 23, count 0 2006.169.08:10:06.14#ibcon#wrote, iclass 23, count 0 2006.169.08:10:06.14#ibcon#about to read 3, iclass 23, count 0 2006.169.08:10:06.16#ibcon#read 3, iclass 23, count 0 2006.169.08:10:06.16#ibcon#about to read 4, iclass 23, count 0 2006.169.08:10:06.16#ibcon#read 4, iclass 23, count 0 2006.169.08:10:06.16#ibcon#about to read 5, iclass 23, count 0 2006.169.08:10:06.16#ibcon#read 5, iclass 23, count 0 2006.169.08:10:06.16#ibcon#about to read 6, iclass 23, count 0 2006.169.08:10:06.16#ibcon#read 6, iclass 23, count 0 2006.169.08:10:06.16#ibcon#end of sib2, iclass 23, count 0 2006.169.08:10:06.16#ibcon#*mode == 0, iclass 23, count 0 2006.169.08:10:06.16#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.169.08:10:06.16#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.08:10:06.16#ibcon#*before write, iclass 23, count 0 2006.169.08:10:06.16#ibcon#enter sib2, iclass 23, count 0 2006.169.08:10:06.16#ibcon#flushed, iclass 23, count 0 2006.169.08:10:06.16#ibcon#about to write, iclass 23, count 0 2006.169.08:10:06.16#ibcon#wrote, iclass 23, count 0 2006.169.08:10:06.16#ibcon#about to read 3, iclass 23, count 0 2006.169.08:10:06.20#ibcon#read 3, iclass 23, count 0 2006.169.08:10:06.20#ibcon#about to read 4, iclass 23, count 0 2006.169.08:10:06.20#ibcon#read 4, iclass 23, count 0 2006.169.08:10:06.20#ibcon#about to read 5, iclass 23, count 0 2006.169.08:10:06.20#ibcon#read 5, iclass 23, count 0 2006.169.08:10:06.20#ibcon#about to read 6, iclass 23, count 0 2006.169.08:10:06.20#ibcon#read 6, iclass 23, count 0 2006.169.08:10:06.20#ibcon#end of sib2, iclass 23, count 0 2006.169.08:10:06.20#ibcon#*after write, iclass 23, count 0 2006.169.08:10:06.20#ibcon#*before return 0, iclass 23, count 0 2006.169.08:10:06.20#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:10:06.20#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:10:06.20#ibcon#about to clear, iclass 23 cls_cnt 0 2006.169.08:10:06.20#ibcon#cleared, iclass 23 cls_cnt 0 2006.169.08:10:06.20$vc4f8/va=5,7 2006.169.08:10:06.20#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.169.08:10:06.20#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.169.08:10:06.20#ibcon#ireg 11 cls_cnt 2 2006.169.08:10:06.20#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:10:06.26#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:10:06.26#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:10:06.26#ibcon#enter wrdev, iclass 25, count 2 2006.169.08:10:06.26#ibcon#first serial, iclass 25, count 2 2006.169.08:10:06.26#ibcon#enter sib2, iclass 25, count 2 2006.169.08:10:06.26#ibcon#flushed, iclass 25, count 2 2006.169.08:10:06.26#ibcon#about to write, iclass 25, count 2 2006.169.08:10:06.26#ibcon#wrote, iclass 25, count 2 2006.169.08:10:06.26#ibcon#about to read 3, iclass 25, count 2 2006.169.08:10:06.28#ibcon#read 3, iclass 25, count 2 2006.169.08:10:06.28#ibcon#about to read 4, iclass 25, count 2 2006.169.08:10:06.28#ibcon#read 4, iclass 25, count 2 2006.169.08:10:06.28#ibcon#about to read 5, iclass 25, count 2 2006.169.08:10:06.28#ibcon#read 5, iclass 25, count 2 2006.169.08:10:06.28#ibcon#about to read 6, iclass 25, count 2 2006.169.08:10:06.28#ibcon#read 6, iclass 25, count 2 2006.169.08:10:06.28#ibcon#end of sib2, iclass 25, count 2 2006.169.08:10:06.28#ibcon#*mode == 0, iclass 25, count 2 2006.169.08:10:06.28#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.169.08:10:06.28#ibcon#[25=AT05-07\r\n] 2006.169.08:10:06.28#ibcon#*before write, iclass 25, count 2 2006.169.08:10:06.28#ibcon#enter sib2, iclass 25, count 2 2006.169.08:10:06.28#ibcon#flushed, iclass 25, count 2 2006.169.08:10:06.28#ibcon#about to write, iclass 25, count 2 2006.169.08:10:06.28#ibcon#wrote, iclass 25, count 2 2006.169.08:10:06.28#ibcon#about to read 3, iclass 25, count 2 2006.169.08:10:06.31#ibcon#read 3, iclass 25, count 2 2006.169.08:10:06.31#ibcon#about to read 4, iclass 25, count 2 2006.169.08:10:06.31#ibcon#read 4, iclass 25, count 2 2006.169.08:10:06.31#ibcon#about to read 5, iclass 25, count 2 2006.169.08:10:06.31#ibcon#read 5, iclass 25, count 2 2006.169.08:10:06.31#ibcon#about to read 6, iclass 25, count 2 2006.169.08:10:06.31#ibcon#read 6, iclass 25, count 2 2006.169.08:10:06.31#ibcon#end of sib2, iclass 25, count 2 2006.169.08:10:06.31#ibcon#*after write, iclass 25, count 2 2006.169.08:10:06.31#ibcon#*before return 0, iclass 25, count 2 2006.169.08:10:06.31#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:10:06.31#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:10:06.31#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.169.08:10:06.31#ibcon#ireg 7 cls_cnt 0 2006.169.08:10:06.31#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:10:06.43#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:10:06.43#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:10:06.43#ibcon#enter wrdev, iclass 25, count 0 2006.169.08:10:06.43#ibcon#first serial, iclass 25, count 0 2006.169.08:10:06.43#ibcon#enter sib2, iclass 25, count 0 2006.169.08:10:06.43#ibcon#flushed, iclass 25, count 0 2006.169.08:10:06.43#ibcon#about to write, iclass 25, count 0 2006.169.08:10:06.43#ibcon#wrote, iclass 25, count 0 2006.169.08:10:06.43#ibcon#about to read 3, iclass 25, count 0 2006.169.08:10:06.45#ibcon#read 3, iclass 25, count 0 2006.169.08:10:06.45#ibcon#about to read 4, iclass 25, count 0 2006.169.08:10:06.45#ibcon#read 4, iclass 25, count 0 2006.169.08:10:06.45#ibcon#about to read 5, iclass 25, count 0 2006.169.08:10:06.45#ibcon#read 5, iclass 25, count 0 2006.169.08:10:06.45#ibcon#about to read 6, iclass 25, count 0 2006.169.08:10:06.45#ibcon#read 6, iclass 25, count 0 2006.169.08:10:06.45#ibcon#end of sib2, iclass 25, count 0 2006.169.08:10:06.45#ibcon#*mode == 0, iclass 25, count 0 2006.169.08:10:06.45#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.169.08:10:06.45#ibcon#[25=USB\r\n] 2006.169.08:10:06.45#ibcon#*before write, iclass 25, count 0 2006.169.08:10:06.45#ibcon#enter sib2, iclass 25, count 0 2006.169.08:10:06.45#ibcon#flushed, iclass 25, count 0 2006.169.08:10:06.45#ibcon#about to write, iclass 25, count 0 2006.169.08:10:06.45#ibcon#wrote, iclass 25, count 0 2006.169.08:10:06.45#ibcon#about to read 3, iclass 25, count 0 2006.169.08:10:06.48#ibcon#read 3, iclass 25, count 0 2006.169.08:10:06.48#ibcon#about to read 4, iclass 25, count 0 2006.169.08:10:06.48#ibcon#read 4, iclass 25, count 0 2006.169.08:10:06.48#ibcon#about to read 5, iclass 25, count 0 2006.169.08:10:06.48#ibcon#read 5, iclass 25, count 0 2006.169.08:10:06.48#ibcon#about to read 6, iclass 25, count 0 2006.169.08:10:06.48#ibcon#read 6, iclass 25, count 0 2006.169.08:10:06.48#ibcon#end of sib2, iclass 25, count 0 2006.169.08:10:06.48#ibcon#*after write, iclass 25, count 0 2006.169.08:10:06.48#ibcon#*before return 0, iclass 25, count 0 2006.169.08:10:06.48#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:10:06.48#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:10:06.48#ibcon#about to clear, iclass 25 cls_cnt 0 2006.169.08:10:06.48#ibcon#cleared, iclass 25 cls_cnt 0 2006.169.08:10:06.48$vc4f8/valo=6,772.99 2006.169.08:10:06.48#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.169.08:10:06.48#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.169.08:10:06.48#ibcon#ireg 17 cls_cnt 0 2006.169.08:10:06.48#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:10:06.48#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:10:06.48#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:10:06.48#ibcon#enter wrdev, iclass 27, count 0 2006.169.08:10:06.48#ibcon#first serial, iclass 27, count 0 2006.169.08:10:06.48#ibcon#enter sib2, iclass 27, count 0 2006.169.08:10:06.48#ibcon#flushed, iclass 27, count 0 2006.169.08:10:06.48#ibcon#about to write, iclass 27, count 0 2006.169.08:10:06.48#ibcon#wrote, iclass 27, count 0 2006.169.08:10:06.48#ibcon#about to read 3, iclass 27, count 0 2006.169.08:10:06.50#ibcon#read 3, iclass 27, count 0 2006.169.08:10:06.50#ibcon#about to read 4, iclass 27, count 0 2006.169.08:10:06.50#ibcon#read 4, iclass 27, count 0 2006.169.08:10:06.50#ibcon#about to read 5, iclass 27, count 0 2006.169.08:10:06.50#ibcon#read 5, iclass 27, count 0 2006.169.08:10:06.50#ibcon#about to read 6, iclass 27, count 0 2006.169.08:10:06.50#ibcon#read 6, iclass 27, count 0 2006.169.08:10:06.50#ibcon#end of sib2, iclass 27, count 0 2006.169.08:10:06.50#ibcon#*mode == 0, iclass 27, count 0 2006.169.08:10:06.50#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.169.08:10:06.50#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.08:10:06.50#ibcon#*before write, iclass 27, count 0 2006.169.08:10:06.50#ibcon#enter sib2, iclass 27, count 0 2006.169.08:10:06.50#ibcon#flushed, iclass 27, count 0 2006.169.08:10:06.50#ibcon#about to write, iclass 27, count 0 2006.169.08:10:06.50#ibcon#wrote, iclass 27, count 0 2006.169.08:10:06.50#ibcon#about to read 3, iclass 27, count 0 2006.169.08:10:06.54#ibcon#read 3, iclass 27, count 0 2006.169.08:10:06.54#ibcon#about to read 4, iclass 27, count 0 2006.169.08:10:06.54#ibcon#read 4, iclass 27, count 0 2006.169.08:10:06.54#ibcon#about to read 5, iclass 27, count 0 2006.169.08:10:06.54#ibcon#read 5, iclass 27, count 0 2006.169.08:10:06.54#ibcon#about to read 6, iclass 27, count 0 2006.169.08:10:06.54#ibcon#read 6, iclass 27, count 0 2006.169.08:10:06.54#ibcon#end of sib2, iclass 27, count 0 2006.169.08:10:06.54#ibcon#*after write, iclass 27, count 0 2006.169.08:10:06.54#ibcon#*before return 0, iclass 27, count 0 2006.169.08:10:06.54#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:10:06.54#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:10:06.54#ibcon#about to clear, iclass 27 cls_cnt 0 2006.169.08:10:06.54#ibcon#cleared, iclass 27 cls_cnt 0 2006.169.08:10:06.54$vc4f8/va=6,6 2006.169.08:10:06.54#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.169.08:10:06.54#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.169.08:10:06.54#ibcon#ireg 11 cls_cnt 2 2006.169.08:10:06.54#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:10:06.60#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:10:06.60#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:10:06.60#ibcon#enter wrdev, iclass 29, count 2 2006.169.08:10:06.60#ibcon#first serial, iclass 29, count 2 2006.169.08:10:06.60#ibcon#enter sib2, iclass 29, count 2 2006.169.08:10:06.60#ibcon#flushed, iclass 29, count 2 2006.169.08:10:06.60#ibcon#about to write, iclass 29, count 2 2006.169.08:10:06.60#ibcon#wrote, iclass 29, count 2 2006.169.08:10:06.60#ibcon#about to read 3, iclass 29, count 2 2006.169.08:10:06.62#ibcon#read 3, iclass 29, count 2 2006.169.08:10:06.62#ibcon#about to read 4, iclass 29, count 2 2006.169.08:10:06.62#ibcon#read 4, iclass 29, count 2 2006.169.08:10:06.62#ibcon#about to read 5, iclass 29, count 2 2006.169.08:10:06.62#ibcon#read 5, iclass 29, count 2 2006.169.08:10:06.62#ibcon#about to read 6, iclass 29, count 2 2006.169.08:10:06.62#ibcon#read 6, iclass 29, count 2 2006.169.08:10:06.62#ibcon#end of sib2, iclass 29, count 2 2006.169.08:10:06.62#ibcon#*mode == 0, iclass 29, count 2 2006.169.08:10:06.62#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.169.08:10:06.62#ibcon#[25=AT06-06\r\n] 2006.169.08:10:06.62#ibcon#*before write, iclass 29, count 2 2006.169.08:10:06.62#ibcon#enter sib2, iclass 29, count 2 2006.169.08:10:06.62#ibcon#flushed, iclass 29, count 2 2006.169.08:10:06.62#ibcon#about to write, iclass 29, count 2 2006.169.08:10:06.62#ibcon#wrote, iclass 29, count 2 2006.169.08:10:06.62#ibcon#about to read 3, iclass 29, count 2 2006.169.08:10:06.65#ibcon#read 3, iclass 29, count 2 2006.169.08:10:06.65#ibcon#about to read 4, iclass 29, count 2 2006.169.08:10:06.65#ibcon#read 4, iclass 29, count 2 2006.169.08:10:06.65#ibcon#about to read 5, iclass 29, count 2 2006.169.08:10:06.65#ibcon#read 5, iclass 29, count 2 2006.169.08:10:06.65#ibcon#about to read 6, iclass 29, count 2 2006.169.08:10:06.65#ibcon#read 6, iclass 29, count 2 2006.169.08:10:06.65#ibcon#end of sib2, iclass 29, count 2 2006.169.08:10:06.65#ibcon#*after write, iclass 29, count 2 2006.169.08:10:06.65#ibcon#*before return 0, iclass 29, count 2 2006.169.08:10:06.65#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:10:06.65#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:10:06.65#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.169.08:10:06.65#ibcon#ireg 7 cls_cnt 0 2006.169.08:10:06.65#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:10:06.77#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:10:06.77#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:10:06.77#ibcon#enter wrdev, iclass 29, count 0 2006.169.08:10:06.77#ibcon#first serial, iclass 29, count 0 2006.169.08:10:06.77#ibcon#enter sib2, iclass 29, count 0 2006.169.08:10:06.77#ibcon#flushed, iclass 29, count 0 2006.169.08:10:06.77#ibcon#about to write, iclass 29, count 0 2006.169.08:10:06.77#ibcon#wrote, iclass 29, count 0 2006.169.08:10:06.77#ibcon#about to read 3, iclass 29, count 0 2006.169.08:10:06.79#ibcon#read 3, iclass 29, count 0 2006.169.08:10:06.79#ibcon#about to read 4, iclass 29, count 0 2006.169.08:10:06.79#ibcon#read 4, iclass 29, count 0 2006.169.08:10:06.79#ibcon#about to read 5, iclass 29, count 0 2006.169.08:10:06.79#ibcon#read 5, iclass 29, count 0 2006.169.08:10:06.79#ibcon#about to read 6, iclass 29, count 0 2006.169.08:10:06.79#ibcon#read 6, iclass 29, count 0 2006.169.08:10:06.79#ibcon#end of sib2, iclass 29, count 0 2006.169.08:10:06.79#ibcon#*mode == 0, iclass 29, count 0 2006.169.08:10:06.79#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.169.08:10:06.79#ibcon#[25=USB\r\n] 2006.169.08:10:06.79#ibcon#*before write, iclass 29, count 0 2006.169.08:10:06.79#ibcon#enter sib2, iclass 29, count 0 2006.169.08:10:06.79#ibcon#flushed, iclass 29, count 0 2006.169.08:10:06.79#ibcon#about to write, iclass 29, count 0 2006.169.08:10:06.79#ibcon#wrote, iclass 29, count 0 2006.169.08:10:06.79#ibcon#about to read 3, iclass 29, count 0 2006.169.08:10:06.82#ibcon#read 3, iclass 29, count 0 2006.169.08:10:06.82#ibcon#about to read 4, iclass 29, count 0 2006.169.08:10:06.82#ibcon#read 4, iclass 29, count 0 2006.169.08:10:06.82#ibcon#about to read 5, iclass 29, count 0 2006.169.08:10:06.82#ibcon#read 5, iclass 29, count 0 2006.169.08:10:06.82#ibcon#about to read 6, iclass 29, count 0 2006.169.08:10:06.82#ibcon#read 6, iclass 29, count 0 2006.169.08:10:06.82#ibcon#end of sib2, iclass 29, count 0 2006.169.08:10:06.82#ibcon#*after write, iclass 29, count 0 2006.169.08:10:06.82#ibcon#*before return 0, iclass 29, count 0 2006.169.08:10:06.82#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:10:06.82#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:10:06.82#ibcon#about to clear, iclass 29 cls_cnt 0 2006.169.08:10:06.82#ibcon#cleared, iclass 29 cls_cnt 0 2006.169.08:10:06.82$vc4f8/valo=7,832.99 2006.169.08:10:06.82#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.169.08:10:06.82#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.169.08:10:06.82#ibcon#ireg 17 cls_cnt 0 2006.169.08:10:06.82#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:10:06.82#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:10:06.82#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:10:06.82#ibcon#enter wrdev, iclass 31, count 0 2006.169.08:10:06.82#ibcon#first serial, iclass 31, count 0 2006.169.08:10:06.82#ibcon#enter sib2, iclass 31, count 0 2006.169.08:10:06.82#ibcon#flushed, iclass 31, count 0 2006.169.08:10:06.82#ibcon#about to write, iclass 31, count 0 2006.169.08:10:06.82#ibcon#wrote, iclass 31, count 0 2006.169.08:10:06.82#ibcon#about to read 3, iclass 31, count 0 2006.169.08:10:06.84#ibcon#read 3, iclass 31, count 0 2006.169.08:10:06.84#ibcon#about to read 4, iclass 31, count 0 2006.169.08:10:06.84#ibcon#read 4, iclass 31, count 0 2006.169.08:10:06.84#ibcon#about to read 5, iclass 31, count 0 2006.169.08:10:06.84#ibcon#read 5, iclass 31, count 0 2006.169.08:10:06.84#ibcon#about to read 6, iclass 31, count 0 2006.169.08:10:06.84#ibcon#read 6, iclass 31, count 0 2006.169.08:10:06.84#ibcon#end of sib2, iclass 31, count 0 2006.169.08:10:06.84#ibcon#*mode == 0, iclass 31, count 0 2006.169.08:10:06.84#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.169.08:10:06.84#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.08:10:06.84#ibcon#*before write, iclass 31, count 0 2006.169.08:10:06.84#ibcon#enter sib2, iclass 31, count 0 2006.169.08:10:06.84#ibcon#flushed, iclass 31, count 0 2006.169.08:10:06.84#ibcon#about to write, iclass 31, count 0 2006.169.08:10:06.84#ibcon#wrote, iclass 31, count 0 2006.169.08:10:06.84#ibcon#about to read 3, iclass 31, count 0 2006.169.08:10:06.88#ibcon#read 3, iclass 31, count 0 2006.169.08:10:06.88#ibcon#about to read 4, iclass 31, count 0 2006.169.08:10:06.88#ibcon#read 4, iclass 31, count 0 2006.169.08:10:06.88#ibcon#about to read 5, iclass 31, count 0 2006.169.08:10:06.88#ibcon#read 5, iclass 31, count 0 2006.169.08:10:06.88#ibcon#about to read 6, iclass 31, count 0 2006.169.08:10:06.88#ibcon#read 6, iclass 31, count 0 2006.169.08:10:06.88#ibcon#end of sib2, iclass 31, count 0 2006.169.08:10:06.88#ibcon#*after write, iclass 31, count 0 2006.169.08:10:06.88#ibcon#*before return 0, iclass 31, count 0 2006.169.08:10:06.88#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:10:06.88#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:10:06.88#ibcon#about to clear, iclass 31 cls_cnt 0 2006.169.08:10:06.88#ibcon#cleared, iclass 31 cls_cnt 0 2006.169.08:10:06.88$vc4f8/va=7,6 2006.169.08:10:06.88#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.169.08:10:06.88#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.169.08:10:06.88#ibcon#ireg 11 cls_cnt 2 2006.169.08:10:06.88#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:10:06.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:10:06.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:10:06.94#ibcon#enter wrdev, iclass 33, count 2 2006.169.08:10:06.94#ibcon#first serial, iclass 33, count 2 2006.169.08:10:06.94#ibcon#enter sib2, iclass 33, count 2 2006.169.08:10:06.94#ibcon#flushed, iclass 33, count 2 2006.169.08:10:06.94#ibcon#about to write, iclass 33, count 2 2006.169.08:10:06.94#ibcon#wrote, iclass 33, count 2 2006.169.08:10:06.94#ibcon#about to read 3, iclass 33, count 2 2006.169.08:10:06.96#ibcon#read 3, iclass 33, count 2 2006.169.08:10:06.96#ibcon#about to read 4, iclass 33, count 2 2006.169.08:10:06.96#ibcon#read 4, iclass 33, count 2 2006.169.08:10:06.96#ibcon#about to read 5, iclass 33, count 2 2006.169.08:10:06.96#ibcon#read 5, iclass 33, count 2 2006.169.08:10:06.96#ibcon#about to read 6, iclass 33, count 2 2006.169.08:10:06.96#ibcon#read 6, iclass 33, count 2 2006.169.08:10:06.96#ibcon#end of sib2, iclass 33, count 2 2006.169.08:10:06.96#ibcon#*mode == 0, iclass 33, count 2 2006.169.08:10:06.96#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.169.08:10:06.96#ibcon#[25=AT07-06\r\n] 2006.169.08:10:06.96#ibcon#*before write, iclass 33, count 2 2006.169.08:10:06.96#ibcon#enter sib2, iclass 33, count 2 2006.169.08:10:06.96#ibcon#flushed, iclass 33, count 2 2006.169.08:10:06.96#ibcon#about to write, iclass 33, count 2 2006.169.08:10:06.96#ibcon#wrote, iclass 33, count 2 2006.169.08:10:06.96#ibcon#about to read 3, iclass 33, count 2 2006.169.08:10:06.99#ibcon#read 3, iclass 33, count 2 2006.169.08:10:06.99#ibcon#about to read 4, iclass 33, count 2 2006.169.08:10:06.99#ibcon#read 4, iclass 33, count 2 2006.169.08:10:06.99#ibcon#about to read 5, iclass 33, count 2 2006.169.08:10:06.99#ibcon#read 5, iclass 33, count 2 2006.169.08:10:06.99#ibcon#about to read 6, iclass 33, count 2 2006.169.08:10:06.99#ibcon#read 6, iclass 33, count 2 2006.169.08:10:06.99#ibcon#end of sib2, iclass 33, count 2 2006.169.08:10:06.99#ibcon#*after write, iclass 33, count 2 2006.169.08:10:06.99#ibcon#*before return 0, iclass 33, count 2 2006.169.08:10:06.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:10:06.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:10:06.99#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.169.08:10:06.99#ibcon#ireg 7 cls_cnt 0 2006.169.08:10:06.99#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:10:07.11#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:10:07.11#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:10:07.11#ibcon#enter wrdev, iclass 33, count 0 2006.169.08:10:07.11#ibcon#first serial, iclass 33, count 0 2006.169.08:10:07.11#ibcon#enter sib2, iclass 33, count 0 2006.169.08:10:07.11#ibcon#flushed, iclass 33, count 0 2006.169.08:10:07.11#ibcon#about to write, iclass 33, count 0 2006.169.08:10:07.11#ibcon#wrote, iclass 33, count 0 2006.169.08:10:07.11#ibcon#about to read 3, iclass 33, count 0 2006.169.08:10:07.13#ibcon#read 3, iclass 33, count 0 2006.169.08:10:07.13#ibcon#about to read 4, iclass 33, count 0 2006.169.08:10:07.13#ibcon#read 4, iclass 33, count 0 2006.169.08:10:07.13#ibcon#about to read 5, iclass 33, count 0 2006.169.08:10:07.13#ibcon#read 5, iclass 33, count 0 2006.169.08:10:07.13#ibcon#about to read 6, iclass 33, count 0 2006.169.08:10:07.13#ibcon#read 6, iclass 33, count 0 2006.169.08:10:07.13#ibcon#end of sib2, iclass 33, count 0 2006.169.08:10:07.13#ibcon#*mode == 0, iclass 33, count 0 2006.169.08:10:07.13#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.169.08:10:07.13#ibcon#[25=USB\r\n] 2006.169.08:10:07.13#ibcon#*before write, iclass 33, count 0 2006.169.08:10:07.13#ibcon#enter sib2, iclass 33, count 0 2006.169.08:10:07.13#ibcon#flushed, iclass 33, count 0 2006.169.08:10:07.13#ibcon#about to write, iclass 33, count 0 2006.169.08:10:07.13#ibcon#wrote, iclass 33, count 0 2006.169.08:10:07.13#ibcon#about to read 3, iclass 33, count 0 2006.169.08:10:07.16#ibcon#read 3, iclass 33, count 0 2006.169.08:10:07.16#ibcon#about to read 4, iclass 33, count 0 2006.169.08:10:07.16#ibcon#read 4, iclass 33, count 0 2006.169.08:10:07.16#ibcon#about to read 5, iclass 33, count 0 2006.169.08:10:07.16#ibcon#read 5, iclass 33, count 0 2006.169.08:10:07.16#ibcon#about to read 6, iclass 33, count 0 2006.169.08:10:07.16#ibcon#read 6, iclass 33, count 0 2006.169.08:10:07.16#ibcon#end of sib2, iclass 33, count 0 2006.169.08:10:07.16#ibcon#*after write, iclass 33, count 0 2006.169.08:10:07.16#ibcon#*before return 0, iclass 33, count 0 2006.169.08:10:07.16#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:10:07.16#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:10:07.16#ibcon#about to clear, iclass 33 cls_cnt 0 2006.169.08:10:07.16#ibcon#cleared, iclass 33 cls_cnt 0 2006.169.08:10:07.16$vc4f8/valo=8,852.99 2006.169.08:10:07.16#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.169.08:10:07.16#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.169.08:10:07.16#ibcon#ireg 17 cls_cnt 0 2006.169.08:10:07.16#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:10:07.16#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:10:07.16#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:10:07.16#ibcon#enter wrdev, iclass 35, count 0 2006.169.08:10:07.16#ibcon#first serial, iclass 35, count 0 2006.169.08:10:07.16#ibcon#enter sib2, iclass 35, count 0 2006.169.08:10:07.16#ibcon#flushed, iclass 35, count 0 2006.169.08:10:07.16#ibcon#about to write, iclass 35, count 0 2006.169.08:10:07.16#ibcon#wrote, iclass 35, count 0 2006.169.08:10:07.16#ibcon#about to read 3, iclass 35, count 0 2006.169.08:10:07.18#ibcon#read 3, iclass 35, count 0 2006.169.08:10:07.18#ibcon#about to read 4, iclass 35, count 0 2006.169.08:10:07.18#ibcon#read 4, iclass 35, count 0 2006.169.08:10:07.18#ibcon#about to read 5, iclass 35, count 0 2006.169.08:10:07.18#ibcon#read 5, iclass 35, count 0 2006.169.08:10:07.18#ibcon#about to read 6, iclass 35, count 0 2006.169.08:10:07.18#ibcon#read 6, iclass 35, count 0 2006.169.08:10:07.18#ibcon#end of sib2, iclass 35, count 0 2006.169.08:10:07.18#ibcon#*mode == 0, iclass 35, count 0 2006.169.08:10:07.18#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.169.08:10:07.18#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.08:10:07.18#ibcon#*before write, iclass 35, count 0 2006.169.08:10:07.18#ibcon#enter sib2, iclass 35, count 0 2006.169.08:10:07.18#ibcon#flushed, iclass 35, count 0 2006.169.08:10:07.18#ibcon#about to write, iclass 35, count 0 2006.169.08:10:07.18#ibcon#wrote, iclass 35, count 0 2006.169.08:10:07.18#ibcon#about to read 3, iclass 35, count 0 2006.169.08:10:07.22#ibcon#read 3, iclass 35, count 0 2006.169.08:10:07.22#ibcon#about to read 4, iclass 35, count 0 2006.169.08:10:07.22#ibcon#read 4, iclass 35, count 0 2006.169.08:10:07.22#ibcon#about to read 5, iclass 35, count 0 2006.169.08:10:07.22#ibcon#read 5, iclass 35, count 0 2006.169.08:10:07.22#ibcon#about to read 6, iclass 35, count 0 2006.169.08:10:07.22#ibcon#read 6, iclass 35, count 0 2006.169.08:10:07.22#ibcon#end of sib2, iclass 35, count 0 2006.169.08:10:07.22#ibcon#*after write, iclass 35, count 0 2006.169.08:10:07.22#ibcon#*before return 0, iclass 35, count 0 2006.169.08:10:07.22#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:10:07.22#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:10:07.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.169.08:10:07.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.169.08:10:07.22$vc4f8/va=8,7 2006.169.08:10:07.22#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.169.08:10:07.22#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.169.08:10:07.22#ibcon#ireg 11 cls_cnt 2 2006.169.08:10:07.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:10:07.28#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:10:07.28#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:10:07.28#ibcon#enter wrdev, iclass 37, count 2 2006.169.08:10:07.28#ibcon#first serial, iclass 37, count 2 2006.169.08:10:07.28#ibcon#enter sib2, iclass 37, count 2 2006.169.08:10:07.28#ibcon#flushed, iclass 37, count 2 2006.169.08:10:07.28#ibcon#about to write, iclass 37, count 2 2006.169.08:10:07.28#ibcon#wrote, iclass 37, count 2 2006.169.08:10:07.28#ibcon#about to read 3, iclass 37, count 2 2006.169.08:10:07.30#ibcon#read 3, iclass 37, count 2 2006.169.08:10:07.30#ibcon#about to read 4, iclass 37, count 2 2006.169.08:10:07.30#ibcon#read 4, iclass 37, count 2 2006.169.08:10:07.30#ibcon#about to read 5, iclass 37, count 2 2006.169.08:10:07.30#ibcon#read 5, iclass 37, count 2 2006.169.08:10:07.30#ibcon#about to read 6, iclass 37, count 2 2006.169.08:10:07.30#ibcon#read 6, iclass 37, count 2 2006.169.08:10:07.30#ibcon#end of sib2, iclass 37, count 2 2006.169.08:10:07.30#ibcon#*mode == 0, iclass 37, count 2 2006.169.08:10:07.30#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.169.08:10:07.30#ibcon#[25=AT08-07\r\n] 2006.169.08:10:07.30#ibcon#*before write, iclass 37, count 2 2006.169.08:10:07.30#ibcon#enter sib2, iclass 37, count 2 2006.169.08:10:07.30#ibcon#flushed, iclass 37, count 2 2006.169.08:10:07.30#ibcon#about to write, iclass 37, count 2 2006.169.08:10:07.30#ibcon#wrote, iclass 37, count 2 2006.169.08:10:07.30#ibcon#about to read 3, iclass 37, count 2 2006.169.08:10:07.33#ibcon#read 3, iclass 37, count 2 2006.169.08:10:07.33#ibcon#about to read 4, iclass 37, count 2 2006.169.08:10:07.33#ibcon#read 4, iclass 37, count 2 2006.169.08:10:07.33#ibcon#about to read 5, iclass 37, count 2 2006.169.08:10:07.33#ibcon#read 5, iclass 37, count 2 2006.169.08:10:07.33#ibcon#about to read 6, iclass 37, count 2 2006.169.08:10:07.33#ibcon#read 6, iclass 37, count 2 2006.169.08:10:07.33#ibcon#end of sib2, iclass 37, count 2 2006.169.08:10:07.33#ibcon#*after write, iclass 37, count 2 2006.169.08:10:07.33#ibcon#*before return 0, iclass 37, count 2 2006.169.08:10:07.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:10:07.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:10:07.33#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.169.08:10:07.33#ibcon#ireg 7 cls_cnt 0 2006.169.08:10:07.33#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:10:07.45#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:10:07.45#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:10:07.45#ibcon#enter wrdev, iclass 37, count 0 2006.169.08:10:07.45#ibcon#first serial, iclass 37, count 0 2006.169.08:10:07.45#ibcon#enter sib2, iclass 37, count 0 2006.169.08:10:07.45#ibcon#flushed, iclass 37, count 0 2006.169.08:10:07.45#ibcon#about to write, iclass 37, count 0 2006.169.08:10:07.45#ibcon#wrote, iclass 37, count 0 2006.169.08:10:07.45#ibcon#about to read 3, iclass 37, count 0 2006.169.08:10:07.47#ibcon#read 3, iclass 37, count 0 2006.169.08:10:07.47#ibcon#about to read 4, iclass 37, count 0 2006.169.08:10:07.47#ibcon#read 4, iclass 37, count 0 2006.169.08:10:07.47#ibcon#about to read 5, iclass 37, count 0 2006.169.08:10:07.47#ibcon#read 5, iclass 37, count 0 2006.169.08:10:07.47#ibcon#about to read 6, iclass 37, count 0 2006.169.08:10:07.47#ibcon#read 6, iclass 37, count 0 2006.169.08:10:07.47#ibcon#end of sib2, iclass 37, count 0 2006.169.08:10:07.47#ibcon#*mode == 0, iclass 37, count 0 2006.169.08:10:07.47#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.169.08:10:07.47#ibcon#[25=USB\r\n] 2006.169.08:10:07.47#ibcon#*before write, iclass 37, count 0 2006.169.08:10:07.47#ibcon#enter sib2, iclass 37, count 0 2006.169.08:10:07.47#ibcon#flushed, iclass 37, count 0 2006.169.08:10:07.47#ibcon#about to write, iclass 37, count 0 2006.169.08:10:07.47#ibcon#wrote, iclass 37, count 0 2006.169.08:10:07.47#ibcon#about to read 3, iclass 37, count 0 2006.169.08:10:07.50#ibcon#read 3, iclass 37, count 0 2006.169.08:10:07.50#ibcon#about to read 4, iclass 37, count 0 2006.169.08:10:07.50#ibcon#read 4, iclass 37, count 0 2006.169.08:10:07.50#ibcon#about to read 5, iclass 37, count 0 2006.169.08:10:07.50#ibcon#read 5, iclass 37, count 0 2006.169.08:10:07.50#ibcon#about to read 6, iclass 37, count 0 2006.169.08:10:07.50#ibcon#read 6, iclass 37, count 0 2006.169.08:10:07.50#ibcon#end of sib2, iclass 37, count 0 2006.169.08:10:07.50#ibcon#*after write, iclass 37, count 0 2006.169.08:10:07.50#ibcon#*before return 0, iclass 37, count 0 2006.169.08:10:07.50#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:10:07.50#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:10:07.50#ibcon#about to clear, iclass 37 cls_cnt 0 2006.169.08:10:07.50#ibcon#cleared, iclass 37 cls_cnt 0 2006.169.08:10:07.50$vc4f8/vblo=1,632.99 2006.169.08:10:07.50#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.169.08:10:07.50#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.169.08:10:07.50#ibcon#ireg 17 cls_cnt 0 2006.169.08:10:07.50#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:10:07.50#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:10:07.50#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:10:07.50#ibcon#enter wrdev, iclass 39, count 0 2006.169.08:10:07.50#ibcon#first serial, iclass 39, count 0 2006.169.08:10:07.50#ibcon#enter sib2, iclass 39, count 0 2006.169.08:10:07.50#ibcon#flushed, iclass 39, count 0 2006.169.08:10:07.50#ibcon#about to write, iclass 39, count 0 2006.169.08:10:07.50#ibcon#wrote, iclass 39, count 0 2006.169.08:10:07.50#ibcon#about to read 3, iclass 39, count 0 2006.169.08:10:07.52#ibcon#read 3, iclass 39, count 0 2006.169.08:10:07.52#ibcon#about to read 4, iclass 39, count 0 2006.169.08:10:07.52#ibcon#read 4, iclass 39, count 0 2006.169.08:10:07.52#ibcon#about to read 5, iclass 39, count 0 2006.169.08:10:07.52#ibcon#read 5, iclass 39, count 0 2006.169.08:10:07.52#ibcon#about to read 6, iclass 39, count 0 2006.169.08:10:07.52#ibcon#read 6, iclass 39, count 0 2006.169.08:10:07.52#ibcon#end of sib2, iclass 39, count 0 2006.169.08:10:07.52#ibcon#*mode == 0, iclass 39, count 0 2006.169.08:10:07.52#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.169.08:10:07.52#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.08:10:07.52#ibcon#*before write, iclass 39, count 0 2006.169.08:10:07.52#ibcon#enter sib2, iclass 39, count 0 2006.169.08:10:07.52#ibcon#flushed, iclass 39, count 0 2006.169.08:10:07.52#ibcon#about to write, iclass 39, count 0 2006.169.08:10:07.52#ibcon#wrote, iclass 39, count 0 2006.169.08:10:07.52#ibcon#about to read 3, iclass 39, count 0 2006.169.08:10:07.56#ibcon#read 3, iclass 39, count 0 2006.169.08:10:07.56#ibcon#about to read 4, iclass 39, count 0 2006.169.08:10:07.56#ibcon#read 4, iclass 39, count 0 2006.169.08:10:07.56#ibcon#about to read 5, iclass 39, count 0 2006.169.08:10:07.56#ibcon#read 5, iclass 39, count 0 2006.169.08:10:07.56#ibcon#about to read 6, iclass 39, count 0 2006.169.08:10:07.56#ibcon#read 6, iclass 39, count 0 2006.169.08:10:07.56#ibcon#end of sib2, iclass 39, count 0 2006.169.08:10:07.56#ibcon#*after write, iclass 39, count 0 2006.169.08:10:07.56#ibcon#*before return 0, iclass 39, count 0 2006.169.08:10:07.56#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:10:07.56#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:10:07.56#ibcon#about to clear, iclass 39 cls_cnt 0 2006.169.08:10:07.56#ibcon#cleared, iclass 39 cls_cnt 0 2006.169.08:10:07.56$vc4f8/vb=1,4 2006.169.08:10:07.56#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.169.08:10:07.56#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.169.08:10:07.56#ibcon#ireg 11 cls_cnt 2 2006.169.08:10:07.56#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:10:07.56#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:10:07.56#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:10:07.56#ibcon#enter wrdev, iclass 3, count 2 2006.169.08:10:07.56#ibcon#first serial, iclass 3, count 2 2006.169.08:10:07.56#ibcon#enter sib2, iclass 3, count 2 2006.169.08:10:07.56#ibcon#flushed, iclass 3, count 2 2006.169.08:10:07.56#ibcon#about to write, iclass 3, count 2 2006.169.08:10:07.56#ibcon#wrote, iclass 3, count 2 2006.169.08:10:07.56#ibcon#about to read 3, iclass 3, count 2 2006.169.08:10:07.58#ibcon#read 3, iclass 3, count 2 2006.169.08:10:07.58#ibcon#about to read 4, iclass 3, count 2 2006.169.08:10:07.58#ibcon#read 4, iclass 3, count 2 2006.169.08:10:07.58#ibcon#about to read 5, iclass 3, count 2 2006.169.08:10:07.58#ibcon#read 5, iclass 3, count 2 2006.169.08:10:07.58#ibcon#about to read 6, iclass 3, count 2 2006.169.08:10:07.58#ibcon#read 6, iclass 3, count 2 2006.169.08:10:07.58#ibcon#end of sib2, iclass 3, count 2 2006.169.08:10:07.58#ibcon#*mode == 0, iclass 3, count 2 2006.169.08:10:07.58#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.169.08:10:07.58#ibcon#[27=AT01-04\r\n] 2006.169.08:10:07.58#ibcon#*before write, iclass 3, count 2 2006.169.08:10:07.58#ibcon#enter sib2, iclass 3, count 2 2006.169.08:10:07.58#ibcon#flushed, iclass 3, count 2 2006.169.08:10:07.58#ibcon#about to write, iclass 3, count 2 2006.169.08:10:07.58#ibcon#wrote, iclass 3, count 2 2006.169.08:10:07.58#ibcon#about to read 3, iclass 3, count 2 2006.169.08:10:07.61#ibcon#read 3, iclass 3, count 2 2006.169.08:10:07.61#ibcon#about to read 4, iclass 3, count 2 2006.169.08:10:07.61#ibcon#read 4, iclass 3, count 2 2006.169.08:10:07.61#ibcon#about to read 5, iclass 3, count 2 2006.169.08:10:07.61#ibcon#read 5, iclass 3, count 2 2006.169.08:10:07.61#ibcon#about to read 6, iclass 3, count 2 2006.169.08:10:07.61#ibcon#read 6, iclass 3, count 2 2006.169.08:10:07.61#ibcon#end of sib2, iclass 3, count 2 2006.169.08:10:07.61#ibcon#*after write, iclass 3, count 2 2006.169.08:10:07.61#ibcon#*before return 0, iclass 3, count 2 2006.169.08:10:07.61#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:10:07.61#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:10:07.61#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.169.08:10:07.61#ibcon#ireg 7 cls_cnt 0 2006.169.08:10:07.61#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:10:07.63#abcon#<5=/04 3.1 5.8 18.131001003.8\r\n> 2006.169.08:10:07.65#abcon#{5=INTERFACE CLEAR} 2006.169.08:10:07.71#abcon#[5=S1D000X0/0*\r\n] 2006.169.08:10:07.73#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:10:07.73#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:10:07.73#ibcon#enter wrdev, iclass 3, count 0 2006.169.08:10:07.73#ibcon#first serial, iclass 3, count 0 2006.169.08:10:07.73#ibcon#enter sib2, iclass 3, count 0 2006.169.08:10:07.73#ibcon#flushed, iclass 3, count 0 2006.169.08:10:07.73#ibcon#about to write, iclass 3, count 0 2006.169.08:10:07.73#ibcon#wrote, iclass 3, count 0 2006.169.08:10:07.73#ibcon#about to read 3, iclass 3, count 0 2006.169.08:10:07.75#ibcon#read 3, iclass 3, count 0 2006.169.08:10:07.75#ibcon#about to read 4, iclass 3, count 0 2006.169.08:10:07.75#ibcon#read 4, iclass 3, count 0 2006.169.08:10:07.75#ibcon#about to read 5, iclass 3, count 0 2006.169.08:10:07.75#ibcon#read 5, iclass 3, count 0 2006.169.08:10:07.75#ibcon#about to read 6, iclass 3, count 0 2006.169.08:10:07.75#ibcon#read 6, iclass 3, count 0 2006.169.08:10:07.75#ibcon#end of sib2, iclass 3, count 0 2006.169.08:10:07.75#ibcon#*mode == 0, iclass 3, count 0 2006.169.08:10:07.75#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.169.08:10:07.75#ibcon#[27=USB\r\n] 2006.169.08:10:07.75#ibcon#*before write, iclass 3, count 0 2006.169.08:10:07.75#ibcon#enter sib2, iclass 3, count 0 2006.169.08:10:07.75#ibcon#flushed, iclass 3, count 0 2006.169.08:10:07.75#ibcon#about to write, iclass 3, count 0 2006.169.08:10:07.75#ibcon#wrote, iclass 3, count 0 2006.169.08:10:07.75#ibcon#about to read 3, iclass 3, count 0 2006.169.08:10:07.78#ibcon#read 3, iclass 3, count 0 2006.169.08:10:07.78#ibcon#about to read 4, iclass 3, count 0 2006.169.08:10:07.78#ibcon#read 4, iclass 3, count 0 2006.169.08:10:07.78#ibcon#about to read 5, iclass 3, count 0 2006.169.08:10:07.78#ibcon#read 5, iclass 3, count 0 2006.169.08:10:07.78#ibcon#about to read 6, iclass 3, count 0 2006.169.08:10:07.78#ibcon#read 6, iclass 3, count 0 2006.169.08:10:07.78#ibcon#end of sib2, iclass 3, count 0 2006.169.08:10:07.78#ibcon#*after write, iclass 3, count 0 2006.169.08:10:07.78#ibcon#*before return 0, iclass 3, count 0 2006.169.08:10:07.78#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:10:07.78#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:10:07.78#ibcon#about to clear, iclass 3 cls_cnt 0 2006.169.08:10:07.78#ibcon#cleared, iclass 3 cls_cnt 0 2006.169.08:10:07.78$vc4f8/vblo=2,640.99 2006.169.08:10:07.78#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.169.08:10:07.78#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.169.08:10:07.78#ibcon#ireg 17 cls_cnt 0 2006.169.08:10:07.78#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:10:07.78#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:10:07.78#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:10:07.78#ibcon#enter wrdev, iclass 11, count 0 2006.169.08:10:07.78#ibcon#first serial, iclass 11, count 0 2006.169.08:10:07.78#ibcon#enter sib2, iclass 11, count 0 2006.169.08:10:07.78#ibcon#flushed, iclass 11, count 0 2006.169.08:10:07.78#ibcon#about to write, iclass 11, count 0 2006.169.08:10:07.78#ibcon#wrote, iclass 11, count 0 2006.169.08:10:07.78#ibcon#about to read 3, iclass 11, count 0 2006.169.08:10:07.80#ibcon#read 3, iclass 11, count 0 2006.169.08:10:07.80#ibcon#about to read 4, iclass 11, count 0 2006.169.08:10:07.80#ibcon#read 4, iclass 11, count 0 2006.169.08:10:07.80#ibcon#about to read 5, iclass 11, count 0 2006.169.08:10:07.80#ibcon#read 5, iclass 11, count 0 2006.169.08:10:07.80#ibcon#about to read 6, iclass 11, count 0 2006.169.08:10:07.80#ibcon#read 6, iclass 11, count 0 2006.169.08:10:07.80#ibcon#end of sib2, iclass 11, count 0 2006.169.08:10:07.80#ibcon#*mode == 0, iclass 11, count 0 2006.169.08:10:07.80#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.169.08:10:07.80#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.08:10:07.80#ibcon#*before write, iclass 11, count 0 2006.169.08:10:07.80#ibcon#enter sib2, iclass 11, count 0 2006.169.08:10:07.80#ibcon#flushed, iclass 11, count 0 2006.169.08:10:07.80#ibcon#about to write, iclass 11, count 0 2006.169.08:10:07.80#ibcon#wrote, iclass 11, count 0 2006.169.08:10:07.80#ibcon#about to read 3, iclass 11, count 0 2006.169.08:10:07.84#ibcon#read 3, iclass 11, count 0 2006.169.08:10:07.84#ibcon#about to read 4, iclass 11, count 0 2006.169.08:10:07.84#ibcon#read 4, iclass 11, count 0 2006.169.08:10:07.84#ibcon#about to read 5, iclass 11, count 0 2006.169.08:10:07.84#ibcon#read 5, iclass 11, count 0 2006.169.08:10:07.84#ibcon#about to read 6, iclass 11, count 0 2006.169.08:10:07.84#ibcon#read 6, iclass 11, count 0 2006.169.08:10:07.84#ibcon#end of sib2, iclass 11, count 0 2006.169.08:10:07.84#ibcon#*after write, iclass 11, count 0 2006.169.08:10:07.84#ibcon#*before return 0, iclass 11, count 0 2006.169.08:10:07.84#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:10:07.84#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:10:07.84#ibcon#about to clear, iclass 11 cls_cnt 0 2006.169.08:10:07.84#ibcon#cleared, iclass 11 cls_cnt 0 2006.169.08:10:07.84$vc4f8/vb=2,4 2006.169.08:10:07.84#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.169.08:10:07.84#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.169.08:10:07.84#ibcon#ireg 11 cls_cnt 2 2006.169.08:10:07.84#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:10:07.90#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:10:07.90#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:10:07.90#ibcon#enter wrdev, iclass 13, count 2 2006.169.08:10:07.90#ibcon#first serial, iclass 13, count 2 2006.169.08:10:07.90#ibcon#enter sib2, iclass 13, count 2 2006.169.08:10:07.90#ibcon#flushed, iclass 13, count 2 2006.169.08:10:07.90#ibcon#about to write, iclass 13, count 2 2006.169.08:10:07.90#ibcon#wrote, iclass 13, count 2 2006.169.08:10:07.90#ibcon#about to read 3, iclass 13, count 2 2006.169.08:10:07.92#ibcon#read 3, iclass 13, count 2 2006.169.08:10:07.92#ibcon#about to read 4, iclass 13, count 2 2006.169.08:10:07.92#ibcon#read 4, iclass 13, count 2 2006.169.08:10:07.92#ibcon#about to read 5, iclass 13, count 2 2006.169.08:10:07.92#ibcon#read 5, iclass 13, count 2 2006.169.08:10:07.92#ibcon#about to read 6, iclass 13, count 2 2006.169.08:10:07.92#ibcon#read 6, iclass 13, count 2 2006.169.08:10:07.92#ibcon#end of sib2, iclass 13, count 2 2006.169.08:10:07.92#ibcon#*mode == 0, iclass 13, count 2 2006.169.08:10:07.92#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.169.08:10:07.92#ibcon#[27=AT02-04\r\n] 2006.169.08:10:07.92#ibcon#*before write, iclass 13, count 2 2006.169.08:10:07.92#ibcon#enter sib2, iclass 13, count 2 2006.169.08:10:07.92#ibcon#flushed, iclass 13, count 2 2006.169.08:10:07.92#ibcon#about to write, iclass 13, count 2 2006.169.08:10:07.92#ibcon#wrote, iclass 13, count 2 2006.169.08:10:07.92#ibcon#about to read 3, iclass 13, count 2 2006.169.08:10:07.95#ibcon#read 3, iclass 13, count 2 2006.169.08:10:07.95#ibcon#about to read 4, iclass 13, count 2 2006.169.08:10:07.95#ibcon#read 4, iclass 13, count 2 2006.169.08:10:07.95#ibcon#about to read 5, iclass 13, count 2 2006.169.08:10:07.95#ibcon#read 5, iclass 13, count 2 2006.169.08:10:07.95#ibcon#about to read 6, iclass 13, count 2 2006.169.08:10:07.95#ibcon#read 6, iclass 13, count 2 2006.169.08:10:07.95#ibcon#end of sib2, iclass 13, count 2 2006.169.08:10:07.95#ibcon#*after write, iclass 13, count 2 2006.169.08:10:07.95#ibcon#*before return 0, iclass 13, count 2 2006.169.08:10:07.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:10:07.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:10:07.95#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.169.08:10:07.95#ibcon#ireg 7 cls_cnt 0 2006.169.08:10:07.95#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:10:08.07#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:10:08.07#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:10:08.07#ibcon#enter wrdev, iclass 13, count 0 2006.169.08:10:08.07#ibcon#first serial, iclass 13, count 0 2006.169.08:10:08.07#ibcon#enter sib2, iclass 13, count 0 2006.169.08:10:08.07#ibcon#flushed, iclass 13, count 0 2006.169.08:10:08.07#ibcon#about to write, iclass 13, count 0 2006.169.08:10:08.07#ibcon#wrote, iclass 13, count 0 2006.169.08:10:08.07#ibcon#about to read 3, iclass 13, count 0 2006.169.08:10:08.09#ibcon#read 3, iclass 13, count 0 2006.169.08:10:08.09#ibcon#about to read 4, iclass 13, count 0 2006.169.08:10:08.09#ibcon#read 4, iclass 13, count 0 2006.169.08:10:08.09#ibcon#about to read 5, iclass 13, count 0 2006.169.08:10:08.09#ibcon#read 5, iclass 13, count 0 2006.169.08:10:08.09#ibcon#about to read 6, iclass 13, count 0 2006.169.08:10:08.09#ibcon#read 6, iclass 13, count 0 2006.169.08:10:08.09#ibcon#end of sib2, iclass 13, count 0 2006.169.08:10:08.09#ibcon#*mode == 0, iclass 13, count 0 2006.169.08:10:08.09#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.08:10:08.09#ibcon#[27=USB\r\n] 2006.169.08:10:08.09#ibcon#*before write, iclass 13, count 0 2006.169.08:10:08.09#ibcon#enter sib2, iclass 13, count 0 2006.169.08:10:08.09#ibcon#flushed, iclass 13, count 0 2006.169.08:10:08.09#ibcon#about to write, iclass 13, count 0 2006.169.08:10:08.09#ibcon#wrote, iclass 13, count 0 2006.169.08:10:08.09#ibcon#about to read 3, iclass 13, count 0 2006.169.08:10:08.12#ibcon#read 3, iclass 13, count 0 2006.169.08:10:08.12#ibcon#about to read 4, iclass 13, count 0 2006.169.08:10:08.12#ibcon#read 4, iclass 13, count 0 2006.169.08:10:08.12#ibcon#about to read 5, iclass 13, count 0 2006.169.08:10:08.12#ibcon#read 5, iclass 13, count 0 2006.169.08:10:08.12#ibcon#about to read 6, iclass 13, count 0 2006.169.08:10:08.12#ibcon#read 6, iclass 13, count 0 2006.169.08:10:08.12#ibcon#end of sib2, iclass 13, count 0 2006.169.08:10:08.12#ibcon#*after write, iclass 13, count 0 2006.169.08:10:08.12#ibcon#*before return 0, iclass 13, count 0 2006.169.08:10:08.12#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:10:08.12#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:10:08.12#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.08:10:08.12#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.08:10:08.12$vc4f8/vblo=3,656.99 2006.169.08:10:08.12#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.169.08:10:08.12#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.169.08:10:08.12#ibcon#ireg 17 cls_cnt 0 2006.169.08:10:08.12#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:10:08.12#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:10:08.12#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:10:08.12#ibcon#enter wrdev, iclass 15, count 0 2006.169.08:10:08.12#ibcon#first serial, iclass 15, count 0 2006.169.08:10:08.12#ibcon#enter sib2, iclass 15, count 0 2006.169.08:10:08.12#ibcon#flushed, iclass 15, count 0 2006.169.08:10:08.12#ibcon#about to write, iclass 15, count 0 2006.169.08:10:08.12#ibcon#wrote, iclass 15, count 0 2006.169.08:10:08.12#ibcon#about to read 3, iclass 15, count 0 2006.169.08:10:08.14#ibcon#read 3, iclass 15, count 0 2006.169.08:10:08.14#ibcon#about to read 4, iclass 15, count 0 2006.169.08:10:08.14#ibcon#read 4, iclass 15, count 0 2006.169.08:10:08.14#ibcon#about to read 5, iclass 15, count 0 2006.169.08:10:08.14#ibcon#read 5, iclass 15, count 0 2006.169.08:10:08.14#ibcon#about to read 6, iclass 15, count 0 2006.169.08:10:08.14#ibcon#read 6, iclass 15, count 0 2006.169.08:10:08.14#ibcon#end of sib2, iclass 15, count 0 2006.169.08:10:08.14#ibcon#*mode == 0, iclass 15, count 0 2006.169.08:10:08.14#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.169.08:10:08.14#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.08:10:08.14#ibcon#*before write, iclass 15, count 0 2006.169.08:10:08.14#ibcon#enter sib2, iclass 15, count 0 2006.169.08:10:08.14#ibcon#flushed, iclass 15, count 0 2006.169.08:10:08.14#ibcon#about to write, iclass 15, count 0 2006.169.08:10:08.14#ibcon#wrote, iclass 15, count 0 2006.169.08:10:08.14#ibcon#about to read 3, iclass 15, count 0 2006.169.08:10:08.18#ibcon#read 3, iclass 15, count 0 2006.169.08:10:08.18#ibcon#about to read 4, iclass 15, count 0 2006.169.08:10:08.18#ibcon#read 4, iclass 15, count 0 2006.169.08:10:08.18#ibcon#about to read 5, iclass 15, count 0 2006.169.08:10:08.18#ibcon#read 5, iclass 15, count 0 2006.169.08:10:08.18#ibcon#about to read 6, iclass 15, count 0 2006.169.08:10:08.18#ibcon#read 6, iclass 15, count 0 2006.169.08:10:08.18#ibcon#end of sib2, iclass 15, count 0 2006.169.08:10:08.18#ibcon#*after write, iclass 15, count 0 2006.169.08:10:08.18#ibcon#*before return 0, iclass 15, count 0 2006.169.08:10:08.18#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:10:08.18#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:10:08.18#ibcon#about to clear, iclass 15 cls_cnt 0 2006.169.08:10:08.18#ibcon#cleared, iclass 15 cls_cnt 0 2006.169.08:10:08.18$vc4f8/vb=3,4 2006.169.08:10:08.18#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.169.08:10:08.18#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.169.08:10:08.18#ibcon#ireg 11 cls_cnt 2 2006.169.08:10:08.18#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:10:08.24#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:10:08.24#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:10:08.24#ibcon#enter wrdev, iclass 17, count 2 2006.169.08:10:08.24#ibcon#first serial, iclass 17, count 2 2006.169.08:10:08.24#ibcon#enter sib2, iclass 17, count 2 2006.169.08:10:08.24#ibcon#flushed, iclass 17, count 2 2006.169.08:10:08.24#ibcon#about to write, iclass 17, count 2 2006.169.08:10:08.24#ibcon#wrote, iclass 17, count 2 2006.169.08:10:08.24#ibcon#about to read 3, iclass 17, count 2 2006.169.08:10:08.26#ibcon#read 3, iclass 17, count 2 2006.169.08:10:08.26#ibcon#about to read 4, iclass 17, count 2 2006.169.08:10:08.26#ibcon#read 4, iclass 17, count 2 2006.169.08:10:08.26#ibcon#about to read 5, iclass 17, count 2 2006.169.08:10:08.26#ibcon#read 5, iclass 17, count 2 2006.169.08:10:08.26#ibcon#about to read 6, iclass 17, count 2 2006.169.08:10:08.26#ibcon#read 6, iclass 17, count 2 2006.169.08:10:08.26#ibcon#end of sib2, iclass 17, count 2 2006.169.08:10:08.26#ibcon#*mode == 0, iclass 17, count 2 2006.169.08:10:08.26#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.169.08:10:08.26#ibcon#[27=AT03-04\r\n] 2006.169.08:10:08.26#ibcon#*before write, iclass 17, count 2 2006.169.08:10:08.26#ibcon#enter sib2, iclass 17, count 2 2006.169.08:10:08.26#ibcon#flushed, iclass 17, count 2 2006.169.08:10:08.26#ibcon#about to write, iclass 17, count 2 2006.169.08:10:08.26#ibcon#wrote, iclass 17, count 2 2006.169.08:10:08.26#ibcon#about to read 3, iclass 17, count 2 2006.169.08:10:08.29#ibcon#read 3, iclass 17, count 2 2006.169.08:10:08.29#ibcon#about to read 4, iclass 17, count 2 2006.169.08:10:08.29#ibcon#read 4, iclass 17, count 2 2006.169.08:10:08.29#ibcon#about to read 5, iclass 17, count 2 2006.169.08:10:08.29#ibcon#read 5, iclass 17, count 2 2006.169.08:10:08.29#ibcon#about to read 6, iclass 17, count 2 2006.169.08:10:08.29#ibcon#read 6, iclass 17, count 2 2006.169.08:10:08.29#ibcon#end of sib2, iclass 17, count 2 2006.169.08:10:08.29#ibcon#*after write, iclass 17, count 2 2006.169.08:10:08.29#ibcon#*before return 0, iclass 17, count 2 2006.169.08:10:08.29#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:10:08.29#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:10:08.29#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.169.08:10:08.29#ibcon#ireg 7 cls_cnt 0 2006.169.08:10:08.29#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:10:08.41#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:10:08.41#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:10:08.41#ibcon#enter wrdev, iclass 17, count 0 2006.169.08:10:08.41#ibcon#first serial, iclass 17, count 0 2006.169.08:10:08.41#ibcon#enter sib2, iclass 17, count 0 2006.169.08:10:08.41#ibcon#flushed, iclass 17, count 0 2006.169.08:10:08.41#ibcon#about to write, iclass 17, count 0 2006.169.08:10:08.41#ibcon#wrote, iclass 17, count 0 2006.169.08:10:08.41#ibcon#about to read 3, iclass 17, count 0 2006.169.08:10:08.43#ibcon#read 3, iclass 17, count 0 2006.169.08:10:08.43#ibcon#about to read 4, iclass 17, count 0 2006.169.08:10:08.43#ibcon#read 4, iclass 17, count 0 2006.169.08:10:08.43#ibcon#about to read 5, iclass 17, count 0 2006.169.08:10:08.43#ibcon#read 5, iclass 17, count 0 2006.169.08:10:08.43#ibcon#about to read 6, iclass 17, count 0 2006.169.08:10:08.43#ibcon#read 6, iclass 17, count 0 2006.169.08:10:08.43#ibcon#end of sib2, iclass 17, count 0 2006.169.08:10:08.43#ibcon#*mode == 0, iclass 17, count 0 2006.169.08:10:08.43#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.169.08:10:08.43#ibcon#[27=USB\r\n] 2006.169.08:10:08.43#ibcon#*before write, iclass 17, count 0 2006.169.08:10:08.43#ibcon#enter sib2, iclass 17, count 0 2006.169.08:10:08.43#ibcon#flushed, iclass 17, count 0 2006.169.08:10:08.43#ibcon#about to write, iclass 17, count 0 2006.169.08:10:08.43#ibcon#wrote, iclass 17, count 0 2006.169.08:10:08.43#ibcon#about to read 3, iclass 17, count 0 2006.169.08:10:08.46#ibcon#read 3, iclass 17, count 0 2006.169.08:10:08.46#ibcon#about to read 4, iclass 17, count 0 2006.169.08:10:08.46#ibcon#read 4, iclass 17, count 0 2006.169.08:10:08.46#ibcon#about to read 5, iclass 17, count 0 2006.169.08:10:08.46#ibcon#read 5, iclass 17, count 0 2006.169.08:10:08.46#ibcon#about to read 6, iclass 17, count 0 2006.169.08:10:08.46#ibcon#read 6, iclass 17, count 0 2006.169.08:10:08.46#ibcon#end of sib2, iclass 17, count 0 2006.169.08:10:08.46#ibcon#*after write, iclass 17, count 0 2006.169.08:10:08.46#ibcon#*before return 0, iclass 17, count 0 2006.169.08:10:08.46#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:10:08.46#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:10:08.46#ibcon#about to clear, iclass 17 cls_cnt 0 2006.169.08:10:08.46#ibcon#cleared, iclass 17 cls_cnt 0 2006.169.08:10:08.46$vc4f8/vblo=4,712.99 2006.169.08:10:08.46#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.169.08:10:08.46#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.169.08:10:08.46#ibcon#ireg 17 cls_cnt 0 2006.169.08:10:08.46#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.169.08:10:08.46#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.169.08:10:08.46#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.169.08:10:08.46#ibcon#enter wrdev, iclass 19, count 0 2006.169.08:10:08.46#ibcon#first serial, iclass 19, count 0 2006.169.08:10:08.46#ibcon#enter sib2, iclass 19, count 0 2006.169.08:10:08.46#ibcon#flushed, iclass 19, count 0 2006.169.08:10:08.46#ibcon#about to write, iclass 19, count 0 2006.169.08:10:08.46#ibcon#wrote, iclass 19, count 0 2006.169.08:10:08.46#ibcon#about to read 3, iclass 19, count 0 2006.169.08:10:08.48#ibcon#read 3, iclass 19, count 0 2006.169.08:10:08.48#ibcon#about to read 4, iclass 19, count 0 2006.169.08:10:08.48#ibcon#read 4, iclass 19, count 0 2006.169.08:10:08.48#ibcon#about to read 5, iclass 19, count 0 2006.169.08:10:08.48#ibcon#read 5, iclass 19, count 0 2006.169.08:10:08.48#ibcon#about to read 6, iclass 19, count 0 2006.169.08:10:08.48#ibcon#read 6, iclass 19, count 0 2006.169.08:10:08.48#ibcon#end of sib2, iclass 19, count 0 2006.169.08:10:08.48#ibcon#*mode == 0, iclass 19, count 0 2006.169.08:10:08.48#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.169.08:10:08.48#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.08:10:08.48#ibcon#*before write, iclass 19, count 0 2006.169.08:10:08.48#ibcon#enter sib2, iclass 19, count 0 2006.169.08:10:08.48#ibcon#flushed, iclass 19, count 0 2006.169.08:10:08.48#ibcon#about to write, iclass 19, count 0 2006.169.08:10:08.48#ibcon#wrote, iclass 19, count 0 2006.169.08:10:08.48#ibcon#about to read 3, iclass 19, count 0 2006.169.08:10:08.52#ibcon#read 3, iclass 19, count 0 2006.169.08:10:08.52#ibcon#about to read 4, iclass 19, count 0 2006.169.08:10:08.52#ibcon#read 4, iclass 19, count 0 2006.169.08:10:08.52#ibcon#about to read 5, iclass 19, count 0 2006.169.08:10:08.52#ibcon#read 5, iclass 19, count 0 2006.169.08:10:08.52#ibcon#about to read 6, iclass 19, count 0 2006.169.08:10:08.52#ibcon#read 6, iclass 19, count 0 2006.169.08:10:08.52#ibcon#end of sib2, iclass 19, count 0 2006.169.08:10:08.52#ibcon#*after write, iclass 19, count 0 2006.169.08:10:08.52#ibcon#*before return 0, iclass 19, count 0 2006.169.08:10:08.52#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.169.08:10:08.52#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.169.08:10:08.52#ibcon#about to clear, iclass 19 cls_cnt 0 2006.169.08:10:08.52#ibcon#cleared, iclass 19 cls_cnt 0 2006.169.08:10:08.52$vc4f8/vb=4,4 2006.169.08:10:08.52#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.169.08:10:08.52#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.169.08:10:08.52#ibcon#ireg 11 cls_cnt 2 2006.169.08:10:08.52#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.169.08:10:08.58#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.169.08:10:08.58#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.169.08:10:08.58#ibcon#enter wrdev, iclass 21, count 2 2006.169.08:10:08.58#ibcon#first serial, iclass 21, count 2 2006.169.08:10:08.58#ibcon#enter sib2, iclass 21, count 2 2006.169.08:10:08.58#ibcon#flushed, iclass 21, count 2 2006.169.08:10:08.58#ibcon#about to write, iclass 21, count 2 2006.169.08:10:08.58#ibcon#wrote, iclass 21, count 2 2006.169.08:10:08.58#ibcon#about to read 3, iclass 21, count 2 2006.169.08:10:08.60#ibcon#read 3, iclass 21, count 2 2006.169.08:10:08.60#ibcon#about to read 4, iclass 21, count 2 2006.169.08:10:08.60#ibcon#read 4, iclass 21, count 2 2006.169.08:10:08.60#ibcon#about to read 5, iclass 21, count 2 2006.169.08:10:08.60#ibcon#read 5, iclass 21, count 2 2006.169.08:10:08.60#ibcon#about to read 6, iclass 21, count 2 2006.169.08:10:08.60#ibcon#read 6, iclass 21, count 2 2006.169.08:10:08.60#ibcon#end of sib2, iclass 21, count 2 2006.169.08:10:08.60#ibcon#*mode == 0, iclass 21, count 2 2006.169.08:10:08.60#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.169.08:10:08.60#ibcon#[27=AT04-04\r\n] 2006.169.08:10:08.60#ibcon#*before write, iclass 21, count 2 2006.169.08:10:08.60#ibcon#enter sib2, iclass 21, count 2 2006.169.08:10:08.60#ibcon#flushed, iclass 21, count 2 2006.169.08:10:08.60#ibcon#about to write, iclass 21, count 2 2006.169.08:10:08.60#ibcon#wrote, iclass 21, count 2 2006.169.08:10:08.60#ibcon#about to read 3, iclass 21, count 2 2006.169.08:10:08.63#ibcon#read 3, iclass 21, count 2 2006.169.08:10:08.63#ibcon#about to read 4, iclass 21, count 2 2006.169.08:10:08.63#ibcon#read 4, iclass 21, count 2 2006.169.08:10:08.63#ibcon#about to read 5, iclass 21, count 2 2006.169.08:10:08.63#ibcon#read 5, iclass 21, count 2 2006.169.08:10:08.63#ibcon#about to read 6, iclass 21, count 2 2006.169.08:10:08.63#ibcon#read 6, iclass 21, count 2 2006.169.08:10:08.63#ibcon#end of sib2, iclass 21, count 2 2006.169.08:10:08.63#ibcon#*after write, iclass 21, count 2 2006.169.08:10:08.63#ibcon#*before return 0, iclass 21, count 2 2006.169.08:10:08.63#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.169.08:10:08.63#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.169.08:10:08.63#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.169.08:10:08.63#ibcon#ireg 7 cls_cnt 0 2006.169.08:10:08.63#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.169.08:10:08.75#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.169.08:10:08.75#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.169.08:10:08.75#ibcon#enter wrdev, iclass 21, count 0 2006.169.08:10:08.75#ibcon#first serial, iclass 21, count 0 2006.169.08:10:08.75#ibcon#enter sib2, iclass 21, count 0 2006.169.08:10:08.75#ibcon#flushed, iclass 21, count 0 2006.169.08:10:08.75#ibcon#about to write, iclass 21, count 0 2006.169.08:10:08.75#ibcon#wrote, iclass 21, count 0 2006.169.08:10:08.75#ibcon#about to read 3, iclass 21, count 0 2006.169.08:10:08.77#ibcon#read 3, iclass 21, count 0 2006.169.08:10:08.77#ibcon#about to read 4, iclass 21, count 0 2006.169.08:10:08.77#ibcon#read 4, iclass 21, count 0 2006.169.08:10:08.77#ibcon#about to read 5, iclass 21, count 0 2006.169.08:10:08.77#ibcon#read 5, iclass 21, count 0 2006.169.08:10:08.77#ibcon#about to read 6, iclass 21, count 0 2006.169.08:10:08.77#ibcon#read 6, iclass 21, count 0 2006.169.08:10:08.77#ibcon#end of sib2, iclass 21, count 0 2006.169.08:10:08.77#ibcon#*mode == 0, iclass 21, count 0 2006.169.08:10:08.77#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.169.08:10:08.77#ibcon#[27=USB\r\n] 2006.169.08:10:08.77#ibcon#*before write, iclass 21, count 0 2006.169.08:10:08.77#ibcon#enter sib2, iclass 21, count 0 2006.169.08:10:08.77#ibcon#flushed, iclass 21, count 0 2006.169.08:10:08.77#ibcon#about to write, iclass 21, count 0 2006.169.08:10:08.77#ibcon#wrote, iclass 21, count 0 2006.169.08:10:08.77#ibcon#about to read 3, iclass 21, count 0 2006.169.08:10:08.80#ibcon#read 3, iclass 21, count 0 2006.169.08:10:08.80#ibcon#about to read 4, iclass 21, count 0 2006.169.08:10:08.80#ibcon#read 4, iclass 21, count 0 2006.169.08:10:08.80#ibcon#about to read 5, iclass 21, count 0 2006.169.08:10:08.80#ibcon#read 5, iclass 21, count 0 2006.169.08:10:08.80#ibcon#about to read 6, iclass 21, count 0 2006.169.08:10:08.80#ibcon#read 6, iclass 21, count 0 2006.169.08:10:08.80#ibcon#end of sib2, iclass 21, count 0 2006.169.08:10:08.80#ibcon#*after write, iclass 21, count 0 2006.169.08:10:08.80#ibcon#*before return 0, iclass 21, count 0 2006.169.08:10:08.80#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.169.08:10:08.80#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.169.08:10:08.80#ibcon#about to clear, iclass 21 cls_cnt 0 2006.169.08:10:08.80#ibcon#cleared, iclass 21 cls_cnt 0 2006.169.08:10:08.80$vc4f8/vblo=5,744.99 2006.169.08:10:08.80#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.169.08:10:08.80#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.169.08:10:08.80#ibcon#ireg 17 cls_cnt 0 2006.169.08:10:08.80#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:10:08.80#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:10:08.80#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:10:08.80#ibcon#enter wrdev, iclass 23, count 0 2006.169.08:10:08.80#ibcon#first serial, iclass 23, count 0 2006.169.08:10:08.80#ibcon#enter sib2, iclass 23, count 0 2006.169.08:10:08.80#ibcon#flushed, iclass 23, count 0 2006.169.08:10:08.80#ibcon#about to write, iclass 23, count 0 2006.169.08:10:08.80#ibcon#wrote, iclass 23, count 0 2006.169.08:10:08.80#ibcon#about to read 3, iclass 23, count 0 2006.169.08:10:08.82#ibcon#read 3, iclass 23, count 0 2006.169.08:10:08.82#ibcon#about to read 4, iclass 23, count 0 2006.169.08:10:08.82#ibcon#read 4, iclass 23, count 0 2006.169.08:10:08.82#ibcon#about to read 5, iclass 23, count 0 2006.169.08:10:08.82#ibcon#read 5, iclass 23, count 0 2006.169.08:10:08.82#ibcon#about to read 6, iclass 23, count 0 2006.169.08:10:08.82#ibcon#read 6, iclass 23, count 0 2006.169.08:10:08.82#ibcon#end of sib2, iclass 23, count 0 2006.169.08:10:08.82#ibcon#*mode == 0, iclass 23, count 0 2006.169.08:10:08.82#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.169.08:10:08.82#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.08:10:08.82#ibcon#*before write, iclass 23, count 0 2006.169.08:10:08.82#ibcon#enter sib2, iclass 23, count 0 2006.169.08:10:08.82#ibcon#flushed, iclass 23, count 0 2006.169.08:10:08.82#ibcon#about to write, iclass 23, count 0 2006.169.08:10:08.82#ibcon#wrote, iclass 23, count 0 2006.169.08:10:08.82#ibcon#about to read 3, iclass 23, count 0 2006.169.08:10:08.86#ibcon#read 3, iclass 23, count 0 2006.169.08:10:08.86#ibcon#about to read 4, iclass 23, count 0 2006.169.08:10:08.86#ibcon#read 4, iclass 23, count 0 2006.169.08:10:08.86#ibcon#about to read 5, iclass 23, count 0 2006.169.08:10:08.86#ibcon#read 5, iclass 23, count 0 2006.169.08:10:08.86#ibcon#about to read 6, iclass 23, count 0 2006.169.08:10:08.86#ibcon#read 6, iclass 23, count 0 2006.169.08:10:08.86#ibcon#end of sib2, iclass 23, count 0 2006.169.08:10:08.86#ibcon#*after write, iclass 23, count 0 2006.169.08:10:08.86#ibcon#*before return 0, iclass 23, count 0 2006.169.08:10:08.86#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:10:08.86#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:10:08.86#ibcon#about to clear, iclass 23 cls_cnt 0 2006.169.08:10:08.86#ibcon#cleared, iclass 23 cls_cnt 0 2006.169.08:10:08.86$vc4f8/vb=5,4 2006.169.08:10:08.86#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.169.08:10:08.86#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.169.08:10:08.86#ibcon#ireg 11 cls_cnt 2 2006.169.08:10:08.86#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:10:08.92#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:10:08.92#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:10:08.92#ibcon#enter wrdev, iclass 25, count 2 2006.169.08:10:08.92#ibcon#first serial, iclass 25, count 2 2006.169.08:10:08.92#ibcon#enter sib2, iclass 25, count 2 2006.169.08:10:08.92#ibcon#flushed, iclass 25, count 2 2006.169.08:10:08.92#ibcon#about to write, iclass 25, count 2 2006.169.08:10:08.92#ibcon#wrote, iclass 25, count 2 2006.169.08:10:08.92#ibcon#about to read 3, iclass 25, count 2 2006.169.08:10:08.94#ibcon#read 3, iclass 25, count 2 2006.169.08:10:08.94#ibcon#about to read 4, iclass 25, count 2 2006.169.08:10:08.94#ibcon#read 4, iclass 25, count 2 2006.169.08:10:08.94#ibcon#about to read 5, iclass 25, count 2 2006.169.08:10:08.94#ibcon#read 5, iclass 25, count 2 2006.169.08:10:08.94#ibcon#about to read 6, iclass 25, count 2 2006.169.08:10:08.94#ibcon#read 6, iclass 25, count 2 2006.169.08:10:08.94#ibcon#end of sib2, iclass 25, count 2 2006.169.08:10:08.94#ibcon#*mode == 0, iclass 25, count 2 2006.169.08:10:08.94#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.169.08:10:08.94#ibcon#[27=AT05-04\r\n] 2006.169.08:10:08.94#ibcon#*before write, iclass 25, count 2 2006.169.08:10:08.94#ibcon#enter sib2, iclass 25, count 2 2006.169.08:10:08.94#ibcon#flushed, iclass 25, count 2 2006.169.08:10:08.94#ibcon#about to write, iclass 25, count 2 2006.169.08:10:08.94#ibcon#wrote, iclass 25, count 2 2006.169.08:10:08.94#ibcon#about to read 3, iclass 25, count 2 2006.169.08:10:08.97#ibcon#read 3, iclass 25, count 2 2006.169.08:10:08.97#ibcon#about to read 4, iclass 25, count 2 2006.169.08:10:08.97#ibcon#read 4, iclass 25, count 2 2006.169.08:10:08.97#ibcon#about to read 5, iclass 25, count 2 2006.169.08:10:08.97#ibcon#read 5, iclass 25, count 2 2006.169.08:10:08.97#ibcon#about to read 6, iclass 25, count 2 2006.169.08:10:08.97#ibcon#read 6, iclass 25, count 2 2006.169.08:10:08.97#ibcon#end of sib2, iclass 25, count 2 2006.169.08:10:08.97#ibcon#*after write, iclass 25, count 2 2006.169.08:10:08.97#ibcon#*before return 0, iclass 25, count 2 2006.169.08:10:08.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:10:08.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:10:08.97#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.169.08:10:08.97#ibcon#ireg 7 cls_cnt 0 2006.169.08:10:08.97#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:10:09.09#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:10:09.09#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:10:09.09#ibcon#enter wrdev, iclass 25, count 0 2006.169.08:10:09.09#ibcon#first serial, iclass 25, count 0 2006.169.08:10:09.09#ibcon#enter sib2, iclass 25, count 0 2006.169.08:10:09.09#ibcon#flushed, iclass 25, count 0 2006.169.08:10:09.09#ibcon#about to write, iclass 25, count 0 2006.169.08:10:09.09#ibcon#wrote, iclass 25, count 0 2006.169.08:10:09.09#ibcon#about to read 3, iclass 25, count 0 2006.169.08:10:09.11#ibcon#read 3, iclass 25, count 0 2006.169.08:10:09.11#ibcon#about to read 4, iclass 25, count 0 2006.169.08:10:09.11#ibcon#read 4, iclass 25, count 0 2006.169.08:10:09.11#ibcon#about to read 5, iclass 25, count 0 2006.169.08:10:09.11#ibcon#read 5, iclass 25, count 0 2006.169.08:10:09.11#ibcon#about to read 6, iclass 25, count 0 2006.169.08:10:09.11#ibcon#read 6, iclass 25, count 0 2006.169.08:10:09.11#ibcon#end of sib2, iclass 25, count 0 2006.169.08:10:09.11#ibcon#*mode == 0, iclass 25, count 0 2006.169.08:10:09.11#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.169.08:10:09.11#ibcon#[27=USB\r\n] 2006.169.08:10:09.11#ibcon#*before write, iclass 25, count 0 2006.169.08:10:09.11#ibcon#enter sib2, iclass 25, count 0 2006.169.08:10:09.11#ibcon#flushed, iclass 25, count 0 2006.169.08:10:09.11#ibcon#about to write, iclass 25, count 0 2006.169.08:10:09.11#ibcon#wrote, iclass 25, count 0 2006.169.08:10:09.11#ibcon#about to read 3, iclass 25, count 0 2006.169.08:10:09.14#ibcon#read 3, iclass 25, count 0 2006.169.08:10:09.14#ibcon#about to read 4, iclass 25, count 0 2006.169.08:10:09.14#ibcon#read 4, iclass 25, count 0 2006.169.08:10:09.14#ibcon#about to read 5, iclass 25, count 0 2006.169.08:10:09.14#ibcon#read 5, iclass 25, count 0 2006.169.08:10:09.14#ibcon#about to read 6, iclass 25, count 0 2006.169.08:10:09.14#ibcon#read 6, iclass 25, count 0 2006.169.08:10:09.14#ibcon#end of sib2, iclass 25, count 0 2006.169.08:10:09.14#ibcon#*after write, iclass 25, count 0 2006.169.08:10:09.14#ibcon#*before return 0, iclass 25, count 0 2006.169.08:10:09.14#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:10:09.14#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:10:09.14#ibcon#about to clear, iclass 25 cls_cnt 0 2006.169.08:10:09.14#ibcon#cleared, iclass 25 cls_cnt 0 2006.169.08:10:09.14$vc4f8/vblo=6,752.99 2006.169.08:10:09.14#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.169.08:10:09.14#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.169.08:10:09.14#ibcon#ireg 17 cls_cnt 0 2006.169.08:10:09.14#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:10:09.14#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:10:09.14#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:10:09.14#ibcon#enter wrdev, iclass 27, count 0 2006.169.08:10:09.14#ibcon#first serial, iclass 27, count 0 2006.169.08:10:09.14#ibcon#enter sib2, iclass 27, count 0 2006.169.08:10:09.14#ibcon#flushed, iclass 27, count 0 2006.169.08:10:09.14#ibcon#about to write, iclass 27, count 0 2006.169.08:10:09.14#ibcon#wrote, iclass 27, count 0 2006.169.08:10:09.14#ibcon#about to read 3, iclass 27, count 0 2006.169.08:10:09.16#ibcon#read 3, iclass 27, count 0 2006.169.08:10:09.16#ibcon#about to read 4, iclass 27, count 0 2006.169.08:10:09.16#ibcon#read 4, iclass 27, count 0 2006.169.08:10:09.16#ibcon#about to read 5, iclass 27, count 0 2006.169.08:10:09.16#ibcon#read 5, iclass 27, count 0 2006.169.08:10:09.16#ibcon#about to read 6, iclass 27, count 0 2006.169.08:10:09.16#ibcon#read 6, iclass 27, count 0 2006.169.08:10:09.16#ibcon#end of sib2, iclass 27, count 0 2006.169.08:10:09.16#ibcon#*mode == 0, iclass 27, count 0 2006.169.08:10:09.16#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.169.08:10:09.16#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.08:10:09.16#ibcon#*before write, iclass 27, count 0 2006.169.08:10:09.16#ibcon#enter sib2, iclass 27, count 0 2006.169.08:10:09.16#ibcon#flushed, iclass 27, count 0 2006.169.08:10:09.16#ibcon#about to write, iclass 27, count 0 2006.169.08:10:09.16#ibcon#wrote, iclass 27, count 0 2006.169.08:10:09.16#ibcon#about to read 3, iclass 27, count 0 2006.169.08:10:09.20#ibcon#read 3, iclass 27, count 0 2006.169.08:10:09.20#ibcon#about to read 4, iclass 27, count 0 2006.169.08:10:09.20#ibcon#read 4, iclass 27, count 0 2006.169.08:10:09.20#ibcon#about to read 5, iclass 27, count 0 2006.169.08:10:09.20#ibcon#read 5, iclass 27, count 0 2006.169.08:10:09.20#ibcon#about to read 6, iclass 27, count 0 2006.169.08:10:09.20#ibcon#read 6, iclass 27, count 0 2006.169.08:10:09.20#ibcon#end of sib2, iclass 27, count 0 2006.169.08:10:09.20#ibcon#*after write, iclass 27, count 0 2006.169.08:10:09.20#ibcon#*before return 0, iclass 27, count 0 2006.169.08:10:09.20#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:10:09.20#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:10:09.20#ibcon#about to clear, iclass 27 cls_cnt 0 2006.169.08:10:09.20#ibcon#cleared, iclass 27 cls_cnt 0 2006.169.08:10:09.20$vc4f8/vb=6,4 2006.169.08:10:09.20#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.169.08:10:09.20#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.169.08:10:09.20#ibcon#ireg 11 cls_cnt 2 2006.169.08:10:09.20#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:10:09.26#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:10:09.26#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:10:09.26#ibcon#enter wrdev, iclass 29, count 2 2006.169.08:10:09.26#ibcon#first serial, iclass 29, count 2 2006.169.08:10:09.26#ibcon#enter sib2, iclass 29, count 2 2006.169.08:10:09.26#ibcon#flushed, iclass 29, count 2 2006.169.08:10:09.26#ibcon#about to write, iclass 29, count 2 2006.169.08:10:09.26#ibcon#wrote, iclass 29, count 2 2006.169.08:10:09.26#ibcon#about to read 3, iclass 29, count 2 2006.169.08:10:09.28#ibcon#read 3, iclass 29, count 2 2006.169.08:10:09.28#ibcon#about to read 4, iclass 29, count 2 2006.169.08:10:09.28#ibcon#read 4, iclass 29, count 2 2006.169.08:10:09.28#ibcon#about to read 5, iclass 29, count 2 2006.169.08:10:09.28#ibcon#read 5, iclass 29, count 2 2006.169.08:10:09.28#ibcon#about to read 6, iclass 29, count 2 2006.169.08:10:09.28#ibcon#read 6, iclass 29, count 2 2006.169.08:10:09.28#ibcon#end of sib2, iclass 29, count 2 2006.169.08:10:09.28#ibcon#*mode == 0, iclass 29, count 2 2006.169.08:10:09.28#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.169.08:10:09.28#ibcon#[27=AT06-04\r\n] 2006.169.08:10:09.28#ibcon#*before write, iclass 29, count 2 2006.169.08:10:09.28#ibcon#enter sib2, iclass 29, count 2 2006.169.08:10:09.28#ibcon#flushed, iclass 29, count 2 2006.169.08:10:09.28#ibcon#about to write, iclass 29, count 2 2006.169.08:10:09.28#ibcon#wrote, iclass 29, count 2 2006.169.08:10:09.28#ibcon#about to read 3, iclass 29, count 2 2006.169.08:10:09.31#ibcon#read 3, iclass 29, count 2 2006.169.08:10:09.31#ibcon#about to read 4, iclass 29, count 2 2006.169.08:10:09.31#ibcon#read 4, iclass 29, count 2 2006.169.08:10:09.31#ibcon#about to read 5, iclass 29, count 2 2006.169.08:10:09.31#ibcon#read 5, iclass 29, count 2 2006.169.08:10:09.31#ibcon#about to read 6, iclass 29, count 2 2006.169.08:10:09.31#ibcon#read 6, iclass 29, count 2 2006.169.08:10:09.31#ibcon#end of sib2, iclass 29, count 2 2006.169.08:10:09.31#ibcon#*after write, iclass 29, count 2 2006.169.08:10:09.31#ibcon#*before return 0, iclass 29, count 2 2006.169.08:10:09.31#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:10:09.31#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:10:09.31#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.169.08:10:09.31#ibcon#ireg 7 cls_cnt 0 2006.169.08:10:09.31#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:10:09.43#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:10:09.43#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:10:09.43#ibcon#enter wrdev, iclass 29, count 0 2006.169.08:10:09.43#ibcon#first serial, iclass 29, count 0 2006.169.08:10:09.43#ibcon#enter sib2, iclass 29, count 0 2006.169.08:10:09.43#ibcon#flushed, iclass 29, count 0 2006.169.08:10:09.43#ibcon#about to write, iclass 29, count 0 2006.169.08:10:09.43#ibcon#wrote, iclass 29, count 0 2006.169.08:10:09.43#ibcon#about to read 3, iclass 29, count 0 2006.169.08:10:09.45#ibcon#read 3, iclass 29, count 0 2006.169.08:10:09.45#ibcon#about to read 4, iclass 29, count 0 2006.169.08:10:09.45#ibcon#read 4, iclass 29, count 0 2006.169.08:10:09.45#ibcon#about to read 5, iclass 29, count 0 2006.169.08:10:09.45#ibcon#read 5, iclass 29, count 0 2006.169.08:10:09.45#ibcon#about to read 6, iclass 29, count 0 2006.169.08:10:09.45#ibcon#read 6, iclass 29, count 0 2006.169.08:10:09.45#ibcon#end of sib2, iclass 29, count 0 2006.169.08:10:09.45#ibcon#*mode == 0, iclass 29, count 0 2006.169.08:10:09.45#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.169.08:10:09.45#ibcon#[27=USB\r\n] 2006.169.08:10:09.45#ibcon#*before write, iclass 29, count 0 2006.169.08:10:09.45#ibcon#enter sib2, iclass 29, count 0 2006.169.08:10:09.45#ibcon#flushed, iclass 29, count 0 2006.169.08:10:09.45#ibcon#about to write, iclass 29, count 0 2006.169.08:10:09.45#ibcon#wrote, iclass 29, count 0 2006.169.08:10:09.45#ibcon#about to read 3, iclass 29, count 0 2006.169.08:10:09.48#ibcon#read 3, iclass 29, count 0 2006.169.08:10:09.48#ibcon#about to read 4, iclass 29, count 0 2006.169.08:10:09.48#ibcon#read 4, iclass 29, count 0 2006.169.08:10:09.48#ibcon#about to read 5, iclass 29, count 0 2006.169.08:10:09.48#ibcon#read 5, iclass 29, count 0 2006.169.08:10:09.48#ibcon#about to read 6, iclass 29, count 0 2006.169.08:10:09.48#ibcon#read 6, iclass 29, count 0 2006.169.08:10:09.48#ibcon#end of sib2, iclass 29, count 0 2006.169.08:10:09.48#ibcon#*after write, iclass 29, count 0 2006.169.08:10:09.48#ibcon#*before return 0, iclass 29, count 0 2006.169.08:10:09.48#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:10:09.48#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:10:09.48#ibcon#about to clear, iclass 29 cls_cnt 0 2006.169.08:10:09.48#ibcon#cleared, iclass 29 cls_cnt 0 2006.169.08:10:09.48$vc4f8/vabw=wide 2006.169.08:10:09.48#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.169.08:10:09.48#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.169.08:10:09.48#ibcon#ireg 8 cls_cnt 0 2006.169.08:10:09.48#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:10:09.48#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:10:09.48#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:10:09.48#ibcon#enter wrdev, iclass 31, count 0 2006.169.08:10:09.48#ibcon#first serial, iclass 31, count 0 2006.169.08:10:09.48#ibcon#enter sib2, iclass 31, count 0 2006.169.08:10:09.48#ibcon#flushed, iclass 31, count 0 2006.169.08:10:09.48#ibcon#about to write, iclass 31, count 0 2006.169.08:10:09.48#ibcon#wrote, iclass 31, count 0 2006.169.08:10:09.48#ibcon#about to read 3, iclass 31, count 0 2006.169.08:10:09.50#ibcon#read 3, iclass 31, count 0 2006.169.08:10:09.50#ibcon#about to read 4, iclass 31, count 0 2006.169.08:10:09.50#ibcon#read 4, iclass 31, count 0 2006.169.08:10:09.50#ibcon#about to read 5, iclass 31, count 0 2006.169.08:10:09.50#ibcon#read 5, iclass 31, count 0 2006.169.08:10:09.50#ibcon#about to read 6, iclass 31, count 0 2006.169.08:10:09.50#ibcon#read 6, iclass 31, count 0 2006.169.08:10:09.50#ibcon#end of sib2, iclass 31, count 0 2006.169.08:10:09.50#ibcon#*mode == 0, iclass 31, count 0 2006.169.08:10:09.50#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.169.08:10:09.50#ibcon#[25=BW32\r\n] 2006.169.08:10:09.50#ibcon#*before write, iclass 31, count 0 2006.169.08:10:09.50#ibcon#enter sib2, iclass 31, count 0 2006.169.08:10:09.50#ibcon#flushed, iclass 31, count 0 2006.169.08:10:09.50#ibcon#about to write, iclass 31, count 0 2006.169.08:10:09.50#ibcon#wrote, iclass 31, count 0 2006.169.08:10:09.50#ibcon#about to read 3, iclass 31, count 0 2006.169.08:10:09.53#ibcon#read 3, iclass 31, count 0 2006.169.08:10:09.53#ibcon#about to read 4, iclass 31, count 0 2006.169.08:10:09.53#ibcon#read 4, iclass 31, count 0 2006.169.08:10:09.53#ibcon#about to read 5, iclass 31, count 0 2006.169.08:10:09.53#ibcon#read 5, iclass 31, count 0 2006.169.08:10:09.53#ibcon#about to read 6, iclass 31, count 0 2006.169.08:10:09.53#ibcon#read 6, iclass 31, count 0 2006.169.08:10:09.53#ibcon#end of sib2, iclass 31, count 0 2006.169.08:10:09.53#ibcon#*after write, iclass 31, count 0 2006.169.08:10:09.53#ibcon#*before return 0, iclass 31, count 0 2006.169.08:10:09.53#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:10:09.53#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:10:09.53#ibcon#about to clear, iclass 31 cls_cnt 0 2006.169.08:10:09.53#ibcon#cleared, iclass 31 cls_cnt 0 2006.169.08:10:09.53$vc4f8/vbbw=wide 2006.169.08:10:09.53#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.169.08:10:09.53#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.169.08:10:09.53#ibcon#ireg 8 cls_cnt 0 2006.169.08:10:09.53#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:10:09.60#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:10:09.60#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:10:09.60#ibcon#enter wrdev, iclass 33, count 0 2006.169.08:10:09.60#ibcon#first serial, iclass 33, count 0 2006.169.08:10:09.60#ibcon#enter sib2, iclass 33, count 0 2006.169.08:10:09.60#ibcon#flushed, iclass 33, count 0 2006.169.08:10:09.60#ibcon#about to write, iclass 33, count 0 2006.169.08:10:09.60#ibcon#wrote, iclass 33, count 0 2006.169.08:10:09.60#ibcon#about to read 3, iclass 33, count 0 2006.169.08:10:09.62#ibcon#read 3, iclass 33, count 0 2006.169.08:10:09.62#ibcon#about to read 4, iclass 33, count 0 2006.169.08:10:09.62#ibcon#read 4, iclass 33, count 0 2006.169.08:10:09.62#ibcon#about to read 5, iclass 33, count 0 2006.169.08:10:09.62#ibcon#read 5, iclass 33, count 0 2006.169.08:10:09.62#ibcon#about to read 6, iclass 33, count 0 2006.169.08:10:09.62#ibcon#read 6, iclass 33, count 0 2006.169.08:10:09.62#ibcon#end of sib2, iclass 33, count 0 2006.169.08:10:09.62#ibcon#*mode == 0, iclass 33, count 0 2006.169.08:10:09.62#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.169.08:10:09.62#ibcon#[27=BW32\r\n] 2006.169.08:10:09.62#ibcon#*before write, iclass 33, count 0 2006.169.08:10:09.62#ibcon#enter sib2, iclass 33, count 0 2006.169.08:10:09.62#ibcon#flushed, iclass 33, count 0 2006.169.08:10:09.62#ibcon#about to write, iclass 33, count 0 2006.169.08:10:09.62#ibcon#wrote, iclass 33, count 0 2006.169.08:10:09.62#ibcon#about to read 3, iclass 33, count 0 2006.169.08:10:09.65#ibcon#read 3, iclass 33, count 0 2006.169.08:10:09.65#ibcon#about to read 4, iclass 33, count 0 2006.169.08:10:09.65#ibcon#read 4, iclass 33, count 0 2006.169.08:10:09.65#ibcon#about to read 5, iclass 33, count 0 2006.169.08:10:09.65#ibcon#read 5, iclass 33, count 0 2006.169.08:10:09.65#ibcon#about to read 6, iclass 33, count 0 2006.169.08:10:09.65#ibcon#read 6, iclass 33, count 0 2006.169.08:10:09.65#ibcon#end of sib2, iclass 33, count 0 2006.169.08:10:09.65#ibcon#*after write, iclass 33, count 0 2006.169.08:10:09.65#ibcon#*before return 0, iclass 33, count 0 2006.169.08:10:09.65#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:10:09.65#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:10:09.65#ibcon#about to clear, iclass 33 cls_cnt 0 2006.169.08:10:09.65#ibcon#cleared, iclass 33 cls_cnt 0 2006.169.08:10:09.65$4f8m12a/ifd4f 2006.169.08:10:09.65$ifd4f/lo= 2006.169.08:10:09.65$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.08:10:09.65$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.08:10:09.65$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.08:10:09.65$ifd4f/patch= 2006.169.08:10:09.65$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.08:10:09.65$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.08:10:09.65$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.08:10:09.65$4f8m12a/"form=m,16.000,1:2 2006.169.08:10:09.65$4f8m12a/"tpicd 2006.169.08:10:09.65$4f8m12a/echo=off 2006.169.08:10:09.65$4f8m12a/xlog=off 2006.169.08:10:09.65:!2006.169.08:10:20 2006.169.08:10:20.00:preob 2006.169.08:10:21.14/onsource/TRACKING 2006.169.08:10:21.14:!2006.169.08:10:30 2006.169.08:10:30.00:data_valid=on 2006.169.08:10:30.00:midob 2006.169.08:10:30.14/onsource/TRACKING 2006.169.08:10:30.14/wx/18.13,1003.8,100 2006.169.08:10:30.30/cable/+6.5299E-03 2006.169.08:10:31.39/va/01,08,usb,yes,43,46 2006.169.08:10:31.39/va/02,07,usb,yes,44,46 2006.169.08:10:31.39/va/03,06,usb,yes,47,47 2006.169.08:10:31.39/va/04,07,usb,yes,45,49 2006.169.08:10:31.39/va/05,07,usb,yes,49,52 2006.169.08:10:31.39/va/06,06,usb,yes,49,48 2006.169.08:10:31.39/va/07,06,usb,yes,49,49 2006.169.08:10:31.39/va/08,07,usb,yes,47,46 2006.169.08:10:31.62/valo/01,532.99,yes,locked 2006.169.08:10:31.62/valo/02,572.99,yes,locked 2006.169.08:10:31.62/valo/03,672.99,yes,locked 2006.169.08:10:31.62/valo/04,832.99,yes,locked 2006.169.08:10:31.62/valo/05,652.99,yes,locked 2006.169.08:10:31.62/valo/06,772.99,yes,locked 2006.169.08:10:31.62/valo/07,832.99,yes,locked 2006.169.08:10:31.62/valo/08,852.99,yes,locked 2006.169.08:10:32.71/vb/01,04,usb,yes,30,28 2006.169.08:10:32.71/vb/02,04,usb,yes,31,33 2006.169.08:10:32.71/vb/03,04,usb,yes,28,31 2006.169.08:10:32.71/vb/04,04,usb,yes,29,29 2006.169.08:10:32.71/vb/05,04,usb,yes,27,31 2006.169.08:10:32.71/vb/06,04,usb,yes,28,31 2006.169.08:10:32.71/vb/07,04,usb,yes,30,30 2006.169.08:10:32.71/vb/08,04,usb,yes,28,31 2006.169.08:10:32.94/vblo/01,632.99,yes,locked 2006.169.08:10:32.94/vblo/02,640.99,yes,locked 2006.169.08:10:32.94/vblo/03,656.99,yes,locked 2006.169.08:10:32.94/vblo/04,712.99,yes,locked 2006.169.08:10:32.94/vblo/05,744.99,yes,locked 2006.169.08:10:32.94/vblo/06,752.99,yes,locked 2006.169.08:10:32.94/vblo/07,734.99,yes,locked 2006.169.08:10:32.94/vblo/08,744.99,yes,locked 2006.169.08:10:33.09/vabw/8 2006.169.08:10:33.24/vbbw/8 2006.169.08:10:33.33/xfe/off,on,15.2 2006.169.08:10:33.73/ifatt/23,28,28,28 2006.169.08:10:34.07/fmout-gps/S +4.17E-07 2006.169.08:10:34.15:!2006.169.08:11:30 2006.169.08:11:30.00:data_valid=off 2006.169.08:11:30.00:postob 2006.169.08:11:30.18/cable/+6.5293E-03 2006.169.08:11:30.18/wx/18.14,1003.8,100 2006.169.08:11:31.08/fmout-gps/S +4.18E-07 2006.169.08:11:31.08:scan_name=169-0812,k06169,60 2006.169.08:11:31.08:source=0748+126,075052.05,123104.8,2000.0,ccw 2006.169.08:11:31.13#flagr#flagr/antenna,new-source 2006.169.08:11:32.13:checkk5 2006.169.08:11:32.50/chk_autoobs//k5ts1/ autoobs is running! 2006.169.08:11:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.169.08:11:36.91/chk_autoobs//k5ts3?ERROR: timeout happened! 2006.169.08:11:37.29/chk_autoobs//k5ts4/ autoobs is running! 2006.169.08:11:37.65/chk_obsdata//k5ts1/T1690810??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.169.08:11:38.02/chk_obsdata//k5ts2/T1690810??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.169.08:11:45.05/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.08:11:45.42/chk_obsdata//k5ts4/T1690810??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.169.08:11:46.11/k5log//k5ts1_log_newline 2006.169.08:11:46.80/k5log//k5ts2_log_newline 2006.169.08:11:47.13#trakl#Source acquired 2006.169.08:11:49.13#flagr#flagr/antenna,acquired 2006.169.08:11:53.90/k5log//k5ts3?ERROR: timeout happened! 2006.169.08:11:54.59/k5log//k5ts4_log_newline 2006.169.08:11:54.75/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.08:11:54.75:4f8m12a=2 2006.169.08:11:54.75$4f8m12a/echo=on 2006.169.08:11:54.75$4f8m12a/pcalon 2006.169.08:11:54.75$pcalon/"no phase cal control is implemented here 2006.169.08:11:54.75$4f8m12a/"tpicd=stop 2006.169.08:11:54.75$4f8m12a/vc4f8 2006.169.08:11:54.75$vc4f8/valo=1,532.99 2006.169.08:11:54.76#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.169.08:11:54.76#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.169.08:11:54.76#ibcon#ireg 17 cls_cnt 0 2006.169.08:11:54.76#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:11:54.76#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:11:54.76#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:11:54.76#ibcon#enter wrdev, iclass 40, count 0 2006.169.08:11:54.76#ibcon#first serial, iclass 40, count 0 2006.169.08:11:54.76#ibcon#enter sib2, iclass 40, count 0 2006.169.08:11:54.76#ibcon#flushed, iclass 40, count 0 2006.169.08:11:54.76#ibcon#about to write, iclass 40, count 0 2006.169.08:11:54.76#ibcon#wrote, iclass 40, count 0 2006.169.08:11:54.76#ibcon#about to read 3, iclass 40, count 0 2006.169.08:11:54.78#ibcon#read 3, iclass 40, count 0 2006.169.08:11:54.78#ibcon#about to read 4, iclass 40, count 0 2006.169.08:11:54.78#ibcon#read 4, iclass 40, count 0 2006.169.08:11:54.78#ibcon#about to read 5, iclass 40, count 0 2006.169.08:11:54.78#ibcon#read 5, iclass 40, count 0 2006.169.08:11:54.78#ibcon#about to read 6, iclass 40, count 0 2006.169.08:11:54.78#ibcon#read 6, iclass 40, count 0 2006.169.08:11:54.78#ibcon#end of sib2, iclass 40, count 0 2006.169.08:11:54.78#ibcon#*mode == 0, iclass 40, count 0 2006.169.08:11:54.78#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.169.08:11:54.78#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.08:11:54.78#ibcon#*before write, iclass 40, count 0 2006.169.08:11:54.78#ibcon#enter sib2, iclass 40, count 0 2006.169.08:11:54.78#ibcon#flushed, iclass 40, count 0 2006.169.08:11:54.78#ibcon#about to write, iclass 40, count 0 2006.169.08:11:54.78#ibcon#wrote, iclass 40, count 0 2006.169.08:11:54.78#ibcon#about to read 3, iclass 40, count 0 2006.169.08:11:54.83#ibcon#read 3, iclass 40, count 0 2006.169.08:11:54.83#ibcon#about to read 4, iclass 40, count 0 2006.169.08:11:54.83#ibcon#read 4, iclass 40, count 0 2006.169.08:11:54.83#ibcon#about to read 5, iclass 40, count 0 2006.169.08:11:54.83#ibcon#read 5, iclass 40, count 0 2006.169.08:11:54.83#ibcon#about to read 6, iclass 40, count 0 2006.169.08:11:54.83#ibcon#read 6, iclass 40, count 0 2006.169.08:11:54.83#ibcon#end of sib2, iclass 40, count 0 2006.169.08:11:54.83#ibcon#*after write, iclass 40, count 0 2006.169.08:11:54.83#ibcon#*before return 0, iclass 40, count 0 2006.169.08:11:54.83#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:11:54.83#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:11:54.83#ibcon#about to clear, iclass 40 cls_cnt 0 2006.169.08:11:54.83#ibcon#cleared, iclass 40 cls_cnt 0 2006.169.08:11:54.83$vc4f8/va=1,8 2006.169.08:11:54.83#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.169.08:11:54.83#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.169.08:11:54.83#ibcon#ireg 11 cls_cnt 2 2006.169.08:11:54.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:11:54.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:11:54.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:11:54.83#ibcon#enter wrdev, iclass 4, count 2 2006.169.08:11:54.83#ibcon#first serial, iclass 4, count 2 2006.169.08:11:54.83#ibcon#enter sib2, iclass 4, count 2 2006.169.08:11:54.83#ibcon#flushed, iclass 4, count 2 2006.169.08:11:54.83#ibcon#about to write, iclass 4, count 2 2006.169.08:11:54.83#ibcon#wrote, iclass 4, count 2 2006.169.08:11:54.83#ibcon#about to read 3, iclass 4, count 2 2006.169.08:11:54.85#ibcon#read 3, iclass 4, count 2 2006.169.08:11:54.85#ibcon#about to read 4, iclass 4, count 2 2006.169.08:11:54.85#ibcon#read 4, iclass 4, count 2 2006.169.08:11:54.85#ibcon#about to read 5, iclass 4, count 2 2006.169.08:11:54.85#ibcon#read 5, iclass 4, count 2 2006.169.08:11:54.85#ibcon#about to read 6, iclass 4, count 2 2006.169.08:11:54.85#ibcon#read 6, iclass 4, count 2 2006.169.08:11:54.85#ibcon#end of sib2, iclass 4, count 2 2006.169.08:11:54.85#ibcon#*mode == 0, iclass 4, count 2 2006.169.08:11:54.85#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.169.08:11:54.85#ibcon#[25=AT01-08\r\n] 2006.169.08:11:54.85#ibcon#*before write, iclass 4, count 2 2006.169.08:11:54.85#ibcon#enter sib2, iclass 4, count 2 2006.169.08:11:54.85#ibcon#flushed, iclass 4, count 2 2006.169.08:11:54.85#ibcon#about to write, iclass 4, count 2 2006.169.08:11:54.85#ibcon#wrote, iclass 4, count 2 2006.169.08:11:54.85#ibcon#about to read 3, iclass 4, count 2 2006.169.08:11:54.88#ibcon#read 3, iclass 4, count 2 2006.169.08:11:54.88#ibcon#about to read 4, iclass 4, count 2 2006.169.08:11:54.88#ibcon#read 4, iclass 4, count 2 2006.169.08:11:54.88#ibcon#about to read 5, iclass 4, count 2 2006.169.08:11:54.88#ibcon#read 5, iclass 4, count 2 2006.169.08:11:54.88#ibcon#about to read 6, iclass 4, count 2 2006.169.08:11:54.88#ibcon#read 6, iclass 4, count 2 2006.169.08:11:54.88#ibcon#end of sib2, iclass 4, count 2 2006.169.08:11:54.88#ibcon#*after write, iclass 4, count 2 2006.169.08:11:54.88#ibcon#*before return 0, iclass 4, count 2 2006.169.08:11:54.88#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:11:54.88#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:11:54.88#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.169.08:11:54.88#ibcon#ireg 7 cls_cnt 0 2006.169.08:11:54.88#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:11:55.00#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:11:55.00#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:11:55.00#ibcon#enter wrdev, iclass 4, count 0 2006.169.08:11:55.00#ibcon#first serial, iclass 4, count 0 2006.169.08:11:55.00#ibcon#enter sib2, iclass 4, count 0 2006.169.08:11:55.00#ibcon#flushed, iclass 4, count 0 2006.169.08:11:55.00#ibcon#about to write, iclass 4, count 0 2006.169.08:11:55.00#ibcon#wrote, iclass 4, count 0 2006.169.08:11:55.00#ibcon#about to read 3, iclass 4, count 0 2006.169.08:11:55.02#ibcon#read 3, iclass 4, count 0 2006.169.08:11:55.02#ibcon#about to read 4, iclass 4, count 0 2006.169.08:11:55.02#ibcon#read 4, iclass 4, count 0 2006.169.08:11:55.02#ibcon#about to read 5, iclass 4, count 0 2006.169.08:11:55.02#ibcon#read 5, iclass 4, count 0 2006.169.08:11:55.02#ibcon#about to read 6, iclass 4, count 0 2006.169.08:11:55.02#ibcon#read 6, iclass 4, count 0 2006.169.08:11:55.02#ibcon#end of sib2, iclass 4, count 0 2006.169.08:11:55.02#ibcon#*mode == 0, iclass 4, count 0 2006.169.08:11:55.02#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.169.08:11:55.02#ibcon#[25=USB\r\n] 2006.169.08:11:55.02#ibcon#*before write, iclass 4, count 0 2006.169.08:11:55.02#ibcon#enter sib2, iclass 4, count 0 2006.169.08:11:55.02#ibcon#flushed, iclass 4, count 0 2006.169.08:11:55.02#ibcon#about to write, iclass 4, count 0 2006.169.08:11:55.02#ibcon#wrote, iclass 4, count 0 2006.169.08:11:55.02#ibcon#about to read 3, iclass 4, count 0 2006.169.08:11:55.05#ibcon#read 3, iclass 4, count 0 2006.169.08:11:55.05#ibcon#about to read 4, iclass 4, count 0 2006.169.08:11:55.05#ibcon#read 4, iclass 4, count 0 2006.169.08:11:55.05#ibcon#about to read 5, iclass 4, count 0 2006.169.08:11:55.05#ibcon#read 5, iclass 4, count 0 2006.169.08:11:55.05#ibcon#about to read 6, iclass 4, count 0 2006.169.08:11:55.05#ibcon#read 6, iclass 4, count 0 2006.169.08:11:55.05#ibcon#end of sib2, iclass 4, count 0 2006.169.08:11:55.05#ibcon#*after write, iclass 4, count 0 2006.169.08:11:55.05#ibcon#*before return 0, iclass 4, count 0 2006.169.08:11:55.05#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:11:55.05#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:11:55.05#ibcon#about to clear, iclass 4 cls_cnt 0 2006.169.08:11:55.05#ibcon#cleared, iclass 4 cls_cnt 0 2006.169.08:11:55.05$vc4f8/valo=2,572.99 2006.169.08:11:55.05#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.169.08:11:55.05#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.169.08:11:55.05#ibcon#ireg 17 cls_cnt 0 2006.169.08:11:55.05#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:11:55.05#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:11:55.05#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:11:55.05#ibcon#enter wrdev, iclass 6, count 0 2006.169.08:11:55.05#ibcon#first serial, iclass 6, count 0 2006.169.08:11:55.05#ibcon#enter sib2, iclass 6, count 0 2006.169.08:11:55.05#ibcon#flushed, iclass 6, count 0 2006.169.08:11:55.05#ibcon#about to write, iclass 6, count 0 2006.169.08:11:55.05#ibcon#wrote, iclass 6, count 0 2006.169.08:11:55.05#ibcon#about to read 3, iclass 6, count 0 2006.169.08:11:55.07#ibcon#read 3, iclass 6, count 0 2006.169.08:11:55.07#ibcon#about to read 4, iclass 6, count 0 2006.169.08:11:55.07#ibcon#read 4, iclass 6, count 0 2006.169.08:11:55.07#ibcon#about to read 5, iclass 6, count 0 2006.169.08:11:55.07#ibcon#read 5, iclass 6, count 0 2006.169.08:11:55.07#ibcon#about to read 6, iclass 6, count 0 2006.169.08:11:55.07#ibcon#read 6, iclass 6, count 0 2006.169.08:11:55.07#ibcon#end of sib2, iclass 6, count 0 2006.169.08:11:55.07#ibcon#*mode == 0, iclass 6, count 0 2006.169.08:11:55.07#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.169.08:11:55.07#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.08:11:55.07#ibcon#*before write, iclass 6, count 0 2006.169.08:11:55.07#ibcon#enter sib2, iclass 6, count 0 2006.169.08:11:55.07#ibcon#flushed, iclass 6, count 0 2006.169.08:11:55.07#ibcon#about to write, iclass 6, count 0 2006.169.08:11:55.07#ibcon#wrote, iclass 6, count 0 2006.169.08:11:55.07#ibcon#about to read 3, iclass 6, count 0 2006.169.08:11:55.11#ibcon#read 3, iclass 6, count 0 2006.169.08:11:55.11#ibcon#about to read 4, iclass 6, count 0 2006.169.08:11:55.11#ibcon#read 4, iclass 6, count 0 2006.169.08:11:55.11#ibcon#about to read 5, iclass 6, count 0 2006.169.08:11:55.11#ibcon#read 5, iclass 6, count 0 2006.169.08:11:55.11#ibcon#about to read 6, iclass 6, count 0 2006.169.08:11:55.11#ibcon#read 6, iclass 6, count 0 2006.169.08:11:55.11#ibcon#end of sib2, iclass 6, count 0 2006.169.08:11:55.11#ibcon#*after write, iclass 6, count 0 2006.169.08:11:55.11#ibcon#*before return 0, iclass 6, count 0 2006.169.08:11:55.11#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:11:55.11#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:11:55.11#ibcon#about to clear, iclass 6 cls_cnt 0 2006.169.08:11:55.11#ibcon#cleared, iclass 6 cls_cnt 0 2006.169.08:11:55.11$vc4f8/va=2,7 2006.169.08:11:55.11#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.169.08:11:55.11#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.169.08:11:55.11#ibcon#ireg 11 cls_cnt 2 2006.169.08:11:55.11#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:11:55.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:11:55.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:11:55.17#ibcon#enter wrdev, iclass 10, count 2 2006.169.08:11:55.17#ibcon#first serial, iclass 10, count 2 2006.169.08:11:55.17#ibcon#enter sib2, iclass 10, count 2 2006.169.08:11:55.17#ibcon#flushed, iclass 10, count 2 2006.169.08:11:55.17#ibcon#about to write, iclass 10, count 2 2006.169.08:11:55.17#ibcon#wrote, iclass 10, count 2 2006.169.08:11:55.17#ibcon#about to read 3, iclass 10, count 2 2006.169.08:11:55.19#ibcon#read 3, iclass 10, count 2 2006.169.08:11:55.19#ibcon#about to read 4, iclass 10, count 2 2006.169.08:11:55.19#ibcon#read 4, iclass 10, count 2 2006.169.08:11:55.19#ibcon#about to read 5, iclass 10, count 2 2006.169.08:11:55.19#ibcon#read 5, iclass 10, count 2 2006.169.08:11:55.19#ibcon#about to read 6, iclass 10, count 2 2006.169.08:11:55.19#ibcon#read 6, iclass 10, count 2 2006.169.08:11:55.19#ibcon#end of sib2, iclass 10, count 2 2006.169.08:11:55.19#ibcon#*mode == 0, iclass 10, count 2 2006.169.08:11:55.19#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.169.08:11:55.19#ibcon#[25=AT02-07\r\n] 2006.169.08:11:55.19#ibcon#*before write, iclass 10, count 2 2006.169.08:11:55.19#ibcon#enter sib2, iclass 10, count 2 2006.169.08:11:55.19#ibcon#flushed, iclass 10, count 2 2006.169.08:11:55.19#ibcon#about to write, iclass 10, count 2 2006.169.08:11:55.19#ibcon#wrote, iclass 10, count 2 2006.169.08:11:55.19#ibcon#about to read 3, iclass 10, count 2 2006.169.08:11:55.22#ibcon#read 3, iclass 10, count 2 2006.169.08:11:55.22#ibcon#about to read 4, iclass 10, count 2 2006.169.08:11:55.22#ibcon#read 4, iclass 10, count 2 2006.169.08:11:55.22#ibcon#about to read 5, iclass 10, count 2 2006.169.08:11:55.22#ibcon#read 5, iclass 10, count 2 2006.169.08:11:55.22#ibcon#about to read 6, iclass 10, count 2 2006.169.08:11:55.22#ibcon#read 6, iclass 10, count 2 2006.169.08:11:55.22#ibcon#end of sib2, iclass 10, count 2 2006.169.08:11:55.22#ibcon#*after write, iclass 10, count 2 2006.169.08:11:55.22#ibcon#*before return 0, iclass 10, count 2 2006.169.08:11:55.22#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:11:55.22#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:11:55.22#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.169.08:11:55.22#ibcon#ireg 7 cls_cnt 0 2006.169.08:11:55.22#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:11:55.34#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:11:55.34#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:11:55.34#ibcon#enter wrdev, iclass 10, count 0 2006.169.08:11:55.34#ibcon#first serial, iclass 10, count 0 2006.169.08:11:55.34#ibcon#enter sib2, iclass 10, count 0 2006.169.08:11:55.34#ibcon#flushed, iclass 10, count 0 2006.169.08:11:55.34#ibcon#about to write, iclass 10, count 0 2006.169.08:11:55.34#ibcon#wrote, iclass 10, count 0 2006.169.08:11:55.34#ibcon#about to read 3, iclass 10, count 0 2006.169.08:11:55.36#ibcon#read 3, iclass 10, count 0 2006.169.08:11:55.36#ibcon#about to read 4, iclass 10, count 0 2006.169.08:11:55.36#ibcon#read 4, iclass 10, count 0 2006.169.08:11:55.36#ibcon#about to read 5, iclass 10, count 0 2006.169.08:11:55.36#ibcon#read 5, iclass 10, count 0 2006.169.08:11:55.36#ibcon#about to read 6, iclass 10, count 0 2006.169.08:11:55.36#ibcon#read 6, iclass 10, count 0 2006.169.08:11:55.36#ibcon#end of sib2, iclass 10, count 0 2006.169.08:11:55.36#ibcon#*mode == 0, iclass 10, count 0 2006.169.08:11:55.36#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.169.08:11:55.36#ibcon#[25=USB\r\n] 2006.169.08:11:55.36#ibcon#*before write, iclass 10, count 0 2006.169.08:11:55.36#ibcon#enter sib2, iclass 10, count 0 2006.169.08:11:55.36#ibcon#flushed, iclass 10, count 0 2006.169.08:11:55.36#ibcon#about to write, iclass 10, count 0 2006.169.08:11:55.36#ibcon#wrote, iclass 10, count 0 2006.169.08:11:55.36#ibcon#about to read 3, iclass 10, count 0 2006.169.08:11:55.39#ibcon#read 3, iclass 10, count 0 2006.169.08:11:55.39#ibcon#about to read 4, iclass 10, count 0 2006.169.08:11:55.39#ibcon#read 4, iclass 10, count 0 2006.169.08:11:55.39#ibcon#about to read 5, iclass 10, count 0 2006.169.08:11:55.39#ibcon#read 5, iclass 10, count 0 2006.169.08:11:55.39#ibcon#about to read 6, iclass 10, count 0 2006.169.08:11:55.39#ibcon#read 6, iclass 10, count 0 2006.169.08:11:55.39#ibcon#end of sib2, iclass 10, count 0 2006.169.08:11:55.39#ibcon#*after write, iclass 10, count 0 2006.169.08:11:55.39#ibcon#*before return 0, iclass 10, count 0 2006.169.08:11:55.39#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:11:55.39#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:11:55.39#ibcon#about to clear, iclass 10 cls_cnt 0 2006.169.08:11:55.39#ibcon#cleared, iclass 10 cls_cnt 0 2006.169.08:11:55.39$vc4f8/valo=3,672.99 2006.169.08:11:55.39#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.169.08:11:55.39#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.169.08:11:55.39#ibcon#ireg 17 cls_cnt 0 2006.169.08:11:55.39#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:11:55.39#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:11:55.39#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:11:55.39#ibcon#enter wrdev, iclass 12, count 0 2006.169.08:11:55.39#ibcon#first serial, iclass 12, count 0 2006.169.08:11:55.39#ibcon#enter sib2, iclass 12, count 0 2006.169.08:11:55.39#ibcon#flushed, iclass 12, count 0 2006.169.08:11:55.39#ibcon#about to write, iclass 12, count 0 2006.169.08:11:55.39#ibcon#wrote, iclass 12, count 0 2006.169.08:11:55.39#ibcon#about to read 3, iclass 12, count 0 2006.169.08:11:55.41#ibcon#read 3, iclass 12, count 0 2006.169.08:11:55.41#ibcon#about to read 4, iclass 12, count 0 2006.169.08:11:55.41#ibcon#read 4, iclass 12, count 0 2006.169.08:11:55.41#ibcon#about to read 5, iclass 12, count 0 2006.169.08:11:55.41#ibcon#read 5, iclass 12, count 0 2006.169.08:11:55.41#ibcon#about to read 6, iclass 12, count 0 2006.169.08:11:55.41#ibcon#read 6, iclass 12, count 0 2006.169.08:11:55.41#ibcon#end of sib2, iclass 12, count 0 2006.169.08:11:55.41#ibcon#*mode == 0, iclass 12, count 0 2006.169.08:11:55.41#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.169.08:11:55.41#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.08:11:55.41#ibcon#*before write, iclass 12, count 0 2006.169.08:11:55.41#ibcon#enter sib2, iclass 12, count 0 2006.169.08:11:55.41#ibcon#flushed, iclass 12, count 0 2006.169.08:11:55.41#ibcon#about to write, iclass 12, count 0 2006.169.08:11:55.41#ibcon#wrote, iclass 12, count 0 2006.169.08:11:55.41#ibcon#about to read 3, iclass 12, count 0 2006.169.08:11:55.45#ibcon#read 3, iclass 12, count 0 2006.169.08:11:55.45#ibcon#about to read 4, iclass 12, count 0 2006.169.08:11:55.45#ibcon#read 4, iclass 12, count 0 2006.169.08:11:55.45#ibcon#about to read 5, iclass 12, count 0 2006.169.08:11:55.45#ibcon#read 5, iclass 12, count 0 2006.169.08:11:55.45#ibcon#about to read 6, iclass 12, count 0 2006.169.08:11:55.45#ibcon#read 6, iclass 12, count 0 2006.169.08:11:55.45#ibcon#end of sib2, iclass 12, count 0 2006.169.08:11:55.45#ibcon#*after write, iclass 12, count 0 2006.169.08:11:55.45#ibcon#*before return 0, iclass 12, count 0 2006.169.08:11:55.45#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:11:55.45#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:11:55.45#ibcon#about to clear, iclass 12 cls_cnt 0 2006.169.08:11:55.45#ibcon#cleared, iclass 12 cls_cnt 0 2006.169.08:11:55.45$vc4f8/va=3,6 2006.169.08:11:55.45#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.169.08:11:55.45#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.169.08:11:55.45#ibcon#ireg 11 cls_cnt 2 2006.169.08:11:55.45#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.169.08:11:55.51#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.169.08:11:55.51#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.169.08:11:55.51#ibcon#enter wrdev, iclass 14, count 2 2006.169.08:11:55.51#ibcon#first serial, iclass 14, count 2 2006.169.08:11:55.51#ibcon#enter sib2, iclass 14, count 2 2006.169.08:11:55.51#ibcon#flushed, iclass 14, count 2 2006.169.08:11:55.51#ibcon#about to write, iclass 14, count 2 2006.169.08:11:55.51#ibcon#wrote, iclass 14, count 2 2006.169.08:11:55.51#ibcon#about to read 3, iclass 14, count 2 2006.169.08:11:55.53#ibcon#read 3, iclass 14, count 2 2006.169.08:11:55.53#ibcon#about to read 4, iclass 14, count 2 2006.169.08:11:55.53#ibcon#read 4, iclass 14, count 2 2006.169.08:11:55.53#ibcon#about to read 5, iclass 14, count 2 2006.169.08:11:55.53#ibcon#read 5, iclass 14, count 2 2006.169.08:11:55.53#ibcon#about to read 6, iclass 14, count 2 2006.169.08:11:55.53#ibcon#read 6, iclass 14, count 2 2006.169.08:11:55.53#ibcon#end of sib2, iclass 14, count 2 2006.169.08:11:55.53#ibcon#*mode == 0, iclass 14, count 2 2006.169.08:11:55.53#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.169.08:11:55.53#ibcon#[25=AT03-06\r\n] 2006.169.08:11:55.53#ibcon#*before write, iclass 14, count 2 2006.169.08:11:55.53#ibcon#enter sib2, iclass 14, count 2 2006.169.08:11:55.53#ibcon#flushed, iclass 14, count 2 2006.169.08:11:55.53#ibcon#about to write, iclass 14, count 2 2006.169.08:11:55.53#ibcon#wrote, iclass 14, count 2 2006.169.08:11:55.53#ibcon#about to read 3, iclass 14, count 2 2006.169.08:11:55.56#ibcon#read 3, iclass 14, count 2 2006.169.08:11:55.56#ibcon#about to read 4, iclass 14, count 2 2006.169.08:11:55.56#ibcon#read 4, iclass 14, count 2 2006.169.08:11:55.56#ibcon#about to read 5, iclass 14, count 2 2006.169.08:11:55.56#ibcon#read 5, iclass 14, count 2 2006.169.08:11:55.56#ibcon#about to read 6, iclass 14, count 2 2006.169.08:11:55.56#ibcon#read 6, iclass 14, count 2 2006.169.08:11:55.56#ibcon#end of sib2, iclass 14, count 2 2006.169.08:11:55.56#ibcon#*after write, iclass 14, count 2 2006.169.08:11:55.56#ibcon#*before return 0, iclass 14, count 2 2006.169.08:11:55.56#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.169.08:11:55.56#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.169.08:11:55.56#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.169.08:11:55.56#ibcon#ireg 7 cls_cnt 0 2006.169.08:11:55.56#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.169.08:11:55.68#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.169.08:11:55.68#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.169.08:11:55.68#ibcon#enter wrdev, iclass 14, count 0 2006.169.08:11:55.68#ibcon#first serial, iclass 14, count 0 2006.169.08:11:55.68#ibcon#enter sib2, iclass 14, count 0 2006.169.08:11:55.68#ibcon#flushed, iclass 14, count 0 2006.169.08:11:55.68#ibcon#about to write, iclass 14, count 0 2006.169.08:11:55.68#ibcon#wrote, iclass 14, count 0 2006.169.08:11:55.68#ibcon#about to read 3, iclass 14, count 0 2006.169.08:11:55.70#ibcon#read 3, iclass 14, count 0 2006.169.08:11:55.70#ibcon#about to read 4, iclass 14, count 0 2006.169.08:11:55.70#ibcon#read 4, iclass 14, count 0 2006.169.08:11:55.70#ibcon#about to read 5, iclass 14, count 0 2006.169.08:11:55.70#ibcon#read 5, iclass 14, count 0 2006.169.08:11:55.70#ibcon#about to read 6, iclass 14, count 0 2006.169.08:11:55.70#ibcon#read 6, iclass 14, count 0 2006.169.08:11:55.70#ibcon#end of sib2, iclass 14, count 0 2006.169.08:11:55.70#ibcon#*mode == 0, iclass 14, count 0 2006.169.08:11:55.70#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.169.08:11:55.70#ibcon#[25=USB\r\n] 2006.169.08:11:55.70#ibcon#*before write, iclass 14, count 0 2006.169.08:11:55.70#ibcon#enter sib2, iclass 14, count 0 2006.169.08:11:55.70#ibcon#flushed, iclass 14, count 0 2006.169.08:11:55.70#ibcon#about to write, iclass 14, count 0 2006.169.08:11:55.70#ibcon#wrote, iclass 14, count 0 2006.169.08:11:55.70#ibcon#about to read 3, iclass 14, count 0 2006.169.08:11:55.73#ibcon#read 3, iclass 14, count 0 2006.169.08:11:55.73#ibcon#about to read 4, iclass 14, count 0 2006.169.08:11:55.73#ibcon#read 4, iclass 14, count 0 2006.169.08:11:55.73#ibcon#about to read 5, iclass 14, count 0 2006.169.08:11:55.73#ibcon#read 5, iclass 14, count 0 2006.169.08:11:55.73#ibcon#about to read 6, iclass 14, count 0 2006.169.08:11:55.73#ibcon#read 6, iclass 14, count 0 2006.169.08:11:55.73#ibcon#end of sib2, iclass 14, count 0 2006.169.08:11:55.73#ibcon#*after write, iclass 14, count 0 2006.169.08:11:55.73#ibcon#*before return 0, iclass 14, count 0 2006.169.08:11:55.73#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.169.08:11:55.73#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.169.08:11:55.73#ibcon#about to clear, iclass 14 cls_cnt 0 2006.169.08:11:55.73#ibcon#cleared, iclass 14 cls_cnt 0 2006.169.08:11:55.73$vc4f8/valo=4,832.99 2006.169.08:11:55.73#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.169.08:11:55.73#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.169.08:11:55.73#ibcon#ireg 17 cls_cnt 0 2006.169.08:11:55.73#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:11:55.73#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:11:55.73#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:11:55.73#ibcon#enter wrdev, iclass 16, count 0 2006.169.08:11:55.73#ibcon#first serial, iclass 16, count 0 2006.169.08:11:55.73#ibcon#enter sib2, iclass 16, count 0 2006.169.08:11:55.73#ibcon#flushed, iclass 16, count 0 2006.169.08:11:55.73#ibcon#about to write, iclass 16, count 0 2006.169.08:11:55.73#ibcon#wrote, iclass 16, count 0 2006.169.08:11:55.73#ibcon#about to read 3, iclass 16, count 0 2006.169.08:11:55.75#ibcon#read 3, iclass 16, count 0 2006.169.08:11:55.75#ibcon#about to read 4, iclass 16, count 0 2006.169.08:11:55.75#ibcon#read 4, iclass 16, count 0 2006.169.08:11:55.75#ibcon#about to read 5, iclass 16, count 0 2006.169.08:11:55.75#ibcon#read 5, iclass 16, count 0 2006.169.08:11:55.75#ibcon#about to read 6, iclass 16, count 0 2006.169.08:11:55.75#ibcon#read 6, iclass 16, count 0 2006.169.08:11:55.75#ibcon#end of sib2, iclass 16, count 0 2006.169.08:11:55.75#ibcon#*mode == 0, iclass 16, count 0 2006.169.08:11:55.75#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.169.08:11:55.75#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.08:11:55.75#ibcon#*before write, iclass 16, count 0 2006.169.08:11:55.75#ibcon#enter sib2, iclass 16, count 0 2006.169.08:11:55.75#ibcon#flushed, iclass 16, count 0 2006.169.08:11:55.75#ibcon#about to write, iclass 16, count 0 2006.169.08:11:55.75#ibcon#wrote, iclass 16, count 0 2006.169.08:11:55.75#ibcon#about to read 3, iclass 16, count 0 2006.169.08:11:55.79#ibcon#read 3, iclass 16, count 0 2006.169.08:11:55.79#ibcon#about to read 4, iclass 16, count 0 2006.169.08:11:55.79#ibcon#read 4, iclass 16, count 0 2006.169.08:11:55.79#ibcon#about to read 5, iclass 16, count 0 2006.169.08:11:55.79#ibcon#read 5, iclass 16, count 0 2006.169.08:11:55.79#ibcon#about to read 6, iclass 16, count 0 2006.169.08:11:55.79#ibcon#read 6, iclass 16, count 0 2006.169.08:11:55.79#ibcon#end of sib2, iclass 16, count 0 2006.169.08:11:55.79#ibcon#*after write, iclass 16, count 0 2006.169.08:11:55.79#ibcon#*before return 0, iclass 16, count 0 2006.169.08:11:55.79#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:11:55.79#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:11:55.79#ibcon#about to clear, iclass 16 cls_cnt 0 2006.169.08:11:55.79#ibcon#cleared, iclass 16 cls_cnt 0 2006.169.08:11:55.79$vc4f8/va=4,7 2006.169.08:11:55.79#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.169.08:11:55.79#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.169.08:11:55.79#ibcon#ireg 11 cls_cnt 2 2006.169.08:11:55.79#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.169.08:11:55.85#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.169.08:11:55.85#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.169.08:11:55.85#ibcon#enter wrdev, iclass 18, count 2 2006.169.08:11:55.85#ibcon#first serial, iclass 18, count 2 2006.169.08:11:55.85#ibcon#enter sib2, iclass 18, count 2 2006.169.08:11:55.85#ibcon#flushed, iclass 18, count 2 2006.169.08:11:55.85#ibcon#about to write, iclass 18, count 2 2006.169.08:11:55.85#ibcon#wrote, iclass 18, count 2 2006.169.08:11:55.85#ibcon#about to read 3, iclass 18, count 2 2006.169.08:11:55.87#ibcon#read 3, iclass 18, count 2 2006.169.08:11:55.87#ibcon#about to read 4, iclass 18, count 2 2006.169.08:11:55.87#ibcon#read 4, iclass 18, count 2 2006.169.08:11:55.87#ibcon#about to read 5, iclass 18, count 2 2006.169.08:11:55.87#ibcon#read 5, iclass 18, count 2 2006.169.08:11:55.87#ibcon#about to read 6, iclass 18, count 2 2006.169.08:11:55.87#ibcon#read 6, iclass 18, count 2 2006.169.08:11:55.87#ibcon#end of sib2, iclass 18, count 2 2006.169.08:11:55.87#ibcon#*mode == 0, iclass 18, count 2 2006.169.08:11:55.87#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.169.08:11:55.87#ibcon#[25=AT04-07\r\n] 2006.169.08:11:55.87#ibcon#*before write, iclass 18, count 2 2006.169.08:11:55.87#ibcon#enter sib2, iclass 18, count 2 2006.169.08:11:55.87#ibcon#flushed, iclass 18, count 2 2006.169.08:11:55.87#ibcon#about to write, iclass 18, count 2 2006.169.08:11:55.87#ibcon#wrote, iclass 18, count 2 2006.169.08:11:55.87#ibcon#about to read 3, iclass 18, count 2 2006.169.08:11:55.90#ibcon#read 3, iclass 18, count 2 2006.169.08:11:55.90#ibcon#about to read 4, iclass 18, count 2 2006.169.08:11:55.90#ibcon#read 4, iclass 18, count 2 2006.169.08:11:55.90#ibcon#about to read 5, iclass 18, count 2 2006.169.08:11:55.90#ibcon#read 5, iclass 18, count 2 2006.169.08:11:55.90#ibcon#about to read 6, iclass 18, count 2 2006.169.08:11:55.90#ibcon#read 6, iclass 18, count 2 2006.169.08:11:55.90#ibcon#end of sib2, iclass 18, count 2 2006.169.08:11:55.90#ibcon#*after write, iclass 18, count 2 2006.169.08:11:55.90#ibcon#*before return 0, iclass 18, count 2 2006.169.08:11:55.90#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.169.08:11:55.90#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.169.08:11:55.90#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.169.08:11:55.90#ibcon#ireg 7 cls_cnt 0 2006.169.08:11:55.90#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.169.08:11:56.02#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.169.08:11:56.02#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.169.08:11:56.02#ibcon#enter wrdev, iclass 18, count 0 2006.169.08:11:56.02#ibcon#first serial, iclass 18, count 0 2006.169.08:11:56.02#ibcon#enter sib2, iclass 18, count 0 2006.169.08:11:56.02#ibcon#flushed, iclass 18, count 0 2006.169.08:11:56.02#ibcon#about to write, iclass 18, count 0 2006.169.08:11:56.02#ibcon#wrote, iclass 18, count 0 2006.169.08:11:56.02#ibcon#about to read 3, iclass 18, count 0 2006.169.08:11:56.04#ibcon#read 3, iclass 18, count 0 2006.169.08:11:56.04#ibcon#about to read 4, iclass 18, count 0 2006.169.08:11:56.04#ibcon#read 4, iclass 18, count 0 2006.169.08:11:56.04#ibcon#about to read 5, iclass 18, count 0 2006.169.08:11:56.04#ibcon#read 5, iclass 18, count 0 2006.169.08:11:56.04#ibcon#about to read 6, iclass 18, count 0 2006.169.08:11:56.04#ibcon#read 6, iclass 18, count 0 2006.169.08:11:56.04#ibcon#end of sib2, iclass 18, count 0 2006.169.08:11:56.04#ibcon#*mode == 0, iclass 18, count 0 2006.169.08:11:56.04#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.169.08:11:56.04#ibcon#[25=USB\r\n] 2006.169.08:11:56.04#ibcon#*before write, iclass 18, count 0 2006.169.08:11:56.04#ibcon#enter sib2, iclass 18, count 0 2006.169.08:11:56.04#ibcon#flushed, iclass 18, count 0 2006.169.08:11:56.04#ibcon#about to write, iclass 18, count 0 2006.169.08:11:56.04#ibcon#wrote, iclass 18, count 0 2006.169.08:11:56.04#ibcon#about to read 3, iclass 18, count 0 2006.169.08:11:56.07#ibcon#read 3, iclass 18, count 0 2006.169.08:11:56.07#ibcon#about to read 4, iclass 18, count 0 2006.169.08:11:56.07#ibcon#read 4, iclass 18, count 0 2006.169.08:11:56.07#ibcon#about to read 5, iclass 18, count 0 2006.169.08:11:56.07#ibcon#read 5, iclass 18, count 0 2006.169.08:11:56.07#ibcon#about to read 6, iclass 18, count 0 2006.169.08:11:56.07#ibcon#read 6, iclass 18, count 0 2006.169.08:11:56.07#ibcon#end of sib2, iclass 18, count 0 2006.169.08:11:56.07#ibcon#*after write, iclass 18, count 0 2006.169.08:11:56.07#ibcon#*before return 0, iclass 18, count 0 2006.169.08:11:56.07#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.169.08:11:56.07#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.169.08:11:56.07#ibcon#about to clear, iclass 18 cls_cnt 0 2006.169.08:11:56.07#ibcon#cleared, iclass 18 cls_cnt 0 2006.169.08:11:56.07$vc4f8/valo=5,652.99 2006.169.08:11:56.07#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.169.08:11:56.07#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.169.08:11:56.07#ibcon#ireg 17 cls_cnt 0 2006.169.08:11:56.07#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:11:56.07#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:11:56.07#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:11:56.07#ibcon#enter wrdev, iclass 20, count 0 2006.169.08:11:56.07#ibcon#first serial, iclass 20, count 0 2006.169.08:11:56.07#ibcon#enter sib2, iclass 20, count 0 2006.169.08:11:56.07#ibcon#flushed, iclass 20, count 0 2006.169.08:11:56.07#ibcon#about to write, iclass 20, count 0 2006.169.08:11:56.07#ibcon#wrote, iclass 20, count 0 2006.169.08:11:56.07#ibcon#about to read 3, iclass 20, count 0 2006.169.08:11:56.09#ibcon#read 3, iclass 20, count 0 2006.169.08:11:56.09#ibcon#about to read 4, iclass 20, count 0 2006.169.08:11:56.09#ibcon#read 4, iclass 20, count 0 2006.169.08:11:56.09#ibcon#about to read 5, iclass 20, count 0 2006.169.08:11:56.09#ibcon#read 5, iclass 20, count 0 2006.169.08:11:56.09#ibcon#about to read 6, iclass 20, count 0 2006.169.08:11:56.09#ibcon#read 6, iclass 20, count 0 2006.169.08:11:56.09#ibcon#end of sib2, iclass 20, count 0 2006.169.08:11:56.09#ibcon#*mode == 0, iclass 20, count 0 2006.169.08:11:56.09#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.169.08:11:56.09#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.08:11:56.09#ibcon#*before write, iclass 20, count 0 2006.169.08:11:56.09#ibcon#enter sib2, iclass 20, count 0 2006.169.08:11:56.09#ibcon#flushed, iclass 20, count 0 2006.169.08:11:56.09#ibcon#about to write, iclass 20, count 0 2006.169.08:11:56.09#ibcon#wrote, iclass 20, count 0 2006.169.08:11:56.09#ibcon#about to read 3, iclass 20, count 0 2006.169.08:11:56.13#ibcon#read 3, iclass 20, count 0 2006.169.08:11:56.13#ibcon#about to read 4, iclass 20, count 0 2006.169.08:11:56.13#ibcon#read 4, iclass 20, count 0 2006.169.08:11:56.13#ibcon#about to read 5, iclass 20, count 0 2006.169.08:11:56.13#ibcon#read 5, iclass 20, count 0 2006.169.08:11:56.13#ibcon#about to read 6, iclass 20, count 0 2006.169.08:11:56.13#ibcon#read 6, iclass 20, count 0 2006.169.08:11:56.13#ibcon#end of sib2, iclass 20, count 0 2006.169.08:11:56.13#ibcon#*after write, iclass 20, count 0 2006.169.08:11:56.13#ibcon#*before return 0, iclass 20, count 0 2006.169.08:11:56.13#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:11:56.13#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:11:56.13#ibcon#about to clear, iclass 20 cls_cnt 0 2006.169.08:11:56.13#ibcon#cleared, iclass 20 cls_cnt 0 2006.169.08:11:56.13$vc4f8/va=5,7 2006.169.08:11:56.13#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.169.08:11:56.13#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.169.08:11:56.13#ibcon#ireg 11 cls_cnt 2 2006.169.08:11:56.13#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:11:56.19#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:11:56.19#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:11:56.19#ibcon#enter wrdev, iclass 22, count 2 2006.169.08:11:56.19#ibcon#first serial, iclass 22, count 2 2006.169.08:11:56.19#ibcon#enter sib2, iclass 22, count 2 2006.169.08:11:56.19#ibcon#flushed, iclass 22, count 2 2006.169.08:11:56.19#ibcon#about to write, iclass 22, count 2 2006.169.08:11:56.19#ibcon#wrote, iclass 22, count 2 2006.169.08:11:56.19#ibcon#about to read 3, iclass 22, count 2 2006.169.08:11:56.21#ibcon#read 3, iclass 22, count 2 2006.169.08:11:56.21#ibcon#about to read 4, iclass 22, count 2 2006.169.08:11:56.21#ibcon#read 4, iclass 22, count 2 2006.169.08:11:56.21#ibcon#about to read 5, iclass 22, count 2 2006.169.08:11:56.21#ibcon#read 5, iclass 22, count 2 2006.169.08:11:56.21#ibcon#about to read 6, iclass 22, count 2 2006.169.08:11:56.21#ibcon#read 6, iclass 22, count 2 2006.169.08:11:56.21#ibcon#end of sib2, iclass 22, count 2 2006.169.08:11:56.21#ibcon#*mode == 0, iclass 22, count 2 2006.169.08:11:56.21#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.169.08:11:56.21#ibcon#[25=AT05-07\r\n] 2006.169.08:11:56.21#ibcon#*before write, iclass 22, count 2 2006.169.08:11:56.21#ibcon#enter sib2, iclass 22, count 2 2006.169.08:11:56.21#ibcon#flushed, iclass 22, count 2 2006.169.08:11:56.21#ibcon#about to write, iclass 22, count 2 2006.169.08:11:56.21#ibcon#wrote, iclass 22, count 2 2006.169.08:11:56.21#ibcon#about to read 3, iclass 22, count 2 2006.169.08:11:56.24#ibcon#read 3, iclass 22, count 2 2006.169.08:11:56.24#ibcon#about to read 4, iclass 22, count 2 2006.169.08:11:56.24#ibcon#read 4, iclass 22, count 2 2006.169.08:11:56.24#ibcon#about to read 5, iclass 22, count 2 2006.169.08:11:56.24#ibcon#read 5, iclass 22, count 2 2006.169.08:11:56.24#ibcon#about to read 6, iclass 22, count 2 2006.169.08:11:56.24#ibcon#read 6, iclass 22, count 2 2006.169.08:11:56.24#ibcon#end of sib2, iclass 22, count 2 2006.169.08:11:56.24#ibcon#*after write, iclass 22, count 2 2006.169.08:11:56.24#ibcon#*before return 0, iclass 22, count 2 2006.169.08:11:56.24#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:11:56.24#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:11:56.24#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.169.08:11:56.24#ibcon#ireg 7 cls_cnt 0 2006.169.08:11:56.24#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:11:56.36#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:11:56.36#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:11:56.36#ibcon#enter wrdev, iclass 22, count 0 2006.169.08:11:56.36#ibcon#first serial, iclass 22, count 0 2006.169.08:11:56.36#ibcon#enter sib2, iclass 22, count 0 2006.169.08:11:56.36#ibcon#flushed, iclass 22, count 0 2006.169.08:11:56.36#ibcon#about to write, iclass 22, count 0 2006.169.08:11:56.36#ibcon#wrote, iclass 22, count 0 2006.169.08:11:56.36#ibcon#about to read 3, iclass 22, count 0 2006.169.08:11:56.38#ibcon#read 3, iclass 22, count 0 2006.169.08:11:56.38#ibcon#about to read 4, iclass 22, count 0 2006.169.08:11:56.38#ibcon#read 4, iclass 22, count 0 2006.169.08:11:56.38#ibcon#about to read 5, iclass 22, count 0 2006.169.08:11:56.38#ibcon#read 5, iclass 22, count 0 2006.169.08:11:56.38#ibcon#about to read 6, iclass 22, count 0 2006.169.08:11:56.38#ibcon#read 6, iclass 22, count 0 2006.169.08:11:56.38#ibcon#end of sib2, iclass 22, count 0 2006.169.08:11:56.38#ibcon#*mode == 0, iclass 22, count 0 2006.169.08:11:56.38#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.169.08:11:56.38#ibcon#[25=USB\r\n] 2006.169.08:11:56.38#ibcon#*before write, iclass 22, count 0 2006.169.08:11:56.38#ibcon#enter sib2, iclass 22, count 0 2006.169.08:11:56.38#ibcon#flushed, iclass 22, count 0 2006.169.08:11:56.38#ibcon#about to write, iclass 22, count 0 2006.169.08:11:56.38#ibcon#wrote, iclass 22, count 0 2006.169.08:11:56.38#ibcon#about to read 3, iclass 22, count 0 2006.169.08:11:56.41#ibcon#read 3, iclass 22, count 0 2006.169.08:11:56.41#ibcon#about to read 4, iclass 22, count 0 2006.169.08:11:56.41#ibcon#read 4, iclass 22, count 0 2006.169.08:11:56.41#ibcon#about to read 5, iclass 22, count 0 2006.169.08:11:56.41#ibcon#read 5, iclass 22, count 0 2006.169.08:11:56.41#ibcon#about to read 6, iclass 22, count 0 2006.169.08:11:56.41#ibcon#read 6, iclass 22, count 0 2006.169.08:11:56.41#ibcon#end of sib2, iclass 22, count 0 2006.169.08:11:56.41#ibcon#*after write, iclass 22, count 0 2006.169.08:11:56.41#ibcon#*before return 0, iclass 22, count 0 2006.169.08:11:56.41#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:11:56.41#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:11:56.41#ibcon#about to clear, iclass 22 cls_cnt 0 2006.169.08:11:56.41#ibcon#cleared, iclass 22 cls_cnt 0 2006.169.08:11:56.41$vc4f8/valo=6,772.99 2006.169.08:11:56.41#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.169.08:11:56.41#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.169.08:11:56.41#ibcon#ireg 17 cls_cnt 0 2006.169.08:11:56.41#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:11:56.41#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:11:56.41#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:11:56.41#ibcon#enter wrdev, iclass 24, count 0 2006.169.08:11:56.41#ibcon#first serial, iclass 24, count 0 2006.169.08:11:56.41#ibcon#enter sib2, iclass 24, count 0 2006.169.08:11:56.41#ibcon#flushed, iclass 24, count 0 2006.169.08:11:56.41#ibcon#about to write, iclass 24, count 0 2006.169.08:11:56.41#ibcon#wrote, iclass 24, count 0 2006.169.08:11:56.41#ibcon#about to read 3, iclass 24, count 0 2006.169.08:11:56.43#ibcon#read 3, iclass 24, count 0 2006.169.08:11:56.43#ibcon#about to read 4, iclass 24, count 0 2006.169.08:11:56.43#ibcon#read 4, iclass 24, count 0 2006.169.08:11:56.43#ibcon#about to read 5, iclass 24, count 0 2006.169.08:11:56.43#ibcon#read 5, iclass 24, count 0 2006.169.08:11:56.43#ibcon#about to read 6, iclass 24, count 0 2006.169.08:11:56.43#ibcon#read 6, iclass 24, count 0 2006.169.08:11:56.43#ibcon#end of sib2, iclass 24, count 0 2006.169.08:11:56.43#ibcon#*mode == 0, iclass 24, count 0 2006.169.08:11:56.43#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.169.08:11:56.43#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.08:11:56.43#ibcon#*before write, iclass 24, count 0 2006.169.08:11:56.43#ibcon#enter sib2, iclass 24, count 0 2006.169.08:11:56.43#ibcon#flushed, iclass 24, count 0 2006.169.08:11:56.43#ibcon#about to write, iclass 24, count 0 2006.169.08:11:56.43#ibcon#wrote, iclass 24, count 0 2006.169.08:11:56.43#ibcon#about to read 3, iclass 24, count 0 2006.169.08:11:56.47#ibcon#read 3, iclass 24, count 0 2006.169.08:11:56.47#ibcon#about to read 4, iclass 24, count 0 2006.169.08:11:56.47#ibcon#read 4, iclass 24, count 0 2006.169.08:11:56.47#ibcon#about to read 5, iclass 24, count 0 2006.169.08:11:56.47#ibcon#read 5, iclass 24, count 0 2006.169.08:11:56.47#ibcon#about to read 6, iclass 24, count 0 2006.169.08:11:56.47#ibcon#read 6, iclass 24, count 0 2006.169.08:11:56.47#ibcon#end of sib2, iclass 24, count 0 2006.169.08:11:56.47#ibcon#*after write, iclass 24, count 0 2006.169.08:11:56.47#ibcon#*before return 0, iclass 24, count 0 2006.169.08:11:56.47#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:11:56.47#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:11:56.47#ibcon#about to clear, iclass 24 cls_cnt 0 2006.169.08:11:56.47#ibcon#cleared, iclass 24 cls_cnt 0 2006.169.08:11:56.47$vc4f8/va=6,6 2006.169.08:11:56.47#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.169.08:11:56.47#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.169.08:11:56.47#ibcon#ireg 11 cls_cnt 2 2006.169.08:11:56.47#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.169.08:11:56.53#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.169.08:11:56.53#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.169.08:11:56.53#ibcon#enter wrdev, iclass 26, count 2 2006.169.08:11:56.53#ibcon#first serial, iclass 26, count 2 2006.169.08:11:56.53#ibcon#enter sib2, iclass 26, count 2 2006.169.08:11:56.53#ibcon#flushed, iclass 26, count 2 2006.169.08:11:56.53#ibcon#about to write, iclass 26, count 2 2006.169.08:11:56.53#ibcon#wrote, iclass 26, count 2 2006.169.08:11:56.53#ibcon#about to read 3, iclass 26, count 2 2006.169.08:11:56.55#ibcon#read 3, iclass 26, count 2 2006.169.08:11:56.55#ibcon#about to read 4, iclass 26, count 2 2006.169.08:11:56.55#ibcon#read 4, iclass 26, count 2 2006.169.08:11:56.55#ibcon#about to read 5, iclass 26, count 2 2006.169.08:11:56.55#ibcon#read 5, iclass 26, count 2 2006.169.08:11:56.55#ibcon#about to read 6, iclass 26, count 2 2006.169.08:11:56.55#ibcon#read 6, iclass 26, count 2 2006.169.08:11:56.55#ibcon#end of sib2, iclass 26, count 2 2006.169.08:11:56.55#ibcon#*mode == 0, iclass 26, count 2 2006.169.08:11:56.55#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.169.08:11:56.55#ibcon#[25=AT06-06\r\n] 2006.169.08:11:56.55#ibcon#*before write, iclass 26, count 2 2006.169.08:11:56.55#ibcon#enter sib2, iclass 26, count 2 2006.169.08:11:56.55#ibcon#flushed, iclass 26, count 2 2006.169.08:11:56.55#ibcon#about to write, iclass 26, count 2 2006.169.08:11:56.55#ibcon#wrote, iclass 26, count 2 2006.169.08:11:56.55#ibcon#about to read 3, iclass 26, count 2 2006.169.08:11:56.58#ibcon#read 3, iclass 26, count 2 2006.169.08:11:56.58#ibcon#about to read 4, iclass 26, count 2 2006.169.08:11:56.58#ibcon#read 4, iclass 26, count 2 2006.169.08:11:56.58#ibcon#about to read 5, iclass 26, count 2 2006.169.08:11:56.58#ibcon#read 5, iclass 26, count 2 2006.169.08:11:56.58#ibcon#about to read 6, iclass 26, count 2 2006.169.08:11:56.58#ibcon#read 6, iclass 26, count 2 2006.169.08:11:56.58#ibcon#end of sib2, iclass 26, count 2 2006.169.08:11:56.58#ibcon#*after write, iclass 26, count 2 2006.169.08:11:56.58#ibcon#*before return 0, iclass 26, count 2 2006.169.08:11:56.58#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.169.08:11:56.58#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.169.08:11:56.58#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.169.08:11:56.58#ibcon#ireg 7 cls_cnt 0 2006.169.08:11:56.58#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.169.08:11:56.70#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.169.08:11:56.70#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.169.08:11:56.70#ibcon#enter wrdev, iclass 26, count 0 2006.169.08:11:56.70#ibcon#first serial, iclass 26, count 0 2006.169.08:11:56.70#ibcon#enter sib2, iclass 26, count 0 2006.169.08:11:56.70#ibcon#flushed, iclass 26, count 0 2006.169.08:11:56.70#ibcon#about to write, iclass 26, count 0 2006.169.08:11:56.70#ibcon#wrote, iclass 26, count 0 2006.169.08:11:56.70#ibcon#about to read 3, iclass 26, count 0 2006.169.08:11:56.72#ibcon#read 3, iclass 26, count 0 2006.169.08:11:56.72#ibcon#about to read 4, iclass 26, count 0 2006.169.08:11:56.72#ibcon#read 4, iclass 26, count 0 2006.169.08:11:56.72#ibcon#about to read 5, iclass 26, count 0 2006.169.08:11:56.72#ibcon#read 5, iclass 26, count 0 2006.169.08:11:56.72#ibcon#about to read 6, iclass 26, count 0 2006.169.08:11:56.72#ibcon#read 6, iclass 26, count 0 2006.169.08:11:56.72#ibcon#end of sib2, iclass 26, count 0 2006.169.08:11:56.72#ibcon#*mode == 0, iclass 26, count 0 2006.169.08:11:56.72#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.169.08:11:56.72#ibcon#[25=USB\r\n] 2006.169.08:11:56.72#ibcon#*before write, iclass 26, count 0 2006.169.08:11:56.72#ibcon#enter sib2, iclass 26, count 0 2006.169.08:11:56.72#ibcon#flushed, iclass 26, count 0 2006.169.08:11:56.72#ibcon#about to write, iclass 26, count 0 2006.169.08:11:56.72#ibcon#wrote, iclass 26, count 0 2006.169.08:11:56.72#ibcon#about to read 3, iclass 26, count 0 2006.169.08:11:56.75#ibcon#read 3, iclass 26, count 0 2006.169.08:11:56.75#ibcon#about to read 4, iclass 26, count 0 2006.169.08:11:56.75#ibcon#read 4, iclass 26, count 0 2006.169.08:11:56.75#ibcon#about to read 5, iclass 26, count 0 2006.169.08:11:56.75#ibcon#read 5, iclass 26, count 0 2006.169.08:11:56.75#ibcon#about to read 6, iclass 26, count 0 2006.169.08:11:56.75#ibcon#read 6, iclass 26, count 0 2006.169.08:11:56.75#ibcon#end of sib2, iclass 26, count 0 2006.169.08:11:56.75#ibcon#*after write, iclass 26, count 0 2006.169.08:11:56.75#ibcon#*before return 0, iclass 26, count 0 2006.169.08:11:56.75#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.169.08:11:56.75#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.169.08:11:56.75#ibcon#about to clear, iclass 26 cls_cnt 0 2006.169.08:11:56.75#ibcon#cleared, iclass 26 cls_cnt 0 2006.169.08:11:56.75$vc4f8/valo=7,832.99 2006.169.08:11:56.75#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.169.08:11:56.75#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.169.08:11:56.75#ibcon#ireg 17 cls_cnt 0 2006.169.08:11:56.75#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:11:56.75#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:11:56.75#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:11:56.75#ibcon#enter wrdev, iclass 28, count 0 2006.169.08:11:56.75#ibcon#first serial, iclass 28, count 0 2006.169.08:11:56.75#ibcon#enter sib2, iclass 28, count 0 2006.169.08:11:56.75#ibcon#flushed, iclass 28, count 0 2006.169.08:11:56.75#ibcon#about to write, iclass 28, count 0 2006.169.08:11:56.75#ibcon#wrote, iclass 28, count 0 2006.169.08:11:56.75#ibcon#about to read 3, iclass 28, count 0 2006.169.08:11:56.77#ibcon#read 3, iclass 28, count 0 2006.169.08:11:56.77#ibcon#about to read 4, iclass 28, count 0 2006.169.08:11:56.77#ibcon#read 4, iclass 28, count 0 2006.169.08:11:56.77#ibcon#about to read 5, iclass 28, count 0 2006.169.08:11:56.77#ibcon#read 5, iclass 28, count 0 2006.169.08:11:56.77#ibcon#about to read 6, iclass 28, count 0 2006.169.08:11:56.77#ibcon#read 6, iclass 28, count 0 2006.169.08:11:56.77#ibcon#end of sib2, iclass 28, count 0 2006.169.08:11:56.77#ibcon#*mode == 0, iclass 28, count 0 2006.169.08:11:56.77#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.169.08:11:56.77#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.08:11:56.77#ibcon#*before write, iclass 28, count 0 2006.169.08:11:56.77#ibcon#enter sib2, iclass 28, count 0 2006.169.08:11:56.77#ibcon#flushed, iclass 28, count 0 2006.169.08:11:56.77#ibcon#about to write, iclass 28, count 0 2006.169.08:11:56.77#ibcon#wrote, iclass 28, count 0 2006.169.08:11:56.77#ibcon#about to read 3, iclass 28, count 0 2006.169.08:11:56.81#ibcon#read 3, iclass 28, count 0 2006.169.08:11:56.81#ibcon#about to read 4, iclass 28, count 0 2006.169.08:11:56.81#ibcon#read 4, iclass 28, count 0 2006.169.08:11:56.81#ibcon#about to read 5, iclass 28, count 0 2006.169.08:11:56.81#ibcon#read 5, iclass 28, count 0 2006.169.08:11:56.81#ibcon#about to read 6, iclass 28, count 0 2006.169.08:11:56.81#ibcon#read 6, iclass 28, count 0 2006.169.08:11:56.81#ibcon#end of sib2, iclass 28, count 0 2006.169.08:11:56.81#ibcon#*after write, iclass 28, count 0 2006.169.08:11:56.81#ibcon#*before return 0, iclass 28, count 0 2006.169.08:11:56.81#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:11:56.81#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:11:56.81#ibcon#about to clear, iclass 28 cls_cnt 0 2006.169.08:11:56.81#ibcon#cleared, iclass 28 cls_cnt 0 2006.169.08:11:56.81$vc4f8/va=7,6 2006.169.08:11:56.81#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.169.08:11:56.81#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.169.08:11:56.81#ibcon#ireg 11 cls_cnt 2 2006.169.08:11:56.81#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:11:56.87#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:11:56.87#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:11:56.87#ibcon#enter wrdev, iclass 30, count 2 2006.169.08:11:56.87#ibcon#first serial, iclass 30, count 2 2006.169.08:11:56.87#ibcon#enter sib2, iclass 30, count 2 2006.169.08:11:56.87#ibcon#flushed, iclass 30, count 2 2006.169.08:11:56.87#ibcon#about to write, iclass 30, count 2 2006.169.08:11:56.87#ibcon#wrote, iclass 30, count 2 2006.169.08:11:56.87#ibcon#about to read 3, iclass 30, count 2 2006.169.08:11:56.89#ibcon#read 3, iclass 30, count 2 2006.169.08:11:56.89#ibcon#about to read 4, iclass 30, count 2 2006.169.08:11:56.89#ibcon#read 4, iclass 30, count 2 2006.169.08:11:56.89#ibcon#about to read 5, iclass 30, count 2 2006.169.08:11:56.89#ibcon#read 5, iclass 30, count 2 2006.169.08:11:56.89#ibcon#about to read 6, iclass 30, count 2 2006.169.08:11:56.89#ibcon#read 6, iclass 30, count 2 2006.169.08:11:56.89#ibcon#end of sib2, iclass 30, count 2 2006.169.08:11:56.89#ibcon#*mode == 0, iclass 30, count 2 2006.169.08:11:56.89#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.169.08:11:56.89#ibcon#[25=AT07-06\r\n] 2006.169.08:11:56.89#ibcon#*before write, iclass 30, count 2 2006.169.08:11:56.89#ibcon#enter sib2, iclass 30, count 2 2006.169.08:11:56.89#ibcon#flushed, iclass 30, count 2 2006.169.08:11:56.89#ibcon#about to write, iclass 30, count 2 2006.169.08:11:56.89#ibcon#wrote, iclass 30, count 2 2006.169.08:11:56.89#ibcon#about to read 3, iclass 30, count 2 2006.169.08:11:56.92#ibcon#read 3, iclass 30, count 2 2006.169.08:11:56.92#ibcon#about to read 4, iclass 30, count 2 2006.169.08:11:56.92#ibcon#read 4, iclass 30, count 2 2006.169.08:11:56.92#ibcon#about to read 5, iclass 30, count 2 2006.169.08:11:56.92#ibcon#read 5, iclass 30, count 2 2006.169.08:11:56.92#ibcon#about to read 6, iclass 30, count 2 2006.169.08:11:56.92#ibcon#read 6, iclass 30, count 2 2006.169.08:11:56.92#ibcon#end of sib2, iclass 30, count 2 2006.169.08:11:56.92#ibcon#*after write, iclass 30, count 2 2006.169.08:11:56.92#ibcon#*before return 0, iclass 30, count 2 2006.169.08:11:56.92#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:11:56.92#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:11:56.92#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.169.08:11:56.92#ibcon#ireg 7 cls_cnt 0 2006.169.08:11:56.92#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:11:57.04#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:11:57.04#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:11:57.04#ibcon#enter wrdev, iclass 30, count 0 2006.169.08:11:57.04#ibcon#first serial, iclass 30, count 0 2006.169.08:11:57.04#ibcon#enter sib2, iclass 30, count 0 2006.169.08:11:57.04#ibcon#flushed, iclass 30, count 0 2006.169.08:11:57.04#ibcon#about to write, iclass 30, count 0 2006.169.08:11:57.04#ibcon#wrote, iclass 30, count 0 2006.169.08:11:57.04#ibcon#about to read 3, iclass 30, count 0 2006.169.08:11:57.06#ibcon#read 3, iclass 30, count 0 2006.169.08:11:57.06#ibcon#about to read 4, iclass 30, count 0 2006.169.08:11:57.06#ibcon#read 4, iclass 30, count 0 2006.169.08:11:57.06#ibcon#about to read 5, iclass 30, count 0 2006.169.08:11:57.06#ibcon#read 5, iclass 30, count 0 2006.169.08:11:57.06#ibcon#about to read 6, iclass 30, count 0 2006.169.08:11:57.06#ibcon#read 6, iclass 30, count 0 2006.169.08:11:57.06#ibcon#end of sib2, iclass 30, count 0 2006.169.08:11:57.06#ibcon#*mode == 0, iclass 30, count 0 2006.169.08:11:57.06#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.169.08:11:57.06#ibcon#[25=USB\r\n] 2006.169.08:11:57.06#ibcon#*before write, iclass 30, count 0 2006.169.08:11:57.06#ibcon#enter sib2, iclass 30, count 0 2006.169.08:11:57.06#ibcon#flushed, iclass 30, count 0 2006.169.08:11:57.06#ibcon#about to write, iclass 30, count 0 2006.169.08:11:57.06#ibcon#wrote, iclass 30, count 0 2006.169.08:11:57.06#ibcon#about to read 3, iclass 30, count 0 2006.169.08:11:57.09#ibcon#read 3, iclass 30, count 0 2006.169.08:11:57.09#ibcon#about to read 4, iclass 30, count 0 2006.169.08:11:57.09#ibcon#read 4, iclass 30, count 0 2006.169.08:11:57.09#ibcon#about to read 5, iclass 30, count 0 2006.169.08:11:57.09#ibcon#read 5, iclass 30, count 0 2006.169.08:11:57.09#ibcon#about to read 6, iclass 30, count 0 2006.169.08:11:57.09#ibcon#read 6, iclass 30, count 0 2006.169.08:11:57.09#ibcon#end of sib2, iclass 30, count 0 2006.169.08:11:57.09#ibcon#*after write, iclass 30, count 0 2006.169.08:11:57.09#ibcon#*before return 0, iclass 30, count 0 2006.169.08:11:57.09#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:11:57.09#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:11:57.09#ibcon#about to clear, iclass 30 cls_cnt 0 2006.169.08:11:57.09#ibcon#cleared, iclass 30 cls_cnt 0 2006.169.08:11:57.09$vc4f8/valo=8,852.99 2006.169.08:11:57.09#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.169.08:11:57.09#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.169.08:11:57.09#ibcon#ireg 17 cls_cnt 0 2006.169.08:11:57.09#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:11:57.09#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:11:57.09#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:11:57.09#ibcon#enter wrdev, iclass 32, count 0 2006.169.08:11:57.09#ibcon#first serial, iclass 32, count 0 2006.169.08:11:57.09#ibcon#enter sib2, iclass 32, count 0 2006.169.08:11:57.09#ibcon#flushed, iclass 32, count 0 2006.169.08:11:57.09#ibcon#about to write, iclass 32, count 0 2006.169.08:11:57.09#ibcon#wrote, iclass 32, count 0 2006.169.08:11:57.09#ibcon#about to read 3, iclass 32, count 0 2006.169.08:11:57.11#ibcon#read 3, iclass 32, count 0 2006.169.08:11:57.11#ibcon#about to read 4, iclass 32, count 0 2006.169.08:11:57.11#ibcon#read 4, iclass 32, count 0 2006.169.08:11:57.11#ibcon#about to read 5, iclass 32, count 0 2006.169.08:11:57.11#ibcon#read 5, iclass 32, count 0 2006.169.08:11:57.11#ibcon#about to read 6, iclass 32, count 0 2006.169.08:11:57.11#ibcon#read 6, iclass 32, count 0 2006.169.08:11:57.11#ibcon#end of sib2, iclass 32, count 0 2006.169.08:11:57.11#ibcon#*mode == 0, iclass 32, count 0 2006.169.08:11:57.11#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.169.08:11:57.11#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.08:11:57.11#ibcon#*before write, iclass 32, count 0 2006.169.08:11:57.11#ibcon#enter sib2, iclass 32, count 0 2006.169.08:11:57.11#ibcon#flushed, iclass 32, count 0 2006.169.08:11:57.11#ibcon#about to write, iclass 32, count 0 2006.169.08:11:57.11#ibcon#wrote, iclass 32, count 0 2006.169.08:11:57.11#ibcon#about to read 3, iclass 32, count 0 2006.169.08:11:57.15#ibcon#read 3, iclass 32, count 0 2006.169.08:11:57.15#ibcon#about to read 4, iclass 32, count 0 2006.169.08:11:57.15#ibcon#read 4, iclass 32, count 0 2006.169.08:11:57.15#ibcon#about to read 5, iclass 32, count 0 2006.169.08:11:57.15#ibcon#read 5, iclass 32, count 0 2006.169.08:11:57.15#ibcon#about to read 6, iclass 32, count 0 2006.169.08:11:57.15#ibcon#read 6, iclass 32, count 0 2006.169.08:11:57.15#ibcon#end of sib2, iclass 32, count 0 2006.169.08:11:57.15#ibcon#*after write, iclass 32, count 0 2006.169.08:11:57.15#ibcon#*before return 0, iclass 32, count 0 2006.169.08:11:57.15#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:11:57.15#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:11:57.15#ibcon#about to clear, iclass 32 cls_cnt 0 2006.169.08:11:57.15#ibcon#cleared, iclass 32 cls_cnt 0 2006.169.08:11:57.15$vc4f8/va=8,7 2006.169.08:11:57.15#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.169.08:11:57.15#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.169.08:11:57.15#ibcon#ireg 11 cls_cnt 2 2006.169.08:11:57.15#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:11:57.21#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:11:57.21#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:11:57.21#ibcon#enter wrdev, iclass 34, count 2 2006.169.08:11:57.21#ibcon#first serial, iclass 34, count 2 2006.169.08:11:57.21#ibcon#enter sib2, iclass 34, count 2 2006.169.08:11:57.21#ibcon#flushed, iclass 34, count 2 2006.169.08:11:57.21#ibcon#about to write, iclass 34, count 2 2006.169.08:11:57.21#ibcon#wrote, iclass 34, count 2 2006.169.08:11:57.21#ibcon#about to read 3, iclass 34, count 2 2006.169.08:11:57.23#ibcon#read 3, iclass 34, count 2 2006.169.08:11:57.23#ibcon#about to read 4, iclass 34, count 2 2006.169.08:11:57.23#ibcon#read 4, iclass 34, count 2 2006.169.08:11:57.23#ibcon#about to read 5, iclass 34, count 2 2006.169.08:11:57.23#ibcon#read 5, iclass 34, count 2 2006.169.08:11:57.23#ibcon#about to read 6, iclass 34, count 2 2006.169.08:11:57.23#ibcon#read 6, iclass 34, count 2 2006.169.08:11:57.23#ibcon#end of sib2, iclass 34, count 2 2006.169.08:11:57.23#ibcon#*mode == 0, iclass 34, count 2 2006.169.08:11:57.23#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.169.08:11:57.23#ibcon#[25=AT08-07\r\n] 2006.169.08:11:57.23#ibcon#*before write, iclass 34, count 2 2006.169.08:11:57.23#ibcon#enter sib2, iclass 34, count 2 2006.169.08:11:57.23#ibcon#flushed, iclass 34, count 2 2006.169.08:11:57.23#ibcon#about to write, iclass 34, count 2 2006.169.08:11:57.23#ibcon#wrote, iclass 34, count 2 2006.169.08:11:57.23#ibcon#about to read 3, iclass 34, count 2 2006.169.08:11:57.26#ibcon#read 3, iclass 34, count 2 2006.169.08:11:57.26#ibcon#about to read 4, iclass 34, count 2 2006.169.08:11:57.26#ibcon#read 4, iclass 34, count 2 2006.169.08:11:57.26#ibcon#about to read 5, iclass 34, count 2 2006.169.08:11:57.26#ibcon#read 5, iclass 34, count 2 2006.169.08:11:57.26#ibcon#about to read 6, iclass 34, count 2 2006.169.08:11:57.26#ibcon#read 6, iclass 34, count 2 2006.169.08:11:57.26#ibcon#end of sib2, iclass 34, count 2 2006.169.08:11:57.26#ibcon#*after write, iclass 34, count 2 2006.169.08:11:57.26#ibcon#*before return 0, iclass 34, count 2 2006.169.08:11:57.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:11:57.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:11:57.26#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.169.08:11:57.26#ibcon#ireg 7 cls_cnt 0 2006.169.08:11:57.26#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:11:57.38#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:11:57.38#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:11:57.38#ibcon#enter wrdev, iclass 34, count 0 2006.169.08:11:57.38#ibcon#first serial, iclass 34, count 0 2006.169.08:11:57.38#ibcon#enter sib2, iclass 34, count 0 2006.169.08:11:57.38#ibcon#flushed, iclass 34, count 0 2006.169.08:11:57.38#ibcon#about to write, iclass 34, count 0 2006.169.08:11:57.38#ibcon#wrote, iclass 34, count 0 2006.169.08:11:57.38#ibcon#about to read 3, iclass 34, count 0 2006.169.08:11:57.40#ibcon#read 3, iclass 34, count 0 2006.169.08:11:57.40#ibcon#about to read 4, iclass 34, count 0 2006.169.08:11:57.40#ibcon#read 4, iclass 34, count 0 2006.169.08:11:57.40#ibcon#about to read 5, iclass 34, count 0 2006.169.08:11:57.40#ibcon#read 5, iclass 34, count 0 2006.169.08:11:57.40#ibcon#about to read 6, iclass 34, count 0 2006.169.08:11:57.40#ibcon#read 6, iclass 34, count 0 2006.169.08:11:57.40#ibcon#end of sib2, iclass 34, count 0 2006.169.08:11:57.40#ibcon#*mode == 0, iclass 34, count 0 2006.169.08:11:57.40#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.169.08:11:57.40#ibcon#[25=USB\r\n] 2006.169.08:11:57.40#ibcon#*before write, iclass 34, count 0 2006.169.08:11:57.40#ibcon#enter sib2, iclass 34, count 0 2006.169.08:11:57.40#ibcon#flushed, iclass 34, count 0 2006.169.08:11:57.40#ibcon#about to write, iclass 34, count 0 2006.169.08:11:57.40#ibcon#wrote, iclass 34, count 0 2006.169.08:11:57.40#ibcon#about to read 3, iclass 34, count 0 2006.169.08:11:57.43#ibcon#read 3, iclass 34, count 0 2006.169.08:11:57.43#ibcon#about to read 4, iclass 34, count 0 2006.169.08:11:57.43#ibcon#read 4, iclass 34, count 0 2006.169.08:11:57.43#ibcon#about to read 5, iclass 34, count 0 2006.169.08:11:57.43#ibcon#read 5, iclass 34, count 0 2006.169.08:11:57.43#ibcon#about to read 6, iclass 34, count 0 2006.169.08:11:57.43#ibcon#read 6, iclass 34, count 0 2006.169.08:11:57.43#ibcon#end of sib2, iclass 34, count 0 2006.169.08:11:57.43#ibcon#*after write, iclass 34, count 0 2006.169.08:11:57.43#ibcon#*before return 0, iclass 34, count 0 2006.169.08:11:57.43#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:11:57.43#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:11:57.43#ibcon#about to clear, iclass 34 cls_cnt 0 2006.169.08:11:57.43#ibcon#cleared, iclass 34 cls_cnt 0 2006.169.08:11:57.43$vc4f8/vblo=1,632.99 2006.169.08:11:57.43#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.169.08:11:57.43#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.169.08:11:57.43#ibcon#ireg 17 cls_cnt 0 2006.169.08:11:57.43#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:11:57.43#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:11:57.43#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:11:57.43#ibcon#enter wrdev, iclass 36, count 0 2006.169.08:11:57.43#ibcon#first serial, iclass 36, count 0 2006.169.08:11:57.43#ibcon#enter sib2, iclass 36, count 0 2006.169.08:11:57.43#ibcon#flushed, iclass 36, count 0 2006.169.08:11:57.43#ibcon#about to write, iclass 36, count 0 2006.169.08:11:57.43#ibcon#wrote, iclass 36, count 0 2006.169.08:11:57.43#ibcon#about to read 3, iclass 36, count 0 2006.169.08:11:57.45#ibcon#read 3, iclass 36, count 0 2006.169.08:11:57.45#ibcon#about to read 4, iclass 36, count 0 2006.169.08:11:57.45#ibcon#read 4, iclass 36, count 0 2006.169.08:11:57.45#ibcon#about to read 5, iclass 36, count 0 2006.169.08:11:57.45#ibcon#read 5, iclass 36, count 0 2006.169.08:11:57.45#ibcon#about to read 6, iclass 36, count 0 2006.169.08:11:57.45#ibcon#read 6, iclass 36, count 0 2006.169.08:11:57.45#ibcon#end of sib2, iclass 36, count 0 2006.169.08:11:57.45#ibcon#*mode == 0, iclass 36, count 0 2006.169.08:11:57.45#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.169.08:11:57.45#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.08:11:57.45#ibcon#*before write, iclass 36, count 0 2006.169.08:11:57.45#ibcon#enter sib2, iclass 36, count 0 2006.169.08:11:57.45#ibcon#flushed, iclass 36, count 0 2006.169.08:11:57.45#ibcon#about to write, iclass 36, count 0 2006.169.08:11:57.45#ibcon#wrote, iclass 36, count 0 2006.169.08:11:57.45#ibcon#about to read 3, iclass 36, count 0 2006.169.08:11:57.49#ibcon#read 3, iclass 36, count 0 2006.169.08:11:57.49#ibcon#about to read 4, iclass 36, count 0 2006.169.08:11:57.49#ibcon#read 4, iclass 36, count 0 2006.169.08:11:57.49#ibcon#about to read 5, iclass 36, count 0 2006.169.08:11:57.49#ibcon#read 5, iclass 36, count 0 2006.169.08:11:57.49#ibcon#about to read 6, iclass 36, count 0 2006.169.08:11:57.49#ibcon#read 6, iclass 36, count 0 2006.169.08:11:57.49#ibcon#end of sib2, iclass 36, count 0 2006.169.08:11:57.49#ibcon#*after write, iclass 36, count 0 2006.169.08:11:57.49#ibcon#*before return 0, iclass 36, count 0 2006.169.08:11:57.49#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:11:57.49#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:11:57.49#ibcon#about to clear, iclass 36 cls_cnt 0 2006.169.08:11:57.49#ibcon#cleared, iclass 36 cls_cnt 0 2006.169.08:11:57.49$vc4f8/vb=1,4 2006.169.08:11:57.49#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.169.08:11:57.49#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.169.08:11:57.49#ibcon#ireg 11 cls_cnt 2 2006.169.08:11:57.49#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:11:57.49#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:11:57.49#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:11:57.49#ibcon#enter wrdev, iclass 38, count 2 2006.169.08:11:57.49#ibcon#first serial, iclass 38, count 2 2006.169.08:11:57.49#ibcon#enter sib2, iclass 38, count 2 2006.169.08:11:57.49#ibcon#flushed, iclass 38, count 2 2006.169.08:11:57.49#ibcon#about to write, iclass 38, count 2 2006.169.08:11:57.49#ibcon#wrote, iclass 38, count 2 2006.169.08:11:57.49#ibcon#about to read 3, iclass 38, count 2 2006.169.08:11:57.51#ibcon#read 3, iclass 38, count 2 2006.169.08:11:57.51#ibcon#about to read 4, iclass 38, count 2 2006.169.08:11:57.51#ibcon#read 4, iclass 38, count 2 2006.169.08:11:57.51#ibcon#about to read 5, iclass 38, count 2 2006.169.08:11:57.51#ibcon#read 5, iclass 38, count 2 2006.169.08:11:57.51#ibcon#about to read 6, iclass 38, count 2 2006.169.08:11:57.51#ibcon#read 6, iclass 38, count 2 2006.169.08:11:57.51#ibcon#end of sib2, iclass 38, count 2 2006.169.08:11:57.51#ibcon#*mode == 0, iclass 38, count 2 2006.169.08:11:57.51#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.169.08:11:57.51#ibcon#[27=AT01-04\r\n] 2006.169.08:11:57.51#ibcon#*before write, iclass 38, count 2 2006.169.08:11:57.51#ibcon#enter sib2, iclass 38, count 2 2006.169.08:11:57.51#ibcon#flushed, iclass 38, count 2 2006.169.08:11:57.51#ibcon#about to write, iclass 38, count 2 2006.169.08:11:57.51#ibcon#wrote, iclass 38, count 2 2006.169.08:11:57.51#ibcon#about to read 3, iclass 38, count 2 2006.169.08:11:57.54#ibcon#read 3, iclass 38, count 2 2006.169.08:11:57.54#ibcon#about to read 4, iclass 38, count 2 2006.169.08:11:57.54#ibcon#read 4, iclass 38, count 2 2006.169.08:11:57.54#ibcon#about to read 5, iclass 38, count 2 2006.169.08:11:57.54#ibcon#read 5, iclass 38, count 2 2006.169.08:11:57.54#ibcon#about to read 6, iclass 38, count 2 2006.169.08:11:57.54#ibcon#read 6, iclass 38, count 2 2006.169.08:11:57.54#ibcon#end of sib2, iclass 38, count 2 2006.169.08:11:57.54#ibcon#*after write, iclass 38, count 2 2006.169.08:11:57.54#ibcon#*before return 0, iclass 38, count 2 2006.169.08:11:57.54#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:11:57.54#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:11:57.54#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.169.08:11:57.54#ibcon#ireg 7 cls_cnt 0 2006.169.08:11:57.54#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:11:57.66#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:11:57.66#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:11:57.66#ibcon#enter wrdev, iclass 38, count 0 2006.169.08:11:57.66#ibcon#first serial, iclass 38, count 0 2006.169.08:11:57.66#ibcon#enter sib2, iclass 38, count 0 2006.169.08:11:57.66#ibcon#flushed, iclass 38, count 0 2006.169.08:11:57.66#ibcon#about to write, iclass 38, count 0 2006.169.08:11:57.66#ibcon#wrote, iclass 38, count 0 2006.169.08:11:57.66#ibcon#about to read 3, iclass 38, count 0 2006.169.08:11:57.68#ibcon#read 3, iclass 38, count 0 2006.169.08:11:57.68#ibcon#about to read 4, iclass 38, count 0 2006.169.08:11:57.68#ibcon#read 4, iclass 38, count 0 2006.169.08:11:57.68#ibcon#about to read 5, iclass 38, count 0 2006.169.08:11:57.68#ibcon#read 5, iclass 38, count 0 2006.169.08:11:57.68#ibcon#about to read 6, iclass 38, count 0 2006.169.08:11:57.68#ibcon#read 6, iclass 38, count 0 2006.169.08:11:57.68#ibcon#end of sib2, iclass 38, count 0 2006.169.08:11:57.68#ibcon#*mode == 0, iclass 38, count 0 2006.169.08:11:57.68#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.169.08:11:57.68#ibcon#[27=USB\r\n] 2006.169.08:11:57.68#ibcon#*before write, iclass 38, count 0 2006.169.08:11:57.68#ibcon#enter sib2, iclass 38, count 0 2006.169.08:11:57.68#ibcon#flushed, iclass 38, count 0 2006.169.08:11:57.68#ibcon#about to write, iclass 38, count 0 2006.169.08:11:57.68#ibcon#wrote, iclass 38, count 0 2006.169.08:11:57.68#ibcon#about to read 3, iclass 38, count 0 2006.169.08:11:57.71#ibcon#read 3, iclass 38, count 0 2006.169.08:11:57.71#ibcon#about to read 4, iclass 38, count 0 2006.169.08:11:57.71#ibcon#read 4, iclass 38, count 0 2006.169.08:11:57.71#ibcon#about to read 5, iclass 38, count 0 2006.169.08:11:57.71#ibcon#read 5, iclass 38, count 0 2006.169.08:11:57.71#ibcon#about to read 6, iclass 38, count 0 2006.169.08:11:57.71#ibcon#read 6, iclass 38, count 0 2006.169.08:11:57.71#ibcon#end of sib2, iclass 38, count 0 2006.169.08:11:57.71#ibcon#*after write, iclass 38, count 0 2006.169.08:11:57.71#ibcon#*before return 0, iclass 38, count 0 2006.169.08:11:57.71#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:11:57.71#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:11:57.71#ibcon#about to clear, iclass 38 cls_cnt 0 2006.169.08:11:57.71#ibcon#cleared, iclass 38 cls_cnt 0 2006.169.08:11:57.71$vc4f8/vblo=2,640.99 2006.169.08:11:57.71#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.169.08:11:57.71#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.169.08:11:57.71#ibcon#ireg 17 cls_cnt 0 2006.169.08:11:57.71#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:11:57.71#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:11:57.71#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:11:57.71#ibcon#enter wrdev, iclass 40, count 0 2006.169.08:11:57.71#ibcon#first serial, iclass 40, count 0 2006.169.08:11:57.71#ibcon#enter sib2, iclass 40, count 0 2006.169.08:11:57.71#ibcon#flushed, iclass 40, count 0 2006.169.08:11:57.71#ibcon#about to write, iclass 40, count 0 2006.169.08:11:57.71#ibcon#wrote, iclass 40, count 0 2006.169.08:11:57.71#ibcon#about to read 3, iclass 40, count 0 2006.169.08:11:57.73#ibcon#read 3, iclass 40, count 0 2006.169.08:11:57.73#ibcon#about to read 4, iclass 40, count 0 2006.169.08:11:57.73#ibcon#read 4, iclass 40, count 0 2006.169.08:11:57.73#ibcon#about to read 5, iclass 40, count 0 2006.169.08:11:57.73#ibcon#read 5, iclass 40, count 0 2006.169.08:11:57.73#ibcon#about to read 6, iclass 40, count 0 2006.169.08:11:57.73#ibcon#read 6, iclass 40, count 0 2006.169.08:11:57.73#ibcon#end of sib2, iclass 40, count 0 2006.169.08:11:57.73#ibcon#*mode == 0, iclass 40, count 0 2006.169.08:11:57.73#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.169.08:11:57.73#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.08:11:57.73#ibcon#*before write, iclass 40, count 0 2006.169.08:11:57.73#ibcon#enter sib2, iclass 40, count 0 2006.169.08:11:57.73#ibcon#flushed, iclass 40, count 0 2006.169.08:11:57.73#ibcon#about to write, iclass 40, count 0 2006.169.08:11:57.73#ibcon#wrote, iclass 40, count 0 2006.169.08:11:57.73#ibcon#about to read 3, iclass 40, count 0 2006.169.08:11:57.77#ibcon#read 3, iclass 40, count 0 2006.169.08:11:57.77#ibcon#about to read 4, iclass 40, count 0 2006.169.08:11:57.77#ibcon#read 4, iclass 40, count 0 2006.169.08:11:57.77#ibcon#about to read 5, iclass 40, count 0 2006.169.08:11:57.77#ibcon#read 5, iclass 40, count 0 2006.169.08:11:57.77#ibcon#about to read 6, iclass 40, count 0 2006.169.08:11:57.77#ibcon#read 6, iclass 40, count 0 2006.169.08:11:57.77#ibcon#end of sib2, iclass 40, count 0 2006.169.08:11:57.77#ibcon#*after write, iclass 40, count 0 2006.169.08:11:57.77#ibcon#*before return 0, iclass 40, count 0 2006.169.08:11:57.77#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:11:57.77#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:11:57.77#ibcon#about to clear, iclass 40 cls_cnt 0 2006.169.08:11:57.77#ibcon#cleared, iclass 40 cls_cnt 0 2006.169.08:11:57.77$vc4f8/vb=2,4 2006.169.08:11:57.77#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.169.08:11:57.77#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.169.08:11:57.77#ibcon#ireg 11 cls_cnt 2 2006.169.08:11:57.77#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:11:57.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:11:57.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:11:57.83#ibcon#enter wrdev, iclass 4, count 2 2006.169.08:11:57.83#ibcon#first serial, iclass 4, count 2 2006.169.08:11:57.83#ibcon#enter sib2, iclass 4, count 2 2006.169.08:11:57.83#ibcon#flushed, iclass 4, count 2 2006.169.08:11:57.83#ibcon#about to write, iclass 4, count 2 2006.169.08:11:57.83#ibcon#wrote, iclass 4, count 2 2006.169.08:11:57.83#ibcon#about to read 3, iclass 4, count 2 2006.169.08:11:57.85#ibcon#read 3, iclass 4, count 2 2006.169.08:11:57.85#ibcon#about to read 4, iclass 4, count 2 2006.169.08:11:57.85#ibcon#read 4, iclass 4, count 2 2006.169.08:11:57.85#ibcon#about to read 5, iclass 4, count 2 2006.169.08:11:57.85#ibcon#read 5, iclass 4, count 2 2006.169.08:11:57.85#ibcon#about to read 6, iclass 4, count 2 2006.169.08:11:57.85#ibcon#read 6, iclass 4, count 2 2006.169.08:11:57.85#ibcon#end of sib2, iclass 4, count 2 2006.169.08:11:57.85#ibcon#*mode == 0, iclass 4, count 2 2006.169.08:11:57.85#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.169.08:11:57.85#ibcon#[27=AT02-04\r\n] 2006.169.08:11:57.85#ibcon#*before write, iclass 4, count 2 2006.169.08:11:57.85#ibcon#enter sib2, iclass 4, count 2 2006.169.08:11:57.85#ibcon#flushed, iclass 4, count 2 2006.169.08:11:57.85#ibcon#about to write, iclass 4, count 2 2006.169.08:11:57.85#ibcon#wrote, iclass 4, count 2 2006.169.08:11:57.85#ibcon#about to read 3, iclass 4, count 2 2006.169.08:11:57.88#ibcon#read 3, iclass 4, count 2 2006.169.08:11:57.88#ibcon#about to read 4, iclass 4, count 2 2006.169.08:11:57.88#ibcon#read 4, iclass 4, count 2 2006.169.08:11:57.88#ibcon#about to read 5, iclass 4, count 2 2006.169.08:11:57.88#ibcon#read 5, iclass 4, count 2 2006.169.08:11:57.88#ibcon#about to read 6, iclass 4, count 2 2006.169.08:11:57.88#ibcon#read 6, iclass 4, count 2 2006.169.08:11:57.88#ibcon#end of sib2, iclass 4, count 2 2006.169.08:11:57.88#ibcon#*after write, iclass 4, count 2 2006.169.08:11:57.88#ibcon#*before return 0, iclass 4, count 2 2006.169.08:11:57.88#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:11:57.88#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:11:57.88#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.169.08:11:57.88#ibcon#ireg 7 cls_cnt 0 2006.169.08:11:57.88#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:11:58.00#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:11:58.00#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:11:58.00#ibcon#enter wrdev, iclass 4, count 0 2006.169.08:11:58.00#ibcon#first serial, iclass 4, count 0 2006.169.08:11:58.00#ibcon#enter sib2, iclass 4, count 0 2006.169.08:11:58.00#ibcon#flushed, iclass 4, count 0 2006.169.08:11:58.00#ibcon#about to write, iclass 4, count 0 2006.169.08:11:58.00#ibcon#wrote, iclass 4, count 0 2006.169.08:11:58.00#ibcon#about to read 3, iclass 4, count 0 2006.169.08:11:58.02#ibcon#read 3, iclass 4, count 0 2006.169.08:11:58.02#ibcon#about to read 4, iclass 4, count 0 2006.169.08:11:58.02#ibcon#read 4, iclass 4, count 0 2006.169.08:11:58.02#ibcon#about to read 5, iclass 4, count 0 2006.169.08:11:58.02#ibcon#read 5, iclass 4, count 0 2006.169.08:11:58.02#ibcon#about to read 6, iclass 4, count 0 2006.169.08:11:58.02#ibcon#read 6, iclass 4, count 0 2006.169.08:11:58.02#ibcon#end of sib2, iclass 4, count 0 2006.169.08:11:58.02#ibcon#*mode == 0, iclass 4, count 0 2006.169.08:11:58.02#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.169.08:11:58.02#ibcon#[27=USB\r\n] 2006.169.08:11:58.02#ibcon#*before write, iclass 4, count 0 2006.169.08:11:58.02#ibcon#enter sib2, iclass 4, count 0 2006.169.08:11:58.02#ibcon#flushed, iclass 4, count 0 2006.169.08:11:58.02#ibcon#about to write, iclass 4, count 0 2006.169.08:11:58.02#ibcon#wrote, iclass 4, count 0 2006.169.08:11:58.02#ibcon#about to read 3, iclass 4, count 0 2006.169.08:11:58.05#ibcon#read 3, iclass 4, count 0 2006.169.08:11:58.05#ibcon#about to read 4, iclass 4, count 0 2006.169.08:11:58.05#ibcon#read 4, iclass 4, count 0 2006.169.08:11:58.05#ibcon#about to read 5, iclass 4, count 0 2006.169.08:11:58.05#ibcon#read 5, iclass 4, count 0 2006.169.08:11:58.05#ibcon#about to read 6, iclass 4, count 0 2006.169.08:11:58.05#ibcon#read 6, iclass 4, count 0 2006.169.08:11:58.05#ibcon#end of sib2, iclass 4, count 0 2006.169.08:11:58.05#ibcon#*after write, iclass 4, count 0 2006.169.08:11:58.05#ibcon#*before return 0, iclass 4, count 0 2006.169.08:11:58.05#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:11:58.05#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:11:58.05#ibcon#about to clear, iclass 4 cls_cnt 0 2006.169.08:11:58.05#ibcon#cleared, iclass 4 cls_cnt 0 2006.169.08:11:58.05$vc4f8/vblo=3,656.99 2006.169.08:11:58.05#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.169.08:11:58.05#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.169.08:11:58.05#ibcon#ireg 17 cls_cnt 0 2006.169.08:11:58.05#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:11:58.05#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:11:58.05#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:11:58.05#ibcon#enter wrdev, iclass 6, count 0 2006.169.08:11:58.05#ibcon#first serial, iclass 6, count 0 2006.169.08:11:58.05#ibcon#enter sib2, iclass 6, count 0 2006.169.08:11:58.05#ibcon#flushed, iclass 6, count 0 2006.169.08:11:58.05#ibcon#about to write, iclass 6, count 0 2006.169.08:11:58.05#ibcon#wrote, iclass 6, count 0 2006.169.08:11:58.05#ibcon#about to read 3, iclass 6, count 0 2006.169.08:11:58.07#ibcon#read 3, iclass 6, count 0 2006.169.08:11:58.07#ibcon#about to read 4, iclass 6, count 0 2006.169.08:11:58.07#ibcon#read 4, iclass 6, count 0 2006.169.08:11:58.07#ibcon#about to read 5, iclass 6, count 0 2006.169.08:11:58.07#ibcon#read 5, iclass 6, count 0 2006.169.08:11:58.07#ibcon#about to read 6, iclass 6, count 0 2006.169.08:11:58.07#ibcon#read 6, iclass 6, count 0 2006.169.08:11:58.07#ibcon#end of sib2, iclass 6, count 0 2006.169.08:11:58.07#ibcon#*mode == 0, iclass 6, count 0 2006.169.08:11:58.07#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.169.08:11:58.07#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.08:11:58.07#ibcon#*before write, iclass 6, count 0 2006.169.08:11:58.07#ibcon#enter sib2, iclass 6, count 0 2006.169.08:11:58.07#ibcon#flushed, iclass 6, count 0 2006.169.08:11:58.07#ibcon#about to write, iclass 6, count 0 2006.169.08:11:58.07#ibcon#wrote, iclass 6, count 0 2006.169.08:11:58.07#ibcon#about to read 3, iclass 6, count 0 2006.169.08:11:58.11#ibcon#read 3, iclass 6, count 0 2006.169.08:11:58.11#ibcon#about to read 4, iclass 6, count 0 2006.169.08:11:58.11#ibcon#read 4, iclass 6, count 0 2006.169.08:11:58.11#ibcon#about to read 5, iclass 6, count 0 2006.169.08:11:58.11#ibcon#read 5, iclass 6, count 0 2006.169.08:11:58.11#ibcon#about to read 6, iclass 6, count 0 2006.169.08:11:58.11#ibcon#read 6, iclass 6, count 0 2006.169.08:11:58.11#ibcon#end of sib2, iclass 6, count 0 2006.169.08:11:58.11#ibcon#*after write, iclass 6, count 0 2006.169.08:11:58.11#ibcon#*before return 0, iclass 6, count 0 2006.169.08:11:58.11#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:11:58.11#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:11:58.11#ibcon#about to clear, iclass 6 cls_cnt 0 2006.169.08:11:58.11#ibcon#cleared, iclass 6 cls_cnt 0 2006.169.08:11:58.11$vc4f8/vb=3,4 2006.169.08:11:58.11#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.169.08:11:58.11#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.169.08:11:58.11#ibcon#ireg 11 cls_cnt 2 2006.169.08:11:58.11#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:11:58.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:11:58.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:11:58.17#ibcon#enter wrdev, iclass 10, count 2 2006.169.08:11:58.17#ibcon#first serial, iclass 10, count 2 2006.169.08:11:58.17#ibcon#enter sib2, iclass 10, count 2 2006.169.08:11:58.17#ibcon#flushed, iclass 10, count 2 2006.169.08:11:58.17#ibcon#about to write, iclass 10, count 2 2006.169.08:11:58.17#ibcon#wrote, iclass 10, count 2 2006.169.08:11:58.17#ibcon#about to read 3, iclass 10, count 2 2006.169.08:11:58.19#ibcon#read 3, iclass 10, count 2 2006.169.08:11:58.19#ibcon#about to read 4, iclass 10, count 2 2006.169.08:11:58.19#ibcon#read 4, iclass 10, count 2 2006.169.08:11:58.19#ibcon#about to read 5, iclass 10, count 2 2006.169.08:11:58.19#ibcon#read 5, iclass 10, count 2 2006.169.08:11:58.19#ibcon#about to read 6, iclass 10, count 2 2006.169.08:11:58.19#ibcon#read 6, iclass 10, count 2 2006.169.08:11:58.19#ibcon#end of sib2, iclass 10, count 2 2006.169.08:11:58.19#ibcon#*mode == 0, iclass 10, count 2 2006.169.08:11:58.19#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.169.08:11:58.19#ibcon#[27=AT03-04\r\n] 2006.169.08:11:58.19#ibcon#*before write, iclass 10, count 2 2006.169.08:11:58.19#ibcon#enter sib2, iclass 10, count 2 2006.169.08:11:58.19#ibcon#flushed, iclass 10, count 2 2006.169.08:11:58.19#ibcon#about to write, iclass 10, count 2 2006.169.08:11:58.19#ibcon#wrote, iclass 10, count 2 2006.169.08:11:58.19#ibcon#about to read 3, iclass 10, count 2 2006.169.08:11:58.22#ibcon#read 3, iclass 10, count 2 2006.169.08:11:58.22#ibcon#about to read 4, iclass 10, count 2 2006.169.08:11:58.22#ibcon#read 4, iclass 10, count 2 2006.169.08:11:58.22#ibcon#about to read 5, iclass 10, count 2 2006.169.08:11:58.22#ibcon#read 5, iclass 10, count 2 2006.169.08:11:58.22#ibcon#about to read 6, iclass 10, count 2 2006.169.08:11:58.22#ibcon#read 6, iclass 10, count 2 2006.169.08:11:58.22#ibcon#end of sib2, iclass 10, count 2 2006.169.08:11:58.22#ibcon#*after write, iclass 10, count 2 2006.169.08:11:58.22#ibcon#*before return 0, iclass 10, count 2 2006.169.08:11:58.22#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:11:58.22#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:11:58.22#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.169.08:11:58.22#ibcon#ireg 7 cls_cnt 0 2006.169.08:11:58.22#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:11:58.34#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:11:58.34#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:11:58.34#ibcon#enter wrdev, iclass 10, count 0 2006.169.08:11:58.34#ibcon#first serial, iclass 10, count 0 2006.169.08:11:58.34#ibcon#enter sib2, iclass 10, count 0 2006.169.08:11:58.34#ibcon#flushed, iclass 10, count 0 2006.169.08:11:58.34#ibcon#about to write, iclass 10, count 0 2006.169.08:11:58.34#ibcon#wrote, iclass 10, count 0 2006.169.08:11:58.34#ibcon#about to read 3, iclass 10, count 0 2006.169.08:11:58.36#ibcon#read 3, iclass 10, count 0 2006.169.08:11:58.36#ibcon#about to read 4, iclass 10, count 0 2006.169.08:11:58.36#ibcon#read 4, iclass 10, count 0 2006.169.08:11:58.36#ibcon#about to read 5, iclass 10, count 0 2006.169.08:11:58.36#ibcon#read 5, iclass 10, count 0 2006.169.08:11:58.36#ibcon#about to read 6, iclass 10, count 0 2006.169.08:11:58.36#ibcon#read 6, iclass 10, count 0 2006.169.08:11:58.36#ibcon#end of sib2, iclass 10, count 0 2006.169.08:11:58.36#ibcon#*mode == 0, iclass 10, count 0 2006.169.08:11:58.36#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.169.08:11:58.36#ibcon#[27=USB\r\n] 2006.169.08:11:58.36#ibcon#*before write, iclass 10, count 0 2006.169.08:11:58.36#ibcon#enter sib2, iclass 10, count 0 2006.169.08:11:58.36#ibcon#flushed, iclass 10, count 0 2006.169.08:11:58.36#ibcon#about to write, iclass 10, count 0 2006.169.08:11:58.36#ibcon#wrote, iclass 10, count 0 2006.169.08:11:58.36#ibcon#about to read 3, iclass 10, count 0 2006.169.08:11:58.39#ibcon#read 3, iclass 10, count 0 2006.169.08:11:58.39#ibcon#about to read 4, iclass 10, count 0 2006.169.08:11:58.39#ibcon#read 4, iclass 10, count 0 2006.169.08:11:58.39#ibcon#about to read 5, iclass 10, count 0 2006.169.08:11:58.39#ibcon#read 5, iclass 10, count 0 2006.169.08:11:58.39#ibcon#about to read 6, iclass 10, count 0 2006.169.08:11:58.39#ibcon#read 6, iclass 10, count 0 2006.169.08:11:58.39#ibcon#end of sib2, iclass 10, count 0 2006.169.08:11:58.39#ibcon#*after write, iclass 10, count 0 2006.169.08:11:58.39#ibcon#*before return 0, iclass 10, count 0 2006.169.08:11:58.39#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:11:58.39#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:11:58.39#ibcon#about to clear, iclass 10 cls_cnt 0 2006.169.08:11:58.39#ibcon#cleared, iclass 10 cls_cnt 0 2006.169.08:11:58.39$vc4f8/vblo=4,712.99 2006.169.08:11:58.39#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.169.08:11:58.39#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.169.08:11:58.39#ibcon#ireg 17 cls_cnt 0 2006.169.08:11:58.39#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:11:58.39#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:11:58.39#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:11:58.39#ibcon#enter wrdev, iclass 12, count 0 2006.169.08:11:58.39#ibcon#first serial, iclass 12, count 0 2006.169.08:11:58.39#ibcon#enter sib2, iclass 12, count 0 2006.169.08:11:58.39#ibcon#flushed, iclass 12, count 0 2006.169.08:11:58.39#ibcon#about to write, iclass 12, count 0 2006.169.08:11:58.39#ibcon#wrote, iclass 12, count 0 2006.169.08:11:58.39#ibcon#about to read 3, iclass 12, count 0 2006.169.08:11:58.41#ibcon#read 3, iclass 12, count 0 2006.169.08:11:58.41#ibcon#about to read 4, iclass 12, count 0 2006.169.08:11:58.41#ibcon#read 4, iclass 12, count 0 2006.169.08:11:58.41#ibcon#about to read 5, iclass 12, count 0 2006.169.08:11:58.41#ibcon#read 5, iclass 12, count 0 2006.169.08:11:58.41#ibcon#about to read 6, iclass 12, count 0 2006.169.08:11:58.41#ibcon#read 6, iclass 12, count 0 2006.169.08:11:58.41#ibcon#end of sib2, iclass 12, count 0 2006.169.08:11:58.41#ibcon#*mode == 0, iclass 12, count 0 2006.169.08:11:58.41#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.169.08:11:58.41#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.08:11:58.41#ibcon#*before write, iclass 12, count 0 2006.169.08:11:58.41#ibcon#enter sib2, iclass 12, count 0 2006.169.08:11:58.41#ibcon#flushed, iclass 12, count 0 2006.169.08:11:58.41#ibcon#about to write, iclass 12, count 0 2006.169.08:11:58.41#ibcon#wrote, iclass 12, count 0 2006.169.08:11:58.41#ibcon#about to read 3, iclass 12, count 0 2006.169.08:11:58.45#ibcon#read 3, iclass 12, count 0 2006.169.08:11:58.45#ibcon#about to read 4, iclass 12, count 0 2006.169.08:11:58.45#ibcon#read 4, iclass 12, count 0 2006.169.08:11:58.45#ibcon#about to read 5, iclass 12, count 0 2006.169.08:11:58.45#ibcon#read 5, iclass 12, count 0 2006.169.08:11:58.45#ibcon#about to read 6, iclass 12, count 0 2006.169.08:11:58.45#ibcon#read 6, iclass 12, count 0 2006.169.08:11:58.45#ibcon#end of sib2, iclass 12, count 0 2006.169.08:11:58.45#ibcon#*after write, iclass 12, count 0 2006.169.08:11:58.45#ibcon#*before return 0, iclass 12, count 0 2006.169.08:11:58.45#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:11:58.45#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:11:58.45#ibcon#about to clear, iclass 12 cls_cnt 0 2006.169.08:11:58.45#ibcon#cleared, iclass 12 cls_cnt 0 2006.169.08:11:58.45$vc4f8/vb=4,4 2006.169.08:11:58.45#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.169.08:11:58.45#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.169.08:11:58.45#ibcon#ireg 11 cls_cnt 2 2006.169.08:11:58.45#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.169.08:11:58.51#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.169.08:11:58.51#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.169.08:11:58.51#ibcon#enter wrdev, iclass 14, count 2 2006.169.08:11:58.51#ibcon#first serial, iclass 14, count 2 2006.169.08:11:58.51#ibcon#enter sib2, iclass 14, count 2 2006.169.08:11:58.51#ibcon#flushed, iclass 14, count 2 2006.169.08:11:58.51#ibcon#about to write, iclass 14, count 2 2006.169.08:11:58.51#ibcon#wrote, iclass 14, count 2 2006.169.08:11:58.51#ibcon#about to read 3, iclass 14, count 2 2006.169.08:11:58.53#ibcon#read 3, iclass 14, count 2 2006.169.08:11:58.53#ibcon#about to read 4, iclass 14, count 2 2006.169.08:11:58.53#ibcon#read 4, iclass 14, count 2 2006.169.08:11:58.53#ibcon#about to read 5, iclass 14, count 2 2006.169.08:11:58.53#ibcon#read 5, iclass 14, count 2 2006.169.08:11:58.53#ibcon#about to read 6, iclass 14, count 2 2006.169.08:11:58.53#ibcon#read 6, iclass 14, count 2 2006.169.08:11:58.53#ibcon#end of sib2, iclass 14, count 2 2006.169.08:11:58.53#ibcon#*mode == 0, iclass 14, count 2 2006.169.08:11:58.53#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.169.08:11:58.53#ibcon#[27=AT04-04\r\n] 2006.169.08:11:58.53#ibcon#*before write, iclass 14, count 2 2006.169.08:11:58.53#ibcon#enter sib2, iclass 14, count 2 2006.169.08:11:58.53#ibcon#flushed, iclass 14, count 2 2006.169.08:11:58.53#ibcon#about to write, iclass 14, count 2 2006.169.08:11:58.53#ibcon#wrote, iclass 14, count 2 2006.169.08:11:58.53#ibcon#about to read 3, iclass 14, count 2 2006.169.08:11:58.56#ibcon#read 3, iclass 14, count 2 2006.169.08:11:58.56#ibcon#about to read 4, iclass 14, count 2 2006.169.08:11:58.56#ibcon#read 4, iclass 14, count 2 2006.169.08:11:58.56#ibcon#about to read 5, iclass 14, count 2 2006.169.08:11:58.56#ibcon#read 5, iclass 14, count 2 2006.169.08:11:58.56#ibcon#about to read 6, iclass 14, count 2 2006.169.08:11:58.56#ibcon#read 6, iclass 14, count 2 2006.169.08:11:58.56#ibcon#end of sib2, iclass 14, count 2 2006.169.08:11:58.56#ibcon#*after write, iclass 14, count 2 2006.169.08:11:58.56#ibcon#*before return 0, iclass 14, count 2 2006.169.08:11:58.56#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.169.08:11:58.56#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.169.08:11:58.56#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.169.08:11:58.56#ibcon#ireg 7 cls_cnt 0 2006.169.08:11:58.56#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.169.08:11:58.68#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.169.08:11:58.68#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.169.08:11:58.68#ibcon#enter wrdev, iclass 14, count 0 2006.169.08:11:58.68#ibcon#first serial, iclass 14, count 0 2006.169.08:11:58.68#ibcon#enter sib2, iclass 14, count 0 2006.169.08:11:58.68#ibcon#flushed, iclass 14, count 0 2006.169.08:11:58.68#ibcon#about to write, iclass 14, count 0 2006.169.08:11:58.68#ibcon#wrote, iclass 14, count 0 2006.169.08:11:58.68#ibcon#about to read 3, iclass 14, count 0 2006.169.08:11:58.70#ibcon#read 3, iclass 14, count 0 2006.169.08:11:58.70#ibcon#about to read 4, iclass 14, count 0 2006.169.08:11:58.70#ibcon#read 4, iclass 14, count 0 2006.169.08:11:58.70#ibcon#about to read 5, iclass 14, count 0 2006.169.08:11:58.70#ibcon#read 5, iclass 14, count 0 2006.169.08:11:58.70#ibcon#about to read 6, iclass 14, count 0 2006.169.08:11:58.70#ibcon#read 6, iclass 14, count 0 2006.169.08:11:58.70#ibcon#end of sib2, iclass 14, count 0 2006.169.08:11:58.70#ibcon#*mode == 0, iclass 14, count 0 2006.169.08:11:58.70#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.169.08:11:58.70#ibcon#[27=USB\r\n] 2006.169.08:11:58.70#ibcon#*before write, iclass 14, count 0 2006.169.08:11:58.70#ibcon#enter sib2, iclass 14, count 0 2006.169.08:11:58.70#ibcon#flushed, iclass 14, count 0 2006.169.08:11:58.70#ibcon#about to write, iclass 14, count 0 2006.169.08:11:58.70#ibcon#wrote, iclass 14, count 0 2006.169.08:11:58.70#ibcon#about to read 3, iclass 14, count 0 2006.169.08:11:58.73#ibcon#read 3, iclass 14, count 0 2006.169.08:11:58.73#ibcon#about to read 4, iclass 14, count 0 2006.169.08:11:58.73#ibcon#read 4, iclass 14, count 0 2006.169.08:11:58.73#ibcon#about to read 5, iclass 14, count 0 2006.169.08:11:58.73#ibcon#read 5, iclass 14, count 0 2006.169.08:11:58.73#ibcon#about to read 6, iclass 14, count 0 2006.169.08:11:58.73#ibcon#read 6, iclass 14, count 0 2006.169.08:11:58.73#ibcon#end of sib2, iclass 14, count 0 2006.169.08:11:58.73#ibcon#*after write, iclass 14, count 0 2006.169.08:11:58.73#ibcon#*before return 0, iclass 14, count 0 2006.169.08:11:58.73#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.169.08:11:58.73#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.169.08:11:58.73#ibcon#about to clear, iclass 14 cls_cnt 0 2006.169.08:11:58.73#ibcon#cleared, iclass 14 cls_cnt 0 2006.169.08:11:58.73$vc4f8/vblo=5,744.99 2006.169.08:11:58.73#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.169.08:11:58.73#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.169.08:11:58.73#ibcon#ireg 17 cls_cnt 0 2006.169.08:11:58.73#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:11:58.73#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:11:58.73#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:11:58.73#ibcon#enter wrdev, iclass 16, count 0 2006.169.08:11:58.73#ibcon#first serial, iclass 16, count 0 2006.169.08:11:58.73#ibcon#enter sib2, iclass 16, count 0 2006.169.08:11:58.73#ibcon#flushed, iclass 16, count 0 2006.169.08:11:58.73#ibcon#about to write, iclass 16, count 0 2006.169.08:11:58.73#ibcon#wrote, iclass 16, count 0 2006.169.08:11:58.73#ibcon#about to read 3, iclass 16, count 0 2006.169.08:11:58.75#ibcon#read 3, iclass 16, count 0 2006.169.08:11:58.75#ibcon#about to read 4, iclass 16, count 0 2006.169.08:11:58.75#ibcon#read 4, iclass 16, count 0 2006.169.08:11:58.75#ibcon#about to read 5, iclass 16, count 0 2006.169.08:11:58.75#ibcon#read 5, iclass 16, count 0 2006.169.08:11:58.75#ibcon#about to read 6, iclass 16, count 0 2006.169.08:11:58.75#ibcon#read 6, iclass 16, count 0 2006.169.08:11:58.75#ibcon#end of sib2, iclass 16, count 0 2006.169.08:11:58.75#ibcon#*mode == 0, iclass 16, count 0 2006.169.08:11:58.75#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.169.08:11:58.75#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.08:11:58.75#ibcon#*before write, iclass 16, count 0 2006.169.08:11:58.75#ibcon#enter sib2, iclass 16, count 0 2006.169.08:11:58.75#ibcon#flushed, iclass 16, count 0 2006.169.08:11:58.75#ibcon#about to write, iclass 16, count 0 2006.169.08:11:58.75#ibcon#wrote, iclass 16, count 0 2006.169.08:11:58.75#ibcon#about to read 3, iclass 16, count 0 2006.169.08:11:58.79#ibcon#read 3, iclass 16, count 0 2006.169.08:11:58.79#ibcon#about to read 4, iclass 16, count 0 2006.169.08:11:58.79#ibcon#read 4, iclass 16, count 0 2006.169.08:11:58.79#ibcon#about to read 5, iclass 16, count 0 2006.169.08:11:58.79#ibcon#read 5, iclass 16, count 0 2006.169.08:11:58.79#ibcon#about to read 6, iclass 16, count 0 2006.169.08:11:58.79#ibcon#read 6, iclass 16, count 0 2006.169.08:11:58.79#ibcon#end of sib2, iclass 16, count 0 2006.169.08:11:58.79#ibcon#*after write, iclass 16, count 0 2006.169.08:11:58.79#ibcon#*before return 0, iclass 16, count 0 2006.169.08:11:58.79#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:11:58.79#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.169.08:11:58.79#ibcon#about to clear, iclass 16 cls_cnt 0 2006.169.08:11:58.79#ibcon#cleared, iclass 16 cls_cnt 0 2006.169.08:11:58.79$vc4f8/vb=5,4 2006.169.08:11:58.79#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.169.08:11:58.79#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.169.08:11:58.79#ibcon#ireg 11 cls_cnt 2 2006.169.08:11:58.79#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.169.08:11:58.85#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.169.08:11:58.85#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.169.08:11:58.85#ibcon#enter wrdev, iclass 18, count 2 2006.169.08:11:58.85#ibcon#first serial, iclass 18, count 2 2006.169.08:11:58.85#ibcon#enter sib2, iclass 18, count 2 2006.169.08:11:58.85#ibcon#flushed, iclass 18, count 2 2006.169.08:11:58.85#ibcon#about to write, iclass 18, count 2 2006.169.08:11:58.85#ibcon#wrote, iclass 18, count 2 2006.169.08:11:58.85#ibcon#about to read 3, iclass 18, count 2 2006.169.08:11:58.87#ibcon#read 3, iclass 18, count 2 2006.169.08:11:58.87#ibcon#about to read 4, iclass 18, count 2 2006.169.08:11:58.87#ibcon#read 4, iclass 18, count 2 2006.169.08:11:58.87#ibcon#about to read 5, iclass 18, count 2 2006.169.08:11:58.87#ibcon#read 5, iclass 18, count 2 2006.169.08:11:58.87#ibcon#about to read 6, iclass 18, count 2 2006.169.08:11:58.87#ibcon#read 6, iclass 18, count 2 2006.169.08:11:58.87#ibcon#end of sib2, iclass 18, count 2 2006.169.08:11:58.87#ibcon#*mode == 0, iclass 18, count 2 2006.169.08:11:58.87#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.169.08:11:58.87#ibcon#[27=AT05-04\r\n] 2006.169.08:11:58.87#ibcon#*before write, iclass 18, count 2 2006.169.08:11:58.87#ibcon#enter sib2, iclass 18, count 2 2006.169.08:11:58.87#ibcon#flushed, iclass 18, count 2 2006.169.08:11:58.87#ibcon#about to write, iclass 18, count 2 2006.169.08:11:58.87#ibcon#wrote, iclass 18, count 2 2006.169.08:11:58.87#ibcon#about to read 3, iclass 18, count 2 2006.169.08:11:58.90#ibcon#read 3, iclass 18, count 2 2006.169.08:11:58.90#ibcon#about to read 4, iclass 18, count 2 2006.169.08:11:58.90#ibcon#read 4, iclass 18, count 2 2006.169.08:11:58.90#ibcon#about to read 5, iclass 18, count 2 2006.169.08:11:58.90#ibcon#read 5, iclass 18, count 2 2006.169.08:11:58.90#ibcon#about to read 6, iclass 18, count 2 2006.169.08:11:58.90#ibcon#read 6, iclass 18, count 2 2006.169.08:11:58.90#ibcon#end of sib2, iclass 18, count 2 2006.169.08:11:58.90#ibcon#*after write, iclass 18, count 2 2006.169.08:11:58.90#ibcon#*before return 0, iclass 18, count 2 2006.169.08:11:58.90#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.169.08:11:58.90#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.169.08:11:58.90#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.169.08:11:58.90#ibcon#ireg 7 cls_cnt 0 2006.169.08:11:58.90#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.169.08:11:59.02#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.169.08:11:59.02#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.169.08:11:59.02#ibcon#enter wrdev, iclass 18, count 0 2006.169.08:11:59.02#ibcon#first serial, iclass 18, count 0 2006.169.08:11:59.02#ibcon#enter sib2, iclass 18, count 0 2006.169.08:11:59.02#ibcon#flushed, iclass 18, count 0 2006.169.08:11:59.02#ibcon#about to write, iclass 18, count 0 2006.169.08:11:59.02#ibcon#wrote, iclass 18, count 0 2006.169.08:11:59.02#ibcon#about to read 3, iclass 18, count 0 2006.169.08:11:59.04#ibcon#read 3, iclass 18, count 0 2006.169.08:11:59.04#ibcon#about to read 4, iclass 18, count 0 2006.169.08:11:59.04#ibcon#read 4, iclass 18, count 0 2006.169.08:11:59.04#ibcon#about to read 5, iclass 18, count 0 2006.169.08:11:59.04#ibcon#read 5, iclass 18, count 0 2006.169.08:11:59.04#ibcon#about to read 6, iclass 18, count 0 2006.169.08:11:59.04#ibcon#read 6, iclass 18, count 0 2006.169.08:11:59.04#ibcon#end of sib2, iclass 18, count 0 2006.169.08:11:59.04#ibcon#*mode == 0, iclass 18, count 0 2006.169.08:11:59.04#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.169.08:11:59.04#ibcon#[27=USB\r\n] 2006.169.08:11:59.04#ibcon#*before write, iclass 18, count 0 2006.169.08:11:59.04#ibcon#enter sib2, iclass 18, count 0 2006.169.08:11:59.04#ibcon#flushed, iclass 18, count 0 2006.169.08:11:59.04#ibcon#about to write, iclass 18, count 0 2006.169.08:11:59.04#ibcon#wrote, iclass 18, count 0 2006.169.08:11:59.04#ibcon#about to read 3, iclass 18, count 0 2006.169.08:11:59.07#ibcon#read 3, iclass 18, count 0 2006.169.08:11:59.07#ibcon#about to read 4, iclass 18, count 0 2006.169.08:11:59.07#ibcon#read 4, iclass 18, count 0 2006.169.08:11:59.07#ibcon#about to read 5, iclass 18, count 0 2006.169.08:11:59.07#ibcon#read 5, iclass 18, count 0 2006.169.08:11:59.07#ibcon#about to read 6, iclass 18, count 0 2006.169.08:11:59.07#ibcon#read 6, iclass 18, count 0 2006.169.08:11:59.07#ibcon#end of sib2, iclass 18, count 0 2006.169.08:11:59.07#ibcon#*after write, iclass 18, count 0 2006.169.08:11:59.07#ibcon#*before return 0, iclass 18, count 0 2006.169.08:11:59.07#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.169.08:11:59.07#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.169.08:11:59.07#ibcon#about to clear, iclass 18 cls_cnt 0 2006.169.08:11:59.07#ibcon#cleared, iclass 18 cls_cnt 0 2006.169.08:11:59.07$vc4f8/vblo=6,752.99 2006.169.08:11:59.07#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.169.08:11:59.07#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.169.08:11:59.07#ibcon#ireg 17 cls_cnt 0 2006.169.08:11:59.07#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:11:59.07#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:11:59.07#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:11:59.07#ibcon#enter wrdev, iclass 20, count 0 2006.169.08:11:59.07#ibcon#first serial, iclass 20, count 0 2006.169.08:11:59.07#ibcon#enter sib2, iclass 20, count 0 2006.169.08:11:59.07#ibcon#flushed, iclass 20, count 0 2006.169.08:11:59.07#ibcon#about to write, iclass 20, count 0 2006.169.08:11:59.07#ibcon#wrote, iclass 20, count 0 2006.169.08:11:59.07#ibcon#about to read 3, iclass 20, count 0 2006.169.08:11:59.09#ibcon#read 3, iclass 20, count 0 2006.169.08:11:59.09#ibcon#about to read 4, iclass 20, count 0 2006.169.08:11:59.09#ibcon#read 4, iclass 20, count 0 2006.169.08:11:59.09#ibcon#about to read 5, iclass 20, count 0 2006.169.08:11:59.09#ibcon#read 5, iclass 20, count 0 2006.169.08:11:59.09#ibcon#about to read 6, iclass 20, count 0 2006.169.08:11:59.09#ibcon#read 6, iclass 20, count 0 2006.169.08:11:59.09#ibcon#end of sib2, iclass 20, count 0 2006.169.08:11:59.09#ibcon#*mode == 0, iclass 20, count 0 2006.169.08:11:59.09#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.169.08:11:59.09#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.08:11:59.09#ibcon#*before write, iclass 20, count 0 2006.169.08:11:59.09#ibcon#enter sib2, iclass 20, count 0 2006.169.08:11:59.09#ibcon#flushed, iclass 20, count 0 2006.169.08:11:59.09#ibcon#about to write, iclass 20, count 0 2006.169.08:11:59.09#ibcon#wrote, iclass 20, count 0 2006.169.08:11:59.09#ibcon#about to read 3, iclass 20, count 0 2006.169.08:11:59.13#ibcon#read 3, iclass 20, count 0 2006.169.08:11:59.13#ibcon#about to read 4, iclass 20, count 0 2006.169.08:11:59.13#ibcon#read 4, iclass 20, count 0 2006.169.08:11:59.13#ibcon#about to read 5, iclass 20, count 0 2006.169.08:11:59.13#ibcon#read 5, iclass 20, count 0 2006.169.08:11:59.13#ibcon#about to read 6, iclass 20, count 0 2006.169.08:11:59.13#ibcon#read 6, iclass 20, count 0 2006.169.08:11:59.13#ibcon#end of sib2, iclass 20, count 0 2006.169.08:11:59.13#ibcon#*after write, iclass 20, count 0 2006.169.08:11:59.13#ibcon#*before return 0, iclass 20, count 0 2006.169.08:11:59.13#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:11:59.13#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:11:59.13#ibcon#about to clear, iclass 20 cls_cnt 0 2006.169.08:11:59.13#ibcon#cleared, iclass 20 cls_cnt 0 2006.169.08:11:59.13$vc4f8/vb=6,4 2006.169.08:11:59.13#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.169.08:11:59.13#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.169.08:11:59.13#ibcon#ireg 11 cls_cnt 2 2006.169.08:11:59.13#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:11:59.19#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:11:59.19#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:11:59.19#ibcon#enter wrdev, iclass 22, count 2 2006.169.08:11:59.19#ibcon#first serial, iclass 22, count 2 2006.169.08:11:59.19#ibcon#enter sib2, iclass 22, count 2 2006.169.08:11:59.19#ibcon#flushed, iclass 22, count 2 2006.169.08:11:59.19#ibcon#about to write, iclass 22, count 2 2006.169.08:11:59.19#ibcon#wrote, iclass 22, count 2 2006.169.08:11:59.19#ibcon#about to read 3, iclass 22, count 2 2006.169.08:11:59.21#ibcon#read 3, iclass 22, count 2 2006.169.08:11:59.21#ibcon#about to read 4, iclass 22, count 2 2006.169.08:11:59.21#ibcon#read 4, iclass 22, count 2 2006.169.08:11:59.21#ibcon#about to read 5, iclass 22, count 2 2006.169.08:11:59.21#ibcon#read 5, iclass 22, count 2 2006.169.08:11:59.21#ibcon#about to read 6, iclass 22, count 2 2006.169.08:11:59.21#ibcon#read 6, iclass 22, count 2 2006.169.08:11:59.21#ibcon#end of sib2, iclass 22, count 2 2006.169.08:11:59.21#ibcon#*mode == 0, iclass 22, count 2 2006.169.08:11:59.21#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.169.08:11:59.21#ibcon#[27=AT06-04\r\n] 2006.169.08:11:59.21#ibcon#*before write, iclass 22, count 2 2006.169.08:11:59.21#ibcon#enter sib2, iclass 22, count 2 2006.169.08:11:59.21#ibcon#flushed, iclass 22, count 2 2006.169.08:11:59.21#ibcon#about to write, iclass 22, count 2 2006.169.08:11:59.21#ibcon#wrote, iclass 22, count 2 2006.169.08:11:59.21#ibcon#about to read 3, iclass 22, count 2 2006.169.08:11:59.24#ibcon#read 3, iclass 22, count 2 2006.169.08:11:59.24#ibcon#about to read 4, iclass 22, count 2 2006.169.08:11:59.24#ibcon#read 4, iclass 22, count 2 2006.169.08:11:59.24#ibcon#about to read 5, iclass 22, count 2 2006.169.08:11:59.24#ibcon#read 5, iclass 22, count 2 2006.169.08:11:59.24#ibcon#about to read 6, iclass 22, count 2 2006.169.08:11:59.24#ibcon#read 6, iclass 22, count 2 2006.169.08:11:59.24#ibcon#end of sib2, iclass 22, count 2 2006.169.08:11:59.24#ibcon#*after write, iclass 22, count 2 2006.169.08:11:59.24#ibcon#*before return 0, iclass 22, count 2 2006.169.08:11:59.24#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:11:59.24#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:11:59.24#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.169.08:11:59.24#ibcon#ireg 7 cls_cnt 0 2006.169.08:11:59.24#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:11:59.36#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:11:59.36#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:11:59.36#ibcon#enter wrdev, iclass 22, count 0 2006.169.08:11:59.36#ibcon#first serial, iclass 22, count 0 2006.169.08:11:59.36#ibcon#enter sib2, iclass 22, count 0 2006.169.08:11:59.36#ibcon#flushed, iclass 22, count 0 2006.169.08:11:59.36#ibcon#about to write, iclass 22, count 0 2006.169.08:11:59.36#ibcon#wrote, iclass 22, count 0 2006.169.08:11:59.36#ibcon#about to read 3, iclass 22, count 0 2006.169.08:11:59.38#ibcon#read 3, iclass 22, count 0 2006.169.08:11:59.38#ibcon#about to read 4, iclass 22, count 0 2006.169.08:11:59.38#ibcon#read 4, iclass 22, count 0 2006.169.08:11:59.38#ibcon#about to read 5, iclass 22, count 0 2006.169.08:11:59.38#ibcon#read 5, iclass 22, count 0 2006.169.08:11:59.38#ibcon#about to read 6, iclass 22, count 0 2006.169.08:11:59.38#ibcon#read 6, iclass 22, count 0 2006.169.08:11:59.38#ibcon#end of sib2, iclass 22, count 0 2006.169.08:11:59.38#ibcon#*mode == 0, iclass 22, count 0 2006.169.08:11:59.38#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.169.08:11:59.38#ibcon#[27=USB\r\n] 2006.169.08:11:59.38#ibcon#*before write, iclass 22, count 0 2006.169.08:11:59.38#ibcon#enter sib2, iclass 22, count 0 2006.169.08:11:59.38#ibcon#flushed, iclass 22, count 0 2006.169.08:11:59.38#ibcon#about to write, iclass 22, count 0 2006.169.08:11:59.38#ibcon#wrote, iclass 22, count 0 2006.169.08:11:59.38#ibcon#about to read 3, iclass 22, count 0 2006.169.08:11:59.41#ibcon#read 3, iclass 22, count 0 2006.169.08:11:59.41#ibcon#about to read 4, iclass 22, count 0 2006.169.08:11:59.41#ibcon#read 4, iclass 22, count 0 2006.169.08:11:59.41#ibcon#about to read 5, iclass 22, count 0 2006.169.08:11:59.41#ibcon#read 5, iclass 22, count 0 2006.169.08:11:59.41#ibcon#about to read 6, iclass 22, count 0 2006.169.08:11:59.41#ibcon#read 6, iclass 22, count 0 2006.169.08:11:59.41#ibcon#end of sib2, iclass 22, count 0 2006.169.08:11:59.41#ibcon#*after write, iclass 22, count 0 2006.169.08:11:59.41#ibcon#*before return 0, iclass 22, count 0 2006.169.08:11:59.41#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:11:59.41#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:11:59.41#ibcon#about to clear, iclass 22 cls_cnt 0 2006.169.08:11:59.41#ibcon#cleared, iclass 22 cls_cnt 0 2006.169.08:11:59.41$vc4f8/vabw=wide 2006.169.08:11:59.41#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.169.08:11:59.41#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.169.08:11:59.41#ibcon#ireg 8 cls_cnt 0 2006.169.08:11:59.41#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:11:59.41#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:11:59.41#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:11:59.41#ibcon#enter wrdev, iclass 24, count 0 2006.169.08:11:59.41#ibcon#first serial, iclass 24, count 0 2006.169.08:11:59.41#ibcon#enter sib2, iclass 24, count 0 2006.169.08:11:59.41#ibcon#flushed, iclass 24, count 0 2006.169.08:11:59.41#ibcon#about to write, iclass 24, count 0 2006.169.08:11:59.41#ibcon#wrote, iclass 24, count 0 2006.169.08:11:59.41#ibcon#about to read 3, iclass 24, count 0 2006.169.08:11:59.43#ibcon#read 3, iclass 24, count 0 2006.169.08:11:59.43#ibcon#about to read 4, iclass 24, count 0 2006.169.08:11:59.43#ibcon#read 4, iclass 24, count 0 2006.169.08:11:59.43#ibcon#about to read 5, iclass 24, count 0 2006.169.08:11:59.43#ibcon#read 5, iclass 24, count 0 2006.169.08:11:59.43#ibcon#about to read 6, iclass 24, count 0 2006.169.08:11:59.43#ibcon#read 6, iclass 24, count 0 2006.169.08:11:59.43#ibcon#end of sib2, iclass 24, count 0 2006.169.08:11:59.43#ibcon#*mode == 0, iclass 24, count 0 2006.169.08:11:59.43#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.169.08:11:59.43#ibcon#[25=BW32\r\n] 2006.169.08:11:59.43#ibcon#*before write, iclass 24, count 0 2006.169.08:11:59.43#ibcon#enter sib2, iclass 24, count 0 2006.169.08:11:59.43#ibcon#flushed, iclass 24, count 0 2006.169.08:11:59.43#ibcon#about to write, iclass 24, count 0 2006.169.08:11:59.43#ibcon#wrote, iclass 24, count 0 2006.169.08:11:59.43#ibcon#about to read 3, iclass 24, count 0 2006.169.08:11:59.46#ibcon#read 3, iclass 24, count 0 2006.169.08:11:59.46#ibcon#about to read 4, iclass 24, count 0 2006.169.08:11:59.46#ibcon#read 4, iclass 24, count 0 2006.169.08:11:59.46#ibcon#about to read 5, iclass 24, count 0 2006.169.08:11:59.46#ibcon#read 5, iclass 24, count 0 2006.169.08:11:59.46#ibcon#about to read 6, iclass 24, count 0 2006.169.08:11:59.46#ibcon#read 6, iclass 24, count 0 2006.169.08:11:59.46#ibcon#end of sib2, iclass 24, count 0 2006.169.08:11:59.46#ibcon#*after write, iclass 24, count 0 2006.169.08:11:59.46#ibcon#*before return 0, iclass 24, count 0 2006.169.08:11:59.46#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:11:59.46#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:11:59.46#ibcon#about to clear, iclass 24 cls_cnt 0 2006.169.08:11:59.46#ibcon#cleared, iclass 24 cls_cnt 0 2006.169.08:11:59.46$vc4f8/vbbw=wide 2006.169.08:11:59.46#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.169.08:11:59.46#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.169.08:11:59.46#ibcon#ireg 8 cls_cnt 0 2006.169.08:11:59.46#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:11:59.53#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:11:59.53#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:11:59.53#ibcon#enter wrdev, iclass 26, count 0 2006.169.08:11:59.53#ibcon#first serial, iclass 26, count 0 2006.169.08:11:59.53#ibcon#enter sib2, iclass 26, count 0 2006.169.08:11:59.53#ibcon#flushed, iclass 26, count 0 2006.169.08:11:59.53#ibcon#about to write, iclass 26, count 0 2006.169.08:11:59.53#ibcon#wrote, iclass 26, count 0 2006.169.08:11:59.53#ibcon#about to read 3, iclass 26, count 0 2006.169.08:11:59.55#ibcon#read 3, iclass 26, count 0 2006.169.08:11:59.55#ibcon#about to read 4, iclass 26, count 0 2006.169.08:11:59.55#ibcon#read 4, iclass 26, count 0 2006.169.08:11:59.55#ibcon#about to read 5, iclass 26, count 0 2006.169.08:11:59.55#ibcon#read 5, iclass 26, count 0 2006.169.08:11:59.55#ibcon#about to read 6, iclass 26, count 0 2006.169.08:11:59.55#ibcon#read 6, iclass 26, count 0 2006.169.08:11:59.55#ibcon#end of sib2, iclass 26, count 0 2006.169.08:11:59.55#ibcon#*mode == 0, iclass 26, count 0 2006.169.08:11:59.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.169.08:11:59.55#ibcon#[27=BW32\r\n] 2006.169.08:11:59.55#ibcon#*before write, iclass 26, count 0 2006.169.08:11:59.55#ibcon#enter sib2, iclass 26, count 0 2006.169.08:11:59.55#ibcon#flushed, iclass 26, count 0 2006.169.08:11:59.55#ibcon#about to write, iclass 26, count 0 2006.169.08:11:59.55#ibcon#wrote, iclass 26, count 0 2006.169.08:11:59.55#ibcon#about to read 3, iclass 26, count 0 2006.169.08:11:59.58#ibcon#read 3, iclass 26, count 0 2006.169.08:11:59.58#ibcon#about to read 4, iclass 26, count 0 2006.169.08:11:59.58#ibcon#read 4, iclass 26, count 0 2006.169.08:11:59.58#ibcon#about to read 5, iclass 26, count 0 2006.169.08:11:59.58#ibcon#read 5, iclass 26, count 0 2006.169.08:11:59.58#ibcon#about to read 6, iclass 26, count 0 2006.169.08:11:59.58#ibcon#read 6, iclass 26, count 0 2006.169.08:11:59.58#ibcon#end of sib2, iclass 26, count 0 2006.169.08:11:59.58#ibcon#*after write, iclass 26, count 0 2006.169.08:11:59.58#ibcon#*before return 0, iclass 26, count 0 2006.169.08:11:59.58#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:11:59.58#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:11:59.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.169.08:11:59.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.169.08:11:59.58$4f8m12a/ifd4f 2006.169.08:11:59.58$ifd4f/lo= 2006.169.08:11:59.58$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.08:11:59.58$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.08:11:59.58$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.08:11:59.58$ifd4f/patch= 2006.169.08:11:59.58$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.08:11:59.58$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.08:11:59.58$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.08:11:59.58$4f8m12a/"form=m,16.000,1:2 2006.169.08:11:59.58$4f8m12a/"tpicd 2006.169.08:11:59.58$4f8m12a/echo=off 2006.169.08:11:59.58$4f8m12a/xlog=off 2006.169.08:11:59.58:!2006.169.08:12:10 2006.169.08:12:10.00:preob 2006.169.08:12:11.13/onsource/TRACKING 2006.169.08:12:11.13:!2006.169.08:12:20 2006.169.08:12:20.00:data_valid=on 2006.169.08:12:20.00:midob 2006.169.08:12:20.14/onsource/TRACKING 2006.169.08:12:20.14/wx/18.14,1003.8,100 2006.169.08:12:20.29/cable/+6.5290E-03 2006.169.08:12:21.38/va/01,08,usb,yes,44,46 2006.169.08:12:21.38/va/02,07,usb,yes,45,46 2006.169.08:12:21.38/va/03,06,usb,yes,47,47 2006.169.08:12:21.38/va/04,07,usb,yes,46,49 2006.169.08:12:21.38/va/05,07,usb,yes,50,53 2006.169.08:12:21.38/va/06,06,usb,yes,49,49 2006.169.08:12:21.38/va/07,06,usb,yes,49,49 2006.169.08:12:21.38/va/08,07,usb,yes,47,46 2006.169.08:12:21.61/valo/01,532.99,yes,locked 2006.169.08:12:21.61/valo/02,572.99,yes,locked 2006.169.08:12:21.61/valo/03,672.99,yes,locked 2006.169.08:12:21.61/valo/04,832.99,yes,locked 2006.169.08:12:21.61/valo/05,652.99,yes,locked 2006.169.08:12:21.61/valo/06,772.99,yes,locked 2006.169.08:12:21.61/valo/07,832.99,yes,locked 2006.169.08:12:21.61/valo/08,852.99,yes,locked 2006.169.08:12:22.70/vb/01,04,usb,yes,30,29 2006.169.08:12:22.70/vb/02,04,usb,yes,32,33 2006.169.08:12:22.70/vb/03,04,usb,yes,28,32 2006.169.08:12:22.70/vb/04,04,usb,yes,29,29 2006.169.08:12:22.70/vb/05,04,usb,yes,28,31 2006.169.08:12:22.70/vb/06,04,usb,yes,29,31 2006.169.08:12:22.70/vb/07,04,usb,yes,31,30 2006.169.08:12:22.70/vb/08,04,usb,yes,28,31 2006.169.08:12:22.93/vblo/01,632.99,yes,locked 2006.169.08:12:22.93/vblo/02,640.99,yes,locked 2006.169.08:12:22.93/vblo/03,656.99,yes,locked 2006.169.08:12:22.93/vblo/04,712.99,yes,locked 2006.169.08:12:22.93/vblo/05,744.99,yes,locked 2006.169.08:12:22.93/vblo/06,752.99,yes,locked 2006.169.08:12:22.93/vblo/07,734.99,yes,locked 2006.169.08:12:22.93/vblo/08,744.99,yes,locked 2006.169.08:12:23.08/vabw/8 2006.169.08:12:23.23/vbbw/8 2006.169.08:12:23.32/xfe/off,on,15.5 2006.169.08:12:23.69/ifatt/23,28,28,28 2006.169.08:12:24.08/fmout-gps/S +4.17E-07 2006.169.08:12:24.16:!2006.169.08:13:20 2006.169.08:13:20.00:data_valid=off 2006.169.08:13:20.00:postob 2006.169.08:13:20.13/cable/+6.5311E-03 2006.169.08:13:20.13/wx/18.14,1003.8,100 2006.169.08:13:21.08/fmout-gps/S +4.18E-07 2006.169.08:13:21.08:scan_name=169-0814,k06169,60 2006.169.08:13:21.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.169.08:13:21.14#flagr#flagr/antenna,new-source 2006.169.08:13:22.14:checkk5 2006.169.08:13:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.169.08:13:22.92/chk_autoobs//k5ts2/ autoobs is running! 2006.169.08:13:26.94/chk_autoobs//k5ts3?ERROR: timeout happened! 2006.169.08:13:27.32/chk_autoobs//k5ts4/ autoobs is running! 2006.169.08:13:27.68/chk_obsdata//k5ts1/T1690812??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.08:13:28.05/chk_obsdata//k5ts2/T1690812??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.08:13:35.08/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.08:13:35.45/chk_obsdata//k5ts4/T1690812??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.08:13:36.14/k5log//k5ts1_log_newline 2006.169.08:13:36.83/k5log//k5ts2_log_newline 2006.169.08:13:43.14#trakl#Source acquired 2006.169.08:13:43.94/k5log//k5ts3?ERROR: timeout happened! 2006.169.08:13:44.63/k5log//k5ts4_log_newline 2006.169.08:13:44.79/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.08:13:44.79:4f8m12a=2 2006.169.08:13:44.79$4f8m12a/echo=on 2006.169.08:13:44.79$4f8m12a/pcalon 2006.169.08:13:44.79$pcalon/"no phase cal control is implemented here 2006.169.08:13:44.79$4f8m12a/"tpicd=stop 2006.169.08:13:44.79$4f8m12a/vc4f8 2006.169.08:13:44.79$vc4f8/valo=1,532.99 2006.169.08:13:44.80#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.169.08:13:44.80#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.169.08:13:44.80#ibcon#ireg 17 cls_cnt 0 2006.169.08:13:44.80#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:13:44.80#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:13:44.80#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:13:44.80#ibcon#enter wrdev, iclass 37, count 0 2006.169.08:13:44.80#ibcon#first serial, iclass 37, count 0 2006.169.08:13:44.80#ibcon#enter sib2, iclass 37, count 0 2006.169.08:13:44.80#ibcon#flushed, iclass 37, count 0 2006.169.08:13:44.80#ibcon#about to write, iclass 37, count 0 2006.169.08:13:44.80#ibcon#wrote, iclass 37, count 0 2006.169.08:13:44.80#ibcon#about to read 3, iclass 37, count 0 2006.169.08:13:44.82#ibcon#read 3, iclass 37, count 0 2006.169.08:13:44.82#ibcon#about to read 4, iclass 37, count 0 2006.169.08:13:44.82#ibcon#read 4, iclass 37, count 0 2006.169.08:13:44.82#ibcon#about to read 5, iclass 37, count 0 2006.169.08:13:44.82#ibcon#read 5, iclass 37, count 0 2006.169.08:13:44.82#ibcon#about to read 6, iclass 37, count 0 2006.169.08:13:44.82#ibcon#read 6, iclass 37, count 0 2006.169.08:13:44.82#ibcon#end of sib2, iclass 37, count 0 2006.169.08:13:44.82#ibcon#*mode == 0, iclass 37, count 0 2006.169.08:13:44.82#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.169.08:13:44.82#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.08:13:44.82#ibcon#*before write, iclass 37, count 0 2006.169.08:13:44.82#ibcon#enter sib2, iclass 37, count 0 2006.169.08:13:44.82#ibcon#flushed, iclass 37, count 0 2006.169.08:13:44.82#ibcon#about to write, iclass 37, count 0 2006.169.08:13:44.82#ibcon#wrote, iclass 37, count 0 2006.169.08:13:44.82#ibcon#about to read 3, iclass 37, count 0 2006.169.08:13:44.87#ibcon#read 3, iclass 37, count 0 2006.169.08:13:44.87#ibcon#about to read 4, iclass 37, count 0 2006.169.08:13:44.87#ibcon#read 4, iclass 37, count 0 2006.169.08:13:44.87#ibcon#about to read 5, iclass 37, count 0 2006.169.08:13:44.87#ibcon#read 5, iclass 37, count 0 2006.169.08:13:44.87#ibcon#about to read 6, iclass 37, count 0 2006.169.08:13:44.87#ibcon#read 6, iclass 37, count 0 2006.169.08:13:44.87#ibcon#end of sib2, iclass 37, count 0 2006.169.08:13:44.87#ibcon#*after write, iclass 37, count 0 2006.169.08:13:44.87#ibcon#*before return 0, iclass 37, count 0 2006.169.08:13:44.87#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:13:44.87#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:13:44.87#ibcon#about to clear, iclass 37 cls_cnt 0 2006.169.08:13:44.87#ibcon#cleared, iclass 37 cls_cnt 0 2006.169.08:13:44.87$vc4f8/va=1,8 2006.169.08:13:44.87#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.169.08:13:44.87#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.169.08:13:44.87#ibcon#ireg 11 cls_cnt 2 2006.169.08:13:44.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.169.08:13:44.87#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.169.08:13:44.87#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.169.08:13:44.87#ibcon#enter wrdev, iclass 39, count 2 2006.169.08:13:44.87#ibcon#first serial, iclass 39, count 2 2006.169.08:13:44.87#ibcon#enter sib2, iclass 39, count 2 2006.169.08:13:44.87#ibcon#flushed, iclass 39, count 2 2006.169.08:13:44.87#ibcon#about to write, iclass 39, count 2 2006.169.08:13:44.87#ibcon#wrote, iclass 39, count 2 2006.169.08:13:44.87#ibcon#about to read 3, iclass 39, count 2 2006.169.08:13:44.89#ibcon#read 3, iclass 39, count 2 2006.169.08:13:44.89#ibcon#about to read 4, iclass 39, count 2 2006.169.08:13:44.89#ibcon#read 4, iclass 39, count 2 2006.169.08:13:44.89#ibcon#about to read 5, iclass 39, count 2 2006.169.08:13:44.89#ibcon#read 5, iclass 39, count 2 2006.169.08:13:44.89#ibcon#about to read 6, iclass 39, count 2 2006.169.08:13:44.89#ibcon#read 6, iclass 39, count 2 2006.169.08:13:44.89#ibcon#end of sib2, iclass 39, count 2 2006.169.08:13:44.89#ibcon#*mode == 0, iclass 39, count 2 2006.169.08:13:44.89#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.169.08:13:44.89#ibcon#[25=AT01-08\r\n] 2006.169.08:13:44.89#ibcon#*before write, iclass 39, count 2 2006.169.08:13:44.89#ibcon#enter sib2, iclass 39, count 2 2006.169.08:13:44.89#ibcon#flushed, iclass 39, count 2 2006.169.08:13:44.89#ibcon#about to write, iclass 39, count 2 2006.169.08:13:44.89#ibcon#wrote, iclass 39, count 2 2006.169.08:13:44.89#ibcon#about to read 3, iclass 39, count 2 2006.169.08:13:44.92#ibcon#read 3, iclass 39, count 2 2006.169.08:13:44.92#ibcon#about to read 4, iclass 39, count 2 2006.169.08:13:44.92#ibcon#read 4, iclass 39, count 2 2006.169.08:13:44.92#ibcon#about to read 5, iclass 39, count 2 2006.169.08:13:44.92#ibcon#read 5, iclass 39, count 2 2006.169.08:13:44.92#ibcon#about to read 6, iclass 39, count 2 2006.169.08:13:44.92#ibcon#read 6, iclass 39, count 2 2006.169.08:13:44.92#ibcon#end of sib2, iclass 39, count 2 2006.169.08:13:44.92#ibcon#*after write, iclass 39, count 2 2006.169.08:13:44.92#ibcon#*before return 0, iclass 39, count 2 2006.169.08:13:44.92#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.169.08:13:44.92#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.169.08:13:44.92#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.169.08:13:44.92#ibcon#ireg 7 cls_cnt 0 2006.169.08:13:44.92#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.169.08:13:45.05#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.169.08:13:45.05#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.169.08:13:45.05#ibcon#enter wrdev, iclass 39, count 0 2006.169.08:13:45.05#ibcon#first serial, iclass 39, count 0 2006.169.08:13:45.05#ibcon#enter sib2, iclass 39, count 0 2006.169.08:13:45.05#ibcon#flushed, iclass 39, count 0 2006.169.08:13:45.05#ibcon#about to write, iclass 39, count 0 2006.169.08:13:45.05#ibcon#wrote, iclass 39, count 0 2006.169.08:13:45.05#ibcon#about to read 3, iclass 39, count 0 2006.169.08:13:45.07#ibcon#read 3, iclass 39, count 0 2006.169.08:13:45.07#ibcon#about to read 4, iclass 39, count 0 2006.169.08:13:45.07#ibcon#read 4, iclass 39, count 0 2006.169.08:13:45.07#ibcon#about to read 5, iclass 39, count 0 2006.169.08:13:45.07#ibcon#read 5, iclass 39, count 0 2006.169.08:13:45.07#ibcon#about to read 6, iclass 39, count 0 2006.169.08:13:45.07#ibcon#read 6, iclass 39, count 0 2006.169.08:13:45.07#ibcon#end of sib2, iclass 39, count 0 2006.169.08:13:45.07#ibcon#*mode == 0, iclass 39, count 0 2006.169.08:13:45.07#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.169.08:13:45.07#ibcon#[25=USB\r\n] 2006.169.08:13:45.07#ibcon#*before write, iclass 39, count 0 2006.169.08:13:45.07#ibcon#enter sib2, iclass 39, count 0 2006.169.08:13:45.07#ibcon#flushed, iclass 39, count 0 2006.169.08:13:45.07#ibcon#about to write, iclass 39, count 0 2006.169.08:13:45.07#ibcon#wrote, iclass 39, count 0 2006.169.08:13:45.07#ibcon#about to read 3, iclass 39, count 0 2006.169.08:13:45.10#ibcon#read 3, iclass 39, count 0 2006.169.08:13:45.10#ibcon#about to read 4, iclass 39, count 0 2006.169.08:13:45.10#ibcon#read 4, iclass 39, count 0 2006.169.08:13:45.10#ibcon#about to read 5, iclass 39, count 0 2006.169.08:13:45.10#ibcon#read 5, iclass 39, count 0 2006.169.08:13:45.10#ibcon#about to read 6, iclass 39, count 0 2006.169.08:13:45.10#ibcon#read 6, iclass 39, count 0 2006.169.08:13:45.10#ibcon#end of sib2, iclass 39, count 0 2006.169.08:13:45.10#ibcon#*after write, iclass 39, count 0 2006.169.08:13:45.10#ibcon#*before return 0, iclass 39, count 0 2006.169.08:13:45.10#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.169.08:13:45.10#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.169.08:13:45.10#ibcon#about to clear, iclass 39 cls_cnt 0 2006.169.08:13:45.10#ibcon#cleared, iclass 39 cls_cnt 0 2006.169.08:13:45.10$vc4f8/valo=2,572.99 2006.169.08:13:45.10#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.169.08:13:45.10#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.169.08:13:45.10#ibcon#ireg 17 cls_cnt 0 2006.169.08:13:45.10#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.169.08:13:45.10#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.169.08:13:45.10#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.169.08:13:45.10#ibcon#enter wrdev, iclass 3, count 0 2006.169.08:13:45.10#ibcon#first serial, iclass 3, count 0 2006.169.08:13:45.10#ibcon#enter sib2, iclass 3, count 0 2006.169.08:13:45.10#ibcon#flushed, iclass 3, count 0 2006.169.08:13:45.10#ibcon#about to write, iclass 3, count 0 2006.169.08:13:45.10#ibcon#wrote, iclass 3, count 0 2006.169.08:13:45.10#ibcon#about to read 3, iclass 3, count 0 2006.169.08:13:45.12#ibcon#read 3, iclass 3, count 0 2006.169.08:13:45.12#ibcon#about to read 4, iclass 3, count 0 2006.169.08:13:45.12#ibcon#read 4, iclass 3, count 0 2006.169.08:13:45.12#ibcon#about to read 5, iclass 3, count 0 2006.169.08:13:45.12#ibcon#read 5, iclass 3, count 0 2006.169.08:13:45.12#ibcon#about to read 6, iclass 3, count 0 2006.169.08:13:45.12#ibcon#read 6, iclass 3, count 0 2006.169.08:13:45.12#ibcon#end of sib2, iclass 3, count 0 2006.169.08:13:45.12#ibcon#*mode == 0, iclass 3, count 0 2006.169.08:13:45.12#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.169.08:13:45.12#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.08:13:45.12#ibcon#*before write, iclass 3, count 0 2006.169.08:13:45.12#ibcon#enter sib2, iclass 3, count 0 2006.169.08:13:45.12#ibcon#flushed, iclass 3, count 0 2006.169.08:13:45.12#ibcon#about to write, iclass 3, count 0 2006.169.08:13:45.12#ibcon#wrote, iclass 3, count 0 2006.169.08:13:45.12#ibcon#about to read 3, iclass 3, count 0 2006.169.08:13:45.14#flagr#flagr/antenna,acquired 2006.169.08:13:45.16#ibcon#read 3, iclass 3, count 0 2006.169.08:13:45.16#ibcon#about to read 4, iclass 3, count 0 2006.169.08:13:45.16#ibcon#read 4, iclass 3, count 0 2006.169.08:13:45.16#ibcon#about to read 5, iclass 3, count 0 2006.169.08:13:45.16#ibcon#read 5, iclass 3, count 0 2006.169.08:13:45.16#ibcon#about to read 6, iclass 3, count 0 2006.169.08:13:45.16#ibcon#read 6, iclass 3, count 0 2006.169.08:13:45.16#ibcon#end of sib2, iclass 3, count 0 2006.169.08:13:45.16#ibcon#*after write, iclass 3, count 0 2006.169.08:13:45.16#ibcon#*before return 0, iclass 3, count 0 2006.169.08:13:45.16#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.169.08:13:45.16#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.169.08:13:45.16#ibcon#about to clear, iclass 3 cls_cnt 0 2006.169.08:13:45.16#ibcon#cleared, iclass 3 cls_cnt 0 2006.169.08:13:45.16$vc4f8/va=2,7 2006.169.08:13:45.16#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.169.08:13:45.16#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.169.08:13:45.16#ibcon#ireg 11 cls_cnt 2 2006.169.08:13:45.16#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.169.08:13:45.22#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.169.08:13:45.22#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.169.08:13:45.22#ibcon#enter wrdev, iclass 5, count 2 2006.169.08:13:45.22#ibcon#first serial, iclass 5, count 2 2006.169.08:13:45.22#ibcon#enter sib2, iclass 5, count 2 2006.169.08:13:45.22#ibcon#flushed, iclass 5, count 2 2006.169.08:13:45.22#ibcon#about to write, iclass 5, count 2 2006.169.08:13:45.22#ibcon#wrote, iclass 5, count 2 2006.169.08:13:45.22#ibcon#about to read 3, iclass 5, count 2 2006.169.08:13:45.24#ibcon#read 3, iclass 5, count 2 2006.169.08:13:45.24#ibcon#about to read 4, iclass 5, count 2 2006.169.08:13:45.24#ibcon#read 4, iclass 5, count 2 2006.169.08:13:45.24#ibcon#about to read 5, iclass 5, count 2 2006.169.08:13:45.24#ibcon#read 5, iclass 5, count 2 2006.169.08:13:45.24#ibcon#about to read 6, iclass 5, count 2 2006.169.08:13:45.24#ibcon#read 6, iclass 5, count 2 2006.169.08:13:45.24#ibcon#end of sib2, iclass 5, count 2 2006.169.08:13:45.24#ibcon#*mode == 0, iclass 5, count 2 2006.169.08:13:45.24#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.169.08:13:45.24#ibcon#[25=AT02-07\r\n] 2006.169.08:13:45.24#ibcon#*before write, iclass 5, count 2 2006.169.08:13:45.24#ibcon#enter sib2, iclass 5, count 2 2006.169.08:13:45.24#ibcon#flushed, iclass 5, count 2 2006.169.08:13:45.24#ibcon#about to write, iclass 5, count 2 2006.169.08:13:45.24#ibcon#wrote, iclass 5, count 2 2006.169.08:13:45.24#ibcon#about to read 3, iclass 5, count 2 2006.169.08:13:45.28#ibcon#read 3, iclass 5, count 2 2006.169.08:13:45.28#ibcon#about to read 4, iclass 5, count 2 2006.169.08:13:45.28#ibcon#read 4, iclass 5, count 2 2006.169.08:13:45.28#ibcon#about to read 5, iclass 5, count 2 2006.169.08:13:45.28#ibcon#read 5, iclass 5, count 2 2006.169.08:13:45.28#ibcon#about to read 6, iclass 5, count 2 2006.169.08:13:45.28#ibcon#read 6, iclass 5, count 2 2006.169.08:13:45.28#ibcon#end of sib2, iclass 5, count 2 2006.169.08:13:45.28#ibcon#*after write, iclass 5, count 2 2006.169.08:13:45.28#ibcon#*before return 0, iclass 5, count 2 2006.169.08:13:45.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.169.08:13:45.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.169.08:13:45.28#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.169.08:13:45.28#ibcon#ireg 7 cls_cnt 0 2006.169.08:13:45.28#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.169.08:13:45.40#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.169.08:13:45.40#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.169.08:13:45.40#ibcon#enter wrdev, iclass 5, count 0 2006.169.08:13:45.40#ibcon#first serial, iclass 5, count 0 2006.169.08:13:45.40#ibcon#enter sib2, iclass 5, count 0 2006.169.08:13:45.40#ibcon#flushed, iclass 5, count 0 2006.169.08:13:45.40#ibcon#about to write, iclass 5, count 0 2006.169.08:13:45.40#ibcon#wrote, iclass 5, count 0 2006.169.08:13:45.40#ibcon#about to read 3, iclass 5, count 0 2006.169.08:13:45.42#ibcon#read 3, iclass 5, count 0 2006.169.08:13:45.42#ibcon#about to read 4, iclass 5, count 0 2006.169.08:13:45.42#ibcon#read 4, iclass 5, count 0 2006.169.08:13:45.42#ibcon#about to read 5, iclass 5, count 0 2006.169.08:13:45.42#ibcon#read 5, iclass 5, count 0 2006.169.08:13:45.42#ibcon#about to read 6, iclass 5, count 0 2006.169.08:13:45.42#ibcon#read 6, iclass 5, count 0 2006.169.08:13:45.42#ibcon#end of sib2, iclass 5, count 0 2006.169.08:13:45.42#ibcon#*mode == 0, iclass 5, count 0 2006.169.08:13:45.42#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.169.08:13:45.42#ibcon#[25=USB\r\n] 2006.169.08:13:45.42#ibcon#*before write, iclass 5, count 0 2006.169.08:13:45.42#ibcon#enter sib2, iclass 5, count 0 2006.169.08:13:45.42#ibcon#flushed, iclass 5, count 0 2006.169.08:13:45.42#ibcon#about to write, iclass 5, count 0 2006.169.08:13:45.42#ibcon#wrote, iclass 5, count 0 2006.169.08:13:45.42#ibcon#about to read 3, iclass 5, count 0 2006.169.08:13:45.45#ibcon#read 3, iclass 5, count 0 2006.169.08:13:45.45#ibcon#about to read 4, iclass 5, count 0 2006.169.08:13:45.45#ibcon#read 4, iclass 5, count 0 2006.169.08:13:45.45#ibcon#about to read 5, iclass 5, count 0 2006.169.08:13:45.45#ibcon#read 5, iclass 5, count 0 2006.169.08:13:45.45#ibcon#about to read 6, iclass 5, count 0 2006.169.08:13:45.45#ibcon#read 6, iclass 5, count 0 2006.169.08:13:45.45#ibcon#end of sib2, iclass 5, count 0 2006.169.08:13:45.45#ibcon#*after write, iclass 5, count 0 2006.169.08:13:45.45#ibcon#*before return 0, iclass 5, count 0 2006.169.08:13:45.45#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.169.08:13:45.45#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.169.08:13:45.45#ibcon#about to clear, iclass 5 cls_cnt 0 2006.169.08:13:45.45#ibcon#cleared, iclass 5 cls_cnt 0 2006.169.08:13:45.45$vc4f8/valo=3,672.99 2006.169.08:13:45.45#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.169.08:13:45.45#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.169.08:13:45.45#ibcon#ireg 17 cls_cnt 0 2006.169.08:13:45.45#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.169.08:13:45.45#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.169.08:13:45.45#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.169.08:13:45.45#ibcon#enter wrdev, iclass 7, count 0 2006.169.08:13:45.45#ibcon#first serial, iclass 7, count 0 2006.169.08:13:45.45#ibcon#enter sib2, iclass 7, count 0 2006.169.08:13:45.45#ibcon#flushed, iclass 7, count 0 2006.169.08:13:45.45#ibcon#about to write, iclass 7, count 0 2006.169.08:13:45.45#ibcon#wrote, iclass 7, count 0 2006.169.08:13:45.45#ibcon#about to read 3, iclass 7, count 0 2006.169.08:13:45.47#ibcon#read 3, iclass 7, count 0 2006.169.08:13:45.47#ibcon#about to read 4, iclass 7, count 0 2006.169.08:13:45.47#ibcon#read 4, iclass 7, count 0 2006.169.08:13:45.47#ibcon#about to read 5, iclass 7, count 0 2006.169.08:13:45.47#ibcon#read 5, iclass 7, count 0 2006.169.08:13:45.47#ibcon#about to read 6, iclass 7, count 0 2006.169.08:13:45.47#ibcon#read 6, iclass 7, count 0 2006.169.08:13:45.47#ibcon#end of sib2, iclass 7, count 0 2006.169.08:13:45.47#ibcon#*mode == 0, iclass 7, count 0 2006.169.08:13:45.47#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.169.08:13:45.47#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.08:13:45.47#ibcon#*before write, iclass 7, count 0 2006.169.08:13:45.47#ibcon#enter sib2, iclass 7, count 0 2006.169.08:13:45.47#ibcon#flushed, iclass 7, count 0 2006.169.08:13:45.47#ibcon#about to write, iclass 7, count 0 2006.169.08:13:45.47#ibcon#wrote, iclass 7, count 0 2006.169.08:13:45.47#ibcon#about to read 3, iclass 7, count 0 2006.169.08:13:45.51#ibcon#read 3, iclass 7, count 0 2006.169.08:13:45.51#ibcon#about to read 4, iclass 7, count 0 2006.169.08:13:45.51#ibcon#read 4, iclass 7, count 0 2006.169.08:13:45.51#ibcon#about to read 5, iclass 7, count 0 2006.169.08:13:45.51#ibcon#read 5, iclass 7, count 0 2006.169.08:13:45.51#ibcon#about to read 6, iclass 7, count 0 2006.169.08:13:45.51#ibcon#read 6, iclass 7, count 0 2006.169.08:13:45.51#ibcon#end of sib2, iclass 7, count 0 2006.169.08:13:45.51#ibcon#*after write, iclass 7, count 0 2006.169.08:13:45.51#ibcon#*before return 0, iclass 7, count 0 2006.169.08:13:45.51#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.169.08:13:45.51#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.169.08:13:45.51#ibcon#about to clear, iclass 7 cls_cnt 0 2006.169.08:13:45.51#ibcon#cleared, iclass 7 cls_cnt 0 2006.169.08:13:45.51$vc4f8/va=3,6 2006.169.08:13:45.51#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.169.08:13:45.51#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.169.08:13:45.51#ibcon#ireg 11 cls_cnt 2 2006.169.08:13:45.51#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.169.08:13:45.57#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.169.08:13:45.57#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.169.08:13:45.57#ibcon#enter wrdev, iclass 11, count 2 2006.169.08:13:45.57#ibcon#first serial, iclass 11, count 2 2006.169.08:13:45.57#ibcon#enter sib2, iclass 11, count 2 2006.169.08:13:45.57#ibcon#flushed, iclass 11, count 2 2006.169.08:13:45.57#ibcon#about to write, iclass 11, count 2 2006.169.08:13:45.57#ibcon#wrote, iclass 11, count 2 2006.169.08:13:45.57#ibcon#about to read 3, iclass 11, count 2 2006.169.08:13:45.59#ibcon#read 3, iclass 11, count 2 2006.169.08:13:45.59#ibcon#about to read 4, iclass 11, count 2 2006.169.08:13:45.59#ibcon#read 4, iclass 11, count 2 2006.169.08:13:45.59#ibcon#about to read 5, iclass 11, count 2 2006.169.08:13:45.59#ibcon#read 5, iclass 11, count 2 2006.169.08:13:45.59#ibcon#about to read 6, iclass 11, count 2 2006.169.08:13:45.59#ibcon#read 6, iclass 11, count 2 2006.169.08:13:45.59#ibcon#end of sib2, iclass 11, count 2 2006.169.08:13:45.59#ibcon#*mode == 0, iclass 11, count 2 2006.169.08:13:45.59#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.169.08:13:45.59#ibcon#[25=AT03-06\r\n] 2006.169.08:13:45.59#ibcon#*before write, iclass 11, count 2 2006.169.08:13:45.59#ibcon#enter sib2, iclass 11, count 2 2006.169.08:13:45.59#ibcon#flushed, iclass 11, count 2 2006.169.08:13:45.59#ibcon#about to write, iclass 11, count 2 2006.169.08:13:45.59#ibcon#wrote, iclass 11, count 2 2006.169.08:13:45.59#ibcon#about to read 3, iclass 11, count 2 2006.169.08:13:45.62#ibcon#read 3, iclass 11, count 2 2006.169.08:13:45.62#ibcon#about to read 4, iclass 11, count 2 2006.169.08:13:45.62#ibcon#read 4, iclass 11, count 2 2006.169.08:13:45.62#ibcon#about to read 5, iclass 11, count 2 2006.169.08:13:45.62#ibcon#read 5, iclass 11, count 2 2006.169.08:13:45.62#ibcon#about to read 6, iclass 11, count 2 2006.169.08:13:45.62#ibcon#read 6, iclass 11, count 2 2006.169.08:13:45.62#ibcon#end of sib2, iclass 11, count 2 2006.169.08:13:45.62#ibcon#*after write, iclass 11, count 2 2006.169.08:13:45.62#ibcon#*before return 0, iclass 11, count 2 2006.169.08:13:45.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.169.08:13:45.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.169.08:13:45.62#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.169.08:13:45.62#ibcon#ireg 7 cls_cnt 0 2006.169.08:13:45.62#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.169.08:13:45.74#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.169.08:13:45.74#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.169.08:13:45.74#ibcon#enter wrdev, iclass 11, count 0 2006.169.08:13:45.74#ibcon#first serial, iclass 11, count 0 2006.169.08:13:45.74#ibcon#enter sib2, iclass 11, count 0 2006.169.08:13:45.74#ibcon#flushed, iclass 11, count 0 2006.169.08:13:45.74#ibcon#about to write, iclass 11, count 0 2006.169.08:13:45.74#ibcon#wrote, iclass 11, count 0 2006.169.08:13:45.74#ibcon#about to read 3, iclass 11, count 0 2006.169.08:13:45.76#ibcon#read 3, iclass 11, count 0 2006.169.08:13:45.76#ibcon#about to read 4, iclass 11, count 0 2006.169.08:13:45.76#ibcon#read 4, iclass 11, count 0 2006.169.08:13:45.76#ibcon#about to read 5, iclass 11, count 0 2006.169.08:13:45.76#ibcon#read 5, iclass 11, count 0 2006.169.08:13:45.76#ibcon#about to read 6, iclass 11, count 0 2006.169.08:13:45.76#ibcon#read 6, iclass 11, count 0 2006.169.08:13:45.76#ibcon#end of sib2, iclass 11, count 0 2006.169.08:13:45.76#ibcon#*mode == 0, iclass 11, count 0 2006.169.08:13:45.76#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.169.08:13:45.76#ibcon#[25=USB\r\n] 2006.169.08:13:45.76#ibcon#*before write, iclass 11, count 0 2006.169.08:13:45.76#ibcon#enter sib2, iclass 11, count 0 2006.169.08:13:45.76#ibcon#flushed, iclass 11, count 0 2006.169.08:13:45.76#ibcon#about to write, iclass 11, count 0 2006.169.08:13:45.76#ibcon#wrote, iclass 11, count 0 2006.169.08:13:45.76#ibcon#about to read 3, iclass 11, count 0 2006.169.08:13:45.79#ibcon#read 3, iclass 11, count 0 2006.169.08:13:45.79#ibcon#about to read 4, iclass 11, count 0 2006.169.08:13:45.79#ibcon#read 4, iclass 11, count 0 2006.169.08:13:45.79#ibcon#about to read 5, iclass 11, count 0 2006.169.08:13:45.79#ibcon#read 5, iclass 11, count 0 2006.169.08:13:45.79#ibcon#about to read 6, iclass 11, count 0 2006.169.08:13:45.79#ibcon#read 6, iclass 11, count 0 2006.169.08:13:45.79#ibcon#end of sib2, iclass 11, count 0 2006.169.08:13:45.79#ibcon#*after write, iclass 11, count 0 2006.169.08:13:45.79#ibcon#*before return 0, iclass 11, count 0 2006.169.08:13:45.79#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.169.08:13:45.79#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.169.08:13:45.79#ibcon#about to clear, iclass 11 cls_cnt 0 2006.169.08:13:45.79#ibcon#cleared, iclass 11 cls_cnt 0 2006.169.08:13:45.79$vc4f8/valo=4,832.99 2006.169.08:13:45.79#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.169.08:13:45.79#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.169.08:13:45.79#ibcon#ireg 17 cls_cnt 0 2006.169.08:13:45.79#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:13:45.79#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:13:45.79#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:13:45.79#ibcon#enter wrdev, iclass 13, count 0 2006.169.08:13:45.79#ibcon#first serial, iclass 13, count 0 2006.169.08:13:45.79#ibcon#enter sib2, iclass 13, count 0 2006.169.08:13:45.79#ibcon#flushed, iclass 13, count 0 2006.169.08:13:45.79#ibcon#about to write, iclass 13, count 0 2006.169.08:13:45.79#ibcon#wrote, iclass 13, count 0 2006.169.08:13:45.79#ibcon#about to read 3, iclass 13, count 0 2006.169.08:13:45.81#ibcon#read 3, iclass 13, count 0 2006.169.08:13:45.81#ibcon#about to read 4, iclass 13, count 0 2006.169.08:13:45.81#ibcon#read 4, iclass 13, count 0 2006.169.08:13:45.81#ibcon#about to read 5, iclass 13, count 0 2006.169.08:13:45.81#ibcon#read 5, iclass 13, count 0 2006.169.08:13:45.81#ibcon#about to read 6, iclass 13, count 0 2006.169.08:13:45.81#ibcon#read 6, iclass 13, count 0 2006.169.08:13:45.81#ibcon#end of sib2, iclass 13, count 0 2006.169.08:13:45.81#ibcon#*mode == 0, iclass 13, count 0 2006.169.08:13:45.81#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.08:13:45.81#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.08:13:45.81#ibcon#*before write, iclass 13, count 0 2006.169.08:13:45.81#ibcon#enter sib2, iclass 13, count 0 2006.169.08:13:45.81#ibcon#flushed, iclass 13, count 0 2006.169.08:13:45.81#ibcon#about to write, iclass 13, count 0 2006.169.08:13:45.81#ibcon#wrote, iclass 13, count 0 2006.169.08:13:45.81#ibcon#about to read 3, iclass 13, count 0 2006.169.08:13:45.85#ibcon#read 3, iclass 13, count 0 2006.169.08:13:45.85#ibcon#about to read 4, iclass 13, count 0 2006.169.08:13:45.85#ibcon#read 4, iclass 13, count 0 2006.169.08:13:45.85#ibcon#about to read 5, iclass 13, count 0 2006.169.08:13:45.85#ibcon#read 5, iclass 13, count 0 2006.169.08:13:45.85#ibcon#about to read 6, iclass 13, count 0 2006.169.08:13:45.85#ibcon#read 6, iclass 13, count 0 2006.169.08:13:45.85#ibcon#end of sib2, iclass 13, count 0 2006.169.08:13:45.85#ibcon#*after write, iclass 13, count 0 2006.169.08:13:45.85#ibcon#*before return 0, iclass 13, count 0 2006.169.08:13:45.85#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:13:45.85#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:13:45.85#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.08:13:45.85#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.08:13:45.85$vc4f8/va=4,7 2006.169.08:13:45.85#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.169.08:13:45.85#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.169.08:13:45.85#ibcon#ireg 11 cls_cnt 2 2006.169.08:13:45.85#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.169.08:13:45.91#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.169.08:13:45.91#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.169.08:13:45.91#ibcon#enter wrdev, iclass 15, count 2 2006.169.08:13:45.91#ibcon#first serial, iclass 15, count 2 2006.169.08:13:45.91#ibcon#enter sib2, iclass 15, count 2 2006.169.08:13:45.91#ibcon#flushed, iclass 15, count 2 2006.169.08:13:45.91#ibcon#about to write, iclass 15, count 2 2006.169.08:13:45.91#ibcon#wrote, iclass 15, count 2 2006.169.08:13:45.91#ibcon#about to read 3, iclass 15, count 2 2006.169.08:13:45.93#ibcon#read 3, iclass 15, count 2 2006.169.08:13:45.93#ibcon#about to read 4, iclass 15, count 2 2006.169.08:13:45.93#ibcon#read 4, iclass 15, count 2 2006.169.08:13:45.93#ibcon#about to read 5, iclass 15, count 2 2006.169.08:13:45.93#ibcon#read 5, iclass 15, count 2 2006.169.08:13:45.93#ibcon#about to read 6, iclass 15, count 2 2006.169.08:13:45.93#ibcon#read 6, iclass 15, count 2 2006.169.08:13:45.93#ibcon#end of sib2, iclass 15, count 2 2006.169.08:13:45.93#ibcon#*mode == 0, iclass 15, count 2 2006.169.08:13:45.93#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.169.08:13:45.93#ibcon#[25=AT04-07\r\n] 2006.169.08:13:45.93#ibcon#*before write, iclass 15, count 2 2006.169.08:13:45.93#ibcon#enter sib2, iclass 15, count 2 2006.169.08:13:45.93#ibcon#flushed, iclass 15, count 2 2006.169.08:13:45.93#ibcon#about to write, iclass 15, count 2 2006.169.08:13:45.93#ibcon#wrote, iclass 15, count 2 2006.169.08:13:45.93#ibcon#about to read 3, iclass 15, count 2 2006.169.08:13:45.96#ibcon#read 3, iclass 15, count 2 2006.169.08:13:45.96#ibcon#about to read 4, iclass 15, count 2 2006.169.08:13:45.96#ibcon#read 4, iclass 15, count 2 2006.169.08:13:45.96#ibcon#about to read 5, iclass 15, count 2 2006.169.08:13:45.96#ibcon#read 5, iclass 15, count 2 2006.169.08:13:45.96#ibcon#about to read 6, iclass 15, count 2 2006.169.08:13:45.96#ibcon#read 6, iclass 15, count 2 2006.169.08:13:45.96#ibcon#end of sib2, iclass 15, count 2 2006.169.08:13:45.96#ibcon#*after write, iclass 15, count 2 2006.169.08:13:45.96#ibcon#*before return 0, iclass 15, count 2 2006.169.08:13:45.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.169.08:13:45.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.169.08:13:45.96#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.169.08:13:45.96#ibcon#ireg 7 cls_cnt 0 2006.169.08:13:45.96#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.169.08:13:46.08#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.169.08:13:46.08#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.169.08:13:46.08#ibcon#enter wrdev, iclass 15, count 0 2006.169.08:13:46.08#ibcon#first serial, iclass 15, count 0 2006.169.08:13:46.08#ibcon#enter sib2, iclass 15, count 0 2006.169.08:13:46.08#ibcon#flushed, iclass 15, count 0 2006.169.08:13:46.08#ibcon#about to write, iclass 15, count 0 2006.169.08:13:46.08#ibcon#wrote, iclass 15, count 0 2006.169.08:13:46.08#ibcon#about to read 3, iclass 15, count 0 2006.169.08:13:46.10#ibcon#read 3, iclass 15, count 0 2006.169.08:13:46.10#ibcon#about to read 4, iclass 15, count 0 2006.169.08:13:46.10#ibcon#read 4, iclass 15, count 0 2006.169.08:13:46.10#ibcon#about to read 5, iclass 15, count 0 2006.169.08:13:46.10#ibcon#read 5, iclass 15, count 0 2006.169.08:13:46.10#ibcon#about to read 6, iclass 15, count 0 2006.169.08:13:46.10#ibcon#read 6, iclass 15, count 0 2006.169.08:13:46.10#ibcon#end of sib2, iclass 15, count 0 2006.169.08:13:46.10#ibcon#*mode == 0, iclass 15, count 0 2006.169.08:13:46.10#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.169.08:13:46.10#ibcon#[25=USB\r\n] 2006.169.08:13:46.10#ibcon#*before write, iclass 15, count 0 2006.169.08:13:46.10#ibcon#enter sib2, iclass 15, count 0 2006.169.08:13:46.10#ibcon#flushed, iclass 15, count 0 2006.169.08:13:46.10#ibcon#about to write, iclass 15, count 0 2006.169.08:13:46.10#ibcon#wrote, iclass 15, count 0 2006.169.08:13:46.10#ibcon#about to read 3, iclass 15, count 0 2006.169.08:13:46.13#ibcon#read 3, iclass 15, count 0 2006.169.08:13:46.13#ibcon#about to read 4, iclass 15, count 0 2006.169.08:13:46.13#ibcon#read 4, iclass 15, count 0 2006.169.08:13:46.13#ibcon#about to read 5, iclass 15, count 0 2006.169.08:13:46.13#ibcon#read 5, iclass 15, count 0 2006.169.08:13:46.13#ibcon#about to read 6, iclass 15, count 0 2006.169.08:13:46.13#ibcon#read 6, iclass 15, count 0 2006.169.08:13:46.13#ibcon#end of sib2, iclass 15, count 0 2006.169.08:13:46.13#ibcon#*after write, iclass 15, count 0 2006.169.08:13:46.13#ibcon#*before return 0, iclass 15, count 0 2006.169.08:13:46.13#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.169.08:13:46.13#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.169.08:13:46.13#ibcon#about to clear, iclass 15 cls_cnt 0 2006.169.08:13:46.13#ibcon#cleared, iclass 15 cls_cnt 0 2006.169.08:13:46.13$vc4f8/valo=5,652.99 2006.169.08:13:46.13#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.169.08:13:46.13#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.169.08:13:46.13#ibcon#ireg 17 cls_cnt 0 2006.169.08:13:46.13#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:13:46.13#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:13:46.13#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:13:46.13#ibcon#enter wrdev, iclass 17, count 0 2006.169.08:13:46.13#ibcon#first serial, iclass 17, count 0 2006.169.08:13:46.13#ibcon#enter sib2, iclass 17, count 0 2006.169.08:13:46.13#ibcon#flushed, iclass 17, count 0 2006.169.08:13:46.13#ibcon#about to write, iclass 17, count 0 2006.169.08:13:46.13#ibcon#wrote, iclass 17, count 0 2006.169.08:13:46.13#ibcon#about to read 3, iclass 17, count 0 2006.169.08:13:46.15#ibcon#read 3, iclass 17, count 0 2006.169.08:13:46.15#ibcon#about to read 4, iclass 17, count 0 2006.169.08:13:46.15#ibcon#read 4, iclass 17, count 0 2006.169.08:13:46.15#ibcon#about to read 5, iclass 17, count 0 2006.169.08:13:46.15#ibcon#read 5, iclass 17, count 0 2006.169.08:13:46.15#ibcon#about to read 6, iclass 17, count 0 2006.169.08:13:46.15#ibcon#read 6, iclass 17, count 0 2006.169.08:13:46.15#ibcon#end of sib2, iclass 17, count 0 2006.169.08:13:46.15#ibcon#*mode == 0, iclass 17, count 0 2006.169.08:13:46.15#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.169.08:13:46.15#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.08:13:46.15#ibcon#*before write, iclass 17, count 0 2006.169.08:13:46.15#ibcon#enter sib2, iclass 17, count 0 2006.169.08:13:46.15#ibcon#flushed, iclass 17, count 0 2006.169.08:13:46.15#ibcon#about to write, iclass 17, count 0 2006.169.08:13:46.15#ibcon#wrote, iclass 17, count 0 2006.169.08:13:46.15#ibcon#about to read 3, iclass 17, count 0 2006.169.08:13:46.19#ibcon#read 3, iclass 17, count 0 2006.169.08:13:46.19#ibcon#about to read 4, iclass 17, count 0 2006.169.08:13:46.19#ibcon#read 4, iclass 17, count 0 2006.169.08:13:46.19#ibcon#about to read 5, iclass 17, count 0 2006.169.08:13:46.19#ibcon#read 5, iclass 17, count 0 2006.169.08:13:46.19#ibcon#about to read 6, iclass 17, count 0 2006.169.08:13:46.19#ibcon#read 6, iclass 17, count 0 2006.169.08:13:46.19#ibcon#end of sib2, iclass 17, count 0 2006.169.08:13:46.19#ibcon#*after write, iclass 17, count 0 2006.169.08:13:46.19#ibcon#*before return 0, iclass 17, count 0 2006.169.08:13:46.19#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:13:46.19#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:13:46.19#ibcon#about to clear, iclass 17 cls_cnt 0 2006.169.08:13:46.19#ibcon#cleared, iclass 17 cls_cnt 0 2006.169.08:13:46.19$vc4f8/va=5,7 2006.169.08:13:46.19#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.169.08:13:46.19#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.169.08:13:46.19#ibcon#ireg 11 cls_cnt 2 2006.169.08:13:46.19#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.169.08:13:46.25#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.169.08:13:46.25#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.169.08:13:46.25#ibcon#enter wrdev, iclass 19, count 2 2006.169.08:13:46.25#ibcon#first serial, iclass 19, count 2 2006.169.08:13:46.25#ibcon#enter sib2, iclass 19, count 2 2006.169.08:13:46.25#ibcon#flushed, iclass 19, count 2 2006.169.08:13:46.25#ibcon#about to write, iclass 19, count 2 2006.169.08:13:46.25#ibcon#wrote, iclass 19, count 2 2006.169.08:13:46.25#ibcon#about to read 3, iclass 19, count 2 2006.169.08:13:46.27#ibcon#read 3, iclass 19, count 2 2006.169.08:13:46.27#ibcon#about to read 4, iclass 19, count 2 2006.169.08:13:46.27#ibcon#read 4, iclass 19, count 2 2006.169.08:13:46.27#ibcon#about to read 5, iclass 19, count 2 2006.169.08:13:46.27#ibcon#read 5, iclass 19, count 2 2006.169.08:13:46.27#ibcon#about to read 6, iclass 19, count 2 2006.169.08:13:46.27#ibcon#read 6, iclass 19, count 2 2006.169.08:13:46.27#ibcon#end of sib2, iclass 19, count 2 2006.169.08:13:46.27#ibcon#*mode == 0, iclass 19, count 2 2006.169.08:13:46.27#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.169.08:13:46.27#ibcon#[25=AT05-07\r\n] 2006.169.08:13:46.27#ibcon#*before write, iclass 19, count 2 2006.169.08:13:46.27#ibcon#enter sib2, iclass 19, count 2 2006.169.08:13:46.27#ibcon#flushed, iclass 19, count 2 2006.169.08:13:46.27#ibcon#about to write, iclass 19, count 2 2006.169.08:13:46.27#ibcon#wrote, iclass 19, count 2 2006.169.08:13:46.27#ibcon#about to read 3, iclass 19, count 2 2006.169.08:13:46.30#ibcon#read 3, iclass 19, count 2 2006.169.08:13:46.30#ibcon#about to read 4, iclass 19, count 2 2006.169.08:13:46.30#ibcon#read 4, iclass 19, count 2 2006.169.08:13:46.30#ibcon#about to read 5, iclass 19, count 2 2006.169.08:13:46.30#ibcon#read 5, iclass 19, count 2 2006.169.08:13:46.30#ibcon#about to read 6, iclass 19, count 2 2006.169.08:13:46.30#ibcon#read 6, iclass 19, count 2 2006.169.08:13:46.30#ibcon#end of sib2, iclass 19, count 2 2006.169.08:13:46.30#ibcon#*after write, iclass 19, count 2 2006.169.08:13:46.30#ibcon#*before return 0, iclass 19, count 2 2006.169.08:13:46.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.169.08:13:46.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.169.08:13:46.30#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.169.08:13:46.30#ibcon#ireg 7 cls_cnt 0 2006.169.08:13:46.30#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.169.08:13:46.42#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.169.08:13:46.42#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.169.08:13:46.42#ibcon#enter wrdev, iclass 19, count 0 2006.169.08:13:46.42#ibcon#first serial, iclass 19, count 0 2006.169.08:13:46.42#ibcon#enter sib2, iclass 19, count 0 2006.169.08:13:46.42#ibcon#flushed, iclass 19, count 0 2006.169.08:13:46.42#ibcon#about to write, iclass 19, count 0 2006.169.08:13:46.42#ibcon#wrote, iclass 19, count 0 2006.169.08:13:46.42#ibcon#about to read 3, iclass 19, count 0 2006.169.08:13:46.44#ibcon#read 3, iclass 19, count 0 2006.169.08:13:46.44#ibcon#about to read 4, iclass 19, count 0 2006.169.08:13:46.44#ibcon#read 4, iclass 19, count 0 2006.169.08:13:46.44#ibcon#about to read 5, iclass 19, count 0 2006.169.08:13:46.44#ibcon#read 5, iclass 19, count 0 2006.169.08:13:46.44#ibcon#about to read 6, iclass 19, count 0 2006.169.08:13:46.44#ibcon#read 6, iclass 19, count 0 2006.169.08:13:46.44#ibcon#end of sib2, iclass 19, count 0 2006.169.08:13:46.44#ibcon#*mode == 0, iclass 19, count 0 2006.169.08:13:46.44#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.169.08:13:46.44#ibcon#[25=USB\r\n] 2006.169.08:13:46.44#ibcon#*before write, iclass 19, count 0 2006.169.08:13:46.44#ibcon#enter sib2, iclass 19, count 0 2006.169.08:13:46.44#ibcon#flushed, iclass 19, count 0 2006.169.08:13:46.44#ibcon#about to write, iclass 19, count 0 2006.169.08:13:46.44#ibcon#wrote, iclass 19, count 0 2006.169.08:13:46.44#ibcon#about to read 3, iclass 19, count 0 2006.169.08:13:46.47#ibcon#read 3, iclass 19, count 0 2006.169.08:13:46.47#ibcon#about to read 4, iclass 19, count 0 2006.169.08:13:46.47#ibcon#read 4, iclass 19, count 0 2006.169.08:13:46.47#ibcon#about to read 5, iclass 19, count 0 2006.169.08:13:46.47#ibcon#read 5, iclass 19, count 0 2006.169.08:13:46.47#ibcon#about to read 6, iclass 19, count 0 2006.169.08:13:46.47#ibcon#read 6, iclass 19, count 0 2006.169.08:13:46.47#ibcon#end of sib2, iclass 19, count 0 2006.169.08:13:46.47#ibcon#*after write, iclass 19, count 0 2006.169.08:13:46.47#ibcon#*before return 0, iclass 19, count 0 2006.169.08:13:46.47#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.169.08:13:46.47#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.169.08:13:46.47#ibcon#about to clear, iclass 19 cls_cnt 0 2006.169.08:13:46.47#ibcon#cleared, iclass 19 cls_cnt 0 2006.169.08:13:46.47$vc4f8/valo=6,772.99 2006.169.08:13:46.47#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.169.08:13:46.47#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.169.08:13:46.47#ibcon#ireg 17 cls_cnt 0 2006.169.08:13:46.47#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.169.08:13:46.47#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.169.08:13:46.47#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.169.08:13:46.47#ibcon#enter wrdev, iclass 21, count 0 2006.169.08:13:46.47#ibcon#first serial, iclass 21, count 0 2006.169.08:13:46.47#ibcon#enter sib2, iclass 21, count 0 2006.169.08:13:46.47#ibcon#flushed, iclass 21, count 0 2006.169.08:13:46.47#ibcon#about to write, iclass 21, count 0 2006.169.08:13:46.47#ibcon#wrote, iclass 21, count 0 2006.169.08:13:46.47#ibcon#about to read 3, iclass 21, count 0 2006.169.08:13:46.49#ibcon#read 3, iclass 21, count 0 2006.169.08:13:46.49#ibcon#about to read 4, iclass 21, count 0 2006.169.08:13:46.49#ibcon#read 4, iclass 21, count 0 2006.169.08:13:46.49#ibcon#about to read 5, iclass 21, count 0 2006.169.08:13:46.49#ibcon#read 5, iclass 21, count 0 2006.169.08:13:46.49#ibcon#about to read 6, iclass 21, count 0 2006.169.08:13:46.49#ibcon#read 6, iclass 21, count 0 2006.169.08:13:46.49#ibcon#end of sib2, iclass 21, count 0 2006.169.08:13:46.49#ibcon#*mode == 0, iclass 21, count 0 2006.169.08:13:46.49#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.169.08:13:46.49#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.08:13:46.49#ibcon#*before write, iclass 21, count 0 2006.169.08:13:46.49#ibcon#enter sib2, iclass 21, count 0 2006.169.08:13:46.49#ibcon#flushed, iclass 21, count 0 2006.169.08:13:46.49#ibcon#about to write, iclass 21, count 0 2006.169.08:13:46.49#ibcon#wrote, iclass 21, count 0 2006.169.08:13:46.49#ibcon#about to read 3, iclass 21, count 0 2006.169.08:13:46.53#ibcon#read 3, iclass 21, count 0 2006.169.08:13:46.53#ibcon#about to read 4, iclass 21, count 0 2006.169.08:13:46.53#ibcon#read 4, iclass 21, count 0 2006.169.08:13:46.53#ibcon#about to read 5, iclass 21, count 0 2006.169.08:13:46.53#ibcon#read 5, iclass 21, count 0 2006.169.08:13:46.53#ibcon#about to read 6, iclass 21, count 0 2006.169.08:13:46.53#ibcon#read 6, iclass 21, count 0 2006.169.08:13:46.53#ibcon#end of sib2, iclass 21, count 0 2006.169.08:13:46.53#ibcon#*after write, iclass 21, count 0 2006.169.08:13:46.53#ibcon#*before return 0, iclass 21, count 0 2006.169.08:13:46.53#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.169.08:13:46.53#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.169.08:13:46.53#ibcon#about to clear, iclass 21 cls_cnt 0 2006.169.08:13:46.53#ibcon#cleared, iclass 21 cls_cnt 0 2006.169.08:13:46.53$vc4f8/va=6,6 2006.169.08:13:46.53#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.169.08:13:46.53#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.169.08:13:46.53#ibcon#ireg 11 cls_cnt 2 2006.169.08:13:46.53#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.169.08:13:46.59#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.169.08:13:46.59#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.169.08:13:46.59#ibcon#enter wrdev, iclass 23, count 2 2006.169.08:13:46.59#ibcon#first serial, iclass 23, count 2 2006.169.08:13:46.59#ibcon#enter sib2, iclass 23, count 2 2006.169.08:13:46.59#ibcon#flushed, iclass 23, count 2 2006.169.08:13:46.59#ibcon#about to write, iclass 23, count 2 2006.169.08:13:46.59#ibcon#wrote, iclass 23, count 2 2006.169.08:13:46.59#ibcon#about to read 3, iclass 23, count 2 2006.169.08:13:46.61#ibcon#read 3, iclass 23, count 2 2006.169.08:13:46.61#ibcon#about to read 4, iclass 23, count 2 2006.169.08:13:46.61#ibcon#read 4, iclass 23, count 2 2006.169.08:13:46.61#ibcon#about to read 5, iclass 23, count 2 2006.169.08:13:46.61#ibcon#read 5, iclass 23, count 2 2006.169.08:13:46.61#ibcon#about to read 6, iclass 23, count 2 2006.169.08:13:46.61#ibcon#read 6, iclass 23, count 2 2006.169.08:13:46.61#ibcon#end of sib2, iclass 23, count 2 2006.169.08:13:46.61#ibcon#*mode == 0, iclass 23, count 2 2006.169.08:13:46.61#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.169.08:13:46.61#ibcon#[25=AT06-06\r\n] 2006.169.08:13:46.61#ibcon#*before write, iclass 23, count 2 2006.169.08:13:46.61#ibcon#enter sib2, iclass 23, count 2 2006.169.08:13:46.61#ibcon#flushed, iclass 23, count 2 2006.169.08:13:46.61#ibcon#about to write, iclass 23, count 2 2006.169.08:13:46.61#ibcon#wrote, iclass 23, count 2 2006.169.08:13:46.61#ibcon#about to read 3, iclass 23, count 2 2006.169.08:13:46.64#ibcon#read 3, iclass 23, count 2 2006.169.08:13:46.64#ibcon#about to read 4, iclass 23, count 2 2006.169.08:13:46.64#ibcon#read 4, iclass 23, count 2 2006.169.08:13:46.64#ibcon#about to read 5, iclass 23, count 2 2006.169.08:13:46.64#ibcon#read 5, iclass 23, count 2 2006.169.08:13:46.64#ibcon#about to read 6, iclass 23, count 2 2006.169.08:13:46.64#ibcon#read 6, iclass 23, count 2 2006.169.08:13:46.64#ibcon#end of sib2, iclass 23, count 2 2006.169.08:13:46.64#ibcon#*after write, iclass 23, count 2 2006.169.08:13:46.64#ibcon#*before return 0, iclass 23, count 2 2006.169.08:13:46.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.169.08:13:46.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.169.08:13:46.64#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.169.08:13:46.64#ibcon#ireg 7 cls_cnt 0 2006.169.08:13:46.64#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.169.08:13:46.76#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.169.08:13:46.76#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.169.08:13:46.76#ibcon#enter wrdev, iclass 23, count 0 2006.169.08:13:46.76#ibcon#first serial, iclass 23, count 0 2006.169.08:13:46.76#ibcon#enter sib2, iclass 23, count 0 2006.169.08:13:46.76#ibcon#flushed, iclass 23, count 0 2006.169.08:13:46.76#ibcon#about to write, iclass 23, count 0 2006.169.08:13:46.76#ibcon#wrote, iclass 23, count 0 2006.169.08:13:46.76#ibcon#about to read 3, iclass 23, count 0 2006.169.08:13:46.78#ibcon#read 3, iclass 23, count 0 2006.169.08:13:46.78#ibcon#about to read 4, iclass 23, count 0 2006.169.08:13:46.78#ibcon#read 4, iclass 23, count 0 2006.169.08:13:46.78#ibcon#about to read 5, iclass 23, count 0 2006.169.08:13:46.78#ibcon#read 5, iclass 23, count 0 2006.169.08:13:46.78#ibcon#about to read 6, iclass 23, count 0 2006.169.08:13:46.78#ibcon#read 6, iclass 23, count 0 2006.169.08:13:46.78#ibcon#end of sib2, iclass 23, count 0 2006.169.08:13:46.78#ibcon#*mode == 0, iclass 23, count 0 2006.169.08:13:46.78#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.169.08:13:46.78#ibcon#[25=USB\r\n] 2006.169.08:13:46.78#ibcon#*before write, iclass 23, count 0 2006.169.08:13:46.78#ibcon#enter sib2, iclass 23, count 0 2006.169.08:13:46.78#ibcon#flushed, iclass 23, count 0 2006.169.08:13:46.78#ibcon#about to write, iclass 23, count 0 2006.169.08:13:46.78#ibcon#wrote, iclass 23, count 0 2006.169.08:13:46.78#ibcon#about to read 3, iclass 23, count 0 2006.169.08:13:46.81#ibcon#read 3, iclass 23, count 0 2006.169.08:13:46.81#ibcon#about to read 4, iclass 23, count 0 2006.169.08:13:46.81#ibcon#read 4, iclass 23, count 0 2006.169.08:13:46.81#ibcon#about to read 5, iclass 23, count 0 2006.169.08:13:46.81#ibcon#read 5, iclass 23, count 0 2006.169.08:13:46.81#ibcon#about to read 6, iclass 23, count 0 2006.169.08:13:46.81#ibcon#read 6, iclass 23, count 0 2006.169.08:13:46.81#ibcon#end of sib2, iclass 23, count 0 2006.169.08:13:46.81#ibcon#*after write, iclass 23, count 0 2006.169.08:13:46.81#ibcon#*before return 0, iclass 23, count 0 2006.169.08:13:46.81#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.169.08:13:46.81#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.169.08:13:46.81#ibcon#about to clear, iclass 23 cls_cnt 0 2006.169.08:13:46.81#ibcon#cleared, iclass 23 cls_cnt 0 2006.169.08:13:46.81$vc4f8/valo=7,832.99 2006.169.08:13:46.81#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.169.08:13:46.81#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.169.08:13:46.81#ibcon#ireg 17 cls_cnt 0 2006.169.08:13:46.81#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.169.08:13:46.81#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.169.08:13:46.81#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.169.08:13:46.81#ibcon#enter wrdev, iclass 25, count 0 2006.169.08:13:46.81#ibcon#first serial, iclass 25, count 0 2006.169.08:13:46.81#ibcon#enter sib2, iclass 25, count 0 2006.169.08:13:46.81#ibcon#flushed, iclass 25, count 0 2006.169.08:13:46.81#ibcon#about to write, iclass 25, count 0 2006.169.08:13:46.81#ibcon#wrote, iclass 25, count 0 2006.169.08:13:46.81#ibcon#about to read 3, iclass 25, count 0 2006.169.08:13:46.83#ibcon#read 3, iclass 25, count 0 2006.169.08:13:46.83#ibcon#about to read 4, iclass 25, count 0 2006.169.08:13:46.83#ibcon#read 4, iclass 25, count 0 2006.169.08:13:46.83#ibcon#about to read 5, iclass 25, count 0 2006.169.08:13:46.83#ibcon#read 5, iclass 25, count 0 2006.169.08:13:46.83#ibcon#about to read 6, iclass 25, count 0 2006.169.08:13:46.83#ibcon#read 6, iclass 25, count 0 2006.169.08:13:46.83#ibcon#end of sib2, iclass 25, count 0 2006.169.08:13:46.83#ibcon#*mode == 0, iclass 25, count 0 2006.169.08:13:46.83#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.169.08:13:46.83#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.08:13:46.83#ibcon#*before write, iclass 25, count 0 2006.169.08:13:46.83#ibcon#enter sib2, iclass 25, count 0 2006.169.08:13:46.83#ibcon#flushed, iclass 25, count 0 2006.169.08:13:46.83#ibcon#about to write, iclass 25, count 0 2006.169.08:13:46.83#ibcon#wrote, iclass 25, count 0 2006.169.08:13:46.83#ibcon#about to read 3, iclass 25, count 0 2006.169.08:13:46.87#ibcon#read 3, iclass 25, count 0 2006.169.08:13:46.87#ibcon#about to read 4, iclass 25, count 0 2006.169.08:13:46.87#ibcon#read 4, iclass 25, count 0 2006.169.08:13:46.87#ibcon#about to read 5, iclass 25, count 0 2006.169.08:13:46.87#ibcon#read 5, iclass 25, count 0 2006.169.08:13:46.87#ibcon#about to read 6, iclass 25, count 0 2006.169.08:13:46.87#ibcon#read 6, iclass 25, count 0 2006.169.08:13:46.87#ibcon#end of sib2, iclass 25, count 0 2006.169.08:13:46.87#ibcon#*after write, iclass 25, count 0 2006.169.08:13:46.87#ibcon#*before return 0, iclass 25, count 0 2006.169.08:13:46.87#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.169.08:13:46.87#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.169.08:13:46.87#ibcon#about to clear, iclass 25 cls_cnt 0 2006.169.08:13:46.87#ibcon#cleared, iclass 25 cls_cnt 0 2006.169.08:13:46.87$vc4f8/va=7,6 2006.169.08:13:46.87#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.169.08:13:46.87#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.169.08:13:46.87#ibcon#ireg 11 cls_cnt 2 2006.169.08:13:46.87#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.169.08:13:46.93#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.169.08:13:46.93#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.169.08:13:46.93#ibcon#enter wrdev, iclass 27, count 2 2006.169.08:13:46.93#ibcon#first serial, iclass 27, count 2 2006.169.08:13:46.93#ibcon#enter sib2, iclass 27, count 2 2006.169.08:13:46.93#ibcon#flushed, iclass 27, count 2 2006.169.08:13:46.93#ibcon#about to write, iclass 27, count 2 2006.169.08:13:46.93#ibcon#wrote, iclass 27, count 2 2006.169.08:13:46.93#ibcon#about to read 3, iclass 27, count 2 2006.169.08:13:46.95#ibcon#read 3, iclass 27, count 2 2006.169.08:13:46.95#ibcon#about to read 4, iclass 27, count 2 2006.169.08:13:46.95#ibcon#read 4, iclass 27, count 2 2006.169.08:13:46.95#ibcon#about to read 5, iclass 27, count 2 2006.169.08:13:46.95#ibcon#read 5, iclass 27, count 2 2006.169.08:13:46.95#ibcon#about to read 6, iclass 27, count 2 2006.169.08:13:46.95#ibcon#read 6, iclass 27, count 2 2006.169.08:13:46.95#ibcon#end of sib2, iclass 27, count 2 2006.169.08:13:46.95#ibcon#*mode == 0, iclass 27, count 2 2006.169.08:13:46.95#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.169.08:13:46.95#ibcon#[25=AT07-06\r\n] 2006.169.08:13:46.95#ibcon#*before write, iclass 27, count 2 2006.169.08:13:46.95#ibcon#enter sib2, iclass 27, count 2 2006.169.08:13:46.95#ibcon#flushed, iclass 27, count 2 2006.169.08:13:46.95#ibcon#about to write, iclass 27, count 2 2006.169.08:13:46.95#ibcon#wrote, iclass 27, count 2 2006.169.08:13:46.95#ibcon#about to read 3, iclass 27, count 2 2006.169.08:13:46.98#ibcon#read 3, iclass 27, count 2 2006.169.08:13:46.98#ibcon#about to read 4, iclass 27, count 2 2006.169.08:13:46.98#ibcon#read 4, iclass 27, count 2 2006.169.08:13:46.98#ibcon#about to read 5, iclass 27, count 2 2006.169.08:13:46.98#ibcon#read 5, iclass 27, count 2 2006.169.08:13:46.98#ibcon#about to read 6, iclass 27, count 2 2006.169.08:13:46.98#ibcon#read 6, iclass 27, count 2 2006.169.08:13:46.98#ibcon#end of sib2, iclass 27, count 2 2006.169.08:13:46.98#ibcon#*after write, iclass 27, count 2 2006.169.08:13:46.98#ibcon#*before return 0, iclass 27, count 2 2006.169.08:13:46.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.169.08:13:46.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.169.08:13:46.98#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.169.08:13:46.98#ibcon#ireg 7 cls_cnt 0 2006.169.08:13:46.98#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.169.08:13:47.10#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.169.08:13:47.10#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.169.08:13:47.10#ibcon#enter wrdev, iclass 27, count 0 2006.169.08:13:47.10#ibcon#first serial, iclass 27, count 0 2006.169.08:13:47.10#ibcon#enter sib2, iclass 27, count 0 2006.169.08:13:47.10#ibcon#flushed, iclass 27, count 0 2006.169.08:13:47.10#ibcon#about to write, iclass 27, count 0 2006.169.08:13:47.10#ibcon#wrote, iclass 27, count 0 2006.169.08:13:47.10#ibcon#about to read 3, iclass 27, count 0 2006.169.08:13:47.12#ibcon#read 3, iclass 27, count 0 2006.169.08:13:47.12#ibcon#about to read 4, iclass 27, count 0 2006.169.08:13:47.12#ibcon#read 4, iclass 27, count 0 2006.169.08:13:47.12#ibcon#about to read 5, iclass 27, count 0 2006.169.08:13:47.12#ibcon#read 5, iclass 27, count 0 2006.169.08:13:47.12#ibcon#about to read 6, iclass 27, count 0 2006.169.08:13:47.12#ibcon#read 6, iclass 27, count 0 2006.169.08:13:47.12#ibcon#end of sib2, iclass 27, count 0 2006.169.08:13:47.12#ibcon#*mode == 0, iclass 27, count 0 2006.169.08:13:47.12#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.169.08:13:47.12#ibcon#[25=USB\r\n] 2006.169.08:13:47.12#ibcon#*before write, iclass 27, count 0 2006.169.08:13:47.12#ibcon#enter sib2, iclass 27, count 0 2006.169.08:13:47.12#ibcon#flushed, iclass 27, count 0 2006.169.08:13:47.12#ibcon#about to write, iclass 27, count 0 2006.169.08:13:47.12#ibcon#wrote, iclass 27, count 0 2006.169.08:13:47.12#ibcon#about to read 3, iclass 27, count 0 2006.169.08:13:47.15#ibcon#read 3, iclass 27, count 0 2006.169.08:13:47.15#ibcon#about to read 4, iclass 27, count 0 2006.169.08:13:47.15#ibcon#read 4, iclass 27, count 0 2006.169.08:13:47.15#ibcon#about to read 5, iclass 27, count 0 2006.169.08:13:47.15#ibcon#read 5, iclass 27, count 0 2006.169.08:13:47.15#ibcon#about to read 6, iclass 27, count 0 2006.169.08:13:47.15#ibcon#read 6, iclass 27, count 0 2006.169.08:13:47.15#ibcon#end of sib2, iclass 27, count 0 2006.169.08:13:47.15#ibcon#*after write, iclass 27, count 0 2006.169.08:13:47.15#ibcon#*before return 0, iclass 27, count 0 2006.169.08:13:47.15#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.169.08:13:47.15#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.169.08:13:47.15#ibcon#about to clear, iclass 27 cls_cnt 0 2006.169.08:13:47.15#ibcon#cleared, iclass 27 cls_cnt 0 2006.169.08:13:47.15$vc4f8/valo=8,852.99 2006.169.08:13:47.15#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.169.08:13:47.15#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.169.08:13:47.15#ibcon#ireg 17 cls_cnt 0 2006.169.08:13:47.15#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.169.08:13:47.15#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.169.08:13:47.15#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.169.08:13:47.15#ibcon#enter wrdev, iclass 29, count 0 2006.169.08:13:47.15#ibcon#first serial, iclass 29, count 0 2006.169.08:13:47.15#ibcon#enter sib2, iclass 29, count 0 2006.169.08:13:47.15#ibcon#flushed, iclass 29, count 0 2006.169.08:13:47.15#ibcon#about to write, iclass 29, count 0 2006.169.08:13:47.15#ibcon#wrote, iclass 29, count 0 2006.169.08:13:47.15#ibcon#about to read 3, iclass 29, count 0 2006.169.08:13:47.17#ibcon#read 3, iclass 29, count 0 2006.169.08:13:47.17#ibcon#about to read 4, iclass 29, count 0 2006.169.08:13:47.17#ibcon#read 4, iclass 29, count 0 2006.169.08:13:47.17#ibcon#about to read 5, iclass 29, count 0 2006.169.08:13:47.17#ibcon#read 5, iclass 29, count 0 2006.169.08:13:47.17#ibcon#about to read 6, iclass 29, count 0 2006.169.08:13:47.17#ibcon#read 6, iclass 29, count 0 2006.169.08:13:47.17#ibcon#end of sib2, iclass 29, count 0 2006.169.08:13:47.17#ibcon#*mode == 0, iclass 29, count 0 2006.169.08:13:47.17#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.169.08:13:47.17#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.08:13:47.17#ibcon#*before write, iclass 29, count 0 2006.169.08:13:47.17#ibcon#enter sib2, iclass 29, count 0 2006.169.08:13:47.17#ibcon#flushed, iclass 29, count 0 2006.169.08:13:47.17#ibcon#about to write, iclass 29, count 0 2006.169.08:13:47.17#ibcon#wrote, iclass 29, count 0 2006.169.08:13:47.17#ibcon#about to read 3, iclass 29, count 0 2006.169.08:13:47.21#ibcon#read 3, iclass 29, count 0 2006.169.08:13:47.21#ibcon#about to read 4, iclass 29, count 0 2006.169.08:13:47.21#ibcon#read 4, iclass 29, count 0 2006.169.08:13:47.21#ibcon#about to read 5, iclass 29, count 0 2006.169.08:13:47.21#ibcon#read 5, iclass 29, count 0 2006.169.08:13:47.21#ibcon#about to read 6, iclass 29, count 0 2006.169.08:13:47.21#ibcon#read 6, iclass 29, count 0 2006.169.08:13:47.21#ibcon#end of sib2, iclass 29, count 0 2006.169.08:13:47.21#ibcon#*after write, iclass 29, count 0 2006.169.08:13:47.21#ibcon#*before return 0, iclass 29, count 0 2006.169.08:13:47.21#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.169.08:13:47.21#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.169.08:13:47.21#ibcon#about to clear, iclass 29 cls_cnt 0 2006.169.08:13:47.21#ibcon#cleared, iclass 29 cls_cnt 0 2006.169.08:13:47.21$vc4f8/va=8,7 2006.169.08:13:47.21#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.169.08:13:47.21#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.169.08:13:47.21#ibcon#ireg 11 cls_cnt 2 2006.169.08:13:47.21#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.169.08:13:47.27#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.169.08:13:47.27#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.169.08:13:47.27#ibcon#enter wrdev, iclass 31, count 2 2006.169.08:13:47.27#ibcon#first serial, iclass 31, count 2 2006.169.08:13:47.27#ibcon#enter sib2, iclass 31, count 2 2006.169.08:13:47.27#ibcon#flushed, iclass 31, count 2 2006.169.08:13:47.27#ibcon#about to write, iclass 31, count 2 2006.169.08:13:47.27#ibcon#wrote, iclass 31, count 2 2006.169.08:13:47.27#ibcon#about to read 3, iclass 31, count 2 2006.169.08:13:47.29#ibcon#read 3, iclass 31, count 2 2006.169.08:13:47.29#ibcon#about to read 4, iclass 31, count 2 2006.169.08:13:47.29#ibcon#read 4, iclass 31, count 2 2006.169.08:13:47.29#ibcon#about to read 5, iclass 31, count 2 2006.169.08:13:47.29#ibcon#read 5, iclass 31, count 2 2006.169.08:13:47.29#ibcon#about to read 6, iclass 31, count 2 2006.169.08:13:47.29#ibcon#read 6, iclass 31, count 2 2006.169.08:13:47.29#ibcon#end of sib2, iclass 31, count 2 2006.169.08:13:47.29#ibcon#*mode == 0, iclass 31, count 2 2006.169.08:13:47.29#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.169.08:13:47.29#ibcon#[25=AT08-07\r\n] 2006.169.08:13:47.29#ibcon#*before write, iclass 31, count 2 2006.169.08:13:47.29#ibcon#enter sib2, iclass 31, count 2 2006.169.08:13:47.29#ibcon#flushed, iclass 31, count 2 2006.169.08:13:47.29#ibcon#about to write, iclass 31, count 2 2006.169.08:13:47.29#ibcon#wrote, iclass 31, count 2 2006.169.08:13:47.29#ibcon#about to read 3, iclass 31, count 2 2006.169.08:13:47.32#ibcon#read 3, iclass 31, count 2 2006.169.08:13:47.32#ibcon#about to read 4, iclass 31, count 2 2006.169.08:13:47.32#ibcon#read 4, iclass 31, count 2 2006.169.08:13:47.32#ibcon#about to read 5, iclass 31, count 2 2006.169.08:13:47.32#ibcon#read 5, iclass 31, count 2 2006.169.08:13:47.32#ibcon#about to read 6, iclass 31, count 2 2006.169.08:13:47.32#ibcon#read 6, iclass 31, count 2 2006.169.08:13:47.32#ibcon#end of sib2, iclass 31, count 2 2006.169.08:13:47.32#ibcon#*after write, iclass 31, count 2 2006.169.08:13:47.32#ibcon#*before return 0, iclass 31, count 2 2006.169.08:13:47.32#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.169.08:13:47.32#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.169.08:13:47.32#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.169.08:13:47.32#ibcon#ireg 7 cls_cnt 0 2006.169.08:13:47.32#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.169.08:13:47.44#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.169.08:13:47.44#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.169.08:13:47.44#ibcon#enter wrdev, iclass 31, count 0 2006.169.08:13:47.44#ibcon#first serial, iclass 31, count 0 2006.169.08:13:47.44#ibcon#enter sib2, iclass 31, count 0 2006.169.08:13:47.44#ibcon#flushed, iclass 31, count 0 2006.169.08:13:47.44#ibcon#about to write, iclass 31, count 0 2006.169.08:13:47.44#ibcon#wrote, iclass 31, count 0 2006.169.08:13:47.44#ibcon#about to read 3, iclass 31, count 0 2006.169.08:13:47.46#ibcon#read 3, iclass 31, count 0 2006.169.08:13:47.46#ibcon#about to read 4, iclass 31, count 0 2006.169.08:13:47.46#ibcon#read 4, iclass 31, count 0 2006.169.08:13:47.46#ibcon#about to read 5, iclass 31, count 0 2006.169.08:13:47.46#ibcon#read 5, iclass 31, count 0 2006.169.08:13:47.46#ibcon#about to read 6, iclass 31, count 0 2006.169.08:13:47.46#ibcon#read 6, iclass 31, count 0 2006.169.08:13:47.46#ibcon#end of sib2, iclass 31, count 0 2006.169.08:13:47.46#ibcon#*mode == 0, iclass 31, count 0 2006.169.08:13:47.46#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.169.08:13:47.46#ibcon#[25=USB\r\n] 2006.169.08:13:47.46#ibcon#*before write, iclass 31, count 0 2006.169.08:13:47.46#ibcon#enter sib2, iclass 31, count 0 2006.169.08:13:47.46#ibcon#flushed, iclass 31, count 0 2006.169.08:13:47.46#ibcon#about to write, iclass 31, count 0 2006.169.08:13:47.46#ibcon#wrote, iclass 31, count 0 2006.169.08:13:47.46#ibcon#about to read 3, iclass 31, count 0 2006.169.08:13:47.49#ibcon#read 3, iclass 31, count 0 2006.169.08:13:47.49#ibcon#about to read 4, iclass 31, count 0 2006.169.08:13:47.49#ibcon#read 4, iclass 31, count 0 2006.169.08:13:47.49#ibcon#about to read 5, iclass 31, count 0 2006.169.08:13:47.49#ibcon#read 5, iclass 31, count 0 2006.169.08:13:47.49#ibcon#about to read 6, iclass 31, count 0 2006.169.08:13:47.49#ibcon#read 6, iclass 31, count 0 2006.169.08:13:47.49#ibcon#end of sib2, iclass 31, count 0 2006.169.08:13:47.49#ibcon#*after write, iclass 31, count 0 2006.169.08:13:47.49#ibcon#*before return 0, iclass 31, count 0 2006.169.08:13:47.49#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.169.08:13:47.49#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.169.08:13:47.49#ibcon#about to clear, iclass 31 cls_cnt 0 2006.169.08:13:47.49#ibcon#cleared, iclass 31 cls_cnt 0 2006.169.08:13:47.49$vc4f8/vblo=1,632.99 2006.169.08:13:47.49#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.169.08:13:47.49#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.169.08:13:47.49#ibcon#ireg 17 cls_cnt 0 2006.169.08:13:47.49#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:13:47.49#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:13:47.49#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:13:47.49#ibcon#enter wrdev, iclass 33, count 0 2006.169.08:13:47.49#ibcon#first serial, iclass 33, count 0 2006.169.08:13:47.49#ibcon#enter sib2, iclass 33, count 0 2006.169.08:13:47.49#ibcon#flushed, iclass 33, count 0 2006.169.08:13:47.49#ibcon#about to write, iclass 33, count 0 2006.169.08:13:47.49#ibcon#wrote, iclass 33, count 0 2006.169.08:13:47.49#ibcon#about to read 3, iclass 33, count 0 2006.169.08:13:47.51#ibcon#read 3, iclass 33, count 0 2006.169.08:13:47.51#ibcon#about to read 4, iclass 33, count 0 2006.169.08:13:47.51#ibcon#read 4, iclass 33, count 0 2006.169.08:13:47.51#ibcon#about to read 5, iclass 33, count 0 2006.169.08:13:47.51#ibcon#read 5, iclass 33, count 0 2006.169.08:13:47.51#ibcon#about to read 6, iclass 33, count 0 2006.169.08:13:47.51#ibcon#read 6, iclass 33, count 0 2006.169.08:13:47.51#ibcon#end of sib2, iclass 33, count 0 2006.169.08:13:47.51#ibcon#*mode == 0, iclass 33, count 0 2006.169.08:13:47.51#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.169.08:13:47.51#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.08:13:47.51#ibcon#*before write, iclass 33, count 0 2006.169.08:13:47.51#ibcon#enter sib2, iclass 33, count 0 2006.169.08:13:47.51#ibcon#flushed, iclass 33, count 0 2006.169.08:13:47.51#ibcon#about to write, iclass 33, count 0 2006.169.08:13:47.51#ibcon#wrote, iclass 33, count 0 2006.169.08:13:47.51#ibcon#about to read 3, iclass 33, count 0 2006.169.08:13:47.55#ibcon#read 3, iclass 33, count 0 2006.169.08:13:47.55#ibcon#about to read 4, iclass 33, count 0 2006.169.08:13:47.55#ibcon#read 4, iclass 33, count 0 2006.169.08:13:47.55#ibcon#about to read 5, iclass 33, count 0 2006.169.08:13:47.55#ibcon#read 5, iclass 33, count 0 2006.169.08:13:47.55#ibcon#about to read 6, iclass 33, count 0 2006.169.08:13:47.55#ibcon#read 6, iclass 33, count 0 2006.169.08:13:47.55#ibcon#end of sib2, iclass 33, count 0 2006.169.08:13:47.55#ibcon#*after write, iclass 33, count 0 2006.169.08:13:47.55#ibcon#*before return 0, iclass 33, count 0 2006.169.08:13:47.55#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:13:47.55#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:13:47.55#ibcon#about to clear, iclass 33 cls_cnt 0 2006.169.08:13:47.55#ibcon#cleared, iclass 33 cls_cnt 0 2006.169.08:13:47.55$vc4f8/vb=1,4 2006.169.08:13:47.55#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.169.08:13:47.55#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.169.08:13:47.55#ibcon#ireg 11 cls_cnt 2 2006.169.08:13:47.55#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.169.08:13:47.55#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.169.08:13:47.55#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.169.08:13:47.55#ibcon#enter wrdev, iclass 35, count 2 2006.169.08:13:47.55#ibcon#first serial, iclass 35, count 2 2006.169.08:13:47.55#ibcon#enter sib2, iclass 35, count 2 2006.169.08:13:47.55#ibcon#flushed, iclass 35, count 2 2006.169.08:13:47.55#ibcon#about to write, iclass 35, count 2 2006.169.08:13:47.55#ibcon#wrote, iclass 35, count 2 2006.169.08:13:47.55#ibcon#about to read 3, iclass 35, count 2 2006.169.08:13:47.57#ibcon#read 3, iclass 35, count 2 2006.169.08:13:47.57#ibcon#about to read 4, iclass 35, count 2 2006.169.08:13:47.57#ibcon#read 4, iclass 35, count 2 2006.169.08:13:47.57#ibcon#about to read 5, iclass 35, count 2 2006.169.08:13:47.57#ibcon#read 5, iclass 35, count 2 2006.169.08:13:47.57#ibcon#about to read 6, iclass 35, count 2 2006.169.08:13:47.57#ibcon#read 6, iclass 35, count 2 2006.169.08:13:47.57#ibcon#end of sib2, iclass 35, count 2 2006.169.08:13:47.57#ibcon#*mode == 0, iclass 35, count 2 2006.169.08:13:47.57#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.169.08:13:47.57#ibcon#[27=AT01-04\r\n] 2006.169.08:13:47.57#ibcon#*before write, iclass 35, count 2 2006.169.08:13:47.57#ibcon#enter sib2, iclass 35, count 2 2006.169.08:13:47.57#ibcon#flushed, iclass 35, count 2 2006.169.08:13:47.57#ibcon#about to write, iclass 35, count 2 2006.169.08:13:47.57#ibcon#wrote, iclass 35, count 2 2006.169.08:13:47.57#ibcon#about to read 3, iclass 35, count 2 2006.169.08:13:47.60#ibcon#read 3, iclass 35, count 2 2006.169.08:13:47.60#ibcon#about to read 4, iclass 35, count 2 2006.169.08:13:47.60#ibcon#read 4, iclass 35, count 2 2006.169.08:13:47.60#ibcon#about to read 5, iclass 35, count 2 2006.169.08:13:47.60#ibcon#read 5, iclass 35, count 2 2006.169.08:13:47.60#ibcon#about to read 6, iclass 35, count 2 2006.169.08:13:47.60#ibcon#read 6, iclass 35, count 2 2006.169.08:13:47.60#ibcon#end of sib2, iclass 35, count 2 2006.169.08:13:47.60#ibcon#*after write, iclass 35, count 2 2006.169.08:13:47.60#ibcon#*before return 0, iclass 35, count 2 2006.169.08:13:47.60#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.169.08:13:47.60#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.169.08:13:47.60#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.169.08:13:47.60#ibcon#ireg 7 cls_cnt 0 2006.169.08:13:47.60#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.169.08:13:47.72#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.169.08:13:47.72#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.169.08:13:47.72#ibcon#enter wrdev, iclass 35, count 0 2006.169.08:13:47.72#ibcon#first serial, iclass 35, count 0 2006.169.08:13:47.72#ibcon#enter sib2, iclass 35, count 0 2006.169.08:13:47.72#ibcon#flushed, iclass 35, count 0 2006.169.08:13:47.72#ibcon#about to write, iclass 35, count 0 2006.169.08:13:47.72#ibcon#wrote, iclass 35, count 0 2006.169.08:13:47.72#ibcon#about to read 3, iclass 35, count 0 2006.169.08:13:47.74#ibcon#read 3, iclass 35, count 0 2006.169.08:13:47.74#ibcon#about to read 4, iclass 35, count 0 2006.169.08:13:47.74#ibcon#read 4, iclass 35, count 0 2006.169.08:13:47.74#ibcon#about to read 5, iclass 35, count 0 2006.169.08:13:47.74#ibcon#read 5, iclass 35, count 0 2006.169.08:13:47.74#ibcon#about to read 6, iclass 35, count 0 2006.169.08:13:47.74#ibcon#read 6, iclass 35, count 0 2006.169.08:13:47.74#ibcon#end of sib2, iclass 35, count 0 2006.169.08:13:47.74#ibcon#*mode == 0, iclass 35, count 0 2006.169.08:13:47.74#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.169.08:13:47.74#ibcon#[27=USB\r\n] 2006.169.08:13:47.74#ibcon#*before write, iclass 35, count 0 2006.169.08:13:47.74#ibcon#enter sib2, iclass 35, count 0 2006.169.08:13:47.74#ibcon#flushed, iclass 35, count 0 2006.169.08:13:47.74#ibcon#about to write, iclass 35, count 0 2006.169.08:13:47.74#ibcon#wrote, iclass 35, count 0 2006.169.08:13:47.74#ibcon#about to read 3, iclass 35, count 0 2006.169.08:13:47.77#ibcon#read 3, iclass 35, count 0 2006.169.08:13:47.77#ibcon#about to read 4, iclass 35, count 0 2006.169.08:13:47.77#ibcon#read 4, iclass 35, count 0 2006.169.08:13:47.77#ibcon#about to read 5, iclass 35, count 0 2006.169.08:13:47.77#ibcon#read 5, iclass 35, count 0 2006.169.08:13:47.77#ibcon#about to read 6, iclass 35, count 0 2006.169.08:13:47.77#ibcon#read 6, iclass 35, count 0 2006.169.08:13:47.77#ibcon#end of sib2, iclass 35, count 0 2006.169.08:13:47.77#ibcon#*after write, iclass 35, count 0 2006.169.08:13:47.77#ibcon#*before return 0, iclass 35, count 0 2006.169.08:13:47.77#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.169.08:13:47.77#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.169.08:13:47.77#ibcon#about to clear, iclass 35 cls_cnt 0 2006.169.08:13:47.77#ibcon#cleared, iclass 35 cls_cnt 0 2006.169.08:13:47.77$vc4f8/vblo=2,640.99 2006.169.08:13:47.77#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.169.08:13:47.77#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.169.08:13:47.77#ibcon#ireg 17 cls_cnt 0 2006.169.08:13:47.77#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:13:47.77#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:13:47.77#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:13:47.77#ibcon#enter wrdev, iclass 37, count 0 2006.169.08:13:47.77#ibcon#first serial, iclass 37, count 0 2006.169.08:13:47.77#ibcon#enter sib2, iclass 37, count 0 2006.169.08:13:47.77#ibcon#flushed, iclass 37, count 0 2006.169.08:13:47.77#ibcon#about to write, iclass 37, count 0 2006.169.08:13:47.77#ibcon#wrote, iclass 37, count 0 2006.169.08:13:47.77#ibcon#about to read 3, iclass 37, count 0 2006.169.08:13:47.79#ibcon#read 3, iclass 37, count 0 2006.169.08:13:47.79#ibcon#about to read 4, iclass 37, count 0 2006.169.08:13:47.79#ibcon#read 4, iclass 37, count 0 2006.169.08:13:47.79#ibcon#about to read 5, iclass 37, count 0 2006.169.08:13:47.79#ibcon#read 5, iclass 37, count 0 2006.169.08:13:47.79#ibcon#about to read 6, iclass 37, count 0 2006.169.08:13:47.79#ibcon#read 6, iclass 37, count 0 2006.169.08:13:47.79#ibcon#end of sib2, iclass 37, count 0 2006.169.08:13:47.79#ibcon#*mode == 0, iclass 37, count 0 2006.169.08:13:47.79#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.169.08:13:47.79#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.08:13:47.79#ibcon#*before write, iclass 37, count 0 2006.169.08:13:47.79#ibcon#enter sib2, iclass 37, count 0 2006.169.08:13:47.79#ibcon#flushed, iclass 37, count 0 2006.169.08:13:47.79#ibcon#about to write, iclass 37, count 0 2006.169.08:13:47.79#ibcon#wrote, iclass 37, count 0 2006.169.08:13:47.79#ibcon#about to read 3, iclass 37, count 0 2006.169.08:13:47.83#ibcon#read 3, iclass 37, count 0 2006.169.08:13:47.83#ibcon#about to read 4, iclass 37, count 0 2006.169.08:13:47.83#ibcon#read 4, iclass 37, count 0 2006.169.08:13:47.83#ibcon#about to read 5, iclass 37, count 0 2006.169.08:13:47.83#ibcon#read 5, iclass 37, count 0 2006.169.08:13:47.83#ibcon#about to read 6, iclass 37, count 0 2006.169.08:13:47.83#ibcon#read 6, iclass 37, count 0 2006.169.08:13:47.83#ibcon#end of sib2, iclass 37, count 0 2006.169.08:13:47.83#ibcon#*after write, iclass 37, count 0 2006.169.08:13:47.83#ibcon#*before return 0, iclass 37, count 0 2006.169.08:13:47.83#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:13:47.83#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:13:47.83#ibcon#about to clear, iclass 37 cls_cnt 0 2006.169.08:13:47.83#ibcon#cleared, iclass 37 cls_cnt 0 2006.169.08:13:47.83$vc4f8/vb=2,4 2006.169.08:13:47.83#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.169.08:13:47.83#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.169.08:13:47.83#ibcon#ireg 11 cls_cnt 2 2006.169.08:13:47.83#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.169.08:13:47.89#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.169.08:13:47.89#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.169.08:13:47.89#ibcon#enter wrdev, iclass 39, count 2 2006.169.08:13:47.89#ibcon#first serial, iclass 39, count 2 2006.169.08:13:47.89#ibcon#enter sib2, iclass 39, count 2 2006.169.08:13:47.89#ibcon#flushed, iclass 39, count 2 2006.169.08:13:47.89#ibcon#about to write, iclass 39, count 2 2006.169.08:13:47.89#ibcon#wrote, iclass 39, count 2 2006.169.08:13:47.89#ibcon#about to read 3, iclass 39, count 2 2006.169.08:13:47.91#ibcon#read 3, iclass 39, count 2 2006.169.08:13:47.91#ibcon#about to read 4, iclass 39, count 2 2006.169.08:13:47.91#ibcon#read 4, iclass 39, count 2 2006.169.08:13:47.91#ibcon#about to read 5, iclass 39, count 2 2006.169.08:13:47.91#ibcon#read 5, iclass 39, count 2 2006.169.08:13:47.91#ibcon#about to read 6, iclass 39, count 2 2006.169.08:13:47.91#ibcon#read 6, iclass 39, count 2 2006.169.08:13:47.91#ibcon#end of sib2, iclass 39, count 2 2006.169.08:13:47.91#ibcon#*mode == 0, iclass 39, count 2 2006.169.08:13:47.91#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.169.08:13:47.91#ibcon#[27=AT02-04\r\n] 2006.169.08:13:47.91#ibcon#*before write, iclass 39, count 2 2006.169.08:13:47.91#ibcon#enter sib2, iclass 39, count 2 2006.169.08:13:47.91#ibcon#flushed, iclass 39, count 2 2006.169.08:13:47.91#ibcon#about to write, iclass 39, count 2 2006.169.08:13:47.91#ibcon#wrote, iclass 39, count 2 2006.169.08:13:47.91#ibcon#about to read 3, iclass 39, count 2 2006.169.08:13:47.94#ibcon#read 3, iclass 39, count 2 2006.169.08:13:47.94#ibcon#about to read 4, iclass 39, count 2 2006.169.08:13:47.94#ibcon#read 4, iclass 39, count 2 2006.169.08:13:47.94#ibcon#about to read 5, iclass 39, count 2 2006.169.08:13:47.94#ibcon#read 5, iclass 39, count 2 2006.169.08:13:47.94#ibcon#about to read 6, iclass 39, count 2 2006.169.08:13:47.94#ibcon#read 6, iclass 39, count 2 2006.169.08:13:47.94#ibcon#end of sib2, iclass 39, count 2 2006.169.08:13:47.94#ibcon#*after write, iclass 39, count 2 2006.169.08:13:47.94#ibcon#*before return 0, iclass 39, count 2 2006.169.08:13:47.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.169.08:13:47.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.169.08:13:47.94#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.169.08:13:47.94#ibcon#ireg 7 cls_cnt 0 2006.169.08:13:47.94#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.169.08:13:48.06#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.169.08:13:48.06#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.169.08:13:48.06#ibcon#enter wrdev, iclass 39, count 0 2006.169.08:13:48.06#ibcon#first serial, iclass 39, count 0 2006.169.08:13:48.06#ibcon#enter sib2, iclass 39, count 0 2006.169.08:13:48.06#ibcon#flushed, iclass 39, count 0 2006.169.08:13:48.06#ibcon#about to write, iclass 39, count 0 2006.169.08:13:48.06#ibcon#wrote, iclass 39, count 0 2006.169.08:13:48.06#ibcon#about to read 3, iclass 39, count 0 2006.169.08:13:48.08#ibcon#read 3, iclass 39, count 0 2006.169.08:13:48.08#ibcon#about to read 4, iclass 39, count 0 2006.169.08:13:48.08#ibcon#read 4, iclass 39, count 0 2006.169.08:13:48.08#ibcon#about to read 5, iclass 39, count 0 2006.169.08:13:48.08#ibcon#read 5, iclass 39, count 0 2006.169.08:13:48.08#ibcon#about to read 6, iclass 39, count 0 2006.169.08:13:48.08#ibcon#read 6, iclass 39, count 0 2006.169.08:13:48.08#ibcon#end of sib2, iclass 39, count 0 2006.169.08:13:48.08#ibcon#*mode == 0, iclass 39, count 0 2006.169.08:13:48.08#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.169.08:13:48.08#ibcon#[27=USB\r\n] 2006.169.08:13:48.08#ibcon#*before write, iclass 39, count 0 2006.169.08:13:48.08#ibcon#enter sib2, iclass 39, count 0 2006.169.08:13:48.08#ibcon#flushed, iclass 39, count 0 2006.169.08:13:48.08#ibcon#about to write, iclass 39, count 0 2006.169.08:13:48.08#ibcon#wrote, iclass 39, count 0 2006.169.08:13:48.08#ibcon#about to read 3, iclass 39, count 0 2006.169.08:13:48.11#ibcon#read 3, iclass 39, count 0 2006.169.08:13:48.11#ibcon#about to read 4, iclass 39, count 0 2006.169.08:13:48.11#ibcon#read 4, iclass 39, count 0 2006.169.08:13:48.11#ibcon#about to read 5, iclass 39, count 0 2006.169.08:13:48.11#ibcon#read 5, iclass 39, count 0 2006.169.08:13:48.11#ibcon#about to read 6, iclass 39, count 0 2006.169.08:13:48.11#ibcon#read 6, iclass 39, count 0 2006.169.08:13:48.11#ibcon#end of sib2, iclass 39, count 0 2006.169.08:13:48.11#ibcon#*after write, iclass 39, count 0 2006.169.08:13:48.11#ibcon#*before return 0, iclass 39, count 0 2006.169.08:13:48.11#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.169.08:13:48.11#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.169.08:13:48.11#ibcon#about to clear, iclass 39 cls_cnt 0 2006.169.08:13:48.11#ibcon#cleared, iclass 39 cls_cnt 0 2006.169.08:13:48.11$vc4f8/vblo=3,656.99 2006.169.08:13:48.11#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.169.08:13:48.11#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.169.08:13:48.11#ibcon#ireg 17 cls_cnt 0 2006.169.08:13:48.11#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.169.08:13:48.11#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.169.08:13:48.11#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.169.08:13:48.11#ibcon#enter wrdev, iclass 3, count 0 2006.169.08:13:48.11#ibcon#first serial, iclass 3, count 0 2006.169.08:13:48.11#ibcon#enter sib2, iclass 3, count 0 2006.169.08:13:48.11#ibcon#flushed, iclass 3, count 0 2006.169.08:13:48.11#ibcon#about to write, iclass 3, count 0 2006.169.08:13:48.11#ibcon#wrote, iclass 3, count 0 2006.169.08:13:48.11#ibcon#about to read 3, iclass 3, count 0 2006.169.08:13:48.13#ibcon#read 3, iclass 3, count 0 2006.169.08:13:48.13#ibcon#about to read 4, iclass 3, count 0 2006.169.08:13:48.13#ibcon#read 4, iclass 3, count 0 2006.169.08:13:48.13#ibcon#about to read 5, iclass 3, count 0 2006.169.08:13:48.13#ibcon#read 5, iclass 3, count 0 2006.169.08:13:48.13#ibcon#about to read 6, iclass 3, count 0 2006.169.08:13:48.13#ibcon#read 6, iclass 3, count 0 2006.169.08:13:48.13#ibcon#end of sib2, iclass 3, count 0 2006.169.08:13:48.13#ibcon#*mode == 0, iclass 3, count 0 2006.169.08:13:48.13#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.169.08:13:48.13#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.08:13:48.13#ibcon#*before write, iclass 3, count 0 2006.169.08:13:48.13#ibcon#enter sib2, iclass 3, count 0 2006.169.08:13:48.13#ibcon#flushed, iclass 3, count 0 2006.169.08:13:48.13#ibcon#about to write, iclass 3, count 0 2006.169.08:13:48.13#ibcon#wrote, iclass 3, count 0 2006.169.08:13:48.13#ibcon#about to read 3, iclass 3, count 0 2006.169.08:13:48.17#ibcon#read 3, iclass 3, count 0 2006.169.08:13:48.17#ibcon#about to read 4, iclass 3, count 0 2006.169.08:13:48.17#ibcon#read 4, iclass 3, count 0 2006.169.08:13:48.17#ibcon#about to read 5, iclass 3, count 0 2006.169.08:13:48.17#ibcon#read 5, iclass 3, count 0 2006.169.08:13:48.17#ibcon#about to read 6, iclass 3, count 0 2006.169.08:13:48.17#ibcon#read 6, iclass 3, count 0 2006.169.08:13:48.17#ibcon#end of sib2, iclass 3, count 0 2006.169.08:13:48.17#ibcon#*after write, iclass 3, count 0 2006.169.08:13:48.17#ibcon#*before return 0, iclass 3, count 0 2006.169.08:13:48.17#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.169.08:13:48.17#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.169.08:13:48.17#ibcon#about to clear, iclass 3 cls_cnt 0 2006.169.08:13:48.17#ibcon#cleared, iclass 3 cls_cnt 0 2006.169.08:13:48.17$vc4f8/vb=3,4 2006.169.08:13:48.17#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.169.08:13:48.17#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.169.08:13:48.17#ibcon#ireg 11 cls_cnt 2 2006.169.08:13:48.17#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.169.08:13:48.23#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.169.08:13:48.23#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.169.08:13:48.23#ibcon#enter wrdev, iclass 5, count 2 2006.169.08:13:48.23#ibcon#first serial, iclass 5, count 2 2006.169.08:13:48.23#ibcon#enter sib2, iclass 5, count 2 2006.169.08:13:48.23#ibcon#flushed, iclass 5, count 2 2006.169.08:13:48.23#ibcon#about to write, iclass 5, count 2 2006.169.08:13:48.23#ibcon#wrote, iclass 5, count 2 2006.169.08:13:48.23#ibcon#about to read 3, iclass 5, count 2 2006.169.08:13:48.25#ibcon#read 3, iclass 5, count 2 2006.169.08:13:48.25#ibcon#about to read 4, iclass 5, count 2 2006.169.08:13:48.25#ibcon#read 4, iclass 5, count 2 2006.169.08:13:48.25#ibcon#about to read 5, iclass 5, count 2 2006.169.08:13:48.25#ibcon#read 5, iclass 5, count 2 2006.169.08:13:48.25#ibcon#about to read 6, iclass 5, count 2 2006.169.08:13:48.25#ibcon#read 6, iclass 5, count 2 2006.169.08:13:48.25#ibcon#end of sib2, iclass 5, count 2 2006.169.08:13:48.25#ibcon#*mode == 0, iclass 5, count 2 2006.169.08:13:48.25#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.169.08:13:48.25#ibcon#[27=AT03-04\r\n] 2006.169.08:13:48.25#ibcon#*before write, iclass 5, count 2 2006.169.08:13:48.25#ibcon#enter sib2, iclass 5, count 2 2006.169.08:13:48.25#ibcon#flushed, iclass 5, count 2 2006.169.08:13:48.25#ibcon#about to write, iclass 5, count 2 2006.169.08:13:48.25#ibcon#wrote, iclass 5, count 2 2006.169.08:13:48.25#ibcon#about to read 3, iclass 5, count 2 2006.169.08:13:48.28#ibcon#read 3, iclass 5, count 2 2006.169.08:13:48.28#ibcon#about to read 4, iclass 5, count 2 2006.169.08:13:48.28#ibcon#read 4, iclass 5, count 2 2006.169.08:13:48.28#ibcon#about to read 5, iclass 5, count 2 2006.169.08:13:48.28#ibcon#read 5, iclass 5, count 2 2006.169.08:13:48.28#ibcon#about to read 6, iclass 5, count 2 2006.169.08:13:48.28#ibcon#read 6, iclass 5, count 2 2006.169.08:13:48.28#ibcon#end of sib2, iclass 5, count 2 2006.169.08:13:48.28#ibcon#*after write, iclass 5, count 2 2006.169.08:13:48.28#ibcon#*before return 0, iclass 5, count 2 2006.169.08:13:48.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.169.08:13:48.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.169.08:13:48.28#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.169.08:13:48.28#ibcon#ireg 7 cls_cnt 0 2006.169.08:13:48.28#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.169.08:13:48.40#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.169.08:13:48.40#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.169.08:13:48.40#ibcon#enter wrdev, iclass 5, count 0 2006.169.08:13:48.40#ibcon#first serial, iclass 5, count 0 2006.169.08:13:48.40#ibcon#enter sib2, iclass 5, count 0 2006.169.08:13:48.40#ibcon#flushed, iclass 5, count 0 2006.169.08:13:48.40#ibcon#about to write, iclass 5, count 0 2006.169.08:13:48.40#ibcon#wrote, iclass 5, count 0 2006.169.08:13:48.40#ibcon#about to read 3, iclass 5, count 0 2006.169.08:13:48.42#ibcon#read 3, iclass 5, count 0 2006.169.08:13:48.42#ibcon#about to read 4, iclass 5, count 0 2006.169.08:13:48.42#ibcon#read 4, iclass 5, count 0 2006.169.08:13:48.42#ibcon#about to read 5, iclass 5, count 0 2006.169.08:13:48.42#ibcon#read 5, iclass 5, count 0 2006.169.08:13:48.42#ibcon#about to read 6, iclass 5, count 0 2006.169.08:13:48.42#ibcon#read 6, iclass 5, count 0 2006.169.08:13:48.42#ibcon#end of sib2, iclass 5, count 0 2006.169.08:13:48.42#ibcon#*mode == 0, iclass 5, count 0 2006.169.08:13:48.42#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.169.08:13:48.42#ibcon#[27=USB\r\n] 2006.169.08:13:48.42#ibcon#*before write, iclass 5, count 0 2006.169.08:13:48.42#ibcon#enter sib2, iclass 5, count 0 2006.169.08:13:48.42#ibcon#flushed, iclass 5, count 0 2006.169.08:13:48.42#ibcon#about to write, iclass 5, count 0 2006.169.08:13:48.42#ibcon#wrote, iclass 5, count 0 2006.169.08:13:48.42#ibcon#about to read 3, iclass 5, count 0 2006.169.08:13:48.45#ibcon#read 3, iclass 5, count 0 2006.169.08:13:48.45#ibcon#about to read 4, iclass 5, count 0 2006.169.08:13:48.45#ibcon#read 4, iclass 5, count 0 2006.169.08:13:48.45#ibcon#about to read 5, iclass 5, count 0 2006.169.08:13:48.45#ibcon#read 5, iclass 5, count 0 2006.169.08:13:48.45#ibcon#about to read 6, iclass 5, count 0 2006.169.08:13:48.45#ibcon#read 6, iclass 5, count 0 2006.169.08:13:48.45#ibcon#end of sib2, iclass 5, count 0 2006.169.08:13:48.45#ibcon#*after write, iclass 5, count 0 2006.169.08:13:48.45#ibcon#*before return 0, iclass 5, count 0 2006.169.08:13:48.45#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.169.08:13:48.45#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.169.08:13:48.45#ibcon#about to clear, iclass 5 cls_cnt 0 2006.169.08:13:48.45#ibcon#cleared, iclass 5 cls_cnt 0 2006.169.08:13:48.45$vc4f8/vblo=4,712.99 2006.169.08:13:48.45#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.169.08:13:48.45#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.169.08:13:48.45#ibcon#ireg 17 cls_cnt 0 2006.169.08:13:48.45#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.169.08:13:48.45#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.169.08:13:48.45#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.169.08:13:48.45#ibcon#enter wrdev, iclass 7, count 0 2006.169.08:13:48.45#ibcon#first serial, iclass 7, count 0 2006.169.08:13:48.45#ibcon#enter sib2, iclass 7, count 0 2006.169.08:13:48.45#ibcon#flushed, iclass 7, count 0 2006.169.08:13:48.45#ibcon#about to write, iclass 7, count 0 2006.169.08:13:48.45#ibcon#wrote, iclass 7, count 0 2006.169.08:13:48.45#ibcon#about to read 3, iclass 7, count 0 2006.169.08:13:48.47#ibcon#read 3, iclass 7, count 0 2006.169.08:13:48.47#ibcon#about to read 4, iclass 7, count 0 2006.169.08:13:48.47#ibcon#read 4, iclass 7, count 0 2006.169.08:13:48.47#ibcon#about to read 5, iclass 7, count 0 2006.169.08:13:48.47#ibcon#read 5, iclass 7, count 0 2006.169.08:13:48.47#ibcon#about to read 6, iclass 7, count 0 2006.169.08:13:48.47#ibcon#read 6, iclass 7, count 0 2006.169.08:13:48.47#ibcon#end of sib2, iclass 7, count 0 2006.169.08:13:48.47#ibcon#*mode == 0, iclass 7, count 0 2006.169.08:13:48.47#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.169.08:13:48.47#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.08:13:48.47#ibcon#*before write, iclass 7, count 0 2006.169.08:13:48.47#ibcon#enter sib2, iclass 7, count 0 2006.169.08:13:48.47#ibcon#flushed, iclass 7, count 0 2006.169.08:13:48.47#ibcon#about to write, iclass 7, count 0 2006.169.08:13:48.47#ibcon#wrote, iclass 7, count 0 2006.169.08:13:48.47#ibcon#about to read 3, iclass 7, count 0 2006.169.08:13:48.51#ibcon#read 3, iclass 7, count 0 2006.169.08:13:48.51#ibcon#about to read 4, iclass 7, count 0 2006.169.08:13:48.51#ibcon#read 4, iclass 7, count 0 2006.169.08:13:48.51#ibcon#about to read 5, iclass 7, count 0 2006.169.08:13:48.51#ibcon#read 5, iclass 7, count 0 2006.169.08:13:48.51#ibcon#about to read 6, iclass 7, count 0 2006.169.08:13:48.51#ibcon#read 6, iclass 7, count 0 2006.169.08:13:48.51#ibcon#end of sib2, iclass 7, count 0 2006.169.08:13:48.51#ibcon#*after write, iclass 7, count 0 2006.169.08:13:48.51#ibcon#*before return 0, iclass 7, count 0 2006.169.08:13:48.51#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.169.08:13:48.51#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.169.08:13:48.51#ibcon#about to clear, iclass 7 cls_cnt 0 2006.169.08:13:48.51#ibcon#cleared, iclass 7 cls_cnt 0 2006.169.08:13:48.51$vc4f8/vb=4,4 2006.169.08:13:48.51#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.169.08:13:48.51#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.169.08:13:48.51#ibcon#ireg 11 cls_cnt 2 2006.169.08:13:48.51#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.169.08:13:48.57#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.169.08:13:48.57#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.169.08:13:48.57#ibcon#enter wrdev, iclass 11, count 2 2006.169.08:13:48.57#ibcon#first serial, iclass 11, count 2 2006.169.08:13:48.57#ibcon#enter sib2, iclass 11, count 2 2006.169.08:13:48.57#ibcon#flushed, iclass 11, count 2 2006.169.08:13:48.57#ibcon#about to write, iclass 11, count 2 2006.169.08:13:48.57#ibcon#wrote, iclass 11, count 2 2006.169.08:13:48.57#ibcon#about to read 3, iclass 11, count 2 2006.169.08:13:48.59#ibcon#read 3, iclass 11, count 2 2006.169.08:13:48.59#ibcon#about to read 4, iclass 11, count 2 2006.169.08:13:48.59#ibcon#read 4, iclass 11, count 2 2006.169.08:13:48.59#ibcon#about to read 5, iclass 11, count 2 2006.169.08:13:48.59#ibcon#read 5, iclass 11, count 2 2006.169.08:13:48.59#ibcon#about to read 6, iclass 11, count 2 2006.169.08:13:48.59#ibcon#read 6, iclass 11, count 2 2006.169.08:13:48.59#ibcon#end of sib2, iclass 11, count 2 2006.169.08:13:48.59#ibcon#*mode == 0, iclass 11, count 2 2006.169.08:13:48.59#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.169.08:13:48.59#ibcon#[27=AT04-04\r\n] 2006.169.08:13:48.59#ibcon#*before write, iclass 11, count 2 2006.169.08:13:48.59#ibcon#enter sib2, iclass 11, count 2 2006.169.08:13:48.59#ibcon#flushed, iclass 11, count 2 2006.169.08:13:48.59#ibcon#about to write, iclass 11, count 2 2006.169.08:13:48.59#ibcon#wrote, iclass 11, count 2 2006.169.08:13:48.59#ibcon#about to read 3, iclass 11, count 2 2006.169.08:13:48.62#ibcon#read 3, iclass 11, count 2 2006.169.08:13:48.62#ibcon#about to read 4, iclass 11, count 2 2006.169.08:13:48.62#ibcon#read 4, iclass 11, count 2 2006.169.08:13:48.62#ibcon#about to read 5, iclass 11, count 2 2006.169.08:13:48.62#ibcon#read 5, iclass 11, count 2 2006.169.08:13:48.62#ibcon#about to read 6, iclass 11, count 2 2006.169.08:13:48.62#ibcon#read 6, iclass 11, count 2 2006.169.08:13:48.62#ibcon#end of sib2, iclass 11, count 2 2006.169.08:13:48.62#ibcon#*after write, iclass 11, count 2 2006.169.08:13:48.62#ibcon#*before return 0, iclass 11, count 2 2006.169.08:13:48.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.169.08:13:48.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.169.08:13:48.62#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.169.08:13:48.62#ibcon#ireg 7 cls_cnt 0 2006.169.08:13:48.62#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.169.08:13:48.74#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.169.08:13:48.74#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.169.08:13:48.74#ibcon#enter wrdev, iclass 11, count 0 2006.169.08:13:48.74#ibcon#first serial, iclass 11, count 0 2006.169.08:13:48.74#ibcon#enter sib2, iclass 11, count 0 2006.169.08:13:48.74#ibcon#flushed, iclass 11, count 0 2006.169.08:13:48.74#ibcon#about to write, iclass 11, count 0 2006.169.08:13:48.74#ibcon#wrote, iclass 11, count 0 2006.169.08:13:48.74#ibcon#about to read 3, iclass 11, count 0 2006.169.08:13:48.76#ibcon#read 3, iclass 11, count 0 2006.169.08:13:48.76#ibcon#about to read 4, iclass 11, count 0 2006.169.08:13:48.76#ibcon#read 4, iclass 11, count 0 2006.169.08:13:48.76#ibcon#about to read 5, iclass 11, count 0 2006.169.08:13:48.76#ibcon#read 5, iclass 11, count 0 2006.169.08:13:48.76#ibcon#about to read 6, iclass 11, count 0 2006.169.08:13:48.76#ibcon#read 6, iclass 11, count 0 2006.169.08:13:48.76#ibcon#end of sib2, iclass 11, count 0 2006.169.08:13:48.76#ibcon#*mode == 0, iclass 11, count 0 2006.169.08:13:48.76#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.169.08:13:48.76#ibcon#[27=USB\r\n] 2006.169.08:13:48.76#ibcon#*before write, iclass 11, count 0 2006.169.08:13:48.76#ibcon#enter sib2, iclass 11, count 0 2006.169.08:13:48.76#ibcon#flushed, iclass 11, count 0 2006.169.08:13:48.76#ibcon#about to write, iclass 11, count 0 2006.169.08:13:48.76#ibcon#wrote, iclass 11, count 0 2006.169.08:13:48.76#ibcon#about to read 3, iclass 11, count 0 2006.169.08:13:48.79#ibcon#read 3, iclass 11, count 0 2006.169.08:13:48.79#ibcon#about to read 4, iclass 11, count 0 2006.169.08:13:48.79#ibcon#read 4, iclass 11, count 0 2006.169.08:13:48.79#ibcon#about to read 5, iclass 11, count 0 2006.169.08:13:48.79#ibcon#read 5, iclass 11, count 0 2006.169.08:13:48.79#ibcon#about to read 6, iclass 11, count 0 2006.169.08:13:48.79#ibcon#read 6, iclass 11, count 0 2006.169.08:13:48.79#ibcon#end of sib2, iclass 11, count 0 2006.169.08:13:48.79#ibcon#*after write, iclass 11, count 0 2006.169.08:13:48.79#ibcon#*before return 0, iclass 11, count 0 2006.169.08:13:48.79#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.169.08:13:48.79#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.169.08:13:48.79#ibcon#about to clear, iclass 11 cls_cnt 0 2006.169.08:13:48.79#ibcon#cleared, iclass 11 cls_cnt 0 2006.169.08:13:48.79$vc4f8/vblo=5,744.99 2006.169.08:13:48.79#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.169.08:13:48.79#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.169.08:13:48.79#ibcon#ireg 17 cls_cnt 0 2006.169.08:13:48.79#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:13:48.79#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:13:48.79#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:13:48.79#ibcon#enter wrdev, iclass 13, count 0 2006.169.08:13:48.79#ibcon#first serial, iclass 13, count 0 2006.169.08:13:48.79#ibcon#enter sib2, iclass 13, count 0 2006.169.08:13:48.79#ibcon#flushed, iclass 13, count 0 2006.169.08:13:48.79#ibcon#about to write, iclass 13, count 0 2006.169.08:13:48.79#ibcon#wrote, iclass 13, count 0 2006.169.08:13:48.79#ibcon#about to read 3, iclass 13, count 0 2006.169.08:13:48.81#ibcon#read 3, iclass 13, count 0 2006.169.08:13:48.81#ibcon#about to read 4, iclass 13, count 0 2006.169.08:13:48.81#ibcon#read 4, iclass 13, count 0 2006.169.08:13:48.81#ibcon#about to read 5, iclass 13, count 0 2006.169.08:13:48.81#ibcon#read 5, iclass 13, count 0 2006.169.08:13:48.81#ibcon#about to read 6, iclass 13, count 0 2006.169.08:13:48.81#ibcon#read 6, iclass 13, count 0 2006.169.08:13:48.81#ibcon#end of sib2, iclass 13, count 0 2006.169.08:13:48.81#ibcon#*mode == 0, iclass 13, count 0 2006.169.08:13:48.81#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.08:13:48.81#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.08:13:48.81#ibcon#*before write, iclass 13, count 0 2006.169.08:13:48.81#ibcon#enter sib2, iclass 13, count 0 2006.169.08:13:48.81#ibcon#flushed, iclass 13, count 0 2006.169.08:13:48.81#ibcon#about to write, iclass 13, count 0 2006.169.08:13:48.81#ibcon#wrote, iclass 13, count 0 2006.169.08:13:48.81#ibcon#about to read 3, iclass 13, count 0 2006.169.08:13:48.85#ibcon#read 3, iclass 13, count 0 2006.169.08:13:48.85#ibcon#about to read 4, iclass 13, count 0 2006.169.08:13:48.85#ibcon#read 4, iclass 13, count 0 2006.169.08:13:48.85#ibcon#about to read 5, iclass 13, count 0 2006.169.08:13:48.85#ibcon#read 5, iclass 13, count 0 2006.169.08:13:48.85#ibcon#about to read 6, iclass 13, count 0 2006.169.08:13:48.85#ibcon#read 6, iclass 13, count 0 2006.169.08:13:48.85#ibcon#end of sib2, iclass 13, count 0 2006.169.08:13:48.85#ibcon#*after write, iclass 13, count 0 2006.169.08:13:48.85#ibcon#*before return 0, iclass 13, count 0 2006.169.08:13:48.85#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:13:48.85#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:13:48.85#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.08:13:48.85#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.08:13:48.85$vc4f8/vb=5,4 2006.169.08:13:48.85#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.169.08:13:48.85#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.169.08:13:48.85#ibcon#ireg 11 cls_cnt 2 2006.169.08:13:48.85#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.169.08:13:48.91#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.169.08:13:48.91#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.169.08:13:48.91#ibcon#enter wrdev, iclass 15, count 2 2006.169.08:13:48.91#ibcon#first serial, iclass 15, count 2 2006.169.08:13:48.91#ibcon#enter sib2, iclass 15, count 2 2006.169.08:13:48.91#ibcon#flushed, iclass 15, count 2 2006.169.08:13:48.91#ibcon#about to write, iclass 15, count 2 2006.169.08:13:48.91#ibcon#wrote, iclass 15, count 2 2006.169.08:13:48.91#ibcon#about to read 3, iclass 15, count 2 2006.169.08:13:48.93#ibcon#read 3, iclass 15, count 2 2006.169.08:13:48.93#ibcon#about to read 4, iclass 15, count 2 2006.169.08:13:48.93#ibcon#read 4, iclass 15, count 2 2006.169.08:13:48.93#ibcon#about to read 5, iclass 15, count 2 2006.169.08:13:48.93#ibcon#read 5, iclass 15, count 2 2006.169.08:13:48.93#ibcon#about to read 6, iclass 15, count 2 2006.169.08:13:48.93#ibcon#read 6, iclass 15, count 2 2006.169.08:13:48.93#ibcon#end of sib2, iclass 15, count 2 2006.169.08:13:48.93#ibcon#*mode == 0, iclass 15, count 2 2006.169.08:13:48.93#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.169.08:13:48.93#ibcon#[27=AT05-04\r\n] 2006.169.08:13:48.93#ibcon#*before write, iclass 15, count 2 2006.169.08:13:48.93#ibcon#enter sib2, iclass 15, count 2 2006.169.08:13:48.93#ibcon#flushed, iclass 15, count 2 2006.169.08:13:48.93#ibcon#about to write, iclass 15, count 2 2006.169.08:13:48.93#ibcon#wrote, iclass 15, count 2 2006.169.08:13:48.93#ibcon#about to read 3, iclass 15, count 2 2006.169.08:13:48.96#ibcon#read 3, iclass 15, count 2 2006.169.08:13:48.96#ibcon#about to read 4, iclass 15, count 2 2006.169.08:13:48.96#ibcon#read 4, iclass 15, count 2 2006.169.08:13:48.96#ibcon#about to read 5, iclass 15, count 2 2006.169.08:13:48.96#ibcon#read 5, iclass 15, count 2 2006.169.08:13:48.96#ibcon#about to read 6, iclass 15, count 2 2006.169.08:13:48.96#ibcon#read 6, iclass 15, count 2 2006.169.08:13:48.96#ibcon#end of sib2, iclass 15, count 2 2006.169.08:13:48.96#ibcon#*after write, iclass 15, count 2 2006.169.08:13:48.96#ibcon#*before return 0, iclass 15, count 2 2006.169.08:13:48.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.169.08:13:48.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.169.08:13:48.96#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.169.08:13:48.96#ibcon#ireg 7 cls_cnt 0 2006.169.08:13:48.96#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.169.08:13:49.08#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.169.08:13:49.08#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.169.08:13:49.08#ibcon#enter wrdev, iclass 15, count 0 2006.169.08:13:49.08#ibcon#first serial, iclass 15, count 0 2006.169.08:13:49.08#ibcon#enter sib2, iclass 15, count 0 2006.169.08:13:49.08#ibcon#flushed, iclass 15, count 0 2006.169.08:13:49.08#ibcon#about to write, iclass 15, count 0 2006.169.08:13:49.08#ibcon#wrote, iclass 15, count 0 2006.169.08:13:49.08#ibcon#about to read 3, iclass 15, count 0 2006.169.08:13:49.10#ibcon#read 3, iclass 15, count 0 2006.169.08:13:49.10#ibcon#about to read 4, iclass 15, count 0 2006.169.08:13:49.10#ibcon#read 4, iclass 15, count 0 2006.169.08:13:49.10#ibcon#about to read 5, iclass 15, count 0 2006.169.08:13:49.10#ibcon#read 5, iclass 15, count 0 2006.169.08:13:49.10#ibcon#about to read 6, iclass 15, count 0 2006.169.08:13:49.10#ibcon#read 6, iclass 15, count 0 2006.169.08:13:49.10#ibcon#end of sib2, iclass 15, count 0 2006.169.08:13:49.10#ibcon#*mode == 0, iclass 15, count 0 2006.169.08:13:49.10#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.169.08:13:49.10#ibcon#[27=USB\r\n] 2006.169.08:13:49.10#ibcon#*before write, iclass 15, count 0 2006.169.08:13:49.10#ibcon#enter sib2, iclass 15, count 0 2006.169.08:13:49.10#ibcon#flushed, iclass 15, count 0 2006.169.08:13:49.10#ibcon#about to write, iclass 15, count 0 2006.169.08:13:49.10#ibcon#wrote, iclass 15, count 0 2006.169.08:13:49.10#ibcon#about to read 3, iclass 15, count 0 2006.169.08:13:49.13#ibcon#read 3, iclass 15, count 0 2006.169.08:13:49.13#ibcon#about to read 4, iclass 15, count 0 2006.169.08:13:49.13#ibcon#read 4, iclass 15, count 0 2006.169.08:13:49.13#ibcon#about to read 5, iclass 15, count 0 2006.169.08:13:49.13#ibcon#read 5, iclass 15, count 0 2006.169.08:13:49.13#ibcon#about to read 6, iclass 15, count 0 2006.169.08:13:49.13#ibcon#read 6, iclass 15, count 0 2006.169.08:13:49.13#ibcon#end of sib2, iclass 15, count 0 2006.169.08:13:49.13#ibcon#*after write, iclass 15, count 0 2006.169.08:13:49.13#ibcon#*before return 0, iclass 15, count 0 2006.169.08:13:49.13#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.169.08:13:49.13#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.169.08:13:49.13#ibcon#about to clear, iclass 15 cls_cnt 0 2006.169.08:13:49.13#ibcon#cleared, iclass 15 cls_cnt 0 2006.169.08:13:49.13$vc4f8/vblo=6,752.99 2006.169.08:13:49.13#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.169.08:13:49.13#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.169.08:13:49.13#ibcon#ireg 17 cls_cnt 0 2006.169.08:13:49.13#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:13:49.13#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:13:49.13#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:13:49.13#ibcon#enter wrdev, iclass 17, count 0 2006.169.08:13:49.13#ibcon#first serial, iclass 17, count 0 2006.169.08:13:49.13#ibcon#enter sib2, iclass 17, count 0 2006.169.08:13:49.13#ibcon#flushed, iclass 17, count 0 2006.169.08:13:49.13#ibcon#about to write, iclass 17, count 0 2006.169.08:13:49.13#ibcon#wrote, iclass 17, count 0 2006.169.08:13:49.13#ibcon#about to read 3, iclass 17, count 0 2006.169.08:13:49.15#ibcon#read 3, iclass 17, count 0 2006.169.08:13:49.15#ibcon#about to read 4, iclass 17, count 0 2006.169.08:13:49.15#ibcon#read 4, iclass 17, count 0 2006.169.08:13:49.15#ibcon#about to read 5, iclass 17, count 0 2006.169.08:13:49.15#ibcon#read 5, iclass 17, count 0 2006.169.08:13:49.15#ibcon#about to read 6, iclass 17, count 0 2006.169.08:13:49.15#ibcon#read 6, iclass 17, count 0 2006.169.08:13:49.15#ibcon#end of sib2, iclass 17, count 0 2006.169.08:13:49.15#ibcon#*mode == 0, iclass 17, count 0 2006.169.08:13:49.15#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.169.08:13:49.15#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.08:13:49.15#ibcon#*before write, iclass 17, count 0 2006.169.08:13:49.15#ibcon#enter sib2, iclass 17, count 0 2006.169.08:13:49.15#ibcon#flushed, iclass 17, count 0 2006.169.08:13:49.15#ibcon#about to write, iclass 17, count 0 2006.169.08:13:49.15#ibcon#wrote, iclass 17, count 0 2006.169.08:13:49.15#ibcon#about to read 3, iclass 17, count 0 2006.169.08:13:49.19#ibcon#read 3, iclass 17, count 0 2006.169.08:13:49.19#ibcon#about to read 4, iclass 17, count 0 2006.169.08:13:49.19#ibcon#read 4, iclass 17, count 0 2006.169.08:13:49.19#ibcon#about to read 5, iclass 17, count 0 2006.169.08:13:49.19#ibcon#read 5, iclass 17, count 0 2006.169.08:13:49.19#ibcon#about to read 6, iclass 17, count 0 2006.169.08:13:49.19#ibcon#read 6, iclass 17, count 0 2006.169.08:13:49.19#ibcon#end of sib2, iclass 17, count 0 2006.169.08:13:49.19#ibcon#*after write, iclass 17, count 0 2006.169.08:13:49.19#ibcon#*before return 0, iclass 17, count 0 2006.169.08:13:49.19#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:13:49.19#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:13:49.19#ibcon#about to clear, iclass 17 cls_cnt 0 2006.169.08:13:49.19#ibcon#cleared, iclass 17 cls_cnt 0 2006.169.08:13:49.19$vc4f8/vb=6,4 2006.169.08:13:49.19#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.169.08:13:49.19#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.169.08:13:49.19#ibcon#ireg 11 cls_cnt 2 2006.169.08:13:49.19#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.169.08:13:49.25#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.169.08:13:49.25#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.169.08:13:49.25#ibcon#enter wrdev, iclass 19, count 2 2006.169.08:13:49.25#ibcon#first serial, iclass 19, count 2 2006.169.08:13:49.25#ibcon#enter sib2, iclass 19, count 2 2006.169.08:13:49.25#ibcon#flushed, iclass 19, count 2 2006.169.08:13:49.25#ibcon#about to write, iclass 19, count 2 2006.169.08:13:49.25#ibcon#wrote, iclass 19, count 2 2006.169.08:13:49.25#ibcon#about to read 3, iclass 19, count 2 2006.169.08:13:49.27#ibcon#read 3, iclass 19, count 2 2006.169.08:13:49.27#ibcon#about to read 4, iclass 19, count 2 2006.169.08:13:49.27#ibcon#read 4, iclass 19, count 2 2006.169.08:13:49.27#ibcon#about to read 5, iclass 19, count 2 2006.169.08:13:49.27#ibcon#read 5, iclass 19, count 2 2006.169.08:13:49.27#ibcon#about to read 6, iclass 19, count 2 2006.169.08:13:49.27#ibcon#read 6, iclass 19, count 2 2006.169.08:13:49.27#ibcon#end of sib2, iclass 19, count 2 2006.169.08:13:49.27#ibcon#*mode == 0, iclass 19, count 2 2006.169.08:13:49.27#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.169.08:13:49.27#ibcon#[27=AT06-04\r\n] 2006.169.08:13:49.27#ibcon#*before write, iclass 19, count 2 2006.169.08:13:49.27#ibcon#enter sib2, iclass 19, count 2 2006.169.08:13:49.27#ibcon#flushed, iclass 19, count 2 2006.169.08:13:49.27#ibcon#about to write, iclass 19, count 2 2006.169.08:13:49.27#ibcon#wrote, iclass 19, count 2 2006.169.08:13:49.27#ibcon#about to read 3, iclass 19, count 2 2006.169.08:13:49.30#ibcon#read 3, iclass 19, count 2 2006.169.08:13:49.30#ibcon#about to read 4, iclass 19, count 2 2006.169.08:13:49.30#ibcon#read 4, iclass 19, count 2 2006.169.08:13:49.30#ibcon#about to read 5, iclass 19, count 2 2006.169.08:13:49.30#ibcon#read 5, iclass 19, count 2 2006.169.08:13:49.30#ibcon#about to read 6, iclass 19, count 2 2006.169.08:13:49.30#ibcon#read 6, iclass 19, count 2 2006.169.08:13:49.30#ibcon#end of sib2, iclass 19, count 2 2006.169.08:13:49.30#ibcon#*after write, iclass 19, count 2 2006.169.08:13:49.30#ibcon#*before return 0, iclass 19, count 2 2006.169.08:13:49.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.169.08:13:49.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.169.08:13:49.30#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.169.08:13:49.30#ibcon#ireg 7 cls_cnt 0 2006.169.08:13:49.30#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.169.08:13:49.42#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.169.08:13:49.42#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.169.08:13:49.42#ibcon#enter wrdev, iclass 19, count 0 2006.169.08:13:49.42#ibcon#first serial, iclass 19, count 0 2006.169.08:13:49.42#ibcon#enter sib2, iclass 19, count 0 2006.169.08:13:49.42#ibcon#flushed, iclass 19, count 0 2006.169.08:13:49.42#ibcon#about to write, iclass 19, count 0 2006.169.08:13:49.42#ibcon#wrote, iclass 19, count 0 2006.169.08:13:49.42#ibcon#about to read 3, iclass 19, count 0 2006.169.08:13:49.44#ibcon#read 3, iclass 19, count 0 2006.169.08:13:49.44#ibcon#about to read 4, iclass 19, count 0 2006.169.08:13:49.44#ibcon#read 4, iclass 19, count 0 2006.169.08:13:49.44#ibcon#about to read 5, iclass 19, count 0 2006.169.08:13:49.44#ibcon#read 5, iclass 19, count 0 2006.169.08:13:49.44#ibcon#about to read 6, iclass 19, count 0 2006.169.08:13:49.44#ibcon#read 6, iclass 19, count 0 2006.169.08:13:49.44#ibcon#end of sib2, iclass 19, count 0 2006.169.08:13:49.44#ibcon#*mode == 0, iclass 19, count 0 2006.169.08:13:49.44#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.169.08:13:49.44#ibcon#[27=USB\r\n] 2006.169.08:13:49.44#ibcon#*before write, iclass 19, count 0 2006.169.08:13:49.44#ibcon#enter sib2, iclass 19, count 0 2006.169.08:13:49.44#ibcon#flushed, iclass 19, count 0 2006.169.08:13:49.44#ibcon#about to write, iclass 19, count 0 2006.169.08:13:49.44#ibcon#wrote, iclass 19, count 0 2006.169.08:13:49.44#ibcon#about to read 3, iclass 19, count 0 2006.169.08:13:49.47#ibcon#read 3, iclass 19, count 0 2006.169.08:13:49.47#ibcon#about to read 4, iclass 19, count 0 2006.169.08:13:49.47#ibcon#read 4, iclass 19, count 0 2006.169.08:13:49.47#ibcon#about to read 5, iclass 19, count 0 2006.169.08:13:49.47#ibcon#read 5, iclass 19, count 0 2006.169.08:13:49.47#ibcon#about to read 6, iclass 19, count 0 2006.169.08:13:49.47#ibcon#read 6, iclass 19, count 0 2006.169.08:13:49.47#ibcon#end of sib2, iclass 19, count 0 2006.169.08:13:49.47#ibcon#*after write, iclass 19, count 0 2006.169.08:13:49.47#ibcon#*before return 0, iclass 19, count 0 2006.169.08:13:49.47#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.169.08:13:49.47#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.169.08:13:49.47#ibcon#about to clear, iclass 19 cls_cnt 0 2006.169.08:13:49.47#ibcon#cleared, iclass 19 cls_cnt 0 2006.169.08:13:49.47$vc4f8/vabw=wide 2006.169.08:13:49.47#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.169.08:13:49.47#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.169.08:13:49.47#ibcon#ireg 8 cls_cnt 0 2006.169.08:13:49.47#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.169.08:13:49.47#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.169.08:13:49.47#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.169.08:13:49.47#ibcon#enter wrdev, iclass 21, count 0 2006.169.08:13:49.47#ibcon#first serial, iclass 21, count 0 2006.169.08:13:49.47#ibcon#enter sib2, iclass 21, count 0 2006.169.08:13:49.47#ibcon#flushed, iclass 21, count 0 2006.169.08:13:49.47#ibcon#about to write, iclass 21, count 0 2006.169.08:13:49.47#ibcon#wrote, iclass 21, count 0 2006.169.08:13:49.47#ibcon#about to read 3, iclass 21, count 0 2006.169.08:13:49.49#ibcon#read 3, iclass 21, count 0 2006.169.08:13:49.49#ibcon#about to read 4, iclass 21, count 0 2006.169.08:13:49.49#ibcon#read 4, iclass 21, count 0 2006.169.08:13:49.49#ibcon#about to read 5, iclass 21, count 0 2006.169.08:13:49.49#ibcon#read 5, iclass 21, count 0 2006.169.08:13:49.49#ibcon#about to read 6, iclass 21, count 0 2006.169.08:13:49.49#ibcon#read 6, iclass 21, count 0 2006.169.08:13:49.49#ibcon#end of sib2, iclass 21, count 0 2006.169.08:13:49.49#ibcon#*mode == 0, iclass 21, count 0 2006.169.08:13:49.49#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.169.08:13:49.49#ibcon#[25=BW32\r\n] 2006.169.08:13:49.49#ibcon#*before write, iclass 21, count 0 2006.169.08:13:49.49#ibcon#enter sib2, iclass 21, count 0 2006.169.08:13:49.49#ibcon#flushed, iclass 21, count 0 2006.169.08:13:49.49#ibcon#about to write, iclass 21, count 0 2006.169.08:13:49.49#ibcon#wrote, iclass 21, count 0 2006.169.08:13:49.49#ibcon#about to read 3, iclass 21, count 0 2006.169.08:13:49.52#ibcon#read 3, iclass 21, count 0 2006.169.08:13:49.52#ibcon#about to read 4, iclass 21, count 0 2006.169.08:13:49.52#ibcon#read 4, iclass 21, count 0 2006.169.08:13:49.52#ibcon#about to read 5, iclass 21, count 0 2006.169.08:13:49.52#ibcon#read 5, iclass 21, count 0 2006.169.08:13:49.52#ibcon#about to read 6, iclass 21, count 0 2006.169.08:13:49.52#ibcon#read 6, iclass 21, count 0 2006.169.08:13:49.52#ibcon#end of sib2, iclass 21, count 0 2006.169.08:13:49.52#ibcon#*after write, iclass 21, count 0 2006.169.08:13:49.52#ibcon#*before return 0, iclass 21, count 0 2006.169.08:13:49.52#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.169.08:13:49.52#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.169.08:13:49.52#ibcon#about to clear, iclass 21 cls_cnt 0 2006.169.08:13:49.52#ibcon#cleared, iclass 21 cls_cnt 0 2006.169.08:13:49.52$vc4f8/vbbw=wide 2006.169.08:13:49.52#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.169.08:13:49.52#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.169.08:13:49.52#ibcon#ireg 8 cls_cnt 0 2006.169.08:13:49.52#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:13:49.59#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:13:49.59#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:13:49.59#ibcon#enter wrdev, iclass 23, count 0 2006.169.08:13:49.59#ibcon#first serial, iclass 23, count 0 2006.169.08:13:49.59#ibcon#enter sib2, iclass 23, count 0 2006.169.08:13:49.59#ibcon#flushed, iclass 23, count 0 2006.169.08:13:49.59#ibcon#about to write, iclass 23, count 0 2006.169.08:13:49.59#ibcon#wrote, iclass 23, count 0 2006.169.08:13:49.59#ibcon#about to read 3, iclass 23, count 0 2006.169.08:13:49.61#ibcon#read 3, iclass 23, count 0 2006.169.08:13:49.61#ibcon#about to read 4, iclass 23, count 0 2006.169.08:13:49.61#ibcon#read 4, iclass 23, count 0 2006.169.08:13:49.61#ibcon#about to read 5, iclass 23, count 0 2006.169.08:13:49.61#ibcon#read 5, iclass 23, count 0 2006.169.08:13:49.61#ibcon#about to read 6, iclass 23, count 0 2006.169.08:13:49.61#ibcon#read 6, iclass 23, count 0 2006.169.08:13:49.61#ibcon#end of sib2, iclass 23, count 0 2006.169.08:13:49.61#ibcon#*mode == 0, iclass 23, count 0 2006.169.08:13:49.61#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.169.08:13:49.61#ibcon#[27=BW32\r\n] 2006.169.08:13:49.61#ibcon#*before write, iclass 23, count 0 2006.169.08:13:49.61#ibcon#enter sib2, iclass 23, count 0 2006.169.08:13:49.61#ibcon#flushed, iclass 23, count 0 2006.169.08:13:49.61#ibcon#about to write, iclass 23, count 0 2006.169.08:13:49.61#ibcon#wrote, iclass 23, count 0 2006.169.08:13:49.61#ibcon#about to read 3, iclass 23, count 0 2006.169.08:13:49.64#ibcon#read 3, iclass 23, count 0 2006.169.08:13:49.64#ibcon#about to read 4, iclass 23, count 0 2006.169.08:13:49.64#ibcon#read 4, iclass 23, count 0 2006.169.08:13:49.64#ibcon#about to read 5, iclass 23, count 0 2006.169.08:13:49.64#ibcon#read 5, iclass 23, count 0 2006.169.08:13:49.64#ibcon#about to read 6, iclass 23, count 0 2006.169.08:13:49.64#ibcon#read 6, iclass 23, count 0 2006.169.08:13:49.64#ibcon#end of sib2, iclass 23, count 0 2006.169.08:13:49.64#ibcon#*after write, iclass 23, count 0 2006.169.08:13:49.64#ibcon#*before return 0, iclass 23, count 0 2006.169.08:13:49.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:13:49.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:13:49.64#ibcon#about to clear, iclass 23 cls_cnt 0 2006.169.08:13:49.64#ibcon#cleared, iclass 23 cls_cnt 0 2006.169.08:13:49.64$4f8m12a/ifd4f 2006.169.08:13:49.64$ifd4f/lo= 2006.169.08:13:49.64$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.08:13:49.64$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.08:13:49.64$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.08:13:49.64$ifd4f/patch= 2006.169.08:13:49.64$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.08:13:49.64$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.08:13:49.64$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.08:13:49.64$4f8m12a/"form=m,16.000,1:2 2006.169.08:13:49.64$4f8m12a/"tpicd 2006.169.08:13:49.64$4f8m12a/echo=off 2006.169.08:13:49.64$4f8m12a/xlog=off 2006.169.08:13:49.64:!2006.169.08:14:00 2006.169.08:14:00.00:preob 2006.169.08:14:01.14/onsource/TRACKING 2006.169.08:14:01.14:!2006.169.08:14:10 2006.169.08:14:10.00:data_valid=on 2006.169.08:14:10.00:midob 2006.169.08:14:10.14/onsource/TRACKING 2006.169.08:14:10.14/wx/18.14,1003.8,100 2006.169.08:14:10.26/cable/+6.5289E-03 2006.169.08:14:11.35/va/01,08,usb,yes,43,46 2006.169.08:14:11.35/va/02,07,usb,yes,44,46 2006.169.08:14:11.35/va/03,06,usb,yes,47,47 2006.169.08:14:11.35/va/04,07,usb,yes,45,49 2006.169.08:14:11.35/va/05,07,usb,yes,49,52 2006.169.08:14:11.35/va/06,06,usb,yes,49,48 2006.169.08:14:11.35/va/07,06,usb,yes,49,49 2006.169.08:14:11.35/va/08,07,usb,yes,47,46 2006.169.08:14:11.58/valo/01,532.99,yes,locked 2006.169.08:14:11.58/valo/02,572.99,yes,locked 2006.169.08:14:11.58/valo/03,672.99,yes,locked 2006.169.08:14:11.58/valo/04,832.99,yes,locked 2006.169.08:14:11.58/valo/05,652.99,yes,locked 2006.169.08:14:11.58/valo/06,772.99,yes,locked 2006.169.08:14:11.58/valo/07,832.99,yes,locked 2006.169.08:14:11.58/valo/08,852.99,yes,locked 2006.169.08:14:12.67/vb/01,04,usb,yes,30,28 2006.169.08:14:12.67/vb/02,04,usb,yes,32,33 2006.169.08:14:12.67/vb/03,04,usb,yes,28,32 2006.169.08:14:12.67/vb/04,04,usb,yes,29,29 2006.169.08:14:12.67/vb/05,04,usb,yes,27,31 2006.169.08:14:12.67/vb/06,04,usb,yes,28,31 2006.169.08:14:12.67/vb/07,04,usb,yes,30,30 2006.169.08:14:12.67/vb/08,04,usb,yes,28,31 2006.169.08:14:12.90/vblo/01,632.99,yes,locked 2006.169.08:14:12.90/vblo/02,640.99,yes,locked 2006.169.08:14:12.90/vblo/03,656.99,yes,locked 2006.169.08:14:12.90/vblo/04,712.99,yes,locked 2006.169.08:14:12.90/vblo/05,744.99,yes,locked 2006.169.08:14:12.90/vblo/06,752.99,yes,locked 2006.169.08:14:12.90/vblo/07,734.99,yes,locked 2006.169.08:14:12.90/vblo/08,744.99,yes,locked 2006.169.08:14:13.05/vabw/8 2006.169.08:14:13.20/vbbw/8 2006.169.08:14:13.29/xfe/off,on,15.0 2006.169.08:14:13.67/ifatt/23,28,28,28 2006.169.08:14:14.08/fmout-gps/S +4.17E-07 2006.169.08:14:14.16:!2006.169.08:15:10 2006.169.08:15:10.00:data_valid=off 2006.169.08:15:10.00:postob 2006.169.08:15:10.16/cable/+6.5315E-03 2006.169.08:15:10.16/wx/18.13,1003.9,100 2006.169.08:15:11.08/fmout-gps/S +4.17E-07 2006.169.08:15:11.08:scan_name=169-0816,k06169,60 2006.169.08:15:11.08:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.169.08:15:11.14#flagr#flagr/antenna,new-source 2006.169.08:15:12.14:checkk5 2006.169.08:15:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.169.08:15:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.169.08:15:16.92/chk_autoobs//k5ts3?ERROR: timeout happened! 2006.169.08:15:17.30/chk_autoobs//k5ts4/ autoobs is running! 2006.169.08:15:17.67/chk_obsdata//k5ts1/T1690814??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.08:15:18.04/chk_obsdata//k5ts2/T1690814??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.08:15:25.10/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.08:15:25.47/chk_obsdata//k5ts4/T1690814??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.08:15:26.17/k5log//k5ts1_log_newline 2006.169.08:15:26.86/k5log//k5ts2_log_newline 2006.169.08:15:30.13#trakl#Source acquired 2006.169.08:15:32.14#flagr#flagr/antenna,acquired 2006.169.08:15:33.97/k5log//k5ts3?ERROR: timeout happened! 2006.169.08:15:34.66/k5log//k5ts4_log_newline 2006.169.08:15:34.82/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.08:15:34.82:4f8m12a=2 2006.169.08:15:34.82$4f8m12a/echo=on 2006.169.08:15:34.82$4f8m12a/pcalon 2006.169.08:15:34.82$pcalon/"no phase cal control is implemented here 2006.169.08:15:34.82$4f8m12a/"tpicd=stop 2006.169.08:15:34.82$4f8m12a/vc4f8 2006.169.08:15:34.82$vc4f8/valo=1,532.99 2006.169.08:15:34.83#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.169.08:15:34.83#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.169.08:15:34.83#ibcon#ireg 17 cls_cnt 0 2006.169.08:15:34.83#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:15:34.83#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:15:34.83#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:15:34.83#ibcon#enter wrdev, iclass 34, count 0 2006.169.08:15:34.83#ibcon#first serial, iclass 34, count 0 2006.169.08:15:34.83#ibcon#enter sib2, iclass 34, count 0 2006.169.08:15:34.83#ibcon#flushed, iclass 34, count 0 2006.169.08:15:34.83#ibcon#about to write, iclass 34, count 0 2006.169.08:15:34.83#ibcon#wrote, iclass 34, count 0 2006.169.08:15:34.83#ibcon#about to read 3, iclass 34, count 0 2006.169.08:15:34.84#ibcon#read 3, iclass 34, count 0 2006.169.08:15:34.84#ibcon#about to read 4, iclass 34, count 0 2006.169.08:15:34.84#ibcon#read 4, iclass 34, count 0 2006.169.08:15:34.84#ibcon#about to read 5, iclass 34, count 0 2006.169.08:15:34.85#ibcon#read 5, iclass 34, count 0 2006.169.08:15:34.85#ibcon#about to read 6, iclass 34, count 0 2006.169.08:15:34.85#ibcon#read 6, iclass 34, count 0 2006.169.08:15:34.85#ibcon#end of sib2, iclass 34, count 0 2006.169.08:15:34.85#ibcon#*mode == 0, iclass 34, count 0 2006.169.08:15:34.85#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.169.08:15:34.85#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.08:15:34.85#ibcon#*before write, iclass 34, count 0 2006.169.08:15:34.85#ibcon#enter sib2, iclass 34, count 0 2006.169.08:15:34.85#ibcon#flushed, iclass 34, count 0 2006.169.08:15:34.85#ibcon#about to write, iclass 34, count 0 2006.169.08:15:34.85#ibcon#wrote, iclass 34, count 0 2006.169.08:15:34.85#ibcon#about to read 3, iclass 34, count 0 2006.169.08:15:34.90#ibcon#read 3, iclass 34, count 0 2006.169.08:15:34.90#ibcon#about to read 4, iclass 34, count 0 2006.169.08:15:34.90#ibcon#read 4, iclass 34, count 0 2006.169.08:15:34.90#ibcon#about to read 5, iclass 34, count 0 2006.169.08:15:34.90#ibcon#read 5, iclass 34, count 0 2006.169.08:15:34.90#ibcon#about to read 6, iclass 34, count 0 2006.169.08:15:34.90#ibcon#read 6, iclass 34, count 0 2006.169.08:15:34.90#ibcon#end of sib2, iclass 34, count 0 2006.169.08:15:34.90#ibcon#*after write, iclass 34, count 0 2006.169.08:15:34.90#ibcon#*before return 0, iclass 34, count 0 2006.169.08:15:34.90#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:15:34.90#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:15:34.90#ibcon#about to clear, iclass 34 cls_cnt 0 2006.169.08:15:34.90#ibcon#cleared, iclass 34 cls_cnt 0 2006.169.08:15:34.90$vc4f8/va=1,8 2006.169.08:15:34.90#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.169.08:15:34.90#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.169.08:15:34.90#ibcon#ireg 11 cls_cnt 2 2006.169.08:15:34.90#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.169.08:15:34.90#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.169.08:15:34.90#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.169.08:15:34.90#ibcon#enter wrdev, iclass 36, count 2 2006.169.08:15:34.90#ibcon#first serial, iclass 36, count 2 2006.169.08:15:34.90#ibcon#enter sib2, iclass 36, count 2 2006.169.08:15:34.90#ibcon#flushed, iclass 36, count 2 2006.169.08:15:34.90#ibcon#about to write, iclass 36, count 2 2006.169.08:15:34.90#ibcon#wrote, iclass 36, count 2 2006.169.08:15:34.90#ibcon#about to read 3, iclass 36, count 2 2006.169.08:15:34.92#ibcon#read 3, iclass 36, count 2 2006.169.08:15:34.92#ibcon#about to read 4, iclass 36, count 2 2006.169.08:15:34.92#ibcon#read 4, iclass 36, count 2 2006.169.08:15:34.92#ibcon#about to read 5, iclass 36, count 2 2006.169.08:15:34.92#ibcon#read 5, iclass 36, count 2 2006.169.08:15:34.92#ibcon#about to read 6, iclass 36, count 2 2006.169.08:15:34.92#ibcon#read 6, iclass 36, count 2 2006.169.08:15:34.92#ibcon#end of sib2, iclass 36, count 2 2006.169.08:15:34.92#ibcon#*mode == 0, iclass 36, count 2 2006.169.08:15:34.92#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.169.08:15:34.92#ibcon#[25=AT01-08\r\n] 2006.169.08:15:34.92#ibcon#*before write, iclass 36, count 2 2006.169.08:15:34.92#ibcon#enter sib2, iclass 36, count 2 2006.169.08:15:34.92#ibcon#flushed, iclass 36, count 2 2006.169.08:15:34.92#ibcon#about to write, iclass 36, count 2 2006.169.08:15:34.92#ibcon#wrote, iclass 36, count 2 2006.169.08:15:34.92#ibcon#about to read 3, iclass 36, count 2 2006.169.08:15:34.94#ibcon#read 3, iclass 36, count 2 2006.169.08:15:34.94#ibcon#about to read 4, iclass 36, count 2 2006.169.08:15:34.94#ibcon#read 4, iclass 36, count 2 2006.169.08:15:34.94#ibcon#about to read 5, iclass 36, count 2 2006.169.08:15:34.95#ibcon#read 5, iclass 36, count 2 2006.169.08:15:34.95#ibcon#about to read 6, iclass 36, count 2 2006.169.08:15:34.95#ibcon#read 6, iclass 36, count 2 2006.169.08:15:34.95#ibcon#end of sib2, iclass 36, count 2 2006.169.08:15:34.95#ibcon#*after write, iclass 36, count 2 2006.169.08:15:34.95#ibcon#*before return 0, iclass 36, count 2 2006.169.08:15:34.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.169.08:15:34.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.169.08:15:34.95#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.169.08:15:34.95#ibcon#ireg 7 cls_cnt 0 2006.169.08:15:34.95#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.169.08:15:35.06#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.169.08:15:35.06#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.169.08:15:35.06#ibcon#enter wrdev, iclass 36, count 0 2006.169.08:15:35.06#ibcon#first serial, iclass 36, count 0 2006.169.08:15:35.06#ibcon#enter sib2, iclass 36, count 0 2006.169.08:15:35.06#ibcon#flushed, iclass 36, count 0 2006.169.08:15:35.07#ibcon#about to write, iclass 36, count 0 2006.169.08:15:35.07#ibcon#wrote, iclass 36, count 0 2006.169.08:15:35.07#ibcon#about to read 3, iclass 36, count 0 2006.169.08:15:35.10#ibcon#read 3, iclass 36, count 0 2006.169.08:15:35.10#ibcon#about to read 4, iclass 36, count 0 2006.169.08:15:35.10#ibcon#read 4, iclass 36, count 0 2006.169.08:15:35.10#ibcon#about to read 5, iclass 36, count 0 2006.169.08:15:35.10#ibcon#read 5, iclass 36, count 0 2006.169.08:15:35.10#ibcon#about to read 6, iclass 36, count 0 2006.169.08:15:35.10#ibcon#read 6, iclass 36, count 0 2006.169.08:15:35.10#ibcon#end of sib2, iclass 36, count 0 2006.169.08:15:35.10#ibcon#*mode == 0, iclass 36, count 0 2006.169.08:15:35.10#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.169.08:15:35.10#ibcon#[25=USB\r\n] 2006.169.08:15:35.10#ibcon#*before write, iclass 36, count 0 2006.169.08:15:35.10#ibcon#enter sib2, iclass 36, count 0 2006.169.08:15:35.10#ibcon#flushed, iclass 36, count 0 2006.169.08:15:35.10#ibcon#about to write, iclass 36, count 0 2006.169.08:15:35.10#ibcon#wrote, iclass 36, count 0 2006.169.08:15:35.10#ibcon#about to read 3, iclass 36, count 0 2006.169.08:15:35.13#ibcon#read 3, iclass 36, count 0 2006.169.08:15:35.13#ibcon#about to read 4, iclass 36, count 0 2006.169.08:15:35.13#ibcon#read 4, iclass 36, count 0 2006.169.08:15:35.13#ibcon#about to read 5, iclass 36, count 0 2006.169.08:15:35.14#ibcon#read 5, iclass 36, count 0 2006.169.08:15:35.14#ibcon#about to read 6, iclass 36, count 0 2006.169.08:15:35.14#ibcon#read 6, iclass 36, count 0 2006.169.08:15:35.14#ibcon#end of sib2, iclass 36, count 0 2006.169.08:15:35.14#ibcon#*after write, iclass 36, count 0 2006.169.08:15:35.14#ibcon#*before return 0, iclass 36, count 0 2006.169.08:15:35.14#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.169.08:15:35.14#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.169.08:15:35.14#ibcon#about to clear, iclass 36 cls_cnt 0 2006.169.08:15:35.14#ibcon#cleared, iclass 36 cls_cnt 0 2006.169.08:15:35.14$vc4f8/valo=2,572.99 2006.169.08:15:35.14#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.169.08:15:35.14#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.169.08:15:35.14#ibcon#ireg 17 cls_cnt 0 2006.169.08:15:35.14#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.169.08:15:35.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.169.08:15:35.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.169.08:15:35.14#ibcon#enter wrdev, iclass 38, count 0 2006.169.08:15:35.14#ibcon#first serial, iclass 38, count 0 2006.169.08:15:35.14#ibcon#enter sib2, iclass 38, count 0 2006.169.08:15:35.14#ibcon#flushed, iclass 38, count 0 2006.169.08:15:35.14#ibcon#about to write, iclass 38, count 0 2006.169.08:15:35.14#ibcon#wrote, iclass 38, count 0 2006.169.08:15:35.14#ibcon#about to read 3, iclass 38, count 0 2006.169.08:15:35.15#ibcon#read 3, iclass 38, count 0 2006.169.08:15:35.15#ibcon#about to read 4, iclass 38, count 0 2006.169.08:15:35.16#ibcon#read 4, iclass 38, count 0 2006.169.08:15:35.16#ibcon#about to read 5, iclass 38, count 0 2006.169.08:15:35.16#ibcon#read 5, iclass 38, count 0 2006.169.08:15:35.16#ibcon#about to read 6, iclass 38, count 0 2006.169.08:15:35.16#ibcon#read 6, iclass 38, count 0 2006.169.08:15:35.16#ibcon#end of sib2, iclass 38, count 0 2006.169.08:15:35.16#ibcon#*mode == 0, iclass 38, count 0 2006.169.08:15:35.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.169.08:15:35.16#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.08:15:35.16#ibcon#*before write, iclass 38, count 0 2006.169.08:15:35.16#ibcon#enter sib2, iclass 38, count 0 2006.169.08:15:35.16#ibcon#flushed, iclass 38, count 0 2006.169.08:15:35.16#ibcon#about to write, iclass 38, count 0 2006.169.08:15:35.16#ibcon#wrote, iclass 38, count 0 2006.169.08:15:35.16#ibcon#about to read 3, iclass 38, count 0 2006.169.08:15:35.19#ibcon#read 3, iclass 38, count 0 2006.169.08:15:35.19#ibcon#about to read 4, iclass 38, count 0 2006.169.08:15:35.19#ibcon#read 4, iclass 38, count 0 2006.169.08:15:35.19#ibcon#about to read 5, iclass 38, count 0 2006.169.08:15:35.19#ibcon#read 5, iclass 38, count 0 2006.169.08:15:35.20#ibcon#about to read 6, iclass 38, count 0 2006.169.08:15:35.20#ibcon#read 6, iclass 38, count 0 2006.169.08:15:35.20#ibcon#end of sib2, iclass 38, count 0 2006.169.08:15:35.20#ibcon#*after write, iclass 38, count 0 2006.169.08:15:35.20#ibcon#*before return 0, iclass 38, count 0 2006.169.08:15:35.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.169.08:15:35.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.169.08:15:35.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.169.08:15:35.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.169.08:15:35.20$vc4f8/va=2,7 2006.169.08:15:35.20#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.169.08:15:35.20#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.169.08:15:35.20#ibcon#ireg 11 cls_cnt 2 2006.169.08:15:35.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.169.08:15:35.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.169.08:15:35.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.169.08:15:35.25#ibcon#enter wrdev, iclass 40, count 2 2006.169.08:15:35.25#ibcon#first serial, iclass 40, count 2 2006.169.08:15:35.25#ibcon#enter sib2, iclass 40, count 2 2006.169.08:15:35.25#ibcon#flushed, iclass 40, count 2 2006.169.08:15:35.26#ibcon#about to write, iclass 40, count 2 2006.169.08:15:35.26#ibcon#wrote, iclass 40, count 2 2006.169.08:15:35.26#ibcon#about to read 3, iclass 40, count 2 2006.169.08:15:35.28#ibcon#read 3, iclass 40, count 2 2006.169.08:15:35.28#ibcon#about to read 4, iclass 40, count 2 2006.169.08:15:35.28#ibcon#read 4, iclass 40, count 2 2006.169.08:15:35.28#ibcon#about to read 5, iclass 40, count 2 2006.169.08:15:35.28#ibcon#read 5, iclass 40, count 2 2006.169.08:15:35.28#ibcon#about to read 6, iclass 40, count 2 2006.169.08:15:35.28#ibcon#read 6, iclass 40, count 2 2006.169.08:15:35.28#ibcon#end of sib2, iclass 40, count 2 2006.169.08:15:35.28#ibcon#*mode == 0, iclass 40, count 2 2006.169.08:15:35.28#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.169.08:15:35.28#ibcon#[25=AT02-07\r\n] 2006.169.08:15:35.28#ibcon#*before write, iclass 40, count 2 2006.169.08:15:35.28#ibcon#enter sib2, iclass 40, count 2 2006.169.08:15:35.28#ibcon#flushed, iclass 40, count 2 2006.169.08:15:35.28#ibcon#about to write, iclass 40, count 2 2006.169.08:15:35.28#ibcon#wrote, iclass 40, count 2 2006.169.08:15:35.28#ibcon#about to read 3, iclass 40, count 2 2006.169.08:15:35.31#ibcon#read 3, iclass 40, count 2 2006.169.08:15:35.31#ibcon#about to read 4, iclass 40, count 2 2006.169.08:15:35.31#ibcon#read 4, iclass 40, count 2 2006.169.08:15:35.32#ibcon#about to read 5, iclass 40, count 2 2006.169.08:15:35.32#ibcon#read 5, iclass 40, count 2 2006.169.08:15:35.32#ibcon#about to read 6, iclass 40, count 2 2006.169.08:15:35.32#ibcon#read 6, iclass 40, count 2 2006.169.08:15:35.32#ibcon#end of sib2, iclass 40, count 2 2006.169.08:15:35.32#ibcon#*after write, iclass 40, count 2 2006.169.08:15:35.32#ibcon#*before return 0, iclass 40, count 2 2006.169.08:15:35.32#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.169.08:15:35.32#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.169.08:15:35.32#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.169.08:15:35.32#ibcon#ireg 7 cls_cnt 0 2006.169.08:15:35.32#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.169.08:15:35.43#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.169.08:15:35.43#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.169.08:15:35.43#ibcon#enter wrdev, iclass 40, count 0 2006.169.08:15:35.43#ibcon#first serial, iclass 40, count 0 2006.169.08:15:35.43#ibcon#enter sib2, iclass 40, count 0 2006.169.08:15:35.44#ibcon#flushed, iclass 40, count 0 2006.169.08:15:35.44#ibcon#about to write, iclass 40, count 0 2006.169.08:15:35.44#ibcon#wrote, iclass 40, count 0 2006.169.08:15:35.44#ibcon#about to read 3, iclass 40, count 0 2006.169.08:15:35.45#ibcon#read 3, iclass 40, count 0 2006.169.08:15:35.45#ibcon#about to read 4, iclass 40, count 0 2006.169.08:15:35.45#ibcon#read 4, iclass 40, count 0 2006.169.08:15:35.45#ibcon#about to read 5, iclass 40, count 0 2006.169.08:15:35.46#ibcon#read 5, iclass 40, count 0 2006.169.08:15:35.46#ibcon#about to read 6, iclass 40, count 0 2006.169.08:15:35.46#ibcon#read 6, iclass 40, count 0 2006.169.08:15:35.46#ibcon#end of sib2, iclass 40, count 0 2006.169.08:15:35.46#ibcon#*mode == 0, iclass 40, count 0 2006.169.08:15:35.46#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.169.08:15:35.46#ibcon#[25=USB\r\n] 2006.169.08:15:35.46#ibcon#*before write, iclass 40, count 0 2006.169.08:15:35.46#ibcon#enter sib2, iclass 40, count 0 2006.169.08:15:35.46#ibcon#flushed, iclass 40, count 0 2006.169.08:15:35.46#ibcon#about to write, iclass 40, count 0 2006.169.08:15:35.46#ibcon#wrote, iclass 40, count 0 2006.169.08:15:35.46#ibcon#about to read 3, iclass 40, count 0 2006.169.08:15:35.48#ibcon#read 3, iclass 40, count 0 2006.169.08:15:35.48#ibcon#about to read 4, iclass 40, count 0 2006.169.08:15:35.48#ibcon#read 4, iclass 40, count 0 2006.169.08:15:35.48#ibcon#about to read 5, iclass 40, count 0 2006.169.08:15:35.49#ibcon#read 5, iclass 40, count 0 2006.169.08:15:35.49#ibcon#about to read 6, iclass 40, count 0 2006.169.08:15:35.49#ibcon#read 6, iclass 40, count 0 2006.169.08:15:35.49#ibcon#end of sib2, iclass 40, count 0 2006.169.08:15:35.49#ibcon#*after write, iclass 40, count 0 2006.169.08:15:35.49#ibcon#*before return 0, iclass 40, count 0 2006.169.08:15:35.49#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.169.08:15:35.49#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.169.08:15:35.49#ibcon#about to clear, iclass 40 cls_cnt 0 2006.169.08:15:35.49#ibcon#cleared, iclass 40 cls_cnt 0 2006.169.08:15:35.49$vc4f8/valo=3,672.99 2006.169.08:15:35.49#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.169.08:15:35.49#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.169.08:15:35.49#ibcon#ireg 17 cls_cnt 0 2006.169.08:15:35.49#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:15:35.49#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:15:35.49#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:15:35.49#ibcon#enter wrdev, iclass 4, count 0 2006.169.08:15:35.49#ibcon#first serial, iclass 4, count 0 2006.169.08:15:35.49#ibcon#enter sib2, iclass 4, count 0 2006.169.08:15:35.49#ibcon#flushed, iclass 4, count 0 2006.169.08:15:35.49#ibcon#about to write, iclass 4, count 0 2006.169.08:15:35.49#ibcon#wrote, iclass 4, count 0 2006.169.08:15:35.49#ibcon#about to read 3, iclass 4, count 0 2006.169.08:15:35.51#ibcon#read 3, iclass 4, count 0 2006.169.08:15:35.51#ibcon#about to read 4, iclass 4, count 0 2006.169.08:15:35.51#ibcon#read 4, iclass 4, count 0 2006.169.08:15:35.51#ibcon#about to read 5, iclass 4, count 0 2006.169.08:15:35.51#ibcon#read 5, iclass 4, count 0 2006.169.08:15:35.51#ibcon#about to read 6, iclass 4, count 0 2006.169.08:15:35.51#ibcon#read 6, iclass 4, count 0 2006.169.08:15:35.51#ibcon#end of sib2, iclass 4, count 0 2006.169.08:15:35.51#ibcon#*mode == 0, iclass 4, count 0 2006.169.08:15:35.51#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.169.08:15:35.51#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.08:15:35.51#ibcon#*before write, iclass 4, count 0 2006.169.08:15:35.51#ibcon#enter sib2, iclass 4, count 0 2006.169.08:15:35.51#ibcon#flushed, iclass 4, count 0 2006.169.08:15:35.51#ibcon#about to write, iclass 4, count 0 2006.169.08:15:35.51#ibcon#wrote, iclass 4, count 0 2006.169.08:15:35.51#ibcon#about to read 3, iclass 4, count 0 2006.169.08:15:35.55#ibcon#read 3, iclass 4, count 0 2006.169.08:15:35.55#ibcon#about to read 4, iclass 4, count 0 2006.169.08:15:35.55#ibcon#read 4, iclass 4, count 0 2006.169.08:15:35.55#ibcon#about to read 5, iclass 4, count 0 2006.169.08:15:35.55#ibcon#read 5, iclass 4, count 0 2006.169.08:15:35.55#ibcon#about to read 6, iclass 4, count 0 2006.169.08:15:35.55#ibcon#read 6, iclass 4, count 0 2006.169.08:15:35.55#ibcon#end of sib2, iclass 4, count 0 2006.169.08:15:35.55#ibcon#*after write, iclass 4, count 0 2006.169.08:15:35.55#ibcon#*before return 0, iclass 4, count 0 2006.169.08:15:35.55#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:15:35.55#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:15:35.55#ibcon#about to clear, iclass 4 cls_cnt 0 2006.169.08:15:35.55#ibcon#cleared, iclass 4 cls_cnt 0 2006.169.08:15:35.55$vc4f8/va=3,6 2006.169.08:15:35.55#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.169.08:15:35.55#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.169.08:15:35.55#ibcon#ireg 11 cls_cnt 2 2006.169.08:15:35.55#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.169.08:15:35.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.169.08:15:35.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.169.08:15:35.60#ibcon#enter wrdev, iclass 6, count 2 2006.169.08:15:35.60#ibcon#first serial, iclass 6, count 2 2006.169.08:15:35.60#ibcon#enter sib2, iclass 6, count 2 2006.169.08:15:35.60#ibcon#flushed, iclass 6, count 2 2006.169.08:15:35.61#ibcon#about to write, iclass 6, count 2 2006.169.08:15:35.61#ibcon#wrote, iclass 6, count 2 2006.169.08:15:35.61#ibcon#about to read 3, iclass 6, count 2 2006.169.08:15:35.62#ibcon#read 3, iclass 6, count 2 2006.169.08:15:35.62#ibcon#about to read 4, iclass 6, count 2 2006.169.08:15:35.62#ibcon#read 4, iclass 6, count 2 2006.169.08:15:35.62#ibcon#about to read 5, iclass 6, count 2 2006.169.08:15:35.63#ibcon#read 5, iclass 6, count 2 2006.169.08:15:35.63#ibcon#about to read 6, iclass 6, count 2 2006.169.08:15:35.63#ibcon#read 6, iclass 6, count 2 2006.169.08:15:35.63#ibcon#end of sib2, iclass 6, count 2 2006.169.08:15:35.63#ibcon#*mode == 0, iclass 6, count 2 2006.169.08:15:35.63#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.169.08:15:35.63#ibcon#[25=AT03-06\r\n] 2006.169.08:15:35.63#ibcon#*before write, iclass 6, count 2 2006.169.08:15:35.63#ibcon#enter sib2, iclass 6, count 2 2006.169.08:15:35.63#ibcon#flushed, iclass 6, count 2 2006.169.08:15:35.63#ibcon#about to write, iclass 6, count 2 2006.169.08:15:35.63#ibcon#wrote, iclass 6, count 2 2006.169.08:15:35.63#ibcon#about to read 3, iclass 6, count 2 2006.169.08:15:35.65#ibcon#read 3, iclass 6, count 2 2006.169.08:15:35.65#ibcon#about to read 4, iclass 6, count 2 2006.169.08:15:35.65#ibcon#read 4, iclass 6, count 2 2006.169.08:15:35.65#ibcon#about to read 5, iclass 6, count 2 2006.169.08:15:35.66#ibcon#read 5, iclass 6, count 2 2006.169.08:15:35.66#ibcon#about to read 6, iclass 6, count 2 2006.169.08:15:35.66#ibcon#read 6, iclass 6, count 2 2006.169.08:15:35.66#ibcon#end of sib2, iclass 6, count 2 2006.169.08:15:35.66#ibcon#*after write, iclass 6, count 2 2006.169.08:15:35.66#ibcon#*before return 0, iclass 6, count 2 2006.169.08:15:35.66#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.169.08:15:35.66#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.169.08:15:35.66#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.169.08:15:35.66#ibcon#ireg 7 cls_cnt 0 2006.169.08:15:35.66#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.169.08:15:35.77#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.169.08:15:35.77#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.169.08:15:35.77#ibcon#enter wrdev, iclass 6, count 0 2006.169.08:15:35.77#ibcon#first serial, iclass 6, count 0 2006.169.08:15:35.77#ibcon#enter sib2, iclass 6, count 0 2006.169.08:15:35.77#ibcon#flushed, iclass 6, count 0 2006.169.08:15:35.78#ibcon#about to write, iclass 6, count 0 2006.169.08:15:35.78#ibcon#wrote, iclass 6, count 0 2006.169.08:15:35.78#ibcon#about to read 3, iclass 6, count 0 2006.169.08:15:35.80#ibcon#read 3, iclass 6, count 0 2006.169.08:15:35.80#ibcon#about to read 4, iclass 6, count 0 2006.169.08:15:35.80#ibcon#read 4, iclass 6, count 0 2006.169.08:15:35.80#ibcon#about to read 5, iclass 6, count 0 2006.169.08:15:35.80#ibcon#read 5, iclass 6, count 0 2006.169.08:15:35.80#ibcon#about to read 6, iclass 6, count 0 2006.169.08:15:35.80#ibcon#read 6, iclass 6, count 0 2006.169.08:15:35.80#ibcon#end of sib2, iclass 6, count 0 2006.169.08:15:35.80#ibcon#*mode == 0, iclass 6, count 0 2006.169.08:15:35.80#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.169.08:15:35.80#ibcon#[25=USB\r\n] 2006.169.08:15:35.80#ibcon#*before write, iclass 6, count 0 2006.169.08:15:35.80#ibcon#enter sib2, iclass 6, count 0 2006.169.08:15:35.80#ibcon#flushed, iclass 6, count 0 2006.169.08:15:35.80#ibcon#about to write, iclass 6, count 0 2006.169.08:15:35.80#ibcon#wrote, iclass 6, count 0 2006.169.08:15:35.80#ibcon#about to read 3, iclass 6, count 0 2006.169.08:15:35.82#ibcon#read 3, iclass 6, count 0 2006.169.08:15:35.82#ibcon#about to read 4, iclass 6, count 0 2006.169.08:15:35.82#ibcon#read 4, iclass 6, count 0 2006.169.08:15:35.82#ibcon#about to read 5, iclass 6, count 0 2006.169.08:15:35.83#ibcon#read 5, iclass 6, count 0 2006.169.08:15:35.83#ibcon#about to read 6, iclass 6, count 0 2006.169.08:15:35.83#ibcon#read 6, iclass 6, count 0 2006.169.08:15:35.83#ibcon#end of sib2, iclass 6, count 0 2006.169.08:15:35.83#ibcon#*after write, iclass 6, count 0 2006.169.08:15:35.83#ibcon#*before return 0, iclass 6, count 0 2006.169.08:15:35.83#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.169.08:15:35.83#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.169.08:15:35.83#ibcon#about to clear, iclass 6 cls_cnt 0 2006.169.08:15:35.83#ibcon#cleared, iclass 6 cls_cnt 0 2006.169.08:15:35.83$vc4f8/valo=4,832.99 2006.169.08:15:35.83#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.169.08:15:35.83#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.169.08:15:35.83#ibcon#ireg 17 cls_cnt 0 2006.169.08:15:35.83#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.169.08:15:35.83#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.169.08:15:35.83#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.169.08:15:35.83#ibcon#enter wrdev, iclass 10, count 0 2006.169.08:15:35.83#ibcon#first serial, iclass 10, count 0 2006.169.08:15:35.83#ibcon#enter sib2, iclass 10, count 0 2006.169.08:15:35.83#ibcon#flushed, iclass 10, count 0 2006.169.08:15:35.83#ibcon#about to write, iclass 10, count 0 2006.169.08:15:35.83#ibcon#wrote, iclass 10, count 0 2006.169.08:15:35.83#ibcon#about to read 3, iclass 10, count 0 2006.169.08:15:35.84#ibcon#read 3, iclass 10, count 0 2006.169.08:15:35.84#ibcon#about to read 4, iclass 10, count 0 2006.169.08:15:35.84#ibcon#read 4, iclass 10, count 0 2006.169.08:15:35.84#ibcon#about to read 5, iclass 10, count 0 2006.169.08:15:35.85#ibcon#read 5, iclass 10, count 0 2006.169.08:15:35.85#ibcon#about to read 6, iclass 10, count 0 2006.169.08:15:35.85#ibcon#read 6, iclass 10, count 0 2006.169.08:15:35.85#ibcon#end of sib2, iclass 10, count 0 2006.169.08:15:35.85#ibcon#*mode == 0, iclass 10, count 0 2006.169.08:15:35.85#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.169.08:15:35.85#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.08:15:35.85#ibcon#*before write, iclass 10, count 0 2006.169.08:15:35.85#ibcon#enter sib2, iclass 10, count 0 2006.169.08:15:35.85#ibcon#flushed, iclass 10, count 0 2006.169.08:15:35.85#ibcon#about to write, iclass 10, count 0 2006.169.08:15:35.85#ibcon#wrote, iclass 10, count 0 2006.169.08:15:35.85#ibcon#about to read 3, iclass 10, count 0 2006.169.08:15:35.88#ibcon#read 3, iclass 10, count 0 2006.169.08:15:35.88#ibcon#about to read 4, iclass 10, count 0 2006.169.08:15:35.88#ibcon#read 4, iclass 10, count 0 2006.169.08:15:35.88#ibcon#about to read 5, iclass 10, count 0 2006.169.08:15:35.88#ibcon#read 5, iclass 10, count 0 2006.169.08:15:35.88#ibcon#about to read 6, iclass 10, count 0 2006.169.08:15:35.89#ibcon#read 6, iclass 10, count 0 2006.169.08:15:35.89#ibcon#end of sib2, iclass 10, count 0 2006.169.08:15:35.89#ibcon#*after write, iclass 10, count 0 2006.169.08:15:35.89#ibcon#*before return 0, iclass 10, count 0 2006.169.08:15:35.89#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.169.08:15:35.89#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.169.08:15:35.89#ibcon#about to clear, iclass 10 cls_cnt 0 2006.169.08:15:35.89#ibcon#cleared, iclass 10 cls_cnt 0 2006.169.08:15:35.89$vc4f8/va=4,7 2006.169.08:15:35.89#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.169.08:15:35.89#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.169.08:15:35.89#ibcon#ireg 11 cls_cnt 2 2006.169.08:15:35.89#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.169.08:15:35.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.169.08:15:35.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.169.08:15:35.94#ibcon#enter wrdev, iclass 12, count 2 2006.169.08:15:35.94#ibcon#first serial, iclass 12, count 2 2006.169.08:15:35.94#ibcon#enter sib2, iclass 12, count 2 2006.169.08:15:35.95#ibcon#flushed, iclass 12, count 2 2006.169.08:15:35.95#ibcon#about to write, iclass 12, count 2 2006.169.08:15:35.95#ibcon#wrote, iclass 12, count 2 2006.169.08:15:35.95#ibcon#about to read 3, iclass 12, count 2 2006.169.08:15:35.96#ibcon#read 3, iclass 12, count 2 2006.169.08:15:35.97#ibcon#about to read 4, iclass 12, count 2 2006.169.08:15:35.97#ibcon#read 4, iclass 12, count 2 2006.169.08:15:35.97#ibcon#about to read 5, iclass 12, count 2 2006.169.08:15:35.97#ibcon#read 5, iclass 12, count 2 2006.169.08:15:35.97#ibcon#about to read 6, iclass 12, count 2 2006.169.08:15:35.97#ibcon#read 6, iclass 12, count 2 2006.169.08:15:35.97#ibcon#end of sib2, iclass 12, count 2 2006.169.08:15:35.97#ibcon#*mode == 0, iclass 12, count 2 2006.169.08:15:35.97#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.169.08:15:35.97#ibcon#[25=AT04-07\r\n] 2006.169.08:15:35.97#ibcon#*before write, iclass 12, count 2 2006.169.08:15:35.97#ibcon#enter sib2, iclass 12, count 2 2006.169.08:15:35.97#ibcon#flushed, iclass 12, count 2 2006.169.08:15:35.97#ibcon#about to write, iclass 12, count 2 2006.169.08:15:35.97#ibcon#wrote, iclass 12, count 2 2006.169.08:15:35.97#ibcon#about to read 3, iclass 12, count 2 2006.169.08:15:35.99#ibcon#read 3, iclass 12, count 2 2006.169.08:15:35.99#ibcon#about to read 4, iclass 12, count 2 2006.169.08:15:35.99#ibcon#read 4, iclass 12, count 2 2006.169.08:15:35.99#ibcon#about to read 5, iclass 12, count 2 2006.169.08:15:35.99#ibcon#read 5, iclass 12, count 2 2006.169.08:15:36.00#ibcon#about to read 6, iclass 12, count 2 2006.169.08:15:36.00#ibcon#read 6, iclass 12, count 2 2006.169.08:15:36.00#ibcon#end of sib2, iclass 12, count 2 2006.169.08:15:36.00#ibcon#*after write, iclass 12, count 2 2006.169.08:15:36.00#ibcon#*before return 0, iclass 12, count 2 2006.169.08:15:36.00#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.169.08:15:36.00#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.169.08:15:36.00#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.169.08:15:36.00#ibcon#ireg 7 cls_cnt 0 2006.169.08:15:36.00#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.169.08:15:36.11#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.169.08:15:36.11#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.169.08:15:36.11#ibcon#enter wrdev, iclass 12, count 0 2006.169.08:15:36.11#ibcon#first serial, iclass 12, count 0 2006.169.08:15:36.11#ibcon#enter sib2, iclass 12, count 0 2006.169.08:15:36.11#ibcon#flushed, iclass 12, count 0 2006.169.08:15:36.12#ibcon#about to write, iclass 12, count 0 2006.169.08:15:36.12#ibcon#wrote, iclass 12, count 0 2006.169.08:15:36.12#ibcon#about to read 3, iclass 12, count 0 2006.169.08:15:36.13#ibcon#read 3, iclass 12, count 0 2006.169.08:15:36.13#ibcon#about to read 4, iclass 12, count 0 2006.169.08:15:36.13#ibcon#read 4, iclass 12, count 0 2006.169.08:15:36.13#ibcon#about to read 5, iclass 12, count 0 2006.169.08:15:36.14#ibcon#read 5, iclass 12, count 0 2006.169.08:15:36.14#ibcon#about to read 6, iclass 12, count 0 2006.169.08:15:36.14#ibcon#read 6, iclass 12, count 0 2006.169.08:15:36.14#ibcon#end of sib2, iclass 12, count 0 2006.169.08:15:36.14#ibcon#*mode == 0, iclass 12, count 0 2006.169.08:15:36.14#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.169.08:15:36.14#ibcon#[25=USB\r\n] 2006.169.08:15:36.14#ibcon#*before write, iclass 12, count 0 2006.169.08:15:36.14#ibcon#enter sib2, iclass 12, count 0 2006.169.08:15:36.14#ibcon#flushed, iclass 12, count 0 2006.169.08:15:36.14#ibcon#about to write, iclass 12, count 0 2006.169.08:15:36.14#ibcon#wrote, iclass 12, count 0 2006.169.08:15:36.14#ibcon#about to read 3, iclass 12, count 0 2006.169.08:15:36.16#ibcon#read 3, iclass 12, count 0 2006.169.08:15:36.16#ibcon#about to read 4, iclass 12, count 0 2006.169.08:15:36.16#ibcon#read 4, iclass 12, count 0 2006.169.08:15:36.16#ibcon#about to read 5, iclass 12, count 0 2006.169.08:15:36.17#ibcon#read 5, iclass 12, count 0 2006.169.08:15:36.17#ibcon#about to read 6, iclass 12, count 0 2006.169.08:15:36.17#ibcon#read 6, iclass 12, count 0 2006.169.08:15:36.17#ibcon#end of sib2, iclass 12, count 0 2006.169.08:15:36.17#ibcon#*after write, iclass 12, count 0 2006.169.08:15:36.17#ibcon#*before return 0, iclass 12, count 0 2006.169.08:15:36.17#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.169.08:15:36.17#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.169.08:15:36.17#ibcon#about to clear, iclass 12 cls_cnt 0 2006.169.08:15:36.17#ibcon#cleared, iclass 12 cls_cnt 0 2006.169.08:15:36.17$vc4f8/valo=5,652.99 2006.169.08:15:36.17#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.169.08:15:36.17#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.169.08:15:36.17#ibcon#ireg 17 cls_cnt 0 2006.169.08:15:36.17#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:15:36.17#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:15:36.17#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:15:36.17#ibcon#enter wrdev, iclass 14, count 0 2006.169.08:15:36.17#ibcon#first serial, iclass 14, count 0 2006.169.08:15:36.17#ibcon#enter sib2, iclass 14, count 0 2006.169.08:15:36.17#ibcon#flushed, iclass 14, count 0 2006.169.08:15:36.17#ibcon#about to write, iclass 14, count 0 2006.169.08:15:36.17#ibcon#wrote, iclass 14, count 0 2006.169.08:15:36.17#ibcon#about to read 3, iclass 14, count 0 2006.169.08:15:36.18#ibcon#read 3, iclass 14, count 0 2006.169.08:15:36.18#ibcon#about to read 4, iclass 14, count 0 2006.169.08:15:36.18#ibcon#read 4, iclass 14, count 0 2006.169.08:15:36.18#ibcon#about to read 5, iclass 14, count 0 2006.169.08:15:36.18#ibcon#read 5, iclass 14, count 0 2006.169.08:15:36.19#ibcon#about to read 6, iclass 14, count 0 2006.169.08:15:36.19#ibcon#read 6, iclass 14, count 0 2006.169.08:15:36.19#ibcon#end of sib2, iclass 14, count 0 2006.169.08:15:36.19#ibcon#*mode == 0, iclass 14, count 0 2006.169.08:15:36.19#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.169.08:15:36.19#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.08:15:36.19#ibcon#*before write, iclass 14, count 0 2006.169.08:15:36.19#ibcon#enter sib2, iclass 14, count 0 2006.169.08:15:36.19#ibcon#flushed, iclass 14, count 0 2006.169.08:15:36.19#ibcon#about to write, iclass 14, count 0 2006.169.08:15:36.19#ibcon#wrote, iclass 14, count 0 2006.169.08:15:36.19#ibcon#about to read 3, iclass 14, count 0 2006.169.08:15:36.22#ibcon#read 3, iclass 14, count 0 2006.169.08:15:36.22#ibcon#about to read 4, iclass 14, count 0 2006.169.08:15:36.22#ibcon#read 4, iclass 14, count 0 2006.169.08:15:36.22#ibcon#about to read 5, iclass 14, count 0 2006.169.08:15:36.22#ibcon#read 5, iclass 14, count 0 2006.169.08:15:36.23#ibcon#about to read 6, iclass 14, count 0 2006.169.08:15:36.23#ibcon#read 6, iclass 14, count 0 2006.169.08:15:36.23#ibcon#end of sib2, iclass 14, count 0 2006.169.08:15:36.23#ibcon#*after write, iclass 14, count 0 2006.169.08:15:36.23#ibcon#*before return 0, iclass 14, count 0 2006.169.08:15:36.23#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:15:36.23#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:15:36.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.169.08:15:36.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.169.08:15:36.23$vc4f8/va=5,7 2006.169.08:15:36.23#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.169.08:15:36.23#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.169.08:15:36.23#ibcon#ireg 11 cls_cnt 2 2006.169.08:15:36.23#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.169.08:15:36.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.169.08:15:36.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.169.08:15:36.28#ibcon#enter wrdev, iclass 16, count 2 2006.169.08:15:36.28#ibcon#first serial, iclass 16, count 2 2006.169.08:15:36.28#ibcon#enter sib2, iclass 16, count 2 2006.169.08:15:36.29#ibcon#flushed, iclass 16, count 2 2006.169.08:15:36.29#ibcon#about to write, iclass 16, count 2 2006.169.08:15:36.29#ibcon#wrote, iclass 16, count 2 2006.169.08:15:36.29#ibcon#about to read 3, iclass 16, count 2 2006.169.08:15:36.30#ibcon#read 3, iclass 16, count 2 2006.169.08:15:36.30#ibcon#about to read 4, iclass 16, count 2 2006.169.08:15:36.31#ibcon#read 4, iclass 16, count 2 2006.169.08:15:36.31#ibcon#about to read 5, iclass 16, count 2 2006.169.08:15:36.31#ibcon#read 5, iclass 16, count 2 2006.169.08:15:36.31#ibcon#about to read 6, iclass 16, count 2 2006.169.08:15:36.31#ibcon#read 6, iclass 16, count 2 2006.169.08:15:36.31#ibcon#end of sib2, iclass 16, count 2 2006.169.08:15:36.31#ibcon#*mode == 0, iclass 16, count 2 2006.169.08:15:36.31#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.169.08:15:36.31#ibcon#[25=AT05-07\r\n] 2006.169.08:15:36.31#ibcon#*before write, iclass 16, count 2 2006.169.08:15:36.31#ibcon#enter sib2, iclass 16, count 2 2006.169.08:15:36.31#ibcon#flushed, iclass 16, count 2 2006.169.08:15:36.31#ibcon#about to write, iclass 16, count 2 2006.169.08:15:36.31#ibcon#wrote, iclass 16, count 2 2006.169.08:15:36.31#ibcon#about to read 3, iclass 16, count 2 2006.169.08:15:36.33#ibcon#read 3, iclass 16, count 2 2006.169.08:15:36.33#ibcon#about to read 4, iclass 16, count 2 2006.169.08:15:36.33#ibcon#read 4, iclass 16, count 2 2006.169.08:15:36.33#ibcon#about to read 5, iclass 16, count 2 2006.169.08:15:36.33#ibcon#read 5, iclass 16, count 2 2006.169.08:15:36.34#ibcon#about to read 6, iclass 16, count 2 2006.169.08:15:36.34#ibcon#read 6, iclass 16, count 2 2006.169.08:15:36.34#ibcon#end of sib2, iclass 16, count 2 2006.169.08:15:36.34#ibcon#*after write, iclass 16, count 2 2006.169.08:15:36.34#ibcon#*before return 0, iclass 16, count 2 2006.169.08:15:36.34#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.169.08:15:36.34#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.169.08:15:36.34#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.169.08:15:36.34#ibcon#ireg 7 cls_cnt 0 2006.169.08:15:36.34#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.169.08:15:36.45#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.169.08:15:36.45#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.169.08:15:36.45#ibcon#enter wrdev, iclass 16, count 0 2006.169.08:15:36.45#ibcon#first serial, iclass 16, count 0 2006.169.08:15:36.45#ibcon#enter sib2, iclass 16, count 0 2006.169.08:15:36.45#ibcon#flushed, iclass 16, count 0 2006.169.08:15:36.46#ibcon#about to write, iclass 16, count 0 2006.169.08:15:36.46#ibcon#wrote, iclass 16, count 0 2006.169.08:15:36.46#ibcon#about to read 3, iclass 16, count 0 2006.169.08:15:36.47#ibcon#read 3, iclass 16, count 0 2006.169.08:15:36.47#ibcon#about to read 4, iclass 16, count 0 2006.169.08:15:36.47#ibcon#read 4, iclass 16, count 0 2006.169.08:15:36.47#ibcon#about to read 5, iclass 16, count 0 2006.169.08:15:36.47#ibcon#read 5, iclass 16, count 0 2006.169.08:15:36.48#ibcon#about to read 6, iclass 16, count 0 2006.169.08:15:36.48#ibcon#read 6, iclass 16, count 0 2006.169.08:15:36.48#ibcon#end of sib2, iclass 16, count 0 2006.169.08:15:36.48#ibcon#*mode == 0, iclass 16, count 0 2006.169.08:15:36.48#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.169.08:15:36.48#ibcon#[25=USB\r\n] 2006.169.08:15:36.48#ibcon#*before write, iclass 16, count 0 2006.169.08:15:36.48#ibcon#enter sib2, iclass 16, count 0 2006.169.08:15:36.48#ibcon#flushed, iclass 16, count 0 2006.169.08:15:36.48#ibcon#about to write, iclass 16, count 0 2006.169.08:15:36.48#ibcon#wrote, iclass 16, count 0 2006.169.08:15:36.48#ibcon#about to read 3, iclass 16, count 0 2006.169.08:15:36.50#ibcon#read 3, iclass 16, count 0 2006.169.08:15:36.50#ibcon#about to read 4, iclass 16, count 0 2006.169.08:15:36.50#ibcon#read 4, iclass 16, count 0 2006.169.08:15:36.50#ibcon#about to read 5, iclass 16, count 0 2006.169.08:15:36.51#ibcon#read 5, iclass 16, count 0 2006.169.08:15:36.51#ibcon#about to read 6, iclass 16, count 0 2006.169.08:15:36.51#ibcon#read 6, iclass 16, count 0 2006.169.08:15:36.51#ibcon#end of sib2, iclass 16, count 0 2006.169.08:15:36.51#ibcon#*after write, iclass 16, count 0 2006.169.08:15:36.51#ibcon#*before return 0, iclass 16, count 0 2006.169.08:15:36.51#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.169.08:15:36.51#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.169.08:15:36.51#ibcon#about to clear, iclass 16 cls_cnt 0 2006.169.08:15:36.51#ibcon#cleared, iclass 16 cls_cnt 0 2006.169.08:15:36.51$vc4f8/valo=6,772.99 2006.169.08:15:36.51#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.169.08:15:36.51#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.169.08:15:36.51#ibcon#ireg 17 cls_cnt 0 2006.169.08:15:36.51#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:15:36.51#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:15:36.51#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:15:36.51#ibcon#enter wrdev, iclass 18, count 0 2006.169.08:15:36.51#ibcon#first serial, iclass 18, count 0 2006.169.08:15:36.51#ibcon#enter sib2, iclass 18, count 0 2006.169.08:15:36.51#ibcon#flushed, iclass 18, count 0 2006.169.08:15:36.51#ibcon#about to write, iclass 18, count 0 2006.169.08:15:36.51#ibcon#wrote, iclass 18, count 0 2006.169.08:15:36.51#ibcon#about to read 3, iclass 18, count 0 2006.169.08:15:36.52#ibcon#read 3, iclass 18, count 0 2006.169.08:15:36.52#ibcon#about to read 4, iclass 18, count 0 2006.169.08:15:36.52#ibcon#read 4, iclass 18, count 0 2006.169.08:15:36.52#ibcon#about to read 5, iclass 18, count 0 2006.169.08:15:36.53#ibcon#read 5, iclass 18, count 0 2006.169.08:15:36.53#ibcon#about to read 6, iclass 18, count 0 2006.169.08:15:36.53#ibcon#read 6, iclass 18, count 0 2006.169.08:15:36.53#ibcon#end of sib2, iclass 18, count 0 2006.169.08:15:36.53#ibcon#*mode == 0, iclass 18, count 0 2006.169.08:15:36.53#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.169.08:15:36.53#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.08:15:36.53#ibcon#*before write, iclass 18, count 0 2006.169.08:15:36.53#ibcon#enter sib2, iclass 18, count 0 2006.169.08:15:36.53#ibcon#flushed, iclass 18, count 0 2006.169.08:15:36.53#ibcon#about to write, iclass 18, count 0 2006.169.08:15:36.53#ibcon#wrote, iclass 18, count 0 2006.169.08:15:36.53#ibcon#about to read 3, iclass 18, count 0 2006.169.08:15:36.56#ibcon#read 3, iclass 18, count 0 2006.169.08:15:36.56#ibcon#about to read 4, iclass 18, count 0 2006.169.08:15:36.56#ibcon#read 4, iclass 18, count 0 2006.169.08:15:36.56#ibcon#about to read 5, iclass 18, count 0 2006.169.08:15:36.57#ibcon#read 5, iclass 18, count 0 2006.169.08:15:36.57#ibcon#about to read 6, iclass 18, count 0 2006.169.08:15:36.57#ibcon#read 6, iclass 18, count 0 2006.169.08:15:36.57#ibcon#end of sib2, iclass 18, count 0 2006.169.08:15:36.57#ibcon#*after write, iclass 18, count 0 2006.169.08:15:36.57#ibcon#*before return 0, iclass 18, count 0 2006.169.08:15:36.57#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:15:36.57#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:15:36.57#ibcon#about to clear, iclass 18 cls_cnt 0 2006.169.08:15:36.57#ibcon#cleared, iclass 18 cls_cnt 0 2006.169.08:15:36.57$vc4f8/va=6,6 2006.169.08:15:36.57#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.169.08:15:36.57#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.169.08:15:36.57#ibcon#ireg 11 cls_cnt 2 2006.169.08:15:36.57#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.169.08:15:36.62#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.169.08:15:36.62#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.169.08:15:36.62#ibcon#enter wrdev, iclass 20, count 2 2006.169.08:15:36.62#ibcon#first serial, iclass 20, count 2 2006.169.08:15:36.62#ibcon#enter sib2, iclass 20, count 2 2006.169.08:15:36.62#ibcon#flushed, iclass 20, count 2 2006.169.08:15:36.62#ibcon#about to write, iclass 20, count 2 2006.169.08:15:36.63#ibcon#wrote, iclass 20, count 2 2006.169.08:15:36.63#ibcon#about to read 3, iclass 20, count 2 2006.169.08:15:36.64#ibcon#read 3, iclass 20, count 2 2006.169.08:15:36.64#ibcon#about to read 4, iclass 20, count 2 2006.169.08:15:36.65#ibcon#read 4, iclass 20, count 2 2006.169.08:15:36.65#ibcon#about to read 5, iclass 20, count 2 2006.169.08:15:36.65#ibcon#read 5, iclass 20, count 2 2006.169.08:15:36.65#ibcon#about to read 6, iclass 20, count 2 2006.169.08:15:36.65#ibcon#read 6, iclass 20, count 2 2006.169.08:15:36.65#ibcon#end of sib2, iclass 20, count 2 2006.169.08:15:36.65#ibcon#*mode == 0, iclass 20, count 2 2006.169.08:15:36.65#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.169.08:15:36.65#ibcon#[25=AT06-06\r\n] 2006.169.08:15:36.65#ibcon#*before write, iclass 20, count 2 2006.169.08:15:36.65#ibcon#enter sib2, iclass 20, count 2 2006.169.08:15:36.65#ibcon#flushed, iclass 20, count 2 2006.169.08:15:36.65#ibcon#about to write, iclass 20, count 2 2006.169.08:15:36.65#ibcon#wrote, iclass 20, count 2 2006.169.08:15:36.65#ibcon#about to read 3, iclass 20, count 2 2006.169.08:15:36.67#ibcon#read 3, iclass 20, count 2 2006.169.08:15:36.67#ibcon#about to read 4, iclass 20, count 2 2006.169.08:15:36.67#ibcon#read 4, iclass 20, count 2 2006.169.08:15:36.67#ibcon#about to read 5, iclass 20, count 2 2006.169.08:15:36.68#ibcon#read 5, iclass 20, count 2 2006.169.08:15:36.68#ibcon#about to read 6, iclass 20, count 2 2006.169.08:15:36.68#ibcon#read 6, iclass 20, count 2 2006.169.08:15:36.68#ibcon#end of sib2, iclass 20, count 2 2006.169.08:15:36.68#ibcon#*after write, iclass 20, count 2 2006.169.08:15:36.68#ibcon#*before return 0, iclass 20, count 2 2006.169.08:15:36.68#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.169.08:15:36.68#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.169.08:15:36.68#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.169.08:15:36.68#ibcon#ireg 7 cls_cnt 0 2006.169.08:15:36.68#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.169.08:15:36.79#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.169.08:15:36.79#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.169.08:15:36.79#ibcon#enter wrdev, iclass 20, count 0 2006.169.08:15:36.79#ibcon#first serial, iclass 20, count 0 2006.169.08:15:36.79#ibcon#enter sib2, iclass 20, count 0 2006.169.08:15:36.79#ibcon#flushed, iclass 20, count 0 2006.169.08:15:36.79#ibcon#about to write, iclass 20, count 0 2006.169.08:15:36.80#ibcon#wrote, iclass 20, count 0 2006.169.08:15:36.80#ibcon#about to read 3, iclass 20, count 0 2006.169.08:15:36.81#ibcon#read 3, iclass 20, count 0 2006.169.08:15:36.81#ibcon#about to read 4, iclass 20, count 0 2006.169.08:15:36.81#ibcon#read 4, iclass 20, count 0 2006.169.08:15:36.81#ibcon#about to read 5, iclass 20, count 0 2006.169.08:15:36.82#ibcon#read 5, iclass 20, count 0 2006.169.08:15:36.82#ibcon#about to read 6, iclass 20, count 0 2006.169.08:15:36.82#ibcon#read 6, iclass 20, count 0 2006.169.08:15:36.82#ibcon#end of sib2, iclass 20, count 0 2006.169.08:15:36.82#ibcon#*mode == 0, iclass 20, count 0 2006.169.08:15:36.82#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.169.08:15:36.82#ibcon#[25=USB\r\n] 2006.169.08:15:36.82#ibcon#*before write, iclass 20, count 0 2006.169.08:15:36.82#ibcon#enter sib2, iclass 20, count 0 2006.169.08:15:36.82#ibcon#flushed, iclass 20, count 0 2006.169.08:15:36.82#ibcon#about to write, iclass 20, count 0 2006.169.08:15:36.82#ibcon#wrote, iclass 20, count 0 2006.169.08:15:36.82#ibcon#about to read 3, iclass 20, count 0 2006.169.08:15:36.84#ibcon#read 3, iclass 20, count 0 2006.169.08:15:36.84#ibcon#about to read 4, iclass 20, count 0 2006.169.08:15:36.84#ibcon#read 4, iclass 20, count 0 2006.169.08:15:36.84#ibcon#about to read 5, iclass 20, count 0 2006.169.08:15:36.84#ibcon#read 5, iclass 20, count 0 2006.169.08:15:36.85#ibcon#about to read 6, iclass 20, count 0 2006.169.08:15:36.85#ibcon#read 6, iclass 20, count 0 2006.169.08:15:36.85#ibcon#end of sib2, iclass 20, count 0 2006.169.08:15:36.85#ibcon#*after write, iclass 20, count 0 2006.169.08:15:36.85#ibcon#*before return 0, iclass 20, count 0 2006.169.08:15:36.85#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.169.08:15:36.85#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.169.08:15:36.85#ibcon#about to clear, iclass 20 cls_cnt 0 2006.169.08:15:36.85#ibcon#cleared, iclass 20 cls_cnt 0 2006.169.08:15:36.85$vc4f8/valo=7,832.99 2006.169.08:15:36.85#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.169.08:15:36.85#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.169.08:15:36.85#ibcon#ireg 17 cls_cnt 0 2006.169.08:15:36.85#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.169.08:15:36.85#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.169.08:15:36.85#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.169.08:15:36.85#ibcon#enter wrdev, iclass 22, count 0 2006.169.08:15:36.85#ibcon#first serial, iclass 22, count 0 2006.169.08:15:36.85#ibcon#enter sib2, iclass 22, count 0 2006.169.08:15:36.85#ibcon#flushed, iclass 22, count 0 2006.169.08:15:36.85#ibcon#about to write, iclass 22, count 0 2006.169.08:15:36.85#ibcon#wrote, iclass 22, count 0 2006.169.08:15:36.85#ibcon#about to read 3, iclass 22, count 0 2006.169.08:15:36.86#ibcon#read 3, iclass 22, count 0 2006.169.08:15:36.86#ibcon#about to read 4, iclass 22, count 0 2006.169.08:15:36.86#ibcon#read 4, iclass 22, count 0 2006.169.08:15:36.86#ibcon#about to read 5, iclass 22, count 0 2006.169.08:15:36.86#ibcon#read 5, iclass 22, count 0 2006.169.08:15:36.87#ibcon#about to read 6, iclass 22, count 0 2006.169.08:15:36.87#ibcon#read 6, iclass 22, count 0 2006.169.08:15:36.87#ibcon#end of sib2, iclass 22, count 0 2006.169.08:15:36.87#ibcon#*mode == 0, iclass 22, count 0 2006.169.08:15:36.87#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.169.08:15:36.87#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.08:15:36.87#ibcon#*before write, iclass 22, count 0 2006.169.08:15:36.87#ibcon#enter sib2, iclass 22, count 0 2006.169.08:15:36.87#ibcon#flushed, iclass 22, count 0 2006.169.08:15:36.87#ibcon#about to write, iclass 22, count 0 2006.169.08:15:36.87#ibcon#wrote, iclass 22, count 0 2006.169.08:15:36.87#ibcon#about to read 3, iclass 22, count 0 2006.169.08:15:36.90#ibcon#read 3, iclass 22, count 0 2006.169.08:15:36.90#ibcon#about to read 4, iclass 22, count 0 2006.169.08:15:36.90#ibcon#read 4, iclass 22, count 0 2006.169.08:15:36.90#ibcon#about to read 5, iclass 22, count 0 2006.169.08:15:36.90#ibcon#read 5, iclass 22, count 0 2006.169.08:15:36.90#ibcon#about to read 6, iclass 22, count 0 2006.169.08:15:36.91#ibcon#read 6, iclass 22, count 0 2006.169.08:15:36.91#ibcon#end of sib2, iclass 22, count 0 2006.169.08:15:36.91#ibcon#*after write, iclass 22, count 0 2006.169.08:15:36.91#ibcon#*before return 0, iclass 22, count 0 2006.169.08:15:36.91#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.169.08:15:36.91#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.169.08:15:36.91#ibcon#about to clear, iclass 22 cls_cnt 0 2006.169.08:15:36.91#ibcon#cleared, iclass 22 cls_cnt 0 2006.169.08:15:36.91$vc4f8/va=7,6 2006.169.08:15:36.91#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.169.08:15:36.91#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.169.08:15:36.91#ibcon#ireg 11 cls_cnt 2 2006.169.08:15:36.91#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.169.08:15:36.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.169.08:15:36.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.169.08:15:36.97#ibcon#enter wrdev, iclass 24, count 2 2006.169.08:15:36.97#ibcon#first serial, iclass 24, count 2 2006.169.08:15:36.97#ibcon#enter sib2, iclass 24, count 2 2006.169.08:15:36.97#ibcon#flushed, iclass 24, count 2 2006.169.08:15:36.97#ibcon#about to write, iclass 24, count 2 2006.169.08:15:36.97#ibcon#wrote, iclass 24, count 2 2006.169.08:15:36.97#ibcon#about to read 3, iclass 24, count 2 2006.169.08:15:36.98#ibcon#read 3, iclass 24, count 2 2006.169.08:15:36.99#ibcon#about to read 4, iclass 24, count 2 2006.169.08:15:36.99#ibcon#read 4, iclass 24, count 2 2006.169.08:15:36.99#ibcon#about to read 5, iclass 24, count 2 2006.169.08:15:36.99#ibcon#read 5, iclass 24, count 2 2006.169.08:15:36.99#ibcon#about to read 6, iclass 24, count 2 2006.169.08:15:36.99#ibcon#read 6, iclass 24, count 2 2006.169.08:15:36.99#ibcon#end of sib2, iclass 24, count 2 2006.169.08:15:36.99#ibcon#*mode == 0, iclass 24, count 2 2006.169.08:15:36.99#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.169.08:15:36.99#ibcon#[25=AT07-06\r\n] 2006.169.08:15:36.99#ibcon#*before write, iclass 24, count 2 2006.169.08:15:36.99#ibcon#enter sib2, iclass 24, count 2 2006.169.08:15:36.99#ibcon#flushed, iclass 24, count 2 2006.169.08:15:36.99#ibcon#about to write, iclass 24, count 2 2006.169.08:15:36.99#ibcon#wrote, iclass 24, count 2 2006.169.08:15:36.99#ibcon#about to read 3, iclass 24, count 2 2006.169.08:15:37.01#ibcon#read 3, iclass 24, count 2 2006.169.08:15:37.01#ibcon#about to read 4, iclass 24, count 2 2006.169.08:15:37.01#ibcon#read 4, iclass 24, count 2 2006.169.08:15:37.01#ibcon#about to read 5, iclass 24, count 2 2006.169.08:15:37.01#ibcon#read 5, iclass 24, count 2 2006.169.08:15:37.02#ibcon#about to read 6, iclass 24, count 2 2006.169.08:15:37.02#ibcon#read 6, iclass 24, count 2 2006.169.08:15:37.02#ibcon#end of sib2, iclass 24, count 2 2006.169.08:15:37.02#ibcon#*after write, iclass 24, count 2 2006.169.08:15:37.02#ibcon#*before return 0, iclass 24, count 2 2006.169.08:15:37.02#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.169.08:15:37.02#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.169.08:15:37.02#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.169.08:15:37.02#ibcon#ireg 7 cls_cnt 0 2006.169.08:15:37.02#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.169.08:15:37.14#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.169.08:15:37.14#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.169.08:15:37.14#ibcon#enter wrdev, iclass 24, count 0 2006.169.08:15:37.14#ibcon#first serial, iclass 24, count 0 2006.169.08:15:37.14#ibcon#enter sib2, iclass 24, count 0 2006.169.08:15:37.14#ibcon#flushed, iclass 24, count 0 2006.169.08:15:37.14#ibcon#about to write, iclass 24, count 0 2006.169.08:15:37.14#ibcon#wrote, iclass 24, count 0 2006.169.08:15:37.14#ibcon#about to read 3, iclass 24, count 0 2006.169.08:15:37.15#ibcon#read 3, iclass 24, count 0 2006.169.08:15:37.15#ibcon#about to read 4, iclass 24, count 0 2006.169.08:15:37.15#ibcon#read 4, iclass 24, count 0 2006.169.08:15:37.16#ibcon#about to read 5, iclass 24, count 0 2006.169.08:15:37.16#ibcon#read 5, iclass 24, count 0 2006.169.08:15:37.16#ibcon#about to read 6, iclass 24, count 0 2006.169.08:15:37.16#ibcon#read 6, iclass 24, count 0 2006.169.08:15:37.16#ibcon#end of sib2, iclass 24, count 0 2006.169.08:15:37.16#ibcon#*mode == 0, iclass 24, count 0 2006.169.08:15:37.16#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.169.08:15:37.16#ibcon#[25=USB\r\n] 2006.169.08:15:37.16#ibcon#*before write, iclass 24, count 0 2006.169.08:15:37.16#ibcon#enter sib2, iclass 24, count 0 2006.169.08:15:37.16#ibcon#flushed, iclass 24, count 0 2006.169.08:15:37.16#ibcon#about to write, iclass 24, count 0 2006.169.08:15:37.16#ibcon#wrote, iclass 24, count 0 2006.169.08:15:37.16#ibcon#about to read 3, iclass 24, count 0 2006.169.08:15:37.18#ibcon#read 3, iclass 24, count 0 2006.169.08:15:37.18#ibcon#about to read 4, iclass 24, count 0 2006.169.08:15:37.18#ibcon#read 4, iclass 24, count 0 2006.169.08:15:37.18#ibcon#about to read 5, iclass 24, count 0 2006.169.08:15:37.18#ibcon#read 5, iclass 24, count 0 2006.169.08:15:37.19#ibcon#about to read 6, iclass 24, count 0 2006.169.08:15:37.19#ibcon#read 6, iclass 24, count 0 2006.169.08:15:37.19#ibcon#end of sib2, iclass 24, count 0 2006.169.08:15:37.19#ibcon#*after write, iclass 24, count 0 2006.169.08:15:37.19#ibcon#*before return 0, iclass 24, count 0 2006.169.08:15:37.19#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.169.08:15:37.19#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.169.08:15:37.19#ibcon#about to clear, iclass 24 cls_cnt 0 2006.169.08:15:37.19#ibcon#cleared, iclass 24 cls_cnt 0 2006.169.08:15:37.19$vc4f8/valo=8,852.99 2006.169.08:15:37.19#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.169.08:15:37.19#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.169.08:15:37.19#ibcon#ireg 17 cls_cnt 0 2006.169.08:15:37.19#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:15:37.19#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:15:37.19#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:15:37.19#ibcon#enter wrdev, iclass 26, count 0 2006.169.08:15:37.19#ibcon#first serial, iclass 26, count 0 2006.169.08:15:37.19#ibcon#enter sib2, iclass 26, count 0 2006.169.08:15:37.19#ibcon#flushed, iclass 26, count 0 2006.169.08:15:37.19#ibcon#about to write, iclass 26, count 0 2006.169.08:15:37.19#ibcon#wrote, iclass 26, count 0 2006.169.08:15:37.19#ibcon#about to read 3, iclass 26, count 0 2006.169.08:15:37.20#ibcon#read 3, iclass 26, count 0 2006.169.08:15:37.20#ibcon#about to read 4, iclass 26, count 0 2006.169.08:15:37.20#ibcon#read 4, iclass 26, count 0 2006.169.08:15:37.20#ibcon#about to read 5, iclass 26, count 0 2006.169.08:15:37.20#ibcon#read 5, iclass 26, count 0 2006.169.08:15:37.21#ibcon#about to read 6, iclass 26, count 0 2006.169.08:15:37.21#ibcon#read 6, iclass 26, count 0 2006.169.08:15:37.21#ibcon#end of sib2, iclass 26, count 0 2006.169.08:15:37.21#ibcon#*mode == 0, iclass 26, count 0 2006.169.08:15:37.21#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.169.08:15:37.21#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.08:15:37.21#ibcon#*before write, iclass 26, count 0 2006.169.08:15:37.21#ibcon#enter sib2, iclass 26, count 0 2006.169.08:15:37.21#ibcon#flushed, iclass 26, count 0 2006.169.08:15:37.21#ibcon#about to write, iclass 26, count 0 2006.169.08:15:37.21#ibcon#wrote, iclass 26, count 0 2006.169.08:15:37.21#ibcon#about to read 3, iclass 26, count 0 2006.169.08:15:37.24#ibcon#read 3, iclass 26, count 0 2006.169.08:15:37.24#ibcon#about to read 4, iclass 26, count 0 2006.169.08:15:37.24#ibcon#read 4, iclass 26, count 0 2006.169.08:15:37.24#ibcon#about to read 5, iclass 26, count 0 2006.169.08:15:37.24#ibcon#read 5, iclass 26, count 0 2006.169.08:15:37.25#ibcon#about to read 6, iclass 26, count 0 2006.169.08:15:37.25#ibcon#read 6, iclass 26, count 0 2006.169.08:15:37.25#ibcon#end of sib2, iclass 26, count 0 2006.169.08:15:37.25#ibcon#*after write, iclass 26, count 0 2006.169.08:15:37.25#ibcon#*before return 0, iclass 26, count 0 2006.169.08:15:37.25#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:15:37.25#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:15:37.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.169.08:15:37.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.169.08:15:37.25$vc4f8/va=8,7 2006.169.08:15:37.25#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.169.08:15:37.25#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.169.08:15:37.25#ibcon#ireg 11 cls_cnt 2 2006.169.08:15:37.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.169.08:15:37.30#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.169.08:15:37.30#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.169.08:15:37.30#ibcon#enter wrdev, iclass 28, count 2 2006.169.08:15:37.30#ibcon#first serial, iclass 28, count 2 2006.169.08:15:37.30#ibcon#enter sib2, iclass 28, count 2 2006.169.08:15:37.30#ibcon#flushed, iclass 28, count 2 2006.169.08:15:37.30#ibcon#about to write, iclass 28, count 2 2006.169.08:15:37.31#ibcon#wrote, iclass 28, count 2 2006.169.08:15:37.31#ibcon#about to read 3, iclass 28, count 2 2006.169.08:15:37.32#ibcon#read 3, iclass 28, count 2 2006.169.08:15:37.32#ibcon#about to read 4, iclass 28, count 2 2006.169.08:15:37.32#ibcon#read 4, iclass 28, count 2 2006.169.08:15:37.32#ibcon#about to read 5, iclass 28, count 2 2006.169.08:15:37.33#ibcon#read 5, iclass 28, count 2 2006.169.08:15:37.33#ibcon#about to read 6, iclass 28, count 2 2006.169.08:15:37.33#ibcon#read 6, iclass 28, count 2 2006.169.08:15:37.33#ibcon#end of sib2, iclass 28, count 2 2006.169.08:15:37.33#ibcon#*mode == 0, iclass 28, count 2 2006.169.08:15:37.33#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.169.08:15:37.33#ibcon#[25=AT08-07\r\n] 2006.169.08:15:37.33#ibcon#*before write, iclass 28, count 2 2006.169.08:15:37.33#ibcon#enter sib2, iclass 28, count 2 2006.169.08:15:37.33#ibcon#flushed, iclass 28, count 2 2006.169.08:15:37.33#ibcon#about to write, iclass 28, count 2 2006.169.08:15:37.33#ibcon#wrote, iclass 28, count 2 2006.169.08:15:37.33#ibcon#about to read 3, iclass 28, count 2 2006.169.08:15:37.35#ibcon#read 3, iclass 28, count 2 2006.169.08:15:37.35#ibcon#about to read 4, iclass 28, count 2 2006.169.08:15:37.35#ibcon#read 4, iclass 28, count 2 2006.169.08:15:37.35#ibcon#about to read 5, iclass 28, count 2 2006.169.08:15:37.35#ibcon#read 5, iclass 28, count 2 2006.169.08:15:37.36#ibcon#about to read 6, iclass 28, count 2 2006.169.08:15:37.36#ibcon#read 6, iclass 28, count 2 2006.169.08:15:37.36#ibcon#end of sib2, iclass 28, count 2 2006.169.08:15:37.36#ibcon#*after write, iclass 28, count 2 2006.169.08:15:37.36#ibcon#*before return 0, iclass 28, count 2 2006.169.08:15:37.36#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.169.08:15:37.36#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.169.08:15:37.36#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.169.08:15:37.36#ibcon#ireg 7 cls_cnt 0 2006.169.08:15:37.36#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.169.08:15:37.47#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.169.08:15:37.47#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.169.08:15:37.47#ibcon#enter wrdev, iclass 28, count 0 2006.169.08:15:37.47#ibcon#first serial, iclass 28, count 0 2006.169.08:15:37.47#ibcon#enter sib2, iclass 28, count 0 2006.169.08:15:37.47#ibcon#flushed, iclass 28, count 0 2006.169.08:15:37.48#ibcon#about to write, iclass 28, count 0 2006.169.08:15:37.48#ibcon#wrote, iclass 28, count 0 2006.169.08:15:37.48#ibcon#about to read 3, iclass 28, count 0 2006.169.08:15:37.49#ibcon#read 3, iclass 28, count 0 2006.169.08:15:37.49#ibcon#about to read 4, iclass 28, count 0 2006.169.08:15:37.49#ibcon#read 4, iclass 28, count 0 2006.169.08:15:37.49#ibcon#about to read 5, iclass 28, count 0 2006.169.08:15:37.49#ibcon#read 5, iclass 28, count 0 2006.169.08:15:37.50#ibcon#about to read 6, iclass 28, count 0 2006.169.08:15:37.50#ibcon#read 6, iclass 28, count 0 2006.169.08:15:37.50#ibcon#end of sib2, iclass 28, count 0 2006.169.08:15:37.50#ibcon#*mode == 0, iclass 28, count 0 2006.169.08:15:37.50#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.169.08:15:37.50#ibcon#[25=USB\r\n] 2006.169.08:15:37.50#ibcon#*before write, iclass 28, count 0 2006.169.08:15:37.50#ibcon#enter sib2, iclass 28, count 0 2006.169.08:15:37.50#ibcon#flushed, iclass 28, count 0 2006.169.08:15:37.50#ibcon#about to write, iclass 28, count 0 2006.169.08:15:37.50#ibcon#wrote, iclass 28, count 0 2006.169.08:15:37.50#ibcon#about to read 3, iclass 28, count 0 2006.169.08:15:37.52#ibcon#read 3, iclass 28, count 0 2006.169.08:15:37.52#ibcon#about to read 4, iclass 28, count 0 2006.169.08:15:37.52#ibcon#read 4, iclass 28, count 0 2006.169.08:15:37.52#ibcon#about to read 5, iclass 28, count 0 2006.169.08:15:37.52#ibcon#read 5, iclass 28, count 0 2006.169.08:15:37.53#ibcon#about to read 6, iclass 28, count 0 2006.169.08:15:37.53#ibcon#read 6, iclass 28, count 0 2006.169.08:15:37.53#ibcon#end of sib2, iclass 28, count 0 2006.169.08:15:37.53#ibcon#*after write, iclass 28, count 0 2006.169.08:15:37.53#ibcon#*before return 0, iclass 28, count 0 2006.169.08:15:37.53#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.169.08:15:37.53#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.169.08:15:37.53#ibcon#about to clear, iclass 28 cls_cnt 0 2006.169.08:15:37.53#ibcon#cleared, iclass 28 cls_cnt 0 2006.169.08:15:37.53$vc4f8/vblo=1,632.99 2006.169.08:15:37.53#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.169.08:15:37.53#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.169.08:15:37.53#ibcon#ireg 17 cls_cnt 0 2006.169.08:15:37.53#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.169.08:15:37.53#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.169.08:15:37.53#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.169.08:15:37.53#ibcon#enter wrdev, iclass 30, count 0 2006.169.08:15:37.53#ibcon#first serial, iclass 30, count 0 2006.169.08:15:37.53#ibcon#enter sib2, iclass 30, count 0 2006.169.08:15:37.53#ibcon#flushed, iclass 30, count 0 2006.169.08:15:37.53#ibcon#about to write, iclass 30, count 0 2006.169.08:15:37.53#ibcon#wrote, iclass 30, count 0 2006.169.08:15:37.53#ibcon#about to read 3, iclass 30, count 0 2006.169.08:15:37.54#ibcon#read 3, iclass 30, count 0 2006.169.08:15:37.54#ibcon#about to read 4, iclass 30, count 0 2006.169.08:15:37.54#ibcon#read 4, iclass 30, count 0 2006.169.08:15:37.54#ibcon#about to read 5, iclass 30, count 0 2006.169.08:15:37.54#ibcon#read 5, iclass 30, count 0 2006.169.08:15:37.55#ibcon#about to read 6, iclass 30, count 0 2006.169.08:15:37.55#ibcon#read 6, iclass 30, count 0 2006.169.08:15:37.55#ibcon#end of sib2, iclass 30, count 0 2006.169.08:15:37.55#ibcon#*mode == 0, iclass 30, count 0 2006.169.08:15:37.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.169.08:15:37.55#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.08:15:37.55#ibcon#*before write, iclass 30, count 0 2006.169.08:15:37.55#ibcon#enter sib2, iclass 30, count 0 2006.169.08:15:37.55#ibcon#flushed, iclass 30, count 0 2006.169.08:15:37.55#ibcon#about to write, iclass 30, count 0 2006.169.08:15:37.55#ibcon#wrote, iclass 30, count 0 2006.169.08:15:37.55#ibcon#about to read 3, iclass 30, count 0 2006.169.08:15:37.58#ibcon#read 3, iclass 30, count 0 2006.169.08:15:37.58#ibcon#about to read 4, iclass 30, count 0 2006.169.08:15:37.58#ibcon#read 4, iclass 30, count 0 2006.169.08:15:37.58#ibcon#about to read 5, iclass 30, count 0 2006.169.08:15:37.58#ibcon#read 5, iclass 30, count 0 2006.169.08:15:37.58#ibcon#about to read 6, iclass 30, count 0 2006.169.08:15:37.59#ibcon#read 6, iclass 30, count 0 2006.169.08:15:37.59#ibcon#end of sib2, iclass 30, count 0 2006.169.08:15:37.59#ibcon#*after write, iclass 30, count 0 2006.169.08:15:37.59#ibcon#*before return 0, iclass 30, count 0 2006.169.08:15:37.59#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.169.08:15:37.59#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.169.08:15:37.59#ibcon#about to clear, iclass 30 cls_cnt 0 2006.169.08:15:37.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.169.08:15:37.59$vc4f8/vb=1,4 2006.169.08:15:37.59#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.169.08:15:37.59#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.169.08:15:37.59#ibcon#ireg 11 cls_cnt 2 2006.169.08:15:37.59#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.169.08:15:37.59#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.169.08:15:37.59#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.169.08:15:37.59#ibcon#enter wrdev, iclass 32, count 2 2006.169.08:15:37.59#ibcon#first serial, iclass 32, count 2 2006.169.08:15:37.59#ibcon#enter sib2, iclass 32, count 2 2006.169.08:15:37.59#ibcon#flushed, iclass 32, count 2 2006.169.08:15:37.59#ibcon#about to write, iclass 32, count 2 2006.169.08:15:37.59#ibcon#wrote, iclass 32, count 2 2006.169.08:15:37.59#ibcon#about to read 3, iclass 32, count 2 2006.169.08:15:37.60#ibcon#read 3, iclass 32, count 2 2006.169.08:15:37.60#ibcon#about to read 4, iclass 32, count 2 2006.169.08:15:37.60#ibcon#read 4, iclass 32, count 2 2006.169.08:15:37.60#ibcon#about to read 5, iclass 32, count 2 2006.169.08:15:37.60#ibcon#read 5, iclass 32, count 2 2006.169.08:15:37.61#ibcon#about to read 6, iclass 32, count 2 2006.169.08:15:37.61#ibcon#read 6, iclass 32, count 2 2006.169.08:15:37.61#ibcon#end of sib2, iclass 32, count 2 2006.169.08:15:37.61#ibcon#*mode == 0, iclass 32, count 2 2006.169.08:15:37.61#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.169.08:15:37.61#ibcon#[27=AT01-04\r\n] 2006.169.08:15:37.61#ibcon#*before write, iclass 32, count 2 2006.169.08:15:37.61#ibcon#enter sib2, iclass 32, count 2 2006.169.08:15:37.61#ibcon#flushed, iclass 32, count 2 2006.169.08:15:37.61#ibcon#about to write, iclass 32, count 2 2006.169.08:15:37.61#ibcon#wrote, iclass 32, count 2 2006.169.08:15:37.61#ibcon#about to read 3, iclass 32, count 2 2006.169.08:15:37.63#ibcon#read 3, iclass 32, count 2 2006.169.08:15:37.63#ibcon#about to read 4, iclass 32, count 2 2006.169.08:15:37.63#ibcon#read 4, iclass 32, count 2 2006.169.08:15:37.63#ibcon#about to read 5, iclass 32, count 2 2006.169.08:15:37.63#ibcon#read 5, iclass 32, count 2 2006.169.08:15:37.64#ibcon#about to read 6, iclass 32, count 2 2006.169.08:15:37.64#ibcon#read 6, iclass 32, count 2 2006.169.08:15:37.64#ibcon#end of sib2, iclass 32, count 2 2006.169.08:15:37.64#ibcon#*after write, iclass 32, count 2 2006.169.08:15:37.64#ibcon#*before return 0, iclass 32, count 2 2006.169.08:15:37.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.169.08:15:37.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.169.08:15:37.64#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.169.08:15:37.64#ibcon#ireg 7 cls_cnt 0 2006.169.08:15:37.64#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.169.08:15:37.75#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.169.08:15:37.75#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.169.08:15:37.75#ibcon#enter wrdev, iclass 32, count 0 2006.169.08:15:37.75#ibcon#first serial, iclass 32, count 0 2006.169.08:15:37.75#ibcon#enter sib2, iclass 32, count 0 2006.169.08:15:37.75#ibcon#flushed, iclass 32, count 0 2006.169.08:15:37.75#ibcon#about to write, iclass 32, count 0 2006.169.08:15:37.76#ibcon#wrote, iclass 32, count 0 2006.169.08:15:37.76#ibcon#about to read 3, iclass 32, count 0 2006.169.08:15:37.77#ibcon#read 3, iclass 32, count 0 2006.169.08:15:37.77#ibcon#about to read 4, iclass 32, count 0 2006.169.08:15:37.77#ibcon#read 4, iclass 32, count 0 2006.169.08:15:37.77#ibcon#about to read 5, iclass 32, count 0 2006.169.08:15:37.77#ibcon#read 5, iclass 32, count 0 2006.169.08:15:37.78#ibcon#about to read 6, iclass 32, count 0 2006.169.08:15:37.78#ibcon#read 6, iclass 32, count 0 2006.169.08:15:37.78#ibcon#end of sib2, iclass 32, count 0 2006.169.08:15:37.78#ibcon#*mode == 0, iclass 32, count 0 2006.169.08:15:37.78#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.169.08:15:37.78#ibcon#[27=USB\r\n] 2006.169.08:15:37.78#ibcon#*before write, iclass 32, count 0 2006.169.08:15:37.78#ibcon#enter sib2, iclass 32, count 0 2006.169.08:15:37.78#ibcon#flushed, iclass 32, count 0 2006.169.08:15:37.78#ibcon#about to write, iclass 32, count 0 2006.169.08:15:37.78#ibcon#wrote, iclass 32, count 0 2006.169.08:15:37.78#ibcon#about to read 3, iclass 32, count 0 2006.169.08:15:37.80#ibcon#read 3, iclass 32, count 0 2006.169.08:15:37.80#ibcon#about to read 4, iclass 32, count 0 2006.169.08:15:37.81#ibcon#read 4, iclass 32, count 0 2006.169.08:15:37.81#ibcon#about to read 5, iclass 32, count 0 2006.169.08:15:37.81#ibcon#read 5, iclass 32, count 0 2006.169.08:15:37.81#ibcon#about to read 6, iclass 32, count 0 2006.169.08:15:37.81#ibcon#read 6, iclass 32, count 0 2006.169.08:15:37.81#ibcon#end of sib2, iclass 32, count 0 2006.169.08:15:37.81#ibcon#*after write, iclass 32, count 0 2006.169.08:15:37.81#ibcon#*before return 0, iclass 32, count 0 2006.169.08:15:37.81#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.169.08:15:37.81#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.169.08:15:37.81#ibcon#about to clear, iclass 32 cls_cnt 0 2006.169.08:15:37.81#ibcon#cleared, iclass 32 cls_cnt 0 2006.169.08:15:37.81$vc4f8/vblo=2,640.99 2006.169.08:15:37.81#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.169.08:15:37.81#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.169.08:15:37.81#ibcon#ireg 17 cls_cnt 0 2006.169.08:15:37.81#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:15:37.81#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:15:37.81#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:15:37.81#ibcon#enter wrdev, iclass 34, count 0 2006.169.08:15:37.81#ibcon#first serial, iclass 34, count 0 2006.169.08:15:37.81#ibcon#enter sib2, iclass 34, count 0 2006.169.08:15:37.81#ibcon#flushed, iclass 34, count 0 2006.169.08:15:37.81#ibcon#about to write, iclass 34, count 0 2006.169.08:15:37.81#ibcon#wrote, iclass 34, count 0 2006.169.08:15:37.81#ibcon#about to read 3, iclass 34, count 0 2006.169.08:15:37.82#ibcon#read 3, iclass 34, count 0 2006.169.08:15:37.82#ibcon#about to read 4, iclass 34, count 0 2006.169.08:15:37.82#ibcon#read 4, iclass 34, count 0 2006.169.08:15:37.82#ibcon#about to read 5, iclass 34, count 0 2006.169.08:15:37.83#ibcon#read 5, iclass 34, count 0 2006.169.08:15:37.83#ibcon#about to read 6, iclass 34, count 0 2006.169.08:15:37.83#ibcon#read 6, iclass 34, count 0 2006.169.08:15:37.83#ibcon#end of sib2, iclass 34, count 0 2006.169.08:15:37.83#ibcon#*mode == 0, iclass 34, count 0 2006.169.08:15:37.83#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.169.08:15:37.83#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.08:15:37.83#ibcon#*before write, iclass 34, count 0 2006.169.08:15:37.83#ibcon#enter sib2, iclass 34, count 0 2006.169.08:15:37.83#ibcon#flushed, iclass 34, count 0 2006.169.08:15:37.83#ibcon#about to write, iclass 34, count 0 2006.169.08:15:37.83#ibcon#wrote, iclass 34, count 0 2006.169.08:15:37.83#ibcon#about to read 3, iclass 34, count 0 2006.169.08:15:37.86#ibcon#read 3, iclass 34, count 0 2006.169.08:15:37.86#ibcon#about to read 4, iclass 34, count 0 2006.169.08:15:37.86#ibcon#read 4, iclass 34, count 0 2006.169.08:15:37.86#ibcon#about to read 5, iclass 34, count 0 2006.169.08:15:37.86#ibcon#read 5, iclass 34, count 0 2006.169.08:15:37.87#ibcon#about to read 6, iclass 34, count 0 2006.169.08:15:37.87#ibcon#read 6, iclass 34, count 0 2006.169.08:15:37.87#ibcon#end of sib2, iclass 34, count 0 2006.169.08:15:37.87#ibcon#*after write, iclass 34, count 0 2006.169.08:15:37.87#ibcon#*before return 0, iclass 34, count 0 2006.169.08:15:37.87#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:15:37.87#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:15:37.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.169.08:15:37.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.169.08:15:37.87$vc4f8/vb=2,4 2006.169.08:15:37.87#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.169.08:15:37.87#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.169.08:15:37.87#ibcon#ireg 11 cls_cnt 2 2006.169.08:15:37.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.169.08:15:37.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.169.08:15:37.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.169.08:15:37.92#ibcon#enter wrdev, iclass 36, count 2 2006.169.08:15:37.92#ibcon#first serial, iclass 36, count 2 2006.169.08:15:37.92#ibcon#enter sib2, iclass 36, count 2 2006.169.08:15:37.92#ibcon#flushed, iclass 36, count 2 2006.169.08:15:37.92#ibcon#about to write, iclass 36, count 2 2006.169.08:15:37.93#ibcon#wrote, iclass 36, count 2 2006.169.08:15:37.93#ibcon#about to read 3, iclass 36, count 2 2006.169.08:15:37.94#ibcon#read 3, iclass 36, count 2 2006.169.08:15:37.94#ibcon#about to read 4, iclass 36, count 2 2006.169.08:15:37.94#ibcon#read 4, iclass 36, count 2 2006.169.08:15:37.94#ibcon#about to read 5, iclass 36, count 2 2006.169.08:15:37.94#ibcon#read 5, iclass 36, count 2 2006.169.08:15:37.94#ibcon#about to read 6, iclass 36, count 2 2006.169.08:15:37.95#ibcon#read 6, iclass 36, count 2 2006.169.08:15:37.95#ibcon#end of sib2, iclass 36, count 2 2006.169.08:15:37.95#ibcon#*mode == 0, iclass 36, count 2 2006.169.08:15:37.95#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.169.08:15:37.95#ibcon#[27=AT02-04\r\n] 2006.169.08:15:37.95#ibcon#*before write, iclass 36, count 2 2006.169.08:15:37.95#ibcon#enter sib2, iclass 36, count 2 2006.169.08:15:37.95#ibcon#flushed, iclass 36, count 2 2006.169.08:15:37.95#ibcon#about to write, iclass 36, count 2 2006.169.08:15:37.95#ibcon#wrote, iclass 36, count 2 2006.169.08:15:37.95#ibcon#about to read 3, iclass 36, count 2 2006.169.08:15:37.97#ibcon#read 3, iclass 36, count 2 2006.169.08:15:37.97#ibcon#about to read 4, iclass 36, count 2 2006.169.08:15:37.97#ibcon#read 4, iclass 36, count 2 2006.169.08:15:37.97#ibcon#about to read 5, iclass 36, count 2 2006.169.08:15:37.97#ibcon#read 5, iclass 36, count 2 2006.169.08:15:37.97#ibcon#about to read 6, iclass 36, count 2 2006.169.08:15:37.98#ibcon#read 6, iclass 36, count 2 2006.169.08:15:37.98#ibcon#end of sib2, iclass 36, count 2 2006.169.08:15:37.98#ibcon#*after write, iclass 36, count 2 2006.169.08:15:37.98#ibcon#*before return 0, iclass 36, count 2 2006.169.08:15:37.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.169.08:15:37.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.169.08:15:37.98#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.169.08:15:37.98#ibcon#ireg 7 cls_cnt 0 2006.169.08:15:37.98#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.169.08:15:38.10#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.169.08:15:38.10#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.169.08:15:38.10#ibcon#enter wrdev, iclass 36, count 0 2006.169.08:15:38.10#ibcon#first serial, iclass 36, count 0 2006.169.08:15:38.10#ibcon#enter sib2, iclass 36, count 0 2006.169.08:15:38.10#ibcon#flushed, iclass 36, count 0 2006.169.08:15:38.10#ibcon#about to write, iclass 36, count 0 2006.169.08:15:38.10#ibcon#wrote, iclass 36, count 0 2006.169.08:15:38.10#ibcon#about to read 3, iclass 36, count 0 2006.169.08:15:38.11#ibcon#read 3, iclass 36, count 0 2006.169.08:15:38.11#ibcon#about to read 4, iclass 36, count 0 2006.169.08:15:38.12#ibcon#read 4, iclass 36, count 0 2006.169.08:15:38.12#ibcon#about to read 5, iclass 36, count 0 2006.169.08:15:38.12#ibcon#read 5, iclass 36, count 0 2006.169.08:15:38.12#ibcon#about to read 6, iclass 36, count 0 2006.169.08:15:38.12#ibcon#read 6, iclass 36, count 0 2006.169.08:15:38.12#ibcon#end of sib2, iclass 36, count 0 2006.169.08:15:38.12#ibcon#*mode == 0, iclass 36, count 0 2006.169.08:15:38.12#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.169.08:15:38.12#ibcon#[27=USB\r\n] 2006.169.08:15:38.12#ibcon#*before write, iclass 36, count 0 2006.169.08:15:38.12#ibcon#enter sib2, iclass 36, count 0 2006.169.08:15:38.12#ibcon#flushed, iclass 36, count 0 2006.169.08:15:38.12#ibcon#about to write, iclass 36, count 0 2006.169.08:15:38.12#ibcon#wrote, iclass 36, count 0 2006.169.08:15:38.12#ibcon#about to read 3, iclass 36, count 0 2006.169.08:15:38.14#ibcon#read 3, iclass 36, count 0 2006.169.08:15:38.14#ibcon#about to read 4, iclass 36, count 0 2006.169.08:15:38.14#ibcon#read 4, iclass 36, count 0 2006.169.08:15:38.14#ibcon#about to read 5, iclass 36, count 0 2006.169.08:15:38.14#ibcon#read 5, iclass 36, count 0 2006.169.08:15:38.14#ibcon#about to read 6, iclass 36, count 0 2006.169.08:15:38.14#ibcon#read 6, iclass 36, count 0 2006.169.08:15:38.14#ibcon#end of sib2, iclass 36, count 0 2006.169.08:15:38.15#ibcon#*after write, iclass 36, count 0 2006.169.08:15:38.15#ibcon#*before return 0, iclass 36, count 0 2006.169.08:15:38.15#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.169.08:15:38.15#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.169.08:15:38.15#ibcon#about to clear, iclass 36 cls_cnt 0 2006.169.08:15:38.15#ibcon#cleared, iclass 36 cls_cnt 0 2006.169.08:15:38.15$vc4f8/vblo=3,656.99 2006.169.08:15:38.15#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.169.08:15:38.15#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.169.08:15:38.15#ibcon#ireg 17 cls_cnt 0 2006.169.08:15:38.15#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.169.08:15:38.15#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.169.08:15:38.15#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.169.08:15:38.15#ibcon#enter wrdev, iclass 38, count 0 2006.169.08:15:38.15#ibcon#first serial, iclass 38, count 0 2006.169.08:15:38.15#ibcon#enter sib2, iclass 38, count 0 2006.169.08:15:38.15#ibcon#flushed, iclass 38, count 0 2006.169.08:15:38.15#ibcon#about to write, iclass 38, count 0 2006.169.08:15:38.15#ibcon#wrote, iclass 38, count 0 2006.169.08:15:38.15#ibcon#about to read 3, iclass 38, count 0 2006.169.08:15:38.16#ibcon#read 3, iclass 38, count 0 2006.169.08:15:38.16#ibcon#about to read 4, iclass 38, count 0 2006.169.08:15:38.16#ibcon#read 4, iclass 38, count 0 2006.169.08:15:38.16#ibcon#about to read 5, iclass 38, count 0 2006.169.08:15:38.16#ibcon#read 5, iclass 38, count 0 2006.169.08:15:38.17#ibcon#about to read 6, iclass 38, count 0 2006.169.08:15:38.17#ibcon#read 6, iclass 38, count 0 2006.169.08:15:38.17#ibcon#end of sib2, iclass 38, count 0 2006.169.08:15:38.17#ibcon#*mode == 0, iclass 38, count 0 2006.169.08:15:38.17#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.169.08:15:38.17#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.08:15:38.17#ibcon#*before write, iclass 38, count 0 2006.169.08:15:38.17#ibcon#enter sib2, iclass 38, count 0 2006.169.08:15:38.17#ibcon#flushed, iclass 38, count 0 2006.169.08:15:38.17#ibcon#about to write, iclass 38, count 0 2006.169.08:15:38.17#ibcon#wrote, iclass 38, count 0 2006.169.08:15:38.17#ibcon#about to read 3, iclass 38, count 0 2006.169.08:15:38.20#ibcon#read 3, iclass 38, count 0 2006.169.08:15:38.20#ibcon#about to read 4, iclass 38, count 0 2006.169.08:15:38.20#ibcon#read 4, iclass 38, count 0 2006.169.08:15:38.20#ibcon#about to read 5, iclass 38, count 0 2006.169.08:15:38.20#ibcon#read 5, iclass 38, count 0 2006.169.08:15:38.21#ibcon#about to read 6, iclass 38, count 0 2006.169.08:15:38.21#ibcon#read 6, iclass 38, count 0 2006.169.08:15:38.21#ibcon#end of sib2, iclass 38, count 0 2006.169.08:15:38.21#ibcon#*after write, iclass 38, count 0 2006.169.08:15:38.21#ibcon#*before return 0, iclass 38, count 0 2006.169.08:15:38.21#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.169.08:15:38.21#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.169.08:15:38.21#ibcon#about to clear, iclass 38 cls_cnt 0 2006.169.08:15:38.21#ibcon#cleared, iclass 38 cls_cnt 0 2006.169.08:15:38.21$vc4f8/vb=3,4 2006.169.08:15:38.21#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.169.08:15:38.21#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.169.08:15:38.21#ibcon#ireg 11 cls_cnt 2 2006.169.08:15:38.21#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.169.08:15:38.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.169.08:15:38.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.169.08:15:38.27#ibcon#enter wrdev, iclass 40, count 2 2006.169.08:15:38.27#ibcon#first serial, iclass 40, count 2 2006.169.08:15:38.27#ibcon#enter sib2, iclass 40, count 2 2006.169.08:15:38.27#ibcon#flushed, iclass 40, count 2 2006.169.08:15:38.27#ibcon#about to write, iclass 40, count 2 2006.169.08:15:38.27#ibcon#wrote, iclass 40, count 2 2006.169.08:15:38.27#ibcon#about to read 3, iclass 40, count 2 2006.169.08:15:38.28#ibcon#read 3, iclass 40, count 2 2006.169.08:15:38.28#ibcon#about to read 4, iclass 40, count 2 2006.169.08:15:38.28#ibcon#read 4, iclass 40, count 2 2006.169.08:15:38.28#ibcon#about to read 5, iclass 40, count 2 2006.169.08:15:38.29#ibcon#read 5, iclass 40, count 2 2006.169.08:15:38.29#ibcon#about to read 6, iclass 40, count 2 2006.169.08:15:38.29#ibcon#read 6, iclass 40, count 2 2006.169.08:15:38.29#ibcon#end of sib2, iclass 40, count 2 2006.169.08:15:38.29#ibcon#*mode == 0, iclass 40, count 2 2006.169.08:15:38.29#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.169.08:15:38.29#ibcon#[27=AT03-04\r\n] 2006.169.08:15:38.29#ibcon#*before write, iclass 40, count 2 2006.169.08:15:38.29#ibcon#enter sib2, iclass 40, count 2 2006.169.08:15:38.29#ibcon#flushed, iclass 40, count 2 2006.169.08:15:38.29#ibcon#about to write, iclass 40, count 2 2006.169.08:15:38.29#ibcon#wrote, iclass 40, count 2 2006.169.08:15:38.29#ibcon#about to read 3, iclass 40, count 2 2006.169.08:15:38.31#ibcon#read 3, iclass 40, count 2 2006.169.08:15:38.31#ibcon#about to read 4, iclass 40, count 2 2006.169.08:15:38.31#ibcon#read 4, iclass 40, count 2 2006.169.08:15:38.31#ibcon#about to read 5, iclass 40, count 2 2006.169.08:15:38.31#ibcon#read 5, iclass 40, count 2 2006.169.08:15:38.32#ibcon#about to read 6, iclass 40, count 2 2006.169.08:15:38.32#ibcon#read 6, iclass 40, count 2 2006.169.08:15:38.32#ibcon#end of sib2, iclass 40, count 2 2006.169.08:15:38.32#ibcon#*after write, iclass 40, count 2 2006.169.08:15:38.32#ibcon#*before return 0, iclass 40, count 2 2006.169.08:15:38.32#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.169.08:15:38.32#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.169.08:15:38.32#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.169.08:15:38.32#ibcon#ireg 7 cls_cnt 0 2006.169.08:15:38.32#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.169.08:15:38.43#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.169.08:15:38.43#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.169.08:15:38.43#ibcon#enter wrdev, iclass 40, count 0 2006.169.08:15:38.43#ibcon#first serial, iclass 40, count 0 2006.169.08:15:38.43#ibcon#enter sib2, iclass 40, count 0 2006.169.08:15:38.43#ibcon#flushed, iclass 40, count 0 2006.169.08:15:38.43#ibcon#about to write, iclass 40, count 0 2006.169.08:15:38.44#ibcon#wrote, iclass 40, count 0 2006.169.08:15:38.44#ibcon#about to read 3, iclass 40, count 0 2006.169.08:15:38.45#ibcon#read 3, iclass 40, count 0 2006.169.08:15:38.45#ibcon#about to read 4, iclass 40, count 0 2006.169.08:15:38.45#ibcon#read 4, iclass 40, count 0 2006.169.08:15:38.45#ibcon#about to read 5, iclass 40, count 0 2006.169.08:15:38.45#ibcon#read 5, iclass 40, count 0 2006.169.08:15:38.46#ibcon#about to read 6, iclass 40, count 0 2006.169.08:15:38.46#ibcon#read 6, iclass 40, count 0 2006.169.08:15:38.46#ibcon#end of sib2, iclass 40, count 0 2006.169.08:15:38.46#ibcon#*mode == 0, iclass 40, count 0 2006.169.08:15:38.46#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.169.08:15:38.46#ibcon#[27=USB\r\n] 2006.169.08:15:38.46#ibcon#*before write, iclass 40, count 0 2006.169.08:15:38.46#ibcon#enter sib2, iclass 40, count 0 2006.169.08:15:38.46#ibcon#flushed, iclass 40, count 0 2006.169.08:15:38.46#ibcon#about to write, iclass 40, count 0 2006.169.08:15:38.46#ibcon#wrote, iclass 40, count 0 2006.169.08:15:38.46#ibcon#about to read 3, iclass 40, count 0 2006.169.08:15:38.48#ibcon#read 3, iclass 40, count 0 2006.169.08:15:38.48#ibcon#about to read 4, iclass 40, count 0 2006.169.08:15:38.48#ibcon#read 4, iclass 40, count 0 2006.169.08:15:38.48#ibcon#about to read 5, iclass 40, count 0 2006.169.08:15:38.48#ibcon#read 5, iclass 40, count 0 2006.169.08:15:38.49#ibcon#about to read 6, iclass 40, count 0 2006.169.08:15:38.49#ibcon#read 6, iclass 40, count 0 2006.169.08:15:38.49#ibcon#end of sib2, iclass 40, count 0 2006.169.08:15:38.49#ibcon#*after write, iclass 40, count 0 2006.169.08:15:38.49#ibcon#*before return 0, iclass 40, count 0 2006.169.08:15:38.49#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.169.08:15:38.49#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.169.08:15:38.49#ibcon#about to clear, iclass 40 cls_cnt 0 2006.169.08:15:38.49#ibcon#cleared, iclass 40 cls_cnt 0 2006.169.08:15:38.49$vc4f8/vblo=4,712.99 2006.169.08:15:38.49#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.169.08:15:38.49#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.169.08:15:38.49#ibcon#ireg 17 cls_cnt 0 2006.169.08:15:38.49#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:15:38.49#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:15:38.49#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:15:38.49#ibcon#enter wrdev, iclass 4, count 0 2006.169.08:15:38.49#ibcon#first serial, iclass 4, count 0 2006.169.08:15:38.49#ibcon#enter sib2, iclass 4, count 0 2006.169.08:15:38.49#ibcon#flushed, iclass 4, count 0 2006.169.08:15:38.49#ibcon#about to write, iclass 4, count 0 2006.169.08:15:38.49#ibcon#wrote, iclass 4, count 0 2006.169.08:15:38.49#ibcon#about to read 3, iclass 4, count 0 2006.169.08:15:38.50#ibcon#read 3, iclass 4, count 0 2006.169.08:15:38.50#ibcon#about to read 4, iclass 4, count 0 2006.169.08:15:38.50#ibcon#read 4, iclass 4, count 0 2006.169.08:15:38.50#ibcon#about to read 5, iclass 4, count 0 2006.169.08:15:38.51#ibcon#read 5, iclass 4, count 0 2006.169.08:15:38.51#ibcon#about to read 6, iclass 4, count 0 2006.169.08:15:38.51#ibcon#read 6, iclass 4, count 0 2006.169.08:15:38.51#ibcon#end of sib2, iclass 4, count 0 2006.169.08:15:38.51#ibcon#*mode == 0, iclass 4, count 0 2006.169.08:15:38.51#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.169.08:15:38.51#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.08:15:38.51#ibcon#*before write, iclass 4, count 0 2006.169.08:15:38.51#ibcon#enter sib2, iclass 4, count 0 2006.169.08:15:38.51#ibcon#flushed, iclass 4, count 0 2006.169.08:15:38.51#ibcon#about to write, iclass 4, count 0 2006.169.08:15:38.51#ibcon#wrote, iclass 4, count 0 2006.169.08:15:38.51#ibcon#about to read 3, iclass 4, count 0 2006.169.08:15:38.54#ibcon#read 3, iclass 4, count 0 2006.169.08:15:38.54#ibcon#about to read 4, iclass 4, count 0 2006.169.08:15:38.54#ibcon#read 4, iclass 4, count 0 2006.169.08:15:38.54#ibcon#about to read 5, iclass 4, count 0 2006.169.08:15:38.54#ibcon#read 5, iclass 4, count 0 2006.169.08:15:38.54#ibcon#about to read 6, iclass 4, count 0 2006.169.08:15:38.55#ibcon#read 6, iclass 4, count 0 2006.169.08:15:38.55#ibcon#end of sib2, iclass 4, count 0 2006.169.08:15:38.55#ibcon#*after write, iclass 4, count 0 2006.169.08:15:38.55#ibcon#*before return 0, iclass 4, count 0 2006.169.08:15:38.55#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:15:38.55#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:15:38.55#ibcon#about to clear, iclass 4 cls_cnt 0 2006.169.08:15:38.55#ibcon#cleared, iclass 4 cls_cnt 0 2006.169.08:15:38.55$vc4f8/vb=4,4 2006.169.08:15:38.55#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.169.08:15:38.55#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.169.08:15:38.55#ibcon#ireg 11 cls_cnt 2 2006.169.08:15:38.55#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.169.08:15:38.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.169.08:15:38.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.169.08:15:38.60#ibcon#enter wrdev, iclass 6, count 2 2006.169.08:15:38.60#ibcon#first serial, iclass 6, count 2 2006.169.08:15:38.60#ibcon#enter sib2, iclass 6, count 2 2006.169.08:15:38.61#ibcon#flushed, iclass 6, count 2 2006.169.08:15:38.61#ibcon#about to write, iclass 6, count 2 2006.169.08:15:38.61#ibcon#wrote, iclass 6, count 2 2006.169.08:15:38.61#ibcon#about to read 3, iclass 6, count 2 2006.169.08:15:38.62#ibcon#read 3, iclass 6, count 2 2006.169.08:15:38.62#ibcon#about to read 4, iclass 6, count 2 2006.169.08:15:38.63#ibcon#read 4, iclass 6, count 2 2006.169.08:15:38.63#ibcon#about to read 5, iclass 6, count 2 2006.169.08:15:38.63#ibcon#read 5, iclass 6, count 2 2006.169.08:15:38.63#ibcon#about to read 6, iclass 6, count 2 2006.169.08:15:38.63#ibcon#read 6, iclass 6, count 2 2006.169.08:15:38.63#ibcon#end of sib2, iclass 6, count 2 2006.169.08:15:38.63#ibcon#*mode == 0, iclass 6, count 2 2006.169.08:15:38.63#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.169.08:15:38.63#ibcon#[27=AT04-04\r\n] 2006.169.08:15:38.63#ibcon#*before write, iclass 6, count 2 2006.169.08:15:38.63#ibcon#enter sib2, iclass 6, count 2 2006.169.08:15:38.63#ibcon#flushed, iclass 6, count 2 2006.169.08:15:38.63#ibcon#about to write, iclass 6, count 2 2006.169.08:15:38.63#ibcon#wrote, iclass 6, count 2 2006.169.08:15:38.63#ibcon#about to read 3, iclass 6, count 2 2006.169.08:15:38.65#ibcon#read 3, iclass 6, count 2 2006.169.08:15:38.65#ibcon#about to read 4, iclass 6, count 2 2006.169.08:15:38.65#ibcon#read 4, iclass 6, count 2 2006.169.08:15:38.65#ibcon#about to read 5, iclass 6, count 2 2006.169.08:15:38.65#ibcon#read 5, iclass 6, count 2 2006.169.08:15:38.66#ibcon#about to read 6, iclass 6, count 2 2006.169.08:15:38.66#ibcon#read 6, iclass 6, count 2 2006.169.08:15:38.66#ibcon#end of sib2, iclass 6, count 2 2006.169.08:15:38.66#ibcon#*after write, iclass 6, count 2 2006.169.08:15:38.66#ibcon#*before return 0, iclass 6, count 2 2006.169.08:15:38.66#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.169.08:15:38.66#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.169.08:15:38.66#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.169.08:15:38.66#ibcon#ireg 7 cls_cnt 0 2006.169.08:15:38.66#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.169.08:15:38.77#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.169.08:15:38.77#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.169.08:15:38.77#ibcon#enter wrdev, iclass 6, count 0 2006.169.08:15:38.77#ibcon#first serial, iclass 6, count 0 2006.169.08:15:38.77#ibcon#enter sib2, iclass 6, count 0 2006.169.08:15:38.77#ibcon#flushed, iclass 6, count 0 2006.169.08:15:38.77#ibcon#about to write, iclass 6, count 0 2006.169.08:15:38.78#ibcon#wrote, iclass 6, count 0 2006.169.08:15:38.78#ibcon#about to read 3, iclass 6, count 0 2006.169.08:15:38.79#ibcon#read 3, iclass 6, count 0 2006.169.08:15:38.79#ibcon#about to read 4, iclass 6, count 0 2006.169.08:15:38.79#ibcon#read 4, iclass 6, count 0 2006.169.08:15:38.79#ibcon#about to read 5, iclass 6, count 0 2006.169.08:15:38.79#ibcon#read 5, iclass 6, count 0 2006.169.08:15:38.80#ibcon#about to read 6, iclass 6, count 0 2006.169.08:15:38.80#ibcon#read 6, iclass 6, count 0 2006.169.08:15:38.80#ibcon#end of sib2, iclass 6, count 0 2006.169.08:15:38.80#ibcon#*mode == 0, iclass 6, count 0 2006.169.08:15:38.80#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.169.08:15:38.80#ibcon#[27=USB\r\n] 2006.169.08:15:38.80#ibcon#*before write, iclass 6, count 0 2006.169.08:15:38.80#ibcon#enter sib2, iclass 6, count 0 2006.169.08:15:38.80#ibcon#flushed, iclass 6, count 0 2006.169.08:15:38.80#ibcon#about to write, iclass 6, count 0 2006.169.08:15:38.80#ibcon#wrote, iclass 6, count 0 2006.169.08:15:38.80#ibcon#about to read 3, iclass 6, count 0 2006.169.08:15:38.82#ibcon#read 3, iclass 6, count 0 2006.169.08:15:38.82#ibcon#about to read 4, iclass 6, count 0 2006.169.08:15:38.82#ibcon#read 4, iclass 6, count 0 2006.169.08:15:38.82#ibcon#about to read 5, iclass 6, count 0 2006.169.08:15:38.82#ibcon#read 5, iclass 6, count 0 2006.169.08:15:38.83#ibcon#about to read 6, iclass 6, count 0 2006.169.08:15:38.83#ibcon#read 6, iclass 6, count 0 2006.169.08:15:38.83#ibcon#end of sib2, iclass 6, count 0 2006.169.08:15:38.83#ibcon#*after write, iclass 6, count 0 2006.169.08:15:38.83#ibcon#*before return 0, iclass 6, count 0 2006.169.08:15:38.83#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.169.08:15:38.83#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.169.08:15:38.83#ibcon#about to clear, iclass 6 cls_cnt 0 2006.169.08:15:38.83#ibcon#cleared, iclass 6 cls_cnt 0 2006.169.08:15:38.83$vc4f8/vblo=5,744.99 2006.169.08:15:38.83#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.169.08:15:38.83#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.169.08:15:38.83#ibcon#ireg 17 cls_cnt 0 2006.169.08:15:38.83#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.169.08:15:38.83#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.169.08:15:38.83#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.169.08:15:38.83#ibcon#enter wrdev, iclass 10, count 0 2006.169.08:15:38.83#ibcon#first serial, iclass 10, count 0 2006.169.08:15:38.83#ibcon#enter sib2, iclass 10, count 0 2006.169.08:15:38.83#ibcon#flushed, iclass 10, count 0 2006.169.08:15:38.83#ibcon#about to write, iclass 10, count 0 2006.169.08:15:38.83#ibcon#wrote, iclass 10, count 0 2006.169.08:15:38.83#ibcon#about to read 3, iclass 10, count 0 2006.169.08:15:38.84#ibcon#read 3, iclass 10, count 0 2006.169.08:15:38.84#ibcon#about to read 4, iclass 10, count 0 2006.169.08:15:38.84#ibcon#read 4, iclass 10, count 0 2006.169.08:15:38.84#ibcon#about to read 5, iclass 10, count 0 2006.169.08:15:38.84#ibcon#read 5, iclass 10, count 0 2006.169.08:15:38.85#ibcon#about to read 6, iclass 10, count 0 2006.169.08:15:38.85#ibcon#read 6, iclass 10, count 0 2006.169.08:15:38.85#ibcon#end of sib2, iclass 10, count 0 2006.169.08:15:38.85#ibcon#*mode == 0, iclass 10, count 0 2006.169.08:15:38.85#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.169.08:15:38.85#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.08:15:38.85#ibcon#*before write, iclass 10, count 0 2006.169.08:15:38.85#ibcon#enter sib2, iclass 10, count 0 2006.169.08:15:38.85#ibcon#flushed, iclass 10, count 0 2006.169.08:15:38.85#ibcon#about to write, iclass 10, count 0 2006.169.08:15:38.85#ibcon#wrote, iclass 10, count 0 2006.169.08:15:38.85#ibcon#about to read 3, iclass 10, count 0 2006.169.08:15:38.88#ibcon#read 3, iclass 10, count 0 2006.169.08:15:38.88#ibcon#about to read 4, iclass 10, count 0 2006.169.08:15:38.88#ibcon#read 4, iclass 10, count 0 2006.169.08:15:38.88#ibcon#about to read 5, iclass 10, count 0 2006.169.08:15:38.88#ibcon#read 5, iclass 10, count 0 2006.169.08:15:38.88#ibcon#about to read 6, iclass 10, count 0 2006.169.08:15:38.89#ibcon#read 6, iclass 10, count 0 2006.169.08:15:38.89#ibcon#end of sib2, iclass 10, count 0 2006.169.08:15:38.89#ibcon#*after write, iclass 10, count 0 2006.169.08:15:38.89#ibcon#*before return 0, iclass 10, count 0 2006.169.08:15:38.89#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.169.08:15:38.89#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.169.08:15:38.89#ibcon#about to clear, iclass 10 cls_cnt 0 2006.169.08:15:38.89#ibcon#cleared, iclass 10 cls_cnt 0 2006.169.08:15:38.89$vc4f8/vb=5,4 2006.169.08:15:38.89#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.169.08:15:38.89#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.169.08:15:38.89#ibcon#ireg 11 cls_cnt 2 2006.169.08:15:38.89#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.169.08:15:38.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.169.08:15:38.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.169.08:15:38.94#ibcon#enter wrdev, iclass 12, count 2 2006.169.08:15:38.94#ibcon#first serial, iclass 12, count 2 2006.169.08:15:38.94#ibcon#enter sib2, iclass 12, count 2 2006.169.08:15:38.94#ibcon#flushed, iclass 12, count 2 2006.169.08:15:38.94#ibcon#about to write, iclass 12, count 2 2006.169.08:15:38.95#ibcon#wrote, iclass 12, count 2 2006.169.08:15:38.95#ibcon#about to read 3, iclass 12, count 2 2006.169.08:15:38.96#ibcon#read 3, iclass 12, count 2 2006.169.08:15:38.96#ibcon#about to read 4, iclass 12, count 2 2006.169.08:15:38.96#ibcon#read 4, iclass 12, count 2 2006.169.08:15:38.96#ibcon#about to read 5, iclass 12, count 2 2006.169.08:15:38.97#ibcon#read 5, iclass 12, count 2 2006.169.08:15:38.97#ibcon#about to read 6, iclass 12, count 2 2006.169.08:15:38.97#ibcon#read 6, iclass 12, count 2 2006.169.08:15:38.97#ibcon#end of sib2, iclass 12, count 2 2006.169.08:15:38.97#ibcon#*mode == 0, iclass 12, count 2 2006.169.08:15:38.97#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.169.08:15:38.97#ibcon#[27=AT05-04\r\n] 2006.169.08:15:38.97#ibcon#*before write, iclass 12, count 2 2006.169.08:15:38.97#ibcon#enter sib2, iclass 12, count 2 2006.169.08:15:38.97#ibcon#flushed, iclass 12, count 2 2006.169.08:15:38.97#ibcon#about to write, iclass 12, count 2 2006.169.08:15:38.97#ibcon#wrote, iclass 12, count 2 2006.169.08:15:38.97#ibcon#about to read 3, iclass 12, count 2 2006.169.08:15:38.99#ibcon#read 3, iclass 12, count 2 2006.169.08:15:38.99#ibcon#about to read 4, iclass 12, count 2 2006.169.08:15:38.99#ibcon#read 4, iclass 12, count 2 2006.169.08:15:38.99#ibcon#about to read 5, iclass 12, count 2 2006.169.08:15:38.99#ibcon#read 5, iclass 12, count 2 2006.169.08:15:39.00#ibcon#about to read 6, iclass 12, count 2 2006.169.08:15:39.00#ibcon#read 6, iclass 12, count 2 2006.169.08:15:39.00#ibcon#end of sib2, iclass 12, count 2 2006.169.08:15:39.00#ibcon#*after write, iclass 12, count 2 2006.169.08:15:39.00#ibcon#*before return 0, iclass 12, count 2 2006.169.08:15:39.00#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.169.08:15:39.00#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.169.08:15:39.00#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.169.08:15:39.00#ibcon#ireg 7 cls_cnt 0 2006.169.08:15:39.00#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.169.08:15:39.11#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.169.08:15:39.11#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.169.08:15:39.11#ibcon#enter wrdev, iclass 12, count 0 2006.169.08:15:39.11#ibcon#first serial, iclass 12, count 0 2006.169.08:15:39.11#ibcon#enter sib2, iclass 12, count 0 2006.169.08:15:39.12#ibcon#flushed, iclass 12, count 0 2006.169.08:15:39.12#ibcon#about to write, iclass 12, count 0 2006.169.08:15:39.12#ibcon#wrote, iclass 12, count 0 2006.169.08:15:39.12#ibcon#about to read 3, iclass 12, count 0 2006.169.08:15:39.13#ibcon#read 3, iclass 12, count 0 2006.169.08:15:39.13#ibcon#about to read 4, iclass 12, count 0 2006.169.08:15:39.13#ibcon#read 4, iclass 12, count 0 2006.169.08:15:39.13#ibcon#about to read 5, iclass 12, count 0 2006.169.08:15:39.13#ibcon#read 5, iclass 12, count 0 2006.169.08:15:39.14#ibcon#about to read 6, iclass 12, count 0 2006.169.08:15:39.14#ibcon#read 6, iclass 12, count 0 2006.169.08:15:39.14#ibcon#end of sib2, iclass 12, count 0 2006.169.08:15:39.14#ibcon#*mode == 0, iclass 12, count 0 2006.169.08:15:39.14#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.169.08:15:39.14#ibcon#[27=USB\r\n] 2006.169.08:15:39.14#ibcon#*before write, iclass 12, count 0 2006.169.08:15:39.14#ibcon#enter sib2, iclass 12, count 0 2006.169.08:15:39.14#ibcon#flushed, iclass 12, count 0 2006.169.08:15:39.14#ibcon#about to write, iclass 12, count 0 2006.169.08:15:39.14#ibcon#wrote, iclass 12, count 0 2006.169.08:15:39.14#ibcon#about to read 3, iclass 12, count 0 2006.169.08:15:39.16#ibcon#read 3, iclass 12, count 0 2006.169.08:15:39.16#ibcon#about to read 4, iclass 12, count 0 2006.169.08:15:39.16#ibcon#read 4, iclass 12, count 0 2006.169.08:15:39.16#ibcon#about to read 5, iclass 12, count 0 2006.169.08:15:39.16#ibcon#read 5, iclass 12, count 0 2006.169.08:15:39.17#ibcon#about to read 6, iclass 12, count 0 2006.169.08:15:39.17#ibcon#read 6, iclass 12, count 0 2006.169.08:15:39.17#ibcon#end of sib2, iclass 12, count 0 2006.169.08:15:39.17#ibcon#*after write, iclass 12, count 0 2006.169.08:15:39.17#ibcon#*before return 0, iclass 12, count 0 2006.169.08:15:39.17#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.169.08:15:39.17#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.169.08:15:39.17#ibcon#about to clear, iclass 12 cls_cnt 0 2006.169.08:15:39.17#ibcon#cleared, iclass 12 cls_cnt 0 2006.169.08:15:39.17$vc4f8/vblo=6,752.99 2006.169.08:15:39.17#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.169.08:15:39.17#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.169.08:15:39.17#ibcon#ireg 17 cls_cnt 0 2006.169.08:15:39.17#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:15:39.17#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:15:39.17#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:15:39.17#ibcon#enter wrdev, iclass 14, count 0 2006.169.08:15:39.17#ibcon#first serial, iclass 14, count 0 2006.169.08:15:39.17#ibcon#enter sib2, iclass 14, count 0 2006.169.08:15:39.17#ibcon#flushed, iclass 14, count 0 2006.169.08:15:39.17#ibcon#about to write, iclass 14, count 0 2006.169.08:15:39.17#ibcon#wrote, iclass 14, count 0 2006.169.08:15:39.17#ibcon#about to read 3, iclass 14, count 0 2006.169.08:15:39.18#ibcon#read 3, iclass 14, count 0 2006.169.08:15:39.18#ibcon#about to read 4, iclass 14, count 0 2006.169.08:15:39.18#ibcon#read 4, iclass 14, count 0 2006.169.08:15:39.18#ibcon#about to read 5, iclass 14, count 0 2006.169.08:15:39.18#ibcon#read 5, iclass 14, count 0 2006.169.08:15:39.19#ibcon#about to read 6, iclass 14, count 0 2006.169.08:15:39.19#ibcon#read 6, iclass 14, count 0 2006.169.08:15:39.19#ibcon#end of sib2, iclass 14, count 0 2006.169.08:15:39.19#ibcon#*mode == 0, iclass 14, count 0 2006.169.08:15:39.19#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.169.08:15:39.19#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.08:15:39.19#ibcon#*before write, iclass 14, count 0 2006.169.08:15:39.19#ibcon#enter sib2, iclass 14, count 0 2006.169.08:15:39.19#ibcon#flushed, iclass 14, count 0 2006.169.08:15:39.19#ibcon#about to write, iclass 14, count 0 2006.169.08:15:39.19#ibcon#wrote, iclass 14, count 0 2006.169.08:15:39.19#ibcon#about to read 3, iclass 14, count 0 2006.169.08:15:39.22#ibcon#read 3, iclass 14, count 0 2006.169.08:15:39.22#ibcon#about to read 4, iclass 14, count 0 2006.169.08:15:39.22#ibcon#read 4, iclass 14, count 0 2006.169.08:15:39.22#ibcon#about to read 5, iclass 14, count 0 2006.169.08:15:39.22#ibcon#read 5, iclass 14, count 0 2006.169.08:15:39.23#ibcon#about to read 6, iclass 14, count 0 2006.169.08:15:39.23#ibcon#read 6, iclass 14, count 0 2006.169.08:15:39.23#ibcon#end of sib2, iclass 14, count 0 2006.169.08:15:39.23#ibcon#*after write, iclass 14, count 0 2006.169.08:15:39.23#ibcon#*before return 0, iclass 14, count 0 2006.169.08:15:39.23#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:15:39.23#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:15:39.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.169.08:15:39.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.169.08:15:39.23$vc4f8/vb=6,4 2006.169.08:15:39.23#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.169.08:15:39.23#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.169.08:15:39.23#ibcon#ireg 11 cls_cnt 2 2006.169.08:15:39.23#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.169.08:15:39.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.169.08:15:39.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.169.08:15:39.28#ibcon#enter wrdev, iclass 16, count 2 2006.169.08:15:39.28#ibcon#first serial, iclass 16, count 2 2006.169.08:15:39.28#ibcon#enter sib2, iclass 16, count 2 2006.169.08:15:39.28#ibcon#flushed, iclass 16, count 2 2006.169.08:15:39.28#ibcon#about to write, iclass 16, count 2 2006.169.08:15:39.29#ibcon#wrote, iclass 16, count 2 2006.169.08:15:39.29#ibcon#about to read 3, iclass 16, count 2 2006.169.08:15:39.30#ibcon#read 3, iclass 16, count 2 2006.169.08:15:39.31#ibcon#about to read 4, iclass 16, count 2 2006.169.08:15:39.31#ibcon#read 4, iclass 16, count 2 2006.169.08:15:39.31#ibcon#about to read 5, iclass 16, count 2 2006.169.08:15:39.31#ibcon#read 5, iclass 16, count 2 2006.169.08:15:39.31#ibcon#about to read 6, iclass 16, count 2 2006.169.08:15:39.31#ibcon#read 6, iclass 16, count 2 2006.169.08:15:39.31#ibcon#end of sib2, iclass 16, count 2 2006.169.08:15:39.31#ibcon#*mode == 0, iclass 16, count 2 2006.169.08:15:39.31#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.169.08:15:39.31#ibcon#[27=AT06-04\r\n] 2006.169.08:15:39.31#ibcon#*before write, iclass 16, count 2 2006.169.08:15:39.31#ibcon#enter sib2, iclass 16, count 2 2006.169.08:15:39.31#ibcon#flushed, iclass 16, count 2 2006.169.08:15:39.31#ibcon#about to write, iclass 16, count 2 2006.169.08:15:39.31#ibcon#wrote, iclass 16, count 2 2006.169.08:15:39.31#ibcon#about to read 3, iclass 16, count 2 2006.169.08:15:39.33#ibcon#read 3, iclass 16, count 2 2006.169.08:15:39.33#ibcon#about to read 4, iclass 16, count 2 2006.169.08:15:39.33#ibcon#read 4, iclass 16, count 2 2006.169.08:15:39.33#ibcon#about to read 5, iclass 16, count 2 2006.169.08:15:39.33#ibcon#read 5, iclass 16, count 2 2006.169.08:15:39.34#ibcon#about to read 6, iclass 16, count 2 2006.169.08:15:39.34#ibcon#read 6, iclass 16, count 2 2006.169.08:15:39.34#ibcon#end of sib2, iclass 16, count 2 2006.169.08:15:39.34#ibcon#*after write, iclass 16, count 2 2006.169.08:15:39.34#ibcon#*before return 0, iclass 16, count 2 2006.169.08:15:39.34#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.169.08:15:39.34#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.169.08:15:39.34#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.169.08:15:39.34#ibcon#ireg 7 cls_cnt 0 2006.169.08:15:39.34#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.169.08:15:39.45#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.169.08:15:39.45#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.169.08:15:39.45#ibcon#enter wrdev, iclass 16, count 0 2006.169.08:15:39.45#ibcon#first serial, iclass 16, count 0 2006.169.08:15:39.45#ibcon#enter sib2, iclass 16, count 0 2006.169.08:15:39.45#ibcon#flushed, iclass 16, count 0 2006.169.08:15:39.45#ibcon#about to write, iclass 16, count 0 2006.169.08:15:39.46#ibcon#wrote, iclass 16, count 0 2006.169.08:15:39.46#ibcon#about to read 3, iclass 16, count 0 2006.169.08:15:39.47#ibcon#read 3, iclass 16, count 0 2006.169.08:15:39.47#ibcon#about to read 4, iclass 16, count 0 2006.169.08:15:39.47#ibcon#read 4, iclass 16, count 0 2006.169.08:15:39.47#ibcon#about to read 5, iclass 16, count 0 2006.169.08:15:39.47#ibcon#read 5, iclass 16, count 0 2006.169.08:15:39.48#ibcon#about to read 6, iclass 16, count 0 2006.169.08:15:39.48#ibcon#read 6, iclass 16, count 0 2006.169.08:15:39.48#ibcon#end of sib2, iclass 16, count 0 2006.169.08:15:39.48#ibcon#*mode == 0, iclass 16, count 0 2006.169.08:15:39.48#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.169.08:15:39.48#ibcon#[27=USB\r\n] 2006.169.08:15:39.48#ibcon#*before write, iclass 16, count 0 2006.169.08:15:39.48#ibcon#enter sib2, iclass 16, count 0 2006.169.08:15:39.48#ibcon#flushed, iclass 16, count 0 2006.169.08:15:39.48#ibcon#about to write, iclass 16, count 0 2006.169.08:15:39.48#ibcon#wrote, iclass 16, count 0 2006.169.08:15:39.48#ibcon#about to read 3, iclass 16, count 0 2006.169.08:15:39.50#ibcon#read 3, iclass 16, count 0 2006.169.08:15:39.50#ibcon#about to read 4, iclass 16, count 0 2006.169.08:15:39.50#ibcon#read 4, iclass 16, count 0 2006.169.08:15:39.50#ibcon#about to read 5, iclass 16, count 0 2006.169.08:15:39.50#ibcon#read 5, iclass 16, count 0 2006.169.08:15:39.51#ibcon#about to read 6, iclass 16, count 0 2006.169.08:15:39.51#ibcon#read 6, iclass 16, count 0 2006.169.08:15:39.51#ibcon#end of sib2, iclass 16, count 0 2006.169.08:15:39.51#ibcon#*after write, iclass 16, count 0 2006.169.08:15:39.51#ibcon#*before return 0, iclass 16, count 0 2006.169.08:15:39.51#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.169.08:15:39.51#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.169.08:15:39.51#ibcon#about to clear, iclass 16 cls_cnt 0 2006.169.08:15:39.51#ibcon#cleared, iclass 16 cls_cnt 0 2006.169.08:15:39.51$vc4f8/vabw=wide 2006.169.08:15:39.51#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.169.08:15:39.51#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.169.08:15:39.51#ibcon#ireg 8 cls_cnt 0 2006.169.08:15:39.51#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:15:39.51#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:15:39.51#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:15:39.51#ibcon#enter wrdev, iclass 18, count 0 2006.169.08:15:39.51#ibcon#first serial, iclass 18, count 0 2006.169.08:15:39.51#ibcon#enter sib2, iclass 18, count 0 2006.169.08:15:39.51#ibcon#flushed, iclass 18, count 0 2006.169.08:15:39.51#ibcon#about to write, iclass 18, count 0 2006.169.08:15:39.51#ibcon#wrote, iclass 18, count 0 2006.169.08:15:39.51#ibcon#about to read 3, iclass 18, count 0 2006.169.08:15:39.52#ibcon#read 3, iclass 18, count 0 2006.169.08:15:39.52#ibcon#about to read 4, iclass 18, count 0 2006.169.08:15:39.52#ibcon#read 4, iclass 18, count 0 2006.169.08:15:39.52#ibcon#about to read 5, iclass 18, count 0 2006.169.08:15:39.52#ibcon#read 5, iclass 18, count 0 2006.169.08:15:39.52#ibcon#about to read 6, iclass 18, count 0 2006.169.08:15:39.53#ibcon#read 6, iclass 18, count 0 2006.169.08:15:39.53#ibcon#end of sib2, iclass 18, count 0 2006.169.08:15:39.53#ibcon#*mode == 0, iclass 18, count 0 2006.169.08:15:39.53#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.169.08:15:39.53#ibcon#[25=BW32\r\n] 2006.169.08:15:39.53#ibcon#*before write, iclass 18, count 0 2006.169.08:15:39.53#ibcon#enter sib2, iclass 18, count 0 2006.169.08:15:39.53#ibcon#flushed, iclass 18, count 0 2006.169.08:15:39.53#ibcon#about to write, iclass 18, count 0 2006.169.08:15:39.53#ibcon#wrote, iclass 18, count 0 2006.169.08:15:39.53#ibcon#about to read 3, iclass 18, count 0 2006.169.08:15:39.55#ibcon#read 3, iclass 18, count 0 2006.169.08:15:39.55#ibcon#about to read 4, iclass 18, count 0 2006.169.08:15:39.55#ibcon#read 4, iclass 18, count 0 2006.169.08:15:39.55#ibcon#about to read 5, iclass 18, count 0 2006.169.08:15:39.56#ibcon#read 5, iclass 18, count 0 2006.169.08:15:39.56#ibcon#about to read 6, iclass 18, count 0 2006.169.08:15:39.56#ibcon#read 6, iclass 18, count 0 2006.169.08:15:39.56#ibcon#end of sib2, iclass 18, count 0 2006.169.08:15:39.56#ibcon#*after write, iclass 18, count 0 2006.169.08:15:39.56#ibcon#*before return 0, iclass 18, count 0 2006.169.08:15:39.56#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:15:39.56#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:15:39.56#ibcon#about to clear, iclass 18 cls_cnt 0 2006.169.08:15:39.56#ibcon#cleared, iclass 18 cls_cnt 0 2006.169.08:15:39.56$vc4f8/vbbw=wide 2006.169.08:15:39.56#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.169.08:15:39.56#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.169.08:15:39.56#ibcon#ireg 8 cls_cnt 0 2006.169.08:15:39.56#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:15:39.62#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:15:39.62#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:15:39.62#ibcon#enter wrdev, iclass 20, count 0 2006.169.08:15:39.62#ibcon#first serial, iclass 20, count 0 2006.169.08:15:39.62#ibcon#enter sib2, iclass 20, count 0 2006.169.08:15:39.63#ibcon#flushed, iclass 20, count 0 2006.169.08:15:39.63#ibcon#about to write, iclass 20, count 0 2006.169.08:15:39.63#ibcon#wrote, iclass 20, count 0 2006.169.08:15:39.63#ibcon#about to read 3, iclass 20, count 0 2006.169.08:15:39.64#ibcon#read 3, iclass 20, count 0 2006.169.08:15:39.64#ibcon#about to read 4, iclass 20, count 0 2006.169.08:15:39.65#ibcon#read 4, iclass 20, count 0 2006.169.08:15:39.65#ibcon#about to read 5, iclass 20, count 0 2006.169.08:15:39.65#ibcon#read 5, iclass 20, count 0 2006.169.08:15:39.65#ibcon#about to read 6, iclass 20, count 0 2006.169.08:15:39.65#ibcon#read 6, iclass 20, count 0 2006.169.08:15:39.65#ibcon#end of sib2, iclass 20, count 0 2006.169.08:15:39.65#ibcon#*mode == 0, iclass 20, count 0 2006.169.08:15:39.65#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.169.08:15:39.65#ibcon#[27=BW32\r\n] 2006.169.08:15:39.65#ibcon#*before write, iclass 20, count 0 2006.169.08:15:39.65#ibcon#enter sib2, iclass 20, count 0 2006.169.08:15:39.65#ibcon#flushed, iclass 20, count 0 2006.169.08:15:39.65#ibcon#about to write, iclass 20, count 0 2006.169.08:15:39.65#ibcon#wrote, iclass 20, count 0 2006.169.08:15:39.65#ibcon#about to read 3, iclass 20, count 0 2006.169.08:15:39.67#ibcon#read 3, iclass 20, count 0 2006.169.08:15:39.67#ibcon#about to read 4, iclass 20, count 0 2006.169.08:15:39.67#ibcon#read 4, iclass 20, count 0 2006.169.08:15:39.67#ibcon#about to read 5, iclass 20, count 0 2006.169.08:15:39.67#ibcon#read 5, iclass 20, count 0 2006.169.08:15:39.68#ibcon#about to read 6, iclass 20, count 0 2006.169.08:15:39.68#ibcon#read 6, iclass 20, count 0 2006.169.08:15:39.68#ibcon#end of sib2, iclass 20, count 0 2006.169.08:15:39.68#ibcon#*after write, iclass 20, count 0 2006.169.08:15:39.68#ibcon#*before return 0, iclass 20, count 0 2006.169.08:15:39.68#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:15:39.68#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:15:39.68#ibcon#about to clear, iclass 20 cls_cnt 0 2006.169.08:15:39.68#ibcon#cleared, iclass 20 cls_cnt 0 2006.169.08:15:39.68$4f8m12a/ifd4f 2006.169.08:15:39.68$ifd4f/lo= 2006.169.08:15:39.68$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.08:15:39.68$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.08:15:39.68$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.08:15:39.68$ifd4f/patch= 2006.169.08:15:39.68$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.08:15:39.68$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.08:15:39.68$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.08:15:39.68$4f8m12a/"form=m,16.000,1:2 2006.169.08:15:39.68$4f8m12a/"tpicd 2006.169.08:15:39.68$4f8m12a/echo=off 2006.169.08:15:39.68$4f8m12a/xlog=off 2006.169.08:15:39.68:!2006.169.08:15:50 2006.169.08:15:50.02:preob 2006.169.08:15:51.15/onsource/TRACKING 2006.169.08:15:51.15:!2006.169.08:16:00 2006.169.08:16:00.02:data_valid=on 2006.169.08:16:00.02:midob 2006.169.08:16:01.15/onsource/TRACKING 2006.169.08:16:01.15/wx/18.12,1003.9,100 2006.169.08:16:01.24/cable/+6.5308E-03 2006.169.08:16:02.33/va/01,08,usb,yes,44,46 2006.169.08:16:02.33/va/02,07,usb,yes,45,47 2006.169.08:16:02.33/va/03,06,usb,yes,47,48 2006.169.08:16:02.33/va/04,07,usb,yes,46,49 2006.169.08:16:02.33/va/05,07,usb,yes,50,53 2006.169.08:16:02.33/va/06,06,usb,yes,50,49 2006.169.08:16:02.33/va/07,06,usb,yes,50,50 2006.169.08:16:02.34/va/08,07,usb,yes,48,47 2006.169.08:16:02.56/valo/01,532.99,yes,locked 2006.169.08:16:02.56/valo/02,572.99,yes,locked 2006.169.08:16:02.57/valo/03,672.99,yes,locked 2006.169.08:16:02.57/valo/04,832.99,yes,locked 2006.169.08:16:02.57/valo/05,652.99,yes,locked 2006.169.08:16:02.57/valo/06,772.99,yes,locked 2006.169.08:16:02.57/valo/07,832.99,yes,locked 2006.169.08:16:02.57/valo/08,852.99,yes,locked 2006.169.08:16:03.65/vb/01,04,usb,yes,30,28 2006.169.08:16:03.65/vb/02,04,usb,yes,31,33 2006.169.08:16:03.65/vb/03,04,usb,yes,28,31 2006.169.08:16:03.65/vb/04,04,usb,yes,29,29 2006.169.08:16:03.65/vb/05,04,usb,yes,27,31 2006.169.08:16:03.65/vb/06,04,usb,yes,28,31 2006.169.08:16:03.65/vb/07,04,usb,yes,30,30 2006.169.08:16:03.66/vb/08,04,usb,yes,28,31 2006.169.08:16:03.88/vblo/01,632.99,yes,locked 2006.169.08:16:03.88/vblo/02,640.99,yes,locked 2006.169.08:16:03.88/vblo/03,656.99,yes,locked 2006.169.08:16:03.88/vblo/04,712.99,yes,locked 2006.169.08:16:03.88/vblo/05,744.99,yes,locked 2006.169.08:16:03.88/vblo/06,752.99,yes,locked 2006.169.08:16:03.88/vblo/07,734.99,yes,locked 2006.169.08:16:03.89/vblo/08,744.99,yes,locked 2006.169.08:16:04.03/vabw/8 2006.169.08:16:04.18/vbbw/8 2006.169.08:16:04.27/xfe/off,on,14.2 2006.169.08:16:04.65/ifatt/23,28,28,28 2006.169.08:16:05.07/fmout-gps/S +4.17E-07 2006.169.08:16:05.16:!2006.169.08:17:00 2006.169.08:17:00.02:data_valid=off 2006.169.08:17:00.02:postob 2006.169.08:17:00.10/cable/+6.5299E-03 2006.169.08:17:00.11/wx/18.11,1003.9,100 2006.169.08:17:01.07/fmout-gps/S +4.18E-07 2006.169.08:17:01.08:scan_name=169-0820,k06169,130 2006.169.08:17:01.08:source=0722+145,072516.81,142513.7,2000.0,ccw 2006.169.08:17:02.15#flagr#flagr/antenna,new-source 2006.169.08:17:02.15:checkk5 2006.169.08:17:02.53/chk_autoobs//k5ts1/ autoobs is running! 2006.169.08:17:02.91/chk_autoobs//k5ts2/ autoobs is running! 2006.169.08:17:06.93/chk_autoobs//k5ts3?ERROR: timeout happened! 2006.169.08:17:07.31/chk_autoobs//k5ts4/ autoobs is running! 2006.169.08:17:07.68/chk_obsdata//k5ts1/T1690816??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.169.08:17:08.04/chk_obsdata//k5ts2/T1690816??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.169.08:17:15.11/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.08:17:15.48/chk_obsdata//k5ts4/T1690816??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.169.08:17:16.18/k5log//k5ts1_log_newline 2006.169.08:17:16.87/k5log//k5ts2_log_newline 2006.169.08:17:23.98/k5log//k5ts3?ERROR: timeout happened! 2006.169.08:17:24.68/k5log//k5ts4_log_newline 2006.169.08:17:24.84/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.08:17:24.84:4f8m12a=3 2006.169.08:17:24.84$4f8m12a/echo=on 2006.169.08:17:24.84$4f8m12a/pcalon 2006.169.08:17:24.84$pcalon/"no phase cal control is implemented here 2006.169.08:17:24.84$4f8m12a/"tpicd=stop 2006.169.08:17:24.84$4f8m12a/vc4f8 2006.169.08:17:24.84$vc4f8/valo=1,532.99 2006.169.08:17:24.84#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.169.08:17:24.84#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.169.08:17:24.84#ibcon#ireg 17 cls_cnt 0 2006.169.08:17:24.84#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:17:24.84#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:17:24.84#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:17:24.84#ibcon#enter wrdev, iclass 27, count 0 2006.169.08:17:24.84#ibcon#first serial, iclass 27, count 0 2006.169.08:17:24.84#ibcon#enter sib2, iclass 27, count 0 2006.169.08:17:24.84#ibcon#flushed, iclass 27, count 0 2006.169.08:17:24.84#ibcon#about to write, iclass 27, count 0 2006.169.08:17:24.84#ibcon#wrote, iclass 27, count 0 2006.169.08:17:24.84#ibcon#about to read 3, iclass 27, count 0 2006.169.08:17:24.85#ibcon#read 3, iclass 27, count 0 2006.169.08:17:24.85#ibcon#about to read 4, iclass 27, count 0 2006.169.08:17:24.85#ibcon#read 4, iclass 27, count 0 2006.169.08:17:24.85#ibcon#about to read 5, iclass 27, count 0 2006.169.08:17:24.85#ibcon#read 5, iclass 27, count 0 2006.169.08:17:24.85#ibcon#about to read 6, iclass 27, count 0 2006.169.08:17:24.85#ibcon#read 6, iclass 27, count 0 2006.169.08:17:24.85#ibcon#end of sib2, iclass 27, count 0 2006.169.08:17:24.85#ibcon#*mode == 0, iclass 27, count 0 2006.169.08:17:24.85#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.169.08:17:24.85#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.08:17:24.85#ibcon#*before write, iclass 27, count 0 2006.169.08:17:24.85#ibcon#enter sib2, iclass 27, count 0 2006.169.08:17:24.85#ibcon#flushed, iclass 27, count 0 2006.169.08:17:24.85#ibcon#about to write, iclass 27, count 0 2006.169.08:17:24.85#ibcon#wrote, iclass 27, count 0 2006.169.08:17:24.85#ibcon#about to read 3, iclass 27, count 0 2006.169.08:17:24.91#ibcon#read 3, iclass 27, count 0 2006.169.08:17:24.91#ibcon#about to read 4, iclass 27, count 0 2006.169.08:17:24.91#ibcon#read 4, iclass 27, count 0 2006.169.08:17:24.91#ibcon#about to read 5, iclass 27, count 0 2006.169.08:17:24.91#ibcon#read 5, iclass 27, count 0 2006.169.08:17:24.91#ibcon#about to read 6, iclass 27, count 0 2006.169.08:17:24.91#ibcon#read 6, iclass 27, count 0 2006.169.08:17:24.91#ibcon#end of sib2, iclass 27, count 0 2006.169.08:17:24.91#ibcon#*after write, iclass 27, count 0 2006.169.08:17:24.91#ibcon#*before return 0, iclass 27, count 0 2006.169.08:17:24.91#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:17:24.91#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:17:24.91#ibcon#about to clear, iclass 27 cls_cnt 0 2006.169.08:17:24.91#ibcon#cleared, iclass 27 cls_cnt 0 2006.169.08:17:24.91$vc4f8/va=1,8 2006.169.08:17:24.91#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.169.08:17:24.91#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.169.08:17:24.91#ibcon#ireg 11 cls_cnt 2 2006.169.08:17:24.91#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:17:24.91#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:17:24.91#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:17:24.91#ibcon#enter wrdev, iclass 29, count 2 2006.169.08:17:24.91#ibcon#first serial, iclass 29, count 2 2006.169.08:17:24.91#ibcon#enter sib2, iclass 29, count 2 2006.169.08:17:24.91#ibcon#flushed, iclass 29, count 2 2006.169.08:17:24.91#ibcon#about to write, iclass 29, count 2 2006.169.08:17:24.91#ibcon#wrote, iclass 29, count 2 2006.169.08:17:24.91#ibcon#about to read 3, iclass 29, count 2 2006.169.08:17:24.92#ibcon#read 3, iclass 29, count 2 2006.169.08:17:24.92#ibcon#about to read 4, iclass 29, count 2 2006.169.08:17:24.92#ibcon#read 4, iclass 29, count 2 2006.169.08:17:24.92#ibcon#about to read 5, iclass 29, count 2 2006.169.08:17:24.92#ibcon#read 5, iclass 29, count 2 2006.169.08:17:24.92#ibcon#about to read 6, iclass 29, count 2 2006.169.08:17:24.92#ibcon#read 6, iclass 29, count 2 2006.169.08:17:24.92#ibcon#end of sib2, iclass 29, count 2 2006.169.08:17:24.92#ibcon#*mode == 0, iclass 29, count 2 2006.169.08:17:24.92#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.169.08:17:24.92#ibcon#[25=AT01-08\r\n] 2006.169.08:17:24.92#ibcon#*before write, iclass 29, count 2 2006.169.08:17:24.92#ibcon#enter sib2, iclass 29, count 2 2006.169.08:17:24.92#ibcon#flushed, iclass 29, count 2 2006.169.08:17:24.92#ibcon#about to write, iclass 29, count 2 2006.169.08:17:24.92#ibcon#wrote, iclass 29, count 2 2006.169.08:17:24.92#ibcon#about to read 3, iclass 29, count 2 2006.169.08:17:24.95#ibcon#read 3, iclass 29, count 2 2006.169.08:17:24.95#ibcon#about to read 4, iclass 29, count 2 2006.169.08:17:24.95#ibcon#read 4, iclass 29, count 2 2006.169.08:17:24.95#ibcon#about to read 5, iclass 29, count 2 2006.169.08:17:24.95#ibcon#read 5, iclass 29, count 2 2006.169.08:17:24.95#ibcon#about to read 6, iclass 29, count 2 2006.169.08:17:24.95#ibcon#read 6, iclass 29, count 2 2006.169.08:17:24.95#ibcon#end of sib2, iclass 29, count 2 2006.169.08:17:24.95#ibcon#*after write, iclass 29, count 2 2006.169.08:17:24.95#ibcon#*before return 0, iclass 29, count 2 2006.169.08:17:24.95#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:17:24.95#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:17:24.95#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.169.08:17:24.95#ibcon#ireg 7 cls_cnt 0 2006.169.08:17:24.95#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:17:25.07#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:17:25.07#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:17:25.07#ibcon#enter wrdev, iclass 29, count 0 2006.169.08:17:25.07#ibcon#first serial, iclass 29, count 0 2006.169.08:17:25.07#ibcon#enter sib2, iclass 29, count 0 2006.169.08:17:25.07#ibcon#flushed, iclass 29, count 0 2006.169.08:17:25.07#ibcon#about to write, iclass 29, count 0 2006.169.08:17:25.07#ibcon#wrote, iclass 29, count 0 2006.169.08:17:25.07#ibcon#about to read 3, iclass 29, count 0 2006.169.08:17:25.11#ibcon#read 3, iclass 29, count 0 2006.169.08:17:25.11#ibcon#about to read 4, iclass 29, count 0 2006.169.08:17:25.11#ibcon#read 4, iclass 29, count 0 2006.169.08:17:25.11#ibcon#about to read 5, iclass 29, count 0 2006.169.08:17:25.11#ibcon#read 5, iclass 29, count 0 2006.169.08:17:25.11#ibcon#about to read 6, iclass 29, count 0 2006.169.08:17:25.11#ibcon#read 6, iclass 29, count 0 2006.169.08:17:25.11#ibcon#end of sib2, iclass 29, count 0 2006.169.08:17:25.11#ibcon#*mode == 0, iclass 29, count 0 2006.169.08:17:25.11#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.169.08:17:25.11#ibcon#[25=USB\r\n] 2006.169.08:17:25.11#ibcon#*before write, iclass 29, count 0 2006.169.08:17:25.11#ibcon#enter sib2, iclass 29, count 0 2006.169.08:17:25.11#ibcon#flushed, iclass 29, count 0 2006.169.08:17:25.11#ibcon#about to write, iclass 29, count 0 2006.169.08:17:25.12#ibcon#wrote, iclass 29, count 0 2006.169.08:17:25.12#ibcon#about to read 3, iclass 29, count 0 2006.169.08:17:25.14#ibcon#read 3, iclass 29, count 0 2006.169.08:17:25.14#ibcon#about to read 4, iclass 29, count 0 2006.169.08:17:25.14#ibcon#read 4, iclass 29, count 0 2006.169.08:17:25.14#ibcon#about to read 5, iclass 29, count 0 2006.169.08:17:25.14#ibcon#read 5, iclass 29, count 0 2006.169.08:17:25.14#ibcon#about to read 6, iclass 29, count 0 2006.169.08:17:25.14#ibcon#read 6, iclass 29, count 0 2006.169.08:17:25.14#ibcon#end of sib2, iclass 29, count 0 2006.169.08:17:25.14#ibcon#*after write, iclass 29, count 0 2006.169.08:17:25.14#ibcon#*before return 0, iclass 29, count 0 2006.169.08:17:25.14#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:17:25.14#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:17:25.14#ibcon#about to clear, iclass 29 cls_cnt 0 2006.169.08:17:25.14#ibcon#cleared, iclass 29 cls_cnt 0 2006.169.08:17:25.14$vc4f8/valo=2,572.99 2006.169.08:17:25.15#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.169.08:17:25.15#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.169.08:17:25.15#ibcon#ireg 17 cls_cnt 0 2006.169.08:17:25.15#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:17:25.15#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:17:25.15#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:17:25.15#ibcon#enter wrdev, iclass 31, count 0 2006.169.08:17:25.15#ibcon#first serial, iclass 31, count 0 2006.169.08:17:25.15#ibcon#enter sib2, iclass 31, count 0 2006.169.08:17:25.15#ibcon#flushed, iclass 31, count 0 2006.169.08:17:25.15#ibcon#about to write, iclass 31, count 0 2006.169.08:17:25.15#ibcon#wrote, iclass 31, count 0 2006.169.08:17:25.15#ibcon#about to read 3, iclass 31, count 0 2006.169.08:17:25.16#ibcon#read 3, iclass 31, count 0 2006.169.08:17:25.16#ibcon#about to read 4, iclass 31, count 0 2006.169.08:17:25.16#ibcon#read 4, iclass 31, count 0 2006.169.08:17:25.16#ibcon#about to read 5, iclass 31, count 0 2006.169.08:17:25.16#ibcon#read 5, iclass 31, count 0 2006.169.08:17:25.16#ibcon#about to read 6, iclass 31, count 0 2006.169.08:17:25.16#ibcon#read 6, iclass 31, count 0 2006.169.08:17:25.16#ibcon#end of sib2, iclass 31, count 0 2006.169.08:17:25.16#ibcon#*mode == 0, iclass 31, count 0 2006.169.08:17:25.16#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.169.08:17:25.16#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.08:17:25.16#ibcon#*before write, iclass 31, count 0 2006.169.08:17:25.16#ibcon#enter sib2, iclass 31, count 0 2006.169.08:17:25.16#ibcon#flushed, iclass 31, count 0 2006.169.08:17:25.16#ibcon#about to write, iclass 31, count 0 2006.169.08:17:25.16#ibcon#wrote, iclass 31, count 0 2006.169.08:17:25.16#ibcon#about to read 3, iclass 31, count 0 2006.169.08:17:25.21#ibcon#read 3, iclass 31, count 0 2006.169.08:17:25.21#ibcon#about to read 4, iclass 31, count 0 2006.169.08:17:25.21#ibcon#read 4, iclass 31, count 0 2006.169.08:17:25.21#ibcon#about to read 5, iclass 31, count 0 2006.169.08:17:25.21#ibcon#read 5, iclass 31, count 0 2006.169.08:17:25.21#ibcon#about to read 6, iclass 31, count 0 2006.169.08:17:25.21#ibcon#read 6, iclass 31, count 0 2006.169.08:17:25.21#ibcon#end of sib2, iclass 31, count 0 2006.169.08:17:25.21#ibcon#*after write, iclass 31, count 0 2006.169.08:17:25.21#ibcon#*before return 0, iclass 31, count 0 2006.169.08:17:25.21#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:17:25.21#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:17:25.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.169.08:17:25.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.169.08:17:25.21$vc4f8/va=2,7 2006.169.08:17:25.21#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.169.08:17:25.21#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.169.08:17:25.21#ibcon#ireg 11 cls_cnt 2 2006.169.08:17:25.21#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:17:25.21#abcon#<5=/05 3.6 7.0 18.111001003.9\r\n> 2006.169.08:17:25.23#abcon#{5=INTERFACE CLEAR} 2006.169.08:17:25.25#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:17:25.25#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:17:25.25#ibcon#enter wrdev, iclass 34, count 2 2006.169.08:17:25.25#ibcon#first serial, iclass 34, count 2 2006.169.08:17:25.25#ibcon#enter sib2, iclass 34, count 2 2006.169.08:17:25.25#ibcon#flushed, iclass 34, count 2 2006.169.08:17:25.25#ibcon#about to write, iclass 34, count 2 2006.169.08:17:25.25#ibcon#wrote, iclass 34, count 2 2006.169.08:17:25.25#ibcon#about to read 3, iclass 34, count 2 2006.169.08:17:25.27#ibcon#read 3, iclass 34, count 2 2006.169.08:17:25.27#ibcon#about to read 4, iclass 34, count 2 2006.169.08:17:25.27#ibcon#read 4, iclass 34, count 2 2006.169.08:17:25.27#ibcon#about to read 5, iclass 34, count 2 2006.169.08:17:25.27#ibcon#read 5, iclass 34, count 2 2006.169.08:17:25.27#ibcon#about to read 6, iclass 34, count 2 2006.169.08:17:25.27#ibcon#read 6, iclass 34, count 2 2006.169.08:17:25.27#ibcon#end of sib2, iclass 34, count 2 2006.169.08:17:25.27#ibcon#*mode == 0, iclass 34, count 2 2006.169.08:17:25.27#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.169.08:17:25.27#ibcon#[25=AT02-07\r\n] 2006.169.08:17:25.27#ibcon#*before write, iclass 34, count 2 2006.169.08:17:25.27#ibcon#enter sib2, iclass 34, count 2 2006.169.08:17:25.27#ibcon#flushed, iclass 34, count 2 2006.169.08:17:25.27#ibcon#about to write, iclass 34, count 2 2006.169.08:17:25.27#ibcon#wrote, iclass 34, count 2 2006.169.08:17:25.27#ibcon#about to read 3, iclass 34, count 2 2006.169.08:17:25.30#abcon#[5=S1D000X0/0*\r\n] 2006.169.08:17:25.30#ibcon#read 3, iclass 34, count 2 2006.169.08:17:25.30#ibcon#about to read 4, iclass 34, count 2 2006.169.08:17:25.30#ibcon#read 4, iclass 34, count 2 2006.169.08:17:25.30#ibcon#about to read 5, iclass 34, count 2 2006.169.08:17:25.30#ibcon#read 5, iclass 34, count 2 2006.169.08:17:25.30#ibcon#about to read 6, iclass 34, count 2 2006.169.08:17:25.30#ibcon#read 6, iclass 34, count 2 2006.169.08:17:25.30#ibcon#end of sib2, iclass 34, count 2 2006.169.08:17:25.30#ibcon#*after write, iclass 34, count 2 2006.169.08:17:25.30#ibcon#*before return 0, iclass 34, count 2 2006.169.08:17:25.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:17:25.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:17:25.30#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.169.08:17:25.30#ibcon#ireg 7 cls_cnt 0 2006.169.08:17:25.30#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:17:25.42#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:17:25.42#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:17:25.42#ibcon#enter wrdev, iclass 34, count 0 2006.169.08:17:25.42#ibcon#first serial, iclass 34, count 0 2006.169.08:17:25.42#ibcon#enter sib2, iclass 34, count 0 2006.169.08:17:25.42#ibcon#flushed, iclass 34, count 0 2006.169.08:17:25.42#ibcon#about to write, iclass 34, count 0 2006.169.08:17:25.42#ibcon#wrote, iclass 34, count 0 2006.169.08:17:25.42#ibcon#about to read 3, iclass 34, count 0 2006.169.08:17:25.44#ibcon#read 3, iclass 34, count 0 2006.169.08:17:25.44#ibcon#about to read 4, iclass 34, count 0 2006.169.08:17:25.44#ibcon#read 4, iclass 34, count 0 2006.169.08:17:25.44#ibcon#about to read 5, iclass 34, count 0 2006.169.08:17:25.44#ibcon#read 5, iclass 34, count 0 2006.169.08:17:25.44#ibcon#about to read 6, iclass 34, count 0 2006.169.08:17:25.44#ibcon#read 6, iclass 34, count 0 2006.169.08:17:25.44#ibcon#end of sib2, iclass 34, count 0 2006.169.08:17:25.44#ibcon#*mode == 0, iclass 34, count 0 2006.169.08:17:25.44#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.169.08:17:25.44#ibcon#[25=USB\r\n] 2006.169.08:17:25.44#ibcon#*before write, iclass 34, count 0 2006.169.08:17:25.44#ibcon#enter sib2, iclass 34, count 0 2006.169.08:17:25.44#ibcon#flushed, iclass 34, count 0 2006.169.08:17:25.44#ibcon#about to write, iclass 34, count 0 2006.169.08:17:25.44#ibcon#wrote, iclass 34, count 0 2006.169.08:17:25.44#ibcon#about to read 3, iclass 34, count 0 2006.169.08:17:25.47#ibcon#read 3, iclass 34, count 0 2006.169.08:17:25.47#ibcon#about to read 4, iclass 34, count 0 2006.169.08:17:25.47#ibcon#read 4, iclass 34, count 0 2006.169.08:17:25.47#ibcon#about to read 5, iclass 34, count 0 2006.169.08:17:25.47#ibcon#read 5, iclass 34, count 0 2006.169.08:17:25.47#ibcon#about to read 6, iclass 34, count 0 2006.169.08:17:25.47#ibcon#read 6, iclass 34, count 0 2006.169.08:17:25.47#ibcon#end of sib2, iclass 34, count 0 2006.169.08:17:25.47#ibcon#*after write, iclass 34, count 0 2006.169.08:17:25.47#ibcon#*before return 0, iclass 34, count 0 2006.169.08:17:25.47#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:17:25.47#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:17:25.47#ibcon#about to clear, iclass 34 cls_cnt 0 2006.169.08:17:25.47#ibcon#cleared, iclass 34 cls_cnt 0 2006.169.08:17:25.47$vc4f8/valo=3,672.99 2006.169.08:17:25.48#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.169.08:17:25.48#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.169.08:17:25.48#ibcon#ireg 17 cls_cnt 0 2006.169.08:17:25.48#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:17:25.48#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:17:25.48#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:17:25.48#ibcon#enter wrdev, iclass 39, count 0 2006.169.08:17:25.48#ibcon#first serial, iclass 39, count 0 2006.169.08:17:25.48#ibcon#enter sib2, iclass 39, count 0 2006.169.08:17:25.48#ibcon#flushed, iclass 39, count 0 2006.169.08:17:25.48#ibcon#about to write, iclass 39, count 0 2006.169.08:17:25.48#ibcon#wrote, iclass 39, count 0 2006.169.08:17:25.48#ibcon#about to read 3, iclass 39, count 0 2006.169.08:17:25.49#ibcon#read 3, iclass 39, count 0 2006.169.08:17:25.49#ibcon#about to read 4, iclass 39, count 0 2006.169.08:17:25.49#ibcon#read 4, iclass 39, count 0 2006.169.08:17:25.49#ibcon#about to read 5, iclass 39, count 0 2006.169.08:17:25.49#ibcon#read 5, iclass 39, count 0 2006.169.08:17:25.49#ibcon#about to read 6, iclass 39, count 0 2006.169.08:17:25.49#ibcon#read 6, iclass 39, count 0 2006.169.08:17:25.49#ibcon#end of sib2, iclass 39, count 0 2006.169.08:17:25.49#ibcon#*mode == 0, iclass 39, count 0 2006.169.08:17:25.49#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.169.08:17:25.49#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.08:17:25.49#ibcon#*before write, iclass 39, count 0 2006.169.08:17:25.49#ibcon#enter sib2, iclass 39, count 0 2006.169.08:17:25.49#ibcon#flushed, iclass 39, count 0 2006.169.08:17:25.49#ibcon#about to write, iclass 39, count 0 2006.169.08:17:25.49#ibcon#wrote, iclass 39, count 0 2006.169.08:17:25.49#ibcon#about to read 3, iclass 39, count 0 2006.169.08:17:25.54#ibcon#read 3, iclass 39, count 0 2006.169.08:17:25.54#ibcon#about to read 4, iclass 39, count 0 2006.169.08:17:25.54#ibcon#read 4, iclass 39, count 0 2006.169.08:17:25.54#ibcon#about to read 5, iclass 39, count 0 2006.169.08:17:25.54#ibcon#read 5, iclass 39, count 0 2006.169.08:17:25.54#ibcon#about to read 6, iclass 39, count 0 2006.169.08:17:25.54#ibcon#read 6, iclass 39, count 0 2006.169.08:17:25.54#ibcon#end of sib2, iclass 39, count 0 2006.169.08:17:25.54#ibcon#*after write, iclass 39, count 0 2006.169.08:17:25.54#ibcon#*before return 0, iclass 39, count 0 2006.169.08:17:25.54#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:17:25.54#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:17:25.54#ibcon#about to clear, iclass 39 cls_cnt 0 2006.169.08:17:25.54#ibcon#cleared, iclass 39 cls_cnt 0 2006.169.08:17:25.54$vc4f8/va=3,6 2006.169.08:17:25.54#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.169.08:17:25.54#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.169.08:17:25.54#ibcon#ireg 11 cls_cnt 2 2006.169.08:17:25.54#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:17:25.58#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:17:25.58#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:17:25.58#ibcon#enter wrdev, iclass 3, count 2 2006.169.08:17:25.58#ibcon#first serial, iclass 3, count 2 2006.169.08:17:25.58#ibcon#enter sib2, iclass 3, count 2 2006.169.08:17:25.58#ibcon#flushed, iclass 3, count 2 2006.169.08:17:25.58#ibcon#about to write, iclass 3, count 2 2006.169.08:17:25.58#ibcon#wrote, iclass 3, count 2 2006.169.08:17:25.58#ibcon#about to read 3, iclass 3, count 2 2006.169.08:17:25.60#ibcon#read 3, iclass 3, count 2 2006.169.08:17:25.60#ibcon#about to read 4, iclass 3, count 2 2006.169.08:17:25.60#ibcon#read 4, iclass 3, count 2 2006.169.08:17:25.60#ibcon#about to read 5, iclass 3, count 2 2006.169.08:17:25.60#ibcon#read 5, iclass 3, count 2 2006.169.08:17:25.60#ibcon#about to read 6, iclass 3, count 2 2006.169.08:17:25.60#ibcon#read 6, iclass 3, count 2 2006.169.08:17:25.60#ibcon#end of sib2, iclass 3, count 2 2006.169.08:17:25.60#ibcon#*mode == 0, iclass 3, count 2 2006.169.08:17:25.60#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.169.08:17:25.60#ibcon#[25=AT03-06\r\n] 2006.169.08:17:25.60#ibcon#*before write, iclass 3, count 2 2006.169.08:17:25.60#ibcon#enter sib2, iclass 3, count 2 2006.169.08:17:25.60#ibcon#flushed, iclass 3, count 2 2006.169.08:17:25.60#ibcon#about to write, iclass 3, count 2 2006.169.08:17:25.60#ibcon#wrote, iclass 3, count 2 2006.169.08:17:25.60#ibcon#about to read 3, iclass 3, count 2 2006.169.08:17:25.63#ibcon#read 3, iclass 3, count 2 2006.169.08:17:25.63#ibcon#about to read 4, iclass 3, count 2 2006.169.08:17:25.63#ibcon#read 4, iclass 3, count 2 2006.169.08:17:25.63#ibcon#about to read 5, iclass 3, count 2 2006.169.08:17:25.63#ibcon#read 5, iclass 3, count 2 2006.169.08:17:25.63#ibcon#about to read 6, iclass 3, count 2 2006.169.08:17:25.63#ibcon#read 6, iclass 3, count 2 2006.169.08:17:25.63#ibcon#end of sib2, iclass 3, count 2 2006.169.08:17:25.63#ibcon#*after write, iclass 3, count 2 2006.169.08:17:25.63#ibcon#*before return 0, iclass 3, count 2 2006.169.08:17:25.63#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:17:25.63#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:17:25.63#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.169.08:17:25.63#ibcon#ireg 7 cls_cnt 0 2006.169.08:17:25.63#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:17:25.75#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:17:25.75#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:17:25.75#ibcon#enter wrdev, iclass 3, count 0 2006.169.08:17:25.75#ibcon#first serial, iclass 3, count 0 2006.169.08:17:25.75#ibcon#enter sib2, iclass 3, count 0 2006.169.08:17:25.75#ibcon#flushed, iclass 3, count 0 2006.169.08:17:25.75#ibcon#about to write, iclass 3, count 0 2006.169.08:17:25.75#ibcon#wrote, iclass 3, count 0 2006.169.08:17:25.75#ibcon#about to read 3, iclass 3, count 0 2006.169.08:17:25.77#ibcon#read 3, iclass 3, count 0 2006.169.08:17:25.77#ibcon#about to read 4, iclass 3, count 0 2006.169.08:17:25.77#ibcon#read 4, iclass 3, count 0 2006.169.08:17:25.77#ibcon#about to read 5, iclass 3, count 0 2006.169.08:17:25.77#ibcon#read 5, iclass 3, count 0 2006.169.08:17:25.77#ibcon#about to read 6, iclass 3, count 0 2006.169.08:17:25.77#ibcon#read 6, iclass 3, count 0 2006.169.08:17:25.77#ibcon#end of sib2, iclass 3, count 0 2006.169.08:17:25.77#ibcon#*mode == 0, iclass 3, count 0 2006.169.08:17:25.77#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.169.08:17:25.77#ibcon#[25=USB\r\n] 2006.169.08:17:25.77#ibcon#*before write, iclass 3, count 0 2006.169.08:17:25.77#ibcon#enter sib2, iclass 3, count 0 2006.169.08:17:25.77#ibcon#flushed, iclass 3, count 0 2006.169.08:17:25.77#ibcon#about to write, iclass 3, count 0 2006.169.08:17:25.77#ibcon#wrote, iclass 3, count 0 2006.169.08:17:25.77#ibcon#about to read 3, iclass 3, count 0 2006.169.08:17:25.80#ibcon#read 3, iclass 3, count 0 2006.169.08:17:25.80#ibcon#about to read 4, iclass 3, count 0 2006.169.08:17:25.80#ibcon#read 4, iclass 3, count 0 2006.169.08:17:25.80#ibcon#about to read 5, iclass 3, count 0 2006.169.08:17:25.80#ibcon#read 5, iclass 3, count 0 2006.169.08:17:25.80#ibcon#about to read 6, iclass 3, count 0 2006.169.08:17:25.80#ibcon#read 6, iclass 3, count 0 2006.169.08:17:25.80#ibcon#end of sib2, iclass 3, count 0 2006.169.08:17:25.80#ibcon#*after write, iclass 3, count 0 2006.169.08:17:25.80#ibcon#*before return 0, iclass 3, count 0 2006.169.08:17:25.80#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:17:25.80#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:17:25.80#ibcon#about to clear, iclass 3 cls_cnt 0 2006.169.08:17:25.80#ibcon#cleared, iclass 3 cls_cnt 0 2006.169.08:17:25.80$vc4f8/valo=4,832.99 2006.169.08:17:25.81#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.169.08:17:25.81#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.169.08:17:25.81#ibcon#ireg 17 cls_cnt 0 2006.169.08:17:25.81#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:17:25.81#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:17:25.81#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:17:25.81#ibcon#enter wrdev, iclass 5, count 0 2006.169.08:17:25.81#ibcon#first serial, iclass 5, count 0 2006.169.08:17:25.81#ibcon#enter sib2, iclass 5, count 0 2006.169.08:17:25.81#ibcon#flushed, iclass 5, count 0 2006.169.08:17:25.81#ibcon#about to write, iclass 5, count 0 2006.169.08:17:25.81#ibcon#wrote, iclass 5, count 0 2006.169.08:17:25.81#ibcon#about to read 3, iclass 5, count 0 2006.169.08:17:25.82#ibcon#read 3, iclass 5, count 0 2006.169.08:17:25.82#ibcon#about to read 4, iclass 5, count 0 2006.169.08:17:25.82#ibcon#read 4, iclass 5, count 0 2006.169.08:17:25.82#ibcon#about to read 5, iclass 5, count 0 2006.169.08:17:25.82#ibcon#read 5, iclass 5, count 0 2006.169.08:17:25.82#ibcon#about to read 6, iclass 5, count 0 2006.169.08:17:25.82#ibcon#read 6, iclass 5, count 0 2006.169.08:17:25.82#ibcon#end of sib2, iclass 5, count 0 2006.169.08:17:25.82#ibcon#*mode == 0, iclass 5, count 0 2006.169.08:17:25.82#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.169.08:17:25.82#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.08:17:25.82#ibcon#*before write, iclass 5, count 0 2006.169.08:17:25.82#ibcon#enter sib2, iclass 5, count 0 2006.169.08:17:25.82#ibcon#flushed, iclass 5, count 0 2006.169.08:17:25.82#ibcon#about to write, iclass 5, count 0 2006.169.08:17:25.82#ibcon#wrote, iclass 5, count 0 2006.169.08:17:25.82#ibcon#about to read 3, iclass 5, count 0 2006.169.08:17:25.86#ibcon#read 3, iclass 5, count 0 2006.169.08:17:25.86#ibcon#about to read 4, iclass 5, count 0 2006.169.08:17:25.86#ibcon#read 4, iclass 5, count 0 2006.169.08:17:25.86#ibcon#about to read 5, iclass 5, count 0 2006.169.08:17:25.86#ibcon#read 5, iclass 5, count 0 2006.169.08:17:25.86#ibcon#about to read 6, iclass 5, count 0 2006.169.08:17:25.86#ibcon#read 6, iclass 5, count 0 2006.169.08:17:25.86#ibcon#end of sib2, iclass 5, count 0 2006.169.08:17:25.86#ibcon#*after write, iclass 5, count 0 2006.169.08:17:25.86#ibcon#*before return 0, iclass 5, count 0 2006.169.08:17:25.86#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:17:25.86#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:17:25.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.169.08:17:25.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.169.08:17:25.86$vc4f8/va=4,7 2006.169.08:17:25.87#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.169.08:17:25.87#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.169.08:17:25.87#ibcon#ireg 11 cls_cnt 2 2006.169.08:17:25.87#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:17:25.91#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:17:25.91#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:17:25.91#ibcon#enter wrdev, iclass 7, count 2 2006.169.08:17:25.91#ibcon#first serial, iclass 7, count 2 2006.169.08:17:25.91#ibcon#enter sib2, iclass 7, count 2 2006.169.08:17:25.91#ibcon#flushed, iclass 7, count 2 2006.169.08:17:25.91#ibcon#about to write, iclass 7, count 2 2006.169.08:17:25.91#ibcon#wrote, iclass 7, count 2 2006.169.08:17:25.91#ibcon#about to read 3, iclass 7, count 2 2006.169.08:17:25.93#ibcon#read 3, iclass 7, count 2 2006.169.08:17:25.93#ibcon#about to read 4, iclass 7, count 2 2006.169.08:17:25.93#ibcon#read 4, iclass 7, count 2 2006.169.08:17:25.93#ibcon#about to read 5, iclass 7, count 2 2006.169.08:17:25.93#ibcon#read 5, iclass 7, count 2 2006.169.08:17:25.93#ibcon#about to read 6, iclass 7, count 2 2006.169.08:17:25.93#ibcon#read 6, iclass 7, count 2 2006.169.08:17:25.93#ibcon#end of sib2, iclass 7, count 2 2006.169.08:17:25.93#ibcon#*mode == 0, iclass 7, count 2 2006.169.08:17:25.93#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.169.08:17:25.93#ibcon#[25=AT04-07\r\n] 2006.169.08:17:25.93#ibcon#*before write, iclass 7, count 2 2006.169.08:17:25.93#ibcon#enter sib2, iclass 7, count 2 2006.169.08:17:25.93#ibcon#flushed, iclass 7, count 2 2006.169.08:17:25.93#ibcon#about to write, iclass 7, count 2 2006.169.08:17:25.93#ibcon#wrote, iclass 7, count 2 2006.169.08:17:25.93#ibcon#about to read 3, iclass 7, count 2 2006.169.08:17:25.96#ibcon#read 3, iclass 7, count 2 2006.169.08:17:25.96#ibcon#about to read 4, iclass 7, count 2 2006.169.08:17:25.96#ibcon#read 4, iclass 7, count 2 2006.169.08:17:25.96#ibcon#about to read 5, iclass 7, count 2 2006.169.08:17:25.96#ibcon#read 5, iclass 7, count 2 2006.169.08:17:25.96#ibcon#about to read 6, iclass 7, count 2 2006.169.08:17:25.96#ibcon#read 6, iclass 7, count 2 2006.169.08:17:25.96#ibcon#end of sib2, iclass 7, count 2 2006.169.08:17:25.96#ibcon#*after write, iclass 7, count 2 2006.169.08:17:25.96#ibcon#*before return 0, iclass 7, count 2 2006.169.08:17:25.96#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:17:25.96#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:17:25.96#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.169.08:17:25.96#ibcon#ireg 7 cls_cnt 0 2006.169.08:17:25.96#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:17:26.08#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:17:26.08#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:17:26.08#ibcon#enter wrdev, iclass 7, count 0 2006.169.08:17:26.08#ibcon#first serial, iclass 7, count 0 2006.169.08:17:26.08#ibcon#enter sib2, iclass 7, count 0 2006.169.08:17:26.08#ibcon#flushed, iclass 7, count 0 2006.169.08:17:26.08#ibcon#about to write, iclass 7, count 0 2006.169.08:17:26.08#ibcon#wrote, iclass 7, count 0 2006.169.08:17:26.08#ibcon#about to read 3, iclass 7, count 0 2006.169.08:17:26.10#ibcon#read 3, iclass 7, count 0 2006.169.08:17:26.10#ibcon#about to read 4, iclass 7, count 0 2006.169.08:17:26.10#ibcon#read 4, iclass 7, count 0 2006.169.08:17:26.10#ibcon#about to read 5, iclass 7, count 0 2006.169.08:17:26.10#ibcon#read 5, iclass 7, count 0 2006.169.08:17:26.10#ibcon#about to read 6, iclass 7, count 0 2006.169.08:17:26.10#ibcon#read 6, iclass 7, count 0 2006.169.08:17:26.10#ibcon#end of sib2, iclass 7, count 0 2006.169.08:17:26.10#ibcon#*mode == 0, iclass 7, count 0 2006.169.08:17:26.10#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.169.08:17:26.10#ibcon#[25=USB\r\n] 2006.169.08:17:26.10#ibcon#*before write, iclass 7, count 0 2006.169.08:17:26.10#ibcon#enter sib2, iclass 7, count 0 2006.169.08:17:26.10#ibcon#flushed, iclass 7, count 0 2006.169.08:17:26.10#ibcon#about to write, iclass 7, count 0 2006.169.08:17:26.10#ibcon#wrote, iclass 7, count 0 2006.169.08:17:26.10#ibcon#about to read 3, iclass 7, count 0 2006.169.08:17:26.13#ibcon#read 3, iclass 7, count 0 2006.169.08:17:26.13#ibcon#about to read 4, iclass 7, count 0 2006.169.08:17:26.13#ibcon#read 4, iclass 7, count 0 2006.169.08:17:26.13#ibcon#about to read 5, iclass 7, count 0 2006.169.08:17:26.13#ibcon#read 5, iclass 7, count 0 2006.169.08:17:26.13#ibcon#about to read 6, iclass 7, count 0 2006.169.08:17:26.13#ibcon#read 6, iclass 7, count 0 2006.169.08:17:26.13#ibcon#end of sib2, iclass 7, count 0 2006.169.08:17:26.13#ibcon#*after write, iclass 7, count 0 2006.169.08:17:26.13#ibcon#*before return 0, iclass 7, count 0 2006.169.08:17:26.13#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:17:26.13#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:17:26.13#ibcon#about to clear, iclass 7 cls_cnt 0 2006.169.08:17:26.13#ibcon#cleared, iclass 7 cls_cnt 0 2006.169.08:17:26.13$vc4f8/valo=5,652.99 2006.169.08:17:26.14#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.169.08:17:26.14#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.169.08:17:26.14#ibcon#ireg 17 cls_cnt 0 2006.169.08:17:26.14#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:17:26.14#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:17:26.14#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:17:26.14#ibcon#enter wrdev, iclass 11, count 0 2006.169.08:17:26.14#ibcon#first serial, iclass 11, count 0 2006.169.08:17:26.14#ibcon#enter sib2, iclass 11, count 0 2006.169.08:17:26.14#ibcon#flushed, iclass 11, count 0 2006.169.08:17:26.14#ibcon#about to write, iclass 11, count 0 2006.169.08:17:26.14#ibcon#wrote, iclass 11, count 0 2006.169.08:17:26.14#ibcon#about to read 3, iclass 11, count 0 2006.169.08:17:26.15#ibcon#read 3, iclass 11, count 0 2006.169.08:17:26.15#ibcon#about to read 4, iclass 11, count 0 2006.169.08:17:26.15#ibcon#read 4, iclass 11, count 0 2006.169.08:17:26.15#ibcon#about to read 5, iclass 11, count 0 2006.169.08:17:26.15#ibcon#read 5, iclass 11, count 0 2006.169.08:17:26.15#ibcon#about to read 6, iclass 11, count 0 2006.169.08:17:26.15#ibcon#read 6, iclass 11, count 0 2006.169.08:17:26.15#ibcon#end of sib2, iclass 11, count 0 2006.169.08:17:26.15#ibcon#*mode == 0, iclass 11, count 0 2006.169.08:17:26.15#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.169.08:17:26.15#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.08:17:26.15#ibcon#*before write, iclass 11, count 0 2006.169.08:17:26.15#ibcon#enter sib2, iclass 11, count 0 2006.169.08:17:26.15#ibcon#flushed, iclass 11, count 0 2006.169.08:17:26.15#ibcon#about to write, iclass 11, count 0 2006.169.08:17:26.15#ibcon#wrote, iclass 11, count 0 2006.169.08:17:26.15#ibcon#about to read 3, iclass 11, count 0 2006.169.08:17:26.19#ibcon#read 3, iclass 11, count 0 2006.169.08:17:26.19#ibcon#about to read 4, iclass 11, count 0 2006.169.08:17:26.19#ibcon#read 4, iclass 11, count 0 2006.169.08:17:26.19#ibcon#about to read 5, iclass 11, count 0 2006.169.08:17:26.19#ibcon#read 5, iclass 11, count 0 2006.169.08:17:26.19#ibcon#about to read 6, iclass 11, count 0 2006.169.08:17:26.19#ibcon#read 6, iclass 11, count 0 2006.169.08:17:26.19#ibcon#end of sib2, iclass 11, count 0 2006.169.08:17:26.19#ibcon#*after write, iclass 11, count 0 2006.169.08:17:26.19#ibcon#*before return 0, iclass 11, count 0 2006.169.08:17:26.19#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:17:26.19#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:17:26.19#ibcon#about to clear, iclass 11 cls_cnt 0 2006.169.08:17:26.19#ibcon#cleared, iclass 11 cls_cnt 0 2006.169.08:17:26.19$vc4f8/va=5,7 2006.169.08:17:26.20#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.169.08:17:26.20#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.169.08:17:26.20#ibcon#ireg 11 cls_cnt 2 2006.169.08:17:26.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:17:26.24#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:17:26.24#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:17:26.24#ibcon#enter wrdev, iclass 13, count 2 2006.169.08:17:26.24#ibcon#first serial, iclass 13, count 2 2006.169.08:17:26.24#ibcon#enter sib2, iclass 13, count 2 2006.169.08:17:26.24#ibcon#flushed, iclass 13, count 2 2006.169.08:17:26.24#ibcon#about to write, iclass 13, count 2 2006.169.08:17:26.24#ibcon#wrote, iclass 13, count 2 2006.169.08:17:26.24#ibcon#about to read 3, iclass 13, count 2 2006.169.08:17:26.26#ibcon#read 3, iclass 13, count 2 2006.169.08:17:26.26#ibcon#about to read 4, iclass 13, count 2 2006.169.08:17:26.26#ibcon#read 4, iclass 13, count 2 2006.169.08:17:26.26#ibcon#about to read 5, iclass 13, count 2 2006.169.08:17:26.26#ibcon#read 5, iclass 13, count 2 2006.169.08:17:26.26#ibcon#about to read 6, iclass 13, count 2 2006.169.08:17:26.26#ibcon#read 6, iclass 13, count 2 2006.169.08:17:26.26#ibcon#end of sib2, iclass 13, count 2 2006.169.08:17:26.26#ibcon#*mode == 0, iclass 13, count 2 2006.169.08:17:26.26#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.169.08:17:26.26#ibcon#[25=AT05-07\r\n] 2006.169.08:17:26.26#ibcon#*before write, iclass 13, count 2 2006.169.08:17:26.26#ibcon#enter sib2, iclass 13, count 2 2006.169.08:17:26.26#ibcon#flushed, iclass 13, count 2 2006.169.08:17:26.26#ibcon#about to write, iclass 13, count 2 2006.169.08:17:26.26#ibcon#wrote, iclass 13, count 2 2006.169.08:17:26.26#ibcon#about to read 3, iclass 13, count 2 2006.169.08:17:26.29#ibcon#read 3, iclass 13, count 2 2006.169.08:17:26.29#ibcon#about to read 4, iclass 13, count 2 2006.169.08:17:26.29#ibcon#read 4, iclass 13, count 2 2006.169.08:17:26.29#ibcon#about to read 5, iclass 13, count 2 2006.169.08:17:26.29#ibcon#read 5, iclass 13, count 2 2006.169.08:17:26.29#ibcon#about to read 6, iclass 13, count 2 2006.169.08:17:26.29#ibcon#read 6, iclass 13, count 2 2006.169.08:17:26.29#ibcon#end of sib2, iclass 13, count 2 2006.169.08:17:26.29#ibcon#*after write, iclass 13, count 2 2006.169.08:17:26.29#ibcon#*before return 0, iclass 13, count 2 2006.169.08:17:26.29#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:17:26.29#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:17:26.29#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.169.08:17:26.29#ibcon#ireg 7 cls_cnt 0 2006.169.08:17:26.29#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:17:26.41#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:17:26.41#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:17:26.41#ibcon#enter wrdev, iclass 13, count 0 2006.169.08:17:26.41#ibcon#first serial, iclass 13, count 0 2006.169.08:17:26.41#ibcon#enter sib2, iclass 13, count 0 2006.169.08:17:26.41#ibcon#flushed, iclass 13, count 0 2006.169.08:17:26.41#ibcon#about to write, iclass 13, count 0 2006.169.08:17:26.41#ibcon#wrote, iclass 13, count 0 2006.169.08:17:26.41#ibcon#about to read 3, iclass 13, count 0 2006.169.08:17:26.43#ibcon#read 3, iclass 13, count 0 2006.169.08:17:26.43#ibcon#about to read 4, iclass 13, count 0 2006.169.08:17:26.43#ibcon#read 4, iclass 13, count 0 2006.169.08:17:26.43#ibcon#about to read 5, iclass 13, count 0 2006.169.08:17:26.43#ibcon#read 5, iclass 13, count 0 2006.169.08:17:26.43#ibcon#about to read 6, iclass 13, count 0 2006.169.08:17:26.43#ibcon#read 6, iclass 13, count 0 2006.169.08:17:26.43#ibcon#end of sib2, iclass 13, count 0 2006.169.08:17:26.43#ibcon#*mode == 0, iclass 13, count 0 2006.169.08:17:26.43#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.08:17:26.43#ibcon#[25=USB\r\n] 2006.169.08:17:26.43#ibcon#*before write, iclass 13, count 0 2006.169.08:17:26.43#ibcon#enter sib2, iclass 13, count 0 2006.169.08:17:26.43#ibcon#flushed, iclass 13, count 0 2006.169.08:17:26.43#ibcon#about to write, iclass 13, count 0 2006.169.08:17:26.43#ibcon#wrote, iclass 13, count 0 2006.169.08:17:26.43#ibcon#about to read 3, iclass 13, count 0 2006.169.08:17:26.46#ibcon#read 3, iclass 13, count 0 2006.169.08:17:26.46#ibcon#about to read 4, iclass 13, count 0 2006.169.08:17:26.46#ibcon#read 4, iclass 13, count 0 2006.169.08:17:26.46#ibcon#about to read 5, iclass 13, count 0 2006.169.08:17:26.46#ibcon#read 5, iclass 13, count 0 2006.169.08:17:26.46#ibcon#about to read 6, iclass 13, count 0 2006.169.08:17:26.46#ibcon#read 6, iclass 13, count 0 2006.169.08:17:26.46#ibcon#end of sib2, iclass 13, count 0 2006.169.08:17:26.46#ibcon#*after write, iclass 13, count 0 2006.169.08:17:26.46#ibcon#*before return 0, iclass 13, count 0 2006.169.08:17:26.46#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:17:26.46#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:17:26.46#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.08:17:26.46#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.08:17:26.46$vc4f8/valo=6,772.99 2006.169.08:17:26.47#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.169.08:17:26.47#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.169.08:17:26.47#ibcon#ireg 17 cls_cnt 0 2006.169.08:17:26.47#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:17:26.47#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:17:26.47#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:17:26.47#ibcon#enter wrdev, iclass 15, count 0 2006.169.08:17:26.47#ibcon#first serial, iclass 15, count 0 2006.169.08:17:26.47#ibcon#enter sib2, iclass 15, count 0 2006.169.08:17:26.47#ibcon#flushed, iclass 15, count 0 2006.169.08:17:26.47#ibcon#about to write, iclass 15, count 0 2006.169.08:17:26.47#ibcon#wrote, iclass 15, count 0 2006.169.08:17:26.47#ibcon#about to read 3, iclass 15, count 0 2006.169.08:17:26.48#ibcon#read 3, iclass 15, count 0 2006.169.08:17:26.48#ibcon#about to read 4, iclass 15, count 0 2006.169.08:17:26.48#ibcon#read 4, iclass 15, count 0 2006.169.08:17:26.48#ibcon#about to read 5, iclass 15, count 0 2006.169.08:17:26.48#ibcon#read 5, iclass 15, count 0 2006.169.08:17:26.48#ibcon#about to read 6, iclass 15, count 0 2006.169.08:17:26.48#ibcon#read 6, iclass 15, count 0 2006.169.08:17:26.48#ibcon#end of sib2, iclass 15, count 0 2006.169.08:17:26.48#ibcon#*mode == 0, iclass 15, count 0 2006.169.08:17:26.48#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.169.08:17:26.48#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.08:17:26.48#ibcon#*before write, iclass 15, count 0 2006.169.08:17:26.48#ibcon#enter sib2, iclass 15, count 0 2006.169.08:17:26.48#ibcon#flushed, iclass 15, count 0 2006.169.08:17:26.48#ibcon#about to write, iclass 15, count 0 2006.169.08:17:26.48#ibcon#wrote, iclass 15, count 0 2006.169.08:17:26.48#ibcon#about to read 3, iclass 15, count 0 2006.169.08:17:26.52#ibcon#read 3, iclass 15, count 0 2006.169.08:17:26.52#ibcon#about to read 4, iclass 15, count 0 2006.169.08:17:26.52#ibcon#read 4, iclass 15, count 0 2006.169.08:17:26.52#ibcon#about to read 5, iclass 15, count 0 2006.169.08:17:26.52#ibcon#read 5, iclass 15, count 0 2006.169.08:17:26.52#ibcon#about to read 6, iclass 15, count 0 2006.169.08:17:26.52#ibcon#read 6, iclass 15, count 0 2006.169.08:17:26.52#ibcon#end of sib2, iclass 15, count 0 2006.169.08:17:26.52#ibcon#*after write, iclass 15, count 0 2006.169.08:17:26.52#ibcon#*before return 0, iclass 15, count 0 2006.169.08:17:26.52#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:17:26.52#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:17:26.52#ibcon#about to clear, iclass 15 cls_cnt 0 2006.169.08:17:26.52#ibcon#cleared, iclass 15 cls_cnt 0 2006.169.08:17:26.52$vc4f8/va=6,6 2006.169.08:17:26.53#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.169.08:17:26.53#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.169.08:17:26.53#ibcon#ireg 11 cls_cnt 2 2006.169.08:17:26.53#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:17:26.57#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:17:26.57#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:17:26.57#ibcon#enter wrdev, iclass 17, count 2 2006.169.08:17:26.57#ibcon#first serial, iclass 17, count 2 2006.169.08:17:26.57#ibcon#enter sib2, iclass 17, count 2 2006.169.08:17:26.57#ibcon#flushed, iclass 17, count 2 2006.169.08:17:26.57#ibcon#about to write, iclass 17, count 2 2006.169.08:17:26.57#ibcon#wrote, iclass 17, count 2 2006.169.08:17:26.57#ibcon#about to read 3, iclass 17, count 2 2006.169.08:17:26.59#ibcon#read 3, iclass 17, count 2 2006.169.08:17:26.59#ibcon#about to read 4, iclass 17, count 2 2006.169.08:17:26.59#ibcon#read 4, iclass 17, count 2 2006.169.08:17:26.59#ibcon#about to read 5, iclass 17, count 2 2006.169.08:17:26.59#ibcon#read 5, iclass 17, count 2 2006.169.08:17:26.59#ibcon#about to read 6, iclass 17, count 2 2006.169.08:17:26.59#ibcon#read 6, iclass 17, count 2 2006.169.08:17:26.59#ibcon#end of sib2, iclass 17, count 2 2006.169.08:17:26.59#ibcon#*mode == 0, iclass 17, count 2 2006.169.08:17:26.59#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.169.08:17:26.59#ibcon#[25=AT06-06\r\n] 2006.169.08:17:26.59#ibcon#*before write, iclass 17, count 2 2006.169.08:17:26.59#ibcon#enter sib2, iclass 17, count 2 2006.169.08:17:26.59#ibcon#flushed, iclass 17, count 2 2006.169.08:17:26.59#ibcon#about to write, iclass 17, count 2 2006.169.08:17:26.59#ibcon#wrote, iclass 17, count 2 2006.169.08:17:26.59#ibcon#about to read 3, iclass 17, count 2 2006.169.08:17:26.62#ibcon#read 3, iclass 17, count 2 2006.169.08:17:26.62#ibcon#about to read 4, iclass 17, count 2 2006.169.08:17:26.62#ibcon#read 4, iclass 17, count 2 2006.169.08:17:26.62#ibcon#about to read 5, iclass 17, count 2 2006.169.08:17:26.62#ibcon#read 5, iclass 17, count 2 2006.169.08:17:26.62#ibcon#about to read 6, iclass 17, count 2 2006.169.08:17:26.62#ibcon#read 6, iclass 17, count 2 2006.169.08:17:26.62#ibcon#end of sib2, iclass 17, count 2 2006.169.08:17:26.62#ibcon#*after write, iclass 17, count 2 2006.169.08:17:26.62#ibcon#*before return 0, iclass 17, count 2 2006.169.08:17:26.62#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:17:26.62#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:17:26.62#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.169.08:17:26.62#ibcon#ireg 7 cls_cnt 0 2006.169.08:17:26.62#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:17:26.74#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:17:26.74#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:17:26.74#ibcon#enter wrdev, iclass 17, count 0 2006.169.08:17:26.74#ibcon#first serial, iclass 17, count 0 2006.169.08:17:26.74#ibcon#enter sib2, iclass 17, count 0 2006.169.08:17:26.74#ibcon#flushed, iclass 17, count 0 2006.169.08:17:26.74#ibcon#about to write, iclass 17, count 0 2006.169.08:17:26.74#ibcon#wrote, iclass 17, count 0 2006.169.08:17:26.74#ibcon#about to read 3, iclass 17, count 0 2006.169.08:17:26.76#ibcon#read 3, iclass 17, count 0 2006.169.08:17:26.76#ibcon#about to read 4, iclass 17, count 0 2006.169.08:17:26.76#ibcon#read 4, iclass 17, count 0 2006.169.08:17:26.76#ibcon#about to read 5, iclass 17, count 0 2006.169.08:17:26.76#ibcon#read 5, iclass 17, count 0 2006.169.08:17:26.76#ibcon#about to read 6, iclass 17, count 0 2006.169.08:17:26.76#ibcon#read 6, iclass 17, count 0 2006.169.08:17:26.76#ibcon#end of sib2, iclass 17, count 0 2006.169.08:17:26.76#ibcon#*mode == 0, iclass 17, count 0 2006.169.08:17:26.76#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.169.08:17:26.76#ibcon#[25=USB\r\n] 2006.169.08:17:26.76#ibcon#*before write, iclass 17, count 0 2006.169.08:17:26.76#ibcon#enter sib2, iclass 17, count 0 2006.169.08:17:26.76#ibcon#flushed, iclass 17, count 0 2006.169.08:17:26.76#ibcon#about to write, iclass 17, count 0 2006.169.08:17:26.76#ibcon#wrote, iclass 17, count 0 2006.169.08:17:26.76#ibcon#about to read 3, iclass 17, count 0 2006.169.08:17:26.79#ibcon#read 3, iclass 17, count 0 2006.169.08:17:26.79#ibcon#about to read 4, iclass 17, count 0 2006.169.08:17:26.79#ibcon#read 4, iclass 17, count 0 2006.169.08:17:26.79#ibcon#about to read 5, iclass 17, count 0 2006.169.08:17:26.79#ibcon#read 5, iclass 17, count 0 2006.169.08:17:26.79#ibcon#about to read 6, iclass 17, count 0 2006.169.08:17:26.79#ibcon#read 6, iclass 17, count 0 2006.169.08:17:26.79#ibcon#end of sib2, iclass 17, count 0 2006.169.08:17:26.79#ibcon#*after write, iclass 17, count 0 2006.169.08:17:26.79#ibcon#*before return 0, iclass 17, count 0 2006.169.08:17:26.79#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:17:26.79#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:17:26.79#ibcon#about to clear, iclass 17 cls_cnt 0 2006.169.08:17:26.79#ibcon#cleared, iclass 17 cls_cnt 0 2006.169.08:17:26.79$vc4f8/valo=7,832.99 2006.169.08:17:26.80#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.169.08:17:26.80#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.169.08:17:26.80#ibcon#ireg 17 cls_cnt 0 2006.169.08:17:26.80#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.169.08:17:26.80#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.169.08:17:26.80#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.169.08:17:26.80#ibcon#enter wrdev, iclass 19, count 0 2006.169.08:17:26.80#ibcon#first serial, iclass 19, count 0 2006.169.08:17:26.80#ibcon#enter sib2, iclass 19, count 0 2006.169.08:17:26.80#ibcon#flushed, iclass 19, count 0 2006.169.08:17:26.80#ibcon#about to write, iclass 19, count 0 2006.169.08:17:26.80#ibcon#wrote, iclass 19, count 0 2006.169.08:17:26.80#ibcon#about to read 3, iclass 19, count 0 2006.169.08:17:26.81#ibcon#read 3, iclass 19, count 0 2006.169.08:17:26.81#ibcon#about to read 4, iclass 19, count 0 2006.169.08:17:26.81#ibcon#read 4, iclass 19, count 0 2006.169.08:17:26.81#ibcon#about to read 5, iclass 19, count 0 2006.169.08:17:26.81#ibcon#read 5, iclass 19, count 0 2006.169.08:17:26.81#ibcon#about to read 6, iclass 19, count 0 2006.169.08:17:26.81#ibcon#read 6, iclass 19, count 0 2006.169.08:17:26.81#ibcon#end of sib2, iclass 19, count 0 2006.169.08:17:26.81#ibcon#*mode == 0, iclass 19, count 0 2006.169.08:17:26.81#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.169.08:17:26.81#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.08:17:26.81#ibcon#*before write, iclass 19, count 0 2006.169.08:17:26.81#ibcon#enter sib2, iclass 19, count 0 2006.169.08:17:26.81#ibcon#flushed, iclass 19, count 0 2006.169.08:17:26.81#ibcon#about to write, iclass 19, count 0 2006.169.08:17:26.81#ibcon#wrote, iclass 19, count 0 2006.169.08:17:26.81#ibcon#about to read 3, iclass 19, count 0 2006.169.08:17:26.85#ibcon#read 3, iclass 19, count 0 2006.169.08:17:26.85#ibcon#about to read 4, iclass 19, count 0 2006.169.08:17:26.85#ibcon#read 4, iclass 19, count 0 2006.169.08:17:26.85#ibcon#about to read 5, iclass 19, count 0 2006.169.08:17:26.85#ibcon#read 5, iclass 19, count 0 2006.169.08:17:26.85#ibcon#about to read 6, iclass 19, count 0 2006.169.08:17:26.85#ibcon#read 6, iclass 19, count 0 2006.169.08:17:26.85#ibcon#end of sib2, iclass 19, count 0 2006.169.08:17:26.85#ibcon#*after write, iclass 19, count 0 2006.169.08:17:26.85#ibcon#*before return 0, iclass 19, count 0 2006.169.08:17:26.85#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.169.08:17:26.85#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.169.08:17:26.85#ibcon#about to clear, iclass 19 cls_cnt 0 2006.169.08:17:26.85#ibcon#cleared, iclass 19 cls_cnt 0 2006.169.08:17:26.85$vc4f8/va=7,6 2006.169.08:17:26.86#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.169.08:17:26.86#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.169.08:17:26.86#ibcon#ireg 11 cls_cnt 2 2006.169.08:17:26.86#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.169.08:17:26.90#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.169.08:17:26.90#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.169.08:17:26.90#ibcon#enter wrdev, iclass 21, count 2 2006.169.08:17:26.90#ibcon#first serial, iclass 21, count 2 2006.169.08:17:26.90#ibcon#enter sib2, iclass 21, count 2 2006.169.08:17:26.90#ibcon#flushed, iclass 21, count 2 2006.169.08:17:26.90#ibcon#about to write, iclass 21, count 2 2006.169.08:17:26.90#ibcon#wrote, iclass 21, count 2 2006.169.08:17:26.90#ibcon#about to read 3, iclass 21, count 2 2006.169.08:17:26.92#ibcon#read 3, iclass 21, count 2 2006.169.08:17:26.92#ibcon#about to read 4, iclass 21, count 2 2006.169.08:17:26.92#ibcon#read 4, iclass 21, count 2 2006.169.08:17:26.92#ibcon#about to read 5, iclass 21, count 2 2006.169.08:17:26.92#ibcon#read 5, iclass 21, count 2 2006.169.08:17:26.92#ibcon#about to read 6, iclass 21, count 2 2006.169.08:17:26.92#ibcon#read 6, iclass 21, count 2 2006.169.08:17:26.92#ibcon#end of sib2, iclass 21, count 2 2006.169.08:17:26.92#ibcon#*mode == 0, iclass 21, count 2 2006.169.08:17:26.92#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.169.08:17:26.92#ibcon#[25=AT07-06\r\n] 2006.169.08:17:26.92#ibcon#*before write, iclass 21, count 2 2006.169.08:17:26.92#ibcon#enter sib2, iclass 21, count 2 2006.169.08:17:26.92#ibcon#flushed, iclass 21, count 2 2006.169.08:17:26.92#ibcon#about to write, iclass 21, count 2 2006.169.08:17:26.92#ibcon#wrote, iclass 21, count 2 2006.169.08:17:26.92#ibcon#about to read 3, iclass 21, count 2 2006.169.08:17:26.95#ibcon#read 3, iclass 21, count 2 2006.169.08:17:26.95#ibcon#about to read 4, iclass 21, count 2 2006.169.08:17:26.95#ibcon#read 4, iclass 21, count 2 2006.169.08:17:26.95#ibcon#about to read 5, iclass 21, count 2 2006.169.08:17:26.95#ibcon#read 5, iclass 21, count 2 2006.169.08:17:26.95#ibcon#about to read 6, iclass 21, count 2 2006.169.08:17:26.95#ibcon#read 6, iclass 21, count 2 2006.169.08:17:26.95#ibcon#end of sib2, iclass 21, count 2 2006.169.08:17:26.95#ibcon#*after write, iclass 21, count 2 2006.169.08:17:26.95#ibcon#*before return 0, iclass 21, count 2 2006.169.08:17:26.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.169.08:17:26.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.169.08:17:26.95#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.169.08:17:26.95#ibcon#ireg 7 cls_cnt 0 2006.169.08:17:26.95#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.169.08:17:27.07#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.169.08:17:27.07#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.169.08:17:27.07#ibcon#enter wrdev, iclass 21, count 0 2006.169.08:17:27.07#ibcon#first serial, iclass 21, count 0 2006.169.08:17:27.07#ibcon#enter sib2, iclass 21, count 0 2006.169.08:17:27.07#ibcon#flushed, iclass 21, count 0 2006.169.08:17:27.07#ibcon#about to write, iclass 21, count 0 2006.169.08:17:27.07#ibcon#wrote, iclass 21, count 0 2006.169.08:17:27.07#ibcon#about to read 3, iclass 21, count 0 2006.169.08:17:27.09#ibcon#read 3, iclass 21, count 0 2006.169.08:17:27.09#ibcon#about to read 4, iclass 21, count 0 2006.169.08:17:27.09#ibcon#read 4, iclass 21, count 0 2006.169.08:17:27.09#ibcon#about to read 5, iclass 21, count 0 2006.169.08:17:27.09#ibcon#read 5, iclass 21, count 0 2006.169.08:17:27.09#ibcon#about to read 6, iclass 21, count 0 2006.169.08:17:27.09#ibcon#read 6, iclass 21, count 0 2006.169.08:17:27.09#ibcon#end of sib2, iclass 21, count 0 2006.169.08:17:27.09#ibcon#*mode == 0, iclass 21, count 0 2006.169.08:17:27.09#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.169.08:17:27.09#ibcon#[25=USB\r\n] 2006.169.08:17:27.09#ibcon#*before write, iclass 21, count 0 2006.169.08:17:27.09#ibcon#enter sib2, iclass 21, count 0 2006.169.08:17:27.09#ibcon#flushed, iclass 21, count 0 2006.169.08:17:27.09#ibcon#about to write, iclass 21, count 0 2006.169.08:17:27.09#ibcon#wrote, iclass 21, count 0 2006.169.08:17:27.09#ibcon#about to read 3, iclass 21, count 0 2006.169.08:17:27.12#ibcon#read 3, iclass 21, count 0 2006.169.08:17:27.12#ibcon#about to read 4, iclass 21, count 0 2006.169.08:17:27.12#ibcon#read 4, iclass 21, count 0 2006.169.08:17:27.12#ibcon#about to read 5, iclass 21, count 0 2006.169.08:17:27.12#ibcon#read 5, iclass 21, count 0 2006.169.08:17:27.12#ibcon#about to read 6, iclass 21, count 0 2006.169.08:17:27.12#ibcon#read 6, iclass 21, count 0 2006.169.08:17:27.12#ibcon#end of sib2, iclass 21, count 0 2006.169.08:17:27.12#ibcon#*after write, iclass 21, count 0 2006.169.08:17:27.12#ibcon#*before return 0, iclass 21, count 0 2006.169.08:17:27.12#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.169.08:17:27.12#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.169.08:17:27.12#ibcon#about to clear, iclass 21 cls_cnt 0 2006.169.08:17:27.12#ibcon#cleared, iclass 21 cls_cnt 0 2006.169.08:17:27.12$vc4f8/valo=8,852.99 2006.169.08:17:27.13#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.169.08:17:27.13#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.169.08:17:27.13#ibcon#ireg 17 cls_cnt 0 2006.169.08:17:27.13#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:17:27.13#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:17:27.13#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:17:27.13#ibcon#enter wrdev, iclass 23, count 0 2006.169.08:17:27.13#ibcon#first serial, iclass 23, count 0 2006.169.08:17:27.13#ibcon#enter sib2, iclass 23, count 0 2006.169.08:17:27.13#ibcon#flushed, iclass 23, count 0 2006.169.08:17:27.13#ibcon#about to write, iclass 23, count 0 2006.169.08:17:27.13#ibcon#wrote, iclass 23, count 0 2006.169.08:17:27.13#ibcon#about to read 3, iclass 23, count 0 2006.169.08:17:27.14#ibcon#read 3, iclass 23, count 0 2006.169.08:17:27.14#ibcon#about to read 4, iclass 23, count 0 2006.169.08:17:27.14#ibcon#read 4, iclass 23, count 0 2006.169.08:17:27.14#ibcon#about to read 5, iclass 23, count 0 2006.169.08:17:27.14#ibcon#read 5, iclass 23, count 0 2006.169.08:17:27.14#ibcon#about to read 6, iclass 23, count 0 2006.169.08:17:27.14#ibcon#read 6, iclass 23, count 0 2006.169.08:17:27.14#ibcon#end of sib2, iclass 23, count 0 2006.169.08:17:27.14#ibcon#*mode == 0, iclass 23, count 0 2006.169.08:17:27.14#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.169.08:17:27.14#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.08:17:27.14#ibcon#*before write, iclass 23, count 0 2006.169.08:17:27.14#ibcon#enter sib2, iclass 23, count 0 2006.169.08:17:27.14#ibcon#flushed, iclass 23, count 0 2006.169.08:17:27.14#ibcon#about to write, iclass 23, count 0 2006.169.08:17:27.14#ibcon#wrote, iclass 23, count 0 2006.169.08:17:27.14#ibcon#about to read 3, iclass 23, count 0 2006.169.08:17:27.14#trakl#Source acquired 2006.169.08:17:27.18#ibcon#read 3, iclass 23, count 0 2006.169.08:17:27.18#ibcon#about to read 4, iclass 23, count 0 2006.169.08:17:27.18#ibcon#read 4, iclass 23, count 0 2006.169.08:17:27.18#ibcon#about to read 5, iclass 23, count 0 2006.169.08:17:27.18#ibcon#read 5, iclass 23, count 0 2006.169.08:17:27.18#ibcon#about to read 6, iclass 23, count 0 2006.169.08:17:27.18#ibcon#read 6, iclass 23, count 0 2006.169.08:17:27.18#ibcon#end of sib2, iclass 23, count 0 2006.169.08:17:27.18#ibcon#*after write, iclass 23, count 0 2006.169.08:17:27.18#ibcon#*before return 0, iclass 23, count 0 2006.169.08:17:27.18#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:17:27.18#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:17:27.18#ibcon#about to clear, iclass 23 cls_cnt 0 2006.169.08:17:27.18#ibcon#cleared, iclass 23 cls_cnt 0 2006.169.08:17:27.19$vc4f8/va=8,7 2006.169.08:17:27.19#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.169.08:17:27.19#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.169.08:17:27.19#ibcon#ireg 11 cls_cnt 2 2006.169.08:17:27.19#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:17:27.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:17:27.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:17:27.23#ibcon#enter wrdev, iclass 25, count 2 2006.169.08:17:27.23#ibcon#first serial, iclass 25, count 2 2006.169.08:17:27.23#ibcon#enter sib2, iclass 25, count 2 2006.169.08:17:27.23#ibcon#flushed, iclass 25, count 2 2006.169.08:17:27.23#ibcon#about to write, iclass 25, count 2 2006.169.08:17:27.23#ibcon#wrote, iclass 25, count 2 2006.169.08:17:27.23#ibcon#about to read 3, iclass 25, count 2 2006.169.08:17:27.25#ibcon#read 3, iclass 25, count 2 2006.169.08:17:27.25#ibcon#about to read 4, iclass 25, count 2 2006.169.08:17:27.25#ibcon#read 4, iclass 25, count 2 2006.169.08:17:27.25#ibcon#about to read 5, iclass 25, count 2 2006.169.08:17:27.25#ibcon#read 5, iclass 25, count 2 2006.169.08:17:27.25#ibcon#about to read 6, iclass 25, count 2 2006.169.08:17:27.25#ibcon#read 6, iclass 25, count 2 2006.169.08:17:27.25#ibcon#end of sib2, iclass 25, count 2 2006.169.08:17:27.25#ibcon#*mode == 0, iclass 25, count 2 2006.169.08:17:27.25#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.169.08:17:27.25#ibcon#[25=AT08-07\r\n] 2006.169.08:17:27.25#ibcon#*before write, iclass 25, count 2 2006.169.08:17:27.25#ibcon#enter sib2, iclass 25, count 2 2006.169.08:17:27.25#ibcon#flushed, iclass 25, count 2 2006.169.08:17:27.25#ibcon#about to write, iclass 25, count 2 2006.169.08:17:27.25#ibcon#wrote, iclass 25, count 2 2006.169.08:17:27.25#ibcon#about to read 3, iclass 25, count 2 2006.169.08:17:27.28#ibcon#read 3, iclass 25, count 2 2006.169.08:17:27.28#ibcon#about to read 4, iclass 25, count 2 2006.169.08:17:27.28#ibcon#read 4, iclass 25, count 2 2006.169.08:17:27.28#ibcon#about to read 5, iclass 25, count 2 2006.169.08:17:27.28#ibcon#read 5, iclass 25, count 2 2006.169.08:17:27.28#ibcon#about to read 6, iclass 25, count 2 2006.169.08:17:27.28#ibcon#read 6, iclass 25, count 2 2006.169.08:17:27.28#ibcon#end of sib2, iclass 25, count 2 2006.169.08:17:27.28#ibcon#*after write, iclass 25, count 2 2006.169.08:17:27.28#ibcon#*before return 0, iclass 25, count 2 2006.169.08:17:27.28#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:17:27.28#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:17:27.28#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.169.08:17:27.28#ibcon#ireg 7 cls_cnt 0 2006.169.08:17:27.28#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:17:27.40#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:17:27.40#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:17:27.40#ibcon#enter wrdev, iclass 25, count 0 2006.169.08:17:27.40#ibcon#first serial, iclass 25, count 0 2006.169.08:17:27.40#ibcon#enter sib2, iclass 25, count 0 2006.169.08:17:27.40#ibcon#flushed, iclass 25, count 0 2006.169.08:17:27.40#ibcon#about to write, iclass 25, count 0 2006.169.08:17:27.40#ibcon#wrote, iclass 25, count 0 2006.169.08:17:27.40#ibcon#about to read 3, iclass 25, count 0 2006.169.08:17:27.42#ibcon#read 3, iclass 25, count 0 2006.169.08:17:27.42#ibcon#about to read 4, iclass 25, count 0 2006.169.08:17:27.42#ibcon#read 4, iclass 25, count 0 2006.169.08:17:27.42#ibcon#about to read 5, iclass 25, count 0 2006.169.08:17:27.42#ibcon#read 5, iclass 25, count 0 2006.169.08:17:27.42#ibcon#about to read 6, iclass 25, count 0 2006.169.08:17:27.42#ibcon#read 6, iclass 25, count 0 2006.169.08:17:27.42#ibcon#end of sib2, iclass 25, count 0 2006.169.08:17:27.42#ibcon#*mode == 0, iclass 25, count 0 2006.169.08:17:27.42#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.169.08:17:27.42#ibcon#[25=USB\r\n] 2006.169.08:17:27.42#ibcon#*before write, iclass 25, count 0 2006.169.08:17:27.42#ibcon#enter sib2, iclass 25, count 0 2006.169.08:17:27.42#ibcon#flushed, iclass 25, count 0 2006.169.08:17:27.42#ibcon#about to write, iclass 25, count 0 2006.169.08:17:27.42#ibcon#wrote, iclass 25, count 0 2006.169.08:17:27.42#ibcon#about to read 3, iclass 25, count 0 2006.169.08:17:27.45#ibcon#read 3, iclass 25, count 0 2006.169.08:17:27.45#ibcon#about to read 4, iclass 25, count 0 2006.169.08:17:27.45#ibcon#read 4, iclass 25, count 0 2006.169.08:17:27.45#ibcon#about to read 5, iclass 25, count 0 2006.169.08:17:27.45#ibcon#read 5, iclass 25, count 0 2006.169.08:17:27.45#ibcon#about to read 6, iclass 25, count 0 2006.169.08:17:27.45#ibcon#read 6, iclass 25, count 0 2006.169.08:17:27.45#ibcon#end of sib2, iclass 25, count 0 2006.169.08:17:27.45#ibcon#*after write, iclass 25, count 0 2006.169.08:17:27.45#ibcon#*before return 0, iclass 25, count 0 2006.169.08:17:27.45#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:17:27.45#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:17:27.45#ibcon#about to clear, iclass 25 cls_cnt 0 2006.169.08:17:27.45#ibcon#cleared, iclass 25 cls_cnt 0 2006.169.08:17:27.45$vc4f8/vblo=1,632.99 2006.169.08:17:27.46#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.169.08:17:27.46#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.169.08:17:27.46#ibcon#ireg 17 cls_cnt 0 2006.169.08:17:27.46#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:17:27.46#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:17:27.46#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:17:27.46#ibcon#enter wrdev, iclass 27, count 0 2006.169.08:17:27.46#ibcon#first serial, iclass 27, count 0 2006.169.08:17:27.46#ibcon#enter sib2, iclass 27, count 0 2006.169.08:17:27.46#ibcon#flushed, iclass 27, count 0 2006.169.08:17:27.46#ibcon#about to write, iclass 27, count 0 2006.169.08:17:27.46#ibcon#wrote, iclass 27, count 0 2006.169.08:17:27.46#ibcon#about to read 3, iclass 27, count 0 2006.169.08:17:27.47#ibcon#read 3, iclass 27, count 0 2006.169.08:17:27.47#ibcon#about to read 4, iclass 27, count 0 2006.169.08:17:27.47#ibcon#read 4, iclass 27, count 0 2006.169.08:17:27.47#ibcon#about to read 5, iclass 27, count 0 2006.169.08:17:27.47#ibcon#read 5, iclass 27, count 0 2006.169.08:17:27.47#ibcon#about to read 6, iclass 27, count 0 2006.169.08:17:27.47#ibcon#read 6, iclass 27, count 0 2006.169.08:17:27.47#ibcon#end of sib2, iclass 27, count 0 2006.169.08:17:27.47#ibcon#*mode == 0, iclass 27, count 0 2006.169.08:17:27.47#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.169.08:17:27.47#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.08:17:27.47#ibcon#*before write, iclass 27, count 0 2006.169.08:17:27.47#ibcon#enter sib2, iclass 27, count 0 2006.169.08:17:27.47#ibcon#flushed, iclass 27, count 0 2006.169.08:17:27.47#ibcon#about to write, iclass 27, count 0 2006.169.08:17:27.47#ibcon#wrote, iclass 27, count 0 2006.169.08:17:27.47#ibcon#about to read 3, iclass 27, count 0 2006.169.08:17:27.51#ibcon#read 3, iclass 27, count 0 2006.169.08:17:27.51#ibcon#about to read 4, iclass 27, count 0 2006.169.08:17:27.51#ibcon#read 4, iclass 27, count 0 2006.169.08:17:27.51#ibcon#about to read 5, iclass 27, count 0 2006.169.08:17:27.51#ibcon#read 5, iclass 27, count 0 2006.169.08:17:27.51#ibcon#about to read 6, iclass 27, count 0 2006.169.08:17:27.51#ibcon#read 6, iclass 27, count 0 2006.169.08:17:27.51#ibcon#end of sib2, iclass 27, count 0 2006.169.08:17:27.51#ibcon#*after write, iclass 27, count 0 2006.169.08:17:27.51#ibcon#*before return 0, iclass 27, count 0 2006.169.08:17:27.51#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:17:27.51#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:17:27.51#ibcon#about to clear, iclass 27 cls_cnt 0 2006.169.08:17:27.51#ibcon#cleared, iclass 27 cls_cnt 0 2006.169.08:17:27.51$vc4f8/vb=1,4 2006.169.08:17:27.52#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.169.08:17:27.52#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.169.08:17:27.52#ibcon#ireg 11 cls_cnt 2 2006.169.08:17:27.52#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:17:27.52#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:17:27.52#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:17:27.52#ibcon#enter wrdev, iclass 29, count 2 2006.169.08:17:27.52#ibcon#first serial, iclass 29, count 2 2006.169.08:17:27.52#ibcon#enter sib2, iclass 29, count 2 2006.169.08:17:27.52#ibcon#flushed, iclass 29, count 2 2006.169.08:17:27.52#ibcon#about to write, iclass 29, count 2 2006.169.08:17:27.52#ibcon#wrote, iclass 29, count 2 2006.169.08:17:27.52#ibcon#about to read 3, iclass 29, count 2 2006.169.08:17:27.53#ibcon#read 3, iclass 29, count 2 2006.169.08:17:27.53#ibcon#about to read 4, iclass 29, count 2 2006.169.08:17:27.53#ibcon#read 4, iclass 29, count 2 2006.169.08:17:27.53#ibcon#about to read 5, iclass 29, count 2 2006.169.08:17:27.53#ibcon#read 5, iclass 29, count 2 2006.169.08:17:27.53#ibcon#about to read 6, iclass 29, count 2 2006.169.08:17:27.53#ibcon#read 6, iclass 29, count 2 2006.169.08:17:27.53#ibcon#end of sib2, iclass 29, count 2 2006.169.08:17:27.53#ibcon#*mode == 0, iclass 29, count 2 2006.169.08:17:27.53#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.169.08:17:27.53#ibcon#[27=AT01-04\r\n] 2006.169.08:17:27.53#ibcon#*before write, iclass 29, count 2 2006.169.08:17:27.53#ibcon#enter sib2, iclass 29, count 2 2006.169.08:17:27.53#ibcon#flushed, iclass 29, count 2 2006.169.08:17:27.53#ibcon#about to write, iclass 29, count 2 2006.169.08:17:27.53#ibcon#wrote, iclass 29, count 2 2006.169.08:17:27.53#ibcon#about to read 3, iclass 29, count 2 2006.169.08:17:27.56#ibcon#read 3, iclass 29, count 2 2006.169.08:17:27.56#ibcon#about to read 4, iclass 29, count 2 2006.169.08:17:27.56#ibcon#read 4, iclass 29, count 2 2006.169.08:17:27.56#ibcon#about to read 5, iclass 29, count 2 2006.169.08:17:27.56#ibcon#read 5, iclass 29, count 2 2006.169.08:17:27.56#ibcon#about to read 6, iclass 29, count 2 2006.169.08:17:27.56#ibcon#read 6, iclass 29, count 2 2006.169.08:17:27.56#ibcon#end of sib2, iclass 29, count 2 2006.169.08:17:27.56#ibcon#*after write, iclass 29, count 2 2006.169.08:17:27.56#ibcon#*before return 0, iclass 29, count 2 2006.169.08:17:27.56#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:17:27.56#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:17:27.56#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.169.08:17:27.56#ibcon#ireg 7 cls_cnt 0 2006.169.08:17:27.56#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:17:27.68#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:17:27.68#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:17:27.68#ibcon#enter wrdev, iclass 29, count 0 2006.169.08:17:27.68#ibcon#first serial, iclass 29, count 0 2006.169.08:17:27.68#ibcon#enter sib2, iclass 29, count 0 2006.169.08:17:27.68#ibcon#flushed, iclass 29, count 0 2006.169.08:17:27.68#ibcon#about to write, iclass 29, count 0 2006.169.08:17:27.68#ibcon#wrote, iclass 29, count 0 2006.169.08:17:27.68#ibcon#about to read 3, iclass 29, count 0 2006.169.08:17:27.70#ibcon#read 3, iclass 29, count 0 2006.169.08:17:27.70#ibcon#about to read 4, iclass 29, count 0 2006.169.08:17:27.70#ibcon#read 4, iclass 29, count 0 2006.169.08:17:27.70#ibcon#about to read 5, iclass 29, count 0 2006.169.08:17:27.70#ibcon#read 5, iclass 29, count 0 2006.169.08:17:27.70#ibcon#about to read 6, iclass 29, count 0 2006.169.08:17:27.70#ibcon#read 6, iclass 29, count 0 2006.169.08:17:27.70#ibcon#end of sib2, iclass 29, count 0 2006.169.08:17:27.70#ibcon#*mode == 0, iclass 29, count 0 2006.169.08:17:27.70#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.169.08:17:27.70#ibcon#[27=USB\r\n] 2006.169.08:17:27.70#ibcon#*before write, iclass 29, count 0 2006.169.08:17:27.70#ibcon#enter sib2, iclass 29, count 0 2006.169.08:17:27.70#ibcon#flushed, iclass 29, count 0 2006.169.08:17:27.70#ibcon#about to write, iclass 29, count 0 2006.169.08:17:27.70#ibcon#wrote, iclass 29, count 0 2006.169.08:17:27.70#ibcon#about to read 3, iclass 29, count 0 2006.169.08:17:27.73#ibcon#read 3, iclass 29, count 0 2006.169.08:17:27.73#ibcon#about to read 4, iclass 29, count 0 2006.169.08:17:27.73#ibcon#read 4, iclass 29, count 0 2006.169.08:17:27.73#ibcon#about to read 5, iclass 29, count 0 2006.169.08:17:27.73#ibcon#read 5, iclass 29, count 0 2006.169.08:17:27.73#ibcon#about to read 6, iclass 29, count 0 2006.169.08:17:27.73#ibcon#read 6, iclass 29, count 0 2006.169.08:17:27.73#ibcon#end of sib2, iclass 29, count 0 2006.169.08:17:27.73#ibcon#*after write, iclass 29, count 0 2006.169.08:17:27.73#ibcon#*before return 0, iclass 29, count 0 2006.169.08:17:27.73#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:17:27.73#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:17:27.73#ibcon#about to clear, iclass 29 cls_cnt 0 2006.169.08:17:27.73#ibcon#cleared, iclass 29 cls_cnt 0 2006.169.08:17:27.74$vc4f8/vblo=2,640.99 2006.169.08:17:27.74#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.169.08:17:27.74#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.169.08:17:27.74#ibcon#ireg 17 cls_cnt 0 2006.169.08:17:27.74#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:17:27.74#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:17:27.74#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:17:27.74#ibcon#enter wrdev, iclass 31, count 0 2006.169.08:17:27.74#ibcon#first serial, iclass 31, count 0 2006.169.08:17:27.74#ibcon#enter sib2, iclass 31, count 0 2006.169.08:17:27.74#ibcon#flushed, iclass 31, count 0 2006.169.08:17:27.74#ibcon#about to write, iclass 31, count 0 2006.169.08:17:27.74#ibcon#wrote, iclass 31, count 0 2006.169.08:17:27.74#ibcon#about to read 3, iclass 31, count 0 2006.169.08:17:27.75#ibcon#read 3, iclass 31, count 0 2006.169.08:17:27.75#ibcon#about to read 4, iclass 31, count 0 2006.169.08:17:27.75#ibcon#read 4, iclass 31, count 0 2006.169.08:17:27.75#ibcon#about to read 5, iclass 31, count 0 2006.169.08:17:27.75#ibcon#read 5, iclass 31, count 0 2006.169.08:17:27.75#ibcon#about to read 6, iclass 31, count 0 2006.169.08:17:27.75#ibcon#read 6, iclass 31, count 0 2006.169.08:17:27.75#ibcon#end of sib2, iclass 31, count 0 2006.169.08:17:27.75#ibcon#*mode == 0, iclass 31, count 0 2006.169.08:17:27.75#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.169.08:17:27.75#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.08:17:27.75#ibcon#*before write, iclass 31, count 0 2006.169.08:17:27.75#ibcon#enter sib2, iclass 31, count 0 2006.169.08:17:27.75#ibcon#flushed, iclass 31, count 0 2006.169.08:17:27.75#ibcon#about to write, iclass 31, count 0 2006.169.08:17:27.75#ibcon#wrote, iclass 31, count 0 2006.169.08:17:27.75#ibcon#about to read 3, iclass 31, count 0 2006.169.08:17:27.79#ibcon#read 3, iclass 31, count 0 2006.169.08:17:27.79#ibcon#about to read 4, iclass 31, count 0 2006.169.08:17:27.79#ibcon#read 4, iclass 31, count 0 2006.169.08:17:27.79#ibcon#about to read 5, iclass 31, count 0 2006.169.08:17:27.79#ibcon#read 5, iclass 31, count 0 2006.169.08:17:27.79#ibcon#about to read 6, iclass 31, count 0 2006.169.08:17:27.79#ibcon#read 6, iclass 31, count 0 2006.169.08:17:27.79#ibcon#end of sib2, iclass 31, count 0 2006.169.08:17:27.79#ibcon#*after write, iclass 31, count 0 2006.169.08:17:27.79#ibcon#*before return 0, iclass 31, count 0 2006.169.08:17:27.79#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:17:27.79#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:17:27.79#ibcon#about to clear, iclass 31 cls_cnt 0 2006.169.08:17:27.79#ibcon#cleared, iclass 31 cls_cnt 0 2006.169.08:17:27.79$vc4f8/vb=2,4 2006.169.08:17:27.80#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.169.08:17:27.80#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.169.08:17:27.80#ibcon#ireg 11 cls_cnt 2 2006.169.08:17:27.80#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:17:27.84#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:17:27.84#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:17:27.84#ibcon#enter wrdev, iclass 33, count 2 2006.169.08:17:27.84#ibcon#first serial, iclass 33, count 2 2006.169.08:17:27.84#ibcon#enter sib2, iclass 33, count 2 2006.169.08:17:27.84#ibcon#flushed, iclass 33, count 2 2006.169.08:17:27.84#ibcon#about to write, iclass 33, count 2 2006.169.08:17:27.84#ibcon#wrote, iclass 33, count 2 2006.169.08:17:27.84#ibcon#about to read 3, iclass 33, count 2 2006.169.08:17:27.86#ibcon#read 3, iclass 33, count 2 2006.169.08:17:27.86#ibcon#about to read 4, iclass 33, count 2 2006.169.08:17:27.86#ibcon#read 4, iclass 33, count 2 2006.169.08:17:27.86#ibcon#about to read 5, iclass 33, count 2 2006.169.08:17:27.86#ibcon#read 5, iclass 33, count 2 2006.169.08:17:27.86#ibcon#about to read 6, iclass 33, count 2 2006.169.08:17:27.86#ibcon#read 6, iclass 33, count 2 2006.169.08:17:27.86#ibcon#end of sib2, iclass 33, count 2 2006.169.08:17:27.86#ibcon#*mode == 0, iclass 33, count 2 2006.169.08:17:27.86#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.169.08:17:27.86#ibcon#[27=AT02-04\r\n] 2006.169.08:17:27.86#ibcon#*before write, iclass 33, count 2 2006.169.08:17:27.86#ibcon#enter sib2, iclass 33, count 2 2006.169.08:17:27.86#ibcon#flushed, iclass 33, count 2 2006.169.08:17:27.86#ibcon#about to write, iclass 33, count 2 2006.169.08:17:27.86#ibcon#wrote, iclass 33, count 2 2006.169.08:17:27.86#ibcon#about to read 3, iclass 33, count 2 2006.169.08:17:27.89#ibcon#read 3, iclass 33, count 2 2006.169.08:17:27.89#ibcon#about to read 4, iclass 33, count 2 2006.169.08:17:27.89#ibcon#read 4, iclass 33, count 2 2006.169.08:17:27.89#ibcon#about to read 5, iclass 33, count 2 2006.169.08:17:27.89#ibcon#read 5, iclass 33, count 2 2006.169.08:17:27.89#ibcon#about to read 6, iclass 33, count 2 2006.169.08:17:27.89#ibcon#read 6, iclass 33, count 2 2006.169.08:17:27.89#ibcon#end of sib2, iclass 33, count 2 2006.169.08:17:27.89#ibcon#*after write, iclass 33, count 2 2006.169.08:17:27.89#ibcon#*before return 0, iclass 33, count 2 2006.169.08:17:27.89#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:17:27.89#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:17:27.89#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.169.08:17:27.89#ibcon#ireg 7 cls_cnt 0 2006.169.08:17:27.89#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:17:28.01#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:17:28.02#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:17:28.02#ibcon#enter wrdev, iclass 33, count 0 2006.169.08:17:28.02#ibcon#first serial, iclass 33, count 0 2006.169.08:17:28.02#ibcon#enter sib2, iclass 33, count 0 2006.169.08:17:28.02#ibcon#flushed, iclass 33, count 0 2006.169.08:17:28.02#ibcon#about to write, iclass 33, count 0 2006.169.08:17:28.02#ibcon#wrote, iclass 33, count 0 2006.169.08:17:28.02#ibcon#about to read 3, iclass 33, count 0 2006.169.08:17:28.03#ibcon#read 3, iclass 33, count 0 2006.169.08:17:28.03#ibcon#about to read 4, iclass 33, count 0 2006.169.08:17:28.03#ibcon#read 4, iclass 33, count 0 2006.169.08:17:28.03#ibcon#about to read 5, iclass 33, count 0 2006.169.08:17:28.03#ibcon#read 5, iclass 33, count 0 2006.169.08:17:28.03#ibcon#about to read 6, iclass 33, count 0 2006.169.08:17:28.03#ibcon#read 6, iclass 33, count 0 2006.169.08:17:28.03#ibcon#end of sib2, iclass 33, count 0 2006.169.08:17:28.03#ibcon#*mode == 0, iclass 33, count 0 2006.169.08:17:28.03#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.169.08:17:28.03#ibcon#[27=USB\r\n] 2006.169.08:17:28.03#ibcon#*before write, iclass 33, count 0 2006.169.08:17:28.03#ibcon#enter sib2, iclass 33, count 0 2006.169.08:17:28.03#ibcon#flushed, iclass 33, count 0 2006.169.08:17:28.03#ibcon#about to write, iclass 33, count 0 2006.169.08:17:28.03#ibcon#wrote, iclass 33, count 0 2006.169.08:17:28.03#ibcon#about to read 3, iclass 33, count 0 2006.169.08:17:28.06#ibcon#read 3, iclass 33, count 0 2006.169.08:17:28.06#ibcon#about to read 4, iclass 33, count 0 2006.169.08:17:28.06#ibcon#read 4, iclass 33, count 0 2006.169.08:17:28.06#ibcon#about to read 5, iclass 33, count 0 2006.169.08:17:28.06#ibcon#read 5, iclass 33, count 0 2006.169.08:17:28.06#ibcon#about to read 6, iclass 33, count 0 2006.169.08:17:28.06#ibcon#read 6, iclass 33, count 0 2006.169.08:17:28.06#ibcon#end of sib2, iclass 33, count 0 2006.169.08:17:28.06#ibcon#*after write, iclass 33, count 0 2006.169.08:17:28.06#ibcon#*before return 0, iclass 33, count 0 2006.169.08:17:28.06#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:17:28.06#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:17:28.06#ibcon#about to clear, iclass 33 cls_cnt 0 2006.169.08:17:28.06#ibcon#cleared, iclass 33 cls_cnt 0 2006.169.08:17:28.06$vc4f8/vblo=3,656.99 2006.169.08:17:28.07#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.169.08:17:28.07#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.169.08:17:28.07#ibcon#ireg 17 cls_cnt 0 2006.169.08:17:28.07#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:17:28.07#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:17:28.07#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:17:28.07#ibcon#enter wrdev, iclass 35, count 0 2006.169.08:17:28.07#ibcon#first serial, iclass 35, count 0 2006.169.08:17:28.07#ibcon#enter sib2, iclass 35, count 0 2006.169.08:17:28.07#ibcon#flushed, iclass 35, count 0 2006.169.08:17:28.07#ibcon#about to write, iclass 35, count 0 2006.169.08:17:28.07#ibcon#wrote, iclass 35, count 0 2006.169.08:17:28.07#ibcon#about to read 3, iclass 35, count 0 2006.169.08:17:28.08#ibcon#read 3, iclass 35, count 0 2006.169.08:17:28.08#ibcon#about to read 4, iclass 35, count 0 2006.169.08:17:28.08#ibcon#read 4, iclass 35, count 0 2006.169.08:17:28.08#ibcon#about to read 5, iclass 35, count 0 2006.169.08:17:28.08#ibcon#read 5, iclass 35, count 0 2006.169.08:17:28.08#ibcon#about to read 6, iclass 35, count 0 2006.169.08:17:28.08#ibcon#read 6, iclass 35, count 0 2006.169.08:17:28.08#ibcon#end of sib2, iclass 35, count 0 2006.169.08:17:28.08#ibcon#*mode == 0, iclass 35, count 0 2006.169.08:17:28.08#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.169.08:17:28.08#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.08:17:28.08#ibcon#*before write, iclass 35, count 0 2006.169.08:17:28.08#ibcon#enter sib2, iclass 35, count 0 2006.169.08:17:28.08#ibcon#flushed, iclass 35, count 0 2006.169.08:17:28.08#ibcon#about to write, iclass 35, count 0 2006.169.08:17:28.08#ibcon#wrote, iclass 35, count 0 2006.169.08:17:28.08#ibcon#about to read 3, iclass 35, count 0 2006.169.08:17:28.12#ibcon#read 3, iclass 35, count 0 2006.169.08:17:28.12#ibcon#about to read 4, iclass 35, count 0 2006.169.08:17:28.12#ibcon#read 4, iclass 35, count 0 2006.169.08:17:28.12#ibcon#about to read 5, iclass 35, count 0 2006.169.08:17:28.12#ibcon#read 5, iclass 35, count 0 2006.169.08:17:28.12#ibcon#about to read 6, iclass 35, count 0 2006.169.08:17:28.12#ibcon#read 6, iclass 35, count 0 2006.169.08:17:28.12#ibcon#end of sib2, iclass 35, count 0 2006.169.08:17:28.12#ibcon#*after write, iclass 35, count 0 2006.169.08:17:28.12#ibcon#*before return 0, iclass 35, count 0 2006.169.08:17:28.12#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:17:28.12#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:17:28.12#ibcon#about to clear, iclass 35 cls_cnt 0 2006.169.08:17:28.12#ibcon#cleared, iclass 35 cls_cnt 0 2006.169.08:17:28.12$vc4f8/vb=3,4 2006.169.08:17:28.13#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.169.08:17:28.13#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.169.08:17:28.13#ibcon#ireg 11 cls_cnt 2 2006.169.08:17:28.13#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:17:28.15#flagr#flagr/antenna,acquired 2006.169.08:17:28.17#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:17:28.17#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:17:28.17#ibcon#enter wrdev, iclass 37, count 2 2006.169.08:17:28.17#ibcon#first serial, iclass 37, count 2 2006.169.08:17:28.17#ibcon#enter sib2, iclass 37, count 2 2006.169.08:17:28.17#ibcon#flushed, iclass 37, count 2 2006.169.08:17:28.17#ibcon#about to write, iclass 37, count 2 2006.169.08:17:28.17#ibcon#wrote, iclass 37, count 2 2006.169.08:17:28.17#ibcon#about to read 3, iclass 37, count 2 2006.169.08:17:28.19#ibcon#read 3, iclass 37, count 2 2006.169.08:17:28.19#ibcon#about to read 4, iclass 37, count 2 2006.169.08:17:28.19#ibcon#read 4, iclass 37, count 2 2006.169.08:17:28.19#ibcon#about to read 5, iclass 37, count 2 2006.169.08:17:28.19#ibcon#read 5, iclass 37, count 2 2006.169.08:17:28.19#ibcon#about to read 6, iclass 37, count 2 2006.169.08:17:28.19#ibcon#read 6, iclass 37, count 2 2006.169.08:17:28.19#ibcon#end of sib2, iclass 37, count 2 2006.169.08:17:28.19#ibcon#*mode == 0, iclass 37, count 2 2006.169.08:17:28.19#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.169.08:17:28.19#ibcon#[27=AT03-04\r\n] 2006.169.08:17:28.19#ibcon#*before write, iclass 37, count 2 2006.169.08:17:28.19#ibcon#enter sib2, iclass 37, count 2 2006.169.08:17:28.19#ibcon#flushed, iclass 37, count 2 2006.169.08:17:28.19#ibcon#about to write, iclass 37, count 2 2006.169.08:17:28.19#ibcon#wrote, iclass 37, count 2 2006.169.08:17:28.19#ibcon#about to read 3, iclass 37, count 2 2006.169.08:17:28.22#ibcon#read 3, iclass 37, count 2 2006.169.08:17:28.22#ibcon#about to read 4, iclass 37, count 2 2006.169.08:17:28.22#ibcon#read 4, iclass 37, count 2 2006.169.08:17:28.22#ibcon#about to read 5, iclass 37, count 2 2006.169.08:17:28.22#ibcon#read 5, iclass 37, count 2 2006.169.08:17:28.22#ibcon#about to read 6, iclass 37, count 2 2006.169.08:17:28.22#ibcon#read 6, iclass 37, count 2 2006.169.08:17:28.22#ibcon#end of sib2, iclass 37, count 2 2006.169.08:17:28.22#ibcon#*after write, iclass 37, count 2 2006.169.08:17:28.22#ibcon#*before return 0, iclass 37, count 2 2006.169.08:17:28.22#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:17:28.22#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:17:28.22#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.169.08:17:28.22#ibcon#ireg 7 cls_cnt 0 2006.169.08:17:28.22#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:17:28.34#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:17:28.34#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:17:28.34#ibcon#enter wrdev, iclass 37, count 0 2006.169.08:17:28.34#ibcon#first serial, iclass 37, count 0 2006.169.08:17:28.34#ibcon#enter sib2, iclass 37, count 0 2006.169.08:17:28.34#ibcon#flushed, iclass 37, count 0 2006.169.08:17:28.34#ibcon#about to write, iclass 37, count 0 2006.169.08:17:28.34#ibcon#wrote, iclass 37, count 0 2006.169.08:17:28.34#ibcon#about to read 3, iclass 37, count 0 2006.169.08:17:28.36#ibcon#read 3, iclass 37, count 0 2006.169.08:17:28.36#ibcon#about to read 4, iclass 37, count 0 2006.169.08:17:28.36#ibcon#read 4, iclass 37, count 0 2006.169.08:17:28.36#ibcon#about to read 5, iclass 37, count 0 2006.169.08:17:28.36#ibcon#read 5, iclass 37, count 0 2006.169.08:17:28.36#ibcon#about to read 6, iclass 37, count 0 2006.169.08:17:28.36#ibcon#read 6, iclass 37, count 0 2006.169.08:17:28.36#ibcon#end of sib2, iclass 37, count 0 2006.169.08:17:28.36#ibcon#*mode == 0, iclass 37, count 0 2006.169.08:17:28.36#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.169.08:17:28.36#ibcon#[27=USB\r\n] 2006.169.08:17:28.36#ibcon#*before write, iclass 37, count 0 2006.169.08:17:28.36#ibcon#enter sib2, iclass 37, count 0 2006.169.08:17:28.36#ibcon#flushed, iclass 37, count 0 2006.169.08:17:28.36#ibcon#about to write, iclass 37, count 0 2006.169.08:17:28.36#ibcon#wrote, iclass 37, count 0 2006.169.08:17:28.36#ibcon#about to read 3, iclass 37, count 0 2006.169.08:17:28.39#ibcon#read 3, iclass 37, count 0 2006.169.08:17:28.39#ibcon#about to read 4, iclass 37, count 0 2006.169.08:17:28.39#ibcon#read 4, iclass 37, count 0 2006.169.08:17:28.39#ibcon#about to read 5, iclass 37, count 0 2006.169.08:17:28.39#ibcon#read 5, iclass 37, count 0 2006.169.08:17:28.39#ibcon#about to read 6, iclass 37, count 0 2006.169.08:17:28.39#ibcon#read 6, iclass 37, count 0 2006.169.08:17:28.39#ibcon#end of sib2, iclass 37, count 0 2006.169.08:17:28.39#ibcon#*after write, iclass 37, count 0 2006.169.08:17:28.39#ibcon#*before return 0, iclass 37, count 0 2006.169.08:17:28.39#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:17:28.39#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:17:28.39#ibcon#about to clear, iclass 37 cls_cnt 0 2006.169.08:17:28.39#ibcon#cleared, iclass 37 cls_cnt 0 2006.169.08:17:28.39$vc4f8/vblo=4,712.99 2006.169.08:17:28.40#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.169.08:17:28.40#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.169.08:17:28.40#ibcon#ireg 17 cls_cnt 0 2006.169.08:17:28.40#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:17:28.40#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:17:28.40#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:17:28.40#ibcon#enter wrdev, iclass 39, count 0 2006.169.08:17:28.40#ibcon#first serial, iclass 39, count 0 2006.169.08:17:28.40#ibcon#enter sib2, iclass 39, count 0 2006.169.08:17:28.40#ibcon#flushed, iclass 39, count 0 2006.169.08:17:28.40#ibcon#about to write, iclass 39, count 0 2006.169.08:17:28.40#ibcon#wrote, iclass 39, count 0 2006.169.08:17:28.40#ibcon#about to read 3, iclass 39, count 0 2006.169.08:17:28.41#ibcon#read 3, iclass 39, count 0 2006.169.08:17:28.41#ibcon#about to read 4, iclass 39, count 0 2006.169.08:17:28.41#ibcon#read 4, iclass 39, count 0 2006.169.08:17:28.41#ibcon#about to read 5, iclass 39, count 0 2006.169.08:17:28.41#ibcon#read 5, iclass 39, count 0 2006.169.08:17:28.41#ibcon#about to read 6, iclass 39, count 0 2006.169.08:17:28.41#ibcon#read 6, iclass 39, count 0 2006.169.08:17:28.41#ibcon#end of sib2, iclass 39, count 0 2006.169.08:17:28.41#ibcon#*mode == 0, iclass 39, count 0 2006.169.08:17:28.41#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.169.08:17:28.41#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.08:17:28.41#ibcon#*before write, iclass 39, count 0 2006.169.08:17:28.41#ibcon#enter sib2, iclass 39, count 0 2006.169.08:17:28.41#ibcon#flushed, iclass 39, count 0 2006.169.08:17:28.41#ibcon#about to write, iclass 39, count 0 2006.169.08:17:28.41#ibcon#wrote, iclass 39, count 0 2006.169.08:17:28.41#ibcon#about to read 3, iclass 39, count 0 2006.169.08:17:28.45#ibcon#read 3, iclass 39, count 0 2006.169.08:17:28.45#ibcon#about to read 4, iclass 39, count 0 2006.169.08:17:28.45#ibcon#read 4, iclass 39, count 0 2006.169.08:17:28.45#ibcon#about to read 5, iclass 39, count 0 2006.169.08:17:28.45#ibcon#read 5, iclass 39, count 0 2006.169.08:17:28.45#ibcon#about to read 6, iclass 39, count 0 2006.169.08:17:28.45#ibcon#read 6, iclass 39, count 0 2006.169.08:17:28.45#ibcon#end of sib2, iclass 39, count 0 2006.169.08:17:28.45#ibcon#*after write, iclass 39, count 0 2006.169.08:17:28.45#ibcon#*before return 0, iclass 39, count 0 2006.169.08:17:28.45#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:17:28.45#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:17:28.45#ibcon#about to clear, iclass 39 cls_cnt 0 2006.169.08:17:28.45#ibcon#cleared, iclass 39 cls_cnt 0 2006.169.08:17:28.45$vc4f8/vb=4,4 2006.169.08:17:28.46#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.169.08:17:28.46#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.169.08:17:28.46#ibcon#ireg 11 cls_cnt 2 2006.169.08:17:28.46#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:17:28.50#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:17:28.50#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:17:28.50#ibcon#enter wrdev, iclass 3, count 2 2006.169.08:17:28.50#ibcon#first serial, iclass 3, count 2 2006.169.08:17:28.50#ibcon#enter sib2, iclass 3, count 2 2006.169.08:17:28.50#ibcon#flushed, iclass 3, count 2 2006.169.08:17:28.50#ibcon#about to write, iclass 3, count 2 2006.169.08:17:28.50#ibcon#wrote, iclass 3, count 2 2006.169.08:17:28.50#ibcon#about to read 3, iclass 3, count 2 2006.169.08:17:28.52#ibcon#read 3, iclass 3, count 2 2006.169.08:17:28.52#ibcon#about to read 4, iclass 3, count 2 2006.169.08:17:28.52#ibcon#read 4, iclass 3, count 2 2006.169.08:17:28.52#ibcon#about to read 5, iclass 3, count 2 2006.169.08:17:28.52#ibcon#read 5, iclass 3, count 2 2006.169.08:17:28.52#ibcon#about to read 6, iclass 3, count 2 2006.169.08:17:28.52#ibcon#read 6, iclass 3, count 2 2006.169.08:17:28.52#ibcon#end of sib2, iclass 3, count 2 2006.169.08:17:28.52#ibcon#*mode == 0, iclass 3, count 2 2006.169.08:17:28.52#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.169.08:17:28.52#ibcon#[27=AT04-04\r\n] 2006.169.08:17:28.52#ibcon#*before write, iclass 3, count 2 2006.169.08:17:28.52#ibcon#enter sib2, iclass 3, count 2 2006.169.08:17:28.52#ibcon#flushed, iclass 3, count 2 2006.169.08:17:28.52#ibcon#about to write, iclass 3, count 2 2006.169.08:17:28.52#ibcon#wrote, iclass 3, count 2 2006.169.08:17:28.52#ibcon#about to read 3, iclass 3, count 2 2006.169.08:17:28.55#ibcon#read 3, iclass 3, count 2 2006.169.08:17:28.55#ibcon#about to read 4, iclass 3, count 2 2006.169.08:17:28.55#ibcon#read 4, iclass 3, count 2 2006.169.08:17:28.55#ibcon#about to read 5, iclass 3, count 2 2006.169.08:17:28.55#ibcon#read 5, iclass 3, count 2 2006.169.08:17:28.55#ibcon#about to read 6, iclass 3, count 2 2006.169.08:17:28.55#ibcon#read 6, iclass 3, count 2 2006.169.08:17:28.55#ibcon#end of sib2, iclass 3, count 2 2006.169.08:17:28.55#ibcon#*after write, iclass 3, count 2 2006.169.08:17:28.55#ibcon#*before return 0, iclass 3, count 2 2006.169.08:17:28.55#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:17:28.55#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:17:28.55#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.169.08:17:28.55#ibcon#ireg 7 cls_cnt 0 2006.169.08:17:28.55#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:17:28.67#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:17:28.67#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:17:28.67#ibcon#enter wrdev, iclass 3, count 0 2006.169.08:17:28.67#ibcon#first serial, iclass 3, count 0 2006.169.08:17:28.67#ibcon#enter sib2, iclass 3, count 0 2006.169.08:17:28.67#ibcon#flushed, iclass 3, count 0 2006.169.08:17:28.67#ibcon#about to write, iclass 3, count 0 2006.169.08:17:28.67#ibcon#wrote, iclass 3, count 0 2006.169.08:17:28.67#ibcon#about to read 3, iclass 3, count 0 2006.169.08:17:28.69#ibcon#read 3, iclass 3, count 0 2006.169.08:17:28.69#ibcon#about to read 4, iclass 3, count 0 2006.169.08:17:28.69#ibcon#read 4, iclass 3, count 0 2006.169.08:17:28.69#ibcon#about to read 5, iclass 3, count 0 2006.169.08:17:28.69#ibcon#read 5, iclass 3, count 0 2006.169.08:17:28.69#ibcon#about to read 6, iclass 3, count 0 2006.169.08:17:28.69#ibcon#read 6, iclass 3, count 0 2006.169.08:17:28.69#ibcon#end of sib2, iclass 3, count 0 2006.169.08:17:28.69#ibcon#*mode == 0, iclass 3, count 0 2006.169.08:17:28.69#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.169.08:17:28.69#ibcon#[27=USB\r\n] 2006.169.08:17:28.69#ibcon#*before write, iclass 3, count 0 2006.169.08:17:28.69#ibcon#enter sib2, iclass 3, count 0 2006.169.08:17:28.69#ibcon#flushed, iclass 3, count 0 2006.169.08:17:28.69#ibcon#about to write, iclass 3, count 0 2006.169.08:17:28.69#ibcon#wrote, iclass 3, count 0 2006.169.08:17:28.69#ibcon#about to read 3, iclass 3, count 0 2006.169.08:17:28.72#ibcon#read 3, iclass 3, count 0 2006.169.08:17:28.72#ibcon#about to read 4, iclass 3, count 0 2006.169.08:17:28.72#ibcon#read 4, iclass 3, count 0 2006.169.08:17:28.72#ibcon#about to read 5, iclass 3, count 0 2006.169.08:17:28.72#ibcon#read 5, iclass 3, count 0 2006.169.08:17:28.72#ibcon#about to read 6, iclass 3, count 0 2006.169.08:17:28.72#ibcon#read 6, iclass 3, count 0 2006.169.08:17:28.72#ibcon#end of sib2, iclass 3, count 0 2006.169.08:17:28.72#ibcon#*after write, iclass 3, count 0 2006.169.08:17:28.72#ibcon#*before return 0, iclass 3, count 0 2006.169.08:17:28.72#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:17:28.72#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:17:28.72#ibcon#about to clear, iclass 3 cls_cnt 0 2006.169.08:17:28.72#ibcon#cleared, iclass 3 cls_cnt 0 2006.169.08:17:28.72$vc4f8/vblo=5,744.99 2006.169.08:17:28.73#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.169.08:17:28.73#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.169.08:17:28.73#ibcon#ireg 17 cls_cnt 0 2006.169.08:17:28.73#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:17:28.73#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:17:28.73#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:17:28.73#ibcon#enter wrdev, iclass 5, count 0 2006.169.08:17:28.73#ibcon#first serial, iclass 5, count 0 2006.169.08:17:28.73#ibcon#enter sib2, iclass 5, count 0 2006.169.08:17:28.73#ibcon#flushed, iclass 5, count 0 2006.169.08:17:28.73#ibcon#about to write, iclass 5, count 0 2006.169.08:17:28.73#ibcon#wrote, iclass 5, count 0 2006.169.08:17:28.73#ibcon#about to read 3, iclass 5, count 0 2006.169.08:17:28.74#ibcon#read 3, iclass 5, count 0 2006.169.08:17:28.74#ibcon#about to read 4, iclass 5, count 0 2006.169.08:17:28.74#ibcon#read 4, iclass 5, count 0 2006.169.08:17:28.74#ibcon#about to read 5, iclass 5, count 0 2006.169.08:17:28.74#ibcon#read 5, iclass 5, count 0 2006.169.08:17:28.74#ibcon#about to read 6, iclass 5, count 0 2006.169.08:17:28.74#ibcon#read 6, iclass 5, count 0 2006.169.08:17:28.74#ibcon#end of sib2, iclass 5, count 0 2006.169.08:17:28.74#ibcon#*mode == 0, iclass 5, count 0 2006.169.08:17:28.74#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.169.08:17:28.74#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.08:17:28.74#ibcon#*before write, iclass 5, count 0 2006.169.08:17:28.74#ibcon#enter sib2, iclass 5, count 0 2006.169.08:17:28.74#ibcon#flushed, iclass 5, count 0 2006.169.08:17:28.74#ibcon#about to write, iclass 5, count 0 2006.169.08:17:28.74#ibcon#wrote, iclass 5, count 0 2006.169.08:17:28.74#ibcon#about to read 3, iclass 5, count 0 2006.169.08:17:28.78#ibcon#read 3, iclass 5, count 0 2006.169.08:17:28.78#ibcon#about to read 4, iclass 5, count 0 2006.169.08:17:28.78#ibcon#read 4, iclass 5, count 0 2006.169.08:17:28.78#ibcon#about to read 5, iclass 5, count 0 2006.169.08:17:28.78#ibcon#read 5, iclass 5, count 0 2006.169.08:17:28.78#ibcon#about to read 6, iclass 5, count 0 2006.169.08:17:28.78#ibcon#read 6, iclass 5, count 0 2006.169.08:17:28.78#ibcon#end of sib2, iclass 5, count 0 2006.169.08:17:28.78#ibcon#*after write, iclass 5, count 0 2006.169.08:17:28.78#ibcon#*before return 0, iclass 5, count 0 2006.169.08:17:28.78#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:17:28.78#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:17:28.78#ibcon#about to clear, iclass 5 cls_cnt 0 2006.169.08:17:28.78#ibcon#cleared, iclass 5 cls_cnt 0 2006.169.08:17:28.78$vc4f8/vb=5,4 2006.169.08:17:28.78#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.169.08:17:28.79#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.169.08:17:28.79#ibcon#ireg 11 cls_cnt 2 2006.169.08:17:28.79#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:17:28.83#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:17:28.83#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:17:28.83#ibcon#enter wrdev, iclass 7, count 2 2006.169.08:17:28.83#ibcon#first serial, iclass 7, count 2 2006.169.08:17:28.83#ibcon#enter sib2, iclass 7, count 2 2006.169.08:17:28.83#ibcon#flushed, iclass 7, count 2 2006.169.08:17:28.83#ibcon#about to write, iclass 7, count 2 2006.169.08:17:28.83#ibcon#wrote, iclass 7, count 2 2006.169.08:17:28.83#ibcon#about to read 3, iclass 7, count 2 2006.169.08:17:28.85#ibcon#read 3, iclass 7, count 2 2006.169.08:17:28.85#ibcon#about to read 4, iclass 7, count 2 2006.169.08:17:28.85#ibcon#read 4, iclass 7, count 2 2006.169.08:17:28.85#ibcon#about to read 5, iclass 7, count 2 2006.169.08:17:28.85#ibcon#read 5, iclass 7, count 2 2006.169.08:17:28.85#ibcon#about to read 6, iclass 7, count 2 2006.169.08:17:28.85#ibcon#read 6, iclass 7, count 2 2006.169.08:17:28.85#ibcon#end of sib2, iclass 7, count 2 2006.169.08:17:28.85#ibcon#*mode == 0, iclass 7, count 2 2006.169.08:17:28.85#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.169.08:17:28.85#ibcon#[27=AT05-04\r\n] 2006.169.08:17:28.85#ibcon#*before write, iclass 7, count 2 2006.169.08:17:28.85#ibcon#enter sib2, iclass 7, count 2 2006.169.08:17:28.85#ibcon#flushed, iclass 7, count 2 2006.169.08:17:28.85#ibcon#about to write, iclass 7, count 2 2006.169.08:17:28.85#ibcon#wrote, iclass 7, count 2 2006.169.08:17:28.85#ibcon#about to read 3, iclass 7, count 2 2006.169.08:17:28.89#ibcon#read 3, iclass 7, count 2 2006.169.08:17:28.89#ibcon#about to read 4, iclass 7, count 2 2006.169.08:17:28.89#ibcon#read 4, iclass 7, count 2 2006.169.08:17:28.89#ibcon#about to read 5, iclass 7, count 2 2006.169.08:17:28.89#ibcon#read 5, iclass 7, count 2 2006.169.08:17:28.89#ibcon#about to read 6, iclass 7, count 2 2006.169.08:17:28.89#ibcon#read 6, iclass 7, count 2 2006.169.08:17:28.89#ibcon#end of sib2, iclass 7, count 2 2006.169.08:17:28.89#ibcon#*after write, iclass 7, count 2 2006.169.08:17:28.89#ibcon#*before return 0, iclass 7, count 2 2006.169.08:17:28.89#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:17:28.89#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:17:28.89#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.169.08:17:28.89#ibcon#ireg 7 cls_cnt 0 2006.169.08:17:28.89#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:17:29.00#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:17:29.00#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:17:29.00#ibcon#enter wrdev, iclass 7, count 0 2006.169.08:17:29.00#ibcon#first serial, iclass 7, count 0 2006.169.08:17:29.00#ibcon#enter sib2, iclass 7, count 0 2006.169.08:17:29.00#ibcon#flushed, iclass 7, count 0 2006.169.08:17:29.00#ibcon#about to write, iclass 7, count 0 2006.169.08:17:29.00#ibcon#wrote, iclass 7, count 0 2006.169.08:17:29.00#ibcon#about to read 3, iclass 7, count 0 2006.169.08:17:29.02#ibcon#read 3, iclass 7, count 0 2006.169.08:17:29.02#ibcon#about to read 4, iclass 7, count 0 2006.169.08:17:29.02#ibcon#read 4, iclass 7, count 0 2006.169.08:17:29.02#ibcon#about to read 5, iclass 7, count 0 2006.169.08:17:29.02#ibcon#read 5, iclass 7, count 0 2006.169.08:17:29.02#ibcon#about to read 6, iclass 7, count 0 2006.169.08:17:29.02#ibcon#read 6, iclass 7, count 0 2006.169.08:17:29.02#ibcon#end of sib2, iclass 7, count 0 2006.169.08:17:29.02#ibcon#*mode == 0, iclass 7, count 0 2006.169.08:17:29.02#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.169.08:17:29.02#ibcon#[27=USB\r\n] 2006.169.08:17:29.02#ibcon#*before write, iclass 7, count 0 2006.169.08:17:29.02#ibcon#enter sib2, iclass 7, count 0 2006.169.08:17:29.02#ibcon#flushed, iclass 7, count 0 2006.169.08:17:29.02#ibcon#about to write, iclass 7, count 0 2006.169.08:17:29.02#ibcon#wrote, iclass 7, count 0 2006.169.08:17:29.02#ibcon#about to read 3, iclass 7, count 0 2006.169.08:17:29.05#ibcon#read 3, iclass 7, count 0 2006.169.08:17:29.05#ibcon#about to read 4, iclass 7, count 0 2006.169.08:17:29.05#ibcon#read 4, iclass 7, count 0 2006.169.08:17:29.05#ibcon#about to read 5, iclass 7, count 0 2006.169.08:17:29.05#ibcon#read 5, iclass 7, count 0 2006.169.08:17:29.05#ibcon#about to read 6, iclass 7, count 0 2006.169.08:17:29.05#ibcon#read 6, iclass 7, count 0 2006.169.08:17:29.05#ibcon#end of sib2, iclass 7, count 0 2006.169.08:17:29.05#ibcon#*after write, iclass 7, count 0 2006.169.08:17:29.05#ibcon#*before return 0, iclass 7, count 0 2006.169.08:17:29.05#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:17:29.05#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:17:29.05#ibcon#about to clear, iclass 7 cls_cnt 0 2006.169.08:17:29.05#ibcon#cleared, iclass 7 cls_cnt 0 2006.169.08:17:29.05$vc4f8/vblo=6,752.99 2006.169.08:17:29.06#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.169.08:17:29.06#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.169.08:17:29.06#ibcon#ireg 17 cls_cnt 0 2006.169.08:17:29.06#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:17:29.06#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:17:29.06#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:17:29.06#ibcon#enter wrdev, iclass 11, count 0 2006.169.08:17:29.06#ibcon#first serial, iclass 11, count 0 2006.169.08:17:29.06#ibcon#enter sib2, iclass 11, count 0 2006.169.08:17:29.06#ibcon#flushed, iclass 11, count 0 2006.169.08:17:29.06#ibcon#about to write, iclass 11, count 0 2006.169.08:17:29.06#ibcon#wrote, iclass 11, count 0 2006.169.08:17:29.06#ibcon#about to read 3, iclass 11, count 0 2006.169.08:17:29.07#ibcon#read 3, iclass 11, count 0 2006.169.08:17:29.07#ibcon#about to read 4, iclass 11, count 0 2006.169.08:17:29.07#ibcon#read 4, iclass 11, count 0 2006.169.08:17:29.07#ibcon#about to read 5, iclass 11, count 0 2006.169.08:17:29.07#ibcon#read 5, iclass 11, count 0 2006.169.08:17:29.07#ibcon#about to read 6, iclass 11, count 0 2006.169.08:17:29.07#ibcon#read 6, iclass 11, count 0 2006.169.08:17:29.07#ibcon#end of sib2, iclass 11, count 0 2006.169.08:17:29.07#ibcon#*mode == 0, iclass 11, count 0 2006.169.08:17:29.07#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.169.08:17:29.07#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.08:17:29.07#ibcon#*before write, iclass 11, count 0 2006.169.08:17:29.07#ibcon#enter sib2, iclass 11, count 0 2006.169.08:17:29.07#ibcon#flushed, iclass 11, count 0 2006.169.08:17:29.07#ibcon#about to write, iclass 11, count 0 2006.169.08:17:29.07#ibcon#wrote, iclass 11, count 0 2006.169.08:17:29.07#ibcon#about to read 3, iclass 11, count 0 2006.169.08:17:29.11#ibcon#read 3, iclass 11, count 0 2006.169.08:17:29.11#ibcon#about to read 4, iclass 11, count 0 2006.169.08:17:29.11#ibcon#read 4, iclass 11, count 0 2006.169.08:17:29.11#ibcon#about to read 5, iclass 11, count 0 2006.169.08:17:29.11#ibcon#read 5, iclass 11, count 0 2006.169.08:17:29.11#ibcon#about to read 6, iclass 11, count 0 2006.169.08:17:29.11#ibcon#read 6, iclass 11, count 0 2006.169.08:17:29.11#ibcon#end of sib2, iclass 11, count 0 2006.169.08:17:29.11#ibcon#*after write, iclass 11, count 0 2006.169.08:17:29.11#ibcon#*before return 0, iclass 11, count 0 2006.169.08:17:29.11#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:17:29.11#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:17:29.11#ibcon#about to clear, iclass 11 cls_cnt 0 2006.169.08:17:29.11#ibcon#cleared, iclass 11 cls_cnt 0 2006.169.08:17:29.11$vc4f8/vb=6,4 2006.169.08:17:29.12#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.169.08:17:29.12#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.169.08:17:29.12#ibcon#ireg 11 cls_cnt 2 2006.169.08:17:29.12#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:17:29.16#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:17:29.16#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:17:29.16#ibcon#enter wrdev, iclass 13, count 2 2006.169.08:17:29.16#ibcon#first serial, iclass 13, count 2 2006.169.08:17:29.16#ibcon#enter sib2, iclass 13, count 2 2006.169.08:17:29.16#ibcon#flushed, iclass 13, count 2 2006.169.08:17:29.16#ibcon#about to write, iclass 13, count 2 2006.169.08:17:29.16#ibcon#wrote, iclass 13, count 2 2006.169.08:17:29.16#ibcon#about to read 3, iclass 13, count 2 2006.169.08:17:29.18#ibcon#read 3, iclass 13, count 2 2006.169.08:17:29.18#ibcon#about to read 4, iclass 13, count 2 2006.169.08:17:29.18#ibcon#read 4, iclass 13, count 2 2006.169.08:17:29.18#ibcon#about to read 5, iclass 13, count 2 2006.169.08:17:29.18#ibcon#read 5, iclass 13, count 2 2006.169.08:17:29.18#ibcon#about to read 6, iclass 13, count 2 2006.169.08:17:29.18#ibcon#read 6, iclass 13, count 2 2006.169.08:17:29.18#ibcon#end of sib2, iclass 13, count 2 2006.169.08:17:29.18#ibcon#*mode == 0, iclass 13, count 2 2006.169.08:17:29.18#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.169.08:17:29.18#ibcon#[27=AT06-04\r\n] 2006.169.08:17:29.18#ibcon#*before write, iclass 13, count 2 2006.169.08:17:29.18#ibcon#enter sib2, iclass 13, count 2 2006.169.08:17:29.18#ibcon#flushed, iclass 13, count 2 2006.169.08:17:29.18#ibcon#about to write, iclass 13, count 2 2006.169.08:17:29.18#ibcon#wrote, iclass 13, count 2 2006.169.08:17:29.18#ibcon#about to read 3, iclass 13, count 2 2006.169.08:17:29.21#ibcon#read 3, iclass 13, count 2 2006.169.08:17:29.21#ibcon#about to read 4, iclass 13, count 2 2006.169.08:17:29.21#ibcon#read 4, iclass 13, count 2 2006.169.08:17:29.21#ibcon#about to read 5, iclass 13, count 2 2006.169.08:17:29.21#ibcon#read 5, iclass 13, count 2 2006.169.08:17:29.21#ibcon#about to read 6, iclass 13, count 2 2006.169.08:17:29.21#ibcon#read 6, iclass 13, count 2 2006.169.08:17:29.21#ibcon#end of sib2, iclass 13, count 2 2006.169.08:17:29.21#ibcon#*after write, iclass 13, count 2 2006.169.08:17:29.21#ibcon#*before return 0, iclass 13, count 2 2006.169.08:17:29.21#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:17:29.21#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:17:29.21#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.169.08:17:29.21#ibcon#ireg 7 cls_cnt 0 2006.169.08:17:29.21#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:17:29.33#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:17:29.33#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:17:29.33#ibcon#enter wrdev, iclass 13, count 0 2006.169.08:17:29.33#ibcon#first serial, iclass 13, count 0 2006.169.08:17:29.33#ibcon#enter sib2, iclass 13, count 0 2006.169.08:17:29.33#ibcon#flushed, iclass 13, count 0 2006.169.08:17:29.33#ibcon#about to write, iclass 13, count 0 2006.169.08:17:29.33#ibcon#wrote, iclass 13, count 0 2006.169.08:17:29.33#ibcon#about to read 3, iclass 13, count 0 2006.169.08:17:29.35#ibcon#read 3, iclass 13, count 0 2006.169.08:17:29.35#ibcon#about to read 4, iclass 13, count 0 2006.169.08:17:29.35#ibcon#read 4, iclass 13, count 0 2006.169.08:17:29.35#ibcon#about to read 5, iclass 13, count 0 2006.169.08:17:29.35#ibcon#read 5, iclass 13, count 0 2006.169.08:17:29.35#ibcon#about to read 6, iclass 13, count 0 2006.169.08:17:29.35#ibcon#read 6, iclass 13, count 0 2006.169.08:17:29.35#ibcon#end of sib2, iclass 13, count 0 2006.169.08:17:29.35#ibcon#*mode == 0, iclass 13, count 0 2006.169.08:17:29.35#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.08:17:29.35#ibcon#[27=USB\r\n] 2006.169.08:17:29.35#ibcon#*before write, iclass 13, count 0 2006.169.08:17:29.35#ibcon#enter sib2, iclass 13, count 0 2006.169.08:17:29.35#ibcon#flushed, iclass 13, count 0 2006.169.08:17:29.35#ibcon#about to write, iclass 13, count 0 2006.169.08:17:29.35#ibcon#wrote, iclass 13, count 0 2006.169.08:17:29.35#ibcon#about to read 3, iclass 13, count 0 2006.169.08:17:29.38#ibcon#read 3, iclass 13, count 0 2006.169.08:17:29.38#ibcon#about to read 4, iclass 13, count 0 2006.169.08:17:29.38#ibcon#read 4, iclass 13, count 0 2006.169.08:17:29.38#ibcon#about to read 5, iclass 13, count 0 2006.169.08:17:29.38#ibcon#read 5, iclass 13, count 0 2006.169.08:17:29.38#ibcon#about to read 6, iclass 13, count 0 2006.169.08:17:29.38#ibcon#read 6, iclass 13, count 0 2006.169.08:17:29.38#ibcon#end of sib2, iclass 13, count 0 2006.169.08:17:29.38#ibcon#*after write, iclass 13, count 0 2006.169.08:17:29.38#ibcon#*before return 0, iclass 13, count 0 2006.169.08:17:29.38#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:17:29.38#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:17:29.38#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.08:17:29.38#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.08:17:29.38$vc4f8/vabw=wide 2006.169.08:17:29.39#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.169.08:17:29.39#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.169.08:17:29.39#ibcon#ireg 8 cls_cnt 0 2006.169.08:17:29.39#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:17:29.39#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:17:29.39#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:17:29.39#ibcon#enter wrdev, iclass 15, count 0 2006.169.08:17:29.39#ibcon#first serial, iclass 15, count 0 2006.169.08:17:29.39#ibcon#enter sib2, iclass 15, count 0 2006.169.08:17:29.39#ibcon#flushed, iclass 15, count 0 2006.169.08:17:29.39#ibcon#about to write, iclass 15, count 0 2006.169.08:17:29.39#ibcon#wrote, iclass 15, count 0 2006.169.08:17:29.39#ibcon#about to read 3, iclass 15, count 0 2006.169.08:17:29.40#ibcon#read 3, iclass 15, count 0 2006.169.08:17:29.40#ibcon#about to read 4, iclass 15, count 0 2006.169.08:17:29.40#ibcon#read 4, iclass 15, count 0 2006.169.08:17:29.40#ibcon#about to read 5, iclass 15, count 0 2006.169.08:17:29.40#ibcon#read 5, iclass 15, count 0 2006.169.08:17:29.40#ibcon#about to read 6, iclass 15, count 0 2006.169.08:17:29.40#ibcon#read 6, iclass 15, count 0 2006.169.08:17:29.40#ibcon#end of sib2, iclass 15, count 0 2006.169.08:17:29.40#ibcon#*mode == 0, iclass 15, count 0 2006.169.08:17:29.40#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.169.08:17:29.40#ibcon#[25=BW32\r\n] 2006.169.08:17:29.40#ibcon#*before write, iclass 15, count 0 2006.169.08:17:29.40#ibcon#enter sib2, iclass 15, count 0 2006.169.08:17:29.40#ibcon#flushed, iclass 15, count 0 2006.169.08:17:29.40#ibcon#about to write, iclass 15, count 0 2006.169.08:17:29.40#ibcon#wrote, iclass 15, count 0 2006.169.08:17:29.40#ibcon#about to read 3, iclass 15, count 0 2006.169.08:17:29.43#ibcon#read 3, iclass 15, count 0 2006.169.08:17:29.43#ibcon#about to read 4, iclass 15, count 0 2006.169.08:17:29.43#ibcon#read 4, iclass 15, count 0 2006.169.08:17:29.43#ibcon#about to read 5, iclass 15, count 0 2006.169.08:17:29.43#ibcon#read 5, iclass 15, count 0 2006.169.08:17:29.43#ibcon#about to read 6, iclass 15, count 0 2006.169.08:17:29.43#ibcon#read 6, iclass 15, count 0 2006.169.08:17:29.43#ibcon#end of sib2, iclass 15, count 0 2006.169.08:17:29.43#ibcon#*after write, iclass 15, count 0 2006.169.08:17:29.43#ibcon#*before return 0, iclass 15, count 0 2006.169.08:17:29.43#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:17:29.43#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:17:29.43#ibcon#about to clear, iclass 15 cls_cnt 0 2006.169.08:17:29.43#ibcon#cleared, iclass 15 cls_cnt 0 2006.169.08:17:29.43$vc4f8/vbbw=wide 2006.169.08:17:29.44#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.169.08:17:29.44#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.169.08:17:29.44#ibcon#ireg 8 cls_cnt 0 2006.169.08:17:29.44#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:17:29.49#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:17:29.49#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:17:29.49#ibcon#enter wrdev, iclass 17, count 0 2006.169.08:17:29.49#ibcon#first serial, iclass 17, count 0 2006.169.08:17:29.49#ibcon#enter sib2, iclass 17, count 0 2006.169.08:17:29.49#ibcon#flushed, iclass 17, count 0 2006.169.08:17:29.49#ibcon#about to write, iclass 17, count 0 2006.169.08:17:29.49#ibcon#wrote, iclass 17, count 0 2006.169.08:17:29.49#ibcon#about to read 3, iclass 17, count 0 2006.169.08:17:29.51#ibcon#read 3, iclass 17, count 0 2006.169.08:17:29.51#ibcon#about to read 4, iclass 17, count 0 2006.169.08:17:29.51#ibcon#read 4, iclass 17, count 0 2006.169.08:17:29.51#ibcon#about to read 5, iclass 17, count 0 2006.169.08:17:29.51#ibcon#read 5, iclass 17, count 0 2006.169.08:17:29.51#ibcon#about to read 6, iclass 17, count 0 2006.169.08:17:29.51#ibcon#read 6, iclass 17, count 0 2006.169.08:17:29.51#ibcon#end of sib2, iclass 17, count 0 2006.169.08:17:29.51#ibcon#*mode == 0, iclass 17, count 0 2006.169.08:17:29.51#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.169.08:17:29.51#ibcon#[27=BW32\r\n] 2006.169.08:17:29.51#ibcon#*before write, iclass 17, count 0 2006.169.08:17:29.51#ibcon#enter sib2, iclass 17, count 0 2006.169.08:17:29.51#ibcon#flushed, iclass 17, count 0 2006.169.08:17:29.51#ibcon#about to write, iclass 17, count 0 2006.169.08:17:29.51#ibcon#wrote, iclass 17, count 0 2006.169.08:17:29.51#ibcon#about to read 3, iclass 17, count 0 2006.169.08:17:29.54#ibcon#read 3, iclass 17, count 0 2006.169.08:17:29.54#ibcon#about to read 4, iclass 17, count 0 2006.169.08:17:29.54#ibcon#read 4, iclass 17, count 0 2006.169.08:17:29.54#ibcon#about to read 5, iclass 17, count 0 2006.169.08:17:29.54#ibcon#read 5, iclass 17, count 0 2006.169.08:17:29.54#ibcon#about to read 6, iclass 17, count 0 2006.169.08:17:29.54#ibcon#read 6, iclass 17, count 0 2006.169.08:17:29.54#ibcon#end of sib2, iclass 17, count 0 2006.169.08:17:29.54#ibcon#*after write, iclass 17, count 0 2006.169.08:17:29.54#ibcon#*before return 0, iclass 17, count 0 2006.169.08:17:29.54#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:17:29.54#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:17:29.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.169.08:17:29.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.169.08:17:29.54$4f8m12a/ifd4f 2006.169.08:17:29.55$ifd4f/lo= 2006.169.08:17:29.55$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.08:17:29.55$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.08:17:29.55$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.08:17:29.55$ifd4f/patch= 2006.169.08:17:29.55$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.08:17:29.55$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.08:17:29.55$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.08:17:29.55$4f8m12a/"form=m,16.000,1:2 2006.169.08:17:29.55$4f8m12a/"tpicd 2006.169.08:17:29.55$4f8m12a/echo=off 2006.169.08:17:29.55$4f8m12a/xlog=off 2006.169.08:17:29.55:!2006.169.08:19:50 2006.169.08:19:50.01:preob 2006.169.08:19:51.13/onsource/TRACKING 2006.169.08:19:51.13:!2006.169.08:20:00 2006.169.08:20:00.00:data_valid=on 2006.169.08:20:00.00:midob 2006.169.08:20:00.13/onsource/TRACKING 2006.169.08:20:00.13/wx/18.10,1003.9,100 2006.169.08:20:00.25/cable/+6.5304E-03 2006.169.08:20:01.34/va/01,08,usb,yes,43,45 2006.169.08:20:01.34/va/02,07,usb,yes,43,45 2006.169.08:20:01.34/va/03,06,usb,yes,46,46 2006.169.08:20:01.34/va/04,07,usb,yes,45,48 2006.169.08:20:01.34/va/05,07,usb,yes,48,51 2006.169.08:20:01.34/va/06,06,usb,yes,48,47 2006.169.08:20:01.34/va/07,06,usb,yes,48,48 2006.169.08:20:01.34/va/08,07,usb,yes,46,45 2006.169.08:20:01.57/valo/01,532.99,yes,locked 2006.169.08:20:01.57/valo/02,572.99,yes,locked 2006.169.08:20:01.57/valo/03,672.99,yes,locked 2006.169.08:20:01.57/valo/04,832.99,yes,locked 2006.169.08:20:01.57/valo/05,652.99,yes,locked 2006.169.08:20:01.57/valo/06,772.99,yes,locked 2006.169.08:20:01.57/valo/07,832.99,yes,locked 2006.169.08:20:01.57/valo/08,852.99,yes,locked 2006.169.08:20:02.66/vb/01,04,usb,yes,30,28 2006.169.08:20:02.66/vb/02,04,usb,yes,32,33 2006.169.08:20:02.66/vb/03,04,usb,yes,28,32 2006.169.08:20:02.66/vb/04,04,usb,yes,29,29 2006.169.08:20:02.66/vb/05,04,usb,yes,27,31 2006.169.08:20:02.66/vb/06,04,usb,yes,28,31 2006.169.08:20:02.66/vb/07,04,usb,yes,30,30 2006.169.08:20:02.66/vb/08,04,usb,yes,28,31 2006.169.08:20:02.89/vblo/01,632.99,yes,locked 2006.169.08:20:02.89/vblo/02,640.99,yes,locked 2006.169.08:20:02.89/vblo/03,656.99,yes,locked 2006.169.08:20:02.89/vblo/04,712.99,yes,locked 2006.169.08:20:02.89/vblo/05,744.99,yes,locked 2006.169.08:20:02.89/vblo/06,752.99,yes,locked 2006.169.08:20:02.89/vblo/07,734.99,yes,locked 2006.169.08:20:02.89/vblo/08,744.99,yes,locked 2006.169.08:20:03.04/vabw/8 2006.169.08:20:03.19/vbbw/8 2006.169.08:20:03.28/xfe/off,on,14.2 2006.169.08:20:03.65/ifatt/23,28,28,28 2006.169.08:20:04.08/fmout-gps/S +4.16E-07 2006.169.08:20:04.16:!2006.169.08:22:10 2006.169.08:22:10.01:data_valid=off 2006.169.08:22:10.02:postob 2006.169.08:22:10.09/cable/+6.5283E-03 2006.169.08:22:10.10/wx/18.09,1003.9,100 2006.169.08:22:11.07/fmout-gps/S +4.16E-07 2006.169.08:22:11.08:scan_name=169-0824,k06169,60 2006.169.08:22:11.08:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.169.08:22:12.14#flagr#flagr/antenna,new-source 2006.169.08:22:12.15:checkk5 2006.169.08:22:12.53/chk_autoobs//k5ts1/ autoobs is running! 2006.169.08:22:12.91/chk_autoobs//k5ts2/ autoobs is running! 2006.169.08:22:16.93/chk_autoobs//k5ts3?ERROR: timeout happened! 2006.169.08:22:17.32/chk_autoobs//k5ts4/ autoobs is running! 2006.169.08:22:17.69/chk_obsdata//k5ts1/T1690820??a.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.169.08:22:18.07/chk_obsdata//k5ts2/T1690820??b.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.169.08:22:25.09/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.08:22:25.46/chk_obsdata//k5ts4/T1690820??d.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.169.08:22:26.17/k5log//k5ts1_log_newline 2006.169.08:22:26.86/k5log//k5ts2_log_newline 2006.169.08:22:33.95/k5log//k5ts3?ERROR: timeout happened! 2006.169.08:22:34.66/k5log//k5ts4_log_newline 2006.169.08:22:34.82/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.08:22:34.82:4f8m12a=3 2006.169.08:22:34.82$4f8m12a/echo=on 2006.169.08:22:34.82$4f8m12a/pcalon 2006.169.08:22:34.82$pcalon/"no phase cal control is implemented here 2006.169.08:22:34.83$4f8m12a/"tpicd=stop 2006.169.08:22:34.83$4f8m12a/vc4f8 2006.169.08:22:34.83$vc4f8/valo=1,532.99 2006.169.08:22:34.83#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.169.08:22:34.83#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.169.08:22:34.83#ibcon#ireg 17 cls_cnt 0 2006.169.08:22:34.83#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:22:34.83#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:22:34.83#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:22:34.83#ibcon#enter wrdev, iclass 27, count 0 2006.169.08:22:34.83#ibcon#first serial, iclass 27, count 0 2006.169.08:22:34.83#ibcon#enter sib2, iclass 27, count 0 2006.169.08:22:34.83#ibcon#flushed, iclass 27, count 0 2006.169.08:22:34.83#ibcon#about to write, iclass 27, count 0 2006.169.08:22:34.83#ibcon#wrote, iclass 27, count 0 2006.169.08:22:34.83#ibcon#about to read 3, iclass 27, count 0 2006.169.08:22:34.86#ibcon#read 3, iclass 27, count 0 2006.169.08:22:34.86#ibcon#about to read 4, iclass 27, count 0 2006.169.08:22:34.86#ibcon#read 4, iclass 27, count 0 2006.169.08:22:34.86#ibcon#about to read 5, iclass 27, count 0 2006.169.08:22:34.86#ibcon#read 5, iclass 27, count 0 2006.169.08:22:34.86#ibcon#about to read 6, iclass 27, count 0 2006.169.08:22:34.86#ibcon#read 6, iclass 27, count 0 2006.169.08:22:34.86#ibcon#end of sib2, iclass 27, count 0 2006.169.08:22:34.86#ibcon#*mode == 0, iclass 27, count 0 2006.169.08:22:34.86#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.169.08:22:34.86#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.08:22:34.86#ibcon#*before write, iclass 27, count 0 2006.169.08:22:34.86#ibcon#enter sib2, iclass 27, count 0 2006.169.08:22:34.86#ibcon#flushed, iclass 27, count 0 2006.169.08:22:34.86#ibcon#about to write, iclass 27, count 0 2006.169.08:22:34.86#ibcon#wrote, iclass 27, count 0 2006.169.08:22:34.86#ibcon#about to read 3, iclass 27, count 0 2006.169.08:22:34.90#ibcon#read 3, iclass 27, count 0 2006.169.08:22:34.90#ibcon#about to read 4, iclass 27, count 0 2006.169.08:22:34.90#ibcon#read 4, iclass 27, count 0 2006.169.08:22:34.90#ibcon#about to read 5, iclass 27, count 0 2006.169.08:22:34.90#ibcon#read 5, iclass 27, count 0 2006.169.08:22:34.90#ibcon#about to read 6, iclass 27, count 0 2006.169.08:22:34.90#ibcon#read 6, iclass 27, count 0 2006.169.08:22:34.90#ibcon#end of sib2, iclass 27, count 0 2006.169.08:22:34.90#ibcon#*after write, iclass 27, count 0 2006.169.08:22:34.90#ibcon#*before return 0, iclass 27, count 0 2006.169.08:22:34.90#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:22:34.90#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:22:34.90#ibcon#about to clear, iclass 27 cls_cnt 0 2006.169.08:22:34.90#ibcon#cleared, iclass 27 cls_cnt 0 2006.169.08:22:34.90$vc4f8/va=1,8 2006.169.08:22:34.90#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.169.08:22:34.90#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.169.08:22:34.90#ibcon#ireg 11 cls_cnt 2 2006.169.08:22:34.90#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:22:34.90#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:22:34.90#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:22:34.90#ibcon#enter wrdev, iclass 29, count 2 2006.169.08:22:34.90#ibcon#first serial, iclass 29, count 2 2006.169.08:22:34.90#ibcon#enter sib2, iclass 29, count 2 2006.169.08:22:34.90#ibcon#flushed, iclass 29, count 2 2006.169.08:22:34.90#ibcon#about to write, iclass 29, count 2 2006.169.08:22:34.90#ibcon#wrote, iclass 29, count 2 2006.169.08:22:34.90#ibcon#about to read 3, iclass 29, count 2 2006.169.08:22:34.92#ibcon#read 3, iclass 29, count 2 2006.169.08:22:34.92#ibcon#about to read 4, iclass 29, count 2 2006.169.08:22:34.92#ibcon#read 4, iclass 29, count 2 2006.169.08:22:34.92#ibcon#about to read 5, iclass 29, count 2 2006.169.08:22:34.92#ibcon#read 5, iclass 29, count 2 2006.169.08:22:34.92#ibcon#about to read 6, iclass 29, count 2 2006.169.08:22:34.92#ibcon#read 6, iclass 29, count 2 2006.169.08:22:34.92#ibcon#end of sib2, iclass 29, count 2 2006.169.08:22:34.92#ibcon#*mode == 0, iclass 29, count 2 2006.169.08:22:34.92#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.169.08:22:34.92#ibcon#[25=AT01-08\r\n] 2006.169.08:22:34.92#ibcon#*before write, iclass 29, count 2 2006.169.08:22:34.92#ibcon#enter sib2, iclass 29, count 2 2006.169.08:22:34.92#ibcon#flushed, iclass 29, count 2 2006.169.08:22:34.92#ibcon#about to write, iclass 29, count 2 2006.169.08:22:34.92#ibcon#wrote, iclass 29, count 2 2006.169.08:22:34.92#ibcon#about to read 3, iclass 29, count 2 2006.169.08:22:34.95#ibcon#read 3, iclass 29, count 2 2006.169.08:22:34.95#ibcon#about to read 4, iclass 29, count 2 2006.169.08:22:34.95#ibcon#read 4, iclass 29, count 2 2006.169.08:22:34.95#ibcon#about to read 5, iclass 29, count 2 2006.169.08:22:34.95#ibcon#read 5, iclass 29, count 2 2006.169.08:22:34.95#ibcon#about to read 6, iclass 29, count 2 2006.169.08:22:34.95#ibcon#read 6, iclass 29, count 2 2006.169.08:22:34.95#ibcon#end of sib2, iclass 29, count 2 2006.169.08:22:34.95#ibcon#*after write, iclass 29, count 2 2006.169.08:22:34.95#ibcon#*before return 0, iclass 29, count 2 2006.169.08:22:34.95#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:22:34.95#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:22:34.95#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.169.08:22:34.95#ibcon#ireg 7 cls_cnt 0 2006.169.08:22:34.95#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:22:35.08#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:22:35.08#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:22:35.08#ibcon#enter wrdev, iclass 29, count 0 2006.169.08:22:35.08#ibcon#first serial, iclass 29, count 0 2006.169.08:22:35.08#ibcon#enter sib2, iclass 29, count 0 2006.169.08:22:35.08#ibcon#flushed, iclass 29, count 0 2006.169.08:22:35.08#ibcon#about to write, iclass 29, count 0 2006.169.08:22:35.08#ibcon#wrote, iclass 29, count 0 2006.169.08:22:35.08#ibcon#about to read 3, iclass 29, count 0 2006.169.08:22:35.10#ibcon#read 3, iclass 29, count 0 2006.169.08:22:35.10#ibcon#about to read 4, iclass 29, count 0 2006.169.08:22:35.10#ibcon#read 4, iclass 29, count 0 2006.169.08:22:35.10#ibcon#about to read 5, iclass 29, count 0 2006.169.08:22:35.10#ibcon#read 5, iclass 29, count 0 2006.169.08:22:35.10#ibcon#about to read 6, iclass 29, count 0 2006.169.08:22:35.10#ibcon#read 6, iclass 29, count 0 2006.169.08:22:35.10#ibcon#end of sib2, iclass 29, count 0 2006.169.08:22:35.10#ibcon#*mode == 0, iclass 29, count 0 2006.169.08:22:35.10#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.169.08:22:35.10#ibcon#[25=USB\r\n] 2006.169.08:22:35.10#ibcon#*before write, iclass 29, count 0 2006.169.08:22:35.10#ibcon#enter sib2, iclass 29, count 0 2006.169.08:22:35.10#ibcon#flushed, iclass 29, count 0 2006.169.08:22:35.10#ibcon#about to write, iclass 29, count 0 2006.169.08:22:35.10#ibcon#wrote, iclass 29, count 0 2006.169.08:22:35.10#ibcon#about to read 3, iclass 29, count 0 2006.169.08:22:35.13#ibcon#read 3, iclass 29, count 0 2006.169.08:22:35.13#ibcon#about to read 4, iclass 29, count 0 2006.169.08:22:35.13#ibcon#read 4, iclass 29, count 0 2006.169.08:22:35.13#ibcon#about to read 5, iclass 29, count 0 2006.169.08:22:35.13#ibcon#read 5, iclass 29, count 0 2006.169.08:22:35.13#ibcon#about to read 6, iclass 29, count 0 2006.169.08:22:35.13#ibcon#read 6, iclass 29, count 0 2006.169.08:22:35.13#ibcon#end of sib2, iclass 29, count 0 2006.169.08:22:35.13#ibcon#*after write, iclass 29, count 0 2006.169.08:22:35.13#ibcon#*before return 0, iclass 29, count 0 2006.169.08:22:35.13#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:22:35.13#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:22:35.13#ibcon#about to clear, iclass 29 cls_cnt 0 2006.169.08:22:35.13#ibcon#cleared, iclass 29 cls_cnt 0 2006.169.08:22:35.13$vc4f8/valo=2,572.99 2006.169.08:22:35.13#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.169.08:22:35.13#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.169.08:22:35.13#ibcon#ireg 17 cls_cnt 0 2006.169.08:22:35.13#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:22:35.13#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:22:35.13#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:22:35.13#ibcon#enter wrdev, iclass 31, count 0 2006.169.08:22:35.13#ibcon#first serial, iclass 31, count 0 2006.169.08:22:35.13#ibcon#enter sib2, iclass 31, count 0 2006.169.08:22:35.13#ibcon#flushed, iclass 31, count 0 2006.169.08:22:35.13#ibcon#about to write, iclass 31, count 0 2006.169.08:22:35.13#ibcon#wrote, iclass 31, count 0 2006.169.08:22:35.13#ibcon#about to read 3, iclass 31, count 0 2006.169.08:22:35.15#ibcon#read 3, iclass 31, count 0 2006.169.08:22:35.15#ibcon#about to read 4, iclass 31, count 0 2006.169.08:22:35.15#ibcon#read 4, iclass 31, count 0 2006.169.08:22:35.15#ibcon#about to read 5, iclass 31, count 0 2006.169.08:22:35.15#ibcon#read 5, iclass 31, count 0 2006.169.08:22:35.15#ibcon#about to read 6, iclass 31, count 0 2006.169.08:22:35.15#ibcon#read 6, iclass 31, count 0 2006.169.08:22:35.15#ibcon#end of sib2, iclass 31, count 0 2006.169.08:22:35.15#ibcon#*mode == 0, iclass 31, count 0 2006.169.08:22:35.15#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.169.08:22:35.15#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.08:22:35.15#ibcon#*before write, iclass 31, count 0 2006.169.08:22:35.15#ibcon#enter sib2, iclass 31, count 0 2006.169.08:22:35.15#ibcon#flushed, iclass 31, count 0 2006.169.08:22:35.15#ibcon#about to write, iclass 31, count 0 2006.169.08:22:35.15#ibcon#wrote, iclass 31, count 0 2006.169.08:22:35.15#ibcon#about to read 3, iclass 31, count 0 2006.169.08:22:35.19#ibcon#read 3, iclass 31, count 0 2006.169.08:22:35.19#ibcon#about to read 4, iclass 31, count 0 2006.169.08:22:35.19#ibcon#read 4, iclass 31, count 0 2006.169.08:22:35.19#ibcon#about to read 5, iclass 31, count 0 2006.169.08:22:35.19#ibcon#read 5, iclass 31, count 0 2006.169.08:22:35.19#ibcon#about to read 6, iclass 31, count 0 2006.169.08:22:35.19#ibcon#read 6, iclass 31, count 0 2006.169.08:22:35.19#ibcon#end of sib2, iclass 31, count 0 2006.169.08:22:35.19#ibcon#*after write, iclass 31, count 0 2006.169.08:22:35.19#ibcon#*before return 0, iclass 31, count 0 2006.169.08:22:35.19#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:22:35.19#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:22:35.19#ibcon#about to clear, iclass 31 cls_cnt 0 2006.169.08:22:35.19#ibcon#cleared, iclass 31 cls_cnt 0 2006.169.08:22:35.19$vc4f8/va=2,7 2006.169.08:22:35.19#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.169.08:22:35.19#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.169.08:22:35.19#ibcon#ireg 11 cls_cnt 2 2006.169.08:22:35.19#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:22:35.25#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:22:35.25#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:22:35.25#ibcon#enter wrdev, iclass 33, count 2 2006.169.08:22:35.25#ibcon#first serial, iclass 33, count 2 2006.169.08:22:35.25#ibcon#enter sib2, iclass 33, count 2 2006.169.08:22:35.25#ibcon#flushed, iclass 33, count 2 2006.169.08:22:35.25#ibcon#about to write, iclass 33, count 2 2006.169.08:22:35.25#ibcon#wrote, iclass 33, count 2 2006.169.08:22:35.25#ibcon#about to read 3, iclass 33, count 2 2006.169.08:22:35.28#ibcon#read 3, iclass 33, count 2 2006.169.08:22:35.28#ibcon#about to read 4, iclass 33, count 2 2006.169.08:22:35.28#ibcon#read 4, iclass 33, count 2 2006.169.08:22:35.28#ibcon#about to read 5, iclass 33, count 2 2006.169.08:22:35.28#ibcon#read 5, iclass 33, count 2 2006.169.08:22:35.28#ibcon#about to read 6, iclass 33, count 2 2006.169.08:22:35.28#ibcon#read 6, iclass 33, count 2 2006.169.08:22:35.28#ibcon#end of sib2, iclass 33, count 2 2006.169.08:22:35.28#ibcon#*mode == 0, iclass 33, count 2 2006.169.08:22:35.28#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.169.08:22:35.28#ibcon#[25=AT02-07\r\n] 2006.169.08:22:35.28#ibcon#*before write, iclass 33, count 2 2006.169.08:22:35.28#ibcon#enter sib2, iclass 33, count 2 2006.169.08:22:35.28#ibcon#flushed, iclass 33, count 2 2006.169.08:22:35.28#ibcon#about to write, iclass 33, count 2 2006.169.08:22:35.28#ibcon#wrote, iclass 33, count 2 2006.169.08:22:35.28#ibcon#about to read 3, iclass 33, count 2 2006.169.08:22:35.32#ibcon#read 3, iclass 33, count 2 2006.169.08:22:35.32#ibcon#about to read 4, iclass 33, count 2 2006.169.08:22:35.32#ibcon#read 4, iclass 33, count 2 2006.169.08:22:35.32#ibcon#about to read 5, iclass 33, count 2 2006.169.08:22:35.32#ibcon#read 5, iclass 33, count 2 2006.169.08:22:35.32#ibcon#about to read 6, iclass 33, count 2 2006.169.08:22:35.32#ibcon#read 6, iclass 33, count 2 2006.169.08:22:35.32#ibcon#end of sib2, iclass 33, count 2 2006.169.08:22:35.32#ibcon#*after write, iclass 33, count 2 2006.169.08:22:35.32#ibcon#*before return 0, iclass 33, count 2 2006.169.08:22:35.32#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:22:35.32#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:22:35.32#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.169.08:22:35.32#ibcon#ireg 7 cls_cnt 0 2006.169.08:22:35.32#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:22:35.43#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:22:35.43#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:22:35.43#ibcon#enter wrdev, iclass 33, count 0 2006.169.08:22:35.43#ibcon#first serial, iclass 33, count 0 2006.169.08:22:35.43#ibcon#enter sib2, iclass 33, count 0 2006.169.08:22:35.43#ibcon#flushed, iclass 33, count 0 2006.169.08:22:35.43#ibcon#about to write, iclass 33, count 0 2006.169.08:22:35.43#ibcon#wrote, iclass 33, count 0 2006.169.08:22:35.43#ibcon#about to read 3, iclass 33, count 0 2006.169.08:22:35.45#ibcon#read 3, iclass 33, count 0 2006.169.08:22:35.45#ibcon#about to read 4, iclass 33, count 0 2006.169.08:22:35.45#ibcon#read 4, iclass 33, count 0 2006.169.08:22:35.45#ibcon#about to read 5, iclass 33, count 0 2006.169.08:22:35.45#ibcon#read 5, iclass 33, count 0 2006.169.08:22:35.45#ibcon#about to read 6, iclass 33, count 0 2006.169.08:22:35.45#ibcon#read 6, iclass 33, count 0 2006.169.08:22:35.45#ibcon#end of sib2, iclass 33, count 0 2006.169.08:22:35.45#ibcon#*mode == 0, iclass 33, count 0 2006.169.08:22:35.45#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.169.08:22:35.45#ibcon#[25=USB\r\n] 2006.169.08:22:35.45#ibcon#*before write, iclass 33, count 0 2006.169.08:22:35.45#ibcon#enter sib2, iclass 33, count 0 2006.169.08:22:35.45#ibcon#flushed, iclass 33, count 0 2006.169.08:22:35.45#ibcon#about to write, iclass 33, count 0 2006.169.08:22:35.45#ibcon#wrote, iclass 33, count 0 2006.169.08:22:35.45#ibcon#about to read 3, iclass 33, count 0 2006.169.08:22:35.48#ibcon#read 3, iclass 33, count 0 2006.169.08:22:35.48#ibcon#about to read 4, iclass 33, count 0 2006.169.08:22:35.48#ibcon#read 4, iclass 33, count 0 2006.169.08:22:35.48#ibcon#about to read 5, iclass 33, count 0 2006.169.08:22:35.48#ibcon#read 5, iclass 33, count 0 2006.169.08:22:35.48#ibcon#about to read 6, iclass 33, count 0 2006.169.08:22:35.48#ibcon#read 6, iclass 33, count 0 2006.169.08:22:35.48#ibcon#end of sib2, iclass 33, count 0 2006.169.08:22:35.48#ibcon#*after write, iclass 33, count 0 2006.169.08:22:35.48#ibcon#*before return 0, iclass 33, count 0 2006.169.08:22:35.48#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:22:35.48#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:22:35.48#ibcon#about to clear, iclass 33 cls_cnt 0 2006.169.08:22:35.48#ibcon#cleared, iclass 33 cls_cnt 0 2006.169.08:22:35.48$vc4f8/valo=3,672.99 2006.169.08:22:35.48#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.169.08:22:35.48#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.169.08:22:35.48#ibcon#ireg 17 cls_cnt 0 2006.169.08:22:35.48#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:22:35.48#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:22:35.48#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:22:35.48#ibcon#enter wrdev, iclass 35, count 0 2006.169.08:22:35.48#ibcon#first serial, iclass 35, count 0 2006.169.08:22:35.48#ibcon#enter sib2, iclass 35, count 0 2006.169.08:22:35.48#ibcon#flushed, iclass 35, count 0 2006.169.08:22:35.48#ibcon#about to write, iclass 35, count 0 2006.169.08:22:35.48#ibcon#wrote, iclass 35, count 0 2006.169.08:22:35.48#ibcon#about to read 3, iclass 35, count 0 2006.169.08:22:35.50#ibcon#read 3, iclass 35, count 0 2006.169.08:22:35.50#ibcon#about to read 4, iclass 35, count 0 2006.169.08:22:35.50#ibcon#read 4, iclass 35, count 0 2006.169.08:22:35.50#ibcon#about to read 5, iclass 35, count 0 2006.169.08:22:35.50#ibcon#read 5, iclass 35, count 0 2006.169.08:22:35.50#ibcon#about to read 6, iclass 35, count 0 2006.169.08:22:35.50#ibcon#read 6, iclass 35, count 0 2006.169.08:22:35.50#ibcon#end of sib2, iclass 35, count 0 2006.169.08:22:35.50#ibcon#*mode == 0, iclass 35, count 0 2006.169.08:22:35.50#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.169.08:22:35.50#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.08:22:35.50#ibcon#*before write, iclass 35, count 0 2006.169.08:22:35.50#ibcon#enter sib2, iclass 35, count 0 2006.169.08:22:35.50#ibcon#flushed, iclass 35, count 0 2006.169.08:22:35.50#ibcon#about to write, iclass 35, count 0 2006.169.08:22:35.50#ibcon#wrote, iclass 35, count 0 2006.169.08:22:35.50#ibcon#about to read 3, iclass 35, count 0 2006.169.08:22:35.54#ibcon#read 3, iclass 35, count 0 2006.169.08:22:35.54#ibcon#about to read 4, iclass 35, count 0 2006.169.08:22:35.54#ibcon#read 4, iclass 35, count 0 2006.169.08:22:35.54#ibcon#about to read 5, iclass 35, count 0 2006.169.08:22:35.54#ibcon#read 5, iclass 35, count 0 2006.169.08:22:35.54#ibcon#about to read 6, iclass 35, count 0 2006.169.08:22:35.54#ibcon#read 6, iclass 35, count 0 2006.169.08:22:35.54#ibcon#end of sib2, iclass 35, count 0 2006.169.08:22:35.54#ibcon#*after write, iclass 35, count 0 2006.169.08:22:35.54#ibcon#*before return 0, iclass 35, count 0 2006.169.08:22:35.54#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:22:35.54#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:22:35.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.169.08:22:35.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.169.08:22:35.54$vc4f8/va=3,6 2006.169.08:22:35.54#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.169.08:22:35.54#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.169.08:22:35.54#ibcon#ireg 11 cls_cnt 2 2006.169.08:22:35.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:22:35.60#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:22:35.60#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:22:35.60#ibcon#enter wrdev, iclass 37, count 2 2006.169.08:22:35.60#ibcon#first serial, iclass 37, count 2 2006.169.08:22:35.60#ibcon#enter sib2, iclass 37, count 2 2006.169.08:22:35.60#ibcon#flushed, iclass 37, count 2 2006.169.08:22:35.60#ibcon#about to write, iclass 37, count 2 2006.169.08:22:35.60#ibcon#wrote, iclass 37, count 2 2006.169.08:22:35.60#ibcon#about to read 3, iclass 37, count 2 2006.169.08:22:35.62#ibcon#read 3, iclass 37, count 2 2006.169.08:22:35.62#ibcon#about to read 4, iclass 37, count 2 2006.169.08:22:35.62#ibcon#read 4, iclass 37, count 2 2006.169.08:22:35.62#ibcon#about to read 5, iclass 37, count 2 2006.169.08:22:35.62#ibcon#read 5, iclass 37, count 2 2006.169.08:22:35.62#ibcon#about to read 6, iclass 37, count 2 2006.169.08:22:35.62#ibcon#read 6, iclass 37, count 2 2006.169.08:22:35.62#ibcon#end of sib2, iclass 37, count 2 2006.169.08:22:35.62#ibcon#*mode == 0, iclass 37, count 2 2006.169.08:22:35.62#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.169.08:22:35.62#ibcon#[25=AT03-06\r\n] 2006.169.08:22:35.62#ibcon#*before write, iclass 37, count 2 2006.169.08:22:35.62#ibcon#enter sib2, iclass 37, count 2 2006.169.08:22:35.62#ibcon#flushed, iclass 37, count 2 2006.169.08:22:35.62#ibcon#about to write, iclass 37, count 2 2006.169.08:22:35.62#ibcon#wrote, iclass 37, count 2 2006.169.08:22:35.62#ibcon#about to read 3, iclass 37, count 2 2006.169.08:22:35.65#ibcon#read 3, iclass 37, count 2 2006.169.08:22:35.65#ibcon#about to read 4, iclass 37, count 2 2006.169.08:22:35.65#ibcon#read 4, iclass 37, count 2 2006.169.08:22:35.65#ibcon#about to read 5, iclass 37, count 2 2006.169.08:22:35.65#ibcon#read 5, iclass 37, count 2 2006.169.08:22:35.65#ibcon#about to read 6, iclass 37, count 2 2006.169.08:22:35.65#ibcon#read 6, iclass 37, count 2 2006.169.08:22:35.65#ibcon#end of sib2, iclass 37, count 2 2006.169.08:22:35.65#ibcon#*after write, iclass 37, count 2 2006.169.08:22:35.65#ibcon#*before return 0, iclass 37, count 2 2006.169.08:22:35.65#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:22:35.65#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:22:35.65#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.169.08:22:35.65#ibcon#ireg 7 cls_cnt 0 2006.169.08:22:35.65#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:22:35.77#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:22:35.77#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:22:35.77#ibcon#enter wrdev, iclass 37, count 0 2006.169.08:22:35.77#ibcon#first serial, iclass 37, count 0 2006.169.08:22:35.77#ibcon#enter sib2, iclass 37, count 0 2006.169.08:22:35.77#ibcon#flushed, iclass 37, count 0 2006.169.08:22:35.77#ibcon#about to write, iclass 37, count 0 2006.169.08:22:35.77#ibcon#wrote, iclass 37, count 0 2006.169.08:22:35.77#ibcon#about to read 3, iclass 37, count 0 2006.169.08:22:35.79#ibcon#read 3, iclass 37, count 0 2006.169.08:22:35.79#ibcon#about to read 4, iclass 37, count 0 2006.169.08:22:35.79#ibcon#read 4, iclass 37, count 0 2006.169.08:22:35.79#ibcon#about to read 5, iclass 37, count 0 2006.169.08:22:35.79#ibcon#read 5, iclass 37, count 0 2006.169.08:22:35.79#ibcon#about to read 6, iclass 37, count 0 2006.169.08:22:35.79#ibcon#read 6, iclass 37, count 0 2006.169.08:22:35.79#ibcon#end of sib2, iclass 37, count 0 2006.169.08:22:35.79#ibcon#*mode == 0, iclass 37, count 0 2006.169.08:22:35.79#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.169.08:22:35.79#ibcon#[25=USB\r\n] 2006.169.08:22:35.79#ibcon#*before write, iclass 37, count 0 2006.169.08:22:35.79#ibcon#enter sib2, iclass 37, count 0 2006.169.08:22:35.79#ibcon#flushed, iclass 37, count 0 2006.169.08:22:35.79#ibcon#about to write, iclass 37, count 0 2006.169.08:22:35.79#ibcon#wrote, iclass 37, count 0 2006.169.08:22:35.79#ibcon#about to read 3, iclass 37, count 0 2006.169.08:22:35.82#ibcon#read 3, iclass 37, count 0 2006.169.08:22:35.82#ibcon#about to read 4, iclass 37, count 0 2006.169.08:22:35.82#ibcon#read 4, iclass 37, count 0 2006.169.08:22:35.82#ibcon#about to read 5, iclass 37, count 0 2006.169.08:22:35.82#ibcon#read 5, iclass 37, count 0 2006.169.08:22:35.82#ibcon#about to read 6, iclass 37, count 0 2006.169.08:22:35.82#ibcon#read 6, iclass 37, count 0 2006.169.08:22:35.82#ibcon#end of sib2, iclass 37, count 0 2006.169.08:22:35.82#ibcon#*after write, iclass 37, count 0 2006.169.08:22:35.82#ibcon#*before return 0, iclass 37, count 0 2006.169.08:22:35.82#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:22:35.82#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:22:35.82#ibcon#about to clear, iclass 37 cls_cnt 0 2006.169.08:22:35.82#ibcon#cleared, iclass 37 cls_cnt 0 2006.169.08:22:35.82$vc4f8/valo=4,832.99 2006.169.08:22:35.82#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.169.08:22:35.82#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.169.08:22:35.82#ibcon#ireg 17 cls_cnt 0 2006.169.08:22:35.82#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:22:35.82#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:22:35.82#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:22:35.82#ibcon#enter wrdev, iclass 39, count 0 2006.169.08:22:35.82#ibcon#first serial, iclass 39, count 0 2006.169.08:22:35.82#ibcon#enter sib2, iclass 39, count 0 2006.169.08:22:35.82#ibcon#flushed, iclass 39, count 0 2006.169.08:22:35.82#ibcon#about to write, iclass 39, count 0 2006.169.08:22:35.82#ibcon#wrote, iclass 39, count 0 2006.169.08:22:35.82#ibcon#about to read 3, iclass 39, count 0 2006.169.08:22:35.84#ibcon#read 3, iclass 39, count 0 2006.169.08:22:35.84#ibcon#about to read 4, iclass 39, count 0 2006.169.08:22:35.84#ibcon#read 4, iclass 39, count 0 2006.169.08:22:35.84#ibcon#about to read 5, iclass 39, count 0 2006.169.08:22:35.84#ibcon#read 5, iclass 39, count 0 2006.169.08:22:35.84#ibcon#about to read 6, iclass 39, count 0 2006.169.08:22:35.84#ibcon#read 6, iclass 39, count 0 2006.169.08:22:35.84#ibcon#end of sib2, iclass 39, count 0 2006.169.08:22:35.84#ibcon#*mode == 0, iclass 39, count 0 2006.169.08:22:35.84#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.169.08:22:35.84#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.08:22:35.84#ibcon#*before write, iclass 39, count 0 2006.169.08:22:35.84#ibcon#enter sib2, iclass 39, count 0 2006.169.08:22:35.84#ibcon#flushed, iclass 39, count 0 2006.169.08:22:35.84#ibcon#about to write, iclass 39, count 0 2006.169.08:22:35.84#ibcon#wrote, iclass 39, count 0 2006.169.08:22:35.84#ibcon#about to read 3, iclass 39, count 0 2006.169.08:22:35.88#ibcon#read 3, iclass 39, count 0 2006.169.08:22:35.88#ibcon#about to read 4, iclass 39, count 0 2006.169.08:22:35.88#ibcon#read 4, iclass 39, count 0 2006.169.08:22:35.88#ibcon#about to read 5, iclass 39, count 0 2006.169.08:22:35.88#ibcon#read 5, iclass 39, count 0 2006.169.08:22:35.88#ibcon#about to read 6, iclass 39, count 0 2006.169.08:22:35.88#ibcon#read 6, iclass 39, count 0 2006.169.08:22:35.88#ibcon#end of sib2, iclass 39, count 0 2006.169.08:22:35.88#ibcon#*after write, iclass 39, count 0 2006.169.08:22:35.88#ibcon#*before return 0, iclass 39, count 0 2006.169.08:22:35.88#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:22:35.88#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:22:35.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.169.08:22:35.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.169.08:22:35.88$vc4f8/va=4,7 2006.169.08:22:35.88#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.169.08:22:35.88#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.169.08:22:35.88#ibcon#ireg 11 cls_cnt 2 2006.169.08:22:35.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:22:35.94#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:22:35.94#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:22:35.94#ibcon#enter wrdev, iclass 3, count 2 2006.169.08:22:35.94#ibcon#first serial, iclass 3, count 2 2006.169.08:22:35.94#ibcon#enter sib2, iclass 3, count 2 2006.169.08:22:35.94#ibcon#flushed, iclass 3, count 2 2006.169.08:22:35.94#ibcon#about to write, iclass 3, count 2 2006.169.08:22:35.94#ibcon#wrote, iclass 3, count 2 2006.169.08:22:35.94#ibcon#about to read 3, iclass 3, count 2 2006.169.08:22:35.96#ibcon#read 3, iclass 3, count 2 2006.169.08:22:35.96#ibcon#about to read 4, iclass 3, count 2 2006.169.08:22:35.96#ibcon#read 4, iclass 3, count 2 2006.169.08:22:35.96#ibcon#about to read 5, iclass 3, count 2 2006.169.08:22:35.96#ibcon#read 5, iclass 3, count 2 2006.169.08:22:35.96#ibcon#about to read 6, iclass 3, count 2 2006.169.08:22:35.96#ibcon#read 6, iclass 3, count 2 2006.169.08:22:35.96#ibcon#end of sib2, iclass 3, count 2 2006.169.08:22:35.96#ibcon#*mode == 0, iclass 3, count 2 2006.169.08:22:35.96#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.169.08:22:35.96#ibcon#[25=AT04-07\r\n] 2006.169.08:22:35.96#ibcon#*before write, iclass 3, count 2 2006.169.08:22:35.96#ibcon#enter sib2, iclass 3, count 2 2006.169.08:22:35.96#ibcon#flushed, iclass 3, count 2 2006.169.08:22:35.96#ibcon#about to write, iclass 3, count 2 2006.169.08:22:35.96#ibcon#wrote, iclass 3, count 2 2006.169.08:22:35.96#ibcon#about to read 3, iclass 3, count 2 2006.169.08:22:35.99#ibcon#read 3, iclass 3, count 2 2006.169.08:22:35.99#ibcon#about to read 4, iclass 3, count 2 2006.169.08:22:35.99#ibcon#read 4, iclass 3, count 2 2006.169.08:22:35.99#ibcon#about to read 5, iclass 3, count 2 2006.169.08:22:35.99#ibcon#read 5, iclass 3, count 2 2006.169.08:22:35.99#ibcon#about to read 6, iclass 3, count 2 2006.169.08:22:35.99#ibcon#read 6, iclass 3, count 2 2006.169.08:22:35.99#ibcon#end of sib2, iclass 3, count 2 2006.169.08:22:35.99#ibcon#*after write, iclass 3, count 2 2006.169.08:22:35.99#ibcon#*before return 0, iclass 3, count 2 2006.169.08:22:35.99#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:22:35.99#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:22:35.99#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.169.08:22:35.99#ibcon#ireg 7 cls_cnt 0 2006.169.08:22:35.99#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:22:36.11#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:22:36.11#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:22:36.11#ibcon#enter wrdev, iclass 3, count 0 2006.169.08:22:36.11#ibcon#first serial, iclass 3, count 0 2006.169.08:22:36.11#ibcon#enter sib2, iclass 3, count 0 2006.169.08:22:36.11#ibcon#flushed, iclass 3, count 0 2006.169.08:22:36.11#ibcon#about to write, iclass 3, count 0 2006.169.08:22:36.11#ibcon#wrote, iclass 3, count 0 2006.169.08:22:36.11#ibcon#about to read 3, iclass 3, count 0 2006.169.08:22:36.13#ibcon#read 3, iclass 3, count 0 2006.169.08:22:36.13#ibcon#about to read 4, iclass 3, count 0 2006.169.08:22:36.13#ibcon#read 4, iclass 3, count 0 2006.169.08:22:36.13#ibcon#about to read 5, iclass 3, count 0 2006.169.08:22:36.13#ibcon#read 5, iclass 3, count 0 2006.169.08:22:36.13#ibcon#about to read 6, iclass 3, count 0 2006.169.08:22:36.13#ibcon#read 6, iclass 3, count 0 2006.169.08:22:36.13#ibcon#end of sib2, iclass 3, count 0 2006.169.08:22:36.13#ibcon#*mode == 0, iclass 3, count 0 2006.169.08:22:36.13#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.169.08:22:36.13#ibcon#[25=USB\r\n] 2006.169.08:22:36.13#ibcon#*before write, iclass 3, count 0 2006.169.08:22:36.13#ibcon#enter sib2, iclass 3, count 0 2006.169.08:22:36.13#ibcon#flushed, iclass 3, count 0 2006.169.08:22:36.13#ibcon#about to write, iclass 3, count 0 2006.169.08:22:36.13#ibcon#wrote, iclass 3, count 0 2006.169.08:22:36.13#ibcon#about to read 3, iclass 3, count 0 2006.169.08:22:36.16#ibcon#read 3, iclass 3, count 0 2006.169.08:22:36.16#ibcon#about to read 4, iclass 3, count 0 2006.169.08:22:36.16#ibcon#read 4, iclass 3, count 0 2006.169.08:22:36.16#ibcon#about to read 5, iclass 3, count 0 2006.169.08:22:36.16#ibcon#read 5, iclass 3, count 0 2006.169.08:22:36.16#ibcon#about to read 6, iclass 3, count 0 2006.169.08:22:36.16#ibcon#read 6, iclass 3, count 0 2006.169.08:22:36.16#ibcon#end of sib2, iclass 3, count 0 2006.169.08:22:36.16#ibcon#*after write, iclass 3, count 0 2006.169.08:22:36.16#ibcon#*before return 0, iclass 3, count 0 2006.169.08:22:36.16#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:22:36.16#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:22:36.16#ibcon#about to clear, iclass 3 cls_cnt 0 2006.169.08:22:36.16#ibcon#cleared, iclass 3 cls_cnt 0 2006.169.08:22:36.16$vc4f8/valo=5,652.99 2006.169.08:22:36.16#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.169.08:22:36.16#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.169.08:22:36.16#ibcon#ireg 17 cls_cnt 0 2006.169.08:22:36.16#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:22:36.16#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:22:36.16#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:22:36.16#ibcon#enter wrdev, iclass 5, count 0 2006.169.08:22:36.16#ibcon#first serial, iclass 5, count 0 2006.169.08:22:36.16#ibcon#enter sib2, iclass 5, count 0 2006.169.08:22:36.16#ibcon#flushed, iclass 5, count 0 2006.169.08:22:36.16#ibcon#about to write, iclass 5, count 0 2006.169.08:22:36.16#ibcon#wrote, iclass 5, count 0 2006.169.08:22:36.16#ibcon#about to read 3, iclass 5, count 0 2006.169.08:22:36.18#ibcon#read 3, iclass 5, count 0 2006.169.08:22:36.18#ibcon#about to read 4, iclass 5, count 0 2006.169.08:22:36.18#ibcon#read 4, iclass 5, count 0 2006.169.08:22:36.18#ibcon#about to read 5, iclass 5, count 0 2006.169.08:22:36.18#ibcon#read 5, iclass 5, count 0 2006.169.08:22:36.18#ibcon#about to read 6, iclass 5, count 0 2006.169.08:22:36.18#ibcon#read 6, iclass 5, count 0 2006.169.08:22:36.18#ibcon#end of sib2, iclass 5, count 0 2006.169.08:22:36.18#ibcon#*mode == 0, iclass 5, count 0 2006.169.08:22:36.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.169.08:22:36.18#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.08:22:36.18#ibcon#*before write, iclass 5, count 0 2006.169.08:22:36.18#ibcon#enter sib2, iclass 5, count 0 2006.169.08:22:36.18#ibcon#flushed, iclass 5, count 0 2006.169.08:22:36.18#ibcon#about to write, iclass 5, count 0 2006.169.08:22:36.18#ibcon#wrote, iclass 5, count 0 2006.169.08:22:36.18#ibcon#about to read 3, iclass 5, count 0 2006.169.08:22:36.22#ibcon#read 3, iclass 5, count 0 2006.169.08:22:36.22#ibcon#about to read 4, iclass 5, count 0 2006.169.08:22:36.22#ibcon#read 4, iclass 5, count 0 2006.169.08:22:36.22#ibcon#about to read 5, iclass 5, count 0 2006.169.08:22:36.22#ibcon#read 5, iclass 5, count 0 2006.169.08:22:36.22#ibcon#about to read 6, iclass 5, count 0 2006.169.08:22:36.22#ibcon#read 6, iclass 5, count 0 2006.169.08:22:36.22#ibcon#end of sib2, iclass 5, count 0 2006.169.08:22:36.22#ibcon#*after write, iclass 5, count 0 2006.169.08:22:36.22#ibcon#*before return 0, iclass 5, count 0 2006.169.08:22:36.22#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:22:36.22#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:22:36.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.169.08:22:36.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.169.08:22:36.22$vc4f8/va=5,7 2006.169.08:22:36.22#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.169.08:22:36.22#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.169.08:22:36.22#ibcon#ireg 11 cls_cnt 2 2006.169.08:22:36.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:22:36.28#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:22:36.28#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:22:36.28#ibcon#enter wrdev, iclass 7, count 2 2006.169.08:22:36.28#ibcon#first serial, iclass 7, count 2 2006.169.08:22:36.28#ibcon#enter sib2, iclass 7, count 2 2006.169.08:22:36.28#ibcon#flushed, iclass 7, count 2 2006.169.08:22:36.28#ibcon#about to write, iclass 7, count 2 2006.169.08:22:36.28#ibcon#wrote, iclass 7, count 2 2006.169.08:22:36.28#ibcon#about to read 3, iclass 7, count 2 2006.169.08:22:36.30#ibcon#read 3, iclass 7, count 2 2006.169.08:22:36.30#ibcon#about to read 4, iclass 7, count 2 2006.169.08:22:36.30#ibcon#read 4, iclass 7, count 2 2006.169.08:22:36.30#ibcon#about to read 5, iclass 7, count 2 2006.169.08:22:36.30#ibcon#read 5, iclass 7, count 2 2006.169.08:22:36.30#ibcon#about to read 6, iclass 7, count 2 2006.169.08:22:36.30#ibcon#read 6, iclass 7, count 2 2006.169.08:22:36.30#ibcon#end of sib2, iclass 7, count 2 2006.169.08:22:36.30#ibcon#*mode == 0, iclass 7, count 2 2006.169.08:22:36.30#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.169.08:22:36.30#ibcon#[25=AT05-07\r\n] 2006.169.08:22:36.30#ibcon#*before write, iclass 7, count 2 2006.169.08:22:36.30#ibcon#enter sib2, iclass 7, count 2 2006.169.08:22:36.30#ibcon#flushed, iclass 7, count 2 2006.169.08:22:36.30#ibcon#about to write, iclass 7, count 2 2006.169.08:22:36.30#ibcon#wrote, iclass 7, count 2 2006.169.08:22:36.30#ibcon#about to read 3, iclass 7, count 2 2006.169.08:22:36.33#ibcon#read 3, iclass 7, count 2 2006.169.08:22:36.33#ibcon#about to read 4, iclass 7, count 2 2006.169.08:22:36.33#ibcon#read 4, iclass 7, count 2 2006.169.08:22:36.33#ibcon#about to read 5, iclass 7, count 2 2006.169.08:22:36.33#ibcon#read 5, iclass 7, count 2 2006.169.08:22:36.33#ibcon#about to read 6, iclass 7, count 2 2006.169.08:22:36.33#ibcon#read 6, iclass 7, count 2 2006.169.08:22:36.33#ibcon#end of sib2, iclass 7, count 2 2006.169.08:22:36.33#ibcon#*after write, iclass 7, count 2 2006.169.08:22:36.33#ibcon#*before return 0, iclass 7, count 2 2006.169.08:22:36.33#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:22:36.33#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:22:36.33#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.169.08:22:36.33#ibcon#ireg 7 cls_cnt 0 2006.169.08:22:36.33#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:22:36.45#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:22:36.45#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:22:36.45#ibcon#enter wrdev, iclass 7, count 0 2006.169.08:22:36.45#ibcon#first serial, iclass 7, count 0 2006.169.08:22:36.45#ibcon#enter sib2, iclass 7, count 0 2006.169.08:22:36.45#ibcon#flushed, iclass 7, count 0 2006.169.08:22:36.45#ibcon#about to write, iclass 7, count 0 2006.169.08:22:36.45#ibcon#wrote, iclass 7, count 0 2006.169.08:22:36.45#ibcon#about to read 3, iclass 7, count 0 2006.169.08:22:36.47#ibcon#read 3, iclass 7, count 0 2006.169.08:22:36.47#ibcon#about to read 4, iclass 7, count 0 2006.169.08:22:36.47#ibcon#read 4, iclass 7, count 0 2006.169.08:22:36.47#ibcon#about to read 5, iclass 7, count 0 2006.169.08:22:36.47#ibcon#read 5, iclass 7, count 0 2006.169.08:22:36.47#ibcon#about to read 6, iclass 7, count 0 2006.169.08:22:36.47#ibcon#read 6, iclass 7, count 0 2006.169.08:22:36.47#ibcon#end of sib2, iclass 7, count 0 2006.169.08:22:36.47#ibcon#*mode == 0, iclass 7, count 0 2006.169.08:22:36.47#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.169.08:22:36.47#ibcon#[25=USB\r\n] 2006.169.08:22:36.47#ibcon#*before write, iclass 7, count 0 2006.169.08:22:36.47#ibcon#enter sib2, iclass 7, count 0 2006.169.08:22:36.47#ibcon#flushed, iclass 7, count 0 2006.169.08:22:36.47#ibcon#about to write, iclass 7, count 0 2006.169.08:22:36.47#ibcon#wrote, iclass 7, count 0 2006.169.08:22:36.47#ibcon#about to read 3, iclass 7, count 0 2006.169.08:22:36.50#ibcon#read 3, iclass 7, count 0 2006.169.08:22:36.50#ibcon#about to read 4, iclass 7, count 0 2006.169.08:22:36.50#ibcon#read 4, iclass 7, count 0 2006.169.08:22:36.50#ibcon#about to read 5, iclass 7, count 0 2006.169.08:22:36.50#ibcon#read 5, iclass 7, count 0 2006.169.08:22:36.50#ibcon#about to read 6, iclass 7, count 0 2006.169.08:22:36.50#ibcon#read 6, iclass 7, count 0 2006.169.08:22:36.50#ibcon#end of sib2, iclass 7, count 0 2006.169.08:22:36.50#ibcon#*after write, iclass 7, count 0 2006.169.08:22:36.50#ibcon#*before return 0, iclass 7, count 0 2006.169.08:22:36.50#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:22:36.50#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:22:36.50#ibcon#about to clear, iclass 7 cls_cnt 0 2006.169.08:22:36.50#ibcon#cleared, iclass 7 cls_cnt 0 2006.169.08:22:36.50$vc4f8/valo=6,772.99 2006.169.08:22:36.50#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.169.08:22:36.50#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.169.08:22:36.50#ibcon#ireg 17 cls_cnt 0 2006.169.08:22:36.50#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:22:36.50#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:22:36.50#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:22:36.50#ibcon#enter wrdev, iclass 11, count 0 2006.169.08:22:36.50#ibcon#first serial, iclass 11, count 0 2006.169.08:22:36.50#ibcon#enter sib2, iclass 11, count 0 2006.169.08:22:36.50#ibcon#flushed, iclass 11, count 0 2006.169.08:22:36.50#ibcon#about to write, iclass 11, count 0 2006.169.08:22:36.50#ibcon#wrote, iclass 11, count 0 2006.169.08:22:36.50#ibcon#about to read 3, iclass 11, count 0 2006.169.08:22:36.52#ibcon#read 3, iclass 11, count 0 2006.169.08:22:36.52#ibcon#about to read 4, iclass 11, count 0 2006.169.08:22:36.52#ibcon#read 4, iclass 11, count 0 2006.169.08:22:36.52#ibcon#about to read 5, iclass 11, count 0 2006.169.08:22:36.52#ibcon#read 5, iclass 11, count 0 2006.169.08:22:36.52#ibcon#about to read 6, iclass 11, count 0 2006.169.08:22:36.52#ibcon#read 6, iclass 11, count 0 2006.169.08:22:36.52#ibcon#end of sib2, iclass 11, count 0 2006.169.08:22:36.52#ibcon#*mode == 0, iclass 11, count 0 2006.169.08:22:36.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.169.08:22:36.52#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.08:22:36.52#ibcon#*before write, iclass 11, count 0 2006.169.08:22:36.52#ibcon#enter sib2, iclass 11, count 0 2006.169.08:22:36.52#ibcon#flushed, iclass 11, count 0 2006.169.08:22:36.52#ibcon#about to write, iclass 11, count 0 2006.169.08:22:36.52#ibcon#wrote, iclass 11, count 0 2006.169.08:22:36.52#ibcon#about to read 3, iclass 11, count 0 2006.169.08:22:36.56#ibcon#read 3, iclass 11, count 0 2006.169.08:22:36.56#ibcon#about to read 4, iclass 11, count 0 2006.169.08:22:36.56#ibcon#read 4, iclass 11, count 0 2006.169.08:22:36.56#ibcon#about to read 5, iclass 11, count 0 2006.169.08:22:36.56#ibcon#read 5, iclass 11, count 0 2006.169.08:22:36.56#ibcon#about to read 6, iclass 11, count 0 2006.169.08:22:36.56#ibcon#read 6, iclass 11, count 0 2006.169.08:22:36.56#ibcon#end of sib2, iclass 11, count 0 2006.169.08:22:36.56#ibcon#*after write, iclass 11, count 0 2006.169.08:22:36.56#ibcon#*before return 0, iclass 11, count 0 2006.169.08:22:36.56#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:22:36.56#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:22:36.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.169.08:22:36.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.169.08:22:36.56$vc4f8/va=6,6 2006.169.08:22:36.56#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.169.08:22:36.56#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.169.08:22:36.56#ibcon#ireg 11 cls_cnt 2 2006.169.08:22:36.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:22:36.62#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:22:36.62#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:22:36.62#ibcon#enter wrdev, iclass 13, count 2 2006.169.08:22:36.62#ibcon#first serial, iclass 13, count 2 2006.169.08:22:36.62#ibcon#enter sib2, iclass 13, count 2 2006.169.08:22:36.62#ibcon#flushed, iclass 13, count 2 2006.169.08:22:36.62#ibcon#about to write, iclass 13, count 2 2006.169.08:22:36.62#ibcon#wrote, iclass 13, count 2 2006.169.08:22:36.62#ibcon#about to read 3, iclass 13, count 2 2006.169.08:22:36.64#ibcon#read 3, iclass 13, count 2 2006.169.08:22:36.64#ibcon#about to read 4, iclass 13, count 2 2006.169.08:22:36.64#ibcon#read 4, iclass 13, count 2 2006.169.08:22:36.64#ibcon#about to read 5, iclass 13, count 2 2006.169.08:22:36.64#ibcon#read 5, iclass 13, count 2 2006.169.08:22:36.64#ibcon#about to read 6, iclass 13, count 2 2006.169.08:22:36.64#ibcon#read 6, iclass 13, count 2 2006.169.08:22:36.64#ibcon#end of sib2, iclass 13, count 2 2006.169.08:22:36.64#ibcon#*mode == 0, iclass 13, count 2 2006.169.08:22:36.64#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.169.08:22:36.64#ibcon#[25=AT06-06\r\n] 2006.169.08:22:36.64#ibcon#*before write, iclass 13, count 2 2006.169.08:22:36.64#ibcon#enter sib2, iclass 13, count 2 2006.169.08:22:36.64#ibcon#flushed, iclass 13, count 2 2006.169.08:22:36.64#ibcon#about to write, iclass 13, count 2 2006.169.08:22:36.64#ibcon#wrote, iclass 13, count 2 2006.169.08:22:36.64#ibcon#about to read 3, iclass 13, count 2 2006.169.08:22:36.67#ibcon#read 3, iclass 13, count 2 2006.169.08:22:36.67#ibcon#about to read 4, iclass 13, count 2 2006.169.08:22:36.67#ibcon#read 4, iclass 13, count 2 2006.169.08:22:36.67#ibcon#about to read 5, iclass 13, count 2 2006.169.08:22:36.67#ibcon#read 5, iclass 13, count 2 2006.169.08:22:36.67#ibcon#about to read 6, iclass 13, count 2 2006.169.08:22:36.67#ibcon#read 6, iclass 13, count 2 2006.169.08:22:36.67#ibcon#end of sib2, iclass 13, count 2 2006.169.08:22:36.67#ibcon#*after write, iclass 13, count 2 2006.169.08:22:36.67#ibcon#*before return 0, iclass 13, count 2 2006.169.08:22:36.67#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:22:36.67#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.169.08:22:36.67#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.169.08:22:36.67#ibcon#ireg 7 cls_cnt 0 2006.169.08:22:36.67#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:22:36.79#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:22:36.79#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:22:36.79#ibcon#enter wrdev, iclass 13, count 0 2006.169.08:22:36.79#ibcon#first serial, iclass 13, count 0 2006.169.08:22:36.79#ibcon#enter sib2, iclass 13, count 0 2006.169.08:22:36.79#ibcon#flushed, iclass 13, count 0 2006.169.08:22:36.79#ibcon#about to write, iclass 13, count 0 2006.169.08:22:36.79#ibcon#wrote, iclass 13, count 0 2006.169.08:22:36.79#ibcon#about to read 3, iclass 13, count 0 2006.169.08:22:36.81#ibcon#read 3, iclass 13, count 0 2006.169.08:22:36.81#ibcon#about to read 4, iclass 13, count 0 2006.169.08:22:36.81#ibcon#read 4, iclass 13, count 0 2006.169.08:22:36.81#ibcon#about to read 5, iclass 13, count 0 2006.169.08:22:36.81#ibcon#read 5, iclass 13, count 0 2006.169.08:22:36.81#ibcon#about to read 6, iclass 13, count 0 2006.169.08:22:36.81#ibcon#read 6, iclass 13, count 0 2006.169.08:22:36.81#ibcon#end of sib2, iclass 13, count 0 2006.169.08:22:36.81#ibcon#*mode == 0, iclass 13, count 0 2006.169.08:22:36.81#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.08:22:36.81#ibcon#[25=USB\r\n] 2006.169.08:22:36.81#ibcon#*before write, iclass 13, count 0 2006.169.08:22:36.81#ibcon#enter sib2, iclass 13, count 0 2006.169.08:22:36.81#ibcon#flushed, iclass 13, count 0 2006.169.08:22:36.81#ibcon#about to write, iclass 13, count 0 2006.169.08:22:36.81#ibcon#wrote, iclass 13, count 0 2006.169.08:22:36.81#ibcon#about to read 3, iclass 13, count 0 2006.169.08:22:36.84#ibcon#read 3, iclass 13, count 0 2006.169.08:22:36.84#ibcon#about to read 4, iclass 13, count 0 2006.169.08:22:36.84#ibcon#read 4, iclass 13, count 0 2006.169.08:22:36.84#ibcon#about to read 5, iclass 13, count 0 2006.169.08:22:36.84#ibcon#read 5, iclass 13, count 0 2006.169.08:22:36.84#ibcon#about to read 6, iclass 13, count 0 2006.169.08:22:36.84#ibcon#read 6, iclass 13, count 0 2006.169.08:22:36.84#ibcon#end of sib2, iclass 13, count 0 2006.169.08:22:36.84#ibcon#*after write, iclass 13, count 0 2006.169.08:22:36.84#ibcon#*before return 0, iclass 13, count 0 2006.169.08:22:36.84#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:22:36.84#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.169.08:22:36.84#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.08:22:36.84#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.08:22:36.84$vc4f8/valo=7,832.99 2006.169.08:22:36.84#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.169.08:22:36.84#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.169.08:22:36.84#ibcon#ireg 17 cls_cnt 0 2006.169.08:22:36.84#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:22:36.84#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:22:36.84#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:22:36.84#ibcon#enter wrdev, iclass 15, count 0 2006.169.08:22:36.84#ibcon#first serial, iclass 15, count 0 2006.169.08:22:36.84#ibcon#enter sib2, iclass 15, count 0 2006.169.08:22:36.84#ibcon#flushed, iclass 15, count 0 2006.169.08:22:36.84#ibcon#about to write, iclass 15, count 0 2006.169.08:22:36.84#ibcon#wrote, iclass 15, count 0 2006.169.08:22:36.84#ibcon#about to read 3, iclass 15, count 0 2006.169.08:22:36.86#ibcon#read 3, iclass 15, count 0 2006.169.08:22:36.86#ibcon#about to read 4, iclass 15, count 0 2006.169.08:22:36.86#ibcon#read 4, iclass 15, count 0 2006.169.08:22:36.86#ibcon#about to read 5, iclass 15, count 0 2006.169.08:22:36.86#ibcon#read 5, iclass 15, count 0 2006.169.08:22:36.86#ibcon#about to read 6, iclass 15, count 0 2006.169.08:22:36.86#ibcon#read 6, iclass 15, count 0 2006.169.08:22:36.86#ibcon#end of sib2, iclass 15, count 0 2006.169.08:22:36.86#ibcon#*mode == 0, iclass 15, count 0 2006.169.08:22:36.86#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.169.08:22:36.86#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.08:22:36.86#ibcon#*before write, iclass 15, count 0 2006.169.08:22:36.86#ibcon#enter sib2, iclass 15, count 0 2006.169.08:22:36.86#ibcon#flushed, iclass 15, count 0 2006.169.08:22:36.86#ibcon#about to write, iclass 15, count 0 2006.169.08:22:36.86#ibcon#wrote, iclass 15, count 0 2006.169.08:22:36.86#ibcon#about to read 3, iclass 15, count 0 2006.169.08:22:36.90#ibcon#read 3, iclass 15, count 0 2006.169.08:22:36.90#ibcon#about to read 4, iclass 15, count 0 2006.169.08:22:36.90#ibcon#read 4, iclass 15, count 0 2006.169.08:22:36.90#ibcon#about to read 5, iclass 15, count 0 2006.169.08:22:36.90#ibcon#read 5, iclass 15, count 0 2006.169.08:22:36.90#ibcon#about to read 6, iclass 15, count 0 2006.169.08:22:36.90#ibcon#read 6, iclass 15, count 0 2006.169.08:22:36.90#ibcon#end of sib2, iclass 15, count 0 2006.169.08:22:36.90#ibcon#*after write, iclass 15, count 0 2006.169.08:22:36.90#ibcon#*before return 0, iclass 15, count 0 2006.169.08:22:36.90#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:22:36.90#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:22:36.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.169.08:22:36.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.169.08:22:36.90$vc4f8/va=7,6 2006.169.08:22:36.90#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.169.08:22:36.90#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.169.08:22:36.90#ibcon#ireg 11 cls_cnt 2 2006.169.08:22:36.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:22:36.96#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:22:36.96#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:22:36.96#ibcon#enter wrdev, iclass 17, count 2 2006.169.08:22:36.96#ibcon#first serial, iclass 17, count 2 2006.169.08:22:36.96#ibcon#enter sib2, iclass 17, count 2 2006.169.08:22:36.96#ibcon#flushed, iclass 17, count 2 2006.169.08:22:36.96#ibcon#about to write, iclass 17, count 2 2006.169.08:22:36.96#ibcon#wrote, iclass 17, count 2 2006.169.08:22:36.96#ibcon#about to read 3, iclass 17, count 2 2006.169.08:22:36.98#ibcon#read 3, iclass 17, count 2 2006.169.08:22:36.98#ibcon#about to read 4, iclass 17, count 2 2006.169.08:22:36.98#ibcon#read 4, iclass 17, count 2 2006.169.08:22:36.98#ibcon#about to read 5, iclass 17, count 2 2006.169.08:22:36.98#ibcon#read 5, iclass 17, count 2 2006.169.08:22:36.98#ibcon#about to read 6, iclass 17, count 2 2006.169.08:22:36.98#ibcon#read 6, iclass 17, count 2 2006.169.08:22:36.98#ibcon#end of sib2, iclass 17, count 2 2006.169.08:22:36.98#ibcon#*mode == 0, iclass 17, count 2 2006.169.08:22:36.98#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.169.08:22:36.98#ibcon#[25=AT07-06\r\n] 2006.169.08:22:36.98#ibcon#*before write, iclass 17, count 2 2006.169.08:22:36.98#ibcon#enter sib2, iclass 17, count 2 2006.169.08:22:36.98#ibcon#flushed, iclass 17, count 2 2006.169.08:22:36.98#ibcon#about to write, iclass 17, count 2 2006.169.08:22:36.98#ibcon#wrote, iclass 17, count 2 2006.169.08:22:36.98#ibcon#about to read 3, iclass 17, count 2 2006.169.08:22:37.01#ibcon#read 3, iclass 17, count 2 2006.169.08:22:37.01#ibcon#about to read 4, iclass 17, count 2 2006.169.08:22:37.01#ibcon#read 4, iclass 17, count 2 2006.169.08:22:37.01#ibcon#about to read 5, iclass 17, count 2 2006.169.08:22:37.01#ibcon#read 5, iclass 17, count 2 2006.169.08:22:37.01#ibcon#about to read 6, iclass 17, count 2 2006.169.08:22:37.01#ibcon#read 6, iclass 17, count 2 2006.169.08:22:37.01#ibcon#end of sib2, iclass 17, count 2 2006.169.08:22:37.01#ibcon#*after write, iclass 17, count 2 2006.169.08:22:37.01#ibcon#*before return 0, iclass 17, count 2 2006.169.08:22:37.01#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:22:37.01#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:22:37.01#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.169.08:22:37.01#ibcon#ireg 7 cls_cnt 0 2006.169.08:22:37.01#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:22:37.13#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:22:37.13#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:22:37.13#ibcon#enter wrdev, iclass 17, count 0 2006.169.08:22:37.13#ibcon#first serial, iclass 17, count 0 2006.169.08:22:37.13#ibcon#enter sib2, iclass 17, count 0 2006.169.08:22:37.13#ibcon#flushed, iclass 17, count 0 2006.169.08:22:37.13#ibcon#about to write, iclass 17, count 0 2006.169.08:22:37.13#ibcon#wrote, iclass 17, count 0 2006.169.08:22:37.13#ibcon#about to read 3, iclass 17, count 0 2006.169.08:22:37.15#ibcon#read 3, iclass 17, count 0 2006.169.08:22:37.15#ibcon#about to read 4, iclass 17, count 0 2006.169.08:22:37.15#ibcon#read 4, iclass 17, count 0 2006.169.08:22:37.15#ibcon#about to read 5, iclass 17, count 0 2006.169.08:22:37.15#ibcon#read 5, iclass 17, count 0 2006.169.08:22:37.15#ibcon#about to read 6, iclass 17, count 0 2006.169.08:22:37.15#ibcon#read 6, iclass 17, count 0 2006.169.08:22:37.15#ibcon#end of sib2, iclass 17, count 0 2006.169.08:22:37.15#ibcon#*mode == 0, iclass 17, count 0 2006.169.08:22:37.15#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.169.08:22:37.15#ibcon#[25=USB\r\n] 2006.169.08:22:37.15#ibcon#*before write, iclass 17, count 0 2006.169.08:22:37.15#ibcon#enter sib2, iclass 17, count 0 2006.169.08:22:37.15#ibcon#flushed, iclass 17, count 0 2006.169.08:22:37.15#ibcon#about to write, iclass 17, count 0 2006.169.08:22:37.15#ibcon#wrote, iclass 17, count 0 2006.169.08:22:37.15#ibcon#about to read 3, iclass 17, count 0 2006.169.08:22:37.18#ibcon#read 3, iclass 17, count 0 2006.169.08:22:37.18#ibcon#about to read 4, iclass 17, count 0 2006.169.08:22:37.18#ibcon#read 4, iclass 17, count 0 2006.169.08:22:37.18#ibcon#about to read 5, iclass 17, count 0 2006.169.08:22:37.18#ibcon#read 5, iclass 17, count 0 2006.169.08:22:37.18#ibcon#about to read 6, iclass 17, count 0 2006.169.08:22:37.18#ibcon#read 6, iclass 17, count 0 2006.169.08:22:37.18#ibcon#end of sib2, iclass 17, count 0 2006.169.08:22:37.18#ibcon#*after write, iclass 17, count 0 2006.169.08:22:37.18#ibcon#*before return 0, iclass 17, count 0 2006.169.08:22:37.18#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:22:37.18#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:22:37.18#ibcon#about to clear, iclass 17 cls_cnt 0 2006.169.08:22:37.18#ibcon#cleared, iclass 17 cls_cnt 0 2006.169.08:22:37.18$vc4f8/valo=8,852.99 2006.169.08:22:37.18#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.169.08:22:37.18#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.169.08:22:37.18#ibcon#ireg 17 cls_cnt 0 2006.169.08:22:37.18#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.169.08:22:37.18#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.169.08:22:37.18#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.169.08:22:37.18#ibcon#enter wrdev, iclass 19, count 0 2006.169.08:22:37.18#ibcon#first serial, iclass 19, count 0 2006.169.08:22:37.18#ibcon#enter sib2, iclass 19, count 0 2006.169.08:22:37.18#ibcon#flushed, iclass 19, count 0 2006.169.08:22:37.18#ibcon#about to write, iclass 19, count 0 2006.169.08:22:37.18#ibcon#wrote, iclass 19, count 0 2006.169.08:22:37.18#ibcon#about to read 3, iclass 19, count 0 2006.169.08:22:37.20#ibcon#read 3, iclass 19, count 0 2006.169.08:22:37.20#ibcon#about to read 4, iclass 19, count 0 2006.169.08:22:37.20#ibcon#read 4, iclass 19, count 0 2006.169.08:22:37.20#ibcon#about to read 5, iclass 19, count 0 2006.169.08:22:37.20#ibcon#read 5, iclass 19, count 0 2006.169.08:22:37.20#ibcon#about to read 6, iclass 19, count 0 2006.169.08:22:37.20#ibcon#read 6, iclass 19, count 0 2006.169.08:22:37.20#ibcon#end of sib2, iclass 19, count 0 2006.169.08:22:37.20#ibcon#*mode == 0, iclass 19, count 0 2006.169.08:22:37.20#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.169.08:22:37.20#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.08:22:37.20#ibcon#*before write, iclass 19, count 0 2006.169.08:22:37.20#ibcon#enter sib2, iclass 19, count 0 2006.169.08:22:37.20#ibcon#flushed, iclass 19, count 0 2006.169.08:22:37.20#ibcon#about to write, iclass 19, count 0 2006.169.08:22:37.20#ibcon#wrote, iclass 19, count 0 2006.169.08:22:37.20#ibcon#about to read 3, iclass 19, count 0 2006.169.08:22:37.24#ibcon#read 3, iclass 19, count 0 2006.169.08:22:37.24#ibcon#about to read 4, iclass 19, count 0 2006.169.08:22:37.24#ibcon#read 4, iclass 19, count 0 2006.169.08:22:37.24#ibcon#about to read 5, iclass 19, count 0 2006.169.08:22:37.24#ibcon#read 5, iclass 19, count 0 2006.169.08:22:37.24#ibcon#about to read 6, iclass 19, count 0 2006.169.08:22:37.24#ibcon#read 6, iclass 19, count 0 2006.169.08:22:37.24#ibcon#end of sib2, iclass 19, count 0 2006.169.08:22:37.24#ibcon#*after write, iclass 19, count 0 2006.169.08:22:37.24#ibcon#*before return 0, iclass 19, count 0 2006.169.08:22:37.24#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.169.08:22:37.24#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.169.08:22:37.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.169.08:22:37.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.169.08:22:37.24$vc4f8/va=8,7 2006.169.08:22:37.24#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.169.08:22:37.24#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.169.08:22:37.24#ibcon#ireg 11 cls_cnt 2 2006.169.08:22:37.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.169.08:22:37.30#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.169.08:22:37.30#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.169.08:22:37.30#ibcon#enter wrdev, iclass 21, count 2 2006.169.08:22:37.30#ibcon#first serial, iclass 21, count 2 2006.169.08:22:37.30#ibcon#enter sib2, iclass 21, count 2 2006.169.08:22:37.30#ibcon#flushed, iclass 21, count 2 2006.169.08:22:37.30#ibcon#about to write, iclass 21, count 2 2006.169.08:22:37.30#ibcon#wrote, iclass 21, count 2 2006.169.08:22:37.30#ibcon#about to read 3, iclass 21, count 2 2006.169.08:22:37.32#ibcon#read 3, iclass 21, count 2 2006.169.08:22:37.32#ibcon#about to read 4, iclass 21, count 2 2006.169.08:22:37.32#ibcon#read 4, iclass 21, count 2 2006.169.08:22:37.32#ibcon#about to read 5, iclass 21, count 2 2006.169.08:22:37.32#ibcon#read 5, iclass 21, count 2 2006.169.08:22:37.32#ibcon#about to read 6, iclass 21, count 2 2006.169.08:22:37.32#ibcon#read 6, iclass 21, count 2 2006.169.08:22:37.32#ibcon#end of sib2, iclass 21, count 2 2006.169.08:22:37.32#ibcon#*mode == 0, iclass 21, count 2 2006.169.08:22:37.32#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.169.08:22:37.32#ibcon#[25=AT08-07\r\n] 2006.169.08:22:37.32#ibcon#*before write, iclass 21, count 2 2006.169.08:22:37.32#ibcon#enter sib2, iclass 21, count 2 2006.169.08:22:37.32#ibcon#flushed, iclass 21, count 2 2006.169.08:22:37.32#ibcon#about to write, iclass 21, count 2 2006.169.08:22:37.32#ibcon#wrote, iclass 21, count 2 2006.169.08:22:37.32#ibcon#about to read 3, iclass 21, count 2 2006.169.08:22:37.35#ibcon#read 3, iclass 21, count 2 2006.169.08:22:37.35#ibcon#about to read 4, iclass 21, count 2 2006.169.08:22:37.35#ibcon#read 4, iclass 21, count 2 2006.169.08:22:37.35#ibcon#about to read 5, iclass 21, count 2 2006.169.08:22:37.35#ibcon#read 5, iclass 21, count 2 2006.169.08:22:37.35#ibcon#about to read 6, iclass 21, count 2 2006.169.08:22:37.35#ibcon#read 6, iclass 21, count 2 2006.169.08:22:37.35#ibcon#end of sib2, iclass 21, count 2 2006.169.08:22:37.35#ibcon#*after write, iclass 21, count 2 2006.169.08:22:37.35#ibcon#*before return 0, iclass 21, count 2 2006.169.08:22:37.35#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.169.08:22:37.35#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.169.08:22:37.35#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.169.08:22:37.35#ibcon#ireg 7 cls_cnt 0 2006.169.08:22:37.35#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.169.08:22:37.47#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.169.08:22:37.47#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.169.08:22:37.47#ibcon#enter wrdev, iclass 21, count 0 2006.169.08:22:37.47#ibcon#first serial, iclass 21, count 0 2006.169.08:22:37.47#ibcon#enter sib2, iclass 21, count 0 2006.169.08:22:37.47#ibcon#flushed, iclass 21, count 0 2006.169.08:22:37.47#ibcon#about to write, iclass 21, count 0 2006.169.08:22:37.47#ibcon#wrote, iclass 21, count 0 2006.169.08:22:37.47#ibcon#about to read 3, iclass 21, count 0 2006.169.08:22:37.49#ibcon#read 3, iclass 21, count 0 2006.169.08:22:37.49#ibcon#about to read 4, iclass 21, count 0 2006.169.08:22:37.49#ibcon#read 4, iclass 21, count 0 2006.169.08:22:37.49#ibcon#about to read 5, iclass 21, count 0 2006.169.08:22:37.49#ibcon#read 5, iclass 21, count 0 2006.169.08:22:37.49#ibcon#about to read 6, iclass 21, count 0 2006.169.08:22:37.49#ibcon#read 6, iclass 21, count 0 2006.169.08:22:37.49#ibcon#end of sib2, iclass 21, count 0 2006.169.08:22:37.49#ibcon#*mode == 0, iclass 21, count 0 2006.169.08:22:37.49#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.169.08:22:37.49#ibcon#[25=USB\r\n] 2006.169.08:22:37.49#ibcon#*before write, iclass 21, count 0 2006.169.08:22:37.49#ibcon#enter sib2, iclass 21, count 0 2006.169.08:22:37.49#ibcon#flushed, iclass 21, count 0 2006.169.08:22:37.49#ibcon#about to write, iclass 21, count 0 2006.169.08:22:37.49#ibcon#wrote, iclass 21, count 0 2006.169.08:22:37.49#ibcon#about to read 3, iclass 21, count 0 2006.169.08:22:37.52#ibcon#read 3, iclass 21, count 0 2006.169.08:22:37.52#ibcon#about to read 4, iclass 21, count 0 2006.169.08:22:37.52#ibcon#read 4, iclass 21, count 0 2006.169.08:22:37.52#ibcon#about to read 5, iclass 21, count 0 2006.169.08:22:37.52#ibcon#read 5, iclass 21, count 0 2006.169.08:22:37.52#ibcon#about to read 6, iclass 21, count 0 2006.169.08:22:37.52#ibcon#read 6, iclass 21, count 0 2006.169.08:22:37.52#ibcon#end of sib2, iclass 21, count 0 2006.169.08:22:37.52#ibcon#*after write, iclass 21, count 0 2006.169.08:22:37.52#ibcon#*before return 0, iclass 21, count 0 2006.169.08:22:37.52#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.169.08:22:37.52#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.169.08:22:37.52#ibcon#about to clear, iclass 21 cls_cnt 0 2006.169.08:22:37.52#ibcon#cleared, iclass 21 cls_cnt 0 2006.169.08:22:37.52$vc4f8/vblo=1,632.99 2006.169.08:22:37.52#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.169.08:22:37.52#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.169.08:22:37.52#ibcon#ireg 17 cls_cnt 0 2006.169.08:22:37.52#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:22:37.52#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:22:37.52#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:22:37.52#ibcon#enter wrdev, iclass 23, count 0 2006.169.08:22:37.52#ibcon#first serial, iclass 23, count 0 2006.169.08:22:37.52#ibcon#enter sib2, iclass 23, count 0 2006.169.08:22:37.52#ibcon#flushed, iclass 23, count 0 2006.169.08:22:37.52#ibcon#about to write, iclass 23, count 0 2006.169.08:22:37.52#ibcon#wrote, iclass 23, count 0 2006.169.08:22:37.52#ibcon#about to read 3, iclass 23, count 0 2006.169.08:22:37.54#ibcon#read 3, iclass 23, count 0 2006.169.08:22:37.54#ibcon#about to read 4, iclass 23, count 0 2006.169.08:22:37.54#ibcon#read 4, iclass 23, count 0 2006.169.08:22:37.54#ibcon#about to read 5, iclass 23, count 0 2006.169.08:22:37.54#ibcon#read 5, iclass 23, count 0 2006.169.08:22:37.54#ibcon#about to read 6, iclass 23, count 0 2006.169.08:22:37.54#ibcon#read 6, iclass 23, count 0 2006.169.08:22:37.54#ibcon#end of sib2, iclass 23, count 0 2006.169.08:22:37.54#ibcon#*mode == 0, iclass 23, count 0 2006.169.08:22:37.54#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.169.08:22:37.54#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.08:22:37.54#ibcon#*before write, iclass 23, count 0 2006.169.08:22:37.54#ibcon#enter sib2, iclass 23, count 0 2006.169.08:22:37.54#ibcon#flushed, iclass 23, count 0 2006.169.08:22:37.54#ibcon#about to write, iclass 23, count 0 2006.169.08:22:37.54#ibcon#wrote, iclass 23, count 0 2006.169.08:22:37.54#ibcon#about to read 3, iclass 23, count 0 2006.169.08:22:37.58#ibcon#read 3, iclass 23, count 0 2006.169.08:22:37.58#ibcon#about to read 4, iclass 23, count 0 2006.169.08:22:37.58#ibcon#read 4, iclass 23, count 0 2006.169.08:22:37.58#ibcon#about to read 5, iclass 23, count 0 2006.169.08:22:37.58#ibcon#read 5, iclass 23, count 0 2006.169.08:22:37.58#ibcon#about to read 6, iclass 23, count 0 2006.169.08:22:37.58#ibcon#read 6, iclass 23, count 0 2006.169.08:22:37.58#ibcon#end of sib2, iclass 23, count 0 2006.169.08:22:37.58#ibcon#*after write, iclass 23, count 0 2006.169.08:22:37.58#ibcon#*before return 0, iclass 23, count 0 2006.169.08:22:37.58#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:22:37.58#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.169.08:22:37.58#ibcon#about to clear, iclass 23 cls_cnt 0 2006.169.08:22:37.58#ibcon#cleared, iclass 23 cls_cnt 0 2006.169.08:22:37.58$vc4f8/vb=1,4 2006.169.08:22:37.58#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.169.08:22:37.58#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.169.08:22:37.58#ibcon#ireg 11 cls_cnt 2 2006.169.08:22:37.58#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:22:37.58#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:22:37.58#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:22:37.58#ibcon#enter wrdev, iclass 25, count 2 2006.169.08:22:37.58#ibcon#first serial, iclass 25, count 2 2006.169.08:22:37.58#ibcon#enter sib2, iclass 25, count 2 2006.169.08:22:37.58#ibcon#flushed, iclass 25, count 2 2006.169.08:22:37.58#ibcon#about to write, iclass 25, count 2 2006.169.08:22:37.58#ibcon#wrote, iclass 25, count 2 2006.169.08:22:37.58#ibcon#about to read 3, iclass 25, count 2 2006.169.08:22:37.60#ibcon#read 3, iclass 25, count 2 2006.169.08:22:37.60#ibcon#about to read 4, iclass 25, count 2 2006.169.08:22:37.60#ibcon#read 4, iclass 25, count 2 2006.169.08:22:37.60#ibcon#about to read 5, iclass 25, count 2 2006.169.08:22:37.60#ibcon#read 5, iclass 25, count 2 2006.169.08:22:37.60#ibcon#about to read 6, iclass 25, count 2 2006.169.08:22:37.60#ibcon#read 6, iclass 25, count 2 2006.169.08:22:37.60#ibcon#end of sib2, iclass 25, count 2 2006.169.08:22:37.60#ibcon#*mode == 0, iclass 25, count 2 2006.169.08:22:37.60#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.169.08:22:37.60#ibcon#[27=AT01-04\r\n] 2006.169.08:22:37.60#ibcon#*before write, iclass 25, count 2 2006.169.08:22:37.60#ibcon#enter sib2, iclass 25, count 2 2006.169.08:22:37.60#ibcon#flushed, iclass 25, count 2 2006.169.08:22:37.60#ibcon#about to write, iclass 25, count 2 2006.169.08:22:37.60#ibcon#wrote, iclass 25, count 2 2006.169.08:22:37.60#ibcon#about to read 3, iclass 25, count 2 2006.169.08:22:37.63#ibcon#read 3, iclass 25, count 2 2006.169.08:22:37.63#ibcon#about to read 4, iclass 25, count 2 2006.169.08:22:37.63#ibcon#read 4, iclass 25, count 2 2006.169.08:22:37.63#ibcon#about to read 5, iclass 25, count 2 2006.169.08:22:37.63#ibcon#read 5, iclass 25, count 2 2006.169.08:22:37.63#ibcon#about to read 6, iclass 25, count 2 2006.169.08:22:37.63#ibcon#read 6, iclass 25, count 2 2006.169.08:22:37.63#ibcon#end of sib2, iclass 25, count 2 2006.169.08:22:37.63#ibcon#*after write, iclass 25, count 2 2006.169.08:22:37.63#ibcon#*before return 0, iclass 25, count 2 2006.169.08:22:37.63#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:22:37.63#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.169.08:22:37.63#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.169.08:22:37.63#ibcon#ireg 7 cls_cnt 0 2006.169.08:22:37.63#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:22:37.75#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:22:37.75#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:22:37.75#ibcon#enter wrdev, iclass 25, count 0 2006.169.08:22:37.75#ibcon#first serial, iclass 25, count 0 2006.169.08:22:37.75#ibcon#enter sib2, iclass 25, count 0 2006.169.08:22:37.75#ibcon#flushed, iclass 25, count 0 2006.169.08:22:37.75#ibcon#about to write, iclass 25, count 0 2006.169.08:22:37.75#ibcon#wrote, iclass 25, count 0 2006.169.08:22:37.75#ibcon#about to read 3, iclass 25, count 0 2006.169.08:22:37.77#ibcon#read 3, iclass 25, count 0 2006.169.08:22:37.77#ibcon#about to read 4, iclass 25, count 0 2006.169.08:22:37.77#ibcon#read 4, iclass 25, count 0 2006.169.08:22:37.77#ibcon#about to read 5, iclass 25, count 0 2006.169.08:22:37.77#ibcon#read 5, iclass 25, count 0 2006.169.08:22:37.77#ibcon#about to read 6, iclass 25, count 0 2006.169.08:22:37.77#ibcon#read 6, iclass 25, count 0 2006.169.08:22:37.77#ibcon#end of sib2, iclass 25, count 0 2006.169.08:22:37.77#ibcon#*mode == 0, iclass 25, count 0 2006.169.08:22:37.77#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.169.08:22:37.77#ibcon#[27=USB\r\n] 2006.169.08:22:37.77#ibcon#*before write, iclass 25, count 0 2006.169.08:22:37.77#ibcon#enter sib2, iclass 25, count 0 2006.169.08:22:37.77#ibcon#flushed, iclass 25, count 0 2006.169.08:22:37.77#ibcon#about to write, iclass 25, count 0 2006.169.08:22:37.77#ibcon#wrote, iclass 25, count 0 2006.169.08:22:37.77#ibcon#about to read 3, iclass 25, count 0 2006.169.08:22:37.80#ibcon#read 3, iclass 25, count 0 2006.169.08:22:37.80#ibcon#about to read 4, iclass 25, count 0 2006.169.08:22:37.80#ibcon#read 4, iclass 25, count 0 2006.169.08:22:37.80#ibcon#about to read 5, iclass 25, count 0 2006.169.08:22:37.80#ibcon#read 5, iclass 25, count 0 2006.169.08:22:37.80#ibcon#about to read 6, iclass 25, count 0 2006.169.08:22:37.80#ibcon#read 6, iclass 25, count 0 2006.169.08:22:37.80#ibcon#end of sib2, iclass 25, count 0 2006.169.08:22:37.80#ibcon#*after write, iclass 25, count 0 2006.169.08:22:37.80#ibcon#*before return 0, iclass 25, count 0 2006.169.08:22:37.80#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:22:37.80#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.169.08:22:37.80#ibcon#about to clear, iclass 25 cls_cnt 0 2006.169.08:22:37.80#ibcon#cleared, iclass 25 cls_cnt 0 2006.169.08:22:37.80$vc4f8/vblo=2,640.99 2006.169.08:22:37.80#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.169.08:22:37.80#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.169.08:22:37.80#ibcon#ireg 17 cls_cnt 0 2006.169.08:22:37.80#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:22:37.80#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:22:37.80#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:22:37.80#ibcon#enter wrdev, iclass 27, count 0 2006.169.08:22:37.80#ibcon#first serial, iclass 27, count 0 2006.169.08:22:37.80#ibcon#enter sib2, iclass 27, count 0 2006.169.08:22:37.80#ibcon#flushed, iclass 27, count 0 2006.169.08:22:37.80#ibcon#about to write, iclass 27, count 0 2006.169.08:22:37.80#ibcon#wrote, iclass 27, count 0 2006.169.08:22:37.80#ibcon#about to read 3, iclass 27, count 0 2006.169.08:22:37.82#ibcon#read 3, iclass 27, count 0 2006.169.08:22:37.82#ibcon#about to read 4, iclass 27, count 0 2006.169.08:22:37.82#ibcon#read 4, iclass 27, count 0 2006.169.08:22:37.82#ibcon#about to read 5, iclass 27, count 0 2006.169.08:22:37.82#ibcon#read 5, iclass 27, count 0 2006.169.08:22:37.82#ibcon#about to read 6, iclass 27, count 0 2006.169.08:22:37.82#ibcon#read 6, iclass 27, count 0 2006.169.08:22:37.82#ibcon#end of sib2, iclass 27, count 0 2006.169.08:22:37.82#ibcon#*mode == 0, iclass 27, count 0 2006.169.08:22:37.82#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.169.08:22:37.82#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.08:22:37.82#ibcon#*before write, iclass 27, count 0 2006.169.08:22:37.82#ibcon#enter sib2, iclass 27, count 0 2006.169.08:22:37.82#ibcon#flushed, iclass 27, count 0 2006.169.08:22:37.82#ibcon#about to write, iclass 27, count 0 2006.169.08:22:37.82#ibcon#wrote, iclass 27, count 0 2006.169.08:22:37.82#ibcon#about to read 3, iclass 27, count 0 2006.169.08:22:37.86#ibcon#read 3, iclass 27, count 0 2006.169.08:22:37.86#ibcon#about to read 4, iclass 27, count 0 2006.169.08:22:37.86#ibcon#read 4, iclass 27, count 0 2006.169.08:22:37.86#ibcon#about to read 5, iclass 27, count 0 2006.169.08:22:37.86#ibcon#read 5, iclass 27, count 0 2006.169.08:22:37.86#ibcon#about to read 6, iclass 27, count 0 2006.169.08:22:37.86#ibcon#read 6, iclass 27, count 0 2006.169.08:22:37.86#ibcon#end of sib2, iclass 27, count 0 2006.169.08:22:37.86#ibcon#*after write, iclass 27, count 0 2006.169.08:22:37.86#ibcon#*before return 0, iclass 27, count 0 2006.169.08:22:37.86#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:22:37.86#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.169.08:22:37.86#ibcon#about to clear, iclass 27 cls_cnt 0 2006.169.08:22:37.86#ibcon#cleared, iclass 27 cls_cnt 0 2006.169.08:22:37.86$vc4f8/vb=2,4 2006.169.08:22:37.86#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.169.08:22:37.86#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.169.08:22:37.86#ibcon#ireg 11 cls_cnt 2 2006.169.08:22:37.86#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:22:37.92#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:22:37.92#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:22:37.92#ibcon#enter wrdev, iclass 29, count 2 2006.169.08:22:37.92#ibcon#first serial, iclass 29, count 2 2006.169.08:22:37.92#ibcon#enter sib2, iclass 29, count 2 2006.169.08:22:37.92#ibcon#flushed, iclass 29, count 2 2006.169.08:22:37.92#ibcon#about to write, iclass 29, count 2 2006.169.08:22:37.92#ibcon#wrote, iclass 29, count 2 2006.169.08:22:37.92#ibcon#about to read 3, iclass 29, count 2 2006.169.08:22:37.94#ibcon#read 3, iclass 29, count 2 2006.169.08:22:37.94#ibcon#about to read 4, iclass 29, count 2 2006.169.08:22:37.94#ibcon#read 4, iclass 29, count 2 2006.169.08:22:37.94#ibcon#about to read 5, iclass 29, count 2 2006.169.08:22:37.94#ibcon#read 5, iclass 29, count 2 2006.169.08:22:37.94#ibcon#about to read 6, iclass 29, count 2 2006.169.08:22:37.94#ibcon#read 6, iclass 29, count 2 2006.169.08:22:37.94#ibcon#end of sib2, iclass 29, count 2 2006.169.08:22:37.94#ibcon#*mode == 0, iclass 29, count 2 2006.169.08:22:37.94#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.169.08:22:37.94#ibcon#[27=AT02-04\r\n] 2006.169.08:22:37.94#ibcon#*before write, iclass 29, count 2 2006.169.08:22:37.94#ibcon#enter sib2, iclass 29, count 2 2006.169.08:22:37.94#ibcon#flushed, iclass 29, count 2 2006.169.08:22:37.94#ibcon#about to write, iclass 29, count 2 2006.169.08:22:37.94#ibcon#wrote, iclass 29, count 2 2006.169.08:22:37.94#ibcon#about to read 3, iclass 29, count 2 2006.169.08:22:37.97#ibcon#read 3, iclass 29, count 2 2006.169.08:22:37.97#ibcon#about to read 4, iclass 29, count 2 2006.169.08:22:37.97#ibcon#read 4, iclass 29, count 2 2006.169.08:22:37.97#ibcon#about to read 5, iclass 29, count 2 2006.169.08:22:37.97#ibcon#read 5, iclass 29, count 2 2006.169.08:22:37.97#ibcon#about to read 6, iclass 29, count 2 2006.169.08:22:37.97#ibcon#read 6, iclass 29, count 2 2006.169.08:22:37.97#ibcon#end of sib2, iclass 29, count 2 2006.169.08:22:37.97#ibcon#*after write, iclass 29, count 2 2006.169.08:22:37.97#ibcon#*before return 0, iclass 29, count 2 2006.169.08:22:37.97#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:22:37.97#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.169.08:22:37.97#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.169.08:22:37.97#ibcon#ireg 7 cls_cnt 0 2006.169.08:22:37.97#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:22:38.09#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:22:38.09#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:22:38.09#ibcon#enter wrdev, iclass 29, count 0 2006.169.08:22:38.09#ibcon#first serial, iclass 29, count 0 2006.169.08:22:38.09#ibcon#enter sib2, iclass 29, count 0 2006.169.08:22:38.09#ibcon#flushed, iclass 29, count 0 2006.169.08:22:38.09#ibcon#about to write, iclass 29, count 0 2006.169.08:22:38.09#ibcon#wrote, iclass 29, count 0 2006.169.08:22:38.09#ibcon#about to read 3, iclass 29, count 0 2006.169.08:22:38.11#ibcon#read 3, iclass 29, count 0 2006.169.08:22:38.11#ibcon#about to read 4, iclass 29, count 0 2006.169.08:22:38.11#ibcon#read 4, iclass 29, count 0 2006.169.08:22:38.11#ibcon#about to read 5, iclass 29, count 0 2006.169.08:22:38.11#ibcon#read 5, iclass 29, count 0 2006.169.08:22:38.11#ibcon#about to read 6, iclass 29, count 0 2006.169.08:22:38.11#ibcon#read 6, iclass 29, count 0 2006.169.08:22:38.11#ibcon#end of sib2, iclass 29, count 0 2006.169.08:22:38.11#ibcon#*mode == 0, iclass 29, count 0 2006.169.08:22:38.11#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.169.08:22:38.11#ibcon#[27=USB\r\n] 2006.169.08:22:38.11#ibcon#*before write, iclass 29, count 0 2006.169.08:22:38.11#ibcon#enter sib2, iclass 29, count 0 2006.169.08:22:38.11#ibcon#flushed, iclass 29, count 0 2006.169.08:22:38.11#ibcon#about to write, iclass 29, count 0 2006.169.08:22:38.11#ibcon#wrote, iclass 29, count 0 2006.169.08:22:38.11#ibcon#about to read 3, iclass 29, count 0 2006.169.08:22:38.14#ibcon#read 3, iclass 29, count 0 2006.169.08:22:38.14#ibcon#about to read 4, iclass 29, count 0 2006.169.08:22:38.14#ibcon#read 4, iclass 29, count 0 2006.169.08:22:38.14#ibcon#about to read 5, iclass 29, count 0 2006.169.08:22:38.14#ibcon#read 5, iclass 29, count 0 2006.169.08:22:38.14#ibcon#about to read 6, iclass 29, count 0 2006.169.08:22:38.14#ibcon#read 6, iclass 29, count 0 2006.169.08:22:38.14#ibcon#end of sib2, iclass 29, count 0 2006.169.08:22:38.14#ibcon#*after write, iclass 29, count 0 2006.169.08:22:38.14#ibcon#*before return 0, iclass 29, count 0 2006.169.08:22:38.14#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:22:38.14#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.169.08:22:38.14#ibcon#about to clear, iclass 29 cls_cnt 0 2006.169.08:22:38.14#ibcon#cleared, iclass 29 cls_cnt 0 2006.169.08:22:38.14$vc4f8/vblo=3,656.99 2006.169.08:22:38.14#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.169.08:22:38.14#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.169.08:22:38.14#ibcon#ireg 17 cls_cnt 0 2006.169.08:22:38.14#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:22:38.14#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:22:38.14#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:22:38.14#ibcon#enter wrdev, iclass 31, count 0 2006.169.08:22:38.14#ibcon#first serial, iclass 31, count 0 2006.169.08:22:38.14#ibcon#enter sib2, iclass 31, count 0 2006.169.08:22:38.14#ibcon#flushed, iclass 31, count 0 2006.169.08:22:38.14#ibcon#about to write, iclass 31, count 0 2006.169.08:22:38.14#ibcon#wrote, iclass 31, count 0 2006.169.08:22:38.14#ibcon#about to read 3, iclass 31, count 0 2006.169.08:22:38.16#ibcon#read 3, iclass 31, count 0 2006.169.08:22:38.16#ibcon#about to read 4, iclass 31, count 0 2006.169.08:22:38.16#ibcon#read 4, iclass 31, count 0 2006.169.08:22:38.16#ibcon#about to read 5, iclass 31, count 0 2006.169.08:22:38.16#ibcon#read 5, iclass 31, count 0 2006.169.08:22:38.16#ibcon#about to read 6, iclass 31, count 0 2006.169.08:22:38.16#ibcon#read 6, iclass 31, count 0 2006.169.08:22:38.16#ibcon#end of sib2, iclass 31, count 0 2006.169.08:22:38.16#ibcon#*mode == 0, iclass 31, count 0 2006.169.08:22:38.16#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.169.08:22:38.16#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.08:22:38.16#ibcon#*before write, iclass 31, count 0 2006.169.08:22:38.16#ibcon#enter sib2, iclass 31, count 0 2006.169.08:22:38.16#ibcon#flushed, iclass 31, count 0 2006.169.08:22:38.16#ibcon#about to write, iclass 31, count 0 2006.169.08:22:38.16#ibcon#wrote, iclass 31, count 0 2006.169.08:22:38.16#ibcon#about to read 3, iclass 31, count 0 2006.169.08:22:38.20#ibcon#read 3, iclass 31, count 0 2006.169.08:22:38.20#ibcon#about to read 4, iclass 31, count 0 2006.169.08:22:38.20#ibcon#read 4, iclass 31, count 0 2006.169.08:22:38.20#ibcon#about to read 5, iclass 31, count 0 2006.169.08:22:38.20#ibcon#read 5, iclass 31, count 0 2006.169.08:22:38.20#ibcon#about to read 6, iclass 31, count 0 2006.169.08:22:38.20#ibcon#read 6, iclass 31, count 0 2006.169.08:22:38.20#ibcon#end of sib2, iclass 31, count 0 2006.169.08:22:38.20#ibcon#*after write, iclass 31, count 0 2006.169.08:22:38.20#ibcon#*before return 0, iclass 31, count 0 2006.169.08:22:38.20#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:22:38.20#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.169.08:22:38.20#ibcon#about to clear, iclass 31 cls_cnt 0 2006.169.08:22:38.20#ibcon#cleared, iclass 31 cls_cnt 0 2006.169.08:22:38.20$vc4f8/vb=3,4 2006.169.08:22:38.20#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.169.08:22:38.20#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.169.08:22:38.20#ibcon#ireg 11 cls_cnt 2 2006.169.08:22:38.20#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:22:38.26#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:22:38.26#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:22:38.26#ibcon#enter wrdev, iclass 33, count 2 2006.169.08:22:38.26#ibcon#first serial, iclass 33, count 2 2006.169.08:22:38.26#ibcon#enter sib2, iclass 33, count 2 2006.169.08:22:38.26#ibcon#flushed, iclass 33, count 2 2006.169.08:22:38.26#ibcon#about to write, iclass 33, count 2 2006.169.08:22:38.26#ibcon#wrote, iclass 33, count 2 2006.169.08:22:38.26#ibcon#about to read 3, iclass 33, count 2 2006.169.08:22:38.28#ibcon#read 3, iclass 33, count 2 2006.169.08:22:38.28#ibcon#about to read 4, iclass 33, count 2 2006.169.08:22:38.28#ibcon#read 4, iclass 33, count 2 2006.169.08:22:38.28#ibcon#about to read 5, iclass 33, count 2 2006.169.08:22:38.28#ibcon#read 5, iclass 33, count 2 2006.169.08:22:38.28#ibcon#about to read 6, iclass 33, count 2 2006.169.08:22:38.28#ibcon#read 6, iclass 33, count 2 2006.169.08:22:38.28#ibcon#end of sib2, iclass 33, count 2 2006.169.08:22:38.28#ibcon#*mode == 0, iclass 33, count 2 2006.169.08:22:38.28#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.169.08:22:38.28#ibcon#[27=AT03-04\r\n] 2006.169.08:22:38.28#ibcon#*before write, iclass 33, count 2 2006.169.08:22:38.28#ibcon#enter sib2, iclass 33, count 2 2006.169.08:22:38.28#ibcon#flushed, iclass 33, count 2 2006.169.08:22:38.28#ibcon#about to write, iclass 33, count 2 2006.169.08:22:38.28#ibcon#wrote, iclass 33, count 2 2006.169.08:22:38.28#ibcon#about to read 3, iclass 33, count 2 2006.169.08:22:38.31#ibcon#read 3, iclass 33, count 2 2006.169.08:22:38.31#ibcon#about to read 4, iclass 33, count 2 2006.169.08:22:38.31#ibcon#read 4, iclass 33, count 2 2006.169.08:22:38.31#ibcon#about to read 5, iclass 33, count 2 2006.169.08:22:38.31#ibcon#read 5, iclass 33, count 2 2006.169.08:22:38.31#ibcon#about to read 6, iclass 33, count 2 2006.169.08:22:38.31#ibcon#read 6, iclass 33, count 2 2006.169.08:22:38.31#ibcon#end of sib2, iclass 33, count 2 2006.169.08:22:38.31#ibcon#*after write, iclass 33, count 2 2006.169.08:22:38.31#ibcon#*before return 0, iclass 33, count 2 2006.169.08:22:38.31#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:22:38.31#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.169.08:22:38.31#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.169.08:22:38.31#ibcon#ireg 7 cls_cnt 0 2006.169.08:22:38.31#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:22:38.43#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:22:38.43#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:22:38.43#ibcon#enter wrdev, iclass 33, count 0 2006.169.08:22:38.43#ibcon#first serial, iclass 33, count 0 2006.169.08:22:38.43#ibcon#enter sib2, iclass 33, count 0 2006.169.08:22:38.43#ibcon#flushed, iclass 33, count 0 2006.169.08:22:38.43#ibcon#about to write, iclass 33, count 0 2006.169.08:22:38.43#ibcon#wrote, iclass 33, count 0 2006.169.08:22:38.43#ibcon#about to read 3, iclass 33, count 0 2006.169.08:22:38.45#ibcon#read 3, iclass 33, count 0 2006.169.08:22:38.45#ibcon#about to read 4, iclass 33, count 0 2006.169.08:22:38.45#ibcon#read 4, iclass 33, count 0 2006.169.08:22:38.45#ibcon#about to read 5, iclass 33, count 0 2006.169.08:22:38.45#ibcon#read 5, iclass 33, count 0 2006.169.08:22:38.45#ibcon#about to read 6, iclass 33, count 0 2006.169.08:22:38.45#ibcon#read 6, iclass 33, count 0 2006.169.08:22:38.45#ibcon#end of sib2, iclass 33, count 0 2006.169.08:22:38.45#ibcon#*mode == 0, iclass 33, count 0 2006.169.08:22:38.45#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.169.08:22:38.45#ibcon#[27=USB\r\n] 2006.169.08:22:38.45#ibcon#*before write, iclass 33, count 0 2006.169.08:22:38.45#ibcon#enter sib2, iclass 33, count 0 2006.169.08:22:38.45#ibcon#flushed, iclass 33, count 0 2006.169.08:22:38.45#ibcon#about to write, iclass 33, count 0 2006.169.08:22:38.45#ibcon#wrote, iclass 33, count 0 2006.169.08:22:38.45#ibcon#about to read 3, iclass 33, count 0 2006.169.08:22:38.48#ibcon#read 3, iclass 33, count 0 2006.169.08:22:38.48#ibcon#about to read 4, iclass 33, count 0 2006.169.08:22:38.48#ibcon#read 4, iclass 33, count 0 2006.169.08:22:38.48#ibcon#about to read 5, iclass 33, count 0 2006.169.08:22:38.48#ibcon#read 5, iclass 33, count 0 2006.169.08:22:38.48#ibcon#about to read 6, iclass 33, count 0 2006.169.08:22:38.48#ibcon#read 6, iclass 33, count 0 2006.169.08:22:38.48#ibcon#end of sib2, iclass 33, count 0 2006.169.08:22:38.48#ibcon#*after write, iclass 33, count 0 2006.169.08:22:38.48#ibcon#*before return 0, iclass 33, count 0 2006.169.08:22:38.48#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:22:38.48#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.169.08:22:38.48#ibcon#about to clear, iclass 33 cls_cnt 0 2006.169.08:22:38.48#ibcon#cleared, iclass 33 cls_cnt 0 2006.169.08:22:38.48$vc4f8/vblo=4,712.99 2006.169.08:22:38.48#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.169.08:22:38.48#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.169.08:22:38.48#ibcon#ireg 17 cls_cnt 0 2006.169.08:22:38.48#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:22:38.48#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:22:38.48#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:22:38.48#ibcon#enter wrdev, iclass 35, count 0 2006.169.08:22:38.48#ibcon#first serial, iclass 35, count 0 2006.169.08:22:38.48#ibcon#enter sib2, iclass 35, count 0 2006.169.08:22:38.48#ibcon#flushed, iclass 35, count 0 2006.169.08:22:38.48#ibcon#about to write, iclass 35, count 0 2006.169.08:22:38.48#ibcon#wrote, iclass 35, count 0 2006.169.08:22:38.48#ibcon#about to read 3, iclass 35, count 0 2006.169.08:22:38.50#ibcon#read 3, iclass 35, count 0 2006.169.08:22:38.50#ibcon#about to read 4, iclass 35, count 0 2006.169.08:22:38.50#ibcon#read 4, iclass 35, count 0 2006.169.08:22:38.50#ibcon#about to read 5, iclass 35, count 0 2006.169.08:22:38.50#ibcon#read 5, iclass 35, count 0 2006.169.08:22:38.50#ibcon#about to read 6, iclass 35, count 0 2006.169.08:22:38.50#ibcon#read 6, iclass 35, count 0 2006.169.08:22:38.50#ibcon#end of sib2, iclass 35, count 0 2006.169.08:22:38.50#ibcon#*mode == 0, iclass 35, count 0 2006.169.08:22:38.50#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.169.08:22:38.50#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.08:22:38.50#ibcon#*before write, iclass 35, count 0 2006.169.08:22:38.50#ibcon#enter sib2, iclass 35, count 0 2006.169.08:22:38.50#ibcon#flushed, iclass 35, count 0 2006.169.08:22:38.50#ibcon#about to write, iclass 35, count 0 2006.169.08:22:38.50#ibcon#wrote, iclass 35, count 0 2006.169.08:22:38.50#ibcon#about to read 3, iclass 35, count 0 2006.169.08:22:38.54#ibcon#read 3, iclass 35, count 0 2006.169.08:22:38.54#ibcon#about to read 4, iclass 35, count 0 2006.169.08:22:38.54#ibcon#read 4, iclass 35, count 0 2006.169.08:22:38.54#ibcon#about to read 5, iclass 35, count 0 2006.169.08:22:38.54#ibcon#read 5, iclass 35, count 0 2006.169.08:22:38.54#ibcon#about to read 6, iclass 35, count 0 2006.169.08:22:38.54#ibcon#read 6, iclass 35, count 0 2006.169.08:22:38.54#ibcon#end of sib2, iclass 35, count 0 2006.169.08:22:38.54#ibcon#*after write, iclass 35, count 0 2006.169.08:22:38.54#ibcon#*before return 0, iclass 35, count 0 2006.169.08:22:38.54#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:22:38.54#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.169.08:22:38.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.169.08:22:38.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.169.08:22:38.54$vc4f8/vb=4,4 2006.169.08:22:38.54#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.169.08:22:38.54#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.169.08:22:38.54#ibcon#ireg 11 cls_cnt 2 2006.169.08:22:38.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:22:38.60#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:22:38.60#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:22:38.60#ibcon#enter wrdev, iclass 37, count 2 2006.169.08:22:38.60#ibcon#first serial, iclass 37, count 2 2006.169.08:22:38.60#ibcon#enter sib2, iclass 37, count 2 2006.169.08:22:38.60#ibcon#flushed, iclass 37, count 2 2006.169.08:22:38.60#ibcon#about to write, iclass 37, count 2 2006.169.08:22:38.60#ibcon#wrote, iclass 37, count 2 2006.169.08:22:38.60#ibcon#about to read 3, iclass 37, count 2 2006.169.08:22:38.62#ibcon#read 3, iclass 37, count 2 2006.169.08:22:38.62#ibcon#about to read 4, iclass 37, count 2 2006.169.08:22:38.62#ibcon#read 4, iclass 37, count 2 2006.169.08:22:38.62#ibcon#about to read 5, iclass 37, count 2 2006.169.08:22:38.62#ibcon#read 5, iclass 37, count 2 2006.169.08:22:38.62#ibcon#about to read 6, iclass 37, count 2 2006.169.08:22:38.62#ibcon#read 6, iclass 37, count 2 2006.169.08:22:38.62#ibcon#end of sib2, iclass 37, count 2 2006.169.08:22:38.62#ibcon#*mode == 0, iclass 37, count 2 2006.169.08:22:38.62#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.169.08:22:38.62#ibcon#[27=AT04-04\r\n] 2006.169.08:22:38.62#ibcon#*before write, iclass 37, count 2 2006.169.08:22:38.62#ibcon#enter sib2, iclass 37, count 2 2006.169.08:22:38.62#ibcon#flushed, iclass 37, count 2 2006.169.08:22:38.62#ibcon#about to write, iclass 37, count 2 2006.169.08:22:38.62#ibcon#wrote, iclass 37, count 2 2006.169.08:22:38.62#ibcon#about to read 3, iclass 37, count 2 2006.169.08:22:38.65#ibcon#read 3, iclass 37, count 2 2006.169.08:22:38.65#ibcon#about to read 4, iclass 37, count 2 2006.169.08:22:38.65#ibcon#read 4, iclass 37, count 2 2006.169.08:22:38.65#ibcon#about to read 5, iclass 37, count 2 2006.169.08:22:38.65#ibcon#read 5, iclass 37, count 2 2006.169.08:22:38.65#ibcon#about to read 6, iclass 37, count 2 2006.169.08:22:38.65#ibcon#read 6, iclass 37, count 2 2006.169.08:22:38.65#ibcon#end of sib2, iclass 37, count 2 2006.169.08:22:38.65#ibcon#*after write, iclass 37, count 2 2006.169.08:22:38.65#ibcon#*before return 0, iclass 37, count 2 2006.169.08:22:38.65#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:22:38.65#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.169.08:22:38.65#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.169.08:22:38.65#ibcon#ireg 7 cls_cnt 0 2006.169.08:22:38.65#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:22:38.77#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:22:38.77#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:22:38.77#ibcon#enter wrdev, iclass 37, count 0 2006.169.08:22:38.77#ibcon#first serial, iclass 37, count 0 2006.169.08:22:38.77#ibcon#enter sib2, iclass 37, count 0 2006.169.08:22:38.77#ibcon#flushed, iclass 37, count 0 2006.169.08:22:38.77#ibcon#about to write, iclass 37, count 0 2006.169.08:22:38.77#ibcon#wrote, iclass 37, count 0 2006.169.08:22:38.77#ibcon#about to read 3, iclass 37, count 0 2006.169.08:22:38.79#ibcon#read 3, iclass 37, count 0 2006.169.08:22:38.79#ibcon#about to read 4, iclass 37, count 0 2006.169.08:22:38.79#ibcon#read 4, iclass 37, count 0 2006.169.08:22:38.79#ibcon#about to read 5, iclass 37, count 0 2006.169.08:22:38.79#ibcon#read 5, iclass 37, count 0 2006.169.08:22:38.79#ibcon#about to read 6, iclass 37, count 0 2006.169.08:22:38.79#ibcon#read 6, iclass 37, count 0 2006.169.08:22:38.79#ibcon#end of sib2, iclass 37, count 0 2006.169.08:22:38.79#ibcon#*mode == 0, iclass 37, count 0 2006.169.08:22:38.79#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.169.08:22:38.79#ibcon#[27=USB\r\n] 2006.169.08:22:38.79#ibcon#*before write, iclass 37, count 0 2006.169.08:22:38.79#ibcon#enter sib2, iclass 37, count 0 2006.169.08:22:38.79#ibcon#flushed, iclass 37, count 0 2006.169.08:22:38.79#ibcon#about to write, iclass 37, count 0 2006.169.08:22:38.79#ibcon#wrote, iclass 37, count 0 2006.169.08:22:38.79#ibcon#about to read 3, iclass 37, count 0 2006.169.08:22:38.82#ibcon#read 3, iclass 37, count 0 2006.169.08:22:38.82#ibcon#about to read 4, iclass 37, count 0 2006.169.08:22:38.82#ibcon#read 4, iclass 37, count 0 2006.169.08:22:38.82#ibcon#about to read 5, iclass 37, count 0 2006.169.08:22:38.82#ibcon#read 5, iclass 37, count 0 2006.169.08:22:38.82#ibcon#about to read 6, iclass 37, count 0 2006.169.08:22:38.82#ibcon#read 6, iclass 37, count 0 2006.169.08:22:38.82#ibcon#end of sib2, iclass 37, count 0 2006.169.08:22:38.82#ibcon#*after write, iclass 37, count 0 2006.169.08:22:38.82#ibcon#*before return 0, iclass 37, count 0 2006.169.08:22:38.82#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:22:38.82#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.169.08:22:38.82#ibcon#about to clear, iclass 37 cls_cnt 0 2006.169.08:22:38.82#ibcon#cleared, iclass 37 cls_cnt 0 2006.169.08:22:38.82$vc4f8/vblo=5,744.99 2006.169.08:22:38.82#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.169.08:22:38.82#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.169.08:22:38.82#ibcon#ireg 17 cls_cnt 0 2006.169.08:22:38.82#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:22:38.82#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:22:38.82#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:22:38.82#ibcon#enter wrdev, iclass 39, count 0 2006.169.08:22:38.82#ibcon#first serial, iclass 39, count 0 2006.169.08:22:38.82#ibcon#enter sib2, iclass 39, count 0 2006.169.08:22:38.82#ibcon#flushed, iclass 39, count 0 2006.169.08:22:38.82#ibcon#about to write, iclass 39, count 0 2006.169.08:22:38.82#ibcon#wrote, iclass 39, count 0 2006.169.08:22:38.82#ibcon#about to read 3, iclass 39, count 0 2006.169.08:22:38.84#ibcon#read 3, iclass 39, count 0 2006.169.08:22:38.84#ibcon#about to read 4, iclass 39, count 0 2006.169.08:22:38.84#ibcon#read 4, iclass 39, count 0 2006.169.08:22:38.84#ibcon#about to read 5, iclass 39, count 0 2006.169.08:22:38.84#ibcon#read 5, iclass 39, count 0 2006.169.08:22:38.84#ibcon#about to read 6, iclass 39, count 0 2006.169.08:22:38.84#ibcon#read 6, iclass 39, count 0 2006.169.08:22:38.84#ibcon#end of sib2, iclass 39, count 0 2006.169.08:22:38.84#ibcon#*mode == 0, iclass 39, count 0 2006.169.08:22:38.84#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.169.08:22:38.84#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.08:22:38.84#ibcon#*before write, iclass 39, count 0 2006.169.08:22:38.84#ibcon#enter sib2, iclass 39, count 0 2006.169.08:22:38.84#ibcon#flushed, iclass 39, count 0 2006.169.08:22:38.84#ibcon#about to write, iclass 39, count 0 2006.169.08:22:38.84#ibcon#wrote, iclass 39, count 0 2006.169.08:22:38.84#ibcon#about to read 3, iclass 39, count 0 2006.169.08:22:38.88#ibcon#read 3, iclass 39, count 0 2006.169.08:22:38.88#ibcon#about to read 4, iclass 39, count 0 2006.169.08:22:38.88#ibcon#read 4, iclass 39, count 0 2006.169.08:22:38.88#ibcon#about to read 5, iclass 39, count 0 2006.169.08:22:38.88#ibcon#read 5, iclass 39, count 0 2006.169.08:22:38.88#ibcon#about to read 6, iclass 39, count 0 2006.169.08:22:38.88#ibcon#read 6, iclass 39, count 0 2006.169.08:22:38.88#ibcon#end of sib2, iclass 39, count 0 2006.169.08:22:38.88#ibcon#*after write, iclass 39, count 0 2006.169.08:22:38.88#ibcon#*before return 0, iclass 39, count 0 2006.169.08:22:38.88#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:22:38.88#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.169.08:22:38.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.169.08:22:38.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.169.08:22:38.88$vc4f8/vb=5,4 2006.169.08:22:38.88#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.169.08:22:38.88#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.169.08:22:38.88#ibcon#ireg 11 cls_cnt 2 2006.169.08:22:38.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:22:38.94#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:22:38.94#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:22:38.94#ibcon#enter wrdev, iclass 3, count 2 2006.169.08:22:38.94#ibcon#first serial, iclass 3, count 2 2006.169.08:22:38.94#ibcon#enter sib2, iclass 3, count 2 2006.169.08:22:38.94#ibcon#flushed, iclass 3, count 2 2006.169.08:22:38.94#ibcon#about to write, iclass 3, count 2 2006.169.08:22:38.94#ibcon#wrote, iclass 3, count 2 2006.169.08:22:38.94#ibcon#about to read 3, iclass 3, count 2 2006.169.08:22:38.96#ibcon#read 3, iclass 3, count 2 2006.169.08:22:38.96#ibcon#about to read 4, iclass 3, count 2 2006.169.08:22:38.96#ibcon#read 4, iclass 3, count 2 2006.169.08:22:38.96#ibcon#about to read 5, iclass 3, count 2 2006.169.08:22:38.96#ibcon#read 5, iclass 3, count 2 2006.169.08:22:38.96#ibcon#about to read 6, iclass 3, count 2 2006.169.08:22:38.96#ibcon#read 6, iclass 3, count 2 2006.169.08:22:38.96#ibcon#end of sib2, iclass 3, count 2 2006.169.08:22:38.96#ibcon#*mode == 0, iclass 3, count 2 2006.169.08:22:38.96#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.169.08:22:38.96#ibcon#[27=AT05-04\r\n] 2006.169.08:22:38.96#ibcon#*before write, iclass 3, count 2 2006.169.08:22:38.96#ibcon#enter sib2, iclass 3, count 2 2006.169.08:22:38.96#ibcon#flushed, iclass 3, count 2 2006.169.08:22:38.96#ibcon#about to write, iclass 3, count 2 2006.169.08:22:38.96#ibcon#wrote, iclass 3, count 2 2006.169.08:22:38.96#ibcon#about to read 3, iclass 3, count 2 2006.169.08:22:38.99#ibcon#read 3, iclass 3, count 2 2006.169.08:22:38.99#ibcon#about to read 4, iclass 3, count 2 2006.169.08:22:38.99#ibcon#read 4, iclass 3, count 2 2006.169.08:22:38.99#ibcon#about to read 5, iclass 3, count 2 2006.169.08:22:38.99#ibcon#read 5, iclass 3, count 2 2006.169.08:22:38.99#ibcon#about to read 6, iclass 3, count 2 2006.169.08:22:38.99#ibcon#read 6, iclass 3, count 2 2006.169.08:22:38.99#ibcon#end of sib2, iclass 3, count 2 2006.169.08:22:38.99#ibcon#*after write, iclass 3, count 2 2006.169.08:22:38.99#ibcon#*before return 0, iclass 3, count 2 2006.169.08:22:38.99#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:22:38.99#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.169.08:22:38.99#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.169.08:22:38.99#ibcon#ireg 7 cls_cnt 0 2006.169.08:22:38.99#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:22:39.11#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:22:39.11#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:22:39.11#ibcon#enter wrdev, iclass 3, count 0 2006.169.08:22:39.11#ibcon#first serial, iclass 3, count 0 2006.169.08:22:39.11#ibcon#enter sib2, iclass 3, count 0 2006.169.08:22:39.11#ibcon#flushed, iclass 3, count 0 2006.169.08:22:39.11#ibcon#about to write, iclass 3, count 0 2006.169.08:22:39.11#ibcon#wrote, iclass 3, count 0 2006.169.08:22:39.11#ibcon#about to read 3, iclass 3, count 0 2006.169.08:22:39.13#ibcon#read 3, iclass 3, count 0 2006.169.08:22:39.13#ibcon#about to read 4, iclass 3, count 0 2006.169.08:22:39.13#ibcon#read 4, iclass 3, count 0 2006.169.08:22:39.13#ibcon#about to read 5, iclass 3, count 0 2006.169.08:22:39.13#ibcon#read 5, iclass 3, count 0 2006.169.08:22:39.13#ibcon#about to read 6, iclass 3, count 0 2006.169.08:22:39.13#ibcon#read 6, iclass 3, count 0 2006.169.08:22:39.13#ibcon#end of sib2, iclass 3, count 0 2006.169.08:22:39.13#ibcon#*mode == 0, iclass 3, count 0 2006.169.08:22:39.13#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.169.08:22:39.13#ibcon#[27=USB\r\n] 2006.169.08:22:39.13#ibcon#*before write, iclass 3, count 0 2006.169.08:22:39.13#ibcon#enter sib2, iclass 3, count 0 2006.169.08:22:39.13#ibcon#flushed, iclass 3, count 0 2006.169.08:22:39.13#ibcon#about to write, iclass 3, count 0 2006.169.08:22:39.13#ibcon#wrote, iclass 3, count 0 2006.169.08:22:39.13#ibcon#about to read 3, iclass 3, count 0 2006.169.08:22:39.16#ibcon#read 3, iclass 3, count 0 2006.169.08:22:39.16#ibcon#about to read 4, iclass 3, count 0 2006.169.08:22:39.16#ibcon#read 4, iclass 3, count 0 2006.169.08:22:39.16#ibcon#about to read 5, iclass 3, count 0 2006.169.08:22:39.16#ibcon#read 5, iclass 3, count 0 2006.169.08:22:39.16#ibcon#about to read 6, iclass 3, count 0 2006.169.08:22:39.16#ibcon#read 6, iclass 3, count 0 2006.169.08:22:39.16#ibcon#end of sib2, iclass 3, count 0 2006.169.08:22:39.16#ibcon#*after write, iclass 3, count 0 2006.169.08:22:39.16#ibcon#*before return 0, iclass 3, count 0 2006.169.08:22:39.16#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:22:39.16#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.169.08:22:39.16#ibcon#about to clear, iclass 3 cls_cnt 0 2006.169.08:22:39.16#ibcon#cleared, iclass 3 cls_cnt 0 2006.169.08:22:39.16$vc4f8/vblo=6,752.99 2006.169.08:22:39.16#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.169.08:22:39.16#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.169.08:22:39.16#ibcon#ireg 17 cls_cnt 0 2006.169.08:22:39.16#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:22:39.16#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:22:39.16#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:22:39.16#ibcon#enter wrdev, iclass 5, count 0 2006.169.08:22:39.16#ibcon#first serial, iclass 5, count 0 2006.169.08:22:39.16#ibcon#enter sib2, iclass 5, count 0 2006.169.08:22:39.16#ibcon#flushed, iclass 5, count 0 2006.169.08:22:39.16#ibcon#about to write, iclass 5, count 0 2006.169.08:22:39.16#ibcon#wrote, iclass 5, count 0 2006.169.08:22:39.16#ibcon#about to read 3, iclass 5, count 0 2006.169.08:22:39.18#ibcon#read 3, iclass 5, count 0 2006.169.08:22:39.18#ibcon#about to read 4, iclass 5, count 0 2006.169.08:22:39.18#ibcon#read 4, iclass 5, count 0 2006.169.08:22:39.18#ibcon#about to read 5, iclass 5, count 0 2006.169.08:22:39.18#ibcon#read 5, iclass 5, count 0 2006.169.08:22:39.18#ibcon#about to read 6, iclass 5, count 0 2006.169.08:22:39.18#ibcon#read 6, iclass 5, count 0 2006.169.08:22:39.18#ibcon#end of sib2, iclass 5, count 0 2006.169.08:22:39.18#ibcon#*mode == 0, iclass 5, count 0 2006.169.08:22:39.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.169.08:22:39.18#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.08:22:39.18#ibcon#*before write, iclass 5, count 0 2006.169.08:22:39.18#ibcon#enter sib2, iclass 5, count 0 2006.169.08:22:39.18#ibcon#flushed, iclass 5, count 0 2006.169.08:22:39.18#ibcon#about to write, iclass 5, count 0 2006.169.08:22:39.18#ibcon#wrote, iclass 5, count 0 2006.169.08:22:39.18#ibcon#about to read 3, iclass 5, count 0 2006.169.08:22:39.22#ibcon#read 3, iclass 5, count 0 2006.169.08:22:39.22#ibcon#about to read 4, iclass 5, count 0 2006.169.08:22:39.22#ibcon#read 4, iclass 5, count 0 2006.169.08:22:39.22#ibcon#about to read 5, iclass 5, count 0 2006.169.08:22:39.22#ibcon#read 5, iclass 5, count 0 2006.169.08:22:39.22#ibcon#about to read 6, iclass 5, count 0 2006.169.08:22:39.22#ibcon#read 6, iclass 5, count 0 2006.169.08:22:39.22#ibcon#end of sib2, iclass 5, count 0 2006.169.08:22:39.22#ibcon#*after write, iclass 5, count 0 2006.169.08:22:39.22#ibcon#*before return 0, iclass 5, count 0 2006.169.08:22:39.22#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:22:39.22#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.169.08:22:39.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.169.08:22:39.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.169.08:22:39.22$vc4f8/vb=6,4 2006.169.08:22:39.22#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.169.08:22:39.22#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.169.08:22:39.22#ibcon#ireg 11 cls_cnt 2 2006.169.08:22:39.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:22:39.28#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:22:39.28#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:22:39.28#ibcon#enter wrdev, iclass 7, count 2 2006.169.08:22:39.28#ibcon#first serial, iclass 7, count 2 2006.169.08:22:39.28#ibcon#enter sib2, iclass 7, count 2 2006.169.08:22:39.28#ibcon#flushed, iclass 7, count 2 2006.169.08:22:39.28#ibcon#about to write, iclass 7, count 2 2006.169.08:22:39.28#ibcon#wrote, iclass 7, count 2 2006.169.08:22:39.28#ibcon#about to read 3, iclass 7, count 2 2006.169.08:22:39.30#ibcon#read 3, iclass 7, count 2 2006.169.08:22:39.30#ibcon#about to read 4, iclass 7, count 2 2006.169.08:22:39.30#ibcon#read 4, iclass 7, count 2 2006.169.08:22:39.30#ibcon#about to read 5, iclass 7, count 2 2006.169.08:22:39.30#ibcon#read 5, iclass 7, count 2 2006.169.08:22:39.30#ibcon#about to read 6, iclass 7, count 2 2006.169.08:22:39.30#ibcon#read 6, iclass 7, count 2 2006.169.08:22:39.30#ibcon#end of sib2, iclass 7, count 2 2006.169.08:22:39.30#ibcon#*mode == 0, iclass 7, count 2 2006.169.08:22:39.30#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.169.08:22:39.30#ibcon#[27=AT06-04\r\n] 2006.169.08:22:39.30#ibcon#*before write, iclass 7, count 2 2006.169.08:22:39.30#ibcon#enter sib2, iclass 7, count 2 2006.169.08:22:39.30#ibcon#flushed, iclass 7, count 2 2006.169.08:22:39.30#ibcon#about to write, iclass 7, count 2 2006.169.08:22:39.30#ibcon#wrote, iclass 7, count 2 2006.169.08:22:39.30#ibcon#about to read 3, iclass 7, count 2 2006.169.08:22:39.33#ibcon#read 3, iclass 7, count 2 2006.169.08:22:39.33#ibcon#about to read 4, iclass 7, count 2 2006.169.08:22:39.33#ibcon#read 4, iclass 7, count 2 2006.169.08:22:39.33#ibcon#about to read 5, iclass 7, count 2 2006.169.08:22:39.33#ibcon#read 5, iclass 7, count 2 2006.169.08:22:39.33#ibcon#about to read 6, iclass 7, count 2 2006.169.08:22:39.33#ibcon#read 6, iclass 7, count 2 2006.169.08:22:39.33#ibcon#end of sib2, iclass 7, count 2 2006.169.08:22:39.33#ibcon#*after write, iclass 7, count 2 2006.169.08:22:39.33#ibcon#*before return 0, iclass 7, count 2 2006.169.08:22:39.33#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:22:39.33#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.169.08:22:39.33#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.169.08:22:39.33#ibcon#ireg 7 cls_cnt 0 2006.169.08:22:39.33#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:22:39.45#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:22:39.45#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:22:39.45#ibcon#enter wrdev, iclass 7, count 0 2006.169.08:22:39.45#ibcon#first serial, iclass 7, count 0 2006.169.08:22:39.45#ibcon#enter sib2, iclass 7, count 0 2006.169.08:22:39.45#ibcon#flushed, iclass 7, count 0 2006.169.08:22:39.45#ibcon#about to write, iclass 7, count 0 2006.169.08:22:39.45#ibcon#wrote, iclass 7, count 0 2006.169.08:22:39.45#ibcon#about to read 3, iclass 7, count 0 2006.169.08:22:39.47#ibcon#read 3, iclass 7, count 0 2006.169.08:22:39.47#ibcon#about to read 4, iclass 7, count 0 2006.169.08:22:39.47#ibcon#read 4, iclass 7, count 0 2006.169.08:22:39.47#ibcon#about to read 5, iclass 7, count 0 2006.169.08:22:39.47#ibcon#read 5, iclass 7, count 0 2006.169.08:22:39.47#ibcon#about to read 6, iclass 7, count 0 2006.169.08:22:39.47#ibcon#read 6, iclass 7, count 0 2006.169.08:22:39.47#ibcon#end of sib2, iclass 7, count 0 2006.169.08:22:39.47#ibcon#*mode == 0, iclass 7, count 0 2006.169.08:22:39.47#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.169.08:22:39.47#ibcon#[27=USB\r\n] 2006.169.08:22:39.47#ibcon#*before write, iclass 7, count 0 2006.169.08:22:39.47#ibcon#enter sib2, iclass 7, count 0 2006.169.08:22:39.47#ibcon#flushed, iclass 7, count 0 2006.169.08:22:39.47#ibcon#about to write, iclass 7, count 0 2006.169.08:22:39.47#ibcon#wrote, iclass 7, count 0 2006.169.08:22:39.47#ibcon#about to read 3, iclass 7, count 0 2006.169.08:22:39.50#ibcon#read 3, iclass 7, count 0 2006.169.08:22:39.50#ibcon#about to read 4, iclass 7, count 0 2006.169.08:22:39.50#ibcon#read 4, iclass 7, count 0 2006.169.08:22:39.50#ibcon#about to read 5, iclass 7, count 0 2006.169.08:22:39.50#ibcon#read 5, iclass 7, count 0 2006.169.08:22:39.50#ibcon#about to read 6, iclass 7, count 0 2006.169.08:22:39.50#ibcon#read 6, iclass 7, count 0 2006.169.08:22:39.50#ibcon#end of sib2, iclass 7, count 0 2006.169.08:22:39.50#ibcon#*after write, iclass 7, count 0 2006.169.08:22:39.50#ibcon#*before return 0, iclass 7, count 0 2006.169.08:22:39.50#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:22:39.50#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.169.08:22:39.50#ibcon#about to clear, iclass 7 cls_cnt 0 2006.169.08:22:39.50#ibcon#cleared, iclass 7 cls_cnt 0 2006.169.08:22:39.50$vc4f8/vabw=wide 2006.169.08:22:39.50#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.169.08:22:39.50#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.169.08:22:39.50#ibcon#ireg 8 cls_cnt 0 2006.169.08:22:39.50#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:22:39.50#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:22:39.50#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:22:39.50#ibcon#enter wrdev, iclass 11, count 0 2006.169.08:22:39.50#ibcon#first serial, iclass 11, count 0 2006.169.08:22:39.50#ibcon#enter sib2, iclass 11, count 0 2006.169.08:22:39.50#ibcon#flushed, iclass 11, count 0 2006.169.08:22:39.50#ibcon#about to write, iclass 11, count 0 2006.169.08:22:39.50#ibcon#wrote, iclass 11, count 0 2006.169.08:22:39.50#ibcon#about to read 3, iclass 11, count 0 2006.169.08:22:39.52#ibcon#read 3, iclass 11, count 0 2006.169.08:22:39.52#ibcon#about to read 4, iclass 11, count 0 2006.169.08:22:39.52#ibcon#read 4, iclass 11, count 0 2006.169.08:22:39.52#ibcon#about to read 5, iclass 11, count 0 2006.169.08:22:39.52#ibcon#read 5, iclass 11, count 0 2006.169.08:22:39.52#ibcon#about to read 6, iclass 11, count 0 2006.169.08:22:39.52#ibcon#read 6, iclass 11, count 0 2006.169.08:22:39.52#ibcon#end of sib2, iclass 11, count 0 2006.169.08:22:39.52#ibcon#*mode == 0, iclass 11, count 0 2006.169.08:22:39.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.169.08:22:39.52#ibcon#[25=BW32\r\n] 2006.169.08:22:39.52#ibcon#*before write, iclass 11, count 0 2006.169.08:22:39.52#ibcon#enter sib2, iclass 11, count 0 2006.169.08:22:39.52#ibcon#flushed, iclass 11, count 0 2006.169.08:22:39.52#ibcon#about to write, iclass 11, count 0 2006.169.08:22:39.52#ibcon#wrote, iclass 11, count 0 2006.169.08:22:39.52#ibcon#about to read 3, iclass 11, count 0 2006.169.08:22:39.55#ibcon#read 3, iclass 11, count 0 2006.169.08:22:39.55#ibcon#about to read 4, iclass 11, count 0 2006.169.08:22:39.55#ibcon#read 4, iclass 11, count 0 2006.169.08:22:39.55#ibcon#about to read 5, iclass 11, count 0 2006.169.08:22:39.55#ibcon#read 5, iclass 11, count 0 2006.169.08:22:39.55#ibcon#about to read 6, iclass 11, count 0 2006.169.08:22:39.55#ibcon#read 6, iclass 11, count 0 2006.169.08:22:39.55#ibcon#end of sib2, iclass 11, count 0 2006.169.08:22:39.55#ibcon#*after write, iclass 11, count 0 2006.169.08:22:39.55#ibcon#*before return 0, iclass 11, count 0 2006.169.08:22:39.55#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:22:39.55#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.169.08:22:39.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.169.08:22:39.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.169.08:22:39.55$vc4f8/vbbw=wide 2006.169.08:22:39.55#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.169.08:22:39.55#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.169.08:22:39.55#ibcon#ireg 8 cls_cnt 0 2006.169.08:22:39.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:22:39.62#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:22:39.62#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:22:39.62#ibcon#enter wrdev, iclass 13, count 0 2006.169.08:22:39.62#ibcon#first serial, iclass 13, count 0 2006.169.08:22:39.62#ibcon#enter sib2, iclass 13, count 0 2006.169.08:22:39.62#ibcon#flushed, iclass 13, count 0 2006.169.08:22:39.62#ibcon#about to write, iclass 13, count 0 2006.169.08:22:39.62#ibcon#wrote, iclass 13, count 0 2006.169.08:22:39.62#ibcon#about to read 3, iclass 13, count 0 2006.169.08:22:39.64#ibcon#read 3, iclass 13, count 0 2006.169.08:22:39.64#ibcon#about to read 4, iclass 13, count 0 2006.169.08:22:39.64#ibcon#read 4, iclass 13, count 0 2006.169.08:22:39.64#ibcon#about to read 5, iclass 13, count 0 2006.169.08:22:39.64#ibcon#read 5, iclass 13, count 0 2006.169.08:22:39.64#ibcon#about to read 6, iclass 13, count 0 2006.169.08:22:39.64#ibcon#read 6, iclass 13, count 0 2006.169.08:22:39.64#ibcon#end of sib2, iclass 13, count 0 2006.169.08:22:39.64#ibcon#*mode == 0, iclass 13, count 0 2006.169.08:22:39.64#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.08:22:39.64#ibcon#[27=BW32\r\n] 2006.169.08:22:39.64#ibcon#*before write, iclass 13, count 0 2006.169.08:22:39.64#ibcon#enter sib2, iclass 13, count 0 2006.169.08:22:39.64#ibcon#flushed, iclass 13, count 0 2006.169.08:22:39.64#ibcon#about to write, iclass 13, count 0 2006.169.08:22:39.64#ibcon#wrote, iclass 13, count 0 2006.169.08:22:39.64#ibcon#about to read 3, iclass 13, count 0 2006.169.08:22:39.67#ibcon#read 3, iclass 13, count 0 2006.169.08:22:39.67#ibcon#about to read 4, iclass 13, count 0 2006.169.08:22:39.67#ibcon#read 4, iclass 13, count 0 2006.169.08:22:39.67#ibcon#about to read 5, iclass 13, count 0 2006.169.08:22:39.67#ibcon#read 5, iclass 13, count 0 2006.169.08:22:39.67#ibcon#about to read 6, iclass 13, count 0 2006.169.08:22:39.67#ibcon#read 6, iclass 13, count 0 2006.169.08:22:39.67#ibcon#end of sib2, iclass 13, count 0 2006.169.08:22:39.67#ibcon#*after write, iclass 13, count 0 2006.169.08:22:39.67#ibcon#*before return 0, iclass 13, count 0 2006.169.08:22:39.67#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:22:39.67#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:22:39.67#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.08:22:39.67#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.08:22:39.67$4f8m12a/ifd4f 2006.169.08:22:39.67$ifd4f/lo= 2006.169.08:22:39.67$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.08:22:39.67$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.08:22:39.67$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.08:22:39.67$ifd4f/patch= 2006.169.08:22:39.67$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.08:22:39.67$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.08:22:39.68$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.08:22:39.68$4f8m12a/"form=m,16.000,1:2 2006.169.08:22:39.68$4f8m12a/"tpicd 2006.169.08:22:39.68$4f8m12a/echo=off 2006.169.08:22:39.68$4f8m12a/xlog=off 2006.169.08:22:39.68:!2006.169.08:24:30 2006.169.08:22:42.14#trakl#Source acquired 2006.169.08:22:44.14#flagr#flagr/antenna,acquired 2006.169.08:24:30.01:preob 2006.169.08:24:31.14/onsource/TRACKING 2006.169.08:24:31.14:!2006.169.08:24:40 2006.169.08:24:40.00:data_valid=on 2006.169.08:24:40.00:midob 2006.169.08:24:40.14/onsource/TRACKING 2006.169.08:24:40.14/wx/18.09,1003.9,100 2006.169.08:24:40.32/cable/+6.5311E-03 2006.169.08:24:41.41/va/01,08,usb,yes,41,43 2006.169.08:24:41.41/va/02,07,usb,yes,41,43 2006.169.08:24:41.41/va/03,06,usb,yes,44,44 2006.169.08:24:41.41/va/04,07,usb,yes,42,45 2006.169.08:24:41.41/va/05,07,usb,yes,46,49 2006.169.08:24:41.41/va/06,06,usb,yes,46,45 2006.169.08:24:41.41/va/07,06,usb,yes,46,46 2006.169.08:24:41.41/va/08,07,usb,yes,44,43 2006.169.08:24:41.64/valo/01,532.99,yes,locked 2006.169.08:24:41.64/valo/02,572.99,yes,locked 2006.169.08:24:41.64/valo/03,672.99,yes,locked 2006.169.08:24:41.64/valo/04,832.99,yes,locked 2006.169.08:24:41.64/valo/05,652.99,yes,locked 2006.169.08:24:41.64/valo/06,772.99,yes,locked 2006.169.08:24:41.64/valo/07,832.99,yes,locked 2006.169.08:24:41.64/valo/08,852.99,yes,locked 2006.169.08:24:42.73/vb/01,04,usb,yes,30,28 2006.169.08:24:42.73/vb/02,04,usb,yes,31,33 2006.169.08:24:42.73/vb/03,04,usb,yes,28,31 2006.169.08:24:42.73/vb/04,04,usb,yes,29,29 2006.169.08:24:42.73/vb/05,04,usb,yes,27,31 2006.169.08:24:42.73/vb/06,04,usb,yes,28,31 2006.169.08:24:42.73/vb/07,04,usb,yes,30,30 2006.169.08:24:42.73/vb/08,04,usb,yes,28,31 2006.169.08:24:42.96/vblo/01,632.99,yes,locked 2006.169.08:24:42.96/vblo/02,640.99,yes,locked 2006.169.08:24:42.96/vblo/03,656.99,yes,locked 2006.169.08:24:42.96/vblo/04,712.99,yes,locked 2006.169.08:24:42.96/vblo/05,744.99,yes,locked 2006.169.08:24:42.96/vblo/06,752.99,yes,locked 2006.169.08:24:42.96/vblo/07,734.99,yes,locked 2006.169.08:24:42.96/vblo/08,744.99,yes,locked 2006.169.08:24:43.11/vabw/8 2006.169.08:24:43.26/vbbw/8 2006.169.08:24:43.37/xfe/off,on,15.0 2006.169.08:24:43.74/ifatt/23,28,28,28 2006.169.08:24:44.07/fmout-gps/S +4.16E-07 2006.169.08:24:44.15:!2006.169.08:25:40 2006.169.08:25:40.01:data_valid=off 2006.169.08:25:40.02:postob 2006.169.08:25:40.24/cable/+6.5299E-03 2006.169.08:25:40.25/wx/18.10,1003.9,100 2006.169.08:25:41.08/fmout-gps/S +4.16E-07 2006.169.08:25:41.09:scan_name=169-0826,k06169,60 2006.169.08:25:41.09:source=1739+522,174036.98,521143.4,2000.0,cw 2006.169.08:25:42.14#flagr#flagr/antenna,new-source 2006.169.08:25:42.15:checkk5 2006.169.08:25:42.53/chk_autoobs//k5ts1/ autoobs is running! 2006.169.08:25:42.91/chk_autoobs//k5ts2/ autoobs is running! 2006.169.08:25:46.93/chk_autoobs//k5ts3?ERROR: timeout happened! 2006.169.08:25:47.31/chk_autoobs//k5ts4/ autoobs is running! 2006.169.08:25:47.68/chk_obsdata//k5ts1/T1690824??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.169.08:25:48.05/chk_obsdata//k5ts2/T1690824??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.169.08:25:55.10/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.08:25:55.47/chk_obsdata//k5ts4/T1690824??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.169.08:25:56.17/k5log//k5ts1_log_newline 2006.169.08:25:56.86/k5log//k5ts2_log_newline 2006.169.08:26:03.95/k5log//k5ts3?ERROR: timeout happened! 2006.169.08:26:04.64/k5log//k5ts4_log_newline 2006.169.08:26:04.80/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.08:26:04.80:4f8m12a=3 2006.169.08:26:04.80$4f8m12a/echo=on 2006.169.08:26:04.80$4f8m12a/pcalon 2006.169.08:26:04.80$pcalon/"no phase cal control is implemented here 2006.169.08:26:04.80$4f8m12a/"tpicd=stop 2006.169.08:26:04.80$4f8m12a/vc4f8 2006.169.08:26:04.80$vc4f8/valo=1,532.99 2006.169.08:26:04.81#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.169.08:26:04.81#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.169.08:26:04.81#ibcon#ireg 17 cls_cnt 0 2006.169.08:26:04.81#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:26:04.81#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:26:04.81#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:26:04.81#ibcon#enter wrdev, iclass 24, count 0 2006.169.08:26:04.81#ibcon#first serial, iclass 24, count 0 2006.169.08:26:04.81#ibcon#enter sib2, iclass 24, count 0 2006.169.08:26:04.81#ibcon#flushed, iclass 24, count 0 2006.169.08:26:04.81#ibcon#about to write, iclass 24, count 0 2006.169.08:26:04.81#ibcon#wrote, iclass 24, count 0 2006.169.08:26:04.81#ibcon#about to read 3, iclass 24, count 0 2006.169.08:26:04.83#ibcon#read 3, iclass 24, count 0 2006.169.08:26:04.83#ibcon#about to read 4, iclass 24, count 0 2006.169.08:26:04.83#ibcon#read 4, iclass 24, count 0 2006.169.08:26:04.83#ibcon#about to read 5, iclass 24, count 0 2006.169.08:26:04.83#ibcon#read 5, iclass 24, count 0 2006.169.08:26:04.83#ibcon#about to read 6, iclass 24, count 0 2006.169.08:26:04.83#ibcon#read 6, iclass 24, count 0 2006.169.08:26:04.83#ibcon#end of sib2, iclass 24, count 0 2006.169.08:26:04.83#ibcon#*mode == 0, iclass 24, count 0 2006.169.08:26:04.83#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.169.08:26:04.83#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.08:26:04.83#ibcon#*before write, iclass 24, count 0 2006.169.08:26:04.83#ibcon#enter sib2, iclass 24, count 0 2006.169.08:26:04.83#ibcon#flushed, iclass 24, count 0 2006.169.08:26:04.83#ibcon#about to write, iclass 24, count 0 2006.169.08:26:04.83#ibcon#wrote, iclass 24, count 0 2006.169.08:26:04.83#ibcon#about to read 3, iclass 24, count 0 2006.169.08:26:04.89#ibcon#read 3, iclass 24, count 0 2006.169.08:26:04.89#ibcon#about to read 4, iclass 24, count 0 2006.169.08:26:04.89#ibcon#read 4, iclass 24, count 0 2006.169.08:26:04.89#ibcon#about to read 5, iclass 24, count 0 2006.169.08:26:04.89#ibcon#read 5, iclass 24, count 0 2006.169.08:26:04.89#ibcon#about to read 6, iclass 24, count 0 2006.169.08:26:04.89#ibcon#read 6, iclass 24, count 0 2006.169.08:26:04.89#ibcon#end of sib2, iclass 24, count 0 2006.169.08:26:04.89#ibcon#*after write, iclass 24, count 0 2006.169.08:26:04.89#ibcon#*before return 0, iclass 24, count 0 2006.169.08:26:04.89#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:26:04.89#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:26:04.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.169.08:26:04.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.169.08:26:04.89$vc4f8/va=1,8 2006.169.08:26:04.89#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.169.08:26:04.89#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.169.08:26:04.89#ibcon#ireg 11 cls_cnt 2 2006.169.08:26:04.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.169.08:26:04.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.169.08:26:04.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.169.08:26:04.89#ibcon#enter wrdev, iclass 26, count 2 2006.169.08:26:04.89#ibcon#first serial, iclass 26, count 2 2006.169.08:26:04.89#ibcon#enter sib2, iclass 26, count 2 2006.169.08:26:04.89#ibcon#flushed, iclass 26, count 2 2006.169.08:26:04.89#ibcon#about to write, iclass 26, count 2 2006.169.08:26:04.89#ibcon#wrote, iclass 26, count 2 2006.169.08:26:04.89#ibcon#about to read 3, iclass 26, count 2 2006.169.08:26:04.90#ibcon#read 3, iclass 26, count 2 2006.169.08:26:04.90#ibcon#about to read 4, iclass 26, count 2 2006.169.08:26:04.90#ibcon#read 4, iclass 26, count 2 2006.169.08:26:04.90#ibcon#about to read 5, iclass 26, count 2 2006.169.08:26:04.90#ibcon#read 5, iclass 26, count 2 2006.169.08:26:04.90#ibcon#about to read 6, iclass 26, count 2 2006.169.08:26:04.90#ibcon#read 6, iclass 26, count 2 2006.169.08:26:04.90#ibcon#end of sib2, iclass 26, count 2 2006.169.08:26:04.90#ibcon#*mode == 0, iclass 26, count 2 2006.169.08:26:04.90#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.169.08:26:04.90#ibcon#[25=AT01-08\r\n] 2006.169.08:26:04.90#ibcon#*before write, iclass 26, count 2 2006.169.08:26:04.90#ibcon#enter sib2, iclass 26, count 2 2006.169.08:26:04.90#ibcon#flushed, iclass 26, count 2 2006.169.08:26:04.90#ibcon#about to write, iclass 26, count 2 2006.169.08:26:04.90#ibcon#wrote, iclass 26, count 2 2006.169.08:26:04.90#ibcon#about to read 3, iclass 26, count 2 2006.169.08:26:04.93#ibcon#read 3, iclass 26, count 2 2006.169.08:26:04.93#ibcon#about to read 4, iclass 26, count 2 2006.169.08:26:04.93#ibcon#read 4, iclass 26, count 2 2006.169.08:26:04.93#ibcon#about to read 5, iclass 26, count 2 2006.169.08:26:04.93#ibcon#read 5, iclass 26, count 2 2006.169.08:26:04.93#ibcon#about to read 6, iclass 26, count 2 2006.169.08:26:04.93#ibcon#read 6, iclass 26, count 2 2006.169.08:26:04.93#ibcon#end of sib2, iclass 26, count 2 2006.169.08:26:04.93#ibcon#*after write, iclass 26, count 2 2006.169.08:26:04.93#ibcon#*before return 0, iclass 26, count 2 2006.169.08:26:04.93#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.169.08:26:04.93#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.169.08:26:04.93#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.169.08:26:04.93#ibcon#ireg 7 cls_cnt 0 2006.169.08:26:04.93#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.169.08:26:05.06#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.169.08:26:05.06#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.169.08:26:05.06#ibcon#enter wrdev, iclass 26, count 0 2006.169.08:26:05.06#ibcon#first serial, iclass 26, count 0 2006.169.08:26:05.07#ibcon#enter sib2, iclass 26, count 0 2006.169.08:26:05.07#ibcon#flushed, iclass 26, count 0 2006.169.08:26:05.07#ibcon#about to write, iclass 26, count 0 2006.169.08:26:05.07#ibcon#wrote, iclass 26, count 0 2006.169.08:26:05.07#ibcon#about to read 3, iclass 26, count 0 2006.169.08:26:05.08#ibcon#read 3, iclass 26, count 0 2006.169.08:26:05.08#ibcon#about to read 4, iclass 26, count 0 2006.169.08:26:05.08#ibcon#read 4, iclass 26, count 0 2006.169.08:26:05.08#ibcon#about to read 5, iclass 26, count 0 2006.169.08:26:05.08#ibcon#read 5, iclass 26, count 0 2006.169.08:26:05.08#ibcon#about to read 6, iclass 26, count 0 2006.169.08:26:05.08#ibcon#read 6, iclass 26, count 0 2006.169.08:26:05.08#ibcon#end of sib2, iclass 26, count 0 2006.169.08:26:05.08#ibcon#*mode == 0, iclass 26, count 0 2006.169.08:26:05.08#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.169.08:26:05.08#ibcon#[25=USB\r\n] 2006.169.08:26:05.08#ibcon#*before write, iclass 26, count 0 2006.169.08:26:05.08#ibcon#enter sib2, iclass 26, count 0 2006.169.08:26:05.08#ibcon#flushed, iclass 26, count 0 2006.169.08:26:05.08#ibcon#about to write, iclass 26, count 0 2006.169.08:26:05.08#ibcon#wrote, iclass 26, count 0 2006.169.08:26:05.08#ibcon#about to read 3, iclass 26, count 0 2006.169.08:26:05.11#ibcon#read 3, iclass 26, count 0 2006.169.08:26:05.11#ibcon#about to read 4, iclass 26, count 0 2006.169.08:26:05.11#ibcon#read 4, iclass 26, count 0 2006.169.08:26:05.11#ibcon#about to read 5, iclass 26, count 0 2006.169.08:26:05.11#ibcon#read 5, iclass 26, count 0 2006.169.08:26:05.11#ibcon#about to read 6, iclass 26, count 0 2006.169.08:26:05.11#ibcon#read 6, iclass 26, count 0 2006.169.08:26:05.11#ibcon#end of sib2, iclass 26, count 0 2006.169.08:26:05.11#ibcon#*after write, iclass 26, count 0 2006.169.08:26:05.11#ibcon#*before return 0, iclass 26, count 0 2006.169.08:26:05.11#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.169.08:26:05.11#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.169.08:26:05.11#ibcon#about to clear, iclass 26 cls_cnt 0 2006.169.08:26:05.11#ibcon#cleared, iclass 26 cls_cnt 0 2006.169.08:26:05.11$vc4f8/valo=2,572.99 2006.169.08:26:05.11#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.169.08:26:05.11#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.169.08:26:05.11#ibcon#ireg 17 cls_cnt 0 2006.169.08:26:05.11#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:26:05.11#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:26:05.11#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:26:05.11#ibcon#enter wrdev, iclass 28, count 0 2006.169.08:26:05.11#ibcon#first serial, iclass 28, count 0 2006.169.08:26:05.11#ibcon#enter sib2, iclass 28, count 0 2006.169.08:26:05.11#ibcon#flushed, iclass 28, count 0 2006.169.08:26:05.11#ibcon#about to write, iclass 28, count 0 2006.169.08:26:05.11#ibcon#wrote, iclass 28, count 0 2006.169.08:26:05.11#ibcon#about to read 3, iclass 28, count 0 2006.169.08:26:05.13#ibcon#read 3, iclass 28, count 0 2006.169.08:26:05.13#ibcon#about to read 4, iclass 28, count 0 2006.169.08:26:05.13#ibcon#read 4, iclass 28, count 0 2006.169.08:26:05.13#ibcon#about to read 5, iclass 28, count 0 2006.169.08:26:05.13#ibcon#read 5, iclass 28, count 0 2006.169.08:26:05.13#ibcon#about to read 6, iclass 28, count 0 2006.169.08:26:05.13#ibcon#read 6, iclass 28, count 0 2006.169.08:26:05.13#ibcon#end of sib2, iclass 28, count 0 2006.169.08:26:05.13#ibcon#*mode == 0, iclass 28, count 0 2006.169.08:26:05.13#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.169.08:26:05.13#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.08:26:05.13#ibcon#*before write, iclass 28, count 0 2006.169.08:26:05.13#ibcon#enter sib2, iclass 28, count 0 2006.169.08:26:05.13#ibcon#flushed, iclass 28, count 0 2006.169.08:26:05.13#ibcon#about to write, iclass 28, count 0 2006.169.08:26:05.13#ibcon#wrote, iclass 28, count 0 2006.169.08:26:05.13#ibcon#about to read 3, iclass 28, count 0 2006.169.08:26:05.17#ibcon#read 3, iclass 28, count 0 2006.169.08:26:05.17#ibcon#about to read 4, iclass 28, count 0 2006.169.08:26:05.17#ibcon#read 4, iclass 28, count 0 2006.169.08:26:05.17#ibcon#about to read 5, iclass 28, count 0 2006.169.08:26:05.17#ibcon#read 5, iclass 28, count 0 2006.169.08:26:05.17#ibcon#about to read 6, iclass 28, count 0 2006.169.08:26:05.17#ibcon#read 6, iclass 28, count 0 2006.169.08:26:05.17#ibcon#end of sib2, iclass 28, count 0 2006.169.08:26:05.17#ibcon#*after write, iclass 28, count 0 2006.169.08:26:05.17#ibcon#*before return 0, iclass 28, count 0 2006.169.08:26:05.17#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:26:05.17#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:26:05.17#ibcon#about to clear, iclass 28 cls_cnt 0 2006.169.08:26:05.17#ibcon#cleared, iclass 28 cls_cnt 0 2006.169.08:26:05.17$vc4f8/va=2,7 2006.169.08:26:05.17#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.169.08:26:05.17#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.169.08:26:05.17#ibcon#ireg 11 cls_cnt 2 2006.169.08:26:05.17#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:26:05.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:26:05.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:26:05.23#ibcon#enter wrdev, iclass 30, count 2 2006.169.08:26:05.23#ibcon#first serial, iclass 30, count 2 2006.169.08:26:05.23#ibcon#enter sib2, iclass 30, count 2 2006.169.08:26:05.23#ibcon#flushed, iclass 30, count 2 2006.169.08:26:05.23#ibcon#about to write, iclass 30, count 2 2006.169.08:26:05.23#ibcon#wrote, iclass 30, count 2 2006.169.08:26:05.23#ibcon#about to read 3, iclass 30, count 2 2006.169.08:26:05.25#ibcon#read 3, iclass 30, count 2 2006.169.08:26:05.25#ibcon#about to read 4, iclass 30, count 2 2006.169.08:26:05.25#ibcon#read 4, iclass 30, count 2 2006.169.08:26:05.25#ibcon#about to read 5, iclass 30, count 2 2006.169.08:26:05.25#ibcon#read 5, iclass 30, count 2 2006.169.08:26:05.25#ibcon#about to read 6, iclass 30, count 2 2006.169.08:26:05.25#ibcon#read 6, iclass 30, count 2 2006.169.08:26:05.25#ibcon#end of sib2, iclass 30, count 2 2006.169.08:26:05.25#ibcon#*mode == 0, iclass 30, count 2 2006.169.08:26:05.25#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.169.08:26:05.25#ibcon#[25=AT02-07\r\n] 2006.169.08:26:05.25#ibcon#*before write, iclass 30, count 2 2006.169.08:26:05.25#ibcon#enter sib2, iclass 30, count 2 2006.169.08:26:05.25#ibcon#flushed, iclass 30, count 2 2006.169.08:26:05.25#ibcon#about to write, iclass 30, count 2 2006.169.08:26:05.25#ibcon#wrote, iclass 30, count 2 2006.169.08:26:05.25#ibcon#about to read 3, iclass 30, count 2 2006.169.08:26:05.28#ibcon#read 3, iclass 30, count 2 2006.169.08:26:05.28#ibcon#about to read 4, iclass 30, count 2 2006.169.08:26:05.28#ibcon#read 4, iclass 30, count 2 2006.169.08:26:05.28#ibcon#about to read 5, iclass 30, count 2 2006.169.08:26:05.28#ibcon#read 5, iclass 30, count 2 2006.169.08:26:05.28#ibcon#about to read 6, iclass 30, count 2 2006.169.08:26:05.28#ibcon#read 6, iclass 30, count 2 2006.169.08:26:05.28#ibcon#end of sib2, iclass 30, count 2 2006.169.08:26:05.28#ibcon#*after write, iclass 30, count 2 2006.169.08:26:05.28#ibcon#*before return 0, iclass 30, count 2 2006.169.08:26:05.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:26:05.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:26:05.28#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.169.08:26:05.28#ibcon#ireg 7 cls_cnt 0 2006.169.08:26:05.28#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:26:05.40#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:26:05.40#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:26:05.40#ibcon#enter wrdev, iclass 30, count 0 2006.169.08:26:05.40#ibcon#first serial, iclass 30, count 0 2006.169.08:26:05.40#ibcon#enter sib2, iclass 30, count 0 2006.169.08:26:05.40#ibcon#flushed, iclass 30, count 0 2006.169.08:26:05.40#ibcon#about to write, iclass 30, count 0 2006.169.08:26:05.40#ibcon#wrote, iclass 30, count 0 2006.169.08:26:05.40#ibcon#about to read 3, iclass 30, count 0 2006.169.08:26:05.42#ibcon#read 3, iclass 30, count 0 2006.169.08:26:05.42#ibcon#about to read 4, iclass 30, count 0 2006.169.08:26:05.42#ibcon#read 4, iclass 30, count 0 2006.169.08:26:05.42#ibcon#about to read 5, iclass 30, count 0 2006.169.08:26:05.42#ibcon#read 5, iclass 30, count 0 2006.169.08:26:05.42#ibcon#about to read 6, iclass 30, count 0 2006.169.08:26:05.42#ibcon#read 6, iclass 30, count 0 2006.169.08:26:05.42#ibcon#end of sib2, iclass 30, count 0 2006.169.08:26:05.42#ibcon#*mode == 0, iclass 30, count 0 2006.169.08:26:05.42#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.169.08:26:05.42#ibcon#[25=USB\r\n] 2006.169.08:26:05.42#ibcon#*before write, iclass 30, count 0 2006.169.08:26:05.42#ibcon#enter sib2, iclass 30, count 0 2006.169.08:26:05.42#ibcon#flushed, iclass 30, count 0 2006.169.08:26:05.42#ibcon#about to write, iclass 30, count 0 2006.169.08:26:05.42#ibcon#wrote, iclass 30, count 0 2006.169.08:26:05.42#ibcon#about to read 3, iclass 30, count 0 2006.169.08:26:05.45#ibcon#read 3, iclass 30, count 0 2006.169.08:26:05.45#ibcon#about to read 4, iclass 30, count 0 2006.169.08:26:05.45#ibcon#read 4, iclass 30, count 0 2006.169.08:26:05.45#ibcon#about to read 5, iclass 30, count 0 2006.169.08:26:05.45#ibcon#read 5, iclass 30, count 0 2006.169.08:26:05.45#ibcon#about to read 6, iclass 30, count 0 2006.169.08:26:05.45#ibcon#read 6, iclass 30, count 0 2006.169.08:26:05.45#ibcon#end of sib2, iclass 30, count 0 2006.169.08:26:05.45#ibcon#*after write, iclass 30, count 0 2006.169.08:26:05.45#ibcon#*before return 0, iclass 30, count 0 2006.169.08:26:05.45#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:26:05.45#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:26:05.45#ibcon#about to clear, iclass 30 cls_cnt 0 2006.169.08:26:05.45#ibcon#cleared, iclass 30 cls_cnt 0 2006.169.08:26:05.45$vc4f8/valo=3,672.99 2006.169.08:26:05.45#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.169.08:26:05.45#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.169.08:26:05.45#ibcon#ireg 17 cls_cnt 0 2006.169.08:26:05.45#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:26:05.45#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:26:05.45#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:26:05.45#ibcon#enter wrdev, iclass 32, count 0 2006.169.08:26:05.45#ibcon#first serial, iclass 32, count 0 2006.169.08:26:05.45#ibcon#enter sib2, iclass 32, count 0 2006.169.08:26:05.45#ibcon#flushed, iclass 32, count 0 2006.169.08:26:05.45#ibcon#about to write, iclass 32, count 0 2006.169.08:26:05.45#ibcon#wrote, iclass 32, count 0 2006.169.08:26:05.45#ibcon#about to read 3, iclass 32, count 0 2006.169.08:26:05.47#ibcon#read 3, iclass 32, count 0 2006.169.08:26:05.47#ibcon#about to read 4, iclass 32, count 0 2006.169.08:26:05.47#ibcon#read 4, iclass 32, count 0 2006.169.08:26:05.47#ibcon#about to read 5, iclass 32, count 0 2006.169.08:26:05.47#ibcon#read 5, iclass 32, count 0 2006.169.08:26:05.47#ibcon#about to read 6, iclass 32, count 0 2006.169.08:26:05.47#ibcon#read 6, iclass 32, count 0 2006.169.08:26:05.47#ibcon#end of sib2, iclass 32, count 0 2006.169.08:26:05.47#ibcon#*mode == 0, iclass 32, count 0 2006.169.08:26:05.47#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.169.08:26:05.47#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.08:26:05.47#ibcon#*before write, iclass 32, count 0 2006.169.08:26:05.47#ibcon#enter sib2, iclass 32, count 0 2006.169.08:26:05.47#ibcon#flushed, iclass 32, count 0 2006.169.08:26:05.47#ibcon#about to write, iclass 32, count 0 2006.169.08:26:05.47#ibcon#wrote, iclass 32, count 0 2006.169.08:26:05.47#ibcon#about to read 3, iclass 32, count 0 2006.169.08:26:05.51#ibcon#read 3, iclass 32, count 0 2006.169.08:26:05.51#ibcon#about to read 4, iclass 32, count 0 2006.169.08:26:05.51#ibcon#read 4, iclass 32, count 0 2006.169.08:26:05.51#ibcon#about to read 5, iclass 32, count 0 2006.169.08:26:05.51#ibcon#read 5, iclass 32, count 0 2006.169.08:26:05.51#ibcon#about to read 6, iclass 32, count 0 2006.169.08:26:05.51#ibcon#read 6, iclass 32, count 0 2006.169.08:26:05.51#ibcon#end of sib2, iclass 32, count 0 2006.169.08:26:05.51#ibcon#*after write, iclass 32, count 0 2006.169.08:26:05.51#ibcon#*before return 0, iclass 32, count 0 2006.169.08:26:05.51#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:26:05.51#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:26:05.51#ibcon#about to clear, iclass 32 cls_cnt 0 2006.169.08:26:05.51#ibcon#cleared, iclass 32 cls_cnt 0 2006.169.08:26:05.51$vc4f8/va=3,6 2006.169.08:26:05.51#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.169.08:26:05.51#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.169.08:26:05.51#ibcon#ireg 11 cls_cnt 2 2006.169.08:26:05.51#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:26:05.58#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:26:05.58#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:26:05.58#ibcon#enter wrdev, iclass 34, count 2 2006.169.08:26:05.58#ibcon#first serial, iclass 34, count 2 2006.169.08:26:05.58#ibcon#enter sib2, iclass 34, count 2 2006.169.08:26:05.58#ibcon#flushed, iclass 34, count 2 2006.169.08:26:05.58#ibcon#about to write, iclass 34, count 2 2006.169.08:26:05.58#ibcon#wrote, iclass 34, count 2 2006.169.08:26:05.58#ibcon#about to read 3, iclass 34, count 2 2006.169.08:26:05.60#ibcon#read 3, iclass 34, count 2 2006.169.08:26:05.60#ibcon#about to read 4, iclass 34, count 2 2006.169.08:26:05.60#ibcon#read 4, iclass 34, count 2 2006.169.08:26:05.60#ibcon#about to read 5, iclass 34, count 2 2006.169.08:26:05.60#ibcon#read 5, iclass 34, count 2 2006.169.08:26:05.60#ibcon#about to read 6, iclass 34, count 2 2006.169.08:26:05.60#ibcon#read 6, iclass 34, count 2 2006.169.08:26:05.60#ibcon#end of sib2, iclass 34, count 2 2006.169.08:26:05.60#ibcon#*mode == 0, iclass 34, count 2 2006.169.08:26:05.60#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.169.08:26:05.60#ibcon#[25=AT03-06\r\n] 2006.169.08:26:05.60#ibcon#*before write, iclass 34, count 2 2006.169.08:26:05.60#ibcon#enter sib2, iclass 34, count 2 2006.169.08:26:05.60#ibcon#flushed, iclass 34, count 2 2006.169.08:26:05.60#ibcon#about to write, iclass 34, count 2 2006.169.08:26:05.60#ibcon#wrote, iclass 34, count 2 2006.169.08:26:05.60#ibcon#about to read 3, iclass 34, count 2 2006.169.08:26:05.62#ibcon#read 3, iclass 34, count 2 2006.169.08:26:05.62#ibcon#about to read 4, iclass 34, count 2 2006.169.08:26:05.62#ibcon#read 4, iclass 34, count 2 2006.169.08:26:05.62#ibcon#about to read 5, iclass 34, count 2 2006.169.08:26:05.62#ibcon#read 5, iclass 34, count 2 2006.169.08:26:05.62#ibcon#about to read 6, iclass 34, count 2 2006.169.08:26:05.62#ibcon#read 6, iclass 34, count 2 2006.169.08:26:05.62#ibcon#end of sib2, iclass 34, count 2 2006.169.08:26:05.62#ibcon#*after write, iclass 34, count 2 2006.169.08:26:05.62#ibcon#*before return 0, iclass 34, count 2 2006.169.08:26:05.62#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:26:05.62#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:26:05.62#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.169.08:26:05.62#ibcon#ireg 7 cls_cnt 0 2006.169.08:26:05.62#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:26:05.74#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:26:05.74#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:26:05.74#ibcon#enter wrdev, iclass 34, count 0 2006.169.08:26:05.74#ibcon#first serial, iclass 34, count 0 2006.169.08:26:05.74#ibcon#enter sib2, iclass 34, count 0 2006.169.08:26:05.74#ibcon#flushed, iclass 34, count 0 2006.169.08:26:05.74#ibcon#about to write, iclass 34, count 0 2006.169.08:26:05.74#ibcon#wrote, iclass 34, count 0 2006.169.08:26:05.74#ibcon#about to read 3, iclass 34, count 0 2006.169.08:26:05.76#ibcon#read 3, iclass 34, count 0 2006.169.08:26:05.76#ibcon#about to read 4, iclass 34, count 0 2006.169.08:26:05.76#ibcon#read 4, iclass 34, count 0 2006.169.08:26:05.76#ibcon#about to read 5, iclass 34, count 0 2006.169.08:26:05.76#ibcon#read 5, iclass 34, count 0 2006.169.08:26:05.76#ibcon#about to read 6, iclass 34, count 0 2006.169.08:26:05.76#ibcon#read 6, iclass 34, count 0 2006.169.08:26:05.76#ibcon#end of sib2, iclass 34, count 0 2006.169.08:26:05.76#ibcon#*mode == 0, iclass 34, count 0 2006.169.08:26:05.76#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.169.08:26:05.76#ibcon#[25=USB\r\n] 2006.169.08:26:05.76#ibcon#*before write, iclass 34, count 0 2006.169.08:26:05.76#ibcon#enter sib2, iclass 34, count 0 2006.169.08:26:05.76#ibcon#flushed, iclass 34, count 0 2006.169.08:26:05.76#ibcon#about to write, iclass 34, count 0 2006.169.08:26:05.76#ibcon#wrote, iclass 34, count 0 2006.169.08:26:05.76#ibcon#about to read 3, iclass 34, count 0 2006.169.08:26:05.79#ibcon#read 3, iclass 34, count 0 2006.169.08:26:05.79#ibcon#about to read 4, iclass 34, count 0 2006.169.08:26:05.79#ibcon#read 4, iclass 34, count 0 2006.169.08:26:05.79#ibcon#about to read 5, iclass 34, count 0 2006.169.08:26:05.79#ibcon#read 5, iclass 34, count 0 2006.169.08:26:05.79#ibcon#about to read 6, iclass 34, count 0 2006.169.08:26:05.79#ibcon#read 6, iclass 34, count 0 2006.169.08:26:05.79#ibcon#end of sib2, iclass 34, count 0 2006.169.08:26:05.79#ibcon#*after write, iclass 34, count 0 2006.169.08:26:05.79#ibcon#*before return 0, iclass 34, count 0 2006.169.08:26:05.79#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:26:05.79#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:26:05.79#ibcon#about to clear, iclass 34 cls_cnt 0 2006.169.08:26:05.79#ibcon#cleared, iclass 34 cls_cnt 0 2006.169.08:26:05.79$vc4f8/valo=4,832.99 2006.169.08:26:05.79#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.169.08:26:05.79#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.169.08:26:05.79#ibcon#ireg 17 cls_cnt 0 2006.169.08:26:05.79#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:26:05.79#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:26:05.79#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:26:05.79#ibcon#enter wrdev, iclass 36, count 0 2006.169.08:26:05.79#ibcon#first serial, iclass 36, count 0 2006.169.08:26:05.79#ibcon#enter sib2, iclass 36, count 0 2006.169.08:26:05.79#ibcon#flushed, iclass 36, count 0 2006.169.08:26:05.79#ibcon#about to write, iclass 36, count 0 2006.169.08:26:05.79#ibcon#wrote, iclass 36, count 0 2006.169.08:26:05.79#ibcon#about to read 3, iclass 36, count 0 2006.169.08:26:05.81#ibcon#read 3, iclass 36, count 0 2006.169.08:26:05.81#ibcon#about to read 4, iclass 36, count 0 2006.169.08:26:05.81#ibcon#read 4, iclass 36, count 0 2006.169.08:26:05.81#ibcon#about to read 5, iclass 36, count 0 2006.169.08:26:05.81#ibcon#read 5, iclass 36, count 0 2006.169.08:26:05.81#ibcon#about to read 6, iclass 36, count 0 2006.169.08:26:05.81#ibcon#read 6, iclass 36, count 0 2006.169.08:26:05.81#ibcon#end of sib2, iclass 36, count 0 2006.169.08:26:05.81#ibcon#*mode == 0, iclass 36, count 0 2006.169.08:26:05.81#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.169.08:26:05.81#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.08:26:05.81#ibcon#*before write, iclass 36, count 0 2006.169.08:26:05.81#ibcon#enter sib2, iclass 36, count 0 2006.169.08:26:05.81#ibcon#flushed, iclass 36, count 0 2006.169.08:26:05.81#ibcon#about to write, iclass 36, count 0 2006.169.08:26:05.81#ibcon#wrote, iclass 36, count 0 2006.169.08:26:05.81#ibcon#about to read 3, iclass 36, count 0 2006.169.08:26:05.85#ibcon#read 3, iclass 36, count 0 2006.169.08:26:05.85#ibcon#about to read 4, iclass 36, count 0 2006.169.08:26:05.85#ibcon#read 4, iclass 36, count 0 2006.169.08:26:05.85#ibcon#about to read 5, iclass 36, count 0 2006.169.08:26:05.85#ibcon#read 5, iclass 36, count 0 2006.169.08:26:05.85#ibcon#about to read 6, iclass 36, count 0 2006.169.08:26:05.85#ibcon#read 6, iclass 36, count 0 2006.169.08:26:05.85#ibcon#end of sib2, iclass 36, count 0 2006.169.08:26:05.85#ibcon#*after write, iclass 36, count 0 2006.169.08:26:05.85#ibcon#*before return 0, iclass 36, count 0 2006.169.08:26:05.85#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:26:05.85#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:26:05.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.169.08:26:05.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.169.08:26:05.85$vc4f8/va=4,7 2006.169.08:26:05.85#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.169.08:26:05.85#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.169.08:26:05.85#ibcon#ireg 11 cls_cnt 2 2006.169.08:26:05.85#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:26:05.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:26:05.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:26:05.91#ibcon#enter wrdev, iclass 38, count 2 2006.169.08:26:05.91#ibcon#first serial, iclass 38, count 2 2006.169.08:26:05.91#ibcon#enter sib2, iclass 38, count 2 2006.169.08:26:05.91#ibcon#flushed, iclass 38, count 2 2006.169.08:26:05.91#ibcon#about to write, iclass 38, count 2 2006.169.08:26:05.91#ibcon#wrote, iclass 38, count 2 2006.169.08:26:05.91#ibcon#about to read 3, iclass 38, count 2 2006.169.08:26:05.93#ibcon#read 3, iclass 38, count 2 2006.169.08:26:05.93#ibcon#about to read 4, iclass 38, count 2 2006.169.08:26:05.93#ibcon#read 4, iclass 38, count 2 2006.169.08:26:05.93#ibcon#about to read 5, iclass 38, count 2 2006.169.08:26:05.93#ibcon#read 5, iclass 38, count 2 2006.169.08:26:05.93#ibcon#about to read 6, iclass 38, count 2 2006.169.08:26:05.93#ibcon#read 6, iclass 38, count 2 2006.169.08:26:05.93#ibcon#end of sib2, iclass 38, count 2 2006.169.08:26:05.93#ibcon#*mode == 0, iclass 38, count 2 2006.169.08:26:05.93#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.169.08:26:05.93#ibcon#[25=AT04-07\r\n] 2006.169.08:26:05.93#ibcon#*before write, iclass 38, count 2 2006.169.08:26:05.93#ibcon#enter sib2, iclass 38, count 2 2006.169.08:26:05.93#ibcon#flushed, iclass 38, count 2 2006.169.08:26:05.93#ibcon#about to write, iclass 38, count 2 2006.169.08:26:05.93#ibcon#wrote, iclass 38, count 2 2006.169.08:26:05.93#ibcon#about to read 3, iclass 38, count 2 2006.169.08:26:05.96#ibcon#read 3, iclass 38, count 2 2006.169.08:26:05.96#ibcon#about to read 4, iclass 38, count 2 2006.169.08:26:05.96#ibcon#read 4, iclass 38, count 2 2006.169.08:26:05.96#ibcon#about to read 5, iclass 38, count 2 2006.169.08:26:05.96#ibcon#read 5, iclass 38, count 2 2006.169.08:26:05.96#ibcon#about to read 6, iclass 38, count 2 2006.169.08:26:05.96#ibcon#read 6, iclass 38, count 2 2006.169.08:26:05.96#ibcon#end of sib2, iclass 38, count 2 2006.169.08:26:05.96#ibcon#*after write, iclass 38, count 2 2006.169.08:26:05.96#ibcon#*before return 0, iclass 38, count 2 2006.169.08:26:05.96#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:26:05.96#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:26:05.96#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.169.08:26:05.96#ibcon#ireg 7 cls_cnt 0 2006.169.08:26:05.96#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:26:06.08#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:26:06.08#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:26:06.08#ibcon#enter wrdev, iclass 38, count 0 2006.169.08:26:06.08#ibcon#first serial, iclass 38, count 0 2006.169.08:26:06.08#ibcon#enter sib2, iclass 38, count 0 2006.169.08:26:06.08#ibcon#flushed, iclass 38, count 0 2006.169.08:26:06.08#ibcon#about to write, iclass 38, count 0 2006.169.08:26:06.08#ibcon#wrote, iclass 38, count 0 2006.169.08:26:06.08#ibcon#about to read 3, iclass 38, count 0 2006.169.08:26:06.10#ibcon#read 3, iclass 38, count 0 2006.169.08:26:06.10#ibcon#about to read 4, iclass 38, count 0 2006.169.08:26:06.10#ibcon#read 4, iclass 38, count 0 2006.169.08:26:06.10#ibcon#about to read 5, iclass 38, count 0 2006.169.08:26:06.10#ibcon#read 5, iclass 38, count 0 2006.169.08:26:06.10#ibcon#about to read 6, iclass 38, count 0 2006.169.08:26:06.10#ibcon#read 6, iclass 38, count 0 2006.169.08:26:06.10#ibcon#end of sib2, iclass 38, count 0 2006.169.08:26:06.10#ibcon#*mode == 0, iclass 38, count 0 2006.169.08:26:06.10#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.169.08:26:06.10#ibcon#[25=USB\r\n] 2006.169.08:26:06.10#ibcon#*before write, iclass 38, count 0 2006.169.08:26:06.10#ibcon#enter sib2, iclass 38, count 0 2006.169.08:26:06.10#ibcon#flushed, iclass 38, count 0 2006.169.08:26:06.10#ibcon#about to write, iclass 38, count 0 2006.169.08:26:06.10#ibcon#wrote, iclass 38, count 0 2006.169.08:26:06.10#ibcon#about to read 3, iclass 38, count 0 2006.169.08:26:06.13#ibcon#read 3, iclass 38, count 0 2006.169.08:26:06.13#ibcon#about to read 4, iclass 38, count 0 2006.169.08:26:06.13#ibcon#read 4, iclass 38, count 0 2006.169.08:26:06.13#ibcon#about to read 5, iclass 38, count 0 2006.169.08:26:06.13#ibcon#read 5, iclass 38, count 0 2006.169.08:26:06.13#ibcon#about to read 6, iclass 38, count 0 2006.169.08:26:06.13#ibcon#read 6, iclass 38, count 0 2006.169.08:26:06.13#ibcon#end of sib2, iclass 38, count 0 2006.169.08:26:06.13#ibcon#*after write, iclass 38, count 0 2006.169.08:26:06.13#ibcon#*before return 0, iclass 38, count 0 2006.169.08:26:06.13#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:26:06.13#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:26:06.13#ibcon#about to clear, iclass 38 cls_cnt 0 2006.169.08:26:06.13#ibcon#cleared, iclass 38 cls_cnt 0 2006.169.08:26:06.13$vc4f8/valo=5,652.99 2006.169.08:26:06.13#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.169.08:26:06.13#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.169.08:26:06.13#ibcon#ireg 17 cls_cnt 0 2006.169.08:26:06.13#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:26:06.13#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:26:06.13#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:26:06.13#ibcon#enter wrdev, iclass 40, count 0 2006.169.08:26:06.13#ibcon#first serial, iclass 40, count 0 2006.169.08:26:06.13#ibcon#enter sib2, iclass 40, count 0 2006.169.08:26:06.13#ibcon#flushed, iclass 40, count 0 2006.169.08:26:06.13#ibcon#about to write, iclass 40, count 0 2006.169.08:26:06.13#ibcon#wrote, iclass 40, count 0 2006.169.08:26:06.13#ibcon#about to read 3, iclass 40, count 0 2006.169.08:26:06.15#ibcon#read 3, iclass 40, count 0 2006.169.08:26:06.15#ibcon#about to read 4, iclass 40, count 0 2006.169.08:26:06.15#ibcon#read 4, iclass 40, count 0 2006.169.08:26:06.15#ibcon#about to read 5, iclass 40, count 0 2006.169.08:26:06.15#ibcon#read 5, iclass 40, count 0 2006.169.08:26:06.15#ibcon#about to read 6, iclass 40, count 0 2006.169.08:26:06.15#ibcon#read 6, iclass 40, count 0 2006.169.08:26:06.15#ibcon#end of sib2, iclass 40, count 0 2006.169.08:26:06.15#ibcon#*mode == 0, iclass 40, count 0 2006.169.08:26:06.15#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.169.08:26:06.15#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.08:26:06.15#ibcon#*before write, iclass 40, count 0 2006.169.08:26:06.15#ibcon#enter sib2, iclass 40, count 0 2006.169.08:26:06.15#ibcon#flushed, iclass 40, count 0 2006.169.08:26:06.15#ibcon#about to write, iclass 40, count 0 2006.169.08:26:06.15#ibcon#wrote, iclass 40, count 0 2006.169.08:26:06.15#ibcon#about to read 3, iclass 40, count 0 2006.169.08:26:06.19#ibcon#read 3, iclass 40, count 0 2006.169.08:26:06.19#ibcon#about to read 4, iclass 40, count 0 2006.169.08:26:06.19#ibcon#read 4, iclass 40, count 0 2006.169.08:26:06.19#ibcon#about to read 5, iclass 40, count 0 2006.169.08:26:06.19#ibcon#read 5, iclass 40, count 0 2006.169.08:26:06.19#ibcon#about to read 6, iclass 40, count 0 2006.169.08:26:06.19#ibcon#read 6, iclass 40, count 0 2006.169.08:26:06.19#ibcon#end of sib2, iclass 40, count 0 2006.169.08:26:06.19#ibcon#*after write, iclass 40, count 0 2006.169.08:26:06.19#ibcon#*before return 0, iclass 40, count 0 2006.169.08:26:06.19#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:26:06.19#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:26:06.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.169.08:26:06.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.169.08:26:06.19$vc4f8/va=5,7 2006.169.08:26:06.19#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.169.08:26:06.19#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.169.08:26:06.19#ibcon#ireg 11 cls_cnt 2 2006.169.08:26:06.19#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:26:06.25#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:26:06.25#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:26:06.25#ibcon#enter wrdev, iclass 4, count 2 2006.169.08:26:06.25#ibcon#first serial, iclass 4, count 2 2006.169.08:26:06.25#ibcon#enter sib2, iclass 4, count 2 2006.169.08:26:06.25#ibcon#flushed, iclass 4, count 2 2006.169.08:26:06.25#ibcon#about to write, iclass 4, count 2 2006.169.08:26:06.25#ibcon#wrote, iclass 4, count 2 2006.169.08:26:06.25#ibcon#about to read 3, iclass 4, count 2 2006.169.08:26:06.27#ibcon#read 3, iclass 4, count 2 2006.169.08:26:06.27#ibcon#about to read 4, iclass 4, count 2 2006.169.08:26:06.27#ibcon#read 4, iclass 4, count 2 2006.169.08:26:06.27#ibcon#about to read 5, iclass 4, count 2 2006.169.08:26:06.27#ibcon#read 5, iclass 4, count 2 2006.169.08:26:06.27#ibcon#about to read 6, iclass 4, count 2 2006.169.08:26:06.27#ibcon#read 6, iclass 4, count 2 2006.169.08:26:06.27#ibcon#end of sib2, iclass 4, count 2 2006.169.08:26:06.27#ibcon#*mode == 0, iclass 4, count 2 2006.169.08:26:06.27#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.169.08:26:06.27#ibcon#[25=AT05-07\r\n] 2006.169.08:26:06.27#ibcon#*before write, iclass 4, count 2 2006.169.08:26:06.27#ibcon#enter sib2, iclass 4, count 2 2006.169.08:26:06.27#ibcon#flushed, iclass 4, count 2 2006.169.08:26:06.27#ibcon#about to write, iclass 4, count 2 2006.169.08:26:06.27#ibcon#wrote, iclass 4, count 2 2006.169.08:26:06.27#ibcon#about to read 3, iclass 4, count 2 2006.169.08:26:06.30#ibcon#read 3, iclass 4, count 2 2006.169.08:26:06.30#ibcon#about to read 4, iclass 4, count 2 2006.169.08:26:06.30#ibcon#read 4, iclass 4, count 2 2006.169.08:26:06.30#ibcon#about to read 5, iclass 4, count 2 2006.169.08:26:06.30#ibcon#read 5, iclass 4, count 2 2006.169.08:26:06.30#ibcon#about to read 6, iclass 4, count 2 2006.169.08:26:06.30#ibcon#read 6, iclass 4, count 2 2006.169.08:26:06.30#ibcon#end of sib2, iclass 4, count 2 2006.169.08:26:06.30#ibcon#*after write, iclass 4, count 2 2006.169.08:26:06.30#ibcon#*before return 0, iclass 4, count 2 2006.169.08:26:06.30#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:26:06.30#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:26:06.30#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.169.08:26:06.30#ibcon#ireg 7 cls_cnt 0 2006.169.08:26:06.30#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:26:06.42#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:26:06.42#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:26:06.42#ibcon#enter wrdev, iclass 4, count 0 2006.169.08:26:06.42#ibcon#first serial, iclass 4, count 0 2006.169.08:26:06.42#ibcon#enter sib2, iclass 4, count 0 2006.169.08:26:06.42#ibcon#flushed, iclass 4, count 0 2006.169.08:26:06.42#ibcon#about to write, iclass 4, count 0 2006.169.08:26:06.42#ibcon#wrote, iclass 4, count 0 2006.169.08:26:06.42#ibcon#about to read 3, iclass 4, count 0 2006.169.08:26:06.44#ibcon#read 3, iclass 4, count 0 2006.169.08:26:06.44#ibcon#about to read 4, iclass 4, count 0 2006.169.08:26:06.44#ibcon#read 4, iclass 4, count 0 2006.169.08:26:06.44#ibcon#about to read 5, iclass 4, count 0 2006.169.08:26:06.44#ibcon#read 5, iclass 4, count 0 2006.169.08:26:06.44#ibcon#about to read 6, iclass 4, count 0 2006.169.08:26:06.44#ibcon#read 6, iclass 4, count 0 2006.169.08:26:06.44#ibcon#end of sib2, iclass 4, count 0 2006.169.08:26:06.44#ibcon#*mode == 0, iclass 4, count 0 2006.169.08:26:06.44#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.169.08:26:06.44#ibcon#[25=USB\r\n] 2006.169.08:26:06.44#ibcon#*before write, iclass 4, count 0 2006.169.08:26:06.44#ibcon#enter sib2, iclass 4, count 0 2006.169.08:26:06.44#ibcon#flushed, iclass 4, count 0 2006.169.08:26:06.44#ibcon#about to write, iclass 4, count 0 2006.169.08:26:06.44#ibcon#wrote, iclass 4, count 0 2006.169.08:26:06.44#ibcon#about to read 3, iclass 4, count 0 2006.169.08:26:06.47#ibcon#read 3, iclass 4, count 0 2006.169.08:26:06.47#ibcon#about to read 4, iclass 4, count 0 2006.169.08:26:06.47#ibcon#read 4, iclass 4, count 0 2006.169.08:26:06.47#ibcon#about to read 5, iclass 4, count 0 2006.169.08:26:06.47#ibcon#read 5, iclass 4, count 0 2006.169.08:26:06.47#ibcon#about to read 6, iclass 4, count 0 2006.169.08:26:06.47#ibcon#read 6, iclass 4, count 0 2006.169.08:26:06.47#ibcon#end of sib2, iclass 4, count 0 2006.169.08:26:06.47#ibcon#*after write, iclass 4, count 0 2006.169.08:26:06.47#ibcon#*before return 0, iclass 4, count 0 2006.169.08:26:06.47#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:26:06.47#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:26:06.47#ibcon#about to clear, iclass 4 cls_cnt 0 2006.169.08:26:06.47#ibcon#cleared, iclass 4 cls_cnt 0 2006.169.08:26:06.47$vc4f8/valo=6,772.99 2006.169.08:26:06.47#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.169.08:26:06.47#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.169.08:26:06.47#ibcon#ireg 17 cls_cnt 0 2006.169.08:26:06.47#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:26:06.47#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:26:06.47#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:26:06.47#ibcon#enter wrdev, iclass 6, count 0 2006.169.08:26:06.47#ibcon#first serial, iclass 6, count 0 2006.169.08:26:06.47#ibcon#enter sib2, iclass 6, count 0 2006.169.08:26:06.47#ibcon#flushed, iclass 6, count 0 2006.169.08:26:06.47#ibcon#about to write, iclass 6, count 0 2006.169.08:26:06.47#ibcon#wrote, iclass 6, count 0 2006.169.08:26:06.47#ibcon#about to read 3, iclass 6, count 0 2006.169.08:26:06.49#ibcon#read 3, iclass 6, count 0 2006.169.08:26:06.49#ibcon#about to read 4, iclass 6, count 0 2006.169.08:26:06.49#ibcon#read 4, iclass 6, count 0 2006.169.08:26:06.49#ibcon#about to read 5, iclass 6, count 0 2006.169.08:26:06.49#ibcon#read 5, iclass 6, count 0 2006.169.08:26:06.49#ibcon#about to read 6, iclass 6, count 0 2006.169.08:26:06.49#ibcon#read 6, iclass 6, count 0 2006.169.08:26:06.49#ibcon#end of sib2, iclass 6, count 0 2006.169.08:26:06.49#ibcon#*mode == 0, iclass 6, count 0 2006.169.08:26:06.49#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.169.08:26:06.49#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.08:26:06.49#ibcon#*before write, iclass 6, count 0 2006.169.08:26:06.49#ibcon#enter sib2, iclass 6, count 0 2006.169.08:26:06.49#ibcon#flushed, iclass 6, count 0 2006.169.08:26:06.49#ibcon#about to write, iclass 6, count 0 2006.169.08:26:06.49#ibcon#wrote, iclass 6, count 0 2006.169.08:26:06.49#ibcon#about to read 3, iclass 6, count 0 2006.169.08:26:06.53#ibcon#read 3, iclass 6, count 0 2006.169.08:26:06.53#ibcon#about to read 4, iclass 6, count 0 2006.169.08:26:06.53#ibcon#read 4, iclass 6, count 0 2006.169.08:26:06.53#ibcon#about to read 5, iclass 6, count 0 2006.169.08:26:06.53#ibcon#read 5, iclass 6, count 0 2006.169.08:26:06.53#ibcon#about to read 6, iclass 6, count 0 2006.169.08:26:06.53#ibcon#read 6, iclass 6, count 0 2006.169.08:26:06.53#ibcon#end of sib2, iclass 6, count 0 2006.169.08:26:06.53#ibcon#*after write, iclass 6, count 0 2006.169.08:26:06.53#ibcon#*before return 0, iclass 6, count 0 2006.169.08:26:06.53#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:26:06.53#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:26:06.53#ibcon#about to clear, iclass 6 cls_cnt 0 2006.169.08:26:06.53#ibcon#cleared, iclass 6 cls_cnt 0 2006.169.08:26:06.53$vc4f8/va=6,6 2006.169.08:26:06.53#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.169.08:26:06.53#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.169.08:26:06.53#ibcon#ireg 11 cls_cnt 2 2006.169.08:26:06.53#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:26:06.59#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:26:06.59#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:26:06.59#ibcon#enter wrdev, iclass 10, count 2 2006.169.08:26:06.59#ibcon#first serial, iclass 10, count 2 2006.169.08:26:06.59#ibcon#enter sib2, iclass 10, count 2 2006.169.08:26:06.59#ibcon#flushed, iclass 10, count 2 2006.169.08:26:06.59#ibcon#about to write, iclass 10, count 2 2006.169.08:26:06.59#ibcon#wrote, iclass 10, count 2 2006.169.08:26:06.59#ibcon#about to read 3, iclass 10, count 2 2006.169.08:26:06.61#ibcon#read 3, iclass 10, count 2 2006.169.08:26:06.61#ibcon#about to read 4, iclass 10, count 2 2006.169.08:26:06.61#ibcon#read 4, iclass 10, count 2 2006.169.08:26:06.61#ibcon#about to read 5, iclass 10, count 2 2006.169.08:26:06.61#ibcon#read 5, iclass 10, count 2 2006.169.08:26:06.61#ibcon#about to read 6, iclass 10, count 2 2006.169.08:26:06.61#ibcon#read 6, iclass 10, count 2 2006.169.08:26:06.61#ibcon#end of sib2, iclass 10, count 2 2006.169.08:26:06.61#ibcon#*mode == 0, iclass 10, count 2 2006.169.08:26:06.61#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.169.08:26:06.61#ibcon#[25=AT06-06\r\n] 2006.169.08:26:06.61#ibcon#*before write, iclass 10, count 2 2006.169.08:26:06.61#ibcon#enter sib2, iclass 10, count 2 2006.169.08:26:06.61#ibcon#flushed, iclass 10, count 2 2006.169.08:26:06.61#ibcon#about to write, iclass 10, count 2 2006.169.08:26:06.61#ibcon#wrote, iclass 10, count 2 2006.169.08:26:06.61#ibcon#about to read 3, iclass 10, count 2 2006.169.08:26:06.64#ibcon#read 3, iclass 10, count 2 2006.169.08:26:06.64#ibcon#about to read 4, iclass 10, count 2 2006.169.08:26:06.64#ibcon#read 4, iclass 10, count 2 2006.169.08:26:06.64#ibcon#about to read 5, iclass 10, count 2 2006.169.08:26:06.64#ibcon#read 5, iclass 10, count 2 2006.169.08:26:06.64#ibcon#about to read 6, iclass 10, count 2 2006.169.08:26:06.64#ibcon#read 6, iclass 10, count 2 2006.169.08:26:06.64#ibcon#end of sib2, iclass 10, count 2 2006.169.08:26:06.64#ibcon#*after write, iclass 10, count 2 2006.169.08:26:06.64#ibcon#*before return 0, iclass 10, count 2 2006.169.08:26:06.64#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:26:06.64#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:26:06.64#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.169.08:26:06.64#ibcon#ireg 7 cls_cnt 0 2006.169.08:26:06.64#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:26:06.76#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:26:06.76#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:26:06.76#ibcon#enter wrdev, iclass 10, count 0 2006.169.08:26:06.76#ibcon#first serial, iclass 10, count 0 2006.169.08:26:06.76#ibcon#enter sib2, iclass 10, count 0 2006.169.08:26:06.76#ibcon#flushed, iclass 10, count 0 2006.169.08:26:06.76#ibcon#about to write, iclass 10, count 0 2006.169.08:26:06.76#ibcon#wrote, iclass 10, count 0 2006.169.08:26:06.76#ibcon#about to read 3, iclass 10, count 0 2006.169.08:26:06.78#ibcon#read 3, iclass 10, count 0 2006.169.08:26:06.78#ibcon#about to read 4, iclass 10, count 0 2006.169.08:26:06.78#ibcon#read 4, iclass 10, count 0 2006.169.08:26:06.78#ibcon#about to read 5, iclass 10, count 0 2006.169.08:26:06.78#ibcon#read 5, iclass 10, count 0 2006.169.08:26:06.78#ibcon#about to read 6, iclass 10, count 0 2006.169.08:26:06.78#ibcon#read 6, iclass 10, count 0 2006.169.08:26:06.78#ibcon#end of sib2, iclass 10, count 0 2006.169.08:26:06.78#ibcon#*mode == 0, iclass 10, count 0 2006.169.08:26:06.78#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.169.08:26:06.78#ibcon#[25=USB\r\n] 2006.169.08:26:06.78#ibcon#*before write, iclass 10, count 0 2006.169.08:26:06.78#ibcon#enter sib2, iclass 10, count 0 2006.169.08:26:06.78#ibcon#flushed, iclass 10, count 0 2006.169.08:26:06.78#ibcon#about to write, iclass 10, count 0 2006.169.08:26:06.78#ibcon#wrote, iclass 10, count 0 2006.169.08:26:06.78#ibcon#about to read 3, iclass 10, count 0 2006.169.08:26:06.81#ibcon#read 3, iclass 10, count 0 2006.169.08:26:06.81#ibcon#about to read 4, iclass 10, count 0 2006.169.08:26:06.81#ibcon#read 4, iclass 10, count 0 2006.169.08:26:06.81#ibcon#about to read 5, iclass 10, count 0 2006.169.08:26:06.81#ibcon#read 5, iclass 10, count 0 2006.169.08:26:06.81#ibcon#about to read 6, iclass 10, count 0 2006.169.08:26:06.81#ibcon#read 6, iclass 10, count 0 2006.169.08:26:06.81#ibcon#end of sib2, iclass 10, count 0 2006.169.08:26:06.81#ibcon#*after write, iclass 10, count 0 2006.169.08:26:06.81#ibcon#*before return 0, iclass 10, count 0 2006.169.08:26:06.81#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:26:06.81#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:26:06.81#ibcon#about to clear, iclass 10 cls_cnt 0 2006.169.08:26:06.81#ibcon#cleared, iclass 10 cls_cnt 0 2006.169.08:26:06.81$vc4f8/valo=7,832.99 2006.169.08:26:06.81#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.169.08:26:06.81#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.169.08:26:06.81#ibcon#ireg 17 cls_cnt 0 2006.169.08:26:06.81#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:26:06.81#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:26:06.81#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:26:06.81#ibcon#enter wrdev, iclass 13, count 0 2006.169.08:26:06.81#ibcon#first serial, iclass 13, count 0 2006.169.08:26:06.81#ibcon#enter sib2, iclass 13, count 0 2006.169.08:26:06.81#ibcon#flushed, iclass 13, count 0 2006.169.08:26:06.81#ibcon#about to write, iclass 13, count 0 2006.169.08:26:06.81#ibcon#wrote, iclass 13, count 0 2006.169.08:26:06.81#ibcon#about to read 3, iclass 13, count 0 2006.169.08:26:06.83#ibcon#read 3, iclass 13, count 0 2006.169.08:26:06.83#ibcon#about to read 4, iclass 13, count 0 2006.169.08:26:06.83#ibcon#read 4, iclass 13, count 0 2006.169.08:26:06.83#ibcon#about to read 5, iclass 13, count 0 2006.169.08:26:06.83#ibcon#read 5, iclass 13, count 0 2006.169.08:26:06.83#ibcon#about to read 6, iclass 13, count 0 2006.169.08:26:06.83#ibcon#read 6, iclass 13, count 0 2006.169.08:26:06.83#ibcon#end of sib2, iclass 13, count 0 2006.169.08:26:06.83#ibcon#*mode == 0, iclass 13, count 0 2006.169.08:26:06.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.08:26:06.83#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.08:26:06.83#ibcon#*before write, iclass 13, count 0 2006.169.08:26:06.83#ibcon#enter sib2, iclass 13, count 0 2006.169.08:26:06.83#ibcon#flushed, iclass 13, count 0 2006.169.08:26:06.83#ibcon#about to write, iclass 13, count 0 2006.169.08:26:06.83#ibcon#wrote, iclass 13, count 0 2006.169.08:26:06.83#ibcon#about to read 3, iclass 13, count 0 2006.169.08:26:06.83#abcon#<5=/05 4.0 6.2 18.091001003.9\r\n> 2006.169.08:26:06.85#abcon#{5=INTERFACE CLEAR} 2006.169.08:26:06.87#ibcon#read 3, iclass 13, count 0 2006.169.08:26:06.87#ibcon#about to read 4, iclass 13, count 0 2006.169.08:26:06.87#ibcon#read 4, iclass 13, count 0 2006.169.08:26:06.87#ibcon#about to read 5, iclass 13, count 0 2006.169.08:26:06.87#ibcon#read 5, iclass 13, count 0 2006.169.08:26:06.87#ibcon#about to read 6, iclass 13, count 0 2006.169.08:26:06.87#ibcon#read 6, iclass 13, count 0 2006.169.08:26:06.87#ibcon#end of sib2, iclass 13, count 0 2006.169.08:26:06.87#ibcon#*after write, iclass 13, count 0 2006.169.08:26:06.87#ibcon#*before return 0, iclass 13, count 0 2006.169.08:26:06.87#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:26:06.87#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:26:06.87#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.08:26:06.87#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.08:26:06.87$vc4f8/va=7,6 2006.169.08:26:06.87#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.169.08:26:06.87#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.169.08:26:06.87#ibcon#ireg 11 cls_cnt 2 2006.169.08:26:06.87#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:26:06.91#abcon#[5=S1D000X0/0*\r\n] 2006.169.08:26:06.93#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:26:06.93#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:26:06.93#ibcon#enter wrdev, iclass 17, count 2 2006.169.08:26:06.93#ibcon#first serial, iclass 17, count 2 2006.169.08:26:06.93#ibcon#enter sib2, iclass 17, count 2 2006.169.08:26:06.93#ibcon#flushed, iclass 17, count 2 2006.169.08:26:06.93#ibcon#about to write, iclass 17, count 2 2006.169.08:26:06.93#ibcon#wrote, iclass 17, count 2 2006.169.08:26:06.93#ibcon#about to read 3, iclass 17, count 2 2006.169.08:26:06.95#ibcon#read 3, iclass 17, count 2 2006.169.08:26:06.95#ibcon#about to read 4, iclass 17, count 2 2006.169.08:26:06.95#ibcon#read 4, iclass 17, count 2 2006.169.08:26:06.95#ibcon#about to read 5, iclass 17, count 2 2006.169.08:26:06.95#ibcon#read 5, iclass 17, count 2 2006.169.08:26:06.95#ibcon#about to read 6, iclass 17, count 2 2006.169.08:26:06.95#ibcon#read 6, iclass 17, count 2 2006.169.08:26:06.95#ibcon#end of sib2, iclass 17, count 2 2006.169.08:26:06.95#ibcon#*mode == 0, iclass 17, count 2 2006.169.08:26:06.95#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.169.08:26:06.95#ibcon#[25=AT07-06\r\n] 2006.169.08:26:06.95#ibcon#*before write, iclass 17, count 2 2006.169.08:26:06.95#ibcon#enter sib2, iclass 17, count 2 2006.169.08:26:06.95#ibcon#flushed, iclass 17, count 2 2006.169.08:26:06.95#ibcon#about to write, iclass 17, count 2 2006.169.08:26:06.95#ibcon#wrote, iclass 17, count 2 2006.169.08:26:06.95#ibcon#about to read 3, iclass 17, count 2 2006.169.08:26:06.98#ibcon#read 3, iclass 17, count 2 2006.169.08:26:06.98#ibcon#about to read 4, iclass 17, count 2 2006.169.08:26:06.98#ibcon#read 4, iclass 17, count 2 2006.169.08:26:06.98#ibcon#about to read 5, iclass 17, count 2 2006.169.08:26:06.98#ibcon#read 5, iclass 17, count 2 2006.169.08:26:06.98#ibcon#about to read 6, iclass 17, count 2 2006.169.08:26:06.98#ibcon#read 6, iclass 17, count 2 2006.169.08:26:06.98#ibcon#end of sib2, iclass 17, count 2 2006.169.08:26:06.98#ibcon#*after write, iclass 17, count 2 2006.169.08:26:06.98#ibcon#*before return 0, iclass 17, count 2 2006.169.08:26:06.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:26:06.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.169.08:26:06.98#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.169.08:26:06.98#ibcon#ireg 7 cls_cnt 0 2006.169.08:26:06.98#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:26:07.10#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:26:07.10#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:26:07.10#ibcon#enter wrdev, iclass 17, count 0 2006.169.08:26:07.10#ibcon#first serial, iclass 17, count 0 2006.169.08:26:07.10#ibcon#enter sib2, iclass 17, count 0 2006.169.08:26:07.10#ibcon#flushed, iclass 17, count 0 2006.169.08:26:07.10#ibcon#about to write, iclass 17, count 0 2006.169.08:26:07.10#ibcon#wrote, iclass 17, count 0 2006.169.08:26:07.10#ibcon#about to read 3, iclass 17, count 0 2006.169.08:26:07.14#ibcon#read 3, iclass 17, count 0 2006.169.08:26:07.14#ibcon#about to read 4, iclass 17, count 0 2006.169.08:26:07.14#ibcon#read 4, iclass 17, count 0 2006.169.08:26:07.14#ibcon#about to read 5, iclass 17, count 0 2006.169.08:26:07.14#ibcon#read 5, iclass 17, count 0 2006.169.08:26:07.14#ibcon#about to read 6, iclass 17, count 0 2006.169.08:26:07.14#ibcon#read 6, iclass 17, count 0 2006.169.08:26:07.14#ibcon#end of sib2, iclass 17, count 0 2006.169.08:26:07.14#ibcon#*mode == 0, iclass 17, count 0 2006.169.08:26:07.14#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.169.08:26:07.14#ibcon#[25=USB\r\n] 2006.169.08:26:07.14#ibcon#*before write, iclass 17, count 0 2006.169.08:26:07.14#ibcon#enter sib2, iclass 17, count 0 2006.169.08:26:07.14#ibcon#flushed, iclass 17, count 0 2006.169.08:26:07.14#ibcon#about to write, iclass 17, count 0 2006.169.08:26:07.14#ibcon#wrote, iclass 17, count 0 2006.169.08:26:07.14#ibcon#about to read 3, iclass 17, count 0 2006.169.08:26:07.17#ibcon#read 3, iclass 17, count 0 2006.169.08:26:07.17#ibcon#about to read 4, iclass 17, count 0 2006.169.08:26:07.17#ibcon#read 4, iclass 17, count 0 2006.169.08:26:07.17#ibcon#about to read 5, iclass 17, count 0 2006.169.08:26:07.17#ibcon#read 5, iclass 17, count 0 2006.169.08:26:07.17#ibcon#about to read 6, iclass 17, count 0 2006.169.08:26:07.17#ibcon#read 6, iclass 17, count 0 2006.169.08:26:07.17#ibcon#end of sib2, iclass 17, count 0 2006.169.08:26:07.17#ibcon#*after write, iclass 17, count 0 2006.169.08:26:07.17#ibcon#*before return 0, iclass 17, count 0 2006.169.08:26:07.17#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:26:07.17#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.169.08:26:07.17#ibcon#about to clear, iclass 17 cls_cnt 0 2006.169.08:26:07.17#ibcon#cleared, iclass 17 cls_cnt 0 2006.169.08:26:07.17$vc4f8/valo=8,852.99 2006.169.08:26:07.17#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.169.08:26:07.17#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.169.08:26:07.17#ibcon#ireg 17 cls_cnt 0 2006.169.08:26:07.17#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:26:07.17#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:26:07.17#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:26:07.17#ibcon#enter wrdev, iclass 20, count 0 2006.169.08:26:07.17#ibcon#first serial, iclass 20, count 0 2006.169.08:26:07.17#ibcon#enter sib2, iclass 20, count 0 2006.169.08:26:07.17#ibcon#flushed, iclass 20, count 0 2006.169.08:26:07.17#ibcon#about to write, iclass 20, count 0 2006.169.08:26:07.17#ibcon#wrote, iclass 20, count 0 2006.169.08:26:07.17#ibcon#about to read 3, iclass 20, count 0 2006.169.08:26:07.19#ibcon#read 3, iclass 20, count 0 2006.169.08:26:07.19#ibcon#about to read 4, iclass 20, count 0 2006.169.08:26:07.19#ibcon#read 4, iclass 20, count 0 2006.169.08:26:07.19#ibcon#about to read 5, iclass 20, count 0 2006.169.08:26:07.19#ibcon#read 5, iclass 20, count 0 2006.169.08:26:07.19#ibcon#about to read 6, iclass 20, count 0 2006.169.08:26:07.19#ibcon#read 6, iclass 20, count 0 2006.169.08:26:07.19#ibcon#end of sib2, iclass 20, count 0 2006.169.08:26:07.19#ibcon#*mode == 0, iclass 20, count 0 2006.169.08:26:07.19#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.169.08:26:07.19#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.08:26:07.19#ibcon#*before write, iclass 20, count 0 2006.169.08:26:07.19#ibcon#enter sib2, iclass 20, count 0 2006.169.08:26:07.19#ibcon#flushed, iclass 20, count 0 2006.169.08:26:07.19#ibcon#about to write, iclass 20, count 0 2006.169.08:26:07.19#ibcon#wrote, iclass 20, count 0 2006.169.08:26:07.19#ibcon#about to read 3, iclass 20, count 0 2006.169.08:26:07.23#ibcon#read 3, iclass 20, count 0 2006.169.08:26:07.23#ibcon#about to read 4, iclass 20, count 0 2006.169.08:26:07.23#ibcon#read 4, iclass 20, count 0 2006.169.08:26:07.23#ibcon#about to read 5, iclass 20, count 0 2006.169.08:26:07.23#ibcon#read 5, iclass 20, count 0 2006.169.08:26:07.23#ibcon#about to read 6, iclass 20, count 0 2006.169.08:26:07.23#ibcon#read 6, iclass 20, count 0 2006.169.08:26:07.23#ibcon#end of sib2, iclass 20, count 0 2006.169.08:26:07.23#ibcon#*after write, iclass 20, count 0 2006.169.08:26:07.23#ibcon#*before return 0, iclass 20, count 0 2006.169.08:26:07.23#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:26:07.23#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.169.08:26:07.23#ibcon#about to clear, iclass 20 cls_cnt 0 2006.169.08:26:07.23#ibcon#cleared, iclass 20 cls_cnt 0 2006.169.08:26:07.23$vc4f8/va=8,7 2006.169.08:26:07.23#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.169.08:26:07.23#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.169.08:26:07.23#ibcon#ireg 11 cls_cnt 2 2006.169.08:26:07.23#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:26:07.29#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:26:07.29#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:26:07.29#ibcon#enter wrdev, iclass 22, count 2 2006.169.08:26:07.29#ibcon#first serial, iclass 22, count 2 2006.169.08:26:07.29#ibcon#enter sib2, iclass 22, count 2 2006.169.08:26:07.29#ibcon#flushed, iclass 22, count 2 2006.169.08:26:07.29#ibcon#about to write, iclass 22, count 2 2006.169.08:26:07.29#ibcon#wrote, iclass 22, count 2 2006.169.08:26:07.29#ibcon#about to read 3, iclass 22, count 2 2006.169.08:26:07.31#ibcon#read 3, iclass 22, count 2 2006.169.08:26:07.31#ibcon#about to read 4, iclass 22, count 2 2006.169.08:26:07.31#ibcon#read 4, iclass 22, count 2 2006.169.08:26:07.31#ibcon#about to read 5, iclass 22, count 2 2006.169.08:26:07.31#ibcon#read 5, iclass 22, count 2 2006.169.08:26:07.31#ibcon#about to read 6, iclass 22, count 2 2006.169.08:26:07.31#ibcon#read 6, iclass 22, count 2 2006.169.08:26:07.31#ibcon#end of sib2, iclass 22, count 2 2006.169.08:26:07.31#ibcon#*mode == 0, iclass 22, count 2 2006.169.08:26:07.31#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.169.08:26:07.31#ibcon#[25=AT08-07\r\n] 2006.169.08:26:07.31#ibcon#*before write, iclass 22, count 2 2006.169.08:26:07.31#ibcon#enter sib2, iclass 22, count 2 2006.169.08:26:07.31#ibcon#flushed, iclass 22, count 2 2006.169.08:26:07.31#ibcon#about to write, iclass 22, count 2 2006.169.08:26:07.31#ibcon#wrote, iclass 22, count 2 2006.169.08:26:07.31#ibcon#about to read 3, iclass 22, count 2 2006.169.08:26:07.34#ibcon#read 3, iclass 22, count 2 2006.169.08:26:07.34#ibcon#about to read 4, iclass 22, count 2 2006.169.08:26:07.34#ibcon#read 4, iclass 22, count 2 2006.169.08:26:07.34#ibcon#about to read 5, iclass 22, count 2 2006.169.08:26:07.34#ibcon#read 5, iclass 22, count 2 2006.169.08:26:07.34#ibcon#about to read 6, iclass 22, count 2 2006.169.08:26:07.34#ibcon#read 6, iclass 22, count 2 2006.169.08:26:07.34#ibcon#end of sib2, iclass 22, count 2 2006.169.08:26:07.34#ibcon#*after write, iclass 22, count 2 2006.169.08:26:07.34#ibcon#*before return 0, iclass 22, count 2 2006.169.08:26:07.34#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:26:07.34#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.169.08:26:07.34#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.169.08:26:07.34#ibcon#ireg 7 cls_cnt 0 2006.169.08:26:07.34#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:26:07.46#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:26:07.46#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:26:07.46#ibcon#enter wrdev, iclass 22, count 0 2006.169.08:26:07.46#ibcon#first serial, iclass 22, count 0 2006.169.08:26:07.46#ibcon#enter sib2, iclass 22, count 0 2006.169.08:26:07.46#ibcon#flushed, iclass 22, count 0 2006.169.08:26:07.46#ibcon#about to write, iclass 22, count 0 2006.169.08:26:07.46#ibcon#wrote, iclass 22, count 0 2006.169.08:26:07.46#ibcon#about to read 3, iclass 22, count 0 2006.169.08:26:07.48#ibcon#read 3, iclass 22, count 0 2006.169.08:26:07.48#ibcon#about to read 4, iclass 22, count 0 2006.169.08:26:07.48#ibcon#read 4, iclass 22, count 0 2006.169.08:26:07.48#ibcon#about to read 5, iclass 22, count 0 2006.169.08:26:07.48#ibcon#read 5, iclass 22, count 0 2006.169.08:26:07.48#ibcon#about to read 6, iclass 22, count 0 2006.169.08:26:07.48#ibcon#read 6, iclass 22, count 0 2006.169.08:26:07.48#ibcon#end of sib2, iclass 22, count 0 2006.169.08:26:07.48#ibcon#*mode == 0, iclass 22, count 0 2006.169.08:26:07.48#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.169.08:26:07.48#ibcon#[25=USB\r\n] 2006.169.08:26:07.48#ibcon#*before write, iclass 22, count 0 2006.169.08:26:07.48#ibcon#enter sib2, iclass 22, count 0 2006.169.08:26:07.48#ibcon#flushed, iclass 22, count 0 2006.169.08:26:07.48#ibcon#about to write, iclass 22, count 0 2006.169.08:26:07.48#ibcon#wrote, iclass 22, count 0 2006.169.08:26:07.48#ibcon#about to read 3, iclass 22, count 0 2006.169.08:26:07.51#ibcon#read 3, iclass 22, count 0 2006.169.08:26:07.51#ibcon#about to read 4, iclass 22, count 0 2006.169.08:26:07.51#ibcon#read 4, iclass 22, count 0 2006.169.08:26:07.51#ibcon#about to read 5, iclass 22, count 0 2006.169.08:26:07.51#ibcon#read 5, iclass 22, count 0 2006.169.08:26:07.51#ibcon#about to read 6, iclass 22, count 0 2006.169.08:26:07.51#ibcon#read 6, iclass 22, count 0 2006.169.08:26:07.51#ibcon#end of sib2, iclass 22, count 0 2006.169.08:26:07.51#ibcon#*after write, iclass 22, count 0 2006.169.08:26:07.51#ibcon#*before return 0, iclass 22, count 0 2006.169.08:26:07.51#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:26:07.51#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.169.08:26:07.51#ibcon#about to clear, iclass 22 cls_cnt 0 2006.169.08:26:07.51#ibcon#cleared, iclass 22 cls_cnt 0 2006.169.08:26:07.51$vc4f8/vblo=1,632.99 2006.169.08:26:07.51#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.169.08:26:07.51#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.169.08:26:07.51#ibcon#ireg 17 cls_cnt 0 2006.169.08:26:07.51#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:26:07.51#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:26:07.51#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:26:07.51#ibcon#enter wrdev, iclass 24, count 0 2006.169.08:26:07.51#ibcon#first serial, iclass 24, count 0 2006.169.08:26:07.51#ibcon#enter sib2, iclass 24, count 0 2006.169.08:26:07.51#ibcon#flushed, iclass 24, count 0 2006.169.08:26:07.51#ibcon#about to write, iclass 24, count 0 2006.169.08:26:07.51#ibcon#wrote, iclass 24, count 0 2006.169.08:26:07.51#ibcon#about to read 3, iclass 24, count 0 2006.169.08:26:07.53#ibcon#read 3, iclass 24, count 0 2006.169.08:26:07.53#ibcon#about to read 4, iclass 24, count 0 2006.169.08:26:07.53#ibcon#read 4, iclass 24, count 0 2006.169.08:26:07.53#ibcon#about to read 5, iclass 24, count 0 2006.169.08:26:07.53#ibcon#read 5, iclass 24, count 0 2006.169.08:26:07.53#ibcon#about to read 6, iclass 24, count 0 2006.169.08:26:07.53#ibcon#read 6, iclass 24, count 0 2006.169.08:26:07.53#ibcon#end of sib2, iclass 24, count 0 2006.169.08:26:07.53#ibcon#*mode == 0, iclass 24, count 0 2006.169.08:26:07.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.169.08:26:07.53#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.08:26:07.53#ibcon#*before write, iclass 24, count 0 2006.169.08:26:07.53#ibcon#enter sib2, iclass 24, count 0 2006.169.08:26:07.53#ibcon#flushed, iclass 24, count 0 2006.169.08:26:07.53#ibcon#about to write, iclass 24, count 0 2006.169.08:26:07.53#ibcon#wrote, iclass 24, count 0 2006.169.08:26:07.53#ibcon#about to read 3, iclass 24, count 0 2006.169.08:26:07.57#ibcon#read 3, iclass 24, count 0 2006.169.08:26:07.57#ibcon#about to read 4, iclass 24, count 0 2006.169.08:26:07.57#ibcon#read 4, iclass 24, count 0 2006.169.08:26:07.57#ibcon#about to read 5, iclass 24, count 0 2006.169.08:26:07.57#ibcon#read 5, iclass 24, count 0 2006.169.08:26:07.57#ibcon#about to read 6, iclass 24, count 0 2006.169.08:26:07.57#ibcon#read 6, iclass 24, count 0 2006.169.08:26:07.57#ibcon#end of sib2, iclass 24, count 0 2006.169.08:26:07.57#ibcon#*after write, iclass 24, count 0 2006.169.08:26:07.57#ibcon#*before return 0, iclass 24, count 0 2006.169.08:26:07.57#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:26:07.57#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.169.08:26:07.57#ibcon#about to clear, iclass 24 cls_cnt 0 2006.169.08:26:07.57#ibcon#cleared, iclass 24 cls_cnt 0 2006.169.08:26:07.57$vc4f8/vb=1,4 2006.169.08:26:07.57#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.169.08:26:07.57#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.169.08:26:07.57#ibcon#ireg 11 cls_cnt 2 2006.169.08:26:07.57#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.169.08:26:07.57#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.169.08:26:07.57#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.169.08:26:07.57#ibcon#enter wrdev, iclass 26, count 2 2006.169.08:26:07.57#ibcon#first serial, iclass 26, count 2 2006.169.08:26:07.57#ibcon#enter sib2, iclass 26, count 2 2006.169.08:26:07.57#ibcon#flushed, iclass 26, count 2 2006.169.08:26:07.57#ibcon#about to write, iclass 26, count 2 2006.169.08:26:07.57#ibcon#wrote, iclass 26, count 2 2006.169.08:26:07.57#ibcon#about to read 3, iclass 26, count 2 2006.169.08:26:07.59#ibcon#read 3, iclass 26, count 2 2006.169.08:26:07.59#ibcon#about to read 4, iclass 26, count 2 2006.169.08:26:07.59#ibcon#read 4, iclass 26, count 2 2006.169.08:26:07.59#ibcon#about to read 5, iclass 26, count 2 2006.169.08:26:07.59#ibcon#read 5, iclass 26, count 2 2006.169.08:26:07.59#ibcon#about to read 6, iclass 26, count 2 2006.169.08:26:07.59#ibcon#read 6, iclass 26, count 2 2006.169.08:26:07.59#ibcon#end of sib2, iclass 26, count 2 2006.169.08:26:07.59#ibcon#*mode == 0, iclass 26, count 2 2006.169.08:26:07.59#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.169.08:26:07.59#ibcon#[27=AT01-04\r\n] 2006.169.08:26:07.59#ibcon#*before write, iclass 26, count 2 2006.169.08:26:07.59#ibcon#enter sib2, iclass 26, count 2 2006.169.08:26:07.59#ibcon#flushed, iclass 26, count 2 2006.169.08:26:07.59#ibcon#about to write, iclass 26, count 2 2006.169.08:26:07.59#ibcon#wrote, iclass 26, count 2 2006.169.08:26:07.59#ibcon#about to read 3, iclass 26, count 2 2006.169.08:26:07.62#ibcon#read 3, iclass 26, count 2 2006.169.08:26:07.62#ibcon#about to read 4, iclass 26, count 2 2006.169.08:26:07.62#ibcon#read 4, iclass 26, count 2 2006.169.08:26:07.62#ibcon#about to read 5, iclass 26, count 2 2006.169.08:26:07.62#ibcon#read 5, iclass 26, count 2 2006.169.08:26:07.62#ibcon#about to read 6, iclass 26, count 2 2006.169.08:26:07.62#ibcon#read 6, iclass 26, count 2 2006.169.08:26:07.62#ibcon#end of sib2, iclass 26, count 2 2006.169.08:26:07.62#ibcon#*after write, iclass 26, count 2 2006.169.08:26:07.62#ibcon#*before return 0, iclass 26, count 2 2006.169.08:26:07.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.169.08:26:07.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.169.08:26:07.62#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.169.08:26:07.62#ibcon#ireg 7 cls_cnt 0 2006.169.08:26:07.62#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.169.08:26:07.74#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.169.08:26:07.74#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.169.08:26:07.74#ibcon#enter wrdev, iclass 26, count 0 2006.169.08:26:07.74#ibcon#first serial, iclass 26, count 0 2006.169.08:26:07.74#ibcon#enter sib2, iclass 26, count 0 2006.169.08:26:07.74#ibcon#flushed, iclass 26, count 0 2006.169.08:26:07.74#ibcon#about to write, iclass 26, count 0 2006.169.08:26:07.74#ibcon#wrote, iclass 26, count 0 2006.169.08:26:07.74#ibcon#about to read 3, iclass 26, count 0 2006.169.08:26:07.76#ibcon#read 3, iclass 26, count 0 2006.169.08:26:07.76#ibcon#about to read 4, iclass 26, count 0 2006.169.08:26:07.76#ibcon#read 4, iclass 26, count 0 2006.169.08:26:07.76#ibcon#about to read 5, iclass 26, count 0 2006.169.08:26:07.76#ibcon#read 5, iclass 26, count 0 2006.169.08:26:07.76#ibcon#about to read 6, iclass 26, count 0 2006.169.08:26:07.76#ibcon#read 6, iclass 26, count 0 2006.169.08:26:07.76#ibcon#end of sib2, iclass 26, count 0 2006.169.08:26:07.76#ibcon#*mode == 0, iclass 26, count 0 2006.169.08:26:07.76#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.169.08:26:07.76#ibcon#[27=USB\r\n] 2006.169.08:26:07.76#ibcon#*before write, iclass 26, count 0 2006.169.08:26:07.76#ibcon#enter sib2, iclass 26, count 0 2006.169.08:26:07.76#ibcon#flushed, iclass 26, count 0 2006.169.08:26:07.76#ibcon#about to write, iclass 26, count 0 2006.169.08:26:07.76#ibcon#wrote, iclass 26, count 0 2006.169.08:26:07.76#ibcon#about to read 3, iclass 26, count 0 2006.169.08:26:07.79#ibcon#read 3, iclass 26, count 0 2006.169.08:26:07.79#ibcon#about to read 4, iclass 26, count 0 2006.169.08:26:07.79#ibcon#read 4, iclass 26, count 0 2006.169.08:26:07.79#ibcon#about to read 5, iclass 26, count 0 2006.169.08:26:07.79#ibcon#read 5, iclass 26, count 0 2006.169.08:26:07.79#ibcon#about to read 6, iclass 26, count 0 2006.169.08:26:07.79#ibcon#read 6, iclass 26, count 0 2006.169.08:26:07.79#ibcon#end of sib2, iclass 26, count 0 2006.169.08:26:07.79#ibcon#*after write, iclass 26, count 0 2006.169.08:26:07.79#ibcon#*before return 0, iclass 26, count 0 2006.169.08:26:07.79#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.169.08:26:07.79#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.169.08:26:07.79#ibcon#about to clear, iclass 26 cls_cnt 0 2006.169.08:26:07.79#ibcon#cleared, iclass 26 cls_cnt 0 2006.169.08:26:07.79$vc4f8/vblo=2,640.99 2006.169.08:26:07.79#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.169.08:26:07.79#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.169.08:26:07.79#ibcon#ireg 17 cls_cnt 0 2006.169.08:26:07.79#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:26:07.79#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:26:07.79#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:26:07.79#ibcon#enter wrdev, iclass 28, count 0 2006.169.08:26:07.79#ibcon#first serial, iclass 28, count 0 2006.169.08:26:07.79#ibcon#enter sib2, iclass 28, count 0 2006.169.08:26:07.79#ibcon#flushed, iclass 28, count 0 2006.169.08:26:07.79#ibcon#about to write, iclass 28, count 0 2006.169.08:26:07.79#ibcon#wrote, iclass 28, count 0 2006.169.08:26:07.79#ibcon#about to read 3, iclass 28, count 0 2006.169.08:26:07.81#ibcon#read 3, iclass 28, count 0 2006.169.08:26:07.81#ibcon#about to read 4, iclass 28, count 0 2006.169.08:26:07.81#ibcon#read 4, iclass 28, count 0 2006.169.08:26:07.81#ibcon#about to read 5, iclass 28, count 0 2006.169.08:26:07.81#ibcon#read 5, iclass 28, count 0 2006.169.08:26:07.81#ibcon#about to read 6, iclass 28, count 0 2006.169.08:26:07.81#ibcon#read 6, iclass 28, count 0 2006.169.08:26:07.81#ibcon#end of sib2, iclass 28, count 0 2006.169.08:26:07.81#ibcon#*mode == 0, iclass 28, count 0 2006.169.08:26:07.81#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.169.08:26:07.81#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.08:26:07.81#ibcon#*before write, iclass 28, count 0 2006.169.08:26:07.81#ibcon#enter sib2, iclass 28, count 0 2006.169.08:26:07.81#ibcon#flushed, iclass 28, count 0 2006.169.08:26:07.81#ibcon#about to write, iclass 28, count 0 2006.169.08:26:07.81#ibcon#wrote, iclass 28, count 0 2006.169.08:26:07.81#ibcon#about to read 3, iclass 28, count 0 2006.169.08:26:07.85#ibcon#read 3, iclass 28, count 0 2006.169.08:26:07.85#ibcon#about to read 4, iclass 28, count 0 2006.169.08:26:07.85#ibcon#read 4, iclass 28, count 0 2006.169.08:26:07.85#ibcon#about to read 5, iclass 28, count 0 2006.169.08:26:07.85#ibcon#read 5, iclass 28, count 0 2006.169.08:26:07.85#ibcon#about to read 6, iclass 28, count 0 2006.169.08:26:07.85#ibcon#read 6, iclass 28, count 0 2006.169.08:26:07.85#ibcon#end of sib2, iclass 28, count 0 2006.169.08:26:07.85#ibcon#*after write, iclass 28, count 0 2006.169.08:26:07.85#ibcon#*before return 0, iclass 28, count 0 2006.169.08:26:07.85#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:26:07.85#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.169.08:26:07.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.169.08:26:07.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.169.08:26:07.85$vc4f8/vb=2,4 2006.169.08:26:07.85#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.169.08:26:07.85#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.169.08:26:07.85#ibcon#ireg 11 cls_cnt 2 2006.169.08:26:07.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:26:07.91#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:26:07.91#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:26:07.91#ibcon#enter wrdev, iclass 30, count 2 2006.169.08:26:07.91#ibcon#first serial, iclass 30, count 2 2006.169.08:26:07.91#ibcon#enter sib2, iclass 30, count 2 2006.169.08:26:07.91#ibcon#flushed, iclass 30, count 2 2006.169.08:26:07.91#ibcon#about to write, iclass 30, count 2 2006.169.08:26:07.91#ibcon#wrote, iclass 30, count 2 2006.169.08:26:07.91#ibcon#about to read 3, iclass 30, count 2 2006.169.08:26:07.93#ibcon#read 3, iclass 30, count 2 2006.169.08:26:07.93#ibcon#about to read 4, iclass 30, count 2 2006.169.08:26:07.93#ibcon#read 4, iclass 30, count 2 2006.169.08:26:07.93#ibcon#about to read 5, iclass 30, count 2 2006.169.08:26:07.93#ibcon#read 5, iclass 30, count 2 2006.169.08:26:07.93#ibcon#about to read 6, iclass 30, count 2 2006.169.08:26:07.93#ibcon#read 6, iclass 30, count 2 2006.169.08:26:07.93#ibcon#end of sib2, iclass 30, count 2 2006.169.08:26:07.93#ibcon#*mode == 0, iclass 30, count 2 2006.169.08:26:07.93#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.169.08:26:07.93#ibcon#[27=AT02-04\r\n] 2006.169.08:26:07.93#ibcon#*before write, iclass 30, count 2 2006.169.08:26:07.93#ibcon#enter sib2, iclass 30, count 2 2006.169.08:26:07.93#ibcon#flushed, iclass 30, count 2 2006.169.08:26:07.93#ibcon#about to write, iclass 30, count 2 2006.169.08:26:07.93#ibcon#wrote, iclass 30, count 2 2006.169.08:26:07.93#ibcon#about to read 3, iclass 30, count 2 2006.169.08:26:07.96#ibcon#read 3, iclass 30, count 2 2006.169.08:26:07.96#ibcon#about to read 4, iclass 30, count 2 2006.169.08:26:07.96#ibcon#read 4, iclass 30, count 2 2006.169.08:26:07.96#ibcon#about to read 5, iclass 30, count 2 2006.169.08:26:07.96#ibcon#read 5, iclass 30, count 2 2006.169.08:26:07.96#ibcon#about to read 6, iclass 30, count 2 2006.169.08:26:07.96#ibcon#read 6, iclass 30, count 2 2006.169.08:26:07.96#ibcon#end of sib2, iclass 30, count 2 2006.169.08:26:07.96#ibcon#*after write, iclass 30, count 2 2006.169.08:26:07.96#ibcon#*before return 0, iclass 30, count 2 2006.169.08:26:07.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:26:07.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.169.08:26:07.96#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.169.08:26:07.96#ibcon#ireg 7 cls_cnt 0 2006.169.08:26:07.96#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:26:08.08#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:26:08.08#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:26:08.08#ibcon#enter wrdev, iclass 30, count 0 2006.169.08:26:08.08#ibcon#first serial, iclass 30, count 0 2006.169.08:26:08.08#ibcon#enter sib2, iclass 30, count 0 2006.169.08:26:08.08#ibcon#flushed, iclass 30, count 0 2006.169.08:26:08.08#ibcon#about to write, iclass 30, count 0 2006.169.08:26:08.08#ibcon#wrote, iclass 30, count 0 2006.169.08:26:08.08#ibcon#about to read 3, iclass 30, count 0 2006.169.08:26:08.10#ibcon#read 3, iclass 30, count 0 2006.169.08:26:08.10#ibcon#about to read 4, iclass 30, count 0 2006.169.08:26:08.10#ibcon#read 4, iclass 30, count 0 2006.169.08:26:08.10#ibcon#about to read 5, iclass 30, count 0 2006.169.08:26:08.10#ibcon#read 5, iclass 30, count 0 2006.169.08:26:08.10#ibcon#about to read 6, iclass 30, count 0 2006.169.08:26:08.10#ibcon#read 6, iclass 30, count 0 2006.169.08:26:08.10#ibcon#end of sib2, iclass 30, count 0 2006.169.08:26:08.10#ibcon#*mode == 0, iclass 30, count 0 2006.169.08:26:08.10#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.169.08:26:08.10#ibcon#[27=USB\r\n] 2006.169.08:26:08.10#ibcon#*before write, iclass 30, count 0 2006.169.08:26:08.10#ibcon#enter sib2, iclass 30, count 0 2006.169.08:26:08.10#ibcon#flushed, iclass 30, count 0 2006.169.08:26:08.10#ibcon#about to write, iclass 30, count 0 2006.169.08:26:08.10#ibcon#wrote, iclass 30, count 0 2006.169.08:26:08.10#ibcon#about to read 3, iclass 30, count 0 2006.169.08:26:08.13#ibcon#read 3, iclass 30, count 0 2006.169.08:26:08.13#ibcon#about to read 4, iclass 30, count 0 2006.169.08:26:08.13#ibcon#read 4, iclass 30, count 0 2006.169.08:26:08.13#ibcon#about to read 5, iclass 30, count 0 2006.169.08:26:08.13#ibcon#read 5, iclass 30, count 0 2006.169.08:26:08.13#ibcon#about to read 6, iclass 30, count 0 2006.169.08:26:08.13#ibcon#read 6, iclass 30, count 0 2006.169.08:26:08.13#ibcon#end of sib2, iclass 30, count 0 2006.169.08:26:08.13#ibcon#*after write, iclass 30, count 0 2006.169.08:26:08.13#ibcon#*before return 0, iclass 30, count 0 2006.169.08:26:08.13#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:26:08.13#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.169.08:26:08.13#ibcon#about to clear, iclass 30 cls_cnt 0 2006.169.08:26:08.13#ibcon#cleared, iclass 30 cls_cnt 0 2006.169.08:26:08.13$vc4f8/vblo=3,656.99 2006.169.08:26:08.13#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.169.08:26:08.13#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.169.08:26:08.13#ibcon#ireg 17 cls_cnt 0 2006.169.08:26:08.13#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:26:08.13#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:26:08.13#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:26:08.13#ibcon#enter wrdev, iclass 32, count 0 2006.169.08:26:08.13#ibcon#first serial, iclass 32, count 0 2006.169.08:26:08.13#ibcon#enter sib2, iclass 32, count 0 2006.169.08:26:08.13#ibcon#flushed, iclass 32, count 0 2006.169.08:26:08.13#ibcon#about to write, iclass 32, count 0 2006.169.08:26:08.13#ibcon#wrote, iclass 32, count 0 2006.169.08:26:08.13#ibcon#about to read 3, iclass 32, count 0 2006.169.08:26:08.15#ibcon#read 3, iclass 32, count 0 2006.169.08:26:08.15#ibcon#about to read 4, iclass 32, count 0 2006.169.08:26:08.15#ibcon#read 4, iclass 32, count 0 2006.169.08:26:08.15#ibcon#about to read 5, iclass 32, count 0 2006.169.08:26:08.15#ibcon#read 5, iclass 32, count 0 2006.169.08:26:08.15#ibcon#about to read 6, iclass 32, count 0 2006.169.08:26:08.15#ibcon#read 6, iclass 32, count 0 2006.169.08:26:08.15#ibcon#end of sib2, iclass 32, count 0 2006.169.08:26:08.15#ibcon#*mode == 0, iclass 32, count 0 2006.169.08:26:08.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.169.08:26:08.15#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.08:26:08.15#ibcon#*before write, iclass 32, count 0 2006.169.08:26:08.15#ibcon#enter sib2, iclass 32, count 0 2006.169.08:26:08.15#ibcon#flushed, iclass 32, count 0 2006.169.08:26:08.15#ibcon#about to write, iclass 32, count 0 2006.169.08:26:08.15#ibcon#wrote, iclass 32, count 0 2006.169.08:26:08.15#ibcon#about to read 3, iclass 32, count 0 2006.169.08:26:08.19#ibcon#read 3, iclass 32, count 0 2006.169.08:26:08.19#ibcon#about to read 4, iclass 32, count 0 2006.169.08:26:08.19#ibcon#read 4, iclass 32, count 0 2006.169.08:26:08.19#ibcon#about to read 5, iclass 32, count 0 2006.169.08:26:08.19#ibcon#read 5, iclass 32, count 0 2006.169.08:26:08.19#ibcon#about to read 6, iclass 32, count 0 2006.169.08:26:08.19#ibcon#read 6, iclass 32, count 0 2006.169.08:26:08.19#ibcon#end of sib2, iclass 32, count 0 2006.169.08:26:08.19#ibcon#*after write, iclass 32, count 0 2006.169.08:26:08.19#ibcon#*before return 0, iclass 32, count 0 2006.169.08:26:08.19#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:26:08.19#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.169.08:26:08.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.169.08:26:08.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.169.08:26:08.19$vc4f8/vb=3,4 2006.169.08:26:08.19#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.169.08:26:08.19#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.169.08:26:08.19#ibcon#ireg 11 cls_cnt 2 2006.169.08:26:08.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:26:08.25#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:26:08.25#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:26:08.25#ibcon#enter wrdev, iclass 34, count 2 2006.169.08:26:08.25#ibcon#first serial, iclass 34, count 2 2006.169.08:26:08.25#ibcon#enter sib2, iclass 34, count 2 2006.169.08:26:08.25#ibcon#flushed, iclass 34, count 2 2006.169.08:26:08.25#ibcon#about to write, iclass 34, count 2 2006.169.08:26:08.25#ibcon#wrote, iclass 34, count 2 2006.169.08:26:08.25#ibcon#about to read 3, iclass 34, count 2 2006.169.08:26:08.27#ibcon#read 3, iclass 34, count 2 2006.169.08:26:08.27#ibcon#about to read 4, iclass 34, count 2 2006.169.08:26:08.27#ibcon#read 4, iclass 34, count 2 2006.169.08:26:08.27#ibcon#about to read 5, iclass 34, count 2 2006.169.08:26:08.27#ibcon#read 5, iclass 34, count 2 2006.169.08:26:08.27#ibcon#about to read 6, iclass 34, count 2 2006.169.08:26:08.27#ibcon#read 6, iclass 34, count 2 2006.169.08:26:08.27#ibcon#end of sib2, iclass 34, count 2 2006.169.08:26:08.27#ibcon#*mode == 0, iclass 34, count 2 2006.169.08:26:08.27#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.169.08:26:08.27#ibcon#[27=AT03-04\r\n] 2006.169.08:26:08.27#ibcon#*before write, iclass 34, count 2 2006.169.08:26:08.27#ibcon#enter sib2, iclass 34, count 2 2006.169.08:26:08.27#ibcon#flushed, iclass 34, count 2 2006.169.08:26:08.27#ibcon#about to write, iclass 34, count 2 2006.169.08:26:08.27#ibcon#wrote, iclass 34, count 2 2006.169.08:26:08.27#ibcon#about to read 3, iclass 34, count 2 2006.169.08:26:08.30#ibcon#read 3, iclass 34, count 2 2006.169.08:26:08.30#ibcon#about to read 4, iclass 34, count 2 2006.169.08:26:08.30#ibcon#read 4, iclass 34, count 2 2006.169.08:26:08.30#ibcon#about to read 5, iclass 34, count 2 2006.169.08:26:08.30#ibcon#read 5, iclass 34, count 2 2006.169.08:26:08.30#ibcon#about to read 6, iclass 34, count 2 2006.169.08:26:08.30#ibcon#read 6, iclass 34, count 2 2006.169.08:26:08.30#ibcon#end of sib2, iclass 34, count 2 2006.169.08:26:08.30#ibcon#*after write, iclass 34, count 2 2006.169.08:26:08.30#ibcon#*before return 0, iclass 34, count 2 2006.169.08:26:08.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:26:08.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.169.08:26:08.30#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.169.08:26:08.30#ibcon#ireg 7 cls_cnt 0 2006.169.08:26:08.30#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:26:08.42#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:26:08.42#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:26:08.42#ibcon#enter wrdev, iclass 34, count 0 2006.169.08:26:08.42#ibcon#first serial, iclass 34, count 0 2006.169.08:26:08.42#ibcon#enter sib2, iclass 34, count 0 2006.169.08:26:08.42#ibcon#flushed, iclass 34, count 0 2006.169.08:26:08.42#ibcon#about to write, iclass 34, count 0 2006.169.08:26:08.42#ibcon#wrote, iclass 34, count 0 2006.169.08:26:08.42#ibcon#about to read 3, iclass 34, count 0 2006.169.08:26:08.44#ibcon#read 3, iclass 34, count 0 2006.169.08:26:08.44#ibcon#about to read 4, iclass 34, count 0 2006.169.08:26:08.44#ibcon#read 4, iclass 34, count 0 2006.169.08:26:08.44#ibcon#about to read 5, iclass 34, count 0 2006.169.08:26:08.44#ibcon#read 5, iclass 34, count 0 2006.169.08:26:08.44#ibcon#about to read 6, iclass 34, count 0 2006.169.08:26:08.44#ibcon#read 6, iclass 34, count 0 2006.169.08:26:08.44#ibcon#end of sib2, iclass 34, count 0 2006.169.08:26:08.44#ibcon#*mode == 0, iclass 34, count 0 2006.169.08:26:08.44#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.169.08:26:08.44#ibcon#[27=USB\r\n] 2006.169.08:26:08.44#ibcon#*before write, iclass 34, count 0 2006.169.08:26:08.44#ibcon#enter sib2, iclass 34, count 0 2006.169.08:26:08.44#ibcon#flushed, iclass 34, count 0 2006.169.08:26:08.44#ibcon#about to write, iclass 34, count 0 2006.169.08:26:08.44#ibcon#wrote, iclass 34, count 0 2006.169.08:26:08.44#ibcon#about to read 3, iclass 34, count 0 2006.169.08:26:08.47#ibcon#read 3, iclass 34, count 0 2006.169.08:26:08.47#ibcon#about to read 4, iclass 34, count 0 2006.169.08:26:08.47#ibcon#read 4, iclass 34, count 0 2006.169.08:26:08.47#ibcon#about to read 5, iclass 34, count 0 2006.169.08:26:08.47#ibcon#read 5, iclass 34, count 0 2006.169.08:26:08.47#ibcon#about to read 6, iclass 34, count 0 2006.169.08:26:08.47#ibcon#read 6, iclass 34, count 0 2006.169.08:26:08.47#ibcon#end of sib2, iclass 34, count 0 2006.169.08:26:08.47#ibcon#*after write, iclass 34, count 0 2006.169.08:26:08.47#ibcon#*before return 0, iclass 34, count 0 2006.169.08:26:08.47#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:26:08.47#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.169.08:26:08.47#ibcon#about to clear, iclass 34 cls_cnt 0 2006.169.08:26:08.47#ibcon#cleared, iclass 34 cls_cnt 0 2006.169.08:26:08.47$vc4f8/vblo=4,712.99 2006.169.08:26:08.47#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.169.08:26:08.47#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.169.08:26:08.47#ibcon#ireg 17 cls_cnt 0 2006.169.08:26:08.47#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:26:08.47#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:26:08.47#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:26:08.47#ibcon#enter wrdev, iclass 36, count 0 2006.169.08:26:08.47#ibcon#first serial, iclass 36, count 0 2006.169.08:26:08.47#ibcon#enter sib2, iclass 36, count 0 2006.169.08:26:08.47#ibcon#flushed, iclass 36, count 0 2006.169.08:26:08.47#ibcon#about to write, iclass 36, count 0 2006.169.08:26:08.47#ibcon#wrote, iclass 36, count 0 2006.169.08:26:08.47#ibcon#about to read 3, iclass 36, count 0 2006.169.08:26:08.49#ibcon#read 3, iclass 36, count 0 2006.169.08:26:08.49#ibcon#about to read 4, iclass 36, count 0 2006.169.08:26:08.49#ibcon#read 4, iclass 36, count 0 2006.169.08:26:08.49#ibcon#about to read 5, iclass 36, count 0 2006.169.08:26:08.49#ibcon#read 5, iclass 36, count 0 2006.169.08:26:08.49#ibcon#about to read 6, iclass 36, count 0 2006.169.08:26:08.49#ibcon#read 6, iclass 36, count 0 2006.169.08:26:08.49#ibcon#end of sib2, iclass 36, count 0 2006.169.08:26:08.49#ibcon#*mode == 0, iclass 36, count 0 2006.169.08:26:08.49#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.169.08:26:08.49#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.08:26:08.49#ibcon#*before write, iclass 36, count 0 2006.169.08:26:08.49#ibcon#enter sib2, iclass 36, count 0 2006.169.08:26:08.49#ibcon#flushed, iclass 36, count 0 2006.169.08:26:08.49#ibcon#about to write, iclass 36, count 0 2006.169.08:26:08.49#ibcon#wrote, iclass 36, count 0 2006.169.08:26:08.49#ibcon#about to read 3, iclass 36, count 0 2006.169.08:26:08.53#ibcon#read 3, iclass 36, count 0 2006.169.08:26:08.53#ibcon#about to read 4, iclass 36, count 0 2006.169.08:26:08.53#ibcon#read 4, iclass 36, count 0 2006.169.08:26:08.53#ibcon#about to read 5, iclass 36, count 0 2006.169.08:26:08.53#ibcon#read 5, iclass 36, count 0 2006.169.08:26:08.53#ibcon#about to read 6, iclass 36, count 0 2006.169.08:26:08.53#ibcon#read 6, iclass 36, count 0 2006.169.08:26:08.53#ibcon#end of sib2, iclass 36, count 0 2006.169.08:26:08.53#ibcon#*after write, iclass 36, count 0 2006.169.08:26:08.53#ibcon#*before return 0, iclass 36, count 0 2006.169.08:26:08.53#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:26:08.53#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.169.08:26:08.53#ibcon#about to clear, iclass 36 cls_cnt 0 2006.169.08:26:08.53#ibcon#cleared, iclass 36 cls_cnt 0 2006.169.08:26:08.53$vc4f8/vb=4,4 2006.169.08:26:08.53#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.169.08:26:08.53#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.169.08:26:08.53#ibcon#ireg 11 cls_cnt 2 2006.169.08:26:08.53#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:26:08.59#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:26:08.59#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:26:08.59#ibcon#enter wrdev, iclass 38, count 2 2006.169.08:26:08.59#ibcon#first serial, iclass 38, count 2 2006.169.08:26:08.59#ibcon#enter sib2, iclass 38, count 2 2006.169.08:26:08.59#ibcon#flushed, iclass 38, count 2 2006.169.08:26:08.59#ibcon#about to write, iclass 38, count 2 2006.169.08:26:08.59#ibcon#wrote, iclass 38, count 2 2006.169.08:26:08.59#ibcon#about to read 3, iclass 38, count 2 2006.169.08:26:08.61#ibcon#read 3, iclass 38, count 2 2006.169.08:26:08.61#ibcon#about to read 4, iclass 38, count 2 2006.169.08:26:08.61#ibcon#read 4, iclass 38, count 2 2006.169.08:26:08.61#ibcon#about to read 5, iclass 38, count 2 2006.169.08:26:08.61#ibcon#read 5, iclass 38, count 2 2006.169.08:26:08.61#ibcon#about to read 6, iclass 38, count 2 2006.169.08:26:08.61#ibcon#read 6, iclass 38, count 2 2006.169.08:26:08.61#ibcon#end of sib2, iclass 38, count 2 2006.169.08:26:08.61#ibcon#*mode == 0, iclass 38, count 2 2006.169.08:26:08.61#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.169.08:26:08.61#ibcon#[27=AT04-04\r\n] 2006.169.08:26:08.61#ibcon#*before write, iclass 38, count 2 2006.169.08:26:08.61#ibcon#enter sib2, iclass 38, count 2 2006.169.08:26:08.61#ibcon#flushed, iclass 38, count 2 2006.169.08:26:08.61#ibcon#about to write, iclass 38, count 2 2006.169.08:26:08.61#ibcon#wrote, iclass 38, count 2 2006.169.08:26:08.61#ibcon#about to read 3, iclass 38, count 2 2006.169.08:26:08.64#ibcon#read 3, iclass 38, count 2 2006.169.08:26:08.64#ibcon#about to read 4, iclass 38, count 2 2006.169.08:26:08.64#ibcon#read 4, iclass 38, count 2 2006.169.08:26:08.64#ibcon#about to read 5, iclass 38, count 2 2006.169.08:26:08.64#ibcon#read 5, iclass 38, count 2 2006.169.08:26:08.64#ibcon#about to read 6, iclass 38, count 2 2006.169.08:26:08.64#ibcon#read 6, iclass 38, count 2 2006.169.08:26:08.64#ibcon#end of sib2, iclass 38, count 2 2006.169.08:26:08.64#ibcon#*after write, iclass 38, count 2 2006.169.08:26:08.64#ibcon#*before return 0, iclass 38, count 2 2006.169.08:26:08.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:26:08.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.169.08:26:08.64#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.169.08:26:08.64#ibcon#ireg 7 cls_cnt 0 2006.169.08:26:08.64#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:26:08.76#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:26:08.76#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:26:08.76#ibcon#enter wrdev, iclass 38, count 0 2006.169.08:26:08.76#ibcon#first serial, iclass 38, count 0 2006.169.08:26:08.76#ibcon#enter sib2, iclass 38, count 0 2006.169.08:26:08.76#ibcon#flushed, iclass 38, count 0 2006.169.08:26:08.76#ibcon#about to write, iclass 38, count 0 2006.169.08:26:08.76#ibcon#wrote, iclass 38, count 0 2006.169.08:26:08.76#ibcon#about to read 3, iclass 38, count 0 2006.169.08:26:08.78#ibcon#read 3, iclass 38, count 0 2006.169.08:26:08.78#ibcon#about to read 4, iclass 38, count 0 2006.169.08:26:08.78#ibcon#read 4, iclass 38, count 0 2006.169.08:26:08.78#ibcon#about to read 5, iclass 38, count 0 2006.169.08:26:08.78#ibcon#read 5, iclass 38, count 0 2006.169.08:26:08.78#ibcon#about to read 6, iclass 38, count 0 2006.169.08:26:08.78#ibcon#read 6, iclass 38, count 0 2006.169.08:26:08.78#ibcon#end of sib2, iclass 38, count 0 2006.169.08:26:08.78#ibcon#*mode == 0, iclass 38, count 0 2006.169.08:26:08.78#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.169.08:26:08.78#ibcon#[27=USB\r\n] 2006.169.08:26:08.78#ibcon#*before write, iclass 38, count 0 2006.169.08:26:08.78#ibcon#enter sib2, iclass 38, count 0 2006.169.08:26:08.78#ibcon#flushed, iclass 38, count 0 2006.169.08:26:08.78#ibcon#about to write, iclass 38, count 0 2006.169.08:26:08.78#ibcon#wrote, iclass 38, count 0 2006.169.08:26:08.78#ibcon#about to read 3, iclass 38, count 0 2006.169.08:26:08.81#ibcon#read 3, iclass 38, count 0 2006.169.08:26:08.81#ibcon#about to read 4, iclass 38, count 0 2006.169.08:26:08.81#ibcon#read 4, iclass 38, count 0 2006.169.08:26:08.81#ibcon#about to read 5, iclass 38, count 0 2006.169.08:26:08.81#ibcon#read 5, iclass 38, count 0 2006.169.08:26:08.81#ibcon#about to read 6, iclass 38, count 0 2006.169.08:26:08.81#ibcon#read 6, iclass 38, count 0 2006.169.08:26:08.81#ibcon#end of sib2, iclass 38, count 0 2006.169.08:26:08.81#ibcon#*after write, iclass 38, count 0 2006.169.08:26:08.81#ibcon#*before return 0, iclass 38, count 0 2006.169.08:26:08.81#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:26:08.81#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.169.08:26:08.81#ibcon#about to clear, iclass 38 cls_cnt 0 2006.169.08:26:08.81#ibcon#cleared, iclass 38 cls_cnt 0 2006.169.08:26:08.81$vc4f8/vblo=5,744.99 2006.169.08:26:08.81#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.169.08:26:08.81#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.169.08:26:08.81#ibcon#ireg 17 cls_cnt 0 2006.169.08:26:08.81#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:26:08.81#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:26:08.81#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:26:08.81#ibcon#enter wrdev, iclass 40, count 0 2006.169.08:26:08.81#ibcon#first serial, iclass 40, count 0 2006.169.08:26:08.81#ibcon#enter sib2, iclass 40, count 0 2006.169.08:26:08.81#ibcon#flushed, iclass 40, count 0 2006.169.08:26:08.81#ibcon#about to write, iclass 40, count 0 2006.169.08:26:08.81#ibcon#wrote, iclass 40, count 0 2006.169.08:26:08.81#ibcon#about to read 3, iclass 40, count 0 2006.169.08:26:08.83#ibcon#read 3, iclass 40, count 0 2006.169.08:26:08.83#ibcon#about to read 4, iclass 40, count 0 2006.169.08:26:08.83#ibcon#read 4, iclass 40, count 0 2006.169.08:26:08.83#ibcon#about to read 5, iclass 40, count 0 2006.169.08:26:08.83#ibcon#read 5, iclass 40, count 0 2006.169.08:26:08.83#ibcon#about to read 6, iclass 40, count 0 2006.169.08:26:08.83#ibcon#read 6, iclass 40, count 0 2006.169.08:26:08.83#ibcon#end of sib2, iclass 40, count 0 2006.169.08:26:08.83#ibcon#*mode == 0, iclass 40, count 0 2006.169.08:26:08.83#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.169.08:26:08.83#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.08:26:08.83#ibcon#*before write, iclass 40, count 0 2006.169.08:26:08.83#ibcon#enter sib2, iclass 40, count 0 2006.169.08:26:08.83#ibcon#flushed, iclass 40, count 0 2006.169.08:26:08.83#ibcon#about to write, iclass 40, count 0 2006.169.08:26:08.83#ibcon#wrote, iclass 40, count 0 2006.169.08:26:08.83#ibcon#about to read 3, iclass 40, count 0 2006.169.08:26:08.87#ibcon#read 3, iclass 40, count 0 2006.169.08:26:08.87#ibcon#about to read 4, iclass 40, count 0 2006.169.08:26:08.87#ibcon#read 4, iclass 40, count 0 2006.169.08:26:08.87#ibcon#about to read 5, iclass 40, count 0 2006.169.08:26:08.87#ibcon#read 5, iclass 40, count 0 2006.169.08:26:08.87#ibcon#about to read 6, iclass 40, count 0 2006.169.08:26:08.87#ibcon#read 6, iclass 40, count 0 2006.169.08:26:08.87#ibcon#end of sib2, iclass 40, count 0 2006.169.08:26:08.87#ibcon#*after write, iclass 40, count 0 2006.169.08:26:08.87#ibcon#*before return 0, iclass 40, count 0 2006.169.08:26:08.87#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:26:08.87#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.169.08:26:08.87#ibcon#about to clear, iclass 40 cls_cnt 0 2006.169.08:26:08.87#ibcon#cleared, iclass 40 cls_cnt 0 2006.169.08:26:08.87$vc4f8/vb=5,4 2006.169.08:26:08.87#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.169.08:26:08.87#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.169.08:26:08.87#ibcon#ireg 11 cls_cnt 2 2006.169.08:26:08.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:26:08.93#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:26:08.93#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:26:08.93#ibcon#enter wrdev, iclass 4, count 2 2006.169.08:26:08.93#ibcon#first serial, iclass 4, count 2 2006.169.08:26:08.93#ibcon#enter sib2, iclass 4, count 2 2006.169.08:26:08.93#ibcon#flushed, iclass 4, count 2 2006.169.08:26:08.93#ibcon#about to write, iclass 4, count 2 2006.169.08:26:08.93#ibcon#wrote, iclass 4, count 2 2006.169.08:26:08.93#ibcon#about to read 3, iclass 4, count 2 2006.169.08:26:08.95#ibcon#read 3, iclass 4, count 2 2006.169.08:26:08.95#ibcon#about to read 4, iclass 4, count 2 2006.169.08:26:08.95#ibcon#read 4, iclass 4, count 2 2006.169.08:26:08.95#ibcon#about to read 5, iclass 4, count 2 2006.169.08:26:08.95#ibcon#read 5, iclass 4, count 2 2006.169.08:26:08.95#ibcon#about to read 6, iclass 4, count 2 2006.169.08:26:08.95#ibcon#read 6, iclass 4, count 2 2006.169.08:26:08.95#ibcon#end of sib2, iclass 4, count 2 2006.169.08:26:08.95#ibcon#*mode == 0, iclass 4, count 2 2006.169.08:26:08.95#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.169.08:26:08.95#ibcon#[27=AT05-04\r\n] 2006.169.08:26:08.95#ibcon#*before write, iclass 4, count 2 2006.169.08:26:08.95#ibcon#enter sib2, iclass 4, count 2 2006.169.08:26:08.95#ibcon#flushed, iclass 4, count 2 2006.169.08:26:08.95#ibcon#about to write, iclass 4, count 2 2006.169.08:26:08.95#ibcon#wrote, iclass 4, count 2 2006.169.08:26:08.95#ibcon#about to read 3, iclass 4, count 2 2006.169.08:26:08.98#ibcon#read 3, iclass 4, count 2 2006.169.08:26:08.98#ibcon#about to read 4, iclass 4, count 2 2006.169.08:26:08.98#ibcon#read 4, iclass 4, count 2 2006.169.08:26:08.98#ibcon#about to read 5, iclass 4, count 2 2006.169.08:26:08.98#ibcon#read 5, iclass 4, count 2 2006.169.08:26:08.98#ibcon#about to read 6, iclass 4, count 2 2006.169.08:26:08.98#ibcon#read 6, iclass 4, count 2 2006.169.08:26:08.98#ibcon#end of sib2, iclass 4, count 2 2006.169.08:26:08.98#ibcon#*after write, iclass 4, count 2 2006.169.08:26:08.98#ibcon#*before return 0, iclass 4, count 2 2006.169.08:26:08.98#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:26:08.98#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.169.08:26:08.98#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.169.08:26:08.98#ibcon#ireg 7 cls_cnt 0 2006.169.08:26:08.98#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:26:09.10#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:26:09.10#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:26:09.10#ibcon#enter wrdev, iclass 4, count 0 2006.169.08:26:09.10#ibcon#first serial, iclass 4, count 0 2006.169.08:26:09.10#ibcon#enter sib2, iclass 4, count 0 2006.169.08:26:09.10#ibcon#flushed, iclass 4, count 0 2006.169.08:26:09.10#ibcon#about to write, iclass 4, count 0 2006.169.08:26:09.10#ibcon#wrote, iclass 4, count 0 2006.169.08:26:09.10#ibcon#about to read 3, iclass 4, count 0 2006.169.08:26:09.12#ibcon#read 3, iclass 4, count 0 2006.169.08:26:09.12#ibcon#about to read 4, iclass 4, count 0 2006.169.08:26:09.12#ibcon#read 4, iclass 4, count 0 2006.169.08:26:09.12#ibcon#about to read 5, iclass 4, count 0 2006.169.08:26:09.12#ibcon#read 5, iclass 4, count 0 2006.169.08:26:09.12#ibcon#about to read 6, iclass 4, count 0 2006.169.08:26:09.12#ibcon#read 6, iclass 4, count 0 2006.169.08:26:09.12#ibcon#end of sib2, iclass 4, count 0 2006.169.08:26:09.12#ibcon#*mode == 0, iclass 4, count 0 2006.169.08:26:09.12#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.169.08:26:09.12#ibcon#[27=USB\r\n] 2006.169.08:26:09.12#ibcon#*before write, iclass 4, count 0 2006.169.08:26:09.12#ibcon#enter sib2, iclass 4, count 0 2006.169.08:26:09.12#ibcon#flushed, iclass 4, count 0 2006.169.08:26:09.12#ibcon#about to write, iclass 4, count 0 2006.169.08:26:09.12#ibcon#wrote, iclass 4, count 0 2006.169.08:26:09.12#ibcon#about to read 3, iclass 4, count 0 2006.169.08:26:09.15#ibcon#read 3, iclass 4, count 0 2006.169.08:26:09.15#ibcon#about to read 4, iclass 4, count 0 2006.169.08:26:09.15#ibcon#read 4, iclass 4, count 0 2006.169.08:26:09.15#ibcon#about to read 5, iclass 4, count 0 2006.169.08:26:09.15#ibcon#read 5, iclass 4, count 0 2006.169.08:26:09.15#ibcon#about to read 6, iclass 4, count 0 2006.169.08:26:09.15#ibcon#read 6, iclass 4, count 0 2006.169.08:26:09.15#ibcon#end of sib2, iclass 4, count 0 2006.169.08:26:09.15#ibcon#*after write, iclass 4, count 0 2006.169.08:26:09.15#ibcon#*before return 0, iclass 4, count 0 2006.169.08:26:09.15#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:26:09.15#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.169.08:26:09.15#ibcon#about to clear, iclass 4 cls_cnt 0 2006.169.08:26:09.15#ibcon#cleared, iclass 4 cls_cnt 0 2006.169.08:26:09.15$vc4f8/vblo=6,752.99 2006.169.08:26:09.15#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.169.08:26:09.15#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.169.08:26:09.15#ibcon#ireg 17 cls_cnt 0 2006.169.08:26:09.15#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:26:09.15#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:26:09.15#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:26:09.15#ibcon#enter wrdev, iclass 6, count 0 2006.169.08:26:09.15#ibcon#first serial, iclass 6, count 0 2006.169.08:26:09.15#ibcon#enter sib2, iclass 6, count 0 2006.169.08:26:09.15#ibcon#flushed, iclass 6, count 0 2006.169.08:26:09.15#ibcon#about to write, iclass 6, count 0 2006.169.08:26:09.15#ibcon#wrote, iclass 6, count 0 2006.169.08:26:09.15#ibcon#about to read 3, iclass 6, count 0 2006.169.08:26:09.17#ibcon#read 3, iclass 6, count 0 2006.169.08:26:09.17#ibcon#about to read 4, iclass 6, count 0 2006.169.08:26:09.17#ibcon#read 4, iclass 6, count 0 2006.169.08:26:09.17#ibcon#about to read 5, iclass 6, count 0 2006.169.08:26:09.17#ibcon#read 5, iclass 6, count 0 2006.169.08:26:09.17#ibcon#about to read 6, iclass 6, count 0 2006.169.08:26:09.17#ibcon#read 6, iclass 6, count 0 2006.169.08:26:09.17#ibcon#end of sib2, iclass 6, count 0 2006.169.08:26:09.17#ibcon#*mode == 0, iclass 6, count 0 2006.169.08:26:09.17#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.169.08:26:09.17#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.08:26:09.17#ibcon#*before write, iclass 6, count 0 2006.169.08:26:09.17#ibcon#enter sib2, iclass 6, count 0 2006.169.08:26:09.17#ibcon#flushed, iclass 6, count 0 2006.169.08:26:09.17#ibcon#about to write, iclass 6, count 0 2006.169.08:26:09.17#ibcon#wrote, iclass 6, count 0 2006.169.08:26:09.17#ibcon#about to read 3, iclass 6, count 0 2006.169.08:26:09.21#ibcon#read 3, iclass 6, count 0 2006.169.08:26:09.21#ibcon#about to read 4, iclass 6, count 0 2006.169.08:26:09.21#ibcon#read 4, iclass 6, count 0 2006.169.08:26:09.21#ibcon#about to read 5, iclass 6, count 0 2006.169.08:26:09.21#ibcon#read 5, iclass 6, count 0 2006.169.08:26:09.21#ibcon#about to read 6, iclass 6, count 0 2006.169.08:26:09.21#ibcon#read 6, iclass 6, count 0 2006.169.08:26:09.21#ibcon#end of sib2, iclass 6, count 0 2006.169.08:26:09.21#ibcon#*after write, iclass 6, count 0 2006.169.08:26:09.21#ibcon#*before return 0, iclass 6, count 0 2006.169.08:26:09.21#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:26:09.21#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:26:09.21#ibcon#about to clear, iclass 6 cls_cnt 0 2006.169.08:26:09.21#ibcon#cleared, iclass 6 cls_cnt 0 2006.169.08:26:09.21$vc4f8/vb=6,4 2006.169.08:26:09.21#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.169.08:26:09.21#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.169.08:26:09.21#ibcon#ireg 11 cls_cnt 2 2006.169.08:26:09.21#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:26:09.27#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:26:09.27#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:26:09.27#ibcon#enter wrdev, iclass 10, count 2 2006.169.08:26:09.27#ibcon#first serial, iclass 10, count 2 2006.169.08:26:09.27#ibcon#enter sib2, iclass 10, count 2 2006.169.08:26:09.27#ibcon#flushed, iclass 10, count 2 2006.169.08:26:09.27#ibcon#about to write, iclass 10, count 2 2006.169.08:26:09.27#ibcon#wrote, iclass 10, count 2 2006.169.08:26:09.27#ibcon#about to read 3, iclass 10, count 2 2006.169.08:26:09.29#ibcon#read 3, iclass 10, count 2 2006.169.08:26:09.29#ibcon#about to read 4, iclass 10, count 2 2006.169.08:26:09.29#ibcon#read 4, iclass 10, count 2 2006.169.08:26:09.29#ibcon#about to read 5, iclass 10, count 2 2006.169.08:26:09.29#ibcon#read 5, iclass 10, count 2 2006.169.08:26:09.29#ibcon#about to read 6, iclass 10, count 2 2006.169.08:26:09.29#ibcon#read 6, iclass 10, count 2 2006.169.08:26:09.29#ibcon#end of sib2, iclass 10, count 2 2006.169.08:26:09.29#ibcon#*mode == 0, iclass 10, count 2 2006.169.08:26:09.29#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.169.08:26:09.29#ibcon#[27=AT06-04\r\n] 2006.169.08:26:09.29#ibcon#*before write, iclass 10, count 2 2006.169.08:26:09.29#ibcon#enter sib2, iclass 10, count 2 2006.169.08:26:09.29#ibcon#flushed, iclass 10, count 2 2006.169.08:26:09.29#ibcon#about to write, iclass 10, count 2 2006.169.08:26:09.29#ibcon#wrote, iclass 10, count 2 2006.169.08:26:09.29#ibcon#about to read 3, iclass 10, count 2 2006.169.08:26:09.32#ibcon#read 3, iclass 10, count 2 2006.169.08:26:09.32#ibcon#about to read 4, iclass 10, count 2 2006.169.08:26:09.32#ibcon#read 4, iclass 10, count 2 2006.169.08:26:09.32#ibcon#about to read 5, iclass 10, count 2 2006.169.08:26:09.32#ibcon#read 5, iclass 10, count 2 2006.169.08:26:09.32#ibcon#about to read 6, iclass 10, count 2 2006.169.08:26:09.32#ibcon#read 6, iclass 10, count 2 2006.169.08:26:09.32#ibcon#end of sib2, iclass 10, count 2 2006.169.08:26:09.32#ibcon#*after write, iclass 10, count 2 2006.169.08:26:09.32#ibcon#*before return 0, iclass 10, count 2 2006.169.08:26:09.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:26:09.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.169.08:26:09.32#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.169.08:26:09.32#ibcon#ireg 7 cls_cnt 0 2006.169.08:26:09.32#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:26:09.44#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:26:09.44#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:26:09.44#ibcon#enter wrdev, iclass 10, count 0 2006.169.08:26:09.44#ibcon#first serial, iclass 10, count 0 2006.169.08:26:09.44#ibcon#enter sib2, iclass 10, count 0 2006.169.08:26:09.44#ibcon#flushed, iclass 10, count 0 2006.169.08:26:09.44#ibcon#about to write, iclass 10, count 0 2006.169.08:26:09.44#ibcon#wrote, iclass 10, count 0 2006.169.08:26:09.44#ibcon#about to read 3, iclass 10, count 0 2006.169.08:26:09.46#ibcon#read 3, iclass 10, count 0 2006.169.08:26:09.46#ibcon#about to read 4, iclass 10, count 0 2006.169.08:26:09.46#ibcon#read 4, iclass 10, count 0 2006.169.08:26:09.46#ibcon#about to read 5, iclass 10, count 0 2006.169.08:26:09.46#ibcon#read 5, iclass 10, count 0 2006.169.08:26:09.46#ibcon#about to read 6, iclass 10, count 0 2006.169.08:26:09.46#ibcon#read 6, iclass 10, count 0 2006.169.08:26:09.46#ibcon#end of sib2, iclass 10, count 0 2006.169.08:26:09.46#ibcon#*mode == 0, iclass 10, count 0 2006.169.08:26:09.46#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.169.08:26:09.46#ibcon#[27=USB\r\n] 2006.169.08:26:09.46#ibcon#*before write, iclass 10, count 0 2006.169.08:26:09.46#ibcon#enter sib2, iclass 10, count 0 2006.169.08:26:09.46#ibcon#flushed, iclass 10, count 0 2006.169.08:26:09.46#ibcon#about to write, iclass 10, count 0 2006.169.08:26:09.46#ibcon#wrote, iclass 10, count 0 2006.169.08:26:09.46#ibcon#about to read 3, iclass 10, count 0 2006.169.08:26:09.49#ibcon#read 3, iclass 10, count 0 2006.169.08:26:09.49#ibcon#about to read 4, iclass 10, count 0 2006.169.08:26:09.49#ibcon#read 4, iclass 10, count 0 2006.169.08:26:09.49#ibcon#about to read 5, iclass 10, count 0 2006.169.08:26:09.49#ibcon#read 5, iclass 10, count 0 2006.169.08:26:09.49#ibcon#about to read 6, iclass 10, count 0 2006.169.08:26:09.49#ibcon#read 6, iclass 10, count 0 2006.169.08:26:09.49#ibcon#end of sib2, iclass 10, count 0 2006.169.08:26:09.49#ibcon#*after write, iclass 10, count 0 2006.169.08:26:09.49#ibcon#*before return 0, iclass 10, count 0 2006.169.08:26:09.49#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:26:09.49#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.169.08:26:09.49#ibcon#about to clear, iclass 10 cls_cnt 0 2006.169.08:26:09.49#ibcon#cleared, iclass 10 cls_cnt 0 2006.169.08:26:09.49$vc4f8/vabw=wide 2006.169.08:26:09.49#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.169.08:26:09.49#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.169.08:26:09.49#ibcon#ireg 8 cls_cnt 0 2006.169.08:26:09.49#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:26:09.49#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:26:09.49#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:26:09.49#ibcon#enter wrdev, iclass 12, count 0 2006.169.08:26:09.49#ibcon#first serial, iclass 12, count 0 2006.169.08:26:09.49#ibcon#enter sib2, iclass 12, count 0 2006.169.08:26:09.49#ibcon#flushed, iclass 12, count 0 2006.169.08:26:09.49#ibcon#about to write, iclass 12, count 0 2006.169.08:26:09.49#ibcon#wrote, iclass 12, count 0 2006.169.08:26:09.49#ibcon#about to read 3, iclass 12, count 0 2006.169.08:26:09.51#ibcon#read 3, iclass 12, count 0 2006.169.08:26:09.51#ibcon#about to read 4, iclass 12, count 0 2006.169.08:26:09.51#ibcon#read 4, iclass 12, count 0 2006.169.08:26:09.51#ibcon#about to read 5, iclass 12, count 0 2006.169.08:26:09.51#ibcon#read 5, iclass 12, count 0 2006.169.08:26:09.51#ibcon#about to read 6, iclass 12, count 0 2006.169.08:26:09.51#ibcon#read 6, iclass 12, count 0 2006.169.08:26:09.51#ibcon#end of sib2, iclass 12, count 0 2006.169.08:26:09.51#ibcon#*mode == 0, iclass 12, count 0 2006.169.08:26:09.51#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.169.08:26:09.51#ibcon#[25=BW32\r\n] 2006.169.08:26:09.51#ibcon#*before write, iclass 12, count 0 2006.169.08:26:09.51#ibcon#enter sib2, iclass 12, count 0 2006.169.08:26:09.51#ibcon#flushed, iclass 12, count 0 2006.169.08:26:09.51#ibcon#about to write, iclass 12, count 0 2006.169.08:26:09.51#ibcon#wrote, iclass 12, count 0 2006.169.08:26:09.51#ibcon#about to read 3, iclass 12, count 0 2006.169.08:26:09.54#ibcon#read 3, iclass 12, count 0 2006.169.08:26:09.54#ibcon#about to read 4, iclass 12, count 0 2006.169.08:26:09.54#ibcon#read 4, iclass 12, count 0 2006.169.08:26:09.54#ibcon#about to read 5, iclass 12, count 0 2006.169.08:26:09.54#ibcon#read 5, iclass 12, count 0 2006.169.08:26:09.54#ibcon#about to read 6, iclass 12, count 0 2006.169.08:26:09.54#ibcon#read 6, iclass 12, count 0 2006.169.08:26:09.54#ibcon#end of sib2, iclass 12, count 0 2006.169.08:26:09.54#ibcon#*after write, iclass 12, count 0 2006.169.08:26:09.54#ibcon#*before return 0, iclass 12, count 0 2006.169.08:26:09.54#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:26:09.54#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.169.08:26:09.54#ibcon#about to clear, iclass 12 cls_cnt 0 2006.169.08:26:09.54#ibcon#cleared, iclass 12 cls_cnt 0 2006.169.08:26:09.54$vc4f8/vbbw=wide 2006.169.08:26:09.54#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.169.08:26:09.54#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.169.08:26:09.54#ibcon#ireg 8 cls_cnt 0 2006.169.08:26:09.54#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:26:09.61#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:26:09.61#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:26:09.61#ibcon#enter wrdev, iclass 14, count 0 2006.169.08:26:09.61#ibcon#first serial, iclass 14, count 0 2006.169.08:26:09.61#ibcon#enter sib2, iclass 14, count 0 2006.169.08:26:09.61#ibcon#flushed, iclass 14, count 0 2006.169.08:26:09.61#ibcon#about to write, iclass 14, count 0 2006.169.08:26:09.61#ibcon#wrote, iclass 14, count 0 2006.169.08:26:09.61#ibcon#about to read 3, iclass 14, count 0 2006.169.08:26:09.63#ibcon#read 3, iclass 14, count 0 2006.169.08:26:09.63#ibcon#about to read 4, iclass 14, count 0 2006.169.08:26:09.63#ibcon#read 4, iclass 14, count 0 2006.169.08:26:09.63#ibcon#about to read 5, iclass 14, count 0 2006.169.08:26:09.63#ibcon#read 5, iclass 14, count 0 2006.169.08:26:09.63#ibcon#about to read 6, iclass 14, count 0 2006.169.08:26:09.63#ibcon#read 6, iclass 14, count 0 2006.169.08:26:09.63#ibcon#end of sib2, iclass 14, count 0 2006.169.08:26:09.63#ibcon#*mode == 0, iclass 14, count 0 2006.169.08:26:09.63#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.169.08:26:09.63#ibcon#[27=BW32\r\n] 2006.169.08:26:09.63#ibcon#*before write, iclass 14, count 0 2006.169.08:26:09.63#ibcon#enter sib2, iclass 14, count 0 2006.169.08:26:09.63#ibcon#flushed, iclass 14, count 0 2006.169.08:26:09.63#ibcon#about to write, iclass 14, count 0 2006.169.08:26:09.63#ibcon#wrote, iclass 14, count 0 2006.169.08:26:09.63#ibcon#about to read 3, iclass 14, count 0 2006.169.08:26:09.66#ibcon#read 3, iclass 14, count 0 2006.169.08:26:09.66#ibcon#about to read 4, iclass 14, count 0 2006.169.08:26:09.66#ibcon#read 4, iclass 14, count 0 2006.169.08:26:09.66#ibcon#about to read 5, iclass 14, count 0 2006.169.08:26:09.66#ibcon#read 5, iclass 14, count 0 2006.169.08:26:09.66#ibcon#about to read 6, iclass 14, count 0 2006.169.08:26:09.66#ibcon#read 6, iclass 14, count 0 2006.169.08:26:09.66#ibcon#end of sib2, iclass 14, count 0 2006.169.08:26:09.66#ibcon#*after write, iclass 14, count 0 2006.169.08:26:09.66#ibcon#*before return 0, iclass 14, count 0 2006.169.08:26:09.66#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:26:09.66#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:26:09.66#ibcon#about to clear, iclass 14 cls_cnt 0 2006.169.08:26:09.66#ibcon#cleared, iclass 14 cls_cnt 0 2006.169.08:26:09.66$4f8m12a/ifd4f 2006.169.08:26:09.66$ifd4f/lo= 2006.169.08:26:09.66$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.08:26:09.66$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.08:26:09.66$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.08:26:09.66$ifd4f/patch= 2006.169.08:26:09.66$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.08:26:09.66$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.08:26:09.66$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.08:26:09.66$4f8m12a/"form=m,16.000,1:2 2006.169.08:26:09.66$4f8m12a/"tpicd 2006.169.08:26:09.66$4f8m12a/echo=off 2006.169.08:26:09.66$4f8m12a/xlog=off 2006.169.08:26:09.66:!2006.169.08:26:30 2006.169.08:26:14.14#trakl#Source acquired 2006.169.08:26:16.14#flagr#flagr/antenna,acquired 2006.169.08:26:30.00:preob 2006.169.08:26:30.14/onsource/TRACKING 2006.169.08:26:30.14:!2006.169.08:26:40 2006.169.08:26:40.00:data_valid=on 2006.169.08:26:40.00:midob 2006.169.08:26:40.14/onsource/TRACKING 2006.169.08:26:40.14/wx/18.10,1003.8,100 2006.169.08:26:40.23/cable/+6.5283E-03 2006.169.08:26:41.31/va/01,08,usb,yes,41,43 2006.169.08:26:41.31/va/02,07,usb,yes,42,43 2006.169.08:26:41.31/va/03,06,usb,yes,44,44 2006.169.08:26:41.31/va/04,07,usb,yes,43,46 2006.169.08:26:41.31/va/05,07,usb,yes,47,50 2006.169.08:26:41.31/va/06,06,usb,yes,47,46 2006.169.08:26:41.31/va/07,06,usb,yes,47,47 2006.169.08:26:41.31/va/08,07,usb,yes,45,44 2006.169.08:26:41.54/valo/01,532.99,yes,locked 2006.169.08:26:41.54/valo/02,572.99,yes,locked 2006.169.08:26:41.54/valo/03,672.99,yes,locked 2006.169.08:26:41.54/valo/04,832.99,yes,locked 2006.169.08:26:41.54/valo/05,652.99,yes,locked 2006.169.08:26:41.54/valo/06,772.99,yes,locked 2006.169.08:26:41.54/valo/07,832.99,yes,locked 2006.169.08:26:41.54/valo/08,852.99,yes,locked 2006.169.08:26:42.63/vb/01,04,usb,yes,30,29 2006.169.08:26:42.63/vb/02,04,usb,yes,32,33 2006.169.08:26:42.63/vb/03,04,usb,yes,28,32 2006.169.08:26:42.63/vb/04,04,usb,yes,29,29 2006.169.08:26:42.63/vb/05,04,usb,yes,28,32 2006.169.08:26:42.63/vb/06,04,usb,yes,29,31 2006.169.08:26:42.63/vb/07,04,usb,yes,31,31 2006.169.08:26:42.63/vb/08,04,usb,yes,28,32 2006.169.08:26:42.87/vblo/01,632.99,yes,locked 2006.169.08:26:42.87/vblo/02,640.99,yes,locked 2006.169.08:26:42.87/vblo/03,656.99,yes,locked 2006.169.08:26:42.87/vblo/04,712.99,yes,locked 2006.169.08:26:42.87/vblo/05,744.99,yes,locked 2006.169.08:26:42.87/vblo/06,752.99,yes,locked 2006.169.08:26:42.87/vblo/07,734.99,yes,locked 2006.169.08:26:42.87/vblo/08,744.99,yes,locked 2006.169.08:26:43.02/vabw/8 2006.169.08:26:43.17/vbbw/8 2006.169.08:26:43.26/xfe/off,on,15.0 2006.169.08:26:43.63/ifatt/23,28,28,28 2006.169.08:26:44.07/fmout-gps/S +4.17E-07 2006.169.08:26:44.15:!2006.169.08:27:40 2006.169.08:27:40.01:data_valid=off 2006.169.08:27:40.02:postob 2006.169.08:27:40.15/cable/+6.5292E-03 2006.169.08:27:40.16/wx/18.10,1003.9,100 2006.169.08:27:41.07/fmout-gps/S +4.17E-07 2006.169.08:27:41.08:scan_name=169-0828,k06169,60 2006.169.08:27:41.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.169.08:27:41.13#flagr#flagr/antenna,new-source 2006.169.08:27:42.13:checkk5 2006.169.08:27:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.169.08:27:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.169.08:27:46.91/chk_autoobs//k5ts3?ERROR: timeout happened! 2006.169.08:27:47.29/chk_autoobs//k5ts4/ autoobs is running! 2006.169.08:27:47.66/chk_obsdata//k5ts1/T1690826??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.08:27:48.03/chk_obsdata//k5ts2/T1690826??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.08:27:55.05/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.08:27:55.42/chk_obsdata//k5ts4/T1690826??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.08:27:56.11/k5log//k5ts1_log_newline 2006.169.08:27:56.80/k5log//k5ts2_log_newline 2006.169.08:28:00.13#trakl#Source acquired 2006.169.08:28:02.13#flagr#flagr/antenna,acquired 2006.169.08:28:03.89/k5log//k5ts3?ERROR: timeout happened! 2006.169.08:28:04.58/k5log//k5ts4_log_newline 2006.169.08:28:04.75/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.08:28:04.75:4f8m12a=3 2006.169.08:28:04.75$4f8m12a/echo=on 2006.169.08:28:04.75$4f8m12a/pcalon 2006.169.08:28:04.75$pcalon/"no phase cal control is implemented here 2006.169.08:28:04.75$4f8m12a/"tpicd=stop 2006.169.08:28:04.75$4f8m12a/vc4f8 2006.169.08:28:04.75$vc4f8/valo=1,532.99 2006.169.08:28:04.75#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.169.08:28:04.75#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.169.08:28:04.75#ibcon#ireg 17 cls_cnt 0 2006.169.08:28:04.75#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.169.08:28:04.75#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.169.08:28:04.75#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.169.08:28:04.75#ibcon#enter wrdev, iclass 25, count 0 2006.169.08:28:04.75#ibcon#first serial, iclass 25, count 0 2006.169.08:28:04.75#ibcon#enter sib2, iclass 25, count 0 2006.169.08:28:04.75#ibcon#flushed, iclass 25, count 0 2006.169.08:28:04.75#ibcon#about to write, iclass 25, count 0 2006.169.08:28:04.75#ibcon#wrote, iclass 25, count 0 2006.169.08:28:04.75#ibcon#about to read 3, iclass 25, count 0 2006.169.08:28:04.76#ibcon#read 3, iclass 25, count 0 2006.169.08:28:04.76#ibcon#about to read 4, iclass 25, count 0 2006.169.08:28:04.76#ibcon#read 4, iclass 25, count 0 2006.169.08:28:04.76#ibcon#about to read 5, iclass 25, count 0 2006.169.08:28:04.76#ibcon#read 5, iclass 25, count 0 2006.169.08:28:04.76#ibcon#about to read 6, iclass 25, count 0 2006.169.08:28:04.76#ibcon#read 6, iclass 25, count 0 2006.169.08:28:04.76#ibcon#end of sib2, iclass 25, count 0 2006.169.08:28:04.76#ibcon#*mode == 0, iclass 25, count 0 2006.169.08:28:04.76#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.169.08:28:04.76#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.08:28:04.76#ibcon#*before write, iclass 25, count 0 2006.169.08:28:04.76#ibcon#enter sib2, iclass 25, count 0 2006.169.08:28:04.76#ibcon#flushed, iclass 25, count 0 2006.169.08:28:04.76#ibcon#about to write, iclass 25, count 0 2006.169.08:28:04.76#ibcon#wrote, iclass 25, count 0 2006.169.08:28:04.76#ibcon#about to read 3, iclass 25, count 0 2006.169.08:28:04.81#ibcon#read 3, iclass 25, count 0 2006.169.08:28:04.81#ibcon#about to read 4, iclass 25, count 0 2006.169.08:28:04.81#ibcon#read 4, iclass 25, count 0 2006.169.08:28:04.81#ibcon#about to read 5, iclass 25, count 0 2006.169.08:28:04.81#ibcon#read 5, iclass 25, count 0 2006.169.08:28:04.81#ibcon#about to read 6, iclass 25, count 0 2006.169.08:28:04.81#ibcon#read 6, iclass 25, count 0 2006.169.08:28:04.81#ibcon#end of sib2, iclass 25, count 0 2006.169.08:28:04.81#ibcon#*after write, iclass 25, count 0 2006.169.08:28:04.81#ibcon#*before return 0, iclass 25, count 0 2006.169.08:28:04.81#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.169.08:28:04.81#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.169.08:28:04.81#ibcon#about to clear, iclass 25 cls_cnt 0 2006.169.08:28:04.81#ibcon#cleared, iclass 25 cls_cnt 0 2006.169.08:28:04.81$vc4f8/va=1,8 2006.169.08:28:04.81#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.169.08:28:04.81#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.169.08:28:04.81#ibcon#ireg 11 cls_cnt 2 2006.169.08:28:04.81#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.169.08:28:04.81#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.169.08:28:04.81#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.169.08:28:04.81#ibcon#enter wrdev, iclass 27, count 2 2006.169.08:28:04.81#ibcon#first serial, iclass 27, count 2 2006.169.08:28:04.81#ibcon#enter sib2, iclass 27, count 2 2006.169.08:28:04.81#ibcon#flushed, iclass 27, count 2 2006.169.08:28:04.81#ibcon#about to write, iclass 27, count 2 2006.169.08:28:04.81#ibcon#wrote, iclass 27, count 2 2006.169.08:28:04.81#ibcon#about to read 3, iclass 27, count 2 2006.169.08:28:04.83#ibcon#read 3, iclass 27, count 2 2006.169.08:28:04.83#ibcon#about to read 4, iclass 27, count 2 2006.169.08:28:04.83#ibcon#read 4, iclass 27, count 2 2006.169.08:28:04.83#ibcon#about to read 5, iclass 27, count 2 2006.169.08:28:04.83#ibcon#read 5, iclass 27, count 2 2006.169.08:28:04.83#ibcon#about to read 6, iclass 27, count 2 2006.169.08:28:04.83#ibcon#read 6, iclass 27, count 2 2006.169.08:28:04.83#ibcon#end of sib2, iclass 27, count 2 2006.169.08:28:04.83#ibcon#*mode == 0, iclass 27, count 2 2006.169.08:28:04.83#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.169.08:28:04.83#ibcon#[25=AT01-08\r\n] 2006.169.08:28:04.83#ibcon#*before write, iclass 27, count 2 2006.169.08:28:04.83#ibcon#enter sib2, iclass 27, count 2 2006.169.08:28:04.83#ibcon#flushed, iclass 27, count 2 2006.169.08:28:04.83#ibcon#about to write, iclass 27, count 2 2006.169.08:28:04.83#ibcon#wrote, iclass 27, count 2 2006.169.08:28:04.83#ibcon#about to read 3, iclass 27, count 2 2006.169.08:28:04.86#ibcon#read 3, iclass 27, count 2 2006.169.08:28:04.86#ibcon#about to read 4, iclass 27, count 2 2006.169.08:28:04.86#ibcon#read 4, iclass 27, count 2 2006.169.08:28:04.86#ibcon#about to read 5, iclass 27, count 2 2006.169.08:28:04.86#ibcon#read 5, iclass 27, count 2 2006.169.08:28:04.86#ibcon#about to read 6, iclass 27, count 2 2006.169.08:28:04.86#ibcon#read 6, iclass 27, count 2 2006.169.08:28:04.86#ibcon#end of sib2, iclass 27, count 2 2006.169.08:28:04.86#ibcon#*after write, iclass 27, count 2 2006.169.08:28:04.86#ibcon#*before return 0, iclass 27, count 2 2006.169.08:28:04.86#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.169.08:28:04.86#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.169.08:28:04.86#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.169.08:28:04.86#ibcon#ireg 7 cls_cnt 0 2006.169.08:28:04.86#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.169.08:28:04.98#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.169.08:28:04.98#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.169.08:28:04.98#ibcon#enter wrdev, iclass 27, count 0 2006.169.08:28:04.98#ibcon#first serial, iclass 27, count 0 2006.169.08:28:04.98#ibcon#enter sib2, iclass 27, count 0 2006.169.08:28:04.98#ibcon#flushed, iclass 27, count 0 2006.169.08:28:04.98#ibcon#about to write, iclass 27, count 0 2006.169.08:28:04.98#ibcon#wrote, iclass 27, count 0 2006.169.08:28:04.98#ibcon#about to read 3, iclass 27, count 0 2006.169.08:28:05.00#ibcon#read 3, iclass 27, count 0 2006.169.08:28:05.00#ibcon#about to read 4, iclass 27, count 0 2006.169.08:28:05.00#ibcon#read 4, iclass 27, count 0 2006.169.08:28:05.00#ibcon#about to read 5, iclass 27, count 0 2006.169.08:28:05.00#ibcon#read 5, iclass 27, count 0 2006.169.08:28:05.00#ibcon#about to read 6, iclass 27, count 0 2006.169.08:28:05.00#ibcon#read 6, iclass 27, count 0 2006.169.08:28:05.00#ibcon#end of sib2, iclass 27, count 0 2006.169.08:28:05.00#ibcon#*mode == 0, iclass 27, count 0 2006.169.08:28:05.00#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.169.08:28:05.00#ibcon#[25=USB\r\n] 2006.169.08:28:05.00#ibcon#*before write, iclass 27, count 0 2006.169.08:28:05.00#ibcon#enter sib2, iclass 27, count 0 2006.169.08:28:05.00#ibcon#flushed, iclass 27, count 0 2006.169.08:28:05.00#ibcon#about to write, iclass 27, count 0 2006.169.08:28:05.00#ibcon#wrote, iclass 27, count 0 2006.169.08:28:05.00#ibcon#about to read 3, iclass 27, count 0 2006.169.08:28:05.03#ibcon#read 3, iclass 27, count 0 2006.169.08:28:05.03#ibcon#about to read 4, iclass 27, count 0 2006.169.08:28:05.03#ibcon#read 4, iclass 27, count 0 2006.169.08:28:05.03#ibcon#about to read 5, iclass 27, count 0 2006.169.08:28:05.03#ibcon#read 5, iclass 27, count 0 2006.169.08:28:05.03#ibcon#about to read 6, iclass 27, count 0 2006.169.08:28:05.03#ibcon#read 6, iclass 27, count 0 2006.169.08:28:05.03#ibcon#end of sib2, iclass 27, count 0 2006.169.08:28:05.03#ibcon#*after write, iclass 27, count 0 2006.169.08:28:05.03#ibcon#*before return 0, iclass 27, count 0 2006.169.08:28:05.03#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.169.08:28:05.03#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.169.08:28:05.03#ibcon#about to clear, iclass 27 cls_cnt 0 2006.169.08:28:05.03#ibcon#cleared, iclass 27 cls_cnt 0 2006.169.08:28:05.03$vc4f8/valo=2,572.99 2006.169.08:28:05.03#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.169.08:28:05.03#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.169.08:28:05.03#ibcon#ireg 17 cls_cnt 0 2006.169.08:28:05.03#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.169.08:28:05.03#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.169.08:28:05.03#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.169.08:28:05.03#ibcon#enter wrdev, iclass 29, count 0 2006.169.08:28:05.03#ibcon#first serial, iclass 29, count 0 2006.169.08:28:05.03#ibcon#enter sib2, iclass 29, count 0 2006.169.08:28:05.03#ibcon#flushed, iclass 29, count 0 2006.169.08:28:05.03#ibcon#about to write, iclass 29, count 0 2006.169.08:28:05.03#ibcon#wrote, iclass 29, count 0 2006.169.08:28:05.03#ibcon#about to read 3, iclass 29, count 0 2006.169.08:28:05.05#ibcon#read 3, iclass 29, count 0 2006.169.08:28:05.05#ibcon#about to read 4, iclass 29, count 0 2006.169.08:28:05.05#ibcon#read 4, iclass 29, count 0 2006.169.08:28:05.05#ibcon#about to read 5, iclass 29, count 0 2006.169.08:28:05.05#ibcon#read 5, iclass 29, count 0 2006.169.08:28:05.05#ibcon#about to read 6, iclass 29, count 0 2006.169.08:28:05.05#ibcon#read 6, iclass 29, count 0 2006.169.08:28:05.05#ibcon#end of sib2, iclass 29, count 0 2006.169.08:28:05.05#ibcon#*mode == 0, iclass 29, count 0 2006.169.08:28:05.05#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.169.08:28:05.05#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.08:28:05.05#ibcon#*before write, iclass 29, count 0 2006.169.08:28:05.05#ibcon#enter sib2, iclass 29, count 0 2006.169.08:28:05.05#ibcon#flushed, iclass 29, count 0 2006.169.08:28:05.05#ibcon#about to write, iclass 29, count 0 2006.169.08:28:05.05#ibcon#wrote, iclass 29, count 0 2006.169.08:28:05.05#ibcon#about to read 3, iclass 29, count 0 2006.169.08:28:05.09#ibcon#read 3, iclass 29, count 0 2006.169.08:28:05.09#ibcon#about to read 4, iclass 29, count 0 2006.169.08:28:05.09#ibcon#read 4, iclass 29, count 0 2006.169.08:28:05.09#ibcon#about to read 5, iclass 29, count 0 2006.169.08:28:05.09#ibcon#read 5, iclass 29, count 0 2006.169.08:28:05.09#ibcon#about to read 6, iclass 29, count 0 2006.169.08:28:05.09#ibcon#read 6, iclass 29, count 0 2006.169.08:28:05.09#ibcon#end of sib2, iclass 29, count 0 2006.169.08:28:05.09#ibcon#*after write, iclass 29, count 0 2006.169.08:28:05.09#ibcon#*before return 0, iclass 29, count 0 2006.169.08:28:05.09#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.169.08:28:05.09#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.169.08:28:05.09#ibcon#about to clear, iclass 29 cls_cnt 0 2006.169.08:28:05.09#ibcon#cleared, iclass 29 cls_cnt 0 2006.169.08:28:05.09$vc4f8/va=2,7 2006.169.08:28:05.09#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.169.08:28:05.09#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.169.08:28:05.09#ibcon#ireg 11 cls_cnt 2 2006.169.08:28:05.09#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.169.08:28:05.15#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.169.08:28:05.15#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.169.08:28:05.15#ibcon#enter wrdev, iclass 31, count 2 2006.169.08:28:05.15#ibcon#first serial, iclass 31, count 2 2006.169.08:28:05.15#ibcon#enter sib2, iclass 31, count 2 2006.169.08:28:05.15#ibcon#flushed, iclass 31, count 2 2006.169.08:28:05.15#ibcon#about to write, iclass 31, count 2 2006.169.08:28:05.15#ibcon#wrote, iclass 31, count 2 2006.169.08:28:05.15#ibcon#about to read 3, iclass 31, count 2 2006.169.08:28:05.17#ibcon#read 3, iclass 31, count 2 2006.169.08:28:05.17#ibcon#about to read 4, iclass 31, count 2 2006.169.08:28:05.17#ibcon#read 4, iclass 31, count 2 2006.169.08:28:05.17#ibcon#about to read 5, iclass 31, count 2 2006.169.08:28:05.17#ibcon#read 5, iclass 31, count 2 2006.169.08:28:05.17#ibcon#about to read 6, iclass 31, count 2 2006.169.08:28:05.17#ibcon#read 6, iclass 31, count 2 2006.169.08:28:05.17#ibcon#end of sib2, iclass 31, count 2 2006.169.08:28:05.17#ibcon#*mode == 0, iclass 31, count 2 2006.169.08:28:05.17#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.169.08:28:05.17#ibcon#[25=AT02-07\r\n] 2006.169.08:28:05.17#ibcon#*before write, iclass 31, count 2 2006.169.08:28:05.17#ibcon#enter sib2, iclass 31, count 2 2006.169.08:28:05.17#ibcon#flushed, iclass 31, count 2 2006.169.08:28:05.17#ibcon#about to write, iclass 31, count 2 2006.169.08:28:05.17#ibcon#wrote, iclass 31, count 2 2006.169.08:28:05.17#ibcon#about to read 3, iclass 31, count 2 2006.169.08:28:05.20#ibcon#read 3, iclass 31, count 2 2006.169.08:28:05.20#ibcon#about to read 4, iclass 31, count 2 2006.169.08:28:05.20#ibcon#read 4, iclass 31, count 2 2006.169.08:28:05.20#ibcon#about to read 5, iclass 31, count 2 2006.169.08:28:05.20#ibcon#read 5, iclass 31, count 2 2006.169.08:28:05.20#ibcon#about to read 6, iclass 31, count 2 2006.169.08:28:05.20#ibcon#read 6, iclass 31, count 2 2006.169.08:28:05.20#ibcon#end of sib2, iclass 31, count 2 2006.169.08:28:05.20#ibcon#*after write, iclass 31, count 2 2006.169.08:28:05.20#ibcon#*before return 0, iclass 31, count 2 2006.169.08:28:05.20#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.169.08:28:05.20#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.169.08:28:05.20#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.169.08:28:05.20#ibcon#ireg 7 cls_cnt 0 2006.169.08:28:05.20#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.169.08:28:05.32#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.169.08:28:05.32#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.169.08:28:05.32#ibcon#enter wrdev, iclass 31, count 0 2006.169.08:28:05.32#ibcon#first serial, iclass 31, count 0 2006.169.08:28:05.32#ibcon#enter sib2, iclass 31, count 0 2006.169.08:28:05.32#ibcon#flushed, iclass 31, count 0 2006.169.08:28:05.32#ibcon#about to write, iclass 31, count 0 2006.169.08:28:05.32#ibcon#wrote, iclass 31, count 0 2006.169.08:28:05.32#ibcon#about to read 3, iclass 31, count 0 2006.169.08:28:05.34#ibcon#read 3, iclass 31, count 0 2006.169.08:28:05.34#ibcon#about to read 4, iclass 31, count 0 2006.169.08:28:05.34#ibcon#read 4, iclass 31, count 0 2006.169.08:28:05.34#ibcon#about to read 5, iclass 31, count 0 2006.169.08:28:05.34#ibcon#read 5, iclass 31, count 0 2006.169.08:28:05.34#ibcon#about to read 6, iclass 31, count 0 2006.169.08:28:05.34#ibcon#read 6, iclass 31, count 0 2006.169.08:28:05.34#ibcon#end of sib2, iclass 31, count 0 2006.169.08:28:05.34#ibcon#*mode == 0, iclass 31, count 0 2006.169.08:28:05.34#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.169.08:28:05.34#ibcon#[25=USB\r\n] 2006.169.08:28:05.34#ibcon#*before write, iclass 31, count 0 2006.169.08:28:05.34#ibcon#enter sib2, iclass 31, count 0 2006.169.08:28:05.34#ibcon#flushed, iclass 31, count 0 2006.169.08:28:05.34#ibcon#about to write, iclass 31, count 0 2006.169.08:28:05.34#ibcon#wrote, iclass 31, count 0 2006.169.08:28:05.34#ibcon#about to read 3, iclass 31, count 0 2006.169.08:28:05.37#ibcon#read 3, iclass 31, count 0 2006.169.08:28:05.37#ibcon#about to read 4, iclass 31, count 0 2006.169.08:28:05.37#ibcon#read 4, iclass 31, count 0 2006.169.08:28:05.37#ibcon#about to read 5, iclass 31, count 0 2006.169.08:28:05.37#ibcon#read 5, iclass 31, count 0 2006.169.08:28:05.37#ibcon#about to read 6, iclass 31, count 0 2006.169.08:28:05.37#ibcon#read 6, iclass 31, count 0 2006.169.08:28:05.37#ibcon#end of sib2, iclass 31, count 0 2006.169.08:28:05.37#ibcon#*after write, iclass 31, count 0 2006.169.08:28:05.37#ibcon#*before return 0, iclass 31, count 0 2006.169.08:28:05.37#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.169.08:28:05.37#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.169.08:28:05.37#ibcon#about to clear, iclass 31 cls_cnt 0 2006.169.08:28:05.37#ibcon#cleared, iclass 31 cls_cnt 0 2006.169.08:28:05.37$vc4f8/valo=3,672.99 2006.169.08:28:05.37#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.169.08:28:05.37#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.169.08:28:05.37#ibcon#ireg 17 cls_cnt 0 2006.169.08:28:05.37#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:28:05.37#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:28:05.37#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:28:05.37#ibcon#enter wrdev, iclass 33, count 0 2006.169.08:28:05.37#ibcon#first serial, iclass 33, count 0 2006.169.08:28:05.37#ibcon#enter sib2, iclass 33, count 0 2006.169.08:28:05.37#ibcon#flushed, iclass 33, count 0 2006.169.08:28:05.37#ibcon#about to write, iclass 33, count 0 2006.169.08:28:05.37#ibcon#wrote, iclass 33, count 0 2006.169.08:28:05.37#ibcon#about to read 3, iclass 33, count 0 2006.169.08:28:05.40#ibcon#read 3, iclass 33, count 0 2006.169.08:28:05.40#ibcon#about to read 4, iclass 33, count 0 2006.169.08:28:05.40#ibcon#read 4, iclass 33, count 0 2006.169.08:28:05.40#ibcon#about to read 5, iclass 33, count 0 2006.169.08:28:05.40#ibcon#read 5, iclass 33, count 0 2006.169.08:28:05.40#ibcon#about to read 6, iclass 33, count 0 2006.169.08:28:05.40#ibcon#read 6, iclass 33, count 0 2006.169.08:28:05.40#ibcon#end of sib2, iclass 33, count 0 2006.169.08:28:05.40#ibcon#*mode == 0, iclass 33, count 0 2006.169.08:28:05.40#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.169.08:28:05.40#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.08:28:05.40#ibcon#*before write, iclass 33, count 0 2006.169.08:28:05.40#ibcon#enter sib2, iclass 33, count 0 2006.169.08:28:05.40#ibcon#flushed, iclass 33, count 0 2006.169.08:28:05.40#ibcon#about to write, iclass 33, count 0 2006.169.08:28:05.40#ibcon#wrote, iclass 33, count 0 2006.169.08:28:05.40#ibcon#about to read 3, iclass 33, count 0 2006.169.08:28:05.44#ibcon#read 3, iclass 33, count 0 2006.169.08:28:05.44#ibcon#about to read 4, iclass 33, count 0 2006.169.08:28:05.44#ibcon#read 4, iclass 33, count 0 2006.169.08:28:05.44#ibcon#about to read 5, iclass 33, count 0 2006.169.08:28:05.44#ibcon#read 5, iclass 33, count 0 2006.169.08:28:05.44#ibcon#about to read 6, iclass 33, count 0 2006.169.08:28:05.44#ibcon#read 6, iclass 33, count 0 2006.169.08:28:05.44#ibcon#end of sib2, iclass 33, count 0 2006.169.08:28:05.44#ibcon#*after write, iclass 33, count 0 2006.169.08:28:05.44#ibcon#*before return 0, iclass 33, count 0 2006.169.08:28:05.44#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:28:05.44#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:28:05.44#ibcon#about to clear, iclass 33 cls_cnt 0 2006.169.08:28:05.44#ibcon#cleared, iclass 33 cls_cnt 0 2006.169.08:28:05.44$vc4f8/va=3,6 2006.169.08:28:05.44#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.169.08:28:05.44#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.169.08:28:05.44#ibcon#ireg 11 cls_cnt 2 2006.169.08:28:05.44#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.169.08:28:05.49#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.169.08:28:05.49#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.169.08:28:05.49#ibcon#enter wrdev, iclass 35, count 2 2006.169.08:28:05.49#ibcon#first serial, iclass 35, count 2 2006.169.08:28:05.49#ibcon#enter sib2, iclass 35, count 2 2006.169.08:28:05.49#ibcon#flushed, iclass 35, count 2 2006.169.08:28:05.49#ibcon#about to write, iclass 35, count 2 2006.169.08:28:05.49#ibcon#wrote, iclass 35, count 2 2006.169.08:28:05.49#ibcon#about to read 3, iclass 35, count 2 2006.169.08:28:05.51#ibcon#read 3, iclass 35, count 2 2006.169.08:28:05.51#ibcon#about to read 4, iclass 35, count 2 2006.169.08:28:05.51#ibcon#read 4, iclass 35, count 2 2006.169.08:28:05.51#ibcon#about to read 5, iclass 35, count 2 2006.169.08:28:05.51#ibcon#read 5, iclass 35, count 2 2006.169.08:28:05.51#ibcon#about to read 6, iclass 35, count 2 2006.169.08:28:05.51#ibcon#read 6, iclass 35, count 2 2006.169.08:28:05.51#ibcon#end of sib2, iclass 35, count 2 2006.169.08:28:05.51#ibcon#*mode == 0, iclass 35, count 2 2006.169.08:28:05.51#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.169.08:28:05.51#ibcon#[25=AT03-06\r\n] 2006.169.08:28:05.51#ibcon#*before write, iclass 35, count 2 2006.169.08:28:05.51#ibcon#enter sib2, iclass 35, count 2 2006.169.08:28:05.51#ibcon#flushed, iclass 35, count 2 2006.169.08:28:05.51#ibcon#about to write, iclass 35, count 2 2006.169.08:28:05.51#ibcon#wrote, iclass 35, count 2 2006.169.08:28:05.51#ibcon#about to read 3, iclass 35, count 2 2006.169.08:28:05.54#ibcon#read 3, iclass 35, count 2 2006.169.08:28:05.54#ibcon#about to read 4, iclass 35, count 2 2006.169.08:28:05.54#ibcon#read 4, iclass 35, count 2 2006.169.08:28:05.54#ibcon#about to read 5, iclass 35, count 2 2006.169.08:28:05.54#ibcon#read 5, iclass 35, count 2 2006.169.08:28:05.54#ibcon#about to read 6, iclass 35, count 2 2006.169.08:28:05.54#ibcon#read 6, iclass 35, count 2 2006.169.08:28:05.54#ibcon#end of sib2, iclass 35, count 2 2006.169.08:28:05.54#ibcon#*after write, iclass 35, count 2 2006.169.08:28:05.54#ibcon#*before return 0, iclass 35, count 2 2006.169.08:28:05.54#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.169.08:28:05.54#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.169.08:28:05.54#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.169.08:28:05.54#ibcon#ireg 7 cls_cnt 0 2006.169.08:28:05.54#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.169.08:28:05.66#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.169.08:28:05.66#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.169.08:28:05.66#ibcon#enter wrdev, iclass 35, count 0 2006.169.08:28:05.66#ibcon#first serial, iclass 35, count 0 2006.169.08:28:05.66#ibcon#enter sib2, iclass 35, count 0 2006.169.08:28:05.66#ibcon#flushed, iclass 35, count 0 2006.169.08:28:05.66#ibcon#about to write, iclass 35, count 0 2006.169.08:28:05.66#ibcon#wrote, iclass 35, count 0 2006.169.08:28:05.66#ibcon#about to read 3, iclass 35, count 0 2006.169.08:28:05.68#ibcon#read 3, iclass 35, count 0 2006.169.08:28:05.68#ibcon#about to read 4, iclass 35, count 0 2006.169.08:28:05.68#ibcon#read 4, iclass 35, count 0 2006.169.08:28:05.68#ibcon#about to read 5, iclass 35, count 0 2006.169.08:28:05.68#ibcon#read 5, iclass 35, count 0 2006.169.08:28:05.68#ibcon#about to read 6, iclass 35, count 0 2006.169.08:28:05.68#ibcon#read 6, iclass 35, count 0 2006.169.08:28:05.68#ibcon#end of sib2, iclass 35, count 0 2006.169.08:28:05.68#ibcon#*mode == 0, iclass 35, count 0 2006.169.08:28:05.68#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.169.08:28:05.68#ibcon#[25=USB\r\n] 2006.169.08:28:05.68#ibcon#*before write, iclass 35, count 0 2006.169.08:28:05.68#ibcon#enter sib2, iclass 35, count 0 2006.169.08:28:05.68#ibcon#flushed, iclass 35, count 0 2006.169.08:28:05.68#ibcon#about to write, iclass 35, count 0 2006.169.08:28:05.68#ibcon#wrote, iclass 35, count 0 2006.169.08:28:05.68#ibcon#about to read 3, iclass 35, count 0 2006.169.08:28:05.71#ibcon#read 3, iclass 35, count 0 2006.169.08:28:05.71#ibcon#about to read 4, iclass 35, count 0 2006.169.08:28:05.71#ibcon#read 4, iclass 35, count 0 2006.169.08:28:05.71#ibcon#about to read 5, iclass 35, count 0 2006.169.08:28:05.71#ibcon#read 5, iclass 35, count 0 2006.169.08:28:05.71#ibcon#about to read 6, iclass 35, count 0 2006.169.08:28:05.71#ibcon#read 6, iclass 35, count 0 2006.169.08:28:05.71#ibcon#end of sib2, iclass 35, count 0 2006.169.08:28:05.71#ibcon#*after write, iclass 35, count 0 2006.169.08:28:05.71#ibcon#*before return 0, iclass 35, count 0 2006.169.08:28:05.71#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.169.08:28:05.71#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.169.08:28:05.71#ibcon#about to clear, iclass 35 cls_cnt 0 2006.169.08:28:05.71#ibcon#cleared, iclass 35 cls_cnt 0 2006.169.08:28:05.71$vc4f8/valo=4,832.99 2006.169.08:28:05.71#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.169.08:28:05.71#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.169.08:28:05.71#ibcon#ireg 17 cls_cnt 0 2006.169.08:28:05.71#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:28:05.71#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:28:05.71#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:28:05.71#ibcon#enter wrdev, iclass 37, count 0 2006.169.08:28:05.71#ibcon#first serial, iclass 37, count 0 2006.169.08:28:05.71#ibcon#enter sib2, iclass 37, count 0 2006.169.08:28:05.71#ibcon#flushed, iclass 37, count 0 2006.169.08:28:05.71#ibcon#about to write, iclass 37, count 0 2006.169.08:28:05.71#ibcon#wrote, iclass 37, count 0 2006.169.08:28:05.71#ibcon#about to read 3, iclass 37, count 0 2006.169.08:28:05.73#ibcon#read 3, iclass 37, count 0 2006.169.08:28:05.73#ibcon#about to read 4, iclass 37, count 0 2006.169.08:28:05.73#ibcon#read 4, iclass 37, count 0 2006.169.08:28:05.73#ibcon#about to read 5, iclass 37, count 0 2006.169.08:28:05.73#ibcon#read 5, iclass 37, count 0 2006.169.08:28:05.73#ibcon#about to read 6, iclass 37, count 0 2006.169.08:28:05.73#ibcon#read 6, iclass 37, count 0 2006.169.08:28:05.73#ibcon#end of sib2, iclass 37, count 0 2006.169.08:28:05.73#ibcon#*mode == 0, iclass 37, count 0 2006.169.08:28:05.73#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.169.08:28:05.73#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.08:28:05.73#ibcon#*before write, iclass 37, count 0 2006.169.08:28:05.73#ibcon#enter sib2, iclass 37, count 0 2006.169.08:28:05.73#ibcon#flushed, iclass 37, count 0 2006.169.08:28:05.73#ibcon#about to write, iclass 37, count 0 2006.169.08:28:05.73#ibcon#wrote, iclass 37, count 0 2006.169.08:28:05.73#ibcon#about to read 3, iclass 37, count 0 2006.169.08:28:05.77#ibcon#read 3, iclass 37, count 0 2006.169.08:28:05.77#ibcon#about to read 4, iclass 37, count 0 2006.169.08:28:05.77#ibcon#read 4, iclass 37, count 0 2006.169.08:28:05.77#ibcon#about to read 5, iclass 37, count 0 2006.169.08:28:05.77#ibcon#read 5, iclass 37, count 0 2006.169.08:28:05.77#ibcon#about to read 6, iclass 37, count 0 2006.169.08:28:05.77#ibcon#read 6, iclass 37, count 0 2006.169.08:28:05.77#ibcon#end of sib2, iclass 37, count 0 2006.169.08:28:05.77#ibcon#*after write, iclass 37, count 0 2006.169.08:28:05.77#ibcon#*before return 0, iclass 37, count 0 2006.169.08:28:05.77#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:28:05.77#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:28:05.77#ibcon#about to clear, iclass 37 cls_cnt 0 2006.169.08:28:05.77#ibcon#cleared, iclass 37 cls_cnt 0 2006.169.08:28:05.77$vc4f8/va=4,7 2006.169.08:28:05.77#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.169.08:28:05.77#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.169.08:28:05.77#ibcon#ireg 11 cls_cnt 2 2006.169.08:28:05.77#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.169.08:28:05.83#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.169.08:28:05.83#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.169.08:28:05.83#ibcon#enter wrdev, iclass 39, count 2 2006.169.08:28:05.83#ibcon#first serial, iclass 39, count 2 2006.169.08:28:05.83#ibcon#enter sib2, iclass 39, count 2 2006.169.08:28:05.83#ibcon#flushed, iclass 39, count 2 2006.169.08:28:05.83#ibcon#about to write, iclass 39, count 2 2006.169.08:28:05.83#ibcon#wrote, iclass 39, count 2 2006.169.08:28:05.83#ibcon#about to read 3, iclass 39, count 2 2006.169.08:28:05.85#ibcon#read 3, iclass 39, count 2 2006.169.08:28:05.85#ibcon#about to read 4, iclass 39, count 2 2006.169.08:28:05.85#ibcon#read 4, iclass 39, count 2 2006.169.08:28:05.85#ibcon#about to read 5, iclass 39, count 2 2006.169.08:28:05.85#ibcon#read 5, iclass 39, count 2 2006.169.08:28:05.85#ibcon#about to read 6, iclass 39, count 2 2006.169.08:28:05.85#ibcon#read 6, iclass 39, count 2 2006.169.08:28:05.85#ibcon#end of sib2, iclass 39, count 2 2006.169.08:28:05.85#ibcon#*mode == 0, iclass 39, count 2 2006.169.08:28:05.85#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.169.08:28:05.85#ibcon#[25=AT04-07\r\n] 2006.169.08:28:05.85#ibcon#*before write, iclass 39, count 2 2006.169.08:28:05.85#ibcon#enter sib2, iclass 39, count 2 2006.169.08:28:05.85#ibcon#flushed, iclass 39, count 2 2006.169.08:28:05.85#ibcon#about to write, iclass 39, count 2 2006.169.08:28:05.85#ibcon#wrote, iclass 39, count 2 2006.169.08:28:05.85#ibcon#about to read 3, iclass 39, count 2 2006.169.08:28:05.88#ibcon#read 3, iclass 39, count 2 2006.169.08:28:05.88#ibcon#about to read 4, iclass 39, count 2 2006.169.08:28:05.88#ibcon#read 4, iclass 39, count 2 2006.169.08:28:05.88#ibcon#about to read 5, iclass 39, count 2 2006.169.08:28:05.88#ibcon#read 5, iclass 39, count 2 2006.169.08:28:05.88#ibcon#about to read 6, iclass 39, count 2 2006.169.08:28:05.88#ibcon#read 6, iclass 39, count 2 2006.169.08:28:05.88#ibcon#end of sib2, iclass 39, count 2 2006.169.08:28:05.88#ibcon#*after write, iclass 39, count 2 2006.169.08:28:05.88#ibcon#*before return 0, iclass 39, count 2 2006.169.08:28:05.88#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.169.08:28:05.88#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.169.08:28:05.88#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.169.08:28:05.88#ibcon#ireg 7 cls_cnt 0 2006.169.08:28:05.88#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.169.08:28:06.00#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.169.08:28:06.00#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.169.08:28:06.00#ibcon#enter wrdev, iclass 39, count 0 2006.169.08:28:06.00#ibcon#first serial, iclass 39, count 0 2006.169.08:28:06.00#ibcon#enter sib2, iclass 39, count 0 2006.169.08:28:06.00#ibcon#flushed, iclass 39, count 0 2006.169.08:28:06.00#ibcon#about to write, iclass 39, count 0 2006.169.08:28:06.00#ibcon#wrote, iclass 39, count 0 2006.169.08:28:06.00#ibcon#about to read 3, iclass 39, count 0 2006.169.08:28:06.02#ibcon#read 3, iclass 39, count 0 2006.169.08:28:06.02#ibcon#about to read 4, iclass 39, count 0 2006.169.08:28:06.02#ibcon#read 4, iclass 39, count 0 2006.169.08:28:06.02#ibcon#about to read 5, iclass 39, count 0 2006.169.08:28:06.02#ibcon#read 5, iclass 39, count 0 2006.169.08:28:06.02#ibcon#about to read 6, iclass 39, count 0 2006.169.08:28:06.02#ibcon#read 6, iclass 39, count 0 2006.169.08:28:06.02#ibcon#end of sib2, iclass 39, count 0 2006.169.08:28:06.02#ibcon#*mode == 0, iclass 39, count 0 2006.169.08:28:06.02#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.169.08:28:06.02#ibcon#[25=USB\r\n] 2006.169.08:28:06.02#ibcon#*before write, iclass 39, count 0 2006.169.08:28:06.02#ibcon#enter sib2, iclass 39, count 0 2006.169.08:28:06.02#ibcon#flushed, iclass 39, count 0 2006.169.08:28:06.02#ibcon#about to write, iclass 39, count 0 2006.169.08:28:06.02#ibcon#wrote, iclass 39, count 0 2006.169.08:28:06.02#ibcon#about to read 3, iclass 39, count 0 2006.169.08:28:06.05#ibcon#read 3, iclass 39, count 0 2006.169.08:28:06.05#ibcon#about to read 4, iclass 39, count 0 2006.169.08:28:06.05#ibcon#read 4, iclass 39, count 0 2006.169.08:28:06.05#ibcon#about to read 5, iclass 39, count 0 2006.169.08:28:06.05#ibcon#read 5, iclass 39, count 0 2006.169.08:28:06.05#ibcon#about to read 6, iclass 39, count 0 2006.169.08:28:06.05#ibcon#read 6, iclass 39, count 0 2006.169.08:28:06.05#ibcon#end of sib2, iclass 39, count 0 2006.169.08:28:06.05#ibcon#*after write, iclass 39, count 0 2006.169.08:28:06.05#ibcon#*before return 0, iclass 39, count 0 2006.169.08:28:06.05#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.169.08:28:06.05#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.169.08:28:06.05#ibcon#about to clear, iclass 39 cls_cnt 0 2006.169.08:28:06.05#ibcon#cleared, iclass 39 cls_cnt 0 2006.169.08:28:06.05$vc4f8/valo=5,652.99 2006.169.08:28:06.05#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.169.08:28:06.05#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.169.08:28:06.05#ibcon#ireg 17 cls_cnt 0 2006.169.08:28:06.05#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.169.08:28:06.05#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.169.08:28:06.05#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.169.08:28:06.05#ibcon#enter wrdev, iclass 3, count 0 2006.169.08:28:06.05#ibcon#first serial, iclass 3, count 0 2006.169.08:28:06.05#ibcon#enter sib2, iclass 3, count 0 2006.169.08:28:06.05#ibcon#flushed, iclass 3, count 0 2006.169.08:28:06.05#ibcon#about to write, iclass 3, count 0 2006.169.08:28:06.05#ibcon#wrote, iclass 3, count 0 2006.169.08:28:06.05#ibcon#about to read 3, iclass 3, count 0 2006.169.08:28:06.07#ibcon#read 3, iclass 3, count 0 2006.169.08:28:06.07#ibcon#about to read 4, iclass 3, count 0 2006.169.08:28:06.07#ibcon#read 4, iclass 3, count 0 2006.169.08:28:06.07#ibcon#about to read 5, iclass 3, count 0 2006.169.08:28:06.07#ibcon#read 5, iclass 3, count 0 2006.169.08:28:06.07#ibcon#about to read 6, iclass 3, count 0 2006.169.08:28:06.07#ibcon#read 6, iclass 3, count 0 2006.169.08:28:06.07#ibcon#end of sib2, iclass 3, count 0 2006.169.08:28:06.07#ibcon#*mode == 0, iclass 3, count 0 2006.169.08:28:06.07#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.169.08:28:06.07#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.08:28:06.07#ibcon#*before write, iclass 3, count 0 2006.169.08:28:06.07#ibcon#enter sib2, iclass 3, count 0 2006.169.08:28:06.07#ibcon#flushed, iclass 3, count 0 2006.169.08:28:06.07#ibcon#about to write, iclass 3, count 0 2006.169.08:28:06.07#ibcon#wrote, iclass 3, count 0 2006.169.08:28:06.07#ibcon#about to read 3, iclass 3, count 0 2006.169.08:28:06.11#ibcon#read 3, iclass 3, count 0 2006.169.08:28:06.11#ibcon#about to read 4, iclass 3, count 0 2006.169.08:28:06.11#ibcon#read 4, iclass 3, count 0 2006.169.08:28:06.11#ibcon#about to read 5, iclass 3, count 0 2006.169.08:28:06.11#ibcon#read 5, iclass 3, count 0 2006.169.08:28:06.11#ibcon#about to read 6, iclass 3, count 0 2006.169.08:28:06.11#ibcon#read 6, iclass 3, count 0 2006.169.08:28:06.11#ibcon#end of sib2, iclass 3, count 0 2006.169.08:28:06.11#ibcon#*after write, iclass 3, count 0 2006.169.08:28:06.11#ibcon#*before return 0, iclass 3, count 0 2006.169.08:28:06.11#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.169.08:28:06.11#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.169.08:28:06.11#ibcon#about to clear, iclass 3 cls_cnt 0 2006.169.08:28:06.11#ibcon#cleared, iclass 3 cls_cnt 0 2006.169.08:28:06.11$vc4f8/va=5,7 2006.169.08:28:06.11#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.169.08:28:06.11#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.169.08:28:06.11#ibcon#ireg 11 cls_cnt 2 2006.169.08:28:06.11#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.169.08:28:06.17#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.169.08:28:06.17#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.169.08:28:06.17#ibcon#enter wrdev, iclass 5, count 2 2006.169.08:28:06.17#ibcon#first serial, iclass 5, count 2 2006.169.08:28:06.17#ibcon#enter sib2, iclass 5, count 2 2006.169.08:28:06.17#ibcon#flushed, iclass 5, count 2 2006.169.08:28:06.17#ibcon#about to write, iclass 5, count 2 2006.169.08:28:06.17#ibcon#wrote, iclass 5, count 2 2006.169.08:28:06.17#ibcon#about to read 3, iclass 5, count 2 2006.169.08:28:06.19#ibcon#read 3, iclass 5, count 2 2006.169.08:28:06.19#ibcon#about to read 4, iclass 5, count 2 2006.169.08:28:06.19#ibcon#read 4, iclass 5, count 2 2006.169.08:28:06.19#ibcon#about to read 5, iclass 5, count 2 2006.169.08:28:06.19#ibcon#read 5, iclass 5, count 2 2006.169.08:28:06.19#ibcon#about to read 6, iclass 5, count 2 2006.169.08:28:06.19#ibcon#read 6, iclass 5, count 2 2006.169.08:28:06.19#ibcon#end of sib2, iclass 5, count 2 2006.169.08:28:06.19#ibcon#*mode == 0, iclass 5, count 2 2006.169.08:28:06.19#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.169.08:28:06.19#ibcon#[25=AT05-07\r\n] 2006.169.08:28:06.19#ibcon#*before write, iclass 5, count 2 2006.169.08:28:06.19#ibcon#enter sib2, iclass 5, count 2 2006.169.08:28:06.19#ibcon#flushed, iclass 5, count 2 2006.169.08:28:06.19#ibcon#about to write, iclass 5, count 2 2006.169.08:28:06.19#ibcon#wrote, iclass 5, count 2 2006.169.08:28:06.19#ibcon#about to read 3, iclass 5, count 2 2006.169.08:28:06.22#ibcon#read 3, iclass 5, count 2 2006.169.08:28:06.22#ibcon#about to read 4, iclass 5, count 2 2006.169.08:28:06.22#ibcon#read 4, iclass 5, count 2 2006.169.08:28:06.22#ibcon#about to read 5, iclass 5, count 2 2006.169.08:28:06.22#ibcon#read 5, iclass 5, count 2 2006.169.08:28:06.22#ibcon#about to read 6, iclass 5, count 2 2006.169.08:28:06.22#ibcon#read 6, iclass 5, count 2 2006.169.08:28:06.22#ibcon#end of sib2, iclass 5, count 2 2006.169.08:28:06.22#ibcon#*after write, iclass 5, count 2 2006.169.08:28:06.22#ibcon#*before return 0, iclass 5, count 2 2006.169.08:28:06.22#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.169.08:28:06.22#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.169.08:28:06.22#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.169.08:28:06.22#ibcon#ireg 7 cls_cnt 0 2006.169.08:28:06.22#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.169.08:28:06.34#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.169.08:28:06.34#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.169.08:28:06.34#ibcon#enter wrdev, iclass 5, count 0 2006.169.08:28:06.34#ibcon#first serial, iclass 5, count 0 2006.169.08:28:06.34#ibcon#enter sib2, iclass 5, count 0 2006.169.08:28:06.34#ibcon#flushed, iclass 5, count 0 2006.169.08:28:06.34#ibcon#about to write, iclass 5, count 0 2006.169.08:28:06.34#ibcon#wrote, iclass 5, count 0 2006.169.08:28:06.34#ibcon#about to read 3, iclass 5, count 0 2006.169.08:28:06.36#ibcon#read 3, iclass 5, count 0 2006.169.08:28:06.36#ibcon#about to read 4, iclass 5, count 0 2006.169.08:28:06.36#ibcon#read 4, iclass 5, count 0 2006.169.08:28:06.36#ibcon#about to read 5, iclass 5, count 0 2006.169.08:28:06.36#ibcon#read 5, iclass 5, count 0 2006.169.08:28:06.36#ibcon#about to read 6, iclass 5, count 0 2006.169.08:28:06.36#ibcon#read 6, iclass 5, count 0 2006.169.08:28:06.36#ibcon#end of sib2, iclass 5, count 0 2006.169.08:28:06.36#ibcon#*mode == 0, iclass 5, count 0 2006.169.08:28:06.36#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.169.08:28:06.36#ibcon#[25=USB\r\n] 2006.169.08:28:06.36#ibcon#*before write, iclass 5, count 0 2006.169.08:28:06.36#ibcon#enter sib2, iclass 5, count 0 2006.169.08:28:06.36#ibcon#flushed, iclass 5, count 0 2006.169.08:28:06.36#ibcon#about to write, iclass 5, count 0 2006.169.08:28:06.36#ibcon#wrote, iclass 5, count 0 2006.169.08:28:06.36#ibcon#about to read 3, iclass 5, count 0 2006.169.08:28:06.39#ibcon#read 3, iclass 5, count 0 2006.169.08:28:06.39#ibcon#about to read 4, iclass 5, count 0 2006.169.08:28:06.39#ibcon#read 4, iclass 5, count 0 2006.169.08:28:06.39#ibcon#about to read 5, iclass 5, count 0 2006.169.08:28:06.39#ibcon#read 5, iclass 5, count 0 2006.169.08:28:06.39#ibcon#about to read 6, iclass 5, count 0 2006.169.08:28:06.39#ibcon#read 6, iclass 5, count 0 2006.169.08:28:06.39#ibcon#end of sib2, iclass 5, count 0 2006.169.08:28:06.39#ibcon#*after write, iclass 5, count 0 2006.169.08:28:06.39#ibcon#*before return 0, iclass 5, count 0 2006.169.08:28:06.39#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.169.08:28:06.39#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.169.08:28:06.39#ibcon#about to clear, iclass 5 cls_cnt 0 2006.169.08:28:06.39#ibcon#cleared, iclass 5 cls_cnt 0 2006.169.08:28:06.39$vc4f8/valo=6,772.99 2006.169.08:28:06.39#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.169.08:28:06.39#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.169.08:28:06.39#ibcon#ireg 17 cls_cnt 0 2006.169.08:28:06.39#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.169.08:28:06.39#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.169.08:28:06.39#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.169.08:28:06.39#ibcon#enter wrdev, iclass 7, count 0 2006.169.08:28:06.39#ibcon#first serial, iclass 7, count 0 2006.169.08:28:06.39#ibcon#enter sib2, iclass 7, count 0 2006.169.08:28:06.39#ibcon#flushed, iclass 7, count 0 2006.169.08:28:06.39#ibcon#about to write, iclass 7, count 0 2006.169.08:28:06.39#ibcon#wrote, iclass 7, count 0 2006.169.08:28:06.39#ibcon#about to read 3, iclass 7, count 0 2006.169.08:28:06.41#ibcon#read 3, iclass 7, count 0 2006.169.08:28:06.41#ibcon#about to read 4, iclass 7, count 0 2006.169.08:28:06.41#ibcon#read 4, iclass 7, count 0 2006.169.08:28:06.41#ibcon#about to read 5, iclass 7, count 0 2006.169.08:28:06.41#ibcon#read 5, iclass 7, count 0 2006.169.08:28:06.41#ibcon#about to read 6, iclass 7, count 0 2006.169.08:28:06.41#ibcon#read 6, iclass 7, count 0 2006.169.08:28:06.41#ibcon#end of sib2, iclass 7, count 0 2006.169.08:28:06.41#ibcon#*mode == 0, iclass 7, count 0 2006.169.08:28:06.41#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.169.08:28:06.41#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.08:28:06.41#ibcon#*before write, iclass 7, count 0 2006.169.08:28:06.41#ibcon#enter sib2, iclass 7, count 0 2006.169.08:28:06.41#ibcon#flushed, iclass 7, count 0 2006.169.08:28:06.41#ibcon#about to write, iclass 7, count 0 2006.169.08:28:06.41#ibcon#wrote, iclass 7, count 0 2006.169.08:28:06.41#ibcon#about to read 3, iclass 7, count 0 2006.169.08:28:06.45#ibcon#read 3, iclass 7, count 0 2006.169.08:28:06.45#ibcon#about to read 4, iclass 7, count 0 2006.169.08:28:06.45#ibcon#read 4, iclass 7, count 0 2006.169.08:28:06.45#ibcon#about to read 5, iclass 7, count 0 2006.169.08:28:06.45#ibcon#read 5, iclass 7, count 0 2006.169.08:28:06.45#ibcon#about to read 6, iclass 7, count 0 2006.169.08:28:06.45#ibcon#read 6, iclass 7, count 0 2006.169.08:28:06.45#ibcon#end of sib2, iclass 7, count 0 2006.169.08:28:06.45#ibcon#*after write, iclass 7, count 0 2006.169.08:28:06.45#ibcon#*before return 0, iclass 7, count 0 2006.169.08:28:06.45#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.169.08:28:06.45#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.169.08:28:06.45#ibcon#about to clear, iclass 7 cls_cnt 0 2006.169.08:28:06.45#ibcon#cleared, iclass 7 cls_cnt 0 2006.169.08:28:06.45$vc4f8/va=6,6 2006.169.08:28:06.45#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.169.08:28:06.45#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.169.08:28:06.45#ibcon#ireg 11 cls_cnt 2 2006.169.08:28:06.45#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.169.08:28:06.51#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.169.08:28:06.51#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.169.08:28:06.51#ibcon#enter wrdev, iclass 11, count 2 2006.169.08:28:06.51#ibcon#first serial, iclass 11, count 2 2006.169.08:28:06.51#ibcon#enter sib2, iclass 11, count 2 2006.169.08:28:06.51#ibcon#flushed, iclass 11, count 2 2006.169.08:28:06.51#ibcon#about to write, iclass 11, count 2 2006.169.08:28:06.51#ibcon#wrote, iclass 11, count 2 2006.169.08:28:06.51#ibcon#about to read 3, iclass 11, count 2 2006.169.08:28:06.53#ibcon#read 3, iclass 11, count 2 2006.169.08:28:06.53#ibcon#about to read 4, iclass 11, count 2 2006.169.08:28:06.53#ibcon#read 4, iclass 11, count 2 2006.169.08:28:06.53#ibcon#about to read 5, iclass 11, count 2 2006.169.08:28:06.53#ibcon#read 5, iclass 11, count 2 2006.169.08:28:06.53#ibcon#about to read 6, iclass 11, count 2 2006.169.08:28:06.53#ibcon#read 6, iclass 11, count 2 2006.169.08:28:06.53#ibcon#end of sib2, iclass 11, count 2 2006.169.08:28:06.53#ibcon#*mode == 0, iclass 11, count 2 2006.169.08:28:06.53#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.169.08:28:06.53#ibcon#[25=AT06-06\r\n] 2006.169.08:28:06.53#ibcon#*before write, iclass 11, count 2 2006.169.08:28:06.53#ibcon#enter sib2, iclass 11, count 2 2006.169.08:28:06.53#ibcon#flushed, iclass 11, count 2 2006.169.08:28:06.53#ibcon#about to write, iclass 11, count 2 2006.169.08:28:06.53#ibcon#wrote, iclass 11, count 2 2006.169.08:28:06.53#ibcon#about to read 3, iclass 11, count 2 2006.169.08:28:06.56#ibcon#read 3, iclass 11, count 2 2006.169.08:28:06.56#ibcon#about to read 4, iclass 11, count 2 2006.169.08:28:06.56#ibcon#read 4, iclass 11, count 2 2006.169.08:28:06.56#ibcon#about to read 5, iclass 11, count 2 2006.169.08:28:06.56#ibcon#read 5, iclass 11, count 2 2006.169.08:28:06.56#ibcon#about to read 6, iclass 11, count 2 2006.169.08:28:06.56#ibcon#read 6, iclass 11, count 2 2006.169.08:28:06.56#ibcon#end of sib2, iclass 11, count 2 2006.169.08:28:06.56#ibcon#*after write, iclass 11, count 2 2006.169.08:28:06.56#ibcon#*before return 0, iclass 11, count 2 2006.169.08:28:06.56#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.169.08:28:06.56#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.169.08:28:06.56#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.169.08:28:06.56#ibcon#ireg 7 cls_cnt 0 2006.169.08:28:06.56#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.169.08:28:06.68#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.169.08:28:06.68#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.169.08:28:06.68#ibcon#enter wrdev, iclass 11, count 0 2006.169.08:28:06.68#ibcon#first serial, iclass 11, count 0 2006.169.08:28:06.68#ibcon#enter sib2, iclass 11, count 0 2006.169.08:28:06.68#ibcon#flushed, iclass 11, count 0 2006.169.08:28:06.68#ibcon#about to write, iclass 11, count 0 2006.169.08:28:06.68#ibcon#wrote, iclass 11, count 0 2006.169.08:28:06.68#ibcon#about to read 3, iclass 11, count 0 2006.169.08:28:06.70#ibcon#read 3, iclass 11, count 0 2006.169.08:28:06.70#ibcon#about to read 4, iclass 11, count 0 2006.169.08:28:06.70#ibcon#read 4, iclass 11, count 0 2006.169.08:28:06.70#ibcon#about to read 5, iclass 11, count 0 2006.169.08:28:06.70#ibcon#read 5, iclass 11, count 0 2006.169.08:28:06.70#ibcon#about to read 6, iclass 11, count 0 2006.169.08:28:06.70#ibcon#read 6, iclass 11, count 0 2006.169.08:28:06.70#ibcon#end of sib2, iclass 11, count 0 2006.169.08:28:06.70#ibcon#*mode == 0, iclass 11, count 0 2006.169.08:28:06.70#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.169.08:28:06.70#ibcon#[25=USB\r\n] 2006.169.08:28:06.70#ibcon#*before write, iclass 11, count 0 2006.169.08:28:06.70#ibcon#enter sib2, iclass 11, count 0 2006.169.08:28:06.70#ibcon#flushed, iclass 11, count 0 2006.169.08:28:06.70#ibcon#about to write, iclass 11, count 0 2006.169.08:28:06.70#ibcon#wrote, iclass 11, count 0 2006.169.08:28:06.70#ibcon#about to read 3, iclass 11, count 0 2006.169.08:28:06.73#ibcon#read 3, iclass 11, count 0 2006.169.08:28:06.73#ibcon#about to read 4, iclass 11, count 0 2006.169.08:28:06.73#ibcon#read 4, iclass 11, count 0 2006.169.08:28:06.73#ibcon#about to read 5, iclass 11, count 0 2006.169.08:28:06.73#ibcon#read 5, iclass 11, count 0 2006.169.08:28:06.73#ibcon#about to read 6, iclass 11, count 0 2006.169.08:28:06.73#ibcon#read 6, iclass 11, count 0 2006.169.08:28:06.73#ibcon#end of sib2, iclass 11, count 0 2006.169.08:28:06.73#ibcon#*after write, iclass 11, count 0 2006.169.08:28:06.73#ibcon#*before return 0, iclass 11, count 0 2006.169.08:28:06.73#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.169.08:28:06.73#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.169.08:28:06.73#ibcon#about to clear, iclass 11 cls_cnt 0 2006.169.08:28:06.73#ibcon#cleared, iclass 11 cls_cnt 0 2006.169.08:28:06.73$vc4f8/valo=7,832.99 2006.169.08:28:06.73#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.169.08:28:06.73#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.169.08:28:06.73#ibcon#ireg 17 cls_cnt 0 2006.169.08:28:06.73#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:28:06.73#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:28:06.73#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:28:06.73#ibcon#enter wrdev, iclass 13, count 0 2006.169.08:28:06.73#ibcon#first serial, iclass 13, count 0 2006.169.08:28:06.73#ibcon#enter sib2, iclass 13, count 0 2006.169.08:28:06.73#ibcon#flushed, iclass 13, count 0 2006.169.08:28:06.73#ibcon#about to write, iclass 13, count 0 2006.169.08:28:06.73#ibcon#wrote, iclass 13, count 0 2006.169.08:28:06.73#ibcon#about to read 3, iclass 13, count 0 2006.169.08:28:06.75#ibcon#read 3, iclass 13, count 0 2006.169.08:28:06.75#ibcon#about to read 4, iclass 13, count 0 2006.169.08:28:06.75#ibcon#read 4, iclass 13, count 0 2006.169.08:28:06.75#ibcon#about to read 5, iclass 13, count 0 2006.169.08:28:06.75#ibcon#read 5, iclass 13, count 0 2006.169.08:28:06.75#ibcon#about to read 6, iclass 13, count 0 2006.169.08:28:06.75#ibcon#read 6, iclass 13, count 0 2006.169.08:28:06.75#ibcon#end of sib2, iclass 13, count 0 2006.169.08:28:06.75#ibcon#*mode == 0, iclass 13, count 0 2006.169.08:28:06.75#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.08:28:06.75#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.08:28:06.75#ibcon#*before write, iclass 13, count 0 2006.169.08:28:06.75#ibcon#enter sib2, iclass 13, count 0 2006.169.08:28:06.75#ibcon#flushed, iclass 13, count 0 2006.169.08:28:06.75#ibcon#about to write, iclass 13, count 0 2006.169.08:28:06.75#ibcon#wrote, iclass 13, count 0 2006.169.08:28:06.75#ibcon#about to read 3, iclass 13, count 0 2006.169.08:28:06.79#ibcon#read 3, iclass 13, count 0 2006.169.08:28:06.79#ibcon#about to read 4, iclass 13, count 0 2006.169.08:28:06.79#ibcon#read 4, iclass 13, count 0 2006.169.08:28:06.79#ibcon#about to read 5, iclass 13, count 0 2006.169.08:28:06.79#ibcon#read 5, iclass 13, count 0 2006.169.08:28:06.79#ibcon#about to read 6, iclass 13, count 0 2006.169.08:28:06.79#ibcon#read 6, iclass 13, count 0 2006.169.08:28:06.79#ibcon#end of sib2, iclass 13, count 0 2006.169.08:28:06.79#ibcon#*after write, iclass 13, count 0 2006.169.08:28:06.79#ibcon#*before return 0, iclass 13, count 0 2006.169.08:28:06.79#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:28:06.79#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:28:06.79#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.08:28:06.79#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.08:28:06.79$vc4f8/va=7,6 2006.169.08:28:06.79#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.169.08:28:06.79#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.169.08:28:06.79#ibcon#ireg 11 cls_cnt 2 2006.169.08:28:06.79#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.169.08:28:06.85#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.169.08:28:06.85#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.169.08:28:06.85#ibcon#enter wrdev, iclass 15, count 2 2006.169.08:28:06.85#ibcon#first serial, iclass 15, count 2 2006.169.08:28:06.85#ibcon#enter sib2, iclass 15, count 2 2006.169.08:28:06.85#ibcon#flushed, iclass 15, count 2 2006.169.08:28:06.85#ibcon#about to write, iclass 15, count 2 2006.169.08:28:06.85#ibcon#wrote, iclass 15, count 2 2006.169.08:28:06.85#ibcon#about to read 3, iclass 15, count 2 2006.169.08:28:06.87#ibcon#read 3, iclass 15, count 2 2006.169.08:28:06.87#ibcon#about to read 4, iclass 15, count 2 2006.169.08:28:06.87#ibcon#read 4, iclass 15, count 2 2006.169.08:28:06.87#ibcon#about to read 5, iclass 15, count 2 2006.169.08:28:06.87#ibcon#read 5, iclass 15, count 2 2006.169.08:28:06.87#ibcon#about to read 6, iclass 15, count 2 2006.169.08:28:06.87#ibcon#read 6, iclass 15, count 2 2006.169.08:28:06.87#ibcon#end of sib2, iclass 15, count 2 2006.169.08:28:06.87#ibcon#*mode == 0, iclass 15, count 2 2006.169.08:28:06.87#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.169.08:28:06.87#ibcon#[25=AT07-06\r\n] 2006.169.08:28:06.87#ibcon#*before write, iclass 15, count 2 2006.169.08:28:06.87#ibcon#enter sib2, iclass 15, count 2 2006.169.08:28:06.87#ibcon#flushed, iclass 15, count 2 2006.169.08:28:06.87#ibcon#about to write, iclass 15, count 2 2006.169.08:28:06.87#ibcon#wrote, iclass 15, count 2 2006.169.08:28:06.87#ibcon#about to read 3, iclass 15, count 2 2006.169.08:28:06.90#ibcon#read 3, iclass 15, count 2 2006.169.08:28:06.90#ibcon#about to read 4, iclass 15, count 2 2006.169.08:28:06.90#ibcon#read 4, iclass 15, count 2 2006.169.08:28:06.90#ibcon#about to read 5, iclass 15, count 2 2006.169.08:28:06.90#ibcon#read 5, iclass 15, count 2 2006.169.08:28:06.90#ibcon#about to read 6, iclass 15, count 2 2006.169.08:28:06.90#ibcon#read 6, iclass 15, count 2 2006.169.08:28:06.90#ibcon#end of sib2, iclass 15, count 2 2006.169.08:28:06.90#ibcon#*after write, iclass 15, count 2 2006.169.08:28:06.90#ibcon#*before return 0, iclass 15, count 2 2006.169.08:28:06.90#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.169.08:28:06.90#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.169.08:28:06.90#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.169.08:28:06.90#ibcon#ireg 7 cls_cnt 0 2006.169.08:28:06.90#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.169.08:28:07.02#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.169.08:28:07.02#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.169.08:28:07.02#ibcon#enter wrdev, iclass 15, count 0 2006.169.08:28:07.02#ibcon#first serial, iclass 15, count 0 2006.169.08:28:07.02#ibcon#enter sib2, iclass 15, count 0 2006.169.08:28:07.02#ibcon#flushed, iclass 15, count 0 2006.169.08:28:07.02#ibcon#about to write, iclass 15, count 0 2006.169.08:28:07.02#ibcon#wrote, iclass 15, count 0 2006.169.08:28:07.02#ibcon#about to read 3, iclass 15, count 0 2006.169.08:28:07.04#ibcon#read 3, iclass 15, count 0 2006.169.08:28:07.04#ibcon#about to read 4, iclass 15, count 0 2006.169.08:28:07.04#ibcon#read 4, iclass 15, count 0 2006.169.08:28:07.04#ibcon#about to read 5, iclass 15, count 0 2006.169.08:28:07.04#ibcon#read 5, iclass 15, count 0 2006.169.08:28:07.04#ibcon#about to read 6, iclass 15, count 0 2006.169.08:28:07.04#ibcon#read 6, iclass 15, count 0 2006.169.08:28:07.04#ibcon#end of sib2, iclass 15, count 0 2006.169.08:28:07.04#ibcon#*mode == 0, iclass 15, count 0 2006.169.08:28:07.04#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.169.08:28:07.04#ibcon#[25=USB\r\n] 2006.169.08:28:07.04#ibcon#*before write, iclass 15, count 0 2006.169.08:28:07.04#ibcon#enter sib2, iclass 15, count 0 2006.169.08:28:07.04#ibcon#flushed, iclass 15, count 0 2006.169.08:28:07.04#ibcon#about to write, iclass 15, count 0 2006.169.08:28:07.04#ibcon#wrote, iclass 15, count 0 2006.169.08:28:07.04#ibcon#about to read 3, iclass 15, count 0 2006.169.08:28:07.07#ibcon#read 3, iclass 15, count 0 2006.169.08:28:07.07#ibcon#about to read 4, iclass 15, count 0 2006.169.08:28:07.07#ibcon#read 4, iclass 15, count 0 2006.169.08:28:07.07#ibcon#about to read 5, iclass 15, count 0 2006.169.08:28:07.07#ibcon#read 5, iclass 15, count 0 2006.169.08:28:07.07#ibcon#about to read 6, iclass 15, count 0 2006.169.08:28:07.07#ibcon#read 6, iclass 15, count 0 2006.169.08:28:07.07#ibcon#end of sib2, iclass 15, count 0 2006.169.08:28:07.07#ibcon#*after write, iclass 15, count 0 2006.169.08:28:07.07#ibcon#*before return 0, iclass 15, count 0 2006.169.08:28:07.07#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.169.08:28:07.07#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.169.08:28:07.07#ibcon#about to clear, iclass 15 cls_cnt 0 2006.169.08:28:07.07#ibcon#cleared, iclass 15 cls_cnt 0 2006.169.08:28:07.07$vc4f8/valo=8,852.99 2006.169.08:28:07.07#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.169.08:28:07.07#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.169.08:28:07.07#ibcon#ireg 17 cls_cnt 0 2006.169.08:28:07.07#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:28:07.07#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:28:07.07#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:28:07.07#ibcon#enter wrdev, iclass 17, count 0 2006.169.08:28:07.07#ibcon#first serial, iclass 17, count 0 2006.169.08:28:07.07#ibcon#enter sib2, iclass 17, count 0 2006.169.08:28:07.07#ibcon#flushed, iclass 17, count 0 2006.169.08:28:07.07#ibcon#about to write, iclass 17, count 0 2006.169.08:28:07.07#ibcon#wrote, iclass 17, count 0 2006.169.08:28:07.07#ibcon#about to read 3, iclass 17, count 0 2006.169.08:28:07.09#ibcon#read 3, iclass 17, count 0 2006.169.08:28:07.09#ibcon#about to read 4, iclass 17, count 0 2006.169.08:28:07.09#ibcon#read 4, iclass 17, count 0 2006.169.08:28:07.09#ibcon#about to read 5, iclass 17, count 0 2006.169.08:28:07.09#ibcon#read 5, iclass 17, count 0 2006.169.08:28:07.09#ibcon#about to read 6, iclass 17, count 0 2006.169.08:28:07.09#ibcon#read 6, iclass 17, count 0 2006.169.08:28:07.09#ibcon#end of sib2, iclass 17, count 0 2006.169.08:28:07.09#ibcon#*mode == 0, iclass 17, count 0 2006.169.08:28:07.09#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.169.08:28:07.09#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.08:28:07.09#ibcon#*before write, iclass 17, count 0 2006.169.08:28:07.09#ibcon#enter sib2, iclass 17, count 0 2006.169.08:28:07.09#ibcon#flushed, iclass 17, count 0 2006.169.08:28:07.09#ibcon#about to write, iclass 17, count 0 2006.169.08:28:07.09#ibcon#wrote, iclass 17, count 0 2006.169.08:28:07.09#ibcon#about to read 3, iclass 17, count 0 2006.169.08:28:07.13#ibcon#read 3, iclass 17, count 0 2006.169.08:28:07.13#ibcon#about to read 4, iclass 17, count 0 2006.169.08:28:07.13#ibcon#read 4, iclass 17, count 0 2006.169.08:28:07.13#ibcon#about to read 5, iclass 17, count 0 2006.169.08:28:07.13#ibcon#read 5, iclass 17, count 0 2006.169.08:28:07.13#ibcon#about to read 6, iclass 17, count 0 2006.169.08:28:07.13#ibcon#read 6, iclass 17, count 0 2006.169.08:28:07.13#ibcon#end of sib2, iclass 17, count 0 2006.169.08:28:07.13#ibcon#*after write, iclass 17, count 0 2006.169.08:28:07.13#ibcon#*before return 0, iclass 17, count 0 2006.169.08:28:07.13#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:28:07.13#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.169.08:28:07.13#ibcon#about to clear, iclass 17 cls_cnt 0 2006.169.08:28:07.13#ibcon#cleared, iclass 17 cls_cnt 0 2006.169.08:28:07.13$vc4f8/va=8,7 2006.169.08:28:07.13#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.169.08:28:07.13#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.169.08:28:07.13#ibcon#ireg 11 cls_cnt 2 2006.169.08:28:07.13#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.169.08:28:07.19#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.169.08:28:07.19#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.169.08:28:07.19#ibcon#enter wrdev, iclass 19, count 2 2006.169.08:28:07.19#ibcon#first serial, iclass 19, count 2 2006.169.08:28:07.19#ibcon#enter sib2, iclass 19, count 2 2006.169.08:28:07.19#ibcon#flushed, iclass 19, count 2 2006.169.08:28:07.19#ibcon#about to write, iclass 19, count 2 2006.169.08:28:07.19#ibcon#wrote, iclass 19, count 2 2006.169.08:28:07.19#ibcon#about to read 3, iclass 19, count 2 2006.169.08:28:07.21#ibcon#read 3, iclass 19, count 2 2006.169.08:28:07.21#ibcon#about to read 4, iclass 19, count 2 2006.169.08:28:07.21#ibcon#read 4, iclass 19, count 2 2006.169.08:28:07.21#ibcon#about to read 5, iclass 19, count 2 2006.169.08:28:07.21#ibcon#read 5, iclass 19, count 2 2006.169.08:28:07.21#ibcon#about to read 6, iclass 19, count 2 2006.169.08:28:07.21#ibcon#read 6, iclass 19, count 2 2006.169.08:28:07.21#ibcon#end of sib2, iclass 19, count 2 2006.169.08:28:07.21#ibcon#*mode == 0, iclass 19, count 2 2006.169.08:28:07.21#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.169.08:28:07.21#ibcon#[25=AT08-07\r\n] 2006.169.08:28:07.21#ibcon#*before write, iclass 19, count 2 2006.169.08:28:07.21#ibcon#enter sib2, iclass 19, count 2 2006.169.08:28:07.21#ibcon#flushed, iclass 19, count 2 2006.169.08:28:07.21#ibcon#about to write, iclass 19, count 2 2006.169.08:28:07.21#ibcon#wrote, iclass 19, count 2 2006.169.08:28:07.21#ibcon#about to read 3, iclass 19, count 2 2006.169.08:28:07.24#ibcon#read 3, iclass 19, count 2 2006.169.08:28:07.24#ibcon#about to read 4, iclass 19, count 2 2006.169.08:28:07.24#ibcon#read 4, iclass 19, count 2 2006.169.08:28:07.24#ibcon#about to read 5, iclass 19, count 2 2006.169.08:28:07.24#ibcon#read 5, iclass 19, count 2 2006.169.08:28:07.24#ibcon#about to read 6, iclass 19, count 2 2006.169.08:28:07.24#ibcon#read 6, iclass 19, count 2 2006.169.08:28:07.24#ibcon#end of sib2, iclass 19, count 2 2006.169.08:28:07.24#ibcon#*after write, iclass 19, count 2 2006.169.08:28:07.24#ibcon#*before return 0, iclass 19, count 2 2006.169.08:28:07.24#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.169.08:28:07.24#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.169.08:28:07.24#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.169.08:28:07.24#ibcon#ireg 7 cls_cnt 0 2006.169.08:28:07.24#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.169.08:28:07.36#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.169.08:28:07.36#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.169.08:28:07.36#ibcon#enter wrdev, iclass 19, count 0 2006.169.08:28:07.36#ibcon#first serial, iclass 19, count 0 2006.169.08:28:07.36#ibcon#enter sib2, iclass 19, count 0 2006.169.08:28:07.36#ibcon#flushed, iclass 19, count 0 2006.169.08:28:07.36#ibcon#about to write, iclass 19, count 0 2006.169.08:28:07.36#ibcon#wrote, iclass 19, count 0 2006.169.08:28:07.36#ibcon#about to read 3, iclass 19, count 0 2006.169.08:28:07.38#ibcon#read 3, iclass 19, count 0 2006.169.08:28:07.38#ibcon#about to read 4, iclass 19, count 0 2006.169.08:28:07.38#ibcon#read 4, iclass 19, count 0 2006.169.08:28:07.38#ibcon#about to read 5, iclass 19, count 0 2006.169.08:28:07.38#ibcon#read 5, iclass 19, count 0 2006.169.08:28:07.38#ibcon#about to read 6, iclass 19, count 0 2006.169.08:28:07.38#ibcon#read 6, iclass 19, count 0 2006.169.08:28:07.38#ibcon#end of sib2, iclass 19, count 0 2006.169.08:28:07.38#ibcon#*mode == 0, iclass 19, count 0 2006.169.08:28:07.38#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.169.08:28:07.38#ibcon#[25=USB\r\n] 2006.169.08:28:07.38#ibcon#*before write, iclass 19, count 0 2006.169.08:28:07.38#ibcon#enter sib2, iclass 19, count 0 2006.169.08:28:07.38#ibcon#flushed, iclass 19, count 0 2006.169.08:28:07.38#ibcon#about to write, iclass 19, count 0 2006.169.08:28:07.38#ibcon#wrote, iclass 19, count 0 2006.169.08:28:07.38#ibcon#about to read 3, iclass 19, count 0 2006.169.08:28:07.41#ibcon#read 3, iclass 19, count 0 2006.169.08:28:07.41#ibcon#about to read 4, iclass 19, count 0 2006.169.08:28:07.41#ibcon#read 4, iclass 19, count 0 2006.169.08:28:07.41#ibcon#about to read 5, iclass 19, count 0 2006.169.08:28:07.41#ibcon#read 5, iclass 19, count 0 2006.169.08:28:07.41#ibcon#about to read 6, iclass 19, count 0 2006.169.08:28:07.41#ibcon#read 6, iclass 19, count 0 2006.169.08:28:07.41#ibcon#end of sib2, iclass 19, count 0 2006.169.08:28:07.41#ibcon#*after write, iclass 19, count 0 2006.169.08:28:07.41#ibcon#*before return 0, iclass 19, count 0 2006.169.08:28:07.41#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.169.08:28:07.41#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.169.08:28:07.41#ibcon#about to clear, iclass 19 cls_cnt 0 2006.169.08:28:07.41#ibcon#cleared, iclass 19 cls_cnt 0 2006.169.08:28:07.41$vc4f8/vblo=1,632.99 2006.169.08:28:07.41#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.169.08:28:07.41#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.169.08:28:07.41#ibcon#ireg 17 cls_cnt 0 2006.169.08:28:07.41#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.169.08:28:07.41#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.169.08:28:07.41#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.169.08:28:07.41#ibcon#enter wrdev, iclass 21, count 0 2006.169.08:28:07.41#ibcon#first serial, iclass 21, count 0 2006.169.08:28:07.41#ibcon#enter sib2, iclass 21, count 0 2006.169.08:28:07.41#ibcon#flushed, iclass 21, count 0 2006.169.08:28:07.41#ibcon#about to write, iclass 21, count 0 2006.169.08:28:07.41#ibcon#wrote, iclass 21, count 0 2006.169.08:28:07.41#ibcon#about to read 3, iclass 21, count 0 2006.169.08:28:07.43#ibcon#read 3, iclass 21, count 0 2006.169.08:28:07.43#ibcon#about to read 4, iclass 21, count 0 2006.169.08:28:07.43#ibcon#read 4, iclass 21, count 0 2006.169.08:28:07.43#ibcon#about to read 5, iclass 21, count 0 2006.169.08:28:07.43#ibcon#read 5, iclass 21, count 0 2006.169.08:28:07.43#ibcon#about to read 6, iclass 21, count 0 2006.169.08:28:07.43#ibcon#read 6, iclass 21, count 0 2006.169.08:28:07.43#ibcon#end of sib2, iclass 21, count 0 2006.169.08:28:07.43#ibcon#*mode == 0, iclass 21, count 0 2006.169.08:28:07.43#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.169.08:28:07.43#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.08:28:07.43#ibcon#*before write, iclass 21, count 0 2006.169.08:28:07.43#ibcon#enter sib2, iclass 21, count 0 2006.169.08:28:07.43#ibcon#flushed, iclass 21, count 0 2006.169.08:28:07.43#ibcon#about to write, iclass 21, count 0 2006.169.08:28:07.43#ibcon#wrote, iclass 21, count 0 2006.169.08:28:07.43#ibcon#about to read 3, iclass 21, count 0 2006.169.08:28:07.47#ibcon#read 3, iclass 21, count 0 2006.169.08:28:07.47#ibcon#about to read 4, iclass 21, count 0 2006.169.08:28:07.47#ibcon#read 4, iclass 21, count 0 2006.169.08:28:07.47#ibcon#about to read 5, iclass 21, count 0 2006.169.08:28:07.47#ibcon#read 5, iclass 21, count 0 2006.169.08:28:07.47#ibcon#about to read 6, iclass 21, count 0 2006.169.08:28:07.47#ibcon#read 6, iclass 21, count 0 2006.169.08:28:07.47#ibcon#end of sib2, iclass 21, count 0 2006.169.08:28:07.47#ibcon#*after write, iclass 21, count 0 2006.169.08:28:07.47#ibcon#*before return 0, iclass 21, count 0 2006.169.08:28:07.47#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.169.08:28:07.47#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.169.08:28:07.47#ibcon#about to clear, iclass 21 cls_cnt 0 2006.169.08:28:07.47#ibcon#cleared, iclass 21 cls_cnt 0 2006.169.08:28:07.47$vc4f8/vb=1,4 2006.169.08:28:07.47#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.169.08:28:07.47#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.169.08:28:07.47#ibcon#ireg 11 cls_cnt 2 2006.169.08:28:07.47#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.169.08:28:07.47#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.169.08:28:07.47#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.169.08:28:07.47#ibcon#enter wrdev, iclass 23, count 2 2006.169.08:28:07.47#ibcon#first serial, iclass 23, count 2 2006.169.08:28:07.47#ibcon#enter sib2, iclass 23, count 2 2006.169.08:28:07.47#ibcon#flushed, iclass 23, count 2 2006.169.08:28:07.47#ibcon#about to write, iclass 23, count 2 2006.169.08:28:07.47#ibcon#wrote, iclass 23, count 2 2006.169.08:28:07.47#ibcon#about to read 3, iclass 23, count 2 2006.169.08:28:07.49#ibcon#read 3, iclass 23, count 2 2006.169.08:28:07.49#ibcon#about to read 4, iclass 23, count 2 2006.169.08:28:07.49#ibcon#read 4, iclass 23, count 2 2006.169.08:28:07.49#ibcon#about to read 5, iclass 23, count 2 2006.169.08:28:07.49#ibcon#read 5, iclass 23, count 2 2006.169.08:28:07.49#ibcon#about to read 6, iclass 23, count 2 2006.169.08:28:07.49#ibcon#read 6, iclass 23, count 2 2006.169.08:28:07.49#ibcon#end of sib2, iclass 23, count 2 2006.169.08:28:07.49#ibcon#*mode == 0, iclass 23, count 2 2006.169.08:28:07.49#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.169.08:28:07.49#ibcon#[27=AT01-04\r\n] 2006.169.08:28:07.49#ibcon#*before write, iclass 23, count 2 2006.169.08:28:07.49#ibcon#enter sib2, iclass 23, count 2 2006.169.08:28:07.49#ibcon#flushed, iclass 23, count 2 2006.169.08:28:07.49#ibcon#about to write, iclass 23, count 2 2006.169.08:28:07.49#ibcon#wrote, iclass 23, count 2 2006.169.08:28:07.49#ibcon#about to read 3, iclass 23, count 2 2006.169.08:28:07.52#ibcon#read 3, iclass 23, count 2 2006.169.08:28:07.52#ibcon#about to read 4, iclass 23, count 2 2006.169.08:28:07.52#ibcon#read 4, iclass 23, count 2 2006.169.08:28:07.52#ibcon#about to read 5, iclass 23, count 2 2006.169.08:28:07.52#ibcon#read 5, iclass 23, count 2 2006.169.08:28:07.52#ibcon#about to read 6, iclass 23, count 2 2006.169.08:28:07.52#ibcon#read 6, iclass 23, count 2 2006.169.08:28:07.52#ibcon#end of sib2, iclass 23, count 2 2006.169.08:28:07.52#ibcon#*after write, iclass 23, count 2 2006.169.08:28:07.52#ibcon#*before return 0, iclass 23, count 2 2006.169.08:28:07.52#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.169.08:28:07.52#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.169.08:28:07.52#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.169.08:28:07.52#ibcon#ireg 7 cls_cnt 0 2006.169.08:28:07.52#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.169.08:28:07.64#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.169.08:28:07.64#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.169.08:28:07.64#ibcon#enter wrdev, iclass 23, count 0 2006.169.08:28:07.64#ibcon#first serial, iclass 23, count 0 2006.169.08:28:07.64#ibcon#enter sib2, iclass 23, count 0 2006.169.08:28:07.64#ibcon#flushed, iclass 23, count 0 2006.169.08:28:07.64#ibcon#about to write, iclass 23, count 0 2006.169.08:28:07.64#ibcon#wrote, iclass 23, count 0 2006.169.08:28:07.64#ibcon#about to read 3, iclass 23, count 0 2006.169.08:28:07.66#ibcon#read 3, iclass 23, count 0 2006.169.08:28:07.66#ibcon#about to read 4, iclass 23, count 0 2006.169.08:28:07.66#ibcon#read 4, iclass 23, count 0 2006.169.08:28:07.66#ibcon#about to read 5, iclass 23, count 0 2006.169.08:28:07.66#ibcon#read 5, iclass 23, count 0 2006.169.08:28:07.66#ibcon#about to read 6, iclass 23, count 0 2006.169.08:28:07.66#ibcon#read 6, iclass 23, count 0 2006.169.08:28:07.66#ibcon#end of sib2, iclass 23, count 0 2006.169.08:28:07.66#ibcon#*mode == 0, iclass 23, count 0 2006.169.08:28:07.66#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.169.08:28:07.66#ibcon#[27=USB\r\n] 2006.169.08:28:07.66#ibcon#*before write, iclass 23, count 0 2006.169.08:28:07.66#ibcon#enter sib2, iclass 23, count 0 2006.169.08:28:07.66#ibcon#flushed, iclass 23, count 0 2006.169.08:28:07.66#ibcon#about to write, iclass 23, count 0 2006.169.08:28:07.66#ibcon#wrote, iclass 23, count 0 2006.169.08:28:07.66#ibcon#about to read 3, iclass 23, count 0 2006.169.08:28:07.69#ibcon#read 3, iclass 23, count 0 2006.169.08:28:07.69#ibcon#about to read 4, iclass 23, count 0 2006.169.08:28:07.69#ibcon#read 4, iclass 23, count 0 2006.169.08:28:07.69#ibcon#about to read 5, iclass 23, count 0 2006.169.08:28:07.69#ibcon#read 5, iclass 23, count 0 2006.169.08:28:07.69#ibcon#about to read 6, iclass 23, count 0 2006.169.08:28:07.69#ibcon#read 6, iclass 23, count 0 2006.169.08:28:07.69#ibcon#end of sib2, iclass 23, count 0 2006.169.08:28:07.69#ibcon#*after write, iclass 23, count 0 2006.169.08:28:07.69#ibcon#*before return 0, iclass 23, count 0 2006.169.08:28:07.69#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.169.08:28:07.69#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.169.08:28:07.69#ibcon#about to clear, iclass 23 cls_cnt 0 2006.169.08:28:07.69#ibcon#cleared, iclass 23 cls_cnt 0 2006.169.08:28:07.69$vc4f8/vblo=2,640.99 2006.169.08:28:07.69#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.169.08:28:07.69#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.169.08:28:07.69#ibcon#ireg 17 cls_cnt 0 2006.169.08:28:07.69#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.169.08:28:07.69#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.169.08:28:07.69#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.169.08:28:07.69#ibcon#enter wrdev, iclass 25, count 0 2006.169.08:28:07.69#ibcon#first serial, iclass 25, count 0 2006.169.08:28:07.69#ibcon#enter sib2, iclass 25, count 0 2006.169.08:28:07.69#ibcon#flushed, iclass 25, count 0 2006.169.08:28:07.69#ibcon#about to write, iclass 25, count 0 2006.169.08:28:07.69#ibcon#wrote, iclass 25, count 0 2006.169.08:28:07.69#ibcon#about to read 3, iclass 25, count 0 2006.169.08:28:07.71#ibcon#read 3, iclass 25, count 0 2006.169.08:28:07.71#ibcon#about to read 4, iclass 25, count 0 2006.169.08:28:07.71#ibcon#read 4, iclass 25, count 0 2006.169.08:28:07.71#ibcon#about to read 5, iclass 25, count 0 2006.169.08:28:07.71#ibcon#read 5, iclass 25, count 0 2006.169.08:28:07.71#ibcon#about to read 6, iclass 25, count 0 2006.169.08:28:07.71#ibcon#read 6, iclass 25, count 0 2006.169.08:28:07.71#ibcon#end of sib2, iclass 25, count 0 2006.169.08:28:07.71#ibcon#*mode == 0, iclass 25, count 0 2006.169.08:28:07.71#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.169.08:28:07.71#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.08:28:07.71#ibcon#*before write, iclass 25, count 0 2006.169.08:28:07.71#ibcon#enter sib2, iclass 25, count 0 2006.169.08:28:07.71#ibcon#flushed, iclass 25, count 0 2006.169.08:28:07.71#ibcon#about to write, iclass 25, count 0 2006.169.08:28:07.71#ibcon#wrote, iclass 25, count 0 2006.169.08:28:07.71#ibcon#about to read 3, iclass 25, count 0 2006.169.08:28:07.75#ibcon#read 3, iclass 25, count 0 2006.169.08:28:07.75#ibcon#about to read 4, iclass 25, count 0 2006.169.08:28:07.75#ibcon#read 4, iclass 25, count 0 2006.169.08:28:07.75#ibcon#about to read 5, iclass 25, count 0 2006.169.08:28:07.75#ibcon#read 5, iclass 25, count 0 2006.169.08:28:07.75#ibcon#about to read 6, iclass 25, count 0 2006.169.08:28:07.75#ibcon#read 6, iclass 25, count 0 2006.169.08:28:07.75#ibcon#end of sib2, iclass 25, count 0 2006.169.08:28:07.75#ibcon#*after write, iclass 25, count 0 2006.169.08:28:07.75#ibcon#*before return 0, iclass 25, count 0 2006.169.08:28:07.75#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.169.08:28:07.75#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.169.08:28:07.75#ibcon#about to clear, iclass 25 cls_cnt 0 2006.169.08:28:07.75#ibcon#cleared, iclass 25 cls_cnt 0 2006.169.08:28:07.75$vc4f8/vb=2,4 2006.169.08:28:07.75#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.169.08:28:07.75#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.169.08:28:07.75#ibcon#ireg 11 cls_cnt 2 2006.169.08:28:07.75#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.169.08:28:07.81#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.169.08:28:07.81#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.169.08:28:07.81#ibcon#enter wrdev, iclass 27, count 2 2006.169.08:28:07.81#ibcon#first serial, iclass 27, count 2 2006.169.08:28:07.81#ibcon#enter sib2, iclass 27, count 2 2006.169.08:28:07.81#ibcon#flushed, iclass 27, count 2 2006.169.08:28:07.81#ibcon#about to write, iclass 27, count 2 2006.169.08:28:07.81#ibcon#wrote, iclass 27, count 2 2006.169.08:28:07.81#ibcon#about to read 3, iclass 27, count 2 2006.169.08:28:07.83#ibcon#read 3, iclass 27, count 2 2006.169.08:28:07.83#ibcon#about to read 4, iclass 27, count 2 2006.169.08:28:07.83#ibcon#read 4, iclass 27, count 2 2006.169.08:28:07.83#ibcon#about to read 5, iclass 27, count 2 2006.169.08:28:07.83#ibcon#read 5, iclass 27, count 2 2006.169.08:28:07.83#ibcon#about to read 6, iclass 27, count 2 2006.169.08:28:07.83#ibcon#read 6, iclass 27, count 2 2006.169.08:28:07.83#ibcon#end of sib2, iclass 27, count 2 2006.169.08:28:07.83#ibcon#*mode == 0, iclass 27, count 2 2006.169.08:28:07.83#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.169.08:28:07.83#ibcon#[27=AT02-04\r\n] 2006.169.08:28:07.83#ibcon#*before write, iclass 27, count 2 2006.169.08:28:07.83#ibcon#enter sib2, iclass 27, count 2 2006.169.08:28:07.83#ibcon#flushed, iclass 27, count 2 2006.169.08:28:07.83#ibcon#about to write, iclass 27, count 2 2006.169.08:28:07.83#ibcon#wrote, iclass 27, count 2 2006.169.08:28:07.83#ibcon#about to read 3, iclass 27, count 2 2006.169.08:28:07.86#ibcon#read 3, iclass 27, count 2 2006.169.08:28:07.86#ibcon#about to read 4, iclass 27, count 2 2006.169.08:28:07.86#ibcon#read 4, iclass 27, count 2 2006.169.08:28:07.86#ibcon#about to read 5, iclass 27, count 2 2006.169.08:28:07.86#ibcon#read 5, iclass 27, count 2 2006.169.08:28:07.86#ibcon#about to read 6, iclass 27, count 2 2006.169.08:28:07.86#ibcon#read 6, iclass 27, count 2 2006.169.08:28:07.86#ibcon#end of sib2, iclass 27, count 2 2006.169.08:28:07.86#ibcon#*after write, iclass 27, count 2 2006.169.08:28:07.86#ibcon#*before return 0, iclass 27, count 2 2006.169.08:28:07.86#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.169.08:28:07.86#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.169.08:28:07.86#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.169.08:28:07.86#ibcon#ireg 7 cls_cnt 0 2006.169.08:28:07.86#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.169.08:28:07.98#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.169.08:28:07.98#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.169.08:28:07.98#ibcon#enter wrdev, iclass 27, count 0 2006.169.08:28:07.98#ibcon#first serial, iclass 27, count 0 2006.169.08:28:07.98#ibcon#enter sib2, iclass 27, count 0 2006.169.08:28:07.98#ibcon#flushed, iclass 27, count 0 2006.169.08:28:07.98#ibcon#about to write, iclass 27, count 0 2006.169.08:28:07.98#ibcon#wrote, iclass 27, count 0 2006.169.08:28:07.98#ibcon#about to read 3, iclass 27, count 0 2006.169.08:28:08.00#ibcon#read 3, iclass 27, count 0 2006.169.08:28:08.00#ibcon#about to read 4, iclass 27, count 0 2006.169.08:28:08.00#ibcon#read 4, iclass 27, count 0 2006.169.08:28:08.00#ibcon#about to read 5, iclass 27, count 0 2006.169.08:28:08.00#ibcon#read 5, iclass 27, count 0 2006.169.08:28:08.00#ibcon#about to read 6, iclass 27, count 0 2006.169.08:28:08.00#ibcon#read 6, iclass 27, count 0 2006.169.08:28:08.00#ibcon#end of sib2, iclass 27, count 0 2006.169.08:28:08.00#ibcon#*mode == 0, iclass 27, count 0 2006.169.08:28:08.00#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.169.08:28:08.00#ibcon#[27=USB\r\n] 2006.169.08:28:08.00#ibcon#*before write, iclass 27, count 0 2006.169.08:28:08.00#ibcon#enter sib2, iclass 27, count 0 2006.169.08:28:08.00#ibcon#flushed, iclass 27, count 0 2006.169.08:28:08.00#ibcon#about to write, iclass 27, count 0 2006.169.08:28:08.00#ibcon#wrote, iclass 27, count 0 2006.169.08:28:08.00#ibcon#about to read 3, iclass 27, count 0 2006.169.08:28:08.03#ibcon#read 3, iclass 27, count 0 2006.169.08:28:08.03#ibcon#about to read 4, iclass 27, count 0 2006.169.08:28:08.03#ibcon#read 4, iclass 27, count 0 2006.169.08:28:08.03#ibcon#about to read 5, iclass 27, count 0 2006.169.08:28:08.03#ibcon#read 5, iclass 27, count 0 2006.169.08:28:08.03#ibcon#about to read 6, iclass 27, count 0 2006.169.08:28:08.03#ibcon#read 6, iclass 27, count 0 2006.169.08:28:08.03#ibcon#end of sib2, iclass 27, count 0 2006.169.08:28:08.03#ibcon#*after write, iclass 27, count 0 2006.169.08:28:08.03#ibcon#*before return 0, iclass 27, count 0 2006.169.08:28:08.03#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.169.08:28:08.03#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.169.08:28:08.03#ibcon#about to clear, iclass 27 cls_cnt 0 2006.169.08:28:08.03#ibcon#cleared, iclass 27 cls_cnt 0 2006.169.08:28:08.03$vc4f8/vblo=3,656.99 2006.169.08:28:08.03#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.169.08:28:08.03#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.169.08:28:08.03#ibcon#ireg 17 cls_cnt 0 2006.169.08:28:08.03#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.169.08:28:08.03#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.169.08:28:08.03#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.169.08:28:08.03#ibcon#enter wrdev, iclass 29, count 0 2006.169.08:28:08.03#ibcon#first serial, iclass 29, count 0 2006.169.08:28:08.03#ibcon#enter sib2, iclass 29, count 0 2006.169.08:28:08.03#ibcon#flushed, iclass 29, count 0 2006.169.08:28:08.03#ibcon#about to write, iclass 29, count 0 2006.169.08:28:08.03#ibcon#wrote, iclass 29, count 0 2006.169.08:28:08.03#ibcon#about to read 3, iclass 29, count 0 2006.169.08:28:08.05#ibcon#read 3, iclass 29, count 0 2006.169.08:28:08.05#ibcon#about to read 4, iclass 29, count 0 2006.169.08:28:08.05#ibcon#read 4, iclass 29, count 0 2006.169.08:28:08.05#ibcon#about to read 5, iclass 29, count 0 2006.169.08:28:08.05#ibcon#read 5, iclass 29, count 0 2006.169.08:28:08.05#ibcon#about to read 6, iclass 29, count 0 2006.169.08:28:08.05#ibcon#read 6, iclass 29, count 0 2006.169.08:28:08.05#ibcon#end of sib2, iclass 29, count 0 2006.169.08:28:08.05#ibcon#*mode == 0, iclass 29, count 0 2006.169.08:28:08.05#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.169.08:28:08.05#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.08:28:08.05#ibcon#*before write, iclass 29, count 0 2006.169.08:28:08.05#ibcon#enter sib2, iclass 29, count 0 2006.169.08:28:08.05#ibcon#flushed, iclass 29, count 0 2006.169.08:28:08.05#ibcon#about to write, iclass 29, count 0 2006.169.08:28:08.05#ibcon#wrote, iclass 29, count 0 2006.169.08:28:08.05#ibcon#about to read 3, iclass 29, count 0 2006.169.08:28:08.09#ibcon#read 3, iclass 29, count 0 2006.169.08:28:08.09#ibcon#about to read 4, iclass 29, count 0 2006.169.08:28:08.09#ibcon#read 4, iclass 29, count 0 2006.169.08:28:08.09#ibcon#about to read 5, iclass 29, count 0 2006.169.08:28:08.09#ibcon#read 5, iclass 29, count 0 2006.169.08:28:08.09#ibcon#about to read 6, iclass 29, count 0 2006.169.08:28:08.09#ibcon#read 6, iclass 29, count 0 2006.169.08:28:08.09#ibcon#end of sib2, iclass 29, count 0 2006.169.08:28:08.09#ibcon#*after write, iclass 29, count 0 2006.169.08:28:08.09#ibcon#*before return 0, iclass 29, count 0 2006.169.08:28:08.09#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.169.08:28:08.09#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.169.08:28:08.09#ibcon#about to clear, iclass 29 cls_cnt 0 2006.169.08:28:08.09#ibcon#cleared, iclass 29 cls_cnt 0 2006.169.08:28:08.09$vc4f8/vb=3,4 2006.169.08:28:08.09#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.169.08:28:08.09#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.169.08:28:08.09#ibcon#ireg 11 cls_cnt 2 2006.169.08:28:08.09#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.169.08:28:08.15#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.169.08:28:08.15#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.169.08:28:08.15#ibcon#enter wrdev, iclass 31, count 2 2006.169.08:28:08.15#ibcon#first serial, iclass 31, count 2 2006.169.08:28:08.15#ibcon#enter sib2, iclass 31, count 2 2006.169.08:28:08.15#ibcon#flushed, iclass 31, count 2 2006.169.08:28:08.15#ibcon#about to write, iclass 31, count 2 2006.169.08:28:08.15#ibcon#wrote, iclass 31, count 2 2006.169.08:28:08.15#ibcon#about to read 3, iclass 31, count 2 2006.169.08:28:08.17#ibcon#read 3, iclass 31, count 2 2006.169.08:28:08.17#ibcon#about to read 4, iclass 31, count 2 2006.169.08:28:08.17#ibcon#read 4, iclass 31, count 2 2006.169.08:28:08.17#ibcon#about to read 5, iclass 31, count 2 2006.169.08:28:08.17#ibcon#read 5, iclass 31, count 2 2006.169.08:28:08.17#ibcon#about to read 6, iclass 31, count 2 2006.169.08:28:08.17#ibcon#read 6, iclass 31, count 2 2006.169.08:28:08.17#ibcon#end of sib2, iclass 31, count 2 2006.169.08:28:08.17#ibcon#*mode == 0, iclass 31, count 2 2006.169.08:28:08.17#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.169.08:28:08.17#ibcon#[27=AT03-04\r\n] 2006.169.08:28:08.17#ibcon#*before write, iclass 31, count 2 2006.169.08:28:08.17#ibcon#enter sib2, iclass 31, count 2 2006.169.08:28:08.17#ibcon#flushed, iclass 31, count 2 2006.169.08:28:08.17#ibcon#about to write, iclass 31, count 2 2006.169.08:28:08.17#ibcon#wrote, iclass 31, count 2 2006.169.08:28:08.17#ibcon#about to read 3, iclass 31, count 2 2006.169.08:28:08.20#ibcon#read 3, iclass 31, count 2 2006.169.08:28:08.20#ibcon#about to read 4, iclass 31, count 2 2006.169.08:28:08.20#ibcon#read 4, iclass 31, count 2 2006.169.08:28:08.20#ibcon#about to read 5, iclass 31, count 2 2006.169.08:28:08.20#ibcon#read 5, iclass 31, count 2 2006.169.08:28:08.20#ibcon#about to read 6, iclass 31, count 2 2006.169.08:28:08.20#ibcon#read 6, iclass 31, count 2 2006.169.08:28:08.20#ibcon#end of sib2, iclass 31, count 2 2006.169.08:28:08.20#ibcon#*after write, iclass 31, count 2 2006.169.08:28:08.20#ibcon#*before return 0, iclass 31, count 2 2006.169.08:28:08.20#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.169.08:28:08.20#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.169.08:28:08.20#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.169.08:28:08.20#ibcon#ireg 7 cls_cnt 0 2006.169.08:28:08.20#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.169.08:28:08.32#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.169.08:28:08.32#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.169.08:28:08.32#ibcon#enter wrdev, iclass 31, count 0 2006.169.08:28:08.32#ibcon#first serial, iclass 31, count 0 2006.169.08:28:08.32#ibcon#enter sib2, iclass 31, count 0 2006.169.08:28:08.32#ibcon#flushed, iclass 31, count 0 2006.169.08:28:08.32#ibcon#about to write, iclass 31, count 0 2006.169.08:28:08.32#ibcon#wrote, iclass 31, count 0 2006.169.08:28:08.32#ibcon#about to read 3, iclass 31, count 0 2006.169.08:28:08.34#ibcon#read 3, iclass 31, count 0 2006.169.08:28:08.34#ibcon#about to read 4, iclass 31, count 0 2006.169.08:28:08.34#ibcon#read 4, iclass 31, count 0 2006.169.08:28:08.34#ibcon#about to read 5, iclass 31, count 0 2006.169.08:28:08.34#ibcon#read 5, iclass 31, count 0 2006.169.08:28:08.34#ibcon#about to read 6, iclass 31, count 0 2006.169.08:28:08.34#ibcon#read 6, iclass 31, count 0 2006.169.08:28:08.34#ibcon#end of sib2, iclass 31, count 0 2006.169.08:28:08.34#ibcon#*mode == 0, iclass 31, count 0 2006.169.08:28:08.34#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.169.08:28:08.34#ibcon#[27=USB\r\n] 2006.169.08:28:08.34#ibcon#*before write, iclass 31, count 0 2006.169.08:28:08.34#ibcon#enter sib2, iclass 31, count 0 2006.169.08:28:08.34#ibcon#flushed, iclass 31, count 0 2006.169.08:28:08.34#ibcon#about to write, iclass 31, count 0 2006.169.08:28:08.34#ibcon#wrote, iclass 31, count 0 2006.169.08:28:08.34#ibcon#about to read 3, iclass 31, count 0 2006.169.08:28:08.37#ibcon#read 3, iclass 31, count 0 2006.169.08:28:08.37#ibcon#about to read 4, iclass 31, count 0 2006.169.08:28:08.37#ibcon#read 4, iclass 31, count 0 2006.169.08:28:08.37#ibcon#about to read 5, iclass 31, count 0 2006.169.08:28:08.37#ibcon#read 5, iclass 31, count 0 2006.169.08:28:08.37#ibcon#about to read 6, iclass 31, count 0 2006.169.08:28:08.37#ibcon#read 6, iclass 31, count 0 2006.169.08:28:08.37#ibcon#end of sib2, iclass 31, count 0 2006.169.08:28:08.37#ibcon#*after write, iclass 31, count 0 2006.169.08:28:08.37#ibcon#*before return 0, iclass 31, count 0 2006.169.08:28:08.37#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.169.08:28:08.37#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.169.08:28:08.37#ibcon#about to clear, iclass 31 cls_cnt 0 2006.169.08:28:08.37#ibcon#cleared, iclass 31 cls_cnt 0 2006.169.08:28:08.37$vc4f8/vblo=4,712.99 2006.169.08:28:08.37#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.169.08:28:08.37#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.169.08:28:08.37#ibcon#ireg 17 cls_cnt 0 2006.169.08:28:08.37#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:28:08.37#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:28:08.37#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:28:08.37#ibcon#enter wrdev, iclass 33, count 0 2006.169.08:28:08.37#ibcon#first serial, iclass 33, count 0 2006.169.08:28:08.37#ibcon#enter sib2, iclass 33, count 0 2006.169.08:28:08.37#ibcon#flushed, iclass 33, count 0 2006.169.08:28:08.37#ibcon#about to write, iclass 33, count 0 2006.169.08:28:08.37#ibcon#wrote, iclass 33, count 0 2006.169.08:28:08.37#ibcon#about to read 3, iclass 33, count 0 2006.169.08:28:08.39#ibcon#read 3, iclass 33, count 0 2006.169.08:28:08.39#ibcon#about to read 4, iclass 33, count 0 2006.169.08:28:08.39#ibcon#read 4, iclass 33, count 0 2006.169.08:28:08.39#ibcon#about to read 5, iclass 33, count 0 2006.169.08:28:08.39#ibcon#read 5, iclass 33, count 0 2006.169.08:28:08.39#ibcon#about to read 6, iclass 33, count 0 2006.169.08:28:08.39#ibcon#read 6, iclass 33, count 0 2006.169.08:28:08.39#ibcon#end of sib2, iclass 33, count 0 2006.169.08:28:08.39#ibcon#*mode == 0, iclass 33, count 0 2006.169.08:28:08.39#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.169.08:28:08.39#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.08:28:08.39#ibcon#*before write, iclass 33, count 0 2006.169.08:28:08.39#ibcon#enter sib2, iclass 33, count 0 2006.169.08:28:08.39#ibcon#flushed, iclass 33, count 0 2006.169.08:28:08.39#ibcon#about to write, iclass 33, count 0 2006.169.08:28:08.39#ibcon#wrote, iclass 33, count 0 2006.169.08:28:08.39#ibcon#about to read 3, iclass 33, count 0 2006.169.08:28:08.43#ibcon#read 3, iclass 33, count 0 2006.169.08:28:08.43#ibcon#about to read 4, iclass 33, count 0 2006.169.08:28:08.43#ibcon#read 4, iclass 33, count 0 2006.169.08:28:08.43#ibcon#about to read 5, iclass 33, count 0 2006.169.08:28:08.43#ibcon#read 5, iclass 33, count 0 2006.169.08:28:08.43#ibcon#about to read 6, iclass 33, count 0 2006.169.08:28:08.43#ibcon#read 6, iclass 33, count 0 2006.169.08:28:08.43#ibcon#end of sib2, iclass 33, count 0 2006.169.08:28:08.43#ibcon#*after write, iclass 33, count 0 2006.169.08:28:08.43#ibcon#*before return 0, iclass 33, count 0 2006.169.08:28:08.43#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:28:08.43#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.169.08:28:08.43#ibcon#about to clear, iclass 33 cls_cnt 0 2006.169.08:28:08.43#ibcon#cleared, iclass 33 cls_cnt 0 2006.169.08:28:08.43$vc4f8/vb=4,4 2006.169.08:28:08.43#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.169.08:28:08.43#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.169.08:28:08.43#ibcon#ireg 11 cls_cnt 2 2006.169.08:28:08.43#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.169.08:28:08.49#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.169.08:28:08.49#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.169.08:28:08.49#ibcon#enter wrdev, iclass 35, count 2 2006.169.08:28:08.49#ibcon#first serial, iclass 35, count 2 2006.169.08:28:08.49#ibcon#enter sib2, iclass 35, count 2 2006.169.08:28:08.49#ibcon#flushed, iclass 35, count 2 2006.169.08:28:08.49#ibcon#about to write, iclass 35, count 2 2006.169.08:28:08.49#ibcon#wrote, iclass 35, count 2 2006.169.08:28:08.49#ibcon#about to read 3, iclass 35, count 2 2006.169.08:28:08.51#ibcon#read 3, iclass 35, count 2 2006.169.08:28:08.51#ibcon#about to read 4, iclass 35, count 2 2006.169.08:28:08.51#ibcon#read 4, iclass 35, count 2 2006.169.08:28:08.51#ibcon#about to read 5, iclass 35, count 2 2006.169.08:28:08.51#ibcon#read 5, iclass 35, count 2 2006.169.08:28:08.51#ibcon#about to read 6, iclass 35, count 2 2006.169.08:28:08.51#ibcon#read 6, iclass 35, count 2 2006.169.08:28:08.51#ibcon#end of sib2, iclass 35, count 2 2006.169.08:28:08.51#ibcon#*mode == 0, iclass 35, count 2 2006.169.08:28:08.51#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.169.08:28:08.51#ibcon#[27=AT04-04\r\n] 2006.169.08:28:08.51#ibcon#*before write, iclass 35, count 2 2006.169.08:28:08.51#ibcon#enter sib2, iclass 35, count 2 2006.169.08:28:08.51#ibcon#flushed, iclass 35, count 2 2006.169.08:28:08.51#ibcon#about to write, iclass 35, count 2 2006.169.08:28:08.51#ibcon#wrote, iclass 35, count 2 2006.169.08:28:08.51#ibcon#about to read 3, iclass 35, count 2 2006.169.08:28:08.54#ibcon#read 3, iclass 35, count 2 2006.169.08:28:08.54#ibcon#about to read 4, iclass 35, count 2 2006.169.08:28:08.54#ibcon#read 4, iclass 35, count 2 2006.169.08:28:08.54#ibcon#about to read 5, iclass 35, count 2 2006.169.08:28:08.54#ibcon#read 5, iclass 35, count 2 2006.169.08:28:08.54#ibcon#about to read 6, iclass 35, count 2 2006.169.08:28:08.54#ibcon#read 6, iclass 35, count 2 2006.169.08:28:08.54#ibcon#end of sib2, iclass 35, count 2 2006.169.08:28:08.54#ibcon#*after write, iclass 35, count 2 2006.169.08:28:08.54#ibcon#*before return 0, iclass 35, count 2 2006.169.08:28:08.54#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.169.08:28:08.54#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.169.08:28:08.54#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.169.08:28:08.54#ibcon#ireg 7 cls_cnt 0 2006.169.08:28:08.54#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.169.08:28:08.66#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.169.08:28:08.66#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.169.08:28:08.66#ibcon#enter wrdev, iclass 35, count 0 2006.169.08:28:08.66#ibcon#first serial, iclass 35, count 0 2006.169.08:28:08.66#ibcon#enter sib2, iclass 35, count 0 2006.169.08:28:08.66#ibcon#flushed, iclass 35, count 0 2006.169.08:28:08.66#ibcon#about to write, iclass 35, count 0 2006.169.08:28:08.66#ibcon#wrote, iclass 35, count 0 2006.169.08:28:08.66#ibcon#about to read 3, iclass 35, count 0 2006.169.08:28:08.68#ibcon#read 3, iclass 35, count 0 2006.169.08:28:08.68#ibcon#about to read 4, iclass 35, count 0 2006.169.08:28:08.68#ibcon#read 4, iclass 35, count 0 2006.169.08:28:08.68#ibcon#about to read 5, iclass 35, count 0 2006.169.08:28:08.68#ibcon#read 5, iclass 35, count 0 2006.169.08:28:08.68#ibcon#about to read 6, iclass 35, count 0 2006.169.08:28:08.68#ibcon#read 6, iclass 35, count 0 2006.169.08:28:08.68#ibcon#end of sib2, iclass 35, count 0 2006.169.08:28:08.68#ibcon#*mode == 0, iclass 35, count 0 2006.169.08:28:08.68#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.169.08:28:08.68#ibcon#[27=USB\r\n] 2006.169.08:28:08.68#ibcon#*before write, iclass 35, count 0 2006.169.08:28:08.68#ibcon#enter sib2, iclass 35, count 0 2006.169.08:28:08.68#ibcon#flushed, iclass 35, count 0 2006.169.08:28:08.68#ibcon#about to write, iclass 35, count 0 2006.169.08:28:08.68#ibcon#wrote, iclass 35, count 0 2006.169.08:28:08.68#ibcon#about to read 3, iclass 35, count 0 2006.169.08:28:08.71#ibcon#read 3, iclass 35, count 0 2006.169.08:28:08.71#ibcon#about to read 4, iclass 35, count 0 2006.169.08:28:08.71#ibcon#read 4, iclass 35, count 0 2006.169.08:28:08.71#ibcon#about to read 5, iclass 35, count 0 2006.169.08:28:08.71#ibcon#read 5, iclass 35, count 0 2006.169.08:28:08.71#ibcon#about to read 6, iclass 35, count 0 2006.169.08:28:08.71#ibcon#read 6, iclass 35, count 0 2006.169.08:28:08.71#ibcon#end of sib2, iclass 35, count 0 2006.169.08:28:08.71#ibcon#*after write, iclass 35, count 0 2006.169.08:28:08.71#ibcon#*before return 0, iclass 35, count 0 2006.169.08:28:08.71#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.169.08:28:08.71#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.169.08:28:08.71#ibcon#about to clear, iclass 35 cls_cnt 0 2006.169.08:28:08.71#ibcon#cleared, iclass 35 cls_cnt 0 2006.169.08:28:08.71$vc4f8/vblo=5,744.99 2006.169.08:28:08.71#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.169.08:28:08.71#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.169.08:28:08.71#ibcon#ireg 17 cls_cnt 0 2006.169.08:28:08.71#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:28:08.71#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:28:08.71#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:28:08.71#ibcon#enter wrdev, iclass 37, count 0 2006.169.08:28:08.71#ibcon#first serial, iclass 37, count 0 2006.169.08:28:08.71#ibcon#enter sib2, iclass 37, count 0 2006.169.08:28:08.71#ibcon#flushed, iclass 37, count 0 2006.169.08:28:08.71#ibcon#about to write, iclass 37, count 0 2006.169.08:28:08.71#ibcon#wrote, iclass 37, count 0 2006.169.08:28:08.71#ibcon#about to read 3, iclass 37, count 0 2006.169.08:28:08.73#ibcon#read 3, iclass 37, count 0 2006.169.08:28:08.73#ibcon#about to read 4, iclass 37, count 0 2006.169.08:28:08.73#ibcon#read 4, iclass 37, count 0 2006.169.08:28:08.73#ibcon#about to read 5, iclass 37, count 0 2006.169.08:28:08.73#ibcon#read 5, iclass 37, count 0 2006.169.08:28:08.73#ibcon#about to read 6, iclass 37, count 0 2006.169.08:28:08.73#ibcon#read 6, iclass 37, count 0 2006.169.08:28:08.73#ibcon#end of sib2, iclass 37, count 0 2006.169.08:28:08.73#ibcon#*mode == 0, iclass 37, count 0 2006.169.08:28:08.73#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.169.08:28:08.73#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.08:28:08.73#ibcon#*before write, iclass 37, count 0 2006.169.08:28:08.73#ibcon#enter sib2, iclass 37, count 0 2006.169.08:28:08.73#ibcon#flushed, iclass 37, count 0 2006.169.08:28:08.73#ibcon#about to write, iclass 37, count 0 2006.169.08:28:08.73#ibcon#wrote, iclass 37, count 0 2006.169.08:28:08.73#ibcon#about to read 3, iclass 37, count 0 2006.169.08:28:08.77#ibcon#read 3, iclass 37, count 0 2006.169.08:28:08.77#ibcon#about to read 4, iclass 37, count 0 2006.169.08:28:08.77#ibcon#read 4, iclass 37, count 0 2006.169.08:28:08.77#ibcon#about to read 5, iclass 37, count 0 2006.169.08:28:08.77#ibcon#read 5, iclass 37, count 0 2006.169.08:28:08.77#ibcon#about to read 6, iclass 37, count 0 2006.169.08:28:08.77#ibcon#read 6, iclass 37, count 0 2006.169.08:28:08.77#ibcon#end of sib2, iclass 37, count 0 2006.169.08:28:08.77#ibcon#*after write, iclass 37, count 0 2006.169.08:28:08.77#ibcon#*before return 0, iclass 37, count 0 2006.169.08:28:08.77#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:28:08.77#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.169.08:28:08.77#ibcon#about to clear, iclass 37 cls_cnt 0 2006.169.08:28:08.77#ibcon#cleared, iclass 37 cls_cnt 0 2006.169.08:28:08.77$vc4f8/vb=5,4 2006.169.08:28:08.77#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.169.08:28:08.77#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.169.08:28:08.77#ibcon#ireg 11 cls_cnt 2 2006.169.08:28:08.77#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.169.08:28:08.83#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.169.08:28:08.83#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.169.08:28:08.83#ibcon#enter wrdev, iclass 39, count 2 2006.169.08:28:08.83#ibcon#first serial, iclass 39, count 2 2006.169.08:28:08.83#ibcon#enter sib2, iclass 39, count 2 2006.169.08:28:08.83#ibcon#flushed, iclass 39, count 2 2006.169.08:28:08.83#ibcon#about to write, iclass 39, count 2 2006.169.08:28:08.83#ibcon#wrote, iclass 39, count 2 2006.169.08:28:08.83#ibcon#about to read 3, iclass 39, count 2 2006.169.08:28:08.85#ibcon#read 3, iclass 39, count 2 2006.169.08:28:08.85#ibcon#about to read 4, iclass 39, count 2 2006.169.08:28:08.85#ibcon#read 4, iclass 39, count 2 2006.169.08:28:08.85#ibcon#about to read 5, iclass 39, count 2 2006.169.08:28:08.85#ibcon#read 5, iclass 39, count 2 2006.169.08:28:08.85#ibcon#about to read 6, iclass 39, count 2 2006.169.08:28:08.85#ibcon#read 6, iclass 39, count 2 2006.169.08:28:08.85#ibcon#end of sib2, iclass 39, count 2 2006.169.08:28:08.85#ibcon#*mode == 0, iclass 39, count 2 2006.169.08:28:08.85#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.169.08:28:08.85#ibcon#[27=AT05-04\r\n] 2006.169.08:28:08.85#ibcon#*before write, iclass 39, count 2 2006.169.08:28:08.85#ibcon#enter sib2, iclass 39, count 2 2006.169.08:28:08.85#ibcon#flushed, iclass 39, count 2 2006.169.08:28:08.85#ibcon#about to write, iclass 39, count 2 2006.169.08:28:08.85#ibcon#wrote, iclass 39, count 2 2006.169.08:28:08.85#ibcon#about to read 3, iclass 39, count 2 2006.169.08:28:08.88#ibcon#read 3, iclass 39, count 2 2006.169.08:28:08.88#ibcon#about to read 4, iclass 39, count 2 2006.169.08:28:08.88#ibcon#read 4, iclass 39, count 2 2006.169.08:28:08.88#ibcon#about to read 5, iclass 39, count 2 2006.169.08:28:08.88#ibcon#read 5, iclass 39, count 2 2006.169.08:28:08.88#ibcon#about to read 6, iclass 39, count 2 2006.169.08:28:08.88#ibcon#read 6, iclass 39, count 2 2006.169.08:28:08.88#ibcon#end of sib2, iclass 39, count 2 2006.169.08:28:08.88#ibcon#*after write, iclass 39, count 2 2006.169.08:28:08.88#ibcon#*before return 0, iclass 39, count 2 2006.169.08:28:08.88#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.169.08:28:08.88#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.169.08:28:08.88#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.169.08:28:08.88#ibcon#ireg 7 cls_cnt 0 2006.169.08:28:08.88#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.169.08:28:08.99#abcon#<5=/05 4.0 6.5 18.101001003.9\r\n> 2006.169.08:28:09.00#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.169.08:28:09.00#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.169.08:28:09.00#ibcon#enter wrdev, iclass 39, count 0 2006.169.08:28:09.00#ibcon#first serial, iclass 39, count 0 2006.169.08:28:09.00#ibcon#enter sib2, iclass 39, count 0 2006.169.08:28:09.00#ibcon#flushed, iclass 39, count 0 2006.169.08:28:09.00#ibcon#about to write, iclass 39, count 0 2006.169.08:28:09.00#ibcon#wrote, iclass 39, count 0 2006.169.08:28:09.00#ibcon#about to read 3, iclass 39, count 0 2006.169.08:28:09.01#abcon#{5=INTERFACE CLEAR} 2006.169.08:28:09.02#ibcon#read 3, iclass 39, count 0 2006.169.08:28:09.02#ibcon#about to read 4, iclass 39, count 0 2006.169.08:28:09.02#ibcon#read 4, iclass 39, count 0 2006.169.08:28:09.02#ibcon#about to read 5, iclass 39, count 0 2006.169.08:28:09.02#ibcon#read 5, iclass 39, count 0 2006.169.08:28:09.02#ibcon#about to read 6, iclass 39, count 0 2006.169.08:28:09.02#ibcon#read 6, iclass 39, count 0 2006.169.08:28:09.02#ibcon#end of sib2, iclass 39, count 0 2006.169.08:28:09.02#ibcon#*mode == 0, iclass 39, count 0 2006.169.08:28:09.02#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.169.08:28:09.02#ibcon#[27=USB\r\n] 2006.169.08:28:09.02#ibcon#*before write, iclass 39, count 0 2006.169.08:28:09.02#ibcon#enter sib2, iclass 39, count 0 2006.169.08:28:09.02#ibcon#flushed, iclass 39, count 0 2006.169.08:28:09.02#ibcon#about to write, iclass 39, count 0 2006.169.08:28:09.02#ibcon#wrote, iclass 39, count 0 2006.169.08:28:09.02#ibcon#about to read 3, iclass 39, count 0 2006.169.08:28:09.05#ibcon#read 3, iclass 39, count 0 2006.169.08:28:09.05#ibcon#about to read 4, iclass 39, count 0 2006.169.08:28:09.05#ibcon#read 4, iclass 39, count 0 2006.169.08:28:09.05#ibcon#about to read 5, iclass 39, count 0 2006.169.08:28:09.05#ibcon#read 5, iclass 39, count 0 2006.169.08:28:09.05#ibcon#about to read 6, iclass 39, count 0 2006.169.08:28:09.05#ibcon#read 6, iclass 39, count 0 2006.169.08:28:09.05#ibcon#end of sib2, iclass 39, count 0 2006.169.08:28:09.05#ibcon#*after write, iclass 39, count 0 2006.169.08:28:09.05#ibcon#*before return 0, iclass 39, count 0 2006.169.08:28:09.05#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.169.08:28:09.05#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.169.08:28:09.05#ibcon#about to clear, iclass 39 cls_cnt 0 2006.169.08:28:09.05#ibcon#cleared, iclass 39 cls_cnt 0 2006.169.08:28:09.05$vc4f8/vblo=6,752.99 2006.169.08:28:09.05#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.169.08:28:09.05#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.169.08:28:09.05#ibcon#ireg 17 cls_cnt 0 2006.169.08:28:09.05#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:28:09.05#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:28:09.05#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:28:09.05#ibcon#enter wrdev, iclass 6, count 0 2006.169.08:28:09.05#ibcon#first serial, iclass 6, count 0 2006.169.08:28:09.05#ibcon#enter sib2, iclass 6, count 0 2006.169.08:28:09.05#ibcon#flushed, iclass 6, count 0 2006.169.08:28:09.05#ibcon#about to write, iclass 6, count 0 2006.169.08:28:09.05#ibcon#wrote, iclass 6, count 0 2006.169.08:28:09.05#ibcon#about to read 3, iclass 6, count 0 2006.169.08:28:09.07#ibcon#read 3, iclass 6, count 0 2006.169.08:28:09.07#ibcon#about to read 4, iclass 6, count 0 2006.169.08:28:09.07#ibcon#read 4, iclass 6, count 0 2006.169.08:28:09.07#ibcon#about to read 5, iclass 6, count 0 2006.169.08:28:09.07#ibcon#read 5, iclass 6, count 0 2006.169.08:28:09.07#ibcon#about to read 6, iclass 6, count 0 2006.169.08:28:09.07#ibcon#read 6, iclass 6, count 0 2006.169.08:28:09.07#ibcon#end of sib2, iclass 6, count 0 2006.169.08:28:09.07#ibcon#*mode == 0, iclass 6, count 0 2006.169.08:28:09.07#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.169.08:28:09.07#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.08:28:09.07#ibcon#*before write, iclass 6, count 0 2006.169.08:28:09.07#ibcon#enter sib2, iclass 6, count 0 2006.169.08:28:09.07#ibcon#flushed, iclass 6, count 0 2006.169.08:28:09.07#ibcon#about to write, iclass 6, count 0 2006.169.08:28:09.07#ibcon#wrote, iclass 6, count 0 2006.169.08:28:09.07#ibcon#about to read 3, iclass 6, count 0 2006.169.08:28:09.07#abcon#[5=S1D000X0/0*\r\n] 2006.169.08:28:09.11#ibcon#read 3, iclass 6, count 0 2006.169.08:28:09.11#ibcon#about to read 4, iclass 6, count 0 2006.169.08:28:09.11#ibcon#read 4, iclass 6, count 0 2006.169.08:28:09.11#ibcon#about to read 5, iclass 6, count 0 2006.169.08:28:09.11#ibcon#read 5, iclass 6, count 0 2006.169.08:28:09.11#ibcon#about to read 6, iclass 6, count 0 2006.169.08:28:09.11#ibcon#read 6, iclass 6, count 0 2006.169.08:28:09.11#ibcon#end of sib2, iclass 6, count 0 2006.169.08:28:09.11#ibcon#*after write, iclass 6, count 0 2006.169.08:28:09.11#ibcon#*before return 0, iclass 6, count 0 2006.169.08:28:09.11#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:28:09.11#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:28:09.11#ibcon#about to clear, iclass 6 cls_cnt 0 2006.169.08:28:09.11#ibcon#cleared, iclass 6 cls_cnt 0 2006.169.08:28:09.11$vc4f8/vb=6,4 2006.169.08:28:09.11#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.169.08:28:09.11#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.169.08:28:09.11#ibcon#ireg 11 cls_cnt 2 2006.169.08:28:09.11#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.169.08:28:09.17#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.169.08:28:09.17#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.169.08:28:09.17#ibcon#enter wrdev, iclass 11, count 2 2006.169.08:28:09.17#ibcon#first serial, iclass 11, count 2 2006.169.08:28:09.17#ibcon#enter sib2, iclass 11, count 2 2006.169.08:28:09.17#ibcon#flushed, iclass 11, count 2 2006.169.08:28:09.17#ibcon#about to write, iclass 11, count 2 2006.169.08:28:09.17#ibcon#wrote, iclass 11, count 2 2006.169.08:28:09.17#ibcon#about to read 3, iclass 11, count 2 2006.169.08:28:09.19#ibcon#read 3, iclass 11, count 2 2006.169.08:28:09.19#ibcon#about to read 4, iclass 11, count 2 2006.169.08:28:09.19#ibcon#read 4, iclass 11, count 2 2006.169.08:28:09.19#ibcon#about to read 5, iclass 11, count 2 2006.169.08:28:09.19#ibcon#read 5, iclass 11, count 2 2006.169.08:28:09.19#ibcon#about to read 6, iclass 11, count 2 2006.169.08:28:09.19#ibcon#read 6, iclass 11, count 2 2006.169.08:28:09.19#ibcon#end of sib2, iclass 11, count 2 2006.169.08:28:09.19#ibcon#*mode == 0, iclass 11, count 2 2006.169.08:28:09.19#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.169.08:28:09.19#ibcon#[27=AT06-04\r\n] 2006.169.08:28:09.19#ibcon#*before write, iclass 11, count 2 2006.169.08:28:09.19#ibcon#enter sib2, iclass 11, count 2 2006.169.08:28:09.19#ibcon#flushed, iclass 11, count 2 2006.169.08:28:09.19#ibcon#about to write, iclass 11, count 2 2006.169.08:28:09.19#ibcon#wrote, iclass 11, count 2 2006.169.08:28:09.19#ibcon#about to read 3, iclass 11, count 2 2006.169.08:28:09.22#ibcon#read 3, iclass 11, count 2 2006.169.08:28:09.22#ibcon#about to read 4, iclass 11, count 2 2006.169.08:28:09.22#ibcon#read 4, iclass 11, count 2 2006.169.08:28:09.22#ibcon#about to read 5, iclass 11, count 2 2006.169.08:28:09.22#ibcon#read 5, iclass 11, count 2 2006.169.08:28:09.22#ibcon#about to read 6, iclass 11, count 2 2006.169.08:28:09.22#ibcon#read 6, iclass 11, count 2 2006.169.08:28:09.22#ibcon#end of sib2, iclass 11, count 2 2006.169.08:28:09.22#ibcon#*after write, iclass 11, count 2 2006.169.08:28:09.22#ibcon#*before return 0, iclass 11, count 2 2006.169.08:28:09.22#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.169.08:28:09.22#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.169.08:28:09.22#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.169.08:28:09.22#ibcon#ireg 7 cls_cnt 0 2006.169.08:28:09.22#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.169.08:28:09.34#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.169.08:28:09.34#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.169.08:28:09.34#ibcon#enter wrdev, iclass 11, count 0 2006.169.08:28:09.34#ibcon#first serial, iclass 11, count 0 2006.169.08:28:09.34#ibcon#enter sib2, iclass 11, count 0 2006.169.08:28:09.34#ibcon#flushed, iclass 11, count 0 2006.169.08:28:09.34#ibcon#about to write, iclass 11, count 0 2006.169.08:28:09.34#ibcon#wrote, iclass 11, count 0 2006.169.08:28:09.34#ibcon#about to read 3, iclass 11, count 0 2006.169.08:28:09.36#ibcon#read 3, iclass 11, count 0 2006.169.08:28:09.36#ibcon#about to read 4, iclass 11, count 0 2006.169.08:28:09.36#ibcon#read 4, iclass 11, count 0 2006.169.08:28:09.36#ibcon#about to read 5, iclass 11, count 0 2006.169.08:28:09.36#ibcon#read 5, iclass 11, count 0 2006.169.08:28:09.36#ibcon#about to read 6, iclass 11, count 0 2006.169.08:28:09.36#ibcon#read 6, iclass 11, count 0 2006.169.08:28:09.36#ibcon#end of sib2, iclass 11, count 0 2006.169.08:28:09.36#ibcon#*mode == 0, iclass 11, count 0 2006.169.08:28:09.36#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.169.08:28:09.36#ibcon#[27=USB\r\n] 2006.169.08:28:09.36#ibcon#*before write, iclass 11, count 0 2006.169.08:28:09.36#ibcon#enter sib2, iclass 11, count 0 2006.169.08:28:09.36#ibcon#flushed, iclass 11, count 0 2006.169.08:28:09.36#ibcon#about to write, iclass 11, count 0 2006.169.08:28:09.36#ibcon#wrote, iclass 11, count 0 2006.169.08:28:09.36#ibcon#about to read 3, iclass 11, count 0 2006.169.08:28:09.39#ibcon#read 3, iclass 11, count 0 2006.169.08:28:09.39#ibcon#about to read 4, iclass 11, count 0 2006.169.08:28:09.39#ibcon#read 4, iclass 11, count 0 2006.169.08:28:09.39#ibcon#about to read 5, iclass 11, count 0 2006.169.08:28:09.39#ibcon#read 5, iclass 11, count 0 2006.169.08:28:09.39#ibcon#about to read 6, iclass 11, count 0 2006.169.08:28:09.39#ibcon#read 6, iclass 11, count 0 2006.169.08:28:09.39#ibcon#end of sib2, iclass 11, count 0 2006.169.08:28:09.39#ibcon#*after write, iclass 11, count 0 2006.169.08:28:09.39#ibcon#*before return 0, iclass 11, count 0 2006.169.08:28:09.39#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.169.08:28:09.39#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.169.08:28:09.39#ibcon#about to clear, iclass 11 cls_cnt 0 2006.169.08:28:09.39#ibcon#cleared, iclass 11 cls_cnt 0 2006.169.08:28:09.39$vc4f8/vabw=wide 2006.169.08:28:09.39#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.169.08:28:09.39#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.169.08:28:09.39#ibcon#ireg 8 cls_cnt 0 2006.169.08:28:09.39#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:28:09.39#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:28:09.39#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:28:09.39#ibcon#enter wrdev, iclass 13, count 0 2006.169.08:28:09.39#ibcon#first serial, iclass 13, count 0 2006.169.08:28:09.39#ibcon#enter sib2, iclass 13, count 0 2006.169.08:28:09.39#ibcon#flushed, iclass 13, count 0 2006.169.08:28:09.39#ibcon#about to write, iclass 13, count 0 2006.169.08:28:09.39#ibcon#wrote, iclass 13, count 0 2006.169.08:28:09.39#ibcon#about to read 3, iclass 13, count 0 2006.169.08:28:09.41#ibcon#read 3, iclass 13, count 0 2006.169.08:28:09.41#ibcon#about to read 4, iclass 13, count 0 2006.169.08:28:09.41#ibcon#read 4, iclass 13, count 0 2006.169.08:28:09.41#ibcon#about to read 5, iclass 13, count 0 2006.169.08:28:09.41#ibcon#read 5, iclass 13, count 0 2006.169.08:28:09.41#ibcon#about to read 6, iclass 13, count 0 2006.169.08:28:09.41#ibcon#read 6, iclass 13, count 0 2006.169.08:28:09.41#ibcon#end of sib2, iclass 13, count 0 2006.169.08:28:09.41#ibcon#*mode == 0, iclass 13, count 0 2006.169.08:28:09.41#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.169.08:28:09.41#ibcon#[25=BW32\r\n] 2006.169.08:28:09.41#ibcon#*before write, iclass 13, count 0 2006.169.08:28:09.41#ibcon#enter sib2, iclass 13, count 0 2006.169.08:28:09.41#ibcon#flushed, iclass 13, count 0 2006.169.08:28:09.41#ibcon#about to write, iclass 13, count 0 2006.169.08:28:09.41#ibcon#wrote, iclass 13, count 0 2006.169.08:28:09.41#ibcon#about to read 3, iclass 13, count 0 2006.169.08:28:09.44#ibcon#read 3, iclass 13, count 0 2006.169.08:28:09.44#ibcon#about to read 4, iclass 13, count 0 2006.169.08:28:09.44#ibcon#read 4, iclass 13, count 0 2006.169.08:28:09.44#ibcon#about to read 5, iclass 13, count 0 2006.169.08:28:09.44#ibcon#read 5, iclass 13, count 0 2006.169.08:28:09.44#ibcon#about to read 6, iclass 13, count 0 2006.169.08:28:09.44#ibcon#read 6, iclass 13, count 0 2006.169.08:28:09.44#ibcon#end of sib2, iclass 13, count 0 2006.169.08:28:09.44#ibcon#*after write, iclass 13, count 0 2006.169.08:28:09.44#ibcon#*before return 0, iclass 13, count 0 2006.169.08:28:09.44#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:28:09.44#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.169.08:28:09.44#ibcon#about to clear, iclass 13 cls_cnt 0 2006.169.08:28:09.44#ibcon#cleared, iclass 13 cls_cnt 0 2006.169.08:28:09.44$vc4f8/vbbw=wide 2006.169.08:28:09.44#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.169.08:28:09.44#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.169.08:28:09.44#ibcon#ireg 8 cls_cnt 0 2006.169.08:28:09.44#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:28:09.51#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:28:09.51#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:28:09.51#ibcon#enter wrdev, iclass 15, count 0 2006.169.08:28:09.51#ibcon#first serial, iclass 15, count 0 2006.169.08:28:09.51#ibcon#enter sib2, iclass 15, count 0 2006.169.08:28:09.51#ibcon#flushed, iclass 15, count 0 2006.169.08:28:09.51#ibcon#about to write, iclass 15, count 0 2006.169.08:28:09.51#ibcon#wrote, iclass 15, count 0 2006.169.08:28:09.51#ibcon#about to read 3, iclass 15, count 0 2006.169.08:28:09.53#ibcon#read 3, iclass 15, count 0 2006.169.08:28:09.53#ibcon#about to read 4, iclass 15, count 0 2006.169.08:28:09.53#ibcon#read 4, iclass 15, count 0 2006.169.08:28:09.53#ibcon#about to read 5, iclass 15, count 0 2006.169.08:28:09.53#ibcon#read 5, iclass 15, count 0 2006.169.08:28:09.53#ibcon#about to read 6, iclass 15, count 0 2006.169.08:28:09.53#ibcon#read 6, iclass 15, count 0 2006.169.08:28:09.53#ibcon#end of sib2, iclass 15, count 0 2006.169.08:28:09.53#ibcon#*mode == 0, iclass 15, count 0 2006.169.08:28:09.53#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.169.08:28:09.53#ibcon#[27=BW32\r\n] 2006.169.08:28:09.53#ibcon#*before write, iclass 15, count 0 2006.169.08:28:09.53#ibcon#enter sib2, iclass 15, count 0 2006.169.08:28:09.53#ibcon#flushed, iclass 15, count 0 2006.169.08:28:09.53#ibcon#about to write, iclass 15, count 0 2006.169.08:28:09.53#ibcon#wrote, iclass 15, count 0 2006.169.08:28:09.53#ibcon#about to read 3, iclass 15, count 0 2006.169.08:28:09.56#ibcon#read 3, iclass 15, count 0 2006.169.08:28:09.56#ibcon#about to read 4, iclass 15, count 0 2006.169.08:28:09.56#ibcon#read 4, iclass 15, count 0 2006.169.08:28:09.56#ibcon#about to read 5, iclass 15, count 0 2006.169.08:28:09.56#ibcon#read 5, iclass 15, count 0 2006.169.08:28:09.56#ibcon#about to read 6, iclass 15, count 0 2006.169.08:28:09.56#ibcon#read 6, iclass 15, count 0 2006.169.08:28:09.56#ibcon#end of sib2, iclass 15, count 0 2006.169.08:28:09.56#ibcon#*after write, iclass 15, count 0 2006.169.08:28:09.56#ibcon#*before return 0, iclass 15, count 0 2006.169.08:28:09.56#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:28:09.56#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.169.08:28:09.56#ibcon#about to clear, iclass 15 cls_cnt 0 2006.169.08:28:09.56#ibcon#cleared, iclass 15 cls_cnt 0 2006.169.08:28:09.56$4f8m12a/ifd4f 2006.169.08:28:09.56$ifd4f/lo= 2006.169.08:28:09.56$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.08:28:09.56$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.08:28:09.56$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.08:28:09.56$ifd4f/patch= 2006.169.08:28:09.56$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.08:28:09.56$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.08:28:09.56$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.08:28:09.56$4f8m12a/"form=m,16.000,1:2 2006.169.08:28:09.56$4f8m12a/"tpicd 2006.169.08:28:09.56$4f8m12a/echo=off 2006.169.08:28:09.56$4f8m12a/xlog=off 2006.169.08:28:09.56:!2006.169.08:28:20 2006.169.08:28:20.00:preob 2006.169.08:28:21.13/onsource/TRACKING 2006.169.08:28:21.13:!2006.169.08:28:30 2006.169.08:28:30.00:data_valid=on 2006.169.08:28:30.00:midob 2006.169.08:28:30.13/onsource/TRACKING 2006.169.08:28:30.13/wx/18.10,1003.8,100 2006.169.08:28:30.24/cable/+6.5294E-03 2006.169.08:28:31.33/va/01,08,usb,yes,40,42 2006.169.08:28:31.33/va/02,07,usb,yes,41,42 2006.169.08:28:31.33/va/03,06,usb,yes,43,43 2006.169.08:28:31.33/va/04,07,usb,yes,42,45 2006.169.08:28:31.33/va/05,07,usb,yes,46,48 2006.169.08:28:31.33/va/06,06,usb,yes,45,44 2006.169.08:28:31.33/va/07,06,usb,yes,45,45 2006.169.08:28:31.33/va/08,07,usb,yes,43,42 2006.169.08:28:31.56/valo/01,532.99,yes,locked 2006.169.08:28:31.56/valo/02,572.99,yes,locked 2006.169.08:28:31.56/valo/03,672.99,yes,locked 2006.169.08:28:31.56/valo/04,832.99,yes,locked 2006.169.08:28:31.56/valo/05,652.99,yes,locked 2006.169.08:28:31.56/valo/06,772.99,yes,locked 2006.169.08:28:31.56/valo/07,832.99,yes,locked 2006.169.08:28:31.56/valo/08,852.99,yes,locked 2006.169.08:28:32.65/vb/01,04,usb,yes,30,28 2006.169.08:28:32.65/vb/02,04,usb,yes,32,33 2006.169.08:28:32.65/vb/03,04,usb,yes,28,32 2006.169.08:28:32.65/vb/04,04,usb,yes,29,29 2006.169.08:28:32.65/vb/05,04,usb,yes,27,31 2006.169.08:28:32.65/vb/06,04,usb,yes,29,31 2006.169.08:28:32.65/vb/07,04,usb,yes,30,30 2006.169.08:28:32.65/vb/08,04,usb,yes,28,31 2006.169.08:28:32.89/vblo/01,632.99,yes,locked 2006.169.08:28:32.89/vblo/02,640.99,yes,locked 2006.169.08:28:32.89/vblo/03,656.99,yes,locked 2006.169.08:28:32.89/vblo/04,712.99,yes,locked 2006.169.08:28:32.89/vblo/05,744.99,yes,locked 2006.169.08:28:32.89/vblo/06,752.99,yes,locked 2006.169.08:28:32.89/vblo/07,734.99,yes,locked 2006.169.08:28:32.89/vblo/08,744.99,yes,locked 2006.169.08:28:33.04/vabw/8 2006.169.08:28:33.19/vbbw/8 2006.169.08:28:33.28/xfe/off,on,15.0 2006.169.08:28:33.67/ifatt/23,28,28,28 2006.169.08:28:34.07/fmout-gps/S +4.18E-07 2006.169.08:28:34.15:!2006.169.08:29:30 2006.169.08:29:30.01:data_valid=off 2006.169.08:29:30.02:postob 2006.169.08:29:30.09/cable/+6.5272E-03 2006.169.08:29:30.09/wx/18.09,1003.8,100 2006.169.08:29:31.07/fmout-gps/S +4.18E-07 2006.169.08:29:31.08:scan_name=169-0830,k06169,60 2006.169.08:29:31.08:source=1803+784,180045.68,782804.0,2000.0,cw 2006.169.08:29:31.14#flagr#flagr/antenna,new-source 2006.169.08:29:32.14:checkk5 2006.169.08:29:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.169.08:29:32.90/chk_autoobs//k5ts2/ autoobs is running! 2006.169.08:29:36.92/chk_autoobs//k5ts3?ERROR: timeout happened! 2006.169.08:29:37.30/chk_autoobs//k5ts4/ autoobs is running! 2006.169.08:29:37.67/chk_obsdata//k5ts1/T1690828??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.08:29:38.04/chk_obsdata//k5ts2/T1690828??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.08:29:45.10/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.08:29:45.15#trakl#Source acquired 2006.169.08:29:45.48/chk_obsdata//k5ts4/T1690828??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.169.08:29:46.12#flagr#flagr/antenna,acquired 2006.169.08:29:46.20/k5log//k5ts1_log_newline 2006.169.08:29:46.90/k5log//k5ts2_log_newline 2006.169.08:29:53.99/k5log//k5ts3?ERROR: timeout happened! 2006.169.08:29:54.68/k5log//k5ts4_log_newline 2006.169.08:29:54.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.08:29:54.85:4f8m12a=3 2006.169.08:29:54.85$4f8m12a/echo=on 2006.169.08:29:54.85$4f8m12a/pcalon 2006.169.08:29:54.85$pcalon/"no phase cal control is implemented here 2006.169.08:29:54.85$4f8m12a/"tpicd=stop 2006.169.08:29:54.85$4f8m12a/vc4f8 2006.169.08:29:54.85$vc4f8/valo=1,532.99 2006.169.08:29:54.85#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.169.08:29:54.85#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.169.08:29:54.85#ibcon#ireg 17 cls_cnt 0 2006.169.08:29:54.85#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.169.08:29:54.85#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.169.08:29:54.85#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.169.08:29:54.85#ibcon#enter wrdev, iclass 22, count 0 2006.169.08:29:54.85#ibcon#first serial, iclass 22, count 0 2006.169.08:29:54.85#ibcon#enter sib2, iclass 22, count 0 2006.169.08:29:54.85#ibcon#flushed, iclass 22, count 0 2006.169.08:29:54.85#ibcon#about to write, iclass 22, count 0 2006.169.08:29:54.85#ibcon#wrote, iclass 22, count 0 2006.169.08:29:54.85#ibcon#about to read 3, iclass 22, count 0 2006.169.08:29:54.87#ibcon#read 3, iclass 22, count 0 2006.169.08:29:54.87#ibcon#about to read 4, iclass 22, count 0 2006.169.08:29:54.87#ibcon#read 4, iclass 22, count 0 2006.169.08:29:54.87#ibcon#about to read 5, iclass 22, count 0 2006.169.08:29:54.87#ibcon#read 5, iclass 22, count 0 2006.169.08:29:54.87#ibcon#about to read 6, iclass 22, count 0 2006.169.08:29:54.87#ibcon#read 6, iclass 22, count 0 2006.169.08:29:54.87#ibcon#end of sib2, iclass 22, count 0 2006.169.08:29:54.87#ibcon#*mode == 0, iclass 22, count 0 2006.169.08:29:54.87#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.169.08:29:54.87#ibcon#[26=FRQ=01,532.99\r\n] 2006.169.08:29:54.87#ibcon#*before write, iclass 22, count 0 2006.169.08:29:54.87#ibcon#enter sib2, iclass 22, count 0 2006.169.08:29:54.87#ibcon#flushed, iclass 22, count 0 2006.169.08:29:54.87#ibcon#about to write, iclass 22, count 0 2006.169.08:29:54.87#ibcon#wrote, iclass 22, count 0 2006.169.08:29:54.87#ibcon#about to read 3, iclass 22, count 0 2006.169.08:29:54.93#ibcon#read 3, iclass 22, count 0 2006.169.08:29:54.93#ibcon#about to read 4, iclass 22, count 0 2006.169.08:29:54.93#ibcon#read 4, iclass 22, count 0 2006.169.08:29:54.93#ibcon#about to read 5, iclass 22, count 0 2006.169.08:29:54.93#ibcon#read 5, iclass 22, count 0 2006.169.08:29:54.93#ibcon#about to read 6, iclass 22, count 0 2006.169.08:29:54.93#ibcon#read 6, iclass 22, count 0 2006.169.08:29:54.93#ibcon#end of sib2, iclass 22, count 0 2006.169.08:29:54.93#ibcon#*after write, iclass 22, count 0 2006.169.08:29:54.93#ibcon#*before return 0, iclass 22, count 0 2006.169.08:29:54.93#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.169.08:29:54.93#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.169.08:29:54.93#ibcon#about to clear, iclass 22 cls_cnt 0 2006.169.08:29:54.93#ibcon#cleared, iclass 22 cls_cnt 0 2006.169.08:29:54.93$vc4f8/va=1,8 2006.169.08:29:54.93#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.169.08:29:54.93#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.169.08:29:54.93#ibcon#ireg 11 cls_cnt 2 2006.169.08:29:54.93#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.169.08:29:54.93#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.169.08:29:54.93#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.169.08:29:54.93#ibcon#enter wrdev, iclass 24, count 2 2006.169.08:29:54.93#ibcon#first serial, iclass 24, count 2 2006.169.08:29:54.93#ibcon#enter sib2, iclass 24, count 2 2006.169.08:29:54.93#ibcon#flushed, iclass 24, count 2 2006.169.08:29:54.93#ibcon#about to write, iclass 24, count 2 2006.169.08:29:54.93#ibcon#wrote, iclass 24, count 2 2006.169.08:29:54.93#ibcon#about to read 3, iclass 24, count 2 2006.169.08:29:54.94#ibcon#read 3, iclass 24, count 2 2006.169.08:29:54.94#ibcon#about to read 4, iclass 24, count 2 2006.169.08:29:54.94#ibcon#read 4, iclass 24, count 2 2006.169.08:29:54.94#ibcon#about to read 5, iclass 24, count 2 2006.169.08:29:54.94#ibcon#read 5, iclass 24, count 2 2006.169.08:29:54.94#ibcon#about to read 6, iclass 24, count 2 2006.169.08:29:54.94#ibcon#read 6, iclass 24, count 2 2006.169.08:29:54.94#ibcon#end of sib2, iclass 24, count 2 2006.169.08:29:54.94#ibcon#*mode == 0, iclass 24, count 2 2006.169.08:29:54.94#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.169.08:29:54.94#ibcon#[25=AT01-08\r\n] 2006.169.08:29:54.94#ibcon#*before write, iclass 24, count 2 2006.169.08:29:54.94#ibcon#enter sib2, iclass 24, count 2 2006.169.08:29:54.94#ibcon#flushed, iclass 24, count 2 2006.169.08:29:54.94#ibcon#about to write, iclass 24, count 2 2006.169.08:29:54.94#ibcon#wrote, iclass 24, count 2 2006.169.08:29:54.94#ibcon#about to read 3, iclass 24, count 2 2006.169.08:29:54.97#ibcon#read 3, iclass 24, count 2 2006.169.08:29:54.97#ibcon#about to read 4, iclass 24, count 2 2006.169.08:29:54.97#ibcon#read 4, iclass 24, count 2 2006.169.08:29:54.97#ibcon#about to read 5, iclass 24, count 2 2006.169.08:29:54.97#ibcon#read 5, iclass 24, count 2 2006.169.08:29:54.97#ibcon#about to read 6, iclass 24, count 2 2006.169.08:29:54.97#ibcon#read 6, iclass 24, count 2 2006.169.08:29:54.97#ibcon#end of sib2, iclass 24, count 2 2006.169.08:29:54.97#ibcon#*after write, iclass 24, count 2 2006.169.08:29:54.97#ibcon#*before return 0, iclass 24, count 2 2006.169.08:29:54.97#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.169.08:29:54.97#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.169.08:29:54.97#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.169.08:29:54.97#ibcon#ireg 7 cls_cnt 0 2006.169.08:29:54.97#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.169.08:29:55.09#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.169.08:29:55.09#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.169.08:29:55.09#ibcon#enter wrdev, iclass 24, count 0 2006.169.08:29:55.09#ibcon#first serial, iclass 24, count 0 2006.169.08:29:55.09#ibcon#enter sib2, iclass 24, count 0 2006.169.08:29:55.09#ibcon#flushed, iclass 24, count 0 2006.169.08:29:55.09#ibcon#about to write, iclass 24, count 0 2006.169.08:29:55.09#ibcon#wrote, iclass 24, count 0 2006.169.08:29:55.09#ibcon#about to read 3, iclass 24, count 0 2006.169.08:29:55.13#ibcon#read 3, iclass 24, count 0 2006.169.08:29:55.13#ibcon#about to read 4, iclass 24, count 0 2006.169.08:29:55.13#ibcon#read 4, iclass 24, count 0 2006.169.08:29:55.13#ibcon#about to read 5, iclass 24, count 0 2006.169.08:29:55.13#ibcon#read 5, iclass 24, count 0 2006.169.08:29:55.13#ibcon#about to read 6, iclass 24, count 0 2006.169.08:29:55.13#ibcon#read 6, iclass 24, count 0 2006.169.08:29:55.13#ibcon#end of sib2, iclass 24, count 0 2006.169.08:29:55.13#ibcon#*mode == 0, iclass 24, count 0 2006.169.08:29:55.13#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.169.08:29:55.13#ibcon#[25=USB\r\n] 2006.169.08:29:55.13#ibcon#*before write, iclass 24, count 0 2006.169.08:29:55.13#ibcon#enter sib2, iclass 24, count 0 2006.169.08:29:55.13#ibcon#flushed, iclass 24, count 0 2006.169.08:29:55.13#ibcon#about to write, iclass 24, count 0 2006.169.08:29:55.13#ibcon#wrote, iclass 24, count 0 2006.169.08:29:55.13#ibcon#about to read 3, iclass 24, count 0 2006.169.08:29:55.16#ibcon#read 3, iclass 24, count 0 2006.169.08:29:55.16#ibcon#about to read 4, iclass 24, count 0 2006.169.08:29:55.16#ibcon#read 4, iclass 24, count 0 2006.169.08:29:55.16#ibcon#about to read 5, iclass 24, count 0 2006.169.08:29:55.16#ibcon#read 5, iclass 24, count 0 2006.169.08:29:55.16#ibcon#about to read 6, iclass 24, count 0 2006.169.08:29:55.16#ibcon#read 6, iclass 24, count 0 2006.169.08:29:55.16#ibcon#end of sib2, iclass 24, count 0 2006.169.08:29:55.16#ibcon#*after write, iclass 24, count 0 2006.169.08:29:55.16#ibcon#*before return 0, iclass 24, count 0 2006.169.08:29:55.16#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.169.08:29:55.16#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.169.08:29:55.16#ibcon#about to clear, iclass 24 cls_cnt 0 2006.169.08:29:55.16#ibcon#cleared, iclass 24 cls_cnt 0 2006.169.08:29:55.16$vc4f8/valo=2,572.99 2006.169.08:29:55.16#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.169.08:29:55.16#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.169.08:29:55.16#ibcon#ireg 17 cls_cnt 0 2006.169.08:29:55.16#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:29:55.16#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:29:55.16#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:29:55.16#ibcon#enter wrdev, iclass 26, count 0 2006.169.08:29:55.16#ibcon#first serial, iclass 26, count 0 2006.169.08:29:55.16#ibcon#enter sib2, iclass 26, count 0 2006.169.08:29:55.16#ibcon#flushed, iclass 26, count 0 2006.169.08:29:55.16#ibcon#about to write, iclass 26, count 0 2006.169.08:29:55.16#ibcon#wrote, iclass 26, count 0 2006.169.08:29:55.16#ibcon#about to read 3, iclass 26, count 0 2006.169.08:29:55.18#ibcon#read 3, iclass 26, count 0 2006.169.08:29:55.18#ibcon#about to read 4, iclass 26, count 0 2006.169.08:29:55.18#ibcon#read 4, iclass 26, count 0 2006.169.08:29:55.18#ibcon#about to read 5, iclass 26, count 0 2006.169.08:29:55.18#ibcon#read 5, iclass 26, count 0 2006.169.08:29:55.18#ibcon#about to read 6, iclass 26, count 0 2006.169.08:29:55.18#ibcon#read 6, iclass 26, count 0 2006.169.08:29:55.18#ibcon#end of sib2, iclass 26, count 0 2006.169.08:29:55.18#ibcon#*mode == 0, iclass 26, count 0 2006.169.08:29:55.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.169.08:29:55.18#ibcon#[26=FRQ=02,572.99\r\n] 2006.169.08:29:55.18#ibcon#*before write, iclass 26, count 0 2006.169.08:29:55.18#ibcon#enter sib2, iclass 26, count 0 2006.169.08:29:55.18#ibcon#flushed, iclass 26, count 0 2006.169.08:29:55.18#ibcon#about to write, iclass 26, count 0 2006.169.08:29:55.18#ibcon#wrote, iclass 26, count 0 2006.169.08:29:55.18#ibcon#about to read 3, iclass 26, count 0 2006.169.08:29:55.23#ibcon#read 3, iclass 26, count 0 2006.169.08:29:55.23#ibcon#about to read 4, iclass 26, count 0 2006.169.08:29:55.23#ibcon#read 4, iclass 26, count 0 2006.169.08:29:55.23#ibcon#about to read 5, iclass 26, count 0 2006.169.08:29:55.23#ibcon#read 5, iclass 26, count 0 2006.169.08:29:55.23#ibcon#about to read 6, iclass 26, count 0 2006.169.08:29:55.23#ibcon#read 6, iclass 26, count 0 2006.169.08:29:55.23#ibcon#end of sib2, iclass 26, count 0 2006.169.08:29:55.23#ibcon#*after write, iclass 26, count 0 2006.169.08:29:55.23#ibcon#*before return 0, iclass 26, count 0 2006.169.08:29:55.23#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:29:55.23#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:29:55.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.169.08:29:55.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.169.08:29:55.23$vc4f8/va=2,7 2006.169.08:29:55.23#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.169.08:29:55.23#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.169.08:29:55.23#ibcon#ireg 11 cls_cnt 2 2006.169.08:29:55.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.169.08:29:55.27#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.169.08:29:55.27#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.169.08:29:55.27#ibcon#enter wrdev, iclass 28, count 2 2006.169.08:29:55.27#ibcon#first serial, iclass 28, count 2 2006.169.08:29:55.27#ibcon#enter sib2, iclass 28, count 2 2006.169.08:29:55.27#ibcon#flushed, iclass 28, count 2 2006.169.08:29:55.27#ibcon#about to write, iclass 28, count 2 2006.169.08:29:55.27#ibcon#wrote, iclass 28, count 2 2006.169.08:29:55.27#ibcon#about to read 3, iclass 28, count 2 2006.169.08:29:55.29#ibcon#read 3, iclass 28, count 2 2006.169.08:29:55.29#ibcon#about to read 4, iclass 28, count 2 2006.169.08:29:55.29#ibcon#read 4, iclass 28, count 2 2006.169.08:29:55.29#ibcon#about to read 5, iclass 28, count 2 2006.169.08:29:55.29#ibcon#read 5, iclass 28, count 2 2006.169.08:29:55.29#ibcon#about to read 6, iclass 28, count 2 2006.169.08:29:55.29#ibcon#read 6, iclass 28, count 2 2006.169.08:29:55.29#ibcon#end of sib2, iclass 28, count 2 2006.169.08:29:55.29#ibcon#*mode == 0, iclass 28, count 2 2006.169.08:29:55.29#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.169.08:29:55.29#ibcon#[25=AT02-07\r\n] 2006.169.08:29:55.29#ibcon#*before write, iclass 28, count 2 2006.169.08:29:55.29#ibcon#enter sib2, iclass 28, count 2 2006.169.08:29:55.29#ibcon#flushed, iclass 28, count 2 2006.169.08:29:55.29#ibcon#about to write, iclass 28, count 2 2006.169.08:29:55.29#ibcon#wrote, iclass 28, count 2 2006.169.08:29:55.29#ibcon#about to read 3, iclass 28, count 2 2006.169.08:29:55.32#ibcon#read 3, iclass 28, count 2 2006.169.08:29:55.32#ibcon#about to read 4, iclass 28, count 2 2006.169.08:29:55.32#ibcon#read 4, iclass 28, count 2 2006.169.08:29:55.32#ibcon#about to read 5, iclass 28, count 2 2006.169.08:29:55.32#ibcon#read 5, iclass 28, count 2 2006.169.08:29:55.32#ibcon#about to read 6, iclass 28, count 2 2006.169.08:29:55.32#ibcon#read 6, iclass 28, count 2 2006.169.08:29:55.32#ibcon#end of sib2, iclass 28, count 2 2006.169.08:29:55.32#ibcon#*after write, iclass 28, count 2 2006.169.08:29:55.32#ibcon#*before return 0, iclass 28, count 2 2006.169.08:29:55.32#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.169.08:29:55.32#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.169.08:29:55.32#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.169.08:29:55.32#ibcon#ireg 7 cls_cnt 0 2006.169.08:29:55.32#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.169.08:29:55.44#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.169.08:29:55.44#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.169.08:29:55.44#ibcon#enter wrdev, iclass 28, count 0 2006.169.08:29:55.44#ibcon#first serial, iclass 28, count 0 2006.169.08:29:55.44#ibcon#enter sib2, iclass 28, count 0 2006.169.08:29:55.44#ibcon#flushed, iclass 28, count 0 2006.169.08:29:55.44#ibcon#about to write, iclass 28, count 0 2006.169.08:29:55.44#ibcon#wrote, iclass 28, count 0 2006.169.08:29:55.44#ibcon#about to read 3, iclass 28, count 0 2006.169.08:29:55.46#ibcon#read 3, iclass 28, count 0 2006.169.08:29:55.46#ibcon#about to read 4, iclass 28, count 0 2006.169.08:29:55.46#ibcon#read 4, iclass 28, count 0 2006.169.08:29:55.46#ibcon#about to read 5, iclass 28, count 0 2006.169.08:29:55.46#ibcon#read 5, iclass 28, count 0 2006.169.08:29:55.46#ibcon#about to read 6, iclass 28, count 0 2006.169.08:29:55.46#ibcon#read 6, iclass 28, count 0 2006.169.08:29:55.46#ibcon#end of sib2, iclass 28, count 0 2006.169.08:29:55.46#ibcon#*mode == 0, iclass 28, count 0 2006.169.08:29:55.46#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.169.08:29:55.46#ibcon#[25=USB\r\n] 2006.169.08:29:55.46#ibcon#*before write, iclass 28, count 0 2006.169.08:29:55.46#ibcon#enter sib2, iclass 28, count 0 2006.169.08:29:55.46#ibcon#flushed, iclass 28, count 0 2006.169.08:29:55.46#ibcon#about to write, iclass 28, count 0 2006.169.08:29:55.46#ibcon#wrote, iclass 28, count 0 2006.169.08:29:55.46#ibcon#about to read 3, iclass 28, count 0 2006.169.08:29:55.49#ibcon#read 3, iclass 28, count 0 2006.169.08:29:55.49#ibcon#about to read 4, iclass 28, count 0 2006.169.08:29:55.49#ibcon#read 4, iclass 28, count 0 2006.169.08:29:55.49#ibcon#about to read 5, iclass 28, count 0 2006.169.08:29:55.49#ibcon#read 5, iclass 28, count 0 2006.169.08:29:55.49#ibcon#about to read 6, iclass 28, count 0 2006.169.08:29:55.49#ibcon#read 6, iclass 28, count 0 2006.169.08:29:55.49#ibcon#end of sib2, iclass 28, count 0 2006.169.08:29:55.49#ibcon#*after write, iclass 28, count 0 2006.169.08:29:55.49#ibcon#*before return 0, iclass 28, count 0 2006.169.08:29:55.49#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.169.08:29:55.49#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.169.08:29:55.49#ibcon#about to clear, iclass 28 cls_cnt 0 2006.169.08:29:55.49#ibcon#cleared, iclass 28 cls_cnt 0 2006.169.08:29:55.49$vc4f8/valo=3,672.99 2006.169.08:29:55.49#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.169.08:29:55.49#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.169.08:29:55.49#ibcon#ireg 17 cls_cnt 0 2006.169.08:29:55.49#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.169.08:29:55.49#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.169.08:29:55.49#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.169.08:29:55.49#ibcon#enter wrdev, iclass 30, count 0 2006.169.08:29:55.49#ibcon#first serial, iclass 30, count 0 2006.169.08:29:55.49#ibcon#enter sib2, iclass 30, count 0 2006.169.08:29:55.49#ibcon#flushed, iclass 30, count 0 2006.169.08:29:55.49#ibcon#about to write, iclass 30, count 0 2006.169.08:29:55.49#ibcon#wrote, iclass 30, count 0 2006.169.08:29:55.49#ibcon#about to read 3, iclass 30, count 0 2006.169.08:29:55.51#ibcon#read 3, iclass 30, count 0 2006.169.08:29:55.51#ibcon#about to read 4, iclass 30, count 0 2006.169.08:29:55.51#ibcon#read 4, iclass 30, count 0 2006.169.08:29:55.51#ibcon#about to read 5, iclass 30, count 0 2006.169.08:29:55.51#ibcon#read 5, iclass 30, count 0 2006.169.08:29:55.51#ibcon#about to read 6, iclass 30, count 0 2006.169.08:29:55.51#ibcon#read 6, iclass 30, count 0 2006.169.08:29:55.51#ibcon#end of sib2, iclass 30, count 0 2006.169.08:29:55.51#ibcon#*mode == 0, iclass 30, count 0 2006.169.08:29:55.51#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.169.08:29:55.51#ibcon#[26=FRQ=03,672.99\r\n] 2006.169.08:29:55.51#ibcon#*before write, iclass 30, count 0 2006.169.08:29:55.51#ibcon#enter sib2, iclass 30, count 0 2006.169.08:29:55.51#ibcon#flushed, iclass 30, count 0 2006.169.08:29:55.51#ibcon#about to write, iclass 30, count 0 2006.169.08:29:55.51#ibcon#wrote, iclass 30, count 0 2006.169.08:29:55.51#ibcon#about to read 3, iclass 30, count 0 2006.169.08:29:55.55#ibcon#read 3, iclass 30, count 0 2006.169.08:29:55.55#ibcon#about to read 4, iclass 30, count 0 2006.169.08:29:55.55#ibcon#read 4, iclass 30, count 0 2006.169.08:29:55.55#ibcon#about to read 5, iclass 30, count 0 2006.169.08:29:55.55#ibcon#read 5, iclass 30, count 0 2006.169.08:29:55.55#ibcon#about to read 6, iclass 30, count 0 2006.169.08:29:55.55#ibcon#read 6, iclass 30, count 0 2006.169.08:29:55.55#ibcon#end of sib2, iclass 30, count 0 2006.169.08:29:55.55#ibcon#*after write, iclass 30, count 0 2006.169.08:29:55.55#ibcon#*before return 0, iclass 30, count 0 2006.169.08:29:55.55#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.169.08:29:55.55#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.169.08:29:55.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.169.08:29:55.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.169.08:29:55.55$vc4f8/va=3,6 2006.169.08:29:55.55#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.169.08:29:55.55#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.169.08:29:55.55#ibcon#ireg 11 cls_cnt 2 2006.169.08:29:55.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.169.08:29:55.61#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.169.08:29:55.61#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.169.08:29:55.61#ibcon#enter wrdev, iclass 32, count 2 2006.169.08:29:55.61#ibcon#first serial, iclass 32, count 2 2006.169.08:29:55.61#ibcon#enter sib2, iclass 32, count 2 2006.169.08:29:55.61#ibcon#flushed, iclass 32, count 2 2006.169.08:29:55.61#ibcon#about to write, iclass 32, count 2 2006.169.08:29:55.61#ibcon#wrote, iclass 32, count 2 2006.169.08:29:55.61#ibcon#about to read 3, iclass 32, count 2 2006.169.08:29:55.63#ibcon#read 3, iclass 32, count 2 2006.169.08:29:55.63#ibcon#about to read 4, iclass 32, count 2 2006.169.08:29:55.63#ibcon#read 4, iclass 32, count 2 2006.169.08:29:55.63#ibcon#about to read 5, iclass 32, count 2 2006.169.08:29:55.63#ibcon#read 5, iclass 32, count 2 2006.169.08:29:55.63#ibcon#about to read 6, iclass 32, count 2 2006.169.08:29:55.63#ibcon#read 6, iclass 32, count 2 2006.169.08:29:55.63#ibcon#end of sib2, iclass 32, count 2 2006.169.08:29:55.63#ibcon#*mode == 0, iclass 32, count 2 2006.169.08:29:55.63#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.169.08:29:55.63#ibcon#[25=AT03-06\r\n] 2006.169.08:29:55.63#ibcon#*before write, iclass 32, count 2 2006.169.08:29:55.63#ibcon#enter sib2, iclass 32, count 2 2006.169.08:29:55.63#ibcon#flushed, iclass 32, count 2 2006.169.08:29:55.63#ibcon#about to write, iclass 32, count 2 2006.169.08:29:55.63#ibcon#wrote, iclass 32, count 2 2006.169.08:29:55.63#ibcon#about to read 3, iclass 32, count 2 2006.169.08:29:55.66#ibcon#read 3, iclass 32, count 2 2006.169.08:29:55.66#ibcon#about to read 4, iclass 32, count 2 2006.169.08:29:55.66#ibcon#read 4, iclass 32, count 2 2006.169.08:29:55.66#ibcon#about to read 5, iclass 32, count 2 2006.169.08:29:55.66#ibcon#read 5, iclass 32, count 2 2006.169.08:29:55.66#ibcon#about to read 6, iclass 32, count 2 2006.169.08:29:55.66#ibcon#read 6, iclass 32, count 2 2006.169.08:29:55.66#ibcon#end of sib2, iclass 32, count 2 2006.169.08:29:55.66#ibcon#*after write, iclass 32, count 2 2006.169.08:29:55.66#ibcon#*before return 0, iclass 32, count 2 2006.169.08:29:55.66#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.169.08:29:55.66#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.169.08:29:55.66#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.169.08:29:55.66#ibcon#ireg 7 cls_cnt 0 2006.169.08:29:55.66#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.169.08:29:55.78#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.169.08:29:55.78#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.169.08:29:55.78#ibcon#enter wrdev, iclass 32, count 0 2006.169.08:29:55.78#ibcon#first serial, iclass 32, count 0 2006.169.08:29:55.78#ibcon#enter sib2, iclass 32, count 0 2006.169.08:29:55.78#ibcon#flushed, iclass 32, count 0 2006.169.08:29:55.78#ibcon#about to write, iclass 32, count 0 2006.169.08:29:55.78#ibcon#wrote, iclass 32, count 0 2006.169.08:29:55.78#ibcon#about to read 3, iclass 32, count 0 2006.169.08:29:55.80#ibcon#read 3, iclass 32, count 0 2006.169.08:29:55.80#ibcon#about to read 4, iclass 32, count 0 2006.169.08:29:55.80#ibcon#read 4, iclass 32, count 0 2006.169.08:29:55.80#ibcon#about to read 5, iclass 32, count 0 2006.169.08:29:55.80#ibcon#read 5, iclass 32, count 0 2006.169.08:29:55.80#ibcon#about to read 6, iclass 32, count 0 2006.169.08:29:55.80#ibcon#read 6, iclass 32, count 0 2006.169.08:29:55.80#ibcon#end of sib2, iclass 32, count 0 2006.169.08:29:55.80#ibcon#*mode == 0, iclass 32, count 0 2006.169.08:29:55.80#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.169.08:29:55.80#ibcon#[25=USB\r\n] 2006.169.08:29:55.80#ibcon#*before write, iclass 32, count 0 2006.169.08:29:55.80#ibcon#enter sib2, iclass 32, count 0 2006.169.08:29:55.80#ibcon#flushed, iclass 32, count 0 2006.169.08:29:55.80#ibcon#about to write, iclass 32, count 0 2006.169.08:29:55.80#ibcon#wrote, iclass 32, count 0 2006.169.08:29:55.80#ibcon#about to read 3, iclass 32, count 0 2006.169.08:29:55.83#ibcon#read 3, iclass 32, count 0 2006.169.08:29:55.83#ibcon#about to read 4, iclass 32, count 0 2006.169.08:29:55.83#ibcon#read 4, iclass 32, count 0 2006.169.08:29:55.83#ibcon#about to read 5, iclass 32, count 0 2006.169.08:29:55.83#ibcon#read 5, iclass 32, count 0 2006.169.08:29:55.83#ibcon#about to read 6, iclass 32, count 0 2006.169.08:29:55.83#ibcon#read 6, iclass 32, count 0 2006.169.08:29:55.83#ibcon#end of sib2, iclass 32, count 0 2006.169.08:29:55.83#ibcon#*after write, iclass 32, count 0 2006.169.08:29:55.83#ibcon#*before return 0, iclass 32, count 0 2006.169.08:29:55.83#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.169.08:29:55.83#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.169.08:29:55.83#ibcon#about to clear, iclass 32 cls_cnt 0 2006.169.08:29:55.83#ibcon#cleared, iclass 32 cls_cnt 0 2006.169.08:29:55.83$vc4f8/valo=4,832.99 2006.169.08:29:55.83#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.169.08:29:55.83#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.169.08:29:55.83#ibcon#ireg 17 cls_cnt 0 2006.169.08:29:55.83#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:29:55.83#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:29:55.83#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:29:55.83#ibcon#enter wrdev, iclass 34, count 0 2006.169.08:29:55.83#ibcon#first serial, iclass 34, count 0 2006.169.08:29:55.83#ibcon#enter sib2, iclass 34, count 0 2006.169.08:29:55.83#ibcon#flushed, iclass 34, count 0 2006.169.08:29:55.83#ibcon#about to write, iclass 34, count 0 2006.169.08:29:55.83#ibcon#wrote, iclass 34, count 0 2006.169.08:29:55.83#ibcon#about to read 3, iclass 34, count 0 2006.169.08:29:55.85#ibcon#read 3, iclass 34, count 0 2006.169.08:29:55.85#ibcon#about to read 4, iclass 34, count 0 2006.169.08:29:55.85#ibcon#read 4, iclass 34, count 0 2006.169.08:29:55.85#ibcon#about to read 5, iclass 34, count 0 2006.169.08:29:55.85#ibcon#read 5, iclass 34, count 0 2006.169.08:29:55.85#ibcon#about to read 6, iclass 34, count 0 2006.169.08:29:55.85#ibcon#read 6, iclass 34, count 0 2006.169.08:29:55.85#ibcon#end of sib2, iclass 34, count 0 2006.169.08:29:55.85#ibcon#*mode == 0, iclass 34, count 0 2006.169.08:29:55.85#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.169.08:29:55.85#ibcon#[26=FRQ=04,832.99\r\n] 2006.169.08:29:55.85#ibcon#*before write, iclass 34, count 0 2006.169.08:29:55.85#ibcon#enter sib2, iclass 34, count 0 2006.169.08:29:55.85#ibcon#flushed, iclass 34, count 0 2006.169.08:29:55.85#ibcon#about to write, iclass 34, count 0 2006.169.08:29:55.85#ibcon#wrote, iclass 34, count 0 2006.169.08:29:55.85#ibcon#about to read 3, iclass 34, count 0 2006.169.08:29:55.89#ibcon#read 3, iclass 34, count 0 2006.169.08:29:55.89#ibcon#about to read 4, iclass 34, count 0 2006.169.08:29:55.89#ibcon#read 4, iclass 34, count 0 2006.169.08:29:55.89#ibcon#about to read 5, iclass 34, count 0 2006.169.08:29:55.89#ibcon#read 5, iclass 34, count 0 2006.169.08:29:55.89#ibcon#about to read 6, iclass 34, count 0 2006.169.08:29:55.89#ibcon#read 6, iclass 34, count 0 2006.169.08:29:55.89#ibcon#end of sib2, iclass 34, count 0 2006.169.08:29:55.89#ibcon#*after write, iclass 34, count 0 2006.169.08:29:55.89#ibcon#*before return 0, iclass 34, count 0 2006.169.08:29:55.89#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:29:55.89#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:29:55.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.169.08:29:55.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.169.08:29:55.89$vc4f8/va=4,7 2006.169.08:29:55.89#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.169.08:29:55.89#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.169.08:29:55.89#ibcon#ireg 11 cls_cnt 2 2006.169.08:29:55.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.169.08:29:55.95#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.169.08:29:55.95#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.169.08:29:55.95#ibcon#enter wrdev, iclass 36, count 2 2006.169.08:29:55.95#ibcon#first serial, iclass 36, count 2 2006.169.08:29:55.95#ibcon#enter sib2, iclass 36, count 2 2006.169.08:29:55.95#ibcon#flushed, iclass 36, count 2 2006.169.08:29:55.95#ibcon#about to write, iclass 36, count 2 2006.169.08:29:55.95#ibcon#wrote, iclass 36, count 2 2006.169.08:29:55.95#ibcon#about to read 3, iclass 36, count 2 2006.169.08:29:55.97#ibcon#read 3, iclass 36, count 2 2006.169.08:29:55.97#ibcon#about to read 4, iclass 36, count 2 2006.169.08:29:55.97#ibcon#read 4, iclass 36, count 2 2006.169.08:29:55.97#ibcon#about to read 5, iclass 36, count 2 2006.169.08:29:55.97#ibcon#read 5, iclass 36, count 2 2006.169.08:29:55.97#ibcon#about to read 6, iclass 36, count 2 2006.169.08:29:55.97#ibcon#read 6, iclass 36, count 2 2006.169.08:29:55.97#ibcon#end of sib2, iclass 36, count 2 2006.169.08:29:55.97#ibcon#*mode == 0, iclass 36, count 2 2006.169.08:29:55.97#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.169.08:29:55.97#ibcon#[25=AT04-07\r\n] 2006.169.08:29:55.97#ibcon#*before write, iclass 36, count 2 2006.169.08:29:55.97#ibcon#enter sib2, iclass 36, count 2 2006.169.08:29:55.97#ibcon#flushed, iclass 36, count 2 2006.169.08:29:55.97#ibcon#about to write, iclass 36, count 2 2006.169.08:29:55.97#ibcon#wrote, iclass 36, count 2 2006.169.08:29:55.97#ibcon#about to read 3, iclass 36, count 2 2006.169.08:29:56.00#ibcon#read 3, iclass 36, count 2 2006.169.08:29:56.00#ibcon#about to read 4, iclass 36, count 2 2006.169.08:29:56.00#ibcon#read 4, iclass 36, count 2 2006.169.08:29:56.00#ibcon#about to read 5, iclass 36, count 2 2006.169.08:29:56.00#ibcon#read 5, iclass 36, count 2 2006.169.08:29:56.00#ibcon#about to read 6, iclass 36, count 2 2006.169.08:29:56.00#ibcon#read 6, iclass 36, count 2 2006.169.08:29:56.00#ibcon#end of sib2, iclass 36, count 2 2006.169.08:29:56.00#ibcon#*after write, iclass 36, count 2 2006.169.08:29:56.00#ibcon#*before return 0, iclass 36, count 2 2006.169.08:29:56.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.169.08:29:56.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.169.08:29:56.00#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.169.08:29:56.00#ibcon#ireg 7 cls_cnt 0 2006.169.08:29:56.00#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.169.08:29:56.12#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.169.08:29:56.12#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.169.08:29:56.12#ibcon#enter wrdev, iclass 36, count 0 2006.169.08:29:56.12#ibcon#first serial, iclass 36, count 0 2006.169.08:29:56.12#ibcon#enter sib2, iclass 36, count 0 2006.169.08:29:56.12#ibcon#flushed, iclass 36, count 0 2006.169.08:29:56.12#ibcon#about to write, iclass 36, count 0 2006.169.08:29:56.12#ibcon#wrote, iclass 36, count 0 2006.169.08:29:56.12#ibcon#about to read 3, iclass 36, count 0 2006.169.08:29:56.14#ibcon#read 3, iclass 36, count 0 2006.169.08:29:56.14#ibcon#about to read 4, iclass 36, count 0 2006.169.08:29:56.14#ibcon#read 4, iclass 36, count 0 2006.169.08:29:56.14#ibcon#about to read 5, iclass 36, count 0 2006.169.08:29:56.14#ibcon#read 5, iclass 36, count 0 2006.169.08:29:56.14#ibcon#about to read 6, iclass 36, count 0 2006.169.08:29:56.14#ibcon#read 6, iclass 36, count 0 2006.169.08:29:56.14#ibcon#end of sib2, iclass 36, count 0 2006.169.08:29:56.14#ibcon#*mode == 0, iclass 36, count 0 2006.169.08:29:56.14#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.169.08:29:56.14#ibcon#[25=USB\r\n] 2006.169.08:29:56.14#ibcon#*before write, iclass 36, count 0 2006.169.08:29:56.14#ibcon#enter sib2, iclass 36, count 0 2006.169.08:29:56.14#ibcon#flushed, iclass 36, count 0 2006.169.08:29:56.14#ibcon#about to write, iclass 36, count 0 2006.169.08:29:56.14#ibcon#wrote, iclass 36, count 0 2006.169.08:29:56.14#ibcon#about to read 3, iclass 36, count 0 2006.169.08:29:56.17#ibcon#read 3, iclass 36, count 0 2006.169.08:29:56.17#ibcon#about to read 4, iclass 36, count 0 2006.169.08:29:56.17#ibcon#read 4, iclass 36, count 0 2006.169.08:29:56.17#ibcon#about to read 5, iclass 36, count 0 2006.169.08:29:56.17#ibcon#read 5, iclass 36, count 0 2006.169.08:29:56.17#ibcon#about to read 6, iclass 36, count 0 2006.169.08:29:56.17#ibcon#read 6, iclass 36, count 0 2006.169.08:29:56.17#ibcon#end of sib2, iclass 36, count 0 2006.169.08:29:56.17#ibcon#*after write, iclass 36, count 0 2006.169.08:29:56.17#ibcon#*before return 0, iclass 36, count 0 2006.169.08:29:56.17#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.169.08:29:56.17#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.169.08:29:56.17#ibcon#about to clear, iclass 36 cls_cnt 0 2006.169.08:29:56.17#ibcon#cleared, iclass 36 cls_cnt 0 2006.169.08:29:56.17$vc4f8/valo=5,652.99 2006.169.08:29:56.17#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.169.08:29:56.17#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.169.08:29:56.17#ibcon#ireg 17 cls_cnt 0 2006.169.08:29:56.17#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.169.08:29:56.17#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.169.08:29:56.17#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.169.08:29:56.17#ibcon#enter wrdev, iclass 38, count 0 2006.169.08:29:56.17#ibcon#first serial, iclass 38, count 0 2006.169.08:29:56.17#ibcon#enter sib2, iclass 38, count 0 2006.169.08:29:56.17#ibcon#flushed, iclass 38, count 0 2006.169.08:29:56.17#ibcon#about to write, iclass 38, count 0 2006.169.08:29:56.17#ibcon#wrote, iclass 38, count 0 2006.169.08:29:56.17#ibcon#about to read 3, iclass 38, count 0 2006.169.08:29:56.19#ibcon#read 3, iclass 38, count 0 2006.169.08:29:56.19#ibcon#about to read 4, iclass 38, count 0 2006.169.08:29:56.19#ibcon#read 4, iclass 38, count 0 2006.169.08:29:56.19#ibcon#about to read 5, iclass 38, count 0 2006.169.08:29:56.19#ibcon#read 5, iclass 38, count 0 2006.169.08:29:56.19#ibcon#about to read 6, iclass 38, count 0 2006.169.08:29:56.19#ibcon#read 6, iclass 38, count 0 2006.169.08:29:56.19#ibcon#end of sib2, iclass 38, count 0 2006.169.08:29:56.19#ibcon#*mode == 0, iclass 38, count 0 2006.169.08:29:56.19#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.169.08:29:56.19#ibcon#[26=FRQ=05,652.99\r\n] 2006.169.08:29:56.19#ibcon#*before write, iclass 38, count 0 2006.169.08:29:56.19#ibcon#enter sib2, iclass 38, count 0 2006.169.08:29:56.19#ibcon#flushed, iclass 38, count 0 2006.169.08:29:56.19#ibcon#about to write, iclass 38, count 0 2006.169.08:29:56.19#ibcon#wrote, iclass 38, count 0 2006.169.08:29:56.19#ibcon#about to read 3, iclass 38, count 0 2006.169.08:29:56.23#ibcon#read 3, iclass 38, count 0 2006.169.08:29:56.23#ibcon#about to read 4, iclass 38, count 0 2006.169.08:29:56.23#ibcon#read 4, iclass 38, count 0 2006.169.08:29:56.23#ibcon#about to read 5, iclass 38, count 0 2006.169.08:29:56.23#ibcon#read 5, iclass 38, count 0 2006.169.08:29:56.23#ibcon#about to read 6, iclass 38, count 0 2006.169.08:29:56.23#ibcon#read 6, iclass 38, count 0 2006.169.08:29:56.23#ibcon#end of sib2, iclass 38, count 0 2006.169.08:29:56.23#ibcon#*after write, iclass 38, count 0 2006.169.08:29:56.23#ibcon#*before return 0, iclass 38, count 0 2006.169.08:29:56.23#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.169.08:29:56.23#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.169.08:29:56.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.169.08:29:56.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.169.08:29:56.23$vc4f8/va=5,7 2006.169.08:29:56.23#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.169.08:29:56.23#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.169.08:29:56.23#ibcon#ireg 11 cls_cnt 2 2006.169.08:29:56.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.169.08:29:56.30#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.169.08:29:56.30#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.169.08:29:56.30#ibcon#enter wrdev, iclass 40, count 2 2006.169.08:29:56.30#ibcon#first serial, iclass 40, count 2 2006.169.08:29:56.30#ibcon#enter sib2, iclass 40, count 2 2006.169.08:29:56.30#ibcon#flushed, iclass 40, count 2 2006.169.08:29:56.30#ibcon#about to write, iclass 40, count 2 2006.169.08:29:56.30#ibcon#wrote, iclass 40, count 2 2006.169.08:29:56.30#ibcon#about to read 3, iclass 40, count 2 2006.169.08:29:56.31#ibcon#read 3, iclass 40, count 2 2006.169.08:29:56.31#ibcon#about to read 4, iclass 40, count 2 2006.169.08:29:56.31#ibcon#read 4, iclass 40, count 2 2006.169.08:29:56.31#ibcon#about to read 5, iclass 40, count 2 2006.169.08:29:56.31#ibcon#read 5, iclass 40, count 2 2006.169.08:29:56.31#ibcon#about to read 6, iclass 40, count 2 2006.169.08:29:56.31#ibcon#read 6, iclass 40, count 2 2006.169.08:29:56.31#ibcon#end of sib2, iclass 40, count 2 2006.169.08:29:56.31#ibcon#*mode == 0, iclass 40, count 2 2006.169.08:29:56.31#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.169.08:29:56.31#ibcon#[25=AT05-07\r\n] 2006.169.08:29:56.31#ibcon#*before write, iclass 40, count 2 2006.169.08:29:56.31#ibcon#enter sib2, iclass 40, count 2 2006.169.08:29:56.31#ibcon#flushed, iclass 40, count 2 2006.169.08:29:56.31#ibcon#about to write, iclass 40, count 2 2006.169.08:29:56.31#ibcon#wrote, iclass 40, count 2 2006.169.08:29:56.31#ibcon#about to read 3, iclass 40, count 2 2006.169.08:29:56.34#ibcon#read 3, iclass 40, count 2 2006.169.08:29:56.34#ibcon#about to read 4, iclass 40, count 2 2006.169.08:29:56.34#ibcon#read 4, iclass 40, count 2 2006.169.08:29:56.34#ibcon#about to read 5, iclass 40, count 2 2006.169.08:29:56.34#ibcon#read 5, iclass 40, count 2 2006.169.08:29:56.34#ibcon#about to read 6, iclass 40, count 2 2006.169.08:29:56.34#ibcon#read 6, iclass 40, count 2 2006.169.08:29:56.34#ibcon#end of sib2, iclass 40, count 2 2006.169.08:29:56.34#ibcon#*after write, iclass 40, count 2 2006.169.08:29:56.34#ibcon#*before return 0, iclass 40, count 2 2006.169.08:29:56.34#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.169.08:29:56.34#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.169.08:29:56.34#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.169.08:29:56.34#ibcon#ireg 7 cls_cnt 0 2006.169.08:29:56.34#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.169.08:29:56.46#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.169.08:29:56.46#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.169.08:29:56.46#ibcon#enter wrdev, iclass 40, count 0 2006.169.08:29:56.46#ibcon#first serial, iclass 40, count 0 2006.169.08:29:56.46#ibcon#enter sib2, iclass 40, count 0 2006.169.08:29:56.46#ibcon#flushed, iclass 40, count 0 2006.169.08:29:56.46#ibcon#about to write, iclass 40, count 0 2006.169.08:29:56.46#ibcon#wrote, iclass 40, count 0 2006.169.08:29:56.46#ibcon#about to read 3, iclass 40, count 0 2006.169.08:29:56.48#ibcon#read 3, iclass 40, count 0 2006.169.08:29:56.48#ibcon#about to read 4, iclass 40, count 0 2006.169.08:29:56.48#ibcon#read 4, iclass 40, count 0 2006.169.08:29:56.48#ibcon#about to read 5, iclass 40, count 0 2006.169.08:29:56.48#ibcon#read 5, iclass 40, count 0 2006.169.08:29:56.48#ibcon#about to read 6, iclass 40, count 0 2006.169.08:29:56.48#ibcon#read 6, iclass 40, count 0 2006.169.08:29:56.48#ibcon#end of sib2, iclass 40, count 0 2006.169.08:29:56.48#ibcon#*mode == 0, iclass 40, count 0 2006.169.08:29:56.48#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.169.08:29:56.48#ibcon#[25=USB\r\n] 2006.169.08:29:56.48#ibcon#*before write, iclass 40, count 0 2006.169.08:29:56.48#ibcon#enter sib2, iclass 40, count 0 2006.169.08:29:56.48#ibcon#flushed, iclass 40, count 0 2006.169.08:29:56.48#ibcon#about to write, iclass 40, count 0 2006.169.08:29:56.48#ibcon#wrote, iclass 40, count 0 2006.169.08:29:56.48#ibcon#about to read 3, iclass 40, count 0 2006.169.08:29:56.51#ibcon#read 3, iclass 40, count 0 2006.169.08:29:56.51#ibcon#about to read 4, iclass 40, count 0 2006.169.08:29:56.51#ibcon#read 4, iclass 40, count 0 2006.169.08:29:56.51#ibcon#about to read 5, iclass 40, count 0 2006.169.08:29:56.51#ibcon#read 5, iclass 40, count 0 2006.169.08:29:56.51#ibcon#about to read 6, iclass 40, count 0 2006.169.08:29:56.51#ibcon#read 6, iclass 40, count 0 2006.169.08:29:56.51#ibcon#end of sib2, iclass 40, count 0 2006.169.08:29:56.51#ibcon#*after write, iclass 40, count 0 2006.169.08:29:56.51#ibcon#*before return 0, iclass 40, count 0 2006.169.08:29:56.51#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.169.08:29:56.51#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.169.08:29:56.51#ibcon#about to clear, iclass 40 cls_cnt 0 2006.169.08:29:56.51#ibcon#cleared, iclass 40 cls_cnt 0 2006.169.08:29:56.51$vc4f8/valo=6,772.99 2006.169.08:29:56.51#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.169.08:29:56.51#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.169.08:29:56.51#ibcon#ireg 17 cls_cnt 0 2006.169.08:29:56.51#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:29:56.51#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:29:56.51#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:29:56.51#ibcon#enter wrdev, iclass 4, count 0 2006.169.08:29:56.51#ibcon#first serial, iclass 4, count 0 2006.169.08:29:56.51#ibcon#enter sib2, iclass 4, count 0 2006.169.08:29:56.51#ibcon#flushed, iclass 4, count 0 2006.169.08:29:56.51#ibcon#about to write, iclass 4, count 0 2006.169.08:29:56.51#ibcon#wrote, iclass 4, count 0 2006.169.08:29:56.51#ibcon#about to read 3, iclass 4, count 0 2006.169.08:29:56.53#ibcon#read 3, iclass 4, count 0 2006.169.08:29:56.53#ibcon#about to read 4, iclass 4, count 0 2006.169.08:29:56.53#ibcon#read 4, iclass 4, count 0 2006.169.08:29:56.53#ibcon#about to read 5, iclass 4, count 0 2006.169.08:29:56.53#ibcon#read 5, iclass 4, count 0 2006.169.08:29:56.53#ibcon#about to read 6, iclass 4, count 0 2006.169.08:29:56.53#ibcon#read 6, iclass 4, count 0 2006.169.08:29:56.53#ibcon#end of sib2, iclass 4, count 0 2006.169.08:29:56.53#ibcon#*mode == 0, iclass 4, count 0 2006.169.08:29:56.53#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.169.08:29:56.53#ibcon#[26=FRQ=06,772.99\r\n] 2006.169.08:29:56.53#ibcon#*before write, iclass 4, count 0 2006.169.08:29:56.53#ibcon#enter sib2, iclass 4, count 0 2006.169.08:29:56.53#ibcon#flushed, iclass 4, count 0 2006.169.08:29:56.53#ibcon#about to write, iclass 4, count 0 2006.169.08:29:56.53#ibcon#wrote, iclass 4, count 0 2006.169.08:29:56.53#ibcon#about to read 3, iclass 4, count 0 2006.169.08:29:56.57#ibcon#read 3, iclass 4, count 0 2006.169.08:29:56.57#ibcon#about to read 4, iclass 4, count 0 2006.169.08:29:56.57#ibcon#read 4, iclass 4, count 0 2006.169.08:29:56.57#ibcon#about to read 5, iclass 4, count 0 2006.169.08:29:56.57#ibcon#read 5, iclass 4, count 0 2006.169.08:29:56.57#ibcon#about to read 6, iclass 4, count 0 2006.169.08:29:56.57#ibcon#read 6, iclass 4, count 0 2006.169.08:29:56.57#ibcon#end of sib2, iclass 4, count 0 2006.169.08:29:56.57#ibcon#*after write, iclass 4, count 0 2006.169.08:29:56.57#ibcon#*before return 0, iclass 4, count 0 2006.169.08:29:56.57#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:29:56.57#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:29:56.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.169.08:29:56.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.169.08:29:56.57$vc4f8/va=6,6 2006.169.08:29:56.57#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.169.08:29:56.57#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.169.08:29:56.57#ibcon#ireg 11 cls_cnt 2 2006.169.08:29:56.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.169.08:29:56.63#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.169.08:29:56.63#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.169.08:29:56.63#ibcon#enter wrdev, iclass 6, count 2 2006.169.08:29:56.63#ibcon#first serial, iclass 6, count 2 2006.169.08:29:56.63#ibcon#enter sib2, iclass 6, count 2 2006.169.08:29:56.63#ibcon#flushed, iclass 6, count 2 2006.169.08:29:56.63#ibcon#about to write, iclass 6, count 2 2006.169.08:29:56.63#ibcon#wrote, iclass 6, count 2 2006.169.08:29:56.63#ibcon#about to read 3, iclass 6, count 2 2006.169.08:29:56.65#ibcon#read 3, iclass 6, count 2 2006.169.08:29:56.65#ibcon#about to read 4, iclass 6, count 2 2006.169.08:29:56.65#ibcon#read 4, iclass 6, count 2 2006.169.08:29:56.65#ibcon#about to read 5, iclass 6, count 2 2006.169.08:29:56.65#ibcon#read 5, iclass 6, count 2 2006.169.08:29:56.65#ibcon#about to read 6, iclass 6, count 2 2006.169.08:29:56.65#ibcon#read 6, iclass 6, count 2 2006.169.08:29:56.65#ibcon#end of sib2, iclass 6, count 2 2006.169.08:29:56.65#ibcon#*mode == 0, iclass 6, count 2 2006.169.08:29:56.65#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.169.08:29:56.65#ibcon#[25=AT06-06\r\n] 2006.169.08:29:56.65#ibcon#*before write, iclass 6, count 2 2006.169.08:29:56.65#ibcon#enter sib2, iclass 6, count 2 2006.169.08:29:56.65#ibcon#flushed, iclass 6, count 2 2006.169.08:29:56.65#ibcon#about to write, iclass 6, count 2 2006.169.08:29:56.65#ibcon#wrote, iclass 6, count 2 2006.169.08:29:56.65#ibcon#about to read 3, iclass 6, count 2 2006.169.08:29:56.68#ibcon#read 3, iclass 6, count 2 2006.169.08:29:56.68#ibcon#about to read 4, iclass 6, count 2 2006.169.08:29:56.68#ibcon#read 4, iclass 6, count 2 2006.169.08:29:56.68#ibcon#about to read 5, iclass 6, count 2 2006.169.08:29:56.68#ibcon#read 5, iclass 6, count 2 2006.169.08:29:56.68#ibcon#about to read 6, iclass 6, count 2 2006.169.08:29:56.68#ibcon#read 6, iclass 6, count 2 2006.169.08:29:56.68#ibcon#end of sib2, iclass 6, count 2 2006.169.08:29:56.68#ibcon#*after write, iclass 6, count 2 2006.169.08:29:56.68#ibcon#*before return 0, iclass 6, count 2 2006.169.08:29:56.68#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.169.08:29:56.68#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.169.08:29:56.68#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.169.08:29:56.68#ibcon#ireg 7 cls_cnt 0 2006.169.08:29:56.68#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.169.08:29:56.80#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.169.08:29:56.80#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.169.08:29:56.80#ibcon#enter wrdev, iclass 6, count 0 2006.169.08:29:56.80#ibcon#first serial, iclass 6, count 0 2006.169.08:29:56.80#ibcon#enter sib2, iclass 6, count 0 2006.169.08:29:56.80#ibcon#flushed, iclass 6, count 0 2006.169.08:29:56.80#ibcon#about to write, iclass 6, count 0 2006.169.08:29:56.80#ibcon#wrote, iclass 6, count 0 2006.169.08:29:56.80#ibcon#about to read 3, iclass 6, count 0 2006.169.08:29:56.82#ibcon#read 3, iclass 6, count 0 2006.169.08:29:56.82#ibcon#about to read 4, iclass 6, count 0 2006.169.08:29:56.82#ibcon#read 4, iclass 6, count 0 2006.169.08:29:56.82#ibcon#about to read 5, iclass 6, count 0 2006.169.08:29:56.82#ibcon#read 5, iclass 6, count 0 2006.169.08:29:56.82#ibcon#about to read 6, iclass 6, count 0 2006.169.08:29:56.82#ibcon#read 6, iclass 6, count 0 2006.169.08:29:56.82#ibcon#end of sib2, iclass 6, count 0 2006.169.08:29:56.82#ibcon#*mode == 0, iclass 6, count 0 2006.169.08:29:56.82#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.169.08:29:56.82#ibcon#[25=USB\r\n] 2006.169.08:29:56.82#ibcon#*before write, iclass 6, count 0 2006.169.08:29:56.82#ibcon#enter sib2, iclass 6, count 0 2006.169.08:29:56.82#ibcon#flushed, iclass 6, count 0 2006.169.08:29:56.82#ibcon#about to write, iclass 6, count 0 2006.169.08:29:56.82#ibcon#wrote, iclass 6, count 0 2006.169.08:29:56.82#ibcon#about to read 3, iclass 6, count 0 2006.169.08:29:56.85#ibcon#read 3, iclass 6, count 0 2006.169.08:29:56.85#ibcon#about to read 4, iclass 6, count 0 2006.169.08:29:56.85#ibcon#read 4, iclass 6, count 0 2006.169.08:29:56.85#ibcon#about to read 5, iclass 6, count 0 2006.169.08:29:56.85#ibcon#read 5, iclass 6, count 0 2006.169.08:29:56.85#ibcon#about to read 6, iclass 6, count 0 2006.169.08:29:56.85#ibcon#read 6, iclass 6, count 0 2006.169.08:29:56.85#ibcon#end of sib2, iclass 6, count 0 2006.169.08:29:56.85#ibcon#*after write, iclass 6, count 0 2006.169.08:29:56.85#ibcon#*before return 0, iclass 6, count 0 2006.169.08:29:56.85#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.169.08:29:56.85#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.169.08:29:56.85#ibcon#about to clear, iclass 6 cls_cnt 0 2006.169.08:29:56.85#ibcon#cleared, iclass 6 cls_cnt 0 2006.169.08:29:56.85$vc4f8/valo=7,832.99 2006.169.08:29:56.85#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.169.08:29:56.85#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.169.08:29:56.85#ibcon#ireg 17 cls_cnt 0 2006.169.08:29:56.85#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.169.08:29:56.85#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.169.08:29:56.85#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.169.08:29:56.85#ibcon#enter wrdev, iclass 10, count 0 2006.169.08:29:56.85#ibcon#first serial, iclass 10, count 0 2006.169.08:29:56.85#ibcon#enter sib2, iclass 10, count 0 2006.169.08:29:56.85#ibcon#flushed, iclass 10, count 0 2006.169.08:29:56.85#ibcon#about to write, iclass 10, count 0 2006.169.08:29:56.85#ibcon#wrote, iclass 10, count 0 2006.169.08:29:56.85#ibcon#about to read 3, iclass 10, count 0 2006.169.08:29:56.87#ibcon#read 3, iclass 10, count 0 2006.169.08:29:56.87#ibcon#about to read 4, iclass 10, count 0 2006.169.08:29:56.87#ibcon#read 4, iclass 10, count 0 2006.169.08:29:56.87#ibcon#about to read 5, iclass 10, count 0 2006.169.08:29:56.87#ibcon#read 5, iclass 10, count 0 2006.169.08:29:56.87#ibcon#about to read 6, iclass 10, count 0 2006.169.08:29:56.87#ibcon#read 6, iclass 10, count 0 2006.169.08:29:56.87#ibcon#end of sib2, iclass 10, count 0 2006.169.08:29:56.87#ibcon#*mode == 0, iclass 10, count 0 2006.169.08:29:56.87#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.169.08:29:56.87#ibcon#[26=FRQ=07,832.99\r\n] 2006.169.08:29:56.87#ibcon#*before write, iclass 10, count 0 2006.169.08:29:56.87#ibcon#enter sib2, iclass 10, count 0 2006.169.08:29:56.87#ibcon#flushed, iclass 10, count 0 2006.169.08:29:56.87#ibcon#about to write, iclass 10, count 0 2006.169.08:29:56.87#ibcon#wrote, iclass 10, count 0 2006.169.08:29:56.87#ibcon#about to read 3, iclass 10, count 0 2006.169.08:29:56.91#ibcon#read 3, iclass 10, count 0 2006.169.08:29:56.91#ibcon#about to read 4, iclass 10, count 0 2006.169.08:29:56.91#ibcon#read 4, iclass 10, count 0 2006.169.08:29:56.91#ibcon#about to read 5, iclass 10, count 0 2006.169.08:29:56.91#ibcon#read 5, iclass 10, count 0 2006.169.08:29:56.91#ibcon#about to read 6, iclass 10, count 0 2006.169.08:29:56.91#ibcon#read 6, iclass 10, count 0 2006.169.08:29:56.91#ibcon#end of sib2, iclass 10, count 0 2006.169.08:29:56.91#ibcon#*after write, iclass 10, count 0 2006.169.08:29:56.91#ibcon#*before return 0, iclass 10, count 0 2006.169.08:29:56.91#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.169.08:29:56.91#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.169.08:29:56.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.169.08:29:56.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.169.08:29:56.91$vc4f8/va=7,6 2006.169.08:29:56.91#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.169.08:29:56.91#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.169.08:29:56.91#ibcon#ireg 11 cls_cnt 2 2006.169.08:29:56.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.169.08:29:56.98#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.169.08:29:56.98#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.169.08:29:56.98#ibcon#enter wrdev, iclass 12, count 2 2006.169.08:29:56.98#ibcon#first serial, iclass 12, count 2 2006.169.08:29:56.98#ibcon#enter sib2, iclass 12, count 2 2006.169.08:29:56.98#ibcon#flushed, iclass 12, count 2 2006.169.08:29:56.98#ibcon#about to write, iclass 12, count 2 2006.169.08:29:56.98#ibcon#wrote, iclass 12, count 2 2006.169.08:29:56.98#ibcon#about to read 3, iclass 12, count 2 2006.169.08:29:56.99#ibcon#read 3, iclass 12, count 2 2006.169.08:29:56.99#ibcon#about to read 4, iclass 12, count 2 2006.169.08:29:56.99#ibcon#read 4, iclass 12, count 2 2006.169.08:29:56.99#ibcon#about to read 5, iclass 12, count 2 2006.169.08:29:56.99#ibcon#read 5, iclass 12, count 2 2006.169.08:29:56.99#ibcon#about to read 6, iclass 12, count 2 2006.169.08:29:56.99#ibcon#read 6, iclass 12, count 2 2006.169.08:29:56.99#ibcon#end of sib2, iclass 12, count 2 2006.169.08:29:56.99#ibcon#*mode == 0, iclass 12, count 2 2006.169.08:29:56.99#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.169.08:29:56.99#ibcon#[25=AT07-06\r\n] 2006.169.08:29:56.99#ibcon#*before write, iclass 12, count 2 2006.169.08:29:56.99#ibcon#enter sib2, iclass 12, count 2 2006.169.08:29:56.99#ibcon#flushed, iclass 12, count 2 2006.169.08:29:56.99#ibcon#about to write, iclass 12, count 2 2006.169.08:29:56.99#ibcon#wrote, iclass 12, count 2 2006.169.08:29:56.99#ibcon#about to read 3, iclass 12, count 2 2006.169.08:29:57.02#ibcon#read 3, iclass 12, count 2 2006.169.08:29:57.02#ibcon#about to read 4, iclass 12, count 2 2006.169.08:29:57.02#ibcon#read 4, iclass 12, count 2 2006.169.08:29:57.02#ibcon#about to read 5, iclass 12, count 2 2006.169.08:29:57.02#ibcon#read 5, iclass 12, count 2 2006.169.08:29:57.02#ibcon#about to read 6, iclass 12, count 2 2006.169.08:29:57.02#ibcon#read 6, iclass 12, count 2 2006.169.08:29:57.02#ibcon#end of sib2, iclass 12, count 2 2006.169.08:29:57.02#ibcon#*after write, iclass 12, count 2 2006.169.08:29:57.02#ibcon#*before return 0, iclass 12, count 2 2006.169.08:29:57.02#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.169.08:29:57.02#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.169.08:29:57.02#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.169.08:29:57.02#ibcon#ireg 7 cls_cnt 0 2006.169.08:29:57.02#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.169.08:29:57.14#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.169.08:29:57.14#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.169.08:29:57.14#ibcon#enter wrdev, iclass 12, count 0 2006.169.08:29:57.14#ibcon#first serial, iclass 12, count 0 2006.169.08:29:57.14#ibcon#enter sib2, iclass 12, count 0 2006.169.08:29:57.14#ibcon#flushed, iclass 12, count 0 2006.169.08:29:57.14#ibcon#about to write, iclass 12, count 0 2006.169.08:29:57.14#ibcon#wrote, iclass 12, count 0 2006.169.08:29:57.14#ibcon#about to read 3, iclass 12, count 0 2006.169.08:29:57.16#ibcon#read 3, iclass 12, count 0 2006.169.08:29:57.16#ibcon#about to read 4, iclass 12, count 0 2006.169.08:29:57.16#ibcon#read 4, iclass 12, count 0 2006.169.08:29:57.16#ibcon#about to read 5, iclass 12, count 0 2006.169.08:29:57.16#ibcon#read 5, iclass 12, count 0 2006.169.08:29:57.16#ibcon#about to read 6, iclass 12, count 0 2006.169.08:29:57.16#ibcon#read 6, iclass 12, count 0 2006.169.08:29:57.16#ibcon#end of sib2, iclass 12, count 0 2006.169.08:29:57.16#ibcon#*mode == 0, iclass 12, count 0 2006.169.08:29:57.16#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.169.08:29:57.16#ibcon#[25=USB\r\n] 2006.169.08:29:57.16#ibcon#*before write, iclass 12, count 0 2006.169.08:29:57.16#ibcon#enter sib2, iclass 12, count 0 2006.169.08:29:57.16#ibcon#flushed, iclass 12, count 0 2006.169.08:29:57.16#ibcon#about to write, iclass 12, count 0 2006.169.08:29:57.16#ibcon#wrote, iclass 12, count 0 2006.169.08:29:57.16#ibcon#about to read 3, iclass 12, count 0 2006.169.08:29:57.19#ibcon#read 3, iclass 12, count 0 2006.169.08:29:57.19#ibcon#about to read 4, iclass 12, count 0 2006.169.08:29:57.19#ibcon#read 4, iclass 12, count 0 2006.169.08:29:57.19#ibcon#about to read 5, iclass 12, count 0 2006.169.08:29:57.19#ibcon#read 5, iclass 12, count 0 2006.169.08:29:57.19#ibcon#about to read 6, iclass 12, count 0 2006.169.08:29:57.19#ibcon#read 6, iclass 12, count 0 2006.169.08:29:57.19#ibcon#end of sib2, iclass 12, count 0 2006.169.08:29:57.19#ibcon#*after write, iclass 12, count 0 2006.169.08:29:57.19#ibcon#*before return 0, iclass 12, count 0 2006.169.08:29:57.19#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.169.08:29:57.19#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.169.08:29:57.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.169.08:29:57.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.169.08:29:57.19$vc4f8/valo=8,852.99 2006.169.08:29:57.19#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.169.08:29:57.19#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.169.08:29:57.19#ibcon#ireg 17 cls_cnt 0 2006.169.08:29:57.19#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:29:57.19#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:29:57.19#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:29:57.19#ibcon#enter wrdev, iclass 14, count 0 2006.169.08:29:57.19#ibcon#first serial, iclass 14, count 0 2006.169.08:29:57.19#ibcon#enter sib2, iclass 14, count 0 2006.169.08:29:57.19#ibcon#flushed, iclass 14, count 0 2006.169.08:29:57.19#ibcon#about to write, iclass 14, count 0 2006.169.08:29:57.19#ibcon#wrote, iclass 14, count 0 2006.169.08:29:57.19#ibcon#about to read 3, iclass 14, count 0 2006.169.08:29:57.22#ibcon#read 3, iclass 14, count 0 2006.169.08:29:57.22#ibcon#about to read 4, iclass 14, count 0 2006.169.08:29:57.22#ibcon#read 4, iclass 14, count 0 2006.169.08:29:57.22#ibcon#about to read 5, iclass 14, count 0 2006.169.08:29:57.22#ibcon#read 5, iclass 14, count 0 2006.169.08:29:57.22#ibcon#about to read 6, iclass 14, count 0 2006.169.08:29:57.22#ibcon#read 6, iclass 14, count 0 2006.169.08:29:57.22#ibcon#end of sib2, iclass 14, count 0 2006.169.08:29:57.22#ibcon#*mode == 0, iclass 14, count 0 2006.169.08:29:57.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.169.08:29:57.22#ibcon#[26=FRQ=08,852.99\r\n] 2006.169.08:29:57.22#ibcon#*before write, iclass 14, count 0 2006.169.08:29:57.22#ibcon#enter sib2, iclass 14, count 0 2006.169.08:29:57.22#ibcon#flushed, iclass 14, count 0 2006.169.08:29:57.22#ibcon#about to write, iclass 14, count 0 2006.169.08:29:57.22#ibcon#wrote, iclass 14, count 0 2006.169.08:29:57.22#ibcon#about to read 3, iclass 14, count 0 2006.169.08:29:57.26#ibcon#read 3, iclass 14, count 0 2006.169.08:29:57.26#ibcon#about to read 4, iclass 14, count 0 2006.169.08:29:57.26#ibcon#read 4, iclass 14, count 0 2006.169.08:29:57.26#ibcon#about to read 5, iclass 14, count 0 2006.169.08:29:57.26#ibcon#read 5, iclass 14, count 0 2006.169.08:29:57.26#ibcon#about to read 6, iclass 14, count 0 2006.169.08:29:57.26#ibcon#read 6, iclass 14, count 0 2006.169.08:29:57.26#ibcon#end of sib2, iclass 14, count 0 2006.169.08:29:57.26#ibcon#*after write, iclass 14, count 0 2006.169.08:29:57.26#ibcon#*before return 0, iclass 14, count 0 2006.169.08:29:57.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:29:57.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.169.08:29:57.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.169.08:29:57.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.169.08:29:57.26$vc4f8/va=8,7 2006.169.08:29:57.26#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.169.08:29:57.26#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.169.08:29:57.26#ibcon#ireg 11 cls_cnt 2 2006.169.08:29:57.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.169.08:29:57.31#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.169.08:29:57.31#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.169.08:29:57.31#ibcon#enter wrdev, iclass 16, count 2 2006.169.08:29:57.31#ibcon#first serial, iclass 16, count 2 2006.169.08:29:57.31#ibcon#enter sib2, iclass 16, count 2 2006.169.08:29:57.31#ibcon#flushed, iclass 16, count 2 2006.169.08:29:57.31#ibcon#about to write, iclass 16, count 2 2006.169.08:29:57.31#ibcon#wrote, iclass 16, count 2 2006.169.08:29:57.31#ibcon#about to read 3, iclass 16, count 2 2006.169.08:29:57.33#ibcon#read 3, iclass 16, count 2 2006.169.08:29:57.33#ibcon#about to read 4, iclass 16, count 2 2006.169.08:29:57.33#ibcon#read 4, iclass 16, count 2 2006.169.08:29:57.33#ibcon#about to read 5, iclass 16, count 2 2006.169.08:29:57.33#ibcon#read 5, iclass 16, count 2 2006.169.08:29:57.33#ibcon#about to read 6, iclass 16, count 2 2006.169.08:29:57.33#ibcon#read 6, iclass 16, count 2 2006.169.08:29:57.33#ibcon#end of sib2, iclass 16, count 2 2006.169.08:29:57.33#ibcon#*mode == 0, iclass 16, count 2 2006.169.08:29:57.33#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.169.08:29:57.33#ibcon#[25=AT08-07\r\n] 2006.169.08:29:57.33#ibcon#*before write, iclass 16, count 2 2006.169.08:29:57.33#ibcon#enter sib2, iclass 16, count 2 2006.169.08:29:57.33#ibcon#flushed, iclass 16, count 2 2006.169.08:29:57.33#ibcon#about to write, iclass 16, count 2 2006.169.08:29:57.33#ibcon#wrote, iclass 16, count 2 2006.169.08:29:57.33#ibcon#about to read 3, iclass 16, count 2 2006.169.08:29:57.36#ibcon#read 3, iclass 16, count 2 2006.169.08:29:57.36#ibcon#about to read 4, iclass 16, count 2 2006.169.08:29:57.36#ibcon#read 4, iclass 16, count 2 2006.169.08:29:57.36#ibcon#about to read 5, iclass 16, count 2 2006.169.08:29:57.36#ibcon#read 5, iclass 16, count 2 2006.169.08:29:57.36#ibcon#about to read 6, iclass 16, count 2 2006.169.08:29:57.36#ibcon#read 6, iclass 16, count 2 2006.169.08:29:57.36#ibcon#end of sib2, iclass 16, count 2 2006.169.08:29:57.36#ibcon#*after write, iclass 16, count 2 2006.169.08:29:57.36#ibcon#*before return 0, iclass 16, count 2 2006.169.08:29:57.36#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.169.08:29:57.36#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.169.08:29:57.36#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.169.08:29:57.36#ibcon#ireg 7 cls_cnt 0 2006.169.08:29:57.36#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.169.08:29:57.48#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.169.08:29:57.48#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.169.08:29:57.48#ibcon#enter wrdev, iclass 16, count 0 2006.169.08:29:57.48#ibcon#first serial, iclass 16, count 0 2006.169.08:29:57.48#ibcon#enter sib2, iclass 16, count 0 2006.169.08:29:57.48#ibcon#flushed, iclass 16, count 0 2006.169.08:29:57.48#ibcon#about to write, iclass 16, count 0 2006.169.08:29:57.48#ibcon#wrote, iclass 16, count 0 2006.169.08:29:57.48#ibcon#about to read 3, iclass 16, count 0 2006.169.08:29:57.50#ibcon#read 3, iclass 16, count 0 2006.169.08:29:57.50#ibcon#about to read 4, iclass 16, count 0 2006.169.08:29:57.50#ibcon#read 4, iclass 16, count 0 2006.169.08:29:57.50#ibcon#about to read 5, iclass 16, count 0 2006.169.08:29:57.50#ibcon#read 5, iclass 16, count 0 2006.169.08:29:57.50#ibcon#about to read 6, iclass 16, count 0 2006.169.08:29:57.50#ibcon#read 6, iclass 16, count 0 2006.169.08:29:57.50#ibcon#end of sib2, iclass 16, count 0 2006.169.08:29:57.50#ibcon#*mode == 0, iclass 16, count 0 2006.169.08:29:57.50#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.169.08:29:57.50#ibcon#[25=USB\r\n] 2006.169.08:29:57.50#ibcon#*before write, iclass 16, count 0 2006.169.08:29:57.50#ibcon#enter sib2, iclass 16, count 0 2006.169.08:29:57.50#ibcon#flushed, iclass 16, count 0 2006.169.08:29:57.50#ibcon#about to write, iclass 16, count 0 2006.169.08:29:57.50#ibcon#wrote, iclass 16, count 0 2006.169.08:29:57.50#ibcon#about to read 3, iclass 16, count 0 2006.169.08:29:57.53#ibcon#read 3, iclass 16, count 0 2006.169.08:29:57.53#ibcon#about to read 4, iclass 16, count 0 2006.169.08:29:57.53#ibcon#read 4, iclass 16, count 0 2006.169.08:29:57.53#ibcon#about to read 5, iclass 16, count 0 2006.169.08:29:57.53#ibcon#read 5, iclass 16, count 0 2006.169.08:29:57.53#ibcon#about to read 6, iclass 16, count 0 2006.169.08:29:57.53#ibcon#read 6, iclass 16, count 0 2006.169.08:29:57.53#ibcon#end of sib2, iclass 16, count 0 2006.169.08:29:57.53#ibcon#*after write, iclass 16, count 0 2006.169.08:29:57.53#ibcon#*before return 0, iclass 16, count 0 2006.169.08:29:57.53#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.169.08:29:57.53#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.169.08:29:57.53#ibcon#about to clear, iclass 16 cls_cnt 0 2006.169.08:29:57.53#ibcon#cleared, iclass 16 cls_cnt 0 2006.169.08:29:57.53$vc4f8/vblo=1,632.99 2006.169.08:29:57.53#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.169.08:29:57.53#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.169.08:29:57.53#ibcon#ireg 17 cls_cnt 0 2006.169.08:29:57.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:29:57.53#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:29:57.53#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:29:57.53#ibcon#enter wrdev, iclass 18, count 0 2006.169.08:29:57.53#ibcon#first serial, iclass 18, count 0 2006.169.08:29:57.53#ibcon#enter sib2, iclass 18, count 0 2006.169.08:29:57.53#ibcon#flushed, iclass 18, count 0 2006.169.08:29:57.53#ibcon#about to write, iclass 18, count 0 2006.169.08:29:57.53#ibcon#wrote, iclass 18, count 0 2006.169.08:29:57.53#ibcon#about to read 3, iclass 18, count 0 2006.169.08:29:57.55#ibcon#read 3, iclass 18, count 0 2006.169.08:29:57.55#ibcon#about to read 4, iclass 18, count 0 2006.169.08:29:57.55#ibcon#read 4, iclass 18, count 0 2006.169.08:29:57.55#ibcon#about to read 5, iclass 18, count 0 2006.169.08:29:57.55#ibcon#read 5, iclass 18, count 0 2006.169.08:29:57.55#ibcon#about to read 6, iclass 18, count 0 2006.169.08:29:57.55#ibcon#read 6, iclass 18, count 0 2006.169.08:29:57.55#ibcon#end of sib2, iclass 18, count 0 2006.169.08:29:57.55#ibcon#*mode == 0, iclass 18, count 0 2006.169.08:29:57.55#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.169.08:29:57.55#ibcon#[28=FRQ=01,632.99\r\n] 2006.169.08:29:57.55#ibcon#*before write, iclass 18, count 0 2006.169.08:29:57.55#ibcon#enter sib2, iclass 18, count 0 2006.169.08:29:57.55#ibcon#flushed, iclass 18, count 0 2006.169.08:29:57.55#ibcon#about to write, iclass 18, count 0 2006.169.08:29:57.55#ibcon#wrote, iclass 18, count 0 2006.169.08:29:57.55#ibcon#about to read 3, iclass 18, count 0 2006.169.08:29:57.59#ibcon#read 3, iclass 18, count 0 2006.169.08:29:57.59#ibcon#about to read 4, iclass 18, count 0 2006.169.08:29:57.59#ibcon#read 4, iclass 18, count 0 2006.169.08:29:57.59#ibcon#about to read 5, iclass 18, count 0 2006.169.08:29:57.59#ibcon#read 5, iclass 18, count 0 2006.169.08:29:57.59#ibcon#about to read 6, iclass 18, count 0 2006.169.08:29:57.59#ibcon#read 6, iclass 18, count 0 2006.169.08:29:57.59#ibcon#end of sib2, iclass 18, count 0 2006.169.08:29:57.59#ibcon#*after write, iclass 18, count 0 2006.169.08:29:57.59#ibcon#*before return 0, iclass 18, count 0 2006.169.08:29:57.59#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:29:57.59#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.169.08:29:57.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.169.08:29:57.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.169.08:29:57.59$vc4f8/vb=1,4 2006.169.08:29:57.59#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.169.08:29:57.59#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.169.08:29:57.59#ibcon#ireg 11 cls_cnt 2 2006.169.08:29:57.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.169.08:29:57.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.169.08:29:57.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.169.08:29:57.59#ibcon#enter wrdev, iclass 20, count 2 2006.169.08:29:57.59#ibcon#first serial, iclass 20, count 2 2006.169.08:29:57.59#ibcon#enter sib2, iclass 20, count 2 2006.169.08:29:57.59#ibcon#flushed, iclass 20, count 2 2006.169.08:29:57.59#ibcon#about to write, iclass 20, count 2 2006.169.08:29:57.59#ibcon#wrote, iclass 20, count 2 2006.169.08:29:57.59#ibcon#about to read 3, iclass 20, count 2 2006.169.08:29:57.61#ibcon#read 3, iclass 20, count 2 2006.169.08:29:57.61#ibcon#about to read 4, iclass 20, count 2 2006.169.08:29:57.61#ibcon#read 4, iclass 20, count 2 2006.169.08:29:57.61#ibcon#about to read 5, iclass 20, count 2 2006.169.08:29:57.61#ibcon#read 5, iclass 20, count 2 2006.169.08:29:57.61#ibcon#about to read 6, iclass 20, count 2 2006.169.08:29:57.61#ibcon#read 6, iclass 20, count 2 2006.169.08:29:57.61#ibcon#end of sib2, iclass 20, count 2 2006.169.08:29:57.61#ibcon#*mode == 0, iclass 20, count 2 2006.169.08:29:57.61#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.169.08:29:57.61#ibcon#[27=AT01-04\r\n] 2006.169.08:29:57.61#ibcon#*before write, iclass 20, count 2 2006.169.08:29:57.61#ibcon#enter sib2, iclass 20, count 2 2006.169.08:29:57.61#ibcon#flushed, iclass 20, count 2 2006.169.08:29:57.61#ibcon#about to write, iclass 20, count 2 2006.169.08:29:57.61#ibcon#wrote, iclass 20, count 2 2006.169.08:29:57.61#ibcon#about to read 3, iclass 20, count 2 2006.169.08:29:57.64#ibcon#read 3, iclass 20, count 2 2006.169.08:29:57.64#ibcon#about to read 4, iclass 20, count 2 2006.169.08:29:57.64#ibcon#read 4, iclass 20, count 2 2006.169.08:29:57.64#ibcon#about to read 5, iclass 20, count 2 2006.169.08:29:57.64#ibcon#read 5, iclass 20, count 2 2006.169.08:29:57.64#ibcon#about to read 6, iclass 20, count 2 2006.169.08:29:57.64#ibcon#read 6, iclass 20, count 2 2006.169.08:29:57.64#ibcon#end of sib2, iclass 20, count 2 2006.169.08:29:57.64#ibcon#*after write, iclass 20, count 2 2006.169.08:29:57.64#ibcon#*before return 0, iclass 20, count 2 2006.169.08:29:57.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.169.08:29:57.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.169.08:29:57.64#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.169.08:29:57.64#ibcon#ireg 7 cls_cnt 0 2006.169.08:29:57.64#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.169.08:29:57.76#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.169.08:29:57.76#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.169.08:29:57.76#ibcon#enter wrdev, iclass 20, count 0 2006.169.08:29:57.76#ibcon#first serial, iclass 20, count 0 2006.169.08:29:57.76#ibcon#enter sib2, iclass 20, count 0 2006.169.08:29:57.76#ibcon#flushed, iclass 20, count 0 2006.169.08:29:57.76#ibcon#about to write, iclass 20, count 0 2006.169.08:29:57.76#ibcon#wrote, iclass 20, count 0 2006.169.08:29:57.76#ibcon#about to read 3, iclass 20, count 0 2006.169.08:29:57.78#ibcon#read 3, iclass 20, count 0 2006.169.08:29:57.78#ibcon#about to read 4, iclass 20, count 0 2006.169.08:29:57.78#ibcon#read 4, iclass 20, count 0 2006.169.08:29:57.78#ibcon#about to read 5, iclass 20, count 0 2006.169.08:29:57.78#ibcon#read 5, iclass 20, count 0 2006.169.08:29:57.78#ibcon#about to read 6, iclass 20, count 0 2006.169.08:29:57.78#ibcon#read 6, iclass 20, count 0 2006.169.08:29:57.78#ibcon#end of sib2, iclass 20, count 0 2006.169.08:29:57.78#ibcon#*mode == 0, iclass 20, count 0 2006.169.08:29:57.78#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.169.08:29:57.78#ibcon#[27=USB\r\n] 2006.169.08:29:57.78#ibcon#*before write, iclass 20, count 0 2006.169.08:29:57.78#ibcon#enter sib2, iclass 20, count 0 2006.169.08:29:57.78#ibcon#flushed, iclass 20, count 0 2006.169.08:29:57.78#ibcon#about to write, iclass 20, count 0 2006.169.08:29:57.78#ibcon#wrote, iclass 20, count 0 2006.169.08:29:57.78#ibcon#about to read 3, iclass 20, count 0 2006.169.08:29:57.81#ibcon#read 3, iclass 20, count 0 2006.169.08:29:57.81#ibcon#about to read 4, iclass 20, count 0 2006.169.08:29:57.81#ibcon#read 4, iclass 20, count 0 2006.169.08:29:57.81#ibcon#about to read 5, iclass 20, count 0 2006.169.08:29:57.81#ibcon#read 5, iclass 20, count 0 2006.169.08:29:57.81#ibcon#about to read 6, iclass 20, count 0 2006.169.08:29:57.81#ibcon#read 6, iclass 20, count 0 2006.169.08:29:57.81#ibcon#end of sib2, iclass 20, count 0 2006.169.08:29:57.81#ibcon#*after write, iclass 20, count 0 2006.169.08:29:57.81#ibcon#*before return 0, iclass 20, count 0 2006.169.08:29:57.81#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.169.08:29:57.81#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.169.08:29:57.81#ibcon#about to clear, iclass 20 cls_cnt 0 2006.169.08:29:57.81#ibcon#cleared, iclass 20 cls_cnt 0 2006.169.08:29:57.81$vc4f8/vblo=2,640.99 2006.169.08:29:57.81#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.169.08:29:57.81#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.169.08:29:57.81#ibcon#ireg 17 cls_cnt 0 2006.169.08:29:57.81#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.169.08:29:57.81#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.169.08:29:57.81#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.169.08:29:57.81#ibcon#enter wrdev, iclass 22, count 0 2006.169.08:29:57.81#ibcon#first serial, iclass 22, count 0 2006.169.08:29:57.81#ibcon#enter sib2, iclass 22, count 0 2006.169.08:29:57.81#ibcon#flushed, iclass 22, count 0 2006.169.08:29:57.81#ibcon#about to write, iclass 22, count 0 2006.169.08:29:57.81#ibcon#wrote, iclass 22, count 0 2006.169.08:29:57.81#ibcon#about to read 3, iclass 22, count 0 2006.169.08:29:57.83#ibcon#read 3, iclass 22, count 0 2006.169.08:29:57.83#ibcon#about to read 4, iclass 22, count 0 2006.169.08:29:57.83#ibcon#read 4, iclass 22, count 0 2006.169.08:29:57.83#ibcon#about to read 5, iclass 22, count 0 2006.169.08:29:57.83#ibcon#read 5, iclass 22, count 0 2006.169.08:29:57.83#ibcon#about to read 6, iclass 22, count 0 2006.169.08:29:57.83#ibcon#read 6, iclass 22, count 0 2006.169.08:29:57.83#ibcon#end of sib2, iclass 22, count 0 2006.169.08:29:57.83#ibcon#*mode == 0, iclass 22, count 0 2006.169.08:29:57.83#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.169.08:29:57.83#ibcon#[28=FRQ=02,640.99\r\n] 2006.169.08:29:57.83#ibcon#*before write, iclass 22, count 0 2006.169.08:29:57.83#ibcon#enter sib2, iclass 22, count 0 2006.169.08:29:57.83#ibcon#flushed, iclass 22, count 0 2006.169.08:29:57.83#ibcon#about to write, iclass 22, count 0 2006.169.08:29:57.83#ibcon#wrote, iclass 22, count 0 2006.169.08:29:57.83#ibcon#about to read 3, iclass 22, count 0 2006.169.08:29:57.87#ibcon#read 3, iclass 22, count 0 2006.169.08:29:57.87#ibcon#about to read 4, iclass 22, count 0 2006.169.08:29:57.87#ibcon#read 4, iclass 22, count 0 2006.169.08:29:57.87#ibcon#about to read 5, iclass 22, count 0 2006.169.08:29:57.87#ibcon#read 5, iclass 22, count 0 2006.169.08:29:57.87#ibcon#about to read 6, iclass 22, count 0 2006.169.08:29:57.87#ibcon#read 6, iclass 22, count 0 2006.169.08:29:57.87#ibcon#end of sib2, iclass 22, count 0 2006.169.08:29:57.87#ibcon#*after write, iclass 22, count 0 2006.169.08:29:57.87#ibcon#*before return 0, iclass 22, count 0 2006.169.08:29:57.87#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.169.08:29:57.87#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.169.08:29:57.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.169.08:29:57.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.169.08:29:57.87$vc4f8/vb=2,4 2006.169.08:29:57.87#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.169.08:29:57.87#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.169.08:29:57.87#ibcon#ireg 11 cls_cnt 2 2006.169.08:29:57.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.169.08:29:57.93#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.169.08:29:57.93#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.169.08:29:57.93#ibcon#enter wrdev, iclass 24, count 2 2006.169.08:29:57.93#ibcon#first serial, iclass 24, count 2 2006.169.08:29:57.93#ibcon#enter sib2, iclass 24, count 2 2006.169.08:29:57.93#ibcon#flushed, iclass 24, count 2 2006.169.08:29:57.93#ibcon#about to write, iclass 24, count 2 2006.169.08:29:57.93#ibcon#wrote, iclass 24, count 2 2006.169.08:29:57.93#ibcon#about to read 3, iclass 24, count 2 2006.169.08:29:57.95#ibcon#read 3, iclass 24, count 2 2006.169.08:29:57.95#ibcon#about to read 4, iclass 24, count 2 2006.169.08:29:57.95#ibcon#read 4, iclass 24, count 2 2006.169.08:29:57.95#ibcon#about to read 5, iclass 24, count 2 2006.169.08:29:57.95#ibcon#read 5, iclass 24, count 2 2006.169.08:29:57.95#ibcon#about to read 6, iclass 24, count 2 2006.169.08:29:57.95#ibcon#read 6, iclass 24, count 2 2006.169.08:29:57.95#ibcon#end of sib2, iclass 24, count 2 2006.169.08:29:57.95#ibcon#*mode == 0, iclass 24, count 2 2006.169.08:29:57.95#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.169.08:29:57.95#ibcon#[27=AT02-04\r\n] 2006.169.08:29:57.95#ibcon#*before write, iclass 24, count 2 2006.169.08:29:57.95#ibcon#enter sib2, iclass 24, count 2 2006.169.08:29:57.95#ibcon#flushed, iclass 24, count 2 2006.169.08:29:57.95#ibcon#about to write, iclass 24, count 2 2006.169.08:29:57.95#ibcon#wrote, iclass 24, count 2 2006.169.08:29:57.95#ibcon#about to read 3, iclass 24, count 2 2006.169.08:29:57.98#ibcon#read 3, iclass 24, count 2 2006.169.08:29:57.98#ibcon#about to read 4, iclass 24, count 2 2006.169.08:29:57.98#ibcon#read 4, iclass 24, count 2 2006.169.08:29:57.98#ibcon#about to read 5, iclass 24, count 2 2006.169.08:29:57.98#ibcon#read 5, iclass 24, count 2 2006.169.08:29:57.98#ibcon#about to read 6, iclass 24, count 2 2006.169.08:29:57.98#ibcon#read 6, iclass 24, count 2 2006.169.08:29:57.98#ibcon#end of sib2, iclass 24, count 2 2006.169.08:29:57.98#ibcon#*after write, iclass 24, count 2 2006.169.08:29:57.98#ibcon#*before return 0, iclass 24, count 2 2006.169.08:29:57.98#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.169.08:29:57.98#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.169.08:29:57.98#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.169.08:29:57.98#ibcon#ireg 7 cls_cnt 0 2006.169.08:29:57.98#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.169.08:29:58.10#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.169.08:29:58.10#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.169.08:29:58.10#ibcon#enter wrdev, iclass 24, count 0 2006.169.08:29:58.10#ibcon#first serial, iclass 24, count 0 2006.169.08:29:58.10#ibcon#enter sib2, iclass 24, count 0 2006.169.08:29:58.10#ibcon#flushed, iclass 24, count 0 2006.169.08:29:58.10#ibcon#about to write, iclass 24, count 0 2006.169.08:29:58.10#ibcon#wrote, iclass 24, count 0 2006.169.08:29:58.10#ibcon#about to read 3, iclass 24, count 0 2006.169.08:29:58.12#ibcon#read 3, iclass 24, count 0 2006.169.08:29:58.12#ibcon#about to read 4, iclass 24, count 0 2006.169.08:29:58.12#ibcon#read 4, iclass 24, count 0 2006.169.08:29:58.12#ibcon#about to read 5, iclass 24, count 0 2006.169.08:29:58.12#ibcon#read 5, iclass 24, count 0 2006.169.08:29:58.12#ibcon#about to read 6, iclass 24, count 0 2006.169.08:29:58.12#ibcon#read 6, iclass 24, count 0 2006.169.08:29:58.12#ibcon#end of sib2, iclass 24, count 0 2006.169.08:29:58.12#ibcon#*mode == 0, iclass 24, count 0 2006.169.08:29:58.12#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.169.08:29:58.12#ibcon#[27=USB\r\n] 2006.169.08:29:58.12#ibcon#*before write, iclass 24, count 0 2006.169.08:29:58.12#ibcon#enter sib2, iclass 24, count 0 2006.169.08:29:58.12#ibcon#flushed, iclass 24, count 0 2006.169.08:29:58.12#ibcon#about to write, iclass 24, count 0 2006.169.08:29:58.12#ibcon#wrote, iclass 24, count 0 2006.169.08:29:58.12#ibcon#about to read 3, iclass 24, count 0 2006.169.08:29:58.15#ibcon#read 3, iclass 24, count 0 2006.169.08:29:58.15#ibcon#about to read 4, iclass 24, count 0 2006.169.08:29:58.15#ibcon#read 4, iclass 24, count 0 2006.169.08:29:58.15#ibcon#about to read 5, iclass 24, count 0 2006.169.08:29:58.15#ibcon#read 5, iclass 24, count 0 2006.169.08:29:58.15#ibcon#about to read 6, iclass 24, count 0 2006.169.08:29:58.15#ibcon#read 6, iclass 24, count 0 2006.169.08:29:58.15#ibcon#end of sib2, iclass 24, count 0 2006.169.08:29:58.15#ibcon#*after write, iclass 24, count 0 2006.169.08:29:58.15#ibcon#*before return 0, iclass 24, count 0 2006.169.08:29:58.15#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.169.08:29:58.15#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.169.08:29:58.15#ibcon#about to clear, iclass 24 cls_cnt 0 2006.169.08:29:58.15#ibcon#cleared, iclass 24 cls_cnt 0 2006.169.08:29:58.15$vc4f8/vblo=3,656.99 2006.169.08:29:58.15#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.169.08:29:58.15#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.169.08:29:58.15#ibcon#ireg 17 cls_cnt 0 2006.169.08:29:58.15#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:29:58.15#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:29:58.15#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:29:58.15#ibcon#enter wrdev, iclass 26, count 0 2006.169.08:29:58.15#ibcon#first serial, iclass 26, count 0 2006.169.08:29:58.15#ibcon#enter sib2, iclass 26, count 0 2006.169.08:29:58.15#ibcon#flushed, iclass 26, count 0 2006.169.08:29:58.15#ibcon#about to write, iclass 26, count 0 2006.169.08:29:58.15#ibcon#wrote, iclass 26, count 0 2006.169.08:29:58.15#ibcon#about to read 3, iclass 26, count 0 2006.169.08:29:58.17#ibcon#read 3, iclass 26, count 0 2006.169.08:29:58.17#ibcon#about to read 4, iclass 26, count 0 2006.169.08:29:58.17#ibcon#read 4, iclass 26, count 0 2006.169.08:29:58.17#ibcon#about to read 5, iclass 26, count 0 2006.169.08:29:58.17#ibcon#read 5, iclass 26, count 0 2006.169.08:29:58.17#ibcon#about to read 6, iclass 26, count 0 2006.169.08:29:58.17#ibcon#read 6, iclass 26, count 0 2006.169.08:29:58.17#ibcon#end of sib2, iclass 26, count 0 2006.169.08:29:58.17#ibcon#*mode == 0, iclass 26, count 0 2006.169.08:29:58.17#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.169.08:29:58.17#ibcon#[28=FRQ=03,656.99\r\n] 2006.169.08:29:58.17#ibcon#*before write, iclass 26, count 0 2006.169.08:29:58.17#ibcon#enter sib2, iclass 26, count 0 2006.169.08:29:58.17#ibcon#flushed, iclass 26, count 0 2006.169.08:29:58.17#ibcon#about to write, iclass 26, count 0 2006.169.08:29:58.17#ibcon#wrote, iclass 26, count 0 2006.169.08:29:58.17#ibcon#about to read 3, iclass 26, count 0 2006.169.08:29:58.21#ibcon#read 3, iclass 26, count 0 2006.169.08:29:58.21#ibcon#about to read 4, iclass 26, count 0 2006.169.08:29:58.21#ibcon#read 4, iclass 26, count 0 2006.169.08:29:58.21#ibcon#about to read 5, iclass 26, count 0 2006.169.08:29:58.21#ibcon#read 5, iclass 26, count 0 2006.169.08:29:58.21#ibcon#about to read 6, iclass 26, count 0 2006.169.08:29:58.21#ibcon#read 6, iclass 26, count 0 2006.169.08:29:58.21#ibcon#end of sib2, iclass 26, count 0 2006.169.08:29:58.21#ibcon#*after write, iclass 26, count 0 2006.169.08:29:58.21#ibcon#*before return 0, iclass 26, count 0 2006.169.08:29:58.21#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:29:58.21#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.169.08:29:58.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.169.08:29:58.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.169.08:29:58.21$vc4f8/vb=3,4 2006.169.08:29:58.21#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.169.08:29:58.21#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.169.08:29:58.21#ibcon#ireg 11 cls_cnt 2 2006.169.08:29:58.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.169.08:29:58.27#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.169.08:29:58.27#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.169.08:29:58.27#ibcon#enter wrdev, iclass 28, count 2 2006.169.08:29:58.27#ibcon#first serial, iclass 28, count 2 2006.169.08:29:58.27#ibcon#enter sib2, iclass 28, count 2 2006.169.08:29:58.27#ibcon#flushed, iclass 28, count 2 2006.169.08:29:58.27#ibcon#about to write, iclass 28, count 2 2006.169.08:29:58.27#ibcon#wrote, iclass 28, count 2 2006.169.08:29:58.27#ibcon#about to read 3, iclass 28, count 2 2006.169.08:29:58.29#ibcon#read 3, iclass 28, count 2 2006.169.08:29:58.29#ibcon#about to read 4, iclass 28, count 2 2006.169.08:29:58.29#ibcon#read 4, iclass 28, count 2 2006.169.08:29:58.29#ibcon#about to read 5, iclass 28, count 2 2006.169.08:29:58.29#ibcon#read 5, iclass 28, count 2 2006.169.08:29:58.29#ibcon#about to read 6, iclass 28, count 2 2006.169.08:29:58.29#ibcon#read 6, iclass 28, count 2 2006.169.08:29:58.29#ibcon#end of sib2, iclass 28, count 2 2006.169.08:29:58.29#ibcon#*mode == 0, iclass 28, count 2 2006.169.08:29:58.29#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.169.08:29:58.29#ibcon#[27=AT03-04\r\n] 2006.169.08:29:58.29#ibcon#*before write, iclass 28, count 2 2006.169.08:29:58.29#ibcon#enter sib2, iclass 28, count 2 2006.169.08:29:58.29#ibcon#flushed, iclass 28, count 2 2006.169.08:29:58.29#ibcon#about to write, iclass 28, count 2 2006.169.08:29:58.29#ibcon#wrote, iclass 28, count 2 2006.169.08:29:58.29#ibcon#about to read 3, iclass 28, count 2 2006.169.08:29:58.32#ibcon#read 3, iclass 28, count 2 2006.169.08:29:58.32#ibcon#about to read 4, iclass 28, count 2 2006.169.08:29:58.32#ibcon#read 4, iclass 28, count 2 2006.169.08:29:58.32#ibcon#about to read 5, iclass 28, count 2 2006.169.08:29:58.32#ibcon#read 5, iclass 28, count 2 2006.169.08:29:58.32#ibcon#about to read 6, iclass 28, count 2 2006.169.08:29:58.32#ibcon#read 6, iclass 28, count 2 2006.169.08:29:58.32#ibcon#end of sib2, iclass 28, count 2 2006.169.08:29:58.32#ibcon#*after write, iclass 28, count 2 2006.169.08:29:58.32#ibcon#*before return 0, iclass 28, count 2 2006.169.08:29:58.32#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.169.08:29:58.32#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.169.08:29:58.32#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.169.08:29:58.32#ibcon#ireg 7 cls_cnt 0 2006.169.08:29:58.32#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.169.08:29:58.44#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.169.08:29:58.44#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.169.08:29:58.44#ibcon#enter wrdev, iclass 28, count 0 2006.169.08:29:58.44#ibcon#first serial, iclass 28, count 0 2006.169.08:29:58.44#ibcon#enter sib2, iclass 28, count 0 2006.169.08:29:58.44#ibcon#flushed, iclass 28, count 0 2006.169.08:29:58.44#ibcon#about to write, iclass 28, count 0 2006.169.08:29:58.44#ibcon#wrote, iclass 28, count 0 2006.169.08:29:58.44#ibcon#about to read 3, iclass 28, count 0 2006.169.08:29:58.46#ibcon#read 3, iclass 28, count 0 2006.169.08:29:58.46#ibcon#about to read 4, iclass 28, count 0 2006.169.08:29:58.46#ibcon#read 4, iclass 28, count 0 2006.169.08:29:58.46#ibcon#about to read 5, iclass 28, count 0 2006.169.08:29:58.46#ibcon#read 5, iclass 28, count 0 2006.169.08:29:58.46#ibcon#about to read 6, iclass 28, count 0 2006.169.08:29:58.46#ibcon#read 6, iclass 28, count 0 2006.169.08:29:58.46#ibcon#end of sib2, iclass 28, count 0 2006.169.08:29:58.46#ibcon#*mode == 0, iclass 28, count 0 2006.169.08:29:58.46#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.169.08:29:58.46#ibcon#[27=USB\r\n] 2006.169.08:29:58.46#ibcon#*before write, iclass 28, count 0 2006.169.08:29:58.46#ibcon#enter sib2, iclass 28, count 0 2006.169.08:29:58.46#ibcon#flushed, iclass 28, count 0 2006.169.08:29:58.46#ibcon#about to write, iclass 28, count 0 2006.169.08:29:58.46#ibcon#wrote, iclass 28, count 0 2006.169.08:29:58.46#ibcon#about to read 3, iclass 28, count 0 2006.169.08:29:58.49#ibcon#read 3, iclass 28, count 0 2006.169.08:29:58.49#ibcon#about to read 4, iclass 28, count 0 2006.169.08:29:58.49#ibcon#read 4, iclass 28, count 0 2006.169.08:29:58.49#ibcon#about to read 5, iclass 28, count 0 2006.169.08:29:58.49#ibcon#read 5, iclass 28, count 0 2006.169.08:29:58.49#ibcon#about to read 6, iclass 28, count 0 2006.169.08:29:58.49#ibcon#read 6, iclass 28, count 0 2006.169.08:29:58.49#ibcon#end of sib2, iclass 28, count 0 2006.169.08:29:58.49#ibcon#*after write, iclass 28, count 0 2006.169.08:29:58.49#ibcon#*before return 0, iclass 28, count 0 2006.169.08:29:58.49#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.169.08:29:58.49#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.169.08:29:58.49#ibcon#about to clear, iclass 28 cls_cnt 0 2006.169.08:29:58.49#ibcon#cleared, iclass 28 cls_cnt 0 2006.169.08:29:58.49$vc4f8/vblo=4,712.99 2006.169.08:29:58.49#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.169.08:29:58.49#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.169.08:29:58.49#ibcon#ireg 17 cls_cnt 0 2006.169.08:29:58.49#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.169.08:29:58.49#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.169.08:29:58.49#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.169.08:29:58.49#ibcon#enter wrdev, iclass 30, count 0 2006.169.08:29:58.49#ibcon#first serial, iclass 30, count 0 2006.169.08:29:58.49#ibcon#enter sib2, iclass 30, count 0 2006.169.08:29:58.49#ibcon#flushed, iclass 30, count 0 2006.169.08:29:58.49#ibcon#about to write, iclass 30, count 0 2006.169.08:29:58.49#ibcon#wrote, iclass 30, count 0 2006.169.08:29:58.49#ibcon#about to read 3, iclass 30, count 0 2006.169.08:29:58.51#ibcon#read 3, iclass 30, count 0 2006.169.08:29:58.51#ibcon#about to read 4, iclass 30, count 0 2006.169.08:29:58.51#ibcon#read 4, iclass 30, count 0 2006.169.08:29:58.51#ibcon#about to read 5, iclass 30, count 0 2006.169.08:29:58.51#ibcon#read 5, iclass 30, count 0 2006.169.08:29:58.51#ibcon#about to read 6, iclass 30, count 0 2006.169.08:29:58.51#ibcon#read 6, iclass 30, count 0 2006.169.08:29:58.51#ibcon#end of sib2, iclass 30, count 0 2006.169.08:29:58.51#ibcon#*mode == 0, iclass 30, count 0 2006.169.08:29:58.51#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.169.08:29:58.51#ibcon#[28=FRQ=04,712.99\r\n] 2006.169.08:29:58.51#ibcon#*before write, iclass 30, count 0 2006.169.08:29:58.51#ibcon#enter sib2, iclass 30, count 0 2006.169.08:29:58.51#ibcon#flushed, iclass 30, count 0 2006.169.08:29:58.51#ibcon#about to write, iclass 30, count 0 2006.169.08:29:58.51#ibcon#wrote, iclass 30, count 0 2006.169.08:29:58.51#ibcon#about to read 3, iclass 30, count 0 2006.169.08:29:58.55#ibcon#read 3, iclass 30, count 0 2006.169.08:29:58.55#ibcon#about to read 4, iclass 30, count 0 2006.169.08:29:58.55#ibcon#read 4, iclass 30, count 0 2006.169.08:29:58.55#ibcon#about to read 5, iclass 30, count 0 2006.169.08:29:58.55#ibcon#read 5, iclass 30, count 0 2006.169.08:29:58.55#ibcon#about to read 6, iclass 30, count 0 2006.169.08:29:58.55#ibcon#read 6, iclass 30, count 0 2006.169.08:29:58.55#ibcon#end of sib2, iclass 30, count 0 2006.169.08:29:58.55#ibcon#*after write, iclass 30, count 0 2006.169.08:29:58.55#ibcon#*before return 0, iclass 30, count 0 2006.169.08:29:58.55#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.169.08:29:58.55#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.169.08:29:58.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.169.08:29:58.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.169.08:29:58.55$vc4f8/vb=4,4 2006.169.08:29:58.55#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.169.08:29:58.55#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.169.08:29:58.55#ibcon#ireg 11 cls_cnt 2 2006.169.08:29:58.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.169.08:29:58.61#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.169.08:29:58.61#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.169.08:29:58.61#ibcon#enter wrdev, iclass 32, count 2 2006.169.08:29:58.61#ibcon#first serial, iclass 32, count 2 2006.169.08:29:58.61#ibcon#enter sib2, iclass 32, count 2 2006.169.08:29:58.61#ibcon#flushed, iclass 32, count 2 2006.169.08:29:58.61#ibcon#about to write, iclass 32, count 2 2006.169.08:29:58.61#ibcon#wrote, iclass 32, count 2 2006.169.08:29:58.61#ibcon#about to read 3, iclass 32, count 2 2006.169.08:29:58.63#ibcon#read 3, iclass 32, count 2 2006.169.08:29:58.63#ibcon#about to read 4, iclass 32, count 2 2006.169.08:29:58.63#ibcon#read 4, iclass 32, count 2 2006.169.08:29:58.63#ibcon#about to read 5, iclass 32, count 2 2006.169.08:29:58.63#ibcon#read 5, iclass 32, count 2 2006.169.08:29:58.63#ibcon#about to read 6, iclass 32, count 2 2006.169.08:29:58.63#ibcon#read 6, iclass 32, count 2 2006.169.08:29:58.63#ibcon#end of sib2, iclass 32, count 2 2006.169.08:29:58.63#ibcon#*mode == 0, iclass 32, count 2 2006.169.08:29:58.63#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.169.08:29:58.63#ibcon#[27=AT04-04\r\n] 2006.169.08:29:58.63#ibcon#*before write, iclass 32, count 2 2006.169.08:29:58.63#ibcon#enter sib2, iclass 32, count 2 2006.169.08:29:58.63#ibcon#flushed, iclass 32, count 2 2006.169.08:29:58.63#ibcon#about to write, iclass 32, count 2 2006.169.08:29:58.63#ibcon#wrote, iclass 32, count 2 2006.169.08:29:58.63#ibcon#about to read 3, iclass 32, count 2 2006.169.08:29:58.66#ibcon#read 3, iclass 32, count 2 2006.169.08:29:58.66#ibcon#about to read 4, iclass 32, count 2 2006.169.08:29:58.66#ibcon#read 4, iclass 32, count 2 2006.169.08:29:58.66#ibcon#about to read 5, iclass 32, count 2 2006.169.08:29:58.66#ibcon#read 5, iclass 32, count 2 2006.169.08:29:58.66#ibcon#about to read 6, iclass 32, count 2 2006.169.08:29:58.66#ibcon#read 6, iclass 32, count 2 2006.169.08:29:58.66#ibcon#end of sib2, iclass 32, count 2 2006.169.08:29:58.66#ibcon#*after write, iclass 32, count 2 2006.169.08:29:58.66#ibcon#*before return 0, iclass 32, count 2 2006.169.08:29:58.66#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.169.08:29:58.66#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.169.08:29:58.66#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.169.08:29:58.66#ibcon#ireg 7 cls_cnt 0 2006.169.08:29:58.66#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.169.08:29:58.78#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.169.08:29:58.78#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.169.08:29:58.78#ibcon#enter wrdev, iclass 32, count 0 2006.169.08:29:58.78#ibcon#first serial, iclass 32, count 0 2006.169.08:29:58.78#ibcon#enter sib2, iclass 32, count 0 2006.169.08:29:58.78#ibcon#flushed, iclass 32, count 0 2006.169.08:29:58.78#ibcon#about to write, iclass 32, count 0 2006.169.08:29:58.78#ibcon#wrote, iclass 32, count 0 2006.169.08:29:58.78#ibcon#about to read 3, iclass 32, count 0 2006.169.08:29:58.80#ibcon#read 3, iclass 32, count 0 2006.169.08:29:58.80#ibcon#about to read 4, iclass 32, count 0 2006.169.08:29:58.80#ibcon#read 4, iclass 32, count 0 2006.169.08:29:58.80#ibcon#about to read 5, iclass 32, count 0 2006.169.08:29:58.80#ibcon#read 5, iclass 32, count 0 2006.169.08:29:58.80#ibcon#about to read 6, iclass 32, count 0 2006.169.08:29:58.80#ibcon#read 6, iclass 32, count 0 2006.169.08:29:58.80#ibcon#end of sib2, iclass 32, count 0 2006.169.08:29:58.80#ibcon#*mode == 0, iclass 32, count 0 2006.169.08:29:58.80#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.169.08:29:58.80#ibcon#[27=USB\r\n] 2006.169.08:29:58.80#ibcon#*before write, iclass 32, count 0 2006.169.08:29:58.80#ibcon#enter sib2, iclass 32, count 0 2006.169.08:29:58.80#ibcon#flushed, iclass 32, count 0 2006.169.08:29:58.80#ibcon#about to write, iclass 32, count 0 2006.169.08:29:58.80#ibcon#wrote, iclass 32, count 0 2006.169.08:29:58.80#ibcon#about to read 3, iclass 32, count 0 2006.169.08:29:58.83#ibcon#read 3, iclass 32, count 0 2006.169.08:29:58.83#ibcon#about to read 4, iclass 32, count 0 2006.169.08:29:58.83#ibcon#read 4, iclass 32, count 0 2006.169.08:29:58.83#ibcon#about to read 5, iclass 32, count 0 2006.169.08:29:58.83#ibcon#read 5, iclass 32, count 0 2006.169.08:29:58.83#ibcon#about to read 6, iclass 32, count 0 2006.169.08:29:58.83#ibcon#read 6, iclass 32, count 0 2006.169.08:29:58.83#ibcon#end of sib2, iclass 32, count 0 2006.169.08:29:58.83#ibcon#*after write, iclass 32, count 0 2006.169.08:29:58.83#ibcon#*before return 0, iclass 32, count 0 2006.169.08:29:58.83#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.169.08:29:58.83#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.169.08:29:58.83#ibcon#about to clear, iclass 32 cls_cnt 0 2006.169.08:29:58.83#ibcon#cleared, iclass 32 cls_cnt 0 2006.169.08:29:58.83$vc4f8/vblo=5,744.99 2006.169.08:29:58.83#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.169.08:29:58.83#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.169.08:29:58.83#ibcon#ireg 17 cls_cnt 0 2006.169.08:29:58.83#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:29:58.83#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:29:58.83#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:29:58.83#ibcon#enter wrdev, iclass 34, count 0 2006.169.08:29:58.83#ibcon#first serial, iclass 34, count 0 2006.169.08:29:58.83#ibcon#enter sib2, iclass 34, count 0 2006.169.08:29:58.83#ibcon#flushed, iclass 34, count 0 2006.169.08:29:58.83#ibcon#about to write, iclass 34, count 0 2006.169.08:29:58.83#ibcon#wrote, iclass 34, count 0 2006.169.08:29:58.83#ibcon#about to read 3, iclass 34, count 0 2006.169.08:29:58.85#ibcon#read 3, iclass 34, count 0 2006.169.08:29:58.85#ibcon#about to read 4, iclass 34, count 0 2006.169.08:29:58.85#ibcon#read 4, iclass 34, count 0 2006.169.08:29:58.85#ibcon#about to read 5, iclass 34, count 0 2006.169.08:29:58.85#ibcon#read 5, iclass 34, count 0 2006.169.08:29:58.85#ibcon#about to read 6, iclass 34, count 0 2006.169.08:29:58.85#ibcon#read 6, iclass 34, count 0 2006.169.08:29:58.85#ibcon#end of sib2, iclass 34, count 0 2006.169.08:29:58.85#ibcon#*mode == 0, iclass 34, count 0 2006.169.08:29:58.85#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.169.08:29:58.85#ibcon#[28=FRQ=05,744.99\r\n] 2006.169.08:29:58.85#ibcon#*before write, iclass 34, count 0 2006.169.08:29:58.85#ibcon#enter sib2, iclass 34, count 0 2006.169.08:29:58.85#ibcon#flushed, iclass 34, count 0 2006.169.08:29:58.85#ibcon#about to write, iclass 34, count 0 2006.169.08:29:58.85#ibcon#wrote, iclass 34, count 0 2006.169.08:29:58.85#ibcon#about to read 3, iclass 34, count 0 2006.169.08:29:58.89#ibcon#read 3, iclass 34, count 0 2006.169.08:29:58.89#ibcon#about to read 4, iclass 34, count 0 2006.169.08:29:58.89#ibcon#read 4, iclass 34, count 0 2006.169.08:29:58.89#ibcon#about to read 5, iclass 34, count 0 2006.169.08:29:58.89#ibcon#read 5, iclass 34, count 0 2006.169.08:29:58.89#ibcon#about to read 6, iclass 34, count 0 2006.169.08:29:58.89#ibcon#read 6, iclass 34, count 0 2006.169.08:29:58.89#ibcon#end of sib2, iclass 34, count 0 2006.169.08:29:58.89#ibcon#*after write, iclass 34, count 0 2006.169.08:29:58.89#ibcon#*before return 0, iclass 34, count 0 2006.169.08:29:58.89#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:29:58.89#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.169.08:29:58.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.169.08:29:58.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.169.08:29:58.89$vc4f8/vb=5,4 2006.169.08:29:58.89#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.169.08:29:58.89#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.169.08:29:58.89#ibcon#ireg 11 cls_cnt 2 2006.169.08:29:58.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.169.08:29:58.96#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.169.08:29:58.96#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.169.08:29:58.96#ibcon#enter wrdev, iclass 36, count 2 2006.169.08:29:58.96#ibcon#first serial, iclass 36, count 2 2006.169.08:29:58.96#ibcon#enter sib2, iclass 36, count 2 2006.169.08:29:58.96#ibcon#flushed, iclass 36, count 2 2006.169.08:29:58.96#ibcon#about to write, iclass 36, count 2 2006.169.08:29:58.96#ibcon#wrote, iclass 36, count 2 2006.169.08:29:58.96#ibcon#about to read 3, iclass 36, count 2 2006.169.08:29:58.97#ibcon#read 3, iclass 36, count 2 2006.169.08:29:58.97#ibcon#about to read 4, iclass 36, count 2 2006.169.08:29:58.97#ibcon#read 4, iclass 36, count 2 2006.169.08:29:58.97#ibcon#about to read 5, iclass 36, count 2 2006.169.08:29:58.97#ibcon#read 5, iclass 36, count 2 2006.169.08:29:58.97#ibcon#about to read 6, iclass 36, count 2 2006.169.08:29:58.97#ibcon#read 6, iclass 36, count 2 2006.169.08:29:58.97#ibcon#end of sib2, iclass 36, count 2 2006.169.08:29:58.97#ibcon#*mode == 0, iclass 36, count 2 2006.169.08:29:58.97#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.169.08:29:58.97#ibcon#[27=AT05-04\r\n] 2006.169.08:29:58.97#ibcon#*before write, iclass 36, count 2 2006.169.08:29:58.97#ibcon#enter sib2, iclass 36, count 2 2006.169.08:29:58.97#ibcon#flushed, iclass 36, count 2 2006.169.08:29:58.97#ibcon#about to write, iclass 36, count 2 2006.169.08:29:58.97#ibcon#wrote, iclass 36, count 2 2006.169.08:29:58.97#ibcon#about to read 3, iclass 36, count 2 2006.169.08:29:59.00#ibcon#read 3, iclass 36, count 2 2006.169.08:29:59.00#ibcon#about to read 4, iclass 36, count 2 2006.169.08:29:59.00#ibcon#read 4, iclass 36, count 2 2006.169.08:29:59.00#ibcon#about to read 5, iclass 36, count 2 2006.169.08:29:59.00#ibcon#read 5, iclass 36, count 2 2006.169.08:29:59.00#ibcon#about to read 6, iclass 36, count 2 2006.169.08:29:59.00#ibcon#read 6, iclass 36, count 2 2006.169.08:29:59.00#ibcon#end of sib2, iclass 36, count 2 2006.169.08:29:59.00#ibcon#*after write, iclass 36, count 2 2006.169.08:29:59.00#ibcon#*before return 0, iclass 36, count 2 2006.169.08:29:59.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.169.08:29:59.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.169.08:29:59.00#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.169.08:29:59.00#ibcon#ireg 7 cls_cnt 0 2006.169.08:29:59.00#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.169.08:29:59.12#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.169.08:29:59.12#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.169.08:29:59.12#ibcon#enter wrdev, iclass 36, count 0 2006.169.08:29:59.12#ibcon#first serial, iclass 36, count 0 2006.169.08:29:59.12#ibcon#enter sib2, iclass 36, count 0 2006.169.08:29:59.12#ibcon#flushed, iclass 36, count 0 2006.169.08:29:59.12#ibcon#about to write, iclass 36, count 0 2006.169.08:29:59.12#ibcon#wrote, iclass 36, count 0 2006.169.08:29:59.12#ibcon#about to read 3, iclass 36, count 0 2006.169.08:29:59.14#ibcon#read 3, iclass 36, count 0 2006.169.08:29:59.14#ibcon#about to read 4, iclass 36, count 0 2006.169.08:29:59.14#ibcon#read 4, iclass 36, count 0 2006.169.08:29:59.14#ibcon#about to read 5, iclass 36, count 0 2006.169.08:29:59.14#ibcon#read 5, iclass 36, count 0 2006.169.08:29:59.14#ibcon#about to read 6, iclass 36, count 0 2006.169.08:29:59.14#ibcon#read 6, iclass 36, count 0 2006.169.08:29:59.14#ibcon#end of sib2, iclass 36, count 0 2006.169.08:29:59.14#ibcon#*mode == 0, iclass 36, count 0 2006.169.08:29:59.14#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.169.08:29:59.14#ibcon#[27=USB\r\n] 2006.169.08:29:59.14#ibcon#*before write, iclass 36, count 0 2006.169.08:29:59.14#ibcon#enter sib2, iclass 36, count 0 2006.169.08:29:59.14#ibcon#flushed, iclass 36, count 0 2006.169.08:29:59.14#ibcon#about to write, iclass 36, count 0 2006.169.08:29:59.14#ibcon#wrote, iclass 36, count 0 2006.169.08:29:59.14#ibcon#about to read 3, iclass 36, count 0 2006.169.08:29:59.17#ibcon#read 3, iclass 36, count 0 2006.169.08:29:59.17#ibcon#about to read 4, iclass 36, count 0 2006.169.08:29:59.17#ibcon#read 4, iclass 36, count 0 2006.169.08:29:59.17#ibcon#about to read 5, iclass 36, count 0 2006.169.08:29:59.17#ibcon#read 5, iclass 36, count 0 2006.169.08:29:59.17#ibcon#about to read 6, iclass 36, count 0 2006.169.08:29:59.17#ibcon#read 6, iclass 36, count 0 2006.169.08:29:59.17#ibcon#end of sib2, iclass 36, count 0 2006.169.08:29:59.17#ibcon#*after write, iclass 36, count 0 2006.169.08:29:59.17#ibcon#*before return 0, iclass 36, count 0 2006.169.08:29:59.17#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.169.08:29:59.17#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.169.08:29:59.17#ibcon#about to clear, iclass 36 cls_cnt 0 2006.169.08:29:59.17#ibcon#cleared, iclass 36 cls_cnt 0 2006.169.08:29:59.17$vc4f8/vblo=6,752.99 2006.169.08:29:59.17#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.169.08:29:59.17#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.169.08:29:59.17#ibcon#ireg 17 cls_cnt 0 2006.169.08:29:59.17#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.169.08:29:59.17#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.169.08:29:59.17#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.169.08:29:59.17#ibcon#enter wrdev, iclass 38, count 0 2006.169.08:29:59.17#ibcon#first serial, iclass 38, count 0 2006.169.08:29:59.17#ibcon#enter sib2, iclass 38, count 0 2006.169.08:29:59.17#ibcon#flushed, iclass 38, count 0 2006.169.08:29:59.17#ibcon#about to write, iclass 38, count 0 2006.169.08:29:59.17#ibcon#wrote, iclass 38, count 0 2006.169.08:29:59.17#ibcon#about to read 3, iclass 38, count 0 2006.169.08:29:59.19#ibcon#read 3, iclass 38, count 0 2006.169.08:29:59.19#ibcon#about to read 4, iclass 38, count 0 2006.169.08:29:59.19#ibcon#read 4, iclass 38, count 0 2006.169.08:29:59.19#ibcon#about to read 5, iclass 38, count 0 2006.169.08:29:59.19#ibcon#read 5, iclass 38, count 0 2006.169.08:29:59.19#ibcon#about to read 6, iclass 38, count 0 2006.169.08:29:59.19#ibcon#read 6, iclass 38, count 0 2006.169.08:29:59.19#ibcon#end of sib2, iclass 38, count 0 2006.169.08:29:59.19#ibcon#*mode == 0, iclass 38, count 0 2006.169.08:29:59.19#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.169.08:29:59.19#ibcon#[28=FRQ=06,752.99\r\n] 2006.169.08:29:59.19#ibcon#*before write, iclass 38, count 0 2006.169.08:29:59.19#ibcon#enter sib2, iclass 38, count 0 2006.169.08:29:59.19#ibcon#flushed, iclass 38, count 0 2006.169.08:29:59.19#ibcon#about to write, iclass 38, count 0 2006.169.08:29:59.19#ibcon#wrote, iclass 38, count 0 2006.169.08:29:59.19#ibcon#about to read 3, iclass 38, count 0 2006.169.08:29:59.23#ibcon#read 3, iclass 38, count 0 2006.169.08:29:59.23#ibcon#about to read 4, iclass 38, count 0 2006.169.08:29:59.23#ibcon#read 4, iclass 38, count 0 2006.169.08:29:59.23#ibcon#about to read 5, iclass 38, count 0 2006.169.08:29:59.23#ibcon#read 5, iclass 38, count 0 2006.169.08:29:59.23#ibcon#about to read 6, iclass 38, count 0 2006.169.08:29:59.23#ibcon#read 6, iclass 38, count 0 2006.169.08:29:59.23#ibcon#end of sib2, iclass 38, count 0 2006.169.08:29:59.23#ibcon#*after write, iclass 38, count 0 2006.169.08:29:59.23#ibcon#*before return 0, iclass 38, count 0 2006.169.08:29:59.23#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.169.08:29:59.23#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.169.08:29:59.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.169.08:29:59.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.169.08:29:59.23$vc4f8/vb=6,4 2006.169.08:29:59.23#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.169.08:29:59.23#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.169.08:29:59.23#ibcon#ireg 11 cls_cnt 2 2006.169.08:29:59.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.169.08:29:59.29#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.169.08:29:59.29#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.169.08:29:59.29#ibcon#enter wrdev, iclass 40, count 2 2006.169.08:29:59.29#ibcon#first serial, iclass 40, count 2 2006.169.08:29:59.29#ibcon#enter sib2, iclass 40, count 2 2006.169.08:29:59.29#ibcon#flushed, iclass 40, count 2 2006.169.08:29:59.29#ibcon#about to write, iclass 40, count 2 2006.169.08:29:59.29#ibcon#wrote, iclass 40, count 2 2006.169.08:29:59.29#ibcon#about to read 3, iclass 40, count 2 2006.169.08:29:59.31#ibcon#read 3, iclass 40, count 2 2006.169.08:29:59.31#ibcon#about to read 4, iclass 40, count 2 2006.169.08:29:59.31#ibcon#read 4, iclass 40, count 2 2006.169.08:29:59.31#ibcon#about to read 5, iclass 40, count 2 2006.169.08:29:59.31#ibcon#read 5, iclass 40, count 2 2006.169.08:29:59.31#ibcon#about to read 6, iclass 40, count 2 2006.169.08:29:59.31#ibcon#read 6, iclass 40, count 2 2006.169.08:29:59.31#ibcon#end of sib2, iclass 40, count 2 2006.169.08:29:59.31#ibcon#*mode == 0, iclass 40, count 2 2006.169.08:29:59.31#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.169.08:29:59.31#ibcon#[27=AT06-04\r\n] 2006.169.08:29:59.31#ibcon#*before write, iclass 40, count 2 2006.169.08:29:59.31#ibcon#enter sib2, iclass 40, count 2 2006.169.08:29:59.31#ibcon#flushed, iclass 40, count 2 2006.169.08:29:59.31#ibcon#about to write, iclass 40, count 2 2006.169.08:29:59.31#ibcon#wrote, iclass 40, count 2 2006.169.08:29:59.31#ibcon#about to read 3, iclass 40, count 2 2006.169.08:29:59.34#ibcon#read 3, iclass 40, count 2 2006.169.08:29:59.34#ibcon#about to read 4, iclass 40, count 2 2006.169.08:29:59.34#ibcon#read 4, iclass 40, count 2 2006.169.08:29:59.34#ibcon#about to read 5, iclass 40, count 2 2006.169.08:29:59.34#ibcon#read 5, iclass 40, count 2 2006.169.08:29:59.34#ibcon#about to read 6, iclass 40, count 2 2006.169.08:29:59.34#ibcon#read 6, iclass 40, count 2 2006.169.08:29:59.34#ibcon#end of sib2, iclass 40, count 2 2006.169.08:29:59.34#ibcon#*after write, iclass 40, count 2 2006.169.08:29:59.34#ibcon#*before return 0, iclass 40, count 2 2006.169.08:29:59.34#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.169.08:29:59.34#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.169.08:29:59.34#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.169.08:29:59.34#ibcon#ireg 7 cls_cnt 0 2006.169.08:29:59.34#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.169.08:29:59.46#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.169.08:29:59.46#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.169.08:29:59.46#ibcon#enter wrdev, iclass 40, count 0 2006.169.08:29:59.46#ibcon#first serial, iclass 40, count 0 2006.169.08:29:59.46#ibcon#enter sib2, iclass 40, count 0 2006.169.08:29:59.46#ibcon#flushed, iclass 40, count 0 2006.169.08:29:59.46#ibcon#about to write, iclass 40, count 0 2006.169.08:29:59.46#ibcon#wrote, iclass 40, count 0 2006.169.08:29:59.46#ibcon#about to read 3, iclass 40, count 0 2006.169.08:29:59.48#ibcon#read 3, iclass 40, count 0 2006.169.08:29:59.48#ibcon#about to read 4, iclass 40, count 0 2006.169.08:29:59.48#ibcon#read 4, iclass 40, count 0 2006.169.08:29:59.48#ibcon#about to read 5, iclass 40, count 0 2006.169.08:29:59.48#ibcon#read 5, iclass 40, count 0 2006.169.08:29:59.48#ibcon#about to read 6, iclass 40, count 0 2006.169.08:29:59.48#ibcon#read 6, iclass 40, count 0 2006.169.08:29:59.48#ibcon#end of sib2, iclass 40, count 0 2006.169.08:29:59.48#ibcon#*mode == 0, iclass 40, count 0 2006.169.08:29:59.48#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.169.08:29:59.48#ibcon#[27=USB\r\n] 2006.169.08:29:59.48#ibcon#*before write, iclass 40, count 0 2006.169.08:29:59.48#ibcon#enter sib2, iclass 40, count 0 2006.169.08:29:59.48#ibcon#flushed, iclass 40, count 0 2006.169.08:29:59.48#ibcon#about to write, iclass 40, count 0 2006.169.08:29:59.48#ibcon#wrote, iclass 40, count 0 2006.169.08:29:59.48#ibcon#about to read 3, iclass 40, count 0 2006.169.08:29:59.51#ibcon#read 3, iclass 40, count 0 2006.169.08:29:59.51#ibcon#about to read 4, iclass 40, count 0 2006.169.08:29:59.51#ibcon#read 4, iclass 40, count 0 2006.169.08:29:59.51#ibcon#about to read 5, iclass 40, count 0 2006.169.08:29:59.51#ibcon#read 5, iclass 40, count 0 2006.169.08:29:59.51#ibcon#about to read 6, iclass 40, count 0 2006.169.08:29:59.51#ibcon#read 6, iclass 40, count 0 2006.169.08:29:59.51#ibcon#end of sib2, iclass 40, count 0 2006.169.08:29:59.51#ibcon#*after write, iclass 40, count 0 2006.169.08:29:59.51#ibcon#*before return 0, iclass 40, count 0 2006.169.08:29:59.51#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.169.08:29:59.51#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.169.08:29:59.51#ibcon#about to clear, iclass 40 cls_cnt 0 2006.169.08:29:59.51#ibcon#cleared, iclass 40 cls_cnt 0 2006.169.08:29:59.51$vc4f8/vabw=wide 2006.169.08:29:59.51#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.169.08:29:59.51#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.169.08:29:59.51#ibcon#ireg 8 cls_cnt 0 2006.169.08:29:59.51#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:29:59.51#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:29:59.51#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:29:59.51#ibcon#enter wrdev, iclass 4, count 0 2006.169.08:29:59.51#ibcon#first serial, iclass 4, count 0 2006.169.08:29:59.51#ibcon#enter sib2, iclass 4, count 0 2006.169.08:29:59.51#ibcon#flushed, iclass 4, count 0 2006.169.08:29:59.51#ibcon#about to write, iclass 4, count 0 2006.169.08:29:59.51#ibcon#wrote, iclass 4, count 0 2006.169.08:29:59.51#ibcon#about to read 3, iclass 4, count 0 2006.169.08:29:59.53#ibcon#read 3, iclass 4, count 0 2006.169.08:29:59.53#ibcon#about to read 4, iclass 4, count 0 2006.169.08:29:59.53#ibcon#read 4, iclass 4, count 0 2006.169.08:29:59.53#ibcon#about to read 5, iclass 4, count 0 2006.169.08:29:59.53#ibcon#read 5, iclass 4, count 0 2006.169.08:29:59.53#ibcon#about to read 6, iclass 4, count 0 2006.169.08:29:59.53#ibcon#read 6, iclass 4, count 0 2006.169.08:29:59.53#ibcon#end of sib2, iclass 4, count 0 2006.169.08:29:59.53#ibcon#*mode == 0, iclass 4, count 0 2006.169.08:29:59.53#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.169.08:29:59.53#ibcon#[25=BW32\r\n] 2006.169.08:29:59.53#ibcon#*before write, iclass 4, count 0 2006.169.08:29:59.53#ibcon#enter sib2, iclass 4, count 0 2006.169.08:29:59.53#ibcon#flushed, iclass 4, count 0 2006.169.08:29:59.53#ibcon#about to write, iclass 4, count 0 2006.169.08:29:59.53#ibcon#wrote, iclass 4, count 0 2006.169.08:29:59.53#ibcon#about to read 3, iclass 4, count 0 2006.169.08:29:59.56#ibcon#read 3, iclass 4, count 0 2006.169.08:29:59.56#ibcon#about to read 4, iclass 4, count 0 2006.169.08:29:59.56#ibcon#read 4, iclass 4, count 0 2006.169.08:29:59.56#ibcon#about to read 5, iclass 4, count 0 2006.169.08:29:59.56#ibcon#read 5, iclass 4, count 0 2006.169.08:29:59.56#ibcon#about to read 6, iclass 4, count 0 2006.169.08:29:59.56#ibcon#read 6, iclass 4, count 0 2006.169.08:29:59.56#ibcon#end of sib2, iclass 4, count 0 2006.169.08:29:59.56#ibcon#*after write, iclass 4, count 0 2006.169.08:29:59.56#ibcon#*before return 0, iclass 4, count 0 2006.169.08:29:59.56#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:29:59.56#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.169.08:29:59.56#ibcon#about to clear, iclass 4 cls_cnt 0 2006.169.08:29:59.56#ibcon#cleared, iclass 4 cls_cnt 0 2006.169.08:29:59.56$vc4f8/vbbw=wide 2006.169.08:29:59.56#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.169.08:29:59.56#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.169.08:29:59.56#ibcon#ireg 8 cls_cnt 0 2006.169.08:29:59.56#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:29:59.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:29:59.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:29:59.64#ibcon#enter wrdev, iclass 6, count 0 2006.169.08:29:59.64#ibcon#first serial, iclass 6, count 0 2006.169.08:29:59.64#ibcon#enter sib2, iclass 6, count 0 2006.169.08:29:59.64#ibcon#flushed, iclass 6, count 0 2006.169.08:29:59.64#ibcon#about to write, iclass 6, count 0 2006.169.08:29:59.64#ibcon#wrote, iclass 6, count 0 2006.169.08:29:59.64#ibcon#about to read 3, iclass 6, count 0 2006.169.08:29:59.65#ibcon#read 3, iclass 6, count 0 2006.169.08:29:59.65#ibcon#about to read 4, iclass 6, count 0 2006.169.08:29:59.65#ibcon#read 4, iclass 6, count 0 2006.169.08:29:59.65#ibcon#about to read 5, iclass 6, count 0 2006.169.08:29:59.65#ibcon#read 5, iclass 6, count 0 2006.169.08:29:59.65#ibcon#about to read 6, iclass 6, count 0 2006.169.08:29:59.65#ibcon#read 6, iclass 6, count 0 2006.169.08:29:59.65#ibcon#end of sib2, iclass 6, count 0 2006.169.08:29:59.65#ibcon#*mode == 0, iclass 6, count 0 2006.169.08:29:59.65#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.169.08:29:59.65#ibcon#[27=BW32\r\n] 2006.169.08:29:59.65#ibcon#*before write, iclass 6, count 0 2006.169.08:29:59.65#ibcon#enter sib2, iclass 6, count 0 2006.169.08:29:59.65#ibcon#flushed, iclass 6, count 0 2006.169.08:29:59.65#ibcon#about to write, iclass 6, count 0 2006.169.08:29:59.65#ibcon#wrote, iclass 6, count 0 2006.169.08:29:59.65#ibcon#about to read 3, iclass 6, count 0 2006.169.08:29:59.68#ibcon#read 3, iclass 6, count 0 2006.169.08:29:59.68#ibcon#about to read 4, iclass 6, count 0 2006.169.08:29:59.68#ibcon#read 4, iclass 6, count 0 2006.169.08:29:59.68#ibcon#about to read 5, iclass 6, count 0 2006.169.08:29:59.68#ibcon#read 5, iclass 6, count 0 2006.169.08:29:59.68#ibcon#about to read 6, iclass 6, count 0 2006.169.08:29:59.68#ibcon#read 6, iclass 6, count 0 2006.169.08:29:59.68#ibcon#end of sib2, iclass 6, count 0 2006.169.08:29:59.68#ibcon#*after write, iclass 6, count 0 2006.169.08:29:59.68#ibcon#*before return 0, iclass 6, count 0 2006.169.08:29:59.68#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:29:59.68#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.169.08:29:59.68#ibcon#about to clear, iclass 6 cls_cnt 0 2006.169.08:29:59.68#ibcon#cleared, iclass 6 cls_cnt 0 2006.169.08:29:59.68$4f8m12a/ifd4f 2006.169.08:29:59.68$ifd4f/lo= 2006.169.08:29:59.68$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.169.08:29:59.68$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.169.08:29:59.68$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.169.08:29:59.68$ifd4f/patch= 2006.169.08:29:59.68$ifd4f/patch=lo1,a1,a2,a3,a4 2006.169.08:29:59.68$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.169.08:29:59.68$ifd4f/patch=lo3,a5,a6,a7,a8 2006.169.08:29:59.68$4f8m12a/"form=m,16.000,1:2 2006.169.08:29:59.68$4f8m12a/"tpicd 2006.169.08:29:59.68$4f8m12a/echo=off 2006.169.08:29:59.68$4f8m12a/xlog=off 2006.169.08:29:59.68:!2006.169.08:30:10 2006.169.08:30:10.00:preob 2006.169.08:30:11.14/onsource/TRACKING 2006.169.08:30:11.14:!2006.169.08:30:20 2006.169.08:30:20.00:data_valid=on 2006.169.08:30:20.00:midob 2006.169.08:30:20.14/onsource/TRACKING 2006.169.08:30:20.14/wx/18.08,1003.8,100 2006.169.08:30:20.33/cable/+6.5284E-03 2006.169.08:30:21.42/va/01,08,usb,yes,40,42 2006.169.08:30:21.42/va/02,07,usb,yes,40,42 2006.169.08:30:21.42/va/03,06,usb,yes,42,43 2006.169.08:30:21.42/va/04,07,usb,yes,41,44 2006.169.08:30:21.42/va/05,07,usb,yes,45,47 2006.169.08:30:21.42/va/06,06,usb,yes,44,44 2006.169.08:30:21.42/va/07,06,usb,yes,45,44 2006.169.08:30:21.42/va/08,07,usb,yes,42,42 2006.169.08:30:21.65/valo/01,532.99,yes,locked 2006.169.08:30:21.65/valo/02,572.99,yes,locked 2006.169.08:30:21.65/valo/03,672.99,yes,locked 2006.169.08:30:21.65/valo/04,832.99,yes,locked 2006.169.08:30:21.65/valo/05,652.99,yes,locked 2006.169.08:30:21.65/valo/06,772.99,yes,locked 2006.169.08:30:21.65/valo/07,832.99,yes,locked 2006.169.08:30:21.65/valo/08,852.99,yes,locked 2006.169.08:30:22.74/vb/01,04,usb,yes,29,28 2006.169.08:30:22.74/vb/02,04,usb,yes,31,33 2006.169.08:30:22.74/vb/03,04,usb,yes,28,31 2006.169.08:30:22.74/vb/04,04,usb,yes,29,29 2006.169.08:30:22.74/vb/05,04,usb,yes,27,31 2006.169.08:30:22.74/vb/06,04,usb,yes,28,31 2006.169.08:30:22.74/vb/07,04,usb,yes,30,30 2006.169.08:30:22.74/vb/08,04,usb,yes,28,31 2006.169.08:30:22.97/vblo/01,632.99,yes,locked 2006.169.08:30:22.97/vblo/02,640.99,yes,locked 2006.169.08:30:22.97/vblo/03,656.99,yes,locked 2006.169.08:30:22.97/vblo/04,712.99,yes,locked 2006.169.08:30:22.97/vblo/05,744.99,yes,locked 2006.169.08:30:22.97/vblo/06,752.99,yes,locked 2006.169.08:30:22.97/vblo/07,734.99,yes,locked 2006.169.08:30:22.97/vblo/08,744.99,yes,locked 2006.169.08:30:23.12/vabw/8 2006.169.08:30:23.27/vbbw/8 2006.169.08:30:23.36/xfe/off,on,14.7 2006.169.08:30:23.75/ifatt/23,28,28,28 2006.169.08:30:24.08/fmout-gps/S +4.18E-07 2006.169.08:30:24.16:!2006.169.08:31:20 2006.169.08:31:20.00:data_valid=off 2006.169.08:31:20.01:postob 2006.169.08:31:20.20/cable/+6.5294E-03 2006.169.08:31:20.21/wx/18.07,1003.8,100 2006.169.08:31:21.08/fmout-gps/S +4.19E-07 2006.169.08:31:21.08:checkk5last 2006.169.08:31:21.09&checkk5last/chk_obsdata=1 2006.169.08:31:21.09&checkk5last/chk_obsdata=2 2006.169.08:31:21.10&checkk5last/chk_obsdata=3 2006.169.08:31:21.10&checkk5last/chk_obsdata=4 2006.169.08:31:21.10&checkk5last/k5log=1 2006.169.08:31:21.10&checkk5last/k5log=2 2006.169.08:31:21.10&checkk5last/k5log=3 2006.169.08:31:21.10&checkk5last/k5log=4 2006.169.08:31:21.10&checkk5last/obsinfo 2006.169.08:31:21.49/chk_obsdata//k5ts1/T1690830??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.169.08:31:21.86/chk_obsdata//k5ts2/T1690830??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.169.08:31:28.88/chk_obsdata//k5ts3?ERROR: timeout happened! 2006.169.08:31:29.26/chk_obsdata//k5ts4/T1690830??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.169.08:31:29.94/k5log//k5ts1_log_newline 2006.169.08:31:30.64/k5log//k5ts2_log_newline 2006.169.08:31:37.73/k5log//k5ts3?ERROR: timeout happened! 2006.169.08:31:38.42/k5log//k5ts4_log_newline 2006.169.08:31:38.51/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.169.08:31:38.51:sched_end 2006.169.08:31:38.51&sched_end/stopcheck 2006.169.08:31:38.51&stopcheck/sy=killall check_fsrun.pl 2006.169.08:31:38.51&stopcheck/" sy=killall chmem.sh 2006.169.08:31:38.61:source=idle 2006.169.08:31:39.14#flagr#flagr/antenna,new-source 2006.169.08:31:39.15:stow 2006.169.08:31:39.15&stow/source=idle 2006.169.08:31:39.15&stow/"this is stow command. 2006.169.08:31:39.15&stow/antenna=m3 2006.169.08:31:43.01:!+10m 2006.169.08:41:43.03:standby 2006.169.08:41:43.03&standby/"this is standby command. 2006.169.08:41:43.04&standby/antenna=m0 2006.169.08:41:44.01:sy=cp /usr2/log/k06169ts.log /usr2/log_backup/ 2006.169.08:41:44.10:*end of schedule