2006.168.07:02:04.09:Log Opened: Mark IV Field System Version 9.7.7 2006.168.07:02:04.09:location,TSUKUB32,-140.09,36.10,61.0 2006.168.07:02:04.10:horizon1,0.,5.,360. 2006.168.07:02:04.10:antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.168.07:02:04.10:equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.168.07:02:04.11:drivev11,330,270,no 2006.168.07:02:04.11:drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.168.07:02:04.11:drivev13,15.000,268,10.000,10.000,10.000 2006.168.07:02:04.12:drivev21,330,270,no 2006.168.07:02:04.12:drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.168.07:02:04.13:drivev23,15.000,268,10.000,10.000,10.000 2006.168.07:02:04.17:head10,all,all,all,odd,adaptive,no,5.0000,1 2006.168.07:02:04.18:head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.168.07:02:04.18:head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.168.07:02:04.18:head20,all,all,all,odd,adaptive,no,5.0000,1 2006.168.07:02:04.19:head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.168.07:02:04.19:head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.168.07:02:04.20:time,-0.364,101.533,rate 2006.168.07:02:04.20:flagr,200 2006.168.07:02:04.20:proc=k06168ts 2006.168.07:02:04.21:" k06168 2006 tsukub32 t ts 2006.168.07:02:04.21:" t tsukub32 azel .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 ts 108 2006.168.07:02:04.26:" ts tsukub32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.168.07:02:04.26:" 108 tsukub32 14 17400 2006.168.07:02:04.27:" drudg version 050216 compiled under fs 9.7.07 2006.168.07:02:04.27:" rack=k4-2/m4 recorder 1=k5 recorder 2=none 2006.168.07:02:04.27:!2006.168.07:19:50 2006.168.07:19:50.00:antenna=m2 2006.168.07:19:50.01:scan_name=168-0730,k06168,60 2006.168.07:19:50.02:source=3c371,180650.68,694928.1,2000.0,ccw 2006.168.07:19:50.02#antcn#PM 1 00019 2005 228 00 22 31 00 2006.168.07:19:50.02#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.168.07:19:50.02#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.168.07:19:50.02#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.168.07:19:50.02#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.168.07:19:50.02#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.168.07:19:50.13#flagr#flagr/antenna,new-source 2006.168.07:19:51.13:ready_k5 2006.168.07:19:51.13&ready_k5/obsinfo=st 2006.168.07:19:51.13&ready_k5/autoobs=1 2006.168.07:19:51.13&ready_k5/autoobs=2 2006.168.07:19:51.13&ready_k5/autoobs=3 2006.168.07:19:51.13&ready_k5/autoobs=4 2006.168.07:19:51.13&ready_k5/obsinfo 2006.168.07:19:51.13/obsinfo=st/error_log.tmp was not found (or not removed). 2006.168.07:19:54.35/autoobs//k5ts1/ autoobs started! 2006.168.07:19:57.47/autoobs//k5ts2/ autoobs started! 2006.168.07:20:00.59/autoobs//k5ts3/ autoobs started! 2006.168.07:20:03.69/autoobs//k5ts4/ autoobs started! 2006.168.07:20:03.72/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.07:20:03.72:4f8m12a=1 2006.168.07:20:03.72&4f8m12a/xlog=on 2006.168.07:20:03.72&4f8m12a/echo=on 2006.168.07:20:03.72&4f8m12a/pcalon 2006.168.07:20:03.72&4f8m12a/"tpicd=stop 2006.168.07:20:03.72&4f8m12a/vc4f8 2006.168.07:20:03.72&4f8m12a/ifd4f 2006.168.07:20:03.72&4f8m12a/"form=m,16.000,1:2 2006.168.07:20:03.72&4f8m12a/"tpicd 2006.168.07:20:03.72&4f8m12a/echo=off 2006.168.07:20:03.72&4f8m12a/xlog=off 2006.168.07:20:03.72$4f8m12a/echo=on 2006.168.07:20:03.72$4f8m12a/pcalon 2006.168.07:20:03.72&pcalon/"no phase cal control is implemented here 2006.168.07:20:03.72$pcalon/"no phase cal control is implemented here 2006.168.07:20:03.72$4f8m12a/"tpicd=stop 2006.168.07:20:03.72$4f8m12a/vc4f8 2006.168.07:20:03.72&vc4f8/valo=1,532.99 2006.168.07:20:03.72&vc4f8/va=1,8 2006.168.07:20:03.72&vc4f8/valo=2,572.99 2006.168.07:20:03.72&vc4f8/va=2,7 2006.168.07:20:03.72&vc4f8/valo=3,672.99 2006.168.07:20:03.72&vc4f8/va=3,6 2006.168.07:20:03.72&vc4f8/valo=4,832.99 2006.168.07:20:03.72&vc4f8/va=4,7 2006.168.07:20:03.72&vc4f8/valo=5,652.99 2006.168.07:20:03.72&vc4f8/va=5,7 2006.168.07:20:03.72&vc4f8/valo=6,772.99 2006.168.07:20:03.72&vc4f8/va=6,6 2006.168.07:20:03.72&vc4f8/valo=7,832.99 2006.168.07:20:03.72&vc4f8/va=7,6 2006.168.07:20:03.72&vc4f8/valo=8,852.99 2006.168.07:20:03.72&vc4f8/va=8,7 2006.168.07:20:03.72&vc4f8/vblo=1,632.99 2006.168.07:20:03.72&vc4f8/vb=1,4 2006.168.07:20:03.72&vc4f8/vblo=2,640.99 2006.168.07:20:03.72&vc4f8/vb=2,4 2006.168.07:20:03.72&vc4f8/vblo=3,656.99 2006.168.07:20:03.72&vc4f8/vb=3,4 2006.168.07:20:03.72&vc4f8/vblo=4,712.99 2006.168.07:20:03.72&vc4f8/vb=4,4 2006.168.07:20:03.72&vc4f8/vblo=5,744.99 2006.168.07:20:03.72&vc4f8/vb=5,4 2006.168.07:20:03.72&vc4f8/vblo=6,752.99 2006.168.07:20:03.72&vc4f8/vb=6,4 2006.168.07:20:03.72&vc4f8/vabw=wide 2006.168.07:20:03.72&vc4f8/vbbw=wide 2006.168.07:20:03.72$vc4f8/valo=1,532.99 2006.168.07:20:03.72#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.168.07:20:03.72#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.168.07:20:03.72#ibcon#ireg 17 cls_cnt 0 2006.168.07:20:03.72#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:20:03.72#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:20:03.72#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:20:03.72#ibcon#enter wrdev, iclass 31, count 0 2006.168.07:20:03.72#ibcon#first serial, iclass 31, count 0 2006.168.07:20:03.72#ibcon#enter sib2, iclass 31, count 0 2006.168.07:20:03.72#ibcon#flushed, iclass 31, count 0 2006.168.07:20:03.72#ibcon#about to write, iclass 31, count 0 2006.168.07:20:03.72#ibcon#wrote, iclass 31, count 0 2006.168.07:20:03.72#ibcon#about to read 3, iclass 31, count 0 2006.168.07:20:03.76#ibcon#read 3, iclass 31, count 0 2006.168.07:20:03.76#ibcon#about to read 4, iclass 31, count 0 2006.168.07:20:03.76#ibcon#read 4, iclass 31, count 0 2006.168.07:20:03.76#ibcon#about to read 5, iclass 31, count 0 2006.168.07:20:03.76#ibcon#read 5, iclass 31, count 0 2006.168.07:20:03.76#ibcon#about to read 6, iclass 31, count 0 2006.168.07:20:03.76#ibcon#read 6, iclass 31, count 0 2006.168.07:20:03.76#ibcon#end of sib2, iclass 31, count 0 2006.168.07:20:03.76#ibcon#*mode == 0, iclass 31, count 0 2006.168.07:20:03.76#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.168.07:20:03.76#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.07:20:03.76#ibcon#*before write, iclass 31, count 0 2006.168.07:20:03.76#ibcon#enter sib2, iclass 31, count 0 2006.168.07:20:03.76#ibcon#flushed, iclass 31, count 0 2006.168.07:20:03.76#ibcon#about to write, iclass 31, count 0 2006.168.07:20:03.76#ibcon#wrote, iclass 31, count 0 2006.168.07:20:03.76#ibcon#about to read 3, iclass 31, count 0 2006.168.07:20:03.78#abcon#{5=INTERFACE CLEAR} 2006.168.07:20:03.81#ibcon#read 3, iclass 31, count 0 2006.168.07:20:03.81#ibcon#about to read 4, iclass 31, count 0 2006.168.07:20:03.81#ibcon#read 4, iclass 31, count 0 2006.168.07:20:03.81#ibcon#about to read 5, iclass 31, count 0 2006.168.07:20:03.81#ibcon#read 5, iclass 31, count 0 2006.168.07:20:03.81#ibcon#about to read 6, iclass 31, count 0 2006.168.07:20:03.81#ibcon#read 6, iclass 31, count 0 2006.168.07:20:03.81#ibcon#end of sib2, iclass 31, count 0 2006.168.07:20:03.81#ibcon#*after write, iclass 31, count 0 2006.168.07:20:03.81#ibcon#*before return 0, iclass 31, count 0 2006.168.07:20:03.81#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:20:03.81#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:20:03.81#ibcon#about to clear, iclass 31 cls_cnt 0 2006.168.07:20:03.81#ibcon#cleared, iclass 31 cls_cnt 0 2006.168.07:20:03.81$vc4f8/va=1,8 2006.168.07:20:03.81#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.168.07:20:03.81#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.168.07:20:03.81#ibcon#ireg 11 cls_cnt 2 2006.168.07:20:03.81#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:20:03.81#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:20:03.81#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:20:03.81#ibcon#enter wrdev, iclass 35, count 2 2006.168.07:20:03.81#ibcon#first serial, iclass 35, count 2 2006.168.07:20:03.81#ibcon#enter sib2, iclass 35, count 2 2006.168.07:20:03.81#ibcon#flushed, iclass 35, count 2 2006.168.07:20:03.81#ibcon#about to write, iclass 35, count 2 2006.168.07:20:03.81#ibcon#wrote, iclass 35, count 2 2006.168.07:20:03.81#ibcon#about to read 3, iclass 35, count 2 2006.168.07:20:03.83#ibcon#read 3, iclass 35, count 2 2006.168.07:20:03.83#ibcon#about to read 4, iclass 35, count 2 2006.168.07:20:03.83#ibcon#read 4, iclass 35, count 2 2006.168.07:20:03.83#ibcon#about to read 5, iclass 35, count 2 2006.168.07:20:03.83#ibcon#read 5, iclass 35, count 2 2006.168.07:20:03.83#ibcon#about to read 6, iclass 35, count 2 2006.168.07:20:03.83#ibcon#read 6, iclass 35, count 2 2006.168.07:20:03.83#ibcon#end of sib2, iclass 35, count 2 2006.168.07:20:03.83#ibcon#*mode == 0, iclass 35, count 2 2006.168.07:20:03.83#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.168.07:20:03.83#ibcon#[25=AT01-08\r\n] 2006.168.07:20:03.83#ibcon#*before write, iclass 35, count 2 2006.168.07:20:03.83#ibcon#enter sib2, iclass 35, count 2 2006.168.07:20:03.83#ibcon#flushed, iclass 35, count 2 2006.168.07:20:03.83#ibcon#about to write, iclass 35, count 2 2006.168.07:20:03.83#ibcon#wrote, iclass 35, count 2 2006.168.07:20:03.83#ibcon#about to read 3, iclass 35, count 2 2006.168.07:20:03.84#abcon#[5=S1D000X0/0*\r\n] 2006.168.07:20:03.86#ibcon#read 3, iclass 35, count 2 2006.168.07:20:03.86#ibcon#about to read 4, iclass 35, count 2 2006.168.07:20:03.86#ibcon#read 4, iclass 35, count 2 2006.168.07:20:03.86#ibcon#about to read 5, iclass 35, count 2 2006.168.07:20:03.86#ibcon#read 5, iclass 35, count 2 2006.168.07:20:03.86#ibcon#about to read 6, iclass 35, count 2 2006.168.07:20:03.86#ibcon#read 6, iclass 35, count 2 2006.168.07:20:03.86#ibcon#end of sib2, iclass 35, count 2 2006.168.07:20:03.86#ibcon#*after write, iclass 35, count 2 2006.168.07:20:03.86#ibcon#*before return 0, iclass 35, count 2 2006.168.07:20:03.86#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:20:03.86#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:20:03.86#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.168.07:20:03.86#ibcon#ireg 7 cls_cnt 0 2006.168.07:20:03.86#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:20:03.98#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:20:03.98#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:20:03.98#ibcon#enter wrdev, iclass 35, count 0 2006.168.07:20:03.98#ibcon#first serial, iclass 35, count 0 2006.168.07:20:03.98#ibcon#enter sib2, iclass 35, count 0 2006.168.07:20:03.98#ibcon#flushed, iclass 35, count 0 2006.168.07:20:03.98#ibcon#about to write, iclass 35, count 0 2006.168.07:20:03.98#ibcon#wrote, iclass 35, count 0 2006.168.07:20:03.98#ibcon#about to read 3, iclass 35, count 0 2006.168.07:20:04.00#ibcon#read 3, iclass 35, count 0 2006.168.07:20:04.00#ibcon#about to read 4, iclass 35, count 0 2006.168.07:20:04.00#ibcon#read 4, iclass 35, count 0 2006.168.07:20:04.00#ibcon#about to read 5, iclass 35, count 0 2006.168.07:20:04.00#ibcon#read 5, iclass 35, count 0 2006.168.07:20:04.00#ibcon#about to read 6, iclass 35, count 0 2006.168.07:20:04.00#ibcon#read 6, iclass 35, count 0 2006.168.07:20:04.00#ibcon#end of sib2, iclass 35, count 0 2006.168.07:20:04.00#ibcon#*mode == 0, iclass 35, count 0 2006.168.07:20:04.00#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.168.07:20:04.00#ibcon#[25=USB\r\n] 2006.168.07:20:04.00#ibcon#*before write, iclass 35, count 0 2006.168.07:20:04.00#ibcon#enter sib2, iclass 35, count 0 2006.168.07:20:04.00#ibcon#flushed, iclass 35, count 0 2006.168.07:20:04.00#ibcon#about to write, iclass 35, count 0 2006.168.07:20:04.00#ibcon#wrote, iclass 35, count 0 2006.168.07:20:04.00#ibcon#about to read 3, iclass 35, count 0 2006.168.07:20:04.03#ibcon#read 3, iclass 35, count 0 2006.168.07:20:04.03#ibcon#about to read 4, iclass 35, count 0 2006.168.07:20:04.03#ibcon#read 4, iclass 35, count 0 2006.168.07:20:04.03#ibcon#about to read 5, iclass 35, count 0 2006.168.07:20:04.03#ibcon#read 5, iclass 35, count 0 2006.168.07:20:04.03#ibcon#about to read 6, iclass 35, count 0 2006.168.07:20:04.03#ibcon#read 6, iclass 35, count 0 2006.168.07:20:04.03#ibcon#end of sib2, iclass 35, count 0 2006.168.07:20:04.03#ibcon#*after write, iclass 35, count 0 2006.168.07:20:04.03#ibcon#*before return 0, iclass 35, count 0 2006.168.07:20:04.03#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:20:04.03#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:20:04.03#ibcon#about to clear, iclass 35 cls_cnt 0 2006.168.07:20:04.03#ibcon#cleared, iclass 35 cls_cnt 0 2006.168.07:20:04.03$vc4f8/valo=2,572.99 2006.168.07:20:04.03#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.168.07:20:04.03#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.168.07:20:04.03#ibcon#ireg 17 cls_cnt 0 2006.168.07:20:04.03#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:20:04.03#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:20:04.03#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:20:04.03#ibcon#enter wrdev, iclass 38, count 0 2006.168.07:20:04.03#ibcon#first serial, iclass 38, count 0 2006.168.07:20:04.03#ibcon#enter sib2, iclass 38, count 0 2006.168.07:20:04.03#ibcon#flushed, iclass 38, count 0 2006.168.07:20:04.03#ibcon#about to write, iclass 38, count 0 2006.168.07:20:04.03#ibcon#wrote, iclass 38, count 0 2006.168.07:20:04.03#ibcon#about to read 3, iclass 38, count 0 2006.168.07:20:04.05#ibcon#read 3, iclass 38, count 0 2006.168.07:20:04.05#ibcon#about to read 4, iclass 38, count 0 2006.168.07:20:04.05#ibcon#read 4, iclass 38, count 0 2006.168.07:20:04.05#ibcon#about to read 5, iclass 38, count 0 2006.168.07:20:04.05#ibcon#read 5, iclass 38, count 0 2006.168.07:20:04.05#ibcon#about to read 6, iclass 38, count 0 2006.168.07:20:04.05#ibcon#read 6, iclass 38, count 0 2006.168.07:20:04.05#ibcon#end of sib2, iclass 38, count 0 2006.168.07:20:04.05#ibcon#*mode == 0, iclass 38, count 0 2006.168.07:20:04.05#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.168.07:20:04.05#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.07:20:04.05#ibcon#*before write, iclass 38, count 0 2006.168.07:20:04.05#ibcon#enter sib2, iclass 38, count 0 2006.168.07:20:04.05#ibcon#flushed, iclass 38, count 0 2006.168.07:20:04.05#ibcon#about to write, iclass 38, count 0 2006.168.07:20:04.05#ibcon#wrote, iclass 38, count 0 2006.168.07:20:04.05#ibcon#about to read 3, iclass 38, count 0 2006.168.07:20:04.09#ibcon#read 3, iclass 38, count 0 2006.168.07:20:04.09#ibcon#about to read 4, iclass 38, count 0 2006.168.07:20:04.09#ibcon#read 4, iclass 38, count 0 2006.168.07:20:04.09#ibcon#about to read 5, iclass 38, count 0 2006.168.07:20:04.09#ibcon#read 5, iclass 38, count 0 2006.168.07:20:04.09#ibcon#about to read 6, iclass 38, count 0 2006.168.07:20:04.09#ibcon#read 6, iclass 38, count 0 2006.168.07:20:04.09#ibcon#end of sib2, iclass 38, count 0 2006.168.07:20:04.09#ibcon#*after write, iclass 38, count 0 2006.168.07:20:04.09#ibcon#*before return 0, iclass 38, count 0 2006.168.07:20:04.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:20:04.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:20:04.09#ibcon#about to clear, iclass 38 cls_cnt 0 2006.168.07:20:04.09#ibcon#cleared, iclass 38 cls_cnt 0 2006.168.07:20:04.09$vc4f8/va=2,7 2006.168.07:20:04.09#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.168.07:20:04.09#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.168.07:20:04.09#ibcon#ireg 11 cls_cnt 2 2006.168.07:20:04.09#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:20:04.15#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:20:04.15#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:20:04.15#ibcon#enter wrdev, iclass 40, count 2 2006.168.07:20:04.15#ibcon#first serial, iclass 40, count 2 2006.168.07:20:04.15#ibcon#enter sib2, iclass 40, count 2 2006.168.07:20:04.15#ibcon#flushed, iclass 40, count 2 2006.168.07:20:04.15#ibcon#about to write, iclass 40, count 2 2006.168.07:20:04.15#ibcon#wrote, iclass 40, count 2 2006.168.07:20:04.15#ibcon#about to read 3, iclass 40, count 2 2006.168.07:20:04.17#ibcon#read 3, iclass 40, count 2 2006.168.07:20:04.17#ibcon#about to read 4, iclass 40, count 2 2006.168.07:20:04.17#ibcon#read 4, iclass 40, count 2 2006.168.07:20:04.17#ibcon#about to read 5, iclass 40, count 2 2006.168.07:20:04.17#ibcon#read 5, iclass 40, count 2 2006.168.07:20:04.17#ibcon#about to read 6, iclass 40, count 2 2006.168.07:20:04.17#ibcon#read 6, iclass 40, count 2 2006.168.07:20:04.17#ibcon#end of sib2, iclass 40, count 2 2006.168.07:20:04.17#ibcon#*mode == 0, iclass 40, count 2 2006.168.07:20:04.17#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.168.07:20:04.17#ibcon#[25=AT02-07\r\n] 2006.168.07:20:04.17#ibcon#*before write, iclass 40, count 2 2006.168.07:20:04.17#ibcon#enter sib2, iclass 40, count 2 2006.168.07:20:04.17#ibcon#flushed, iclass 40, count 2 2006.168.07:20:04.17#ibcon#about to write, iclass 40, count 2 2006.168.07:20:04.17#ibcon#wrote, iclass 40, count 2 2006.168.07:20:04.17#ibcon#about to read 3, iclass 40, count 2 2006.168.07:20:04.20#ibcon#read 3, iclass 40, count 2 2006.168.07:20:04.20#ibcon#about to read 4, iclass 40, count 2 2006.168.07:20:04.20#ibcon#read 4, iclass 40, count 2 2006.168.07:20:04.20#ibcon#about to read 5, iclass 40, count 2 2006.168.07:20:04.20#ibcon#read 5, iclass 40, count 2 2006.168.07:20:04.20#ibcon#about to read 6, iclass 40, count 2 2006.168.07:20:04.20#ibcon#read 6, iclass 40, count 2 2006.168.07:20:04.20#ibcon#end of sib2, iclass 40, count 2 2006.168.07:20:04.20#ibcon#*after write, iclass 40, count 2 2006.168.07:20:04.20#ibcon#*before return 0, iclass 40, count 2 2006.168.07:20:04.20#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:20:04.20#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:20:04.20#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.168.07:20:04.20#ibcon#ireg 7 cls_cnt 0 2006.168.07:20:04.20#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:20:04.32#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:20:04.32#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:20:04.32#ibcon#enter wrdev, iclass 40, count 0 2006.168.07:20:04.32#ibcon#first serial, iclass 40, count 0 2006.168.07:20:04.32#ibcon#enter sib2, iclass 40, count 0 2006.168.07:20:04.32#ibcon#flushed, iclass 40, count 0 2006.168.07:20:04.32#ibcon#about to write, iclass 40, count 0 2006.168.07:20:04.32#ibcon#wrote, iclass 40, count 0 2006.168.07:20:04.32#ibcon#about to read 3, iclass 40, count 0 2006.168.07:20:04.34#ibcon#read 3, iclass 40, count 0 2006.168.07:20:04.34#ibcon#about to read 4, iclass 40, count 0 2006.168.07:20:04.34#ibcon#read 4, iclass 40, count 0 2006.168.07:20:04.34#ibcon#about to read 5, iclass 40, count 0 2006.168.07:20:04.34#ibcon#read 5, iclass 40, count 0 2006.168.07:20:04.34#ibcon#about to read 6, iclass 40, count 0 2006.168.07:20:04.34#ibcon#read 6, iclass 40, count 0 2006.168.07:20:04.34#ibcon#end of sib2, iclass 40, count 0 2006.168.07:20:04.34#ibcon#*mode == 0, iclass 40, count 0 2006.168.07:20:04.34#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.168.07:20:04.34#ibcon#[25=USB\r\n] 2006.168.07:20:04.34#ibcon#*before write, iclass 40, count 0 2006.168.07:20:04.34#ibcon#enter sib2, iclass 40, count 0 2006.168.07:20:04.34#ibcon#flushed, iclass 40, count 0 2006.168.07:20:04.34#ibcon#about to write, iclass 40, count 0 2006.168.07:20:04.34#ibcon#wrote, iclass 40, count 0 2006.168.07:20:04.34#ibcon#about to read 3, iclass 40, count 0 2006.168.07:20:04.37#ibcon#read 3, iclass 40, count 0 2006.168.07:20:04.37#ibcon#about to read 4, iclass 40, count 0 2006.168.07:20:04.37#ibcon#read 4, iclass 40, count 0 2006.168.07:20:04.37#ibcon#about to read 5, iclass 40, count 0 2006.168.07:20:04.37#ibcon#read 5, iclass 40, count 0 2006.168.07:20:04.37#ibcon#about to read 6, iclass 40, count 0 2006.168.07:20:04.37#ibcon#read 6, iclass 40, count 0 2006.168.07:20:04.37#ibcon#end of sib2, iclass 40, count 0 2006.168.07:20:04.37#ibcon#*after write, iclass 40, count 0 2006.168.07:20:04.37#ibcon#*before return 0, iclass 40, count 0 2006.168.07:20:04.37#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:20:04.37#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:20:04.37#ibcon#about to clear, iclass 40 cls_cnt 0 2006.168.07:20:04.37#ibcon#cleared, iclass 40 cls_cnt 0 2006.168.07:20:04.37$vc4f8/valo=3,672.99 2006.168.07:20:04.37#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.168.07:20:04.37#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.168.07:20:04.37#ibcon#ireg 17 cls_cnt 0 2006.168.07:20:04.37#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:20:04.37#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:20:04.37#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:20:04.37#ibcon#enter wrdev, iclass 4, count 0 2006.168.07:20:04.37#ibcon#first serial, iclass 4, count 0 2006.168.07:20:04.37#ibcon#enter sib2, iclass 4, count 0 2006.168.07:20:04.37#ibcon#flushed, iclass 4, count 0 2006.168.07:20:04.37#ibcon#about to write, iclass 4, count 0 2006.168.07:20:04.37#ibcon#wrote, iclass 4, count 0 2006.168.07:20:04.37#ibcon#about to read 3, iclass 4, count 0 2006.168.07:20:04.39#ibcon#read 3, iclass 4, count 0 2006.168.07:20:04.39#ibcon#about to read 4, iclass 4, count 0 2006.168.07:20:04.39#ibcon#read 4, iclass 4, count 0 2006.168.07:20:04.39#ibcon#about to read 5, iclass 4, count 0 2006.168.07:20:04.39#ibcon#read 5, iclass 4, count 0 2006.168.07:20:04.39#ibcon#about to read 6, iclass 4, count 0 2006.168.07:20:04.39#ibcon#read 6, iclass 4, count 0 2006.168.07:20:04.39#ibcon#end of sib2, iclass 4, count 0 2006.168.07:20:04.39#ibcon#*mode == 0, iclass 4, count 0 2006.168.07:20:04.39#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.168.07:20:04.39#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.07:20:04.39#ibcon#*before write, iclass 4, count 0 2006.168.07:20:04.39#ibcon#enter sib2, iclass 4, count 0 2006.168.07:20:04.39#ibcon#flushed, iclass 4, count 0 2006.168.07:20:04.39#ibcon#about to write, iclass 4, count 0 2006.168.07:20:04.39#ibcon#wrote, iclass 4, count 0 2006.168.07:20:04.39#ibcon#about to read 3, iclass 4, count 0 2006.168.07:20:04.43#ibcon#read 3, iclass 4, count 0 2006.168.07:20:04.43#ibcon#about to read 4, iclass 4, count 0 2006.168.07:20:04.43#ibcon#read 4, iclass 4, count 0 2006.168.07:20:04.43#ibcon#about to read 5, iclass 4, count 0 2006.168.07:20:04.43#ibcon#read 5, iclass 4, count 0 2006.168.07:20:04.43#ibcon#about to read 6, iclass 4, count 0 2006.168.07:20:04.43#ibcon#read 6, iclass 4, count 0 2006.168.07:20:04.43#ibcon#end of sib2, iclass 4, count 0 2006.168.07:20:04.43#ibcon#*after write, iclass 4, count 0 2006.168.07:20:04.43#ibcon#*before return 0, iclass 4, count 0 2006.168.07:20:04.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:20:04.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:20:04.43#ibcon#about to clear, iclass 4 cls_cnt 0 2006.168.07:20:04.43#ibcon#cleared, iclass 4 cls_cnt 0 2006.168.07:20:04.43$vc4f8/va=3,6 2006.168.07:20:04.43#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.168.07:20:04.43#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.168.07:20:04.43#ibcon#ireg 11 cls_cnt 2 2006.168.07:20:04.43#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:20:04.49#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:20:04.49#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:20:04.49#ibcon#enter wrdev, iclass 6, count 2 2006.168.07:20:04.49#ibcon#first serial, iclass 6, count 2 2006.168.07:20:04.49#ibcon#enter sib2, iclass 6, count 2 2006.168.07:20:04.49#ibcon#flushed, iclass 6, count 2 2006.168.07:20:04.49#ibcon#about to write, iclass 6, count 2 2006.168.07:20:04.49#ibcon#wrote, iclass 6, count 2 2006.168.07:20:04.49#ibcon#about to read 3, iclass 6, count 2 2006.168.07:20:04.51#ibcon#read 3, iclass 6, count 2 2006.168.07:20:04.51#ibcon#about to read 4, iclass 6, count 2 2006.168.07:20:04.51#ibcon#read 4, iclass 6, count 2 2006.168.07:20:04.51#ibcon#about to read 5, iclass 6, count 2 2006.168.07:20:04.51#ibcon#read 5, iclass 6, count 2 2006.168.07:20:04.51#ibcon#about to read 6, iclass 6, count 2 2006.168.07:20:04.51#ibcon#read 6, iclass 6, count 2 2006.168.07:20:04.51#ibcon#end of sib2, iclass 6, count 2 2006.168.07:20:04.51#ibcon#*mode == 0, iclass 6, count 2 2006.168.07:20:04.51#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.168.07:20:04.51#ibcon#[25=AT03-06\r\n] 2006.168.07:20:04.51#ibcon#*before write, iclass 6, count 2 2006.168.07:20:04.51#ibcon#enter sib2, iclass 6, count 2 2006.168.07:20:04.51#ibcon#flushed, iclass 6, count 2 2006.168.07:20:04.51#ibcon#about to write, iclass 6, count 2 2006.168.07:20:04.51#ibcon#wrote, iclass 6, count 2 2006.168.07:20:04.51#ibcon#about to read 3, iclass 6, count 2 2006.168.07:20:04.54#ibcon#read 3, iclass 6, count 2 2006.168.07:20:04.54#ibcon#about to read 4, iclass 6, count 2 2006.168.07:20:04.54#ibcon#read 4, iclass 6, count 2 2006.168.07:20:04.54#ibcon#about to read 5, iclass 6, count 2 2006.168.07:20:04.54#ibcon#read 5, iclass 6, count 2 2006.168.07:20:04.54#ibcon#about to read 6, iclass 6, count 2 2006.168.07:20:04.54#ibcon#read 6, iclass 6, count 2 2006.168.07:20:04.54#ibcon#end of sib2, iclass 6, count 2 2006.168.07:20:04.54#ibcon#*after write, iclass 6, count 2 2006.168.07:20:04.54#ibcon#*before return 0, iclass 6, count 2 2006.168.07:20:04.54#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:20:04.54#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:20:04.54#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.168.07:20:04.54#ibcon#ireg 7 cls_cnt 0 2006.168.07:20:04.54#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:20:04.66#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:20:04.66#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:20:04.66#ibcon#enter wrdev, iclass 6, count 0 2006.168.07:20:04.66#ibcon#first serial, iclass 6, count 0 2006.168.07:20:04.66#ibcon#enter sib2, iclass 6, count 0 2006.168.07:20:04.66#ibcon#flushed, iclass 6, count 0 2006.168.07:20:04.66#ibcon#about to write, iclass 6, count 0 2006.168.07:20:04.66#ibcon#wrote, iclass 6, count 0 2006.168.07:20:04.66#ibcon#about to read 3, iclass 6, count 0 2006.168.07:20:04.68#ibcon#read 3, iclass 6, count 0 2006.168.07:20:04.68#ibcon#about to read 4, iclass 6, count 0 2006.168.07:20:04.68#ibcon#read 4, iclass 6, count 0 2006.168.07:20:04.68#ibcon#about to read 5, iclass 6, count 0 2006.168.07:20:04.68#ibcon#read 5, iclass 6, count 0 2006.168.07:20:04.68#ibcon#about to read 6, iclass 6, count 0 2006.168.07:20:04.68#ibcon#read 6, iclass 6, count 0 2006.168.07:20:04.68#ibcon#end of sib2, iclass 6, count 0 2006.168.07:20:04.68#ibcon#*mode == 0, iclass 6, count 0 2006.168.07:20:04.68#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.168.07:20:04.68#ibcon#[25=USB\r\n] 2006.168.07:20:04.68#ibcon#*before write, iclass 6, count 0 2006.168.07:20:04.68#ibcon#enter sib2, iclass 6, count 0 2006.168.07:20:04.68#ibcon#flushed, iclass 6, count 0 2006.168.07:20:04.68#ibcon#about to write, iclass 6, count 0 2006.168.07:20:04.68#ibcon#wrote, iclass 6, count 0 2006.168.07:20:04.68#ibcon#about to read 3, iclass 6, count 0 2006.168.07:20:04.71#ibcon#read 3, iclass 6, count 0 2006.168.07:20:04.71#ibcon#about to read 4, iclass 6, count 0 2006.168.07:20:04.71#ibcon#read 4, iclass 6, count 0 2006.168.07:20:04.71#ibcon#about to read 5, iclass 6, count 0 2006.168.07:20:04.71#ibcon#read 5, iclass 6, count 0 2006.168.07:20:04.71#ibcon#about to read 6, iclass 6, count 0 2006.168.07:20:04.71#ibcon#read 6, iclass 6, count 0 2006.168.07:20:04.71#ibcon#end of sib2, iclass 6, count 0 2006.168.07:20:04.71#ibcon#*after write, iclass 6, count 0 2006.168.07:20:04.71#ibcon#*before return 0, iclass 6, count 0 2006.168.07:20:04.71#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:20:04.71#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:20:04.71#ibcon#about to clear, iclass 6 cls_cnt 0 2006.168.07:20:04.71#ibcon#cleared, iclass 6 cls_cnt 0 2006.168.07:20:04.71$vc4f8/valo=4,832.99 2006.168.07:20:04.71#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.168.07:20:04.71#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.168.07:20:04.71#ibcon#ireg 17 cls_cnt 0 2006.168.07:20:04.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:20:04.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:20:04.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:20:04.71#ibcon#enter wrdev, iclass 10, count 0 2006.168.07:20:04.71#ibcon#first serial, iclass 10, count 0 2006.168.07:20:04.71#ibcon#enter sib2, iclass 10, count 0 2006.168.07:20:04.71#ibcon#flushed, iclass 10, count 0 2006.168.07:20:04.71#ibcon#about to write, iclass 10, count 0 2006.168.07:20:04.71#ibcon#wrote, iclass 10, count 0 2006.168.07:20:04.71#ibcon#about to read 3, iclass 10, count 0 2006.168.07:20:04.73#ibcon#read 3, iclass 10, count 0 2006.168.07:20:04.73#ibcon#about to read 4, iclass 10, count 0 2006.168.07:20:04.73#ibcon#read 4, iclass 10, count 0 2006.168.07:20:04.73#ibcon#about to read 5, iclass 10, count 0 2006.168.07:20:04.73#ibcon#read 5, iclass 10, count 0 2006.168.07:20:04.73#ibcon#about to read 6, iclass 10, count 0 2006.168.07:20:04.73#ibcon#read 6, iclass 10, count 0 2006.168.07:20:04.73#ibcon#end of sib2, iclass 10, count 0 2006.168.07:20:04.73#ibcon#*mode == 0, iclass 10, count 0 2006.168.07:20:04.73#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.168.07:20:04.73#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.07:20:04.73#ibcon#*before write, iclass 10, count 0 2006.168.07:20:04.73#ibcon#enter sib2, iclass 10, count 0 2006.168.07:20:04.73#ibcon#flushed, iclass 10, count 0 2006.168.07:20:04.73#ibcon#about to write, iclass 10, count 0 2006.168.07:20:04.73#ibcon#wrote, iclass 10, count 0 2006.168.07:20:04.73#ibcon#about to read 3, iclass 10, count 0 2006.168.07:20:04.77#ibcon#read 3, iclass 10, count 0 2006.168.07:20:04.77#ibcon#about to read 4, iclass 10, count 0 2006.168.07:20:04.77#ibcon#read 4, iclass 10, count 0 2006.168.07:20:04.77#ibcon#about to read 5, iclass 10, count 0 2006.168.07:20:04.77#ibcon#read 5, iclass 10, count 0 2006.168.07:20:04.77#ibcon#about to read 6, iclass 10, count 0 2006.168.07:20:04.77#ibcon#read 6, iclass 10, count 0 2006.168.07:20:04.77#ibcon#end of sib2, iclass 10, count 0 2006.168.07:20:04.77#ibcon#*after write, iclass 10, count 0 2006.168.07:20:04.77#ibcon#*before return 0, iclass 10, count 0 2006.168.07:20:04.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:20:04.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:20:04.77#ibcon#about to clear, iclass 10 cls_cnt 0 2006.168.07:20:04.77#ibcon#cleared, iclass 10 cls_cnt 0 2006.168.07:20:04.77$vc4f8/va=4,7 2006.168.07:20:04.77#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.168.07:20:04.77#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.168.07:20:04.77#ibcon#ireg 11 cls_cnt 2 2006.168.07:20:04.77#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:20:04.83#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:20:04.83#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:20:04.83#ibcon#enter wrdev, iclass 12, count 2 2006.168.07:20:04.83#ibcon#first serial, iclass 12, count 2 2006.168.07:20:04.83#ibcon#enter sib2, iclass 12, count 2 2006.168.07:20:04.83#ibcon#flushed, iclass 12, count 2 2006.168.07:20:04.83#ibcon#about to write, iclass 12, count 2 2006.168.07:20:04.83#ibcon#wrote, iclass 12, count 2 2006.168.07:20:04.83#ibcon#about to read 3, iclass 12, count 2 2006.168.07:20:04.85#ibcon#read 3, iclass 12, count 2 2006.168.07:20:04.85#ibcon#about to read 4, iclass 12, count 2 2006.168.07:20:04.85#ibcon#read 4, iclass 12, count 2 2006.168.07:20:04.85#ibcon#about to read 5, iclass 12, count 2 2006.168.07:20:04.85#ibcon#read 5, iclass 12, count 2 2006.168.07:20:04.85#ibcon#about to read 6, iclass 12, count 2 2006.168.07:20:04.85#ibcon#read 6, iclass 12, count 2 2006.168.07:20:04.85#ibcon#end of sib2, iclass 12, count 2 2006.168.07:20:04.85#ibcon#*mode == 0, iclass 12, count 2 2006.168.07:20:04.85#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.168.07:20:04.85#ibcon#[25=AT04-07\r\n] 2006.168.07:20:04.85#ibcon#*before write, iclass 12, count 2 2006.168.07:20:04.85#ibcon#enter sib2, iclass 12, count 2 2006.168.07:20:04.85#ibcon#flushed, iclass 12, count 2 2006.168.07:20:04.85#ibcon#about to write, iclass 12, count 2 2006.168.07:20:04.85#ibcon#wrote, iclass 12, count 2 2006.168.07:20:04.85#ibcon#about to read 3, iclass 12, count 2 2006.168.07:20:04.88#ibcon#read 3, iclass 12, count 2 2006.168.07:20:04.88#ibcon#about to read 4, iclass 12, count 2 2006.168.07:20:04.88#ibcon#read 4, iclass 12, count 2 2006.168.07:20:04.88#ibcon#about to read 5, iclass 12, count 2 2006.168.07:20:04.88#ibcon#read 5, iclass 12, count 2 2006.168.07:20:04.88#ibcon#about to read 6, iclass 12, count 2 2006.168.07:20:04.88#ibcon#read 6, iclass 12, count 2 2006.168.07:20:04.88#ibcon#end of sib2, iclass 12, count 2 2006.168.07:20:04.88#ibcon#*after write, iclass 12, count 2 2006.168.07:20:04.88#ibcon#*before return 0, iclass 12, count 2 2006.168.07:20:04.88#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:20:04.88#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:20:04.88#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.168.07:20:04.88#ibcon#ireg 7 cls_cnt 0 2006.168.07:20:04.88#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:20:05.00#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:20:05.00#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:20:05.00#ibcon#enter wrdev, iclass 12, count 0 2006.168.07:20:05.00#ibcon#first serial, iclass 12, count 0 2006.168.07:20:05.00#ibcon#enter sib2, iclass 12, count 0 2006.168.07:20:05.00#ibcon#flushed, iclass 12, count 0 2006.168.07:20:05.00#ibcon#about to write, iclass 12, count 0 2006.168.07:20:05.00#ibcon#wrote, iclass 12, count 0 2006.168.07:20:05.00#ibcon#about to read 3, iclass 12, count 0 2006.168.07:20:05.02#ibcon#read 3, iclass 12, count 0 2006.168.07:20:05.02#ibcon#about to read 4, iclass 12, count 0 2006.168.07:20:05.02#ibcon#read 4, iclass 12, count 0 2006.168.07:20:05.02#ibcon#about to read 5, iclass 12, count 0 2006.168.07:20:05.02#ibcon#read 5, iclass 12, count 0 2006.168.07:20:05.02#ibcon#about to read 6, iclass 12, count 0 2006.168.07:20:05.02#ibcon#read 6, iclass 12, count 0 2006.168.07:20:05.02#ibcon#end of sib2, iclass 12, count 0 2006.168.07:20:05.02#ibcon#*mode == 0, iclass 12, count 0 2006.168.07:20:05.02#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.168.07:20:05.02#ibcon#[25=USB\r\n] 2006.168.07:20:05.02#ibcon#*before write, iclass 12, count 0 2006.168.07:20:05.02#ibcon#enter sib2, iclass 12, count 0 2006.168.07:20:05.02#ibcon#flushed, iclass 12, count 0 2006.168.07:20:05.02#ibcon#about to write, iclass 12, count 0 2006.168.07:20:05.02#ibcon#wrote, iclass 12, count 0 2006.168.07:20:05.02#ibcon#about to read 3, iclass 12, count 0 2006.168.07:20:05.05#ibcon#read 3, iclass 12, count 0 2006.168.07:20:05.05#ibcon#about to read 4, iclass 12, count 0 2006.168.07:20:05.05#ibcon#read 4, iclass 12, count 0 2006.168.07:20:05.05#ibcon#about to read 5, iclass 12, count 0 2006.168.07:20:05.05#ibcon#read 5, iclass 12, count 0 2006.168.07:20:05.05#ibcon#about to read 6, iclass 12, count 0 2006.168.07:20:05.05#ibcon#read 6, iclass 12, count 0 2006.168.07:20:05.05#ibcon#end of sib2, iclass 12, count 0 2006.168.07:20:05.05#ibcon#*after write, iclass 12, count 0 2006.168.07:20:05.05#ibcon#*before return 0, iclass 12, count 0 2006.168.07:20:05.05#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:20:05.05#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:20:05.05#ibcon#about to clear, iclass 12 cls_cnt 0 2006.168.07:20:05.05#ibcon#cleared, iclass 12 cls_cnt 0 2006.168.07:20:05.05$vc4f8/valo=5,652.99 2006.168.07:20:05.05#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.168.07:20:05.05#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.168.07:20:05.05#ibcon#ireg 17 cls_cnt 0 2006.168.07:20:05.05#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:20:05.05#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:20:05.05#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:20:05.05#ibcon#enter wrdev, iclass 14, count 0 2006.168.07:20:05.05#ibcon#first serial, iclass 14, count 0 2006.168.07:20:05.05#ibcon#enter sib2, iclass 14, count 0 2006.168.07:20:05.05#ibcon#flushed, iclass 14, count 0 2006.168.07:20:05.05#ibcon#about to write, iclass 14, count 0 2006.168.07:20:05.05#ibcon#wrote, iclass 14, count 0 2006.168.07:20:05.05#ibcon#about to read 3, iclass 14, count 0 2006.168.07:20:05.07#ibcon#read 3, iclass 14, count 0 2006.168.07:20:05.07#ibcon#about to read 4, iclass 14, count 0 2006.168.07:20:05.07#ibcon#read 4, iclass 14, count 0 2006.168.07:20:05.07#ibcon#about to read 5, iclass 14, count 0 2006.168.07:20:05.07#ibcon#read 5, iclass 14, count 0 2006.168.07:20:05.07#ibcon#about to read 6, iclass 14, count 0 2006.168.07:20:05.07#ibcon#read 6, iclass 14, count 0 2006.168.07:20:05.07#ibcon#end of sib2, iclass 14, count 0 2006.168.07:20:05.07#ibcon#*mode == 0, iclass 14, count 0 2006.168.07:20:05.07#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.168.07:20:05.07#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.07:20:05.07#ibcon#*before write, iclass 14, count 0 2006.168.07:20:05.07#ibcon#enter sib2, iclass 14, count 0 2006.168.07:20:05.07#ibcon#flushed, iclass 14, count 0 2006.168.07:20:05.07#ibcon#about to write, iclass 14, count 0 2006.168.07:20:05.07#ibcon#wrote, iclass 14, count 0 2006.168.07:20:05.07#ibcon#about to read 3, iclass 14, count 0 2006.168.07:20:05.11#ibcon#read 3, iclass 14, count 0 2006.168.07:20:05.11#ibcon#about to read 4, iclass 14, count 0 2006.168.07:20:05.11#ibcon#read 4, iclass 14, count 0 2006.168.07:20:05.11#ibcon#about to read 5, iclass 14, count 0 2006.168.07:20:05.11#ibcon#read 5, iclass 14, count 0 2006.168.07:20:05.11#ibcon#about to read 6, iclass 14, count 0 2006.168.07:20:05.11#ibcon#read 6, iclass 14, count 0 2006.168.07:20:05.11#ibcon#end of sib2, iclass 14, count 0 2006.168.07:20:05.11#ibcon#*after write, iclass 14, count 0 2006.168.07:20:05.11#ibcon#*before return 0, iclass 14, count 0 2006.168.07:20:05.11#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:20:05.11#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:20:05.11#ibcon#about to clear, iclass 14 cls_cnt 0 2006.168.07:20:05.11#ibcon#cleared, iclass 14 cls_cnt 0 2006.168.07:20:05.11$vc4f8/va=5,7 2006.168.07:20:05.11#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.168.07:20:05.11#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.168.07:20:05.11#ibcon#ireg 11 cls_cnt 2 2006.168.07:20:05.11#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:20:05.17#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:20:05.17#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:20:05.17#ibcon#enter wrdev, iclass 16, count 2 2006.168.07:20:05.17#ibcon#first serial, iclass 16, count 2 2006.168.07:20:05.17#ibcon#enter sib2, iclass 16, count 2 2006.168.07:20:05.17#ibcon#flushed, iclass 16, count 2 2006.168.07:20:05.17#ibcon#about to write, iclass 16, count 2 2006.168.07:20:05.17#ibcon#wrote, iclass 16, count 2 2006.168.07:20:05.17#ibcon#about to read 3, iclass 16, count 2 2006.168.07:20:05.19#ibcon#read 3, iclass 16, count 2 2006.168.07:20:05.19#ibcon#about to read 4, iclass 16, count 2 2006.168.07:20:05.19#ibcon#read 4, iclass 16, count 2 2006.168.07:20:05.19#ibcon#about to read 5, iclass 16, count 2 2006.168.07:20:05.19#ibcon#read 5, iclass 16, count 2 2006.168.07:20:05.19#ibcon#about to read 6, iclass 16, count 2 2006.168.07:20:05.19#ibcon#read 6, iclass 16, count 2 2006.168.07:20:05.19#ibcon#end of sib2, iclass 16, count 2 2006.168.07:20:05.19#ibcon#*mode == 0, iclass 16, count 2 2006.168.07:20:05.19#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.168.07:20:05.19#ibcon#[25=AT05-07\r\n] 2006.168.07:20:05.19#ibcon#*before write, iclass 16, count 2 2006.168.07:20:05.19#ibcon#enter sib2, iclass 16, count 2 2006.168.07:20:05.19#ibcon#flushed, iclass 16, count 2 2006.168.07:20:05.19#ibcon#about to write, iclass 16, count 2 2006.168.07:20:05.19#ibcon#wrote, iclass 16, count 2 2006.168.07:20:05.19#ibcon#about to read 3, iclass 16, count 2 2006.168.07:20:05.22#ibcon#read 3, iclass 16, count 2 2006.168.07:20:05.22#ibcon#about to read 4, iclass 16, count 2 2006.168.07:20:05.22#ibcon#read 4, iclass 16, count 2 2006.168.07:20:05.22#ibcon#about to read 5, iclass 16, count 2 2006.168.07:20:05.22#ibcon#read 5, iclass 16, count 2 2006.168.07:20:05.22#ibcon#about to read 6, iclass 16, count 2 2006.168.07:20:05.22#ibcon#read 6, iclass 16, count 2 2006.168.07:20:05.22#ibcon#end of sib2, iclass 16, count 2 2006.168.07:20:05.22#ibcon#*after write, iclass 16, count 2 2006.168.07:20:05.22#ibcon#*before return 0, iclass 16, count 2 2006.168.07:20:05.22#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:20:05.22#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:20:05.22#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.168.07:20:05.22#ibcon#ireg 7 cls_cnt 0 2006.168.07:20:05.22#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:20:05.34#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:20:05.34#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:20:05.34#ibcon#enter wrdev, iclass 16, count 0 2006.168.07:20:05.34#ibcon#first serial, iclass 16, count 0 2006.168.07:20:05.34#ibcon#enter sib2, iclass 16, count 0 2006.168.07:20:05.34#ibcon#flushed, iclass 16, count 0 2006.168.07:20:05.34#ibcon#about to write, iclass 16, count 0 2006.168.07:20:05.34#ibcon#wrote, iclass 16, count 0 2006.168.07:20:05.34#ibcon#about to read 3, iclass 16, count 0 2006.168.07:20:05.36#ibcon#read 3, iclass 16, count 0 2006.168.07:20:05.36#ibcon#about to read 4, iclass 16, count 0 2006.168.07:20:05.36#ibcon#read 4, iclass 16, count 0 2006.168.07:20:05.36#ibcon#about to read 5, iclass 16, count 0 2006.168.07:20:05.36#ibcon#read 5, iclass 16, count 0 2006.168.07:20:05.36#ibcon#about to read 6, iclass 16, count 0 2006.168.07:20:05.36#ibcon#read 6, iclass 16, count 0 2006.168.07:20:05.36#ibcon#end of sib2, iclass 16, count 0 2006.168.07:20:05.36#ibcon#*mode == 0, iclass 16, count 0 2006.168.07:20:05.36#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.168.07:20:05.36#ibcon#[25=USB\r\n] 2006.168.07:20:05.36#ibcon#*before write, iclass 16, count 0 2006.168.07:20:05.36#ibcon#enter sib2, iclass 16, count 0 2006.168.07:20:05.36#ibcon#flushed, iclass 16, count 0 2006.168.07:20:05.36#ibcon#about to write, iclass 16, count 0 2006.168.07:20:05.36#ibcon#wrote, iclass 16, count 0 2006.168.07:20:05.36#ibcon#about to read 3, iclass 16, count 0 2006.168.07:20:05.39#ibcon#read 3, iclass 16, count 0 2006.168.07:20:05.39#ibcon#about to read 4, iclass 16, count 0 2006.168.07:20:05.39#ibcon#read 4, iclass 16, count 0 2006.168.07:20:05.39#ibcon#about to read 5, iclass 16, count 0 2006.168.07:20:05.39#ibcon#read 5, iclass 16, count 0 2006.168.07:20:05.39#ibcon#about to read 6, iclass 16, count 0 2006.168.07:20:05.39#ibcon#read 6, iclass 16, count 0 2006.168.07:20:05.39#ibcon#end of sib2, iclass 16, count 0 2006.168.07:20:05.39#ibcon#*after write, iclass 16, count 0 2006.168.07:20:05.39#ibcon#*before return 0, iclass 16, count 0 2006.168.07:20:05.39#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:20:05.39#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:20:05.39#ibcon#about to clear, iclass 16 cls_cnt 0 2006.168.07:20:05.39#ibcon#cleared, iclass 16 cls_cnt 0 2006.168.07:20:05.39$vc4f8/valo=6,772.99 2006.168.07:20:05.39#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.168.07:20:05.39#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.168.07:20:05.39#ibcon#ireg 17 cls_cnt 0 2006.168.07:20:05.39#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:20:05.39#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:20:05.39#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:20:05.39#ibcon#enter wrdev, iclass 18, count 0 2006.168.07:20:05.39#ibcon#first serial, iclass 18, count 0 2006.168.07:20:05.39#ibcon#enter sib2, iclass 18, count 0 2006.168.07:20:05.39#ibcon#flushed, iclass 18, count 0 2006.168.07:20:05.39#ibcon#about to write, iclass 18, count 0 2006.168.07:20:05.39#ibcon#wrote, iclass 18, count 0 2006.168.07:20:05.39#ibcon#about to read 3, iclass 18, count 0 2006.168.07:20:05.41#ibcon#read 3, iclass 18, count 0 2006.168.07:20:05.41#ibcon#about to read 4, iclass 18, count 0 2006.168.07:20:05.41#ibcon#read 4, iclass 18, count 0 2006.168.07:20:05.41#ibcon#about to read 5, iclass 18, count 0 2006.168.07:20:05.41#ibcon#read 5, iclass 18, count 0 2006.168.07:20:05.41#ibcon#about to read 6, iclass 18, count 0 2006.168.07:20:05.41#ibcon#read 6, iclass 18, count 0 2006.168.07:20:05.41#ibcon#end of sib2, iclass 18, count 0 2006.168.07:20:05.41#ibcon#*mode == 0, iclass 18, count 0 2006.168.07:20:05.41#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.07:20:05.41#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.07:20:05.41#ibcon#*before write, iclass 18, count 0 2006.168.07:20:05.41#ibcon#enter sib2, iclass 18, count 0 2006.168.07:20:05.41#ibcon#flushed, iclass 18, count 0 2006.168.07:20:05.41#ibcon#about to write, iclass 18, count 0 2006.168.07:20:05.41#ibcon#wrote, iclass 18, count 0 2006.168.07:20:05.41#ibcon#about to read 3, iclass 18, count 0 2006.168.07:20:05.45#ibcon#read 3, iclass 18, count 0 2006.168.07:20:05.45#ibcon#about to read 4, iclass 18, count 0 2006.168.07:20:05.45#ibcon#read 4, iclass 18, count 0 2006.168.07:20:05.45#ibcon#about to read 5, iclass 18, count 0 2006.168.07:20:05.45#ibcon#read 5, iclass 18, count 0 2006.168.07:20:05.45#ibcon#about to read 6, iclass 18, count 0 2006.168.07:20:05.45#ibcon#read 6, iclass 18, count 0 2006.168.07:20:05.45#ibcon#end of sib2, iclass 18, count 0 2006.168.07:20:05.45#ibcon#*after write, iclass 18, count 0 2006.168.07:20:05.45#ibcon#*before return 0, iclass 18, count 0 2006.168.07:20:05.45#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:20:05.45#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:20:05.45#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.07:20:05.45#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.07:20:05.45$vc4f8/va=6,6 2006.168.07:20:05.45#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.168.07:20:05.45#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.168.07:20:05.45#ibcon#ireg 11 cls_cnt 2 2006.168.07:20:05.45#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:20:05.51#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:20:05.51#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:20:05.51#ibcon#enter wrdev, iclass 20, count 2 2006.168.07:20:05.51#ibcon#first serial, iclass 20, count 2 2006.168.07:20:05.51#ibcon#enter sib2, iclass 20, count 2 2006.168.07:20:05.51#ibcon#flushed, iclass 20, count 2 2006.168.07:20:05.51#ibcon#about to write, iclass 20, count 2 2006.168.07:20:05.51#ibcon#wrote, iclass 20, count 2 2006.168.07:20:05.51#ibcon#about to read 3, iclass 20, count 2 2006.168.07:20:05.53#ibcon#read 3, iclass 20, count 2 2006.168.07:20:05.53#ibcon#about to read 4, iclass 20, count 2 2006.168.07:20:05.53#ibcon#read 4, iclass 20, count 2 2006.168.07:20:05.53#ibcon#about to read 5, iclass 20, count 2 2006.168.07:20:05.53#ibcon#read 5, iclass 20, count 2 2006.168.07:20:05.53#ibcon#about to read 6, iclass 20, count 2 2006.168.07:20:05.53#ibcon#read 6, iclass 20, count 2 2006.168.07:20:05.53#ibcon#end of sib2, iclass 20, count 2 2006.168.07:20:05.53#ibcon#*mode == 0, iclass 20, count 2 2006.168.07:20:05.53#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.168.07:20:05.53#ibcon#[25=AT06-06\r\n] 2006.168.07:20:05.53#ibcon#*before write, iclass 20, count 2 2006.168.07:20:05.53#ibcon#enter sib2, iclass 20, count 2 2006.168.07:20:05.53#ibcon#flushed, iclass 20, count 2 2006.168.07:20:05.53#ibcon#about to write, iclass 20, count 2 2006.168.07:20:05.53#ibcon#wrote, iclass 20, count 2 2006.168.07:20:05.53#ibcon#about to read 3, iclass 20, count 2 2006.168.07:20:05.56#ibcon#read 3, iclass 20, count 2 2006.168.07:20:05.56#ibcon#about to read 4, iclass 20, count 2 2006.168.07:20:05.56#ibcon#read 4, iclass 20, count 2 2006.168.07:20:05.56#ibcon#about to read 5, iclass 20, count 2 2006.168.07:20:05.56#ibcon#read 5, iclass 20, count 2 2006.168.07:20:05.56#ibcon#about to read 6, iclass 20, count 2 2006.168.07:20:05.56#ibcon#read 6, iclass 20, count 2 2006.168.07:20:05.56#ibcon#end of sib2, iclass 20, count 2 2006.168.07:20:05.56#ibcon#*after write, iclass 20, count 2 2006.168.07:20:05.56#ibcon#*before return 0, iclass 20, count 2 2006.168.07:20:05.56#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:20:05.56#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:20:05.56#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.168.07:20:05.56#ibcon#ireg 7 cls_cnt 0 2006.168.07:20:05.56#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:20:05.68#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:20:05.68#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:20:05.68#ibcon#enter wrdev, iclass 20, count 0 2006.168.07:20:05.68#ibcon#first serial, iclass 20, count 0 2006.168.07:20:05.68#ibcon#enter sib2, iclass 20, count 0 2006.168.07:20:05.68#ibcon#flushed, iclass 20, count 0 2006.168.07:20:05.68#ibcon#about to write, iclass 20, count 0 2006.168.07:20:05.68#ibcon#wrote, iclass 20, count 0 2006.168.07:20:05.68#ibcon#about to read 3, iclass 20, count 0 2006.168.07:20:05.70#ibcon#read 3, iclass 20, count 0 2006.168.07:20:05.70#ibcon#about to read 4, iclass 20, count 0 2006.168.07:20:05.70#ibcon#read 4, iclass 20, count 0 2006.168.07:20:05.70#ibcon#about to read 5, iclass 20, count 0 2006.168.07:20:05.70#ibcon#read 5, iclass 20, count 0 2006.168.07:20:05.70#ibcon#about to read 6, iclass 20, count 0 2006.168.07:20:05.70#ibcon#read 6, iclass 20, count 0 2006.168.07:20:05.70#ibcon#end of sib2, iclass 20, count 0 2006.168.07:20:05.70#ibcon#*mode == 0, iclass 20, count 0 2006.168.07:20:05.70#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.168.07:20:05.70#ibcon#[25=USB\r\n] 2006.168.07:20:05.70#ibcon#*before write, iclass 20, count 0 2006.168.07:20:05.70#ibcon#enter sib2, iclass 20, count 0 2006.168.07:20:05.70#ibcon#flushed, iclass 20, count 0 2006.168.07:20:05.70#ibcon#about to write, iclass 20, count 0 2006.168.07:20:05.70#ibcon#wrote, iclass 20, count 0 2006.168.07:20:05.70#ibcon#about to read 3, iclass 20, count 0 2006.168.07:20:05.73#ibcon#read 3, iclass 20, count 0 2006.168.07:20:05.73#ibcon#about to read 4, iclass 20, count 0 2006.168.07:20:05.73#ibcon#read 4, iclass 20, count 0 2006.168.07:20:05.73#ibcon#about to read 5, iclass 20, count 0 2006.168.07:20:05.73#ibcon#read 5, iclass 20, count 0 2006.168.07:20:05.73#ibcon#about to read 6, iclass 20, count 0 2006.168.07:20:05.73#ibcon#read 6, iclass 20, count 0 2006.168.07:20:05.73#ibcon#end of sib2, iclass 20, count 0 2006.168.07:20:05.73#ibcon#*after write, iclass 20, count 0 2006.168.07:20:05.73#ibcon#*before return 0, iclass 20, count 0 2006.168.07:20:05.73#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:20:05.73#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:20:05.73#ibcon#about to clear, iclass 20 cls_cnt 0 2006.168.07:20:05.73#ibcon#cleared, iclass 20 cls_cnt 0 2006.168.07:20:05.73$vc4f8/valo=7,832.99 2006.168.07:20:05.73#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.168.07:20:05.73#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.168.07:20:05.73#ibcon#ireg 17 cls_cnt 0 2006.168.07:20:05.73#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:20:05.73#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:20:05.73#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:20:05.73#ibcon#enter wrdev, iclass 22, count 0 2006.168.07:20:05.73#ibcon#first serial, iclass 22, count 0 2006.168.07:20:05.73#ibcon#enter sib2, iclass 22, count 0 2006.168.07:20:05.73#ibcon#flushed, iclass 22, count 0 2006.168.07:20:05.73#ibcon#about to write, iclass 22, count 0 2006.168.07:20:05.73#ibcon#wrote, iclass 22, count 0 2006.168.07:20:05.73#ibcon#about to read 3, iclass 22, count 0 2006.168.07:20:05.75#ibcon#read 3, iclass 22, count 0 2006.168.07:20:05.75#ibcon#about to read 4, iclass 22, count 0 2006.168.07:20:05.75#ibcon#read 4, iclass 22, count 0 2006.168.07:20:05.75#ibcon#about to read 5, iclass 22, count 0 2006.168.07:20:05.75#ibcon#read 5, iclass 22, count 0 2006.168.07:20:05.75#ibcon#about to read 6, iclass 22, count 0 2006.168.07:20:05.75#ibcon#read 6, iclass 22, count 0 2006.168.07:20:05.75#ibcon#end of sib2, iclass 22, count 0 2006.168.07:20:05.75#ibcon#*mode == 0, iclass 22, count 0 2006.168.07:20:05.75#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.168.07:20:05.75#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.07:20:05.75#ibcon#*before write, iclass 22, count 0 2006.168.07:20:05.75#ibcon#enter sib2, iclass 22, count 0 2006.168.07:20:05.75#ibcon#flushed, iclass 22, count 0 2006.168.07:20:05.75#ibcon#about to write, iclass 22, count 0 2006.168.07:20:05.75#ibcon#wrote, iclass 22, count 0 2006.168.07:20:05.75#ibcon#about to read 3, iclass 22, count 0 2006.168.07:20:05.79#ibcon#read 3, iclass 22, count 0 2006.168.07:20:05.79#ibcon#about to read 4, iclass 22, count 0 2006.168.07:20:05.79#ibcon#read 4, iclass 22, count 0 2006.168.07:20:05.79#ibcon#about to read 5, iclass 22, count 0 2006.168.07:20:05.79#ibcon#read 5, iclass 22, count 0 2006.168.07:20:05.79#ibcon#about to read 6, iclass 22, count 0 2006.168.07:20:05.79#ibcon#read 6, iclass 22, count 0 2006.168.07:20:05.79#ibcon#end of sib2, iclass 22, count 0 2006.168.07:20:05.79#ibcon#*after write, iclass 22, count 0 2006.168.07:20:05.79#ibcon#*before return 0, iclass 22, count 0 2006.168.07:20:05.79#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:20:05.79#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:20:05.79#ibcon#about to clear, iclass 22 cls_cnt 0 2006.168.07:20:05.79#ibcon#cleared, iclass 22 cls_cnt 0 2006.168.07:20:05.79$vc4f8/va=7,6 2006.168.07:20:05.79#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.168.07:20:05.79#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.168.07:20:05.79#ibcon#ireg 11 cls_cnt 2 2006.168.07:20:05.79#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:20:05.85#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:20:05.85#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:20:05.85#ibcon#enter wrdev, iclass 24, count 2 2006.168.07:20:05.85#ibcon#first serial, iclass 24, count 2 2006.168.07:20:05.85#ibcon#enter sib2, iclass 24, count 2 2006.168.07:20:05.85#ibcon#flushed, iclass 24, count 2 2006.168.07:20:05.85#ibcon#about to write, iclass 24, count 2 2006.168.07:20:05.85#ibcon#wrote, iclass 24, count 2 2006.168.07:20:05.85#ibcon#about to read 3, iclass 24, count 2 2006.168.07:20:05.87#ibcon#read 3, iclass 24, count 2 2006.168.07:20:05.87#ibcon#about to read 4, iclass 24, count 2 2006.168.07:20:05.87#ibcon#read 4, iclass 24, count 2 2006.168.07:20:05.87#ibcon#about to read 5, iclass 24, count 2 2006.168.07:20:05.87#ibcon#read 5, iclass 24, count 2 2006.168.07:20:05.87#ibcon#about to read 6, iclass 24, count 2 2006.168.07:20:05.87#ibcon#read 6, iclass 24, count 2 2006.168.07:20:05.87#ibcon#end of sib2, iclass 24, count 2 2006.168.07:20:05.87#ibcon#*mode == 0, iclass 24, count 2 2006.168.07:20:05.87#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.168.07:20:05.87#ibcon#[25=AT07-06\r\n] 2006.168.07:20:05.87#ibcon#*before write, iclass 24, count 2 2006.168.07:20:05.87#ibcon#enter sib2, iclass 24, count 2 2006.168.07:20:05.87#ibcon#flushed, iclass 24, count 2 2006.168.07:20:05.87#ibcon#about to write, iclass 24, count 2 2006.168.07:20:05.87#ibcon#wrote, iclass 24, count 2 2006.168.07:20:05.87#ibcon#about to read 3, iclass 24, count 2 2006.168.07:20:05.90#ibcon#read 3, iclass 24, count 2 2006.168.07:20:05.90#ibcon#about to read 4, iclass 24, count 2 2006.168.07:20:05.90#ibcon#read 4, iclass 24, count 2 2006.168.07:20:05.90#ibcon#about to read 5, iclass 24, count 2 2006.168.07:20:05.90#ibcon#read 5, iclass 24, count 2 2006.168.07:20:05.90#ibcon#about to read 6, iclass 24, count 2 2006.168.07:20:05.90#ibcon#read 6, iclass 24, count 2 2006.168.07:20:05.90#ibcon#end of sib2, iclass 24, count 2 2006.168.07:20:05.90#ibcon#*after write, iclass 24, count 2 2006.168.07:20:05.90#ibcon#*before return 0, iclass 24, count 2 2006.168.07:20:05.90#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:20:05.90#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:20:05.90#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.168.07:20:05.90#ibcon#ireg 7 cls_cnt 0 2006.168.07:20:05.90#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:20:06.02#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:20:06.02#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:20:06.02#ibcon#enter wrdev, iclass 24, count 0 2006.168.07:20:06.02#ibcon#first serial, iclass 24, count 0 2006.168.07:20:06.02#ibcon#enter sib2, iclass 24, count 0 2006.168.07:20:06.02#ibcon#flushed, iclass 24, count 0 2006.168.07:20:06.02#ibcon#about to write, iclass 24, count 0 2006.168.07:20:06.02#ibcon#wrote, iclass 24, count 0 2006.168.07:20:06.02#ibcon#about to read 3, iclass 24, count 0 2006.168.07:20:06.04#ibcon#read 3, iclass 24, count 0 2006.168.07:20:06.04#ibcon#about to read 4, iclass 24, count 0 2006.168.07:20:06.04#ibcon#read 4, iclass 24, count 0 2006.168.07:20:06.04#ibcon#about to read 5, iclass 24, count 0 2006.168.07:20:06.04#ibcon#read 5, iclass 24, count 0 2006.168.07:20:06.04#ibcon#about to read 6, iclass 24, count 0 2006.168.07:20:06.04#ibcon#read 6, iclass 24, count 0 2006.168.07:20:06.04#ibcon#end of sib2, iclass 24, count 0 2006.168.07:20:06.04#ibcon#*mode == 0, iclass 24, count 0 2006.168.07:20:06.04#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.168.07:20:06.04#ibcon#[25=USB\r\n] 2006.168.07:20:06.04#ibcon#*before write, iclass 24, count 0 2006.168.07:20:06.04#ibcon#enter sib2, iclass 24, count 0 2006.168.07:20:06.04#ibcon#flushed, iclass 24, count 0 2006.168.07:20:06.04#ibcon#about to write, iclass 24, count 0 2006.168.07:20:06.04#ibcon#wrote, iclass 24, count 0 2006.168.07:20:06.04#ibcon#about to read 3, iclass 24, count 0 2006.168.07:20:06.07#ibcon#read 3, iclass 24, count 0 2006.168.07:20:06.07#ibcon#about to read 4, iclass 24, count 0 2006.168.07:20:06.07#ibcon#read 4, iclass 24, count 0 2006.168.07:20:06.07#ibcon#about to read 5, iclass 24, count 0 2006.168.07:20:06.07#ibcon#read 5, iclass 24, count 0 2006.168.07:20:06.07#ibcon#about to read 6, iclass 24, count 0 2006.168.07:20:06.07#ibcon#read 6, iclass 24, count 0 2006.168.07:20:06.07#ibcon#end of sib2, iclass 24, count 0 2006.168.07:20:06.07#ibcon#*after write, iclass 24, count 0 2006.168.07:20:06.07#ibcon#*before return 0, iclass 24, count 0 2006.168.07:20:06.07#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:20:06.07#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:20:06.07#ibcon#about to clear, iclass 24 cls_cnt 0 2006.168.07:20:06.07#ibcon#cleared, iclass 24 cls_cnt 0 2006.168.07:20:06.07$vc4f8/valo=8,852.99 2006.168.07:20:06.07#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.168.07:20:06.07#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.168.07:20:06.07#ibcon#ireg 17 cls_cnt 0 2006.168.07:20:06.07#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:20:06.07#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:20:06.07#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:20:06.07#ibcon#enter wrdev, iclass 26, count 0 2006.168.07:20:06.07#ibcon#first serial, iclass 26, count 0 2006.168.07:20:06.07#ibcon#enter sib2, iclass 26, count 0 2006.168.07:20:06.07#ibcon#flushed, iclass 26, count 0 2006.168.07:20:06.07#ibcon#about to write, iclass 26, count 0 2006.168.07:20:06.07#ibcon#wrote, iclass 26, count 0 2006.168.07:20:06.07#ibcon#about to read 3, iclass 26, count 0 2006.168.07:20:06.09#ibcon#read 3, iclass 26, count 0 2006.168.07:20:06.09#ibcon#about to read 4, iclass 26, count 0 2006.168.07:20:06.09#ibcon#read 4, iclass 26, count 0 2006.168.07:20:06.09#ibcon#about to read 5, iclass 26, count 0 2006.168.07:20:06.09#ibcon#read 5, iclass 26, count 0 2006.168.07:20:06.09#ibcon#about to read 6, iclass 26, count 0 2006.168.07:20:06.09#ibcon#read 6, iclass 26, count 0 2006.168.07:20:06.09#ibcon#end of sib2, iclass 26, count 0 2006.168.07:20:06.09#ibcon#*mode == 0, iclass 26, count 0 2006.168.07:20:06.09#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.168.07:20:06.09#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.07:20:06.09#ibcon#*before write, iclass 26, count 0 2006.168.07:20:06.09#ibcon#enter sib2, iclass 26, count 0 2006.168.07:20:06.09#ibcon#flushed, iclass 26, count 0 2006.168.07:20:06.09#ibcon#about to write, iclass 26, count 0 2006.168.07:20:06.09#ibcon#wrote, iclass 26, count 0 2006.168.07:20:06.09#ibcon#about to read 3, iclass 26, count 0 2006.168.07:20:06.13#ibcon#read 3, iclass 26, count 0 2006.168.07:20:06.13#ibcon#about to read 4, iclass 26, count 0 2006.168.07:20:06.13#ibcon#read 4, iclass 26, count 0 2006.168.07:20:06.13#ibcon#about to read 5, iclass 26, count 0 2006.168.07:20:06.13#ibcon#read 5, iclass 26, count 0 2006.168.07:20:06.13#ibcon#about to read 6, iclass 26, count 0 2006.168.07:20:06.13#ibcon#read 6, iclass 26, count 0 2006.168.07:20:06.13#ibcon#end of sib2, iclass 26, count 0 2006.168.07:20:06.13#ibcon#*after write, iclass 26, count 0 2006.168.07:20:06.13#ibcon#*before return 0, iclass 26, count 0 2006.168.07:20:06.13#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:20:06.13#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:20:06.13#ibcon#about to clear, iclass 26 cls_cnt 0 2006.168.07:20:06.13#ibcon#cleared, iclass 26 cls_cnt 0 2006.168.07:20:06.13$vc4f8/va=8,7 2006.168.07:20:06.13#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.168.07:20:06.13#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.168.07:20:06.13#ibcon#ireg 11 cls_cnt 2 2006.168.07:20:06.13#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.168.07:20:06.19#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.168.07:20:06.19#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.168.07:20:06.19#ibcon#enter wrdev, iclass 28, count 2 2006.168.07:20:06.19#ibcon#first serial, iclass 28, count 2 2006.168.07:20:06.19#ibcon#enter sib2, iclass 28, count 2 2006.168.07:20:06.19#ibcon#flushed, iclass 28, count 2 2006.168.07:20:06.19#ibcon#about to write, iclass 28, count 2 2006.168.07:20:06.19#ibcon#wrote, iclass 28, count 2 2006.168.07:20:06.19#ibcon#about to read 3, iclass 28, count 2 2006.168.07:20:06.21#ibcon#read 3, iclass 28, count 2 2006.168.07:20:06.21#ibcon#about to read 4, iclass 28, count 2 2006.168.07:20:06.21#ibcon#read 4, iclass 28, count 2 2006.168.07:20:06.21#ibcon#about to read 5, iclass 28, count 2 2006.168.07:20:06.21#ibcon#read 5, iclass 28, count 2 2006.168.07:20:06.21#ibcon#about to read 6, iclass 28, count 2 2006.168.07:20:06.21#ibcon#read 6, iclass 28, count 2 2006.168.07:20:06.21#ibcon#end of sib2, iclass 28, count 2 2006.168.07:20:06.21#ibcon#*mode == 0, iclass 28, count 2 2006.168.07:20:06.21#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.168.07:20:06.21#ibcon#[25=AT08-07\r\n] 2006.168.07:20:06.21#ibcon#*before write, iclass 28, count 2 2006.168.07:20:06.21#ibcon#enter sib2, iclass 28, count 2 2006.168.07:20:06.21#ibcon#flushed, iclass 28, count 2 2006.168.07:20:06.21#ibcon#about to write, iclass 28, count 2 2006.168.07:20:06.21#ibcon#wrote, iclass 28, count 2 2006.168.07:20:06.21#ibcon#about to read 3, iclass 28, count 2 2006.168.07:20:06.24#ibcon#read 3, iclass 28, count 2 2006.168.07:20:06.24#ibcon#about to read 4, iclass 28, count 2 2006.168.07:20:06.24#ibcon#read 4, iclass 28, count 2 2006.168.07:20:06.24#ibcon#about to read 5, iclass 28, count 2 2006.168.07:20:06.24#ibcon#read 5, iclass 28, count 2 2006.168.07:20:06.24#ibcon#about to read 6, iclass 28, count 2 2006.168.07:20:06.24#ibcon#read 6, iclass 28, count 2 2006.168.07:20:06.24#ibcon#end of sib2, iclass 28, count 2 2006.168.07:20:06.24#ibcon#*after write, iclass 28, count 2 2006.168.07:20:06.24#ibcon#*before return 0, iclass 28, count 2 2006.168.07:20:06.24#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.168.07:20:06.24#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.168.07:20:06.24#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.168.07:20:06.24#ibcon#ireg 7 cls_cnt 0 2006.168.07:20:06.24#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.168.07:20:06.36#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.168.07:20:06.36#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.168.07:20:06.36#ibcon#enter wrdev, iclass 28, count 0 2006.168.07:20:06.36#ibcon#first serial, iclass 28, count 0 2006.168.07:20:06.36#ibcon#enter sib2, iclass 28, count 0 2006.168.07:20:06.36#ibcon#flushed, iclass 28, count 0 2006.168.07:20:06.36#ibcon#about to write, iclass 28, count 0 2006.168.07:20:06.36#ibcon#wrote, iclass 28, count 0 2006.168.07:20:06.36#ibcon#about to read 3, iclass 28, count 0 2006.168.07:20:06.38#ibcon#read 3, iclass 28, count 0 2006.168.07:20:06.38#ibcon#about to read 4, iclass 28, count 0 2006.168.07:20:06.38#ibcon#read 4, iclass 28, count 0 2006.168.07:20:06.38#ibcon#about to read 5, iclass 28, count 0 2006.168.07:20:06.38#ibcon#read 5, iclass 28, count 0 2006.168.07:20:06.38#ibcon#about to read 6, iclass 28, count 0 2006.168.07:20:06.38#ibcon#read 6, iclass 28, count 0 2006.168.07:20:06.38#ibcon#end of sib2, iclass 28, count 0 2006.168.07:20:06.38#ibcon#*mode == 0, iclass 28, count 0 2006.168.07:20:06.38#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.168.07:20:06.38#ibcon#[25=USB\r\n] 2006.168.07:20:06.38#ibcon#*before write, iclass 28, count 0 2006.168.07:20:06.38#ibcon#enter sib2, iclass 28, count 0 2006.168.07:20:06.38#ibcon#flushed, iclass 28, count 0 2006.168.07:20:06.38#ibcon#about to write, iclass 28, count 0 2006.168.07:20:06.38#ibcon#wrote, iclass 28, count 0 2006.168.07:20:06.38#ibcon#about to read 3, iclass 28, count 0 2006.168.07:20:06.41#ibcon#read 3, iclass 28, count 0 2006.168.07:20:06.41#ibcon#about to read 4, iclass 28, count 0 2006.168.07:20:06.41#ibcon#read 4, iclass 28, count 0 2006.168.07:20:06.41#ibcon#about to read 5, iclass 28, count 0 2006.168.07:20:06.41#ibcon#read 5, iclass 28, count 0 2006.168.07:20:06.41#ibcon#about to read 6, iclass 28, count 0 2006.168.07:20:06.41#ibcon#read 6, iclass 28, count 0 2006.168.07:20:06.41#ibcon#end of sib2, iclass 28, count 0 2006.168.07:20:06.41#ibcon#*after write, iclass 28, count 0 2006.168.07:20:06.41#ibcon#*before return 0, iclass 28, count 0 2006.168.07:20:06.41#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.168.07:20:06.41#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.168.07:20:06.41#ibcon#about to clear, iclass 28 cls_cnt 0 2006.168.07:20:06.41#ibcon#cleared, iclass 28 cls_cnt 0 2006.168.07:20:06.41$vc4f8/vblo=1,632.99 2006.168.07:20:06.41#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.168.07:20:06.41#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.168.07:20:06.41#ibcon#ireg 17 cls_cnt 0 2006.168.07:20:06.41#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:20:06.41#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:20:06.41#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:20:06.41#ibcon#enter wrdev, iclass 30, count 0 2006.168.07:20:06.41#ibcon#first serial, iclass 30, count 0 2006.168.07:20:06.41#ibcon#enter sib2, iclass 30, count 0 2006.168.07:20:06.41#ibcon#flushed, iclass 30, count 0 2006.168.07:20:06.41#ibcon#about to write, iclass 30, count 0 2006.168.07:20:06.41#ibcon#wrote, iclass 30, count 0 2006.168.07:20:06.41#ibcon#about to read 3, iclass 30, count 0 2006.168.07:20:06.43#ibcon#read 3, iclass 30, count 0 2006.168.07:20:06.43#ibcon#about to read 4, iclass 30, count 0 2006.168.07:20:06.43#ibcon#read 4, iclass 30, count 0 2006.168.07:20:06.43#ibcon#about to read 5, iclass 30, count 0 2006.168.07:20:06.43#ibcon#read 5, iclass 30, count 0 2006.168.07:20:06.43#ibcon#about to read 6, iclass 30, count 0 2006.168.07:20:06.43#ibcon#read 6, iclass 30, count 0 2006.168.07:20:06.43#ibcon#end of sib2, iclass 30, count 0 2006.168.07:20:06.43#ibcon#*mode == 0, iclass 30, count 0 2006.168.07:20:06.43#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.168.07:20:06.43#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.07:20:06.43#ibcon#*before write, iclass 30, count 0 2006.168.07:20:06.43#ibcon#enter sib2, iclass 30, count 0 2006.168.07:20:06.43#ibcon#flushed, iclass 30, count 0 2006.168.07:20:06.43#ibcon#about to write, iclass 30, count 0 2006.168.07:20:06.43#ibcon#wrote, iclass 30, count 0 2006.168.07:20:06.43#ibcon#about to read 3, iclass 30, count 0 2006.168.07:20:06.47#ibcon#read 3, iclass 30, count 0 2006.168.07:20:06.47#ibcon#about to read 4, iclass 30, count 0 2006.168.07:20:06.47#ibcon#read 4, iclass 30, count 0 2006.168.07:20:06.47#ibcon#about to read 5, iclass 30, count 0 2006.168.07:20:06.47#ibcon#read 5, iclass 30, count 0 2006.168.07:20:06.47#ibcon#about to read 6, iclass 30, count 0 2006.168.07:20:06.47#ibcon#read 6, iclass 30, count 0 2006.168.07:20:06.47#ibcon#end of sib2, iclass 30, count 0 2006.168.07:20:06.47#ibcon#*after write, iclass 30, count 0 2006.168.07:20:06.47#ibcon#*before return 0, iclass 30, count 0 2006.168.07:20:06.47#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:20:06.47#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:20:06.47#ibcon#about to clear, iclass 30 cls_cnt 0 2006.168.07:20:06.47#ibcon#cleared, iclass 30 cls_cnt 0 2006.168.07:20:06.47$vc4f8/vb=1,4 2006.168.07:20:06.47#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.168.07:20:06.47#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.168.07:20:06.47#ibcon#ireg 11 cls_cnt 2 2006.168.07:20:06.47#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:20:06.47#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:20:06.47#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:20:06.47#ibcon#enter wrdev, iclass 32, count 2 2006.168.07:20:06.47#ibcon#first serial, iclass 32, count 2 2006.168.07:20:06.47#ibcon#enter sib2, iclass 32, count 2 2006.168.07:20:06.47#ibcon#flushed, iclass 32, count 2 2006.168.07:20:06.47#ibcon#about to write, iclass 32, count 2 2006.168.07:20:06.47#ibcon#wrote, iclass 32, count 2 2006.168.07:20:06.47#ibcon#about to read 3, iclass 32, count 2 2006.168.07:20:06.49#ibcon#read 3, iclass 32, count 2 2006.168.07:20:06.49#ibcon#about to read 4, iclass 32, count 2 2006.168.07:20:06.49#ibcon#read 4, iclass 32, count 2 2006.168.07:20:06.49#ibcon#about to read 5, iclass 32, count 2 2006.168.07:20:06.49#ibcon#read 5, iclass 32, count 2 2006.168.07:20:06.49#ibcon#about to read 6, iclass 32, count 2 2006.168.07:20:06.49#ibcon#read 6, iclass 32, count 2 2006.168.07:20:06.49#ibcon#end of sib2, iclass 32, count 2 2006.168.07:20:06.49#ibcon#*mode == 0, iclass 32, count 2 2006.168.07:20:06.49#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.168.07:20:06.49#ibcon#[27=AT01-04\r\n] 2006.168.07:20:06.49#ibcon#*before write, iclass 32, count 2 2006.168.07:20:06.49#ibcon#enter sib2, iclass 32, count 2 2006.168.07:20:06.49#ibcon#flushed, iclass 32, count 2 2006.168.07:20:06.49#ibcon#about to write, iclass 32, count 2 2006.168.07:20:06.49#ibcon#wrote, iclass 32, count 2 2006.168.07:20:06.49#ibcon#about to read 3, iclass 32, count 2 2006.168.07:20:06.52#ibcon#read 3, iclass 32, count 2 2006.168.07:20:06.52#ibcon#about to read 4, iclass 32, count 2 2006.168.07:20:06.52#ibcon#read 4, iclass 32, count 2 2006.168.07:20:06.52#ibcon#about to read 5, iclass 32, count 2 2006.168.07:20:06.52#ibcon#read 5, iclass 32, count 2 2006.168.07:20:06.52#ibcon#about to read 6, iclass 32, count 2 2006.168.07:20:06.52#ibcon#read 6, iclass 32, count 2 2006.168.07:20:06.52#ibcon#end of sib2, iclass 32, count 2 2006.168.07:20:06.52#ibcon#*after write, iclass 32, count 2 2006.168.07:20:06.52#ibcon#*before return 0, iclass 32, count 2 2006.168.07:20:06.52#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:20:06.52#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:20:06.52#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.168.07:20:06.52#ibcon#ireg 7 cls_cnt 0 2006.168.07:20:06.52#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:20:06.64#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:20:06.64#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:20:06.64#ibcon#enter wrdev, iclass 32, count 0 2006.168.07:20:06.64#ibcon#first serial, iclass 32, count 0 2006.168.07:20:06.64#ibcon#enter sib2, iclass 32, count 0 2006.168.07:20:06.64#ibcon#flushed, iclass 32, count 0 2006.168.07:20:06.64#ibcon#about to write, iclass 32, count 0 2006.168.07:20:06.64#ibcon#wrote, iclass 32, count 0 2006.168.07:20:06.64#ibcon#about to read 3, iclass 32, count 0 2006.168.07:20:06.66#ibcon#read 3, iclass 32, count 0 2006.168.07:20:06.66#ibcon#about to read 4, iclass 32, count 0 2006.168.07:20:06.66#ibcon#read 4, iclass 32, count 0 2006.168.07:20:06.66#ibcon#about to read 5, iclass 32, count 0 2006.168.07:20:06.66#ibcon#read 5, iclass 32, count 0 2006.168.07:20:06.66#ibcon#about to read 6, iclass 32, count 0 2006.168.07:20:06.66#ibcon#read 6, iclass 32, count 0 2006.168.07:20:06.66#ibcon#end of sib2, iclass 32, count 0 2006.168.07:20:06.66#ibcon#*mode == 0, iclass 32, count 0 2006.168.07:20:06.66#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.168.07:20:06.66#ibcon#[27=USB\r\n] 2006.168.07:20:06.66#ibcon#*before write, iclass 32, count 0 2006.168.07:20:06.66#ibcon#enter sib2, iclass 32, count 0 2006.168.07:20:06.66#ibcon#flushed, iclass 32, count 0 2006.168.07:20:06.66#ibcon#about to write, iclass 32, count 0 2006.168.07:20:06.66#ibcon#wrote, iclass 32, count 0 2006.168.07:20:06.66#ibcon#about to read 3, iclass 32, count 0 2006.168.07:20:06.69#ibcon#read 3, iclass 32, count 0 2006.168.07:20:06.69#ibcon#about to read 4, iclass 32, count 0 2006.168.07:20:06.69#ibcon#read 4, iclass 32, count 0 2006.168.07:20:06.69#ibcon#about to read 5, iclass 32, count 0 2006.168.07:20:06.69#ibcon#read 5, iclass 32, count 0 2006.168.07:20:06.69#ibcon#about to read 6, iclass 32, count 0 2006.168.07:20:06.69#ibcon#read 6, iclass 32, count 0 2006.168.07:20:06.69#ibcon#end of sib2, iclass 32, count 0 2006.168.07:20:06.69#ibcon#*after write, iclass 32, count 0 2006.168.07:20:06.69#ibcon#*before return 0, iclass 32, count 0 2006.168.07:20:06.69#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:20:06.69#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:20:06.69#ibcon#about to clear, iclass 32 cls_cnt 0 2006.168.07:20:06.69#ibcon#cleared, iclass 32 cls_cnt 0 2006.168.07:20:06.69$vc4f8/vblo=2,640.99 2006.168.07:20:06.69#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.168.07:20:06.69#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.168.07:20:06.69#ibcon#ireg 17 cls_cnt 0 2006.168.07:20:06.69#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:20:06.69#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:20:06.69#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:20:06.69#ibcon#enter wrdev, iclass 34, count 0 2006.168.07:20:06.69#ibcon#first serial, iclass 34, count 0 2006.168.07:20:06.69#ibcon#enter sib2, iclass 34, count 0 2006.168.07:20:06.69#ibcon#flushed, iclass 34, count 0 2006.168.07:20:06.69#ibcon#about to write, iclass 34, count 0 2006.168.07:20:06.69#ibcon#wrote, iclass 34, count 0 2006.168.07:20:06.69#ibcon#about to read 3, iclass 34, count 0 2006.168.07:20:06.71#ibcon#read 3, iclass 34, count 0 2006.168.07:20:06.71#ibcon#about to read 4, iclass 34, count 0 2006.168.07:20:06.71#ibcon#read 4, iclass 34, count 0 2006.168.07:20:06.71#ibcon#about to read 5, iclass 34, count 0 2006.168.07:20:06.71#ibcon#read 5, iclass 34, count 0 2006.168.07:20:06.71#ibcon#about to read 6, iclass 34, count 0 2006.168.07:20:06.71#ibcon#read 6, iclass 34, count 0 2006.168.07:20:06.71#ibcon#end of sib2, iclass 34, count 0 2006.168.07:20:06.71#ibcon#*mode == 0, iclass 34, count 0 2006.168.07:20:06.71#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.168.07:20:06.71#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.07:20:06.71#ibcon#*before write, iclass 34, count 0 2006.168.07:20:06.71#ibcon#enter sib2, iclass 34, count 0 2006.168.07:20:06.71#ibcon#flushed, iclass 34, count 0 2006.168.07:20:06.71#ibcon#about to write, iclass 34, count 0 2006.168.07:20:06.71#ibcon#wrote, iclass 34, count 0 2006.168.07:20:06.71#ibcon#about to read 3, iclass 34, count 0 2006.168.07:20:06.75#ibcon#read 3, iclass 34, count 0 2006.168.07:20:06.75#ibcon#about to read 4, iclass 34, count 0 2006.168.07:20:06.75#ibcon#read 4, iclass 34, count 0 2006.168.07:20:06.75#ibcon#about to read 5, iclass 34, count 0 2006.168.07:20:06.75#ibcon#read 5, iclass 34, count 0 2006.168.07:20:06.75#ibcon#about to read 6, iclass 34, count 0 2006.168.07:20:06.75#ibcon#read 6, iclass 34, count 0 2006.168.07:20:06.75#ibcon#end of sib2, iclass 34, count 0 2006.168.07:20:06.75#ibcon#*after write, iclass 34, count 0 2006.168.07:20:06.75#ibcon#*before return 0, iclass 34, count 0 2006.168.07:20:06.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:20:06.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:20:06.75#ibcon#about to clear, iclass 34 cls_cnt 0 2006.168.07:20:06.75#ibcon#cleared, iclass 34 cls_cnt 0 2006.168.07:20:06.75$vc4f8/vb=2,4 2006.168.07:20:06.75#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.168.07:20:06.75#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.168.07:20:06.75#ibcon#ireg 11 cls_cnt 2 2006.168.07:20:06.75#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:20:06.81#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:20:06.81#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:20:06.81#ibcon#enter wrdev, iclass 36, count 2 2006.168.07:20:06.81#ibcon#first serial, iclass 36, count 2 2006.168.07:20:06.81#ibcon#enter sib2, iclass 36, count 2 2006.168.07:20:06.81#ibcon#flushed, iclass 36, count 2 2006.168.07:20:06.81#ibcon#about to write, iclass 36, count 2 2006.168.07:20:06.81#ibcon#wrote, iclass 36, count 2 2006.168.07:20:06.81#ibcon#about to read 3, iclass 36, count 2 2006.168.07:20:06.83#ibcon#read 3, iclass 36, count 2 2006.168.07:20:06.83#ibcon#about to read 4, iclass 36, count 2 2006.168.07:20:06.83#ibcon#read 4, iclass 36, count 2 2006.168.07:20:06.83#ibcon#about to read 5, iclass 36, count 2 2006.168.07:20:06.83#ibcon#read 5, iclass 36, count 2 2006.168.07:20:06.83#ibcon#about to read 6, iclass 36, count 2 2006.168.07:20:06.83#ibcon#read 6, iclass 36, count 2 2006.168.07:20:06.83#ibcon#end of sib2, iclass 36, count 2 2006.168.07:20:06.83#ibcon#*mode == 0, iclass 36, count 2 2006.168.07:20:06.83#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.168.07:20:06.83#ibcon#[27=AT02-04\r\n] 2006.168.07:20:06.83#ibcon#*before write, iclass 36, count 2 2006.168.07:20:06.83#ibcon#enter sib2, iclass 36, count 2 2006.168.07:20:06.83#ibcon#flushed, iclass 36, count 2 2006.168.07:20:06.83#ibcon#about to write, iclass 36, count 2 2006.168.07:20:06.83#ibcon#wrote, iclass 36, count 2 2006.168.07:20:06.83#ibcon#about to read 3, iclass 36, count 2 2006.168.07:20:06.86#ibcon#read 3, iclass 36, count 2 2006.168.07:20:06.86#ibcon#about to read 4, iclass 36, count 2 2006.168.07:20:06.86#ibcon#read 4, iclass 36, count 2 2006.168.07:20:06.86#ibcon#about to read 5, iclass 36, count 2 2006.168.07:20:06.86#ibcon#read 5, iclass 36, count 2 2006.168.07:20:06.86#ibcon#about to read 6, iclass 36, count 2 2006.168.07:20:06.86#ibcon#read 6, iclass 36, count 2 2006.168.07:20:06.86#ibcon#end of sib2, iclass 36, count 2 2006.168.07:20:06.86#ibcon#*after write, iclass 36, count 2 2006.168.07:20:06.86#ibcon#*before return 0, iclass 36, count 2 2006.168.07:20:06.86#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:20:06.86#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:20:06.86#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.168.07:20:06.86#ibcon#ireg 7 cls_cnt 0 2006.168.07:20:06.86#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:20:06.98#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:20:06.98#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:20:06.98#ibcon#enter wrdev, iclass 36, count 0 2006.168.07:20:06.98#ibcon#first serial, iclass 36, count 0 2006.168.07:20:06.98#ibcon#enter sib2, iclass 36, count 0 2006.168.07:20:06.98#ibcon#flushed, iclass 36, count 0 2006.168.07:20:06.98#ibcon#about to write, iclass 36, count 0 2006.168.07:20:06.98#ibcon#wrote, iclass 36, count 0 2006.168.07:20:06.98#ibcon#about to read 3, iclass 36, count 0 2006.168.07:20:07.00#ibcon#read 3, iclass 36, count 0 2006.168.07:20:07.00#ibcon#about to read 4, iclass 36, count 0 2006.168.07:20:07.00#ibcon#read 4, iclass 36, count 0 2006.168.07:20:07.00#ibcon#about to read 5, iclass 36, count 0 2006.168.07:20:07.00#ibcon#read 5, iclass 36, count 0 2006.168.07:20:07.00#ibcon#about to read 6, iclass 36, count 0 2006.168.07:20:07.00#ibcon#read 6, iclass 36, count 0 2006.168.07:20:07.00#ibcon#end of sib2, iclass 36, count 0 2006.168.07:20:07.00#ibcon#*mode == 0, iclass 36, count 0 2006.168.07:20:07.00#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.168.07:20:07.00#ibcon#[27=USB\r\n] 2006.168.07:20:07.00#ibcon#*before write, iclass 36, count 0 2006.168.07:20:07.00#ibcon#enter sib2, iclass 36, count 0 2006.168.07:20:07.00#ibcon#flushed, iclass 36, count 0 2006.168.07:20:07.00#ibcon#about to write, iclass 36, count 0 2006.168.07:20:07.00#ibcon#wrote, iclass 36, count 0 2006.168.07:20:07.00#ibcon#about to read 3, iclass 36, count 0 2006.168.07:20:07.03#ibcon#read 3, iclass 36, count 0 2006.168.07:20:07.03#ibcon#about to read 4, iclass 36, count 0 2006.168.07:20:07.03#ibcon#read 4, iclass 36, count 0 2006.168.07:20:07.03#ibcon#about to read 5, iclass 36, count 0 2006.168.07:20:07.03#ibcon#read 5, iclass 36, count 0 2006.168.07:20:07.03#ibcon#about to read 6, iclass 36, count 0 2006.168.07:20:07.03#ibcon#read 6, iclass 36, count 0 2006.168.07:20:07.03#ibcon#end of sib2, iclass 36, count 0 2006.168.07:20:07.03#ibcon#*after write, iclass 36, count 0 2006.168.07:20:07.03#ibcon#*before return 0, iclass 36, count 0 2006.168.07:20:07.03#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:20:07.03#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:20:07.03#ibcon#about to clear, iclass 36 cls_cnt 0 2006.168.07:20:07.03#ibcon#cleared, iclass 36 cls_cnt 0 2006.168.07:20:07.03$vc4f8/vblo=3,656.99 2006.168.07:20:07.03#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.168.07:20:07.03#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.168.07:20:07.03#ibcon#ireg 17 cls_cnt 0 2006.168.07:20:07.03#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:20:07.03#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:20:07.03#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:20:07.03#ibcon#enter wrdev, iclass 38, count 0 2006.168.07:20:07.03#ibcon#first serial, iclass 38, count 0 2006.168.07:20:07.03#ibcon#enter sib2, iclass 38, count 0 2006.168.07:20:07.03#ibcon#flushed, iclass 38, count 0 2006.168.07:20:07.03#ibcon#about to write, iclass 38, count 0 2006.168.07:20:07.03#ibcon#wrote, iclass 38, count 0 2006.168.07:20:07.03#ibcon#about to read 3, iclass 38, count 0 2006.168.07:20:07.05#ibcon#read 3, iclass 38, count 0 2006.168.07:20:07.05#ibcon#about to read 4, iclass 38, count 0 2006.168.07:20:07.05#ibcon#read 4, iclass 38, count 0 2006.168.07:20:07.05#ibcon#about to read 5, iclass 38, count 0 2006.168.07:20:07.05#ibcon#read 5, iclass 38, count 0 2006.168.07:20:07.05#ibcon#about to read 6, iclass 38, count 0 2006.168.07:20:07.05#ibcon#read 6, iclass 38, count 0 2006.168.07:20:07.05#ibcon#end of sib2, iclass 38, count 0 2006.168.07:20:07.05#ibcon#*mode == 0, iclass 38, count 0 2006.168.07:20:07.05#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.168.07:20:07.05#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.07:20:07.05#ibcon#*before write, iclass 38, count 0 2006.168.07:20:07.05#ibcon#enter sib2, iclass 38, count 0 2006.168.07:20:07.05#ibcon#flushed, iclass 38, count 0 2006.168.07:20:07.05#ibcon#about to write, iclass 38, count 0 2006.168.07:20:07.05#ibcon#wrote, iclass 38, count 0 2006.168.07:20:07.05#ibcon#about to read 3, iclass 38, count 0 2006.168.07:20:07.09#ibcon#read 3, iclass 38, count 0 2006.168.07:20:07.09#ibcon#about to read 4, iclass 38, count 0 2006.168.07:20:07.09#ibcon#read 4, iclass 38, count 0 2006.168.07:20:07.09#ibcon#about to read 5, iclass 38, count 0 2006.168.07:20:07.09#ibcon#read 5, iclass 38, count 0 2006.168.07:20:07.09#ibcon#about to read 6, iclass 38, count 0 2006.168.07:20:07.09#ibcon#read 6, iclass 38, count 0 2006.168.07:20:07.09#ibcon#end of sib2, iclass 38, count 0 2006.168.07:20:07.09#ibcon#*after write, iclass 38, count 0 2006.168.07:20:07.09#ibcon#*before return 0, iclass 38, count 0 2006.168.07:20:07.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:20:07.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:20:07.09#ibcon#about to clear, iclass 38 cls_cnt 0 2006.168.07:20:07.09#ibcon#cleared, iclass 38 cls_cnt 0 2006.168.07:20:07.09$vc4f8/vb=3,4 2006.168.07:20:07.09#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.168.07:20:07.09#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.168.07:20:07.09#ibcon#ireg 11 cls_cnt 2 2006.168.07:20:07.09#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:20:07.15#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:20:07.15#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:20:07.15#ibcon#enter wrdev, iclass 40, count 2 2006.168.07:20:07.15#ibcon#first serial, iclass 40, count 2 2006.168.07:20:07.15#ibcon#enter sib2, iclass 40, count 2 2006.168.07:20:07.15#ibcon#flushed, iclass 40, count 2 2006.168.07:20:07.15#ibcon#about to write, iclass 40, count 2 2006.168.07:20:07.15#ibcon#wrote, iclass 40, count 2 2006.168.07:20:07.15#ibcon#about to read 3, iclass 40, count 2 2006.168.07:20:07.17#ibcon#read 3, iclass 40, count 2 2006.168.07:20:07.17#ibcon#about to read 4, iclass 40, count 2 2006.168.07:20:07.17#ibcon#read 4, iclass 40, count 2 2006.168.07:20:07.17#ibcon#about to read 5, iclass 40, count 2 2006.168.07:20:07.17#ibcon#read 5, iclass 40, count 2 2006.168.07:20:07.17#ibcon#about to read 6, iclass 40, count 2 2006.168.07:20:07.17#ibcon#read 6, iclass 40, count 2 2006.168.07:20:07.17#ibcon#end of sib2, iclass 40, count 2 2006.168.07:20:07.17#ibcon#*mode == 0, iclass 40, count 2 2006.168.07:20:07.17#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.168.07:20:07.17#ibcon#[27=AT03-04\r\n] 2006.168.07:20:07.17#ibcon#*before write, iclass 40, count 2 2006.168.07:20:07.17#ibcon#enter sib2, iclass 40, count 2 2006.168.07:20:07.17#ibcon#flushed, iclass 40, count 2 2006.168.07:20:07.17#ibcon#about to write, iclass 40, count 2 2006.168.07:20:07.17#ibcon#wrote, iclass 40, count 2 2006.168.07:20:07.17#ibcon#about to read 3, iclass 40, count 2 2006.168.07:20:07.20#ibcon#read 3, iclass 40, count 2 2006.168.07:20:07.20#ibcon#about to read 4, iclass 40, count 2 2006.168.07:20:07.20#ibcon#read 4, iclass 40, count 2 2006.168.07:20:07.20#ibcon#about to read 5, iclass 40, count 2 2006.168.07:20:07.20#ibcon#read 5, iclass 40, count 2 2006.168.07:20:07.20#ibcon#about to read 6, iclass 40, count 2 2006.168.07:20:07.20#ibcon#read 6, iclass 40, count 2 2006.168.07:20:07.20#ibcon#end of sib2, iclass 40, count 2 2006.168.07:20:07.20#ibcon#*after write, iclass 40, count 2 2006.168.07:20:07.20#ibcon#*before return 0, iclass 40, count 2 2006.168.07:20:07.20#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:20:07.20#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:20:07.20#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.168.07:20:07.20#ibcon#ireg 7 cls_cnt 0 2006.168.07:20:07.20#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:20:07.32#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:20:07.32#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:20:07.32#ibcon#enter wrdev, iclass 40, count 0 2006.168.07:20:07.32#ibcon#first serial, iclass 40, count 0 2006.168.07:20:07.32#ibcon#enter sib2, iclass 40, count 0 2006.168.07:20:07.32#ibcon#flushed, iclass 40, count 0 2006.168.07:20:07.32#ibcon#about to write, iclass 40, count 0 2006.168.07:20:07.32#ibcon#wrote, iclass 40, count 0 2006.168.07:20:07.32#ibcon#about to read 3, iclass 40, count 0 2006.168.07:20:07.34#ibcon#read 3, iclass 40, count 0 2006.168.07:20:07.34#ibcon#about to read 4, iclass 40, count 0 2006.168.07:20:07.34#ibcon#read 4, iclass 40, count 0 2006.168.07:20:07.34#ibcon#about to read 5, iclass 40, count 0 2006.168.07:20:07.34#ibcon#read 5, iclass 40, count 0 2006.168.07:20:07.34#ibcon#about to read 6, iclass 40, count 0 2006.168.07:20:07.34#ibcon#read 6, iclass 40, count 0 2006.168.07:20:07.34#ibcon#end of sib2, iclass 40, count 0 2006.168.07:20:07.34#ibcon#*mode == 0, iclass 40, count 0 2006.168.07:20:07.34#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.168.07:20:07.34#ibcon#[27=USB\r\n] 2006.168.07:20:07.34#ibcon#*before write, iclass 40, count 0 2006.168.07:20:07.34#ibcon#enter sib2, iclass 40, count 0 2006.168.07:20:07.34#ibcon#flushed, iclass 40, count 0 2006.168.07:20:07.34#ibcon#about to write, iclass 40, count 0 2006.168.07:20:07.34#ibcon#wrote, iclass 40, count 0 2006.168.07:20:07.34#ibcon#about to read 3, iclass 40, count 0 2006.168.07:20:07.37#ibcon#read 3, iclass 40, count 0 2006.168.07:20:07.37#ibcon#about to read 4, iclass 40, count 0 2006.168.07:20:07.37#ibcon#read 4, iclass 40, count 0 2006.168.07:20:07.37#ibcon#about to read 5, iclass 40, count 0 2006.168.07:20:07.37#ibcon#read 5, iclass 40, count 0 2006.168.07:20:07.37#ibcon#about to read 6, iclass 40, count 0 2006.168.07:20:07.37#ibcon#read 6, iclass 40, count 0 2006.168.07:20:07.37#ibcon#end of sib2, iclass 40, count 0 2006.168.07:20:07.37#ibcon#*after write, iclass 40, count 0 2006.168.07:20:07.37#ibcon#*before return 0, iclass 40, count 0 2006.168.07:20:07.37#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:20:07.37#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:20:07.37#ibcon#about to clear, iclass 40 cls_cnt 0 2006.168.07:20:07.37#ibcon#cleared, iclass 40 cls_cnt 0 2006.168.07:20:07.37$vc4f8/vblo=4,712.99 2006.168.07:20:07.37#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.168.07:20:07.37#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.168.07:20:07.37#ibcon#ireg 17 cls_cnt 0 2006.168.07:20:07.37#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:20:07.37#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:20:07.37#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:20:07.37#ibcon#enter wrdev, iclass 4, count 0 2006.168.07:20:07.37#ibcon#first serial, iclass 4, count 0 2006.168.07:20:07.37#ibcon#enter sib2, iclass 4, count 0 2006.168.07:20:07.37#ibcon#flushed, iclass 4, count 0 2006.168.07:20:07.37#ibcon#about to write, iclass 4, count 0 2006.168.07:20:07.37#ibcon#wrote, iclass 4, count 0 2006.168.07:20:07.37#ibcon#about to read 3, iclass 4, count 0 2006.168.07:20:07.39#ibcon#read 3, iclass 4, count 0 2006.168.07:20:07.39#ibcon#about to read 4, iclass 4, count 0 2006.168.07:20:07.39#ibcon#read 4, iclass 4, count 0 2006.168.07:20:07.39#ibcon#about to read 5, iclass 4, count 0 2006.168.07:20:07.39#ibcon#read 5, iclass 4, count 0 2006.168.07:20:07.39#ibcon#about to read 6, iclass 4, count 0 2006.168.07:20:07.39#ibcon#read 6, iclass 4, count 0 2006.168.07:20:07.39#ibcon#end of sib2, iclass 4, count 0 2006.168.07:20:07.39#ibcon#*mode == 0, iclass 4, count 0 2006.168.07:20:07.39#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.168.07:20:07.39#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.07:20:07.39#ibcon#*before write, iclass 4, count 0 2006.168.07:20:07.39#ibcon#enter sib2, iclass 4, count 0 2006.168.07:20:07.39#ibcon#flushed, iclass 4, count 0 2006.168.07:20:07.39#ibcon#about to write, iclass 4, count 0 2006.168.07:20:07.39#ibcon#wrote, iclass 4, count 0 2006.168.07:20:07.39#ibcon#about to read 3, iclass 4, count 0 2006.168.07:20:07.43#ibcon#read 3, iclass 4, count 0 2006.168.07:20:07.43#ibcon#about to read 4, iclass 4, count 0 2006.168.07:20:07.43#ibcon#read 4, iclass 4, count 0 2006.168.07:20:07.43#ibcon#about to read 5, iclass 4, count 0 2006.168.07:20:07.43#ibcon#read 5, iclass 4, count 0 2006.168.07:20:07.43#ibcon#about to read 6, iclass 4, count 0 2006.168.07:20:07.43#ibcon#read 6, iclass 4, count 0 2006.168.07:20:07.43#ibcon#end of sib2, iclass 4, count 0 2006.168.07:20:07.43#ibcon#*after write, iclass 4, count 0 2006.168.07:20:07.43#ibcon#*before return 0, iclass 4, count 0 2006.168.07:20:07.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:20:07.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:20:07.43#ibcon#about to clear, iclass 4 cls_cnt 0 2006.168.07:20:07.43#ibcon#cleared, iclass 4 cls_cnt 0 2006.168.07:20:07.43$vc4f8/vb=4,4 2006.168.07:20:07.43#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.168.07:20:07.43#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.168.07:20:07.43#ibcon#ireg 11 cls_cnt 2 2006.168.07:20:07.43#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:20:07.49#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:20:07.49#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:20:07.49#ibcon#enter wrdev, iclass 6, count 2 2006.168.07:20:07.49#ibcon#first serial, iclass 6, count 2 2006.168.07:20:07.49#ibcon#enter sib2, iclass 6, count 2 2006.168.07:20:07.49#ibcon#flushed, iclass 6, count 2 2006.168.07:20:07.49#ibcon#about to write, iclass 6, count 2 2006.168.07:20:07.49#ibcon#wrote, iclass 6, count 2 2006.168.07:20:07.49#ibcon#about to read 3, iclass 6, count 2 2006.168.07:20:07.51#ibcon#read 3, iclass 6, count 2 2006.168.07:20:07.51#ibcon#about to read 4, iclass 6, count 2 2006.168.07:20:07.51#ibcon#read 4, iclass 6, count 2 2006.168.07:20:07.51#ibcon#about to read 5, iclass 6, count 2 2006.168.07:20:07.51#ibcon#read 5, iclass 6, count 2 2006.168.07:20:07.51#ibcon#about to read 6, iclass 6, count 2 2006.168.07:20:07.51#ibcon#read 6, iclass 6, count 2 2006.168.07:20:07.51#ibcon#end of sib2, iclass 6, count 2 2006.168.07:20:07.51#ibcon#*mode == 0, iclass 6, count 2 2006.168.07:20:07.51#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.168.07:20:07.51#ibcon#[27=AT04-04\r\n] 2006.168.07:20:07.51#ibcon#*before write, iclass 6, count 2 2006.168.07:20:07.51#ibcon#enter sib2, iclass 6, count 2 2006.168.07:20:07.51#ibcon#flushed, iclass 6, count 2 2006.168.07:20:07.51#ibcon#about to write, iclass 6, count 2 2006.168.07:20:07.51#ibcon#wrote, iclass 6, count 2 2006.168.07:20:07.51#ibcon#about to read 3, iclass 6, count 2 2006.168.07:20:07.54#ibcon#read 3, iclass 6, count 2 2006.168.07:20:07.54#ibcon#about to read 4, iclass 6, count 2 2006.168.07:20:07.54#ibcon#read 4, iclass 6, count 2 2006.168.07:20:07.54#ibcon#about to read 5, iclass 6, count 2 2006.168.07:20:07.54#ibcon#read 5, iclass 6, count 2 2006.168.07:20:07.54#ibcon#about to read 6, iclass 6, count 2 2006.168.07:20:07.54#ibcon#read 6, iclass 6, count 2 2006.168.07:20:07.54#ibcon#end of sib2, iclass 6, count 2 2006.168.07:20:07.54#ibcon#*after write, iclass 6, count 2 2006.168.07:20:07.54#ibcon#*before return 0, iclass 6, count 2 2006.168.07:20:07.54#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:20:07.54#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:20:07.54#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.168.07:20:07.54#ibcon#ireg 7 cls_cnt 0 2006.168.07:20:07.54#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:20:07.66#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:20:07.66#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:20:07.66#ibcon#enter wrdev, iclass 6, count 0 2006.168.07:20:07.66#ibcon#first serial, iclass 6, count 0 2006.168.07:20:07.66#ibcon#enter sib2, iclass 6, count 0 2006.168.07:20:07.66#ibcon#flushed, iclass 6, count 0 2006.168.07:20:07.66#ibcon#about to write, iclass 6, count 0 2006.168.07:20:07.66#ibcon#wrote, iclass 6, count 0 2006.168.07:20:07.66#ibcon#about to read 3, iclass 6, count 0 2006.168.07:20:07.68#ibcon#read 3, iclass 6, count 0 2006.168.07:20:07.68#ibcon#about to read 4, iclass 6, count 0 2006.168.07:20:07.68#ibcon#read 4, iclass 6, count 0 2006.168.07:20:07.68#ibcon#about to read 5, iclass 6, count 0 2006.168.07:20:07.68#ibcon#read 5, iclass 6, count 0 2006.168.07:20:07.68#ibcon#about to read 6, iclass 6, count 0 2006.168.07:20:07.68#ibcon#read 6, iclass 6, count 0 2006.168.07:20:07.68#ibcon#end of sib2, iclass 6, count 0 2006.168.07:20:07.68#ibcon#*mode == 0, iclass 6, count 0 2006.168.07:20:07.68#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.168.07:20:07.68#ibcon#[27=USB\r\n] 2006.168.07:20:07.68#ibcon#*before write, iclass 6, count 0 2006.168.07:20:07.68#ibcon#enter sib2, iclass 6, count 0 2006.168.07:20:07.68#ibcon#flushed, iclass 6, count 0 2006.168.07:20:07.68#ibcon#about to write, iclass 6, count 0 2006.168.07:20:07.68#ibcon#wrote, iclass 6, count 0 2006.168.07:20:07.68#ibcon#about to read 3, iclass 6, count 0 2006.168.07:20:07.71#ibcon#read 3, iclass 6, count 0 2006.168.07:20:07.71#ibcon#about to read 4, iclass 6, count 0 2006.168.07:20:07.71#ibcon#read 4, iclass 6, count 0 2006.168.07:20:07.71#ibcon#about to read 5, iclass 6, count 0 2006.168.07:20:07.71#ibcon#read 5, iclass 6, count 0 2006.168.07:20:07.71#ibcon#about to read 6, iclass 6, count 0 2006.168.07:20:07.71#ibcon#read 6, iclass 6, count 0 2006.168.07:20:07.71#ibcon#end of sib2, iclass 6, count 0 2006.168.07:20:07.71#ibcon#*after write, iclass 6, count 0 2006.168.07:20:07.71#ibcon#*before return 0, iclass 6, count 0 2006.168.07:20:07.71#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:20:07.71#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:20:07.71#ibcon#about to clear, iclass 6 cls_cnt 0 2006.168.07:20:07.71#ibcon#cleared, iclass 6 cls_cnt 0 2006.168.07:20:07.71$vc4f8/vblo=5,744.99 2006.168.07:20:07.71#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.168.07:20:07.71#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.168.07:20:07.71#ibcon#ireg 17 cls_cnt 0 2006.168.07:20:07.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:20:07.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:20:07.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:20:07.71#ibcon#enter wrdev, iclass 10, count 0 2006.168.07:20:07.71#ibcon#first serial, iclass 10, count 0 2006.168.07:20:07.71#ibcon#enter sib2, iclass 10, count 0 2006.168.07:20:07.71#ibcon#flushed, iclass 10, count 0 2006.168.07:20:07.71#ibcon#about to write, iclass 10, count 0 2006.168.07:20:07.71#ibcon#wrote, iclass 10, count 0 2006.168.07:20:07.71#ibcon#about to read 3, iclass 10, count 0 2006.168.07:20:07.73#ibcon#read 3, iclass 10, count 0 2006.168.07:20:07.73#ibcon#about to read 4, iclass 10, count 0 2006.168.07:20:07.73#ibcon#read 4, iclass 10, count 0 2006.168.07:20:07.73#ibcon#about to read 5, iclass 10, count 0 2006.168.07:20:07.73#ibcon#read 5, iclass 10, count 0 2006.168.07:20:07.73#ibcon#about to read 6, iclass 10, count 0 2006.168.07:20:07.73#ibcon#read 6, iclass 10, count 0 2006.168.07:20:07.73#ibcon#end of sib2, iclass 10, count 0 2006.168.07:20:07.73#ibcon#*mode == 0, iclass 10, count 0 2006.168.07:20:07.73#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.168.07:20:07.73#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.07:20:07.73#ibcon#*before write, iclass 10, count 0 2006.168.07:20:07.73#ibcon#enter sib2, iclass 10, count 0 2006.168.07:20:07.73#ibcon#flushed, iclass 10, count 0 2006.168.07:20:07.73#ibcon#about to write, iclass 10, count 0 2006.168.07:20:07.73#ibcon#wrote, iclass 10, count 0 2006.168.07:20:07.73#ibcon#about to read 3, iclass 10, count 0 2006.168.07:20:07.77#ibcon#read 3, iclass 10, count 0 2006.168.07:20:07.77#ibcon#about to read 4, iclass 10, count 0 2006.168.07:20:07.77#ibcon#read 4, iclass 10, count 0 2006.168.07:20:07.77#ibcon#about to read 5, iclass 10, count 0 2006.168.07:20:07.77#ibcon#read 5, iclass 10, count 0 2006.168.07:20:07.77#ibcon#about to read 6, iclass 10, count 0 2006.168.07:20:07.77#ibcon#read 6, iclass 10, count 0 2006.168.07:20:07.77#ibcon#end of sib2, iclass 10, count 0 2006.168.07:20:07.77#ibcon#*after write, iclass 10, count 0 2006.168.07:20:07.77#ibcon#*before return 0, iclass 10, count 0 2006.168.07:20:07.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:20:07.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:20:07.77#ibcon#about to clear, iclass 10 cls_cnt 0 2006.168.07:20:07.77#ibcon#cleared, iclass 10 cls_cnt 0 2006.168.07:20:07.77$vc4f8/vb=5,4 2006.168.07:20:07.77#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.168.07:20:07.77#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.168.07:20:07.77#ibcon#ireg 11 cls_cnt 2 2006.168.07:20:07.77#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:20:07.83#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:20:07.83#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:20:07.83#ibcon#enter wrdev, iclass 12, count 2 2006.168.07:20:07.83#ibcon#first serial, iclass 12, count 2 2006.168.07:20:07.83#ibcon#enter sib2, iclass 12, count 2 2006.168.07:20:07.83#ibcon#flushed, iclass 12, count 2 2006.168.07:20:07.83#ibcon#about to write, iclass 12, count 2 2006.168.07:20:07.83#ibcon#wrote, iclass 12, count 2 2006.168.07:20:07.83#ibcon#about to read 3, iclass 12, count 2 2006.168.07:20:07.85#ibcon#read 3, iclass 12, count 2 2006.168.07:20:07.85#ibcon#about to read 4, iclass 12, count 2 2006.168.07:20:07.85#ibcon#read 4, iclass 12, count 2 2006.168.07:20:07.85#ibcon#about to read 5, iclass 12, count 2 2006.168.07:20:07.85#ibcon#read 5, iclass 12, count 2 2006.168.07:20:07.85#ibcon#about to read 6, iclass 12, count 2 2006.168.07:20:07.85#ibcon#read 6, iclass 12, count 2 2006.168.07:20:07.85#ibcon#end of sib2, iclass 12, count 2 2006.168.07:20:07.85#ibcon#*mode == 0, iclass 12, count 2 2006.168.07:20:07.85#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.168.07:20:07.85#ibcon#[27=AT05-04\r\n] 2006.168.07:20:07.85#ibcon#*before write, iclass 12, count 2 2006.168.07:20:07.85#ibcon#enter sib2, iclass 12, count 2 2006.168.07:20:07.85#ibcon#flushed, iclass 12, count 2 2006.168.07:20:07.85#ibcon#about to write, iclass 12, count 2 2006.168.07:20:07.85#ibcon#wrote, iclass 12, count 2 2006.168.07:20:07.85#ibcon#about to read 3, iclass 12, count 2 2006.168.07:20:07.88#ibcon#read 3, iclass 12, count 2 2006.168.07:20:07.88#ibcon#about to read 4, iclass 12, count 2 2006.168.07:20:07.88#ibcon#read 4, iclass 12, count 2 2006.168.07:20:07.88#ibcon#about to read 5, iclass 12, count 2 2006.168.07:20:07.88#ibcon#read 5, iclass 12, count 2 2006.168.07:20:07.88#ibcon#about to read 6, iclass 12, count 2 2006.168.07:20:07.88#ibcon#read 6, iclass 12, count 2 2006.168.07:20:07.88#ibcon#end of sib2, iclass 12, count 2 2006.168.07:20:07.88#ibcon#*after write, iclass 12, count 2 2006.168.07:20:07.88#ibcon#*before return 0, iclass 12, count 2 2006.168.07:20:07.88#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:20:07.88#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:20:07.88#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.168.07:20:07.88#ibcon#ireg 7 cls_cnt 0 2006.168.07:20:07.88#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:20:08.00#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:20:08.00#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:20:08.00#ibcon#enter wrdev, iclass 12, count 0 2006.168.07:20:08.00#ibcon#first serial, iclass 12, count 0 2006.168.07:20:08.00#ibcon#enter sib2, iclass 12, count 0 2006.168.07:20:08.00#ibcon#flushed, iclass 12, count 0 2006.168.07:20:08.00#ibcon#about to write, iclass 12, count 0 2006.168.07:20:08.00#ibcon#wrote, iclass 12, count 0 2006.168.07:20:08.00#ibcon#about to read 3, iclass 12, count 0 2006.168.07:20:08.02#ibcon#read 3, iclass 12, count 0 2006.168.07:20:08.02#ibcon#about to read 4, iclass 12, count 0 2006.168.07:20:08.02#ibcon#read 4, iclass 12, count 0 2006.168.07:20:08.02#ibcon#about to read 5, iclass 12, count 0 2006.168.07:20:08.02#ibcon#read 5, iclass 12, count 0 2006.168.07:20:08.02#ibcon#about to read 6, iclass 12, count 0 2006.168.07:20:08.02#ibcon#read 6, iclass 12, count 0 2006.168.07:20:08.02#ibcon#end of sib2, iclass 12, count 0 2006.168.07:20:08.02#ibcon#*mode == 0, iclass 12, count 0 2006.168.07:20:08.02#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.168.07:20:08.02#ibcon#[27=USB\r\n] 2006.168.07:20:08.02#ibcon#*before write, iclass 12, count 0 2006.168.07:20:08.02#ibcon#enter sib2, iclass 12, count 0 2006.168.07:20:08.02#ibcon#flushed, iclass 12, count 0 2006.168.07:20:08.02#ibcon#about to write, iclass 12, count 0 2006.168.07:20:08.02#ibcon#wrote, iclass 12, count 0 2006.168.07:20:08.02#ibcon#about to read 3, iclass 12, count 0 2006.168.07:20:08.05#ibcon#read 3, iclass 12, count 0 2006.168.07:20:08.05#ibcon#about to read 4, iclass 12, count 0 2006.168.07:20:08.05#ibcon#read 4, iclass 12, count 0 2006.168.07:20:08.05#ibcon#about to read 5, iclass 12, count 0 2006.168.07:20:08.05#ibcon#read 5, iclass 12, count 0 2006.168.07:20:08.05#ibcon#about to read 6, iclass 12, count 0 2006.168.07:20:08.05#ibcon#read 6, iclass 12, count 0 2006.168.07:20:08.05#ibcon#end of sib2, iclass 12, count 0 2006.168.07:20:08.05#ibcon#*after write, iclass 12, count 0 2006.168.07:20:08.05#ibcon#*before return 0, iclass 12, count 0 2006.168.07:20:08.05#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:20:08.05#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:20:08.05#ibcon#about to clear, iclass 12 cls_cnt 0 2006.168.07:20:08.05#ibcon#cleared, iclass 12 cls_cnt 0 2006.168.07:20:08.05$vc4f8/vblo=6,752.99 2006.168.07:20:08.05#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.168.07:20:08.05#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.168.07:20:08.05#ibcon#ireg 17 cls_cnt 0 2006.168.07:20:08.05#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:20:08.05#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:20:08.05#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:20:08.05#ibcon#enter wrdev, iclass 14, count 0 2006.168.07:20:08.05#ibcon#first serial, iclass 14, count 0 2006.168.07:20:08.05#ibcon#enter sib2, iclass 14, count 0 2006.168.07:20:08.05#ibcon#flushed, iclass 14, count 0 2006.168.07:20:08.05#ibcon#about to write, iclass 14, count 0 2006.168.07:20:08.05#ibcon#wrote, iclass 14, count 0 2006.168.07:20:08.05#ibcon#about to read 3, iclass 14, count 0 2006.168.07:20:08.07#ibcon#read 3, iclass 14, count 0 2006.168.07:20:08.07#ibcon#about to read 4, iclass 14, count 0 2006.168.07:20:08.07#ibcon#read 4, iclass 14, count 0 2006.168.07:20:08.07#ibcon#about to read 5, iclass 14, count 0 2006.168.07:20:08.07#ibcon#read 5, iclass 14, count 0 2006.168.07:20:08.07#ibcon#about to read 6, iclass 14, count 0 2006.168.07:20:08.07#ibcon#read 6, iclass 14, count 0 2006.168.07:20:08.07#ibcon#end of sib2, iclass 14, count 0 2006.168.07:20:08.07#ibcon#*mode == 0, iclass 14, count 0 2006.168.07:20:08.07#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.168.07:20:08.07#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.07:20:08.07#ibcon#*before write, iclass 14, count 0 2006.168.07:20:08.07#ibcon#enter sib2, iclass 14, count 0 2006.168.07:20:08.07#ibcon#flushed, iclass 14, count 0 2006.168.07:20:08.07#ibcon#about to write, iclass 14, count 0 2006.168.07:20:08.07#ibcon#wrote, iclass 14, count 0 2006.168.07:20:08.07#ibcon#about to read 3, iclass 14, count 0 2006.168.07:20:08.11#ibcon#read 3, iclass 14, count 0 2006.168.07:20:08.11#ibcon#about to read 4, iclass 14, count 0 2006.168.07:20:08.11#ibcon#read 4, iclass 14, count 0 2006.168.07:20:08.11#ibcon#about to read 5, iclass 14, count 0 2006.168.07:20:08.11#ibcon#read 5, iclass 14, count 0 2006.168.07:20:08.11#ibcon#about to read 6, iclass 14, count 0 2006.168.07:20:08.11#ibcon#read 6, iclass 14, count 0 2006.168.07:20:08.11#ibcon#end of sib2, iclass 14, count 0 2006.168.07:20:08.11#ibcon#*after write, iclass 14, count 0 2006.168.07:20:08.11#ibcon#*before return 0, iclass 14, count 0 2006.168.07:20:08.11#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:20:08.11#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:20:08.11#ibcon#about to clear, iclass 14 cls_cnt 0 2006.168.07:20:08.11#ibcon#cleared, iclass 14 cls_cnt 0 2006.168.07:20:08.11$vc4f8/vb=6,4 2006.168.07:20:08.11#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.168.07:20:08.11#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.168.07:20:08.11#ibcon#ireg 11 cls_cnt 2 2006.168.07:20:08.11#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:20:08.17#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:20:08.17#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:20:08.17#ibcon#enter wrdev, iclass 16, count 2 2006.168.07:20:08.17#ibcon#first serial, iclass 16, count 2 2006.168.07:20:08.17#ibcon#enter sib2, iclass 16, count 2 2006.168.07:20:08.17#ibcon#flushed, iclass 16, count 2 2006.168.07:20:08.17#ibcon#about to write, iclass 16, count 2 2006.168.07:20:08.17#ibcon#wrote, iclass 16, count 2 2006.168.07:20:08.17#ibcon#about to read 3, iclass 16, count 2 2006.168.07:20:08.19#ibcon#read 3, iclass 16, count 2 2006.168.07:20:08.19#ibcon#about to read 4, iclass 16, count 2 2006.168.07:20:08.19#ibcon#read 4, iclass 16, count 2 2006.168.07:20:08.19#ibcon#about to read 5, iclass 16, count 2 2006.168.07:20:08.19#ibcon#read 5, iclass 16, count 2 2006.168.07:20:08.19#ibcon#about to read 6, iclass 16, count 2 2006.168.07:20:08.19#ibcon#read 6, iclass 16, count 2 2006.168.07:20:08.19#ibcon#end of sib2, iclass 16, count 2 2006.168.07:20:08.19#ibcon#*mode == 0, iclass 16, count 2 2006.168.07:20:08.19#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.168.07:20:08.19#ibcon#[27=AT06-04\r\n] 2006.168.07:20:08.19#ibcon#*before write, iclass 16, count 2 2006.168.07:20:08.19#ibcon#enter sib2, iclass 16, count 2 2006.168.07:20:08.19#ibcon#flushed, iclass 16, count 2 2006.168.07:20:08.19#ibcon#about to write, iclass 16, count 2 2006.168.07:20:08.19#ibcon#wrote, iclass 16, count 2 2006.168.07:20:08.19#ibcon#about to read 3, iclass 16, count 2 2006.168.07:20:08.22#ibcon#read 3, iclass 16, count 2 2006.168.07:20:08.22#ibcon#about to read 4, iclass 16, count 2 2006.168.07:20:08.22#ibcon#read 4, iclass 16, count 2 2006.168.07:20:08.22#ibcon#about to read 5, iclass 16, count 2 2006.168.07:20:08.22#ibcon#read 5, iclass 16, count 2 2006.168.07:20:08.22#ibcon#about to read 6, iclass 16, count 2 2006.168.07:20:08.22#ibcon#read 6, iclass 16, count 2 2006.168.07:20:08.22#ibcon#end of sib2, iclass 16, count 2 2006.168.07:20:08.22#ibcon#*after write, iclass 16, count 2 2006.168.07:20:08.22#ibcon#*before return 0, iclass 16, count 2 2006.168.07:20:08.22#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:20:08.22#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:20:08.22#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.168.07:20:08.22#ibcon#ireg 7 cls_cnt 0 2006.168.07:20:08.22#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:20:08.34#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:20:08.34#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:20:08.34#ibcon#enter wrdev, iclass 16, count 0 2006.168.07:20:08.34#ibcon#first serial, iclass 16, count 0 2006.168.07:20:08.34#ibcon#enter sib2, iclass 16, count 0 2006.168.07:20:08.34#ibcon#flushed, iclass 16, count 0 2006.168.07:20:08.34#ibcon#about to write, iclass 16, count 0 2006.168.07:20:08.34#ibcon#wrote, iclass 16, count 0 2006.168.07:20:08.34#ibcon#about to read 3, iclass 16, count 0 2006.168.07:20:08.36#ibcon#read 3, iclass 16, count 0 2006.168.07:20:08.36#ibcon#about to read 4, iclass 16, count 0 2006.168.07:20:08.36#ibcon#read 4, iclass 16, count 0 2006.168.07:20:08.36#ibcon#about to read 5, iclass 16, count 0 2006.168.07:20:08.36#ibcon#read 5, iclass 16, count 0 2006.168.07:20:08.36#ibcon#about to read 6, iclass 16, count 0 2006.168.07:20:08.36#ibcon#read 6, iclass 16, count 0 2006.168.07:20:08.36#ibcon#end of sib2, iclass 16, count 0 2006.168.07:20:08.36#ibcon#*mode == 0, iclass 16, count 0 2006.168.07:20:08.36#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.168.07:20:08.36#ibcon#[27=USB\r\n] 2006.168.07:20:08.36#ibcon#*before write, iclass 16, count 0 2006.168.07:20:08.36#ibcon#enter sib2, iclass 16, count 0 2006.168.07:20:08.36#ibcon#flushed, iclass 16, count 0 2006.168.07:20:08.36#ibcon#about to write, iclass 16, count 0 2006.168.07:20:08.36#ibcon#wrote, iclass 16, count 0 2006.168.07:20:08.36#ibcon#about to read 3, iclass 16, count 0 2006.168.07:20:08.39#ibcon#read 3, iclass 16, count 0 2006.168.07:20:08.39#ibcon#about to read 4, iclass 16, count 0 2006.168.07:20:08.39#ibcon#read 4, iclass 16, count 0 2006.168.07:20:08.39#ibcon#about to read 5, iclass 16, count 0 2006.168.07:20:08.39#ibcon#read 5, iclass 16, count 0 2006.168.07:20:08.39#ibcon#about to read 6, iclass 16, count 0 2006.168.07:20:08.39#ibcon#read 6, iclass 16, count 0 2006.168.07:20:08.39#ibcon#end of sib2, iclass 16, count 0 2006.168.07:20:08.39#ibcon#*after write, iclass 16, count 0 2006.168.07:20:08.39#ibcon#*before return 0, iclass 16, count 0 2006.168.07:20:08.39#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:20:08.39#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:20:08.39#ibcon#about to clear, iclass 16 cls_cnt 0 2006.168.07:20:08.39#ibcon#cleared, iclass 16 cls_cnt 0 2006.168.07:20:08.39$vc4f8/vabw=wide 2006.168.07:20:08.39#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.168.07:20:08.39#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.168.07:20:08.39#ibcon#ireg 8 cls_cnt 0 2006.168.07:20:08.39#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:20:08.39#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:20:08.39#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:20:08.39#ibcon#enter wrdev, iclass 18, count 0 2006.168.07:20:08.39#ibcon#first serial, iclass 18, count 0 2006.168.07:20:08.39#ibcon#enter sib2, iclass 18, count 0 2006.168.07:20:08.39#ibcon#flushed, iclass 18, count 0 2006.168.07:20:08.39#ibcon#about to write, iclass 18, count 0 2006.168.07:20:08.39#ibcon#wrote, iclass 18, count 0 2006.168.07:20:08.39#ibcon#about to read 3, iclass 18, count 0 2006.168.07:20:08.41#ibcon#read 3, iclass 18, count 0 2006.168.07:20:08.41#ibcon#about to read 4, iclass 18, count 0 2006.168.07:20:08.41#ibcon#read 4, iclass 18, count 0 2006.168.07:20:08.41#ibcon#about to read 5, iclass 18, count 0 2006.168.07:20:08.41#ibcon#read 5, iclass 18, count 0 2006.168.07:20:08.41#ibcon#about to read 6, iclass 18, count 0 2006.168.07:20:08.41#ibcon#read 6, iclass 18, count 0 2006.168.07:20:08.41#ibcon#end of sib2, iclass 18, count 0 2006.168.07:20:08.41#ibcon#*mode == 0, iclass 18, count 0 2006.168.07:20:08.41#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.07:20:08.41#ibcon#[25=BW32\r\n] 2006.168.07:20:08.41#ibcon#*before write, iclass 18, count 0 2006.168.07:20:08.41#ibcon#enter sib2, iclass 18, count 0 2006.168.07:20:08.41#ibcon#flushed, iclass 18, count 0 2006.168.07:20:08.41#ibcon#about to write, iclass 18, count 0 2006.168.07:20:08.41#ibcon#wrote, iclass 18, count 0 2006.168.07:20:08.41#ibcon#about to read 3, iclass 18, count 0 2006.168.07:20:08.44#ibcon#read 3, iclass 18, count 0 2006.168.07:20:08.44#ibcon#about to read 4, iclass 18, count 0 2006.168.07:20:08.44#ibcon#read 4, iclass 18, count 0 2006.168.07:20:08.44#ibcon#about to read 5, iclass 18, count 0 2006.168.07:20:08.44#ibcon#read 5, iclass 18, count 0 2006.168.07:20:08.44#ibcon#about to read 6, iclass 18, count 0 2006.168.07:20:08.44#ibcon#read 6, iclass 18, count 0 2006.168.07:20:08.44#ibcon#end of sib2, iclass 18, count 0 2006.168.07:20:08.44#ibcon#*after write, iclass 18, count 0 2006.168.07:20:08.44#ibcon#*before return 0, iclass 18, count 0 2006.168.07:20:08.44#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:20:08.44#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:20:08.44#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.07:20:08.44#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.07:20:08.44$vc4f8/vbbw=wide 2006.168.07:20:08.44#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.168.07:20:08.44#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.168.07:20:08.44#ibcon#ireg 8 cls_cnt 0 2006.168.07:20:08.44#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:20:08.51#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:20:08.51#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:20:08.51#ibcon#enter wrdev, iclass 20, count 0 2006.168.07:20:08.51#ibcon#first serial, iclass 20, count 0 2006.168.07:20:08.51#ibcon#enter sib2, iclass 20, count 0 2006.168.07:20:08.51#ibcon#flushed, iclass 20, count 0 2006.168.07:20:08.51#ibcon#about to write, iclass 20, count 0 2006.168.07:20:08.51#ibcon#wrote, iclass 20, count 0 2006.168.07:20:08.51#ibcon#about to read 3, iclass 20, count 0 2006.168.07:20:08.53#ibcon#read 3, iclass 20, count 0 2006.168.07:20:08.53#ibcon#about to read 4, iclass 20, count 0 2006.168.07:20:08.53#ibcon#read 4, iclass 20, count 0 2006.168.07:20:08.53#ibcon#about to read 5, iclass 20, count 0 2006.168.07:20:08.53#ibcon#read 5, iclass 20, count 0 2006.168.07:20:08.53#ibcon#about to read 6, iclass 20, count 0 2006.168.07:20:08.53#ibcon#read 6, iclass 20, count 0 2006.168.07:20:08.53#ibcon#end of sib2, iclass 20, count 0 2006.168.07:20:08.53#ibcon#*mode == 0, iclass 20, count 0 2006.168.07:20:08.53#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.168.07:20:08.53#ibcon#[27=BW32\r\n] 2006.168.07:20:08.53#ibcon#*before write, iclass 20, count 0 2006.168.07:20:08.53#ibcon#enter sib2, iclass 20, count 0 2006.168.07:20:08.53#ibcon#flushed, iclass 20, count 0 2006.168.07:20:08.53#ibcon#about to write, iclass 20, count 0 2006.168.07:20:08.53#ibcon#wrote, iclass 20, count 0 2006.168.07:20:08.53#ibcon#about to read 3, iclass 20, count 0 2006.168.07:20:08.56#ibcon#read 3, iclass 20, count 0 2006.168.07:20:08.56#ibcon#about to read 4, iclass 20, count 0 2006.168.07:20:08.56#ibcon#read 4, iclass 20, count 0 2006.168.07:20:08.56#ibcon#about to read 5, iclass 20, count 0 2006.168.07:20:08.56#ibcon#read 5, iclass 20, count 0 2006.168.07:20:08.56#ibcon#about to read 6, iclass 20, count 0 2006.168.07:20:08.56#ibcon#read 6, iclass 20, count 0 2006.168.07:20:08.56#ibcon#end of sib2, iclass 20, count 0 2006.168.07:20:08.56#ibcon#*after write, iclass 20, count 0 2006.168.07:20:08.56#ibcon#*before return 0, iclass 20, count 0 2006.168.07:20:08.56#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:20:08.56#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:20:08.56#ibcon#about to clear, iclass 20 cls_cnt 0 2006.168.07:20:08.56#ibcon#cleared, iclass 20 cls_cnt 0 2006.168.07:20:08.56$4f8m12a/ifd4f 2006.168.07:20:08.56&ifd4f/lo= 2006.168.07:20:08.56&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.07:20:08.56&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.07:20:08.56&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.07:20:08.56&ifd4f/patch= 2006.168.07:20:08.56&ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.07:20:08.56&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.07:20:08.56&ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.07:20:08.56$ifd4f/lo= 2006.168.07:20:08.56$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.07:20:08.56$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.07:20:08.56$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.07:20:08.56$ifd4f/patch= 2006.168.07:20:08.56$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.07:20:08.56$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.07:20:08.56$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.07:20:08.56$4f8m12a/"form=m,16.000,1:2 2006.168.07:20:08.56$4f8m12a/"tpicd 2006.168.07:20:08.56$4f8m12a/echo=off 2006.168.07:20:08.56$4f8m12a/xlog=off 2006.168.07:20:08.56:!2006.168.07:29:50 2006.168.07:20:24.13#trakl#Source acquired 2006.168.07:20:26.13#flagr#flagr/antenna,acquired 2006.168.07:29:50.00:preob 2006.168.07:29:50.00&preob/onsource 2006.168.07:29:51.14/onsource/TRACKING 2006.168.07:29:51.14:!2006.168.07:30:00 2006.168.07:30:00.00:data_valid=on 2006.168.07:30:00.00:midob 2006.168.07:30:00.00&midob/onsource 2006.168.07:30:00.00&midob/wx 2006.168.07:30:00.00&midob/cable 2006.168.07:30:00.00&midob/va 2006.168.07:30:00.00&midob/valo 2006.168.07:30:00.00&midob/vb 2006.168.07:30:00.00&midob/vblo 2006.168.07:30:00.00&midob/vabw 2006.168.07:30:00.00&midob/vbbw 2006.168.07:30:00.00&midob/"form 2006.168.07:30:00.00&midob/xfe 2006.168.07:30:00.00&midob/ifatt 2006.168.07:30:00.00&midob/clockoff 2006.168.07:30:00.00&midob/sy=logmail 2006.168.07:30:00.00&midob/"sy=run setcl adapt & 2006.168.07:30:00.14/onsource/TRACKING 2006.168.07:30:00.14/wx/27.93,1004.6,73 2006.168.07:30:00.36/cable/+6.4709E-03 2006.168.07:30:01.45/va/01,08,usb,yes,31,32 2006.168.07:30:01.45/va/02,07,usb,yes,31,32 2006.168.07:30:01.45/va/03,06,usb,yes,32,33 2006.168.07:30:01.45/va/04,07,usb,yes,32,34 2006.168.07:30:01.45/va/05,07,usb,yes,31,33 2006.168.07:30:01.45/va/06,06,usb,yes,30,30 2006.168.07:30:01.45/va/07,06,usb,yes,31,30 2006.168.07:30:01.45/va/08,07,usb,yes,29,29 2006.168.07:30:01.68/valo/01,532.99,yes,locked 2006.168.07:30:01.68/valo/02,572.99,yes,locked 2006.168.07:30:01.68/valo/03,672.99,yes,locked 2006.168.07:30:01.68/valo/04,832.99,yes,locked 2006.168.07:30:01.68/valo/05,652.99,yes,locked 2006.168.07:30:01.68/valo/06,772.99,yes,locked 2006.168.07:30:01.68/valo/07,832.99,yes,locked 2006.168.07:30:01.68/valo/08,852.99,yes,locked 2006.168.07:30:02.77/vb/01,04,usb,yes,30,28 2006.168.07:30:02.77/vb/02,04,usb,yes,32,33 2006.168.07:30:02.77/vb/03,04,usb,yes,28,32 2006.168.07:30:02.77/vb/04,04,usb,yes,29,29 2006.168.07:30:02.77/vb/05,04,usb,yes,27,31 2006.168.07:30:02.77/vb/06,04,usb,yes,28,31 2006.168.07:30:02.77/vb/07,04,usb,yes,30,30 2006.168.07:30:02.77/vb/08,04,usb,yes,28,31 2006.168.07:30:03.01/vblo/01,632.99,yes,locked 2006.168.07:30:03.01/vblo/02,640.99,yes,locked 2006.168.07:30:03.01/vblo/03,656.99,yes,locked 2006.168.07:30:03.01/vblo/04,712.99,yes,locked 2006.168.07:30:03.01/vblo/05,744.99,yes,locked 2006.168.07:30:03.01/vblo/06,752.99,yes,locked 2006.168.07:30:03.01/vblo/07,734.99,yes,locked 2006.168.07:30:03.01/vblo/08,744.99,yes,locked 2006.168.07:30:03.16/vabw/8 2006.168.07:30:03.31/vbbw/8 2006.168.07:30:03.48/xfe/off,on,15.2 2006.168.07:30:03.85/ifatt/23,28,28,28 2006.168.07:30:03.85&clockoff/"gps-fmout=1p 2006.168.07:30:03.85&clockoff/fmout-gps=1p 2006.168.07:30:04.08/fmout-gps/S +4.20E-07 2006.168.07:30:04.16:!2006.168.07:31:00 2006.168.07:31:00.01:data_valid=off 2006.168.07:31:00.01:postob 2006.168.07:31:00.02&postob/cable 2006.168.07:31:00.02&postob/wx 2006.168.07:31:00.02&postob/clockoff 2006.168.07:31:00.12/cable/+6.4719E-03 2006.168.07:31:00.12/wx/27.92,1004.6,74 2006.168.07:31:00.21/fmout-gps/S +4.21E-07 2006.168.07:31:00.21:scan_name=168-0733,k06168,60 2006.168.07:31:00.21:source=0748+126,075052.05,123104.8,2000.0,ccw 2006.168.07:31:01.14#flagr#flagr/antenna,new-source 2006.168.07:31:01.14:checkk5 2006.168.07:31:01.15&checkk5/chk_autoobs=1 2006.168.07:31:01.15&checkk5/chk_autoobs=2 2006.168.07:31:01.15&checkk5/chk_autoobs=3 2006.168.07:31:01.16&checkk5/chk_autoobs=4 2006.168.07:31:01.16&checkk5/chk_obsdata=1 2006.168.07:31:01.16&checkk5/chk_obsdata=2 2006.168.07:31:01.16&checkk5/chk_obsdata=3 2006.168.07:31:01.16&checkk5/chk_obsdata=4 2006.168.07:31:01.16&checkk5/k5log=1 2006.168.07:31:01.16&checkk5/k5log=2 2006.168.07:31:01.16&checkk5/k5log=3 2006.168.07:31:01.16&checkk5/k5log=4 2006.168.07:31:01.16&checkk5/obsinfo 2006.168.07:31:01.56/chk_autoobs//k5ts1/ autoobs is running! 2006.168.07:31:01.97/chk_autoobs//k5ts2/ autoobs is running! 2006.168.07:31:02.38/chk_autoobs//k5ts3/ autoobs is running! 2006.168.07:31:02.77/chk_autoobs//k5ts4/ autoobs is running! 2006.168.07:31:03.15/chk_obsdata//k5ts1/T1680730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:31:03.51/chk_obsdata//k5ts2/T1680730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:31:03.89/chk_obsdata//k5ts3/T1680730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:31:04.27/chk_obsdata//k5ts4/T1680730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:31:04.97/k5log//k5ts1_log_newline 2006.168.07:31:05.65/k5log//k5ts2_log_newline 2006.168.07:31:06.35/k5log//k5ts3_log_newline 2006.168.07:31:07.04/k5log//k5ts4_log_newline 2006.168.07:31:07.10/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.07:31:07.10:4f8m12a=1 2006.168.07:31:07.10$4f8m12a/echo=on 2006.168.07:31:07.10$4f8m12a/pcalon 2006.168.07:31:07.10$pcalon/"no phase cal control is implemented here 2006.168.07:31:07.10$4f8m12a/"tpicd=stop 2006.168.07:31:07.10$4f8m12a/vc4f8 2006.168.07:31:07.10$vc4f8/valo=1,532.99 2006.168.07:31:07.11#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.168.07:31:07.11#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.168.07:31:07.11#ibcon#ireg 17 cls_cnt 0 2006.168.07:31:07.11#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:31:07.11#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:31:07.11#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:31:07.11#ibcon#enter wrdev, iclass 31, count 0 2006.168.07:31:07.11#ibcon#first serial, iclass 31, count 0 2006.168.07:31:07.11#ibcon#enter sib2, iclass 31, count 0 2006.168.07:31:07.11#ibcon#flushed, iclass 31, count 0 2006.168.07:31:07.11#ibcon#about to write, iclass 31, count 0 2006.168.07:31:07.11#ibcon#wrote, iclass 31, count 0 2006.168.07:31:07.11#ibcon#about to read 3, iclass 31, count 0 2006.168.07:31:07.13#ibcon#read 3, iclass 31, count 0 2006.168.07:31:07.13#ibcon#about to read 4, iclass 31, count 0 2006.168.07:31:07.13#ibcon#read 4, iclass 31, count 0 2006.168.07:31:07.13#ibcon#about to read 5, iclass 31, count 0 2006.168.07:31:07.13#ibcon#read 5, iclass 31, count 0 2006.168.07:31:07.13#ibcon#about to read 6, iclass 31, count 0 2006.168.07:31:07.13#ibcon#read 6, iclass 31, count 0 2006.168.07:31:07.13#ibcon#end of sib2, iclass 31, count 0 2006.168.07:31:07.13#ibcon#*mode == 0, iclass 31, count 0 2006.168.07:31:07.13#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.168.07:31:07.13#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.07:31:07.13#ibcon#*before write, iclass 31, count 0 2006.168.07:31:07.13#ibcon#enter sib2, iclass 31, count 0 2006.168.07:31:07.13#ibcon#flushed, iclass 31, count 0 2006.168.07:31:07.13#ibcon#about to write, iclass 31, count 0 2006.168.07:31:07.13#ibcon#wrote, iclass 31, count 0 2006.168.07:31:07.13#ibcon#about to read 3, iclass 31, count 0 2006.168.07:31:07.18#ibcon#read 3, iclass 31, count 0 2006.168.07:31:07.18#ibcon#about to read 4, iclass 31, count 0 2006.168.07:31:07.18#ibcon#read 4, iclass 31, count 0 2006.168.07:31:07.18#ibcon#about to read 5, iclass 31, count 0 2006.168.07:31:07.18#ibcon#read 5, iclass 31, count 0 2006.168.07:31:07.18#ibcon#about to read 6, iclass 31, count 0 2006.168.07:31:07.18#ibcon#read 6, iclass 31, count 0 2006.168.07:31:07.18#ibcon#end of sib2, iclass 31, count 0 2006.168.07:31:07.18#ibcon#*after write, iclass 31, count 0 2006.168.07:31:07.18#ibcon#*before return 0, iclass 31, count 0 2006.168.07:31:07.18#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:31:07.18#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:31:07.18#ibcon#about to clear, iclass 31 cls_cnt 0 2006.168.07:31:07.18#ibcon#cleared, iclass 31 cls_cnt 0 2006.168.07:31:07.18$vc4f8/va=1,8 2006.168.07:31:07.18#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.168.07:31:07.18#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.168.07:31:07.18#ibcon#ireg 11 cls_cnt 2 2006.168.07:31:07.18#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:31:07.18#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:31:07.18#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:31:07.18#ibcon#enter wrdev, iclass 33, count 2 2006.168.07:31:07.18#ibcon#first serial, iclass 33, count 2 2006.168.07:31:07.18#ibcon#enter sib2, iclass 33, count 2 2006.168.07:31:07.18#ibcon#flushed, iclass 33, count 2 2006.168.07:31:07.18#ibcon#about to write, iclass 33, count 2 2006.168.07:31:07.18#ibcon#wrote, iclass 33, count 2 2006.168.07:31:07.18#ibcon#about to read 3, iclass 33, count 2 2006.168.07:31:07.20#ibcon#read 3, iclass 33, count 2 2006.168.07:31:07.20#ibcon#about to read 4, iclass 33, count 2 2006.168.07:31:07.20#ibcon#read 4, iclass 33, count 2 2006.168.07:31:07.20#ibcon#about to read 5, iclass 33, count 2 2006.168.07:31:07.20#ibcon#read 5, iclass 33, count 2 2006.168.07:31:07.20#ibcon#about to read 6, iclass 33, count 2 2006.168.07:31:07.20#ibcon#read 6, iclass 33, count 2 2006.168.07:31:07.20#ibcon#end of sib2, iclass 33, count 2 2006.168.07:31:07.20#ibcon#*mode == 0, iclass 33, count 2 2006.168.07:31:07.20#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.168.07:31:07.20#ibcon#[25=AT01-08\r\n] 2006.168.07:31:07.20#ibcon#*before write, iclass 33, count 2 2006.168.07:31:07.20#ibcon#enter sib2, iclass 33, count 2 2006.168.07:31:07.20#ibcon#flushed, iclass 33, count 2 2006.168.07:31:07.20#ibcon#about to write, iclass 33, count 2 2006.168.07:31:07.20#ibcon#wrote, iclass 33, count 2 2006.168.07:31:07.20#ibcon#about to read 3, iclass 33, count 2 2006.168.07:31:07.23#ibcon#read 3, iclass 33, count 2 2006.168.07:31:07.23#ibcon#about to read 4, iclass 33, count 2 2006.168.07:31:07.23#ibcon#read 4, iclass 33, count 2 2006.168.07:31:07.23#ibcon#about to read 5, iclass 33, count 2 2006.168.07:31:07.23#ibcon#read 5, iclass 33, count 2 2006.168.07:31:07.23#ibcon#about to read 6, iclass 33, count 2 2006.168.07:31:07.23#ibcon#read 6, iclass 33, count 2 2006.168.07:31:07.23#ibcon#end of sib2, iclass 33, count 2 2006.168.07:31:07.23#ibcon#*after write, iclass 33, count 2 2006.168.07:31:07.23#ibcon#*before return 0, iclass 33, count 2 2006.168.07:31:07.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:31:07.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:31:07.23#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.168.07:31:07.23#ibcon#ireg 7 cls_cnt 0 2006.168.07:31:07.23#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:31:07.35#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:31:07.35#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:31:07.35#ibcon#enter wrdev, iclass 33, count 0 2006.168.07:31:07.35#ibcon#first serial, iclass 33, count 0 2006.168.07:31:07.35#ibcon#enter sib2, iclass 33, count 0 2006.168.07:31:07.35#ibcon#flushed, iclass 33, count 0 2006.168.07:31:07.35#ibcon#about to write, iclass 33, count 0 2006.168.07:31:07.35#ibcon#wrote, iclass 33, count 0 2006.168.07:31:07.35#ibcon#about to read 3, iclass 33, count 0 2006.168.07:31:07.37#ibcon#read 3, iclass 33, count 0 2006.168.07:31:07.37#ibcon#about to read 4, iclass 33, count 0 2006.168.07:31:07.37#ibcon#read 4, iclass 33, count 0 2006.168.07:31:07.37#ibcon#about to read 5, iclass 33, count 0 2006.168.07:31:07.37#ibcon#read 5, iclass 33, count 0 2006.168.07:31:07.37#ibcon#about to read 6, iclass 33, count 0 2006.168.07:31:07.37#ibcon#read 6, iclass 33, count 0 2006.168.07:31:07.37#ibcon#end of sib2, iclass 33, count 0 2006.168.07:31:07.37#ibcon#*mode == 0, iclass 33, count 0 2006.168.07:31:07.37#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.168.07:31:07.37#ibcon#[25=USB\r\n] 2006.168.07:31:07.37#ibcon#*before write, iclass 33, count 0 2006.168.07:31:07.37#ibcon#enter sib2, iclass 33, count 0 2006.168.07:31:07.37#ibcon#flushed, iclass 33, count 0 2006.168.07:31:07.37#ibcon#about to write, iclass 33, count 0 2006.168.07:31:07.37#ibcon#wrote, iclass 33, count 0 2006.168.07:31:07.37#ibcon#about to read 3, iclass 33, count 0 2006.168.07:31:07.40#ibcon#read 3, iclass 33, count 0 2006.168.07:31:07.40#ibcon#about to read 4, iclass 33, count 0 2006.168.07:31:07.40#ibcon#read 4, iclass 33, count 0 2006.168.07:31:07.40#ibcon#about to read 5, iclass 33, count 0 2006.168.07:31:07.40#ibcon#read 5, iclass 33, count 0 2006.168.07:31:07.40#ibcon#about to read 6, iclass 33, count 0 2006.168.07:31:07.40#ibcon#read 6, iclass 33, count 0 2006.168.07:31:07.40#ibcon#end of sib2, iclass 33, count 0 2006.168.07:31:07.40#ibcon#*after write, iclass 33, count 0 2006.168.07:31:07.40#ibcon#*before return 0, iclass 33, count 0 2006.168.07:31:07.40#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:31:07.40#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:31:07.40#ibcon#about to clear, iclass 33 cls_cnt 0 2006.168.07:31:07.40#ibcon#cleared, iclass 33 cls_cnt 0 2006.168.07:31:07.40$vc4f8/valo=2,572.99 2006.168.07:31:07.40#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.168.07:31:07.40#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.168.07:31:07.40#ibcon#ireg 17 cls_cnt 0 2006.168.07:31:07.40#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:31:07.40#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:31:07.40#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:31:07.40#ibcon#enter wrdev, iclass 35, count 0 2006.168.07:31:07.40#ibcon#first serial, iclass 35, count 0 2006.168.07:31:07.40#ibcon#enter sib2, iclass 35, count 0 2006.168.07:31:07.40#ibcon#flushed, iclass 35, count 0 2006.168.07:31:07.40#ibcon#about to write, iclass 35, count 0 2006.168.07:31:07.40#ibcon#wrote, iclass 35, count 0 2006.168.07:31:07.40#ibcon#about to read 3, iclass 35, count 0 2006.168.07:31:07.42#ibcon#read 3, iclass 35, count 0 2006.168.07:31:07.42#ibcon#about to read 4, iclass 35, count 0 2006.168.07:31:07.42#ibcon#read 4, iclass 35, count 0 2006.168.07:31:07.42#ibcon#about to read 5, iclass 35, count 0 2006.168.07:31:07.42#ibcon#read 5, iclass 35, count 0 2006.168.07:31:07.42#ibcon#about to read 6, iclass 35, count 0 2006.168.07:31:07.42#ibcon#read 6, iclass 35, count 0 2006.168.07:31:07.42#ibcon#end of sib2, iclass 35, count 0 2006.168.07:31:07.42#ibcon#*mode == 0, iclass 35, count 0 2006.168.07:31:07.42#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.168.07:31:07.42#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.07:31:07.42#ibcon#*before write, iclass 35, count 0 2006.168.07:31:07.42#ibcon#enter sib2, iclass 35, count 0 2006.168.07:31:07.42#ibcon#flushed, iclass 35, count 0 2006.168.07:31:07.42#ibcon#about to write, iclass 35, count 0 2006.168.07:31:07.42#ibcon#wrote, iclass 35, count 0 2006.168.07:31:07.42#ibcon#about to read 3, iclass 35, count 0 2006.168.07:31:07.46#ibcon#read 3, iclass 35, count 0 2006.168.07:31:07.46#ibcon#about to read 4, iclass 35, count 0 2006.168.07:31:07.46#ibcon#read 4, iclass 35, count 0 2006.168.07:31:07.46#ibcon#about to read 5, iclass 35, count 0 2006.168.07:31:07.46#ibcon#read 5, iclass 35, count 0 2006.168.07:31:07.46#ibcon#about to read 6, iclass 35, count 0 2006.168.07:31:07.46#ibcon#read 6, iclass 35, count 0 2006.168.07:31:07.46#ibcon#end of sib2, iclass 35, count 0 2006.168.07:31:07.46#ibcon#*after write, iclass 35, count 0 2006.168.07:31:07.46#ibcon#*before return 0, iclass 35, count 0 2006.168.07:31:07.46#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:31:07.46#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:31:07.46#ibcon#about to clear, iclass 35 cls_cnt 0 2006.168.07:31:07.46#ibcon#cleared, iclass 35 cls_cnt 0 2006.168.07:31:07.46$vc4f8/va=2,7 2006.168.07:31:07.46#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.168.07:31:07.46#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.168.07:31:07.46#ibcon#ireg 11 cls_cnt 2 2006.168.07:31:07.46#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:31:07.52#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:31:07.52#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:31:07.52#ibcon#enter wrdev, iclass 37, count 2 2006.168.07:31:07.52#ibcon#first serial, iclass 37, count 2 2006.168.07:31:07.52#ibcon#enter sib2, iclass 37, count 2 2006.168.07:31:07.52#ibcon#flushed, iclass 37, count 2 2006.168.07:31:07.52#ibcon#about to write, iclass 37, count 2 2006.168.07:31:07.52#ibcon#wrote, iclass 37, count 2 2006.168.07:31:07.52#ibcon#about to read 3, iclass 37, count 2 2006.168.07:31:07.55#ibcon#read 3, iclass 37, count 2 2006.168.07:31:07.55#ibcon#about to read 4, iclass 37, count 2 2006.168.07:31:07.55#ibcon#read 4, iclass 37, count 2 2006.168.07:31:07.55#ibcon#about to read 5, iclass 37, count 2 2006.168.07:31:07.55#ibcon#read 5, iclass 37, count 2 2006.168.07:31:07.55#ibcon#about to read 6, iclass 37, count 2 2006.168.07:31:07.55#ibcon#read 6, iclass 37, count 2 2006.168.07:31:07.55#ibcon#end of sib2, iclass 37, count 2 2006.168.07:31:07.55#ibcon#*mode == 0, iclass 37, count 2 2006.168.07:31:07.55#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.168.07:31:07.55#ibcon#[25=AT02-07\r\n] 2006.168.07:31:07.55#ibcon#*before write, iclass 37, count 2 2006.168.07:31:07.55#ibcon#enter sib2, iclass 37, count 2 2006.168.07:31:07.55#ibcon#flushed, iclass 37, count 2 2006.168.07:31:07.55#ibcon#about to write, iclass 37, count 2 2006.168.07:31:07.55#ibcon#wrote, iclass 37, count 2 2006.168.07:31:07.55#ibcon#about to read 3, iclass 37, count 2 2006.168.07:31:07.58#ibcon#read 3, iclass 37, count 2 2006.168.07:31:07.58#ibcon#about to read 4, iclass 37, count 2 2006.168.07:31:07.58#ibcon#read 4, iclass 37, count 2 2006.168.07:31:07.58#ibcon#about to read 5, iclass 37, count 2 2006.168.07:31:07.58#ibcon#read 5, iclass 37, count 2 2006.168.07:31:07.58#ibcon#about to read 6, iclass 37, count 2 2006.168.07:31:07.58#ibcon#read 6, iclass 37, count 2 2006.168.07:31:07.58#ibcon#end of sib2, iclass 37, count 2 2006.168.07:31:07.58#ibcon#*after write, iclass 37, count 2 2006.168.07:31:07.58#ibcon#*before return 0, iclass 37, count 2 2006.168.07:31:07.58#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:31:07.58#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:31:07.58#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.168.07:31:07.58#ibcon#ireg 7 cls_cnt 0 2006.168.07:31:07.58#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:31:07.70#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:31:07.70#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:31:07.70#ibcon#enter wrdev, iclass 37, count 0 2006.168.07:31:07.70#ibcon#first serial, iclass 37, count 0 2006.168.07:31:07.70#ibcon#enter sib2, iclass 37, count 0 2006.168.07:31:07.70#ibcon#flushed, iclass 37, count 0 2006.168.07:31:07.70#ibcon#about to write, iclass 37, count 0 2006.168.07:31:07.70#ibcon#wrote, iclass 37, count 0 2006.168.07:31:07.70#ibcon#about to read 3, iclass 37, count 0 2006.168.07:31:07.72#ibcon#read 3, iclass 37, count 0 2006.168.07:31:07.72#ibcon#about to read 4, iclass 37, count 0 2006.168.07:31:07.72#ibcon#read 4, iclass 37, count 0 2006.168.07:31:07.72#ibcon#about to read 5, iclass 37, count 0 2006.168.07:31:07.72#ibcon#read 5, iclass 37, count 0 2006.168.07:31:07.72#ibcon#about to read 6, iclass 37, count 0 2006.168.07:31:07.72#ibcon#read 6, iclass 37, count 0 2006.168.07:31:07.72#ibcon#end of sib2, iclass 37, count 0 2006.168.07:31:07.72#ibcon#*mode == 0, iclass 37, count 0 2006.168.07:31:07.72#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.168.07:31:07.72#ibcon#[25=USB\r\n] 2006.168.07:31:07.72#ibcon#*before write, iclass 37, count 0 2006.168.07:31:07.72#ibcon#enter sib2, iclass 37, count 0 2006.168.07:31:07.72#ibcon#flushed, iclass 37, count 0 2006.168.07:31:07.72#ibcon#about to write, iclass 37, count 0 2006.168.07:31:07.72#ibcon#wrote, iclass 37, count 0 2006.168.07:31:07.72#ibcon#about to read 3, iclass 37, count 0 2006.168.07:31:07.75#ibcon#read 3, iclass 37, count 0 2006.168.07:31:07.75#ibcon#about to read 4, iclass 37, count 0 2006.168.07:31:07.75#ibcon#read 4, iclass 37, count 0 2006.168.07:31:07.75#ibcon#about to read 5, iclass 37, count 0 2006.168.07:31:07.75#ibcon#read 5, iclass 37, count 0 2006.168.07:31:07.75#ibcon#about to read 6, iclass 37, count 0 2006.168.07:31:07.75#ibcon#read 6, iclass 37, count 0 2006.168.07:31:07.75#ibcon#end of sib2, iclass 37, count 0 2006.168.07:31:07.75#ibcon#*after write, iclass 37, count 0 2006.168.07:31:07.75#ibcon#*before return 0, iclass 37, count 0 2006.168.07:31:07.75#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:31:07.75#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:31:07.75#ibcon#about to clear, iclass 37 cls_cnt 0 2006.168.07:31:07.75#ibcon#cleared, iclass 37 cls_cnt 0 2006.168.07:31:07.75$vc4f8/valo=3,672.99 2006.168.07:31:07.75#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.168.07:31:07.75#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.168.07:31:07.75#ibcon#ireg 17 cls_cnt 0 2006.168.07:31:07.75#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.168.07:31:07.75#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.168.07:31:07.75#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.168.07:31:07.75#ibcon#enter wrdev, iclass 39, count 0 2006.168.07:31:07.75#ibcon#first serial, iclass 39, count 0 2006.168.07:31:07.75#ibcon#enter sib2, iclass 39, count 0 2006.168.07:31:07.75#ibcon#flushed, iclass 39, count 0 2006.168.07:31:07.75#ibcon#about to write, iclass 39, count 0 2006.168.07:31:07.75#ibcon#wrote, iclass 39, count 0 2006.168.07:31:07.75#ibcon#about to read 3, iclass 39, count 0 2006.168.07:31:07.77#ibcon#read 3, iclass 39, count 0 2006.168.07:31:07.77#ibcon#about to read 4, iclass 39, count 0 2006.168.07:31:07.77#ibcon#read 4, iclass 39, count 0 2006.168.07:31:07.77#ibcon#about to read 5, iclass 39, count 0 2006.168.07:31:07.77#ibcon#read 5, iclass 39, count 0 2006.168.07:31:07.77#ibcon#about to read 6, iclass 39, count 0 2006.168.07:31:07.77#ibcon#read 6, iclass 39, count 0 2006.168.07:31:07.77#ibcon#end of sib2, iclass 39, count 0 2006.168.07:31:07.77#ibcon#*mode == 0, iclass 39, count 0 2006.168.07:31:07.77#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.168.07:31:07.77#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.07:31:07.77#ibcon#*before write, iclass 39, count 0 2006.168.07:31:07.77#ibcon#enter sib2, iclass 39, count 0 2006.168.07:31:07.77#ibcon#flushed, iclass 39, count 0 2006.168.07:31:07.77#ibcon#about to write, iclass 39, count 0 2006.168.07:31:07.77#ibcon#wrote, iclass 39, count 0 2006.168.07:31:07.77#ibcon#about to read 3, iclass 39, count 0 2006.168.07:31:07.81#ibcon#read 3, iclass 39, count 0 2006.168.07:31:07.81#ibcon#about to read 4, iclass 39, count 0 2006.168.07:31:07.81#ibcon#read 4, iclass 39, count 0 2006.168.07:31:07.81#ibcon#about to read 5, iclass 39, count 0 2006.168.07:31:07.81#ibcon#read 5, iclass 39, count 0 2006.168.07:31:07.81#ibcon#about to read 6, iclass 39, count 0 2006.168.07:31:07.81#ibcon#read 6, iclass 39, count 0 2006.168.07:31:07.81#ibcon#end of sib2, iclass 39, count 0 2006.168.07:31:07.81#ibcon#*after write, iclass 39, count 0 2006.168.07:31:07.81#ibcon#*before return 0, iclass 39, count 0 2006.168.07:31:07.81#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.168.07:31:07.81#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.168.07:31:07.81#ibcon#about to clear, iclass 39 cls_cnt 0 2006.168.07:31:07.81#ibcon#cleared, iclass 39 cls_cnt 0 2006.168.07:31:07.81$vc4f8/va=3,6 2006.168.07:31:07.81#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.168.07:31:07.81#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.168.07:31:07.81#ibcon#ireg 11 cls_cnt 2 2006.168.07:31:07.81#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.168.07:31:07.87#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.168.07:31:07.87#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.168.07:31:07.87#ibcon#enter wrdev, iclass 3, count 2 2006.168.07:31:07.87#ibcon#first serial, iclass 3, count 2 2006.168.07:31:07.87#ibcon#enter sib2, iclass 3, count 2 2006.168.07:31:07.87#ibcon#flushed, iclass 3, count 2 2006.168.07:31:07.87#ibcon#about to write, iclass 3, count 2 2006.168.07:31:07.87#ibcon#wrote, iclass 3, count 2 2006.168.07:31:07.87#ibcon#about to read 3, iclass 3, count 2 2006.168.07:31:07.90#ibcon#read 3, iclass 3, count 2 2006.168.07:31:07.90#ibcon#about to read 4, iclass 3, count 2 2006.168.07:31:07.90#ibcon#read 4, iclass 3, count 2 2006.168.07:31:07.90#ibcon#about to read 5, iclass 3, count 2 2006.168.07:31:07.90#ibcon#read 5, iclass 3, count 2 2006.168.07:31:07.90#ibcon#about to read 6, iclass 3, count 2 2006.168.07:31:07.90#ibcon#read 6, iclass 3, count 2 2006.168.07:31:07.90#ibcon#end of sib2, iclass 3, count 2 2006.168.07:31:07.90#ibcon#*mode == 0, iclass 3, count 2 2006.168.07:31:07.90#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.168.07:31:07.90#ibcon#[25=AT03-06\r\n] 2006.168.07:31:07.90#ibcon#*before write, iclass 3, count 2 2006.168.07:31:07.90#ibcon#enter sib2, iclass 3, count 2 2006.168.07:31:07.90#ibcon#flushed, iclass 3, count 2 2006.168.07:31:07.90#ibcon#about to write, iclass 3, count 2 2006.168.07:31:07.90#ibcon#wrote, iclass 3, count 2 2006.168.07:31:07.90#ibcon#about to read 3, iclass 3, count 2 2006.168.07:31:07.93#ibcon#read 3, iclass 3, count 2 2006.168.07:31:07.93#ibcon#about to read 4, iclass 3, count 2 2006.168.07:31:07.93#ibcon#read 4, iclass 3, count 2 2006.168.07:31:07.93#ibcon#about to read 5, iclass 3, count 2 2006.168.07:31:07.93#ibcon#read 5, iclass 3, count 2 2006.168.07:31:07.93#ibcon#about to read 6, iclass 3, count 2 2006.168.07:31:07.93#ibcon#read 6, iclass 3, count 2 2006.168.07:31:07.93#ibcon#end of sib2, iclass 3, count 2 2006.168.07:31:07.93#ibcon#*after write, iclass 3, count 2 2006.168.07:31:07.93#ibcon#*before return 0, iclass 3, count 2 2006.168.07:31:07.93#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.168.07:31:07.93#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.168.07:31:07.93#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.168.07:31:07.93#ibcon#ireg 7 cls_cnt 0 2006.168.07:31:07.93#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.168.07:31:08.05#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.168.07:31:08.05#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.168.07:31:08.05#ibcon#enter wrdev, iclass 3, count 0 2006.168.07:31:08.05#ibcon#first serial, iclass 3, count 0 2006.168.07:31:08.05#ibcon#enter sib2, iclass 3, count 0 2006.168.07:31:08.05#ibcon#flushed, iclass 3, count 0 2006.168.07:31:08.05#ibcon#about to write, iclass 3, count 0 2006.168.07:31:08.05#ibcon#wrote, iclass 3, count 0 2006.168.07:31:08.05#ibcon#about to read 3, iclass 3, count 0 2006.168.07:31:08.07#ibcon#read 3, iclass 3, count 0 2006.168.07:31:08.07#ibcon#about to read 4, iclass 3, count 0 2006.168.07:31:08.07#ibcon#read 4, iclass 3, count 0 2006.168.07:31:08.07#ibcon#about to read 5, iclass 3, count 0 2006.168.07:31:08.07#ibcon#read 5, iclass 3, count 0 2006.168.07:31:08.07#ibcon#about to read 6, iclass 3, count 0 2006.168.07:31:08.07#ibcon#read 6, iclass 3, count 0 2006.168.07:31:08.07#ibcon#end of sib2, iclass 3, count 0 2006.168.07:31:08.07#ibcon#*mode == 0, iclass 3, count 0 2006.168.07:31:08.07#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.168.07:31:08.07#ibcon#[25=USB\r\n] 2006.168.07:31:08.07#ibcon#*before write, iclass 3, count 0 2006.168.07:31:08.07#ibcon#enter sib2, iclass 3, count 0 2006.168.07:31:08.07#ibcon#flushed, iclass 3, count 0 2006.168.07:31:08.07#ibcon#about to write, iclass 3, count 0 2006.168.07:31:08.07#ibcon#wrote, iclass 3, count 0 2006.168.07:31:08.07#ibcon#about to read 3, iclass 3, count 0 2006.168.07:31:08.10#ibcon#read 3, iclass 3, count 0 2006.168.07:31:08.10#ibcon#about to read 4, iclass 3, count 0 2006.168.07:31:08.10#ibcon#read 4, iclass 3, count 0 2006.168.07:31:08.10#ibcon#about to read 5, iclass 3, count 0 2006.168.07:31:08.10#ibcon#read 5, iclass 3, count 0 2006.168.07:31:08.10#ibcon#about to read 6, iclass 3, count 0 2006.168.07:31:08.10#ibcon#read 6, iclass 3, count 0 2006.168.07:31:08.10#ibcon#end of sib2, iclass 3, count 0 2006.168.07:31:08.10#ibcon#*after write, iclass 3, count 0 2006.168.07:31:08.10#ibcon#*before return 0, iclass 3, count 0 2006.168.07:31:08.10#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.168.07:31:08.10#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.168.07:31:08.10#ibcon#about to clear, iclass 3 cls_cnt 0 2006.168.07:31:08.10#ibcon#cleared, iclass 3 cls_cnt 0 2006.168.07:31:08.10$vc4f8/valo=4,832.99 2006.168.07:31:08.10#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.168.07:31:08.10#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.168.07:31:08.10#ibcon#ireg 17 cls_cnt 0 2006.168.07:31:08.10#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.168.07:31:08.10#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.168.07:31:08.10#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.168.07:31:08.10#ibcon#enter wrdev, iclass 5, count 0 2006.168.07:31:08.10#ibcon#first serial, iclass 5, count 0 2006.168.07:31:08.10#ibcon#enter sib2, iclass 5, count 0 2006.168.07:31:08.10#ibcon#flushed, iclass 5, count 0 2006.168.07:31:08.10#ibcon#about to write, iclass 5, count 0 2006.168.07:31:08.10#ibcon#wrote, iclass 5, count 0 2006.168.07:31:08.10#ibcon#about to read 3, iclass 5, count 0 2006.168.07:31:08.12#ibcon#read 3, iclass 5, count 0 2006.168.07:31:08.12#ibcon#about to read 4, iclass 5, count 0 2006.168.07:31:08.12#ibcon#read 4, iclass 5, count 0 2006.168.07:31:08.12#ibcon#about to read 5, iclass 5, count 0 2006.168.07:31:08.12#ibcon#read 5, iclass 5, count 0 2006.168.07:31:08.12#ibcon#about to read 6, iclass 5, count 0 2006.168.07:31:08.12#ibcon#read 6, iclass 5, count 0 2006.168.07:31:08.12#ibcon#end of sib2, iclass 5, count 0 2006.168.07:31:08.12#ibcon#*mode == 0, iclass 5, count 0 2006.168.07:31:08.12#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.168.07:31:08.12#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.07:31:08.12#ibcon#*before write, iclass 5, count 0 2006.168.07:31:08.12#ibcon#enter sib2, iclass 5, count 0 2006.168.07:31:08.12#ibcon#flushed, iclass 5, count 0 2006.168.07:31:08.12#ibcon#about to write, iclass 5, count 0 2006.168.07:31:08.12#ibcon#wrote, iclass 5, count 0 2006.168.07:31:08.12#ibcon#about to read 3, iclass 5, count 0 2006.168.07:31:08.16#ibcon#read 3, iclass 5, count 0 2006.168.07:31:08.16#ibcon#about to read 4, iclass 5, count 0 2006.168.07:31:08.16#ibcon#read 4, iclass 5, count 0 2006.168.07:31:08.16#ibcon#about to read 5, iclass 5, count 0 2006.168.07:31:08.16#ibcon#read 5, iclass 5, count 0 2006.168.07:31:08.16#ibcon#about to read 6, iclass 5, count 0 2006.168.07:31:08.16#ibcon#read 6, iclass 5, count 0 2006.168.07:31:08.16#ibcon#end of sib2, iclass 5, count 0 2006.168.07:31:08.16#ibcon#*after write, iclass 5, count 0 2006.168.07:31:08.16#ibcon#*before return 0, iclass 5, count 0 2006.168.07:31:08.16#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.168.07:31:08.16#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.168.07:31:08.16#ibcon#about to clear, iclass 5 cls_cnt 0 2006.168.07:31:08.16#ibcon#cleared, iclass 5 cls_cnt 0 2006.168.07:31:08.16$vc4f8/va=4,7 2006.168.07:31:08.16#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.168.07:31:08.16#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.168.07:31:08.16#ibcon#ireg 11 cls_cnt 2 2006.168.07:31:08.16#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.168.07:31:08.22#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.168.07:31:08.22#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.168.07:31:08.22#ibcon#enter wrdev, iclass 7, count 2 2006.168.07:31:08.22#ibcon#first serial, iclass 7, count 2 2006.168.07:31:08.22#ibcon#enter sib2, iclass 7, count 2 2006.168.07:31:08.22#ibcon#flushed, iclass 7, count 2 2006.168.07:31:08.22#ibcon#about to write, iclass 7, count 2 2006.168.07:31:08.22#ibcon#wrote, iclass 7, count 2 2006.168.07:31:08.22#ibcon#about to read 3, iclass 7, count 2 2006.168.07:31:08.24#ibcon#read 3, iclass 7, count 2 2006.168.07:31:08.24#ibcon#about to read 4, iclass 7, count 2 2006.168.07:31:08.24#ibcon#read 4, iclass 7, count 2 2006.168.07:31:08.24#ibcon#about to read 5, iclass 7, count 2 2006.168.07:31:08.24#ibcon#read 5, iclass 7, count 2 2006.168.07:31:08.24#ibcon#about to read 6, iclass 7, count 2 2006.168.07:31:08.24#ibcon#read 6, iclass 7, count 2 2006.168.07:31:08.24#ibcon#end of sib2, iclass 7, count 2 2006.168.07:31:08.24#ibcon#*mode == 0, iclass 7, count 2 2006.168.07:31:08.24#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.168.07:31:08.24#ibcon#[25=AT04-07\r\n] 2006.168.07:31:08.24#ibcon#*before write, iclass 7, count 2 2006.168.07:31:08.24#ibcon#enter sib2, iclass 7, count 2 2006.168.07:31:08.24#ibcon#flushed, iclass 7, count 2 2006.168.07:31:08.24#ibcon#about to write, iclass 7, count 2 2006.168.07:31:08.24#ibcon#wrote, iclass 7, count 2 2006.168.07:31:08.24#ibcon#about to read 3, iclass 7, count 2 2006.168.07:31:08.27#ibcon#read 3, iclass 7, count 2 2006.168.07:31:08.27#ibcon#about to read 4, iclass 7, count 2 2006.168.07:31:08.27#ibcon#read 4, iclass 7, count 2 2006.168.07:31:08.27#ibcon#about to read 5, iclass 7, count 2 2006.168.07:31:08.27#ibcon#read 5, iclass 7, count 2 2006.168.07:31:08.27#ibcon#about to read 6, iclass 7, count 2 2006.168.07:31:08.27#ibcon#read 6, iclass 7, count 2 2006.168.07:31:08.27#ibcon#end of sib2, iclass 7, count 2 2006.168.07:31:08.27#ibcon#*after write, iclass 7, count 2 2006.168.07:31:08.27#ibcon#*before return 0, iclass 7, count 2 2006.168.07:31:08.27#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.168.07:31:08.27#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.168.07:31:08.27#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.168.07:31:08.27#ibcon#ireg 7 cls_cnt 0 2006.168.07:31:08.27#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.168.07:31:08.39#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.168.07:31:08.39#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.168.07:31:08.39#ibcon#enter wrdev, iclass 7, count 0 2006.168.07:31:08.39#ibcon#first serial, iclass 7, count 0 2006.168.07:31:08.39#ibcon#enter sib2, iclass 7, count 0 2006.168.07:31:08.39#ibcon#flushed, iclass 7, count 0 2006.168.07:31:08.39#ibcon#about to write, iclass 7, count 0 2006.168.07:31:08.39#ibcon#wrote, iclass 7, count 0 2006.168.07:31:08.39#ibcon#about to read 3, iclass 7, count 0 2006.168.07:31:08.41#ibcon#read 3, iclass 7, count 0 2006.168.07:31:08.41#ibcon#about to read 4, iclass 7, count 0 2006.168.07:31:08.41#ibcon#read 4, iclass 7, count 0 2006.168.07:31:08.41#ibcon#about to read 5, iclass 7, count 0 2006.168.07:31:08.41#ibcon#read 5, iclass 7, count 0 2006.168.07:31:08.41#ibcon#about to read 6, iclass 7, count 0 2006.168.07:31:08.41#ibcon#read 6, iclass 7, count 0 2006.168.07:31:08.41#ibcon#end of sib2, iclass 7, count 0 2006.168.07:31:08.41#ibcon#*mode == 0, iclass 7, count 0 2006.168.07:31:08.41#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.168.07:31:08.41#ibcon#[25=USB\r\n] 2006.168.07:31:08.41#ibcon#*before write, iclass 7, count 0 2006.168.07:31:08.41#ibcon#enter sib2, iclass 7, count 0 2006.168.07:31:08.41#ibcon#flushed, iclass 7, count 0 2006.168.07:31:08.41#ibcon#about to write, iclass 7, count 0 2006.168.07:31:08.41#ibcon#wrote, iclass 7, count 0 2006.168.07:31:08.41#ibcon#about to read 3, iclass 7, count 0 2006.168.07:31:08.44#ibcon#read 3, iclass 7, count 0 2006.168.07:31:08.44#ibcon#about to read 4, iclass 7, count 0 2006.168.07:31:08.44#ibcon#read 4, iclass 7, count 0 2006.168.07:31:08.44#ibcon#about to read 5, iclass 7, count 0 2006.168.07:31:08.44#ibcon#read 5, iclass 7, count 0 2006.168.07:31:08.44#ibcon#about to read 6, iclass 7, count 0 2006.168.07:31:08.44#ibcon#read 6, iclass 7, count 0 2006.168.07:31:08.44#ibcon#end of sib2, iclass 7, count 0 2006.168.07:31:08.44#ibcon#*after write, iclass 7, count 0 2006.168.07:31:08.44#ibcon#*before return 0, iclass 7, count 0 2006.168.07:31:08.44#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.168.07:31:08.44#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.168.07:31:08.44#ibcon#about to clear, iclass 7 cls_cnt 0 2006.168.07:31:08.44#ibcon#cleared, iclass 7 cls_cnt 0 2006.168.07:31:08.44$vc4f8/valo=5,652.99 2006.168.07:31:08.44#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.168.07:31:08.44#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.168.07:31:08.44#ibcon#ireg 17 cls_cnt 0 2006.168.07:31:08.44#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.168.07:31:08.44#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.168.07:31:08.44#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.168.07:31:08.44#ibcon#enter wrdev, iclass 11, count 0 2006.168.07:31:08.44#ibcon#first serial, iclass 11, count 0 2006.168.07:31:08.44#ibcon#enter sib2, iclass 11, count 0 2006.168.07:31:08.44#ibcon#flushed, iclass 11, count 0 2006.168.07:31:08.44#ibcon#about to write, iclass 11, count 0 2006.168.07:31:08.44#ibcon#wrote, iclass 11, count 0 2006.168.07:31:08.44#ibcon#about to read 3, iclass 11, count 0 2006.168.07:31:08.46#ibcon#read 3, iclass 11, count 0 2006.168.07:31:08.46#ibcon#about to read 4, iclass 11, count 0 2006.168.07:31:08.46#ibcon#read 4, iclass 11, count 0 2006.168.07:31:08.46#ibcon#about to read 5, iclass 11, count 0 2006.168.07:31:08.46#ibcon#read 5, iclass 11, count 0 2006.168.07:31:08.46#ibcon#about to read 6, iclass 11, count 0 2006.168.07:31:08.46#ibcon#read 6, iclass 11, count 0 2006.168.07:31:08.46#ibcon#end of sib2, iclass 11, count 0 2006.168.07:31:08.46#ibcon#*mode == 0, iclass 11, count 0 2006.168.07:31:08.46#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.168.07:31:08.46#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.07:31:08.46#ibcon#*before write, iclass 11, count 0 2006.168.07:31:08.46#ibcon#enter sib2, iclass 11, count 0 2006.168.07:31:08.46#ibcon#flushed, iclass 11, count 0 2006.168.07:31:08.46#ibcon#about to write, iclass 11, count 0 2006.168.07:31:08.46#ibcon#wrote, iclass 11, count 0 2006.168.07:31:08.46#ibcon#about to read 3, iclass 11, count 0 2006.168.07:31:08.50#ibcon#read 3, iclass 11, count 0 2006.168.07:31:08.50#ibcon#about to read 4, iclass 11, count 0 2006.168.07:31:08.50#ibcon#read 4, iclass 11, count 0 2006.168.07:31:08.50#ibcon#about to read 5, iclass 11, count 0 2006.168.07:31:08.50#ibcon#read 5, iclass 11, count 0 2006.168.07:31:08.50#ibcon#about to read 6, iclass 11, count 0 2006.168.07:31:08.50#ibcon#read 6, iclass 11, count 0 2006.168.07:31:08.50#ibcon#end of sib2, iclass 11, count 0 2006.168.07:31:08.50#ibcon#*after write, iclass 11, count 0 2006.168.07:31:08.50#ibcon#*before return 0, iclass 11, count 0 2006.168.07:31:08.50#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.168.07:31:08.50#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.168.07:31:08.50#ibcon#about to clear, iclass 11 cls_cnt 0 2006.168.07:31:08.50#ibcon#cleared, iclass 11 cls_cnt 0 2006.168.07:31:08.50$vc4f8/va=5,7 2006.168.07:31:08.50#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.168.07:31:08.50#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.168.07:31:08.50#ibcon#ireg 11 cls_cnt 2 2006.168.07:31:08.50#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.168.07:31:08.56#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.168.07:31:08.56#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.168.07:31:08.56#ibcon#enter wrdev, iclass 13, count 2 2006.168.07:31:08.56#ibcon#first serial, iclass 13, count 2 2006.168.07:31:08.56#ibcon#enter sib2, iclass 13, count 2 2006.168.07:31:08.56#ibcon#flushed, iclass 13, count 2 2006.168.07:31:08.56#ibcon#about to write, iclass 13, count 2 2006.168.07:31:08.56#ibcon#wrote, iclass 13, count 2 2006.168.07:31:08.56#ibcon#about to read 3, iclass 13, count 2 2006.168.07:31:08.59#ibcon#read 3, iclass 13, count 2 2006.168.07:31:08.59#ibcon#about to read 4, iclass 13, count 2 2006.168.07:31:08.59#ibcon#read 4, iclass 13, count 2 2006.168.07:31:08.59#ibcon#about to read 5, iclass 13, count 2 2006.168.07:31:08.59#ibcon#read 5, iclass 13, count 2 2006.168.07:31:08.59#ibcon#about to read 6, iclass 13, count 2 2006.168.07:31:08.59#ibcon#read 6, iclass 13, count 2 2006.168.07:31:08.59#ibcon#end of sib2, iclass 13, count 2 2006.168.07:31:08.59#ibcon#*mode == 0, iclass 13, count 2 2006.168.07:31:08.59#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.168.07:31:08.59#ibcon#[25=AT05-07\r\n] 2006.168.07:31:08.59#ibcon#*before write, iclass 13, count 2 2006.168.07:31:08.59#ibcon#enter sib2, iclass 13, count 2 2006.168.07:31:08.59#ibcon#flushed, iclass 13, count 2 2006.168.07:31:08.59#ibcon#about to write, iclass 13, count 2 2006.168.07:31:08.59#ibcon#wrote, iclass 13, count 2 2006.168.07:31:08.59#ibcon#about to read 3, iclass 13, count 2 2006.168.07:31:08.62#ibcon#read 3, iclass 13, count 2 2006.168.07:31:08.62#ibcon#about to read 4, iclass 13, count 2 2006.168.07:31:08.62#ibcon#read 4, iclass 13, count 2 2006.168.07:31:08.62#ibcon#about to read 5, iclass 13, count 2 2006.168.07:31:08.62#ibcon#read 5, iclass 13, count 2 2006.168.07:31:08.62#ibcon#about to read 6, iclass 13, count 2 2006.168.07:31:08.62#ibcon#read 6, iclass 13, count 2 2006.168.07:31:08.62#ibcon#end of sib2, iclass 13, count 2 2006.168.07:31:08.62#ibcon#*after write, iclass 13, count 2 2006.168.07:31:08.62#ibcon#*before return 0, iclass 13, count 2 2006.168.07:31:08.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.168.07:31:08.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.168.07:31:08.62#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.168.07:31:08.62#ibcon#ireg 7 cls_cnt 0 2006.168.07:31:08.62#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.168.07:31:08.74#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.168.07:31:08.74#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.168.07:31:08.74#ibcon#enter wrdev, iclass 13, count 0 2006.168.07:31:08.74#ibcon#first serial, iclass 13, count 0 2006.168.07:31:08.74#ibcon#enter sib2, iclass 13, count 0 2006.168.07:31:08.74#ibcon#flushed, iclass 13, count 0 2006.168.07:31:08.74#ibcon#about to write, iclass 13, count 0 2006.168.07:31:08.74#ibcon#wrote, iclass 13, count 0 2006.168.07:31:08.74#ibcon#about to read 3, iclass 13, count 0 2006.168.07:31:08.76#ibcon#read 3, iclass 13, count 0 2006.168.07:31:08.76#ibcon#about to read 4, iclass 13, count 0 2006.168.07:31:08.76#ibcon#read 4, iclass 13, count 0 2006.168.07:31:08.76#ibcon#about to read 5, iclass 13, count 0 2006.168.07:31:08.76#ibcon#read 5, iclass 13, count 0 2006.168.07:31:08.76#ibcon#about to read 6, iclass 13, count 0 2006.168.07:31:08.76#ibcon#read 6, iclass 13, count 0 2006.168.07:31:08.76#ibcon#end of sib2, iclass 13, count 0 2006.168.07:31:08.76#ibcon#*mode == 0, iclass 13, count 0 2006.168.07:31:08.76#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.168.07:31:08.76#ibcon#[25=USB\r\n] 2006.168.07:31:08.76#ibcon#*before write, iclass 13, count 0 2006.168.07:31:08.76#ibcon#enter sib2, iclass 13, count 0 2006.168.07:31:08.76#ibcon#flushed, iclass 13, count 0 2006.168.07:31:08.76#ibcon#about to write, iclass 13, count 0 2006.168.07:31:08.76#ibcon#wrote, iclass 13, count 0 2006.168.07:31:08.76#ibcon#about to read 3, iclass 13, count 0 2006.168.07:31:08.79#ibcon#read 3, iclass 13, count 0 2006.168.07:31:08.79#ibcon#about to read 4, iclass 13, count 0 2006.168.07:31:08.79#ibcon#read 4, iclass 13, count 0 2006.168.07:31:08.79#ibcon#about to read 5, iclass 13, count 0 2006.168.07:31:08.79#ibcon#read 5, iclass 13, count 0 2006.168.07:31:08.79#ibcon#about to read 6, iclass 13, count 0 2006.168.07:31:08.79#ibcon#read 6, iclass 13, count 0 2006.168.07:31:08.79#ibcon#end of sib2, iclass 13, count 0 2006.168.07:31:08.79#ibcon#*after write, iclass 13, count 0 2006.168.07:31:08.79#ibcon#*before return 0, iclass 13, count 0 2006.168.07:31:08.79#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.168.07:31:08.79#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.168.07:31:08.79#ibcon#about to clear, iclass 13 cls_cnt 0 2006.168.07:31:08.79#ibcon#cleared, iclass 13 cls_cnt 0 2006.168.07:31:08.79$vc4f8/valo=6,772.99 2006.168.07:31:08.79#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.168.07:31:08.79#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.168.07:31:08.79#ibcon#ireg 17 cls_cnt 0 2006.168.07:31:08.79#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:31:08.79#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:31:08.79#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:31:08.79#ibcon#enter wrdev, iclass 15, count 0 2006.168.07:31:08.79#ibcon#first serial, iclass 15, count 0 2006.168.07:31:08.79#ibcon#enter sib2, iclass 15, count 0 2006.168.07:31:08.79#ibcon#flushed, iclass 15, count 0 2006.168.07:31:08.79#ibcon#about to write, iclass 15, count 0 2006.168.07:31:08.79#ibcon#wrote, iclass 15, count 0 2006.168.07:31:08.79#ibcon#about to read 3, iclass 15, count 0 2006.168.07:31:08.81#ibcon#read 3, iclass 15, count 0 2006.168.07:31:08.81#ibcon#about to read 4, iclass 15, count 0 2006.168.07:31:08.81#ibcon#read 4, iclass 15, count 0 2006.168.07:31:08.81#ibcon#about to read 5, iclass 15, count 0 2006.168.07:31:08.81#ibcon#read 5, iclass 15, count 0 2006.168.07:31:08.81#ibcon#about to read 6, iclass 15, count 0 2006.168.07:31:08.81#ibcon#read 6, iclass 15, count 0 2006.168.07:31:08.81#ibcon#end of sib2, iclass 15, count 0 2006.168.07:31:08.81#ibcon#*mode == 0, iclass 15, count 0 2006.168.07:31:08.81#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.168.07:31:08.81#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.07:31:08.81#ibcon#*before write, iclass 15, count 0 2006.168.07:31:08.81#ibcon#enter sib2, iclass 15, count 0 2006.168.07:31:08.81#ibcon#flushed, iclass 15, count 0 2006.168.07:31:08.81#ibcon#about to write, iclass 15, count 0 2006.168.07:31:08.81#ibcon#wrote, iclass 15, count 0 2006.168.07:31:08.81#ibcon#about to read 3, iclass 15, count 0 2006.168.07:31:08.85#ibcon#read 3, iclass 15, count 0 2006.168.07:31:08.85#ibcon#about to read 4, iclass 15, count 0 2006.168.07:31:08.85#ibcon#read 4, iclass 15, count 0 2006.168.07:31:08.85#ibcon#about to read 5, iclass 15, count 0 2006.168.07:31:08.85#ibcon#read 5, iclass 15, count 0 2006.168.07:31:08.85#ibcon#about to read 6, iclass 15, count 0 2006.168.07:31:08.85#ibcon#read 6, iclass 15, count 0 2006.168.07:31:08.85#ibcon#end of sib2, iclass 15, count 0 2006.168.07:31:08.85#ibcon#*after write, iclass 15, count 0 2006.168.07:31:08.85#ibcon#*before return 0, iclass 15, count 0 2006.168.07:31:08.85#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:31:08.85#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:31:08.85#ibcon#about to clear, iclass 15 cls_cnt 0 2006.168.07:31:08.85#ibcon#cleared, iclass 15 cls_cnt 0 2006.168.07:31:08.85$vc4f8/va=6,6 2006.168.07:31:08.85#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.168.07:31:08.85#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.168.07:31:08.85#ibcon#ireg 11 cls_cnt 2 2006.168.07:31:08.85#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.168.07:31:08.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.168.07:31:08.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.168.07:31:08.91#ibcon#enter wrdev, iclass 17, count 2 2006.168.07:31:08.91#ibcon#first serial, iclass 17, count 2 2006.168.07:31:08.91#ibcon#enter sib2, iclass 17, count 2 2006.168.07:31:08.91#ibcon#flushed, iclass 17, count 2 2006.168.07:31:08.91#ibcon#about to write, iclass 17, count 2 2006.168.07:31:08.91#ibcon#wrote, iclass 17, count 2 2006.168.07:31:08.91#ibcon#about to read 3, iclass 17, count 2 2006.168.07:31:08.93#ibcon#read 3, iclass 17, count 2 2006.168.07:31:08.93#ibcon#about to read 4, iclass 17, count 2 2006.168.07:31:08.93#ibcon#read 4, iclass 17, count 2 2006.168.07:31:08.93#ibcon#about to read 5, iclass 17, count 2 2006.168.07:31:08.93#ibcon#read 5, iclass 17, count 2 2006.168.07:31:08.93#ibcon#about to read 6, iclass 17, count 2 2006.168.07:31:08.93#ibcon#read 6, iclass 17, count 2 2006.168.07:31:08.93#ibcon#end of sib2, iclass 17, count 2 2006.168.07:31:08.93#ibcon#*mode == 0, iclass 17, count 2 2006.168.07:31:08.93#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.168.07:31:08.93#ibcon#[25=AT06-06\r\n] 2006.168.07:31:08.93#ibcon#*before write, iclass 17, count 2 2006.168.07:31:08.93#ibcon#enter sib2, iclass 17, count 2 2006.168.07:31:08.93#ibcon#flushed, iclass 17, count 2 2006.168.07:31:08.93#ibcon#about to write, iclass 17, count 2 2006.168.07:31:08.93#ibcon#wrote, iclass 17, count 2 2006.168.07:31:08.93#ibcon#about to read 3, iclass 17, count 2 2006.168.07:31:08.96#ibcon#read 3, iclass 17, count 2 2006.168.07:31:08.96#ibcon#about to read 4, iclass 17, count 2 2006.168.07:31:08.96#ibcon#read 4, iclass 17, count 2 2006.168.07:31:08.96#ibcon#about to read 5, iclass 17, count 2 2006.168.07:31:08.96#ibcon#read 5, iclass 17, count 2 2006.168.07:31:08.96#ibcon#about to read 6, iclass 17, count 2 2006.168.07:31:08.96#ibcon#read 6, iclass 17, count 2 2006.168.07:31:08.96#ibcon#end of sib2, iclass 17, count 2 2006.168.07:31:08.96#ibcon#*after write, iclass 17, count 2 2006.168.07:31:08.96#ibcon#*before return 0, iclass 17, count 2 2006.168.07:31:08.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.168.07:31:08.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.168.07:31:08.96#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.168.07:31:08.96#ibcon#ireg 7 cls_cnt 0 2006.168.07:31:08.96#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.168.07:31:09.08#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.168.07:31:09.08#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.168.07:31:09.08#ibcon#enter wrdev, iclass 17, count 0 2006.168.07:31:09.08#ibcon#first serial, iclass 17, count 0 2006.168.07:31:09.08#ibcon#enter sib2, iclass 17, count 0 2006.168.07:31:09.08#ibcon#flushed, iclass 17, count 0 2006.168.07:31:09.08#ibcon#about to write, iclass 17, count 0 2006.168.07:31:09.08#ibcon#wrote, iclass 17, count 0 2006.168.07:31:09.08#ibcon#about to read 3, iclass 17, count 0 2006.168.07:31:09.10#ibcon#read 3, iclass 17, count 0 2006.168.07:31:09.10#ibcon#about to read 4, iclass 17, count 0 2006.168.07:31:09.10#ibcon#read 4, iclass 17, count 0 2006.168.07:31:09.10#ibcon#about to read 5, iclass 17, count 0 2006.168.07:31:09.10#ibcon#read 5, iclass 17, count 0 2006.168.07:31:09.10#ibcon#about to read 6, iclass 17, count 0 2006.168.07:31:09.10#ibcon#read 6, iclass 17, count 0 2006.168.07:31:09.10#ibcon#end of sib2, iclass 17, count 0 2006.168.07:31:09.10#ibcon#*mode == 0, iclass 17, count 0 2006.168.07:31:09.10#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.168.07:31:09.10#ibcon#[25=USB\r\n] 2006.168.07:31:09.10#ibcon#*before write, iclass 17, count 0 2006.168.07:31:09.10#ibcon#enter sib2, iclass 17, count 0 2006.168.07:31:09.10#ibcon#flushed, iclass 17, count 0 2006.168.07:31:09.10#ibcon#about to write, iclass 17, count 0 2006.168.07:31:09.10#ibcon#wrote, iclass 17, count 0 2006.168.07:31:09.10#ibcon#about to read 3, iclass 17, count 0 2006.168.07:31:09.13#ibcon#read 3, iclass 17, count 0 2006.168.07:31:09.13#ibcon#about to read 4, iclass 17, count 0 2006.168.07:31:09.13#ibcon#read 4, iclass 17, count 0 2006.168.07:31:09.13#ibcon#about to read 5, iclass 17, count 0 2006.168.07:31:09.13#ibcon#read 5, iclass 17, count 0 2006.168.07:31:09.13#ibcon#about to read 6, iclass 17, count 0 2006.168.07:31:09.13#ibcon#read 6, iclass 17, count 0 2006.168.07:31:09.13#ibcon#end of sib2, iclass 17, count 0 2006.168.07:31:09.13#ibcon#*after write, iclass 17, count 0 2006.168.07:31:09.13#ibcon#*before return 0, iclass 17, count 0 2006.168.07:31:09.13#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.168.07:31:09.13#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.168.07:31:09.13#ibcon#about to clear, iclass 17 cls_cnt 0 2006.168.07:31:09.13#ibcon#cleared, iclass 17 cls_cnt 0 2006.168.07:31:09.13$vc4f8/valo=7,832.99 2006.168.07:31:09.13#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.168.07:31:09.13#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.168.07:31:09.13#ibcon#ireg 17 cls_cnt 0 2006.168.07:31:09.13#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:31:09.13#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:31:09.13#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:31:09.13#ibcon#enter wrdev, iclass 19, count 0 2006.168.07:31:09.13#ibcon#first serial, iclass 19, count 0 2006.168.07:31:09.13#ibcon#enter sib2, iclass 19, count 0 2006.168.07:31:09.13#ibcon#flushed, iclass 19, count 0 2006.168.07:31:09.13#ibcon#about to write, iclass 19, count 0 2006.168.07:31:09.13#ibcon#wrote, iclass 19, count 0 2006.168.07:31:09.13#ibcon#about to read 3, iclass 19, count 0 2006.168.07:31:09.15#ibcon#read 3, iclass 19, count 0 2006.168.07:31:09.15#ibcon#about to read 4, iclass 19, count 0 2006.168.07:31:09.15#ibcon#read 4, iclass 19, count 0 2006.168.07:31:09.15#ibcon#about to read 5, iclass 19, count 0 2006.168.07:31:09.15#ibcon#read 5, iclass 19, count 0 2006.168.07:31:09.15#ibcon#about to read 6, iclass 19, count 0 2006.168.07:31:09.15#ibcon#read 6, iclass 19, count 0 2006.168.07:31:09.15#ibcon#end of sib2, iclass 19, count 0 2006.168.07:31:09.15#ibcon#*mode == 0, iclass 19, count 0 2006.168.07:31:09.15#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.168.07:31:09.15#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.07:31:09.15#ibcon#*before write, iclass 19, count 0 2006.168.07:31:09.15#ibcon#enter sib2, iclass 19, count 0 2006.168.07:31:09.15#ibcon#flushed, iclass 19, count 0 2006.168.07:31:09.15#ibcon#about to write, iclass 19, count 0 2006.168.07:31:09.15#ibcon#wrote, iclass 19, count 0 2006.168.07:31:09.15#ibcon#about to read 3, iclass 19, count 0 2006.168.07:31:09.19#ibcon#read 3, iclass 19, count 0 2006.168.07:31:09.19#ibcon#about to read 4, iclass 19, count 0 2006.168.07:31:09.19#ibcon#read 4, iclass 19, count 0 2006.168.07:31:09.19#ibcon#about to read 5, iclass 19, count 0 2006.168.07:31:09.19#ibcon#read 5, iclass 19, count 0 2006.168.07:31:09.19#ibcon#about to read 6, iclass 19, count 0 2006.168.07:31:09.19#ibcon#read 6, iclass 19, count 0 2006.168.07:31:09.19#ibcon#end of sib2, iclass 19, count 0 2006.168.07:31:09.19#ibcon#*after write, iclass 19, count 0 2006.168.07:31:09.19#ibcon#*before return 0, iclass 19, count 0 2006.168.07:31:09.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:31:09.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:31:09.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.168.07:31:09.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.168.07:31:09.19$vc4f8/va=7,6 2006.168.07:31:09.19#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.168.07:31:09.19#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.168.07:31:09.19#ibcon#ireg 11 cls_cnt 2 2006.168.07:31:09.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.168.07:31:09.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.168.07:31:09.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.168.07:31:09.25#ibcon#enter wrdev, iclass 21, count 2 2006.168.07:31:09.25#ibcon#first serial, iclass 21, count 2 2006.168.07:31:09.25#ibcon#enter sib2, iclass 21, count 2 2006.168.07:31:09.25#ibcon#flushed, iclass 21, count 2 2006.168.07:31:09.25#ibcon#about to write, iclass 21, count 2 2006.168.07:31:09.25#ibcon#wrote, iclass 21, count 2 2006.168.07:31:09.25#ibcon#about to read 3, iclass 21, count 2 2006.168.07:31:09.27#ibcon#read 3, iclass 21, count 2 2006.168.07:31:09.27#ibcon#about to read 4, iclass 21, count 2 2006.168.07:31:09.27#ibcon#read 4, iclass 21, count 2 2006.168.07:31:09.27#ibcon#about to read 5, iclass 21, count 2 2006.168.07:31:09.27#ibcon#read 5, iclass 21, count 2 2006.168.07:31:09.27#ibcon#about to read 6, iclass 21, count 2 2006.168.07:31:09.27#ibcon#read 6, iclass 21, count 2 2006.168.07:31:09.27#ibcon#end of sib2, iclass 21, count 2 2006.168.07:31:09.27#ibcon#*mode == 0, iclass 21, count 2 2006.168.07:31:09.27#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.168.07:31:09.27#ibcon#[25=AT07-06\r\n] 2006.168.07:31:09.27#ibcon#*before write, iclass 21, count 2 2006.168.07:31:09.27#ibcon#enter sib2, iclass 21, count 2 2006.168.07:31:09.27#ibcon#flushed, iclass 21, count 2 2006.168.07:31:09.27#ibcon#about to write, iclass 21, count 2 2006.168.07:31:09.27#ibcon#wrote, iclass 21, count 2 2006.168.07:31:09.27#ibcon#about to read 3, iclass 21, count 2 2006.168.07:31:09.30#ibcon#read 3, iclass 21, count 2 2006.168.07:31:09.30#ibcon#about to read 4, iclass 21, count 2 2006.168.07:31:09.30#ibcon#read 4, iclass 21, count 2 2006.168.07:31:09.30#ibcon#about to read 5, iclass 21, count 2 2006.168.07:31:09.30#ibcon#read 5, iclass 21, count 2 2006.168.07:31:09.30#ibcon#about to read 6, iclass 21, count 2 2006.168.07:31:09.30#ibcon#read 6, iclass 21, count 2 2006.168.07:31:09.30#ibcon#end of sib2, iclass 21, count 2 2006.168.07:31:09.30#ibcon#*after write, iclass 21, count 2 2006.168.07:31:09.30#ibcon#*before return 0, iclass 21, count 2 2006.168.07:31:09.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.168.07:31:09.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.168.07:31:09.30#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.168.07:31:09.30#ibcon#ireg 7 cls_cnt 0 2006.168.07:31:09.30#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.168.07:31:09.42#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.168.07:31:09.42#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.168.07:31:09.42#ibcon#enter wrdev, iclass 21, count 0 2006.168.07:31:09.42#ibcon#first serial, iclass 21, count 0 2006.168.07:31:09.42#ibcon#enter sib2, iclass 21, count 0 2006.168.07:31:09.42#ibcon#flushed, iclass 21, count 0 2006.168.07:31:09.42#ibcon#about to write, iclass 21, count 0 2006.168.07:31:09.42#ibcon#wrote, iclass 21, count 0 2006.168.07:31:09.42#ibcon#about to read 3, iclass 21, count 0 2006.168.07:31:09.44#ibcon#read 3, iclass 21, count 0 2006.168.07:31:09.44#ibcon#about to read 4, iclass 21, count 0 2006.168.07:31:09.44#ibcon#read 4, iclass 21, count 0 2006.168.07:31:09.44#ibcon#about to read 5, iclass 21, count 0 2006.168.07:31:09.44#ibcon#read 5, iclass 21, count 0 2006.168.07:31:09.44#ibcon#about to read 6, iclass 21, count 0 2006.168.07:31:09.44#ibcon#read 6, iclass 21, count 0 2006.168.07:31:09.44#ibcon#end of sib2, iclass 21, count 0 2006.168.07:31:09.44#ibcon#*mode == 0, iclass 21, count 0 2006.168.07:31:09.44#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.168.07:31:09.44#ibcon#[25=USB\r\n] 2006.168.07:31:09.44#ibcon#*before write, iclass 21, count 0 2006.168.07:31:09.44#ibcon#enter sib2, iclass 21, count 0 2006.168.07:31:09.44#ibcon#flushed, iclass 21, count 0 2006.168.07:31:09.44#ibcon#about to write, iclass 21, count 0 2006.168.07:31:09.44#ibcon#wrote, iclass 21, count 0 2006.168.07:31:09.44#ibcon#about to read 3, iclass 21, count 0 2006.168.07:31:09.47#ibcon#read 3, iclass 21, count 0 2006.168.07:31:09.47#ibcon#about to read 4, iclass 21, count 0 2006.168.07:31:09.47#ibcon#read 4, iclass 21, count 0 2006.168.07:31:09.47#ibcon#about to read 5, iclass 21, count 0 2006.168.07:31:09.47#ibcon#read 5, iclass 21, count 0 2006.168.07:31:09.47#ibcon#about to read 6, iclass 21, count 0 2006.168.07:31:09.47#ibcon#read 6, iclass 21, count 0 2006.168.07:31:09.47#ibcon#end of sib2, iclass 21, count 0 2006.168.07:31:09.47#ibcon#*after write, iclass 21, count 0 2006.168.07:31:09.47#ibcon#*before return 0, iclass 21, count 0 2006.168.07:31:09.47#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.168.07:31:09.47#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.168.07:31:09.47#ibcon#about to clear, iclass 21 cls_cnt 0 2006.168.07:31:09.47#ibcon#cleared, iclass 21 cls_cnt 0 2006.168.07:31:09.47$vc4f8/valo=8,852.99 2006.168.07:31:09.47#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.168.07:31:09.47#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.168.07:31:09.47#ibcon#ireg 17 cls_cnt 0 2006.168.07:31:09.47#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:31:09.47#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:31:09.47#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:31:09.47#ibcon#enter wrdev, iclass 23, count 0 2006.168.07:31:09.47#ibcon#first serial, iclass 23, count 0 2006.168.07:31:09.47#ibcon#enter sib2, iclass 23, count 0 2006.168.07:31:09.47#ibcon#flushed, iclass 23, count 0 2006.168.07:31:09.47#ibcon#about to write, iclass 23, count 0 2006.168.07:31:09.47#ibcon#wrote, iclass 23, count 0 2006.168.07:31:09.47#ibcon#about to read 3, iclass 23, count 0 2006.168.07:31:09.49#ibcon#read 3, iclass 23, count 0 2006.168.07:31:09.49#ibcon#about to read 4, iclass 23, count 0 2006.168.07:31:09.49#ibcon#read 4, iclass 23, count 0 2006.168.07:31:09.49#ibcon#about to read 5, iclass 23, count 0 2006.168.07:31:09.49#ibcon#read 5, iclass 23, count 0 2006.168.07:31:09.49#ibcon#about to read 6, iclass 23, count 0 2006.168.07:31:09.49#ibcon#read 6, iclass 23, count 0 2006.168.07:31:09.49#ibcon#end of sib2, iclass 23, count 0 2006.168.07:31:09.49#ibcon#*mode == 0, iclass 23, count 0 2006.168.07:31:09.49#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.168.07:31:09.49#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.07:31:09.49#ibcon#*before write, iclass 23, count 0 2006.168.07:31:09.49#ibcon#enter sib2, iclass 23, count 0 2006.168.07:31:09.49#ibcon#flushed, iclass 23, count 0 2006.168.07:31:09.49#ibcon#about to write, iclass 23, count 0 2006.168.07:31:09.49#ibcon#wrote, iclass 23, count 0 2006.168.07:31:09.49#ibcon#about to read 3, iclass 23, count 0 2006.168.07:31:09.53#ibcon#read 3, iclass 23, count 0 2006.168.07:31:09.53#ibcon#about to read 4, iclass 23, count 0 2006.168.07:31:09.53#ibcon#read 4, iclass 23, count 0 2006.168.07:31:09.53#ibcon#about to read 5, iclass 23, count 0 2006.168.07:31:09.53#ibcon#read 5, iclass 23, count 0 2006.168.07:31:09.53#ibcon#about to read 6, iclass 23, count 0 2006.168.07:31:09.53#ibcon#read 6, iclass 23, count 0 2006.168.07:31:09.53#ibcon#end of sib2, iclass 23, count 0 2006.168.07:31:09.53#ibcon#*after write, iclass 23, count 0 2006.168.07:31:09.53#ibcon#*before return 0, iclass 23, count 0 2006.168.07:31:09.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:31:09.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:31:09.53#ibcon#about to clear, iclass 23 cls_cnt 0 2006.168.07:31:09.53#ibcon#cleared, iclass 23 cls_cnt 0 2006.168.07:31:09.53$vc4f8/va=8,7 2006.168.07:31:09.53#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.168.07:31:09.53#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.168.07:31:09.53#ibcon#ireg 11 cls_cnt 2 2006.168.07:31:09.53#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.168.07:31:09.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.168.07:31:09.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.168.07:31:09.59#ibcon#enter wrdev, iclass 25, count 2 2006.168.07:31:09.59#ibcon#first serial, iclass 25, count 2 2006.168.07:31:09.59#ibcon#enter sib2, iclass 25, count 2 2006.168.07:31:09.59#ibcon#flushed, iclass 25, count 2 2006.168.07:31:09.59#ibcon#about to write, iclass 25, count 2 2006.168.07:31:09.59#ibcon#wrote, iclass 25, count 2 2006.168.07:31:09.59#ibcon#about to read 3, iclass 25, count 2 2006.168.07:31:09.61#ibcon#read 3, iclass 25, count 2 2006.168.07:31:09.61#ibcon#about to read 4, iclass 25, count 2 2006.168.07:31:09.61#ibcon#read 4, iclass 25, count 2 2006.168.07:31:09.61#ibcon#about to read 5, iclass 25, count 2 2006.168.07:31:09.61#ibcon#read 5, iclass 25, count 2 2006.168.07:31:09.61#ibcon#about to read 6, iclass 25, count 2 2006.168.07:31:09.61#ibcon#read 6, iclass 25, count 2 2006.168.07:31:09.61#ibcon#end of sib2, iclass 25, count 2 2006.168.07:31:09.61#ibcon#*mode == 0, iclass 25, count 2 2006.168.07:31:09.61#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.168.07:31:09.61#ibcon#[25=AT08-07\r\n] 2006.168.07:31:09.61#ibcon#*before write, iclass 25, count 2 2006.168.07:31:09.61#ibcon#enter sib2, iclass 25, count 2 2006.168.07:31:09.61#ibcon#flushed, iclass 25, count 2 2006.168.07:31:09.61#ibcon#about to write, iclass 25, count 2 2006.168.07:31:09.61#ibcon#wrote, iclass 25, count 2 2006.168.07:31:09.61#ibcon#about to read 3, iclass 25, count 2 2006.168.07:31:09.64#ibcon#read 3, iclass 25, count 2 2006.168.07:31:09.64#ibcon#about to read 4, iclass 25, count 2 2006.168.07:31:09.64#ibcon#read 4, iclass 25, count 2 2006.168.07:31:09.64#ibcon#about to read 5, iclass 25, count 2 2006.168.07:31:09.64#ibcon#read 5, iclass 25, count 2 2006.168.07:31:09.64#ibcon#about to read 6, iclass 25, count 2 2006.168.07:31:09.64#ibcon#read 6, iclass 25, count 2 2006.168.07:31:09.64#ibcon#end of sib2, iclass 25, count 2 2006.168.07:31:09.64#ibcon#*after write, iclass 25, count 2 2006.168.07:31:09.64#ibcon#*before return 0, iclass 25, count 2 2006.168.07:31:09.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.168.07:31:09.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.168.07:31:09.64#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.168.07:31:09.64#ibcon#ireg 7 cls_cnt 0 2006.168.07:31:09.64#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.168.07:31:09.76#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.168.07:31:09.76#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.168.07:31:09.76#ibcon#enter wrdev, iclass 25, count 0 2006.168.07:31:09.76#ibcon#first serial, iclass 25, count 0 2006.168.07:31:09.76#ibcon#enter sib2, iclass 25, count 0 2006.168.07:31:09.76#ibcon#flushed, iclass 25, count 0 2006.168.07:31:09.76#ibcon#about to write, iclass 25, count 0 2006.168.07:31:09.76#ibcon#wrote, iclass 25, count 0 2006.168.07:31:09.76#ibcon#about to read 3, iclass 25, count 0 2006.168.07:31:09.78#ibcon#read 3, iclass 25, count 0 2006.168.07:31:09.78#ibcon#about to read 4, iclass 25, count 0 2006.168.07:31:09.78#ibcon#read 4, iclass 25, count 0 2006.168.07:31:09.78#ibcon#about to read 5, iclass 25, count 0 2006.168.07:31:09.78#ibcon#read 5, iclass 25, count 0 2006.168.07:31:09.78#ibcon#about to read 6, iclass 25, count 0 2006.168.07:31:09.78#ibcon#read 6, iclass 25, count 0 2006.168.07:31:09.78#ibcon#end of sib2, iclass 25, count 0 2006.168.07:31:09.78#ibcon#*mode == 0, iclass 25, count 0 2006.168.07:31:09.78#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.168.07:31:09.78#ibcon#[25=USB\r\n] 2006.168.07:31:09.78#ibcon#*before write, iclass 25, count 0 2006.168.07:31:09.78#ibcon#enter sib2, iclass 25, count 0 2006.168.07:31:09.78#ibcon#flushed, iclass 25, count 0 2006.168.07:31:09.78#ibcon#about to write, iclass 25, count 0 2006.168.07:31:09.78#ibcon#wrote, iclass 25, count 0 2006.168.07:31:09.78#ibcon#about to read 3, iclass 25, count 0 2006.168.07:31:09.81#ibcon#read 3, iclass 25, count 0 2006.168.07:31:09.81#ibcon#about to read 4, iclass 25, count 0 2006.168.07:31:09.81#ibcon#read 4, iclass 25, count 0 2006.168.07:31:09.81#ibcon#about to read 5, iclass 25, count 0 2006.168.07:31:09.81#ibcon#read 5, iclass 25, count 0 2006.168.07:31:09.81#ibcon#about to read 6, iclass 25, count 0 2006.168.07:31:09.81#ibcon#read 6, iclass 25, count 0 2006.168.07:31:09.81#ibcon#end of sib2, iclass 25, count 0 2006.168.07:31:09.81#ibcon#*after write, iclass 25, count 0 2006.168.07:31:09.81#ibcon#*before return 0, iclass 25, count 0 2006.168.07:31:09.81#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.168.07:31:09.81#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.168.07:31:09.81#ibcon#about to clear, iclass 25 cls_cnt 0 2006.168.07:31:09.81#ibcon#cleared, iclass 25 cls_cnt 0 2006.168.07:31:09.81$vc4f8/vblo=1,632.99 2006.168.07:31:09.81#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.168.07:31:09.81#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.168.07:31:09.81#ibcon#ireg 17 cls_cnt 0 2006.168.07:31:09.81#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.168.07:31:09.81#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.168.07:31:09.81#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.168.07:31:09.81#ibcon#enter wrdev, iclass 27, count 0 2006.168.07:31:09.81#ibcon#first serial, iclass 27, count 0 2006.168.07:31:09.81#ibcon#enter sib2, iclass 27, count 0 2006.168.07:31:09.81#ibcon#flushed, iclass 27, count 0 2006.168.07:31:09.81#ibcon#about to write, iclass 27, count 0 2006.168.07:31:09.81#ibcon#wrote, iclass 27, count 0 2006.168.07:31:09.81#ibcon#about to read 3, iclass 27, count 0 2006.168.07:31:09.83#ibcon#read 3, iclass 27, count 0 2006.168.07:31:09.83#ibcon#about to read 4, iclass 27, count 0 2006.168.07:31:09.83#ibcon#read 4, iclass 27, count 0 2006.168.07:31:09.83#ibcon#about to read 5, iclass 27, count 0 2006.168.07:31:09.83#ibcon#read 5, iclass 27, count 0 2006.168.07:31:09.83#ibcon#about to read 6, iclass 27, count 0 2006.168.07:31:09.83#ibcon#read 6, iclass 27, count 0 2006.168.07:31:09.83#ibcon#end of sib2, iclass 27, count 0 2006.168.07:31:09.83#ibcon#*mode == 0, iclass 27, count 0 2006.168.07:31:09.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.168.07:31:09.83#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.07:31:09.83#ibcon#*before write, iclass 27, count 0 2006.168.07:31:09.83#ibcon#enter sib2, iclass 27, count 0 2006.168.07:31:09.83#ibcon#flushed, iclass 27, count 0 2006.168.07:31:09.83#ibcon#about to write, iclass 27, count 0 2006.168.07:31:09.83#ibcon#wrote, iclass 27, count 0 2006.168.07:31:09.83#ibcon#about to read 3, iclass 27, count 0 2006.168.07:31:09.87#ibcon#read 3, iclass 27, count 0 2006.168.07:31:09.87#ibcon#about to read 4, iclass 27, count 0 2006.168.07:31:09.87#ibcon#read 4, iclass 27, count 0 2006.168.07:31:09.87#ibcon#about to read 5, iclass 27, count 0 2006.168.07:31:09.87#ibcon#read 5, iclass 27, count 0 2006.168.07:31:09.87#ibcon#about to read 6, iclass 27, count 0 2006.168.07:31:09.87#ibcon#read 6, iclass 27, count 0 2006.168.07:31:09.87#ibcon#end of sib2, iclass 27, count 0 2006.168.07:31:09.87#ibcon#*after write, iclass 27, count 0 2006.168.07:31:09.87#ibcon#*before return 0, iclass 27, count 0 2006.168.07:31:09.87#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.168.07:31:09.87#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.168.07:31:09.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.168.07:31:09.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.168.07:31:09.87$vc4f8/vb=1,4 2006.168.07:31:09.87#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.168.07:31:09.87#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.168.07:31:09.87#ibcon#ireg 11 cls_cnt 2 2006.168.07:31:09.87#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.168.07:31:09.87#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.168.07:31:09.87#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.168.07:31:09.87#ibcon#enter wrdev, iclass 29, count 2 2006.168.07:31:09.87#ibcon#first serial, iclass 29, count 2 2006.168.07:31:09.87#ibcon#enter sib2, iclass 29, count 2 2006.168.07:31:09.87#ibcon#flushed, iclass 29, count 2 2006.168.07:31:09.87#ibcon#about to write, iclass 29, count 2 2006.168.07:31:09.87#ibcon#wrote, iclass 29, count 2 2006.168.07:31:09.87#ibcon#about to read 3, iclass 29, count 2 2006.168.07:31:09.89#ibcon#read 3, iclass 29, count 2 2006.168.07:31:09.89#ibcon#about to read 4, iclass 29, count 2 2006.168.07:31:09.89#ibcon#read 4, iclass 29, count 2 2006.168.07:31:09.89#ibcon#about to read 5, iclass 29, count 2 2006.168.07:31:09.89#ibcon#read 5, iclass 29, count 2 2006.168.07:31:09.89#ibcon#about to read 6, iclass 29, count 2 2006.168.07:31:09.89#ibcon#read 6, iclass 29, count 2 2006.168.07:31:09.89#ibcon#end of sib2, iclass 29, count 2 2006.168.07:31:09.89#ibcon#*mode == 0, iclass 29, count 2 2006.168.07:31:09.89#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.168.07:31:09.89#ibcon#[27=AT01-04\r\n] 2006.168.07:31:09.89#ibcon#*before write, iclass 29, count 2 2006.168.07:31:09.89#ibcon#enter sib2, iclass 29, count 2 2006.168.07:31:09.89#ibcon#flushed, iclass 29, count 2 2006.168.07:31:09.89#ibcon#about to write, iclass 29, count 2 2006.168.07:31:09.89#ibcon#wrote, iclass 29, count 2 2006.168.07:31:09.89#ibcon#about to read 3, iclass 29, count 2 2006.168.07:31:09.92#ibcon#read 3, iclass 29, count 2 2006.168.07:31:09.92#ibcon#about to read 4, iclass 29, count 2 2006.168.07:31:09.92#ibcon#read 4, iclass 29, count 2 2006.168.07:31:09.92#ibcon#about to read 5, iclass 29, count 2 2006.168.07:31:09.92#ibcon#read 5, iclass 29, count 2 2006.168.07:31:09.92#ibcon#about to read 6, iclass 29, count 2 2006.168.07:31:09.92#ibcon#read 6, iclass 29, count 2 2006.168.07:31:09.92#ibcon#end of sib2, iclass 29, count 2 2006.168.07:31:09.92#ibcon#*after write, iclass 29, count 2 2006.168.07:31:09.92#ibcon#*before return 0, iclass 29, count 2 2006.168.07:31:09.92#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.168.07:31:09.92#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.168.07:31:09.92#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.168.07:31:09.92#ibcon#ireg 7 cls_cnt 0 2006.168.07:31:09.92#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.168.07:31:10.04#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.168.07:31:10.04#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.168.07:31:10.04#ibcon#enter wrdev, iclass 29, count 0 2006.168.07:31:10.04#ibcon#first serial, iclass 29, count 0 2006.168.07:31:10.04#ibcon#enter sib2, iclass 29, count 0 2006.168.07:31:10.04#ibcon#flushed, iclass 29, count 0 2006.168.07:31:10.04#ibcon#about to write, iclass 29, count 0 2006.168.07:31:10.04#ibcon#wrote, iclass 29, count 0 2006.168.07:31:10.04#ibcon#about to read 3, iclass 29, count 0 2006.168.07:31:10.06#ibcon#read 3, iclass 29, count 0 2006.168.07:31:10.06#ibcon#about to read 4, iclass 29, count 0 2006.168.07:31:10.06#ibcon#read 4, iclass 29, count 0 2006.168.07:31:10.06#ibcon#about to read 5, iclass 29, count 0 2006.168.07:31:10.06#ibcon#read 5, iclass 29, count 0 2006.168.07:31:10.06#ibcon#about to read 6, iclass 29, count 0 2006.168.07:31:10.06#ibcon#read 6, iclass 29, count 0 2006.168.07:31:10.06#ibcon#end of sib2, iclass 29, count 0 2006.168.07:31:10.06#ibcon#*mode == 0, iclass 29, count 0 2006.168.07:31:10.06#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.168.07:31:10.06#ibcon#[27=USB\r\n] 2006.168.07:31:10.06#ibcon#*before write, iclass 29, count 0 2006.168.07:31:10.06#ibcon#enter sib2, iclass 29, count 0 2006.168.07:31:10.06#ibcon#flushed, iclass 29, count 0 2006.168.07:31:10.06#ibcon#about to write, iclass 29, count 0 2006.168.07:31:10.06#ibcon#wrote, iclass 29, count 0 2006.168.07:31:10.06#ibcon#about to read 3, iclass 29, count 0 2006.168.07:31:10.09#ibcon#read 3, iclass 29, count 0 2006.168.07:31:10.09#ibcon#about to read 4, iclass 29, count 0 2006.168.07:31:10.09#ibcon#read 4, iclass 29, count 0 2006.168.07:31:10.09#ibcon#about to read 5, iclass 29, count 0 2006.168.07:31:10.09#ibcon#read 5, iclass 29, count 0 2006.168.07:31:10.09#ibcon#about to read 6, iclass 29, count 0 2006.168.07:31:10.09#ibcon#read 6, iclass 29, count 0 2006.168.07:31:10.09#ibcon#end of sib2, iclass 29, count 0 2006.168.07:31:10.09#ibcon#*after write, iclass 29, count 0 2006.168.07:31:10.09#ibcon#*before return 0, iclass 29, count 0 2006.168.07:31:10.09#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.168.07:31:10.09#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.168.07:31:10.09#ibcon#about to clear, iclass 29 cls_cnt 0 2006.168.07:31:10.09#ibcon#cleared, iclass 29 cls_cnt 0 2006.168.07:31:10.09$vc4f8/vblo=2,640.99 2006.168.07:31:10.09#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.168.07:31:10.09#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.168.07:31:10.09#ibcon#ireg 17 cls_cnt 0 2006.168.07:31:10.09#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:31:10.09#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:31:10.09#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:31:10.09#ibcon#enter wrdev, iclass 31, count 0 2006.168.07:31:10.09#ibcon#first serial, iclass 31, count 0 2006.168.07:31:10.09#ibcon#enter sib2, iclass 31, count 0 2006.168.07:31:10.09#ibcon#flushed, iclass 31, count 0 2006.168.07:31:10.09#ibcon#about to write, iclass 31, count 0 2006.168.07:31:10.09#ibcon#wrote, iclass 31, count 0 2006.168.07:31:10.09#ibcon#about to read 3, iclass 31, count 0 2006.168.07:31:10.11#ibcon#read 3, iclass 31, count 0 2006.168.07:31:10.11#ibcon#about to read 4, iclass 31, count 0 2006.168.07:31:10.11#ibcon#read 4, iclass 31, count 0 2006.168.07:31:10.11#ibcon#about to read 5, iclass 31, count 0 2006.168.07:31:10.11#ibcon#read 5, iclass 31, count 0 2006.168.07:31:10.11#ibcon#about to read 6, iclass 31, count 0 2006.168.07:31:10.11#ibcon#read 6, iclass 31, count 0 2006.168.07:31:10.11#ibcon#end of sib2, iclass 31, count 0 2006.168.07:31:10.11#ibcon#*mode == 0, iclass 31, count 0 2006.168.07:31:10.11#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.168.07:31:10.11#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.07:31:10.11#ibcon#*before write, iclass 31, count 0 2006.168.07:31:10.11#ibcon#enter sib2, iclass 31, count 0 2006.168.07:31:10.11#ibcon#flushed, iclass 31, count 0 2006.168.07:31:10.11#ibcon#about to write, iclass 31, count 0 2006.168.07:31:10.11#ibcon#wrote, iclass 31, count 0 2006.168.07:31:10.11#ibcon#about to read 3, iclass 31, count 0 2006.168.07:31:10.15#ibcon#read 3, iclass 31, count 0 2006.168.07:31:10.16#ibcon#about to read 4, iclass 31, count 0 2006.168.07:31:10.16#ibcon#read 4, iclass 31, count 0 2006.168.07:31:10.16#ibcon#about to read 5, iclass 31, count 0 2006.168.07:31:10.16#ibcon#read 5, iclass 31, count 0 2006.168.07:31:10.16#ibcon#about to read 6, iclass 31, count 0 2006.168.07:31:10.16#ibcon#read 6, iclass 31, count 0 2006.168.07:31:10.16#ibcon#end of sib2, iclass 31, count 0 2006.168.07:31:10.16#ibcon#*after write, iclass 31, count 0 2006.168.07:31:10.16#ibcon#*before return 0, iclass 31, count 0 2006.168.07:31:10.16#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:31:10.16#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:31:10.16#ibcon#about to clear, iclass 31 cls_cnt 0 2006.168.07:31:10.16#ibcon#cleared, iclass 31 cls_cnt 0 2006.168.07:31:10.16$vc4f8/vb=2,4 2006.168.07:31:10.16#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.168.07:31:10.16#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.168.07:31:10.16#ibcon#ireg 11 cls_cnt 2 2006.168.07:31:10.16#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:31:10.20#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:31:10.20#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:31:10.20#ibcon#enter wrdev, iclass 33, count 2 2006.168.07:31:10.20#ibcon#first serial, iclass 33, count 2 2006.168.07:31:10.20#ibcon#enter sib2, iclass 33, count 2 2006.168.07:31:10.20#ibcon#flushed, iclass 33, count 2 2006.168.07:31:10.20#ibcon#about to write, iclass 33, count 2 2006.168.07:31:10.20#ibcon#wrote, iclass 33, count 2 2006.168.07:31:10.20#ibcon#about to read 3, iclass 33, count 2 2006.168.07:31:10.22#ibcon#read 3, iclass 33, count 2 2006.168.07:31:10.22#ibcon#about to read 4, iclass 33, count 2 2006.168.07:31:10.22#ibcon#read 4, iclass 33, count 2 2006.168.07:31:10.22#ibcon#about to read 5, iclass 33, count 2 2006.168.07:31:10.22#ibcon#read 5, iclass 33, count 2 2006.168.07:31:10.22#ibcon#about to read 6, iclass 33, count 2 2006.168.07:31:10.22#ibcon#read 6, iclass 33, count 2 2006.168.07:31:10.22#ibcon#end of sib2, iclass 33, count 2 2006.168.07:31:10.22#ibcon#*mode == 0, iclass 33, count 2 2006.168.07:31:10.22#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.168.07:31:10.22#ibcon#[27=AT02-04\r\n] 2006.168.07:31:10.22#ibcon#*before write, iclass 33, count 2 2006.168.07:31:10.22#ibcon#enter sib2, iclass 33, count 2 2006.168.07:31:10.22#ibcon#flushed, iclass 33, count 2 2006.168.07:31:10.22#ibcon#about to write, iclass 33, count 2 2006.168.07:31:10.22#ibcon#wrote, iclass 33, count 2 2006.168.07:31:10.22#ibcon#about to read 3, iclass 33, count 2 2006.168.07:31:10.25#ibcon#read 3, iclass 33, count 2 2006.168.07:31:10.25#ibcon#about to read 4, iclass 33, count 2 2006.168.07:31:10.25#ibcon#read 4, iclass 33, count 2 2006.168.07:31:10.25#ibcon#about to read 5, iclass 33, count 2 2006.168.07:31:10.25#ibcon#read 5, iclass 33, count 2 2006.168.07:31:10.25#ibcon#about to read 6, iclass 33, count 2 2006.168.07:31:10.25#ibcon#read 6, iclass 33, count 2 2006.168.07:31:10.25#ibcon#end of sib2, iclass 33, count 2 2006.168.07:31:10.25#ibcon#*after write, iclass 33, count 2 2006.168.07:31:10.25#ibcon#*before return 0, iclass 33, count 2 2006.168.07:31:10.25#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:31:10.25#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:31:10.25#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.168.07:31:10.25#ibcon#ireg 7 cls_cnt 0 2006.168.07:31:10.25#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:31:10.37#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:31:10.37#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:31:10.37#ibcon#enter wrdev, iclass 33, count 0 2006.168.07:31:10.37#ibcon#first serial, iclass 33, count 0 2006.168.07:31:10.37#ibcon#enter sib2, iclass 33, count 0 2006.168.07:31:10.37#ibcon#flushed, iclass 33, count 0 2006.168.07:31:10.37#ibcon#about to write, iclass 33, count 0 2006.168.07:31:10.37#ibcon#wrote, iclass 33, count 0 2006.168.07:31:10.37#ibcon#about to read 3, iclass 33, count 0 2006.168.07:31:10.39#ibcon#read 3, iclass 33, count 0 2006.168.07:31:10.39#ibcon#about to read 4, iclass 33, count 0 2006.168.07:31:10.39#ibcon#read 4, iclass 33, count 0 2006.168.07:31:10.39#ibcon#about to read 5, iclass 33, count 0 2006.168.07:31:10.39#ibcon#read 5, iclass 33, count 0 2006.168.07:31:10.39#ibcon#about to read 6, iclass 33, count 0 2006.168.07:31:10.39#ibcon#read 6, iclass 33, count 0 2006.168.07:31:10.39#ibcon#end of sib2, iclass 33, count 0 2006.168.07:31:10.39#ibcon#*mode == 0, iclass 33, count 0 2006.168.07:31:10.39#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.168.07:31:10.39#ibcon#[27=USB\r\n] 2006.168.07:31:10.39#ibcon#*before write, iclass 33, count 0 2006.168.07:31:10.39#ibcon#enter sib2, iclass 33, count 0 2006.168.07:31:10.39#ibcon#flushed, iclass 33, count 0 2006.168.07:31:10.39#ibcon#about to write, iclass 33, count 0 2006.168.07:31:10.39#ibcon#wrote, iclass 33, count 0 2006.168.07:31:10.39#ibcon#about to read 3, iclass 33, count 0 2006.168.07:31:10.42#ibcon#read 3, iclass 33, count 0 2006.168.07:31:10.42#ibcon#about to read 4, iclass 33, count 0 2006.168.07:31:10.42#ibcon#read 4, iclass 33, count 0 2006.168.07:31:10.42#ibcon#about to read 5, iclass 33, count 0 2006.168.07:31:10.42#ibcon#read 5, iclass 33, count 0 2006.168.07:31:10.42#ibcon#about to read 6, iclass 33, count 0 2006.168.07:31:10.42#ibcon#read 6, iclass 33, count 0 2006.168.07:31:10.42#ibcon#end of sib2, iclass 33, count 0 2006.168.07:31:10.42#ibcon#*after write, iclass 33, count 0 2006.168.07:31:10.42#ibcon#*before return 0, iclass 33, count 0 2006.168.07:31:10.42#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:31:10.42#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:31:10.42#ibcon#about to clear, iclass 33 cls_cnt 0 2006.168.07:31:10.42#ibcon#cleared, iclass 33 cls_cnt 0 2006.168.07:31:10.42$vc4f8/vblo=3,656.99 2006.168.07:31:10.42#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.168.07:31:10.42#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.168.07:31:10.42#ibcon#ireg 17 cls_cnt 0 2006.168.07:31:10.42#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:31:10.42#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:31:10.42#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:31:10.42#ibcon#enter wrdev, iclass 35, count 0 2006.168.07:31:10.42#ibcon#first serial, iclass 35, count 0 2006.168.07:31:10.42#ibcon#enter sib2, iclass 35, count 0 2006.168.07:31:10.42#ibcon#flushed, iclass 35, count 0 2006.168.07:31:10.42#ibcon#about to write, iclass 35, count 0 2006.168.07:31:10.42#ibcon#wrote, iclass 35, count 0 2006.168.07:31:10.42#ibcon#about to read 3, iclass 35, count 0 2006.168.07:31:10.44#ibcon#read 3, iclass 35, count 0 2006.168.07:31:10.44#ibcon#about to read 4, iclass 35, count 0 2006.168.07:31:10.44#ibcon#read 4, iclass 35, count 0 2006.168.07:31:10.44#ibcon#about to read 5, iclass 35, count 0 2006.168.07:31:10.44#ibcon#read 5, iclass 35, count 0 2006.168.07:31:10.44#ibcon#about to read 6, iclass 35, count 0 2006.168.07:31:10.44#ibcon#read 6, iclass 35, count 0 2006.168.07:31:10.44#ibcon#end of sib2, iclass 35, count 0 2006.168.07:31:10.44#ibcon#*mode == 0, iclass 35, count 0 2006.168.07:31:10.44#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.168.07:31:10.44#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.07:31:10.44#ibcon#*before write, iclass 35, count 0 2006.168.07:31:10.44#ibcon#enter sib2, iclass 35, count 0 2006.168.07:31:10.44#ibcon#flushed, iclass 35, count 0 2006.168.07:31:10.44#ibcon#about to write, iclass 35, count 0 2006.168.07:31:10.44#ibcon#wrote, iclass 35, count 0 2006.168.07:31:10.44#ibcon#about to read 3, iclass 35, count 0 2006.168.07:31:10.48#ibcon#read 3, iclass 35, count 0 2006.168.07:31:10.48#ibcon#about to read 4, iclass 35, count 0 2006.168.07:31:10.48#ibcon#read 4, iclass 35, count 0 2006.168.07:31:10.48#ibcon#about to read 5, iclass 35, count 0 2006.168.07:31:10.48#ibcon#read 5, iclass 35, count 0 2006.168.07:31:10.48#ibcon#about to read 6, iclass 35, count 0 2006.168.07:31:10.48#ibcon#read 6, iclass 35, count 0 2006.168.07:31:10.48#ibcon#end of sib2, iclass 35, count 0 2006.168.07:31:10.48#ibcon#*after write, iclass 35, count 0 2006.168.07:31:10.48#ibcon#*before return 0, iclass 35, count 0 2006.168.07:31:10.48#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:31:10.48#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:31:10.48#ibcon#about to clear, iclass 35 cls_cnt 0 2006.168.07:31:10.48#ibcon#cleared, iclass 35 cls_cnt 0 2006.168.07:31:10.48$vc4f8/vb=3,4 2006.168.07:31:10.48#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.168.07:31:10.48#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.168.07:31:10.48#ibcon#ireg 11 cls_cnt 2 2006.168.07:31:10.48#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:31:10.54#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:31:10.54#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:31:10.54#ibcon#enter wrdev, iclass 37, count 2 2006.168.07:31:10.54#ibcon#first serial, iclass 37, count 2 2006.168.07:31:10.54#ibcon#enter sib2, iclass 37, count 2 2006.168.07:31:10.54#ibcon#flushed, iclass 37, count 2 2006.168.07:31:10.54#ibcon#about to write, iclass 37, count 2 2006.168.07:31:10.54#ibcon#wrote, iclass 37, count 2 2006.168.07:31:10.54#ibcon#about to read 3, iclass 37, count 2 2006.168.07:31:10.56#ibcon#read 3, iclass 37, count 2 2006.168.07:31:10.56#ibcon#about to read 4, iclass 37, count 2 2006.168.07:31:10.56#ibcon#read 4, iclass 37, count 2 2006.168.07:31:10.56#ibcon#about to read 5, iclass 37, count 2 2006.168.07:31:10.56#ibcon#read 5, iclass 37, count 2 2006.168.07:31:10.56#ibcon#about to read 6, iclass 37, count 2 2006.168.07:31:10.56#ibcon#read 6, iclass 37, count 2 2006.168.07:31:10.56#ibcon#end of sib2, iclass 37, count 2 2006.168.07:31:10.56#ibcon#*mode == 0, iclass 37, count 2 2006.168.07:31:10.56#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.168.07:31:10.56#ibcon#[27=AT03-04\r\n] 2006.168.07:31:10.56#ibcon#*before write, iclass 37, count 2 2006.168.07:31:10.56#ibcon#enter sib2, iclass 37, count 2 2006.168.07:31:10.56#ibcon#flushed, iclass 37, count 2 2006.168.07:31:10.56#ibcon#about to write, iclass 37, count 2 2006.168.07:31:10.56#ibcon#wrote, iclass 37, count 2 2006.168.07:31:10.56#ibcon#about to read 3, iclass 37, count 2 2006.168.07:31:10.59#ibcon#read 3, iclass 37, count 2 2006.168.07:31:10.59#ibcon#about to read 4, iclass 37, count 2 2006.168.07:31:10.59#ibcon#read 4, iclass 37, count 2 2006.168.07:31:10.59#ibcon#about to read 5, iclass 37, count 2 2006.168.07:31:10.59#ibcon#read 5, iclass 37, count 2 2006.168.07:31:10.59#ibcon#about to read 6, iclass 37, count 2 2006.168.07:31:10.59#ibcon#read 6, iclass 37, count 2 2006.168.07:31:10.59#ibcon#end of sib2, iclass 37, count 2 2006.168.07:31:10.59#ibcon#*after write, iclass 37, count 2 2006.168.07:31:10.59#ibcon#*before return 0, iclass 37, count 2 2006.168.07:31:10.59#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:31:10.59#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:31:10.59#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.168.07:31:10.59#ibcon#ireg 7 cls_cnt 0 2006.168.07:31:10.59#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:31:10.71#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:31:10.71#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:31:10.71#ibcon#enter wrdev, iclass 37, count 0 2006.168.07:31:10.71#ibcon#first serial, iclass 37, count 0 2006.168.07:31:10.71#ibcon#enter sib2, iclass 37, count 0 2006.168.07:31:10.71#ibcon#flushed, iclass 37, count 0 2006.168.07:31:10.71#ibcon#about to write, iclass 37, count 0 2006.168.07:31:10.71#ibcon#wrote, iclass 37, count 0 2006.168.07:31:10.71#ibcon#about to read 3, iclass 37, count 0 2006.168.07:31:10.73#ibcon#read 3, iclass 37, count 0 2006.168.07:31:10.73#ibcon#about to read 4, iclass 37, count 0 2006.168.07:31:10.73#ibcon#read 4, iclass 37, count 0 2006.168.07:31:10.73#ibcon#about to read 5, iclass 37, count 0 2006.168.07:31:10.73#ibcon#read 5, iclass 37, count 0 2006.168.07:31:10.73#ibcon#about to read 6, iclass 37, count 0 2006.168.07:31:10.73#ibcon#read 6, iclass 37, count 0 2006.168.07:31:10.73#ibcon#end of sib2, iclass 37, count 0 2006.168.07:31:10.73#ibcon#*mode == 0, iclass 37, count 0 2006.168.07:31:10.73#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.168.07:31:10.73#ibcon#[27=USB\r\n] 2006.168.07:31:10.73#ibcon#*before write, iclass 37, count 0 2006.168.07:31:10.73#ibcon#enter sib2, iclass 37, count 0 2006.168.07:31:10.73#ibcon#flushed, iclass 37, count 0 2006.168.07:31:10.73#ibcon#about to write, iclass 37, count 0 2006.168.07:31:10.73#ibcon#wrote, iclass 37, count 0 2006.168.07:31:10.73#ibcon#about to read 3, iclass 37, count 0 2006.168.07:31:10.76#ibcon#read 3, iclass 37, count 0 2006.168.07:31:10.76#ibcon#about to read 4, iclass 37, count 0 2006.168.07:31:10.76#ibcon#read 4, iclass 37, count 0 2006.168.07:31:10.76#ibcon#about to read 5, iclass 37, count 0 2006.168.07:31:10.76#ibcon#read 5, iclass 37, count 0 2006.168.07:31:10.76#ibcon#about to read 6, iclass 37, count 0 2006.168.07:31:10.76#ibcon#read 6, iclass 37, count 0 2006.168.07:31:10.76#ibcon#end of sib2, iclass 37, count 0 2006.168.07:31:10.76#ibcon#*after write, iclass 37, count 0 2006.168.07:31:10.76#ibcon#*before return 0, iclass 37, count 0 2006.168.07:31:10.76#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:31:10.76#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:31:10.76#ibcon#about to clear, iclass 37 cls_cnt 0 2006.168.07:31:10.76#ibcon#cleared, iclass 37 cls_cnt 0 2006.168.07:31:10.76$vc4f8/vblo=4,712.99 2006.168.07:31:10.76#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.168.07:31:10.76#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.168.07:31:10.76#ibcon#ireg 17 cls_cnt 0 2006.168.07:31:10.76#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.168.07:31:10.76#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.168.07:31:10.76#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.168.07:31:10.76#ibcon#enter wrdev, iclass 39, count 0 2006.168.07:31:10.76#ibcon#first serial, iclass 39, count 0 2006.168.07:31:10.76#ibcon#enter sib2, iclass 39, count 0 2006.168.07:31:10.76#ibcon#flushed, iclass 39, count 0 2006.168.07:31:10.76#ibcon#about to write, iclass 39, count 0 2006.168.07:31:10.76#ibcon#wrote, iclass 39, count 0 2006.168.07:31:10.76#ibcon#about to read 3, iclass 39, count 0 2006.168.07:31:10.78#ibcon#read 3, iclass 39, count 0 2006.168.07:31:10.78#ibcon#about to read 4, iclass 39, count 0 2006.168.07:31:10.78#ibcon#read 4, iclass 39, count 0 2006.168.07:31:10.78#ibcon#about to read 5, iclass 39, count 0 2006.168.07:31:10.78#ibcon#read 5, iclass 39, count 0 2006.168.07:31:10.78#ibcon#about to read 6, iclass 39, count 0 2006.168.07:31:10.78#ibcon#read 6, iclass 39, count 0 2006.168.07:31:10.78#ibcon#end of sib2, iclass 39, count 0 2006.168.07:31:10.78#ibcon#*mode == 0, iclass 39, count 0 2006.168.07:31:10.78#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.168.07:31:10.78#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.07:31:10.78#ibcon#*before write, iclass 39, count 0 2006.168.07:31:10.78#ibcon#enter sib2, iclass 39, count 0 2006.168.07:31:10.78#ibcon#flushed, iclass 39, count 0 2006.168.07:31:10.78#ibcon#about to write, iclass 39, count 0 2006.168.07:31:10.78#ibcon#wrote, iclass 39, count 0 2006.168.07:31:10.78#ibcon#about to read 3, iclass 39, count 0 2006.168.07:31:10.82#ibcon#read 3, iclass 39, count 0 2006.168.07:31:10.82#ibcon#about to read 4, iclass 39, count 0 2006.168.07:31:10.82#ibcon#read 4, iclass 39, count 0 2006.168.07:31:10.82#ibcon#about to read 5, iclass 39, count 0 2006.168.07:31:10.82#ibcon#read 5, iclass 39, count 0 2006.168.07:31:10.82#ibcon#about to read 6, iclass 39, count 0 2006.168.07:31:10.82#ibcon#read 6, iclass 39, count 0 2006.168.07:31:10.82#ibcon#end of sib2, iclass 39, count 0 2006.168.07:31:10.82#ibcon#*after write, iclass 39, count 0 2006.168.07:31:10.82#ibcon#*before return 0, iclass 39, count 0 2006.168.07:31:10.82#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.168.07:31:10.82#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.168.07:31:10.82#ibcon#about to clear, iclass 39 cls_cnt 0 2006.168.07:31:10.82#ibcon#cleared, iclass 39 cls_cnt 0 2006.168.07:31:10.82$vc4f8/vb=4,4 2006.168.07:31:10.82#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.168.07:31:10.82#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.168.07:31:10.82#ibcon#ireg 11 cls_cnt 2 2006.168.07:31:10.82#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.168.07:31:10.88#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.168.07:31:10.88#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.168.07:31:10.88#ibcon#enter wrdev, iclass 3, count 2 2006.168.07:31:10.88#ibcon#first serial, iclass 3, count 2 2006.168.07:31:10.88#ibcon#enter sib2, iclass 3, count 2 2006.168.07:31:10.88#ibcon#flushed, iclass 3, count 2 2006.168.07:31:10.88#ibcon#about to write, iclass 3, count 2 2006.168.07:31:10.88#ibcon#wrote, iclass 3, count 2 2006.168.07:31:10.88#ibcon#about to read 3, iclass 3, count 2 2006.168.07:31:10.90#ibcon#read 3, iclass 3, count 2 2006.168.07:31:10.90#ibcon#about to read 4, iclass 3, count 2 2006.168.07:31:10.90#ibcon#read 4, iclass 3, count 2 2006.168.07:31:10.90#ibcon#about to read 5, iclass 3, count 2 2006.168.07:31:10.90#ibcon#read 5, iclass 3, count 2 2006.168.07:31:10.90#ibcon#about to read 6, iclass 3, count 2 2006.168.07:31:10.90#ibcon#read 6, iclass 3, count 2 2006.168.07:31:10.90#ibcon#end of sib2, iclass 3, count 2 2006.168.07:31:10.90#ibcon#*mode == 0, iclass 3, count 2 2006.168.07:31:10.90#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.168.07:31:10.90#ibcon#[27=AT04-04\r\n] 2006.168.07:31:10.90#ibcon#*before write, iclass 3, count 2 2006.168.07:31:10.90#ibcon#enter sib2, iclass 3, count 2 2006.168.07:31:10.90#ibcon#flushed, iclass 3, count 2 2006.168.07:31:10.90#ibcon#about to write, iclass 3, count 2 2006.168.07:31:10.90#ibcon#wrote, iclass 3, count 2 2006.168.07:31:10.90#ibcon#about to read 3, iclass 3, count 2 2006.168.07:31:10.93#ibcon#read 3, iclass 3, count 2 2006.168.07:31:10.93#ibcon#about to read 4, iclass 3, count 2 2006.168.07:31:10.93#ibcon#read 4, iclass 3, count 2 2006.168.07:31:10.93#ibcon#about to read 5, iclass 3, count 2 2006.168.07:31:10.93#ibcon#read 5, iclass 3, count 2 2006.168.07:31:10.93#ibcon#about to read 6, iclass 3, count 2 2006.168.07:31:10.93#ibcon#read 6, iclass 3, count 2 2006.168.07:31:10.93#ibcon#end of sib2, iclass 3, count 2 2006.168.07:31:10.93#ibcon#*after write, iclass 3, count 2 2006.168.07:31:10.93#ibcon#*before return 0, iclass 3, count 2 2006.168.07:31:10.93#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.168.07:31:10.93#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.168.07:31:10.93#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.168.07:31:10.93#ibcon#ireg 7 cls_cnt 0 2006.168.07:31:10.93#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.168.07:31:11.05#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.168.07:31:11.05#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.168.07:31:11.05#ibcon#enter wrdev, iclass 3, count 0 2006.168.07:31:11.05#ibcon#first serial, iclass 3, count 0 2006.168.07:31:11.05#ibcon#enter sib2, iclass 3, count 0 2006.168.07:31:11.05#ibcon#flushed, iclass 3, count 0 2006.168.07:31:11.05#ibcon#about to write, iclass 3, count 0 2006.168.07:31:11.05#ibcon#wrote, iclass 3, count 0 2006.168.07:31:11.05#ibcon#about to read 3, iclass 3, count 0 2006.168.07:31:11.07#ibcon#read 3, iclass 3, count 0 2006.168.07:31:11.07#ibcon#about to read 4, iclass 3, count 0 2006.168.07:31:11.07#ibcon#read 4, iclass 3, count 0 2006.168.07:31:11.07#ibcon#about to read 5, iclass 3, count 0 2006.168.07:31:11.07#ibcon#read 5, iclass 3, count 0 2006.168.07:31:11.07#ibcon#about to read 6, iclass 3, count 0 2006.168.07:31:11.07#ibcon#read 6, iclass 3, count 0 2006.168.07:31:11.07#ibcon#end of sib2, iclass 3, count 0 2006.168.07:31:11.07#ibcon#*mode == 0, iclass 3, count 0 2006.168.07:31:11.07#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.168.07:31:11.07#ibcon#[27=USB\r\n] 2006.168.07:31:11.07#ibcon#*before write, iclass 3, count 0 2006.168.07:31:11.07#ibcon#enter sib2, iclass 3, count 0 2006.168.07:31:11.07#ibcon#flushed, iclass 3, count 0 2006.168.07:31:11.07#ibcon#about to write, iclass 3, count 0 2006.168.07:31:11.07#ibcon#wrote, iclass 3, count 0 2006.168.07:31:11.07#ibcon#about to read 3, iclass 3, count 0 2006.168.07:31:11.10#ibcon#read 3, iclass 3, count 0 2006.168.07:31:11.10#ibcon#about to read 4, iclass 3, count 0 2006.168.07:31:11.10#ibcon#read 4, iclass 3, count 0 2006.168.07:31:11.10#ibcon#about to read 5, iclass 3, count 0 2006.168.07:31:11.10#ibcon#read 5, iclass 3, count 0 2006.168.07:31:11.10#ibcon#about to read 6, iclass 3, count 0 2006.168.07:31:11.10#ibcon#read 6, iclass 3, count 0 2006.168.07:31:11.10#ibcon#end of sib2, iclass 3, count 0 2006.168.07:31:11.10#ibcon#*after write, iclass 3, count 0 2006.168.07:31:11.10#ibcon#*before return 0, iclass 3, count 0 2006.168.07:31:11.10#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.168.07:31:11.10#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.168.07:31:11.10#ibcon#about to clear, iclass 3 cls_cnt 0 2006.168.07:31:11.10#ibcon#cleared, iclass 3 cls_cnt 0 2006.168.07:31:11.10$vc4f8/vblo=5,744.99 2006.168.07:31:11.10#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.168.07:31:11.10#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.168.07:31:11.10#ibcon#ireg 17 cls_cnt 0 2006.168.07:31:11.10#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.168.07:31:11.10#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.168.07:31:11.10#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.168.07:31:11.10#ibcon#enter wrdev, iclass 5, count 0 2006.168.07:31:11.10#ibcon#first serial, iclass 5, count 0 2006.168.07:31:11.10#ibcon#enter sib2, iclass 5, count 0 2006.168.07:31:11.10#ibcon#flushed, iclass 5, count 0 2006.168.07:31:11.10#ibcon#about to write, iclass 5, count 0 2006.168.07:31:11.10#ibcon#wrote, iclass 5, count 0 2006.168.07:31:11.10#ibcon#about to read 3, iclass 5, count 0 2006.168.07:31:11.12#ibcon#read 3, iclass 5, count 0 2006.168.07:31:11.12#ibcon#about to read 4, iclass 5, count 0 2006.168.07:31:11.12#ibcon#read 4, iclass 5, count 0 2006.168.07:31:11.12#ibcon#about to read 5, iclass 5, count 0 2006.168.07:31:11.12#ibcon#read 5, iclass 5, count 0 2006.168.07:31:11.12#ibcon#about to read 6, iclass 5, count 0 2006.168.07:31:11.12#ibcon#read 6, iclass 5, count 0 2006.168.07:31:11.12#ibcon#end of sib2, iclass 5, count 0 2006.168.07:31:11.12#ibcon#*mode == 0, iclass 5, count 0 2006.168.07:31:11.12#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.168.07:31:11.12#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.07:31:11.12#ibcon#*before write, iclass 5, count 0 2006.168.07:31:11.12#ibcon#enter sib2, iclass 5, count 0 2006.168.07:31:11.12#ibcon#flushed, iclass 5, count 0 2006.168.07:31:11.12#ibcon#about to write, iclass 5, count 0 2006.168.07:31:11.12#ibcon#wrote, iclass 5, count 0 2006.168.07:31:11.12#ibcon#about to read 3, iclass 5, count 0 2006.168.07:31:11.16#ibcon#read 3, iclass 5, count 0 2006.168.07:31:11.16#ibcon#about to read 4, iclass 5, count 0 2006.168.07:31:11.16#ibcon#read 4, iclass 5, count 0 2006.168.07:31:11.16#ibcon#about to read 5, iclass 5, count 0 2006.168.07:31:11.16#ibcon#read 5, iclass 5, count 0 2006.168.07:31:11.16#ibcon#about to read 6, iclass 5, count 0 2006.168.07:31:11.16#ibcon#read 6, iclass 5, count 0 2006.168.07:31:11.16#ibcon#end of sib2, iclass 5, count 0 2006.168.07:31:11.16#ibcon#*after write, iclass 5, count 0 2006.168.07:31:11.16#ibcon#*before return 0, iclass 5, count 0 2006.168.07:31:11.16#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.168.07:31:11.16#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.168.07:31:11.16#ibcon#about to clear, iclass 5 cls_cnt 0 2006.168.07:31:11.16#ibcon#cleared, iclass 5 cls_cnt 0 2006.168.07:31:11.16$vc4f8/vb=5,4 2006.168.07:31:11.16#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.168.07:31:11.16#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.168.07:31:11.16#ibcon#ireg 11 cls_cnt 2 2006.168.07:31:11.16#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.168.07:31:11.22#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.168.07:31:11.22#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.168.07:31:11.22#ibcon#enter wrdev, iclass 7, count 2 2006.168.07:31:11.22#ibcon#first serial, iclass 7, count 2 2006.168.07:31:11.22#ibcon#enter sib2, iclass 7, count 2 2006.168.07:31:11.22#ibcon#flushed, iclass 7, count 2 2006.168.07:31:11.22#ibcon#about to write, iclass 7, count 2 2006.168.07:31:11.22#ibcon#wrote, iclass 7, count 2 2006.168.07:31:11.22#ibcon#about to read 3, iclass 7, count 2 2006.168.07:31:11.24#ibcon#read 3, iclass 7, count 2 2006.168.07:31:11.24#ibcon#about to read 4, iclass 7, count 2 2006.168.07:31:11.24#ibcon#read 4, iclass 7, count 2 2006.168.07:31:11.24#ibcon#about to read 5, iclass 7, count 2 2006.168.07:31:11.24#ibcon#read 5, iclass 7, count 2 2006.168.07:31:11.24#ibcon#about to read 6, iclass 7, count 2 2006.168.07:31:11.24#ibcon#read 6, iclass 7, count 2 2006.168.07:31:11.24#ibcon#end of sib2, iclass 7, count 2 2006.168.07:31:11.24#ibcon#*mode == 0, iclass 7, count 2 2006.168.07:31:11.24#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.168.07:31:11.24#ibcon#[27=AT05-04\r\n] 2006.168.07:31:11.24#ibcon#*before write, iclass 7, count 2 2006.168.07:31:11.24#ibcon#enter sib2, iclass 7, count 2 2006.168.07:31:11.24#ibcon#flushed, iclass 7, count 2 2006.168.07:31:11.24#ibcon#about to write, iclass 7, count 2 2006.168.07:31:11.24#ibcon#wrote, iclass 7, count 2 2006.168.07:31:11.24#ibcon#about to read 3, iclass 7, count 2 2006.168.07:31:11.27#ibcon#read 3, iclass 7, count 2 2006.168.07:31:11.27#ibcon#about to read 4, iclass 7, count 2 2006.168.07:31:11.27#ibcon#read 4, iclass 7, count 2 2006.168.07:31:11.27#ibcon#about to read 5, iclass 7, count 2 2006.168.07:31:11.27#ibcon#read 5, iclass 7, count 2 2006.168.07:31:11.27#ibcon#about to read 6, iclass 7, count 2 2006.168.07:31:11.27#ibcon#read 6, iclass 7, count 2 2006.168.07:31:11.27#ibcon#end of sib2, iclass 7, count 2 2006.168.07:31:11.27#ibcon#*after write, iclass 7, count 2 2006.168.07:31:11.27#ibcon#*before return 0, iclass 7, count 2 2006.168.07:31:11.27#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.168.07:31:11.27#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.168.07:31:11.27#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.168.07:31:11.27#ibcon#ireg 7 cls_cnt 0 2006.168.07:31:11.27#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.168.07:31:11.39#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.168.07:31:11.39#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.168.07:31:11.39#ibcon#enter wrdev, iclass 7, count 0 2006.168.07:31:11.39#ibcon#first serial, iclass 7, count 0 2006.168.07:31:11.39#ibcon#enter sib2, iclass 7, count 0 2006.168.07:31:11.39#ibcon#flushed, iclass 7, count 0 2006.168.07:31:11.39#ibcon#about to write, iclass 7, count 0 2006.168.07:31:11.39#ibcon#wrote, iclass 7, count 0 2006.168.07:31:11.39#ibcon#about to read 3, iclass 7, count 0 2006.168.07:31:11.41#ibcon#read 3, iclass 7, count 0 2006.168.07:31:11.41#ibcon#about to read 4, iclass 7, count 0 2006.168.07:31:11.41#ibcon#read 4, iclass 7, count 0 2006.168.07:31:11.41#ibcon#about to read 5, iclass 7, count 0 2006.168.07:31:11.41#ibcon#read 5, iclass 7, count 0 2006.168.07:31:11.41#ibcon#about to read 6, iclass 7, count 0 2006.168.07:31:11.41#ibcon#read 6, iclass 7, count 0 2006.168.07:31:11.41#ibcon#end of sib2, iclass 7, count 0 2006.168.07:31:11.41#ibcon#*mode == 0, iclass 7, count 0 2006.168.07:31:11.41#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.168.07:31:11.41#ibcon#[27=USB\r\n] 2006.168.07:31:11.41#ibcon#*before write, iclass 7, count 0 2006.168.07:31:11.41#ibcon#enter sib2, iclass 7, count 0 2006.168.07:31:11.41#ibcon#flushed, iclass 7, count 0 2006.168.07:31:11.41#ibcon#about to write, iclass 7, count 0 2006.168.07:31:11.41#ibcon#wrote, iclass 7, count 0 2006.168.07:31:11.41#ibcon#about to read 3, iclass 7, count 0 2006.168.07:31:11.44#ibcon#read 3, iclass 7, count 0 2006.168.07:31:11.44#ibcon#about to read 4, iclass 7, count 0 2006.168.07:31:11.44#ibcon#read 4, iclass 7, count 0 2006.168.07:31:11.44#ibcon#about to read 5, iclass 7, count 0 2006.168.07:31:11.44#ibcon#read 5, iclass 7, count 0 2006.168.07:31:11.44#ibcon#about to read 6, iclass 7, count 0 2006.168.07:31:11.44#ibcon#read 6, iclass 7, count 0 2006.168.07:31:11.44#ibcon#end of sib2, iclass 7, count 0 2006.168.07:31:11.44#ibcon#*after write, iclass 7, count 0 2006.168.07:31:11.44#ibcon#*before return 0, iclass 7, count 0 2006.168.07:31:11.44#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.168.07:31:11.44#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.168.07:31:11.44#ibcon#about to clear, iclass 7 cls_cnt 0 2006.168.07:31:11.44#ibcon#cleared, iclass 7 cls_cnt 0 2006.168.07:31:11.44$vc4f8/vblo=6,752.99 2006.168.07:31:11.44#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.168.07:31:11.44#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.168.07:31:11.44#ibcon#ireg 17 cls_cnt 0 2006.168.07:31:11.44#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.168.07:31:11.44#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.168.07:31:11.44#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.168.07:31:11.44#ibcon#enter wrdev, iclass 11, count 0 2006.168.07:31:11.44#ibcon#first serial, iclass 11, count 0 2006.168.07:31:11.44#ibcon#enter sib2, iclass 11, count 0 2006.168.07:31:11.44#ibcon#flushed, iclass 11, count 0 2006.168.07:31:11.44#ibcon#about to write, iclass 11, count 0 2006.168.07:31:11.44#ibcon#wrote, iclass 11, count 0 2006.168.07:31:11.44#ibcon#about to read 3, iclass 11, count 0 2006.168.07:31:11.46#ibcon#read 3, iclass 11, count 0 2006.168.07:31:11.46#ibcon#about to read 4, iclass 11, count 0 2006.168.07:31:11.46#ibcon#read 4, iclass 11, count 0 2006.168.07:31:11.46#ibcon#about to read 5, iclass 11, count 0 2006.168.07:31:11.46#ibcon#read 5, iclass 11, count 0 2006.168.07:31:11.46#ibcon#about to read 6, iclass 11, count 0 2006.168.07:31:11.46#ibcon#read 6, iclass 11, count 0 2006.168.07:31:11.46#ibcon#end of sib2, iclass 11, count 0 2006.168.07:31:11.46#ibcon#*mode == 0, iclass 11, count 0 2006.168.07:31:11.46#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.168.07:31:11.46#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.07:31:11.46#ibcon#*before write, iclass 11, count 0 2006.168.07:31:11.46#ibcon#enter sib2, iclass 11, count 0 2006.168.07:31:11.46#ibcon#flushed, iclass 11, count 0 2006.168.07:31:11.46#ibcon#about to write, iclass 11, count 0 2006.168.07:31:11.46#ibcon#wrote, iclass 11, count 0 2006.168.07:31:11.46#ibcon#about to read 3, iclass 11, count 0 2006.168.07:31:11.50#ibcon#read 3, iclass 11, count 0 2006.168.07:31:11.50#ibcon#about to read 4, iclass 11, count 0 2006.168.07:31:11.50#ibcon#read 4, iclass 11, count 0 2006.168.07:31:11.50#ibcon#about to read 5, iclass 11, count 0 2006.168.07:31:11.50#ibcon#read 5, iclass 11, count 0 2006.168.07:31:11.50#ibcon#about to read 6, iclass 11, count 0 2006.168.07:31:11.50#ibcon#read 6, iclass 11, count 0 2006.168.07:31:11.50#ibcon#end of sib2, iclass 11, count 0 2006.168.07:31:11.50#ibcon#*after write, iclass 11, count 0 2006.168.07:31:11.50#ibcon#*before return 0, iclass 11, count 0 2006.168.07:31:11.50#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.168.07:31:11.50#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.168.07:31:11.50#ibcon#about to clear, iclass 11 cls_cnt 0 2006.168.07:31:11.50#ibcon#cleared, iclass 11 cls_cnt 0 2006.168.07:31:11.50$vc4f8/vb=6,4 2006.168.07:31:11.50#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.168.07:31:11.50#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.168.07:31:11.50#ibcon#ireg 11 cls_cnt 2 2006.168.07:31:11.50#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.168.07:31:11.56#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.168.07:31:11.56#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.168.07:31:11.56#ibcon#enter wrdev, iclass 13, count 2 2006.168.07:31:11.56#ibcon#first serial, iclass 13, count 2 2006.168.07:31:11.56#ibcon#enter sib2, iclass 13, count 2 2006.168.07:31:11.56#ibcon#flushed, iclass 13, count 2 2006.168.07:31:11.56#ibcon#about to write, iclass 13, count 2 2006.168.07:31:11.56#ibcon#wrote, iclass 13, count 2 2006.168.07:31:11.56#ibcon#about to read 3, iclass 13, count 2 2006.168.07:31:11.58#ibcon#read 3, iclass 13, count 2 2006.168.07:31:11.58#ibcon#about to read 4, iclass 13, count 2 2006.168.07:31:11.58#ibcon#read 4, iclass 13, count 2 2006.168.07:31:11.58#ibcon#about to read 5, iclass 13, count 2 2006.168.07:31:11.58#ibcon#read 5, iclass 13, count 2 2006.168.07:31:11.58#ibcon#about to read 6, iclass 13, count 2 2006.168.07:31:11.58#ibcon#read 6, iclass 13, count 2 2006.168.07:31:11.58#ibcon#end of sib2, iclass 13, count 2 2006.168.07:31:11.58#ibcon#*mode == 0, iclass 13, count 2 2006.168.07:31:11.58#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.168.07:31:11.58#ibcon#[27=AT06-04\r\n] 2006.168.07:31:11.58#ibcon#*before write, iclass 13, count 2 2006.168.07:31:11.58#ibcon#enter sib2, iclass 13, count 2 2006.168.07:31:11.58#ibcon#flushed, iclass 13, count 2 2006.168.07:31:11.58#ibcon#about to write, iclass 13, count 2 2006.168.07:31:11.58#ibcon#wrote, iclass 13, count 2 2006.168.07:31:11.58#ibcon#about to read 3, iclass 13, count 2 2006.168.07:31:11.61#ibcon#read 3, iclass 13, count 2 2006.168.07:31:11.61#ibcon#about to read 4, iclass 13, count 2 2006.168.07:31:11.61#ibcon#read 4, iclass 13, count 2 2006.168.07:31:11.61#ibcon#about to read 5, iclass 13, count 2 2006.168.07:31:11.61#ibcon#read 5, iclass 13, count 2 2006.168.07:31:11.61#ibcon#about to read 6, iclass 13, count 2 2006.168.07:31:11.61#ibcon#read 6, iclass 13, count 2 2006.168.07:31:11.61#ibcon#end of sib2, iclass 13, count 2 2006.168.07:31:11.61#ibcon#*after write, iclass 13, count 2 2006.168.07:31:11.61#ibcon#*before return 0, iclass 13, count 2 2006.168.07:31:11.61#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.168.07:31:11.61#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.168.07:31:11.61#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.168.07:31:11.61#ibcon#ireg 7 cls_cnt 0 2006.168.07:31:11.61#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.168.07:31:11.73#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.168.07:31:11.73#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.168.07:31:11.73#ibcon#enter wrdev, iclass 13, count 0 2006.168.07:31:11.73#ibcon#first serial, iclass 13, count 0 2006.168.07:31:11.73#ibcon#enter sib2, iclass 13, count 0 2006.168.07:31:11.73#ibcon#flushed, iclass 13, count 0 2006.168.07:31:11.73#ibcon#about to write, iclass 13, count 0 2006.168.07:31:11.73#ibcon#wrote, iclass 13, count 0 2006.168.07:31:11.73#ibcon#about to read 3, iclass 13, count 0 2006.168.07:31:11.75#ibcon#read 3, iclass 13, count 0 2006.168.07:31:11.75#ibcon#about to read 4, iclass 13, count 0 2006.168.07:31:11.75#ibcon#read 4, iclass 13, count 0 2006.168.07:31:11.75#ibcon#about to read 5, iclass 13, count 0 2006.168.07:31:11.75#ibcon#read 5, iclass 13, count 0 2006.168.07:31:11.75#ibcon#about to read 6, iclass 13, count 0 2006.168.07:31:11.75#ibcon#read 6, iclass 13, count 0 2006.168.07:31:11.75#ibcon#end of sib2, iclass 13, count 0 2006.168.07:31:11.75#ibcon#*mode == 0, iclass 13, count 0 2006.168.07:31:11.75#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.168.07:31:11.75#ibcon#[27=USB\r\n] 2006.168.07:31:11.75#ibcon#*before write, iclass 13, count 0 2006.168.07:31:11.75#ibcon#enter sib2, iclass 13, count 0 2006.168.07:31:11.75#ibcon#flushed, iclass 13, count 0 2006.168.07:31:11.75#ibcon#about to write, iclass 13, count 0 2006.168.07:31:11.75#ibcon#wrote, iclass 13, count 0 2006.168.07:31:11.75#ibcon#about to read 3, iclass 13, count 0 2006.168.07:31:11.78#ibcon#read 3, iclass 13, count 0 2006.168.07:31:11.78#ibcon#about to read 4, iclass 13, count 0 2006.168.07:31:11.78#ibcon#read 4, iclass 13, count 0 2006.168.07:31:11.78#ibcon#about to read 5, iclass 13, count 0 2006.168.07:31:11.78#ibcon#read 5, iclass 13, count 0 2006.168.07:31:11.78#ibcon#about to read 6, iclass 13, count 0 2006.168.07:31:11.78#ibcon#read 6, iclass 13, count 0 2006.168.07:31:11.78#ibcon#end of sib2, iclass 13, count 0 2006.168.07:31:11.78#ibcon#*after write, iclass 13, count 0 2006.168.07:31:11.78#ibcon#*before return 0, iclass 13, count 0 2006.168.07:31:11.78#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.168.07:31:11.78#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.168.07:31:11.78#ibcon#about to clear, iclass 13 cls_cnt 0 2006.168.07:31:11.78#ibcon#cleared, iclass 13 cls_cnt 0 2006.168.07:31:11.78$vc4f8/vabw=wide 2006.168.07:31:11.78#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.168.07:31:11.78#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.168.07:31:11.78#ibcon#ireg 8 cls_cnt 0 2006.168.07:31:11.78#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:31:11.78#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:31:11.78#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:31:11.78#ibcon#enter wrdev, iclass 15, count 0 2006.168.07:31:11.78#ibcon#first serial, iclass 15, count 0 2006.168.07:31:11.78#ibcon#enter sib2, iclass 15, count 0 2006.168.07:31:11.78#ibcon#flushed, iclass 15, count 0 2006.168.07:31:11.78#ibcon#about to write, iclass 15, count 0 2006.168.07:31:11.78#ibcon#wrote, iclass 15, count 0 2006.168.07:31:11.78#ibcon#about to read 3, iclass 15, count 0 2006.168.07:31:11.80#ibcon#read 3, iclass 15, count 0 2006.168.07:31:11.80#ibcon#about to read 4, iclass 15, count 0 2006.168.07:31:11.80#ibcon#read 4, iclass 15, count 0 2006.168.07:31:11.80#ibcon#about to read 5, iclass 15, count 0 2006.168.07:31:11.80#ibcon#read 5, iclass 15, count 0 2006.168.07:31:11.80#ibcon#about to read 6, iclass 15, count 0 2006.168.07:31:11.80#ibcon#read 6, iclass 15, count 0 2006.168.07:31:11.80#ibcon#end of sib2, iclass 15, count 0 2006.168.07:31:11.80#ibcon#*mode == 0, iclass 15, count 0 2006.168.07:31:11.80#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.168.07:31:11.80#ibcon#[25=BW32\r\n] 2006.168.07:31:11.80#ibcon#*before write, iclass 15, count 0 2006.168.07:31:11.80#ibcon#enter sib2, iclass 15, count 0 2006.168.07:31:11.80#ibcon#flushed, iclass 15, count 0 2006.168.07:31:11.80#ibcon#about to write, iclass 15, count 0 2006.168.07:31:11.80#ibcon#wrote, iclass 15, count 0 2006.168.07:31:11.80#ibcon#about to read 3, iclass 15, count 0 2006.168.07:31:11.83#ibcon#read 3, iclass 15, count 0 2006.168.07:31:11.83#ibcon#about to read 4, iclass 15, count 0 2006.168.07:31:11.83#ibcon#read 4, iclass 15, count 0 2006.168.07:31:11.83#ibcon#about to read 5, iclass 15, count 0 2006.168.07:31:11.83#ibcon#read 5, iclass 15, count 0 2006.168.07:31:11.83#ibcon#about to read 6, iclass 15, count 0 2006.168.07:31:11.83#ibcon#read 6, iclass 15, count 0 2006.168.07:31:11.83#ibcon#end of sib2, iclass 15, count 0 2006.168.07:31:11.83#ibcon#*after write, iclass 15, count 0 2006.168.07:31:11.83#ibcon#*before return 0, iclass 15, count 0 2006.168.07:31:11.83#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:31:11.83#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:31:11.83#ibcon#about to clear, iclass 15 cls_cnt 0 2006.168.07:31:11.83#ibcon#cleared, iclass 15 cls_cnt 0 2006.168.07:31:11.83$vc4f8/vbbw=wide 2006.168.07:31:11.83#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.168.07:31:11.83#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.168.07:31:11.83#ibcon#ireg 8 cls_cnt 0 2006.168.07:31:11.83#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:31:11.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:31:11.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:31:11.90#ibcon#enter wrdev, iclass 17, count 0 2006.168.07:31:11.90#ibcon#first serial, iclass 17, count 0 2006.168.07:31:11.90#ibcon#enter sib2, iclass 17, count 0 2006.168.07:31:11.90#ibcon#flushed, iclass 17, count 0 2006.168.07:31:11.90#ibcon#about to write, iclass 17, count 0 2006.168.07:31:11.90#ibcon#wrote, iclass 17, count 0 2006.168.07:31:11.90#ibcon#about to read 3, iclass 17, count 0 2006.168.07:31:11.92#ibcon#read 3, iclass 17, count 0 2006.168.07:31:11.92#ibcon#about to read 4, iclass 17, count 0 2006.168.07:31:11.92#ibcon#read 4, iclass 17, count 0 2006.168.07:31:11.92#ibcon#about to read 5, iclass 17, count 0 2006.168.07:31:11.92#ibcon#read 5, iclass 17, count 0 2006.168.07:31:11.92#ibcon#about to read 6, iclass 17, count 0 2006.168.07:31:11.92#ibcon#read 6, iclass 17, count 0 2006.168.07:31:11.92#ibcon#end of sib2, iclass 17, count 0 2006.168.07:31:11.92#ibcon#*mode == 0, iclass 17, count 0 2006.168.07:31:11.92#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.168.07:31:11.92#ibcon#[27=BW32\r\n] 2006.168.07:31:11.92#ibcon#*before write, iclass 17, count 0 2006.168.07:31:11.92#ibcon#enter sib2, iclass 17, count 0 2006.168.07:31:11.92#ibcon#flushed, iclass 17, count 0 2006.168.07:31:11.92#ibcon#about to write, iclass 17, count 0 2006.168.07:31:11.92#ibcon#wrote, iclass 17, count 0 2006.168.07:31:11.92#ibcon#about to read 3, iclass 17, count 0 2006.168.07:31:11.95#ibcon#read 3, iclass 17, count 0 2006.168.07:31:11.95#ibcon#about to read 4, iclass 17, count 0 2006.168.07:31:11.95#ibcon#read 4, iclass 17, count 0 2006.168.07:31:11.95#ibcon#about to read 5, iclass 17, count 0 2006.168.07:31:11.95#ibcon#read 5, iclass 17, count 0 2006.168.07:31:11.95#ibcon#about to read 6, iclass 17, count 0 2006.168.07:31:11.95#ibcon#read 6, iclass 17, count 0 2006.168.07:31:11.95#ibcon#end of sib2, iclass 17, count 0 2006.168.07:31:11.95#ibcon#*after write, iclass 17, count 0 2006.168.07:31:11.95#ibcon#*before return 0, iclass 17, count 0 2006.168.07:31:11.95#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:31:11.95#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:31:11.95#ibcon#about to clear, iclass 17 cls_cnt 0 2006.168.07:31:11.95#ibcon#cleared, iclass 17 cls_cnt 0 2006.168.07:31:11.95$4f8m12a/ifd4f 2006.168.07:31:11.95$ifd4f/lo= 2006.168.07:31:11.95$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.07:31:11.95$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.07:31:11.95$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.07:31:11.95$ifd4f/patch= 2006.168.07:31:11.95$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.07:31:11.95$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.07:31:11.95$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.07:31:11.95$4f8m12a/"form=m,16.000,1:2 2006.168.07:31:11.95$4f8m12a/"tpicd 2006.168.07:31:11.95$4f8m12a/echo=off 2006.168.07:31:11.95$4f8m12a/xlog=off 2006.168.07:31:11.95:!2006.168.07:33:20 2006.168.07:31:52.14#trakl#Source acquired 2006.168.07:31:54.14#flagr#flagr/antenna,acquired 2006.168.07:33:20.00:preob 2006.168.07:33:20.14/onsource/TRACKING 2006.168.07:33:20.14:!2006.168.07:33:30 2006.168.07:33:30.00:data_valid=on 2006.168.07:33:30.00:midob 2006.168.07:33:30.14/onsource/TRACKING 2006.168.07:33:30.14/wx/27.92,1004.7,75 2006.168.07:33:30.33/cable/+6.4720E-03 2006.168.07:33:31.42/va/01,08,usb,yes,29,31 2006.168.07:33:31.42/va/02,07,usb,yes,29,30 2006.168.07:33:31.42/va/03,06,usb,yes,31,31 2006.168.07:33:31.42/va/04,07,usb,yes,30,32 2006.168.07:33:31.42/va/05,07,usb,yes,29,31 2006.168.07:33:31.42/va/06,06,usb,yes,28,28 2006.168.07:33:31.42/va/07,06,usb,yes,29,28 2006.168.07:33:31.42/va/08,07,usb,yes,27,27 2006.168.07:33:31.65/valo/01,532.99,yes,locked 2006.168.07:33:31.65/valo/02,572.99,yes,locked 2006.168.07:33:31.65/valo/03,672.99,yes,locked 2006.168.07:33:31.65/valo/04,832.99,yes,locked 2006.168.07:33:31.65/valo/05,652.99,yes,locked 2006.168.07:33:31.65/valo/06,772.99,yes,locked 2006.168.07:33:31.65/valo/07,832.99,yes,locked 2006.168.07:33:31.65/valo/08,852.99,yes,locked 2006.168.07:33:32.74/vb/01,04,usb,yes,29,28 2006.168.07:33:32.74/vb/02,04,usb,yes,31,32 2006.168.07:33:32.74/vb/03,04,usb,yes,27,31 2006.168.07:33:32.74/vb/04,04,usb,yes,28,28 2006.168.07:33:32.74/vb/05,04,usb,yes,26,30 2006.168.07:33:32.74/vb/06,04,usb,yes,27,30 2006.168.07:33:32.74/vb/07,04,usb,yes,29,29 2006.168.07:33:32.74/vb/08,04,usb,yes,27,30 2006.168.07:33:32.97/vblo/01,632.99,yes,locked 2006.168.07:33:32.97/vblo/02,640.99,yes,locked 2006.168.07:33:32.97/vblo/03,656.99,yes,locked 2006.168.07:33:32.97/vblo/04,712.99,yes,locked 2006.168.07:33:32.97/vblo/05,744.99,yes,locked 2006.168.07:33:32.97/vblo/06,752.99,yes,locked 2006.168.07:33:32.97/vblo/07,734.99,yes,locked 2006.168.07:33:32.97/vblo/08,744.99,yes,locked 2006.168.07:33:33.12/vabw/8 2006.168.07:33:33.27/vbbw/8 2006.168.07:33:33.36/xfe/off,on,14.2 2006.168.07:33:33.73/ifatt/23,28,28,28 2006.168.07:33:34.08/fmout-gps/S +4.21E-07 2006.168.07:33:34.12:!2006.168.07:34:30 2006.168.07:34:30.00:data_valid=off 2006.168.07:34:30.00:postob 2006.168.07:34:30.17/cable/+6.4742E-03 2006.168.07:34:30.17/wx/27.90,1004.7,73 2006.168.07:34:31.08/fmout-gps/S +4.21E-07 2006.168.07:34:31.08:scan_name=168-0735,k06168,60 2006.168.07:34:31.09:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.168.07:34:31.14#flagr#flagr/antenna,new-source 2006.168.07:34:32.14:checkk5 2006.168.07:34:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.168.07:34:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.168.07:34:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.168.07:34:33.65/chk_autoobs//k5ts4/ autoobs is running! 2006.168.07:34:34.02/chk_obsdata//k5ts1/T1680733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:34:34.40/chk_obsdata//k5ts2/T1680733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:34:34.77/chk_obsdata//k5ts3/T1680733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:34:35.14/chk_obsdata//k5ts4/T1680733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:34:35.83/k5log//k5ts1_log_newline 2006.168.07:34:36.51/k5log//k5ts2_log_newline 2006.168.07:34:37.21/k5log//k5ts3_log_newline 2006.168.07:34:37.90/k5log//k5ts4_log_newline 2006.168.07:34:37.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.07:34:37.93:4f8m12a=1 2006.168.07:34:37.93$4f8m12a/echo=on 2006.168.07:34:37.93$4f8m12a/pcalon 2006.168.07:34:37.93$pcalon/"no phase cal control is implemented here 2006.168.07:34:37.93$4f8m12a/"tpicd=stop 2006.168.07:34:37.93$4f8m12a/vc4f8 2006.168.07:34:37.93$vc4f8/valo=1,532.99 2006.168.07:34:37.93#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.168.07:34:37.93#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.168.07:34:37.93#ibcon#ireg 17 cls_cnt 0 2006.168.07:34:37.93#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:34:37.93#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:34:37.93#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:34:37.93#ibcon#enter wrdev, iclass 28, count 0 2006.168.07:34:37.93#ibcon#first serial, iclass 28, count 0 2006.168.07:34:37.93#ibcon#enter sib2, iclass 28, count 0 2006.168.07:34:37.93#ibcon#flushed, iclass 28, count 0 2006.168.07:34:37.93#ibcon#about to write, iclass 28, count 0 2006.168.07:34:37.93#ibcon#wrote, iclass 28, count 0 2006.168.07:34:37.93#ibcon#about to read 3, iclass 28, count 0 2006.168.07:34:37.97#ibcon#read 3, iclass 28, count 0 2006.168.07:34:37.97#ibcon#about to read 4, iclass 28, count 0 2006.168.07:34:37.97#ibcon#read 4, iclass 28, count 0 2006.168.07:34:37.97#ibcon#about to read 5, iclass 28, count 0 2006.168.07:34:37.97#ibcon#read 5, iclass 28, count 0 2006.168.07:34:37.97#ibcon#about to read 6, iclass 28, count 0 2006.168.07:34:37.97#ibcon#read 6, iclass 28, count 0 2006.168.07:34:37.97#ibcon#end of sib2, iclass 28, count 0 2006.168.07:34:37.97#ibcon#*mode == 0, iclass 28, count 0 2006.168.07:34:37.97#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.168.07:34:37.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.07:34:37.97#ibcon#*before write, iclass 28, count 0 2006.168.07:34:37.97#ibcon#enter sib2, iclass 28, count 0 2006.168.07:34:37.97#ibcon#flushed, iclass 28, count 0 2006.168.07:34:37.97#ibcon#about to write, iclass 28, count 0 2006.168.07:34:37.97#ibcon#wrote, iclass 28, count 0 2006.168.07:34:37.97#ibcon#about to read 3, iclass 28, count 0 2006.168.07:34:38.02#ibcon#read 3, iclass 28, count 0 2006.168.07:34:38.02#ibcon#about to read 4, iclass 28, count 0 2006.168.07:34:38.02#ibcon#read 4, iclass 28, count 0 2006.168.07:34:38.02#ibcon#about to read 5, iclass 28, count 0 2006.168.07:34:38.02#ibcon#read 5, iclass 28, count 0 2006.168.07:34:38.02#ibcon#about to read 6, iclass 28, count 0 2006.168.07:34:38.02#ibcon#read 6, iclass 28, count 0 2006.168.07:34:38.02#ibcon#end of sib2, iclass 28, count 0 2006.168.07:34:38.02#ibcon#*after write, iclass 28, count 0 2006.168.07:34:38.02#ibcon#*before return 0, iclass 28, count 0 2006.168.07:34:38.02#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:34:38.02#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:34:38.02#ibcon#about to clear, iclass 28 cls_cnt 0 2006.168.07:34:38.02#ibcon#cleared, iclass 28 cls_cnt 0 2006.168.07:34:38.02$vc4f8/va=1,8 2006.168.07:34:38.02#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.168.07:34:38.02#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.168.07:34:38.02#ibcon#ireg 11 cls_cnt 2 2006.168.07:34:38.02#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:34:38.02#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:34:38.02#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:34:38.02#ibcon#enter wrdev, iclass 30, count 2 2006.168.07:34:38.02#ibcon#first serial, iclass 30, count 2 2006.168.07:34:38.02#ibcon#enter sib2, iclass 30, count 2 2006.168.07:34:38.02#ibcon#flushed, iclass 30, count 2 2006.168.07:34:38.02#ibcon#about to write, iclass 30, count 2 2006.168.07:34:38.02#ibcon#wrote, iclass 30, count 2 2006.168.07:34:38.02#ibcon#about to read 3, iclass 30, count 2 2006.168.07:34:38.04#ibcon#read 3, iclass 30, count 2 2006.168.07:34:38.04#ibcon#about to read 4, iclass 30, count 2 2006.168.07:34:38.04#ibcon#read 4, iclass 30, count 2 2006.168.07:34:38.04#ibcon#about to read 5, iclass 30, count 2 2006.168.07:34:38.04#ibcon#read 5, iclass 30, count 2 2006.168.07:34:38.04#ibcon#about to read 6, iclass 30, count 2 2006.168.07:34:38.04#ibcon#read 6, iclass 30, count 2 2006.168.07:34:38.04#ibcon#end of sib2, iclass 30, count 2 2006.168.07:34:38.04#ibcon#*mode == 0, iclass 30, count 2 2006.168.07:34:38.04#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.168.07:34:38.04#ibcon#[25=AT01-08\r\n] 2006.168.07:34:38.04#ibcon#*before write, iclass 30, count 2 2006.168.07:34:38.04#ibcon#enter sib2, iclass 30, count 2 2006.168.07:34:38.04#ibcon#flushed, iclass 30, count 2 2006.168.07:34:38.04#ibcon#about to write, iclass 30, count 2 2006.168.07:34:38.04#ibcon#wrote, iclass 30, count 2 2006.168.07:34:38.04#ibcon#about to read 3, iclass 30, count 2 2006.168.07:34:38.07#ibcon#read 3, iclass 30, count 2 2006.168.07:34:38.07#ibcon#about to read 4, iclass 30, count 2 2006.168.07:34:38.07#ibcon#read 4, iclass 30, count 2 2006.168.07:34:38.07#ibcon#about to read 5, iclass 30, count 2 2006.168.07:34:38.07#ibcon#read 5, iclass 30, count 2 2006.168.07:34:38.07#ibcon#about to read 6, iclass 30, count 2 2006.168.07:34:38.07#ibcon#read 6, iclass 30, count 2 2006.168.07:34:38.07#ibcon#end of sib2, iclass 30, count 2 2006.168.07:34:38.07#ibcon#*after write, iclass 30, count 2 2006.168.07:34:38.07#ibcon#*before return 0, iclass 30, count 2 2006.168.07:34:38.07#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:34:38.07#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:34:38.07#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.168.07:34:38.07#ibcon#ireg 7 cls_cnt 0 2006.168.07:34:38.07#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:34:38.19#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:34:38.19#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:34:38.19#ibcon#enter wrdev, iclass 30, count 0 2006.168.07:34:38.19#ibcon#first serial, iclass 30, count 0 2006.168.07:34:38.19#ibcon#enter sib2, iclass 30, count 0 2006.168.07:34:38.19#ibcon#flushed, iclass 30, count 0 2006.168.07:34:38.19#ibcon#about to write, iclass 30, count 0 2006.168.07:34:38.19#ibcon#wrote, iclass 30, count 0 2006.168.07:34:38.19#ibcon#about to read 3, iclass 30, count 0 2006.168.07:34:38.21#ibcon#read 3, iclass 30, count 0 2006.168.07:34:38.21#ibcon#about to read 4, iclass 30, count 0 2006.168.07:34:38.21#ibcon#read 4, iclass 30, count 0 2006.168.07:34:38.21#ibcon#about to read 5, iclass 30, count 0 2006.168.07:34:38.21#ibcon#read 5, iclass 30, count 0 2006.168.07:34:38.21#ibcon#about to read 6, iclass 30, count 0 2006.168.07:34:38.21#ibcon#read 6, iclass 30, count 0 2006.168.07:34:38.21#ibcon#end of sib2, iclass 30, count 0 2006.168.07:34:38.21#ibcon#*mode == 0, iclass 30, count 0 2006.168.07:34:38.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.168.07:34:38.21#ibcon#[25=USB\r\n] 2006.168.07:34:38.21#ibcon#*before write, iclass 30, count 0 2006.168.07:34:38.21#ibcon#enter sib2, iclass 30, count 0 2006.168.07:34:38.21#ibcon#flushed, iclass 30, count 0 2006.168.07:34:38.21#ibcon#about to write, iclass 30, count 0 2006.168.07:34:38.21#ibcon#wrote, iclass 30, count 0 2006.168.07:34:38.21#ibcon#about to read 3, iclass 30, count 0 2006.168.07:34:38.24#ibcon#read 3, iclass 30, count 0 2006.168.07:34:38.24#ibcon#about to read 4, iclass 30, count 0 2006.168.07:34:38.24#ibcon#read 4, iclass 30, count 0 2006.168.07:34:38.24#ibcon#about to read 5, iclass 30, count 0 2006.168.07:34:38.24#ibcon#read 5, iclass 30, count 0 2006.168.07:34:38.24#ibcon#about to read 6, iclass 30, count 0 2006.168.07:34:38.24#ibcon#read 6, iclass 30, count 0 2006.168.07:34:38.24#ibcon#end of sib2, iclass 30, count 0 2006.168.07:34:38.24#ibcon#*after write, iclass 30, count 0 2006.168.07:34:38.24#ibcon#*before return 0, iclass 30, count 0 2006.168.07:34:38.24#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:34:38.24#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:34:38.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.168.07:34:38.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.168.07:34:38.24$vc4f8/valo=2,572.99 2006.168.07:34:38.24#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.168.07:34:38.24#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.168.07:34:38.24#ibcon#ireg 17 cls_cnt 0 2006.168.07:34:38.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:34:38.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:34:38.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:34:38.24#ibcon#enter wrdev, iclass 32, count 0 2006.168.07:34:38.24#ibcon#first serial, iclass 32, count 0 2006.168.07:34:38.24#ibcon#enter sib2, iclass 32, count 0 2006.168.07:34:38.24#ibcon#flushed, iclass 32, count 0 2006.168.07:34:38.24#ibcon#about to write, iclass 32, count 0 2006.168.07:34:38.24#ibcon#wrote, iclass 32, count 0 2006.168.07:34:38.24#ibcon#about to read 3, iclass 32, count 0 2006.168.07:34:38.26#ibcon#read 3, iclass 32, count 0 2006.168.07:34:38.26#ibcon#about to read 4, iclass 32, count 0 2006.168.07:34:38.26#ibcon#read 4, iclass 32, count 0 2006.168.07:34:38.26#ibcon#about to read 5, iclass 32, count 0 2006.168.07:34:38.26#ibcon#read 5, iclass 32, count 0 2006.168.07:34:38.26#ibcon#about to read 6, iclass 32, count 0 2006.168.07:34:38.26#ibcon#read 6, iclass 32, count 0 2006.168.07:34:38.26#ibcon#end of sib2, iclass 32, count 0 2006.168.07:34:38.26#ibcon#*mode == 0, iclass 32, count 0 2006.168.07:34:38.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.168.07:34:38.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.07:34:38.26#ibcon#*before write, iclass 32, count 0 2006.168.07:34:38.26#ibcon#enter sib2, iclass 32, count 0 2006.168.07:34:38.26#ibcon#flushed, iclass 32, count 0 2006.168.07:34:38.26#ibcon#about to write, iclass 32, count 0 2006.168.07:34:38.26#ibcon#wrote, iclass 32, count 0 2006.168.07:34:38.26#ibcon#about to read 3, iclass 32, count 0 2006.168.07:34:38.30#ibcon#read 3, iclass 32, count 0 2006.168.07:34:38.30#ibcon#about to read 4, iclass 32, count 0 2006.168.07:34:38.30#ibcon#read 4, iclass 32, count 0 2006.168.07:34:38.30#ibcon#about to read 5, iclass 32, count 0 2006.168.07:34:38.30#ibcon#read 5, iclass 32, count 0 2006.168.07:34:38.30#ibcon#about to read 6, iclass 32, count 0 2006.168.07:34:38.30#ibcon#read 6, iclass 32, count 0 2006.168.07:34:38.30#ibcon#end of sib2, iclass 32, count 0 2006.168.07:34:38.30#ibcon#*after write, iclass 32, count 0 2006.168.07:34:38.30#ibcon#*before return 0, iclass 32, count 0 2006.168.07:34:38.30#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:34:38.30#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:34:38.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.168.07:34:38.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.168.07:34:38.30$vc4f8/va=2,7 2006.168.07:34:38.30#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.168.07:34:38.30#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.168.07:34:38.30#ibcon#ireg 11 cls_cnt 2 2006.168.07:34:38.30#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:34:38.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:34:38.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:34:38.36#ibcon#enter wrdev, iclass 34, count 2 2006.168.07:34:38.36#ibcon#first serial, iclass 34, count 2 2006.168.07:34:38.36#ibcon#enter sib2, iclass 34, count 2 2006.168.07:34:38.36#ibcon#flushed, iclass 34, count 2 2006.168.07:34:38.36#ibcon#about to write, iclass 34, count 2 2006.168.07:34:38.36#ibcon#wrote, iclass 34, count 2 2006.168.07:34:38.36#ibcon#about to read 3, iclass 34, count 2 2006.168.07:34:38.38#ibcon#read 3, iclass 34, count 2 2006.168.07:34:38.38#ibcon#about to read 4, iclass 34, count 2 2006.168.07:34:38.38#ibcon#read 4, iclass 34, count 2 2006.168.07:34:38.38#ibcon#about to read 5, iclass 34, count 2 2006.168.07:34:38.38#ibcon#read 5, iclass 34, count 2 2006.168.07:34:38.38#ibcon#about to read 6, iclass 34, count 2 2006.168.07:34:38.38#ibcon#read 6, iclass 34, count 2 2006.168.07:34:38.38#ibcon#end of sib2, iclass 34, count 2 2006.168.07:34:38.38#ibcon#*mode == 0, iclass 34, count 2 2006.168.07:34:38.38#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.168.07:34:38.38#ibcon#[25=AT02-07\r\n] 2006.168.07:34:38.38#ibcon#*before write, iclass 34, count 2 2006.168.07:34:38.38#ibcon#enter sib2, iclass 34, count 2 2006.168.07:34:38.38#ibcon#flushed, iclass 34, count 2 2006.168.07:34:38.38#ibcon#about to write, iclass 34, count 2 2006.168.07:34:38.38#ibcon#wrote, iclass 34, count 2 2006.168.07:34:38.38#ibcon#about to read 3, iclass 34, count 2 2006.168.07:34:38.41#ibcon#read 3, iclass 34, count 2 2006.168.07:34:38.41#ibcon#about to read 4, iclass 34, count 2 2006.168.07:34:38.41#ibcon#read 4, iclass 34, count 2 2006.168.07:34:38.41#ibcon#about to read 5, iclass 34, count 2 2006.168.07:34:38.41#ibcon#read 5, iclass 34, count 2 2006.168.07:34:38.41#ibcon#about to read 6, iclass 34, count 2 2006.168.07:34:38.41#ibcon#read 6, iclass 34, count 2 2006.168.07:34:38.41#ibcon#end of sib2, iclass 34, count 2 2006.168.07:34:38.41#ibcon#*after write, iclass 34, count 2 2006.168.07:34:38.41#ibcon#*before return 0, iclass 34, count 2 2006.168.07:34:38.41#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:34:38.41#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:34:38.41#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.168.07:34:38.41#ibcon#ireg 7 cls_cnt 0 2006.168.07:34:38.41#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:34:38.53#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:34:38.53#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:34:38.53#ibcon#enter wrdev, iclass 34, count 0 2006.168.07:34:38.53#ibcon#first serial, iclass 34, count 0 2006.168.07:34:38.53#ibcon#enter sib2, iclass 34, count 0 2006.168.07:34:38.53#ibcon#flushed, iclass 34, count 0 2006.168.07:34:38.53#ibcon#about to write, iclass 34, count 0 2006.168.07:34:38.53#ibcon#wrote, iclass 34, count 0 2006.168.07:34:38.53#ibcon#about to read 3, iclass 34, count 0 2006.168.07:34:38.55#ibcon#read 3, iclass 34, count 0 2006.168.07:34:38.55#ibcon#about to read 4, iclass 34, count 0 2006.168.07:34:38.55#ibcon#read 4, iclass 34, count 0 2006.168.07:34:38.55#ibcon#about to read 5, iclass 34, count 0 2006.168.07:34:38.55#ibcon#read 5, iclass 34, count 0 2006.168.07:34:38.55#ibcon#about to read 6, iclass 34, count 0 2006.168.07:34:38.55#ibcon#read 6, iclass 34, count 0 2006.168.07:34:38.55#ibcon#end of sib2, iclass 34, count 0 2006.168.07:34:38.55#ibcon#*mode == 0, iclass 34, count 0 2006.168.07:34:38.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.168.07:34:38.55#ibcon#[25=USB\r\n] 2006.168.07:34:38.55#ibcon#*before write, iclass 34, count 0 2006.168.07:34:38.55#ibcon#enter sib2, iclass 34, count 0 2006.168.07:34:38.55#ibcon#flushed, iclass 34, count 0 2006.168.07:34:38.55#ibcon#about to write, iclass 34, count 0 2006.168.07:34:38.55#ibcon#wrote, iclass 34, count 0 2006.168.07:34:38.55#ibcon#about to read 3, iclass 34, count 0 2006.168.07:34:38.58#ibcon#read 3, iclass 34, count 0 2006.168.07:34:38.58#ibcon#about to read 4, iclass 34, count 0 2006.168.07:34:38.58#ibcon#read 4, iclass 34, count 0 2006.168.07:34:38.58#ibcon#about to read 5, iclass 34, count 0 2006.168.07:34:38.58#ibcon#read 5, iclass 34, count 0 2006.168.07:34:38.58#ibcon#about to read 6, iclass 34, count 0 2006.168.07:34:38.58#ibcon#read 6, iclass 34, count 0 2006.168.07:34:38.58#ibcon#end of sib2, iclass 34, count 0 2006.168.07:34:38.58#ibcon#*after write, iclass 34, count 0 2006.168.07:34:38.58#ibcon#*before return 0, iclass 34, count 0 2006.168.07:34:38.58#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:34:38.58#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:34:38.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.168.07:34:38.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.168.07:34:38.58$vc4f8/valo=3,672.99 2006.168.07:34:38.58#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.168.07:34:38.58#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.168.07:34:38.58#ibcon#ireg 17 cls_cnt 0 2006.168.07:34:38.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:34:38.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:34:38.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:34:38.58#ibcon#enter wrdev, iclass 36, count 0 2006.168.07:34:38.58#ibcon#first serial, iclass 36, count 0 2006.168.07:34:38.58#ibcon#enter sib2, iclass 36, count 0 2006.168.07:34:38.58#ibcon#flushed, iclass 36, count 0 2006.168.07:34:38.58#ibcon#about to write, iclass 36, count 0 2006.168.07:34:38.58#ibcon#wrote, iclass 36, count 0 2006.168.07:34:38.58#ibcon#about to read 3, iclass 36, count 0 2006.168.07:34:38.60#ibcon#read 3, iclass 36, count 0 2006.168.07:34:38.60#ibcon#about to read 4, iclass 36, count 0 2006.168.07:34:38.60#ibcon#read 4, iclass 36, count 0 2006.168.07:34:38.60#ibcon#about to read 5, iclass 36, count 0 2006.168.07:34:38.60#ibcon#read 5, iclass 36, count 0 2006.168.07:34:38.60#ibcon#about to read 6, iclass 36, count 0 2006.168.07:34:38.60#ibcon#read 6, iclass 36, count 0 2006.168.07:34:38.60#ibcon#end of sib2, iclass 36, count 0 2006.168.07:34:38.60#ibcon#*mode == 0, iclass 36, count 0 2006.168.07:34:38.60#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.168.07:34:38.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.07:34:38.60#ibcon#*before write, iclass 36, count 0 2006.168.07:34:38.60#ibcon#enter sib2, iclass 36, count 0 2006.168.07:34:38.60#ibcon#flushed, iclass 36, count 0 2006.168.07:34:38.60#ibcon#about to write, iclass 36, count 0 2006.168.07:34:38.60#ibcon#wrote, iclass 36, count 0 2006.168.07:34:38.60#ibcon#about to read 3, iclass 36, count 0 2006.168.07:34:38.64#ibcon#read 3, iclass 36, count 0 2006.168.07:34:38.64#ibcon#about to read 4, iclass 36, count 0 2006.168.07:34:38.64#ibcon#read 4, iclass 36, count 0 2006.168.07:34:38.64#ibcon#about to read 5, iclass 36, count 0 2006.168.07:34:38.64#ibcon#read 5, iclass 36, count 0 2006.168.07:34:38.64#ibcon#about to read 6, iclass 36, count 0 2006.168.07:34:38.64#ibcon#read 6, iclass 36, count 0 2006.168.07:34:38.64#ibcon#end of sib2, iclass 36, count 0 2006.168.07:34:38.64#ibcon#*after write, iclass 36, count 0 2006.168.07:34:38.64#ibcon#*before return 0, iclass 36, count 0 2006.168.07:34:38.64#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:34:38.64#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:34:38.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.168.07:34:38.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.168.07:34:38.64$vc4f8/va=3,6 2006.168.07:34:38.64#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.168.07:34:38.64#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.168.07:34:38.64#ibcon#ireg 11 cls_cnt 2 2006.168.07:34:38.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.168.07:34:38.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.168.07:34:38.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.168.07:34:38.70#ibcon#enter wrdev, iclass 38, count 2 2006.168.07:34:38.70#ibcon#first serial, iclass 38, count 2 2006.168.07:34:38.70#ibcon#enter sib2, iclass 38, count 2 2006.168.07:34:38.70#ibcon#flushed, iclass 38, count 2 2006.168.07:34:38.70#ibcon#about to write, iclass 38, count 2 2006.168.07:34:38.70#ibcon#wrote, iclass 38, count 2 2006.168.07:34:38.70#ibcon#about to read 3, iclass 38, count 2 2006.168.07:34:38.73#ibcon#read 3, iclass 38, count 2 2006.168.07:34:38.73#ibcon#about to read 4, iclass 38, count 2 2006.168.07:34:38.73#ibcon#read 4, iclass 38, count 2 2006.168.07:34:38.73#ibcon#about to read 5, iclass 38, count 2 2006.168.07:34:38.73#ibcon#read 5, iclass 38, count 2 2006.168.07:34:38.73#ibcon#about to read 6, iclass 38, count 2 2006.168.07:34:38.73#ibcon#read 6, iclass 38, count 2 2006.168.07:34:38.73#ibcon#end of sib2, iclass 38, count 2 2006.168.07:34:38.73#ibcon#*mode == 0, iclass 38, count 2 2006.168.07:34:38.73#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.168.07:34:38.73#ibcon#[25=AT03-06\r\n] 2006.168.07:34:38.73#ibcon#*before write, iclass 38, count 2 2006.168.07:34:38.73#ibcon#enter sib2, iclass 38, count 2 2006.168.07:34:38.73#ibcon#flushed, iclass 38, count 2 2006.168.07:34:38.73#ibcon#about to write, iclass 38, count 2 2006.168.07:34:38.73#ibcon#wrote, iclass 38, count 2 2006.168.07:34:38.73#ibcon#about to read 3, iclass 38, count 2 2006.168.07:34:38.76#ibcon#read 3, iclass 38, count 2 2006.168.07:34:38.76#ibcon#about to read 4, iclass 38, count 2 2006.168.07:34:38.76#ibcon#read 4, iclass 38, count 2 2006.168.07:34:38.76#ibcon#about to read 5, iclass 38, count 2 2006.168.07:34:38.76#ibcon#read 5, iclass 38, count 2 2006.168.07:34:38.76#ibcon#about to read 6, iclass 38, count 2 2006.168.07:34:38.76#ibcon#read 6, iclass 38, count 2 2006.168.07:34:38.76#ibcon#end of sib2, iclass 38, count 2 2006.168.07:34:38.76#ibcon#*after write, iclass 38, count 2 2006.168.07:34:38.76#ibcon#*before return 0, iclass 38, count 2 2006.168.07:34:38.76#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.168.07:34:38.76#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.168.07:34:38.76#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.168.07:34:38.76#ibcon#ireg 7 cls_cnt 0 2006.168.07:34:38.76#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.168.07:34:38.88#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.168.07:34:38.88#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.168.07:34:38.88#ibcon#enter wrdev, iclass 38, count 0 2006.168.07:34:38.88#ibcon#first serial, iclass 38, count 0 2006.168.07:34:38.88#ibcon#enter sib2, iclass 38, count 0 2006.168.07:34:38.88#ibcon#flushed, iclass 38, count 0 2006.168.07:34:38.88#ibcon#about to write, iclass 38, count 0 2006.168.07:34:38.88#ibcon#wrote, iclass 38, count 0 2006.168.07:34:38.88#ibcon#about to read 3, iclass 38, count 0 2006.168.07:34:38.90#ibcon#read 3, iclass 38, count 0 2006.168.07:34:38.90#ibcon#about to read 4, iclass 38, count 0 2006.168.07:34:38.90#ibcon#read 4, iclass 38, count 0 2006.168.07:34:38.90#ibcon#about to read 5, iclass 38, count 0 2006.168.07:34:38.90#ibcon#read 5, iclass 38, count 0 2006.168.07:34:38.90#ibcon#about to read 6, iclass 38, count 0 2006.168.07:34:38.90#ibcon#read 6, iclass 38, count 0 2006.168.07:34:38.90#ibcon#end of sib2, iclass 38, count 0 2006.168.07:34:38.90#ibcon#*mode == 0, iclass 38, count 0 2006.168.07:34:38.90#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.168.07:34:38.90#ibcon#[25=USB\r\n] 2006.168.07:34:38.90#ibcon#*before write, iclass 38, count 0 2006.168.07:34:38.90#ibcon#enter sib2, iclass 38, count 0 2006.168.07:34:38.90#ibcon#flushed, iclass 38, count 0 2006.168.07:34:38.90#ibcon#about to write, iclass 38, count 0 2006.168.07:34:38.90#ibcon#wrote, iclass 38, count 0 2006.168.07:34:38.90#ibcon#about to read 3, iclass 38, count 0 2006.168.07:34:38.90#abcon#<5=/08 1.5 5.4 27.90 731004.6\r\n> 2006.168.07:34:38.92#abcon#{5=INTERFACE CLEAR} 2006.168.07:34:38.93#ibcon#read 3, iclass 38, count 0 2006.168.07:34:38.93#ibcon#about to read 4, iclass 38, count 0 2006.168.07:34:38.93#ibcon#read 4, iclass 38, count 0 2006.168.07:34:38.93#ibcon#about to read 5, iclass 38, count 0 2006.168.07:34:38.93#ibcon#read 5, iclass 38, count 0 2006.168.07:34:38.93#ibcon#about to read 6, iclass 38, count 0 2006.168.07:34:38.93#ibcon#read 6, iclass 38, count 0 2006.168.07:34:38.93#ibcon#end of sib2, iclass 38, count 0 2006.168.07:34:38.93#ibcon#*after write, iclass 38, count 0 2006.168.07:34:38.93#ibcon#*before return 0, iclass 38, count 0 2006.168.07:34:38.93#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.168.07:34:38.93#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.168.07:34:38.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.168.07:34:38.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.168.07:34:38.93$vc4f8/valo=4,832.99 2006.168.07:34:38.93#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.168.07:34:38.93#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.168.07:34:38.93#ibcon#ireg 17 cls_cnt 0 2006.168.07:34:38.93#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.168.07:34:38.93#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.168.07:34:38.93#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.168.07:34:38.93#ibcon#enter wrdev, iclass 5, count 0 2006.168.07:34:38.93#ibcon#first serial, iclass 5, count 0 2006.168.07:34:38.93#ibcon#enter sib2, iclass 5, count 0 2006.168.07:34:38.93#ibcon#flushed, iclass 5, count 0 2006.168.07:34:38.93#ibcon#about to write, iclass 5, count 0 2006.168.07:34:38.93#ibcon#wrote, iclass 5, count 0 2006.168.07:34:38.93#ibcon#about to read 3, iclass 5, count 0 2006.168.07:34:38.95#ibcon#read 3, iclass 5, count 0 2006.168.07:34:38.95#ibcon#about to read 4, iclass 5, count 0 2006.168.07:34:38.95#ibcon#read 4, iclass 5, count 0 2006.168.07:34:38.95#ibcon#about to read 5, iclass 5, count 0 2006.168.07:34:38.95#ibcon#read 5, iclass 5, count 0 2006.168.07:34:38.95#ibcon#about to read 6, iclass 5, count 0 2006.168.07:34:38.95#ibcon#read 6, iclass 5, count 0 2006.168.07:34:38.95#ibcon#end of sib2, iclass 5, count 0 2006.168.07:34:38.95#ibcon#*mode == 0, iclass 5, count 0 2006.168.07:34:38.95#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.168.07:34:38.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.07:34:38.95#ibcon#*before write, iclass 5, count 0 2006.168.07:34:38.95#ibcon#enter sib2, iclass 5, count 0 2006.168.07:34:38.95#ibcon#flushed, iclass 5, count 0 2006.168.07:34:38.95#ibcon#about to write, iclass 5, count 0 2006.168.07:34:38.95#ibcon#wrote, iclass 5, count 0 2006.168.07:34:38.95#ibcon#about to read 3, iclass 5, count 0 2006.168.07:34:38.98#abcon#[5=S1D000X0/0*\r\n] 2006.168.07:34:38.99#ibcon#read 3, iclass 5, count 0 2006.168.07:34:38.99#ibcon#about to read 4, iclass 5, count 0 2006.168.07:34:38.99#ibcon#read 4, iclass 5, count 0 2006.168.07:34:38.99#ibcon#about to read 5, iclass 5, count 0 2006.168.07:34:38.99#ibcon#read 5, iclass 5, count 0 2006.168.07:34:38.99#ibcon#about to read 6, iclass 5, count 0 2006.168.07:34:38.99#ibcon#read 6, iclass 5, count 0 2006.168.07:34:38.99#ibcon#end of sib2, iclass 5, count 0 2006.168.07:34:38.99#ibcon#*after write, iclass 5, count 0 2006.168.07:34:38.99#ibcon#*before return 0, iclass 5, count 0 2006.168.07:34:38.99#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.168.07:34:38.99#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.168.07:34:38.99#ibcon#about to clear, iclass 5 cls_cnt 0 2006.168.07:34:38.99#ibcon#cleared, iclass 5 cls_cnt 0 2006.168.07:34:38.99$vc4f8/va=4,7 2006.168.07:34:38.99#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.168.07:34:38.99#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.168.07:34:38.99#ibcon#ireg 11 cls_cnt 2 2006.168.07:34:38.99#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.168.07:34:39.05#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.168.07:34:39.05#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.168.07:34:39.05#ibcon#enter wrdev, iclass 10, count 2 2006.168.07:34:39.05#ibcon#first serial, iclass 10, count 2 2006.168.07:34:39.05#ibcon#enter sib2, iclass 10, count 2 2006.168.07:34:39.05#ibcon#flushed, iclass 10, count 2 2006.168.07:34:39.05#ibcon#about to write, iclass 10, count 2 2006.168.07:34:39.05#ibcon#wrote, iclass 10, count 2 2006.168.07:34:39.05#ibcon#about to read 3, iclass 10, count 2 2006.168.07:34:39.07#ibcon#read 3, iclass 10, count 2 2006.168.07:34:39.07#ibcon#about to read 4, iclass 10, count 2 2006.168.07:34:39.07#ibcon#read 4, iclass 10, count 2 2006.168.07:34:39.07#ibcon#about to read 5, iclass 10, count 2 2006.168.07:34:39.07#ibcon#read 5, iclass 10, count 2 2006.168.07:34:39.07#ibcon#about to read 6, iclass 10, count 2 2006.168.07:34:39.07#ibcon#read 6, iclass 10, count 2 2006.168.07:34:39.07#ibcon#end of sib2, iclass 10, count 2 2006.168.07:34:39.07#ibcon#*mode == 0, iclass 10, count 2 2006.168.07:34:39.07#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.168.07:34:39.07#ibcon#[25=AT04-07\r\n] 2006.168.07:34:39.07#ibcon#*before write, iclass 10, count 2 2006.168.07:34:39.07#ibcon#enter sib2, iclass 10, count 2 2006.168.07:34:39.07#ibcon#flushed, iclass 10, count 2 2006.168.07:34:39.07#ibcon#about to write, iclass 10, count 2 2006.168.07:34:39.07#ibcon#wrote, iclass 10, count 2 2006.168.07:34:39.07#ibcon#about to read 3, iclass 10, count 2 2006.168.07:34:39.10#ibcon#read 3, iclass 10, count 2 2006.168.07:34:39.10#ibcon#about to read 4, iclass 10, count 2 2006.168.07:34:39.10#ibcon#read 4, iclass 10, count 2 2006.168.07:34:39.10#ibcon#about to read 5, iclass 10, count 2 2006.168.07:34:39.10#ibcon#read 5, iclass 10, count 2 2006.168.07:34:39.10#ibcon#about to read 6, iclass 10, count 2 2006.168.07:34:39.10#ibcon#read 6, iclass 10, count 2 2006.168.07:34:39.10#ibcon#end of sib2, iclass 10, count 2 2006.168.07:34:39.10#ibcon#*after write, iclass 10, count 2 2006.168.07:34:39.10#ibcon#*before return 0, iclass 10, count 2 2006.168.07:34:39.10#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.168.07:34:39.10#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.168.07:34:39.10#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.168.07:34:39.10#ibcon#ireg 7 cls_cnt 0 2006.168.07:34:39.10#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.168.07:34:39.22#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.168.07:34:39.22#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.168.07:34:39.22#ibcon#enter wrdev, iclass 10, count 0 2006.168.07:34:39.22#ibcon#first serial, iclass 10, count 0 2006.168.07:34:39.22#ibcon#enter sib2, iclass 10, count 0 2006.168.07:34:39.22#ibcon#flushed, iclass 10, count 0 2006.168.07:34:39.22#ibcon#about to write, iclass 10, count 0 2006.168.07:34:39.22#ibcon#wrote, iclass 10, count 0 2006.168.07:34:39.22#ibcon#about to read 3, iclass 10, count 0 2006.168.07:34:39.24#ibcon#read 3, iclass 10, count 0 2006.168.07:34:39.24#ibcon#about to read 4, iclass 10, count 0 2006.168.07:34:39.24#ibcon#read 4, iclass 10, count 0 2006.168.07:34:39.24#ibcon#about to read 5, iclass 10, count 0 2006.168.07:34:39.24#ibcon#read 5, iclass 10, count 0 2006.168.07:34:39.24#ibcon#about to read 6, iclass 10, count 0 2006.168.07:34:39.24#ibcon#read 6, iclass 10, count 0 2006.168.07:34:39.24#ibcon#end of sib2, iclass 10, count 0 2006.168.07:34:39.24#ibcon#*mode == 0, iclass 10, count 0 2006.168.07:34:39.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.168.07:34:39.24#ibcon#[25=USB\r\n] 2006.168.07:34:39.24#ibcon#*before write, iclass 10, count 0 2006.168.07:34:39.24#ibcon#enter sib2, iclass 10, count 0 2006.168.07:34:39.24#ibcon#flushed, iclass 10, count 0 2006.168.07:34:39.24#ibcon#about to write, iclass 10, count 0 2006.168.07:34:39.24#ibcon#wrote, iclass 10, count 0 2006.168.07:34:39.24#ibcon#about to read 3, iclass 10, count 0 2006.168.07:34:39.27#ibcon#read 3, iclass 10, count 0 2006.168.07:34:39.27#ibcon#about to read 4, iclass 10, count 0 2006.168.07:34:39.27#ibcon#read 4, iclass 10, count 0 2006.168.07:34:39.27#ibcon#about to read 5, iclass 10, count 0 2006.168.07:34:39.27#ibcon#read 5, iclass 10, count 0 2006.168.07:34:39.27#ibcon#about to read 6, iclass 10, count 0 2006.168.07:34:39.27#ibcon#read 6, iclass 10, count 0 2006.168.07:34:39.27#ibcon#end of sib2, iclass 10, count 0 2006.168.07:34:39.27#ibcon#*after write, iclass 10, count 0 2006.168.07:34:39.27#ibcon#*before return 0, iclass 10, count 0 2006.168.07:34:39.27#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.168.07:34:39.27#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.168.07:34:39.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.168.07:34:39.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.168.07:34:39.27$vc4f8/valo=5,652.99 2006.168.07:34:39.27#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.168.07:34:39.27#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.168.07:34:39.27#ibcon#ireg 17 cls_cnt 0 2006.168.07:34:39.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.168.07:34:39.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.168.07:34:39.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.168.07:34:39.27#ibcon#enter wrdev, iclass 12, count 0 2006.168.07:34:39.27#ibcon#first serial, iclass 12, count 0 2006.168.07:34:39.27#ibcon#enter sib2, iclass 12, count 0 2006.168.07:34:39.27#ibcon#flushed, iclass 12, count 0 2006.168.07:34:39.27#ibcon#about to write, iclass 12, count 0 2006.168.07:34:39.27#ibcon#wrote, iclass 12, count 0 2006.168.07:34:39.27#ibcon#about to read 3, iclass 12, count 0 2006.168.07:34:39.29#ibcon#read 3, iclass 12, count 0 2006.168.07:34:39.29#ibcon#about to read 4, iclass 12, count 0 2006.168.07:34:39.29#ibcon#read 4, iclass 12, count 0 2006.168.07:34:39.29#ibcon#about to read 5, iclass 12, count 0 2006.168.07:34:39.29#ibcon#read 5, iclass 12, count 0 2006.168.07:34:39.29#ibcon#about to read 6, iclass 12, count 0 2006.168.07:34:39.29#ibcon#read 6, iclass 12, count 0 2006.168.07:34:39.29#ibcon#end of sib2, iclass 12, count 0 2006.168.07:34:39.29#ibcon#*mode == 0, iclass 12, count 0 2006.168.07:34:39.29#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.168.07:34:39.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.07:34:39.29#ibcon#*before write, iclass 12, count 0 2006.168.07:34:39.29#ibcon#enter sib2, iclass 12, count 0 2006.168.07:34:39.29#ibcon#flushed, iclass 12, count 0 2006.168.07:34:39.29#ibcon#about to write, iclass 12, count 0 2006.168.07:34:39.29#ibcon#wrote, iclass 12, count 0 2006.168.07:34:39.29#ibcon#about to read 3, iclass 12, count 0 2006.168.07:34:39.33#ibcon#read 3, iclass 12, count 0 2006.168.07:34:39.33#ibcon#about to read 4, iclass 12, count 0 2006.168.07:34:39.33#ibcon#read 4, iclass 12, count 0 2006.168.07:34:39.33#ibcon#about to read 5, iclass 12, count 0 2006.168.07:34:39.33#ibcon#read 5, iclass 12, count 0 2006.168.07:34:39.33#ibcon#about to read 6, iclass 12, count 0 2006.168.07:34:39.33#ibcon#read 6, iclass 12, count 0 2006.168.07:34:39.33#ibcon#end of sib2, iclass 12, count 0 2006.168.07:34:39.33#ibcon#*after write, iclass 12, count 0 2006.168.07:34:39.33#ibcon#*before return 0, iclass 12, count 0 2006.168.07:34:39.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.168.07:34:39.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.168.07:34:39.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.168.07:34:39.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.168.07:34:39.33$vc4f8/va=5,7 2006.168.07:34:39.33#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.168.07:34:39.33#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.168.07:34:39.33#ibcon#ireg 11 cls_cnt 2 2006.168.07:34:39.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.168.07:34:39.39#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.168.07:34:39.39#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.168.07:34:39.39#ibcon#enter wrdev, iclass 14, count 2 2006.168.07:34:39.39#ibcon#first serial, iclass 14, count 2 2006.168.07:34:39.39#ibcon#enter sib2, iclass 14, count 2 2006.168.07:34:39.39#ibcon#flushed, iclass 14, count 2 2006.168.07:34:39.39#ibcon#about to write, iclass 14, count 2 2006.168.07:34:39.39#ibcon#wrote, iclass 14, count 2 2006.168.07:34:39.39#ibcon#about to read 3, iclass 14, count 2 2006.168.07:34:39.41#ibcon#read 3, iclass 14, count 2 2006.168.07:34:39.41#ibcon#about to read 4, iclass 14, count 2 2006.168.07:34:39.41#ibcon#read 4, iclass 14, count 2 2006.168.07:34:39.41#ibcon#about to read 5, iclass 14, count 2 2006.168.07:34:39.41#ibcon#read 5, iclass 14, count 2 2006.168.07:34:39.41#ibcon#about to read 6, iclass 14, count 2 2006.168.07:34:39.41#ibcon#read 6, iclass 14, count 2 2006.168.07:34:39.41#ibcon#end of sib2, iclass 14, count 2 2006.168.07:34:39.41#ibcon#*mode == 0, iclass 14, count 2 2006.168.07:34:39.41#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.168.07:34:39.41#ibcon#[25=AT05-07\r\n] 2006.168.07:34:39.41#ibcon#*before write, iclass 14, count 2 2006.168.07:34:39.41#ibcon#enter sib2, iclass 14, count 2 2006.168.07:34:39.41#ibcon#flushed, iclass 14, count 2 2006.168.07:34:39.41#ibcon#about to write, iclass 14, count 2 2006.168.07:34:39.41#ibcon#wrote, iclass 14, count 2 2006.168.07:34:39.41#ibcon#about to read 3, iclass 14, count 2 2006.168.07:34:39.44#ibcon#read 3, iclass 14, count 2 2006.168.07:34:39.44#ibcon#about to read 4, iclass 14, count 2 2006.168.07:34:39.44#ibcon#read 4, iclass 14, count 2 2006.168.07:34:39.44#ibcon#about to read 5, iclass 14, count 2 2006.168.07:34:39.44#ibcon#read 5, iclass 14, count 2 2006.168.07:34:39.44#ibcon#about to read 6, iclass 14, count 2 2006.168.07:34:39.44#ibcon#read 6, iclass 14, count 2 2006.168.07:34:39.44#ibcon#end of sib2, iclass 14, count 2 2006.168.07:34:39.44#ibcon#*after write, iclass 14, count 2 2006.168.07:34:39.44#ibcon#*before return 0, iclass 14, count 2 2006.168.07:34:39.44#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.168.07:34:39.44#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.168.07:34:39.44#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.168.07:34:39.44#ibcon#ireg 7 cls_cnt 0 2006.168.07:34:39.44#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.168.07:34:39.56#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.168.07:34:39.56#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.168.07:34:39.56#ibcon#enter wrdev, iclass 14, count 0 2006.168.07:34:39.56#ibcon#first serial, iclass 14, count 0 2006.168.07:34:39.56#ibcon#enter sib2, iclass 14, count 0 2006.168.07:34:39.56#ibcon#flushed, iclass 14, count 0 2006.168.07:34:39.56#ibcon#about to write, iclass 14, count 0 2006.168.07:34:39.56#ibcon#wrote, iclass 14, count 0 2006.168.07:34:39.56#ibcon#about to read 3, iclass 14, count 0 2006.168.07:34:39.58#ibcon#read 3, iclass 14, count 0 2006.168.07:34:39.58#ibcon#about to read 4, iclass 14, count 0 2006.168.07:34:39.58#ibcon#read 4, iclass 14, count 0 2006.168.07:34:39.58#ibcon#about to read 5, iclass 14, count 0 2006.168.07:34:39.58#ibcon#read 5, iclass 14, count 0 2006.168.07:34:39.58#ibcon#about to read 6, iclass 14, count 0 2006.168.07:34:39.58#ibcon#read 6, iclass 14, count 0 2006.168.07:34:39.58#ibcon#end of sib2, iclass 14, count 0 2006.168.07:34:39.58#ibcon#*mode == 0, iclass 14, count 0 2006.168.07:34:39.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.168.07:34:39.58#ibcon#[25=USB\r\n] 2006.168.07:34:39.58#ibcon#*before write, iclass 14, count 0 2006.168.07:34:39.58#ibcon#enter sib2, iclass 14, count 0 2006.168.07:34:39.58#ibcon#flushed, iclass 14, count 0 2006.168.07:34:39.58#ibcon#about to write, iclass 14, count 0 2006.168.07:34:39.58#ibcon#wrote, iclass 14, count 0 2006.168.07:34:39.58#ibcon#about to read 3, iclass 14, count 0 2006.168.07:34:39.61#ibcon#read 3, iclass 14, count 0 2006.168.07:34:39.61#ibcon#about to read 4, iclass 14, count 0 2006.168.07:34:39.61#ibcon#read 4, iclass 14, count 0 2006.168.07:34:39.61#ibcon#about to read 5, iclass 14, count 0 2006.168.07:34:39.61#ibcon#read 5, iclass 14, count 0 2006.168.07:34:39.61#ibcon#about to read 6, iclass 14, count 0 2006.168.07:34:39.61#ibcon#read 6, iclass 14, count 0 2006.168.07:34:39.61#ibcon#end of sib2, iclass 14, count 0 2006.168.07:34:39.61#ibcon#*after write, iclass 14, count 0 2006.168.07:34:39.61#ibcon#*before return 0, iclass 14, count 0 2006.168.07:34:39.61#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.168.07:34:39.61#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.168.07:34:39.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.168.07:34:39.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.168.07:34:39.61$vc4f8/valo=6,772.99 2006.168.07:34:39.61#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.168.07:34:39.61#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.168.07:34:39.61#ibcon#ireg 17 cls_cnt 0 2006.168.07:34:39.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:34:39.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:34:39.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:34:39.61#ibcon#enter wrdev, iclass 16, count 0 2006.168.07:34:39.61#ibcon#first serial, iclass 16, count 0 2006.168.07:34:39.61#ibcon#enter sib2, iclass 16, count 0 2006.168.07:34:39.61#ibcon#flushed, iclass 16, count 0 2006.168.07:34:39.61#ibcon#about to write, iclass 16, count 0 2006.168.07:34:39.61#ibcon#wrote, iclass 16, count 0 2006.168.07:34:39.61#ibcon#about to read 3, iclass 16, count 0 2006.168.07:34:39.63#ibcon#read 3, iclass 16, count 0 2006.168.07:34:39.63#ibcon#about to read 4, iclass 16, count 0 2006.168.07:34:39.63#ibcon#read 4, iclass 16, count 0 2006.168.07:34:39.63#ibcon#about to read 5, iclass 16, count 0 2006.168.07:34:39.63#ibcon#read 5, iclass 16, count 0 2006.168.07:34:39.63#ibcon#about to read 6, iclass 16, count 0 2006.168.07:34:39.63#ibcon#read 6, iclass 16, count 0 2006.168.07:34:39.63#ibcon#end of sib2, iclass 16, count 0 2006.168.07:34:39.63#ibcon#*mode == 0, iclass 16, count 0 2006.168.07:34:39.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.168.07:34:39.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.07:34:39.63#ibcon#*before write, iclass 16, count 0 2006.168.07:34:39.63#ibcon#enter sib2, iclass 16, count 0 2006.168.07:34:39.63#ibcon#flushed, iclass 16, count 0 2006.168.07:34:39.63#ibcon#about to write, iclass 16, count 0 2006.168.07:34:39.63#ibcon#wrote, iclass 16, count 0 2006.168.07:34:39.63#ibcon#about to read 3, iclass 16, count 0 2006.168.07:34:39.67#ibcon#read 3, iclass 16, count 0 2006.168.07:34:39.67#ibcon#about to read 4, iclass 16, count 0 2006.168.07:34:39.67#ibcon#read 4, iclass 16, count 0 2006.168.07:34:39.67#ibcon#about to read 5, iclass 16, count 0 2006.168.07:34:39.67#ibcon#read 5, iclass 16, count 0 2006.168.07:34:39.67#ibcon#about to read 6, iclass 16, count 0 2006.168.07:34:39.67#ibcon#read 6, iclass 16, count 0 2006.168.07:34:39.67#ibcon#end of sib2, iclass 16, count 0 2006.168.07:34:39.67#ibcon#*after write, iclass 16, count 0 2006.168.07:34:39.67#ibcon#*before return 0, iclass 16, count 0 2006.168.07:34:39.67#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:34:39.67#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:34:39.67#ibcon#about to clear, iclass 16 cls_cnt 0 2006.168.07:34:39.67#ibcon#cleared, iclass 16 cls_cnt 0 2006.168.07:34:39.67$vc4f8/va=6,6 2006.168.07:34:39.67#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.168.07:34:39.67#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.168.07:34:39.67#ibcon#ireg 11 cls_cnt 2 2006.168.07:34:39.67#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:34:39.73#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:34:39.73#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:34:39.73#ibcon#enter wrdev, iclass 18, count 2 2006.168.07:34:39.73#ibcon#first serial, iclass 18, count 2 2006.168.07:34:39.73#ibcon#enter sib2, iclass 18, count 2 2006.168.07:34:39.73#ibcon#flushed, iclass 18, count 2 2006.168.07:34:39.73#ibcon#about to write, iclass 18, count 2 2006.168.07:34:39.73#ibcon#wrote, iclass 18, count 2 2006.168.07:34:39.73#ibcon#about to read 3, iclass 18, count 2 2006.168.07:34:39.75#ibcon#read 3, iclass 18, count 2 2006.168.07:34:39.75#ibcon#about to read 4, iclass 18, count 2 2006.168.07:34:39.75#ibcon#read 4, iclass 18, count 2 2006.168.07:34:39.75#ibcon#about to read 5, iclass 18, count 2 2006.168.07:34:39.75#ibcon#read 5, iclass 18, count 2 2006.168.07:34:39.75#ibcon#about to read 6, iclass 18, count 2 2006.168.07:34:39.75#ibcon#read 6, iclass 18, count 2 2006.168.07:34:39.75#ibcon#end of sib2, iclass 18, count 2 2006.168.07:34:39.75#ibcon#*mode == 0, iclass 18, count 2 2006.168.07:34:39.75#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.168.07:34:39.75#ibcon#[25=AT06-06\r\n] 2006.168.07:34:39.75#ibcon#*before write, iclass 18, count 2 2006.168.07:34:39.75#ibcon#enter sib2, iclass 18, count 2 2006.168.07:34:39.75#ibcon#flushed, iclass 18, count 2 2006.168.07:34:39.75#ibcon#about to write, iclass 18, count 2 2006.168.07:34:39.75#ibcon#wrote, iclass 18, count 2 2006.168.07:34:39.75#ibcon#about to read 3, iclass 18, count 2 2006.168.07:34:39.78#ibcon#read 3, iclass 18, count 2 2006.168.07:34:39.78#ibcon#about to read 4, iclass 18, count 2 2006.168.07:34:39.78#ibcon#read 4, iclass 18, count 2 2006.168.07:34:39.78#ibcon#about to read 5, iclass 18, count 2 2006.168.07:34:39.78#ibcon#read 5, iclass 18, count 2 2006.168.07:34:39.78#ibcon#about to read 6, iclass 18, count 2 2006.168.07:34:39.78#ibcon#read 6, iclass 18, count 2 2006.168.07:34:39.78#ibcon#end of sib2, iclass 18, count 2 2006.168.07:34:39.78#ibcon#*after write, iclass 18, count 2 2006.168.07:34:39.78#ibcon#*before return 0, iclass 18, count 2 2006.168.07:34:39.78#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:34:39.78#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:34:39.78#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.168.07:34:39.78#ibcon#ireg 7 cls_cnt 0 2006.168.07:34:39.78#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:34:39.90#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:34:39.90#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:34:39.90#ibcon#enter wrdev, iclass 18, count 0 2006.168.07:34:39.90#ibcon#first serial, iclass 18, count 0 2006.168.07:34:39.90#ibcon#enter sib2, iclass 18, count 0 2006.168.07:34:39.90#ibcon#flushed, iclass 18, count 0 2006.168.07:34:39.90#ibcon#about to write, iclass 18, count 0 2006.168.07:34:39.90#ibcon#wrote, iclass 18, count 0 2006.168.07:34:39.90#ibcon#about to read 3, iclass 18, count 0 2006.168.07:34:39.92#ibcon#read 3, iclass 18, count 0 2006.168.07:34:39.92#ibcon#about to read 4, iclass 18, count 0 2006.168.07:34:39.92#ibcon#read 4, iclass 18, count 0 2006.168.07:34:39.92#ibcon#about to read 5, iclass 18, count 0 2006.168.07:34:39.92#ibcon#read 5, iclass 18, count 0 2006.168.07:34:39.92#ibcon#about to read 6, iclass 18, count 0 2006.168.07:34:39.92#ibcon#read 6, iclass 18, count 0 2006.168.07:34:39.92#ibcon#end of sib2, iclass 18, count 0 2006.168.07:34:39.92#ibcon#*mode == 0, iclass 18, count 0 2006.168.07:34:39.92#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.07:34:39.92#ibcon#[25=USB\r\n] 2006.168.07:34:39.92#ibcon#*before write, iclass 18, count 0 2006.168.07:34:39.92#ibcon#enter sib2, iclass 18, count 0 2006.168.07:34:39.92#ibcon#flushed, iclass 18, count 0 2006.168.07:34:39.92#ibcon#about to write, iclass 18, count 0 2006.168.07:34:39.92#ibcon#wrote, iclass 18, count 0 2006.168.07:34:39.92#ibcon#about to read 3, iclass 18, count 0 2006.168.07:34:39.95#ibcon#read 3, iclass 18, count 0 2006.168.07:34:39.95#ibcon#about to read 4, iclass 18, count 0 2006.168.07:34:39.95#ibcon#read 4, iclass 18, count 0 2006.168.07:34:39.95#ibcon#about to read 5, iclass 18, count 0 2006.168.07:34:39.95#ibcon#read 5, iclass 18, count 0 2006.168.07:34:39.95#ibcon#about to read 6, iclass 18, count 0 2006.168.07:34:39.95#ibcon#read 6, iclass 18, count 0 2006.168.07:34:39.95#ibcon#end of sib2, iclass 18, count 0 2006.168.07:34:39.95#ibcon#*after write, iclass 18, count 0 2006.168.07:34:39.95#ibcon#*before return 0, iclass 18, count 0 2006.168.07:34:39.95#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:34:39.95#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:34:39.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.07:34:39.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.07:34:39.95$vc4f8/valo=7,832.99 2006.168.07:34:39.95#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.168.07:34:39.95#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.168.07:34:39.95#ibcon#ireg 17 cls_cnt 0 2006.168.07:34:39.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:34:39.95#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:34:39.95#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:34:39.95#ibcon#enter wrdev, iclass 20, count 0 2006.168.07:34:39.95#ibcon#first serial, iclass 20, count 0 2006.168.07:34:39.95#ibcon#enter sib2, iclass 20, count 0 2006.168.07:34:39.95#ibcon#flushed, iclass 20, count 0 2006.168.07:34:39.95#ibcon#about to write, iclass 20, count 0 2006.168.07:34:39.95#ibcon#wrote, iclass 20, count 0 2006.168.07:34:39.95#ibcon#about to read 3, iclass 20, count 0 2006.168.07:34:39.97#ibcon#read 3, iclass 20, count 0 2006.168.07:34:39.97#ibcon#about to read 4, iclass 20, count 0 2006.168.07:34:39.97#ibcon#read 4, iclass 20, count 0 2006.168.07:34:39.97#ibcon#about to read 5, iclass 20, count 0 2006.168.07:34:39.97#ibcon#read 5, iclass 20, count 0 2006.168.07:34:39.97#ibcon#about to read 6, iclass 20, count 0 2006.168.07:34:39.97#ibcon#read 6, iclass 20, count 0 2006.168.07:34:39.97#ibcon#end of sib2, iclass 20, count 0 2006.168.07:34:39.97#ibcon#*mode == 0, iclass 20, count 0 2006.168.07:34:39.97#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.168.07:34:39.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.07:34:39.97#ibcon#*before write, iclass 20, count 0 2006.168.07:34:39.97#ibcon#enter sib2, iclass 20, count 0 2006.168.07:34:39.97#ibcon#flushed, iclass 20, count 0 2006.168.07:34:39.97#ibcon#about to write, iclass 20, count 0 2006.168.07:34:39.97#ibcon#wrote, iclass 20, count 0 2006.168.07:34:39.97#ibcon#about to read 3, iclass 20, count 0 2006.168.07:34:40.01#ibcon#read 3, iclass 20, count 0 2006.168.07:34:40.01#ibcon#about to read 4, iclass 20, count 0 2006.168.07:34:40.01#ibcon#read 4, iclass 20, count 0 2006.168.07:34:40.01#ibcon#about to read 5, iclass 20, count 0 2006.168.07:34:40.01#ibcon#read 5, iclass 20, count 0 2006.168.07:34:40.01#ibcon#about to read 6, iclass 20, count 0 2006.168.07:34:40.01#ibcon#read 6, iclass 20, count 0 2006.168.07:34:40.01#ibcon#end of sib2, iclass 20, count 0 2006.168.07:34:40.01#ibcon#*after write, iclass 20, count 0 2006.168.07:34:40.01#ibcon#*before return 0, iclass 20, count 0 2006.168.07:34:40.01#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:34:40.01#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:34:40.01#ibcon#about to clear, iclass 20 cls_cnt 0 2006.168.07:34:40.01#ibcon#cleared, iclass 20 cls_cnt 0 2006.168.07:34:40.01$vc4f8/va=7,6 2006.168.07:34:40.01#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.168.07:34:40.01#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.168.07:34:40.01#ibcon#ireg 11 cls_cnt 2 2006.168.07:34:40.01#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:34:40.07#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:34:40.07#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:34:40.07#ibcon#enter wrdev, iclass 22, count 2 2006.168.07:34:40.07#ibcon#first serial, iclass 22, count 2 2006.168.07:34:40.07#ibcon#enter sib2, iclass 22, count 2 2006.168.07:34:40.07#ibcon#flushed, iclass 22, count 2 2006.168.07:34:40.07#ibcon#about to write, iclass 22, count 2 2006.168.07:34:40.07#ibcon#wrote, iclass 22, count 2 2006.168.07:34:40.07#ibcon#about to read 3, iclass 22, count 2 2006.168.07:34:40.09#ibcon#read 3, iclass 22, count 2 2006.168.07:34:40.09#ibcon#about to read 4, iclass 22, count 2 2006.168.07:34:40.09#ibcon#read 4, iclass 22, count 2 2006.168.07:34:40.09#ibcon#about to read 5, iclass 22, count 2 2006.168.07:34:40.09#ibcon#read 5, iclass 22, count 2 2006.168.07:34:40.09#ibcon#about to read 6, iclass 22, count 2 2006.168.07:34:40.09#ibcon#read 6, iclass 22, count 2 2006.168.07:34:40.09#ibcon#end of sib2, iclass 22, count 2 2006.168.07:34:40.09#ibcon#*mode == 0, iclass 22, count 2 2006.168.07:34:40.09#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.168.07:34:40.09#ibcon#[25=AT07-06\r\n] 2006.168.07:34:40.09#ibcon#*before write, iclass 22, count 2 2006.168.07:34:40.09#ibcon#enter sib2, iclass 22, count 2 2006.168.07:34:40.09#ibcon#flushed, iclass 22, count 2 2006.168.07:34:40.09#ibcon#about to write, iclass 22, count 2 2006.168.07:34:40.09#ibcon#wrote, iclass 22, count 2 2006.168.07:34:40.09#ibcon#about to read 3, iclass 22, count 2 2006.168.07:34:40.12#ibcon#read 3, iclass 22, count 2 2006.168.07:34:40.12#ibcon#about to read 4, iclass 22, count 2 2006.168.07:34:40.12#ibcon#read 4, iclass 22, count 2 2006.168.07:34:40.12#ibcon#about to read 5, iclass 22, count 2 2006.168.07:34:40.12#ibcon#read 5, iclass 22, count 2 2006.168.07:34:40.12#ibcon#about to read 6, iclass 22, count 2 2006.168.07:34:40.12#ibcon#read 6, iclass 22, count 2 2006.168.07:34:40.12#ibcon#end of sib2, iclass 22, count 2 2006.168.07:34:40.12#ibcon#*after write, iclass 22, count 2 2006.168.07:34:40.12#ibcon#*before return 0, iclass 22, count 2 2006.168.07:34:40.12#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:34:40.12#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:34:40.12#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.168.07:34:40.12#ibcon#ireg 7 cls_cnt 0 2006.168.07:34:40.12#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:34:40.24#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:34:40.24#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:34:40.24#ibcon#enter wrdev, iclass 22, count 0 2006.168.07:34:40.24#ibcon#first serial, iclass 22, count 0 2006.168.07:34:40.24#ibcon#enter sib2, iclass 22, count 0 2006.168.07:34:40.24#ibcon#flushed, iclass 22, count 0 2006.168.07:34:40.24#ibcon#about to write, iclass 22, count 0 2006.168.07:34:40.24#ibcon#wrote, iclass 22, count 0 2006.168.07:34:40.24#ibcon#about to read 3, iclass 22, count 0 2006.168.07:34:40.26#ibcon#read 3, iclass 22, count 0 2006.168.07:34:40.26#ibcon#about to read 4, iclass 22, count 0 2006.168.07:34:40.26#ibcon#read 4, iclass 22, count 0 2006.168.07:34:40.26#ibcon#about to read 5, iclass 22, count 0 2006.168.07:34:40.26#ibcon#read 5, iclass 22, count 0 2006.168.07:34:40.26#ibcon#about to read 6, iclass 22, count 0 2006.168.07:34:40.26#ibcon#read 6, iclass 22, count 0 2006.168.07:34:40.26#ibcon#end of sib2, iclass 22, count 0 2006.168.07:34:40.26#ibcon#*mode == 0, iclass 22, count 0 2006.168.07:34:40.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.168.07:34:40.26#ibcon#[25=USB\r\n] 2006.168.07:34:40.26#ibcon#*before write, iclass 22, count 0 2006.168.07:34:40.26#ibcon#enter sib2, iclass 22, count 0 2006.168.07:34:40.26#ibcon#flushed, iclass 22, count 0 2006.168.07:34:40.26#ibcon#about to write, iclass 22, count 0 2006.168.07:34:40.26#ibcon#wrote, iclass 22, count 0 2006.168.07:34:40.26#ibcon#about to read 3, iclass 22, count 0 2006.168.07:34:40.29#ibcon#read 3, iclass 22, count 0 2006.168.07:34:40.29#ibcon#about to read 4, iclass 22, count 0 2006.168.07:34:40.29#ibcon#read 4, iclass 22, count 0 2006.168.07:34:40.29#ibcon#about to read 5, iclass 22, count 0 2006.168.07:34:40.29#ibcon#read 5, iclass 22, count 0 2006.168.07:34:40.29#ibcon#about to read 6, iclass 22, count 0 2006.168.07:34:40.29#ibcon#read 6, iclass 22, count 0 2006.168.07:34:40.29#ibcon#end of sib2, iclass 22, count 0 2006.168.07:34:40.29#ibcon#*after write, iclass 22, count 0 2006.168.07:34:40.29#ibcon#*before return 0, iclass 22, count 0 2006.168.07:34:40.29#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:34:40.29#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:34:40.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.168.07:34:40.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.168.07:34:40.29$vc4f8/valo=8,852.99 2006.168.07:34:40.29#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.168.07:34:40.29#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.168.07:34:40.29#ibcon#ireg 17 cls_cnt 0 2006.168.07:34:40.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.168.07:34:40.29#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.168.07:34:40.29#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.168.07:34:40.29#ibcon#enter wrdev, iclass 24, count 0 2006.168.07:34:40.29#ibcon#first serial, iclass 24, count 0 2006.168.07:34:40.29#ibcon#enter sib2, iclass 24, count 0 2006.168.07:34:40.29#ibcon#flushed, iclass 24, count 0 2006.168.07:34:40.29#ibcon#about to write, iclass 24, count 0 2006.168.07:34:40.29#ibcon#wrote, iclass 24, count 0 2006.168.07:34:40.29#ibcon#about to read 3, iclass 24, count 0 2006.168.07:34:40.31#ibcon#read 3, iclass 24, count 0 2006.168.07:34:40.31#ibcon#about to read 4, iclass 24, count 0 2006.168.07:34:40.31#ibcon#read 4, iclass 24, count 0 2006.168.07:34:40.31#ibcon#about to read 5, iclass 24, count 0 2006.168.07:34:40.31#ibcon#read 5, iclass 24, count 0 2006.168.07:34:40.31#ibcon#about to read 6, iclass 24, count 0 2006.168.07:34:40.31#ibcon#read 6, iclass 24, count 0 2006.168.07:34:40.31#ibcon#end of sib2, iclass 24, count 0 2006.168.07:34:40.31#ibcon#*mode == 0, iclass 24, count 0 2006.168.07:34:40.31#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.168.07:34:40.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.07:34:40.31#ibcon#*before write, iclass 24, count 0 2006.168.07:34:40.31#ibcon#enter sib2, iclass 24, count 0 2006.168.07:34:40.31#ibcon#flushed, iclass 24, count 0 2006.168.07:34:40.31#ibcon#about to write, iclass 24, count 0 2006.168.07:34:40.31#ibcon#wrote, iclass 24, count 0 2006.168.07:34:40.31#ibcon#about to read 3, iclass 24, count 0 2006.168.07:34:40.35#ibcon#read 3, iclass 24, count 0 2006.168.07:34:40.35#ibcon#about to read 4, iclass 24, count 0 2006.168.07:34:40.35#ibcon#read 4, iclass 24, count 0 2006.168.07:34:40.35#ibcon#about to read 5, iclass 24, count 0 2006.168.07:34:40.35#ibcon#read 5, iclass 24, count 0 2006.168.07:34:40.35#ibcon#about to read 6, iclass 24, count 0 2006.168.07:34:40.35#ibcon#read 6, iclass 24, count 0 2006.168.07:34:40.35#ibcon#end of sib2, iclass 24, count 0 2006.168.07:34:40.35#ibcon#*after write, iclass 24, count 0 2006.168.07:34:40.35#ibcon#*before return 0, iclass 24, count 0 2006.168.07:34:40.35#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.168.07:34:40.35#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.168.07:34:40.35#ibcon#about to clear, iclass 24 cls_cnt 0 2006.168.07:34:40.35#ibcon#cleared, iclass 24 cls_cnt 0 2006.168.07:34:40.35$vc4f8/va=8,7 2006.168.07:34:40.35#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.168.07:34:40.35#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.168.07:34:40.35#ibcon#ireg 11 cls_cnt 2 2006.168.07:34:40.35#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.168.07:34:40.41#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.168.07:34:40.41#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.168.07:34:40.41#ibcon#enter wrdev, iclass 26, count 2 2006.168.07:34:40.41#ibcon#first serial, iclass 26, count 2 2006.168.07:34:40.41#ibcon#enter sib2, iclass 26, count 2 2006.168.07:34:40.41#ibcon#flushed, iclass 26, count 2 2006.168.07:34:40.41#ibcon#about to write, iclass 26, count 2 2006.168.07:34:40.41#ibcon#wrote, iclass 26, count 2 2006.168.07:34:40.41#ibcon#about to read 3, iclass 26, count 2 2006.168.07:34:40.43#ibcon#read 3, iclass 26, count 2 2006.168.07:34:40.43#ibcon#about to read 4, iclass 26, count 2 2006.168.07:34:40.43#ibcon#read 4, iclass 26, count 2 2006.168.07:34:40.43#ibcon#about to read 5, iclass 26, count 2 2006.168.07:34:40.43#ibcon#read 5, iclass 26, count 2 2006.168.07:34:40.43#ibcon#about to read 6, iclass 26, count 2 2006.168.07:34:40.43#ibcon#read 6, iclass 26, count 2 2006.168.07:34:40.43#ibcon#end of sib2, iclass 26, count 2 2006.168.07:34:40.43#ibcon#*mode == 0, iclass 26, count 2 2006.168.07:34:40.43#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.168.07:34:40.43#ibcon#[25=AT08-07\r\n] 2006.168.07:34:40.43#ibcon#*before write, iclass 26, count 2 2006.168.07:34:40.43#ibcon#enter sib2, iclass 26, count 2 2006.168.07:34:40.43#ibcon#flushed, iclass 26, count 2 2006.168.07:34:40.43#ibcon#about to write, iclass 26, count 2 2006.168.07:34:40.43#ibcon#wrote, iclass 26, count 2 2006.168.07:34:40.43#ibcon#about to read 3, iclass 26, count 2 2006.168.07:34:40.46#ibcon#read 3, iclass 26, count 2 2006.168.07:34:40.46#ibcon#about to read 4, iclass 26, count 2 2006.168.07:34:40.46#ibcon#read 4, iclass 26, count 2 2006.168.07:34:40.46#ibcon#about to read 5, iclass 26, count 2 2006.168.07:34:40.46#ibcon#read 5, iclass 26, count 2 2006.168.07:34:40.46#ibcon#about to read 6, iclass 26, count 2 2006.168.07:34:40.46#ibcon#read 6, iclass 26, count 2 2006.168.07:34:40.46#ibcon#end of sib2, iclass 26, count 2 2006.168.07:34:40.46#ibcon#*after write, iclass 26, count 2 2006.168.07:34:40.46#ibcon#*before return 0, iclass 26, count 2 2006.168.07:34:40.46#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.168.07:34:40.46#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.168.07:34:40.46#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.168.07:34:40.46#ibcon#ireg 7 cls_cnt 0 2006.168.07:34:40.46#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.168.07:34:40.58#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.168.07:34:40.58#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.168.07:34:40.58#ibcon#enter wrdev, iclass 26, count 0 2006.168.07:34:40.58#ibcon#first serial, iclass 26, count 0 2006.168.07:34:40.58#ibcon#enter sib2, iclass 26, count 0 2006.168.07:34:40.58#ibcon#flushed, iclass 26, count 0 2006.168.07:34:40.58#ibcon#about to write, iclass 26, count 0 2006.168.07:34:40.58#ibcon#wrote, iclass 26, count 0 2006.168.07:34:40.58#ibcon#about to read 3, iclass 26, count 0 2006.168.07:34:40.60#ibcon#read 3, iclass 26, count 0 2006.168.07:34:40.60#ibcon#about to read 4, iclass 26, count 0 2006.168.07:34:40.60#ibcon#read 4, iclass 26, count 0 2006.168.07:34:40.60#ibcon#about to read 5, iclass 26, count 0 2006.168.07:34:40.60#ibcon#read 5, iclass 26, count 0 2006.168.07:34:40.60#ibcon#about to read 6, iclass 26, count 0 2006.168.07:34:40.60#ibcon#read 6, iclass 26, count 0 2006.168.07:34:40.60#ibcon#end of sib2, iclass 26, count 0 2006.168.07:34:40.60#ibcon#*mode == 0, iclass 26, count 0 2006.168.07:34:40.60#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.168.07:34:40.60#ibcon#[25=USB\r\n] 2006.168.07:34:40.60#ibcon#*before write, iclass 26, count 0 2006.168.07:34:40.60#ibcon#enter sib2, iclass 26, count 0 2006.168.07:34:40.60#ibcon#flushed, iclass 26, count 0 2006.168.07:34:40.60#ibcon#about to write, iclass 26, count 0 2006.168.07:34:40.60#ibcon#wrote, iclass 26, count 0 2006.168.07:34:40.60#ibcon#about to read 3, iclass 26, count 0 2006.168.07:34:40.63#ibcon#read 3, iclass 26, count 0 2006.168.07:34:40.63#ibcon#about to read 4, iclass 26, count 0 2006.168.07:34:40.63#ibcon#read 4, iclass 26, count 0 2006.168.07:34:40.63#ibcon#about to read 5, iclass 26, count 0 2006.168.07:34:40.63#ibcon#read 5, iclass 26, count 0 2006.168.07:34:40.63#ibcon#about to read 6, iclass 26, count 0 2006.168.07:34:40.63#ibcon#read 6, iclass 26, count 0 2006.168.07:34:40.63#ibcon#end of sib2, iclass 26, count 0 2006.168.07:34:40.63#ibcon#*after write, iclass 26, count 0 2006.168.07:34:40.63#ibcon#*before return 0, iclass 26, count 0 2006.168.07:34:40.63#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.168.07:34:40.63#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.168.07:34:40.63#ibcon#about to clear, iclass 26 cls_cnt 0 2006.168.07:34:40.63#ibcon#cleared, iclass 26 cls_cnt 0 2006.168.07:34:40.63$vc4f8/vblo=1,632.99 2006.168.07:34:40.63#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.168.07:34:40.63#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.168.07:34:40.63#ibcon#ireg 17 cls_cnt 0 2006.168.07:34:40.63#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:34:40.63#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:34:40.63#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:34:40.63#ibcon#enter wrdev, iclass 28, count 0 2006.168.07:34:40.63#ibcon#first serial, iclass 28, count 0 2006.168.07:34:40.63#ibcon#enter sib2, iclass 28, count 0 2006.168.07:34:40.63#ibcon#flushed, iclass 28, count 0 2006.168.07:34:40.63#ibcon#about to write, iclass 28, count 0 2006.168.07:34:40.63#ibcon#wrote, iclass 28, count 0 2006.168.07:34:40.63#ibcon#about to read 3, iclass 28, count 0 2006.168.07:34:40.65#ibcon#read 3, iclass 28, count 0 2006.168.07:34:40.65#ibcon#about to read 4, iclass 28, count 0 2006.168.07:34:40.65#ibcon#read 4, iclass 28, count 0 2006.168.07:34:40.65#ibcon#about to read 5, iclass 28, count 0 2006.168.07:34:40.65#ibcon#read 5, iclass 28, count 0 2006.168.07:34:40.65#ibcon#about to read 6, iclass 28, count 0 2006.168.07:34:40.65#ibcon#read 6, iclass 28, count 0 2006.168.07:34:40.65#ibcon#end of sib2, iclass 28, count 0 2006.168.07:34:40.65#ibcon#*mode == 0, iclass 28, count 0 2006.168.07:34:40.65#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.168.07:34:40.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.07:34:40.65#ibcon#*before write, iclass 28, count 0 2006.168.07:34:40.65#ibcon#enter sib2, iclass 28, count 0 2006.168.07:34:40.65#ibcon#flushed, iclass 28, count 0 2006.168.07:34:40.65#ibcon#about to write, iclass 28, count 0 2006.168.07:34:40.65#ibcon#wrote, iclass 28, count 0 2006.168.07:34:40.65#ibcon#about to read 3, iclass 28, count 0 2006.168.07:34:40.69#ibcon#read 3, iclass 28, count 0 2006.168.07:34:40.69#ibcon#about to read 4, iclass 28, count 0 2006.168.07:34:40.69#ibcon#read 4, iclass 28, count 0 2006.168.07:34:40.69#ibcon#about to read 5, iclass 28, count 0 2006.168.07:34:40.69#ibcon#read 5, iclass 28, count 0 2006.168.07:34:40.69#ibcon#about to read 6, iclass 28, count 0 2006.168.07:34:40.69#ibcon#read 6, iclass 28, count 0 2006.168.07:34:40.69#ibcon#end of sib2, iclass 28, count 0 2006.168.07:34:40.69#ibcon#*after write, iclass 28, count 0 2006.168.07:34:40.69#ibcon#*before return 0, iclass 28, count 0 2006.168.07:34:40.69#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:34:40.69#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:34:40.69#ibcon#about to clear, iclass 28 cls_cnt 0 2006.168.07:34:40.69#ibcon#cleared, iclass 28 cls_cnt 0 2006.168.07:34:40.69$vc4f8/vb=1,4 2006.168.07:34:40.69#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.168.07:34:40.69#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.168.07:34:40.69#ibcon#ireg 11 cls_cnt 2 2006.168.07:34:40.69#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:34:40.69#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:34:40.69#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:34:40.69#ibcon#enter wrdev, iclass 30, count 2 2006.168.07:34:40.69#ibcon#first serial, iclass 30, count 2 2006.168.07:34:40.69#ibcon#enter sib2, iclass 30, count 2 2006.168.07:34:40.69#ibcon#flushed, iclass 30, count 2 2006.168.07:34:40.69#ibcon#about to write, iclass 30, count 2 2006.168.07:34:40.69#ibcon#wrote, iclass 30, count 2 2006.168.07:34:40.69#ibcon#about to read 3, iclass 30, count 2 2006.168.07:34:40.71#ibcon#read 3, iclass 30, count 2 2006.168.07:34:40.71#ibcon#about to read 4, iclass 30, count 2 2006.168.07:34:40.71#ibcon#read 4, iclass 30, count 2 2006.168.07:34:40.71#ibcon#about to read 5, iclass 30, count 2 2006.168.07:34:40.71#ibcon#read 5, iclass 30, count 2 2006.168.07:34:40.71#ibcon#about to read 6, iclass 30, count 2 2006.168.07:34:40.71#ibcon#read 6, iclass 30, count 2 2006.168.07:34:40.71#ibcon#end of sib2, iclass 30, count 2 2006.168.07:34:40.71#ibcon#*mode == 0, iclass 30, count 2 2006.168.07:34:40.71#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.168.07:34:40.71#ibcon#[27=AT01-04\r\n] 2006.168.07:34:40.71#ibcon#*before write, iclass 30, count 2 2006.168.07:34:40.71#ibcon#enter sib2, iclass 30, count 2 2006.168.07:34:40.71#ibcon#flushed, iclass 30, count 2 2006.168.07:34:40.71#ibcon#about to write, iclass 30, count 2 2006.168.07:34:40.71#ibcon#wrote, iclass 30, count 2 2006.168.07:34:40.71#ibcon#about to read 3, iclass 30, count 2 2006.168.07:34:40.74#ibcon#read 3, iclass 30, count 2 2006.168.07:34:40.74#ibcon#about to read 4, iclass 30, count 2 2006.168.07:34:40.74#ibcon#read 4, iclass 30, count 2 2006.168.07:34:40.74#ibcon#about to read 5, iclass 30, count 2 2006.168.07:34:40.74#ibcon#read 5, iclass 30, count 2 2006.168.07:34:40.74#ibcon#about to read 6, iclass 30, count 2 2006.168.07:34:40.74#ibcon#read 6, iclass 30, count 2 2006.168.07:34:40.74#ibcon#end of sib2, iclass 30, count 2 2006.168.07:34:40.74#ibcon#*after write, iclass 30, count 2 2006.168.07:34:40.74#ibcon#*before return 0, iclass 30, count 2 2006.168.07:34:40.74#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:34:40.74#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:34:40.74#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.168.07:34:40.74#ibcon#ireg 7 cls_cnt 0 2006.168.07:34:40.74#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:34:40.86#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:34:40.86#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:34:40.86#ibcon#enter wrdev, iclass 30, count 0 2006.168.07:34:40.86#ibcon#first serial, iclass 30, count 0 2006.168.07:34:40.86#ibcon#enter sib2, iclass 30, count 0 2006.168.07:34:40.86#ibcon#flushed, iclass 30, count 0 2006.168.07:34:40.86#ibcon#about to write, iclass 30, count 0 2006.168.07:34:40.86#ibcon#wrote, iclass 30, count 0 2006.168.07:34:40.86#ibcon#about to read 3, iclass 30, count 0 2006.168.07:34:40.88#ibcon#read 3, iclass 30, count 0 2006.168.07:34:40.88#ibcon#about to read 4, iclass 30, count 0 2006.168.07:34:40.88#ibcon#read 4, iclass 30, count 0 2006.168.07:34:40.88#ibcon#about to read 5, iclass 30, count 0 2006.168.07:34:40.88#ibcon#read 5, iclass 30, count 0 2006.168.07:34:40.88#ibcon#about to read 6, iclass 30, count 0 2006.168.07:34:40.88#ibcon#read 6, iclass 30, count 0 2006.168.07:34:40.88#ibcon#end of sib2, iclass 30, count 0 2006.168.07:34:40.88#ibcon#*mode == 0, iclass 30, count 0 2006.168.07:34:40.88#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.168.07:34:40.88#ibcon#[27=USB\r\n] 2006.168.07:34:40.88#ibcon#*before write, iclass 30, count 0 2006.168.07:34:40.88#ibcon#enter sib2, iclass 30, count 0 2006.168.07:34:40.88#ibcon#flushed, iclass 30, count 0 2006.168.07:34:40.88#ibcon#about to write, iclass 30, count 0 2006.168.07:34:40.88#ibcon#wrote, iclass 30, count 0 2006.168.07:34:40.88#ibcon#about to read 3, iclass 30, count 0 2006.168.07:34:40.91#ibcon#read 3, iclass 30, count 0 2006.168.07:34:40.91#ibcon#about to read 4, iclass 30, count 0 2006.168.07:34:40.91#ibcon#read 4, iclass 30, count 0 2006.168.07:34:40.91#ibcon#about to read 5, iclass 30, count 0 2006.168.07:34:40.91#ibcon#read 5, iclass 30, count 0 2006.168.07:34:40.91#ibcon#about to read 6, iclass 30, count 0 2006.168.07:34:40.91#ibcon#read 6, iclass 30, count 0 2006.168.07:34:40.91#ibcon#end of sib2, iclass 30, count 0 2006.168.07:34:40.91#ibcon#*after write, iclass 30, count 0 2006.168.07:34:40.91#ibcon#*before return 0, iclass 30, count 0 2006.168.07:34:40.91#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:34:40.91#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:34:40.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.168.07:34:40.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.168.07:34:40.91$vc4f8/vblo=2,640.99 2006.168.07:34:40.91#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.168.07:34:40.91#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.168.07:34:40.91#ibcon#ireg 17 cls_cnt 0 2006.168.07:34:40.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:34:40.91#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:34:40.91#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:34:40.91#ibcon#enter wrdev, iclass 32, count 0 2006.168.07:34:40.91#ibcon#first serial, iclass 32, count 0 2006.168.07:34:40.91#ibcon#enter sib2, iclass 32, count 0 2006.168.07:34:40.91#ibcon#flushed, iclass 32, count 0 2006.168.07:34:40.91#ibcon#about to write, iclass 32, count 0 2006.168.07:34:40.91#ibcon#wrote, iclass 32, count 0 2006.168.07:34:40.91#ibcon#about to read 3, iclass 32, count 0 2006.168.07:34:40.93#ibcon#read 3, iclass 32, count 0 2006.168.07:34:40.93#ibcon#about to read 4, iclass 32, count 0 2006.168.07:34:40.93#ibcon#read 4, iclass 32, count 0 2006.168.07:34:40.93#ibcon#about to read 5, iclass 32, count 0 2006.168.07:34:40.93#ibcon#read 5, iclass 32, count 0 2006.168.07:34:40.93#ibcon#about to read 6, iclass 32, count 0 2006.168.07:34:40.93#ibcon#read 6, iclass 32, count 0 2006.168.07:34:40.93#ibcon#end of sib2, iclass 32, count 0 2006.168.07:34:40.93#ibcon#*mode == 0, iclass 32, count 0 2006.168.07:34:40.93#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.168.07:34:40.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.07:34:40.93#ibcon#*before write, iclass 32, count 0 2006.168.07:34:40.93#ibcon#enter sib2, iclass 32, count 0 2006.168.07:34:40.93#ibcon#flushed, iclass 32, count 0 2006.168.07:34:40.93#ibcon#about to write, iclass 32, count 0 2006.168.07:34:40.93#ibcon#wrote, iclass 32, count 0 2006.168.07:34:40.93#ibcon#about to read 3, iclass 32, count 0 2006.168.07:34:40.97#ibcon#read 3, iclass 32, count 0 2006.168.07:34:40.97#ibcon#about to read 4, iclass 32, count 0 2006.168.07:34:40.97#ibcon#read 4, iclass 32, count 0 2006.168.07:34:40.97#ibcon#about to read 5, iclass 32, count 0 2006.168.07:34:40.97#ibcon#read 5, iclass 32, count 0 2006.168.07:34:40.97#ibcon#about to read 6, iclass 32, count 0 2006.168.07:34:40.97#ibcon#read 6, iclass 32, count 0 2006.168.07:34:40.97#ibcon#end of sib2, iclass 32, count 0 2006.168.07:34:40.97#ibcon#*after write, iclass 32, count 0 2006.168.07:34:40.97#ibcon#*before return 0, iclass 32, count 0 2006.168.07:34:40.97#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:34:40.97#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:34:40.97#ibcon#about to clear, iclass 32 cls_cnt 0 2006.168.07:34:40.97#ibcon#cleared, iclass 32 cls_cnt 0 2006.168.07:34:40.97$vc4f8/vb=2,4 2006.168.07:34:40.97#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.168.07:34:40.97#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.168.07:34:40.97#ibcon#ireg 11 cls_cnt 2 2006.168.07:34:40.97#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:34:41.03#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:34:41.03#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:34:41.03#ibcon#enter wrdev, iclass 34, count 2 2006.168.07:34:41.03#ibcon#first serial, iclass 34, count 2 2006.168.07:34:41.03#ibcon#enter sib2, iclass 34, count 2 2006.168.07:34:41.03#ibcon#flushed, iclass 34, count 2 2006.168.07:34:41.03#ibcon#about to write, iclass 34, count 2 2006.168.07:34:41.03#ibcon#wrote, iclass 34, count 2 2006.168.07:34:41.03#ibcon#about to read 3, iclass 34, count 2 2006.168.07:34:41.05#ibcon#read 3, iclass 34, count 2 2006.168.07:34:41.05#ibcon#about to read 4, iclass 34, count 2 2006.168.07:34:41.05#ibcon#read 4, iclass 34, count 2 2006.168.07:34:41.05#ibcon#about to read 5, iclass 34, count 2 2006.168.07:34:41.05#ibcon#read 5, iclass 34, count 2 2006.168.07:34:41.05#ibcon#about to read 6, iclass 34, count 2 2006.168.07:34:41.05#ibcon#read 6, iclass 34, count 2 2006.168.07:34:41.05#ibcon#end of sib2, iclass 34, count 2 2006.168.07:34:41.05#ibcon#*mode == 0, iclass 34, count 2 2006.168.07:34:41.05#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.168.07:34:41.05#ibcon#[27=AT02-04\r\n] 2006.168.07:34:41.05#ibcon#*before write, iclass 34, count 2 2006.168.07:34:41.05#ibcon#enter sib2, iclass 34, count 2 2006.168.07:34:41.05#ibcon#flushed, iclass 34, count 2 2006.168.07:34:41.05#ibcon#about to write, iclass 34, count 2 2006.168.07:34:41.05#ibcon#wrote, iclass 34, count 2 2006.168.07:34:41.05#ibcon#about to read 3, iclass 34, count 2 2006.168.07:34:41.08#ibcon#read 3, iclass 34, count 2 2006.168.07:34:41.08#ibcon#about to read 4, iclass 34, count 2 2006.168.07:34:41.08#ibcon#read 4, iclass 34, count 2 2006.168.07:34:41.08#ibcon#about to read 5, iclass 34, count 2 2006.168.07:34:41.08#ibcon#read 5, iclass 34, count 2 2006.168.07:34:41.08#ibcon#about to read 6, iclass 34, count 2 2006.168.07:34:41.08#ibcon#read 6, iclass 34, count 2 2006.168.07:34:41.08#ibcon#end of sib2, iclass 34, count 2 2006.168.07:34:41.08#ibcon#*after write, iclass 34, count 2 2006.168.07:34:41.08#ibcon#*before return 0, iclass 34, count 2 2006.168.07:34:41.08#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:34:41.08#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:34:41.08#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.168.07:34:41.08#ibcon#ireg 7 cls_cnt 0 2006.168.07:34:41.08#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:34:41.20#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:34:41.20#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:34:41.20#ibcon#enter wrdev, iclass 34, count 0 2006.168.07:34:41.20#ibcon#first serial, iclass 34, count 0 2006.168.07:34:41.20#ibcon#enter sib2, iclass 34, count 0 2006.168.07:34:41.20#ibcon#flushed, iclass 34, count 0 2006.168.07:34:41.20#ibcon#about to write, iclass 34, count 0 2006.168.07:34:41.20#ibcon#wrote, iclass 34, count 0 2006.168.07:34:41.20#ibcon#about to read 3, iclass 34, count 0 2006.168.07:34:41.22#ibcon#read 3, iclass 34, count 0 2006.168.07:34:41.22#ibcon#about to read 4, iclass 34, count 0 2006.168.07:34:41.22#ibcon#read 4, iclass 34, count 0 2006.168.07:34:41.22#ibcon#about to read 5, iclass 34, count 0 2006.168.07:34:41.22#ibcon#read 5, iclass 34, count 0 2006.168.07:34:41.22#ibcon#about to read 6, iclass 34, count 0 2006.168.07:34:41.22#ibcon#read 6, iclass 34, count 0 2006.168.07:34:41.22#ibcon#end of sib2, iclass 34, count 0 2006.168.07:34:41.22#ibcon#*mode == 0, iclass 34, count 0 2006.168.07:34:41.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.168.07:34:41.22#ibcon#[27=USB\r\n] 2006.168.07:34:41.22#ibcon#*before write, iclass 34, count 0 2006.168.07:34:41.22#ibcon#enter sib2, iclass 34, count 0 2006.168.07:34:41.22#ibcon#flushed, iclass 34, count 0 2006.168.07:34:41.22#ibcon#about to write, iclass 34, count 0 2006.168.07:34:41.22#ibcon#wrote, iclass 34, count 0 2006.168.07:34:41.22#ibcon#about to read 3, iclass 34, count 0 2006.168.07:34:41.25#ibcon#read 3, iclass 34, count 0 2006.168.07:34:41.25#ibcon#about to read 4, iclass 34, count 0 2006.168.07:34:41.25#ibcon#read 4, iclass 34, count 0 2006.168.07:34:41.25#ibcon#about to read 5, iclass 34, count 0 2006.168.07:34:41.25#ibcon#read 5, iclass 34, count 0 2006.168.07:34:41.25#ibcon#about to read 6, iclass 34, count 0 2006.168.07:34:41.25#ibcon#read 6, iclass 34, count 0 2006.168.07:34:41.25#ibcon#end of sib2, iclass 34, count 0 2006.168.07:34:41.25#ibcon#*after write, iclass 34, count 0 2006.168.07:34:41.25#ibcon#*before return 0, iclass 34, count 0 2006.168.07:34:41.25#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:34:41.25#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:34:41.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.168.07:34:41.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.168.07:34:41.25$vc4f8/vblo=3,656.99 2006.168.07:34:41.25#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.168.07:34:41.25#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.168.07:34:41.25#ibcon#ireg 17 cls_cnt 0 2006.168.07:34:41.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:34:41.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:34:41.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:34:41.25#ibcon#enter wrdev, iclass 36, count 0 2006.168.07:34:41.25#ibcon#first serial, iclass 36, count 0 2006.168.07:34:41.25#ibcon#enter sib2, iclass 36, count 0 2006.168.07:34:41.25#ibcon#flushed, iclass 36, count 0 2006.168.07:34:41.25#ibcon#about to write, iclass 36, count 0 2006.168.07:34:41.25#ibcon#wrote, iclass 36, count 0 2006.168.07:34:41.25#ibcon#about to read 3, iclass 36, count 0 2006.168.07:34:41.27#ibcon#read 3, iclass 36, count 0 2006.168.07:34:41.27#ibcon#about to read 4, iclass 36, count 0 2006.168.07:34:41.27#ibcon#read 4, iclass 36, count 0 2006.168.07:34:41.27#ibcon#about to read 5, iclass 36, count 0 2006.168.07:34:41.27#ibcon#read 5, iclass 36, count 0 2006.168.07:34:41.27#ibcon#about to read 6, iclass 36, count 0 2006.168.07:34:41.27#ibcon#read 6, iclass 36, count 0 2006.168.07:34:41.27#ibcon#end of sib2, iclass 36, count 0 2006.168.07:34:41.27#ibcon#*mode == 0, iclass 36, count 0 2006.168.07:34:41.27#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.168.07:34:41.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.07:34:41.27#ibcon#*before write, iclass 36, count 0 2006.168.07:34:41.27#ibcon#enter sib2, iclass 36, count 0 2006.168.07:34:41.27#ibcon#flushed, iclass 36, count 0 2006.168.07:34:41.27#ibcon#about to write, iclass 36, count 0 2006.168.07:34:41.27#ibcon#wrote, iclass 36, count 0 2006.168.07:34:41.27#ibcon#about to read 3, iclass 36, count 0 2006.168.07:34:41.31#ibcon#read 3, iclass 36, count 0 2006.168.07:34:41.31#ibcon#about to read 4, iclass 36, count 0 2006.168.07:34:41.31#ibcon#read 4, iclass 36, count 0 2006.168.07:34:41.31#ibcon#about to read 5, iclass 36, count 0 2006.168.07:34:41.31#ibcon#read 5, iclass 36, count 0 2006.168.07:34:41.31#ibcon#about to read 6, iclass 36, count 0 2006.168.07:34:41.31#ibcon#read 6, iclass 36, count 0 2006.168.07:34:41.31#ibcon#end of sib2, iclass 36, count 0 2006.168.07:34:41.31#ibcon#*after write, iclass 36, count 0 2006.168.07:34:41.31#ibcon#*before return 0, iclass 36, count 0 2006.168.07:34:41.31#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:34:41.31#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:34:41.31#ibcon#about to clear, iclass 36 cls_cnt 0 2006.168.07:34:41.31#ibcon#cleared, iclass 36 cls_cnt 0 2006.168.07:34:41.31$vc4f8/vb=3,4 2006.168.07:34:41.31#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.168.07:34:41.31#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.168.07:34:41.31#ibcon#ireg 11 cls_cnt 2 2006.168.07:34:41.31#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.168.07:34:41.37#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.168.07:34:41.37#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.168.07:34:41.37#ibcon#enter wrdev, iclass 38, count 2 2006.168.07:34:41.37#ibcon#first serial, iclass 38, count 2 2006.168.07:34:41.37#ibcon#enter sib2, iclass 38, count 2 2006.168.07:34:41.37#ibcon#flushed, iclass 38, count 2 2006.168.07:34:41.37#ibcon#about to write, iclass 38, count 2 2006.168.07:34:41.37#ibcon#wrote, iclass 38, count 2 2006.168.07:34:41.37#ibcon#about to read 3, iclass 38, count 2 2006.168.07:34:41.39#ibcon#read 3, iclass 38, count 2 2006.168.07:34:41.39#ibcon#about to read 4, iclass 38, count 2 2006.168.07:34:41.39#ibcon#read 4, iclass 38, count 2 2006.168.07:34:41.39#ibcon#about to read 5, iclass 38, count 2 2006.168.07:34:41.39#ibcon#read 5, iclass 38, count 2 2006.168.07:34:41.39#ibcon#about to read 6, iclass 38, count 2 2006.168.07:34:41.39#ibcon#read 6, iclass 38, count 2 2006.168.07:34:41.39#ibcon#end of sib2, iclass 38, count 2 2006.168.07:34:41.39#ibcon#*mode == 0, iclass 38, count 2 2006.168.07:34:41.39#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.168.07:34:41.39#ibcon#[27=AT03-04\r\n] 2006.168.07:34:41.39#ibcon#*before write, iclass 38, count 2 2006.168.07:34:41.39#ibcon#enter sib2, iclass 38, count 2 2006.168.07:34:41.39#ibcon#flushed, iclass 38, count 2 2006.168.07:34:41.39#ibcon#about to write, iclass 38, count 2 2006.168.07:34:41.39#ibcon#wrote, iclass 38, count 2 2006.168.07:34:41.39#ibcon#about to read 3, iclass 38, count 2 2006.168.07:34:41.42#ibcon#read 3, iclass 38, count 2 2006.168.07:34:41.42#ibcon#about to read 4, iclass 38, count 2 2006.168.07:34:41.42#ibcon#read 4, iclass 38, count 2 2006.168.07:34:41.42#ibcon#about to read 5, iclass 38, count 2 2006.168.07:34:41.42#ibcon#read 5, iclass 38, count 2 2006.168.07:34:41.42#ibcon#about to read 6, iclass 38, count 2 2006.168.07:34:41.42#ibcon#read 6, iclass 38, count 2 2006.168.07:34:41.42#ibcon#end of sib2, iclass 38, count 2 2006.168.07:34:41.42#ibcon#*after write, iclass 38, count 2 2006.168.07:34:41.42#ibcon#*before return 0, iclass 38, count 2 2006.168.07:34:41.42#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.168.07:34:41.42#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.168.07:34:41.42#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.168.07:34:41.42#ibcon#ireg 7 cls_cnt 0 2006.168.07:34:41.42#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.168.07:34:41.54#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.168.07:34:41.54#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.168.07:34:41.54#ibcon#enter wrdev, iclass 38, count 0 2006.168.07:34:41.54#ibcon#first serial, iclass 38, count 0 2006.168.07:34:41.54#ibcon#enter sib2, iclass 38, count 0 2006.168.07:34:41.54#ibcon#flushed, iclass 38, count 0 2006.168.07:34:41.54#ibcon#about to write, iclass 38, count 0 2006.168.07:34:41.54#ibcon#wrote, iclass 38, count 0 2006.168.07:34:41.54#ibcon#about to read 3, iclass 38, count 0 2006.168.07:34:41.56#ibcon#read 3, iclass 38, count 0 2006.168.07:34:41.56#ibcon#about to read 4, iclass 38, count 0 2006.168.07:34:41.56#ibcon#read 4, iclass 38, count 0 2006.168.07:34:41.56#ibcon#about to read 5, iclass 38, count 0 2006.168.07:34:41.56#ibcon#read 5, iclass 38, count 0 2006.168.07:34:41.56#ibcon#about to read 6, iclass 38, count 0 2006.168.07:34:41.56#ibcon#read 6, iclass 38, count 0 2006.168.07:34:41.56#ibcon#end of sib2, iclass 38, count 0 2006.168.07:34:41.56#ibcon#*mode == 0, iclass 38, count 0 2006.168.07:34:41.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.168.07:34:41.56#ibcon#[27=USB\r\n] 2006.168.07:34:41.56#ibcon#*before write, iclass 38, count 0 2006.168.07:34:41.56#ibcon#enter sib2, iclass 38, count 0 2006.168.07:34:41.56#ibcon#flushed, iclass 38, count 0 2006.168.07:34:41.56#ibcon#about to write, iclass 38, count 0 2006.168.07:34:41.56#ibcon#wrote, iclass 38, count 0 2006.168.07:34:41.56#ibcon#about to read 3, iclass 38, count 0 2006.168.07:34:41.59#ibcon#read 3, iclass 38, count 0 2006.168.07:34:41.59#ibcon#about to read 4, iclass 38, count 0 2006.168.07:34:41.59#ibcon#read 4, iclass 38, count 0 2006.168.07:34:41.59#ibcon#about to read 5, iclass 38, count 0 2006.168.07:34:41.59#ibcon#read 5, iclass 38, count 0 2006.168.07:34:41.59#ibcon#about to read 6, iclass 38, count 0 2006.168.07:34:41.59#ibcon#read 6, iclass 38, count 0 2006.168.07:34:41.59#ibcon#end of sib2, iclass 38, count 0 2006.168.07:34:41.59#ibcon#*after write, iclass 38, count 0 2006.168.07:34:41.59#ibcon#*before return 0, iclass 38, count 0 2006.168.07:34:41.59#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.168.07:34:41.59#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.168.07:34:41.59#ibcon#about to clear, iclass 38 cls_cnt 0 2006.168.07:34:41.59#ibcon#cleared, iclass 38 cls_cnt 0 2006.168.07:34:41.59$vc4f8/vblo=4,712.99 2006.168.07:34:41.59#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.168.07:34:41.59#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.168.07:34:41.59#ibcon#ireg 17 cls_cnt 0 2006.168.07:34:41.59#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.168.07:34:41.59#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.168.07:34:41.59#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.168.07:34:41.59#ibcon#enter wrdev, iclass 40, count 0 2006.168.07:34:41.59#ibcon#first serial, iclass 40, count 0 2006.168.07:34:41.59#ibcon#enter sib2, iclass 40, count 0 2006.168.07:34:41.59#ibcon#flushed, iclass 40, count 0 2006.168.07:34:41.59#ibcon#about to write, iclass 40, count 0 2006.168.07:34:41.59#ibcon#wrote, iclass 40, count 0 2006.168.07:34:41.59#ibcon#about to read 3, iclass 40, count 0 2006.168.07:34:41.61#ibcon#read 3, iclass 40, count 0 2006.168.07:34:41.61#ibcon#about to read 4, iclass 40, count 0 2006.168.07:34:41.61#ibcon#read 4, iclass 40, count 0 2006.168.07:34:41.61#ibcon#about to read 5, iclass 40, count 0 2006.168.07:34:41.61#ibcon#read 5, iclass 40, count 0 2006.168.07:34:41.61#ibcon#about to read 6, iclass 40, count 0 2006.168.07:34:41.61#ibcon#read 6, iclass 40, count 0 2006.168.07:34:41.61#ibcon#end of sib2, iclass 40, count 0 2006.168.07:34:41.61#ibcon#*mode == 0, iclass 40, count 0 2006.168.07:34:41.61#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.168.07:34:41.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.07:34:41.61#ibcon#*before write, iclass 40, count 0 2006.168.07:34:41.61#ibcon#enter sib2, iclass 40, count 0 2006.168.07:34:41.61#ibcon#flushed, iclass 40, count 0 2006.168.07:34:41.61#ibcon#about to write, iclass 40, count 0 2006.168.07:34:41.61#ibcon#wrote, iclass 40, count 0 2006.168.07:34:41.61#ibcon#about to read 3, iclass 40, count 0 2006.168.07:34:41.65#ibcon#read 3, iclass 40, count 0 2006.168.07:34:41.65#ibcon#about to read 4, iclass 40, count 0 2006.168.07:34:41.65#ibcon#read 4, iclass 40, count 0 2006.168.07:34:41.65#ibcon#about to read 5, iclass 40, count 0 2006.168.07:34:41.65#ibcon#read 5, iclass 40, count 0 2006.168.07:34:41.65#ibcon#about to read 6, iclass 40, count 0 2006.168.07:34:41.65#ibcon#read 6, iclass 40, count 0 2006.168.07:34:41.65#ibcon#end of sib2, iclass 40, count 0 2006.168.07:34:41.65#ibcon#*after write, iclass 40, count 0 2006.168.07:34:41.65#ibcon#*before return 0, iclass 40, count 0 2006.168.07:34:41.65#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.168.07:34:41.65#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.168.07:34:41.65#ibcon#about to clear, iclass 40 cls_cnt 0 2006.168.07:34:41.65#ibcon#cleared, iclass 40 cls_cnt 0 2006.168.07:34:41.65$vc4f8/vb=4,4 2006.168.07:34:41.65#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.168.07:34:41.65#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.168.07:34:41.65#ibcon#ireg 11 cls_cnt 2 2006.168.07:34:41.65#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.168.07:34:41.71#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.168.07:34:41.71#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.168.07:34:41.71#ibcon#enter wrdev, iclass 4, count 2 2006.168.07:34:41.71#ibcon#first serial, iclass 4, count 2 2006.168.07:34:41.71#ibcon#enter sib2, iclass 4, count 2 2006.168.07:34:41.71#ibcon#flushed, iclass 4, count 2 2006.168.07:34:41.71#ibcon#about to write, iclass 4, count 2 2006.168.07:34:41.71#ibcon#wrote, iclass 4, count 2 2006.168.07:34:41.71#ibcon#about to read 3, iclass 4, count 2 2006.168.07:34:41.73#ibcon#read 3, iclass 4, count 2 2006.168.07:34:41.73#ibcon#about to read 4, iclass 4, count 2 2006.168.07:34:41.73#ibcon#read 4, iclass 4, count 2 2006.168.07:34:41.73#ibcon#about to read 5, iclass 4, count 2 2006.168.07:34:41.73#ibcon#read 5, iclass 4, count 2 2006.168.07:34:41.73#ibcon#about to read 6, iclass 4, count 2 2006.168.07:34:41.73#ibcon#read 6, iclass 4, count 2 2006.168.07:34:41.73#ibcon#end of sib2, iclass 4, count 2 2006.168.07:34:41.73#ibcon#*mode == 0, iclass 4, count 2 2006.168.07:34:41.73#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.168.07:34:41.73#ibcon#[27=AT04-04\r\n] 2006.168.07:34:41.73#ibcon#*before write, iclass 4, count 2 2006.168.07:34:41.73#ibcon#enter sib2, iclass 4, count 2 2006.168.07:34:41.73#ibcon#flushed, iclass 4, count 2 2006.168.07:34:41.73#ibcon#about to write, iclass 4, count 2 2006.168.07:34:41.73#ibcon#wrote, iclass 4, count 2 2006.168.07:34:41.73#ibcon#about to read 3, iclass 4, count 2 2006.168.07:34:41.76#ibcon#read 3, iclass 4, count 2 2006.168.07:34:41.76#ibcon#about to read 4, iclass 4, count 2 2006.168.07:34:41.76#ibcon#read 4, iclass 4, count 2 2006.168.07:34:41.76#ibcon#about to read 5, iclass 4, count 2 2006.168.07:34:41.76#ibcon#read 5, iclass 4, count 2 2006.168.07:34:41.76#ibcon#about to read 6, iclass 4, count 2 2006.168.07:34:41.76#ibcon#read 6, iclass 4, count 2 2006.168.07:34:41.76#ibcon#end of sib2, iclass 4, count 2 2006.168.07:34:41.76#ibcon#*after write, iclass 4, count 2 2006.168.07:34:41.76#ibcon#*before return 0, iclass 4, count 2 2006.168.07:34:41.76#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.168.07:34:41.76#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.168.07:34:41.76#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.168.07:34:41.76#ibcon#ireg 7 cls_cnt 0 2006.168.07:34:41.76#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.168.07:34:41.88#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.168.07:34:41.88#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.168.07:34:41.88#ibcon#enter wrdev, iclass 4, count 0 2006.168.07:34:41.88#ibcon#first serial, iclass 4, count 0 2006.168.07:34:41.88#ibcon#enter sib2, iclass 4, count 0 2006.168.07:34:41.88#ibcon#flushed, iclass 4, count 0 2006.168.07:34:41.88#ibcon#about to write, iclass 4, count 0 2006.168.07:34:41.88#ibcon#wrote, iclass 4, count 0 2006.168.07:34:41.88#ibcon#about to read 3, iclass 4, count 0 2006.168.07:34:41.90#ibcon#read 3, iclass 4, count 0 2006.168.07:34:41.90#ibcon#about to read 4, iclass 4, count 0 2006.168.07:34:41.90#ibcon#read 4, iclass 4, count 0 2006.168.07:34:41.90#ibcon#about to read 5, iclass 4, count 0 2006.168.07:34:41.90#ibcon#read 5, iclass 4, count 0 2006.168.07:34:41.90#ibcon#about to read 6, iclass 4, count 0 2006.168.07:34:41.90#ibcon#read 6, iclass 4, count 0 2006.168.07:34:41.90#ibcon#end of sib2, iclass 4, count 0 2006.168.07:34:41.90#ibcon#*mode == 0, iclass 4, count 0 2006.168.07:34:41.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.168.07:34:41.90#ibcon#[27=USB\r\n] 2006.168.07:34:41.90#ibcon#*before write, iclass 4, count 0 2006.168.07:34:41.90#ibcon#enter sib2, iclass 4, count 0 2006.168.07:34:41.90#ibcon#flushed, iclass 4, count 0 2006.168.07:34:41.90#ibcon#about to write, iclass 4, count 0 2006.168.07:34:41.90#ibcon#wrote, iclass 4, count 0 2006.168.07:34:41.90#ibcon#about to read 3, iclass 4, count 0 2006.168.07:34:41.93#ibcon#read 3, iclass 4, count 0 2006.168.07:34:41.93#ibcon#about to read 4, iclass 4, count 0 2006.168.07:34:41.93#ibcon#read 4, iclass 4, count 0 2006.168.07:34:41.93#ibcon#about to read 5, iclass 4, count 0 2006.168.07:34:41.93#ibcon#read 5, iclass 4, count 0 2006.168.07:34:41.93#ibcon#about to read 6, iclass 4, count 0 2006.168.07:34:41.93#ibcon#read 6, iclass 4, count 0 2006.168.07:34:41.93#ibcon#end of sib2, iclass 4, count 0 2006.168.07:34:41.93#ibcon#*after write, iclass 4, count 0 2006.168.07:34:41.93#ibcon#*before return 0, iclass 4, count 0 2006.168.07:34:41.93#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.168.07:34:41.93#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.168.07:34:41.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.168.07:34:41.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.168.07:34:41.93$vc4f8/vblo=5,744.99 2006.168.07:34:41.93#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.168.07:34:41.93#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.168.07:34:41.93#ibcon#ireg 17 cls_cnt 0 2006.168.07:34:41.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.168.07:34:41.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.168.07:34:41.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.168.07:34:41.93#ibcon#enter wrdev, iclass 6, count 0 2006.168.07:34:41.93#ibcon#first serial, iclass 6, count 0 2006.168.07:34:41.93#ibcon#enter sib2, iclass 6, count 0 2006.168.07:34:41.93#ibcon#flushed, iclass 6, count 0 2006.168.07:34:41.93#ibcon#about to write, iclass 6, count 0 2006.168.07:34:41.93#ibcon#wrote, iclass 6, count 0 2006.168.07:34:41.93#ibcon#about to read 3, iclass 6, count 0 2006.168.07:34:41.95#ibcon#read 3, iclass 6, count 0 2006.168.07:34:41.95#ibcon#about to read 4, iclass 6, count 0 2006.168.07:34:41.95#ibcon#read 4, iclass 6, count 0 2006.168.07:34:41.95#ibcon#about to read 5, iclass 6, count 0 2006.168.07:34:41.95#ibcon#read 5, iclass 6, count 0 2006.168.07:34:41.95#ibcon#about to read 6, iclass 6, count 0 2006.168.07:34:41.95#ibcon#read 6, iclass 6, count 0 2006.168.07:34:41.95#ibcon#end of sib2, iclass 6, count 0 2006.168.07:34:41.95#ibcon#*mode == 0, iclass 6, count 0 2006.168.07:34:41.95#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.168.07:34:41.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.07:34:41.95#ibcon#*before write, iclass 6, count 0 2006.168.07:34:41.95#ibcon#enter sib2, iclass 6, count 0 2006.168.07:34:41.95#ibcon#flushed, iclass 6, count 0 2006.168.07:34:41.95#ibcon#about to write, iclass 6, count 0 2006.168.07:34:41.95#ibcon#wrote, iclass 6, count 0 2006.168.07:34:41.95#ibcon#about to read 3, iclass 6, count 0 2006.168.07:34:41.99#ibcon#read 3, iclass 6, count 0 2006.168.07:34:41.99#ibcon#about to read 4, iclass 6, count 0 2006.168.07:34:41.99#ibcon#read 4, iclass 6, count 0 2006.168.07:34:41.99#ibcon#about to read 5, iclass 6, count 0 2006.168.07:34:41.99#ibcon#read 5, iclass 6, count 0 2006.168.07:34:41.99#ibcon#about to read 6, iclass 6, count 0 2006.168.07:34:41.99#ibcon#read 6, iclass 6, count 0 2006.168.07:34:41.99#ibcon#end of sib2, iclass 6, count 0 2006.168.07:34:41.99#ibcon#*after write, iclass 6, count 0 2006.168.07:34:41.99#ibcon#*before return 0, iclass 6, count 0 2006.168.07:34:41.99#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.168.07:34:41.99#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.168.07:34:41.99#ibcon#about to clear, iclass 6 cls_cnt 0 2006.168.07:34:41.99#ibcon#cleared, iclass 6 cls_cnt 0 2006.168.07:34:41.99$vc4f8/vb=5,4 2006.168.07:34:41.99#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.168.07:34:41.99#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.168.07:34:41.99#ibcon#ireg 11 cls_cnt 2 2006.168.07:34:41.99#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.168.07:34:42.05#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.168.07:34:42.05#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.168.07:34:42.05#ibcon#enter wrdev, iclass 10, count 2 2006.168.07:34:42.05#ibcon#first serial, iclass 10, count 2 2006.168.07:34:42.05#ibcon#enter sib2, iclass 10, count 2 2006.168.07:34:42.05#ibcon#flushed, iclass 10, count 2 2006.168.07:34:42.05#ibcon#about to write, iclass 10, count 2 2006.168.07:34:42.05#ibcon#wrote, iclass 10, count 2 2006.168.07:34:42.05#ibcon#about to read 3, iclass 10, count 2 2006.168.07:34:42.07#ibcon#read 3, iclass 10, count 2 2006.168.07:34:42.07#ibcon#about to read 4, iclass 10, count 2 2006.168.07:34:42.07#ibcon#read 4, iclass 10, count 2 2006.168.07:34:42.07#ibcon#about to read 5, iclass 10, count 2 2006.168.07:34:42.07#ibcon#read 5, iclass 10, count 2 2006.168.07:34:42.07#ibcon#about to read 6, iclass 10, count 2 2006.168.07:34:42.07#ibcon#read 6, iclass 10, count 2 2006.168.07:34:42.07#ibcon#end of sib2, iclass 10, count 2 2006.168.07:34:42.07#ibcon#*mode == 0, iclass 10, count 2 2006.168.07:34:42.07#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.168.07:34:42.07#ibcon#[27=AT05-04\r\n] 2006.168.07:34:42.07#ibcon#*before write, iclass 10, count 2 2006.168.07:34:42.07#ibcon#enter sib2, iclass 10, count 2 2006.168.07:34:42.07#ibcon#flushed, iclass 10, count 2 2006.168.07:34:42.07#ibcon#about to write, iclass 10, count 2 2006.168.07:34:42.07#ibcon#wrote, iclass 10, count 2 2006.168.07:34:42.07#ibcon#about to read 3, iclass 10, count 2 2006.168.07:34:42.10#ibcon#read 3, iclass 10, count 2 2006.168.07:34:42.10#ibcon#about to read 4, iclass 10, count 2 2006.168.07:34:42.10#ibcon#read 4, iclass 10, count 2 2006.168.07:34:42.10#ibcon#about to read 5, iclass 10, count 2 2006.168.07:34:42.10#ibcon#read 5, iclass 10, count 2 2006.168.07:34:42.10#ibcon#about to read 6, iclass 10, count 2 2006.168.07:34:42.10#ibcon#read 6, iclass 10, count 2 2006.168.07:34:42.10#ibcon#end of sib2, iclass 10, count 2 2006.168.07:34:42.10#ibcon#*after write, iclass 10, count 2 2006.168.07:34:42.10#ibcon#*before return 0, iclass 10, count 2 2006.168.07:34:42.10#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.168.07:34:42.10#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.168.07:34:42.10#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.168.07:34:42.10#ibcon#ireg 7 cls_cnt 0 2006.168.07:34:42.10#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.168.07:34:42.22#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.168.07:34:42.22#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.168.07:34:42.22#ibcon#enter wrdev, iclass 10, count 0 2006.168.07:34:42.22#ibcon#first serial, iclass 10, count 0 2006.168.07:34:42.22#ibcon#enter sib2, iclass 10, count 0 2006.168.07:34:42.22#ibcon#flushed, iclass 10, count 0 2006.168.07:34:42.22#ibcon#about to write, iclass 10, count 0 2006.168.07:34:42.22#ibcon#wrote, iclass 10, count 0 2006.168.07:34:42.22#ibcon#about to read 3, iclass 10, count 0 2006.168.07:34:42.24#ibcon#read 3, iclass 10, count 0 2006.168.07:34:42.24#ibcon#about to read 4, iclass 10, count 0 2006.168.07:34:42.24#ibcon#read 4, iclass 10, count 0 2006.168.07:34:42.24#ibcon#about to read 5, iclass 10, count 0 2006.168.07:34:42.24#ibcon#read 5, iclass 10, count 0 2006.168.07:34:42.24#ibcon#about to read 6, iclass 10, count 0 2006.168.07:34:42.24#ibcon#read 6, iclass 10, count 0 2006.168.07:34:42.24#ibcon#end of sib2, iclass 10, count 0 2006.168.07:34:42.24#ibcon#*mode == 0, iclass 10, count 0 2006.168.07:34:42.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.168.07:34:42.24#ibcon#[27=USB\r\n] 2006.168.07:34:42.24#ibcon#*before write, iclass 10, count 0 2006.168.07:34:42.24#ibcon#enter sib2, iclass 10, count 0 2006.168.07:34:42.24#ibcon#flushed, iclass 10, count 0 2006.168.07:34:42.24#ibcon#about to write, iclass 10, count 0 2006.168.07:34:42.24#ibcon#wrote, iclass 10, count 0 2006.168.07:34:42.24#ibcon#about to read 3, iclass 10, count 0 2006.168.07:34:42.27#ibcon#read 3, iclass 10, count 0 2006.168.07:34:42.27#ibcon#about to read 4, iclass 10, count 0 2006.168.07:34:42.27#ibcon#read 4, iclass 10, count 0 2006.168.07:34:42.27#ibcon#about to read 5, iclass 10, count 0 2006.168.07:34:42.27#ibcon#read 5, iclass 10, count 0 2006.168.07:34:42.27#ibcon#about to read 6, iclass 10, count 0 2006.168.07:34:42.27#ibcon#read 6, iclass 10, count 0 2006.168.07:34:42.27#ibcon#end of sib2, iclass 10, count 0 2006.168.07:34:42.27#ibcon#*after write, iclass 10, count 0 2006.168.07:34:42.27#ibcon#*before return 0, iclass 10, count 0 2006.168.07:34:42.27#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.168.07:34:42.27#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.168.07:34:42.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.168.07:34:42.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.168.07:34:42.27$vc4f8/vblo=6,752.99 2006.168.07:34:42.27#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.168.07:34:42.27#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.168.07:34:42.27#ibcon#ireg 17 cls_cnt 0 2006.168.07:34:42.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.168.07:34:42.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.168.07:34:42.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.168.07:34:42.27#ibcon#enter wrdev, iclass 12, count 0 2006.168.07:34:42.27#ibcon#first serial, iclass 12, count 0 2006.168.07:34:42.27#ibcon#enter sib2, iclass 12, count 0 2006.168.07:34:42.27#ibcon#flushed, iclass 12, count 0 2006.168.07:34:42.27#ibcon#about to write, iclass 12, count 0 2006.168.07:34:42.27#ibcon#wrote, iclass 12, count 0 2006.168.07:34:42.27#ibcon#about to read 3, iclass 12, count 0 2006.168.07:34:42.29#ibcon#read 3, iclass 12, count 0 2006.168.07:34:42.29#ibcon#about to read 4, iclass 12, count 0 2006.168.07:34:42.29#ibcon#read 4, iclass 12, count 0 2006.168.07:34:42.29#ibcon#about to read 5, iclass 12, count 0 2006.168.07:34:42.29#ibcon#read 5, iclass 12, count 0 2006.168.07:34:42.29#ibcon#about to read 6, iclass 12, count 0 2006.168.07:34:42.29#ibcon#read 6, iclass 12, count 0 2006.168.07:34:42.29#ibcon#end of sib2, iclass 12, count 0 2006.168.07:34:42.29#ibcon#*mode == 0, iclass 12, count 0 2006.168.07:34:42.29#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.168.07:34:42.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.07:34:42.29#ibcon#*before write, iclass 12, count 0 2006.168.07:34:42.29#ibcon#enter sib2, iclass 12, count 0 2006.168.07:34:42.29#ibcon#flushed, iclass 12, count 0 2006.168.07:34:42.29#ibcon#about to write, iclass 12, count 0 2006.168.07:34:42.29#ibcon#wrote, iclass 12, count 0 2006.168.07:34:42.29#ibcon#about to read 3, iclass 12, count 0 2006.168.07:34:42.33#ibcon#read 3, iclass 12, count 0 2006.168.07:34:42.33#ibcon#about to read 4, iclass 12, count 0 2006.168.07:34:42.33#ibcon#read 4, iclass 12, count 0 2006.168.07:34:42.33#ibcon#about to read 5, iclass 12, count 0 2006.168.07:34:42.33#ibcon#read 5, iclass 12, count 0 2006.168.07:34:42.33#ibcon#about to read 6, iclass 12, count 0 2006.168.07:34:42.33#ibcon#read 6, iclass 12, count 0 2006.168.07:34:42.33#ibcon#end of sib2, iclass 12, count 0 2006.168.07:34:42.33#ibcon#*after write, iclass 12, count 0 2006.168.07:34:42.33#ibcon#*before return 0, iclass 12, count 0 2006.168.07:34:42.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.168.07:34:42.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.168.07:34:42.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.168.07:34:42.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.168.07:34:42.33$vc4f8/vb=6,4 2006.168.07:34:42.33#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.168.07:34:42.33#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.168.07:34:42.33#ibcon#ireg 11 cls_cnt 2 2006.168.07:34:42.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.168.07:34:42.39#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.168.07:34:42.39#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.168.07:34:42.39#ibcon#enter wrdev, iclass 14, count 2 2006.168.07:34:42.39#ibcon#first serial, iclass 14, count 2 2006.168.07:34:42.39#ibcon#enter sib2, iclass 14, count 2 2006.168.07:34:42.39#ibcon#flushed, iclass 14, count 2 2006.168.07:34:42.39#ibcon#about to write, iclass 14, count 2 2006.168.07:34:42.39#ibcon#wrote, iclass 14, count 2 2006.168.07:34:42.39#ibcon#about to read 3, iclass 14, count 2 2006.168.07:34:42.41#ibcon#read 3, iclass 14, count 2 2006.168.07:34:42.41#ibcon#about to read 4, iclass 14, count 2 2006.168.07:34:42.41#ibcon#read 4, iclass 14, count 2 2006.168.07:34:42.41#ibcon#about to read 5, iclass 14, count 2 2006.168.07:34:42.41#ibcon#read 5, iclass 14, count 2 2006.168.07:34:42.41#ibcon#about to read 6, iclass 14, count 2 2006.168.07:34:42.41#ibcon#read 6, iclass 14, count 2 2006.168.07:34:42.41#ibcon#end of sib2, iclass 14, count 2 2006.168.07:34:42.41#ibcon#*mode == 0, iclass 14, count 2 2006.168.07:34:42.41#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.168.07:34:42.41#ibcon#[27=AT06-04\r\n] 2006.168.07:34:42.41#ibcon#*before write, iclass 14, count 2 2006.168.07:34:42.41#ibcon#enter sib2, iclass 14, count 2 2006.168.07:34:42.41#ibcon#flushed, iclass 14, count 2 2006.168.07:34:42.41#ibcon#about to write, iclass 14, count 2 2006.168.07:34:42.41#ibcon#wrote, iclass 14, count 2 2006.168.07:34:42.41#ibcon#about to read 3, iclass 14, count 2 2006.168.07:34:42.44#ibcon#read 3, iclass 14, count 2 2006.168.07:34:42.44#ibcon#about to read 4, iclass 14, count 2 2006.168.07:34:42.44#ibcon#read 4, iclass 14, count 2 2006.168.07:34:42.44#ibcon#about to read 5, iclass 14, count 2 2006.168.07:34:42.44#ibcon#read 5, iclass 14, count 2 2006.168.07:34:42.44#ibcon#about to read 6, iclass 14, count 2 2006.168.07:34:42.44#ibcon#read 6, iclass 14, count 2 2006.168.07:34:42.44#ibcon#end of sib2, iclass 14, count 2 2006.168.07:34:42.44#ibcon#*after write, iclass 14, count 2 2006.168.07:34:42.44#ibcon#*before return 0, iclass 14, count 2 2006.168.07:34:42.44#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.168.07:34:42.44#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.168.07:34:42.44#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.168.07:34:42.44#ibcon#ireg 7 cls_cnt 0 2006.168.07:34:42.44#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.168.07:34:42.56#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.168.07:34:42.56#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.168.07:34:42.56#ibcon#enter wrdev, iclass 14, count 0 2006.168.07:34:42.56#ibcon#first serial, iclass 14, count 0 2006.168.07:34:42.56#ibcon#enter sib2, iclass 14, count 0 2006.168.07:34:42.56#ibcon#flushed, iclass 14, count 0 2006.168.07:34:42.56#ibcon#about to write, iclass 14, count 0 2006.168.07:34:42.56#ibcon#wrote, iclass 14, count 0 2006.168.07:34:42.56#ibcon#about to read 3, iclass 14, count 0 2006.168.07:34:42.58#ibcon#read 3, iclass 14, count 0 2006.168.07:34:42.58#ibcon#about to read 4, iclass 14, count 0 2006.168.07:34:42.58#ibcon#read 4, iclass 14, count 0 2006.168.07:34:42.58#ibcon#about to read 5, iclass 14, count 0 2006.168.07:34:42.58#ibcon#read 5, iclass 14, count 0 2006.168.07:34:42.58#ibcon#about to read 6, iclass 14, count 0 2006.168.07:34:42.58#ibcon#read 6, iclass 14, count 0 2006.168.07:34:42.58#ibcon#end of sib2, iclass 14, count 0 2006.168.07:34:42.58#ibcon#*mode == 0, iclass 14, count 0 2006.168.07:34:42.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.168.07:34:42.58#ibcon#[27=USB\r\n] 2006.168.07:34:42.58#ibcon#*before write, iclass 14, count 0 2006.168.07:34:42.58#ibcon#enter sib2, iclass 14, count 0 2006.168.07:34:42.58#ibcon#flushed, iclass 14, count 0 2006.168.07:34:42.58#ibcon#about to write, iclass 14, count 0 2006.168.07:34:42.58#ibcon#wrote, iclass 14, count 0 2006.168.07:34:42.58#ibcon#about to read 3, iclass 14, count 0 2006.168.07:34:42.61#ibcon#read 3, iclass 14, count 0 2006.168.07:34:42.61#ibcon#about to read 4, iclass 14, count 0 2006.168.07:34:42.61#ibcon#read 4, iclass 14, count 0 2006.168.07:34:42.61#ibcon#about to read 5, iclass 14, count 0 2006.168.07:34:42.61#ibcon#read 5, iclass 14, count 0 2006.168.07:34:42.61#ibcon#about to read 6, iclass 14, count 0 2006.168.07:34:42.61#ibcon#read 6, iclass 14, count 0 2006.168.07:34:42.61#ibcon#end of sib2, iclass 14, count 0 2006.168.07:34:42.61#ibcon#*after write, iclass 14, count 0 2006.168.07:34:42.61#ibcon#*before return 0, iclass 14, count 0 2006.168.07:34:42.61#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.168.07:34:42.61#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.168.07:34:42.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.168.07:34:42.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.168.07:34:42.61$vc4f8/vabw=wide 2006.168.07:34:42.61#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.168.07:34:42.61#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.168.07:34:42.61#ibcon#ireg 8 cls_cnt 0 2006.168.07:34:42.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:34:42.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:34:42.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:34:42.61#ibcon#enter wrdev, iclass 16, count 0 2006.168.07:34:42.61#ibcon#first serial, iclass 16, count 0 2006.168.07:34:42.61#ibcon#enter sib2, iclass 16, count 0 2006.168.07:34:42.61#ibcon#flushed, iclass 16, count 0 2006.168.07:34:42.61#ibcon#about to write, iclass 16, count 0 2006.168.07:34:42.61#ibcon#wrote, iclass 16, count 0 2006.168.07:34:42.61#ibcon#about to read 3, iclass 16, count 0 2006.168.07:34:42.63#ibcon#read 3, iclass 16, count 0 2006.168.07:34:42.63#ibcon#about to read 4, iclass 16, count 0 2006.168.07:34:42.63#ibcon#read 4, iclass 16, count 0 2006.168.07:34:42.63#ibcon#about to read 5, iclass 16, count 0 2006.168.07:34:42.63#ibcon#read 5, iclass 16, count 0 2006.168.07:34:42.63#ibcon#about to read 6, iclass 16, count 0 2006.168.07:34:42.63#ibcon#read 6, iclass 16, count 0 2006.168.07:34:42.63#ibcon#end of sib2, iclass 16, count 0 2006.168.07:34:42.63#ibcon#*mode == 0, iclass 16, count 0 2006.168.07:34:42.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.168.07:34:42.63#ibcon#[25=BW32\r\n] 2006.168.07:34:42.63#ibcon#*before write, iclass 16, count 0 2006.168.07:34:42.63#ibcon#enter sib2, iclass 16, count 0 2006.168.07:34:42.63#ibcon#flushed, iclass 16, count 0 2006.168.07:34:42.63#ibcon#about to write, iclass 16, count 0 2006.168.07:34:42.63#ibcon#wrote, iclass 16, count 0 2006.168.07:34:42.63#ibcon#about to read 3, iclass 16, count 0 2006.168.07:34:42.66#ibcon#read 3, iclass 16, count 0 2006.168.07:34:42.66#ibcon#about to read 4, iclass 16, count 0 2006.168.07:34:42.66#ibcon#read 4, iclass 16, count 0 2006.168.07:34:42.66#ibcon#about to read 5, iclass 16, count 0 2006.168.07:34:42.66#ibcon#read 5, iclass 16, count 0 2006.168.07:34:42.66#ibcon#about to read 6, iclass 16, count 0 2006.168.07:34:42.66#ibcon#read 6, iclass 16, count 0 2006.168.07:34:42.66#ibcon#end of sib2, iclass 16, count 0 2006.168.07:34:42.66#ibcon#*after write, iclass 16, count 0 2006.168.07:34:42.66#ibcon#*before return 0, iclass 16, count 0 2006.168.07:34:42.66#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:34:42.66#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:34:42.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.168.07:34:42.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.168.07:34:42.66$vc4f8/vbbw=wide 2006.168.07:34:42.66#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.168.07:34:42.66#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.168.07:34:42.66#ibcon#ireg 8 cls_cnt 0 2006.168.07:34:42.66#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:34:42.73#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:34:42.73#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:34:42.73#ibcon#enter wrdev, iclass 18, count 0 2006.168.07:34:42.73#ibcon#first serial, iclass 18, count 0 2006.168.07:34:42.73#ibcon#enter sib2, iclass 18, count 0 2006.168.07:34:42.73#ibcon#flushed, iclass 18, count 0 2006.168.07:34:42.73#ibcon#about to write, iclass 18, count 0 2006.168.07:34:42.73#ibcon#wrote, iclass 18, count 0 2006.168.07:34:42.73#ibcon#about to read 3, iclass 18, count 0 2006.168.07:34:42.75#ibcon#read 3, iclass 18, count 0 2006.168.07:34:42.75#ibcon#about to read 4, iclass 18, count 0 2006.168.07:34:42.75#ibcon#read 4, iclass 18, count 0 2006.168.07:34:42.75#ibcon#about to read 5, iclass 18, count 0 2006.168.07:34:42.75#ibcon#read 5, iclass 18, count 0 2006.168.07:34:42.75#ibcon#about to read 6, iclass 18, count 0 2006.168.07:34:42.75#ibcon#read 6, iclass 18, count 0 2006.168.07:34:42.75#ibcon#end of sib2, iclass 18, count 0 2006.168.07:34:42.75#ibcon#*mode == 0, iclass 18, count 0 2006.168.07:34:42.75#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.07:34:42.75#ibcon#[27=BW32\r\n] 2006.168.07:34:42.75#ibcon#*before write, iclass 18, count 0 2006.168.07:34:42.75#ibcon#enter sib2, iclass 18, count 0 2006.168.07:34:42.75#ibcon#flushed, iclass 18, count 0 2006.168.07:34:42.75#ibcon#about to write, iclass 18, count 0 2006.168.07:34:42.75#ibcon#wrote, iclass 18, count 0 2006.168.07:34:42.75#ibcon#about to read 3, iclass 18, count 0 2006.168.07:34:42.78#ibcon#read 3, iclass 18, count 0 2006.168.07:34:42.78#ibcon#about to read 4, iclass 18, count 0 2006.168.07:34:42.78#ibcon#read 4, iclass 18, count 0 2006.168.07:34:42.78#ibcon#about to read 5, iclass 18, count 0 2006.168.07:34:42.78#ibcon#read 5, iclass 18, count 0 2006.168.07:34:42.78#ibcon#about to read 6, iclass 18, count 0 2006.168.07:34:42.78#ibcon#read 6, iclass 18, count 0 2006.168.07:34:42.78#ibcon#end of sib2, iclass 18, count 0 2006.168.07:34:42.78#ibcon#*after write, iclass 18, count 0 2006.168.07:34:42.78#ibcon#*before return 0, iclass 18, count 0 2006.168.07:34:42.78#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:34:42.78#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:34:42.78#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.07:34:42.78#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.07:34:42.78$4f8m12a/ifd4f 2006.168.07:34:42.78$ifd4f/lo= 2006.168.07:34:42.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.07:34:42.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.07:34:42.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.07:34:42.78$ifd4f/patch= 2006.168.07:34:42.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.07:34:42.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.07:34:42.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.07:34:42.78$4f8m12a/"form=m,16.000,1:2 2006.168.07:34:42.78$4f8m12a/"tpicd 2006.168.07:34:42.78$4f8m12a/echo=off 2006.168.07:34:42.78$4f8m12a/xlog=off 2006.168.07:34:42.78:!2006.168.07:35:10 2006.168.07:34:54.14#trakl#Source acquired 2006.168.07:34:55.14#flagr#flagr/antenna,acquired 2006.168.07:35:10.00:preob 2006.168.07:35:11.14/onsource/TRACKING 2006.168.07:35:11.14:!2006.168.07:35:20 2006.168.07:35:20.00:data_valid=on 2006.168.07:35:20.00:midob 2006.168.07:35:20.14/onsource/TRACKING 2006.168.07:35:20.14/wx/27.88,1004.6,73 2006.168.07:35:20.32/cable/+6.4724E-03 2006.168.07:35:21.41/va/01,08,usb,yes,29,31 2006.168.07:35:21.41/va/02,07,usb,yes,29,30 2006.168.07:35:21.41/va/03,06,usb,yes,31,31 2006.168.07:35:21.41/va/04,07,usb,yes,30,32 2006.168.07:35:21.41/va/05,07,usb,yes,29,31 2006.168.07:35:21.41/va/06,06,usb,yes,28,28 2006.168.07:35:21.41/va/07,06,usb,yes,29,28 2006.168.07:35:21.41/va/08,07,usb,yes,27,27 2006.168.07:35:21.64/valo/01,532.99,yes,locked 2006.168.07:35:21.64/valo/02,572.99,yes,locked 2006.168.07:35:21.64/valo/03,672.99,yes,locked 2006.168.07:35:21.64/valo/04,832.99,yes,locked 2006.168.07:35:21.64/valo/05,652.99,yes,locked 2006.168.07:35:21.64/valo/06,772.99,yes,locked 2006.168.07:35:21.64/valo/07,832.99,yes,locked 2006.168.07:35:21.64/valo/08,852.99,yes,locked 2006.168.07:35:22.73/vb/01,04,usb,yes,29,28 2006.168.07:35:22.73/vb/02,04,usb,yes,31,32 2006.168.07:35:22.73/vb/03,04,usb,yes,27,31 2006.168.07:35:22.73/vb/04,04,usb,yes,28,28 2006.168.07:35:22.73/vb/05,04,usb,yes,27,30 2006.168.07:35:22.73/vb/06,04,usb,yes,27,30 2006.168.07:35:22.73/vb/07,04,usb,yes,29,29 2006.168.07:35:22.73/vb/08,04,usb,yes,27,30 2006.168.07:35:22.97/vblo/01,632.99,yes,locked 2006.168.07:35:22.97/vblo/02,640.99,yes,locked 2006.168.07:35:22.97/vblo/03,656.99,yes,locked 2006.168.07:35:22.97/vblo/04,712.99,yes,locked 2006.168.07:35:22.97/vblo/05,744.99,yes,locked 2006.168.07:35:22.97/vblo/06,752.99,yes,locked 2006.168.07:35:22.97/vblo/07,734.99,yes,locked 2006.168.07:35:22.97/vblo/08,744.99,yes,locked 2006.168.07:35:23.12/vabw/8 2006.168.07:35:23.27/vbbw/8 2006.168.07:35:23.39/xfe/off,on,14.2 2006.168.07:35:23.76/ifatt/23,28,28,28 2006.168.07:35:24.08/fmout-gps/S +4.21E-07 2006.168.07:35:24.16:!2006.168.07:36:20 2006.168.07:36:20.00:data_valid=off 2006.168.07:36:20.00:postob 2006.168.07:36:20.09/cable/+6.4726E-03 2006.168.07:36:20.09/wx/27.86,1004.6,72 2006.168.07:36:21.08/fmout-gps/S +4.21E-07 2006.168.07:36:21.08:scan_name=168-0737,k06168,60 2006.168.07:36:21.09:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.168.07:36:21.13#flagr#flagr/antenna,new-source 2006.168.07:36:22.13:checkk5 2006.168.07:36:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.168.07:36:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.168.07:36:23.26/chk_autoobs//k5ts3/ autoobs is running! 2006.168.07:36:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.168.07:36:24.01/chk_obsdata//k5ts1/T1680735??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:36:24.38/chk_obsdata//k5ts2/T1680735??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:36:24.75/chk_obsdata//k5ts3/T1680735??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:36:25.12/chk_obsdata//k5ts4/T1680735??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:36:25.82/k5log//k5ts1_log_newline 2006.168.07:36:26.51/k5log//k5ts2_log_newline 2006.168.07:36:27.19/k5log//k5ts3_log_newline 2006.168.07:36:27.88/k5log//k5ts4_log_newline 2006.168.07:36:27.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.07:36:27.91:4f8m12a=1 2006.168.07:36:27.91$4f8m12a/echo=on 2006.168.07:36:27.91$4f8m12a/pcalon 2006.168.07:36:27.91$pcalon/"no phase cal control is implemented here 2006.168.07:36:27.91$4f8m12a/"tpicd=stop 2006.168.07:36:27.91$4f8m12a/vc4f8 2006.168.07:36:27.91$vc4f8/valo=1,532.99 2006.168.07:36:27.92#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.168.07:36:27.92#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.168.07:36:27.92#ibcon#ireg 17 cls_cnt 0 2006.168.07:36:27.92#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.168.07:36:27.92#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.168.07:36:27.92#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.168.07:36:27.92#ibcon#enter wrdev, iclass 25, count 0 2006.168.07:36:27.92#ibcon#first serial, iclass 25, count 0 2006.168.07:36:27.92#ibcon#enter sib2, iclass 25, count 0 2006.168.07:36:27.92#ibcon#flushed, iclass 25, count 0 2006.168.07:36:27.92#ibcon#about to write, iclass 25, count 0 2006.168.07:36:27.92#ibcon#wrote, iclass 25, count 0 2006.168.07:36:27.92#ibcon#about to read 3, iclass 25, count 0 2006.168.07:36:27.95#ibcon#read 3, iclass 25, count 0 2006.168.07:36:27.95#ibcon#about to read 4, iclass 25, count 0 2006.168.07:36:27.95#ibcon#read 4, iclass 25, count 0 2006.168.07:36:27.95#ibcon#about to read 5, iclass 25, count 0 2006.168.07:36:27.95#ibcon#read 5, iclass 25, count 0 2006.168.07:36:27.95#ibcon#about to read 6, iclass 25, count 0 2006.168.07:36:27.95#ibcon#read 6, iclass 25, count 0 2006.168.07:36:27.95#ibcon#end of sib2, iclass 25, count 0 2006.168.07:36:27.95#ibcon#*mode == 0, iclass 25, count 0 2006.168.07:36:27.95#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.168.07:36:27.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.07:36:27.95#ibcon#*before write, iclass 25, count 0 2006.168.07:36:27.95#ibcon#enter sib2, iclass 25, count 0 2006.168.07:36:27.95#ibcon#flushed, iclass 25, count 0 2006.168.07:36:27.95#ibcon#about to write, iclass 25, count 0 2006.168.07:36:27.95#ibcon#wrote, iclass 25, count 0 2006.168.07:36:27.95#ibcon#about to read 3, iclass 25, count 0 2006.168.07:36:28.00#ibcon#read 3, iclass 25, count 0 2006.168.07:36:28.00#ibcon#about to read 4, iclass 25, count 0 2006.168.07:36:28.00#ibcon#read 4, iclass 25, count 0 2006.168.07:36:28.00#ibcon#about to read 5, iclass 25, count 0 2006.168.07:36:28.00#ibcon#read 5, iclass 25, count 0 2006.168.07:36:28.00#ibcon#about to read 6, iclass 25, count 0 2006.168.07:36:28.00#ibcon#read 6, iclass 25, count 0 2006.168.07:36:28.00#ibcon#end of sib2, iclass 25, count 0 2006.168.07:36:28.00#ibcon#*after write, iclass 25, count 0 2006.168.07:36:28.00#ibcon#*before return 0, iclass 25, count 0 2006.168.07:36:28.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.168.07:36:28.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.168.07:36:28.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.168.07:36:28.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.168.07:36:28.00$vc4f8/va=1,8 2006.168.07:36:28.00#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.168.07:36:28.00#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.168.07:36:28.00#ibcon#ireg 11 cls_cnt 2 2006.168.07:36:28.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.168.07:36:28.00#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.168.07:36:28.00#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.168.07:36:28.00#ibcon#enter wrdev, iclass 27, count 2 2006.168.07:36:28.00#ibcon#first serial, iclass 27, count 2 2006.168.07:36:28.00#ibcon#enter sib2, iclass 27, count 2 2006.168.07:36:28.00#ibcon#flushed, iclass 27, count 2 2006.168.07:36:28.00#ibcon#about to write, iclass 27, count 2 2006.168.07:36:28.00#ibcon#wrote, iclass 27, count 2 2006.168.07:36:28.00#ibcon#about to read 3, iclass 27, count 2 2006.168.07:36:28.02#ibcon#read 3, iclass 27, count 2 2006.168.07:36:28.02#ibcon#about to read 4, iclass 27, count 2 2006.168.07:36:28.02#ibcon#read 4, iclass 27, count 2 2006.168.07:36:28.02#ibcon#about to read 5, iclass 27, count 2 2006.168.07:36:28.02#ibcon#read 5, iclass 27, count 2 2006.168.07:36:28.02#ibcon#about to read 6, iclass 27, count 2 2006.168.07:36:28.02#ibcon#read 6, iclass 27, count 2 2006.168.07:36:28.02#ibcon#end of sib2, iclass 27, count 2 2006.168.07:36:28.02#ibcon#*mode == 0, iclass 27, count 2 2006.168.07:36:28.02#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.168.07:36:28.02#ibcon#[25=AT01-08\r\n] 2006.168.07:36:28.02#ibcon#*before write, iclass 27, count 2 2006.168.07:36:28.02#ibcon#enter sib2, iclass 27, count 2 2006.168.07:36:28.02#ibcon#flushed, iclass 27, count 2 2006.168.07:36:28.02#ibcon#about to write, iclass 27, count 2 2006.168.07:36:28.02#ibcon#wrote, iclass 27, count 2 2006.168.07:36:28.02#ibcon#about to read 3, iclass 27, count 2 2006.168.07:36:28.05#ibcon#read 3, iclass 27, count 2 2006.168.07:36:28.05#ibcon#about to read 4, iclass 27, count 2 2006.168.07:36:28.05#ibcon#read 4, iclass 27, count 2 2006.168.07:36:28.05#ibcon#about to read 5, iclass 27, count 2 2006.168.07:36:28.05#ibcon#read 5, iclass 27, count 2 2006.168.07:36:28.05#ibcon#about to read 6, iclass 27, count 2 2006.168.07:36:28.05#ibcon#read 6, iclass 27, count 2 2006.168.07:36:28.05#ibcon#end of sib2, iclass 27, count 2 2006.168.07:36:28.05#ibcon#*after write, iclass 27, count 2 2006.168.07:36:28.05#ibcon#*before return 0, iclass 27, count 2 2006.168.07:36:28.05#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.168.07:36:28.05#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.168.07:36:28.05#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.168.07:36:28.05#ibcon#ireg 7 cls_cnt 0 2006.168.07:36:28.05#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.168.07:36:28.17#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.168.07:36:28.17#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.168.07:36:28.17#ibcon#enter wrdev, iclass 27, count 0 2006.168.07:36:28.17#ibcon#first serial, iclass 27, count 0 2006.168.07:36:28.17#ibcon#enter sib2, iclass 27, count 0 2006.168.07:36:28.17#ibcon#flushed, iclass 27, count 0 2006.168.07:36:28.17#ibcon#about to write, iclass 27, count 0 2006.168.07:36:28.17#ibcon#wrote, iclass 27, count 0 2006.168.07:36:28.17#ibcon#about to read 3, iclass 27, count 0 2006.168.07:36:28.19#ibcon#read 3, iclass 27, count 0 2006.168.07:36:28.19#ibcon#about to read 4, iclass 27, count 0 2006.168.07:36:28.19#ibcon#read 4, iclass 27, count 0 2006.168.07:36:28.19#ibcon#about to read 5, iclass 27, count 0 2006.168.07:36:28.19#ibcon#read 5, iclass 27, count 0 2006.168.07:36:28.19#ibcon#about to read 6, iclass 27, count 0 2006.168.07:36:28.19#ibcon#read 6, iclass 27, count 0 2006.168.07:36:28.19#ibcon#end of sib2, iclass 27, count 0 2006.168.07:36:28.19#ibcon#*mode == 0, iclass 27, count 0 2006.168.07:36:28.19#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.168.07:36:28.19#ibcon#[25=USB\r\n] 2006.168.07:36:28.19#ibcon#*before write, iclass 27, count 0 2006.168.07:36:28.19#ibcon#enter sib2, iclass 27, count 0 2006.168.07:36:28.19#ibcon#flushed, iclass 27, count 0 2006.168.07:36:28.19#ibcon#about to write, iclass 27, count 0 2006.168.07:36:28.19#ibcon#wrote, iclass 27, count 0 2006.168.07:36:28.19#ibcon#about to read 3, iclass 27, count 0 2006.168.07:36:28.22#ibcon#read 3, iclass 27, count 0 2006.168.07:36:28.22#ibcon#about to read 4, iclass 27, count 0 2006.168.07:36:28.22#ibcon#read 4, iclass 27, count 0 2006.168.07:36:28.22#ibcon#about to read 5, iclass 27, count 0 2006.168.07:36:28.22#ibcon#read 5, iclass 27, count 0 2006.168.07:36:28.22#ibcon#about to read 6, iclass 27, count 0 2006.168.07:36:28.22#ibcon#read 6, iclass 27, count 0 2006.168.07:36:28.22#ibcon#end of sib2, iclass 27, count 0 2006.168.07:36:28.22#ibcon#*after write, iclass 27, count 0 2006.168.07:36:28.22#ibcon#*before return 0, iclass 27, count 0 2006.168.07:36:28.22#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.168.07:36:28.22#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.168.07:36:28.22#ibcon#about to clear, iclass 27 cls_cnt 0 2006.168.07:36:28.22#ibcon#cleared, iclass 27 cls_cnt 0 2006.168.07:36:28.22$vc4f8/valo=2,572.99 2006.168.07:36:28.22#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.168.07:36:28.22#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.168.07:36:28.22#ibcon#ireg 17 cls_cnt 0 2006.168.07:36:28.22#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.168.07:36:28.22#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.168.07:36:28.22#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.168.07:36:28.22#ibcon#enter wrdev, iclass 29, count 0 2006.168.07:36:28.22#ibcon#first serial, iclass 29, count 0 2006.168.07:36:28.22#ibcon#enter sib2, iclass 29, count 0 2006.168.07:36:28.22#ibcon#flushed, iclass 29, count 0 2006.168.07:36:28.22#ibcon#about to write, iclass 29, count 0 2006.168.07:36:28.22#ibcon#wrote, iclass 29, count 0 2006.168.07:36:28.22#ibcon#about to read 3, iclass 29, count 0 2006.168.07:36:28.25#ibcon#read 3, iclass 29, count 0 2006.168.07:36:28.25#ibcon#about to read 4, iclass 29, count 0 2006.168.07:36:28.25#ibcon#read 4, iclass 29, count 0 2006.168.07:36:28.25#ibcon#about to read 5, iclass 29, count 0 2006.168.07:36:28.25#ibcon#read 5, iclass 29, count 0 2006.168.07:36:28.25#ibcon#about to read 6, iclass 29, count 0 2006.168.07:36:28.25#ibcon#read 6, iclass 29, count 0 2006.168.07:36:28.25#ibcon#end of sib2, iclass 29, count 0 2006.168.07:36:28.25#ibcon#*mode == 0, iclass 29, count 0 2006.168.07:36:28.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.168.07:36:28.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.07:36:28.25#ibcon#*before write, iclass 29, count 0 2006.168.07:36:28.25#ibcon#enter sib2, iclass 29, count 0 2006.168.07:36:28.25#ibcon#flushed, iclass 29, count 0 2006.168.07:36:28.25#ibcon#about to write, iclass 29, count 0 2006.168.07:36:28.25#ibcon#wrote, iclass 29, count 0 2006.168.07:36:28.25#ibcon#about to read 3, iclass 29, count 0 2006.168.07:36:28.29#ibcon#read 3, iclass 29, count 0 2006.168.07:36:28.29#ibcon#about to read 4, iclass 29, count 0 2006.168.07:36:28.29#ibcon#read 4, iclass 29, count 0 2006.168.07:36:28.29#ibcon#about to read 5, iclass 29, count 0 2006.168.07:36:28.29#ibcon#read 5, iclass 29, count 0 2006.168.07:36:28.29#ibcon#about to read 6, iclass 29, count 0 2006.168.07:36:28.29#ibcon#read 6, iclass 29, count 0 2006.168.07:36:28.29#ibcon#end of sib2, iclass 29, count 0 2006.168.07:36:28.29#ibcon#*after write, iclass 29, count 0 2006.168.07:36:28.29#ibcon#*before return 0, iclass 29, count 0 2006.168.07:36:28.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.168.07:36:28.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.168.07:36:28.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.168.07:36:28.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.168.07:36:28.29$vc4f8/va=2,7 2006.168.07:36:28.29#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.168.07:36:28.29#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.168.07:36:28.29#ibcon#ireg 11 cls_cnt 2 2006.168.07:36:28.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.168.07:36:28.34#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.168.07:36:28.34#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.168.07:36:28.34#ibcon#enter wrdev, iclass 31, count 2 2006.168.07:36:28.34#ibcon#first serial, iclass 31, count 2 2006.168.07:36:28.34#ibcon#enter sib2, iclass 31, count 2 2006.168.07:36:28.34#ibcon#flushed, iclass 31, count 2 2006.168.07:36:28.34#ibcon#about to write, iclass 31, count 2 2006.168.07:36:28.34#ibcon#wrote, iclass 31, count 2 2006.168.07:36:28.34#ibcon#about to read 3, iclass 31, count 2 2006.168.07:36:28.36#ibcon#read 3, iclass 31, count 2 2006.168.07:36:28.36#ibcon#about to read 4, iclass 31, count 2 2006.168.07:36:28.36#ibcon#read 4, iclass 31, count 2 2006.168.07:36:28.36#ibcon#about to read 5, iclass 31, count 2 2006.168.07:36:28.36#ibcon#read 5, iclass 31, count 2 2006.168.07:36:28.36#ibcon#about to read 6, iclass 31, count 2 2006.168.07:36:28.36#ibcon#read 6, iclass 31, count 2 2006.168.07:36:28.36#ibcon#end of sib2, iclass 31, count 2 2006.168.07:36:28.36#ibcon#*mode == 0, iclass 31, count 2 2006.168.07:36:28.36#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.168.07:36:28.36#ibcon#[25=AT02-07\r\n] 2006.168.07:36:28.36#ibcon#*before write, iclass 31, count 2 2006.168.07:36:28.36#ibcon#enter sib2, iclass 31, count 2 2006.168.07:36:28.36#ibcon#flushed, iclass 31, count 2 2006.168.07:36:28.36#ibcon#about to write, iclass 31, count 2 2006.168.07:36:28.36#ibcon#wrote, iclass 31, count 2 2006.168.07:36:28.36#ibcon#about to read 3, iclass 31, count 2 2006.168.07:36:28.39#ibcon#read 3, iclass 31, count 2 2006.168.07:36:28.39#ibcon#about to read 4, iclass 31, count 2 2006.168.07:36:28.39#ibcon#read 4, iclass 31, count 2 2006.168.07:36:28.39#ibcon#about to read 5, iclass 31, count 2 2006.168.07:36:28.39#ibcon#read 5, iclass 31, count 2 2006.168.07:36:28.39#ibcon#about to read 6, iclass 31, count 2 2006.168.07:36:28.39#ibcon#read 6, iclass 31, count 2 2006.168.07:36:28.39#ibcon#end of sib2, iclass 31, count 2 2006.168.07:36:28.39#ibcon#*after write, iclass 31, count 2 2006.168.07:36:28.39#ibcon#*before return 0, iclass 31, count 2 2006.168.07:36:28.39#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.168.07:36:28.39#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.168.07:36:28.39#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.168.07:36:28.39#ibcon#ireg 7 cls_cnt 0 2006.168.07:36:28.39#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.168.07:36:28.51#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.168.07:36:28.51#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.168.07:36:28.51#ibcon#enter wrdev, iclass 31, count 0 2006.168.07:36:28.51#ibcon#first serial, iclass 31, count 0 2006.168.07:36:28.51#ibcon#enter sib2, iclass 31, count 0 2006.168.07:36:28.51#ibcon#flushed, iclass 31, count 0 2006.168.07:36:28.51#ibcon#about to write, iclass 31, count 0 2006.168.07:36:28.51#ibcon#wrote, iclass 31, count 0 2006.168.07:36:28.51#ibcon#about to read 3, iclass 31, count 0 2006.168.07:36:28.53#ibcon#read 3, iclass 31, count 0 2006.168.07:36:28.53#ibcon#about to read 4, iclass 31, count 0 2006.168.07:36:28.53#ibcon#read 4, iclass 31, count 0 2006.168.07:36:28.53#ibcon#about to read 5, iclass 31, count 0 2006.168.07:36:28.53#ibcon#read 5, iclass 31, count 0 2006.168.07:36:28.53#ibcon#about to read 6, iclass 31, count 0 2006.168.07:36:28.53#ibcon#read 6, iclass 31, count 0 2006.168.07:36:28.53#ibcon#end of sib2, iclass 31, count 0 2006.168.07:36:28.53#ibcon#*mode == 0, iclass 31, count 0 2006.168.07:36:28.53#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.168.07:36:28.53#ibcon#[25=USB\r\n] 2006.168.07:36:28.53#ibcon#*before write, iclass 31, count 0 2006.168.07:36:28.53#ibcon#enter sib2, iclass 31, count 0 2006.168.07:36:28.53#ibcon#flushed, iclass 31, count 0 2006.168.07:36:28.53#ibcon#about to write, iclass 31, count 0 2006.168.07:36:28.53#ibcon#wrote, iclass 31, count 0 2006.168.07:36:28.53#ibcon#about to read 3, iclass 31, count 0 2006.168.07:36:28.56#ibcon#read 3, iclass 31, count 0 2006.168.07:36:28.56#ibcon#about to read 4, iclass 31, count 0 2006.168.07:36:28.56#ibcon#read 4, iclass 31, count 0 2006.168.07:36:28.56#ibcon#about to read 5, iclass 31, count 0 2006.168.07:36:28.56#ibcon#read 5, iclass 31, count 0 2006.168.07:36:28.56#ibcon#about to read 6, iclass 31, count 0 2006.168.07:36:28.56#ibcon#read 6, iclass 31, count 0 2006.168.07:36:28.56#ibcon#end of sib2, iclass 31, count 0 2006.168.07:36:28.56#ibcon#*after write, iclass 31, count 0 2006.168.07:36:28.56#ibcon#*before return 0, iclass 31, count 0 2006.168.07:36:28.56#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.168.07:36:28.56#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.168.07:36:28.56#ibcon#about to clear, iclass 31 cls_cnt 0 2006.168.07:36:28.56#ibcon#cleared, iclass 31 cls_cnt 0 2006.168.07:36:28.56$vc4f8/valo=3,672.99 2006.168.07:36:28.56#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.168.07:36:28.56#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.168.07:36:28.56#ibcon#ireg 17 cls_cnt 0 2006.168.07:36:28.56#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.168.07:36:28.56#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.168.07:36:28.56#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.168.07:36:28.56#ibcon#enter wrdev, iclass 33, count 0 2006.168.07:36:28.56#ibcon#first serial, iclass 33, count 0 2006.168.07:36:28.56#ibcon#enter sib2, iclass 33, count 0 2006.168.07:36:28.56#ibcon#flushed, iclass 33, count 0 2006.168.07:36:28.56#ibcon#about to write, iclass 33, count 0 2006.168.07:36:28.56#ibcon#wrote, iclass 33, count 0 2006.168.07:36:28.56#ibcon#about to read 3, iclass 33, count 0 2006.168.07:36:28.58#ibcon#read 3, iclass 33, count 0 2006.168.07:36:28.58#ibcon#about to read 4, iclass 33, count 0 2006.168.07:36:28.58#ibcon#read 4, iclass 33, count 0 2006.168.07:36:28.58#ibcon#about to read 5, iclass 33, count 0 2006.168.07:36:28.58#ibcon#read 5, iclass 33, count 0 2006.168.07:36:28.58#ibcon#about to read 6, iclass 33, count 0 2006.168.07:36:28.58#ibcon#read 6, iclass 33, count 0 2006.168.07:36:28.58#ibcon#end of sib2, iclass 33, count 0 2006.168.07:36:28.58#ibcon#*mode == 0, iclass 33, count 0 2006.168.07:36:28.58#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.168.07:36:28.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.07:36:28.58#ibcon#*before write, iclass 33, count 0 2006.168.07:36:28.58#ibcon#enter sib2, iclass 33, count 0 2006.168.07:36:28.58#ibcon#flushed, iclass 33, count 0 2006.168.07:36:28.58#ibcon#about to write, iclass 33, count 0 2006.168.07:36:28.58#ibcon#wrote, iclass 33, count 0 2006.168.07:36:28.58#ibcon#about to read 3, iclass 33, count 0 2006.168.07:36:28.62#ibcon#read 3, iclass 33, count 0 2006.168.07:36:28.62#ibcon#about to read 4, iclass 33, count 0 2006.168.07:36:28.62#ibcon#read 4, iclass 33, count 0 2006.168.07:36:28.62#ibcon#about to read 5, iclass 33, count 0 2006.168.07:36:28.62#ibcon#read 5, iclass 33, count 0 2006.168.07:36:28.62#ibcon#about to read 6, iclass 33, count 0 2006.168.07:36:28.62#ibcon#read 6, iclass 33, count 0 2006.168.07:36:28.62#ibcon#end of sib2, iclass 33, count 0 2006.168.07:36:28.62#ibcon#*after write, iclass 33, count 0 2006.168.07:36:28.62#ibcon#*before return 0, iclass 33, count 0 2006.168.07:36:28.62#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.168.07:36:28.62#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.168.07:36:28.62#ibcon#about to clear, iclass 33 cls_cnt 0 2006.168.07:36:28.62#ibcon#cleared, iclass 33 cls_cnt 0 2006.168.07:36:28.62$vc4f8/va=3,6 2006.168.07:36:28.62#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.168.07:36:28.62#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.168.07:36:28.62#ibcon#ireg 11 cls_cnt 2 2006.168.07:36:28.62#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:36:28.68#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:36:28.68#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:36:28.68#ibcon#enter wrdev, iclass 35, count 2 2006.168.07:36:28.68#ibcon#first serial, iclass 35, count 2 2006.168.07:36:28.68#ibcon#enter sib2, iclass 35, count 2 2006.168.07:36:28.68#ibcon#flushed, iclass 35, count 2 2006.168.07:36:28.68#ibcon#about to write, iclass 35, count 2 2006.168.07:36:28.68#ibcon#wrote, iclass 35, count 2 2006.168.07:36:28.68#ibcon#about to read 3, iclass 35, count 2 2006.168.07:36:28.71#ibcon#read 3, iclass 35, count 2 2006.168.07:36:28.71#ibcon#about to read 4, iclass 35, count 2 2006.168.07:36:28.71#ibcon#read 4, iclass 35, count 2 2006.168.07:36:28.71#ibcon#about to read 5, iclass 35, count 2 2006.168.07:36:28.71#ibcon#read 5, iclass 35, count 2 2006.168.07:36:28.71#ibcon#about to read 6, iclass 35, count 2 2006.168.07:36:28.71#ibcon#read 6, iclass 35, count 2 2006.168.07:36:28.71#ibcon#end of sib2, iclass 35, count 2 2006.168.07:36:28.71#ibcon#*mode == 0, iclass 35, count 2 2006.168.07:36:28.71#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.168.07:36:28.71#ibcon#[25=AT03-06\r\n] 2006.168.07:36:28.71#ibcon#*before write, iclass 35, count 2 2006.168.07:36:28.71#ibcon#enter sib2, iclass 35, count 2 2006.168.07:36:28.71#ibcon#flushed, iclass 35, count 2 2006.168.07:36:28.71#ibcon#about to write, iclass 35, count 2 2006.168.07:36:28.71#ibcon#wrote, iclass 35, count 2 2006.168.07:36:28.71#ibcon#about to read 3, iclass 35, count 2 2006.168.07:36:28.74#ibcon#read 3, iclass 35, count 2 2006.168.07:36:28.74#ibcon#about to read 4, iclass 35, count 2 2006.168.07:36:28.74#ibcon#read 4, iclass 35, count 2 2006.168.07:36:28.74#ibcon#about to read 5, iclass 35, count 2 2006.168.07:36:28.74#ibcon#read 5, iclass 35, count 2 2006.168.07:36:28.74#ibcon#about to read 6, iclass 35, count 2 2006.168.07:36:28.74#ibcon#read 6, iclass 35, count 2 2006.168.07:36:28.74#ibcon#end of sib2, iclass 35, count 2 2006.168.07:36:28.74#ibcon#*after write, iclass 35, count 2 2006.168.07:36:28.74#ibcon#*before return 0, iclass 35, count 2 2006.168.07:36:28.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:36:28.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:36:28.74#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.168.07:36:28.74#ibcon#ireg 7 cls_cnt 0 2006.168.07:36:28.74#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:36:28.86#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:36:28.86#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:36:28.86#ibcon#enter wrdev, iclass 35, count 0 2006.168.07:36:28.86#ibcon#first serial, iclass 35, count 0 2006.168.07:36:28.86#ibcon#enter sib2, iclass 35, count 0 2006.168.07:36:28.86#ibcon#flushed, iclass 35, count 0 2006.168.07:36:28.86#ibcon#about to write, iclass 35, count 0 2006.168.07:36:28.86#ibcon#wrote, iclass 35, count 0 2006.168.07:36:28.86#ibcon#about to read 3, iclass 35, count 0 2006.168.07:36:28.88#ibcon#read 3, iclass 35, count 0 2006.168.07:36:28.88#ibcon#about to read 4, iclass 35, count 0 2006.168.07:36:28.88#ibcon#read 4, iclass 35, count 0 2006.168.07:36:28.88#ibcon#about to read 5, iclass 35, count 0 2006.168.07:36:28.88#ibcon#read 5, iclass 35, count 0 2006.168.07:36:28.88#ibcon#about to read 6, iclass 35, count 0 2006.168.07:36:28.88#ibcon#read 6, iclass 35, count 0 2006.168.07:36:28.88#ibcon#end of sib2, iclass 35, count 0 2006.168.07:36:28.88#ibcon#*mode == 0, iclass 35, count 0 2006.168.07:36:28.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.168.07:36:28.88#ibcon#[25=USB\r\n] 2006.168.07:36:28.88#ibcon#*before write, iclass 35, count 0 2006.168.07:36:28.88#ibcon#enter sib2, iclass 35, count 0 2006.168.07:36:28.88#ibcon#flushed, iclass 35, count 0 2006.168.07:36:28.88#ibcon#about to write, iclass 35, count 0 2006.168.07:36:28.88#ibcon#wrote, iclass 35, count 0 2006.168.07:36:28.88#ibcon#about to read 3, iclass 35, count 0 2006.168.07:36:28.91#ibcon#read 3, iclass 35, count 0 2006.168.07:36:28.91#ibcon#about to read 4, iclass 35, count 0 2006.168.07:36:28.91#ibcon#read 4, iclass 35, count 0 2006.168.07:36:28.91#ibcon#about to read 5, iclass 35, count 0 2006.168.07:36:28.91#ibcon#read 5, iclass 35, count 0 2006.168.07:36:28.91#ibcon#about to read 6, iclass 35, count 0 2006.168.07:36:28.91#ibcon#read 6, iclass 35, count 0 2006.168.07:36:28.91#ibcon#end of sib2, iclass 35, count 0 2006.168.07:36:28.91#ibcon#*after write, iclass 35, count 0 2006.168.07:36:28.91#ibcon#*before return 0, iclass 35, count 0 2006.168.07:36:28.91#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:36:28.91#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:36:28.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.168.07:36:28.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.168.07:36:28.91$vc4f8/valo=4,832.99 2006.168.07:36:28.91#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.168.07:36:28.91#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.168.07:36:28.91#ibcon#ireg 17 cls_cnt 0 2006.168.07:36:28.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:36:28.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:36:28.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:36:28.91#ibcon#enter wrdev, iclass 37, count 0 2006.168.07:36:28.91#ibcon#first serial, iclass 37, count 0 2006.168.07:36:28.91#ibcon#enter sib2, iclass 37, count 0 2006.168.07:36:28.91#ibcon#flushed, iclass 37, count 0 2006.168.07:36:28.91#ibcon#about to write, iclass 37, count 0 2006.168.07:36:28.91#ibcon#wrote, iclass 37, count 0 2006.168.07:36:28.91#ibcon#about to read 3, iclass 37, count 0 2006.168.07:36:28.93#ibcon#read 3, iclass 37, count 0 2006.168.07:36:28.93#ibcon#about to read 4, iclass 37, count 0 2006.168.07:36:28.93#ibcon#read 4, iclass 37, count 0 2006.168.07:36:28.93#ibcon#about to read 5, iclass 37, count 0 2006.168.07:36:28.93#ibcon#read 5, iclass 37, count 0 2006.168.07:36:28.93#ibcon#about to read 6, iclass 37, count 0 2006.168.07:36:28.93#ibcon#read 6, iclass 37, count 0 2006.168.07:36:28.93#ibcon#end of sib2, iclass 37, count 0 2006.168.07:36:28.93#ibcon#*mode == 0, iclass 37, count 0 2006.168.07:36:28.93#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.168.07:36:28.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.07:36:28.93#ibcon#*before write, iclass 37, count 0 2006.168.07:36:28.93#ibcon#enter sib2, iclass 37, count 0 2006.168.07:36:28.93#ibcon#flushed, iclass 37, count 0 2006.168.07:36:28.93#ibcon#about to write, iclass 37, count 0 2006.168.07:36:28.93#ibcon#wrote, iclass 37, count 0 2006.168.07:36:28.93#ibcon#about to read 3, iclass 37, count 0 2006.168.07:36:28.97#ibcon#read 3, iclass 37, count 0 2006.168.07:36:28.97#ibcon#about to read 4, iclass 37, count 0 2006.168.07:36:28.97#ibcon#read 4, iclass 37, count 0 2006.168.07:36:28.97#ibcon#about to read 5, iclass 37, count 0 2006.168.07:36:28.97#ibcon#read 5, iclass 37, count 0 2006.168.07:36:28.97#ibcon#about to read 6, iclass 37, count 0 2006.168.07:36:28.97#ibcon#read 6, iclass 37, count 0 2006.168.07:36:28.97#ibcon#end of sib2, iclass 37, count 0 2006.168.07:36:28.97#ibcon#*after write, iclass 37, count 0 2006.168.07:36:28.97#ibcon#*before return 0, iclass 37, count 0 2006.168.07:36:28.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:36:28.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:36:28.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.168.07:36:28.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.168.07:36:28.97$vc4f8/va=4,7 2006.168.07:36:28.97#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.168.07:36:28.97#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.168.07:36:28.97#ibcon#ireg 11 cls_cnt 2 2006.168.07:36:28.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:36:29.03#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:36:29.03#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:36:29.03#ibcon#enter wrdev, iclass 39, count 2 2006.168.07:36:29.03#ibcon#first serial, iclass 39, count 2 2006.168.07:36:29.03#ibcon#enter sib2, iclass 39, count 2 2006.168.07:36:29.03#ibcon#flushed, iclass 39, count 2 2006.168.07:36:29.03#ibcon#about to write, iclass 39, count 2 2006.168.07:36:29.03#ibcon#wrote, iclass 39, count 2 2006.168.07:36:29.03#ibcon#about to read 3, iclass 39, count 2 2006.168.07:36:29.05#ibcon#read 3, iclass 39, count 2 2006.168.07:36:29.05#ibcon#about to read 4, iclass 39, count 2 2006.168.07:36:29.05#ibcon#read 4, iclass 39, count 2 2006.168.07:36:29.05#ibcon#about to read 5, iclass 39, count 2 2006.168.07:36:29.05#ibcon#read 5, iclass 39, count 2 2006.168.07:36:29.05#ibcon#about to read 6, iclass 39, count 2 2006.168.07:36:29.05#ibcon#read 6, iclass 39, count 2 2006.168.07:36:29.05#ibcon#end of sib2, iclass 39, count 2 2006.168.07:36:29.05#ibcon#*mode == 0, iclass 39, count 2 2006.168.07:36:29.05#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.168.07:36:29.05#ibcon#[25=AT04-07\r\n] 2006.168.07:36:29.05#ibcon#*before write, iclass 39, count 2 2006.168.07:36:29.05#ibcon#enter sib2, iclass 39, count 2 2006.168.07:36:29.05#ibcon#flushed, iclass 39, count 2 2006.168.07:36:29.05#ibcon#about to write, iclass 39, count 2 2006.168.07:36:29.05#ibcon#wrote, iclass 39, count 2 2006.168.07:36:29.05#ibcon#about to read 3, iclass 39, count 2 2006.168.07:36:29.08#ibcon#read 3, iclass 39, count 2 2006.168.07:36:29.08#ibcon#about to read 4, iclass 39, count 2 2006.168.07:36:29.08#ibcon#read 4, iclass 39, count 2 2006.168.07:36:29.08#ibcon#about to read 5, iclass 39, count 2 2006.168.07:36:29.08#ibcon#read 5, iclass 39, count 2 2006.168.07:36:29.08#ibcon#about to read 6, iclass 39, count 2 2006.168.07:36:29.08#ibcon#read 6, iclass 39, count 2 2006.168.07:36:29.08#ibcon#end of sib2, iclass 39, count 2 2006.168.07:36:29.08#ibcon#*after write, iclass 39, count 2 2006.168.07:36:29.08#ibcon#*before return 0, iclass 39, count 2 2006.168.07:36:29.08#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:36:29.08#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:36:29.08#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.168.07:36:29.08#ibcon#ireg 7 cls_cnt 0 2006.168.07:36:29.08#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:36:29.20#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:36:29.20#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:36:29.20#ibcon#enter wrdev, iclass 39, count 0 2006.168.07:36:29.20#ibcon#first serial, iclass 39, count 0 2006.168.07:36:29.20#ibcon#enter sib2, iclass 39, count 0 2006.168.07:36:29.20#ibcon#flushed, iclass 39, count 0 2006.168.07:36:29.20#ibcon#about to write, iclass 39, count 0 2006.168.07:36:29.20#ibcon#wrote, iclass 39, count 0 2006.168.07:36:29.20#ibcon#about to read 3, iclass 39, count 0 2006.168.07:36:29.22#ibcon#read 3, iclass 39, count 0 2006.168.07:36:29.22#ibcon#about to read 4, iclass 39, count 0 2006.168.07:36:29.22#ibcon#read 4, iclass 39, count 0 2006.168.07:36:29.22#ibcon#about to read 5, iclass 39, count 0 2006.168.07:36:29.22#ibcon#read 5, iclass 39, count 0 2006.168.07:36:29.22#ibcon#about to read 6, iclass 39, count 0 2006.168.07:36:29.22#ibcon#read 6, iclass 39, count 0 2006.168.07:36:29.22#ibcon#end of sib2, iclass 39, count 0 2006.168.07:36:29.22#ibcon#*mode == 0, iclass 39, count 0 2006.168.07:36:29.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.168.07:36:29.22#ibcon#[25=USB\r\n] 2006.168.07:36:29.22#ibcon#*before write, iclass 39, count 0 2006.168.07:36:29.22#ibcon#enter sib2, iclass 39, count 0 2006.168.07:36:29.22#ibcon#flushed, iclass 39, count 0 2006.168.07:36:29.22#ibcon#about to write, iclass 39, count 0 2006.168.07:36:29.22#ibcon#wrote, iclass 39, count 0 2006.168.07:36:29.22#ibcon#about to read 3, iclass 39, count 0 2006.168.07:36:29.25#ibcon#read 3, iclass 39, count 0 2006.168.07:36:29.25#ibcon#about to read 4, iclass 39, count 0 2006.168.07:36:29.25#ibcon#read 4, iclass 39, count 0 2006.168.07:36:29.25#ibcon#about to read 5, iclass 39, count 0 2006.168.07:36:29.25#ibcon#read 5, iclass 39, count 0 2006.168.07:36:29.25#ibcon#about to read 6, iclass 39, count 0 2006.168.07:36:29.25#ibcon#read 6, iclass 39, count 0 2006.168.07:36:29.25#ibcon#end of sib2, iclass 39, count 0 2006.168.07:36:29.25#ibcon#*after write, iclass 39, count 0 2006.168.07:36:29.25#ibcon#*before return 0, iclass 39, count 0 2006.168.07:36:29.25#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:36:29.25#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:36:29.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.168.07:36:29.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.168.07:36:29.25$vc4f8/valo=5,652.99 2006.168.07:36:29.25#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.168.07:36:29.25#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.168.07:36:29.25#ibcon#ireg 17 cls_cnt 0 2006.168.07:36:29.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:36:29.25#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:36:29.25#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:36:29.25#ibcon#enter wrdev, iclass 3, count 0 2006.168.07:36:29.25#ibcon#first serial, iclass 3, count 0 2006.168.07:36:29.25#ibcon#enter sib2, iclass 3, count 0 2006.168.07:36:29.25#ibcon#flushed, iclass 3, count 0 2006.168.07:36:29.25#ibcon#about to write, iclass 3, count 0 2006.168.07:36:29.25#ibcon#wrote, iclass 3, count 0 2006.168.07:36:29.25#ibcon#about to read 3, iclass 3, count 0 2006.168.07:36:29.27#ibcon#read 3, iclass 3, count 0 2006.168.07:36:29.27#ibcon#about to read 4, iclass 3, count 0 2006.168.07:36:29.27#ibcon#read 4, iclass 3, count 0 2006.168.07:36:29.27#ibcon#about to read 5, iclass 3, count 0 2006.168.07:36:29.27#ibcon#read 5, iclass 3, count 0 2006.168.07:36:29.27#ibcon#about to read 6, iclass 3, count 0 2006.168.07:36:29.27#ibcon#read 6, iclass 3, count 0 2006.168.07:36:29.27#ibcon#end of sib2, iclass 3, count 0 2006.168.07:36:29.27#ibcon#*mode == 0, iclass 3, count 0 2006.168.07:36:29.27#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.168.07:36:29.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.07:36:29.27#ibcon#*before write, iclass 3, count 0 2006.168.07:36:29.27#ibcon#enter sib2, iclass 3, count 0 2006.168.07:36:29.27#ibcon#flushed, iclass 3, count 0 2006.168.07:36:29.27#ibcon#about to write, iclass 3, count 0 2006.168.07:36:29.27#ibcon#wrote, iclass 3, count 0 2006.168.07:36:29.27#ibcon#about to read 3, iclass 3, count 0 2006.168.07:36:29.31#ibcon#read 3, iclass 3, count 0 2006.168.07:36:29.31#ibcon#about to read 4, iclass 3, count 0 2006.168.07:36:29.31#ibcon#read 4, iclass 3, count 0 2006.168.07:36:29.31#ibcon#about to read 5, iclass 3, count 0 2006.168.07:36:29.31#ibcon#read 5, iclass 3, count 0 2006.168.07:36:29.31#ibcon#about to read 6, iclass 3, count 0 2006.168.07:36:29.31#ibcon#read 6, iclass 3, count 0 2006.168.07:36:29.31#ibcon#end of sib2, iclass 3, count 0 2006.168.07:36:29.31#ibcon#*after write, iclass 3, count 0 2006.168.07:36:29.31#ibcon#*before return 0, iclass 3, count 0 2006.168.07:36:29.31#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:36:29.31#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:36:29.31#ibcon#about to clear, iclass 3 cls_cnt 0 2006.168.07:36:29.31#ibcon#cleared, iclass 3 cls_cnt 0 2006.168.07:36:29.31$vc4f8/va=5,7 2006.168.07:36:29.31#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.168.07:36:29.31#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.168.07:36:29.31#ibcon#ireg 11 cls_cnt 2 2006.168.07:36:29.31#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:36:29.37#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:36:29.37#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:36:29.37#ibcon#enter wrdev, iclass 5, count 2 2006.168.07:36:29.37#ibcon#first serial, iclass 5, count 2 2006.168.07:36:29.37#ibcon#enter sib2, iclass 5, count 2 2006.168.07:36:29.37#ibcon#flushed, iclass 5, count 2 2006.168.07:36:29.37#ibcon#about to write, iclass 5, count 2 2006.168.07:36:29.37#ibcon#wrote, iclass 5, count 2 2006.168.07:36:29.37#ibcon#about to read 3, iclass 5, count 2 2006.168.07:36:29.39#ibcon#read 3, iclass 5, count 2 2006.168.07:36:29.39#ibcon#about to read 4, iclass 5, count 2 2006.168.07:36:29.39#ibcon#read 4, iclass 5, count 2 2006.168.07:36:29.39#ibcon#about to read 5, iclass 5, count 2 2006.168.07:36:29.39#ibcon#read 5, iclass 5, count 2 2006.168.07:36:29.39#ibcon#about to read 6, iclass 5, count 2 2006.168.07:36:29.39#ibcon#read 6, iclass 5, count 2 2006.168.07:36:29.39#ibcon#end of sib2, iclass 5, count 2 2006.168.07:36:29.39#ibcon#*mode == 0, iclass 5, count 2 2006.168.07:36:29.39#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.168.07:36:29.39#ibcon#[25=AT05-07\r\n] 2006.168.07:36:29.39#ibcon#*before write, iclass 5, count 2 2006.168.07:36:29.39#ibcon#enter sib2, iclass 5, count 2 2006.168.07:36:29.39#ibcon#flushed, iclass 5, count 2 2006.168.07:36:29.39#ibcon#about to write, iclass 5, count 2 2006.168.07:36:29.39#ibcon#wrote, iclass 5, count 2 2006.168.07:36:29.39#ibcon#about to read 3, iclass 5, count 2 2006.168.07:36:29.42#ibcon#read 3, iclass 5, count 2 2006.168.07:36:29.42#ibcon#about to read 4, iclass 5, count 2 2006.168.07:36:29.42#ibcon#read 4, iclass 5, count 2 2006.168.07:36:29.42#ibcon#about to read 5, iclass 5, count 2 2006.168.07:36:29.42#ibcon#read 5, iclass 5, count 2 2006.168.07:36:29.42#ibcon#about to read 6, iclass 5, count 2 2006.168.07:36:29.42#ibcon#read 6, iclass 5, count 2 2006.168.07:36:29.42#ibcon#end of sib2, iclass 5, count 2 2006.168.07:36:29.42#ibcon#*after write, iclass 5, count 2 2006.168.07:36:29.42#ibcon#*before return 0, iclass 5, count 2 2006.168.07:36:29.42#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:36:29.42#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:36:29.42#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.168.07:36:29.42#ibcon#ireg 7 cls_cnt 0 2006.168.07:36:29.42#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:36:29.54#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:36:29.54#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:36:29.54#ibcon#enter wrdev, iclass 5, count 0 2006.168.07:36:29.54#ibcon#first serial, iclass 5, count 0 2006.168.07:36:29.54#ibcon#enter sib2, iclass 5, count 0 2006.168.07:36:29.54#ibcon#flushed, iclass 5, count 0 2006.168.07:36:29.54#ibcon#about to write, iclass 5, count 0 2006.168.07:36:29.54#ibcon#wrote, iclass 5, count 0 2006.168.07:36:29.54#ibcon#about to read 3, iclass 5, count 0 2006.168.07:36:29.56#ibcon#read 3, iclass 5, count 0 2006.168.07:36:29.56#ibcon#about to read 4, iclass 5, count 0 2006.168.07:36:29.56#ibcon#read 4, iclass 5, count 0 2006.168.07:36:29.56#ibcon#about to read 5, iclass 5, count 0 2006.168.07:36:29.56#ibcon#read 5, iclass 5, count 0 2006.168.07:36:29.56#ibcon#about to read 6, iclass 5, count 0 2006.168.07:36:29.56#ibcon#read 6, iclass 5, count 0 2006.168.07:36:29.56#ibcon#end of sib2, iclass 5, count 0 2006.168.07:36:29.56#ibcon#*mode == 0, iclass 5, count 0 2006.168.07:36:29.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.168.07:36:29.56#ibcon#[25=USB\r\n] 2006.168.07:36:29.56#ibcon#*before write, iclass 5, count 0 2006.168.07:36:29.56#ibcon#enter sib2, iclass 5, count 0 2006.168.07:36:29.56#ibcon#flushed, iclass 5, count 0 2006.168.07:36:29.56#ibcon#about to write, iclass 5, count 0 2006.168.07:36:29.56#ibcon#wrote, iclass 5, count 0 2006.168.07:36:29.56#ibcon#about to read 3, iclass 5, count 0 2006.168.07:36:29.59#ibcon#read 3, iclass 5, count 0 2006.168.07:36:29.59#ibcon#about to read 4, iclass 5, count 0 2006.168.07:36:29.59#ibcon#read 4, iclass 5, count 0 2006.168.07:36:29.59#ibcon#about to read 5, iclass 5, count 0 2006.168.07:36:29.59#ibcon#read 5, iclass 5, count 0 2006.168.07:36:29.59#ibcon#about to read 6, iclass 5, count 0 2006.168.07:36:29.59#ibcon#read 6, iclass 5, count 0 2006.168.07:36:29.59#ibcon#end of sib2, iclass 5, count 0 2006.168.07:36:29.59#ibcon#*after write, iclass 5, count 0 2006.168.07:36:29.59#ibcon#*before return 0, iclass 5, count 0 2006.168.07:36:29.59#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:36:29.59#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:36:29.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.168.07:36:29.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.168.07:36:29.59$vc4f8/valo=6,772.99 2006.168.07:36:29.59#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.168.07:36:29.59#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.168.07:36:29.59#ibcon#ireg 17 cls_cnt 0 2006.168.07:36:29.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:36:29.59#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:36:29.59#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:36:29.59#ibcon#enter wrdev, iclass 7, count 0 2006.168.07:36:29.59#ibcon#first serial, iclass 7, count 0 2006.168.07:36:29.59#ibcon#enter sib2, iclass 7, count 0 2006.168.07:36:29.59#ibcon#flushed, iclass 7, count 0 2006.168.07:36:29.59#ibcon#about to write, iclass 7, count 0 2006.168.07:36:29.59#ibcon#wrote, iclass 7, count 0 2006.168.07:36:29.59#ibcon#about to read 3, iclass 7, count 0 2006.168.07:36:29.61#ibcon#read 3, iclass 7, count 0 2006.168.07:36:29.61#ibcon#about to read 4, iclass 7, count 0 2006.168.07:36:29.61#ibcon#read 4, iclass 7, count 0 2006.168.07:36:29.61#ibcon#about to read 5, iclass 7, count 0 2006.168.07:36:29.61#ibcon#read 5, iclass 7, count 0 2006.168.07:36:29.61#ibcon#about to read 6, iclass 7, count 0 2006.168.07:36:29.61#ibcon#read 6, iclass 7, count 0 2006.168.07:36:29.61#ibcon#end of sib2, iclass 7, count 0 2006.168.07:36:29.61#ibcon#*mode == 0, iclass 7, count 0 2006.168.07:36:29.61#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.168.07:36:29.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.07:36:29.61#ibcon#*before write, iclass 7, count 0 2006.168.07:36:29.61#ibcon#enter sib2, iclass 7, count 0 2006.168.07:36:29.61#ibcon#flushed, iclass 7, count 0 2006.168.07:36:29.61#ibcon#about to write, iclass 7, count 0 2006.168.07:36:29.61#ibcon#wrote, iclass 7, count 0 2006.168.07:36:29.61#ibcon#about to read 3, iclass 7, count 0 2006.168.07:36:29.65#ibcon#read 3, iclass 7, count 0 2006.168.07:36:29.65#ibcon#about to read 4, iclass 7, count 0 2006.168.07:36:29.65#ibcon#read 4, iclass 7, count 0 2006.168.07:36:29.65#ibcon#about to read 5, iclass 7, count 0 2006.168.07:36:29.65#ibcon#read 5, iclass 7, count 0 2006.168.07:36:29.65#ibcon#about to read 6, iclass 7, count 0 2006.168.07:36:29.65#ibcon#read 6, iclass 7, count 0 2006.168.07:36:29.65#ibcon#end of sib2, iclass 7, count 0 2006.168.07:36:29.65#ibcon#*after write, iclass 7, count 0 2006.168.07:36:29.65#ibcon#*before return 0, iclass 7, count 0 2006.168.07:36:29.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:36:29.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:36:29.65#ibcon#about to clear, iclass 7 cls_cnt 0 2006.168.07:36:29.65#ibcon#cleared, iclass 7 cls_cnt 0 2006.168.07:36:29.65$vc4f8/va=6,6 2006.168.07:36:29.65#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.168.07:36:29.65#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.168.07:36:29.65#ibcon#ireg 11 cls_cnt 2 2006.168.07:36:29.65#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:36:29.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:36:29.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:36:29.71#ibcon#enter wrdev, iclass 11, count 2 2006.168.07:36:29.71#ibcon#first serial, iclass 11, count 2 2006.168.07:36:29.71#ibcon#enter sib2, iclass 11, count 2 2006.168.07:36:29.71#ibcon#flushed, iclass 11, count 2 2006.168.07:36:29.71#ibcon#about to write, iclass 11, count 2 2006.168.07:36:29.71#ibcon#wrote, iclass 11, count 2 2006.168.07:36:29.71#ibcon#about to read 3, iclass 11, count 2 2006.168.07:36:29.73#ibcon#read 3, iclass 11, count 2 2006.168.07:36:29.73#ibcon#about to read 4, iclass 11, count 2 2006.168.07:36:29.73#ibcon#read 4, iclass 11, count 2 2006.168.07:36:29.73#ibcon#about to read 5, iclass 11, count 2 2006.168.07:36:29.73#ibcon#read 5, iclass 11, count 2 2006.168.07:36:29.73#ibcon#about to read 6, iclass 11, count 2 2006.168.07:36:29.73#ibcon#read 6, iclass 11, count 2 2006.168.07:36:29.73#ibcon#end of sib2, iclass 11, count 2 2006.168.07:36:29.73#ibcon#*mode == 0, iclass 11, count 2 2006.168.07:36:29.73#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.168.07:36:29.73#ibcon#[25=AT06-06\r\n] 2006.168.07:36:29.73#ibcon#*before write, iclass 11, count 2 2006.168.07:36:29.73#ibcon#enter sib2, iclass 11, count 2 2006.168.07:36:29.73#ibcon#flushed, iclass 11, count 2 2006.168.07:36:29.73#ibcon#about to write, iclass 11, count 2 2006.168.07:36:29.73#ibcon#wrote, iclass 11, count 2 2006.168.07:36:29.73#ibcon#about to read 3, iclass 11, count 2 2006.168.07:36:29.76#ibcon#read 3, iclass 11, count 2 2006.168.07:36:29.76#ibcon#about to read 4, iclass 11, count 2 2006.168.07:36:29.76#ibcon#read 4, iclass 11, count 2 2006.168.07:36:29.76#ibcon#about to read 5, iclass 11, count 2 2006.168.07:36:29.76#ibcon#read 5, iclass 11, count 2 2006.168.07:36:29.76#ibcon#about to read 6, iclass 11, count 2 2006.168.07:36:29.76#ibcon#read 6, iclass 11, count 2 2006.168.07:36:29.76#ibcon#end of sib2, iclass 11, count 2 2006.168.07:36:29.76#ibcon#*after write, iclass 11, count 2 2006.168.07:36:29.76#ibcon#*before return 0, iclass 11, count 2 2006.168.07:36:29.76#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:36:29.76#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:36:29.76#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.168.07:36:29.76#ibcon#ireg 7 cls_cnt 0 2006.168.07:36:29.76#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:36:29.88#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:36:29.88#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:36:29.88#ibcon#enter wrdev, iclass 11, count 0 2006.168.07:36:29.88#ibcon#first serial, iclass 11, count 0 2006.168.07:36:29.88#ibcon#enter sib2, iclass 11, count 0 2006.168.07:36:29.88#ibcon#flushed, iclass 11, count 0 2006.168.07:36:29.88#ibcon#about to write, iclass 11, count 0 2006.168.07:36:29.88#ibcon#wrote, iclass 11, count 0 2006.168.07:36:29.88#ibcon#about to read 3, iclass 11, count 0 2006.168.07:36:29.90#ibcon#read 3, iclass 11, count 0 2006.168.07:36:29.90#ibcon#about to read 4, iclass 11, count 0 2006.168.07:36:29.90#ibcon#read 4, iclass 11, count 0 2006.168.07:36:29.90#ibcon#about to read 5, iclass 11, count 0 2006.168.07:36:29.90#ibcon#read 5, iclass 11, count 0 2006.168.07:36:29.90#ibcon#about to read 6, iclass 11, count 0 2006.168.07:36:29.90#ibcon#read 6, iclass 11, count 0 2006.168.07:36:29.90#ibcon#end of sib2, iclass 11, count 0 2006.168.07:36:29.90#ibcon#*mode == 0, iclass 11, count 0 2006.168.07:36:29.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.168.07:36:29.90#ibcon#[25=USB\r\n] 2006.168.07:36:29.90#ibcon#*before write, iclass 11, count 0 2006.168.07:36:29.90#ibcon#enter sib2, iclass 11, count 0 2006.168.07:36:29.90#ibcon#flushed, iclass 11, count 0 2006.168.07:36:29.90#ibcon#about to write, iclass 11, count 0 2006.168.07:36:29.90#ibcon#wrote, iclass 11, count 0 2006.168.07:36:29.90#ibcon#about to read 3, iclass 11, count 0 2006.168.07:36:29.93#ibcon#read 3, iclass 11, count 0 2006.168.07:36:29.93#ibcon#about to read 4, iclass 11, count 0 2006.168.07:36:29.93#ibcon#read 4, iclass 11, count 0 2006.168.07:36:29.93#ibcon#about to read 5, iclass 11, count 0 2006.168.07:36:29.93#ibcon#read 5, iclass 11, count 0 2006.168.07:36:29.93#ibcon#about to read 6, iclass 11, count 0 2006.168.07:36:29.93#ibcon#read 6, iclass 11, count 0 2006.168.07:36:29.93#ibcon#end of sib2, iclass 11, count 0 2006.168.07:36:29.93#ibcon#*after write, iclass 11, count 0 2006.168.07:36:29.93#ibcon#*before return 0, iclass 11, count 0 2006.168.07:36:29.93#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:36:29.93#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:36:29.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.168.07:36:29.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.168.07:36:29.93$vc4f8/valo=7,832.99 2006.168.07:36:29.93#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.168.07:36:29.93#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.168.07:36:29.93#ibcon#ireg 17 cls_cnt 0 2006.168.07:36:29.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:36:29.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:36:29.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:36:29.93#ibcon#enter wrdev, iclass 13, count 0 2006.168.07:36:29.93#ibcon#first serial, iclass 13, count 0 2006.168.07:36:29.93#ibcon#enter sib2, iclass 13, count 0 2006.168.07:36:29.93#ibcon#flushed, iclass 13, count 0 2006.168.07:36:29.93#ibcon#about to write, iclass 13, count 0 2006.168.07:36:29.93#ibcon#wrote, iclass 13, count 0 2006.168.07:36:29.93#ibcon#about to read 3, iclass 13, count 0 2006.168.07:36:29.95#ibcon#read 3, iclass 13, count 0 2006.168.07:36:29.95#ibcon#about to read 4, iclass 13, count 0 2006.168.07:36:29.95#ibcon#read 4, iclass 13, count 0 2006.168.07:36:29.95#ibcon#about to read 5, iclass 13, count 0 2006.168.07:36:29.95#ibcon#read 5, iclass 13, count 0 2006.168.07:36:29.95#ibcon#about to read 6, iclass 13, count 0 2006.168.07:36:29.95#ibcon#read 6, iclass 13, count 0 2006.168.07:36:29.95#ibcon#end of sib2, iclass 13, count 0 2006.168.07:36:29.95#ibcon#*mode == 0, iclass 13, count 0 2006.168.07:36:29.95#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.168.07:36:29.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.07:36:29.95#ibcon#*before write, iclass 13, count 0 2006.168.07:36:29.95#ibcon#enter sib2, iclass 13, count 0 2006.168.07:36:29.95#ibcon#flushed, iclass 13, count 0 2006.168.07:36:29.95#ibcon#about to write, iclass 13, count 0 2006.168.07:36:29.95#ibcon#wrote, iclass 13, count 0 2006.168.07:36:29.95#ibcon#about to read 3, iclass 13, count 0 2006.168.07:36:29.99#ibcon#read 3, iclass 13, count 0 2006.168.07:36:29.99#ibcon#about to read 4, iclass 13, count 0 2006.168.07:36:29.99#ibcon#read 4, iclass 13, count 0 2006.168.07:36:29.99#ibcon#about to read 5, iclass 13, count 0 2006.168.07:36:29.99#ibcon#read 5, iclass 13, count 0 2006.168.07:36:29.99#ibcon#about to read 6, iclass 13, count 0 2006.168.07:36:29.99#ibcon#read 6, iclass 13, count 0 2006.168.07:36:29.99#ibcon#end of sib2, iclass 13, count 0 2006.168.07:36:29.99#ibcon#*after write, iclass 13, count 0 2006.168.07:36:29.99#ibcon#*before return 0, iclass 13, count 0 2006.168.07:36:29.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:36:29.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:36:29.99#ibcon#about to clear, iclass 13 cls_cnt 0 2006.168.07:36:29.99#ibcon#cleared, iclass 13 cls_cnt 0 2006.168.07:36:29.99$vc4f8/va=7,6 2006.168.07:36:29.99#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.168.07:36:29.99#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.168.07:36:29.99#ibcon#ireg 11 cls_cnt 2 2006.168.07:36:29.99#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.168.07:36:30.05#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.168.07:36:30.05#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.168.07:36:30.05#ibcon#enter wrdev, iclass 15, count 2 2006.168.07:36:30.05#ibcon#first serial, iclass 15, count 2 2006.168.07:36:30.05#ibcon#enter sib2, iclass 15, count 2 2006.168.07:36:30.05#ibcon#flushed, iclass 15, count 2 2006.168.07:36:30.05#ibcon#about to write, iclass 15, count 2 2006.168.07:36:30.05#ibcon#wrote, iclass 15, count 2 2006.168.07:36:30.05#ibcon#about to read 3, iclass 15, count 2 2006.168.07:36:30.07#ibcon#read 3, iclass 15, count 2 2006.168.07:36:30.07#ibcon#about to read 4, iclass 15, count 2 2006.168.07:36:30.07#ibcon#read 4, iclass 15, count 2 2006.168.07:36:30.07#ibcon#about to read 5, iclass 15, count 2 2006.168.07:36:30.07#ibcon#read 5, iclass 15, count 2 2006.168.07:36:30.07#ibcon#about to read 6, iclass 15, count 2 2006.168.07:36:30.07#ibcon#read 6, iclass 15, count 2 2006.168.07:36:30.07#ibcon#end of sib2, iclass 15, count 2 2006.168.07:36:30.07#ibcon#*mode == 0, iclass 15, count 2 2006.168.07:36:30.07#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.168.07:36:30.07#ibcon#[25=AT07-06\r\n] 2006.168.07:36:30.07#ibcon#*before write, iclass 15, count 2 2006.168.07:36:30.07#ibcon#enter sib2, iclass 15, count 2 2006.168.07:36:30.07#ibcon#flushed, iclass 15, count 2 2006.168.07:36:30.07#ibcon#about to write, iclass 15, count 2 2006.168.07:36:30.07#ibcon#wrote, iclass 15, count 2 2006.168.07:36:30.07#ibcon#about to read 3, iclass 15, count 2 2006.168.07:36:30.10#ibcon#read 3, iclass 15, count 2 2006.168.07:36:30.10#ibcon#about to read 4, iclass 15, count 2 2006.168.07:36:30.10#ibcon#read 4, iclass 15, count 2 2006.168.07:36:30.10#ibcon#about to read 5, iclass 15, count 2 2006.168.07:36:30.10#ibcon#read 5, iclass 15, count 2 2006.168.07:36:30.10#ibcon#about to read 6, iclass 15, count 2 2006.168.07:36:30.10#ibcon#read 6, iclass 15, count 2 2006.168.07:36:30.10#ibcon#end of sib2, iclass 15, count 2 2006.168.07:36:30.10#ibcon#*after write, iclass 15, count 2 2006.168.07:36:30.10#ibcon#*before return 0, iclass 15, count 2 2006.168.07:36:30.10#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.168.07:36:30.10#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.168.07:36:30.10#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.168.07:36:30.10#ibcon#ireg 7 cls_cnt 0 2006.168.07:36:30.10#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.168.07:36:30.22#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.168.07:36:30.22#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.168.07:36:30.22#ibcon#enter wrdev, iclass 15, count 0 2006.168.07:36:30.22#ibcon#first serial, iclass 15, count 0 2006.168.07:36:30.22#ibcon#enter sib2, iclass 15, count 0 2006.168.07:36:30.22#ibcon#flushed, iclass 15, count 0 2006.168.07:36:30.22#ibcon#about to write, iclass 15, count 0 2006.168.07:36:30.22#ibcon#wrote, iclass 15, count 0 2006.168.07:36:30.22#ibcon#about to read 3, iclass 15, count 0 2006.168.07:36:30.24#ibcon#read 3, iclass 15, count 0 2006.168.07:36:30.24#ibcon#about to read 4, iclass 15, count 0 2006.168.07:36:30.24#ibcon#read 4, iclass 15, count 0 2006.168.07:36:30.24#ibcon#about to read 5, iclass 15, count 0 2006.168.07:36:30.24#ibcon#read 5, iclass 15, count 0 2006.168.07:36:30.24#ibcon#about to read 6, iclass 15, count 0 2006.168.07:36:30.24#ibcon#read 6, iclass 15, count 0 2006.168.07:36:30.24#ibcon#end of sib2, iclass 15, count 0 2006.168.07:36:30.24#ibcon#*mode == 0, iclass 15, count 0 2006.168.07:36:30.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.168.07:36:30.24#ibcon#[25=USB\r\n] 2006.168.07:36:30.24#ibcon#*before write, iclass 15, count 0 2006.168.07:36:30.24#ibcon#enter sib2, iclass 15, count 0 2006.168.07:36:30.24#ibcon#flushed, iclass 15, count 0 2006.168.07:36:30.24#ibcon#about to write, iclass 15, count 0 2006.168.07:36:30.24#ibcon#wrote, iclass 15, count 0 2006.168.07:36:30.24#ibcon#about to read 3, iclass 15, count 0 2006.168.07:36:30.27#ibcon#read 3, iclass 15, count 0 2006.168.07:36:30.27#ibcon#about to read 4, iclass 15, count 0 2006.168.07:36:30.27#ibcon#read 4, iclass 15, count 0 2006.168.07:36:30.27#ibcon#about to read 5, iclass 15, count 0 2006.168.07:36:30.27#ibcon#read 5, iclass 15, count 0 2006.168.07:36:30.27#ibcon#about to read 6, iclass 15, count 0 2006.168.07:36:30.27#ibcon#read 6, iclass 15, count 0 2006.168.07:36:30.27#ibcon#end of sib2, iclass 15, count 0 2006.168.07:36:30.27#ibcon#*after write, iclass 15, count 0 2006.168.07:36:30.27#ibcon#*before return 0, iclass 15, count 0 2006.168.07:36:30.27#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.168.07:36:30.27#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.168.07:36:30.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.168.07:36:30.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.168.07:36:30.27$vc4f8/valo=8,852.99 2006.168.07:36:30.27#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.168.07:36:30.27#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.168.07:36:30.27#ibcon#ireg 17 cls_cnt 0 2006.168.07:36:30.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:36:30.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:36:30.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:36:30.27#ibcon#enter wrdev, iclass 17, count 0 2006.168.07:36:30.27#ibcon#first serial, iclass 17, count 0 2006.168.07:36:30.27#ibcon#enter sib2, iclass 17, count 0 2006.168.07:36:30.27#ibcon#flushed, iclass 17, count 0 2006.168.07:36:30.27#ibcon#about to write, iclass 17, count 0 2006.168.07:36:30.27#ibcon#wrote, iclass 17, count 0 2006.168.07:36:30.27#ibcon#about to read 3, iclass 17, count 0 2006.168.07:36:30.29#ibcon#read 3, iclass 17, count 0 2006.168.07:36:30.29#ibcon#about to read 4, iclass 17, count 0 2006.168.07:36:30.29#ibcon#read 4, iclass 17, count 0 2006.168.07:36:30.29#ibcon#about to read 5, iclass 17, count 0 2006.168.07:36:30.29#ibcon#read 5, iclass 17, count 0 2006.168.07:36:30.29#ibcon#about to read 6, iclass 17, count 0 2006.168.07:36:30.29#ibcon#read 6, iclass 17, count 0 2006.168.07:36:30.29#ibcon#end of sib2, iclass 17, count 0 2006.168.07:36:30.29#ibcon#*mode == 0, iclass 17, count 0 2006.168.07:36:30.29#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.168.07:36:30.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.07:36:30.29#ibcon#*before write, iclass 17, count 0 2006.168.07:36:30.29#ibcon#enter sib2, iclass 17, count 0 2006.168.07:36:30.29#ibcon#flushed, iclass 17, count 0 2006.168.07:36:30.29#ibcon#about to write, iclass 17, count 0 2006.168.07:36:30.29#ibcon#wrote, iclass 17, count 0 2006.168.07:36:30.29#ibcon#about to read 3, iclass 17, count 0 2006.168.07:36:30.33#ibcon#read 3, iclass 17, count 0 2006.168.07:36:30.33#ibcon#about to read 4, iclass 17, count 0 2006.168.07:36:30.33#ibcon#read 4, iclass 17, count 0 2006.168.07:36:30.33#ibcon#about to read 5, iclass 17, count 0 2006.168.07:36:30.33#ibcon#read 5, iclass 17, count 0 2006.168.07:36:30.33#ibcon#about to read 6, iclass 17, count 0 2006.168.07:36:30.33#ibcon#read 6, iclass 17, count 0 2006.168.07:36:30.33#ibcon#end of sib2, iclass 17, count 0 2006.168.07:36:30.33#ibcon#*after write, iclass 17, count 0 2006.168.07:36:30.33#ibcon#*before return 0, iclass 17, count 0 2006.168.07:36:30.33#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:36:30.33#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:36:30.33#ibcon#about to clear, iclass 17 cls_cnt 0 2006.168.07:36:30.33#ibcon#cleared, iclass 17 cls_cnt 0 2006.168.07:36:30.33$vc4f8/va=8,7 2006.168.07:36:30.33#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.168.07:36:30.33#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.168.07:36:30.33#ibcon#ireg 11 cls_cnt 2 2006.168.07:36:30.33#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.168.07:36:30.39#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.168.07:36:30.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.168.07:36:30.39#ibcon#enter wrdev, iclass 19, count 2 2006.168.07:36:30.39#ibcon#first serial, iclass 19, count 2 2006.168.07:36:30.39#ibcon#enter sib2, iclass 19, count 2 2006.168.07:36:30.39#ibcon#flushed, iclass 19, count 2 2006.168.07:36:30.39#ibcon#about to write, iclass 19, count 2 2006.168.07:36:30.39#ibcon#wrote, iclass 19, count 2 2006.168.07:36:30.39#ibcon#about to read 3, iclass 19, count 2 2006.168.07:36:30.41#ibcon#read 3, iclass 19, count 2 2006.168.07:36:30.41#ibcon#about to read 4, iclass 19, count 2 2006.168.07:36:30.41#ibcon#read 4, iclass 19, count 2 2006.168.07:36:30.41#ibcon#about to read 5, iclass 19, count 2 2006.168.07:36:30.41#ibcon#read 5, iclass 19, count 2 2006.168.07:36:30.41#ibcon#about to read 6, iclass 19, count 2 2006.168.07:36:30.41#ibcon#read 6, iclass 19, count 2 2006.168.07:36:30.41#ibcon#end of sib2, iclass 19, count 2 2006.168.07:36:30.41#ibcon#*mode == 0, iclass 19, count 2 2006.168.07:36:30.41#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.168.07:36:30.41#ibcon#[25=AT08-07\r\n] 2006.168.07:36:30.41#ibcon#*before write, iclass 19, count 2 2006.168.07:36:30.41#ibcon#enter sib2, iclass 19, count 2 2006.168.07:36:30.41#ibcon#flushed, iclass 19, count 2 2006.168.07:36:30.41#ibcon#about to write, iclass 19, count 2 2006.168.07:36:30.41#ibcon#wrote, iclass 19, count 2 2006.168.07:36:30.41#ibcon#about to read 3, iclass 19, count 2 2006.168.07:36:30.44#ibcon#read 3, iclass 19, count 2 2006.168.07:36:30.44#ibcon#about to read 4, iclass 19, count 2 2006.168.07:36:30.44#ibcon#read 4, iclass 19, count 2 2006.168.07:36:30.44#ibcon#about to read 5, iclass 19, count 2 2006.168.07:36:30.44#ibcon#read 5, iclass 19, count 2 2006.168.07:36:30.44#ibcon#about to read 6, iclass 19, count 2 2006.168.07:36:30.44#ibcon#read 6, iclass 19, count 2 2006.168.07:36:30.44#ibcon#end of sib2, iclass 19, count 2 2006.168.07:36:30.44#ibcon#*after write, iclass 19, count 2 2006.168.07:36:30.44#ibcon#*before return 0, iclass 19, count 2 2006.168.07:36:30.44#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.168.07:36:30.44#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.168.07:36:30.44#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.168.07:36:30.44#ibcon#ireg 7 cls_cnt 0 2006.168.07:36:30.44#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.168.07:36:30.56#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.168.07:36:30.56#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.168.07:36:30.56#ibcon#enter wrdev, iclass 19, count 0 2006.168.07:36:30.56#ibcon#first serial, iclass 19, count 0 2006.168.07:36:30.56#ibcon#enter sib2, iclass 19, count 0 2006.168.07:36:30.56#ibcon#flushed, iclass 19, count 0 2006.168.07:36:30.56#ibcon#about to write, iclass 19, count 0 2006.168.07:36:30.56#ibcon#wrote, iclass 19, count 0 2006.168.07:36:30.56#ibcon#about to read 3, iclass 19, count 0 2006.168.07:36:30.58#ibcon#read 3, iclass 19, count 0 2006.168.07:36:30.58#ibcon#about to read 4, iclass 19, count 0 2006.168.07:36:30.58#ibcon#read 4, iclass 19, count 0 2006.168.07:36:30.58#ibcon#about to read 5, iclass 19, count 0 2006.168.07:36:30.58#ibcon#read 5, iclass 19, count 0 2006.168.07:36:30.58#ibcon#about to read 6, iclass 19, count 0 2006.168.07:36:30.58#ibcon#read 6, iclass 19, count 0 2006.168.07:36:30.58#ibcon#end of sib2, iclass 19, count 0 2006.168.07:36:30.58#ibcon#*mode == 0, iclass 19, count 0 2006.168.07:36:30.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.168.07:36:30.58#ibcon#[25=USB\r\n] 2006.168.07:36:30.58#ibcon#*before write, iclass 19, count 0 2006.168.07:36:30.58#ibcon#enter sib2, iclass 19, count 0 2006.168.07:36:30.58#ibcon#flushed, iclass 19, count 0 2006.168.07:36:30.58#ibcon#about to write, iclass 19, count 0 2006.168.07:36:30.58#ibcon#wrote, iclass 19, count 0 2006.168.07:36:30.58#ibcon#about to read 3, iclass 19, count 0 2006.168.07:36:30.61#ibcon#read 3, iclass 19, count 0 2006.168.07:36:30.61#ibcon#about to read 4, iclass 19, count 0 2006.168.07:36:30.61#ibcon#read 4, iclass 19, count 0 2006.168.07:36:30.61#ibcon#about to read 5, iclass 19, count 0 2006.168.07:36:30.61#ibcon#read 5, iclass 19, count 0 2006.168.07:36:30.61#ibcon#about to read 6, iclass 19, count 0 2006.168.07:36:30.61#ibcon#read 6, iclass 19, count 0 2006.168.07:36:30.61#ibcon#end of sib2, iclass 19, count 0 2006.168.07:36:30.61#ibcon#*after write, iclass 19, count 0 2006.168.07:36:30.61#ibcon#*before return 0, iclass 19, count 0 2006.168.07:36:30.61#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.168.07:36:30.61#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.168.07:36:30.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.168.07:36:30.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.168.07:36:30.61$vc4f8/vblo=1,632.99 2006.168.07:36:30.61#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.168.07:36:30.61#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.168.07:36:30.61#ibcon#ireg 17 cls_cnt 0 2006.168.07:36:30.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.168.07:36:30.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.168.07:36:30.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.168.07:36:30.61#ibcon#enter wrdev, iclass 21, count 0 2006.168.07:36:30.61#ibcon#first serial, iclass 21, count 0 2006.168.07:36:30.61#ibcon#enter sib2, iclass 21, count 0 2006.168.07:36:30.61#ibcon#flushed, iclass 21, count 0 2006.168.07:36:30.61#ibcon#about to write, iclass 21, count 0 2006.168.07:36:30.61#ibcon#wrote, iclass 21, count 0 2006.168.07:36:30.61#ibcon#about to read 3, iclass 21, count 0 2006.168.07:36:30.63#ibcon#read 3, iclass 21, count 0 2006.168.07:36:30.63#ibcon#about to read 4, iclass 21, count 0 2006.168.07:36:30.63#ibcon#read 4, iclass 21, count 0 2006.168.07:36:30.63#ibcon#about to read 5, iclass 21, count 0 2006.168.07:36:30.63#ibcon#read 5, iclass 21, count 0 2006.168.07:36:30.63#ibcon#about to read 6, iclass 21, count 0 2006.168.07:36:30.63#ibcon#read 6, iclass 21, count 0 2006.168.07:36:30.63#ibcon#end of sib2, iclass 21, count 0 2006.168.07:36:30.63#ibcon#*mode == 0, iclass 21, count 0 2006.168.07:36:30.63#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.168.07:36:30.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.07:36:30.63#ibcon#*before write, iclass 21, count 0 2006.168.07:36:30.63#ibcon#enter sib2, iclass 21, count 0 2006.168.07:36:30.63#ibcon#flushed, iclass 21, count 0 2006.168.07:36:30.63#ibcon#about to write, iclass 21, count 0 2006.168.07:36:30.63#ibcon#wrote, iclass 21, count 0 2006.168.07:36:30.63#ibcon#about to read 3, iclass 21, count 0 2006.168.07:36:30.67#ibcon#read 3, iclass 21, count 0 2006.168.07:36:30.67#ibcon#about to read 4, iclass 21, count 0 2006.168.07:36:30.67#ibcon#read 4, iclass 21, count 0 2006.168.07:36:30.67#ibcon#about to read 5, iclass 21, count 0 2006.168.07:36:30.67#ibcon#read 5, iclass 21, count 0 2006.168.07:36:30.67#ibcon#about to read 6, iclass 21, count 0 2006.168.07:36:30.67#ibcon#read 6, iclass 21, count 0 2006.168.07:36:30.67#ibcon#end of sib2, iclass 21, count 0 2006.168.07:36:30.67#ibcon#*after write, iclass 21, count 0 2006.168.07:36:30.67#ibcon#*before return 0, iclass 21, count 0 2006.168.07:36:30.67#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.168.07:36:30.67#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.168.07:36:30.67#ibcon#about to clear, iclass 21 cls_cnt 0 2006.168.07:36:30.67#ibcon#cleared, iclass 21 cls_cnt 0 2006.168.07:36:30.67$vc4f8/vb=1,4 2006.168.07:36:30.67#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.168.07:36:30.67#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.168.07:36:30.67#ibcon#ireg 11 cls_cnt 2 2006.168.07:36:30.67#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.168.07:36:30.67#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.168.07:36:30.67#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.168.07:36:30.67#ibcon#enter wrdev, iclass 23, count 2 2006.168.07:36:30.67#ibcon#first serial, iclass 23, count 2 2006.168.07:36:30.67#ibcon#enter sib2, iclass 23, count 2 2006.168.07:36:30.67#ibcon#flushed, iclass 23, count 2 2006.168.07:36:30.67#ibcon#about to write, iclass 23, count 2 2006.168.07:36:30.67#ibcon#wrote, iclass 23, count 2 2006.168.07:36:30.67#ibcon#about to read 3, iclass 23, count 2 2006.168.07:36:30.69#ibcon#read 3, iclass 23, count 2 2006.168.07:36:30.69#ibcon#about to read 4, iclass 23, count 2 2006.168.07:36:30.69#ibcon#read 4, iclass 23, count 2 2006.168.07:36:30.69#ibcon#about to read 5, iclass 23, count 2 2006.168.07:36:30.69#ibcon#read 5, iclass 23, count 2 2006.168.07:36:30.69#ibcon#about to read 6, iclass 23, count 2 2006.168.07:36:30.69#ibcon#read 6, iclass 23, count 2 2006.168.07:36:30.69#ibcon#end of sib2, iclass 23, count 2 2006.168.07:36:30.69#ibcon#*mode == 0, iclass 23, count 2 2006.168.07:36:30.69#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.168.07:36:30.69#ibcon#[27=AT01-04\r\n] 2006.168.07:36:30.69#ibcon#*before write, iclass 23, count 2 2006.168.07:36:30.69#ibcon#enter sib2, iclass 23, count 2 2006.168.07:36:30.69#ibcon#flushed, iclass 23, count 2 2006.168.07:36:30.69#ibcon#about to write, iclass 23, count 2 2006.168.07:36:30.69#ibcon#wrote, iclass 23, count 2 2006.168.07:36:30.69#ibcon#about to read 3, iclass 23, count 2 2006.168.07:36:30.72#ibcon#read 3, iclass 23, count 2 2006.168.07:36:30.72#ibcon#about to read 4, iclass 23, count 2 2006.168.07:36:30.72#ibcon#read 4, iclass 23, count 2 2006.168.07:36:30.72#ibcon#about to read 5, iclass 23, count 2 2006.168.07:36:30.72#ibcon#read 5, iclass 23, count 2 2006.168.07:36:30.72#ibcon#about to read 6, iclass 23, count 2 2006.168.07:36:30.72#ibcon#read 6, iclass 23, count 2 2006.168.07:36:30.72#ibcon#end of sib2, iclass 23, count 2 2006.168.07:36:30.72#ibcon#*after write, iclass 23, count 2 2006.168.07:36:30.72#ibcon#*before return 0, iclass 23, count 2 2006.168.07:36:30.72#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.168.07:36:30.72#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.168.07:36:30.72#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.168.07:36:30.72#ibcon#ireg 7 cls_cnt 0 2006.168.07:36:30.72#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.168.07:36:30.77#abcon#<5=/08 1.7 5.8 27.85 731004.6\r\n> 2006.168.07:36:30.79#abcon#{5=INTERFACE CLEAR} 2006.168.07:36:30.84#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.168.07:36:30.84#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.168.07:36:30.84#ibcon#enter wrdev, iclass 23, count 0 2006.168.07:36:30.84#ibcon#first serial, iclass 23, count 0 2006.168.07:36:30.84#ibcon#enter sib2, iclass 23, count 0 2006.168.07:36:30.84#ibcon#flushed, iclass 23, count 0 2006.168.07:36:30.84#ibcon#about to write, iclass 23, count 0 2006.168.07:36:30.84#ibcon#wrote, iclass 23, count 0 2006.168.07:36:30.84#ibcon#about to read 3, iclass 23, count 0 2006.168.07:36:30.85#abcon#[5=S1D000X0/0*\r\n] 2006.168.07:36:30.86#ibcon#read 3, iclass 23, count 0 2006.168.07:36:30.86#ibcon#about to read 4, iclass 23, count 0 2006.168.07:36:30.86#ibcon#read 4, iclass 23, count 0 2006.168.07:36:30.86#ibcon#about to read 5, iclass 23, count 0 2006.168.07:36:30.86#ibcon#read 5, iclass 23, count 0 2006.168.07:36:30.86#ibcon#about to read 6, iclass 23, count 0 2006.168.07:36:30.86#ibcon#read 6, iclass 23, count 0 2006.168.07:36:30.86#ibcon#end of sib2, iclass 23, count 0 2006.168.07:36:30.86#ibcon#*mode == 0, iclass 23, count 0 2006.168.07:36:30.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.168.07:36:30.86#ibcon#[27=USB\r\n] 2006.168.07:36:30.86#ibcon#*before write, iclass 23, count 0 2006.168.07:36:30.86#ibcon#enter sib2, iclass 23, count 0 2006.168.07:36:30.86#ibcon#flushed, iclass 23, count 0 2006.168.07:36:30.86#ibcon#about to write, iclass 23, count 0 2006.168.07:36:30.86#ibcon#wrote, iclass 23, count 0 2006.168.07:36:30.86#ibcon#about to read 3, iclass 23, count 0 2006.168.07:36:30.89#ibcon#read 3, iclass 23, count 0 2006.168.07:36:30.89#ibcon#about to read 4, iclass 23, count 0 2006.168.07:36:30.89#ibcon#read 4, iclass 23, count 0 2006.168.07:36:30.89#ibcon#about to read 5, iclass 23, count 0 2006.168.07:36:30.89#ibcon#read 5, iclass 23, count 0 2006.168.07:36:30.89#ibcon#about to read 6, iclass 23, count 0 2006.168.07:36:30.89#ibcon#read 6, iclass 23, count 0 2006.168.07:36:30.89#ibcon#end of sib2, iclass 23, count 0 2006.168.07:36:30.89#ibcon#*after write, iclass 23, count 0 2006.168.07:36:30.89#ibcon#*before return 0, iclass 23, count 0 2006.168.07:36:30.89#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.168.07:36:30.89#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.168.07:36:30.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.168.07:36:30.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.168.07:36:30.89$vc4f8/vblo=2,640.99 2006.168.07:36:30.89#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.168.07:36:30.89#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.168.07:36:30.89#ibcon#ireg 17 cls_cnt 0 2006.168.07:36:30.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.168.07:36:30.89#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.168.07:36:30.89#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.168.07:36:30.89#ibcon#enter wrdev, iclass 29, count 0 2006.168.07:36:30.89#ibcon#first serial, iclass 29, count 0 2006.168.07:36:30.89#ibcon#enter sib2, iclass 29, count 0 2006.168.07:36:30.89#ibcon#flushed, iclass 29, count 0 2006.168.07:36:30.89#ibcon#about to write, iclass 29, count 0 2006.168.07:36:30.89#ibcon#wrote, iclass 29, count 0 2006.168.07:36:30.89#ibcon#about to read 3, iclass 29, count 0 2006.168.07:36:30.91#ibcon#read 3, iclass 29, count 0 2006.168.07:36:30.91#ibcon#about to read 4, iclass 29, count 0 2006.168.07:36:30.91#ibcon#read 4, iclass 29, count 0 2006.168.07:36:30.91#ibcon#about to read 5, iclass 29, count 0 2006.168.07:36:30.91#ibcon#read 5, iclass 29, count 0 2006.168.07:36:30.91#ibcon#about to read 6, iclass 29, count 0 2006.168.07:36:30.91#ibcon#read 6, iclass 29, count 0 2006.168.07:36:30.91#ibcon#end of sib2, iclass 29, count 0 2006.168.07:36:30.91#ibcon#*mode == 0, iclass 29, count 0 2006.168.07:36:30.91#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.168.07:36:30.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.07:36:30.91#ibcon#*before write, iclass 29, count 0 2006.168.07:36:30.91#ibcon#enter sib2, iclass 29, count 0 2006.168.07:36:30.91#ibcon#flushed, iclass 29, count 0 2006.168.07:36:30.91#ibcon#about to write, iclass 29, count 0 2006.168.07:36:30.91#ibcon#wrote, iclass 29, count 0 2006.168.07:36:30.91#ibcon#about to read 3, iclass 29, count 0 2006.168.07:36:30.95#ibcon#read 3, iclass 29, count 0 2006.168.07:36:30.95#ibcon#about to read 4, iclass 29, count 0 2006.168.07:36:30.95#ibcon#read 4, iclass 29, count 0 2006.168.07:36:30.95#ibcon#about to read 5, iclass 29, count 0 2006.168.07:36:30.95#ibcon#read 5, iclass 29, count 0 2006.168.07:36:30.95#ibcon#about to read 6, iclass 29, count 0 2006.168.07:36:30.95#ibcon#read 6, iclass 29, count 0 2006.168.07:36:30.95#ibcon#end of sib2, iclass 29, count 0 2006.168.07:36:30.95#ibcon#*after write, iclass 29, count 0 2006.168.07:36:30.95#ibcon#*before return 0, iclass 29, count 0 2006.168.07:36:30.95#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.168.07:36:30.95#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.168.07:36:30.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.168.07:36:30.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.168.07:36:30.95$vc4f8/vb=2,4 2006.168.07:36:30.95#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.168.07:36:30.95#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.168.07:36:30.95#ibcon#ireg 11 cls_cnt 2 2006.168.07:36:30.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.168.07:36:31.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.168.07:36:31.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.168.07:36:31.01#ibcon#enter wrdev, iclass 31, count 2 2006.168.07:36:31.01#ibcon#first serial, iclass 31, count 2 2006.168.07:36:31.01#ibcon#enter sib2, iclass 31, count 2 2006.168.07:36:31.01#ibcon#flushed, iclass 31, count 2 2006.168.07:36:31.01#ibcon#about to write, iclass 31, count 2 2006.168.07:36:31.01#ibcon#wrote, iclass 31, count 2 2006.168.07:36:31.01#ibcon#about to read 3, iclass 31, count 2 2006.168.07:36:31.03#ibcon#read 3, iclass 31, count 2 2006.168.07:36:31.03#ibcon#about to read 4, iclass 31, count 2 2006.168.07:36:31.03#ibcon#read 4, iclass 31, count 2 2006.168.07:36:31.03#ibcon#about to read 5, iclass 31, count 2 2006.168.07:36:31.03#ibcon#read 5, iclass 31, count 2 2006.168.07:36:31.03#ibcon#about to read 6, iclass 31, count 2 2006.168.07:36:31.03#ibcon#read 6, iclass 31, count 2 2006.168.07:36:31.03#ibcon#end of sib2, iclass 31, count 2 2006.168.07:36:31.03#ibcon#*mode == 0, iclass 31, count 2 2006.168.07:36:31.03#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.168.07:36:31.03#ibcon#[27=AT02-04\r\n] 2006.168.07:36:31.03#ibcon#*before write, iclass 31, count 2 2006.168.07:36:31.03#ibcon#enter sib2, iclass 31, count 2 2006.168.07:36:31.03#ibcon#flushed, iclass 31, count 2 2006.168.07:36:31.03#ibcon#about to write, iclass 31, count 2 2006.168.07:36:31.03#ibcon#wrote, iclass 31, count 2 2006.168.07:36:31.03#ibcon#about to read 3, iclass 31, count 2 2006.168.07:36:31.06#ibcon#read 3, iclass 31, count 2 2006.168.07:36:31.06#ibcon#about to read 4, iclass 31, count 2 2006.168.07:36:31.06#ibcon#read 4, iclass 31, count 2 2006.168.07:36:31.06#ibcon#about to read 5, iclass 31, count 2 2006.168.07:36:31.06#ibcon#read 5, iclass 31, count 2 2006.168.07:36:31.06#ibcon#about to read 6, iclass 31, count 2 2006.168.07:36:31.06#ibcon#read 6, iclass 31, count 2 2006.168.07:36:31.06#ibcon#end of sib2, iclass 31, count 2 2006.168.07:36:31.06#ibcon#*after write, iclass 31, count 2 2006.168.07:36:31.06#ibcon#*before return 0, iclass 31, count 2 2006.168.07:36:31.06#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.168.07:36:31.06#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.168.07:36:31.06#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.168.07:36:31.06#ibcon#ireg 7 cls_cnt 0 2006.168.07:36:31.06#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.168.07:36:31.18#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.168.07:36:31.18#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.168.07:36:31.18#ibcon#enter wrdev, iclass 31, count 0 2006.168.07:36:31.18#ibcon#first serial, iclass 31, count 0 2006.168.07:36:31.18#ibcon#enter sib2, iclass 31, count 0 2006.168.07:36:31.18#ibcon#flushed, iclass 31, count 0 2006.168.07:36:31.18#ibcon#about to write, iclass 31, count 0 2006.168.07:36:31.18#ibcon#wrote, iclass 31, count 0 2006.168.07:36:31.18#ibcon#about to read 3, iclass 31, count 0 2006.168.07:36:31.20#ibcon#read 3, iclass 31, count 0 2006.168.07:36:31.20#ibcon#about to read 4, iclass 31, count 0 2006.168.07:36:31.20#ibcon#read 4, iclass 31, count 0 2006.168.07:36:31.20#ibcon#about to read 5, iclass 31, count 0 2006.168.07:36:31.20#ibcon#read 5, iclass 31, count 0 2006.168.07:36:31.20#ibcon#about to read 6, iclass 31, count 0 2006.168.07:36:31.20#ibcon#read 6, iclass 31, count 0 2006.168.07:36:31.20#ibcon#end of sib2, iclass 31, count 0 2006.168.07:36:31.20#ibcon#*mode == 0, iclass 31, count 0 2006.168.07:36:31.20#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.168.07:36:31.20#ibcon#[27=USB\r\n] 2006.168.07:36:31.20#ibcon#*before write, iclass 31, count 0 2006.168.07:36:31.20#ibcon#enter sib2, iclass 31, count 0 2006.168.07:36:31.20#ibcon#flushed, iclass 31, count 0 2006.168.07:36:31.20#ibcon#about to write, iclass 31, count 0 2006.168.07:36:31.20#ibcon#wrote, iclass 31, count 0 2006.168.07:36:31.20#ibcon#about to read 3, iclass 31, count 0 2006.168.07:36:31.23#ibcon#read 3, iclass 31, count 0 2006.168.07:36:31.23#ibcon#about to read 4, iclass 31, count 0 2006.168.07:36:31.23#ibcon#read 4, iclass 31, count 0 2006.168.07:36:31.23#ibcon#about to read 5, iclass 31, count 0 2006.168.07:36:31.23#ibcon#read 5, iclass 31, count 0 2006.168.07:36:31.23#ibcon#about to read 6, iclass 31, count 0 2006.168.07:36:31.23#ibcon#read 6, iclass 31, count 0 2006.168.07:36:31.23#ibcon#end of sib2, iclass 31, count 0 2006.168.07:36:31.23#ibcon#*after write, iclass 31, count 0 2006.168.07:36:31.23#ibcon#*before return 0, iclass 31, count 0 2006.168.07:36:31.23#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.168.07:36:31.23#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.168.07:36:31.23#ibcon#about to clear, iclass 31 cls_cnt 0 2006.168.07:36:31.23#ibcon#cleared, iclass 31 cls_cnt 0 2006.168.07:36:31.23$vc4f8/vblo=3,656.99 2006.168.07:36:31.23#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.168.07:36:31.23#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.168.07:36:31.23#ibcon#ireg 17 cls_cnt 0 2006.168.07:36:31.23#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.168.07:36:31.23#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.168.07:36:31.23#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.168.07:36:31.23#ibcon#enter wrdev, iclass 33, count 0 2006.168.07:36:31.23#ibcon#first serial, iclass 33, count 0 2006.168.07:36:31.23#ibcon#enter sib2, iclass 33, count 0 2006.168.07:36:31.23#ibcon#flushed, iclass 33, count 0 2006.168.07:36:31.23#ibcon#about to write, iclass 33, count 0 2006.168.07:36:31.23#ibcon#wrote, iclass 33, count 0 2006.168.07:36:31.23#ibcon#about to read 3, iclass 33, count 0 2006.168.07:36:31.25#ibcon#read 3, iclass 33, count 0 2006.168.07:36:31.25#ibcon#about to read 4, iclass 33, count 0 2006.168.07:36:31.25#ibcon#read 4, iclass 33, count 0 2006.168.07:36:31.25#ibcon#about to read 5, iclass 33, count 0 2006.168.07:36:31.25#ibcon#read 5, iclass 33, count 0 2006.168.07:36:31.25#ibcon#about to read 6, iclass 33, count 0 2006.168.07:36:31.25#ibcon#read 6, iclass 33, count 0 2006.168.07:36:31.25#ibcon#end of sib2, iclass 33, count 0 2006.168.07:36:31.25#ibcon#*mode == 0, iclass 33, count 0 2006.168.07:36:31.25#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.168.07:36:31.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.07:36:31.25#ibcon#*before write, iclass 33, count 0 2006.168.07:36:31.25#ibcon#enter sib2, iclass 33, count 0 2006.168.07:36:31.25#ibcon#flushed, iclass 33, count 0 2006.168.07:36:31.25#ibcon#about to write, iclass 33, count 0 2006.168.07:36:31.25#ibcon#wrote, iclass 33, count 0 2006.168.07:36:31.25#ibcon#about to read 3, iclass 33, count 0 2006.168.07:36:31.29#ibcon#read 3, iclass 33, count 0 2006.168.07:36:31.29#ibcon#about to read 4, iclass 33, count 0 2006.168.07:36:31.29#ibcon#read 4, iclass 33, count 0 2006.168.07:36:31.29#ibcon#about to read 5, iclass 33, count 0 2006.168.07:36:31.29#ibcon#read 5, iclass 33, count 0 2006.168.07:36:31.29#ibcon#about to read 6, iclass 33, count 0 2006.168.07:36:31.29#ibcon#read 6, iclass 33, count 0 2006.168.07:36:31.29#ibcon#end of sib2, iclass 33, count 0 2006.168.07:36:31.29#ibcon#*after write, iclass 33, count 0 2006.168.07:36:31.29#ibcon#*before return 0, iclass 33, count 0 2006.168.07:36:31.29#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.168.07:36:31.29#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.168.07:36:31.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.168.07:36:31.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.168.07:36:31.29$vc4f8/vb=3,4 2006.168.07:36:31.29#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.168.07:36:31.29#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.168.07:36:31.29#ibcon#ireg 11 cls_cnt 2 2006.168.07:36:31.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:36:31.35#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:36:31.35#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:36:31.35#ibcon#enter wrdev, iclass 35, count 2 2006.168.07:36:31.35#ibcon#first serial, iclass 35, count 2 2006.168.07:36:31.35#ibcon#enter sib2, iclass 35, count 2 2006.168.07:36:31.35#ibcon#flushed, iclass 35, count 2 2006.168.07:36:31.35#ibcon#about to write, iclass 35, count 2 2006.168.07:36:31.35#ibcon#wrote, iclass 35, count 2 2006.168.07:36:31.35#ibcon#about to read 3, iclass 35, count 2 2006.168.07:36:31.37#ibcon#read 3, iclass 35, count 2 2006.168.07:36:31.37#ibcon#about to read 4, iclass 35, count 2 2006.168.07:36:31.37#ibcon#read 4, iclass 35, count 2 2006.168.07:36:31.37#ibcon#about to read 5, iclass 35, count 2 2006.168.07:36:31.37#ibcon#read 5, iclass 35, count 2 2006.168.07:36:31.37#ibcon#about to read 6, iclass 35, count 2 2006.168.07:36:31.37#ibcon#read 6, iclass 35, count 2 2006.168.07:36:31.37#ibcon#end of sib2, iclass 35, count 2 2006.168.07:36:31.37#ibcon#*mode == 0, iclass 35, count 2 2006.168.07:36:31.37#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.168.07:36:31.37#ibcon#[27=AT03-04\r\n] 2006.168.07:36:31.37#ibcon#*before write, iclass 35, count 2 2006.168.07:36:31.37#ibcon#enter sib2, iclass 35, count 2 2006.168.07:36:31.37#ibcon#flushed, iclass 35, count 2 2006.168.07:36:31.37#ibcon#about to write, iclass 35, count 2 2006.168.07:36:31.37#ibcon#wrote, iclass 35, count 2 2006.168.07:36:31.37#ibcon#about to read 3, iclass 35, count 2 2006.168.07:36:31.40#ibcon#read 3, iclass 35, count 2 2006.168.07:36:31.40#ibcon#about to read 4, iclass 35, count 2 2006.168.07:36:31.40#ibcon#read 4, iclass 35, count 2 2006.168.07:36:31.40#ibcon#about to read 5, iclass 35, count 2 2006.168.07:36:31.40#ibcon#read 5, iclass 35, count 2 2006.168.07:36:31.40#ibcon#about to read 6, iclass 35, count 2 2006.168.07:36:31.40#ibcon#read 6, iclass 35, count 2 2006.168.07:36:31.40#ibcon#end of sib2, iclass 35, count 2 2006.168.07:36:31.40#ibcon#*after write, iclass 35, count 2 2006.168.07:36:31.40#ibcon#*before return 0, iclass 35, count 2 2006.168.07:36:31.40#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:36:31.40#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:36:31.40#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.168.07:36:31.40#ibcon#ireg 7 cls_cnt 0 2006.168.07:36:31.40#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:36:31.52#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:36:31.52#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:36:31.52#ibcon#enter wrdev, iclass 35, count 0 2006.168.07:36:31.52#ibcon#first serial, iclass 35, count 0 2006.168.07:36:31.52#ibcon#enter sib2, iclass 35, count 0 2006.168.07:36:31.52#ibcon#flushed, iclass 35, count 0 2006.168.07:36:31.52#ibcon#about to write, iclass 35, count 0 2006.168.07:36:31.52#ibcon#wrote, iclass 35, count 0 2006.168.07:36:31.52#ibcon#about to read 3, iclass 35, count 0 2006.168.07:36:31.54#ibcon#read 3, iclass 35, count 0 2006.168.07:36:31.54#ibcon#about to read 4, iclass 35, count 0 2006.168.07:36:31.54#ibcon#read 4, iclass 35, count 0 2006.168.07:36:31.54#ibcon#about to read 5, iclass 35, count 0 2006.168.07:36:31.54#ibcon#read 5, iclass 35, count 0 2006.168.07:36:31.54#ibcon#about to read 6, iclass 35, count 0 2006.168.07:36:31.54#ibcon#read 6, iclass 35, count 0 2006.168.07:36:31.54#ibcon#end of sib2, iclass 35, count 0 2006.168.07:36:31.54#ibcon#*mode == 0, iclass 35, count 0 2006.168.07:36:31.54#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.168.07:36:31.54#ibcon#[27=USB\r\n] 2006.168.07:36:31.54#ibcon#*before write, iclass 35, count 0 2006.168.07:36:31.54#ibcon#enter sib2, iclass 35, count 0 2006.168.07:36:31.54#ibcon#flushed, iclass 35, count 0 2006.168.07:36:31.54#ibcon#about to write, iclass 35, count 0 2006.168.07:36:31.54#ibcon#wrote, iclass 35, count 0 2006.168.07:36:31.54#ibcon#about to read 3, iclass 35, count 0 2006.168.07:36:31.57#ibcon#read 3, iclass 35, count 0 2006.168.07:36:31.57#ibcon#about to read 4, iclass 35, count 0 2006.168.07:36:31.57#ibcon#read 4, iclass 35, count 0 2006.168.07:36:31.57#ibcon#about to read 5, iclass 35, count 0 2006.168.07:36:31.57#ibcon#read 5, iclass 35, count 0 2006.168.07:36:31.57#ibcon#about to read 6, iclass 35, count 0 2006.168.07:36:31.57#ibcon#read 6, iclass 35, count 0 2006.168.07:36:31.57#ibcon#end of sib2, iclass 35, count 0 2006.168.07:36:31.57#ibcon#*after write, iclass 35, count 0 2006.168.07:36:31.57#ibcon#*before return 0, iclass 35, count 0 2006.168.07:36:31.57#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:36:31.57#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:36:31.57#ibcon#about to clear, iclass 35 cls_cnt 0 2006.168.07:36:31.57#ibcon#cleared, iclass 35 cls_cnt 0 2006.168.07:36:31.57$vc4f8/vblo=4,712.99 2006.168.07:36:31.57#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.168.07:36:31.57#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.168.07:36:31.57#ibcon#ireg 17 cls_cnt 0 2006.168.07:36:31.57#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:36:31.57#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:36:31.57#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:36:31.57#ibcon#enter wrdev, iclass 37, count 0 2006.168.07:36:31.57#ibcon#first serial, iclass 37, count 0 2006.168.07:36:31.57#ibcon#enter sib2, iclass 37, count 0 2006.168.07:36:31.57#ibcon#flushed, iclass 37, count 0 2006.168.07:36:31.57#ibcon#about to write, iclass 37, count 0 2006.168.07:36:31.57#ibcon#wrote, iclass 37, count 0 2006.168.07:36:31.57#ibcon#about to read 3, iclass 37, count 0 2006.168.07:36:31.59#ibcon#read 3, iclass 37, count 0 2006.168.07:36:31.59#ibcon#about to read 4, iclass 37, count 0 2006.168.07:36:31.59#ibcon#read 4, iclass 37, count 0 2006.168.07:36:31.59#ibcon#about to read 5, iclass 37, count 0 2006.168.07:36:31.59#ibcon#read 5, iclass 37, count 0 2006.168.07:36:31.59#ibcon#about to read 6, iclass 37, count 0 2006.168.07:36:31.59#ibcon#read 6, iclass 37, count 0 2006.168.07:36:31.59#ibcon#end of sib2, iclass 37, count 0 2006.168.07:36:31.59#ibcon#*mode == 0, iclass 37, count 0 2006.168.07:36:31.59#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.168.07:36:31.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.07:36:31.59#ibcon#*before write, iclass 37, count 0 2006.168.07:36:31.59#ibcon#enter sib2, iclass 37, count 0 2006.168.07:36:31.59#ibcon#flushed, iclass 37, count 0 2006.168.07:36:31.59#ibcon#about to write, iclass 37, count 0 2006.168.07:36:31.59#ibcon#wrote, iclass 37, count 0 2006.168.07:36:31.59#ibcon#about to read 3, iclass 37, count 0 2006.168.07:36:31.63#ibcon#read 3, iclass 37, count 0 2006.168.07:36:31.63#ibcon#about to read 4, iclass 37, count 0 2006.168.07:36:31.63#ibcon#read 4, iclass 37, count 0 2006.168.07:36:31.63#ibcon#about to read 5, iclass 37, count 0 2006.168.07:36:31.63#ibcon#read 5, iclass 37, count 0 2006.168.07:36:31.63#ibcon#about to read 6, iclass 37, count 0 2006.168.07:36:31.63#ibcon#read 6, iclass 37, count 0 2006.168.07:36:31.63#ibcon#end of sib2, iclass 37, count 0 2006.168.07:36:31.63#ibcon#*after write, iclass 37, count 0 2006.168.07:36:31.63#ibcon#*before return 0, iclass 37, count 0 2006.168.07:36:31.63#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:36:31.63#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:36:31.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.168.07:36:31.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.168.07:36:31.63$vc4f8/vb=4,4 2006.168.07:36:31.63#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.168.07:36:31.63#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.168.07:36:31.63#ibcon#ireg 11 cls_cnt 2 2006.168.07:36:31.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:36:31.69#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:36:31.69#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:36:31.69#ibcon#enter wrdev, iclass 39, count 2 2006.168.07:36:31.69#ibcon#first serial, iclass 39, count 2 2006.168.07:36:31.69#ibcon#enter sib2, iclass 39, count 2 2006.168.07:36:31.69#ibcon#flushed, iclass 39, count 2 2006.168.07:36:31.69#ibcon#about to write, iclass 39, count 2 2006.168.07:36:31.69#ibcon#wrote, iclass 39, count 2 2006.168.07:36:31.69#ibcon#about to read 3, iclass 39, count 2 2006.168.07:36:31.71#ibcon#read 3, iclass 39, count 2 2006.168.07:36:31.71#ibcon#about to read 4, iclass 39, count 2 2006.168.07:36:31.71#ibcon#read 4, iclass 39, count 2 2006.168.07:36:31.71#ibcon#about to read 5, iclass 39, count 2 2006.168.07:36:31.71#ibcon#read 5, iclass 39, count 2 2006.168.07:36:31.71#ibcon#about to read 6, iclass 39, count 2 2006.168.07:36:31.71#ibcon#read 6, iclass 39, count 2 2006.168.07:36:31.71#ibcon#end of sib2, iclass 39, count 2 2006.168.07:36:31.71#ibcon#*mode == 0, iclass 39, count 2 2006.168.07:36:31.71#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.168.07:36:31.71#ibcon#[27=AT04-04\r\n] 2006.168.07:36:31.71#ibcon#*before write, iclass 39, count 2 2006.168.07:36:31.71#ibcon#enter sib2, iclass 39, count 2 2006.168.07:36:31.71#ibcon#flushed, iclass 39, count 2 2006.168.07:36:31.71#ibcon#about to write, iclass 39, count 2 2006.168.07:36:31.71#ibcon#wrote, iclass 39, count 2 2006.168.07:36:31.71#ibcon#about to read 3, iclass 39, count 2 2006.168.07:36:31.74#ibcon#read 3, iclass 39, count 2 2006.168.07:36:31.74#ibcon#about to read 4, iclass 39, count 2 2006.168.07:36:31.74#ibcon#read 4, iclass 39, count 2 2006.168.07:36:31.74#ibcon#about to read 5, iclass 39, count 2 2006.168.07:36:31.74#ibcon#read 5, iclass 39, count 2 2006.168.07:36:31.74#ibcon#about to read 6, iclass 39, count 2 2006.168.07:36:31.74#ibcon#read 6, iclass 39, count 2 2006.168.07:36:31.74#ibcon#end of sib2, iclass 39, count 2 2006.168.07:36:31.74#ibcon#*after write, iclass 39, count 2 2006.168.07:36:31.74#ibcon#*before return 0, iclass 39, count 2 2006.168.07:36:31.74#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:36:31.74#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:36:31.74#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.168.07:36:31.74#ibcon#ireg 7 cls_cnt 0 2006.168.07:36:31.74#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:36:31.86#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:36:31.86#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:36:31.86#ibcon#enter wrdev, iclass 39, count 0 2006.168.07:36:31.86#ibcon#first serial, iclass 39, count 0 2006.168.07:36:31.86#ibcon#enter sib2, iclass 39, count 0 2006.168.07:36:31.86#ibcon#flushed, iclass 39, count 0 2006.168.07:36:31.86#ibcon#about to write, iclass 39, count 0 2006.168.07:36:31.86#ibcon#wrote, iclass 39, count 0 2006.168.07:36:31.86#ibcon#about to read 3, iclass 39, count 0 2006.168.07:36:31.88#ibcon#read 3, iclass 39, count 0 2006.168.07:36:31.88#ibcon#about to read 4, iclass 39, count 0 2006.168.07:36:31.88#ibcon#read 4, iclass 39, count 0 2006.168.07:36:31.88#ibcon#about to read 5, iclass 39, count 0 2006.168.07:36:31.88#ibcon#read 5, iclass 39, count 0 2006.168.07:36:31.88#ibcon#about to read 6, iclass 39, count 0 2006.168.07:36:31.88#ibcon#read 6, iclass 39, count 0 2006.168.07:36:31.88#ibcon#end of sib2, iclass 39, count 0 2006.168.07:36:31.88#ibcon#*mode == 0, iclass 39, count 0 2006.168.07:36:31.88#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.168.07:36:31.88#ibcon#[27=USB\r\n] 2006.168.07:36:31.88#ibcon#*before write, iclass 39, count 0 2006.168.07:36:31.88#ibcon#enter sib2, iclass 39, count 0 2006.168.07:36:31.88#ibcon#flushed, iclass 39, count 0 2006.168.07:36:31.88#ibcon#about to write, iclass 39, count 0 2006.168.07:36:31.88#ibcon#wrote, iclass 39, count 0 2006.168.07:36:31.88#ibcon#about to read 3, iclass 39, count 0 2006.168.07:36:31.91#ibcon#read 3, iclass 39, count 0 2006.168.07:36:31.91#ibcon#about to read 4, iclass 39, count 0 2006.168.07:36:31.91#ibcon#read 4, iclass 39, count 0 2006.168.07:36:31.91#ibcon#about to read 5, iclass 39, count 0 2006.168.07:36:31.91#ibcon#read 5, iclass 39, count 0 2006.168.07:36:31.91#ibcon#about to read 6, iclass 39, count 0 2006.168.07:36:31.91#ibcon#read 6, iclass 39, count 0 2006.168.07:36:31.91#ibcon#end of sib2, iclass 39, count 0 2006.168.07:36:31.91#ibcon#*after write, iclass 39, count 0 2006.168.07:36:31.91#ibcon#*before return 0, iclass 39, count 0 2006.168.07:36:31.91#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:36:31.91#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:36:31.91#ibcon#about to clear, iclass 39 cls_cnt 0 2006.168.07:36:31.91#ibcon#cleared, iclass 39 cls_cnt 0 2006.168.07:36:31.91$vc4f8/vblo=5,744.99 2006.168.07:36:31.91#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.168.07:36:31.91#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.168.07:36:31.91#ibcon#ireg 17 cls_cnt 0 2006.168.07:36:31.91#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:36:31.91#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:36:31.91#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:36:31.91#ibcon#enter wrdev, iclass 3, count 0 2006.168.07:36:31.91#ibcon#first serial, iclass 3, count 0 2006.168.07:36:31.91#ibcon#enter sib2, iclass 3, count 0 2006.168.07:36:31.91#ibcon#flushed, iclass 3, count 0 2006.168.07:36:31.91#ibcon#about to write, iclass 3, count 0 2006.168.07:36:31.91#ibcon#wrote, iclass 3, count 0 2006.168.07:36:31.91#ibcon#about to read 3, iclass 3, count 0 2006.168.07:36:31.93#ibcon#read 3, iclass 3, count 0 2006.168.07:36:31.93#ibcon#about to read 4, iclass 3, count 0 2006.168.07:36:31.93#ibcon#read 4, iclass 3, count 0 2006.168.07:36:31.93#ibcon#about to read 5, iclass 3, count 0 2006.168.07:36:31.93#ibcon#read 5, iclass 3, count 0 2006.168.07:36:31.93#ibcon#about to read 6, iclass 3, count 0 2006.168.07:36:31.93#ibcon#read 6, iclass 3, count 0 2006.168.07:36:31.93#ibcon#end of sib2, iclass 3, count 0 2006.168.07:36:31.93#ibcon#*mode == 0, iclass 3, count 0 2006.168.07:36:31.93#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.168.07:36:31.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.07:36:31.93#ibcon#*before write, iclass 3, count 0 2006.168.07:36:31.93#ibcon#enter sib2, iclass 3, count 0 2006.168.07:36:31.93#ibcon#flushed, iclass 3, count 0 2006.168.07:36:31.93#ibcon#about to write, iclass 3, count 0 2006.168.07:36:31.93#ibcon#wrote, iclass 3, count 0 2006.168.07:36:31.93#ibcon#about to read 3, iclass 3, count 0 2006.168.07:36:31.97#ibcon#read 3, iclass 3, count 0 2006.168.07:36:31.97#ibcon#about to read 4, iclass 3, count 0 2006.168.07:36:31.97#ibcon#read 4, iclass 3, count 0 2006.168.07:36:31.97#ibcon#about to read 5, iclass 3, count 0 2006.168.07:36:31.97#ibcon#read 5, iclass 3, count 0 2006.168.07:36:31.97#ibcon#about to read 6, iclass 3, count 0 2006.168.07:36:31.97#ibcon#read 6, iclass 3, count 0 2006.168.07:36:31.97#ibcon#end of sib2, iclass 3, count 0 2006.168.07:36:31.97#ibcon#*after write, iclass 3, count 0 2006.168.07:36:31.97#ibcon#*before return 0, iclass 3, count 0 2006.168.07:36:31.97#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:36:31.97#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:36:31.97#ibcon#about to clear, iclass 3 cls_cnt 0 2006.168.07:36:31.97#ibcon#cleared, iclass 3 cls_cnt 0 2006.168.07:36:31.97$vc4f8/vb=5,4 2006.168.07:36:31.97#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.168.07:36:31.97#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.168.07:36:31.97#ibcon#ireg 11 cls_cnt 2 2006.168.07:36:31.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:36:32.03#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:36:32.03#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:36:32.03#ibcon#enter wrdev, iclass 5, count 2 2006.168.07:36:32.03#ibcon#first serial, iclass 5, count 2 2006.168.07:36:32.03#ibcon#enter sib2, iclass 5, count 2 2006.168.07:36:32.03#ibcon#flushed, iclass 5, count 2 2006.168.07:36:32.03#ibcon#about to write, iclass 5, count 2 2006.168.07:36:32.03#ibcon#wrote, iclass 5, count 2 2006.168.07:36:32.03#ibcon#about to read 3, iclass 5, count 2 2006.168.07:36:32.05#ibcon#read 3, iclass 5, count 2 2006.168.07:36:32.05#ibcon#about to read 4, iclass 5, count 2 2006.168.07:36:32.05#ibcon#read 4, iclass 5, count 2 2006.168.07:36:32.05#ibcon#about to read 5, iclass 5, count 2 2006.168.07:36:32.05#ibcon#read 5, iclass 5, count 2 2006.168.07:36:32.05#ibcon#about to read 6, iclass 5, count 2 2006.168.07:36:32.05#ibcon#read 6, iclass 5, count 2 2006.168.07:36:32.05#ibcon#end of sib2, iclass 5, count 2 2006.168.07:36:32.05#ibcon#*mode == 0, iclass 5, count 2 2006.168.07:36:32.05#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.168.07:36:32.05#ibcon#[27=AT05-04\r\n] 2006.168.07:36:32.05#ibcon#*before write, iclass 5, count 2 2006.168.07:36:32.05#ibcon#enter sib2, iclass 5, count 2 2006.168.07:36:32.05#ibcon#flushed, iclass 5, count 2 2006.168.07:36:32.05#ibcon#about to write, iclass 5, count 2 2006.168.07:36:32.05#ibcon#wrote, iclass 5, count 2 2006.168.07:36:32.05#ibcon#about to read 3, iclass 5, count 2 2006.168.07:36:32.08#ibcon#read 3, iclass 5, count 2 2006.168.07:36:32.08#ibcon#about to read 4, iclass 5, count 2 2006.168.07:36:32.08#ibcon#read 4, iclass 5, count 2 2006.168.07:36:32.08#ibcon#about to read 5, iclass 5, count 2 2006.168.07:36:32.08#ibcon#read 5, iclass 5, count 2 2006.168.07:36:32.08#ibcon#about to read 6, iclass 5, count 2 2006.168.07:36:32.08#ibcon#read 6, iclass 5, count 2 2006.168.07:36:32.08#ibcon#end of sib2, iclass 5, count 2 2006.168.07:36:32.08#ibcon#*after write, iclass 5, count 2 2006.168.07:36:32.08#ibcon#*before return 0, iclass 5, count 2 2006.168.07:36:32.08#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:36:32.08#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:36:32.08#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.168.07:36:32.08#ibcon#ireg 7 cls_cnt 0 2006.168.07:36:32.08#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:36:32.20#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:36:32.20#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:36:32.20#ibcon#enter wrdev, iclass 5, count 0 2006.168.07:36:32.20#ibcon#first serial, iclass 5, count 0 2006.168.07:36:32.20#ibcon#enter sib2, iclass 5, count 0 2006.168.07:36:32.20#ibcon#flushed, iclass 5, count 0 2006.168.07:36:32.20#ibcon#about to write, iclass 5, count 0 2006.168.07:36:32.20#ibcon#wrote, iclass 5, count 0 2006.168.07:36:32.20#ibcon#about to read 3, iclass 5, count 0 2006.168.07:36:32.22#ibcon#read 3, iclass 5, count 0 2006.168.07:36:32.22#ibcon#about to read 4, iclass 5, count 0 2006.168.07:36:32.22#ibcon#read 4, iclass 5, count 0 2006.168.07:36:32.22#ibcon#about to read 5, iclass 5, count 0 2006.168.07:36:32.22#ibcon#read 5, iclass 5, count 0 2006.168.07:36:32.22#ibcon#about to read 6, iclass 5, count 0 2006.168.07:36:32.22#ibcon#read 6, iclass 5, count 0 2006.168.07:36:32.22#ibcon#end of sib2, iclass 5, count 0 2006.168.07:36:32.22#ibcon#*mode == 0, iclass 5, count 0 2006.168.07:36:32.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.168.07:36:32.22#ibcon#[27=USB\r\n] 2006.168.07:36:32.22#ibcon#*before write, iclass 5, count 0 2006.168.07:36:32.22#ibcon#enter sib2, iclass 5, count 0 2006.168.07:36:32.22#ibcon#flushed, iclass 5, count 0 2006.168.07:36:32.22#ibcon#about to write, iclass 5, count 0 2006.168.07:36:32.22#ibcon#wrote, iclass 5, count 0 2006.168.07:36:32.22#ibcon#about to read 3, iclass 5, count 0 2006.168.07:36:32.25#ibcon#read 3, iclass 5, count 0 2006.168.07:36:32.25#ibcon#about to read 4, iclass 5, count 0 2006.168.07:36:32.25#ibcon#read 4, iclass 5, count 0 2006.168.07:36:32.25#ibcon#about to read 5, iclass 5, count 0 2006.168.07:36:32.25#ibcon#read 5, iclass 5, count 0 2006.168.07:36:32.25#ibcon#about to read 6, iclass 5, count 0 2006.168.07:36:32.25#ibcon#read 6, iclass 5, count 0 2006.168.07:36:32.25#ibcon#end of sib2, iclass 5, count 0 2006.168.07:36:32.25#ibcon#*after write, iclass 5, count 0 2006.168.07:36:32.25#ibcon#*before return 0, iclass 5, count 0 2006.168.07:36:32.25#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:36:32.25#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:36:32.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.168.07:36:32.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.168.07:36:32.25$vc4f8/vblo=6,752.99 2006.168.07:36:32.25#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.168.07:36:32.25#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.168.07:36:32.25#ibcon#ireg 17 cls_cnt 0 2006.168.07:36:32.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:36:32.25#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:36:32.25#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:36:32.25#ibcon#enter wrdev, iclass 7, count 0 2006.168.07:36:32.25#ibcon#first serial, iclass 7, count 0 2006.168.07:36:32.25#ibcon#enter sib2, iclass 7, count 0 2006.168.07:36:32.25#ibcon#flushed, iclass 7, count 0 2006.168.07:36:32.25#ibcon#about to write, iclass 7, count 0 2006.168.07:36:32.25#ibcon#wrote, iclass 7, count 0 2006.168.07:36:32.25#ibcon#about to read 3, iclass 7, count 0 2006.168.07:36:32.27#ibcon#read 3, iclass 7, count 0 2006.168.07:36:32.27#ibcon#about to read 4, iclass 7, count 0 2006.168.07:36:32.27#ibcon#read 4, iclass 7, count 0 2006.168.07:36:32.27#ibcon#about to read 5, iclass 7, count 0 2006.168.07:36:32.27#ibcon#read 5, iclass 7, count 0 2006.168.07:36:32.27#ibcon#about to read 6, iclass 7, count 0 2006.168.07:36:32.27#ibcon#read 6, iclass 7, count 0 2006.168.07:36:32.27#ibcon#end of sib2, iclass 7, count 0 2006.168.07:36:32.27#ibcon#*mode == 0, iclass 7, count 0 2006.168.07:36:32.27#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.168.07:36:32.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.07:36:32.27#ibcon#*before write, iclass 7, count 0 2006.168.07:36:32.27#ibcon#enter sib2, iclass 7, count 0 2006.168.07:36:32.27#ibcon#flushed, iclass 7, count 0 2006.168.07:36:32.27#ibcon#about to write, iclass 7, count 0 2006.168.07:36:32.27#ibcon#wrote, iclass 7, count 0 2006.168.07:36:32.27#ibcon#about to read 3, iclass 7, count 0 2006.168.07:36:32.31#ibcon#read 3, iclass 7, count 0 2006.168.07:36:32.31#ibcon#about to read 4, iclass 7, count 0 2006.168.07:36:32.31#ibcon#read 4, iclass 7, count 0 2006.168.07:36:32.31#ibcon#about to read 5, iclass 7, count 0 2006.168.07:36:32.31#ibcon#read 5, iclass 7, count 0 2006.168.07:36:32.31#ibcon#about to read 6, iclass 7, count 0 2006.168.07:36:32.31#ibcon#read 6, iclass 7, count 0 2006.168.07:36:32.31#ibcon#end of sib2, iclass 7, count 0 2006.168.07:36:32.31#ibcon#*after write, iclass 7, count 0 2006.168.07:36:32.31#ibcon#*before return 0, iclass 7, count 0 2006.168.07:36:32.31#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:36:32.31#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:36:32.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.168.07:36:32.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.168.07:36:32.31$vc4f8/vb=6,4 2006.168.07:36:32.31#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.168.07:36:32.31#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.168.07:36:32.31#ibcon#ireg 11 cls_cnt 2 2006.168.07:36:32.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:36:32.37#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:36:32.37#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:36:32.37#ibcon#enter wrdev, iclass 11, count 2 2006.168.07:36:32.37#ibcon#first serial, iclass 11, count 2 2006.168.07:36:32.37#ibcon#enter sib2, iclass 11, count 2 2006.168.07:36:32.37#ibcon#flushed, iclass 11, count 2 2006.168.07:36:32.37#ibcon#about to write, iclass 11, count 2 2006.168.07:36:32.37#ibcon#wrote, iclass 11, count 2 2006.168.07:36:32.37#ibcon#about to read 3, iclass 11, count 2 2006.168.07:36:32.39#ibcon#read 3, iclass 11, count 2 2006.168.07:36:32.39#ibcon#about to read 4, iclass 11, count 2 2006.168.07:36:32.39#ibcon#read 4, iclass 11, count 2 2006.168.07:36:32.39#ibcon#about to read 5, iclass 11, count 2 2006.168.07:36:32.39#ibcon#read 5, iclass 11, count 2 2006.168.07:36:32.39#ibcon#about to read 6, iclass 11, count 2 2006.168.07:36:32.39#ibcon#read 6, iclass 11, count 2 2006.168.07:36:32.39#ibcon#end of sib2, iclass 11, count 2 2006.168.07:36:32.39#ibcon#*mode == 0, iclass 11, count 2 2006.168.07:36:32.39#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.168.07:36:32.39#ibcon#[27=AT06-04\r\n] 2006.168.07:36:32.39#ibcon#*before write, iclass 11, count 2 2006.168.07:36:32.39#ibcon#enter sib2, iclass 11, count 2 2006.168.07:36:32.39#ibcon#flushed, iclass 11, count 2 2006.168.07:36:32.39#ibcon#about to write, iclass 11, count 2 2006.168.07:36:32.39#ibcon#wrote, iclass 11, count 2 2006.168.07:36:32.39#ibcon#about to read 3, iclass 11, count 2 2006.168.07:36:32.42#ibcon#read 3, iclass 11, count 2 2006.168.07:36:32.42#ibcon#about to read 4, iclass 11, count 2 2006.168.07:36:32.42#ibcon#read 4, iclass 11, count 2 2006.168.07:36:32.42#ibcon#about to read 5, iclass 11, count 2 2006.168.07:36:32.42#ibcon#read 5, iclass 11, count 2 2006.168.07:36:32.42#ibcon#about to read 6, iclass 11, count 2 2006.168.07:36:32.42#ibcon#read 6, iclass 11, count 2 2006.168.07:36:32.42#ibcon#end of sib2, iclass 11, count 2 2006.168.07:36:32.42#ibcon#*after write, iclass 11, count 2 2006.168.07:36:32.42#ibcon#*before return 0, iclass 11, count 2 2006.168.07:36:32.42#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:36:32.42#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:36:32.42#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.168.07:36:32.42#ibcon#ireg 7 cls_cnt 0 2006.168.07:36:32.42#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:36:32.54#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:36:32.54#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:36:32.54#ibcon#enter wrdev, iclass 11, count 0 2006.168.07:36:32.54#ibcon#first serial, iclass 11, count 0 2006.168.07:36:32.54#ibcon#enter sib2, iclass 11, count 0 2006.168.07:36:32.54#ibcon#flushed, iclass 11, count 0 2006.168.07:36:32.54#ibcon#about to write, iclass 11, count 0 2006.168.07:36:32.54#ibcon#wrote, iclass 11, count 0 2006.168.07:36:32.54#ibcon#about to read 3, iclass 11, count 0 2006.168.07:36:32.56#ibcon#read 3, iclass 11, count 0 2006.168.07:36:32.56#ibcon#about to read 4, iclass 11, count 0 2006.168.07:36:32.56#ibcon#read 4, iclass 11, count 0 2006.168.07:36:32.56#ibcon#about to read 5, iclass 11, count 0 2006.168.07:36:32.56#ibcon#read 5, iclass 11, count 0 2006.168.07:36:32.56#ibcon#about to read 6, iclass 11, count 0 2006.168.07:36:32.56#ibcon#read 6, iclass 11, count 0 2006.168.07:36:32.56#ibcon#end of sib2, iclass 11, count 0 2006.168.07:36:32.56#ibcon#*mode == 0, iclass 11, count 0 2006.168.07:36:32.56#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.168.07:36:32.56#ibcon#[27=USB\r\n] 2006.168.07:36:32.56#ibcon#*before write, iclass 11, count 0 2006.168.07:36:32.56#ibcon#enter sib2, iclass 11, count 0 2006.168.07:36:32.56#ibcon#flushed, iclass 11, count 0 2006.168.07:36:32.56#ibcon#about to write, iclass 11, count 0 2006.168.07:36:32.56#ibcon#wrote, iclass 11, count 0 2006.168.07:36:32.56#ibcon#about to read 3, iclass 11, count 0 2006.168.07:36:32.59#ibcon#read 3, iclass 11, count 0 2006.168.07:36:32.59#ibcon#about to read 4, iclass 11, count 0 2006.168.07:36:32.59#ibcon#read 4, iclass 11, count 0 2006.168.07:36:32.59#ibcon#about to read 5, iclass 11, count 0 2006.168.07:36:32.59#ibcon#read 5, iclass 11, count 0 2006.168.07:36:32.59#ibcon#about to read 6, iclass 11, count 0 2006.168.07:36:32.59#ibcon#read 6, iclass 11, count 0 2006.168.07:36:32.59#ibcon#end of sib2, iclass 11, count 0 2006.168.07:36:32.59#ibcon#*after write, iclass 11, count 0 2006.168.07:36:32.59#ibcon#*before return 0, iclass 11, count 0 2006.168.07:36:32.59#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:36:32.59#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:36:32.59#ibcon#about to clear, iclass 11 cls_cnt 0 2006.168.07:36:32.59#ibcon#cleared, iclass 11 cls_cnt 0 2006.168.07:36:32.59$vc4f8/vabw=wide 2006.168.07:36:32.59#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.168.07:36:32.59#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.168.07:36:32.59#ibcon#ireg 8 cls_cnt 0 2006.168.07:36:32.59#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:36:32.59#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:36:32.59#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:36:32.59#ibcon#enter wrdev, iclass 13, count 0 2006.168.07:36:32.59#ibcon#first serial, iclass 13, count 0 2006.168.07:36:32.59#ibcon#enter sib2, iclass 13, count 0 2006.168.07:36:32.59#ibcon#flushed, iclass 13, count 0 2006.168.07:36:32.59#ibcon#about to write, iclass 13, count 0 2006.168.07:36:32.59#ibcon#wrote, iclass 13, count 0 2006.168.07:36:32.59#ibcon#about to read 3, iclass 13, count 0 2006.168.07:36:32.61#ibcon#read 3, iclass 13, count 0 2006.168.07:36:32.61#ibcon#about to read 4, iclass 13, count 0 2006.168.07:36:32.61#ibcon#read 4, iclass 13, count 0 2006.168.07:36:32.61#ibcon#about to read 5, iclass 13, count 0 2006.168.07:36:32.61#ibcon#read 5, iclass 13, count 0 2006.168.07:36:32.61#ibcon#about to read 6, iclass 13, count 0 2006.168.07:36:32.61#ibcon#read 6, iclass 13, count 0 2006.168.07:36:32.61#ibcon#end of sib2, iclass 13, count 0 2006.168.07:36:32.61#ibcon#*mode == 0, iclass 13, count 0 2006.168.07:36:32.61#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.168.07:36:32.61#ibcon#[25=BW32\r\n] 2006.168.07:36:32.61#ibcon#*before write, iclass 13, count 0 2006.168.07:36:32.61#ibcon#enter sib2, iclass 13, count 0 2006.168.07:36:32.61#ibcon#flushed, iclass 13, count 0 2006.168.07:36:32.61#ibcon#about to write, iclass 13, count 0 2006.168.07:36:32.61#ibcon#wrote, iclass 13, count 0 2006.168.07:36:32.61#ibcon#about to read 3, iclass 13, count 0 2006.168.07:36:32.64#ibcon#read 3, iclass 13, count 0 2006.168.07:36:32.64#ibcon#about to read 4, iclass 13, count 0 2006.168.07:36:32.64#ibcon#read 4, iclass 13, count 0 2006.168.07:36:32.64#ibcon#about to read 5, iclass 13, count 0 2006.168.07:36:32.64#ibcon#read 5, iclass 13, count 0 2006.168.07:36:32.64#ibcon#about to read 6, iclass 13, count 0 2006.168.07:36:32.64#ibcon#read 6, iclass 13, count 0 2006.168.07:36:32.64#ibcon#end of sib2, iclass 13, count 0 2006.168.07:36:32.64#ibcon#*after write, iclass 13, count 0 2006.168.07:36:32.64#ibcon#*before return 0, iclass 13, count 0 2006.168.07:36:32.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:36:32.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:36:32.64#ibcon#about to clear, iclass 13 cls_cnt 0 2006.168.07:36:32.64#ibcon#cleared, iclass 13 cls_cnt 0 2006.168.07:36:32.64$vc4f8/vbbw=wide 2006.168.07:36:32.64#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.168.07:36:32.64#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.168.07:36:32.64#ibcon#ireg 8 cls_cnt 0 2006.168.07:36:32.64#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:36:32.71#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:36:32.71#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:36:32.71#ibcon#enter wrdev, iclass 15, count 0 2006.168.07:36:32.71#ibcon#first serial, iclass 15, count 0 2006.168.07:36:32.71#ibcon#enter sib2, iclass 15, count 0 2006.168.07:36:32.71#ibcon#flushed, iclass 15, count 0 2006.168.07:36:32.71#ibcon#about to write, iclass 15, count 0 2006.168.07:36:32.71#ibcon#wrote, iclass 15, count 0 2006.168.07:36:32.71#ibcon#about to read 3, iclass 15, count 0 2006.168.07:36:32.73#ibcon#read 3, iclass 15, count 0 2006.168.07:36:32.73#ibcon#about to read 4, iclass 15, count 0 2006.168.07:36:32.73#ibcon#read 4, iclass 15, count 0 2006.168.07:36:32.73#ibcon#about to read 5, iclass 15, count 0 2006.168.07:36:32.73#ibcon#read 5, iclass 15, count 0 2006.168.07:36:32.73#ibcon#about to read 6, iclass 15, count 0 2006.168.07:36:32.73#ibcon#read 6, iclass 15, count 0 2006.168.07:36:32.73#ibcon#end of sib2, iclass 15, count 0 2006.168.07:36:32.73#ibcon#*mode == 0, iclass 15, count 0 2006.168.07:36:32.73#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.168.07:36:32.73#ibcon#[27=BW32\r\n] 2006.168.07:36:32.73#ibcon#*before write, iclass 15, count 0 2006.168.07:36:32.73#ibcon#enter sib2, iclass 15, count 0 2006.168.07:36:32.73#ibcon#flushed, iclass 15, count 0 2006.168.07:36:32.73#ibcon#about to write, iclass 15, count 0 2006.168.07:36:32.73#ibcon#wrote, iclass 15, count 0 2006.168.07:36:32.73#ibcon#about to read 3, iclass 15, count 0 2006.168.07:36:32.76#ibcon#read 3, iclass 15, count 0 2006.168.07:36:32.76#ibcon#about to read 4, iclass 15, count 0 2006.168.07:36:32.76#ibcon#read 4, iclass 15, count 0 2006.168.07:36:32.76#ibcon#about to read 5, iclass 15, count 0 2006.168.07:36:32.76#ibcon#read 5, iclass 15, count 0 2006.168.07:36:32.76#ibcon#about to read 6, iclass 15, count 0 2006.168.07:36:32.76#ibcon#read 6, iclass 15, count 0 2006.168.07:36:32.76#ibcon#end of sib2, iclass 15, count 0 2006.168.07:36:32.76#ibcon#*after write, iclass 15, count 0 2006.168.07:36:32.76#ibcon#*before return 0, iclass 15, count 0 2006.168.07:36:32.76#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:36:32.76#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:36:32.76#ibcon#about to clear, iclass 15 cls_cnt 0 2006.168.07:36:32.76#ibcon#cleared, iclass 15 cls_cnt 0 2006.168.07:36:32.76$4f8m12a/ifd4f 2006.168.07:36:32.76$ifd4f/lo= 2006.168.07:36:32.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.07:36:32.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.07:36:32.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.07:36:32.76$ifd4f/patch= 2006.168.07:36:32.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.07:36:32.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.07:36:32.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.07:36:32.76$4f8m12a/"form=m,16.000,1:2 2006.168.07:36:32.76$4f8m12a/"tpicd 2006.168.07:36:32.76$4f8m12a/echo=off 2006.168.07:36:32.76$4f8m12a/xlog=off 2006.168.07:36:32.76:!2006.168.07:37:00 2006.168.07:36:47.13#trakl#Source acquired 2006.168.07:36:48.13#flagr#flagr/antenna,acquired 2006.168.07:37:00.00:preob 2006.168.07:37:01.13/onsource/TRACKING 2006.168.07:37:01.13:!2006.168.07:37:10 2006.168.07:37:10.00:data_valid=on 2006.168.07:37:10.00:midob 2006.168.07:37:10.13/onsource/TRACKING 2006.168.07:37:10.13/wx/27.84,1004.6,72 2006.168.07:37:10.21/cable/+6.4726E-03 2006.168.07:37:11.30/va/01,08,usb,yes,30,31 2006.168.07:37:11.30/va/02,07,usb,yes,30,31 2006.168.07:37:11.30/va/03,06,usb,yes,31,32 2006.168.07:37:11.30/va/04,07,usb,yes,30,33 2006.168.07:37:11.30/va/05,07,usb,yes,30,32 2006.168.07:37:11.30/va/06,06,usb,yes,29,29 2006.168.07:37:11.30/va/07,06,usb,yes,30,29 2006.168.07:37:11.30/va/08,07,usb,yes,28,27 2006.168.07:37:11.53/valo/01,532.99,yes,locked 2006.168.07:37:11.53/valo/02,572.99,yes,locked 2006.168.07:37:11.53/valo/03,672.99,yes,locked 2006.168.07:37:11.53/valo/04,832.99,yes,locked 2006.168.07:37:11.53/valo/05,652.99,yes,locked 2006.168.07:37:11.53/valo/06,772.99,yes,locked 2006.168.07:37:11.53/valo/07,832.99,yes,locked 2006.168.07:37:11.53/valo/08,852.99,yes,locked 2006.168.07:37:12.62/vb/01,04,usb,yes,29,28 2006.168.07:37:12.62/vb/02,04,usb,yes,31,33 2006.168.07:37:12.62/vb/03,04,usb,yes,28,31 2006.168.07:37:12.62/vb/04,04,usb,yes,28,29 2006.168.07:37:12.62/vb/05,04,usb,yes,27,31 2006.168.07:37:12.62/vb/06,04,usb,yes,28,31 2006.168.07:37:12.62/vb/07,04,usb,yes,30,30 2006.168.07:37:12.62/vb/08,04,usb,yes,28,31 2006.168.07:37:12.85/vblo/01,632.99,yes,locked 2006.168.07:37:12.85/vblo/02,640.99,yes,locked 2006.168.07:37:12.85/vblo/03,656.99,yes,locked 2006.168.07:37:12.85/vblo/04,712.99,yes,locked 2006.168.07:37:12.85/vblo/05,744.99,yes,locked 2006.168.07:37:12.85/vblo/06,752.99,yes,locked 2006.168.07:37:12.85/vblo/07,734.99,yes,locked 2006.168.07:37:12.85/vblo/08,744.99,yes,locked 2006.168.07:37:13.00/vabw/8 2006.168.07:37:13.15/vbbw/8 2006.168.07:37:13.24/xfe/off,on,14.2 2006.168.07:37:13.61/ifatt/23,28,28,28 2006.168.07:37:14.08/fmout-gps/S +4.20E-07 2006.168.07:37:14.12:!2006.168.07:38:10 2006.168.07:38:10.00:data_valid=off 2006.168.07:38:10.00:postob 2006.168.07:38:10.16/cable/+6.4718E-03 2006.168.07:38:10.16/wx/27.80,1004.6,72 2006.168.07:38:11.08/fmout-gps/S +4.20E-07 2006.168.07:38:11.08:scan_name=168-0739,k06168,60 2006.168.07:38:11.09:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.168.07:38:11.14#flagr#flagr/antenna,new-source 2006.168.07:38:12.14:checkk5 2006.168.07:38:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.168.07:38:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.168.07:38:13.28/chk_autoobs//k5ts3/ autoobs is running! 2006.168.07:38:13.66/chk_autoobs//k5ts4/ autoobs is running! 2006.168.07:38:14.03/chk_obsdata//k5ts1/T1680737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:38:14.40/chk_obsdata//k5ts2/T1680737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:38:14.77/chk_obsdata//k5ts3/T1680737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:38:15.15/chk_obsdata//k5ts4/T1680737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:38:15.84/k5log//k5ts1_log_newline 2006.168.07:38:16.53/k5log//k5ts2_log_newline 2006.168.07:38:17.21/k5log//k5ts3_log_newline 2006.168.07:38:17.90/k5log//k5ts4_log_newline 2006.168.07:38:17.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.07:38:17.93:4f8m12a=1 2006.168.07:38:17.93$4f8m12a/echo=on 2006.168.07:38:17.93$4f8m12a/pcalon 2006.168.07:38:17.93$pcalon/"no phase cal control is implemented here 2006.168.07:38:17.93$4f8m12a/"tpicd=stop 2006.168.07:38:17.93$4f8m12a/vc4f8 2006.168.07:38:17.93$vc4f8/valo=1,532.99 2006.168.07:38:17.93#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.168.07:38:17.93#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.168.07:38:17.93#ibcon#ireg 17 cls_cnt 0 2006.168.07:38:17.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:38:17.93#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:38:17.93#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:38:17.93#ibcon#enter wrdev, iclass 22, count 0 2006.168.07:38:17.93#ibcon#first serial, iclass 22, count 0 2006.168.07:38:17.93#ibcon#enter sib2, iclass 22, count 0 2006.168.07:38:17.93#ibcon#flushed, iclass 22, count 0 2006.168.07:38:17.93#ibcon#about to write, iclass 22, count 0 2006.168.07:38:17.93#ibcon#wrote, iclass 22, count 0 2006.168.07:38:17.93#ibcon#about to read 3, iclass 22, count 0 2006.168.07:38:17.98#ibcon#read 3, iclass 22, count 0 2006.168.07:38:17.98#ibcon#about to read 4, iclass 22, count 0 2006.168.07:38:17.98#ibcon#read 4, iclass 22, count 0 2006.168.07:38:17.98#ibcon#about to read 5, iclass 22, count 0 2006.168.07:38:17.98#ibcon#read 5, iclass 22, count 0 2006.168.07:38:17.98#ibcon#about to read 6, iclass 22, count 0 2006.168.07:38:17.98#ibcon#read 6, iclass 22, count 0 2006.168.07:38:17.98#ibcon#end of sib2, iclass 22, count 0 2006.168.07:38:17.98#ibcon#*mode == 0, iclass 22, count 0 2006.168.07:38:17.98#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.168.07:38:17.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.07:38:17.98#ibcon#*before write, iclass 22, count 0 2006.168.07:38:17.98#ibcon#enter sib2, iclass 22, count 0 2006.168.07:38:17.98#ibcon#flushed, iclass 22, count 0 2006.168.07:38:17.98#ibcon#about to write, iclass 22, count 0 2006.168.07:38:17.98#ibcon#wrote, iclass 22, count 0 2006.168.07:38:17.98#ibcon#about to read 3, iclass 22, count 0 2006.168.07:38:18.02#ibcon#read 3, iclass 22, count 0 2006.168.07:38:18.02#ibcon#about to read 4, iclass 22, count 0 2006.168.07:38:18.02#ibcon#read 4, iclass 22, count 0 2006.168.07:38:18.02#ibcon#about to read 5, iclass 22, count 0 2006.168.07:38:18.02#ibcon#read 5, iclass 22, count 0 2006.168.07:38:18.02#ibcon#about to read 6, iclass 22, count 0 2006.168.07:38:18.02#ibcon#read 6, iclass 22, count 0 2006.168.07:38:18.02#ibcon#end of sib2, iclass 22, count 0 2006.168.07:38:18.02#ibcon#*after write, iclass 22, count 0 2006.168.07:38:18.02#ibcon#*before return 0, iclass 22, count 0 2006.168.07:38:18.02#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:38:18.02#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:38:18.02#ibcon#about to clear, iclass 22 cls_cnt 0 2006.168.07:38:18.02#ibcon#cleared, iclass 22 cls_cnt 0 2006.168.07:38:18.02$vc4f8/va=1,8 2006.168.07:38:18.02#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.168.07:38:18.02#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.168.07:38:18.02#ibcon#ireg 11 cls_cnt 2 2006.168.07:38:18.02#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:38:18.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:38:18.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:38:18.02#ibcon#enter wrdev, iclass 24, count 2 2006.168.07:38:18.02#ibcon#first serial, iclass 24, count 2 2006.168.07:38:18.02#ibcon#enter sib2, iclass 24, count 2 2006.168.07:38:18.02#ibcon#flushed, iclass 24, count 2 2006.168.07:38:18.02#ibcon#about to write, iclass 24, count 2 2006.168.07:38:18.02#ibcon#wrote, iclass 24, count 2 2006.168.07:38:18.02#ibcon#about to read 3, iclass 24, count 2 2006.168.07:38:18.04#ibcon#read 3, iclass 24, count 2 2006.168.07:38:18.04#ibcon#about to read 4, iclass 24, count 2 2006.168.07:38:18.04#ibcon#read 4, iclass 24, count 2 2006.168.07:38:18.04#ibcon#about to read 5, iclass 24, count 2 2006.168.07:38:18.04#ibcon#read 5, iclass 24, count 2 2006.168.07:38:18.04#ibcon#about to read 6, iclass 24, count 2 2006.168.07:38:18.04#ibcon#read 6, iclass 24, count 2 2006.168.07:38:18.04#ibcon#end of sib2, iclass 24, count 2 2006.168.07:38:18.04#ibcon#*mode == 0, iclass 24, count 2 2006.168.07:38:18.04#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.168.07:38:18.04#ibcon#[25=AT01-08\r\n] 2006.168.07:38:18.04#ibcon#*before write, iclass 24, count 2 2006.168.07:38:18.04#ibcon#enter sib2, iclass 24, count 2 2006.168.07:38:18.04#ibcon#flushed, iclass 24, count 2 2006.168.07:38:18.04#ibcon#about to write, iclass 24, count 2 2006.168.07:38:18.04#ibcon#wrote, iclass 24, count 2 2006.168.07:38:18.04#ibcon#about to read 3, iclass 24, count 2 2006.168.07:38:18.07#ibcon#read 3, iclass 24, count 2 2006.168.07:38:18.07#ibcon#about to read 4, iclass 24, count 2 2006.168.07:38:18.07#ibcon#read 4, iclass 24, count 2 2006.168.07:38:18.07#ibcon#about to read 5, iclass 24, count 2 2006.168.07:38:18.07#ibcon#read 5, iclass 24, count 2 2006.168.07:38:18.07#ibcon#about to read 6, iclass 24, count 2 2006.168.07:38:18.07#ibcon#read 6, iclass 24, count 2 2006.168.07:38:18.07#ibcon#end of sib2, iclass 24, count 2 2006.168.07:38:18.07#ibcon#*after write, iclass 24, count 2 2006.168.07:38:18.07#ibcon#*before return 0, iclass 24, count 2 2006.168.07:38:18.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:38:18.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:38:18.07#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.168.07:38:18.07#ibcon#ireg 7 cls_cnt 0 2006.168.07:38:18.07#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:38:18.19#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:38:18.19#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:38:18.19#ibcon#enter wrdev, iclass 24, count 0 2006.168.07:38:18.19#ibcon#first serial, iclass 24, count 0 2006.168.07:38:18.19#ibcon#enter sib2, iclass 24, count 0 2006.168.07:38:18.19#ibcon#flushed, iclass 24, count 0 2006.168.07:38:18.19#ibcon#about to write, iclass 24, count 0 2006.168.07:38:18.19#ibcon#wrote, iclass 24, count 0 2006.168.07:38:18.19#ibcon#about to read 3, iclass 24, count 0 2006.168.07:38:18.21#ibcon#read 3, iclass 24, count 0 2006.168.07:38:18.21#ibcon#about to read 4, iclass 24, count 0 2006.168.07:38:18.21#ibcon#read 4, iclass 24, count 0 2006.168.07:38:18.21#ibcon#about to read 5, iclass 24, count 0 2006.168.07:38:18.21#ibcon#read 5, iclass 24, count 0 2006.168.07:38:18.21#ibcon#about to read 6, iclass 24, count 0 2006.168.07:38:18.21#ibcon#read 6, iclass 24, count 0 2006.168.07:38:18.21#ibcon#end of sib2, iclass 24, count 0 2006.168.07:38:18.21#ibcon#*mode == 0, iclass 24, count 0 2006.168.07:38:18.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.168.07:38:18.21#ibcon#[25=USB\r\n] 2006.168.07:38:18.21#ibcon#*before write, iclass 24, count 0 2006.168.07:38:18.21#ibcon#enter sib2, iclass 24, count 0 2006.168.07:38:18.21#ibcon#flushed, iclass 24, count 0 2006.168.07:38:18.21#ibcon#about to write, iclass 24, count 0 2006.168.07:38:18.21#ibcon#wrote, iclass 24, count 0 2006.168.07:38:18.21#ibcon#about to read 3, iclass 24, count 0 2006.168.07:38:18.24#ibcon#read 3, iclass 24, count 0 2006.168.07:38:18.24#ibcon#about to read 4, iclass 24, count 0 2006.168.07:38:18.24#ibcon#read 4, iclass 24, count 0 2006.168.07:38:18.24#ibcon#about to read 5, iclass 24, count 0 2006.168.07:38:18.24#ibcon#read 5, iclass 24, count 0 2006.168.07:38:18.24#ibcon#about to read 6, iclass 24, count 0 2006.168.07:38:18.24#ibcon#read 6, iclass 24, count 0 2006.168.07:38:18.24#ibcon#end of sib2, iclass 24, count 0 2006.168.07:38:18.24#ibcon#*after write, iclass 24, count 0 2006.168.07:38:18.24#ibcon#*before return 0, iclass 24, count 0 2006.168.07:38:18.24#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:38:18.24#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:38:18.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.168.07:38:18.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.168.07:38:18.24$vc4f8/valo=2,572.99 2006.168.07:38:18.24#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.168.07:38:18.24#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.168.07:38:18.24#ibcon#ireg 17 cls_cnt 0 2006.168.07:38:18.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:38:18.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:38:18.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:38:18.24#ibcon#enter wrdev, iclass 26, count 0 2006.168.07:38:18.24#ibcon#first serial, iclass 26, count 0 2006.168.07:38:18.24#ibcon#enter sib2, iclass 26, count 0 2006.168.07:38:18.24#ibcon#flushed, iclass 26, count 0 2006.168.07:38:18.24#ibcon#about to write, iclass 26, count 0 2006.168.07:38:18.24#ibcon#wrote, iclass 26, count 0 2006.168.07:38:18.24#ibcon#about to read 3, iclass 26, count 0 2006.168.07:38:18.26#ibcon#read 3, iclass 26, count 0 2006.168.07:38:18.26#ibcon#about to read 4, iclass 26, count 0 2006.168.07:38:18.26#ibcon#read 4, iclass 26, count 0 2006.168.07:38:18.26#ibcon#about to read 5, iclass 26, count 0 2006.168.07:38:18.26#ibcon#read 5, iclass 26, count 0 2006.168.07:38:18.26#ibcon#about to read 6, iclass 26, count 0 2006.168.07:38:18.26#ibcon#read 6, iclass 26, count 0 2006.168.07:38:18.26#ibcon#end of sib2, iclass 26, count 0 2006.168.07:38:18.26#ibcon#*mode == 0, iclass 26, count 0 2006.168.07:38:18.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.168.07:38:18.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.07:38:18.26#ibcon#*before write, iclass 26, count 0 2006.168.07:38:18.26#ibcon#enter sib2, iclass 26, count 0 2006.168.07:38:18.26#ibcon#flushed, iclass 26, count 0 2006.168.07:38:18.26#ibcon#about to write, iclass 26, count 0 2006.168.07:38:18.26#ibcon#wrote, iclass 26, count 0 2006.168.07:38:18.26#ibcon#about to read 3, iclass 26, count 0 2006.168.07:38:18.30#ibcon#read 3, iclass 26, count 0 2006.168.07:38:18.30#ibcon#about to read 4, iclass 26, count 0 2006.168.07:38:18.30#ibcon#read 4, iclass 26, count 0 2006.168.07:38:18.30#ibcon#about to read 5, iclass 26, count 0 2006.168.07:38:18.30#ibcon#read 5, iclass 26, count 0 2006.168.07:38:18.30#ibcon#about to read 6, iclass 26, count 0 2006.168.07:38:18.30#ibcon#read 6, iclass 26, count 0 2006.168.07:38:18.30#ibcon#end of sib2, iclass 26, count 0 2006.168.07:38:18.30#ibcon#*after write, iclass 26, count 0 2006.168.07:38:18.30#ibcon#*before return 0, iclass 26, count 0 2006.168.07:38:18.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:38:18.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:38:18.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.168.07:38:18.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.168.07:38:18.30$vc4f8/va=2,7 2006.168.07:38:18.30#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.168.07:38:18.30#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.168.07:38:18.30#ibcon#ireg 11 cls_cnt 2 2006.168.07:38:18.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.168.07:38:18.36#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.168.07:38:18.36#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.168.07:38:18.36#ibcon#enter wrdev, iclass 28, count 2 2006.168.07:38:18.36#ibcon#first serial, iclass 28, count 2 2006.168.07:38:18.36#ibcon#enter sib2, iclass 28, count 2 2006.168.07:38:18.36#ibcon#flushed, iclass 28, count 2 2006.168.07:38:18.36#ibcon#about to write, iclass 28, count 2 2006.168.07:38:18.36#ibcon#wrote, iclass 28, count 2 2006.168.07:38:18.36#ibcon#about to read 3, iclass 28, count 2 2006.168.07:38:18.38#ibcon#read 3, iclass 28, count 2 2006.168.07:38:18.38#ibcon#about to read 4, iclass 28, count 2 2006.168.07:38:18.38#ibcon#read 4, iclass 28, count 2 2006.168.07:38:18.38#ibcon#about to read 5, iclass 28, count 2 2006.168.07:38:18.38#ibcon#read 5, iclass 28, count 2 2006.168.07:38:18.38#ibcon#about to read 6, iclass 28, count 2 2006.168.07:38:18.38#ibcon#read 6, iclass 28, count 2 2006.168.07:38:18.38#ibcon#end of sib2, iclass 28, count 2 2006.168.07:38:18.38#ibcon#*mode == 0, iclass 28, count 2 2006.168.07:38:18.38#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.168.07:38:18.38#ibcon#[25=AT02-07\r\n] 2006.168.07:38:18.38#ibcon#*before write, iclass 28, count 2 2006.168.07:38:18.38#ibcon#enter sib2, iclass 28, count 2 2006.168.07:38:18.38#ibcon#flushed, iclass 28, count 2 2006.168.07:38:18.38#ibcon#about to write, iclass 28, count 2 2006.168.07:38:18.38#ibcon#wrote, iclass 28, count 2 2006.168.07:38:18.38#ibcon#about to read 3, iclass 28, count 2 2006.168.07:38:18.41#ibcon#read 3, iclass 28, count 2 2006.168.07:38:18.41#ibcon#about to read 4, iclass 28, count 2 2006.168.07:38:18.41#ibcon#read 4, iclass 28, count 2 2006.168.07:38:18.41#ibcon#about to read 5, iclass 28, count 2 2006.168.07:38:18.41#ibcon#read 5, iclass 28, count 2 2006.168.07:38:18.41#ibcon#about to read 6, iclass 28, count 2 2006.168.07:38:18.41#ibcon#read 6, iclass 28, count 2 2006.168.07:38:18.41#ibcon#end of sib2, iclass 28, count 2 2006.168.07:38:18.41#ibcon#*after write, iclass 28, count 2 2006.168.07:38:18.41#ibcon#*before return 0, iclass 28, count 2 2006.168.07:38:18.41#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.168.07:38:18.41#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.168.07:38:18.41#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.168.07:38:18.41#ibcon#ireg 7 cls_cnt 0 2006.168.07:38:18.41#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.168.07:38:18.53#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.168.07:38:18.53#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.168.07:38:18.53#ibcon#enter wrdev, iclass 28, count 0 2006.168.07:38:18.53#ibcon#first serial, iclass 28, count 0 2006.168.07:38:18.53#ibcon#enter sib2, iclass 28, count 0 2006.168.07:38:18.53#ibcon#flushed, iclass 28, count 0 2006.168.07:38:18.53#ibcon#about to write, iclass 28, count 0 2006.168.07:38:18.53#ibcon#wrote, iclass 28, count 0 2006.168.07:38:18.53#ibcon#about to read 3, iclass 28, count 0 2006.168.07:38:18.55#ibcon#read 3, iclass 28, count 0 2006.168.07:38:18.55#ibcon#about to read 4, iclass 28, count 0 2006.168.07:38:18.55#ibcon#read 4, iclass 28, count 0 2006.168.07:38:18.55#ibcon#about to read 5, iclass 28, count 0 2006.168.07:38:18.55#ibcon#read 5, iclass 28, count 0 2006.168.07:38:18.55#ibcon#about to read 6, iclass 28, count 0 2006.168.07:38:18.55#ibcon#read 6, iclass 28, count 0 2006.168.07:38:18.55#ibcon#end of sib2, iclass 28, count 0 2006.168.07:38:18.55#ibcon#*mode == 0, iclass 28, count 0 2006.168.07:38:18.55#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.168.07:38:18.55#ibcon#[25=USB\r\n] 2006.168.07:38:18.55#ibcon#*before write, iclass 28, count 0 2006.168.07:38:18.55#ibcon#enter sib2, iclass 28, count 0 2006.168.07:38:18.55#ibcon#flushed, iclass 28, count 0 2006.168.07:38:18.55#ibcon#about to write, iclass 28, count 0 2006.168.07:38:18.55#ibcon#wrote, iclass 28, count 0 2006.168.07:38:18.55#ibcon#about to read 3, iclass 28, count 0 2006.168.07:38:18.58#ibcon#read 3, iclass 28, count 0 2006.168.07:38:18.58#ibcon#about to read 4, iclass 28, count 0 2006.168.07:38:18.58#ibcon#read 4, iclass 28, count 0 2006.168.07:38:18.58#ibcon#about to read 5, iclass 28, count 0 2006.168.07:38:18.58#ibcon#read 5, iclass 28, count 0 2006.168.07:38:18.58#ibcon#about to read 6, iclass 28, count 0 2006.168.07:38:18.58#ibcon#read 6, iclass 28, count 0 2006.168.07:38:18.58#ibcon#end of sib2, iclass 28, count 0 2006.168.07:38:18.58#ibcon#*after write, iclass 28, count 0 2006.168.07:38:18.58#ibcon#*before return 0, iclass 28, count 0 2006.168.07:38:18.58#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.168.07:38:18.58#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.168.07:38:18.58#ibcon#about to clear, iclass 28 cls_cnt 0 2006.168.07:38:18.58#ibcon#cleared, iclass 28 cls_cnt 0 2006.168.07:38:18.58$vc4f8/valo=3,672.99 2006.168.07:38:18.58#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.168.07:38:18.58#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.168.07:38:18.58#ibcon#ireg 17 cls_cnt 0 2006.168.07:38:18.58#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:38:18.58#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:38:18.58#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:38:18.58#ibcon#enter wrdev, iclass 30, count 0 2006.168.07:38:18.58#ibcon#first serial, iclass 30, count 0 2006.168.07:38:18.58#ibcon#enter sib2, iclass 30, count 0 2006.168.07:38:18.58#ibcon#flushed, iclass 30, count 0 2006.168.07:38:18.58#ibcon#about to write, iclass 30, count 0 2006.168.07:38:18.58#ibcon#wrote, iclass 30, count 0 2006.168.07:38:18.58#ibcon#about to read 3, iclass 30, count 0 2006.168.07:38:18.60#ibcon#read 3, iclass 30, count 0 2006.168.07:38:18.60#ibcon#about to read 4, iclass 30, count 0 2006.168.07:38:18.60#ibcon#read 4, iclass 30, count 0 2006.168.07:38:18.60#ibcon#about to read 5, iclass 30, count 0 2006.168.07:38:18.60#ibcon#read 5, iclass 30, count 0 2006.168.07:38:18.60#ibcon#about to read 6, iclass 30, count 0 2006.168.07:38:18.60#ibcon#read 6, iclass 30, count 0 2006.168.07:38:18.60#ibcon#end of sib2, iclass 30, count 0 2006.168.07:38:18.60#ibcon#*mode == 0, iclass 30, count 0 2006.168.07:38:18.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.168.07:38:18.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.07:38:18.60#ibcon#*before write, iclass 30, count 0 2006.168.07:38:18.60#ibcon#enter sib2, iclass 30, count 0 2006.168.07:38:18.60#ibcon#flushed, iclass 30, count 0 2006.168.07:38:18.60#ibcon#about to write, iclass 30, count 0 2006.168.07:38:18.60#ibcon#wrote, iclass 30, count 0 2006.168.07:38:18.60#ibcon#about to read 3, iclass 30, count 0 2006.168.07:38:18.64#ibcon#read 3, iclass 30, count 0 2006.168.07:38:18.64#ibcon#about to read 4, iclass 30, count 0 2006.168.07:38:18.64#ibcon#read 4, iclass 30, count 0 2006.168.07:38:18.64#ibcon#about to read 5, iclass 30, count 0 2006.168.07:38:18.64#ibcon#read 5, iclass 30, count 0 2006.168.07:38:18.64#ibcon#about to read 6, iclass 30, count 0 2006.168.07:38:18.64#ibcon#read 6, iclass 30, count 0 2006.168.07:38:18.64#ibcon#end of sib2, iclass 30, count 0 2006.168.07:38:18.64#ibcon#*after write, iclass 30, count 0 2006.168.07:38:18.64#ibcon#*before return 0, iclass 30, count 0 2006.168.07:38:18.64#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:38:18.64#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:38:18.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.168.07:38:18.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.168.07:38:18.64$vc4f8/va=3,6 2006.168.07:38:18.64#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.168.07:38:18.64#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.168.07:38:18.64#ibcon#ireg 11 cls_cnt 2 2006.168.07:38:18.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:38:18.70#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:38:18.70#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:38:18.70#ibcon#enter wrdev, iclass 32, count 2 2006.168.07:38:18.70#ibcon#first serial, iclass 32, count 2 2006.168.07:38:18.70#ibcon#enter sib2, iclass 32, count 2 2006.168.07:38:18.70#ibcon#flushed, iclass 32, count 2 2006.168.07:38:18.70#ibcon#about to write, iclass 32, count 2 2006.168.07:38:18.70#ibcon#wrote, iclass 32, count 2 2006.168.07:38:18.70#ibcon#about to read 3, iclass 32, count 2 2006.168.07:38:18.72#ibcon#read 3, iclass 32, count 2 2006.168.07:38:18.72#ibcon#about to read 4, iclass 32, count 2 2006.168.07:38:18.72#ibcon#read 4, iclass 32, count 2 2006.168.07:38:18.72#ibcon#about to read 5, iclass 32, count 2 2006.168.07:38:18.72#ibcon#read 5, iclass 32, count 2 2006.168.07:38:18.72#ibcon#about to read 6, iclass 32, count 2 2006.168.07:38:18.73#ibcon#read 6, iclass 32, count 2 2006.168.07:38:18.73#ibcon#end of sib2, iclass 32, count 2 2006.168.07:38:18.73#ibcon#*mode == 0, iclass 32, count 2 2006.168.07:38:18.73#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.168.07:38:18.73#ibcon#[25=AT03-06\r\n] 2006.168.07:38:18.73#ibcon#*before write, iclass 32, count 2 2006.168.07:38:18.73#ibcon#enter sib2, iclass 32, count 2 2006.168.07:38:18.73#ibcon#flushed, iclass 32, count 2 2006.168.07:38:18.73#ibcon#about to write, iclass 32, count 2 2006.168.07:38:18.73#ibcon#wrote, iclass 32, count 2 2006.168.07:38:18.73#ibcon#about to read 3, iclass 32, count 2 2006.168.07:38:18.76#ibcon#read 3, iclass 32, count 2 2006.168.07:38:18.76#ibcon#about to read 4, iclass 32, count 2 2006.168.07:38:18.76#ibcon#read 4, iclass 32, count 2 2006.168.07:38:18.76#ibcon#about to read 5, iclass 32, count 2 2006.168.07:38:18.76#ibcon#read 5, iclass 32, count 2 2006.168.07:38:18.76#ibcon#about to read 6, iclass 32, count 2 2006.168.07:38:18.76#ibcon#read 6, iclass 32, count 2 2006.168.07:38:18.76#ibcon#end of sib2, iclass 32, count 2 2006.168.07:38:18.76#ibcon#*after write, iclass 32, count 2 2006.168.07:38:18.76#ibcon#*before return 0, iclass 32, count 2 2006.168.07:38:18.76#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:38:18.76#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:38:18.76#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.168.07:38:18.76#ibcon#ireg 7 cls_cnt 0 2006.168.07:38:18.76#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:38:18.88#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:38:18.88#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:38:18.88#ibcon#enter wrdev, iclass 32, count 0 2006.168.07:38:18.88#ibcon#first serial, iclass 32, count 0 2006.168.07:38:18.88#ibcon#enter sib2, iclass 32, count 0 2006.168.07:38:18.88#ibcon#flushed, iclass 32, count 0 2006.168.07:38:18.88#ibcon#about to write, iclass 32, count 0 2006.168.07:38:18.88#ibcon#wrote, iclass 32, count 0 2006.168.07:38:18.88#ibcon#about to read 3, iclass 32, count 0 2006.168.07:38:18.90#ibcon#read 3, iclass 32, count 0 2006.168.07:38:18.90#ibcon#about to read 4, iclass 32, count 0 2006.168.07:38:18.90#ibcon#read 4, iclass 32, count 0 2006.168.07:38:18.90#ibcon#about to read 5, iclass 32, count 0 2006.168.07:38:18.90#ibcon#read 5, iclass 32, count 0 2006.168.07:38:18.90#ibcon#about to read 6, iclass 32, count 0 2006.168.07:38:18.90#ibcon#read 6, iclass 32, count 0 2006.168.07:38:18.90#ibcon#end of sib2, iclass 32, count 0 2006.168.07:38:18.90#ibcon#*mode == 0, iclass 32, count 0 2006.168.07:38:18.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.168.07:38:18.90#ibcon#[25=USB\r\n] 2006.168.07:38:18.90#ibcon#*before write, iclass 32, count 0 2006.168.07:38:18.90#ibcon#enter sib2, iclass 32, count 0 2006.168.07:38:18.90#ibcon#flushed, iclass 32, count 0 2006.168.07:38:18.90#ibcon#about to write, iclass 32, count 0 2006.168.07:38:18.90#ibcon#wrote, iclass 32, count 0 2006.168.07:38:18.90#ibcon#about to read 3, iclass 32, count 0 2006.168.07:38:18.93#ibcon#read 3, iclass 32, count 0 2006.168.07:38:18.93#ibcon#about to read 4, iclass 32, count 0 2006.168.07:38:18.93#ibcon#read 4, iclass 32, count 0 2006.168.07:38:18.93#ibcon#about to read 5, iclass 32, count 0 2006.168.07:38:18.93#ibcon#read 5, iclass 32, count 0 2006.168.07:38:18.93#ibcon#about to read 6, iclass 32, count 0 2006.168.07:38:18.93#ibcon#read 6, iclass 32, count 0 2006.168.07:38:18.93#ibcon#end of sib2, iclass 32, count 0 2006.168.07:38:18.93#ibcon#*after write, iclass 32, count 0 2006.168.07:38:18.93#ibcon#*before return 0, iclass 32, count 0 2006.168.07:38:18.93#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:38:18.93#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:38:18.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.168.07:38:18.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.168.07:38:18.93$vc4f8/valo=4,832.99 2006.168.07:38:18.93#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.168.07:38:18.93#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.168.07:38:18.93#ibcon#ireg 17 cls_cnt 0 2006.168.07:38:18.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:38:18.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:38:18.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:38:18.93#ibcon#enter wrdev, iclass 34, count 0 2006.168.07:38:18.93#ibcon#first serial, iclass 34, count 0 2006.168.07:38:18.93#ibcon#enter sib2, iclass 34, count 0 2006.168.07:38:18.93#ibcon#flushed, iclass 34, count 0 2006.168.07:38:18.93#ibcon#about to write, iclass 34, count 0 2006.168.07:38:18.93#ibcon#wrote, iclass 34, count 0 2006.168.07:38:18.93#ibcon#about to read 3, iclass 34, count 0 2006.168.07:38:18.95#ibcon#read 3, iclass 34, count 0 2006.168.07:38:18.95#ibcon#about to read 4, iclass 34, count 0 2006.168.07:38:18.95#ibcon#read 4, iclass 34, count 0 2006.168.07:38:18.95#ibcon#about to read 5, iclass 34, count 0 2006.168.07:38:18.95#ibcon#read 5, iclass 34, count 0 2006.168.07:38:18.95#ibcon#about to read 6, iclass 34, count 0 2006.168.07:38:18.95#ibcon#read 6, iclass 34, count 0 2006.168.07:38:18.95#ibcon#end of sib2, iclass 34, count 0 2006.168.07:38:18.95#ibcon#*mode == 0, iclass 34, count 0 2006.168.07:38:18.95#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.168.07:38:18.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.07:38:18.95#ibcon#*before write, iclass 34, count 0 2006.168.07:38:18.95#ibcon#enter sib2, iclass 34, count 0 2006.168.07:38:18.95#ibcon#flushed, iclass 34, count 0 2006.168.07:38:18.95#ibcon#about to write, iclass 34, count 0 2006.168.07:38:18.95#ibcon#wrote, iclass 34, count 0 2006.168.07:38:18.95#ibcon#about to read 3, iclass 34, count 0 2006.168.07:38:18.99#ibcon#read 3, iclass 34, count 0 2006.168.07:38:18.99#ibcon#about to read 4, iclass 34, count 0 2006.168.07:38:18.99#ibcon#read 4, iclass 34, count 0 2006.168.07:38:18.99#ibcon#about to read 5, iclass 34, count 0 2006.168.07:38:18.99#ibcon#read 5, iclass 34, count 0 2006.168.07:38:18.99#ibcon#about to read 6, iclass 34, count 0 2006.168.07:38:18.99#ibcon#read 6, iclass 34, count 0 2006.168.07:38:18.99#ibcon#end of sib2, iclass 34, count 0 2006.168.07:38:18.99#ibcon#*after write, iclass 34, count 0 2006.168.07:38:18.99#ibcon#*before return 0, iclass 34, count 0 2006.168.07:38:18.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:38:18.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:38:18.99#ibcon#about to clear, iclass 34 cls_cnt 0 2006.168.07:38:18.99#ibcon#cleared, iclass 34 cls_cnt 0 2006.168.07:38:18.99$vc4f8/va=4,7 2006.168.07:38:18.99#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.168.07:38:18.99#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.168.07:38:18.99#ibcon#ireg 11 cls_cnt 2 2006.168.07:38:18.99#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:38:19.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:38:19.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:38:19.05#ibcon#enter wrdev, iclass 36, count 2 2006.168.07:38:19.05#ibcon#first serial, iclass 36, count 2 2006.168.07:38:19.05#ibcon#enter sib2, iclass 36, count 2 2006.168.07:38:19.05#ibcon#flushed, iclass 36, count 2 2006.168.07:38:19.05#ibcon#about to write, iclass 36, count 2 2006.168.07:38:19.05#ibcon#wrote, iclass 36, count 2 2006.168.07:38:19.05#ibcon#about to read 3, iclass 36, count 2 2006.168.07:38:19.07#ibcon#read 3, iclass 36, count 2 2006.168.07:38:19.07#ibcon#about to read 4, iclass 36, count 2 2006.168.07:38:19.07#ibcon#read 4, iclass 36, count 2 2006.168.07:38:19.07#ibcon#about to read 5, iclass 36, count 2 2006.168.07:38:19.07#ibcon#read 5, iclass 36, count 2 2006.168.07:38:19.07#ibcon#about to read 6, iclass 36, count 2 2006.168.07:38:19.07#ibcon#read 6, iclass 36, count 2 2006.168.07:38:19.07#ibcon#end of sib2, iclass 36, count 2 2006.168.07:38:19.07#ibcon#*mode == 0, iclass 36, count 2 2006.168.07:38:19.07#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.168.07:38:19.07#ibcon#[25=AT04-07\r\n] 2006.168.07:38:19.07#ibcon#*before write, iclass 36, count 2 2006.168.07:38:19.07#ibcon#enter sib2, iclass 36, count 2 2006.168.07:38:19.07#ibcon#flushed, iclass 36, count 2 2006.168.07:38:19.07#ibcon#about to write, iclass 36, count 2 2006.168.07:38:19.07#ibcon#wrote, iclass 36, count 2 2006.168.07:38:19.07#ibcon#about to read 3, iclass 36, count 2 2006.168.07:38:19.10#ibcon#read 3, iclass 36, count 2 2006.168.07:38:19.10#ibcon#about to read 4, iclass 36, count 2 2006.168.07:38:19.10#ibcon#read 4, iclass 36, count 2 2006.168.07:38:19.10#ibcon#about to read 5, iclass 36, count 2 2006.168.07:38:19.10#ibcon#read 5, iclass 36, count 2 2006.168.07:38:19.10#ibcon#about to read 6, iclass 36, count 2 2006.168.07:38:19.10#ibcon#read 6, iclass 36, count 2 2006.168.07:38:19.10#ibcon#end of sib2, iclass 36, count 2 2006.168.07:38:19.10#ibcon#*after write, iclass 36, count 2 2006.168.07:38:19.10#ibcon#*before return 0, iclass 36, count 2 2006.168.07:38:19.10#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:38:19.10#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:38:19.10#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.168.07:38:19.10#ibcon#ireg 7 cls_cnt 0 2006.168.07:38:19.10#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:38:19.22#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:38:19.22#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:38:19.22#ibcon#enter wrdev, iclass 36, count 0 2006.168.07:38:19.22#ibcon#first serial, iclass 36, count 0 2006.168.07:38:19.22#ibcon#enter sib2, iclass 36, count 0 2006.168.07:38:19.22#ibcon#flushed, iclass 36, count 0 2006.168.07:38:19.22#ibcon#about to write, iclass 36, count 0 2006.168.07:38:19.22#ibcon#wrote, iclass 36, count 0 2006.168.07:38:19.22#ibcon#about to read 3, iclass 36, count 0 2006.168.07:38:19.24#ibcon#read 3, iclass 36, count 0 2006.168.07:38:19.24#ibcon#about to read 4, iclass 36, count 0 2006.168.07:38:19.24#ibcon#read 4, iclass 36, count 0 2006.168.07:38:19.24#ibcon#about to read 5, iclass 36, count 0 2006.168.07:38:19.24#ibcon#read 5, iclass 36, count 0 2006.168.07:38:19.24#ibcon#about to read 6, iclass 36, count 0 2006.168.07:38:19.24#ibcon#read 6, iclass 36, count 0 2006.168.07:38:19.24#ibcon#end of sib2, iclass 36, count 0 2006.168.07:38:19.24#ibcon#*mode == 0, iclass 36, count 0 2006.168.07:38:19.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.168.07:38:19.24#ibcon#[25=USB\r\n] 2006.168.07:38:19.24#ibcon#*before write, iclass 36, count 0 2006.168.07:38:19.24#ibcon#enter sib2, iclass 36, count 0 2006.168.07:38:19.24#ibcon#flushed, iclass 36, count 0 2006.168.07:38:19.24#ibcon#about to write, iclass 36, count 0 2006.168.07:38:19.24#ibcon#wrote, iclass 36, count 0 2006.168.07:38:19.24#ibcon#about to read 3, iclass 36, count 0 2006.168.07:38:19.27#ibcon#read 3, iclass 36, count 0 2006.168.07:38:19.27#ibcon#about to read 4, iclass 36, count 0 2006.168.07:38:19.27#ibcon#read 4, iclass 36, count 0 2006.168.07:38:19.27#ibcon#about to read 5, iclass 36, count 0 2006.168.07:38:19.27#ibcon#read 5, iclass 36, count 0 2006.168.07:38:19.27#ibcon#about to read 6, iclass 36, count 0 2006.168.07:38:19.27#ibcon#read 6, iclass 36, count 0 2006.168.07:38:19.27#ibcon#end of sib2, iclass 36, count 0 2006.168.07:38:19.27#ibcon#*after write, iclass 36, count 0 2006.168.07:38:19.27#ibcon#*before return 0, iclass 36, count 0 2006.168.07:38:19.27#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:38:19.27#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:38:19.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.168.07:38:19.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.168.07:38:19.27$vc4f8/valo=5,652.99 2006.168.07:38:19.27#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.168.07:38:19.27#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.168.07:38:19.27#ibcon#ireg 17 cls_cnt 0 2006.168.07:38:19.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:38:19.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:38:19.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:38:19.27#ibcon#enter wrdev, iclass 38, count 0 2006.168.07:38:19.27#ibcon#first serial, iclass 38, count 0 2006.168.07:38:19.27#ibcon#enter sib2, iclass 38, count 0 2006.168.07:38:19.27#ibcon#flushed, iclass 38, count 0 2006.168.07:38:19.27#ibcon#about to write, iclass 38, count 0 2006.168.07:38:19.27#ibcon#wrote, iclass 38, count 0 2006.168.07:38:19.27#ibcon#about to read 3, iclass 38, count 0 2006.168.07:38:19.29#ibcon#read 3, iclass 38, count 0 2006.168.07:38:19.29#ibcon#about to read 4, iclass 38, count 0 2006.168.07:38:19.29#ibcon#read 4, iclass 38, count 0 2006.168.07:38:19.29#ibcon#about to read 5, iclass 38, count 0 2006.168.07:38:19.29#ibcon#read 5, iclass 38, count 0 2006.168.07:38:19.29#ibcon#about to read 6, iclass 38, count 0 2006.168.07:38:19.29#ibcon#read 6, iclass 38, count 0 2006.168.07:38:19.29#ibcon#end of sib2, iclass 38, count 0 2006.168.07:38:19.29#ibcon#*mode == 0, iclass 38, count 0 2006.168.07:38:19.29#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.168.07:38:19.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.07:38:19.29#ibcon#*before write, iclass 38, count 0 2006.168.07:38:19.29#ibcon#enter sib2, iclass 38, count 0 2006.168.07:38:19.29#ibcon#flushed, iclass 38, count 0 2006.168.07:38:19.29#ibcon#about to write, iclass 38, count 0 2006.168.07:38:19.29#ibcon#wrote, iclass 38, count 0 2006.168.07:38:19.29#ibcon#about to read 3, iclass 38, count 0 2006.168.07:38:19.33#ibcon#read 3, iclass 38, count 0 2006.168.07:38:19.33#ibcon#about to read 4, iclass 38, count 0 2006.168.07:38:19.33#ibcon#read 4, iclass 38, count 0 2006.168.07:38:19.33#ibcon#about to read 5, iclass 38, count 0 2006.168.07:38:19.33#ibcon#read 5, iclass 38, count 0 2006.168.07:38:19.33#ibcon#about to read 6, iclass 38, count 0 2006.168.07:38:19.33#ibcon#read 6, iclass 38, count 0 2006.168.07:38:19.33#ibcon#end of sib2, iclass 38, count 0 2006.168.07:38:19.33#ibcon#*after write, iclass 38, count 0 2006.168.07:38:19.33#ibcon#*before return 0, iclass 38, count 0 2006.168.07:38:19.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:38:19.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:38:19.33#ibcon#about to clear, iclass 38 cls_cnt 0 2006.168.07:38:19.33#ibcon#cleared, iclass 38 cls_cnt 0 2006.168.07:38:19.33$vc4f8/va=5,7 2006.168.07:38:19.33#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.168.07:38:19.33#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.168.07:38:19.33#ibcon#ireg 11 cls_cnt 2 2006.168.07:38:19.33#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:38:19.39#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:38:19.39#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:38:19.39#ibcon#enter wrdev, iclass 40, count 2 2006.168.07:38:19.39#ibcon#first serial, iclass 40, count 2 2006.168.07:38:19.39#ibcon#enter sib2, iclass 40, count 2 2006.168.07:38:19.39#ibcon#flushed, iclass 40, count 2 2006.168.07:38:19.39#ibcon#about to write, iclass 40, count 2 2006.168.07:38:19.39#ibcon#wrote, iclass 40, count 2 2006.168.07:38:19.39#ibcon#about to read 3, iclass 40, count 2 2006.168.07:38:19.41#ibcon#read 3, iclass 40, count 2 2006.168.07:38:19.41#ibcon#about to read 4, iclass 40, count 2 2006.168.07:38:19.41#ibcon#read 4, iclass 40, count 2 2006.168.07:38:19.41#ibcon#about to read 5, iclass 40, count 2 2006.168.07:38:19.41#ibcon#read 5, iclass 40, count 2 2006.168.07:38:19.41#ibcon#about to read 6, iclass 40, count 2 2006.168.07:38:19.41#ibcon#read 6, iclass 40, count 2 2006.168.07:38:19.41#ibcon#end of sib2, iclass 40, count 2 2006.168.07:38:19.41#ibcon#*mode == 0, iclass 40, count 2 2006.168.07:38:19.41#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.168.07:38:19.41#ibcon#[25=AT05-07\r\n] 2006.168.07:38:19.41#ibcon#*before write, iclass 40, count 2 2006.168.07:38:19.41#ibcon#enter sib2, iclass 40, count 2 2006.168.07:38:19.41#ibcon#flushed, iclass 40, count 2 2006.168.07:38:19.41#ibcon#about to write, iclass 40, count 2 2006.168.07:38:19.41#ibcon#wrote, iclass 40, count 2 2006.168.07:38:19.41#ibcon#about to read 3, iclass 40, count 2 2006.168.07:38:19.44#ibcon#read 3, iclass 40, count 2 2006.168.07:38:19.44#ibcon#about to read 4, iclass 40, count 2 2006.168.07:38:19.44#ibcon#read 4, iclass 40, count 2 2006.168.07:38:19.44#ibcon#about to read 5, iclass 40, count 2 2006.168.07:38:19.44#ibcon#read 5, iclass 40, count 2 2006.168.07:38:19.44#ibcon#about to read 6, iclass 40, count 2 2006.168.07:38:19.44#ibcon#read 6, iclass 40, count 2 2006.168.07:38:19.44#ibcon#end of sib2, iclass 40, count 2 2006.168.07:38:19.44#ibcon#*after write, iclass 40, count 2 2006.168.07:38:19.44#ibcon#*before return 0, iclass 40, count 2 2006.168.07:38:19.44#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:38:19.44#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:38:19.44#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.168.07:38:19.44#ibcon#ireg 7 cls_cnt 0 2006.168.07:38:19.44#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:38:19.56#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:38:19.56#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:38:19.56#ibcon#enter wrdev, iclass 40, count 0 2006.168.07:38:19.56#ibcon#first serial, iclass 40, count 0 2006.168.07:38:19.56#ibcon#enter sib2, iclass 40, count 0 2006.168.07:38:19.56#ibcon#flushed, iclass 40, count 0 2006.168.07:38:19.56#ibcon#about to write, iclass 40, count 0 2006.168.07:38:19.56#ibcon#wrote, iclass 40, count 0 2006.168.07:38:19.56#ibcon#about to read 3, iclass 40, count 0 2006.168.07:38:19.58#ibcon#read 3, iclass 40, count 0 2006.168.07:38:19.58#ibcon#about to read 4, iclass 40, count 0 2006.168.07:38:19.58#ibcon#read 4, iclass 40, count 0 2006.168.07:38:19.58#ibcon#about to read 5, iclass 40, count 0 2006.168.07:38:19.58#ibcon#read 5, iclass 40, count 0 2006.168.07:38:19.58#ibcon#about to read 6, iclass 40, count 0 2006.168.07:38:19.58#ibcon#read 6, iclass 40, count 0 2006.168.07:38:19.58#ibcon#end of sib2, iclass 40, count 0 2006.168.07:38:19.58#ibcon#*mode == 0, iclass 40, count 0 2006.168.07:38:19.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.168.07:38:19.58#ibcon#[25=USB\r\n] 2006.168.07:38:19.58#ibcon#*before write, iclass 40, count 0 2006.168.07:38:19.58#ibcon#enter sib2, iclass 40, count 0 2006.168.07:38:19.58#ibcon#flushed, iclass 40, count 0 2006.168.07:38:19.58#ibcon#about to write, iclass 40, count 0 2006.168.07:38:19.58#ibcon#wrote, iclass 40, count 0 2006.168.07:38:19.58#ibcon#about to read 3, iclass 40, count 0 2006.168.07:38:19.61#ibcon#read 3, iclass 40, count 0 2006.168.07:38:19.61#ibcon#about to read 4, iclass 40, count 0 2006.168.07:38:19.61#ibcon#read 4, iclass 40, count 0 2006.168.07:38:19.61#ibcon#about to read 5, iclass 40, count 0 2006.168.07:38:19.61#ibcon#read 5, iclass 40, count 0 2006.168.07:38:19.61#ibcon#about to read 6, iclass 40, count 0 2006.168.07:38:19.61#ibcon#read 6, iclass 40, count 0 2006.168.07:38:19.61#ibcon#end of sib2, iclass 40, count 0 2006.168.07:38:19.61#ibcon#*after write, iclass 40, count 0 2006.168.07:38:19.61#ibcon#*before return 0, iclass 40, count 0 2006.168.07:38:19.61#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:38:19.61#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:38:19.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.168.07:38:19.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.168.07:38:19.61$vc4f8/valo=6,772.99 2006.168.07:38:19.61#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.168.07:38:19.61#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.168.07:38:19.61#ibcon#ireg 17 cls_cnt 0 2006.168.07:38:19.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:38:19.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:38:19.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:38:19.61#ibcon#enter wrdev, iclass 4, count 0 2006.168.07:38:19.61#ibcon#first serial, iclass 4, count 0 2006.168.07:38:19.61#ibcon#enter sib2, iclass 4, count 0 2006.168.07:38:19.61#ibcon#flushed, iclass 4, count 0 2006.168.07:38:19.61#ibcon#about to write, iclass 4, count 0 2006.168.07:38:19.61#ibcon#wrote, iclass 4, count 0 2006.168.07:38:19.61#ibcon#about to read 3, iclass 4, count 0 2006.168.07:38:19.63#ibcon#read 3, iclass 4, count 0 2006.168.07:38:19.63#ibcon#about to read 4, iclass 4, count 0 2006.168.07:38:19.63#ibcon#read 4, iclass 4, count 0 2006.168.07:38:19.63#ibcon#about to read 5, iclass 4, count 0 2006.168.07:38:19.63#ibcon#read 5, iclass 4, count 0 2006.168.07:38:19.63#ibcon#about to read 6, iclass 4, count 0 2006.168.07:38:19.63#ibcon#read 6, iclass 4, count 0 2006.168.07:38:19.63#ibcon#end of sib2, iclass 4, count 0 2006.168.07:38:19.63#ibcon#*mode == 0, iclass 4, count 0 2006.168.07:38:19.63#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.168.07:38:19.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.07:38:19.63#ibcon#*before write, iclass 4, count 0 2006.168.07:38:19.63#ibcon#enter sib2, iclass 4, count 0 2006.168.07:38:19.63#ibcon#flushed, iclass 4, count 0 2006.168.07:38:19.63#ibcon#about to write, iclass 4, count 0 2006.168.07:38:19.63#ibcon#wrote, iclass 4, count 0 2006.168.07:38:19.63#ibcon#about to read 3, iclass 4, count 0 2006.168.07:38:19.67#ibcon#read 3, iclass 4, count 0 2006.168.07:38:19.67#ibcon#about to read 4, iclass 4, count 0 2006.168.07:38:19.67#ibcon#read 4, iclass 4, count 0 2006.168.07:38:19.67#ibcon#about to read 5, iclass 4, count 0 2006.168.07:38:19.67#ibcon#read 5, iclass 4, count 0 2006.168.07:38:19.67#ibcon#about to read 6, iclass 4, count 0 2006.168.07:38:19.67#ibcon#read 6, iclass 4, count 0 2006.168.07:38:19.67#ibcon#end of sib2, iclass 4, count 0 2006.168.07:38:19.67#ibcon#*after write, iclass 4, count 0 2006.168.07:38:19.67#ibcon#*before return 0, iclass 4, count 0 2006.168.07:38:19.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:38:19.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:38:19.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.168.07:38:19.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.168.07:38:19.67$vc4f8/va=6,6 2006.168.07:38:19.67#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.168.07:38:19.67#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.168.07:38:19.67#ibcon#ireg 11 cls_cnt 2 2006.168.07:38:19.67#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:38:19.73#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:38:19.73#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:38:19.73#ibcon#enter wrdev, iclass 6, count 2 2006.168.07:38:19.73#ibcon#first serial, iclass 6, count 2 2006.168.07:38:19.73#ibcon#enter sib2, iclass 6, count 2 2006.168.07:38:19.73#ibcon#flushed, iclass 6, count 2 2006.168.07:38:19.73#ibcon#about to write, iclass 6, count 2 2006.168.07:38:19.73#ibcon#wrote, iclass 6, count 2 2006.168.07:38:19.73#ibcon#about to read 3, iclass 6, count 2 2006.168.07:38:19.75#ibcon#read 3, iclass 6, count 2 2006.168.07:38:19.75#ibcon#about to read 4, iclass 6, count 2 2006.168.07:38:19.75#ibcon#read 4, iclass 6, count 2 2006.168.07:38:19.75#ibcon#about to read 5, iclass 6, count 2 2006.168.07:38:19.75#ibcon#read 5, iclass 6, count 2 2006.168.07:38:19.75#ibcon#about to read 6, iclass 6, count 2 2006.168.07:38:19.75#ibcon#read 6, iclass 6, count 2 2006.168.07:38:19.75#ibcon#end of sib2, iclass 6, count 2 2006.168.07:38:19.75#ibcon#*mode == 0, iclass 6, count 2 2006.168.07:38:19.75#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.168.07:38:19.75#ibcon#[25=AT06-06\r\n] 2006.168.07:38:19.75#ibcon#*before write, iclass 6, count 2 2006.168.07:38:19.75#ibcon#enter sib2, iclass 6, count 2 2006.168.07:38:19.75#ibcon#flushed, iclass 6, count 2 2006.168.07:38:19.75#ibcon#about to write, iclass 6, count 2 2006.168.07:38:19.75#ibcon#wrote, iclass 6, count 2 2006.168.07:38:19.75#ibcon#about to read 3, iclass 6, count 2 2006.168.07:38:19.78#ibcon#read 3, iclass 6, count 2 2006.168.07:38:19.78#ibcon#about to read 4, iclass 6, count 2 2006.168.07:38:19.78#ibcon#read 4, iclass 6, count 2 2006.168.07:38:19.78#ibcon#about to read 5, iclass 6, count 2 2006.168.07:38:19.78#ibcon#read 5, iclass 6, count 2 2006.168.07:38:19.78#ibcon#about to read 6, iclass 6, count 2 2006.168.07:38:19.78#ibcon#read 6, iclass 6, count 2 2006.168.07:38:19.78#ibcon#end of sib2, iclass 6, count 2 2006.168.07:38:19.78#ibcon#*after write, iclass 6, count 2 2006.168.07:38:19.78#ibcon#*before return 0, iclass 6, count 2 2006.168.07:38:19.78#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:38:19.78#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:38:19.78#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.168.07:38:19.78#ibcon#ireg 7 cls_cnt 0 2006.168.07:38:19.78#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:38:19.90#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:38:19.90#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:38:19.90#ibcon#enter wrdev, iclass 6, count 0 2006.168.07:38:19.90#ibcon#first serial, iclass 6, count 0 2006.168.07:38:19.90#ibcon#enter sib2, iclass 6, count 0 2006.168.07:38:19.90#ibcon#flushed, iclass 6, count 0 2006.168.07:38:19.90#ibcon#about to write, iclass 6, count 0 2006.168.07:38:19.90#ibcon#wrote, iclass 6, count 0 2006.168.07:38:19.90#ibcon#about to read 3, iclass 6, count 0 2006.168.07:38:19.92#ibcon#read 3, iclass 6, count 0 2006.168.07:38:19.92#ibcon#about to read 4, iclass 6, count 0 2006.168.07:38:19.92#ibcon#read 4, iclass 6, count 0 2006.168.07:38:19.92#ibcon#about to read 5, iclass 6, count 0 2006.168.07:38:19.92#ibcon#read 5, iclass 6, count 0 2006.168.07:38:19.92#ibcon#about to read 6, iclass 6, count 0 2006.168.07:38:19.92#ibcon#read 6, iclass 6, count 0 2006.168.07:38:19.92#ibcon#end of sib2, iclass 6, count 0 2006.168.07:38:19.92#ibcon#*mode == 0, iclass 6, count 0 2006.168.07:38:19.92#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.168.07:38:19.92#ibcon#[25=USB\r\n] 2006.168.07:38:19.92#ibcon#*before write, iclass 6, count 0 2006.168.07:38:19.92#ibcon#enter sib2, iclass 6, count 0 2006.168.07:38:19.92#ibcon#flushed, iclass 6, count 0 2006.168.07:38:19.92#ibcon#about to write, iclass 6, count 0 2006.168.07:38:19.92#ibcon#wrote, iclass 6, count 0 2006.168.07:38:19.92#ibcon#about to read 3, iclass 6, count 0 2006.168.07:38:19.95#ibcon#read 3, iclass 6, count 0 2006.168.07:38:19.95#ibcon#about to read 4, iclass 6, count 0 2006.168.07:38:19.95#ibcon#read 4, iclass 6, count 0 2006.168.07:38:19.95#ibcon#about to read 5, iclass 6, count 0 2006.168.07:38:19.95#ibcon#read 5, iclass 6, count 0 2006.168.07:38:19.95#ibcon#about to read 6, iclass 6, count 0 2006.168.07:38:19.95#ibcon#read 6, iclass 6, count 0 2006.168.07:38:19.95#ibcon#end of sib2, iclass 6, count 0 2006.168.07:38:19.95#ibcon#*after write, iclass 6, count 0 2006.168.07:38:19.95#ibcon#*before return 0, iclass 6, count 0 2006.168.07:38:19.95#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:38:19.95#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:38:19.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.168.07:38:19.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.168.07:38:19.95$vc4f8/valo=7,832.99 2006.168.07:38:19.95#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.168.07:38:19.95#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.168.07:38:19.95#ibcon#ireg 17 cls_cnt 0 2006.168.07:38:19.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:38:19.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:38:19.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:38:19.95#ibcon#enter wrdev, iclass 10, count 0 2006.168.07:38:19.95#ibcon#first serial, iclass 10, count 0 2006.168.07:38:19.95#ibcon#enter sib2, iclass 10, count 0 2006.168.07:38:19.95#ibcon#flushed, iclass 10, count 0 2006.168.07:38:19.95#ibcon#about to write, iclass 10, count 0 2006.168.07:38:19.95#ibcon#wrote, iclass 10, count 0 2006.168.07:38:19.95#ibcon#about to read 3, iclass 10, count 0 2006.168.07:38:19.97#ibcon#read 3, iclass 10, count 0 2006.168.07:38:19.97#ibcon#about to read 4, iclass 10, count 0 2006.168.07:38:19.97#ibcon#read 4, iclass 10, count 0 2006.168.07:38:19.97#ibcon#about to read 5, iclass 10, count 0 2006.168.07:38:19.97#ibcon#read 5, iclass 10, count 0 2006.168.07:38:19.97#ibcon#about to read 6, iclass 10, count 0 2006.168.07:38:19.97#ibcon#read 6, iclass 10, count 0 2006.168.07:38:19.97#ibcon#end of sib2, iclass 10, count 0 2006.168.07:38:19.97#ibcon#*mode == 0, iclass 10, count 0 2006.168.07:38:19.97#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.168.07:38:19.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.07:38:19.97#ibcon#*before write, iclass 10, count 0 2006.168.07:38:19.97#ibcon#enter sib2, iclass 10, count 0 2006.168.07:38:19.97#ibcon#flushed, iclass 10, count 0 2006.168.07:38:19.97#ibcon#about to write, iclass 10, count 0 2006.168.07:38:19.97#ibcon#wrote, iclass 10, count 0 2006.168.07:38:19.97#ibcon#about to read 3, iclass 10, count 0 2006.168.07:38:20.01#ibcon#read 3, iclass 10, count 0 2006.168.07:38:20.01#ibcon#about to read 4, iclass 10, count 0 2006.168.07:38:20.01#ibcon#read 4, iclass 10, count 0 2006.168.07:38:20.01#ibcon#about to read 5, iclass 10, count 0 2006.168.07:38:20.01#ibcon#read 5, iclass 10, count 0 2006.168.07:38:20.01#ibcon#about to read 6, iclass 10, count 0 2006.168.07:38:20.01#ibcon#read 6, iclass 10, count 0 2006.168.07:38:20.01#ibcon#end of sib2, iclass 10, count 0 2006.168.07:38:20.01#ibcon#*after write, iclass 10, count 0 2006.168.07:38:20.01#ibcon#*before return 0, iclass 10, count 0 2006.168.07:38:20.01#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:38:20.01#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:38:20.01#ibcon#about to clear, iclass 10 cls_cnt 0 2006.168.07:38:20.01#ibcon#cleared, iclass 10 cls_cnt 0 2006.168.07:38:20.01$vc4f8/va=7,6 2006.168.07:38:20.01#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.168.07:38:20.01#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.168.07:38:20.01#ibcon#ireg 11 cls_cnt 2 2006.168.07:38:20.01#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:38:20.07#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:38:20.07#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:38:20.07#ibcon#enter wrdev, iclass 12, count 2 2006.168.07:38:20.07#ibcon#first serial, iclass 12, count 2 2006.168.07:38:20.07#ibcon#enter sib2, iclass 12, count 2 2006.168.07:38:20.07#ibcon#flushed, iclass 12, count 2 2006.168.07:38:20.07#ibcon#about to write, iclass 12, count 2 2006.168.07:38:20.07#ibcon#wrote, iclass 12, count 2 2006.168.07:38:20.07#ibcon#about to read 3, iclass 12, count 2 2006.168.07:38:20.09#ibcon#read 3, iclass 12, count 2 2006.168.07:38:20.09#ibcon#about to read 4, iclass 12, count 2 2006.168.07:38:20.09#ibcon#read 4, iclass 12, count 2 2006.168.07:38:20.09#ibcon#about to read 5, iclass 12, count 2 2006.168.07:38:20.09#ibcon#read 5, iclass 12, count 2 2006.168.07:38:20.09#ibcon#about to read 6, iclass 12, count 2 2006.168.07:38:20.09#ibcon#read 6, iclass 12, count 2 2006.168.07:38:20.09#ibcon#end of sib2, iclass 12, count 2 2006.168.07:38:20.09#ibcon#*mode == 0, iclass 12, count 2 2006.168.07:38:20.09#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.168.07:38:20.09#ibcon#[25=AT07-06\r\n] 2006.168.07:38:20.09#ibcon#*before write, iclass 12, count 2 2006.168.07:38:20.09#ibcon#enter sib2, iclass 12, count 2 2006.168.07:38:20.09#ibcon#flushed, iclass 12, count 2 2006.168.07:38:20.09#ibcon#about to write, iclass 12, count 2 2006.168.07:38:20.09#ibcon#wrote, iclass 12, count 2 2006.168.07:38:20.09#ibcon#about to read 3, iclass 12, count 2 2006.168.07:38:20.12#ibcon#read 3, iclass 12, count 2 2006.168.07:38:20.12#ibcon#about to read 4, iclass 12, count 2 2006.168.07:38:20.12#ibcon#read 4, iclass 12, count 2 2006.168.07:38:20.12#ibcon#about to read 5, iclass 12, count 2 2006.168.07:38:20.12#ibcon#read 5, iclass 12, count 2 2006.168.07:38:20.12#ibcon#about to read 6, iclass 12, count 2 2006.168.07:38:20.12#ibcon#read 6, iclass 12, count 2 2006.168.07:38:20.12#ibcon#end of sib2, iclass 12, count 2 2006.168.07:38:20.12#ibcon#*after write, iclass 12, count 2 2006.168.07:38:20.12#ibcon#*before return 0, iclass 12, count 2 2006.168.07:38:20.12#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:38:20.12#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:38:20.12#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.168.07:38:20.12#ibcon#ireg 7 cls_cnt 0 2006.168.07:38:20.12#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:38:20.24#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:38:20.24#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:38:20.24#ibcon#enter wrdev, iclass 12, count 0 2006.168.07:38:20.24#ibcon#first serial, iclass 12, count 0 2006.168.07:38:20.24#ibcon#enter sib2, iclass 12, count 0 2006.168.07:38:20.24#ibcon#flushed, iclass 12, count 0 2006.168.07:38:20.24#ibcon#about to write, iclass 12, count 0 2006.168.07:38:20.24#ibcon#wrote, iclass 12, count 0 2006.168.07:38:20.24#ibcon#about to read 3, iclass 12, count 0 2006.168.07:38:20.26#ibcon#read 3, iclass 12, count 0 2006.168.07:38:20.26#ibcon#about to read 4, iclass 12, count 0 2006.168.07:38:20.26#ibcon#read 4, iclass 12, count 0 2006.168.07:38:20.26#ibcon#about to read 5, iclass 12, count 0 2006.168.07:38:20.26#ibcon#read 5, iclass 12, count 0 2006.168.07:38:20.26#ibcon#about to read 6, iclass 12, count 0 2006.168.07:38:20.26#ibcon#read 6, iclass 12, count 0 2006.168.07:38:20.26#ibcon#end of sib2, iclass 12, count 0 2006.168.07:38:20.26#ibcon#*mode == 0, iclass 12, count 0 2006.168.07:38:20.26#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.168.07:38:20.26#ibcon#[25=USB\r\n] 2006.168.07:38:20.26#ibcon#*before write, iclass 12, count 0 2006.168.07:38:20.26#ibcon#enter sib2, iclass 12, count 0 2006.168.07:38:20.26#ibcon#flushed, iclass 12, count 0 2006.168.07:38:20.26#ibcon#about to write, iclass 12, count 0 2006.168.07:38:20.26#ibcon#wrote, iclass 12, count 0 2006.168.07:38:20.26#ibcon#about to read 3, iclass 12, count 0 2006.168.07:38:20.29#ibcon#read 3, iclass 12, count 0 2006.168.07:38:20.29#ibcon#about to read 4, iclass 12, count 0 2006.168.07:38:20.29#ibcon#read 4, iclass 12, count 0 2006.168.07:38:20.29#ibcon#about to read 5, iclass 12, count 0 2006.168.07:38:20.29#ibcon#read 5, iclass 12, count 0 2006.168.07:38:20.29#ibcon#about to read 6, iclass 12, count 0 2006.168.07:38:20.29#ibcon#read 6, iclass 12, count 0 2006.168.07:38:20.29#ibcon#end of sib2, iclass 12, count 0 2006.168.07:38:20.29#ibcon#*after write, iclass 12, count 0 2006.168.07:38:20.29#ibcon#*before return 0, iclass 12, count 0 2006.168.07:38:20.29#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:38:20.29#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:38:20.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.168.07:38:20.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.168.07:38:20.29$vc4f8/valo=8,852.99 2006.168.07:38:20.29#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.168.07:38:20.29#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.168.07:38:20.29#ibcon#ireg 17 cls_cnt 0 2006.168.07:38:20.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:38:20.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:38:20.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:38:20.29#ibcon#enter wrdev, iclass 14, count 0 2006.168.07:38:20.29#ibcon#first serial, iclass 14, count 0 2006.168.07:38:20.29#ibcon#enter sib2, iclass 14, count 0 2006.168.07:38:20.29#ibcon#flushed, iclass 14, count 0 2006.168.07:38:20.29#ibcon#about to write, iclass 14, count 0 2006.168.07:38:20.29#ibcon#wrote, iclass 14, count 0 2006.168.07:38:20.29#ibcon#about to read 3, iclass 14, count 0 2006.168.07:38:20.31#ibcon#read 3, iclass 14, count 0 2006.168.07:38:20.31#ibcon#about to read 4, iclass 14, count 0 2006.168.07:38:20.31#ibcon#read 4, iclass 14, count 0 2006.168.07:38:20.31#ibcon#about to read 5, iclass 14, count 0 2006.168.07:38:20.31#ibcon#read 5, iclass 14, count 0 2006.168.07:38:20.31#ibcon#about to read 6, iclass 14, count 0 2006.168.07:38:20.31#ibcon#read 6, iclass 14, count 0 2006.168.07:38:20.31#ibcon#end of sib2, iclass 14, count 0 2006.168.07:38:20.31#ibcon#*mode == 0, iclass 14, count 0 2006.168.07:38:20.31#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.168.07:38:20.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.07:38:20.31#ibcon#*before write, iclass 14, count 0 2006.168.07:38:20.31#ibcon#enter sib2, iclass 14, count 0 2006.168.07:38:20.31#ibcon#flushed, iclass 14, count 0 2006.168.07:38:20.31#ibcon#about to write, iclass 14, count 0 2006.168.07:38:20.31#ibcon#wrote, iclass 14, count 0 2006.168.07:38:20.31#ibcon#about to read 3, iclass 14, count 0 2006.168.07:38:20.35#ibcon#read 3, iclass 14, count 0 2006.168.07:38:20.35#ibcon#about to read 4, iclass 14, count 0 2006.168.07:38:20.35#ibcon#read 4, iclass 14, count 0 2006.168.07:38:20.35#ibcon#about to read 5, iclass 14, count 0 2006.168.07:38:20.35#ibcon#read 5, iclass 14, count 0 2006.168.07:38:20.35#ibcon#about to read 6, iclass 14, count 0 2006.168.07:38:20.35#ibcon#read 6, iclass 14, count 0 2006.168.07:38:20.35#ibcon#end of sib2, iclass 14, count 0 2006.168.07:38:20.35#ibcon#*after write, iclass 14, count 0 2006.168.07:38:20.35#ibcon#*before return 0, iclass 14, count 0 2006.168.07:38:20.35#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:38:20.35#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:38:20.35#ibcon#about to clear, iclass 14 cls_cnt 0 2006.168.07:38:20.35#ibcon#cleared, iclass 14 cls_cnt 0 2006.168.07:38:20.35$vc4f8/va=8,7 2006.168.07:38:20.35#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.168.07:38:20.35#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.168.07:38:20.35#ibcon#ireg 11 cls_cnt 2 2006.168.07:38:20.35#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:38:20.41#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:38:20.41#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:38:20.41#ibcon#enter wrdev, iclass 16, count 2 2006.168.07:38:20.41#ibcon#first serial, iclass 16, count 2 2006.168.07:38:20.41#ibcon#enter sib2, iclass 16, count 2 2006.168.07:38:20.41#ibcon#flushed, iclass 16, count 2 2006.168.07:38:20.41#ibcon#about to write, iclass 16, count 2 2006.168.07:38:20.41#ibcon#wrote, iclass 16, count 2 2006.168.07:38:20.41#ibcon#about to read 3, iclass 16, count 2 2006.168.07:38:20.43#ibcon#read 3, iclass 16, count 2 2006.168.07:38:20.43#ibcon#about to read 4, iclass 16, count 2 2006.168.07:38:20.43#ibcon#read 4, iclass 16, count 2 2006.168.07:38:20.43#ibcon#about to read 5, iclass 16, count 2 2006.168.07:38:20.43#ibcon#read 5, iclass 16, count 2 2006.168.07:38:20.43#ibcon#about to read 6, iclass 16, count 2 2006.168.07:38:20.43#ibcon#read 6, iclass 16, count 2 2006.168.07:38:20.43#ibcon#end of sib2, iclass 16, count 2 2006.168.07:38:20.43#ibcon#*mode == 0, iclass 16, count 2 2006.168.07:38:20.43#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.168.07:38:20.43#ibcon#[25=AT08-07\r\n] 2006.168.07:38:20.43#ibcon#*before write, iclass 16, count 2 2006.168.07:38:20.43#ibcon#enter sib2, iclass 16, count 2 2006.168.07:38:20.43#ibcon#flushed, iclass 16, count 2 2006.168.07:38:20.43#ibcon#about to write, iclass 16, count 2 2006.168.07:38:20.43#ibcon#wrote, iclass 16, count 2 2006.168.07:38:20.43#ibcon#about to read 3, iclass 16, count 2 2006.168.07:38:20.46#ibcon#read 3, iclass 16, count 2 2006.168.07:38:20.46#ibcon#about to read 4, iclass 16, count 2 2006.168.07:38:20.46#ibcon#read 4, iclass 16, count 2 2006.168.07:38:20.46#ibcon#about to read 5, iclass 16, count 2 2006.168.07:38:20.46#ibcon#read 5, iclass 16, count 2 2006.168.07:38:20.46#ibcon#about to read 6, iclass 16, count 2 2006.168.07:38:20.46#ibcon#read 6, iclass 16, count 2 2006.168.07:38:20.46#ibcon#end of sib2, iclass 16, count 2 2006.168.07:38:20.46#ibcon#*after write, iclass 16, count 2 2006.168.07:38:20.46#ibcon#*before return 0, iclass 16, count 2 2006.168.07:38:20.46#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:38:20.46#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:38:20.46#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.168.07:38:20.46#ibcon#ireg 7 cls_cnt 0 2006.168.07:38:20.46#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:38:20.58#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:38:20.58#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:38:20.58#ibcon#enter wrdev, iclass 16, count 0 2006.168.07:38:20.58#ibcon#first serial, iclass 16, count 0 2006.168.07:38:20.58#ibcon#enter sib2, iclass 16, count 0 2006.168.07:38:20.58#ibcon#flushed, iclass 16, count 0 2006.168.07:38:20.58#ibcon#about to write, iclass 16, count 0 2006.168.07:38:20.58#ibcon#wrote, iclass 16, count 0 2006.168.07:38:20.58#ibcon#about to read 3, iclass 16, count 0 2006.168.07:38:20.60#ibcon#read 3, iclass 16, count 0 2006.168.07:38:20.60#ibcon#about to read 4, iclass 16, count 0 2006.168.07:38:20.60#ibcon#read 4, iclass 16, count 0 2006.168.07:38:20.60#ibcon#about to read 5, iclass 16, count 0 2006.168.07:38:20.60#ibcon#read 5, iclass 16, count 0 2006.168.07:38:20.60#ibcon#about to read 6, iclass 16, count 0 2006.168.07:38:20.60#ibcon#read 6, iclass 16, count 0 2006.168.07:38:20.60#ibcon#end of sib2, iclass 16, count 0 2006.168.07:38:20.60#ibcon#*mode == 0, iclass 16, count 0 2006.168.07:38:20.60#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.168.07:38:20.60#ibcon#[25=USB\r\n] 2006.168.07:38:20.60#ibcon#*before write, iclass 16, count 0 2006.168.07:38:20.60#ibcon#enter sib2, iclass 16, count 0 2006.168.07:38:20.60#ibcon#flushed, iclass 16, count 0 2006.168.07:38:20.60#ibcon#about to write, iclass 16, count 0 2006.168.07:38:20.60#ibcon#wrote, iclass 16, count 0 2006.168.07:38:20.60#ibcon#about to read 3, iclass 16, count 0 2006.168.07:38:20.63#ibcon#read 3, iclass 16, count 0 2006.168.07:38:20.63#ibcon#about to read 4, iclass 16, count 0 2006.168.07:38:20.63#ibcon#read 4, iclass 16, count 0 2006.168.07:38:20.63#ibcon#about to read 5, iclass 16, count 0 2006.168.07:38:20.63#ibcon#read 5, iclass 16, count 0 2006.168.07:38:20.63#ibcon#about to read 6, iclass 16, count 0 2006.168.07:38:20.63#ibcon#read 6, iclass 16, count 0 2006.168.07:38:20.63#ibcon#end of sib2, iclass 16, count 0 2006.168.07:38:20.63#ibcon#*after write, iclass 16, count 0 2006.168.07:38:20.63#ibcon#*before return 0, iclass 16, count 0 2006.168.07:38:20.63#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:38:20.63#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:38:20.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.168.07:38:20.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.168.07:38:20.63$vc4f8/vblo=1,632.99 2006.168.07:38:20.63#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.168.07:38:20.63#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.168.07:38:20.63#ibcon#ireg 17 cls_cnt 0 2006.168.07:38:20.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:38:20.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:38:20.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:38:20.63#ibcon#enter wrdev, iclass 18, count 0 2006.168.07:38:20.63#ibcon#first serial, iclass 18, count 0 2006.168.07:38:20.63#ibcon#enter sib2, iclass 18, count 0 2006.168.07:38:20.63#ibcon#flushed, iclass 18, count 0 2006.168.07:38:20.63#ibcon#about to write, iclass 18, count 0 2006.168.07:38:20.63#ibcon#wrote, iclass 18, count 0 2006.168.07:38:20.63#ibcon#about to read 3, iclass 18, count 0 2006.168.07:38:20.65#ibcon#read 3, iclass 18, count 0 2006.168.07:38:20.65#ibcon#about to read 4, iclass 18, count 0 2006.168.07:38:20.65#ibcon#read 4, iclass 18, count 0 2006.168.07:38:20.65#ibcon#about to read 5, iclass 18, count 0 2006.168.07:38:20.65#ibcon#read 5, iclass 18, count 0 2006.168.07:38:20.65#ibcon#about to read 6, iclass 18, count 0 2006.168.07:38:20.65#ibcon#read 6, iclass 18, count 0 2006.168.07:38:20.65#ibcon#end of sib2, iclass 18, count 0 2006.168.07:38:20.65#ibcon#*mode == 0, iclass 18, count 0 2006.168.07:38:20.65#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.07:38:20.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.07:38:20.65#ibcon#*before write, iclass 18, count 0 2006.168.07:38:20.65#ibcon#enter sib2, iclass 18, count 0 2006.168.07:38:20.65#ibcon#flushed, iclass 18, count 0 2006.168.07:38:20.65#ibcon#about to write, iclass 18, count 0 2006.168.07:38:20.65#ibcon#wrote, iclass 18, count 0 2006.168.07:38:20.65#ibcon#about to read 3, iclass 18, count 0 2006.168.07:38:20.69#ibcon#read 3, iclass 18, count 0 2006.168.07:38:20.69#ibcon#about to read 4, iclass 18, count 0 2006.168.07:38:20.69#ibcon#read 4, iclass 18, count 0 2006.168.07:38:20.69#ibcon#about to read 5, iclass 18, count 0 2006.168.07:38:20.69#ibcon#read 5, iclass 18, count 0 2006.168.07:38:20.69#ibcon#about to read 6, iclass 18, count 0 2006.168.07:38:20.69#ibcon#read 6, iclass 18, count 0 2006.168.07:38:20.69#ibcon#end of sib2, iclass 18, count 0 2006.168.07:38:20.69#ibcon#*after write, iclass 18, count 0 2006.168.07:38:20.69#ibcon#*before return 0, iclass 18, count 0 2006.168.07:38:20.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:38:20.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:38:20.69#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.07:38:20.69#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.07:38:20.69$vc4f8/vb=1,4 2006.168.07:38:20.69#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.168.07:38:20.69#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.168.07:38:20.69#ibcon#ireg 11 cls_cnt 2 2006.168.07:38:20.69#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:38:20.69#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:38:20.69#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:38:20.69#ibcon#enter wrdev, iclass 20, count 2 2006.168.07:38:20.69#ibcon#first serial, iclass 20, count 2 2006.168.07:38:20.69#ibcon#enter sib2, iclass 20, count 2 2006.168.07:38:20.69#ibcon#flushed, iclass 20, count 2 2006.168.07:38:20.69#ibcon#about to write, iclass 20, count 2 2006.168.07:38:20.69#ibcon#wrote, iclass 20, count 2 2006.168.07:38:20.69#ibcon#about to read 3, iclass 20, count 2 2006.168.07:38:20.71#ibcon#read 3, iclass 20, count 2 2006.168.07:38:20.71#ibcon#about to read 4, iclass 20, count 2 2006.168.07:38:20.71#ibcon#read 4, iclass 20, count 2 2006.168.07:38:20.71#ibcon#about to read 5, iclass 20, count 2 2006.168.07:38:20.71#ibcon#read 5, iclass 20, count 2 2006.168.07:38:20.71#ibcon#about to read 6, iclass 20, count 2 2006.168.07:38:20.71#ibcon#read 6, iclass 20, count 2 2006.168.07:38:20.71#ibcon#end of sib2, iclass 20, count 2 2006.168.07:38:20.71#ibcon#*mode == 0, iclass 20, count 2 2006.168.07:38:20.71#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.168.07:38:20.71#ibcon#[27=AT01-04\r\n] 2006.168.07:38:20.71#ibcon#*before write, iclass 20, count 2 2006.168.07:38:20.71#ibcon#enter sib2, iclass 20, count 2 2006.168.07:38:20.71#ibcon#flushed, iclass 20, count 2 2006.168.07:38:20.71#ibcon#about to write, iclass 20, count 2 2006.168.07:38:20.71#ibcon#wrote, iclass 20, count 2 2006.168.07:38:20.71#ibcon#about to read 3, iclass 20, count 2 2006.168.07:38:20.74#ibcon#read 3, iclass 20, count 2 2006.168.07:38:20.74#ibcon#about to read 4, iclass 20, count 2 2006.168.07:38:20.74#ibcon#read 4, iclass 20, count 2 2006.168.07:38:20.74#ibcon#about to read 5, iclass 20, count 2 2006.168.07:38:20.74#ibcon#read 5, iclass 20, count 2 2006.168.07:38:20.74#ibcon#about to read 6, iclass 20, count 2 2006.168.07:38:20.74#ibcon#read 6, iclass 20, count 2 2006.168.07:38:20.74#ibcon#end of sib2, iclass 20, count 2 2006.168.07:38:20.74#ibcon#*after write, iclass 20, count 2 2006.168.07:38:20.74#ibcon#*before return 0, iclass 20, count 2 2006.168.07:38:20.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:38:20.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:38:20.74#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.168.07:38:20.74#ibcon#ireg 7 cls_cnt 0 2006.168.07:38:20.74#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:38:20.86#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:38:20.86#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:38:20.86#ibcon#enter wrdev, iclass 20, count 0 2006.168.07:38:20.86#ibcon#first serial, iclass 20, count 0 2006.168.07:38:20.86#ibcon#enter sib2, iclass 20, count 0 2006.168.07:38:20.86#ibcon#flushed, iclass 20, count 0 2006.168.07:38:20.86#ibcon#about to write, iclass 20, count 0 2006.168.07:38:20.86#ibcon#wrote, iclass 20, count 0 2006.168.07:38:20.86#ibcon#about to read 3, iclass 20, count 0 2006.168.07:38:20.88#ibcon#read 3, iclass 20, count 0 2006.168.07:38:20.88#ibcon#about to read 4, iclass 20, count 0 2006.168.07:38:20.88#ibcon#read 4, iclass 20, count 0 2006.168.07:38:20.88#ibcon#about to read 5, iclass 20, count 0 2006.168.07:38:20.88#ibcon#read 5, iclass 20, count 0 2006.168.07:38:20.88#ibcon#about to read 6, iclass 20, count 0 2006.168.07:38:20.88#ibcon#read 6, iclass 20, count 0 2006.168.07:38:20.88#ibcon#end of sib2, iclass 20, count 0 2006.168.07:38:20.88#ibcon#*mode == 0, iclass 20, count 0 2006.168.07:38:20.88#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.168.07:38:20.88#ibcon#[27=USB\r\n] 2006.168.07:38:20.88#ibcon#*before write, iclass 20, count 0 2006.168.07:38:20.88#ibcon#enter sib2, iclass 20, count 0 2006.168.07:38:20.88#ibcon#flushed, iclass 20, count 0 2006.168.07:38:20.88#ibcon#about to write, iclass 20, count 0 2006.168.07:38:20.88#ibcon#wrote, iclass 20, count 0 2006.168.07:38:20.88#ibcon#about to read 3, iclass 20, count 0 2006.168.07:38:20.91#ibcon#read 3, iclass 20, count 0 2006.168.07:38:20.91#ibcon#about to read 4, iclass 20, count 0 2006.168.07:38:20.91#ibcon#read 4, iclass 20, count 0 2006.168.07:38:20.91#ibcon#about to read 5, iclass 20, count 0 2006.168.07:38:20.91#ibcon#read 5, iclass 20, count 0 2006.168.07:38:20.91#ibcon#about to read 6, iclass 20, count 0 2006.168.07:38:20.91#ibcon#read 6, iclass 20, count 0 2006.168.07:38:20.91#ibcon#end of sib2, iclass 20, count 0 2006.168.07:38:20.91#ibcon#*after write, iclass 20, count 0 2006.168.07:38:20.91#ibcon#*before return 0, iclass 20, count 0 2006.168.07:38:20.91#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:38:20.91#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:38:20.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.168.07:38:20.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.168.07:38:20.91$vc4f8/vblo=2,640.99 2006.168.07:38:20.91#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.168.07:38:20.91#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.168.07:38:20.91#ibcon#ireg 17 cls_cnt 0 2006.168.07:38:20.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:38:20.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:38:20.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:38:20.91#ibcon#enter wrdev, iclass 22, count 0 2006.168.07:38:20.91#ibcon#first serial, iclass 22, count 0 2006.168.07:38:20.91#ibcon#enter sib2, iclass 22, count 0 2006.168.07:38:20.91#ibcon#flushed, iclass 22, count 0 2006.168.07:38:20.91#ibcon#about to write, iclass 22, count 0 2006.168.07:38:20.91#ibcon#wrote, iclass 22, count 0 2006.168.07:38:20.91#ibcon#about to read 3, iclass 22, count 0 2006.168.07:38:20.93#ibcon#read 3, iclass 22, count 0 2006.168.07:38:20.93#ibcon#about to read 4, iclass 22, count 0 2006.168.07:38:20.93#ibcon#read 4, iclass 22, count 0 2006.168.07:38:20.93#ibcon#about to read 5, iclass 22, count 0 2006.168.07:38:20.93#ibcon#read 5, iclass 22, count 0 2006.168.07:38:20.93#ibcon#about to read 6, iclass 22, count 0 2006.168.07:38:20.93#ibcon#read 6, iclass 22, count 0 2006.168.07:38:20.93#ibcon#end of sib2, iclass 22, count 0 2006.168.07:38:20.93#ibcon#*mode == 0, iclass 22, count 0 2006.168.07:38:20.93#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.168.07:38:20.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.07:38:20.93#ibcon#*before write, iclass 22, count 0 2006.168.07:38:20.93#ibcon#enter sib2, iclass 22, count 0 2006.168.07:38:20.93#ibcon#flushed, iclass 22, count 0 2006.168.07:38:20.93#ibcon#about to write, iclass 22, count 0 2006.168.07:38:20.93#ibcon#wrote, iclass 22, count 0 2006.168.07:38:20.93#ibcon#about to read 3, iclass 22, count 0 2006.168.07:38:20.97#ibcon#read 3, iclass 22, count 0 2006.168.07:38:20.97#ibcon#about to read 4, iclass 22, count 0 2006.168.07:38:20.97#ibcon#read 4, iclass 22, count 0 2006.168.07:38:20.97#ibcon#about to read 5, iclass 22, count 0 2006.168.07:38:20.97#ibcon#read 5, iclass 22, count 0 2006.168.07:38:20.97#ibcon#about to read 6, iclass 22, count 0 2006.168.07:38:20.97#ibcon#read 6, iclass 22, count 0 2006.168.07:38:20.97#ibcon#end of sib2, iclass 22, count 0 2006.168.07:38:20.97#ibcon#*after write, iclass 22, count 0 2006.168.07:38:20.97#ibcon#*before return 0, iclass 22, count 0 2006.168.07:38:20.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:38:20.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:38:20.97#ibcon#about to clear, iclass 22 cls_cnt 0 2006.168.07:38:20.97#ibcon#cleared, iclass 22 cls_cnt 0 2006.168.07:38:20.97$vc4f8/vb=2,4 2006.168.07:38:20.97#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.168.07:38:20.97#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.168.07:38:20.97#ibcon#ireg 11 cls_cnt 2 2006.168.07:38:20.97#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:38:21.03#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:38:21.03#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:38:21.03#ibcon#enter wrdev, iclass 24, count 2 2006.168.07:38:21.03#ibcon#first serial, iclass 24, count 2 2006.168.07:38:21.03#ibcon#enter sib2, iclass 24, count 2 2006.168.07:38:21.03#ibcon#flushed, iclass 24, count 2 2006.168.07:38:21.03#ibcon#about to write, iclass 24, count 2 2006.168.07:38:21.03#ibcon#wrote, iclass 24, count 2 2006.168.07:38:21.03#ibcon#about to read 3, iclass 24, count 2 2006.168.07:38:21.05#ibcon#read 3, iclass 24, count 2 2006.168.07:38:21.05#ibcon#about to read 4, iclass 24, count 2 2006.168.07:38:21.05#ibcon#read 4, iclass 24, count 2 2006.168.07:38:21.05#ibcon#about to read 5, iclass 24, count 2 2006.168.07:38:21.05#ibcon#read 5, iclass 24, count 2 2006.168.07:38:21.05#ibcon#about to read 6, iclass 24, count 2 2006.168.07:38:21.05#ibcon#read 6, iclass 24, count 2 2006.168.07:38:21.05#ibcon#end of sib2, iclass 24, count 2 2006.168.07:38:21.05#ibcon#*mode == 0, iclass 24, count 2 2006.168.07:38:21.05#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.168.07:38:21.05#ibcon#[27=AT02-04\r\n] 2006.168.07:38:21.05#ibcon#*before write, iclass 24, count 2 2006.168.07:38:21.05#ibcon#enter sib2, iclass 24, count 2 2006.168.07:38:21.05#ibcon#flushed, iclass 24, count 2 2006.168.07:38:21.05#ibcon#about to write, iclass 24, count 2 2006.168.07:38:21.05#ibcon#wrote, iclass 24, count 2 2006.168.07:38:21.05#ibcon#about to read 3, iclass 24, count 2 2006.168.07:38:21.08#ibcon#read 3, iclass 24, count 2 2006.168.07:38:21.08#ibcon#about to read 4, iclass 24, count 2 2006.168.07:38:21.08#ibcon#read 4, iclass 24, count 2 2006.168.07:38:21.08#ibcon#about to read 5, iclass 24, count 2 2006.168.07:38:21.08#ibcon#read 5, iclass 24, count 2 2006.168.07:38:21.08#ibcon#about to read 6, iclass 24, count 2 2006.168.07:38:21.08#ibcon#read 6, iclass 24, count 2 2006.168.07:38:21.08#ibcon#end of sib2, iclass 24, count 2 2006.168.07:38:21.08#ibcon#*after write, iclass 24, count 2 2006.168.07:38:21.08#ibcon#*before return 0, iclass 24, count 2 2006.168.07:38:21.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:38:21.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:38:21.08#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.168.07:38:21.08#ibcon#ireg 7 cls_cnt 0 2006.168.07:38:21.08#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:38:21.20#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:38:21.20#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:38:21.20#ibcon#enter wrdev, iclass 24, count 0 2006.168.07:38:21.20#ibcon#first serial, iclass 24, count 0 2006.168.07:38:21.20#ibcon#enter sib2, iclass 24, count 0 2006.168.07:38:21.20#ibcon#flushed, iclass 24, count 0 2006.168.07:38:21.20#ibcon#about to write, iclass 24, count 0 2006.168.07:38:21.20#ibcon#wrote, iclass 24, count 0 2006.168.07:38:21.20#ibcon#about to read 3, iclass 24, count 0 2006.168.07:38:21.22#ibcon#read 3, iclass 24, count 0 2006.168.07:38:21.22#ibcon#about to read 4, iclass 24, count 0 2006.168.07:38:21.22#ibcon#read 4, iclass 24, count 0 2006.168.07:38:21.22#ibcon#about to read 5, iclass 24, count 0 2006.168.07:38:21.22#ibcon#read 5, iclass 24, count 0 2006.168.07:38:21.22#ibcon#about to read 6, iclass 24, count 0 2006.168.07:38:21.22#ibcon#read 6, iclass 24, count 0 2006.168.07:38:21.22#ibcon#end of sib2, iclass 24, count 0 2006.168.07:38:21.22#ibcon#*mode == 0, iclass 24, count 0 2006.168.07:38:21.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.168.07:38:21.22#ibcon#[27=USB\r\n] 2006.168.07:38:21.22#ibcon#*before write, iclass 24, count 0 2006.168.07:38:21.22#ibcon#enter sib2, iclass 24, count 0 2006.168.07:38:21.22#ibcon#flushed, iclass 24, count 0 2006.168.07:38:21.22#ibcon#about to write, iclass 24, count 0 2006.168.07:38:21.22#ibcon#wrote, iclass 24, count 0 2006.168.07:38:21.22#ibcon#about to read 3, iclass 24, count 0 2006.168.07:38:21.25#ibcon#read 3, iclass 24, count 0 2006.168.07:38:21.25#ibcon#about to read 4, iclass 24, count 0 2006.168.07:38:21.25#ibcon#read 4, iclass 24, count 0 2006.168.07:38:21.25#ibcon#about to read 5, iclass 24, count 0 2006.168.07:38:21.25#ibcon#read 5, iclass 24, count 0 2006.168.07:38:21.25#ibcon#about to read 6, iclass 24, count 0 2006.168.07:38:21.25#ibcon#read 6, iclass 24, count 0 2006.168.07:38:21.25#ibcon#end of sib2, iclass 24, count 0 2006.168.07:38:21.25#ibcon#*after write, iclass 24, count 0 2006.168.07:38:21.25#ibcon#*before return 0, iclass 24, count 0 2006.168.07:38:21.25#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:38:21.25#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:38:21.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.168.07:38:21.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.168.07:38:21.25$vc4f8/vblo=3,656.99 2006.168.07:38:21.25#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.168.07:38:21.25#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.168.07:38:21.25#ibcon#ireg 17 cls_cnt 0 2006.168.07:38:21.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:38:21.25#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:38:21.25#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:38:21.25#ibcon#enter wrdev, iclass 26, count 0 2006.168.07:38:21.25#ibcon#first serial, iclass 26, count 0 2006.168.07:38:21.25#ibcon#enter sib2, iclass 26, count 0 2006.168.07:38:21.25#ibcon#flushed, iclass 26, count 0 2006.168.07:38:21.25#ibcon#about to write, iclass 26, count 0 2006.168.07:38:21.25#ibcon#wrote, iclass 26, count 0 2006.168.07:38:21.25#ibcon#about to read 3, iclass 26, count 0 2006.168.07:38:21.27#ibcon#read 3, iclass 26, count 0 2006.168.07:38:21.27#ibcon#about to read 4, iclass 26, count 0 2006.168.07:38:21.27#ibcon#read 4, iclass 26, count 0 2006.168.07:38:21.27#ibcon#about to read 5, iclass 26, count 0 2006.168.07:38:21.27#ibcon#read 5, iclass 26, count 0 2006.168.07:38:21.27#ibcon#about to read 6, iclass 26, count 0 2006.168.07:38:21.27#ibcon#read 6, iclass 26, count 0 2006.168.07:38:21.27#ibcon#end of sib2, iclass 26, count 0 2006.168.07:38:21.27#ibcon#*mode == 0, iclass 26, count 0 2006.168.07:38:21.27#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.168.07:38:21.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.07:38:21.27#ibcon#*before write, iclass 26, count 0 2006.168.07:38:21.27#ibcon#enter sib2, iclass 26, count 0 2006.168.07:38:21.27#ibcon#flushed, iclass 26, count 0 2006.168.07:38:21.27#ibcon#about to write, iclass 26, count 0 2006.168.07:38:21.27#ibcon#wrote, iclass 26, count 0 2006.168.07:38:21.27#ibcon#about to read 3, iclass 26, count 0 2006.168.07:38:21.31#ibcon#read 3, iclass 26, count 0 2006.168.07:38:21.31#ibcon#about to read 4, iclass 26, count 0 2006.168.07:38:21.31#ibcon#read 4, iclass 26, count 0 2006.168.07:38:21.31#ibcon#about to read 5, iclass 26, count 0 2006.168.07:38:21.31#ibcon#read 5, iclass 26, count 0 2006.168.07:38:21.31#ibcon#about to read 6, iclass 26, count 0 2006.168.07:38:21.31#ibcon#read 6, iclass 26, count 0 2006.168.07:38:21.31#ibcon#end of sib2, iclass 26, count 0 2006.168.07:38:21.31#ibcon#*after write, iclass 26, count 0 2006.168.07:38:21.31#ibcon#*before return 0, iclass 26, count 0 2006.168.07:38:21.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:38:21.31#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:38:21.31#ibcon#about to clear, iclass 26 cls_cnt 0 2006.168.07:38:21.31#ibcon#cleared, iclass 26 cls_cnt 0 2006.168.07:38:21.31$vc4f8/vb=3,4 2006.168.07:38:21.31#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.168.07:38:21.31#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.168.07:38:21.31#ibcon#ireg 11 cls_cnt 2 2006.168.07:38:21.31#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.168.07:38:21.37#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.168.07:38:21.37#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.168.07:38:21.37#ibcon#enter wrdev, iclass 28, count 2 2006.168.07:38:21.37#ibcon#first serial, iclass 28, count 2 2006.168.07:38:21.37#ibcon#enter sib2, iclass 28, count 2 2006.168.07:38:21.37#ibcon#flushed, iclass 28, count 2 2006.168.07:38:21.37#ibcon#about to write, iclass 28, count 2 2006.168.07:38:21.37#ibcon#wrote, iclass 28, count 2 2006.168.07:38:21.37#ibcon#about to read 3, iclass 28, count 2 2006.168.07:38:21.39#ibcon#read 3, iclass 28, count 2 2006.168.07:38:21.39#ibcon#about to read 4, iclass 28, count 2 2006.168.07:38:21.39#ibcon#read 4, iclass 28, count 2 2006.168.07:38:21.39#ibcon#about to read 5, iclass 28, count 2 2006.168.07:38:21.39#ibcon#read 5, iclass 28, count 2 2006.168.07:38:21.39#ibcon#about to read 6, iclass 28, count 2 2006.168.07:38:21.39#ibcon#read 6, iclass 28, count 2 2006.168.07:38:21.39#ibcon#end of sib2, iclass 28, count 2 2006.168.07:38:21.39#ibcon#*mode == 0, iclass 28, count 2 2006.168.07:38:21.39#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.168.07:38:21.39#ibcon#[27=AT03-04\r\n] 2006.168.07:38:21.39#ibcon#*before write, iclass 28, count 2 2006.168.07:38:21.39#ibcon#enter sib2, iclass 28, count 2 2006.168.07:38:21.39#ibcon#flushed, iclass 28, count 2 2006.168.07:38:21.39#ibcon#about to write, iclass 28, count 2 2006.168.07:38:21.39#ibcon#wrote, iclass 28, count 2 2006.168.07:38:21.39#ibcon#about to read 3, iclass 28, count 2 2006.168.07:38:21.42#ibcon#read 3, iclass 28, count 2 2006.168.07:38:21.42#ibcon#about to read 4, iclass 28, count 2 2006.168.07:38:21.42#ibcon#read 4, iclass 28, count 2 2006.168.07:38:21.42#ibcon#about to read 5, iclass 28, count 2 2006.168.07:38:21.42#ibcon#read 5, iclass 28, count 2 2006.168.07:38:21.42#ibcon#about to read 6, iclass 28, count 2 2006.168.07:38:21.42#ibcon#read 6, iclass 28, count 2 2006.168.07:38:21.42#ibcon#end of sib2, iclass 28, count 2 2006.168.07:38:21.42#ibcon#*after write, iclass 28, count 2 2006.168.07:38:21.42#ibcon#*before return 0, iclass 28, count 2 2006.168.07:38:21.42#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.168.07:38:21.42#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.168.07:38:21.42#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.168.07:38:21.42#ibcon#ireg 7 cls_cnt 0 2006.168.07:38:21.42#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.168.07:38:21.54#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.168.07:38:21.54#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.168.07:38:21.54#ibcon#enter wrdev, iclass 28, count 0 2006.168.07:38:21.54#ibcon#first serial, iclass 28, count 0 2006.168.07:38:21.54#ibcon#enter sib2, iclass 28, count 0 2006.168.07:38:21.54#ibcon#flushed, iclass 28, count 0 2006.168.07:38:21.54#ibcon#about to write, iclass 28, count 0 2006.168.07:38:21.54#ibcon#wrote, iclass 28, count 0 2006.168.07:38:21.54#ibcon#about to read 3, iclass 28, count 0 2006.168.07:38:21.56#ibcon#read 3, iclass 28, count 0 2006.168.07:38:21.56#ibcon#about to read 4, iclass 28, count 0 2006.168.07:38:21.56#ibcon#read 4, iclass 28, count 0 2006.168.07:38:21.56#ibcon#about to read 5, iclass 28, count 0 2006.168.07:38:21.56#ibcon#read 5, iclass 28, count 0 2006.168.07:38:21.56#ibcon#about to read 6, iclass 28, count 0 2006.168.07:38:21.56#ibcon#read 6, iclass 28, count 0 2006.168.07:38:21.56#ibcon#end of sib2, iclass 28, count 0 2006.168.07:38:21.56#ibcon#*mode == 0, iclass 28, count 0 2006.168.07:38:21.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.168.07:38:21.56#ibcon#[27=USB\r\n] 2006.168.07:38:21.56#ibcon#*before write, iclass 28, count 0 2006.168.07:38:21.56#ibcon#enter sib2, iclass 28, count 0 2006.168.07:38:21.56#ibcon#flushed, iclass 28, count 0 2006.168.07:38:21.56#ibcon#about to write, iclass 28, count 0 2006.168.07:38:21.56#ibcon#wrote, iclass 28, count 0 2006.168.07:38:21.56#ibcon#about to read 3, iclass 28, count 0 2006.168.07:38:21.59#ibcon#read 3, iclass 28, count 0 2006.168.07:38:21.59#ibcon#about to read 4, iclass 28, count 0 2006.168.07:38:21.59#ibcon#read 4, iclass 28, count 0 2006.168.07:38:21.59#ibcon#about to read 5, iclass 28, count 0 2006.168.07:38:21.59#ibcon#read 5, iclass 28, count 0 2006.168.07:38:21.59#ibcon#about to read 6, iclass 28, count 0 2006.168.07:38:21.59#ibcon#read 6, iclass 28, count 0 2006.168.07:38:21.59#ibcon#end of sib2, iclass 28, count 0 2006.168.07:38:21.59#ibcon#*after write, iclass 28, count 0 2006.168.07:38:21.59#ibcon#*before return 0, iclass 28, count 0 2006.168.07:38:21.59#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.168.07:38:21.59#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.168.07:38:21.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.168.07:38:21.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.168.07:38:21.59$vc4f8/vblo=4,712.99 2006.168.07:38:21.59#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.168.07:38:21.59#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.168.07:38:21.59#ibcon#ireg 17 cls_cnt 0 2006.168.07:38:21.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:38:21.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:38:21.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:38:21.59#ibcon#enter wrdev, iclass 30, count 0 2006.168.07:38:21.59#ibcon#first serial, iclass 30, count 0 2006.168.07:38:21.59#ibcon#enter sib2, iclass 30, count 0 2006.168.07:38:21.59#ibcon#flushed, iclass 30, count 0 2006.168.07:38:21.59#ibcon#about to write, iclass 30, count 0 2006.168.07:38:21.59#ibcon#wrote, iclass 30, count 0 2006.168.07:38:21.59#ibcon#about to read 3, iclass 30, count 0 2006.168.07:38:21.61#ibcon#read 3, iclass 30, count 0 2006.168.07:38:21.61#ibcon#about to read 4, iclass 30, count 0 2006.168.07:38:21.61#ibcon#read 4, iclass 30, count 0 2006.168.07:38:21.61#ibcon#about to read 5, iclass 30, count 0 2006.168.07:38:21.61#ibcon#read 5, iclass 30, count 0 2006.168.07:38:21.61#ibcon#about to read 6, iclass 30, count 0 2006.168.07:38:21.61#ibcon#read 6, iclass 30, count 0 2006.168.07:38:21.61#ibcon#end of sib2, iclass 30, count 0 2006.168.07:38:21.61#ibcon#*mode == 0, iclass 30, count 0 2006.168.07:38:21.61#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.168.07:38:21.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.07:38:21.61#ibcon#*before write, iclass 30, count 0 2006.168.07:38:21.61#ibcon#enter sib2, iclass 30, count 0 2006.168.07:38:21.61#ibcon#flushed, iclass 30, count 0 2006.168.07:38:21.61#ibcon#about to write, iclass 30, count 0 2006.168.07:38:21.61#ibcon#wrote, iclass 30, count 0 2006.168.07:38:21.61#ibcon#about to read 3, iclass 30, count 0 2006.168.07:38:21.65#ibcon#read 3, iclass 30, count 0 2006.168.07:38:21.65#ibcon#about to read 4, iclass 30, count 0 2006.168.07:38:21.65#ibcon#read 4, iclass 30, count 0 2006.168.07:38:21.65#ibcon#about to read 5, iclass 30, count 0 2006.168.07:38:21.65#ibcon#read 5, iclass 30, count 0 2006.168.07:38:21.65#ibcon#about to read 6, iclass 30, count 0 2006.168.07:38:21.65#ibcon#read 6, iclass 30, count 0 2006.168.07:38:21.65#ibcon#end of sib2, iclass 30, count 0 2006.168.07:38:21.65#ibcon#*after write, iclass 30, count 0 2006.168.07:38:21.65#ibcon#*before return 0, iclass 30, count 0 2006.168.07:38:21.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:38:21.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:38:21.65#ibcon#about to clear, iclass 30 cls_cnt 0 2006.168.07:38:21.65#ibcon#cleared, iclass 30 cls_cnt 0 2006.168.07:38:21.65$vc4f8/vb=4,4 2006.168.07:38:21.65#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.168.07:38:21.65#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.168.07:38:21.65#ibcon#ireg 11 cls_cnt 2 2006.168.07:38:21.65#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:38:21.71#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:38:21.71#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:38:21.71#ibcon#enter wrdev, iclass 32, count 2 2006.168.07:38:21.71#ibcon#first serial, iclass 32, count 2 2006.168.07:38:21.71#ibcon#enter sib2, iclass 32, count 2 2006.168.07:38:21.71#ibcon#flushed, iclass 32, count 2 2006.168.07:38:21.71#ibcon#about to write, iclass 32, count 2 2006.168.07:38:21.71#ibcon#wrote, iclass 32, count 2 2006.168.07:38:21.71#ibcon#about to read 3, iclass 32, count 2 2006.168.07:38:21.73#ibcon#read 3, iclass 32, count 2 2006.168.07:38:21.73#ibcon#about to read 4, iclass 32, count 2 2006.168.07:38:21.73#ibcon#read 4, iclass 32, count 2 2006.168.07:38:21.73#ibcon#about to read 5, iclass 32, count 2 2006.168.07:38:21.73#ibcon#read 5, iclass 32, count 2 2006.168.07:38:21.73#ibcon#about to read 6, iclass 32, count 2 2006.168.07:38:21.73#ibcon#read 6, iclass 32, count 2 2006.168.07:38:21.73#ibcon#end of sib2, iclass 32, count 2 2006.168.07:38:21.73#ibcon#*mode == 0, iclass 32, count 2 2006.168.07:38:21.73#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.168.07:38:21.73#ibcon#[27=AT04-04\r\n] 2006.168.07:38:21.73#ibcon#*before write, iclass 32, count 2 2006.168.07:38:21.73#ibcon#enter sib2, iclass 32, count 2 2006.168.07:38:21.73#ibcon#flushed, iclass 32, count 2 2006.168.07:38:21.73#ibcon#about to write, iclass 32, count 2 2006.168.07:38:21.73#ibcon#wrote, iclass 32, count 2 2006.168.07:38:21.73#ibcon#about to read 3, iclass 32, count 2 2006.168.07:38:21.76#ibcon#read 3, iclass 32, count 2 2006.168.07:38:21.76#ibcon#about to read 4, iclass 32, count 2 2006.168.07:38:21.76#ibcon#read 4, iclass 32, count 2 2006.168.07:38:21.76#ibcon#about to read 5, iclass 32, count 2 2006.168.07:38:21.76#ibcon#read 5, iclass 32, count 2 2006.168.07:38:21.76#ibcon#about to read 6, iclass 32, count 2 2006.168.07:38:21.76#ibcon#read 6, iclass 32, count 2 2006.168.07:38:21.76#ibcon#end of sib2, iclass 32, count 2 2006.168.07:38:21.76#ibcon#*after write, iclass 32, count 2 2006.168.07:38:21.76#ibcon#*before return 0, iclass 32, count 2 2006.168.07:38:21.76#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:38:21.76#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:38:21.76#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.168.07:38:21.76#ibcon#ireg 7 cls_cnt 0 2006.168.07:38:21.76#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:38:21.88#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:38:21.88#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:38:21.88#ibcon#enter wrdev, iclass 32, count 0 2006.168.07:38:21.88#ibcon#first serial, iclass 32, count 0 2006.168.07:38:21.88#ibcon#enter sib2, iclass 32, count 0 2006.168.07:38:21.88#ibcon#flushed, iclass 32, count 0 2006.168.07:38:21.88#ibcon#about to write, iclass 32, count 0 2006.168.07:38:21.88#ibcon#wrote, iclass 32, count 0 2006.168.07:38:21.88#ibcon#about to read 3, iclass 32, count 0 2006.168.07:38:21.90#ibcon#read 3, iclass 32, count 0 2006.168.07:38:21.90#ibcon#about to read 4, iclass 32, count 0 2006.168.07:38:21.90#ibcon#read 4, iclass 32, count 0 2006.168.07:38:21.90#ibcon#about to read 5, iclass 32, count 0 2006.168.07:38:21.90#ibcon#read 5, iclass 32, count 0 2006.168.07:38:21.90#ibcon#about to read 6, iclass 32, count 0 2006.168.07:38:21.90#ibcon#read 6, iclass 32, count 0 2006.168.07:38:21.90#ibcon#end of sib2, iclass 32, count 0 2006.168.07:38:21.90#ibcon#*mode == 0, iclass 32, count 0 2006.168.07:38:21.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.168.07:38:21.90#ibcon#[27=USB\r\n] 2006.168.07:38:21.90#ibcon#*before write, iclass 32, count 0 2006.168.07:38:21.90#ibcon#enter sib2, iclass 32, count 0 2006.168.07:38:21.90#ibcon#flushed, iclass 32, count 0 2006.168.07:38:21.90#ibcon#about to write, iclass 32, count 0 2006.168.07:38:21.90#ibcon#wrote, iclass 32, count 0 2006.168.07:38:21.90#ibcon#about to read 3, iclass 32, count 0 2006.168.07:38:21.93#ibcon#read 3, iclass 32, count 0 2006.168.07:38:21.93#ibcon#about to read 4, iclass 32, count 0 2006.168.07:38:21.93#ibcon#read 4, iclass 32, count 0 2006.168.07:38:21.93#ibcon#about to read 5, iclass 32, count 0 2006.168.07:38:21.93#ibcon#read 5, iclass 32, count 0 2006.168.07:38:21.93#ibcon#about to read 6, iclass 32, count 0 2006.168.07:38:21.93#ibcon#read 6, iclass 32, count 0 2006.168.07:38:21.93#ibcon#end of sib2, iclass 32, count 0 2006.168.07:38:21.93#ibcon#*after write, iclass 32, count 0 2006.168.07:38:21.93#ibcon#*before return 0, iclass 32, count 0 2006.168.07:38:21.93#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:38:21.93#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:38:21.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.168.07:38:21.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.168.07:38:21.93$vc4f8/vblo=5,744.99 2006.168.07:38:21.93#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.168.07:38:21.93#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.168.07:38:21.93#ibcon#ireg 17 cls_cnt 0 2006.168.07:38:21.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:38:21.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:38:21.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:38:21.93#ibcon#enter wrdev, iclass 34, count 0 2006.168.07:38:21.93#ibcon#first serial, iclass 34, count 0 2006.168.07:38:21.93#ibcon#enter sib2, iclass 34, count 0 2006.168.07:38:21.93#ibcon#flushed, iclass 34, count 0 2006.168.07:38:21.93#ibcon#about to write, iclass 34, count 0 2006.168.07:38:21.93#ibcon#wrote, iclass 34, count 0 2006.168.07:38:21.93#ibcon#about to read 3, iclass 34, count 0 2006.168.07:38:21.95#ibcon#read 3, iclass 34, count 0 2006.168.07:38:21.95#ibcon#about to read 4, iclass 34, count 0 2006.168.07:38:21.95#ibcon#read 4, iclass 34, count 0 2006.168.07:38:21.95#ibcon#about to read 5, iclass 34, count 0 2006.168.07:38:21.95#ibcon#read 5, iclass 34, count 0 2006.168.07:38:21.95#ibcon#about to read 6, iclass 34, count 0 2006.168.07:38:21.95#ibcon#read 6, iclass 34, count 0 2006.168.07:38:21.95#ibcon#end of sib2, iclass 34, count 0 2006.168.07:38:21.95#ibcon#*mode == 0, iclass 34, count 0 2006.168.07:38:21.95#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.168.07:38:21.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.07:38:21.95#ibcon#*before write, iclass 34, count 0 2006.168.07:38:21.95#ibcon#enter sib2, iclass 34, count 0 2006.168.07:38:21.95#ibcon#flushed, iclass 34, count 0 2006.168.07:38:21.95#ibcon#about to write, iclass 34, count 0 2006.168.07:38:21.95#ibcon#wrote, iclass 34, count 0 2006.168.07:38:21.95#ibcon#about to read 3, iclass 34, count 0 2006.168.07:38:21.99#ibcon#read 3, iclass 34, count 0 2006.168.07:38:21.99#ibcon#about to read 4, iclass 34, count 0 2006.168.07:38:21.99#ibcon#read 4, iclass 34, count 0 2006.168.07:38:21.99#ibcon#about to read 5, iclass 34, count 0 2006.168.07:38:21.99#ibcon#read 5, iclass 34, count 0 2006.168.07:38:21.99#ibcon#about to read 6, iclass 34, count 0 2006.168.07:38:21.99#ibcon#read 6, iclass 34, count 0 2006.168.07:38:21.99#ibcon#end of sib2, iclass 34, count 0 2006.168.07:38:21.99#ibcon#*after write, iclass 34, count 0 2006.168.07:38:21.99#ibcon#*before return 0, iclass 34, count 0 2006.168.07:38:21.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:38:21.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:38:21.99#ibcon#about to clear, iclass 34 cls_cnt 0 2006.168.07:38:21.99#ibcon#cleared, iclass 34 cls_cnt 0 2006.168.07:38:21.99$vc4f8/vb=5,4 2006.168.07:38:21.99#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.168.07:38:21.99#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.168.07:38:21.99#ibcon#ireg 11 cls_cnt 2 2006.168.07:38:21.99#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:38:22.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:38:22.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:38:22.05#ibcon#enter wrdev, iclass 36, count 2 2006.168.07:38:22.05#ibcon#first serial, iclass 36, count 2 2006.168.07:38:22.05#ibcon#enter sib2, iclass 36, count 2 2006.168.07:38:22.05#ibcon#flushed, iclass 36, count 2 2006.168.07:38:22.05#ibcon#about to write, iclass 36, count 2 2006.168.07:38:22.05#ibcon#wrote, iclass 36, count 2 2006.168.07:38:22.05#ibcon#about to read 3, iclass 36, count 2 2006.168.07:38:22.07#ibcon#read 3, iclass 36, count 2 2006.168.07:38:22.07#ibcon#about to read 4, iclass 36, count 2 2006.168.07:38:22.07#ibcon#read 4, iclass 36, count 2 2006.168.07:38:22.07#ibcon#about to read 5, iclass 36, count 2 2006.168.07:38:22.07#ibcon#read 5, iclass 36, count 2 2006.168.07:38:22.07#ibcon#about to read 6, iclass 36, count 2 2006.168.07:38:22.07#ibcon#read 6, iclass 36, count 2 2006.168.07:38:22.07#ibcon#end of sib2, iclass 36, count 2 2006.168.07:38:22.07#ibcon#*mode == 0, iclass 36, count 2 2006.168.07:38:22.07#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.168.07:38:22.07#ibcon#[27=AT05-04\r\n] 2006.168.07:38:22.07#ibcon#*before write, iclass 36, count 2 2006.168.07:38:22.07#ibcon#enter sib2, iclass 36, count 2 2006.168.07:38:22.07#ibcon#flushed, iclass 36, count 2 2006.168.07:38:22.07#ibcon#about to write, iclass 36, count 2 2006.168.07:38:22.07#ibcon#wrote, iclass 36, count 2 2006.168.07:38:22.07#ibcon#about to read 3, iclass 36, count 2 2006.168.07:38:22.10#ibcon#read 3, iclass 36, count 2 2006.168.07:38:22.10#ibcon#about to read 4, iclass 36, count 2 2006.168.07:38:22.10#ibcon#read 4, iclass 36, count 2 2006.168.07:38:22.10#ibcon#about to read 5, iclass 36, count 2 2006.168.07:38:22.10#ibcon#read 5, iclass 36, count 2 2006.168.07:38:22.10#ibcon#about to read 6, iclass 36, count 2 2006.168.07:38:22.10#ibcon#read 6, iclass 36, count 2 2006.168.07:38:22.10#ibcon#end of sib2, iclass 36, count 2 2006.168.07:38:22.10#ibcon#*after write, iclass 36, count 2 2006.168.07:38:22.10#ibcon#*before return 0, iclass 36, count 2 2006.168.07:38:22.10#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:38:22.10#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:38:22.10#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.168.07:38:22.10#ibcon#ireg 7 cls_cnt 0 2006.168.07:38:22.10#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:38:22.22#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:38:22.22#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:38:22.22#ibcon#enter wrdev, iclass 36, count 0 2006.168.07:38:22.22#ibcon#first serial, iclass 36, count 0 2006.168.07:38:22.22#ibcon#enter sib2, iclass 36, count 0 2006.168.07:38:22.22#ibcon#flushed, iclass 36, count 0 2006.168.07:38:22.22#ibcon#about to write, iclass 36, count 0 2006.168.07:38:22.22#ibcon#wrote, iclass 36, count 0 2006.168.07:38:22.22#ibcon#about to read 3, iclass 36, count 0 2006.168.07:38:22.24#ibcon#read 3, iclass 36, count 0 2006.168.07:38:22.24#ibcon#about to read 4, iclass 36, count 0 2006.168.07:38:22.24#ibcon#read 4, iclass 36, count 0 2006.168.07:38:22.24#ibcon#about to read 5, iclass 36, count 0 2006.168.07:38:22.24#ibcon#read 5, iclass 36, count 0 2006.168.07:38:22.24#ibcon#about to read 6, iclass 36, count 0 2006.168.07:38:22.24#ibcon#read 6, iclass 36, count 0 2006.168.07:38:22.24#ibcon#end of sib2, iclass 36, count 0 2006.168.07:38:22.24#ibcon#*mode == 0, iclass 36, count 0 2006.168.07:38:22.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.168.07:38:22.24#ibcon#[27=USB\r\n] 2006.168.07:38:22.24#ibcon#*before write, iclass 36, count 0 2006.168.07:38:22.24#ibcon#enter sib2, iclass 36, count 0 2006.168.07:38:22.24#ibcon#flushed, iclass 36, count 0 2006.168.07:38:22.24#ibcon#about to write, iclass 36, count 0 2006.168.07:38:22.24#ibcon#wrote, iclass 36, count 0 2006.168.07:38:22.24#ibcon#about to read 3, iclass 36, count 0 2006.168.07:38:22.27#ibcon#read 3, iclass 36, count 0 2006.168.07:38:22.27#ibcon#about to read 4, iclass 36, count 0 2006.168.07:38:22.27#ibcon#read 4, iclass 36, count 0 2006.168.07:38:22.27#ibcon#about to read 5, iclass 36, count 0 2006.168.07:38:22.27#ibcon#read 5, iclass 36, count 0 2006.168.07:38:22.27#ibcon#about to read 6, iclass 36, count 0 2006.168.07:38:22.27#ibcon#read 6, iclass 36, count 0 2006.168.07:38:22.27#ibcon#end of sib2, iclass 36, count 0 2006.168.07:38:22.27#ibcon#*after write, iclass 36, count 0 2006.168.07:38:22.27#ibcon#*before return 0, iclass 36, count 0 2006.168.07:38:22.27#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:38:22.27#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:38:22.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.168.07:38:22.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.168.07:38:22.27$vc4f8/vblo=6,752.99 2006.168.07:38:22.27#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.168.07:38:22.27#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.168.07:38:22.27#ibcon#ireg 17 cls_cnt 0 2006.168.07:38:22.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:38:22.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:38:22.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:38:22.27#ibcon#enter wrdev, iclass 38, count 0 2006.168.07:38:22.27#ibcon#first serial, iclass 38, count 0 2006.168.07:38:22.27#ibcon#enter sib2, iclass 38, count 0 2006.168.07:38:22.27#ibcon#flushed, iclass 38, count 0 2006.168.07:38:22.27#ibcon#about to write, iclass 38, count 0 2006.168.07:38:22.27#ibcon#wrote, iclass 38, count 0 2006.168.07:38:22.27#ibcon#about to read 3, iclass 38, count 0 2006.168.07:38:22.29#ibcon#read 3, iclass 38, count 0 2006.168.07:38:22.29#ibcon#about to read 4, iclass 38, count 0 2006.168.07:38:22.29#ibcon#read 4, iclass 38, count 0 2006.168.07:38:22.29#ibcon#about to read 5, iclass 38, count 0 2006.168.07:38:22.29#ibcon#read 5, iclass 38, count 0 2006.168.07:38:22.29#ibcon#about to read 6, iclass 38, count 0 2006.168.07:38:22.29#ibcon#read 6, iclass 38, count 0 2006.168.07:38:22.29#ibcon#end of sib2, iclass 38, count 0 2006.168.07:38:22.29#ibcon#*mode == 0, iclass 38, count 0 2006.168.07:38:22.29#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.168.07:38:22.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.07:38:22.29#ibcon#*before write, iclass 38, count 0 2006.168.07:38:22.29#ibcon#enter sib2, iclass 38, count 0 2006.168.07:38:22.29#ibcon#flushed, iclass 38, count 0 2006.168.07:38:22.29#ibcon#about to write, iclass 38, count 0 2006.168.07:38:22.29#ibcon#wrote, iclass 38, count 0 2006.168.07:38:22.29#ibcon#about to read 3, iclass 38, count 0 2006.168.07:38:22.33#ibcon#read 3, iclass 38, count 0 2006.168.07:38:22.33#ibcon#about to read 4, iclass 38, count 0 2006.168.07:38:22.33#ibcon#read 4, iclass 38, count 0 2006.168.07:38:22.33#ibcon#about to read 5, iclass 38, count 0 2006.168.07:38:22.33#ibcon#read 5, iclass 38, count 0 2006.168.07:38:22.33#ibcon#about to read 6, iclass 38, count 0 2006.168.07:38:22.33#ibcon#read 6, iclass 38, count 0 2006.168.07:38:22.33#ibcon#end of sib2, iclass 38, count 0 2006.168.07:38:22.33#ibcon#*after write, iclass 38, count 0 2006.168.07:38:22.33#ibcon#*before return 0, iclass 38, count 0 2006.168.07:38:22.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:38:22.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:38:22.33#ibcon#about to clear, iclass 38 cls_cnt 0 2006.168.07:38:22.33#ibcon#cleared, iclass 38 cls_cnt 0 2006.168.07:38:22.33$vc4f8/vb=6,4 2006.168.07:38:22.33#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.168.07:38:22.33#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.168.07:38:22.33#ibcon#ireg 11 cls_cnt 2 2006.168.07:38:22.33#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:38:22.39#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:38:22.39#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:38:22.39#ibcon#enter wrdev, iclass 40, count 2 2006.168.07:38:22.39#ibcon#first serial, iclass 40, count 2 2006.168.07:38:22.39#ibcon#enter sib2, iclass 40, count 2 2006.168.07:38:22.39#ibcon#flushed, iclass 40, count 2 2006.168.07:38:22.39#ibcon#about to write, iclass 40, count 2 2006.168.07:38:22.39#ibcon#wrote, iclass 40, count 2 2006.168.07:38:22.39#ibcon#about to read 3, iclass 40, count 2 2006.168.07:38:22.41#ibcon#read 3, iclass 40, count 2 2006.168.07:38:22.41#ibcon#about to read 4, iclass 40, count 2 2006.168.07:38:22.41#ibcon#read 4, iclass 40, count 2 2006.168.07:38:22.41#ibcon#about to read 5, iclass 40, count 2 2006.168.07:38:22.41#ibcon#read 5, iclass 40, count 2 2006.168.07:38:22.41#ibcon#about to read 6, iclass 40, count 2 2006.168.07:38:22.41#ibcon#read 6, iclass 40, count 2 2006.168.07:38:22.41#ibcon#end of sib2, iclass 40, count 2 2006.168.07:38:22.41#ibcon#*mode == 0, iclass 40, count 2 2006.168.07:38:22.41#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.168.07:38:22.41#ibcon#[27=AT06-04\r\n] 2006.168.07:38:22.41#ibcon#*before write, iclass 40, count 2 2006.168.07:38:22.41#ibcon#enter sib2, iclass 40, count 2 2006.168.07:38:22.41#ibcon#flushed, iclass 40, count 2 2006.168.07:38:22.41#ibcon#about to write, iclass 40, count 2 2006.168.07:38:22.41#ibcon#wrote, iclass 40, count 2 2006.168.07:38:22.41#ibcon#about to read 3, iclass 40, count 2 2006.168.07:38:22.44#ibcon#read 3, iclass 40, count 2 2006.168.07:38:22.44#ibcon#about to read 4, iclass 40, count 2 2006.168.07:38:22.44#ibcon#read 4, iclass 40, count 2 2006.168.07:38:22.44#ibcon#about to read 5, iclass 40, count 2 2006.168.07:38:22.44#ibcon#read 5, iclass 40, count 2 2006.168.07:38:22.44#ibcon#about to read 6, iclass 40, count 2 2006.168.07:38:22.44#ibcon#read 6, iclass 40, count 2 2006.168.07:38:22.44#ibcon#end of sib2, iclass 40, count 2 2006.168.07:38:22.44#ibcon#*after write, iclass 40, count 2 2006.168.07:38:22.44#ibcon#*before return 0, iclass 40, count 2 2006.168.07:38:22.44#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:38:22.44#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:38:22.44#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.168.07:38:22.44#ibcon#ireg 7 cls_cnt 0 2006.168.07:38:22.44#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:38:22.56#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:38:22.56#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:38:22.56#ibcon#enter wrdev, iclass 40, count 0 2006.168.07:38:22.56#ibcon#first serial, iclass 40, count 0 2006.168.07:38:22.56#ibcon#enter sib2, iclass 40, count 0 2006.168.07:38:22.56#ibcon#flushed, iclass 40, count 0 2006.168.07:38:22.56#ibcon#about to write, iclass 40, count 0 2006.168.07:38:22.56#ibcon#wrote, iclass 40, count 0 2006.168.07:38:22.56#ibcon#about to read 3, iclass 40, count 0 2006.168.07:38:22.58#ibcon#read 3, iclass 40, count 0 2006.168.07:38:22.58#ibcon#about to read 4, iclass 40, count 0 2006.168.07:38:22.58#ibcon#read 4, iclass 40, count 0 2006.168.07:38:22.58#ibcon#about to read 5, iclass 40, count 0 2006.168.07:38:22.58#ibcon#read 5, iclass 40, count 0 2006.168.07:38:22.58#ibcon#about to read 6, iclass 40, count 0 2006.168.07:38:22.58#ibcon#read 6, iclass 40, count 0 2006.168.07:38:22.58#ibcon#end of sib2, iclass 40, count 0 2006.168.07:38:22.58#ibcon#*mode == 0, iclass 40, count 0 2006.168.07:38:22.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.168.07:38:22.58#ibcon#[27=USB\r\n] 2006.168.07:38:22.58#ibcon#*before write, iclass 40, count 0 2006.168.07:38:22.58#ibcon#enter sib2, iclass 40, count 0 2006.168.07:38:22.58#ibcon#flushed, iclass 40, count 0 2006.168.07:38:22.58#ibcon#about to write, iclass 40, count 0 2006.168.07:38:22.58#ibcon#wrote, iclass 40, count 0 2006.168.07:38:22.58#ibcon#about to read 3, iclass 40, count 0 2006.168.07:38:22.61#ibcon#read 3, iclass 40, count 0 2006.168.07:38:22.61#ibcon#about to read 4, iclass 40, count 0 2006.168.07:38:22.61#ibcon#read 4, iclass 40, count 0 2006.168.07:38:22.61#ibcon#about to read 5, iclass 40, count 0 2006.168.07:38:22.61#ibcon#read 5, iclass 40, count 0 2006.168.07:38:22.61#ibcon#about to read 6, iclass 40, count 0 2006.168.07:38:22.61#ibcon#read 6, iclass 40, count 0 2006.168.07:38:22.61#ibcon#end of sib2, iclass 40, count 0 2006.168.07:38:22.61#ibcon#*after write, iclass 40, count 0 2006.168.07:38:22.61#ibcon#*before return 0, iclass 40, count 0 2006.168.07:38:22.61#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:38:22.61#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:38:22.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.168.07:38:22.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.168.07:38:22.61$vc4f8/vabw=wide 2006.168.07:38:22.61#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.168.07:38:22.61#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.168.07:38:22.61#ibcon#ireg 8 cls_cnt 0 2006.168.07:38:22.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:38:22.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:38:22.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:38:22.61#ibcon#enter wrdev, iclass 4, count 0 2006.168.07:38:22.61#ibcon#first serial, iclass 4, count 0 2006.168.07:38:22.61#ibcon#enter sib2, iclass 4, count 0 2006.168.07:38:22.61#ibcon#flushed, iclass 4, count 0 2006.168.07:38:22.61#ibcon#about to write, iclass 4, count 0 2006.168.07:38:22.61#ibcon#wrote, iclass 4, count 0 2006.168.07:38:22.61#ibcon#about to read 3, iclass 4, count 0 2006.168.07:38:22.63#ibcon#read 3, iclass 4, count 0 2006.168.07:38:22.63#ibcon#about to read 4, iclass 4, count 0 2006.168.07:38:22.63#ibcon#read 4, iclass 4, count 0 2006.168.07:38:22.63#ibcon#about to read 5, iclass 4, count 0 2006.168.07:38:22.63#ibcon#read 5, iclass 4, count 0 2006.168.07:38:22.63#ibcon#about to read 6, iclass 4, count 0 2006.168.07:38:22.63#ibcon#read 6, iclass 4, count 0 2006.168.07:38:22.63#ibcon#end of sib2, iclass 4, count 0 2006.168.07:38:22.63#ibcon#*mode == 0, iclass 4, count 0 2006.168.07:38:22.63#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.168.07:38:22.63#ibcon#[25=BW32\r\n] 2006.168.07:38:22.63#ibcon#*before write, iclass 4, count 0 2006.168.07:38:22.63#ibcon#enter sib2, iclass 4, count 0 2006.168.07:38:22.63#ibcon#flushed, iclass 4, count 0 2006.168.07:38:22.63#ibcon#about to write, iclass 4, count 0 2006.168.07:38:22.63#ibcon#wrote, iclass 4, count 0 2006.168.07:38:22.63#ibcon#about to read 3, iclass 4, count 0 2006.168.07:38:22.66#abcon#<5=/08 1.9 5.7 27.79 721004.6\r\n> 2006.168.07:38:22.66#ibcon#read 3, iclass 4, count 0 2006.168.07:38:22.66#ibcon#about to read 4, iclass 4, count 0 2006.168.07:38:22.66#ibcon#read 4, iclass 4, count 0 2006.168.07:38:22.66#ibcon#about to read 5, iclass 4, count 0 2006.168.07:38:22.66#ibcon#read 5, iclass 4, count 0 2006.168.07:38:22.66#ibcon#about to read 6, iclass 4, count 0 2006.168.07:38:22.66#ibcon#read 6, iclass 4, count 0 2006.168.07:38:22.66#ibcon#end of sib2, iclass 4, count 0 2006.168.07:38:22.66#ibcon#*after write, iclass 4, count 0 2006.168.07:38:22.66#ibcon#*before return 0, iclass 4, count 0 2006.168.07:38:22.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:38:22.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:38:22.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.168.07:38:22.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.168.07:38:22.66$vc4f8/vbbw=wide 2006.168.07:38:22.66#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.168.07:38:22.66#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.168.07:38:22.66#ibcon#ireg 8 cls_cnt 0 2006.168.07:38:22.66#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.168.07:38:22.68#abcon#{5=INTERFACE CLEAR} 2006.168.07:38:22.73#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.168.07:38:22.73#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.168.07:38:22.73#ibcon#enter wrdev, iclass 11, count 0 2006.168.07:38:22.73#ibcon#first serial, iclass 11, count 0 2006.168.07:38:22.73#ibcon#enter sib2, iclass 11, count 0 2006.168.07:38:22.73#ibcon#flushed, iclass 11, count 0 2006.168.07:38:22.73#ibcon#about to write, iclass 11, count 0 2006.168.07:38:22.73#ibcon#wrote, iclass 11, count 0 2006.168.07:38:22.73#ibcon#about to read 3, iclass 11, count 0 2006.168.07:38:22.74#abcon#[5=S1D000X0/0*\r\n] 2006.168.07:38:22.75#ibcon#read 3, iclass 11, count 0 2006.168.07:38:22.75#ibcon#about to read 4, iclass 11, count 0 2006.168.07:38:22.75#ibcon#read 4, iclass 11, count 0 2006.168.07:38:22.75#ibcon#about to read 5, iclass 11, count 0 2006.168.07:38:22.75#ibcon#read 5, iclass 11, count 0 2006.168.07:38:22.75#ibcon#about to read 6, iclass 11, count 0 2006.168.07:38:22.75#ibcon#read 6, iclass 11, count 0 2006.168.07:38:22.75#ibcon#end of sib2, iclass 11, count 0 2006.168.07:38:22.75#ibcon#*mode == 0, iclass 11, count 0 2006.168.07:38:22.75#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.168.07:38:22.75#ibcon#[27=BW32\r\n] 2006.168.07:38:22.75#ibcon#*before write, iclass 11, count 0 2006.168.07:38:22.75#ibcon#enter sib2, iclass 11, count 0 2006.168.07:38:22.75#ibcon#flushed, iclass 11, count 0 2006.168.07:38:22.75#ibcon#about to write, iclass 11, count 0 2006.168.07:38:22.75#ibcon#wrote, iclass 11, count 0 2006.168.07:38:22.75#ibcon#about to read 3, iclass 11, count 0 2006.168.07:38:22.78#ibcon#read 3, iclass 11, count 0 2006.168.07:38:22.78#ibcon#about to read 4, iclass 11, count 0 2006.168.07:38:22.78#ibcon#read 4, iclass 11, count 0 2006.168.07:38:22.78#ibcon#about to read 5, iclass 11, count 0 2006.168.07:38:22.78#ibcon#read 5, iclass 11, count 0 2006.168.07:38:22.78#ibcon#about to read 6, iclass 11, count 0 2006.168.07:38:22.78#ibcon#read 6, iclass 11, count 0 2006.168.07:38:22.78#ibcon#end of sib2, iclass 11, count 0 2006.168.07:38:22.78#ibcon#*after write, iclass 11, count 0 2006.168.07:38:22.78#ibcon#*before return 0, iclass 11, count 0 2006.168.07:38:22.78#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.168.07:38:22.78#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.168.07:38:22.78#ibcon#about to clear, iclass 11 cls_cnt 0 2006.168.07:38:22.78#ibcon#cleared, iclass 11 cls_cnt 0 2006.168.07:38:22.78$4f8m12a/ifd4f 2006.168.07:38:22.78$ifd4f/lo= 2006.168.07:38:22.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.07:38:22.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.07:38:22.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.07:38:22.78$ifd4f/patch= 2006.168.07:38:22.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.07:38:22.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.07:38:22.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.07:38:22.78$4f8m12a/"form=m,16.000,1:2 2006.168.07:38:22.78$4f8m12a/"tpicd 2006.168.07:38:22.78$4f8m12a/echo=off 2006.168.07:38:22.78$4f8m12a/xlog=off 2006.168.07:38:22.78:!2006.168.07:38:50 2006.168.07:38:32.14#trakl#Source acquired 2006.168.07:38:32.14#flagr#flagr/antenna,acquired 2006.168.07:38:50.00:preob 2006.168.07:38:51.14/onsource/TRACKING 2006.168.07:38:51.14:!2006.168.07:39:00 2006.168.07:39:00.00:data_valid=on 2006.168.07:39:00.00:midob 2006.168.07:39:00.14/onsource/TRACKING 2006.168.07:39:00.14/wx/27.77,1004.6,71 2006.168.07:39:00.26/cable/+6.4704E-03 2006.168.07:39:01.35/va/01,08,usb,yes,29,31 2006.168.07:39:01.35/va/02,07,usb,yes,29,31 2006.168.07:39:01.35/va/03,06,usb,yes,31,31 2006.168.07:39:01.35/va/04,07,usb,yes,30,32 2006.168.07:39:01.35/va/05,07,usb,yes,29,31 2006.168.07:39:01.35/va/06,06,usb,yes,29,28 2006.168.07:39:01.35/va/07,06,usb,yes,29,29 2006.168.07:39:01.35/va/08,07,usb,yes,28,27 2006.168.07:39:01.58/valo/01,532.99,yes,locked 2006.168.07:39:01.58/valo/02,572.99,yes,locked 2006.168.07:39:01.58/valo/03,672.99,yes,locked 2006.168.07:39:01.58/valo/04,832.99,yes,locked 2006.168.07:39:01.58/valo/05,652.99,yes,locked 2006.168.07:39:01.58/valo/06,772.99,yes,locked 2006.168.07:39:01.58/valo/07,832.99,yes,locked 2006.168.07:39:01.58/valo/08,852.99,yes,locked 2006.168.07:39:02.67/vb/01,04,usb,yes,29,28 2006.168.07:39:02.67/vb/02,04,usb,yes,31,32 2006.168.07:39:02.67/vb/03,04,usb,yes,27,31 2006.168.07:39:02.67/vb/04,04,usb,yes,28,28 2006.168.07:39:02.67/vb/05,04,usb,yes,27,31 2006.168.07:39:02.67/vb/06,04,usb,yes,28,30 2006.168.07:39:02.67/vb/07,04,usb,yes,30,29 2006.168.07:39:02.67/vb/08,04,usb,yes,27,31 2006.168.07:39:02.90/vblo/01,632.99,yes,locked 2006.168.07:39:02.90/vblo/02,640.99,yes,locked 2006.168.07:39:02.90/vblo/03,656.99,yes,locked 2006.168.07:39:02.90/vblo/04,712.99,yes,locked 2006.168.07:39:02.90/vblo/05,744.99,yes,locked 2006.168.07:39:02.90/vblo/06,752.99,yes,locked 2006.168.07:39:02.90/vblo/07,734.99,yes,locked 2006.168.07:39:02.90/vblo/08,744.99,yes,locked 2006.168.07:39:03.05/vabw/8 2006.168.07:39:03.20/vbbw/8 2006.168.07:39:03.29/xfe/off,on,15.0 2006.168.07:39:03.66/ifatt/23,28,28,28 2006.168.07:39:04.08/fmout-gps/S +4.20E-07 2006.168.07:39:04.16:!2006.168.07:40:00 2006.168.07:40:00.00:data_valid=off 2006.168.07:40:00.00:postob 2006.168.07:40:00.18/cable/+6.4723E-03 2006.168.07:40:00.22/wx/27.73,1004.6,71 2006.168.07:40:01.08/fmout-gps/S +4.19E-07 2006.168.07:40:01.08:scan_name=168-0740,k06168,60 2006.168.07:40:01.08:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.168.07:40:01.14#flagr#flagr/antenna,new-source 2006.168.07:40:02.14:checkk5 2006.168.07:40:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.168.07:40:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.168.07:40:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.168.07:40:03.65/chk_autoobs//k5ts4/ autoobs is running! 2006.168.07:40:04.03/chk_obsdata//k5ts1/T1680739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:40:04.40/chk_obsdata//k5ts2/T1680739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:40:04.78/chk_obsdata//k5ts3/T1680739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:40:05.15/chk_obsdata//k5ts4/T1680739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:40:05.83/k5log//k5ts1_log_newline 2006.168.07:40:06.53/k5log//k5ts2_log_newline 2006.168.07:40:07.21/k5log//k5ts3_log_newline 2006.168.07:40:07.90/k5log//k5ts4_log_newline 2006.168.07:40:07.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.07:40:07.93:4f8m12a=1 2006.168.07:40:07.93$4f8m12a/echo=on 2006.168.07:40:07.93$4f8m12a/pcalon 2006.168.07:40:07.93$pcalon/"no phase cal control is implemented here 2006.168.07:40:07.93$4f8m12a/"tpicd=stop 2006.168.07:40:07.93$4f8m12a/vc4f8 2006.168.07:40:07.93$vc4f8/valo=1,532.99 2006.168.07:40:07.94#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.168.07:40:07.94#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.168.07:40:07.94#ibcon#ireg 17 cls_cnt 0 2006.168.07:40:07.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:40:07.94#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:40:07.94#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:40:07.94#ibcon#enter wrdev, iclass 19, count 0 2006.168.07:40:07.94#ibcon#first serial, iclass 19, count 0 2006.168.07:40:07.94#ibcon#enter sib2, iclass 19, count 0 2006.168.07:40:07.94#ibcon#flushed, iclass 19, count 0 2006.168.07:40:07.94#ibcon#about to write, iclass 19, count 0 2006.168.07:40:07.94#ibcon#wrote, iclass 19, count 0 2006.168.07:40:07.94#ibcon#about to read 3, iclass 19, count 0 2006.168.07:40:07.97#ibcon#read 3, iclass 19, count 0 2006.168.07:40:07.97#ibcon#about to read 4, iclass 19, count 0 2006.168.07:40:07.97#ibcon#read 4, iclass 19, count 0 2006.168.07:40:07.97#ibcon#about to read 5, iclass 19, count 0 2006.168.07:40:07.97#ibcon#read 5, iclass 19, count 0 2006.168.07:40:07.97#ibcon#about to read 6, iclass 19, count 0 2006.168.07:40:07.97#ibcon#read 6, iclass 19, count 0 2006.168.07:40:07.97#ibcon#end of sib2, iclass 19, count 0 2006.168.07:40:07.97#ibcon#*mode == 0, iclass 19, count 0 2006.168.07:40:07.97#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.168.07:40:07.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.07:40:07.97#ibcon#*before write, iclass 19, count 0 2006.168.07:40:07.97#ibcon#enter sib2, iclass 19, count 0 2006.168.07:40:07.97#ibcon#flushed, iclass 19, count 0 2006.168.07:40:07.97#ibcon#about to write, iclass 19, count 0 2006.168.07:40:07.97#ibcon#wrote, iclass 19, count 0 2006.168.07:40:07.97#ibcon#about to read 3, iclass 19, count 0 2006.168.07:40:08.02#ibcon#read 3, iclass 19, count 0 2006.168.07:40:08.02#ibcon#about to read 4, iclass 19, count 0 2006.168.07:40:08.02#ibcon#read 4, iclass 19, count 0 2006.168.07:40:08.02#ibcon#about to read 5, iclass 19, count 0 2006.168.07:40:08.02#ibcon#read 5, iclass 19, count 0 2006.168.07:40:08.02#ibcon#about to read 6, iclass 19, count 0 2006.168.07:40:08.02#ibcon#read 6, iclass 19, count 0 2006.168.07:40:08.02#ibcon#end of sib2, iclass 19, count 0 2006.168.07:40:08.02#ibcon#*after write, iclass 19, count 0 2006.168.07:40:08.02#ibcon#*before return 0, iclass 19, count 0 2006.168.07:40:08.02#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:40:08.02#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:40:08.02#ibcon#about to clear, iclass 19 cls_cnt 0 2006.168.07:40:08.02#ibcon#cleared, iclass 19 cls_cnt 0 2006.168.07:40:08.02$vc4f8/va=1,8 2006.168.07:40:08.02#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.168.07:40:08.02#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.168.07:40:08.02#ibcon#ireg 11 cls_cnt 2 2006.168.07:40:08.02#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.168.07:40:08.02#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.168.07:40:08.02#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.168.07:40:08.02#ibcon#enter wrdev, iclass 21, count 2 2006.168.07:40:08.02#ibcon#first serial, iclass 21, count 2 2006.168.07:40:08.02#ibcon#enter sib2, iclass 21, count 2 2006.168.07:40:08.02#ibcon#flushed, iclass 21, count 2 2006.168.07:40:08.02#ibcon#about to write, iclass 21, count 2 2006.168.07:40:08.02#ibcon#wrote, iclass 21, count 2 2006.168.07:40:08.02#ibcon#about to read 3, iclass 21, count 2 2006.168.07:40:08.04#ibcon#read 3, iclass 21, count 2 2006.168.07:40:08.04#ibcon#about to read 4, iclass 21, count 2 2006.168.07:40:08.04#ibcon#read 4, iclass 21, count 2 2006.168.07:40:08.04#ibcon#about to read 5, iclass 21, count 2 2006.168.07:40:08.04#ibcon#read 5, iclass 21, count 2 2006.168.07:40:08.04#ibcon#about to read 6, iclass 21, count 2 2006.168.07:40:08.04#ibcon#read 6, iclass 21, count 2 2006.168.07:40:08.04#ibcon#end of sib2, iclass 21, count 2 2006.168.07:40:08.04#ibcon#*mode == 0, iclass 21, count 2 2006.168.07:40:08.04#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.168.07:40:08.04#ibcon#[25=AT01-08\r\n] 2006.168.07:40:08.04#ibcon#*before write, iclass 21, count 2 2006.168.07:40:08.04#ibcon#enter sib2, iclass 21, count 2 2006.168.07:40:08.04#ibcon#flushed, iclass 21, count 2 2006.168.07:40:08.04#ibcon#about to write, iclass 21, count 2 2006.168.07:40:08.04#ibcon#wrote, iclass 21, count 2 2006.168.07:40:08.04#ibcon#about to read 3, iclass 21, count 2 2006.168.07:40:08.07#ibcon#read 3, iclass 21, count 2 2006.168.07:40:08.07#ibcon#about to read 4, iclass 21, count 2 2006.168.07:40:08.07#ibcon#read 4, iclass 21, count 2 2006.168.07:40:08.07#ibcon#about to read 5, iclass 21, count 2 2006.168.07:40:08.07#ibcon#read 5, iclass 21, count 2 2006.168.07:40:08.07#ibcon#about to read 6, iclass 21, count 2 2006.168.07:40:08.07#ibcon#read 6, iclass 21, count 2 2006.168.07:40:08.07#ibcon#end of sib2, iclass 21, count 2 2006.168.07:40:08.07#ibcon#*after write, iclass 21, count 2 2006.168.07:40:08.07#ibcon#*before return 0, iclass 21, count 2 2006.168.07:40:08.07#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.168.07:40:08.07#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.168.07:40:08.07#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.168.07:40:08.07#ibcon#ireg 7 cls_cnt 0 2006.168.07:40:08.07#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.168.07:40:08.19#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.168.07:40:08.19#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.168.07:40:08.19#ibcon#enter wrdev, iclass 21, count 0 2006.168.07:40:08.19#ibcon#first serial, iclass 21, count 0 2006.168.07:40:08.19#ibcon#enter sib2, iclass 21, count 0 2006.168.07:40:08.19#ibcon#flushed, iclass 21, count 0 2006.168.07:40:08.19#ibcon#about to write, iclass 21, count 0 2006.168.07:40:08.19#ibcon#wrote, iclass 21, count 0 2006.168.07:40:08.19#ibcon#about to read 3, iclass 21, count 0 2006.168.07:40:08.21#ibcon#read 3, iclass 21, count 0 2006.168.07:40:08.21#ibcon#about to read 4, iclass 21, count 0 2006.168.07:40:08.21#ibcon#read 4, iclass 21, count 0 2006.168.07:40:08.21#ibcon#about to read 5, iclass 21, count 0 2006.168.07:40:08.21#ibcon#read 5, iclass 21, count 0 2006.168.07:40:08.21#ibcon#about to read 6, iclass 21, count 0 2006.168.07:40:08.21#ibcon#read 6, iclass 21, count 0 2006.168.07:40:08.21#ibcon#end of sib2, iclass 21, count 0 2006.168.07:40:08.21#ibcon#*mode == 0, iclass 21, count 0 2006.168.07:40:08.21#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.168.07:40:08.21#ibcon#[25=USB\r\n] 2006.168.07:40:08.21#ibcon#*before write, iclass 21, count 0 2006.168.07:40:08.21#ibcon#enter sib2, iclass 21, count 0 2006.168.07:40:08.21#ibcon#flushed, iclass 21, count 0 2006.168.07:40:08.21#ibcon#about to write, iclass 21, count 0 2006.168.07:40:08.21#ibcon#wrote, iclass 21, count 0 2006.168.07:40:08.21#ibcon#about to read 3, iclass 21, count 0 2006.168.07:40:08.24#ibcon#read 3, iclass 21, count 0 2006.168.07:40:08.24#ibcon#about to read 4, iclass 21, count 0 2006.168.07:40:08.24#ibcon#read 4, iclass 21, count 0 2006.168.07:40:08.24#ibcon#about to read 5, iclass 21, count 0 2006.168.07:40:08.24#ibcon#read 5, iclass 21, count 0 2006.168.07:40:08.24#ibcon#about to read 6, iclass 21, count 0 2006.168.07:40:08.24#ibcon#read 6, iclass 21, count 0 2006.168.07:40:08.24#ibcon#end of sib2, iclass 21, count 0 2006.168.07:40:08.24#ibcon#*after write, iclass 21, count 0 2006.168.07:40:08.24#ibcon#*before return 0, iclass 21, count 0 2006.168.07:40:08.24#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.168.07:40:08.24#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.168.07:40:08.24#ibcon#about to clear, iclass 21 cls_cnt 0 2006.168.07:40:08.24#ibcon#cleared, iclass 21 cls_cnt 0 2006.168.07:40:08.24$vc4f8/valo=2,572.99 2006.168.07:40:08.24#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.168.07:40:08.24#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.168.07:40:08.24#ibcon#ireg 17 cls_cnt 0 2006.168.07:40:08.24#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:40:08.24#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:40:08.24#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:40:08.24#ibcon#enter wrdev, iclass 23, count 0 2006.168.07:40:08.24#ibcon#first serial, iclass 23, count 0 2006.168.07:40:08.24#ibcon#enter sib2, iclass 23, count 0 2006.168.07:40:08.24#ibcon#flushed, iclass 23, count 0 2006.168.07:40:08.24#ibcon#about to write, iclass 23, count 0 2006.168.07:40:08.24#ibcon#wrote, iclass 23, count 0 2006.168.07:40:08.24#ibcon#about to read 3, iclass 23, count 0 2006.168.07:40:08.26#ibcon#read 3, iclass 23, count 0 2006.168.07:40:08.26#ibcon#about to read 4, iclass 23, count 0 2006.168.07:40:08.26#ibcon#read 4, iclass 23, count 0 2006.168.07:40:08.26#ibcon#about to read 5, iclass 23, count 0 2006.168.07:40:08.26#ibcon#read 5, iclass 23, count 0 2006.168.07:40:08.26#ibcon#about to read 6, iclass 23, count 0 2006.168.07:40:08.26#ibcon#read 6, iclass 23, count 0 2006.168.07:40:08.26#ibcon#end of sib2, iclass 23, count 0 2006.168.07:40:08.26#ibcon#*mode == 0, iclass 23, count 0 2006.168.07:40:08.26#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.168.07:40:08.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.07:40:08.26#ibcon#*before write, iclass 23, count 0 2006.168.07:40:08.26#ibcon#enter sib2, iclass 23, count 0 2006.168.07:40:08.26#ibcon#flushed, iclass 23, count 0 2006.168.07:40:08.26#ibcon#about to write, iclass 23, count 0 2006.168.07:40:08.26#ibcon#wrote, iclass 23, count 0 2006.168.07:40:08.26#ibcon#about to read 3, iclass 23, count 0 2006.168.07:40:08.30#ibcon#read 3, iclass 23, count 0 2006.168.07:40:08.30#ibcon#about to read 4, iclass 23, count 0 2006.168.07:40:08.30#ibcon#read 4, iclass 23, count 0 2006.168.07:40:08.30#ibcon#about to read 5, iclass 23, count 0 2006.168.07:40:08.30#ibcon#read 5, iclass 23, count 0 2006.168.07:40:08.30#ibcon#about to read 6, iclass 23, count 0 2006.168.07:40:08.30#ibcon#read 6, iclass 23, count 0 2006.168.07:40:08.30#ibcon#end of sib2, iclass 23, count 0 2006.168.07:40:08.30#ibcon#*after write, iclass 23, count 0 2006.168.07:40:08.30#ibcon#*before return 0, iclass 23, count 0 2006.168.07:40:08.30#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:40:08.30#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:40:08.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.168.07:40:08.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.168.07:40:08.30$vc4f8/va=2,7 2006.168.07:40:08.30#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.168.07:40:08.30#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.168.07:40:08.30#ibcon#ireg 11 cls_cnt 2 2006.168.07:40:08.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.168.07:40:08.36#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.168.07:40:08.36#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.168.07:40:08.36#ibcon#enter wrdev, iclass 25, count 2 2006.168.07:40:08.36#ibcon#first serial, iclass 25, count 2 2006.168.07:40:08.36#ibcon#enter sib2, iclass 25, count 2 2006.168.07:40:08.36#ibcon#flushed, iclass 25, count 2 2006.168.07:40:08.36#ibcon#about to write, iclass 25, count 2 2006.168.07:40:08.36#ibcon#wrote, iclass 25, count 2 2006.168.07:40:08.36#ibcon#about to read 3, iclass 25, count 2 2006.168.07:40:08.38#ibcon#read 3, iclass 25, count 2 2006.168.07:40:08.38#ibcon#about to read 4, iclass 25, count 2 2006.168.07:40:08.38#ibcon#read 4, iclass 25, count 2 2006.168.07:40:08.38#ibcon#about to read 5, iclass 25, count 2 2006.168.07:40:08.38#ibcon#read 5, iclass 25, count 2 2006.168.07:40:08.38#ibcon#about to read 6, iclass 25, count 2 2006.168.07:40:08.38#ibcon#read 6, iclass 25, count 2 2006.168.07:40:08.38#ibcon#end of sib2, iclass 25, count 2 2006.168.07:40:08.38#ibcon#*mode == 0, iclass 25, count 2 2006.168.07:40:08.38#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.168.07:40:08.38#ibcon#[25=AT02-07\r\n] 2006.168.07:40:08.38#ibcon#*before write, iclass 25, count 2 2006.168.07:40:08.38#ibcon#enter sib2, iclass 25, count 2 2006.168.07:40:08.38#ibcon#flushed, iclass 25, count 2 2006.168.07:40:08.38#ibcon#about to write, iclass 25, count 2 2006.168.07:40:08.38#ibcon#wrote, iclass 25, count 2 2006.168.07:40:08.38#ibcon#about to read 3, iclass 25, count 2 2006.168.07:40:08.41#ibcon#read 3, iclass 25, count 2 2006.168.07:40:08.41#ibcon#about to read 4, iclass 25, count 2 2006.168.07:40:08.41#ibcon#read 4, iclass 25, count 2 2006.168.07:40:08.41#ibcon#about to read 5, iclass 25, count 2 2006.168.07:40:08.41#ibcon#read 5, iclass 25, count 2 2006.168.07:40:08.41#ibcon#about to read 6, iclass 25, count 2 2006.168.07:40:08.41#ibcon#read 6, iclass 25, count 2 2006.168.07:40:08.41#ibcon#end of sib2, iclass 25, count 2 2006.168.07:40:08.41#ibcon#*after write, iclass 25, count 2 2006.168.07:40:08.41#ibcon#*before return 0, iclass 25, count 2 2006.168.07:40:08.41#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.168.07:40:08.41#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.168.07:40:08.41#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.168.07:40:08.41#ibcon#ireg 7 cls_cnt 0 2006.168.07:40:08.41#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.168.07:40:08.53#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.168.07:40:08.53#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.168.07:40:08.53#ibcon#enter wrdev, iclass 25, count 0 2006.168.07:40:08.53#ibcon#first serial, iclass 25, count 0 2006.168.07:40:08.53#ibcon#enter sib2, iclass 25, count 0 2006.168.07:40:08.53#ibcon#flushed, iclass 25, count 0 2006.168.07:40:08.53#ibcon#about to write, iclass 25, count 0 2006.168.07:40:08.53#ibcon#wrote, iclass 25, count 0 2006.168.07:40:08.53#ibcon#about to read 3, iclass 25, count 0 2006.168.07:40:08.55#ibcon#read 3, iclass 25, count 0 2006.168.07:40:08.55#ibcon#about to read 4, iclass 25, count 0 2006.168.07:40:08.55#ibcon#read 4, iclass 25, count 0 2006.168.07:40:08.55#ibcon#about to read 5, iclass 25, count 0 2006.168.07:40:08.55#ibcon#read 5, iclass 25, count 0 2006.168.07:40:08.55#ibcon#about to read 6, iclass 25, count 0 2006.168.07:40:08.55#ibcon#read 6, iclass 25, count 0 2006.168.07:40:08.55#ibcon#end of sib2, iclass 25, count 0 2006.168.07:40:08.55#ibcon#*mode == 0, iclass 25, count 0 2006.168.07:40:08.55#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.168.07:40:08.55#ibcon#[25=USB\r\n] 2006.168.07:40:08.55#ibcon#*before write, iclass 25, count 0 2006.168.07:40:08.55#ibcon#enter sib2, iclass 25, count 0 2006.168.07:40:08.55#ibcon#flushed, iclass 25, count 0 2006.168.07:40:08.55#ibcon#about to write, iclass 25, count 0 2006.168.07:40:08.55#ibcon#wrote, iclass 25, count 0 2006.168.07:40:08.55#ibcon#about to read 3, iclass 25, count 0 2006.168.07:40:08.58#ibcon#read 3, iclass 25, count 0 2006.168.07:40:08.58#ibcon#about to read 4, iclass 25, count 0 2006.168.07:40:08.58#ibcon#read 4, iclass 25, count 0 2006.168.07:40:08.58#ibcon#about to read 5, iclass 25, count 0 2006.168.07:40:08.58#ibcon#read 5, iclass 25, count 0 2006.168.07:40:08.58#ibcon#about to read 6, iclass 25, count 0 2006.168.07:40:08.58#ibcon#read 6, iclass 25, count 0 2006.168.07:40:08.58#ibcon#end of sib2, iclass 25, count 0 2006.168.07:40:08.58#ibcon#*after write, iclass 25, count 0 2006.168.07:40:08.58#ibcon#*before return 0, iclass 25, count 0 2006.168.07:40:08.58#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.168.07:40:08.58#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.168.07:40:08.58#ibcon#about to clear, iclass 25 cls_cnt 0 2006.168.07:40:08.58#ibcon#cleared, iclass 25 cls_cnt 0 2006.168.07:40:08.58$vc4f8/valo=3,672.99 2006.168.07:40:08.58#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.168.07:40:08.58#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.168.07:40:08.58#ibcon#ireg 17 cls_cnt 0 2006.168.07:40:08.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.168.07:40:08.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.168.07:40:08.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.168.07:40:08.58#ibcon#enter wrdev, iclass 27, count 0 2006.168.07:40:08.58#ibcon#first serial, iclass 27, count 0 2006.168.07:40:08.58#ibcon#enter sib2, iclass 27, count 0 2006.168.07:40:08.58#ibcon#flushed, iclass 27, count 0 2006.168.07:40:08.58#ibcon#about to write, iclass 27, count 0 2006.168.07:40:08.58#ibcon#wrote, iclass 27, count 0 2006.168.07:40:08.58#ibcon#about to read 3, iclass 27, count 0 2006.168.07:40:08.60#ibcon#read 3, iclass 27, count 0 2006.168.07:40:08.60#ibcon#about to read 4, iclass 27, count 0 2006.168.07:40:08.60#ibcon#read 4, iclass 27, count 0 2006.168.07:40:08.60#ibcon#about to read 5, iclass 27, count 0 2006.168.07:40:08.60#ibcon#read 5, iclass 27, count 0 2006.168.07:40:08.60#ibcon#about to read 6, iclass 27, count 0 2006.168.07:40:08.60#ibcon#read 6, iclass 27, count 0 2006.168.07:40:08.60#ibcon#end of sib2, iclass 27, count 0 2006.168.07:40:08.60#ibcon#*mode == 0, iclass 27, count 0 2006.168.07:40:08.60#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.168.07:40:08.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.07:40:08.60#ibcon#*before write, iclass 27, count 0 2006.168.07:40:08.60#ibcon#enter sib2, iclass 27, count 0 2006.168.07:40:08.60#ibcon#flushed, iclass 27, count 0 2006.168.07:40:08.60#ibcon#about to write, iclass 27, count 0 2006.168.07:40:08.60#ibcon#wrote, iclass 27, count 0 2006.168.07:40:08.60#ibcon#about to read 3, iclass 27, count 0 2006.168.07:40:08.64#ibcon#read 3, iclass 27, count 0 2006.168.07:40:08.64#ibcon#about to read 4, iclass 27, count 0 2006.168.07:40:08.64#ibcon#read 4, iclass 27, count 0 2006.168.07:40:08.64#ibcon#about to read 5, iclass 27, count 0 2006.168.07:40:08.64#ibcon#read 5, iclass 27, count 0 2006.168.07:40:08.64#ibcon#about to read 6, iclass 27, count 0 2006.168.07:40:08.64#ibcon#read 6, iclass 27, count 0 2006.168.07:40:08.64#ibcon#end of sib2, iclass 27, count 0 2006.168.07:40:08.64#ibcon#*after write, iclass 27, count 0 2006.168.07:40:08.64#ibcon#*before return 0, iclass 27, count 0 2006.168.07:40:08.64#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.168.07:40:08.64#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.168.07:40:08.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.168.07:40:08.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.168.07:40:08.64$vc4f8/va=3,6 2006.168.07:40:08.64#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.168.07:40:08.64#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.168.07:40:08.64#ibcon#ireg 11 cls_cnt 2 2006.168.07:40:08.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.168.07:40:08.70#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.168.07:40:08.70#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.168.07:40:08.70#ibcon#enter wrdev, iclass 29, count 2 2006.168.07:40:08.70#ibcon#first serial, iclass 29, count 2 2006.168.07:40:08.70#ibcon#enter sib2, iclass 29, count 2 2006.168.07:40:08.70#ibcon#flushed, iclass 29, count 2 2006.168.07:40:08.70#ibcon#about to write, iclass 29, count 2 2006.168.07:40:08.70#ibcon#wrote, iclass 29, count 2 2006.168.07:40:08.70#ibcon#about to read 3, iclass 29, count 2 2006.168.07:40:08.72#ibcon#read 3, iclass 29, count 2 2006.168.07:40:08.72#ibcon#about to read 4, iclass 29, count 2 2006.168.07:40:08.72#ibcon#read 4, iclass 29, count 2 2006.168.07:40:08.72#ibcon#about to read 5, iclass 29, count 2 2006.168.07:40:08.72#ibcon#read 5, iclass 29, count 2 2006.168.07:40:08.72#ibcon#about to read 6, iclass 29, count 2 2006.168.07:40:08.72#ibcon#read 6, iclass 29, count 2 2006.168.07:40:08.72#ibcon#end of sib2, iclass 29, count 2 2006.168.07:40:08.72#ibcon#*mode == 0, iclass 29, count 2 2006.168.07:40:08.72#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.168.07:40:08.72#ibcon#[25=AT03-06\r\n] 2006.168.07:40:08.72#ibcon#*before write, iclass 29, count 2 2006.168.07:40:08.72#ibcon#enter sib2, iclass 29, count 2 2006.168.07:40:08.72#ibcon#flushed, iclass 29, count 2 2006.168.07:40:08.72#ibcon#about to write, iclass 29, count 2 2006.168.07:40:08.72#ibcon#wrote, iclass 29, count 2 2006.168.07:40:08.72#ibcon#about to read 3, iclass 29, count 2 2006.168.07:40:08.76#ibcon#read 3, iclass 29, count 2 2006.168.07:40:08.76#ibcon#about to read 4, iclass 29, count 2 2006.168.07:40:08.76#ibcon#read 4, iclass 29, count 2 2006.168.07:40:08.76#ibcon#about to read 5, iclass 29, count 2 2006.168.07:40:08.76#ibcon#read 5, iclass 29, count 2 2006.168.07:40:08.76#ibcon#about to read 6, iclass 29, count 2 2006.168.07:40:08.76#ibcon#read 6, iclass 29, count 2 2006.168.07:40:08.76#ibcon#end of sib2, iclass 29, count 2 2006.168.07:40:08.76#ibcon#*after write, iclass 29, count 2 2006.168.07:40:08.76#ibcon#*before return 0, iclass 29, count 2 2006.168.07:40:08.76#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.168.07:40:08.76#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.168.07:40:08.76#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.168.07:40:08.76#ibcon#ireg 7 cls_cnt 0 2006.168.07:40:08.76#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.168.07:40:08.88#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.168.07:40:08.88#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.168.07:40:08.88#ibcon#enter wrdev, iclass 29, count 0 2006.168.07:40:08.88#ibcon#first serial, iclass 29, count 0 2006.168.07:40:08.88#ibcon#enter sib2, iclass 29, count 0 2006.168.07:40:08.88#ibcon#flushed, iclass 29, count 0 2006.168.07:40:08.88#ibcon#about to write, iclass 29, count 0 2006.168.07:40:08.88#ibcon#wrote, iclass 29, count 0 2006.168.07:40:08.88#ibcon#about to read 3, iclass 29, count 0 2006.168.07:40:08.90#ibcon#read 3, iclass 29, count 0 2006.168.07:40:08.90#ibcon#about to read 4, iclass 29, count 0 2006.168.07:40:08.90#ibcon#read 4, iclass 29, count 0 2006.168.07:40:08.90#ibcon#about to read 5, iclass 29, count 0 2006.168.07:40:08.90#ibcon#read 5, iclass 29, count 0 2006.168.07:40:08.90#ibcon#about to read 6, iclass 29, count 0 2006.168.07:40:08.90#ibcon#read 6, iclass 29, count 0 2006.168.07:40:08.90#ibcon#end of sib2, iclass 29, count 0 2006.168.07:40:08.90#ibcon#*mode == 0, iclass 29, count 0 2006.168.07:40:08.90#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.168.07:40:08.90#ibcon#[25=USB\r\n] 2006.168.07:40:08.90#ibcon#*before write, iclass 29, count 0 2006.168.07:40:08.90#ibcon#enter sib2, iclass 29, count 0 2006.168.07:40:08.90#ibcon#flushed, iclass 29, count 0 2006.168.07:40:08.90#ibcon#about to write, iclass 29, count 0 2006.168.07:40:08.90#ibcon#wrote, iclass 29, count 0 2006.168.07:40:08.90#ibcon#about to read 3, iclass 29, count 0 2006.168.07:40:08.93#ibcon#read 3, iclass 29, count 0 2006.168.07:40:08.93#ibcon#about to read 4, iclass 29, count 0 2006.168.07:40:08.93#ibcon#read 4, iclass 29, count 0 2006.168.07:40:08.93#ibcon#about to read 5, iclass 29, count 0 2006.168.07:40:08.93#ibcon#read 5, iclass 29, count 0 2006.168.07:40:08.93#ibcon#about to read 6, iclass 29, count 0 2006.168.07:40:08.93#ibcon#read 6, iclass 29, count 0 2006.168.07:40:08.93#ibcon#end of sib2, iclass 29, count 0 2006.168.07:40:08.93#ibcon#*after write, iclass 29, count 0 2006.168.07:40:08.93#ibcon#*before return 0, iclass 29, count 0 2006.168.07:40:08.93#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.168.07:40:08.93#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.168.07:40:08.93#ibcon#about to clear, iclass 29 cls_cnt 0 2006.168.07:40:08.93#ibcon#cleared, iclass 29 cls_cnt 0 2006.168.07:40:08.93$vc4f8/valo=4,832.99 2006.168.07:40:08.93#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.168.07:40:08.93#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.168.07:40:08.93#ibcon#ireg 17 cls_cnt 0 2006.168.07:40:08.93#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:40:08.93#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:40:08.93#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:40:08.93#ibcon#enter wrdev, iclass 31, count 0 2006.168.07:40:08.93#ibcon#first serial, iclass 31, count 0 2006.168.07:40:08.93#ibcon#enter sib2, iclass 31, count 0 2006.168.07:40:08.93#ibcon#flushed, iclass 31, count 0 2006.168.07:40:08.93#ibcon#about to write, iclass 31, count 0 2006.168.07:40:08.93#ibcon#wrote, iclass 31, count 0 2006.168.07:40:08.93#ibcon#about to read 3, iclass 31, count 0 2006.168.07:40:08.95#ibcon#read 3, iclass 31, count 0 2006.168.07:40:08.95#ibcon#about to read 4, iclass 31, count 0 2006.168.07:40:08.95#ibcon#read 4, iclass 31, count 0 2006.168.07:40:08.95#ibcon#about to read 5, iclass 31, count 0 2006.168.07:40:08.95#ibcon#read 5, iclass 31, count 0 2006.168.07:40:08.95#ibcon#about to read 6, iclass 31, count 0 2006.168.07:40:08.95#ibcon#read 6, iclass 31, count 0 2006.168.07:40:08.95#ibcon#end of sib2, iclass 31, count 0 2006.168.07:40:08.95#ibcon#*mode == 0, iclass 31, count 0 2006.168.07:40:08.95#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.168.07:40:08.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.07:40:08.95#ibcon#*before write, iclass 31, count 0 2006.168.07:40:08.95#ibcon#enter sib2, iclass 31, count 0 2006.168.07:40:08.95#ibcon#flushed, iclass 31, count 0 2006.168.07:40:08.95#ibcon#about to write, iclass 31, count 0 2006.168.07:40:08.95#ibcon#wrote, iclass 31, count 0 2006.168.07:40:08.95#ibcon#about to read 3, iclass 31, count 0 2006.168.07:40:08.99#ibcon#read 3, iclass 31, count 0 2006.168.07:40:08.99#ibcon#about to read 4, iclass 31, count 0 2006.168.07:40:08.99#ibcon#read 4, iclass 31, count 0 2006.168.07:40:08.99#ibcon#about to read 5, iclass 31, count 0 2006.168.07:40:08.99#ibcon#read 5, iclass 31, count 0 2006.168.07:40:08.99#ibcon#about to read 6, iclass 31, count 0 2006.168.07:40:08.99#ibcon#read 6, iclass 31, count 0 2006.168.07:40:08.99#ibcon#end of sib2, iclass 31, count 0 2006.168.07:40:08.99#ibcon#*after write, iclass 31, count 0 2006.168.07:40:08.99#ibcon#*before return 0, iclass 31, count 0 2006.168.07:40:08.99#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:40:08.99#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:40:08.99#ibcon#about to clear, iclass 31 cls_cnt 0 2006.168.07:40:08.99#ibcon#cleared, iclass 31 cls_cnt 0 2006.168.07:40:08.99$vc4f8/va=4,7 2006.168.07:40:08.99#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.168.07:40:08.99#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.168.07:40:08.99#ibcon#ireg 11 cls_cnt 2 2006.168.07:40:08.99#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:40:09.05#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:40:09.05#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:40:09.05#ibcon#enter wrdev, iclass 33, count 2 2006.168.07:40:09.05#ibcon#first serial, iclass 33, count 2 2006.168.07:40:09.05#ibcon#enter sib2, iclass 33, count 2 2006.168.07:40:09.05#ibcon#flushed, iclass 33, count 2 2006.168.07:40:09.05#ibcon#about to write, iclass 33, count 2 2006.168.07:40:09.05#ibcon#wrote, iclass 33, count 2 2006.168.07:40:09.05#ibcon#about to read 3, iclass 33, count 2 2006.168.07:40:09.07#ibcon#read 3, iclass 33, count 2 2006.168.07:40:09.07#ibcon#about to read 4, iclass 33, count 2 2006.168.07:40:09.07#ibcon#read 4, iclass 33, count 2 2006.168.07:40:09.07#ibcon#about to read 5, iclass 33, count 2 2006.168.07:40:09.07#ibcon#read 5, iclass 33, count 2 2006.168.07:40:09.07#ibcon#about to read 6, iclass 33, count 2 2006.168.07:40:09.07#ibcon#read 6, iclass 33, count 2 2006.168.07:40:09.07#ibcon#end of sib2, iclass 33, count 2 2006.168.07:40:09.07#ibcon#*mode == 0, iclass 33, count 2 2006.168.07:40:09.07#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.168.07:40:09.07#ibcon#[25=AT04-07\r\n] 2006.168.07:40:09.07#ibcon#*before write, iclass 33, count 2 2006.168.07:40:09.07#ibcon#enter sib2, iclass 33, count 2 2006.168.07:40:09.07#ibcon#flushed, iclass 33, count 2 2006.168.07:40:09.07#ibcon#about to write, iclass 33, count 2 2006.168.07:40:09.07#ibcon#wrote, iclass 33, count 2 2006.168.07:40:09.07#ibcon#about to read 3, iclass 33, count 2 2006.168.07:40:09.10#ibcon#read 3, iclass 33, count 2 2006.168.07:40:09.10#ibcon#about to read 4, iclass 33, count 2 2006.168.07:40:09.10#ibcon#read 4, iclass 33, count 2 2006.168.07:40:09.10#ibcon#about to read 5, iclass 33, count 2 2006.168.07:40:09.10#ibcon#read 5, iclass 33, count 2 2006.168.07:40:09.10#ibcon#about to read 6, iclass 33, count 2 2006.168.07:40:09.10#ibcon#read 6, iclass 33, count 2 2006.168.07:40:09.10#ibcon#end of sib2, iclass 33, count 2 2006.168.07:40:09.10#ibcon#*after write, iclass 33, count 2 2006.168.07:40:09.10#ibcon#*before return 0, iclass 33, count 2 2006.168.07:40:09.10#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:40:09.10#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:40:09.10#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.168.07:40:09.10#ibcon#ireg 7 cls_cnt 0 2006.168.07:40:09.10#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:40:09.22#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:40:09.22#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:40:09.22#ibcon#enter wrdev, iclass 33, count 0 2006.168.07:40:09.22#ibcon#first serial, iclass 33, count 0 2006.168.07:40:09.22#ibcon#enter sib2, iclass 33, count 0 2006.168.07:40:09.22#ibcon#flushed, iclass 33, count 0 2006.168.07:40:09.22#ibcon#about to write, iclass 33, count 0 2006.168.07:40:09.22#ibcon#wrote, iclass 33, count 0 2006.168.07:40:09.22#ibcon#about to read 3, iclass 33, count 0 2006.168.07:40:09.24#ibcon#read 3, iclass 33, count 0 2006.168.07:40:09.24#ibcon#about to read 4, iclass 33, count 0 2006.168.07:40:09.24#ibcon#read 4, iclass 33, count 0 2006.168.07:40:09.24#ibcon#about to read 5, iclass 33, count 0 2006.168.07:40:09.24#ibcon#read 5, iclass 33, count 0 2006.168.07:40:09.24#ibcon#about to read 6, iclass 33, count 0 2006.168.07:40:09.24#ibcon#read 6, iclass 33, count 0 2006.168.07:40:09.24#ibcon#end of sib2, iclass 33, count 0 2006.168.07:40:09.24#ibcon#*mode == 0, iclass 33, count 0 2006.168.07:40:09.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.168.07:40:09.24#ibcon#[25=USB\r\n] 2006.168.07:40:09.24#ibcon#*before write, iclass 33, count 0 2006.168.07:40:09.24#ibcon#enter sib2, iclass 33, count 0 2006.168.07:40:09.24#ibcon#flushed, iclass 33, count 0 2006.168.07:40:09.24#ibcon#about to write, iclass 33, count 0 2006.168.07:40:09.24#ibcon#wrote, iclass 33, count 0 2006.168.07:40:09.24#ibcon#about to read 3, iclass 33, count 0 2006.168.07:40:09.27#ibcon#read 3, iclass 33, count 0 2006.168.07:40:09.27#ibcon#about to read 4, iclass 33, count 0 2006.168.07:40:09.27#ibcon#read 4, iclass 33, count 0 2006.168.07:40:09.27#ibcon#about to read 5, iclass 33, count 0 2006.168.07:40:09.27#ibcon#read 5, iclass 33, count 0 2006.168.07:40:09.27#ibcon#about to read 6, iclass 33, count 0 2006.168.07:40:09.27#ibcon#read 6, iclass 33, count 0 2006.168.07:40:09.27#ibcon#end of sib2, iclass 33, count 0 2006.168.07:40:09.27#ibcon#*after write, iclass 33, count 0 2006.168.07:40:09.27#ibcon#*before return 0, iclass 33, count 0 2006.168.07:40:09.27#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:40:09.27#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:40:09.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.168.07:40:09.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.168.07:40:09.27$vc4f8/valo=5,652.99 2006.168.07:40:09.27#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.168.07:40:09.27#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.168.07:40:09.27#ibcon#ireg 17 cls_cnt 0 2006.168.07:40:09.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:40:09.27#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:40:09.27#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:40:09.27#ibcon#enter wrdev, iclass 35, count 0 2006.168.07:40:09.27#ibcon#first serial, iclass 35, count 0 2006.168.07:40:09.27#ibcon#enter sib2, iclass 35, count 0 2006.168.07:40:09.27#ibcon#flushed, iclass 35, count 0 2006.168.07:40:09.27#ibcon#about to write, iclass 35, count 0 2006.168.07:40:09.27#ibcon#wrote, iclass 35, count 0 2006.168.07:40:09.27#ibcon#about to read 3, iclass 35, count 0 2006.168.07:40:09.29#ibcon#read 3, iclass 35, count 0 2006.168.07:40:09.29#ibcon#about to read 4, iclass 35, count 0 2006.168.07:40:09.29#ibcon#read 4, iclass 35, count 0 2006.168.07:40:09.29#ibcon#about to read 5, iclass 35, count 0 2006.168.07:40:09.29#ibcon#read 5, iclass 35, count 0 2006.168.07:40:09.29#ibcon#about to read 6, iclass 35, count 0 2006.168.07:40:09.29#ibcon#read 6, iclass 35, count 0 2006.168.07:40:09.29#ibcon#end of sib2, iclass 35, count 0 2006.168.07:40:09.29#ibcon#*mode == 0, iclass 35, count 0 2006.168.07:40:09.29#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.168.07:40:09.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.07:40:09.29#ibcon#*before write, iclass 35, count 0 2006.168.07:40:09.29#ibcon#enter sib2, iclass 35, count 0 2006.168.07:40:09.29#ibcon#flushed, iclass 35, count 0 2006.168.07:40:09.29#ibcon#about to write, iclass 35, count 0 2006.168.07:40:09.29#ibcon#wrote, iclass 35, count 0 2006.168.07:40:09.29#ibcon#about to read 3, iclass 35, count 0 2006.168.07:40:09.33#ibcon#read 3, iclass 35, count 0 2006.168.07:40:09.33#ibcon#about to read 4, iclass 35, count 0 2006.168.07:40:09.33#ibcon#read 4, iclass 35, count 0 2006.168.07:40:09.33#ibcon#about to read 5, iclass 35, count 0 2006.168.07:40:09.33#ibcon#read 5, iclass 35, count 0 2006.168.07:40:09.33#ibcon#about to read 6, iclass 35, count 0 2006.168.07:40:09.33#ibcon#read 6, iclass 35, count 0 2006.168.07:40:09.33#ibcon#end of sib2, iclass 35, count 0 2006.168.07:40:09.33#ibcon#*after write, iclass 35, count 0 2006.168.07:40:09.33#ibcon#*before return 0, iclass 35, count 0 2006.168.07:40:09.33#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:40:09.33#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:40:09.33#ibcon#about to clear, iclass 35 cls_cnt 0 2006.168.07:40:09.33#ibcon#cleared, iclass 35 cls_cnt 0 2006.168.07:40:09.33$vc4f8/va=5,7 2006.168.07:40:09.33#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.168.07:40:09.33#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.168.07:40:09.33#ibcon#ireg 11 cls_cnt 2 2006.168.07:40:09.33#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:40:09.39#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:40:09.39#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:40:09.39#ibcon#enter wrdev, iclass 37, count 2 2006.168.07:40:09.39#ibcon#first serial, iclass 37, count 2 2006.168.07:40:09.39#ibcon#enter sib2, iclass 37, count 2 2006.168.07:40:09.39#ibcon#flushed, iclass 37, count 2 2006.168.07:40:09.39#ibcon#about to write, iclass 37, count 2 2006.168.07:40:09.39#ibcon#wrote, iclass 37, count 2 2006.168.07:40:09.39#ibcon#about to read 3, iclass 37, count 2 2006.168.07:40:09.41#ibcon#read 3, iclass 37, count 2 2006.168.07:40:09.41#ibcon#about to read 4, iclass 37, count 2 2006.168.07:40:09.41#ibcon#read 4, iclass 37, count 2 2006.168.07:40:09.41#ibcon#about to read 5, iclass 37, count 2 2006.168.07:40:09.41#ibcon#read 5, iclass 37, count 2 2006.168.07:40:09.41#ibcon#about to read 6, iclass 37, count 2 2006.168.07:40:09.41#ibcon#read 6, iclass 37, count 2 2006.168.07:40:09.41#ibcon#end of sib2, iclass 37, count 2 2006.168.07:40:09.41#ibcon#*mode == 0, iclass 37, count 2 2006.168.07:40:09.41#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.168.07:40:09.41#ibcon#[25=AT05-07\r\n] 2006.168.07:40:09.41#ibcon#*before write, iclass 37, count 2 2006.168.07:40:09.41#ibcon#enter sib2, iclass 37, count 2 2006.168.07:40:09.41#ibcon#flushed, iclass 37, count 2 2006.168.07:40:09.41#ibcon#about to write, iclass 37, count 2 2006.168.07:40:09.41#ibcon#wrote, iclass 37, count 2 2006.168.07:40:09.41#ibcon#about to read 3, iclass 37, count 2 2006.168.07:40:09.44#ibcon#read 3, iclass 37, count 2 2006.168.07:40:09.44#ibcon#about to read 4, iclass 37, count 2 2006.168.07:40:09.44#ibcon#read 4, iclass 37, count 2 2006.168.07:40:09.44#ibcon#about to read 5, iclass 37, count 2 2006.168.07:40:09.44#ibcon#read 5, iclass 37, count 2 2006.168.07:40:09.44#ibcon#about to read 6, iclass 37, count 2 2006.168.07:40:09.44#ibcon#read 6, iclass 37, count 2 2006.168.07:40:09.44#ibcon#end of sib2, iclass 37, count 2 2006.168.07:40:09.44#ibcon#*after write, iclass 37, count 2 2006.168.07:40:09.44#ibcon#*before return 0, iclass 37, count 2 2006.168.07:40:09.44#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:40:09.44#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:40:09.44#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.168.07:40:09.44#ibcon#ireg 7 cls_cnt 0 2006.168.07:40:09.44#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:40:09.56#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:40:09.56#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:40:09.56#ibcon#enter wrdev, iclass 37, count 0 2006.168.07:40:09.56#ibcon#first serial, iclass 37, count 0 2006.168.07:40:09.56#ibcon#enter sib2, iclass 37, count 0 2006.168.07:40:09.56#ibcon#flushed, iclass 37, count 0 2006.168.07:40:09.56#ibcon#about to write, iclass 37, count 0 2006.168.07:40:09.56#ibcon#wrote, iclass 37, count 0 2006.168.07:40:09.56#ibcon#about to read 3, iclass 37, count 0 2006.168.07:40:09.58#ibcon#read 3, iclass 37, count 0 2006.168.07:40:09.58#ibcon#about to read 4, iclass 37, count 0 2006.168.07:40:09.58#ibcon#read 4, iclass 37, count 0 2006.168.07:40:09.58#ibcon#about to read 5, iclass 37, count 0 2006.168.07:40:09.58#ibcon#read 5, iclass 37, count 0 2006.168.07:40:09.58#ibcon#about to read 6, iclass 37, count 0 2006.168.07:40:09.58#ibcon#read 6, iclass 37, count 0 2006.168.07:40:09.58#ibcon#end of sib2, iclass 37, count 0 2006.168.07:40:09.58#ibcon#*mode == 0, iclass 37, count 0 2006.168.07:40:09.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.168.07:40:09.58#ibcon#[25=USB\r\n] 2006.168.07:40:09.58#ibcon#*before write, iclass 37, count 0 2006.168.07:40:09.58#ibcon#enter sib2, iclass 37, count 0 2006.168.07:40:09.58#ibcon#flushed, iclass 37, count 0 2006.168.07:40:09.58#ibcon#about to write, iclass 37, count 0 2006.168.07:40:09.58#ibcon#wrote, iclass 37, count 0 2006.168.07:40:09.58#ibcon#about to read 3, iclass 37, count 0 2006.168.07:40:09.61#ibcon#read 3, iclass 37, count 0 2006.168.07:40:09.61#ibcon#about to read 4, iclass 37, count 0 2006.168.07:40:09.61#ibcon#read 4, iclass 37, count 0 2006.168.07:40:09.61#ibcon#about to read 5, iclass 37, count 0 2006.168.07:40:09.61#ibcon#read 5, iclass 37, count 0 2006.168.07:40:09.61#ibcon#about to read 6, iclass 37, count 0 2006.168.07:40:09.61#ibcon#read 6, iclass 37, count 0 2006.168.07:40:09.61#ibcon#end of sib2, iclass 37, count 0 2006.168.07:40:09.61#ibcon#*after write, iclass 37, count 0 2006.168.07:40:09.61#ibcon#*before return 0, iclass 37, count 0 2006.168.07:40:09.61#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:40:09.61#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:40:09.61#ibcon#about to clear, iclass 37 cls_cnt 0 2006.168.07:40:09.61#ibcon#cleared, iclass 37 cls_cnt 0 2006.168.07:40:09.61$vc4f8/valo=6,772.99 2006.168.07:40:09.61#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.168.07:40:09.61#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.168.07:40:09.61#ibcon#ireg 17 cls_cnt 0 2006.168.07:40:09.61#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.168.07:40:09.61#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.168.07:40:09.61#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.168.07:40:09.61#ibcon#enter wrdev, iclass 39, count 0 2006.168.07:40:09.61#ibcon#first serial, iclass 39, count 0 2006.168.07:40:09.61#ibcon#enter sib2, iclass 39, count 0 2006.168.07:40:09.61#ibcon#flushed, iclass 39, count 0 2006.168.07:40:09.61#ibcon#about to write, iclass 39, count 0 2006.168.07:40:09.61#ibcon#wrote, iclass 39, count 0 2006.168.07:40:09.61#ibcon#about to read 3, iclass 39, count 0 2006.168.07:40:09.63#ibcon#read 3, iclass 39, count 0 2006.168.07:40:09.63#ibcon#about to read 4, iclass 39, count 0 2006.168.07:40:09.63#ibcon#read 4, iclass 39, count 0 2006.168.07:40:09.63#ibcon#about to read 5, iclass 39, count 0 2006.168.07:40:09.63#ibcon#read 5, iclass 39, count 0 2006.168.07:40:09.63#ibcon#about to read 6, iclass 39, count 0 2006.168.07:40:09.63#ibcon#read 6, iclass 39, count 0 2006.168.07:40:09.63#ibcon#end of sib2, iclass 39, count 0 2006.168.07:40:09.63#ibcon#*mode == 0, iclass 39, count 0 2006.168.07:40:09.63#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.168.07:40:09.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.07:40:09.63#ibcon#*before write, iclass 39, count 0 2006.168.07:40:09.63#ibcon#enter sib2, iclass 39, count 0 2006.168.07:40:09.63#ibcon#flushed, iclass 39, count 0 2006.168.07:40:09.63#ibcon#about to write, iclass 39, count 0 2006.168.07:40:09.63#ibcon#wrote, iclass 39, count 0 2006.168.07:40:09.63#ibcon#about to read 3, iclass 39, count 0 2006.168.07:40:09.67#ibcon#read 3, iclass 39, count 0 2006.168.07:40:09.67#ibcon#about to read 4, iclass 39, count 0 2006.168.07:40:09.67#ibcon#read 4, iclass 39, count 0 2006.168.07:40:09.67#ibcon#about to read 5, iclass 39, count 0 2006.168.07:40:09.67#ibcon#read 5, iclass 39, count 0 2006.168.07:40:09.67#ibcon#about to read 6, iclass 39, count 0 2006.168.07:40:09.67#ibcon#read 6, iclass 39, count 0 2006.168.07:40:09.67#ibcon#end of sib2, iclass 39, count 0 2006.168.07:40:09.67#ibcon#*after write, iclass 39, count 0 2006.168.07:40:09.67#ibcon#*before return 0, iclass 39, count 0 2006.168.07:40:09.67#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.168.07:40:09.67#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.168.07:40:09.67#ibcon#about to clear, iclass 39 cls_cnt 0 2006.168.07:40:09.67#ibcon#cleared, iclass 39 cls_cnt 0 2006.168.07:40:09.67$vc4f8/va=6,6 2006.168.07:40:09.67#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.168.07:40:09.67#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.168.07:40:09.67#ibcon#ireg 11 cls_cnt 2 2006.168.07:40:09.67#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.168.07:40:09.73#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.168.07:40:09.73#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.168.07:40:09.73#ibcon#enter wrdev, iclass 3, count 2 2006.168.07:40:09.73#ibcon#first serial, iclass 3, count 2 2006.168.07:40:09.73#ibcon#enter sib2, iclass 3, count 2 2006.168.07:40:09.73#ibcon#flushed, iclass 3, count 2 2006.168.07:40:09.73#ibcon#about to write, iclass 3, count 2 2006.168.07:40:09.73#ibcon#wrote, iclass 3, count 2 2006.168.07:40:09.73#ibcon#about to read 3, iclass 3, count 2 2006.168.07:40:09.75#ibcon#read 3, iclass 3, count 2 2006.168.07:40:09.75#ibcon#about to read 4, iclass 3, count 2 2006.168.07:40:09.75#ibcon#read 4, iclass 3, count 2 2006.168.07:40:09.75#ibcon#about to read 5, iclass 3, count 2 2006.168.07:40:09.75#ibcon#read 5, iclass 3, count 2 2006.168.07:40:09.75#ibcon#about to read 6, iclass 3, count 2 2006.168.07:40:09.75#ibcon#read 6, iclass 3, count 2 2006.168.07:40:09.75#ibcon#end of sib2, iclass 3, count 2 2006.168.07:40:09.75#ibcon#*mode == 0, iclass 3, count 2 2006.168.07:40:09.75#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.168.07:40:09.75#ibcon#[25=AT06-06\r\n] 2006.168.07:40:09.75#ibcon#*before write, iclass 3, count 2 2006.168.07:40:09.75#ibcon#enter sib2, iclass 3, count 2 2006.168.07:40:09.75#ibcon#flushed, iclass 3, count 2 2006.168.07:40:09.75#ibcon#about to write, iclass 3, count 2 2006.168.07:40:09.75#ibcon#wrote, iclass 3, count 2 2006.168.07:40:09.75#ibcon#about to read 3, iclass 3, count 2 2006.168.07:40:09.78#ibcon#read 3, iclass 3, count 2 2006.168.07:40:09.78#ibcon#about to read 4, iclass 3, count 2 2006.168.07:40:09.78#ibcon#read 4, iclass 3, count 2 2006.168.07:40:09.78#ibcon#about to read 5, iclass 3, count 2 2006.168.07:40:09.78#ibcon#read 5, iclass 3, count 2 2006.168.07:40:09.78#ibcon#about to read 6, iclass 3, count 2 2006.168.07:40:09.78#ibcon#read 6, iclass 3, count 2 2006.168.07:40:09.78#ibcon#end of sib2, iclass 3, count 2 2006.168.07:40:09.78#ibcon#*after write, iclass 3, count 2 2006.168.07:40:09.78#ibcon#*before return 0, iclass 3, count 2 2006.168.07:40:09.78#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.168.07:40:09.78#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.168.07:40:09.78#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.168.07:40:09.78#ibcon#ireg 7 cls_cnt 0 2006.168.07:40:09.78#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.168.07:40:09.90#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.168.07:40:09.90#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.168.07:40:09.90#ibcon#enter wrdev, iclass 3, count 0 2006.168.07:40:09.90#ibcon#first serial, iclass 3, count 0 2006.168.07:40:09.90#ibcon#enter sib2, iclass 3, count 0 2006.168.07:40:09.90#ibcon#flushed, iclass 3, count 0 2006.168.07:40:09.90#ibcon#about to write, iclass 3, count 0 2006.168.07:40:09.90#ibcon#wrote, iclass 3, count 0 2006.168.07:40:09.90#ibcon#about to read 3, iclass 3, count 0 2006.168.07:40:09.92#ibcon#read 3, iclass 3, count 0 2006.168.07:40:09.92#ibcon#about to read 4, iclass 3, count 0 2006.168.07:40:09.92#ibcon#read 4, iclass 3, count 0 2006.168.07:40:09.92#ibcon#about to read 5, iclass 3, count 0 2006.168.07:40:09.92#ibcon#read 5, iclass 3, count 0 2006.168.07:40:09.92#ibcon#about to read 6, iclass 3, count 0 2006.168.07:40:09.92#ibcon#read 6, iclass 3, count 0 2006.168.07:40:09.92#ibcon#end of sib2, iclass 3, count 0 2006.168.07:40:09.92#ibcon#*mode == 0, iclass 3, count 0 2006.168.07:40:09.92#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.168.07:40:09.92#ibcon#[25=USB\r\n] 2006.168.07:40:09.92#ibcon#*before write, iclass 3, count 0 2006.168.07:40:09.92#ibcon#enter sib2, iclass 3, count 0 2006.168.07:40:09.92#ibcon#flushed, iclass 3, count 0 2006.168.07:40:09.92#ibcon#about to write, iclass 3, count 0 2006.168.07:40:09.92#ibcon#wrote, iclass 3, count 0 2006.168.07:40:09.92#ibcon#about to read 3, iclass 3, count 0 2006.168.07:40:09.95#ibcon#read 3, iclass 3, count 0 2006.168.07:40:09.95#ibcon#about to read 4, iclass 3, count 0 2006.168.07:40:09.95#ibcon#read 4, iclass 3, count 0 2006.168.07:40:09.95#ibcon#about to read 5, iclass 3, count 0 2006.168.07:40:09.95#ibcon#read 5, iclass 3, count 0 2006.168.07:40:09.95#ibcon#about to read 6, iclass 3, count 0 2006.168.07:40:09.95#ibcon#read 6, iclass 3, count 0 2006.168.07:40:09.95#ibcon#end of sib2, iclass 3, count 0 2006.168.07:40:09.95#ibcon#*after write, iclass 3, count 0 2006.168.07:40:09.95#ibcon#*before return 0, iclass 3, count 0 2006.168.07:40:09.95#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.168.07:40:09.95#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.168.07:40:09.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.168.07:40:09.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.168.07:40:09.95$vc4f8/valo=7,832.99 2006.168.07:40:09.95#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.168.07:40:09.95#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.168.07:40:09.95#ibcon#ireg 17 cls_cnt 0 2006.168.07:40:09.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.168.07:40:09.95#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.168.07:40:09.95#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.168.07:40:09.95#ibcon#enter wrdev, iclass 5, count 0 2006.168.07:40:09.95#ibcon#first serial, iclass 5, count 0 2006.168.07:40:09.95#ibcon#enter sib2, iclass 5, count 0 2006.168.07:40:09.95#ibcon#flushed, iclass 5, count 0 2006.168.07:40:09.95#ibcon#about to write, iclass 5, count 0 2006.168.07:40:09.95#ibcon#wrote, iclass 5, count 0 2006.168.07:40:09.95#ibcon#about to read 3, iclass 5, count 0 2006.168.07:40:09.97#ibcon#read 3, iclass 5, count 0 2006.168.07:40:09.97#ibcon#about to read 4, iclass 5, count 0 2006.168.07:40:09.97#ibcon#read 4, iclass 5, count 0 2006.168.07:40:09.97#ibcon#about to read 5, iclass 5, count 0 2006.168.07:40:09.97#ibcon#read 5, iclass 5, count 0 2006.168.07:40:09.97#ibcon#about to read 6, iclass 5, count 0 2006.168.07:40:09.97#ibcon#read 6, iclass 5, count 0 2006.168.07:40:09.97#ibcon#end of sib2, iclass 5, count 0 2006.168.07:40:09.97#ibcon#*mode == 0, iclass 5, count 0 2006.168.07:40:09.97#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.168.07:40:09.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.07:40:09.97#ibcon#*before write, iclass 5, count 0 2006.168.07:40:09.97#ibcon#enter sib2, iclass 5, count 0 2006.168.07:40:09.97#ibcon#flushed, iclass 5, count 0 2006.168.07:40:09.97#ibcon#about to write, iclass 5, count 0 2006.168.07:40:09.97#ibcon#wrote, iclass 5, count 0 2006.168.07:40:09.97#ibcon#about to read 3, iclass 5, count 0 2006.168.07:40:10.01#ibcon#read 3, iclass 5, count 0 2006.168.07:40:10.01#ibcon#about to read 4, iclass 5, count 0 2006.168.07:40:10.01#ibcon#read 4, iclass 5, count 0 2006.168.07:40:10.01#ibcon#about to read 5, iclass 5, count 0 2006.168.07:40:10.01#ibcon#read 5, iclass 5, count 0 2006.168.07:40:10.01#ibcon#about to read 6, iclass 5, count 0 2006.168.07:40:10.01#ibcon#read 6, iclass 5, count 0 2006.168.07:40:10.01#ibcon#end of sib2, iclass 5, count 0 2006.168.07:40:10.01#ibcon#*after write, iclass 5, count 0 2006.168.07:40:10.01#ibcon#*before return 0, iclass 5, count 0 2006.168.07:40:10.01#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.168.07:40:10.01#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.168.07:40:10.01#ibcon#about to clear, iclass 5 cls_cnt 0 2006.168.07:40:10.01#ibcon#cleared, iclass 5 cls_cnt 0 2006.168.07:40:10.01$vc4f8/va=7,6 2006.168.07:40:10.01#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.168.07:40:10.01#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.168.07:40:10.01#ibcon#ireg 11 cls_cnt 2 2006.168.07:40:10.01#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.168.07:40:10.07#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.168.07:40:10.07#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.168.07:40:10.07#ibcon#enter wrdev, iclass 7, count 2 2006.168.07:40:10.07#ibcon#first serial, iclass 7, count 2 2006.168.07:40:10.07#ibcon#enter sib2, iclass 7, count 2 2006.168.07:40:10.07#ibcon#flushed, iclass 7, count 2 2006.168.07:40:10.07#ibcon#about to write, iclass 7, count 2 2006.168.07:40:10.07#ibcon#wrote, iclass 7, count 2 2006.168.07:40:10.07#ibcon#about to read 3, iclass 7, count 2 2006.168.07:40:10.09#ibcon#read 3, iclass 7, count 2 2006.168.07:40:10.09#ibcon#about to read 4, iclass 7, count 2 2006.168.07:40:10.09#ibcon#read 4, iclass 7, count 2 2006.168.07:40:10.09#ibcon#about to read 5, iclass 7, count 2 2006.168.07:40:10.09#ibcon#read 5, iclass 7, count 2 2006.168.07:40:10.09#ibcon#about to read 6, iclass 7, count 2 2006.168.07:40:10.09#ibcon#read 6, iclass 7, count 2 2006.168.07:40:10.09#ibcon#end of sib2, iclass 7, count 2 2006.168.07:40:10.09#ibcon#*mode == 0, iclass 7, count 2 2006.168.07:40:10.09#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.168.07:40:10.09#ibcon#[25=AT07-06\r\n] 2006.168.07:40:10.09#ibcon#*before write, iclass 7, count 2 2006.168.07:40:10.09#ibcon#enter sib2, iclass 7, count 2 2006.168.07:40:10.09#ibcon#flushed, iclass 7, count 2 2006.168.07:40:10.09#ibcon#about to write, iclass 7, count 2 2006.168.07:40:10.09#ibcon#wrote, iclass 7, count 2 2006.168.07:40:10.09#ibcon#about to read 3, iclass 7, count 2 2006.168.07:40:10.12#ibcon#read 3, iclass 7, count 2 2006.168.07:40:10.12#ibcon#about to read 4, iclass 7, count 2 2006.168.07:40:10.12#ibcon#read 4, iclass 7, count 2 2006.168.07:40:10.12#ibcon#about to read 5, iclass 7, count 2 2006.168.07:40:10.12#ibcon#read 5, iclass 7, count 2 2006.168.07:40:10.12#ibcon#about to read 6, iclass 7, count 2 2006.168.07:40:10.12#ibcon#read 6, iclass 7, count 2 2006.168.07:40:10.12#ibcon#end of sib2, iclass 7, count 2 2006.168.07:40:10.12#ibcon#*after write, iclass 7, count 2 2006.168.07:40:10.12#ibcon#*before return 0, iclass 7, count 2 2006.168.07:40:10.12#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.168.07:40:10.12#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.168.07:40:10.12#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.168.07:40:10.12#ibcon#ireg 7 cls_cnt 0 2006.168.07:40:10.12#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.168.07:40:10.24#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.168.07:40:10.24#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.168.07:40:10.24#ibcon#enter wrdev, iclass 7, count 0 2006.168.07:40:10.24#ibcon#first serial, iclass 7, count 0 2006.168.07:40:10.24#ibcon#enter sib2, iclass 7, count 0 2006.168.07:40:10.24#ibcon#flushed, iclass 7, count 0 2006.168.07:40:10.24#ibcon#about to write, iclass 7, count 0 2006.168.07:40:10.24#ibcon#wrote, iclass 7, count 0 2006.168.07:40:10.24#ibcon#about to read 3, iclass 7, count 0 2006.168.07:40:10.26#ibcon#read 3, iclass 7, count 0 2006.168.07:40:10.26#ibcon#about to read 4, iclass 7, count 0 2006.168.07:40:10.26#ibcon#read 4, iclass 7, count 0 2006.168.07:40:10.26#ibcon#about to read 5, iclass 7, count 0 2006.168.07:40:10.26#ibcon#read 5, iclass 7, count 0 2006.168.07:40:10.26#ibcon#about to read 6, iclass 7, count 0 2006.168.07:40:10.26#ibcon#read 6, iclass 7, count 0 2006.168.07:40:10.26#ibcon#end of sib2, iclass 7, count 0 2006.168.07:40:10.26#ibcon#*mode == 0, iclass 7, count 0 2006.168.07:40:10.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.168.07:40:10.26#ibcon#[25=USB\r\n] 2006.168.07:40:10.26#ibcon#*before write, iclass 7, count 0 2006.168.07:40:10.26#ibcon#enter sib2, iclass 7, count 0 2006.168.07:40:10.26#ibcon#flushed, iclass 7, count 0 2006.168.07:40:10.26#ibcon#about to write, iclass 7, count 0 2006.168.07:40:10.26#ibcon#wrote, iclass 7, count 0 2006.168.07:40:10.26#ibcon#about to read 3, iclass 7, count 0 2006.168.07:40:10.29#ibcon#read 3, iclass 7, count 0 2006.168.07:40:10.29#ibcon#about to read 4, iclass 7, count 0 2006.168.07:40:10.29#ibcon#read 4, iclass 7, count 0 2006.168.07:40:10.29#ibcon#about to read 5, iclass 7, count 0 2006.168.07:40:10.29#ibcon#read 5, iclass 7, count 0 2006.168.07:40:10.29#ibcon#about to read 6, iclass 7, count 0 2006.168.07:40:10.29#ibcon#read 6, iclass 7, count 0 2006.168.07:40:10.29#ibcon#end of sib2, iclass 7, count 0 2006.168.07:40:10.29#ibcon#*after write, iclass 7, count 0 2006.168.07:40:10.29#ibcon#*before return 0, iclass 7, count 0 2006.168.07:40:10.29#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.168.07:40:10.29#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.168.07:40:10.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.168.07:40:10.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.168.07:40:10.29$vc4f8/valo=8,852.99 2006.168.07:40:10.29#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.168.07:40:10.29#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.168.07:40:10.29#ibcon#ireg 17 cls_cnt 0 2006.168.07:40:10.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.168.07:40:10.29#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.168.07:40:10.29#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.168.07:40:10.29#ibcon#enter wrdev, iclass 11, count 0 2006.168.07:40:10.29#ibcon#first serial, iclass 11, count 0 2006.168.07:40:10.29#ibcon#enter sib2, iclass 11, count 0 2006.168.07:40:10.29#ibcon#flushed, iclass 11, count 0 2006.168.07:40:10.29#ibcon#about to write, iclass 11, count 0 2006.168.07:40:10.29#ibcon#wrote, iclass 11, count 0 2006.168.07:40:10.29#ibcon#about to read 3, iclass 11, count 0 2006.168.07:40:10.31#ibcon#read 3, iclass 11, count 0 2006.168.07:40:10.31#ibcon#about to read 4, iclass 11, count 0 2006.168.07:40:10.31#ibcon#read 4, iclass 11, count 0 2006.168.07:40:10.31#ibcon#about to read 5, iclass 11, count 0 2006.168.07:40:10.31#ibcon#read 5, iclass 11, count 0 2006.168.07:40:10.31#ibcon#about to read 6, iclass 11, count 0 2006.168.07:40:10.31#ibcon#read 6, iclass 11, count 0 2006.168.07:40:10.31#ibcon#end of sib2, iclass 11, count 0 2006.168.07:40:10.31#ibcon#*mode == 0, iclass 11, count 0 2006.168.07:40:10.31#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.168.07:40:10.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.07:40:10.31#ibcon#*before write, iclass 11, count 0 2006.168.07:40:10.31#ibcon#enter sib2, iclass 11, count 0 2006.168.07:40:10.31#ibcon#flushed, iclass 11, count 0 2006.168.07:40:10.31#ibcon#about to write, iclass 11, count 0 2006.168.07:40:10.31#ibcon#wrote, iclass 11, count 0 2006.168.07:40:10.31#ibcon#about to read 3, iclass 11, count 0 2006.168.07:40:10.35#ibcon#read 3, iclass 11, count 0 2006.168.07:40:10.35#ibcon#about to read 4, iclass 11, count 0 2006.168.07:40:10.35#ibcon#read 4, iclass 11, count 0 2006.168.07:40:10.35#ibcon#about to read 5, iclass 11, count 0 2006.168.07:40:10.35#ibcon#read 5, iclass 11, count 0 2006.168.07:40:10.35#ibcon#about to read 6, iclass 11, count 0 2006.168.07:40:10.35#ibcon#read 6, iclass 11, count 0 2006.168.07:40:10.35#ibcon#end of sib2, iclass 11, count 0 2006.168.07:40:10.35#ibcon#*after write, iclass 11, count 0 2006.168.07:40:10.35#ibcon#*before return 0, iclass 11, count 0 2006.168.07:40:10.35#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.168.07:40:10.35#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.168.07:40:10.35#ibcon#about to clear, iclass 11 cls_cnt 0 2006.168.07:40:10.35#ibcon#cleared, iclass 11 cls_cnt 0 2006.168.07:40:10.35$vc4f8/va=8,7 2006.168.07:40:10.35#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.168.07:40:10.35#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.168.07:40:10.35#ibcon#ireg 11 cls_cnt 2 2006.168.07:40:10.35#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.168.07:40:10.41#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.168.07:40:10.41#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.168.07:40:10.41#ibcon#enter wrdev, iclass 13, count 2 2006.168.07:40:10.41#ibcon#first serial, iclass 13, count 2 2006.168.07:40:10.41#ibcon#enter sib2, iclass 13, count 2 2006.168.07:40:10.41#ibcon#flushed, iclass 13, count 2 2006.168.07:40:10.41#ibcon#about to write, iclass 13, count 2 2006.168.07:40:10.41#ibcon#wrote, iclass 13, count 2 2006.168.07:40:10.41#ibcon#about to read 3, iclass 13, count 2 2006.168.07:40:10.43#ibcon#read 3, iclass 13, count 2 2006.168.07:40:10.43#ibcon#about to read 4, iclass 13, count 2 2006.168.07:40:10.43#ibcon#read 4, iclass 13, count 2 2006.168.07:40:10.43#ibcon#about to read 5, iclass 13, count 2 2006.168.07:40:10.43#ibcon#read 5, iclass 13, count 2 2006.168.07:40:10.43#ibcon#about to read 6, iclass 13, count 2 2006.168.07:40:10.43#ibcon#read 6, iclass 13, count 2 2006.168.07:40:10.43#ibcon#end of sib2, iclass 13, count 2 2006.168.07:40:10.43#ibcon#*mode == 0, iclass 13, count 2 2006.168.07:40:10.43#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.168.07:40:10.43#ibcon#[25=AT08-07\r\n] 2006.168.07:40:10.43#ibcon#*before write, iclass 13, count 2 2006.168.07:40:10.43#ibcon#enter sib2, iclass 13, count 2 2006.168.07:40:10.43#ibcon#flushed, iclass 13, count 2 2006.168.07:40:10.43#ibcon#about to write, iclass 13, count 2 2006.168.07:40:10.43#ibcon#wrote, iclass 13, count 2 2006.168.07:40:10.43#ibcon#about to read 3, iclass 13, count 2 2006.168.07:40:10.46#ibcon#read 3, iclass 13, count 2 2006.168.07:40:10.46#ibcon#about to read 4, iclass 13, count 2 2006.168.07:40:10.46#ibcon#read 4, iclass 13, count 2 2006.168.07:40:10.46#ibcon#about to read 5, iclass 13, count 2 2006.168.07:40:10.46#ibcon#read 5, iclass 13, count 2 2006.168.07:40:10.46#ibcon#about to read 6, iclass 13, count 2 2006.168.07:40:10.46#ibcon#read 6, iclass 13, count 2 2006.168.07:40:10.46#ibcon#end of sib2, iclass 13, count 2 2006.168.07:40:10.46#ibcon#*after write, iclass 13, count 2 2006.168.07:40:10.46#ibcon#*before return 0, iclass 13, count 2 2006.168.07:40:10.46#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.168.07:40:10.46#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.168.07:40:10.46#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.168.07:40:10.46#ibcon#ireg 7 cls_cnt 0 2006.168.07:40:10.46#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.168.07:40:10.58#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.168.07:40:10.58#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.168.07:40:10.58#ibcon#enter wrdev, iclass 13, count 0 2006.168.07:40:10.58#ibcon#first serial, iclass 13, count 0 2006.168.07:40:10.58#ibcon#enter sib2, iclass 13, count 0 2006.168.07:40:10.58#ibcon#flushed, iclass 13, count 0 2006.168.07:40:10.58#ibcon#about to write, iclass 13, count 0 2006.168.07:40:10.58#ibcon#wrote, iclass 13, count 0 2006.168.07:40:10.58#ibcon#about to read 3, iclass 13, count 0 2006.168.07:40:10.60#ibcon#read 3, iclass 13, count 0 2006.168.07:40:10.60#ibcon#about to read 4, iclass 13, count 0 2006.168.07:40:10.60#ibcon#read 4, iclass 13, count 0 2006.168.07:40:10.60#ibcon#about to read 5, iclass 13, count 0 2006.168.07:40:10.60#ibcon#read 5, iclass 13, count 0 2006.168.07:40:10.60#ibcon#about to read 6, iclass 13, count 0 2006.168.07:40:10.60#ibcon#read 6, iclass 13, count 0 2006.168.07:40:10.60#ibcon#end of sib2, iclass 13, count 0 2006.168.07:40:10.60#ibcon#*mode == 0, iclass 13, count 0 2006.168.07:40:10.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.168.07:40:10.60#ibcon#[25=USB\r\n] 2006.168.07:40:10.60#ibcon#*before write, iclass 13, count 0 2006.168.07:40:10.60#ibcon#enter sib2, iclass 13, count 0 2006.168.07:40:10.60#ibcon#flushed, iclass 13, count 0 2006.168.07:40:10.60#ibcon#about to write, iclass 13, count 0 2006.168.07:40:10.60#ibcon#wrote, iclass 13, count 0 2006.168.07:40:10.60#ibcon#about to read 3, iclass 13, count 0 2006.168.07:40:10.63#ibcon#read 3, iclass 13, count 0 2006.168.07:40:10.63#ibcon#about to read 4, iclass 13, count 0 2006.168.07:40:10.63#ibcon#read 4, iclass 13, count 0 2006.168.07:40:10.63#ibcon#about to read 5, iclass 13, count 0 2006.168.07:40:10.63#ibcon#read 5, iclass 13, count 0 2006.168.07:40:10.63#ibcon#about to read 6, iclass 13, count 0 2006.168.07:40:10.63#ibcon#read 6, iclass 13, count 0 2006.168.07:40:10.63#ibcon#end of sib2, iclass 13, count 0 2006.168.07:40:10.63#ibcon#*after write, iclass 13, count 0 2006.168.07:40:10.63#ibcon#*before return 0, iclass 13, count 0 2006.168.07:40:10.63#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.168.07:40:10.63#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.168.07:40:10.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.168.07:40:10.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.168.07:40:10.63$vc4f8/vblo=1,632.99 2006.168.07:40:10.63#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.168.07:40:10.63#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.168.07:40:10.63#ibcon#ireg 17 cls_cnt 0 2006.168.07:40:10.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:40:10.63#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:40:10.63#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:40:10.63#ibcon#enter wrdev, iclass 15, count 0 2006.168.07:40:10.63#ibcon#first serial, iclass 15, count 0 2006.168.07:40:10.63#ibcon#enter sib2, iclass 15, count 0 2006.168.07:40:10.63#ibcon#flushed, iclass 15, count 0 2006.168.07:40:10.63#ibcon#about to write, iclass 15, count 0 2006.168.07:40:10.63#ibcon#wrote, iclass 15, count 0 2006.168.07:40:10.63#ibcon#about to read 3, iclass 15, count 0 2006.168.07:40:10.65#ibcon#read 3, iclass 15, count 0 2006.168.07:40:10.65#ibcon#about to read 4, iclass 15, count 0 2006.168.07:40:10.65#ibcon#read 4, iclass 15, count 0 2006.168.07:40:10.65#ibcon#about to read 5, iclass 15, count 0 2006.168.07:40:10.65#ibcon#read 5, iclass 15, count 0 2006.168.07:40:10.65#ibcon#about to read 6, iclass 15, count 0 2006.168.07:40:10.65#ibcon#read 6, iclass 15, count 0 2006.168.07:40:10.65#ibcon#end of sib2, iclass 15, count 0 2006.168.07:40:10.65#ibcon#*mode == 0, iclass 15, count 0 2006.168.07:40:10.65#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.168.07:40:10.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.07:40:10.65#ibcon#*before write, iclass 15, count 0 2006.168.07:40:10.65#ibcon#enter sib2, iclass 15, count 0 2006.168.07:40:10.65#ibcon#flushed, iclass 15, count 0 2006.168.07:40:10.65#ibcon#about to write, iclass 15, count 0 2006.168.07:40:10.65#ibcon#wrote, iclass 15, count 0 2006.168.07:40:10.65#ibcon#about to read 3, iclass 15, count 0 2006.168.07:40:10.69#ibcon#read 3, iclass 15, count 0 2006.168.07:40:10.69#ibcon#about to read 4, iclass 15, count 0 2006.168.07:40:10.69#ibcon#read 4, iclass 15, count 0 2006.168.07:40:10.69#ibcon#about to read 5, iclass 15, count 0 2006.168.07:40:10.69#ibcon#read 5, iclass 15, count 0 2006.168.07:40:10.69#ibcon#about to read 6, iclass 15, count 0 2006.168.07:40:10.69#ibcon#read 6, iclass 15, count 0 2006.168.07:40:10.69#ibcon#end of sib2, iclass 15, count 0 2006.168.07:40:10.69#ibcon#*after write, iclass 15, count 0 2006.168.07:40:10.69#ibcon#*before return 0, iclass 15, count 0 2006.168.07:40:10.69#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:40:10.69#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:40:10.69#ibcon#about to clear, iclass 15 cls_cnt 0 2006.168.07:40:10.69#ibcon#cleared, iclass 15 cls_cnt 0 2006.168.07:40:10.69$vc4f8/vb=1,4 2006.168.07:40:10.69#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.168.07:40:10.69#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.168.07:40:10.69#ibcon#ireg 11 cls_cnt 2 2006.168.07:40:10.69#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.168.07:40:10.69#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.168.07:40:10.69#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.168.07:40:10.69#ibcon#enter wrdev, iclass 17, count 2 2006.168.07:40:10.69#ibcon#first serial, iclass 17, count 2 2006.168.07:40:10.69#ibcon#enter sib2, iclass 17, count 2 2006.168.07:40:10.69#ibcon#flushed, iclass 17, count 2 2006.168.07:40:10.69#ibcon#about to write, iclass 17, count 2 2006.168.07:40:10.69#ibcon#wrote, iclass 17, count 2 2006.168.07:40:10.69#ibcon#about to read 3, iclass 17, count 2 2006.168.07:40:10.71#ibcon#read 3, iclass 17, count 2 2006.168.07:40:10.71#ibcon#about to read 4, iclass 17, count 2 2006.168.07:40:10.71#ibcon#read 4, iclass 17, count 2 2006.168.07:40:10.71#ibcon#about to read 5, iclass 17, count 2 2006.168.07:40:10.71#ibcon#read 5, iclass 17, count 2 2006.168.07:40:10.71#ibcon#about to read 6, iclass 17, count 2 2006.168.07:40:10.71#ibcon#read 6, iclass 17, count 2 2006.168.07:40:10.71#ibcon#end of sib2, iclass 17, count 2 2006.168.07:40:10.71#ibcon#*mode == 0, iclass 17, count 2 2006.168.07:40:10.71#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.168.07:40:10.71#ibcon#[27=AT01-04\r\n] 2006.168.07:40:10.71#ibcon#*before write, iclass 17, count 2 2006.168.07:40:10.71#ibcon#enter sib2, iclass 17, count 2 2006.168.07:40:10.71#ibcon#flushed, iclass 17, count 2 2006.168.07:40:10.71#ibcon#about to write, iclass 17, count 2 2006.168.07:40:10.71#ibcon#wrote, iclass 17, count 2 2006.168.07:40:10.71#ibcon#about to read 3, iclass 17, count 2 2006.168.07:40:10.74#ibcon#read 3, iclass 17, count 2 2006.168.07:40:10.74#ibcon#about to read 4, iclass 17, count 2 2006.168.07:40:10.74#ibcon#read 4, iclass 17, count 2 2006.168.07:40:10.74#ibcon#about to read 5, iclass 17, count 2 2006.168.07:40:10.74#ibcon#read 5, iclass 17, count 2 2006.168.07:40:10.74#ibcon#about to read 6, iclass 17, count 2 2006.168.07:40:10.74#ibcon#read 6, iclass 17, count 2 2006.168.07:40:10.74#ibcon#end of sib2, iclass 17, count 2 2006.168.07:40:10.74#ibcon#*after write, iclass 17, count 2 2006.168.07:40:10.74#ibcon#*before return 0, iclass 17, count 2 2006.168.07:40:10.74#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.168.07:40:10.74#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.168.07:40:10.74#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.168.07:40:10.74#ibcon#ireg 7 cls_cnt 0 2006.168.07:40:10.74#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.168.07:40:10.86#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.168.07:40:10.86#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.168.07:40:10.86#ibcon#enter wrdev, iclass 17, count 0 2006.168.07:40:10.86#ibcon#first serial, iclass 17, count 0 2006.168.07:40:10.86#ibcon#enter sib2, iclass 17, count 0 2006.168.07:40:10.86#ibcon#flushed, iclass 17, count 0 2006.168.07:40:10.86#ibcon#about to write, iclass 17, count 0 2006.168.07:40:10.86#ibcon#wrote, iclass 17, count 0 2006.168.07:40:10.86#ibcon#about to read 3, iclass 17, count 0 2006.168.07:40:10.88#ibcon#read 3, iclass 17, count 0 2006.168.07:40:10.88#ibcon#about to read 4, iclass 17, count 0 2006.168.07:40:10.88#ibcon#read 4, iclass 17, count 0 2006.168.07:40:10.88#ibcon#about to read 5, iclass 17, count 0 2006.168.07:40:10.88#ibcon#read 5, iclass 17, count 0 2006.168.07:40:10.88#ibcon#about to read 6, iclass 17, count 0 2006.168.07:40:10.88#ibcon#read 6, iclass 17, count 0 2006.168.07:40:10.88#ibcon#end of sib2, iclass 17, count 0 2006.168.07:40:10.88#ibcon#*mode == 0, iclass 17, count 0 2006.168.07:40:10.88#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.168.07:40:10.88#ibcon#[27=USB\r\n] 2006.168.07:40:10.88#ibcon#*before write, iclass 17, count 0 2006.168.07:40:10.88#ibcon#enter sib2, iclass 17, count 0 2006.168.07:40:10.88#ibcon#flushed, iclass 17, count 0 2006.168.07:40:10.88#ibcon#about to write, iclass 17, count 0 2006.168.07:40:10.88#ibcon#wrote, iclass 17, count 0 2006.168.07:40:10.88#ibcon#about to read 3, iclass 17, count 0 2006.168.07:40:10.91#ibcon#read 3, iclass 17, count 0 2006.168.07:40:10.91#ibcon#about to read 4, iclass 17, count 0 2006.168.07:40:10.91#ibcon#read 4, iclass 17, count 0 2006.168.07:40:10.91#ibcon#about to read 5, iclass 17, count 0 2006.168.07:40:10.91#ibcon#read 5, iclass 17, count 0 2006.168.07:40:10.91#ibcon#about to read 6, iclass 17, count 0 2006.168.07:40:10.91#ibcon#read 6, iclass 17, count 0 2006.168.07:40:10.91#ibcon#end of sib2, iclass 17, count 0 2006.168.07:40:10.91#ibcon#*after write, iclass 17, count 0 2006.168.07:40:10.91#ibcon#*before return 0, iclass 17, count 0 2006.168.07:40:10.91#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.168.07:40:10.91#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.168.07:40:10.91#ibcon#about to clear, iclass 17 cls_cnt 0 2006.168.07:40:10.91#ibcon#cleared, iclass 17 cls_cnt 0 2006.168.07:40:10.91$vc4f8/vblo=2,640.99 2006.168.07:40:10.91#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.168.07:40:10.91#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.168.07:40:10.91#ibcon#ireg 17 cls_cnt 0 2006.168.07:40:10.91#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:40:10.91#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:40:10.91#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:40:10.91#ibcon#enter wrdev, iclass 19, count 0 2006.168.07:40:10.91#ibcon#first serial, iclass 19, count 0 2006.168.07:40:10.91#ibcon#enter sib2, iclass 19, count 0 2006.168.07:40:10.91#ibcon#flushed, iclass 19, count 0 2006.168.07:40:10.91#ibcon#about to write, iclass 19, count 0 2006.168.07:40:10.91#ibcon#wrote, iclass 19, count 0 2006.168.07:40:10.91#ibcon#about to read 3, iclass 19, count 0 2006.168.07:40:10.93#ibcon#read 3, iclass 19, count 0 2006.168.07:40:10.93#ibcon#about to read 4, iclass 19, count 0 2006.168.07:40:10.93#ibcon#read 4, iclass 19, count 0 2006.168.07:40:10.93#ibcon#about to read 5, iclass 19, count 0 2006.168.07:40:10.93#ibcon#read 5, iclass 19, count 0 2006.168.07:40:10.93#ibcon#about to read 6, iclass 19, count 0 2006.168.07:40:10.93#ibcon#read 6, iclass 19, count 0 2006.168.07:40:10.93#ibcon#end of sib2, iclass 19, count 0 2006.168.07:40:10.93#ibcon#*mode == 0, iclass 19, count 0 2006.168.07:40:10.93#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.168.07:40:10.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.07:40:10.93#ibcon#*before write, iclass 19, count 0 2006.168.07:40:10.93#ibcon#enter sib2, iclass 19, count 0 2006.168.07:40:10.93#ibcon#flushed, iclass 19, count 0 2006.168.07:40:10.93#ibcon#about to write, iclass 19, count 0 2006.168.07:40:10.93#ibcon#wrote, iclass 19, count 0 2006.168.07:40:10.93#ibcon#about to read 3, iclass 19, count 0 2006.168.07:40:10.97#ibcon#read 3, iclass 19, count 0 2006.168.07:40:10.97#ibcon#about to read 4, iclass 19, count 0 2006.168.07:40:10.97#ibcon#read 4, iclass 19, count 0 2006.168.07:40:10.97#ibcon#about to read 5, iclass 19, count 0 2006.168.07:40:10.97#ibcon#read 5, iclass 19, count 0 2006.168.07:40:10.97#ibcon#about to read 6, iclass 19, count 0 2006.168.07:40:10.97#ibcon#read 6, iclass 19, count 0 2006.168.07:40:10.97#ibcon#end of sib2, iclass 19, count 0 2006.168.07:40:10.97#ibcon#*after write, iclass 19, count 0 2006.168.07:40:10.97#ibcon#*before return 0, iclass 19, count 0 2006.168.07:40:10.97#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:40:10.97#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:40:10.97#ibcon#about to clear, iclass 19 cls_cnt 0 2006.168.07:40:10.97#ibcon#cleared, iclass 19 cls_cnt 0 2006.168.07:40:10.97$vc4f8/vb=2,4 2006.168.07:40:10.97#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.168.07:40:10.97#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.168.07:40:10.97#ibcon#ireg 11 cls_cnt 2 2006.168.07:40:10.97#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.168.07:40:11.03#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.168.07:40:11.03#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.168.07:40:11.03#ibcon#enter wrdev, iclass 21, count 2 2006.168.07:40:11.03#ibcon#first serial, iclass 21, count 2 2006.168.07:40:11.03#ibcon#enter sib2, iclass 21, count 2 2006.168.07:40:11.03#ibcon#flushed, iclass 21, count 2 2006.168.07:40:11.03#ibcon#about to write, iclass 21, count 2 2006.168.07:40:11.03#ibcon#wrote, iclass 21, count 2 2006.168.07:40:11.03#ibcon#about to read 3, iclass 21, count 2 2006.168.07:40:11.05#ibcon#read 3, iclass 21, count 2 2006.168.07:40:11.05#ibcon#about to read 4, iclass 21, count 2 2006.168.07:40:11.05#ibcon#read 4, iclass 21, count 2 2006.168.07:40:11.05#ibcon#about to read 5, iclass 21, count 2 2006.168.07:40:11.05#ibcon#read 5, iclass 21, count 2 2006.168.07:40:11.05#ibcon#about to read 6, iclass 21, count 2 2006.168.07:40:11.05#ibcon#read 6, iclass 21, count 2 2006.168.07:40:11.05#ibcon#end of sib2, iclass 21, count 2 2006.168.07:40:11.05#ibcon#*mode == 0, iclass 21, count 2 2006.168.07:40:11.05#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.168.07:40:11.05#ibcon#[27=AT02-04\r\n] 2006.168.07:40:11.05#ibcon#*before write, iclass 21, count 2 2006.168.07:40:11.05#ibcon#enter sib2, iclass 21, count 2 2006.168.07:40:11.05#ibcon#flushed, iclass 21, count 2 2006.168.07:40:11.05#ibcon#about to write, iclass 21, count 2 2006.168.07:40:11.05#ibcon#wrote, iclass 21, count 2 2006.168.07:40:11.05#ibcon#about to read 3, iclass 21, count 2 2006.168.07:40:11.08#ibcon#read 3, iclass 21, count 2 2006.168.07:40:11.08#ibcon#about to read 4, iclass 21, count 2 2006.168.07:40:11.08#ibcon#read 4, iclass 21, count 2 2006.168.07:40:11.08#ibcon#about to read 5, iclass 21, count 2 2006.168.07:40:11.08#ibcon#read 5, iclass 21, count 2 2006.168.07:40:11.08#ibcon#about to read 6, iclass 21, count 2 2006.168.07:40:11.08#ibcon#read 6, iclass 21, count 2 2006.168.07:40:11.08#ibcon#end of sib2, iclass 21, count 2 2006.168.07:40:11.08#ibcon#*after write, iclass 21, count 2 2006.168.07:40:11.08#ibcon#*before return 0, iclass 21, count 2 2006.168.07:40:11.08#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.168.07:40:11.08#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.168.07:40:11.08#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.168.07:40:11.08#ibcon#ireg 7 cls_cnt 0 2006.168.07:40:11.08#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.168.07:40:11.20#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.168.07:40:11.20#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.168.07:40:11.20#ibcon#enter wrdev, iclass 21, count 0 2006.168.07:40:11.20#ibcon#first serial, iclass 21, count 0 2006.168.07:40:11.20#ibcon#enter sib2, iclass 21, count 0 2006.168.07:40:11.20#ibcon#flushed, iclass 21, count 0 2006.168.07:40:11.20#ibcon#about to write, iclass 21, count 0 2006.168.07:40:11.20#ibcon#wrote, iclass 21, count 0 2006.168.07:40:11.20#ibcon#about to read 3, iclass 21, count 0 2006.168.07:40:11.22#ibcon#read 3, iclass 21, count 0 2006.168.07:40:11.22#ibcon#about to read 4, iclass 21, count 0 2006.168.07:40:11.22#ibcon#read 4, iclass 21, count 0 2006.168.07:40:11.22#ibcon#about to read 5, iclass 21, count 0 2006.168.07:40:11.22#ibcon#read 5, iclass 21, count 0 2006.168.07:40:11.22#ibcon#about to read 6, iclass 21, count 0 2006.168.07:40:11.22#ibcon#read 6, iclass 21, count 0 2006.168.07:40:11.22#ibcon#end of sib2, iclass 21, count 0 2006.168.07:40:11.22#ibcon#*mode == 0, iclass 21, count 0 2006.168.07:40:11.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.168.07:40:11.22#ibcon#[27=USB\r\n] 2006.168.07:40:11.22#ibcon#*before write, iclass 21, count 0 2006.168.07:40:11.22#ibcon#enter sib2, iclass 21, count 0 2006.168.07:40:11.22#ibcon#flushed, iclass 21, count 0 2006.168.07:40:11.22#ibcon#about to write, iclass 21, count 0 2006.168.07:40:11.22#ibcon#wrote, iclass 21, count 0 2006.168.07:40:11.22#ibcon#about to read 3, iclass 21, count 0 2006.168.07:40:11.25#ibcon#read 3, iclass 21, count 0 2006.168.07:40:11.25#ibcon#about to read 4, iclass 21, count 0 2006.168.07:40:11.25#ibcon#read 4, iclass 21, count 0 2006.168.07:40:11.25#ibcon#about to read 5, iclass 21, count 0 2006.168.07:40:11.25#ibcon#read 5, iclass 21, count 0 2006.168.07:40:11.25#ibcon#about to read 6, iclass 21, count 0 2006.168.07:40:11.25#ibcon#read 6, iclass 21, count 0 2006.168.07:40:11.25#ibcon#end of sib2, iclass 21, count 0 2006.168.07:40:11.25#ibcon#*after write, iclass 21, count 0 2006.168.07:40:11.25#ibcon#*before return 0, iclass 21, count 0 2006.168.07:40:11.25#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.168.07:40:11.25#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.168.07:40:11.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.168.07:40:11.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.168.07:40:11.25$vc4f8/vblo=3,656.99 2006.168.07:40:11.25#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.168.07:40:11.25#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.168.07:40:11.25#ibcon#ireg 17 cls_cnt 0 2006.168.07:40:11.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:40:11.25#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:40:11.25#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:40:11.25#ibcon#enter wrdev, iclass 23, count 0 2006.168.07:40:11.25#ibcon#first serial, iclass 23, count 0 2006.168.07:40:11.25#ibcon#enter sib2, iclass 23, count 0 2006.168.07:40:11.25#ibcon#flushed, iclass 23, count 0 2006.168.07:40:11.25#ibcon#about to write, iclass 23, count 0 2006.168.07:40:11.25#ibcon#wrote, iclass 23, count 0 2006.168.07:40:11.25#ibcon#about to read 3, iclass 23, count 0 2006.168.07:40:11.27#ibcon#read 3, iclass 23, count 0 2006.168.07:40:11.27#ibcon#about to read 4, iclass 23, count 0 2006.168.07:40:11.27#ibcon#read 4, iclass 23, count 0 2006.168.07:40:11.27#ibcon#about to read 5, iclass 23, count 0 2006.168.07:40:11.27#ibcon#read 5, iclass 23, count 0 2006.168.07:40:11.27#ibcon#about to read 6, iclass 23, count 0 2006.168.07:40:11.27#ibcon#read 6, iclass 23, count 0 2006.168.07:40:11.27#ibcon#end of sib2, iclass 23, count 0 2006.168.07:40:11.27#ibcon#*mode == 0, iclass 23, count 0 2006.168.07:40:11.27#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.168.07:40:11.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.07:40:11.27#ibcon#*before write, iclass 23, count 0 2006.168.07:40:11.27#ibcon#enter sib2, iclass 23, count 0 2006.168.07:40:11.27#ibcon#flushed, iclass 23, count 0 2006.168.07:40:11.27#ibcon#about to write, iclass 23, count 0 2006.168.07:40:11.27#ibcon#wrote, iclass 23, count 0 2006.168.07:40:11.27#ibcon#about to read 3, iclass 23, count 0 2006.168.07:40:11.31#ibcon#read 3, iclass 23, count 0 2006.168.07:40:11.31#ibcon#about to read 4, iclass 23, count 0 2006.168.07:40:11.31#ibcon#read 4, iclass 23, count 0 2006.168.07:40:11.31#ibcon#about to read 5, iclass 23, count 0 2006.168.07:40:11.31#ibcon#read 5, iclass 23, count 0 2006.168.07:40:11.31#ibcon#about to read 6, iclass 23, count 0 2006.168.07:40:11.31#ibcon#read 6, iclass 23, count 0 2006.168.07:40:11.31#ibcon#end of sib2, iclass 23, count 0 2006.168.07:40:11.31#ibcon#*after write, iclass 23, count 0 2006.168.07:40:11.31#ibcon#*before return 0, iclass 23, count 0 2006.168.07:40:11.31#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:40:11.31#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:40:11.31#ibcon#about to clear, iclass 23 cls_cnt 0 2006.168.07:40:11.31#ibcon#cleared, iclass 23 cls_cnt 0 2006.168.07:40:11.31$vc4f8/vb=3,4 2006.168.07:40:11.31#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.168.07:40:11.31#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.168.07:40:11.31#ibcon#ireg 11 cls_cnt 2 2006.168.07:40:11.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.168.07:40:11.37#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.168.07:40:11.37#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.168.07:40:11.37#ibcon#enter wrdev, iclass 25, count 2 2006.168.07:40:11.37#ibcon#first serial, iclass 25, count 2 2006.168.07:40:11.37#ibcon#enter sib2, iclass 25, count 2 2006.168.07:40:11.37#ibcon#flushed, iclass 25, count 2 2006.168.07:40:11.37#ibcon#about to write, iclass 25, count 2 2006.168.07:40:11.37#ibcon#wrote, iclass 25, count 2 2006.168.07:40:11.37#ibcon#about to read 3, iclass 25, count 2 2006.168.07:40:11.39#ibcon#read 3, iclass 25, count 2 2006.168.07:40:11.39#ibcon#about to read 4, iclass 25, count 2 2006.168.07:40:11.39#ibcon#read 4, iclass 25, count 2 2006.168.07:40:11.39#ibcon#about to read 5, iclass 25, count 2 2006.168.07:40:11.39#ibcon#read 5, iclass 25, count 2 2006.168.07:40:11.39#ibcon#about to read 6, iclass 25, count 2 2006.168.07:40:11.39#ibcon#read 6, iclass 25, count 2 2006.168.07:40:11.39#ibcon#end of sib2, iclass 25, count 2 2006.168.07:40:11.39#ibcon#*mode == 0, iclass 25, count 2 2006.168.07:40:11.39#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.168.07:40:11.39#ibcon#[27=AT03-04\r\n] 2006.168.07:40:11.39#ibcon#*before write, iclass 25, count 2 2006.168.07:40:11.39#ibcon#enter sib2, iclass 25, count 2 2006.168.07:40:11.39#ibcon#flushed, iclass 25, count 2 2006.168.07:40:11.39#ibcon#about to write, iclass 25, count 2 2006.168.07:40:11.39#ibcon#wrote, iclass 25, count 2 2006.168.07:40:11.39#ibcon#about to read 3, iclass 25, count 2 2006.168.07:40:11.42#ibcon#read 3, iclass 25, count 2 2006.168.07:40:11.42#ibcon#about to read 4, iclass 25, count 2 2006.168.07:40:11.42#ibcon#read 4, iclass 25, count 2 2006.168.07:40:11.42#ibcon#about to read 5, iclass 25, count 2 2006.168.07:40:11.42#ibcon#read 5, iclass 25, count 2 2006.168.07:40:11.42#ibcon#about to read 6, iclass 25, count 2 2006.168.07:40:11.42#ibcon#read 6, iclass 25, count 2 2006.168.07:40:11.42#ibcon#end of sib2, iclass 25, count 2 2006.168.07:40:11.42#ibcon#*after write, iclass 25, count 2 2006.168.07:40:11.42#ibcon#*before return 0, iclass 25, count 2 2006.168.07:40:11.42#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.168.07:40:11.42#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.168.07:40:11.42#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.168.07:40:11.42#ibcon#ireg 7 cls_cnt 0 2006.168.07:40:11.42#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.168.07:40:11.54#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.168.07:40:11.54#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.168.07:40:11.54#ibcon#enter wrdev, iclass 25, count 0 2006.168.07:40:11.54#ibcon#first serial, iclass 25, count 0 2006.168.07:40:11.54#ibcon#enter sib2, iclass 25, count 0 2006.168.07:40:11.54#ibcon#flushed, iclass 25, count 0 2006.168.07:40:11.54#ibcon#about to write, iclass 25, count 0 2006.168.07:40:11.54#ibcon#wrote, iclass 25, count 0 2006.168.07:40:11.54#ibcon#about to read 3, iclass 25, count 0 2006.168.07:40:11.56#ibcon#read 3, iclass 25, count 0 2006.168.07:40:11.56#ibcon#about to read 4, iclass 25, count 0 2006.168.07:40:11.56#ibcon#read 4, iclass 25, count 0 2006.168.07:40:11.56#ibcon#about to read 5, iclass 25, count 0 2006.168.07:40:11.56#ibcon#read 5, iclass 25, count 0 2006.168.07:40:11.56#ibcon#about to read 6, iclass 25, count 0 2006.168.07:40:11.56#ibcon#read 6, iclass 25, count 0 2006.168.07:40:11.56#ibcon#end of sib2, iclass 25, count 0 2006.168.07:40:11.56#ibcon#*mode == 0, iclass 25, count 0 2006.168.07:40:11.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.168.07:40:11.56#ibcon#[27=USB\r\n] 2006.168.07:40:11.56#ibcon#*before write, iclass 25, count 0 2006.168.07:40:11.56#ibcon#enter sib2, iclass 25, count 0 2006.168.07:40:11.56#ibcon#flushed, iclass 25, count 0 2006.168.07:40:11.56#ibcon#about to write, iclass 25, count 0 2006.168.07:40:11.56#ibcon#wrote, iclass 25, count 0 2006.168.07:40:11.56#ibcon#about to read 3, iclass 25, count 0 2006.168.07:40:11.59#ibcon#read 3, iclass 25, count 0 2006.168.07:40:11.59#ibcon#about to read 4, iclass 25, count 0 2006.168.07:40:11.59#ibcon#read 4, iclass 25, count 0 2006.168.07:40:11.59#ibcon#about to read 5, iclass 25, count 0 2006.168.07:40:11.59#ibcon#read 5, iclass 25, count 0 2006.168.07:40:11.59#ibcon#about to read 6, iclass 25, count 0 2006.168.07:40:11.59#ibcon#read 6, iclass 25, count 0 2006.168.07:40:11.59#ibcon#end of sib2, iclass 25, count 0 2006.168.07:40:11.59#ibcon#*after write, iclass 25, count 0 2006.168.07:40:11.59#ibcon#*before return 0, iclass 25, count 0 2006.168.07:40:11.59#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.168.07:40:11.59#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.168.07:40:11.59#ibcon#about to clear, iclass 25 cls_cnt 0 2006.168.07:40:11.59#ibcon#cleared, iclass 25 cls_cnt 0 2006.168.07:40:11.59$vc4f8/vblo=4,712.99 2006.168.07:40:11.59#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.168.07:40:11.59#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.168.07:40:11.59#ibcon#ireg 17 cls_cnt 0 2006.168.07:40:11.59#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.168.07:40:11.59#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.168.07:40:11.59#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.168.07:40:11.59#ibcon#enter wrdev, iclass 27, count 0 2006.168.07:40:11.59#ibcon#first serial, iclass 27, count 0 2006.168.07:40:11.59#ibcon#enter sib2, iclass 27, count 0 2006.168.07:40:11.59#ibcon#flushed, iclass 27, count 0 2006.168.07:40:11.59#ibcon#about to write, iclass 27, count 0 2006.168.07:40:11.59#ibcon#wrote, iclass 27, count 0 2006.168.07:40:11.59#ibcon#about to read 3, iclass 27, count 0 2006.168.07:40:11.61#ibcon#read 3, iclass 27, count 0 2006.168.07:40:11.61#ibcon#about to read 4, iclass 27, count 0 2006.168.07:40:11.61#ibcon#read 4, iclass 27, count 0 2006.168.07:40:11.61#ibcon#about to read 5, iclass 27, count 0 2006.168.07:40:11.61#ibcon#read 5, iclass 27, count 0 2006.168.07:40:11.61#ibcon#about to read 6, iclass 27, count 0 2006.168.07:40:11.61#ibcon#read 6, iclass 27, count 0 2006.168.07:40:11.61#ibcon#end of sib2, iclass 27, count 0 2006.168.07:40:11.61#ibcon#*mode == 0, iclass 27, count 0 2006.168.07:40:11.61#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.168.07:40:11.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.07:40:11.61#ibcon#*before write, iclass 27, count 0 2006.168.07:40:11.61#ibcon#enter sib2, iclass 27, count 0 2006.168.07:40:11.61#ibcon#flushed, iclass 27, count 0 2006.168.07:40:11.61#ibcon#about to write, iclass 27, count 0 2006.168.07:40:11.61#ibcon#wrote, iclass 27, count 0 2006.168.07:40:11.61#ibcon#about to read 3, iclass 27, count 0 2006.168.07:40:11.65#ibcon#read 3, iclass 27, count 0 2006.168.07:40:11.65#ibcon#about to read 4, iclass 27, count 0 2006.168.07:40:11.65#ibcon#read 4, iclass 27, count 0 2006.168.07:40:11.65#ibcon#about to read 5, iclass 27, count 0 2006.168.07:40:11.65#ibcon#read 5, iclass 27, count 0 2006.168.07:40:11.65#ibcon#about to read 6, iclass 27, count 0 2006.168.07:40:11.65#ibcon#read 6, iclass 27, count 0 2006.168.07:40:11.65#ibcon#end of sib2, iclass 27, count 0 2006.168.07:40:11.65#ibcon#*after write, iclass 27, count 0 2006.168.07:40:11.65#ibcon#*before return 0, iclass 27, count 0 2006.168.07:40:11.65#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.168.07:40:11.65#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.168.07:40:11.65#ibcon#about to clear, iclass 27 cls_cnt 0 2006.168.07:40:11.65#ibcon#cleared, iclass 27 cls_cnt 0 2006.168.07:40:11.65$vc4f8/vb=4,4 2006.168.07:40:11.65#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.168.07:40:11.65#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.168.07:40:11.65#ibcon#ireg 11 cls_cnt 2 2006.168.07:40:11.65#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.168.07:40:11.71#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.168.07:40:11.71#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.168.07:40:11.71#ibcon#enter wrdev, iclass 29, count 2 2006.168.07:40:11.71#ibcon#first serial, iclass 29, count 2 2006.168.07:40:11.71#ibcon#enter sib2, iclass 29, count 2 2006.168.07:40:11.71#ibcon#flushed, iclass 29, count 2 2006.168.07:40:11.71#ibcon#about to write, iclass 29, count 2 2006.168.07:40:11.71#ibcon#wrote, iclass 29, count 2 2006.168.07:40:11.71#ibcon#about to read 3, iclass 29, count 2 2006.168.07:40:11.73#ibcon#read 3, iclass 29, count 2 2006.168.07:40:11.73#ibcon#about to read 4, iclass 29, count 2 2006.168.07:40:11.73#ibcon#read 4, iclass 29, count 2 2006.168.07:40:11.73#ibcon#about to read 5, iclass 29, count 2 2006.168.07:40:11.73#ibcon#read 5, iclass 29, count 2 2006.168.07:40:11.73#ibcon#about to read 6, iclass 29, count 2 2006.168.07:40:11.73#ibcon#read 6, iclass 29, count 2 2006.168.07:40:11.73#ibcon#end of sib2, iclass 29, count 2 2006.168.07:40:11.73#ibcon#*mode == 0, iclass 29, count 2 2006.168.07:40:11.73#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.168.07:40:11.73#ibcon#[27=AT04-04\r\n] 2006.168.07:40:11.73#ibcon#*before write, iclass 29, count 2 2006.168.07:40:11.73#ibcon#enter sib2, iclass 29, count 2 2006.168.07:40:11.73#ibcon#flushed, iclass 29, count 2 2006.168.07:40:11.73#ibcon#about to write, iclass 29, count 2 2006.168.07:40:11.73#ibcon#wrote, iclass 29, count 2 2006.168.07:40:11.73#ibcon#about to read 3, iclass 29, count 2 2006.168.07:40:11.76#ibcon#read 3, iclass 29, count 2 2006.168.07:40:11.76#ibcon#about to read 4, iclass 29, count 2 2006.168.07:40:11.76#ibcon#read 4, iclass 29, count 2 2006.168.07:40:11.76#ibcon#about to read 5, iclass 29, count 2 2006.168.07:40:11.76#ibcon#read 5, iclass 29, count 2 2006.168.07:40:11.76#ibcon#about to read 6, iclass 29, count 2 2006.168.07:40:11.76#ibcon#read 6, iclass 29, count 2 2006.168.07:40:11.76#ibcon#end of sib2, iclass 29, count 2 2006.168.07:40:11.76#ibcon#*after write, iclass 29, count 2 2006.168.07:40:11.76#ibcon#*before return 0, iclass 29, count 2 2006.168.07:40:11.76#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.168.07:40:11.76#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.168.07:40:11.76#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.168.07:40:11.76#ibcon#ireg 7 cls_cnt 0 2006.168.07:40:11.76#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.168.07:40:11.88#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.168.07:40:11.88#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.168.07:40:11.88#ibcon#enter wrdev, iclass 29, count 0 2006.168.07:40:11.88#ibcon#first serial, iclass 29, count 0 2006.168.07:40:11.88#ibcon#enter sib2, iclass 29, count 0 2006.168.07:40:11.88#ibcon#flushed, iclass 29, count 0 2006.168.07:40:11.88#ibcon#about to write, iclass 29, count 0 2006.168.07:40:11.88#ibcon#wrote, iclass 29, count 0 2006.168.07:40:11.88#ibcon#about to read 3, iclass 29, count 0 2006.168.07:40:11.90#ibcon#read 3, iclass 29, count 0 2006.168.07:40:11.90#ibcon#about to read 4, iclass 29, count 0 2006.168.07:40:11.90#ibcon#read 4, iclass 29, count 0 2006.168.07:40:11.90#ibcon#about to read 5, iclass 29, count 0 2006.168.07:40:11.90#ibcon#read 5, iclass 29, count 0 2006.168.07:40:11.90#ibcon#about to read 6, iclass 29, count 0 2006.168.07:40:11.90#ibcon#read 6, iclass 29, count 0 2006.168.07:40:11.90#ibcon#end of sib2, iclass 29, count 0 2006.168.07:40:11.90#ibcon#*mode == 0, iclass 29, count 0 2006.168.07:40:11.90#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.168.07:40:11.90#ibcon#[27=USB\r\n] 2006.168.07:40:11.90#ibcon#*before write, iclass 29, count 0 2006.168.07:40:11.90#ibcon#enter sib2, iclass 29, count 0 2006.168.07:40:11.90#ibcon#flushed, iclass 29, count 0 2006.168.07:40:11.90#ibcon#about to write, iclass 29, count 0 2006.168.07:40:11.90#ibcon#wrote, iclass 29, count 0 2006.168.07:40:11.90#ibcon#about to read 3, iclass 29, count 0 2006.168.07:40:11.93#ibcon#read 3, iclass 29, count 0 2006.168.07:40:11.93#ibcon#about to read 4, iclass 29, count 0 2006.168.07:40:11.93#ibcon#read 4, iclass 29, count 0 2006.168.07:40:11.93#ibcon#about to read 5, iclass 29, count 0 2006.168.07:40:11.93#ibcon#read 5, iclass 29, count 0 2006.168.07:40:11.93#ibcon#about to read 6, iclass 29, count 0 2006.168.07:40:11.93#ibcon#read 6, iclass 29, count 0 2006.168.07:40:11.93#ibcon#end of sib2, iclass 29, count 0 2006.168.07:40:11.93#ibcon#*after write, iclass 29, count 0 2006.168.07:40:11.93#ibcon#*before return 0, iclass 29, count 0 2006.168.07:40:11.93#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.168.07:40:11.93#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.168.07:40:11.93#ibcon#about to clear, iclass 29 cls_cnt 0 2006.168.07:40:11.93#ibcon#cleared, iclass 29 cls_cnt 0 2006.168.07:40:11.93$vc4f8/vblo=5,744.99 2006.168.07:40:11.93#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.168.07:40:11.93#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.168.07:40:11.93#ibcon#ireg 17 cls_cnt 0 2006.168.07:40:11.93#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:40:11.93#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:40:11.93#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:40:11.93#ibcon#enter wrdev, iclass 31, count 0 2006.168.07:40:11.93#ibcon#first serial, iclass 31, count 0 2006.168.07:40:11.93#ibcon#enter sib2, iclass 31, count 0 2006.168.07:40:11.93#ibcon#flushed, iclass 31, count 0 2006.168.07:40:11.93#ibcon#about to write, iclass 31, count 0 2006.168.07:40:11.93#ibcon#wrote, iclass 31, count 0 2006.168.07:40:11.93#ibcon#about to read 3, iclass 31, count 0 2006.168.07:40:11.95#ibcon#read 3, iclass 31, count 0 2006.168.07:40:11.95#ibcon#about to read 4, iclass 31, count 0 2006.168.07:40:11.95#ibcon#read 4, iclass 31, count 0 2006.168.07:40:11.95#ibcon#about to read 5, iclass 31, count 0 2006.168.07:40:11.95#ibcon#read 5, iclass 31, count 0 2006.168.07:40:11.95#ibcon#about to read 6, iclass 31, count 0 2006.168.07:40:11.95#ibcon#read 6, iclass 31, count 0 2006.168.07:40:11.95#ibcon#end of sib2, iclass 31, count 0 2006.168.07:40:11.95#ibcon#*mode == 0, iclass 31, count 0 2006.168.07:40:11.95#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.168.07:40:11.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.07:40:11.95#ibcon#*before write, iclass 31, count 0 2006.168.07:40:11.95#ibcon#enter sib2, iclass 31, count 0 2006.168.07:40:11.95#ibcon#flushed, iclass 31, count 0 2006.168.07:40:11.95#ibcon#about to write, iclass 31, count 0 2006.168.07:40:11.95#ibcon#wrote, iclass 31, count 0 2006.168.07:40:11.95#ibcon#about to read 3, iclass 31, count 0 2006.168.07:40:11.99#ibcon#read 3, iclass 31, count 0 2006.168.07:40:11.99#ibcon#about to read 4, iclass 31, count 0 2006.168.07:40:11.99#ibcon#read 4, iclass 31, count 0 2006.168.07:40:11.99#ibcon#about to read 5, iclass 31, count 0 2006.168.07:40:11.99#ibcon#read 5, iclass 31, count 0 2006.168.07:40:11.99#ibcon#about to read 6, iclass 31, count 0 2006.168.07:40:11.99#ibcon#read 6, iclass 31, count 0 2006.168.07:40:11.99#ibcon#end of sib2, iclass 31, count 0 2006.168.07:40:11.99#ibcon#*after write, iclass 31, count 0 2006.168.07:40:11.99#ibcon#*before return 0, iclass 31, count 0 2006.168.07:40:11.99#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:40:11.99#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:40:11.99#ibcon#about to clear, iclass 31 cls_cnt 0 2006.168.07:40:11.99#ibcon#cleared, iclass 31 cls_cnt 0 2006.168.07:40:11.99$vc4f8/vb=5,4 2006.168.07:40:11.99#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.168.07:40:11.99#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.168.07:40:11.99#ibcon#ireg 11 cls_cnt 2 2006.168.07:40:11.99#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:40:12.05#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:40:12.05#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:40:12.05#ibcon#enter wrdev, iclass 33, count 2 2006.168.07:40:12.05#ibcon#first serial, iclass 33, count 2 2006.168.07:40:12.05#ibcon#enter sib2, iclass 33, count 2 2006.168.07:40:12.05#ibcon#flushed, iclass 33, count 2 2006.168.07:40:12.05#ibcon#about to write, iclass 33, count 2 2006.168.07:40:12.05#ibcon#wrote, iclass 33, count 2 2006.168.07:40:12.05#ibcon#about to read 3, iclass 33, count 2 2006.168.07:40:12.07#ibcon#read 3, iclass 33, count 2 2006.168.07:40:12.07#ibcon#about to read 4, iclass 33, count 2 2006.168.07:40:12.07#ibcon#read 4, iclass 33, count 2 2006.168.07:40:12.07#ibcon#about to read 5, iclass 33, count 2 2006.168.07:40:12.07#ibcon#read 5, iclass 33, count 2 2006.168.07:40:12.07#ibcon#about to read 6, iclass 33, count 2 2006.168.07:40:12.07#ibcon#read 6, iclass 33, count 2 2006.168.07:40:12.07#ibcon#end of sib2, iclass 33, count 2 2006.168.07:40:12.07#ibcon#*mode == 0, iclass 33, count 2 2006.168.07:40:12.07#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.168.07:40:12.07#ibcon#[27=AT05-04\r\n] 2006.168.07:40:12.07#ibcon#*before write, iclass 33, count 2 2006.168.07:40:12.07#ibcon#enter sib2, iclass 33, count 2 2006.168.07:40:12.07#ibcon#flushed, iclass 33, count 2 2006.168.07:40:12.07#ibcon#about to write, iclass 33, count 2 2006.168.07:40:12.07#ibcon#wrote, iclass 33, count 2 2006.168.07:40:12.07#ibcon#about to read 3, iclass 33, count 2 2006.168.07:40:12.10#ibcon#read 3, iclass 33, count 2 2006.168.07:40:12.10#ibcon#about to read 4, iclass 33, count 2 2006.168.07:40:12.10#ibcon#read 4, iclass 33, count 2 2006.168.07:40:12.10#ibcon#about to read 5, iclass 33, count 2 2006.168.07:40:12.10#ibcon#read 5, iclass 33, count 2 2006.168.07:40:12.10#ibcon#about to read 6, iclass 33, count 2 2006.168.07:40:12.10#ibcon#read 6, iclass 33, count 2 2006.168.07:40:12.10#ibcon#end of sib2, iclass 33, count 2 2006.168.07:40:12.10#ibcon#*after write, iclass 33, count 2 2006.168.07:40:12.10#ibcon#*before return 0, iclass 33, count 2 2006.168.07:40:12.10#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:40:12.10#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:40:12.10#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.168.07:40:12.10#ibcon#ireg 7 cls_cnt 0 2006.168.07:40:12.10#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:40:12.22#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:40:12.22#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:40:12.22#ibcon#enter wrdev, iclass 33, count 0 2006.168.07:40:12.22#ibcon#first serial, iclass 33, count 0 2006.168.07:40:12.22#ibcon#enter sib2, iclass 33, count 0 2006.168.07:40:12.22#ibcon#flushed, iclass 33, count 0 2006.168.07:40:12.22#ibcon#about to write, iclass 33, count 0 2006.168.07:40:12.22#ibcon#wrote, iclass 33, count 0 2006.168.07:40:12.22#ibcon#about to read 3, iclass 33, count 0 2006.168.07:40:12.24#ibcon#read 3, iclass 33, count 0 2006.168.07:40:12.24#ibcon#about to read 4, iclass 33, count 0 2006.168.07:40:12.24#ibcon#read 4, iclass 33, count 0 2006.168.07:40:12.24#ibcon#about to read 5, iclass 33, count 0 2006.168.07:40:12.24#ibcon#read 5, iclass 33, count 0 2006.168.07:40:12.24#ibcon#about to read 6, iclass 33, count 0 2006.168.07:40:12.24#ibcon#read 6, iclass 33, count 0 2006.168.07:40:12.24#ibcon#end of sib2, iclass 33, count 0 2006.168.07:40:12.24#ibcon#*mode == 0, iclass 33, count 0 2006.168.07:40:12.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.168.07:40:12.24#ibcon#[27=USB\r\n] 2006.168.07:40:12.24#ibcon#*before write, iclass 33, count 0 2006.168.07:40:12.24#ibcon#enter sib2, iclass 33, count 0 2006.168.07:40:12.24#ibcon#flushed, iclass 33, count 0 2006.168.07:40:12.24#ibcon#about to write, iclass 33, count 0 2006.168.07:40:12.24#ibcon#wrote, iclass 33, count 0 2006.168.07:40:12.24#ibcon#about to read 3, iclass 33, count 0 2006.168.07:40:12.27#ibcon#read 3, iclass 33, count 0 2006.168.07:40:12.27#ibcon#about to read 4, iclass 33, count 0 2006.168.07:40:12.27#ibcon#read 4, iclass 33, count 0 2006.168.07:40:12.27#ibcon#about to read 5, iclass 33, count 0 2006.168.07:40:12.27#ibcon#read 5, iclass 33, count 0 2006.168.07:40:12.27#ibcon#about to read 6, iclass 33, count 0 2006.168.07:40:12.27#ibcon#read 6, iclass 33, count 0 2006.168.07:40:12.27#ibcon#end of sib2, iclass 33, count 0 2006.168.07:40:12.27#ibcon#*after write, iclass 33, count 0 2006.168.07:40:12.27#ibcon#*before return 0, iclass 33, count 0 2006.168.07:40:12.27#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:40:12.27#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:40:12.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.168.07:40:12.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.168.07:40:12.27$vc4f8/vblo=6,752.99 2006.168.07:40:12.27#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.168.07:40:12.27#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.168.07:40:12.27#ibcon#ireg 17 cls_cnt 0 2006.168.07:40:12.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:40:12.27#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:40:12.27#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:40:12.27#ibcon#enter wrdev, iclass 35, count 0 2006.168.07:40:12.27#ibcon#first serial, iclass 35, count 0 2006.168.07:40:12.27#ibcon#enter sib2, iclass 35, count 0 2006.168.07:40:12.27#ibcon#flushed, iclass 35, count 0 2006.168.07:40:12.27#ibcon#about to write, iclass 35, count 0 2006.168.07:40:12.27#ibcon#wrote, iclass 35, count 0 2006.168.07:40:12.27#ibcon#about to read 3, iclass 35, count 0 2006.168.07:40:12.29#ibcon#read 3, iclass 35, count 0 2006.168.07:40:12.29#ibcon#about to read 4, iclass 35, count 0 2006.168.07:40:12.29#ibcon#read 4, iclass 35, count 0 2006.168.07:40:12.29#ibcon#about to read 5, iclass 35, count 0 2006.168.07:40:12.29#ibcon#read 5, iclass 35, count 0 2006.168.07:40:12.29#ibcon#about to read 6, iclass 35, count 0 2006.168.07:40:12.29#ibcon#read 6, iclass 35, count 0 2006.168.07:40:12.29#ibcon#end of sib2, iclass 35, count 0 2006.168.07:40:12.29#ibcon#*mode == 0, iclass 35, count 0 2006.168.07:40:12.29#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.168.07:40:12.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.07:40:12.29#ibcon#*before write, iclass 35, count 0 2006.168.07:40:12.29#ibcon#enter sib2, iclass 35, count 0 2006.168.07:40:12.29#ibcon#flushed, iclass 35, count 0 2006.168.07:40:12.29#ibcon#about to write, iclass 35, count 0 2006.168.07:40:12.29#ibcon#wrote, iclass 35, count 0 2006.168.07:40:12.29#ibcon#about to read 3, iclass 35, count 0 2006.168.07:40:12.33#ibcon#read 3, iclass 35, count 0 2006.168.07:40:12.33#ibcon#about to read 4, iclass 35, count 0 2006.168.07:40:12.33#ibcon#read 4, iclass 35, count 0 2006.168.07:40:12.33#ibcon#about to read 5, iclass 35, count 0 2006.168.07:40:12.33#ibcon#read 5, iclass 35, count 0 2006.168.07:40:12.33#ibcon#about to read 6, iclass 35, count 0 2006.168.07:40:12.33#ibcon#read 6, iclass 35, count 0 2006.168.07:40:12.33#ibcon#end of sib2, iclass 35, count 0 2006.168.07:40:12.33#ibcon#*after write, iclass 35, count 0 2006.168.07:40:12.33#ibcon#*before return 0, iclass 35, count 0 2006.168.07:40:12.33#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:40:12.33#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:40:12.33#ibcon#about to clear, iclass 35 cls_cnt 0 2006.168.07:40:12.33#ibcon#cleared, iclass 35 cls_cnt 0 2006.168.07:40:12.33$vc4f8/vb=6,4 2006.168.07:40:12.33#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.168.07:40:12.33#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.168.07:40:12.33#ibcon#ireg 11 cls_cnt 2 2006.168.07:40:12.33#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:40:12.39#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:40:12.39#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:40:12.39#ibcon#enter wrdev, iclass 37, count 2 2006.168.07:40:12.39#ibcon#first serial, iclass 37, count 2 2006.168.07:40:12.39#ibcon#enter sib2, iclass 37, count 2 2006.168.07:40:12.39#ibcon#flushed, iclass 37, count 2 2006.168.07:40:12.39#ibcon#about to write, iclass 37, count 2 2006.168.07:40:12.39#ibcon#wrote, iclass 37, count 2 2006.168.07:40:12.39#ibcon#about to read 3, iclass 37, count 2 2006.168.07:40:12.41#ibcon#read 3, iclass 37, count 2 2006.168.07:40:12.41#ibcon#about to read 4, iclass 37, count 2 2006.168.07:40:12.41#ibcon#read 4, iclass 37, count 2 2006.168.07:40:12.41#ibcon#about to read 5, iclass 37, count 2 2006.168.07:40:12.41#ibcon#read 5, iclass 37, count 2 2006.168.07:40:12.41#ibcon#about to read 6, iclass 37, count 2 2006.168.07:40:12.41#ibcon#read 6, iclass 37, count 2 2006.168.07:40:12.41#ibcon#end of sib2, iclass 37, count 2 2006.168.07:40:12.41#ibcon#*mode == 0, iclass 37, count 2 2006.168.07:40:12.41#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.168.07:40:12.41#ibcon#[27=AT06-04\r\n] 2006.168.07:40:12.41#ibcon#*before write, iclass 37, count 2 2006.168.07:40:12.41#ibcon#enter sib2, iclass 37, count 2 2006.168.07:40:12.41#ibcon#flushed, iclass 37, count 2 2006.168.07:40:12.41#ibcon#about to write, iclass 37, count 2 2006.168.07:40:12.41#ibcon#wrote, iclass 37, count 2 2006.168.07:40:12.41#ibcon#about to read 3, iclass 37, count 2 2006.168.07:40:12.44#ibcon#read 3, iclass 37, count 2 2006.168.07:40:12.44#ibcon#about to read 4, iclass 37, count 2 2006.168.07:40:12.44#ibcon#read 4, iclass 37, count 2 2006.168.07:40:12.44#ibcon#about to read 5, iclass 37, count 2 2006.168.07:40:12.44#ibcon#read 5, iclass 37, count 2 2006.168.07:40:12.44#ibcon#about to read 6, iclass 37, count 2 2006.168.07:40:12.44#ibcon#read 6, iclass 37, count 2 2006.168.07:40:12.44#ibcon#end of sib2, iclass 37, count 2 2006.168.07:40:12.44#ibcon#*after write, iclass 37, count 2 2006.168.07:40:12.44#ibcon#*before return 0, iclass 37, count 2 2006.168.07:40:12.44#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:40:12.44#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:40:12.44#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.168.07:40:12.44#ibcon#ireg 7 cls_cnt 0 2006.168.07:40:12.44#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:40:12.56#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:40:12.56#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:40:12.56#ibcon#enter wrdev, iclass 37, count 0 2006.168.07:40:12.56#ibcon#first serial, iclass 37, count 0 2006.168.07:40:12.56#ibcon#enter sib2, iclass 37, count 0 2006.168.07:40:12.56#ibcon#flushed, iclass 37, count 0 2006.168.07:40:12.56#ibcon#about to write, iclass 37, count 0 2006.168.07:40:12.56#ibcon#wrote, iclass 37, count 0 2006.168.07:40:12.56#ibcon#about to read 3, iclass 37, count 0 2006.168.07:40:12.58#ibcon#read 3, iclass 37, count 0 2006.168.07:40:12.58#ibcon#about to read 4, iclass 37, count 0 2006.168.07:40:12.58#ibcon#read 4, iclass 37, count 0 2006.168.07:40:12.58#ibcon#about to read 5, iclass 37, count 0 2006.168.07:40:12.58#ibcon#read 5, iclass 37, count 0 2006.168.07:40:12.58#ibcon#about to read 6, iclass 37, count 0 2006.168.07:40:12.58#ibcon#read 6, iclass 37, count 0 2006.168.07:40:12.58#ibcon#end of sib2, iclass 37, count 0 2006.168.07:40:12.58#ibcon#*mode == 0, iclass 37, count 0 2006.168.07:40:12.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.168.07:40:12.58#ibcon#[27=USB\r\n] 2006.168.07:40:12.58#ibcon#*before write, iclass 37, count 0 2006.168.07:40:12.58#ibcon#enter sib2, iclass 37, count 0 2006.168.07:40:12.58#ibcon#flushed, iclass 37, count 0 2006.168.07:40:12.58#ibcon#about to write, iclass 37, count 0 2006.168.07:40:12.58#ibcon#wrote, iclass 37, count 0 2006.168.07:40:12.58#ibcon#about to read 3, iclass 37, count 0 2006.168.07:40:12.61#ibcon#read 3, iclass 37, count 0 2006.168.07:40:12.61#ibcon#about to read 4, iclass 37, count 0 2006.168.07:40:12.61#ibcon#read 4, iclass 37, count 0 2006.168.07:40:12.61#ibcon#about to read 5, iclass 37, count 0 2006.168.07:40:12.61#ibcon#read 5, iclass 37, count 0 2006.168.07:40:12.61#ibcon#about to read 6, iclass 37, count 0 2006.168.07:40:12.61#ibcon#read 6, iclass 37, count 0 2006.168.07:40:12.61#ibcon#end of sib2, iclass 37, count 0 2006.168.07:40:12.61#ibcon#*after write, iclass 37, count 0 2006.168.07:40:12.61#ibcon#*before return 0, iclass 37, count 0 2006.168.07:40:12.61#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:40:12.61#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:40:12.61#ibcon#about to clear, iclass 37 cls_cnt 0 2006.168.07:40:12.61#ibcon#cleared, iclass 37 cls_cnt 0 2006.168.07:40:12.61$vc4f8/vabw=wide 2006.168.07:40:12.61#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.168.07:40:12.61#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.168.07:40:12.61#ibcon#ireg 8 cls_cnt 0 2006.168.07:40:12.61#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.168.07:40:12.61#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.168.07:40:12.61#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.168.07:40:12.61#ibcon#enter wrdev, iclass 39, count 0 2006.168.07:40:12.61#ibcon#first serial, iclass 39, count 0 2006.168.07:40:12.61#ibcon#enter sib2, iclass 39, count 0 2006.168.07:40:12.61#ibcon#flushed, iclass 39, count 0 2006.168.07:40:12.61#ibcon#about to write, iclass 39, count 0 2006.168.07:40:12.61#ibcon#wrote, iclass 39, count 0 2006.168.07:40:12.61#ibcon#about to read 3, iclass 39, count 0 2006.168.07:40:12.63#ibcon#read 3, iclass 39, count 0 2006.168.07:40:12.63#ibcon#about to read 4, iclass 39, count 0 2006.168.07:40:12.63#ibcon#read 4, iclass 39, count 0 2006.168.07:40:12.63#ibcon#about to read 5, iclass 39, count 0 2006.168.07:40:12.63#ibcon#read 5, iclass 39, count 0 2006.168.07:40:12.63#ibcon#about to read 6, iclass 39, count 0 2006.168.07:40:12.63#ibcon#read 6, iclass 39, count 0 2006.168.07:40:12.63#ibcon#end of sib2, iclass 39, count 0 2006.168.07:40:12.63#ibcon#*mode == 0, iclass 39, count 0 2006.168.07:40:12.63#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.168.07:40:12.63#ibcon#[25=BW32\r\n] 2006.168.07:40:12.63#ibcon#*before write, iclass 39, count 0 2006.168.07:40:12.63#ibcon#enter sib2, iclass 39, count 0 2006.168.07:40:12.63#ibcon#flushed, iclass 39, count 0 2006.168.07:40:12.63#ibcon#about to write, iclass 39, count 0 2006.168.07:40:12.63#ibcon#wrote, iclass 39, count 0 2006.168.07:40:12.63#ibcon#about to read 3, iclass 39, count 0 2006.168.07:40:12.66#ibcon#read 3, iclass 39, count 0 2006.168.07:40:12.66#ibcon#about to read 4, iclass 39, count 0 2006.168.07:40:12.66#ibcon#read 4, iclass 39, count 0 2006.168.07:40:12.66#ibcon#about to read 5, iclass 39, count 0 2006.168.07:40:12.66#ibcon#read 5, iclass 39, count 0 2006.168.07:40:12.66#ibcon#about to read 6, iclass 39, count 0 2006.168.07:40:12.66#ibcon#read 6, iclass 39, count 0 2006.168.07:40:12.66#ibcon#end of sib2, iclass 39, count 0 2006.168.07:40:12.66#ibcon#*after write, iclass 39, count 0 2006.168.07:40:12.66#ibcon#*before return 0, iclass 39, count 0 2006.168.07:40:12.66#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.168.07:40:12.66#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.168.07:40:12.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.168.07:40:12.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.168.07:40:12.66$vc4f8/vbbw=wide 2006.168.07:40:12.66#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.168.07:40:12.66#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.168.07:40:12.66#ibcon#ireg 8 cls_cnt 0 2006.168.07:40:12.66#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:40:12.73#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:40:12.73#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:40:12.73#ibcon#enter wrdev, iclass 3, count 0 2006.168.07:40:12.73#ibcon#first serial, iclass 3, count 0 2006.168.07:40:12.73#ibcon#enter sib2, iclass 3, count 0 2006.168.07:40:12.73#ibcon#flushed, iclass 3, count 0 2006.168.07:40:12.73#ibcon#about to write, iclass 3, count 0 2006.168.07:40:12.73#ibcon#wrote, iclass 3, count 0 2006.168.07:40:12.73#ibcon#about to read 3, iclass 3, count 0 2006.168.07:40:12.75#ibcon#read 3, iclass 3, count 0 2006.168.07:40:12.75#ibcon#about to read 4, iclass 3, count 0 2006.168.07:40:12.75#ibcon#read 4, iclass 3, count 0 2006.168.07:40:12.75#ibcon#about to read 5, iclass 3, count 0 2006.168.07:40:12.75#ibcon#read 5, iclass 3, count 0 2006.168.07:40:12.75#ibcon#about to read 6, iclass 3, count 0 2006.168.07:40:12.75#ibcon#read 6, iclass 3, count 0 2006.168.07:40:12.75#ibcon#end of sib2, iclass 3, count 0 2006.168.07:40:12.75#ibcon#*mode == 0, iclass 3, count 0 2006.168.07:40:12.75#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.168.07:40:12.75#ibcon#[27=BW32\r\n] 2006.168.07:40:12.75#ibcon#*before write, iclass 3, count 0 2006.168.07:40:12.75#ibcon#enter sib2, iclass 3, count 0 2006.168.07:40:12.75#ibcon#flushed, iclass 3, count 0 2006.168.07:40:12.75#ibcon#about to write, iclass 3, count 0 2006.168.07:40:12.75#ibcon#wrote, iclass 3, count 0 2006.168.07:40:12.75#ibcon#about to read 3, iclass 3, count 0 2006.168.07:40:12.78#ibcon#read 3, iclass 3, count 0 2006.168.07:40:12.78#ibcon#about to read 4, iclass 3, count 0 2006.168.07:40:12.78#ibcon#read 4, iclass 3, count 0 2006.168.07:40:12.78#ibcon#about to read 5, iclass 3, count 0 2006.168.07:40:12.78#ibcon#read 5, iclass 3, count 0 2006.168.07:40:12.78#ibcon#about to read 6, iclass 3, count 0 2006.168.07:40:12.78#ibcon#read 6, iclass 3, count 0 2006.168.07:40:12.78#ibcon#end of sib2, iclass 3, count 0 2006.168.07:40:12.78#ibcon#*after write, iclass 3, count 0 2006.168.07:40:12.78#ibcon#*before return 0, iclass 3, count 0 2006.168.07:40:12.78#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:40:12.78#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:40:12.78#ibcon#about to clear, iclass 3 cls_cnt 0 2006.168.07:40:12.78#ibcon#cleared, iclass 3 cls_cnt 0 2006.168.07:40:12.78$4f8m12a/ifd4f 2006.168.07:40:12.78$ifd4f/lo= 2006.168.07:40:12.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.07:40:12.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.07:40:12.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.07:40:12.78$ifd4f/patch= 2006.168.07:40:12.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.07:40:12.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.07:40:12.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.07:40:12.78$4f8m12a/"form=m,16.000,1:2 2006.168.07:40:12.78$4f8m12a/"tpicd 2006.168.07:40:12.78$4f8m12a/echo=off 2006.168.07:40:12.78$4f8m12a/xlog=off 2006.168.07:40:12.78:!2006.168.07:40:40 2006.168.07:40:25.14#trakl#Source acquired 2006.168.07:40:25.14#flagr#flagr/antenna,acquired 2006.168.07:40:40.00:preob 2006.168.07:40:41.14/onsource/TRACKING 2006.168.07:40:41.14:!2006.168.07:40:50 2006.168.07:40:50.00:data_valid=on 2006.168.07:40:50.00:midob 2006.168.07:40:50.14/onsource/TRACKING 2006.168.07:40:50.14/wx/27.70,1004.6,72 2006.168.07:40:50.28/cable/+6.4726E-03 2006.168.07:40:51.37/va/01,08,usb,yes,36,38 2006.168.07:40:51.37/va/02,07,usb,yes,36,38 2006.168.07:40:51.37/va/03,06,usb,yes,38,38 2006.168.07:40:51.37/va/04,07,usb,yes,37,40 2006.168.07:40:51.37/va/05,07,usb,yes,36,39 2006.168.07:40:51.37/va/06,06,usb,yes,36,36 2006.168.07:40:51.37/va/07,06,usb,yes,36,36 2006.168.07:40:51.37/va/08,07,usb,yes,34,34 2006.168.07:40:51.60/valo/01,532.99,yes,locked 2006.168.07:40:51.60/valo/02,572.99,yes,locked 2006.168.07:40:51.60/valo/03,672.99,yes,locked 2006.168.07:40:51.60/valo/04,832.99,yes,locked 2006.168.07:40:51.60/valo/05,652.99,yes,locked 2006.168.07:40:51.60/valo/06,772.99,yes,locked 2006.168.07:40:51.60/valo/07,832.99,yes,locked 2006.168.07:40:51.60/valo/08,852.99,yes,locked 2006.168.07:40:52.69/vb/01,04,usb,yes,33,31 2006.168.07:40:52.69/vb/02,04,usb,yes,34,36 2006.168.07:40:52.69/vb/03,04,usb,yes,31,35 2006.168.07:40:52.69/vb/04,04,usb,yes,32,32 2006.168.07:40:52.69/vb/05,04,usb,yes,30,34 2006.168.07:40:52.69/vb/06,04,usb,yes,31,34 2006.168.07:40:52.69/vb/07,04,usb,yes,33,33 2006.168.07:40:52.69/vb/08,04,usb,yes,31,34 2006.168.07:40:52.93/vblo/01,632.99,yes,locked 2006.168.07:40:52.93/vblo/02,640.99,yes,locked 2006.168.07:40:52.93/vblo/03,656.99,yes,locked 2006.168.07:40:52.93/vblo/04,712.99,yes,locked 2006.168.07:40:52.93/vblo/05,744.99,yes,locked 2006.168.07:40:52.93/vblo/06,752.99,yes,locked 2006.168.07:40:52.93/vblo/07,734.99,yes,locked 2006.168.07:40:52.93/vblo/08,744.99,yes,locked 2006.168.07:40:53.08/vabw/8 2006.168.07:40:53.23/vbbw/8 2006.168.07:40:53.36/xfe/off,on,15.2 2006.168.07:40:53.73/ifatt/23,28,28,28 2006.168.07:40:54.08/fmout-gps/S +4.19E-07 2006.168.07:40:54.12:!2006.168.07:41:50 2006.168.07:41:50.00:data_valid=off 2006.168.07:41:50.00:postob 2006.168.07:41:50.22/cable/+6.4718E-03 2006.168.07:41:50.22/wx/27.66,1004.5,72 2006.168.07:41:51.08/fmout-gps/S +4.19E-07 2006.168.07:41:51.08:scan_name=168-0742,k06168,60 2006.168.07:41:51.08:source=1357+769,135755.37,764321.1,2000.0,cw 2006.168.07:41:51.14#flagr#flagr/antenna,new-source 2006.168.07:41:52.14:checkk5 2006.168.07:41:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.168.07:41:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.168.07:41:53.26/chk_autoobs//k5ts3/ autoobs is running! 2006.168.07:41:53.64/chk_autoobs//k5ts4/ autoobs is running! 2006.168.07:41:54.01/chk_obsdata//k5ts1/T1680740??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:41:54.38/chk_obsdata//k5ts2/T1680740??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:41:54.75/chk_obsdata//k5ts3/T1680740??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:41:55.13/chk_obsdata//k5ts4/T1680740??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:41:55.81/k5log//k5ts1_log_newline 2006.168.07:41:56.50/k5log//k5ts2_log_newline 2006.168.07:41:57.18/k5log//k5ts3_log_newline 2006.168.07:41:57.87/k5log//k5ts4_log_newline 2006.168.07:41:57.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.07:41:57.90:4f8m12a=1 2006.168.07:41:57.90$4f8m12a/echo=on 2006.168.07:41:57.90$4f8m12a/pcalon 2006.168.07:41:57.90$pcalon/"no phase cal control is implemented here 2006.168.07:41:57.90$4f8m12a/"tpicd=stop 2006.168.07:41:57.90$4f8m12a/vc4f8 2006.168.07:41:57.90$vc4f8/valo=1,532.99 2006.168.07:41:57.90#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.168.07:41:57.90#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.168.07:41:57.90#ibcon#ireg 17 cls_cnt 0 2006.168.07:41:57.90#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:41:57.90#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:41:57.90#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:41:57.90#ibcon#enter wrdev, iclass 16, count 0 2006.168.07:41:57.90#ibcon#first serial, iclass 16, count 0 2006.168.07:41:57.90#ibcon#enter sib2, iclass 16, count 0 2006.168.07:41:57.90#ibcon#flushed, iclass 16, count 0 2006.168.07:41:57.90#ibcon#about to write, iclass 16, count 0 2006.168.07:41:57.90#ibcon#wrote, iclass 16, count 0 2006.168.07:41:57.90#ibcon#about to read 3, iclass 16, count 0 2006.168.07:41:57.95#ibcon#read 3, iclass 16, count 0 2006.168.07:41:57.95#ibcon#about to read 4, iclass 16, count 0 2006.168.07:41:57.95#ibcon#read 4, iclass 16, count 0 2006.168.07:41:57.95#ibcon#about to read 5, iclass 16, count 0 2006.168.07:41:57.95#ibcon#read 5, iclass 16, count 0 2006.168.07:41:57.95#ibcon#about to read 6, iclass 16, count 0 2006.168.07:41:57.95#ibcon#read 6, iclass 16, count 0 2006.168.07:41:57.95#ibcon#end of sib2, iclass 16, count 0 2006.168.07:41:57.95#ibcon#*mode == 0, iclass 16, count 0 2006.168.07:41:57.95#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.168.07:41:57.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.07:41:57.95#ibcon#*before write, iclass 16, count 0 2006.168.07:41:57.95#ibcon#enter sib2, iclass 16, count 0 2006.168.07:41:57.95#ibcon#flushed, iclass 16, count 0 2006.168.07:41:57.95#ibcon#about to write, iclass 16, count 0 2006.168.07:41:57.95#ibcon#wrote, iclass 16, count 0 2006.168.07:41:57.95#ibcon#about to read 3, iclass 16, count 0 2006.168.07:41:58.00#ibcon#read 3, iclass 16, count 0 2006.168.07:41:58.00#ibcon#about to read 4, iclass 16, count 0 2006.168.07:41:58.00#ibcon#read 4, iclass 16, count 0 2006.168.07:41:58.00#ibcon#about to read 5, iclass 16, count 0 2006.168.07:41:58.00#ibcon#read 5, iclass 16, count 0 2006.168.07:41:58.00#ibcon#about to read 6, iclass 16, count 0 2006.168.07:41:58.00#ibcon#read 6, iclass 16, count 0 2006.168.07:41:58.00#ibcon#end of sib2, iclass 16, count 0 2006.168.07:41:58.00#ibcon#*after write, iclass 16, count 0 2006.168.07:41:58.00#ibcon#*before return 0, iclass 16, count 0 2006.168.07:41:58.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:41:58.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:41:58.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.168.07:41:58.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.168.07:41:58.00$vc4f8/va=1,8 2006.168.07:41:58.00#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.168.07:41:58.00#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.168.07:41:58.00#ibcon#ireg 11 cls_cnt 2 2006.168.07:41:58.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:41:58.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:41:58.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:41:58.00#ibcon#enter wrdev, iclass 18, count 2 2006.168.07:41:58.00#ibcon#first serial, iclass 18, count 2 2006.168.07:41:58.00#ibcon#enter sib2, iclass 18, count 2 2006.168.07:41:58.00#ibcon#flushed, iclass 18, count 2 2006.168.07:41:58.00#ibcon#about to write, iclass 18, count 2 2006.168.07:41:58.00#ibcon#wrote, iclass 18, count 2 2006.168.07:41:58.00#ibcon#about to read 3, iclass 18, count 2 2006.168.07:41:58.02#ibcon#read 3, iclass 18, count 2 2006.168.07:41:58.02#ibcon#about to read 4, iclass 18, count 2 2006.168.07:41:58.02#ibcon#read 4, iclass 18, count 2 2006.168.07:41:58.02#ibcon#about to read 5, iclass 18, count 2 2006.168.07:41:58.02#ibcon#read 5, iclass 18, count 2 2006.168.07:41:58.02#ibcon#about to read 6, iclass 18, count 2 2006.168.07:41:58.02#ibcon#read 6, iclass 18, count 2 2006.168.07:41:58.02#ibcon#end of sib2, iclass 18, count 2 2006.168.07:41:58.02#ibcon#*mode == 0, iclass 18, count 2 2006.168.07:41:58.02#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.168.07:41:58.02#ibcon#[25=AT01-08\r\n] 2006.168.07:41:58.02#ibcon#*before write, iclass 18, count 2 2006.168.07:41:58.02#ibcon#enter sib2, iclass 18, count 2 2006.168.07:41:58.02#ibcon#flushed, iclass 18, count 2 2006.168.07:41:58.02#ibcon#about to write, iclass 18, count 2 2006.168.07:41:58.02#ibcon#wrote, iclass 18, count 2 2006.168.07:41:58.02#ibcon#about to read 3, iclass 18, count 2 2006.168.07:41:58.06#ibcon#read 3, iclass 18, count 2 2006.168.07:41:58.06#ibcon#about to read 4, iclass 18, count 2 2006.168.07:41:58.06#ibcon#read 4, iclass 18, count 2 2006.168.07:41:58.06#ibcon#about to read 5, iclass 18, count 2 2006.168.07:41:58.06#ibcon#read 5, iclass 18, count 2 2006.168.07:41:58.06#ibcon#about to read 6, iclass 18, count 2 2006.168.07:41:58.06#ibcon#read 6, iclass 18, count 2 2006.168.07:41:58.06#ibcon#end of sib2, iclass 18, count 2 2006.168.07:41:58.06#ibcon#*after write, iclass 18, count 2 2006.168.07:41:58.06#ibcon#*before return 0, iclass 18, count 2 2006.168.07:41:58.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:41:58.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:41:58.06#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.168.07:41:58.06#ibcon#ireg 7 cls_cnt 0 2006.168.07:41:58.06#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:41:58.18#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:41:58.18#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:41:58.18#ibcon#enter wrdev, iclass 18, count 0 2006.168.07:41:58.18#ibcon#first serial, iclass 18, count 0 2006.168.07:41:58.18#ibcon#enter sib2, iclass 18, count 0 2006.168.07:41:58.18#ibcon#flushed, iclass 18, count 0 2006.168.07:41:58.18#ibcon#about to write, iclass 18, count 0 2006.168.07:41:58.18#ibcon#wrote, iclass 18, count 0 2006.168.07:41:58.18#ibcon#about to read 3, iclass 18, count 0 2006.168.07:41:58.20#ibcon#read 3, iclass 18, count 0 2006.168.07:41:58.20#ibcon#about to read 4, iclass 18, count 0 2006.168.07:41:58.20#ibcon#read 4, iclass 18, count 0 2006.168.07:41:58.20#ibcon#about to read 5, iclass 18, count 0 2006.168.07:41:58.20#ibcon#read 5, iclass 18, count 0 2006.168.07:41:58.20#ibcon#about to read 6, iclass 18, count 0 2006.168.07:41:58.20#ibcon#read 6, iclass 18, count 0 2006.168.07:41:58.20#ibcon#end of sib2, iclass 18, count 0 2006.168.07:41:58.20#ibcon#*mode == 0, iclass 18, count 0 2006.168.07:41:58.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.07:41:58.20#ibcon#[25=USB\r\n] 2006.168.07:41:58.20#ibcon#*before write, iclass 18, count 0 2006.168.07:41:58.20#ibcon#enter sib2, iclass 18, count 0 2006.168.07:41:58.20#ibcon#flushed, iclass 18, count 0 2006.168.07:41:58.20#ibcon#about to write, iclass 18, count 0 2006.168.07:41:58.20#ibcon#wrote, iclass 18, count 0 2006.168.07:41:58.20#ibcon#about to read 3, iclass 18, count 0 2006.168.07:41:58.23#ibcon#read 3, iclass 18, count 0 2006.168.07:41:58.23#ibcon#about to read 4, iclass 18, count 0 2006.168.07:41:58.23#ibcon#read 4, iclass 18, count 0 2006.168.07:41:58.23#ibcon#about to read 5, iclass 18, count 0 2006.168.07:41:58.23#ibcon#read 5, iclass 18, count 0 2006.168.07:41:58.23#ibcon#about to read 6, iclass 18, count 0 2006.168.07:41:58.23#ibcon#read 6, iclass 18, count 0 2006.168.07:41:58.23#ibcon#end of sib2, iclass 18, count 0 2006.168.07:41:58.23#ibcon#*after write, iclass 18, count 0 2006.168.07:41:58.23#ibcon#*before return 0, iclass 18, count 0 2006.168.07:41:58.23#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:41:58.23#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:41:58.23#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.07:41:58.23#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.07:41:58.23$vc4f8/valo=2,572.99 2006.168.07:41:58.23#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.168.07:41:58.23#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.168.07:41:58.23#ibcon#ireg 17 cls_cnt 0 2006.168.07:41:58.23#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:41:58.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:41:58.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:41:58.23#ibcon#enter wrdev, iclass 20, count 0 2006.168.07:41:58.23#ibcon#first serial, iclass 20, count 0 2006.168.07:41:58.23#ibcon#enter sib2, iclass 20, count 0 2006.168.07:41:58.23#ibcon#flushed, iclass 20, count 0 2006.168.07:41:58.23#ibcon#about to write, iclass 20, count 0 2006.168.07:41:58.23#ibcon#wrote, iclass 20, count 0 2006.168.07:41:58.23#ibcon#about to read 3, iclass 20, count 0 2006.168.07:41:58.25#ibcon#read 3, iclass 20, count 0 2006.168.07:41:58.25#ibcon#about to read 4, iclass 20, count 0 2006.168.07:41:58.25#ibcon#read 4, iclass 20, count 0 2006.168.07:41:58.25#ibcon#about to read 5, iclass 20, count 0 2006.168.07:41:58.25#ibcon#read 5, iclass 20, count 0 2006.168.07:41:58.25#ibcon#about to read 6, iclass 20, count 0 2006.168.07:41:58.25#ibcon#read 6, iclass 20, count 0 2006.168.07:41:58.25#ibcon#end of sib2, iclass 20, count 0 2006.168.07:41:58.25#ibcon#*mode == 0, iclass 20, count 0 2006.168.07:41:58.25#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.168.07:41:58.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.07:41:58.25#ibcon#*before write, iclass 20, count 0 2006.168.07:41:58.25#ibcon#enter sib2, iclass 20, count 0 2006.168.07:41:58.25#ibcon#flushed, iclass 20, count 0 2006.168.07:41:58.25#ibcon#about to write, iclass 20, count 0 2006.168.07:41:58.25#ibcon#wrote, iclass 20, count 0 2006.168.07:41:58.25#ibcon#about to read 3, iclass 20, count 0 2006.168.07:41:58.29#ibcon#read 3, iclass 20, count 0 2006.168.07:41:58.29#ibcon#about to read 4, iclass 20, count 0 2006.168.07:41:58.29#ibcon#read 4, iclass 20, count 0 2006.168.07:41:58.29#ibcon#about to read 5, iclass 20, count 0 2006.168.07:41:58.29#ibcon#read 5, iclass 20, count 0 2006.168.07:41:58.29#ibcon#about to read 6, iclass 20, count 0 2006.168.07:41:58.29#ibcon#read 6, iclass 20, count 0 2006.168.07:41:58.29#ibcon#end of sib2, iclass 20, count 0 2006.168.07:41:58.29#ibcon#*after write, iclass 20, count 0 2006.168.07:41:58.29#ibcon#*before return 0, iclass 20, count 0 2006.168.07:41:58.29#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:41:58.29#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:41:58.29#ibcon#about to clear, iclass 20 cls_cnt 0 2006.168.07:41:58.29#ibcon#cleared, iclass 20 cls_cnt 0 2006.168.07:41:58.29$vc4f8/va=2,7 2006.168.07:41:58.29#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.168.07:41:58.29#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.168.07:41:58.29#ibcon#ireg 11 cls_cnt 2 2006.168.07:41:58.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:41:58.35#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:41:58.35#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:41:58.35#ibcon#enter wrdev, iclass 22, count 2 2006.168.07:41:58.35#ibcon#first serial, iclass 22, count 2 2006.168.07:41:58.35#ibcon#enter sib2, iclass 22, count 2 2006.168.07:41:58.35#ibcon#flushed, iclass 22, count 2 2006.168.07:41:58.35#ibcon#about to write, iclass 22, count 2 2006.168.07:41:58.35#ibcon#wrote, iclass 22, count 2 2006.168.07:41:58.35#ibcon#about to read 3, iclass 22, count 2 2006.168.07:41:58.37#ibcon#read 3, iclass 22, count 2 2006.168.07:41:58.37#ibcon#about to read 4, iclass 22, count 2 2006.168.07:41:58.37#ibcon#read 4, iclass 22, count 2 2006.168.07:41:58.37#ibcon#about to read 5, iclass 22, count 2 2006.168.07:41:58.37#ibcon#read 5, iclass 22, count 2 2006.168.07:41:58.37#ibcon#about to read 6, iclass 22, count 2 2006.168.07:41:58.37#ibcon#read 6, iclass 22, count 2 2006.168.07:41:58.37#ibcon#end of sib2, iclass 22, count 2 2006.168.07:41:58.37#ibcon#*mode == 0, iclass 22, count 2 2006.168.07:41:58.37#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.168.07:41:58.37#ibcon#[25=AT02-07\r\n] 2006.168.07:41:58.37#ibcon#*before write, iclass 22, count 2 2006.168.07:41:58.37#ibcon#enter sib2, iclass 22, count 2 2006.168.07:41:58.37#ibcon#flushed, iclass 22, count 2 2006.168.07:41:58.37#ibcon#about to write, iclass 22, count 2 2006.168.07:41:58.37#ibcon#wrote, iclass 22, count 2 2006.168.07:41:58.37#ibcon#about to read 3, iclass 22, count 2 2006.168.07:41:58.40#ibcon#read 3, iclass 22, count 2 2006.168.07:41:58.40#ibcon#about to read 4, iclass 22, count 2 2006.168.07:41:58.40#ibcon#read 4, iclass 22, count 2 2006.168.07:41:58.40#ibcon#about to read 5, iclass 22, count 2 2006.168.07:41:58.40#ibcon#read 5, iclass 22, count 2 2006.168.07:41:58.40#ibcon#about to read 6, iclass 22, count 2 2006.168.07:41:58.40#ibcon#read 6, iclass 22, count 2 2006.168.07:41:58.40#ibcon#end of sib2, iclass 22, count 2 2006.168.07:41:58.40#ibcon#*after write, iclass 22, count 2 2006.168.07:41:58.40#ibcon#*before return 0, iclass 22, count 2 2006.168.07:41:58.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:41:58.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:41:58.40#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.168.07:41:58.40#ibcon#ireg 7 cls_cnt 0 2006.168.07:41:58.40#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:41:58.52#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:41:58.52#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:41:58.52#ibcon#enter wrdev, iclass 22, count 0 2006.168.07:41:58.52#ibcon#first serial, iclass 22, count 0 2006.168.07:41:58.52#ibcon#enter sib2, iclass 22, count 0 2006.168.07:41:58.52#ibcon#flushed, iclass 22, count 0 2006.168.07:41:58.52#ibcon#about to write, iclass 22, count 0 2006.168.07:41:58.52#ibcon#wrote, iclass 22, count 0 2006.168.07:41:58.52#ibcon#about to read 3, iclass 22, count 0 2006.168.07:41:58.54#ibcon#read 3, iclass 22, count 0 2006.168.07:41:58.54#ibcon#about to read 4, iclass 22, count 0 2006.168.07:41:58.54#ibcon#read 4, iclass 22, count 0 2006.168.07:41:58.54#ibcon#about to read 5, iclass 22, count 0 2006.168.07:41:58.54#ibcon#read 5, iclass 22, count 0 2006.168.07:41:58.54#ibcon#about to read 6, iclass 22, count 0 2006.168.07:41:58.54#ibcon#read 6, iclass 22, count 0 2006.168.07:41:58.54#ibcon#end of sib2, iclass 22, count 0 2006.168.07:41:58.54#ibcon#*mode == 0, iclass 22, count 0 2006.168.07:41:58.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.168.07:41:58.54#ibcon#[25=USB\r\n] 2006.168.07:41:58.54#ibcon#*before write, iclass 22, count 0 2006.168.07:41:58.54#ibcon#enter sib2, iclass 22, count 0 2006.168.07:41:58.54#ibcon#flushed, iclass 22, count 0 2006.168.07:41:58.54#ibcon#about to write, iclass 22, count 0 2006.168.07:41:58.54#ibcon#wrote, iclass 22, count 0 2006.168.07:41:58.54#ibcon#about to read 3, iclass 22, count 0 2006.168.07:41:58.57#ibcon#read 3, iclass 22, count 0 2006.168.07:41:58.57#ibcon#about to read 4, iclass 22, count 0 2006.168.07:41:58.57#ibcon#read 4, iclass 22, count 0 2006.168.07:41:58.57#ibcon#about to read 5, iclass 22, count 0 2006.168.07:41:58.57#ibcon#read 5, iclass 22, count 0 2006.168.07:41:58.57#ibcon#about to read 6, iclass 22, count 0 2006.168.07:41:58.57#ibcon#read 6, iclass 22, count 0 2006.168.07:41:58.57#ibcon#end of sib2, iclass 22, count 0 2006.168.07:41:58.57#ibcon#*after write, iclass 22, count 0 2006.168.07:41:58.57#ibcon#*before return 0, iclass 22, count 0 2006.168.07:41:58.57#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:41:58.57#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:41:58.57#ibcon#about to clear, iclass 22 cls_cnt 0 2006.168.07:41:58.57#ibcon#cleared, iclass 22 cls_cnt 0 2006.168.07:41:58.57$vc4f8/valo=3,672.99 2006.168.07:41:58.57#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.168.07:41:58.57#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.168.07:41:58.57#ibcon#ireg 17 cls_cnt 0 2006.168.07:41:58.57#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.168.07:41:58.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.168.07:41:58.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.168.07:41:58.57#ibcon#enter wrdev, iclass 24, count 0 2006.168.07:41:58.57#ibcon#first serial, iclass 24, count 0 2006.168.07:41:58.57#ibcon#enter sib2, iclass 24, count 0 2006.168.07:41:58.57#ibcon#flushed, iclass 24, count 0 2006.168.07:41:58.57#ibcon#about to write, iclass 24, count 0 2006.168.07:41:58.57#ibcon#wrote, iclass 24, count 0 2006.168.07:41:58.57#ibcon#about to read 3, iclass 24, count 0 2006.168.07:41:58.59#ibcon#read 3, iclass 24, count 0 2006.168.07:41:58.59#ibcon#about to read 4, iclass 24, count 0 2006.168.07:41:58.59#ibcon#read 4, iclass 24, count 0 2006.168.07:41:58.59#ibcon#about to read 5, iclass 24, count 0 2006.168.07:41:58.59#ibcon#read 5, iclass 24, count 0 2006.168.07:41:58.59#ibcon#about to read 6, iclass 24, count 0 2006.168.07:41:58.59#ibcon#read 6, iclass 24, count 0 2006.168.07:41:58.59#ibcon#end of sib2, iclass 24, count 0 2006.168.07:41:58.59#ibcon#*mode == 0, iclass 24, count 0 2006.168.07:41:58.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.168.07:41:58.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.07:41:58.59#ibcon#*before write, iclass 24, count 0 2006.168.07:41:58.59#ibcon#enter sib2, iclass 24, count 0 2006.168.07:41:58.59#ibcon#flushed, iclass 24, count 0 2006.168.07:41:58.59#ibcon#about to write, iclass 24, count 0 2006.168.07:41:58.59#ibcon#wrote, iclass 24, count 0 2006.168.07:41:58.59#ibcon#about to read 3, iclass 24, count 0 2006.168.07:41:58.63#ibcon#read 3, iclass 24, count 0 2006.168.07:41:58.63#ibcon#about to read 4, iclass 24, count 0 2006.168.07:41:58.63#ibcon#read 4, iclass 24, count 0 2006.168.07:41:58.63#ibcon#about to read 5, iclass 24, count 0 2006.168.07:41:58.63#ibcon#read 5, iclass 24, count 0 2006.168.07:41:58.63#ibcon#about to read 6, iclass 24, count 0 2006.168.07:41:58.63#ibcon#read 6, iclass 24, count 0 2006.168.07:41:58.63#ibcon#end of sib2, iclass 24, count 0 2006.168.07:41:58.63#ibcon#*after write, iclass 24, count 0 2006.168.07:41:58.63#ibcon#*before return 0, iclass 24, count 0 2006.168.07:41:58.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.168.07:41:58.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.168.07:41:58.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.168.07:41:58.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.168.07:41:58.63$vc4f8/va=3,6 2006.168.07:41:58.63#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.168.07:41:58.63#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.168.07:41:58.63#ibcon#ireg 11 cls_cnt 2 2006.168.07:41:58.63#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.168.07:41:58.69#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.168.07:41:58.69#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.168.07:41:58.69#ibcon#enter wrdev, iclass 26, count 2 2006.168.07:41:58.69#ibcon#first serial, iclass 26, count 2 2006.168.07:41:58.69#ibcon#enter sib2, iclass 26, count 2 2006.168.07:41:58.69#ibcon#flushed, iclass 26, count 2 2006.168.07:41:58.69#ibcon#about to write, iclass 26, count 2 2006.168.07:41:58.69#ibcon#wrote, iclass 26, count 2 2006.168.07:41:58.69#ibcon#about to read 3, iclass 26, count 2 2006.168.07:41:58.71#ibcon#read 3, iclass 26, count 2 2006.168.07:41:58.71#ibcon#about to read 4, iclass 26, count 2 2006.168.07:41:58.71#ibcon#read 4, iclass 26, count 2 2006.168.07:41:58.71#ibcon#about to read 5, iclass 26, count 2 2006.168.07:41:58.71#ibcon#read 5, iclass 26, count 2 2006.168.07:41:58.71#ibcon#about to read 6, iclass 26, count 2 2006.168.07:41:58.71#ibcon#read 6, iclass 26, count 2 2006.168.07:41:58.71#ibcon#end of sib2, iclass 26, count 2 2006.168.07:41:58.71#ibcon#*mode == 0, iclass 26, count 2 2006.168.07:41:58.71#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.168.07:41:58.71#ibcon#[25=AT03-06\r\n] 2006.168.07:41:58.71#ibcon#*before write, iclass 26, count 2 2006.168.07:41:58.71#ibcon#enter sib2, iclass 26, count 2 2006.168.07:41:58.71#ibcon#flushed, iclass 26, count 2 2006.168.07:41:58.71#ibcon#about to write, iclass 26, count 2 2006.168.07:41:58.71#ibcon#wrote, iclass 26, count 2 2006.168.07:41:58.71#ibcon#about to read 3, iclass 26, count 2 2006.168.07:41:58.74#ibcon#read 3, iclass 26, count 2 2006.168.07:41:58.74#ibcon#about to read 4, iclass 26, count 2 2006.168.07:41:58.74#ibcon#read 4, iclass 26, count 2 2006.168.07:41:58.74#ibcon#about to read 5, iclass 26, count 2 2006.168.07:41:58.74#ibcon#read 5, iclass 26, count 2 2006.168.07:41:58.74#ibcon#about to read 6, iclass 26, count 2 2006.168.07:41:58.74#ibcon#read 6, iclass 26, count 2 2006.168.07:41:58.74#ibcon#end of sib2, iclass 26, count 2 2006.168.07:41:58.74#ibcon#*after write, iclass 26, count 2 2006.168.07:41:58.74#ibcon#*before return 0, iclass 26, count 2 2006.168.07:41:58.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.168.07:41:58.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.168.07:41:58.74#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.168.07:41:58.74#ibcon#ireg 7 cls_cnt 0 2006.168.07:41:58.74#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.168.07:41:58.86#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.168.07:41:58.86#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.168.07:41:58.86#ibcon#enter wrdev, iclass 26, count 0 2006.168.07:41:58.86#ibcon#first serial, iclass 26, count 0 2006.168.07:41:58.86#ibcon#enter sib2, iclass 26, count 0 2006.168.07:41:58.86#ibcon#flushed, iclass 26, count 0 2006.168.07:41:58.86#ibcon#about to write, iclass 26, count 0 2006.168.07:41:58.86#ibcon#wrote, iclass 26, count 0 2006.168.07:41:58.86#ibcon#about to read 3, iclass 26, count 0 2006.168.07:41:58.88#ibcon#read 3, iclass 26, count 0 2006.168.07:41:58.88#ibcon#about to read 4, iclass 26, count 0 2006.168.07:41:58.88#ibcon#read 4, iclass 26, count 0 2006.168.07:41:58.88#ibcon#about to read 5, iclass 26, count 0 2006.168.07:41:58.88#ibcon#read 5, iclass 26, count 0 2006.168.07:41:58.88#ibcon#about to read 6, iclass 26, count 0 2006.168.07:41:58.88#ibcon#read 6, iclass 26, count 0 2006.168.07:41:58.88#ibcon#end of sib2, iclass 26, count 0 2006.168.07:41:58.88#ibcon#*mode == 0, iclass 26, count 0 2006.168.07:41:58.88#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.168.07:41:58.88#ibcon#[25=USB\r\n] 2006.168.07:41:58.88#ibcon#*before write, iclass 26, count 0 2006.168.07:41:58.88#ibcon#enter sib2, iclass 26, count 0 2006.168.07:41:58.88#ibcon#flushed, iclass 26, count 0 2006.168.07:41:58.88#ibcon#about to write, iclass 26, count 0 2006.168.07:41:58.88#ibcon#wrote, iclass 26, count 0 2006.168.07:41:58.88#ibcon#about to read 3, iclass 26, count 0 2006.168.07:41:58.91#ibcon#read 3, iclass 26, count 0 2006.168.07:41:58.91#ibcon#about to read 4, iclass 26, count 0 2006.168.07:41:58.91#ibcon#read 4, iclass 26, count 0 2006.168.07:41:58.91#ibcon#about to read 5, iclass 26, count 0 2006.168.07:41:58.91#ibcon#read 5, iclass 26, count 0 2006.168.07:41:58.91#ibcon#about to read 6, iclass 26, count 0 2006.168.07:41:58.91#ibcon#read 6, iclass 26, count 0 2006.168.07:41:58.91#ibcon#end of sib2, iclass 26, count 0 2006.168.07:41:58.91#ibcon#*after write, iclass 26, count 0 2006.168.07:41:58.91#ibcon#*before return 0, iclass 26, count 0 2006.168.07:41:58.91#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.168.07:41:58.91#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.168.07:41:58.91#ibcon#about to clear, iclass 26 cls_cnt 0 2006.168.07:41:58.91#ibcon#cleared, iclass 26 cls_cnt 0 2006.168.07:41:58.91$vc4f8/valo=4,832.99 2006.168.07:41:58.91#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.168.07:41:58.91#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.168.07:41:58.91#ibcon#ireg 17 cls_cnt 0 2006.168.07:41:58.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:41:58.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:41:58.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:41:58.91#ibcon#enter wrdev, iclass 28, count 0 2006.168.07:41:58.91#ibcon#first serial, iclass 28, count 0 2006.168.07:41:58.91#ibcon#enter sib2, iclass 28, count 0 2006.168.07:41:58.91#ibcon#flushed, iclass 28, count 0 2006.168.07:41:58.91#ibcon#about to write, iclass 28, count 0 2006.168.07:41:58.91#ibcon#wrote, iclass 28, count 0 2006.168.07:41:58.91#ibcon#about to read 3, iclass 28, count 0 2006.168.07:41:58.93#ibcon#read 3, iclass 28, count 0 2006.168.07:41:58.93#ibcon#about to read 4, iclass 28, count 0 2006.168.07:41:58.93#ibcon#read 4, iclass 28, count 0 2006.168.07:41:58.93#ibcon#about to read 5, iclass 28, count 0 2006.168.07:41:58.93#ibcon#read 5, iclass 28, count 0 2006.168.07:41:58.93#ibcon#about to read 6, iclass 28, count 0 2006.168.07:41:58.93#ibcon#read 6, iclass 28, count 0 2006.168.07:41:58.93#ibcon#end of sib2, iclass 28, count 0 2006.168.07:41:58.93#ibcon#*mode == 0, iclass 28, count 0 2006.168.07:41:58.93#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.168.07:41:58.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.07:41:58.93#ibcon#*before write, iclass 28, count 0 2006.168.07:41:58.93#ibcon#enter sib2, iclass 28, count 0 2006.168.07:41:58.93#ibcon#flushed, iclass 28, count 0 2006.168.07:41:58.93#ibcon#about to write, iclass 28, count 0 2006.168.07:41:58.93#ibcon#wrote, iclass 28, count 0 2006.168.07:41:58.93#ibcon#about to read 3, iclass 28, count 0 2006.168.07:41:58.97#ibcon#read 3, iclass 28, count 0 2006.168.07:41:58.97#ibcon#about to read 4, iclass 28, count 0 2006.168.07:41:58.97#ibcon#read 4, iclass 28, count 0 2006.168.07:41:58.97#ibcon#about to read 5, iclass 28, count 0 2006.168.07:41:58.97#ibcon#read 5, iclass 28, count 0 2006.168.07:41:58.97#ibcon#about to read 6, iclass 28, count 0 2006.168.07:41:58.97#ibcon#read 6, iclass 28, count 0 2006.168.07:41:58.97#ibcon#end of sib2, iclass 28, count 0 2006.168.07:41:58.97#ibcon#*after write, iclass 28, count 0 2006.168.07:41:58.97#ibcon#*before return 0, iclass 28, count 0 2006.168.07:41:58.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:41:58.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:41:58.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.168.07:41:58.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.168.07:41:58.97$vc4f8/va=4,7 2006.168.07:41:58.97#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.168.07:41:58.97#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.168.07:41:58.97#ibcon#ireg 11 cls_cnt 2 2006.168.07:41:58.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:41:59.03#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:41:59.03#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:41:59.03#ibcon#enter wrdev, iclass 30, count 2 2006.168.07:41:59.03#ibcon#first serial, iclass 30, count 2 2006.168.07:41:59.03#ibcon#enter sib2, iclass 30, count 2 2006.168.07:41:59.03#ibcon#flushed, iclass 30, count 2 2006.168.07:41:59.03#ibcon#about to write, iclass 30, count 2 2006.168.07:41:59.03#ibcon#wrote, iclass 30, count 2 2006.168.07:41:59.03#ibcon#about to read 3, iclass 30, count 2 2006.168.07:41:59.05#ibcon#read 3, iclass 30, count 2 2006.168.07:41:59.05#ibcon#about to read 4, iclass 30, count 2 2006.168.07:41:59.05#ibcon#read 4, iclass 30, count 2 2006.168.07:41:59.05#ibcon#about to read 5, iclass 30, count 2 2006.168.07:41:59.05#ibcon#read 5, iclass 30, count 2 2006.168.07:41:59.05#ibcon#about to read 6, iclass 30, count 2 2006.168.07:41:59.05#ibcon#read 6, iclass 30, count 2 2006.168.07:41:59.05#ibcon#end of sib2, iclass 30, count 2 2006.168.07:41:59.05#ibcon#*mode == 0, iclass 30, count 2 2006.168.07:41:59.05#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.168.07:41:59.05#ibcon#[25=AT04-07\r\n] 2006.168.07:41:59.05#ibcon#*before write, iclass 30, count 2 2006.168.07:41:59.05#ibcon#enter sib2, iclass 30, count 2 2006.168.07:41:59.05#ibcon#flushed, iclass 30, count 2 2006.168.07:41:59.05#ibcon#about to write, iclass 30, count 2 2006.168.07:41:59.05#ibcon#wrote, iclass 30, count 2 2006.168.07:41:59.05#ibcon#about to read 3, iclass 30, count 2 2006.168.07:41:59.08#ibcon#read 3, iclass 30, count 2 2006.168.07:41:59.08#ibcon#about to read 4, iclass 30, count 2 2006.168.07:41:59.08#ibcon#read 4, iclass 30, count 2 2006.168.07:41:59.08#ibcon#about to read 5, iclass 30, count 2 2006.168.07:41:59.08#ibcon#read 5, iclass 30, count 2 2006.168.07:41:59.08#ibcon#about to read 6, iclass 30, count 2 2006.168.07:41:59.08#ibcon#read 6, iclass 30, count 2 2006.168.07:41:59.08#ibcon#end of sib2, iclass 30, count 2 2006.168.07:41:59.08#ibcon#*after write, iclass 30, count 2 2006.168.07:41:59.08#ibcon#*before return 0, iclass 30, count 2 2006.168.07:41:59.08#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:41:59.08#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:41:59.08#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.168.07:41:59.08#ibcon#ireg 7 cls_cnt 0 2006.168.07:41:59.08#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:41:59.20#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:41:59.20#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:41:59.20#ibcon#enter wrdev, iclass 30, count 0 2006.168.07:41:59.20#ibcon#first serial, iclass 30, count 0 2006.168.07:41:59.20#ibcon#enter sib2, iclass 30, count 0 2006.168.07:41:59.20#ibcon#flushed, iclass 30, count 0 2006.168.07:41:59.20#ibcon#about to write, iclass 30, count 0 2006.168.07:41:59.20#ibcon#wrote, iclass 30, count 0 2006.168.07:41:59.20#ibcon#about to read 3, iclass 30, count 0 2006.168.07:41:59.22#ibcon#read 3, iclass 30, count 0 2006.168.07:41:59.22#ibcon#about to read 4, iclass 30, count 0 2006.168.07:41:59.22#ibcon#read 4, iclass 30, count 0 2006.168.07:41:59.22#ibcon#about to read 5, iclass 30, count 0 2006.168.07:41:59.22#ibcon#read 5, iclass 30, count 0 2006.168.07:41:59.22#ibcon#about to read 6, iclass 30, count 0 2006.168.07:41:59.22#ibcon#read 6, iclass 30, count 0 2006.168.07:41:59.22#ibcon#end of sib2, iclass 30, count 0 2006.168.07:41:59.22#ibcon#*mode == 0, iclass 30, count 0 2006.168.07:41:59.22#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.168.07:41:59.22#ibcon#[25=USB\r\n] 2006.168.07:41:59.22#ibcon#*before write, iclass 30, count 0 2006.168.07:41:59.22#ibcon#enter sib2, iclass 30, count 0 2006.168.07:41:59.22#ibcon#flushed, iclass 30, count 0 2006.168.07:41:59.22#ibcon#about to write, iclass 30, count 0 2006.168.07:41:59.22#ibcon#wrote, iclass 30, count 0 2006.168.07:41:59.22#ibcon#about to read 3, iclass 30, count 0 2006.168.07:41:59.25#ibcon#read 3, iclass 30, count 0 2006.168.07:41:59.25#ibcon#about to read 4, iclass 30, count 0 2006.168.07:41:59.25#ibcon#read 4, iclass 30, count 0 2006.168.07:41:59.25#ibcon#about to read 5, iclass 30, count 0 2006.168.07:41:59.25#ibcon#read 5, iclass 30, count 0 2006.168.07:41:59.25#ibcon#about to read 6, iclass 30, count 0 2006.168.07:41:59.25#ibcon#read 6, iclass 30, count 0 2006.168.07:41:59.25#ibcon#end of sib2, iclass 30, count 0 2006.168.07:41:59.25#ibcon#*after write, iclass 30, count 0 2006.168.07:41:59.25#ibcon#*before return 0, iclass 30, count 0 2006.168.07:41:59.25#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:41:59.25#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:41:59.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.168.07:41:59.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.168.07:41:59.25$vc4f8/valo=5,652.99 2006.168.07:41:59.25#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.168.07:41:59.25#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.168.07:41:59.25#ibcon#ireg 17 cls_cnt 0 2006.168.07:41:59.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:41:59.25#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:41:59.25#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:41:59.25#ibcon#enter wrdev, iclass 32, count 0 2006.168.07:41:59.25#ibcon#first serial, iclass 32, count 0 2006.168.07:41:59.25#ibcon#enter sib2, iclass 32, count 0 2006.168.07:41:59.25#ibcon#flushed, iclass 32, count 0 2006.168.07:41:59.25#ibcon#about to write, iclass 32, count 0 2006.168.07:41:59.25#ibcon#wrote, iclass 32, count 0 2006.168.07:41:59.25#ibcon#about to read 3, iclass 32, count 0 2006.168.07:41:59.27#ibcon#read 3, iclass 32, count 0 2006.168.07:41:59.27#ibcon#about to read 4, iclass 32, count 0 2006.168.07:41:59.27#ibcon#read 4, iclass 32, count 0 2006.168.07:41:59.27#ibcon#about to read 5, iclass 32, count 0 2006.168.07:41:59.27#ibcon#read 5, iclass 32, count 0 2006.168.07:41:59.27#ibcon#about to read 6, iclass 32, count 0 2006.168.07:41:59.27#ibcon#read 6, iclass 32, count 0 2006.168.07:41:59.27#ibcon#end of sib2, iclass 32, count 0 2006.168.07:41:59.27#ibcon#*mode == 0, iclass 32, count 0 2006.168.07:41:59.27#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.168.07:41:59.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.07:41:59.27#ibcon#*before write, iclass 32, count 0 2006.168.07:41:59.27#ibcon#enter sib2, iclass 32, count 0 2006.168.07:41:59.27#ibcon#flushed, iclass 32, count 0 2006.168.07:41:59.27#ibcon#about to write, iclass 32, count 0 2006.168.07:41:59.27#ibcon#wrote, iclass 32, count 0 2006.168.07:41:59.27#ibcon#about to read 3, iclass 32, count 0 2006.168.07:41:59.31#ibcon#read 3, iclass 32, count 0 2006.168.07:41:59.31#ibcon#about to read 4, iclass 32, count 0 2006.168.07:41:59.31#ibcon#read 4, iclass 32, count 0 2006.168.07:41:59.31#ibcon#about to read 5, iclass 32, count 0 2006.168.07:41:59.31#ibcon#read 5, iclass 32, count 0 2006.168.07:41:59.31#ibcon#about to read 6, iclass 32, count 0 2006.168.07:41:59.31#ibcon#read 6, iclass 32, count 0 2006.168.07:41:59.31#ibcon#end of sib2, iclass 32, count 0 2006.168.07:41:59.31#ibcon#*after write, iclass 32, count 0 2006.168.07:41:59.31#ibcon#*before return 0, iclass 32, count 0 2006.168.07:41:59.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:41:59.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:41:59.31#ibcon#about to clear, iclass 32 cls_cnt 0 2006.168.07:41:59.31#ibcon#cleared, iclass 32 cls_cnt 0 2006.168.07:41:59.31$vc4f8/va=5,7 2006.168.07:41:59.31#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.168.07:41:59.31#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.168.07:41:59.31#ibcon#ireg 11 cls_cnt 2 2006.168.07:41:59.31#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:41:59.37#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:41:59.37#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:41:59.37#ibcon#enter wrdev, iclass 34, count 2 2006.168.07:41:59.37#ibcon#first serial, iclass 34, count 2 2006.168.07:41:59.37#ibcon#enter sib2, iclass 34, count 2 2006.168.07:41:59.37#ibcon#flushed, iclass 34, count 2 2006.168.07:41:59.37#ibcon#about to write, iclass 34, count 2 2006.168.07:41:59.37#ibcon#wrote, iclass 34, count 2 2006.168.07:41:59.37#ibcon#about to read 3, iclass 34, count 2 2006.168.07:41:59.39#ibcon#read 3, iclass 34, count 2 2006.168.07:41:59.39#ibcon#about to read 4, iclass 34, count 2 2006.168.07:41:59.39#ibcon#read 4, iclass 34, count 2 2006.168.07:41:59.39#ibcon#about to read 5, iclass 34, count 2 2006.168.07:41:59.39#ibcon#read 5, iclass 34, count 2 2006.168.07:41:59.39#ibcon#about to read 6, iclass 34, count 2 2006.168.07:41:59.39#ibcon#read 6, iclass 34, count 2 2006.168.07:41:59.39#ibcon#end of sib2, iclass 34, count 2 2006.168.07:41:59.39#ibcon#*mode == 0, iclass 34, count 2 2006.168.07:41:59.39#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.168.07:41:59.39#ibcon#[25=AT05-07\r\n] 2006.168.07:41:59.39#ibcon#*before write, iclass 34, count 2 2006.168.07:41:59.39#ibcon#enter sib2, iclass 34, count 2 2006.168.07:41:59.39#ibcon#flushed, iclass 34, count 2 2006.168.07:41:59.39#ibcon#about to write, iclass 34, count 2 2006.168.07:41:59.39#ibcon#wrote, iclass 34, count 2 2006.168.07:41:59.39#ibcon#about to read 3, iclass 34, count 2 2006.168.07:41:59.42#ibcon#read 3, iclass 34, count 2 2006.168.07:41:59.42#ibcon#about to read 4, iclass 34, count 2 2006.168.07:41:59.42#ibcon#read 4, iclass 34, count 2 2006.168.07:41:59.42#ibcon#about to read 5, iclass 34, count 2 2006.168.07:41:59.42#ibcon#read 5, iclass 34, count 2 2006.168.07:41:59.42#ibcon#about to read 6, iclass 34, count 2 2006.168.07:41:59.42#ibcon#read 6, iclass 34, count 2 2006.168.07:41:59.42#ibcon#end of sib2, iclass 34, count 2 2006.168.07:41:59.42#ibcon#*after write, iclass 34, count 2 2006.168.07:41:59.42#ibcon#*before return 0, iclass 34, count 2 2006.168.07:41:59.42#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:41:59.42#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:41:59.42#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.168.07:41:59.42#ibcon#ireg 7 cls_cnt 0 2006.168.07:41:59.42#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:41:59.54#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:41:59.54#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:41:59.54#ibcon#enter wrdev, iclass 34, count 0 2006.168.07:41:59.54#ibcon#first serial, iclass 34, count 0 2006.168.07:41:59.54#ibcon#enter sib2, iclass 34, count 0 2006.168.07:41:59.54#ibcon#flushed, iclass 34, count 0 2006.168.07:41:59.54#ibcon#about to write, iclass 34, count 0 2006.168.07:41:59.54#ibcon#wrote, iclass 34, count 0 2006.168.07:41:59.54#ibcon#about to read 3, iclass 34, count 0 2006.168.07:41:59.56#ibcon#read 3, iclass 34, count 0 2006.168.07:41:59.56#ibcon#about to read 4, iclass 34, count 0 2006.168.07:41:59.56#ibcon#read 4, iclass 34, count 0 2006.168.07:41:59.56#ibcon#about to read 5, iclass 34, count 0 2006.168.07:41:59.56#ibcon#read 5, iclass 34, count 0 2006.168.07:41:59.56#ibcon#about to read 6, iclass 34, count 0 2006.168.07:41:59.56#ibcon#read 6, iclass 34, count 0 2006.168.07:41:59.56#ibcon#end of sib2, iclass 34, count 0 2006.168.07:41:59.56#ibcon#*mode == 0, iclass 34, count 0 2006.168.07:41:59.56#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.168.07:41:59.56#ibcon#[25=USB\r\n] 2006.168.07:41:59.56#ibcon#*before write, iclass 34, count 0 2006.168.07:41:59.56#ibcon#enter sib2, iclass 34, count 0 2006.168.07:41:59.56#ibcon#flushed, iclass 34, count 0 2006.168.07:41:59.56#ibcon#about to write, iclass 34, count 0 2006.168.07:41:59.56#ibcon#wrote, iclass 34, count 0 2006.168.07:41:59.56#ibcon#about to read 3, iclass 34, count 0 2006.168.07:41:59.59#ibcon#read 3, iclass 34, count 0 2006.168.07:41:59.59#ibcon#about to read 4, iclass 34, count 0 2006.168.07:41:59.59#ibcon#read 4, iclass 34, count 0 2006.168.07:41:59.59#ibcon#about to read 5, iclass 34, count 0 2006.168.07:41:59.59#ibcon#read 5, iclass 34, count 0 2006.168.07:41:59.59#ibcon#about to read 6, iclass 34, count 0 2006.168.07:41:59.59#ibcon#read 6, iclass 34, count 0 2006.168.07:41:59.59#ibcon#end of sib2, iclass 34, count 0 2006.168.07:41:59.59#ibcon#*after write, iclass 34, count 0 2006.168.07:41:59.59#ibcon#*before return 0, iclass 34, count 0 2006.168.07:41:59.59#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:41:59.59#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:41:59.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.168.07:41:59.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.168.07:41:59.59$vc4f8/valo=6,772.99 2006.168.07:41:59.59#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.168.07:41:59.59#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.168.07:41:59.59#ibcon#ireg 17 cls_cnt 0 2006.168.07:41:59.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:41:59.59#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:41:59.59#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:41:59.59#ibcon#enter wrdev, iclass 36, count 0 2006.168.07:41:59.59#ibcon#first serial, iclass 36, count 0 2006.168.07:41:59.59#ibcon#enter sib2, iclass 36, count 0 2006.168.07:41:59.59#ibcon#flushed, iclass 36, count 0 2006.168.07:41:59.59#ibcon#about to write, iclass 36, count 0 2006.168.07:41:59.59#ibcon#wrote, iclass 36, count 0 2006.168.07:41:59.59#ibcon#about to read 3, iclass 36, count 0 2006.168.07:41:59.61#ibcon#read 3, iclass 36, count 0 2006.168.07:41:59.61#ibcon#about to read 4, iclass 36, count 0 2006.168.07:41:59.61#ibcon#read 4, iclass 36, count 0 2006.168.07:41:59.61#ibcon#about to read 5, iclass 36, count 0 2006.168.07:41:59.61#ibcon#read 5, iclass 36, count 0 2006.168.07:41:59.61#ibcon#about to read 6, iclass 36, count 0 2006.168.07:41:59.61#ibcon#read 6, iclass 36, count 0 2006.168.07:41:59.61#ibcon#end of sib2, iclass 36, count 0 2006.168.07:41:59.61#ibcon#*mode == 0, iclass 36, count 0 2006.168.07:41:59.61#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.168.07:41:59.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.07:41:59.61#ibcon#*before write, iclass 36, count 0 2006.168.07:41:59.61#ibcon#enter sib2, iclass 36, count 0 2006.168.07:41:59.61#ibcon#flushed, iclass 36, count 0 2006.168.07:41:59.61#ibcon#about to write, iclass 36, count 0 2006.168.07:41:59.61#ibcon#wrote, iclass 36, count 0 2006.168.07:41:59.61#ibcon#about to read 3, iclass 36, count 0 2006.168.07:41:59.65#ibcon#read 3, iclass 36, count 0 2006.168.07:41:59.65#ibcon#about to read 4, iclass 36, count 0 2006.168.07:41:59.65#ibcon#read 4, iclass 36, count 0 2006.168.07:41:59.65#ibcon#about to read 5, iclass 36, count 0 2006.168.07:41:59.65#ibcon#read 5, iclass 36, count 0 2006.168.07:41:59.65#ibcon#about to read 6, iclass 36, count 0 2006.168.07:41:59.65#ibcon#read 6, iclass 36, count 0 2006.168.07:41:59.65#ibcon#end of sib2, iclass 36, count 0 2006.168.07:41:59.65#ibcon#*after write, iclass 36, count 0 2006.168.07:41:59.65#ibcon#*before return 0, iclass 36, count 0 2006.168.07:41:59.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:41:59.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:41:59.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.168.07:41:59.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.168.07:41:59.65$vc4f8/va=6,6 2006.168.07:41:59.65#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.168.07:41:59.65#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.168.07:41:59.65#ibcon#ireg 11 cls_cnt 2 2006.168.07:41:59.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.168.07:41:59.71#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.168.07:41:59.71#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.168.07:41:59.71#ibcon#enter wrdev, iclass 38, count 2 2006.168.07:41:59.71#ibcon#first serial, iclass 38, count 2 2006.168.07:41:59.71#ibcon#enter sib2, iclass 38, count 2 2006.168.07:41:59.71#ibcon#flushed, iclass 38, count 2 2006.168.07:41:59.71#ibcon#about to write, iclass 38, count 2 2006.168.07:41:59.71#ibcon#wrote, iclass 38, count 2 2006.168.07:41:59.71#ibcon#about to read 3, iclass 38, count 2 2006.168.07:41:59.73#ibcon#read 3, iclass 38, count 2 2006.168.07:41:59.73#ibcon#about to read 4, iclass 38, count 2 2006.168.07:41:59.73#ibcon#read 4, iclass 38, count 2 2006.168.07:41:59.73#ibcon#about to read 5, iclass 38, count 2 2006.168.07:41:59.73#ibcon#read 5, iclass 38, count 2 2006.168.07:41:59.73#ibcon#about to read 6, iclass 38, count 2 2006.168.07:41:59.73#ibcon#read 6, iclass 38, count 2 2006.168.07:41:59.73#ibcon#end of sib2, iclass 38, count 2 2006.168.07:41:59.73#ibcon#*mode == 0, iclass 38, count 2 2006.168.07:41:59.73#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.168.07:41:59.73#ibcon#[25=AT06-06\r\n] 2006.168.07:41:59.73#ibcon#*before write, iclass 38, count 2 2006.168.07:41:59.73#ibcon#enter sib2, iclass 38, count 2 2006.168.07:41:59.73#ibcon#flushed, iclass 38, count 2 2006.168.07:41:59.73#ibcon#about to write, iclass 38, count 2 2006.168.07:41:59.73#ibcon#wrote, iclass 38, count 2 2006.168.07:41:59.73#ibcon#about to read 3, iclass 38, count 2 2006.168.07:41:59.76#ibcon#read 3, iclass 38, count 2 2006.168.07:41:59.76#ibcon#about to read 4, iclass 38, count 2 2006.168.07:41:59.76#ibcon#read 4, iclass 38, count 2 2006.168.07:41:59.76#ibcon#about to read 5, iclass 38, count 2 2006.168.07:41:59.76#ibcon#read 5, iclass 38, count 2 2006.168.07:41:59.76#ibcon#about to read 6, iclass 38, count 2 2006.168.07:41:59.76#ibcon#read 6, iclass 38, count 2 2006.168.07:41:59.76#ibcon#end of sib2, iclass 38, count 2 2006.168.07:41:59.76#ibcon#*after write, iclass 38, count 2 2006.168.07:41:59.76#ibcon#*before return 0, iclass 38, count 2 2006.168.07:41:59.76#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.168.07:41:59.76#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.168.07:41:59.76#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.168.07:41:59.76#ibcon#ireg 7 cls_cnt 0 2006.168.07:41:59.76#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.168.07:41:59.88#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.168.07:41:59.88#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.168.07:41:59.88#ibcon#enter wrdev, iclass 38, count 0 2006.168.07:41:59.88#ibcon#first serial, iclass 38, count 0 2006.168.07:41:59.88#ibcon#enter sib2, iclass 38, count 0 2006.168.07:41:59.88#ibcon#flushed, iclass 38, count 0 2006.168.07:41:59.88#ibcon#about to write, iclass 38, count 0 2006.168.07:41:59.88#ibcon#wrote, iclass 38, count 0 2006.168.07:41:59.88#ibcon#about to read 3, iclass 38, count 0 2006.168.07:41:59.90#ibcon#read 3, iclass 38, count 0 2006.168.07:41:59.90#ibcon#about to read 4, iclass 38, count 0 2006.168.07:41:59.90#ibcon#read 4, iclass 38, count 0 2006.168.07:41:59.90#ibcon#about to read 5, iclass 38, count 0 2006.168.07:41:59.90#ibcon#read 5, iclass 38, count 0 2006.168.07:41:59.90#ibcon#about to read 6, iclass 38, count 0 2006.168.07:41:59.90#ibcon#read 6, iclass 38, count 0 2006.168.07:41:59.90#ibcon#end of sib2, iclass 38, count 0 2006.168.07:41:59.90#ibcon#*mode == 0, iclass 38, count 0 2006.168.07:41:59.90#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.168.07:41:59.90#ibcon#[25=USB\r\n] 2006.168.07:41:59.90#ibcon#*before write, iclass 38, count 0 2006.168.07:41:59.90#ibcon#enter sib2, iclass 38, count 0 2006.168.07:41:59.90#ibcon#flushed, iclass 38, count 0 2006.168.07:41:59.90#ibcon#about to write, iclass 38, count 0 2006.168.07:41:59.90#ibcon#wrote, iclass 38, count 0 2006.168.07:41:59.90#ibcon#about to read 3, iclass 38, count 0 2006.168.07:41:59.93#ibcon#read 3, iclass 38, count 0 2006.168.07:41:59.93#ibcon#about to read 4, iclass 38, count 0 2006.168.07:41:59.93#ibcon#read 4, iclass 38, count 0 2006.168.07:41:59.93#ibcon#about to read 5, iclass 38, count 0 2006.168.07:41:59.93#ibcon#read 5, iclass 38, count 0 2006.168.07:41:59.93#ibcon#about to read 6, iclass 38, count 0 2006.168.07:41:59.93#ibcon#read 6, iclass 38, count 0 2006.168.07:41:59.93#ibcon#end of sib2, iclass 38, count 0 2006.168.07:41:59.93#ibcon#*after write, iclass 38, count 0 2006.168.07:41:59.93#ibcon#*before return 0, iclass 38, count 0 2006.168.07:41:59.93#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.168.07:41:59.93#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.168.07:41:59.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.168.07:41:59.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.168.07:41:59.93$vc4f8/valo=7,832.99 2006.168.07:41:59.93#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.168.07:41:59.93#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.168.07:41:59.93#ibcon#ireg 17 cls_cnt 0 2006.168.07:41:59.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.168.07:41:59.93#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.168.07:41:59.93#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.168.07:41:59.93#ibcon#enter wrdev, iclass 40, count 0 2006.168.07:41:59.93#ibcon#first serial, iclass 40, count 0 2006.168.07:41:59.93#ibcon#enter sib2, iclass 40, count 0 2006.168.07:41:59.93#ibcon#flushed, iclass 40, count 0 2006.168.07:41:59.93#ibcon#about to write, iclass 40, count 0 2006.168.07:41:59.93#ibcon#wrote, iclass 40, count 0 2006.168.07:41:59.93#ibcon#about to read 3, iclass 40, count 0 2006.168.07:41:59.95#ibcon#read 3, iclass 40, count 0 2006.168.07:41:59.95#ibcon#about to read 4, iclass 40, count 0 2006.168.07:41:59.95#ibcon#read 4, iclass 40, count 0 2006.168.07:41:59.95#ibcon#about to read 5, iclass 40, count 0 2006.168.07:41:59.95#ibcon#read 5, iclass 40, count 0 2006.168.07:41:59.95#ibcon#about to read 6, iclass 40, count 0 2006.168.07:41:59.95#ibcon#read 6, iclass 40, count 0 2006.168.07:41:59.95#ibcon#end of sib2, iclass 40, count 0 2006.168.07:41:59.95#ibcon#*mode == 0, iclass 40, count 0 2006.168.07:41:59.95#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.168.07:41:59.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.07:41:59.95#ibcon#*before write, iclass 40, count 0 2006.168.07:41:59.95#ibcon#enter sib2, iclass 40, count 0 2006.168.07:41:59.95#ibcon#flushed, iclass 40, count 0 2006.168.07:41:59.95#ibcon#about to write, iclass 40, count 0 2006.168.07:41:59.95#ibcon#wrote, iclass 40, count 0 2006.168.07:41:59.95#ibcon#about to read 3, iclass 40, count 0 2006.168.07:41:59.99#ibcon#read 3, iclass 40, count 0 2006.168.07:41:59.99#ibcon#about to read 4, iclass 40, count 0 2006.168.07:41:59.99#ibcon#read 4, iclass 40, count 0 2006.168.07:41:59.99#ibcon#about to read 5, iclass 40, count 0 2006.168.07:41:59.99#ibcon#read 5, iclass 40, count 0 2006.168.07:41:59.99#ibcon#about to read 6, iclass 40, count 0 2006.168.07:41:59.99#ibcon#read 6, iclass 40, count 0 2006.168.07:41:59.99#ibcon#end of sib2, iclass 40, count 0 2006.168.07:41:59.99#ibcon#*after write, iclass 40, count 0 2006.168.07:41:59.99#ibcon#*before return 0, iclass 40, count 0 2006.168.07:41:59.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.168.07:41:59.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.168.07:41:59.99#ibcon#about to clear, iclass 40 cls_cnt 0 2006.168.07:41:59.99#ibcon#cleared, iclass 40 cls_cnt 0 2006.168.07:41:59.99$vc4f8/va=7,6 2006.168.07:41:59.99#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.168.07:41:59.99#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.168.07:41:59.99#ibcon#ireg 11 cls_cnt 2 2006.168.07:41:59.99#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.168.07:42:00.05#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.168.07:42:00.05#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.168.07:42:00.05#ibcon#enter wrdev, iclass 4, count 2 2006.168.07:42:00.05#ibcon#first serial, iclass 4, count 2 2006.168.07:42:00.05#ibcon#enter sib2, iclass 4, count 2 2006.168.07:42:00.05#ibcon#flushed, iclass 4, count 2 2006.168.07:42:00.05#ibcon#about to write, iclass 4, count 2 2006.168.07:42:00.05#ibcon#wrote, iclass 4, count 2 2006.168.07:42:00.05#ibcon#about to read 3, iclass 4, count 2 2006.168.07:42:00.07#ibcon#read 3, iclass 4, count 2 2006.168.07:42:00.07#ibcon#about to read 4, iclass 4, count 2 2006.168.07:42:00.07#ibcon#read 4, iclass 4, count 2 2006.168.07:42:00.07#ibcon#about to read 5, iclass 4, count 2 2006.168.07:42:00.07#ibcon#read 5, iclass 4, count 2 2006.168.07:42:00.07#ibcon#about to read 6, iclass 4, count 2 2006.168.07:42:00.07#ibcon#read 6, iclass 4, count 2 2006.168.07:42:00.07#ibcon#end of sib2, iclass 4, count 2 2006.168.07:42:00.07#ibcon#*mode == 0, iclass 4, count 2 2006.168.07:42:00.07#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.168.07:42:00.07#ibcon#[25=AT07-06\r\n] 2006.168.07:42:00.07#ibcon#*before write, iclass 4, count 2 2006.168.07:42:00.07#ibcon#enter sib2, iclass 4, count 2 2006.168.07:42:00.07#ibcon#flushed, iclass 4, count 2 2006.168.07:42:00.07#ibcon#about to write, iclass 4, count 2 2006.168.07:42:00.07#ibcon#wrote, iclass 4, count 2 2006.168.07:42:00.07#ibcon#about to read 3, iclass 4, count 2 2006.168.07:42:00.10#ibcon#read 3, iclass 4, count 2 2006.168.07:42:00.10#ibcon#about to read 4, iclass 4, count 2 2006.168.07:42:00.10#ibcon#read 4, iclass 4, count 2 2006.168.07:42:00.10#ibcon#about to read 5, iclass 4, count 2 2006.168.07:42:00.10#ibcon#read 5, iclass 4, count 2 2006.168.07:42:00.10#ibcon#about to read 6, iclass 4, count 2 2006.168.07:42:00.10#ibcon#read 6, iclass 4, count 2 2006.168.07:42:00.10#ibcon#end of sib2, iclass 4, count 2 2006.168.07:42:00.10#ibcon#*after write, iclass 4, count 2 2006.168.07:42:00.10#ibcon#*before return 0, iclass 4, count 2 2006.168.07:42:00.10#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.168.07:42:00.10#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.168.07:42:00.10#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.168.07:42:00.10#ibcon#ireg 7 cls_cnt 0 2006.168.07:42:00.10#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.168.07:42:00.22#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.168.07:42:00.22#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.168.07:42:00.22#ibcon#enter wrdev, iclass 4, count 0 2006.168.07:42:00.22#ibcon#first serial, iclass 4, count 0 2006.168.07:42:00.22#ibcon#enter sib2, iclass 4, count 0 2006.168.07:42:00.22#ibcon#flushed, iclass 4, count 0 2006.168.07:42:00.22#ibcon#about to write, iclass 4, count 0 2006.168.07:42:00.22#ibcon#wrote, iclass 4, count 0 2006.168.07:42:00.22#ibcon#about to read 3, iclass 4, count 0 2006.168.07:42:00.24#ibcon#read 3, iclass 4, count 0 2006.168.07:42:00.24#ibcon#about to read 4, iclass 4, count 0 2006.168.07:42:00.24#ibcon#read 4, iclass 4, count 0 2006.168.07:42:00.24#ibcon#about to read 5, iclass 4, count 0 2006.168.07:42:00.24#ibcon#read 5, iclass 4, count 0 2006.168.07:42:00.24#ibcon#about to read 6, iclass 4, count 0 2006.168.07:42:00.24#ibcon#read 6, iclass 4, count 0 2006.168.07:42:00.24#ibcon#end of sib2, iclass 4, count 0 2006.168.07:42:00.24#ibcon#*mode == 0, iclass 4, count 0 2006.168.07:42:00.24#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.168.07:42:00.24#ibcon#[25=USB\r\n] 2006.168.07:42:00.24#ibcon#*before write, iclass 4, count 0 2006.168.07:42:00.24#ibcon#enter sib2, iclass 4, count 0 2006.168.07:42:00.24#ibcon#flushed, iclass 4, count 0 2006.168.07:42:00.24#ibcon#about to write, iclass 4, count 0 2006.168.07:42:00.24#ibcon#wrote, iclass 4, count 0 2006.168.07:42:00.24#ibcon#about to read 3, iclass 4, count 0 2006.168.07:42:00.27#ibcon#read 3, iclass 4, count 0 2006.168.07:42:00.27#ibcon#about to read 4, iclass 4, count 0 2006.168.07:42:00.27#ibcon#read 4, iclass 4, count 0 2006.168.07:42:00.27#ibcon#about to read 5, iclass 4, count 0 2006.168.07:42:00.27#ibcon#read 5, iclass 4, count 0 2006.168.07:42:00.27#ibcon#about to read 6, iclass 4, count 0 2006.168.07:42:00.27#ibcon#read 6, iclass 4, count 0 2006.168.07:42:00.27#ibcon#end of sib2, iclass 4, count 0 2006.168.07:42:00.27#ibcon#*after write, iclass 4, count 0 2006.168.07:42:00.27#ibcon#*before return 0, iclass 4, count 0 2006.168.07:42:00.27#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.168.07:42:00.27#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.168.07:42:00.27#ibcon#about to clear, iclass 4 cls_cnt 0 2006.168.07:42:00.27#ibcon#cleared, iclass 4 cls_cnt 0 2006.168.07:42:00.27$vc4f8/valo=8,852.99 2006.168.07:42:00.27#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.168.07:42:00.27#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.168.07:42:00.27#ibcon#ireg 17 cls_cnt 0 2006.168.07:42:00.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.168.07:42:00.27#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.168.07:42:00.27#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.168.07:42:00.27#ibcon#enter wrdev, iclass 6, count 0 2006.168.07:42:00.27#ibcon#first serial, iclass 6, count 0 2006.168.07:42:00.27#ibcon#enter sib2, iclass 6, count 0 2006.168.07:42:00.27#ibcon#flushed, iclass 6, count 0 2006.168.07:42:00.27#ibcon#about to write, iclass 6, count 0 2006.168.07:42:00.27#ibcon#wrote, iclass 6, count 0 2006.168.07:42:00.27#ibcon#about to read 3, iclass 6, count 0 2006.168.07:42:00.29#ibcon#read 3, iclass 6, count 0 2006.168.07:42:00.29#ibcon#about to read 4, iclass 6, count 0 2006.168.07:42:00.29#ibcon#read 4, iclass 6, count 0 2006.168.07:42:00.29#ibcon#about to read 5, iclass 6, count 0 2006.168.07:42:00.29#ibcon#read 5, iclass 6, count 0 2006.168.07:42:00.29#ibcon#about to read 6, iclass 6, count 0 2006.168.07:42:00.29#ibcon#read 6, iclass 6, count 0 2006.168.07:42:00.29#ibcon#end of sib2, iclass 6, count 0 2006.168.07:42:00.29#ibcon#*mode == 0, iclass 6, count 0 2006.168.07:42:00.29#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.168.07:42:00.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.07:42:00.29#ibcon#*before write, iclass 6, count 0 2006.168.07:42:00.29#ibcon#enter sib2, iclass 6, count 0 2006.168.07:42:00.29#ibcon#flushed, iclass 6, count 0 2006.168.07:42:00.29#ibcon#about to write, iclass 6, count 0 2006.168.07:42:00.29#ibcon#wrote, iclass 6, count 0 2006.168.07:42:00.29#ibcon#about to read 3, iclass 6, count 0 2006.168.07:42:00.33#ibcon#read 3, iclass 6, count 0 2006.168.07:42:00.33#ibcon#about to read 4, iclass 6, count 0 2006.168.07:42:00.33#ibcon#read 4, iclass 6, count 0 2006.168.07:42:00.33#ibcon#about to read 5, iclass 6, count 0 2006.168.07:42:00.33#ibcon#read 5, iclass 6, count 0 2006.168.07:42:00.33#ibcon#about to read 6, iclass 6, count 0 2006.168.07:42:00.33#ibcon#read 6, iclass 6, count 0 2006.168.07:42:00.33#ibcon#end of sib2, iclass 6, count 0 2006.168.07:42:00.33#ibcon#*after write, iclass 6, count 0 2006.168.07:42:00.33#ibcon#*before return 0, iclass 6, count 0 2006.168.07:42:00.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.168.07:42:00.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.168.07:42:00.33#ibcon#about to clear, iclass 6 cls_cnt 0 2006.168.07:42:00.33#ibcon#cleared, iclass 6 cls_cnt 0 2006.168.07:42:00.33$vc4f8/va=8,7 2006.168.07:42:00.33#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.168.07:42:00.33#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.168.07:42:00.33#ibcon#ireg 11 cls_cnt 2 2006.168.07:42:00.33#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.168.07:42:00.39#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.168.07:42:00.39#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.168.07:42:00.39#ibcon#enter wrdev, iclass 10, count 2 2006.168.07:42:00.39#ibcon#first serial, iclass 10, count 2 2006.168.07:42:00.39#ibcon#enter sib2, iclass 10, count 2 2006.168.07:42:00.39#ibcon#flushed, iclass 10, count 2 2006.168.07:42:00.39#ibcon#about to write, iclass 10, count 2 2006.168.07:42:00.39#ibcon#wrote, iclass 10, count 2 2006.168.07:42:00.39#ibcon#about to read 3, iclass 10, count 2 2006.168.07:42:00.41#ibcon#read 3, iclass 10, count 2 2006.168.07:42:00.41#ibcon#about to read 4, iclass 10, count 2 2006.168.07:42:00.41#ibcon#read 4, iclass 10, count 2 2006.168.07:42:00.41#ibcon#about to read 5, iclass 10, count 2 2006.168.07:42:00.41#ibcon#read 5, iclass 10, count 2 2006.168.07:42:00.41#ibcon#about to read 6, iclass 10, count 2 2006.168.07:42:00.41#ibcon#read 6, iclass 10, count 2 2006.168.07:42:00.41#ibcon#end of sib2, iclass 10, count 2 2006.168.07:42:00.41#ibcon#*mode == 0, iclass 10, count 2 2006.168.07:42:00.41#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.168.07:42:00.41#ibcon#[25=AT08-07\r\n] 2006.168.07:42:00.41#ibcon#*before write, iclass 10, count 2 2006.168.07:42:00.41#ibcon#enter sib2, iclass 10, count 2 2006.168.07:42:00.41#ibcon#flushed, iclass 10, count 2 2006.168.07:42:00.41#ibcon#about to write, iclass 10, count 2 2006.168.07:42:00.41#ibcon#wrote, iclass 10, count 2 2006.168.07:42:00.41#ibcon#about to read 3, iclass 10, count 2 2006.168.07:42:00.44#ibcon#read 3, iclass 10, count 2 2006.168.07:42:00.44#ibcon#about to read 4, iclass 10, count 2 2006.168.07:42:00.44#ibcon#read 4, iclass 10, count 2 2006.168.07:42:00.44#ibcon#about to read 5, iclass 10, count 2 2006.168.07:42:00.44#ibcon#read 5, iclass 10, count 2 2006.168.07:42:00.44#ibcon#about to read 6, iclass 10, count 2 2006.168.07:42:00.44#ibcon#read 6, iclass 10, count 2 2006.168.07:42:00.44#ibcon#end of sib2, iclass 10, count 2 2006.168.07:42:00.44#ibcon#*after write, iclass 10, count 2 2006.168.07:42:00.44#ibcon#*before return 0, iclass 10, count 2 2006.168.07:42:00.44#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.168.07:42:00.44#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.168.07:42:00.44#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.168.07:42:00.44#ibcon#ireg 7 cls_cnt 0 2006.168.07:42:00.44#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.168.07:42:00.56#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.168.07:42:00.56#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.168.07:42:00.56#ibcon#enter wrdev, iclass 10, count 0 2006.168.07:42:00.56#ibcon#first serial, iclass 10, count 0 2006.168.07:42:00.56#ibcon#enter sib2, iclass 10, count 0 2006.168.07:42:00.56#ibcon#flushed, iclass 10, count 0 2006.168.07:42:00.56#ibcon#about to write, iclass 10, count 0 2006.168.07:42:00.56#ibcon#wrote, iclass 10, count 0 2006.168.07:42:00.56#ibcon#about to read 3, iclass 10, count 0 2006.168.07:42:00.58#ibcon#read 3, iclass 10, count 0 2006.168.07:42:00.58#ibcon#about to read 4, iclass 10, count 0 2006.168.07:42:00.58#ibcon#read 4, iclass 10, count 0 2006.168.07:42:00.58#ibcon#about to read 5, iclass 10, count 0 2006.168.07:42:00.58#ibcon#read 5, iclass 10, count 0 2006.168.07:42:00.58#ibcon#about to read 6, iclass 10, count 0 2006.168.07:42:00.58#ibcon#read 6, iclass 10, count 0 2006.168.07:42:00.58#ibcon#end of sib2, iclass 10, count 0 2006.168.07:42:00.58#ibcon#*mode == 0, iclass 10, count 0 2006.168.07:42:00.58#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.168.07:42:00.58#ibcon#[25=USB\r\n] 2006.168.07:42:00.58#ibcon#*before write, iclass 10, count 0 2006.168.07:42:00.58#ibcon#enter sib2, iclass 10, count 0 2006.168.07:42:00.58#ibcon#flushed, iclass 10, count 0 2006.168.07:42:00.58#ibcon#about to write, iclass 10, count 0 2006.168.07:42:00.58#ibcon#wrote, iclass 10, count 0 2006.168.07:42:00.58#ibcon#about to read 3, iclass 10, count 0 2006.168.07:42:00.61#ibcon#read 3, iclass 10, count 0 2006.168.07:42:00.61#ibcon#about to read 4, iclass 10, count 0 2006.168.07:42:00.61#ibcon#read 4, iclass 10, count 0 2006.168.07:42:00.61#ibcon#about to read 5, iclass 10, count 0 2006.168.07:42:00.61#ibcon#read 5, iclass 10, count 0 2006.168.07:42:00.61#ibcon#about to read 6, iclass 10, count 0 2006.168.07:42:00.61#ibcon#read 6, iclass 10, count 0 2006.168.07:42:00.61#ibcon#end of sib2, iclass 10, count 0 2006.168.07:42:00.61#ibcon#*after write, iclass 10, count 0 2006.168.07:42:00.61#ibcon#*before return 0, iclass 10, count 0 2006.168.07:42:00.61#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.168.07:42:00.61#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.168.07:42:00.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.168.07:42:00.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.168.07:42:00.61$vc4f8/vblo=1,632.99 2006.168.07:42:00.61#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.168.07:42:00.61#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.168.07:42:00.61#ibcon#ireg 17 cls_cnt 0 2006.168.07:42:00.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.168.07:42:00.61#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.168.07:42:00.61#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.168.07:42:00.61#ibcon#enter wrdev, iclass 12, count 0 2006.168.07:42:00.61#ibcon#first serial, iclass 12, count 0 2006.168.07:42:00.61#ibcon#enter sib2, iclass 12, count 0 2006.168.07:42:00.61#ibcon#flushed, iclass 12, count 0 2006.168.07:42:00.61#ibcon#about to write, iclass 12, count 0 2006.168.07:42:00.61#ibcon#wrote, iclass 12, count 0 2006.168.07:42:00.61#ibcon#about to read 3, iclass 12, count 0 2006.168.07:42:00.63#ibcon#read 3, iclass 12, count 0 2006.168.07:42:00.63#ibcon#about to read 4, iclass 12, count 0 2006.168.07:42:00.63#ibcon#read 4, iclass 12, count 0 2006.168.07:42:00.63#ibcon#about to read 5, iclass 12, count 0 2006.168.07:42:00.63#ibcon#read 5, iclass 12, count 0 2006.168.07:42:00.63#ibcon#about to read 6, iclass 12, count 0 2006.168.07:42:00.63#ibcon#read 6, iclass 12, count 0 2006.168.07:42:00.63#ibcon#end of sib2, iclass 12, count 0 2006.168.07:42:00.63#ibcon#*mode == 0, iclass 12, count 0 2006.168.07:42:00.63#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.168.07:42:00.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.07:42:00.63#ibcon#*before write, iclass 12, count 0 2006.168.07:42:00.63#ibcon#enter sib2, iclass 12, count 0 2006.168.07:42:00.63#ibcon#flushed, iclass 12, count 0 2006.168.07:42:00.63#ibcon#about to write, iclass 12, count 0 2006.168.07:42:00.63#ibcon#wrote, iclass 12, count 0 2006.168.07:42:00.63#ibcon#about to read 3, iclass 12, count 0 2006.168.07:42:00.67#ibcon#read 3, iclass 12, count 0 2006.168.07:42:00.67#ibcon#about to read 4, iclass 12, count 0 2006.168.07:42:00.67#ibcon#read 4, iclass 12, count 0 2006.168.07:42:00.67#ibcon#about to read 5, iclass 12, count 0 2006.168.07:42:00.67#ibcon#read 5, iclass 12, count 0 2006.168.07:42:00.67#ibcon#about to read 6, iclass 12, count 0 2006.168.07:42:00.67#ibcon#read 6, iclass 12, count 0 2006.168.07:42:00.67#ibcon#end of sib2, iclass 12, count 0 2006.168.07:42:00.67#ibcon#*after write, iclass 12, count 0 2006.168.07:42:00.67#ibcon#*before return 0, iclass 12, count 0 2006.168.07:42:00.67#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.168.07:42:00.67#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.168.07:42:00.67#ibcon#about to clear, iclass 12 cls_cnt 0 2006.168.07:42:00.67#ibcon#cleared, iclass 12 cls_cnt 0 2006.168.07:42:00.67$vc4f8/vb=1,4 2006.168.07:42:00.67#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.168.07:42:00.67#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.168.07:42:00.67#ibcon#ireg 11 cls_cnt 2 2006.168.07:42:00.67#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.168.07:42:00.67#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.168.07:42:00.67#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.168.07:42:00.67#ibcon#enter wrdev, iclass 14, count 2 2006.168.07:42:00.67#ibcon#first serial, iclass 14, count 2 2006.168.07:42:00.67#ibcon#enter sib2, iclass 14, count 2 2006.168.07:42:00.67#ibcon#flushed, iclass 14, count 2 2006.168.07:42:00.67#ibcon#about to write, iclass 14, count 2 2006.168.07:42:00.67#ibcon#wrote, iclass 14, count 2 2006.168.07:42:00.67#ibcon#about to read 3, iclass 14, count 2 2006.168.07:42:00.69#ibcon#read 3, iclass 14, count 2 2006.168.07:42:00.69#ibcon#about to read 4, iclass 14, count 2 2006.168.07:42:00.69#ibcon#read 4, iclass 14, count 2 2006.168.07:42:00.69#ibcon#about to read 5, iclass 14, count 2 2006.168.07:42:00.69#ibcon#read 5, iclass 14, count 2 2006.168.07:42:00.69#ibcon#about to read 6, iclass 14, count 2 2006.168.07:42:00.69#ibcon#read 6, iclass 14, count 2 2006.168.07:42:00.69#ibcon#end of sib2, iclass 14, count 2 2006.168.07:42:00.69#ibcon#*mode == 0, iclass 14, count 2 2006.168.07:42:00.69#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.168.07:42:00.69#ibcon#[27=AT01-04\r\n] 2006.168.07:42:00.69#ibcon#*before write, iclass 14, count 2 2006.168.07:42:00.69#ibcon#enter sib2, iclass 14, count 2 2006.168.07:42:00.69#ibcon#flushed, iclass 14, count 2 2006.168.07:42:00.69#ibcon#about to write, iclass 14, count 2 2006.168.07:42:00.69#ibcon#wrote, iclass 14, count 2 2006.168.07:42:00.69#ibcon#about to read 3, iclass 14, count 2 2006.168.07:42:00.72#ibcon#read 3, iclass 14, count 2 2006.168.07:42:00.72#ibcon#about to read 4, iclass 14, count 2 2006.168.07:42:00.72#ibcon#read 4, iclass 14, count 2 2006.168.07:42:00.72#ibcon#about to read 5, iclass 14, count 2 2006.168.07:42:00.72#ibcon#read 5, iclass 14, count 2 2006.168.07:42:00.72#ibcon#about to read 6, iclass 14, count 2 2006.168.07:42:00.72#ibcon#read 6, iclass 14, count 2 2006.168.07:42:00.72#ibcon#end of sib2, iclass 14, count 2 2006.168.07:42:00.72#ibcon#*after write, iclass 14, count 2 2006.168.07:42:00.72#ibcon#*before return 0, iclass 14, count 2 2006.168.07:42:00.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.168.07:42:00.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.168.07:42:00.72#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.168.07:42:00.72#ibcon#ireg 7 cls_cnt 0 2006.168.07:42:00.72#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.168.07:42:00.84#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.168.07:42:00.84#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.168.07:42:00.84#ibcon#enter wrdev, iclass 14, count 0 2006.168.07:42:00.84#ibcon#first serial, iclass 14, count 0 2006.168.07:42:00.84#ibcon#enter sib2, iclass 14, count 0 2006.168.07:42:00.84#ibcon#flushed, iclass 14, count 0 2006.168.07:42:00.84#ibcon#about to write, iclass 14, count 0 2006.168.07:42:00.84#ibcon#wrote, iclass 14, count 0 2006.168.07:42:00.84#ibcon#about to read 3, iclass 14, count 0 2006.168.07:42:00.86#ibcon#read 3, iclass 14, count 0 2006.168.07:42:00.86#ibcon#about to read 4, iclass 14, count 0 2006.168.07:42:00.86#ibcon#read 4, iclass 14, count 0 2006.168.07:42:00.86#ibcon#about to read 5, iclass 14, count 0 2006.168.07:42:00.86#ibcon#read 5, iclass 14, count 0 2006.168.07:42:00.86#ibcon#about to read 6, iclass 14, count 0 2006.168.07:42:00.86#ibcon#read 6, iclass 14, count 0 2006.168.07:42:00.86#ibcon#end of sib2, iclass 14, count 0 2006.168.07:42:00.86#ibcon#*mode == 0, iclass 14, count 0 2006.168.07:42:00.86#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.168.07:42:00.86#ibcon#[27=USB\r\n] 2006.168.07:42:00.86#ibcon#*before write, iclass 14, count 0 2006.168.07:42:00.86#ibcon#enter sib2, iclass 14, count 0 2006.168.07:42:00.86#ibcon#flushed, iclass 14, count 0 2006.168.07:42:00.86#ibcon#about to write, iclass 14, count 0 2006.168.07:42:00.86#ibcon#wrote, iclass 14, count 0 2006.168.07:42:00.86#ibcon#about to read 3, iclass 14, count 0 2006.168.07:42:00.89#ibcon#read 3, iclass 14, count 0 2006.168.07:42:00.89#ibcon#about to read 4, iclass 14, count 0 2006.168.07:42:00.89#ibcon#read 4, iclass 14, count 0 2006.168.07:42:00.89#ibcon#about to read 5, iclass 14, count 0 2006.168.07:42:00.89#ibcon#read 5, iclass 14, count 0 2006.168.07:42:00.89#ibcon#about to read 6, iclass 14, count 0 2006.168.07:42:00.89#ibcon#read 6, iclass 14, count 0 2006.168.07:42:00.89#ibcon#end of sib2, iclass 14, count 0 2006.168.07:42:00.89#ibcon#*after write, iclass 14, count 0 2006.168.07:42:00.89#ibcon#*before return 0, iclass 14, count 0 2006.168.07:42:00.89#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.168.07:42:00.89#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.168.07:42:00.89#ibcon#about to clear, iclass 14 cls_cnt 0 2006.168.07:42:00.89#ibcon#cleared, iclass 14 cls_cnt 0 2006.168.07:42:00.89$vc4f8/vblo=2,640.99 2006.168.07:42:00.89#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.168.07:42:00.89#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.168.07:42:00.89#ibcon#ireg 17 cls_cnt 0 2006.168.07:42:00.89#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:42:00.89#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:42:00.89#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:42:00.89#ibcon#enter wrdev, iclass 16, count 0 2006.168.07:42:00.89#ibcon#first serial, iclass 16, count 0 2006.168.07:42:00.89#ibcon#enter sib2, iclass 16, count 0 2006.168.07:42:00.89#ibcon#flushed, iclass 16, count 0 2006.168.07:42:00.89#ibcon#about to write, iclass 16, count 0 2006.168.07:42:00.89#ibcon#wrote, iclass 16, count 0 2006.168.07:42:00.89#ibcon#about to read 3, iclass 16, count 0 2006.168.07:42:00.91#ibcon#read 3, iclass 16, count 0 2006.168.07:42:00.91#ibcon#about to read 4, iclass 16, count 0 2006.168.07:42:00.91#ibcon#read 4, iclass 16, count 0 2006.168.07:42:00.91#ibcon#about to read 5, iclass 16, count 0 2006.168.07:42:00.91#ibcon#read 5, iclass 16, count 0 2006.168.07:42:00.91#ibcon#about to read 6, iclass 16, count 0 2006.168.07:42:00.91#ibcon#read 6, iclass 16, count 0 2006.168.07:42:00.91#ibcon#end of sib2, iclass 16, count 0 2006.168.07:42:00.91#ibcon#*mode == 0, iclass 16, count 0 2006.168.07:42:00.91#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.168.07:42:00.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.07:42:00.91#ibcon#*before write, iclass 16, count 0 2006.168.07:42:00.91#ibcon#enter sib2, iclass 16, count 0 2006.168.07:42:00.91#ibcon#flushed, iclass 16, count 0 2006.168.07:42:00.91#ibcon#about to write, iclass 16, count 0 2006.168.07:42:00.91#ibcon#wrote, iclass 16, count 0 2006.168.07:42:00.91#ibcon#about to read 3, iclass 16, count 0 2006.168.07:42:00.95#ibcon#read 3, iclass 16, count 0 2006.168.07:42:00.95#ibcon#about to read 4, iclass 16, count 0 2006.168.07:42:00.95#ibcon#read 4, iclass 16, count 0 2006.168.07:42:00.95#ibcon#about to read 5, iclass 16, count 0 2006.168.07:42:00.95#ibcon#read 5, iclass 16, count 0 2006.168.07:42:00.95#ibcon#about to read 6, iclass 16, count 0 2006.168.07:42:00.95#ibcon#read 6, iclass 16, count 0 2006.168.07:42:00.95#ibcon#end of sib2, iclass 16, count 0 2006.168.07:42:00.95#ibcon#*after write, iclass 16, count 0 2006.168.07:42:00.95#ibcon#*before return 0, iclass 16, count 0 2006.168.07:42:00.95#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:42:00.95#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:42:00.95#ibcon#about to clear, iclass 16 cls_cnt 0 2006.168.07:42:00.95#ibcon#cleared, iclass 16 cls_cnt 0 2006.168.07:42:00.95$vc4f8/vb=2,4 2006.168.07:42:00.95#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.168.07:42:00.95#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.168.07:42:00.95#ibcon#ireg 11 cls_cnt 2 2006.168.07:42:00.95#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:42:01.01#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:42:01.01#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:42:01.01#ibcon#enter wrdev, iclass 18, count 2 2006.168.07:42:01.01#ibcon#first serial, iclass 18, count 2 2006.168.07:42:01.01#ibcon#enter sib2, iclass 18, count 2 2006.168.07:42:01.01#ibcon#flushed, iclass 18, count 2 2006.168.07:42:01.01#ibcon#about to write, iclass 18, count 2 2006.168.07:42:01.01#ibcon#wrote, iclass 18, count 2 2006.168.07:42:01.01#ibcon#about to read 3, iclass 18, count 2 2006.168.07:42:01.03#ibcon#read 3, iclass 18, count 2 2006.168.07:42:01.03#ibcon#about to read 4, iclass 18, count 2 2006.168.07:42:01.03#ibcon#read 4, iclass 18, count 2 2006.168.07:42:01.03#ibcon#about to read 5, iclass 18, count 2 2006.168.07:42:01.03#ibcon#read 5, iclass 18, count 2 2006.168.07:42:01.03#ibcon#about to read 6, iclass 18, count 2 2006.168.07:42:01.03#ibcon#read 6, iclass 18, count 2 2006.168.07:42:01.03#ibcon#end of sib2, iclass 18, count 2 2006.168.07:42:01.03#ibcon#*mode == 0, iclass 18, count 2 2006.168.07:42:01.03#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.168.07:42:01.03#ibcon#[27=AT02-04\r\n] 2006.168.07:42:01.03#ibcon#*before write, iclass 18, count 2 2006.168.07:42:01.03#ibcon#enter sib2, iclass 18, count 2 2006.168.07:42:01.03#ibcon#flushed, iclass 18, count 2 2006.168.07:42:01.03#ibcon#about to write, iclass 18, count 2 2006.168.07:42:01.03#ibcon#wrote, iclass 18, count 2 2006.168.07:42:01.03#ibcon#about to read 3, iclass 18, count 2 2006.168.07:42:01.06#ibcon#read 3, iclass 18, count 2 2006.168.07:42:01.06#ibcon#about to read 4, iclass 18, count 2 2006.168.07:42:01.06#ibcon#read 4, iclass 18, count 2 2006.168.07:42:01.06#ibcon#about to read 5, iclass 18, count 2 2006.168.07:42:01.06#ibcon#read 5, iclass 18, count 2 2006.168.07:42:01.06#ibcon#about to read 6, iclass 18, count 2 2006.168.07:42:01.06#ibcon#read 6, iclass 18, count 2 2006.168.07:42:01.06#ibcon#end of sib2, iclass 18, count 2 2006.168.07:42:01.06#ibcon#*after write, iclass 18, count 2 2006.168.07:42:01.06#ibcon#*before return 0, iclass 18, count 2 2006.168.07:42:01.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:42:01.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:42:01.06#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.168.07:42:01.06#ibcon#ireg 7 cls_cnt 0 2006.168.07:42:01.06#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:42:01.18#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:42:01.18#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:42:01.18#ibcon#enter wrdev, iclass 18, count 0 2006.168.07:42:01.18#ibcon#first serial, iclass 18, count 0 2006.168.07:42:01.18#ibcon#enter sib2, iclass 18, count 0 2006.168.07:42:01.18#ibcon#flushed, iclass 18, count 0 2006.168.07:42:01.18#ibcon#about to write, iclass 18, count 0 2006.168.07:42:01.18#ibcon#wrote, iclass 18, count 0 2006.168.07:42:01.18#ibcon#about to read 3, iclass 18, count 0 2006.168.07:42:01.20#ibcon#read 3, iclass 18, count 0 2006.168.07:42:01.20#ibcon#about to read 4, iclass 18, count 0 2006.168.07:42:01.20#ibcon#read 4, iclass 18, count 0 2006.168.07:42:01.20#ibcon#about to read 5, iclass 18, count 0 2006.168.07:42:01.20#ibcon#read 5, iclass 18, count 0 2006.168.07:42:01.20#ibcon#about to read 6, iclass 18, count 0 2006.168.07:42:01.20#ibcon#read 6, iclass 18, count 0 2006.168.07:42:01.20#ibcon#end of sib2, iclass 18, count 0 2006.168.07:42:01.20#ibcon#*mode == 0, iclass 18, count 0 2006.168.07:42:01.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.07:42:01.20#ibcon#[27=USB\r\n] 2006.168.07:42:01.20#ibcon#*before write, iclass 18, count 0 2006.168.07:42:01.20#ibcon#enter sib2, iclass 18, count 0 2006.168.07:42:01.20#ibcon#flushed, iclass 18, count 0 2006.168.07:42:01.20#ibcon#about to write, iclass 18, count 0 2006.168.07:42:01.20#ibcon#wrote, iclass 18, count 0 2006.168.07:42:01.20#ibcon#about to read 3, iclass 18, count 0 2006.168.07:42:01.23#ibcon#read 3, iclass 18, count 0 2006.168.07:42:01.23#ibcon#about to read 4, iclass 18, count 0 2006.168.07:42:01.23#ibcon#read 4, iclass 18, count 0 2006.168.07:42:01.23#ibcon#about to read 5, iclass 18, count 0 2006.168.07:42:01.23#ibcon#read 5, iclass 18, count 0 2006.168.07:42:01.23#ibcon#about to read 6, iclass 18, count 0 2006.168.07:42:01.23#ibcon#read 6, iclass 18, count 0 2006.168.07:42:01.23#ibcon#end of sib2, iclass 18, count 0 2006.168.07:42:01.23#ibcon#*after write, iclass 18, count 0 2006.168.07:42:01.23#ibcon#*before return 0, iclass 18, count 0 2006.168.07:42:01.23#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:42:01.23#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:42:01.23#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.07:42:01.23#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.07:42:01.23$vc4f8/vblo=3,656.99 2006.168.07:42:01.23#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.168.07:42:01.23#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.168.07:42:01.23#ibcon#ireg 17 cls_cnt 0 2006.168.07:42:01.23#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:42:01.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:42:01.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:42:01.23#ibcon#enter wrdev, iclass 20, count 0 2006.168.07:42:01.23#ibcon#first serial, iclass 20, count 0 2006.168.07:42:01.23#ibcon#enter sib2, iclass 20, count 0 2006.168.07:42:01.23#ibcon#flushed, iclass 20, count 0 2006.168.07:42:01.23#ibcon#about to write, iclass 20, count 0 2006.168.07:42:01.23#ibcon#wrote, iclass 20, count 0 2006.168.07:42:01.23#ibcon#about to read 3, iclass 20, count 0 2006.168.07:42:01.25#ibcon#read 3, iclass 20, count 0 2006.168.07:42:01.25#ibcon#about to read 4, iclass 20, count 0 2006.168.07:42:01.25#ibcon#read 4, iclass 20, count 0 2006.168.07:42:01.25#ibcon#about to read 5, iclass 20, count 0 2006.168.07:42:01.25#ibcon#read 5, iclass 20, count 0 2006.168.07:42:01.25#ibcon#about to read 6, iclass 20, count 0 2006.168.07:42:01.25#ibcon#read 6, iclass 20, count 0 2006.168.07:42:01.25#ibcon#end of sib2, iclass 20, count 0 2006.168.07:42:01.25#ibcon#*mode == 0, iclass 20, count 0 2006.168.07:42:01.25#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.168.07:42:01.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.07:42:01.25#ibcon#*before write, iclass 20, count 0 2006.168.07:42:01.25#ibcon#enter sib2, iclass 20, count 0 2006.168.07:42:01.25#ibcon#flushed, iclass 20, count 0 2006.168.07:42:01.25#ibcon#about to write, iclass 20, count 0 2006.168.07:42:01.25#ibcon#wrote, iclass 20, count 0 2006.168.07:42:01.25#ibcon#about to read 3, iclass 20, count 0 2006.168.07:42:01.29#ibcon#read 3, iclass 20, count 0 2006.168.07:42:01.29#ibcon#about to read 4, iclass 20, count 0 2006.168.07:42:01.29#ibcon#read 4, iclass 20, count 0 2006.168.07:42:01.29#ibcon#about to read 5, iclass 20, count 0 2006.168.07:42:01.29#ibcon#read 5, iclass 20, count 0 2006.168.07:42:01.29#ibcon#about to read 6, iclass 20, count 0 2006.168.07:42:01.29#ibcon#read 6, iclass 20, count 0 2006.168.07:42:01.29#ibcon#end of sib2, iclass 20, count 0 2006.168.07:42:01.29#ibcon#*after write, iclass 20, count 0 2006.168.07:42:01.29#ibcon#*before return 0, iclass 20, count 0 2006.168.07:42:01.29#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:42:01.29#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:42:01.29#ibcon#about to clear, iclass 20 cls_cnt 0 2006.168.07:42:01.29#ibcon#cleared, iclass 20 cls_cnt 0 2006.168.07:42:01.29$vc4f8/vb=3,4 2006.168.07:42:01.29#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.168.07:42:01.29#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.168.07:42:01.29#ibcon#ireg 11 cls_cnt 2 2006.168.07:42:01.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:42:01.35#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:42:01.35#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:42:01.35#ibcon#enter wrdev, iclass 22, count 2 2006.168.07:42:01.35#ibcon#first serial, iclass 22, count 2 2006.168.07:42:01.35#ibcon#enter sib2, iclass 22, count 2 2006.168.07:42:01.35#ibcon#flushed, iclass 22, count 2 2006.168.07:42:01.35#ibcon#about to write, iclass 22, count 2 2006.168.07:42:01.35#ibcon#wrote, iclass 22, count 2 2006.168.07:42:01.35#ibcon#about to read 3, iclass 22, count 2 2006.168.07:42:01.37#ibcon#read 3, iclass 22, count 2 2006.168.07:42:01.37#ibcon#about to read 4, iclass 22, count 2 2006.168.07:42:01.37#ibcon#read 4, iclass 22, count 2 2006.168.07:42:01.37#ibcon#about to read 5, iclass 22, count 2 2006.168.07:42:01.37#ibcon#read 5, iclass 22, count 2 2006.168.07:42:01.37#ibcon#about to read 6, iclass 22, count 2 2006.168.07:42:01.37#ibcon#read 6, iclass 22, count 2 2006.168.07:42:01.37#ibcon#end of sib2, iclass 22, count 2 2006.168.07:42:01.37#ibcon#*mode == 0, iclass 22, count 2 2006.168.07:42:01.37#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.168.07:42:01.37#ibcon#[27=AT03-04\r\n] 2006.168.07:42:01.37#ibcon#*before write, iclass 22, count 2 2006.168.07:42:01.37#ibcon#enter sib2, iclass 22, count 2 2006.168.07:42:01.37#ibcon#flushed, iclass 22, count 2 2006.168.07:42:01.37#ibcon#about to write, iclass 22, count 2 2006.168.07:42:01.37#ibcon#wrote, iclass 22, count 2 2006.168.07:42:01.37#ibcon#about to read 3, iclass 22, count 2 2006.168.07:42:01.40#ibcon#read 3, iclass 22, count 2 2006.168.07:42:01.40#ibcon#about to read 4, iclass 22, count 2 2006.168.07:42:01.40#ibcon#read 4, iclass 22, count 2 2006.168.07:42:01.40#ibcon#about to read 5, iclass 22, count 2 2006.168.07:42:01.40#ibcon#read 5, iclass 22, count 2 2006.168.07:42:01.40#ibcon#about to read 6, iclass 22, count 2 2006.168.07:42:01.40#ibcon#read 6, iclass 22, count 2 2006.168.07:42:01.40#ibcon#end of sib2, iclass 22, count 2 2006.168.07:42:01.40#ibcon#*after write, iclass 22, count 2 2006.168.07:42:01.40#ibcon#*before return 0, iclass 22, count 2 2006.168.07:42:01.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:42:01.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:42:01.40#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.168.07:42:01.40#ibcon#ireg 7 cls_cnt 0 2006.168.07:42:01.40#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:42:01.52#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:42:01.52#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:42:01.52#ibcon#enter wrdev, iclass 22, count 0 2006.168.07:42:01.52#ibcon#first serial, iclass 22, count 0 2006.168.07:42:01.52#ibcon#enter sib2, iclass 22, count 0 2006.168.07:42:01.52#ibcon#flushed, iclass 22, count 0 2006.168.07:42:01.52#ibcon#about to write, iclass 22, count 0 2006.168.07:42:01.52#ibcon#wrote, iclass 22, count 0 2006.168.07:42:01.52#ibcon#about to read 3, iclass 22, count 0 2006.168.07:42:01.54#ibcon#read 3, iclass 22, count 0 2006.168.07:42:01.54#ibcon#about to read 4, iclass 22, count 0 2006.168.07:42:01.54#ibcon#read 4, iclass 22, count 0 2006.168.07:42:01.54#ibcon#about to read 5, iclass 22, count 0 2006.168.07:42:01.54#ibcon#read 5, iclass 22, count 0 2006.168.07:42:01.54#ibcon#about to read 6, iclass 22, count 0 2006.168.07:42:01.54#ibcon#read 6, iclass 22, count 0 2006.168.07:42:01.54#ibcon#end of sib2, iclass 22, count 0 2006.168.07:42:01.54#ibcon#*mode == 0, iclass 22, count 0 2006.168.07:42:01.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.168.07:42:01.54#ibcon#[27=USB\r\n] 2006.168.07:42:01.54#ibcon#*before write, iclass 22, count 0 2006.168.07:42:01.54#ibcon#enter sib2, iclass 22, count 0 2006.168.07:42:01.54#ibcon#flushed, iclass 22, count 0 2006.168.07:42:01.54#ibcon#about to write, iclass 22, count 0 2006.168.07:42:01.54#ibcon#wrote, iclass 22, count 0 2006.168.07:42:01.54#ibcon#about to read 3, iclass 22, count 0 2006.168.07:42:01.57#ibcon#read 3, iclass 22, count 0 2006.168.07:42:01.57#ibcon#about to read 4, iclass 22, count 0 2006.168.07:42:01.57#ibcon#read 4, iclass 22, count 0 2006.168.07:42:01.57#ibcon#about to read 5, iclass 22, count 0 2006.168.07:42:01.57#ibcon#read 5, iclass 22, count 0 2006.168.07:42:01.57#ibcon#about to read 6, iclass 22, count 0 2006.168.07:42:01.57#ibcon#read 6, iclass 22, count 0 2006.168.07:42:01.57#ibcon#end of sib2, iclass 22, count 0 2006.168.07:42:01.57#ibcon#*after write, iclass 22, count 0 2006.168.07:42:01.57#ibcon#*before return 0, iclass 22, count 0 2006.168.07:42:01.57#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:42:01.57#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:42:01.57#ibcon#about to clear, iclass 22 cls_cnt 0 2006.168.07:42:01.57#ibcon#cleared, iclass 22 cls_cnt 0 2006.168.07:42:01.57$vc4f8/vblo=4,712.99 2006.168.07:42:01.57#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.168.07:42:01.57#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.168.07:42:01.57#ibcon#ireg 17 cls_cnt 0 2006.168.07:42:01.57#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.168.07:42:01.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.168.07:42:01.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.168.07:42:01.57#ibcon#enter wrdev, iclass 24, count 0 2006.168.07:42:01.57#ibcon#first serial, iclass 24, count 0 2006.168.07:42:01.57#ibcon#enter sib2, iclass 24, count 0 2006.168.07:42:01.57#ibcon#flushed, iclass 24, count 0 2006.168.07:42:01.57#ibcon#about to write, iclass 24, count 0 2006.168.07:42:01.57#ibcon#wrote, iclass 24, count 0 2006.168.07:42:01.57#ibcon#about to read 3, iclass 24, count 0 2006.168.07:42:01.59#ibcon#read 3, iclass 24, count 0 2006.168.07:42:01.59#ibcon#about to read 4, iclass 24, count 0 2006.168.07:42:01.59#ibcon#read 4, iclass 24, count 0 2006.168.07:42:01.59#ibcon#about to read 5, iclass 24, count 0 2006.168.07:42:01.59#ibcon#read 5, iclass 24, count 0 2006.168.07:42:01.59#ibcon#about to read 6, iclass 24, count 0 2006.168.07:42:01.59#ibcon#read 6, iclass 24, count 0 2006.168.07:42:01.59#ibcon#end of sib2, iclass 24, count 0 2006.168.07:42:01.59#ibcon#*mode == 0, iclass 24, count 0 2006.168.07:42:01.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.168.07:42:01.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.07:42:01.59#ibcon#*before write, iclass 24, count 0 2006.168.07:42:01.59#ibcon#enter sib2, iclass 24, count 0 2006.168.07:42:01.59#ibcon#flushed, iclass 24, count 0 2006.168.07:42:01.59#ibcon#about to write, iclass 24, count 0 2006.168.07:42:01.59#ibcon#wrote, iclass 24, count 0 2006.168.07:42:01.59#ibcon#about to read 3, iclass 24, count 0 2006.168.07:42:01.63#ibcon#read 3, iclass 24, count 0 2006.168.07:42:01.63#ibcon#about to read 4, iclass 24, count 0 2006.168.07:42:01.63#ibcon#read 4, iclass 24, count 0 2006.168.07:42:01.63#ibcon#about to read 5, iclass 24, count 0 2006.168.07:42:01.63#ibcon#read 5, iclass 24, count 0 2006.168.07:42:01.63#ibcon#about to read 6, iclass 24, count 0 2006.168.07:42:01.63#ibcon#read 6, iclass 24, count 0 2006.168.07:42:01.63#ibcon#end of sib2, iclass 24, count 0 2006.168.07:42:01.63#ibcon#*after write, iclass 24, count 0 2006.168.07:42:01.63#ibcon#*before return 0, iclass 24, count 0 2006.168.07:42:01.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.168.07:42:01.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.168.07:42:01.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.168.07:42:01.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.168.07:42:01.63$vc4f8/vb=4,4 2006.168.07:42:01.63#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.168.07:42:01.63#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.168.07:42:01.63#ibcon#ireg 11 cls_cnt 2 2006.168.07:42:01.63#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.168.07:42:01.69#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.168.07:42:01.69#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.168.07:42:01.69#ibcon#enter wrdev, iclass 26, count 2 2006.168.07:42:01.69#ibcon#first serial, iclass 26, count 2 2006.168.07:42:01.69#ibcon#enter sib2, iclass 26, count 2 2006.168.07:42:01.69#ibcon#flushed, iclass 26, count 2 2006.168.07:42:01.69#ibcon#about to write, iclass 26, count 2 2006.168.07:42:01.69#ibcon#wrote, iclass 26, count 2 2006.168.07:42:01.69#ibcon#about to read 3, iclass 26, count 2 2006.168.07:42:01.71#ibcon#read 3, iclass 26, count 2 2006.168.07:42:01.71#ibcon#about to read 4, iclass 26, count 2 2006.168.07:42:01.71#ibcon#read 4, iclass 26, count 2 2006.168.07:42:01.71#ibcon#about to read 5, iclass 26, count 2 2006.168.07:42:01.71#ibcon#read 5, iclass 26, count 2 2006.168.07:42:01.71#ibcon#about to read 6, iclass 26, count 2 2006.168.07:42:01.71#ibcon#read 6, iclass 26, count 2 2006.168.07:42:01.71#ibcon#end of sib2, iclass 26, count 2 2006.168.07:42:01.71#ibcon#*mode == 0, iclass 26, count 2 2006.168.07:42:01.71#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.168.07:42:01.71#ibcon#[27=AT04-04\r\n] 2006.168.07:42:01.71#ibcon#*before write, iclass 26, count 2 2006.168.07:42:01.71#ibcon#enter sib2, iclass 26, count 2 2006.168.07:42:01.71#ibcon#flushed, iclass 26, count 2 2006.168.07:42:01.71#ibcon#about to write, iclass 26, count 2 2006.168.07:42:01.71#ibcon#wrote, iclass 26, count 2 2006.168.07:42:01.71#ibcon#about to read 3, iclass 26, count 2 2006.168.07:42:01.74#ibcon#read 3, iclass 26, count 2 2006.168.07:42:01.74#ibcon#about to read 4, iclass 26, count 2 2006.168.07:42:01.74#ibcon#read 4, iclass 26, count 2 2006.168.07:42:01.74#ibcon#about to read 5, iclass 26, count 2 2006.168.07:42:01.74#ibcon#read 5, iclass 26, count 2 2006.168.07:42:01.74#ibcon#about to read 6, iclass 26, count 2 2006.168.07:42:01.74#ibcon#read 6, iclass 26, count 2 2006.168.07:42:01.74#ibcon#end of sib2, iclass 26, count 2 2006.168.07:42:01.74#ibcon#*after write, iclass 26, count 2 2006.168.07:42:01.74#ibcon#*before return 0, iclass 26, count 2 2006.168.07:42:01.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.168.07:42:01.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.168.07:42:01.74#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.168.07:42:01.74#ibcon#ireg 7 cls_cnt 0 2006.168.07:42:01.74#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.168.07:42:01.86#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.168.07:42:01.86#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.168.07:42:01.86#ibcon#enter wrdev, iclass 26, count 0 2006.168.07:42:01.86#ibcon#first serial, iclass 26, count 0 2006.168.07:42:01.86#ibcon#enter sib2, iclass 26, count 0 2006.168.07:42:01.86#ibcon#flushed, iclass 26, count 0 2006.168.07:42:01.86#ibcon#about to write, iclass 26, count 0 2006.168.07:42:01.86#ibcon#wrote, iclass 26, count 0 2006.168.07:42:01.86#ibcon#about to read 3, iclass 26, count 0 2006.168.07:42:01.88#ibcon#read 3, iclass 26, count 0 2006.168.07:42:01.88#ibcon#about to read 4, iclass 26, count 0 2006.168.07:42:01.88#ibcon#read 4, iclass 26, count 0 2006.168.07:42:01.88#ibcon#about to read 5, iclass 26, count 0 2006.168.07:42:01.88#ibcon#read 5, iclass 26, count 0 2006.168.07:42:01.88#ibcon#about to read 6, iclass 26, count 0 2006.168.07:42:01.88#ibcon#read 6, iclass 26, count 0 2006.168.07:42:01.88#ibcon#end of sib2, iclass 26, count 0 2006.168.07:42:01.88#ibcon#*mode == 0, iclass 26, count 0 2006.168.07:42:01.88#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.168.07:42:01.88#ibcon#[27=USB\r\n] 2006.168.07:42:01.88#ibcon#*before write, iclass 26, count 0 2006.168.07:42:01.88#ibcon#enter sib2, iclass 26, count 0 2006.168.07:42:01.88#ibcon#flushed, iclass 26, count 0 2006.168.07:42:01.88#ibcon#about to write, iclass 26, count 0 2006.168.07:42:01.88#ibcon#wrote, iclass 26, count 0 2006.168.07:42:01.88#ibcon#about to read 3, iclass 26, count 0 2006.168.07:42:01.91#ibcon#read 3, iclass 26, count 0 2006.168.07:42:01.91#ibcon#about to read 4, iclass 26, count 0 2006.168.07:42:01.91#ibcon#read 4, iclass 26, count 0 2006.168.07:42:01.91#ibcon#about to read 5, iclass 26, count 0 2006.168.07:42:01.91#ibcon#read 5, iclass 26, count 0 2006.168.07:42:01.91#ibcon#about to read 6, iclass 26, count 0 2006.168.07:42:01.91#ibcon#read 6, iclass 26, count 0 2006.168.07:42:01.91#ibcon#end of sib2, iclass 26, count 0 2006.168.07:42:01.91#ibcon#*after write, iclass 26, count 0 2006.168.07:42:01.91#ibcon#*before return 0, iclass 26, count 0 2006.168.07:42:01.91#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.168.07:42:01.91#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.168.07:42:01.91#ibcon#about to clear, iclass 26 cls_cnt 0 2006.168.07:42:01.91#ibcon#cleared, iclass 26 cls_cnt 0 2006.168.07:42:01.91$vc4f8/vblo=5,744.99 2006.168.07:42:01.91#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.168.07:42:01.91#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.168.07:42:01.91#ibcon#ireg 17 cls_cnt 0 2006.168.07:42:01.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:42:01.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:42:01.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:42:01.91#ibcon#enter wrdev, iclass 28, count 0 2006.168.07:42:01.91#ibcon#first serial, iclass 28, count 0 2006.168.07:42:01.91#ibcon#enter sib2, iclass 28, count 0 2006.168.07:42:01.91#ibcon#flushed, iclass 28, count 0 2006.168.07:42:01.91#ibcon#about to write, iclass 28, count 0 2006.168.07:42:01.91#ibcon#wrote, iclass 28, count 0 2006.168.07:42:01.91#ibcon#about to read 3, iclass 28, count 0 2006.168.07:42:01.93#ibcon#read 3, iclass 28, count 0 2006.168.07:42:01.93#ibcon#about to read 4, iclass 28, count 0 2006.168.07:42:01.93#ibcon#read 4, iclass 28, count 0 2006.168.07:42:01.93#ibcon#about to read 5, iclass 28, count 0 2006.168.07:42:01.93#ibcon#read 5, iclass 28, count 0 2006.168.07:42:01.93#ibcon#about to read 6, iclass 28, count 0 2006.168.07:42:01.93#ibcon#read 6, iclass 28, count 0 2006.168.07:42:01.93#ibcon#end of sib2, iclass 28, count 0 2006.168.07:42:01.93#ibcon#*mode == 0, iclass 28, count 0 2006.168.07:42:01.93#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.168.07:42:01.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.07:42:01.93#ibcon#*before write, iclass 28, count 0 2006.168.07:42:01.93#ibcon#enter sib2, iclass 28, count 0 2006.168.07:42:01.93#ibcon#flushed, iclass 28, count 0 2006.168.07:42:01.93#ibcon#about to write, iclass 28, count 0 2006.168.07:42:01.93#ibcon#wrote, iclass 28, count 0 2006.168.07:42:01.93#ibcon#about to read 3, iclass 28, count 0 2006.168.07:42:01.97#ibcon#read 3, iclass 28, count 0 2006.168.07:42:01.97#ibcon#about to read 4, iclass 28, count 0 2006.168.07:42:01.97#ibcon#read 4, iclass 28, count 0 2006.168.07:42:01.97#ibcon#about to read 5, iclass 28, count 0 2006.168.07:42:01.97#ibcon#read 5, iclass 28, count 0 2006.168.07:42:01.97#ibcon#about to read 6, iclass 28, count 0 2006.168.07:42:01.97#ibcon#read 6, iclass 28, count 0 2006.168.07:42:01.97#ibcon#end of sib2, iclass 28, count 0 2006.168.07:42:01.97#ibcon#*after write, iclass 28, count 0 2006.168.07:42:01.97#ibcon#*before return 0, iclass 28, count 0 2006.168.07:42:01.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:42:01.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:42:01.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.168.07:42:01.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.168.07:42:01.97$vc4f8/vb=5,4 2006.168.07:42:01.97#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.168.07:42:01.97#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.168.07:42:01.97#ibcon#ireg 11 cls_cnt 2 2006.168.07:42:01.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:42:02.03#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:42:02.03#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:42:02.03#ibcon#enter wrdev, iclass 30, count 2 2006.168.07:42:02.03#ibcon#first serial, iclass 30, count 2 2006.168.07:42:02.03#ibcon#enter sib2, iclass 30, count 2 2006.168.07:42:02.03#ibcon#flushed, iclass 30, count 2 2006.168.07:42:02.03#ibcon#about to write, iclass 30, count 2 2006.168.07:42:02.03#ibcon#wrote, iclass 30, count 2 2006.168.07:42:02.03#ibcon#about to read 3, iclass 30, count 2 2006.168.07:42:02.05#ibcon#read 3, iclass 30, count 2 2006.168.07:42:02.05#ibcon#about to read 4, iclass 30, count 2 2006.168.07:42:02.05#ibcon#read 4, iclass 30, count 2 2006.168.07:42:02.05#ibcon#about to read 5, iclass 30, count 2 2006.168.07:42:02.05#ibcon#read 5, iclass 30, count 2 2006.168.07:42:02.05#ibcon#about to read 6, iclass 30, count 2 2006.168.07:42:02.05#ibcon#read 6, iclass 30, count 2 2006.168.07:42:02.05#ibcon#end of sib2, iclass 30, count 2 2006.168.07:42:02.05#ibcon#*mode == 0, iclass 30, count 2 2006.168.07:42:02.05#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.168.07:42:02.05#ibcon#[27=AT05-04\r\n] 2006.168.07:42:02.05#ibcon#*before write, iclass 30, count 2 2006.168.07:42:02.05#ibcon#enter sib2, iclass 30, count 2 2006.168.07:42:02.05#ibcon#flushed, iclass 30, count 2 2006.168.07:42:02.05#ibcon#about to write, iclass 30, count 2 2006.168.07:42:02.05#ibcon#wrote, iclass 30, count 2 2006.168.07:42:02.05#ibcon#about to read 3, iclass 30, count 2 2006.168.07:42:02.08#ibcon#read 3, iclass 30, count 2 2006.168.07:42:02.08#ibcon#about to read 4, iclass 30, count 2 2006.168.07:42:02.08#ibcon#read 4, iclass 30, count 2 2006.168.07:42:02.08#ibcon#about to read 5, iclass 30, count 2 2006.168.07:42:02.08#ibcon#read 5, iclass 30, count 2 2006.168.07:42:02.08#ibcon#about to read 6, iclass 30, count 2 2006.168.07:42:02.08#ibcon#read 6, iclass 30, count 2 2006.168.07:42:02.08#ibcon#end of sib2, iclass 30, count 2 2006.168.07:42:02.08#ibcon#*after write, iclass 30, count 2 2006.168.07:42:02.08#ibcon#*before return 0, iclass 30, count 2 2006.168.07:42:02.08#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:42:02.08#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:42:02.08#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.168.07:42:02.08#ibcon#ireg 7 cls_cnt 0 2006.168.07:42:02.08#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:42:02.20#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:42:02.20#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:42:02.20#ibcon#enter wrdev, iclass 30, count 0 2006.168.07:42:02.20#ibcon#first serial, iclass 30, count 0 2006.168.07:42:02.20#ibcon#enter sib2, iclass 30, count 0 2006.168.07:42:02.20#ibcon#flushed, iclass 30, count 0 2006.168.07:42:02.20#ibcon#about to write, iclass 30, count 0 2006.168.07:42:02.20#ibcon#wrote, iclass 30, count 0 2006.168.07:42:02.20#ibcon#about to read 3, iclass 30, count 0 2006.168.07:42:02.22#ibcon#read 3, iclass 30, count 0 2006.168.07:42:02.22#ibcon#about to read 4, iclass 30, count 0 2006.168.07:42:02.22#ibcon#read 4, iclass 30, count 0 2006.168.07:42:02.22#ibcon#about to read 5, iclass 30, count 0 2006.168.07:42:02.22#ibcon#read 5, iclass 30, count 0 2006.168.07:42:02.22#ibcon#about to read 6, iclass 30, count 0 2006.168.07:42:02.22#ibcon#read 6, iclass 30, count 0 2006.168.07:42:02.22#ibcon#end of sib2, iclass 30, count 0 2006.168.07:42:02.22#ibcon#*mode == 0, iclass 30, count 0 2006.168.07:42:02.22#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.168.07:42:02.22#ibcon#[27=USB\r\n] 2006.168.07:42:02.22#ibcon#*before write, iclass 30, count 0 2006.168.07:42:02.22#ibcon#enter sib2, iclass 30, count 0 2006.168.07:42:02.22#ibcon#flushed, iclass 30, count 0 2006.168.07:42:02.22#ibcon#about to write, iclass 30, count 0 2006.168.07:42:02.22#ibcon#wrote, iclass 30, count 0 2006.168.07:42:02.22#ibcon#about to read 3, iclass 30, count 0 2006.168.07:42:02.25#ibcon#read 3, iclass 30, count 0 2006.168.07:42:02.25#ibcon#about to read 4, iclass 30, count 0 2006.168.07:42:02.25#ibcon#read 4, iclass 30, count 0 2006.168.07:42:02.25#ibcon#about to read 5, iclass 30, count 0 2006.168.07:42:02.25#ibcon#read 5, iclass 30, count 0 2006.168.07:42:02.25#ibcon#about to read 6, iclass 30, count 0 2006.168.07:42:02.25#ibcon#read 6, iclass 30, count 0 2006.168.07:42:02.25#ibcon#end of sib2, iclass 30, count 0 2006.168.07:42:02.25#ibcon#*after write, iclass 30, count 0 2006.168.07:42:02.25#ibcon#*before return 0, iclass 30, count 0 2006.168.07:42:02.25#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:42:02.25#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:42:02.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.168.07:42:02.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.168.07:42:02.25$vc4f8/vblo=6,752.99 2006.168.07:42:02.25#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.168.07:42:02.25#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.168.07:42:02.25#ibcon#ireg 17 cls_cnt 0 2006.168.07:42:02.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:42:02.25#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:42:02.25#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:42:02.25#ibcon#enter wrdev, iclass 32, count 0 2006.168.07:42:02.25#ibcon#first serial, iclass 32, count 0 2006.168.07:42:02.25#ibcon#enter sib2, iclass 32, count 0 2006.168.07:42:02.25#ibcon#flushed, iclass 32, count 0 2006.168.07:42:02.25#ibcon#about to write, iclass 32, count 0 2006.168.07:42:02.25#ibcon#wrote, iclass 32, count 0 2006.168.07:42:02.25#ibcon#about to read 3, iclass 32, count 0 2006.168.07:42:02.27#ibcon#read 3, iclass 32, count 0 2006.168.07:42:02.27#ibcon#about to read 4, iclass 32, count 0 2006.168.07:42:02.27#ibcon#read 4, iclass 32, count 0 2006.168.07:42:02.27#ibcon#about to read 5, iclass 32, count 0 2006.168.07:42:02.27#ibcon#read 5, iclass 32, count 0 2006.168.07:42:02.27#ibcon#about to read 6, iclass 32, count 0 2006.168.07:42:02.27#ibcon#read 6, iclass 32, count 0 2006.168.07:42:02.27#ibcon#end of sib2, iclass 32, count 0 2006.168.07:42:02.27#ibcon#*mode == 0, iclass 32, count 0 2006.168.07:42:02.27#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.168.07:42:02.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.07:42:02.27#ibcon#*before write, iclass 32, count 0 2006.168.07:42:02.27#ibcon#enter sib2, iclass 32, count 0 2006.168.07:42:02.27#ibcon#flushed, iclass 32, count 0 2006.168.07:42:02.27#ibcon#about to write, iclass 32, count 0 2006.168.07:42:02.27#ibcon#wrote, iclass 32, count 0 2006.168.07:42:02.27#ibcon#about to read 3, iclass 32, count 0 2006.168.07:42:02.31#ibcon#read 3, iclass 32, count 0 2006.168.07:42:02.31#ibcon#about to read 4, iclass 32, count 0 2006.168.07:42:02.31#ibcon#read 4, iclass 32, count 0 2006.168.07:42:02.31#ibcon#about to read 5, iclass 32, count 0 2006.168.07:42:02.31#ibcon#read 5, iclass 32, count 0 2006.168.07:42:02.31#ibcon#about to read 6, iclass 32, count 0 2006.168.07:42:02.31#ibcon#read 6, iclass 32, count 0 2006.168.07:42:02.31#ibcon#end of sib2, iclass 32, count 0 2006.168.07:42:02.31#ibcon#*after write, iclass 32, count 0 2006.168.07:42:02.31#ibcon#*before return 0, iclass 32, count 0 2006.168.07:42:02.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:42:02.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:42:02.31#ibcon#about to clear, iclass 32 cls_cnt 0 2006.168.07:42:02.31#ibcon#cleared, iclass 32 cls_cnt 0 2006.168.07:42:02.31$vc4f8/vb=6,4 2006.168.07:42:02.31#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.168.07:42:02.31#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.168.07:42:02.31#ibcon#ireg 11 cls_cnt 2 2006.168.07:42:02.31#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:42:02.37#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:42:02.37#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:42:02.37#ibcon#enter wrdev, iclass 34, count 2 2006.168.07:42:02.37#ibcon#first serial, iclass 34, count 2 2006.168.07:42:02.37#ibcon#enter sib2, iclass 34, count 2 2006.168.07:42:02.37#ibcon#flushed, iclass 34, count 2 2006.168.07:42:02.37#ibcon#about to write, iclass 34, count 2 2006.168.07:42:02.37#ibcon#wrote, iclass 34, count 2 2006.168.07:42:02.37#ibcon#about to read 3, iclass 34, count 2 2006.168.07:42:02.39#ibcon#read 3, iclass 34, count 2 2006.168.07:42:02.39#ibcon#about to read 4, iclass 34, count 2 2006.168.07:42:02.39#ibcon#read 4, iclass 34, count 2 2006.168.07:42:02.39#ibcon#about to read 5, iclass 34, count 2 2006.168.07:42:02.39#ibcon#read 5, iclass 34, count 2 2006.168.07:42:02.39#ibcon#about to read 6, iclass 34, count 2 2006.168.07:42:02.39#ibcon#read 6, iclass 34, count 2 2006.168.07:42:02.39#ibcon#end of sib2, iclass 34, count 2 2006.168.07:42:02.39#ibcon#*mode == 0, iclass 34, count 2 2006.168.07:42:02.39#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.168.07:42:02.39#ibcon#[27=AT06-04\r\n] 2006.168.07:42:02.39#ibcon#*before write, iclass 34, count 2 2006.168.07:42:02.39#ibcon#enter sib2, iclass 34, count 2 2006.168.07:42:02.39#ibcon#flushed, iclass 34, count 2 2006.168.07:42:02.39#ibcon#about to write, iclass 34, count 2 2006.168.07:42:02.39#ibcon#wrote, iclass 34, count 2 2006.168.07:42:02.39#ibcon#about to read 3, iclass 34, count 2 2006.168.07:42:02.42#ibcon#read 3, iclass 34, count 2 2006.168.07:42:02.42#ibcon#about to read 4, iclass 34, count 2 2006.168.07:42:02.42#ibcon#read 4, iclass 34, count 2 2006.168.07:42:02.42#ibcon#about to read 5, iclass 34, count 2 2006.168.07:42:02.42#ibcon#read 5, iclass 34, count 2 2006.168.07:42:02.42#ibcon#about to read 6, iclass 34, count 2 2006.168.07:42:02.42#ibcon#read 6, iclass 34, count 2 2006.168.07:42:02.42#ibcon#end of sib2, iclass 34, count 2 2006.168.07:42:02.42#ibcon#*after write, iclass 34, count 2 2006.168.07:42:02.42#ibcon#*before return 0, iclass 34, count 2 2006.168.07:42:02.42#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:42:02.42#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:42:02.42#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.168.07:42:02.42#ibcon#ireg 7 cls_cnt 0 2006.168.07:42:02.42#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:42:02.54#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:42:02.54#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:42:02.54#ibcon#enter wrdev, iclass 34, count 0 2006.168.07:42:02.54#ibcon#first serial, iclass 34, count 0 2006.168.07:42:02.54#ibcon#enter sib2, iclass 34, count 0 2006.168.07:42:02.54#ibcon#flushed, iclass 34, count 0 2006.168.07:42:02.54#ibcon#about to write, iclass 34, count 0 2006.168.07:42:02.54#ibcon#wrote, iclass 34, count 0 2006.168.07:42:02.54#ibcon#about to read 3, iclass 34, count 0 2006.168.07:42:02.56#ibcon#read 3, iclass 34, count 0 2006.168.07:42:02.56#ibcon#about to read 4, iclass 34, count 0 2006.168.07:42:02.56#ibcon#read 4, iclass 34, count 0 2006.168.07:42:02.56#ibcon#about to read 5, iclass 34, count 0 2006.168.07:42:02.56#ibcon#read 5, iclass 34, count 0 2006.168.07:42:02.56#ibcon#about to read 6, iclass 34, count 0 2006.168.07:42:02.56#ibcon#read 6, iclass 34, count 0 2006.168.07:42:02.56#ibcon#end of sib2, iclass 34, count 0 2006.168.07:42:02.56#ibcon#*mode == 0, iclass 34, count 0 2006.168.07:42:02.56#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.168.07:42:02.56#ibcon#[27=USB\r\n] 2006.168.07:42:02.56#ibcon#*before write, iclass 34, count 0 2006.168.07:42:02.56#ibcon#enter sib2, iclass 34, count 0 2006.168.07:42:02.56#ibcon#flushed, iclass 34, count 0 2006.168.07:42:02.56#ibcon#about to write, iclass 34, count 0 2006.168.07:42:02.56#ibcon#wrote, iclass 34, count 0 2006.168.07:42:02.56#ibcon#about to read 3, iclass 34, count 0 2006.168.07:42:02.59#ibcon#read 3, iclass 34, count 0 2006.168.07:42:02.59#ibcon#about to read 4, iclass 34, count 0 2006.168.07:42:02.59#ibcon#read 4, iclass 34, count 0 2006.168.07:42:02.59#ibcon#about to read 5, iclass 34, count 0 2006.168.07:42:02.59#ibcon#read 5, iclass 34, count 0 2006.168.07:42:02.59#ibcon#about to read 6, iclass 34, count 0 2006.168.07:42:02.59#ibcon#read 6, iclass 34, count 0 2006.168.07:42:02.59#ibcon#end of sib2, iclass 34, count 0 2006.168.07:42:02.59#ibcon#*after write, iclass 34, count 0 2006.168.07:42:02.59#ibcon#*before return 0, iclass 34, count 0 2006.168.07:42:02.59#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:42:02.59#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:42:02.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.168.07:42:02.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.168.07:42:02.59$vc4f8/vabw=wide 2006.168.07:42:02.59#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.168.07:42:02.59#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.168.07:42:02.59#ibcon#ireg 8 cls_cnt 0 2006.168.07:42:02.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:42:02.59#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:42:02.59#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:42:02.59#ibcon#enter wrdev, iclass 36, count 0 2006.168.07:42:02.59#ibcon#first serial, iclass 36, count 0 2006.168.07:42:02.59#ibcon#enter sib2, iclass 36, count 0 2006.168.07:42:02.59#ibcon#flushed, iclass 36, count 0 2006.168.07:42:02.59#ibcon#about to write, iclass 36, count 0 2006.168.07:42:02.59#ibcon#wrote, iclass 36, count 0 2006.168.07:42:02.59#ibcon#about to read 3, iclass 36, count 0 2006.168.07:42:02.61#ibcon#read 3, iclass 36, count 0 2006.168.07:42:02.61#ibcon#about to read 4, iclass 36, count 0 2006.168.07:42:02.61#ibcon#read 4, iclass 36, count 0 2006.168.07:42:02.61#ibcon#about to read 5, iclass 36, count 0 2006.168.07:42:02.61#ibcon#read 5, iclass 36, count 0 2006.168.07:42:02.61#ibcon#about to read 6, iclass 36, count 0 2006.168.07:42:02.61#ibcon#read 6, iclass 36, count 0 2006.168.07:42:02.61#ibcon#end of sib2, iclass 36, count 0 2006.168.07:42:02.61#ibcon#*mode == 0, iclass 36, count 0 2006.168.07:42:02.61#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.168.07:42:02.61#ibcon#[25=BW32\r\n] 2006.168.07:42:02.61#ibcon#*before write, iclass 36, count 0 2006.168.07:42:02.61#ibcon#enter sib2, iclass 36, count 0 2006.168.07:42:02.61#ibcon#flushed, iclass 36, count 0 2006.168.07:42:02.61#ibcon#about to write, iclass 36, count 0 2006.168.07:42:02.61#ibcon#wrote, iclass 36, count 0 2006.168.07:42:02.61#ibcon#about to read 3, iclass 36, count 0 2006.168.07:42:02.64#ibcon#read 3, iclass 36, count 0 2006.168.07:42:02.64#ibcon#about to read 4, iclass 36, count 0 2006.168.07:42:02.64#ibcon#read 4, iclass 36, count 0 2006.168.07:42:02.64#ibcon#about to read 5, iclass 36, count 0 2006.168.07:42:02.64#ibcon#read 5, iclass 36, count 0 2006.168.07:42:02.64#ibcon#about to read 6, iclass 36, count 0 2006.168.07:42:02.64#ibcon#read 6, iclass 36, count 0 2006.168.07:42:02.64#ibcon#end of sib2, iclass 36, count 0 2006.168.07:42:02.64#ibcon#*after write, iclass 36, count 0 2006.168.07:42:02.64#ibcon#*before return 0, iclass 36, count 0 2006.168.07:42:02.64#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:42:02.64#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:42:02.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.168.07:42:02.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.168.07:42:02.64$vc4f8/vbbw=wide 2006.168.07:42:02.64#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.168.07:42:02.64#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.168.07:42:02.64#ibcon#ireg 8 cls_cnt 0 2006.168.07:42:02.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:42:02.71#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:42:02.71#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:42:02.71#ibcon#enter wrdev, iclass 38, count 0 2006.168.07:42:02.71#ibcon#first serial, iclass 38, count 0 2006.168.07:42:02.71#ibcon#enter sib2, iclass 38, count 0 2006.168.07:42:02.71#ibcon#flushed, iclass 38, count 0 2006.168.07:42:02.71#ibcon#about to write, iclass 38, count 0 2006.168.07:42:02.71#ibcon#wrote, iclass 38, count 0 2006.168.07:42:02.71#ibcon#about to read 3, iclass 38, count 0 2006.168.07:42:02.73#ibcon#read 3, iclass 38, count 0 2006.168.07:42:02.73#ibcon#about to read 4, iclass 38, count 0 2006.168.07:42:02.73#ibcon#read 4, iclass 38, count 0 2006.168.07:42:02.73#ibcon#about to read 5, iclass 38, count 0 2006.168.07:42:02.73#ibcon#read 5, iclass 38, count 0 2006.168.07:42:02.73#ibcon#about to read 6, iclass 38, count 0 2006.168.07:42:02.73#ibcon#read 6, iclass 38, count 0 2006.168.07:42:02.73#ibcon#end of sib2, iclass 38, count 0 2006.168.07:42:02.73#ibcon#*mode == 0, iclass 38, count 0 2006.168.07:42:02.73#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.168.07:42:02.73#ibcon#[27=BW32\r\n] 2006.168.07:42:02.73#ibcon#*before write, iclass 38, count 0 2006.168.07:42:02.73#ibcon#enter sib2, iclass 38, count 0 2006.168.07:42:02.73#ibcon#flushed, iclass 38, count 0 2006.168.07:42:02.73#ibcon#about to write, iclass 38, count 0 2006.168.07:42:02.73#ibcon#wrote, iclass 38, count 0 2006.168.07:42:02.73#ibcon#about to read 3, iclass 38, count 0 2006.168.07:42:02.76#ibcon#read 3, iclass 38, count 0 2006.168.07:42:02.76#ibcon#about to read 4, iclass 38, count 0 2006.168.07:42:02.76#ibcon#read 4, iclass 38, count 0 2006.168.07:42:02.76#ibcon#about to read 5, iclass 38, count 0 2006.168.07:42:02.76#ibcon#read 5, iclass 38, count 0 2006.168.07:42:02.76#ibcon#about to read 6, iclass 38, count 0 2006.168.07:42:02.76#ibcon#read 6, iclass 38, count 0 2006.168.07:42:02.76#ibcon#end of sib2, iclass 38, count 0 2006.168.07:42:02.76#ibcon#*after write, iclass 38, count 0 2006.168.07:42:02.76#ibcon#*before return 0, iclass 38, count 0 2006.168.07:42:02.76#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:42:02.76#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:42:02.76#ibcon#about to clear, iclass 38 cls_cnt 0 2006.168.07:42:02.76#ibcon#cleared, iclass 38 cls_cnt 0 2006.168.07:42:02.76$4f8m12a/ifd4f 2006.168.07:42:02.76$ifd4f/lo= 2006.168.07:42:02.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.07:42:02.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.07:42:02.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.07:42:02.76$ifd4f/patch= 2006.168.07:42:02.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.07:42:02.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.07:42:02.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.07:42:02.76$4f8m12a/"form=m,16.000,1:2 2006.168.07:42:02.76$4f8m12a/"tpicd 2006.168.07:42:02.76$4f8m12a/echo=off 2006.168.07:42:02.76$4f8m12a/xlog=off 2006.168.07:42:02.76:!2006.168.07:42:30 2006.168.07:42:15.14#trakl#Source acquired 2006.168.07:42:15.14#flagr#flagr/antenna,acquired 2006.168.07:42:30.00:preob 2006.168.07:42:31.14/onsource/TRACKING 2006.168.07:42:31.14:!2006.168.07:42:40 2006.168.07:42:40.00:data_valid=on 2006.168.07:42:40.00:midob 2006.168.07:42:40.14/onsource/TRACKING 2006.168.07:42:40.14/wx/27.63,1004.5,73 2006.168.07:42:40.29/cable/+6.4721E-03 2006.168.07:42:41.38/va/01,08,usb,yes,29,31 2006.168.07:42:41.38/va/02,07,usb,yes,29,31 2006.168.07:42:41.38/va/03,06,usb,yes,31,31 2006.168.07:42:41.38/va/04,07,usb,yes,30,32 2006.168.07:42:41.38/va/05,07,usb,yes,29,31 2006.168.07:42:41.38/va/06,06,usb,yes,28,28 2006.168.07:42:41.38/va/07,06,usb,yes,29,29 2006.168.07:42:41.38/va/08,07,usb,yes,27,27 2006.168.07:42:41.61/valo/01,532.99,yes,locked 2006.168.07:42:41.61/valo/02,572.99,yes,locked 2006.168.07:42:41.61/valo/03,672.99,yes,locked 2006.168.07:42:41.61/valo/04,832.99,yes,locked 2006.168.07:42:41.61/valo/05,652.99,yes,locked 2006.168.07:42:41.61/valo/06,772.99,yes,locked 2006.168.07:42:41.61/valo/07,832.99,yes,locked 2006.168.07:42:41.61/valo/08,852.99,yes,locked 2006.168.07:42:42.70/vb/01,04,usb,yes,29,27 2006.168.07:42:42.70/vb/02,04,usb,yes,30,32 2006.168.07:42:42.70/vb/03,04,usb,yes,27,31 2006.168.07:42:42.70/vb/04,04,usb,yes,28,28 2006.168.07:42:42.70/vb/05,04,usb,yes,26,30 2006.168.07:42:42.70/vb/06,04,usb,yes,27,30 2006.168.07:42:42.70/vb/07,04,usb,yes,29,29 2006.168.07:42:42.70/vb/08,04,usb,yes,27,30 2006.168.07:42:42.94/vblo/01,632.99,yes,locked 2006.168.07:42:42.94/vblo/02,640.99,yes,locked 2006.168.07:42:42.94/vblo/03,656.99,yes,locked 2006.168.07:42:42.94/vblo/04,712.99,yes,locked 2006.168.07:42:42.94/vblo/05,744.99,yes,locked 2006.168.07:42:42.94/vblo/06,752.99,yes,locked 2006.168.07:42:42.94/vblo/07,734.99,yes,locked 2006.168.07:42:42.94/vblo/08,744.99,yes,locked 2006.168.07:42:43.09/vabw/8 2006.168.07:42:43.24/vbbw/8 2006.168.07:42:43.33/xfe/off,on,15.0 2006.168.07:42:43.70/ifatt/23,28,28,28 2006.168.07:42:44.08/fmout-gps/S +4.18E-07 2006.168.07:42:44.16:!2006.168.07:43:40 2006.168.07:43:40.00:data_valid=off 2006.168.07:43:40.00:postob 2006.168.07:43:40.21/cable/+6.4709E-03 2006.168.07:43:40.21/wx/27.60,1004.6,73 2006.168.07:43:41.08/fmout-gps/S +4.18E-07 2006.168.07:43:41.08:scan_name=168-0744,k06168,60 2006.168.07:43:41.08:source=1418+546,141946.60,542314.8,2000.0,cw 2006.168.07:43:41.14#flagr#flagr/antenna,new-source 2006.168.07:43:42.14:checkk5 2006.168.07:43:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.168.07:43:42.88/chk_autoobs//k5ts2/ autoobs is running! 2006.168.07:43:43.26/chk_autoobs//k5ts3/ autoobs is running! 2006.168.07:43:43.64/chk_autoobs//k5ts4/ autoobs is running! 2006.168.07:43:44.02/chk_obsdata//k5ts1/T1680742??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:43:44.39/chk_obsdata//k5ts2/T1680742??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:43:44.77/chk_obsdata//k5ts3/T1680742??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:43:45.14/chk_obsdata//k5ts4/T1680742??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:43:45.83/k5log//k5ts1_log_newline 2006.168.07:43:46.53/k5log//k5ts2_log_newline 2006.168.07:43:47.21/k5log//k5ts3_log_newline 2006.168.07:43:47.90/k5log//k5ts4_log_newline 2006.168.07:43:47.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.07:43:47.93:4f8m12a=1 2006.168.07:43:47.93$4f8m12a/echo=on 2006.168.07:43:47.93$4f8m12a/pcalon 2006.168.07:43:47.93$pcalon/"no phase cal control is implemented here 2006.168.07:43:47.93$4f8m12a/"tpicd=stop 2006.168.07:43:47.93$4f8m12a/vc4f8 2006.168.07:43:47.93$vc4f8/valo=1,532.99 2006.168.07:43:47.93#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.168.07:43:47.93#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.168.07:43:47.93#ibcon#ireg 17 cls_cnt 0 2006.168.07:43:47.93#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:43:47.93#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:43:47.93#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:43:47.93#ibcon#enter wrdev, iclass 4, count 0 2006.168.07:43:47.93#ibcon#first serial, iclass 4, count 0 2006.168.07:43:47.93#ibcon#enter sib2, iclass 4, count 0 2006.168.07:43:47.93#ibcon#flushed, iclass 4, count 0 2006.168.07:43:47.93#ibcon#about to write, iclass 4, count 0 2006.168.07:43:47.93#ibcon#wrote, iclass 4, count 0 2006.168.07:43:47.93#ibcon#about to read 3, iclass 4, count 0 2006.168.07:43:47.98#ibcon#read 3, iclass 4, count 0 2006.168.07:43:47.98#ibcon#about to read 4, iclass 4, count 0 2006.168.07:43:47.98#ibcon#read 4, iclass 4, count 0 2006.168.07:43:47.98#ibcon#about to read 5, iclass 4, count 0 2006.168.07:43:47.98#ibcon#read 5, iclass 4, count 0 2006.168.07:43:47.98#ibcon#about to read 6, iclass 4, count 0 2006.168.07:43:47.98#ibcon#read 6, iclass 4, count 0 2006.168.07:43:47.98#ibcon#end of sib2, iclass 4, count 0 2006.168.07:43:47.98#ibcon#*mode == 0, iclass 4, count 0 2006.168.07:43:47.98#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.168.07:43:47.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.07:43:47.98#ibcon#*before write, iclass 4, count 0 2006.168.07:43:47.98#ibcon#enter sib2, iclass 4, count 0 2006.168.07:43:47.98#ibcon#flushed, iclass 4, count 0 2006.168.07:43:47.98#ibcon#about to write, iclass 4, count 0 2006.168.07:43:47.98#ibcon#wrote, iclass 4, count 0 2006.168.07:43:47.98#ibcon#about to read 3, iclass 4, count 0 2006.168.07:43:48.03#ibcon#read 3, iclass 4, count 0 2006.168.07:43:48.03#ibcon#about to read 4, iclass 4, count 0 2006.168.07:43:48.03#ibcon#read 4, iclass 4, count 0 2006.168.07:43:48.03#ibcon#about to read 5, iclass 4, count 0 2006.168.07:43:48.03#ibcon#read 5, iclass 4, count 0 2006.168.07:43:48.03#ibcon#about to read 6, iclass 4, count 0 2006.168.07:43:48.03#ibcon#read 6, iclass 4, count 0 2006.168.07:43:48.03#ibcon#end of sib2, iclass 4, count 0 2006.168.07:43:48.03#ibcon#*after write, iclass 4, count 0 2006.168.07:43:48.03#ibcon#*before return 0, iclass 4, count 0 2006.168.07:43:48.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:43:48.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:43:48.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.168.07:43:48.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.168.07:43:48.03$vc4f8/va=1,8 2006.168.07:43:48.03#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.168.07:43:48.03#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.168.07:43:48.03#ibcon#ireg 11 cls_cnt 2 2006.168.07:43:48.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:43:48.03#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:43:48.03#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:43:48.03#ibcon#enter wrdev, iclass 6, count 2 2006.168.07:43:48.03#ibcon#first serial, iclass 6, count 2 2006.168.07:43:48.03#ibcon#enter sib2, iclass 6, count 2 2006.168.07:43:48.03#ibcon#flushed, iclass 6, count 2 2006.168.07:43:48.03#ibcon#about to write, iclass 6, count 2 2006.168.07:43:48.03#ibcon#wrote, iclass 6, count 2 2006.168.07:43:48.03#ibcon#about to read 3, iclass 6, count 2 2006.168.07:43:48.05#ibcon#read 3, iclass 6, count 2 2006.168.07:43:48.05#ibcon#about to read 4, iclass 6, count 2 2006.168.07:43:48.05#ibcon#read 4, iclass 6, count 2 2006.168.07:43:48.05#ibcon#about to read 5, iclass 6, count 2 2006.168.07:43:48.05#ibcon#read 5, iclass 6, count 2 2006.168.07:43:48.05#ibcon#about to read 6, iclass 6, count 2 2006.168.07:43:48.05#ibcon#read 6, iclass 6, count 2 2006.168.07:43:48.05#ibcon#end of sib2, iclass 6, count 2 2006.168.07:43:48.05#ibcon#*mode == 0, iclass 6, count 2 2006.168.07:43:48.05#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.168.07:43:48.05#ibcon#[25=AT01-08\r\n] 2006.168.07:43:48.05#ibcon#*before write, iclass 6, count 2 2006.168.07:43:48.05#ibcon#enter sib2, iclass 6, count 2 2006.168.07:43:48.05#ibcon#flushed, iclass 6, count 2 2006.168.07:43:48.05#ibcon#about to write, iclass 6, count 2 2006.168.07:43:48.05#ibcon#wrote, iclass 6, count 2 2006.168.07:43:48.05#ibcon#about to read 3, iclass 6, count 2 2006.168.07:43:48.09#ibcon#read 3, iclass 6, count 2 2006.168.07:43:48.09#ibcon#about to read 4, iclass 6, count 2 2006.168.07:43:48.09#ibcon#read 4, iclass 6, count 2 2006.168.07:43:48.09#ibcon#about to read 5, iclass 6, count 2 2006.168.07:43:48.09#ibcon#read 5, iclass 6, count 2 2006.168.07:43:48.09#ibcon#about to read 6, iclass 6, count 2 2006.168.07:43:48.09#ibcon#read 6, iclass 6, count 2 2006.168.07:43:48.09#ibcon#end of sib2, iclass 6, count 2 2006.168.07:43:48.09#ibcon#*after write, iclass 6, count 2 2006.168.07:43:48.09#ibcon#*before return 0, iclass 6, count 2 2006.168.07:43:48.09#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:43:48.09#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:43:48.09#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.168.07:43:48.09#ibcon#ireg 7 cls_cnt 0 2006.168.07:43:48.09#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:43:48.21#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:43:48.21#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:43:48.21#ibcon#enter wrdev, iclass 6, count 0 2006.168.07:43:48.21#ibcon#first serial, iclass 6, count 0 2006.168.07:43:48.21#ibcon#enter sib2, iclass 6, count 0 2006.168.07:43:48.21#ibcon#flushed, iclass 6, count 0 2006.168.07:43:48.21#ibcon#about to write, iclass 6, count 0 2006.168.07:43:48.21#ibcon#wrote, iclass 6, count 0 2006.168.07:43:48.21#ibcon#about to read 3, iclass 6, count 0 2006.168.07:43:48.23#ibcon#read 3, iclass 6, count 0 2006.168.07:43:48.23#ibcon#about to read 4, iclass 6, count 0 2006.168.07:43:48.23#ibcon#read 4, iclass 6, count 0 2006.168.07:43:48.23#ibcon#about to read 5, iclass 6, count 0 2006.168.07:43:48.23#ibcon#read 5, iclass 6, count 0 2006.168.07:43:48.23#ibcon#about to read 6, iclass 6, count 0 2006.168.07:43:48.23#ibcon#read 6, iclass 6, count 0 2006.168.07:43:48.23#ibcon#end of sib2, iclass 6, count 0 2006.168.07:43:48.23#ibcon#*mode == 0, iclass 6, count 0 2006.168.07:43:48.23#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.168.07:43:48.23#ibcon#[25=USB\r\n] 2006.168.07:43:48.23#ibcon#*before write, iclass 6, count 0 2006.168.07:43:48.23#ibcon#enter sib2, iclass 6, count 0 2006.168.07:43:48.23#ibcon#flushed, iclass 6, count 0 2006.168.07:43:48.23#ibcon#about to write, iclass 6, count 0 2006.168.07:43:48.23#ibcon#wrote, iclass 6, count 0 2006.168.07:43:48.23#ibcon#about to read 3, iclass 6, count 0 2006.168.07:43:48.26#ibcon#read 3, iclass 6, count 0 2006.168.07:43:48.26#ibcon#about to read 4, iclass 6, count 0 2006.168.07:43:48.26#ibcon#read 4, iclass 6, count 0 2006.168.07:43:48.26#ibcon#about to read 5, iclass 6, count 0 2006.168.07:43:48.26#ibcon#read 5, iclass 6, count 0 2006.168.07:43:48.26#ibcon#about to read 6, iclass 6, count 0 2006.168.07:43:48.26#ibcon#read 6, iclass 6, count 0 2006.168.07:43:48.26#ibcon#end of sib2, iclass 6, count 0 2006.168.07:43:48.26#ibcon#*after write, iclass 6, count 0 2006.168.07:43:48.26#ibcon#*before return 0, iclass 6, count 0 2006.168.07:43:48.26#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:43:48.26#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:43:48.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.168.07:43:48.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.168.07:43:48.26$vc4f8/valo=2,572.99 2006.168.07:43:48.26#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.168.07:43:48.26#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.168.07:43:48.26#ibcon#ireg 17 cls_cnt 0 2006.168.07:43:48.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:43:48.26#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:43:48.26#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:43:48.26#ibcon#enter wrdev, iclass 10, count 0 2006.168.07:43:48.26#ibcon#first serial, iclass 10, count 0 2006.168.07:43:48.26#ibcon#enter sib2, iclass 10, count 0 2006.168.07:43:48.26#ibcon#flushed, iclass 10, count 0 2006.168.07:43:48.26#ibcon#about to write, iclass 10, count 0 2006.168.07:43:48.26#ibcon#wrote, iclass 10, count 0 2006.168.07:43:48.26#ibcon#about to read 3, iclass 10, count 0 2006.168.07:43:48.28#ibcon#read 3, iclass 10, count 0 2006.168.07:43:48.28#ibcon#about to read 4, iclass 10, count 0 2006.168.07:43:48.28#ibcon#read 4, iclass 10, count 0 2006.168.07:43:48.28#ibcon#about to read 5, iclass 10, count 0 2006.168.07:43:48.28#ibcon#read 5, iclass 10, count 0 2006.168.07:43:48.28#ibcon#about to read 6, iclass 10, count 0 2006.168.07:43:48.28#ibcon#read 6, iclass 10, count 0 2006.168.07:43:48.28#ibcon#end of sib2, iclass 10, count 0 2006.168.07:43:48.28#ibcon#*mode == 0, iclass 10, count 0 2006.168.07:43:48.28#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.168.07:43:48.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.07:43:48.28#ibcon#*before write, iclass 10, count 0 2006.168.07:43:48.28#ibcon#enter sib2, iclass 10, count 0 2006.168.07:43:48.28#ibcon#flushed, iclass 10, count 0 2006.168.07:43:48.28#ibcon#about to write, iclass 10, count 0 2006.168.07:43:48.28#ibcon#wrote, iclass 10, count 0 2006.168.07:43:48.28#ibcon#about to read 3, iclass 10, count 0 2006.168.07:43:48.32#ibcon#read 3, iclass 10, count 0 2006.168.07:43:48.32#ibcon#about to read 4, iclass 10, count 0 2006.168.07:43:48.32#ibcon#read 4, iclass 10, count 0 2006.168.07:43:48.32#ibcon#about to read 5, iclass 10, count 0 2006.168.07:43:48.32#ibcon#read 5, iclass 10, count 0 2006.168.07:43:48.32#ibcon#about to read 6, iclass 10, count 0 2006.168.07:43:48.32#ibcon#read 6, iclass 10, count 0 2006.168.07:43:48.32#ibcon#end of sib2, iclass 10, count 0 2006.168.07:43:48.32#ibcon#*after write, iclass 10, count 0 2006.168.07:43:48.32#ibcon#*before return 0, iclass 10, count 0 2006.168.07:43:48.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:43:48.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:43:48.32#ibcon#about to clear, iclass 10 cls_cnt 0 2006.168.07:43:48.32#ibcon#cleared, iclass 10 cls_cnt 0 2006.168.07:43:48.32$vc4f8/va=2,7 2006.168.07:43:48.32#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.168.07:43:48.32#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.168.07:43:48.32#ibcon#ireg 11 cls_cnt 2 2006.168.07:43:48.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:43:48.38#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:43:48.38#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:43:48.38#ibcon#enter wrdev, iclass 12, count 2 2006.168.07:43:48.38#ibcon#first serial, iclass 12, count 2 2006.168.07:43:48.38#ibcon#enter sib2, iclass 12, count 2 2006.168.07:43:48.38#ibcon#flushed, iclass 12, count 2 2006.168.07:43:48.38#ibcon#about to write, iclass 12, count 2 2006.168.07:43:48.38#ibcon#wrote, iclass 12, count 2 2006.168.07:43:48.38#ibcon#about to read 3, iclass 12, count 2 2006.168.07:43:48.40#ibcon#read 3, iclass 12, count 2 2006.168.07:43:48.40#ibcon#about to read 4, iclass 12, count 2 2006.168.07:43:48.40#ibcon#read 4, iclass 12, count 2 2006.168.07:43:48.40#ibcon#about to read 5, iclass 12, count 2 2006.168.07:43:48.40#ibcon#read 5, iclass 12, count 2 2006.168.07:43:48.40#ibcon#about to read 6, iclass 12, count 2 2006.168.07:43:48.40#ibcon#read 6, iclass 12, count 2 2006.168.07:43:48.40#ibcon#end of sib2, iclass 12, count 2 2006.168.07:43:48.40#ibcon#*mode == 0, iclass 12, count 2 2006.168.07:43:48.40#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.168.07:43:48.40#ibcon#[25=AT02-07\r\n] 2006.168.07:43:48.40#ibcon#*before write, iclass 12, count 2 2006.168.07:43:48.40#ibcon#enter sib2, iclass 12, count 2 2006.168.07:43:48.40#ibcon#flushed, iclass 12, count 2 2006.168.07:43:48.40#ibcon#about to write, iclass 12, count 2 2006.168.07:43:48.40#ibcon#wrote, iclass 12, count 2 2006.168.07:43:48.40#ibcon#about to read 3, iclass 12, count 2 2006.168.07:43:48.43#ibcon#read 3, iclass 12, count 2 2006.168.07:43:48.43#ibcon#about to read 4, iclass 12, count 2 2006.168.07:43:48.43#ibcon#read 4, iclass 12, count 2 2006.168.07:43:48.43#ibcon#about to read 5, iclass 12, count 2 2006.168.07:43:48.43#ibcon#read 5, iclass 12, count 2 2006.168.07:43:48.43#ibcon#about to read 6, iclass 12, count 2 2006.168.07:43:48.43#ibcon#read 6, iclass 12, count 2 2006.168.07:43:48.43#ibcon#end of sib2, iclass 12, count 2 2006.168.07:43:48.43#ibcon#*after write, iclass 12, count 2 2006.168.07:43:48.43#ibcon#*before return 0, iclass 12, count 2 2006.168.07:43:48.43#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:43:48.43#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:43:48.43#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.168.07:43:48.43#ibcon#ireg 7 cls_cnt 0 2006.168.07:43:48.43#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:43:48.55#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:43:48.55#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:43:48.55#ibcon#enter wrdev, iclass 12, count 0 2006.168.07:43:48.55#ibcon#first serial, iclass 12, count 0 2006.168.07:43:48.55#ibcon#enter sib2, iclass 12, count 0 2006.168.07:43:48.55#ibcon#flushed, iclass 12, count 0 2006.168.07:43:48.55#ibcon#about to write, iclass 12, count 0 2006.168.07:43:48.55#ibcon#wrote, iclass 12, count 0 2006.168.07:43:48.55#ibcon#about to read 3, iclass 12, count 0 2006.168.07:43:48.57#ibcon#read 3, iclass 12, count 0 2006.168.07:43:48.57#ibcon#about to read 4, iclass 12, count 0 2006.168.07:43:48.57#ibcon#read 4, iclass 12, count 0 2006.168.07:43:48.57#ibcon#about to read 5, iclass 12, count 0 2006.168.07:43:48.57#ibcon#read 5, iclass 12, count 0 2006.168.07:43:48.57#ibcon#about to read 6, iclass 12, count 0 2006.168.07:43:48.57#ibcon#read 6, iclass 12, count 0 2006.168.07:43:48.57#ibcon#end of sib2, iclass 12, count 0 2006.168.07:43:48.57#ibcon#*mode == 0, iclass 12, count 0 2006.168.07:43:48.57#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.168.07:43:48.57#ibcon#[25=USB\r\n] 2006.168.07:43:48.57#ibcon#*before write, iclass 12, count 0 2006.168.07:43:48.57#ibcon#enter sib2, iclass 12, count 0 2006.168.07:43:48.57#ibcon#flushed, iclass 12, count 0 2006.168.07:43:48.57#ibcon#about to write, iclass 12, count 0 2006.168.07:43:48.57#ibcon#wrote, iclass 12, count 0 2006.168.07:43:48.57#ibcon#about to read 3, iclass 12, count 0 2006.168.07:43:48.60#ibcon#read 3, iclass 12, count 0 2006.168.07:43:48.60#ibcon#about to read 4, iclass 12, count 0 2006.168.07:43:48.60#ibcon#read 4, iclass 12, count 0 2006.168.07:43:48.60#ibcon#about to read 5, iclass 12, count 0 2006.168.07:43:48.60#ibcon#read 5, iclass 12, count 0 2006.168.07:43:48.60#ibcon#about to read 6, iclass 12, count 0 2006.168.07:43:48.60#ibcon#read 6, iclass 12, count 0 2006.168.07:43:48.60#ibcon#end of sib2, iclass 12, count 0 2006.168.07:43:48.60#ibcon#*after write, iclass 12, count 0 2006.168.07:43:48.60#ibcon#*before return 0, iclass 12, count 0 2006.168.07:43:48.60#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:43:48.60#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:43:48.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.168.07:43:48.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.168.07:43:48.60$vc4f8/valo=3,672.99 2006.168.07:43:48.60#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.168.07:43:48.60#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.168.07:43:48.60#ibcon#ireg 17 cls_cnt 0 2006.168.07:43:48.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:43:48.60#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:43:48.60#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:43:48.60#ibcon#enter wrdev, iclass 14, count 0 2006.168.07:43:48.60#ibcon#first serial, iclass 14, count 0 2006.168.07:43:48.60#ibcon#enter sib2, iclass 14, count 0 2006.168.07:43:48.60#ibcon#flushed, iclass 14, count 0 2006.168.07:43:48.60#ibcon#about to write, iclass 14, count 0 2006.168.07:43:48.60#ibcon#wrote, iclass 14, count 0 2006.168.07:43:48.60#ibcon#about to read 3, iclass 14, count 0 2006.168.07:43:48.62#ibcon#read 3, iclass 14, count 0 2006.168.07:43:48.62#ibcon#about to read 4, iclass 14, count 0 2006.168.07:43:48.62#ibcon#read 4, iclass 14, count 0 2006.168.07:43:48.62#ibcon#about to read 5, iclass 14, count 0 2006.168.07:43:48.62#ibcon#read 5, iclass 14, count 0 2006.168.07:43:48.62#ibcon#about to read 6, iclass 14, count 0 2006.168.07:43:48.62#ibcon#read 6, iclass 14, count 0 2006.168.07:43:48.62#ibcon#end of sib2, iclass 14, count 0 2006.168.07:43:48.62#ibcon#*mode == 0, iclass 14, count 0 2006.168.07:43:48.62#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.168.07:43:48.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.07:43:48.62#ibcon#*before write, iclass 14, count 0 2006.168.07:43:48.62#ibcon#enter sib2, iclass 14, count 0 2006.168.07:43:48.62#ibcon#flushed, iclass 14, count 0 2006.168.07:43:48.62#ibcon#about to write, iclass 14, count 0 2006.168.07:43:48.62#ibcon#wrote, iclass 14, count 0 2006.168.07:43:48.62#ibcon#about to read 3, iclass 14, count 0 2006.168.07:43:48.66#ibcon#read 3, iclass 14, count 0 2006.168.07:43:48.66#ibcon#about to read 4, iclass 14, count 0 2006.168.07:43:48.66#ibcon#read 4, iclass 14, count 0 2006.168.07:43:48.66#ibcon#about to read 5, iclass 14, count 0 2006.168.07:43:48.66#ibcon#read 5, iclass 14, count 0 2006.168.07:43:48.66#ibcon#about to read 6, iclass 14, count 0 2006.168.07:43:48.66#ibcon#read 6, iclass 14, count 0 2006.168.07:43:48.66#ibcon#end of sib2, iclass 14, count 0 2006.168.07:43:48.66#ibcon#*after write, iclass 14, count 0 2006.168.07:43:48.66#ibcon#*before return 0, iclass 14, count 0 2006.168.07:43:48.66#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:43:48.66#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:43:48.66#ibcon#about to clear, iclass 14 cls_cnt 0 2006.168.07:43:48.66#ibcon#cleared, iclass 14 cls_cnt 0 2006.168.07:43:48.66$vc4f8/va=3,6 2006.168.07:43:48.66#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.168.07:43:48.66#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.168.07:43:48.66#ibcon#ireg 11 cls_cnt 2 2006.168.07:43:48.66#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:43:48.72#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:43:48.72#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:43:48.72#ibcon#enter wrdev, iclass 16, count 2 2006.168.07:43:48.72#ibcon#first serial, iclass 16, count 2 2006.168.07:43:48.72#ibcon#enter sib2, iclass 16, count 2 2006.168.07:43:48.72#ibcon#flushed, iclass 16, count 2 2006.168.07:43:48.72#ibcon#about to write, iclass 16, count 2 2006.168.07:43:48.72#ibcon#wrote, iclass 16, count 2 2006.168.07:43:48.72#ibcon#about to read 3, iclass 16, count 2 2006.168.07:43:48.74#ibcon#read 3, iclass 16, count 2 2006.168.07:43:48.74#ibcon#about to read 4, iclass 16, count 2 2006.168.07:43:48.74#ibcon#read 4, iclass 16, count 2 2006.168.07:43:48.74#ibcon#about to read 5, iclass 16, count 2 2006.168.07:43:48.74#ibcon#read 5, iclass 16, count 2 2006.168.07:43:48.74#ibcon#about to read 6, iclass 16, count 2 2006.168.07:43:48.74#ibcon#read 6, iclass 16, count 2 2006.168.07:43:48.74#ibcon#end of sib2, iclass 16, count 2 2006.168.07:43:48.74#ibcon#*mode == 0, iclass 16, count 2 2006.168.07:43:48.74#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.168.07:43:48.74#ibcon#[25=AT03-06\r\n] 2006.168.07:43:48.74#ibcon#*before write, iclass 16, count 2 2006.168.07:43:48.74#ibcon#enter sib2, iclass 16, count 2 2006.168.07:43:48.74#ibcon#flushed, iclass 16, count 2 2006.168.07:43:48.74#ibcon#about to write, iclass 16, count 2 2006.168.07:43:48.74#ibcon#wrote, iclass 16, count 2 2006.168.07:43:48.74#ibcon#about to read 3, iclass 16, count 2 2006.168.07:43:48.78#ibcon#read 3, iclass 16, count 2 2006.168.07:43:48.78#ibcon#about to read 4, iclass 16, count 2 2006.168.07:43:48.78#ibcon#read 4, iclass 16, count 2 2006.168.07:43:48.78#ibcon#about to read 5, iclass 16, count 2 2006.168.07:43:48.78#ibcon#read 5, iclass 16, count 2 2006.168.07:43:48.78#ibcon#about to read 6, iclass 16, count 2 2006.168.07:43:48.78#ibcon#read 6, iclass 16, count 2 2006.168.07:43:48.78#ibcon#end of sib2, iclass 16, count 2 2006.168.07:43:48.78#ibcon#*after write, iclass 16, count 2 2006.168.07:43:48.78#ibcon#*before return 0, iclass 16, count 2 2006.168.07:43:48.78#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:43:48.78#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:43:48.78#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.168.07:43:48.78#ibcon#ireg 7 cls_cnt 0 2006.168.07:43:48.78#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:43:48.90#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:43:48.90#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:43:48.90#ibcon#enter wrdev, iclass 16, count 0 2006.168.07:43:48.90#ibcon#first serial, iclass 16, count 0 2006.168.07:43:48.90#ibcon#enter sib2, iclass 16, count 0 2006.168.07:43:48.90#ibcon#flushed, iclass 16, count 0 2006.168.07:43:48.90#ibcon#about to write, iclass 16, count 0 2006.168.07:43:48.90#ibcon#wrote, iclass 16, count 0 2006.168.07:43:48.90#ibcon#about to read 3, iclass 16, count 0 2006.168.07:43:48.92#ibcon#read 3, iclass 16, count 0 2006.168.07:43:48.92#ibcon#about to read 4, iclass 16, count 0 2006.168.07:43:48.92#ibcon#read 4, iclass 16, count 0 2006.168.07:43:48.92#ibcon#about to read 5, iclass 16, count 0 2006.168.07:43:48.92#ibcon#read 5, iclass 16, count 0 2006.168.07:43:48.92#ibcon#about to read 6, iclass 16, count 0 2006.168.07:43:48.92#ibcon#read 6, iclass 16, count 0 2006.168.07:43:48.92#ibcon#end of sib2, iclass 16, count 0 2006.168.07:43:48.92#ibcon#*mode == 0, iclass 16, count 0 2006.168.07:43:48.92#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.168.07:43:48.92#ibcon#[25=USB\r\n] 2006.168.07:43:48.92#ibcon#*before write, iclass 16, count 0 2006.168.07:43:48.92#ibcon#enter sib2, iclass 16, count 0 2006.168.07:43:48.92#ibcon#flushed, iclass 16, count 0 2006.168.07:43:48.92#ibcon#about to write, iclass 16, count 0 2006.168.07:43:48.92#ibcon#wrote, iclass 16, count 0 2006.168.07:43:48.92#ibcon#about to read 3, iclass 16, count 0 2006.168.07:43:48.95#ibcon#read 3, iclass 16, count 0 2006.168.07:43:48.95#ibcon#about to read 4, iclass 16, count 0 2006.168.07:43:48.95#ibcon#read 4, iclass 16, count 0 2006.168.07:43:48.95#ibcon#about to read 5, iclass 16, count 0 2006.168.07:43:48.95#ibcon#read 5, iclass 16, count 0 2006.168.07:43:48.95#ibcon#about to read 6, iclass 16, count 0 2006.168.07:43:48.95#ibcon#read 6, iclass 16, count 0 2006.168.07:43:48.95#ibcon#end of sib2, iclass 16, count 0 2006.168.07:43:48.95#ibcon#*after write, iclass 16, count 0 2006.168.07:43:48.95#ibcon#*before return 0, iclass 16, count 0 2006.168.07:43:48.95#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:43:48.95#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:43:48.95#ibcon#about to clear, iclass 16 cls_cnt 0 2006.168.07:43:48.95#ibcon#cleared, iclass 16 cls_cnt 0 2006.168.07:43:48.95$vc4f8/valo=4,832.99 2006.168.07:43:48.95#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.168.07:43:48.95#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.168.07:43:48.95#ibcon#ireg 17 cls_cnt 0 2006.168.07:43:48.95#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:43:48.95#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:43:48.95#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:43:48.95#ibcon#enter wrdev, iclass 18, count 0 2006.168.07:43:48.95#ibcon#first serial, iclass 18, count 0 2006.168.07:43:48.95#ibcon#enter sib2, iclass 18, count 0 2006.168.07:43:48.95#ibcon#flushed, iclass 18, count 0 2006.168.07:43:48.95#ibcon#about to write, iclass 18, count 0 2006.168.07:43:48.95#ibcon#wrote, iclass 18, count 0 2006.168.07:43:48.95#ibcon#about to read 3, iclass 18, count 0 2006.168.07:43:48.97#ibcon#read 3, iclass 18, count 0 2006.168.07:43:48.97#ibcon#about to read 4, iclass 18, count 0 2006.168.07:43:48.97#ibcon#read 4, iclass 18, count 0 2006.168.07:43:48.97#ibcon#about to read 5, iclass 18, count 0 2006.168.07:43:48.97#ibcon#read 5, iclass 18, count 0 2006.168.07:43:48.97#ibcon#about to read 6, iclass 18, count 0 2006.168.07:43:48.97#ibcon#read 6, iclass 18, count 0 2006.168.07:43:48.97#ibcon#end of sib2, iclass 18, count 0 2006.168.07:43:48.97#ibcon#*mode == 0, iclass 18, count 0 2006.168.07:43:48.97#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.07:43:48.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.07:43:48.97#ibcon#*before write, iclass 18, count 0 2006.168.07:43:48.97#ibcon#enter sib2, iclass 18, count 0 2006.168.07:43:48.97#ibcon#flushed, iclass 18, count 0 2006.168.07:43:48.97#ibcon#about to write, iclass 18, count 0 2006.168.07:43:48.97#ibcon#wrote, iclass 18, count 0 2006.168.07:43:48.97#ibcon#about to read 3, iclass 18, count 0 2006.168.07:43:49.01#ibcon#read 3, iclass 18, count 0 2006.168.07:43:49.01#ibcon#about to read 4, iclass 18, count 0 2006.168.07:43:49.01#ibcon#read 4, iclass 18, count 0 2006.168.07:43:49.01#ibcon#about to read 5, iclass 18, count 0 2006.168.07:43:49.01#ibcon#read 5, iclass 18, count 0 2006.168.07:43:49.01#ibcon#about to read 6, iclass 18, count 0 2006.168.07:43:49.01#ibcon#read 6, iclass 18, count 0 2006.168.07:43:49.01#ibcon#end of sib2, iclass 18, count 0 2006.168.07:43:49.01#ibcon#*after write, iclass 18, count 0 2006.168.07:43:49.01#ibcon#*before return 0, iclass 18, count 0 2006.168.07:43:49.01#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:43:49.01#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:43:49.01#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.07:43:49.01#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.07:43:49.01$vc4f8/va=4,7 2006.168.07:43:49.01#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.168.07:43:49.01#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.168.07:43:49.01#ibcon#ireg 11 cls_cnt 2 2006.168.07:43:49.01#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:43:49.07#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:43:49.07#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:43:49.07#ibcon#enter wrdev, iclass 20, count 2 2006.168.07:43:49.07#ibcon#first serial, iclass 20, count 2 2006.168.07:43:49.07#ibcon#enter sib2, iclass 20, count 2 2006.168.07:43:49.07#ibcon#flushed, iclass 20, count 2 2006.168.07:43:49.07#ibcon#about to write, iclass 20, count 2 2006.168.07:43:49.07#ibcon#wrote, iclass 20, count 2 2006.168.07:43:49.07#ibcon#about to read 3, iclass 20, count 2 2006.168.07:43:49.09#ibcon#read 3, iclass 20, count 2 2006.168.07:43:49.09#ibcon#about to read 4, iclass 20, count 2 2006.168.07:43:49.09#ibcon#read 4, iclass 20, count 2 2006.168.07:43:49.09#ibcon#about to read 5, iclass 20, count 2 2006.168.07:43:49.09#ibcon#read 5, iclass 20, count 2 2006.168.07:43:49.09#ibcon#about to read 6, iclass 20, count 2 2006.168.07:43:49.09#ibcon#read 6, iclass 20, count 2 2006.168.07:43:49.09#ibcon#end of sib2, iclass 20, count 2 2006.168.07:43:49.09#ibcon#*mode == 0, iclass 20, count 2 2006.168.07:43:49.09#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.168.07:43:49.09#ibcon#[25=AT04-07\r\n] 2006.168.07:43:49.09#ibcon#*before write, iclass 20, count 2 2006.168.07:43:49.09#ibcon#enter sib2, iclass 20, count 2 2006.168.07:43:49.09#ibcon#flushed, iclass 20, count 2 2006.168.07:43:49.09#ibcon#about to write, iclass 20, count 2 2006.168.07:43:49.09#ibcon#wrote, iclass 20, count 2 2006.168.07:43:49.09#ibcon#about to read 3, iclass 20, count 2 2006.168.07:43:49.12#ibcon#read 3, iclass 20, count 2 2006.168.07:43:49.12#ibcon#about to read 4, iclass 20, count 2 2006.168.07:43:49.12#ibcon#read 4, iclass 20, count 2 2006.168.07:43:49.12#ibcon#about to read 5, iclass 20, count 2 2006.168.07:43:49.12#ibcon#read 5, iclass 20, count 2 2006.168.07:43:49.12#ibcon#about to read 6, iclass 20, count 2 2006.168.07:43:49.12#ibcon#read 6, iclass 20, count 2 2006.168.07:43:49.12#ibcon#end of sib2, iclass 20, count 2 2006.168.07:43:49.12#ibcon#*after write, iclass 20, count 2 2006.168.07:43:49.12#ibcon#*before return 0, iclass 20, count 2 2006.168.07:43:49.12#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:43:49.12#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:43:49.12#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.168.07:43:49.12#ibcon#ireg 7 cls_cnt 0 2006.168.07:43:49.12#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:43:49.24#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:43:49.24#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:43:49.24#ibcon#enter wrdev, iclass 20, count 0 2006.168.07:43:49.24#ibcon#first serial, iclass 20, count 0 2006.168.07:43:49.24#ibcon#enter sib2, iclass 20, count 0 2006.168.07:43:49.24#ibcon#flushed, iclass 20, count 0 2006.168.07:43:49.24#ibcon#about to write, iclass 20, count 0 2006.168.07:43:49.24#ibcon#wrote, iclass 20, count 0 2006.168.07:43:49.24#ibcon#about to read 3, iclass 20, count 0 2006.168.07:43:49.26#ibcon#read 3, iclass 20, count 0 2006.168.07:43:49.26#ibcon#about to read 4, iclass 20, count 0 2006.168.07:43:49.26#ibcon#read 4, iclass 20, count 0 2006.168.07:43:49.26#ibcon#about to read 5, iclass 20, count 0 2006.168.07:43:49.26#ibcon#read 5, iclass 20, count 0 2006.168.07:43:49.26#ibcon#about to read 6, iclass 20, count 0 2006.168.07:43:49.26#ibcon#read 6, iclass 20, count 0 2006.168.07:43:49.26#ibcon#end of sib2, iclass 20, count 0 2006.168.07:43:49.26#ibcon#*mode == 0, iclass 20, count 0 2006.168.07:43:49.26#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.168.07:43:49.26#ibcon#[25=USB\r\n] 2006.168.07:43:49.26#ibcon#*before write, iclass 20, count 0 2006.168.07:43:49.26#ibcon#enter sib2, iclass 20, count 0 2006.168.07:43:49.26#ibcon#flushed, iclass 20, count 0 2006.168.07:43:49.26#ibcon#about to write, iclass 20, count 0 2006.168.07:43:49.26#ibcon#wrote, iclass 20, count 0 2006.168.07:43:49.26#ibcon#about to read 3, iclass 20, count 0 2006.168.07:43:49.29#ibcon#read 3, iclass 20, count 0 2006.168.07:43:49.29#ibcon#about to read 4, iclass 20, count 0 2006.168.07:43:49.29#ibcon#read 4, iclass 20, count 0 2006.168.07:43:49.29#ibcon#about to read 5, iclass 20, count 0 2006.168.07:43:49.29#ibcon#read 5, iclass 20, count 0 2006.168.07:43:49.29#ibcon#about to read 6, iclass 20, count 0 2006.168.07:43:49.29#ibcon#read 6, iclass 20, count 0 2006.168.07:43:49.29#ibcon#end of sib2, iclass 20, count 0 2006.168.07:43:49.29#ibcon#*after write, iclass 20, count 0 2006.168.07:43:49.29#ibcon#*before return 0, iclass 20, count 0 2006.168.07:43:49.29#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:43:49.29#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:43:49.29#ibcon#about to clear, iclass 20 cls_cnt 0 2006.168.07:43:49.29#ibcon#cleared, iclass 20 cls_cnt 0 2006.168.07:43:49.29$vc4f8/valo=5,652.99 2006.168.07:43:49.29#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.168.07:43:49.29#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.168.07:43:49.29#ibcon#ireg 17 cls_cnt 0 2006.168.07:43:49.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:43:49.29#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:43:49.29#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:43:49.29#ibcon#enter wrdev, iclass 22, count 0 2006.168.07:43:49.29#ibcon#first serial, iclass 22, count 0 2006.168.07:43:49.29#ibcon#enter sib2, iclass 22, count 0 2006.168.07:43:49.29#ibcon#flushed, iclass 22, count 0 2006.168.07:43:49.29#ibcon#about to write, iclass 22, count 0 2006.168.07:43:49.29#ibcon#wrote, iclass 22, count 0 2006.168.07:43:49.29#ibcon#about to read 3, iclass 22, count 0 2006.168.07:43:49.31#ibcon#read 3, iclass 22, count 0 2006.168.07:43:49.31#ibcon#about to read 4, iclass 22, count 0 2006.168.07:43:49.31#ibcon#read 4, iclass 22, count 0 2006.168.07:43:49.31#ibcon#about to read 5, iclass 22, count 0 2006.168.07:43:49.31#ibcon#read 5, iclass 22, count 0 2006.168.07:43:49.31#ibcon#about to read 6, iclass 22, count 0 2006.168.07:43:49.31#ibcon#read 6, iclass 22, count 0 2006.168.07:43:49.31#ibcon#end of sib2, iclass 22, count 0 2006.168.07:43:49.31#ibcon#*mode == 0, iclass 22, count 0 2006.168.07:43:49.31#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.168.07:43:49.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.07:43:49.31#ibcon#*before write, iclass 22, count 0 2006.168.07:43:49.31#ibcon#enter sib2, iclass 22, count 0 2006.168.07:43:49.31#ibcon#flushed, iclass 22, count 0 2006.168.07:43:49.31#ibcon#about to write, iclass 22, count 0 2006.168.07:43:49.31#ibcon#wrote, iclass 22, count 0 2006.168.07:43:49.31#ibcon#about to read 3, iclass 22, count 0 2006.168.07:43:49.35#ibcon#read 3, iclass 22, count 0 2006.168.07:43:49.35#ibcon#about to read 4, iclass 22, count 0 2006.168.07:43:49.35#ibcon#read 4, iclass 22, count 0 2006.168.07:43:49.35#ibcon#about to read 5, iclass 22, count 0 2006.168.07:43:49.35#ibcon#read 5, iclass 22, count 0 2006.168.07:43:49.35#ibcon#about to read 6, iclass 22, count 0 2006.168.07:43:49.35#ibcon#read 6, iclass 22, count 0 2006.168.07:43:49.35#ibcon#end of sib2, iclass 22, count 0 2006.168.07:43:49.35#ibcon#*after write, iclass 22, count 0 2006.168.07:43:49.35#ibcon#*before return 0, iclass 22, count 0 2006.168.07:43:49.35#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:43:49.35#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:43:49.35#ibcon#about to clear, iclass 22 cls_cnt 0 2006.168.07:43:49.35#ibcon#cleared, iclass 22 cls_cnt 0 2006.168.07:43:49.35$vc4f8/va=5,7 2006.168.07:43:49.35#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.168.07:43:49.35#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.168.07:43:49.35#ibcon#ireg 11 cls_cnt 2 2006.168.07:43:49.35#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:43:49.41#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:43:49.41#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:43:49.41#ibcon#enter wrdev, iclass 24, count 2 2006.168.07:43:49.41#ibcon#first serial, iclass 24, count 2 2006.168.07:43:49.41#ibcon#enter sib2, iclass 24, count 2 2006.168.07:43:49.41#ibcon#flushed, iclass 24, count 2 2006.168.07:43:49.41#ibcon#about to write, iclass 24, count 2 2006.168.07:43:49.41#ibcon#wrote, iclass 24, count 2 2006.168.07:43:49.41#ibcon#about to read 3, iclass 24, count 2 2006.168.07:43:49.43#ibcon#read 3, iclass 24, count 2 2006.168.07:43:49.43#ibcon#about to read 4, iclass 24, count 2 2006.168.07:43:49.43#ibcon#read 4, iclass 24, count 2 2006.168.07:43:49.43#ibcon#about to read 5, iclass 24, count 2 2006.168.07:43:49.43#ibcon#read 5, iclass 24, count 2 2006.168.07:43:49.43#ibcon#about to read 6, iclass 24, count 2 2006.168.07:43:49.43#ibcon#read 6, iclass 24, count 2 2006.168.07:43:49.43#ibcon#end of sib2, iclass 24, count 2 2006.168.07:43:49.43#ibcon#*mode == 0, iclass 24, count 2 2006.168.07:43:49.43#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.168.07:43:49.43#ibcon#[25=AT05-07\r\n] 2006.168.07:43:49.43#ibcon#*before write, iclass 24, count 2 2006.168.07:43:49.43#ibcon#enter sib2, iclass 24, count 2 2006.168.07:43:49.43#ibcon#flushed, iclass 24, count 2 2006.168.07:43:49.43#ibcon#about to write, iclass 24, count 2 2006.168.07:43:49.43#ibcon#wrote, iclass 24, count 2 2006.168.07:43:49.43#ibcon#about to read 3, iclass 24, count 2 2006.168.07:43:49.46#ibcon#read 3, iclass 24, count 2 2006.168.07:43:49.46#ibcon#about to read 4, iclass 24, count 2 2006.168.07:43:49.46#ibcon#read 4, iclass 24, count 2 2006.168.07:43:49.46#ibcon#about to read 5, iclass 24, count 2 2006.168.07:43:49.46#ibcon#read 5, iclass 24, count 2 2006.168.07:43:49.46#ibcon#about to read 6, iclass 24, count 2 2006.168.07:43:49.46#ibcon#read 6, iclass 24, count 2 2006.168.07:43:49.46#ibcon#end of sib2, iclass 24, count 2 2006.168.07:43:49.46#ibcon#*after write, iclass 24, count 2 2006.168.07:43:49.46#ibcon#*before return 0, iclass 24, count 2 2006.168.07:43:49.46#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:43:49.46#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:43:49.46#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.168.07:43:49.46#ibcon#ireg 7 cls_cnt 0 2006.168.07:43:49.46#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:43:49.58#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:43:49.58#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:43:49.58#ibcon#enter wrdev, iclass 24, count 0 2006.168.07:43:49.58#ibcon#first serial, iclass 24, count 0 2006.168.07:43:49.58#ibcon#enter sib2, iclass 24, count 0 2006.168.07:43:49.58#ibcon#flushed, iclass 24, count 0 2006.168.07:43:49.58#ibcon#about to write, iclass 24, count 0 2006.168.07:43:49.58#ibcon#wrote, iclass 24, count 0 2006.168.07:43:49.58#ibcon#about to read 3, iclass 24, count 0 2006.168.07:43:49.60#ibcon#read 3, iclass 24, count 0 2006.168.07:43:49.60#ibcon#about to read 4, iclass 24, count 0 2006.168.07:43:49.60#ibcon#read 4, iclass 24, count 0 2006.168.07:43:49.60#ibcon#about to read 5, iclass 24, count 0 2006.168.07:43:49.60#ibcon#read 5, iclass 24, count 0 2006.168.07:43:49.60#ibcon#about to read 6, iclass 24, count 0 2006.168.07:43:49.60#ibcon#read 6, iclass 24, count 0 2006.168.07:43:49.60#ibcon#end of sib2, iclass 24, count 0 2006.168.07:43:49.60#ibcon#*mode == 0, iclass 24, count 0 2006.168.07:43:49.60#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.168.07:43:49.60#ibcon#[25=USB\r\n] 2006.168.07:43:49.60#ibcon#*before write, iclass 24, count 0 2006.168.07:43:49.60#ibcon#enter sib2, iclass 24, count 0 2006.168.07:43:49.60#ibcon#flushed, iclass 24, count 0 2006.168.07:43:49.60#ibcon#about to write, iclass 24, count 0 2006.168.07:43:49.60#ibcon#wrote, iclass 24, count 0 2006.168.07:43:49.60#ibcon#about to read 3, iclass 24, count 0 2006.168.07:43:49.63#ibcon#read 3, iclass 24, count 0 2006.168.07:43:49.63#ibcon#about to read 4, iclass 24, count 0 2006.168.07:43:49.63#ibcon#read 4, iclass 24, count 0 2006.168.07:43:49.63#ibcon#about to read 5, iclass 24, count 0 2006.168.07:43:49.63#ibcon#read 5, iclass 24, count 0 2006.168.07:43:49.63#ibcon#about to read 6, iclass 24, count 0 2006.168.07:43:49.63#ibcon#read 6, iclass 24, count 0 2006.168.07:43:49.63#ibcon#end of sib2, iclass 24, count 0 2006.168.07:43:49.63#ibcon#*after write, iclass 24, count 0 2006.168.07:43:49.63#ibcon#*before return 0, iclass 24, count 0 2006.168.07:43:49.63#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:43:49.63#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:43:49.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.168.07:43:49.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.168.07:43:49.63$vc4f8/valo=6,772.99 2006.168.07:43:49.63#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.168.07:43:49.63#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.168.07:43:49.63#ibcon#ireg 17 cls_cnt 0 2006.168.07:43:49.63#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:43:49.63#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:43:49.63#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:43:49.63#ibcon#enter wrdev, iclass 26, count 0 2006.168.07:43:49.63#ibcon#first serial, iclass 26, count 0 2006.168.07:43:49.63#ibcon#enter sib2, iclass 26, count 0 2006.168.07:43:49.63#ibcon#flushed, iclass 26, count 0 2006.168.07:43:49.63#ibcon#about to write, iclass 26, count 0 2006.168.07:43:49.63#ibcon#wrote, iclass 26, count 0 2006.168.07:43:49.63#ibcon#about to read 3, iclass 26, count 0 2006.168.07:43:49.65#ibcon#read 3, iclass 26, count 0 2006.168.07:43:49.65#ibcon#about to read 4, iclass 26, count 0 2006.168.07:43:49.65#ibcon#read 4, iclass 26, count 0 2006.168.07:43:49.65#ibcon#about to read 5, iclass 26, count 0 2006.168.07:43:49.65#ibcon#read 5, iclass 26, count 0 2006.168.07:43:49.65#ibcon#about to read 6, iclass 26, count 0 2006.168.07:43:49.65#ibcon#read 6, iclass 26, count 0 2006.168.07:43:49.65#ibcon#end of sib2, iclass 26, count 0 2006.168.07:43:49.65#ibcon#*mode == 0, iclass 26, count 0 2006.168.07:43:49.65#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.168.07:43:49.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.07:43:49.65#ibcon#*before write, iclass 26, count 0 2006.168.07:43:49.65#ibcon#enter sib2, iclass 26, count 0 2006.168.07:43:49.65#ibcon#flushed, iclass 26, count 0 2006.168.07:43:49.65#ibcon#about to write, iclass 26, count 0 2006.168.07:43:49.65#ibcon#wrote, iclass 26, count 0 2006.168.07:43:49.65#ibcon#about to read 3, iclass 26, count 0 2006.168.07:43:49.69#ibcon#read 3, iclass 26, count 0 2006.168.07:43:49.69#ibcon#about to read 4, iclass 26, count 0 2006.168.07:43:49.69#ibcon#read 4, iclass 26, count 0 2006.168.07:43:49.69#ibcon#about to read 5, iclass 26, count 0 2006.168.07:43:49.69#ibcon#read 5, iclass 26, count 0 2006.168.07:43:49.69#ibcon#about to read 6, iclass 26, count 0 2006.168.07:43:49.69#ibcon#read 6, iclass 26, count 0 2006.168.07:43:49.69#ibcon#end of sib2, iclass 26, count 0 2006.168.07:43:49.69#ibcon#*after write, iclass 26, count 0 2006.168.07:43:49.69#ibcon#*before return 0, iclass 26, count 0 2006.168.07:43:49.69#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:43:49.69#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:43:49.69#ibcon#about to clear, iclass 26 cls_cnt 0 2006.168.07:43:49.69#ibcon#cleared, iclass 26 cls_cnt 0 2006.168.07:43:49.69$vc4f8/va=6,6 2006.168.07:43:49.69#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.168.07:43:49.69#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.168.07:43:49.69#ibcon#ireg 11 cls_cnt 2 2006.168.07:43:49.69#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.168.07:43:49.75#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.168.07:43:49.75#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.168.07:43:49.75#ibcon#enter wrdev, iclass 28, count 2 2006.168.07:43:49.75#ibcon#first serial, iclass 28, count 2 2006.168.07:43:49.75#ibcon#enter sib2, iclass 28, count 2 2006.168.07:43:49.75#ibcon#flushed, iclass 28, count 2 2006.168.07:43:49.75#ibcon#about to write, iclass 28, count 2 2006.168.07:43:49.75#ibcon#wrote, iclass 28, count 2 2006.168.07:43:49.75#ibcon#about to read 3, iclass 28, count 2 2006.168.07:43:49.77#ibcon#read 3, iclass 28, count 2 2006.168.07:43:49.77#ibcon#about to read 4, iclass 28, count 2 2006.168.07:43:49.77#ibcon#read 4, iclass 28, count 2 2006.168.07:43:49.77#ibcon#about to read 5, iclass 28, count 2 2006.168.07:43:49.77#ibcon#read 5, iclass 28, count 2 2006.168.07:43:49.77#ibcon#about to read 6, iclass 28, count 2 2006.168.07:43:49.77#ibcon#read 6, iclass 28, count 2 2006.168.07:43:49.77#ibcon#end of sib2, iclass 28, count 2 2006.168.07:43:49.77#ibcon#*mode == 0, iclass 28, count 2 2006.168.07:43:49.77#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.168.07:43:49.77#ibcon#[25=AT06-06\r\n] 2006.168.07:43:49.77#ibcon#*before write, iclass 28, count 2 2006.168.07:43:49.77#ibcon#enter sib2, iclass 28, count 2 2006.168.07:43:49.77#ibcon#flushed, iclass 28, count 2 2006.168.07:43:49.77#ibcon#about to write, iclass 28, count 2 2006.168.07:43:49.77#ibcon#wrote, iclass 28, count 2 2006.168.07:43:49.77#ibcon#about to read 3, iclass 28, count 2 2006.168.07:43:49.80#ibcon#read 3, iclass 28, count 2 2006.168.07:43:49.80#ibcon#about to read 4, iclass 28, count 2 2006.168.07:43:49.80#ibcon#read 4, iclass 28, count 2 2006.168.07:43:49.80#ibcon#about to read 5, iclass 28, count 2 2006.168.07:43:49.80#ibcon#read 5, iclass 28, count 2 2006.168.07:43:49.80#ibcon#about to read 6, iclass 28, count 2 2006.168.07:43:49.80#ibcon#read 6, iclass 28, count 2 2006.168.07:43:49.80#ibcon#end of sib2, iclass 28, count 2 2006.168.07:43:49.80#ibcon#*after write, iclass 28, count 2 2006.168.07:43:49.80#ibcon#*before return 0, iclass 28, count 2 2006.168.07:43:49.80#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.168.07:43:49.80#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.168.07:43:49.80#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.168.07:43:49.80#ibcon#ireg 7 cls_cnt 0 2006.168.07:43:49.80#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.168.07:43:49.92#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.168.07:43:49.92#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.168.07:43:49.92#ibcon#enter wrdev, iclass 28, count 0 2006.168.07:43:49.92#ibcon#first serial, iclass 28, count 0 2006.168.07:43:49.92#ibcon#enter sib2, iclass 28, count 0 2006.168.07:43:49.92#ibcon#flushed, iclass 28, count 0 2006.168.07:43:49.92#ibcon#about to write, iclass 28, count 0 2006.168.07:43:49.92#ibcon#wrote, iclass 28, count 0 2006.168.07:43:49.92#ibcon#about to read 3, iclass 28, count 0 2006.168.07:43:49.94#ibcon#read 3, iclass 28, count 0 2006.168.07:43:49.94#ibcon#about to read 4, iclass 28, count 0 2006.168.07:43:49.94#ibcon#read 4, iclass 28, count 0 2006.168.07:43:49.94#ibcon#about to read 5, iclass 28, count 0 2006.168.07:43:49.94#ibcon#read 5, iclass 28, count 0 2006.168.07:43:49.94#ibcon#about to read 6, iclass 28, count 0 2006.168.07:43:49.94#ibcon#read 6, iclass 28, count 0 2006.168.07:43:49.94#ibcon#end of sib2, iclass 28, count 0 2006.168.07:43:49.94#ibcon#*mode == 0, iclass 28, count 0 2006.168.07:43:49.94#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.168.07:43:49.94#ibcon#[25=USB\r\n] 2006.168.07:43:49.94#ibcon#*before write, iclass 28, count 0 2006.168.07:43:49.94#ibcon#enter sib2, iclass 28, count 0 2006.168.07:43:49.94#ibcon#flushed, iclass 28, count 0 2006.168.07:43:49.94#ibcon#about to write, iclass 28, count 0 2006.168.07:43:49.94#ibcon#wrote, iclass 28, count 0 2006.168.07:43:49.94#ibcon#about to read 3, iclass 28, count 0 2006.168.07:43:49.97#ibcon#read 3, iclass 28, count 0 2006.168.07:43:49.97#ibcon#about to read 4, iclass 28, count 0 2006.168.07:43:49.97#ibcon#read 4, iclass 28, count 0 2006.168.07:43:49.97#ibcon#about to read 5, iclass 28, count 0 2006.168.07:43:49.97#ibcon#read 5, iclass 28, count 0 2006.168.07:43:49.97#ibcon#about to read 6, iclass 28, count 0 2006.168.07:43:49.97#ibcon#read 6, iclass 28, count 0 2006.168.07:43:49.97#ibcon#end of sib2, iclass 28, count 0 2006.168.07:43:49.97#ibcon#*after write, iclass 28, count 0 2006.168.07:43:49.97#ibcon#*before return 0, iclass 28, count 0 2006.168.07:43:49.97#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.168.07:43:49.97#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.168.07:43:49.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.168.07:43:49.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.168.07:43:49.97$vc4f8/valo=7,832.99 2006.168.07:43:49.97#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.168.07:43:49.97#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.168.07:43:49.97#ibcon#ireg 17 cls_cnt 0 2006.168.07:43:49.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:43:49.97#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:43:49.97#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:43:49.97#ibcon#enter wrdev, iclass 30, count 0 2006.168.07:43:49.97#ibcon#first serial, iclass 30, count 0 2006.168.07:43:49.97#ibcon#enter sib2, iclass 30, count 0 2006.168.07:43:49.97#ibcon#flushed, iclass 30, count 0 2006.168.07:43:49.97#ibcon#about to write, iclass 30, count 0 2006.168.07:43:49.97#ibcon#wrote, iclass 30, count 0 2006.168.07:43:49.97#ibcon#about to read 3, iclass 30, count 0 2006.168.07:43:49.99#ibcon#read 3, iclass 30, count 0 2006.168.07:43:49.99#ibcon#about to read 4, iclass 30, count 0 2006.168.07:43:49.99#ibcon#read 4, iclass 30, count 0 2006.168.07:43:49.99#ibcon#about to read 5, iclass 30, count 0 2006.168.07:43:49.99#ibcon#read 5, iclass 30, count 0 2006.168.07:43:49.99#ibcon#about to read 6, iclass 30, count 0 2006.168.07:43:49.99#ibcon#read 6, iclass 30, count 0 2006.168.07:43:49.99#ibcon#end of sib2, iclass 30, count 0 2006.168.07:43:49.99#ibcon#*mode == 0, iclass 30, count 0 2006.168.07:43:49.99#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.168.07:43:49.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.07:43:49.99#ibcon#*before write, iclass 30, count 0 2006.168.07:43:49.99#ibcon#enter sib2, iclass 30, count 0 2006.168.07:43:49.99#ibcon#flushed, iclass 30, count 0 2006.168.07:43:49.99#ibcon#about to write, iclass 30, count 0 2006.168.07:43:49.99#ibcon#wrote, iclass 30, count 0 2006.168.07:43:49.99#ibcon#about to read 3, iclass 30, count 0 2006.168.07:43:50.03#ibcon#read 3, iclass 30, count 0 2006.168.07:43:50.03#ibcon#about to read 4, iclass 30, count 0 2006.168.07:43:50.03#ibcon#read 4, iclass 30, count 0 2006.168.07:43:50.03#ibcon#about to read 5, iclass 30, count 0 2006.168.07:43:50.03#ibcon#read 5, iclass 30, count 0 2006.168.07:43:50.03#ibcon#about to read 6, iclass 30, count 0 2006.168.07:43:50.03#ibcon#read 6, iclass 30, count 0 2006.168.07:43:50.03#ibcon#end of sib2, iclass 30, count 0 2006.168.07:43:50.03#ibcon#*after write, iclass 30, count 0 2006.168.07:43:50.03#ibcon#*before return 0, iclass 30, count 0 2006.168.07:43:50.03#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:43:50.03#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:43:50.03#ibcon#about to clear, iclass 30 cls_cnt 0 2006.168.07:43:50.03#ibcon#cleared, iclass 30 cls_cnt 0 2006.168.07:43:50.03$vc4f8/va=7,6 2006.168.07:43:50.03#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.168.07:43:50.03#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.168.07:43:50.03#ibcon#ireg 11 cls_cnt 2 2006.168.07:43:50.03#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:43:50.09#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:43:50.09#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:43:50.09#ibcon#enter wrdev, iclass 32, count 2 2006.168.07:43:50.09#ibcon#first serial, iclass 32, count 2 2006.168.07:43:50.09#ibcon#enter sib2, iclass 32, count 2 2006.168.07:43:50.09#ibcon#flushed, iclass 32, count 2 2006.168.07:43:50.09#ibcon#about to write, iclass 32, count 2 2006.168.07:43:50.09#ibcon#wrote, iclass 32, count 2 2006.168.07:43:50.09#ibcon#about to read 3, iclass 32, count 2 2006.168.07:43:50.11#ibcon#read 3, iclass 32, count 2 2006.168.07:43:50.11#ibcon#about to read 4, iclass 32, count 2 2006.168.07:43:50.11#ibcon#read 4, iclass 32, count 2 2006.168.07:43:50.11#ibcon#about to read 5, iclass 32, count 2 2006.168.07:43:50.11#ibcon#read 5, iclass 32, count 2 2006.168.07:43:50.11#ibcon#about to read 6, iclass 32, count 2 2006.168.07:43:50.11#ibcon#read 6, iclass 32, count 2 2006.168.07:43:50.11#ibcon#end of sib2, iclass 32, count 2 2006.168.07:43:50.11#ibcon#*mode == 0, iclass 32, count 2 2006.168.07:43:50.11#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.168.07:43:50.11#ibcon#[25=AT07-06\r\n] 2006.168.07:43:50.11#ibcon#*before write, iclass 32, count 2 2006.168.07:43:50.11#ibcon#enter sib2, iclass 32, count 2 2006.168.07:43:50.11#ibcon#flushed, iclass 32, count 2 2006.168.07:43:50.11#ibcon#about to write, iclass 32, count 2 2006.168.07:43:50.11#ibcon#wrote, iclass 32, count 2 2006.168.07:43:50.11#ibcon#about to read 3, iclass 32, count 2 2006.168.07:43:50.14#ibcon#read 3, iclass 32, count 2 2006.168.07:43:50.14#ibcon#about to read 4, iclass 32, count 2 2006.168.07:43:50.14#ibcon#read 4, iclass 32, count 2 2006.168.07:43:50.14#ibcon#about to read 5, iclass 32, count 2 2006.168.07:43:50.14#ibcon#read 5, iclass 32, count 2 2006.168.07:43:50.14#ibcon#about to read 6, iclass 32, count 2 2006.168.07:43:50.14#ibcon#read 6, iclass 32, count 2 2006.168.07:43:50.14#ibcon#end of sib2, iclass 32, count 2 2006.168.07:43:50.14#ibcon#*after write, iclass 32, count 2 2006.168.07:43:50.14#ibcon#*before return 0, iclass 32, count 2 2006.168.07:43:50.14#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:43:50.14#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:43:50.14#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.168.07:43:50.14#ibcon#ireg 7 cls_cnt 0 2006.168.07:43:50.14#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:43:50.26#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:43:50.26#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:43:50.26#ibcon#enter wrdev, iclass 32, count 0 2006.168.07:43:50.26#ibcon#first serial, iclass 32, count 0 2006.168.07:43:50.26#ibcon#enter sib2, iclass 32, count 0 2006.168.07:43:50.26#ibcon#flushed, iclass 32, count 0 2006.168.07:43:50.26#ibcon#about to write, iclass 32, count 0 2006.168.07:43:50.26#ibcon#wrote, iclass 32, count 0 2006.168.07:43:50.26#ibcon#about to read 3, iclass 32, count 0 2006.168.07:43:50.28#ibcon#read 3, iclass 32, count 0 2006.168.07:43:50.28#ibcon#about to read 4, iclass 32, count 0 2006.168.07:43:50.28#ibcon#read 4, iclass 32, count 0 2006.168.07:43:50.28#ibcon#about to read 5, iclass 32, count 0 2006.168.07:43:50.28#ibcon#read 5, iclass 32, count 0 2006.168.07:43:50.28#ibcon#about to read 6, iclass 32, count 0 2006.168.07:43:50.28#ibcon#read 6, iclass 32, count 0 2006.168.07:43:50.28#ibcon#end of sib2, iclass 32, count 0 2006.168.07:43:50.28#ibcon#*mode == 0, iclass 32, count 0 2006.168.07:43:50.28#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.168.07:43:50.28#ibcon#[25=USB\r\n] 2006.168.07:43:50.28#ibcon#*before write, iclass 32, count 0 2006.168.07:43:50.28#ibcon#enter sib2, iclass 32, count 0 2006.168.07:43:50.28#ibcon#flushed, iclass 32, count 0 2006.168.07:43:50.28#ibcon#about to write, iclass 32, count 0 2006.168.07:43:50.28#ibcon#wrote, iclass 32, count 0 2006.168.07:43:50.28#ibcon#about to read 3, iclass 32, count 0 2006.168.07:43:50.31#ibcon#read 3, iclass 32, count 0 2006.168.07:43:50.31#ibcon#about to read 4, iclass 32, count 0 2006.168.07:43:50.31#ibcon#read 4, iclass 32, count 0 2006.168.07:43:50.31#ibcon#about to read 5, iclass 32, count 0 2006.168.07:43:50.31#ibcon#read 5, iclass 32, count 0 2006.168.07:43:50.31#ibcon#about to read 6, iclass 32, count 0 2006.168.07:43:50.31#ibcon#read 6, iclass 32, count 0 2006.168.07:43:50.31#ibcon#end of sib2, iclass 32, count 0 2006.168.07:43:50.31#ibcon#*after write, iclass 32, count 0 2006.168.07:43:50.31#ibcon#*before return 0, iclass 32, count 0 2006.168.07:43:50.31#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:43:50.31#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:43:50.31#ibcon#about to clear, iclass 32 cls_cnt 0 2006.168.07:43:50.31#ibcon#cleared, iclass 32 cls_cnt 0 2006.168.07:43:50.31$vc4f8/valo=8,852.99 2006.168.07:43:50.31#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.168.07:43:50.31#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.168.07:43:50.31#ibcon#ireg 17 cls_cnt 0 2006.168.07:43:50.31#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:43:50.31#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:43:50.31#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:43:50.31#ibcon#enter wrdev, iclass 34, count 0 2006.168.07:43:50.31#ibcon#first serial, iclass 34, count 0 2006.168.07:43:50.31#ibcon#enter sib2, iclass 34, count 0 2006.168.07:43:50.31#ibcon#flushed, iclass 34, count 0 2006.168.07:43:50.31#ibcon#about to write, iclass 34, count 0 2006.168.07:43:50.31#ibcon#wrote, iclass 34, count 0 2006.168.07:43:50.31#ibcon#about to read 3, iclass 34, count 0 2006.168.07:43:50.33#ibcon#read 3, iclass 34, count 0 2006.168.07:43:50.33#ibcon#about to read 4, iclass 34, count 0 2006.168.07:43:50.33#ibcon#read 4, iclass 34, count 0 2006.168.07:43:50.33#ibcon#about to read 5, iclass 34, count 0 2006.168.07:43:50.33#ibcon#read 5, iclass 34, count 0 2006.168.07:43:50.33#ibcon#about to read 6, iclass 34, count 0 2006.168.07:43:50.33#ibcon#read 6, iclass 34, count 0 2006.168.07:43:50.33#ibcon#end of sib2, iclass 34, count 0 2006.168.07:43:50.33#ibcon#*mode == 0, iclass 34, count 0 2006.168.07:43:50.33#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.168.07:43:50.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.07:43:50.33#ibcon#*before write, iclass 34, count 0 2006.168.07:43:50.33#ibcon#enter sib2, iclass 34, count 0 2006.168.07:43:50.33#ibcon#flushed, iclass 34, count 0 2006.168.07:43:50.33#ibcon#about to write, iclass 34, count 0 2006.168.07:43:50.33#ibcon#wrote, iclass 34, count 0 2006.168.07:43:50.33#ibcon#about to read 3, iclass 34, count 0 2006.168.07:43:50.37#ibcon#read 3, iclass 34, count 0 2006.168.07:43:50.37#ibcon#about to read 4, iclass 34, count 0 2006.168.07:43:50.37#ibcon#read 4, iclass 34, count 0 2006.168.07:43:50.37#ibcon#about to read 5, iclass 34, count 0 2006.168.07:43:50.37#ibcon#read 5, iclass 34, count 0 2006.168.07:43:50.37#ibcon#about to read 6, iclass 34, count 0 2006.168.07:43:50.37#ibcon#read 6, iclass 34, count 0 2006.168.07:43:50.37#ibcon#end of sib2, iclass 34, count 0 2006.168.07:43:50.37#ibcon#*after write, iclass 34, count 0 2006.168.07:43:50.37#ibcon#*before return 0, iclass 34, count 0 2006.168.07:43:50.37#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:43:50.37#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:43:50.37#ibcon#about to clear, iclass 34 cls_cnt 0 2006.168.07:43:50.37#ibcon#cleared, iclass 34 cls_cnt 0 2006.168.07:43:50.37$vc4f8/va=8,7 2006.168.07:43:50.37#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.168.07:43:50.37#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.168.07:43:50.37#ibcon#ireg 11 cls_cnt 2 2006.168.07:43:50.37#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:43:50.43#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:43:50.43#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:43:50.43#ibcon#enter wrdev, iclass 36, count 2 2006.168.07:43:50.43#ibcon#first serial, iclass 36, count 2 2006.168.07:43:50.43#ibcon#enter sib2, iclass 36, count 2 2006.168.07:43:50.43#ibcon#flushed, iclass 36, count 2 2006.168.07:43:50.43#ibcon#about to write, iclass 36, count 2 2006.168.07:43:50.43#ibcon#wrote, iclass 36, count 2 2006.168.07:43:50.43#ibcon#about to read 3, iclass 36, count 2 2006.168.07:43:50.45#ibcon#read 3, iclass 36, count 2 2006.168.07:43:50.45#ibcon#about to read 4, iclass 36, count 2 2006.168.07:43:50.45#ibcon#read 4, iclass 36, count 2 2006.168.07:43:50.45#ibcon#about to read 5, iclass 36, count 2 2006.168.07:43:50.45#ibcon#read 5, iclass 36, count 2 2006.168.07:43:50.45#ibcon#about to read 6, iclass 36, count 2 2006.168.07:43:50.45#ibcon#read 6, iclass 36, count 2 2006.168.07:43:50.45#ibcon#end of sib2, iclass 36, count 2 2006.168.07:43:50.45#ibcon#*mode == 0, iclass 36, count 2 2006.168.07:43:50.45#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.168.07:43:50.45#ibcon#[25=AT08-07\r\n] 2006.168.07:43:50.45#ibcon#*before write, iclass 36, count 2 2006.168.07:43:50.45#ibcon#enter sib2, iclass 36, count 2 2006.168.07:43:50.45#ibcon#flushed, iclass 36, count 2 2006.168.07:43:50.45#ibcon#about to write, iclass 36, count 2 2006.168.07:43:50.45#ibcon#wrote, iclass 36, count 2 2006.168.07:43:50.45#ibcon#about to read 3, iclass 36, count 2 2006.168.07:43:50.49#ibcon#read 3, iclass 36, count 2 2006.168.07:43:50.49#ibcon#about to read 4, iclass 36, count 2 2006.168.07:43:50.49#ibcon#read 4, iclass 36, count 2 2006.168.07:43:50.49#ibcon#about to read 5, iclass 36, count 2 2006.168.07:43:50.49#ibcon#read 5, iclass 36, count 2 2006.168.07:43:50.49#ibcon#about to read 6, iclass 36, count 2 2006.168.07:43:50.49#ibcon#read 6, iclass 36, count 2 2006.168.07:43:50.49#ibcon#end of sib2, iclass 36, count 2 2006.168.07:43:50.49#ibcon#*after write, iclass 36, count 2 2006.168.07:43:50.49#ibcon#*before return 0, iclass 36, count 2 2006.168.07:43:50.49#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:43:50.49#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:43:50.49#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.168.07:43:50.49#ibcon#ireg 7 cls_cnt 0 2006.168.07:43:50.49#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:43:50.61#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:43:50.61#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:43:50.61#ibcon#enter wrdev, iclass 36, count 0 2006.168.07:43:50.61#ibcon#first serial, iclass 36, count 0 2006.168.07:43:50.61#ibcon#enter sib2, iclass 36, count 0 2006.168.07:43:50.61#ibcon#flushed, iclass 36, count 0 2006.168.07:43:50.61#ibcon#about to write, iclass 36, count 0 2006.168.07:43:50.61#ibcon#wrote, iclass 36, count 0 2006.168.07:43:50.61#ibcon#about to read 3, iclass 36, count 0 2006.168.07:43:50.63#ibcon#read 3, iclass 36, count 0 2006.168.07:43:50.63#ibcon#about to read 4, iclass 36, count 0 2006.168.07:43:50.63#ibcon#read 4, iclass 36, count 0 2006.168.07:43:50.63#ibcon#about to read 5, iclass 36, count 0 2006.168.07:43:50.63#ibcon#read 5, iclass 36, count 0 2006.168.07:43:50.63#ibcon#about to read 6, iclass 36, count 0 2006.168.07:43:50.63#ibcon#read 6, iclass 36, count 0 2006.168.07:43:50.63#ibcon#end of sib2, iclass 36, count 0 2006.168.07:43:50.63#ibcon#*mode == 0, iclass 36, count 0 2006.168.07:43:50.63#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.168.07:43:50.63#ibcon#[25=USB\r\n] 2006.168.07:43:50.63#ibcon#*before write, iclass 36, count 0 2006.168.07:43:50.63#ibcon#enter sib2, iclass 36, count 0 2006.168.07:43:50.63#ibcon#flushed, iclass 36, count 0 2006.168.07:43:50.63#ibcon#about to write, iclass 36, count 0 2006.168.07:43:50.63#ibcon#wrote, iclass 36, count 0 2006.168.07:43:50.63#ibcon#about to read 3, iclass 36, count 0 2006.168.07:43:50.66#ibcon#read 3, iclass 36, count 0 2006.168.07:43:50.66#ibcon#about to read 4, iclass 36, count 0 2006.168.07:43:50.66#ibcon#read 4, iclass 36, count 0 2006.168.07:43:50.66#ibcon#about to read 5, iclass 36, count 0 2006.168.07:43:50.66#ibcon#read 5, iclass 36, count 0 2006.168.07:43:50.66#ibcon#about to read 6, iclass 36, count 0 2006.168.07:43:50.66#ibcon#read 6, iclass 36, count 0 2006.168.07:43:50.66#ibcon#end of sib2, iclass 36, count 0 2006.168.07:43:50.66#ibcon#*after write, iclass 36, count 0 2006.168.07:43:50.66#ibcon#*before return 0, iclass 36, count 0 2006.168.07:43:50.66#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:43:50.66#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:43:50.66#ibcon#about to clear, iclass 36 cls_cnt 0 2006.168.07:43:50.66#ibcon#cleared, iclass 36 cls_cnt 0 2006.168.07:43:50.66$vc4f8/vblo=1,632.99 2006.168.07:43:50.66#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.168.07:43:50.66#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.168.07:43:50.66#ibcon#ireg 17 cls_cnt 0 2006.168.07:43:50.66#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:43:50.66#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:43:50.66#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:43:50.66#ibcon#enter wrdev, iclass 38, count 0 2006.168.07:43:50.66#ibcon#first serial, iclass 38, count 0 2006.168.07:43:50.66#ibcon#enter sib2, iclass 38, count 0 2006.168.07:43:50.66#ibcon#flushed, iclass 38, count 0 2006.168.07:43:50.66#ibcon#about to write, iclass 38, count 0 2006.168.07:43:50.66#ibcon#wrote, iclass 38, count 0 2006.168.07:43:50.66#ibcon#about to read 3, iclass 38, count 0 2006.168.07:43:50.68#ibcon#read 3, iclass 38, count 0 2006.168.07:43:50.68#ibcon#about to read 4, iclass 38, count 0 2006.168.07:43:50.68#ibcon#read 4, iclass 38, count 0 2006.168.07:43:50.68#ibcon#about to read 5, iclass 38, count 0 2006.168.07:43:50.68#ibcon#read 5, iclass 38, count 0 2006.168.07:43:50.68#ibcon#about to read 6, iclass 38, count 0 2006.168.07:43:50.68#ibcon#read 6, iclass 38, count 0 2006.168.07:43:50.68#ibcon#end of sib2, iclass 38, count 0 2006.168.07:43:50.68#ibcon#*mode == 0, iclass 38, count 0 2006.168.07:43:50.68#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.168.07:43:50.68#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.07:43:50.68#ibcon#*before write, iclass 38, count 0 2006.168.07:43:50.68#ibcon#enter sib2, iclass 38, count 0 2006.168.07:43:50.68#ibcon#flushed, iclass 38, count 0 2006.168.07:43:50.68#ibcon#about to write, iclass 38, count 0 2006.168.07:43:50.68#ibcon#wrote, iclass 38, count 0 2006.168.07:43:50.68#ibcon#about to read 3, iclass 38, count 0 2006.168.07:43:50.72#ibcon#read 3, iclass 38, count 0 2006.168.07:43:50.72#ibcon#about to read 4, iclass 38, count 0 2006.168.07:43:50.72#ibcon#read 4, iclass 38, count 0 2006.168.07:43:50.72#ibcon#about to read 5, iclass 38, count 0 2006.168.07:43:50.72#ibcon#read 5, iclass 38, count 0 2006.168.07:43:50.72#ibcon#about to read 6, iclass 38, count 0 2006.168.07:43:50.72#ibcon#read 6, iclass 38, count 0 2006.168.07:43:50.72#ibcon#end of sib2, iclass 38, count 0 2006.168.07:43:50.72#ibcon#*after write, iclass 38, count 0 2006.168.07:43:50.72#ibcon#*before return 0, iclass 38, count 0 2006.168.07:43:50.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:43:50.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:43:50.72#ibcon#about to clear, iclass 38 cls_cnt 0 2006.168.07:43:50.72#ibcon#cleared, iclass 38 cls_cnt 0 2006.168.07:43:50.72$vc4f8/vb=1,4 2006.168.07:43:50.72#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.168.07:43:50.72#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.168.07:43:50.72#ibcon#ireg 11 cls_cnt 2 2006.168.07:43:50.72#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:43:50.72#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:43:50.72#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:43:50.72#ibcon#enter wrdev, iclass 40, count 2 2006.168.07:43:50.72#ibcon#first serial, iclass 40, count 2 2006.168.07:43:50.72#ibcon#enter sib2, iclass 40, count 2 2006.168.07:43:50.72#ibcon#flushed, iclass 40, count 2 2006.168.07:43:50.72#ibcon#about to write, iclass 40, count 2 2006.168.07:43:50.72#ibcon#wrote, iclass 40, count 2 2006.168.07:43:50.72#ibcon#about to read 3, iclass 40, count 2 2006.168.07:43:50.74#ibcon#read 3, iclass 40, count 2 2006.168.07:43:50.74#ibcon#about to read 4, iclass 40, count 2 2006.168.07:43:50.74#ibcon#read 4, iclass 40, count 2 2006.168.07:43:50.74#ibcon#about to read 5, iclass 40, count 2 2006.168.07:43:50.74#ibcon#read 5, iclass 40, count 2 2006.168.07:43:50.74#ibcon#about to read 6, iclass 40, count 2 2006.168.07:43:50.74#ibcon#read 6, iclass 40, count 2 2006.168.07:43:50.74#ibcon#end of sib2, iclass 40, count 2 2006.168.07:43:50.74#ibcon#*mode == 0, iclass 40, count 2 2006.168.07:43:50.74#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.168.07:43:50.74#ibcon#[27=AT01-04\r\n] 2006.168.07:43:50.74#ibcon#*before write, iclass 40, count 2 2006.168.07:43:50.74#ibcon#enter sib2, iclass 40, count 2 2006.168.07:43:50.74#ibcon#flushed, iclass 40, count 2 2006.168.07:43:50.74#ibcon#about to write, iclass 40, count 2 2006.168.07:43:50.74#ibcon#wrote, iclass 40, count 2 2006.168.07:43:50.74#ibcon#about to read 3, iclass 40, count 2 2006.168.07:43:50.77#ibcon#read 3, iclass 40, count 2 2006.168.07:43:50.77#ibcon#about to read 4, iclass 40, count 2 2006.168.07:43:50.77#ibcon#read 4, iclass 40, count 2 2006.168.07:43:50.77#ibcon#about to read 5, iclass 40, count 2 2006.168.07:43:50.77#ibcon#read 5, iclass 40, count 2 2006.168.07:43:50.77#ibcon#about to read 6, iclass 40, count 2 2006.168.07:43:50.77#ibcon#read 6, iclass 40, count 2 2006.168.07:43:50.77#ibcon#end of sib2, iclass 40, count 2 2006.168.07:43:50.77#ibcon#*after write, iclass 40, count 2 2006.168.07:43:50.77#ibcon#*before return 0, iclass 40, count 2 2006.168.07:43:50.77#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:43:50.77#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:43:50.77#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.168.07:43:50.77#ibcon#ireg 7 cls_cnt 0 2006.168.07:43:50.77#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:43:50.89#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:43:50.89#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:43:50.89#ibcon#enter wrdev, iclass 40, count 0 2006.168.07:43:50.89#ibcon#first serial, iclass 40, count 0 2006.168.07:43:50.89#ibcon#enter sib2, iclass 40, count 0 2006.168.07:43:50.89#ibcon#flushed, iclass 40, count 0 2006.168.07:43:50.89#ibcon#about to write, iclass 40, count 0 2006.168.07:43:50.89#ibcon#wrote, iclass 40, count 0 2006.168.07:43:50.89#ibcon#about to read 3, iclass 40, count 0 2006.168.07:43:50.91#ibcon#read 3, iclass 40, count 0 2006.168.07:43:50.91#ibcon#about to read 4, iclass 40, count 0 2006.168.07:43:50.91#ibcon#read 4, iclass 40, count 0 2006.168.07:43:50.91#ibcon#about to read 5, iclass 40, count 0 2006.168.07:43:50.91#ibcon#read 5, iclass 40, count 0 2006.168.07:43:50.91#ibcon#about to read 6, iclass 40, count 0 2006.168.07:43:50.91#ibcon#read 6, iclass 40, count 0 2006.168.07:43:50.91#ibcon#end of sib2, iclass 40, count 0 2006.168.07:43:50.91#ibcon#*mode == 0, iclass 40, count 0 2006.168.07:43:50.91#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.168.07:43:50.91#ibcon#[27=USB\r\n] 2006.168.07:43:50.91#ibcon#*before write, iclass 40, count 0 2006.168.07:43:50.91#ibcon#enter sib2, iclass 40, count 0 2006.168.07:43:50.91#ibcon#flushed, iclass 40, count 0 2006.168.07:43:50.91#ibcon#about to write, iclass 40, count 0 2006.168.07:43:50.91#ibcon#wrote, iclass 40, count 0 2006.168.07:43:50.91#ibcon#about to read 3, iclass 40, count 0 2006.168.07:43:50.94#ibcon#read 3, iclass 40, count 0 2006.168.07:43:50.94#ibcon#about to read 4, iclass 40, count 0 2006.168.07:43:50.94#ibcon#read 4, iclass 40, count 0 2006.168.07:43:50.94#ibcon#about to read 5, iclass 40, count 0 2006.168.07:43:50.94#ibcon#read 5, iclass 40, count 0 2006.168.07:43:50.94#ibcon#about to read 6, iclass 40, count 0 2006.168.07:43:50.94#ibcon#read 6, iclass 40, count 0 2006.168.07:43:50.94#ibcon#end of sib2, iclass 40, count 0 2006.168.07:43:50.94#ibcon#*after write, iclass 40, count 0 2006.168.07:43:50.94#ibcon#*before return 0, iclass 40, count 0 2006.168.07:43:50.94#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:43:50.94#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:43:50.94#ibcon#about to clear, iclass 40 cls_cnt 0 2006.168.07:43:50.94#ibcon#cleared, iclass 40 cls_cnt 0 2006.168.07:43:50.94$vc4f8/vblo=2,640.99 2006.168.07:43:50.94#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.168.07:43:50.94#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.168.07:43:50.94#ibcon#ireg 17 cls_cnt 0 2006.168.07:43:50.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:43:50.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:43:50.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:43:50.94#ibcon#enter wrdev, iclass 4, count 0 2006.168.07:43:50.94#ibcon#first serial, iclass 4, count 0 2006.168.07:43:50.94#ibcon#enter sib2, iclass 4, count 0 2006.168.07:43:50.94#ibcon#flushed, iclass 4, count 0 2006.168.07:43:50.94#ibcon#about to write, iclass 4, count 0 2006.168.07:43:50.94#ibcon#wrote, iclass 4, count 0 2006.168.07:43:50.94#ibcon#about to read 3, iclass 4, count 0 2006.168.07:43:50.96#ibcon#read 3, iclass 4, count 0 2006.168.07:43:50.96#ibcon#about to read 4, iclass 4, count 0 2006.168.07:43:50.96#ibcon#read 4, iclass 4, count 0 2006.168.07:43:50.96#ibcon#about to read 5, iclass 4, count 0 2006.168.07:43:50.96#ibcon#read 5, iclass 4, count 0 2006.168.07:43:50.96#ibcon#about to read 6, iclass 4, count 0 2006.168.07:43:50.96#ibcon#read 6, iclass 4, count 0 2006.168.07:43:50.96#ibcon#end of sib2, iclass 4, count 0 2006.168.07:43:50.96#ibcon#*mode == 0, iclass 4, count 0 2006.168.07:43:50.96#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.168.07:43:50.96#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.07:43:50.96#ibcon#*before write, iclass 4, count 0 2006.168.07:43:50.96#ibcon#enter sib2, iclass 4, count 0 2006.168.07:43:50.96#ibcon#flushed, iclass 4, count 0 2006.168.07:43:50.96#ibcon#about to write, iclass 4, count 0 2006.168.07:43:50.96#ibcon#wrote, iclass 4, count 0 2006.168.07:43:50.96#ibcon#about to read 3, iclass 4, count 0 2006.168.07:43:51.00#ibcon#read 3, iclass 4, count 0 2006.168.07:43:51.00#ibcon#about to read 4, iclass 4, count 0 2006.168.07:43:51.00#ibcon#read 4, iclass 4, count 0 2006.168.07:43:51.00#ibcon#about to read 5, iclass 4, count 0 2006.168.07:43:51.00#ibcon#read 5, iclass 4, count 0 2006.168.07:43:51.00#ibcon#about to read 6, iclass 4, count 0 2006.168.07:43:51.00#ibcon#read 6, iclass 4, count 0 2006.168.07:43:51.00#ibcon#end of sib2, iclass 4, count 0 2006.168.07:43:51.00#ibcon#*after write, iclass 4, count 0 2006.168.07:43:51.00#ibcon#*before return 0, iclass 4, count 0 2006.168.07:43:51.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:43:51.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:43:51.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.168.07:43:51.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.168.07:43:51.00$vc4f8/vb=2,4 2006.168.07:43:51.00#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.168.07:43:51.00#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.168.07:43:51.00#ibcon#ireg 11 cls_cnt 2 2006.168.07:43:51.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:43:51.06#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:43:51.06#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:43:51.06#ibcon#enter wrdev, iclass 6, count 2 2006.168.07:43:51.06#ibcon#first serial, iclass 6, count 2 2006.168.07:43:51.06#ibcon#enter sib2, iclass 6, count 2 2006.168.07:43:51.06#ibcon#flushed, iclass 6, count 2 2006.168.07:43:51.06#ibcon#about to write, iclass 6, count 2 2006.168.07:43:51.06#ibcon#wrote, iclass 6, count 2 2006.168.07:43:51.06#ibcon#about to read 3, iclass 6, count 2 2006.168.07:43:51.08#ibcon#read 3, iclass 6, count 2 2006.168.07:43:51.08#ibcon#about to read 4, iclass 6, count 2 2006.168.07:43:51.08#ibcon#read 4, iclass 6, count 2 2006.168.07:43:51.08#ibcon#about to read 5, iclass 6, count 2 2006.168.07:43:51.08#ibcon#read 5, iclass 6, count 2 2006.168.07:43:51.08#ibcon#about to read 6, iclass 6, count 2 2006.168.07:43:51.08#ibcon#read 6, iclass 6, count 2 2006.168.07:43:51.08#ibcon#end of sib2, iclass 6, count 2 2006.168.07:43:51.08#ibcon#*mode == 0, iclass 6, count 2 2006.168.07:43:51.08#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.168.07:43:51.08#ibcon#[27=AT02-04\r\n] 2006.168.07:43:51.08#ibcon#*before write, iclass 6, count 2 2006.168.07:43:51.08#ibcon#enter sib2, iclass 6, count 2 2006.168.07:43:51.08#ibcon#flushed, iclass 6, count 2 2006.168.07:43:51.08#ibcon#about to write, iclass 6, count 2 2006.168.07:43:51.08#ibcon#wrote, iclass 6, count 2 2006.168.07:43:51.08#ibcon#about to read 3, iclass 6, count 2 2006.168.07:43:51.11#ibcon#read 3, iclass 6, count 2 2006.168.07:43:51.11#ibcon#about to read 4, iclass 6, count 2 2006.168.07:43:51.11#ibcon#read 4, iclass 6, count 2 2006.168.07:43:51.11#ibcon#about to read 5, iclass 6, count 2 2006.168.07:43:51.11#ibcon#read 5, iclass 6, count 2 2006.168.07:43:51.11#ibcon#about to read 6, iclass 6, count 2 2006.168.07:43:51.11#ibcon#read 6, iclass 6, count 2 2006.168.07:43:51.11#ibcon#end of sib2, iclass 6, count 2 2006.168.07:43:51.11#ibcon#*after write, iclass 6, count 2 2006.168.07:43:51.11#ibcon#*before return 0, iclass 6, count 2 2006.168.07:43:51.11#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:43:51.11#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:43:51.11#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.168.07:43:51.11#ibcon#ireg 7 cls_cnt 0 2006.168.07:43:51.11#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:43:51.23#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:43:51.23#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:43:51.23#ibcon#enter wrdev, iclass 6, count 0 2006.168.07:43:51.23#ibcon#first serial, iclass 6, count 0 2006.168.07:43:51.23#ibcon#enter sib2, iclass 6, count 0 2006.168.07:43:51.23#ibcon#flushed, iclass 6, count 0 2006.168.07:43:51.23#ibcon#about to write, iclass 6, count 0 2006.168.07:43:51.23#ibcon#wrote, iclass 6, count 0 2006.168.07:43:51.23#ibcon#about to read 3, iclass 6, count 0 2006.168.07:43:51.25#ibcon#read 3, iclass 6, count 0 2006.168.07:43:51.25#ibcon#about to read 4, iclass 6, count 0 2006.168.07:43:51.25#ibcon#read 4, iclass 6, count 0 2006.168.07:43:51.25#ibcon#about to read 5, iclass 6, count 0 2006.168.07:43:51.25#ibcon#read 5, iclass 6, count 0 2006.168.07:43:51.25#ibcon#about to read 6, iclass 6, count 0 2006.168.07:43:51.25#ibcon#read 6, iclass 6, count 0 2006.168.07:43:51.25#ibcon#end of sib2, iclass 6, count 0 2006.168.07:43:51.25#ibcon#*mode == 0, iclass 6, count 0 2006.168.07:43:51.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.168.07:43:51.25#ibcon#[27=USB\r\n] 2006.168.07:43:51.25#ibcon#*before write, iclass 6, count 0 2006.168.07:43:51.25#ibcon#enter sib2, iclass 6, count 0 2006.168.07:43:51.25#ibcon#flushed, iclass 6, count 0 2006.168.07:43:51.25#ibcon#about to write, iclass 6, count 0 2006.168.07:43:51.25#ibcon#wrote, iclass 6, count 0 2006.168.07:43:51.25#ibcon#about to read 3, iclass 6, count 0 2006.168.07:43:51.28#ibcon#read 3, iclass 6, count 0 2006.168.07:43:51.28#ibcon#about to read 4, iclass 6, count 0 2006.168.07:43:51.28#ibcon#read 4, iclass 6, count 0 2006.168.07:43:51.28#ibcon#about to read 5, iclass 6, count 0 2006.168.07:43:51.28#ibcon#read 5, iclass 6, count 0 2006.168.07:43:51.28#ibcon#about to read 6, iclass 6, count 0 2006.168.07:43:51.28#ibcon#read 6, iclass 6, count 0 2006.168.07:43:51.28#ibcon#end of sib2, iclass 6, count 0 2006.168.07:43:51.28#ibcon#*after write, iclass 6, count 0 2006.168.07:43:51.28#ibcon#*before return 0, iclass 6, count 0 2006.168.07:43:51.28#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:43:51.28#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:43:51.28#ibcon#about to clear, iclass 6 cls_cnt 0 2006.168.07:43:51.28#ibcon#cleared, iclass 6 cls_cnt 0 2006.168.07:43:51.28$vc4f8/vblo=3,656.99 2006.168.07:43:51.28#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.168.07:43:51.28#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.168.07:43:51.28#ibcon#ireg 17 cls_cnt 0 2006.168.07:43:51.28#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:43:51.28#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:43:51.28#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:43:51.28#ibcon#enter wrdev, iclass 10, count 0 2006.168.07:43:51.28#ibcon#first serial, iclass 10, count 0 2006.168.07:43:51.28#ibcon#enter sib2, iclass 10, count 0 2006.168.07:43:51.28#ibcon#flushed, iclass 10, count 0 2006.168.07:43:51.28#ibcon#about to write, iclass 10, count 0 2006.168.07:43:51.28#ibcon#wrote, iclass 10, count 0 2006.168.07:43:51.28#ibcon#about to read 3, iclass 10, count 0 2006.168.07:43:51.30#ibcon#read 3, iclass 10, count 0 2006.168.07:43:51.30#ibcon#about to read 4, iclass 10, count 0 2006.168.07:43:51.30#ibcon#read 4, iclass 10, count 0 2006.168.07:43:51.30#ibcon#about to read 5, iclass 10, count 0 2006.168.07:43:51.30#ibcon#read 5, iclass 10, count 0 2006.168.07:43:51.30#ibcon#about to read 6, iclass 10, count 0 2006.168.07:43:51.30#ibcon#read 6, iclass 10, count 0 2006.168.07:43:51.30#ibcon#end of sib2, iclass 10, count 0 2006.168.07:43:51.30#ibcon#*mode == 0, iclass 10, count 0 2006.168.07:43:51.30#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.168.07:43:51.30#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.07:43:51.30#ibcon#*before write, iclass 10, count 0 2006.168.07:43:51.30#ibcon#enter sib2, iclass 10, count 0 2006.168.07:43:51.30#ibcon#flushed, iclass 10, count 0 2006.168.07:43:51.30#ibcon#about to write, iclass 10, count 0 2006.168.07:43:51.30#ibcon#wrote, iclass 10, count 0 2006.168.07:43:51.30#ibcon#about to read 3, iclass 10, count 0 2006.168.07:43:51.34#ibcon#read 3, iclass 10, count 0 2006.168.07:43:51.34#ibcon#about to read 4, iclass 10, count 0 2006.168.07:43:51.34#ibcon#read 4, iclass 10, count 0 2006.168.07:43:51.34#ibcon#about to read 5, iclass 10, count 0 2006.168.07:43:51.34#ibcon#read 5, iclass 10, count 0 2006.168.07:43:51.34#ibcon#about to read 6, iclass 10, count 0 2006.168.07:43:51.34#ibcon#read 6, iclass 10, count 0 2006.168.07:43:51.34#ibcon#end of sib2, iclass 10, count 0 2006.168.07:43:51.34#ibcon#*after write, iclass 10, count 0 2006.168.07:43:51.34#ibcon#*before return 0, iclass 10, count 0 2006.168.07:43:51.34#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:43:51.34#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:43:51.34#ibcon#about to clear, iclass 10 cls_cnt 0 2006.168.07:43:51.34#ibcon#cleared, iclass 10 cls_cnt 0 2006.168.07:43:51.34$vc4f8/vb=3,4 2006.168.07:43:51.34#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.168.07:43:51.34#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.168.07:43:51.34#ibcon#ireg 11 cls_cnt 2 2006.168.07:43:51.34#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.168.07:43:51.35#abcon#{5=INTERFACE CLEAR} 2006.168.07:43:51.40#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.168.07:43:51.40#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.168.07:43:51.40#ibcon#enter wrdev, iclass 13, count 2 2006.168.07:43:51.40#ibcon#first serial, iclass 13, count 2 2006.168.07:43:51.40#ibcon#enter sib2, iclass 13, count 2 2006.168.07:43:51.40#ibcon#flushed, iclass 13, count 2 2006.168.07:43:51.40#ibcon#about to write, iclass 13, count 2 2006.168.07:43:51.40#ibcon#wrote, iclass 13, count 2 2006.168.07:43:51.40#ibcon#about to read 3, iclass 13, count 2 2006.168.07:43:51.41#abcon#[5=S1D000X0/0*\r\n] 2006.168.07:43:51.42#ibcon#read 3, iclass 13, count 2 2006.168.07:43:51.42#ibcon#about to read 4, iclass 13, count 2 2006.168.07:43:51.42#ibcon#read 4, iclass 13, count 2 2006.168.07:43:51.42#ibcon#about to read 5, iclass 13, count 2 2006.168.07:43:51.42#ibcon#read 5, iclass 13, count 2 2006.168.07:43:51.42#ibcon#about to read 6, iclass 13, count 2 2006.168.07:43:51.42#ibcon#read 6, iclass 13, count 2 2006.168.07:43:51.42#ibcon#end of sib2, iclass 13, count 2 2006.168.07:43:51.42#ibcon#*mode == 0, iclass 13, count 2 2006.168.07:43:51.42#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.168.07:43:51.42#ibcon#[27=AT03-04\r\n] 2006.168.07:43:51.42#ibcon#*before write, iclass 13, count 2 2006.168.07:43:51.42#ibcon#enter sib2, iclass 13, count 2 2006.168.07:43:51.42#ibcon#flushed, iclass 13, count 2 2006.168.07:43:51.42#ibcon#about to write, iclass 13, count 2 2006.168.07:43:51.42#ibcon#wrote, iclass 13, count 2 2006.168.07:43:51.42#ibcon#about to read 3, iclass 13, count 2 2006.168.07:43:51.45#ibcon#read 3, iclass 13, count 2 2006.168.07:43:51.45#ibcon#about to read 4, iclass 13, count 2 2006.168.07:43:51.45#ibcon#read 4, iclass 13, count 2 2006.168.07:43:51.45#ibcon#about to read 5, iclass 13, count 2 2006.168.07:43:51.45#ibcon#read 5, iclass 13, count 2 2006.168.07:43:51.45#ibcon#about to read 6, iclass 13, count 2 2006.168.07:43:51.45#ibcon#read 6, iclass 13, count 2 2006.168.07:43:51.45#ibcon#end of sib2, iclass 13, count 2 2006.168.07:43:51.45#ibcon#*after write, iclass 13, count 2 2006.168.07:43:51.45#ibcon#*before return 0, iclass 13, count 2 2006.168.07:43:51.45#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.168.07:43:51.45#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.168.07:43:51.45#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.168.07:43:51.45#ibcon#ireg 7 cls_cnt 0 2006.168.07:43:51.45#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.168.07:43:51.57#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.168.07:43:51.57#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.168.07:43:51.57#ibcon#enter wrdev, iclass 13, count 0 2006.168.07:43:51.57#ibcon#first serial, iclass 13, count 0 2006.168.07:43:51.57#ibcon#enter sib2, iclass 13, count 0 2006.168.07:43:51.57#ibcon#flushed, iclass 13, count 0 2006.168.07:43:51.57#ibcon#about to write, iclass 13, count 0 2006.168.07:43:51.57#ibcon#wrote, iclass 13, count 0 2006.168.07:43:51.57#ibcon#about to read 3, iclass 13, count 0 2006.168.07:43:51.59#ibcon#read 3, iclass 13, count 0 2006.168.07:43:51.59#ibcon#about to read 4, iclass 13, count 0 2006.168.07:43:51.59#ibcon#read 4, iclass 13, count 0 2006.168.07:43:51.59#ibcon#about to read 5, iclass 13, count 0 2006.168.07:43:51.59#ibcon#read 5, iclass 13, count 0 2006.168.07:43:51.59#ibcon#about to read 6, iclass 13, count 0 2006.168.07:43:51.59#ibcon#read 6, iclass 13, count 0 2006.168.07:43:51.59#ibcon#end of sib2, iclass 13, count 0 2006.168.07:43:51.59#ibcon#*mode == 0, iclass 13, count 0 2006.168.07:43:51.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.168.07:43:51.59#ibcon#[27=USB\r\n] 2006.168.07:43:51.59#ibcon#*before write, iclass 13, count 0 2006.168.07:43:51.59#ibcon#enter sib2, iclass 13, count 0 2006.168.07:43:51.59#ibcon#flushed, iclass 13, count 0 2006.168.07:43:51.59#ibcon#about to write, iclass 13, count 0 2006.168.07:43:51.59#ibcon#wrote, iclass 13, count 0 2006.168.07:43:51.59#ibcon#about to read 3, iclass 13, count 0 2006.168.07:43:51.62#ibcon#read 3, iclass 13, count 0 2006.168.07:43:51.62#ibcon#about to read 4, iclass 13, count 0 2006.168.07:43:51.62#ibcon#read 4, iclass 13, count 0 2006.168.07:43:51.62#ibcon#about to read 5, iclass 13, count 0 2006.168.07:43:51.62#ibcon#read 5, iclass 13, count 0 2006.168.07:43:51.62#ibcon#about to read 6, iclass 13, count 0 2006.168.07:43:51.62#ibcon#read 6, iclass 13, count 0 2006.168.07:43:51.62#ibcon#end of sib2, iclass 13, count 0 2006.168.07:43:51.62#ibcon#*after write, iclass 13, count 0 2006.168.07:43:51.62#ibcon#*before return 0, iclass 13, count 0 2006.168.07:43:51.62#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.168.07:43:51.62#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.168.07:43:51.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.168.07:43:51.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.168.07:43:51.62$vc4f8/vblo=4,712.99 2006.168.07:43:51.62#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.168.07:43:51.62#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.168.07:43:51.62#ibcon#ireg 17 cls_cnt 0 2006.168.07:43:51.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:43:51.62#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:43:51.62#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:43:51.62#ibcon#enter wrdev, iclass 16, count 0 2006.168.07:43:51.62#ibcon#first serial, iclass 16, count 0 2006.168.07:43:51.62#ibcon#enter sib2, iclass 16, count 0 2006.168.07:43:51.62#ibcon#flushed, iclass 16, count 0 2006.168.07:43:51.62#ibcon#about to write, iclass 16, count 0 2006.168.07:43:51.62#ibcon#wrote, iclass 16, count 0 2006.168.07:43:51.62#ibcon#about to read 3, iclass 16, count 0 2006.168.07:43:51.64#ibcon#read 3, iclass 16, count 0 2006.168.07:43:51.64#ibcon#about to read 4, iclass 16, count 0 2006.168.07:43:51.64#ibcon#read 4, iclass 16, count 0 2006.168.07:43:51.64#ibcon#about to read 5, iclass 16, count 0 2006.168.07:43:51.64#ibcon#read 5, iclass 16, count 0 2006.168.07:43:51.64#ibcon#about to read 6, iclass 16, count 0 2006.168.07:43:51.64#ibcon#read 6, iclass 16, count 0 2006.168.07:43:51.64#ibcon#end of sib2, iclass 16, count 0 2006.168.07:43:51.64#ibcon#*mode == 0, iclass 16, count 0 2006.168.07:43:51.64#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.168.07:43:51.64#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.07:43:51.64#ibcon#*before write, iclass 16, count 0 2006.168.07:43:51.64#ibcon#enter sib2, iclass 16, count 0 2006.168.07:43:51.64#ibcon#flushed, iclass 16, count 0 2006.168.07:43:51.64#ibcon#about to write, iclass 16, count 0 2006.168.07:43:51.64#ibcon#wrote, iclass 16, count 0 2006.168.07:43:51.64#ibcon#about to read 3, iclass 16, count 0 2006.168.07:43:51.68#ibcon#read 3, iclass 16, count 0 2006.168.07:43:51.68#ibcon#about to read 4, iclass 16, count 0 2006.168.07:43:51.68#ibcon#read 4, iclass 16, count 0 2006.168.07:43:51.68#ibcon#about to read 5, iclass 16, count 0 2006.168.07:43:51.68#ibcon#read 5, iclass 16, count 0 2006.168.07:43:51.68#ibcon#about to read 6, iclass 16, count 0 2006.168.07:43:51.68#ibcon#read 6, iclass 16, count 0 2006.168.07:43:51.68#ibcon#end of sib2, iclass 16, count 0 2006.168.07:43:51.68#ibcon#*after write, iclass 16, count 0 2006.168.07:43:51.68#ibcon#*before return 0, iclass 16, count 0 2006.168.07:43:51.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:43:51.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:43:51.68#ibcon#about to clear, iclass 16 cls_cnt 0 2006.168.07:43:51.68#ibcon#cleared, iclass 16 cls_cnt 0 2006.168.07:43:51.68$vc4f8/vb=4,4 2006.168.07:43:51.68#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.168.07:43:51.68#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.168.07:43:51.68#ibcon#ireg 11 cls_cnt 2 2006.168.07:43:51.68#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:43:51.74#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:43:51.74#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:43:51.74#ibcon#enter wrdev, iclass 18, count 2 2006.168.07:43:51.74#ibcon#first serial, iclass 18, count 2 2006.168.07:43:51.74#ibcon#enter sib2, iclass 18, count 2 2006.168.07:43:51.74#ibcon#flushed, iclass 18, count 2 2006.168.07:43:51.74#ibcon#about to write, iclass 18, count 2 2006.168.07:43:51.74#ibcon#wrote, iclass 18, count 2 2006.168.07:43:51.74#ibcon#about to read 3, iclass 18, count 2 2006.168.07:43:51.76#ibcon#read 3, iclass 18, count 2 2006.168.07:43:51.76#ibcon#about to read 4, iclass 18, count 2 2006.168.07:43:51.76#ibcon#read 4, iclass 18, count 2 2006.168.07:43:51.76#ibcon#about to read 5, iclass 18, count 2 2006.168.07:43:51.76#ibcon#read 5, iclass 18, count 2 2006.168.07:43:51.76#ibcon#about to read 6, iclass 18, count 2 2006.168.07:43:51.76#ibcon#read 6, iclass 18, count 2 2006.168.07:43:51.76#ibcon#end of sib2, iclass 18, count 2 2006.168.07:43:51.76#ibcon#*mode == 0, iclass 18, count 2 2006.168.07:43:51.76#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.168.07:43:51.76#ibcon#[27=AT04-04\r\n] 2006.168.07:43:51.76#ibcon#*before write, iclass 18, count 2 2006.168.07:43:51.76#ibcon#enter sib2, iclass 18, count 2 2006.168.07:43:51.76#ibcon#flushed, iclass 18, count 2 2006.168.07:43:51.76#ibcon#about to write, iclass 18, count 2 2006.168.07:43:51.76#ibcon#wrote, iclass 18, count 2 2006.168.07:43:51.76#ibcon#about to read 3, iclass 18, count 2 2006.168.07:43:51.79#ibcon#read 3, iclass 18, count 2 2006.168.07:43:51.79#ibcon#about to read 4, iclass 18, count 2 2006.168.07:43:51.79#ibcon#read 4, iclass 18, count 2 2006.168.07:43:51.79#ibcon#about to read 5, iclass 18, count 2 2006.168.07:43:51.79#ibcon#read 5, iclass 18, count 2 2006.168.07:43:51.79#ibcon#about to read 6, iclass 18, count 2 2006.168.07:43:51.79#ibcon#read 6, iclass 18, count 2 2006.168.07:43:51.79#ibcon#end of sib2, iclass 18, count 2 2006.168.07:43:51.79#ibcon#*after write, iclass 18, count 2 2006.168.07:43:51.79#ibcon#*before return 0, iclass 18, count 2 2006.168.07:43:51.79#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:43:51.79#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:43:51.79#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.168.07:43:51.79#ibcon#ireg 7 cls_cnt 0 2006.168.07:43:51.79#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:43:51.91#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:43:51.91#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:43:51.91#ibcon#enter wrdev, iclass 18, count 0 2006.168.07:43:51.91#ibcon#first serial, iclass 18, count 0 2006.168.07:43:51.91#ibcon#enter sib2, iclass 18, count 0 2006.168.07:43:51.91#ibcon#flushed, iclass 18, count 0 2006.168.07:43:51.91#ibcon#about to write, iclass 18, count 0 2006.168.07:43:51.91#ibcon#wrote, iclass 18, count 0 2006.168.07:43:51.91#ibcon#about to read 3, iclass 18, count 0 2006.168.07:43:51.93#ibcon#read 3, iclass 18, count 0 2006.168.07:43:51.93#ibcon#about to read 4, iclass 18, count 0 2006.168.07:43:51.93#ibcon#read 4, iclass 18, count 0 2006.168.07:43:51.93#ibcon#about to read 5, iclass 18, count 0 2006.168.07:43:51.93#ibcon#read 5, iclass 18, count 0 2006.168.07:43:51.93#ibcon#about to read 6, iclass 18, count 0 2006.168.07:43:51.93#ibcon#read 6, iclass 18, count 0 2006.168.07:43:51.93#ibcon#end of sib2, iclass 18, count 0 2006.168.07:43:51.93#ibcon#*mode == 0, iclass 18, count 0 2006.168.07:43:51.93#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.07:43:51.93#ibcon#[27=USB\r\n] 2006.168.07:43:51.93#ibcon#*before write, iclass 18, count 0 2006.168.07:43:51.93#ibcon#enter sib2, iclass 18, count 0 2006.168.07:43:51.93#ibcon#flushed, iclass 18, count 0 2006.168.07:43:51.93#ibcon#about to write, iclass 18, count 0 2006.168.07:43:51.93#ibcon#wrote, iclass 18, count 0 2006.168.07:43:51.93#ibcon#about to read 3, iclass 18, count 0 2006.168.07:43:51.96#ibcon#read 3, iclass 18, count 0 2006.168.07:43:51.96#ibcon#about to read 4, iclass 18, count 0 2006.168.07:43:51.96#ibcon#read 4, iclass 18, count 0 2006.168.07:43:51.96#ibcon#about to read 5, iclass 18, count 0 2006.168.07:43:51.96#ibcon#read 5, iclass 18, count 0 2006.168.07:43:51.96#ibcon#about to read 6, iclass 18, count 0 2006.168.07:43:51.96#ibcon#read 6, iclass 18, count 0 2006.168.07:43:51.96#ibcon#end of sib2, iclass 18, count 0 2006.168.07:43:51.96#ibcon#*after write, iclass 18, count 0 2006.168.07:43:51.96#ibcon#*before return 0, iclass 18, count 0 2006.168.07:43:51.96#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:43:51.96#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:43:51.96#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.07:43:51.96#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.07:43:51.96$vc4f8/vblo=5,744.99 2006.168.07:43:51.96#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.168.07:43:51.96#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.168.07:43:51.96#ibcon#ireg 17 cls_cnt 0 2006.168.07:43:51.96#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:43:51.96#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:43:51.96#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:43:51.96#ibcon#enter wrdev, iclass 20, count 0 2006.168.07:43:51.96#ibcon#first serial, iclass 20, count 0 2006.168.07:43:51.96#ibcon#enter sib2, iclass 20, count 0 2006.168.07:43:51.96#ibcon#flushed, iclass 20, count 0 2006.168.07:43:51.96#ibcon#about to write, iclass 20, count 0 2006.168.07:43:51.96#ibcon#wrote, iclass 20, count 0 2006.168.07:43:51.96#ibcon#about to read 3, iclass 20, count 0 2006.168.07:43:51.98#ibcon#read 3, iclass 20, count 0 2006.168.07:43:51.98#ibcon#about to read 4, iclass 20, count 0 2006.168.07:43:51.98#ibcon#read 4, iclass 20, count 0 2006.168.07:43:51.98#ibcon#about to read 5, iclass 20, count 0 2006.168.07:43:51.98#ibcon#read 5, iclass 20, count 0 2006.168.07:43:51.98#ibcon#about to read 6, iclass 20, count 0 2006.168.07:43:51.98#ibcon#read 6, iclass 20, count 0 2006.168.07:43:51.98#ibcon#end of sib2, iclass 20, count 0 2006.168.07:43:51.98#ibcon#*mode == 0, iclass 20, count 0 2006.168.07:43:51.98#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.168.07:43:51.98#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.07:43:51.98#ibcon#*before write, iclass 20, count 0 2006.168.07:43:51.98#ibcon#enter sib2, iclass 20, count 0 2006.168.07:43:51.98#ibcon#flushed, iclass 20, count 0 2006.168.07:43:51.98#ibcon#about to write, iclass 20, count 0 2006.168.07:43:51.98#ibcon#wrote, iclass 20, count 0 2006.168.07:43:51.98#ibcon#about to read 3, iclass 20, count 0 2006.168.07:43:52.02#ibcon#read 3, iclass 20, count 0 2006.168.07:43:52.02#ibcon#about to read 4, iclass 20, count 0 2006.168.07:43:52.02#ibcon#read 4, iclass 20, count 0 2006.168.07:43:52.02#ibcon#about to read 5, iclass 20, count 0 2006.168.07:43:52.02#ibcon#read 5, iclass 20, count 0 2006.168.07:43:52.02#ibcon#about to read 6, iclass 20, count 0 2006.168.07:43:52.02#ibcon#read 6, iclass 20, count 0 2006.168.07:43:52.02#ibcon#end of sib2, iclass 20, count 0 2006.168.07:43:52.02#ibcon#*after write, iclass 20, count 0 2006.168.07:43:52.02#ibcon#*before return 0, iclass 20, count 0 2006.168.07:43:52.02#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:43:52.02#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:43:52.02#ibcon#about to clear, iclass 20 cls_cnt 0 2006.168.07:43:52.02#ibcon#cleared, iclass 20 cls_cnt 0 2006.168.07:43:52.02$vc4f8/vb=5,4 2006.168.07:43:52.02#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.168.07:43:52.02#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.168.07:43:52.02#ibcon#ireg 11 cls_cnt 2 2006.168.07:43:52.02#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:43:52.08#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:43:52.08#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:43:52.08#ibcon#enter wrdev, iclass 22, count 2 2006.168.07:43:52.08#ibcon#first serial, iclass 22, count 2 2006.168.07:43:52.08#ibcon#enter sib2, iclass 22, count 2 2006.168.07:43:52.08#ibcon#flushed, iclass 22, count 2 2006.168.07:43:52.08#ibcon#about to write, iclass 22, count 2 2006.168.07:43:52.08#ibcon#wrote, iclass 22, count 2 2006.168.07:43:52.08#ibcon#about to read 3, iclass 22, count 2 2006.168.07:43:52.10#ibcon#read 3, iclass 22, count 2 2006.168.07:43:52.10#ibcon#about to read 4, iclass 22, count 2 2006.168.07:43:52.10#ibcon#read 4, iclass 22, count 2 2006.168.07:43:52.10#ibcon#about to read 5, iclass 22, count 2 2006.168.07:43:52.10#ibcon#read 5, iclass 22, count 2 2006.168.07:43:52.10#ibcon#about to read 6, iclass 22, count 2 2006.168.07:43:52.10#ibcon#read 6, iclass 22, count 2 2006.168.07:43:52.10#ibcon#end of sib2, iclass 22, count 2 2006.168.07:43:52.10#ibcon#*mode == 0, iclass 22, count 2 2006.168.07:43:52.10#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.168.07:43:52.10#ibcon#[27=AT05-04\r\n] 2006.168.07:43:52.10#ibcon#*before write, iclass 22, count 2 2006.168.07:43:52.10#ibcon#enter sib2, iclass 22, count 2 2006.168.07:43:52.10#ibcon#flushed, iclass 22, count 2 2006.168.07:43:52.10#ibcon#about to write, iclass 22, count 2 2006.168.07:43:52.10#ibcon#wrote, iclass 22, count 2 2006.168.07:43:52.10#ibcon#about to read 3, iclass 22, count 2 2006.168.07:43:52.13#ibcon#read 3, iclass 22, count 2 2006.168.07:43:52.13#ibcon#about to read 4, iclass 22, count 2 2006.168.07:43:52.13#ibcon#read 4, iclass 22, count 2 2006.168.07:43:52.13#ibcon#about to read 5, iclass 22, count 2 2006.168.07:43:52.13#ibcon#read 5, iclass 22, count 2 2006.168.07:43:52.13#ibcon#about to read 6, iclass 22, count 2 2006.168.07:43:52.13#ibcon#read 6, iclass 22, count 2 2006.168.07:43:52.13#ibcon#end of sib2, iclass 22, count 2 2006.168.07:43:52.13#ibcon#*after write, iclass 22, count 2 2006.168.07:43:52.13#ibcon#*before return 0, iclass 22, count 2 2006.168.07:43:52.13#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:43:52.13#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:43:52.13#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.168.07:43:52.13#ibcon#ireg 7 cls_cnt 0 2006.168.07:43:52.13#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:43:52.25#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:43:52.25#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:43:52.25#ibcon#enter wrdev, iclass 22, count 0 2006.168.07:43:52.25#ibcon#first serial, iclass 22, count 0 2006.168.07:43:52.25#ibcon#enter sib2, iclass 22, count 0 2006.168.07:43:52.25#ibcon#flushed, iclass 22, count 0 2006.168.07:43:52.25#ibcon#about to write, iclass 22, count 0 2006.168.07:43:52.25#ibcon#wrote, iclass 22, count 0 2006.168.07:43:52.25#ibcon#about to read 3, iclass 22, count 0 2006.168.07:43:52.27#ibcon#read 3, iclass 22, count 0 2006.168.07:43:52.27#ibcon#about to read 4, iclass 22, count 0 2006.168.07:43:52.27#ibcon#read 4, iclass 22, count 0 2006.168.07:43:52.27#ibcon#about to read 5, iclass 22, count 0 2006.168.07:43:52.27#ibcon#read 5, iclass 22, count 0 2006.168.07:43:52.27#ibcon#about to read 6, iclass 22, count 0 2006.168.07:43:52.27#ibcon#read 6, iclass 22, count 0 2006.168.07:43:52.27#ibcon#end of sib2, iclass 22, count 0 2006.168.07:43:52.27#ibcon#*mode == 0, iclass 22, count 0 2006.168.07:43:52.27#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.168.07:43:52.27#ibcon#[27=USB\r\n] 2006.168.07:43:52.27#ibcon#*before write, iclass 22, count 0 2006.168.07:43:52.27#ibcon#enter sib2, iclass 22, count 0 2006.168.07:43:52.27#ibcon#flushed, iclass 22, count 0 2006.168.07:43:52.27#ibcon#about to write, iclass 22, count 0 2006.168.07:43:52.27#ibcon#wrote, iclass 22, count 0 2006.168.07:43:52.27#ibcon#about to read 3, iclass 22, count 0 2006.168.07:43:52.30#ibcon#read 3, iclass 22, count 0 2006.168.07:43:52.30#ibcon#about to read 4, iclass 22, count 0 2006.168.07:43:52.30#ibcon#read 4, iclass 22, count 0 2006.168.07:43:52.30#ibcon#about to read 5, iclass 22, count 0 2006.168.07:43:52.30#ibcon#read 5, iclass 22, count 0 2006.168.07:43:52.30#ibcon#about to read 6, iclass 22, count 0 2006.168.07:43:52.30#ibcon#read 6, iclass 22, count 0 2006.168.07:43:52.30#ibcon#end of sib2, iclass 22, count 0 2006.168.07:43:52.30#ibcon#*after write, iclass 22, count 0 2006.168.07:43:52.30#ibcon#*before return 0, iclass 22, count 0 2006.168.07:43:52.30#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:43:52.30#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:43:52.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.168.07:43:52.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.168.07:43:52.30$vc4f8/vblo=6,752.99 2006.168.07:43:52.30#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.168.07:43:52.30#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.168.07:43:52.30#ibcon#ireg 17 cls_cnt 0 2006.168.07:43:52.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.168.07:43:52.30#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.168.07:43:52.30#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.168.07:43:52.30#ibcon#enter wrdev, iclass 24, count 0 2006.168.07:43:52.30#ibcon#first serial, iclass 24, count 0 2006.168.07:43:52.30#ibcon#enter sib2, iclass 24, count 0 2006.168.07:43:52.30#ibcon#flushed, iclass 24, count 0 2006.168.07:43:52.30#ibcon#about to write, iclass 24, count 0 2006.168.07:43:52.30#ibcon#wrote, iclass 24, count 0 2006.168.07:43:52.30#ibcon#about to read 3, iclass 24, count 0 2006.168.07:43:52.32#ibcon#read 3, iclass 24, count 0 2006.168.07:43:52.32#ibcon#about to read 4, iclass 24, count 0 2006.168.07:43:52.32#ibcon#read 4, iclass 24, count 0 2006.168.07:43:52.32#ibcon#about to read 5, iclass 24, count 0 2006.168.07:43:52.32#ibcon#read 5, iclass 24, count 0 2006.168.07:43:52.32#ibcon#about to read 6, iclass 24, count 0 2006.168.07:43:52.32#ibcon#read 6, iclass 24, count 0 2006.168.07:43:52.32#ibcon#end of sib2, iclass 24, count 0 2006.168.07:43:52.32#ibcon#*mode == 0, iclass 24, count 0 2006.168.07:43:52.32#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.168.07:43:52.32#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.07:43:52.32#ibcon#*before write, iclass 24, count 0 2006.168.07:43:52.32#ibcon#enter sib2, iclass 24, count 0 2006.168.07:43:52.32#ibcon#flushed, iclass 24, count 0 2006.168.07:43:52.32#ibcon#about to write, iclass 24, count 0 2006.168.07:43:52.32#ibcon#wrote, iclass 24, count 0 2006.168.07:43:52.32#ibcon#about to read 3, iclass 24, count 0 2006.168.07:43:52.36#ibcon#read 3, iclass 24, count 0 2006.168.07:43:52.36#ibcon#about to read 4, iclass 24, count 0 2006.168.07:43:52.36#ibcon#read 4, iclass 24, count 0 2006.168.07:43:52.36#ibcon#about to read 5, iclass 24, count 0 2006.168.07:43:52.36#ibcon#read 5, iclass 24, count 0 2006.168.07:43:52.36#ibcon#about to read 6, iclass 24, count 0 2006.168.07:43:52.36#ibcon#read 6, iclass 24, count 0 2006.168.07:43:52.36#ibcon#end of sib2, iclass 24, count 0 2006.168.07:43:52.36#ibcon#*after write, iclass 24, count 0 2006.168.07:43:52.36#ibcon#*before return 0, iclass 24, count 0 2006.168.07:43:52.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.168.07:43:52.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.168.07:43:52.36#ibcon#about to clear, iclass 24 cls_cnt 0 2006.168.07:43:52.36#ibcon#cleared, iclass 24 cls_cnt 0 2006.168.07:43:52.36$vc4f8/vb=6,4 2006.168.07:43:52.36#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.168.07:43:52.36#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.168.07:43:52.36#ibcon#ireg 11 cls_cnt 2 2006.168.07:43:52.36#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.168.07:43:52.42#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.168.07:43:52.42#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.168.07:43:52.42#ibcon#enter wrdev, iclass 26, count 2 2006.168.07:43:52.42#ibcon#first serial, iclass 26, count 2 2006.168.07:43:52.42#ibcon#enter sib2, iclass 26, count 2 2006.168.07:43:52.42#ibcon#flushed, iclass 26, count 2 2006.168.07:43:52.42#ibcon#about to write, iclass 26, count 2 2006.168.07:43:52.42#ibcon#wrote, iclass 26, count 2 2006.168.07:43:52.42#ibcon#about to read 3, iclass 26, count 2 2006.168.07:43:52.44#ibcon#read 3, iclass 26, count 2 2006.168.07:43:52.44#ibcon#about to read 4, iclass 26, count 2 2006.168.07:43:52.44#ibcon#read 4, iclass 26, count 2 2006.168.07:43:52.44#ibcon#about to read 5, iclass 26, count 2 2006.168.07:43:52.44#ibcon#read 5, iclass 26, count 2 2006.168.07:43:52.44#ibcon#about to read 6, iclass 26, count 2 2006.168.07:43:52.44#ibcon#read 6, iclass 26, count 2 2006.168.07:43:52.44#ibcon#end of sib2, iclass 26, count 2 2006.168.07:43:52.44#ibcon#*mode == 0, iclass 26, count 2 2006.168.07:43:52.44#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.168.07:43:52.44#ibcon#[27=AT06-04\r\n] 2006.168.07:43:52.44#ibcon#*before write, iclass 26, count 2 2006.168.07:43:52.44#ibcon#enter sib2, iclass 26, count 2 2006.168.07:43:52.44#ibcon#flushed, iclass 26, count 2 2006.168.07:43:52.44#ibcon#about to write, iclass 26, count 2 2006.168.07:43:52.44#ibcon#wrote, iclass 26, count 2 2006.168.07:43:52.44#ibcon#about to read 3, iclass 26, count 2 2006.168.07:43:52.47#ibcon#read 3, iclass 26, count 2 2006.168.07:43:52.47#ibcon#about to read 4, iclass 26, count 2 2006.168.07:43:52.47#ibcon#read 4, iclass 26, count 2 2006.168.07:43:52.47#ibcon#about to read 5, iclass 26, count 2 2006.168.07:43:52.47#ibcon#read 5, iclass 26, count 2 2006.168.07:43:52.47#ibcon#about to read 6, iclass 26, count 2 2006.168.07:43:52.47#ibcon#read 6, iclass 26, count 2 2006.168.07:43:52.47#ibcon#end of sib2, iclass 26, count 2 2006.168.07:43:52.47#ibcon#*after write, iclass 26, count 2 2006.168.07:43:52.47#ibcon#*before return 0, iclass 26, count 2 2006.168.07:43:52.47#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.168.07:43:52.47#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.168.07:43:52.47#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.168.07:43:52.47#ibcon#ireg 7 cls_cnt 0 2006.168.07:43:52.47#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.168.07:43:52.59#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.168.07:43:52.59#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.168.07:43:52.59#ibcon#enter wrdev, iclass 26, count 0 2006.168.07:43:52.59#ibcon#first serial, iclass 26, count 0 2006.168.07:43:52.59#ibcon#enter sib2, iclass 26, count 0 2006.168.07:43:52.59#ibcon#flushed, iclass 26, count 0 2006.168.07:43:52.59#ibcon#about to write, iclass 26, count 0 2006.168.07:43:52.59#ibcon#wrote, iclass 26, count 0 2006.168.07:43:52.59#ibcon#about to read 3, iclass 26, count 0 2006.168.07:43:52.61#ibcon#read 3, iclass 26, count 0 2006.168.07:43:52.61#ibcon#about to read 4, iclass 26, count 0 2006.168.07:43:52.61#ibcon#read 4, iclass 26, count 0 2006.168.07:43:52.61#ibcon#about to read 5, iclass 26, count 0 2006.168.07:43:52.61#ibcon#read 5, iclass 26, count 0 2006.168.07:43:52.61#ibcon#about to read 6, iclass 26, count 0 2006.168.07:43:52.61#ibcon#read 6, iclass 26, count 0 2006.168.07:43:52.61#ibcon#end of sib2, iclass 26, count 0 2006.168.07:43:52.61#ibcon#*mode == 0, iclass 26, count 0 2006.168.07:43:52.61#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.168.07:43:52.61#ibcon#[27=USB\r\n] 2006.168.07:43:52.61#ibcon#*before write, iclass 26, count 0 2006.168.07:43:52.61#ibcon#enter sib2, iclass 26, count 0 2006.168.07:43:52.61#ibcon#flushed, iclass 26, count 0 2006.168.07:43:52.61#ibcon#about to write, iclass 26, count 0 2006.168.07:43:52.61#ibcon#wrote, iclass 26, count 0 2006.168.07:43:52.61#ibcon#about to read 3, iclass 26, count 0 2006.168.07:43:52.64#ibcon#read 3, iclass 26, count 0 2006.168.07:43:52.64#ibcon#about to read 4, iclass 26, count 0 2006.168.07:43:52.64#ibcon#read 4, iclass 26, count 0 2006.168.07:43:52.64#ibcon#about to read 5, iclass 26, count 0 2006.168.07:43:52.64#ibcon#read 5, iclass 26, count 0 2006.168.07:43:52.64#ibcon#about to read 6, iclass 26, count 0 2006.168.07:43:52.64#ibcon#read 6, iclass 26, count 0 2006.168.07:43:52.64#ibcon#end of sib2, iclass 26, count 0 2006.168.07:43:52.64#ibcon#*after write, iclass 26, count 0 2006.168.07:43:52.64#ibcon#*before return 0, iclass 26, count 0 2006.168.07:43:52.64#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.168.07:43:52.64#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.168.07:43:52.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.168.07:43:52.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.168.07:43:52.64$vc4f8/vabw=wide 2006.168.07:43:52.64#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.168.07:43:52.64#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.168.07:43:52.64#ibcon#ireg 8 cls_cnt 0 2006.168.07:43:52.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:43:52.64#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:43:52.64#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:43:52.64#ibcon#enter wrdev, iclass 28, count 0 2006.168.07:43:52.64#ibcon#first serial, iclass 28, count 0 2006.168.07:43:52.64#ibcon#enter sib2, iclass 28, count 0 2006.168.07:43:52.64#ibcon#flushed, iclass 28, count 0 2006.168.07:43:52.64#ibcon#about to write, iclass 28, count 0 2006.168.07:43:52.64#ibcon#wrote, iclass 28, count 0 2006.168.07:43:52.64#ibcon#about to read 3, iclass 28, count 0 2006.168.07:43:52.66#ibcon#read 3, iclass 28, count 0 2006.168.07:43:52.66#ibcon#about to read 4, iclass 28, count 0 2006.168.07:43:52.66#ibcon#read 4, iclass 28, count 0 2006.168.07:43:52.66#ibcon#about to read 5, iclass 28, count 0 2006.168.07:43:52.66#ibcon#read 5, iclass 28, count 0 2006.168.07:43:52.66#ibcon#about to read 6, iclass 28, count 0 2006.168.07:43:52.66#ibcon#read 6, iclass 28, count 0 2006.168.07:43:52.66#ibcon#end of sib2, iclass 28, count 0 2006.168.07:43:52.66#ibcon#*mode == 0, iclass 28, count 0 2006.168.07:43:52.66#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.168.07:43:52.66#ibcon#[25=BW32\r\n] 2006.168.07:43:52.66#ibcon#*before write, iclass 28, count 0 2006.168.07:43:52.66#ibcon#enter sib2, iclass 28, count 0 2006.168.07:43:52.66#ibcon#flushed, iclass 28, count 0 2006.168.07:43:52.66#ibcon#about to write, iclass 28, count 0 2006.168.07:43:52.66#ibcon#wrote, iclass 28, count 0 2006.168.07:43:52.66#ibcon#about to read 3, iclass 28, count 0 2006.168.07:43:52.69#ibcon#read 3, iclass 28, count 0 2006.168.07:43:52.69#ibcon#about to read 4, iclass 28, count 0 2006.168.07:43:52.69#ibcon#read 4, iclass 28, count 0 2006.168.07:43:52.69#ibcon#about to read 5, iclass 28, count 0 2006.168.07:43:52.69#ibcon#read 5, iclass 28, count 0 2006.168.07:43:52.69#ibcon#about to read 6, iclass 28, count 0 2006.168.07:43:52.69#ibcon#read 6, iclass 28, count 0 2006.168.07:43:52.69#ibcon#end of sib2, iclass 28, count 0 2006.168.07:43:52.69#ibcon#*after write, iclass 28, count 0 2006.168.07:43:52.69#ibcon#*before return 0, iclass 28, count 0 2006.168.07:43:52.69#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:43:52.69#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:43:52.69#ibcon#about to clear, iclass 28 cls_cnt 0 2006.168.07:43:52.69#ibcon#cleared, iclass 28 cls_cnt 0 2006.168.07:43:52.69$vc4f8/vbbw=wide 2006.168.07:43:52.69#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.168.07:43:52.69#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.168.07:43:52.69#ibcon#ireg 8 cls_cnt 0 2006.168.07:43:52.69#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:43:52.76#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:43:52.76#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:43:52.76#ibcon#enter wrdev, iclass 30, count 0 2006.168.07:43:52.76#ibcon#first serial, iclass 30, count 0 2006.168.07:43:52.76#ibcon#enter sib2, iclass 30, count 0 2006.168.07:43:52.76#ibcon#flushed, iclass 30, count 0 2006.168.07:43:52.76#ibcon#about to write, iclass 30, count 0 2006.168.07:43:52.76#ibcon#wrote, iclass 30, count 0 2006.168.07:43:52.76#ibcon#about to read 3, iclass 30, count 0 2006.168.07:43:52.78#ibcon#read 3, iclass 30, count 0 2006.168.07:43:52.78#ibcon#about to read 4, iclass 30, count 0 2006.168.07:43:52.78#ibcon#read 4, iclass 30, count 0 2006.168.07:43:52.78#ibcon#about to read 5, iclass 30, count 0 2006.168.07:43:52.78#ibcon#read 5, iclass 30, count 0 2006.168.07:43:52.78#ibcon#about to read 6, iclass 30, count 0 2006.168.07:43:52.78#ibcon#read 6, iclass 30, count 0 2006.168.07:43:52.78#ibcon#end of sib2, iclass 30, count 0 2006.168.07:43:52.78#ibcon#*mode == 0, iclass 30, count 0 2006.168.07:43:52.78#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.168.07:43:52.78#ibcon#[27=BW32\r\n] 2006.168.07:43:52.78#ibcon#*before write, iclass 30, count 0 2006.168.07:43:52.78#ibcon#enter sib2, iclass 30, count 0 2006.168.07:43:52.78#ibcon#flushed, iclass 30, count 0 2006.168.07:43:52.78#ibcon#about to write, iclass 30, count 0 2006.168.07:43:52.78#ibcon#wrote, iclass 30, count 0 2006.168.07:43:52.78#ibcon#about to read 3, iclass 30, count 0 2006.168.07:43:52.81#ibcon#read 3, iclass 30, count 0 2006.168.07:43:52.81#ibcon#about to read 4, iclass 30, count 0 2006.168.07:43:52.81#ibcon#read 4, iclass 30, count 0 2006.168.07:43:52.81#ibcon#about to read 5, iclass 30, count 0 2006.168.07:43:52.81#ibcon#read 5, iclass 30, count 0 2006.168.07:43:52.81#ibcon#about to read 6, iclass 30, count 0 2006.168.07:43:52.81#ibcon#read 6, iclass 30, count 0 2006.168.07:43:52.81#ibcon#end of sib2, iclass 30, count 0 2006.168.07:43:52.81#ibcon#*after write, iclass 30, count 0 2006.168.07:43:52.81#ibcon#*before return 0, iclass 30, count 0 2006.168.07:43:52.81#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:43:52.81#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:43:52.81#ibcon#about to clear, iclass 30 cls_cnt 0 2006.168.07:43:52.81#ibcon#cleared, iclass 30 cls_cnt 0 2006.168.07:43:52.81$4f8m12a/ifd4f 2006.168.07:43:52.81$ifd4f/lo= 2006.168.07:43:52.81$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.07:43:52.81$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.07:43:52.81$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.07:43:52.81$ifd4f/patch= 2006.168.07:43:52.81$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.07:43:52.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.07:43:52.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.07:43:52.81$4f8m12a/"form=m,16.000,1:2 2006.168.07:43:52.81$4f8m12a/"tpicd 2006.168.07:43:52.81$4f8m12a/echo=off 2006.168.07:43:52.81$4f8m12a/xlog=off 2006.168.07:43:52.81:!2006.168.07:44:20 2006.168.07:44:02.14#trakl#Source acquired 2006.168.07:44:02.14#flagr#flagr/antenna,acquired 2006.168.07:44:20.00:preob 2006.168.07:44:21.13/onsource/TRACKING 2006.168.07:44:21.13:!2006.168.07:44:30 2006.168.07:44:30.00:data_valid=on 2006.168.07:44:30.00:midob 2006.168.07:44:30.13/onsource/TRACKING 2006.168.07:44:30.13/wx/27.58,1004.6,73 2006.168.07:44:30.25/cable/+6.4711E-03 2006.168.07:44:31.34/va/01,08,usb,yes,29,30 2006.168.07:44:31.34/va/02,07,usb,yes,29,30 2006.168.07:44:31.34/va/03,06,usb,yes,30,31 2006.168.07:44:31.34/va/04,07,usb,yes,30,32 2006.168.07:44:31.34/va/05,07,usb,yes,29,31 2006.168.07:44:31.34/va/06,06,usb,yes,28,28 2006.168.07:44:31.34/va/07,06,usb,yes,29,29 2006.168.07:44:31.34/va/08,07,usb,yes,27,27 2006.168.07:44:31.57/valo/01,532.99,yes,locked 2006.168.07:44:31.57/valo/02,572.99,yes,locked 2006.168.07:44:31.57/valo/03,672.99,yes,locked 2006.168.07:44:31.57/valo/04,832.99,yes,locked 2006.168.07:44:31.57/valo/05,652.99,yes,locked 2006.168.07:44:31.57/valo/06,772.99,yes,locked 2006.168.07:44:31.57/valo/07,832.99,yes,locked 2006.168.07:44:31.57/valo/08,852.99,yes,locked 2006.168.07:44:32.66/vb/01,04,usb,yes,29,28 2006.168.07:44:32.66/vb/02,04,usb,yes,31,32 2006.168.07:44:32.66/vb/03,04,usb,yes,27,31 2006.168.07:44:32.66/vb/04,04,usb,yes,28,28 2006.168.07:44:32.66/vb/05,04,usb,yes,27,30 2006.168.07:44:32.66/vb/06,04,usb,yes,27,30 2006.168.07:44:32.66/vb/07,04,usb,yes,29,29 2006.168.07:44:32.66/vb/08,04,usb,yes,27,30 2006.168.07:44:32.89/vblo/01,632.99,yes,locked 2006.168.07:44:32.89/vblo/02,640.99,yes,locked 2006.168.07:44:32.89/vblo/03,656.99,yes,locked 2006.168.07:44:32.89/vblo/04,712.99,yes,locked 2006.168.07:44:32.89/vblo/05,744.99,yes,locked 2006.168.07:44:32.89/vblo/06,752.99,yes,locked 2006.168.07:44:32.89/vblo/07,734.99,yes,locked 2006.168.07:44:32.89/vblo/08,744.99,yes,locked 2006.168.07:44:33.04/vabw/8 2006.168.07:44:33.19/vbbw/8 2006.168.07:44:33.28/xfe/off,on,14.7 2006.168.07:44:33.66/ifatt/23,28,28,28 2006.168.07:44:34.08/fmout-gps/S +4.18E-07 2006.168.07:44:34.12:!2006.168.07:45:30 2006.168.07:45:30.00:data_valid=off 2006.168.07:45:30.00:postob 2006.168.07:45:30.21/cable/+6.4729E-03 2006.168.07:45:30.21/wx/27.55,1004.6,74 2006.168.07:45:31.08/fmout-gps/S +4.18E-07 2006.168.07:45:31.08:scan_name=168-0747,k06168,130 2006.168.07:45:31.08:source=0722+145,072516.81,142513.7,2000.0,ccw 2006.168.07:45:31.13#flagr#flagr/antenna,new-source 2006.168.07:45:32.13:checkk5 2006.168.07:45:32.50/chk_autoobs//k5ts1/ autoobs is running! 2006.168.07:45:32.87/chk_autoobs//k5ts2/ autoobs is running! 2006.168.07:45:33.26/chk_autoobs//k5ts3/ autoobs is running! 2006.168.07:45:33.63/chk_autoobs//k5ts4/ autoobs is running! 2006.168.07:45:34.00/chk_obsdata//k5ts1/T1680744??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:45:34.38/chk_obsdata//k5ts2/T1680744??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:45:34.76/chk_obsdata//k5ts3/T1680744??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:45:35.13/chk_obsdata//k5ts4/T1680744??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:45:35.83/k5log//k5ts1_log_newline 2006.168.07:45:36.53/k5log//k5ts2_log_newline 2006.168.07:45:37.22/k5log//k5ts3_log_newline 2006.168.07:45:37.90/k5log//k5ts4_log_newline 2006.168.07:45:37.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.07:45:37.93:4f8m12a=1 2006.168.07:45:37.93$4f8m12a/echo=on 2006.168.07:45:37.93$4f8m12a/pcalon 2006.168.07:45:37.93$pcalon/"no phase cal control is implemented here 2006.168.07:45:37.93$4f8m12a/"tpicd=stop 2006.168.07:45:37.93$4f8m12a/vc4f8 2006.168.07:45:37.93$vc4f8/valo=1,532.99 2006.168.07:45:37.93#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.168.07:45:37.93#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.168.07:45:37.93#ibcon#ireg 17 cls_cnt 0 2006.168.07:45:37.93#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:45:37.93#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:45:37.93#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:45:37.93#ibcon#enter wrdev, iclass 37, count 0 2006.168.07:45:37.93#ibcon#first serial, iclass 37, count 0 2006.168.07:45:37.93#ibcon#enter sib2, iclass 37, count 0 2006.168.07:45:37.93#ibcon#flushed, iclass 37, count 0 2006.168.07:45:37.93#ibcon#about to write, iclass 37, count 0 2006.168.07:45:37.93#ibcon#wrote, iclass 37, count 0 2006.168.07:45:37.93#ibcon#about to read 3, iclass 37, count 0 2006.168.07:45:37.95#ibcon#read 3, iclass 37, count 0 2006.168.07:45:37.95#ibcon#about to read 4, iclass 37, count 0 2006.168.07:45:37.95#ibcon#read 4, iclass 37, count 0 2006.168.07:45:37.95#ibcon#about to read 5, iclass 37, count 0 2006.168.07:45:37.95#ibcon#read 5, iclass 37, count 0 2006.168.07:45:37.95#ibcon#about to read 6, iclass 37, count 0 2006.168.07:45:37.95#ibcon#read 6, iclass 37, count 0 2006.168.07:45:37.95#ibcon#end of sib2, iclass 37, count 0 2006.168.07:45:37.95#ibcon#*mode == 0, iclass 37, count 0 2006.168.07:45:37.95#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.168.07:45:37.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.07:45:37.95#ibcon#*before write, iclass 37, count 0 2006.168.07:45:37.95#ibcon#enter sib2, iclass 37, count 0 2006.168.07:45:37.95#ibcon#flushed, iclass 37, count 0 2006.168.07:45:37.95#ibcon#about to write, iclass 37, count 0 2006.168.07:45:37.95#ibcon#wrote, iclass 37, count 0 2006.168.07:45:37.95#ibcon#about to read 3, iclass 37, count 0 2006.168.07:45:38.00#ibcon#read 3, iclass 37, count 0 2006.168.07:45:38.00#ibcon#about to read 4, iclass 37, count 0 2006.168.07:45:38.00#ibcon#read 4, iclass 37, count 0 2006.168.07:45:38.00#ibcon#about to read 5, iclass 37, count 0 2006.168.07:45:38.00#ibcon#read 5, iclass 37, count 0 2006.168.07:45:38.00#ibcon#about to read 6, iclass 37, count 0 2006.168.07:45:38.00#ibcon#read 6, iclass 37, count 0 2006.168.07:45:38.00#ibcon#end of sib2, iclass 37, count 0 2006.168.07:45:38.00#ibcon#*after write, iclass 37, count 0 2006.168.07:45:38.00#ibcon#*before return 0, iclass 37, count 0 2006.168.07:45:38.00#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:45:38.00#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:45:38.00#ibcon#about to clear, iclass 37 cls_cnt 0 2006.168.07:45:38.00#ibcon#cleared, iclass 37 cls_cnt 0 2006.168.07:45:38.00$vc4f8/va=1,8 2006.168.07:45:38.00#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.168.07:45:38.00#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.168.07:45:38.00#ibcon#ireg 11 cls_cnt 2 2006.168.07:45:38.00#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:45:38.00#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:45:38.00#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:45:38.00#ibcon#enter wrdev, iclass 39, count 2 2006.168.07:45:38.00#ibcon#first serial, iclass 39, count 2 2006.168.07:45:38.00#ibcon#enter sib2, iclass 39, count 2 2006.168.07:45:38.00#ibcon#flushed, iclass 39, count 2 2006.168.07:45:38.00#ibcon#about to write, iclass 39, count 2 2006.168.07:45:38.00#ibcon#wrote, iclass 39, count 2 2006.168.07:45:38.00#ibcon#about to read 3, iclass 39, count 2 2006.168.07:45:38.02#ibcon#read 3, iclass 39, count 2 2006.168.07:45:38.02#ibcon#about to read 4, iclass 39, count 2 2006.168.07:45:38.02#ibcon#read 4, iclass 39, count 2 2006.168.07:45:38.02#ibcon#about to read 5, iclass 39, count 2 2006.168.07:45:38.02#ibcon#read 5, iclass 39, count 2 2006.168.07:45:38.02#ibcon#about to read 6, iclass 39, count 2 2006.168.07:45:38.02#ibcon#read 6, iclass 39, count 2 2006.168.07:45:38.02#ibcon#end of sib2, iclass 39, count 2 2006.168.07:45:38.02#ibcon#*mode == 0, iclass 39, count 2 2006.168.07:45:38.02#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.168.07:45:38.02#ibcon#[25=AT01-08\r\n] 2006.168.07:45:38.02#ibcon#*before write, iclass 39, count 2 2006.168.07:45:38.02#ibcon#enter sib2, iclass 39, count 2 2006.168.07:45:38.02#ibcon#flushed, iclass 39, count 2 2006.168.07:45:38.02#ibcon#about to write, iclass 39, count 2 2006.168.07:45:38.02#ibcon#wrote, iclass 39, count 2 2006.168.07:45:38.02#ibcon#about to read 3, iclass 39, count 2 2006.168.07:45:38.05#ibcon#read 3, iclass 39, count 2 2006.168.07:45:38.05#ibcon#about to read 4, iclass 39, count 2 2006.168.07:45:38.05#ibcon#read 4, iclass 39, count 2 2006.168.07:45:38.05#ibcon#about to read 5, iclass 39, count 2 2006.168.07:45:38.05#ibcon#read 5, iclass 39, count 2 2006.168.07:45:38.05#ibcon#about to read 6, iclass 39, count 2 2006.168.07:45:38.05#ibcon#read 6, iclass 39, count 2 2006.168.07:45:38.05#ibcon#end of sib2, iclass 39, count 2 2006.168.07:45:38.05#ibcon#*after write, iclass 39, count 2 2006.168.07:45:38.05#ibcon#*before return 0, iclass 39, count 2 2006.168.07:45:38.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:45:38.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:45:38.05#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.168.07:45:38.05#ibcon#ireg 7 cls_cnt 0 2006.168.07:45:38.05#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:45:38.16#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:45:38.17#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:45:38.17#ibcon#enter wrdev, iclass 39, count 0 2006.168.07:45:38.17#ibcon#first serial, iclass 39, count 0 2006.168.07:45:38.17#ibcon#enter sib2, iclass 39, count 0 2006.168.07:45:38.17#ibcon#flushed, iclass 39, count 0 2006.168.07:45:38.17#ibcon#about to write, iclass 39, count 0 2006.168.07:45:38.17#ibcon#wrote, iclass 39, count 0 2006.168.07:45:38.17#ibcon#about to read 3, iclass 39, count 0 2006.168.07:45:38.19#ibcon#read 3, iclass 39, count 0 2006.168.07:45:38.19#ibcon#about to read 4, iclass 39, count 0 2006.168.07:45:38.19#ibcon#read 4, iclass 39, count 0 2006.168.07:45:38.19#ibcon#about to read 5, iclass 39, count 0 2006.168.07:45:38.19#ibcon#read 5, iclass 39, count 0 2006.168.07:45:38.19#ibcon#about to read 6, iclass 39, count 0 2006.168.07:45:38.19#ibcon#read 6, iclass 39, count 0 2006.168.07:45:38.19#ibcon#end of sib2, iclass 39, count 0 2006.168.07:45:38.19#ibcon#*mode == 0, iclass 39, count 0 2006.168.07:45:38.19#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.168.07:45:38.19#ibcon#[25=USB\r\n] 2006.168.07:45:38.19#ibcon#*before write, iclass 39, count 0 2006.168.07:45:38.19#ibcon#enter sib2, iclass 39, count 0 2006.168.07:45:38.19#ibcon#flushed, iclass 39, count 0 2006.168.07:45:38.19#ibcon#about to write, iclass 39, count 0 2006.168.07:45:38.19#ibcon#wrote, iclass 39, count 0 2006.168.07:45:38.19#ibcon#about to read 3, iclass 39, count 0 2006.168.07:45:38.21#ibcon#read 3, iclass 39, count 0 2006.168.07:45:38.22#ibcon#about to read 4, iclass 39, count 0 2006.168.07:45:38.22#ibcon#read 4, iclass 39, count 0 2006.168.07:45:38.22#ibcon#about to read 5, iclass 39, count 0 2006.168.07:45:38.22#ibcon#read 5, iclass 39, count 0 2006.168.07:45:38.22#ibcon#about to read 6, iclass 39, count 0 2006.168.07:45:38.22#ibcon#read 6, iclass 39, count 0 2006.168.07:45:38.22#ibcon#end of sib2, iclass 39, count 0 2006.168.07:45:38.22#ibcon#*after write, iclass 39, count 0 2006.168.07:45:38.22#ibcon#*before return 0, iclass 39, count 0 2006.168.07:45:38.22#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:45:38.22#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:45:38.22#ibcon#about to clear, iclass 39 cls_cnt 0 2006.168.07:45:38.22#ibcon#cleared, iclass 39 cls_cnt 0 2006.168.07:45:38.22$vc4f8/valo=2,572.99 2006.168.07:45:38.22#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.168.07:45:38.22#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.168.07:45:38.22#ibcon#ireg 17 cls_cnt 0 2006.168.07:45:38.22#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:45:38.22#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:45:38.22#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:45:38.22#ibcon#enter wrdev, iclass 3, count 0 2006.168.07:45:38.22#ibcon#first serial, iclass 3, count 0 2006.168.07:45:38.22#ibcon#enter sib2, iclass 3, count 0 2006.168.07:45:38.22#ibcon#flushed, iclass 3, count 0 2006.168.07:45:38.22#ibcon#about to write, iclass 3, count 0 2006.168.07:45:38.22#ibcon#wrote, iclass 3, count 0 2006.168.07:45:38.22#ibcon#about to read 3, iclass 3, count 0 2006.168.07:45:38.23#ibcon#read 3, iclass 3, count 0 2006.168.07:45:38.24#ibcon#about to read 4, iclass 3, count 0 2006.168.07:45:38.24#ibcon#read 4, iclass 3, count 0 2006.168.07:45:38.24#ibcon#about to read 5, iclass 3, count 0 2006.168.07:45:38.24#ibcon#read 5, iclass 3, count 0 2006.168.07:45:38.24#ibcon#about to read 6, iclass 3, count 0 2006.168.07:45:38.24#ibcon#read 6, iclass 3, count 0 2006.168.07:45:38.24#ibcon#end of sib2, iclass 3, count 0 2006.168.07:45:38.24#ibcon#*mode == 0, iclass 3, count 0 2006.168.07:45:38.24#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.168.07:45:38.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.07:45:38.24#ibcon#*before write, iclass 3, count 0 2006.168.07:45:38.24#ibcon#enter sib2, iclass 3, count 0 2006.168.07:45:38.24#ibcon#flushed, iclass 3, count 0 2006.168.07:45:38.24#ibcon#about to write, iclass 3, count 0 2006.168.07:45:38.24#ibcon#wrote, iclass 3, count 0 2006.168.07:45:38.24#ibcon#about to read 3, iclass 3, count 0 2006.168.07:45:38.28#ibcon#read 3, iclass 3, count 0 2006.168.07:45:38.28#ibcon#about to read 4, iclass 3, count 0 2006.168.07:45:38.28#ibcon#read 4, iclass 3, count 0 2006.168.07:45:38.28#ibcon#about to read 5, iclass 3, count 0 2006.168.07:45:38.28#ibcon#read 5, iclass 3, count 0 2006.168.07:45:38.28#ibcon#about to read 6, iclass 3, count 0 2006.168.07:45:38.28#ibcon#read 6, iclass 3, count 0 2006.168.07:45:38.28#ibcon#end of sib2, iclass 3, count 0 2006.168.07:45:38.28#ibcon#*after write, iclass 3, count 0 2006.168.07:45:38.28#ibcon#*before return 0, iclass 3, count 0 2006.168.07:45:38.28#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:45:38.28#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:45:38.28#ibcon#about to clear, iclass 3 cls_cnt 0 2006.168.07:45:38.28#ibcon#cleared, iclass 3 cls_cnt 0 2006.168.07:45:38.28$vc4f8/va=2,7 2006.168.07:45:38.28#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.168.07:45:38.28#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.168.07:45:38.28#ibcon#ireg 11 cls_cnt 2 2006.168.07:45:38.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:45:38.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:45:38.34#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:45:38.34#ibcon#enter wrdev, iclass 5, count 2 2006.168.07:45:38.34#ibcon#first serial, iclass 5, count 2 2006.168.07:45:38.34#ibcon#enter sib2, iclass 5, count 2 2006.168.07:45:38.34#ibcon#flushed, iclass 5, count 2 2006.168.07:45:38.34#ibcon#about to write, iclass 5, count 2 2006.168.07:45:38.34#ibcon#wrote, iclass 5, count 2 2006.168.07:45:38.34#ibcon#about to read 3, iclass 5, count 2 2006.168.07:45:38.36#ibcon#read 3, iclass 5, count 2 2006.168.07:45:38.36#ibcon#about to read 4, iclass 5, count 2 2006.168.07:45:38.36#ibcon#read 4, iclass 5, count 2 2006.168.07:45:38.36#ibcon#about to read 5, iclass 5, count 2 2006.168.07:45:38.36#ibcon#read 5, iclass 5, count 2 2006.168.07:45:38.36#ibcon#about to read 6, iclass 5, count 2 2006.168.07:45:38.36#ibcon#read 6, iclass 5, count 2 2006.168.07:45:38.36#ibcon#end of sib2, iclass 5, count 2 2006.168.07:45:38.36#ibcon#*mode == 0, iclass 5, count 2 2006.168.07:45:38.36#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.168.07:45:38.36#ibcon#[25=AT02-07\r\n] 2006.168.07:45:38.36#ibcon#*before write, iclass 5, count 2 2006.168.07:45:38.36#ibcon#enter sib2, iclass 5, count 2 2006.168.07:45:38.36#ibcon#flushed, iclass 5, count 2 2006.168.07:45:38.36#ibcon#about to write, iclass 5, count 2 2006.168.07:45:38.36#ibcon#wrote, iclass 5, count 2 2006.168.07:45:38.36#ibcon#about to read 3, iclass 5, count 2 2006.168.07:45:38.40#ibcon#read 3, iclass 5, count 2 2006.168.07:45:38.40#ibcon#about to read 4, iclass 5, count 2 2006.168.07:45:38.40#ibcon#read 4, iclass 5, count 2 2006.168.07:45:38.40#ibcon#about to read 5, iclass 5, count 2 2006.168.07:45:38.40#ibcon#read 5, iclass 5, count 2 2006.168.07:45:38.40#ibcon#about to read 6, iclass 5, count 2 2006.168.07:45:38.40#ibcon#read 6, iclass 5, count 2 2006.168.07:45:38.40#ibcon#end of sib2, iclass 5, count 2 2006.168.07:45:38.40#ibcon#*after write, iclass 5, count 2 2006.168.07:45:38.40#ibcon#*before return 0, iclass 5, count 2 2006.168.07:45:38.40#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:45:38.40#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:45:38.40#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.168.07:45:38.40#ibcon#ireg 7 cls_cnt 0 2006.168.07:45:38.40#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:45:38.51#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:45:38.52#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:45:38.52#ibcon#enter wrdev, iclass 5, count 0 2006.168.07:45:38.52#ibcon#first serial, iclass 5, count 0 2006.168.07:45:38.52#ibcon#enter sib2, iclass 5, count 0 2006.168.07:45:38.52#ibcon#flushed, iclass 5, count 0 2006.168.07:45:38.52#ibcon#about to write, iclass 5, count 0 2006.168.07:45:38.52#ibcon#wrote, iclass 5, count 0 2006.168.07:45:38.52#ibcon#about to read 3, iclass 5, count 0 2006.168.07:45:38.53#ibcon#read 3, iclass 5, count 0 2006.168.07:45:38.54#ibcon#about to read 4, iclass 5, count 0 2006.168.07:45:38.54#ibcon#read 4, iclass 5, count 0 2006.168.07:45:38.54#ibcon#about to read 5, iclass 5, count 0 2006.168.07:45:38.54#ibcon#read 5, iclass 5, count 0 2006.168.07:45:38.54#ibcon#about to read 6, iclass 5, count 0 2006.168.07:45:38.54#ibcon#read 6, iclass 5, count 0 2006.168.07:45:38.54#ibcon#end of sib2, iclass 5, count 0 2006.168.07:45:38.54#ibcon#*mode == 0, iclass 5, count 0 2006.168.07:45:38.54#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.168.07:45:38.54#ibcon#[25=USB\r\n] 2006.168.07:45:38.54#ibcon#*before write, iclass 5, count 0 2006.168.07:45:38.54#ibcon#enter sib2, iclass 5, count 0 2006.168.07:45:38.54#ibcon#flushed, iclass 5, count 0 2006.168.07:45:38.54#ibcon#about to write, iclass 5, count 0 2006.168.07:45:38.54#ibcon#wrote, iclass 5, count 0 2006.168.07:45:38.54#ibcon#about to read 3, iclass 5, count 0 2006.168.07:45:38.56#ibcon#read 3, iclass 5, count 0 2006.168.07:45:38.57#ibcon#about to read 4, iclass 5, count 0 2006.168.07:45:38.57#ibcon#read 4, iclass 5, count 0 2006.168.07:45:38.57#ibcon#about to read 5, iclass 5, count 0 2006.168.07:45:38.57#ibcon#read 5, iclass 5, count 0 2006.168.07:45:38.57#ibcon#about to read 6, iclass 5, count 0 2006.168.07:45:38.57#ibcon#read 6, iclass 5, count 0 2006.168.07:45:38.57#ibcon#end of sib2, iclass 5, count 0 2006.168.07:45:38.57#ibcon#*after write, iclass 5, count 0 2006.168.07:45:38.57#ibcon#*before return 0, iclass 5, count 0 2006.168.07:45:38.57#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:45:38.57#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:45:38.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.168.07:45:38.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.168.07:45:38.57$vc4f8/valo=3,672.99 2006.168.07:45:38.57#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.168.07:45:38.57#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.168.07:45:38.57#ibcon#ireg 17 cls_cnt 0 2006.168.07:45:38.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:45:38.57#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:45:38.57#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:45:38.57#ibcon#enter wrdev, iclass 7, count 0 2006.168.07:45:38.57#ibcon#first serial, iclass 7, count 0 2006.168.07:45:38.57#ibcon#enter sib2, iclass 7, count 0 2006.168.07:45:38.57#ibcon#flushed, iclass 7, count 0 2006.168.07:45:38.57#ibcon#about to write, iclass 7, count 0 2006.168.07:45:38.57#ibcon#wrote, iclass 7, count 0 2006.168.07:45:38.57#ibcon#about to read 3, iclass 7, count 0 2006.168.07:45:38.59#ibcon#read 3, iclass 7, count 0 2006.168.07:45:38.59#ibcon#about to read 4, iclass 7, count 0 2006.168.07:45:38.59#ibcon#read 4, iclass 7, count 0 2006.168.07:45:38.59#ibcon#about to read 5, iclass 7, count 0 2006.168.07:45:38.59#ibcon#read 5, iclass 7, count 0 2006.168.07:45:38.59#ibcon#about to read 6, iclass 7, count 0 2006.168.07:45:38.59#ibcon#read 6, iclass 7, count 0 2006.168.07:45:38.59#ibcon#end of sib2, iclass 7, count 0 2006.168.07:45:38.59#ibcon#*mode == 0, iclass 7, count 0 2006.168.07:45:38.59#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.168.07:45:38.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.07:45:38.59#ibcon#*before write, iclass 7, count 0 2006.168.07:45:38.59#ibcon#enter sib2, iclass 7, count 0 2006.168.07:45:38.59#ibcon#flushed, iclass 7, count 0 2006.168.07:45:38.59#ibcon#about to write, iclass 7, count 0 2006.168.07:45:38.59#ibcon#wrote, iclass 7, count 0 2006.168.07:45:38.59#ibcon#about to read 3, iclass 7, count 0 2006.168.07:45:38.63#ibcon#read 3, iclass 7, count 0 2006.168.07:45:38.63#ibcon#about to read 4, iclass 7, count 0 2006.168.07:45:38.63#ibcon#read 4, iclass 7, count 0 2006.168.07:45:38.63#ibcon#about to read 5, iclass 7, count 0 2006.168.07:45:38.63#ibcon#read 5, iclass 7, count 0 2006.168.07:45:38.63#ibcon#about to read 6, iclass 7, count 0 2006.168.07:45:38.63#ibcon#read 6, iclass 7, count 0 2006.168.07:45:38.63#ibcon#end of sib2, iclass 7, count 0 2006.168.07:45:38.63#ibcon#*after write, iclass 7, count 0 2006.168.07:45:38.63#ibcon#*before return 0, iclass 7, count 0 2006.168.07:45:38.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:45:38.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:45:38.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.168.07:45:38.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.168.07:45:38.63$vc4f8/va=3,6 2006.168.07:45:38.63#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.168.07:45:38.63#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.168.07:45:38.63#ibcon#ireg 11 cls_cnt 2 2006.168.07:45:38.63#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:45:38.68#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:45:38.69#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:45:38.69#ibcon#enter wrdev, iclass 11, count 2 2006.168.07:45:38.69#ibcon#first serial, iclass 11, count 2 2006.168.07:45:38.69#ibcon#enter sib2, iclass 11, count 2 2006.168.07:45:38.69#ibcon#flushed, iclass 11, count 2 2006.168.07:45:38.69#ibcon#about to write, iclass 11, count 2 2006.168.07:45:38.69#ibcon#wrote, iclass 11, count 2 2006.168.07:45:38.69#ibcon#about to read 3, iclass 11, count 2 2006.168.07:45:38.71#ibcon#read 3, iclass 11, count 2 2006.168.07:45:38.71#ibcon#about to read 4, iclass 11, count 2 2006.168.07:45:38.71#ibcon#read 4, iclass 11, count 2 2006.168.07:45:38.71#ibcon#about to read 5, iclass 11, count 2 2006.168.07:45:38.71#ibcon#read 5, iclass 11, count 2 2006.168.07:45:38.71#ibcon#about to read 6, iclass 11, count 2 2006.168.07:45:38.71#ibcon#read 6, iclass 11, count 2 2006.168.07:45:38.71#ibcon#end of sib2, iclass 11, count 2 2006.168.07:45:38.71#ibcon#*mode == 0, iclass 11, count 2 2006.168.07:45:38.71#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.168.07:45:38.71#ibcon#[25=AT03-06\r\n] 2006.168.07:45:38.71#ibcon#*before write, iclass 11, count 2 2006.168.07:45:38.71#ibcon#enter sib2, iclass 11, count 2 2006.168.07:45:38.71#ibcon#flushed, iclass 11, count 2 2006.168.07:45:38.71#ibcon#about to write, iclass 11, count 2 2006.168.07:45:38.71#ibcon#wrote, iclass 11, count 2 2006.168.07:45:38.71#ibcon#about to read 3, iclass 11, count 2 2006.168.07:45:38.75#ibcon#read 3, iclass 11, count 2 2006.168.07:45:38.75#ibcon#about to read 4, iclass 11, count 2 2006.168.07:45:38.75#ibcon#read 4, iclass 11, count 2 2006.168.07:45:38.75#ibcon#about to read 5, iclass 11, count 2 2006.168.07:45:38.75#ibcon#read 5, iclass 11, count 2 2006.168.07:45:38.75#ibcon#about to read 6, iclass 11, count 2 2006.168.07:45:38.75#ibcon#read 6, iclass 11, count 2 2006.168.07:45:38.75#ibcon#end of sib2, iclass 11, count 2 2006.168.07:45:38.75#ibcon#*after write, iclass 11, count 2 2006.168.07:45:38.75#ibcon#*before return 0, iclass 11, count 2 2006.168.07:45:38.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:45:38.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:45:38.75#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.168.07:45:38.75#ibcon#ireg 7 cls_cnt 0 2006.168.07:45:38.75#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:45:38.86#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:45:38.87#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:45:38.87#ibcon#enter wrdev, iclass 11, count 0 2006.168.07:45:38.87#ibcon#first serial, iclass 11, count 0 2006.168.07:45:38.87#ibcon#enter sib2, iclass 11, count 0 2006.168.07:45:38.87#ibcon#flushed, iclass 11, count 0 2006.168.07:45:38.87#ibcon#about to write, iclass 11, count 0 2006.168.07:45:38.87#ibcon#wrote, iclass 11, count 0 2006.168.07:45:38.87#ibcon#about to read 3, iclass 11, count 0 2006.168.07:45:38.88#ibcon#read 3, iclass 11, count 0 2006.168.07:45:38.89#ibcon#about to read 4, iclass 11, count 0 2006.168.07:45:38.89#ibcon#read 4, iclass 11, count 0 2006.168.07:45:38.89#ibcon#about to read 5, iclass 11, count 0 2006.168.07:45:38.89#ibcon#read 5, iclass 11, count 0 2006.168.07:45:38.89#ibcon#about to read 6, iclass 11, count 0 2006.168.07:45:38.89#ibcon#read 6, iclass 11, count 0 2006.168.07:45:38.89#ibcon#end of sib2, iclass 11, count 0 2006.168.07:45:38.89#ibcon#*mode == 0, iclass 11, count 0 2006.168.07:45:38.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.168.07:45:38.89#ibcon#[25=USB\r\n] 2006.168.07:45:38.89#ibcon#*before write, iclass 11, count 0 2006.168.07:45:38.89#ibcon#enter sib2, iclass 11, count 0 2006.168.07:45:38.89#ibcon#flushed, iclass 11, count 0 2006.168.07:45:38.89#ibcon#about to write, iclass 11, count 0 2006.168.07:45:38.89#ibcon#wrote, iclass 11, count 0 2006.168.07:45:38.89#ibcon#about to read 3, iclass 11, count 0 2006.168.07:45:38.91#ibcon#read 3, iclass 11, count 0 2006.168.07:45:38.92#ibcon#about to read 4, iclass 11, count 0 2006.168.07:45:38.92#ibcon#read 4, iclass 11, count 0 2006.168.07:45:38.92#ibcon#about to read 5, iclass 11, count 0 2006.168.07:45:38.92#ibcon#read 5, iclass 11, count 0 2006.168.07:45:38.92#ibcon#about to read 6, iclass 11, count 0 2006.168.07:45:38.92#ibcon#read 6, iclass 11, count 0 2006.168.07:45:38.92#ibcon#end of sib2, iclass 11, count 0 2006.168.07:45:38.92#ibcon#*after write, iclass 11, count 0 2006.168.07:45:38.92#ibcon#*before return 0, iclass 11, count 0 2006.168.07:45:38.92#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:45:38.92#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:45:38.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.168.07:45:38.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.168.07:45:38.92$vc4f8/valo=4,832.99 2006.168.07:45:38.92#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.168.07:45:38.92#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.168.07:45:38.92#ibcon#ireg 17 cls_cnt 0 2006.168.07:45:38.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:45:38.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:45:38.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:45:38.92#ibcon#enter wrdev, iclass 13, count 0 2006.168.07:45:38.92#ibcon#first serial, iclass 13, count 0 2006.168.07:45:38.92#ibcon#enter sib2, iclass 13, count 0 2006.168.07:45:38.92#ibcon#flushed, iclass 13, count 0 2006.168.07:45:38.92#ibcon#about to write, iclass 13, count 0 2006.168.07:45:38.92#ibcon#wrote, iclass 13, count 0 2006.168.07:45:38.92#ibcon#about to read 3, iclass 13, count 0 2006.168.07:45:38.93#ibcon#read 3, iclass 13, count 0 2006.168.07:45:38.94#ibcon#about to read 4, iclass 13, count 0 2006.168.07:45:38.94#ibcon#read 4, iclass 13, count 0 2006.168.07:45:38.94#ibcon#about to read 5, iclass 13, count 0 2006.168.07:45:38.94#ibcon#read 5, iclass 13, count 0 2006.168.07:45:38.94#ibcon#about to read 6, iclass 13, count 0 2006.168.07:45:38.94#ibcon#read 6, iclass 13, count 0 2006.168.07:45:38.94#ibcon#end of sib2, iclass 13, count 0 2006.168.07:45:38.94#ibcon#*mode == 0, iclass 13, count 0 2006.168.07:45:38.94#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.168.07:45:38.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.07:45:38.94#ibcon#*before write, iclass 13, count 0 2006.168.07:45:38.94#ibcon#enter sib2, iclass 13, count 0 2006.168.07:45:38.94#ibcon#flushed, iclass 13, count 0 2006.168.07:45:38.94#ibcon#about to write, iclass 13, count 0 2006.168.07:45:38.94#ibcon#wrote, iclass 13, count 0 2006.168.07:45:38.94#ibcon#about to read 3, iclass 13, count 0 2006.168.07:45:38.97#ibcon#read 3, iclass 13, count 0 2006.168.07:45:38.98#ibcon#about to read 4, iclass 13, count 0 2006.168.07:45:38.98#ibcon#read 4, iclass 13, count 0 2006.168.07:45:38.98#ibcon#about to read 5, iclass 13, count 0 2006.168.07:45:38.98#ibcon#read 5, iclass 13, count 0 2006.168.07:45:38.98#ibcon#about to read 6, iclass 13, count 0 2006.168.07:45:38.98#ibcon#read 6, iclass 13, count 0 2006.168.07:45:38.98#ibcon#end of sib2, iclass 13, count 0 2006.168.07:45:38.98#ibcon#*after write, iclass 13, count 0 2006.168.07:45:38.98#ibcon#*before return 0, iclass 13, count 0 2006.168.07:45:38.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:45:38.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:45:38.98#ibcon#about to clear, iclass 13 cls_cnt 0 2006.168.07:45:38.98#ibcon#cleared, iclass 13 cls_cnt 0 2006.168.07:45:38.98$vc4f8/va=4,7 2006.168.07:45:38.98#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.168.07:45:38.98#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.168.07:45:38.98#ibcon#ireg 11 cls_cnt 2 2006.168.07:45:38.98#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.168.07:45:39.03#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.168.07:45:39.04#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.168.07:45:39.04#ibcon#enter wrdev, iclass 15, count 2 2006.168.07:45:39.04#ibcon#first serial, iclass 15, count 2 2006.168.07:45:39.04#ibcon#enter sib2, iclass 15, count 2 2006.168.07:45:39.04#ibcon#flushed, iclass 15, count 2 2006.168.07:45:39.04#ibcon#about to write, iclass 15, count 2 2006.168.07:45:39.04#ibcon#wrote, iclass 15, count 2 2006.168.07:45:39.04#ibcon#about to read 3, iclass 15, count 2 2006.168.07:45:39.05#ibcon#read 3, iclass 15, count 2 2006.168.07:45:39.06#ibcon#about to read 4, iclass 15, count 2 2006.168.07:45:39.06#ibcon#read 4, iclass 15, count 2 2006.168.07:45:39.06#ibcon#about to read 5, iclass 15, count 2 2006.168.07:45:39.06#ibcon#read 5, iclass 15, count 2 2006.168.07:45:39.06#ibcon#about to read 6, iclass 15, count 2 2006.168.07:45:39.06#ibcon#read 6, iclass 15, count 2 2006.168.07:45:39.06#ibcon#end of sib2, iclass 15, count 2 2006.168.07:45:39.06#ibcon#*mode == 0, iclass 15, count 2 2006.168.07:45:39.06#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.168.07:45:39.06#ibcon#[25=AT04-07\r\n] 2006.168.07:45:39.06#ibcon#*before write, iclass 15, count 2 2006.168.07:45:39.06#ibcon#enter sib2, iclass 15, count 2 2006.168.07:45:39.06#ibcon#flushed, iclass 15, count 2 2006.168.07:45:39.06#ibcon#about to write, iclass 15, count 2 2006.168.07:45:39.06#ibcon#wrote, iclass 15, count 2 2006.168.07:45:39.06#ibcon#about to read 3, iclass 15, count 2 2006.168.07:45:39.08#ibcon#read 3, iclass 15, count 2 2006.168.07:45:39.09#ibcon#about to read 4, iclass 15, count 2 2006.168.07:45:39.09#ibcon#read 4, iclass 15, count 2 2006.168.07:45:39.09#ibcon#about to read 5, iclass 15, count 2 2006.168.07:45:39.09#ibcon#read 5, iclass 15, count 2 2006.168.07:45:39.09#ibcon#about to read 6, iclass 15, count 2 2006.168.07:45:39.09#ibcon#read 6, iclass 15, count 2 2006.168.07:45:39.09#ibcon#end of sib2, iclass 15, count 2 2006.168.07:45:39.09#ibcon#*after write, iclass 15, count 2 2006.168.07:45:39.09#ibcon#*before return 0, iclass 15, count 2 2006.168.07:45:39.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.168.07:45:39.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.168.07:45:39.09#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.168.07:45:39.09#ibcon#ireg 7 cls_cnt 0 2006.168.07:45:39.09#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.168.07:45:39.20#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.168.07:45:39.21#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.168.07:45:39.21#ibcon#enter wrdev, iclass 15, count 0 2006.168.07:45:39.21#ibcon#first serial, iclass 15, count 0 2006.168.07:45:39.21#ibcon#enter sib2, iclass 15, count 0 2006.168.07:45:39.21#ibcon#flushed, iclass 15, count 0 2006.168.07:45:39.21#ibcon#about to write, iclass 15, count 0 2006.168.07:45:39.21#ibcon#wrote, iclass 15, count 0 2006.168.07:45:39.21#ibcon#about to read 3, iclass 15, count 0 2006.168.07:45:39.22#ibcon#read 3, iclass 15, count 0 2006.168.07:45:39.23#ibcon#about to read 4, iclass 15, count 0 2006.168.07:45:39.23#ibcon#read 4, iclass 15, count 0 2006.168.07:45:39.23#ibcon#about to read 5, iclass 15, count 0 2006.168.07:45:39.23#ibcon#read 5, iclass 15, count 0 2006.168.07:45:39.23#ibcon#about to read 6, iclass 15, count 0 2006.168.07:45:39.23#ibcon#read 6, iclass 15, count 0 2006.168.07:45:39.23#ibcon#end of sib2, iclass 15, count 0 2006.168.07:45:39.23#ibcon#*mode == 0, iclass 15, count 0 2006.168.07:45:39.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.168.07:45:39.23#ibcon#[25=USB\r\n] 2006.168.07:45:39.23#ibcon#*before write, iclass 15, count 0 2006.168.07:45:39.23#ibcon#enter sib2, iclass 15, count 0 2006.168.07:45:39.23#ibcon#flushed, iclass 15, count 0 2006.168.07:45:39.23#ibcon#about to write, iclass 15, count 0 2006.168.07:45:39.23#ibcon#wrote, iclass 15, count 0 2006.168.07:45:39.23#ibcon#about to read 3, iclass 15, count 0 2006.168.07:45:39.25#ibcon#read 3, iclass 15, count 0 2006.168.07:45:39.26#ibcon#about to read 4, iclass 15, count 0 2006.168.07:45:39.26#ibcon#read 4, iclass 15, count 0 2006.168.07:45:39.26#ibcon#about to read 5, iclass 15, count 0 2006.168.07:45:39.26#ibcon#read 5, iclass 15, count 0 2006.168.07:45:39.26#ibcon#about to read 6, iclass 15, count 0 2006.168.07:45:39.26#ibcon#read 6, iclass 15, count 0 2006.168.07:45:39.26#ibcon#end of sib2, iclass 15, count 0 2006.168.07:45:39.26#ibcon#*after write, iclass 15, count 0 2006.168.07:45:39.26#ibcon#*before return 0, iclass 15, count 0 2006.168.07:45:39.26#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.168.07:45:39.26#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.168.07:45:39.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.168.07:45:39.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.168.07:45:39.26$vc4f8/valo=5,652.99 2006.168.07:45:39.26#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.168.07:45:39.26#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.168.07:45:39.26#ibcon#ireg 17 cls_cnt 0 2006.168.07:45:39.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:45:39.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:45:39.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:45:39.26#ibcon#enter wrdev, iclass 17, count 0 2006.168.07:45:39.26#ibcon#first serial, iclass 17, count 0 2006.168.07:45:39.26#ibcon#enter sib2, iclass 17, count 0 2006.168.07:45:39.26#ibcon#flushed, iclass 17, count 0 2006.168.07:45:39.26#ibcon#about to write, iclass 17, count 0 2006.168.07:45:39.26#ibcon#wrote, iclass 17, count 0 2006.168.07:45:39.26#ibcon#about to read 3, iclass 17, count 0 2006.168.07:45:39.27#ibcon#read 3, iclass 17, count 0 2006.168.07:45:39.28#ibcon#about to read 4, iclass 17, count 0 2006.168.07:45:39.28#ibcon#read 4, iclass 17, count 0 2006.168.07:45:39.28#ibcon#about to read 5, iclass 17, count 0 2006.168.07:45:39.28#ibcon#read 5, iclass 17, count 0 2006.168.07:45:39.28#ibcon#about to read 6, iclass 17, count 0 2006.168.07:45:39.28#ibcon#read 6, iclass 17, count 0 2006.168.07:45:39.28#ibcon#end of sib2, iclass 17, count 0 2006.168.07:45:39.28#ibcon#*mode == 0, iclass 17, count 0 2006.168.07:45:39.28#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.168.07:45:39.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.07:45:39.28#ibcon#*before write, iclass 17, count 0 2006.168.07:45:39.28#ibcon#enter sib2, iclass 17, count 0 2006.168.07:45:39.28#ibcon#flushed, iclass 17, count 0 2006.168.07:45:39.28#ibcon#about to write, iclass 17, count 0 2006.168.07:45:39.28#ibcon#wrote, iclass 17, count 0 2006.168.07:45:39.28#ibcon#about to read 3, iclass 17, count 0 2006.168.07:45:39.31#ibcon#read 3, iclass 17, count 0 2006.168.07:45:39.32#ibcon#about to read 4, iclass 17, count 0 2006.168.07:45:39.32#ibcon#read 4, iclass 17, count 0 2006.168.07:45:39.32#ibcon#about to read 5, iclass 17, count 0 2006.168.07:45:39.32#ibcon#read 5, iclass 17, count 0 2006.168.07:45:39.32#ibcon#about to read 6, iclass 17, count 0 2006.168.07:45:39.32#ibcon#read 6, iclass 17, count 0 2006.168.07:45:39.32#ibcon#end of sib2, iclass 17, count 0 2006.168.07:45:39.32#ibcon#*after write, iclass 17, count 0 2006.168.07:45:39.32#ibcon#*before return 0, iclass 17, count 0 2006.168.07:45:39.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:45:39.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:45:39.32#ibcon#about to clear, iclass 17 cls_cnt 0 2006.168.07:45:39.32#ibcon#cleared, iclass 17 cls_cnt 0 2006.168.07:45:39.32$vc4f8/va=5,7 2006.168.07:45:39.32#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.168.07:45:39.32#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.168.07:45:39.32#ibcon#ireg 11 cls_cnt 2 2006.168.07:45:39.32#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.168.07:45:39.37#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.168.07:45:39.38#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.168.07:45:39.38#ibcon#enter wrdev, iclass 19, count 2 2006.168.07:45:39.38#ibcon#first serial, iclass 19, count 2 2006.168.07:45:39.38#ibcon#enter sib2, iclass 19, count 2 2006.168.07:45:39.38#ibcon#flushed, iclass 19, count 2 2006.168.07:45:39.38#ibcon#about to write, iclass 19, count 2 2006.168.07:45:39.38#ibcon#wrote, iclass 19, count 2 2006.168.07:45:39.38#ibcon#about to read 3, iclass 19, count 2 2006.168.07:45:39.40#ibcon#read 3, iclass 19, count 2 2006.168.07:45:39.40#ibcon#about to read 4, iclass 19, count 2 2006.168.07:45:39.40#ibcon#read 4, iclass 19, count 2 2006.168.07:45:39.40#ibcon#about to read 5, iclass 19, count 2 2006.168.07:45:39.40#ibcon#read 5, iclass 19, count 2 2006.168.07:45:39.40#ibcon#about to read 6, iclass 19, count 2 2006.168.07:45:39.40#ibcon#read 6, iclass 19, count 2 2006.168.07:45:39.40#ibcon#end of sib2, iclass 19, count 2 2006.168.07:45:39.40#ibcon#*mode == 0, iclass 19, count 2 2006.168.07:45:39.40#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.168.07:45:39.40#ibcon#[25=AT05-07\r\n] 2006.168.07:45:39.40#ibcon#*before write, iclass 19, count 2 2006.168.07:45:39.40#ibcon#enter sib2, iclass 19, count 2 2006.168.07:45:39.40#ibcon#flushed, iclass 19, count 2 2006.168.07:45:39.40#ibcon#about to write, iclass 19, count 2 2006.168.07:45:39.40#ibcon#wrote, iclass 19, count 2 2006.168.07:45:39.40#ibcon#about to read 3, iclass 19, count 2 2006.168.07:45:39.42#ibcon#read 3, iclass 19, count 2 2006.168.07:45:39.43#ibcon#about to read 4, iclass 19, count 2 2006.168.07:45:39.43#ibcon#read 4, iclass 19, count 2 2006.168.07:45:39.43#ibcon#about to read 5, iclass 19, count 2 2006.168.07:45:39.43#ibcon#read 5, iclass 19, count 2 2006.168.07:45:39.43#ibcon#about to read 6, iclass 19, count 2 2006.168.07:45:39.43#ibcon#read 6, iclass 19, count 2 2006.168.07:45:39.43#ibcon#end of sib2, iclass 19, count 2 2006.168.07:45:39.43#ibcon#*after write, iclass 19, count 2 2006.168.07:45:39.43#ibcon#*before return 0, iclass 19, count 2 2006.168.07:45:39.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.168.07:45:39.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.168.07:45:39.43#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.168.07:45:39.43#ibcon#ireg 7 cls_cnt 0 2006.168.07:45:39.43#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.168.07:45:39.54#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.168.07:45:39.55#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.168.07:45:39.55#ibcon#enter wrdev, iclass 19, count 0 2006.168.07:45:39.55#ibcon#first serial, iclass 19, count 0 2006.168.07:45:39.55#ibcon#enter sib2, iclass 19, count 0 2006.168.07:45:39.55#ibcon#flushed, iclass 19, count 0 2006.168.07:45:39.55#ibcon#about to write, iclass 19, count 0 2006.168.07:45:39.55#ibcon#wrote, iclass 19, count 0 2006.168.07:45:39.55#ibcon#about to read 3, iclass 19, count 0 2006.168.07:45:39.56#ibcon#read 3, iclass 19, count 0 2006.168.07:45:39.57#ibcon#about to read 4, iclass 19, count 0 2006.168.07:45:39.57#ibcon#read 4, iclass 19, count 0 2006.168.07:45:39.57#ibcon#about to read 5, iclass 19, count 0 2006.168.07:45:39.57#ibcon#read 5, iclass 19, count 0 2006.168.07:45:39.57#ibcon#about to read 6, iclass 19, count 0 2006.168.07:45:39.57#ibcon#read 6, iclass 19, count 0 2006.168.07:45:39.57#ibcon#end of sib2, iclass 19, count 0 2006.168.07:45:39.57#ibcon#*mode == 0, iclass 19, count 0 2006.168.07:45:39.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.168.07:45:39.57#ibcon#[25=USB\r\n] 2006.168.07:45:39.57#ibcon#*before write, iclass 19, count 0 2006.168.07:45:39.57#ibcon#enter sib2, iclass 19, count 0 2006.168.07:45:39.57#ibcon#flushed, iclass 19, count 0 2006.168.07:45:39.57#ibcon#about to write, iclass 19, count 0 2006.168.07:45:39.57#ibcon#wrote, iclass 19, count 0 2006.168.07:45:39.57#ibcon#about to read 3, iclass 19, count 0 2006.168.07:45:39.59#ibcon#read 3, iclass 19, count 0 2006.168.07:45:39.60#ibcon#about to read 4, iclass 19, count 0 2006.168.07:45:39.60#ibcon#read 4, iclass 19, count 0 2006.168.07:45:39.60#ibcon#about to read 5, iclass 19, count 0 2006.168.07:45:39.60#ibcon#read 5, iclass 19, count 0 2006.168.07:45:39.60#ibcon#about to read 6, iclass 19, count 0 2006.168.07:45:39.60#ibcon#read 6, iclass 19, count 0 2006.168.07:45:39.60#ibcon#end of sib2, iclass 19, count 0 2006.168.07:45:39.60#ibcon#*after write, iclass 19, count 0 2006.168.07:45:39.60#ibcon#*before return 0, iclass 19, count 0 2006.168.07:45:39.60#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.168.07:45:39.60#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.168.07:45:39.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.168.07:45:39.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.168.07:45:39.60$vc4f8/valo=6,772.99 2006.168.07:45:39.60#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.168.07:45:39.60#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.168.07:45:39.60#ibcon#ireg 17 cls_cnt 0 2006.168.07:45:39.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.168.07:45:39.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.168.07:45:39.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.168.07:45:39.60#ibcon#enter wrdev, iclass 21, count 0 2006.168.07:45:39.60#ibcon#first serial, iclass 21, count 0 2006.168.07:45:39.60#ibcon#enter sib2, iclass 21, count 0 2006.168.07:45:39.60#ibcon#flushed, iclass 21, count 0 2006.168.07:45:39.60#ibcon#about to write, iclass 21, count 0 2006.168.07:45:39.60#ibcon#wrote, iclass 21, count 0 2006.168.07:45:39.60#ibcon#about to read 3, iclass 21, count 0 2006.168.07:45:39.62#ibcon#read 3, iclass 21, count 0 2006.168.07:45:39.62#ibcon#about to read 4, iclass 21, count 0 2006.168.07:45:39.62#ibcon#read 4, iclass 21, count 0 2006.168.07:45:39.62#ibcon#about to read 5, iclass 21, count 0 2006.168.07:45:39.62#ibcon#read 5, iclass 21, count 0 2006.168.07:45:39.62#ibcon#about to read 6, iclass 21, count 0 2006.168.07:45:39.62#ibcon#read 6, iclass 21, count 0 2006.168.07:45:39.62#ibcon#end of sib2, iclass 21, count 0 2006.168.07:45:39.62#ibcon#*mode == 0, iclass 21, count 0 2006.168.07:45:39.62#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.168.07:45:39.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.07:45:39.62#ibcon#*before write, iclass 21, count 0 2006.168.07:45:39.62#ibcon#enter sib2, iclass 21, count 0 2006.168.07:45:39.62#ibcon#flushed, iclass 21, count 0 2006.168.07:45:39.62#ibcon#about to write, iclass 21, count 0 2006.168.07:45:39.62#ibcon#wrote, iclass 21, count 0 2006.168.07:45:39.62#ibcon#about to read 3, iclass 21, count 0 2006.168.07:45:39.66#ibcon#read 3, iclass 21, count 0 2006.168.07:45:39.66#ibcon#about to read 4, iclass 21, count 0 2006.168.07:45:39.66#ibcon#read 4, iclass 21, count 0 2006.168.07:45:39.66#ibcon#about to read 5, iclass 21, count 0 2006.168.07:45:39.66#ibcon#read 5, iclass 21, count 0 2006.168.07:45:39.66#ibcon#about to read 6, iclass 21, count 0 2006.168.07:45:39.66#ibcon#read 6, iclass 21, count 0 2006.168.07:45:39.66#ibcon#end of sib2, iclass 21, count 0 2006.168.07:45:39.66#ibcon#*after write, iclass 21, count 0 2006.168.07:45:39.66#ibcon#*before return 0, iclass 21, count 0 2006.168.07:45:39.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.168.07:45:39.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.168.07:45:39.66#ibcon#about to clear, iclass 21 cls_cnt 0 2006.168.07:45:39.66#ibcon#cleared, iclass 21 cls_cnt 0 2006.168.07:45:39.66$vc4f8/va=6,6 2006.168.07:45:39.66#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.168.07:45:39.66#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.168.07:45:39.66#ibcon#ireg 11 cls_cnt 2 2006.168.07:45:39.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.168.07:45:39.71#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.168.07:45:39.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.168.07:45:39.72#ibcon#enter wrdev, iclass 23, count 2 2006.168.07:45:39.72#ibcon#first serial, iclass 23, count 2 2006.168.07:45:39.72#ibcon#enter sib2, iclass 23, count 2 2006.168.07:45:39.72#ibcon#flushed, iclass 23, count 2 2006.168.07:45:39.72#ibcon#about to write, iclass 23, count 2 2006.168.07:45:39.72#ibcon#wrote, iclass 23, count 2 2006.168.07:45:39.72#ibcon#about to read 3, iclass 23, count 2 2006.168.07:45:39.73#ibcon#read 3, iclass 23, count 2 2006.168.07:45:39.74#ibcon#about to read 4, iclass 23, count 2 2006.168.07:45:39.74#ibcon#read 4, iclass 23, count 2 2006.168.07:45:39.74#ibcon#about to read 5, iclass 23, count 2 2006.168.07:45:39.74#ibcon#read 5, iclass 23, count 2 2006.168.07:45:39.74#ibcon#about to read 6, iclass 23, count 2 2006.168.07:45:39.74#ibcon#read 6, iclass 23, count 2 2006.168.07:45:39.74#ibcon#end of sib2, iclass 23, count 2 2006.168.07:45:39.74#ibcon#*mode == 0, iclass 23, count 2 2006.168.07:45:39.74#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.168.07:45:39.74#ibcon#[25=AT06-06\r\n] 2006.168.07:45:39.74#ibcon#*before write, iclass 23, count 2 2006.168.07:45:39.74#ibcon#enter sib2, iclass 23, count 2 2006.168.07:45:39.74#ibcon#flushed, iclass 23, count 2 2006.168.07:45:39.74#ibcon#about to write, iclass 23, count 2 2006.168.07:45:39.74#ibcon#wrote, iclass 23, count 2 2006.168.07:45:39.74#ibcon#about to read 3, iclass 23, count 2 2006.168.07:45:39.76#ibcon#read 3, iclass 23, count 2 2006.168.07:45:39.77#ibcon#about to read 4, iclass 23, count 2 2006.168.07:45:39.77#ibcon#read 4, iclass 23, count 2 2006.168.07:45:39.77#ibcon#about to read 5, iclass 23, count 2 2006.168.07:45:39.77#ibcon#read 5, iclass 23, count 2 2006.168.07:45:39.77#ibcon#about to read 6, iclass 23, count 2 2006.168.07:45:39.77#ibcon#read 6, iclass 23, count 2 2006.168.07:45:39.77#ibcon#end of sib2, iclass 23, count 2 2006.168.07:45:39.77#ibcon#*after write, iclass 23, count 2 2006.168.07:45:39.77#ibcon#*before return 0, iclass 23, count 2 2006.168.07:45:39.77#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.168.07:45:39.77#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.168.07:45:39.77#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.168.07:45:39.77#ibcon#ireg 7 cls_cnt 0 2006.168.07:45:39.77#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.168.07:45:39.88#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.168.07:45:39.89#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.168.07:45:39.89#ibcon#enter wrdev, iclass 23, count 0 2006.168.07:45:39.89#ibcon#first serial, iclass 23, count 0 2006.168.07:45:39.89#ibcon#enter sib2, iclass 23, count 0 2006.168.07:45:39.89#ibcon#flushed, iclass 23, count 0 2006.168.07:45:39.89#ibcon#about to write, iclass 23, count 0 2006.168.07:45:39.89#ibcon#wrote, iclass 23, count 0 2006.168.07:45:39.89#ibcon#about to read 3, iclass 23, count 0 2006.168.07:45:39.90#ibcon#read 3, iclass 23, count 0 2006.168.07:45:39.91#ibcon#about to read 4, iclass 23, count 0 2006.168.07:45:39.91#ibcon#read 4, iclass 23, count 0 2006.168.07:45:39.91#ibcon#about to read 5, iclass 23, count 0 2006.168.07:45:39.91#ibcon#read 5, iclass 23, count 0 2006.168.07:45:39.91#ibcon#about to read 6, iclass 23, count 0 2006.168.07:45:39.91#ibcon#read 6, iclass 23, count 0 2006.168.07:45:39.91#ibcon#end of sib2, iclass 23, count 0 2006.168.07:45:39.91#ibcon#*mode == 0, iclass 23, count 0 2006.168.07:45:39.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.168.07:45:39.91#ibcon#[25=USB\r\n] 2006.168.07:45:39.91#ibcon#*before write, iclass 23, count 0 2006.168.07:45:39.91#ibcon#enter sib2, iclass 23, count 0 2006.168.07:45:39.91#ibcon#flushed, iclass 23, count 0 2006.168.07:45:39.91#ibcon#about to write, iclass 23, count 0 2006.168.07:45:39.91#ibcon#wrote, iclass 23, count 0 2006.168.07:45:39.91#ibcon#about to read 3, iclass 23, count 0 2006.168.07:45:39.93#ibcon#read 3, iclass 23, count 0 2006.168.07:45:39.94#ibcon#about to read 4, iclass 23, count 0 2006.168.07:45:39.94#ibcon#read 4, iclass 23, count 0 2006.168.07:45:39.94#ibcon#about to read 5, iclass 23, count 0 2006.168.07:45:39.94#ibcon#read 5, iclass 23, count 0 2006.168.07:45:39.94#ibcon#about to read 6, iclass 23, count 0 2006.168.07:45:39.94#ibcon#read 6, iclass 23, count 0 2006.168.07:45:39.94#ibcon#end of sib2, iclass 23, count 0 2006.168.07:45:39.94#ibcon#*after write, iclass 23, count 0 2006.168.07:45:39.94#ibcon#*before return 0, iclass 23, count 0 2006.168.07:45:39.94#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.168.07:45:39.94#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.168.07:45:39.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.168.07:45:39.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.168.07:45:39.94$vc4f8/valo=7,832.99 2006.168.07:45:39.94#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.168.07:45:39.94#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.168.07:45:39.94#ibcon#ireg 17 cls_cnt 0 2006.168.07:45:39.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.168.07:45:39.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.168.07:45:39.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.168.07:45:39.94#ibcon#enter wrdev, iclass 25, count 0 2006.168.07:45:39.94#ibcon#first serial, iclass 25, count 0 2006.168.07:45:39.94#ibcon#enter sib2, iclass 25, count 0 2006.168.07:45:39.94#ibcon#flushed, iclass 25, count 0 2006.168.07:45:39.94#ibcon#about to write, iclass 25, count 0 2006.168.07:45:39.94#ibcon#wrote, iclass 25, count 0 2006.168.07:45:39.94#ibcon#about to read 3, iclass 25, count 0 2006.168.07:45:39.95#ibcon#read 3, iclass 25, count 0 2006.168.07:45:39.96#ibcon#about to read 4, iclass 25, count 0 2006.168.07:45:39.96#ibcon#read 4, iclass 25, count 0 2006.168.07:45:39.96#ibcon#about to read 5, iclass 25, count 0 2006.168.07:45:39.96#ibcon#read 5, iclass 25, count 0 2006.168.07:45:39.96#ibcon#about to read 6, iclass 25, count 0 2006.168.07:45:39.96#ibcon#read 6, iclass 25, count 0 2006.168.07:45:39.96#ibcon#end of sib2, iclass 25, count 0 2006.168.07:45:39.96#ibcon#*mode == 0, iclass 25, count 0 2006.168.07:45:39.96#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.168.07:45:39.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.07:45:39.96#ibcon#*before write, iclass 25, count 0 2006.168.07:45:39.96#ibcon#enter sib2, iclass 25, count 0 2006.168.07:45:39.96#ibcon#flushed, iclass 25, count 0 2006.168.07:45:39.96#ibcon#about to write, iclass 25, count 0 2006.168.07:45:39.96#ibcon#wrote, iclass 25, count 0 2006.168.07:45:39.96#ibcon#about to read 3, iclass 25, count 0 2006.168.07:45:39.99#ibcon#read 3, iclass 25, count 0 2006.168.07:45:40.00#ibcon#about to read 4, iclass 25, count 0 2006.168.07:45:40.00#ibcon#read 4, iclass 25, count 0 2006.168.07:45:40.00#ibcon#about to read 5, iclass 25, count 0 2006.168.07:45:40.00#ibcon#read 5, iclass 25, count 0 2006.168.07:45:40.00#ibcon#about to read 6, iclass 25, count 0 2006.168.07:45:40.00#ibcon#read 6, iclass 25, count 0 2006.168.07:45:40.00#ibcon#end of sib2, iclass 25, count 0 2006.168.07:45:40.00#ibcon#*after write, iclass 25, count 0 2006.168.07:45:40.00#ibcon#*before return 0, iclass 25, count 0 2006.168.07:45:40.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.168.07:45:40.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.168.07:45:40.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.168.07:45:40.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.168.07:45:40.00$vc4f8/va=7,6 2006.168.07:45:40.00#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.168.07:45:40.00#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.168.07:45:40.00#ibcon#ireg 11 cls_cnt 2 2006.168.07:45:40.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.168.07:45:40.05#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.168.07:45:40.06#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.168.07:45:40.06#ibcon#enter wrdev, iclass 27, count 2 2006.168.07:45:40.06#ibcon#first serial, iclass 27, count 2 2006.168.07:45:40.06#ibcon#enter sib2, iclass 27, count 2 2006.168.07:45:40.06#ibcon#flushed, iclass 27, count 2 2006.168.07:45:40.06#ibcon#about to write, iclass 27, count 2 2006.168.07:45:40.06#ibcon#wrote, iclass 27, count 2 2006.168.07:45:40.06#ibcon#about to read 3, iclass 27, count 2 2006.168.07:45:40.08#ibcon#read 3, iclass 27, count 2 2006.168.07:45:40.08#ibcon#about to read 4, iclass 27, count 2 2006.168.07:45:40.08#ibcon#read 4, iclass 27, count 2 2006.168.07:45:40.08#ibcon#about to read 5, iclass 27, count 2 2006.168.07:45:40.08#ibcon#read 5, iclass 27, count 2 2006.168.07:45:40.08#ibcon#about to read 6, iclass 27, count 2 2006.168.07:45:40.08#ibcon#read 6, iclass 27, count 2 2006.168.07:45:40.08#ibcon#end of sib2, iclass 27, count 2 2006.168.07:45:40.08#ibcon#*mode == 0, iclass 27, count 2 2006.168.07:45:40.08#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.168.07:45:40.08#ibcon#[25=AT07-06\r\n] 2006.168.07:45:40.08#ibcon#*before write, iclass 27, count 2 2006.168.07:45:40.08#ibcon#enter sib2, iclass 27, count 2 2006.168.07:45:40.08#ibcon#flushed, iclass 27, count 2 2006.168.07:45:40.08#ibcon#about to write, iclass 27, count 2 2006.168.07:45:40.08#ibcon#wrote, iclass 27, count 2 2006.168.07:45:40.08#ibcon#about to read 3, iclass 27, count 2 2006.168.07:45:40.10#ibcon#read 3, iclass 27, count 2 2006.168.07:45:40.11#ibcon#about to read 4, iclass 27, count 2 2006.168.07:45:40.11#ibcon#read 4, iclass 27, count 2 2006.168.07:45:40.11#ibcon#about to read 5, iclass 27, count 2 2006.168.07:45:40.11#ibcon#read 5, iclass 27, count 2 2006.168.07:45:40.11#ibcon#about to read 6, iclass 27, count 2 2006.168.07:45:40.11#ibcon#read 6, iclass 27, count 2 2006.168.07:45:40.11#ibcon#end of sib2, iclass 27, count 2 2006.168.07:45:40.11#ibcon#*after write, iclass 27, count 2 2006.168.07:45:40.11#ibcon#*before return 0, iclass 27, count 2 2006.168.07:45:40.11#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.168.07:45:40.11#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.168.07:45:40.11#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.168.07:45:40.11#ibcon#ireg 7 cls_cnt 0 2006.168.07:45:40.11#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.168.07:45:40.22#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.168.07:45:40.23#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.168.07:45:40.23#ibcon#enter wrdev, iclass 27, count 0 2006.168.07:45:40.23#ibcon#first serial, iclass 27, count 0 2006.168.07:45:40.23#ibcon#enter sib2, iclass 27, count 0 2006.168.07:45:40.23#ibcon#flushed, iclass 27, count 0 2006.168.07:45:40.23#ibcon#about to write, iclass 27, count 0 2006.168.07:45:40.23#ibcon#wrote, iclass 27, count 0 2006.168.07:45:40.23#ibcon#about to read 3, iclass 27, count 0 2006.168.07:45:40.24#ibcon#read 3, iclass 27, count 0 2006.168.07:45:40.25#ibcon#about to read 4, iclass 27, count 0 2006.168.07:45:40.25#ibcon#read 4, iclass 27, count 0 2006.168.07:45:40.25#ibcon#about to read 5, iclass 27, count 0 2006.168.07:45:40.25#ibcon#read 5, iclass 27, count 0 2006.168.07:45:40.25#ibcon#about to read 6, iclass 27, count 0 2006.168.07:45:40.25#ibcon#read 6, iclass 27, count 0 2006.168.07:45:40.25#ibcon#end of sib2, iclass 27, count 0 2006.168.07:45:40.25#ibcon#*mode == 0, iclass 27, count 0 2006.168.07:45:40.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.168.07:45:40.25#ibcon#[25=USB\r\n] 2006.168.07:45:40.25#ibcon#*before write, iclass 27, count 0 2006.168.07:45:40.25#ibcon#enter sib2, iclass 27, count 0 2006.168.07:45:40.25#ibcon#flushed, iclass 27, count 0 2006.168.07:45:40.25#ibcon#about to write, iclass 27, count 0 2006.168.07:45:40.25#ibcon#wrote, iclass 27, count 0 2006.168.07:45:40.25#ibcon#about to read 3, iclass 27, count 0 2006.168.07:45:40.27#ibcon#read 3, iclass 27, count 0 2006.168.07:45:40.28#ibcon#about to read 4, iclass 27, count 0 2006.168.07:45:40.28#ibcon#read 4, iclass 27, count 0 2006.168.07:45:40.28#ibcon#about to read 5, iclass 27, count 0 2006.168.07:45:40.28#ibcon#read 5, iclass 27, count 0 2006.168.07:45:40.28#ibcon#about to read 6, iclass 27, count 0 2006.168.07:45:40.28#ibcon#read 6, iclass 27, count 0 2006.168.07:45:40.28#ibcon#end of sib2, iclass 27, count 0 2006.168.07:45:40.28#ibcon#*after write, iclass 27, count 0 2006.168.07:45:40.28#ibcon#*before return 0, iclass 27, count 0 2006.168.07:45:40.28#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.168.07:45:40.28#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.168.07:45:40.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.168.07:45:40.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.168.07:45:40.28$vc4f8/valo=8,852.99 2006.168.07:45:40.28#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.168.07:45:40.28#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.168.07:45:40.28#ibcon#ireg 17 cls_cnt 0 2006.168.07:45:40.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.168.07:45:40.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.168.07:45:40.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.168.07:45:40.28#ibcon#enter wrdev, iclass 29, count 0 2006.168.07:45:40.28#ibcon#first serial, iclass 29, count 0 2006.168.07:45:40.28#ibcon#enter sib2, iclass 29, count 0 2006.168.07:45:40.28#ibcon#flushed, iclass 29, count 0 2006.168.07:45:40.28#ibcon#about to write, iclass 29, count 0 2006.168.07:45:40.28#ibcon#wrote, iclass 29, count 0 2006.168.07:45:40.28#ibcon#about to read 3, iclass 29, count 0 2006.168.07:45:40.30#ibcon#read 3, iclass 29, count 0 2006.168.07:45:40.30#ibcon#about to read 4, iclass 29, count 0 2006.168.07:45:40.30#ibcon#read 4, iclass 29, count 0 2006.168.07:45:40.30#ibcon#about to read 5, iclass 29, count 0 2006.168.07:45:40.30#ibcon#read 5, iclass 29, count 0 2006.168.07:45:40.30#ibcon#about to read 6, iclass 29, count 0 2006.168.07:45:40.30#ibcon#read 6, iclass 29, count 0 2006.168.07:45:40.30#ibcon#end of sib2, iclass 29, count 0 2006.168.07:45:40.30#ibcon#*mode == 0, iclass 29, count 0 2006.168.07:45:40.30#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.168.07:45:40.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.07:45:40.30#ibcon#*before write, iclass 29, count 0 2006.168.07:45:40.30#ibcon#enter sib2, iclass 29, count 0 2006.168.07:45:40.30#ibcon#flushed, iclass 29, count 0 2006.168.07:45:40.30#ibcon#about to write, iclass 29, count 0 2006.168.07:45:40.30#ibcon#wrote, iclass 29, count 0 2006.168.07:45:40.30#ibcon#about to read 3, iclass 29, count 0 2006.168.07:45:40.33#ibcon#read 3, iclass 29, count 0 2006.168.07:45:40.34#ibcon#about to read 4, iclass 29, count 0 2006.168.07:45:40.34#ibcon#read 4, iclass 29, count 0 2006.168.07:45:40.34#ibcon#about to read 5, iclass 29, count 0 2006.168.07:45:40.34#ibcon#read 5, iclass 29, count 0 2006.168.07:45:40.34#ibcon#about to read 6, iclass 29, count 0 2006.168.07:45:40.34#ibcon#read 6, iclass 29, count 0 2006.168.07:45:40.34#ibcon#end of sib2, iclass 29, count 0 2006.168.07:45:40.34#ibcon#*after write, iclass 29, count 0 2006.168.07:45:40.34#ibcon#*before return 0, iclass 29, count 0 2006.168.07:45:40.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.168.07:45:40.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.168.07:45:40.34#ibcon#about to clear, iclass 29 cls_cnt 0 2006.168.07:45:40.34#ibcon#cleared, iclass 29 cls_cnt 0 2006.168.07:45:40.34$vc4f8/va=8,7 2006.168.07:45:40.34#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.168.07:45:40.34#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.168.07:45:40.34#ibcon#ireg 11 cls_cnt 2 2006.168.07:45:40.34#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.168.07:45:40.40#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.168.07:45:40.40#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.168.07:45:40.40#ibcon#enter wrdev, iclass 31, count 2 2006.168.07:45:40.40#ibcon#first serial, iclass 31, count 2 2006.168.07:45:40.40#ibcon#enter sib2, iclass 31, count 2 2006.168.07:45:40.40#ibcon#flushed, iclass 31, count 2 2006.168.07:45:40.40#ibcon#about to write, iclass 31, count 2 2006.168.07:45:40.40#ibcon#wrote, iclass 31, count 2 2006.168.07:45:40.40#ibcon#about to read 3, iclass 31, count 2 2006.168.07:45:40.42#ibcon#read 3, iclass 31, count 2 2006.168.07:45:40.42#ibcon#about to read 4, iclass 31, count 2 2006.168.07:45:40.42#ibcon#read 4, iclass 31, count 2 2006.168.07:45:40.42#ibcon#about to read 5, iclass 31, count 2 2006.168.07:45:40.42#ibcon#read 5, iclass 31, count 2 2006.168.07:45:40.42#ibcon#about to read 6, iclass 31, count 2 2006.168.07:45:40.42#ibcon#read 6, iclass 31, count 2 2006.168.07:45:40.42#ibcon#end of sib2, iclass 31, count 2 2006.168.07:45:40.42#ibcon#*mode == 0, iclass 31, count 2 2006.168.07:45:40.42#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.168.07:45:40.42#ibcon#[25=AT08-07\r\n] 2006.168.07:45:40.42#ibcon#*before write, iclass 31, count 2 2006.168.07:45:40.42#ibcon#enter sib2, iclass 31, count 2 2006.168.07:45:40.42#ibcon#flushed, iclass 31, count 2 2006.168.07:45:40.42#ibcon#about to write, iclass 31, count 2 2006.168.07:45:40.42#ibcon#wrote, iclass 31, count 2 2006.168.07:45:40.42#ibcon#about to read 3, iclass 31, count 2 2006.168.07:45:40.46#ibcon#read 3, iclass 31, count 2 2006.168.07:45:40.46#ibcon#about to read 4, iclass 31, count 2 2006.168.07:45:40.46#ibcon#read 4, iclass 31, count 2 2006.168.07:45:40.46#ibcon#about to read 5, iclass 31, count 2 2006.168.07:45:40.46#ibcon#read 5, iclass 31, count 2 2006.168.07:45:40.46#ibcon#about to read 6, iclass 31, count 2 2006.168.07:45:40.46#ibcon#read 6, iclass 31, count 2 2006.168.07:45:40.46#ibcon#end of sib2, iclass 31, count 2 2006.168.07:45:40.46#ibcon#*after write, iclass 31, count 2 2006.168.07:45:40.46#ibcon#*before return 0, iclass 31, count 2 2006.168.07:45:40.46#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.168.07:45:40.46#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.168.07:45:40.46#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.168.07:45:40.46#ibcon#ireg 7 cls_cnt 0 2006.168.07:45:40.46#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.168.07:45:40.57#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.168.07:45:40.58#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.168.07:45:40.58#ibcon#enter wrdev, iclass 31, count 0 2006.168.07:45:40.58#ibcon#first serial, iclass 31, count 0 2006.168.07:45:40.58#ibcon#enter sib2, iclass 31, count 0 2006.168.07:45:40.58#ibcon#flushed, iclass 31, count 0 2006.168.07:45:40.58#ibcon#about to write, iclass 31, count 0 2006.168.07:45:40.58#ibcon#wrote, iclass 31, count 0 2006.168.07:45:40.58#ibcon#about to read 3, iclass 31, count 0 2006.168.07:45:40.59#ibcon#read 3, iclass 31, count 0 2006.168.07:45:40.60#ibcon#about to read 4, iclass 31, count 0 2006.168.07:45:40.60#ibcon#read 4, iclass 31, count 0 2006.168.07:45:40.60#ibcon#about to read 5, iclass 31, count 0 2006.168.07:45:40.60#ibcon#read 5, iclass 31, count 0 2006.168.07:45:40.60#ibcon#about to read 6, iclass 31, count 0 2006.168.07:45:40.60#ibcon#read 6, iclass 31, count 0 2006.168.07:45:40.60#ibcon#end of sib2, iclass 31, count 0 2006.168.07:45:40.60#ibcon#*mode == 0, iclass 31, count 0 2006.168.07:45:40.60#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.168.07:45:40.60#ibcon#[25=USB\r\n] 2006.168.07:45:40.60#ibcon#*before write, iclass 31, count 0 2006.168.07:45:40.60#ibcon#enter sib2, iclass 31, count 0 2006.168.07:45:40.60#ibcon#flushed, iclass 31, count 0 2006.168.07:45:40.60#ibcon#about to write, iclass 31, count 0 2006.168.07:45:40.60#ibcon#wrote, iclass 31, count 0 2006.168.07:45:40.60#ibcon#about to read 3, iclass 31, count 0 2006.168.07:45:40.62#ibcon#read 3, iclass 31, count 0 2006.168.07:45:40.63#ibcon#about to read 4, iclass 31, count 0 2006.168.07:45:40.63#ibcon#read 4, iclass 31, count 0 2006.168.07:45:40.63#ibcon#about to read 5, iclass 31, count 0 2006.168.07:45:40.63#ibcon#read 5, iclass 31, count 0 2006.168.07:45:40.63#ibcon#about to read 6, iclass 31, count 0 2006.168.07:45:40.63#ibcon#read 6, iclass 31, count 0 2006.168.07:45:40.63#ibcon#end of sib2, iclass 31, count 0 2006.168.07:45:40.63#ibcon#*after write, iclass 31, count 0 2006.168.07:45:40.63#ibcon#*before return 0, iclass 31, count 0 2006.168.07:45:40.63#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.168.07:45:40.63#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.168.07:45:40.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.168.07:45:40.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.168.07:45:40.63$vc4f8/vblo=1,632.99 2006.168.07:45:40.63#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.168.07:45:40.63#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.168.07:45:40.63#ibcon#ireg 17 cls_cnt 0 2006.168.07:45:40.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.168.07:45:40.63#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.168.07:45:40.63#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.168.07:45:40.63#ibcon#enter wrdev, iclass 33, count 0 2006.168.07:45:40.63#ibcon#first serial, iclass 33, count 0 2006.168.07:45:40.63#ibcon#enter sib2, iclass 33, count 0 2006.168.07:45:40.63#ibcon#flushed, iclass 33, count 0 2006.168.07:45:40.63#ibcon#about to write, iclass 33, count 0 2006.168.07:45:40.63#ibcon#wrote, iclass 33, count 0 2006.168.07:45:40.63#ibcon#about to read 3, iclass 33, count 0 2006.168.07:45:40.64#ibcon#read 3, iclass 33, count 0 2006.168.07:45:40.65#ibcon#about to read 4, iclass 33, count 0 2006.168.07:45:40.65#ibcon#read 4, iclass 33, count 0 2006.168.07:45:40.65#ibcon#about to read 5, iclass 33, count 0 2006.168.07:45:40.65#ibcon#read 5, iclass 33, count 0 2006.168.07:45:40.65#ibcon#about to read 6, iclass 33, count 0 2006.168.07:45:40.65#ibcon#read 6, iclass 33, count 0 2006.168.07:45:40.65#ibcon#end of sib2, iclass 33, count 0 2006.168.07:45:40.65#ibcon#*mode == 0, iclass 33, count 0 2006.168.07:45:40.65#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.168.07:45:40.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.07:45:40.65#ibcon#*before write, iclass 33, count 0 2006.168.07:45:40.65#ibcon#enter sib2, iclass 33, count 0 2006.168.07:45:40.65#ibcon#flushed, iclass 33, count 0 2006.168.07:45:40.65#ibcon#about to write, iclass 33, count 0 2006.168.07:45:40.65#ibcon#wrote, iclass 33, count 0 2006.168.07:45:40.65#ibcon#about to read 3, iclass 33, count 0 2006.168.07:45:40.68#ibcon#read 3, iclass 33, count 0 2006.168.07:45:40.69#ibcon#about to read 4, iclass 33, count 0 2006.168.07:45:40.69#ibcon#read 4, iclass 33, count 0 2006.168.07:45:40.69#ibcon#about to read 5, iclass 33, count 0 2006.168.07:45:40.69#ibcon#read 5, iclass 33, count 0 2006.168.07:45:40.69#ibcon#about to read 6, iclass 33, count 0 2006.168.07:45:40.69#ibcon#read 6, iclass 33, count 0 2006.168.07:45:40.69#ibcon#end of sib2, iclass 33, count 0 2006.168.07:45:40.69#ibcon#*after write, iclass 33, count 0 2006.168.07:45:40.69#ibcon#*before return 0, iclass 33, count 0 2006.168.07:45:40.69#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.168.07:45:40.69#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.168.07:45:40.69#ibcon#about to clear, iclass 33 cls_cnt 0 2006.168.07:45:40.69#ibcon#cleared, iclass 33 cls_cnt 0 2006.168.07:45:40.69$vc4f8/vb=1,4 2006.168.07:45:40.69#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.168.07:45:40.69#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.168.07:45:40.69#ibcon#ireg 11 cls_cnt 2 2006.168.07:45:40.69#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:45:40.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:45:40.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:45:40.69#ibcon#enter wrdev, iclass 35, count 2 2006.168.07:45:40.69#ibcon#first serial, iclass 35, count 2 2006.168.07:45:40.69#ibcon#enter sib2, iclass 35, count 2 2006.168.07:45:40.69#ibcon#flushed, iclass 35, count 2 2006.168.07:45:40.69#ibcon#about to write, iclass 35, count 2 2006.168.07:45:40.69#ibcon#wrote, iclass 35, count 2 2006.168.07:45:40.69#ibcon#about to read 3, iclass 35, count 2 2006.168.07:45:40.70#ibcon#read 3, iclass 35, count 2 2006.168.07:45:40.71#ibcon#about to read 4, iclass 35, count 2 2006.168.07:45:40.71#ibcon#read 4, iclass 35, count 2 2006.168.07:45:40.71#ibcon#about to read 5, iclass 35, count 2 2006.168.07:45:40.71#ibcon#read 5, iclass 35, count 2 2006.168.07:45:40.71#ibcon#about to read 6, iclass 35, count 2 2006.168.07:45:40.71#ibcon#read 6, iclass 35, count 2 2006.168.07:45:40.71#ibcon#end of sib2, iclass 35, count 2 2006.168.07:45:40.71#ibcon#*mode == 0, iclass 35, count 2 2006.168.07:45:40.71#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.168.07:45:40.71#ibcon#[27=AT01-04\r\n] 2006.168.07:45:40.71#ibcon#*before write, iclass 35, count 2 2006.168.07:45:40.71#ibcon#enter sib2, iclass 35, count 2 2006.168.07:45:40.71#ibcon#flushed, iclass 35, count 2 2006.168.07:45:40.71#ibcon#about to write, iclass 35, count 2 2006.168.07:45:40.71#ibcon#wrote, iclass 35, count 2 2006.168.07:45:40.71#ibcon#about to read 3, iclass 35, count 2 2006.168.07:45:40.73#ibcon#read 3, iclass 35, count 2 2006.168.07:45:40.74#ibcon#about to read 4, iclass 35, count 2 2006.168.07:45:40.74#ibcon#read 4, iclass 35, count 2 2006.168.07:45:40.74#ibcon#about to read 5, iclass 35, count 2 2006.168.07:45:40.74#ibcon#read 5, iclass 35, count 2 2006.168.07:45:40.74#ibcon#about to read 6, iclass 35, count 2 2006.168.07:45:40.74#ibcon#read 6, iclass 35, count 2 2006.168.07:45:40.74#ibcon#end of sib2, iclass 35, count 2 2006.168.07:45:40.74#ibcon#*after write, iclass 35, count 2 2006.168.07:45:40.74#ibcon#*before return 0, iclass 35, count 2 2006.168.07:45:40.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:45:40.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:45:40.74#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.168.07:45:40.74#ibcon#ireg 7 cls_cnt 0 2006.168.07:45:40.74#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:45:40.85#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:45:40.86#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:45:40.86#ibcon#enter wrdev, iclass 35, count 0 2006.168.07:45:40.86#ibcon#first serial, iclass 35, count 0 2006.168.07:45:40.86#ibcon#enter sib2, iclass 35, count 0 2006.168.07:45:40.86#ibcon#flushed, iclass 35, count 0 2006.168.07:45:40.86#ibcon#about to write, iclass 35, count 0 2006.168.07:45:40.86#ibcon#wrote, iclass 35, count 0 2006.168.07:45:40.86#ibcon#about to read 3, iclass 35, count 0 2006.168.07:45:40.87#ibcon#read 3, iclass 35, count 0 2006.168.07:45:40.88#ibcon#about to read 4, iclass 35, count 0 2006.168.07:45:40.88#ibcon#read 4, iclass 35, count 0 2006.168.07:45:40.88#ibcon#about to read 5, iclass 35, count 0 2006.168.07:45:40.88#ibcon#read 5, iclass 35, count 0 2006.168.07:45:40.88#ibcon#about to read 6, iclass 35, count 0 2006.168.07:45:40.88#ibcon#read 6, iclass 35, count 0 2006.168.07:45:40.88#ibcon#end of sib2, iclass 35, count 0 2006.168.07:45:40.88#ibcon#*mode == 0, iclass 35, count 0 2006.168.07:45:40.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.168.07:45:40.88#ibcon#[27=USB\r\n] 2006.168.07:45:40.88#ibcon#*before write, iclass 35, count 0 2006.168.07:45:40.88#ibcon#enter sib2, iclass 35, count 0 2006.168.07:45:40.88#ibcon#flushed, iclass 35, count 0 2006.168.07:45:40.88#ibcon#about to write, iclass 35, count 0 2006.168.07:45:40.88#ibcon#wrote, iclass 35, count 0 2006.168.07:45:40.88#ibcon#about to read 3, iclass 35, count 0 2006.168.07:45:40.91#ibcon#read 3, iclass 35, count 0 2006.168.07:45:40.91#ibcon#about to read 4, iclass 35, count 0 2006.168.07:45:40.91#ibcon#read 4, iclass 35, count 0 2006.168.07:45:40.91#ibcon#about to read 5, iclass 35, count 0 2006.168.07:45:40.91#ibcon#read 5, iclass 35, count 0 2006.168.07:45:40.91#ibcon#about to read 6, iclass 35, count 0 2006.168.07:45:40.91#ibcon#read 6, iclass 35, count 0 2006.168.07:45:40.91#ibcon#end of sib2, iclass 35, count 0 2006.168.07:45:40.91#ibcon#*after write, iclass 35, count 0 2006.168.07:45:40.91#ibcon#*before return 0, iclass 35, count 0 2006.168.07:45:40.91#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:45:40.91#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:45:40.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.168.07:45:40.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.168.07:45:40.91$vc4f8/vblo=2,640.99 2006.168.07:45:40.91#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.168.07:45:40.91#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.168.07:45:40.91#ibcon#ireg 17 cls_cnt 0 2006.168.07:45:40.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:45:40.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:45:40.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:45:40.91#ibcon#enter wrdev, iclass 37, count 0 2006.168.07:45:40.91#ibcon#first serial, iclass 37, count 0 2006.168.07:45:40.91#ibcon#enter sib2, iclass 37, count 0 2006.168.07:45:40.91#ibcon#flushed, iclass 37, count 0 2006.168.07:45:40.91#ibcon#about to write, iclass 37, count 0 2006.168.07:45:40.91#ibcon#wrote, iclass 37, count 0 2006.168.07:45:40.91#ibcon#about to read 3, iclass 37, count 0 2006.168.07:45:40.92#ibcon#read 3, iclass 37, count 0 2006.168.07:45:40.93#ibcon#about to read 4, iclass 37, count 0 2006.168.07:45:40.93#ibcon#read 4, iclass 37, count 0 2006.168.07:45:40.93#ibcon#about to read 5, iclass 37, count 0 2006.168.07:45:40.93#ibcon#read 5, iclass 37, count 0 2006.168.07:45:40.93#ibcon#about to read 6, iclass 37, count 0 2006.168.07:45:40.93#ibcon#read 6, iclass 37, count 0 2006.168.07:45:40.93#ibcon#end of sib2, iclass 37, count 0 2006.168.07:45:40.93#ibcon#*mode == 0, iclass 37, count 0 2006.168.07:45:40.93#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.168.07:45:40.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.07:45:40.93#ibcon#*before write, iclass 37, count 0 2006.168.07:45:40.93#ibcon#enter sib2, iclass 37, count 0 2006.168.07:45:40.93#ibcon#flushed, iclass 37, count 0 2006.168.07:45:40.93#ibcon#about to write, iclass 37, count 0 2006.168.07:45:40.93#ibcon#wrote, iclass 37, count 0 2006.168.07:45:40.93#ibcon#about to read 3, iclass 37, count 0 2006.168.07:45:40.96#ibcon#read 3, iclass 37, count 0 2006.168.07:45:40.97#ibcon#about to read 4, iclass 37, count 0 2006.168.07:45:40.97#ibcon#read 4, iclass 37, count 0 2006.168.07:45:40.97#ibcon#about to read 5, iclass 37, count 0 2006.168.07:45:40.97#ibcon#read 5, iclass 37, count 0 2006.168.07:45:40.97#ibcon#about to read 6, iclass 37, count 0 2006.168.07:45:40.97#ibcon#read 6, iclass 37, count 0 2006.168.07:45:40.97#ibcon#end of sib2, iclass 37, count 0 2006.168.07:45:40.97#ibcon#*after write, iclass 37, count 0 2006.168.07:45:40.97#ibcon#*before return 0, iclass 37, count 0 2006.168.07:45:40.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:45:40.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:45:40.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.168.07:45:40.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.168.07:45:40.97$vc4f8/vb=2,4 2006.168.07:45:40.97#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.168.07:45:40.97#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.168.07:45:40.97#ibcon#ireg 11 cls_cnt 2 2006.168.07:45:40.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:45:41.02#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:45:41.02#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:45:41.03#ibcon#enter wrdev, iclass 39, count 2 2006.168.07:45:41.03#ibcon#first serial, iclass 39, count 2 2006.168.07:45:41.03#ibcon#enter sib2, iclass 39, count 2 2006.168.07:45:41.03#ibcon#flushed, iclass 39, count 2 2006.168.07:45:41.03#ibcon#about to write, iclass 39, count 2 2006.168.07:45:41.03#ibcon#wrote, iclass 39, count 2 2006.168.07:45:41.03#ibcon#about to read 3, iclass 39, count 2 2006.168.07:45:41.04#ibcon#read 3, iclass 39, count 2 2006.168.07:45:41.05#ibcon#about to read 4, iclass 39, count 2 2006.168.07:45:41.05#ibcon#read 4, iclass 39, count 2 2006.168.07:45:41.05#ibcon#about to read 5, iclass 39, count 2 2006.168.07:45:41.05#ibcon#read 5, iclass 39, count 2 2006.168.07:45:41.05#ibcon#about to read 6, iclass 39, count 2 2006.168.07:45:41.05#ibcon#read 6, iclass 39, count 2 2006.168.07:45:41.05#ibcon#end of sib2, iclass 39, count 2 2006.168.07:45:41.05#ibcon#*mode == 0, iclass 39, count 2 2006.168.07:45:41.05#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.168.07:45:41.05#ibcon#[27=AT02-04\r\n] 2006.168.07:45:41.05#ibcon#*before write, iclass 39, count 2 2006.168.07:45:41.05#ibcon#enter sib2, iclass 39, count 2 2006.168.07:45:41.05#ibcon#flushed, iclass 39, count 2 2006.168.07:45:41.05#ibcon#about to write, iclass 39, count 2 2006.168.07:45:41.05#ibcon#wrote, iclass 39, count 2 2006.168.07:45:41.05#ibcon#about to read 3, iclass 39, count 2 2006.168.07:45:41.07#ibcon#read 3, iclass 39, count 2 2006.168.07:45:41.08#ibcon#about to read 4, iclass 39, count 2 2006.168.07:45:41.08#ibcon#read 4, iclass 39, count 2 2006.168.07:45:41.08#ibcon#about to read 5, iclass 39, count 2 2006.168.07:45:41.08#ibcon#read 5, iclass 39, count 2 2006.168.07:45:41.08#ibcon#about to read 6, iclass 39, count 2 2006.168.07:45:41.08#ibcon#read 6, iclass 39, count 2 2006.168.07:45:41.08#ibcon#end of sib2, iclass 39, count 2 2006.168.07:45:41.08#ibcon#*after write, iclass 39, count 2 2006.168.07:45:41.08#ibcon#*before return 0, iclass 39, count 2 2006.168.07:45:41.08#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:45:41.08#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:45:41.08#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.168.07:45:41.08#ibcon#ireg 7 cls_cnt 0 2006.168.07:45:41.08#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:45:41.20#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:45:41.20#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:45:41.20#ibcon#enter wrdev, iclass 39, count 0 2006.168.07:45:41.20#ibcon#first serial, iclass 39, count 0 2006.168.07:45:41.20#ibcon#enter sib2, iclass 39, count 0 2006.168.07:45:41.20#ibcon#flushed, iclass 39, count 0 2006.168.07:45:41.20#ibcon#about to write, iclass 39, count 0 2006.168.07:45:41.20#ibcon#wrote, iclass 39, count 0 2006.168.07:45:41.20#ibcon#about to read 3, iclass 39, count 0 2006.168.07:45:41.22#ibcon#read 3, iclass 39, count 0 2006.168.07:45:41.22#ibcon#about to read 4, iclass 39, count 0 2006.168.07:45:41.22#ibcon#read 4, iclass 39, count 0 2006.168.07:45:41.22#ibcon#about to read 5, iclass 39, count 0 2006.168.07:45:41.22#ibcon#read 5, iclass 39, count 0 2006.168.07:45:41.22#ibcon#about to read 6, iclass 39, count 0 2006.168.07:45:41.22#ibcon#read 6, iclass 39, count 0 2006.168.07:45:41.22#ibcon#end of sib2, iclass 39, count 0 2006.168.07:45:41.22#ibcon#*mode == 0, iclass 39, count 0 2006.168.07:45:41.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.168.07:45:41.22#ibcon#[27=USB\r\n] 2006.168.07:45:41.22#ibcon#*before write, iclass 39, count 0 2006.168.07:45:41.22#ibcon#enter sib2, iclass 39, count 0 2006.168.07:45:41.22#ibcon#flushed, iclass 39, count 0 2006.168.07:45:41.22#ibcon#about to write, iclass 39, count 0 2006.168.07:45:41.22#ibcon#wrote, iclass 39, count 0 2006.168.07:45:41.22#ibcon#about to read 3, iclass 39, count 0 2006.168.07:45:41.24#ibcon#read 3, iclass 39, count 0 2006.168.07:45:41.25#ibcon#about to read 4, iclass 39, count 0 2006.168.07:45:41.25#ibcon#read 4, iclass 39, count 0 2006.168.07:45:41.25#ibcon#about to read 5, iclass 39, count 0 2006.168.07:45:41.25#ibcon#read 5, iclass 39, count 0 2006.168.07:45:41.25#ibcon#about to read 6, iclass 39, count 0 2006.168.07:45:41.25#ibcon#read 6, iclass 39, count 0 2006.168.07:45:41.25#ibcon#end of sib2, iclass 39, count 0 2006.168.07:45:41.25#ibcon#*after write, iclass 39, count 0 2006.168.07:45:41.25#ibcon#*before return 0, iclass 39, count 0 2006.168.07:45:41.25#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:45:41.25#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:45:41.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.168.07:45:41.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.168.07:45:41.25$vc4f8/vblo=3,656.99 2006.168.07:45:41.25#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.168.07:45:41.25#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.168.07:45:41.25#ibcon#ireg 17 cls_cnt 0 2006.168.07:45:41.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:45:41.25#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:45:41.25#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:45:41.25#ibcon#enter wrdev, iclass 3, count 0 2006.168.07:45:41.25#ibcon#first serial, iclass 3, count 0 2006.168.07:45:41.25#ibcon#enter sib2, iclass 3, count 0 2006.168.07:45:41.25#ibcon#flushed, iclass 3, count 0 2006.168.07:45:41.25#ibcon#about to write, iclass 3, count 0 2006.168.07:45:41.25#ibcon#wrote, iclass 3, count 0 2006.168.07:45:41.25#ibcon#about to read 3, iclass 3, count 0 2006.168.07:45:41.26#ibcon#read 3, iclass 3, count 0 2006.168.07:45:41.27#ibcon#about to read 4, iclass 3, count 0 2006.168.07:45:41.27#ibcon#read 4, iclass 3, count 0 2006.168.07:45:41.27#ibcon#about to read 5, iclass 3, count 0 2006.168.07:45:41.27#ibcon#read 5, iclass 3, count 0 2006.168.07:45:41.27#ibcon#about to read 6, iclass 3, count 0 2006.168.07:45:41.27#ibcon#read 6, iclass 3, count 0 2006.168.07:45:41.27#ibcon#end of sib2, iclass 3, count 0 2006.168.07:45:41.27#ibcon#*mode == 0, iclass 3, count 0 2006.168.07:45:41.27#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.168.07:45:41.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.07:45:41.27#ibcon#*before write, iclass 3, count 0 2006.168.07:45:41.27#ibcon#enter sib2, iclass 3, count 0 2006.168.07:45:41.27#ibcon#flushed, iclass 3, count 0 2006.168.07:45:41.27#ibcon#about to write, iclass 3, count 0 2006.168.07:45:41.27#ibcon#wrote, iclass 3, count 0 2006.168.07:45:41.27#ibcon#about to read 3, iclass 3, count 0 2006.168.07:45:41.30#ibcon#read 3, iclass 3, count 0 2006.168.07:45:41.31#ibcon#about to read 4, iclass 3, count 0 2006.168.07:45:41.31#ibcon#read 4, iclass 3, count 0 2006.168.07:45:41.31#ibcon#about to read 5, iclass 3, count 0 2006.168.07:45:41.31#ibcon#read 5, iclass 3, count 0 2006.168.07:45:41.31#ibcon#about to read 6, iclass 3, count 0 2006.168.07:45:41.31#ibcon#read 6, iclass 3, count 0 2006.168.07:45:41.31#ibcon#end of sib2, iclass 3, count 0 2006.168.07:45:41.31#ibcon#*after write, iclass 3, count 0 2006.168.07:45:41.31#ibcon#*before return 0, iclass 3, count 0 2006.168.07:45:41.31#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:45:41.31#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:45:41.31#ibcon#about to clear, iclass 3 cls_cnt 0 2006.168.07:45:41.31#ibcon#cleared, iclass 3 cls_cnt 0 2006.168.07:45:41.31$vc4f8/vb=3,4 2006.168.07:45:41.31#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.168.07:45:41.31#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.168.07:45:41.31#ibcon#ireg 11 cls_cnt 2 2006.168.07:45:41.31#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:45:41.37#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:45:41.37#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:45:41.37#ibcon#enter wrdev, iclass 5, count 2 2006.168.07:45:41.37#ibcon#first serial, iclass 5, count 2 2006.168.07:45:41.37#ibcon#enter sib2, iclass 5, count 2 2006.168.07:45:41.37#ibcon#flushed, iclass 5, count 2 2006.168.07:45:41.37#ibcon#about to write, iclass 5, count 2 2006.168.07:45:41.37#ibcon#wrote, iclass 5, count 2 2006.168.07:45:41.37#ibcon#about to read 3, iclass 5, count 2 2006.168.07:45:41.38#ibcon#read 3, iclass 5, count 2 2006.168.07:45:41.39#ibcon#about to read 4, iclass 5, count 2 2006.168.07:45:41.39#ibcon#read 4, iclass 5, count 2 2006.168.07:45:41.39#ibcon#about to read 5, iclass 5, count 2 2006.168.07:45:41.39#ibcon#read 5, iclass 5, count 2 2006.168.07:45:41.39#ibcon#about to read 6, iclass 5, count 2 2006.168.07:45:41.39#ibcon#read 6, iclass 5, count 2 2006.168.07:45:41.39#ibcon#end of sib2, iclass 5, count 2 2006.168.07:45:41.39#ibcon#*mode == 0, iclass 5, count 2 2006.168.07:45:41.39#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.168.07:45:41.39#ibcon#[27=AT03-04\r\n] 2006.168.07:45:41.39#ibcon#*before write, iclass 5, count 2 2006.168.07:45:41.39#ibcon#enter sib2, iclass 5, count 2 2006.168.07:45:41.39#ibcon#flushed, iclass 5, count 2 2006.168.07:45:41.39#ibcon#about to write, iclass 5, count 2 2006.168.07:45:41.39#ibcon#wrote, iclass 5, count 2 2006.168.07:45:41.39#ibcon#about to read 3, iclass 5, count 2 2006.168.07:45:41.41#ibcon#read 3, iclass 5, count 2 2006.168.07:45:41.42#ibcon#about to read 4, iclass 5, count 2 2006.168.07:45:41.42#ibcon#read 4, iclass 5, count 2 2006.168.07:45:41.42#ibcon#about to read 5, iclass 5, count 2 2006.168.07:45:41.42#ibcon#read 5, iclass 5, count 2 2006.168.07:45:41.42#ibcon#about to read 6, iclass 5, count 2 2006.168.07:45:41.42#ibcon#read 6, iclass 5, count 2 2006.168.07:45:41.42#ibcon#end of sib2, iclass 5, count 2 2006.168.07:45:41.42#ibcon#*after write, iclass 5, count 2 2006.168.07:45:41.42#ibcon#*before return 0, iclass 5, count 2 2006.168.07:45:41.42#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:45:41.42#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:45:41.42#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.168.07:45:41.42#ibcon#ireg 7 cls_cnt 0 2006.168.07:45:41.42#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:45:41.53#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:45:41.54#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:45:41.54#ibcon#enter wrdev, iclass 5, count 0 2006.168.07:45:41.54#ibcon#first serial, iclass 5, count 0 2006.168.07:45:41.54#ibcon#enter sib2, iclass 5, count 0 2006.168.07:45:41.54#ibcon#flushed, iclass 5, count 0 2006.168.07:45:41.54#ibcon#about to write, iclass 5, count 0 2006.168.07:45:41.54#ibcon#wrote, iclass 5, count 0 2006.168.07:45:41.54#ibcon#about to read 3, iclass 5, count 0 2006.168.07:45:41.55#ibcon#read 3, iclass 5, count 0 2006.168.07:45:41.56#ibcon#about to read 4, iclass 5, count 0 2006.168.07:45:41.56#ibcon#read 4, iclass 5, count 0 2006.168.07:45:41.56#ibcon#about to read 5, iclass 5, count 0 2006.168.07:45:41.56#ibcon#read 5, iclass 5, count 0 2006.168.07:45:41.56#ibcon#about to read 6, iclass 5, count 0 2006.168.07:45:41.56#ibcon#read 6, iclass 5, count 0 2006.168.07:45:41.56#ibcon#end of sib2, iclass 5, count 0 2006.168.07:45:41.56#ibcon#*mode == 0, iclass 5, count 0 2006.168.07:45:41.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.168.07:45:41.56#ibcon#[27=USB\r\n] 2006.168.07:45:41.56#ibcon#*before write, iclass 5, count 0 2006.168.07:45:41.56#ibcon#enter sib2, iclass 5, count 0 2006.168.07:45:41.56#ibcon#flushed, iclass 5, count 0 2006.168.07:45:41.56#ibcon#about to write, iclass 5, count 0 2006.168.07:45:41.56#ibcon#wrote, iclass 5, count 0 2006.168.07:45:41.56#ibcon#about to read 3, iclass 5, count 0 2006.168.07:45:41.58#ibcon#read 3, iclass 5, count 0 2006.168.07:45:41.59#ibcon#about to read 4, iclass 5, count 0 2006.168.07:45:41.59#ibcon#read 4, iclass 5, count 0 2006.168.07:45:41.59#ibcon#about to read 5, iclass 5, count 0 2006.168.07:45:41.59#ibcon#read 5, iclass 5, count 0 2006.168.07:45:41.59#ibcon#about to read 6, iclass 5, count 0 2006.168.07:45:41.59#ibcon#read 6, iclass 5, count 0 2006.168.07:45:41.59#ibcon#end of sib2, iclass 5, count 0 2006.168.07:45:41.59#ibcon#*after write, iclass 5, count 0 2006.168.07:45:41.59#ibcon#*before return 0, iclass 5, count 0 2006.168.07:45:41.59#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:45:41.59#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:45:41.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.168.07:45:41.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.168.07:45:41.59$vc4f8/vblo=4,712.99 2006.168.07:45:41.59#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.168.07:45:41.59#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.168.07:45:41.59#ibcon#ireg 17 cls_cnt 0 2006.168.07:45:41.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:45:41.59#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:45:41.59#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:45:41.59#ibcon#enter wrdev, iclass 7, count 0 2006.168.07:45:41.59#ibcon#first serial, iclass 7, count 0 2006.168.07:45:41.59#ibcon#enter sib2, iclass 7, count 0 2006.168.07:45:41.59#ibcon#flushed, iclass 7, count 0 2006.168.07:45:41.59#ibcon#about to write, iclass 7, count 0 2006.168.07:45:41.59#ibcon#wrote, iclass 7, count 0 2006.168.07:45:41.59#ibcon#about to read 3, iclass 7, count 0 2006.168.07:45:41.60#ibcon#read 3, iclass 7, count 0 2006.168.07:45:41.61#ibcon#about to read 4, iclass 7, count 0 2006.168.07:45:41.61#ibcon#read 4, iclass 7, count 0 2006.168.07:45:41.61#ibcon#about to read 5, iclass 7, count 0 2006.168.07:45:41.61#ibcon#read 5, iclass 7, count 0 2006.168.07:45:41.61#ibcon#about to read 6, iclass 7, count 0 2006.168.07:45:41.61#ibcon#read 6, iclass 7, count 0 2006.168.07:45:41.61#ibcon#end of sib2, iclass 7, count 0 2006.168.07:45:41.61#ibcon#*mode == 0, iclass 7, count 0 2006.168.07:45:41.61#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.168.07:45:41.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.07:45:41.61#ibcon#*before write, iclass 7, count 0 2006.168.07:45:41.61#ibcon#enter sib2, iclass 7, count 0 2006.168.07:45:41.61#ibcon#flushed, iclass 7, count 0 2006.168.07:45:41.61#ibcon#about to write, iclass 7, count 0 2006.168.07:45:41.61#ibcon#wrote, iclass 7, count 0 2006.168.07:45:41.61#ibcon#about to read 3, iclass 7, count 0 2006.168.07:45:41.64#ibcon#read 3, iclass 7, count 0 2006.168.07:45:41.65#ibcon#about to read 4, iclass 7, count 0 2006.168.07:45:41.65#ibcon#read 4, iclass 7, count 0 2006.168.07:45:41.65#ibcon#about to read 5, iclass 7, count 0 2006.168.07:45:41.65#ibcon#read 5, iclass 7, count 0 2006.168.07:45:41.65#ibcon#about to read 6, iclass 7, count 0 2006.168.07:45:41.65#ibcon#read 6, iclass 7, count 0 2006.168.07:45:41.65#ibcon#end of sib2, iclass 7, count 0 2006.168.07:45:41.65#ibcon#*after write, iclass 7, count 0 2006.168.07:45:41.65#ibcon#*before return 0, iclass 7, count 0 2006.168.07:45:41.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:45:41.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:45:41.65#ibcon#about to clear, iclass 7 cls_cnt 0 2006.168.07:45:41.65#ibcon#cleared, iclass 7 cls_cnt 0 2006.168.07:45:41.65$vc4f8/vb=4,4 2006.168.07:45:41.65#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.168.07:45:41.65#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.168.07:45:41.65#ibcon#ireg 11 cls_cnt 2 2006.168.07:45:41.65#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:45:41.70#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:45:41.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:45:41.71#ibcon#enter wrdev, iclass 11, count 2 2006.168.07:45:41.71#ibcon#first serial, iclass 11, count 2 2006.168.07:45:41.71#ibcon#enter sib2, iclass 11, count 2 2006.168.07:45:41.71#ibcon#flushed, iclass 11, count 2 2006.168.07:45:41.71#ibcon#about to write, iclass 11, count 2 2006.168.07:45:41.71#ibcon#wrote, iclass 11, count 2 2006.168.07:45:41.71#ibcon#about to read 3, iclass 11, count 2 2006.168.07:45:41.72#ibcon#read 3, iclass 11, count 2 2006.168.07:45:41.73#ibcon#about to read 4, iclass 11, count 2 2006.168.07:45:41.73#ibcon#read 4, iclass 11, count 2 2006.168.07:45:41.73#ibcon#about to read 5, iclass 11, count 2 2006.168.07:45:41.73#ibcon#read 5, iclass 11, count 2 2006.168.07:45:41.73#ibcon#about to read 6, iclass 11, count 2 2006.168.07:45:41.73#ibcon#read 6, iclass 11, count 2 2006.168.07:45:41.73#ibcon#end of sib2, iclass 11, count 2 2006.168.07:45:41.73#ibcon#*mode == 0, iclass 11, count 2 2006.168.07:45:41.73#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.168.07:45:41.73#ibcon#[27=AT04-04\r\n] 2006.168.07:45:41.73#ibcon#*before write, iclass 11, count 2 2006.168.07:45:41.73#ibcon#enter sib2, iclass 11, count 2 2006.168.07:45:41.73#ibcon#flushed, iclass 11, count 2 2006.168.07:45:41.73#ibcon#about to write, iclass 11, count 2 2006.168.07:45:41.73#ibcon#wrote, iclass 11, count 2 2006.168.07:45:41.73#ibcon#about to read 3, iclass 11, count 2 2006.168.07:45:41.75#ibcon#read 3, iclass 11, count 2 2006.168.07:45:41.76#ibcon#about to read 4, iclass 11, count 2 2006.168.07:45:41.76#ibcon#read 4, iclass 11, count 2 2006.168.07:45:41.76#ibcon#about to read 5, iclass 11, count 2 2006.168.07:45:41.76#ibcon#read 5, iclass 11, count 2 2006.168.07:45:41.76#ibcon#about to read 6, iclass 11, count 2 2006.168.07:45:41.76#ibcon#read 6, iclass 11, count 2 2006.168.07:45:41.76#ibcon#end of sib2, iclass 11, count 2 2006.168.07:45:41.76#ibcon#*after write, iclass 11, count 2 2006.168.07:45:41.76#ibcon#*before return 0, iclass 11, count 2 2006.168.07:45:41.76#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:45:41.76#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:45:41.76#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.168.07:45:41.76#ibcon#ireg 7 cls_cnt 0 2006.168.07:45:41.76#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:45:41.87#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:45:41.88#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:45:41.88#ibcon#enter wrdev, iclass 11, count 0 2006.168.07:45:41.88#ibcon#first serial, iclass 11, count 0 2006.168.07:45:41.88#ibcon#enter sib2, iclass 11, count 0 2006.168.07:45:41.88#ibcon#flushed, iclass 11, count 0 2006.168.07:45:41.88#ibcon#about to write, iclass 11, count 0 2006.168.07:45:41.88#ibcon#wrote, iclass 11, count 0 2006.168.07:45:41.88#ibcon#about to read 3, iclass 11, count 0 2006.168.07:45:41.89#ibcon#read 3, iclass 11, count 0 2006.168.07:45:41.90#ibcon#about to read 4, iclass 11, count 0 2006.168.07:45:41.90#ibcon#read 4, iclass 11, count 0 2006.168.07:45:41.90#ibcon#about to read 5, iclass 11, count 0 2006.168.07:45:41.90#ibcon#read 5, iclass 11, count 0 2006.168.07:45:41.90#ibcon#about to read 6, iclass 11, count 0 2006.168.07:45:41.90#ibcon#read 6, iclass 11, count 0 2006.168.07:45:41.90#ibcon#end of sib2, iclass 11, count 0 2006.168.07:45:41.90#ibcon#*mode == 0, iclass 11, count 0 2006.168.07:45:41.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.168.07:45:41.90#ibcon#[27=USB\r\n] 2006.168.07:45:41.90#ibcon#*before write, iclass 11, count 0 2006.168.07:45:41.90#ibcon#enter sib2, iclass 11, count 0 2006.168.07:45:41.90#ibcon#flushed, iclass 11, count 0 2006.168.07:45:41.90#ibcon#about to write, iclass 11, count 0 2006.168.07:45:41.90#ibcon#wrote, iclass 11, count 0 2006.168.07:45:41.90#ibcon#about to read 3, iclass 11, count 0 2006.168.07:45:41.92#ibcon#read 3, iclass 11, count 0 2006.168.07:45:41.93#ibcon#about to read 4, iclass 11, count 0 2006.168.07:45:41.93#ibcon#read 4, iclass 11, count 0 2006.168.07:45:41.93#ibcon#about to read 5, iclass 11, count 0 2006.168.07:45:41.93#ibcon#read 5, iclass 11, count 0 2006.168.07:45:41.93#ibcon#about to read 6, iclass 11, count 0 2006.168.07:45:41.93#ibcon#read 6, iclass 11, count 0 2006.168.07:45:41.93#ibcon#end of sib2, iclass 11, count 0 2006.168.07:45:41.93#ibcon#*after write, iclass 11, count 0 2006.168.07:45:41.93#ibcon#*before return 0, iclass 11, count 0 2006.168.07:45:41.93#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:45:41.93#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:45:41.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.168.07:45:41.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.168.07:45:41.93$vc4f8/vblo=5,744.99 2006.168.07:45:41.93#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.168.07:45:41.93#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.168.07:45:41.93#ibcon#ireg 17 cls_cnt 0 2006.168.07:45:41.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:45:41.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:45:41.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:45:41.93#ibcon#enter wrdev, iclass 13, count 0 2006.168.07:45:41.93#ibcon#first serial, iclass 13, count 0 2006.168.07:45:41.93#ibcon#enter sib2, iclass 13, count 0 2006.168.07:45:41.93#ibcon#flushed, iclass 13, count 0 2006.168.07:45:41.93#ibcon#about to write, iclass 13, count 0 2006.168.07:45:41.93#ibcon#wrote, iclass 13, count 0 2006.168.07:45:41.93#ibcon#about to read 3, iclass 13, count 0 2006.168.07:45:41.94#ibcon#read 3, iclass 13, count 0 2006.168.07:45:41.95#ibcon#about to read 4, iclass 13, count 0 2006.168.07:45:41.95#ibcon#read 4, iclass 13, count 0 2006.168.07:45:41.95#ibcon#about to read 5, iclass 13, count 0 2006.168.07:45:41.95#ibcon#read 5, iclass 13, count 0 2006.168.07:45:41.95#ibcon#about to read 6, iclass 13, count 0 2006.168.07:45:41.95#ibcon#read 6, iclass 13, count 0 2006.168.07:45:41.95#ibcon#end of sib2, iclass 13, count 0 2006.168.07:45:41.95#ibcon#*mode == 0, iclass 13, count 0 2006.168.07:45:41.95#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.168.07:45:41.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.07:45:41.95#ibcon#*before write, iclass 13, count 0 2006.168.07:45:41.95#ibcon#enter sib2, iclass 13, count 0 2006.168.07:45:41.95#ibcon#flushed, iclass 13, count 0 2006.168.07:45:41.95#ibcon#about to write, iclass 13, count 0 2006.168.07:45:41.95#ibcon#wrote, iclass 13, count 0 2006.168.07:45:41.95#ibcon#about to read 3, iclass 13, count 0 2006.168.07:45:41.99#ibcon#read 3, iclass 13, count 0 2006.168.07:45:41.99#ibcon#about to read 4, iclass 13, count 0 2006.168.07:45:41.99#ibcon#read 4, iclass 13, count 0 2006.168.07:45:41.99#ibcon#about to read 5, iclass 13, count 0 2006.168.07:45:41.99#ibcon#read 5, iclass 13, count 0 2006.168.07:45:41.99#ibcon#about to read 6, iclass 13, count 0 2006.168.07:45:41.99#ibcon#read 6, iclass 13, count 0 2006.168.07:45:41.99#ibcon#end of sib2, iclass 13, count 0 2006.168.07:45:41.99#ibcon#*after write, iclass 13, count 0 2006.168.07:45:41.99#ibcon#*before return 0, iclass 13, count 0 2006.168.07:45:41.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:45:41.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:45:41.99#ibcon#about to clear, iclass 13 cls_cnt 0 2006.168.07:45:41.99#ibcon#cleared, iclass 13 cls_cnt 0 2006.168.07:45:41.99$vc4f8/vb=5,4 2006.168.07:45:41.99#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.168.07:45:41.99#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.168.07:45:41.99#ibcon#ireg 11 cls_cnt 2 2006.168.07:45:41.99#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.168.07:45:42.04#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.168.07:45:42.04#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.168.07:45:42.05#ibcon#enter wrdev, iclass 15, count 2 2006.168.07:45:42.05#ibcon#first serial, iclass 15, count 2 2006.168.07:45:42.05#ibcon#enter sib2, iclass 15, count 2 2006.168.07:45:42.05#ibcon#flushed, iclass 15, count 2 2006.168.07:45:42.05#ibcon#about to write, iclass 15, count 2 2006.168.07:45:42.05#ibcon#wrote, iclass 15, count 2 2006.168.07:45:42.05#ibcon#about to read 3, iclass 15, count 2 2006.168.07:45:42.06#ibcon#read 3, iclass 15, count 2 2006.168.07:45:42.07#ibcon#about to read 4, iclass 15, count 2 2006.168.07:45:42.07#ibcon#read 4, iclass 15, count 2 2006.168.07:45:42.07#ibcon#about to read 5, iclass 15, count 2 2006.168.07:45:42.07#ibcon#read 5, iclass 15, count 2 2006.168.07:45:42.07#ibcon#about to read 6, iclass 15, count 2 2006.168.07:45:42.07#ibcon#read 6, iclass 15, count 2 2006.168.07:45:42.07#ibcon#end of sib2, iclass 15, count 2 2006.168.07:45:42.07#ibcon#*mode == 0, iclass 15, count 2 2006.168.07:45:42.07#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.168.07:45:42.07#ibcon#[27=AT05-04\r\n] 2006.168.07:45:42.07#ibcon#*before write, iclass 15, count 2 2006.168.07:45:42.07#ibcon#enter sib2, iclass 15, count 2 2006.168.07:45:42.07#ibcon#flushed, iclass 15, count 2 2006.168.07:45:42.07#ibcon#about to write, iclass 15, count 2 2006.168.07:45:42.07#ibcon#wrote, iclass 15, count 2 2006.168.07:45:42.07#ibcon#about to read 3, iclass 15, count 2 2006.168.07:45:42.09#ibcon#read 3, iclass 15, count 2 2006.168.07:45:42.10#ibcon#about to read 4, iclass 15, count 2 2006.168.07:45:42.10#ibcon#read 4, iclass 15, count 2 2006.168.07:45:42.10#ibcon#about to read 5, iclass 15, count 2 2006.168.07:45:42.10#ibcon#read 5, iclass 15, count 2 2006.168.07:45:42.10#ibcon#about to read 6, iclass 15, count 2 2006.168.07:45:42.10#ibcon#read 6, iclass 15, count 2 2006.168.07:45:42.10#ibcon#end of sib2, iclass 15, count 2 2006.168.07:45:42.10#ibcon#*after write, iclass 15, count 2 2006.168.07:45:42.10#ibcon#*before return 0, iclass 15, count 2 2006.168.07:45:42.10#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.168.07:45:42.10#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.168.07:45:42.10#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.168.07:45:42.10#ibcon#ireg 7 cls_cnt 0 2006.168.07:45:42.10#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.168.07:45:42.21#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.168.07:45:42.22#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.168.07:45:42.22#ibcon#enter wrdev, iclass 15, count 0 2006.168.07:45:42.22#ibcon#first serial, iclass 15, count 0 2006.168.07:45:42.22#ibcon#enter sib2, iclass 15, count 0 2006.168.07:45:42.22#ibcon#flushed, iclass 15, count 0 2006.168.07:45:42.22#ibcon#about to write, iclass 15, count 0 2006.168.07:45:42.22#ibcon#wrote, iclass 15, count 0 2006.168.07:45:42.22#ibcon#about to read 3, iclass 15, count 0 2006.168.07:45:42.24#ibcon#read 3, iclass 15, count 0 2006.168.07:45:42.24#ibcon#about to read 4, iclass 15, count 0 2006.168.07:45:42.24#ibcon#read 4, iclass 15, count 0 2006.168.07:45:42.24#ibcon#about to read 5, iclass 15, count 0 2006.168.07:45:42.24#ibcon#read 5, iclass 15, count 0 2006.168.07:45:42.24#ibcon#about to read 6, iclass 15, count 0 2006.168.07:45:42.24#ibcon#read 6, iclass 15, count 0 2006.168.07:45:42.24#ibcon#end of sib2, iclass 15, count 0 2006.168.07:45:42.24#ibcon#*mode == 0, iclass 15, count 0 2006.168.07:45:42.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.168.07:45:42.24#ibcon#[27=USB\r\n] 2006.168.07:45:42.24#ibcon#*before write, iclass 15, count 0 2006.168.07:45:42.24#ibcon#enter sib2, iclass 15, count 0 2006.168.07:45:42.24#ibcon#flushed, iclass 15, count 0 2006.168.07:45:42.24#ibcon#about to write, iclass 15, count 0 2006.168.07:45:42.24#ibcon#wrote, iclass 15, count 0 2006.168.07:45:42.24#ibcon#about to read 3, iclass 15, count 0 2006.168.07:45:42.26#ibcon#read 3, iclass 15, count 0 2006.168.07:45:42.27#ibcon#about to read 4, iclass 15, count 0 2006.168.07:45:42.27#ibcon#read 4, iclass 15, count 0 2006.168.07:45:42.27#ibcon#about to read 5, iclass 15, count 0 2006.168.07:45:42.27#ibcon#read 5, iclass 15, count 0 2006.168.07:45:42.27#ibcon#about to read 6, iclass 15, count 0 2006.168.07:45:42.27#ibcon#read 6, iclass 15, count 0 2006.168.07:45:42.27#ibcon#end of sib2, iclass 15, count 0 2006.168.07:45:42.27#ibcon#*after write, iclass 15, count 0 2006.168.07:45:42.27#ibcon#*before return 0, iclass 15, count 0 2006.168.07:45:42.27#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.168.07:45:42.27#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.168.07:45:42.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.168.07:45:42.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.168.07:45:42.27$vc4f8/vblo=6,752.99 2006.168.07:45:42.27#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.168.07:45:42.27#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.168.07:45:42.27#ibcon#ireg 17 cls_cnt 0 2006.168.07:45:42.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:45:42.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:45:42.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:45:42.27#ibcon#enter wrdev, iclass 17, count 0 2006.168.07:45:42.27#ibcon#first serial, iclass 17, count 0 2006.168.07:45:42.27#ibcon#enter sib2, iclass 17, count 0 2006.168.07:45:42.27#ibcon#flushed, iclass 17, count 0 2006.168.07:45:42.27#ibcon#about to write, iclass 17, count 0 2006.168.07:45:42.27#ibcon#wrote, iclass 17, count 0 2006.168.07:45:42.27#ibcon#about to read 3, iclass 17, count 0 2006.168.07:45:42.28#ibcon#read 3, iclass 17, count 0 2006.168.07:45:42.29#ibcon#about to read 4, iclass 17, count 0 2006.168.07:45:42.29#ibcon#read 4, iclass 17, count 0 2006.168.07:45:42.29#ibcon#about to read 5, iclass 17, count 0 2006.168.07:45:42.29#ibcon#read 5, iclass 17, count 0 2006.168.07:45:42.29#ibcon#about to read 6, iclass 17, count 0 2006.168.07:45:42.29#ibcon#read 6, iclass 17, count 0 2006.168.07:45:42.29#ibcon#end of sib2, iclass 17, count 0 2006.168.07:45:42.29#ibcon#*mode == 0, iclass 17, count 0 2006.168.07:45:42.29#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.168.07:45:42.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.07:45:42.29#ibcon#*before write, iclass 17, count 0 2006.168.07:45:42.29#ibcon#enter sib2, iclass 17, count 0 2006.168.07:45:42.29#ibcon#flushed, iclass 17, count 0 2006.168.07:45:42.29#ibcon#about to write, iclass 17, count 0 2006.168.07:45:42.29#ibcon#wrote, iclass 17, count 0 2006.168.07:45:42.29#ibcon#about to read 3, iclass 17, count 0 2006.168.07:45:42.32#ibcon#read 3, iclass 17, count 0 2006.168.07:45:42.33#ibcon#about to read 4, iclass 17, count 0 2006.168.07:45:42.33#ibcon#read 4, iclass 17, count 0 2006.168.07:45:42.33#ibcon#about to read 5, iclass 17, count 0 2006.168.07:45:42.33#ibcon#read 5, iclass 17, count 0 2006.168.07:45:42.33#ibcon#about to read 6, iclass 17, count 0 2006.168.07:45:42.33#ibcon#read 6, iclass 17, count 0 2006.168.07:45:42.33#ibcon#end of sib2, iclass 17, count 0 2006.168.07:45:42.33#ibcon#*after write, iclass 17, count 0 2006.168.07:45:42.33#ibcon#*before return 0, iclass 17, count 0 2006.168.07:45:42.33#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:45:42.33#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:45:42.33#ibcon#about to clear, iclass 17 cls_cnt 0 2006.168.07:45:42.33#ibcon#cleared, iclass 17 cls_cnt 0 2006.168.07:45:42.33$vc4f8/vb=6,4 2006.168.07:45:42.33#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.168.07:45:42.33#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.168.07:45:42.33#ibcon#ireg 11 cls_cnt 2 2006.168.07:45:42.33#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.168.07:45:42.38#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.168.07:45:42.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.168.07:45:42.39#ibcon#enter wrdev, iclass 19, count 2 2006.168.07:45:42.39#ibcon#first serial, iclass 19, count 2 2006.168.07:45:42.39#ibcon#enter sib2, iclass 19, count 2 2006.168.07:45:42.39#ibcon#flushed, iclass 19, count 2 2006.168.07:45:42.39#ibcon#about to write, iclass 19, count 2 2006.168.07:45:42.39#ibcon#wrote, iclass 19, count 2 2006.168.07:45:42.39#ibcon#about to read 3, iclass 19, count 2 2006.168.07:45:42.41#ibcon#read 3, iclass 19, count 2 2006.168.07:45:42.41#ibcon#about to read 4, iclass 19, count 2 2006.168.07:45:42.41#ibcon#read 4, iclass 19, count 2 2006.168.07:45:42.41#ibcon#about to read 5, iclass 19, count 2 2006.168.07:45:42.41#ibcon#read 5, iclass 19, count 2 2006.168.07:45:42.41#ibcon#about to read 6, iclass 19, count 2 2006.168.07:45:42.41#ibcon#read 6, iclass 19, count 2 2006.168.07:45:42.41#ibcon#end of sib2, iclass 19, count 2 2006.168.07:45:42.41#ibcon#*mode == 0, iclass 19, count 2 2006.168.07:45:42.41#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.168.07:45:42.41#ibcon#[27=AT06-04\r\n] 2006.168.07:45:42.41#ibcon#*before write, iclass 19, count 2 2006.168.07:45:42.41#ibcon#enter sib2, iclass 19, count 2 2006.168.07:45:42.41#ibcon#flushed, iclass 19, count 2 2006.168.07:45:42.41#ibcon#about to write, iclass 19, count 2 2006.168.07:45:42.41#ibcon#wrote, iclass 19, count 2 2006.168.07:45:42.41#ibcon#about to read 3, iclass 19, count 2 2006.168.07:45:42.43#ibcon#read 3, iclass 19, count 2 2006.168.07:45:42.44#ibcon#about to read 4, iclass 19, count 2 2006.168.07:45:42.44#ibcon#read 4, iclass 19, count 2 2006.168.07:45:42.44#ibcon#about to read 5, iclass 19, count 2 2006.168.07:45:42.44#ibcon#read 5, iclass 19, count 2 2006.168.07:45:42.44#ibcon#about to read 6, iclass 19, count 2 2006.168.07:45:42.44#ibcon#read 6, iclass 19, count 2 2006.168.07:45:42.44#ibcon#end of sib2, iclass 19, count 2 2006.168.07:45:42.44#ibcon#*after write, iclass 19, count 2 2006.168.07:45:42.44#ibcon#*before return 0, iclass 19, count 2 2006.168.07:45:42.44#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.168.07:45:42.44#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.168.07:45:42.44#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.168.07:45:42.44#ibcon#ireg 7 cls_cnt 0 2006.168.07:45:42.44#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.168.07:45:42.55#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.168.07:45:42.55#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.168.07:45:42.56#ibcon#enter wrdev, iclass 19, count 0 2006.168.07:45:42.56#ibcon#first serial, iclass 19, count 0 2006.168.07:45:42.56#ibcon#enter sib2, iclass 19, count 0 2006.168.07:45:42.56#ibcon#flushed, iclass 19, count 0 2006.168.07:45:42.56#ibcon#about to write, iclass 19, count 0 2006.168.07:45:42.56#ibcon#wrote, iclass 19, count 0 2006.168.07:45:42.56#ibcon#about to read 3, iclass 19, count 0 2006.168.07:45:42.57#ibcon#read 3, iclass 19, count 0 2006.168.07:45:42.58#ibcon#about to read 4, iclass 19, count 0 2006.168.07:45:42.58#ibcon#read 4, iclass 19, count 0 2006.168.07:45:42.58#ibcon#about to read 5, iclass 19, count 0 2006.168.07:45:42.58#ibcon#read 5, iclass 19, count 0 2006.168.07:45:42.58#ibcon#about to read 6, iclass 19, count 0 2006.168.07:45:42.58#ibcon#read 6, iclass 19, count 0 2006.168.07:45:42.58#ibcon#end of sib2, iclass 19, count 0 2006.168.07:45:42.58#ibcon#*mode == 0, iclass 19, count 0 2006.168.07:45:42.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.168.07:45:42.58#ibcon#[27=USB\r\n] 2006.168.07:45:42.58#ibcon#*before write, iclass 19, count 0 2006.168.07:45:42.58#ibcon#enter sib2, iclass 19, count 0 2006.168.07:45:42.58#ibcon#flushed, iclass 19, count 0 2006.168.07:45:42.58#ibcon#about to write, iclass 19, count 0 2006.168.07:45:42.58#ibcon#wrote, iclass 19, count 0 2006.168.07:45:42.58#ibcon#about to read 3, iclass 19, count 0 2006.168.07:45:42.60#ibcon#read 3, iclass 19, count 0 2006.168.07:45:42.61#ibcon#about to read 4, iclass 19, count 0 2006.168.07:45:42.61#ibcon#read 4, iclass 19, count 0 2006.168.07:45:42.61#ibcon#about to read 5, iclass 19, count 0 2006.168.07:45:42.61#ibcon#read 5, iclass 19, count 0 2006.168.07:45:42.61#ibcon#about to read 6, iclass 19, count 0 2006.168.07:45:42.61#ibcon#read 6, iclass 19, count 0 2006.168.07:45:42.61#ibcon#end of sib2, iclass 19, count 0 2006.168.07:45:42.61#ibcon#*after write, iclass 19, count 0 2006.168.07:45:42.61#ibcon#*before return 0, iclass 19, count 0 2006.168.07:45:42.61#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.168.07:45:42.61#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.168.07:45:42.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.168.07:45:42.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.168.07:45:42.61$vc4f8/vabw=wide 2006.168.07:45:42.61#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.168.07:45:42.61#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.168.07:45:42.61#ibcon#ireg 8 cls_cnt 0 2006.168.07:45:42.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.168.07:45:42.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.168.07:45:42.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.168.07:45:42.61#ibcon#enter wrdev, iclass 21, count 0 2006.168.07:45:42.61#ibcon#first serial, iclass 21, count 0 2006.168.07:45:42.61#ibcon#enter sib2, iclass 21, count 0 2006.168.07:45:42.61#ibcon#flushed, iclass 21, count 0 2006.168.07:45:42.61#ibcon#about to write, iclass 21, count 0 2006.168.07:45:42.61#ibcon#wrote, iclass 21, count 0 2006.168.07:45:42.61#ibcon#about to read 3, iclass 21, count 0 2006.168.07:45:42.62#ibcon#read 3, iclass 21, count 0 2006.168.07:45:42.63#ibcon#about to read 4, iclass 21, count 0 2006.168.07:45:42.63#ibcon#read 4, iclass 21, count 0 2006.168.07:45:42.63#ibcon#about to read 5, iclass 21, count 0 2006.168.07:45:42.63#ibcon#read 5, iclass 21, count 0 2006.168.07:45:42.63#ibcon#about to read 6, iclass 21, count 0 2006.168.07:45:42.63#ibcon#read 6, iclass 21, count 0 2006.168.07:45:42.63#ibcon#end of sib2, iclass 21, count 0 2006.168.07:45:42.63#ibcon#*mode == 0, iclass 21, count 0 2006.168.07:45:42.63#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.168.07:45:42.63#ibcon#[25=BW32\r\n] 2006.168.07:45:42.63#ibcon#*before write, iclass 21, count 0 2006.168.07:45:42.63#ibcon#enter sib2, iclass 21, count 0 2006.168.07:45:42.63#ibcon#flushed, iclass 21, count 0 2006.168.07:45:42.63#ibcon#about to write, iclass 21, count 0 2006.168.07:45:42.63#ibcon#wrote, iclass 21, count 0 2006.168.07:45:42.63#ibcon#about to read 3, iclass 21, count 0 2006.168.07:45:42.65#ibcon#read 3, iclass 21, count 0 2006.168.07:45:42.66#ibcon#about to read 4, iclass 21, count 0 2006.168.07:45:42.66#ibcon#read 4, iclass 21, count 0 2006.168.07:45:42.66#ibcon#about to read 5, iclass 21, count 0 2006.168.07:45:42.66#ibcon#read 5, iclass 21, count 0 2006.168.07:45:42.66#ibcon#about to read 6, iclass 21, count 0 2006.168.07:45:42.66#ibcon#read 6, iclass 21, count 0 2006.168.07:45:42.66#ibcon#end of sib2, iclass 21, count 0 2006.168.07:45:42.66#ibcon#*after write, iclass 21, count 0 2006.168.07:45:42.66#ibcon#*before return 0, iclass 21, count 0 2006.168.07:45:42.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.168.07:45:42.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.168.07:45:42.66#ibcon#about to clear, iclass 21 cls_cnt 0 2006.168.07:45:42.66#ibcon#cleared, iclass 21 cls_cnt 0 2006.168.07:45:42.66$vc4f8/vbbw=wide 2006.168.07:45:42.66#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.168.07:45:42.66#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.168.07:45:42.66#ibcon#ireg 8 cls_cnt 0 2006.168.07:45:42.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:45:42.72#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:45:42.73#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:45:42.73#ibcon#enter wrdev, iclass 23, count 0 2006.168.07:45:42.73#ibcon#first serial, iclass 23, count 0 2006.168.07:45:42.73#ibcon#enter sib2, iclass 23, count 0 2006.168.07:45:42.73#ibcon#flushed, iclass 23, count 0 2006.168.07:45:42.73#ibcon#about to write, iclass 23, count 0 2006.168.07:45:42.73#ibcon#wrote, iclass 23, count 0 2006.168.07:45:42.73#ibcon#about to read 3, iclass 23, count 0 2006.168.07:45:42.75#ibcon#read 3, iclass 23, count 0 2006.168.07:45:42.75#ibcon#about to read 4, iclass 23, count 0 2006.168.07:45:42.75#ibcon#read 4, iclass 23, count 0 2006.168.07:45:42.75#ibcon#about to read 5, iclass 23, count 0 2006.168.07:45:42.75#ibcon#read 5, iclass 23, count 0 2006.168.07:45:42.75#ibcon#about to read 6, iclass 23, count 0 2006.168.07:45:42.75#ibcon#read 6, iclass 23, count 0 2006.168.07:45:42.75#ibcon#end of sib2, iclass 23, count 0 2006.168.07:45:42.75#ibcon#*mode == 0, iclass 23, count 0 2006.168.07:45:42.75#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.168.07:45:42.75#ibcon#[27=BW32\r\n] 2006.168.07:45:42.75#ibcon#*before write, iclass 23, count 0 2006.168.07:45:42.75#ibcon#enter sib2, iclass 23, count 0 2006.168.07:45:42.75#ibcon#flushed, iclass 23, count 0 2006.168.07:45:42.75#ibcon#about to write, iclass 23, count 0 2006.168.07:45:42.75#ibcon#wrote, iclass 23, count 0 2006.168.07:45:42.75#ibcon#about to read 3, iclass 23, count 0 2006.168.07:45:42.77#ibcon#read 3, iclass 23, count 0 2006.168.07:45:42.78#ibcon#about to read 4, iclass 23, count 0 2006.168.07:45:42.78#ibcon#read 4, iclass 23, count 0 2006.168.07:45:42.78#ibcon#about to read 5, iclass 23, count 0 2006.168.07:45:42.78#ibcon#read 5, iclass 23, count 0 2006.168.07:45:42.78#ibcon#about to read 6, iclass 23, count 0 2006.168.07:45:42.78#ibcon#read 6, iclass 23, count 0 2006.168.07:45:42.78#ibcon#end of sib2, iclass 23, count 0 2006.168.07:45:42.78#ibcon#*after write, iclass 23, count 0 2006.168.07:45:42.78#ibcon#*before return 0, iclass 23, count 0 2006.168.07:45:42.78#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:45:42.78#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:45:42.78#ibcon#about to clear, iclass 23 cls_cnt 0 2006.168.07:45:42.78#ibcon#cleared, iclass 23 cls_cnt 0 2006.168.07:45:42.78$4f8m12a/ifd4f 2006.168.07:45:42.78$ifd4f/lo= 2006.168.07:45:42.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.07:45:42.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.07:45:42.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.07:45:42.78$ifd4f/patch= 2006.168.07:45:42.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.07:45:42.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.07:45:42.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.07:45:42.78$4f8m12a/"form=m,16.000,1:2 2006.168.07:45:42.78$4f8m12a/"tpicd 2006.168.07:45:42.78$4f8m12a/echo=off 2006.168.07:45:42.78$4f8m12a/xlog=off 2006.168.07:45:42.78:!2006.168.07:46:50 2006.168.07:46:27.13#trakl#Source acquired 2006.168.07:46:28.15#flagr#flagr/antenna,acquired 2006.168.07:46:50.02:preob 2006.168.07:46:51.15/onsource/TRACKING 2006.168.07:46:51.15:!2006.168.07:47:00 2006.168.07:47:00.02:data_valid=on 2006.168.07:47:00.02:midob 2006.168.07:47:01.15/onsource/TRACKING 2006.168.07:47:01.15/wx/27.50,1004.6,72 2006.168.07:47:01.28/cable/+6.4716E-03 2006.168.07:47:02.37/va/01,08,usb,yes,29,31 2006.168.07:47:02.37/va/02,07,usb,yes,29,31 2006.168.07:47:02.37/va/03,06,usb,yes,31,31 2006.168.07:47:02.37/va/04,07,usb,yes,30,32 2006.168.07:47:02.37/va/05,07,usb,yes,29,31 2006.168.07:47:02.37/va/06,06,usb,yes,29,28 2006.168.07:47:02.37/va/07,06,usb,yes,29,29 2006.168.07:47:02.37/va/08,07,usb,yes,28,27 2006.168.07:47:02.60/valo/01,532.99,yes,locked 2006.168.07:47:02.60/valo/02,572.99,yes,locked 2006.168.07:47:02.60/valo/03,672.99,yes,locked 2006.168.07:47:02.60/valo/04,832.99,yes,locked 2006.168.07:47:02.60/valo/05,652.99,yes,locked 2006.168.07:47:02.60/valo/06,772.99,yes,locked 2006.168.07:47:02.60/valo/07,832.99,yes,locked 2006.168.07:47:02.60/valo/08,852.99,yes,locked 2006.168.07:47:03.69/vb/01,04,usb,yes,29,28 2006.168.07:47:03.69/vb/02,04,usb,yes,31,32 2006.168.07:47:03.69/vb/03,04,usb,yes,27,31 2006.168.07:47:03.69/vb/04,04,usb,yes,28,28 2006.168.07:47:03.69/vb/05,04,usb,yes,27,30 2006.168.07:47:03.69/vb/06,04,usb,yes,28,30 2006.168.07:47:03.69/vb/07,04,usb,yes,30,29 2006.168.07:47:03.69/vb/08,04,usb,yes,27,30 2006.168.07:47:03.93/vblo/01,632.99,yes,locked 2006.168.07:47:03.93/vblo/02,640.99,yes,locked 2006.168.07:47:03.93/vblo/03,656.99,yes,locked 2006.168.07:47:03.93/vblo/04,712.99,yes,locked 2006.168.07:47:03.93/vblo/05,744.99,yes,locked 2006.168.07:47:03.93/vblo/06,752.99,yes,locked 2006.168.07:47:03.93/vblo/07,734.99,yes,locked 2006.168.07:47:03.93/vblo/08,744.99,yes,locked 2006.168.07:47:04.08/vabw/8 2006.168.07:47:04.23/vbbw/8 2006.168.07:47:04.32/xfe/off,on,14.7 2006.168.07:47:04.71/ifatt/23,28,28,28 2006.168.07:47:05.07/fmout-gps/S +4.19E-07 2006.168.07:47:05.15:!2006.168.07:49:10 2006.168.07:49:10.01:data_valid=off 2006.168.07:49:10.02:postob 2006.168.07:49:10.08/cable/+6.4721E-03 2006.168.07:49:10.09/wx/27.43,1004.6,72 2006.168.07:49:11.07/fmout-gps/S +4.19E-07 2006.168.07:49:11.08:scan_name=168-0750,k06168,60 2006.168.07:49:11.08:source=1300+580,130252.47,574837.6,2000.0,cw 2006.168.07:49:11.14#flagr#flagr/antenna,new-source 2006.168.07:49:12.15:checkk5 2006.168.07:49:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.168.07:49:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.168.07:49:13.28/chk_autoobs//k5ts3/ autoobs is running! 2006.168.07:49:13.65/chk_autoobs//k5ts4/ autoobs is running! 2006.168.07:49:14.02/chk_obsdata//k5ts1/T1680747??a.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.168.07:49:14.39/chk_obsdata//k5ts2/T1680747??b.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.168.07:49:14.76/chk_obsdata//k5ts3/T1680747??c.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.168.07:49:15.13/chk_obsdata//k5ts4/T1680747??d.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.168.07:49:15.82/k5log//k5ts1_log_newline 2006.168.07:49:16.51/k5log//k5ts2_log_newline 2006.168.07:49:17.20/k5log//k5ts3_log_newline 2006.168.07:49:17.88/k5log//k5ts4_log_newline 2006.168.07:49:17.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.07:49:17.91:4f8m12a=1 2006.168.07:49:17.91$4f8m12a/echo=on 2006.168.07:49:17.91$4f8m12a/pcalon 2006.168.07:49:17.91$pcalon/"no phase cal control is implemented here 2006.168.07:49:17.91$4f8m12a/"tpicd=stop 2006.168.07:49:17.91$4f8m12a/vc4f8 2006.168.07:49:17.91$vc4f8/valo=1,532.99 2006.168.07:49:17.91#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.168.07:49:17.91#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.168.07:49:17.91#ibcon#ireg 17 cls_cnt 0 2006.168.07:49:17.91#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:49:17.91#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:49:17.91#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:49:17.91#ibcon#enter wrdev, iclass 4, count 0 2006.168.07:49:17.91#ibcon#first serial, iclass 4, count 0 2006.168.07:49:17.91#ibcon#enter sib2, iclass 4, count 0 2006.168.07:49:17.91#ibcon#flushed, iclass 4, count 0 2006.168.07:49:17.91#ibcon#about to write, iclass 4, count 0 2006.168.07:49:17.91#ibcon#wrote, iclass 4, count 0 2006.168.07:49:17.91#ibcon#about to read 3, iclass 4, count 0 2006.168.07:49:17.92#ibcon#read 3, iclass 4, count 0 2006.168.07:49:17.92#ibcon#about to read 4, iclass 4, count 0 2006.168.07:49:17.92#ibcon#read 4, iclass 4, count 0 2006.168.07:49:17.92#ibcon#about to read 5, iclass 4, count 0 2006.168.07:49:17.92#ibcon#read 5, iclass 4, count 0 2006.168.07:49:17.92#ibcon#about to read 6, iclass 4, count 0 2006.168.07:49:17.92#ibcon#read 6, iclass 4, count 0 2006.168.07:49:17.92#ibcon#end of sib2, iclass 4, count 0 2006.168.07:49:17.92#ibcon#*mode == 0, iclass 4, count 0 2006.168.07:49:17.92#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.168.07:49:17.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.07:49:17.92#ibcon#*before write, iclass 4, count 0 2006.168.07:49:17.92#ibcon#enter sib2, iclass 4, count 0 2006.168.07:49:17.92#ibcon#flushed, iclass 4, count 0 2006.168.07:49:17.92#ibcon#about to write, iclass 4, count 0 2006.168.07:49:17.92#ibcon#wrote, iclass 4, count 0 2006.168.07:49:17.92#ibcon#about to read 3, iclass 4, count 0 2006.168.07:49:17.97#ibcon#read 3, iclass 4, count 0 2006.168.07:49:17.97#ibcon#about to read 4, iclass 4, count 0 2006.168.07:49:17.97#ibcon#read 4, iclass 4, count 0 2006.168.07:49:17.97#ibcon#about to read 5, iclass 4, count 0 2006.168.07:49:17.97#ibcon#read 5, iclass 4, count 0 2006.168.07:49:17.97#ibcon#about to read 6, iclass 4, count 0 2006.168.07:49:17.97#ibcon#read 6, iclass 4, count 0 2006.168.07:49:17.97#ibcon#end of sib2, iclass 4, count 0 2006.168.07:49:17.97#ibcon#*after write, iclass 4, count 0 2006.168.07:49:17.97#ibcon#*before return 0, iclass 4, count 0 2006.168.07:49:17.97#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:49:17.97#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:49:17.97#ibcon#about to clear, iclass 4 cls_cnt 0 2006.168.07:49:17.97#ibcon#cleared, iclass 4 cls_cnt 0 2006.168.07:49:17.97$vc4f8/va=1,8 2006.168.07:49:17.97#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.168.07:49:17.97#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.168.07:49:17.97#ibcon#ireg 11 cls_cnt 2 2006.168.07:49:17.97#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:49:17.97#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:49:17.97#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:49:17.97#ibcon#enter wrdev, iclass 6, count 2 2006.168.07:49:17.97#ibcon#first serial, iclass 6, count 2 2006.168.07:49:17.97#ibcon#enter sib2, iclass 6, count 2 2006.168.07:49:17.97#ibcon#flushed, iclass 6, count 2 2006.168.07:49:17.97#ibcon#about to write, iclass 6, count 2 2006.168.07:49:17.97#ibcon#wrote, iclass 6, count 2 2006.168.07:49:17.97#ibcon#about to read 3, iclass 6, count 2 2006.168.07:49:17.99#ibcon#read 3, iclass 6, count 2 2006.168.07:49:17.99#ibcon#about to read 4, iclass 6, count 2 2006.168.07:49:17.99#ibcon#read 4, iclass 6, count 2 2006.168.07:49:17.99#ibcon#about to read 5, iclass 6, count 2 2006.168.07:49:17.99#ibcon#read 5, iclass 6, count 2 2006.168.07:49:17.99#ibcon#about to read 6, iclass 6, count 2 2006.168.07:49:17.99#ibcon#read 6, iclass 6, count 2 2006.168.07:49:17.99#ibcon#end of sib2, iclass 6, count 2 2006.168.07:49:17.99#ibcon#*mode == 0, iclass 6, count 2 2006.168.07:49:17.99#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.168.07:49:17.99#ibcon#[25=AT01-08\r\n] 2006.168.07:49:17.99#ibcon#*before write, iclass 6, count 2 2006.168.07:49:17.99#ibcon#enter sib2, iclass 6, count 2 2006.168.07:49:17.99#ibcon#flushed, iclass 6, count 2 2006.168.07:49:17.99#ibcon#about to write, iclass 6, count 2 2006.168.07:49:17.99#ibcon#wrote, iclass 6, count 2 2006.168.07:49:17.99#ibcon#about to read 3, iclass 6, count 2 2006.168.07:49:18.02#ibcon#read 3, iclass 6, count 2 2006.168.07:49:18.02#ibcon#about to read 4, iclass 6, count 2 2006.168.07:49:18.02#ibcon#read 4, iclass 6, count 2 2006.168.07:49:18.02#ibcon#about to read 5, iclass 6, count 2 2006.168.07:49:18.02#ibcon#read 5, iclass 6, count 2 2006.168.07:49:18.02#ibcon#about to read 6, iclass 6, count 2 2006.168.07:49:18.02#ibcon#read 6, iclass 6, count 2 2006.168.07:49:18.02#ibcon#end of sib2, iclass 6, count 2 2006.168.07:49:18.02#ibcon#*after write, iclass 6, count 2 2006.168.07:49:18.02#ibcon#*before return 0, iclass 6, count 2 2006.168.07:49:18.02#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:49:18.02#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:49:18.02#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.168.07:49:18.02#ibcon#ireg 7 cls_cnt 0 2006.168.07:49:18.02#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:49:18.15#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:49:18.15#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:49:18.15#ibcon#enter wrdev, iclass 6, count 0 2006.168.07:49:18.15#ibcon#first serial, iclass 6, count 0 2006.168.07:49:18.15#ibcon#enter sib2, iclass 6, count 0 2006.168.07:49:18.15#ibcon#flushed, iclass 6, count 0 2006.168.07:49:18.15#ibcon#about to write, iclass 6, count 0 2006.168.07:49:18.15#ibcon#wrote, iclass 6, count 0 2006.168.07:49:18.15#ibcon#about to read 3, iclass 6, count 0 2006.168.07:49:18.16#ibcon#read 3, iclass 6, count 0 2006.168.07:49:18.16#ibcon#about to read 4, iclass 6, count 0 2006.168.07:49:18.16#ibcon#read 4, iclass 6, count 0 2006.168.07:49:18.16#ibcon#about to read 5, iclass 6, count 0 2006.168.07:49:18.16#ibcon#read 5, iclass 6, count 0 2006.168.07:49:18.16#ibcon#about to read 6, iclass 6, count 0 2006.168.07:49:18.16#ibcon#read 6, iclass 6, count 0 2006.168.07:49:18.16#ibcon#end of sib2, iclass 6, count 0 2006.168.07:49:18.16#ibcon#*mode == 0, iclass 6, count 0 2006.168.07:49:18.16#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.168.07:49:18.16#ibcon#[25=USB\r\n] 2006.168.07:49:18.16#ibcon#*before write, iclass 6, count 0 2006.168.07:49:18.16#ibcon#enter sib2, iclass 6, count 0 2006.168.07:49:18.16#ibcon#flushed, iclass 6, count 0 2006.168.07:49:18.16#ibcon#about to write, iclass 6, count 0 2006.168.07:49:18.16#ibcon#wrote, iclass 6, count 0 2006.168.07:49:18.16#ibcon#about to read 3, iclass 6, count 0 2006.168.07:49:18.19#ibcon#read 3, iclass 6, count 0 2006.168.07:49:18.19#ibcon#about to read 4, iclass 6, count 0 2006.168.07:49:18.19#ibcon#read 4, iclass 6, count 0 2006.168.07:49:18.19#ibcon#about to read 5, iclass 6, count 0 2006.168.07:49:18.19#ibcon#read 5, iclass 6, count 0 2006.168.07:49:18.19#ibcon#about to read 6, iclass 6, count 0 2006.168.07:49:18.19#ibcon#read 6, iclass 6, count 0 2006.168.07:49:18.19#ibcon#end of sib2, iclass 6, count 0 2006.168.07:49:18.19#ibcon#*after write, iclass 6, count 0 2006.168.07:49:18.19#ibcon#*before return 0, iclass 6, count 0 2006.168.07:49:18.19#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:49:18.19#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:49:18.19#ibcon#about to clear, iclass 6 cls_cnt 0 2006.168.07:49:18.19#ibcon#cleared, iclass 6 cls_cnt 0 2006.168.07:49:18.19$vc4f8/valo=2,572.99 2006.168.07:49:18.19#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.168.07:49:18.19#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.168.07:49:18.19#ibcon#ireg 17 cls_cnt 0 2006.168.07:49:18.19#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:49:18.19#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:49:18.19#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:49:18.19#ibcon#enter wrdev, iclass 10, count 0 2006.168.07:49:18.19#ibcon#first serial, iclass 10, count 0 2006.168.07:49:18.19#ibcon#enter sib2, iclass 10, count 0 2006.168.07:49:18.19#ibcon#flushed, iclass 10, count 0 2006.168.07:49:18.19#ibcon#about to write, iclass 10, count 0 2006.168.07:49:18.19#ibcon#wrote, iclass 10, count 0 2006.168.07:49:18.19#ibcon#about to read 3, iclass 10, count 0 2006.168.07:49:18.21#ibcon#read 3, iclass 10, count 0 2006.168.07:49:18.21#ibcon#about to read 4, iclass 10, count 0 2006.168.07:49:18.21#ibcon#read 4, iclass 10, count 0 2006.168.07:49:18.21#ibcon#about to read 5, iclass 10, count 0 2006.168.07:49:18.21#ibcon#read 5, iclass 10, count 0 2006.168.07:49:18.21#ibcon#about to read 6, iclass 10, count 0 2006.168.07:49:18.21#ibcon#read 6, iclass 10, count 0 2006.168.07:49:18.21#ibcon#end of sib2, iclass 10, count 0 2006.168.07:49:18.21#ibcon#*mode == 0, iclass 10, count 0 2006.168.07:49:18.21#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.168.07:49:18.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.07:49:18.21#ibcon#*before write, iclass 10, count 0 2006.168.07:49:18.21#ibcon#enter sib2, iclass 10, count 0 2006.168.07:49:18.21#ibcon#flushed, iclass 10, count 0 2006.168.07:49:18.21#ibcon#about to write, iclass 10, count 0 2006.168.07:49:18.21#ibcon#wrote, iclass 10, count 0 2006.168.07:49:18.21#ibcon#about to read 3, iclass 10, count 0 2006.168.07:49:18.25#ibcon#read 3, iclass 10, count 0 2006.168.07:49:18.25#ibcon#about to read 4, iclass 10, count 0 2006.168.07:49:18.25#ibcon#read 4, iclass 10, count 0 2006.168.07:49:18.25#ibcon#about to read 5, iclass 10, count 0 2006.168.07:49:18.25#ibcon#read 5, iclass 10, count 0 2006.168.07:49:18.25#ibcon#about to read 6, iclass 10, count 0 2006.168.07:49:18.25#ibcon#read 6, iclass 10, count 0 2006.168.07:49:18.25#ibcon#end of sib2, iclass 10, count 0 2006.168.07:49:18.25#ibcon#*after write, iclass 10, count 0 2006.168.07:49:18.25#ibcon#*before return 0, iclass 10, count 0 2006.168.07:49:18.25#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:49:18.25#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:49:18.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.168.07:49:18.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.168.07:49:18.26$vc4f8/va=2,7 2006.168.07:49:18.26#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.168.07:49:18.26#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.168.07:49:18.26#ibcon#ireg 11 cls_cnt 2 2006.168.07:49:18.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:49:18.30#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:49:18.30#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:49:18.30#ibcon#enter wrdev, iclass 12, count 2 2006.168.07:49:18.30#ibcon#first serial, iclass 12, count 2 2006.168.07:49:18.30#ibcon#enter sib2, iclass 12, count 2 2006.168.07:49:18.30#ibcon#flushed, iclass 12, count 2 2006.168.07:49:18.30#ibcon#about to write, iclass 12, count 2 2006.168.07:49:18.30#ibcon#wrote, iclass 12, count 2 2006.168.07:49:18.30#ibcon#about to read 3, iclass 12, count 2 2006.168.07:49:18.33#ibcon#read 3, iclass 12, count 2 2006.168.07:49:18.33#ibcon#about to read 4, iclass 12, count 2 2006.168.07:49:18.33#ibcon#read 4, iclass 12, count 2 2006.168.07:49:18.33#ibcon#about to read 5, iclass 12, count 2 2006.168.07:49:18.33#ibcon#read 5, iclass 12, count 2 2006.168.07:49:18.33#ibcon#about to read 6, iclass 12, count 2 2006.168.07:49:18.33#ibcon#read 6, iclass 12, count 2 2006.168.07:49:18.33#ibcon#end of sib2, iclass 12, count 2 2006.168.07:49:18.33#ibcon#*mode == 0, iclass 12, count 2 2006.168.07:49:18.33#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.168.07:49:18.33#ibcon#[25=AT02-07\r\n] 2006.168.07:49:18.33#ibcon#*before write, iclass 12, count 2 2006.168.07:49:18.33#ibcon#enter sib2, iclass 12, count 2 2006.168.07:49:18.33#ibcon#flushed, iclass 12, count 2 2006.168.07:49:18.33#ibcon#about to write, iclass 12, count 2 2006.168.07:49:18.33#ibcon#wrote, iclass 12, count 2 2006.168.07:49:18.33#ibcon#about to read 3, iclass 12, count 2 2006.168.07:49:18.36#ibcon#read 3, iclass 12, count 2 2006.168.07:49:18.36#ibcon#about to read 4, iclass 12, count 2 2006.168.07:49:18.36#ibcon#read 4, iclass 12, count 2 2006.168.07:49:18.36#ibcon#about to read 5, iclass 12, count 2 2006.168.07:49:18.36#ibcon#read 5, iclass 12, count 2 2006.168.07:49:18.36#ibcon#about to read 6, iclass 12, count 2 2006.168.07:49:18.36#ibcon#read 6, iclass 12, count 2 2006.168.07:49:18.36#ibcon#end of sib2, iclass 12, count 2 2006.168.07:49:18.36#ibcon#*after write, iclass 12, count 2 2006.168.07:49:18.36#ibcon#*before return 0, iclass 12, count 2 2006.168.07:49:18.36#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:49:18.36#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:49:18.36#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.168.07:49:18.36#ibcon#ireg 7 cls_cnt 0 2006.168.07:49:18.36#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:49:18.48#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:49:18.48#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:49:18.48#ibcon#enter wrdev, iclass 12, count 0 2006.168.07:49:18.48#ibcon#first serial, iclass 12, count 0 2006.168.07:49:18.48#ibcon#enter sib2, iclass 12, count 0 2006.168.07:49:18.48#ibcon#flushed, iclass 12, count 0 2006.168.07:49:18.48#ibcon#about to write, iclass 12, count 0 2006.168.07:49:18.48#ibcon#wrote, iclass 12, count 0 2006.168.07:49:18.48#ibcon#about to read 3, iclass 12, count 0 2006.168.07:49:18.50#ibcon#read 3, iclass 12, count 0 2006.168.07:49:18.50#ibcon#about to read 4, iclass 12, count 0 2006.168.07:49:18.50#ibcon#read 4, iclass 12, count 0 2006.168.07:49:18.50#ibcon#about to read 5, iclass 12, count 0 2006.168.07:49:18.50#ibcon#read 5, iclass 12, count 0 2006.168.07:49:18.50#ibcon#about to read 6, iclass 12, count 0 2006.168.07:49:18.50#ibcon#read 6, iclass 12, count 0 2006.168.07:49:18.50#ibcon#end of sib2, iclass 12, count 0 2006.168.07:49:18.50#ibcon#*mode == 0, iclass 12, count 0 2006.168.07:49:18.50#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.168.07:49:18.50#ibcon#[25=USB\r\n] 2006.168.07:49:18.50#ibcon#*before write, iclass 12, count 0 2006.168.07:49:18.50#ibcon#enter sib2, iclass 12, count 0 2006.168.07:49:18.50#ibcon#flushed, iclass 12, count 0 2006.168.07:49:18.50#ibcon#about to write, iclass 12, count 0 2006.168.07:49:18.50#ibcon#wrote, iclass 12, count 0 2006.168.07:49:18.50#ibcon#about to read 3, iclass 12, count 0 2006.168.07:49:18.53#ibcon#read 3, iclass 12, count 0 2006.168.07:49:18.53#ibcon#about to read 4, iclass 12, count 0 2006.168.07:49:18.53#ibcon#read 4, iclass 12, count 0 2006.168.07:49:18.53#ibcon#about to read 5, iclass 12, count 0 2006.168.07:49:18.53#ibcon#read 5, iclass 12, count 0 2006.168.07:49:18.53#ibcon#about to read 6, iclass 12, count 0 2006.168.07:49:18.53#ibcon#read 6, iclass 12, count 0 2006.168.07:49:18.53#ibcon#end of sib2, iclass 12, count 0 2006.168.07:49:18.53#ibcon#*after write, iclass 12, count 0 2006.168.07:49:18.53#ibcon#*before return 0, iclass 12, count 0 2006.168.07:49:18.53#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:49:18.53#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:49:18.53#ibcon#about to clear, iclass 12 cls_cnt 0 2006.168.07:49:18.53#ibcon#cleared, iclass 12 cls_cnt 0 2006.168.07:49:18.53$vc4f8/valo=3,672.99 2006.168.07:49:18.53#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.168.07:49:18.53#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.168.07:49:18.53#ibcon#ireg 17 cls_cnt 0 2006.168.07:49:18.53#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:49:18.53#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:49:18.53#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:49:18.53#ibcon#enter wrdev, iclass 14, count 0 2006.168.07:49:18.53#ibcon#first serial, iclass 14, count 0 2006.168.07:49:18.53#ibcon#enter sib2, iclass 14, count 0 2006.168.07:49:18.53#ibcon#flushed, iclass 14, count 0 2006.168.07:49:18.53#ibcon#about to write, iclass 14, count 0 2006.168.07:49:18.53#ibcon#wrote, iclass 14, count 0 2006.168.07:49:18.53#ibcon#about to read 3, iclass 14, count 0 2006.168.07:49:18.55#ibcon#read 3, iclass 14, count 0 2006.168.07:49:18.55#ibcon#about to read 4, iclass 14, count 0 2006.168.07:49:18.55#ibcon#read 4, iclass 14, count 0 2006.168.07:49:18.55#ibcon#about to read 5, iclass 14, count 0 2006.168.07:49:18.55#ibcon#read 5, iclass 14, count 0 2006.168.07:49:18.55#ibcon#about to read 6, iclass 14, count 0 2006.168.07:49:18.55#ibcon#read 6, iclass 14, count 0 2006.168.07:49:18.55#ibcon#end of sib2, iclass 14, count 0 2006.168.07:49:18.55#ibcon#*mode == 0, iclass 14, count 0 2006.168.07:49:18.55#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.168.07:49:18.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.07:49:18.55#ibcon#*before write, iclass 14, count 0 2006.168.07:49:18.55#ibcon#enter sib2, iclass 14, count 0 2006.168.07:49:18.55#ibcon#flushed, iclass 14, count 0 2006.168.07:49:18.55#ibcon#about to write, iclass 14, count 0 2006.168.07:49:18.55#ibcon#wrote, iclass 14, count 0 2006.168.07:49:18.55#ibcon#about to read 3, iclass 14, count 0 2006.168.07:49:18.59#ibcon#read 3, iclass 14, count 0 2006.168.07:49:18.59#ibcon#about to read 4, iclass 14, count 0 2006.168.07:49:18.59#ibcon#read 4, iclass 14, count 0 2006.168.07:49:18.59#ibcon#about to read 5, iclass 14, count 0 2006.168.07:49:18.59#ibcon#read 5, iclass 14, count 0 2006.168.07:49:18.59#ibcon#about to read 6, iclass 14, count 0 2006.168.07:49:18.59#ibcon#read 6, iclass 14, count 0 2006.168.07:49:18.59#ibcon#end of sib2, iclass 14, count 0 2006.168.07:49:18.59#ibcon#*after write, iclass 14, count 0 2006.168.07:49:18.59#ibcon#*before return 0, iclass 14, count 0 2006.168.07:49:18.59#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:49:18.60#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:49:18.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.168.07:49:18.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.168.07:49:18.60$vc4f8/va=3,6 2006.168.07:49:18.60#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.168.07:49:18.60#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.168.07:49:18.60#ibcon#ireg 11 cls_cnt 2 2006.168.07:49:18.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:49:18.64#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:49:18.64#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:49:18.64#ibcon#enter wrdev, iclass 16, count 2 2006.168.07:49:18.64#ibcon#first serial, iclass 16, count 2 2006.168.07:49:18.64#ibcon#enter sib2, iclass 16, count 2 2006.168.07:49:18.64#ibcon#flushed, iclass 16, count 2 2006.168.07:49:18.64#ibcon#about to write, iclass 16, count 2 2006.168.07:49:18.64#ibcon#wrote, iclass 16, count 2 2006.168.07:49:18.64#ibcon#about to read 3, iclass 16, count 2 2006.168.07:49:18.67#ibcon#read 3, iclass 16, count 2 2006.168.07:49:18.67#ibcon#about to read 4, iclass 16, count 2 2006.168.07:49:18.67#ibcon#read 4, iclass 16, count 2 2006.168.07:49:18.67#ibcon#about to read 5, iclass 16, count 2 2006.168.07:49:18.67#ibcon#read 5, iclass 16, count 2 2006.168.07:49:18.67#ibcon#about to read 6, iclass 16, count 2 2006.168.07:49:18.67#ibcon#read 6, iclass 16, count 2 2006.168.07:49:18.67#ibcon#end of sib2, iclass 16, count 2 2006.168.07:49:18.67#ibcon#*mode == 0, iclass 16, count 2 2006.168.07:49:18.67#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.168.07:49:18.67#ibcon#[25=AT03-06\r\n] 2006.168.07:49:18.67#ibcon#*before write, iclass 16, count 2 2006.168.07:49:18.67#ibcon#enter sib2, iclass 16, count 2 2006.168.07:49:18.67#ibcon#flushed, iclass 16, count 2 2006.168.07:49:18.67#ibcon#about to write, iclass 16, count 2 2006.168.07:49:18.67#ibcon#wrote, iclass 16, count 2 2006.168.07:49:18.67#ibcon#about to read 3, iclass 16, count 2 2006.168.07:49:18.70#ibcon#read 3, iclass 16, count 2 2006.168.07:49:18.70#ibcon#about to read 4, iclass 16, count 2 2006.168.07:49:18.70#ibcon#read 4, iclass 16, count 2 2006.168.07:49:18.70#ibcon#about to read 5, iclass 16, count 2 2006.168.07:49:18.70#ibcon#read 5, iclass 16, count 2 2006.168.07:49:18.70#ibcon#about to read 6, iclass 16, count 2 2006.168.07:49:18.70#ibcon#read 6, iclass 16, count 2 2006.168.07:49:18.70#ibcon#end of sib2, iclass 16, count 2 2006.168.07:49:18.70#ibcon#*after write, iclass 16, count 2 2006.168.07:49:18.70#ibcon#*before return 0, iclass 16, count 2 2006.168.07:49:18.70#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:49:18.70#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:49:18.70#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.168.07:49:18.70#ibcon#ireg 7 cls_cnt 0 2006.168.07:49:18.70#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:49:18.82#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:49:18.82#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:49:18.82#ibcon#enter wrdev, iclass 16, count 0 2006.168.07:49:18.82#ibcon#first serial, iclass 16, count 0 2006.168.07:49:18.82#ibcon#enter sib2, iclass 16, count 0 2006.168.07:49:18.82#ibcon#flushed, iclass 16, count 0 2006.168.07:49:18.82#ibcon#about to write, iclass 16, count 0 2006.168.07:49:18.82#ibcon#wrote, iclass 16, count 0 2006.168.07:49:18.82#ibcon#about to read 3, iclass 16, count 0 2006.168.07:49:18.84#ibcon#read 3, iclass 16, count 0 2006.168.07:49:18.84#ibcon#about to read 4, iclass 16, count 0 2006.168.07:49:18.84#ibcon#read 4, iclass 16, count 0 2006.168.07:49:18.84#ibcon#about to read 5, iclass 16, count 0 2006.168.07:49:18.84#ibcon#read 5, iclass 16, count 0 2006.168.07:49:18.84#ibcon#about to read 6, iclass 16, count 0 2006.168.07:49:18.84#ibcon#read 6, iclass 16, count 0 2006.168.07:49:18.84#ibcon#end of sib2, iclass 16, count 0 2006.168.07:49:18.84#ibcon#*mode == 0, iclass 16, count 0 2006.168.07:49:18.84#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.168.07:49:18.84#ibcon#[25=USB\r\n] 2006.168.07:49:18.84#ibcon#*before write, iclass 16, count 0 2006.168.07:49:18.84#ibcon#enter sib2, iclass 16, count 0 2006.168.07:49:18.84#ibcon#flushed, iclass 16, count 0 2006.168.07:49:18.84#ibcon#about to write, iclass 16, count 0 2006.168.07:49:18.84#ibcon#wrote, iclass 16, count 0 2006.168.07:49:18.84#ibcon#about to read 3, iclass 16, count 0 2006.168.07:49:18.87#ibcon#read 3, iclass 16, count 0 2006.168.07:49:18.87#ibcon#about to read 4, iclass 16, count 0 2006.168.07:49:18.87#ibcon#read 4, iclass 16, count 0 2006.168.07:49:18.87#ibcon#about to read 5, iclass 16, count 0 2006.168.07:49:18.87#ibcon#read 5, iclass 16, count 0 2006.168.07:49:18.87#ibcon#about to read 6, iclass 16, count 0 2006.168.07:49:18.87#ibcon#read 6, iclass 16, count 0 2006.168.07:49:18.87#ibcon#end of sib2, iclass 16, count 0 2006.168.07:49:18.87#ibcon#*after write, iclass 16, count 0 2006.168.07:49:18.87#ibcon#*before return 0, iclass 16, count 0 2006.168.07:49:18.87#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:49:18.87#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:49:18.87#ibcon#about to clear, iclass 16 cls_cnt 0 2006.168.07:49:18.87#ibcon#cleared, iclass 16 cls_cnt 0 2006.168.07:49:18.87$vc4f8/valo=4,832.99 2006.168.07:49:18.87#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.168.07:49:18.87#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.168.07:49:18.87#ibcon#ireg 17 cls_cnt 0 2006.168.07:49:18.87#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:49:18.87#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:49:18.87#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:49:18.87#ibcon#enter wrdev, iclass 18, count 0 2006.168.07:49:18.87#ibcon#first serial, iclass 18, count 0 2006.168.07:49:18.87#ibcon#enter sib2, iclass 18, count 0 2006.168.07:49:18.87#ibcon#flushed, iclass 18, count 0 2006.168.07:49:18.87#ibcon#about to write, iclass 18, count 0 2006.168.07:49:18.87#ibcon#wrote, iclass 18, count 0 2006.168.07:49:18.87#ibcon#about to read 3, iclass 18, count 0 2006.168.07:49:18.89#ibcon#read 3, iclass 18, count 0 2006.168.07:49:18.89#ibcon#about to read 4, iclass 18, count 0 2006.168.07:49:18.89#ibcon#read 4, iclass 18, count 0 2006.168.07:49:18.89#ibcon#about to read 5, iclass 18, count 0 2006.168.07:49:18.89#ibcon#read 5, iclass 18, count 0 2006.168.07:49:18.89#ibcon#about to read 6, iclass 18, count 0 2006.168.07:49:18.89#ibcon#read 6, iclass 18, count 0 2006.168.07:49:18.89#ibcon#end of sib2, iclass 18, count 0 2006.168.07:49:18.89#ibcon#*mode == 0, iclass 18, count 0 2006.168.07:49:18.89#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.07:49:18.89#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.07:49:18.89#ibcon#*before write, iclass 18, count 0 2006.168.07:49:18.89#ibcon#enter sib2, iclass 18, count 0 2006.168.07:49:18.89#ibcon#flushed, iclass 18, count 0 2006.168.07:49:18.89#ibcon#about to write, iclass 18, count 0 2006.168.07:49:18.89#ibcon#wrote, iclass 18, count 0 2006.168.07:49:18.89#ibcon#about to read 3, iclass 18, count 0 2006.168.07:49:18.93#ibcon#read 3, iclass 18, count 0 2006.168.07:49:18.93#ibcon#about to read 4, iclass 18, count 0 2006.168.07:49:18.93#ibcon#read 4, iclass 18, count 0 2006.168.07:49:18.93#ibcon#about to read 5, iclass 18, count 0 2006.168.07:49:18.93#ibcon#read 5, iclass 18, count 0 2006.168.07:49:18.93#ibcon#about to read 6, iclass 18, count 0 2006.168.07:49:18.93#ibcon#read 6, iclass 18, count 0 2006.168.07:49:18.93#ibcon#end of sib2, iclass 18, count 0 2006.168.07:49:18.93#ibcon#*after write, iclass 18, count 0 2006.168.07:49:18.93#ibcon#*before return 0, iclass 18, count 0 2006.168.07:49:18.93#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:49:18.93#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:49:18.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.07:49:18.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.07:49:18.93$vc4f8/va=4,7 2006.168.07:49:18.93#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.168.07:49:18.93#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.168.07:49:18.93#ibcon#ireg 11 cls_cnt 2 2006.168.07:49:18.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:49:18.99#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:49:18.99#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:49:18.99#ibcon#enter wrdev, iclass 20, count 2 2006.168.07:49:18.99#ibcon#first serial, iclass 20, count 2 2006.168.07:49:18.99#ibcon#enter sib2, iclass 20, count 2 2006.168.07:49:18.99#ibcon#flushed, iclass 20, count 2 2006.168.07:49:18.99#ibcon#about to write, iclass 20, count 2 2006.168.07:49:18.99#ibcon#wrote, iclass 20, count 2 2006.168.07:49:18.99#ibcon#about to read 3, iclass 20, count 2 2006.168.07:49:19.01#ibcon#read 3, iclass 20, count 2 2006.168.07:49:19.01#ibcon#about to read 4, iclass 20, count 2 2006.168.07:49:19.01#ibcon#read 4, iclass 20, count 2 2006.168.07:49:19.01#ibcon#about to read 5, iclass 20, count 2 2006.168.07:49:19.01#ibcon#read 5, iclass 20, count 2 2006.168.07:49:19.01#ibcon#about to read 6, iclass 20, count 2 2006.168.07:49:19.01#ibcon#read 6, iclass 20, count 2 2006.168.07:49:19.01#ibcon#end of sib2, iclass 20, count 2 2006.168.07:49:19.01#ibcon#*mode == 0, iclass 20, count 2 2006.168.07:49:19.01#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.168.07:49:19.01#ibcon#[25=AT04-07\r\n] 2006.168.07:49:19.01#ibcon#*before write, iclass 20, count 2 2006.168.07:49:19.01#ibcon#enter sib2, iclass 20, count 2 2006.168.07:49:19.01#ibcon#flushed, iclass 20, count 2 2006.168.07:49:19.01#ibcon#about to write, iclass 20, count 2 2006.168.07:49:19.01#ibcon#wrote, iclass 20, count 2 2006.168.07:49:19.01#ibcon#about to read 3, iclass 20, count 2 2006.168.07:49:19.04#ibcon#read 3, iclass 20, count 2 2006.168.07:49:19.04#ibcon#about to read 4, iclass 20, count 2 2006.168.07:49:19.04#ibcon#read 4, iclass 20, count 2 2006.168.07:49:19.04#ibcon#about to read 5, iclass 20, count 2 2006.168.07:49:19.04#ibcon#read 5, iclass 20, count 2 2006.168.07:49:19.04#ibcon#about to read 6, iclass 20, count 2 2006.168.07:49:19.04#ibcon#read 6, iclass 20, count 2 2006.168.07:49:19.04#ibcon#end of sib2, iclass 20, count 2 2006.168.07:49:19.04#ibcon#*after write, iclass 20, count 2 2006.168.07:49:19.04#ibcon#*before return 0, iclass 20, count 2 2006.168.07:49:19.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:49:19.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:49:19.04#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.168.07:49:19.04#ibcon#ireg 7 cls_cnt 0 2006.168.07:49:19.04#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:49:19.16#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:49:19.16#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:49:19.16#ibcon#enter wrdev, iclass 20, count 0 2006.168.07:49:19.16#ibcon#first serial, iclass 20, count 0 2006.168.07:49:19.16#ibcon#enter sib2, iclass 20, count 0 2006.168.07:49:19.16#ibcon#flushed, iclass 20, count 0 2006.168.07:49:19.16#ibcon#about to write, iclass 20, count 0 2006.168.07:49:19.16#ibcon#wrote, iclass 20, count 0 2006.168.07:49:19.16#ibcon#about to read 3, iclass 20, count 0 2006.168.07:49:19.18#ibcon#read 3, iclass 20, count 0 2006.168.07:49:19.18#ibcon#about to read 4, iclass 20, count 0 2006.168.07:49:19.18#ibcon#read 4, iclass 20, count 0 2006.168.07:49:19.18#ibcon#about to read 5, iclass 20, count 0 2006.168.07:49:19.18#ibcon#read 5, iclass 20, count 0 2006.168.07:49:19.18#ibcon#about to read 6, iclass 20, count 0 2006.168.07:49:19.18#ibcon#read 6, iclass 20, count 0 2006.168.07:49:19.18#ibcon#end of sib2, iclass 20, count 0 2006.168.07:49:19.18#ibcon#*mode == 0, iclass 20, count 0 2006.168.07:49:19.18#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.168.07:49:19.18#ibcon#[25=USB\r\n] 2006.168.07:49:19.18#ibcon#*before write, iclass 20, count 0 2006.168.07:49:19.18#ibcon#enter sib2, iclass 20, count 0 2006.168.07:49:19.18#ibcon#flushed, iclass 20, count 0 2006.168.07:49:19.18#ibcon#about to write, iclass 20, count 0 2006.168.07:49:19.18#ibcon#wrote, iclass 20, count 0 2006.168.07:49:19.18#ibcon#about to read 3, iclass 20, count 0 2006.168.07:49:19.21#ibcon#read 3, iclass 20, count 0 2006.168.07:49:19.21#ibcon#about to read 4, iclass 20, count 0 2006.168.07:49:19.21#ibcon#read 4, iclass 20, count 0 2006.168.07:49:19.21#ibcon#about to read 5, iclass 20, count 0 2006.168.07:49:19.21#ibcon#read 5, iclass 20, count 0 2006.168.07:49:19.21#ibcon#about to read 6, iclass 20, count 0 2006.168.07:49:19.21#ibcon#read 6, iclass 20, count 0 2006.168.07:49:19.21#ibcon#end of sib2, iclass 20, count 0 2006.168.07:49:19.21#ibcon#*after write, iclass 20, count 0 2006.168.07:49:19.21#ibcon#*before return 0, iclass 20, count 0 2006.168.07:49:19.21#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:49:19.21#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:49:19.21#ibcon#about to clear, iclass 20 cls_cnt 0 2006.168.07:49:19.21#ibcon#cleared, iclass 20 cls_cnt 0 2006.168.07:49:19.21$vc4f8/valo=5,652.99 2006.168.07:49:19.21#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.168.07:49:19.21#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.168.07:49:19.21#ibcon#ireg 17 cls_cnt 0 2006.168.07:49:19.21#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:49:19.21#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:49:19.21#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:49:19.21#ibcon#enter wrdev, iclass 22, count 0 2006.168.07:49:19.21#ibcon#first serial, iclass 22, count 0 2006.168.07:49:19.21#ibcon#enter sib2, iclass 22, count 0 2006.168.07:49:19.21#ibcon#flushed, iclass 22, count 0 2006.168.07:49:19.21#ibcon#about to write, iclass 22, count 0 2006.168.07:49:19.21#ibcon#wrote, iclass 22, count 0 2006.168.07:49:19.21#ibcon#about to read 3, iclass 22, count 0 2006.168.07:49:19.23#ibcon#read 3, iclass 22, count 0 2006.168.07:49:19.23#ibcon#about to read 4, iclass 22, count 0 2006.168.07:49:19.23#ibcon#read 4, iclass 22, count 0 2006.168.07:49:19.23#ibcon#about to read 5, iclass 22, count 0 2006.168.07:49:19.23#ibcon#read 5, iclass 22, count 0 2006.168.07:49:19.23#ibcon#about to read 6, iclass 22, count 0 2006.168.07:49:19.23#ibcon#read 6, iclass 22, count 0 2006.168.07:49:19.23#ibcon#end of sib2, iclass 22, count 0 2006.168.07:49:19.23#ibcon#*mode == 0, iclass 22, count 0 2006.168.07:49:19.23#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.168.07:49:19.23#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.07:49:19.23#ibcon#*before write, iclass 22, count 0 2006.168.07:49:19.23#ibcon#enter sib2, iclass 22, count 0 2006.168.07:49:19.23#ibcon#flushed, iclass 22, count 0 2006.168.07:49:19.23#ibcon#about to write, iclass 22, count 0 2006.168.07:49:19.23#ibcon#wrote, iclass 22, count 0 2006.168.07:49:19.23#ibcon#about to read 3, iclass 22, count 0 2006.168.07:49:19.27#ibcon#read 3, iclass 22, count 0 2006.168.07:49:19.27#ibcon#about to read 4, iclass 22, count 0 2006.168.07:49:19.27#ibcon#read 4, iclass 22, count 0 2006.168.07:49:19.27#ibcon#about to read 5, iclass 22, count 0 2006.168.07:49:19.27#ibcon#read 5, iclass 22, count 0 2006.168.07:49:19.27#ibcon#about to read 6, iclass 22, count 0 2006.168.07:49:19.27#ibcon#read 6, iclass 22, count 0 2006.168.07:49:19.27#ibcon#end of sib2, iclass 22, count 0 2006.168.07:49:19.27#ibcon#*after write, iclass 22, count 0 2006.168.07:49:19.27#ibcon#*before return 0, iclass 22, count 0 2006.168.07:49:19.27#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:49:19.27#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:49:19.27#ibcon#about to clear, iclass 22 cls_cnt 0 2006.168.07:49:19.27#ibcon#cleared, iclass 22 cls_cnt 0 2006.168.07:49:19.27$vc4f8/va=5,7 2006.168.07:49:19.27#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.168.07:49:19.27#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.168.07:49:19.27#ibcon#ireg 11 cls_cnt 2 2006.168.07:49:19.27#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:49:19.33#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:49:19.33#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:49:19.33#ibcon#enter wrdev, iclass 24, count 2 2006.168.07:49:19.33#ibcon#first serial, iclass 24, count 2 2006.168.07:49:19.33#ibcon#enter sib2, iclass 24, count 2 2006.168.07:49:19.33#ibcon#flushed, iclass 24, count 2 2006.168.07:49:19.33#ibcon#about to write, iclass 24, count 2 2006.168.07:49:19.33#ibcon#wrote, iclass 24, count 2 2006.168.07:49:19.33#ibcon#about to read 3, iclass 24, count 2 2006.168.07:49:19.35#ibcon#read 3, iclass 24, count 2 2006.168.07:49:19.35#ibcon#about to read 4, iclass 24, count 2 2006.168.07:49:19.35#ibcon#read 4, iclass 24, count 2 2006.168.07:49:19.35#ibcon#about to read 5, iclass 24, count 2 2006.168.07:49:19.35#ibcon#read 5, iclass 24, count 2 2006.168.07:49:19.35#ibcon#about to read 6, iclass 24, count 2 2006.168.07:49:19.35#ibcon#read 6, iclass 24, count 2 2006.168.07:49:19.35#ibcon#end of sib2, iclass 24, count 2 2006.168.07:49:19.35#ibcon#*mode == 0, iclass 24, count 2 2006.168.07:49:19.35#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.168.07:49:19.35#ibcon#[25=AT05-07\r\n] 2006.168.07:49:19.35#ibcon#*before write, iclass 24, count 2 2006.168.07:49:19.35#ibcon#enter sib2, iclass 24, count 2 2006.168.07:49:19.35#ibcon#flushed, iclass 24, count 2 2006.168.07:49:19.35#ibcon#about to write, iclass 24, count 2 2006.168.07:49:19.35#ibcon#wrote, iclass 24, count 2 2006.168.07:49:19.35#ibcon#about to read 3, iclass 24, count 2 2006.168.07:49:19.38#ibcon#read 3, iclass 24, count 2 2006.168.07:49:19.38#ibcon#about to read 4, iclass 24, count 2 2006.168.07:49:19.38#ibcon#read 4, iclass 24, count 2 2006.168.07:49:19.38#ibcon#about to read 5, iclass 24, count 2 2006.168.07:49:19.38#ibcon#read 5, iclass 24, count 2 2006.168.07:49:19.38#ibcon#about to read 6, iclass 24, count 2 2006.168.07:49:19.38#ibcon#read 6, iclass 24, count 2 2006.168.07:49:19.38#ibcon#end of sib2, iclass 24, count 2 2006.168.07:49:19.38#ibcon#*after write, iclass 24, count 2 2006.168.07:49:19.38#ibcon#*before return 0, iclass 24, count 2 2006.168.07:49:19.38#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:49:19.38#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:49:19.38#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.168.07:49:19.38#ibcon#ireg 7 cls_cnt 0 2006.168.07:49:19.38#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:49:19.50#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:49:19.50#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:49:19.50#ibcon#enter wrdev, iclass 24, count 0 2006.168.07:49:19.50#ibcon#first serial, iclass 24, count 0 2006.168.07:49:19.50#ibcon#enter sib2, iclass 24, count 0 2006.168.07:49:19.50#ibcon#flushed, iclass 24, count 0 2006.168.07:49:19.50#ibcon#about to write, iclass 24, count 0 2006.168.07:49:19.50#ibcon#wrote, iclass 24, count 0 2006.168.07:49:19.50#ibcon#about to read 3, iclass 24, count 0 2006.168.07:49:19.52#ibcon#read 3, iclass 24, count 0 2006.168.07:49:19.52#ibcon#about to read 4, iclass 24, count 0 2006.168.07:49:19.52#ibcon#read 4, iclass 24, count 0 2006.168.07:49:19.52#ibcon#about to read 5, iclass 24, count 0 2006.168.07:49:19.52#ibcon#read 5, iclass 24, count 0 2006.168.07:49:19.52#ibcon#about to read 6, iclass 24, count 0 2006.168.07:49:19.52#ibcon#read 6, iclass 24, count 0 2006.168.07:49:19.52#ibcon#end of sib2, iclass 24, count 0 2006.168.07:49:19.52#ibcon#*mode == 0, iclass 24, count 0 2006.168.07:49:19.52#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.168.07:49:19.52#ibcon#[25=USB\r\n] 2006.168.07:49:19.52#ibcon#*before write, iclass 24, count 0 2006.168.07:49:19.52#ibcon#enter sib2, iclass 24, count 0 2006.168.07:49:19.52#ibcon#flushed, iclass 24, count 0 2006.168.07:49:19.52#ibcon#about to write, iclass 24, count 0 2006.168.07:49:19.52#ibcon#wrote, iclass 24, count 0 2006.168.07:49:19.52#ibcon#about to read 3, iclass 24, count 0 2006.168.07:49:19.55#ibcon#read 3, iclass 24, count 0 2006.168.07:49:19.55#ibcon#about to read 4, iclass 24, count 0 2006.168.07:49:19.55#ibcon#read 4, iclass 24, count 0 2006.168.07:49:19.55#ibcon#about to read 5, iclass 24, count 0 2006.168.07:49:19.55#ibcon#read 5, iclass 24, count 0 2006.168.07:49:19.55#ibcon#about to read 6, iclass 24, count 0 2006.168.07:49:19.55#ibcon#read 6, iclass 24, count 0 2006.168.07:49:19.55#ibcon#end of sib2, iclass 24, count 0 2006.168.07:49:19.55#ibcon#*after write, iclass 24, count 0 2006.168.07:49:19.55#ibcon#*before return 0, iclass 24, count 0 2006.168.07:49:19.55#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:49:19.55#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:49:19.55#ibcon#about to clear, iclass 24 cls_cnt 0 2006.168.07:49:19.55#ibcon#cleared, iclass 24 cls_cnt 0 2006.168.07:49:19.55$vc4f8/valo=6,772.99 2006.168.07:49:19.55#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.168.07:49:19.55#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.168.07:49:19.55#ibcon#ireg 17 cls_cnt 0 2006.168.07:49:19.55#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:49:19.55#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:49:19.55#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:49:19.55#ibcon#enter wrdev, iclass 26, count 0 2006.168.07:49:19.55#ibcon#first serial, iclass 26, count 0 2006.168.07:49:19.55#ibcon#enter sib2, iclass 26, count 0 2006.168.07:49:19.55#ibcon#flushed, iclass 26, count 0 2006.168.07:49:19.55#ibcon#about to write, iclass 26, count 0 2006.168.07:49:19.55#ibcon#wrote, iclass 26, count 0 2006.168.07:49:19.55#ibcon#about to read 3, iclass 26, count 0 2006.168.07:49:19.57#ibcon#read 3, iclass 26, count 0 2006.168.07:49:19.57#ibcon#about to read 4, iclass 26, count 0 2006.168.07:49:19.57#ibcon#read 4, iclass 26, count 0 2006.168.07:49:19.57#ibcon#about to read 5, iclass 26, count 0 2006.168.07:49:19.57#ibcon#read 5, iclass 26, count 0 2006.168.07:49:19.57#ibcon#about to read 6, iclass 26, count 0 2006.168.07:49:19.57#ibcon#read 6, iclass 26, count 0 2006.168.07:49:19.57#ibcon#end of sib2, iclass 26, count 0 2006.168.07:49:19.57#ibcon#*mode == 0, iclass 26, count 0 2006.168.07:49:19.57#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.168.07:49:19.57#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.07:49:19.57#ibcon#*before write, iclass 26, count 0 2006.168.07:49:19.57#ibcon#enter sib2, iclass 26, count 0 2006.168.07:49:19.57#ibcon#flushed, iclass 26, count 0 2006.168.07:49:19.57#ibcon#about to write, iclass 26, count 0 2006.168.07:49:19.57#ibcon#wrote, iclass 26, count 0 2006.168.07:49:19.57#ibcon#about to read 3, iclass 26, count 0 2006.168.07:49:19.61#ibcon#read 3, iclass 26, count 0 2006.168.07:49:19.61#ibcon#about to read 4, iclass 26, count 0 2006.168.07:49:19.61#ibcon#read 4, iclass 26, count 0 2006.168.07:49:19.61#ibcon#about to read 5, iclass 26, count 0 2006.168.07:49:19.61#ibcon#read 5, iclass 26, count 0 2006.168.07:49:19.61#ibcon#about to read 6, iclass 26, count 0 2006.168.07:49:19.61#ibcon#read 6, iclass 26, count 0 2006.168.07:49:19.61#ibcon#end of sib2, iclass 26, count 0 2006.168.07:49:19.61#ibcon#*after write, iclass 26, count 0 2006.168.07:49:19.61#ibcon#*before return 0, iclass 26, count 0 2006.168.07:49:19.61#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:49:19.61#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:49:19.61#ibcon#about to clear, iclass 26 cls_cnt 0 2006.168.07:49:19.61#ibcon#cleared, iclass 26 cls_cnt 0 2006.168.07:49:19.61$vc4f8/va=6,6 2006.168.07:49:19.61#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.168.07:49:19.61#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.168.07:49:19.61#ibcon#ireg 11 cls_cnt 2 2006.168.07:49:19.61#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.168.07:49:19.67#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.168.07:49:19.67#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.168.07:49:19.67#ibcon#enter wrdev, iclass 28, count 2 2006.168.07:49:19.67#ibcon#first serial, iclass 28, count 2 2006.168.07:49:19.67#ibcon#enter sib2, iclass 28, count 2 2006.168.07:49:19.67#ibcon#flushed, iclass 28, count 2 2006.168.07:49:19.67#ibcon#about to write, iclass 28, count 2 2006.168.07:49:19.67#ibcon#wrote, iclass 28, count 2 2006.168.07:49:19.67#ibcon#about to read 3, iclass 28, count 2 2006.168.07:49:19.69#ibcon#read 3, iclass 28, count 2 2006.168.07:49:19.69#ibcon#about to read 4, iclass 28, count 2 2006.168.07:49:19.69#ibcon#read 4, iclass 28, count 2 2006.168.07:49:19.69#ibcon#about to read 5, iclass 28, count 2 2006.168.07:49:19.69#ibcon#read 5, iclass 28, count 2 2006.168.07:49:19.69#ibcon#about to read 6, iclass 28, count 2 2006.168.07:49:19.69#ibcon#read 6, iclass 28, count 2 2006.168.07:49:19.69#ibcon#end of sib2, iclass 28, count 2 2006.168.07:49:19.69#ibcon#*mode == 0, iclass 28, count 2 2006.168.07:49:19.69#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.168.07:49:19.69#ibcon#[25=AT06-06\r\n] 2006.168.07:49:19.69#ibcon#*before write, iclass 28, count 2 2006.168.07:49:19.69#ibcon#enter sib2, iclass 28, count 2 2006.168.07:49:19.69#ibcon#flushed, iclass 28, count 2 2006.168.07:49:19.69#ibcon#about to write, iclass 28, count 2 2006.168.07:49:19.69#ibcon#wrote, iclass 28, count 2 2006.168.07:49:19.69#ibcon#about to read 3, iclass 28, count 2 2006.168.07:49:19.72#ibcon#read 3, iclass 28, count 2 2006.168.07:49:19.72#ibcon#about to read 4, iclass 28, count 2 2006.168.07:49:19.72#ibcon#read 4, iclass 28, count 2 2006.168.07:49:19.72#ibcon#about to read 5, iclass 28, count 2 2006.168.07:49:19.72#ibcon#read 5, iclass 28, count 2 2006.168.07:49:19.72#ibcon#about to read 6, iclass 28, count 2 2006.168.07:49:19.72#ibcon#read 6, iclass 28, count 2 2006.168.07:49:19.72#ibcon#end of sib2, iclass 28, count 2 2006.168.07:49:19.72#ibcon#*after write, iclass 28, count 2 2006.168.07:49:19.72#ibcon#*before return 0, iclass 28, count 2 2006.168.07:49:19.72#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.168.07:49:19.72#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.168.07:49:19.72#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.168.07:49:19.72#ibcon#ireg 7 cls_cnt 0 2006.168.07:49:19.72#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.168.07:49:19.84#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.168.07:49:19.84#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.168.07:49:19.84#ibcon#enter wrdev, iclass 28, count 0 2006.168.07:49:19.84#ibcon#first serial, iclass 28, count 0 2006.168.07:49:19.84#ibcon#enter sib2, iclass 28, count 0 2006.168.07:49:19.84#ibcon#flushed, iclass 28, count 0 2006.168.07:49:19.84#ibcon#about to write, iclass 28, count 0 2006.168.07:49:19.84#ibcon#wrote, iclass 28, count 0 2006.168.07:49:19.84#ibcon#about to read 3, iclass 28, count 0 2006.168.07:49:19.86#ibcon#read 3, iclass 28, count 0 2006.168.07:49:19.86#ibcon#about to read 4, iclass 28, count 0 2006.168.07:49:19.86#ibcon#read 4, iclass 28, count 0 2006.168.07:49:19.86#ibcon#about to read 5, iclass 28, count 0 2006.168.07:49:19.86#ibcon#read 5, iclass 28, count 0 2006.168.07:49:19.86#ibcon#about to read 6, iclass 28, count 0 2006.168.07:49:19.86#ibcon#read 6, iclass 28, count 0 2006.168.07:49:19.86#ibcon#end of sib2, iclass 28, count 0 2006.168.07:49:19.86#ibcon#*mode == 0, iclass 28, count 0 2006.168.07:49:19.86#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.168.07:49:19.86#ibcon#[25=USB\r\n] 2006.168.07:49:19.86#ibcon#*before write, iclass 28, count 0 2006.168.07:49:19.86#ibcon#enter sib2, iclass 28, count 0 2006.168.07:49:19.86#ibcon#flushed, iclass 28, count 0 2006.168.07:49:19.86#ibcon#about to write, iclass 28, count 0 2006.168.07:49:19.86#ibcon#wrote, iclass 28, count 0 2006.168.07:49:19.86#ibcon#about to read 3, iclass 28, count 0 2006.168.07:49:19.89#ibcon#read 3, iclass 28, count 0 2006.168.07:49:19.89#ibcon#about to read 4, iclass 28, count 0 2006.168.07:49:19.89#ibcon#read 4, iclass 28, count 0 2006.168.07:49:19.89#ibcon#about to read 5, iclass 28, count 0 2006.168.07:49:19.89#ibcon#read 5, iclass 28, count 0 2006.168.07:49:19.89#ibcon#about to read 6, iclass 28, count 0 2006.168.07:49:19.89#ibcon#read 6, iclass 28, count 0 2006.168.07:49:19.89#ibcon#end of sib2, iclass 28, count 0 2006.168.07:49:19.89#ibcon#*after write, iclass 28, count 0 2006.168.07:49:19.89#ibcon#*before return 0, iclass 28, count 0 2006.168.07:49:19.89#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.168.07:49:19.89#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.168.07:49:19.89#ibcon#about to clear, iclass 28 cls_cnt 0 2006.168.07:49:19.89#ibcon#cleared, iclass 28 cls_cnt 0 2006.168.07:49:19.89$vc4f8/valo=7,832.99 2006.168.07:49:19.89#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.168.07:49:19.89#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.168.07:49:19.89#ibcon#ireg 17 cls_cnt 0 2006.168.07:49:19.89#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:49:19.89#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:49:19.89#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:49:19.89#ibcon#enter wrdev, iclass 30, count 0 2006.168.07:49:19.89#ibcon#first serial, iclass 30, count 0 2006.168.07:49:19.89#ibcon#enter sib2, iclass 30, count 0 2006.168.07:49:19.89#ibcon#flushed, iclass 30, count 0 2006.168.07:49:19.89#ibcon#about to write, iclass 30, count 0 2006.168.07:49:19.89#ibcon#wrote, iclass 30, count 0 2006.168.07:49:19.89#ibcon#about to read 3, iclass 30, count 0 2006.168.07:49:19.91#ibcon#read 3, iclass 30, count 0 2006.168.07:49:19.91#ibcon#about to read 4, iclass 30, count 0 2006.168.07:49:19.91#ibcon#read 4, iclass 30, count 0 2006.168.07:49:19.91#ibcon#about to read 5, iclass 30, count 0 2006.168.07:49:19.91#ibcon#read 5, iclass 30, count 0 2006.168.07:49:19.91#ibcon#about to read 6, iclass 30, count 0 2006.168.07:49:19.91#ibcon#read 6, iclass 30, count 0 2006.168.07:49:19.91#ibcon#end of sib2, iclass 30, count 0 2006.168.07:49:19.91#ibcon#*mode == 0, iclass 30, count 0 2006.168.07:49:19.91#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.168.07:49:19.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.07:49:19.91#ibcon#*before write, iclass 30, count 0 2006.168.07:49:19.91#ibcon#enter sib2, iclass 30, count 0 2006.168.07:49:19.91#ibcon#flushed, iclass 30, count 0 2006.168.07:49:19.91#ibcon#about to write, iclass 30, count 0 2006.168.07:49:19.91#ibcon#wrote, iclass 30, count 0 2006.168.07:49:19.91#ibcon#about to read 3, iclass 30, count 0 2006.168.07:49:19.95#ibcon#read 3, iclass 30, count 0 2006.168.07:49:19.95#ibcon#about to read 4, iclass 30, count 0 2006.168.07:49:19.95#ibcon#read 4, iclass 30, count 0 2006.168.07:49:19.95#ibcon#about to read 5, iclass 30, count 0 2006.168.07:49:19.95#ibcon#read 5, iclass 30, count 0 2006.168.07:49:19.95#ibcon#about to read 6, iclass 30, count 0 2006.168.07:49:19.95#ibcon#read 6, iclass 30, count 0 2006.168.07:49:19.95#ibcon#end of sib2, iclass 30, count 0 2006.168.07:49:19.95#ibcon#*after write, iclass 30, count 0 2006.168.07:49:19.95#ibcon#*before return 0, iclass 30, count 0 2006.168.07:49:19.95#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:49:19.95#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:49:19.95#ibcon#about to clear, iclass 30 cls_cnt 0 2006.168.07:49:19.95#ibcon#cleared, iclass 30 cls_cnt 0 2006.168.07:49:19.95$vc4f8/va=7,6 2006.168.07:49:19.95#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.168.07:49:19.95#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.168.07:49:19.95#ibcon#ireg 11 cls_cnt 2 2006.168.07:49:19.95#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:49:20.01#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:49:20.01#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:49:20.01#ibcon#enter wrdev, iclass 32, count 2 2006.168.07:49:20.01#ibcon#first serial, iclass 32, count 2 2006.168.07:49:20.01#ibcon#enter sib2, iclass 32, count 2 2006.168.07:49:20.01#ibcon#flushed, iclass 32, count 2 2006.168.07:49:20.01#ibcon#about to write, iclass 32, count 2 2006.168.07:49:20.01#ibcon#wrote, iclass 32, count 2 2006.168.07:49:20.01#ibcon#about to read 3, iclass 32, count 2 2006.168.07:49:20.03#ibcon#read 3, iclass 32, count 2 2006.168.07:49:20.03#ibcon#about to read 4, iclass 32, count 2 2006.168.07:49:20.03#ibcon#read 4, iclass 32, count 2 2006.168.07:49:20.03#ibcon#about to read 5, iclass 32, count 2 2006.168.07:49:20.03#ibcon#read 5, iclass 32, count 2 2006.168.07:49:20.03#ibcon#about to read 6, iclass 32, count 2 2006.168.07:49:20.03#ibcon#read 6, iclass 32, count 2 2006.168.07:49:20.03#ibcon#end of sib2, iclass 32, count 2 2006.168.07:49:20.03#ibcon#*mode == 0, iclass 32, count 2 2006.168.07:49:20.03#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.168.07:49:20.03#ibcon#[25=AT07-06\r\n] 2006.168.07:49:20.03#ibcon#*before write, iclass 32, count 2 2006.168.07:49:20.03#ibcon#enter sib2, iclass 32, count 2 2006.168.07:49:20.03#ibcon#flushed, iclass 32, count 2 2006.168.07:49:20.03#ibcon#about to write, iclass 32, count 2 2006.168.07:49:20.03#ibcon#wrote, iclass 32, count 2 2006.168.07:49:20.03#ibcon#about to read 3, iclass 32, count 2 2006.168.07:49:20.06#ibcon#read 3, iclass 32, count 2 2006.168.07:49:20.06#ibcon#about to read 4, iclass 32, count 2 2006.168.07:49:20.06#ibcon#read 4, iclass 32, count 2 2006.168.07:49:20.06#ibcon#about to read 5, iclass 32, count 2 2006.168.07:49:20.06#ibcon#read 5, iclass 32, count 2 2006.168.07:49:20.06#ibcon#about to read 6, iclass 32, count 2 2006.168.07:49:20.06#ibcon#read 6, iclass 32, count 2 2006.168.07:49:20.06#ibcon#end of sib2, iclass 32, count 2 2006.168.07:49:20.06#ibcon#*after write, iclass 32, count 2 2006.168.07:49:20.06#ibcon#*before return 0, iclass 32, count 2 2006.168.07:49:20.06#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:49:20.06#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:49:20.06#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.168.07:49:20.06#ibcon#ireg 7 cls_cnt 0 2006.168.07:49:20.06#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:49:20.18#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:49:20.18#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:49:20.18#ibcon#enter wrdev, iclass 32, count 0 2006.168.07:49:20.18#ibcon#first serial, iclass 32, count 0 2006.168.07:49:20.18#ibcon#enter sib2, iclass 32, count 0 2006.168.07:49:20.18#ibcon#flushed, iclass 32, count 0 2006.168.07:49:20.18#ibcon#about to write, iclass 32, count 0 2006.168.07:49:20.18#ibcon#wrote, iclass 32, count 0 2006.168.07:49:20.18#ibcon#about to read 3, iclass 32, count 0 2006.168.07:49:20.20#ibcon#read 3, iclass 32, count 0 2006.168.07:49:20.20#ibcon#about to read 4, iclass 32, count 0 2006.168.07:49:20.20#ibcon#read 4, iclass 32, count 0 2006.168.07:49:20.20#ibcon#about to read 5, iclass 32, count 0 2006.168.07:49:20.20#ibcon#read 5, iclass 32, count 0 2006.168.07:49:20.20#ibcon#about to read 6, iclass 32, count 0 2006.168.07:49:20.20#ibcon#read 6, iclass 32, count 0 2006.168.07:49:20.20#ibcon#end of sib2, iclass 32, count 0 2006.168.07:49:20.20#ibcon#*mode == 0, iclass 32, count 0 2006.168.07:49:20.20#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.168.07:49:20.20#ibcon#[25=USB\r\n] 2006.168.07:49:20.20#ibcon#*before write, iclass 32, count 0 2006.168.07:49:20.20#ibcon#enter sib2, iclass 32, count 0 2006.168.07:49:20.20#ibcon#flushed, iclass 32, count 0 2006.168.07:49:20.20#ibcon#about to write, iclass 32, count 0 2006.168.07:49:20.20#ibcon#wrote, iclass 32, count 0 2006.168.07:49:20.20#ibcon#about to read 3, iclass 32, count 0 2006.168.07:49:20.24#ibcon#read 3, iclass 32, count 0 2006.168.07:49:20.24#ibcon#about to read 4, iclass 32, count 0 2006.168.07:49:20.24#ibcon#read 4, iclass 32, count 0 2006.168.07:49:20.24#ibcon#about to read 5, iclass 32, count 0 2006.168.07:49:20.24#ibcon#read 5, iclass 32, count 0 2006.168.07:49:20.24#ibcon#about to read 6, iclass 32, count 0 2006.168.07:49:20.24#ibcon#read 6, iclass 32, count 0 2006.168.07:49:20.24#ibcon#end of sib2, iclass 32, count 0 2006.168.07:49:20.24#ibcon#*after write, iclass 32, count 0 2006.168.07:49:20.24#ibcon#*before return 0, iclass 32, count 0 2006.168.07:49:20.24#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:49:20.24#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:49:20.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.168.07:49:20.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.168.07:49:20.24$vc4f8/valo=8,852.99 2006.168.07:49:20.24#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.168.07:49:20.24#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.168.07:49:20.24#ibcon#ireg 17 cls_cnt 0 2006.168.07:49:20.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:49:20.24#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:49:20.24#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:49:20.24#ibcon#enter wrdev, iclass 34, count 0 2006.168.07:49:20.24#ibcon#first serial, iclass 34, count 0 2006.168.07:49:20.24#ibcon#enter sib2, iclass 34, count 0 2006.168.07:49:20.24#ibcon#flushed, iclass 34, count 0 2006.168.07:49:20.24#ibcon#about to write, iclass 34, count 0 2006.168.07:49:20.24#ibcon#wrote, iclass 34, count 0 2006.168.07:49:20.24#ibcon#about to read 3, iclass 34, count 0 2006.168.07:49:20.25#ibcon#read 3, iclass 34, count 0 2006.168.07:49:20.25#ibcon#about to read 4, iclass 34, count 0 2006.168.07:49:20.25#ibcon#read 4, iclass 34, count 0 2006.168.07:49:20.25#ibcon#about to read 5, iclass 34, count 0 2006.168.07:49:20.25#ibcon#read 5, iclass 34, count 0 2006.168.07:49:20.25#ibcon#about to read 6, iclass 34, count 0 2006.168.07:49:20.25#ibcon#read 6, iclass 34, count 0 2006.168.07:49:20.25#ibcon#end of sib2, iclass 34, count 0 2006.168.07:49:20.25#ibcon#*mode == 0, iclass 34, count 0 2006.168.07:49:20.25#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.168.07:49:20.25#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.07:49:20.25#ibcon#*before write, iclass 34, count 0 2006.168.07:49:20.25#ibcon#enter sib2, iclass 34, count 0 2006.168.07:49:20.25#ibcon#flushed, iclass 34, count 0 2006.168.07:49:20.25#ibcon#about to write, iclass 34, count 0 2006.168.07:49:20.25#ibcon#wrote, iclass 34, count 0 2006.168.07:49:20.25#ibcon#about to read 3, iclass 34, count 0 2006.168.07:49:20.29#ibcon#read 3, iclass 34, count 0 2006.168.07:49:20.29#ibcon#about to read 4, iclass 34, count 0 2006.168.07:49:20.29#ibcon#read 4, iclass 34, count 0 2006.168.07:49:20.29#ibcon#about to read 5, iclass 34, count 0 2006.168.07:49:20.29#ibcon#read 5, iclass 34, count 0 2006.168.07:49:20.29#ibcon#about to read 6, iclass 34, count 0 2006.168.07:49:20.29#ibcon#read 6, iclass 34, count 0 2006.168.07:49:20.29#ibcon#end of sib2, iclass 34, count 0 2006.168.07:49:20.29#ibcon#*after write, iclass 34, count 0 2006.168.07:49:20.29#ibcon#*before return 0, iclass 34, count 0 2006.168.07:49:20.29#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:49:20.29#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:49:20.29#ibcon#about to clear, iclass 34 cls_cnt 0 2006.168.07:49:20.29#ibcon#cleared, iclass 34 cls_cnt 0 2006.168.07:49:20.29$vc4f8/va=8,7 2006.168.07:49:20.29#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.168.07:49:20.29#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.168.07:49:20.29#ibcon#ireg 11 cls_cnt 2 2006.168.07:49:20.29#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:49:20.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:49:20.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:49:20.36#ibcon#enter wrdev, iclass 36, count 2 2006.168.07:49:20.36#ibcon#first serial, iclass 36, count 2 2006.168.07:49:20.36#ibcon#enter sib2, iclass 36, count 2 2006.168.07:49:20.36#ibcon#flushed, iclass 36, count 2 2006.168.07:49:20.36#ibcon#about to write, iclass 36, count 2 2006.168.07:49:20.36#ibcon#wrote, iclass 36, count 2 2006.168.07:49:20.36#ibcon#about to read 3, iclass 36, count 2 2006.168.07:49:20.38#ibcon#read 3, iclass 36, count 2 2006.168.07:49:20.38#ibcon#about to read 4, iclass 36, count 2 2006.168.07:49:20.38#ibcon#read 4, iclass 36, count 2 2006.168.07:49:20.38#ibcon#about to read 5, iclass 36, count 2 2006.168.07:49:20.38#ibcon#read 5, iclass 36, count 2 2006.168.07:49:20.38#ibcon#about to read 6, iclass 36, count 2 2006.168.07:49:20.38#ibcon#read 6, iclass 36, count 2 2006.168.07:49:20.38#ibcon#end of sib2, iclass 36, count 2 2006.168.07:49:20.38#ibcon#*mode == 0, iclass 36, count 2 2006.168.07:49:20.38#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.168.07:49:20.38#ibcon#[25=AT08-07\r\n] 2006.168.07:49:20.38#ibcon#*before write, iclass 36, count 2 2006.168.07:49:20.38#ibcon#enter sib2, iclass 36, count 2 2006.168.07:49:20.38#ibcon#flushed, iclass 36, count 2 2006.168.07:49:20.38#ibcon#about to write, iclass 36, count 2 2006.168.07:49:20.38#ibcon#wrote, iclass 36, count 2 2006.168.07:49:20.38#ibcon#about to read 3, iclass 36, count 2 2006.168.07:49:20.41#ibcon#read 3, iclass 36, count 2 2006.168.07:49:20.41#ibcon#about to read 4, iclass 36, count 2 2006.168.07:49:20.41#ibcon#read 4, iclass 36, count 2 2006.168.07:49:20.41#ibcon#about to read 5, iclass 36, count 2 2006.168.07:49:20.41#ibcon#read 5, iclass 36, count 2 2006.168.07:49:20.41#ibcon#about to read 6, iclass 36, count 2 2006.168.07:49:20.41#ibcon#read 6, iclass 36, count 2 2006.168.07:49:20.41#ibcon#end of sib2, iclass 36, count 2 2006.168.07:49:20.41#ibcon#*after write, iclass 36, count 2 2006.168.07:49:20.41#ibcon#*before return 0, iclass 36, count 2 2006.168.07:49:20.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:49:20.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:49:20.41#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.168.07:49:20.41#ibcon#ireg 7 cls_cnt 0 2006.168.07:49:20.41#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:49:20.53#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:49:20.53#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:49:20.53#ibcon#enter wrdev, iclass 36, count 0 2006.168.07:49:20.53#ibcon#first serial, iclass 36, count 0 2006.168.07:49:20.53#ibcon#enter sib2, iclass 36, count 0 2006.168.07:49:20.53#ibcon#flushed, iclass 36, count 0 2006.168.07:49:20.53#ibcon#about to write, iclass 36, count 0 2006.168.07:49:20.53#ibcon#wrote, iclass 36, count 0 2006.168.07:49:20.53#ibcon#about to read 3, iclass 36, count 0 2006.168.07:49:20.55#ibcon#read 3, iclass 36, count 0 2006.168.07:49:20.55#ibcon#about to read 4, iclass 36, count 0 2006.168.07:49:20.55#ibcon#read 4, iclass 36, count 0 2006.168.07:49:20.55#ibcon#about to read 5, iclass 36, count 0 2006.168.07:49:20.55#ibcon#read 5, iclass 36, count 0 2006.168.07:49:20.55#ibcon#about to read 6, iclass 36, count 0 2006.168.07:49:20.55#ibcon#read 6, iclass 36, count 0 2006.168.07:49:20.55#ibcon#end of sib2, iclass 36, count 0 2006.168.07:49:20.55#ibcon#*mode == 0, iclass 36, count 0 2006.168.07:49:20.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.168.07:49:20.55#ibcon#[25=USB\r\n] 2006.168.07:49:20.55#ibcon#*before write, iclass 36, count 0 2006.168.07:49:20.55#ibcon#enter sib2, iclass 36, count 0 2006.168.07:49:20.55#ibcon#flushed, iclass 36, count 0 2006.168.07:49:20.55#ibcon#about to write, iclass 36, count 0 2006.168.07:49:20.55#ibcon#wrote, iclass 36, count 0 2006.168.07:49:20.55#ibcon#about to read 3, iclass 36, count 0 2006.168.07:49:20.58#ibcon#read 3, iclass 36, count 0 2006.168.07:49:20.58#ibcon#about to read 4, iclass 36, count 0 2006.168.07:49:20.58#ibcon#read 4, iclass 36, count 0 2006.168.07:49:20.58#ibcon#about to read 5, iclass 36, count 0 2006.168.07:49:20.58#ibcon#read 5, iclass 36, count 0 2006.168.07:49:20.58#ibcon#about to read 6, iclass 36, count 0 2006.168.07:49:20.58#ibcon#read 6, iclass 36, count 0 2006.168.07:49:20.58#ibcon#end of sib2, iclass 36, count 0 2006.168.07:49:20.58#ibcon#*after write, iclass 36, count 0 2006.168.07:49:20.58#ibcon#*before return 0, iclass 36, count 0 2006.168.07:49:20.58#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:49:20.58#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:49:20.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.168.07:49:20.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.168.07:49:20.58$vc4f8/vblo=1,632.99 2006.168.07:49:20.58#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.168.07:49:20.58#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.168.07:49:20.58#ibcon#ireg 17 cls_cnt 0 2006.168.07:49:20.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:49:20.58#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:49:20.58#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:49:20.58#ibcon#enter wrdev, iclass 38, count 0 2006.168.07:49:20.58#ibcon#first serial, iclass 38, count 0 2006.168.07:49:20.58#ibcon#enter sib2, iclass 38, count 0 2006.168.07:49:20.58#ibcon#flushed, iclass 38, count 0 2006.168.07:49:20.58#ibcon#about to write, iclass 38, count 0 2006.168.07:49:20.58#ibcon#wrote, iclass 38, count 0 2006.168.07:49:20.58#ibcon#about to read 3, iclass 38, count 0 2006.168.07:49:20.60#ibcon#read 3, iclass 38, count 0 2006.168.07:49:20.60#ibcon#about to read 4, iclass 38, count 0 2006.168.07:49:20.60#ibcon#read 4, iclass 38, count 0 2006.168.07:49:20.60#ibcon#about to read 5, iclass 38, count 0 2006.168.07:49:20.60#ibcon#read 5, iclass 38, count 0 2006.168.07:49:20.60#ibcon#about to read 6, iclass 38, count 0 2006.168.07:49:20.60#ibcon#read 6, iclass 38, count 0 2006.168.07:49:20.60#ibcon#end of sib2, iclass 38, count 0 2006.168.07:49:20.60#ibcon#*mode == 0, iclass 38, count 0 2006.168.07:49:20.60#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.168.07:49:20.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.07:49:20.60#ibcon#*before write, iclass 38, count 0 2006.168.07:49:20.60#ibcon#enter sib2, iclass 38, count 0 2006.168.07:49:20.60#ibcon#flushed, iclass 38, count 0 2006.168.07:49:20.60#ibcon#about to write, iclass 38, count 0 2006.168.07:49:20.60#ibcon#wrote, iclass 38, count 0 2006.168.07:49:20.60#ibcon#about to read 3, iclass 38, count 0 2006.168.07:49:20.64#ibcon#read 3, iclass 38, count 0 2006.168.07:49:20.64#ibcon#about to read 4, iclass 38, count 0 2006.168.07:49:20.64#ibcon#read 4, iclass 38, count 0 2006.168.07:49:20.64#ibcon#about to read 5, iclass 38, count 0 2006.168.07:49:20.64#ibcon#read 5, iclass 38, count 0 2006.168.07:49:20.64#ibcon#about to read 6, iclass 38, count 0 2006.168.07:49:20.64#ibcon#read 6, iclass 38, count 0 2006.168.07:49:20.64#ibcon#end of sib2, iclass 38, count 0 2006.168.07:49:20.64#ibcon#*after write, iclass 38, count 0 2006.168.07:49:20.64#ibcon#*before return 0, iclass 38, count 0 2006.168.07:49:20.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:49:20.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:49:20.64#ibcon#about to clear, iclass 38 cls_cnt 0 2006.168.07:49:20.64#ibcon#cleared, iclass 38 cls_cnt 0 2006.168.07:49:20.64$vc4f8/vb=1,4 2006.168.07:49:20.64#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.168.07:49:20.64#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.168.07:49:20.64#ibcon#ireg 11 cls_cnt 2 2006.168.07:49:20.64#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:49:20.64#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:49:20.64#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:49:20.64#ibcon#enter wrdev, iclass 40, count 2 2006.168.07:49:20.64#ibcon#first serial, iclass 40, count 2 2006.168.07:49:20.64#ibcon#enter sib2, iclass 40, count 2 2006.168.07:49:20.64#ibcon#flushed, iclass 40, count 2 2006.168.07:49:20.64#ibcon#about to write, iclass 40, count 2 2006.168.07:49:20.64#ibcon#wrote, iclass 40, count 2 2006.168.07:49:20.64#ibcon#about to read 3, iclass 40, count 2 2006.168.07:49:20.66#ibcon#read 3, iclass 40, count 2 2006.168.07:49:20.66#ibcon#about to read 4, iclass 40, count 2 2006.168.07:49:20.66#ibcon#read 4, iclass 40, count 2 2006.168.07:49:20.66#ibcon#about to read 5, iclass 40, count 2 2006.168.07:49:20.66#ibcon#read 5, iclass 40, count 2 2006.168.07:49:20.66#ibcon#about to read 6, iclass 40, count 2 2006.168.07:49:20.66#ibcon#read 6, iclass 40, count 2 2006.168.07:49:20.66#ibcon#end of sib2, iclass 40, count 2 2006.168.07:49:20.66#ibcon#*mode == 0, iclass 40, count 2 2006.168.07:49:20.66#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.168.07:49:20.66#ibcon#[27=AT01-04\r\n] 2006.168.07:49:20.66#ibcon#*before write, iclass 40, count 2 2006.168.07:49:20.66#ibcon#enter sib2, iclass 40, count 2 2006.168.07:49:20.66#ibcon#flushed, iclass 40, count 2 2006.168.07:49:20.66#ibcon#about to write, iclass 40, count 2 2006.168.07:49:20.66#ibcon#wrote, iclass 40, count 2 2006.168.07:49:20.66#ibcon#about to read 3, iclass 40, count 2 2006.168.07:49:20.69#ibcon#read 3, iclass 40, count 2 2006.168.07:49:20.69#ibcon#about to read 4, iclass 40, count 2 2006.168.07:49:20.69#ibcon#read 4, iclass 40, count 2 2006.168.07:49:20.69#ibcon#about to read 5, iclass 40, count 2 2006.168.07:49:20.69#ibcon#read 5, iclass 40, count 2 2006.168.07:49:20.69#ibcon#about to read 6, iclass 40, count 2 2006.168.07:49:20.69#ibcon#read 6, iclass 40, count 2 2006.168.07:49:20.69#ibcon#end of sib2, iclass 40, count 2 2006.168.07:49:20.69#ibcon#*after write, iclass 40, count 2 2006.168.07:49:20.69#ibcon#*before return 0, iclass 40, count 2 2006.168.07:49:20.69#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:49:20.69#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.168.07:49:20.69#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.168.07:49:20.69#ibcon#ireg 7 cls_cnt 0 2006.168.07:49:20.69#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:49:20.81#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:49:20.81#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:49:20.81#ibcon#enter wrdev, iclass 40, count 0 2006.168.07:49:20.81#ibcon#first serial, iclass 40, count 0 2006.168.07:49:20.81#ibcon#enter sib2, iclass 40, count 0 2006.168.07:49:20.81#ibcon#flushed, iclass 40, count 0 2006.168.07:49:20.81#ibcon#about to write, iclass 40, count 0 2006.168.07:49:20.81#ibcon#wrote, iclass 40, count 0 2006.168.07:49:20.81#ibcon#about to read 3, iclass 40, count 0 2006.168.07:49:20.83#ibcon#read 3, iclass 40, count 0 2006.168.07:49:20.83#ibcon#about to read 4, iclass 40, count 0 2006.168.07:49:20.83#ibcon#read 4, iclass 40, count 0 2006.168.07:49:20.83#ibcon#about to read 5, iclass 40, count 0 2006.168.07:49:20.83#ibcon#read 5, iclass 40, count 0 2006.168.07:49:20.83#ibcon#about to read 6, iclass 40, count 0 2006.168.07:49:20.83#ibcon#read 6, iclass 40, count 0 2006.168.07:49:20.83#ibcon#end of sib2, iclass 40, count 0 2006.168.07:49:20.83#ibcon#*mode == 0, iclass 40, count 0 2006.168.07:49:20.83#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.168.07:49:20.83#ibcon#[27=USB\r\n] 2006.168.07:49:20.83#ibcon#*before write, iclass 40, count 0 2006.168.07:49:20.83#ibcon#enter sib2, iclass 40, count 0 2006.168.07:49:20.83#ibcon#flushed, iclass 40, count 0 2006.168.07:49:20.83#ibcon#about to write, iclass 40, count 0 2006.168.07:49:20.83#ibcon#wrote, iclass 40, count 0 2006.168.07:49:20.83#ibcon#about to read 3, iclass 40, count 0 2006.168.07:49:20.86#ibcon#read 3, iclass 40, count 0 2006.168.07:49:20.86#ibcon#about to read 4, iclass 40, count 0 2006.168.07:49:20.86#ibcon#read 4, iclass 40, count 0 2006.168.07:49:20.86#ibcon#about to read 5, iclass 40, count 0 2006.168.07:49:20.86#ibcon#read 5, iclass 40, count 0 2006.168.07:49:20.86#ibcon#about to read 6, iclass 40, count 0 2006.168.07:49:20.86#ibcon#read 6, iclass 40, count 0 2006.168.07:49:20.86#ibcon#end of sib2, iclass 40, count 0 2006.168.07:49:20.86#ibcon#*after write, iclass 40, count 0 2006.168.07:49:20.86#ibcon#*before return 0, iclass 40, count 0 2006.168.07:49:20.86#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:49:20.86#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.168.07:49:20.86#ibcon#about to clear, iclass 40 cls_cnt 0 2006.168.07:49:20.86#ibcon#cleared, iclass 40 cls_cnt 0 2006.168.07:49:20.86$vc4f8/vblo=2,640.99 2006.168.07:49:20.86#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.168.07:49:20.86#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.168.07:49:20.86#ibcon#ireg 17 cls_cnt 0 2006.168.07:49:20.86#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:49:20.86#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:49:20.86#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:49:20.86#ibcon#enter wrdev, iclass 4, count 0 2006.168.07:49:20.86#ibcon#first serial, iclass 4, count 0 2006.168.07:49:20.86#ibcon#enter sib2, iclass 4, count 0 2006.168.07:49:20.86#ibcon#flushed, iclass 4, count 0 2006.168.07:49:20.86#ibcon#about to write, iclass 4, count 0 2006.168.07:49:20.86#ibcon#wrote, iclass 4, count 0 2006.168.07:49:20.86#ibcon#about to read 3, iclass 4, count 0 2006.168.07:49:20.88#ibcon#read 3, iclass 4, count 0 2006.168.07:49:20.88#ibcon#about to read 4, iclass 4, count 0 2006.168.07:49:20.88#ibcon#read 4, iclass 4, count 0 2006.168.07:49:20.88#ibcon#about to read 5, iclass 4, count 0 2006.168.07:49:20.88#ibcon#read 5, iclass 4, count 0 2006.168.07:49:20.88#ibcon#about to read 6, iclass 4, count 0 2006.168.07:49:20.88#ibcon#read 6, iclass 4, count 0 2006.168.07:49:20.88#ibcon#end of sib2, iclass 4, count 0 2006.168.07:49:20.88#ibcon#*mode == 0, iclass 4, count 0 2006.168.07:49:20.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.168.07:49:20.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.07:49:20.88#ibcon#*before write, iclass 4, count 0 2006.168.07:49:20.88#ibcon#enter sib2, iclass 4, count 0 2006.168.07:49:20.88#ibcon#flushed, iclass 4, count 0 2006.168.07:49:20.88#ibcon#about to write, iclass 4, count 0 2006.168.07:49:20.88#ibcon#wrote, iclass 4, count 0 2006.168.07:49:20.88#ibcon#about to read 3, iclass 4, count 0 2006.168.07:49:20.92#ibcon#read 3, iclass 4, count 0 2006.168.07:49:20.92#ibcon#about to read 4, iclass 4, count 0 2006.168.07:49:20.92#ibcon#read 4, iclass 4, count 0 2006.168.07:49:20.92#ibcon#about to read 5, iclass 4, count 0 2006.168.07:49:20.92#ibcon#read 5, iclass 4, count 0 2006.168.07:49:20.92#ibcon#about to read 6, iclass 4, count 0 2006.168.07:49:20.92#ibcon#read 6, iclass 4, count 0 2006.168.07:49:20.92#ibcon#end of sib2, iclass 4, count 0 2006.168.07:49:20.92#ibcon#*after write, iclass 4, count 0 2006.168.07:49:20.92#ibcon#*before return 0, iclass 4, count 0 2006.168.07:49:20.92#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:49:20.92#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.168.07:49:20.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.168.07:49:20.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.168.07:49:20.92$vc4f8/vb=2,4 2006.168.07:49:20.92#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.168.07:49:20.92#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.168.07:49:20.92#ibcon#ireg 11 cls_cnt 2 2006.168.07:49:20.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:49:20.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:49:20.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:49:20.98#ibcon#enter wrdev, iclass 6, count 2 2006.168.07:49:20.98#ibcon#first serial, iclass 6, count 2 2006.168.07:49:20.98#ibcon#enter sib2, iclass 6, count 2 2006.168.07:49:20.98#ibcon#flushed, iclass 6, count 2 2006.168.07:49:20.98#ibcon#about to write, iclass 6, count 2 2006.168.07:49:20.98#ibcon#wrote, iclass 6, count 2 2006.168.07:49:20.98#ibcon#about to read 3, iclass 6, count 2 2006.168.07:49:21.00#ibcon#read 3, iclass 6, count 2 2006.168.07:49:21.00#ibcon#about to read 4, iclass 6, count 2 2006.168.07:49:21.00#ibcon#read 4, iclass 6, count 2 2006.168.07:49:21.00#ibcon#about to read 5, iclass 6, count 2 2006.168.07:49:21.00#ibcon#read 5, iclass 6, count 2 2006.168.07:49:21.00#ibcon#about to read 6, iclass 6, count 2 2006.168.07:49:21.00#ibcon#read 6, iclass 6, count 2 2006.168.07:49:21.00#ibcon#end of sib2, iclass 6, count 2 2006.168.07:49:21.00#ibcon#*mode == 0, iclass 6, count 2 2006.168.07:49:21.00#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.168.07:49:21.00#ibcon#[27=AT02-04\r\n] 2006.168.07:49:21.00#ibcon#*before write, iclass 6, count 2 2006.168.07:49:21.00#ibcon#enter sib2, iclass 6, count 2 2006.168.07:49:21.00#ibcon#flushed, iclass 6, count 2 2006.168.07:49:21.00#ibcon#about to write, iclass 6, count 2 2006.168.07:49:21.00#ibcon#wrote, iclass 6, count 2 2006.168.07:49:21.00#ibcon#about to read 3, iclass 6, count 2 2006.168.07:49:21.03#ibcon#read 3, iclass 6, count 2 2006.168.07:49:21.03#ibcon#about to read 4, iclass 6, count 2 2006.168.07:49:21.03#ibcon#read 4, iclass 6, count 2 2006.168.07:49:21.03#ibcon#about to read 5, iclass 6, count 2 2006.168.07:49:21.03#ibcon#read 5, iclass 6, count 2 2006.168.07:49:21.03#ibcon#about to read 6, iclass 6, count 2 2006.168.07:49:21.03#ibcon#read 6, iclass 6, count 2 2006.168.07:49:21.03#ibcon#end of sib2, iclass 6, count 2 2006.168.07:49:21.03#ibcon#*after write, iclass 6, count 2 2006.168.07:49:21.03#ibcon#*before return 0, iclass 6, count 2 2006.168.07:49:21.03#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:49:21.03#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:49:21.03#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.168.07:49:21.03#ibcon#ireg 7 cls_cnt 0 2006.168.07:49:21.03#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:49:21.15#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:49:21.15#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:49:21.15#ibcon#enter wrdev, iclass 6, count 0 2006.168.07:49:21.15#ibcon#first serial, iclass 6, count 0 2006.168.07:49:21.15#ibcon#enter sib2, iclass 6, count 0 2006.168.07:49:21.15#ibcon#flushed, iclass 6, count 0 2006.168.07:49:21.15#ibcon#about to write, iclass 6, count 0 2006.168.07:49:21.15#ibcon#wrote, iclass 6, count 0 2006.168.07:49:21.15#ibcon#about to read 3, iclass 6, count 0 2006.168.07:49:21.17#ibcon#read 3, iclass 6, count 0 2006.168.07:49:21.17#ibcon#about to read 4, iclass 6, count 0 2006.168.07:49:21.17#ibcon#read 4, iclass 6, count 0 2006.168.07:49:21.17#ibcon#about to read 5, iclass 6, count 0 2006.168.07:49:21.17#ibcon#read 5, iclass 6, count 0 2006.168.07:49:21.17#ibcon#about to read 6, iclass 6, count 0 2006.168.07:49:21.17#ibcon#read 6, iclass 6, count 0 2006.168.07:49:21.17#ibcon#end of sib2, iclass 6, count 0 2006.168.07:49:21.17#ibcon#*mode == 0, iclass 6, count 0 2006.168.07:49:21.17#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.168.07:49:21.17#ibcon#[27=USB\r\n] 2006.168.07:49:21.17#ibcon#*before write, iclass 6, count 0 2006.168.07:49:21.17#ibcon#enter sib2, iclass 6, count 0 2006.168.07:49:21.17#ibcon#flushed, iclass 6, count 0 2006.168.07:49:21.17#ibcon#about to write, iclass 6, count 0 2006.168.07:49:21.17#ibcon#wrote, iclass 6, count 0 2006.168.07:49:21.17#ibcon#about to read 3, iclass 6, count 0 2006.168.07:49:21.20#ibcon#read 3, iclass 6, count 0 2006.168.07:49:21.20#ibcon#about to read 4, iclass 6, count 0 2006.168.07:49:21.20#ibcon#read 4, iclass 6, count 0 2006.168.07:49:21.20#ibcon#about to read 5, iclass 6, count 0 2006.168.07:49:21.20#ibcon#read 5, iclass 6, count 0 2006.168.07:49:21.20#ibcon#about to read 6, iclass 6, count 0 2006.168.07:49:21.20#ibcon#read 6, iclass 6, count 0 2006.168.07:49:21.20#ibcon#end of sib2, iclass 6, count 0 2006.168.07:49:21.20#ibcon#*after write, iclass 6, count 0 2006.168.07:49:21.20#ibcon#*before return 0, iclass 6, count 0 2006.168.07:49:21.20#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:49:21.20#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:49:21.20#ibcon#about to clear, iclass 6 cls_cnt 0 2006.168.07:49:21.20#ibcon#cleared, iclass 6 cls_cnt 0 2006.168.07:49:21.20$vc4f8/vblo=3,656.99 2006.168.07:49:21.20#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.168.07:49:21.20#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.168.07:49:21.20#ibcon#ireg 17 cls_cnt 0 2006.168.07:49:21.20#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:49:21.20#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:49:21.20#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:49:21.20#ibcon#enter wrdev, iclass 10, count 0 2006.168.07:49:21.20#ibcon#first serial, iclass 10, count 0 2006.168.07:49:21.20#ibcon#enter sib2, iclass 10, count 0 2006.168.07:49:21.20#ibcon#flushed, iclass 10, count 0 2006.168.07:49:21.20#ibcon#about to write, iclass 10, count 0 2006.168.07:49:21.20#ibcon#wrote, iclass 10, count 0 2006.168.07:49:21.20#ibcon#about to read 3, iclass 10, count 0 2006.168.07:49:21.22#ibcon#read 3, iclass 10, count 0 2006.168.07:49:21.22#ibcon#about to read 4, iclass 10, count 0 2006.168.07:49:21.22#ibcon#read 4, iclass 10, count 0 2006.168.07:49:21.22#ibcon#about to read 5, iclass 10, count 0 2006.168.07:49:21.22#ibcon#read 5, iclass 10, count 0 2006.168.07:49:21.22#ibcon#about to read 6, iclass 10, count 0 2006.168.07:49:21.22#ibcon#read 6, iclass 10, count 0 2006.168.07:49:21.22#ibcon#end of sib2, iclass 10, count 0 2006.168.07:49:21.22#ibcon#*mode == 0, iclass 10, count 0 2006.168.07:49:21.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.168.07:49:21.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.07:49:21.22#ibcon#*before write, iclass 10, count 0 2006.168.07:49:21.22#ibcon#enter sib2, iclass 10, count 0 2006.168.07:49:21.22#ibcon#flushed, iclass 10, count 0 2006.168.07:49:21.22#ibcon#about to write, iclass 10, count 0 2006.168.07:49:21.22#ibcon#wrote, iclass 10, count 0 2006.168.07:49:21.22#ibcon#about to read 3, iclass 10, count 0 2006.168.07:49:21.26#ibcon#read 3, iclass 10, count 0 2006.168.07:49:21.26#ibcon#about to read 4, iclass 10, count 0 2006.168.07:49:21.26#ibcon#read 4, iclass 10, count 0 2006.168.07:49:21.26#ibcon#about to read 5, iclass 10, count 0 2006.168.07:49:21.26#ibcon#read 5, iclass 10, count 0 2006.168.07:49:21.26#ibcon#about to read 6, iclass 10, count 0 2006.168.07:49:21.26#ibcon#read 6, iclass 10, count 0 2006.168.07:49:21.26#ibcon#end of sib2, iclass 10, count 0 2006.168.07:49:21.26#ibcon#*after write, iclass 10, count 0 2006.168.07:49:21.26#ibcon#*before return 0, iclass 10, count 0 2006.168.07:49:21.26#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:49:21.26#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:49:21.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.168.07:49:21.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.168.07:49:21.26$vc4f8/vb=3,4 2006.168.07:49:21.26#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.168.07:49:21.26#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.168.07:49:21.26#ibcon#ireg 11 cls_cnt 2 2006.168.07:49:21.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:49:21.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:49:21.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:49:21.32#ibcon#enter wrdev, iclass 12, count 2 2006.168.07:49:21.32#ibcon#first serial, iclass 12, count 2 2006.168.07:49:21.32#ibcon#enter sib2, iclass 12, count 2 2006.168.07:49:21.32#ibcon#flushed, iclass 12, count 2 2006.168.07:49:21.32#ibcon#about to write, iclass 12, count 2 2006.168.07:49:21.32#ibcon#wrote, iclass 12, count 2 2006.168.07:49:21.32#ibcon#about to read 3, iclass 12, count 2 2006.168.07:49:21.34#ibcon#read 3, iclass 12, count 2 2006.168.07:49:21.34#ibcon#about to read 4, iclass 12, count 2 2006.168.07:49:21.34#ibcon#read 4, iclass 12, count 2 2006.168.07:49:21.34#ibcon#about to read 5, iclass 12, count 2 2006.168.07:49:21.34#ibcon#read 5, iclass 12, count 2 2006.168.07:49:21.34#ibcon#about to read 6, iclass 12, count 2 2006.168.07:49:21.34#ibcon#read 6, iclass 12, count 2 2006.168.07:49:21.34#ibcon#end of sib2, iclass 12, count 2 2006.168.07:49:21.34#ibcon#*mode == 0, iclass 12, count 2 2006.168.07:49:21.34#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.168.07:49:21.34#ibcon#[27=AT03-04\r\n] 2006.168.07:49:21.34#ibcon#*before write, iclass 12, count 2 2006.168.07:49:21.34#ibcon#enter sib2, iclass 12, count 2 2006.168.07:49:21.34#ibcon#flushed, iclass 12, count 2 2006.168.07:49:21.34#ibcon#about to write, iclass 12, count 2 2006.168.07:49:21.34#ibcon#wrote, iclass 12, count 2 2006.168.07:49:21.34#ibcon#about to read 3, iclass 12, count 2 2006.168.07:49:21.37#ibcon#read 3, iclass 12, count 2 2006.168.07:49:21.37#ibcon#about to read 4, iclass 12, count 2 2006.168.07:49:21.37#ibcon#read 4, iclass 12, count 2 2006.168.07:49:21.37#ibcon#about to read 5, iclass 12, count 2 2006.168.07:49:21.37#ibcon#read 5, iclass 12, count 2 2006.168.07:49:21.37#ibcon#about to read 6, iclass 12, count 2 2006.168.07:49:21.37#ibcon#read 6, iclass 12, count 2 2006.168.07:49:21.37#ibcon#end of sib2, iclass 12, count 2 2006.168.07:49:21.37#ibcon#*after write, iclass 12, count 2 2006.168.07:49:21.37#ibcon#*before return 0, iclass 12, count 2 2006.168.07:49:21.37#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:49:21.37#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:49:21.37#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.168.07:49:21.37#ibcon#ireg 7 cls_cnt 0 2006.168.07:49:21.37#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:49:21.49#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:49:21.49#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:49:21.49#ibcon#enter wrdev, iclass 12, count 0 2006.168.07:49:21.49#ibcon#first serial, iclass 12, count 0 2006.168.07:49:21.49#ibcon#enter sib2, iclass 12, count 0 2006.168.07:49:21.49#ibcon#flushed, iclass 12, count 0 2006.168.07:49:21.49#ibcon#about to write, iclass 12, count 0 2006.168.07:49:21.49#ibcon#wrote, iclass 12, count 0 2006.168.07:49:21.49#ibcon#about to read 3, iclass 12, count 0 2006.168.07:49:21.51#ibcon#read 3, iclass 12, count 0 2006.168.07:49:21.51#ibcon#about to read 4, iclass 12, count 0 2006.168.07:49:21.51#ibcon#read 4, iclass 12, count 0 2006.168.07:49:21.51#ibcon#about to read 5, iclass 12, count 0 2006.168.07:49:21.51#ibcon#read 5, iclass 12, count 0 2006.168.07:49:21.51#ibcon#about to read 6, iclass 12, count 0 2006.168.07:49:21.51#ibcon#read 6, iclass 12, count 0 2006.168.07:49:21.51#ibcon#end of sib2, iclass 12, count 0 2006.168.07:49:21.51#ibcon#*mode == 0, iclass 12, count 0 2006.168.07:49:21.51#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.168.07:49:21.51#ibcon#[27=USB\r\n] 2006.168.07:49:21.51#ibcon#*before write, iclass 12, count 0 2006.168.07:49:21.51#ibcon#enter sib2, iclass 12, count 0 2006.168.07:49:21.51#ibcon#flushed, iclass 12, count 0 2006.168.07:49:21.51#ibcon#about to write, iclass 12, count 0 2006.168.07:49:21.51#ibcon#wrote, iclass 12, count 0 2006.168.07:49:21.51#ibcon#about to read 3, iclass 12, count 0 2006.168.07:49:21.54#ibcon#read 3, iclass 12, count 0 2006.168.07:49:21.54#ibcon#about to read 4, iclass 12, count 0 2006.168.07:49:21.54#ibcon#read 4, iclass 12, count 0 2006.168.07:49:21.54#ibcon#about to read 5, iclass 12, count 0 2006.168.07:49:21.54#ibcon#read 5, iclass 12, count 0 2006.168.07:49:21.54#ibcon#about to read 6, iclass 12, count 0 2006.168.07:49:21.54#ibcon#read 6, iclass 12, count 0 2006.168.07:49:21.54#ibcon#end of sib2, iclass 12, count 0 2006.168.07:49:21.54#ibcon#*after write, iclass 12, count 0 2006.168.07:49:21.54#ibcon#*before return 0, iclass 12, count 0 2006.168.07:49:21.54#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:49:21.54#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:49:21.54#ibcon#about to clear, iclass 12 cls_cnt 0 2006.168.07:49:21.54#ibcon#cleared, iclass 12 cls_cnt 0 2006.168.07:49:21.54$vc4f8/vblo=4,712.99 2006.168.07:49:21.54#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.168.07:49:21.54#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.168.07:49:21.54#ibcon#ireg 17 cls_cnt 0 2006.168.07:49:21.54#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:49:21.54#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:49:21.54#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:49:21.54#ibcon#enter wrdev, iclass 14, count 0 2006.168.07:49:21.54#ibcon#first serial, iclass 14, count 0 2006.168.07:49:21.54#ibcon#enter sib2, iclass 14, count 0 2006.168.07:49:21.54#ibcon#flushed, iclass 14, count 0 2006.168.07:49:21.54#ibcon#about to write, iclass 14, count 0 2006.168.07:49:21.54#ibcon#wrote, iclass 14, count 0 2006.168.07:49:21.54#ibcon#about to read 3, iclass 14, count 0 2006.168.07:49:21.56#ibcon#read 3, iclass 14, count 0 2006.168.07:49:21.56#ibcon#about to read 4, iclass 14, count 0 2006.168.07:49:21.56#ibcon#read 4, iclass 14, count 0 2006.168.07:49:21.56#ibcon#about to read 5, iclass 14, count 0 2006.168.07:49:21.56#ibcon#read 5, iclass 14, count 0 2006.168.07:49:21.56#ibcon#about to read 6, iclass 14, count 0 2006.168.07:49:21.56#ibcon#read 6, iclass 14, count 0 2006.168.07:49:21.56#ibcon#end of sib2, iclass 14, count 0 2006.168.07:49:21.56#ibcon#*mode == 0, iclass 14, count 0 2006.168.07:49:21.56#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.168.07:49:21.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.07:49:21.56#ibcon#*before write, iclass 14, count 0 2006.168.07:49:21.56#ibcon#enter sib2, iclass 14, count 0 2006.168.07:49:21.56#ibcon#flushed, iclass 14, count 0 2006.168.07:49:21.56#ibcon#about to write, iclass 14, count 0 2006.168.07:49:21.56#ibcon#wrote, iclass 14, count 0 2006.168.07:49:21.56#ibcon#about to read 3, iclass 14, count 0 2006.168.07:49:21.60#ibcon#read 3, iclass 14, count 0 2006.168.07:49:21.60#ibcon#about to read 4, iclass 14, count 0 2006.168.07:49:21.60#ibcon#read 4, iclass 14, count 0 2006.168.07:49:21.60#ibcon#about to read 5, iclass 14, count 0 2006.168.07:49:21.60#ibcon#read 5, iclass 14, count 0 2006.168.07:49:21.60#ibcon#about to read 6, iclass 14, count 0 2006.168.07:49:21.60#ibcon#read 6, iclass 14, count 0 2006.168.07:49:21.60#ibcon#end of sib2, iclass 14, count 0 2006.168.07:49:21.60#ibcon#*after write, iclass 14, count 0 2006.168.07:49:21.60#ibcon#*before return 0, iclass 14, count 0 2006.168.07:49:21.60#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:49:21.60#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:49:21.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.168.07:49:21.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.168.07:49:21.60$vc4f8/vb=4,4 2006.168.07:49:21.60#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.168.07:49:21.60#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.168.07:49:21.60#ibcon#ireg 11 cls_cnt 2 2006.168.07:49:21.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:49:21.66#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:49:21.66#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:49:21.66#ibcon#enter wrdev, iclass 16, count 2 2006.168.07:49:21.66#ibcon#first serial, iclass 16, count 2 2006.168.07:49:21.66#ibcon#enter sib2, iclass 16, count 2 2006.168.07:49:21.66#ibcon#flushed, iclass 16, count 2 2006.168.07:49:21.66#ibcon#about to write, iclass 16, count 2 2006.168.07:49:21.66#ibcon#wrote, iclass 16, count 2 2006.168.07:49:21.66#ibcon#about to read 3, iclass 16, count 2 2006.168.07:49:21.68#ibcon#read 3, iclass 16, count 2 2006.168.07:49:21.68#ibcon#about to read 4, iclass 16, count 2 2006.168.07:49:21.68#ibcon#read 4, iclass 16, count 2 2006.168.07:49:21.68#ibcon#about to read 5, iclass 16, count 2 2006.168.07:49:21.68#ibcon#read 5, iclass 16, count 2 2006.168.07:49:21.68#ibcon#about to read 6, iclass 16, count 2 2006.168.07:49:21.68#ibcon#read 6, iclass 16, count 2 2006.168.07:49:21.68#ibcon#end of sib2, iclass 16, count 2 2006.168.07:49:21.68#ibcon#*mode == 0, iclass 16, count 2 2006.168.07:49:21.68#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.168.07:49:21.68#ibcon#[27=AT04-04\r\n] 2006.168.07:49:21.68#ibcon#*before write, iclass 16, count 2 2006.168.07:49:21.68#ibcon#enter sib2, iclass 16, count 2 2006.168.07:49:21.68#ibcon#flushed, iclass 16, count 2 2006.168.07:49:21.68#ibcon#about to write, iclass 16, count 2 2006.168.07:49:21.68#ibcon#wrote, iclass 16, count 2 2006.168.07:49:21.68#ibcon#about to read 3, iclass 16, count 2 2006.168.07:49:21.71#ibcon#read 3, iclass 16, count 2 2006.168.07:49:21.71#ibcon#about to read 4, iclass 16, count 2 2006.168.07:49:21.71#ibcon#read 4, iclass 16, count 2 2006.168.07:49:21.71#ibcon#about to read 5, iclass 16, count 2 2006.168.07:49:21.71#ibcon#read 5, iclass 16, count 2 2006.168.07:49:21.71#ibcon#about to read 6, iclass 16, count 2 2006.168.07:49:21.71#ibcon#read 6, iclass 16, count 2 2006.168.07:49:21.71#ibcon#end of sib2, iclass 16, count 2 2006.168.07:49:21.71#ibcon#*after write, iclass 16, count 2 2006.168.07:49:21.71#ibcon#*before return 0, iclass 16, count 2 2006.168.07:49:21.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:49:21.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:49:21.71#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.168.07:49:21.71#ibcon#ireg 7 cls_cnt 0 2006.168.07:49:21.71#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:49:21.83#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:49:21.83#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:49:21.83#ibcon#enter wrdev, iclass 16, count 0 2006.168.07:49:21.83#ibcon#first serial, iclass 16, count 0 2006.168.07:49:21.83#ibcon#enter sib2, iclass 16, count 0 2006.168.07:49:21.83#ibcon#flushed, iclass 16, count 0 2006.168.07:49:21.83#ibcon#about to write, iclass 16, count 0 2006.168.07:49:21.83#ibcon#wrote, iclass 16, count 0 2006.168.07:49:21.83#ibcon#about to read 3, iclass 16, count 0 2006.168.07:49:21.85#ibcon#read 3, iclass 16, count 0 2006.168.07:49:21.85#ibcon#about to read 4, iclass 16, count 0 2006.168.07:49:21.85#ibcon#read 4, iclass 16, count 0 2006.168.07:49:21.85#ibcon#about to read 5, iclass 16, count 0 2006.168.07:49:21.85#ibcon#read 5, iclass 16, count 0 2006.168.07:49:21.85#ibcon#about to read 6, iclass 16, count 0 2006.168.07:49:21.85#ibcon#read 6, iclass 16, count 0 2006.168.07:49:21.85#ibcon#end of sib2, iclass 16, count 0 2006.168.07:49:21.85#ibcon#*mode == 0, iclass 16, count 0 2006.168.07:49:21.85#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.168.07:49:21.85#ibcon#[27=USB\r\n] 2006.168.07:49:21.85#ibcon#*before write, iclass 16, count 0 2006.168.07:49:21.85#ibcon#enter sib2, iclass 16, count 0 2006.168.07:49:21.85#ibcon#flushed, iclass 16, count 0 2006.168.07:49:21.85#ibcon#about to write, iclass 16, count 0 2006.168.07:49:21.85#ibcon#wrote, iclass 16, count 0 2006.168.07:49:21.85#ibcon#about to read 3, iclass 16, count 0 2006.168.07:49:21.88#ibcon#read 3, iclass 16, count 0 2006.168.07:49:21.88#ibcon#about to read 4, iclass 16, count 0 2006.168.07:49:21.88#ibcon#read 4, iclass 16, count 0 2006.168.07:49:21.88#ibcon#about to read 5, iclass 16, count 0 2006.168.07:49:21.88#ibcon#read 5, iclass 16, count 0 2006.168.07:49:21.88#ibcon#about to read 6, iclass 16, count 0 2006.168.07:49:21.88#ibcon#read 6, iclass 16, count 0 2006.168.07:49:21.88#ibcon#end of sib2, iclass 16, count 0 2006.168.07:49:21.88#ibcon#*after write, iclass 16, count 0 2006.168.07:49:21.88#ibcon#*before return 0, iclass 16, count 0 2006.168.07:49:21.88#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:49:21.88#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:49:21.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.168.07:49:21.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.168.07:49:21.88$vc4f8/vblo=5,744.99 2006.168.07:49:21.88#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.168.07:49:21.88#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.168.07:49:21.88#ibcon#ireg 17 cls_cnt 0 2006.168.07:49:21.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:49:21.88#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:49:21.88#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:49:21.88#ibcon#enter wrdev, iclass 18, count 0 2006.168.07:49:21.88#ibcon#first serial, iclass 18, count 0 2006.168.07:49:21.88#ibcon#enter sib2, iclass 18, count 0 2006.168.07:49:21.88#ibcon#flushed, iclass 18, count 0 2006.168.07:49:21.88#ibcon#about to write, iclass 18, count 0 2006.168.07:49:21.88#ibcon#wrote, iclass 18, count 0 2006.168.07:49:21.88#ibcon#about to read 3, iclass 18, count 0 2006.168.07:49:21.90#ibcon#read 3, iclass 18, count 0 2006.168.07:49:21.90#ibcon#about to read 4, iclass 18, count 0 2006.168.07:49:21.90#ibcon#read 4, iclass 18, count 0 2006.168.07:49:21.90#ibcon#about to read 5, iclass 18, count 0 2006.168.07:49:21.90#ibcon#read 5, iclass 18, count 0 2006.168.07:49:21.90#ibcon#about to read 6, iclass 18, count 0 2006.168.07:49:21.90#ibcon#read 6, iclass 18, count 0 2006.168.07:49:21.90#ibcon#end of sib2, iclass 18, count 0 2006.168.07:49:21.90#ibcon#*mode == 0, iclass 18, count 0 2006.168.07:49:21.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.07:49:21.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.07:49:21.90#ibcon#*before write, iclass 18, count 0 2006.168.07:49:21.90#ibcon#enter sib2, iclass 18, count 0 2006.168.07:49:21.90#ibcon#flushed, iclass 18, count 0 2006.168.07:49:21.90#ibcon#about to write, iclass 18, count 0 2006.168.07:49:21.90#ibcon#wrote, iclass 18, count 0 2006.168.07:49:21.90#ibcon#about to read 3, iclass 18, count 0 2006.168.07:49:21.94#ibcon#read 3, iclass 18, count 0 2006.168.07:49:21.94#ibcon#about to read 4, iclass 18, count 0 2006.168.07:49:21.94#ibcon#read 4, iclass 18, count 0 2006.168.07:49:21.94#ibcon#about to read 5, iclass 18, count 0 2006.168.07:49:21.94#ibcon#read 5, iclass 18, count 0 2006.168.07:49:21.94#ibcon#about to read 6, iclass 18, count 0 2006.168.07:49:21.94#ibcon#read 6, iclass 18, count 0 2006.168.07:49:21.94#ibcon#end of sib2, iclass 18, count 0 2006.168.07:49:21.94#ibcon#*after write, iclass 18, count 0 2006.168.07:49:21.94#ibcon#*before return 0, iclass 18, count 0 2006.168.07:49:21.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:49:21.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:49:21.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.07:49:21.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.07:49:21.94$vc4f8/vb=5,4 2006.168.07:49:21.94#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.168.07:49:21.94#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.168.07:49:21.94#ibcon#ireg 11 cls_cnt 2 2006.168.07:49:21.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:49:22.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:49:22.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:49:22.00#ibcon#enter wrdev, iclass 20, count 2 2006.168.07:49:22.00#ibcon#first serial, iclass 20, count 2 2006.168.07:49:22.00#ibcon#enter sib2, iclass 20, count 2 2006.168.07:49:22.00#ibcon#flushed, iclass 20, count 2 2006.168.07:49:22.00#ibcon#about to write, iclass 20, count 2 2006.168.07:49:22.00#ibcon#wrote, iclass 20, count 2 2006.168.07:49:22.00#ibcon#about to read 3, iclass 20, count 2 2006.168.07:49:22.02#ibcon#read 3, iclass 20, count 2 2006.168.07:49:22.02#ibcon#about to read 4, iclass 20, count 2 2006.168.07:49:22.02#ibcon#read 4, iclass 20, count 2 2006.168.07:49:22.02#ibcon#about to read 5, iclass 20, count 2 2006.168.07:49:22.02#ibcon#read 5, iclass 20, count 2 2006.168.07:49:22.02#ibcon#about to read 6, iclass 20, count 2 2006.168.07:49:22.02#ibcon#read 6, iclass 20, count 2 2006.168.07:49:22.02#ibcon#end of sib2, iclass 20, count 2 2006.168.07:49:22.02#ibcon#*mode == 0, iclass 20, count 2 2006.168.07:49:22.02#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.168.07:49:22.02#ibcon#[27=AT05-04\r\n] 2006.168.07:49:22.02#ibcon#*before write, iclass 20, count 2 2006.168.07:49:22.02#ibcon#enter sib2, iclass 20, count 2 2006.168.07:49:22.02#ibcon#flushed, iclass 20, count 2 2006.168.07:49:22.02#ibcon#about to write, iclass 20, count 2 2006.168.07:49:22.02#ibcon#wrote, iclass 20, count 2 2006.168.07:49:22.02#ibcon#about to read 3, iclass 20, count 2 2006.168.07:49:22.05#ibcon#read 3, iclass 20, count 2 2006.168.07:49:22.05#ibcon#about to read 4, iclass 20, count 2 2006.168.07:49:22.05#ibcon#read 4, iclass 20, count 2 2006.168.07:49:22.05#ibcon#about to read 5, iclass 20, count 2 2006.168.07:49:22.05#ibcon#read 5, iclass 20, count 2 2006.168.07:49:22.05#ibcon#about to read 6, iclass 20, count 2 2006.168.07:49:22.05#ibcon#read 6, iclass 20, count 2 2006.168.07:49:22.05#ibcon#end of sib2, iclass 20, count 2 2006.168.07:49:22.05#ibcon#*after write, iclass 20, count 2 2006.168.07:49:22.05#ibcon#*before return 0, iclass 20, count 2 2006.168.07:49:22.05#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:49:22.05#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:49:22.05#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.168.07:49:22.05#ibcon#ireg 7 cls_cnt 0 2006.168.07:49:22.05#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:49:22.17#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:49:22.17#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:49:22.17#ibcon#enter wrdev, iclass 20, count 0 2006.168.07:49:22.17#ibcon#first serial, iclass 20, count 0 2006.168.07:49:22.17#ibcon#enter sib2, iclass 20, count 0 2006.168.07:49:22.17#ibcon#flushed, iclass 20, count 0 2006.168.07:49:22.17#ibcon#about to write, iclass 20, count 0 2006.168.07:49:22.17#ibcon#wrote, iclass 20, count 0 2006.168.07:49:22.17#ibcon#about to read 3, iclass 20, count 0 2006.168.07:49:22.19#ibcon#read 3, iclass 20, count 0 2006.168.07:49:22.19#ibcon#about to read 4, iclass 20, count 0 2006.168.07:49:22.19#ibcon#read 4, iclass 20, count 0 2006.168.07:49:22.19#ibcon#about to read 5, iclass 20, count 0 2006.168.07:49:22.19#ibcon#read 5, iclass 20, count 0 2006.168.07:49:22.19#ibcon#about to read 6, iclass 20, count 0 2006.168.07:49:22.19#ibcon#read 6, iclass 20, count 0 2006.168.07:49:22.19#ibcon#end of sib2, iclass 20, count 0 2006.168.07:49:22.19#ibcon#*mode == 0, iclass 20, count 0 2006.168.07:49:22.19#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.168.07:49:22.19#ibcon#[27=USB\r\n] 2006.168.07:49:22.19#ibcon#*before write, iclass 20, count 0 2006.168.07:49:22.19#ibcon#enter sib2, iclass 20, count 0 2006.168.07:49:22.19#ibcon#flushed, iclass 20, count 0 2006.168.07:49:22.19#ibcon#about to write, iclass 20, count 0 2006.168.07:49:22.19#ibcon#wrote, iclass 20, count 0 2006.168.07:49:22.19#ibcon#about to read 3, iclass 20, count 0 2006.168.07:49:22.22#ibcon#read 3, iclass 20, count 0 2006.168.07:49:22.22#ibcon#about to read 4, iclass 20, count 0 2006.168.07:49:22.22#ibcon#read 4, iclass 20, count 0 2006.168.07:49:22.22#ibcon#about to read 5, iclass 20, count 0 2006.168.07:49:22.22#ibcon#read 5, iclass 20, count 0 2006.168.07:49:22.22#ibcon#about to read 6, iclass 20, count 0 2006.168.07:49:22.22#ibcon#read 6, iclass 20, count 0 2006.168.07:49:22.22#ibcon#end of sib2, iclass 20, count 0 2006.168.07:49:22.22#ibcon#*after write, iclass 20, count 0 2006.168.07:49:22.22#ibcon#*before return 0, iclass 20, count 0 2006.168.07:49:22.22#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:49:22.22#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:49:22.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.168.07:49:22.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.168.07:49:22.22$vc4f8/vblo=6,752.99 2006.168.07:49:22.22#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.168.07:49:22.22#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.168.07:49:22.22#ibcon#ireg 17 cls_cnt 0 2006.168.07:49:22.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:49:22.22#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:49:22.22#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:49:22.22#ibcon#enter wrdev, iclass 22, count 0 2006.168.07:49:22.22#ibcon#first serial, iclass 22, count 0 2006.168.07:49:22.22#ibcon#enter sib2, iclass 22, count 0 2006.168.07:49:22.22#ibcon#flushed, iclass 22, count 0 2006.168.07:49:22.22#ibcon#about to write, iclass 22, count 0 2006.168.07:49:22.22#ibcon#wrote, iclass 22, count 0 2006.168.07:49:22.22#ibcon#about to read 3, iclass 22, count 0 2006.168.07:49:22.24#ibcon#read 3, iclass 22, count 0 2006.168.07:49:22.24#ibcon#about to read 4, iclass 22, count 0 2006.168.07:49:22.24#ibcon#read 4, iclass 22, count 0 2006.168.07:49:22.24#ibcon#about to read 5, iclass 22, count 0 2006.168.07:49:22.24#ibcon#read 5, iclass 22, count 0 2006.168.07:49:22.24#ibcon#about to read 6, iclass 22, count 0 2006.168.07:49:22.24#ibcon#read 6, iclass 22, count 0 2006.168.07:49:22.24#ibcon#end of sib2, iclass 22, count 0 2006.168.07:49:22.24#ibcon#*mode == 0, iclass 22, count 0 2006.168.07:49:22.24#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.168.07:49:22.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.07:49:22.24#ibcon#*before write, iclass 22, count 0 2006.168.07:49:22.24#ibcon#enter sib2, iclass 22, count 0 2006.168.07:49:22.24#ibcon#flushed, iclass 22, count 0 2006.168.07:49:22.24#ibcon#about to write, iclass 22, count 0 2006.168.07:49:22.24#ibcon#wrote, iclass 22, count 0 2006.168.07:49:22.24#ibcon#about to read 3, iclass 22, count 0 2006.168.07:49:22.28#ibcon#read 3, iclass 22, count 0 2006.168.07:49:22.28#ibcon#about to read 4, iclass 22, count 0 2006.168.07:49:22.28#ibcon#read 4, iclass 22, count 0 2006.168.07:49:22.28#ibcon#about to read 5, iclass 22, count 0 2006.168.07:49:22.28#ibcon#read 5, iclass 22, count 0 2006.168.07:49:22.28#ibcon#about to read 6, iclass 22, count 0 2006.168.07:49:22.28#ibcon#read 6, iclass 22, count 0 2006.168.07:49:22.28#ibcon#end of sib2, iclass 22, count 0 2006.168.07:49:22.28#ibcon#*after write, iclass 22, count 0 2006.168.07:49:22.28#ibcon#*before return 0, iclass 22, count 0 2006.168.07:49:22.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:49:22.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:49:22.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.168.07:49:22.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.168.07:49:22.28$vc4f8/vb=6,4 2006.168.07:49:22.28#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.168.07:49:22.28#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.168.07:49:22.28#ibcon#ireg 11 cls_cnt 2 2006.168.07:49:22.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:49:22.34#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:49:22.34#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:49:22.34#ibcon#enter wrdev, iclass 24, count 2 2006.168.07:49:22.34#ibcon#first serial, iclass 24, count 2 2006.168.07:49:22.34#ibcon#enter sib2, iclass 24, count 2 2006.168.07:49:22.34#ibcon#flushed, iclass 24, count 2 2006.168.07:49:22.34#ibcon#about to write, iclass 24, count 2 2006.168.07:49:22.34#ibcon#wrote, iclass 24, count 2 2006.168.07:49:22.34#ibcon#about to read 3, iclass 24, count 2 2006.168.07:49:22.36#ibcon#read 3, iclass 24, count 2 2006.168.07:49:22.36#ibcon#about to read 4, iclass 24, count 2 2006.168.07:49:22.36#ibcon#read 4, iclass 24, count 2 2006.168.07:49:22.36#ibcon#about to read 5, iclass 24, count 2 2006.168.07:49:22.36#ibcon#read 5, iclass 24, count 2 2006.168.07:49:22.36#ibcon#about to read 6, iclass 24, count 2 2006.168.07:49:22.36#ibcon#read 6, iclass 24, count 2 2006.168.07:49:22.36#ibcon#end of sib2, iclass 24, count 2 2006.168.07:49:22.36#ibcon#*mode == 0, iclass 24, count 2 2006.168.07:49:22.36#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.168.07:49:22.36#ibcon#[27=AT06-04\r\n] 2006.168.07:49:22.36#ibcon#*before write, iclass 24, count 2 2006.168.07:49:22.36#ibcon#enter sib2, iclass 24, count 2 2006.168.07:49:22.36#ibcon#flushed, iclass 24, count 2 2006.168.07:49:22.36#ibcon#about to write, iclass 24, count 2 2006.168.07:49:22.36#ibcon#wrote, iclass 24, count 2 2006.168.07:49:22.36#ibcon#about to read 3, iclass 24, count 2 2006.168.07:49:22.39#ibcon#read 3, iclass 24, count 2 2006.168.07:49:22.39#ibcon#about to read 4, iclass 24, count 2 2006.168.07:49:22.39#ibcon#read 4, iclass 24, count 2 2006.168.07:49:22.39#ibcon#about to read 5, iclass 24, count 2 2006.168.07:49:22.39#ibcon#read 5, iclass 24, count 2 2006.168.07:49:22.39#ibcon#about to read 6, iclass 24, count 2 2006.168.07:49:22.39#ibcon#read 6, iclass 24, count 2 2006.168.07:49:22.39#ibcon#end of sib2, iclass 24, count 2 2006.168.07:49:22.39#ibcon#*after write, iclass 24, count 2 2006.168.07:49:22.39#ibcon#*before return 0, iclass 24, count 2 2006.168.07:49:22.39#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:49:22.39#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.168.07:49:22.39#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.168.07:49:22.39#ibcon#ireg 7 cls_cnt 0 2006.168.07:49:22.39#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:49:22.51#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:49:22.51#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:49:22.51#ibcon#enter wrdev, iclass 24, count 0 2006.168.07:49:22.51#ibcon#first serial, iclass 24, count 0 2006.168.07:49:22.51#ibcon#enter sib2, iclass 24, count 0 2006.168.07:49:22.51#ibcon#flushed, iclass 24, count 0 2006.168.07:49:22.51#ibcon#about to write, iclass 24, count 0 2006.168.07:49:22.51#ibcon#wrote, iclass 24, count 0 2006.168.07:49:22.51#ibcon#about to read 3, iclass 24, count 0 2006.168.07:49:22.53#ibcon#read 3, iclass 24, count 0 2006.168.07:49:22.53#ibcon#about to read 4, iclass 24, count 0 2006.168.07:49:22.53#ibcon#read 4, iclass 24, count 0 2006.168.07:49:22.53#ibcon#about to read 5, iclass 24, count 0 2006.168.07:49:22.53#ibcon#read 5, iclass 24, count 0 2006.168.07:49:22.53#ibcon#about to read 6, iclass 24, count 0 2006.168.07:49:22.53#ibcon#read 6, iclass 24, count 0 2006.168.07:49:22.53#ibcon#end of sib2, iclass 24, count 0 2006.168.07:49:22.53#ibcon#*mode == 0, iclass 24, count 0 2006.168.07:49:22.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.168.07:49:22.53#ibcon#[27=USB\r\n] 2006.168.07:49:22.53#ibcon#*before write, iclass 24, count 0 2006.168.07:49:22.53#ibcon#enter sib2, iclass 24, count 0 2006.168.07:49:22.53#ibcon#flushed, iclass 24, count 0 2006.168.07:49:22.53#ibcon#about to write, iclass 24, count 0 2006.168.07:49:22.53#ibcon#wrote, iclass 24, count 0 2006.168.07:49:22.53#ibcon#about to read 3, iclass 24, count 0 2006.168.07:49:22.56#ibcon#read 3, iclass 24, count 0 2006.168.07:49:22.56#ibcon#about to read 4, iclass 24, count 0 2006.168.07:49:22.56#ibcon#read 4, iclass 24, count 0 2006.168.07:49:22.56#ibcon#about to read 5, iclass 24, count 0 2006.168.07:49:22.56#ibcon#read 5, iclass 24, count 0 2006.168.07:49:22.56#ibcon#about to read 6, iclass 24, count 0 2006.168.07:49:22.56#ibcon#read 6, iclass 24, count 0 2006.168.07:49:22.56#ibcon#end of sib2, iclass 24, count 0 2006.168.07:49:22.56#ibcon#*after write, iclass 24, count 0 2006.168.07:49:22.56#ibcon#*before return 0, iclass 24, count 0 2006.168.07:49:22.56#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:49:22.56#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.168.07:49:22.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.168.07:49:22.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.168.07:49:22.56$vc4f8/vabw=wide 2006.168.07:49:22.56#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.168.07:49:22.56#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.168.07:49:22.56#ibcon#ireg 8 cls_cnt 0 2006.168.07:49:22.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:49:22.56#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:49:22.56#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:49:22.56#ibcon#enter wrdev, iclass 26, count 0 2006.168.07:49:22.56#ibcon#first serial, iclass 26, count 0 2006.168.07:49:22.56#ibcon#enter sib2, iclass 26, count 0 2006.168.07:49:22.56#ibcon#flushed, iclass 26, count 0 2006.168.07:49:22.56#ibcon#about to write, iclass 26, count 0 2006.168.07:49:22.56#ibcon#wrote, iclass 26, count 0 2006.168.07:49:22.56#ibcon#about to read 3, iclass 26, count 0 2006.168.07:49:22.58#ibcon#read 3, iclass 26, count 0 2006.168.07:49:22.58#ibcon#about to read 4, iclass 26, count 0 2006.168.07:49:22.58#ibcon#read 4, iclass 26, count 0 2006.168.07:49:22.58#ibcon#about to read 5, iclass 26, count 0 2006.168.07:49:22.58#ibcon#read 5, iclass 26, count 0 2006.168.07:49:22.58#ibcon#about to read 6, iclass 26, count 0 2006.168.07:49:22.58#ibcon#read 6, iclass 26, count 0 2006.168.07:49:22.58#ibcon#end of sib2, iclass 26, count 0 2006.168.07:49:22.58#ibcon#*mode == 0, iclass 26, count 0 2006.168.07:49:22.58#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.168.07:49:22.58#ibcon#[25=BW32\r\n] 2006.168.07:49:22.58#ibcon#*before write, iclass 26, count 0 2006.168.07:49:22.58#ibcon#enter sib2, iclass 26, count 0 2006.168.07:49:22.58#ibcon#flushed, iclass 26, count 0 2006.168.07:49:22.58#ibcon#about to write, iclass 26, count 0 2006.168.07:49:22.58#ibcon#wrote, iclass 26, count 0 2006.168.07:49:22.58#ibcon#about to read 3, iclass 26, count 0 2006.168.07:49:22.61#ibcon#read 3, iclass 26, count 0 2006.168.07:49:22.61#ibcon#about to read 4, iclass 26, count 0 2006.168.07:49:22.61#ibcon#read 4, iclass 26, count 0 2006.168.07:49:22.61#ibcon#about to read 5, iclass 26, count 0 2006.168.07:49:22.61#ibcon#read 5, iclass 26, count 0 2006.168.07:49:22.61#ibcon#about to read 6, iclass 26, count 0 2006.168.07:49:22.61#ibcon#read 6, iclass 26, count 0 2006.168.07:49:22.61#ibcon#end of sib2, iclass 26, count 0 2006.168.07:49:22.61#ibcon#*after write, iclass 26, count 0 2006.168.07:49:22.61#ibcon#*before return 0, iclass 26, count 0 2006.168.07:49:22.61#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:49:22.61#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.168.07:49:22.61#ibcon#about to clear, iclass 26 cls_cnt 0 2006.168.07:49:22.61#ibcon#cleared, iclass 26 cls_cnt 0 2006.168.07:49:22.61$vc4f8/vbbw=wide 2006.168.07:49:22.61#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.168.07:49:22.61#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.168.07:49:22.61#ibcon#ireg 8 cls_cnt 0 2006.168.07:49:22.61#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:49:22.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:49:22.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:49:22.68#ibcon#enter wrdev, iclass 28, count 0 2006.168.07:49:22.68#ibcon#first serial, iclass 28, count 0 2006.168.07:49:22.68#ibcon#enter sib2, iclass 28, count 0 2006.168.07:49:22.68#ibcon#flushed, iclass 28, count 0 2006.168.07:49:22.68#ibcon#about to write, iclass 28, count 0 2006.168.07:49:22.68#ibcon#wrote, iclass 28, count 0 2006.168.07:49:22.68#ibcon#about to read 3, iclass 28, count 0 2006.168.07:49:22.70#ibcon#read 3, iclass 28, count 0 2006.168.07:49:22.70#ibcon#about to read 4, iclass 28, count 0 2006.168.07:49:22.70#ibcon#read 4, iclass 28, count 0 2006.168.07:49:22.70#ibcon#about to read 5, iclass 28, count 0 2006.168.07:49:22.70#ibcon#read 5, iclass 28, count 0 2006.168.07:49:22.70#ibcon#about to read 6, iclass 28, count 0 2006.168.07:49:22.70#ibcon#read 6, iclass 28, count 0 2006.168.07:49:22.70#ibcon#end of sib2, iclass 28, count 0 2006.168.07:49:22.70#ibcon#*mode == 0, iclass 28, count 0 2006.168.07:49:22.70#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.168.07:49:22.70#ibcon#[27=BW32\r\n] 2006.168.07:49:22.70#ibcon#*before write, iclass 28, count 0 2006.168.07:49:22.70#ibcon#enter sib2, iclass 28, count 0 2006.168.07:49:22.70#ibcon#flushed, iclass 28, count 0 2006.168.07:49:22.70#ibcon#about to write, iclass 28, count 0 2006.168.07:49:22.70#ibcon#wrote, iclass 28, count 0 2006.168.07:49:22.70#ibcon#about to read 3, iclass 28, count 0 2006.168.07:49:22.73#ibcon#read 3, iclass 28, count 0 2006.168.07:49:22.73#ibcon#about to read 4, iclass 28, count 0 2006.168.07:49:22.73#ibcon#read 4, iclass 28, count 0 2006.168.07:49:22.73#ibcon#about to read 5, iclass 28, count 0 2006.168.07:49:22.73#ibcon#read 5, iclass 28, count 0 2006.168.07:49:22.73#ibcon#about to read 6, iclass 28, count 0 2006.168.07:49:22.73#ibcon#read 6, iclass 28, count 0 2006.168.07:49:22.73#ibcon#end of sib2, iclass 28, count 0 2006.168.07:49:22.73#ibcon#*after write, iclass 28, count 0 2006.168.07:49:22.73#ibcon#*before return 0, iclass 28, count 0 2006.168.07:49:22.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:49:22.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:49:22.73#ibcon#about to clear, iclass 28 cls_cnt 0 2006.168.07:49:22.73#ibcon#cleared, iclass 28 cls_cnt 0 2006.168.07:49:22.74$4f8m12a/ifd4f 2006.168.07:49:22.74$ifd4f/lo= 2006.168.07:49:22.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.07:49:22.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.07:49:22.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.07:49:22.74$ifd4f/patch= 2006.168.07:49:22.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.07:49:22.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.07:49:22.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.07:49:22.74$4f8m12a/"form=m,16.000,1:2 2006.168.07:49:22.74$4f8m12a/"tpicd 2006.168.07:49:22.74$4f8m12a/echo=off 2006.168.07:49:22.74$4f8m12a/xlog=off 2006.168.07:49:22.74:!2006.168.07:50:30 2006.168.07:50:03.14#trakl#Source acquired 2006.168.07:50:05.14#flagr#flagr/antenna,acquired 2006.168.07:50:30.01:preob 2006.168.07:50:31.14/onsource/TRACKING 2006.168.07:50:31.14:!2006.168.07:50:40 2006.168.07:50:40.00:data_valid=on 2006.168.07:50:40.00:midob 2006.168.07:50:40.14/onsource/TRACKING 2006.168.07:50:40.14/wx/27.37,1004.6,73 2006.168.07:50:40.28/cable/+6.4703E-03 2006.168.07:50:41.37/va/01,08,usb,yes,28,30 2006.168.07:50:41.37/va/02,07,usb,yes,28,30 2006.168.07:50:41.37/va/03,06,usb,yes,30,30 2006.168.07:50:41.37/va/04,07,usb,yes,29,31 2006.168.07:50:41.37/va/05,07,usb,yes,29,31 2006.168.07:50:41.37/va/06,06,usb,yes,28,28 2006.168.07:50:41.37/va/07,06,usb,yes,29,28 2006.168.07:50:41.37/va/08,07,usb,yes,27,27 2006.168.07:50:41.60/valo/01,532.99,yes,locked 2006.168.07:50:41.60/valo/02,572.99,yes,locked 2006.168.07:50:41.60/valo/03,672.99,yes,locked 2006.168.07:50:41.60/valo/04,832.99,yes,locked 2006.168.07:50:41.60/valo/05,652.99,yes,locked 2006.168.07:50:41.60/valo/06,772.99,yes,locked 2006.168.07:50:41.60/valo/07,832.99,yes,locked 2006.168.07:50:41.60/valo/08,852.99,yes,locked 2006.168.07:50:42.69/vb/01,04,usb,yes,29,27 2006.168.07:50:42.69/vb/02,04,usb,yes,31,32 2006.168.07:50:42.69/vb/03,04,usb,yes,27,31 2006.168.07:50:42.69/vb/04,04,usb,yes,28,28 2006.168.07:50:42.69/vb/05,04,usb,yes,27,30 2006.168.07:50:42.69/vb/06,04,usb,yes,28,30 2006.168.07:50:42.69/vb/07,04,usb,yes,29,29 2006.168.07:50:42.69/vb/08,04,usb,yes,28,30 2006.168.07:50:42.93/vblo/01,632.99,yes,locked 2006.168.07:50:42.93/vblo/02,640.99,yes,locked 2006.168.07:50:42.93/vblo/03,656.99,yes,locked 2006.168.07:50:42.93/vblo/04,712.99,yes,locked 2006.168.07:50:42.93/vblo/05,744.99,yes,locked 2006.168.07:50:42.93/vblo/06,752.99,yes,locked 2006.168.07:50:42.93/vblo/07,734.99,yes,locked 2006.168.07:50:42.93/vblo/08,744.99,yes,locked 2006.168.07:50:43.08/vabw/8 2006.168.07:50:43.23/vbbw/8 2006.168.07:50:43.32/xfe/off,on,15.5 2006.168.07:50:43.71/ifatt/23,28,28,28 2006.168.07:50:44.07/fmout-gps/S +4.18E-07 2006.168.07:50:44.15:!2006.168.07:51:40 2006.168.07:51:40.01:data_valid=off 2006.168.07:51:40.02:postob 2006.168.07:51:40.08/cable/+6.4720E-03 2006.168.07:51:40.09/wx/27.34,1004.6,73 2006.168.07:51:41.07/fmout-gps/S +4.18E-07 2006.168.07:51:41.08:scan_name=168-0752,k06168,60 2006.168.07:51:41.08:source=1803+784,180045.68,782804.0,2000.0,cw 2006.168.07:51:42.14#flagr#flagr/antenna,new-source 2006.168.07:51:42.15:checkk5 2006.168.07:51:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.168.07:51:42.90/chk_autoobs//k5ts2/ autoobs is running! 2006.168.07:51:43.28/chk_autoobs//k5ts3/ autoobs is running! 2006.168.07:51:43.66/chk_autoobs//k5ts4/ autoobs is running! 2006.168.07:51:44.02/chk_obsdata//k5ts1/T1680750??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.168.07:51:44.39/chk_obsdata//k5ts2/T1680750??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.168.07:51:44.76/chk_obsdata//k5ts3/T1680750??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.168.07:51:45.13/chk_obsdata//k5ts4/T1680750??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.168.07:51:45.81/k5log//k5ts1_log_newline 2006.168.07:51:46.51/k5log//k5ts2_log_newline 2006.168.07:51:47.20/k5log//k5ts3_log_newline 2006.168.07:51:47.90/k5log//k5ts4_log_newline 2006.168.07:51:47.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.07:51:47.92:4f8m12a=1 2006.168.07:51:47.92$4f8m12a/echo=on 2006.168.07:51:47.92$4f8m12a/pcalon 2006.168.07:51:47.92$pcalon/"no phase cal control is implemented here 2006.168.07:51:47.92$4f8m12a/"tpicd=stop 2006.168.07:51:47.92$4f8m12a/vc4f8 2006.168.07:51:47.92$vc4f8/valo=1,532.99 2006.168.07:51:47.92#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.168.07:51:47.92#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.168.07:51:47.92#ibcon#ireg 17 cls_cnt 0 2006.168.07:51:47.92#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:51:47.92#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:51:47.92#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:51:47.92#ibcon#enter wrdev, iclass 15, count 0 2006.168.07:51:47.92#ibcon#first serial, iclass 15, count 0 2006.168.07:51:47.92#ibcon#enter sib2, iclass 15, count 0 2006.168.07:51:47.92#ibcon#flushed, iclass 15, count 0 2006.168.07:51:47.92#ibcon#about to write, iclass 15, count 0 2006.168.07:51:47.93#ibcon#wrote, iclass 15, count 0 2006.168.07:51:47.93#ibcon#about to read 3, iclass 15, count 0 2006.168.07:51:47.97#ibcon#read 3, iclass 15, count 0 2006.168.07:51:47.97#ibcon#about to read 4, iclass 15, count 0 2006.168.07:51:47.97#ibcon#read 4, iclass 15, count 0 2006.168.07:51:47.97#ibcon#about to read 5, iclass 15, count 0 2006.168.07:51:47.97#ibcon#read 5, iclass 15, count 0 2006.168.07:51:47.97#ibcon#about to read 6, iclass 15, count 0 2006.168.07:51:47.97#ibcon#read 6, iclass 15, count 0 2006.168.07:51:47.97#ibcon#end of sib2, iclass 15, count 0 2006.168.07:51:47.97#ibcon#*mode == 0, iclass 15, count 0 2006.168.07:51:47.97#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.168.07:51:47.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.07:51:47.97#ibcon#*before write, iclass 15, count 0 2006.168.07:51:47.97#ibcon#enter sib2, iclass 15, count 0 2006.168.07:51:47.97#ibcon#flushed, iclass 15, count 0 2006.168.07:51:47.97#ibcon#about to write, iclass 15, count 0 2006.168.07:51:47.97#ibcon#wrote, iclass 15, count 0 2006.168.07:51:47.97#ibcon#about to read 3, iclass 15, count 0 2006.168.07:51:48.01#ibcon#read 3, iclass 15, count 0 2006.168.07:51:48.01#ibcon#about to read 4, iclass 15, count 0 2006.168.07:51:48.01#ibcon#read 4, iclass 15, count 0 2006.168.07:51:48.01#ibcon#about to read 5, iclass 15, count 0 2006.168.07:51:48.01#ibcon#read 5, iclass 15, count 0 2006.168.07:51:48.01#ibcon#about to read 6, iclass 15, count 0 2006.168.07:51:48.01#ibcon#read 6, iclass 15, count 0 2006.168.07:51:48.01#ibcon#end of sib2, iclass 15, count 0 2006.168.07:51:48.01#ibcon#*after write, iclass 15, count 0 2006.168.07:51:48.01#ibcon#*before return 0, iclass 15, count 0 2006.168.07:51:48.01#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:51:48.01#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:51:48.01#ibcon#about to clear, iclass 15 cls_cnt 0 2006.168.07:51:48.01#ibcon#cleared, iclass 15 cls_cnt 0 2006.168.07:51:48.01$vc4f8/va=1,8 2006.168.07:51:48.01#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.168.07:51:48.01#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.168.07:51:48.01#ibcon#ireg 11 cls_cnt 2 2006.168.07:51:48.01#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.168.07:51:48.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.168.07:51:48.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.168.07:51:48.01#ibcon#enter wrdev, iclass 17, count 2 2006.168.07:51:48.01#ibcon#first serial, iclass 17, count 2 2006.168.07:51:48.01#ibcon#enter sib2, iclass 17, count 2 2006.168.07:51:48.01#ibcon#flushed, iclass 17, count 2 2006.168.07:51:48.01#ibcon#about to write, iclass 17, count 2 2006.168.07:51:48.01#ibcon#wrote, iclass 17, count 2 2006.168.07:51:48.01#ibcon#about to read 3, iclass 17, count 2 2006.168.07:51:48.03#ibcon#read 3, iclass 17, count 2 2006.168.07:51:48.03#ibcon#about to read 4, iclass 17, count 2 2006.168.07:51:48.03#ibcon#read 4, iclass 17, count 2 2006.168.07:51:48.03#ibcon#about to read 5, iclass 17, count 2 2006.168.07:51:48.03#ibcon#read 5, iclass 17, count 2 2006.168.07:51:48.03#ibcon#about to read 6, iclass 17, count 2 2006.168.07:51:48.03#ibcon#read 6, iclass 17, count 2 2006.168.07:51:48.03#ibcon#end of sib2, iclass 17, count 2 2006.168.07:51:48.03#ibcon#*mode == 0, iclass 17, count 2 2006.168.07:51:48.03#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.168.07:51:48.03#ibcon#[25=AT01-08\r\n] 2006.168.07:51:48.03#ibcon#*before write, iclass 17, count 2 2006.168.07:51:48.03#ibcon#enter sib2, iclass 17, count 2 2006.168.07:51:48.03#ibcon#flushed, iclass 17, count 2 2006.168.07:51:48.03#ibcon#about to write, iclass 17, count 2 2006.168.07:51:48.04#ibcon#wrote, iclass 17, count 2 2006.168.07:51:48.04#ibcon#about to read 3, iclass 17, count 2 2006.168.07:51:48.06#ibcon#read 3, iclass 17, count 2 2006.168.07:51:48.06#ibcon#about to read 4, iclass 17, count 2 2006.168.07:51:48.06#ibcon#read 4, iclass 17, count 2 2006.168.07:51:48.06#ibcon#about to read 5, iclass 17, count 2 2006.168.07:51:48.06#ibcon#read 5, iclass 17, count 2 2006.168.07:51:48.06#ibcon#about to read 6, iclass 17, count 2 2006.168.07:51:48.06#ibcon#read 6, iclass 17, count 2 2006.168.07:51:48.06#ibcon#end of sib2, iclass 17, count 2 2006.168.07:51:48.06#ibcon#*after write, iclass 17, count 2 2006.168.07:51:48.06#ibcon#*before return 0, iclass 17, count 2 2006.168.07:51:48.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.168.07:51:48.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.168.07:51:48.06#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.168.07:51:48.06#ibcon#ireg 7 cls_cnt 0 2006.168.07:51:48.06#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.168.07:51:48.18#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.168.07:51:48.18#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.168.07:51:48.18#ibcon#enter wrdev, iclass 17, count 0 2006.168.07:51:48.18#ibcon#first serial, iclass 17, count 0 2006.168.07:51:48.18#ibcon#enter sib2, iclass 17, count 0 2006.168.07:51:48.18#ibcon#flushed, iclass 17, count 0 2006.168.07:51:48.18#ibcon#about to write, iclass 17, count 0 2006.168.07:51:48.18#ibcon#wrote, iclass 17, count 0 2006.168.07:51:48.18#ibcon#about to read 3, iclass 17, count 0 2006.168.07:51:48.20#ibcon#read 3, iclass 17, count 0 2006.168.07:51:48.20#ibcon#about to read 4, iclass 17, count 0 2006.168.07:51:48.20#ibcon#read 4, iclass 17, count 0 2006.168.07:51:48.20#ibcon#about to read 5, iclass 17, count 0 2006.168.07:51:48.20#ibcon#read 5, iclass 17, count 0 2006.168.07:51:48.20#ibcon#about to read 6, iclass 17, count 0 2006.168.07:51:48.20#ibcon#read 6, iclass 17, count 0 2006.168.07:51:48.20#ibcon#end of sib2, iclass 17, count 0 2006.168.07:51:48.20#ibcon#*mode == 0, iclass 17, count 0 2006.168.07:51:48.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.168.07:51:48.20#ibcon#[25=USB\r\n] 2006.168.07:51:48.20#ibcon#*before write, iclass 17, count 0 2006.168.07:51:48.20#ibcon#enter sib2, iclass 17, count 0 2006.168.07:51:48.20#ibcon#flushed, iclass 17, count 0 2006.168.07:51:48.20#ibcon#about to write, iclass 17, count 0 2006.168.07:51:48.20#ibcon#wrote, iclass 17, count 0 2006.168.07:51:48.20#ibcon#about to read 3, iclass 17, count 0 2006.168.07:51:48.23#ibcon#read 3, iclass 17, count 0 2006.168.07:51:48.23#ibcon#about to read 4, iclass 17, count 0 2006.168.07:51:48.23#ibcon#read 4, iclass 17, count 0 2006.168.07:51:48.23#ibcon#about to read 5, iclass 17, count 0 2006.168.07:51:48.23#ibcon#read 5, iclass 17, count 0 2006.168.07:51:48.23#ibcon#about to read 6, iclass 17, count 0 2006.168.07:51:48.23#ibcon#read 6, iclass 17, count 0 2006.168.07:51:48.23#ibcon#end of sib2, iclass 17, count 0 2006.168.07:51:48.23#ibcon#*after write, iclass 17, count 0 2006.168.07:51:48.23#ibcon#*before return 0, iclass 17, count 0 2006.168.07:51:48.23#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.168.07:51:48.23#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.168.07:51:48.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.168.07:51:48.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.168.07:51:48.23$vc4f8/valo=2,572.99 2006.168.07:51:48.23#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.168.07:51:48.23#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.168.07:51:48.23#ibcon#ireg 17 cls_cnt 0 2006.168.07:51:48.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:51:48.23#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:51:48.23#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:51:48.23#ibcon#enter wrdev, iclass 19, count 0 2006.168.07:51:48.23#ibcon#first serial, iclass 19, count 0 2006.168.07:51:48.23#ibcon#enter sib2, iclass 19, count 0 2006.168.07:51:48.23#ibcon#flushed, iclass 19, count 0 2006.168.07:51:48.23#ibcon#about to write, iclass 19, count 0 2006.168.07:51:48.23#ibcon#wrote, iclass 19, count 0 2006.168.07:51:48.23#ibcon#about to read 3, iclass 19, count 0 2006.168.07:51:48.26#ibcon#read 3, iclass 19, count 0 2006.168.07:51:48.26#ibcon#about to read 4, iclass 19, count 0 2006.168.07:51:48.26#ibcon#read 4, iclass 19, count 0 2006.168.07:51:48.26#ibcon#about to read 5, iclass 19, count 0 2006.168.07:51:48.26#ibcon#read 5, iclass 19, count 0 2006.168.07:51:48.26#ibcon#about to read 6, iclass 19, count 0 2006.168.07:51:48.26#ibcon#read 6, iclass 19, count 0 2006.168.07:51:48.26#ibcon#end of sib2, iclass 19, count 0 2006.168.07:51:48.26#ibcon#*mode == 0, iclass 19, count 0 2006.168.07:51:48.26#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.168.07:51:48.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.07:51:48.26#ibcon#*before write, iclass 19, count 0 2006.168.07:51:48.26#ibcon#enter sib2, iclass 19, count 0 2006.168.07:51:48.26#ibcon#flushed, iclass 19, count 0 2006.168.07:51:48.26#ibcon#about to write, iclass 19, count 0 2006.168.07:51:48.26#ibcon#wrote, iclass 19, count 0 2006.168.07:51:48.26#ibcon#about to read 3, iclass 19, count 0 2006.168.07:51:48.29#ibcon#read 3, iclass 19, count 0 2006.168.07:51:48.29#ibcon#about to read 4, iclass 19, count 0 2006.168.07:51:48.29#ibcon#read 4, iclass 19, count 0 2006.168.07:51:48.29#ibcon#about to read 5, iclass 19, count 0 2006.168.07:51:48.29#ibcon#read 5, iclass 19, count 0 2006.168.07:51:48.29#ibcon#about to read 6, iclass 19, count 0 2006.168.07:51:48.29#ibcon#read 6, iclass 19, count 0 2006.168.07:51:48.29#ibcon#end of sib2, iclass 19, count 0 2006.168.07:51:48.29#ibcon#*after write, iclass 19, count 0 2006.168.07:51:48.29#ibcon#*before return 0, iclass 19, count 0 2006.168.07:51:48.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:51:48.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:51:48.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.168.07:51:48.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.168.07:51:48.29$vc4f8/va=2,7 2006.168.07:51:48.29#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.168.07:51:48.29#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.168.07:51:48.29#ibcon#ireg 11 cls_cnt 2 2006.168.07:51:48.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.168.07:51:48.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.168.07:51:48.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.168.07:51:48.36#ibcon#enter wrdev, iclass 21, count 2 2006.168.07:51:48.36#ibcon#first serial, iclass 21, count 2 2006.168.07:51:48.36#ibcon#enter sib2, iclass 21, count 2 2006.168.07:51:48.36#ibcon#flushed, iclass 21, count 2 2006.168.07:51:48.36#ibcon#about to write, iclass 21, count 2 2006.168.07:51:48.36#ibcon#wrote, iclass 21, count 2 2006.168.07:51:48.36#ibcon#about to read 3, iclass 21, count 2 2006.168.07:51:48.38#ibcon#read 3, iclass 21, count 2 2006.168.07:51:48.38#ibcon#about to read 4, iclass 21, count 2 2006.168.07:51:48.38#ibcon#read 4, iclass 21, count 2 2006.168.07:51:48.38#ibcon#about to read 5, iclass 21, count 2 2006.168.07:51:48.38#ibcon#read 5, iclass 21, count 2 2006.168.07:51:48.38#ibcon#about to read 6, iclass 21, count 2 2006.168.07:51:48.38#ibcon#read 6, iclass 21, count 2 2006.168.07:51:48.38#ibcon#end of sib2, iclass 21, count 2 2006.168.07:51:48.38#ibcon#*mode == 0, iclass 21, count 2 2006.168.07:51:48.38#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.168.07:51:48.38#ibcon#[25=AT02-07\r\n] 2006.168.07:51:48.38#ibcon#*before write, iclass 21, count 2 2006.168.07:51:48.38#ibcon#enter sib2, iclass 21, count 2 2006.168.07:51:48.38#ibcon#flushed, iclass 21, count 2 2006.168.07:51:48.38#ibcon#about to write, iclass 21, count 2 2006.168.07:51:48.38#ibcon#wrote, iclass 21, count 2 2006.168.07:51:48.38#ibcon#about to read 3, iclass 21, count 2 2006.168.07:51:48.40#ibcon#read 3, iclass 21, count 2 2006.168.07:51:48.40#ibcon#about to read 4, iclass 21, count 2 2006.168.07:51:48.40#ibcon#read 4, iclass 21, count 2 2006.168.07:51:48.40#ibcon#about to read 5, iclass 21, count 2 2006.168.07:51:48.40#ibcon#read 5, iclass 21, count 2 2006.168.07:51:48.40#ibcon#about to read 6, iclass 21, count 2 2006.168.07:51:48.40#ibcon#read 6, iclass 21, count 2 2006.168.07:51:48.40#ibcon#end of sib2, iclass 21, count 2 2006.168.07:51:48.40#ibcon#*after write, iclass 21, count 2 2006.168.07:51:48.40#ibcon#*before return 0, iclass 21, count 2 2006.168.07:51:48.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.168.07:51:48.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.168.07:51:48.40#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.168.07:51:48.40#ibcon#ireg 7 cls_cnt 0 2006.168.07:51:48.40#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.168.07:51:48.52#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.168.07:51:48.52#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.168.07:51:48.52#ibcon#enter wrdev, iclass 21, count 0 2006.168.07:51:48.52#ibcon#first serial, iclass 21, count 0 2006.168.07:51:48.52#ibcon#enter sib2, iclass 21, count 0 2006.168.07:51:48.52#ibcon#flushed, iclass 21, count 0 2006.168.07:51:48.52#ibcon#about to write, iclass 21, count 0 2006.168.07:51:48.52#ibcon#wrote, iclass 21, count 0 2006.168.07:51:48.52#ibcon#about to read 3, iclass 21, count 0 2006.168.07:51:48.54#ibcon#read 3, iclass 21, count 0 2006.168.07:51:48.54#ibcon#about to read 4, iclass 21, count 0 2006.168.07:51:48.54#ibcon#read 4, iclass 21, count 0 2006.168.07:51:48.54#ibcon#about to read 5, iclass 21, count 0 2006.168.07:51:48.54#ibcon#read 5, iclass 21, count 0 2006.168.07:51:48.54#ibcon#about to read 6, iclass 21, count 0 2006.168.07:51:48.54#ibcon#read 6, iclass 21, count 0 2006.168.07:51:48.54#ibcon#end of sib2, iclass 21, count 0 2006.168.07:51:48.54#ibcon#*mode == 0, iclass 21, count 0 2006.168.07:51:48.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.168.07:51:48.54#ibcon#[25=USB\r\n] 2006.168.07:51:48.54#ibcon#*before write, iclass 21, count 0 2006.168.07:51:48.54#ibcon#enter sib2, iclass 21, count 0 2006.168.07:51:48.54#ibcon#flushed, iclass 21, count 0 2006.168.07:51:48.54#ibcon#about to write, iclass 21, count 0 2006.168.07:51:48.54#ibcon#wrote, iclass 21, count 0 2006.168.07:51:48.54#ibcon#about to read 3, iclass 21, count 0 2006.168.07:51:48.57#ibcon#read 3, iclass 21, count 0 2006.168.07:51:48.57#ibcon#about to read 4, iclass 21, count 0 2006.168.07:51:48.57#ibcon#read 4, iclass 21, count 0 2006.168.07:51:48.57#ibcon#about to read 5, iclass 21, count 0 2006.168.07:51:48.57#ibcon#read 5, iclass 21, count 0 2006.168.07:51:48.57#ibcon#about to read 6, iclass 21, count 0 2006.168.07:51:48.57#ibcon#read 6, iclass 21, count 0 2006.168.07:51:48.57#ibcon#end of sib2, iclass 21, count 0 2006.168.07:51:48.57#ibcon#*after write, iclass 21, count 0 2006.168.07:51:48.57#ibcon#*before return 0, iclass 21, count 0 2006.168.07:51:48.57#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.168.07:51:48.57#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.168.07:51:48.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.168.07:51:48.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.168.07:51:48.57$vc4f8/valo=3,672.99 2006.168.07:51:48.57#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.168.07:51:48.57#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.168.07:51:48.57#ibcon#ireg 17 cls_cnt 0 2006.168.07:51:48.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:51:48.57#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:51:48.57#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:51:48.57#ibcon#enter wrdev, iclass 23, count 0 2006.168.07:51:48.57#ibcon#first serial, iclass 23, count 0 2006.168.07:51:48.57#ibcon#enter sib2, iclass 23, count 0 2006.168.07:51:48.57#ibcon#flushed, iclass 23, count 0 2006.168.07:51:48.57#ibcon#about to write, iclass 23, count 0 2006.168.07:51:48.57#ibcon#wrote, iclass 23, count 0 2006.168.07:51:48.57#ibcon#about to read 3, iclass 23, count 0 2006.168.07:51:48.59#ibcon#read 3, iclass 23, count 0 2006.168.07:51:48.59#ibcon#about to read 4, iclass 23, count 0 2006.168.07:51:48.59#ibcon#read 4, iclass 23, count 0 2006.168.07:51:48.59#ibcon#about to read 5, iclass 23, count 0 2006.168.07:51:48.59#ibcon#read 5, iclass 23, count 0 2006.168.07:51:48.59#ibcon#about to read 6, iclass 23, count 0 2006.168.07:51:48.59#ibcon#read 6, iclass 23, count 0 2006.168.07:51:48.59#ibcon#end of sib2, iclass 23, count 0 2006.168.07:51:48.59#ibcon#*mode == 0, iclass 23, count 0 2006.168.07:51:48.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.168.07:51:48.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.07:51:48.59#ibcon#*before write, iclass 23, count 0 2006.168.07:51:48.59#ibcon#enter sib2, iclass 23, count 0 2006.168.07:51:48.59#ibcon#flushed, iclass 23, count 0 2006.168.07:51:48.59#ibcon#about to write, iclass 23, count 0 2006.168.07:51:48.59#ibcon#wrote, iclass 23, count 0 2006.168.07:51:48.59#ibcon#about to read 3, iclass 23, count 0 2006.168.07:51:48.63#ibcon#read 3, iclass 23, count 0 2006.168.07:51:48.63#ibcon#about to read 4, iclass 23, count 0 2006.168.07:51:48.63#ibcon#read 4, iclass 23, count 0 2006.168.07:51:48.63#ibcon#about to read 5, iclass 23, count 0 2006.168.07:51:48.63#ibcon#read 5, iclass 23, count 0 2006.168.07:51:48.63#ibcon#about to read 6, iclass 23, count 0 2006.168.07:51:48.63#ibcon#read 6, iclass 23, count 0 2006.168.07:51:48.63#ibcon#end of sib2, iclass 23, count 0 2006.168.07:51:48.63#ibcon#*after write, iclass 23, count 0 2006.168.07:51:48.63#ibcon#*before return 0, iclass 23, count 0 2006.168.07:51:48.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:51:48.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:51:48.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.168.07:51:48.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.168.07:51:48.63$vc4f8/va=3,6 2006.168.07:51:48.63#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.168.07:51:48.63#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.168.07:51:48.63#ibcon#ireg 11 cls_cnt 2 2006.168.07:51:48.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.168.07:51:48.69#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.168.07:51:48.69#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.168.07:51:48.69#ibcon#enter wrdev, iclass 25, count 2 2006.168.07:51:48.69#ibcon#first serial, iclass 25, count 2 2006.168.07:51:48.69#ibcon#enter sib2, iclass 25, count 2 2006.168.07:51:48.69#ibcon#flushed, iclass 25, count 2 2006.168.07:51:48.69#ibcon#about to write, iclass 25, count 2 2006.168.07:51:48.69#ibcon#wrote, iclass 25, count 2 2006.168.07:51:48.69#ibcon#about to read 3, iclass 25, count 2 2006.168.07:51:48.72#ibcon#read 3, iclass 25, count 2 2006.168.07:51:48.72#ibcon#about to read 4, iclass 25, count 2 2006.168.07:51:48.72#ibcon#read 4, iclass 25, count 2 2006.168.07:51:48.72#ibcon#about to read 5, iclass 25, count 2 2006.168.07:51:48.72#ibcon#read 5, iclass 25, count 2 2006.168.07:51:48.72#ibcon#about to read 6, iclass 25, count 2 2006.168.07:51:48.72#ibcon#read 6, iclass 25, count 2 2006.168.07:51:48.72#ibcon#end of sib2, iclass 25, count 2 2006.168.07:51:48.72#ibcon#*mode == 0, iclass 25, count 2 2006.168.07:51:48.72#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.168.07:51:48.72#ibcon#[25=AT03-06\r\n] 2006.168.07:51:48.72#ibcon#*before write, iclass 25, count 2 2006.168.07:51:48.72#ibcon#enter sib2, iclass 25, count 2 2006.168.07:51:48.72#ibcon#flushed, iclass 25, count 2 2006.168.07:51:48.72#ibcon#about to write, iclass 25, count 2 2006.168.07:51:48.72#ibcon#wrote, iclass 25, count 2 2006.168.07:51:48.72#ibcon#about to read 3, iclass 25, count 2 2006.168.07:51:48.75#ibcon#read 3, iclass 25, count 2 2006.168.07:51:48.75#ibcon#about to read 4, iclass 25, count 2 2006.168.07:51:48.75#ibcon#read 4, iclass 25, count 2 2006.168.07:51:48.75#ibcon#about to read 5, iclass 25, count 2 2006.168.07:51:48.75#ibcon#read 5, iclass 25, count 2 2006.168.07:51:48.75#ibcon#about to read 6, iclass 25, count 2 2006.168.07:51:48.75#ibcon#read 6, iclass 25, count 2 2006.168.07:51:48.75#ibcon#end of sib2, iclass 25, count 2 2006.168.07:51:48.75#ibcon#*after write, iclass 25, count 2 2006.168.07:51:48.75#ibcon#*before return 0, iclass 25, count 2 2006.168.07:51:48.75#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.168.07:51:48.75#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.168.07:51:48.75#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.168.07:51:48.75#ibcon#ireg 7 cls_cnt 0 2006.168.07:51:48.75#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.168.07:51:48.87#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.168.07:51:48.87#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.168.07:51:48.87#ibcon#enter wrdev, iclass 25, count 0 2006.168.07:51:48.87#ibcon#first serial, iclass 25, count 0 2006.168.07:51:48.87#ibcon#enter sib2, iclass 25, count 0 2006.168.07:51:48.87#ibcon#flushed, iclass 25, count 0 2006.168.07:51:48.87#ibcon#about to write, iclass 25, count 0 2006.168.07:51:48.87#ibcon#wrote, iclass 25, count 0 2006.168.07:51:48.87#ibcon#about to read 3, iclass 25, count 0 2006.168.07:51:48.89#ibcon#read 3, iclass 25, count 0 2006.168.07:51:48.89#ibcon#about to read 4, iclass 25, count 0 2006.168.07:51:48.89#ibcon#read 4, iclass 25, count 0 2006.168.07:51:48.89#ibcon#about to read 5, iclass 25, count 0 2006.168.07:51:48.89#ibcon#read 5, iclass 25, count 0 2006.168.07:51:48.89#ibcon#about to read 6, iclass 25, count 0 2006.168.07:51:48.89#ibcon#read 6, iclass 25, count 0 2006.168.07:51:48.89#ibcon#end of sib2, iclass 25, count 0 2006.168.07:51:48.89#ibcon#*mode == 0, iclass 25, count 0 2006.168.07:51:48.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.168.07:51:48.89#ibcon#[25=USB\r\n] 2006.168.07:51:48.89#ibcon#*before write, iclass 25, count 0 2006.168.07:51:48.89#ibcon#enter sib2, iclass 25, count 0 2006.168.07:51:48.89#ibcon#flushed, iclass 25, count 0 2006.168.07:51:48.89#ibcon#about to write, iclass 25, count 0 2006.168.07:51:48.89#ibcon#wrote, iclass 25, count 0 2006.168.07:51:48.89#ibcon#about to read 3, iclass 25, count 0 2006.168.07:51:48.92#ibcon#read 3, iclass 25, count 0 2006.168.07:51:48.92#ibcon#about to read 4, iclass 25, count 0 2006.168.07:51:48.92#ibcon#read 4, iclass 25, count 0 2006.168.07:51:48.92#ibcon#about to read 5, iclass 25, count 0 2006.168.07:51:48.92#ibcon#read 5, iclass 25, count 0 2006.168.07:51:48.92#ibcon#about to read 6, iclass 25, count 0 2006.168.07:51:48.92#ibcon#read 6, iclass 25, count 0 2006.168.07:51:48.92#ibcon#end of sib2, iclass 25, count 0 2006.168.07:51:48.92#ibcon#*after write, iclass 25, count 0 2006.168.07:51:48.92#ibcon#*before return 0, iclass 25, count 0 2006.168.07:51:48.92#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.168.07:51:48.92#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.168.07:51:48.92#ibcon#about to clear, iclass 25 cls_cnt 0 2006.168.07:51:48.92#ibcon#cleared, iclass 25 cls_cnt 0 2006.168.07:51:48.92$vc4f8/valo=4,832.99 2006.168.07:51:48.92#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.168.07:51:48.92#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.168.07:51:48.92#ibcon#ireg 17 cls_cnt 0 2006.168.07:51:48.92#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.168.07:51:48.92#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.168.07:51:48.92#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.168.07:51:48.92#ibcon#enter wrdev, iclass 27, count 0 2006.168.07:51:48.92#ibcon#first serial, iclass 27, count 0 2006.168.07:51:48.92#ibcon#enter sib2, iclass 27, count 0 2006.168.07:51:48.92#ibcon#flushed, iclass 27, count 0 2006.168.07:51:48.92#ibcon#about to write, iclass 27, count 0 2006.168.07:51:48.92#ibcon#wrote, iclass 27, count 0 2006.168.07:51:48.92#ibcon#about to read 3, iclass 27, count 0 2006.168.07:51:48.94#ibcon#read 3, iclass 27, count 0 2006.168.07:51:48.94#ibcon#about to read 4, iclass 27, count 0 2006.168.07:51:48.94#ibcon#read 4, iclass 27, count 0 2006.168.07:51:48.94#ibcon#about to read 5, iclass 27, count 0 2006.168.07:51:48.94#ibcon#read 5, iclass 27, count 0 2006.168.07:51:48.94#ibcon#about to read 6, iclass 27, count 0 2006.168.07:51:48.94#ibcon#read 6, iclass 27, count 0 2006.168.07:51:48.94#ibcon#end of sib2, iclass 27, count 0 2006.168.07:51:48.94#ibcon#*mode == 0, iclass 27, count 0 2006.168.07:51:48.94#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.168.07:51:48.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.07:51:48.94#ibcon#*before write, iclass 27, count 0 2006.168.07:51:48.94#ibcon#enter sib2, iclass 27, count 0 2006.168.07:51:48.94#ibcon#flushed, iclass 27, count 0 2006.168.07:51:48.94#ibcon#about to write, iclass 27, count 0 2006.168.07:51:48.94#ibcon#wrote, iclass 27, count 0 2006.168.07:51:48.94#ibcon#about to read 3, iclass 27, count 0 2006.168.07:51:48.98#ibcon#read 3, iclass 27, count 0 2006.168.07:51:48.98#ibcon#about to read 4, iclass 27, count 0 2006.168.07:51:48.98#ibcon#read 4, iclass 27, count 0 2006.168.07:51:48.98#ibcon#about to read 5, iclass 27, count 0 2006.168.07:51:48.98#ibcon#read 5, iclass 27, count 0 2006.168.07:51:48.98#ibcon#about to read 6, iclass 27, count 0 2006.168.07:51:48.98#ibcon#read 6, iclass 27, count 0 2006.168.07:51:48.98#ibcon#end of sib2, iclass 27, count 0 2006.168.07:51:48.98#ibcon#*after write, iclass 27, count 0 2006.168.07:51:48.98#ibcon#*before return 0, iclass 27, count 0 2006.168.07:51:48.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.168.07:51:48.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.168.07:51:48.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.168.07:51:48.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.168.07:51:48.98$vc4f8/va=4,7 2006.168.07:51:48.98#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.168.07:51:48.98#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.168.07:51:48.98#ibcon#ireg 11 cls_cnt 2 2006.168.07:51:48.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.168.07:51:49.04#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.168.07:51:49.04#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.168.07:51:49.04#ibcon#enter wrdev, iclass 29, count 2 2006.168.07:51:49.04#ibcon#first serial, iclass 29, count 2 2006.168.07:51:49.04#ibcon#enter sib2, iclass 29, count 2 2006.168.07:51:49.04#ibcon#flushed, iclass 29, count 2 2006.168.07:51:49.04#ibcon#about to write, iclass 29, count 2 2006.168.07:51:49.04#ibcon#wrote, iclass 29, count 2 2006.168.07:51:49.04#ibcon#about to read 3, iclass 29, count 2 2006.168.07:51:49.06#ibcon#read 3, iclass 29, count 2 2006.168.07:51:49.06#ibcon#about to read 4, iclass 29, count 2 2006.168.07:51:49.06#ibcon#read 4, iclass 29, count 2 2006.168.07:51:49.06#ibcon#about to read 5, iclass 29, count 2 2006.168.07:51:49.06#ibcon#read 5, iclass 29, count 2 2006.168.07:51:49.06#ibcon#about to read 6, iclass 29, count 2 2006.168.07:51:49.06#ibcon#read 6, iclass 29, count 2 2006.168.07:51:49.06#ibcon#end of sib2, iclass 29, count 2 2006.168.07:51:49.06#ibcon#*mode == 0, iclass 29, count 2 2006.168.07:51:49.06#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.168.07:51:49.06#ibcon#[25=AT04-07\r\n] 2006.168.07:51:49.06#ibcon#*before write, iclass 29, count 2 2006.168.07:51:49.06#ibcon#enter sib2, iclass 29, count 2 2006.168.07:51:49.06#ibcon#flushed, iclass 29, count 2 2006.168.07:51:49.06#ibcon#about to write, iclass 29, count 2 2006.168.07:51:49.06#ibcon#wrote, iclass 29, count 2 2006.168.07:51:49.06#ibcon#about to read 3, iclass 29, count 2 2006.168.07:51:49.09#ibcon#read 3, iclass 29, count 2 2006.168.07:51:49.09#ibcon#about to read 4, iclass 29, count 2 2006.168.07:51:49.09#ibcon#read 4, iclass 29, count 2 2006.168.07:51:49.09#ibcon#about to read 5, iclass 29, count 2 2006.168.07:51:49.09#ibcon#read 5, iclass 29, count 2 2006.168.07:51:49.09#ibcon#about to read 6, iclass 29, count 2 2006.168.07:51:49.09#ibcon#read 6, iclass 29, count 2 2006.168.07:51:49.09#ibcon#end of sib2, iclass 29, count 2 2006.168.07:51:49.09#ibcon#*after write, iclass 29, count 2 2006.168.07:51:49.09#ibcon#*before return 0, iclass 29, count 2 2006.168.07:51:49.09#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.168.07:51:49.09#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.168.07:51:49.09#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.168.07:51:49.09#ibcon#ireg 7 cls_cnt 0 2006.168.07:51:49.09#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.168.07:51:49.21#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.168.07:51:49.21#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.168.07:51:49.21#ibcon#enter wrdev, iclass 29, count 0 2006.168.07:51:49.21#ibcon#first serial, iclass 29, count 0 2006.168.07:51:49.21#ibcon#enter sib2, iclass 29, count 0 2006.168.07:51:49.21#ibcon#flushed, iclass 29, count 0 2006.168.07:51:49.21#ibcon#about to write, iclass 29, count 0 2006.168.07:51:49.21#ibcon#wrote, iclass 29, count 0 2006.168.07:51:49.21#ibcon#about to read 3, iclass 29, count 0 2006.168.07:51:49.25#ibcon#read 3, iclass 29, count 0 2006.168.07:51:49.25#ibcon#about to read 4, iclass 29, count 0 2006.168.07:51:49.25#ibcon#read 4, iclass 29, count 0 2006.168.07:51:49.25#ibcon#about to read 5, iclass 29, count 0 2006.168.07:51:49.25#ibcon#read 5, iclass 29, count 0 2006.168.07:51:49.25#ibcon#about to read 6, iclass 29, count 0 2006.168.07:51:49.25#ibcon#read 6, iclass 29, count 0 2006.168.07:51:49.25#ibcon#end of sib2, iclass 29, count 0 2006.168.07:51:49.25#ibcon#*mode == 0, iclass 29, count 0 2006.168.07:51:49.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.168.07:51:49.25#ibcon#[25=USB\r\n] 2006.168.07:51:49.25#ibcon#*before write, iclass 29, count 0 2006.168.07:51:49.25#ibcon#enter sib2, iclass 29, count 0 2006.168.07:51:49.25#ibcon#flushed, iclass 29, count 0 2006.168.07:51:49.25#ibcon#about to write, iclass 29, count 0 2006.168.07:51:49.25#ibcon#wrote, iclass 29, count 0 2006.168.07:51:49.25#ibcon#about to read 3, iclass 29, count 0 2006.168.07:51:49.28#ibcon#read 3, iclass 29, count 0 2006.168.07:51:49.28#ibcon#about to read 4, iclass 29, count 0 2006.168.07:51:49.28#ibcon#read 4, iclass 29, count 0 2006.168.07:51:49.28#ibcon#about to read 5, iclass 29, count 0 2006.168.07:51:49.28#ibcon#read 5, iclass 29, count 0 2006.168.07:51:49.28#ibcon#about to read 6, iclass 29, count 0 2006.168.07:51:49.28#ibcon#read 6, iclass 29, count 0 2006.168.07:51:49.28#ibcon#end of sib2, iclass 29, count 0 2006.168.07:51:49.28#ibcon#*after write, iclass 29, count 0 2006.168.07:51:49.28#ibcon#*before return 0, iclass 29, count 0 2006.168.07:51:49.28#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.168.07:51:49.28#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.168.07:51:49.28#ibcon#about to clear, iclass 29 cls_cnt 0 2006.168.07:51:49.28#ibcon#cleared, iclass 29 cls_cnt 0 2006.168.07:51:49.28$vc4f8/valo=5,652.99 2006.168.07:51:49.28#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.168.07:51:49.28#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.168.07:51:49.28#ibcon#ireg 17 cls_cnt 0 2006.168.07:51:49.28#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:51:49.28#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:51:49.28#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:51:49.28#ibcon#enter wrdev, iclass 31, count 0 2006.168.07:51:49.28#ibcon#first serial, iclass 31, count 0 2006.168.07:51:49.28#ibcon#enter sib2, iclass 31, count 0 2006.168.07:51:49.28#ibcon#flushed, iclass 31, count 0 2006.168.07:51:49.28#ibcon#about to write, iclass 31, count 0 2006.168.07:51:49.28#ibcon#wrote, iclass 31, count 0 2006.168.07:51:49.28#ibcon#about to read 3, iclass 31, count 0 2006.168.07:51:49.31#ibcon#read 3, iclass 31, count 0 2006.168.07:51:49.31#ibcon#about to read 4, iclass 31, count 0 2006.168.07:51:49.31#ibcon#read 4, iclass 31, count 0 2006.168.07:51:49.31#ibcon#about to read 5, iclass 31, count 0 2006.168.07:51:49.31#ibcon#read 5, iclass 31, count 0 2006.168.07:51:49.31#ibcon#about to read 6, iclass 31, count 0 2006.168.07:51:49.31#ibcon#read 6, iclass 31, count 0 2006.168.07:51:49.31#ibcon#end of sib2, iclass 31, count 0 2006.168.07:51:49.31#ibcon#*mode == 0, iclass 31, count 0 2006.168.07:51:49.31#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.168.07:51:49.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.07:51:49.31#ibcon#*before write, iclass 31, count 0 2006.168.07:51:49.31#ibcon#enter sib2, iclass 31, count 0 2006.168.07:51:49.31#ibcon#flushed, iclass 31, count 0 2006.168.07:51:49.31#ibcon#about to write, iclass 31, count 0 2006.168.07:51:49.31#ibcon#wrote, iclass 31, count 0 2006.168.07:51:49.31#ibcon#about to read 3, iclass 31, count 0 2006.168.07:51:49.35#ibcon#read 3, iclass 31, count 0 2006.168.07:51:49.35#ibcon#about to read 4, iclass 31, count 0 2006.168.07:51:49.35#ibcon#read 4, iclass 31, count 0 2006.168.07:51:49.35#ibcon#about to read 5, iclass 31, count 0 2006.168.07:51:49.35#ibcon#read 5, iclass 31, count 0 2006.168.07:51:49.35#ibcon#about to read 6, iclass 31, count 0 2006.168.07:51:49.35#ibcon#read 6, iclass 31, count 0 2006.168.07:51:49.35#ibcon#end of sib2, iclass 31, count 0 2006.168.07:51:49.35#ibcon#*after write, iclass 31, count 0 2006.168.07:51:49.35#ibcon#*before return 0, iclass 31, count 0 2006.168.07:51:49.35#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:51:49.35#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:51:49.35#ibcon#about to clear, iclass 31 cls_cnt 0 2006.168.07:51:49.35#ibcon#cleared, iclass 31 cls_cnt 0 2006.168.07:51:49.35$vc4f8/va=5,7 2006.168.07:51:49.35#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.168.07:51:49.35#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.168.07:51:49.35#ibcon#ireg 11 cls_cnt 2 2006.168.07:51:49.35#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:51:49.39#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:51:49.39#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:51:49.39#ibcon#enter wrdev, iclass 33, count 2 2006.168.07:51:49.39#ibcon#first serial, iclass 33, count 2 2006.168.07:51:49.39#ibcon#enter sib2, iclass 33, count 2 2006.168.07:51:49.39#ibcon#flushed, iclass 33, count 2 2006.168.07:51:49.39#ibcon#about to write, iclass 33, count 2 2006.168.07:51:49.39#ibcon#wrote, iclass 33, count 2 2006.168.07:51:49.39#ibcon#about to read 3, iclass 33, count 2 2006.168.07:51:49.41#ibcon#read 3, iclass 33, count 2 2006.168.07:51:49.41#ibcon#about to read 4, iclass 33, count 2 2006.168.07:51:49.41#ibcon#read 4, iclass 33, count 2 2006.168.07:51:49.41#ibcon#about to read 5, iclass 33, count 2 2006.168.07:51:49.41#ibcon#read 5, iclass 33, count 2 2006.168.07:51:49.41#ibcon#about to read 6, iclass 33, count 2 2006.168.07:51:49.41#ibcon#read 6, iclass 33, count 2 2006.168.07:51:49.41#ibcon#end of sib2, iclass 33, count 2 2006.168.07:51:49.41#ibcon#*mode == 0, iclass 33, count 2 2006.168.07:51:49.41#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.168.07:51:49.41#ibcon#[25=AT05-07\r\n] 2006.168.07:51:49.41#ibcon#*before write, iclass 33, count 2 2006.168.07:51:49.41#ibcon#enter sib2, iclass 33, count 2 2006.168.07:51:49.41#ibcon#flushed, iclass 33, count 2 2006.168.07:51:49.41#ibcon#about to write, iclass 33, count 2 2006.168.07:51:49.41#ibcon#wrote, iclass 33, count 2 2006.168.07:51:49.41#ibcon#about to read 3, iclass 33, count 2 2006.168.07:51:49.44#ibcon#read 3, iclass 33, count 2 2006.168.07:51:49.44#ibcon#about to read 4, iclass 33, count 2 2006.168.07:51:49.44#ibcon#read 4, iclass 33, count 2 2006.168.07:51:49.44#ibcon#about to read 5, iclass 33, count 2 2006.168.07:51:49.44#ibcon#read 5, iclass 33, count 2 2006.168.07:51:49.44#ibcon#about to read 6, iclass 33, count 2 2006.168.07:51:49.44#ibcon#read 6, iclass 33, count 2 2006.168.07:51:49.44#ibcon#end of sib2, iclass 33, count 2 2006.168.07:51:49.44#ibcon#*after write, iclass 33, count 2 2006.168.07:51:49.44#ibcon#*before return 0, iclass 33, count 2 2006.168.07:51:49.44#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:51:49.44#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:51:49.44#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.168.07:51:49.44#ibcon#ireg 7 cls_cnt 0 2006.168.07:51:49.44#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:51:49.56#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:51:49.56#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:51:49.56#ibcon#enter wrdev, iclass 33, count 0 2006.168.07:51:49.56#ibcon#first serial, iclass 33, count 0 2006.168.07:51:49.56#ibcon#enter sib2, iclass 33, count 0 2006.168.07:51:49.56#ibcon#flushed, iclass 33, count 0 2006.168.07:51:49.56#ibcon#about to write, iclass 33, count 0 2006.168.07:51:49.56#ibcon#wrote, iclass 33, count 0 2006.168.07:51:49.56#ibcon#about to read 3, iclass 33, count 0 2006.168.07:51:49.58#ibcon#read 3, iclass 33, count 0 2006.168.07:51:49.58#ibcon#about to read 4, iclass 33, count 0 2006.168.07:51:49.58#ibcon#read 4, iclass 33, count 0 2006.168.07:51:49.58#ibcon#about to read 5, iclass 33, count 0 2006.168.07:51:49.58#ibcon#read 5, iclass 33, count 0 2006.168.07:51:49.58#ibcon#about to read 6, iclass 33, count 0 2006.168.07:51:49.58#ibcon#read 6, iclass 33, count 0 2006.168.07:51:49.58#ibcon#end of sib2, iclass 33, count 0 2006.168.07:51:49.58#ibcon#*mode == 0, iclass 33, count 0 2006.168.07:51:49.58#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.168.07:51:49.58#ibcon#[25=USB\r\n] 2006.168.07:51:49.58#ibcon#*before write, iclass 33, count 0 2006.168.07:51:49.58#ibcon#enter sib2, iclass 33, count 0 2006.168.07:51:49.58#ibcon#flushed, iclass 33, count 0 2006.168.07:51:49.58#ibcon#about to write, iclass 33, count 0 2006.168.07:51:49.58#ibcon#wrote, iclass 33, count 0 2006.168.07:51:49.58#ibcon#about to read 3, iclass 33, count 0 2006.168.07:51:49.61#ibcon#read 3, iclass 33, count 0 2006.168.07:51:49.61#ibcon#about to read 4, iclass 33, count 0 2006.168.07:51:49.61#ibcon#read 4, iclass 33, count 0 2006.168.07:51:49.61#ibcon#about to read 5, iclass 33, count 0 2006.168.07:51:49.61#ibcon#read 5, iclass 33, count 0 2006.168.07:51:49.61#ibcon#about to read 6, iclass 33, count 0 2006.168.07:51:49.61#ibcon#read 6, iclass 33, count 0 2006.168.07:51:49.61#ibcon#end of sib2, iclass 33, count 0 2006.168.07:51:49.61#ibcon#*after write, iclass 33, count 0 2006.168.07:51:49.61#ibcon#*before return 0, iclass 33, count 0 2006.168.07:51:49.61#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:51:49.61#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:51:49.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.168.07:51:49.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.168.07:51:49.61$vc4f8/valo=6,772.99 2006.168.07:51:49.61#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.168.07:51:49.61#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.168.07:51:49.61#ibcon#ireg 17 cls_cnt 0 2006.168.07:51:49.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:51:49.61#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:51:49.61#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:51:49.61#ibcon#enter wrdev, iclass 35, count 0 2006.168.07:51:49.61#ibcon#first serial, iclass 35, count 0 2006.168.07:51:49.61#ibcon#enter sib2, iclass 35, count 0 2006.168.07:51:49.61#ibcon#flushed, iclass 35, count 0 2006.168.07:51:49.61#ibcon#about to write, iclass 35, count 0 2006.168.07:51:49.61#ibcon#wrote, iclass 35, count 0 2006.168.07:51:49.61#ibcon#about to read 3, iclass 35, count 0 2006.168.07:51:49.63#ibcon#read 3, iclass 35, count 0 2006.168.07:51:49.63#ibcon#about to read 4, iclass 35, count 0 2006.168.07:51:49.63#ibcon#read 4, iclass 35, count 0 2006.168.07:51:49.63#ibcon#about to read 5, iclass 35, count 0 2006.168.07:51:49.63#ibcon#read 5, iclass 35, count 0 2006.168.07:51:49.63#ibcon#about to read 6, iclass 35, count 0 2006.168.07:51:49.63#ibcon#read 6, iclass 35, count 0 2006.168.07:51:49.63#ibcon#end of sib2, iclass 35, count 0 2006.168.07:51:49.63#ibcon#*mode == 0, iclass 35, count 0 2006.168.07:51:49.63#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.168.07:51:49.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.07:51:49.63#ibcon#*before write, iclass 35, count 0 2006.168.07:51:49.63#ibcon#enter sib2, iclass 35, count 0 2006.168.07:51:49.63#ibcon#flushed, iclass 35, count 0 2006.168.07:51:49.63#ibcon#about to write, iclass 35, count 0 2006.168.07:51:49.63#ibcon#wrote, iclass 35, count 0 2006.168.07:51:49.63#ibcon#about to read 3, iclass 35, count 0 2006.168.07:51:49.67#ibcon#read 3, iclass 35, count 0 2006.168.07:51:49.67#ibcon#about to read 4, iclass 35, count 0 2006.168.07:51:49.67#ibcon#read 4, iclass 35, count 0 2006.168.07:51:49.67#ibcon#about to read 5, iclass 35, count 0 2006.168.07:51:49.67#ibcon#read 5, iclass 35, count 0 2006.168.07:51:49.67#ibcon#about to read 6, iclass 35, count 0 2006.168.07:51:49.67#ibcon#read 6, iclass 35, count 0 2006.168.07:51:49.67#ibcon#end of sib2, iclass 35, count 0 2006.168.07:51:49.67#ibcon#*after write, iclass 35, count 0 2006.168.07:51:49.67#ibcon#*before return 0, iclass 35, count 0 2006.168.07:51:49.67#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:51:49.67#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:51:49.67#ibcon#about to clear, iclass 35 cls_cnt 0 2006.168.07:51:49.67#ibcon#cleared, iclass 35 cls_cnt 0 2006.168.07:51:49.67$vc4f8/va=6,6 2006.168.07:51:49.67#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.168.07:51:49.67#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.168.07:51:49.67#ibcon#ireg 11 cls_cnt 2 2006.168.07:51:49.67#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:51:49.73#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:51:49.73#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:51:49.73#ibcon#enter wrdev, iclass 37, count 2 2006.168.07:51:49.73#ibcon#first serial, iclass 37, count 2 2006.168.07:51:49.73#ibcon#enter sib2, iclass 37, count 2 2006.168.07:51:49.73#ibcon#flushed, iclass 37, count 2 2006.168.07:51:49.73#ibcon#about to write, iclass 37, count 2 2006.168.07:51:49.73#ibcon#wrote, iclass 37, count 2 2006.168.07:51:49.73#ibcon#about to read 3, iclass 37, count 2 2006.168.07:51:49.75#ibcon#read 3, iclass 37, count 2 2006.168.07:51:49.75#ibcon#about to read 4, iclass 37, count 2 2006.168.07:51:49.75#ibcon#read 4, iclass 37, count 2 2006.168.07:51:49.75#ibcon#about to read 5, iclass 37, count 2 2006.168.07:51:49.75#ibcon#read 5, iclass 37, count 2 2006.168.07:51:49.75#ibcon#about to read 6, iclass 37, count 2 2006.168.07:51:49.75#ibcon#read 6, iclass 37, count 2 2006.168.07:51:49.75#ibcon#end of sib2, iclass 37, count 2 2006.168.07:51:49.75#ibcon#*mode == 0, iclass 37, count 2 2006.168.07:51:49.75#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.168.07:51:49.75#ibcon#[25=AT06-06\r\n] 2006.168.07:51:49.75#ibcon#*before write, iclass 37, count 2 2006.168.07:51:49.75#ibcon#enter sib2, iclass 37, count 2 2006.168.07:51:49.75#ibcon#flushed, iclass 37, count 2 2006.168.07:51:49.75#ibcon#about to write, iclass 37, count 2 2006.168.07:51:49.75#ibcon#wrote, iclass 37, count 2 2006.168.07:51:49.75#ibcon#about to read 3, iclass 37, count 2 2006.168.07:51:49.78#ibcon#read 3, iclass 37, count 2 2006.168.07:51:49.78#ibcon#about to read 4, iclass 37, count 2 2006.168.07:51:49.78#ibcon#read 4, iclass 37, count 2 2006.168.07:51:49.78#ibcon#about to read 5, iclass 37, count 2 2006.168.07:51:49.78#ibcon#read 5, iclass 37, count 2 2006.168.07:51:49.78#ibcon#about to read 6, iclass 37, count 2 2006.168.07:51:49.78#ibcon#read 6, iclass 37, count 2 2006.168.07:51:49.78#ibcon#end of sib2, iclass 37, count 2 2006.168.07:51:49.78#ibcon#*after write, iclass 37, count 2 2006.168.07:51:49.78#ibcon#*before return 0, iclass 37, count 2 2006.168.07:51:49.78#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:51:49.78#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:51:49.78#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.168.07:51:49.78#ibcon#ireg 7 cls_cnt 0 2006.168.07:51:49.78#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:51:49.83#abcon#<5=/08 1.7 5.4 27.34 731004.6\r\n> 2006.168.07:51:49.85#abcon#{5=INTERFACE CLEAR} 2006.168.07:51:49.90#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:51:49.90#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:51:49.90#ibcon#enter wrdev, iclass 37, count 0 2006.168.07:51:49.90#ibcon#first serial, iclass 37, count 0 2006.168.07:51:49.90#ibcon#enter sib2, iclass 37, count 0 2006.168.07:51:49.90#ibcon#flushed, iclass 37, count 0 2006.168.07:51:49.90#ibcon#about to write, iclass 37, count 0 2006.168.07:51:49.90#ibcon#wrote, iclass 37, count 0 2006.168.07:51:49.90#ibcon#about to read 3, iclass 37, count 0 2006.168.07:51:49.91#abcon#[5=S1D000X0/0*\r\n] 2006.168.07:51:49.92#ibcon#read 3, iclass 37, count 0 2006.168.07:51:49.92#ibcon#about to read 4, iclass 37, count 0 2006.168.07:51:49.92#ibcon#read 4, iclass 37, count 0 2006.168.07:51:49.92#ibcon#about to read 5, iclass 37, count 0 2006.168.07:51:49.92#ibcon#read 5, iclass 37, count 0 2006.168.07:51:49.92#ibcon#about to read 6, iclass 37, count 0 2006.168.07:51:49.92#ibcon#read 6, iclass 37, count 0 2006.168.07:51:49.92#ibcon#end of sib2, iclass 37, count 0 2006.168.07:51:49.92#ibcon#*mode == 0, iclass 37, count 0 2006.168.07:51:49.92#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.168.07:51:49.92#ibcon#[25=USB\r\n] 2006.168.07:51:49.92#ibcon#*before write, iclass 37, count 0 2006.168.07:51:49.92#ibcon#enter sib2, iclass 37, count 0 2006.168.07:51:49.92#ibcon#flushed, iclass 37, count 0 2006.168.07:51:49.92#ibcon#about to write, iclass 37, count 0 2006.168.07:51:49.92#ibcon#wrote, iclass 37, count 0 2006.168.07:51:49.92#ibcon#about to read 3, iclass 37, count 0 2006.168.07:51:49.95#ibcon#read 3, iclass 37, count 0 2006.168.07:51:49.95#ibcon#about to read 4, iclass 37, count 0 2006.168.07:51:49.95#ibcon#read 4, iclass 37, count 0 2006.168.07:51:49.95#ibcon#about to read 5, iclass 37, count 0 2006.168.07:51:49.95#ibcon#read 5, iclass 37, count 0 2006.168.07:51:49.95#ibcon#about to read 6, iclass 37, count 0 2006.168.07:51:49.95#ibcon#read 6, iclass 37, count 0 2006.168.07:51:49.95#ibcon#end of sib2, iclass 37, count 0 2006.168.07:51:49.95#ibcon#*after write, iclass 37, count 0 2006.168.07:51:49.95#ibcon#*before return 0, iclass 37, count 0 2006.168.07:51:49.95#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:51:49.95#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:51:49.95#ibcon#about to clear, iclass 37 cls_cnt 0 2006.168.07:51:49.95#ibcon#cleared, iclass 37 cls_cnt 0 2006.168.07:51:49.95$vc4f8/valo=7,832.99 2006.168.07:51:49.95#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.168.07:51:49.95#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.168.07:51:49.95#ibcon#ireg 17 cls_cnt 0 2006.168.07:51:49.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.168.07:51:49.95#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.168.07:51:49.95#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.168.07:51:49.95#ibcon#enter wrdev, iclass 5, count 0 2006.168.07:51:49.95#ibcon#first serial, iclass 5, count 0 2006.168.07:51:49.95#ibcon#enter sib2, iclass 5, count 0 2006.168.07:51:49.95#ibcon#flushed, iclass 5, count 0 2006.168.07:51:49.95#ibcon#about to write, iclass 5, count 0 2006.168.07:51:49.95#ibcon#wrote, iclass 5, count 0 2006.168.07:51:49.95#ibcon#about to read 3, iclass 5, count 0 2006.168.07:51:49.97#ibcon#read 3, iclass 5, count 0 2006.168.07:51:49.97#ibcon#about to read 4, iclass 5, count 0 2006.168.07:51:49.97#ibcon#read 4, iclass 5, count 0 2006.168.07:51:49.97#ibcon#about to read 5, iclass 5, count 0 2006.168.07:51:49.97#ibcon#read 5, iclass 5, count 0 2006.168.07:51:49.97#ibcon#about to read 6, iclass 5, count 0 2006.168.07:51:49.97#ibcon#read 6, iclass 5, count 0 2006.168.07:51:49.97#ibcon#end of sib2, iclass 5, count 0 2006.168.07:51:49.97#ibcon#*mode == 0, iclass 5, count 0 2006.168.07:51:49.97#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.168.07:51:49.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.07:51:49.97#ibcon#*before write, iclass 5, count 0 2006.168.07:51:49.97#ibcon#enter sib2, iclass 5, count 0 2006.168.07:51:49.97#ibcon#flushed, iclass 5, count 0 2006.168.07:51:49.97#ibcon#about to write, iclass 5, count 0 2006.168.07:51:49.97#ibcon#wrote, iclass 5, count 0 2006.168.07:51:49.97#ibcon#about to read 3, iclass 5, count 0 2006.168.07:51:50.01#ibcon#read 3, iclass 5, count 0 2006.168.07:51:50.01#ibcon#about to read 4, iclass 5, count 0 2006.168.07:51:50.01#ibcon#read 4, iclass 5, count 0 2006.168.07:51:50.01#ibcon#about to read 5, iclass 5, count 0 2006.168.07:51:50.01#ibcon#read 5, iclass 5, count 0 2006.168.07:51:50.01#ibcon#about to read 6, iclass 5, count 0 2006.168.07:51:50.01#ibcon#read 6, iclass 5, count 0 2006.168.07:51:50.01#ibcon#end of sib2, iclass 5, count 0 2006.168.07:51:50.01#ibcon#*after write, iclass 5, count 0 2006.168.07:51:50.01#ibcon#*before return 0, iclass 5, count 0 2006.168.07:51:50.01#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.168.07:51:50.01#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.168.07:51:50.01#ibcon#about to clear, iclass 5 cls_cnt 0 2006.168.07:51:50.01#ibcon#cleared, iclass 5 cls_cnt 0 2006.168.07:51:50.01$vc4f8/va=7,6 2006.168.07:51:50.01#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.168.07:51:50.01#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.168.07:51:50.01#ibcon#ireg 11 cls_cnt 2 2006.168.07:51:50.01#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.168.07:51:50.07#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.168.07:51:50.07#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.168.07:51:50.07#ibcon#enter wrdev, iclass 7, count 2 2006.168.07:51:50.07#ibcon#first serial, iclass 7, count 2 2006.168.07:51:50.07#ibcon#enter sib2, iclass 7, count 2 2006.168.07:51:50.07#ibcon#flushed, iclass 7, count 2 2006.168.07:51:50.07#ibcon#about to write, iclass 7, count 2 2006.168.07:51:50.07#ibcon#wrote, iclass 7, count 2 2006.168.07:51:50.07#ibcon#about to read 3, iclass 7, count 2 2006.168.07:51:50.09#ibcon#read 3, iclass 7, count 2 2006.168.07:51:50.09#ibcon#about to read 4, iclass 7, count 2 2006.168.07:51:50.09#ibcon#read 4, iclass 7, count 2 2006.168.07:51:50.09#ibcon#about to read 5, iclass 7, count 2 2006.168.07:51:50.09#ibcon#read 5, iclass 7, count 2 2006.168.07:51:50.09#ibcon#about to read 6, iclass 7, count 2 2006.168.07:51:50.09#ibcon#read 6, iclass 7, count 2 2006.168.07:51:50.09#ibcon#end of sib2, iclass 7, count 2 2006.168.07:51:50.09#ibcon#*mode == 0, iclass 7, count 2 2006.168.07:51:50.09#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.168.07:51:50.09#ibcon#[25=AT07-06\r\n] 2006.168.07:51:50.09#ibcon#*before write, iclass 7, count 2 2006.168.07:51:50.09#ibcon#enter sib2, iclass 7, count 2 2006.168.07:51:50.09#ibcon#flushed, iclass 7, count 2 2006.168.07:51:50.09#ibcon#about to write, iclass 7, count 2 2006.168.07:51:50.09#ibcon#wrote, iclass 7, count 2 2006.168.07:51:50.09#ibcon#about to read 3, iclass 7, count 2 2006.168.07:51:50.12#ibcon#read 3, iclass 7, count 2 2006.168.07:51:50.12#ibcon#about to read 4, iclass 7, count 2 2006.168.07:51:50.12#ibcon#read 4, iclass 7, count 2 2006.168.07:51:50.12#ibcon#about to read 5, iclass 7, count 2 2006.168.07:51:50.12#ibcon#read 5, iclass 7, count 2 2006.168.07:51:50.12#ibcon#about to read 6, iclass 7, count 2 2006.168.07:51:50.12#ibcon#read 6, iclass 7, count 2 2006.168.07:51:50.12#ibcon#end of sib2, iclass 7, count 2 2006.168.07:51:50.12#ibcon#*after write, iclass 7, count 2 2006.168.07:51:50.12#ibcon#*before return 0, iclass 7, count 2 2006.168.07:51:50.12#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.168.07:51:50.12#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.168.07:51:50.12#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.168.07:51:50.12#ibcon#ireg 7 cls_cnt 0 2006.168.07:51:50.12#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.168.07:51:50.24#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.168.07:51:50.24#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.168.07:51:50.24#ibcon#enter wrdev, iclass 7, count 0 2006.168.07:51:50.24#ibcon#first serial, iclass 7, count 0 2006.168.07:51:50.24#ibcon#enter sib2, iclass 7, count 0 2006.168.07:51:50.24#ibcon#flushed, iclass 7, count 0 2006.168.07:51:50.24#ibcon#about to write, iclass 7, count 0 2006.168.07:51:50.24#ibcon#wrote, iclass 7, count 0 2006.168.07:51:50.24#ibcon#about to read 3, iclass 7, count 0 2006.168.07:51:50.26#ibcon#read 3, iclass 7, count 0 2006.168.07:51:50.26#ibcon#about to read 4, iclass 7, count 0 2006.168.07:51:50.26#ibcon#read 4, iclass 7, count 0 2006.168.07:51:50.26#ibcon#about to read 5, iclass 7, count 0 2006.168.07:51:50.26#ibcon#read 5, iclass 7, count 0 2006.168.07:51:50.26#ibcon#about to read 6, iclass 7, count 0 2006.168.07:51:50.26#ibcon#read 6, iclass 7, count 0 2006.168.07:51:50.26#ibcon#end of sib2, iclass 7, count 0 2006.168.07:51:50.26#ibcon#*mode == 0, iclass 7, count 0 2006.168.07:51:50.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.168.07:51:50.26#ibcon#[25=USB\r\n] 2006.168.07:51:50.26#ibcon#*before write, iclass 7, count 0 2006.168.07:51:50.26#ibcon#enter sib2, iclass 7, count 0 2006.168.07:51:50.26#ibcon#flushed, iclass 7, count 0 2006.168.07:51:50.26#ibcon#about to write, iclass 7, count 0 2006.168.07:51:50.26#ibcon#wrote, iclass 7, count 0 2006.168.07:51:50.26#ibcon#about to read 3, iclass 7, count 0 2006.168.07:51:50.29#ibcon#read 3, iclass 7, count 0 2006.168.07:51:50.29#ibcon#about to read 4, iclass 7, count 0 2006.168.07:51:50.29#ibcon#read 4, iclass 7, count 0 2006.168.07:51:50.29#ibcon#about to read 5, iclass 7, count 0 2006.168.07:51:50.29#ibcon#read 5, iclass 7, count 0 2006.168.07:51:50.29#ibcon#about to read 6, iclass 7, count 0 2006.168.07:51:50.29#ibcon#read 6, iclass 7, count 0 2006.168.07:51:50.29#ibcon#end of sib2, iclass 7, count 0 2006.168.07:51:50.29#ibcon#*after write, iclass 7, count 0 2006.168.07:51:50.29#ibcon#*before return 0, iclass 7, count 0 2006.168.07:51:50.29#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.168.07:51:50.29#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.168.07:51:50.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.168.07:51:50.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.168.07:51:50.29$vc4f8/valo=8,852.99 2006.168.07:51:50.29#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.168.07:51:50.29#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.168.07:51:50.29#ibcon#ireg 17 cls_cnt 0 2006.168.07:51:50.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.168.07:51:50.29#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.168.07:51:50.29#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.168.07:51:50.29#ibcon#enter wrdev, iclass 11, count 0 2006.168.07:51:50.29#ibcon#first serial, iclass 11, count 0 2006.168.07:51:50.29#ibcon#enter sib2, iclass 11, count 0 2006.168.07:51:50.29#ibcon#flushed, iclass 11, count 0 2006.168.07:51:50.29#ibcon#about to write, iclass 11, count 0 2006.168.07:51:50.29#ibcon#wrote, iclass 11, count 0 2006.168.07:51:50.29#ibcon#about to read 3, iclass 11, count 0 2006.168.07:51:50.31#ibcon#read 3, iclass 11, count 0 2006.168.07:51:50.31#ibcon#about to read 4, iclass 11, count 0 2006.168.07:51:50.31#ibcon#read 4, iclass 11, count 0 2006.168.07:51:50.31#ibcon#about to read 5, iclass 11, count 0 2006.168.07:51:50.31#ibcon#read 5, iclass 11, count 0 2006.168.07:51:50.31#ibcon#about to read 6, iclass 11, count 0 2006.168.07:51:50.31#ibcon#read 6, iclass 11, count 0 2006.168.07:51:50.31#ibcon#end of sib2, iclass 11, count 0 2006.168.07:51:50.31#ibcon#*mode == 0, iclass 11, count 0 2006.168.07:51:50.31#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.168.07:51:50.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.07:51:50.31#ibcon#*before write, iclass 11, count 0 2006.168.07:51:50.31#ibcon#enter sib2, iclass 11, count 0 2006.168.07:51:50.31#ibcon#flushed, iclass 11, count 0 2006.168.07:51:50.31#ibcon#about to write, iclass 11, count 0 2006.168.07:51:50.31#ibcon#wrote, iclass 11, count 0 2006.168.07:51:50.31#ibcon#about to read 3, iclass 11, count 0 2006.168.07:51:50.35#ibcon#read 3, iclass 11, count 0 2006.168.07:51:50.35#ibcon#about to read 4, iclass 11, count 0 2006.168.07:51:50.35#ibcon#read 4, iclass 11, count 0 2006.168.07:51:50.35#ibcon#about to read 5, iclass 11, count 0 2006.168.07:51:50.35#ibcon#read 5, iclass 11, count 0 2006.168.07:51:50.35#ibcon#about to read 6, iclass 11, count 0 2006.168.07:51:50.35#ibcon#read 6, iclass 11, count 0 2006.168.07:51:50.35#ibcon#end of sib2, iclass 11, count 0 2006.168.07:51:50.35#ibcon#*after write, iclass 11, count 0 2006.168.07:51:50.35#ibcon#*before return 0, iclass 11, count 0 2006.168.07:51:50.35#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.168.07:51:50.35#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.168.07:51:50.35#ibcon#about to clear, iclass 11 cls_cnt 0 2006.168.07:51:50.35#ibcon#cleared, iclass 11 cls_cnt 0 2006.168.07:51:50.35$vc4f8/va=8,7 2006.168.07:51:50.35#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.168.07:51:50.35#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.168.07:51:50.35#ibcon#ireg 11 cls_cnt 2 2006.168.07:51:50.35#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.168.07:51:50.41#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.168.07:51:50.41#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.168.07:51:50.41#ibcon#enter wrdev, iclass 13, count 2 2006.168.07:51:50.41#ibcon#first serial, iclass 13, count 2 2006.168.07:51:50.41#ibcon#enter sib2, iclass 13, count 2 2006.168.07:51:50.41#ibcon#flushed, iclass 13, count 2 2006.168.07:51:50.41#ibcon#about to write, iclass 13, count 2 2006.168.07:51:50.41#ibcon#wrote, iclass 13, count 2 2006.168.07:51:50.41#ibcon#about to read 3, iclass 13, count 2 2006.168.07:51:50.43#ibcon#read 3, iclass 13, count 2 2006.168.07:51:50.43#ibcon#about to read 4, iclass 13, count 2 2006.168.07:51:50.43#ibcon#read 4, iclass 13, count 2 2006.168.07:51:50.43#ibcon#about to read 5, iclass 13, count 2 2006.168.07:51:50.43#ibcon#read 5, iclass 13, count 2 2006.168.07:51:50.43#ibcon#about to read 6, iclass 13, count 2 2006.168.07:51:50.43#ibcon#read 6, iclass 13, count 2 2006.168.07:51:50.43#ibcon#end of sib2, iclass 13, count 2 2006.168.07:51:50.43#ibcon#*mode == 0, iclass 13, count 2 2006.168.07:51:50.43#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.168.07:51:50.43#ibcon#[25=AT08-07\r\n] 2006.168.07:51:50.43#ibcon#*before write, iclass 13, count 2 2006.168.07:51:50.43#ibcon#enter sib2, iclass 13, count 2 2006.168.07:51:50.43#ibcon#flushed, iclass 13, count 2 2006.168.07:51:50.43#ibcon#about to write, iclass 13, count 2 2006.168.07:51:50.43#ibcon#wrote, iclass 13, count 2 2006.168.07:51:50.43#ibcon#about to read 3, iclass 13, count 2 2006.168.07:51:50.46#ibcon#read 3, iclass 13, count 2 2006.168.07:51:50.46#ibcon#about to read 4, iclass 13, count 2 2006.168.07:51:50.46#ibcon#read 4, iclass 13, count 2 2006.168.07:51:50.46#ibcon#about to read 5, iclass 13, count 2 2006.168.07:51:50.46#ibcon#read 5, iclass 13, count 2 2006.168.07:51:50.46#ibcon#about to read 6, iclass 13, count 2 2006.168.07:51:50.46#ibcon#read 6, iclass 13, count 2 2006.168.07:51:50.46#ibcon#end of sib2, iclass 13, count 2 2006.168.07:51:50.46#ibcon#*after write, iclass 13, count 2 2006.168.07:51:50.46#ibcon#*before return 0, iclass 13, count 2 2006.168.07:51:50.46#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.168.07:51:50.46#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.168.07:51:50.46#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.168.07:51:50.46#ibcon#ireg 7 cls_cnt 0 2006.168.07:51:50.46#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.168.07:51:50.58#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.168.07:51:50.58#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.168.07:51:50.58#ibcon#enter wrdev, iclass 13, count 0 2006.168.07:51:50.58#ibcon#first serial, iclass 13, count 0 2006.168.07:51:50.58#ibcon#enter sib2, iclass 13, count 0 2006.168.07:51:50.58#ibcon#flushed, iclass 13, count 0 2006.168.07:51:50.58#ibcon#about to write, iclass 13, count 0 2006.168.07:51:50.58#ibcon#wrote, iclass 13, count 0 2006.168.07:51:50.58#ibcon#about to read 3, iclass 13, count 0 2006.168.07:51:50.60#ibcon#read 3, iclass 13, count 0 2006.168.07:51:50.60#ibcon#about to read 4, iclass 13, count 0 2006.168.07:51:50.60#ibcon#read 4, iclass 13, count 0 2006.168.07:51:50.60#ibcon#about to read 5, iclass 13, count 0 2006.168.07:51:50.60#ibcon#read 5, iclass 13, count 0 2006.168.07:51:50.60#ibcon#about to read 6, iclass 13, count 0 2006.168.07:51:50.60#ibcon#read 6, iclass 13, count 0 2006.168.07:51:50.60#ibcon#end of sib2, iclass 13, count 0 2006.168.07:51:50.60#ibcon#*mode == 0, iclass 13, count 0 2006.168.07:51:50.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.168.07:51:50.60#ibcon#[25=USB\r\n] 2006.168.07:51:50.60#ibcon#*before write, iclass 13, count 0 2006.168.07:51:50.60#ibcon#enter sib2, iclass 13, count 0 2006.168.07:51:50.60#ibcon#flushed, iclass 13, count 0 2006.168.07:51:50.60#ibcon#about to write, iclass 13, count 0 2006.168.07:51:50.60#ibcon#wrote, iclass 13, count 0 2006.168.07:51:50.60#ibcon#about to read 3, iclass 13, count 0 2006.168.07:51:50.63#ibcon#read 3, iclass 13, count 0 2006.168.07:51:50.63#ibcon#about to read 4, iclass 13, count 0 2006.168.07:51:50.63#ibcon#read 4, iclass 13, count 0 2006.168.07:51:50.63#ibcon#about to read 5, iclass 13, count 0 2006.168.07:51:50.63#ibcon#read 5, iclass 13, count 0 2006.168.07:51:50.63#ibcon#about to read 6, iclass 13, count 0 2006.168.07:51:50.63#ibcon#read 6, iclass 13, count 0 2006.168.07:51:50.63#ibcon#end of sib2, iclass 13, count 0 2006.168.07:51:50.63#ibcon#*after write, iclass 13, count 0 2006.168.07:51:50.63#ibcon#*before return 0, iclass 13, count 0 2006.168.07:51:50.63#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.168.07:51:50.63#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.168.07:51:50.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.168.07:51:50.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.168.07:51:50.63$vc4f8/vblo=1,632.99 2006.168.07:51:50.63#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.168.07:51:50.63#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.168.07:51:50.63#ibcon#ireg 17 cls_cnt 0 2006.168.07:51:50.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:51:50.63#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:51:50.63#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:51:50.63#ibcon#enter wrdev, iclass 15, count 0 2006.168.07:51:50.63#ibcon#first serial, iclass 15, count 0 2006.168.07:51:50.63#ibcon#enter sib2, iclass 15, count 0 2006.168.07:51:50.63#ibcon#flushed, iclass 15, count 0 2006.168.07:51:50.63#ibcon#about to write, iclass 15, count 0 2006.168.07:51:50.63#ibcon#wrote, iclass 15, count 0 2006.168.07:51:50.63#ibcon#about to read 3, iclass 15, count 0 2006.168.07:51:50.65#ibcon#read 3, iclass 15, count 0 2006.168.07:51:50.65#ibcon#about to read 4, iclass 15, count 0 2006.168.07:51:50.65#ibcon#read 4, iclass 15, count 0 2006.168.07:51:50.65#ibcon#about to read 5, iclass 15, count 0 2006.168.07:51:50.65#ibcon#read 5, iclass 15, count 0 2006.168.07:51:50.65#ibcon#about to read 6, iclass 15, count 0 2006.168.07:51:50.65#ibcon#read 6, iclass 15, count 0 2006.168.07:51:50.65#ibcon#end of sib2, iclass 15, count 0 2006.168.07:51:50.65#ibcon#*mode == 0, iclass 15, count 0 2006.168.07:51:50.65#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.168.07:51:50.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.07:51:50.65#ibcon#*before write, iclass 15, count 0 2006.168.07:51:50.65#ibcon#enter sib2, iclass 15, count 0 2006.168.07:51:50.65#ibcon#flushed, iclass 15, count 0 2006.168.07:51:50.65#ibcon#about to write, iclass 15, count 0 2006.168.07:51:50.65#ibcon#wrote, iclass 15, count 0 2006.168.07:51:50.65#ibcon#about to read 3, iclass 15, count 0 2006.168.07:51:50.69#ibcon#read 3, iclass 15, count 0 2006.168.07:51:50.69#ibcon#about to read 4, iclass 15, count 0 2006.168.07:51:50.69#ibcon#read 4, iclass 15, count 0 2006.168.07:51:50.69#ibcon#about to read 5, iclass 15, count 0 2006.168.07:51:50.69#ibcon#read 5, iclass 15, count 0 2006.168.07:51:50.69#ibcon#about to read 6, iclass 15, count 0 2006.168.07:51:50.69#ibcon#read 6, iclass 15, count 0 2006.168.07:51:50.69#ibcon#end of sib2, iclass 15, count 0 2006.168.07:51:50.69#ibcon#*after write, iclass 15, count 0 2006.168.07:51:50.69#ibcon#*before return 0, iclass 15, count 0 2006.168.07:51:50.69#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:51:50.69#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.168.07:51:50.69#ibcon#about to clear, iclass 15 cls_cnt 0 2006.168.07:51:50.69#ibcon#cleared, iclass 15 cls_cnt 0 2006.168.07:51:50.69$vc4f8/vb=1,4 2006.168.07:51:50.69#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.168.07:51:50.69#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.168.07:51:50.69#ibcon#ireg 11 cls_cnt 2 2006.168.07:51:50.69#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.168.07:51:50.69#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.168.07:51:50.69#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.168.07:51:50.69#ibcon#enter wrdev, iclass 17, count 2 2006.168.07:51:50.69#ibcon#first serial, iclass 17, count 2 2006.168.07:51:50.69#ibcon#enter sib2, iclass 17, count 2 2006.168.07:51:50.69#ibcon#flushed, iclass 17, count 2 2006.168.07:51:50.69#ibcon#about to write, iclass 17, count 2 2006.168.07:51:50.69#ibcon#wrote, iclass 17, count 2 2006.168.07:51:50.69#ibcon#about to read 3, iclass 17, count 2 2006.168.07:51:50.71#ibcon#read 3, iclass 17, count 2 2006.168.07:51:50.71#ibcon#about to read 4, iclass 17, count 2 2006.168.07:51:50.71#ibcon#read 4, iclass 17, count 2 2006.168.07:51:50.71#ibcon#about to read 5, iclass 17, count 2 2006.168.07:51:50.71#ibcon#read 5, iclass 17, count 2 2006.168.07:51:50.71#ibcon#about to read 6, iclass 17, count 2 2006.168.07:51:50.71#ibcon#read 6, iclass 17, count 2 2006.168.07:51:50.71#ibcon#end of sib2, iclass 17, count 2 2006.168.07:51:50.71#ibcon#*mode == 0, iclass 17, count 2 2006.168.07:51:50.71#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.168.07:51:50.71#ibcon#[27=AT01-04\r\n] 2006.168.07:51:50.71#ibcon#*before write, iclass 17, count 2 2006.168.07:51:50.71#ibcon#enter sib2, iclass 17, count 2 2006.168.07:51:50.71#ibcon#flushed, iclass 17, count 2 2006.168.07:51:50.71#ibcon#about to write, iclass 17, count 2 2006.168.07:51:50.71#ibcon#wrote, iclass 17, count 2 2006.168.07:51:50.71#ibcon#about to read 3, iclass 17, count 2 2006.168.07:51:50.74#ibcon#read 3, iclass 17, count 2 2006.168.07:51:50.74#ibcon#about to read 4, iclass 17, count 2 2006.168.07:51:50.74#ibcon#read 4, iclass 17, count 2 2006.168.07:51:50.74#ibcon#about to read 5, iclass 17, count 2 2006.168.07:51:50.74#ibcon#read 5, iclass 17, count 2 2006.168.07:51:50.74#ibcon#about to read 6, iclass 17, count 2 2006.168.07:51:50.74#ibcon#read 6, iclass 17, count 2 2006.168.07:51:50.74#ibcon#end of sib2, iclass 17, count 2 2006.168.07:51:50.74#ibcon#*after write, iclass 17, count 2 2006.168.07:51:50.74#ibcon#*before return 0, iclass 17, count 2 2006.168.07:51:50.74#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.168.07:51:50.74#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.168.07:51:50.74#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.168.07:51:50.74#ibcon#ireg 7 cls_cnt 0 2006.168.07:51:50.74#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.168.07:51:50.86#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.168.07:51:50.86#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.168.07:51:50.86#ibcon#enter wrdev, iclass 17, count 0 2006.168.07:51:50.86#ibcon#first serial, iclass 17, count 0 2006.168.07:51:50.86#ibcon#enter sib2, iclass 17, count 0 2006.168.07:51:50.86#ibcon#flushed, iclass 17, count 0 2006.168.07:51:50.86#ibcon#about to write, iclass 17, count 0 2006.168.07:51:50.86#ibcon#wrote, iclass 17, count 0 2006.168.07:51:50.86#ibcon#about to read 3, iclass 17, count 0 2006.168.07:51:50.88#ibcon#read 3, iclass 17, count 0 2006.168.07:51:50.88#ibcon#about to read 4, iclass 17, count 0 2006.168.07:51:50.88#ibcon#read 4, iclass 17, count 0 2006.168.07:51:50.88#ibcon#about to read 5, iclass 17, count 0 2006.168.07:51:50.88#ibcon#read 5, iclass 17, count 0 2006.168.07:51:50.88#ibcon#about to read 6, iclass 17, count 0 2006.168.07:51:50.88#ibcon#read 6, iclass 17, count 0 2006.168.07:51:50.88#ibcon#end of sib2, iclass 17, count 0 2006.168.07:51:50.88#ibcon#*mode == 0, iclass 17, count 0 2006.168.07:51:50.88#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.168.07:51:50.88#ibcon#[27=USB\r\n] 2006.168.07:51:50.88#ibcon#*before write, iclass 17, count 0 2006.168.07:51:50.88#ibcon#enter sib2, iclass 17, count 0 2006.168.07:51:50.88#ibcon#flushed, iclass 17, count 0 2006.168.07:51:50.88#ibcon#about to write, iclass 17, count 0 2006.168.07:51:50.88#ibcon#wrote, iclass 17, count 0 2006.168.07:51:50.88#ibcon#about to read 3, iclass 17, count 0 2006.168.07:51:50.91#ibcon#read 3, iclass 17, count 0 2006.168.07:51:50.91#ibcon#about to read 4, iclass 17, count 0 2006.168.07:51:50.91#ibcon#read 4, iclass 17, count 0 2006.168.07:51:50.91#ibcon#about to read 5, iclass 17, count 0 2006.168.07:51:50.91#ibcon#read 5, iclass 17, count 0 2006.168.07:51:50.91#ibcon#about to read 6, iclass 17, count 0 2006.168.07:51:50.91#ibcon#read 6, iclass 17, count 0 2006.168.07:51:50.91#ibcon#end of sib2, iclass 17, count 0 2006.168.07:51:50.91#ibcon#*after write, iclass 17, count 0 2006.168.07:51:50.91#ibcon#*before return 0, iclass 17, count 0 2006.168.07:51:50.91#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.168.07:51:50.91#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.168.07:51:50.91#ibcon#about to clear, iclass 17 cls_cnt 0 2006.168.07:51:50.91#ibcon#cleared, iclass 17 cls_cnt 0 2006.168.07:51:50.91$vc4f8/vblo=2,640.99 2006.168.07:51:50.91#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.168.07:51:50.91#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.168.07:51:50.91#ibcon#ireg 17 cls_cnt 0 2006.168.07:51:50.91#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:51:50.91#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:51:50.91#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:51:50.91#ibcon#enter wrdev, iclass 19, count 0 2006.168.07:51:50.91#ibcon#first serial, iclass 19, count 0 2006.168.07:51:50.91#ibcon#enter sib2, iclass 19, count 0 2006.168.07:51:50.91#ibcon#flushed, iclass 19, count 0 2006.168.07:51:50.91#ibcon#about to write, iclass 19, count 0 2006.168.07:51:50.91#ibcon#wrote, iclass 19, count 0 2006.168.07:51:50.91#ibcon#about to read 3, iclass 19, count 0 2006.168.07:51:50.93#ibcon#read 3, iclass 19, count 0 2006.168.07:51:50.93#ibcon#about to read 4, iclass 19, count 0 2006.168.07:51:50.93#ibcon#read 4, iclass 19, count 0 2006.168.07:51:50.93#ibcon#about to read 5, iclass 19, count 0 2006.168.07:51:50.93#ibcon#read 5, iclass 19, count 0 2006.168.07:51:50.93#ibcon#about to read 6, iclass 19, count 0 2006.168.07:51:50.93#ibcon#read 6, iclass 19, count 0 2006.168.07:51:50.93#ibcon#end of sib2, iclass 19, count 0 2006.168.07:51:50.93#ibcon#*mode == 0, iclass 19, count 0 2006.168.07:51:50.93#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.168.07:51:50.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.07:51:50.93#ibcon#*before write, iclass 19, count 0 2006.168.07:51:50.93#ibcon#enter sib2, iclass 19, count 0 2006.168.07:51:50.93#ibcon#flushed, iclass 19, count 0 2006.168.07:51:50.93#ibcon#about to write, iclass 19, count 0 2006.168.07:51:50.93#ibcon#wrote, iclass 19, count 0 2006.168.07:51:50.93#ibcon#about to read 3, iclass 19, count 0 2006.168.07:51:50.98#ibcon#read 3, iclass 19, count 0 2006.168.07:51:50.98#ibcon#about to read 4, iclass 19, count 0 2006.168.07:51:50.98#ibcon#read 4, iclass 19, count 0 2006.168.07:51:50.98#ibcon#about to read 5, iclass 19, count 0 2006.168.07:51:50.98#ibcon#read 5, iclass 19, count 0 2006.168.07:51:50.98#ibcon#about to read 6, iclass 19, count 0 2006.168.07:51:50.98#ibcon#read 6, iclass 19, count 0 2006.168.07:51:50.98#ibcon#end of sib2, iclass 19, count 0 2006.168.07:51:50.98#ibcon#*after write, iclass 19, count 0 2006.168.07:51:50.98#ibcon#*before return 0, iclass 19, count 0 2006.168.07:51:50.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:51:50.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:51:50.98#ibcon#about to clear, iclass 19 cls_cnt 0 2006.168.07:51:50.98#ibcon#cleared, iclass 19 cls_cnt 0 2006.168.07:51:50.98$vc4f8/vb=2,4 2006.168.07:51:50.98#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.168.07:51:50.98#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.168.07:51:50.98#ibcon#ireg 11 cls_cnt 2 2006.168.07:51:50.98#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.168.07:51:51.02#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.168.07:51:51.02#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.168.07:51:51.02#ibcon#enter wrdev, iclass 21, count 2 2006.168.07:51:51.02#ibcon#first serial, iclass 21, count 2 2006.168.07:51:51.02#ibcon#enter sib2, iclass 21, count 2 2006.168.07:51:51.02#ibcon#flushed, iclass 21, count 2 2006.168.07:51:51.02#ibcon#about to write, iclass 21, count 2 2006.168.07:51:51.02#ibcon#wrote, iclass 21, count 2 2006.168.07:51:51.02#ibcon#about to read 3, iclass 21, count 2 2006.168.07:51:51.04#ibcon#read 3, iclass 21, count 2 2006.168.07:51:51.04#ibcon#about to read 4, iclass 21, count 2 2006.168.07:51:51.04#ibcon#read 4, iclass 21, count 2 2006.168.07:51:51.04#ibcon#about to read 5, iclass 21, count 2 2006.168.07:51:51.04#ibcon#read 5, iclass 21, count 2 2006.168.07:51:51.04#ibcon#about to read 6, iclass 21, count 2 2006.168.07:51:51.04#ibcon#read 6, iclass 21, count 2 2006.168.07:51:51.04#ibcon#end of sib2, iclass 21, count 2 2006.168.07:51:51.04#ibcon#*mode == 0, iclass 21, count 2 2006.168.07:51:51.04#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.168.07:51:51.04#ibcon#[27=AT02-04\r\n] 2006.168.07:51:51.04#ibcon#*before write, iclass 21, count 2 2006.168.07:51:51.04#ibcon#enter sib2, iclass 21, count 2 2006.168.07:51:51.04#ibcon#flushed, iclass 21, count 2 2006.168.07:51:51.04#ibcon#about to write, iclass 21, count 2 2006.168.07:51:51.04#ibcon#wrote, iclass 21, count 2 2006.168.07:51:51.04#ibcon#about to read 3, iclass 21, count 2 2006.168.07:51:51.07#ibcon#read 3, iclass 21, count 2 2006.168.07:51:51.07#ibcon#about to read 4, iclass 21, count 2 2006.168.07:51:51.07#ibcon#read 4, iclass 21, count 2 2006.168.07:51:51.07#ibcon#about to read 5, iclass 21, count 2 2006.168.07:51:51.07#ibcon#read 5, iclass 21, count 2 2006.168.07:51:51.07#ibcon#about to read 6, iclass 21, count 2 2006.168.07:51:51.07#ibcon#read 6, iclass 21, count 2 2006.168.07:51:51.07#ibcon#end of sib2, iclass 21, count 2 2006.168.07:51:51.07#ibcon#*after write, iclass 21, count 2 2006.168.07:51:51.07#ibcon#*before return 0, iclass 21, count 2 2006.168.07:51:51.07#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.168.07:51:51.07#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.168.07:51:51.07#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.168.07:51:51.07#ibcon#ireg 7 cls_cnt 0 2006.168.07:51:51.07#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.168.07:51:51.19#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.168.07:51:51.19#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.168.07:51:51.19#ibcon#enter wrdev, iclass 21, count 0 2006.168.07:51:51.19#ibcon#first serial, iclass 21, count 0 2006.168.07:51:51.19#ibcon#enter sib2, iclass 21, count 0 2006.168.07:51:51.19#ibcon#flushed, iclass 21, count 0 2006.168.07:51:51.19#ibcon#about to write, iclass 21, count 0 2006.168.07:51:51.19#ibcon#wrote, iclass 21, count 0 2006.168.07:51:51.19#ibcon#about to read 3, iclass 21, count 0 2006.168.07:51:51.21#ibcon#read 3, iclass 21, count 0 2006.168.07:51:51.21#ibcon#about to read 4, iclass 21, count 0 2006.168.07:51:51.21#ibcon#read 4, iclass 21, count 0 2006.168.07:51:51.21#ibcon#about to read 5, iclass 21, count 0 2006.168.07:51:51.21#ibcon#read 5, iclass 21, count 0 2006.168.07:51:51.21#ibcon#about to read 6, iclass 21, count 0 2006.168.07:51:51.21#ibcon#read 6, iclass 21, count 0 2006.168.07:51:51.21#ibcon#end of sib2, iclass 21, count 0 2006.168.07:51:51.21#ibcon#*mode == 0, iclass 21, count 0 2006.168.07:51:51.21#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.168.07:51:51.21#ibcon#[27=USB\r\n] 2006.168.07:51:51.21#ibcon#*before write, iclass 21, count 0 2006.168.07:51:51.21#ibcon#enter sib2, iclass 21, count 0 2006.168.07:51:51.21#ibcon#flushed, iclass 21, count 0 2006.168.07:51:51.21#ibcon#about to write, iclass 21, count 0 2006.168.07:51:51.21#ibcon#wrote, iclass 21, count 0 2006.168.07:51:51.21#ibcon#about to read 3, iclass 21, count 0 2006.168.07:51:51.24#ibcon#read 3, iclass 21, count 0 2006.168.07:51:51.24#ibcon#about to read 4, iclass 21, count 0 2006.168.07:51:51.24#ibcon#read 4, iclass 21, count 0 2006.168.07:51:51.24#ibcon#about to read 5, iclass 21, count 0 2006.168.07:51:51.24#ibcon#read 5, iclass 21, count 0 2006.168.07:51:51.24#ibcon#about to read 6, iclass 21, count 0 2006.168.07:51:51.24#ibcon#read 6, iclass 21, count 0 2006.168.07:51:51.24#ibcon#end of sib2, iclass 21, count 0 2006.168.07:51:51.24#ibcon#*after write, iclass 21, count 0 2006.168.07:51:51.24#ibcon#*before return 0, iclass 21, count 0 2006.168.07:51:51.24#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.168.07:51:51.24#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.168.07:51:51.24#ibcon#about to clear, iclass 21 cls_cnt 0 2006.168.07:51:51.24#ibcon#cleared, iclass 21 cls_cnt 0 2006.168.07:51:51.24$vc4f8/vblo=3,656.99 2006.168.07:51:51.24#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.168.07:51:51.24#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.168.07:51:51.24#ibcon#ireg 17 cls_cnt 0 2006.168.07:51:51.24#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:51:51.24#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:51:51.24#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:51:51.24#ibcon#enter wrdev, iclass 23, count 0 2006.168.07:51:51.24#ibcon#first serial, iclass 23, count 0 2006.168.07:51:51.24#ibcon#enter sib2, iclass 23, count 0 2006.168.07:51:51.24#ibcon#flushed, iclass 23, count 0 2006.168.07:51:51.24#ibcon#about to write, iclass 23, count 0 2006.168.07:51:51.24#ibcon#wrote, iclass 23, count 0 2006.168.07:51:51.24#ibcon#about to read 3, iclass 23, count 0 2006.168.07:51:51.26#ibcon#read 3, iclass 23, count 0 2006.168.07:51:51.26#ibcon#about to read 4, iclass 23, count 0 2006.168.07:51:51.26#ibcon#read 4, iclass 23, count 0 2006.168.07:51:51.26#ibcon#about to read 5, iclass 23, count 0 2006.168.07:51:51.26#ibcon#read 5, iclass 23, count 0 2006.168.07:51:51.26#ibcon#about to read 6, iclass 23, count 0 2006.168.07:51:51.26#ibcon#read 6, iclass 23, count 0 2006.168.07:51:51.26#ibcon#end of sib2, iclass 23, count 0 2006.168.07:51:51.26#ibcon#*mode == 0, iclass 23, count 0 2006.168.07:51:51.26#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.168.07:51:51.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.07:51:51.26#ibcon#*before write, iclass 23, count 0 2006.168.07:51:51.26#ibcon#enter sib2, iclass 23, count 0 2006.168.07:51:51.26#ibcon#flushed, iclass 23, count 0 2006.168.07:51:51.26#ibcon#about to write, iclass 23, count 0 2006.168.07:51:51.26#ibcon#wrote, iclass 23, count 0 2006.168.07:51:51.26#ibcon#about to read 3, iclass 23, count 0 2006.168.07:51:51.30#ibcon#read 3, iclass 23, count 0 2006.168.07:51:51.30#ibcon#about to read 4, iclass 23, count 0 2006.168.07:51:51.30#ibcon#read 4, iclass 23, count 0 2006.168.07:51:51.30#ibcon#about to read 5, iclass 23, count 0 2006.168.07:51:51.30#ibcon#read 5, iclass 23, count 0 2006.168.07:51:51.30#ibcon#about to read 6, iclass 23, count 0 2006.168.07:51:51.30#ibcon#read 6, iclass 23, count 0 2006.168.07:51:51.30#ibcon#end of sib2, iclass 23, count 0 2006.168.07:51:51.30#ibcon#*after write, iclass 23, count 0 2006.168.07:51:51.30#ibcon#*before return 0, iclass 23, count 0 2006.168.07:51:51.30#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:51:51.30#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.168.07:51:51.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.168.07:51:51.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.168.07:51:51.30$vc4f8/vb=3,4 2006.168.07:51:51.30#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.168.07:51:51.30#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.168.07:51:51.30#ibcon#ireg 11 cls_cnt 2 2006.168.07:51:51.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.168.07:51:51.36#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.168.07:51:51.36#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.168.07:51:51.36#ibcon#enter wrdev, iclass 25, count 2 2006.168.07:51:51.36#ibcon#first serial, iclass 25, count 2 2006.168.07:51:51.36#ibcon#enter sib2, iclass 25, count 2 2006.168.07:51:51.36#ibcon#flushed, iclass 25, count 2 2006.168.07:51:51.36#ibcon#about to write, iclass 25, count 2 2006.168.07:51:51.36#ibcon#wrote, iclass 25, count 2 2006.168.07:51:51.36#ibcon#about to read 3, iclass 25, count 2 2006.168.07:51:51.38#ibcon#read 3, iclass 25, count 2 2006.168.07:51:51.38#ibcon#about to read 4, iclass 25, count 2 2006.168.07:51:51.38#ibcon#read 4, iclass 25, count 2 2006.168.07:51:51.38#ibcon#about to read 5, iclass 25, count 2 2006.168.07:51:51.38#ibcon#read 5, iclass 25, count 2 2006.168.07:51:51.38#ibcon#about to read 6, iclass 25, count 2 2006.168.07:51:51.38#ibcon#read 6, iclass 25, count 2 2006.168.07:51:51.38#ibcon#end of sib2, iclass 25, count 2 2006.168.07:51:51.38#ibcon#*mode == 0, iclass 25, count 2 2006.168.07:51:51.38#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.168.07:51:51.38#ibcon#[27=AT03-04\r\n] 2006.168.07:51:51.38#ibcon#*before write, iclass 25, count 2 2006.168.07:51:51.38#ibcon#enter sib2, iclass 25, count 2 2006.168.07:51:51.38#ibcon#flushed, iclass 25, count 2 2006.168.07:51:51.38#ibcon#about to write, iclass 25, count 2 2006.168.07:51:51.38#ibcon#wrote, iclass 25, count 2 2006.168.07:51:51.38#ibcon#about to read 3, iclass 25, count 2 2006.168.07:51:51.41#ibcon#read 3, iclass 25, count 2 2006.168.07:51:51.41#ibcon#about to read 4, iclass 25, count 2 2006.168.07:51:51.41#ibcon#read 4, iclass 25, count 2 2006.168.07:51:51.41#ibcon#about to read 5, iclass 25, count 2 2006.168.07:51:51.41#ibcon#read 5, iclass 25, count 2 2006.168.07:51:51.41#ibcon#about to read 6, iclass 25, count 2 2006.168.07:51:51.41#ibcon#read 6, iclass 25, count 2 2006.168.07:51:51.41#ibcon#end of sib2, iclass 25, count 2 2006.168.07:51:51.41#ibcon#*after write, iclass 25, count 2 2006.168.07:51:51.41#ibcon#*before return 0, iclass 25, count 2 2006.168.07:51:51.41#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.168.07:51:51.41#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.168.07:51:51.41#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.168.07:51:51.41#ibcon#ireg 7 cls_cnt 0 2006.168.07:51:51.41#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.168.07:51:51.53#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.168.07:51:51.53#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.168.07:51:51.53#ibcon#enter wrdev, iclass 25, count 0 2006.168.07:51:51.53#ibcon#first serial, iclass 25, count 0 2006.168.07:51:51.53#ibcon#enter sib2, iclass 25, count 0 2006.168.07:51:51.53#ibcon#flushed, iclass 25, count 0 2006.168.07:51:51.53#ibcon#about to write, iclass 25, count 0 2006.168.07:51:51.53#ibcon#wrote, iclass 25, count 0 2006.168.07:51:51.53#ibcon#about to read 3, iclass 25, count 0 2006.168.07:51:51.55#ibcon#read 3, iclass 25, count 0 2006.168.07:51:51.55#ibcon#about to read 4, iclass 25, count 0 2006.168.07:51:51.55#ibcon#read 4, iclass 25, count 0 2006.168.07:51:51.55#ibcon#about to read 5, iclass 25, count 0 2006.168.07:51:51.55#ibcon#read 5, iclass 25, count 0 2006.168.07:51:51.55#ibcon#about to read 6, iclass 25, count 0 2006.168.07:51:51.55#ibcon#read 6, iclass 25, count 0 2006.168.07:51:51.55#ibcon#end of sib2, iclass 25, count 0 2006.168.07:51:51.55#ibcon#*mode == 0, iclass 25, count 0 2006.168.07:51:51.55#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.168.07:51:51.55#ibcon#[27=USB\r\n] 2006.168.07:51:51.55#ibcon#*before write, iclass 25, count 0 2006.168.07:51:51.55#ibcon#enter sib2, iclass 25, count 0 2006.168.07:51:51.55#ibcon#flushed, iclass 25, count 0 2006.168.07:51:51.55#ibcon#about to write, iclass 25, count 0 2006.168.07:51:51.55#ibcon#wrote, iclass 25, count 0 2006.168.07:51:51.55#ibcon#about to read 3, iclass 25, count 0 2006.168.07:51:51.58#ibcon#read 3, iclass 25, count 0 2006.168.07:51:51.58#ibcon#about to read 4, iclass 25, count 0 2006.168.07:51:51.58#ibcon#read 4, iclass 25, count 0 2006.168.07:51:51.58#ibcon#about to read 5, iclass 25, count 0 2006.168.07:51:51.58#ibcon#read 5, iclass 25, count 0 2006.168.07:51:51.58#ibcon#about to read 6, iclass 25, count 0 2006.168.07:51:51.58#ibcon#read 6, iclass 25, count 0 2006.168.07:51:51.58#ibcon#end of sib2, iclass 25, count 0 2006.168.07:51:51.58#ibcon#*after write, iclass 25, count 0 2006.168.07:51:51.58#ibcon#*before return 0, iclass 25, count 0 2006.168.07:51:51.58#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.168.07:51:51.58#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.168.07:51:51.58#ibcon#about to clear, iclass 25 cls_cnt 0 2006.168.07:51:51.58#ibcon#cleared, iclass 25 cls_cnt 0 2006.168.07:51:51.58$vc4f8/vblo=4,712.99 2006.168.07:51:51.58#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.168.07:51:51.58#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.168.07:51:51.58#ibcon#ireg 17 cls_cnt 0 2006.168.07:51:51.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.168.07:51:51.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.168.07:51:51.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.168.07:51:51.58#ibcon#enter wrdev, iclass 27, count 0 2006.168.07:51:51.58#ibcon#first serial, iclass 27, count 0 2006.168.07:51:51.58#ibcon#enter sib2, iclass 27, count 0 2006.168.07:51:51.58#ibcon#flushed, iclass 27, count 0 2006.168.07:51:51.58#ibcon#about to write, iclass 27, count 0 2006.168.07:51:51.58#ibcon#wrote, iclass 27, count 0 2006.168.07:51:51.58#ibcon#about to read 3, iclass 27, count 0 2006.168.07:51:51.60#ibcon#read 3, iclass 27, count 0 2006.168.07:51:51.60#ibcon#about to read 4, iclass 27, count 0 2006.168.07:51:51.60#ibcon#read 4, iclass 27, count 0 2006.168.07:51:51.60#ibcon#about to read 5, iclass 27, count 0 2006.168.07:51:51.60#ibcon#read 5, iclass 27, count 0 2006.168.07:51:51.60#ibcon#about to read 6, iclass 27, count 0 2006.168.07:51:51.60#ibcon#read 6, iclass 27, count 0 2006.168.07:51:51.60#ibcon#end of sib2, iclass 27, count 0 2006.168.07:51:51.60#ibcon#*mode == 0, iclass 27, count 0 2006.168.07:51:51.60#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.168.07:51:51.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.07:51:51.60#ibcon#*before write, iclass 27, count 0 2006.168.07:51:51.60#ibcon#enter sib2, iclass 27, count 0 2006.168.07:51:51.60#ibcon#flushed, iclass 27, count 0 2006.168.07:51:51.60#ibcon#about to write, iclass 27, count 0 2006.168.07:51:51.60#ibcon#wrote, iclass 27, count 0 2006.168.07:51:51.60#ibcon#about to read 3, iclass 27, count 0 2006.168.07:51:51.64#ibcon#read 3, iclass 27, count 0 2006.168.07:51:51.64#ibcon#about to read 4, iclass 27, count 0 2006.168.07:51:51.64#ibcon#read 4, iclass 27, count 0 2006.168.07:51:51.64#ibcon#about to read 5, iclass 27, count 0 2006.168.07:51:51.64#ibcon#read 5, iclass 27, count 0 2006.168.07:51:51.64#ibcon#about to read 6, iclass 27, count 0 2006.168.07:51:51.64#ibcon#read 6, iclass 27, count 0 2006.168.07:51:51.64#ibcon#end of sib2, iclass 27, count 0 2006.168.07:51:51.64#ibcon#*after write, iclass 27, count 0 2006.168.07:51:51.64#ibcon#*before return 0, iclass 27, count 0 2006.168.07:51:51.64#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.168.07:51:51.64#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.168.07:51:51.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.168.07:51:51.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.168.07:51:51.64$vc4f8/vb=4,4 2006.168.07:51:51.64#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.168.07:51:51.64#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.168.07:51:51.64#ibcon#ireg 11 cls_cnt 2 2006.168.07:51:51.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.168.07:51:51.71#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.168.07:51:51.71#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.168.07:51:51.71#ibcon#enter wrdev, iclass 29, count 2 2006.168.07:51:51.71#ibcon#first serial, iclass 29, count 2 2006.168.07:51:51.71#ibcon#enter sib2, iclass 29, count 2 2006.168.07:51:51.71#ibcon#flushed, iclass 29, count 2 2006.168.07:51:51.71#ibcon#about to write, iclass 29, count 2 2006.168.07:51:51.71#ibcon#wrote, iclass 29, count 2 2006.168.07:51:51.71#ibcon#about to read 3, iclass 29, count 2 2006.168.07:51:51.72#ibcon#read 3, iclass 29, count 2 2006.168.07:51:51.72#ibcon#about to read 4, iclass 29, count 2 2006.168.07:51:51.72#ibcon#read 4, iclass 29, count 2 2006.168.07:51:51.72#ibcon#about to read 5, iclass 29, count 2 2006.168.07:51:51.72#ibcon#read 5, iclass 29, count 2 2006.168.07:51:51.72#ibcon#about to read 6, iclass 29, count 2 2006.168.07:51:51.72#ibcon#read 6, iclass 29, count 2 2006.168.07:51:51.72#ibcon#end of sib2, iclass 29, count 2 2006.168.07:51:51.72#ibcon#*mode == 0, iclass 29, count 2 2006.168.07:51:51.72#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.168.07:51:51.72#ibcon#[27=AT04-04\r\n] 2006.168.07:51:51.72#ibcon#*before write, iclass 29, count 2 2006.168.07:51:51.72#ibcon#enter sib2, iclass 29, count 2 2006.168.07:51:51.72#ibcon#flushed, iclass 29, count 2 2006.168.07:51:51.72#ibcon#about to write, iclass 29, count 2 2006.168.07:51:51.72#ibcon#wrote, iclass 29, count 2 2006.168.07:51:51.72#ibcon#about to read 3, iclass 29, count 2 2006.168.07:51:51.75#ibcon#read 3, iclass 29, count 2 2006.168.07:51:51.75#ibcon#about to read 4, iclass 29, count 2 2006.168.07:51:51.75#ibcon#read 4, iclass 29, count 2 2006.168.07:51:51.75#ibcon#about to read 5, iclass 29, count 2 2006.168.07:51:51.75#ibcon#read 5, iclass 29, count 2 2006.168.07:51:51.75#ibcon#about to read 6, iclass 29, count 2 2006.168.07:51:51.75#ibcon#read 6, iclass 29, count 2 2006.168.07:51:51.75#ibcon#end of sib2, iclass 29, count 2 2006.168.07:51:51.75#ibcon#*after write, iclass 29, count 2 2006.168.07:51:51.75#ibcon#*before return 0, iclass 29, count 2 2006.168.07:51:51.75#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.168.07:51:51.75#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.168.07:51:51.75#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.168.07:51:51.75#ibcon#ireg 7 cls_cnt 0 2006.168.07:51:51.75#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.168.07:51:51.87#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.168.07:51:51.87#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.168.07:51:51.87#ibcon#enter wrdev, iclass 29, count 0 2006.168.07:51:51.87#ibcon#first serial, iclass 29, count 0 2006.168.07:51:51.87#ibcon#enter sib2, iclass 29, count 0 2006.168.07:51:51.87#ibcon#flushed, iclass 29, count 0 2006.168.07:51:51.87#ibcon#about to write, iclass 29, count 0 2006.168.07:51:51.87#ibcon#wrote, iclass 29, count 0 2006.168.07:51:51.87#ibcon#about to read 3, iclass 29, count 0 2006.168.07:51:51.89#ibcon#read 3, iclass 29, count 0 2006.168.07:51:51.89#ibcon#about to read 4, iclass 29, count 0 2006.168.07:51:51.89#ibcon#read 4, iclass 29, count 0 2006.168.07:51:51.89#ibcon#about to read 5, iclass 29, count 0 2006.168.07:51:51.89#ibcon#read 5, iclass 29, count 0 2006.168.07:51:51.89#ibcon#about to read 6, iclass 29, count 0 2006.168.07:51:51.89#ibcon#read 6, iclass 29, count 0 2006.168.07:51:51.89#ibcon#end of sib2, iclass 29, count 0 2006.168.07:51:51.89#ibcon#*mode == 0, iclass 29, count 0 2006.168.07:51:51.89#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.168.07:51:51.89#ibcon#[27=USB\r\n] 2006.168.07:51:51.89#ibcon#*before write, iclass 29, count 0 2006.168.07:51:51.89#ibcon#enter sib2, iclass 29, count 0 2006.168.07:51:51.89#ibcon#flushed, iclass 29, count 0 2006.168.07:51:51.89#ibcon#about to write, iclass 29, count 0 2006.168.07:51:51.89#ibcon#wrote, iclass 29, count 0 2006.168.07:51:51.89#ibcon#about to read 3, iclass 29, count 0 2006.168.07:51:51.92#ibcon#read 3, iclass 29, count 0 2006.168.07:51:51.92#ibcon#about to read 4, iclass 29, count 0 2006.168.07:51:51.92#ibcon#read 4, iclass 29, count 0 2006.168.07:51:51.92#ibcon#about to read 5, iclass 29, count 0 2006.168.07:51:51.92#ibcon#read 5, iclass 29, count 0 2006.168.07:51:51.92#ibcon#about to read 6, iclass 29, count 0 2006.168.07:51:51.92#ibcon#read 6, iclass 29, count 0 2006.168.07:51:51.92#ibcon#end of sib2, iclass 29, count 0 2006.168.07:51:51.92#ibcon#*after write, iclass 29, count 0 2006.168.07:51:51.92#ibcon#*before return 0, iclass 29, count 0 2006.168.07:51:51.92#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.168.07:51:51.92#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.168.07:51:51.92#ibcon#about to clear, iclass 29 cls_cnt 0 2006.168.07:51:51.92#ibcon#cleared, iclass 29 cls_cnt 0 2006.168.07:51:51.92$vc4f8/vblo=5,744.99 2006.168.07:51:51.92#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.168.07:51:51.92#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.168.07:51:51.92#ibcon#ireg 17 cls_cnt 0 2006.168.07:51:51.92#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:51:51.92#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:51:51.92#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:51:51.92#ibcon#enter wrdev, iclass 31, count 0 2006.168.07:51:51.92#ibcon#first serial, iclass 31, count 0 2006.168.07:51:51.92#ibcon#enter sib2, iclass 31, count 0 2006.168.07:51:51.92#ibcon#flushed, iclass 31, count 0 2006.168.07:51:51.92#ibcon#about to write, iclass 31, count 0 2006.168.07:51:51.92#ibcon#wrote, iclass 31, count 0 2006.168.07:51:51.92#ibcon#about to read 3, iclass 31, count 0 2006.168.07:51:51.94#ibcon#read 3, iclass 31, count 0 2006.168.07:51:51.94#ibcon#about to read 4, iclass 31, count 0 2006.168.07:51:51.94#ibcon#read 4, iclass 31, count 0 2006.168.07:51:51.94#ibcon#about to read 5, iclass 31, count 0 2006.168.07:51:51.94#ibcon#read 5, iclass 31, count 0 2006.168.07:51:51.94#ibcon#about to read 6, iclass 31, count 0 2006.168.07:51:51.94#ibcon#read 6, iclass 31, count 0 2006.168.07:51:51.94#ibcon#end of sib2, iclass 31, count 0 2006.168.07:51:51.94#ibcon#*mode == 0, iclass 31, count 0 2006.168.07:51:51.94#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.168.07:51:51.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.07:51:51.94#ibcon#*before write, iclass 31, count 0 2006.168.07:51:51.94#ibcon#enter sib2, iclass 31, count 0 2006.168.07:51:51.94#ibcon#flushed, iclass 31, count 0 2006.168.07:51:51.94#ibcon#about to write, iclass 31, count 0 2006.168.07:51:51.94#ibcon#wrote, iclass 31, count 0 2006.168.07:51:51.94#ibcon#about to read 3, iclass 31, count 0 2006.168.07:51:51.98#ibcon#read 3, iclass 31, count 0 2006.168.07:51:51.98#ibcon#about to read 4, iclass 31, count 0 2006.168.07:51:51.98#ibcon#read 4, iclass 31, count 0 2006.168.07:51:51.98#ibcon#about to read 5, iclass 31, count 0 2006.168.07:51:51.98#ibcon#read 5, iclass 31, count 0 2006.168.07:51:51.98#ibcon#about to read 6, iclass 31, count 0 2006.168.07:51:51.98#ibcon#read 6, iclass 31, count 0 2006.168.07:51:51.98#ibcon#end of sib2, iclass 31, count 0 2006.168.07:51:51.98#ibcon#*after write, iclass 31, count 0 2006.168.07:51:51.98#ibcon#*before return 0, iclass 31, count 0 2006.168.07:51:51.98#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:51:51.98#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.168.07:51:51.98#ibcon#about to clear, iclass 31 cls_cnt 0 2006.168.07:51:51.98#ibcon#cleared, iclass 31 cls_cnt 0 2006.168.07:51:51.98$vc4f8/vb=5,4 2006.168.07:51:51.98#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.168.07:51:51.98#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.168.07:51:51.98#ibcon#ireg 11 cls_cnt 2 2006.168.07:51:51.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:51:52.04#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:51:52.04#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:51:52.04#ibcon#enter wrdev, iclass 33, count 2 2006.168.07:51:52.04#ibcon#first serial, iclass 33, count 2 2006.168.07:51:52.04#ibcon#enter sib2, iclass 33, count 2 2006.168.07:51:52.04#ibcon#flushed, iclass 33, count 2 2006.168.07:51:52.04#ibcon#about to write, iclass 33, count 2 2006.168.07:51:52.04#ibcon#wrote, iclass 33, count 2 2006.168.07:51:52.04#ibcon#about to read 3, iclass 33, count 2 2006.168.07:51:52.06#ibcon#read 3, iclass 33, count 2 2006.168.07:51:52.06#ibcon#about to read 4, iclass 33, count 2 2006.168.07:51:52.06#ibcon#read 4, iclass 33, count 2 2006.168.07:51:52.06#ibcon#about to read 5, iclass 33, count 2 2006.168.07:51:52.06#ibcon#read 5, iclass 33, count 2 2006.168.07:51:52.06#ibcon#about to read 6, iclass 33, count 2 2006.168.07:51:52.06#ibcon#read 6, iclass 33, count 2 2006.168.07:51:52.06#ibcon#end of sib2, iclass 33, count 2 2006.168.07:51:52.06#ibcon#*mode == 0, iclass 33, count 2 2006.168.07:51:52.06#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.168.07:51:52.06#ibcon#[27=AT05-04\r\n] 2006.168.07:51:52.06#ibcon#*before write, iclass 33, count 2 2006.168.07:51:52.06#ibcon#enter sib2, iclass 33, count 2 2006.168.07:51:52.06#ibcon#flushed, iclass 33, count 2 2006.168.07:51:52.06#ibcon#about to write, iclass 33, count 2 2006.168.07:51:52.06#ibcon#wrote, iclass 33, count 2 2006.168.07:51:52.06#ibcon#about to read 3, iclass 33, count 2 2006.168.07:51:52.09#ibcon#read 3, iclass 33, count 2 2006.168.07:51:52.09#ibcon#about to read 4, iclass 33, count 2 2006.168.07:51:52.09#ibcon#read 4, iclass 33, count 2 2006.168.07:51:52.09#ibcon#about to read 5, iclass 33, count 2 2006.168.07:51:52.09#ibcon#read 5, iclass 33, count 2 2006.168.07:51:52.09#ibcon#about to read 6, iclass 33, count 2 2006.168.07:51:52.09#ibcon#read 6, iclass 33, count 2 2006.168.07:51:52.09#ibcon#end of sib2, iclass 33, count 2 2006.168.07:51:52.09#ibcon#*after write, iclass 33, count 2 2006.168.07:51:52.09#ibcon#*before return 0, iclass 33, count 2 2006.168.07:51:52.09#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:51:52.09#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.168.07:51:52.09#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.168.07:51:52.09#ibcon#ireg 7 cls_cnt 0 2006.168.07:51:52.09#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:51:52.21#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:51:52.21#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:51:52.21#ibcon#enter wrdev, iclass 33, count 0 2006.168.07:51:52.21#ibcon#first serial, iclass 33, count 0 2006.168.07:51:52.21#ibcon#enter sib2, iclass 33, count 0 2006.168.07:51:52.21#ibcon#flushed, iclass 33, count 0 2006.168.07:51:52.21#ibcon#about to write, iclass 33, count 0 2006.168.07:51:52.21#ibcon#wrote, iclass 33, count 0 2006.168.07:51:52.21#ibcon#about to read 3, iclass 33, count 0 2006.168.07:51:52.25#ibcon#read 3, iclass 33, count 0 2006.168.07:51:52.25#ibcon#about to read 4, iclass 33, count 0 2006.168.07:51:52.25#ibcon#read 4, iclass 33, count 0 2006.168.07:51:52.25#ibcon#about to read 5, iclass 33, count 0 2006.168.07:51:52.25#ibcon#read 5, iclass 33, count 0 2006.168.07:51:52.25#ibcon#about to read 6, iclass 33, count 0 2006.168.07:51:52.25#ibcon#read 6, iclass 33, count 0 2006.168.07:51:52.25#ibcon#end of sib2, iclass 33, count 0 2006.168.07:51:52.25#ibcon#*mode == 0, iclass 33, count 0 2006.168.07:51:52.25#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.168.07:51:52.25#ibcon#[27=USB\r\n] 2006.168.07:51:52.25#ibcon#*before write, iclass 33, count 0 2006.168.07:51:52.25#ibcon#enter sib2, iclass 33, count 0 2006.168.07:51:52.25#ibcon#flushed, iclass 33, count 0 2006.168.07:51:52.25#ibcon#about to write, iclass 33, count 0 2006.168.07:51:52.25#ibcon#wrote, iclass 33, count 0 2006.168.07:51:52.25#ibcon#about to read 3, iclass 33, count 0 2006.168.07:51:52.28#ibcon#read 3, iclass 33, count 0 2006.168.07:51:52.28#ibcon#about to read 4, iclass 33, count 0 2006.168.07:51:52.28#ibcon#read 4, iclass 33, count 0 2006.168.07:51:52.28#ibcon#about to read 5, iclass 33, count 0 2006.168.07:51:52.28#ibcon#read 5, iclass 33, count 0 2006.168.07:51:52.28#ibcon#about to read 6, iclass 33, count 0 2006.168.07:51:52.28#ibcon#read 6, iclass 33, count 0 2006.168.07:51:52.28#ibcon#end of sib2, iclass 33, count 0 2006.168.07:51:52.28#ibcon#*after write, iclass 33, count 0 2006.168.07:51:52.28#ibcon#*before return 0, iclass 33, count 0 2006.168.07:51:52.28#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:51:52.28#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.168.07:51:52.28#ibcon#about to clear, iclass 33 cls_cnt 0 2006.168.07:51:52.28#ibcon#cleared, iclass 33 cls_cnt 0 2006.168.07:51:52.28$vc4f8/vblo=6,752.99 2006.168.07:51:52.28#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.168.07:51:52.28#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.168.07:51:52.28#ibcon#ireg 17 cls_cnt 0 2006.168.07:51:52.28#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:51:52.28#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:51:52.28#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:51:52.28#ibcon#enter wrdev, iclass 35, count 0 2006.168.07:51:52.28#ibcon#first serial, iclass 35, count 0 2006.168.07:51:52.28#ibcon#enter sib2, iclass 35, count 0 2006.168.07:51:52.28#ibcon#flushed, iclass 35, count 0 2006.168.07:51:52.28#ibcon#about to write, iclass 35, count 0 2006.168.07:51:52.28#ibcon#wrote, iclass 35, count 0 2006.168.07:51:52.28#ibcon#about to read 3, iclass 35, count 0 2006.168.07:51:52.31#ibcon#read 3, iclass 35, count 0 2006.168.07:51:52.31#ibcon#about to read 4, iclass 35, count 0 2006.168.07:51:52.31#ibcon#read 4, iclass 35, count 0 2006.168.07:51:52.31#ibcon#about to read 5, iclass 35, count 0 2006.168.07:51:52.31#ibcon#read 5, iclass 35, count 0 2006.168.07:51:52.31#ibcon#about to read 6, iclass 35, count 0 2006.168.07:51:52.31#ibcon#read 6, iclass 35, count 0 2006.168.07:51:52.31#ibcon#end of sib2, iclass 35, count 0 2006.168.07:51:52.31#ibcon#*mode == 0, iclass 35, count 0 2006.168.07:51:52.31#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.168.07:51:52.31#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.07:51:52.31#ibcon#*before write, iclass 35, count 0 2006.168.07:51:52.31#ibcon#enter sib2, iclass 35, count 0 2006.168.07:51:52.31#ibcon#flushed, iclass 35, count 0 2006.168.07:51:52.31#ibcon#about to write, iclass 35, count 0 2006.168.07:51:52.31#ibcon#wrote, iclass 35, count 0 2006.168.07:51:52.31#ibcon#about to read 3, iclass 35, count 0 2006.168.07:51:52.35#ibcon#read 3, iclass 35, count 0 2006.168.07:51:52.35#ibcon#about to read 4, iclass 35, count 0 2006.168.07:51:52.35#ibcon#read 4, iclass 35, count 0 2006.168.07:51:52.35#ibcon#about to read 5, iclass 35, count 0 2006.168.07:51:52.35#ibcon#read 5, iclass 35, count 0 2006.168.07:51:52.35#ibcon#about to read 6, iclass 35, count 0 2006.168.07:51:52.35#ibcon#read 6, iclass 35, count 0 2006.168.07:51:52.35#ibcon#end of sib2, iclass 35, count 0 2006.168.07:51:52.35#ibcon#*after write, iclass 35, count 0 2006.168.07:51:52.35#ibcon#*before return 0, iclass 35, count 0 2006.168.07:51:52.35#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:51:52.35#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.168.07:51:52.35#ibcon#about to clear, iclass 35 cls_cnt 0 2006.168.07:51:52.35#ibcon#cleared, iclass 35 cls_cnt 0 2006.168.07:51:52.35$vc4f8/vb=6,4 2006.168.07:51:52.35#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.168.07:51:52.35#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.168.07:51:52.35#ibcon#ireg 11 cls_cnt 2 2006.168.07:51:52.35#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:51:52.39#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:51:52.39#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:51:52.39#ibcon#enter wrdev, iclass 37, count 2 2006.168.07:51:52.39#ibcon#first serial, iclass 37, count 2 2006.168.07:51:52.39#ibcon#enter sib2, iclass 37, count 2 2006.168.07:51:52.39#ibcon#flushed, iclass 37, count 2 2006.168.07:51:52.39#ibcon#about to write, iclass 37, count 2 2006.168.07:51:52.39#ibcon#wrote, iclass 37, count 2 2006.168.07:51:52.39#ibcon#about to read 3, iclass 37, count 2 2006.168.07:51:52.41#ibcon#read 3, iclass 37, count 2 2006.168.07:51:52.41#ibcon#about to read 4, iclass 37, count 2 2006.168.07:51:52.41#ibcon#read 4, iclass 37, count 2 2006.168.07:51:52.41#ibcon#about to read 5, iclass 37, count 2 2006.168.07:51:52.41#ibcon#read 5, iclass 37, count 2 2006.168.07:51:52.41#ibcon#about to read 6, iclass 37, count 2 2006.168.07:51:52.41#ibcon#read 6, iclass 37, count 2 2006.168.07:51:52.41#ibcon#end of sib2, iclass 37, count 2 2006.168.07:51:52.41#ibcon#*mode == 0, iclass 37, count 2 2006.168.07:51:52.41#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.168.07:51:52.41#ibcon#[27=AT06-04\r\n] 2006.168.07:51:52.41#ibcon#*before write, iclass 37, count 2 2006.168.07:51:52.41#ibcon#enter sib2, iclass 37, count 2 2006.168.07:51:52.41#ibcon#flushed, iclass 37, count 2 2006.168.07:51:52.41#ibcon#about to write, iclass 37, count 2 2006.168.07:51:52.41#ibcon#wrote, iclass 37, count 2 2006.168.07:51:52.41#ibcon#about to read 3, iclass 37, count 2 2006.168.07:51:52.44#ibcon#read 3, iclass 37, count 2 2006.168.07:51:52.44#ibcon#about to read 4, iclass 37, count 2 2006.168.07:51:52.44#ibcon#read 4, iclass 37, count 2 2006.168.07:51:52.44#ibcon#about to read 5, iclass 37, count 2 2006.168.07:51:52.44#ibcon#read 5, iclass 37, count 2 2006.168.07:51:52.44#ibcon#about to read 6, iclass 37, count 2 2006.168.07:51:52.44#ibcon#read 6, iclass 37, count 2 2006.168.07:51:52.44#ibcon#end of sib2, iclass 37, count 2 2006.168.07:51:52.44#ibcon#*after write, iclass 37, count 2 2006.168.07:51:52.44#ibcon#*before return 0, iclass 37, count 2 2006.168.07:51:52.44#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:51:52.44#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.168.07:51:52.44#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.168.07:51:52.44#ibcon#ireg 7 cls_cnt 0 2006.168.07:51:52.44#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:51:52.56#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:51:52.56#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:51:52.56#ibcon#enter wrdev, iclass 37, count 0 2006.168.07:51:52.56#ibcon#first serial, iclass 37, count 0 2006.168.07:51:52.56#ibcon#enter sib2, iclass 37, count 0 2006.168.07:51:52.56#ibcon#flushed, iclass 37, count 0 2006.168.07:51:52.56#ibcon#about to write, iclass 37, count 0 2006.168.07:51:52.56#ibcon#wrote, iclass 37, count 0 2006.168.07:51:52.56#ibcon#about to read 3, iclass 37, count 0 2006.168.07:51:52.58#ibcon#read 3, iclass 37, count 0 2006.168.07:51:52.58#ibcon#about to read 4, iclass 37, count 0 2006.168.07:51:52.58#ibcon#read 4, iclass 37, count 0 2006.168.07:51:52.58#ibcon#about to read 5, iclass 37, count 0 2006.168.07:51:52.58#ibcon#read 5, iclass 37, count 0 2006.168.07:51:52.58#ibcon#about to read 6, iclass 37, count 0 2006.168.07:51:52.58#ibcon#read 6, iclass 37, count 0 2006.168.07:51:52.58#ibcon#end of sib2, iclass 37, count 0 2006.168.07:51:52.58#ibcon#*mode == 0, iclass 37, count 0 2006.168.07:51:52.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.168.07:51:52.58#ibcon#[27=USB\r\n] 2006.168.07:51:52.58#ibcon#*before write, iclass 37, count 0 2006.168.07:51:52.58#ibcon#enter sib2, iclass 37, count 0 2006.168.07:51:52.58#ibcon#flushed, iclass 37, count 0 2006.168.07:51:52.58#ibcon#about to write, iclass 37, count 0 2006.168.07:51:52.58#ibcon#wrote, iclass 37, count 0 2006.168.07:51:52.58#ibcon#about to read 3, iclass 37, count 0 2006.168.07:51:52.61#ibcon#read 3, iclass 37, count 0 2006.168.07:51:52.61#ibcon#about to read 4, iclass 37, count 0 2006.168.07:51:52.61#ibcon#read 4, iclass 37, count 0 2006.168.07:51:52.61#ibcon#about to read 5, iclass 37, count 0 2006.168.07:51:52.61#ibcon#read 5, iclass 37, count 0 2006.168.07:51:52.61#ibcon#about to read 6, iclass 37, count 0 2006.168.07:51:52.61#ibcon#read 6, iclass 37, count 0 2006.168.07:51:52.61#ibcon#end of sib2, iclass 37, count 0 2006.168.07:51:52.61#ibcon#*after write, iclass 37, count 0 2006.168.07:51:52.61#ibcon#*before return 0, iclass 37, count 0 2006.168.07:51:52.61#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:51:52.61#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.168.07:51:52.61#ibcon#about to clear, iclass 37 cls_cnt 0 2006.168.07:51:52.61#ibcon#cleared, iclass 37 cls_cnt 0 2006.168.07:51:52.61$vc4f8/vabw=wide 2006.168.07:51:52.61#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.168.07:51:52.61#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.168.07:51:52.61#ibcon#ireg 8 cls_cnt 0 2006.168.07:51:52.61#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.168.07:51:52.61#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.168.07:51:52.61#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.168.07:51:52.61#ibcon#enter wrdev, iclass 39, count 0 2006.168.07:51:52.61#ibcon#first serial, iclass 39, count 0 2006.168.07:51:52.61#ibcon#enter sib2, iclass 39, count 0 2006.168.07:51:52.61#ibcon#flushed, iclass 39, count 0 2006.168.07:51:52.61#ibcon#about to write, iclass 39, count 0 2006.168.07:51:52.61#ibcon#wrote, iclass 39, count 0 2006.168.07:51:52.61#ibcon#about to read 3, iclass 39, count 0 2006.168.07:51:52.63#ibcon#read 3, iclass 39, count 0 2006.168.07:51:52.63#ibcon#about to read 4, iclass 39, count 0 2006.168.07:51:52.63#ibcon#read 4, iclass 39, count 0 2006.168.07:51:52.63#ibcon#about to read 5, iclass 39, count 0 2006.168.07:51:52.63#ibcon#read 5, iclass 39, count 0 2006.168.07:51:52.63#ibcon#about to read 6, iclass 39, count 0 2006.168.07:51:52.63#ibcon#read 6, iclass 39, count 0 2006.168.07:51:52.63#ibcon#end of sib2, iclass 39, count 0 2006.168.07:51:52.63#ibcon#*mode == 0, iclass 39, count 0 2006.168.07:51:52.63#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.168.07:51:52.63#ibcon#[25=BW32\r\n] 2006.168.07:51:52.63#ibcon#*before write, iclass 39, count 0 2006.168.07:51:52.63#ibcon#enter sib2, iclass 39, count 0 2006.168.07:51:52.63#ibcon#flushed, iclass 39, count 0 2006.168.07:51:52.63#ibcon#about to write, iclass 39, count 0 2006.168.07:51:52.63#ibcon#wrote, iclass 39, count 0 2006.168.07:51:52.63#ibcon#about to read 3, iclass 39, count 0 2006.168.07:51:52.66#ibcon#read 3, iclass 39, count 0 2006.168.07:51:52.66#ibcon#about to read 4, iclass 39, count 0 2006.168.07:51:52.66#ibcon#read 4, iclass 39, count 0 2006.168.07:51:52.66#ibcon#about to read 5, iclass 39, count 0 2006.168.07:51:52.66#ibcon#read 5, iclass 39, count 0 2006.168.07:51:52.66#ibcon#about to read 6, iclass 39, count 0 2006.168.07:51:52.66#ibcon#read 6, iclass 39, count 0 2006.168.07:51:52.66#ibcon#end of sib2, iclass 39, count 0 2006.168.07:51:52.66#ibcon#*after write, iclass 39, count 0 2006.168.07:51:52.66#ibcon#*before return 0, iclass 39, count 0 2006.168.07:51:52.66#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.168.07:51:52.66#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.168.07:51:52.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.168.07:51:52.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.168.07:51:52.66$vc4f8/vbbw=wide 2006.168.07:51:52.66#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.168.07:51:52.66#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.168.07:51:52.66#ibcon#ireg 8 cls_cnt 0 2006.168.07:51:52.66#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:51:52.73#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:51:52.73#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:51:52.73#ibcon#enter wrdev, iclass 3, count 0 2006.168.07:51:52.73#ibcon#first serial, iclass 3, count 0 2006.168.07:51:52.73#ibcon#enter sib2, iclass 3, count 0 2006.168.07:51:52.73#ibcon#flushed, iclass 3, count 0 2006.168.07:51:52.73#ibcon#about to write, iclass 3, count 0 2006.168.07:51:52.73#ibcon#wrote, iclass 3, count 0 2006.168.07:51:52.73#ibcon#about to read 3, iclass 3, count 0 2006.168.07:51:52.75#ibcon#read 3, iclass 3, count 0 2006.168.07:51:52.75#ibcon#about to read 4, iclass 3, count 0 2006.168.07:51:52.75#ibcon#read 4, iclass 3, count 0 2006.168.07:51:52.75#ibcon#about to read 5, iclass 3, count 0 2006.168.07:51:52.75#ibcon#read 5, iclass 3, count 0 2006.168.07:51:52.75#ibcon#about to read 6, iclass 3, count 0 2006.168.07:51:52.75#ibcon#read 6, iclass 3, count 0 2006.168.07:51:52.75#ibcon#end of sib2, iclass 3, count 0 2006.168.07:51:52.75#ibcon#*mode == 0, iclass 3, count 0 2006.168.07:51:52.75#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.168.07:51:52.75#ibcon#[27=BW32\r\n] 2006.168.07:51:52.75#ibcon#*before write, iclass 3, count 0 2006.168.07:51:52.75#ibcon#enter sib2, iclass 3, count 0 2006.168.07:51:52.75#ibcon#flushed, iclass 3, count 0 2006.168.07:51:52.75#ibcon#about to write, iclass 3, count 0 2006.168.07:51:52.75#ibcon#wrote, iclass 3, count 0 2006.168.07:51:52.75#ibcon#about to read 3, iclass 3, count 0 2006.168.07:51:52.78#ibcon#read 3, iclass 3, count 0 2006.168.07:51:52.78#ibcon#about to read 4, iclass 3, count 0 2006.168.07:51:52.78#ibcon#read 4, iclass 3, count 0 2006.168.07:51:52.78#ibcon#about to read 5, iclass 3, count 0 2006.168.07:51:52.78#ibcon#read 5, iclass 3, count 0 2006.168.07:51:52.78#ibcon#about to read 6, iclass 3, count 0 2006.168.07:51:52.78#ibcon#read 6, iclass 3, count 0 2006.168.07:51:52.78#ibcon#end of sib2, iclass 3, count 0 2006.168.07:51:52.78#ibcon#*after write, iclass 3, count 0 2006.168.07:51:52.78#ibcon#*before return 0, iclass 3, count 0 2006.168.07:51:52.78#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:51:52.78#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:51:52.78#ibcon#about to clear, iclass 3 cls_cnt 0 2006.168.07:51:52.78#ibcon#cleared, iclass 3 cls_cnt 0 2006.168.07:51:52.78$4f8m12a/ifd4f 2006.168.07:51:52.78$ifd4f/lo= 2006.168.07:51:52.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.07:51:52.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.07:51:52.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.07:51:52.78$ifd4f/patch= 2006.168.07:51:52.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.07:51:52.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.07:51:52.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.07:51:52.79$4f8m12a/"form=m,16.000,1:2 2006.168.07:51:52.79$4f8m12a/"tpicd 2006.168.07:51:52.79$4f8m12a/echo=off 2006.168.07:51:52.79$4f8m12a/xlog=off 2006.168.07:51:52.79:!2006.168.07:52:20 2006.168.07:52:03.14#trakl#Source acquired 2006.168.07:52:04.14#flagr#flagr/antenna,acquired 2006.168.07:52:20.01:preob 2006.168.07:52:21.14/onsource/TRACKING 2006.168.07:52:21.14:!2006.168.07:52:30 2006.168.07:52:30.00:data_valid=on 2006.168.07:52:30.00:midob 2006.168.07:52:30.13/onsource/TRACKING 2006.168.07:52:30.13/wx/27.32,1004.6,73 2006.168.07:52:30.20/cable/+6.4739E-03 2006.168.07:52:31.29/va/01,08,usb,yes,30,31 2006.168.07:52:31.29/va/02,07,usb,yes,30,31 2006.168.07:52:31.29/va/03,06,usb,yes,31,32 2006.168.07:52:31.29/va/04,07,usb,yes,30,33 2006.168.07:52:31.29/va/05,07,usb,yes,30,32 2006.168.07:52:31.29/va/06,06,usb,yes,29,29 2006.168.07:52:31.29/va/07,06,usb,yes,30,29 2006.168.07:52:31.29/va/08,07,usb,yes,28,28 2006.168.07:52:31.52/valo/01,532.99,yes,locked 2006.168.07:52:31.52/valo/02,572.99,yes,locked 2006.168.07:52:31.52/valo/03,672.99,yes,locked 2006.168.07:52:31.52/valo/04,832.99,yes,locked 2006.168.07:52:31.52/valo/05,652.99,yes,locked 2006.168.07:52:31.52/valo/06,772.99,yes,locked 2006.168.07:52:31.52/valo/07,832.99,yes,locked 2006.168.07:52:31.52/valo/08,852.99,yes,locked 2006.168.07:52:32.61/vb/01,04,usb,yes,29,28 2006.168.07:52:32.61/vb/02,04,usb,yes,31,32 2006.168.07:52:32.61/vb/03,04,usb,yes,27,31 2006.168.07:52:32.61/vb/04,04,usb,yes,28,28 2006.168.07:52:32.61/vb/05,04,usb,yes,27,31 2006.168.07:52:32.61/vb/06,04,usb,yes,28,31 2006.168.07:52:32.61/vb/07,04,usb,yes,30,30 2006.168.07:52:32.61/vb/08,04,usb,yes,28,31 2006.168.07:52:32.85/vblo/01,632.99,yes,locked 2006.168.07:52:32.85/vblo/02,640.99,yes,locked 2006.168.07:52:32.85/vblo/03,656.99,yes,locked 2006.168.07:52:32.85/vblo/04,712.99,yes,locked 2006.168.07:52:32.85/vblo/05,744.99,yes,locked 2006.168.07:52:32.85/vblo/06,752.99,yes,locked 2006.168.07:52:32.85/vblo/07,734.99,yes,locked 2006.168.07:52:32.85/vblo/08,744.99,yes,locked 2006.168.07:52:33.00/vabw/8 2006.168.07:52:33.15/vbbw/8 2006.168.07:52:33.24/xfe/off,on,15.2 2006.168.07:52:33.63/ifatt/23,28,28,28 2006.168.07:52:34.07/fmout-gps/S +4.18E-07 2006.168.07:52:34.12:!2006.168.07:53:30 2006.168.07:53:30.01:data_valid=off 2006.168.07:53:30.02:postob 2006.168.07:53:30.10/cable/+6.4721E-03 2006.168.07:53:30.10/wx/27.29,1004.6,73 2006.168.07:53:31.07/fmout-gps/S +4.19E-07 2006.168.07:53:31.08:scan_name=168-0755,k06168,60 2006.168.07:53:31.08:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.168.07:53:32.12#flagr#flagr/antenna,new-source 2006.168.07:53:32.13:checkk5 2006.168.07:53:32.50/chk_autoobs//k5ts1/ autoobs is running! 2006.168.07:53:32.88/chk_autoobs//k5ts2/ autoobs is running! 2006.168.07:53:33.26/chk_autoobs//k5ts3/ autoobs is running! 2006.168.07:53:33.64/chk_autoobs//k5ts4/ autoobs is running! 2006.168.07:53:34.02/chk_obsdata//k5ts1/T1680752??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:53:34.38/chk_obsdata//k5ts2/T1680752??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:53:34.75/chk_obsdata//k5ts3/T1680752??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:53:35.12/chk_obsdata//k5ts4/T1680752??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:53:35.82/k5log//k5ts1_log_newline 2006.168.07:53:36.51/k5log//k5ts2_log_newline 2006.168.07:53:37.20/k5log//k5ts3_log_newline 2006.168.07:53:37.89/k5log//k5ts4_log_newline 2006.168.07:53:37.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.07:53:37.92:4f8m12a=2 2006.168.07:53:37.92$4f8m12a/echo=on 2006.168.07:53:37.92$4f8m12a/pcalon 2006.168.07:53:37.92$pcalon/"no phase cal control is implemented here 2006.168.07:53:37.92$4f8m12a/"tpicd=stop 2006.168.07:53:37.92$4f8m12a/vc4f8 2006.168.07:53:37.92$vc4f8/valo=1,532.99 2006.168.07:53:37.92#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.168.07:53:37.92#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.168.07:53:37.92#ibcon#ireg 17 cls_cnt 0 2006.168.07:53:37.92#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.168.07:53:37.92#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.168.07:53:37.92#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.168.07:53:37.92#ibcon#enter wrdev, iclass 12, count 0 2006.168.07:53:37.92#ibcon#first serial, iclass 12, count 0 2006.168.07:53:37.92#ibcon#enter sib2, iclass 12, count 0 2006.168.07:53:37.92#ibcon#flushed, iclass 12, count 0 2006.168.07:53:37.92#ibcon#about to write, iclass 12, count 0 2006.168.07:53:37.92#ibcon#wrote, iclass 12, count 0 2006.168.07:53:37.92#ibcon#about to read 3, iclass 12, count 0 2006.168.07:53:37.97#ibcon#read 3, iclass 12, count 0 2006.168.07:53:37.97#ibcon#about to read 4, iclass 12, count 0 2006.168.07:53:37.97#ibcon#read 4, iclass 12, count 0 2006.168.07:53:37.97#ibcon#about to read 5, iclass 12, count 0 2006.168.07:53:37.97#ibcon#read 5, iclass 12, count 0 2006.168.07:53:37.97#ibcon#about to read 6, iclass 12, count 0 2006.168.07:53:37.97#ibcon#read 6, iclass 12, count 0 2006.168.07:53:37.97#ibcon#end of sib2, iclass 12, count 0 2006.168.07:53:37.97#ibcon#*mode == 0, iclass 12, count 0 2006.168.07:53:37.97#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.168.07:53:37.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.07:53:37.97#ibcon#*before write, iclass 12, count 0 2006.168.07:53:37.97#ibcon#enter sib2, iclass 12, count 0 2006.168.07:53:37.97#ibcon#flushed, iclass 12, count 0 2006.168.07:53:37.97#ibcon#about to write, iclass 12, count 0 2006.168.07:53:37.97#ibcon#wrote, iclass 12, count 0 2006.168.07:53:37.97#ibcon#about to read 3, iclass 12, count 0 2006.168.07:53:38.01#ibcon#read 3, iclass 12, count 0 2006.168.07:53:38.01#ibcon#about to read 4, iclass 12, count 0 2006.168.07:53:38.01#ibcon#read 4, iclass 12, count 0 2006.168.07:53:38.01#ibcon#about to read 5, iclass 12, count 0 2006.168.07:53:38.01#ibcon#read 5, iclass 12, count 0 2006.168.07:53:38.01#ibcon#about to read 6, iclass 12, count 0 2006.168.07:53:38.01#ibcon#read 6, iclass 12, count 0 2006.168.07:53:38.01#ibcon#end of sib2, iclass 12, count 0 2006.168.07:53:38.01#ibcon#*after write, iclass 12, count 0 2006.168.07:53:38.01#ibcon#*before return 0, iclass 12, count 0 2006.168.07:53:38.01#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.168.07:53:38.01#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.168.07:53:38.01#ibcon#about to clear, iclass 12 cls_cnt 0 2006.168.07:53:38.01#ibcon#cleared, iclass 12 cls_cnt 0 2006.168.07:53:38.01$vc4f8/va=1,8 2006.168.07:53:38.01#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.168.07:53:38.01#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.168.07:53:38.01#ibcon#ireg 11 cls_cnt 2 2006.168.07:53:38.01#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.168.07:53:38.01#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.168.07:53:38.01#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.168.07:53:38.01#ibcon#enter wrdev, iclass 14, count 2 2006.168.07:53:38.01#ibcon#first serial, iclass 14, count 2 2006.168.07:53:38.01#ibcon#enter sib2, iclass 14, count 2 2006.168.07:53:38.01#ibcon#flushed, iclass 14, count 2 2006.168.07:53:38.01#ibcon#about to write, iclass 14, count 2 2006.168.07:53:38.01#ibcon#wrote, iclass 14, count 2 2006.168.07:53:38.01#ibcon#about to read 3, iclass 14, count 2 2006.168.07:53:38.03#ibcon#read 3, iclass 14, count 2 2006.168.07:53:38.03#ibcon#about to read 4, iclass 14, count 2 2006.168.07:53:38.03#ibcon#read 4, iclass 14, count 2 2006.168.07:53:38.03#ibcon#about to read 5, iclass 14, count 2 2006.168.07:53:38.03#ibcon#read 5, iclass 14, count 2 2006.168.07:53:38.03#ibcon#about to read 6, iclass 14, count 2 2006.168.07:53:38.03#ibcon#read 6, iclass 14, count 2 2006.168.07:53:38.03#ibcon#end of sib2, iclass 14, count 2 2006.168.07:53:38.03#ibcon#*mode == 0, iclass 14, count 2 2006.168.07:53:38.03#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.168.07:53:38.03#ibcon#[25=AT01-08\r\n] 2006.168.07:53:38.03#ibcon#*before write, iclass 14, count 2 2006.168.07:53:38.03#ibcon#enter sib2, iclass 14, count 2 2006.168.07:53:38.03#ibcon#flushed, iclass 14, count 2 2006.168.07:53:38.03#ibcon#about to write, iclass 14, count 2 2006.168.07:53:38.03#ibcon#wrote, iclass 14, count 2 2006.168.07:53:38.03#ibcon#about to read 3, iclass 14, count 2 2006.168.07:53:38.06#ibcon#read 3, iclass 14, count 2 2006.168.07:53:38.06#ibcon#about to read 4, iclass 14, count 2 2006.168.07:53:38.06#ibcon#read 4, iclass 14, count 2 2006.168.07:53:38.06#ibcon#about to read 5, iclass 14, count 2 2006.168.07:53:38.06#ibcon#read 5, iclass 14, count 2 2006.168.07:53:38.06#ibcon#about to read 6, iclass 14, count 2 2006.168.07:53:38.06#ibcon#read 6, iclass 14, count 2 2006.168.07:53:38.06#ibcon#end of sib2, iclass 14, count 2 2006.168.07:53:38.06#ibcon#*after write, iclass 14, count 2 2006.168.07:53:38.06#ibcon#*before return 0, iclass 14, count 2 2006.168.07:53:38.06#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.168.07:53:38.06#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.168.07:53:38.06#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.168.07:53:38.06#ibcon#ireg 7 cls_cnt 0 2006.168.07:53:38.06#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.168.07:53:38.18#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.168.07:53:38.18#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.168.07:53:38.18#ibcon#enter wrdev, iclass 14, count 0 2006.168.07:53:38.18#ibcon#first serial, iclass 14, count 0 2006.168.07:53:38.18#ibcon#enter sib2, iclass 14, count 0 2006.168.07:53:38.18#ibcon#flushed, iclass 14, count 0 2006.168.07:53:38.18#ibcon#about to write, iclass 14, count 0 2006.168.07:53:38.18#ibcon#wrote, iclass 14, count 0 2006.168.07:53:38.18#ibcon#about to read 3, iclass 14, count 0 2006.168.07:53:38.20#ibcon#read 3, iclass 14, count 0 2006.168.07:53:38.20#ibcon#about to read 4, iclass 14, count 0 2006.168.07:53:38.20#ibcon#read 4, iclass 14, count 0 2006.168.07:53:38.20#ibcon#about to read 5, iclass 14, count 0 2006.168.07:53:38.20#ibcon#read 5, iclass 14, count 0 2006.168.07:53:38.20#ibcon#about to read 6, iclass 14, count 0 2006.168.07:53:38.20#ibcon#read 6, iclass 14, count 0 2006.168.07:53:38.20#ibcon#end of sib2, iclass 14, count 0 2006.168.07:53:38.20#ibcon#*mode == 0, iclass 14, count 0 2006.168.07:53:38.20#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.168.07:53:38.20#ibcon#[25=USB\r\n] 2006.168.07:53:38.20#ibcon#*before write, iclass 14, count 0 2006.168.07:53:38.20#ibcon#enter sib2, iclass 14, count 0 2006.168.07:53:38.20#ibcon#flushed, iclass 14, count 0 2006.168.07:53:38.20#ibcon#about to write, iclass 14, count 0 2006.168.07:53:38.20#ibcon#wrote, iclass 14, count 0 2006.168.07:53:38.20#ibcon#about to read 3, iclass 14, count 0 2006.168.07:53:38.23#ibcon#read 3, iclass 14, count 0 2006.168.07:53:38.23#ibcon#about to read 4, iclass 14, count 0 2006.168.07:53:38.23#ibcon#read 4, iclass 14, count 0 2006.168.07:53:38.23#ibcon#about to read 5, iclass 14, count 0 2006.168.07:53:38.23#ibcon#read 5, iclass 14, count 0 2006.168.07:53:38.23#ibcon#about to read 6, iclass 14, count 0 2006.168.07:53:38.23#ibcon#read 6, iclass 14, count 0 2006.168.07:53:38.23#ibcon#end of sib2, iclass 14, count 0 2006.168.07:53:38.23#ibcon#*after write, iclass 14, count 0 2006.168.07:53:38.23#ibcon#*before return 0, iclass 14, count 0 2006.168.07:53:38.23#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.168.07:53:38.23#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.168.07:53:38.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.168.07:53:38.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.168.07:53:38.23$vc4f8/valo=2,572.99 2006.168.07:53:38.23#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.168.07:53:38.23#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.168.07:53:38.23#ibcon#ireg 17 cls_cnt 0 2006.168.07:53:38.23#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:53:38.23#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:53:38.23#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:53:38.23#ibcon#enter wrdev, iclass 16, count 0 2006.168.07:53:38.23#ibcon#first serial, iclass 16, count 0 2006.168.07:53:38.23#ibcon#enter sib2, iclass 16, count 0 2006.168.07:53:38.23#ibcon#flushed, iclass 16, count 0 2006.168.07:53:38.23#ibcon#about to write, iclass 16, count 0 2006.168.07:53:38.23#ibcon#wrote, iclass 16, count 0 2006.168.07:53:38.23#ibcon#about to read 3, iclass 16, count 0 2006.168.07:53:38.26#ibcon#read 3, iclass 16, count 0 2006.168.07:53:38.26#ibcon#about to read 4, iclass 16, count 0 2006.168.07:53:38.26#ibcon#read 4, iclass 16, count 0 2006.168.07:53:38.26#ibcon#about to read 5, iclass 16, count 0 2006.168.07:53:38.26#ibcon#read 5, iclass 16, count 0 2006.168.07:53:38.26#ibcon#about to read 6, iclass 16, count 0 2006.168.07:53:38.26#ibcon#read 6, iclass 16, count 0 2006.168.07:53:38.26#ibcon#end of sib2, iclass 16, count 0 2006.168.07:53:38.26#ibcon#*mode == 0, iclass 16, count 0 2006.168.07:53:38.26#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.168.07:53:38.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.07:53:38.26#ibcon#*before write, iclass 16, count 0 2006.168.07:53:38.26#ibcon#enter sib2, iclass 16, count 0 2006.168.07:53:38.26#ibcon#flushed, iclass 16, count 0 2006.168.07:53:38.26#ibcon#about to write, iclass 16, count 0 2006.168.07:53:38.26#ibcon#wrote, iclass 16, count 0 2006.168.07:53:38.26#ibcon#about to read 3, iclass 16, count 0 2006.168.07:53:38.29#ibcon#read 3, iclass 16, count 0 2006.168.07:53:38.29#ibcon#about to read 4, iclass 16, count 0 2006.168.07:53:38.29#ibcon#read 4, iclass 16, count 0 2006.168.07:53:38.29#ibcon#about to read 5, iclass 16, count 0 2006.168.07:53:38.29#ibcon#read 5, iclass 16, count 0 2006.168.07:53:38.29#ibcon#about to read 6, iclass 16, count 0 2006.168.07:53:38.29#ibcon#read 6, iclass 16, count 0 2006.168.07:53:38.29#ibcon#end of sib2, iclass 16, count 0 2006.168.07:53:38.29#ibcon#*after write, iclass 16, count 0 2006.168.07:53:38.29#ibcon#*before return 0, iclass 16, count 0 2006.168.07:53:38.29#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:53:38.29#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:53:38.29#ibcon#about to clear, iclass 16 cls_cnt 0 2006.168.07:53:38.29#ibcon#cleared, iclass 16 cls_cnt 0 2006.168.07:53:38.29$vc4f8/va=2,7 2006.168.07:53:38.29#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.168.07:53:38.29#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.168.07:53:38.29#ibcon#ireg 11 cls_cnt 2 2006.168.07:53:38.29#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:53:38.36#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:53:38.36#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:53:38.36#ibcon#enter wrdev, iclass 18, count 2 2006.168.07:53:38.36#ibcon#first serial, iclass 18, count 2 2006.168.07:53:38.36#ibcon#enter sib2, iclass 18, count 2 2006.168.07:53:38.36#ibcon#flushed, iclass 18, count 2 2006.168.07:53:38.36#ibcon#about to write, iclass 18, count 2 2006.168.07:53:38.36#ibcon#wrote, iclass 18, count 2 2006.168.07:53:38.36#ibcon#about to read 3, iclass 18, count 2 2006.168.07:53:38.38#ibcon#read 3, iclass 18, count 2 2006.168.07:53:38.38#ibcon#about to read 4, iclass 18, count 2 2006.168.07:53:38.38#ibcon#read 4, iclass 18, count 2 2006.168.07:53:38.38#ibcon#about to read 5, iclass 18, count 2 2006.168.07:53:38.38#ibcon#read 5, iclass 18, count 2 2006.168.07:53:38.38#ibcon#about to read 6, iclass 18, count 2 2006.168.07:53:38.38#ibcon#read 6, iclass 18, count 2 2006.168.07:53:38.38#ibcon#end of sib2, iclass 18, count 2 2006.168.07:53:38.38#ibcon#*mode == 0, iclass 18, count 2 2006.168.07:53:38.38#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.168.07:53:38.38#ibcon#[25=AT02-07\r\n] 2006.168.07:53:38.38#ibcon#*before write, iclass 18, count 2 2006.168.07:53:38.38#ibcon#enter sib2, iclass 18, count 2 2006.168.07:53:38.38#ibcon#flushed, iclass 18, count 2 2006.168.07:53:38.38#ibcon#about to write, iclass 18, count 2 2006.168.07:53:38.38#ibcon#wrote, iclass 18, count 2 2006.168.07:53:38.38#ibcon#about to read 3, iclass 18, count 2 2006.168.07:53:38.40#ibcon#read 3, iclass 18, count 2 2006.168.07:53:38.40#ibcon#about to read 4, iclass 18, count 2 2006.168.07:53:38.40#ibcon#read 4, iclass 18, count 2 2006.168.07:53:38.40#ibcon#about to read 5, iclass 18, count 2 2006.168.07:53:38.40#ibcon#read 5, iclass 18, count 2 2006.168.07:53:38.40#ibcon#about to read 6, iclass 18, count 2 2006.168.07:53:38.40#ibcon#read 6, iclass 18, count 2 2006.168.07:53:38.40#ibcon#end of sib2, iclass 18, count 2 2006.168.07:53:38.40#ibcon#*after write, iclass 18, count 2 2006.168.07:53:38.40#ibcon#*before return 0, iclass 18, count 2 2006.168.07:53:38.40#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:53:38.40#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:53:38.40#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.168.07:53:38.40#ibcon#ireg 7 cls_cnt 0 2006.168.07:53:38.40#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:53:38.52#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:53:38.52#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:53:38.52#ibcon#enter wrdev, iclass 18, count 0 2006.168.07:53:38.52#ibcon#first serial, iclass 18, count 0 2006.168.07:53:38.52#ibcon#enter sib2, iclass 18, count 0 2006.168.07:53:38.52#ibcon#flushed, iclass 18, count 0 2006.168.07:53:38.52#ibcon#about to write, iclass 18, count 0 2006.168.07:53:38.52#ibcon#wrote, iclass 18, count 0 2006.168.07:53:38.52#ibcon#about to read 3, iclass 18, count 0 2006.168.07:53:38.54#ibcon#read 3, iclass 18, count 0 2006.168.07:53:38.54#ibcon#about to read 4, iclass 18, count 0 2006.168.07:53:38.54#ibcon#read 4, iclass 18, count 0 2006.168.07:53:38.54#ibcon#about to read 5, iclass 18, count 0 2006.168.07:53:38.54#ibcon#read 5, iclass 18, count 0 2006.168.07:53:38.54#ibcon#about to read 6, iclass 18, count 0 2006.168.07:53:38.54#ibcon#read 6, iclass 18, count 0 2006.168.07:53:38.54#ibcon#end of sib2, iclass 18, count 0 2006.168.07:53:38.54#ibcon#*mode == 0, iclass 18, count 0 2006.168.07:53:38.54#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.07:53:38.54#ibcon#[25=USB\r\n] 2006.168.07:53:38.54#ibcon#*before write, iclass 18, count 0 2006.168.07:53:38.54#ibcon#enter sib2, iclass 18, count 0 2006.168.07:53:38.54#ibcon#flushed, iclass 18, count 0 2006.168.07:53:38.54#ibcon#about to write, iclass 18, count 0 2006.168.07:53:38.54#ibcon#wrote, iclass 18, count 0 2006.168.07:53:38.54#ibcon#about to read 3, iclass 18, count 0 2006.168.07:53:38.57#ibcon#read 3, iclass 18, count 0 2006.168.07:53:38.57#ibcon#about to read 4, iclass 18, count 0 2006.168.07:53:38.57#ibcon#read 4, iclass 18, count 0 2006.168.07:53:38.57#ibcon#about to read 5, iclass 18, count 0 2006.168.07:53:38.57#ibcon#read 5, iclass 18, count 0 2006.168.07:53:38.57#ibcon#about to read 6, iclass 18, count 0 2006.168.07:53:38.57#ibcon#read 6, iclass 18, count 0 2006.168.07:53:38.57#ibcon#end of sib2, iclass 18, count 0 2006.168.07:53:38.57#ibcon#*after write, iclass 18, count 0 2006.168.07:53:38.57#ibcon#*before return 0, iclass 18, count 0 2006.168.07:53:38.57#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:53:38.57#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:53:38.57#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.07:53:38.57#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.07:53:38.57$vc4f8/valo=3,672.99 2006.168.07:53:38.57#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.168.07:53:38.57#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.168.07:53:38.57#ibcon#ireg 17 cls_cnt 0 2006.168.07:53:38.57#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:53:38.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:53:38.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:53:38.57#ibcon#enter wrdev, iclass 20, count 0 2006.168.07:53:38.57#ibcon#first serial, iclass 20, count 0 2006.168.07:53:38.57#ibcon#enter sib2, iclass 20, count 0 2006.168.07:53:38.57#ibcon#flushed, iclass 20, count 0 2006.168.07:53:38.57#ibcon#about to write, iclass 20, count 0 2006.168.07:53:38.57#ibcon#wrote, iclass 20, count 0 2006.168.07:53:38.57#ibcon#about to read 3, iclass 20, count 0 2006.168.07:53:38.59#ibcon#read 3, iclass 20, count 0 2006.168.07:53:38.59#ibcon#about to read 4, iclass 20, count 0 2006.168.07:53:38.59#ibcon#read 4, iclass 20, count 0 2006.168.07:53:38.59#ibcon#about to read 5, iclass 20, count 0 2006.168.07:53:38.59#ibcon#read 5, iclass 20, count 0 2006.168.07:53:38.59#ibcon#about to read 6, iclass 20, count 0 2006.168.07:53:38.59#ibcon#read 6, iclass 20, count 0 2006.168.07:53:38.59#ibcon#end of sib2, iclass 20, count 0 2006.168.07:53:38.59#ibcon#*mode == 0, iclass 20, count 0 2006.168.07:53:38.59#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.168.07:53:38.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.07:53:38.59#ibcon#*before write, iclass 20, count 0 2006.168.07:53:38.59#ibcon#enter sib2, iclass 20, count 0 2006.168.07:53:38.59#ibcon#flushed, iclass 20, count 0 2006.168.07:53:38.59#ibcon#about to write, iclass 20, count 0 2006.168.07:53:38.59#ibcon#wrote, iclass 20, count 0 2006.168.07:53:38.59#ibcon#about to read 3, iclass 20, count 0 2006.168.07:53:38.63#ibcon#read 3, iclass 20, count 0 2006.168.07:53:38.63#ibcon#about to read 4, iclass 20, count 0 2006.168.07:53:38.63#ibcon#read 4, iclass 20, count 0 2006.168.07:53:38.63#ibcon#about to read 5, iclass 20, count 0 2006.168.07:53:38.63#ibcon#read 5, iclass 20, count 0 2006.168.07:53:38.63#ibcon#about to read 6, iclass 20, count 0 2006.168.07:53:38.63#ibcon#read 6, iclass 20, count 0 2006.168.07:53:38.63#ibcon#end of sib2, iclass 20, count 0 2006.168.07:53:38.63#ibcon#*after write, iclass 20, count 0 2006.168.07:53:38.63#ibcon#*before return 0, iclass 20, count 0 2006.168.07:53:38.63#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:53:38.63#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:53:38.63#ibcon#about to clear, iclass 20 cls_cnt 0 2006.168.07:53:38.63#ibcon#cleared, iclass 20 cls_cnt 0 2006.168.07:53:38.63$vc4f8/va=3,6 2006.168.07:53:38.63#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.168.07:53:38.63#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.168.07:53:38.63#ibcon#ireg 11 cls_cnt 2 2006.168.07:53:38.63#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:53:38.69#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:53:38.69#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:53:38.69#ibcon#enter wrdev, iclass 22, count 2 2006.168.07:53:38.69#ibcon#first serial, iclass 22, count 2 2006.168.07:53:38.69#ibcon#enter sib2, iclass 22, count 2 2006.168.07:53:38.69#ibcon#flushed, iclass 22, count 2 2006.168.07:53:38.69#ibcon#about to write, iclass 22, count 2 2006.168.07:53:38.69#ibcon#wrote, iclass 22, count 2 2006.168.07:53:38.69#ibcon#about to read 3, iclass 22, count 2 2006.168.07:53:38.71#ibcon#read 3, iclass 22, count 2 2006.168.07:53:38.71#ibcon#about to read 4, iclass 22, count 2 2006.168.07:53:38.71#ibcon#read 4, iclass 22, count 2 2006.168.07:53:38.71#ibcon#about to read 5, iclass 22, count 2 2006.168.07:53:38.71#ibcon#read 5, iclass 22, count 2 2006.168.07:53:38.71#ibcon#about to read 6, iclass 22, count 2 2006.168.07:53:38.71#ibcon#read 6, iclass 22, count 2 2006.168.07:53:38.71#ibcon#end of sib2, iclass 22, count 2 2006.168.07:53:38.71#ibcon#*mode == 0, iclass 22, count 2 2006.168.07:53:38.71#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.168.07:53:38.71#ibcon#[25=AT03-06\r\n] 2006.168.07:53:38.71#ibcon#*before write, iclass 22, count 2 2006.168.07:53:38.71#ibcon#enter sib2, iclass 22, count 2 2006.168.07:53:38.71#ibcon#flushed, iclass 22, count 2 2006.168.07:53:38.71#ibcon#about to write, iclass 22, count 2 2006.168.07:53:38.71#ibcon#wrote, iclass 22, count 2 2006.168.07:53:38.71#ibcon#about to read 3, iclass 22, count 2 2006.168.07:53:38.74#ibcon#read 3, iclass 22, count 2 2006.168.07:53:38.74#ibcon#about to read 4, iclass 22, count 2 2006.168.07:53:38.74#ibcon#read 4, iclass 22, count 2 2006.168.07:53:38.74#ibcon#about to read 5, iclass 22, count 2 2006.168.07:53:38.74#ibcon#read 5, iclass 22, count 2 2006.168.07:53:38.74#ibcon#about to read 6, iclass 22, count 2 2006.168.07:53:38.74#ibcon#read 6, iclass 22, count 2 2006.168.07:53:38.74#ibcon#end of sib2, iclass 22, count 2 2006.168.07:53:38.74#ibcon#*after write, iclass 22, count 2 2006.168.07:53:38.74#ibcon#*before return 0, iclass 22, count 2 2006.168.07:53:38.74#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:53:38.74#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:53:38.74#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.168.07:53:38.74#ibcon#ireg 7 cls_cnt 0 2006.168.07:53:38.74#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:53:38.86#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:53:38.86#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:53:38.86#ibcon#enter wrdev, iclass 22, count 0 2006.168.07:53:38.86#ibcon#first serial, iclass 22, count 0 2006.168.07:53:38.86#ibcon#enter sib2, iclass 22, count 0 2006.168.07:53:38.86#ibcon#flushed, iclass 22, count 0 2006.168.07:53:38.86#ibcon#about to write, iclass 22, count 0 2006.168.07:53:38.86#ibcon#wrote, iclass 22, count 0 2006.168.07:53:38.86#ibcon#about to read 3, iclass 22, count 0 2006.168.07:53:38.88#ibcon#read 3, iclass 22, count 0 2006.168.07:53:38.88#ibcon#about to read 4, iclass 22, count 0 2006.168.07:53:38.88#ibcon#read 4, iclass 22, count 0 2006.168.07:53:38.88#ibcon#about to read 5, iclass 22, count 0 2006.168.07:53:38.88#ibcon#read 5, iclass 22, count 0 2006.168.07:53:38.88#ibcon#about to read 6, iclass 22, count 0 2006.168.07:53:38.88#ibcon#read 6, iclass 22, count 0 2006.168.07:53:38.88#ibcon#end of sib2, iclass 22, count 0 2006.168.07:53:38.88#ibcon#*mode == 0, iclass 22, count 0 2006.168.07:53:38.88#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.168.07:53:38.88#ibcon#[25=USB\r\n] 2006.168.07:53:38.88#ibcon#*before write, iclass 22, count 0 2006.168.07:53:38.88#ibcon#enter sib2, iclass 22, count 0 2006.168.07:53:38.88#ibcon#flushed, iclass 22, count 0 2006.168.07:53:38.88#ibcon#about to write, iclass 22, count 0 2006.168.07:53:38.88#ibcon#wrote, iclass 22, count 0 2006.168.07:53:38.88#ibcon#about to read 3, iclass 22, count 0 2006.168.07:53:38.91#ibcon#read 3, iclass 22, count 0 2006.168.07:53:38.91#ibcon#about to read 4, iclass 22, count 0 2006.168.07:53:38.91#ibcon#read 4, iclass 22, count 0 2006.168.07:53:38.91#ibcon#about to read 5, iclass 22, count 0 2006.168.07:53:38.91#ibcon#read 5, iclass 22, count 0 2006.168.07:53:38.91#ibcon#about to read 6, iclass 22, count 0 2006.168.07:53:38.91#ibcon#read 6, iclass 22, count 0 2006.168.07:53:38.91#ibcon#end of sib2, iclass 22, count 0 2006.168.07:53:38.91#ibcon#*after write, iclass 22, count 0 2006.168.07:53:38.91#ibcon#*before return 0, iclass 22, count 0 2006.168.07:53:38.91#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:53:38.91#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:53:38.91#ibcon#about to clear, iclass 22 cls_cnt 0 2006.168.07:53:38.91#ibcon#cleared, iclass 22 cls_cnt 0 2006.168.07:53:38.91$vc4f8/valo=4,832.99 2006.168.07:53:38.91#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.168.07:53:38.91#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.168.07:53:38.91#ibcon#ireg 17 cls_cnt 0 2006.168.07:53:38.91#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.168.07:53:38.91#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.168.07:53:38.91#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.168.07:53:38.91#ibcon#enter wrdev, iclass 24, count 0 2006.168.07:53:38.91#ibcon#first serial, iclass 24, count 0 2006.168.07:53:38.91#ibcon#enter sib2, iclass 24, count 0 2006.168.07:53:38.91#ibcon#flushed, iclass 24, count 0 2006.168.07:53:38.91#ibcon#about to write, iclass 24, count 0 2006.168.07:53:38.91#ibcon#wrote, iclass 24, count 0 2006.168.07:53:38.91#ibcon#about to read 3, iclass 24, count 0 2006.168.07:53:38.93#ibcon#read 3, iclass 24, count 0 2006.168.07:53:38.93#ibcon#about to read 4, iclass 24, count 0 2006.168.07:53:38.93#ibcon#read 4, iclass 24, count 0 2006.168.07:53:38.93#ibcon#about to read 5, iclass 24, count 0 2006.168.07:53:38.93#ibcon#read 5, iclass 24, count 0 2006.168.07:53:38.93#ibcon#about to read 6, iclass 24, count 0 2006.168.07:53:38.93#ibcon#read 6, iclass 24, count 0 2006.168.07:53:38.93#ibcon#end of sib2, iclass 24, count 0 2006.168.07:53:38.93#ibcon#*mode == 0, iclass 24, count 0 2006.168.07:53:38.93#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.168.07:53:38.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.07:53:38.93#ibcon#*before write, iclass 24, count 0 2006.168.07:53:38.93#ibcon#enter sib2, iclass 24, count 0 2006.168.07:53:38.93#ibcon#flushed, iclass 24, count 0 2006.168.07:53:38.93#ibcon#about to write, iclass 24, count 0 2006.168.07:53:38.93#ibcon#wrote, iclass 24, count 0 2006.168.07:53:38.93#ibcon#about to read 3, iclass 24, count 0 2006.168.07:53:38.97#ibcon#read 3, iclass 24, count 0 2006.168.07:53:38.97#ibcon#about to read 4, iclass 24, count 0 2006.168.07:53:38.97#ibcon#read 4, iclass 24, count 0 2006.168.07:53:38.97#ibcon#about to read 5, iclass 24, count 0 2006.168.07:53:38.97#ibcon#read 5, iclass 24, count 0 2006.168.07:53:38.97#ibcon#about to read 6, iclass 24, count 0 2006.168.07:53:38.97#ibcon#read 6, iclass 24, count 0 2006.168.07:53:38.97#ibcon#end of sib2, iclass 24, count 0 2006.168.07:53:38.97#ibcon#*after write, iclass 24, count 0 2006.168.07:53:38.97#ibcon#*before return 0, iclass 24, count 0 2006.168.07:53:38.97#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.168.07:53:38.97#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.168.07:53:38.97#ibcon#about to clear, iclass 24 cls_cnt 0 2006.168.07:53:38.97#ibcon#cleared, iclass 24 cls_cnt 0 2006.168.07:53:38.97$vc4f8/va=4,7 2006.168.07:53:38.97#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.168.07:53:38.97#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.168.07:53:38.97#ibcon#ireg 11 cls_cnt 2 2006.168.07:53:38.97#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.168.07:53:39.03#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.168.07:53:39.03#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.168.07:53:39.03#ibcon#enter wrdev, iclass 26, count 2 2006.168.07:53:39.03#ibcon#first serial, iclass 26, count 2 2006.168.07:53:39.03#ibcon#enter sib2, iclass 26, count 2 2006.168.07:53:39.03#ibcon#flushed, iclass 26, count 2 2006.168.07:53:39.03#ibcon#about to write, iclass 26, count 2 2006.168.07:53:39.03#ibcon#wrote, iclass 26, count 2 2006.168.07:53:39.03#ibcon#about to read 3, iclass 26, count 2 2006.168.07:53:39.05#ibcon#read 3, iclass 26, count 2 2006.168.07:53:39.05#ibcon#about to read 4, iclass 26, count 2 2006.168.07:53:39.05#ibcon#read 4, iclass 26, count 2 2006.168.07:53:39.05#ibcon#about to read 5, iclass 26, count 2 2006.168.07:53:39.05#ibcon#read 5, iclass 26, count 2 2006.168.07:53:39.05#ibcon#about to read 6, iclass 26, count 2 2006.168.07:53:39.05#ibcon#read 6, iclass 26, count 2 2006.168.07:53:39.05#ibcon#end of sib2, iclass 26, count 2 2006.168.07:53:39.05#ibcon#*mode == 0, iclass 26, count 2 2006.168.07:53:39.05#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.168.07:53:39.05#ibcon#[25=AT04-07\r\n] 2006.168.07:53:39.05#ibcon#*before write, iclass 26, count 2 2006.168.07:53:39.05#ibcon#enter sib2, iclass 26, count 2 2006.168.07:53:39.05#ibcon#flushed, iclass 26, count 2 2006.168.07:53:39.05#ibcon#about to write, iclass 26, count 2 2006.168.07:53:39.05#ibcon#wrote, iclass 26, count 2 2006.168.07:53:39.05#ibcon#about to read 3, iclass 26, count 2 2006.168.07:53:39.08#ibcon#read 3, iclass 26, count 2 2006.168.07:53:39.08#ibcon#about to read 4, iclass 26, count 2 2006.168.07:53:39.08#ibcon#read 4, iclass 26, count 2 2006.168.07:53:39.08#ibcon#about to read 5, iclass 26, count 2 2006.168.07:53:39.08#ibcon#read 5, iclass 26, count 2 2006.168.07:53:39.08#ibcon#about to read 6, iclass 26, count 2 2006.168.07:53:39.08#ibcon#read 6, iclass 26, count 2 2006.168.07:53:39.08#ibcon#end of sib2, iclass 26, count 2 2006.168.07:53:39.08#ibcon#*after write, iclass 26, count 2 2006.168.07:53:39.08#ibcon#*before return 0, iclass 26, count 2 2006.168.07:53:39.08#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.168.07:53:39.08#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.168.07:53:39.08#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.168.07:53:39.08#ibcon#ireg 7 cls_cnt 0 2006.168.07:53:39.08#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.168.07:53:39.20#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.168.07:53:39.20#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.168.07:53:39.20#ibcon#enter wrdev, iclass 26, count 0 2006.168.07:53:39.20#ibcon#first serial, iclass 26, count 0 2006.168.07:53:39.20#ibcon#enter sib2, iclass 26, count 0 2006.168.07:53:39.20#ibcon#flushed, iclass 26, count 0 2006.168.07:53:39.20#ibcon#about to write, iclass 26, count 0 2006.168.07:53:39.20#ibcon#wrote, iclass 26, count 0 2006.168.07:53:39.20#ibcon#about to read 3, iclass 26, count 0 2006.168.07:53:39.22#ibcon#read 3, iclass 26, count 0 2006.168.07:53:39.22#ibcon#about to read 4, iclass 26, count 0 2006.168.07:53:39.22#ibcon#read 4, iclass 26, count 0 2006.168.07:53:39.22#ibcon#about to read 5, iclass 26, count 0 2006.168.07:53:39.22#ibcon#read 5, iclass 26, count 0 2006.168.07:53:39.22#ibcon#about to read 6, iclass 26, count 0 2006.168.07:53:39.22#ibcon#read 6, iclass 26, count 0 2006.168.07:53:39.22#ibcon#end of sib2, iclass 26, count 0 2006.168.07:53:39.22#ibcon#*mode == 0, iclass 26, count 0 2006.168.07:53:39.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.168.07:53:39.22#ibcon#[25=USB\r\n] 2006.168.07:53:39.22#ibcon#*before write, iclass 26, count 0 2006.168.07:53:39.22#ibcon#enter sib2, iclass 26, count 0 2006.168.07:53:39.22#ibcon#flushed, iclass 26, count 0 2006.168.07:53:39.22#ibcon#about to write, iclass 26, count 0 2006.168.07:53:39.22#ibcon#wrote, iclass 26, count 0 2006.168.07:53:39.22#ibcon#about to read 3, iclass 26, count 0 2006.168.07:53:39.25#ibcon#read 3, iclass 26, count 0 2006.168.07:53:39.25#ibcon#about to read 4, iclass 26, count 0 2006.168.07:53:39.25#ibcon#read 4, iclass 26, count 0 2006.168.07:53:39.25#ibcon#about to read 5, iclass 26, count 0 2006.168.07:53:39.25#ibcon#read 5, iclass 26, count 0 2006.168.07:53:39.25#ibcon#about to read 6, iclass 26, count 0 2006.168.07:53:39.25#ibcon#read 6, iclass 26, count 0 2006.168.07:53:39.25#ibcon#end of sib2, iclass 26, count 0 2006.168.07:53:39.25#ibcon#*after write, iclass 26, count 0 2006.168.07:53:39.25#ibcon#*before return 0, iclass 26, count 0 2006.168.07:53:39.25#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.168.07:53:39.25#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.168.07:53:39.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.168.07:53:39.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.168.07:53:39.25$vc4f8/valo=5,652.99 2006.168.07:53:39.25#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.168.07:53:39.25#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.168.07:53:39.25#ibcon#ireg 17 cls_cnt 0 2006.168.07:53:39.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:53:39.25#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:53:39.25#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:53:39.25#ibcon#enter wrdev, iclass 28, count 0 2006.168.07:53:39.25#ibcon#first serial, iclass 28, count 0 2006.168.07:53:39.25#ibcon#enter sib2, iclass 28, count 0 2006.168.07:53:39.25#ibcon#flushed, iclass 28, count 0 2006.168.07:53:39.25#ibcon#about to write, iclass 28, count 0 2006.168.07:53:39.25#ibcon#wrote, iclass 28, count 0 2006.168.07:53:39.25#ibcon#about to read 3, iclass 28, count 0 2006.168.07:53:39.27#ibcon#read 3, iclass 28, count 0 2006.168.07:53:39.27#ibcon#about to read 4, iclass 28, count 0 2006.168.07:53:39.27#ibcon#read 4, iclass 28, count 0 2006.168.07:53:39.27#ibcon#about to read 5, iclass 28, count 0 2006.168.07:53:39.27#ibcon#read 5, iclass 28, count 0 2006.168.07:53:39.27#ibcon#about to read 6, iclass 28, count 0 2006.168.07:53:39.27#ibcon#read 6, iclass 28, count 0 2006.168.07:53:39.27#ibcon#end of sib2, iclass 28, count 0 2006.168.07:53:39.27#ibcon#*mode == 0, iclass 28, count 0 2006.168.07:53:39.27#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.168.07:53:39.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.07:53:39.27#ibcon#*before write, iclass 28, count 0 2006.168.07:53:39.27#ibcon#enter sib2, iclass 28, count 0 2006.168.07:53:39.27#ibcon#flushed, iclass 28, count 0 2006.168.07:53:39.27#ibcon#about to write, iclass 28, count 0 2006.168.07:53:39.27#ibcon#wrote, iclass 28, count 0 2006.168.07:53:39.27#ibcon#about to read 3, iclass 28, count 0 2006.168.07:53:39.31#ibcon#read 3, iclass 28, count 0 2006.168.07:53:39.31#ibcon#about to read 4, iclass 28, count 0 2006.168.07:53:39.31#ibcon#read 4, iclass 28, count 0 2006.168.07:53:39.31#ibcon#about to read 5, iclass 28, count 0 2006.168.07:53:39.31#ibcon#read 5, iclass 28, count 0 2006.168.07:53:39.31#ibcon#about to read 6, iclass 28, count 0 2006.168.07:53:39.31#ibcon#read 6, iclass 28, count 0 2006.168.07:53:39.31#ibcon#end of sib2, iclass 28, count 0 2006.168.07:53:39.31#ibcon#*after write, iclass 28, count 0 2006.168.07:53:39.31#ibcon#*before return 0, iclass 28, count 0 2006.168.07:53:39.31#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:53:39.31#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:53:39.31#ibcon#about to clear, iclass 28 cls_cnt 0 2006.168.07:53:39.31#ibcon#cleared, iclass 28 cls_cnt 0 2006.168.07:53:39.31$vc4f8/va=5,7 2006.168.07:53:39.31#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.168.07:53:39.31#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.168.07:53:39.31#ibcon#ireg 11 cls_cnt 2 2006.168.07:53:39.31#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:53:39.37#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:53:39.37#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:53:39.37#ibcon#enter wrdev, iclass 30, count 2 2006.168.07:53:39.37#ibcon#first serial, iclass 30, count 2 2006.168.07:53:39.37#ibcon#enter sib2, iclass 30, count 2 2006.168.07:53:39.37#ibcon#flushed, iclass 30, count 2 2006.168.07:53:39.37#ibcon#about to write, iclass 30, count 2 2006.168.07:53:39.37#ibcon#wrote, iclass 30, count 2 2006.168.07:53:39.37#ibcon#about to read 3, iclass 30, count 2 2006.168.07:53:39.39#ibcon#read 3, iclass 30, count 2 2006.168.07:53:39.39#ibcon#about to read 4, iclass 30, count 2 2006.168.07:53:39.39#ibcon#read 4, iclass 30, count 2 2006.168.07:53:39.39#ibcon#about to read 5, iclass 30, count 2 2006.168.07:53:39.39#ibcon#read 5, iclass 30, count 2 2006.168.07:53:39.39#ibcon#about to read 6, iclass 30, count 2 2006.168.07:53:39.39#ibcon#read 6, iclass 30, count 2 2006.168.07:53:39.39#ibcon#end of sib2, iclass 30, count 2 2006.168.07:53:39.39#ibcon#*mode == 0, iclass 30, count 2 2006.168.07:53:39.39#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.168.07:53:39.39#ibcon#[25=AT05-07\r\n] 2006.168.07:53:39.39#ibcon#*before write, iclass 30, count 2 2006.168.07:53:39.39#ibcon#enter sib2, iclass 30, count 2 2006.168.07:53:39.39#ibcon#flushed, iclass 30, count 2 2006.168.07:53:39.39#ibcon#about to write, iclass 30, count 2 2006.168.07:53:39.39#ibcon#wrote, iclass 30, count 2 2006.168.07:53:39.39#ibcon#about to read 3, iclass 30, count 2 2006.168.07:53:39.42#ibcon#read 3, iclass 30, count 2 2006.168.07:53:39.42#ibcon#about to read 4, iclass 30, count 2 2006.168.07:53:39.42#ibcon#read 4, iclass 30, count 2 2006.168.07:53:39.42#ibcon#about to read 5, iclass 30, count 2 2006.168.07:53:39.42#ibcon#read 5, iclass 30, count 2 2006.168.07:53:39.42#ibcon#about to read 6, iclass 30, count 2 2006.168.07:53:39.42#ibcon#read 6, iclass 30, count 2 2006.168.07:53:39.42#ibcon#end of sib2, iclass 30, count 2 2006.168.07:53:39.42#ibcon#*after write, iclass 30, count 2 2006.168.07:53:39.42#ibcon#*before return 0, iclass 30, count 2 2006.168.07:53:39.42#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:53:39.42#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:53:39.42#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.168.07:53:39.42#ibcon#ireg 7 cls_cnt 0 2006.168.07:53:39.42#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:53:39.54#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:53:39.54#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:53:39.54#ibcon#enter wrdev, iclass 30, count 0 2006.168.07:53:39.54#ibcon#first serial, iclass 30, count 0 2006.168.07:53:39.54#ibcon#enter sib2, iclass 30, count 0 2006.168.07:53:39.54#ibcon#flushed, iclass 30, count 0 2006.168.07:53:39.54#ibcon#about to write, iclass 30, count 0 2006.168.07:53:39.54#ibcon#wrote, iclass 30, count 0 2006.168.07:53:39.54#ibcon#about to read 3, iclass 30, count 0 2006.168.07:53:39.56#ibcon#read 3, iclass 30, count 0 2006.168.07:53:39.56#ibcon#about to read 4, iclass 30, count 0 2006.168.07:53:39.56#ibcon#read 4, iclass 30, count 0 2006.168.07:53:39.56#ibcon#about to read 5, iclass 30, count 0 2006.168.07:53:39.56#ibcon#read 5, iclass 30, count 0 2006.168.07:53:39.56#ibcon#about to read 6, iclass 30, count 0 2006.168.07:53:39.56#ibcon#read 6, iclass 30, count 0 2006.168.07:53:39.56#ibcon#end of sib2, iclass 30, count 0 2006.168.07:53:39.56#ibcon#*mode == 0, iclass 30, count 0 2006.168.07:53:39.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.168.07:53:39.56#ibcon#[25=USB\r\n] 2006.168.07:53:39.56#ibcon#*before write, iclass 30, count 0 2006.168.07:53:39.56#ibcon#enter sib2, iclass 30, count 0 2006.168.07:53:39.56#ibcon#flushed, iclass 30, count 0 2006.168.07:53:39.56#ibcon#about to write, iclass 30, count 0 2006.168.07:53:39.56#ibcon#wrote, iclass 30, count 0 2006.168.07:53:39.56#ibcon#about to read 3, iclass 30, count 0 2006.168.07:53:39.59#ibcon#read 3, iclass 30, count 0 2006.168.07:53:39.59#ibcon#about to read 4, iclass 30, count 0 2006.168.07:53:39.59#ibcon#read 4, iclass 30, count 0 2006.168.07:53:39.59#ibcon#about to read 5, iclass 30, count 0 2006.168.07:53:39.59#ibcon#read 5, iclass 30, count 0 2006.168.07:53:39.59#ibcon#about to read 6, iclass 30, count 0 2006.168.07:53:39.59#ibcon#read 6, iclass 30, count 0 2006.168.07:53:39.59#ibcon#end of sib2, iclass 30, count 0 2006.168.07:53:39.59#ibcon#*after write, iclass 30, count 0 2006.168.07:53:39.59#ibcon#*before return 0, iclass 30, count 0 2006.168.07:53:39.59#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:53:39.59#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:53:39.59#ibcon#about to clear, iclass 30 cls_cnt 0 2006.168.07:53:39.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.168.07:53:39.59$vc4f8/valo=6,772.99 2006.168.07:53:39.59#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.168.07:53:39.59#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.168.07:53:39.59#ibcon#ireg 17 cls_cnt 0 2006.168.07:53:39.59#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:53:39.59#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:53:39.59#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:53:39.59#ibcon#enter wrdev, iclass 32, count 0 2006.168.07:53:39.59#ibcon#first serial, iclass 32, count 0 2006.168.07:53:39.59#ibcon#enter sib2, iclass 32, count 0 2006.168.07:53:39.59#ibcon#flushed, iclass 32, count 0 2006.168.07:53:39.59#ibcon#about to write, iclass 32, count 0 2006.168.07:53:39.59#ibcon#wrote, iclass 32, count 0 2006.168.07:53:39.59#ibcon#about to read 3, iclass 32, count 0 2006.168.07:53:39.61#ibcon#read 3, iclass 32, count 0 2006.168.07:53:39.61#ibcon#about to read 4, iclass 32, count 0 2006.168.07:53:39.61#ibcon#read 4, iclass 32, count 0 2006.168.07:53:39.61#ibcon#about to read 5, iclass 32, count 0 2006.168.07:53:39.61#ibcon#read 5, iclass 32, count 0 2006.168.07:53:39.61#ibcon#about to read 6, iclass 32, count 0 2006.168.07:53:39.61#ibcon#read 6, iclass 32, count 0 2006.168.07:53:39.61#ibcon#end of sib2, iclass 32, count 0 2006.168.07:53:39.61#ibcon#*mode == 0, iclass 32, count 0 2006.168.07:53:39.61#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.168.07:53:39.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.07:53:39.61#ibcon#*before write, iclass 32, count 0 2006.168.07:53:39.61#ibcon#enter sib2, iclass 32, count 0 2006.168.07:53:39.61#ibcon#flushed, iclass 32, count 0 2006.168.07:53:39.61#ibcon#about to write, iclass 32, count 0 2006.168.07:53:39.61#ibcon#wrote, iclass 32, count 0 2006.168.07:53:39.61#ibcon#about to read 3, iclass 32, count 0 2006.168.07:53:39.65#ibcon#read 3, iclass 32, count 0 2006.168.07:53:39.65#ibcon#about to read 4, iclass 32, count 0 2006.168.07:53:39.65#ibcon#read 4, iclass 32, count 0 2006.168.07:53:39.65#ibcon#about to read 5, iclass 32, count 0 2006.168.07:53:39.65#ibcon#read 5, iclass 32, count 0 2006.168.07:53:39.65#ibcon#about to read 6, iclass 32, count 0 2006.168.07:53:39.65#ibcon#read 6, iclass 32, count 0 2006.168.07:53:39.65#ibcon#end of sib2, iclass 32, count 0 2006.168.07:53:39.65#ibcon#*after write, iclass 32, count 0 2006.168.07:53:39.65#ibcon#*before return 0, iclass 32, count 0 2006.168.07:53:39.65#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:53:39.65#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:53:39.65#ibcon#about to clear, iclass 32 cls_cnt 0 2006.168.07:53:39.65#ibcon#cleared, iclass 32 cls_cnt 0 2006.168.07:53:39.65$vc4f8/va=6,6 2006.168.07:53:39.65#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.168.07:53:39.65#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.168.07:53:39.65#ibcon#ireg 11 cls_cnt 2 2006.168.07:53:39.65#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:53:39.71#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:53:39.71#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:53:39.71#ibcon#enter wrdev, iclass 34, count 2 2006.168.07:53:39.71#ibcon#first serial, iclass 34, count 2 2006.168.07:53:39.71#ibcon#enter sib2, iclass 34, count 2 2006.168.07:53:39.71#ibcon#flushed, iclass 34, count 2 2006.168.07:53:39.71#ibcon#about to write, iclass 34, count 2 2006.168.07:53:39.71#ibcon#wrote, iclass 34, count 2 2006.168.07:53:39.71#ibcon#about to read 3, iclass 34, count 2 2006.168.07:53:39.73#ibcon#read 3, iclass 34, count 2 2006.168.07:53:39.73#ibcon#about to read 4, iclass 34, count 2 2006.168.07:53:39.73#ibcon#read 4, iclass 34, count 2 2006.168.07:53:39.73#ibcon#about to read 5, iclass 34, count 2 2006.168.07:53:39.73#ibcon#read 5, iclass 34, count 2 2006.168.07:53:39.73#ibcon#about to read 6, iclass 34, count 2 2006.168.07:53:39.73#ibcon#read 6, iclass 34, count 2 2006.168.07:53:39.73#ibcon#end of sib2, iclass 34, count 2 2006.168.07:53:39.73#ibcon#*mode == 0, iclass 34, count 2 2006.168.07:53:39.73#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.168.07:53:39.73#ibcon#[25=AT06-06\r\n] 2006.168.07:53:39.73#ibcon#*before write, iclass 34, count 2 2006.168.07:53:39.73#ibcon#enter sib2, iclass 34, count 2 2006.168.07:53:39.73#ibcon#flushed, iclass 34, count 2 2006.168.07:53:39.73#ibcon#about to write, iclass 34, count 2 2006.168.07:53:39.73#ibcon#wrote, iclass 34, count 2 2006.168.07:53:39.73#ibcon#about to read 3, iclass 34, count 2 2006.168.07:53:39.76#ibcon#read 3, iclass 34, count 2 2006.168.07:53:39.76#ibcon#about to read 4, iclass 34, count 2 2006.168.07:53:39.76#ibcon#read 4, iclass 34, count 2 2006.168.07:53:39.76#ibcon#about to read 5, iclass 34, count 2 2006.168.07:53:39.76#ibcon#read 5, iclass 34, count 2 2006.168.07:53:39.76#ibcon#about to read 6, iclass 34, count 2 2006.168.07:53:39.76#ibcon#read 6, iclass 34, count 2 2006.168.07:53:39.76#ibcon#end of sib2, iclass 34, count 2 2006.168.07:53:39.76#ibcon#*after write, iclass 34, count 2 2006.168.07:53:39.76#ibcon#*before return 0, iclass 34, count 2 2006.168.07:53:39.76#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:53:39.76#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:53:39.76#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.168.07:53:39.76#ibcon#ireg 7 cls_cnt 0 2006.168.07:53:39.76#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:53:39.88#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:53:39.88#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:53:39.88#ibcon#enter wrdev, iclass 34, count 0 2006.168.07:53:39.88#ibcon#first serial, iclass 34, count 0 2006.168.07:53:39.88#ibcon#enter sib2, iclass 34, count 0 2006.168.07:53:39.88#ibcon#flushed, iclass 34, count 0 2006.168.07:53:39.88#ibcon#about to write, iclass 34, count 0 2006.168.07:53:39.88#ibcon#wrote, iclass 34, count 0 2006.168.07:53:39.88#ibcon#about to read 3, iclass 34, count 0 2006.168.07:53:39.90#ibcon#read 3, iclass 34, count 0 2006.168.07:53:39.90#ibcon#about to read 4, iclass 34, count 0 2006.168.07:53:39.90#ibcon#read 4, iclass 34, count 0 2006.168.07:53:39.90#ibcon#about to read 5, iclass 34, count 0 2006.168.07:53:39.90#ibcon#read 5, iclass 34, count 0 2006.168.07:53:39.90#ibcon#about to read 6, iclass 34, count 0 2006.168.07:53:39.90#ibcon#read 6, iclass 34, count 0 2006.168.07:53:39.90#ibcon#end of sib2, iclass 34, count 0 2006.168.07:53:39.90#ibcon#*mode == 0, iclass 34, count 0 2006.168.07:53:39.90#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.168.07:53:39.90#ibcon#[25=USB\r\n] 2006.168.07:53:39.90#ibcon#*before write, iclass 34, count 0 2006.168.07:53:39.90#ibcon#enter sib2, iclass 34, count 0 2006.168.07:53:39.90#ibcon#flushed, iclass 34, count 0 2006.168.07:53:39.90#ibcon#about to write, iclass 34, count 0 2006.168.07:53:39.90#ibcon#wrote, iclass 34, count 0 2006.168.07:53:39.90#ibcon#about to read 3, iclass 34, count 0 2006.168.07:53:39.93#ibcon#read 3, iclass 34, count 0 2006.168.07:53:39.93#ibcon#about to read 4, iclass 34, count 0 2006.168.07:53:39.93#ibcon#read 4, iclass 34, count 0 2006.168.07:53:39.93#ibcon#about to read 5, iclass 34, count 0 2006.168.07:53:39.93#ibcon#read 5, iclass 34, count 0 2006.168.07:53:39.93#ibcon#about to read 6, iclass 34, count 0 2006.168.07:53:39.93#ibcon#read 6, iclass 34, count 0 2006.168.07:53:39.93#ibcon#end of sib2, iclass 34, count 0 2006.168.07:53:39.93#ibcon#*after write, iclass 34, count 0 2006.168.07:53:39.93#ibcon#*before return 0, iclass 34, count 0 2006.168.07:53:39.93#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:53:39.93#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:53:39.93#ibcon#about to clear, iclass 34 cls_cnt 0 2006.168.07:53:39.93#ibcon#cleared, iclass 34 cls_cnt 0 2006.168.07:53:39.93$vc4f8/valo=7,832.99 2006.168.07:53:39.93#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.168.07:53:39.93#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.168.07:53:39.93#ibcon#ireg 17 cls_cnt 0 2006.168.07:53:39.93#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:53:39.93#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:53:39.93#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:53:39.93#ibcon#enter wrdev, iclass 36, count 0 2006.168.07:53:39.93#ibcon#first serial, iclass 36, count 0 2006.168.07:53:39.93#ibcon#enter sib2, iclass 36, count 0 2006.168.07:53:39.93#ibcon#flushed, iclass 36, count 0 2006.168.07:53:39.93#ibcon#about to write, iclass 36, count 0 2006.168.07:53:39.93#ibcon#wrote, iclass 36, count 0 2006.168.07:53:39.93#ibcon#about to read 3, iclass 36, count 0 2006.168.07:53:39.95#ibcon#read 3, iclass 36, count 0 2006.168.07:53:39.95#ibcon#about to read 4, iclass 36, count 0 2006.168.07:53:39.95#ibcon#read 4, iclass 36, count 0 2006.168.07:53:39.95#ibcon#about to read 5, iclass 36, count 0 2006.168.07:53:39.95#ibcon#read 5, iclass 36, count 0 2006.168.07:53:39.95#ibcon#about to read 6, iclass 36, count 0 2006.168.07:53:39.95#ibcon#read 6, iclass 36, count 0 2006.168.07:53:39.95#ibcon#end of sib2, iclass 36, count 0 2006.168.07:53:39.95#ibcon#*mode == 0, iclass 36, count 0 2006.168.07:53:39.95#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.168.07:53:39.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.07:53:39.95#ibcon#*before write, iclass 36, count 0 2006.168.07:53:39.95#ibcon#enter sib2, iclass 36, count 0 2006.168.07:53:39.95#ibcon#flushed, iclass 36, count 0 2006.168.07:53:39.95#ibcon#about to write, iclass 36, count 0 2006.168.07:53:39.95#ibcon#wrote, iclass 36, count 0 2006.168.07:53:39.95#ibcon#about to read 3, iclass 36, count 0 2006.168.07:53:39.99#ibcon#read 3, iclass 36, count 0 2006.168.07:53:39.99#ibcon#about to read 4, iclass 36, count 0 2006.168.07:53:39.99#ibcon#read 4, iclass 36, count 0 2006.168.07:53:39.99#ibcon#about to read 5, iclass 36, count 0 2006.168.07:53:39.99#ibcon#read 5, iclass 36, count 0 2006.168.07:53:39.99#ibcon#about to read 6, iclass 36, count 0 2006.168.07:53:39.99#ibcon#read 6, iclass 36, count 0 2006.168.07:53:39.99#ibcon#end of sib2, iclass 36, count 0 2006.168.07:53:39.99#ibcon#*after write, iclass 36, count 0 2006.168.07:53:39.99#ibcon#*before return 0, iclass 36, count 0 2006.168.07:53:39.99#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:53:39.99#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:53:39.99#ibcon#about to clear, iclass 36 cls_cnt 0 2006.168.07:53:39.99#ibcon#cleared, iclass 36 cls_cnt 0 2006.168.07:53:39.99$vc4f8/va=7,6 2006.168.07:53:39.99#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.168.07:53:39.99#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.168.07:53:39.99#ibcon#ireg 11 cls_cnt 2 2006.168.07:53:39.99#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.168.07:53:40.05#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.168.07:53:40.05#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.168.07:53:40.05#ibcon#enter wrdev, iclass 38, count 2 2006.168.07:53:40.05#ibcon#first serial, iclass 38, count 2 2006.168.07:53:40.05#ibcon#enter sib2, iclass 38, count 2 2006.168.07:53:40.05#ibcon#flushed, iclass 38, count 2 2006.168.07:53:40.05#ibcon#about to write, iclass 38, count 2 2006.168.07:53:40.05#ibcon#wrote, iclass 38, count 2 2006.168.07:53:40.05#ibcon#about to read 3, iclass 38, count 2 2006.168.07:53:40.07#ibcon#read 3, iclass 38, count 2 2006.168.07:53:40.07#ibcon#about to read 4, iclass 38, count 2 2006.168.07:53:40.07#ibcon#read 4, iclass 38, count 2 2006.168.07:53:40.07#ibcon#about to read 5, iclass 38, count 2 2006.168.07:53:40.07#ibcon#read 5, iclass 38, count 2 2006.168.07:53:40.07#ibcon#about to read 6, iclass 38, count 2 2006.168.07:53:40.07#ibcon#read 6, iclass 38, count 2 2006.168.07:53:40.07#ibcon#end of sib2, iclass 38, count 2 2006.168.07:53:40.07#ibcon#*mode == 0, iclass 38, count 2 2006.168.07:53:40.07#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.168.07:53:40.07#ibcon#[25=AT07-06\r\n] 2006.168.07:53:40.07#ibcon#*before write, iclass 38, count 2 2006.168.07:53:40.07#ibcon#enter sib2, iclass 38, count 2 2006.168.07:53:40.07#ibcon#flushed, iclass 38, count 2 2006.168.07:53:40.07#ibcon#about to write, iclass 38, count 2 2006.168.07:53:40.07#ibcon#wrote, iclass 38, count 2 2006.168.07:53:40.07#ibcon#about to read 3, iclass 38, count 2 2006.168.07:53:40.10#ibcon#read 3, iclass 38, count 2 2006.168.07:53:40.10#ibcon#about to read 4, iclass 38, count 2 2006.168.07:53:40.10#ibcon#read 4, iclass 38, count 2 2006.168.07:53:40.10#ibcon#about to read 5, iclass 38, count 2 2006.168.07:53:40.10#ibcon#read 5, iclass 38, count 2 2006.168.07:53:40.10#ibcon#about to read 6, iclass 38, count 2 2006.168.07:53:40.10#ibcon#read 6, iclass 38, count 2 2006.168.07:53:40.10#ibcon#end of sib2, iclass 38, count 2 2006.168.07:53:40.10#ibcon#*after write, iclass 38, count 2 2006.168.07:53:40.10#ibcon#*before return 0, iclass 38, count 2 2006.168.07:53:40.10#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.168.07:53:40.10#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.168.07:53:40.10#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.168.07:53:40.10#ibcon#ireg 7 cls_cnt 0 2006.168.07:53:40.10#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.168.07:53:40.22#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.168.07:53:40.22#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.168.07:53:40.22#ibcon#enter wrdev, iclass 38, count 0 2006.168.07:53:40.22#ibcon#first serial, iclass 38, count 0 2006.168.07:53:40.22#ibcon#enter sib2, iclass 38, count 0 2006.168.07:53:40.22#ibcon#flushed, iclass 38, count 0 2006.168.07:53:40.22#ibcon#about to write, iclass 38, count 0 2006.168.07:53:40.22#ibcon#wrote, iclass 38, count 0 2006.168.07:53:40.22#ibcon#about to read 3, iclass 38, count 0 2006.168.07:53:40.24#ibcon#read 3, iclass 38, count 0 2006.168.07:53:40.24#ibcon#about to read 4, iclass 38, count 0 2006.168.07:53:40.24#ibcon#read 4, iclass 38, count 0 2006.168.07:53:40.24#ibcon#about to read 5, iclass 38, count 0 2006.168.07:53:40.24#ibcon#read 5, iclass 38, count 0 2006.168.07:53:40.24#ibcon#about to read 6, iclass 38, count 0 2006.168.07:53:40.24#ibcon#read 6, iclass 38, count 0 2006.168.07:53:40.24#ibcon#end of sib2, iclass 38, count 0 2006.168.07:53:40.24#ibcon#*mode == 0, iclass 38, count 0 2006.168.07:53:40.24#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.168.07:53:40.24#ibcon#[25=USB\r\n] 2006.168.07:53:40.24#ibcon#*before write, iclass 38, count 0 2006.168.07:53:40.24#ibcon#enter sib2, iclass 38, count 0 2006.168.07:53:40.24#ibcon#flushed, iclass 38, count 0 2006.168.07:53:40.24#ibcon#about to write, iclass 38, count 0 2006.168.07:53:40.24#ibcon#wrote, iclass 38, count 0 2006.168.07:53:40.24#ibcon#about to read 3, iclass 38, count 0 2006.168.07:53:40.27#ibcon#read 3, iclass 38, count 0 2006.168.07:53:40.27#ibcon#about to read 4, iclass 38, count 0 2006.168.07:53:40.27#ibcon#read 4, iclass 38, count 0 2006.168.07:53:40.27#ibcon#about to read 5, iclass 38, count 0 2006.168.07:53:40.27#ibcon#read 5, iclass 38, count 0 2006.168.07:53:40.27#ibcon#about to read 6, iclass 38, count 0 2006.168.07:53:40.27#ibcon#read 6, iclass 38, count 0 2006.168.07:53:40.27#ibcon#end of sib2, iclass 38, count 0 2006.168.07:53:40.27#ibcon#*after write, iclass 38, count 0 2006.168.07:53:40.27#ibcon#*before return 0, iclass 38, count 0 2006.168.07:53:40.27#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.168.07:53:40.27#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.168.07:53:40.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.168.07:53:40.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.168.07:53:40.27$vc4f8/valo=8,852.99 2006.168.07:53:40.27#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.168.07:53:40.27#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.168.07:53:40.27#ibcon#ireg 17 cls_cnt 0 2006.168.07:53:40.27#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.168.07:53:40.27#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.168.07:53:40.27#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.168.07:53:40.27#ibcon#enter wrdev, iclass 40, count 0 2006.168.07:53:40.27#ibcon#first serial, iclass 40, count 0 2006.168.07:53:40.27#ibcon#enter sib2, iclass 40, count 0 2006.168.07:53:40.27#ibcon#flushed, iclass 40, count 0 2006.168.07:53:40.27#ibcon#about to write, iclass 40, count 0 2006.168.07:53:40.27#ibcon#wrote, iclass 40, count 0 2006.168.07:53:40.27#ibcon#about to read 3, iclass 40, count 0 2006.168.07:53:40.29#ibcon#read 3, iclass 40, count 0 2006.168.07:53:40.29#ibcon#about to read 4, iclass 40, count 0 2006.168.07:53:40.29#ibcon#read 4, iclass 40, count 0 2006.168.07:53:40.29#ibcon#about to read 5, iclass 40, count 0 2006.168.07:53:40.29#ibcon#read 5, iclass 40, count 0 2006.168.07:53:40.29#ibcon#about to read 6, iclass 40, count 0 2006.168.07:53:40.29#ibcon#read 6, iclass 40, count 0 2006.168.07:53:40.29#ibcon#end of sib2, iclass 40, count 0 2006.168.07:53:40.29#ibcon#*mode == 0, iclass 40, count 0 2006.168.07:53:40.29#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.168.07:53:40.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.07:53:40.29#ibcon#*before write, iclass 40, count 0 2006.168.07:53:40.29#ibcon#enter sib2, iclass 40, count 0 2006.168.07:53:40.29#ibcon#flushed, iclass 40, count 0 2006.168.07:53:40.29#ibcon#about to write, iclass 40, count 0 2006.168.07:53:40.29#ibcon#wrote, iclass 40, count 0 2006.168.07:53:40.29#ibcon#about to read 3, iclass 40, count 0 2006.168.07:53:40.33#ibcon#read 3, iclass 40, count 0 2006.168.07:53:40.33#ibcon#about to read 4, iclass 40, count 0 2006.168.07:53:40.33#ibcon#read 4, iclass 40, count 0 2006.168.07:53:40.33#ibcon#about to read 5, iclass 40, count 0 2006.168.07:53:40.33#ibcon#read 5, iclass 40, count 0 2006.168.07:53:40.33#ibcon#about to read 6, iclass 40, count 0 2006.168.07:53:40.33#ibcon#read 6, iclass 40, count 0 2006.168.07:53:40.33#ibcon#end of sib2, iclass 40, count 0 2006.168.07:53:40.33#ibcon#*after write, iclass 40, count 0 2006.168.07:53:40.33#ibcon#*before return 0, iclass 40, count 0 2006.168.07:53:40.33#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.168.07:53:40.33#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.168.07:53:40.33#ibcon#about to clear, iclass 40 cls_cnt 0 2006.168.07:53:40.33#ibcon#cleared, iclass 40 cls_cnt 0 2006.168.07:53:40.33$vc4f8/va=8,7 2006.168.07:53:40.33#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.168.07:53:40.33#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.168.07:53:40.33#ibcon#ireg 11 cls_cnt 2 2006.168.07:53:40.33#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.168.07:53:40.39#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.168.07:53:40.39#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.168.07:53:40.39#ibcon#enter wrdev, iclass 4, count 2 2006.168.07:53:40.39#ibcon#first serial, iclass 4, count 2 2006.168.07:53:40.39#ibcon#enter sib2, iclass 4, count 2 2006.168.07:53:40.39#ibcon#flushed, iclass 4, count 2 2006.168.07:53:40.39#ibcon#about to write, iclass 4, count 2 2006.168.07:53:40.39#ibcon#wrote, iclass 4, count 2 2006.168.07:53:40.39#ibcon#about to read 3, iclass 4, count 2 2006.168.07:53:40.41#ibcon#read 3, iclass 4, count 2 2006.168.07:53:40.41#ibcon#about to read 4, iclass 4, count 2 2006.168.07:53:40.41#ibcon#read 4, iclass 4, count 2 2006.168.07:53:40.41#ibcon#about to read 5, iclass 4, count 2 2006.168.07:53:40.41#ibcon#read 5, iclass 4, count 2 2006.168.07:53:40.41#ibcon#about to read 6, iclass 4, count 2 2006.168.07:53:40.41#ibcon#read 6, iclass 4, count 2 2006.168.07:53:40.41#ibcon#end of sib2, iclass 4, count 2 2006.168.07:53:40.41#ibcon#*mode == 0, iclass 4, count 2 2006.168.07:53:40.41#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.168.07:53:40.41#ibcon#[25=AT08-07\r\n] 2006.168.07:53:40.41#ibcon#*before write, iclass 4, count 2 2006.168.07:53:40.41#ibcon#enter sib2, iclass 4, count 2 2006.168.07:53:40.41#ibcon#flushed, iclass 4, count 2 2006.168.07:53:40.41#ibcon#about to write, iclass 4, count 2 2006.168.07:53:40.41#ibcon#wrote, iclass 4, count 2 2006.168.07:53:40.41#ibcon#about to read 3, iclass 4, count 2 2006.168.07:53:40.44#ibcon#read 3, iclass 4, count 2 2006.168.07:53:40.44#ibcon#about to read 4, iclass 4, count 2 2006.168.07:53:40.44#ibcon#read 4, iclass 4, count 2 2006.168.07:53:40.44#ibcon#about to read 5, iclass 4, count 2 2006.168.07:53:40.44#ibcon#read 5, iclass 4, count 2 2006.168.07:53:40.44#ibcon#about to read 6, iclass 4, count 2 2006.168.07:53:40.44#ibcon#read 6, iclass 4, count 2 2006.168.07:53:40.44#ibcon#end of sib2, iclass 4, count 2 2006.168.07:53:40.44#ibcon#*after write, iclass 4, count 2 2006.168.07:53:40.44#ibcon#*before return 0, iclass 4, count 2 2006.168.07:53:40.44#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.168.07:53:40.44#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.168.07:53:40.44#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.168.07:53:40.44#ibcon#ireg 7 cls_cnt 0 2006.168.07:53:40.44#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.168.07:53:40.56#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.168.07:53:40.56#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.168.07:53:40.56#ibcon#enter wrdev, iclass 4, count 0 2006.168.07:53:40.56#ibcon#first serial, iclass 4, count 0 2006.168.07:53:40.56#ibcon#enter sib2, iclass 4, count 0 2006.168.07:53:40.56#ibcon#flushed, iclass 4, count 0 2006.168.07:53:40.56#ibcon#about to write, iclass 4, count 0 2006.168.07:53:40.56#ibcon#wrote, iclass 4, count 0 2006.168.07:53:40.56#ibcon#about to read 3, iclass 4, count 0 2006.168.07:53:40.58#ibcon#read 3, iclass 4, count 0 2006.168.07:53:40.58#ibcon#about to read 4, iclass 4, count 0 2006.168.07:53:40.58#ibcon#read 4, iclass 4, count 0 2006.168.07:53:40.58#ibcon#about to read 5, iclass 4, count 0 2006.168.07:53:40.58#ibcon#read 5, iclass 4, count 0 2006.168.07:53:40.58#ibcon#about to read 6, iclass 4, count 0 2006.168.07:53:40.58#ibcon#read 6, iclass 4, count 0 2006.168.07:53:40.58#ibcon#end of sib2, iclass 4, count 0 2006.168.07:53:40.58#ibcon#*mode == 0, iclass 4, count 0 2006.168.07:53:40.58#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.168.07:53:40.58#ibcon#[25=USB\r\n] 2006.168.07:53:40.58#ibcon#*before write, iclass 4, count 0 2006.168.07:53:40.58#ibcon#enter sib2, iclass 4, count 0 2006.168.07:53:40.58#ibcon#flushed, iclass 4, count 0 2006.168.07:53:40.58#ibcon#about to write, iclass 4, count 0 2006.168.07:53:40.58#ibcon#wrote, iclass 4, count 0 2006.168.07:53:40.58#ibcon#about to read 3, iclass 4, count 0 2006.168.07:53:40.61#ibcon#read 3, iclass 4, count 0 2006.168.07:53:40.61#ibcon#about to read 4, iclass 4, count 0 2006.168.07:53:40.61#ibcon#read 4, iclass 4, count 0 2006.168.07:53:40.61#ibcon#about to read 5, iclass 4, count 0 2006.168.07:53:40.61#ibcon#read 5, iclass 4, count 0 2006.168.07:53:40.61#ibcon#about to read 6, iclass 4, count 0 2006.168.07:53:40.61#ibcon#read 6, iclass 4, count 0 2006.168.07:53:40.61#ibcon#end of sib2, iclass 4, count 0 2006.168.07:53:40.61#ibcon#*after write, iclass 4, count 0 2006.168.07:53:40.61#ibcon#*before return 0, iclass 4, count 0 2006.168.07:53:40.61#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.168.07:53:40.61#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.168.07:53:40.61#ibcon#about to clear, iclass 4 cls_cnt 0 2006.168.07:53:40.61#ibcon#cleared, iclass 4 cls_cnt 0 2006.168.07:53:40.61$vc4f8/vblo=1,632.99 2006.168.07:53:40.61#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.168.07:53:40.61#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.168.07:53:40.61#ibcon#ireg 17 cls_cnt 0 2006.168.07:53:40.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.168.07:53:40.61#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.168.07:53:40.61#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.168.07:53:40.61#ibcon#enter wrdev, iclass 6, count 0 2006.168.07:53:40.61#ibcon#first serial, iclass 6, count 0 2006.168.07:53:40.61#ibcon#enter sib2, iclass 6, count 0 2006.168.07:53:40.61#ibcon#flushed, iclass 6, count 0 2006.168.07:53:40.61#ibcon#about to write, iclass 6, count 0 2006.168.07:53:40.61#ibcon#wrote, iclass 6, count 0 2006.168.07:53:40.61#ibcon#about to read 3, iclass 6, count 0 2006.168.07:53:40.63#ibcon#read 3, iclass 6, count 0 2006.168.07:53:40.63#ibcon#about to read 4, iclass 6, count 0 2006.168.07:53:40.63#ibcon#read 4, iclass 6, count 0 2006.168.07:53:40.63#ibcon#about to read 5, iclass 6, count 0 2006.168.07:53:40.63#ibcon#read 5, iclass 6, count 0 2006.168.07:53:40.63#ibcon#about to read 6, iclass 6, count 0 2006.168.07:53:40.63#ibcon#read 6, iclass 6, count 0 2006.168.07:53:40.63#ibcon#end of sib2, iclass 6, count 0 2006.168.07:53:40.63#ibcon#*mode == 0, iclass 6, count 0 2006.168.07:53:40.63#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.168.07:53:40.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.07:53:40.63#ibcon#*before write, iclass 6, count 0 2006.168.07:53:40.63#ibcon#enter sib2, iclass 6, count 0 2006.168.07:53:40.63#ibcon#flushed, iclass 6, count 0 2006.168.07:53:40.63#ibcon#about to write, iclass 6, count 0 2006.168.07:53:40.63#ibcon#wrote, iclass 6, count 0 2006.168.07:53:40.63#ibcon#about to read 3, iclass 6, count 0 2006.168.07:53:40.67#ibcon#read 3, iclass 6, count 0 2006.168.07:53:40.67#ibcon#about to read 4, iclass 6, count 0 2006.168.07:53:40.67#ibcon#read 4, iclass 6, count 0 2006.168.07:53:40.67#ibcon#about to read 5, iclass 6, count 0 2006.168.07:53:40.67#ibcon#read 5, iclass 6, count 0 2006.168.07:53:40.67#ibcon#about to read 6, iclass 6, count 0 2006.168.07:53:40.67#ibcon#read 6, iclass 6, count 0 2006.168.07:53:40.67#ibcon#end of sib2, iclass 6, count 0 2006.168.07:53:40.67#ibcon#*after write, iclass 6, count 0 2006.168.07:53:40.67#ibcon#*before return 0, iclass 6, count 0 2006.168.07:53:40.67#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.168.07:53:40.67#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.168.07:53:40.67#ibcon#about to clear, iclass 6 cls_cnt 0 2006.168.07:53:40.67#ibcon#cleared, iclass 6 cls_cnt 0 2006.168.07:53:40.67$vc4f8/vb=1,4 2006.168.07:53:40.67#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.168.07:53:40.67#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.168.07:53:40.67#ibcon#ireg 11 cls_cnt 2 2006.168.07:53:40.67#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.168.07:53:40.67#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.168.07:53:40.67#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.168.07:53:40.67#ibcon#enter wrdev, iclass 10, count 2 2006.168.07:53:40.67#ibcon#first serial, iclass 10, count 2 2006.168.07:53:40.67#ibcon#enter sib2, iclass 10, count 2 2006.168.07:53:40.67#ibcon#flushed, iclass 10, count 2 2006.168.07:53:40.67#ibcon#about to write, iclass 10, count 2 2006.168.07:53:40.67#ibcon#wrote, iclass 10, count 2 2006.168.07:53:40.67#ibcon#about to read 3, iclass 10, count 2 2006.168.07:53:40.69#ibcon#read 3, iclass 10, count 2 2006.168.07:53:40.69#ibcon#about to read 4, iclass 10, count 2 2006.168.07:53:40.69#ibcon#read 4, iclass 10, count 2 2006.168.07:53:40.69#ibcon#about to read 5, iclass 10, count 2 2006.168.07:53:40.69#ibcon#read 5, iclass 10, count 2 2006.168.07:53:40.69#ibcon#about to read 6, iclass 10, count 2 2006.168.07:53:40.69#ibcon#read 6, iclass 10, count 2 2006.168.07:53:40.69#ibcon#end of sib2, iclass 10, count 2 2006.168.07:53:40.69#ibcon#*mode == 0, iclass 10, count 2 2006.168.07:53:40.69#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.168.07:53:40.69#ibcon#[27=AT01-04\r\n] 2006.168.07:53:40.69#ibcon#*before write, iclass 10, count 2 2006.168.07:53:40.69#ibcon#enter sib2, iclass 10, count 2 2006.168.07:53:40.69#ibcon#flushed, iclass 10, count 2 2006.168.07:53:40.69#ibcon#about to write, iclass 10, count 2 2006.168.07:53:40.69#ibcon#wrote, iclass 10, count 2 2006.168.07:53:40.69#ibcon#about to read 3, iclass 10, count 2 2006.168.07:53:40.72#ibcon#read 3, iclass 10, count 2 2006.168.07:53:40.72#ibcon#about to read 4, iclass 10, count 2 2006.168.07:53:40.72#ibcon#read 4, iclass 10, count 2 2006.168.07:53:40.72#ibcon#about to read 5, iclass 10, count 2 2006.168.07:53:40.72#ibcon#read 5, iclass 10, count 2 2006.168.07:53:40.72#ibcon#about to read 6, iclass 10, count 2 2006.168.07:53:40.72#ibcon#read 6, iclass 10, count 2 2006.168.07:53:40.72#ibcon#end of sib2, iclass 10, count 2 2006.168.07:53:40.72#ibcon#*after write, iclass 10, count 2 2006.168.07:53:40.72#ibcon#*before return 0, iclass 10, count 2 2006.168.07:53:40.72#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.168.07:53:40.72#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.168.07:53:40.72#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.168.07:53:40.72#ibcon#ireg 7 cls_cnt 0 2006.168.07:53:40.72#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.168.07:53:40.84#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.168.07:53:40.84#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.168.07:53:40.84#ibcon#enter wrdev, iclass 10, count 0 2006.168.07:53:40.84#ibcon#first serial, iclass 10, count 0 2006.168.07:53:40.84#ibcon#enter sib2, iclass 10, count 0 2006.168.07:53:40.84#ibcon#flushed, iclass 10, count 0 2006.168.07:53:40.84#ibcon#about to write, iclass 10, count 0 2006.168.07:53:40.84#ibcon#wrote, iclass 10, count 0 2006.168.07:53:40.84#ibcon#about to read 3, iclass 10, count 0 2006.168.07:53:40.86#ibcon#read 3, iclass 10, count 0 2006.168.07:53:40.86#ibcon#about to read 4, iclass 10, count 0 2006.168.07:53:40.86#ibcon#read 4, iclass 10, count 0 2006.168.07:53:40.86#ibcon#about to read 5, iclass 10, count 0 2006.168.07:53:40.86#ibcon#read 5, iclass 10, count 0 2006.168.07:53:40.86#ibcon#about to read 6, iclass 10, count 0 2006.168.07:53:40.86#ibcon#read 6, iclass 10, count 0 2006.168.07:53:40.86#ibcon#end of sib2, iclass 10, count 0 2006.168.07:53:40.86#ibcon#*mode == 0, iclass 10, count 0 2006.168.07:53:40.86#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.168.07:53:40.86#ibcon#[27=USB\r\n] 2006.168.07:53:40.86#ibcon#*before write, iclass 10, count 0 2006.168.07:53:40.86#ibcon#enter sib2, iclass 10, count 0 2006.168.07:53:40.86#ibcon#flushed, iclass 10, count 0 2006.168.07:53:40.86#ibcon#about to write, iclass 10, count 0 2006.168.07:53:40.86#ibcon#wrote, iclass 10, count 0 2006.168.07:53:40.86#ibcon#about to read 3, iclass 10, count 0 2006.168.07:53:40.89#ibcon#read 3, iclass 10, count 0 2006.168.07:53:40.89#ibcon#about to read 4, iclass 10, count 0 2006.168.07:53:40.89#ibcon#read 4, iclass 10, count 0 2006.168.07:53:40.89#ibcon#about to read 5, iclass 10, count 0 2006.168.07:53:40.89#ibcon#read 5, iclass 10, count 0 2006.168.07:53:40.89#ibcon#about to read 6, iclass 10, count 0 2006.168.07:53:40.89#ibcon#read 6, iclass 10, count 0 2006.168.07:53:40.89#ibcon#end of sib2, iclass 10, count 0 2006.168.07:53:40.89#ibcon#*after write, iclass 10, count 0 2006.168.07:53:40.89#ibcon#*before return 0, iclass 10, count 0 2006.168.07:53:40.89#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.168.07:53:40.89#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.168.07:53:40.89#ibcon#about to clear, iclass 10 cls_cnt 0 2006.168.07:53:40.89#ibcon#cleared, iclass 10 cls_cnt 0 2006.168.07:53:40.89$vc4f8/vblo=2,640.99 2006.168.07:53:40.89#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.168.07:53:40.89#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.168.07:53:40.89#ibcon#ireg 17 cls_cnt 0 2006.168.07:53:40.89#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.168.07:53:40.89#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.168.07:53:40.89#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.168.07:53:40.89#ibcon#enter wrdev, iclass 12, count 0 2006.168.07:53:40.89#ibcon#first serial, iclass 12, count 0 2006.168.07:53:40.89#ibcon#enter sib2, iclass 12, count 0 2006.168.07:53:40.89#ibcon#flushed, iclass 12, count 0 2006.168.07:53:40.89#ibcon#about to write, iclass 12, count 0 2006.168.07:53:40.89#ibcon#wrote, iclass 12, count 0 2006.168.07:53:40.89#ibcon#about to read 3, iclass 12, count 0 2006.168.07:53:40.91#ibcon#read 3, iclass 12, count 0 2006.168.07:53:40.91#ibcon#about to read 4, iclass 12, count 0 2006.168.07:53:40.91#ibcon#read 4, iclass 12, count 0 2006.168.07:53:40.91#ibcon#about to read 5, iclass 12, count 0 2006.168.07:53:40.91#ibcon#read 5, iclass 12, count 0 2006.168.07:53:40.91#ibcon#about to read 6, iclass 12, count 0 2006.168.07:53:40.91#ibcon#read 6, iclass 12, count 0 2006.168.07:53:40.91#ibcon#end of sib2, iclass 12, count 0 2006.168.07:53:40.91#ibcon#*mode == 0, iclass 12, count 0 2006.168.07:53:40.91#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.168.07:53:40.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.07:53:40.91#ibcon#*before write, iclass 12, count 0 2006.168.07:53:40.91#ibcon#enter sib2, iclass 12, count 0 2006.168.07:53:40.91#ibcon#flushed, iclass 12, count 0 2006.168.07:53:40.91#ibcon#about to write, iclass 12, count 0 2006.168.07:53:40.91#ibcon#wrote, iclass 12, count 0 2006.168.07:53:40.91#ibcon#about to read 3, iclass 12, count 0 2006.168.07:53:40.95#ibcon#read 3, iclass 12, count 0 2006.168.07:53:40.95#ibcon#about to read 4, iclass 12, count 0 2006.168.07:53:40.95#ibcon#read 4, iclass 12, count 0 2006.168.07:53:40.95#ibcon#about to read 5, iclass 12, count 0 2006.168.07:53:40.95#ibcon#read 5, iclass 12, count 0 2006.168.07:53:40.95#ibcon#about to read 6, iclass 12, count 0 2006.168.07:53:40.95#ibcon#read 6, iclass 12, count 0 2006.168.07:53:40.95#ibcon#end of sib2, iclass 12, count 0 2006.168.07:53:40.95#ibcon#*after write, iclass 12, count 0 2006.168.07:53:40.95#ibcon#*before return 0, iclass 12, count 0 2006.168.07:53:40.95#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.168.07:53:40.95#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.168.07:53:40.95#ibcon#about to clear, iclass 12 cls_cnt 0 2006.168.07:53:40.95#ibcon#cleared, iclass 12 cls_cnt 0 2006.168.07:53:40.95$vc4f8/vb=2,4 2006.168.07:53:40.95#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.168.07:53:40.95#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.168.07:53:40.95#ibcon#ireg 11 cls_cnt 2 2006.168.07:53:40.95#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.168.07:53:41.01#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.168.07:53:41.01#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.168.07:53:41.01#ibcon#enter wrdev, iclass 14, count 2 2006.168.07:53:41.01#ibcon#first serial, iclass 14, count 2 2006.168.07:53:41.01#ibcon#enter sib2, iclass 14, count 2 2006.168.07:53:41.01#ibcon#flushed, iclass 14, count 2 2006.168.07:53:41.01#ibcon#about to write, iclass 14, count 2 2006.168.07:53:41.01#ibcon#wrote, iclass 14, count 2 2006.168.07:53:41.01#ibcon#about to read 3, iclass 14, count 2 2006.168.07:53:41.03#ibcon#read 3, iclass 14, count 2 2006.168.07:53:41.03#ibcon#about to read 4, iclass 14, count 2 2006.168.07:53:41.03#ibcon#read 4, iclass 14, count 2 2006.168.07:53:41.03#ibcon#about to read 5, iclass 14, count 2 2006.168.07:53:41.03#ibcon#read 5, iclass 14, count 2 2006.168.07:53:41.03#ibcon#about to read 6, iclass 14, count 2 2006.168.07:53:41.03#ibcon#read 6, iclass 14, count 2 2006.168.07:53:41.03#ibcon#end of sib2, iclass 14, count 2 2006.168.07:53:41.03#ibcon#*mode == 0, iclass 14, count 2 2006.168.07:53:41.03#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.168.07:53:41.03#ibcon#[27=AT02-04\r\n] 2006.168.07:53:41.03#ibcon#*before write, iclass 14, count 2 2006.168.07:53:41.03#ibcon#enter sib2, iclass 14, count 2 2006.168.07:53:41.03#ibcon#flushed, iclass 14, count 2 2006.168.07:53:41.03#ibcon#about to write, iclass 14, count 2 2006.168.07:53:41.03#ibcon#wrote, iclass 14, count 2 2006.168.07:53:41.03#ibcon#about to read 3, iclass 14, count 2 2006.168.07:53:41.06#ibcon#read 3, iclass 14, count 2 2006.168.07:53:41.06#ibcon#about to read 4, iclass 14, count 2 2006.168.07:53:41.06#ibcon#read 4, iclass 14, count 2 2006.168.07:53:41.06#ibcon#about to read 5, iclass 14, count 2 2006.168.07:53:41.06#ibcon#read 5, iclass 14, count 2 2006.168.07:53:41.06#ibcon#about to read 6, iclass 14, count 2 2006.168.07:53:41.06#ibcon#read 6, iclass 14, count 2 2006.168.07:53:41.06#ibcon#end of sib2, iclass 14, count 2 2006.168.07:53:41.06#ibcon#*after write, iclass 14, count 2 2006.168.07:53:41.06#ibcon#*before return 0, iclass 14, count 2 2006.168.07:53:41.06#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.168.07:53:41.06#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.168.07:53:41.06#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.168.07:53:41.06#ibcon#ireg 7 cls_cnt 0 2006.168.07:53:41.06#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.168.07:53:41.18#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.168.07:53:41.18#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.168.07:53:41.18#ibcon#enter wrdev, iclass 14, count 0 2006.168.07:53:41.18#ibcon#first serial, iclass 14, count 0 2006.168.07:53:41.18#ibcon#enter sib2, iclass 14, count 0 2006.168.07:53:41.18#ibcon#flushed, iclass 14, count 0 2006.168.07:53:41.18#ibcon#about to write, iclass 14, count 0 2006.168.07:53:41.18#ibcon#wrote, iclass 14, count 0 2006.168.07:53:41.18#ibcon#about to read 3, iclass 14, count 0 2006.168.07:53:41.20#ibcon#read 3, iclass 14, count 0 2006.168.07:53:41.20#ibcon#about to read 4, iclass 14, count 0 2006.168.07:53:41.20#ibcon#read 4, iclass 14, count 0 2006.168.07:53:41.20#ibcon#about to read 5, iclass 14, count 0 2006.168.07:53:41.20#ibcon#read 5, iclass 14, count 0 2006.168.07:53:41.20#ibcon#about to read 6, iclass 14, count 0 2006.168.07:53:41.20#ibcon#read 6, iclass 14, count 0 2006.168.07:53:41.20#ibcon#end of sib2, iclass 14, count 0 2006.168.07:53:41.20#ibcon#*mode == 0, iclass 14, count 0 2006.168.07:53:41.20#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.168.07:53:41.20#ibcon#[27=USB\r\n] 2006.168.07:53:41.20#ibcon#*before write, iclass 14, count 0 2006.168.07:53:41.20#ibcon#enter sib2, iclass 14, count 0 2006.168.07:53:41.20#ibcon#flushed, iclass 14, count 0 2006.168.07:53:41.20#ibcon#about to write, iclass 14, count 0 2006.168.07:53:41.20#ibcon#wrote, iclass 14, count 0 2006.168.07:53:41.20#ibcon#about to read 3, iclass 14, count 0 2006.168.07:53:41.23#ibcon#read 3, iclass 14, count 0 2006.168.07:53:41.23#ibcon#about to read 4, iclass 14, count 0 2006.168.07:53:41.23#ibcon#read 4, iclass 14, count 0 2006.168.07:53:41.23#ibcon#about to read 5, iclass 14, count 0 2006.168.07:53:41.23#ibcon#read 5, iclass 14, count 0 2006.168.07:53:41.23#ibcon#about to read 6, iclass 14, count 0 2006.168.07:53:41.23#ibcon#read 6, iclass 14, count 0 2006.168.07:53:41.23#ibcon#end of sib2, iclass 14, count 0 2006.168.07:53:41.23#ibcon#*after write, iclass 14, count 0 2006.168.07:53:41.23#ibcon#*before return 0, iclass 14, count 0 2006.168.07:53:41.23#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.168.07:53:41.23#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.168.07:53:41.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.168.07:53:41.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.168.07:53:41.23$vc4f8/vblo=3,656.99 2006.168.07:53:41.23#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.168.07:53:41.23#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.168.07:53:41.23#ibcon#ireg 17 cls_cnt 0 2006.168.07:53:41.23#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:53:41.23#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:53:41.23#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:53:41.23#ibcon#enter wrdev, iclass 16, count 0 2006.168.07:53:41.23#ibcon#first serial, iclass 16, count 0 2006.168.07:53:41.23#ibcon#enter sib2, iclass 16, count 0 2006.168.07:53:41.23#ibcon#flushed, iclass 16, count 0 2006.168.07:53:41.23#ibcon#about to write, iclass 16, count 0 2006.168.07:53:41.23#ibcon#wrote, iclass 16, count 0 2006.168.07:53:41.23#ibcon#about to read 3, iclass 16, count 0 2006.168.07:53:41.25#ibcon#read 3, iclass 16, count 0 2006.168.07:53:41.25#ibcon#about to read 4, iclass 16, count 0 2006.168.07:53:41.25#ibcon#read 4, iclass 16, count 0 2006.168.07:53:41.25#ibcon#about to read 5, iclass 16, count 0 2006.168.07:53:41.25#ibcon#read 5, iclass 16, count 0 2006.168.07:53:41.25#ibcon#about to read 6, iclass 16, count 0 2006.168.07:53:41.25#ibcon#read 6, iclass 16, count 0 2006.168.07:53:41.25#ibcon#end of sib2, iclass 16, count 0 2006.168.07:53:41.25#ibcon#*mode == 0, iclass 16, count 0 2006.168.07:53:41.25#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.168.07:53:41.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.07:53:41.25#ibcon#*before write, iclass 16, count 0 2006.168.07:53:41.25#ibcon#enter sib2, iclass 16, count 0 2006.168.07:53:41.25#ibcon#flushed, iclass 16, count 0 2006.168.07:53:41.25#ibcon#about to write, iclass 16, count 0 2006.168.07:53:41.25#ibcon#wrote, iclass 16, count 0 2006.168.07:53:41.25#ibcon#about to read 3, iclass 16, count 0 2006.168.07:53:41.29#ibcon#read 3, iclass 16, count 0 2006.168.07:53:41.29#ibcon#about to read 4, iclass 16, count 0 2006.168.07:53:41.29#ibcon#read 4, iclass 16, count 0 2006.168.07:53:41.29#ibcon#about to read 5, iclass 16, count 0 2006.168.07:53:41.29#ibcon#read 5, iclass 16, count 0 2006.168.07:53:41.29#ibcon#about to read 6, iclass 16, count 0 2006.168.07:53:41.29#ibcon#read 6, iclass 16, count 0 2006.168.07:53:41.29#ibcon#end of sib2, iclass 16, count 0 2006.168.07:53:41.29#ibcon#*after write, iclass 16, count 0 2006.168.07:53:41.29#ibcon#*before return 0, iclass 16, count 0 2006.168.07:53:41.29#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:53:41.29#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.168.07:53:41.29#ibcon#about to clear, iclass 16 cls_cnt 0 2006.168.07:53:41.29#ibcon#cleared, iclass 16 cls_cnt 0 2006.168.07:53:41.29$vc4f8/vb=3,4 2006.168.07:53:41.29#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.168.07:53:41.29#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.168.07:53:41.29#ibcon#ireg 11 cls_cnt 2 2006.168.07:53:41.29#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:53:41.35#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:53:41.35#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:53:41.35#ibcon#enter wrdev, iclass 18, count 2 2006.168.07:53:41.35#ibcon#first serial, iclass 18, count 2 2006.168.07:53:41.35#ibcon#enter sib2, iclass 18, count 2 2006.168.07:53:41.35#ibcon#flushed, iclass 18, count 2 2006.168.07:53:41.35#ibcon#about to write, iclass 18, count 2 2006.168.07:53:41.35#ibcon#wrote, iclass 18, count 2 2006.168.07:53:41.35#ibcon#about to read 3, iclass 18, count 2 2006.168.07:53:41.37#ibcon#read 3, iclass 18, count 2 2006.168.07:53:41.37#ibcon#about to read 4, iclass 18, count 2 2006.168.07:53:41.37#ibcon#read 4, iclass 18, count 2 2006.168.07:53:41.37#ibcon#about to read 5, iclass 18, count 2 2006.168.07:53:41.37#ibcon#read 5, iclass 18, count 2 2006.168.07:53:41.37#ibcon#about to read 6, iclass 18, count 2 2006.168.07:53:41.37#ibcon#read 6, iclass 18, count 2 2006.168.07:53:41.37#ibcon#end of sib2, iclass 18, count 2 2006.168.07:53:41.37#ibcon#*mode == 0, iclass 18, count 2 2006.168.07:53:41.37#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.168.07:53:41.37#ibcon#[27=AT03-04\r\n] 2006.168.07:53:41.37#ibcon#*before write, iclass 18, count 2 2006.168.07:53:41.37#ibcon#enter sib2, iclass 18, count 2 2006.168.07:53:41.37#ibcon#flushed, iclass 18, count 2 2006.168.07:53:41.37#ibcon#about to write, iclass 18, count 2 2006.168.07:53:41.37#ibcon#wrote, iclass 18, count 2 2006.168.07:53:41.37#ibcon#about to read 3, iclass 18, count 2 2006.168.07:53:41.40#ibcon#read 3, iclass 18, count 2 2006.168.07:53:41.40#ibcon#about to read 4, iclass 18, count 2 2006.168.07:53:41.40#ibcon#read 4, iclass 18, count 2 2006.168.07:53:41.40#ibcon#about to read 5, iclass 18, count 2 2006.168.07:53:41.40#ibcon#read 5, iclass 18, count 2 2006.168.07:53:41.40#ibcon#about to read 6, iclass 18, count 2 2006.168.07:53:41.40#ibcon#read 6, iclass 18, count 2 2006.168.07:53:41.40#ibcon#end of sib2, iclass 18, count 2 2006.168.07:53:41.40#ibcon#*after write, iclass 18, count 2 2006.168.07:53:41.40#ibcon#*before return 0, iclass 18, count 2 2006.168.07:53:41.40#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:53:41.40#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.168.07:53:41.40#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.168.07:53:41.40#ibcon#ireg 7 cls_cnt 0 2006.168.07:53:41.40#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:53:41.52#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:53:41.52#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:53:41.52#ibcon#enter wrdev, iclass 18, count 0 2006.168.07:53:41.52#ibcon#first serial, iclass 18, count 0 2006.168.07:53:41.52#ibcon#enter sib2, iclass 18, count 0 2006.168.07:53:41.52#ibcon#flushed, iclass 18, count 0 2006.168.07:53:41.52#ibcon#about to write, iclass 18, count 0 2006.168.07:53:41.52#ibcon#wrote, iclass 18, count 0 2006.168.07:53:41.52#ibcon#about to read 3, iclass 18, count 0 2006.168.07:53:41.54#ibcon#read 3, iclass 18, count 0 2006.168.07:53:41.54#ibcon#about to read 4, iclass 18, count 0 2006.168.07:53:41.54#ibcon#read 4, iclass 18, count 0 2006.168.07:53:41.54#ibcon#about to read 5, iclass 18, count 0 2006.168.07:53:41.54#ibcon#read 5, iclass 18, count 0 2006.168.07:53:41.54#ibcon#about to read 6, iclass 18, count 0 2006.168.07:53:41.54#ibcon#read 6, iclass 18, count 0 2006.168.07:53:41.54#ibcon#end of sib2, iclass 18, count 0 2006.168.07:53:41.54#ibcon#*mode == 0, iclass 18, count 0 2006.168.07:53:41.54#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.07:53:41.54#ibcon#[27=USB\r\n] 2006.168.07:53:41.54#ibcon#*before write, iclass 18, count 0 2006.168.07:53:41.54#ibcon#enter sib2, iclass 18, count 0 2006.168.07:53:41.54#ibcon#flushed, iclass 18, count 0 2006.168.07:53:41.54#ibcon#about to write, iclass 18, count 0 2006.168.07:53:41.54#ibcon#wrote, iclass 18, count 0 2006.168.07:53:41.54#ibcon#about to read 3, iclass 18, count 0 2006.168.07:53:41.57#ibcon#read 3, iclass 18, count 0 2006.168.07:53:41.57#ibcon#about to read 4, iclass 18, count 0 2006.168.07:53:41.57#ibcon#read 4, iclass 18, count 0 2006.168.07:53:41.57#ibcon#about to read 5, iclass 18, count 0 2006.168.07:53:41.57#ibcon#read 5, iclass 18, count 0 2006.168.07:53:41.57#ibcon#about to read 6, iclass 18, count 0 2006.168.07:53:41.57#ibcon#read 6, iclass 18, count 0 2006.168.07:53:41.57#ibcon#end of sib2, iclass 18, count 0 2006.168.07:53:41.57#ibcon#*after write, iclass 18, count 0 2006.168.07:53:41.57#ibcon#*before return 0, iclass 18, count 0 2006.168.07:53:41.57#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:53:41.57#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.168.07:53:41.57#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.07:53:41.57#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.07:53:41.57$vc4f8/vblo=4,712.99 2006.168.07:53:41.57#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.168.07:53:41.57#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.168.07:53:41.57#ibcon#ireg 17 cls_cnt 0 2006.168.07:53:41.57#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:53:41.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:53:41.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:53:41.57#ibcon#enter wrdev, iclass 20, count 0 2006.168.07:53:41.57#ibcon#first serial, iclass 20, count 0 2006.168.07:53:41.57#ibcon#enter sib2, iclass 20, count 0 2006.168.07:53:41.57#ibcon#flushed, iclass 20, count 0 2006.168.07:53:41.57#ibcon#about to write, iclass 20, count 0 2006.168.07:53:41.57#ibcon#wrote, iclass 20, count 0 2006.168.07:53:41.57#ibcon#about to read 3, iclass 20, count 0 2006.168.07:53:41.59#ibcon#read 3, iclass 20, count 0 2006.168.07:53:41.59#ibcon#about to read 4, iclass 20, count 0 2006.168.07:53:41.59#ibcon#read 4, iclass 20, count 0 2006.168.07:53:41.59#ibcon#about to read 5, iclass 20, count 0 2006.168.07:53:41.59#ibcon#read 5, iclass 20, count 0 2006.168.07:53:41.59#ibcon#about to read 6, iclass 20, count 0 2006.168.07:53:41.59#ibcon#read 6, iclass 20, count 0 2006.168.07:53:41.59#ibcon#end of sib2, iclass 20, count 0 2006.168.07:53:41.59#ibcon#*mode == 0, iclass 20, count 0 2006.168.07:53:41.59#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.168.07:53:41.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.07:53:41.59#ibcon#*before write, iclass 20, count 0 2006.168.07:53:41.59#ibcon#enter sib2, iclass 20, count 0 2006.168.07:53:41.59#ibcon#flushed, iclass 20, count 0 2006.168.07:53:41.59#ibcon#about to write, iclass 20, count 0 2006.168.07:53:41.59#ibcon#wrote, iclass 20, count 0 2006.168.07:53:41.59#ibcon#about to read 3, iclass 20, count 0 2006.168.07:53:41.63#ibcon#read 3, iclass 20, count 0 2006.168.07:53:41.63#ibcon#about to read 4, iclass 20, count 0 2006.168.07:53:41.63#ibcon#read 4, iclass 20, count 0 2006.168.07:53:41.63#ibcon#about to read 5, iclass 20, count 0 2006.168.07:53:41.63#ibcon#read 5, iclass 20, count 0 2006.168.07:53:41.63#ibcon#about to read 6, iclass 20, count 0 2006.168.07:53:41.63#ibcon#read 6, iclass 20, count 0 2006.168.07:53:41.63#ibcon#end of sib2, iclass 20, count 0 2006.168.07:53:41.63#ibcon#*after write, iclass 20, count 0 2006.168.07:53:41.63#ibcon#*before return 0, iclass 20, count 0 2006.168.07:53:41.63#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:53:41.63#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.168.07:53:41.63#ibcon#about to clear, iclass 20 cls_cnt 0 2006.168.07:53:41.63#ibcon#cleared, iclass 20 cls_cnt 0 2006.168.07:53:41.63$vc4f8/vb=4,4 2006.168.07:53:41.63#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.168.07:53:41.63#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.168.07:53:41.63#ibcon#ireg 11 cls_cnt 2 2006.168.07:53:41.63#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:53:41.69#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:53:41.69#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:53:41.69#ibcon#enter wrdev, iclass 22, count 2 2006.168.07:53:41.69#ibcon#first serial, iclass 22, count 2 2006.168.07:53:41.69#ibcon#enter sib2, iclass 22, count 2 2006.168.07:53:41.69#ibcon#flushed, iclass 22, count 2 2006.168.07:53:41.69#ibcon#about to write, iclass 22, count 2 2006.168.07:53:41.69#ibcon#wrote, iclass 22, count 2 2006.168.07:53:41.69#ibcon#about to read 3, iclass 22, count 2 2006.168.07:53:41.70#abcon#<5=/08 1.7 5.4 27.27 731004.6\r\n> 2006.168.07:53:41.71#ibcon#read 3, iclass 22, count 2 2006.168.07:53:41.71#ibcon#about to read 4, iclass 22, count 2 2006.168.07:53:41.71#ibcon#read 4, iclass 22, count 2 2006.168.07:53:41.71#ibcon#about to read 5, iclass 22, count 2 2006.168.07:53:41.71#ibcon#read 5, iclass 22, count 2 2006.168.07:53:41.71#ibcon#about to read 6, iclass 22, count 2 2006.168.07:53:41.71#ibcon#read 6, iclass 22, count 2 2006.168.07:53:41.71#ibcon#end of sib2, iclass 22, count 2 2006.168.07:53:41.71#ibcon#*mode == 0, iclass 22, count 2 2006.168.07:53:41.71#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.168.07:53:41.71#ibcon#[27=AT04-04\r\n] 2006.168.07:53:41.71#ibcon#*before write, iclass 22, count 2 2006.168.07:53:41.71#ibcon#enter sib2, iclass 22, count 2 2006.168.07:53:41.71#ibcon#flushed, iclass 22, count 2 2006.168.07:53:41.71#ibcon#about to write, iclass 22, count 2 2006.168.07:53:41.71#ibcon#wrote, iclass 22, count 2 2006.168.07:53:41.71#ibcon#about to read 3, iclass 22, count 2 2006.168.07:53:41.72#abcon#{5=INTERFACE CLEAR} 2006.168.07:53:41.74#ibcon#read 3, iclass 22, count 2 2006.168.07:53:41.74#ibcon#about to read 4, iclass 22, count 2 2006.168.07:53:41.74#ibcon#read 4, iclass 22, count 2 2006.168.07:53:41.74#ibcon#about to read 5, iclass 22, count 2 2006.168.07:53:41.74#ibcon#read 5, iclass 22, count 2 2006.168.07:53:41.74#ibcon#about to read 6, iclass 22, count 2 2006.168.07:53:41.74#ibcon#read 6, iclass 22, count 2 2006.168.07:53:41.74#ibcon#end of sib2, iclass 22, count 2 2006.168.07:53:41.74#ibcon#*after write, iclass 22, count 2 2006.168.07:53:41.74#ibcon#*before return 0, iclass 22, count 2 2006.168.07:53:41.74#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:53:41.74#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.168.07:53:41.74#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.168.07:53:41.74#ibcon#ireg 7 cls_cnt 0 2006.168.07:53:41.74#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:53:41.78#abcon#[5=S1D000X0/0*\r\n] 2006.168.07:53:41.86#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:53:41.86#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:53:41.86#ibcon#enter wrdev, iclass 22, count 0 2006.168.07:53:41.86#ibcon#first serial, iclass 22, count 0 2006.168.07:53:41.86#ibcon#enter sib2, iclass 22, count 0 2006.168.07:53:41.86#ibcon#flushed, iclass 22, count 0 2006.168.07:53:41.86#ibcon#about to write, iclass 22, count 0 2006.168.07:53:41.86#ibcon#wrote, iclass 22, count 0 2006.168.07:53:41.86#ibcon#about to read 3, iclass 22, count 0 2006.168.07:53:41.88#ibcon#read 3, iclass 22, count 0 2006.168.07:53:41.88#ibcon#about to read 4, iclass 22, count 0 2006.168.07:53:41.88#ibcon#read 4, iclass 22, count 0 2006.168.07:53:41.88#ibcon#about to read 5, iclass 22, count 0 2006.168.07:53:41.88#ibcon#read 5, iclass 22, count 0 2006.168.07:53:41.88#ibcon#about to read 6, iclass 22, count 0 2006.168.07:53:41.88#ibcon#read 6, iclass 22, count 0 2006.168.07:53:41.88#ibcon#end of sib2, iclass 22, count 0 2006.168.07:53:41.88#ibcon#*mode == 0, iclass 22, count 0 2006.168.07:53:41.88#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.168.07:53:41.88#ibcon#[27=USB\r\n] 2006.168.07:53:41.88#ibcon#*before write, iclass 22, count 0 2006.168.07:53:41.88#ibcon#enter sib2, iclass 22, count 0 2006.168.07:53:41.88#ibcon#flushed, iclass 22, count 0 2006.168.07:53:41.88#ibcon#about to write, iclass 22, count 0 2006.168.07:53:41.88#ibcon#wrote, iclass 22, count 0 2006.168.07:53:41.88#ibcon#about to read 3, iclass 22, count 0 2006.168.07:53:41.91#ibcon#read 3, iclass 22, count 0 2006.168.07:53:41.91#ibcon#about to read 4, iclass 22, count 0 2006.168.07:53:41.91#ibcon#read 4, iclass 22, count 0 2006.168.07:53:41.91#ibcon#about to read 5, iclass 22, count 0 2006.168.07:53:41.91#ibcon#read 5, iclass 22, count 0 2006.168.07:53:41.91#ibcon#about to read 6, iclass 22, count 0 2006.168.07:53:41.91#ibcon#read 6, iclass 22, count 0 2006.168.07:53:41.91#ibcon#end of sib2, iclass 22, count 0 2006.168.07:53:41.91#ibcon#*after write, iclass 22, count 0 2006.168.07:53:41.91#ibcon#*before return 0, iclass 22, count 0 2006.168.07:53:41.91#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:53:41.91#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.168.07:53:41.91#ibcon#about to clear, iclass 22 cls_cnt 0 2006.168.07:53:41.91#ibcon#cleared, iclass 22 cls_cnt 0 2006.168.07:53:41.91$vc4f8/vblo=5,744.99 2006.168.07:53:41.91#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.168.07:53:41.91#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.168.07:53:41.91#ibcon#ireg 17 cls_cnt 0 2006.168.07:53:41.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:53:41.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:53:41.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:53:41.91#ibcon#enter wrdev, iclass 28, count 0 2006.168.07:53:41.91#ibcon#first serial, iclass 28, count 0 2006.168.07:53:41.91#ibcon#enter sib2, iclass 28, count 0 2006.168.07:53:41.91#ibcon#flushed, iclass 28, count 0 2006.168.07:53:41.91#ibcon#about to write, iclass 28, count 0 2006.168.07:53:41.91#ibcon#wrote, iclass 28, count 0 2006.168.07:53:41.91#ibcon#about to read 3, iclass 28, count 0 2006.168.07:53:41.93#ibcon#read 3, iclass 28, count 0 2006.168.07:53:41.93#ibcon#about to read 4, iclass 28, count 0 2006.168.07:53:41.93#ibcon#read 4, iclass 28, count 0 2006.168.07:53:41.93#ibcon#about to read 5, iclass 28, count 0 2006.168.07:53:41.93#ibcon#read 5, iclass 28, count 0 2006.168.07:53:41.93#ibcon#about to read 6, iclass 28, count 0 2006.168.07:53:41.93#ibcon#read 6, iclass 28, count 0 2006.168.07:53:41.93#ibcon#end of sib2, iclass 28, count 0 2006.168.07:53:41.93#ibcon#*mode == 0, iclass 28, count 0 2006.168.07:53:41.93#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.168.07:53:41.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.07:53:41.93#ibcon#*before write, iclass 28, count 0 2006.168.07:53:41.93#ibcon#enter sib2, iclass 28, count 0 2006.168.07:53:41.93#ibcon#flushed, iclass 28, count 0 2006.168.07:53:41.93#ibcon#about to write, iclass 28, count 0 2006.168.07:53:41.93#ibcon#wrote, iclass 28, count 0 2006.168.07:53:41.93#ibcon#about to read 3, iclass 28, count 0 2006.168.07:53:41.97#ibcon#read 3, iclass 28, count 0 2006.168.07:53:41.97#ibcon#about to read 4, iclass 28, count 0 2006.168.07:53:41.97#ibcon#read 4, iclass 28, count 0 2006.168.07:53:41.97#ibcon#about to read 5, iclass 28, count 0 2006.168.07:53:41.97#ibcon#read 5, iclass 28, count 0 2006.168.07:53:41.97#ibcon#about to read 6, iclass 28, count 0 2006.168.07:53:41.97#ibcon#read 6, iclass 28, count 0 2006.168.07:53:41.97#ibcon#end of sib2, iclass 28, count 0 2006.168.07:53:41.97#ibcon#*after write, iclass 28, count 0 2006.168.07:53:41.97#ibcon#*before return 0, iclass 28, count 0 2006.168.07:53:41.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:53:41.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.168.07:53:41.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.168.07:53:41.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.168.07:53:41.97$vc4f8/vb=5,4 2006.168.07:53:41.97#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.168.07:53:41.97#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.168.07:53:41.97#ibcon#ireg 11 cls_cnt 2 2006.168.07:53:41.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:53:42.03#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:53:42.03#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:53:42.03#ibcon#enter wrdev, iclass 30, count 2 2006.168.07:53:42.03#ibcon#first serial, iclass 30, count 2 2006.168.07:53:42.03#ibcon#enter sib2, iclass 30, count 2 2006.168.07:53:42.03#ibcon#flushed, iclass 30, count 2 2006.168.07:53:42.03#ibcon#about to write, iclass 30, count 2 2006.168.07:53:42.03#ibcon#wrote, iclass 30, count 2 2006.168.07:53:42.03#ibcon#about to read 3, iclass 30, count 2 2006.168.07:53:42.05#ibcon#read 3, iclass 30, count 2 2006.168.07:53:42.05#ibcon#about to read 4, iclass 30, count 2 2006.168.07:53:42.05#ibcon#read 4, iclass 30, count 2 2006.168.07:53:42.05#ibcon#about to read 5, iclass 30, count 2 2006.168.07:53:42.05#ibcon#read 5, iclass 30, count 2 2006.168.07:53:42.05#ibcon#about to read 6, iclass 30, count 2 2006.168.07:53:42.05#ibcon#read 6, iclass 30, count 2 2006.168.07:53:42.05#ibcon#end of sib2, iclass 30, count 2 2006.168.07:53:42.05#ibcon#*mode == 0, iclass 30, count 2 2006.168.07:53:42.05#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.168.07:53:42.05#ibcon#[27=AT05-04\r\n] 2006.168.07:53:42.05#ibcon#*before write, iclass 30, count 2 2006.168.07:53:42.05#ibcon#enter sib2, iclass 30, count 2 2006.168.07:53:42.05#ibcon#flushed, iclass 30, count 2 2006.168.07:53:42.05#ibcon#about to write, iclass 30, count 2 2006.168.07:53:42.05#ibcon#wrote, iclass 30, count 2 2006.168.07:53:42.05#ibcon#about to read 3, iclass 30, count 2 2006.168.07:53:42.08#ibcon#read 3, iclass 30, count 2 2006.168.07:53:42.08#ibcon#about to read 4, iclass 30, count 2 2006.168.07:53:42.08#ibcon#read 4, iclass 30, count 2 2006.168.07:53:42.08#ibcon#about to read 5, iclass 30, count 2 2006.168.07:53:42.08#ibcon#read 5, iclass 30, count 2 2006.168.07:53:42.08#ibcon#about to read 6, iclass 30, count 2 2006.168.07:53:42.08#ibcon#read 6, iclass 30, count 2 2006.168.07:53:42.08#ibcon#end of sib2, iclass 30, count 2 2006.168.07:53:42.08#ibcon#*after write, iclass 30, count 2 2006.168.07:53:42.08#ibcon#*before return 0, iclass 30, count 2 2006.168.07:53:42.08#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:53:42.08#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.168.07:53:42.08#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.168.07:53:42.08#ibcon#ireg 7 cls_cnt 0 2006.168.07:53:42.08#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:53:42.20#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:53:42.20#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:53:42.20#ibcon#enter wrdev, iclass 30, count 0 2006.168.07:53:42.20#ibcon#first serial, iclass 30, count 0 2006.168.07:53:42.20#ibcon#enter sib2, iclass 30, count 0 2006.168.07:53:42.20#ibcon#flushed, iclass 30, count 0 2006.168.07:53:42.20#ibcon#about to write, iclass 30, count 0 2006.168.07:53:42.20#ibcon#wrote, iclass 30, count 0 2006.168.07:53:42.20#ibcon#about to read 3, iclass 30, count 0 2006.168.07:53:42.22#ibcon#read 3, iclass 30, count 0 2006.168.07:53:42.22#ibcon#about to read 4, iclass 30, count 0 2006.168.07:53:42.22#ibcon#read 4, iclass 30, count 0 2006.168.07:53:42.22#ibcon#about to read 5, iclass 30, count 0 2006.168.07:53:42.22#ibcon#read 5, iclass 30, count 0 2006.168.07:53:42.22#ibcon#about to read 6, iclass 30, count 0 2006.168.07:53:42.22#ibcon#read 6, iclass 30, count 0 2006.168.07:53:42.22#ibcon#end of sib2, iclass 30, count 0 2006.168.07:53:42.22#ibcon#*mode == 0, iclass 30, count 0 2006.168.07:53:42.22#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.168.07:53:42.22#ibcon#[27=USB\r\n] 2006.168.07:53:42.22#ibcon#*before write, iclass 30, count 0 2006.168.07:53:42.22#ibcon#enter sib2, iclass 30, count 0 2006.168.07:53:42.22#ibcon#flushed, iclass 30, count 0 2006.168.07:53:42.22#ibcon#about to write, iclass 30, count 0 2006.168.07:53:42.22#ibcon#wrote, iclass 30, count 0 2006.168.07:53:42.22#ibcon#about to read 3, iclass 30, count 0 2006.168.07:53:42.25#ibcon#read 3, iclass 30, count 0 2006.168.07:53:42.25#ibcon#about to read 4, iclass 30, count 0 2006.168.07:53:42.25#ibcon#read 4, iclass 30, count 0 2006.168.07:53:42.25#ibcon#about to read 5, iclass 30, count 0 2006.168.07:53:42.25#ibcon#read 5, iclass 30, count 0 2006.168.07:53:42.25#ibcon#about to read 6, iclass 30, count 0 2006.168.07:53:42.25#ibcon#read 6, iclass 30, count 0 2006.168.07:53:42.25#ibcon#end of sib2, iclass 30, count 0 2006.168.07:53:42.25#ibcon#*after write, iclass 30, count 0 2006.168.07:53:42.25#ibcon#*before return 0, iclass 30, count 0 2006.168.07:53:42.25#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:53:42.25#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.168.07:53:42.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.168.07:53:42.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.168.07:53:42.25$vc4f8/vblo=6,752.99 2006.168.07:53:42.25#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.168.07:53:42.25#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.168.07:53:42.25#ibcon#ireg 17 cls_cnt 0 2006.168.07:53:42.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:53:42.25#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:53:42.25#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:53:42.25#ibcon#enter wrdev, iclass 32, count 0 2006.168.07:53:42.25#ibcon#first serial, iclass 32, count 0 2006.168.07:53:42.25#ibcon#enter sib2, iclass 32, count 0 2006.168.07:53:42.25#ibcon#flushed, iclass 32, count 0 2006.168.07:53:42.25#ibcon#about to write, iclass 32, count 0 2006.168.07:53:42.25#ibcon#wrote, iclass 32, count 0 2006.168.07:53:42.25#ibcon#about to read 3, iclass 32, count 0 2006.168.07:53:42.27#ibcon#read 3, iclass 32, count 0 2006.168.07:53:42.27#ibcon#about to read 4, iclass 32, count 0 2006.168.07:53:42.27#ibcon#read 4, iclass 32, count 0 2006.168.07:53:42.27#ibcon#about to read 5, iclass 32, count 0 2006.168.07:53:42.27#ibcon#read 5, iclass 32, count 0 2006.168.07:53:42.27#ibcon#about to read 6, iclass 32, count 0 2006.168.07:53:42.27#ibcon#read 6, iclass 32, count 0 2006.168.07:53:42.27#ibcon#end of sib2, iclass 32, count 0 2006.168.07:53:42.27#ibcon#*mode == 0, iclass 32, count 0 2006.168.07:53:42.27#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.168.07:53:42.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.07:53:42.27#ibcon#*before write, iclass 32, count 0 2006.168.07:53:42.27#ibcon#enter sib2, iclass 32, count 0 2006.168.07:53:42.27#ibcon#flushed, iclass 32, count 0 2006.168.07:53:42.27#ibcon#about to write, iclass 32, count 0 2006.168.07:53:42.27#ibcon#wrote, iclass 32, count 0 2006.168.07:53:42.27#ibcon#about to read 3, iclass 32, count 0 2006.168.07:53:42.31#ibcon#read 3, iclass 32, count 0 2006.168.07:53:42.31#ibcon#about to read 4, iclass 32, count 0 2006.168.07:53:42.31#ibcon#read 4, iclass 32, count 0 2006.168.07:53:42.31#ibcon#about to read 5, iclass 32, count 0 2006.168.07:53:42.31#ibcon#read 5, iclass 32, count 0 2006.168.07:53:42.31#ibcon#about to read 6, iclass 32, count 0 2006.168.07:53:42.31#ibcon#read 6, iclass 32, count 0 2006.168.07:53:42.31#ibcon#end of sib2, iclass 32, count 0 2006.168.07:53:42.31#ibcon#*after write, iclass 32, count 0 2006.168.07:53:42.31#ibcon#*before return 0, iclass 32, count 0 2006.168.07:53:42.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:53:42.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.168.07:53:42.31#ibcon#about to clear, iclass 32 cls_cnt 0 2006.168.07:53:42.31#ibcon#cleared, iclass 32 cls_cnt 0 2006.168.07:53:42.31$vc4f8/vb=6,4 2006.168.07:53:42.31#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.168.07:53:42.31#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.168.07:53:42.31#ibcon#ireg 11 cls_cnt 2 2006.168.07:53:42.31#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:53:42.37#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:53:42.37#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:53:42.37#ibcon#enter wrdev, iclass 34, count 2 2006.168.07:53:42.37#ibcon#first serial, iclass 34, count 2 2006.168.07:53:42.37#ibcon#enter sib2, iclass 34, count 2 2006.168.07:53:42.37#ibcon#flushed, iclass 34, count 2 2006.168.07:53:42.37#ibcon#about to write, iclass 34, count 2 2006.168.07:53:42.37#ibcon#wrote, iclass 34, count 2 2006.168.07:53:42.37#ibcon#about to read 3, iclass 34, count 2 2006.168.07:53:42.39#ibcon#read 3, iclass 34, count 2 2006.168.07:53:42.39#ibcon#about to read 4, iclass 34, count 2 2006.168.07:53:42.39#ibcon#read 4, iclass 34, count 2 2006.168.07:53:42.39#ibcon#about to read 5, iclass 34, count 2 2006.168.07:53:42.39#ibcon#read 5, iclass 34, count 2 2006.168.07:53:42.39#ibcon#about to read 6, iclass 34, count 2 2006.168.07:53:42.39#ibcon#read 6, iclass 34, count 2 2006.168.07:53:42.39#ibcon#end of sib2, iclass 34, count 2 2006.168.07:53:42.39#ibcon#*mode == 0, iclass 34, count 2 2006.168.07:53:42.39#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.168.07:53:42.39#ibcon#[27=AT06-04\r\n] 2006.168.07:53:42.39#ibcon#*before write, iclass 34, count 2 2006.168.07:53:42.39#ibcon#enter sib2, iclass 34, count 2 2006.168.07:53:42.39#ibcon#flushed, iclass 34, count 2 2006.168.07:53:42.39#ibcon#about to write, iclass 34, count 2 2006.168.07:53:42.39#ibcon#wrote, iclass 34, count 2 2006.168.07:53:42.39#ibcon#about to read 3, iclass 34, count 2 2006.168.07:53:42.42#ibcon#read 3, iclass 34, count 2 2006.168.07:53:42.42#ibcon#about to read 4, iclass 34, count 2 2006.168.07:53:42.42#ibcon#read 4, iclass 34, count 2 2006.168.07:53:42.42#ibcon#about to read 5, iclass 34, count 2 2006.168.07:53:42.42#ibcon#read 5, iclass 34, count 2 2006.168.07:53:42.42#ibcon#about to read 6, iclass 34, count 2 2006.168.07:53:42.42#ibcon#read 6, iclass 34, count 2 2006.168.07:53:42.42#ibcon#end of sib2, iclass 34, count 2 2006.168.07:53:42.42#ibcon#*after write, iclass 34, count 2 2006.168.07:53:42.42#ibcon#*before return 0, iclass 34, count 2 2006.168.07:53:42.42#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:53:42.42#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.168.07:53:42.42#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.168.07:53:42.42#ibcon#ireg 7 cls_cnt 0 2006.168.07:53:42.42#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:53:42.54#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:53:42.54#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:53:42.54#ibcon#enter wrdev, iclass 34, count 0 2006.168.07:53:42.54#ibcon#first serial, iclass 34, count 0 2006.168.07:53:42.54#ibcon#enter sib2, iclass 34, count 0 2006.168.07:53:42.54#ibcon#flushed, iclass 34, count 0 2006.168.07:53:42.54#ibcon#about to write, iclass 34, count 0 2006.168.07:53:42.54#ibcon#wrote, iclass 34, count 0 2006.168.07:53:42.54#ibcon#about to read 3, iclass 34, count 0 2006.168.07:53:42.56#ibcon#read 3, iclass 34, count 0 2006.168.07:53:42.56#ibcon#about to read 4, iclass 34, count 0 2006.168.07:53:42.56#ibcon#read 4, iclass 34, count 0 2006.168.07:53:42.56#ibcon#about to read 5, iclass 34, count 0 2006.168.07:53:42.56#ibcon#read 5, iclass 34, count 0 2006.168.07:53:42.56#ibcon#about to read 6, iclass 34, count 0 2006.168.07:53:42.56#ibcon#read 6, iclass 34, count 0 2006.168.07:53:42.56#ibcon#end of sib2, iclass 34, count 0 2006.168.07:53:42.56#ibcon#*mode == 0, iclass 34, count 0 2006.168.07:53:42.56#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.168.07:53:42.56#ibcon#[27=USB\r\n] 2006.168.07:53:42.56#ibcon#*before write, iclass 34, count 0 2006.168.07:53:42.56#ibcon#enter sib2, iclass 34, count 0 2006.168.07:53:42.56#ibcon#flushed, iclass 34, count 0 2006.168.07:53:42.56#ibcon#about to write, iclass 34, count 0 2006.168.07:53:42.56#ibcon#wrote, iclass 34, count 0 2006.168.07:53:42.56#ibcon#about to read 3, iclass 34, count 0 2006.168.07:53:42.59#ibcon#read 3, iclass 34, count 0 2006.168.07:53:42.59#ibcon#about to read 4, iclass 34, count 0 2006.168.07:53:42.59#ibcon#read 4, iclass 34, count 0 2006.168.07:53:42.59#ibcon#about to read 5, iclass 34, count 0 2006.168.07:53:42.59#ibcon#read 5, iclass 34, count 0 2006.168.07:53:42.59#ibcon#about to read 6, iclass 34, count 0 2006.168.07:53:42.59#ibcon#read 6, iclass 34, count 0 2006.168.07:53:42.59#ibcon#end of sib2, iclass 34, count 0 2006.168.07:53:42.59#ibcon#*after write, iclass 34, count 0 2006.168.07:53:42.59#ibcon#*before return 0, iclass 34, count 0 2006.168.07:53:42.59#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:53:42.59#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.168.07:53:42.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.168.07:53:42.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.168.07:53:42.59$vc4f8/vabw=wide 2006.168.07:53:42.59#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.168.07:53:42.59#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.168.07:53:42.59#ibcon#ireg 8 cls_cnt 0 2006.168.07:53:42.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:53:42.59#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:53:42.59#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:53:42.59#ibcon#enter wrdev, iclass 36, count 0 2006.168.07:53:42.59#ibcon#first serial, iclass 36, count 0 2006.168.07:53:42.59#ibcon#enter sib2, iclass 36, count 0 2006.168.07:53:42.59#ibcon#flushed, iclass 36, count 0 2006.168.07:53:42.59#ibcon#about to write, iclass 36, count 0 2006.168.07:53:42.59#ibcon#wrote, iclass 36, count 0 2006.168.07:53:42.59#ibcon#about to read 3, iclass 36, count 0 2006.168.07:53:42.61#ibcon#read 3, iclass 36, count 0 2006.168.07:53:42.61#ibcon#about to read 4, iclass 36, count 0 2006.168.07:53:42.61#ibcon#read 4, iclass 36, count 0 2006.168.07:53:42.61#ibcon#about to read 5, iclass 36, count 0 2006.168.07:53:42.61#ibcon#read 5, iclass 36, count 0 2006.168.07:53:42.61#ibcon#about to read 6, iclass 36, count 0 2006.168.07:53:42.61#ibcon#read 6, iclass 36, count 0 2006.168.07:53:42.61#ibcon#end of sib2, iclass 36, count 0 2006.168.07:53:42.61#ibcon#*mode == 0, iclass 36, count 0 2006.168.07:53:42.61#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.168.07:53:42.61#ibcon#[25=BW32\r\n] 2006.168.07:53:42.61#ibcon#*before write, iclass 36, count 0 2006.168.07:53:42.61#ibcon#enter sib2, iclass 36, count 0 2006.168.07:53:42.61#ibcon#flushed, iclass 36, count 0 2006.168.07:53:42.61#ibcon#about to write, iclass 36, count 0 2006.168.07:53:42.61#ibcon#wrote, iclass 36, count 0 2006.168.07:53:42.61#ibcon#about to read 3, iclass 36, count 0 2006.168.07:53:42.64#ibcon#read 3, iclass 36, count 0 2006.168.07:53:42.64#ibcon#about to read 4, iclass 36, count 0 2006.168.07:53:42.64#ibcon#read 4, iclass 36, count 0 2006.168.07:53:42.64#ibcon#about to read 5, iclass 36, count 0 2006.168.07:53:42.64#ibcon#read 5, iclass 36, count 0 2006.168.07:53:42.64#ibcon#about to read 6, iclass 36, count 0 2006.168.07:53:42.64#ibcon#read 6, iclass 36, count 0 2006.168.07:53:42.64#ibcon#end of sib2, iclass 36, count 0 2006.168.07:53:42.64#ibcon#*after write, iclass 36, count 0 2006.168.07:53:42.64#ibcon#*before return 0, iclass 36, count 0 2006.168.07:53:42.64#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:53:42.64#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.168.07:53:42.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.168.07:53:42.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.168.07:53:42.64$vc4f8/vbbw=wide 2006.168.07:53:42.64#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.168.07:53:42.64#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.168.07:53:42.64#ibcon#ireg 8 cls_cnt 0 2006.168.07:53:42.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:53:42.71#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:53:42.71#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:53:42.71#ibcon#enter wrdev, iclass 38, count 0 2006.168.07:53:42.71#ibcon#first serial, iclass 38, count 0 2006.168.07:53:42.71#ibcon#enter sib2, iclass 38, count 0 2006.168.07:53:42.71#ibcon#flushed, iclass 38, count 0 2006.168.07:53:42.71#ibcon#about to write, iclass 38, count 0 2006.168.07:53:42.71#ibcon#wrote, iclass 38, count 0 2006.168.07:53:42.71#ibcon#about to read 3, iclass 38, count 0 2006.168.07:53:42.73#ibcon#read 3, iclass 38, count 0 2006.168.07:53:42.73#ibcon#about to read 4, iclass 38, count 0 2006.168.07:53:42.73#ibcon#read 4, iclass 38, count 0 2006.168.07:53:42.73#ibcon#about to read 5, iclass 38, count 0 2006.168.07:53:42.73#ibcon#read 5, iclass 38, count 0 2006.168.07:53:42.73#ibcon#about to read 6, iclass 38, count 0 2006.168.07:53:42.73#ibcon#read 6, iclass 38, count 0 2006.168.07:53:42.73#ibcon#end of sib2, iclass 38, count 0 2006.168.07:53:42.73#ibcon#*mode == 0, iclass 38, count 0 2006.168.07:53:42.73#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.168.07:53:42.73#ibcon#[27=BW32\r\n] 2006.168.07:53:42.73#ibcon#*before write, iclass 38, count 0 2006.168.07:53:42.73#ibcon#enter sib2, iclass 38, count 0 2006.168.07:53:42.73#ibcon#flushed, iclass 38, count 0 2006.168.07:53:42.73#ibcon#about to write, iclass 38, count 0 2006.168.07:53:42.73#ibcon#wrote, iclass 38, count 0 2006.168.07:53:42.73#ibcon#about to read 3, iclass 38, count 0 2006.168.07:53:42.76#ibcon#read 3, iclass 38, count 0 2006.168.07:53:42.76#ibcon#about to read 4, iclass 38, count 0 2006.168.07:53:42.76#ibcon#read 4, iclass 38, count 0 2006.168.07:53:42.76#ibcon#about to read 5, iclass 38, count 0 2006.168.07:53:42.76#ibcon#read 5, iclass 38, count 0 2006.168.07:53:42.76#ibcon#about to read 6, iclass 38, count 0 2006.168.07:53:42.76#ibcon#read 6, iclass 38, count 0 2006.168.07:53:42.76#ibcon#end of sib2, iclass 38, count 0 2006.168.07:53:42.76#ibcon#*after write, iclass 38, count 0 2006.168.07:53:42.76#ibcon#*before return 0, iclass 38, count 0 2006.168.07:53:42.76#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:53:42.76#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.168.07:53:42.76#ibcon#about to clear, iclass 38 cls_cnt 0 2006.168.07:53:42.76#ibcon#cleared, iclass 38 cls_cnt 0 2006.168.07:53:42.76$4f8m12a/ifd4f 2006.168.07:53:42.76$ifd4f/lo= 2006.168.07:53:42.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.07:53:42.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.07:53:42.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.07:53:42.76$ifd4f/patch= 2006.168.07:53:42.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.07:53:42.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.07:53:42.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.07:53:42.77$4f8m12a/"form=m,16.000,1:2 2006.168.07:53:42.77$4f8m12a/"tpicd 2006.168.07:53:42.77$4f8m12a/echo=off 2006.168.07:53:42.77$4f8m12a/xlog=off 2006.168.07:53:42.77:!2006.168.07:55:10 2006.168.07:53:55.13#trakl#Source acquired 2006.168.07:53:57.13#flagr#flagr/antenna,acquired 2006.168.07:55:10.01:preob 2006.168.07:55:11.14/onsource/TRACKING 2006.168.07:55:11.14:!2006.168.07:55:20 2006.168.07:55:20.00:data_valid=on 2006.168.07:55:20.00:midob 2006.168.07:55:20.14/onsource/TRACKING 2006.168.07:55:20.14/wx/27.22,1004.6,73 2006.168.07:55:20.32/cable/+6.4709E-03 2006.168.07:55:21.41/va/01,08,usb,yes,29,31 2006.168.07:55:21.41/va/02,07,usb,yes,29,31 2006.168.07:55:21.41/va/03,06,usb,yes,31,31 2006.168.07:55:21.41/va/04,07,usb,yes,30,32 2006.168.07:55:21.41/va/05,07,usb,yes,30,32 2006.168.07:55:21.41/va/06,06,usb,yes,29,29 2006.168.07:55:21.41/va/07,06,usb,yes,29,29 2006.168.07:55:21.41/va/08,07,usb,yes,28,27 2006.168.07:55:21.64/valo/01,532.99,yes,locked 2006.168.07:55:21.64/valo/02,572.99,yes,locked 2006.168.07:55:21.64/valo/03,672.99,yes,locked 2006.168.07:55:21.64/valo/04,832.99,yes,locked 2006.168.07:55:21.64/valo/05,652.99,yes,locked 2006.168.07:55:21.64/valo/06,772.99,yes,locked 2006.168.07:55:21.64/valo/07,832.99,yes,locked 2006.168.07:55:21.64/valo/08,852.99,yes,locked 2006.168.07:55:22.73/vb/01,04,usb,yes,29,28 2006.168.07:55:22.73/vb/02,04,usb,yes,31,32 2006.168.07:55:22.73/vb/03,04,usb,yes,27,31 2006.168.07:55:22.73/vb/04,04,usb,yes,28,28 2006.168.07:55:22.73/vb/05,04,usb,yes,28,31 2006.168.07:55:22.73/vb/06,04,usb,yes,28,31 2006.168.07:55:22.73/vb/07,04,usb,yes,30,30 2006.168.07:55:22.73/vb/08,04,usb,yes,29,31 2006.168.07:55:22.96/vblo/01,632.99,yes,locked 2006.168.07:55:22.96/vblo/02,640.99,yes,locked 2006.168.07:55:22.96/vblo/03,656.99,yes,locked 2006.168.07:55:22.96/vblo/04,712.99,yes,locked 2006.168.07:55:22.96/vblo/05,744.99,yes,locked 2006.168.07:55:22.96/vblo/06,752.99,yes,locked 2006.168.07:55:22.96/vblo/07,734.99,yes,locked 2006.168.07:55:22.96/vblo/08,744.99,yes,locked 2006.168.07:55:23.11/vabw/8 2006.168.07:55:23.26/vbbw/8 2006.168.07:55:23.43/xfe/off,on,14.5 2006.168.07:55:23.82/ifatt/23,28,28,28 2006.168.07:55:24.07/fmout-gps/S +4.20E-07 2006.168.07:55:24.15:!2006.168.07:56:20 2006.168.07:56:20.01:data_valid=off 2006.168.07:56:20.02:postob 2006.168.07:56:20.17/cable/+6.4717E-03 2006.168.07:56:20.18/wx/27.19,1004.5,74 2006.168.07:56:21.07/fmout-gps/S +4.18E-07 2006.168.07:56:21.08:scan_name=168-0758,k06168,60 2006.168.07:56:21.08:source=0748+126,075052.05,123104.8,2000.0,ccw 2006.168.07:56:22.14#flagr#flagr/antenna,new-source 2006.168.07:56:22.15:checkk5 2006.168.07:56:22.53/chk_autoobs//k5ts1/ autoobs is running! 2006.168.07:56:22.91/chk_autoobs//k5ts2/ autoobs is running! 2006.168.07:56:23.29/chk_autoobs//k5ts3/ autoobs is running! 2006.168.07:56:23.66/chk_autoobs//k5ts4/ autoobs is running! 2006.168.07:56:24.03/chk_obsdata//k5ts1/T1680755??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:56:24.40/chk_obsdata//k5ts2/T1680755??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:56:24.77/chk_obsdata//k5ts3/T1680755??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:56:25.15/chk_obsdata//k5ts4/T1680755??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:56:25.84/k5log//k5ts1_log_newline 2006.168.07:56:26.53/k5log//k5ts2_log_newline 2006.168.07:56:27.22/k5log//k5ts3_log_newline 2006.168.07:56:27.91/k5log//k5ts4_log_newline 2006.168.07:56:27.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.07:56:27.94:4f8m12a=2 2006.168.07:56:27.94$4f8m12a/echo=on 2006.168.07:56:27.94$4f8m12a/pcalon 2006.168.07:56:27.94$pcalon/"no phase cal control is implemented here 2006.168.07:56:27.94$4f8m12a/"tpicd=stop 2006.168.07:56:27.94$4f8m12a/vc4f8 2006.168.07:56:27.94$vc4f8/valo=1,532.99 2006.168.07:56:27.94#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.168.07:56:27.94#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.168.07:56:27.94#ibcon#ireg 17 cls_cnt 0 2006.168.07:56:27.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.168.07:56:27.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.168.07:56:27.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.168.07:56:27.94#ibcon#enter wrdev, iclass 33, count 0 2006.168.07:56:27.94#ibcon#first serial, iclass 33, count 0 2006.168.07:56:27.94#ibcon#enter sib2, iclass 33, count 0 2006.168.07:56:27.94#ibcon#flushed, iclass 33, count 0 2006.168.07:56:27.94#ibcon#about to write, iclass 33, count 0 2006.168.07:56:27.94#ibcon#wrote, iclass 33, count 0 2006.168.07:56:27.94#ibcon#about to read 3, iclass 33, count 0 2006.168.07:56:27.99#ibcon#read 3, iclass 33, count 0 2006.168.07:56:27.99#ibcon#about to read 4, iclass 33, count 0 2006.168.07:56:27.99#ibcon#read 4, iclass 33, count 0 2006.168.07:56:27.99#ibcon#about to read 5, iclass 33, count 0 2006.168.07:56:27.99#ibcon#read 5, iclass 33, count 0 2006.168.07:56:27.99#ibcon#about to read 6, iclass 33, count 0 2006.168.07:56:27.99#ibcon#read 6, iclass 33, count 0 2006.168.07:56:27.99#ibcon#end of sib2, iclass 33, count 0 2006.168.07:56:27.99#ibcon#*mode == 0, iclass 33, count 0 2006.168.07:56:27.99#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.168.07:56:27.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.07:56:27.99#ibcon#*before write, iclass 33, count 0 2006.168.07:56:27.99#ibcon#enter sib2, iclass 33, count 0 2006.168.07:56:27.99#ibcon#flushed, iclass 33, count 0 2006.168.07:56:27.99#ibcon#about to write, iclass 33, count 0 2006.168.07:56:27.99#ibcon#wrote, iclass 33, count 0 2006.168.07:56:27.99#ibcon#about to read 3, iclass 33, count 0 2006.168.07:56:28.03#ibcon#read 3, iclass 33, count 0 2006.168.07:56:28.03#ibcon#about to read 4, iclass 33, count 0 2006.168.07:56:28.03#ibcon#read 4, iclass 33, count 0 2006.168.07:56:28.03#ibcon#about to read 5, iclass 33, count 0 2006.168.07:56:28.03#ibcon#read 5, iclass 33, count 0 2006.168.07:56:28.03#ibcon#about to read 6, iclass 33, count 0 2006.168.07:56:28.03#ibcon#read 6, iclass 33, count 0 2006.168.07:56:28.03#ibcon#end of sib2, iclass 33, count 0 2006.168.07:56:28.03#ibcon#*after write, iclass 33, count 0 2006.168.07:56:28.03#ibcon#*before return 0, iclass 33, count 0 2006.168.07:56:28.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.168.07:56:28.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.168.07:56:28.03#ibcon#about to clear, iclass 33 cls_cnt 0 2006.168.07:56:28.03#ibcon#cleared, iclass 33 cls_cnt 0 2006.168.07:56:28.03$vc4f8/va=1,8 2006.168.07:56:28.03#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.168.07:56:28.03#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.168.07:56:28.03#ibcon#ireg 11 cls_cnt 2 2006.168.07:56:28.03#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:56:28.03#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:56:28.03#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:56:28.03#ibcon#enter wrdev, iclass 35, count 2 2006.168.07:56:28.03#ibcon#first serial, iclass 35, count 2 2006.168.07:56:28.03#ibcon#enter sib2, iclass 35, count 2 2006.168.07:56:28.03#ibcon#flushed, iclass 35, count 2 2006.168.07:56:28.03#ibcon#about to write, iclass 35, count 2 2006.168.07:56:28.03#ibcon#wrote, iclass 35, count 2 2006.168.07:56:28.03#ibcon#about to read 3, iclass 35, count 2 2006.168.07:56:28.05#ibcon#read 3, iclass 35, count 2 2006.168.07:56:28.05#ibcon#about to read 4, iclass 35, count 2 2006.168.07:56:28.05#ibcon#read 4, iclass 35, count 2 2006.168.07:56:28.05#ibcon#about to read 5, iclass 35, count 2 2006.168.07:56:28.05#ibcon#read 5, iclass 35, count 2 2006.168.07:56:28.05#ibcon#about to read 6, iclass 35, count 2 2006.168.07:56:28.05#ibcon#read 6, iclass 35, count 2 2006.168.07:56:28.05#ibcon#end of sib2, iclass 35, count 2 2006.168.07:56:28.05#ibcon#*mode == 0, iclass 35, count 2 2006.168.07:56:28.05#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.168.07:56:28.05#ibcon#[25=AT01-08\r\n] 2006.168.07:56:28.05#ibcon#*before write, iclass 35, count 2 2006.168.07:56:28.05#ibcon#enter sib2, iclass 35, count 2 2006.168.07:56:28.05#ibcon#flushed, iclass 35, count 2 2006.168.07:56:28.05#ibcon#about to write, iclass 35, count 2 2006.168.07:56:28.05#ibcon#wrote, iclass 35, count 2 2006.168.07:56:28.05#ibcon#about to read 3, iclass 35, count 2 2006.168.07:56:28.08#ibcon#read 3, iclass 35, count 2 2006.168.07:56:28.08#ibcon#about to read 4, iclass 35, count 2 2006.168.07:56:28.08#ibcon#read 4, iclass 35, count 2 2006.168.07:56:28.08#ibcon#about to read 5, iclass 35, count 2 2006.168.07:56:28.08#ibcon#read 5, iclass 35, count 2 2006.168.07:56:28.08#ibcon#about to read 6, iclass 35, count 2 2006.168.07:56:28.08#ibcon#read 6, iclass 35, count 2 2006.168.07:56:28.08#ibcon#end of sib2, iclass 35, count 2 2006.168.07:56:28.08#ibcon#*after write, iclass 35, count 2 2006.168.07:56:28.08#ibcon#*before return 0, iclass 35, count 2 2006.168.07:56:28.08#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:56:28.08#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:56:28.08#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.168.07:56:28.08#ibcon#ireg 7 cls_cnt 0 2006.168.07:56:28.08#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:56:28.20#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:56:28.20#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:56:28.20#ibcon#enter wrdev, iclass 35, count 0 2006.168.07:56:28.20#ibcon#first serial, iclass 35, count 0 2006.168.07:56:28.20#ibcon#enter sib2, iclass 35, count 0 2006.168.07:56:28.20#ibcon#flushed, iclass 35, count 0 2006.168.07:56:28.20#ibcon#about to write, iclass 35, count 0 2006.168.07:56:28.20#ibcon#wrote, iclass 35, count 0 2006.168.07:56:28.20#ibcon#about to read 3, iclass 35, count 0 2006.168.07:56:28.22#ibcon#read 3, iclass 35, count 0 2006.168.07:56:28.22#ibcon#about to read 4, iclass 35, count 0 2006.168.07:56:28.22#ibcon#read 4, iclass 35, count 0 2006.168.07:56:28.22#ibcon#about to read 5, iclass 35, count 0 2006.168.07:56:28.22#ibcon#read 5, iclass 35, count 0 2006.168.07:56:28.22#ibcon#about to read 6, iclass 35, count 0 2006.168.07:56:28.22#ibcon#read 6, iclass 35, count 0 2006.168.07:56:28.22#ibcon#end of sib2, iclass 35, count 0 2006.168.07:56:28.22#ibcon#*mode == 0, iclass 35, count 0 2006.168.07:56:28.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.168.07:56:28.22#ibcon#[25=USB\r\n] 2006.168.07:56:28.22#ibcon#*before write, iclass 35, count 0 2006.168.07:56:28.22#ibcon#enter sib2, iclass 35, count 0 2006.168.07:56:28.22#ibcon#flushed, iclass 35, count 0 2006.168.07:56:28.22#ibcon#about to write, iclass 35, count 0 2006.168.07:56:28.22#ibcon#wrote, iclass 35, count 0 2006.168.07:56:28.22#ibcon#about to read 3, iclass 35, count 0 2006.168.07:56:28.25#ibcon#read 3, iclass 35, count 0 2006.168.07:56:28.25#ibcon#about to read 4, iclass 35, count 0 2006.168.07:56:28.25#ibcon#read 4, iclass 35, count 0 2006.168.07:56:28.25#ibcon#about to read 5, iclass 35, count 0 2006.168.07:56:28.25#ibcon#read 5, iclass 35, count 0 2006.168.07:56:28.25#ibcon#about to read 6, iclass 35, count 0 2006.168.07:56:28.25#ibcon#read 6, iclass 35, count 0 2006.168.07:56:28.25#ibcon#end of sib2, iclass 35, count 0 2006.168.07:56:28.25#ibcon#*after write, iclass 35, count 0 2006.168.07:56:28.25#ibcon#*before return 0, iclass 35, count 0 2006.168.07:56:28.25#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:56:28.25#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:56:28.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.168.07:56:28.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.168.07:56:28.25$vc4f8/valo=2,572.99 2006.168.07:56:28.25#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.168.07:56:28.25#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.168.07:56:28.25#ibcon#ireg 17 cls_cnt 0 2006.168.07:56:28.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:56:28.25#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:56:28.25#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:56:28.25#ibcon#enter wrdev, iclass 37, count 0 2006.168.07:56:28.25#ibcon#first serial, iclass 37, count 0 2006.168.07:56:28.25#ibcon#enter sib2, iclass 37, count 0 2006.168.07:56:28.25#ibcon#flushed, iclass 37, count 0 2006.168.07:56:28.25#ibcon#about to write, iclass 37, count 0 2006.168.07:56:28.25#ibcon#wrote, iclass 37, count 0 2006.168.07:56:28.25#ibcon#about to read 3, iclass 37, count 0 2006.168.07:56:28.27#ibcon#read 3, iclass 37, count 0 2006.168.07:56:28.27#ibcon#about to read 4, iclass 37, count 0 2006.168.07:56:28.27#ibcon#read 4, iclass 37, count 0 2006.168.07:56:28.27#ibcon#about to read 5, iclass 37, count 0 2006.168.07:56:28.27#ibcon#read 5, iclass 37, count 0 2006.168.07:56:28.27#ibcon#about to read 6, iclass 37, count 0 2006.168.07:56:28.27#ibcon#read 6, iclass 37, count 0 2006.168.07:56:28.27#ibcon#end of sib2, iclass 37, count 0 2006.168.07:56:28.27#ibcon#*mode == 0, iclass 37, count 0 2006.168.07:56:28.27#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.168.07:56:28.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.07:56:28.27#ibcon#*before write, iclass 37, count 0 2006.168.07:56:28.27#ibcon#enter sib2, iclass 37, count 0 2006.168.07:56:28.27#ibcon#flushed, iclass 37, count 0 2006.168.07:56:28.27#ibcon#about to write, iclass 37, count 0 2006.168.07:56:28.27#ibcon#wrote, iclass 37, count 0 2006.168.07:56:28.27#ibcon#about to read 3, iclass 37, count 0 2006.168.07:56:28.31#ibcon#read 3, iclass 37, count 0 2006.168.07:56:28.31#ibcon#about to read 4, iclass 37, count 0 2006.168.07:56:28.31#ibcon#read 4, iclass 37, count 0 2006.168.07:56:28.31#ibcon#about to read 5, iclass 37, count 0 2006.168.07:56:28.31#ibcon#read 5, iclass 37, count 0 2006.168.07:56:28.31#ibcon#about to read 6, iclass 37, count 0 2006.168.07:56:28.31#ibcon#read 6, iclass 37, count 0 2006.168.07:56:28.31#ibcon#end of sib2, iclass 37, count 0 2006.168.07:56:28.31#ibcon#*after write, iclass 37, count 0 2006.168.07:56:28.31#ibcon#*before return 0, iclass 37, count 0 2006.168.07:56:28.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:56:28.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:56:28.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.168.07:56:28.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.168.07:56:28.31$vc4f8/va=2,7 2006.168.07:56:28.31#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.168.07:56:28.31#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.168.07:56:28.31#ibcon#ireg 11 cls_cnt 2 2006.168.07:56:28.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:56:28.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:56:28.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:56:28.38#ibcon#enter wrdev, iclass 39, count 2 2006.168.07:56:28.38#ibcon#first serial, iclass 39, count 2 2006.168.07:56:28.38#ibcon#enter sib2, iclass 39, count 2 2006.168.07:56:28.38#ibcon#flushed, iclass 39, count 2 2006.168.07:56:28.38#ibcon#about to write, iclass 39, count 2 2006.168.07:56:28.38#ibcon#wrote, iclass 39, count 2 2006.168.07:56:28.38#ibcon#about to read 3, iclass 39, count 2 2006.168.07:56:28.40#ibcon#read 3, iclass 39, count 2 2006.168.07:56:28.40#ibcon#about to read 4, iclass 39, count 2 2006.168.07:56:28.40#ibcon#read 4, iclass 39, count 2 2006.168.07:56:28.40#ibcon#about to read 5, iclass 39, count 2 2006.168.07:56:28.40#ibcon#read 5, iclass 39, count 2 2006.168.07:56:28.40#ibcon#about to read 6, iclass 39, count 2 2006.168.07:56:28.40#ibcon#read 6, iclass 39, count 2 2006.168.07:56:28.40#ibcon#end of sib2, iclass 39, count 2 2006.168.07:56:28.40#ibcon#*mode == 0, iclass 39, count 2 2006.168.07:56:28.40#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.168.07:56:28.40#ibcon#[25=AT02-07\r\n] 2006.168.07:56:28.40#ibcon#*before write, iclass 39, count 2 2006.168.07:56:28.40#ibcon#enter sib2, iclass 39, count 2 2006.168.07:56:28.40#ibcon#flushed, iclass 39, count 2 2006.168.07:56:28.40#ibcon#about to write, iclass 39, count 2 2006.168.07:56:28.40#ibcon#wrote, iclass 39, count 2 2006.168.07:56:28.40#ibcon#about to read 3, iclass 39, count 2 2006.168.07:56:28.42#ibcon#read 3, iclass 39, count 2 2006.168.07:56:28.42#ibcon#about to read 4, iclass 39, count 2 2006.168.07:56:28.42#ibcon#read 4, iclass 39, count 2 2006.168.07:56:28.42#ibcon#about to read 5, iclass 39, count 2 2006.168.07:56:28.42#ibcon#read 5, iclass 39, count 2 2006.168.07:56:28.42#ibcon#about to read 6, iclass 39, count 2 2006.168.07:56:28.42#ibcon#read 6, iclass 39, count 2 2006.168.07:56:28.42#ibcon#end of sib2, iclass 39, count 2 2006.168.07:56:28.42#ibcon#*after write, iclass 39, count 2 2006.168.07:56:28.42#ibcon#*before return 0, iclass 39, count 2 2006.168.07:56:28.42#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:56:28.42#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:56:28.42#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.168.07:56:28.42#ibcon#ireg 7 cls_cnt 0 2006.168.07:56:28.42#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:56:28.54#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:56:28.54#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:56:28.54#ibcon#enter wrdev, iclass 39, count 0 2006.168.07:56:28.54#ibcon#first serial, iclass 39, count 0 2006.168.07:56:28.54#ibcon#enter sib2, iclass 39, count 0 2006.168.07:56:28.54#ibcon#flushed, iclass 39, count 0 2006.168.07:56:28.54#ibcon#about to write, iclass 39, count 0 2006.168.07:56:28.54#ibcon#wrote, iclass 39, count 0 2006.168.07:56:28.54#ibcon#about to read 3, iclass 39, count 0 2006.168.07:56:28.56#ibcon#read 3, iclass 39, count 0 2006.168.07:56:28.56#ibcon#about to read 4, iclass 39, count 0 2006.168.07:56:28.56#ibcon#read 4, iclass 39, count 0 2006.168.07:56:28.56#ibcon#about to read 5, iclass 39, count 0 2006.168.07:56:28.56#ibcon#read 5, iclass 39, count 0 2006.168.07:56:28.56#ibcon#about to read 6, iclass 39, count 0 2006.168.07:56:28.56#ibcon#read 6, iclass 39, count 0 2006.168.07:56:28.56#ibcon#end of sib2, iclass 39, count 0 2006.168.07:56:28.56#ibcon#*mode == 0, iclass 39, count 0 2006.168.07:56:28.56#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.168.07:56:28.56#ibcon#[25=USB\r\n] 2006.168.07:56:28.56#ibcon#*before write, iclass 39, count 0 2006.168.07:56:28.56#ibcon#enter sib2, iclass 39, count 0 2006.168.07:56:28.56#ibcon#flushed, iclass 39, count 0 2006.168.07:56:28.56#ibcon#about to write, iclass 39, count 0 2006.168.07:56:28.56#ibcon#wrote, iclass 39, count 0 2006.168.07:56:28.56#ibcon#about to read 3, iclass 39, count 0 2006.168.07:56:28.59#ibcon#read 3, iclass 39, count 0 2006.168.07:56:28.59#ibcon#about to read 4, iclass 39, count 0 2006.168.07:56:28.59#ibcon#read 4, iclass 39, count 0 2006.168.07:56:28.59#ibcon#about to read 5, iclass 39, count 0 2006.168.07:56:28.59#ibcon#read 5, iclass 39, count 0 2006.168.07:56:28.59#ibcon#about to read 6, iclass 39, count 0 2006.168.07:56:28.59#ibcon#read 6, iclass 39, count 0 2006.168.07:56:28.59#ibcon#end of sib2, iclass 39, count 0 2006.168.07:56:28.59#ibcon#*after write, iclass 39, count 0 2006.168.07:56:28.59#ibcon#*before return 0, iclass 39, count 0 2006.168.07:56:28.59#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:56:28.59#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:56:28.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.168.07:56:28.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.168.07:56:28.59$vc4f8/valo=3,672.99 2006.168.07:56:28.59#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.168.07:56:28.59#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.168.07:56:28.59#ibcon#ireg 17 cls_cnt 0 2006.168.07:56:28.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:56:28.59#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:56:28.59#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:56:28.59#ibcon#enter wrdev, iclass 3, count 0 2006.168.07:56:28.59#ibcon#first serial, iclass 3, count 0 2006.168.07:56:28.59#ibcon#enter sib2, iclass 3, count 0 2006.168.07:56:28.59#ibcon#flushed, iclass 3, count 0 2006.168.07:56:28.59#ibcon#about to write, iclass 3, count 0 2006.168.07:56:28.59#ibcon#wrote, iclass 3, count 0 2006.168.07:56:28.59#ibcon#about to read 3, iclass 3, count 0 2006.168.07:56:28.61#ibcon#read 3, iclass 3, count 0 2006.168.07:56:28.61#ibcon#about to read 4, iclass 3, count 0 2006.168.07:56:28.61#ibcon#read 4, iclass 3, count 0 2006.168.07:56:28.61#ibcon#about to read 5, iclass 3, count 0 2006.168.07:56:28.61#ibcon#read 5, iclass 3, count 0 2006.168.07:56:28.61#ibcon#about to read 6, iclass 3, count 0 2006.168.07:56:28.61#ibcon#read 6, iclass 3, count 0 2006.168.07:56:28.61#ibcon#end of sib2, iclass 3, count 0 2006.168.07:56:28.61#ibcon#*mode == 0, iclass 3, count 0 2006.168.07:56:28.61#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.168.07:56:28.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.07:56:28.61#ibcon#*before write, iclass 3, count 0 2006.168.07:56:28.61#ibcon#enter sib2, iclass 3, count 0 2006.168.07:56:28.61#ibcon#flushed, iclass 3, count 0 2006.168.07:56:28.61#ibcon#about to write, iclass 3, count 0 2006.168.07:56:28.61#ibcon#wrote, iclass 3, count 0 2006.168.07:56:28.61#ibcon#about to read 3, iclass 3, count 0 2006.168.07:56:28.65#ibcon#read 3, iclass 3, count 0 2006.168.07:56:28.65#ibcon#about to read 4, iclass 3, count 0 2006.168.07:56:28.65#ibcon#read 4, iclass 3, count 0 2006.168.07:56:28.65#ibcon#about to read 5, iclass 3, count 0 2006.168.07:56:28.65#ibcon#read 5, iclass 3, count 0 2006.168.07:56:28.65#ibcon#about to read 6, iclass 3, count 0 2006.168.07:56:28.65#ibcon#read 6, iclass 3, count 0 2006.168.07:56:28.65#ibcon#end of sib2, iclass 3, count 0 2006.168.07:56:28.65#ibcon#*after write, iclass 3, count 0 2006.168.07:56:28.65#ibcon#*before return 0, iclass 3, count 0 2006.168.07:56:28.65#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:56:28.65#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:56:28.65#ibcon#about to clear, iclass 3 cls_cnt 0 2006.168.07:56:28.65#ibcon#cleared, iclass 3 cls_cnt 0 2006.168.07:56:28.65$vc4f8/va=3,6 2006.168.07:56:28.65#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.168.07:56:28.65#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.168.07:56:28.65#ibcon#ireg 11 cls_cnt 2 2006.168.07:56:28.65#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:56:28.72#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:56:28.72#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:56:28.72#ibcon#enter wrdev, iclass 5, count 2 2006.168.07:56:28.72#ibcon#first serial, iclass 5, count 2 2006.168.07:56:28.72#ibcon#enter sib2, iclass 5, count 2 2006.168.07:56:28.72#ibcon#flushed, iclass 5, count 2 2006.168.07:56:28.72#ibcon#about to write, iclass 5, count 2 2006.168.07:56:28.72#ibcon#wrote, iclass 5, count 2 2006.168.07:56:28.72#ibcon#about to read 3, iclass 5, count 2 2006.168.07:56:28.73#ibcon#read 3, iclass 5, count 2 2006.168.07:56:28.73#ibcon#about to read 4, iclass 5, count 2 2006.168.07:56:28.73#ibcon#read 4, iclass 5, count 2 2006.168.07:56:28.74#ibcon#about to read 5, iclass 5, count 2 2006.168.07:56:28.74#ibcon#read 5, iclass 5, count 2 2006.168.07:56:28.74#ibcon#about to read 6, iclass 5, count 2 2006.168.07:56:28.74#ibcon#read 6, iclass 5, count 2 2006.168.07:56:28.74#ibcon#end of sib2, iclass 5, count 2 2006.168.07:56:28.74#ibcon#*mode == 0, iclass 5, count 2 2006.168.07:56:28.74#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.168.07:56:28.74#ibcon#[25=AT03-06\r\n] 2006.168.07:56:28.74#ibcon#*before write, iclass 5, count 2 2006.168.07:56:28.74#ibcon#enter sib2, iclass 5, count 2 2006.168.07:56:28.74#ibcon#flushed, iclass 5, count 2 2006.168.07:56:28.74#ibcon#about to write, iclass 5, count 2 2006.168.07:56:28.74#ibcon#wrote, iclass 5, count 2 2006.168.07:56:28.74#ibcon#about to read 3, iclass 5, count 2 2006.168.07:56:28.76#ibcon#read 3, iclass 5, count 2 2006.168.07:56:28.76#ibcon#about to read 4, iclass 5, count 2 2006.168.07:56:28.76#ibcon#read 4, iclass 5, count 2 2006.168.07:56:28.76#ibcon#about to read 5, iclass 5, count 2 2006.168.07:56:28.76#ibcon#read 5, iclass 5, count 2 2006.168.07:56:28.76#ibcon#about to read 6, iclass 5, count 2 2006.168.07:56:28.76#ibcon#read 6, iclass 5, count 2 2006.168.07:56:28.76#ibcon#end of sib2, iclass 5, count 2 2006.168.07:56:28.76#ibcon#*after write, iclass 5, count 2 2006.168.07:56:28.76#ibcon#*before return 0, iclass 5, count 2 2006.168.07:56:28.76#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:56:28.76#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:56:28.76#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.168.07:56:28.76#ibcon#ireg 7 cls_cnt 0 2006.168.07:56:28.76#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:56:28.88#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:56:28.88#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:56:28.88#ibcon#enter wrdev, iclass 5, count 0 2006.168.07:56:28.88#ibcon#first serial, iclass 5, count 0 2006.168.07:56:28.88#ibcon#enter sib2, iclass 5, count 0 2006.168.07:56:28.88#ibcon#flushed, iclass 5, count 0 2006.168.07:56:28.88#ibcon#about to write, iclass 5, count 0 2006.168.07:56:28.88#ibcon#wrote, iclass 5, count 0 2006.168.07:56:28.88#ibcon#about to read 3, iclass 5, count 0 2006.168.07:56:28.90#ibcon#read 3, iclass 5, count 0 2006.168.07:56:28.90#ibcon#about to read 4, iclass 5, count 0 2006.168.07:56:28.90#ibcon#read 4, iclass 5, count 0 2006.168.07:56:28.90#ibcon#about to read 5, iclass 5, count 0 2006.168.07:56:28.90#ibcon#read 5, iclass 5, count 0 2006.168.07:56:28.90#ibcon#about to read 6, iclass 5, count 0 2006.168.07:56:28.90#ibcon#read 6, iclass 5, count 0 2006.168.07:56:28.90#ibcon#end of sib2, iclass 5, count 0 2006.168.07:56:28.90#ibcon#*mode == 0, iclass 5, count 0 2006.168.07:56:28.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.168.07:56:28.90#ibcon#[25=USB\r\n] 2006.168.07:56:28.90#ibcon#*before write, iclass 5, count 0 2006.168.07:56:28.90#ibcon#enter sib2, iclass 5, count 0 2006.168.07:56:28.90#ibcon#flushed, iclass 5, count 0 2006.168.07:56:28.90#ibcon#about to write, iclass 5, count 0 2006.168.07:56:28.90#ibcon#wrote, iclass 5, count 0 2006.168.07:56:28.90#ibcon#about to read 3, iclass 5, count 0 2006.168.07:56:28.93#ibcon#read 3, iclass 5, count 0 2006.168.07:56:28.93#ibcon#about to read 4, iclass 5, count 0 2006.168.07:56:28.93#ibcon#read 4, iclass 5, count 0 2006.168.07:56:28.93#ibcon#about to read 5, iclass 5, count 0 2006.168.07:56:28.93#ibcon#read 5, iclass 5, count 0 2006.168.07:56:28.93#ibcon#about to read 6, iclass 5, count 0 2006.168.07:56:28.93#ibcon#read 6, iclass 5, count 0 2006.168.07:56:28.93#ibcon#end of sib2, iclass 5, count 0 2006.168.07:56:28.93#ibcon#*after write, iclass 5, count 0 2006.168.07:56:28.93#ibcon#*before return 0, iclass 5, count 0 2006.168.07:56:28.93#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:56:28.93#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:56:28.93#ibcon#about to clear, iclass 5 cls_cnt 0 2006.168.07:56:28.93#ibcon#cleared, iclass 5 cls_cnt 0 2006.168.07:56:28.93$vc4f8/valo=4,832.99 2006.168.07:56:28.93#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.168.07:56:28.93#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.168.07:56:28.93#ibcon#ireg 17 cls_cnt 0 2006.168.07:56:28.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:56:28.93#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:56:28.93#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:56:28.93#ibcon#enter wrdev, iclass 7, count 0 2006.168.07:56:28.93#ibcon#first serial, iclass 7, count 0 2006.168.07:56:28.93#ibcon#enter sib2, iclass 7, count 0 2006.168.07:56:28.93#ibcon#flushed, iclass 7, count 0 2006.168.07:56:28.93#ibcon#about to write, iclass 7, count 0 2006.168.07:56:28.93#ibcon#wrote, iclass 7, count 0 2006.168.07:56:28.93#ibcon#about to read 3, iclass 7, count 0 2006.168.07:56:28.95#ibcon#read 3, iclass 7, count 0 2006.168.07:56:28.95#ibcon#about to read 4, iclass 7, count 0 2006.168.07:56:28.95#ibcon#read 4, iclass 7, count 0 2006.168.07:56:28.95#ibcon#about to read 5, iclass 7, count 0 2006.168.07:56:28.95#ibcon#read 5, iclass 7, count 0 2006.168.07:56:28.95#ibcon#about to read 6, iclass 7, count 0 2006.168.07:56:28.95#ibcon#read 6, iclass 7, count 0 2006.168.07:56:28.95#ibcon#end of sib2, iclass 7, count 0 2006.168.07:56:28.95#ibcon#*mode == 0, iclass 7, count 0 2006.168.07:56:28.95#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.168.07:56:28.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.07:56:28.95#ibcon#*before write, iclass 7, count 0 2006.168.07:56:28.95#ibcon#enter sib2, iclass 7, count 0 2006.168.07:56:28.95#ibcon#flushed, iclass 7, count 0 2006.168.07:56:28.95#ibcon#about to write, iclass 7, count 0 2006.168.07:56:28.95#ibcon#wrote, iclass 7, count 0 2006.168.07:56:28.95#ibcon#about to read 3, iclass 7, count 0 2006.168.07:56:28.99#ibcon#read 3, iclass 7, count 0 2006.168.07:56:28.99#ibcon#about to read 4, iclass 7, count 0 2006.168.07:56:28.99#ibcon#read 4, iclass 7, count 0 2006.168.07:56:28.99#ibcon#about to read 5, iclass 7, count 0 2006.168.07:56:28.99#ibcon#read 5, iclass 7, count 0 2006.168.07:56:28.99#ibcon#about to read 6, iclass 7, count 0 2006.168.07:56:28.99#ibcon#read 6, iclass 7, count 0 2006.168.07:56:28.99#ibcon#end of sib2, iclass 7, count 0 2006.168.07:56:28.99#ibcon#*after write, iclass 7, count 0 2006.168.07:56:28.99#ibcon#*before return 0, iclass 7, count 0 2006.168.07:56:28.99#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:56:28.99#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:56:28.99#ibcon#about to clear, iclass 7 cls_cnt 0 2006.168.07:56:28.99#ibcon#cleared, iclass 7 cls_cnt 0 2006.168.07:56:28.99$vc4f8/va=4,7 2006.168.07:56:28.99#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.168.07:56:28.99#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.168.07:56:28.99#ibcon#ireg 11 cls_cnt 2 2006.168.07:56:28.99#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:56:29.05#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:56:29.05#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:56:29.05#ibcon#enter wrdev, iclass 11, count 2 2006.168.07:56:29.05#ibcon#first serial, iclass 11, count 2 2006.168.07:56:29.05#ibcon#enter sib2, iclass 11, count 2 2006.168.07:56:29.05#ibcon#flushed, iclass 11, count 2 2006.168.07:56:29.05#ibcon#about to write, iclass 11, count 2 2006.168.07:56:29.05#ibcon#wrote, iclass 11, count 2 2006.168.07:56:29.05#ibcon#about to read 3, iclass 11, count 2 2006.168.07:56:29.07#ibcon#read 3, iclass 11, count 2 2006.168.07:56:29.07#ibcon#about to read 4, iclass 11, count 2 2006.168.07:56:29.07#ibcon#read 4, iclass 11, count 2 2006.168.07:56:29.07#ibcon#about to read 5, iclass 11, count 2 2006.168.07:56:29.07#ibcon#read 5, iclass 11, count 2 2006.168.07:56:29.07#ibcon#about to read 6, iclass 11, count 2 2006.168.07:56:29.07#ibcon#read 6, iclass 11, count 2 2006.168.07:56:29.07#ibcon#end of sib2, iclass 11, count 2 2006.168.07:56:29.07#ibcon#*mode == 0, iclass 11, count 2 2006.168.07:56:29.07#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.168.07:56:29.07#ibcon#[25=AT04-07\r\n] 2006.168.07:56:29.07#ibcon#*before write, iclass 11, count 2 2006.168.07:56:29.07#ibcon#enter sib2, iclass 11, count 2 2006.168.07:56:29.07#ibcon#flushed, iclass 11, count 2 2006.168.07:56:29.07#ibcon#about to write, iclass 11, count 2 2006.168.07:56:29.07#ibcon#wrote, iclass 11, count 2 2006.168.07:56:29.07#ibcon#about to read 3, iclass 11, count 2 2006.168.07:56:29.10#ibcon#read 3, iclass 11, count 2 2006.168.07:56:29.10#ibcon#about to read 4, iclass 11, count 2 2006.168.07:56:29.10#ibcon#read 4, iclass 11, count 2 2006.168.07:56:29.10#ibcon#about to read 5, iclass 11, count 2 2006.168.07:56:29.10#ibcon#read 5, iclass 11, count 2 2006.168.07:56:29.10#ibcon#about to read 6, iclass 11, count 2 2006.168.07:56:29.10#ibcon#read 6, iclass 11, count 2 2006.168.07:56:29.10#ibcon#end of sib2, iclass 11, count 2 2006.168.07:56:29.10#ibcon#*after write, iclass 11, count 2 2006.168.07:56:29.10#ibcon#*before return 0, iclass 11, count 2 2006.168.07:56:29.10#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:56:29.10#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:56:29.10#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.168.07:56:29.10#ibcon#ireg 7 cls_cnt 0 2006.168.07:56:29.10#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:56:29.22#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:56:29.22#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:56:29.22#ibcon#enter wrdev, iclass 11, count 0 2006.168.07:56:29.22#ibcon#first serial, iclass 11, count 0 2006.168.07:56:29.22#ibcon#enter sib2, iclass 11, count 0 2006.168.07:56:29.22#ibcon#flushed, iclass 11, count 0 2006.168.07:56:29.22#ibcon#about to write, iclass 11, count 0 2006.168.07:56:29.22#ibcon#wrote, iclass 11, count 0 2006.168.07:56:29.22#ibcon#about to read 3, iclass 11, count 0 2006.168.07:56:29.26#ibcon#read 3, iclass 11, count 0 2006.168.07:56:29.26#ibcon#about to read 4, iclass 11, count 0 2006.168.07:56:29.26#ibcon#read 4, iclass 11, count 0 2006.168.07:56:29.26#ibcon#about to read 5, iclass 11, count 0 2006.168.07:56:29.26#ibcon#read 5, iclass 11, count 0 2006.168.07:56:29.26#ibcon#about to read 6, iclass 11, count 0 2006.168.07:56:29.26#ibcon#read 6, iclass 11, count 0 2006.168.07:56:29.26#ibcon#end of sib2, iclass 11, count 0 2006.168.07:56:29.26#ibcon#*mode == 0, iclass 11, count 0 2006.168.07:56:29.26#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.168.07:56:29.26#ibcon#[25=USB\r\n] 2006.168.07:56:29.26#ibcon#*before write, iclass 11, count 0 2006.168.07:56:29.26#ibcon#enter sib2, iclass 11, count 0 2006.168.07:56:29.26#ibcon#flushed, iclass 11, count 0 2006.168.07:56:29.26#ibcon#about to write, iclass 11, count 0 2006.168.07:56:29.26#ibcon#wrote, iclass 11, count 0 2006.168.07:56:29.26#ibcon#about to read 3, iclass 11, count 0 2006.168.07:56:29.29#ibcon#read 3, iclass 11, count 0 2006.168.07:56:29.29#ibcon#about to read 4, iclass 11, count 0 2006.168.07:56:29.29#ibcon#read 4, iclass 11, count 0 2006.168.07:56:29.29#ibcon#about to read 5, iclass 11, count 0 2006.168.07:56:29.29#ibcon#read 5, iclass 11, count 0 2006.168.07:56:29.29#ibcon#about to read 6, iclass 11, count 0 2006.168.07:56:29.29#ibcon#read 6, iclass 11, count 0 2006.168.07:56:29.29#ibcon#end of sib2, iclass 11, count 0 2006.168.07:56:29.29#ibcon#*after write, iclass 11, count 0 2006.168.07:56:29.29#ibcon#*before return 0, iclass 11, count 0 2006.168.07:56:29.29#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:56:29.29#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:56:29.29#ibcon#about to clear, iclass 11 cls_cnt 0 2006.168.07:56:29.29#ibcon#cleared, iclass 11 cls_cnt 0 2006.168.07:56:29.29$vc4f8/valo=5,652.99 2006.168.07:56:29.29#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.168.07:56:29.29#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.168.07:56:29.29#ibcon#ireg 17 cls_cnt 0 2006.168.07:56:29.29#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:56:29.29#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:56:29.29#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:56:29.29#ibcon#enter wrdev, iclass 13, count 0 2006.168.07:56:29.29#ibcon#first serial, iclass 13, count 0 2006.168.07:56:29.29#ibcon#enter sib2, iclass 13, count 0 2006.168.07:56:29.29#ibcon#flushed, iclass 13, count 0 2006.168.07:56:29.29#ibcon#about to write, iclass 13, count 0 2006.168.07:56:29.29#ibcon#wrote, iclass 13, count 0 2006.168.07:56:29.29#ibcon#about to read 3, iclass 13, count 0 2006.168.07:56:29.32#ibcon#read 3, iclass 13, count 0 2006.168.07:56:29.32#ibcon#about to read 4, iclass 13, count 0 2006.168.07:56:29.32#ibcon#read 4, iclass 13, count 0 2006.168.07:56:29.32#ibcon#about to read 5, iclass 13, count 0 2006.168.07:56:29.32#ibcon#read 5, iclass 13, count 0 2006.168.07:56:29.32#ibcon#about to read 6, iclass 13, count 0 2006.168.07:56:29.32#ibcon#read 6, iclass 13, count 0 2006.168.07:56:29.32#ibcon#end of sib2, iclass 13, count 0 2006.168.07:56:29.32#ibcon#*mode == 0, iclass 13, count 0 2006.168.07:56:29.32#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.168.07:56:29.32#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.07:56:29.32#ibcon#*before write, iclass 13, count 0 2006.168.07:56:29.32#ibcon#enter sib2, iclass 13, count 0 2006.168.07:56:29.32#ibcon#flushed, iclass 13, count 0 2006.168.07:56:29.32#ibcon#about to write, iclass 13, count 0 2006.168.07:56:29.32#ibcon#wrote, iclass 13, count 0 2006.168.07:56:29.32#ibcon#about to read 3, iclass 13, count 0 2006.168.07:56:29.36#ibcon#read 3, iclass 13, count 0 2006.168.07:56:29.36#ibcon#about to read 4, iclass 13, count 0 2006.168.07:56:29.36#ibcon#read 4, iclass 13, count 0 2006.168.07:56:29.36#ibcon#about to read 5, iclass 13, count 0 2006.168.07:56:29.36#ibcon#read 5, iclass 13, count 0 2006.168.07:56:29.36#ibcon#about to read 6, iclass 13, count 0 2006.168.07:56:29.36#ibcon#read 6, iclass 13, count 0 2006.168.07:56:29.36#ibcon#end of sib2, iclass 13, count 0 2006.168.07:56:29.36#ibcon#*after write, iclass 13, count 0 2006.168.07:56:29.36#ibcon#*before return 0, iclass 13, count 0 2006.168.07:56:29.36#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:56:29.36#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:56:29.36#ibcon#about to clear, iclass 13 cls_cnt 0 2006.168.07:56:29.36#ibcon#cleared, iclass 13 cls_cnt 0 2006.168.07:56:29.36$vc4f8/va=5,7 2006.168.07:56:29.36#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.168.07:56:29.36#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.168.07:56:29.36#ibcon#ireg 11 cls_cnt 2 2006.168.07:56:29.36#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.168.07:56:29.40#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.168.07:56:29.40#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.168.07:56:29.40#ibcon#enter wrdev, iclass 15, count 2 2006.168.07:56:29.40#ibcon#first serial, iclass 15, count 2 2006.168.07:56:29.40#ibcon#enter sib2, iclass 15, count 2 2006.168.07:56:29.40#ibcon#flushed, iclass 15, count 2 2006.168.07:56:29.40#ibcon#about to write, iclass 15, count 2 2006.168.07:56:29.40#ibcon#wrote, iclass 15, count 2 2006.168.07:56:29.40#ibcon#about to read 3, iclass 15, count 2 2006.168.07:56:29.42#ibcon#read 3, iclass 15, count 2 2006.168.07:56:29.42#ibcon#about to read 4, iclass 15, count 2 2006.168.07:56:29.42#ibcon#read 4, iclass 15, count 2 2006.168.07:56:29.42#ibcon#about to read 5, iclass 15, count 2 2006.168.07:56:29.42#ibcon#read 5, iclass 15, count 2 2006.168.07:56:29.42#ibcon#about to read 6, iclass 15, count 2 2006.168.07:56:29.42#ibcon#read 6, iclass 15, count 2 2006.168.07:56:29.42#ibcon#end of sib2, iclass 15, count 2 2006.168.07:56:29.42#ibcon#*mode == 0, iclass 15, count 2 2006.168.07:56:29.42#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.168.07:56:29.42#ibcon#[25=AT05-07\r\n] 2006.168.07:56:29.42#ibcon#*before write, iclass 15, count 2 2006.168.07:56:29.42#ibcon#enter sib2, iclass 15, count 2 2006.168.07:56:29.42#ibcon#flushed, iclass 15, count 2 2006.168.07:56:29.42#ibcon#about to write, iclass 15, count 2 2006.168.07:56:29.42#ibcon#wrote, iclass 15, count 2 2006.168.07:56:29.42#ibcon#about to read 3, iclass 15, count 2 2006.168.07:56:29.45#ibcon#read 3, iclass 15, count 2 2006.168.07:56:29.45#ibcon#about to read 4, iclass 15, count 2 2006.168.07:56:29.45#ibcon#read 4, iclass 15, count 2 2006.168.07:56:29.45#ibcon#about to read 5, iclass 15, count 2 2006.168.07:56:29.45#ibcon#read 5, iclass 15, count 2 2006.168.07:56:29.45#ibcon#about to read 6, iclass 15, count 2 2006.168.07:56:29.45#ibcon#read 6, iclass 15, count 2 2006.168.07:56:29.45#ibcon#end of sib2, iclass 15, count 2 2006.168.07:56:29.45#ibcon#*after write, iclass 15, count 2 2006.168.07:56:29.45#ibcon#*before return 0, iclass 15, count 2 2006.168.07:56:29.45#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.168.07:56:29.45#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.168.07:56:29.45#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.168.07:56:29.45#ibcon#ireg 7 cls_cnt 0 2006.168.07:56:29.45#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.168.07:56:29.57#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.168.07:56:29.57#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.168.07:56:29.57#ibcon#enter wrdev, iclass 15, count 0 2006.168.07:56:29.57#ibcon#first serial, iclass 15, count 0 2006.168.07:56:29.57#ibcon#enter sib2, iclass 15, count 0 2006.168.07:56:29.57#ibcon#flushed, iclass 15, count 0 2006.168.07:56:29.57#ibcon#about to write, iclass 15, count 0 2006.168.07:56:29.57#ibcon#wrote, iclass 15, count 0 2006.168.07:56:29.57#ibcon#about to read 3, iclass 15, count 0 2006.168.07:56:29.59#ibcon#read 3, iclass 15, count 0 2006.168.07:56:29.59#ibcon#about to read 4, iclass 15, count 0 2006.168.07:56:29.59#ibcon#read 4, iclass 15, count 0 2006.168.07:56:29.59#ibcon#about to read 5, iclass 15, count 0 2006.168.07:56:29.59#ibcon#read 5, iclass 15, count 0 2006.168.07:56:29.59#ibcon#about to read 6, iclass 15, count 0 2006.168.07:56:29.59#ibcon#read 6, iclass 15, count 0 2006.168.07:56:29.59#ibcon#end of sib2, iclass 15, count 0 2006.168.07:56:29.59#ibcon#*mode == 0, iclass 15, count 0 2006.168.07:56:29.59#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.168.07:56:29.59#ibcon#[25=USB\r\n] 2006.168.07:56:29.59#ibcon#*before write, iclass 15, count 0 2006.168.07:56:29.59#ibcon#enter sib2, iclass 15, count 0 2006.168.07:56:29.59#ibcon#flushed, iclass 15, count 0 2006.168.07:56:29.59#ibcon#about to write, iclass 15, count 0 2006.168.07:56:29.59#ibcon#wrote, iclass 15, count 0 2006.168.07:56:29.59#ibcon#about to read 3, iclass 15, count 0 2006.168.07:56:29.62#ibcon#read 3, iclass 15, count 0 2006.168.07:56:29.62#ibcon#about to read 4, iclass 15, count 0 2006.168.07:56:29.62#ibcon#read 4, iclass 15, count 0 2006.168.07:56:29.62#ibcon#about to read 5, iclass 15, count 0 2006.168.07:56:29.62#ibcon#read 5, iclass 15, count 0 2006.168.07:56:29.62#ibcon#about to read 6, iclass 15, count 0 2006.168.07:56:29.62#ibcon#read 6, iclass 15, count 0 2006.168.07:56:29.62#ibcon#end of sib2, iclass 15, count 0 2006.168.07:56:29.62#ibcon#*after write, iclass 15, count 0 2006.168.07:56:29.62#ibcon#*before return 0, iclass 15, count 0 2006.168.07:56:29.62#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.168.07:56:29.62#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.168.07:56:29.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.168.07:56:29.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.168.07:56:29.62$vc4f8/valo=6,772.99 2006.168.07:56:29.62#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.168.07:56:29.62#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.168.07:56:29.62#ibcon#ireg 17 cls_cnt 0 2006.168.07:56:29.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:56:29.62#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:56:29.62#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:56:29.62#ibcon#enter wrdev, iclass 17, count 0 2006.168.07:56:29.62#ibcon#first serial, iclass 17, count 0 2006.168.07:56:29.62#ibcon#enter sib2, iclass 17, count 0 2006.168.07:56:29.62#ibcon#flushed, iclass 17, count 0 2006.168.07:56:29.62#ibcon#about to write, iclass 17, count 0 2006.168.07:56:29.62#ibcon#wrote, iclass 17, count 0 2006.168.07:56:29.62#ibcon#about to read 3, iclass 17, count 0 2006.168.07:56:29.64#ibcon#read 3, iclass 17, count 0 2006.168.07:56:29.64#ibcon#about to read 4, iclass 17, count 0 2006.168.07:56:29.64#ibcon#read 4, iclass 17, count 0 2006.168.07:56:29.64#ibcon#about to read 5, iclass 17, count 0 2006.168.07:56:29.64#ibcon#read 5, iclass 17, count 0 2006.168.07:56:29.64#ibcon#about to read 6, iclass 17, count 0 2006.168.07:56:29.64#ibcon#read 6, iclass 17, count 0 2006.168.07:56:29.64#ibcon#end of sib2, iclass 17, count 0 2006.168.07:56:29.64#ibcon#*mode == 0, iclass 17, count 0 2006.168.07:56:29.64#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.168.07:56:29.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.07:56:29.64#ibcon#*before write, iclass 17, count 0 2006.168.07:56:29.64#ibcon#enter sib2, iclass 17, count 0 2006.168.07:56:29.64#ibcon#flushed, iclass 17, count 0 2006.168.07:56:29.64#ibcon#about to write, iclass 17, count 0 2006.168.07:56:29.64#ibcon#wrote, iclass 17, count 0 2006.168.07:56:29.64#ibcon#about to read 3, iclass 17, count 0 2006.168.07:56:29.68#ibcon#read 3, iclass 17, count 0 2006.168.07:56:29.68#ibcon#about to read 4, iclass 17, count 0 2006.168.07:56:29.68#ibcon#read 4, iclass 17, count 0 2006.168.07:56:29.68#ibcon#about to read 5, iclass 17, count 0 2006.168.07:56:29.68#ibcon#read 5, iclass 17, count 0 2006.168.07:56:29.68#ibcon#about to read 6, iclass 17, count 0 2006.168.07:56:29.68#ibcon#read 6, iclass 17, count 0 2006.168.07:56:29.68#ibcon#end of sib2, iclass 17, count 0 2006.168.07:56:29.68#ibcon#*after write, iclass 17, count 0 2006.168.07:56:29.68#ibcon#*before return 0, iclass 17, count 0 2006.168.07:56:29.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:56:29.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:56:29.68#ibcon#about to clear, iclass 17 cls_cnt 0 2006.168.07:56:29.68#ibcon#cleared, iclass 17 cls_cnt 0 2006.168.07:56:29.68$vc4f8/va=6,6 2006.168.07:56:29.68#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.168.07:56:29.68#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.168.07:56:29.68#ibcon#ireg 11 cls_cnt 2 2006.168.07:56:29.68#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.168.07:56:29.74#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.168.07:56:29.74#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.168.07:56:29.74#ibcon#enter wrdev, iclass 19, count 2 2006.168.07:56:29.74#ibcon#first serial, iclass 19, count 2 2006.168.07:56:29.74#ibcon#enter sib2, iclass 19, count 2 2006.168.07:56:29.74#ibcon#flushed, iclass 19, count 2 2006.168.07:56:29.74#ibcon#about to write, iclass 19, count 2 2006.168.07:56:29.74#ibcon#wrote, iclass 19, count 2 2006.168.07:56:29.74#ibcon#about to read 3, iclass 19, count 2 2006.168.07:56:29.76#ibcon#read 3, iclass 19, count 2 2006.168.07:56:29.76#ibcon#about to read 4, iclass 19, count 2 2006.168.07:56:29.76#ibcon#read 4, iclass 19, count 2 2006.168.07:56:29.76#ibcon#about to read 5, iclass 19, count 2 2006.168.07:56:29.76#ibcon#read 5, iclass 19, count 2 2006.168.07:56:29.76#ibcon#about to read 6, iclass 19, count 2 2006.168.07:56:29.76#ibcon#read 6, iclass 19, count 2 2006.168.07:56:29.76#ibcon#end of sib2, iclass 19, count 2 2006.168.07:56:29.76#ibcon#*mode == 0, iclass 19, count 2 2006.168.07:56:29.76#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.168.07:56:29.76#ibcon#[25=AT06-06\r\n] 2006.168.07:56:29.76#ibcon#*before write, iclass 19, count 2 2006.168.07:56:29.76#ibcon#enter sib2, iclass 19, count 2 2006.168.07:56:29.76#ibcon#flushed, iclass 19, count 2 2006.168.07:56:29.76#ibcon#about to write, iclass 19, count 2 2006.168.07:56:29.76#ibcon#wrote, iclass 19, count 2 2006.168.07:56:29.76#ibcon#about to read 3, iclass 19, count 2 2006.168.07:56:29.79#ibcon#read 3, iclass 19, count 2 2006.168.07:56:29.79#ibcon#about to read 4, iclass 19, count 2 2006.168.07:56:29.79#ibcon#read 4, iclass 19, count 2 2006.168.07:56:29.79#ibcon#about to read 5, iclass 19, count 2 2006.168.07:56:29.79#ibcon#read 5, iclass 19, count 2 2006.168.07:56:29.79#ibcon#about to read 6, iclass 19, count 2 2006.168.07:56:29.79#ibcon#read 6, iclass 19, count 2 2006.168.07:56:29.79#ibcon#end of sib2, iclass 19, count 2 2006.168.07:56:29.79#ibcon#*after write, iclass 19, count 2 2006.168.07:56:29.79#ibcon#*before return 0, iclass 19, count 2 2006.168.07:56:29.79#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.168.07:56:29.79#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.168.07:56:29.79#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.168.07:56:29.79#ibcon#ireg 7 cls_cnt 0 2006.168.07:56:29.79#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.168.07:56:29.91#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.168.07:56:29.91#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.168.07:56:29.91#ibcon#enter wrdev, iclass 19, count 0 2006.168.07:56:29.91#ibcon#first serial, iclass 19, count 0 2006.168.07:56:29.91#ibcon#enter sib2, iclass 19, count 0 2006.168.07:56:29.91#ibcon#flushed, iclass 19, count 0 2006.168.07:56:29.91#ibcon#about to write, iclass 19, count 0 2006.168.07:56:29.91#ibcon#wrote, iclass 19, count 0 2006.168.07:56:29.91#ibcon#about to read 3, iclass 19, count 0 2006.168.07:56:29.93#ibcon#read 3, iclass 19, count 0 2006.168.07:56:29.93#ibcon#about to read 4, iclass 19, count 0 2006.168.07:56:29.93#ibcon#read 4, iclass 19, count 0 2006.168.07:56:29.93#ibcon#about to read 5, iclass 19, count 0 2006.168.07:56:29.93#ibcon#read 5, iclass 19, count 0 2006.168.07:56:29.93#ibcon#about to read 6, iclass 19, count 0 2006.168.07:56:29.93#ibcon#read 6, iclass 19, count 0 2006.168.07:56:29.93#ibcon#end of sib2, iclass 19, count 0 2006.168.07:56:29.93#ibcon#*mode == 0, iclass 19, count 0 2006.168.07:56:29.93#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.168.07:56:29.93#ibcon#[25=USB\r\n] 2006.168.07:56:29.93#ibcon#*before write, iclass 19, count 0 2006.168.07:56:29.93#ibcon#enter sib2, iclass 19, count 0 2006.168.07:56:29.93#ibcon#flushed, iclass 19, count 0 2006.168.07:56:29.93#ibcon#about to write, iclass 19, count 0 2006.168.07:56:29.93#ibcon#wrote, iclass 19, count 0 2006.168.07:56:29.93#ibcon#about to read 3, iclass 19, count 0 2006.168.07:56:29.96#ibcon#read 3, iclass 19, count 0 2006.168.07:56:29.96#ibcon#about to read 4, iclass 19, count 0 2006.168.07:56:29.96#ibcon#read 4, iclass 19, count 0 2006.168.07:56:29.96#ibcon#about to read 5, iclass 19, count 0 2006.168.07:56:29.96#ibcon#read 5, iclass 19, count 0 2006.168.07:56:29.96#ibcon#about to read 6, iclass 19, count 0 2006.168.07:56:29.96#ibcon#read 6, iclass 19, count 0 2006.168.07:56:29.96#ibcon#end of sib2, iclass 19, count 0 2006.168.07:56:29.96#ibcon#*after write, iclass 19, count 0 2006.168.07:56:29.96#ibcon#*before return 0, iclass 19, count 0 2006.168.07:56:29.96#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.168.07:56:29.96#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.168.07:56:29.96#ibcon#about to clear, iclass 19 cls_cnt 0 2006.168.07:56:29.96#ibcon#cleared, iclass 19 cls_cnt 0 2006.168.07:56:29.96$vc4f8/valo=7,832.99 2006.168.07:56:29.96#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.168.07:56:29.96#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.168.07:56:29.96#ibcon#ireg 17 cls_cnt 0 2006.168.07:56:29.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.168.07:56:29.96#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.168.07:56:29.96#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.168.07:56:29.96#ibcon#enter wrdev, iclass 21, count 0 2006.168.07:56:29.96#ibcon#first serial, iclass 21, count 0 2006.168.07:56:29.96#ibcon#enter sib2, iclass 21, count 0 2006.168.07:56:29.96#ibcon#flushed, iclass 21, count 0 2006.168.07:56:29.96#ibcon#about to write, iclass 21, count 0 2006.168.07:56:29.96#ibcon#wrote, iclass 21, count 0 2006.168.07:56:29.96#ibcon#about to read 3, iclass 21, count 0 2006.168.07:56:29.98#ibcon#read 3, iclass 21, count 0 2006.168.07:56:29.98#ibcon#about to read 4, iclass 21, count 0 2006.168.07:56:29.98#ibcon#read 4, iclass 21, count 0 2006.168.07:56:29.98#ibcon#about to read 5, iclass 21, count 0 2006.168.07:56:29.98#ibcon#read 5, iclass 21, count 0 2006.168.07:56:29.98#ibcon#about to read 6, iclass 21, count 0 2006.168.07:56:29.98#ibcon#read 6, iclass 21, count 0 2006.168.07:56:29.98#ibcon#end of sib2, iclass 21, count 0 2006.168.07:56:29.98#ibcon#*mode == 0, iclass 21, count 0 2006.168.07:56:29.98#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.168.07:56:29.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.07:56:29.98#ibcon#*before write, iclass 21, count 0 2006.168.07:56:29.98#ibcon#enter sib2, iclass 21, count 0 2006.168.07:56:29.98#ibcon#flushed, iclass 21, count 0 2006.168.07:56:29.98#ibcon#about to write, iclass 21, count 0 2006.168.07:56:29.98#ibcon#wrote, iclass 21, count 0 2006.168.07:56:29.98#ibcon#about to read 3, iclass 21, count 0 2006.168.07:56:30.02#ibcon#read 3, iclass 21, count 0 2006.168.07:56:30.02#ibcon#about to read 4, iclass 21, count 0 2006.168.07:56:30.02#ibcon#read 4, iclass 21, count 0 2006.168.07:56:30.02#ibcon#about to read 5, iclass 21, count 0 2006.168.07:56:30.02#ibcon#read 5, iclass 21, count 0 2006.168.07:56:30.02#ibcon#about to read 6, iclass 21, count 0 2006.168.07:56:30.02#ibcon#read 6, iclass 21, count 0 2006.168.07:56:30.02#ibcon#end of sib2, iclass 21, count 0 2006.168.07:56:30.02#ibcon#*after write, iclass 21, count 0 2006.168.07:56:30.02#ibcon#*before return 0, iclass 21, count 0 2006.168.07:56:30.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.168.07:56:30.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.168.07:56:30.02#ibcon#about to clear, iclass 21 cls_cnt 0 2006.168.07:56:30.02#ibcon#cleared, iclass 21 cls_cnt 0 2006.168.07:56:30.02$vc4f8/va=7,6 2006.168.07:56:30.02#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.168.07:56:30.02#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.168.07:56:30.02#ibcon#ireg 11 cls_cnt 2 2006.168.07:56:30.02#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.168.07:56:30.09#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.168.07:56:30.09#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.168.07:56:30.09#ibcon#enter wrdev, iclass 23, count 2 2006.168.07:56:30.09#ibcon#first serial, iclass 23, count 2 2006.168.07:56:30.09#ibcon#enter sib2, iclass 23, count 2 2006.168.07:56:30.09#ibcon#flushed, iclass 23, count 2 2006.168.07:56:30.09#ibcon#about to write, iclass 23, count 2 2006.168.07:56:30.09#ibcon#wrote, iclass 23, count 2 2006.168.07:56:30.09#ibcon#about to read 3, iclass 23, count 2 2006.168.07:56:30.11#ibcon#read 3, iclass 23, count 2 2006.168.07:56:30.11#ibcon#about to read 4, iclass 23, count 2 2006.168.07:56:30.11#ibcon#read 4, iclass 23, count 2 2006.168.07:56:30.11#ibcon#about to read 5, iclass 23, count 2 2006.168.07:56:30.11#ibcon#read 5, iclass 23, count 2 2006.168.07:56:30.11#ibcon#about to read 6, iclass 23, count 2 2006.168.07:56:30.11#ibcon#read 6, iclass 23, count 2 2006.168.07:56:30.11#ibcon#end of sib2, iclass 23, count 2 2006.168.07:56:30.11#ibcon#*mode == 0, iclass 23, count 2 2006.168.07:56:30.11#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.168.07:56:30.11#ibcon#[25=AT07-06\r\n] 2006.168.07:56:30.11#ibcon#*before write, iclass 23, count 2 2006.168.07:56:30.11#ibcon#enter sib2, iclass 23, count 2 2006.168.07:56:30.11#ibcon#flushed, iclass 23, count 2 2006.168.07:56:30.11#ibcon#about to write, iclass 23, count 2 2006.168.07:56:30.11#ibcon#wrote, iclass 23, count 2 2006.168.07:56:30.11#ibcon#about to read 3, iclass 23, count 2 2006.168.07:56:30.13#ibcon#read 3, iclass 23, count 2 2006.168.07:56:30.13#ibcon#about to read 4, iclass 23, count 2 2006.168.07:56:30.13#ibcon#read 4, iclass 23, count 2 2006.168.07:56:30.13#ibcon#about to read 5, iclass 23, count 2 2006.168.07:56:30.13#ibcon#read 5, iclass 23, count 2 2006.168.07:56:30.13#ibcon#about to read 6, iclass 23, count 2 2006.168.07:56:30.13#ibcon#read 6, iclass 23, count 2 2006.168.07:56:30.13#ibcon#end of sib2, iclass 23, count 2 2006.168.07:56:30.13#ibcon#*after write, iclass 23, count 2 2006.168.07:56:30.13#ibcon#*before return 0, iclass 23, count 2 2006.168.07:56:30.13#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.168.07:56:30.13#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.168.07:56:30.13#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.168.07:56:30.13#ibcon#ireg 7 cls_cnt 0 2006.168.07:56:30.13#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.168.07:56:30.25#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.168.07:56:30.25#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.168.07:56:30.25#ibcon#enter wrdev, iclass 23, count 0 2006.168.07:56:30.25#ibcon#first serial, iclass 23, count 0 2006.168.07:56:30.25#ibcon#enter sib2, iclass 23, count 0 2006.168.07:56:30.25#ibcon#flushed, iclass 23, count 0 2006.168.07:56:30.25#ibcon#about to write, iclass 23, count 0 2006.168.07:56:30.25#ibcon#wrote, iclass 23, count 0 2006.168.07:56:30.25#ibcon#about to read 3, iclass 23, count 0 2006.168.07:56:30.27#ibcon#read 3, iclass 23, count 0 2006.168.07:56:30.27#ibcon#about to read 4, iclass 23, count 0 2006.168.07:56:30.27#ibcon#read 4, iclass 23, count 0 2006.168.07:56:30.27#ibcon#about to read 5, iclass 23, count 0 2006.168.07:56:30.27#ibcon#read 5, iclass 23, count 0 2006.168.07:56:30.27#ibcon#about to read 6, iclass 23, count 0 2006.168.07:56:30.27#ibcon#read 6, iclass 23, count 0 2006.168.07:56:30.27#ibcon#end of sib2, iclass 23, count 0 2006.168.07:56:30.27#ibcon#*mode == 0, iclass 23, count 0 2006.168.07:56:30.27#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.168.07:56:30.27#ibcon#[25=USB\r\n] 2006.168.07:56:30.27#ibcon#*before write, iclass 23, count 0 2006.168.07:56:30.27#ibcon#enter sib2, iclass 23, count 0 2006.168.07:56:30.27#ibcon#flushed, iclass 23, count 0 2006.168.07:56:30.27#ibcon#about to write, iclass 23, count 0 2006.168.07:56:30.27#ibcon#wrote, iclass 23, count 0 2006.168.07:56:30.27#ibcon#about to read 3, iclass 23, count 0 2006.168.07:56:30.30#ibcon#read 3, iclass 23, count 0 2006.168.07:56:30.30#ibcon#about to read 4, iclass 23, count 0 2006.168.07:56:30.30#ibcon#read 4, iclass 23, count 0 2006.168.07:56:30.30#ibcon#about to read 5, iclass 23, count 0 2006.168.07:56:30.30#ibcon#read 5, iclass 23, count 0 2006.168.07:56:30.30#ibcon#about to read 6, iclass 23, count 0 2006.168.07:56:30.30#ibcon#read 6, iclass 23, count 0 2006.168.07:56:30.30#ibcon#end of sib2, iclass 23, count 0 2006.168.07:56:30.30#ibcon#*after write, iclass 23, count 0 2006.168.07:56:30.30#ibcon#*before return 0, iclass 23, count 0 2006.168.07:56:30.30#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.168.07:56:30.30#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.168.07:56:30.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.168.07:56:30.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.168.07:56:30.30$vc4f8/valo=8,852.99 2006.168.07:56:30.30#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.168.07:56:30.30#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.168.07:56:30.30#ibcon#ireg 17 cls_cnt 0 2006.168.07:56:30.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.168.07:56:30.30#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.168.07:56:30.30#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.168.07:56:30.30#ibcon#enter wrdev, iclass 25, count 0 2006.168.07:56:30.30#ibcon#first serial, iclass 25, count 0 2006.168.07:56:30.30#ibcon#enter sib2, iclass 25, count 0 2006.168.07:56:30.30#ibcon#flushed, iclass 25, count 0 2006.168.07:56:30.30#ibcon#about to write, iclass 25, count 0 2006.168.07:56:30.30#ibcon#wrote, iclass 25, count 0 2006.168.07:56:30.30#ibcon#about to read 3, iclass 25, count 0 2006.168.07:56:30.32#ibcon#read 3, iclass 25, count 0 2006.168.07:56:30.32#ibcon#about to read 4, iclass 25, count 0 2006.168.07:56:30.32#ibcon#read 4, iclass 25, count 0 2006.168.07:56:30.32#ibcon#about to read 5, iclass 25, count 0 2006.168.07:56:30.32#ibcon#read 5, iclass 25, count 0 2006.168.07:56:30.32#ibcon#about to read 6, iclass 25, count 0 2006.168.07:56:30.32#ibcon#read 6, iclass 25, count 0 2006.168.07:56:30.32#ibcon#end of sib2, iclass 25, count 0 2006.168.07:56:30.32#ibcon#*mode == 0, iclass 25, count 0 2006.168.07:56:30.32#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.168.07:56:30.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.07:56:30.32#ibcon#*before write, iclass 25, count 0 2006.168.07:56:30.32#ibcon#enter sib2, iclass 25, count 0 2006.168.07:56:30.32#ibcon#flushed, iclass 25, count 0 2006.168.07:56:30.32#ibcon#about to write, iclass 25, count 0 2006.168.07:56:30.32#ibcon#wrote, iclass 25, count 0 2006.168.07:56:30.32#ibcon#about to read 3, iclass 25, count 0 2006.168.07:56:30.36#ibcon#read 3, iclass 25, count 0 2006.168.07:56:30.36#ibcon#about to read 4, iclass 25, count 0 2006.168.07:56:30.36#ibcon#read 4, iclass 25, count 0 2006.168.07:56:30.36#ibcon#about to read 5, iclass 25, count 0 2006.168.07:56:30.36#ibcon#read 5, iclass 25, count 0 2006.168.07:56:30.36#ibcon#about to read 6, iclass 25, count 0 2006.168.07:56:30.36#ibcon#read 6, iclass 25, count 0 2006.168.07:56:30.36#ibcon#end of sib2, iclass 25, count 0 2006.168.07:56:30.36#ibcon#*after write, iclass 25, count 0 2006.168.07:56:30.36#ibcon#*before return 0, iclass 25, count 0 2006.168.07:56:30.36#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.168.07:56:30.36#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.168.07:56:30.36#ibcon#about to clear, iclass 25 cls_cnt 0 2006.168.07:56:30.36#ibcon#cleared, iclass 25 cls_cnt 0 2006.168.07:56:30.36$vc4f8/va=8,7 2006.168.07:56:30.36#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.168.07:56:30.36#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.168.07:56:30.36#ibcon#ireg 11 cls_cnt 2 2006.168.07:56:30.36#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.168.07:56:30.42#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.168.07:56:30.42#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.168.07:56:30.42#ibcon#enter wrdev, iclass 27, count 2 2006.168.07:56:30.42#ibcon#first serial, iclass 27, count 2 2006.168.07:56:30.42#ibcon#enter sib2, iclass 27, count 2 2006.168.07:56:30.42#ibcon#flushed, iclass 27, count 2 2006.168.07:56:30.42#ibcon#about to write, iclass 27, count 2 2006.168.07:56:30.42#ibcon#wrote, iclass 27, count 2 2006.168.07:56:30.42#ibcon#about to read 3, iclass 27, count 2 2006.168.07:56:30.44#ibcon#read 3, iclass 27, count 2 2006.168.07:56:30.44#ibcon#about to read 4, iclass 27, count 2 2006.168.07:56:30.44#ibcon#read 4, iclass 27, count 2 2006.168.07:56:30.44#ibcon#about to read 5, iclass 27, count 2 2006.168.07:56:30.44#ibcon#read 5, iclass 27, count 2 2006.168.07:56:30.44#ibcon#about to read 6, iclass 27, count 2 2006.168.07:56:30.44#ibcon#read 6, iclass 27, count 2 2006.168.07:56:30.44#ibcon#end of sib2, iclass 27, count 2 2006.168.07:56:30.44#ibcon#*mode == 0, iclass 27, count 2 2006.168.07:56:30.44#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.168.07:56:30.44#ibcon#[25=AT08-07\r\n] 2006.168.07:56:30.44#ibcon#*before write, iclass 27, count 2 2006.168.07:56:30.44#ibcon#enter sib2, iclass 27, count 2 2006.168.07:56:30.44#ibcon#flushed, iclass 27, count 2 2006.168.07:56:30.44#ibcon#about to write, iclass 27, count 2 2006.168.07:56:30.44#ibcon#wrote, iclass 27, count 2 2006.168.07:56:30.44#ibcon#about to read 3, iclass 27, count 2 2006.168.07:56:30.47#ibcon#read 3, iclass 27, count 2 2006.168.07:56:30.47#ibcon#about to read 4, iclass 27, count 2 2006.168.07:56:30.47#ibcon#read 4, iclass 27, count 2 2006.168.07:56:30.47#ibcon#about to read 5, iclass 27, count 2 2006.168.07:56:30.47#ibcon#read 5, iclass 27, count 2 2006.168.07:56:30.47#ibcon#about to read 6, iclass 27, count 2 2006.168.07:56:30.47#ibcon#read 6, iclass 27, count 2 2006.168.07:56:30.47#ibcon#end of sib2, iclass 27, count 2 2006.168.07:56:30.47#ibcon#*after write, iclass 27, count 2 2006.168.07:56:30.47#ibcon#*before return 0, iclass 27, count 2 2006.168.07:56:30.47#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.168.07:56:30.47#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.168.07:56:30.47#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.168.07:56:30.47#ibcon#ireg 7 cls_cnt 0 2006.168.07:56:30.47#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.168.07:56:30.59#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.168.07:56:30.59#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.168.07:56:30.59#ibcon#enter wrdev, iclass 27, count 0 2006.168.07:56:30.59#ibcon#first serial, iclass 27, count 0 2006.168.07:56:30.59#ibcon#enter sib2, iclass 27, count 0 2006.168.07:56:30.59#ibcon#flushed, iclass 27, count 0 2006.168.07:56:30.59#ibcon#about to write, iclass 27, count 0 2006.168.07:56:30.59#ibcon#wrote, iclass 27, count 0 2006.168.07:56:30.59#ibcon#about to read 3, iclass 27, count 0 2006.168.07:56:30.61#ibcon#read 3, iclass 27, count 0 2006.168.07:56:30.61#ibcon#about to read 4, iclass 27, count 0 2006.168.07:56:30.61#ibcon#read 4, iclass 27, count 0 2006.168.07:56:30.61#ibcon#about to read 5, iclass 27, count 0 2006.168.07:56:30.61#ibcon#read 5, iclass 27, count 0 2006.168.07:56:30.61#ibcon#about to read 6, iclass 27, count 0 2006.168.07:56:30.61#ibcon#read 6, iclass 27, count 0 2006.168.07:56:30.61#ibcon#end of sib2, iclass 27, count 0 2006.168.07:56:30.61#ibcon#*mode == 0, iclass 27, count 0 2006.168.07:56:30.61#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.168.07:56:30.61#ibcon#[25=USB\r\n] 2006.168.07:56:30.61#ibcon#*before write, iclass 27, count 0 2006.168.07:56:30.61#ibcon#enter sib2, iclass 27, count 0 2006.168.07:56:30.61#ibcon#flushed, iclass 27, count 0 2006.168.07:56:30.61#ibcon#about to write, iclass 27, count 0 2006.168.07:56:30.61#ibcon#wrote, iclass 27, count 0 2006.168.07:56:30.61#ibcon#about to read 3, iclass 27, count 0 2006.168.07:56:30.64#ibcon#read 3, iclass 27, count 0 2006.168.07:56:30.64#ibcon#about to read 4, iclass 27, count 0 2006.168.07:56:30.64#ibcon#read 4, iclass 27, count 0 2006.168.07:56:30.64#ibcon#about to read 5, iclass 27, count 0 2006.168.07:56:30.64#ibcon#read 5, iclass 27, count 0 2006.168.07:56:30.64#ibcon#about to read 6, iclass 27, count 0 2006.168.07:56:30.64#ibcon#read 6, iclass 27, count 0 2006.168.07:56:30.64#ibcon#end of sib2, iclass 27, count 0 2006.168.07:56:30.64#ibcon#*after write, iclass 27, count 0 2006.168.07:56:30.64#ibcon#*before return 0, iclass 27, count 0 2006.168.07:56:30.64#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.168.07:56:30.64#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.168.07:56:30.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.168.07:56:30.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.168.07:56:30.64$vc4f8/vblo=1,632.99 2006.168.07:56:30.64#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.168.07:56:30.64#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.168.07:56:30.64#ibcon#ireg 17 cls_cnt 0 2006.168.07:56:30.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.168.07:56:30.64#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.168.07:56:30.64#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.168.07:56:30.64#ibcon#enter wrdev, iclass 29, count 0 2006.168.07:56:30.64#ibcon#first serial, iclass 29, count 0 2006.168.07:56:30.64#ibcon#enter sib2, iclass 29, count 0 2006.168.07:56:30.64#ibcon#flushed, iclass 29, count 0 2006.168.07:56:30.64#ibcon#about to write, iclass 29, count 0 2006.168.07:56:30.64#ibcon#wrote, iclass 29, count 0 2006.168.07:56:30.64#ibcon#about to read 3, iclass 29, count 0 2006.168.07:56:30.66#ibcon#read 3, iclass 29, count 0 2006.168.07:56:30.66#ibcon#about to read 4, iclass 29, count 0 2006.168.07:56:30.66#ibcon#read 4, iclass 29, count 0 2006.168.07:56:30.66#ibcon#about to read 5, iclass 29, count 0 2006.168.07:56:30.66#ibcon#read 5, iclass 29, count 0 2006.168.07:56:30.66#ibcon#about to read 6, iclass 29, count 0 2006.168.07:56:30.66#ibcon#read 6, iclass 29, count 0 2006.168.07:56:30.66#ibcon#end of sib2, iclass 29, count 0 2006.168.07:56:30.66#ibcon#*mode == 0, iclass 29, count 0 2006.168.07:56:30.66#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.168.07:56:30.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.07:56:30.66#ibcon#*before write, iclass 29, count 0 2006.168.07:56:30.66#ibcon#enter sib2, iclass 29, count 0 2006.168.07:56:30.66#ibcon#flushed, iclass 29, count 0 2006.168.07:56:30.66#ibcon#about to write, iclass 29, count 0 2006.168.07:56:30.66#ibcon#wrote, iclass 29, count 0 2006.168.07:56:30.66#ibcon#about to read 3, iclass 29, count 0 2006.168.07:56:30.70#ibcon#read 3, iclass 29, count 0 2006.168.07:56:30.70#ibcon#about to read 4, iclass 29, count 0 2006.168.07:56:30.70#ibcon#read 4, iclass 29, count 0 2006.168.07:56:30.70#ibcon#about to read 5, iclass 29, count 0 2006.168.07:56:30.70#ibcon#read 5, iclass 29, count 0 2006.168.07:56:30.70#ibcon#about to read 6, iclass 29, count 0 2006.168.07:56:30.70#ibcon#read 6, iclass 29, count 0 2006.168.07:56:30.70#ibcon#end of sib2, iclass 29, count 0 2006.168.07:56:30.70#ibcon#*after write, iclass 29, count 0 2006.168.07:56:30.70#ibcon#*before return 0, iclass 29, count 0 2006.168.07:56:30.70#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.168.07:56:30.70#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.168.07:56:30.70#ibcon#about to clear, iclass 29 cls_cnt 0 2006.168.07:56:30.70#ibcon#cleared, iclass 29 cls_cnt 0 2006.168.07:56:30.70$vc4f8/vb=1,4 2006.168.07:56:30.70#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.168.07:56:30.70#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.168.07:56:30.70#ibcon#ireg 11 cls_cnt 2 2006.168.07:56:30.70#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.168.07:56:30.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.168.07:56:30.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.168.07:56:30.70#ibcon#enter wrdev, iclass 31, count 2 2006.168.07:56:30.70#ibcon#first serial, iclass 31, count 2 2006.168.07:56:30.70#ibcon#enter sib2, iclass 31, count 2 2006.168.07:56:30.70#ibcon#flushed, iclass 31, count 2 2006.168.07:56:30.70#ibcon#about to write, iclass 31, count 2 2006.168.07:56:30.70#ibcon#wrote, iclass 31, count 2 2006.168.07:56:30.70#ibcon#about to read 3, iclass 31, count 2 2006.168.07:56:30.72#ibcon#read 3, iclass 31, count 2 2006.168.07:56:30.72#ibcon#about to read 4, iclass 31, count 2 2006.168.07:56:30.72#ibcon#read 4, iclass 31, count 2 2006.168.07:56:30.72#ibcon#about to read 5, iclass 31, count 2 2006.168.07:56:30.72#ibcon#read 5, iclass 31, count 2 2006.168.07:56:30.72#ibcon#about to read 6, iclass 31, count 2 2006.168.07:56:30.72#ibcon#read 6, iclass 31, count 2 2006.168.07:56:30.72#ibcon#end of sib2, iclass 31, count 2 2006.168.07:56:30.72#ibcon#*mode == 0, iclass 31, count 2 2006.168.07:56:30.72#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.168.07:56:30.72#ibcon#[27=AT01-04\r\n] 2006.168.07:56:30.72#ibcon#*before write, iclass 31, count 2 2006.168.07:56:30.72#ibcon#enter sib2, iclass 31, count 2 2006.168.07:56:30.72#ibcon#flushed, iclass 31, count 2 2006.168.07:56:30.72#ibcon#about to write, iclass 31, count 2 2006.168.07:56:30.72#ibcon#wrote, iclass 31, count 2 2006.168.07:56:30.72#ibcon#about to read 3, iclass 31, count 2 2006.168.07:56:30.75#ibcon#read 3, iclass 31, count 2 2006.168.07:56:30.75#ibcon#about to read 4, iclass 31, count 2 2006.168.07:56:30.75#ibcon#read 4, iclass 31, count 2 2006.168.07:56:30.75#ibcon#about to read 5, iclass 31, count 2 2006.168.07:56:30.75#ibcon#read 5, iclass 31, count 2 2006.168.07:56:30.75#ibcon#about to read 6, iclass 31, count 2 2006.168.07:56:30.75#ibcon#read 6, iclass 31, count 2 2006.168.07:56:30.75#ibcon#end of sib2, iclass 31, count 2 2006.168.07:56:30.75#ibcon#*after write, iclass 31, count 2 2006.168.07:56:30.75#ibcon#*before return 0, iclass 31, count 2 2006.168.07:56:30.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.168.07:56:30.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.168.07:56:30.75#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.168.07:56:30.75#ibcon#ireg 7 cls_cnt 0 2006.168.07:56:30.75#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.168.07:56:30.87#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.168.07:56:30.87#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.168.07:56:30.87#ibcon#enter wrdev, iclass 31, count 0 2006.168.07:56:30.87#ibcon#first serial, iclass 31, count 0 2006.168.07:56:30.87#ibcon#enter sib2, iclass 31, count 0 2006.168.07:56:30.87#ibcon#flushed, iclass 31, count 0 2006.168.07:56:30.87#ibcon#about to write, iclass 31, count 0 2006.168.07:56:30.87#ibcon#wrote, iclass 31, count 0 2006.168.07:56:30.87#ibcon#about to read 3, iclass 31, count 0 2006.168.07:56:30.89#ibcon#read 3, iclass 31, count 0 2006.168.07:56:30.89#ibcon#about to read 4, iclass 31, count 0 2006.168.07:56:30.89#ibcon#read 4, iclass 31, count 0 2006.168.07:56:30.89#ibcon#about to read 5, iclass 31, count 0 2006.168.07:56:30.89#ibcon#read 5, iclass 31, count 0 2006.168.07:56:30.89#ibcon#about to read 6, iclass 31, count 0 2006.168.07:56:30.89#ibcon#read 6, iclass 31, count 0 2006.168.07:56:30.89#ibcon#end of sib2, iclass 31, count 0 2006.168.07:56:30.89#ibcon#*mode == 0, iclass 31, count 0 2006.168.07:56:30.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.168.07:56:30.89#ibcon#[27=USB\r\n] 2006.168.07:56:30.89#ibcon#*before write, iclass 31, count 0 2006.168.07:56:30.89#ibcon#enter sib2, iclass 31, count 0 2006.168.07:56:30.89#ibcon#flushed, iclass 31, count 0 2006.168.07:56:30.89#ibcon#about to write, iclass 31, count 0 2006.168.07:56:30.89#ibcon#wrote, iclass 31, count 0 2006.168.07:56:30.89#ibcon#about to read 3, iclass 31, count 0 2006.168.07:56:30.92#ibcon#read 3, iclass 31, count 0 2006.168.07:56:30.92#ibcon#about to read 4, iclass 31, count 0 2006.168.07:56:30.92#ibcon#read 4, iclass 31, count 0 2006.168.07:56:30.92#ibcon#about to read 5, iclass 31, count 0 2006.168.07:56:30.92#ibcon#read 5, iclass 31, count 0 2006.168.07:56:30.92#ibcon#about to read 6, iclass 31, count 0 2006.168.07:56:30.92#ibcon#read 6, iclass 31, count 0 2006.168.07:56:30.92#ibcon#end of sib2, iclass 31, count 0 2006.168.07:56:30.92#ibcon#*after write, iclass 31, count 0 2006.168.07:56:30.92#ibcon#*before return 0, iclass 31, count 0 2006.168.07:56:30.92#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.168.07:56:30.92#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.168.07:56:30.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.168.07:56:30.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.168.07:56:30.92$vc4f8/vblo=2,640.99 2006.168.07:56:30.92#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.168.07:56:30.92#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.168.07:56:30.92#ibcon#ireg 17 cls_cnt 0 2006.168.07:56:30.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.168.07:56:30.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.168.07:56:30.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.168.07:56:30.92#ibcon#enter wrdev, iclass 33, count 0 2006.168.07:56:30.92#ibcon#first serial, iclass 33, count 0 2006.168.07:56:30.92#ibcon#enter sib2, iclass 33, count 0 2006.168.07:56:30.92#ibcon#flushed, iclass 33, count 0 2006.168.07:56:30.92#ibcon#about to write, iclass 33, count 0 2006.168.07:56:30.92#ibcon#wrote, iclass 33, count 0 2006.168.07:56:30.92#ibcon#about to read 3, iclass 33, count 0 2006.168.07:56:30.94#ibcon#read 3, iclass 33, count 0 2006.168.07:56:30.94#ibcon#about to read 4, iclass 33, count 0 2006.168.07:56:30.94#ibcon#read 4, iclass 33, count 0 2006.168.07:56:30.94#ibcon#about to read 5, iclass 33, count 0 2006.168.07:56:30.94#ibcon#read 5, iclass 33, count 0 2006.168.07:56:30.94#ibcon#about to read 6, iclass 33, count 0 2006.168.07:56:30.94#ibcon#read 6, iclass 33, count 0 2006.168.07:56:30.94#ibcon#end of sib2, iclass 33, count 0 2006.168.07:56:30.94#ibcon#*mode == 0, iclass 33, count 0 2006.168.07:56:30.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.168.07:56:30.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.07:56:30.94#ibcon#*before write, iclass 33, count 0 2006.168.07:56:30.94#ibcon#enter sib2, iclass 33, count 0 2006.168.07:56:30.94#ibcon#flushed, iclass 33, count 0 2006.168.07:56:30.94#ibcon#about to write, iclass 33, count 0 2006.168.07:56:30.94#ibcon#wrote, iclass 33, count 0 2006.168.07:56:30.94#ibcon#about to read 3, iclass 33, count 0 2006.168.07:56:30.98#ibcon#read 3, iclass 33, count 0 2006.168.07:56:30.98#ibcon#about to read 4, iclass 33, count 0 2006.168.07:56:30.98#ibcon#read 4, iclass 33, count 0 2006.168.07:56:30.98#ibcon#about to read 5, iclass 33, count 0 2006.168.07:56:30.98#ibcon#read 5, iclass 33, count 0 2006.168.07:56:30.98#ibcon#about to read 6, iclass 33, count 0 2006.168.07:56:30.98#ibcon#read 6, iclass 33, count 0 2006.168.07:56:30.98#ibcon#end of sib2, iclass 33, count 0 2006.168.07:56:30.98#ibcon#*after write, iclass 33, count 0 2006.168.07:56:30.98#ibcon#*before return 0, iclass 33, count 0 2006.168.07:56:30.98#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.168.07:56:30.98#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.168.07:56:30.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.168.07:56:30.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.168.07:56:30.98$vc4f8/vb=2,4 2006.168.07:56:30.98#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.168.07:56:30.98#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.168.07:56:30.98#ibcon#ireg 11 cls_cnt 2 2006.168.07:56:30.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:56:31.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:56:31.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:56:31.04#ibcon#enter wrdev, iclass 35, count 2 2006.168.07:56:31.04#ibcon#first serial, iclass 35, count 2 2006.168.07:56:31.04#ibcon#enter sib2, iclass 35, count 2 2006.168.07:56:31.04#ibcon#flushed, iclass 35, count 2 2006.168.07:56:31.04#ibcon#about to write, iclass 35, count 2 2006.168.07:56:31.04#ibcon#wrote, iclass 35, count 2 2006.168.07:56:31.04#ibcon#about to read 3, iclass 35, count 2 2006.168.07:56:31.06#ibcon#read 3, iclass 35, count 2 2006.168.07:56:31.06#ibcon#about to read 4, iclass 35, count 2 2006.168.07:56:31.06#ibcon#read 4, iclass 35, count 2 2006.168.07:56:31.06#ibcon#about to read 5, iclass 35, count 2 2006.168.07:56:31.06#ibcon#read 5, iclass 35, count 2 2006.168.07:56:31.06#ibcon#about to read 6, iclass 35, count 2 2006.168.07:56:31.06#ibcon#read 6, iclass 35, count 2 2006.168.07:56:31.06#ibcon#end of sib2, iclass 35, count 2 2006.168.07:56:31.06#ibcon#*mode == 0, iclass 35, count 2 2006.168.07:56:31.06#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.168.07:56:31.06#ibcon#[27=AT02-04\r\n] 2006.168.07:56:31.06#ibcon#*before write, iclass 35, count 2 2006.168.07:56:31.06#ibcon#enter sib2, iclass 35, count 2 2006.168.07:56:31.06#ibcon#flushed, iclass 35, count 2 2006.168.07:56:31.06#ibcon#about to write, iclass 35, count 2 2006.168.07:56:31.06#ibcon#wrote, iclass 35, count 2 2006.168.07:56:31.06#ibcon#about to read 3, iclass 35, count 2 2006.168.07:56:31.09#ibcon#read 3, iclass 35, count 2 2006.168.07:56:31.09#ibcon#about to read 4, iclass 35, count 2 2006.168.07:56:31.09#ibcon#read 4, iclass 35, count 2 2006.168.07:56:31.09#ibcon#about to read 5, iclass 35, count 2 2006.168.07:56:31.09#ibcon#read 5, iclass 35, count 2 2006.168.07:56:31.09#ibcon#about to read 6, iclass 35, count 2 2006.168.07:56:31.09#ibcon#read 6, iclass 35, count 2 2006.168.07:56:31.09#ibcon#end of sib2, iclass 35, count 2 2006.168.07:56:31.09#ibcon#*after write, iclass 35, count 2 2006.168.07:56:31.09#ibcon#*before return 0, iclass 35, count 2 2006.168.07:56:31.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:56:31.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.168.07:56:31.09#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.168.07:56:31.09#ibcon#ireg 7 cls_cnt 0 2006.168.07:56:31.09#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:56:31.21#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:56:31.21#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:56:31.21#ibcon#enter wrdev, iclass 35, count 0 2006.168.07:56:31.21#ibcon#first serial, iclass 35, count 0 2006.168.07:56:31.21#ibcon#enter sib2, iclass 35, count 0 2006.168.07:56:31.21#ibcon#flushed, iclass 35, count 0 2006.168.07:56:31.21#ibcon#about to write, iclass 35, count 0 2006.168.07:56:31.21#ibcon#wrote, iclass 35, count 0 2006.168.07:56:31.21#ibcon#about to read 3, iclass 35, count 0 2006.168.07:56:31.23#ibcon#read 3, iclass 35, count 0 2006.168.07:56:31.23#ibcon#about to read 4, iclass 35, count 0 2006.168.07:56:31.23#ibcon#read 4, iclass 35, count 0 2006.168.07:56:31.23#ibcon#about to read 5, iclass 35, count 0 2006.168.07:56:31.23#ibcon#read 5, iclass 35, count 0 2006.168.07:56:31.23#ibcon#about to read 6, iclass 35, count 0 2006.168.07:56:31.23#ibcon#read 6, iclass 35, count 0 2006.168.07:56:31.23#ibcon#end of sib2, iclass 35, count 0 2006.168.07:56:31.23#ibcon#*mode == 0, iclass 35, count 0 2006.168.07:56:31.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.168.07:56:31.23#ibcon#[27=USB\r\n] 2006.168.07:56:31.23#ibcon#*before write, iclass 35, count 0 2006.168.07:56:31.23#ibcon#enter sib2, iclass 35, count 0 2006.168.07:56:31.23#ibcon#flushed, iclass 35, count 0 2006.168.07:56:31.23#ibcon#about to write, iclass 35, count 0 2006.168.07:56:31.23#ibcon#wrote, iclass 35, count 0 2006.168.07:56:31.23#ibcon#about to read 3, iclass 35, count 0 2006.168.07:56:31.26#ibcon#read 3, iclass 35, count 0 2006.168.07:56:31.26#ibcon#about to read 4, iclass 35, count 0 2006.168.07:56:31.26#ibcon#read 4, iclass 35, count 0 2006.168.07:56:31.26#ibcon#about to read 5, iclass 35, count 0 2006.168.07:56:31.26#ibcon#read 5, iclass 35, count 0 2006.168.07:56:31.26#ibcon#about to read 6, iclass 35, count 0 2006.168.07:56:31.26#ibcon#read 6, iclass 35, count 0 2006.168.07:56:31.26#ibcon#end of sib2, iclass 35, count 0 2006.168.07:56:31.26#ibcon#*after write, iclass 35, count 0 2006.168.07:56:31.26#ibcon#*before return 0, iclass 35, count 0 2006.168.07:56:31.26#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:56:31.26#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.168.07:56:31.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.168.07:56:31.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.168.07:56:31.26$vc4f8/vblo=3,656.99 2006.168.07:56:31.26#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.168.07:56:31.26#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.168.07:56:31.26#ibcon#ireg 17 cls_cnt 0 2006.168.07:56:31.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:56:31.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:56:31.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:56:31.26#ibcon#enter wrdev, iclass 37, count 0 2006.168.07:56:31.26#ibcon#first serial, iclass 37, count 0 2006.168.07:56:31.26#ibcon#enter sib2, iclass 37, count 0 2006.168.07:56:31.26#ibcon#flushed, iclass 37, count 0 2006.168.07:56:31.26#ibcon#about to write, iclass 37, count 0 2006.168.07:56:31.26#ibcon#wrote, iclass 37, count 0 2006.168.07:56:31.26#ibcon#about to read 3, iclass 37, count 0 2006.168.07:56:31.28#ibcon#read 3, iclass 37, count 0 2006.168.07:56:31.28#ibcon#about to read 4, iclass 37, count 0 2006.168.07:56:31.28#ibcon#read 4, iclass 37, count 0 2006.168.07:56:31.28#ibcon#about to read 5, iclass 37, count 0 2006.168.07:56:31.28#ibcon#read 5, iclass 37, count 0 2006.168.07:56:31.28#ibcon#about to read 6, iclass 37, count 0 2006.168.07:56:31.28#ibcon#read 6, iclass 37, count 0 2006.168.07:56:31.28#ibcon#end of sib2, iclass 37, count 0 2006.168.07:56:31.28#ibcon#*mode == 0, iclass 37, count 0 2006.168.07:56:31.28#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.168.07:56:31.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.07:56:31.28#ibcon#*before write, iclass 37, count 0 2006.168.07:56:31.28#ibcon#enter sib2, iclass 37, count 0 2006.168.07:56:31.28#ibcon#flushed, iclass 37, count 0 2006.168.07:56:31.28#ibcon#about to write, iclass 37, count 0 2006.168.07:56:31.28#ibcon#wrote, iclass 37, count 0 2006.168.07:56:31.28#ibcon#about to read 3, iclass 37, count 0 2006.168.07:56:31.32#ibcon#read 3, iclass 37, count 0 2006.168.07:56:31.32#ibcon#about to read 4, iclass 37, count 0 2006.168.07:56:31.32#ibcon#read 4, iclass 37, count 0 2006.168.07:56:31.32#ibcon#about to read 5, iclass 37, count 0 2006.168.07:56:31.32#ibcon#read 5, iclass 37, count 0 2006.168.07:56:31.32#ibcon#about to read 6, iclass 37, count 0 2006.168.07:56:31.32#ibcon#read 6, iclass 37, count 0 2006.168.07:56:31.32#ibcon#end of sib2, iclass 37, count 0 2006.168.07:56:31.32#ibcon#*after write, iclass 37, count 0 2006.168.07:56:31.32#ibcon#*before return 0, iclass 37, count 0 2006.168.07:56:31.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:56:31.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.168.07:56:31.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.168.07:56:31.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.168.07:56:31.32$vc4f8/vb=3,4 2006.168.07:56:31.32#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.168.07:56:31.32#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.168.07:56:31.32#ibcon#ireg 11 cls_cnt 2 2006.168.07:56:31.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:56:31.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:56:31.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:56:31.38#ibcon#enter wrdev, iclass 39, count 2 2006.168.07:56:31.38#ibcon#first serial, iclass 39, count 2 2006.168.07:56:31.38#ibcon#enter sib2, iclass 39, count 2 2006.168.07:56:31.38#ibcon#flushed, iclass 39, count 2 2006.168.07:56:31.38#ibcon#about to write, iclass 39, count 2 2006.168.07:56:31.38#ibcon#wrote, iclass 39, count 2 2006.168.07:56:31.38#ibcon#about to read 3, iclass 39, count 2 2006.168.07:56:31.40#ibcon#read 3, iclass 39, count 2 2006.168.07:56:31.40#ibcon#about to read 4, iclass 39, count 2 2006.168.07:56:31.40#ibcon#read 4, iclass 39, count 2 2006.168.07:56:31.40#ibcon#about to read 5, iclass 39, count 2 2006.168.07:56:31.40#ibcon#read 5, iclass 39, count 2 2006.168.07:56:31.40#ibcon#about to read 6, iclass 39, count 2 2006.168.07:56:31.40#ibcon#read 6, iclass 39, count 2 2006.168.07:56:31.40#ibcon#end of sib2, iclass 39, count 2 2006.168.07:56:31.40#ibcon#*mode == 0, iclass 39, count 2 2006.168.07:56:31.40#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.168.07:56:31.40#ibcon#[27=AT03-04\r\n] 2006.168.07:56:31.40#ibcon#*before write, iclass 39, count 2 2006.168.07:56:31.40#ibcon#enter sib2, iclass 39, count 2 2006.168.07:56:31.40#ibcon#flushed, iclass 39, count 2 2006.168.07:56:31.40#ibcon#about to write, iclass 39, count 2 2006.168.07:56:31.40#ibcon#wrote, iclass 39, count 2 2006.168.07:56:31.40#ibcon#about to read 3, iclass 39, count 2 2006.168.07:56:31.43#ibcon#read 3, iclass 39, count 2 2006.168.07:56:31.43#ibcon#about to read 4, iclass 39, count 2 2006.168.07:56:31.43#ibcon#read 4, iclass 39, count 2 2006.168.07:56:31.43#ibcon#about to read 5, iclass 39, count 2 2006.168.07:56:31.43#ibcon#read 5, iclass 39, count 2 2006.168.07:56:31.43#ibcon#about to read 6, iclass 39, count 2 2006.168.07:56:31.43#ibcon#read 6, iclass 39, count 2 2006.168.07:56:31.43#ibcon#end of sib2, iclass 39, count 2 2006.168.07:56:31.43#ibcon#*after write, iclass 39, count 2 2006.168.07:56:31.43#ibcon#*before return 0, iclass 39, count 2 2006.168.07:56:31.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:56:31.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.168.07:56:31.43#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.168.07:56:31.43#ibcon#ireg 7 cls_cnt 0 2006.168.07:56:31.43#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:56:31.55#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:56:31.55#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:56:31.55#ibcon#enter wrdev, iclass 39, count 0 2006.168.07:56:31.55#ibcon#first serial, iclass 39, count 0 2006.168.07:56:31.55#ibcon#enter sib2, iclass 39, count 0 2006.168.07:56:31.55#ibcon#flushed, iclass 39, count 0 2006.168.07:56:31.55#ibcon#about to write, iclass 39, count 0 2006.168.07:56:31.55#ibcon#wrote, iclass 39, count 0 2006.168.07:56:31.55#ibcon#about to read 3, iclass 39, count 0 2006.168.07:56:31.57#ibcon#read 3, iclass 39, count 0 2006.168.07:56:31.57#ibcon#about to read 4, iclass 39, count 0 2006.168.07:56:31.57#ibcon#read 4, iclass 39, count 0 2006.168.07:56:31.57#ibcon#about to read 5, iclass 39, count 0 2006.168.07:56:31.57#ibcon#read 5, iclass 39, count 0 2006.168.07:56:31.57#ibcon#about to read 6, iclass 39, count 0 2006.168.07:56:31.57#ibcon#read 6, iclass 39, count 0 2006.168.07:56:31.57#ibcon#end of sib2, iclass 39, count 0 2006.168.07:56:31.57#ibcon#*mode == 0, iclass 39, count 0 2006.168.07:56:31.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.168.07:56:31.57#ibcon#[27=USB\r\n] 2006.168.07:56:31.57#ibcon#*before write, iclass 39, count 0 2006.168.07:56:31.57#ibcon#enter sib2, iclass 39, count 0 2006.168.07:56:31.57#ibcon#flushed, iclass 39, count 0 2006.168.07:56:31.57#ibcon#about to write, iclass 39, count 0 2006.168.07:56:31.57#ibcon#wrote, iclass 39, count 0 2006.168.07:56:31.57#ibcon#about to read 3, iclass 39, count 0 2006.168.07:56:31.60#ibcon#read 3, iclass 39, count 0 2006.168.07:56:31.60#ibcon#about to read 4, iclass 39, count 0 2006.168.07:56:31.60#ibcon#read 4, iclass 39, count 0 2006.168.07:56:31.60#ibcon#about to read 5, iclass 39, count 0 2006.168.07:56:31.60#ibcon#read 5, iclass 39, count 0 2006.168.07:56:31.60#ibcon#about to read 6, iclass 39, count 0 2006.168.07:56:31.60#ibcon#read 6, iclass 39, count 0 2006.168.07:56:31.60#ibcon#end of sib2, iclass 39, count 0 2006.168.07:56:31.60#ibcon#*after write, iclass 39, count 0 2006.168.07:56:31.60#ibcon#*before return 0, iclass 39, count 0 2006.168.07:56:31.60#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:56:31.60#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.168.07:56:31.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.168.07:56:31.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.168.07:56:31.60$vc4f8/vblo=4,712.99 2006.168.07:56:31.60#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.168.07:56:31.60#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.168.07:56:31.60#ibcon#ireg 17 cls_cnt 0 2006.168.07:56:31.60#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:56:31.60#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:56:31.60#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:56:31.60#ibcon#enter wrdev, iclass 3, count 0 2006.168.07:56:31.60#ibcon#first serial, iclass 3, count 0 2006.168.07:56:31.60#ibcon#enter sib2, iclass 3, count 0 2006.168.07:56:31.60#ibcon#flushed, iclass 3, count 0 2006.168.07:56:31.60#ibcon#about to write, iclass 3, count 0 2006.168.07:56:31.60#ibcon#wrote, iclass 3, count 0 2006.168.07:56:31.60#ibcon#about to read 3, iclass 3, count 0 2006.168.07:56:31.62#ibcon#read 3, iclass 3, count 0 2006.168.07:56:31.62#ibcon#about to read 4, iclass 3, count 0 2006.168.07:56:31.62#ibcon#read 4, iclass 3, count 0 2006.168.07:56:31.62#ibcon#about to read 5, iclass 3, count 0 2006.168.07:56:31.62#ibcon#read 5, iclass 3, count 0 2006.168.07:56:31.62#ibcon#about to read 6, iclass 3, count 0 2006.168.07:56:31.62#ibcon#read 6, iclass 3, count 0 2006.168.07:56:31.62#ibcon#end of sib2, iclass 3, count 0 2006.168.07:56:31.62#ibcon#*mode == 0, iclass 3, count 0 2006.168.07:56:31.62#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.168.07:56:31.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.07:56:31.62#ibcon#*before write, iclass 3, count 0 2006.168.07:56:31.62#ibcon#enter sib2, iclass 3, count 0 2006.168.07:56:31.62#ibcon#flushed, iclass 3, count 0 2006.168.07:56:31.62#ibcon#about to write, iclass 3, count 0 2006.168.07:56:31.62#ibcon#wrote, iclass 3, count 0 2006.168.07:56:31.62#ibcon#about to read 3, iclass 3, count 0 2006.168.07:56:31.66#ibcon#read 3, iclass 3, count 0 2006.168.07:56:31.66#ibcon#about to read 4, iclass 3, count 0 2006.168.07:56:31.66#ibcon#read 4, iclass 3, count 0 2006.168.07:56:31.66#ibcon#about to read 5, iclass 3, count 0 2006.168.07:56:31.66#ibcon#read 5, iclass 3, count 0 2006.168.07:56:31.66#ibcon#about to read 6, iclass 3, count 0 2006.168.07:56:31.66#ibcon#read 6, iclass 3, count 0 2006.168.07:56:31.66#ibcon#end of sib2, iclass 3, count 0 2006.168.07:56:31.66#ibcon#*after write, iclass 3, count 0 2006.168.07:56:31.66#ibcon#*before return 0, iclass 3, count 0 2006.168.07:56:31.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:56:31.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:56:31.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.168.07:56:31.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.168.07:56:31.66$vc4f8/vb=4,4 2006.168.07:56:31.66#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.168.07:56:31.66#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.168.07:56:31.66#ibcon#ireg 11 cls_cnt 2 2006.168.07:56:31.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:56:31.72#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:56:31.72#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:56:31.72#ibcon#enter wrdev, iclass 5, count 2 2006.168.07:56:31.72#ibcon#first serial, iclass 5, count 2 2006.168.07:56:31.72#ibcon#enter sib2, iclass 5, count 2 2006.168.07:56:31.72#ibcon#flushed, iclass 5, count 2 2006.168.07:56:31.72#ibcon#about to write, iclass 5, count 2 2006.168.07:56:31.72#ibcon#wrote, iclass 5, count 2 2006.168.07:56:31.72#ibcon#about to read 3, iclass 5, count 2 2006.168.07:56:31.74#ibcon#read 3, iclass 5, count 2 2006.168.07:56:31.74#ibcon#about to read 4, iclass 5, count 2 2006.168.07:56:31.74#ibcon#read 4, iclass 5, count 2 2006.168.07:56:31.74#ibcon#about to read 5, iclass 5, count 2 2006.168.07:56:31.74#ibcon#read 5, iclass 5, count 2 2006.168.07:56:31.74#ibcon#about to read 6, iclass 5, count 2 2006.168.07:56:31.74#ibcon#read 6, iclass 5, count 2 2006.168.07:56:31.74#ibcon#end of sib2, iclass 5, count 2 2006.168.07:56:31.74#ibcon#*mode == 0, iclass 5, count 2 2006.168.07:56:31.74#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.168.07:56:31.74#ibcon#[27=AT04-04\r\n] 2006.168.07:56:31.74#ibcon#*before write, iclass 5, count 2 2006.168.07:56:31.74#ibcon#enter sib2, iclass 5, count 2 2006.168.07:56:31.74#ibcon#flushed, iclass 5, count 2 2006.168.07:56:31.74#ibcon#about to write, iclass 5, count 2 2006.168.07:56:31.74#ibcon#wrote, iclass 5, count 2 2006.168.07:56:31.74#ibcon#about to read 3, iclass 5, count 2 2006.168.07:56:31.77#ibcon#read 3, iclass 5, count 2 2006.168.07:56:31.77#ibcon#about to read 4, iclass 5, count 2 2006.168.07:56:31.77#ibcon#read 4, iclass 5, count 2 2006.168.07:56:31.77#ibcon#about to read 5, iclass 5, count 2 2006.168.07:56:31.77#ibcon#read 5, iclass 5, count 2 2006.168.07:56:31.77#ibcon#about to read 6, iclass 5, count 2 2006.168.07:56:31.77#ibcon#read 6, iclass 5, count 2 2006.168.07:56:31.77#ibcon#end of sib2, iclass 5, count 2 2006.168.07:56:31.77#ibcon#*after write, iclass 5, count 2 2006.168.07:56:31.77#ibcon#*before return 0, iclass 5, count 2 2006.168.07:56:31.77#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:56:31.77#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.168.07:56:31.77#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.168.07:56:31.77#ibcon#ireg 7 cls_cnt 0 2006.168.07:56:31.77#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:56:31.89#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:56:31.89#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:56:31.89#ibcon#enter wrdev, iclass 5, count 0 2006.168.07:56:31.89#ibcon#first serial, iclass 5, count 0 2006.168.07:56:31.89#ibcon#enter sib2, iclass 5, count 0 2006.168.07:56:31.89#ibcon#flushed, iclass 5, count 0 2006.168.07:56:31.89#ibcon#about to write, iclass 5, count 0 2006.168.07:56:31.89#ibcon#wrote, iclass 5, count 0 2006.168.07:56:31.89#ibcon#about to read 3, iclass 5, count 0 2006.168.07:56:31.91#ibcon#read 3, iclass 5, count 0 2006.168.07:56:31.91#ibcon#about to read 4, iclass 5, count 0 2006.168.07:56:31.91#ibcon#read 4, iclass 5, count 0 2006.168.07:56:31.91#ibcon#about to read 5, iclass 5, count 0 2006.168.07:56:31.91#ibcon#read 5, iclass 5, count 0 2006.168.07:56:31.91#ibcon#about to read 6, iclass 5, count 0 2006.168.07:56:31.91#ibcon#read 6, iclass 5, count 0 2006.168.07:56:31.91#ibcon#end of sib2, iclass 5, count 0 2006.168.07:56:31.91#ibcon#*mode == 0, iclass 5, count 0 2006.168.07:56:31.91#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.168.07:56:31.91#ibcon#[27=USB\r\n] 2006.168.07:56:31.91#ibcon#*before write, iclass 5, count 0 2006.168.07:56:31.91#ibcon#enter sib2, iclass 5, count 0 2006.168.07:56:31.91#ibcon#flushed, iclass 5, count 0 2006.168.07:56:31.91#ibcon#about to write, iclass 5, count 0 2006.168.07:56:31.91#ibcon#wrote, iclass 5, count 0 2006.168.07:56:31.91#ibcon#about to read 3, iclass 5, count 0 2006.168.07:56:31.94#ibcon#read 3, iclass 5, count 0 2006.168.07:56:31.94#ibcon#about to read 4, iclass 5, count 0 2006.168.07:56:31.94#ibcon#read 4, iclass 5, count 0 2006.168.07:56:31.94#ibcon#about to read 5, iclass 5, count 0 2006.168.07:56:31.94#ibcon#read 5, iclass 5, count 0 2006.168.07:56:31.94#ibcon#about to read 6, iclass 5, count 0 2006.168.07:56:31.94#ibcon#read 6, iclass 5, count 0 2006.168.07:56:31.94#ibcon#end of sib2, iclass 5, count 0 2006.168.07:56:31.94#ibcon#*after write, iclass 5, count 0 2006.168.07:56:31.94#ibcon#*before return 0, iclass 5, count 0 2006.168.07:56:31.94#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:56:31.94#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.168.07:56:31.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.168.07:56:31.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.168.07:56:31.94$vc4f8/vblo=5,744.99 2006.168.07:56:31.94#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.168.07:56:31.94#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.168.07:56:31.94#ibcon#ireg 17 cls_cnt 0 2006.168.07:56:31.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:56:31.94#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:56:31.94#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:56:31.94#ibcon#enter wrdev, iclass 7, count 0 2006.168.07:56:31.94#ibcon#first serial, iclass 7, count 0 2006.168.07:56:31.94#ibcon#enter sib2, iclass 7, count 0 2006.168.07:56:31.94#ibcon#flushed, iclass 7, count 0 2006.168.07:56:31.94#ibcon#about to write, iclass 7, count 0 2006.168.07:56:31.94#ibcon#wrote, iclass 7, count 0 2006.168.07:56:31.94#ibcon#about to read 3, iclass 7, count 0 2006.168.07:56:31.96#ibcon#read 3, iclass 7, count 0 2006.168.07:56:31.96#ibcon#about to read 4, iclass 7, count 0 2006.168.07:56:31.96#ibcon#read 4, iclass 7, count 0 2006.168.07:56:31.96#ibcon#about to read 5, iclass 7, count 0 2006.168.07:56:31.96#ibcon#read 5, iclass 7, count 0 2006.168.07:56:31.96#ibcon#about to read 6, iclass 7, count 0 2006.168.07:56:31.96#ibcon#read 6, iclass 7, count 0 2006.168.07:56:31.96#ibcon#end of sib2, iclass 7, count 0 2006.168.07:56:31.96#ibcon#*mode == 0, iclass 7, count 0 2006.168.07:56:31.96#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.168.07:56:31.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.07:56:31.96#ibcon#*before write, iclass 7, count 0 2006.168.07:56:31.96#ibcon#enter sib2, iclass 7, count 0 2006.168.07:56:31.96#ibcon#flushed, iclass 7, count 0 2006.168.07:56:31.96#ibcon#about to write, iclass 7, count 0 2006.168.07:56:31.96#ibcon#wrote, iclass 7, count 0 2006.168.07:56:31.96#ibcon#about to read 3, iclass 7, count 0 2006.168.07:56:32.00#ibcon#read 3, iclass 7, count 0 2006.168.07:56:32.00#ibcon#about to read 4, iclass 7, count 0 2006.168.07:56:32.00#ibcon#read 4, iclass 7, count 0 2006.168.07:56:32.00#ibcon#about to read 5, iclass 7, count 0 2006.168.07:56:32.00#ibcon#read 5, iclass 7, count 0 2006.168.07:56:32.00#ibcon#about to read 6, iclass 7, count 0 2006.168.07:56:32.00#ibcon#read 6, iclass 7, count 0 2006.168.07:56:32.00#ibcon#end of sib2, iclass 7, count 0 2006.168.07:56:32.00#ibcon#*after write, iclass 7, count 0 2006.168.07:56:32.00#ibcon#*before return 0, iclass 7, count 0 2006.168.07:56:32.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:56:32.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.168.07:56:32.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.168.07:56:32.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.168.07:56:32.00$vc4f8/vb=5,4 2006.168.07:56:32.00#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.168.07:56:32.00#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.168.07:56:32.00#ibcon#ireg 11 cls_cnt 2 2006.168.07:56:32.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:56:32.06#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:56:32.06#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:56:32.06#ibcon#enter wrdev, iclass 11, count 2 2006.168.07:56:32.06#ibcon#first serial, iclass 11, count 2 2006.168.07:56:32.06#ibcon#enter sib2, iclass 11, count 2 2006.168.07:56:32.06#ibcon#flushed, iclass 11, count 2 2006.168.07:56:32.06#ibcon#about to write, iclass 11, count 2 2006.168.07:56:32.06#ibcon#wrote, iclass 11, count 2 2006.168.07:56:32.06#ibcon#about to read 3, iclass 11, count 2 2006.168.07:56:32.08#ibcon#read 3, iclass 11, count 2 2006.168.07:56:32.08#ibcon#about to read 4, iclass 11, count 2 2006.168.07:56:32.08#ibcon#read 4, iclass 11, count 2 2006.168.07:56:32.08#ibcon#about to read 5, iclass 11, count 2 2006.168.07:56:32.08#ibcon#read 5, iclass 11, count 2 2006.168.07:56:32.08#ibcon#about to read 6, iclass 11, count 2 2006.168.07:56:32.08#ibcon#read 6, iclass 11, count 2 2006.168.07:56:32.08#ibcon#end of sib2, iclass 11, count 2 2006.168.07:56:32.08#ibcon#*mode == 0, iclass 11, count 2 2006.168.07:56:32.08#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.168.07:56:32.08#ibcon#[27=AT05-04\r\n] 2006.168.07:56:32.08#ibcon#*before write, iclass 11, count 2 2006.168.07:56:32.08#ibcon#enter sib2, iclass 11, count 2 2006.168.07:56:32.08#ibcon#flushed, iclass 11, count 2 2006.168.07:56:32.08#ibcon#about to write, iclass 11, count 2 2006.168.07:56:32.08#ibcon#wrote, iclass 11, count 2 2006.168.07:56:32.08#ibcon#about to read 3, iclass 11, count 2 2006.168.07:56:32.11#ibcon#read 3, iclass 11, count 2 2006.168.07:56:32.11#ibcon#about to read 4, iclass 11, count 2 2006.168.07:56:32.11#ibcon#read 4, iclass 11, count 2 2006.168.07:56:32.11#ibcon#about to read 5, iclass 11, count 2 2006.168.07:56:32.11#ibcon#read 5, iclass 11, count 2 2006.168.07:56:32.11#ibcon#about to read 6, iclass 11, count 2 2006.168.07:56:32.11#ibcon#read 6, iclass 11, count 2 2006.168.07:56:32.11#ibcon#end of sib2, iclass 11, count 2 2006.168.07:56:32.11#ibcon#*after write, iclass 11, count 2 2006.168.07:56:32.11#ibcon#*before return 0, iclass 11, count 2 2006.168.07:56:32.11#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:56:32.11#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.168.07:56:32.11#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.168.07:56:32.11#ibcon#ireg 7 cls_cnt 0 2006.168.07:56:32.11#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:56:32.23#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:56:32.23#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:56:32.23#ibcon#enter wrdev, iclass 11, count 0 2006.168.07:56:32.23#ibcon#first serial, iclass 11, count 0 2006.168.07:56:32.23#ibcon#enter sib2, iclass 11, count 0 2006.168.07:56:32.23#ibcon#flushed, iclass 11, count 0 2006.168.07:56:32.23#ibcon#about to write, iclass 11, count 0 2006.168.07:56:32.23#ibcon#wrote, iclass 11, count 0 2006.168.07:56:32.23#ibcon#about to read 3, iclass 11, count 0 2006.168.07:56:32.25#ibcon#read 3, iclass 11, count 0 2006.168.07:56:32.25#ibcon#about to read 4, iclass 11, count 0 2006.168.07:56:32.25#ibcon#read 4, iclass 11, count 0 2006.168.07:56:32.25#ibcon#about to read 5, iclass 11, count 0 2006.168.07:56:32.25#ibcon#read 5, iclass 11, count 0 2006.168.07:56:32.25#ibcon#about to read 6, iclass 11, count 0 2006.168.07:56:32.25#ibcon#read 6, iclass 11, count 0 2006.168.07:56:32.25#ibcon#end of sib2, iclass 11, count 0 2006.168.07:56:32.25#ibcon#*mode == 0, iclass 11, count 0 2006.168.07:56:32.25#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.168.07:56:32.25#ibcon#[27=USB\r\n] 2006.168.07:56:32.25#ibcon#*before write, iclass 11, count 0 2006.168.07:56:32.25#ibcon#enter sib2, iclass 11, count 0 2006.168.07:56:32.25#ibcon#flushed, iclass 11, count 0 2006.168.07:56:32.25#ibcon#about to write, iclass 11, count 0 2006.168.07:56:32.25#ibcon#wrote, iclass 11, count 0 2006.168.07:56:32.25#ibcon#about to read 3, iclass 11, count 0 2006.168.07:56:32.28#ibcon#read 3, iclass 11, count 0 2006.168.07:56:32.28#ibcon#about to read 4, iclass 11, count 0 2006.168.07:56:32.28#ibcon#read 4, iclass 11, count 0 2006.168.07:56:32.28#ibcon#about to read 5, iclass 11, count 0 2006.168.07:56:32.28#ibcon#read 5, iclass 11, count 0 2006.168.07:56:32.28#ibcon#about to read 6, iclass 11, count 0 2006.168.07:56:32.28#ibcon#read 6, iclass 11, count 0 2006.168.07:56:32.28#ibcon#end of sib2, iclass 11, count 0 2006.168.07:56:32.28#ibcon#*after write, iclass 11, count 0 2006.168.07:56:32.28#ibcon#*before return 0, iclass 11, count 0 2006.168.07:56:32.28#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:56:32.28#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.168.07:56:32.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.168.07:56:32.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.168.07:56:32.28$vc4f8/vblo=6,752.99 2006.168.07:56:32.28#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.168.07:56:32.28#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.168.07:56:32.28#ibcon#ireg 17 cls_cnt 0 2006.168.07:56:32.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:56:32.28#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:56:32.28#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:56:32.28#ibcon#enter wrdev, iclass 13, count 0 2006.168.07:56:32.28#ibcon#first serial, iclass 13, count 0 2006.168.07:56:32.28#ibcon#enter sib2, iclass 13, count 0 2006.168.07:56:32.28#ibcon#flushed, iclass 13, count 0 2006.168.07:56:32.28#ibcon#about to write, iclass 13, count 0 2006.168.07:56:32.28#ibcon#wrote, iclass 13, count 0 2006.168.07:56:32.28#ibcon#about to read 3, iclass 13, count 0 2006.168.07:56:32.30#ibcon#read 3, iclass 13, count 0 2006.168.07:56:32.30#ibcon#about to read 4, iclass 13, count 0 2006.168.07:56:32.30#ibcon#read 4, iclass 13, count 0 2006.168.07:56:32.30#ibcon#about to read 5, iclass 13, count 0 2006.168.07:56:32.30#ibcon#read 5, iclass 13, count 0 2006.168.07:56:32.30#ibcon#about to read 6, iclass 13, count 0 2006.168.07:56:32.30#ibcon#read 6, iclass 13, count 0 2006.168.07:56:32.30#ibcon#end of sib2, iclass 13, count 0 2006.168.07:56:32.30#ibcon#*mode == 0, iclass 13, count 0 2006.168.07:56:32.30#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.168.07:56:32.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.07:56:32.30#ibcon#*before write, iclass 13, count 0 2006.168.07:56:32.30#ibcon#enter sib2, iclass 13, count 0 2006.168.07:56:32.30#ibcon#flushed, iclass 13, count 0 2006.168.07:56:32.30#ibcon#about to write, iclass 13, count 0 2006.168.07:56:32.30#ibcon#wrote, iclass 13, count 0 2006.168.07:56:32.30#ibcon#about to read 3, iclass 13, count 0 2006.168.07:56:32.34#ibcon#read 3, iclass 13, count 0 2006.168.07:56:32.34#ibcon#about to read 4, iclass 13, count 0 2006.168.07:56:32.34#ibcon#read 4, iclass 13, count 0 2006.168.07:56:32.34#ibcon#about to read 5, iclass 13, count 0 2006.168.07:56:32.34#ibcon#read 5, iclass 13, count 0 2006.168.07:56:32.34#ibcon#about to read 6, iclass 13, count 0 2006.168.07:56:32.34#ibcon#read 6, iclass 13, count 0 2006.168.07:56:32.34#ibcon#end of sib2, iclass 13, count 0 2006.168.07:56:32.34#ibcon#*after write, iclass 13, count 0 2006.168.07:56:32.34#ibcon#*before return 0, iclass 13, count 0 2006.168.07:56:32.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:56:32.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.168.07:56:32.34#ibcon#about to clear, iclass 13 cls_cnt 0 2006.168.07:56:32.34#ibcon#cleared, iclass 13 cls_cnt 0 2006.168.07:56:32.34$vc4f8/vb=6,4 2006.168.07:56:32.34#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.168.07:56:32.34#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.168.07:56:32.34#ibcon#ireg 11 cls_cnt 2 2006.168.07:56:32.34#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.168.07:56:32.40#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.168.07:56:32.40#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.168.07:56:32.40#ibcon#enter wrdev, iclass 15, count 2 2006.168.07:56:32.40#ibcon#first serial, iclass 15, count 2 2006.168.07:56:32.40#ibcon#enter sib2, iclass 15, count 2 2006.168.07:56:32.40#ibcon#flushed, iclass 15, count 2 2006.168.07:56:32.40#ibcon#about to write, iclass 15, count 2 2006.168.07:56:32.40#ibcon#wrote, iclass 15, count 2 2006.168.07:56:32.40#ibcon#about to read 3, iclass 15, count 2 2006.168.07:56:32.42#ibcon#read 3, iclass 15, count 2 2006.168.07:56:32.42#ibcon#about to read 4, iclass 15, count 2 2006.168.07:56:32.42#ibcon#read 4, iclass 15, count 2 2006.168.07:56:32.42#ibcon#about to read 5, iclass 15, count 2 2006.168.07:56:32.42#ibcon#read 5, iclass 15, count 2 2006.168.07:56:32.42#ibcon#about to read 6, iclass 15, count 2 2006.168.07:56:32.42#ibcon#read 6, iclass 15, count 2 2006.168.07:56:32.42#ibcon#end of sib2, iclass 15, count 2 2006.168.07:56:32.42#ibcon#*mode == 0, iclass 15, count 2 2006.168.07:56:32.42#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.168.07:56:32.42#ibcon#[27=AT06-04\r\n] 2006.168.07:56:32.42#ibcon#*before write, iclass 15, count 2 2006.168.07:56:32.42#ibcon#enter sib2, iclass 15, count 2 2006.168.07:56:32.42#ibcon#flushed, iclass 15, count 2 2006.168.07:56:32.42#ibcon#about to write, iclass 15, count 2 2006.168.07:56:32.42#ibcon#wrote, iclass 15, count 2 2006.168.07:56:32.42#ibcon#about to read 3, iclass 15, count 2 2006.168.07:56:32.45#ibcon#read 3, iclass 15, count 2 2006.168.07:56:32.45#ibcon#about to read 4, iclass 15, count 2 2006.168.07:56:32.45#ibcon#read 4, iclass 15, count 2 2006.168.07:56:32.45#ibcon#about to read 5, iclass 15, count 2 2006.168.07:56:32.45#ibcon#read 5, iclass 15, count 2 2006.168.07:56:32.45#ibcon#about to read 6, iclass 15, count 2 2006.168.07:56:32.45#ibcon#read 6, iclass 15, count 2 2006.168.07:56:32.45#ibcon#end of sib2, iclass 15, count 2 2006.168.07:56:32.45#ibcon#*after write, iclass 15, count 2 2006.168.07:56:32.45#ibcon#*before return 0, iclass 15, count 2 2006.168.07:56:32.45#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.168.07:56:32.45#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.168.07:56:32.45#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.168.07:56:32.45#ibcon#ireg 7 cls_cnt 0 2006.168.07:56:32.45#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.168.07:56:32.57#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.168.07:56:32.57#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.168.07:56:32.57#ibcon#enter wrdev, iclass 15, count 0 2006.168.07:56:32.57#ibcon#first serial, iclass 15, count 0 2006.168.07:56:32.57#ibcon#enter sib2, iclass 15, count 0 2006.168.07:56:32.57#ibcon#flushed, iclass 15, count 0 2006.168.07:56:32.57#ibcon#about to write, iclass 15, count 0 2006.168.07:56:32.57#ibcon#wrote, iclass 15, count 0 2006.168.07:56:32.57#ibcon#about to read 3, iclass 15, count 0 2006.168.07:56:32.59#ibcon#read 3, iclass 15, count 0 2006.168.07:56:32.59#ibcon#about to read 4, iclass 15, count 0 2006.168.07:56:32.59#ibcon#read 4, iclass 15, count 0 2006.168.07:56:32.59#ibcon#about to read 5, iclass 15, count 0 2006.168.07:56:32.59#ibcon#read 5, iclass 15, count 0 2006.168.07:56:32.59#ibcon#about to read 6, iclass 15, count 0 2006.168.07:56:32.59#ibcon#read 6, iclass 15, count 0 2006.168.07:56:32.59#ibcon#end of sib2, iclass 15, count 0 2006.168.07:56:32.59#ibcon#*mode == 0, iclass 15, count 0 2006.168.07:56:32.59#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.168.07:56:32.59#ibcon#[27=USB\r\n] 2006.168.07:56:32.59#ibcon#*before write, iclass 15, count 0 2006.168.07:56:32.59#ibcon#enter sib2, iclass 15, count 0 2006.168.07:56:32.59#ibcon#flushed, iclass 15, count 0 2006.168.07:56:32.59#ibcon#about to write, iclass 15, count 0 2006.168.07:56:32.59#ibcon#wrote, iclass 15, count 0 2006.168.07:56:32.59#ibcon#about to read 3, iclass 15, count 0 2006.168.07:56:32.62#ibcon#read 3, iclass 15, count 0 2006.168.07:56:32.62#ibcon#about to read 4, iclass 15, count 0 2006.168.07:56:32.62#ibcon#read 4, iclass 15, count 0 2006.168.07:56:32.62#ibcon#about to read 5, iclass 15, count 0 2006.168.07:56:32.62#ibcon#read 5, iclass 15, count 0 2006.168.07:56:32.62#ibcon#about to read 6, iclass 15, count 0 2006.168.07:56:32.62#ibcon#read 6, iclass 15, count 0 2006.168.07:56:32.62#ibcon#end of sib2, iclass 15, count 0 2006.168.07:56:32.62#ibcon#*after write, iclass 15, count 0 2006.168.07:56:32.62#ibcon#*before return 0, iclass 15, count 0 2006.168.07:56:32.62#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.168.07:56:32.62#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.168.07:56:32.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.168.07:56:32.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.168.07:56:32.62$vc4f8/vabw=wide 2006.168.07:56:32.62#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.168.07:56:32.62#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.168.07:56:32.62#ibcon#ireg 8 cls_cnt 0 2006.168.07:56:32.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:56:32.62#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:56:32.62#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:56:32.62#ibcon#enter wrdev, iclass 17, count 0 2006.168.07:56:32.62#ibcon#first serial, iclass 17, count 0 2006.168.07:56:32.62#ibcon#enter sib2, iclass 17, count 0 2006.168.07:56:32.62#ibcon#flushed, iclass 17, count 0 2006.168.07:56:32.62#ibcon#about to write, iclass 17, count 0 2006.168.07:56:32.62#ibcon#wrote, iclass 17, count 0 2006.168.07:56:32.62#ibcon#about to read 3, iclass 17, count 0 2006.168.07:56:32.64#ibcon#read 3, iclass 17, count 0 2006.168.07:56:32.64#ibcon#about to read 4, iclass 17, count 0 2006.168.07:56:32.64#ibcon#read 4, iclass 17, count 0 2006.168.07:56:32.64#ibcon#about to read 5, iclass 17, count 0 2006.168.07:56:32.64#ibcon#read 5, iclass 17, count 0 2006.168.07:56:32.64#ibcon#about to read 6, iclass 17, count 0 2006.168.07:56:32.64#ibcon#read 6, iclass 17, count 0 2006.168.07:56:32.64#ibcon#end of sib2, iclass 17, count 0 2006.168.07:56:32.64#ibcon#*mode == 0, iclass 17, count 0 2006.168.07:56:32.64#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.168.07:56:32.64#ibcon#[25=BW32\r\n] 2006.168.07:56:32.64#ibcon#*before write, iclass 17, count 0 2006.168.07:56:32.64#ibcon#enter sib2, iclass 17, count 0 2006.168.07:56:32.64#ibcon#flushed, iclass 17, count 0 2006.168.07:56:32.64#ibcon#about to write, iclass 17, count 0 2006.168.07:56:32.64#ibcon#wrote, iclass 17, count 0 2006.168.07:56:32.64#ibcon#about to read 3, iclass 17, count 0 2006.168.07:56:32.67#ibcon#read 3, iclass 17, count 0 2006.168.07:56:32.67#ibcon#about to read 4, iclass 17, count 0 2006.168.07:56:32.67#ibcon#read 4, iclass 17, count 0 2006.168.07:56:32.67#ibcon#about to read 5, iclass 17, count 0 2006.168.07:56:32.67#ibcon#read 5, iclass 17, count 0 2006.168.07:56:32.67#ibcon#about to read 6, iclass 17, count 0 2006.168.07:56:32.67#ibcon#read 6, iclass 17, count 0 2006.168.07:56:32.67#ibcon#end of sib2, iclass 17, count 0 2006.168.07:56:32.67#ibcon#*after write, iclass 17, count 0 2006.168.07:56:32.67#ibcon#*before return 0, iclass 17, count 0 2006.168.07:56:32.67#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:56:32.67#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.168.07:56:32.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.168.07:56:32.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.168.07:56:32.67$vc4f8/vbbw=wide 2006.168.07:56:32.67#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.168.07:56:32.67#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.168.07:56:32.67#ibcon#ireg 8 cls_cnt 0 2006.168.07:56:32.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:56:32.74#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:56:32.74#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:56:32.74#ibcon#enter wrdev, iclass 19, count 0 2006.168.07:56:32.74#ibcon#first serial, iclass 19, count 0 2006.168.07:56:32.74#ibcon#enter sib2, iclass 19, count 0 2006.168.07:56:32.74#ibcon#flushed, iclass 19, count 0 2006.168.07:56:32.74#ibcon#about to write, iclass 19, count 0 2006.168.07:56:32.74#ibcon#wrote, iclass 19, count 0 2006.168.07:56:32.74#ibcon#about to read 3, iclass 19, count 0 2006.168.07:56:32.76#ibcon#read 3, iclass 19, count 0 2006.168.07:56:32.76#ibcon#about to read 4, iclass 19, count 0 2006.168.07:56:32.76#ibcon#read 4, iclass 19, count 0 2006.168.07:56:32.76#ibcon#about to read 5, iclass 19, count 0 2006.168.07:56:32.76#ibcon#read 5, iclass 19, count 0 2006.168.07:56:32.76#ibcon#about to read 6, iclass 19, count 0 2006.168.07:56:32.76#ibcon#read 6, iclass 19, count 0 2006.168.07:56:32.76#ibcon#end of sib2, iclass 19, count 0 2006.168.07:56:32.76#ibcon#*mode == 0, iclass 19, count 0 2006.168.07:56:32.76#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.168.07:56:32.76#ibcon#[27=BW32\r\n] 2006.168.07:56:32.76#ibcon#*before write, iclass 19, count 0 2006.168.07:56:32.76#ibcon#enter sib2, iclass 19, count 0 2006.168.07:56:32.76#ibcon#flushed, iclass 19, count 0 2006.168.07:56:32.76#ibcon#about to write, iclass 19, count 0 2006.168.07:56:32.76#ibcon#wrote, iclass 19, count 0 2006.168.07:56:32.76#ibcon#about to read 3, iclass 19, count 0 2006.168.07:56:32.79#ibcon#read 3, iclass 19, count 0 2006.168.07:56:32.79#ibcon#about to read 4, iclass 19, count 0 2006.168.07:56:32.79#ibcon#read 4, iclass 19, count 0 2006.168.07:56:32.79#ibcon#about to read 5, iclass 19, count 0 2006.168.07:56:32.79#ibcon#read 5, iclass 19, count 0 2006.168.07:56:32.79#ibcon#about to read 6, iclass 19, count 0 2006.168.07:56:32.79#ibcon#read 6, iclass 19, count 0 2006.168.07:56:32.79#ibcon#end of sib2, iclass 19, count 0 2006.168.07:56:32.79#ibcon#*after write, iclass 19, count 0 2006.168.07:56:32.79#ibcon#*before return 0, iclass 19, count 0 2006.168.07:56:32.79#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:56:32.79#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.168.07:56:32.79#ibcon#about to clear, iclass 19 cls_cnt 0 2006.168.07:56:32.79#ibcon#cleared, iclass 19 cls_cnt 0 2006.168.07:56:32.79$4f8m12a/ifd4f 2006.168.07:56:32.79$ifd4f/lo= 2006.168.07:56:32.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.07:56:32.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.07:56:32.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.07:56:32.79$ifd4f/patch= 2006.168.07:56:32.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.07:56:32.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.07:56:32.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.07:56:32.79$4f8m12a/"form=m,16.000,1:2 2006.168.07:56:32.79$4f8m12a/"tpicd 2006.168.07:56:32.79$4f8m12a/echo=off 2006.168.07:56:32.79$4f8m12a/xlog=off 2006.168.07:56:32.79:!2006.168.07:58:40 2006.168.07:56:56.14#trakl#Source acquired 2006.168.07:56:56.14#flagr#flagr/antenna,acquired 2006.168.07:58:40.00:preob 2006.168.07:58:40.14/onsource/TRACKING 2006.168.07:58:40.14:!2006.168.07:58:50 2006.168.07:58:50.00:data_valid=on 2006.168.07:58:50.00:midob 2006.168.07:58:50.14/onsource/TRACKING 2006.168.07:58:50.14/wx/27.12,1004.6,75 2006.168.07:58:50.32/cable/+6.4725E-03 2006.168.07:58:51.41/va/01,08,usb,yes,29,31 2006.168.07:58:51.41/va/02,07,usb,yes,29,31 2006.168.07:58:51.41/va/03,06,usb,yes,31,31 2006.168.07:58:51.41/va/04,07,usb,yes,30,32 2006.168.07:58:51.41/va/05,07,usb,yes,30,32 2006.168.07:58:51.41/va/06,06,usb,yes,29,29 2006.168.07:58:51.41/va/07,06,usb,yes,29,29 2006.168.07:58:51.41/va/08,07,usb,yes,28,27 2006.168.07:58:51.64/valo/01,532.99,yes,locked 2006.168.07:58:51.64/valo/02,572.99,yes,locked 2006.168.07:58:51.64/valo/03,672.99,yes,locked 2006.168.07:58:51.64/valo/04,832.99,yes,locked 2006.168.07:58:51.64/valo/05,652.99,yes,locked 2006.168.07:58:51.64/valo/06,772.99,yes,locked 2006.168.07:58:51.64/valo/07,832.99,yes,locked 2006.168.07:58:51.64/valo/08,852.99,yes,locked 2006.168.07:58:52.73/vb/01,04,usb,yes,29,28 2006.168.07:58:52.73/vb/02,04,usb,yes,31,32 2006.168.07:58:52.73/vb/03,04,usb,yes,27,31 2006.168.07:58:52.73/vb/04,04,usb,yes,28,28 2006.168.07:58:52.73/vb/05,04,usb,yes,27,31 2006.168.07:58:52.73/vb/06,04,usb,yes,28,30 2006.168.07:58:52.73/vb/07,04,usb,yes,30,29 2006.168.07:58:52.73/vb/08,04,usb,yes,27,31 2006.168.07:58:52.96/vblo/01,632.99,yes,locked 2006.168.07:58:52.96/vblo/02,640.99,yes,locked 2006.168.07:58:52.96/vblo/03,656.99,yes,locked 2006.168.07:58:52.96/vblo/04,712.99,yes,locked 2006.168.07:58:52.96/vblo/05,744.99,yes,locked 2006.168.07:58:52.96/vblo/06,752.99,yes,locked 2006.168.07:58:52.96/vblo/07,734.99,yes,locked 2006.168.07:58:52.96/vblo/08,744.99,yes,locked 2006.168.07:58:53.11/vabw/8 2006.168.07:58:53.26/vbbw/8 2006.168.07:58:53.35/xfe/off,on,14.5 2006.168.07:58:53.73/ifatt/23,28,28,28 2006.168.07:58:54.07/fmout-gps/S +4.19E-07 2006.168.07:58:54.15:!2006.168.07:59:50 2006.168.07:59:50.01:data_valid=off 2006.168.07:59:50.02:postob 2006.168.07:59:50.13/cable/+6.4707E-03 2006.168.07:59:50.14/wx/27.09,1004.6,75 2006.168.07:59:51.08/fmout-gps/S +4.20E-07 2006.168.07:59:51.09:scan_name=168-0801,k06168,60 2006.168.07:59:51.09:source=1418+546,141946.60,542314.8,2000.0,cw 2006.168.07:59:51.14#flagr#flagr/antenna,new-source 2006.168.07:59:52.14:checkk5 2006.168.07:59:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.168.07:59:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.168.07:59:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.168.07:59:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.168.07:59:54.02/chk_obsdata//k5ts1/T1680758??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:59:54.39/chk_obsdata//k5ts2/T1680758??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:59:54.77/chk_obsdata//k5ts3/T1680758??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:59:55.14/chk_obsdata//k5ts4/T1680758??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.07:59:55.83/k5log//k5ts1_log_newline 2006.168.07:59:56.51/k5log//k5ts2_log_newline 2006.168.07:59:57.20/k5log//k5ts3_log_newline 2006.168.07:59:57.89/k5log//k5ts4_log_newline 2006.168.07:59:57.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.07:59:57.92:4f8m12a=2 2006.168.07:59:57.92$4f8m12a/echo=on 2006.168.07:59:57.92$4f8m12a/pcalon 2006.168.07:59:57.92$pcalon/"no phase cal control is implemented here 2006.168.07:59:57.92$4f8m12a/"tpicd=stop 2006.168.07:59:57.92$4f8m12a/vc4f8 2006.168.07:59:57.92$vc4f8/valo=1,532.99 2006.168.07:59:57.92#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.168.07:59:57.92#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.168.07:59:57.92#ibcon#ireg 17 cls_cnt 0 2006.168.07:59:57.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:59:57.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:59:57.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:59:57.92#ibcon#enter wrdev, iclass 30, count 0 2006.168.07:59:57.92#ibcon#first serial, iclass 30, count 0 2006.168.07:59:57.92#ibcon#enter sib2, iclass 30, count 0 2006.168.07:59:57.92#ibcon#flushed, iclass 30, count 0 2006.168.07:59:57.92#ibcon#about to write, iclass 30, count 0 2006.168.07:59:57.92#ibcon#wrote, iclass 30, count 0 2006.168.07:59:57.92#ibcon#about to read 3, iclass 30, count 0 2006.168.07:59:57.97#ibcon#read 3, iclass 30, count 0 2006.168.07:59:57.97#ibcon#about to read 4, iclass 30, count 0 2006.168.07:59:57.97#ibcon#read 4, iclass 30, count 0 2006.168.07:59:57.97#ibcon#about to read 5, iclass 30, count 0 2006.168.07:59:57.97#ibcon#read 5, iclass 30, count 0 2006.168.07:59:57.97#ibcon#about to read 6, iclass 30, count 0 2006.168.07:59:57.97#ibcon#read 6, iclass 30, count 0 2006.168.07:59:57.97#ibcon#end of sib2, iclass 30, count 0 2006.168.07:59:57.97#ibcon#*mode == 0, iclass 30, count 0 2006.168.07:59:57.97#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.168.07:59:57.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.07:59:57.97#ibcon#*before write, iclass 30, count 0 2006.168.07:59:57.97#ibcon#enter sib2, iclass 30, count 0 2006.168.07:59:57.97#ibcon#flushed, iclass 30, count 0 2006.168.07:59:57.97#ibcon#about to write, iclass 30, count 0 2006.168.07:59:57.97#ibcon#wrote, iclass 30, count 0 2006.168.07:59:57.97#ibcon#about to read 3, iclass 30, count 0 2006.168.07:59:58.01#ibcon#read 3, iclass 30, count 0 2006.168.07:59:58.01#ibcon#about to read 4, iclass 30, count 0 2006.168.07:59:58.01#ibcon#read 4, iclass 30, count 0 2006.168.07:59:58.01#ibcon#about to read 5, iclass 30, count 0 2006.168.07:59:58.01#ibcon#read 5, iclass 30, count 0 2006.168.07:59:58.01#ibcon#about to read 6, iclass 30, count 0 2006.168.07:59:58.01#ibcon#read 6, iclass 30, count 0 2006.168.07:59:58.01#ibcon#end of sib2, iclass 30, count 0 2006.168.07:59:58.01#ibcon#*after write, iclass 30, count 0 2006.168.07:59:58.01#ibcon#*before return 0, iclass 30, count 0 2006.168.07:59:58.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:59:58.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.168.07:59:58.01#ibcon#about to clear, iclass 30 cls_cnt 0 2006.168.07:59:58.01#ibcon#cleared, iclass 30 cls_cnt 0 2006.168.07:59:58.01$vc4f8/va=1,8 2006.168.07:59:58.01#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.168.07:59:58.01#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.168.07:59:58.01#ibcon#ireg 11 cls_cnt 2 2006.168.07:59:58.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:59:58.01#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:59:58.01#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:59:58.01#ibcon#enter wrdev, iclass 32, count 2 2006.168.07:59:58.01#ibcon#first serial, iclass 32, count 2 2006.168.07:59:58.01#ibcon#enter sib2, iclass 32, count 2 2006.168.07:59:58.01#ibcon#flushed, iclass 32, count 2 2006.168.07:59:58.01#ibcon#about to write, iclass 32, count 2 2006.168.07:59:58.01#ibcon#wrote, iclass 32, count 2 2006.168.07:59:58.01#ibcon#about to read 3, iclass 32, count 2 2006.168.07:59:58.04#ibcon#read 3, iclass 32, count 2 2006.168.07:59:58.04#ibcon#about to read 4, iclass 32, count 2 2006.168.07:59:58.04#ibcon#read 4, iclass 32, count 2 2006.168.07:59:58.04#ibcon#about to read 5, iclass 32, count 2 2006.168.07:59:58.04#ibcon#read 5, iclass 32, count 2 2006.168.07:59:58.04#ibcon#about to read 6, iclass 32, count 2 2006.168.07:59:58.04#ibcon#read 6, iclass 32, count 2 2006.168.07:59:58.04#ibcon#end of sib2, iclass 32, count 2 2006.168.07:59:58.04#ibcon#*mode == 0, iclass 32, count 2 2006.168.07:59:58.04#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.168.07:59:58.04#ibcon#[25=AT01-08\r\n] 2006.168.07:59:58.04#ibcon#*before write, iclass 32, count 2 2006.168.07:59:58.04#ibcon#enter sib2, iclass 32, count 2 2006.168.07:59:58.04#ibcon#flushed, iclass 32, count 2 2006.168.07:59:58.04#ibcon#about to write, iclass 32, count 2 2006.168.07:59:58.04#ibcon#wrote, iclass 32, count 2 2006.168.07:59:58.04#ibcon#about to read 3, iclass 32, count 2 2006.168.07:59:58.07#ibcon#read 3, iclass 32, count 2 2006.168.07:59:58.07#ibcon#about to read 4, iclass 32, count 2 2006.168.07:59:58.07#ibcon#read 4, iclass 32, count 2 2006.168.07:59:58.07#ibcon#about to read 5, iclass 32, count 2 2006.168.07:59:58.07#ibcon#read 5, iclass 32, count 2 2006.168.07:59:58.07#ibcon#about to read 6, iclass 32, count 2 2006.168.07:59:58.07#ibcon#read 6, iclass 32, count 2 2006.168.07:59:58.07#ibcon#end of sib2, iclass 32, count 2 2006.168.07:59:58.07#ibcon#*after write, iclass 32, count 2 2006.168.07:59:58.07#ibcon#*before return 0, iclass 32, count 2 2006.168.07:59:58.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:59:58.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.168.07:59:58.07#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.168.07:59:58.07#ibcon#ireg 7 cls_cnt 0 2006.168.07:59:58.07#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:59:58.19#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:59:58.19#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:59:58.19#ibcon#enter wrdev, iclass 32, count 0 2006.168.07:59:58.19#ibcon#first serial, iclass 32, count 0 2006.168.07:59:58.19#ibcon#enter sib2, iclass 32, count 0 2006.168.07:59:58.19#ibcon#flushed, iclass 32, count 0 2006.168.07:59:58.19#ibcon#about to write, iclass 32, count 0 2006.168.07:59:58.19#ibcon#wrote, iclass 32, count 0 2006.168.07:59:58.19#ibcon#about to read 3, iclass 32, count 0 2006.168.07:59:58.21#ibcon#read 3, iclass 32, count 0 2006.168.07:59:58.21#ibcon#about to read 4, iclass 32, count 0 2006.168.07:59:58.21#ibcon#read 4, iclass 32, count 0 2006.168.07:59:58.21#ibcon#about to read 5, iclass 32, count 0 2006.168.07:59:58.21#ibcon#read 5, iclass 32, count 0 2006.168.07:59:58.21#ibcon#about to read 6, iclass 32, count 0 2006.168.07:59:58.21#ibcon#read 6, iclass 32, count 0 2006.168.07:59:58.21#ibcon#end of sib2, iclass 32, count 0 2006.168.07:59:58.21#ibcon#*mode == 0, iclass 32, count 0 2006.168.07:59:58.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.168.07:59:58.21#ibcon#[25=USB\r\n] 2006.168.07:59:58.21#ibcon#*before write, iclass 32, count 0 2006.168.07:59:58.21#ibcon#enter sib2, iclass 32, count 0 2006.168.07:59:58.21#ibcon#flushed, iclass 32, count 0 2006.168.07:59:58.21#ibcon#about to write, iclass 32, count 0 2006.168.07:59:58.21#ibcon#wrote, iclass 32, count 0 2006.168.07:59:58.21#ibcon#about to read 3, iclass 32, count 0 2006.168.07:59:58.24#ibcon#read 3, iclass 32, count 0 2006.168.07:59:58.24#ibcon#about to read 4, iclass 32, count 0 2006.168.07:59:58.24#ibcon#read 4, iclass 32, count 0 2006.168.07:59:58.24#ibcon#about to read 5, iclass 32, count 0 2006.168.07:59:58.24#ibcon#read 5, iclass 32, count 0 2006.168.07:59:58.24#ibcon#about to read 6, iclass 32, count 0 2006.168.07:59:58.24#ibcon#read 6, iclass 32, count 0 2006.168.07:59:58.24#ibcon#end of sib2, iclass 32, count 0 2006.168.07:59:58.24#ibcon#*after write, iclass 32, count 0 2006.168.07:59:58.24#ibcon#*before return 0, iclass 32, count 0 2006.168.07:59:58.24#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:59:58.24#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.168.07:59:58.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.168.07:59:58.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.168.07:59:58.24$vc4f8/valo=2,572.99 2006.168.07:59:58.24#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.168.07:59:58.24#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.168.07:59:58.24#ibcon#ireg 17 cls_cnt 0 2006.168.07:59:58.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:59:58.24#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:59:58.24#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:59:58.24#ibcon#enter wrdev, iclass 34, count 0 2006.168.07:59:58.24#ibcon#first serial, iclass 34, count 0 2006.168.07:59:58.24#ibcon#enter sib2, iclass 34, count 0 2006.168.07:59:58.24#ibcon#flushed, iclass 34, count 0 2006.168.07:59:58.24#ibcon#about to write, iclass 34, count 0 2006.168.07:59:58.24#ibcon#wrote, iclass 34, count 0 2006.168.07:59:58.24#ibcon#about to read 3, iclass 34, count 0 2006.168.07:59:58.26#ibcon#read 3, iclass 34, count 0 2006.168.07:59:58.26#ibcon#about to read 4, iclass 34, count 0 2006.168.07:59:58.26#ibcon#read 4, iclass 34, count 0 2006.168.07:59:58.26#ibcon#about to read 5, iclass 34, count 0 2006.168.07:59:58.26#ibcon#read 5, iclass 34, count 0 2006.168.07:59:58.26#ibcon#about to read 6, iclass 34, count 0 2006.168.07:59:58.26#ibcon#read 6, iclass 34, count 0 2006.168.07:59:58.26#ibcon#end of sib2, iclass 34, count 0 2006.168.07:59:58.26#ibcon#*mode == 0, iclass 34, count 0 2006.168.07:59:58.26#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.168.07:59:58.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.07:59:58.26#ibcon#*before write, iclass 34, count 0 2006.168.07:59:58.26#ibcon#enter sib2, iclass 34, count 0 2006.168.07:59:58.26#ibcon#flushed, iclass 34, count 0 2006.168.07:59:58.26#ibcon#about to write, iclass 34, count 0 2006.168.07:59:58.26#ibcon#wrote, iclass 34, count 0 2006.168.07:59:58.26#ibcon#about to read 3, iclass 34, count 0 2006.168.07:59:58.30#ibcon#read 3, iclass 34, count 0 2006.168.07:59:58.30#ibcon#about to read 4, iclass 34, count 0 2006.168.07:59:58.30#ibcon#read 4, iclass 34, count 0 2006.168.07:59:58.30#ibcon#about to read 5, iclass 34, count 0 2006.168.07:59:58.30#ibcon#read 5, iclass 34, count 0 2006.168.07:59:58.30#ibcon#about to read 6, iclass 34, count 0 2006.168.07:59:58.30#ibcon#read 6, iclass 34, count 0 2006.168.07:59:58.30#ibcon#end of sib2, iclass 34, count 0 2006.168.07:59:58.30#ibcon#*after write, iclass 34, count 0 2006.168.07:59:58.30#ibcon#*before return 0, iclass 34, count 0 2006.168.07:59:58.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:59:58.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.168.07:59:58.30#ibcon#about to clear, iclass 34 cls_cnt 0 2006.168.07:59:58.30#ibcon#cleared, iclass 34 cls_cnt 0 2006.168.07:59:58.30$vc4f8/va=2,7 2006.168.07:59:58.30#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.168.07:59:58.30#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.168.07:59:58.30#ibcon#ireg 11 cls_cnt 2 2006.168.07:59:58.30#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:59:58.37#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:59:58.37#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:59:58.37#ibcon#enter wrdev, iclass 36, count 2 2006.168.07:59:58.37#ibcon#first serial, iclass 36, count 2 2006.168.07:59:58.37#ibcon#enter sib2, iclass 36, count 2 2006.168.07:59:58.37#ibcon#flushed, iclass 36, count 2 2006.168.07:59:58.37#ibcon#about to write, iclass 36, count 2 2006.168.07:59:58.37#ibcon#wrote, iclass 36, count 2 2006.168.07:59:58.37#ibcon#about to read 3, iclass 36, count 2 2006.168.07:59:58.38#ibcon#read 3, iclass 36, count 2 2006.168.07:59:58.38#ibcon#about to read 4, iclass 36, count 2 2006.168.07:59:58.38#ibcon#read 4, iclass 36, count 2 2006.168.07:59:58.38#ibcon#about to read 5, iclass 36, count 2 2006.168.07:59:58.38#ibcon#read 5, iclass 36, count 2 2006.168.07:59:58.38#ibcon#about to read 6, iclass 36, count 2 2006.168.07:59:58.38#ibcon#read 6, iclass 36, count 2 2006.168.07:59:58.38#ibcon#end of sib2, iclass 36, count 2 2006.168.07:59:58.38#ibcon#*mode == 0, iclass 36, count 2 2006.168.07:59:58.38#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.168.07:59:58.38#ibcon#[25=AT02-07\r\n] 2006.168.07:59:58.38#ibcon#*before write, iclass 36, count 2 2006.168.07:59:58.38#ibcon#enter sib2, iclass 36, count 2 2006.168.07:59:58.38#ibcon#flushed, iclass 36, count 2 2006.168.07:59:58.38#ibcon#about to write, iclass 36, count 2 2006.168.07:59:58.38#ibcon#wrote, iclass 36, count 2 2006.168.07:59:58.38#ibcon#about to read 3, iclass 36, count 2 2006.168.07:59:58.41#ibcon#read 3, iclass 36, count 2 2006.168.07:59:58.41#ibcon#about to read 4, iclass 36, count 2 2006.168.07:59:58.41#ibcon#read 4, iclass 36, count 2 2006.168.07:59:58.41#ibcon#about to read 5, iclass 36, count 2 2006.168.07:59:58.41#ibcon#read 5, iclass 36, count 2 2006.168.07:59:58.41#ibcon#about to read 6, iclass 36, count 2 2006.168.07:59:58.41#ibcon#read 6, iclass 36, count 2 2006.168.07:59:58.41#ibcon#end of sib2, iclass 36, count 2 2006.168.07:59:58.41#ibcon#*after write, iclass 36, count 2 2006.168.07:59:58.41#ibcon#*before return 0, iclass 36, count 2 2006.168.07:59:58.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:59:58.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.168.07:59:58.41#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.168.07:59:58.41#ibcon#ireg 7 cls_cnt 0 2006.168.07:59:58.41#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:59:58.53#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:59:58.53#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:59:58.53#ibcon#enter wrdev, iclass 36, count 0 2006.168.07:59:58.53#ibcon#first serial, iclass 36, count 0 2006.168.07:59:58.53#ibcon#enter sib2, iclass 36, count 0 2006.168.07:59:58.53#ibcon#flushed, iclass 36, count 0 2006.168.07:59:58.53#ibcon#about to write, iclass 36, count 0 2006.168.07:59:58.53#ibcon#wrote, iclass 36, count 0 2006.168.07:59:58.53#ibcon#about to read 3, iclass 36, count 0 2006.168.07:59:58.55#ibcon#read 3, iclass 36, count 0 2006.168.07:59:58.55#ibcon#about to read 4, iclass 36, count 0 2006.168.07:59:58.55#ibcon#read 4, iclass 36, count 0 2006.168.07:59:58.55#ibcon#about to read 5, iclass 36, count 0 2006.168.07:59:58.55#ibcon#read 5, iclass 36, count 0 2006.168.07:59:58.55#ibcon#about to read 6, iclass 36, count 0 2006.168.07:59:58.55#ibcon#read 6, iclass 36, count 0 2006.168.07:59:58.55#ibcon#end of sib2, iclass 36, count 0 2006.168.07:59:58.55#ibcon#*mode == 0, iclass 36, count 0 2006.168.07:59:58.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.168.07:59:58.55#ibcon#[25=USB\r\n] 2006.168.07:59:58.55#ibcon#*before write, iclass 36, count 0 2006.168.07:59:58.55#ibcon#enter sib2, iclass 36, count 0 2006.168.07:59:58.55#ibcon#flushed, iclass 36, count 0 2006.168.07:59:58.55#ibcon#about to write, iclass 36, count 0 2006.168.07:59:58.55#ibcon#wrote, iclass 36, count 0 2006.168.07:59:58.55#ibcon#about to read 3, iclass 36, count 0 2006.168.07:59:58.56#abcon#<5=/08 1.4 4.3 27.08 741004.6\r\n> 2006.168.07:59:58.58#abcon#{5=INTERFACE CLEAR} 2006.168.07:59:58.58#ibcon#read 3, iclass 36, count 0 2006.168.07:59:58.58#ibcon#about to read 4, iclass 36, count 0 2006.168.07:59:58.58#ibcon#read 4, iclass 36, count 0 2006.168.07:59:58.58#ibcon#about to read 5, iclass 36, count 0 2006.168.07:59:58.58#ibcon#read 5, iclass 36, count 0 2006.168.07:59:58.58#ibcon#about to read 6, iclass 36, count 0 2006.168.07:59:58.58#ibcon#read 6, iclass 36, count 0 2006.168.07:59:58.58#ibcon#end of sib2, iclass 36, count 0 2006.168.07:59:58.58#ibcon#*after write, iclass 36, count 0 2006.168.07:59:58.58#ibcon#*before return 0, iclass 36, count 0 2006.168.07:59:58.58#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:59:58.58#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.168.07:59:58.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.168.07:59:58.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.168.07:59:58.58$vc4f8/valo=3,672.99 2006.168.07:59:58.58#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.168.07:59:58.58#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.168.07:59:58.58#ibcon#ireg 17 cls_cnt 0 2006.168.07:59:58.58#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:59:58.58#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:59:58.58#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:59:58.58#ibcon#enter wrdev, iclass 3, count 0 2006.168.07:59:58.58#ibcon#first serial, iclass 3, count 0 2006.168.07:59:58.58#ibcon#enter sib2, iclass 3, count 0 2006.168.07:59:58.58#ibcon#flushed, iclass 3, count 0 2006.168.07:59:58.58#ibcon#about to write, iclass 3, count 0 2006.168.07:59:58.58#ibcon#wrote, iclass 3, count 0 2006.168.07:59:58.58#ibcon#about to read 3, iclass 3, count 0 2006.168.07:59:58.60#ibcon#read 3, iclass 3, count 0 2006.168.07:59:58.60#ibcon#about to read 4, iclass 3, count 0 2006.168.07:59:58.60#ibcon#read 4, iclass 3, count 0 2006.168.07:59:58.60#ibcon#about to read 5, iclass 3, count 0 2006.168.07:59:58.60#ibcon#read 5, iclass 3, count 0 2006.168.07:59:58.60#ibcon#about to read 6, iclass 3, count 0 2006.168.07:59:58.60#ibcon#read 6, iclass 3, count 0 2006.168.07:59:58.60#ibcon#end of sib2, iclass 3, count 0 2006.168.07:59:58.60#ibcon#*mode == 0, iclass 3, count 0 2006.168.07:59:58.60#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.168.07:59:58.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.07:59:58.60#ibcon#*before write, iclass 3, count 0 2006.168.07:59:58.60#ibcon#enter sib2, iclass 3, count 0 2006.168.07:59:58.60#ibcon#flushed, iclass 3, count 0 2006.168.07:59:58.60#ibcon#about to write, iclass 3, count 0 2006.168.07:59:58.60#ibcon#wrote, iclass 3, count 0 2006.168.07:59:58.60#ibcon#about to read 3, iclass 3, count 0 2006.168.07:59:58.64#abcon#[5=S1D000X0/0*\r\n] 2006.168.07:59:58.64#ibcon#read 3, iclass 3, count 0 2006.168.07:59:58.64#ibcon#about to read 4, iclass 3, count 0 2006.168.07:59:58.64#ibcon#read 4, iclass 3, count 0 2006.168.07:59:58.64#ibcon#about to read 5, iclass 3, count 0 2006.168.07:59:58.64#ibcon#read 5, iclass 3, count 0 2006.168.07:59:58.64#ibcon#about to read 6, iclass 3, count 0 2006.168.07:59:58.64#ibcon#read 6, iclass 3, count 0 2006.168.07:59:58.64#ibcon#end of sib2, iclass 3, count 0 2006.168.07:59:58.64#ibcon#*after write, iclass 3, count 0 2006.168.07:59:58.64#ibcon#*before return 0, iclass 3, count 0 2006.168.07:59:58.64#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:59:58.64#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.168.07:59:58.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.168.07:59:58.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.168.07:59:58.64$vc4f8/va=3,6 2006.168.07:59:58.64#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.168.07:59:58.64#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.168.07:59:58.64#ibcon#ireg 11 cls_cnt 2 2006.168.07:59:58.64#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:59:58.70#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:59:58.70#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:59:58.70#ibcon#enter wrdev, iclass 6, count 2 2006.168.07:59:58.70#ibcon#first serial, iclass 6, count 2 2006.168.07:59:58.70#ibcon#enter sib2, iclass 6, count 2 2006.168.07:59:58.70#ibcon#flushed, iclass 6, count 2 2006.168.07:59:58.70#ibcon#about to write, iclass 6, count 2 2006.168.07:59:58.70#ibcon#wrote, iclass 6, count 2 2006.168.07:59:58.70#ibcon#about to read 3, iclass 6, count 2 2006.168.07:59:58.72#ibcon#read 3, iclass 6, count 2 2006.168.07:59:58.72#ibcon#about to read 4, iclass 6, count 2 2006.168.07:59:58.72#ibcon#read 4, iclass 6, count 2 2006.168.07:59:58.72#ibcon#about to read 5, iclass 6, count 2 2006.168.07:59:58.72#ibcon#read 5, iclass 6, count 2 2006.168.07:59:58.72#ibcon#about to read 6, iclass 6, count 2 2006.168.07:59:58.72#ibcon#read 6, iclass 6, count 2 2006.168.07:59:58.72#ibcon#end of sib2, iclass 6, count 2 2006.168.07:59:58.72#ibcon#*mode == 0, iclass 6, count 2 2006.168.07:59:58.72#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.168.07:59:58.72#ibcon#[25=AT03-06\r\n] 2006.168.07:59:58.72#ibcon#*before write, iclass 6, count 2 2006.168.07:59:58.72#ibcon#enter sib2, iclass 6, count 2 2006.168.07:59:58.72#ibcon#flushed, iclass 6, count 2 2006.168.07:59:58.72#ibcon#about to write, iclass 6, count 2 2006.168.07:59:58.72#ibcon#wrote, iclass 6, count 2 2006.168.07:59:58.72#ibcon#about to read 3, iclass 6, count 2 2006.168.07:59:58.75#ibcon#read 3, iclass 6, count 2 2006.168.07:59:58.75#ibcon#about to read 4, iclass 6, count 2 2006.168.07:59:58.75#ibcon#read 4, iclass 6, count 2 2006.168.07:59:58.75#ibcon#about to read 5, iclass 6, count 2 2006.168.07:59:58.75#ibcon#read 5, iclass 6, count 2 2006.168.07:59:58.75#ibcon#about to read 6, iclass 6, count 2 2006.168.07:59:58.75#ibcon#read 6, iclass 6, count 2 2006.168.07:59:58.75#ibcon#end of sib2, iclass 6, count 2 2006.168.07:59:58.75#ibcon#*after write, iclass 6, count 2 2006.168.07:59:58.75#ibcon#*before return 0, iclass 6, count 2 2006.168.07:59:58.75#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:59:58.75#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.168.07:59:58.75#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.168.07:59:58.75#ibcon#ireg 7 cls_cnt 0 2006.168.07:59:58.75#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:59:58.87#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:59:58.87#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:59:58.87#ibcon#enter wrdev, iclass 6, count 0 2006.168.07:59:58.87#ibcon#first serial, iclass 6, count 0 2006.168.07:59:58.87#ibcon#enter sib2, iclass 6, count 0 2006.168.07:59:58.87#ibcon#flushed, iclass 6, count 0 2006.168.07:59:58.87#ibcon#about to write, iclass 6, count 0 2006.168.07:59:58.87#ibcon#wrote, iclass 6, count 0 2006.168.07:59:58.87#ibcon#about to read 3, iclass 6, count 0 2006.168.07:59:58.89#ibcon#read 3, iclass 6, count 0 2006.168.07:59:58.89#ibcon#about to read 4, iclass 6, count 0 2006.168.07:59:58.89#ibcon#read 4, iclass 6, count 0 2006.168.07:59:58.89#ibcon#about to read 5, iclass 6, count 0 2006.168.07:59:58.89#ibcon#read 5, iclass 6, count 0 2006.168.07:59:58.89#ibcon#about to read 6, iclass 6, count 0 2006.168.07:59:58.89#ibcon#read 6, iclass 6, count 0 2006.168.07:59:58.89#ibcon#end of sib2, iclass 6, count 0 2006.168.07:59:58.89#ibcon#*mode == 0, iclass 6, count 0 2006.168.07:59:58.89#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.168.07:59:58.89#ibcon#[25=USB\r\n] 2006.168.07:59:58.89#ibcon#*before write, iclass 6, count 0 2006.168.07:59:58.89#ibcon#enter sib2, iclass 6, count 0 2006.168.07:59:58.89#ibcon#flushed, iclass 6, count 0 2006.168.07:59:58.89#ibcon#about to write, iclass 6, count 0 2006.168.07:59:58.89#ibcon#wrote, iclass 6, count 0 2006.168.07:59:58.89#ibcon#about to read 3, iclass 6, count 0 2006.168.07:59:58.92#ibcon#read 3, iclass 6, count 0 2006.168.07:59:58.92#ibcon#about to read 4, iclass 6, count 0 2006.168.07:59:58.92#ibcon#read 4, iclass 6, count 0 2006.168.07:59:58.92#ibcon#about to read 5, iclass 6, count 0 2006.168.07:59:58.92#ibcon#read 5, iclass 6, count 0 2006.168.07:59:58.92#ibcon#about to read 6, iclass 6, count 0 2006.168.07:59:58.92#ibcon#read 6, iclass 6, count 0 2006.168.07:59:58.92#ibcon#end of sib2, iclass 6, count 0 2006.168.07:59:58.92#ibcon#*after write, iclass 6, count 0 2006.168.07:59:58.92#ibcon#*before return 0, iclass 6, count 0 2006.168.07:59:58.92#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:59:58.92#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.168.07:59:58.92#ibcon#about to clear, iclass 6 cls_cnt 0 2006.168.07:59:58.92#ibcon#cleared, iclass 6 cls_cnt 0 2006.168.07:59:58.92$vc4f8/valo=4,832.99 2006.168.07:59:58.92#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.168.07:59:58.92#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.168.07:59:58.92#ibcon#ireg 17 cls_cnt 0 2006.168.07:59:58.92#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:59:58.92#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:59:58.92#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:59:58.92#ibcon#enter wrdev, iclass 10, count 0 2006.168.07:59:58.92#ibcon#first serial, iclass 10, count 0 2006.168.07:59:58.92#ibcon#enter sib2, iclass 10, count 0 2006.168.07:59:58.92#ibcon#flushed, iclass 10, count 0 2006.168.07:59:58.92#ibcon#about to write, iclass 10, count 0 2006.168.07:59:58.92#ibcon#wrote, iclass 10, count 0 2006.168.07:59:58.92#ibcon#about to read 3, iclass 10, count 0 2006.168.07:59:58.94#ibcon#read 3, iclass 10, count 0 2006.168.07:59:58.94#ibcon#about to read 4, iclass 10, count 0 2006.168.07:59:58.94#ibcon#read 4, iclass 10, count 0 2006.168.07:59:58.94#ibcon#about to read 5, iclass 10, count 0 2006.168.07:59:58.94#ibcon#read 5, iclass 10, count 0 2006.168.07:59:58.94#ibcon#about to read 6, iclass 10, count 0 2006.168.07:59:58.94#ibcon#read 6, iclass 10, count 0 2006.168.07:59:58.94#ibcon#end of sib2, iclass 10, count 0 2006.168.07:59:58.94#ibcon#*mode == 0, iclass 10, count 0 2006.168.07:59:58.94#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.168.07:59:58.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.07:59:58.94#ibcon#*before write, iclass 10, count 0 2006.168.07:59:58.94#ibcon#enter sib2, iclass 10, count 0 2006.168.07:59:58.94#ibcon#flushed, iclass 10, count 0 2006.168.07:59:58.94#ibcon#about to write, iclass 10, count 0 2006.168.07:59:58.94#ibcon#wrote, iclass 10, count 0 2006.168.07:59:58.94#ibcon#about to read 3, iclass 10, count 0 2006.168.07:59:58.98#ibcon#read 3, iclass 10, count 0 2006.168.07:59:58.98#ibcon#about to read 4, iclass 10, count 0 2006.168.07:59:58.98#ibcon#read 4, iclass 10, count 0 2006.168.07:59:58.98#ibcon#about to read 5, iclass 10, count 0 2006.168.07:59:58.98#ibcon#read 5, iclass 10, count 0 2006.168.07:59:58.98#ibcon#about to read 6, iclass 10, count 0 2006.168.07:59:58.98#ibcon#read 6, iclass 10, count 0 2006.168.07:59:58.98#ibcon#end of sib2, iclass 10, count 0 2006.168.07:59:58.98#ibcon#*after write, iclass 10, count 0 2006.168.07:59:58.98#ibcon#*before return 0, iclass 10, count 0 2006.168.07:59:58.98#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:59:58.98#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.168.07:59:58.98#ibcon#about to clear, iclass 10 cls_cnt 0 2006.168.07:59:58.98#ibcon#cleared, iclass 10 cls_cnt 0 2006.168.07:59:58.98$vc4f8/va=4,7 2006.168.07:59:58.98#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.168.07:59:58.98#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.168.07:59:58.98#ibcon#ireg 11 cls_cnt 2 2006.168.07:59:58.98#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:59:59.04#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:59:59.04#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:59:59.04#ibcon#enter wrdev, iclass 12, count 2 2006.168.07:59:59.04#ibcon#first serial, iclass 12, count 2 2006.168.07:59:59.04#ibcon#enter sib2, iclass 12, count 2 2006.168.07:59:59.04#ibcon#flushed, iclass 12, count 2 2006.168.07:59:59.04#ibcon#about to write, iclass 12, count 2 2006.168.07:59:59.04#ibcon#wrote, iclass 12, count 2 2006.168.07:59:59.04#ibcon#about to read 3, iclass 12, count 2 2006.168.07:59:59.06#ibcon#read 3, iclass 12, count 2 2006.168.07:59:59.06#ibcon#about to read 4, iclass 12, count 2 2006.168.07:59:59.06#ibcon#read 4, iclass 12, count 2 2006.168.07:59:59.06#ibcon#about to read 5, iclass 12, count 2 2006.168.07:59:59.06#ibcon#read 5, iclass 12, count 2 2006.168.07:59:59.06#ibcon#about to read 6, iclass 12, count 2 2006.168.07:59:59.06#ibcon#read 6, iclass 12, count 2 2006.168.07:59:59.06#ibcon#end of sib2, iclass 12, count 2 2006.168.07:59:59.06#ibcon#*mode == 0, iclass 12, count 2 2006.168.07:59:59.06#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.168.07:59:59.06#ibcon#[25=AT04-07\r\n] 2006.168.07:59:59.06#ibcon#*before write, iclass 12, count 2 2006.168.07:59:59.06#ibcon#enter sib2, iclass 12, count 2 2006.168.07:59:59.06#ibcon#flushed, iclass 12, count 2 2006.168.07:59:59.06#ibcon#about to write, iclass 12, count 2 2006.168.07:59:59.06#ibcon#wrote, iclass 12, count 2 2006.168.07:59:59.06#ibcon#about to read 3, iclass 12, count 2 2006.168.07:59:59.09#ibcon#read 3, iclass 12, count 2 2006.168.07:59:59.09#ibcon#about to read 4, iclass 12, count 2 2006.168.07:59:59.09#ibcon#read 4, iclass 12, count 2 2006.168.07:59:59.09#ibcon#about to read 5, iclass 12, count 2 2006.168.07:59:59.09#ibcon#read 5, iclass 12, count 2 2006.168.07:59:59.09#ibcon#about to read 6, iclass 12, count 2 2006.168.07:59:59.09#ibcon#read 6, iclass 12, count 2 2006.168.07:59:59.09#ibcon#end of sib2, iclass 12, count 2 2006.168.07:59:59.09#ibcon#*after write, iclass 12, count 2 2006.168.07:59:59.09#ibcon#*before return 0, iclass 12, count 2 2006.168.07:59:59.09#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:59:59.09#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.168.07:59:59.09#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.168.07:59:59.09#ibcon#ireg 7 cls_cnt 0 2006.168.07:59:59.09#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:59:59.21#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:59:59.21#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:59:59.21#ibcon#enter wrdev, iclass 12, count 0 2006.168.07:59:59.21#ibcon#first serial, iclass 12, count 0 2006.168.07:59:59.21#ibcon#enter sib2, iclass 12, count 0 2006.168.07:59:59.21#ibcon#flushed, iclass 12, count 0 2006.168.07:59:59.21#ibcon#about to write, iclass 12, count 0 2006.168.07:59:59.21#ibcon#wrote, iclass 12, count 0 2006.168.07:59:59.21#ibcon#about to read 3, iclass 12, count 0 2006.168.07:59:59.23#ibcon#read 3, iclass 12, count 0 2006.168.07:59:59.23#ibcon#about to read 4, iclass 12, count 0 2006.168.07:59:59.23#ibcon#read 4, iclass 12, count 0 2006.168.07:59:59.23#ibcon#about to read 5, iclass 12, count 0 2006.168.07:59:59.23#ibcon#read 5, iclass 12, count 0 2006.168.07:59:59.23#ibcon#about to read 6, iclass 12, count 0 2006.168.07:59:59.23#ibcon#read 6, iclass 12, count 0 2006.168.07:59:59.23#ibcon#end of sib2, iclass 12, count 0 2006.168.07:59:59.23#ibcon#*mode == 0, iclass 12, count 0 2006.168.07:59:59.23#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.168.07:59:59.23#ibcon#[25=USB\r\n] 2006.168.07:59:59.23#ibcon#*before write, iclass 12, count 0 2006.168.07:59:59.23#ibcon#enter sib2, iclass 12, count 0 2006.168.07:59:59.23#ibcon#flushed, iclass 12, count 0 2006.168.07:59:59.23#ibcon#about to write, iclass 12, count 0 2006.168.07:59:59.23#ibcon#wrote, iclass 12, count 0 2006.168.07:59:59.23#ibcon#about to read 3, iclass 12, count 0 2006.168.07:59:59.26#ibcon#read 3, iclass 12, count 0 2006.168.07:59:59.26#ibcon#about to read 4, iclass 12, count 0 2006.168.07:59:59.26#ibcon#read 4, iclass 12, count 0 2006.168.07:59:59.26#ibcon#about to read 5, iclass 12, count 0 2006.168.07:59:59.26#ibcon#read 5, iclass 12, count 0 2006.168.07:59:59.26#ibcon#about to read 6, iclass 12, count 0 2006.168.07:59:59.26#ibcon#read 6, iclass 12, count 0 2006.168.07:59:59.26#ibcon#end of sib2, iclass 12, count 0 2006.168.07:59:59.26#ibcon#*after write, iclass 12, count 0 2006.168.07:59:59.26#ibcon#*before return 0, iclass 12, count 0 2006.168.07:59:59.26#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:59:59.26#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.168.07:59:59.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.168.07:59:59.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.168.07:59:59.26$vc4f8/valo=5,652.99 2006.168.07:59:59.26#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.168.07:59:59.26#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.168.07:59:59.26#ibcon#ireg 17 cls_cnt 0 2006.168.07:59:59.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:59:59.26#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:59:59.26#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:59:59.26#ibcon#enter wrdev, iclass 14, count 0 2006.168.07:59:59.26#ibcon#first serial, iclass 14, count 0 2006.168.07:59:59.26#ibcon#enter sib2, iclass 14, count 0 2006.168.07:59:59.26#ibcon#flushed, iclass 14, count 0 2006.168.07:59:59.26#ibcon#about to write, iclass 14, count 0 2006.168.07:59:59.26#ibcon#wrote, iclass 14, count 0 2006.168.07:59:59.26#ibcon#about to read 3, iclass 14, count 0 2006.168.07:59:59.28#ibcon#read 3, iclass 14, count 0 2006.168.07:59:59.28#ibcon#about to read 4, iclass 14, count 0 2006.168.07:59:59.28#ibcon#read 4, iclass 14, count 0 2006.168.07:59:59.28#ibcon#about to read 5, iclass 14, count 0 2006.168.07:59:59.28#ibcon#read 5, iclass 14, count 0 2006.168.07:59:59.28#ibcon#about to read 6, iclass 14, count 0 2006.168.07:59:59.28#ibcon#read 6, iclass 14, count 0 2006.168.07:59:59.28#ibcon#end of sib2, iclass 14, count 0 2006.168.07:59:59.28#ibcon#*mode == 0, iclass 14, count 0 2006.168.07:59:59.28#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.168.07:59:59.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.07:59:59.28#ibcon#*before write, iclass 14, count 0 2006.168.07:59:59.28#ibcon#enter sib2, iclass 14, count 0 2006.168.07:59:59.28#ibcon#flushed, iclass 14, count 0 2006.168.07:59:59.28#ibcon#about to write, iclass 14, count 0 2006.168.07:59:59.28#ibcon#wrote, iclass 14, count 0 2006.168.07:59:59.28#ibcon#about to read 3, iclass 14, count 0 2006.168.07:59:59.32#ibcon#read 3, iclass 14, count 0 2006.168.07:59:59.32#ibcon#about to read 4, iclass 14, count 0 2006.168.07:59:59.32#ibcon#read 4, iclass 14, count 0 2006.168.07:59:59.32#ibcon#about to read 5, iclass 14, count 0 2006.168.07:59:59.32#ibcon#read 5, iclass 14, count 0 2006.168.07:59:59.32#ibcon#about to read 6, iclass 14, count 0 2006.168.07:59:59.32#ibcon#read 6, iclass 14, count 0 2006.168.07:59:59.32#ibcon#end of sib2, iclass 14, count 0 2006.168.07:59:59.32#ibcon#*after write, iclass 14, count 0 2006.168.07:59:59.32#ibcon#*before return 0, iclass 14, count 0 2006.168.07:59:59.32#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:59:59.32#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.168.07:59:59.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.168.07:59:59.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.168.07:59:59.32$vc4f8/va=5,7 2006.168.07:59:59.32#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.168.07:59:59.32#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.168.07:59:59.32#ibcon#ireg 11 cls_cnt 2 2006.168.07:59:59.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:59:59.38#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:59:59.38#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:59:59.38#ibcon#enter wrdev, iclass 16, count 2 2006.168.07:59:59.38#ibcon#first serial, iclass 16, count 2 2006.168.07:59:59.38#ibcon#enter sib2, iclass 16, count 2 2006.168.07:59:59.38#ibcon#flushed, iclass 16, count 2 2006.168.07:59:59.38#ibcon#about to write, iclass 16, count 2 2006.168.07:59:59.38#ibcon#wrote, iclass 16, count 2 2006.168.07:59:59.38#ibcon#about to read 3, iclass 16, count 2 2006.168.07:59:59.40#ibcon#read 3, iclass 16, count 2 2006.168.07:59:59.40#ibcon#about to read 4, iclass 16, count 2 2006.168.07:59:59.40#ibcon#read 4, iclass 16, count 2 2006.168.07:59:59.40#ibcon#about to read 5, iclass 16, count 2 2006.168.07:59:59.40#ibcon#read 5, iclass 16, count 2 2006.168.07:59:59.40#ibcon#about to read 6, iclass 16, count 2 2006.168.07:59:59.40#ibcon#read 6, iclass 16, count 2 2006.168.07:59:59.40#ibcon#end of sib2, iclass 16, count 2 2006.168.07:59:59.40#ibcon#*mode == 0, iclass 16, count 2 2006.168.07:59:59.40#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.168.07:59:59.40#ibcon#[25=AT05-07\r\n] 2006.168.07:59:59.40#ibcon#*before write, iclass 16, count 2 2006.168.07:59:59.40#ibcon#enter sib2, iclass 16, count 2 2006.168.07:59:59.40#ibcon#flushed, iclass 16, count 2 2006.168.07:59:59.40#ibcon#about to write, iclass 16, count 2 2006.168.07:59:59.40#ibcon#wrote, iclass 16, count 2 2006.168.07:59:59.40#ibcon#about to read 3, iclass 16, count 2 2006.168.07:59:59.43#ibcon#read 3, iclass 16, count 2 2006.168.07:59:59.43#ibcon#about to read 4, iclass 16, count 2 2006.168.07:59:59.43#ibcon#read 4, iclass 16, count 2 2006.168.07:59:59.43#ibcon#about to read 5, iclass 16, count 2 2006.168.07:59:59.43#ibcon#read 5, iclass 16, count 2 2006.168.07:59:59.43#ibcon#about to read 6, iclass 16, count 2 2006.168.07:59:59.43#ibcon#read 6, iclass 16, count 2 2006.168.07:59:59.43#ibcon#end of sib2, iclass 16, count 2 2006.168.07:59:59.43#ibcon#*after write, iclass 16, count 2 2006.168.07:59:59.43#ibcon#*before return 0, iclass 16, count 2 2006.168.07:59:59.43#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:59:59.43#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.168.07:59:59.43#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.168.07:59:59.43#ibcon#ireg 7 cls_cnt 0 2006.168.07:59:59.43#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:59:59.55#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:59:59.55#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:59:59.55#ibcon#enter wrdev, iclass 16, count 0 2006.168.07:59:59.55#ibcon#first serial, iclass 16, count 0 2006.168.07:59:59.55#ibcon#enter sib2, iclass 16, count 0 2006.168.07:59:59.55#ibcon#flushed, iclass 16, count 0 2006.168.07:59:59.55#ibcon#about to write, iclass 16, count 0 2006.168.07:59:59.55#ibcon#wrote, iclass 16, count 0 2006.168.07:59:59.55#ibcon#about to read 3, iclass 16, count 0 2006.168.07:59:59.57#ibcon#read 3, iclass 16, count 0 2006.168.07:59:59.57#ibcon#about to read 4, iclass 16, count 0 2006.168.07:59:59.57#ibcon#read 4, iclass 16, count 0 2006.168.07:59:59.57#ibcon#about to read 5, iclass 16, count 0 2006.168.07:59:59.57#ibcon#read 5, iclass 16, count 0 2006.168.07:59:59.57#ibcon#about to read 6, iclass 16, count 0 2006.168.07:59:59.57#ibcon#read 6, iclass 16, count 0 2006.168.07:59:59.57#ibcon#end of sib2, iclass 16, count 0 2006.168.07:59:59.57#ibcon#*mode == 0, iclass 16, count 0 2006.168.07:59:59.57#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.168.07:59:59.57#ibcon#[25=USB\r\n] 2006.168.07:59:59.57#ibcon#*before write, iclass 16, count 0 2006.168.07:59:59.57#ibcon#enter sib2, iclass 16, count 0 2006.168.07:59:59.57#ibcon#flushed, iclass 16, count 0 2006.168.07:59:59.57#ibcon#about to write, iclass 16, count 0 2006.168.07:59:59.57#ibcon#wrote, iclass 16, count 0 2006.168.07:59:59.57#ibcon#about to read 3, iclass 16, count 0 2006.168.07:59:59.60#ibcon#read 3, iclass 16, count 0 2006.168.07:59:59.60#ibcon#about to read 4, iclass 16, count 0 2006.168.07:59:59.60#ibcon#read 4, iclass 16, count 0 2006.168.07:59:59.60#ibcon#about to read 5, iclass 16, count 0 2006.168.07:59:59.60#ibcon#read 5, iclass 16, count 0 2006.168.07:59:59.60#ibcon#about to read 6, iclass 16, count 0 2006.168.07:59:59.60#ibcon#read 6, iclass 16, count 0 2006.168.07:59:59.60#ibcon#end of sib2, iclass 16, count 0 2006.168.07:59:59.60#ibcon#*after write, iclass 16, count 0 2006.168.07:59:59.60#ibcon#*before return 0, iclass 16, count 0 2006.168.07:59:59.60#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:59:59.60#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.168.07:59:59.60#ibcon#about to clear, iclass 16 cls_cnt 0 2006.168.07:59:59.60#ibcon#cleared, iclass 16 cls_cnt 0 2006.168.07:59:59.60$vc4f8/valo=6,772.99 2006.168.07:59:59.60#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.168.07:59:59.60#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.168.07:59:59.60#ibcon#ireg 17 cls_cnt 0 2006.168.07:59:59.60#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:59:59.60#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:59:59.60#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:59:59.60#ibcon#enter wrdev, iclass 18, count 0 2006.168.07:59:59.60#ibcon#first serial, iclass 18, count 0 2006.168.07:59:59.60#ibcon#enter sib2, iclass 18, count 0 2006.168.07:59:59.60#ibcon#flushed, iclass 18, count 0 2006.168.07:59:59.60#ibcon#about to write, iclass 18, count 0 2006.168.07:59:59.60#ibcon#wrote, iclass 18, count 0 2006.168.07:59:59.60#ibcon#about to read 3, iclass 18, count 0 2006.168.07:59:59.62#ibcon#read 3, iclass 18, count 0 2006.168.07:59:59.62#ibcon#about to read 4, iclass 18, count 0 2006.168.07:59:59.62#ibcon#read 4, iclass 18, count 0 2006.168.07:59:59.62#ibcon#about to read 5, iclass 18, count 0 2006.168.07:59:59.62#ibcon#read 5, iclass 18, count 0 2006.168.07:59:59.62#ibcon#about to read 6, iclass 18, count 0 2006.168.07:59:59.62#ibcon#read 6, iclass 18, count 0 2006.168.07:59:59.62#ibcon#end of sib2, iclass 18, count 0 2006.168.07:59:59.62#ibcon#*mode == 0, iclass 18, count 0 2006.168.07:59:59.62#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.07:59:59.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.07:59:59.62#ibcon#*before write, iclass 18, count 0 2006.168.07:59:59.62#ibcon#enter sib2, iclass 18, count 0 2006.168.07:59:59.62#ibcon#flushed, iclass 18, count 0 2006.168.07:59:59.62#ibcon#about to write, iclass 18, count 0 2006.168.07:59:59.62#ibcon#wrote, iclass 18, count 0 2006.168.07:59:59.62#ibcon#about to read 3, iclass 18, count 0 2006.168.07:59:59.66#ibcon#read 3, iclass 18, count 0 2006.168.07:59:59.66#ibcon#about to read 4, iclass 18, count 0 2006.168.07:59:59.66#ibcon#read 4, iclass 18, count 0 2006.168.07:59:59.66#ibcon#about to read 5, iclass 18, count 0 2006.168.07:59:59.66#ibcon#read 5, iclass 18, count 0 2006.168.07:59:59.66#ibcon#about to read 6, iclass 18, count 0 2006.168.07:59:59.66#ibcon#read 6, iclass 18, count 0 2006.168.07:59:59.66#ibcon#end of sib2, iclass 18, count 0 2006.168.07:59:59.66#ibcon#*after write, iclass 18, count 0 2006.168.07:59:59.66#ibcon#*before return 0, iclass 18, count 0 2006.168.07:59:59.66#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:59:59.66#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.168.07:59:59.66#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.07:59:59.66#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.07:59:59.66$vc4f8/va=6,6 2006.168.07:59:59.66#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.168.07:59:59.66#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.168.07:59:59.66#ibcon#ireg 11 cls_cnt 2 2006.168.07:59:59.66#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:59:59.72#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:59:59.72#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:59:59.72#ibcon#enter wrdev, iclass 20, count 2 2006.168.07:59:59.72#ibcon#first serial, iclass 20, count 2 2006.168.07:59:59.72#ibcon#enter sib2, iclass 20, count 2 2006.168.07:59:59.72#ibcon#flushed, iclass 20, count 2 2006.168.07:59:59.72#ibcon#about to write, iclass 20, count 2 2006.168.07:59:59.72#ibcon#wrote, iclass 20, count 2 2006.168.07:59:59.72#ibcon#about to read 3, iclass 20, count 2 2006.168.07:59:59.74#ibcon#read 3, iclass 20, count 2 2006.168.07:59:59.74#ibcon#about to read 4, iclass 20, count 2 2006.168.07:59:59.74#ibcon#read 4, iclass 20, count 2 2006.168.07:59:59.74#ibcon#about to read 5, iclass 20, count 2 2006.168.07:59:59.74#ibcon#read 5, iclass 20, count 2 2006.168.07:59:59.74#ibcon#about to read 6, iclass 20, count 2 2006.168.07:59:59.74#ibcon#read 6, iclass 20, count 2 2006.168.07:59:59.74#ibcon#end of sib2, iclass 20, count 2 2006.168.07:59:59.74#ibcon#*mode == 0, iclass 20, count 2 2006.168.07:59:59.74#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.168.07:59:59.74#ibcon#[25=AT06-06\r\n] 2006.168.07:59:59.74#ibcon#*before write, iclass 20, count 2 2006.168.07:59:59.74#ibcon#enter sib2, iclass 20, count 2 2006.168.07:59:59.74#ibcon#flushed, iclass 20, count 2 2006.168.07:59:59.74#ibcon#about to write, iclass 20, count 2 2006.168.07:59:59.74#ibcon#wrote, iclass 20, count 2 2006.168.07:59:59.74#ibcon#about to read 3, iclass 20, count 2 2006.168.07:59:59.77#ibcon#read 3, iclass 20, count 2 2006.168.07:59:59.77#ibcon#about to read 4, iclass 20, count 2 2006.168.07:59:59.77#ibcon#read 4, iclass 20, count 2 2006.168.07:59:59.77#ibcon#about to read 5, iclass 20, count 2 2006.168.07:59:59.77#ibcon#read 5, iclass 20, count 2 2006.168.07:59:59.77#ibcon#about to read 6, iclass 20, count 2 2006.168.07:59:59.77#ibcon#read 6, iclass 20, count 2 2006.168.07:59:59.77#ibcon#end of sib2, iclass 20, count 2 2006.168.07:59:59.77#ibcon#*after write, iclass 20, count 2 2006.168.07:59:59.77#ibcon#*before return 0, iclass 20, count 2 2006.168.07:59:59.77#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:59:59.77#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.168.07:59:59.77#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.168.07:59:59.77#ibcon#ireg 7 cls_cnt 0 2006.168.07:59:59.77#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:59:59.89#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:59:59.89#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:59:59.89#ibcon#enter wrdev, iclass 20, count 0 2006.168.07:59:59.89#ibcon#first serial, iclass 20, count 0 2006.168.07:59:59.89#ibcon#enter sib2, iclass 20, count 0 2006.168.07:59:59.89#ibcon#flushed, iclass 20, count 0 2006.168.07:59:59.89#ibcon#about to write, iclass 20, count 0 2006.168.07:59:59.89#ibcon#wrote, iclass 20, count 0 2006.168.07:59:59.89#ibcon#about to read 3, iclass 20, count 0 2006.168.07:59:59.91#ibcon#read 3, iclass 20, count 0 2006.168.07:59:59.91#ibcon#about to read 4, iclass 20, count 0 2006.168.07:59:59.91#ibcon#read 4, iclass 20, count 0 2006.168.07:59:59.91#ibcon#about to read 5, iclass 20, count 0 2006.168.07:59:59.91#ibcon#read 5, iclass 20, count 0 2006.168.07:59:59.91#ibcon#about to read 6, iclass 20, count 0 2006.168.07:59:59.91#ibcon#read 6, iclass 20, count 0 2006.168.07:59:59.91#ibcon#end of sib2, iclass 20, count 0 2006.168.07:59:59.91#ibcon#*mode == 0, iclass 20, count 0 2006.168.07:59:59.91#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.168.07:59:59.91#ibcon#[25=USB\r\n] 2006.168.07:59:59.91#ibcon#*before write, iclass 20, count 0 2006.168.07:59:59.91#ibcon#enter sib2, iclass 20, count 0 2006.168.07:59:59.91#ibcon#flushed, iclass 20, count 0 2006.168.07:59:59.91#ibcon#about to write, iclass 20, count 0 2006.168.07:59:59.91#ibcon#wrote, iclass 20, count 0 2006.168.07:59:59.91#ibcon#about to read 3, iclass 20, count 0 2006.168.07:59:59.94#ibcon#read 3, iclass 20, count 0 2006.168.07:59:59.94#ibcon#about to read 4, iclass 20, count 0 2006.168.07:59:59.94#ibcon#read 4, iclass 20, count 0 2006.168.07:59:59.94#ibcon#about to read 5, iclass 20, count 0 2006.168.07:59:59.94#ibcon#read 5, iclass 20, count 0 2006.168.07:59:59.94#ibcon#about to read 6, iclass 20, count 0 2006.168.07:59:59.94#ibcon#read 6, iclass 20, count 0 2006.168.07:59:59.94#ibcon#end of sib2, iclass 20, count 0 2006.168.07:59:59.94#ibcon#*after write, iclass 20, count 0 2006.168.07:59:59.94#ibcon#*before return 0, iclass 20, count 0 2006.168.07:59:59.94#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:59:59.94#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.168.07:59:59.94#ibcon#about to clear, iclass 20 cls_cnt 0 2006.168.07:59:59.94#ibcon#cleared, iclass 20 cls_cnt 0 2006.168.07:59:59.94$vc4f8/valo=7,832.99 2006.168.07:59:59.94#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.168.07:59:59.94#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.168.07:59:59.94#ibcon#ireg 17 cls_cnt 0 2006.168.07:59:59.94#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:59:59.94#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:59:59.94#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.07:59:59.94#ibcon#enter wrdev, iclass 22, count 0 2006.168.07:59:59.94#ibcon#first serial, iclass 22, count 0 2006.168.07:59:59.94#ibcon#enter sib2, iclass 22, count 0 2006.168.07:59:59.94#ibcon#flushed, iclass 22, count 0 2006.168.07:59:59.94#ibcon#about to write, iclass 22, count 0 2006.168.07:59:59.94#ibcon#wrote, iclass 22, count 0 2006.168.07:59:59.94#ibcon#about to read 3, iclass 22, count 0 2006.168.07:59:59.96#ibcon#read 3, iclass 22, count 0 2006.168.07:59:59.96#ibcon#about to read 4, iclass 22, count 0 2006.168.07:59:59.96#ibcon#read 4, iclass 22, count 0 2006.168.07:59:59.96#ibcon#about to read 5, iclass 22, count 0 2006.168.07:59:59.96#ibcon#read 5, iclass 22, count 0 2006.168.07:59:59.96#ibcon#about to read 6, iclass 22, count 0 2006.168.07:59:59.96#ibcon#read 6, iclass 22, count 0 2006.168.07:59:59.96#ibcon#end of sib2, iclass 22, count 0 2006.168.07:59:59.96#ibcon#*mode == 0, iclass 22, count 0 2006.168.07:59:59.96#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.168.07:59:59.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.07:59:59.96#ibcon#*before write, iclass 22, count 0 2006.168.07:59:59.96#ibcon#enter sib2, iclass 22, count 0 2006.168.07:59:59.96#ibcon#flushed, iclass 22, count 0 2006.168.07:59:59.96#ibcon#about to write, iclass 22, count 0 2006.168.07:59:59.96#ibcon#wrote, iclass 22, count 0 2006.168.07:59:59.96#ibcon#about to read 3, iclass 22, count 0 2006.168.08:00:00.00#ibcon#read 3, iclass 22, count 0 2006.168.08:00:00.00#ibcon#about to read 4, iclass 22, count 0 2006.168.08:00:00.00#ibcon#read 4, iclass 22, count 0 2006.168.08:00:00.00#ibcon#about to read 5, iclass 22, count 0 2006.168.08:00:00.00#ibcon#read 5, iclass 22, count 0 2006.168.08:00:00.00#ibcon#about to read 6, iclass 22, count 0 2006.168.08:00:00.00#ibcon#read 6, iclass 22, count 0 2006.168.08:00:00.00#ibcon#end of sib2, iclass 22, count 0 2006.168.08:00:00.00#ibcon#*after write, iclass 22, count 0 2006.168.08:00:00.00#ibcon#*before return 0, iclass 22, count 0 2006.168.08:00:00.00#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:00:00.00#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:00:00.00#ibcon#about to clear, iclass 22 cls_cnt 0 2006.168.08:00:00.00#ibcon#cleared, iclass 22 cls_cnt 0 2006.168.08:00:00.00$vc4f8/va=7,6 2006.168.08:00:00.00#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.168.08:00:00.00#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.168.08:00:00.00#ibcon#ireg 11 cls_cnt 2 2006.168.08:00:00.00#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:00:00.06#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:00:00.06#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:00:00.06#ibcon#enter wrdev, iclass 24, count 2 2006.168.08:00:00.06#ibcon#first serial, iclass 24, count 2 2006.168.08:00:00.06#ibcon#enter sib2, iclass 24, count 2 2006.168.08:00:00.06#ibcon#flushed, iclass 24, count 2 2006.168.08:00:00.06#ibcon#about to write, iclass 24, count 2 2006.168.08:00:00.06#ibcon#wrote, iclass 24, count 2 2006.168.08:00:00.06#ibcon#about to read 3, iclass 24, count 2 2006.168.08:00:00.08#ibcon#read 3, iclass 24, count 2 2006.168.08:00:00.08#ibcon#about to read 4, iclass 24, count 2 2006.168.08:00:00.08#ibcon#read 4, iclass 24, count 2 2006.168.08:00:00.08#ibcon#about to read 5, iclass 24, count 2 2006.168.08:00:00.08#ibcon#read 5, iclass 24, count 2 2006.168.08:00:00.08#ibcon#about to read 6, iclass 24, count 2 2006.168.08:00:00.08#ibcon#read 6, iclass 24, count 2 2006.168.08:00:00.08#ibcon#end of sib2, iclass 24, count 2 2006.168.08:00:00.08#ibcon#*mode == 0, iclass 24, count 2 2006.168.08:00:00.08#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.168.08:00:00.08#ibcon#[25=AT07-06\r\n] 2006.168.08:00:00.08#ibcon#*before write, iclass 24, count 2 2006.168.08:00:00.08#ibcon#enter sib2, iclass 24, count 2 2006.168.08:00:00.08#ibcon#flushed, iclass 24, count 2 2006.168.08:00:00.08#ibcon#about to write, iclass 24, count 2 2006.168.08:00:00.08#ibcon#wrote, iclass 24, count 2 2006.168.08:00:00.08#ibcon#about to read 3, iclass 24, count 2 2006.168.08:00:00.11#ibcon#read 3, iclass 24, count 2 2006.168.08:00:00.11#ibcon#about to read 4, iclass 24, count 2 2006.168.08:00:00.11#ibcon#read 4, iclass 24, count 2 2006.168.08:00:00.11#ibcon#about to read 5, iclass 24, count 2 2006.168.08:00:00.11#ibcon#read 5, iclass 24, count 2 2006.168.08:00:00.11#ibcon#about to read 6, iclass 24, count 2 2006.168.08:00:00.11#ibcon#read 6, iclass 24, count 2 2006.168.08:00:00.11#ibcon#end of sib2, iclass 24, count 2 2006.168.08:00:00.11#ibcon#*after write, iclass 24, count 2 2006.168.08:00:00.11#ibcon#*before return 0, iclass 24, count 2 2006.168.08:00:00.11#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:00:00.11#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:00:00.11#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.168.08:00:00.11#ibcon#ireg 7 cls_cnt 0 2006.168.08:00:00.11#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:00:00.23#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:00:00.23#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:00:00.23#ibcon#enter wrdev, iclass 24, count 0 2006.168.08:00:00.23#ibcon#first serial, iclass 24, count 0 2006.168.08:00:00.23#ibcon#enter sib2, iclass 24, count 0 2006.168.08:00:00.23#ibcon#flushed, iclass 24, count 0 2006.168.08:00:00.23#ibcon#about to write, iclass 24, count 0 2006.168.08:00:00.23#ibcon#wrote, iclass 24, count 0 2006.168.08:00:00.23#ibcon#about to read 3, iclass 24, count 0 2006.168.08:00:00.27#ibcon#read 3, iclass 24, count 0 2006.168.08:00:00.27#ibcon#about to read 4, iclass 24, count 0 2006.168.08:00:00.27#ibcon#read 4, iclass 24, count 0 2006.168.08:00:00.27#ibcon#about to read 5, iclass 24, count 0 2006.168.08:00:00.27#ibcon#read 5, iclass 24, count 0 2006.168.08:00:00.27#ibcon#about to read 6, iclass 24, count 0 2006.168.08:00:00.27#ibcon#read 6, iclass 24, count 0 2006.168.08:00:00.27#ibcon#end of sib2, iclass 24, count 0 2006.168.08:00:00.27#ibcon#*mode == 0, iclass 24, count 0 2006.168.08:00:00.27#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.168.08:00:00.27#ibcon#[25=USB\r\n] 2006.168.08:00:00.27#ibcon#*before write, iclass 24, count 0 2006.168.08:00:00.27#ibcon#enter sib2, iclass 24, count 0 2006.168.08:00:00.27#ibcon#flushed, iclass 24, count 0 2006.168.08:00:00.27#ibcon#about to write, iclass 24, count 0 2006.168.08:00:00.27#ibcon#wrote, iclass 24, count 0 2006.168.08:00:00.27#ibcon#about to read 3, iclass 24, count 0 2006.168.08:00:00.30#ibcon#read 3, iclass 24, count 0 2006.168.08:00:00.30#ibcon#about to read 4, iclass 24, count 0 2006.168.08:00:00.30#ibcon#read 4, iclass 24, count 0 2006.168.08:00:00.30#ibcon#about to read 5, iclass 24, count 0 2006.168.08:00:00.30#ibcon#read 5, iclass 24, count 0 2006.168.08:00:00.30#ibcon#about to read 6, iclass 24, count 0 2006.168.08:00:00.30#ibcon#read 6, iclass 24, count 0 2006.168.08:00:00.30#ibcon#end of sib2, iclass 24, count 0 2006.168.08:00:00.30#ibcon#*after write, iclass 24, count 0 2006.168.08:00:00.30#ibcon#*before return 0, iclass 24, count 0 2006.168.08:00:00.30#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:00:00.30#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:00:00.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.168.08:00:00.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.168.08:00:00.30$vc4f8/valo=8,852.99 2006.168.08:00:00.30#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.168.08:00:00.30#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.168.08:00:00.30#ibcon#ireg 17 cls_cnt 0 2006.168.08:00:00.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:00:00.30#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:00:00.30#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:00:00.30#ibcon#enter wrdev, iclass 26, count 0 2006.168.08:00:00.30#ibcon#first serial, iclass 26, count 0 2006.168.08:00:00.30#ibcon#enter sib2, iclass 26, count 0 2006.168.08:00:00.30#ibcon#flushed, iclass 26, count 0 2006.168.08:00:00.30#ibcon#about to write, iclass 26, count 0 2006.168.08:00:00.30#ibcon#wrote, iclass 26, count 0 2006.168.08:00:00.30#ibcon#about to read 3, iclass 26, count 0 2006.168.08:00:00.32#ibcon#read 3, iclass 26, count 0 2006.168.08:00:00.32#ibcon#about to read 4, iclass 26, count 0 2006.168.08:00:00.32#ibcon#read 4, iclass 26, count 0 2006.168.08:00:00.32#ibcon#about to read 5, iclass 26, count 0 2006.168.08:00:00.32#ibcon#read 5, iclass 26, count 0 2006.168.08:00:00.32#ibcon#about to read 6, iclass 26, count 0 2006.168.08:00:00.32#ibcon#read 6, iclass 26, count 0 2006.168.08:00:00.32#ibcon#end of sib2, iclass 26, count 0 2006.168.08:00:00.32#ibcon#*mode == 0, iclass 26, count 0 2006.168.08:00:00.32#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.168.08:00:00.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.08:00:00.32#ibcon#*before write, iclass 26, count 0 2006.168.08:00:00.32#ibcon#enter sib2, iclass 26, count 0 2006.168.08:00:00.32#ibcon#flushed, iclass 26, count 0 2006.168.08:00:00.32#ibcon#about to write, iclass 26, count 0 2006.168.08:00:00.32#ibcon#wrote, iclass 26, count 0 2006.168.08:00:00.32#ibcon#about to read 3, iclass 26, count 0 2006.168.08:00:00.36#ibcon#read 3, iclass 26, count 0 2006.168.08:00:00.36#ibcon#about to read 4, iclass 26, count 0 2006.168.08:00:00.36#ibcon#read 4, iclass 26, count 0 2006.168.08:00:00.36#ibcon#about to read 5, iclass 26, count 0 2006.168.08:00:00.36#ibcon#read 5, iclass 26, count 0 2006.168.08:00:00.36#ibcon#about to read 6, iclass 26, count 0 2006.168.08:00:00.36#ibcon#read 6, iclass 26, count 0 2006.168.08:00:00.36#ibcon#end of sib2, iclass 26, count 0 2006.168.08:00:00.36#ibcon#*after write, iclass 26, count 0 2006.168.08:00:00.36#ibcon#*before return 0, iclass 26, count 0 2006.168.08:00:00.36#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:00:00.36#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:00:00.36#ibcon#about to clear, iclass 26 cls_cnt 0 2006.168.08:00:00.36#ibcon#cleared, iclass 26 cls_cnt 0 2006.168.08:00:00.36$vc4f8/va=8,7 2006.168.08:00:00.36#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.168.08:00:00.36#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.168.08:00:00.36#ibcon#ireg 11 cls_cnt 2 2006.168.08:00:00.36#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:00:00.42#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:00:00.42#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:00:00.42#ibcon#enter wrdev, iclass 28, count 2 2006.168.08:00:00.42#ibcon#first serial, iclass 28, count 2 2006.168.08:00:00.42#ibcon#enter sib2, iclass 28, count 2 2006.168.08:00:00.42#ibcon#flushed, iclass 28, count 2 2006.168.08:00:00.42#ibcon#about to write, iclass 28, count 2 2006.168.08:00:00.42#ibcon#wrote, iclass 28, count 2 2006.168.08:00:00.42#ibcon#about to read 3, iclass 28, count 2 2006.168.08:00:00.44#ibcon#read 3, iclass 28, count 2 2006.168.08:00:00.44#ibcon#about to read 4, iclass 28, count 2 2006.168.08:00:00.44#ibcon#read 4, iclass 28, count 2 2006.168.08:00:00.44#ibcon#about to read 5, iclass 28, count 2 2006.168.08:00:00.44#ibcon#read 5, iclass 28, count 2 2006.168.08:00:00.44#ibcon#about to read 6, iclass 28, count 2 2006.168.08:00:00.44#ibcon#read 6, iclass 28, count 2 2006.168.08:00:00.44#ibcon#end of sib2, iclass 28, count 2 2006.168.08:00:00.44#ibcon#*mode == 0, iclass 28, count 2 2006.168.08:00:00.44#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.168.08:00:00.44#ibcon#[25=AT08-07\r\n] 2006.168.08:00:00.44#ibcon#*before write, iclass 28, count 2 2006.168.08:00:00.44#ibcon#enter sib2, iclass 28, count 2 2006.168.08:00:00.44#ibcon#flushed, iclass 28, count 2 2006.168.08:00:00.44#ibcon#about to write, iclass 28, count 2 2006.168.08:00:00.44#ibcon#wrote, iclass 28, count 2 2006.168.08:00:00.44#ibcon#about to read 3, iclass 28, count 2 2006.168.08:00:00.47#ibcon#read 3, iclass 28, count 2 2006.168.08:00:00.47#ibcon#about to read 4, iclass 28, count 2 2006.168.08:00:00.47#ibcon#read 4, iclass 28, count 2 2006.168.08:00:00.47#ibcon#about to read 5, iclass 28, count 2 2006.168.08:00:00.47#ibcon#read 5, iclass 28, count 2 2006.168.08:00:00.47#ibcon#about to read 6, iclass 28, count 2 2006.168.08:00:00.47#ibcon#read 6, iclass 28, count 2 2006.168.08:00:00.47#ibcon#end of sib2, iclass 28, count 2 2006.168.08:00:00.47#ibcon#*after write, iclass 28, count 2 2006.168.08:00:00.47#ibcon#*before return 0, iclass 28, count 2 2006.168.08:00:00.47#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:00:00.47#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:00:00.47#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.168.08:00:00.47#ibcon#ireg 7 cls_cnt 0 2006.168.08:00:00.47#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:00:00.59#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:00:00.59#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:00:00.59#ibcon#enter wrdev, iclass 28, count 0 2006.168.08:00:00.59#ibcon#first serial, iclass 28, count 0 2006.168.08:00:00.59#ibcon#enter sib2, iclass 28, count 0 2006.168.08:00:00.59#ibcon#flushed, iclass 28, count 0 2006.168.08:00:00.59#ibcon#about to write, iclass 28, count 0 2006.168.08:00:00.59#ibcon#wrote, iclass 28, count 0 2006.168.08:00:00.59#ibcon#about to read 3, iclass 28, count 0 2006.168.08:00:00.61#ibcon#read 3, iclass 28, count 0 2006.168.08:00:00.61#ibcon#about to read 4, iclass 28, count 0 2006.168.08:00:00.61#ibcon#read 4, iclass 28, count 0 2006.168.08:00:00.61#ibcon#about to read 5, iclass 28, count 0 2006.168.08:00:00.61#ibcon#read 5, iclass 28, count 0 2006.168.08:00:00.61#ibcon#about to read 6, iclass 28, count 0 2006.168.08:00:00.61#ibcon#read 6, iclass 28, count 0 2006.168.08:00:00.61#ibcon#end of sib2, iclass 28, count 0 2006.168.08:00:00.61#ibcon#*mode == 0, iclass 28, count 0 2006.168.08:00:00.61#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.168.08:00:00.61#ibcon#[25=USB\r\n] 2006.168.08:00:00.61#ibcon#*before write, iclass 28, count 0 2006.168.08:00:00.61#ibcon#enter sib2, iclass 28, count 0 2006.168.08:00:00.61#ibcon#flushed, iclass 28, count 0 2006.168.08:00:00.61#ibcon#about to write, iclass 28, count 0 2006.168.08:00:00.61#ibcon#wrote, iclass 28, count 0 2006.168.08:00:00.61#ibcon#about to read 3, iclass 28, count 0 2006.168.08:00:00.64#ibcon#read 3, iclass 28, count 0 2006.168.08:00:00.64#ibcon#about to read 4, iclass 28, count 0 2006.168.08:00:00.64#ibcon#read 4, iclass 28, count 0 2006.168.08:00:00.64#ibcon#about to read 5, iclass 28, count 0 2006.168.08:00:00.64#ibcon#read 5, iclass 28, count 0 2006.168.08:00:00.64#ibcon#about to read 6, iclass 28, count 0 2006.168.08:00:00.64#ibcon#read 6, iclass 28, count 0 2006.168.08:00:00.64#ibcon#end of sib2, iclass 28, count 0 2006.168.08:00:00.64#ibcon#*after write, iclass 28, count 0 2006.168.08:00:00.64#ibcon#*before return 0, iclass 28, count 0 2006.168.08:00:00.64#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:00:00.64#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:00:00.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.168.08:00:00.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.168.08:00:00.64$vc4f8/vblo=1,632.99 2006.168.08:00:00.64#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.168.08:00:00.64#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.168.08:00:00.64#ibcon#ireg 17 cls_cnt 0 2006.168.08:00:00.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:00:00.64#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:00:00.64#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:00:00.64#ibcon#enter wrdev, iclass 30, count 0 2006.168.08:00:00.64#ibcon#first serial, iclass 30, count 0 2006.168.08:00:00.64#ibcon#enter sib2, iclass 30, count 0 2006.168.08:00:00.64#ibcon#flushed, iclass 30, count 0 2006.168.08:00:00.64#ibcon#about to write, iclass 30, count 0 2006.168.08:00:00.64#ibcon#wrote, iclass 30, count 0 2006.168.08:00:00.64#ibcon#about to read 3, iclass 30, count 0 2006.168.08:00:00.66#ibcon#read 3, iclass 30, count 0 2006.168.08:00:00.66#ibcon#about to read 4, iclass 30, count 0 2006.168.08:00:00.66#ibcon#read 4, iclass 30, count 0 2006.168.08:00:00.66#ibcon#about to read 5, iclass 30, count 0 2006.168.08:00:00.66#ibcon#read 5, iclass 30, count 0 2006.168.08:00:00.66#ibcon#about to read 6, iclass 30, count 0 2006.168.08:00:00.66#ibcon#read 6, iclass 30, count 0 2006.168.08:00:00.66#ibcon#end of sib2, iclass 30, count 0 2006.168.08:00:00.66#ibcon#*mode == 0, iclass 30, count 0 2006.168.08:00:00.66#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.168.08:00:00.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.08:00:00.66#ibcon#*before write, iclass 30, count 0 2006.168.08:00:00.66#ibcon#enter sib2, iclass 30, count 0 2006.168.08:00:00.66#ibcon#flushed, iclass 30, count 0 2006.168.08:00:00.66#ibcon#about to write, iclass 30, count 0 2006.168.08:00:00.66#ibcon#wrote, iclass 30, count 0 2006.168.08:00:00.66#ibcon#about to read 3, iclass 30, count 0 2006.168.08:00:00.70#ibcon#read 3, iclass 30, count 0 2006.168.08:00:00.70#ibcon#about to read 4, iclass 30, count 0 2006.168.08:00:00.70#ibcon#read 4, iclass 30, count 0 2006.168.08:00:00.70#ibcon#about to read 5, iclass 30, count 0 2006.168.08:00:00.70#ibcon#read 5, iclass 30, count 0 2006.168.08:00:00.70#ibcon#about to read 6, iclass 30, count 0 2006.168.08:00:00.70#ibcon#read 6, iclass 30, count 0 2006.168.08:00:00.70#ibcon#end of sib2, iclass 30, count 0 2006.168.08:00:00.70#ibcon#*after write, iclass 30, count 0 2006.168.08:00:00.70#ibcon#*before return 0, iclass 30, count 0 2006.168.08:00:00.70#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:00:00.70#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:00:00.70#ibcon#about to clear, iclass 30 cls_cnt 0 2006.168.08:00:00.70#ibcon#cleared, iclass 30 cls_cnt 0 2006.168.08:00:00.70$vc4f8/vb=1,4 2006.168.08:00:00.70#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.168.08:00:00.70#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.168.08:00:00.70#ibcon#ireg 11 cls_cnt 2 2006.168.08:00:00.70#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:00:00.70#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:00:00.70#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:00:00.70#ibcon#enter wrdev, iclass 32, count 2 2006.168.08:00:00.70#ibcon#first serial, iclass 32, count 2 2006.168.08:00:00.70#ibcon#enter sib2, iclass 32, count 2 2006.168.08:00:00.70#ibcon#flushed, iclass 32, count 2 2006.168.08:00:00.70#ibcon#about to write, iclass 32, count 2 2006.168.08:00:00.70#ibcon#wrote, iclass 32, count 2 2006.168.08:00:00.70#ibcon#about to read 3, iclass 32, count 2 2006.168.08:00:00.72#ibcon#read 3, iclass 32, count 2 2006.168.08:00:00.72#ibcon#about to read 4, iclass 32, count 2 2006.168.08:00:00.72#ibcon#read 4, iclass 32, count 2 2006.168.08:00:00.72#ibcon#about to read 5, iclass 32, count 2 2006.168.08:00:00.72#ibcon#read 5, iclass 32, count 2 2006.168.08:00:00.72#ibcon#about to read 6, iclass 32, count 2 2006.168.08:00:00.72#ibcon#read 6, iclass 32, count 2 2006.168.08:00:00.72#ibcon#end of sib2, iclass 32, count 2 2006.168.08:00:00.72#ibcon#*mode == 0, iclass 32, count 2 2006.168.08:00:00.72#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.168.08:00:00.72#ibcon#[27=AT01-04\r\n] 2006.168.08:00:00.72#ibcon#*before write, iclass 32, count 2 2006.168.08:00:00.72#ibcon#enter sib2, iclass 32, count 2 2006.168.08:00:00.72#ibcon#flushed, iclass 32, count 2 2006.168.08:00:00.72#ibcon#about to write, iclass 32, count 2 2006.168.08:00:00.72#ibcon#wrote, iclass 32, count 2 2006.168.08:00:00.72#ibcon#about to read 3, iclass 32, count 2 2006.168.08:00:00.75#ibcon#read 3, iclass 32, count 2 2006.168.08:00:00.75#ibcon#about to read 4, iclass 32, count 2 2006.168.08:00:00.75#ibcon#read 4, iclass 32, count 2 2006.168.08:00:00.75#ibcon#about to read 5, iclass 32, count 2 2006.168.08:00:00.75#ibcon#read 5, iclass 32, count 2 2006.168.08:00:00.75#ibcon#about to read 6, iclass 32, count 2 2006.168.08:00:00.75#ibcon#read 6, iclass 32, count 2 2006.168.08:00:00.75#ibcon#end of sib2, iclass 32, count 2 2006.168.08:00:00.75#ibcon#*after write, iclass 32, count 2 2006.168.08:00:00.75#ibcon#*before return 0, iclass 32, count 2 2006.168.08:00:00.75#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:00:00.75#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:00:00.75#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.168.08:00:00.75#ibcon#ireg 7 cls_cnt 0 2006.168.08:00:00.75#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:00:00.87#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:00:00.87#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:00:00.87#ibcon#enter wrdev, iclass 32, count 0 2006.168.08:00:00.87#ibcon#first serial, iclass 32, count 0 2006.168.08:00:00.87#ibcon#enter sib2, iclass 32, count 0 2006.168.08:00:00.87#ibcon#flushed, iclass 32, count 0 2006.168.08:00:00.87#ibcon#about to write, iclass 32, count 0 2006.168.08:00:00.87#ibcon#wrote, iclass 32, count 0 2006.168.08:00:00.87#ibcon#about to read 3, iclass 32, count 0 2006.168.08:00:00.89#ibcon#read 3, iclass 32, count 0 2006.168.08:00:00.89#ibcon#about to read 4, iclass 32, count 0 2006.168.08:00:00.89#ibcon#read 4, iclass 32, count 0 2006.168.08:00:00.89#ibcon#about to read 5, iclass 32, count 0 2006.168.08:00:00.89#ibcon#read 5, iclass 32, count 0 2006.168.08:00:00.89#ibcon#about to read 6, iclass 32, count 0 2006.168.08:00:00.89#ibcon#read 6, iclass 32, count 0 2006.168.08:00:00.89#ibcon#end of sib2, iclass 32, count 0 2006.168.08:00:00.89#ibcon#*mode == 0, iclass 32, count 0 2006.168.08:00:00.89#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.168.08:00:00.89#ibcon#[27=USB\r\n] 2006.168.08:00:00.89#ibcon#*before write, iclass 32, count 0 2006.168.08:00:00.89#ibcon#enter sib2, iclass 32, count 0 2006.168.08:00:00.89#ibcon#flushed, iclass 32, count 0 2006.168.08:00:00.89#ibcon#about to write, iclass 32, count 0 2006.168.08:00:00.89#ibcon#wrote, iclass 32, count 0 2006.168.08:00:00.89#ibcon#about to read 3, iclass 32, count 0 2006.168.08:00:00.92#ibcon#read 3, iclass 32, count 0 2006.168.08:00:00.92#ibcon#about to read 4, iclass 32, count 0 2006.168.08:00:00.92#ibcon#read 4, iclass 32, count 0 2006.168.08:00:00.92#ibcon#about to read 5, iclass 32, count 0 2006.168.08:00:00.92#ibcon#read 5, iclass 32, count 0 2006.168.08:00:00.92#ibcon#about to read 6, iclass 32, count 0 2006.168.08:00:00.92#ibcon#read 6, iclass 32, count 0 2006.168.08:00:00.92#ibcon#end of sib2, iclass 32, count 0 2006.168.08:00:00.92#ibcon#*after write, iclass 32, count 0 2006.168.08:00:00.92#ibcon#*before return 0, iclass 32, count 0 2006.168.08:00:00.92#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:00:00.92#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:00:00.92#ibcon#about to clear, iclass 32 cls_cnt 0 2006.168.08:00:00.92#ibcon#cleared, iclass 32 cls_cnt 0 2006.168.08:00:00.92$vc4f8/vblo=2,640.99 2006.168.08:00:00.92#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.168.08:00:00.92#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.168.08:00:00.92#ibcon#ireg 17 cls_cnt 0 2006.168.08:00:00.92#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:00:00.92#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:00:00.92#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:00:00.92#ibcon#enter wrdev, iclass 34, count 0 2006.168.08:00:00.92#ibcon#first serial, iclass 34, count 0 2006.168.08:00:00.92#ibcon#enter sib2, iclass 34, count 0 2006.168.08:00:00.92#ibcon#flushed, iclass 34, count 0 2006.168.08:00:00.92#ibcon#about to write, iclass 34, count 0 2006.168.08:00:00.92#ibcon#wrote, iclass 34, count 0 2006.168.08:00:00.92#ibcon#about to read 3, iclass 34, count 0 2006.168.08:00:00.94#ibcon#read 3, iclass 34, count 0 2006.168.08:00:00.94#ibcon#about to read 4, iclass 34, count 0 2006.168.08:00:00.94#ibcon#read 4, iclass 34, count 0 2006.168.08:00:00.94#ibcon#about to read 5, iclass 34, count 0 2006.168.08:00:00.94#ibcon#read 5, iclass 34, count 0 2006.168.08:00:00.94#ibcon#about to read 6, iclass 34, count 0 2006.168.08:00:00.94#ibcon#read 6, iclass 34, count 0 2006.168.08:00:00.94#ibcon#end of sib2, iclass 34, count 0 2006.168.08:00:00.94#ibcon#*mode == 0, iclass 34, count 0 2006.168.08:00:00.94#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.168.08:00:00.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.08:00:00.94#ibcon#*before write, iclass 34, count 0 2006.168.08:00:00.94#ibcon#enter sib2, iclass 34, count 0 2006.168.08:00:00.94#ibcon#flushed, iclass 34, count 0 2006.168.08:00:00.94#ibcon#about to write, iclass 34, count 0 2006.168.08:00:00.94#ibcon#wrote, iclass 34, count 0 2006.168.08:00:00.94#ibcon#about to read 3, iclass 34, count 0 2006.168.08:00:00.98#ibcon#read 3, iclass 34, count 0 2006.168.08:00:00.98#ibcon#about to read 4, iclass 34, count 0 2006.168.08:00:00.98#ibcon#read 4, iclass 34, count 0 2006.168.08:00:00.98#ibcon#about to read 5, iclass 34, count 0 2006.168.08:00:00.98#ibcon#read 5, iclass 34, count 0 2006.168.08:00:00.98#ibcon#about to read 6, iclass 34, count 0 2006.168.08:00:00.98#ibcon#read 6, iclass 34, count 0 2006.168.08:00:00.98#ibcon#end of sib2, iclass 34, count 0 2006.168.08:00:00.98#ibcon#*after write, iclass 34, count 0 2006.168.08:00:00.98#ibcon#*before return 0, iclass 34, count 0 2006.168.08:00:00.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:00:00.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:00:00.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.168.08:00:00.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.168.08:00:00.98$vc4f8/vb=2,4 2006.168.08:00:00.98#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.168.08:00:00.98#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.168.08:00:00.98#ibcon#ireg 11 cls_cnt 2 2006.168.08:00:00.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:00:01.04#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:00:01.04#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:00:01.04#ibcon#enter wrdev, iclass 36, count 2 2006.168.08:00:01.04#ibcon#first serial, iclass 36, count 2 2006.168.08:00:01.04#ibcon#enter sib2, iclass 36, count 2 2006.168.08:00:01.04#ibcon#flushed, iclass 36, count 2 2006.168.08:00:01.04#ibcon#about to write, iclass 36, count 2 2006.168.08:00:01.04#ibcon#wrote, iclass 36, count 2 2006.168.08:00:01.04#ibcon#about to read 3, iclass 36, count 2 2006.168.08:00:01.06#ibcon#read 3, iclass 36, count 2 2006.168.08:00:01.06#ibcon#about to read 4, iclass 36, count 2 2006.168.08:00:01.06#ibcon#read 4, iclass 36, count 2 2006.168.08:00:01.06#ibcon#about to read 5, iclass 36, count 2 2006.168.08:00:01.06#ibcon#read 5, iclass 36, count 2 2006.168.08:00:01.06#ibcon#about to read 6, iclass 36, count 2 2006.168.08:00:01.06#ibcon#read 6, iclass 36, count 2 2006.168.08:00:01.06#ibcon#end of sib2, iclass 36, count 2 2006.168.08:00:01.06#ibcon#*mode == 0, iclass 36, count 2 2006.168.08:00:01.06#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.168.08:00:01.06#ibcon#[27=AT02-04\r\n] 2006.168.08:00:01.06#ibcon#*before write, iclass 36, count 2 2006.168.08:00:01.06#ibcon#enter sib2, iclass 36, count 2 2006.168.08:00:01.06#ibcon#flushed, iclass 36, count 2 2006.168.08:00:01.06#ibcon#about to write, iclass 36, count 2 2006.168.08:00:01.06#ibcon#wrote, iclass 36, count 2 2006.168.08:00:01.06#ibcon#about to read 3, iclass 36, count 2 2006.168.08:00:01.09#ibcon#read 3, iclass 36, count 2 2006.168.08:00:01.09#ibcon#about to read 4, iclass 36, count 2 2006.168.08:00:01.09#ibcon#read 4, iclass 36, count 2 2006.168.08:00:01.09#ibcon#about to read 5, iclass 36, count 2 2006.168.08:00:01.09#ibcon#read 5, iclass 36, count 2 2006.168.08:00:01.09#ibcon#about to read 6, iclass 36, count 2 2006.168.08:00:01.09#ibcon#read 6, iclass 36, count 2 2006.168.08:00:01.09#ibcon#end of sib2, iclass 36, count 2 2006.168.08:00:01.09#ibcon#*after write, iclass 36, count 2 2006.168.08:00:01.09#ibcon#*before return 0, iclass 36, count 2 2006.168.08:00:01.09#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:00:01.09#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:00:01.09#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.168.08:00:01.09#ibcon#ireg 7 cls_cnt 0 2006.168.08:00:01.09#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:00:01.21#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:00:01.21#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:00:01.21#ibcon#enter wrdev, iclass 36, count 0 2006.168.08:00:01.21#ibcon#first serial, iclass 36, count 0 2006.168.08:00:01.21#ibcon#enter sib2, iclass 36, count 0 2006.168.08:00:01.21#ibcon#flushed, iclass 36, count 0 2006.168.08:00:01.21#ibcon#about to write, iclass 36, count 0 2006.168.08:00:01.21#ibcon#wrote, iclass 36, count 0 2006.168.08:00:01.21#ibcon#about to read 3, iclass 36, count 0 2006.168.08:00:01.23#ibcon#read 3, iclass 36, count 0 2006.168.08:00:01.23#ibcon#about to read 4, iclass 36, count 0 2006.168.08:00:01.23#ibcon#read 4, iclass 36, count 0 2006.168.08:00:01.23#ibcon#about to read 5, iclass 36, count 0 2006.168.08:00:01.23#ibcon#read 5, iclass 36, count 0 2006.168.08:00:01.23#ibcon#about to read 6, iclass 36, count 0 2006.168.08:00:01.23#ibcon#read 6, iclass 36, count 0 2006.168.08:00:01.23#ibcon#end of sib2, iclass 36, count 0 2006.168.08:00:01.23#ibcon#*mode == 0, iclass 36, count 0 2006.168.08:00:01.23#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.168.08:00:01.23#ibcon#[27=USB\r\n] 2006.168.08:00:01.23#ibcon#*before write, iclass 36, count 0 2006.168.08:00:01.23#ibcon#enter sib2, iclass 36, count 0 2006.168.08:00:01.23#ibcon#flushed, iclass 36, count 0 2006.168.08:00:01.23#ibcon#about to write, iclass 36, count 0 2006.168.08:00:01.23#ibcon#wrote, iclass 36, count 0 2006.168.08:00:01.23#ibcon#about to read 3, iclass 36, count 0 2006.168.08:00:01.26#ibcon#read 3, iclass 36, count 0 2006.168.08:00:01.26#ibcon#about to read 4, iclass 36, count 0 2006.168.08:00:01.26#ibcon#read 4, iclass 36, count 0 2006.168.08:00:01.26#ibcon#about to read 5, iclass 36, count 0 2006.168.08:00:01.26#ibcon#read 5, iclass 36, count 0 2006.168.08:00:01.26#ibcon#about to read 6, iclass 36, count 0 2006.168.08:00:01.26#ibcon#read 6, iclass 36, count 0 2006.168.08:00:01.26#ibcon#end of sib2, iclass 36, count 0 2006.168.08:00:01.26#ibcon#*after write, iclass 36, count 0 2006.168.08:00:01.26#ibcon#*before return 0, iclass 36, count 0 2006.168.08:00:01.26#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:00:01.26#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:00:01.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.168.08:00:01.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.168.08:00:01.26$vc4f8/vblo=3,656.99 2006.168.08:00:01.26#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.168.08:00:01.26#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.168.08:00:01.26#ibcon#ireg 17 cls_cnt 0 2006.168.08:00:01.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:00:01.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:00:01.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:00:01.26#ibcon#enter wrdev, iclass 38, count 0 2006.168.08:00:01.26#ibcon#first serial, iclass 38, count 0 2006.168.08:00:01.26#ibcon#enter sib2, iclass 38, count 0 2006.168.08:00:01.26#ibcon#flushed, iclass 38, count 0 2006.168.08:00:01.26#ibcon#about to write, iclass 38, count 0 2006.168.08:00:01.26#ibcon#wrote, iclass 38, count 0 2006.168.08:00:01.26#ibcon#about to read 3, iclass 38, count 0 2006.168.08:00:01.28#ibcon#read 3, iclass 38, count 0 2006.168.08:00:01.28#ibcon#about to read 4, iclass 38, count 0 2006.168.08:00:01.28#ibcon#read 4, iclass 38, count 0 2006.168.08:00:01.28#ibcon#about to read 5, iclass 38, count 0 2006.168.08:00:01.28#ibcon#read 5, iclass 38, count 0 2006.168.08:00:01.28#ibcon#about to read 6, iclass 38, count 0 2006.168.08:00:01.28#ibcon#read 6, iclass 38, count 0 2006.168.08:00:01.28#ibcon#end of sib2, iclass 38, count 0 2006.168.08:00:01.28#ibcon#*mode == 0, iclass 38, count 0 2006.168.08:00:01.28#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.168.08:00:01.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.08:00:01.28#ibcon#*before write, iclass 38, count 0 2006.168.08:00:01.28#ibcon#enter sib2, iclass 38, count 0 2006.168.08:00:01.28#ibcon#flushed, iclass 38, count 0 2006.168.08:00:01.28#ibcon#about to write, iclass 38, count 0 2006.168.08:00:01.28#ibcon#wrote, iclass 38, count 0 2006.168.08:00:01.28#ibcon#about to read 3, iclass 38, count 0 2006.168.08:00:01.32#ibcon#read 3, iclass 38, count 0 2006.168.08:00:01.32#ibcon#about to read 4, iclass 38, count 0 2006.168.08:00:01.32#ibcon#read 4, iclass 38, count 0 2006.168.08:00:01.32#ibcon#about to read 5, iclass 38, count 0 2006.168.08:00:01.32#ibcon#read 5, iclass 38, count 0 2006.168.08:00:01.32#ibcon#about to read 6, iclass 38, count 0 2006.168.08:00:01.32#ibcon#read 6, iclass 38, count 0 2006.168.08:00:01.32#ibcon#end of sib2, iclass 38, count 0 2006.168.08:00:01.32#ibcon#*after write, iclass 38, count 0 2006.168.08:00:01.32#ibcon#*before return 0, iclass 38, count 0 2006.168.08:00:01.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:00:01.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:00:01.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.168.08:00:01.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.168.08:00:01.32$vc4f8/vb=3,4 2006.168.08:00:01.32#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.168.08:00:01.32#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.168.08:00:01.32#ibcon#ireg 11 cls_cnt 2 2006.168.08:00:01.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:00:01.38#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:00:01.38#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:00:01.38#ibcon#enter wrdev, iclass 40, count 2 2006.168.08:00:01.38#ibcon#first serial, iclass 40, count 2 2006.168.08:00:01.38#ibcon#enter sib2, iclass 40, count 2 2006.168.08:00:01.38#ibcon#flushed, iclass 40, count 2 2006.168.08:00:01.38#ibcon#about to write, iclass 40, count 2 2006.168.08:00:01.38#ibcon#wrote, iclass 40, count 2 2006.168.08:00:01.38#ibcon#about to read 3, iclass 40, count 2 2006.168.08:00:01.40#ibcon#read 3, iclass 40, count 2 2006.168.08:00:01.40#ibcon#about to read 4, iclass 40, count 2 2006.168.08:00:01.40#ibcon#read 4, iclass 40, count 2 2006.168.08:00:01.40#ibcon#about to read 5, iclass 40, count 2 2006.168.08:00:01.40#ibcon#read 5, iclass 40, count 2 2006.168.08:00:01.40#ibcon#about to read 6, iclass 40, count 2 2006.168.08:00:01.40#ibcon#read 6, iclass 40, count 2 2006.168.08:00:01.40#ibcon#end of sib2, iclass 40, count 2 2006.168.08:00:01.40#ibcon#*mode == 0, iclass 40, count 2 2006.168.08:00:01.40#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.168.08:00:01.40#ibcon#[27=AT03-04\r\n] 2006.168.08:00:01.40#ibcon#*before write, iclass 40, count 2 2006.168.08:00:01.40#ibcon#enter sib2, iclass 40, count 2 2006.168.08:00:01.40#ibcon#flushed, iclass 40, count 2 2006.168.08:00:01.40#ibcon#about to write, iclass 40, count 2 2006.168.08:00:01.40#ibcon#wrote, iclass 40, count 2 2006.168.08:00:01.40#ibcon#about to read 3, iclass 40, count 2 2006.168.08:00:01.43#ibcon#read 3, iclass 40, count 2 2006.168.08:00:01.43#ibcon#about to read 4, iclass 40, count 2 2006.168.08:00:01.43#ibcon#read 4, iclass 40, count 2 2006.168.08:00:01.43#ibcon#about to read 5, iclass 40, count 2 2006.168.08:00:01.43#ibcon#read 5, iclass 40, count 2 2006.168.08:00:01.43#ibcon#about to read 6, iclass 40, count 2 2006.168.08:00:01.43#ibcon#read 6, iclass 40, count 2 2006.168.08:00:01.43#ibcon#end of sib2, iclass 40, count 2 2006.168.08:00:01.43#ibcon#*after write, iclass 40, count 2 2006.168.08:00:01.43#ibcon#*before return 0, iclass 40, count 2 2006.168.08:00:01.43#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:00:01.43#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:00:01.43#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.168.08:00:01.43#ibcon#ireg 7 cls_cnt 0 2006.168.08:00:01.43#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:00:01.55#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:00:01.55#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:00:01.55#ibcon#enter wrdev, iclass 40, count 0 2006.168.08:00:01.55#ibcon#first serial, iclass 40, count 0 2006.168.08:00:01.55#ibcon#enter sib2, iclass 40, count 0 2006.168.08:00:01.55#ibcon#flushed, iclass 40, count 0 2006.168.08:00:01.55#ibcon#about to write, iclass 40, count 0 2006.168.08:00:01.55#ibcon#wrote, iclass 40, count 0 2006.168.08:00:01.55#ibcon#about to read 3, iclass 40, count 0 2006.168.08:00:01.57#ibcon#read 3, iclass 40, count 0 2006.168.08:00:01.57#ibcon#about to read 4, iclass 40, count 0 2006.168.08:00:01.57#ibcon#read 4, iclass 40, count 0 2006.168.08:00:01.57#ibcon#about to read 5, iclass 40, count 0 2006.168.08:00:01.57#ibcon#read 5, iclass 40, count 0 2006.168.08:00:01.57#ibcon#about to read 6, iclass 40, count 0 2006.168.08:00:01.57#ibcon#read 6, iclass 40, count 0 2006.168.08:00:01.57#ibcon#end of sib2, iclass 40, count 0 2006.168.08:00:01.57#ibcon#*mode == 0, iclass 40, count 0 2006.168.08:00:01.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.168.08:00:01.57#ibcon#[27=USB\r\n] 2006.168.08:00:01.57#ibcon#*before write, iclass 40, count 0 2006.168.08:00:01.57#ibcon#enter sib2, iclass 40, count 0 2006.168.08:00:01.57#ibcon#flushed, iclass 40, count 0 2006.168.08:00:01.57#ibcon#about to write, iclass 40, count 0 2006.168.08:00:01.57#ibcon#wrote, iclass 40, count 0 2006.168.08:00:01.57#ibcon#about to read 3, iclass 40, count 0 2006.168.08:00:01.60#ibcon#read 3, iclass 40, count 0 2006.168.08:00:01.60#ibcon#about to read 4, iclass 40, count 0 2006.168.08:00:01.60#ibcon#read 4, iclass 40, count 0 2006.168.08:00:01.60#ibcon#about to read 5, iclass 40, count 0 2006.168.08:00:01.60#ibcon#read 5, iclass 40, count 0 2006.168.08:00:01.60#ibcon#about to read 6, iclass 40, count 0 2006.168.08:00:01.60#ibcon#read 6, iclass 40, count 0 2006.168.08:00:01.60#ibcon#end of sib2, iclass 40, count 0 2006.168.08:00:01.60#ibcon#*after write, iclass 40, count 0 2006.168.08:00:01.60#ibcon#*before return 0, iclass 40, count 0 2006.168.08:00:01.60#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:00:01.60#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:00:01.60#ibcon#about to clear, iclass 40 cls_cnt 0 2006.168.08:00:01.60#ibcon#cleared, iclass 40 cls_cnt 0 2006.168.08:00:01.60$vc4f8/vblo=4,712.99 2006.168.08:00:01.60#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.168.08:00:01.60#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.168.08:00:01.60#ibcon#ireg 17 cls_cnt 0 2006.168.08:00:01.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:00:01.60#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:00:01.60#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:00:01.60#ibcon#enter wrdev, iclass 4, count 0 2006.168.08:00:01.60#ibcon#first serial, iclass 4, count 0 2006.168.08:00:01.60#ibcon#enter sib2, iclass 4, count 0 2006.168.08:00:01.60#ibcon#flushed, iclass 4, count 0 2006.168.08:00:01.60#ibcon#about to write, iclass 4, count 0 2006.168.08:00:01.60#ibcon#wrote, iclass 4, count 0 2006.168.08:00:01.60#ibcon#about to read 3, iclass 4, count 0 2006.168.08:00:01.62#ibcon#read 3, iclass 4, count 0 2006.168.08:00:01.62#ibcon#about to read 4, iclass 4, count 0 2006.168.08:00:01.62#ibcon#read 4, iclass 4, count 0 2006.168.08:00:01.62#ibcon#about to read 5, iclass 4, count 0 2006.168.08:00:01.62#ibcon#read 5, iclass 4, count 0 2006.168.08:00:01.62#ibcon#about to read 6, iclass 4, count 0 2006.168.08:00:01.62#ibcon#read 6, iclass 4, count 0 2006.168.08:00:01.62#ibcon#end of sib2, iclass 4, count 0 2006.168.08:00:01.62#ibcon#*mode == 0, iclass 4, count 0 2006.168.08:00:01.62#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.168.08:00:01.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.08:00:01.62#ibcon#*before write, iclass 4, count 0 2006.168.08:00:01.62#ibcon#enter sib2, iclass 4, count 0 2006.168.08:00:01.62#ibcon#flushed, iclass 4, count 0 2006.168.08:00:01.62#ibcon#about to write, iclass 4, count 0 2006.168.08:00:01.62#ibcon#wrote, iclass 4, count 0 2006.168.08:00:01.62#ibcon#about to read 3, iclass 4, count 0 2006.168.08:00:01.66#ibcon#read 3, iclass 4, count 0 2006.168.08:00:01.66#ibcon#about to read 4, iclass 4, count 0 2006.168.08:00:01.66#ibcon#read 4, iclass 4, count 0 2006.168.08:00:01.66#ibcon#about to read 5, iclass 4, count 0 2006.168.08:00:01.66#ibcon#read 5, iclass 4, count 0 2006.168.08:00:01.66#ibcon#about to read 6, iclass 4, count 0 2006.168.08:00:01.66#ibcon#read 6, iclass 4, count 0 2006.168.08:00:01.66#ibcon#end of sib2, iclass 4, count 0 2006.168.08:00:01.66#ibcon#*after write, iclass 4, count 0 2006.168.08:00:01.66#ibcon#*before return 0, iclass 4, count 0 2006.168.08:00:01.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:00:01.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:00:01.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.168.08:00:01.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.168.08:00:01.66$vc4f8/vb=4,4 2006.168.08:00:01.66#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.168.08:00:01.66#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.168.08:00:01.66#ibcon#ireg 11 cls_cnt 2 2006.168.08:00:01.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:00:01.72#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:00:01.72#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:00:01.72#ibcon#enter wrdev, iclass 6, count 2 2006.168.08:00:01.72#ibcon#first serial, iclass 6, count 2 2006.168.08:00:01.72#ibcon#enter sib2, iclass 6, count 2 2006.168.08:00:01.72#ibcon#flushed, iclass 6, count 2 2006.168.08:00:01.72#ibcon#about to write, iclass 6, count 2 2006.168.08:00:01.72#ibcon#wrote, iclass 6, count 2 2006.168.08:00:01.72#ibcon#about to read 3, iclass 6, count 2 2006.168.08:00:01.74#ibcon#read 3, iclass 6, count 2 2006.168.08:00:01.74#ibcon#about to read 4, iclass 6, count 2 2006.168.08:00:01.74#ibcon#read 4, iclass 6, count 2 2006.168.08:00:01.74#ibcon#about to read 5, iclass 6, count 2 2006.168.08:00:01.74#ibcon#read 5, iclass 6, count 2 2006.168.08:00:01.74#ibcon#about to read 6, iclass 6, count 2 2006.168.08:00:01.74#ibcon#read 6, iclass 6, count 2 2006.168.08:00:01.74#ibcon#end of sib2, iclass 6, count 2 2006.168.08:00:01.74#ibcon#*mode == 0, iclass 6, count 2 2006.168.08:00:01.74#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.168.08:00:01.74#ibcon#[27=AT04-04\r\n] 2006.168.08:00:01.74#ibcon#*before write, iclass 6, count 2 2006.168.08:00:01.74#ibcon#enter sib2, iclass 6, count 2 2006.168.08:00:01.74#ibcon#flushed, iclass 6, count 2 2006.168.08:00:01.74#ibcon#about to write, iclass 6, count 2 2006.168.08:00:01.74#ibcon#wrote, iclass 6, count 2 2006.168.08:00:01.74#ibcon#about to read 3, iclass 6, count 2 2006.168.08:00:01.77#ibcon#read 3, iclass 6, count 2 2006.168.08:00:01.77#ibcon#about to read 4, iclass 6, count 2 2006.168.08:00:01.77#ibcon#read 4, iclass 6, count 2 2006.168.08:00:01.77#ibcon#about to read 5, iclass 6, count 2 2006.168.08:00:01.77#ibcon#read 5, iclass 6, count 2 2006.168.08:00:01.77#ibcon#about to read 6, iclass 6, count 2 2006.168.08:00:01.77#ibcon#read 6, iclass 6, count 2 2006.168.08:00:01.77#ibcon#end of sib2, iclass 6, count 2 2006.168.08:00:01.77#ibcon#*after write, iclass 6, count 2 2006.168.08:00:01.77#ibcon#*before return 0, iclass 6, count 2 2006.168.08:00:01.77#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:00:01.77#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:00:01.77#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.168.08:00:01.77#ibcon#ireg 7 cls_cnt 0 2006.168.08:00:01.77#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:00:01.89#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:00:01.89#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:00:01.89#ibcon#enter wrdev, iclass 6, count 0 2006.168.08:00:01.89#ibcon#first serial, iclass 6, count 0 2006.168.08:00:01.89#ibcon#enter sib2, iclass 6, count 0 2006.168.08:00:01.89#ibcon#flushed, iclass 6, count 0 2006.168.08:00:01.89#ibcon#about to write, iclass 6, count 0 2006.168.08:00:01.89#ibcon#wrote, iclass 6, count 0 2006.168.08:00:01.89#ibcon#about to read 3, iclass 6, count 0 2006.168.08:00:01.91#ibcon#read 3, iclass 6, count 0 2006.168.08:00:01.91#ibcon#about to read 4, iclass 6, count 0 2006.168.08:00:01.91#ibcon#read 4, iclass 6, count 0 2006.168.08:00:01.91#ibcon#about to read 5, iclass 6, count 0 2006.168.08:00:01.91#ibcon#read 5, iclass 6, count 0 2006.168.08:00:01.91#ibcon#about to read 6, iclass 6, count 0 2006.168.08:00:01.91#ibcon#read 6, iclass 6, count 0 2006.168.08:00:01.91#ibcon#end of sib2, iclass 6, count 0 2006.168.08:00:01.91#ibcon#*mode == 0, iclass 6, count 0 2006.168.08:00:01.91#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.168.08:00:01.91#ibcon#[27=USB\r\n] 2006.168.08:00:01.91#ibcon#*before write, iclass 6, count 0 2006.168.08:00:01.91#ibcon#enter sib2, iclass 6, count 0 2006.168.08:00:01.91#ibcon#flushed, iclass 6, count 0 2006.168.08:00:01.91#ibcon#about to write, iclass 6, count 0 2006.168.08:00:01.91#ibcon#wrote, iclass 6, count 0 2006.168.08:00:01.91#ibcon#about to read 3, iclass 6, count 0 2006.168.08:00:01.94#ibcon#read 3, iclass 6, count 0 2006.168.08:00:01.94#ibcon#about to read 4, iclass 6, count 0 2006.168.08:00:01.94#ibcon#read 4, iclass 6, count 0 2006.168.08:00:01.94#ibcon#about to read 5, iclass 6, count 0 2006.168.08:00:01.94#ibcon#read 5, iclass 6, count 0 2006.168.08:00:01.94#ibcon#about to read 6, iclass 6, count 0 2006.168.08:00:01.94#ibcon#read 6, iclass 6, count 0 2006.168.08:00:01.94#ibcon#end of sib2, iclass 6, count 0 2006.168.08:00:01.94#ibcon#*after write, iclass 6, count 0 2006.168.08:00:01.94#ibcon#*before return 0, iclass 6, count 0 2006.168.08:00:01.94#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:00:01.94#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:00:01.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.168.08:00:01.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.168.08:00:01.94$vc4f8/vblo=5,744.99 2006.168.08:00:01.94#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.168.08:00:01.94#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.168.08:00:01.94#ibcon#ireg 17 cls_cnt 0 2006.168.08:00:01.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:00:01.94#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:00:01.94#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:00:01.94#ibcon#enter wrdev, iclass 10, count 0 2006.168.08:00:01.94#ibcon#first serial, iclass 10, count 0 2006.168.08:00:01.94#ibcon#enter sib2, iclass 10, count 0 2006.168.08:00:01.94#ibcon#flushed, iclass 10, count 0 2006.168.08:00:01.94#ibcon#about to write, iclass 10, count 0 2006.168.08:00:01.94#ibcon#wrote, iclass 10, count 0 2006.168.08:00:01.94#ibcon#about to read 3, iclass 10, count 0 2006.168.08:00:01.96#ibcon#read 3, iclass 10, count 0 2006.168.08:00:01.96#ibcon#about to read 4, iclass 10, count 0 2006.168.08:00:01.96#ibcon#read 4, iclass 10, count 0 2006.168.08:00:01.96#ibcon#about to read 5, iclass 10, count 0 2006.168.08:00:01.96#ibcon#read 5, iclass 10, count 0 2006.168.08:00:01.96#ibcon#about to read 6, iclass 10, count 0 2006.168.08:00:01.96#ibcon#read 6, iclass 10, count 0 2006.168.08:00:01.96#ibcon#end of sib2, iclass 10, count 0 2006.168.08:00:01.96#ibcon#*mode == 0, iclass 10, count 0 2006.168.08:00:01.96#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.168.08:00:01.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.08:00:01.96#ibcon#*before write, iclass 10, count 0 2006.168.08:00:01.96#ibcon#enter sib2, iclass 10, count 0 2006.168.08:00:01.96#ibcon#flushed, iclass 10, count 0 2006.168.08:00:01.96#ibcon#about to write, iclass 10, count 0 2006.168.08:00:01.96#ibcon#wrote, iclass 10, count 0 2006.168.08:00:01.96#ibcon#about to read 3, iclass 10, count 0 2006.168.08:00:02.00#ibcon#read 3, iclass 10, count 0 2006.168.08:00:02.00#ibcon#about to read 4, iclass 10, count 0 2006.168.08:00:02.00#ibcon#read 4, iclass 10, count 0 2006.168.08:00:02.00#ibcon#about to read 5, iclass 10, count 0 2006.168.08:00:02.00#ibcon#read 5, iclass 10, count 0 2006.168.08:00:02.00#ibcon#about to read 6, iclass 10, count 0 2006.168.08:00:02.00#ibcon#read 6, iclass 10, count 0 2006.168.08:00:02.00#ibcon#end of sib2, iclass 10, count 0 2006.168.08:00:02.00#ibcon#*after write, iclass 10, count 0 2006.168.08:00:02.00#ibcon#*before return 0, iclass 10, count 0 2006.168.08:00:02.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:00:02.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:00:02.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.168.08:00:02.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.168.08:00:02.00$vc4f8/vb=5,4 2006.168.08:00:02.00#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.168.08:00:02.00#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.168.08:00:02.00#ibcon#ireg 11 cls_cnt 2 2006.168.08:00:02.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:00:02.06#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:00:02.06#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:00:02.06#ibcon#enter wrdev, iclass 12, count 2 2006.168.08:00:02.06#ibcon#first serial, iclass 12, count 2 2006.168.08:00:02.06#ibcon#enter sib2, iclass 12, count 2 2006.168.08:00:02.06#ibcon#flushed, iclass 12, count 2 2006.168.08:00:02.06#ibcon#about to write, iclass 12, count 2 2006.168.08:00:02.06#ibcon#wrote, iclass 12, count 2 2006.168.08:00:02.06#ibcon#about to read 3, iclass 12, count 2 2006.168.08:00:02.08#ibcon#read 3, iclass 12, count 2 2006.168.08:00:02.08#ibcon#about to read 4, iclass 12, count 2 2006.168.08:00:02.08#ibcon#read 4, iclass 12, count 2 2006.168.08:00:02.08#ibcon#about to read 5, iclass 12, count 2 2006.168.08:00:02.08#ibcon#read 5, iclass 12, count 2 2006.168.08:00:02.08#ibcon#about to read 6, iclass 12, count 2 2006.168.08:00:02.08#ibcon#read 6, iclass 12, count 2 2006.168.08:00:02.08#ibcon#end of sib2, iclass 12, count 2 2006.168.08:00:02.08#ibcon#*mode == 0, iclass 12, count 2 2006.168.08:00:02.08#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.168.08:00:02.08#ibcon#[27=AT05-04\r\n] 2006.168.08:00:02.08#ibcon#*before write, iclass 12, count 2 2006.168.08:00:02.08#ibcon#enter sib2, iclass 12, count 2 2006.168.08:00:02.08#ibcon#flushed, iclass 12, count 2 2006.168.08:00:02.08#ibcon#about to write, iclass 12, count 2 2006.168.08:00:02.08#ibcon#wrote, iclass 12, count 2 2006.168.08:00:02.08#ibcon#about to read 3, iclass 12, count 2 2006.168.08:00:02.11#ibcon#read 3, iclass 12, count 2 2006.168.08:00:02.11#ibcon#about to read 4, iclass 12, count 2 2006.168.08:00:02.11#ibcon#read 4, iclass 12, count 2 2006.168.08:00:02.11#ibcon#about to read 5, iclass 12, count 2 2006.168.08:00:02.11#ibcon#read 5, iclass 12, count 2 2006.168.08:00:02.11#ibcon#about to read 6, iclass 12, count 2 2006.168.08:00:02.11#ibcon#read 6, iclass 12, count 2 2006.168.08:00:02.11#ibcon#end of sib2, iclass 12, count 2 2006.168.08:00:02.11#ibcon#*after write, iclass 12, count 2 2006.168.08:00:02.11#ibcon#*before return 0, iclass 12, count 2 2006.168.08:00:02.11#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:00:02.11#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:00:02.11#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.168.08:00:02.11#ibcon#ireg 7 cls_cnt 0 2006.168.08:00:02.11#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:00:02.23#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:00:02.23#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:00:02.23#ibcon#enter wrdev, iclass 12, count 0 2006.168.08:00:02.23#ibcon#first serial, iclass 12, count 0 2006.168.08:00:02.23#ibcon#enter sib2, iclass 12, count 0 2006.168.08:00:02.23#ibcon#flushed, iclass 12, count 0 2006.168.08:00:02.23#ibcon#about to write, iclass 12, count 0 2006.168.08:00:02.23#ibcon#wrote, iclass 12, count 0 2006.168.08:00:02.23#ibcon#about to read 3, iclass 12, count 0 2006.168.08:00:02.25#ibcon#read 3, iclass 12, count 0 2006.168.08:00:02.25#ibcon#about to read 4, iclass 12, count 0 2006.168.08:00:02.25#ibcon#read 4, iclass 12, count 0 2006.168.08:00:02.25#ibcon#about to read 5, iclass 12, count 0 2006.168.08:00:02.25#ibcon#read 5, iclass 12, count 0 2006.168.08:00:02.25#ibcon#about to read 6, iclass 12, count 0 2006.168.08:00:02.25#ibcon#read 6, iclass 12, count 0 2006.168.08:00:02.25#ibcon#end of sib2, iclass 12, count 0 2006.168.08:00:02.25#ibcon#*mode == 0, iclass 12, count 0 2006.168.08:00:02.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.168.08:00:02.25#ibcon#[27=USB\r\n] 2006.168.08:00:02.25#ibcon#*before write, iclass 12, count 0 2006.168.08:00:02.25#ibcon#enter sib2, iclass 12, count 0 2006.168.08:00:02.25#ibcon#flushed, iclass 12, count 0 2006.168.08:00:02.25#ibcon#about to write, iclass 12, count 0 2006.168.08:00:02.25#ibcon#wrote, iclass 12, count 0 2006.168.08:00:02.25#ibcon#about to read 3, iclass 12, count 0 2006.168.08:00:02.28#ibcon#read 3, iclass 12, count 0 2006.168.08:00:02.28#ibcon#about to read 4, iclass 12, count 0 2006.168.08:00:02.28#ibcon#read 4, iclass 12, count 0 2006.168.08:00:02.28#ibcon#about to read 5, iclass 12, count 0 2006.168.08:00:02.28#ibcon#read 5, iclass 12, count 0 2006.168.08:00:02.28#ibcon#about to read 6, iclass 12, count 0 2006.168.08:00:02.28#ibcon#read 6, iclass 12, count 0 2006.168.08:00:02.28#ibcon#end of sib2, iclass 12, count 0 2006.168.08:00:02.28#ibcon#*after write, iclass 12, count 0 2006.168.08:00:02.28#ibcon#*before return 0, iclass 12, count 0 2006.168.08:00:02.28#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:00:02.28#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:00:02.28#ibcon#about to clear, iclass 12 cls_cnt 0 2006.168.08:00:02.28#ibcon#cleared, iclass 12 cls_cnt 0 2006.168.08:00:02.28$vc4f8/vblo=6,752.99 2006.168.08:00:02.28#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.168.08:00:02.28#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.168.08:00:02.28#ibcon#ireg 17 cls_cnt 0 2006.168.08:00:02.28#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:00:02.28#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:00:02.28#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:00:02.28#ibcon#enter wrdev, iclass 14, count 0 2006.168.08:00:02.28#ibcon#first serial, iclass 14, count 0 2006.168.08:00:02.28#ibcon#enter sib2, iclass 14, count 0 2006.168.08:00:02.28#ibcon#flushed, iclass 14, count 0 2006.168.08:00:02.28#ibcon#about to write, iclass 14, count 0 2006.168.08:00:02.28#ibcon#wrote, iclass 14, count 0 2006.168.08:00:02.28#ibcon#about to read 3, iclass 14, count 0 2006.168.08:00:02.30#ibcon#read 3, iclass 14, count 0 2006.168.08:00:02.30#ibcon#about to read 4, iclass 14, count 0 2006.168.08:00:02.30#ibcon#read 4, iclass 14, count 0 2006.168.08:00:02.30#ibcon#about to read 5, iclass 14, count 0 2006.168.08:00:02.30#ibcon#read 5, iclass 14, count 0 2006.168.08:00:02.30#ibcon#about to read 6, iclass 14, count 0 2006.168.08:00:02.30#ibcon#read 6, iclass 14, count 0 2006.168.08:00:02.30#ibcon#end of sib2, iclass 14, count 0 2006.168.08:00:02.30#ibcon#*mode == 0, iclass 14, count 0 2006.168.08:00:02.30#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.168.08:00:02.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.08:00:02.30#ibcon#*before write, iclass 14, count 0 2006.168.08:00:02.30#ibcon#enter sib2, iclass 14, count 0 2006.168.08:00:02.30#ibcon#flushed, iclass 14, count 0 2006.168.08:00:02.30#ibcon#about to write, iclass 14, count 0 2006.168.08:00:02.30#ibcon#wrote, iclass 14, count 0 2006.168.08:00:02.30#ibcon#about to read 3, iclass 14, count 0 2006.168.08:00:02.34#ibcon#read 3, iclass 14, count 0 2006.168.08:00:02.34#ibcon#about to read 4, iclass 14, count 0 2006.168.08:00:02.34#ibcon#read 4, iclass 14, count 0 2006.168.08:00:02.34#ibcon#about to read 5, iclass 14, count 0 2006.168.08:00:02.34#ibcon#read 5, iclass 14, count 0 2006.168.08:00:02.34#ibcon#about to read 6, iclass 14, count 0 2006.168.08:00:02.34#ibcon#read 6, iclass 14, count 0 2006.168.08:00:02.34#ibcon#end of sib2, iclass 14, count 0 2006.168.08:00:02.34#ibcon#*after write, iclass 14, count 0 2006.168.08:00:02.34#ibcon#*before return 0, iclass 14, count 0 2006.168.08:00:02.34#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:00:02.34#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:00:02.34#ibcon#about to clear, iclass 14 cls_cnt 0 2006.168.08:00:02.34#ibcon#cleared, iclass 14 cls_cnt 0 2006.168.08:00:02.34$vc4f8/vb=6,4 2006.168.08:00:02.34#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.168.08:00:02.34#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.168.08:00:02.34#ibcon#ireg 11 cls_cnt 2 2006.168.08:00:02.34#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:00:02.40#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:00:02.40#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:00:02.40#ibcon#enter wrdev, iclass 16, count 2 2006.168.08:00:02.40#ibcon#first serial, iclass 16, count 2 2006.168.08:00:02.40#ibcon#enter sib2, iclass 16, count 2 2006.168.08:00:02.40#ibcon#flushed, iclass 16, count 2 2006.168.08:00:02.40#ibcon#about to write, iclass 16, count 2 2006.168.08:00:02.40#ibcon#wrote, iclass 16, count 2 2006.168.08:00:02.40#ibcon#about to read 3, iclass 16, count 2 2006.168.08:00:02.42#ibcon#read 3, iclass 16, count 2 2006.168.08:00:02.42#ibcon#about to read 4, iclass 16, count 2 2006.168.08:00:02.42#ibcon#read 4, iclass 16, count 2 2006.168.08:00:02.42#ibcon#about to read 5, iclass 16, count 2 2006.168.08:00:02.42#ibcon#read 5, iclass 16, count 2 2006.168.08:00:02.42#ibcon#about to read 6, iclass 16, count 2 2006.168.08:00:02.42#ibcon#read 6, iclass 16, count 2 2006.168.08:00:02.42#ibcon#end of sib2, iclass 16, count 2 2006.168.08:00:02.42#ibcon#*mode == 0, iclass 16, count 2 2006.168.08:00:02.42#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.168.08:00:02.42#ibcon#[27=AT06-04\r\n] 2006.168.08:00:02.42#ibcon#*before write, iclass 16, count 2 2006.168.08:00:02.42#ibcon#enter sib2, iclass 16, count 2 2006.168.08:00:02.42#ibcon#flushed, iclass 16, count 2 2006.168.08:00:02.42#ibcon#about to write, iclass 16, count 2 2006.168.08:00:02.42#ibcon#wrote, iclass 16, count 2 2006.168.08:00:02.42#ibcon#about to read 3, iclass 16, count 2 2006.168.08:00:02.45#ibcon#read 3, iclass 16, count 2 2006.168.08:00:02.45#ibcon#about to read 4, iclass 16, count 2 2006.168.08:00:02.45#ibcon#read 4, iclass 16, count 2 2006.168.08:00:02.45#ibcon#about to read 5, iclass 16, count 2 2006.168.08:00:02.45#ibcon#read 5, iclass 16, count 2 2006.168.08:00:02.45#ibcon#about to read 6, iclass 16, count 2 2006.168.08:00:02.45#ibcon#read 6, iclass 16, count 2 2006.168.08:00:02.45#ibcon#end of sib2, iclass 16, count 2 2006.168.08:00:02.45#ibcon#*after write, iclass 16, count 2 2006.168.08:00:02.45#ibcon#*before return 0, iclass 16, count 2 2006.168.08:00:02.45#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:00:02.45#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:00:02.45#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.168.08:00:02.45#ibcon#ireg 7 cls_cnt 0 2006.168.08:00:02.45#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:00:02.57#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:00:02.57#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:00:02.57#ibcon#enter wrdev, iclass 16, count 0 2006.168.08:00:02.57#ibcon#first serial, iclass 16, count 0 2006.168.08:00:02.57#ibcon#enter sib2, iclass 16, count 0 2006.168.08:00:02.57#ibcon#flushed, iclass 16, count 0 2006.168.08:00:02.57#ibcon#about to write, iclass 16, count 0 2006.168.08:00:02.57#ibcon#wrote, iclass 16, count 0 2006.168.08:00:02.57#ibcon#about to read 3, iclass 16, count 0 2006.168.08:00:02.59#ibcon#read 3, iclass 16, count 0 2006.168.08:00:02.59#ibcon#about to read 4, iclass 16, count 0 2006.168.08:00:02.59#ibcon#read 4, iclass 16, count 0 2006.168.08:00:02.59#ibcon#about to read 5, iclass 16, count 0 2006.168.08:00:02.59#ibcon#read 5, iclass 16, count 0 2006.168.08:00:02.59#ibcon#about to read 6, iclass 16, count 0 2006.168.08:00:02.59#ibcon#read 6, iclass 16, count 0 2006.168.08:00:02.59#ibcon#end of sib2, iclass 16, count 0 2006.168.08:00:02.59#ibcon#*mode == 0, iclass 16, count 0 2006.168.08:00:02.59#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.168.08:00:02.59#ibcon#[27=USB\r\n] 2006.168.08:00:02.59#ibcon#*before write, iclass 16, count 0 2006.168.08:00:02.59#ibcon#enter sib2, iclass 16, count 0 2006.168.08:00:02.59#ibcon#flushed, iclass 16, count 0 2006.168.08:00:02.59#ibcon#about to write, iclass 16, count 0 2006.168.08:00:02.59#ibcon#wrote, iclass 16, count 0 2006.168.08:00:02.59#ibcon#about to read 3, iclass 16, count 0 2006.168.08:00:02.62#ibcon#read 3, iclass 16, count 0 2006.168.08:00:02.62#ibcon#about to read 4, iclass 16, count 0 2006.168.08:00:02.62#ibcon#read 4, iclass 16, count 0 2006.168.08:00:02.62#ibcon#about to read 5, iclass 16, count 0 2006.168.08:00:02.62#ibcon#read 5, iclass 16, count 0 2006.168.08:00:02.62#ibcon#about to read 6, iclass 16, count 0 2006.168.08:00:02.62#ibcon#read 6, iclass 16, count 0 2006.168.08:00:02.62#ibcon#end of sib2, iclass 16, count 0 2006.168.08:00:02.62#ibcon#*after write, iclass 16, count 0 2006.168.08:00:02.62#ibcon#*before return 0, iclass 16, count 0 2006.168.08:00:02.62#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:00:02.62#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:00:02.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.168.08:00:02.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.168.08:00:02.62$vc4f8/vabw=wide 2006.168.08:00:02.62#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.168.08:00:02.62#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.168.08:00:02.62#ibcon#ireg 8 cls_cnt 0 2006.168.08:00:02.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:00:02.62#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:00:02.62#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:00:02.62#ibcon#enter wrdev, iclass 18, count 0 2006.168.08:00:02.62#ibcon#first serial, iclass 18, count 0 2006.168.08:00:02.62#ibcon#enter sib2, iclass 18, count 0 2006.168.08:00:02.62#ibcon#flushed, iclass 18, count 0 2006.168.08:00:02.62#ibcon#about to write, iclass 18, count 0 2006.168.08:00:02.62#ibcon#wrote, iclass 18, count 0 2006.168.08:00:02.62#ibcon#about to read 3, iclass 18, count 0 2006.168.08:00:02.64#ibcon#read 3, iclass 18, count 0 2006.168.08:00:02.64#ibcon#about to read 4, iclass 18, count 0 2006.168.08:00:02.64#ibcon#read 4, iclass 18, count 0 2006.168.08:00:02.64#ibcon#about to read 5, iclass 18, count 0 2006.168.08:00:02.64#ibcon#read 5, iclass 18, count 0 2006.168.08:00:02.64#ibcon#about to read 6, iclass 18, count 0 2006.168.08:00:02.64#ibcon#read 6, iclass 18, count 0 2006.168.08:00:02.64#ibcon#end of sib2, iclass 18, count 0 2006.168.08:00:02.64#ibcon#*mode == 0, iclass 18, count 0 2006.168.08:00:02.64#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.08:00:02.64#ibcon#[25=BW32\r\n] 2006.168.08:00:02.64#ibcon#*before write, iclass 18, count 0 2006.168.08:00:02.64#ibcon#enter sib2, iclass 18, count 0 2006.168.08:00:02.64#ibcon#flushed, iclass 18, count 0 2006.168.08:00:02.64#ibcon#about to write, iclass 18, count 0 2006.168.08:00:02.64#ibcon#wrote, iclass 18, count 0 2006.168.08:00:02.64#ibcon#about to read 3, iclass 18, count 0 2006.168.08:00:02.67#ibcon#read 3, iclass 18, count 0 2006.168.08:00:02.67#ibcon#about to read 4, iclass 18, count 0 2006.168.08:00:02.67#ibcon#read 4, iclass 18, count 0 2006.168.08:00:02.67#ibcon#about to read 5, iclass 18, count 0 2006.168.08:00:02.67#ibcon#read 5, iclass 18, count 0 2006.168.08:00:02.67#ibcon#about to read 6, iclass 18, count 0 2006.168.08:00:02.67#ibcon#read 6, iclass 18, count 0 2006.168.08:00:02.67#ibcon#end of sib2, iclass 18, count 0 2006.168.08:00:02.67#ibcon#*after write, iclass 18, count 0 2006.168.08:00:02.67#ibcon#*before return 0, iclass 18, count 0 2006.168.08:00:02.67#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:00:02.67#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:00:02.67#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.08:00:02.67#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.08:00:02.67$vc4f8/vbbw=wide 2006.168.08:00:02.67#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.168.08:00:02.67#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.168.08:00:02.67#ibcon#ireg 8 cls_cnt 0 2006.168.08:00:02.67#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:00:02.75#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:00:02.75#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:00:02.75#ibcon#enter wrdev, iclass 20, count 0 2006.168.08:00:02.75#ibcon#first serial, iclass 20, count 0 2006.168.08:00:02.75#ibcon#enter sib2, iclass 20, count 0 2006.168.08:00:02.75#ibcon#flushed, iclass 20, count 0 2006.168.08:00:02.75#ibcon#about to write, iclass 20, count 0 2006.168.08:00:02.75#ibcon#wrote, iclass 20, count 0 2006.168.08:00:02.75#ibcon#about to read 3, iclass 20, count 0 2006.168.08:00:02.76#ibcon#read 3, iclass 20, count 0 2006.168.08:00:02.76#ibcon#about to read 4, iclass 20, count 0 2006.168.08:00:02.76#ibcon#read 4, iclass 20, count 0 2006.168.08:00:02.76#ibcon#about to read 5, iclass 20, count 0 2006.168.08:00:02.76#ibcon#read 5, iclass 20, count 0 2006.168.08:00:02.76#ibcon#about to read 6, iclass 20, count 0 2006.168.08:00:02.76#ibcon#read 6, iclass 20, count 0 2006.168.08:00:02.76#ibcon#end of sib2, iclass 20, count 0 2006.168.08:00:02.76#ibcon#*mode == 0, iclass 20, count 0 2006.168.08:00:02.76#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.168.08:00:02.76#ibcon#[27=BW32\r\n] 2006.168.08:00:02.76#ibcon#*before write, iclass 20, count 0 2006.168.08:00:02.76#ibcon#enter sib2, iclass 20, count 0 2006.168.08:00:02.76#ibcon#flushed, iclass 20, count 0 2006.168.08:00:02.76#ibcon#about to write, iclass 20, count 0 2006.168.08:00:02.76#ibcon#wrote, iclass 20, count 0 2006.168.08:00:02.76#ibcon#about to read 3, iclass 20, count 0 2006.168.08:00:02.79#ibcon#read 3, iclass 20, count 0 2006.168.08:00:02.79#ibcon#about to read 4, iclass 20, count 0 2006.168.08:00:02.79#ibcon#read 4, iclass 20, count 0 2006.168.08:00:02.79#ibcon#about to read 5, iclass 20, count 0 2006.168.08:00:02.79#ibcon#read 5, iclass 20, count 0 2006.168.08:00:02.79#ibcon#about to read 6, iclass 20, count 0 2006.168.08:00:02.79#ibcon#read 6, iclass 20, count 0 2006.168.08:00:02.79#ibcon#end of sib2, iclass 20, count 0 2006.168.08:00:02.79#ibcon#*after write, iclass 20, count 0 2006.168.08:00:02.79#ibcon#*before return 0, iclass 20, count 0 2006.168.08:00:02.79#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:00:02.79#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:00:02.79#ibcon#about to clear, iclass 20 cls_cnt 0 2006.168.08:00:02.79#ibcon#cleared, iclass 20 cls_cnt 0 2006.168.08:00:02.79$4f8m12a/ifd4f 2006.168.08:00:02.79$ifd4f/lo= 2006.168.08:00:02.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.08:00:02.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.08:00:02.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.08:00:02.79$ifd4f/patch= 2006.168.08:00:02.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.08:00:02.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.08:00:02.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.08:00:02.79$4f8m12a/"form=m,16.000,1:2 2006.168.08:00:02.79$4f8m12a/"tpicd 2006.168.08:00:02.79$4f8m12a/echo=off 2006.168.08:00:02.79$4f8m12a/xlog=off 2006.168.08:00:02.79:!2006.168.08:01:10 2006.168.08:00:48.14#trakl#Source acquired 2006.168.08:00:48.14#flagr#flagr/antenna,acquired 2006.168.08:01:10.00:preob 2006.168.08:01:10.13/onsource/TRACKING 2006.168.08:01:10.13:!2006.168.08:01:20 2006.168.08:01:20.00:data_valid=on 2006.168.08:01:20.00:midob 2006.168.08:01:21.13/onsource/TRACKING 2006.168.08:01:21.13/wx/27.04,1004.5,72 2006.168.08:01:21.33/cable/+6.4699E-03 2006.168.08:01:22.42/va/01,08,usb,yes,29,30 2006.168.08:01:22.42/va/02,07,usb,yes,29,30 2006.168.08:01:22.42/va/03,06,usb,yes,30,31 2006.168.08:01:22.42/va/04,07,usb,yes,30,32 2006.168.08:01:22.42/va/05,07,usb,yes,30,31 2006.168.08:01:22.42/va/06,06,usb,yes,29,29 2006.168.08:01:22.42/va/07,06,usb,yes,29,29 2006.168.08:01:22.42/va/08,07,usb,yes,28,27 2006.168.08:01:22.65/valo/01,532.99,yes,locked 2006.168.08:01:22.65/valo/02,572.99,yes,locked 2006.168.08:01:22.65/valo/03,672.99,yes,locked 2006.168.08:01:22.65/valo/04,832.99,yes,locked 2006.168.08:01:22.65/valo/05,652.99,yes,locked 2006.168.08:01:22.65/valo/06,772.99,yes,locked 2006.168.08:01:22.65/valo/07,832.99,yes,locked 2006.168.08:01:22.65/valo/08,852.99,yes,locked 2006.168.08:01:23.74/vb/01,04,usb,yes,29,27 2006.168.08:01:23.74/vb/02,04,usb,yes,31,32 2006.168.08:01:23.74/vb/03,04,usb,yes,27,31 2006.168.08:01:23.74/vb/04,04,usb,yes,28,28 2006.168.08:01:23.74/vb/05,04,usb,yes,27,30 2006.168.08:01:23.74/vb/06,04,usb,yes,28,30 2006.168.08:01:23.74/vb/07,04,usb,yes,29,29 2006.168.08:01:23.74/vb/08,04,usb,yes,28,30 2006.168.08:01:23.97/vblo/01,632.99,yes,locked 2006.168.08:01:23.97/vblo/02,640.99,yes,locked 2006.168.08:01:23.97/vblo/03,656.99,yes,locked 2006.168.08:01:23.97/vblo/04,712.99,yes,locked 2006.168.08:01:23.97/vblo/05,744.99,yes,locked 2006.168.08:01:23.97/vblo/06,752.99,yes,locked 2006.168.08:01:23.97/vblo/07,734.99,yes,locked 2006.168.08:01:23.97/vblo/08,744.99,yes,locked 2006.168.08:01:24.12/vabw/8 2006.168.08:01:24.27/vbbw/8 2006.168.08:01:24.36/xfe/off,on,15.2 2006.168.08:01:24.73/ifatt/23,28,28,28 2006.168.08:01:25.07/fmout-gps/S +4.21E-07 2006.168.08:01:25.15:!2006.168.08:02:20 2006.168.08:02:20.00:data_valid=off 2006.168.08:02:20.00:postob 2006.168.08:02:20.17/cable/+6.4707E-03 2006.168.08:02:20.18/wx/27.02,1004.5,73 2006.168.08:02:21.08/fmout-gps/S +4.20E-07 2006.168.08:02:21.08:scan_name=168-0803,k06168,60 2006.168.08:02:21.09:source=1739+522,174036.98,521143.4,2000.0,cw 2006.168.08:02:21.13#flagr#flagr/antenna,new-source 2006.168.08:02:22.13:checkk5 2006.168.08:02:22.50/chk_autoobs//k5ts1/ autoobs is running! 2006.168.08:02:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.168.08:02:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.168.08:02:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.168.08:02:24.02/chk_obsdata//k5ts1/T1680801??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:02:24.39/chk_obsdata//k5ts2/T1680801??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:02:24.75/chk_obsdata//k5ts3/T1680801??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:02:25.13/chk_obsdata//k5ts4/T1680801??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:02:25.83/k5log//k5ts1_log_newline 2006.168.08:02:26.51/k5log//k5ts2_log_newline 2006.168.08:02:27.21/k5log//k5ts3_log_newline 2006.168.08:02:27.90/k5log//k5ts4_log_newline 2006.168.08:02:27.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.08:02:27.92:4f8m12a=2 2006.168.08:02:27.92$4f8m12a/echo=on 2006.168.08:02:27.92$4f8m12a/pcalon 2006.168.08:02:27.92$pcalon/"no phase cal control is implemented here 2006.168.08:02:27.92$4f8m12a/"tpicd=stop 2006.168.08:02:27.92$4f8m12a/vc4f8 2006.168.08:02:27.92$vc4f8/valo=1,532.99 2006.168.08:02:27.92#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.168.08:02:27.92#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.168.08:02:27.92#ibcon#ireg 17 cls_cnt 0 2006.168.08:02:27.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.168.08:02:27.92#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.168.08:02:27.92#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.168.08:02:27.92#ibcon#enter wrdev, iclass 5, count 0 2006.168.08:02:27.92#ibcon#first serial, iclass 5, count 0 2006.168.08:02:27.92#ibcon#enter sib2, iclass 5, count 0 2006.168.08:02:27.92#ibcon#flushed, iclass 5, count 0 2006.168.08:02:27.92#ibcon#about to write, iclass 5, count 0 2006.168.08:02:27.92#ibcon#wrote, iclass 5, count 0 2006.168.08:02:27.92#ibcon#about to read 3, iclass 5, count 0 2006.168.08:02:27.97#ibcon#read 3, iclass 5, count 0 2006.168.08:02:27.97#ibcon#about to read 4, iclass 5, count 0 2006.168.08:02:27.97#ibcon#read 4, iclass 5, count 0 2006.168.08:02:27.97#ibcon#about to read 5, iclass 5, count 0 2006.168.08:02:27.97#ibcon#read 5, iclass 5, count 0 2006.168.08:02:27.97#ibcon#about to read 6, iclass 5, count 0 2006.168.08:02:27.97#ibcon#read 6, iclass 5, count 0 2006.168.08:02:27.97#ibcon#end of sib2, iclass 5, count 0 2006.168.08:02:27.97#ibcon#*mode == 0, iclass 5, count 0 2006.168.08:02:27.97#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.168.08:02:27.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.08:02:27.97#ibcon#*before write, iclass 5, count 0 2006.168.08:02:27.97#ibcon#enter sib2, iclass 5, count 0 2006.168.08:02:27.97#ibcon#flushed, iclass 5, count 0 2006.168.08:02:27.97#ibcon#about to write, iclass 5, count 0 2006.168.08:02:27.97#ibcon#wrote, iclass 5, count 0 2006.168.08:02:27.97#ibcon#about to read 3, iclass 5, count 0 2006.168.08:02:28.02#ibcon#read 3, iclass 5, count 0 2006.168.08:02:28.02#ibcon#about to read 4, iclass 5, count 0 2006.168.08:02:28.02#ibcon#read 4, iclass 5, count 0 2006.168.08:02:28.02#ibcon#about to read 5, iclass 5, count 0 2006.168.08:02:28.02#ibcon#read 5, iclass 5, count 0 2006.168.08:02:28.02#ibcon#about to read 6, iclass 5, count 0 2006.168.08:02:28.02#ibcon#read 6, iclass 5, count 0 2006.168.08:02:28.02#ibcon#end of sib2, iclass 5, count 0 2006.168.08:02:28.02#ibcon#*after write, iclass 5, count 0 2006.168.08:02:28.02#ibcon#*before return 0, iclass 5, count 0 2006.168.08:02:28.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.168.08:02:28.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.168.08:02:28.02#ibcon#about to clear, iclass 5 cls_cnt 0 2006.168.08:02:28.02#ibcon#cleared, iclass 5 cls_cnt 0 2006.168.08:02:28.02$vc4f8/va=1,8 2006.168.08:02:28.02#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.168.08:02:28.02#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.168.08:02:28.02#ibcon#ireg 11 cls_cnt 2 2006.168.08:02:28.02#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.168.08:02:28.02#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.168.08:02:28.02#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.168.08:02:28.02#ibcon#enter wrdev, iclass 7, count 2 2006.168.08:02:28.02#ibcon#first serial, iclass 7, count 2 2006.168.08:02:28.02#ibcon#enter sib2, iclass 7, count 2 2006.168.08:02:28.02#ibcon#flushed, iclass 7, count 2 2006.168.08:02:28.02#ibcon#about to write, iclass 7, count 2 2006.168.08:02:28.02#ibcon#wrote, iclass 7, count 2 2006.168.08:02:28.02#ibcon#about to read 3, iclass 7, count 2 2006.168.08:02:28.05#ibcon#read 3, iclass 7, count 2 2006.168.08:02:28.05#ibcon#about to read 4, iclass 7, count 2 2006.168.08:02:28.05#ibcon#read 4, iclass 7, count 2 2006.168.08:02:28.05#ibcon#about to read 5, iclass 7, count 2 2006.168.08:02:28.05#ibcon#read 5, iclass 7, count 2 2006.168.08:02:28.05#ibcon#about to read 6, iclass 7, count 2 2006.168.08:02:28.05#ibcon#read 6, iclass 7, count 2 2006.168.08:02:28.05#ibcon#end of sib2, iclass 7, count 2 2006.168.08:02:28.05#ibcon#*mode == 0, iclass 7, count 2 2006.168.08:02:28.05#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.168.08:02:28.05#ibcon#[25=AT01-08\r\n] 2006.168.08:02:28.05#ibcon#*before write, iclass 7, count 2 2006.168.08:02:28.05#ibcon#enter sib2, iclass 7, count 2 2006.168.08:02:28.05#ibcon#flushed, iclass 7, count 2 2006.168.08:02:28.05#ibcon#about to write, iclass 7, count 2 2006.168.08:02:28.05#ibcon#wrote, iclass 7, count 2 2006.168.08:02:28.05#ibcon#about to read 3, iclass 7, count 2 2006.168.08:02:28.08#ibcon#read 3, iclass 7, count 2 2006.168.08:02:28.08#ibcon#about to read 4, iclass 7, count 2 2006.168.08:02:28.08#ibcon#read 4, iclass 7, count 2 2006.168.08:02:28.08#ibcon#about to read 5, iclass 7, count 2 2006.168.08:02:28.08#ibcon#read 5, iclass 7, count 2 2006.168.08:02:28.08#ibcon#about to read 6, iclass 7, count 2 2006.168.08:02:28.08#ibcon#read 6, iclass 7, count 2 2006.168.08:02:28.08#ibcon#end of sib2, iclass 7, count 2 2006.168.08:02:28.08#ibcon#*after write, iclass 7, count 2 2006.168.08:02:28.08#ibcon#*before return 0, iclass 7, count 2 2006.168.08:02:28.08#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.168.08:02:28.08#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.168.08:02:28.08#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.168.08:02:28.08#ibcon#ireg 7 cls_cnt 0 2006.168.08:02:28.08#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.168.08:02:28.20#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.168.08:02:28.20#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.168.08:02:28.20#ibcon#enter wrdev, iclass 7, count 0 2006.168.08:02:28.20#ibcon#first serial, iclass 7, count 0 2006.168.08:02:28.20#ibcon#enter sib2, iclass 7, count 0 2006.168.08:02:28.20#ibcon#flushed, iclass 7, count 0 2006.168.08:02:28.20#ibcon#about to write, iclass 7, count 0 2006.168.08:02:28.20#ibcon#wrote, iclass 7, count 0 2006.168.08:02:28.20#ibcon#about to read 3, iclass 7, count 0 2006.168.08:02:28.22#ibcon#read 3, iclass 7, count 0 2006.168.08:02:28.22#ibcon#about to read 4, iclass 7, count 0 2006.168.08:02:28.22#ibcon#read 4, iclass 7, count 0 2006.168.08:02:28.22#ibcon#about to read 5, iclass 7, count 0 2006.168.08:02:28.22#ibcon#read 5, iclass 7, count 0 2006.168.08:02:28.22#ibcon#about to read 6, iclass 7, count 0 2006.168.08:02:28.22#ibcon#read 6, iclass 7, count 0 2006.168.08:02:28.22#ibcon#end of sib2, iclass 7, count 0 2006.168.08:02:28.22#ibcon#*mode == 0, iclass 7, count 0 2006.168.08:02:28.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.168.08:02:28.22#ibcon#[25=USB\r\n] 2006.168.08:02:28.22#ibcon#*before write, iclass 7, count 0 2006.168.08:02:28.22#ibcon#enter sib2, iclass 7, count 0 2006.168.08:02:28.22#ibcon#flushed, iclass 7, count 0 2006.168.08:02:28.22#ibcon#about to write, iclass 7, count 0 2006.168.08:02:28.22#ibcon#wrote, iclass 7, count 0 2006.168.08:02:28.22#ibcon#about to read 3, iclass 7, count 0 2006.168.08:02:28.25#ibcon#read 3, iclass 7, count 0 2006.168.08:02:28.25#ibcon#about to read 4, iclass 7, count 0 2006.168.08:02:28.25#ibcon#read 4, iclass 7, count 0 2006.168.08:02:28.25#ibcon#about to read 5, iclass 7, count 0 2006.168.08:02:28.25#ibcon#read 5, iclass 7, count 0 2006.168.08:02:28.25#ibcon#about to read 6, iclass 7, count 0 2006.168.08:02:28.25#ibcon#read 6, iclass 7, count 0 2006.168.08:02:28.25#ibcon#end of sib2, iclass 7, count 0 2006.168.08:02:28.25#ibcon#*after write, iclass 7, count 0 2006.168.08:02:28.25#ibcon#*before return 0, iclass 7, count 0 2006.168.08:02:28.25#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.168.08:02:28.25#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.168.08:02:28.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.168.08:02:28.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.168.08:02:28.25$vc4f8/valo=2,572.99 2006.168.08:02:28.25#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.168.08:02:28.25#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.168.08:02:28.25#ibcon#ireg 17 cls_cnt 0 2006.168.08:02:28.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.168.08:02:28.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.168.08:02:28.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.168.08:02:28.25#ibcon#enter wrdev, iclass 11, count 0 2006.168.08:02:28.25#ibcon#first serial, iclass 11, count 0 2006.168.08:02:28.25#ibcon#enter sib2, iclass 11, count 0 2006.168.08:02:28.25#ibcon#flushed, iclass 11, count 0 2006.168.08:02:28.25#ibcon#about to write, iclass 11, count 0 2006.168.08:02:28.25#ibcon#wrote, iclass 11, count 0 2006.168.08:02:28.25#ibcon#about to read 3, iclass 11, count 0 2006.168.08:02:28.27#ibcon#read 3, iclass 11, count 0 2006.168.08:02:28.27#ibcon#about to read 4, iclass 11, count 0 2006.168.08:02:28.27#ibcon#read 4, iclass 11, count 0 2006.168.08:02:28.27#ibcon#about to read 5, iclass 11, count 0 2006.168.08:02:28.27#ibcon#read 5, iclass 11, count 0 2006.168.08:02:28.27#ibcon#about to read 6, iclass 11, count 0 2006.168.08:02:28.27#ibcon#read 6, iclass 11, count 0 2006.168.08:02:28.27#ibcon#end of sib2, iclass 11, count 0 2006.168.08:02:28.27#ibcon#*mode == 0, iclass 11, count 0 2006.168.08:02:28.27#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.168.08:02:28.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.08:02:28.27#ibcon#*before write, iclass 11, count 0 2006.168.08:02:28.27#ibcon#enter sib2, iclass 11, count 0 2006.168.08:02:28.27#ibcon#flushed, iclass 11, count 0 2006.168.08:02:28.27#ibcon#about to write, iclass 11, count 0 2006.168.08:02:28.27#ibcon#wrote, iclass 11, count 0 2006.168.08:02:28.27#ibcon#about to read 3, iclass 11, count 0 2006.168.08:02:28.31#ibcon#read 3, iclass 11, count 0 2006.168.08:02:28.31#ibcon#about to read 4, iclass 11, count 0 2006.168.08:02:28.31#ibcon#read 4, iclass 11, count 0 2006.168.08:02:28.31#ibcon#about to read 5, iclass 11, count 0 2006.168.08:02:28.31#ibcon#read 5, iclass 11, count 0 2006.168.08:02:28.31#ibcon#about to read 6, iclass 11, count 0 2006.168.08:02:28.31#ibcon#read 6, iclass 11, count 0 2006.168.08:02:28.31#ibcon#end of sib2, iclass 11, count 0 2006.168.08:02:28.31#ibcon#*after write, iclass 11, count 0 2006.168.08:02:28.31#ibcon#*before return 0, iclass 11, count 0 2006.168.08:02:28.31#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.168.08:02:28.31#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.168.08:02:28.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.168.08:02:28.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.168.08:02:28.31$vc4f8/va=2,7 2006.168.08:02:28.31#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.168.08:02:28.31#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.168.08:02:28.31#ibcon#ireg 11 cls_cnt 2 2006.168.08:02:28.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.168.08:02:28.37#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.168.08:02:28.37#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.168.08:02:28.37#ibcon#enter wrdev, iclass 13, count 2 2006.168.08:02:28.37#ibcon#first serial, iclass 13, count 2 2006.168.08:02:28.37#ibcon#enter sib2, iclass 13, count 2 2006.168.08:02:28.37#ibcon#flushed, iclass 13, count 2 2006.168.08:02:28.37#ibcon#about to write, iclass 13, count 2 2006.168.08:02:28.37#ibcon#wrote, iclass 13, count 2 2006.168.08:02:28.37#ibcon#about to read 3, iclass 13, count 2 2006.168.08:02:28.39#ibcon#read 3, iclass 13, count 2 2006.168.08:02:28.39#ibcon#about to read 4, iclass 13, count 2 2006.168.08:02:28.39#ibcon#read 4, iclass 13, count 2 2006.168.08:02:28.39#ibcon#about to read 5, iclass 13, count 2 2006.168.08:02:28.39#ibcon#read 5, iclass 13, count 2 2006.168.08:02:28.39#ibcon#about to read 6, iclass 13, count 2 2006.168.08:02:28.39#ibcon#read 6, iclass 13, count 2 2006.168.08:02:28.39#ibcon#end of sib2, iclass 13, count 2 2006.168.08:02:28.39#ibcon#*mode == 0, iclass 13, count 2 2006.168.08:02:28.39#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.168.08:02:28.39#ibcon#[25=AT02-07\r\n] 2006.168.08:02:28.39#ibcon#*before write, iclass 13, count 2 2006.168.08:02:28.39#ibcon#enter sib2, iclass 13, count 2 2006.168.08:02:28.39#ibcon#flushed, iclass 13, count 2 2006.168.08:02:28.39#ibcon#about to write, iclass 13, count 2 2006.168.08:02:28.39#ibcon#wrote, iclass 13, count 2 2006.168.08:02:28.39#ibcon#about to read 3, iclass 13, count 2 2006.168.08:02:28.42#ibcon#read 3, iclass 13, count 2 2006.168.08:02:28.42#ibcon#about to read 4, iclass 13, count 2 2006.168.08:02:28.42#ibcon#read 4, iclass 13, count 2 2006.168.08:02:28.42#ibcon#about to read 5, iclass 13, count 2 2006.168.08:02:28.42#ibcon#read 5, iclass 13, count 2 2006.168.08:02:28.42#ibcon#about to read 6, iclass 13, count 2 2006.168.08:02:28.42#ibcon#read 6, iclass 13, count 2 2006.168.08:02:28.42#ibcon#end of sib2, iclass 13, count 2 2006.168.08:02:28.42#ibcon#*after write, iclass 13, count 2 2006.168.08:02:28.42#ibcon#*before return 0, iclass 13, count 2 2006.168.08:02:28.42#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.168.08:02:28.42#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.168.08:02:28.42#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.168.08:02:28.42#ibcon#ireg 7 cls_cnt 0 2006.168.08:02:28.42#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.168.08:02:28.54#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.168.08:02:28.54#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.168.08:02:28.54#ibcon#enter wrdev, iclass 13, count 0 2006.168.08:02:28.54#ibcon#first serial, iclass 13, count 0 2006.168.08:02:28.54#ibcon#enter sib2, iclass 13, count 0 2006.168.08:02:28.54#ibcon#flushed, iclass 13, count 0 2006.168.08:02:28.54#ibcon#about to write, iclass 13, count 0 2006.168.08:02:28.54#ibcon#wrote, iclass 13, count 0 2006.168.08:02:28.54#ibcon#about to read 3, iclass 13, count 0 2006.168.08:02:28.56#ibcon#read 3, iclass 13, count 0 2006.168.08:02:28.56#ibcon#about to read 4, iclass 13, count 0 2006.168.08:02:28.56#ibcon#read 4, iclass 13, count 0 2006.168.08:02:28.56#ibcon#about to read 5, iclass 13, count 0 2006.168.08:02:28.56#ibcon#read 5, iclass 13, count 0 2006.168.08:02:28.56#ibcon#about to read 6, iclass 13, count 0 2006.168.08:02:28.56#ibcon#read 6, iclass 13, count 0 2006.168.08:02:28.56#ibcon#end of sib2, iclass 13, count 0 2006.168.08:02:28.56#ibcon#*mode == 0, iclass 13, count 0 2006.168.08:02:28.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.168.08:02:28.56#ibcon#[25=USB\r\n] 2006.168.08:02:28.56#ibcon#*before write, iclass 13, count 0 2006.168.08:02:28.56#ibcon#enter sib2, iclass 13, count 0 2006.168.08:02:28.56#ibcon#flushed, iclass 13, count 0 2006.168.08:02:28.56#ibcon#about to write, iclass 13, count 0 2006.168.08:02:28.56#ibcon#wrote, iclass 13, count 0 2006.168.08:02:28.56#ibcon#about to read 3, iclass 13, count 0 2006.168.08:02:28.59#ibcon#read 3, iclass 13, count 0 2006.168.08:02:28.59#ibcon#about to read 4, iclass 13, count 0 2006.168.08:02:28.59#ibcon#read 4, iclass 13, count 0 2006.168.08:02:28.59#ibcon#about to read 5, iclass 13, count 0 2006.168.08:02:28.59#ibcon#read 5, iclass 13, count 0 2006.168.08:02:28.59#ibcon#about to read 6, iclass 13, count 0 2006.168.08:02:28.59#ibcon#read 6, iclass 13, count 0 2006.168.08:02:28.59#ibcon#end of sib2, iclass 13, count 0 2006.168.08:02:28.59#ibcon#*after write, iclass 13, count 0 2006.168.08:02:28.59#ibcon#*before return 0, iclass 13, count 0 2006.168.08:02:28.59#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.168.08:02:28.59#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.168.08:02:28.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.168.08:02:28.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.168.08:02:28.59$vc4f8/valo=3,672.99 2006.168.08:02:28.59#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.168.08:02:28.59#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.168.08:02:28.59#ibcon#ireg 17 cls_cnt 0 2006.168.08:02:28.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:02:28.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:02:28.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:02:28.59#ibcon#enter wrdev, iclass 15, count 0 2006.168.08:02:28.59#ibcon#first serial, iclass 15, count 0 2006.168.08:02:28.59#ibcon#enter sib2, iclass 15, count 0 2006.168.08:02:28.59#ibcon#flushed, iclass 15, count 0 2006.168.08:02:28.59#ibcon#about to write, iclass 15, count 0 2006.168.08:02:28.59#ibcon#wrote, iclass 15, count 0 2006.168.08:02:28.59#ibcon#about to read 3, iclass 15, count 0 2006.168.08:02:28.61#ibcon#read 3, iclass 15, count 0 2006.168.08:02:28.61#ibcon#about to read 4, iclass 15, count 0 2006.168.08:02:28.61#ibcon#read 4, iclass 15, count 0 2006.168.08:02:28.61#ibcon#about to read 5, iclass 15, count 0 2006.168.08:02:28.61#ibcon#read 5, iclass 15, count 0 2006.168.08:02:28.61#ibcon#about to read 6, iclass 15, count 0 2006.168.08:02:28.61#ibcon#read 6, iclass 15, count 0 2006.168.08:02:28.61#ibcon#end of sib2, iclass 15, count 0 2006.168.08:02:28.61#ibcon#*mode == 0, iclass 15, count 0 2006.168.08:02:28.61#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.168.08:02:28.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.08:02:28.61#ibcon#*before write, iclass 15, count 0 2006.168.08:02:28.61#ibcon#enter sib2, iclass 15, count 0 2006.168.08:02:28.61#ibcon#flushed, iclass 15, count 0 2006.168.08:02:28.61#ibcon#about to write, iclass 15, count 0 2006.168.08:02:28.61#ibcon#wrote, iclass 15, count 0 2006.168.08:02:28.61#ibcon#about to read 3, iclass 15, count 0 2006.168.08:02:28.65#ibcon#read 3, iclass 15, count 0 2006.168.08:02:28.65#ibcon#about to read 4, iclass 15, count 0 2006.168.08:02:28.65#ibcon#read 4, iclass 15, count 0 2006.168.08:02:28.65#ibcon#about to read 5, iclass 15, count 0 2006.168.08:02:28.65#ibcon#read 5, iclass 15, count 0 2006.168.08:02:28.65#ibcon#about to read 6, iclass 15, count 0 2006.168.08:02:28.65#ibcon#read 6, iclass 15, count 0 2006.168.08:02:28.65#ibcon#end of sib2, iclass 15, count 0 2006.168.08:02:28.65#ibcon#*after write, iclass 15, count 0 2006.168.08:02:28.65#ibcon#*before return 0, iclass 15, count 0 2006.168.08:02:28.65#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:02:28.65#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:02:28.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.168.08:02:28.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.168.08:02:28.65$vc4f8/va=3,6 2006.168.08:02:28.65#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.168.08:02:28.65#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.168.08:02:28.65#ibcon#ireg 11 cls_cnt 2 2006.168.08:02:28.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.168.08:02:28.71#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.168.08:02:28.71#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.168.08:02:28.71#ibcon#enter wrdev, iclass 17, count 2 2006.168.08:02:28.71#ibcon#first serial, iclass 17, count 2 2006.168.08:02:28.71#ibcon#enter sib2, iclass 17, count 2 2006.168.08:02:28.71#ibcon#flushed, iclass 17, count 2 2006.168.08:02:28.71#ibcon#about to write, iclass 17, count 2 2006.168.08:02:28.71#ibcon#wrote, iclass 17, count 2 2006.168.08:02:28.71#ibcon#about to read 3, iclass 17, count 2 2006.168.08:02:28.74#ibcon#read 3, iclass 17, count 2 2006.168.08:02:28.74#ibcon#about to read 4, iclass 17, count 2 2006.168.08:02:28.74#ibcon#read 4, iclass 17, count 2 2006.168.08:02:28.74#ibcon#about to read 5, iclass 17, count 2 2006.168.08:02:28.74#ibcon#read 5, iclass 17, count 2 2006.168.08:02:28.74#ibcon#about to read 6, iclass 17, count 2 2006.168.08:02:28.74#ibcon#read 6, iclass 17, count 2 2006.168.08:02:28.74#ibcon#end of sib2, iclass 17, count 2 2006.168.08:02:28.74#ibcon#*mode == 0, iclass 17, count 2 2006.168.08:02:28.74#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.168.08:02:28.74#ibcon#[25=AT03-06\r\n] 2006.168.08:02:28.74#ibcon#*before write, iclass 17, count 2 2006.168.08:02:28.74#ibcon#enter sib2, iclass 17, count 2 2006.168.08:02:28.74#ibcon#flushed, iclass 17, count 2 2006.168.08:02:28.74#ibcon#about to write, iclass 17, count 2 2006.168.08:02:28.74#ibcon#wrote, iclass 17, count 2 2006.168.08:02:28.74#ibcon#about to read 3, iclass 17, count 2 2006.168.08:02:28.77#ibcon#read 3, iclass 17, count 2 2006.168.08:02:28.77#ibcon#about to read 4, iclass 17, count 2 2006.168.08:02:28.77#ibcon#read 4, iclass 17, count 2 2006.168.08:02:28.77#ibcon#about to read 5, iclass 17, count 2 2006.168.08:02:28.77#ibcon#read 5, iclass 17, count 2 2006.168.08:02:28.77#ibcon#about to read 6, iclass 17, count 2 2006.168.08:02:28.77#ibcon#read 6, iclass 17, count 2 2006.168.08:02:28.77#ibcon#end of sib2, iclass 17, count 2 2006.168.08:02:28.77#ibcon#*after write, iclass 17, count 2 2006.168.08:02:28.77#ibcon#*before return 0, iclass 17, count 2 2006.168.08:02:28.77#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.168.08:02:28.77#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.168.08:02:28.77#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.168.08:02:28.77#ibcon#ireg 7 cls_cnt 0 2006.168.08:02:28.77#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.168.08:02:28.89#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.168.08:02:28.89#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.168.08:02:28.89#ibcon#enter wrdev, iclass 17, count 0 2006.168.08:02:28.89#ibcon#first serial, iclass 17, count 0 2006.168.08:02:28.89#ibcon#enter sib2, iclass 17, count 0 2006.168.08:02:28.89#ibcon#flushed, iclass 17, count 0 2006.168.08:02:28.89#ibcon#about to write, iclass 17, count 0 2006.168.08:02:28.89#ibcon#wrote, iclass 17, count 0 2006.168.08:02:28.89#ibcon#about to read 3, iclass 17, count 0 2006.168.08:02:28.91#ibcon#read 3, iclass 17, count 0 2006.168.08:02:28.91#ibcon#about to read 4, iclass 17, count 0 2006.168.08:02:28.91#ibcon#read 4, iclass 17, count 0 2006.168.08:02:28.91#ibcon#about to read 5, iclass 17, count 0 2006.168.08:02:28.91#ibcon#read 5, iclass 17, count 0 2006.168.08:02:28.91#ibcon#about to read 6, iclass 17, count 0 2006.168.08:02:28.91#ibcon#read 6, iclass 17, count 0 2006.168.08:02:28.91#ibcon#end of sib2, iclass 17, count 0 2006.168.08:02:28.91#ibcon#*mode == 0, iclass 17, count 0 2006.168.08:02:28.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.168.08:02:28.91#ibcon#[25=USB\r\n] 2006.168.08:02:28.91#ibcon#*before write, iclass 17, count 0 2006.168.08:02:28.91#ibcon#enter sib2, iclass 17, count 0 2006.168.08:02:28.91#ibcon#flushed, iclass 17, count 0 2006.168.08:02:28.91#ibcon#about to write, iclass 17, count 0 2006.168.08:02:28.91#ibcon#wrote, iclass 17, count 0 2006.168.08:02:28.91#ibcon#about to read 3, iclass 17, count 0 2006.168.08:02:28.94#ibcon#read 3, iclass 17, count 0 2006.168.08:02:28.94#ibcon#about to read 4, iclass 17, count 0 2006.168.08:02:28.94#ibcon#read 4, iclass 17, count 0 2006.168.08:02:28.94#ibcon#about to read 5, iclass 17, count 0 2006.168.08:02:28.94#ibcon#read 5, iclass 17, count 0 2006.168.08:02:28.94#ibcon#about to read 6, iclass 17, count 0 2006.168.08:02:28.94#ibcon#read 6, iclass 17, count 0 2006.168.08:02:28.94#ibcon#end of sib2, iclass 17, count 0 2006.168.08:02:28.94#ibcon#*after write, iclass 17, count 0 2006.168.08:02:28.94#ibcon#*before return 0, iclass 17, count 0 2006.168.08:02:28.94#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.168.08:02:28.94#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.168.08:02:28.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.168.08:02:28.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.168.08:02:28.94$vc4f8/valo=4,832.99 2006.168.08:02:28.94#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.168.08:02:28.94#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.168.08:02:28.94#ibcon#ireg 17 cls_cnt 0 2006.168.08:02:28.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.168.08:02:28.94#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.168.08:02:28.94#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.168.08:02:28.94#ibcon#enter wrdev, iclass 19, count 0 2006.168.08:02:28.94#ibcon#first serial, iclass 19, count 0 2006.168.08:02:28.94#ibcon#enter sib2, iclass 19, count 0 2006.168.08:02:28.94#ibcon#flushed, iclass 19, count 0 2006.168.08:02:28.94#ibcon#about to write, iclass 19, count 0 2006.168.08:02:28.94#ibcon#wrote, iclass 19, count 0 2006.168.08:02:28.94#ibcon#about to read 3, iclass 19, count 0 2006.168.08:02:28.96#ibcon#read 3, iclass 19, count 0 2006.168.08:02:28.96#ibcon#about to read 4, iclass 19, count 0 2006.168.08:02:28.96#ibcon#read 4, iclass 19, count 0 2006.168.08:02:28.96#ibcon#about to read 5, iclass 19, count 0 2006.168.08:02:28.96#ibcon#read 5, iclass 19, count 0 2006.168.08:02:28.96#ibcon#about to read 6, iclass 19, count 0 2006.168.08:02:28.96#ibcon#read 6, iclass 19, count 0 2006.168.08:02:28.96#ibcon#end of sib2, iclass 19, count 0 2006.168.08:02:28.96#ibcon#*mode == 0, iclass 19, count 0 2006.168.08:02:28.96#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.168.08:02:28.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.08:02:28.96#ibcon#*before write, iclass 19, count 0 2006.168.08:02:28.96#ibcon#enter sib2, iclass 19, count 0 2006.168.08:02:28.96#ibcon#flushed, iclass 19, count 0 2006.168.08:02:28.96#ibcon#about to write, iclass 19, count 0 2006.168.08:02:28.96#ibcon#wrote, iclass 19, count 0 2006.168.08:02:28.96#ibcon#about to read 3, iclass 19, count 0 2006.168.08:02:29.00#ibcon#read 3, iclass 19, count 0 2006.168.08:02:29.00#ibcon#about to read 4, iclass 19, count 0 2006.168.08:02:29.00#ibcon#read 4, iclass 19, count 0 2006.168.08:02:29.00#ibcon#about to read 5, iclass 19, count 0 2006.168.08:02:29.00#ibcon#read 5, iclass 19, count 0 2006.168.08:02:29.00#ibcon#about to read 6, iclass 19, count 0 2006.168.08:02:29.00#ibcon#read 6, iclass 19, count 0 2006.168.08:02:29.00#ibcon#end of sib2, iclass 19, count 0 2006.168.08:02:29.00#ibcon#*after write, iclass 19, count 0 2006.168.08:02:29.00#ibcon#*before return 0, iclass 19, count 0 2006.168.08:02:29.00#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.168.08:02:29.00#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.168.08:02:29.00#ibcon#about to clear, iclass 19 cls_cnt 0 2006.168.08:02:29.00#ibcon#cleared, iclass 19 cls_cnt 0 2006.168.08:02:29.00$vc4f8/va=4,7 2006.168.08:02:29.00#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.168.08:02:29.00#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.168.08:02:29.00#ibcon#ireg 11 cls_cnt 2 2006.168.08:02:29.00#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.168.08:02:29.06#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.168.08:02:29.06#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.168.08:02:29.06#ibcon#enter wrdev, iclass 21, count 2 2006.168.08:02:29.06#ibcon#first serial, iclass 21, count 2 2006.168.08:02:29.06#ibcon#enter sib2, iclass 21, count 2 2006.168.08:02:29.06#ibcon#flushed, iclass 21, count 2 2006.168.08:02:29.06#ibcon#about to write, iclass 21, count 2 2006.168.08:02:29.06#ibcon#wrote, iclass 21, count 2 2006.168.08:02:29.06#ibcon#about to read 3, iclass 21, count 2 2006.168.08:02:29.08#ibcon#read 3, iclass 21, count 2 2006.168.08:02:29.08#ibcon#about to read 4, iclass 21, count 2 2006.168.08:02:29.08#ibcon#read 4, iclass 21, count 2 2006.168.08:02:29.08#ibcon#about to read 5, iclass 21, count 2 2006.168.08:02:29.08#ibcon#read 5, iclass 21, count 2 2006.168.08:02:29.08#ibcon#about to read 6, iclass 21, count 2 2006.168.08:02:29.08#ibcon#read 6, iclass 21, count 2 2006.168.08:02:29.08#ibcon#end of sib2, iclass 21, count 2 2006.168.08:02:29.08#ibcon#*mode == 0, iclass 21, count 2 2006.168.08:02:29.08#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.168.08:02:29.08#ibcon#[25=AT04-07\r\n] 2006.168.08:02:29.08#ibcon#*before write, iclass 21, count 2 2006.168.08:02:29.08#ibcon#enter sib2, iclass 21, count 2 2006.168.08:02:29.08#ibcon#flushed, iclass 21, count 2 2006.168.08:02:29.08#ibcon#about to write, iclass 21, count 2 2006.168.08:02:29.08#ibcon#wrote, iclass 21, count 2 2006.168.08:02:29.08#ibcon#about to read 3, iclass 21, count 2 2006.168.08:02:29.11#ibcon#read 3, iclass 21, count 2 2006.168.08:02:29.11#ibcon#about to read 4, iclass 21, count 2 2006.168.08:02:29.11#ibcon#read 4, iclass 21, count 2 2006.168.08:02:29.11#ibcon#about to read 5, iclass 21, count 2 2006.168.08:02:29.11#ibcon#read 5, iclass 21, count 2 2006.168.08:02:29.11#ibcon#about to read 6, iclass 21, count 2 2006.168.08:02:29.11#ibcon#read 6, iclass 21, count 2 2006.168.08:02:29.11#ibcon#end of sib2, iclass 21, count 2 2006.168.08:02:29.11#ibcon#*after write, iclass 21, count 2 2006.168.08:02:29.11#ibcon#*before return 0, iclass 21, count 2 2006.168.08:02:29.11#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.168.08:02:29.11#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.168.08:02:29.11#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.168.08:02:29.11#ibcon#ireg 7 cls_cnt 0 2006.168.08:02:29.11#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.168.08:02:29.23#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.168.08:02:29.23#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.168.08:02:29.23#ibcon#enter wrdev, iclass 21, count 0 2006.168.08:02:29.23#ibcon#first serial, iclass 21, count 0 2006.168.08:02:29.23#ibcon#enter sib2, iclass 21, count 0 2006.168.08:02:29.23#ibcon#flushed, iclass 21, count 0 2006.168.08:02:29.23#ibcon#about to write, iclass 21, count 0 2006.168.08:02:29.23#ibcon#wrote, iclass 21, count 0 2006.168.08:02:29.23#ibcon#about to read 3, iclass 21, count 0 2006.168.08:02:29.25#ibcon#read 3, iclass 21, count 0 2006.168.08:02:29.25#ibcon#about to read 4, iclass 21, count 0 2006.168.08:02:29.25#ibcon#read 4, iclass 21, count 0 2006.168.08:02:29.25#ibcon#about to read 5, iclass 21, count 0 2006.168.08:02:29.25#ibcon#read 5, iclass 21, count 0 2006.168.08:02:29.25#ibcon#about to read 6, iclass 21, count 0 2006.168.08:02:29.25#ibcon#read 6, iclass 21, count 0 2006.168.08:02:29.25#ibcon#end of sib2, iclass 21, count 0 2006.168.08:02:29.25#ibcon#*mode == 0, iclass 21, count 0 2006.168.08:02:29.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.168.08:02:29.25#ibcon#[25=USB\r\n] 2006.168.08:02:29.25#ibcon#*before write, iclass 21, count 0 2006.168.08:02:29.25#ibcon#enter sib2, iclass 21, count 0 2006.168.08:02:29.25#ibcon#flushed, iclass 21, count 0 2006.168.08:02:29.25#ibcon#about to write, iclass 21, count 0 2006.168.08:02:29.25#ibcon#wrote, iclass 21, count 0 2006.168.08:02:29.25#ibcon#about to read 3, iclass 21, count 0 2006.168.08:02:29.28#ibcon#read 3, iclass 21, count 0 2006.168.08:02:29.28#ibcon#about to read 4, iclass 21, count 0 2006.168.08:02:29.28#ibcon#read 4, iclass 21, count 0 2006.168.08:02:29.28#ibcon#about to read 5, iclass 21, count 0 2006.168.08:02:29.28#ibcon#read 5, iclass 21, count 0 2006.168.08:02:29.28#ibcon#about to read 6, iclass 21, count 0 2006.168.08:02:29.28#ibcon#read 6, iclass 21, count 0 2006.168.08:02:29.28#ibcon#end of sib2, iclass 21, count 0 2006.168.08:02:29.28#ibcon#*after write, iclass 21, count 0 2006.168.08:02:29.28#ibcon#*before return 0, iclass 21, count 0 2006.168.08:02:29.28#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.168.08:02:29.28#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.168.08:02:29.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.168.08:02:29.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.168.08:02:29.28$vc4f8/valo=5,652.99 2006.168.08:02:29.28#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.168.08:02:29.28#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.168.08:02:29.28#ibcon#ireg 17 cls_cnt 0 2006.168.08:02:29.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:02:29.28#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:02:29.28#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:02:29.28#ibcon#enter wrdev, iclass 23, count 0 2006.168.08:02:29.28#ibcon#first serial, iclass 23, count 0 2006.168.08:02:29.28#ibcon#enter sib2, iclass 23, count 0 2006.168.08:02:29.28#ibcon#flushed, iclass 23, count 0 2006.168.08:02:29.28#ibcon#about to write, iclass 23, count 0 2006.168.08:02:29.28#ibcon#wrote, iclass 23, count 0 2006.168.08:02:29.28#ibcon#about to read 3, iclass 23, count 0 2006.168.08:02:29.30#ibcon#read 3, iclass 23, count 0 2006.168.08:02:29.30#ibcon#about to read 4, iclass 23, count 0 2006.168.08:02:29.30#ibcon#read 4, iclass 23, count 0 2006.168.08:02:29.30#ibcon#about to read 5, iclass 23, count 0 2006.168.08:02:29.30#ibcon#read 5, iclass 23, count 0 2006.168.08:02:29.30#ibcon#about to read 6, iclass 23, count 0 2006.168.08:02:29.30#ibcon#read 6, iclass 23, count 0 2006.168.08:02:29.30#ibcon#end of sib2, iclass 23, count 0 2006.168.08:02:29.30#ibcon#*mode == 0, iclass 23, count 0 2006.168.08:02:29.30#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.168.08:02:29.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.08:02:29.30#ibcon#*before write, iclass 23, count 0 2006.168.08:02:29.30#ibcon#enter sib2, iclass 23, count 0 2006.168.08:02:29.30#ibcon#flushed, iclass 23, count 0 2006.168.08:02:29.30#ibcon#about to write, iclass 23, count 0 2006.168.08:02:29.30#ibcon#wrote, iclass 23, count 0 2006.168.08:02:29.30#ibcon#about to read 3, iclass 23, count 0 2006.168.08:02:29.34#ibcon#read 3, iclass 23, count 0 2006.168.08:02:29.34#ibcon#about to read 4, iclass 23, count 0 2006.168.08:02:29.34#ibcon#read 4, iclass 23, count 0 2006.168.08:02:29.34#ibcon#about to read 5, iclass 23, count 0 2006.168.08:02:29.34#ibcon#read 5, iclass 23, count 0 2006.168.08:02:29.34#ibcon#about to read 6, iclass 23, count 0 2006.168.08:02:29.34#ibcon#read 6, iclass 23, count 0 2006.168.08:02:29.34#ibcon#end of sib2, iclass 23, count 0 2006.168.08:02:29.34#ibcon#*after write, iclass 23, count 0 2006.168.08:02:29.34#ibcon#*before return 0, iclass 23, count 0 2006.168.08:02:29.34#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:02:29.34#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:02:29.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.168.08:02:29.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.168.08:02:29.34$vc4f8/va=5,7 2006.168.08:02:29.34#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.168.08:02:29.34#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.168.08:02:29.34#ibcon#ireg 11 cls_cnt 2 2006.168.08:02:29.34#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:02:29.40#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:02:29.40#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:02:29.40#ibcon#enter wrdev, iclass 25, count 2 2006.168.08:02:29.40#ibcon#first serial, iclass 25, count 2 2006.168.08:02:29.40#ibcon#enter sib2, iclass 25, count 2 2006.168.08:02:29.40#ibcon#flushed, iclass 25, count 2 2006.168.08:02:29.40#ibcon#about to write, iclass 25, count 2 2006.168.08:02:29.40#ibcon#wrote, iclass 25, count 2 2006.168.08:02:29.40#ibcon#about to read 3, iclass 25, count 2 2006.168.08:02:29.42#ibcon#read 3, iclass 25, count 2 2006.168.08:02:29.42#ibcon#about to read 4, iclass 25, count 2 2006.168.08:02:29.42#ibcon#read 4, iclass 25, count 2 2006.168.08:02:29.42#ibcon#about to read 5, iclass 25, count 2 2006.168.08:02:29.42#ibcon#read 5, iclass 25, count 2 2006.168.08:02:29.42#ibcon#about to read 6, iclass 25, count 2 2006.168.08:02:29.42#ibcon#read 6, iclass 25, count 2 2006.168.08:02:29.42#ibcon#end of sib2, iclass 25, count 2 2006.168.08:02:29.42#ibcon#*mode == 0, iclass 25, count 2 2006.168.08:02:29.42#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.168.08:02:29.42#ibcon#[25=AT05-07\r\n] 2006.168.08:02:29.42#ibcon#*before write, iclass 25, count 2 2006.168.08:02:29.42#ibcon#enter sib2, iclass 25, count 2 2006.168.08:02:29.42#ibcon#flushed, iclass 25, count 2 2006.168.08:02:29.42#ibcon#about to write, iclass 25, count 2 2006.168.08:02:29.42#ibcon#wrote, iclass 25, count 2 2006.168.08:02:29.42#ibcon#about to read 3, iclass 25, count 2 2006.168.08:02:29.45#ibcon#read 3, iclass 25, count 2 2006.168.08:02:29.45#ibcon#about to read 4, iclass 25, count 2 2006.168.08:02:29.45#ibcon#read 4, iclass 25, count 2 2006.168.08:02:29.45#ibcon#about to read 5, iclass 25, count 2 2006.168.08:02:29.45#ibcon#read 5, iclass 25, count 2 2006.168.08:02:29.45#ibcon#about to read 6, iclass 25, count 2 2006.168.08:02:29.45#ibcon#read 6, iclass 25, count 2 2006.168.08:02:29.45#ibcon#end of sib2, iclass 25, count 2 2006.168.08:02:29.45#ibcon#*after write, iclass 25, count 2 2006.168.08:02:29.45#ibcon#*before return 0, iclass 25, count 2 2006.168.08:02:29.45#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:02:29.45#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:02:29.45#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.168.08:02:29.45#ibcon#ireg 7 cls_cnt 0 2006.168.08:02:29.45#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:02:29.57#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:02:29.57#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:02:29.57#ibcon#enter wrdev, iclass 25, count 0 2006.168.08:02:29.57#ibcon#first serial, iclass 25, count 0 2006.168.08:02:29.57#ibcon#enter sib2, iclass 25, count 0 2006.168.08:02:29.57#ibcon#flushed, iclass 25, count 0 2006.168.08:02:29.57#ibcon#about to write, iclass 25, count 0 2006.168.08:02:29.57#ibcon#wrote, iclass 25, count 0 2006.168.08:02:29.57#ibcon#about to read 3, iclass 25, count 0 2006.168.08:02:29.59#ibcon#read 3, iclass 25, count 0 2006.168.08:02:29.59#ibcon#about to read 4, iclass 25, count 0 2006.168.08:02:29.59#ibcon#read 4, iclass 25, count 0 2006.168.08:02:29.59#ibcon#about to read 5, iclass 25, count 0 2006.168.08:02:29.59#ibcon#read 5, iclass 25, count 0 2006.168.08:02:29.59#ibcon#about to read 6, iclass 25, count 0 2006.168.08:02:29.59#ibcon#read 6, iclass 25, count 0 2006.168.08:02:29.59#ibcon#end of sib2, iclass 25, count 0 2006.168.08:02:29.59#ibcon#*mode == 0, iclass 25, count 0 2006.168.08:02:29.59#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.168.08:02:29.59#ibcon#[25=USB\r\n] 2006.168.08:02:29.59#ibcon#*before write, iclass 25, count 0 2006.168.08:02:29.59#ibcon#enter sib2, iclass 25, count 0 2006.168.08:02:29.59#ibcon#flushed, iclass 25, count 0 2006.168.08:02:29.59#ibcon#about to write, iclass 25, count 0 2006.168.08:02:29.59#ibcon#wrote, iclass 25, count 0 2006.168.08:02:29.59#ibcon#about to read 3, iclass 25, count 0 2006.168.08:02:29.62#ibcon#read 3, iclass 25, count 0 2006.168.08:02:29.62#ibcon#about to read 4, iclass 25, count 0 2006.168.08:02:29.62#ibcon#read 4, iclass 25, count 0 2006.168.08:02:29.62#ibcon#about to read 5, iclass 25, count 0 2006.168.08:02:29.62#ibcon#read 5, iclass 25, count 0 2006.168.08:02:29.62#ibcon#about to read 6, iclass 25, count 0 2006.168.08:02:29.62#ibcon#read 6, iclass 25, count 0 2006.168.08:02:29.62#ibcon#end of sib2, iclass 25, count 0 2006.168.08:02:29.62#ibcon#*after write, iclass 25, count 0 2006.168.08:02:29.62#ibcon#*before return 0, iclass 25, count 0 2006.168.08:02:29.62#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:02:29.62#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:02:29.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.168.08:02:29.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.168.08:02:29.62$vc4f8/valo=6,772.99 2006.168.08:02:29.62#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.168.08:02:29.62#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.168.08:02:29.62#ibcon#ireg 17 cls_cnt 0 2006.168.08:02:29.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:02:29.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:02:29.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:02:29.62#ibcon#enter wrdev, iclass 27, count 0 2006.168.08:02:29.62#ibcon#first serial, iclass 27, count 0 2006.168.08:02:29.62#ibcon#enter sib2, iclass 27, count 0 2006.168.08:02:29.62#ibcon#flushed, iclass 27, count 0 2006.168.08:02:29.62#ibcon#about to write, iclass 27, count 0 2006.168.08:02:29.62#ibcon#wrote, iclass 27, count 0 2006.168.08:02:29.62#ibcon#about to read 3, iclass 27, count 0 2006.168.08:02:29.64#ibcon#read 3, iclass 27, count 0 2006.168.08:02:29.64#ibcon#about to read 4, iclass 27, count 0 2006.168.08:02:29.64#ibcon#read 4, iclass 27, count 0 2006.168.08:02:29.64#ibcon#about to read 5, iclass 27, count 0 2006.168.08:02:29.64#ibcon#read 5, iclass 27, count 0 2006.168.08:02:29.64#ibcon#about to read 6, iclass 27, count 0 2006.168.08:02:29.64#ibcon#read 6, iclass 27, count 0 2006.168.08:02:29.64#ibcon#end of sib2, iclass 27, count 0 2006.168.08:02:29.64#ibcon#*mode == 0, iclass 27, count 0 2006.168.08:02:29.64#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.168.08:02:29.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.08:02:29.64#ibcon#*before write, iclass 27, count 0 2006.168.08:02:29.64#ibcon#enter sib2, iclass 27, count 0 2006.168.08:02:29.64#ibcon#flushed, iclass 27, count 0 2006.168.08:02:29.64#ibcon#about to write, iclass 27, count 0 2006.168.08:02:29.64#ibcon#wrote, iclass 27, count 0 2006.168.08:02:29.64#ibcon#about to read 3, iclass 27, count 0 2006.168.08:02:29.68#ibcon#read 3, iclass 27, count 0 2006.168.08:02:29.68#ibcon#about to read 4, iclass 27, count 0 2006.168.08:02:29.68#ibcon#read 4, iclass 27, count 0 2006.168.08:02:29.68#ibcon#about to read 5, iclass 27, count 0 2006.168.08:02:29.68#ibcon#read 5, iclass 27, count 0 2006.168.08:02:29.68#ibcon#about to read 6, iclass 27, count 0 2006.168.08:02:29.68#ibcon#read 6, iclass 27, count 0 2006.168.08:02:29.68#ibcon#end of sib2, iclass 27, count 0 2006.168.08:02:29.68#ibcon#*after write, iclass 27, count 0 2006.168.08:02:29.68#ibcon#*before return 0, iclass 27, count 0 2006.168.08:02:29.68#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:02:29.68#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:02:29.68#ibcon#about to clear, iclass 27 cls_cnt 0 2006.168.08:02:29.68#ibcon#cleared, iclass 27 cls_cnt 0 2006.168.08:02:29.68$vc4f8/va=6,6 2006.168.08:02:29.68#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.168.08:02:29.68#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.168.08:02:29.68#ibcon#ireg 11 cls_cnt 2 2006.168.08:02:29.68#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:02:29.74#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:02:29.74#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:02:29.74#ibcon#enter wrdev, iclass 29, count 2 2006.168.08:02:29.74#ibcon#first serial, iclass 29, count 2 2006.168.08:02:29.74#ibcon#enter sib2, iclass 29, count 2 2006.168.08:02:29.74#ibcon#flushed, iclass 29, count 2 2006.168.08:02:29.74#ibcon#about to write, iclass 29, count 2 2006.168.08:02:29.74#ibcon#wrote, iclass 29, count 2 2006.168.08:02:29.74#ibcon#about to read 3, iclass 29, count 2 2006.168.08:02:29.76#ibcon#read 3, iclass 29, count 2 2006.168.08:02:29.76#ibcon#about to read 4, iclass 29, count 2 2006.168.08:02:29.76#ibcon#read 4, iclass 29, count 2 2006.168.08:02:29.76#ibcon#about to read 5, iclass 29, count 2 2006.168.08:02:29.76#ibcon#read 5, iclass 29, count 2 2006.168.08:02:29.76#ibcon#about to read 6, iclass 29, count 2 2006.168.08:02:29.76#ibcon#read 6, iclass 29, count 2 2006.168.08:02:29.76#ibcon#end of sib2, iclass 29, count 2 2006.168.08:02:29.76#ibcon#*mode == 0, iclass 29, count 2 2006.168.08:02:29.76#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.168.08:02:29.76#ibcon#[25=AT06-06\r\n] 2006.168.08:02:29.76#ibcon#*before write, iclass 29, count 2 2006.168.08:02:29.76#ibcon#enter sib2, iclass 29, count 2 2006.168.08:02:29.76#ibcon#flushed, iclass 29, count 2 2006.168.08:02:29.76#ibcon#about to write, iclass 29, count 2 2006.168.08:02:29.76#ibcon#wrote, iclass 29, count 2 2006.168.08:02:29.76#ibcon#about to read 3, iclass 29, count 2 2006.168.08:02:29.79#ibcon#read 3, iclass 29, count 2 2006.168.08:02:29.79#ibcon#about to read 4, iclass 29, count 2 2006.168.08:02:29.79#ibcon#read 4, iclass 29, count 2 2006.168.08:02:29.79#ibcon#about to read 5, iclass 29, count 2 2006.168.08:02:29.79#ibcon#read 5, iclass 29, count 2 2006.168.08:02:29.79#ibcon#about to read 6, iclass 29, count 2 2006.168.08:02:29.79#ibcon#read 6, iclass 29, count 2 2006.168.08:02:29.79#ibcon#end of sib2, iclass 29, count 2 2006.168.08:02:29.79#ibcon#*after write, iclass 29, count 2 2006.168.08:02:29.79#ibcon#*before return 0, iclass 29, count 2 2006.168.08:02:29.79#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:02:29.79#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:02:29.79#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.168.08:02:29.79#ibcon#ireg 7 cls_cnt 0 2006.168.08:02:29.79#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:02:29.91#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:02:29.91#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:02:29.91#ibcon#enter wrdev, iclass 29, count 0 2006.168.08:02:29.91#ibcon#first serial, iclass 29, count 0 2006.168.08:02:29.91#ibcon#enter sib2, iclass 29, count 0 2006.168.08:02:29.91#ibcon#flushed, iclass 29, count 0 2006.168.08:02:29.91#ibcon#about to write, iclass 29, count 0 2006.168.08:02:29.91#ibcon#wrote, iclass 29, count 0 2006.168.08:02:29.91#ibcon#about to read 3, iclass 29, count 0 2006.168.08:02:29.93#ibcon#read 3, iclass 29, count 0 2006.168.08:02:29.93#ibcon#about to read 4, iclass 29, count 0 2006.168.08:02:29.93#ibcon#read 4, iclass 29, count 0 2006.168.08:02:29.93#ibcon#about to read 5, iclass 29, count 0 2006.168.08:02:29.93#ibcon#read 5, iclass 29, count 0 2006.168.08:02:29.93#ibcon#about to read 6, iclass 29, count 0 2006.168.08:02:29.93#ibcon#read 6, iclass 29, count 0 2006.168.08:02:29.93#ibcon#end of sib2, iclass 29, count 0 2006.168.08:02:29.93#ibcon#*mode == 0, iclass 29, count 0 2006.168.08:02:29.93#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.168.08:02:29.93#ibcon#[25=USB\r\n] 2006.168.08:02:29.93#ibcon#*before write, iclass 29, count 0 2006.168.08:02:29.93#ibcon#enter sib2, iclass 29, count 0 2006.168.08:02:29.93#ibcon#flushed, iclass 29, count 0 2006.168.08:02:29.93#ibcon#about to write, iclass 29, count 0 2006.168.08:02:29.93#ibcon#wrote, iclass 29, count 0 2006.168.08:02:29.93#ibcon#about to read 3, iclass 29, count 0 2006.168.08:02:29.96#ibcon#read 3, iclass 29, count 0 2006.168.08:02:29.96#ibcon#about to read 4, iclass 29, count 0 2006.168.08:02:29.96#ibcon#read 4, iclass 29, count 0 2006.168.08:02:29.96#ibcon#about to read 5, iclass 29, count 0 2006.168.08:02:29.96#ibcon#read 5, iclass 29, count 0 2006.168.08:02:29.96#ibcon#about to read 6, iclass 29, count 0 2006.168.08:02:29.96#ibcon#read 6, iclass 29, count 0 2006.168.08:02:29.96#ibcon#end of sib2, iclass 29, count 0 2006.168.08:02:29.96#ibcon#*after write, iclass 29, count 0 2006.168.08:02:29.96#ibcon#*before return 0, iclass 29, count 0 2006.168.08:02:29.96#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:02:29.96#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:02:29.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.168.08:02:29.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.168.08:02:29.96$vc4f8/valo=7,832.99 2006.168.08:02:29.96#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.168.08:02:29.96#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.168.08:02:29.96#ibcon#ireg 17 cls_cnt 0 2006.168.08:02:29.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:02:29.96#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:02:29.96#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:02:29.96#ibcon#enter wrdev, iclass 31, count 0 2006.168.08:02:29.96#ibcon#first serial, iclass 31, count 0 2006.168.08:02:29.96#ibcon#enter sib2, iclass 31, count 0 2006.168.08:02:29.96#ibcon#flushed, iclass 31, count 0 2006.168.08:02:29.96#ibcon#about to write, iclass 31, count 0 2006.168.08:02:29.96#ibcon#wrote, iclass 31, count 0 2006.168.08:02:29.96#ibcon#about to read 3, iclass 31, count 0 2006.168.08:02:29.98#ibcon#read 3, iclass 31, count 0 2006.168.08:02:29.98#ibcon#about to read 4, iclass 31, count 0 2006.168.08:02:29.98#ibcon#read 4, iclass 31, count 0 2006.168.08:02:29.98#ibcon#about to read 5, iclass 31, count 0 2006.168.08:02:29.98#ibcon#read 5, iclass 31, count 0 2006.168.08:02:29.98#ibcon#about to read 6, iclass 31, count 0 2006.168.08:02:29.98#ibcon#read 6, iclass 31, count 0 2006.168.08:02:29.98#ibcon#end of sib2, iclass 31, count 0 2006.168.08:02:29.98#ibcon#*mode == 0, iclass 31, count 0 2006.168.08:02:29.98#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.168.08:02:29.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.08:02:29.98#ibcon#*before write, iclass 31, count 0 2006.168.08:02:29.98#ibcon#enter sib2, iclass 31, count 0 2006.168.08:02:29.98#ibcon#flushed, iclass 31, count 0 2006.168.08:02:29.98#ibcon#about to write, iclass 31, count 0 2006.168.08:02:29.98#ibcon#wrote, iclass 31, count 0 2006.168.08:02:29.98#ibcon#about to read 3, iclass 31, count 0 2006.168.08:02:30.02#ibcon#read 3, iclass 31, count 0 2006.168.08:02:30.02#ibcon#about to read 4, iclass 31, count 0 2006.168.08:02:30.02#ibcon#read 4, iclass 31, count 0 2006.168.08:02:30.02#ibcon#about to read 5, iclass 31, count 0 2006.168.08:02:30.02#ibcon#read 5, iclass 31, count 0 2006.168.08:02:30.02#ibcon#about to read 6, iclass 31, count 0 2006.168.08:02:30.02#ibcon#read 6, iclass 31, count 0 2006.168.08:02:30.02#ibcon#end of sib2, iclass 31, count 0 2006.168.08:02:30.02#ibcon#*after write, iclass 31, count 0 2006.168.08:02:30.02#ibcon#*before return 0, iclass 31, count 0 2006.168.08:02:30.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:02:30.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:02:30.02#ibcon#about to clear, iclass 31 cls_cnt 0 2006.168.08:02:30.02#ibcon#cleared, iclass 31 cls_cnt 0 2006.168.08:02:30.02$vc4f8/va=7,6 2006.168.08:02:30.02#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.168.08:02:30.02#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.168.08:02:30.02#ibcon#ireg 11 cls_cnt 2 2006.168.08:02:30.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.168.08:02:30.08#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.168.08:02:30.08#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.168.08:02:30.08#ibcon#enter wrdev, iclass 33, count 2 2006.168.08:02:30.08#ibcon#first serial, iclass 33, count 2 2006.168.08:02:30.08#ibcon#enter sib2, iclass 33, count 2 2006.168.08:02:30.08#ibcon#flushed, iclass 33, count 2 2006.168.08:02:30.08#ibcon#about to write, iclass 33, count 2 2006.168.08:02:30.08#ibcon#wrote, iclass 33, count 2 2006.168.08:02:30.08#ibcon#about to read 3, iclass 33, count 2 2006.168.08:02:30.10#ibcon#read 3, iclass 33, count 2 2006.168.08:02:30.10#ibcon#about to read 4, iclass 33, count 2 2006.168.08:02:30.10#ibcon#read 4, iclass 33, count 2 2006.168.08:02:30.10#ibcon#about to read 5, iclass 33, count 2 2006.168.08:02:30.10#ibcon#read 5, iclass 33, count 2 2006.168.08:02:30.10#ibcon#about to read 6, iclass 33, count 2 2006.168.08:02:30.10#ibcon#read 6, iclass 33, count 2 2006.168.08:02:30.10#ibcon#end of sib2, iclass 33, count 2 2006.168.08:02:30.10#ibcon#*mode == 0, iclass 33, count 2 2006.168.08:02:30.10#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.168.08:02:30.10#ibcon#[25=AT07-06\r\n] 2006.168.08:02:30.10#ibcon#*before write, iclass 33, count 2 2006.168.08:02:30.10#ibcon#enter sib2, iclass 33, count 2 2006.168.08:02:30.10#ibcon#flushed, iclass 33, count 2 2006.168.08:02:30.10#ibcon#about to write, iclass 33, count 2 2006.168.08:02:30.10#ibcon#wrote, iclass 33, count 2 2006.168.08:02:30.10#ibcon#about to read 3, iclass 33, count 2 2006.168.08:02:30.13#ibcon#read 3, iclass 33, count 2 2006.168.08:02:30.13#ibcon#about to read 4, iclass 33, count 2 2006.168.08:02:30.13#ibcon#read 4, iclass 33, count 2 2006.168.08:02:30.13#ibcon#about to read 5, iclass 33, count 2 2006.168.08:02:30.13#ibcon#read 5, iclass 33, count 2 2006.168.08:02:30.13#ibcon#about to read 6, iclass 33, count 2 2006.168.08:02:30.13#ibcon#read 6, iclass 33, count 2 2006.168.08:02:30.13#ibcon#end of sib2, iclass 33, count 2 2006.168.08:02:30.13#ibcon#*after write, iclass 33, count 2 2006.168.08:02:30.13#ibcon#*before return 0, iclass 33, count 2 2006.168.08:02:30.13#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.168.08:02:30.13#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.168.08:02:30.13#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.168.08:02:30.13#ibcon#ireg 7 cls_cnt 0 2006.168.08:02:30.13#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.168.08:02:30.25#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.168.08:02:30.25#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.168.08:02:30.25#ibcon#enter wrdev, iclass 33, count 0 2006.168.08:02:30.25#ibcon#first serial, iclass 33, count 0 2006.168.08:02:30.25#ibcon#enter sib2, iclass 33, count 0 2006.168.08:02:30.25#ibcon#flushed, iclass 33, count 0 2006.168.08:02:30.25#ibcon#about to write, iclass 33, count 0 2006.168.08:02:30.25#ibcon#wrote, iclass 33, count 0 2006.168.08:02:30.25#ibcon#about to read 3, iclass 33, count 0 2006.168.08:02:30.27#ibcon#read 3, iclass 33, count 0 2006.168.08:02:30.27#ibcon#about to read 4, iclass 33, count 0 2006.168.08:02:30.27#ibcon#read 4, iclass 33, count 0 2006.168.08:02:30.27#ibcon#about to read 5, iclass 33, count 0 2006.168.08:02:30.27#ibcon#read 5, iclass 33, count 0 2006.168.08:02:30.27#ibcon#about to read 6, iclass 33, count 0 2006.168.08:02:30.27#ibcon#read 6, iclass 33, count 0 2006.168.08:02:30.27#ibcon#end of sib2, iclass 33, count 0 2006.168.08:02:30.27#ibcon#*mode == 0, iclass 33, count 0 2006.168.08:02:30.27#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.168.08:02:30.27#ibcon#[25=USB\r\n] 2006.168.08:02:30.27#ibcon#*before write, iclass 33, count 0 2006.168.08:02:30.27#ibcon#enter sib2, iclass 33, count 0 2006.168.08:02:30.27#ibcon#flushed, iclass 33, count 0 2006.168.08:02:30.27#ibcon#about to write, iclass 33, count 0 2006.168.08:02:30.27#ibcon#wrote, iclass 33, count 0 2006.168.08:02:30.27#ibcon#about to read 3, iclass 33, count 0 2006.168.08:02:30.30#ibcon#read 3, iclass 33, count 0 2006.168.08:02:30.30#ibcon#about to read 4, iclass 33, count 0 2006.168.08:02:30.30#ibcon#read 4, iclass 33, count 0 2006.168.08:02:30.30#ibcon#about to read 5, iclass 33, count 0 2006.168.08:02:30.30#ibcon#read 5, iclass 33, count 0 2006.168.08:02:30.30#ibcon#about to read 6, iclass 33, count 0 2006.168.08:02:30.30#ibcon#read 6, iclass 33, count 0 2006.168.08:02:30.30#ibcon#end of sib2, iclass 33, count 0 2006.168.08:02:30.30#ibcon#*after write, iclass 33, count 0 2006.168.08:02:30.30#ibcon#*before return 0, iclass 33, count 0 2006.168.08:02:30.30#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.168.08:02:30.30#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.168.08:02:30.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.168.08:02:30.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.168.08:02:30.30$vc4f8/valo=8,852.99 2006.168.08:02:30.30#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.168.08:02:30.30#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.168.08:02:30.30#ibcon#ireg 17 cls_cnt 0 2006.168.08:02:30.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.168.08:02:30.30#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.168.08:02:30.30#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.168.08:02:30.30#ibcon#enter wrdev, iclass 35, count 0 2006.168.08:02:30.30#ibcon#first serial, iclass 35, count 0 2006.168.08:02:30.30#ibcon#enter sib2, iclass 35, count 0 2006.168.08:02:30.30#ibcon#flushed, iclass 35, count 0 2006.168.08:02:30.30#ibcon#about to write, iclass 35, count 0 2006.168.08:02:30.30#ibcon#wrote, iclass 35, count 0 2006.168.08:02:30.30#ibcon#about to read 3, iclass 35, count 0 2006.168.08:02:30.32#ibcon#read 3, iclass 35, count 0 2006.168.08:02:30.32#ibcon#about to read 4, iclass 35, count 0 2006.168.08:02:30.32#ibcon#read 4, iclass 35, count 0 2006.168.08:02:30.32#ibcon#about to read 5, iclass 35, count 0 2006.168.08:02:30.32#ibcon#read 5, iclass 35, count 0 2006.168.08:02:30.32#ibcon#about to read 6, iclass 35, count 0 2006.168.08:02:30.32#ibcon#read 6, iclass 35, count 0 2006.168.08:02:30.32#ibcon#end of sib2, iclass 35, count 0 2006.168.08:02:30.32#ibcon#*mode == 0, iclass 35, count 0 2006.168.08:02:30.32#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.168.08:02:30.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.08:02:30.32#ibcon#*before write, iclass 35, count 0 2006.168.08:02:30.32#ibcon#enter sib2, iclass 35, count 0 2006.168.08:02:30.32#ibcon#flushed, iclass 35, count 0 2006.168.08:02:30.32#ibcon#about to write, iclass 35, count 0 2006.168.08:02:30.32#ibcon#wrote, iclass 35, count 0 2006.168.08:02:30.32#ibcon#about to read 3, iclass 35, count 0 2006.168.08:02:30.36#ibcon#read 3, iclass 35, count 0 2006.168.08:02:30.36#ibcon#about to read 4, iclass 35, count 0 2006.168.08:02:30.36#ibcon#read 4, iclass 35, count 0 2006.168.08:02:30.36#ibcon#about to read 5, iclass 35, count 0 2006.168.08:02:30.36#ibcon#read 5, iclass 35, count 0 2006.168.08:02:30.36#ibcon#about to read 6, iclass 35, count 0 2006.168.08:02:30.36#ibcon#read 6, iclass 35, count 0 2006.168.08:02:30.36#ibcon#end of sib2, iclass 35, count 0 2006.168.08:02:30.36#ibcon#*after write, iclass 35, count 0 2006.168.08:02:30.36#ibcon#*before return 0, iclass 35, count 0 2006.168.08:02:30.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.168.08:02:30.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.168.08:02:30.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.168.08:02:30.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.168.08:02:30.36$vc4f8/va=8,7 2006.168.08:02:30.36#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.168.08:02:30.36#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.168.08:02:30.36#ibcon#ireg 11 cls_cnt 2 2006.168.08:02:30.36#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.168.08:02:30.42#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.168.08:02:30.42#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.168.08:02:30.42#ibcon#enter wrdev, iclass 37, count 2 2006.168.08:02:30.42#ibcon#first serial, iclass 37, count 2 2006.168.08:02:30.42#ibcon#enter sib2, iclass 37, count 2 2006.168.08:02:30.42#ibcon#flushed, iclass 37, count 2 2006.168.08:02:30.42#ibcon#about to write, iclass 37, count 2 2006.168.08:02:30.42#ibcon#wrote, iclass 37, count 2 2006.168.08:02:30.42#ibcon#about to read 3, iclass 37, count 2 2006.168.08:02:30.44#ibcon#read 3, iclass 37, count 2 2006.168.08:02:30.44#ibcon#about to read 4, iclass 37, count 2 2006.168.08:02:30.44#ibcon#read 4, iclass 37, count 2 2006.168.08:02:30.44#ibcon#about to read 5, iclass 37, count 2 2006.168.08:02:30.44#ibcon#read 5, iclass 37, count 2 2006.168.08:02:30.44#ibcon#about to read 6, iclass 37, count 2 2006.168.08:02:30.44#ibcon#read 6, iclass 37, count 2 2006.168.08:02:30.44#ibcon#end of sib2, iclass 37, count 2 2006.168.08:02:30.44#ibcon#*mode == 0, iclass 37, count 2 2006.168.08:02:30.44#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.168.08:02:30.44#ibcon#[25=AT08-07\r\n] 2006.168.08:02:30.44#ibcon#*before write, iclass 37, count 2 2006.168.08:02:30.44#ibcon#enter sib2, iclass 37, count 2 2006.168.08:02:30.44#ibcon#flushed, iclass 37, count 2 2006.168.08:02:30.44#ibcon#about to write, iclass 37, count 2 2006.168.08:02:30.44#ibcon#wrote, iclass 37, count 2 2006.168.08:02:30.44#ibcon#about to read 3, iclass 37, count 2 2006.168.08:02:30.47#ibcon#read 3, iclass 37, count 2 2006.168.08:02:30.47#ibcon#about to read 4, iclass 37, count 2 2006.168.08:02:30.47#ibcon#read 4, iclass 37, count 2 2006.168.08:02:30.47#ibcon#about to read 5, iclass 37, count 2 2006.168.08:02:30.47#ibcon#read 5, iclass 37, count 2 2006.168.08:02:30.47#ibcon#about to read 6, iclass 37, count 2 2006.168.08:02:30.47#ibcon#read 6, iclass 37, count 2 2006.168.08:02:30.47#ibcon#end of sib2, iclass 37, count 2 2006.168.08:02:30.47#ibcon#*after write, iclass 37, count 2 2006.168.08:02:30.47#ibcon#*before return 0, iclass 37, count 2 2006.168.08:02:30.47#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.168.08:02:30.47#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.168.08:02:30.47#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.168.08:02:30.47#ibcon#ireg 7 cls_cnt 0 2006.168.08:02:30.47#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.168.08:02:30.59#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.168.08:02:30.59#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.168.08:02:30.59#ibcon#enter wrdev, iclass 37, count 0 2006.168.08:02:30.59#ibcon#first serial, iclass 37, count 0 2006.168.08:02:30.59#ibcon#enter sib2, iclass 37, count 0 2006.168.08:02:30.59#ibcon#flushed, iclass 37, count 0 2006.168.08:02:30.59#ibcon#about to write, iclass 37, count 0 2006.168.08:02:30.59#ibcon#wrote, iclass 37, count 0 2006.168.08:02:30.59#ibcon#about to read 3, iclass 37, count 0 2006.168.08:02:30.61#ibcon#read 3, iclass 37, count 0 2006.168.08:02:30.61#ibcon#about to read 4, iclass 37, count 0 2006.168.08:02:30.61#ibcon#read 4, iclass 37, count 0 2006.168.08:02:30.61#ibcon#about to read 5, iclass 37, count 0 2006.168.08:02:30.61#ibcon#read 5, iclass 37, count 0 2006.168.08:02:30.61#ibcon#about to read 6, iclass 37, count 0 2006.168.08:02:30.61#ibcon#read 6, iclass 37, count 0 2006.168.08:02:30.61#ibcon#end of sib2, iclass 37, count 0 2006.168.08:02:30.61#ibcon#*mode == 0, iclass 37, count 0 2006.168.08:02:30.61#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.168.08:02:30.61#ibcon#[25=USB\r\n] 2006.168.08:02:30.61#ibcon#*before write, iclass 37, count 0 2006.168.08:02:30.61#ibcon#enter sib2, iclass 37, count 0 2006.168.08:02:30.61#ibcon#flushed, iclass 37, count 0 2006.168.08:02:30.61#ibcon#about to write, iclass 37, count 0 2006.168.08:02:30.61#ibcon#wrote, iclass 37, count 0 2006.168.08:02:30.61#ibcon#about to read 3, iclass 37, count 0 2006.168.08:02:30.64#ibcon#read 3, iclass 37, count 0 2006.168.08:02:30.64#ibcon#about to read 4, iclass 37, count 0 2006.168.08:02:30.64#ibcon#read 4, iclass 37, count 0 2006.168.08:02:30.64#ibcon#about to read 5, iclass 37, count 0 2006.168.08:02:30.64#ibcon#read 5, iclass 37, count 0 2006.168.08:02:30.64#ibcon#about to read 6, iclass 37, count 0 2006.168.08:02:30.64#ibcon#read 6, iclass 37, count 0 2006.168.08:02:30.64#ibcon#end of sib2, iclass 37, count 0 2006.168.08:02:30.64#ibcon#*after write, iclass 37, count 0 2006.168.08:02:30.64#ibcon#*before return 0, iclass 37, count 0 2006.168.08:02:30.64#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.168.08:02:30.64#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.168.08:02:30.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.168.08:02:30.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.168.08:02:30.64$vc4f8/vblo=1,632.99 2006.168.08:02:30.64#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.168.08:02:30.64#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.168.08:02:30.64#ibcon#ireg 17 cls_cnt 0 2006.168.08:02:30.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.168.08:02:30.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.168.08:02:30.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.168.08:02:30.64#ibcon#enter wrdev, iclass 39, count 0 2006.168.08:02:30.64#ibcon#first serial, iclass 39, count 0 2006.168.08:02:30.64#ibcon#enter sib2, iclass 39, count 0 2006.168.08:02:30.64#ibcon#flushed, iclass 39, count 0 2006.168.08:02:30.64#ibcon#about to write, iclass 39, count 0 2006.168.08:02:30.64#ibcon#wrote, iclass 39, count 0 2006.168.08:02:30.64#ibcon#about to read 3, iclass 39, count 0 2006.168.08:02:30.66#ibcon#read 3, iclass 39, count 0 2006.168.08:02:30.66#ibcon#about to read 4, iclass 39, count 0 2006.168.08:02:30.66#ibcon#read 4, iclass 39, count 0 2006.168.08:02:30.66#ibcon#about to read 5, iclass 39, count 0 2006.168.08:02:30.66#ibcon#read 5, iclass 39, count 0 2006.168.08:02:30.66#ibcon#about to read 6, iclass 39, count 0 2006.168.08:02:30.66#ibcon#read 6, iclass 39, count 0 2006.168.08:02:30.66#ibcon#end of sib2, iclass 39, count 0 2006.168.08:02:30.66#ibcon#*mode == 0, iclass 39, count 0 2006.168.08:02:30.66#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.168.08:02:30.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.08:02:30.66#ibcon#*before write, iclass 39, count 0 2006.168.08:02:30.66#ibcon#enter sib2, iclass 39, count 0 2006.168.08:02:30.66#ibcon#flushed, iclass 39, count 0 2006.168.08:02:30.66#ibcon#about to write, iclass 39, count 0 2006.168.08:02:30.66#ibcon#wrote, iclass 39, count 0 2006.168.08:02:30.66#ibcon#about to read 3, iclass 39, count 0 2006.168.08:02:30.70#ibcon#read 3, iclass 39, count 0 2006.168.08:02:30.70#ibcon#about to read 4, iclass 39, count 0 2006.168.08:02:30.70#ibcon#read 4, iclass 39, count 0 2006.168.08:02:30.70#ibcon#about to read 5, iclass 39, count 0 2006.168.08:02:30.70#ibcon#read 5, iclass 39, count 0 2006.168.08:02:30.70#ibcon#about to read 6, iclass 39, count 0 2006.168.08:02:30.70#ibcon#read 6, iclass 39, count 0 2006.168.08:02:30.70#ibcon#end of sib2, iclass 39, count 0 2006.168.08:02:30.70#ibcon#*after write, iclass 39, count 0 2006.168.08:02:30.70#ibcon#*before return 0, iclass 39, count 0 2006.168.08:02:30.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.168.08:02:30.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.168.08:02:30.70#ibcon#about to clear, iclass 39 cls_cnt 0 2006.168.08:02:30.70#ibcon#cleared, iclass 39 cls_cnt 0 2006.168.08:02:30.70$vc4f8/vb=1,4 2006.168.08:02:30.70#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.168.08:02:30.70#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.168.08:02:30.70#ibcon#ireg 11 cls_cnt 2 2006.168.08:02:30.70#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.168.08:02:30.70#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.168.08:02:30.70#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.168.08:02:30.70#ibcon#enter wrdev, iclass 3, count 2 2006.168.08:02:30.70#ibcon#first serial, iclass 3, count 2 2006.168.08:02:30.70#ibcon#enter sib2, iclass 3, count 2 2006.168.08:02:30.70#ibcon#flushed, iclass 3, count 2 2006.168.08:02:30.70#ibcon#about to write, iclass 3, count 2 2006.168.08:02:30.70#ibcon#wrote, iclass 3, count 2 2006.168.08:02:30.70#ibcon#about to read 3, iclass 3, count 2 2006.168.08:02:30.72#ibcon#read 3, iclass 3, count 2 2006.168.08:02:30.72#ibcon#about to read 4, iclass 3, count 2 2006.168.08:02:30.72#ibcon#read 4, iclass 3, count 2 2006.168.08:02:30.72#ibcon#about to read 5, iclass 3, count 2 2006.168.08:02:30.72#ibcon#read 5, iclass 3, count 2 2006.168.08:02:30.72#ibcon#about to read 6, iclass 3, count 2 2006.168.08:02:30.72#ibcon#read 6, iclass 3, count 2 2006.168.08:02:30.72#ibcon#end of sib2, iclass 3, count 2 2006.168.08:02:30.72#ibcon#*mode == 0, iclass 3, count 2 2006.168.08:02:30.72#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.168.08:02:30.72#ibcon#[27=AT01-04\r\n] 2006.168.08:02:30.72#ibcon#*before write, iclass 3, count 2 2006.168.08:02:30.72#ibcon#enter sib2, iclass 3, count 2 2006.168.08:02:30.72#ibcon#flushed, iclass 3, count 2 2006.168.08:02:30.72#ibcon#about to write, iclass 3, count 2 2006.168.08:02:30.72#ibcon#wrote, iclass 3, count 2 2006.168.08:02:30.72#ibcon#about to read 3, iclass 3, count 2 2006.168.08:02:30.75#ibcon#read 3, iclass 3, count 2 2006.168.08:02:30.75#ibcon#about to read 4, iclass 3, count 2 2006.168.08:02:30.75#ibcon#read 4, iclass 3, count 2 2006.168.08:02:30.75#ibcon#about to read 5, iclass 3, count 2 2006.168.08:02:30.75#ibcon#read 5, iclass 3, count 2 2006.168.08:02:30.75#ibcon#about to read 6, iclass 3, count 2 2006.168.08:02:30.75#ibcon#read 6, iclass 3, count 2 2006.168.08:02:30.75#ibcon#end of sib2, iclass 3, count 2 2006.168.08:02:30.75#ibcon#*after write, iclass 3, count 2 2006.168.08:02:30.75#ibcon#*before return 0, iclass 3, count 2 2006.168.08:02:30.75#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.168.08:02:30.75#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.168.08:02:30.75#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.168.08:02:30.75#ibcon#ireg 7 cls_cnt 0 2006.168.08:02:30.75#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.168.08:02:30.87#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.168.08:02:30.87#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.168.08:02:30.87#ibcon#enter wrdev, iclass 3, count 0 2006.168.08:02:30.87#ibcon#first serial, iclass 3, count 0 2006.168.08:02:30.87#ibcon#enter sib2, iclass 3, count 0 2006.168.08:02:30.87#ibcon#flushed, iclass 3, count 0 2006.168.08:02:30.87#ibcon#about to write, iclass 3, count 0 2006.168.08:02:30.87#ibcon#wrote, iclass 3, count 0 2006.168.08:02:30.87#ibcon#about to read 3, iclass 3, count 0 2006.168.08:02:30.89#ibcon#read 3, iclass 3, count 0 2006.168.08:02:30.89#ibcon#about to read 4, iclass 3, count 0 2006.168.08:02:30.89#ibcon#read 4, iclass 3, count 0 2006.168.08:02:30.89#ibcon#about to read 5, iclass 3, count 0 2006.168.08:02:30.89#ibcon#read 5, iclass 3, count 0 2006.168.08:02:30.89#ibcon#about to read 6, iclass 3, count 0 2006.168.08:02:30.89#ibcon#read 6, iclass 3, count 0 2006.168.08:02:30.89#ibcon#end of sib2, iclass 3, count 0 2006.168.08:02:30.89#ibcon#*mode == 0, iclass 3, count 0 2006.168.08:02:30.89#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.168.08:02:30.89#ibcon#[27=USB\r\n] 2006.168.08:02:30.89#ibcon#*before write, iclass 3, count 0 2006.168.08:02:30.89#ibcon#enter sib2, iclass 3, count 0 2006.168.08:02:30.89#ibcon#flushed, iclass 3, count 0 2006.168.08:02:30.89#ibcon#about to write, iclass 3, count 0 2006.168.08:02:30.89#ibcon#wrote, iclass 3, count 0 2006.168.08:02:30.89#ibcon#about to read 3, iclass 3, count 0 2006.168.08:02:30.92#ibcon#read 3, iclass 3, count 0 2006.168.08:02:30.92#ibcon#about to read 4, iclass 3, count 0 2006.168.08:02:30.92#ibcon#read 4, iclass 3, count 0 2006.168.08:02:30.92#ibcon#about to read 5, iclass 3, count 0 2006.168.08:02:30.92#ibcon#read 5, iclass 3, count 0 2006.168.08:02:30.92#ibcon#about to read 6, iclass 3, count 0 2006.168.08:02:30.92#ibcon#read 6, iclass 3, count 0 2006.168.08:02:30.92#ibcon#end of sib2, iclass 3, count 0 2006.168.08:02:30.92#ibcon#*after write, iclass 3, count 0 2006.168.08:02:30.92#ibcon#*before return 0, iclass 3, count 0 2006.168.08:02:30.92#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.168.08:02:30.92#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.168.08:02:30.92#ibcon#about to clear, iclass 3 cls_cnt 0 2006.168.08:02:30.92#ibcon#cleared, iclass 3 cls_cnt 0 2006.168.08:02:30.92$vc4f8/vblo=2,640.99 2006.168.08:02:30.92#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.168.08:02:30.92#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.168.08:02:30.92#ibcon#ireg 17 cls_cnt 0 2006.168.08:02:30.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.168.08:02:30.92#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.168.08:02:30.92#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.168.08:02:30.92#ibcon#enter wrdev, iclass 5, count 0 2006.168.08:02:30.92#ibcon#first serial, iclass 5, count 0 2006.168.08:02:30.92#ibcon#enter sib2, iclass 5, count 0 2006.168.08:02:30.92#ibcon#flushed, iclass 5, count 0 2006.168.08:02:30.92#ibcon#about to write, iclass 5, count 0 2006.168.08:02:30.92#ibcon#wrote, iclass 5, count 0 2006.168.08:02:30.92#ibcon#about to read 3, iclass 5, count 0 2006.168.08:02:30.94#ibcon#read 3, iclass 5, count 0 2006.168.08:02:30.94#ibcon#about to read 4, iclass 5, count 0 2006.168.08:02:30.94#ibcon#read 4, iclass 5, count 0 2006.168.08:02:30.94#ibcon#about to read 5, iclass 5, count 0 2006.168.08:02:30.94#ibcon#read 5, iclass 5, count 0 2006.168.08:02:30.94#ibcon#about to read 6, iclass 5, count 0 2006.168.08:02:30.94#ibcon#read 6, iclass 5, count 0 2006.168.08:02:30.94#ibcon#end of sib2, iclass 5, count 0 2006.168.08:02:30.94#ibcon#*mode == 0, iclass 5, count 0 2006.168.08:02:30.94#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.168.08:02:30.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.08:02:30.94#ibcon#*before write, iclass 5, count 0 2006.168.08:02:30.94#ibcon#enter sib2, iclass 5, count 0 2006.168.08:02:30.94#ibcon#flushed, iclass 5, count 0 2006.168.08:02:30.94#ibcon#about to write, iclass 5, count 0 2006.168.08:02:30.94#ibcon#wrote, iclass 5, count 0 2006.168.08:02:30.94#ibcon#about to read 3, iclass 5, count 0 2006.168.08:02:30.98#ibcon#read 3, iclass 5, count 0 2006.168.08:02:30.98#ibcon#about to read 4, iclass 5, count 0 2006.168.08:02:30.98#ibcon#read 4, iclass 5, count 0 2006.168.08:02:30.98#ibcon#about to read 5, iclass 5, count 0 2006.168.08:02:30.98#ibcon#read 5, iclass 5, count 0 2006.168.08:02:30.98#ibcon#about to read 6, iclass 5, count 0 2006.168.08:02:30.98#ibcon#read 6, iclass 5, count 0 2006.168.08:02:30.98#ibcon#end of sib2, iclass 5, count 0 2006.168.08:02:30.98#ibcon#*after write, iclass 5, count 0 2006.168.08:02:30.98#ibcon#*before return 0, iclass 5, count 0 2006.168.08:02:30.98#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.168.08:02:30.98#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.168.08:02:30.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.168.08:02:30.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.168.08:02:30.98$vc4f8/vb=2,4 2006.168.08:02:30.98#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.168.08:02:30.98#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.168.08:02:30.98#ibcon#ireg 11 cls_cnt 2 2006.168.08:02:30.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.168.08:02:31.04#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.168.08:02:31.04#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.168.08:02:31.04#ibcon#enter wrdev, iclass 7, count 2 2006.168.08:02:31.04#ibcon#first serial, iclass 7, count 2 2006.168.08:02:31.04#ibcon#enter sib2, iclass 7, count 2 2006.168.08:02:31.04#ibcon#flushed, iclass 7, count 2 2006.168.08:02:31.04#ibcon#about to write, iclass 7, count 2 2006.168.08:02:31.04#ibcon#wrote, iclass 7, count 2 2006.168.08:02:31.04#ibcon#about to read 3, iclass 7, count 2 2006.168.08:02:31.06#ibcon#read 3, iclass 7, count 2 2006.168.08:02:31.06#ibcon#about to read 4, iclass 7, count 2 2006.168.08:02:31.06#ibcon#read 4, iclass 7, count 2 2006.168.08:02:31.06#ibcon#about to read 5, iclass 7, count 2 2006.168.08:02:31.06#ibcon#read 5, iclass 7, count 2 2006.168.08:02:31.06#ibcon#about to read 6, iclass 7, count 2 2006.168.08:02:31.06#ibcon#read 6, iclass 7, count 2 2006.168.08:02:31.06#ibcon#end of sib2, iclass 7, count 2 2006.168.08:02:31.06#ibcon#*mode == 0, iclass 7, count 2 2006.168.08:02:31.06#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.168.08:02:31.06#ibcon#[27=AT02-04\r\n] 2006.168.08:02:31.06#ibcon#*before write, iclass 7, count 2 2006.168.08:02:31.06#ibcon#enter sib2, iclass 7, count 2 2006.168.08:02:31.06#ibcon#flushed, iclass 7, count 2 2006.168.08:02:31.06#ibcon#about to write, iclass 7, count 2 2006.168.08:02:31.06#ibcon#wrote, iclass 7, count 2 2006.168.08:02:31.06#ibcon#about to read 3, iclass 7, count 2 2006.168.08:02:31.09#ibcon#read 3, iclass 7, count 2 2006.168.08:02:31.09#ibcon#about to read 4, iclass 7, count 2 2006.168.08:02:31.09#ibcon#read 4, iclass 7, count 2 2006.168.08:02:31.09#ibcon#about to read 5, iclass 7, count 2 2006.168.08:02:31.09#ibcon#read 5, iclass 7, count 2 2006.168.08:02:31.09#ibcon#about to read 6, iclass 7, count 2 2006.168.08:02:31.09#ibcon#read 6, iclass 7, count 2 2006.168.08:02:31.09#ibcon#end of sib2, iclass 7, count 2 2006.168.08:02:31.09#ibcon#*after write, iclass 7, count 2 2006.168.08:02:31.09#ibcon#*before return 0, iclass 7, count 2 2006.168.08:02:31.09#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.168.08:02:31.09#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.168.08:02:31.09#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.168.08:02:31.09#ibcon#ireg 7 cls_cnt 0 2006.168.08:02:31.09#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.168.08:02:31.11#abcon#<5=/08 1.5 4.3 27.01 731004.5\r\n> 2006.168.08:02:31.13#abcon#{5=INTERFACE CLEAR} 2006.168.08:02:31.19#abcon#[5=S1D000X0/0*\r\n] 2006.168.08:02:31.21#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.168.08:02:31.21#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.168.08:02:31.21#ibcon#enter wrdev, iclass 7, count 0 2006.168.08:02:31.21#ibcon#first serial, iclass 7, count 0 2006.168.08:02:31.21#ibcon#enter sib2, iclass 7, count 0 2006.168.08:02:31.21#ibcon#flushed, iclass 7, count 0 2006.168.08:02:31.21#ibcon#about to write, iclass 7, count 0 2006.168.08:02:31.21#ibcon#wrote, iclass 7, count 0 2006.168.08:02:31.21#ibcon#about to read 3, iclass 7, count 0 2006.168.08:02:31.23#ibcon#read 3, iclass 7, count 0 2006.168.08:02:31.23#ibcon#about to read 4, iclass 7, count 0 2006.168.08:02:31.23#ibcon#read 4, iclass 7, count 0 2006.168.08:02:31.23#ibcon#about to read 5, iclass 7, count 0 2006.168.08:02:31.23#ibcon#read 5, iclass 7, count 0 2006.168.08:02:31.23#ibcon#about to read 6, iclass 7, count 0 2006.168.08:02:31.23#ibcon#read 6, iclass 7, count 0 2006.168.08:02:31.23#ibcon#end of sib2, iclass 7, count 0 2006.168.08:02:31.23#ibcon#*mode == 0, iclass 7, count 0 2006.168.08:02:31.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.168.08:02:31.23#ibcon#[27=USB\r\n] 2006.168.08:02:31.23#ibcon#*before write, iclass 7, count 0 2006.168.08:02:31.23#ibcon#enter sib2, iclass 7, count 0 2006.168.08:02:31.23#ibcon#flushed, iclass 7, count 0 2006.168.08:02:31.23#ibcon#about to write, iclass 7, count 0 2006.168.08:02:31.23#ibcon#wrote, iclass 7, count 0 2006.168.08:02:31.23#ibcon#about to read 3, iclass 7, count 0 2006.168.08:02:31.26#ibcon#read 3, iclass 7, count 0 2006.168.08:02:31.26#ibcon#about to read 4, iclass 7, count 0 2006.168.08:02:31.26#ibcon#read 4, iclass 7, count 0 2006.168.08:02:31.26#ibcon#about to read 5, iclass 7, count 0 2006.168.08:02:31.26#ibcon#read 5, iclass 7, count 0 2006.168.08:02:31.26#ibcon#about to read 6, iclass 7, count 0 2006.168.08:02:31.26#ibcon#read 6, iclass 7, count 0 2006.168.08:02:31.26#ibcon#end of sib2, iclass 7, count 0 2006.168.08:02:31.26#ibcon#*after write, iclass 7, count 0 2006.168.08:02:31.26#ibcon#*before return 0, iclass 7, count 0 2006.168.08:02:31.26#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.168.08:02:31.26#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.168.08:02:31.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.168.08:02:31.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.168.08:02:31.26$vc4f8/vblo=3,656.99 2006.168.08:02:31.26#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.168.08:02:31.26#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.168.08:02:31.26#ibcon#ireg 17 cls_cnt 0 2006.168.08:02:31.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:02:31.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:02:31.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:02:31.26#ibcon#enter wrdev, iclass 15, count 0 2006.168.08:02:31.26#ibcon#first serial, iclass 15, count 0 2006.168.08:02:31.26#ibcon#enter sib2, iclass 15, count 0 2006.168.08:02:31.26#ibcon#flushed, iclass 15, count 0 2006.168.08:02:31.26#ibcon#about to write, iclass 15, count 0 2006.168.08:02:31.26#ibcon#wrote, iclass 15, count 0 2006.168.08:02:31.26#ibcon#about to read 3, iclass 15, count 0 2006.168.08:02:31.28#ibcon#read 3, iclass 15, count 0 2006.168.08:02:31.28#ibcon#about to read 4, iclass 15, count 0 2006.168.08:02:31.28#ibcon#read 4, iclass 15, count 0 2006.168.08:02:31.28#ibcon#about to read 5, iclass 15, count 0 2006.168.08:02:31.28#ibcon#read 5, iclass 15, count 0 2006.168.08:02:31.28#ibcon#about to read 6, iclass 15, count 0 2006.168.08:02:31.28#ibcon#read 6, iclass 15, count 0 2006.168.08:02:31.28#ibcon#end of sib2, iclass 15, count 0 2006.168.08:02:31.28#ibcon#*mode == 0, iclass 15, count 0 2006.168.08:02:31.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.168.08:02:31.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.08:02:31.28#ibcon#*before write, iclass 15, count 0 2006.168.08:02:31.28#ibcon#enter sib2, iclass 15, count 0 2006.168.08:02:31.28#ibcon#flushed, iclass 15, count 0 2006.168.08:02:31.28#ibcon#about to write, iclass 15, count 0 2006.168.08:02:31.28#ibcon#wrote, iclass 15, count 0 2006.168.08:02:31.28#ibcon#about to read 3, iclass 15, count 0 2006.168.08:02:31.32#ibcon#read 3, iclass 15, count 0 2006.168.08:02:31.32#ibcon#about to read 4, iclass 15, count 0 2006.168.08:02:31.32#ibcon#read 4, iclass 15, count 0 2006.168.08:02:31.32#ibcon#about to read 5, iclass 15, count 0 2006.168.08:02:31.32#ibcon#read 5, iclass 15, count 0 2006.168.08:02:31.32#ibcon#about to read 6, iclass 15, count 0 2006.168.08:02:31.32#ibcon#read 6, iclass 15, count 0 2006.168.08:02:31.32#ibcon#end of sib2, iclass 15, count 0 2006.168.08:02:31.32#ibcon#*after write, iclass 15, count 0 2006.168.08:02:31.32#ibcon#*before return 0, iclass 15, count 0 2006.168.08:02:31.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:02:31.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:02:31.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.168.08:02:31.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.168.08:02:31.32$vc4f8/vb=3,4 2006.168.08:02:31.32#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.168.08:02:31.32#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.168.08:02:31.32#ibcon#ireg 11 cls_cnt 2 2006.168.08:02:31.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.168.08:02:31.38#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.168.08:02:31.38#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.168.08:02:31.38#ibcon#enter wrdev, iclass 17, count 2 2006.168.08:02:31.38#ibcon#first serial, iclass 17, count 2 2006.168.08:02:31.38#ibcon#enter sib2, iclass 17, count 2 2006.168.08:02:31.38#ibcon#flushed, iclass 17, count 2 2006.168.08:02:31.38#ibcon#about to write, iclass 17, count 2 2006.168.08:02:31.38#ibcon#wrote, iclass 17, count 2 2006.168.08:02:31.38#ibcon#about to read 3, iclass 17, count 2 2006.168.08:02:31.40#ibcon#read 3, iclass 17, count 2 2006.168.08:02:31.40#ibcon#about to read 4, iclass 17, count 2 2006.168.08:02:31.40#ibcon#read 4, iclass 17, count 2 2006.168.08:02:31.40#ibcon#about to read 5, iclass 17, count 2 2006.168.08:02:31.40#ibcon#read 5, iclass 17, count 2 2006.168.08:02:31.40#ibcon#about to read 6, iclass 17, count 2 2006.168.08:02:31.40#ibcon#read 6, iclass 17, count 2 2006.168.08:02:31.40#ibcon#end of sib2, iclass 17, count 2 2006.168.08:02:31.40#ibcon#*mode == 0, iclass 17, count 2 2006.168.08:02:31.40#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.168.08:02:31.40#ibcon#[27=AT03-04\r\n] 2006.168.08:02:31.40#ibcon#*before write, iclass 17, count 2 2006.168.08:02:31.40#ibcon#enter sib2, iclass 17, count 2 2006.168.08:02:31.40#ibcon#flushed, iclass 17, count 2 2006.168.08:02:31.40#ibcon#about to write, iclass 17, count 2 2006.168.08:02:31.40#ibcon#wrote, iclass 17, count 2 2006.168.08:02:31.40#ibcon#about to read 3, iclass 17, count 2 2006.168.08:02:31.43#ibcon#read 3, iclass 17, count 2 2006.168.08:02:31.43#ibcon#about to read 4, iclass 17, count 2 2006.168.08:02:31.43#ibcon#read 4, iclass 17, count 2 2006.168.08:02:31.43#ibcon#about to read 5, iclass 17, count 2 2006.168.08:02:31.43#ibcon#read 5, iclass 17, count 2 2006.168.08:02:31.43#ibcon#about to read 6, iclass 17, count 2 2006.168.08:02:31.43#ibcon#read 6, iclass 17, count 2 2006.168.08:02:31.43#ibcon#end of sib2, iclass 17, count 2 2006.168.08:02:31.43#ibcon#*after write, iclass 17, count 2 2006.168.08:02:31.43#ibcon#*before return 0, iclass 17, count 2 2006.168.08:02:31.43#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.168.08:02:31.43#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.168.08:02:31.43#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.168.08:02:31.43#ibcon#ireg 7 cls_cnt 0 2006.168.08:02:31.43#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.168.08:02:31.55#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.168.08:02:31.55#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.168.08:02:31.55#ibcon#enter wrdev, iclass 17, count 0 2006.168.08:02:31.55#ibcon#first serial, iclass 17, count 0 2006.168.08:02:31.55#ibcon#enter sib2, iclass 17, count 0 2006.168.08:02:31.55#ibcon#flushed, iclass 17, count 0 2006.168.08:02:31.55#ibcon#about to write, iclass 17, count 0 2006.168.08:02:31.55#ibcon#wrote, iclass 17, count 0 2006.168.08:02:31.55#ibcon#about to read 3, iclass 17, count 0 2006.168.08:02:31.57#ibcon#read 3, iclass 17, count 0 2006.168.08:02:31.57#ibcon#about to read 4, iclass 17, count 0 2006.168.08:02:31.57#ibcon#read 4, iclass 17, count 0 2006.168.08:02:31.57#ibcon#about to read 5, iclass 17, count 0 2006.168.08:02:31.57#ibcon#read 5, iclass 17, count 0 2006.168.08:02:31.57#ibcon#about to read 6, iclass 17, count 0 2006.168.08:02:31.57#ibcon#read 6, iclass 17, count 0 2006.168.08:02:31.57#ibcon#end of sib2, iclass 17, count 0 2006.168.08:02:31.57#ibcon#*mode == 0, iclass 17, count 0 2006.168.08:02:31.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.168.08:02:31.57#ibcon#[27=USB\r\n] 2006.168.08:02:31.57#ibcon#*before write, iclass 17, count 0 2006.168.08:02:31.57#ibcon#enter sib2, iclass 17, count 0 2006.168.08:02:31.57#ibcon#flushed, iclass 17, count 0 2006.168.08:02:31.57#ibcon#about to write, iclass 17, count 0 2006.168.08:02:31.57#ibcon#wrote, iclass 17, count 0 2006.168.08:02:31.57#ibcon#about to read 3, iclass 17, count 0 2006.168.08:02:31.60#ibcon#read 3, iclass 17, count 0 2006.168.08:02:31.60#ibcon#about to read 4, iclass 17, count 0 2006.168.08:02:31.60#ibcon#read 4, iclass 17, count 0 2006.168.08:02:31.60#ibcon#about to read 5, iclass 17, count 0 2006.168.08:02:31.60#ibcon#read 5, iclass 17, count 0 2006.168.08:02:31.60#ibcon#about to read 6, iclass 17, count 0 2006.168.08:02:31.60#ibcon#read 6, iclass 17, count 0 2006.168.08:02:31.60#ibcon#end of sib2, iclass 17, count 0 2006.168.08:02:31.60#ibcon#*after write, iclass 17, count 0 2006.168.08:02:31.60#ibcon#*before return 0, iclass 17, count 0 2006.168.08:02:31.60#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.168.08:02:31.60#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.168.08:02:31.60#ibcon#about to clear, iclass 17 cls_cnt 0 2006.168.08:02:31.60#ibcon#cleared, iclass 17 cls_cnt 0 2006.168.08:02:31.60$vc4f8/vblo=4,712.99 2006.168.08:02:31.60#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.168.08:02:31.60#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.168.08:02:31.60#ibcon#ireg 17 cls_cnt 0 2006.168.08:02:31.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.168.08:02:31.60#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.168.08:02:31.60#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.168.08:02:31.60#ibcon#enter wrdev, iclass 19, count 0 2006.168.08:02:31.60#ibcon#first serial, iclass 19, count 0 2006.168.08:02:31.60#ibcon#enter sib2, iclass 19, count 0 2006.168.08:02:31.60#ibcon#flushed, iclass 19, count 0 2006.168.08:02:31.60#ibcon#about to write, iclass 19, count 0 2006.168.08:02:31.60#ibcon#wrote, iclass 19, count 0 2006.168.08:02:31.60#ibcon#about to read 3, iclass 19, count 0 2006.168.08:02:31.62#ibcon#read 3, iclass 19, count 0 2006.168.08:02:31.62#ibcon#about to read 4, iclass 19, count 0 2006.168.08:02:31.62#ibcon#read 4, iclass 19, count 0 2006.168.08:02:31.62#ibcon#about to read 5, iclass 19, count 0 2006.168.08:02:31.62#ibcon#read 5, iclass 19, count 0 2006.168.08:02:31.62#ibcon#about to read 6, iclass 19, count 0 2006.168.08:02:31.62#ibcon#read 6, iclass 19, count 0 2006.168.08:02:31.62#ibcon#end of sib2, iclass 19, count 0 2006.168.08:02:31.62#ibcon#*mode == 0, iclass 19, count 0 2006.168.08:02:31.62#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.168.08:02:31.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.08:02:31.62#ibcon#*before write, iclass 19, count 0 2006.168.08:02:31.62#ibcon#enter sib2, iclass 19, count 0 2006.168.08:02:31.62#ibcon#flushed, iclass 19, count 0 2006.168.08:02:31.62#ibcon#about to write, iclass 19, count 0 2006.168.08:02:31.62#ibcon#wrote, iclass 19, count 0 2006.168.08:02:31.62#ibcon#about to read 3, iclass 19, count 0 2006.168.08:02:31.66#ibcon#read 3, iclass 19, count 0 2006.168.08:02:31.66#ibcon#about to read 4, iclass 19, count 0 2006.168.08:02:31.66#ibcon#read 4, iclass 19, count 0 2006.168.08:02:31.66#ibcon#about to read 5, iclass 19, count 0 2006.168.08:02:31.66#ibcon#read 5, iclass 19, count 0 2006.168.08:02:31.66#ibcon#about to read 6, iclass 19, count 0 2006.168.08:02:31.66#ibcon#read 6, iclass 19, count 0 2006.168.08:02:31.66#ibcon#end of sib2, iclass 19, count 0 2006.168.08:02:31.66#ibcon#*after write, iclass 19, count 0 2006.168.08:02:31.66#ibcon#*before return 0, iclass 19, count 0 2006.168.08:02:31.66#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.168.08:02:31.66#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.168.08:02:31.66#ibcon#about to clear, iclass 19 cls_cnt 0 2006.168.08:02:31.66#ibcon#cleared, iclass 19 cls_cnt 0 2006.168.08:02:31.66$vc4f8/vb=4,4 2006.168.08:02:31.66#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.168.08:02:31.66#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.168.08:02:31.66#ibcon#ireg 11 cls_cnt 2 2006.168.08:02:31.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.168.08:02:31.72#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.168.08:02:31.72#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.168.08:02:31.72#ibcon#enter wrdev, iclass 21, count 2 2006.168.08:02:31.72#ibcon#first serial, iclass 21, count 2 2006.168.08:02:31.72#ibcon#enter sib2, iclass 21, count 2 2006.168.08:02:31.72#ibcon#flushed, iclass 21, count 2 2006.168.08:02:31.72#ibcon#about to write, iclass 21, count 2 2006.168.08:02:31.72#ibcon#wrote, iclass 21, count 2 2006.168.08:02:31.72#ibcon#about to read 3, iclass 21, count 2 2006.168.08:02:31.74#ibcon#read 3, iclass 21, count 2 2006.168.08:02:31.74#ibcon#about to read 4, iclass 21, count 2 2006.168.08:02:31.74#ibcon#read 4, iclass 21, count 2 2006.168.08:02:31.74#ibcon#about to read 5, iclass 21, count 2 2006.168.08:02:31.74#ibcon#read 5, iclass 21, count 2 2006.168.08:02:31.74#ibcon#about to read 6, iclass 21, count 2 2006.168.08:02:31.74#ibcon#read 6, iclass 21, count 2 2006.168.08:02:31.74#ibcon#end of sib2, iclass 21, count 2 2006.168.08:02:31.74#ibcon#*mode == 0, iclass 21, count 2 2006.168.08:02:31.74#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.168.08:02:31.74#ibcon#[27=AT04-04\r\n] 2006.168.08:02:31.74#ibcon#*before write, iclass 21, count 2 2006.168.08:02:31.74#ibcon#enter sib2, iclass 21, count 2 2006.168.08:02:31.74#ibcon#flushed, iclass 21, count 2 2006.168.08:02:31.74#ibcon#about to write, iclass 21, count 2 2006.168.08:02:31.74#ibcon#wrote, iclass 21, count 2 2006.168.08:02:31.74#ibcon#about to read 3, iclass 21, count 2 2006.168.08:02:31.77#ibcon#read 3, iclass 21, count 2 2006.168.08:02:31.77#ibcon#about to read 4, iclass 21, count 2 2006.168.08:02:31.77#ibcon#read 4, iclass 21, count 2 2006.168.08:02:31.77#ibcon#about to read 5, iclass 21, count 2 2006.168.08:02:31.77#ibcon#read 5, iclass 21, count 2 2006.168.08:02:31.77#ibcon#about to read 6, iclass 21, count 2 2006.168.08:02:31.77#ibcon#read 6, iclass 21, count 2 2006.168.08:02:31.77#ibcon#end of sib2, iclass 21, count 2 2006.168.08:02:31.77#ibcon#*after write, iclass 21, count 2 2006.168.08:02:31.77#ibcon#*before return 0, iclass 21, count 2 2006.168.08:02:31.77#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.168.08:02:31.77#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.168.08:02:31.77#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.168.08:02:31.77#ibcon#ireg 7 cls_cnt 0 2006.168.08:02:31.77#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.168.08:02:31.89#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.168.08:02:31.89#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.168.08:02:31.89#ibcon#enter wrdev, iclass 21, count 0 2006.168.08:02:31.89#ibcon#first serial, iclass 21, count 0 2006.168.08:02:31.89#ibcon#enter sib2, iclass 21, count 0 2006.168.08:02:31.89#ibcon#flushed, iclass 21, count 0 2006.168.08:02:31.89#ibcon#about to write, iclass 21, count 0 2006.168.08:02:31.89#ibcon#wrote, iclass 21, count 0 2006.168.08:02:31.89#ibcon#about to read 3, iclass 21, count 0 2006.168.08:02:31.91#ibcon#read 3, iclass 21, count 0 2006.168.08:02:31.91#ibcon#about to read 4, iclass 21, count 0 2006.168.08:02:31.91#ibcon#read 4, iclass 21, count 0 2006.168.08:02:31.91#ibcon#about to read 5, iclass 21, count 0 2006.168.08:02:31.91#ibcon#read 5, iclass 21, count 0 2006.168.08:02:31.91#ibcon#about to read 6, iclass 21, count 0 2006.168.08:02:31.91#ibcon#read 6, iclass 21, count 0 2006.168.08:02:31.91#ibcon#end of sib2, iclass 21, count 0 2006.168.08:02:31.91#ibcon#*mode == 0, iclass 21, count 0 2006.168.08:02:31.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.168.08:02:31.91#ibcon#[27=USB\r\n] 2006.168.08:02:31.91#ibcon#*before write, iclass 21, count 0 2006.168.08:02:31.91#ibcon#enter sib2, iclass 21, count 0 2006.168.08:02:31.91#ibcon#flushed, iclass 21, count 0 2006.168.08:02:31.91#ibcon#about to write, iclass 21, count 0 2006.168.08:02:31.91#ibcon#wrote, iclass 21, count 0 2006.168.08:02:31.91#ibcon#about to read 3, iclass 21, count 0 2006.168.08:02:31.94#ibcon#read 3, iclass 21, count 0 2006.168.08:02:31.94#ibcon#about to read 4, iclass 21, count 0 2006.168.08:02:31.94#ibcon#read 4, iclass 21, count 0 2006.168.08:02:31.94#ibcon#about to read 5, iclass 21, count 0 2006.168.08:02:31.94#ibcon#read 5, iclass 21, count 0 2006.168.08:02:31.94#ibcon#about to read 6, iclass 21, count 0 2006.168.08:02:31.94#ibcon#read 6, iclass 21, count 0 2006.168.08:02:31.94#ibcon#end of sib2, iclass 21, count 0 2006.168.08:02:31.94#ibcon#*after write, iclass 21, count 0 2006.168.08:02:31.94#ibcon#*before return 0, iclass 21, count 0 2006.168.08:02:31.94#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.168.08:02:31.94#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.168.08:02:31.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.168.08:02:31.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.168.08:02:31.94$vc4f8/vblo=5,744.99 2006.168.08:02:31.94#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.168.08:02:31.94#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.168.08:02:31.94#ibcon#ireg 17 cls_cnt 0 2006.168.08:02:31.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:02:31.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:02:31.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:02:31.94#ibcon#enter wrdev, iclass 23, count 0 2006.168.08:02:31.94#ibcon#first serial, iclass 23, count 0 2006.168.08:02:31.94#ibcon#enter sib2, iclass 23, count 0 2006.168.08:02:31.94#ibcon#flushed, iclass 23, count 0 2006.168.08:02:31.94#ibcon#about to write, iclass 23, count 0 2006.168.08:02:31.94#ibcon#wrote, iclass 23, count 0 2006.168.08:02:31.94#ibcon#about to read 3, iclass 23, count 0 2006.168.08:02:31.96#ibcon#read 3, iclass 23, count 0 2006.168.08:02:31.96#ibcon#about to read 4, iclass 23, count 0 2006.168.08:02:31.96#ibcon#read 4, iclass 23, count 0 2006.168.08:02:31.96#ibcon#about to read 5, iclass 23, count 0 2006.168.08:02:31.96#ibcon#read 5, iclass 23, count 0 2006.168.08:02:31.96#ibcon#about to read 6, iclass 23, count 0 2006.168.08:02:31.96#ibcon#read 6, iclass 23, count 0 2006.168.08:02:31.96#ibcon#end of sib2, iclass 23, count 0 2006.168.08:02:31.96#ibcon#*mode == 0, iclass 23, count 0 2006.168.08:02:31.96#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.168.08:02:31.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.08:02:31.96#ibcon#*before write, iclass 23, count 0 2006.168.08:02:31.96#ibcon#enter sib2, iclass 23, count 0 2006.168.08:02:31.96#ibcon#flushed, iclass 23, count 0 2006.168.08:02:31.96#ibcon#about to write, iclass 23, count 0 2006.168.08:02:31.96#ibcon#wrote, iclass 23, count 0 2006.168.08:02:31.96#ibcon#about to read 3, iclass 23, count 0 2006.168.08:02:32.00#ibcon#read 3, iclass 23, count 0 2006.168.08:02:32.00#ibcon#about to read 4, iclass 23, count 0 2006.168.08:02:32.00#ibcon#read 4, iclass 23, count 0 2006.168.08:02:32.00#ibcon#about to read 5, iclass 23, count 0 2006.168.08:02:32.00#ibcon#read 5, iclass 23, count 0 2006.168.08:02:32.00#ibcon#about to read 6, iclass 23, count 0 2006.168.08:02:32.00#ibcon#read 6, iclass 23, count 0 2006.168.08:02:32.00#ibcon#end of sib2, iclass 23, count 0 2006.168.08:02:32.00#ibcon#*after write, iclass 23, count 0 2006.168.08:02:32.00#ibcon#*before return 0, iclass 23, count 0 2006.168.08:02:32.00#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:02:32.00#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:02:32.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.168.08:02:32.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.168.08:02:32.00$vc4f8/vb=5,4 2006.168.08:02:32.00#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.168.08:02:32.00#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.168.08:02:32.00#ibcon#ireg 11 cls_cnt 2 2006.168.08:02:32.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:02:32.06#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:02:32.06#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:02:32.06#ibcon#enter wrdev, iclass 25, count 2 2006.168.08:02:32.06#ibcon#first serial, iclass 25, count 2 2006.168.08:02:32.06#ibcon#enter sib2, iclass 25, count 2 2006.168.08:02:32.06#ibcon#flushed, iclass 25, count 2 2006.168.08:02:32.06#ibcon#about to write, iclass 25, count 2 2006.168.08:02:32.06#ibcon#wrote, iclass 25, count 2 2006.168.08:02:32.06#ibcon#about to read 3, iclass 25, count 2 2006.168.08:02:32.08#ibcon#read 3, iclass 25, count 2 2006.168.08:02:32.08#ibcon#about to read 4, iclass 25, count 2 2006.168.08:02:32.08#ibcon#read 4, iclass 25, count 2 2006.168.08:02:32.08#ibcon#about to read 5, iclass 25, count 2 2006.168.08:02:32.08#ibcon#read 5, iclass 25, count 2 2006.168.08:02:32.08#ibcon#about to read 6, iclass 25, count 2 2006.168.08:02:32.08#ibcon#read 6, iclass 25, count 2 2006.168.08:02:32.08#ibcon#end of sib2, iclass 25, count 2 2006.168.08:02:32.08#ibcon#*mode == 0, iclass 25, count 2 2006.168.08:02:32.08#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.168.08:02:32.08#ibcon#[27=AT05-04\r\n] 2006.168.08:02:32.08#ibcon#*before write, iclass 25, count 2 2006.168.08:02:32.08#ibcon#enter sib2, iclass 25, count 2 2006.168.08:02:32.08#ibcon#flushed, iclass 25, count 2 2006.168.08:02:32.08#ibcon#about to write, iclass 25, count 2 2006.168.08:02:32.08#ibcon#wrote, iclass 25, count 2 2006.168.08:02:32.08#ibcon#about to read 3, iclass 25, count 2 2006.168.08:02:32.11#ibcon#read 3, iclass 25, count 2 2006.168.08:02:32.11#ibcon#about to read 4, iclass 25, count 2 2006.168.08:02:32.11#ibcon#read 4, iclass 25, count 2 2006.168.08:02:32.11#ibcon#about to read 5, iclass 25, count 2 2006.168.08:02:32.11#ibcon#read 5, iclass 25, count 2 2006.168.08:02:32.11#ibcon#about to read 6, iclass 25, count 2 2006.168.08:02:32.11#ibcon#read 6, iclass 25, count 2 2006.168.08:02:32.11#ibcon#end of sib2, iclass 25, count 2 2006.168.08:02:32.11#ibcon#*after write, iclass 25, count 2 2006.168.08:02:32.11#ibcon#*before return 0, iclass 25, count 2 2006.168.08:02:32.11#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:02:32.11#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:02:32.11#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.168.08:02:32.11#ibcon#ireg 7 cls_cnt 0 2006.168.08:02:32.11#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:02:32.23#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:02:32.23#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:02:32.23#ibcon#enter wrdev, iclass 25, count 0 2006.168.08:02:32.23#ibcon#first serial, iclass 25, count 0 2006.168.08:02:32.23#ibcon#enter sib2, iclass 25, count 0 2006.168.08:02:32.23#ibcon#flushed, iclass 25, count 0 2006.168.08:02:32.23#ibcon#about to write, iclass 25, count 0 2006.168.08:02:32.23#ibcon#wrote, iclass 25, count 0 2006.168.08:02:32.23#ibcon#about to read 3, iclass 25, count 0 2006.168.08:02:32.25#ibcon#read 3, iclass 25, count 0 2006.168.08:02:32.25#ibcon#about to read 4, iclass 25, count 0 2006.168.08:02:32.25#ibcon#read 4, iclass 25, count 0 2006.168.08:02:32.25#ibcon#about to read 5, iclass 25, count 0 2006.168.08:02:32.25#ibcon#read 5, iclass 25, count 0 2006.168.08:02:32.25#ibcon#about to read 6, iclass 25, count 0 2006.168.08:02:32.25#ibcon#read 6, iclass 25, count 0 2006.168.08:02:32.25#ibcon#end of sib2, iclass 25, count 0 2006.168.08:02:32.25#ibcon#*mode == 0, iclass 25, count 0 2006.168.08:02:32.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.168.08:02:32.25#ibcon#[27=USB\r\n] 2006.168.08:02:32.25#ibcon#*before write, iclass 25, count 0 2006.168.08:02:32.25#ibcon#enter sib2, iclass 25, count 0 2006.168.08:02:32.25#ibcon#flushed, iclass 25, count 0 2006.168.08:02:32.25#ibcon#about to write, iclass 25, count 0 2006.168.08:02:32.25#ibcon#wrote, iclass 25, count 0 2006.168.08:02:32.25#ibcon#about to read 3, iclass 25, count 0 2006.168.08:02:32.28#ibcon#read 3, iclass 25, count 0 2006.168.08:02:32.28#ibcon#about to read 4, iclass 25, count 0 2006.168.08:02:32.28#ibcon#read 4, iclass 25, count 0 2006.168.08:02:32.28#ibcon#about to read 5, iclass 25, count 0 2006.168.08:02:32.28#ibcon#read 5, iclass 25, count 0 2006.168.08:02:32.28#ibcon#about to read 6, iclass 25, count 0 2006.168.08:02:32.28#ibcon#read 6, iclass 25, count 0 2006.168.08:02:32.28#ibcon#end of sib2, iclass 25, count 0 2006.168.08:02:32.28#ibcon#*after write, iclass 25, count 0 2006.168.08:02:32.28#ibcon#*before return 0, iclass 25, count 0 2006.168.08:02:32.28#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:02:32.28#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:02:32.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.168.08:02:32.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.168.08:02:32.28$vc4f8/vblo=6,752.99 2006.168.08:02:32.28#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.168.08:02:32.28#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.168.08:02:32.28#ibcon#ireg 17 cls_cnt 0 2006.168.08:02:32.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:02:32.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:02:32.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:02:32.28#ibcon#enter wrdev, iclass 27, count 0 2006.168.08:02:32.28#ibcon#first serial, iclass 27, count 0 2006.168.08:02:32.28#ibcon#enter sib2, iclass 27, count 0 2006.168.08:02:32.28#ibcon#flushed, iclass 27, count 0 2006.168.08:02:32.28#ibcon#about to write, iclass 27, count 0 2006.168.08:02:32.28#ibcon#wrote, iclass 27, count 0 2006.168.08:02:32.28#ibcon#about to read 3, iclass 27, count 0 2006.168.08:02:32.30#ibcon#read 3, iclass 27, count 0 2006.168.08:02:32.30#ibcon#about to read 4, iclass 27, count 0 2006.168.08:02:32.30#ibcon#read 4, iclass 27, count 0 2006.168.08:02:32.30#ibcon#about to read 5, iclass 27, count 0 2006.168.08:02:32.30#ibcon#read 5, iclass 27, count 0 2006.168.08:02:32.30#ibcon#about to read 6, iclass 27, count 0 2006.168.08:02:32.30#ibcon#read 6, iclass 27, count 0 2006.168.08:02:32.30#ibcon#end of sib2, iclass 27, count 0 2006.168.08:02:32.30#ibcon#*mode == 0, iclass 27, count 0 2006.168.08:02:32.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.168.08:02:32.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.08:02:32.30#ibcon#*before write, iclass 27, count 0 2006.168.08:02:32.30#ibcon#enter sib2, iclass 27, count 0 2006.168.08:02:32.30#ibcon#flushed, iclass 27, count 0 2006.168.08:02:32.30#ibcon#about to write, iclass 27, count 0 2006.168.08:02:32.30#ibcon#wrote, iclass 27, count 0 2006.168.08:02:32.30#ibcon#about to read 3, iclass 27, count 0 2006.168.08:02:32.34#ibcon#read 3, iclass 27, count 0 2006.168.08:02:32.34#ibcon#about to read 4, iclass 27, count 0 2006.168.08:02:32.34#ibcon#read 4, iclass 27, count 0 2006.168.08:02:32.34#ibcon#about to read 5, iclass 27, count 0 2006.168.08:02:32.34#ibcon#read 5, iclass 27, count 0 2006.168.08:02:32.34#ibcon#about to read 6, iclass 27, count 0 2006.168.08:02:32.34#ibcon#read 6, iclass 27, count 0 2006.168.08:02:32.34#ibcon#end of sib2, iclass 27, count 0 2006.168.08:02:32.34#ibcon#*after write, iclass 27, count 0 2006.168.08:02:32.34#ibcon#*before return 0, iclass 27, count 0 2006.168.08:02:32.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:02:32.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:02:32.34#ibcon#about to clear, iclass 27 cls_cnt 0 2006.168.08:02:32.34#ibcon#cleared, iclass 27 cls_cnt 0 2006.168.08:02:32.34$vc4f8/vb=6,4 2006.168.08:02:32.34#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.168.08:02:32.34#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.168.08:02:32.34#ibcon#ireg 11 cls_cnt 2 2006.168.08:02:32.34#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:02:32.40#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:02:32.40#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:02:32.40#ibcon#enter wrdev, iclass 29, count 2 2006.168.08:02:32.40#ibcon#first serial, iclass 29, count 2 2006.168.08:02:32.40#ibcon#enter sib2, iclass 29, count 2 2006.168.08:02:32.40#ibcon#flushed, iclass 29, count 2 2006.168.08:02:32.40#ibcon#about to write, iclass 29, count 2 2006.168.08:02:32.40#ibcon#wrote, iclass 29, count 2 2006.168.08:02:32.40#ibcon#about to read 3, iclass 29, count 2 2006.168.08:02:32.42#ibcon#read 3, iclass 29, count 2 2006.168.08:02:32.42#ibcon#about to read 4, iclass 29, count 2 2006.168.08:02:32.42#ibcon#read 4, iclass 29, count 2 2006.168.08:02:32.42#ibcon#about to read 5, iclass 29, count 2 2006.168.08:02:32.42#ibcon#read 5, iclass 29, count 2 2006.168.08:02:32.42#ibcon#about to read 6, iclass 29, count 2 2006.168.08:02:32.42#ibcon#read 6, iclass 29, count 2 2006.168.08:02:32.42#ibcon#end of sib2, iclass 29, count 2 2006.168.08:02:32.42#ibcon#*mode == 0, iclass 29, count 2 2006.168.08:02:32.42#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.168.08:02:32.42#ibcon#[27=AT06-04\r\n] 2006.168.08:02:32.42#ibcon#*before write, iclass 29, count 2 2006.168.08:02:32.42#ibcon#enter sib2, iclass 29, count 2 2006.168.08:02:32.42#ibcon#flushed, iclass 29, count 2 2006.168.08:02:32.42#ibcon#about to write, iclass 29, count 2 2006.168.08:02:32.42#ibcon#wrote, iclass 29, count 2 2006.168.08:02:32.42#ibcon#about to read 3, iclass 29, count 2 2006.168.08:02:32.45#ibcon#read 3, iclass 29, count 2 2006.168.08:02:32.45#ibcon#about to read 4, iclass 29, count 2 2006.168.08:02:32.45#ibcon#read 4, iclass 29, count 2 2006.168.08:02:32.45#ibcon#about to read 5, iclass 29, count 2 2006.168.08:02:32.45#ibcon#read 5, iclass 29, count 2 2006.168.08:02:32.45#ibcon#about to read 6, iclass 29, count 2 2006.168.08:02:32.45#ibcon#read 6, iclass 29, count 2 2006.168.08:02:32.45#ibcon#end of sib2, iclass 29, count 2 2006.168.08:02:32.45#ibcon#*after write, iclass 29, count 2 2006.168.08:02:32.45#ibcon#*before return 0, iclass 29, count 2 2006.168.08:02:32.45#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:02:32.45#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:02:32.45#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.168.08:02:32.45#ibcon#ireg 7 cls_cnt 0 2006.168.08:02:32.45#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:02:32.57#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:02:32.57#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:02:32.57#ibcon#enter wrdev, iclass 29, count 0 2006.168.08:02:32.57#ibcon#first serial, iclass 29, count 0 2006.168.08:02:32.57#ibcon#enter sib2, iclass 29, count 0 2006.168.08:02:32.57#ibcon#flushed, iclass 29, count 0 2006.168.08:02:32.57#ibcon#about to write, iclass 29, count 0 2006.168.08:02:32.57#ibcon#wrote, iclass 29, count 0 2006.168.08:02:32.57#ibcon#about to read 3, iclass 29, count 0 2006.168.08:02:32.59#ibcon#read 3, iclass 29, count 0 2006.168.08:02:32.59#ibcon#about to read 4, iclass 29, count 0 2006.168.08:02:32.59#ibcon#read 4, iclass 29, count 0 2006.168.08:02:32.59#ibcon#about to read 5, iclass 29, count 0 2006.168.08:02:32.59#ibcon#read 5, iclass 29, count 0 2006.168.08:02:32.59#ibcon#about to read 6, iclass 29, count 0 2006.168.08:02:32.59#ibcon#read 6, iclass 29, count 0 2006.168.08:02:32.59#ibcon#end of sib2, iclass 29, count 0 2006.168.08:02:32.59#ibcon#*mode == 0, iclass 29, count 0 2006.168.08:02:32.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.168.08:02:32.59#ibcon#[27=USB\r\n] 2006.168.08:02:32.59#ibcon#*before write, iclass 29, count 0 2006.168.08:02:32.59#ibcon#enter sib2, iclass 29, count 0 2006.168.08:02:32.59#ibcon#flushed, iclass 29, count 0 2006.168.08:02:32.59#ibcon#about to write, iclass 29, count 0 2006.168.08:02:32.59#ibcon#wrote, iclass 29, count 0 2006.168.08:02:32.59#ibcon#about to read 3, iclass 29, count 0 2006.168.08:02:32.62#ibcon#read 3, iclass 29, count 0 2006.168.08:02:32.62#ibcon#about to read 4, iclass 29, count 0 2006.168.08:02:32.62#ibcon#read 4, iclass 29, count 0 2006.168.08:02:32.62#ibcon#about to read 5, iclass 29, count 0 2006.168.08:02:32.62#ibcon#read 5, iclass 29, count 0 2006.168.08:02:32.62#ibcon#about to read 6, iclass 29, count 0 2006.168.08:02:32.62#ibcon#read 6, iclass 29, count 0 2006.168.08:02:32.62#ibcon#end of sib2, iclass 29, count 0 2006.168.08:02:32.62#ibcon#*after write, iclass 29, count 0 2006.168.08:02:32.62#ibcon#*before return 0, iclass 29, count 0 2006.168.08:02:32.62#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:02:32.62#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:02:32.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.168.08:02:32.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.168.08:02:32.62$vc4f8/vabw=wide 2006.168.08:02:32.62#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.168.08:02:32.62#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.168.08:02:32.62#ibcon#ireg 8 cls_cnt 0 2006.168.08:02:32.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:02:32.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:02:32.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:02:32.62#ibcon#enter wrdev, iclass 31, count 0 2006.168.08:02:32.62#ibcon#first serial, iclass 31, count 0 2006.168.08:02:32.62#ibcon#enter sib2, iclass 31, count 0 2006.168.08:02:32.62#ibcon#flushed, iclass 31, count 0 2006.168.08:02:32.62#ibcon#about to write, iclass 31, count 0 2006.168.08:02:32.62#ibcon#wrote, iclass 31, count 0 2006.168.08:02:32.62#ibcon#about to read 3, iclass 31, count 0 2006.168.08:02:32.64#ibcon#read 3, iclass 31, count 0 2006.168.08:02:32.64#ibcon#about to read 4, iclass 31, count 0 2006.168.08:02:32.64#ibcon#read 4, iclass 31, count 0 2006.168.08:02:32.64#ibcon#about to read 5, iclass 31, count 0 2006.168.08:02:32.64#ibcon#read 5, iclass 31, count 0 2006.168.08:02:32.64#ibcon#about to read 6, iclass 31, count 0 2006.168.08:02:32.64#ibcon#read 6, iclass 31, count 0 2006.168.08:02:32.64#ibcon#end of sib2, iclass 31, count 0 2006.168.08:02:32.64#ibcon#*mode == 0, iclass 31, count 0 2006.168.08:02:32.64#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.168.08:02:32.64#ibcon#[25=BW32\r\n] 2006.168.08:02:32.64#ibcon#*before write, iclass 31, count 0 2006.168.08:02:32.64#ibcon#enter sib2, iclass 31, count 0 2006.168.08:02:32.64#ibcon#flushed, iclass 31, count 0 2006.168.08:02:32.64#ibcon#about to write, iclass 31, count 0 2006.168.08:02:32.64#ibcon#wrote, iclass 31, count 0 2006.168.08:02:32.64#ibcon#about to read 3, iclass 31, count 0 2006.168.08:02:32.67#ibcon#read 3, iclass 31, count 0 2006.168.08:02:32.67#ibcon#about to read 4, iclass 31, count 0 2006.168.08:02:32.67#ibcon#read 4, iclass 31, count 0 2006.168.08:02:32.67#ibcon#about to read 5, iclass 31, count 0 2006.168.08:02:32.67#ibcon#read 5, iclass 31, count 0 2006.168.08:02:32.67#ibcon#about to read 6, iclass 31, count 0 2006.168.08:02:32.67#ibcon#read 6, iclass 31, count 0 2006.168.08:02:32.67#ibcon#end of sib2, iclass 31, count 0 2006.168.08:02:32.67#ibcon#*after write, iclass 31, count 0 2006.168.08:02:32.67#ibcon#*before return 0, iclass 31, count 0 2006.168.08:02:32.67#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:02:32.67#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:02:32.67#ibcon#about to clear, iclass 31 cls_cnt 0 2006.168.08:02:32.67#ibcon#cleared, iclass 31 cls_cnt 0 2006.168.08:02:32.67$vc4f8/vbbw=wide 2006.168.08:02:32.67#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.168.08:02:32.67#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.168.08:02:32.67#ibcon#ireg 8 cls_cnt 0 2006.168.08:02:32.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:02:32.74#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:02:32.74#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:02:32.74#ibcon#enter wrdev, iclass 33, count 0 2006.168.08:02:32.74#ibcon#first serial, iclass 33, count 0 2006.168.08:02:32.74#ibcon#enter sib2, iclass 33, count 0 2006.168.08:02:32.74#ibcon#flushed, iclass 33, count 0 2006.168.08:02:32.74#ibcon#about to write, iclass 33, count 0 2006.168.08:02:32.74#ibcon#wrote, iclass 33, count 0 2006.168.08:02:32.74#ibcon#about to read 3, iclass 33, count 0 2006.168.08:02:32.76#ibcon#read 3, iclass 33, count 0 2006.168.08:02:32.76#ibcon#about to read 4, iclass 33, count 0 2006.168.08:02:32.76#ibcon#read 4, iclass 33, count 0 2006.168.08:02:32.76#ibcon#about to read 5, iclass 33, count 0 2006.168.08:02:32.76#ibcon#read 5, iclass 33, count 0 2006.168.08:02:32.76#ibcon#about to read 6, iclass 33, count 0 2006.168.08:02:32.76#ibcon#read 6, iclass 33, count 0 2006.168.08:02:32.76#ibcon#end of sib2, iclass 33, count 0 2006.168.08:02:32.76#ibcon#*mode == 0, iclass 33, count 0 2006.168.08:02:32.76#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.168.08:02:32.76#ibcon#[27=BW32\r\n] 2006.168.08:02:32.76#ibcon#*before write, iclass 33, count 0 2006.168.08:02:32.76#ibcon#enter sib2, iclass 33, count 0 2006.168.08:02:32.76#ibcon#flushed, iclass 33, count 0 2006.168.08:02:32.76#ibcon#about to write, iclass 33, count 0 2006.168.08:02:32.76#ibcon#wrote, iclass 33, count 0 2006.168.08:02:32.76#ibcon#about to read 3, iclass 33, count 0 2006.168.08:02:32.79#ibcon#read 3, iclass 33, count 0 2006.168.08:02:32.79#ibcon#about to read 4, iclass 33, count 0 2006.168.08:02:32.79#ibcon#read 4, iclass 33, count 0 2006.168.08:02:32.79#ibcon#about to read 5, iclass 33, count 0 2006.168.08:02:32.79#ibcon#read 5, iclass 33, count 0 2006.168.08:02:32.79#ibcon#about to read 6, iclass 33, count 0 2006.168.08:02:32.79#ibcon#read 6, iclass 33, count 0 2006.168.08:02:32.79#ibcon#end of sib2, iclass 33, count 0 2006.168.08:02:32.79#ibcon#*after write, iclass 33, count 0 2006.168.08:02:32.79#ibcon#*before return 0, iclass 33, count 0 2006.168.08:02:32.79#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:02:32.79#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:02:32.79#ibcon#about to clear, iclass 33 cls_cnt 0 2006.168.08:02:32.79#ibcon#cleared, iclass 33 cls_cnt 0 2006.168.08:02:32.79$4f8m12a/ifd4f 2006.168.08:02:32.79$ifd4f/lo= 2006.168.08:02:32.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.08:02:32.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.08:02:32.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.08:02:32.79$ifd4f/patch= 2006.168.08:02:32.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.08:02:32.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.08:02:32.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.08:02:32.79$4f8m12a/"form=m,16.000,1:2 2006.168.08:02:32.79$4f8m12a/"tpicd 2006.168.08:02:32.79$4f8m12a/echo=off 2006.168.08:02:32.79$4f8m12a/xlog=off 2006.168.08:02:32.79:!2006.168.08:03:00 2006.168.08:02:44.13#trakl#Source acquired 2006.168.08:02:45.13#flagr#flagr/antenna,acquired 2006.168.08:03:00.00:preob 2006.168.08:03:01.14/onsource/TRACKING 2006.168.08:03:01.14:!2006.168.08:03:10 2006.168.08:03:10.00:data_valid=on 2006.168.08:03:10.00:midob 2006.168.08:03:10.14/onsource/TRACKING 2006.168.08:03:10.14/wx/27.00,1004.5,74 2006.168.08:03:10.28/cable/+6.4726E-03 2006.168.08:03:11.37/va/01,08,usb,yes,30,32 2006.168.08:03:11.37/va/02,07,usb,yes,31,32 2006.168.08:03:11.37/va/03,06,usb,yes,32,33 2006.168.08:03:11.37/va/04,07,usb,yes,31,34 2006.168.08:03:11.37/va/05,07,usb,yes,32,33 2006.168.08:03:11.37/va/06,06,usb,yes,31,31 2006.168.08:03:11.37/va/07,06,usb,yes,31,31 2006.168.08:03:11.37/va/08,07,usb,yes,30,29 2006.168.08:03:11.60/valo/01,532.99,yes,locked 2006.168.08:03:11.60/valo/02,572.99,yes,locked 2006.168.08:03:11.60/valo/03,672.99,yes,locked 2006.168.08:03:11.60/valo/04,832.99,yes,locked 2006.168.08:03:11.60/valo/05,652.99,yes,locked 2006.168.08:03:11.60/valo/06,772.99,yes,locked 2006.168.08:03:11.60/valo/07,832.99,yes,locked 2006.168.08:03:11.60/valo/08,852.99,yes,locked 2006.168.08:03:12.69/vb/01,04,usb,yes,30,29 2006.168.08:03:12.69/vb/02,04,usb,yes,32,33 2006.168.08:03:12.69/vb/03,04,usb,yes,28,32 2006.168.08:03:12.69/vb/04,04,usb,yes,29,29 2006.168.08:03:12.69/vb/05,04,usb,yes,28,32 2006.168.08:03:12.69/vb/06,04,usb,yes,29,31 2006.168.08:03:12.69/vb/07,04,usb,yes,31,30 2006.168.08:03:12.69/vb/08,04,usb,yes,28,31 2006.168.08:03:12.92/vblo/01,632.99,yes,locked 2006.168.08:03:12.92/vblo/02,640.99,yes,locked 2006.168.08:03:12.92/vblo/03,656.99,yes,locked 2006.168.08:03:12.92/vblo/04,712.99,yes,locked 2006.168.08:03:12.92/vblo/05,744.99,yes,locked 2006.168.08:03:12.92/vblo/06,752.99,yes,locked 2006.168.08:03:12.92/vblo/07,734.99,yes,locked 2006.168.08:03:12.92/vblo/08,744.99,yes,locked 2006.168.08:03:13.07/vabw/8 2006.168.08:03:13.22/vbbw/8 2006.168.08:03:13.31/xfe/off,on,14.7 2006.168.08:03:13.69/ifatt/23,28,28,28 2006.168.08:03:14.08/fmout-gps/S +4.20E-07 2006.168.08:03:14.12:!2006.168.08:04:10 2006.168.08:04:10.00:data_valid=off 2006.168.08:04:10.00:postob 2006.168.08:04:10.13/cable/+6.4715E-03 2006.168.08:04:10.13/wx/26.99,1004.5,74 2006.168.08:04:11.07/fmout-gps/S +4.19E-07 2006.168.08:04:11.07:scan_name=168-0805,k06168,60 2006.168.08:04:11.08:source=1357+769,135755.37,764321.1,2000.0,cw 2006.168.08:04:11.14#flagr#flagr/antenna,new-source 2006.168.08:04:12.14:checkk5 2006.168.08:04:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.168.08:04:12.91/chk_autoobs//k5ts2/ autoobs is running! 2006.168.08:04:13.29/chk_autoobs//k5ts3/ autoobs is running! 2006.168.08:04:13.66/chk_autoobs//k5ts4/ autoobs is running! 2006.168.08:04:14.04/chk_obsdata//k5ts1/T1680803??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:04:14.41/chk_obsdata//k5ts2/T1680803??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:04:14.78/chk_obsdata//k5ts3/T1680803??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:04:15.15/chk_obsdata//k5ts4/T1680803??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:04:15.84/k5log//k5ts1_log_newline 2006.168.08:04:16.53/k5log//k5ts2_log_newline 2006.168.08:04:17.23/k5log//k5ts3_log_newline 2006.168.08:04:17.91/k5log//k5ts4_log_newline 2006.168.08:04:17.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.08:04:17.94:4f8m12a=2 2006.168.08:04:17.94$4f8m12a/echo=on 2006.168.08:04:17.94$4f8m12a/pcalon 2006.168.08:04:17.94$pcalon/"no phase cal control is implemented here 2006.168.08:04:17.94$4f8m12a/"tpicd=stop 2006.168.08:04:17.94$4f8m12a/vc4f8 2006.168.08:04:17.94$vc4f8/valo=1,532.99 2006.168.08:04:17.95#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.168.08:04:17.95#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.168.08:04:17.95#ibcon#ireg 17 cls_cnt 0 2006.168.08:04:17.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:04:17.95#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:04:17.95#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:04:17.95#ibcon#enter wrdev, iclass 40, count 0 2006.168.08:04:17.95#ibcon#first serial, iclass 40, count 0 2006.168.08:04:17.95#ibcon#enter sib2, iclass 40, count 0 2006.168.08:04:17.95#ibcon#flushed, iclass 40, count 0 2006.168.08:04:17.95#ibcon#about to write, iclass 40, count 0 2006.168.08:04:17.95#ibcon#wrote, iclass 40, count 0 2006.168.08:04:17.95#ibcon#about to read 3, iclass 40, count 0 2006.168.08:04:17.99#ibcon#read 3, iclass 40, count 0 2006.168.08:04:17.99#ibcon#about to read 4, iclass 40, count 0 2006.168.08:04:17.99#ibcon#read 4, iclass 40, count 0 2006.168.08:04:17.99#ibcon#about to read 5, iclass 40, count 0 2006.168.08:04:17.99#ibcon#read 5, iclass 40, count 0 2006.168.08:04:17.99#ibcon#about to read 6, iclass 40, count 0 2006.168.08:04:17.99#ibcon#read 6, iclass 40, count 0 2006.168.08:04:17.99#ibcon#end of sib2, iclass 40, count 0 2006.168.08:04:17.99#ibcon#*mode == 0, iclass 40, count 0 2006.168.08:04:17.99#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.168.08:04:17.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.08:04:17.99#ibcon#*before write, iclass 40, count 0 2006.168.08:04:17.99#ibcon#enter sib2, iclass 40, count 0 2006.168.08:04:17.99#ibcon#flushed, iclass 40, count 0 2006.168.08:04:17.99#ibcon#about to write, iclass 40, count 0 2006.168.08:04:17.99#ibcon#wrote, iclass 40, count 0 2006.168.08:04:17.99#ibcon#about to read 3, iclass 40, count 0 2006.168.08:04:18.03#ibcon#read 3, iclass 40, count 0 2006.168.08:04:18.03#ibcon#about to read 4, iclass 40, count 0 2006.168.08:04:18.03#ibcon#read 4, iclass 40, count 0 2006.168.08:04:18.03#ibcon#about to read 5, iclass 40, count 0 2006.168.08:04:18.03#ibcon#read 5, iclass 40, count 0 2006.168.08:04:18.03#ibcon#about to read 6, iclass 40, count 0 2006.168.08:04:18.03#ibcon#read 6, iclass 40, count 0 2006.168.08:04:18.03#ibcon#end of sib2, iclass 40, count 0 2006.168.08:04:18.03#ibcon#*after write, iclass 40, count 0 2006.168.08:04:18.03#ibcon#*before return 0, iclass 40, count 0 2006.168.08:04:18.03#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:04:18.03#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:04:18.03#ibcon#about to clear, iclass 40 cls_cnt 0 2006.168.08:04:18.03#ibcon#cleared, iclass 40 cls_cnt 0 2006.168.08:04:18.03$vc4f8/va=1,8 2006.168.08:04:18.03#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.168.08:04:18.03#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.168.08:04:18.03#ibcon#ireg 11 cls_cnt 2 2006.168.08:04:18.03#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.168.08:04:18.03#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.168.08:04:18.03#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.168.08:04:18.03#ibcon#enter wrdev, iclass 4, count 2 2006.168.08:04:18.03#ibcon#first serial, iclass 4, count 2 2006.168.08:04:18.03#ibcon#enter sib2, iclass 4, count 2 2006.168.08:04:18.03#ibcon#flushed, iclass 4, count 2 2006.168.08:04:18.03#ibcon#about to write, iclass 4, count 2 2006.168.08:04:18.03#ibcon#wrote, iclass 4, count 2 2006.168.08:04:18.03#ibcon#about to read 3, iclass 4, count 2 2006.168.08:04:18.05#ibcon#read 3, iclass 4, count 2 2006.168.08:04:18.05#ibcon#about to read 4, iclass 4, count 2 2006.168.08:04:18.05#ibcon#read 4, iclass 4, count 2 2006.168.08:04:18.05#ibcon#about to read 5, iclass 4, count 2 2006.168.08:04:18.05#ibcon#read 5, iclass 4, count 2 2006.168.08:04:18.05#ibcon#about to read 6, iclass 4, count 2 2006.168.08:04:18.05#ibcon#read 6, iclass 4, count 2 2006.168.08:04:18.05#ibcon#end of sib2, iclass 4, count 2 2006.168.08:04:18.05#ibcon#*mode == 0, iclass 4, count 2 2006.168.08:04:18.05#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.168.08:04:18.05#ibcon#[25=AT01-08\r\n] 2006.168.08:04:18.05#ibcon#*before write, iclass 4, count 2 2006.168.08:04:18.05#ibcon#enter sib2, iclass 4, count 2 2006.168.08:04:18.05#ibcon#flushed, iclass 4, count 2 2006.168.08:04:18.05#ibcon#about to write, iclass 4, count 2 2006.168.08:04:18.05#ibcon#wrote, iclass 4, count 2 2006.168.08:04:18.05#ibcon#about to read 3, iclass 4, count 2 2006.168.08:04:18.08#ibcon#read 3, iclass 4, count 2 2006.168.08:04:18.08#ibcon#about to read 4, iclass 4, count 2 2006.168.08:04:18.08#ibcon#read 4, iclass 4, count 2 2006.168.08:04:18.08#ibcon#about to read 5, iclass 4, count 2 2006.168.08:04:18.08#ibcon#read 5, iclass 4, count 2 2006.168.08:04:18.08#ibcon#about to read 6, iclass 4, count 2 2006.168.08:04:18.08#ibcon#read 6, iclass 4, count 2 2006.168.08:04:18.08#ibcon#end of sib2, iclass 4, count 2 2006.168.08:04:18.08#ibcon#*after write, iclass 4, count 2 2006.168.08:04:18.08#ibcon#*before return 0, iclass 4, count 2 2006.168.08:04:18.08#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.168.08:04:18.08#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.168.08:04:18.08#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.168.08:04:18.08#ibcon#ireg 7 cls_cnt 0 2006.168.08:04:18.08#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.168.08:04:18.20#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.168.08:04:18.20#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.168.08:04:18.20#ibcon#enter wrdev, iclass 4, count 0 2006.168.08:04:18.20#ibcon#first serial, iclass 4, count 0 2006.168.08:04:18.20#ibcon#enter sib2, iclass 4, count 0 2006.168.08:04:18.20#ibcon#flushed, iclass 4, count 0 2006.168.08:04:18.20#ibcon#about to write, iclass 4, count 0 2006.168.08:04:18.20#ibcon#wrote, iclass 4, count 0 2006.168.08:04:18.20#ibcon#about to read 3, iclass 4, count 0 2006.168.08:04:18.22#ibcon#read 3, iclass 4, count 0 2006.168.08:04:18.22#ibcon#about to read 4, iclass 4, count 0 2006.168.08:04:18.22#ibcon#read 4, iclass 4, count 0 2006.168.08:04:18.22#ibcon#about to read 5, iclass 4, count 0 2006.168.08:04:18.22#ibcon#read 5, iclass 4, count 0 2006.168.08:04:18.22#ibcon#about to read 6, iclass 4, count 0 2006.168.08:04:18.22#ibcon#read 6, iclass 4, count 0 2006.168.08:04:18.22#ibcon#end of sib2, iclass 4, count 0 2006.168.08:04:18.22#ibcon#*mode == 0, iclass 4, count 0 2006.168.08:04:18.22#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.168.08:04:18.22#ibcon#[25=USB\r\n] 2006.168.08:04:18.22#ibcon#*before write, iclass 4, count 0 2006.168.08:04:18.22#ibcon#enter sib2, iclass 4, count 0 2006.168.08:04:18.22#ibcon#flushed, iclass 4, count 0 2006.168.08:04:18.22#ibcon#about to write, iclass 4, count 0 2006.168.08:04:18.22#ibcon#wrote, iclass 4, count 0 2006.168.08:04:18.22#ibcon#about to read 3, iclass 4, count 0 2006.168.08:04:18.25#ibcon#read 3, iclass 4, count 0 2006.168.08:04:18.25#ibcon#about to read 4, iclass 4, count 0 2006.168.08:04:18.25#ibcon#read 4, iclass 4, count 0 2006.168.08:04:18.25#ibcon#about to read 5, iclass 4, count 0 2006.168.08:04:18.25#ibcon#read 5, iclass 4, count 0 2006.168.08:04:18.25#ibcon#about to read 6, iclass 4, count 0 2006.168.08:04:18.25#ibcon#read 6, iclass 4, count 0 2006.168.08:04:18.25#ibcon#end of sib2, iclass 4, count 0 2006.168.08:04:18.25#ibcon#*after write, iclass 4, count 0 2006.168.08:04:18.25#ibcon#*before return 0, iclass 4, count 0 2006.168.08:04:18.25#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.168.08:04:18.25#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.168.08:04:18.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.168.08:04:18.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.168.08:04:18.25$vc4f8/valo=2,572.99 2006.168.08:04:18.25#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.168.08:04:18.25#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.168.08:04:18.25#ibcon#ireg 17 cls_cnt 0 2006.168.08:04:18.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.168.08:04:18.25#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.168.08:04:18.25#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.168.08:04:18.25#ibcon#enter wrdev, iclass 6, count 0 2006.168.08:04:18.25#ibcon#first serial, iclass 6, count 0 2006.168.08:04:18.25#ibcon#enter sib2, iclass 6, count 0 2006.168.08:04:18.25#ibcon#flushed, iclass 6, count 0 2006.168.08:04:18.25#ibcon#about to write, iclass 6, count 0 2006.168.08:04:18.25#ibcon#wrote, iclass 6, count 0 2006.168.08:04:18.25#ibcon#about to read 3, iclass 6, count 0 2006.168.08:04:18.27#ibcon#read 3, iclass 6, count 0 2006.168.08:04:18.27#ibcon#about to read 4, iclass 6, count 0 2006.168.08:04:18.27#ibcon#read 4, iclass 6, count 0 2006.168.08:04:18.27#ibcon#about to read 5, iclass 6, count 0 2006.168.08:04:18.27#ibcon#read 5, iclass 6, count 0 2006.168.08:04:18.27#ibcon#about to read 6, iclass 6, count 0 2006.168.08:04:18.27#ibcon#read 6, iclass 6, count 0 2006.168.08:04:18.27#ibcon#end of sib2, iclass 6, count 0 2006.168.08:04:18.27#ibcon#*mode == 0, iclass 6, count 0 2006.168.08:04:18.27#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.168.08:04:18.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.08:04:18.27#ibcon#*before write, iclass 6, count 0 2006.168.08:04:18.27#ibcon#enter sib2, iclass 6, count 0 2006.168.08:04:18.27#ibcon#flushed, iclass 6, count 0 2006.168.08:04:18.27#ibcon#about to write, iclass 6, count 0 2006.168.08:04:18.27#ibcon#wrote, iclass 6, count 0 2006.168.08:04:18.27#ibcon#about to read 3, iclass 6, count 0 2006.168.08:04:18.31#ibcon#read 3, iclass 6, count 0 2006.168.08:04:18.31#ibcon#about to read 4, iclass 6, count 0 2006.168.08:04:18.31#ibcon#read 4, iclass 6, count 0 2006.168.08:04:18.31#ibcon#about to read 5, iclass 6, count 0 2006.168.08:04:18.31#ibcon#read 5, iclass 6, count 0 2006.168.08:04:18.31#ibcon#about to read 6, iclass 6, count 0 2006.168.08:04:18.31#ibcon#read 6, iclass 6, count 0 2006.168.08:04:18.31#ibcon#end of sib2, iclass 6, count 0 2006.168.08:04:18.31#ibcon#*after write, iclass 6, count 0 2006.168.08:04:18.31#ibcon#*before return 0, iclass 6, count 0 2006.168.08:04:18.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.168.08:04:18.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.168.08:04:18.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.168.08:04:18.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.168.08:04:18.31$vc4f8/va=2,7 2006.168.08:04:18.31#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.168.08:04:18.31#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.168.08:04:18.31#ibcon#ireg 11 cls_cnt 2 2006.168.08:04:18.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.168.08:04:18.37#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.168.08:04:18.37#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.168.08:04:18.37#ibcon#enter wrdev, iclass 10, count 2 2006.168.08:04:18.37#ibcon#first serial, iclass 10, count 2 2006.168.08:04:18.37#ibcon#enter sib2, iclass 10, count 2 2006.168.08:04:18.37#ibcon#flushed, iclass 10, count 2 2006.168.08:04:18.37#ibcon#about to write, iclass 10, count 2 2006.168.08:04:18.37#ibcon#wrote, iclass 10, count 2 2006.168.08:04:18.37#ibcon#about to read 3, iclass 10, count 2 2006.168.08:04:18.39#ibcon#read 3, iclass 10, count 2 2006.168.08:04:18.39#ibcon#about to read 4, iclass 10, count 2 2006.168.08:04:18.39#ibcon#read 4, iclass 10, count 2 2006.168.08:04:18.39#ibcon#about to read 5, iclass 10, count 2 2006.168.08:04:18.39#ibcon#read 5, iclass 10, count 2 2006.168.08:04:18.39#ibcon#about to read 6, iclass 10, count 2 2006.168.08:04:18.39#ibcon#read 6, iclass 10, count 2 2006.168.08:04:18.39#ibcon#end of sib2, iclass 10, count 2 2006.168.08:04:18.39#ibcon#*mode == 0, iclass 10, count 2 2006.168.08:04:18.39#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.168.08:04:18.39#ibcon#[25=AT02-07\r\n] 2006.168.08:04:18.39#ibcon#*before write, iclass 10, count 2 2006.168.08:04:18.39#ibcon#enter sib2, iclass 10, count 2 2006.168.08:04:18.39#ibcon#flushed, iclass 10, count 2 2006.168.08:04:18.39#ibcon#about to write, iclass 10, count 2 2006.168.08:04:18.39#ibcon#wrote, iclass 10, count 2 2006.168.08:04:18.39#ibcon#about to read 3, iclass 10, count 2 2006.168.08:04:18.42#ibcon#read 3, iclass 10, count 2 2006.168.08:04:18.42#ibcon#about to read 4, iclass 10, count 2 2006.168.08:04:18.42#ibcon#read 4, iclass 10, count 2 2006.168.08:04:18.42#ibcon#about to read 5, iclass 10, count 2 2006.168.08:04:18.42#ibcon#read 5, iclass 10, count 2 2006.168.08:04:18.42#ibcon#about to read 6, iclass 10, count 2 2006.168.08:04:18.42#ibcon#read 6, iclass 10, count 2 2006.168.08:04:18.42#ibcon#end of sib2, iclass 10, count 2 2006.168.08:04:18.42#ibcon#*after write, iclass 10, count 2 2006.168.08:04:18.42#ibcon#*before return 0, iclass 10, count 2 2006.168.08:04:18.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.168.08:04:18.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.168.08:04:18.42#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.168.08:04:18.42#ibcon#ireg 7 cls_cnt 0 2006.168.08:04:18.42#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.168.08:04:18.54#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.168.08:04:18.54#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.168.08:04:18.54#ibcon#enter wrdev, iclass 10, count 0 2006.168.08:04:18.54#ibcon#first serial, iclass 10, count 0 2006.168.08:04:18.54#ibcon#enter sib2, iclass 10, count 0 2006.168.08:04:18.54#ibcon#flushed, iclass 10, count 0 2006.168.08:04:18.54#ibcon#about to write, iclass 10, count 0 2006.168.08:04:18.54#ibcon#wrote, iclass 10, count 0 2006.168.08:04:18.54#ibcon#about to read 3, iclass 10, count 0 2006.168.08:04:18.56#ibcon#read 3, iclass 10, count 0 2006.168.08:04:18.56#ibcon#about to read 4, iclass 10, count 0 2006.168.08:04:18.56#ibcon#read 4, iclass 10, count 0 2006.168.08:04:18.56#ibcon#about to read 5, iclass 10, count 0 2006.168.08:04:18.56#ibcon#read 5, iclass 10, count 0 2006.168.08:04:18.56#ibcon#about to read 6, iclass 10, count 0 2006.168.08:04:18.56#ibcon#read 6, iclass 10, count 0 2006.168.08:04:18.56#ibcon#end of sib2, iclass 10, count 0 2006.168.08:04:18.56#ibcon#*mode == 0, iclass 10, count 0 2006.168.08:04:18.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.168.08:04:18.56#ibcon#[25=USB\r\n] 2006.168.08:04:18.56#ibcon#*before write, iclass 10, count 0 2006.168.08:04:18.56#ibcon#enter sib2, iclass 10, count 0 2006.168.08:04:18.56#ibcon#flushed, iclass 10, count 0 2006.168.08:04:18.56#ibcon#about to write, iclass 10, count 0 2006.168.08:04:18.56#ibcon#wrote, iclass 10, count 0 2006.168.08:04:18.56#ibcon#about to read 3, iclass 10, count 0 2006.168.08:04:18.59#ibcon#read 3, iclass 10, count 0 2006.168.08:04:18.59#ibcon#about to read 4, iclass 10, count 0 2006.168.08:04:18.59#ibcon#read 4, iclass 10, count 0 2006.168.08:04:18.59#ibcon#about to read 5, iclass 10, count 0 2006.168.08:04:18.59#ibcon#read 5, iclass 10, count 0 2006.168.08:04:18.59#ibcon#about to read 6, iclass 10, count 0 2006.168.08:04:18.59#ibcon#read 6, iclass 10, count 0 2006.168.08:04:18.59#ibcon#end of sib2, iclass 10, count 0 2006.168.08:04:18.59#ibcon#*after write, iclass 10, count 0 2006.168.08:04:18.59#ibcon#*before return 0, iclass 10, count 0 2006.168.08:04:18.59#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.168.08:04:18.59#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.168.08:04:18.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.168.08:04:18.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.168.08:04:18.59$vc4f8/valo=3,672.99 2006.168.08:04:18.59#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.168.08:04:18.59#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.168.08:04:18.59#ibcon#ireg 17 cls_cnt 0 2006.168.08:04:18.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.168.08:04:18.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.168.08:04:18.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.168.08:04:18.59#ibcon#enter wrdev, iclass 12, count 0 2006.168.08:04:18.59#ibcon#first serial, iclass 12, count 0 2006.168.08:04:18.59#ibcon#enter sib2, iclass 12, count 0 2006.168.08:04:18.59#ibcon#flushed, iclass 12, count 0 2006.168.08:04:18.59#ibcon#about to write, iclass 12, count 0 2006.168.08:04:18.59#ibcon#wrote, iclass 12, count 0 2006.168.08:04:18.59#ibcon#about to read 3, iclass 12, count 0 2006.168.08:04:18.61#ibcon#read 3, iclass 12, count 0 2006.168.08:04:18.61#ibcon#about to read 4, iclass 12, count 0 2006.168.08:04:18.61#ibcon#read 4, iclass 12, count 0 2006.168.08:04:18.61#ibcon#about to read 5, iclass 12, count 0 2006.168.08:04:18.61#ibcon#read 5, iclass 12, count 0 2006.168.08:04:18.61#ibcon#about to read 6, iclass 12, count 0 2006.168.08:04:18.61#ibcon#read 6, iclass 12, count 0 2006.168.08:04:18.61#ibcon#end of sib2, iclass 12, count 0 2006.168.08:04:18.61#ibcon#*mode == 0, iclass 12, count 0 2006.168.08:04:18.61#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.168.08:04:18.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.08:04:18.61#ibcon#*before write, iclass 12, count 0 2006.168.08:04:18.61#ibcon#enter sib2, iclass 12, count 0 2006.168.08:04:18.61#ibcon#flushed, iclass 12, count 0 2006.168.08:04:18.61#ibcon#about to write, iclass 12, count 0 2006.168.08:04:18.61#ibcon#wrote, iclass 12, count 0 2006.168.08:04:18.61#ibcon#about to read 3, iclass 12, count 0 2006.168.08:04:18.65#ibcon#read 3, iclass 12, count 0 2006.168.08:04:18.65#ibcon#about to read 4, iclass 12, count 0 2006.168.08:04:18.65#ibcon#read 4, iclass 12, count 0 2006.168.08:04:18.65#ibcon#about to read 5, iclass 12, count 0 2006.168.08:04:18.65#ibcon#read 5, iclass 12, count 0 2006.168.08:04:18.65#ibcon#about to read 6, iclass 12, count 0 2006.168.08:04:18.65#ibcon#read 6, iclass 12, count 0 2006.168.08:04:18.65#ibcon#end of sib2, iclass 12, count 0 2006.168.08:04:18.65#ibcon#*after write, iclass 12, count 0 2006.168.08:04:18.65#ibcon#*before return 0, iclass 12, count 0 2006.168.08:04:18.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.168.08:04:18.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.168.08:04:18.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.168.08:04:18.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.168.08:04:18.65$vc4f8/va=3,6 2006.168.08:04:18.65#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.168.08:04:18.65#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.168.08:04:18.65#ibcon#ireg 11 cls_cnt 2 2006.168.08:04:18.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.168.08:04:18.72#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.168.08:04:18.72#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.168.08:04:18.72#ibcon#enter wrdev, iclass 14, count 2 2006.168.08:04:18.72#ibcon#first serial, iclass 14, count 2 2006.168.08:04:18.72#ibcon#enter sib2, iclass 14, count 2 2006.168.08:04:18.72#ibcon#flushed, iclass 14, count 2 2006.168.08:04:18.72#ibcon#about to write, iclass 14, count 2 2006.168.08:04:18.72#ibcon#wrote, iclass 14, count 2 2006.168.08:04:18.72#ibcon#about to read 3, iclass 14, count 2 2006.168.08:04:18.73#ibcon#read 3, iclass 14, count 2 2006.168.08:04:18.73#ibcon#about to read 4, iclass 14, count 2 2006.168.08:04:18.73#ibcon#read 4, iclass 14, count 2 2006.168.08:04:18.73#ibcon#about to read 5, iclass 14, count 2 2006.168.08:04:18.73#ibcon#read 5, iclass 14, count 2 2006.168.08:04:18.73#ibcon#about to read 6, iclass 14, count 2 2006.168.08:04:18.73#ibcon#read 6, iclass 14, count 2 2006.168.08:04:18.73#ibcon#end of sib2, iclass 14, count 2 2006.168.08:04:18.73#ibcon#*mode == 0, iclass 14, count 2 2006.168.08:04:18.73#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.168.08:04:18.73#ibcon#[25=AT03-06\r\n] 2006.168.08:04:18.73#ibcon#*before write, iclass 14, count 2 2006.168.08:04:18.73#ibcon#enter sib2, iclass 14, count 2 2006.168.08:04:18.73#ibcon#flushed, iclass 14, count 2 2006.168.08:04:18.73#ibcon#about to write, iclass 14, count 2 2006.168.08:04:18.73#ibcon#wrote, iclass 14, count 2 2006.168.08:04:18.73#ibcon#about to read 3, iclass 14, count 2 2006.168.08:04:18.76#ibcon#read 3, iclass 14, count 2 2006.168.08:04:18.76#ibcon#about to read 4, iclass 14, count 2 2006.168.08:04:18.76#ibcon#read 4, iclass 14, count 2 2006.168.08:04:18.76#ibcon#about to read 5, iclass 14, count 2 2006.168.08:04:18.76#ibcon#read 5, iclass 14, count 2 2006.168.08:04:18.76#ibcon#about to read 6, iclass 14, count 2 2006.168.08:04:18.76#ibcon#read 6, iclass 14, count 2 2006.168.08:04:18.76#ibcon#end of sib2, iclass 14, count 2 2006.168.08:04:18.76#ibcon#*after write, iclass 14, count 2 2006.168.08:04:18.76#ibcon#*before return 0, iclass 14, count 2 2006.168.08:04:18.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.168.08:04:18.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.168.08:04:18.76#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.168.08:04:18.76#ibcon#ireg 7 cls_cnt 0 2006.168.08:04:18.76#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.168.08:04:18.88#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.168.08:04:18.88#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.168.08:04:18.88#ibcon#enter wrdev, iclass 14, count 0 2006.168.08:04:18.88#ibcon#first serial, iclass 14, count 0 2006.168.08:04:18.88#ibcon#enter sib2, iclass 14, count 0 2006.168.08:04:18.88#ibcon#flushed, iclass 14, count 0 2006.168.08:04:18.88#ibcon#about to write, iclass 14, count 0 2006.168.08:04:18.88#ibcon#wrote, iclass 14, count 0 2006.168.08:04:18.88#ibcon#about to read 3, iclass 14, count 0 2006.168.08:04:18.90#ibcon#read 3, iclass 14, count 0 2006.168.08:04:18.90#ibcon#about to read 4, iclass 14, count 0 2006.168.08:04:18.90#ibcon#read 4, iclass 14, count 0 2006.168.08:04:18.90#ibcon#about to read 5, iclass 14, count 0 2006.168.08:04:18.90#ibcon#read 5, iclass 14, count 0 2006.168.08:04:18.90#ibcon#about to read 6, iclass 14, count 0 2006.168.08:04:18.90#ibcon#read 6, iclass 14, count 0 2006.168.08:04:18.90#ibcon#end of sib2, iclass 14, count 0 2006.168.08:04:18.90#ibcon#*mode == 0, iclass 14, count 0 2006.168.08:04:18.90#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.168.08:04:18.90#ibcon#[25=USB\r\n] 2006.168.08:04:18.90#ibcon#*before write, iclass 14, count 0 2006.168.08:04:18.90#ibcon#enter sib2, iclass 14, count 0 2006.168.08:04:18.90#ibcon#flushed, iclass 14, count 0 2006.168.08:04:18.90#ibcon#about to write, iclass 14, count 0 2006.168.08:04:18.90#ibcon#wrote, iclass 14, count 0 2006.168.08:04:18.90#ibcon#about to read 3, iclass 14, count 0 2006.168.08:04:18.93#ibcon#read 3, iclass 14, count 0 2006.168.08:04:18.93#ibcon#about to read 4, iclass 14, count 0 2006.168.08:04:18.93#ibcon#read 4, iclass 14, count 0 2006.168.08:04:18.93#ibcon#about to read 5, iclass 14, count 0 2006.168.08:04:18.93#ibcon#read 5, iclass 14, count 0 2006.168.08:04:18.93#ibcon#about to read 6, iclass 14, count 0 2006.168.08:04:18.93#ibcon#read 6, iclass 14, count 0 2006.168.08:04:18.93#ibcon#end of sib2, iclass 14, count 0 2006.168.08:04:18.93#ibcon#*after write, iclass 14, count 0 2006.168.08:04:18.93#ibcon#*before return 0, iclass 14, count 0 2006.168.08:04:18.93#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.168.08:04:18.93#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.168.08:04:18.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.168.08:04:18.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.168.08:04:18.93$vc4f8/valo=4,832.99 2006.168.08:04:18.93#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.168.08:04:18.93#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.168.08:04:18.93#ibcon#ireg 17 cls_cnt 0 2006.168.08:04:18.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.168.08:04:18.93#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.168.08:04:18.93#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.168.08:04:18.93#ibcon#enter wrdev, iclass 16, count 0 2006.168.08:04:18.93#ibcon#first serial, iclass 16, count 0 2006.168.08:04:18.93#ibcon#enter sib2, iclass 16, count 0 2006.168.08:04:18.93#ibcon#flushed, iclass 16, count 0 2006.168.08:04:18.93#ibcon#about to write, iclass 16, count 0 2006.168.08:04:18.93#ibcon#wrote, iclass 16, count 0 2006.168.08:04:18.93#ibcon#about to read 3, iclass 16, count 0 2006.168.08:04:18.95#ibcon#read 3, iclass 16, count 0 2006.168.08:04:18.95#ibcon#about to read 4, iclass 16, count 0 2006.168.08:04:18.95#ibcon#read 4, iclass 16, count 0 2006.168.08:04:18.95#ibcon#about to read 5, iclass 16, count 0 2006.168.08:04:18.95#ibcon#read 5, iclass 16, count 0 2006.168.08:04:18.95#ibcon#about to read 6, iclass 16, count 0 2006.168.08:04:18.95#ibcon#read 6, iclass 16, count 0 2006.168.08:04:18.95#ibcon#end of sib2, iclass 16, count 0 2006.168.08:04:18.95#ibcon#*mode == 0, iclass 16, count 0 2006.168.08:04:18.95#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.168.08:04:18.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.08:04:18.95#ibcon#*before write, iclass 16, count 0 2006.168.08:04:18.95#ibcon#enter sib2, iclass 16, count 0 2006.168.08:04:18.95#ibcon#flushed, iclass 16, count 0 2006.168.08:04:18.95#ibcon#about to write, iclass 16, count 0 2006.168.08:04:18.95#ibcon#wrote, iclass 16, count 0 2006.168.08:04:18.95#ibcon#about to read 3, iclass 16, count 0 2006.168.08:04:18.99#ibcon#read 3, iclass 16, count 0 2006.168.08:04:18.99#ibcon#about to read 4, iclass 16, count 0 2006.168.08:04:18.99#ibcon#read 4, iclass 16, count 0 2006.168.08:04:18.99#ibcon#about to read 5, iclass 16, count 0 2006.168.08:04:18.99#ibcon#read 5, iclass 16, count 0 2006.168.08:04:18.99#ibcon#about to read 6, iclass 16, count 0 2006.168.08:04:18.99#ibcon#read 6, iclass 16, count 0 2006.168.08:04:18.99#ibcon#end of sib2, iclass 16, count 0 2006.168.08:04:18.99#ibcon#*after write, iclass 16, count 0 2006.168.08:04:18.99#ibcon#*before return 0, iclass 16, count 0 2006.168.08:04:18.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.168.08:04:18.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.168.08:04:18.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.168.08:04:18.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.168.08:04:18.99$vc4f8/va=4,7 2006.168.08:04:18.99#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.168.08:04:18.99#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.168.08:04:18.99#ibcon#ireg 11 cls_cnt 2 2006.168.08:04:18.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.168.08:04:19.05#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.168.08:04:19.05#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.168.08:04:19.05#ibcon#enter wrdev, iclass 18, count 2 2006.168.08:04:19.05#ibcon#first serial, iclass 18, count 2 2006.168.08:04:19.05#ibcon#enter sib2, iclass 18, count 2 2006.168.08:04:19.05#ibcon#flushed, iclass 18, count 2 2006.168.08:04:19.05#ibcon#about to write, iclass 18, count 2 2006.168.08:04:19.05#ibcon#wrote, iclass 18, count 2 2006.168.08:04:19.05#ibcon#about to read 3, iclass 18, count 2 2006.168.08:04:19.07#ibcon#read 3, iclass 18, count 2 2006.168.08:04:19.07#ibcon#about to read 4, iclass 18, count 2 2006.168.08:04:19.07#ibcon#read 4, iclass 18, count 2 2006.168.08:04:19.07#ibcon#about to read 5, iclass 18, count 2 2006.168.08:04:19.07#ibcon#read 5, iclass 18, count 2 2006.168.08:04:19.07#ibcon#about to read 6, iclass 18, count 2 2006.168.08:04:19.07#ibcon#read 6, iclass 18, count 2 2006.168.08:04:19.07#ibcon#end of sib2, iclass 18, count 2 2006.168.08:04:19.07#ibcon#*mode == 0, iclass 18, count 2 2006.168.08:04:19.07#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.168.08:04:19.07#ibcon#[25=AT04-07\r\n] 2006.168.08:04:19.07#ibcon#*before write, iclass 18, count 2 2006.168.08:04:19.07#ibcon#enter sib2, iclass 18, count 2 2006.168.08:04:19.07#ibcon#flushed, iclass 18, count 2 2006.168.08:04:19.07#ibcon#about to write, iclass 18, count 2 2006.168.08:04:19.07#ibcon#wrote, iclass 18, count 2 2006.168.08:04:19.07#ibcon#about to read 3, iclass 18, count 2 2006.168.08:04:19.10#ibcon#read 3, iclass 18, count 2 2006.168.08:04:19.10#ibcon#about to read 4, iclass 18, count 2 2006.168.08:04:19.10#ibcon#read 4, iclass 18, count 2 2006.168.08:04:19.10#ibcon#about to read 5, iclass 18, count 2 2006.168.08:04:19.10#ibcon#read 5, iclass 18, count 2 2006.168.08:04:19.10#ibcon#about to read 6, iclass 18, count 2 2006.168.08:04:19.10#ibcon#read 6, iclass 18, count 2 2006.168.08:04:19.10#ibcon#end of sib2, iclass 18, count 2 2006.168.08:04:19.10#ibcon#*after write, iclass 18, count 2 2006.168.08:04:19.10#ibcon#*before return 0, iclass 18, count 2 2006.168.08:04:19.10#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.168.08:04:19.10#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.168.08:04:19.10#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.168.08:04:19.10#ibcon#ireg 7 cls_cnt 0 2006.168.08:04:19.10#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.168.08:04:19.22#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.168.08:04:19.22#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.168.08:04:19.22#ibcon#enter wrdev, iclass 18, count 0 2006.168.08:04:19.22#ibcon#first serial, iclass 18, count 0 2006.168.08:04:19.22#ibcon#enter sib2, iclass 18, count 0 2006.168.08:04:19.22#ibcon#flushed, iclass 18, count 0 2006.168.08:04:19.22#ibcon#about to write, iclass 18, count 0 2006.168.08:04:19.22#ibcon#wrote, iclass 18, count 0 2006.168.08:04:19.22#ibcon#about to read 3, iclass 18, count 0 2006.168.08:04:19.24#ibcon#read 3, iclass 18, count 0 2006.168.08:04:19.24#ibcon#about to read 4, iclass 18, count 0 2006.168.08:04:19.24#ibcon#read 4, iclass 18, count 0 2006.168.08:04:19.24#ibcon#about to read 5, iclass 18, count 0 2006.168.08:04:19.24#ibcon#read 5, iclass 18, count 0 2006.168.08:04:19.24#ibcon#about to read 6, iclass 18, count 0 2006.168.08:04:19.24#ibcon#read 6, iclass 18, count 0 2006.168.08:04:19.24#ibcon#end of sib2, iclass 18, count 0 2006.168.08:04:19.24#ibcon#*mode == 0, iclass 18, count 0 2006.168.08:04:19.24#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.08:04:19.24#ibcon#[25=USB\r\n] 2006.168.08:04:19.24#ibcon#*before write, iclass 18, count 0 2006.168.08:04:19.24#ibcon#enter sib2, iclass 18, count 0 2006.168.08:04:19.24#ibcon#flushed, iclass 18, count 0 2006.168.08:04:19.24#ibcon#about to write, iclass 18, count 0 2006.168.08:04:19.24#ibcon#wrote, iclass 18, count 0 2006.168.08:04:19.24#ibcon#about to read 3, iclass 18, count 0 2006.168.08:04:19.27#ibcon#read 3, iclass 18, count 0 2006.168.08:04:19.27#ibcon#about to read 4, iclass 18, count 0 2006.168.08:04:19.27#ibcon#read 4, iclass 18, count 0 2006.168.08:04:19.27#ibcon#about to read 5, iclass 18, count 0 2006.168.08:04:19.27#ibcon#read 5, iclass 18, count 0 2006.168.08:04:19.27#ibcon#about to read 6, iclass 18, count 0 2006.168.08:04:19.27#ibcon#read 6, iclass 18, count 0 2006.168.08:04:19.27#ibcon#end of sib2, iclass 18, count 0 2006.168.08:04:19.27#ibcon#*after write, iclass 18, count 0 2006.168.08:04:19.27#ibcon#*before return 0, iclass 18, count 0 2006.168.08:04:19.27#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.168.08:04:19.27#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.168.08:04:19.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.08:04:19.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.08:04:19.27$vc4f8/valo=5,652.99 2006.168.08:04:19.27#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.168.08:04:19.27#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.168.08:04:19.27#ibcon#ireg 17 cls_cnt 0 2006.168.08:04:19.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:04:19.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:04:19.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:04:19.27#ibcon#enter wrdev, iclass 20, count 0 2006.168.08:04:19.27#ibcon#first serial, iclass 20, count 0 2006.168.08:04:19.27#ibcon#enter sib2, iclass 20, count 0 2006.168.08:04:19.27#ibcon#flushed, iclass 20, count 0 2006.168.08:04:19.27#ibcon#about to write, iclass 20, count 0 2006.168.08:04:19.27#ibcon#wrote, iclass 20, count 0 2006.168.08:04:19.27#ibcon#about to read 3, iclass 20, count 0 2006.168.08:04:19.29#ibcon#read 3, iclass 20, count 0 2006.168.08:04:19.29#ibcon#about to read 4, iclass 20, count 0 2006.168.08:04:19.29#ibcon#read 4, iclass 20, count 0 2006.168.08:04:19.29#ibcon#about to read 5, iclass 20, count 0 2006.168.08:04:19.29#ibcon#read 5, iclass 20, count 0 2006.168.08:04:19.29#ibcon#about to read 6, iclass 20, count 0 2006.168.08:04:19.29#ibcon#read 6, iclass 20, count 0 2006.168.08:04:19.29#ibcon#end of sib2, iclass 20, count 0 2006.168.08:04:19.29#ibcon#*mode == 0, iclass 20, count 0 2006.168.08:04:19.29#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.168.08:04:19.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.08:04:19.29#ibcon#*before write, iclass 20, count 0 2006.168.08:04:19.29#ibcon#enter sib2, iclass 20, count 0 2006.168.08:04:19.29#ibcon#flushed, iclass 20, count 0 2006.168.08:04:19.29#ibcon#about to write, iclass 20, count 0 2006.168.08:04:19.29#ibcon#wrote, iclass 20, count 0 2006.168.08:04:19.29#ibcon#about to read 3, iclass 20, count 0 2006.168.08:04:19.33#ibcon#read 3, iclass 20, count 0 2006.168.08:04:19.33#ibcon#about to read 4, iclass 20, count 0 2006.168.08:04:19.33#ibcon#read 4, iclass 20, count 0 2006.168.08:04:19.33#ibcon#about to read 5, iclass 20, count 0 2006.168.08:04:19.33#ibcon#read 5, iclass 20, count 0 2006.168.08:04:19.33#ibcon#about to read 6, iclass 20, count 0 2006.168.08:04:19.33#ibcon#read 6, iclass 20, count 0 2006.168.08:04:19.33#ibcon#end of sib2, iclass 20, count 0 2006.168.08:04:19.33#ibcon#*after write, iclass 20, count 0 2006.168.08:04:19.33#ibcon#*before return 0, iclass 20, count 0 2006.168.08:04:19.33#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:04:19.33#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:04:19.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.168.08:04:19.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.168.08:04:19.33$vc4f8/va=5,7 2006.168.08:04:19.33#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.168.08:04:19.33#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.168.08:04:19.33#ibcon#ireg 11 cls_cnt 2 2006.168.08:04:19.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.168.08:04:19.39#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.168.08:04:19.39#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.168.08:04:19.39#ibcon#enter wrdev, iclass 22, count 2 2006.168.08:04:19.39#ibcon#first serial, iclass 22, count 2 2006.168.08:04:19.39#ibcon#enter sib2, iclass 22, count 2 2006.168.08:04:19.39#ibcon#flushed, iclass 22, count 2 2006.168.08:04:19.39#ibcon#about to write, iclass 22, count 2 2006.168.08:04:19.39#ibcon#wrote, iclass 22, count 2 2006.168.08:04:19.39#ibcon#about to read 3, iclass 22, count 2 2006.168.08:04:19.41#ibcon#read 3, iclass 22, count 2 2006.168.08:04:19.41#ibcon#about to read 4, iclass 22, count 2 2006.168.08:04:19.41#ibcon#read 4, iclass 22, count 2 2006.168.08:04:19.41#ibcon#about to read 5, iclass 22, count 2 2006.168.08:04:19.41#ibcon#read 5, iclass 22, count 2 2006.168.08:04:19.41#ibcon#about to read 6, iclass 22, count 2 2006.168.08:04:19.41#ibcon#read 6, iclass 22, count 2 2006.168.08:04:19.41#ibcon#end of sib2, iclass 22, count 2 2006.168.08:04:19.41#ibcon#*mode == 0, iclass 22, count 2 2006.168.08:04:19.41#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.168.08:04:19.41#ibcon#[25=AT05-07\r\n] 2006.168.08:04:19.41#ibcon#*before write, iclass 22, count 2 2006.168.08:04:19.41#ibcon#enter sib2, iclass 22, count 2 2006.168.08:04:19.41#ibcon#flushed, iclass 22, count 2 2006.168.08:04:19.41#ibcon#about to write, iclass 22, count 2 2006.168.08:04:19.41#ibcon#wrote, iclass 22, count 2 2006.168.08:04:19.41#ibcon#about to read 3, iclass 22, count 2 2006.168.08:04:19.44#ibcon#read 3, iclass 22, count 2 2006.168.08:04:19.44#ibcon#about to read 4, iclass 22, count 2 2006.168.08:04:19.44#ibcon#read 4, iclass 22, count 2 2006.168.08:04:19.44#ibcon#about to read 5, iclass 22, count 2 2006.168.08:04:19.44#ibcon#read 5, iclass 22, count 2 2006.168.08:04:19.44#ibcon#about to read 6, iclass 22, count 2 2006.168.08:04:19.44#ibcon#read 6, iclass 22, count 2 2006.168.08:04:19.44#ibcon#end of sib2, iclass 22, count 2 2006.168.08:04:19.44#ibcon#*after write, iclass 22, count 2 2006.168.08:04:19.44#ibcon#*before return 0, iclass 22, count 2 2006.168.08:04:19.44#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.168.08:04:19.44#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.168.08:04:19.44#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.168.08:04:19.44#ibcon#ireg 7 cls_cnt 0 2006.168.08:04:19.44#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.168.08:04:19.56#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.168.08:04:19.56#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.168.08:04:19.56#ibcon#enter wrdev, iclass 22, count 0 2006.168.08:04:19.56#ibcon#first serial, iclass 22, count 0 2006.168.08:04:19.56#ibcon#enter sib2, iclass 22, count 0 2006.168.08:04:19.56#ibcon#flushed, iclass 22, count 0 2006.168.08:04:19.56#ibcon#about to write, iclass 22, count 0 2006.168.08:04:19.56#ibcon#wrote, iclass 22, count 0 2006.168.08:04:19.56#ibcon#about to read 3, iclass 22, count 0 2006.168.08:04:19.58#ibcon#read 3, iclass 22, count 0 2006.168.08:04:19.58#ibcon#about to read 4, iclass 22, count 0 2006.168.08:04:19.58#ibcon#read 4, iclass 22, count 0 2006.168.08:04:19.58#ibcon#about to read 5, iclass 22, count 0 2006.168.08:04:19.58#ibcon#read 5, iclass 22, count 0 2006.168.08:04:19.58#ibcon#about to read 6, iclass 22, count 0 2006.168.08:04:19.58#ibcon#read 6, iclass 22, count 0 2006.168.08:04:19.58#ibcon#end of sib2, iclass 22, count 0 2006.168.08:04:19.58#ibcon#*mode == 0, iclass 22, count 0 2006.168.08:04:19.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.168.08:04:19.58#ibcon#[25=USB\r\n] 2006.168.08:04:19.58#ibcon#*before write, iclass 22, count 0 2006.168.08:04:19.58#ibcon#enter sib2, iclass 22, count 0 2006.168.08:04:19.58#ibcon#flushed, iclass 22, count 0 2006.168.08:04:19.58#ibcon#about to write, iclass 22, count 0 2006.168.08:04:19.58#ibcon#wrote, iclass 22, count 0 2006.168.08:04:19.58#ibcon#about to read 3, iclass 22, count 0 2006.168.08:04:19.61#ibcon#read 3, iclass 22, count 0 2006.168.08:04:19.61#ibcon#about to read 4, iclass 22, count 0 2006.168.08:04:19.61#ibcon#read 4, iclass 22, count 0 2006.168.08:04:19.61#ibcon#about to read 5, iclass 22, count 0 2006.168.08:04:19.61#ibcon#read 5, iclass 22, count 0 2006.168.08:04:19.61#ibcon#about to read 6, iclass 22, count 0 2006.168.08:04:19.61#ibcon#read 6, iclass 22, count 0 2006.168.08:04:19.61#ibcon#end of sib2, iclass 22, count 0 2006.168.08:04:19.61#ibcon#*after write, iclass 22, count 0 2006.168.08:04:19.61#ibcon#*before return 0, iclass 22, count 0 2006.168.08:04:19.61#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.168.08:04:19.61#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.168.08:04:19.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.168.08:04:19.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.168.08:04:19.61$vc4f8/valo=6,772.99 2006.168.08:04:19.61#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.168.08:04:19.61#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.168.08:04:19.61#ibcon#ireg 17 cls_cnt 0 2006.168.08:04:19.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.168.08:04:19.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.168.08:04:19.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.168.08:04:19.61#ibcon#enter wrdev, iclass 24, count 0 2006.168.08:04:19.61#ibcon#first serial, iclass 24, count 0 2006.168.08:04:19.61#ibcon#enter sib2, iclass 24, count 0 2006.168.08:04:19.61#ibcon#flushed, iclass 24, count 0 2006.168.08:04:19.61#ibcon#about to write, iclass 24, count 0 2006.168.08:04:19.61#ibcon#wrote, iclass 24, count 0 2006.168.08:04:19.61#ibcon#about to read 3, iclass 24, count 0 2006.168.08:04:19.63#ibcon#read 3, iclass 24, count 0 2006.168.08:04:19.63#ibcon#about to read 4, iclass 24, count 0 2006.168.08:04:19.63#ibcon#read 4, iclass 24, count 0 2006.168.08:04:19.63#ibcon#about to read 5, iclass 24, count 0 2006.168.08:04:19.63#ibcon#read 5, iclass 24, count 0 2006.168.08:04:19.63#ibcon#about to read 6, iclass 24, count 0 2006.168.08:04:19.63#ibcon#read 6, iclass 24, count 0 2006.168.08:04:19.63#ibcon#end of sib2, iclass 24, count 0 2006.168.08:04:19.63#ibcon#*mode == 0, iclass 24, count 0 2006.168.08:04:19.63#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.168.08:04:19.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.08:04:19.63#ibcon#*before write, iclass 24, count 0 2006.168.08:04:19.63#ibcon#enter sib2, iclass 24, count 0 2006.168.08:04:19.63#ibcon#flushed, iclass 24, count 0 2006.168.08:04:19.63#ibcon#about to write, iclass 24, count 0 2006.168.08:04:19.63#ibcon#wrote, iclass 24, count 0 2006.168.08:04:19.63#ibcon#about to read 3, iclass 24, count 0 2006.168.08:04:19.67#ibcon#read 3, iclass 24, count 0 2006.168.08:04:19.67#ibcon#about to read 4, iclass 24, count 0 2006.168.08:04:19.67#ibcon#read 4, iclass 24, count 0 2006.168.08:04:19.67#ibcon#about to read 5, iclass 24, count 0 2006.168.08:04:19.67#ibcon#read 5, iclass 24, count 0 2006.168.08:04:19.67#ibcon#about to read 6, iclass 24, count 0 2006.168.08:04:19.67#ibcon#read 6, iclass 24, count 0 2006.168.08:04:19.67#ibcon#end of sib2, iclass 24, count 0 2006.168.08:04:19.67#ibcon#*after write, iclass 24, count 0 2006.168.08:04:19.67#ibcon#*before return 0, iclass 24, count 0 2006.168.08:04:19.67#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.168.08:04:19.67#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.168.08:04:19.67#ibcon#about to clear, iclass 24 cls_cnt 0 2006.168.08:04:19.67#ibcon#cleared, iclass 24 cls_cnt 0 2006.168.08:04:19.67$vc4f8/va=6,6 2006.168.08:04:19.67#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.168.08:04:19.67#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.168.08:04:19.67#ibcon#ireg 11 cls_cnt 2 2006.168.08:04:19.67#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.168.08:04:19.73#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.168.08:04:19.73#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.168.08:04:19.73#ibcon#enter wrdev, iclass 26, count 2 2006.168.08:04:19.73#ibcon#first serial, iclass 26, count 2 2006.168.08:04:19.73#ibcon#enter sib2, iclass 26, count 2 2006.168.08:04:19.73#ibcon#flushed, iclass 26, count 2 2006.168.08:04:19.73#ibcon#about to write, iclass 26, count 2 2006.168.08:04:19.73#ibcon#wrote, iclass 26, count 2 2006.168.08:04:19.73#ibcon#about to read 3, iclass 26, count 2 2006.168.08:04:19.75#ibcon#read 3, iclass 26, count 2 2006.168.08:04:19.75#ibcon#about to read 4, iclass 26, count 2 2006.168.08:04:19.75#ibcon#read 4, iclass 26, count 2 2006.168.08:04:19.75#ibcon#about to read 5, iclass 26, count 2 2006.168.08:04:19.75#ibcon#read 5, iclass 26, count 2 2006.168.08:04:19.75#ibcon#about to read 6, iclass 26, count 2 2006.168.08:04:19.75#ibcon#read 6, iclass 26, count 2 2006.168.08:04:19.75#ibcon#end of sib2, iclass 26, count 2 2006.168.08:04:19.75#ibcon#*mode == 0, iclass 26, count 2 2006.168.08:04:19.75#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.168.08:04:19.75#ibcon#[25=AT06-06\r\n] 2006.168.08:04:19.75#ibcon#*before write, iclass 26, count 2 2006.168.08:04:19.75#ibcon#enter sib2, iclass 26, count 2 2006.168.08:04:19.75#ibcon#flushed, iclass 26, count 2 2006.168.08:04:19.75#ibcon#about to write, iclass 26, count 2 2006.168.08:04:19.75#ibcon#wrote, iclass 26, count 2 2006.168.08:04:19.75#ibcon#about to read 3, iclass 26, count 2 2006.168.08:04:19.78#ibcon#read 3, iclass 26, count 2 2006.168.08:04:19.78#ibcon#about to read 4, iclass 26, count 2 2006.168.08:04:19.78#ibcon#read 4, iclass 26, count 2 2006.168.08:04:19.78#ibcon#about to read 5, iclass 26, count 2 2006.168.08:04:19.78#ibcon#read 5, iclass 26, count 2 2006.168.08:04:19.78#ibcon#about to read 6, iclass 26, count 2 2006.168.08:04:19.78#ibcon#read 6, iclass 26, count 2 2006.168.08:04:19.78#ibcon#end of sib2, iclass 26, count 2 2006.168.08:04:19.78#ibcon#*after write, iclass 26, count 2 2006.168.08:04:19.78#ibcon#*before return 0, iclass 26, count 2 2006.168.08:04:19.78#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.168.08:04:19.78#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.168.08:04:19.78#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.168.08:04:19.78#ibcon#ireg 7 cls_cnt 0 2006.168.08:04:19.78#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.168.08:04:19.90#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.168.08:04:19.90#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.168.08:04:19.90#ibcon#enter wrdev, iclass 26, count 0 2006.168.08:04:19.90#ibcon#first serial, iclass 26, count 0 2006.168.08:04:19.90#ibcon#enter sib2, iclass 26, count 0 2006.168.08:04:19.90#ibcon#flushed, iclass 26, count 0 2006.168.08:04:19.90#ibcon#about to write, iclass 26, count 0 2006.168.08:04:19.90#ibcon#wrote, iclass 26, count 0 2006.168.08:04:19.90#ibcon#about to read 3, iclass 26, count 0 2006.168.08:04:19.92#ibcon#read 3, iclass 26, count 0 2006.168.08:04:19.92#ibcon#about to read 4, iclass 26, count 0 2006.168.08:04:19.92#ibcon#read 4, iclass 26, count 0 2006.168.08:04:19.92#ibcon#about to read 5, iclass 26, count 0 2006.168.08:04:19.92#ibcon#read 5, iclass 26, count 0 2006.168.08:04:19.92#ibcon#about to read 6, iclass 26, count 0 2006.168.08:04:19.92#ibcon#read 6, iclass 26, count 0 2006.168.08:04:19.92#ibcon#end of sib2, iclass 26, count 0 2006.168.08:04:19.92#ibcon#*mode == 0, iclass 26, count 0 2006.168.08:04:19.92#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.168.08:04:19.92#ibcon#[25=USB\r\n] 2006.168.08:04:19.92#ibcon#*before write, iclass 26, count 0 2006.168.08:04:19.92#ibcon#enter sib2, iclass 26, count 0 2006.168.08:04:19.92#ibcon#flushed, iclass 26, count 0 2006.168.08:04:19.92#ibcon#about to write, iclass 26, count 0 2006.168.08:04:19.92#ibcon#wrote, iclass 26, count 0 2006.168.08:04:19.92#ibcon#about to read 3, iclass 26, count 0 2006.168.08:04:19.95#ibcon#read 3, iclass 26, count 0 2006.168.08:04:19.95#ibcon#about to read 4, iclass 26, count 0 2006.168.08:04:19.95#ibcon#read 4, iclass 26, count 0 2006.168.08:04:19.95#ibcon#about to read 5, iclass 26, count 0 2006.168.08:04:19.95#ibcon#read 5, iclass 26, count 0 2006.168.08:04:19.95#ibcon#about to read 6, iclass 26, count 0 2006.168.08:04:19.95#ibcon#read 6, iclass 26, count 0 2006.168.08:04:19.95#ibcon#end of sib2, iclass 26, count 0 2006.168.08:04:19.95#ibcon#*after write, iclass 26, count 0 2006.168.08:04:19.95#ibcon#*before return 0, iclass 26, count 0 2006.168.08:04:19.95#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.168.08:04:19.95#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.168.08:04:19.95#ibcon#about to clear, iclass 26 cls_cnt 0 2006.168.08:04:19.95#ibcon#cleared, iclass 26 cls_cnt 0 2006.168.08:04:19.95$vc4f8/valo=7,832.99 2006.168.08:04:19.95#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.168.08:04:19.95#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.168.08:04:19.95#ibcon#ireg 17 cls_cnt 0 2006.168.08:04:19.95#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.168.08:04:19.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.168.08:04:19.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.168.08:04:19.95#ibcon#enter wrdev, iclass 28, count 0 2006.168.08:04:19.95#ibcon#first serial, iclass 28, count 0 2006.168.08:04:19.95#ibcon#enter sib2, iclass 28, count 0 2006.168.08:04:19.95#ibcon#flushed, iclass 28, count 0 2006.168.08:04:19.95#ibcon#about to write, iclass 28, count 0 2006.168.08:04:19.95#ibcon#wrote, iclass 28, count 0 2006.168.08:04:19.95#ibcon#about to read 3, iclass 28, count 0 2006.168.08:04:19.97#ibcon#read 3, iclass 28, count 0 2006.168.08:04:19.97#ibcon#about to read 4, iclass 28, count 0 2006.168.08:04:19.97#ibcon#read 4, iclass 28, count 0 2006.168.08:04:19.97#ibcon#about to read 5, iclass 28, count 0 2006.168.08:04:19.97#ibcon#read 5, iclass 28, count 0 2006.168.08:04:19.97#ibcon#about to read 6, iclass 28, count 0 2006.168.08:04:19.97#ibcon#read 6, iclass 28, count 0 2006.168.08:04:19.97#ibcon#end of sib2, iclass 28, count 0 2006.168.08:04:19.97#ibcon#*mode == 0, iclass 28, count 0 2006.168.08:04:19.97#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.168.08:04:19.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.08:04:19.97#ibcon#*before write, iclass 28, count 0 2006.168.08:04:19.97#ibcon#enter sib2, iclass 28, count 0 2006.168.08:04:19.97#ibcon#flushed, iclass 28, count 0 2006.168.08:04:19.97#ibcon#about to write, iclass 28, count 0 2006.168.08:04:19.97#ibcon#wrote, iclass 28, count 0 2006.168.08:04:19.97#ibcon#about to read 3, iclass 28, count 0 2006.168.08:04:20.01#ibcon#read 3, iclass 28, count 0 2006.168.08:04:20.01#ibcon#about to read 4, iclass 28, count 0 2006.168.08:04:20.01#ibcon#read 4, iclass 28, count 0 2006.168.08:04:20.01#ibcon#about to read 5, iclass 28, count 0 2006.168.08:04:20.01#ibcon#read 5, iclass 28, count 0 2006.168.08:04:20.01#ibcon#about to read 6, iclass 28, count 0 2006.168.08:04:20.01#ibcon#read 6, iclass 28, count 0 2006.168.08:04:20.01#ibcon#end of sib2, iclass 28, count 0 2006.168.08:04:20.01#ibcon#*after write, iclass 28, count 0 2006.168.08:04:20.01#ibcon#*before return 0, iclass 28, count 0 2006.168.08:04:20.01#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.168.08:04:20.01#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.168.08:04:20.01#ibcon#about to clear, iclass 28 cls_cnt 0 2006.168.08:04:20.01#ibcon#cleared, iclass 28 cls_cnt 0 2006.168.08:04:20.01$vc4f8/va=7,6 2006.168.08:04:20.01#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.168.08:04:20.01#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.168.08:04:20.01#ibcon#ireg 11 cls_cnt 2 2006.168.08:04:20.01#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.168.08:04:20.07#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.168.08:04:20.07#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.168.08:04:20.07#ibcon#enter wrdev, iclass 30, count 2 2006.168.08:04:20.07#ibcon#first serial, iclass 30, count 2 2006.168.08:04:20.07#ibcon#enter sib2, iclass 30, count 2 2006.168.08:04:20.07#ibcon#flushed, iclass 30, count 2 2006.168.08:04:20.07#ibcon#about to write, iclass 30, count 2 2006.168.08:04:20.07#ibcon#wrote, iclass 30, count 2 2006.168.08:04:20.07#ibcon#about to read 3, iclass 30, count 2 2006.168.08:04:20.09#ibcon#read 3, iclass 30, count 2 2006.168.08:04:20.09#ibcon#about to read 4, iclass 30, count 2 2006.168.08:04:20.09#ibcon#read 4, iclass 30, count 2 2006.168.08:04:20.09#ibcon#about to read 5, iclass 30, count 2 2006.168.08:04:20.09#ibcon#read 5, iclass 30, count 2 2006.168.08:04:20.09#ibcon#about to read 6, iclass 30, count 2 2006.168.08:04:20.09#ibcon#read 6, iclass 30, count 2 2006.168.08:04:20.09#ibcon#end of sib2, iclass 30, count 2 2006.168.08:04:20.09#ibcon#*mode == 0, iclass 30, count 2 2006.168.08:04:20.09#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.168.08:04:20.09#ibcon#[25=AT07-06\r\n] 2006.168.08:04:20.09#ibcon#*before write, iclass 30, count 2 2006.168.08:04:20.09#ibcon#enter sib2, iclass 30, count 2 2006.168.08:04:20.09#ibcon#flushed, iclass 30, count 2 2006.168.08:04:20.09#ibcon#about to write, iclass 30, count 2 2006.168.08:04:20.09#ibcon#wrote, iclass 30, count 2 2006.168.08:04:20.09#ibcon#about to read 3, iclass 30, count 2 2006.168.08:04:20.12#ibcon#read 3, iclass 30, count 2 2006.168.08:04:20.12#ibcon#about to read 4, iclass 30, count 2 2006.168.08:04:20.12#ibcon#read 4, iclass 30, count 2 2006.168.08:04:20.12#ibcon#about to read 5, iclass 30, count 2 2006.168.08:04:20.12#ibcon#read 5, iclass 30, count 2 2006.168.08:04:20.12#ibcon#about to read 6, iclass 30, count 2 2006.168.08:04:20.12#ibcon#read 6, iclass 30, count 2 2006.168.08:04:20.12#ibcon#end of sib2, iclass 30, count 2 2006.168.08:04:20.12#ibcon#*after write, iclass 30, count 2 2006.168.08:04:20.12#ibcon#*before return 0, iclass 30, count 2 2006.168.08:04:20.12#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.168.08:04:20.12#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.168.08:04:20.12#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.168.08:04:20.12#ibcon#ireg 7 cls_cnt 0 2006.168.08:04:20.12#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.168.08:04:20.24#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.168.08:04:20.24#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.168.08:04:20.24#ibcon#enter wrdev, iclass 30, count 0 2006.168.08:04:20.24#ibcon#first serial, iclass 30, count 0 2006.168.08:04:20.24#ibcon#enter sib2, iclass 30, count 0 2006.168.08:04:20.24#ibcon#flushed, iclass 30, count 0 2006.168.08:04:20.24#ibcon#about to write, iclass 30, count 0 2006.168.08:04:20.24#ibcon#wrote, iclass 30, count 0 2006.168.08:04:20.24#ibcon#about to read 3, iclass 30, count 0 2006.168.08:04:20.26#ibcon#read 3, iclass 30, count 0 2006.168.08:04:20.26#ibcon#about to read 4, iclass 30, count 0 2006.168.08:04:20.26#ibcon#read 4, iclass 30, count 0 2006.168.08:04:20.26#ibcon#about to read 5, iclass 30, count 0 2006.168.08:04:20.26#ibcon#read 5, iclass 30, count 0 2006.168.08:04:20.26#ibcon#about to read 6, iclass 30, count 0 2006.168.08:04:20.26#ibcon#read 6, iclass 30, count 0 2006.168.08:04:20.26#ibcon#end of sib2, iclass 30, count 0 2006.168.08:04:20.26#ibcon#*mode == 0, iclass 30, count 0 2006.168.08:04:20.26#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.168.08:04:20.26#ibcon#[25=USB\r\n] 2006.168.08:04:20.26#ibcon#*before write, iclass 30, count 0 2006.168.08:04:20.26#ibcon#enter sib2, iclass 30, count 0 2006.168.08:04:20.26#ibcon#flushed, iclass 30, count 0 2006.168.08:04:20.26#ibcon#about to write, iclass 30, count 0 2006.168.08:04:20.26#ibcon#wrote, iclass 30, count 0 2006.168.08:04:20.26#ibcon#about to read 3, iclass 30, count 0 2006.168.08:04:20.29#ibcon#read 3, iclass 30, count 0 2006.168.08:04:20.29#ibcon#about to read 4, iclass 30, count 0 2006.168.08:04:20.29#ibcon#read 4, iclass 30, count 0 2006.168.08:04:20.29#ibcon#about to read 5, iclass 30, count 0 2006.168.08:04:20.29#ibcon#read 5, iclass 30, count 0 2006.168.08:04:20.29#ibcon#about to read 6, iclass 30, count 0 2006.168.08:04:20.29#ibcon#read 6, iclass 30, count 0 2006.168.08:04:20.29#ibcon#end of sib2, iclass 30, count 0 2006.168.08:04:20.29#ibcon#*after write, iclass 30, count 0 2006.168.08:04:20.29#ibcon#*before return 0, iclass 30, count 0 2006.168.08:04:20.29#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.168.08:04:20.29#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.168.08:04:20.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.168.08:04:20.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.168.08:04:20.29$vc4f8/valo=8,852.99 2006.168.08:04:20.29#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.168.08:04:20.29#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.168.08:04:20.29#ibcon#ireg 17 cls_cnt 0 2006.168.08:04:20.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:04:20.29#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:04:20.29#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:04:20.29#ibcon#enter wrdev, iclass 32, count 0 2006.168.08:04:20.29#ibcon#first serial, iclass 32, count 0 2006.168.08:04:20.29#ibcon#enter sib2, iclass 32, count 0 2006.168.08:04:20.29#ibcon#flushed, iclass 32, count 0 2006.168.08:04:20.29#ibcon#about to write, iclass 32, count 0 2006.168.08:04:20.29#ibcon#wrote, iclass 32, count 0 2006.168.08:04:20.29#ibcon#about to read 3, iclass 32, count 0 2006.168.08:04:20.31#ibcon#read 3, iclass 32, count 0 2006.168.08:04:20.31#ibcon#about to read 4, iclass 32, count 0 2006.168.08:04:20.31#ibcon#read 4, iclass 32, count 0 2006.168.08:04:20.31#ibcon#about to read 5, iclass 32, count 0 2006.168.08:04:20.31#ibcon#read 5, iclass 32, count 0 2006.168.08:04:20.31#ibcon#about to read 6, iclass 32, count 0 2006.168.08:04:20.31#ibcon#read 6, iclass 32, count 0 2006.168.08:04:20.31#ibcon#end of sib2, iclass 32, count 0 2006.168.08:04:20.31#ibcon#*mode == 0, iclass 32, count 0 2006.168.08:04:20.31#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.168.08:04:20.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.08:04:20.31#ibcon#*before write, iclass 32, count 0 2006.168.08:04:20.31#ibcon#enter sib2, iclass 32, count 0 2006.168.08:04:20.31#ibcon#flushed, iclass 32, count 0 2006.168.08:04:20.31#ibcon#about to write, iclass 32, count 0 2006.168.08:04:20.31#ibcon#wrote, iclass 32, count 0 2006.168.08:04:20.31#ibcon#about to read 3, iclass 32, count 0 2006.168.08:04:20.35#ibcon#read 3, iclass 32, count 0 2006.168.08:04:20.35#ibcon#about to read 4, iclass 32, count 0 2006.168.08:04:20.35#ibcon#read 4, iclass 32, count 0 2006.168.08:04:20.35#ibcon#about to read 5, iclass 32, count 0 2006.168.08:04:20.35#ibcon#read 5, iclass 32, count 0 2006.168.08:04:20.35#ibcon#about to read 6, iclass 32, count 0 2006.168.08:04:20.35#ibcon#read 6, iclass 32, count 0 2006.168.08:04:20.35#ibcon#end of sib2, iclass 32, count 0 2006.168.08:04:20.35#ibcon#*after write, iclass 32, count 0 2006.168.08:04:20.35#ibcon#*before return 0, iclass 32, count 0 2006.168.08:04:20.35#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:04:20.35#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:04:20.35#ibcon#about to clear, iclass 32 cls_cnt 0 2006.168.08:04:20.35#ibcon#cleared, iclass 32 cls_cnt 0 2006.168.08:04:20.35$vc4f8/va=8,7 2006.168.08:04:20.35#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.168.08:04:20.35#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.168.08:04:20.35#ibcon#ireg 11 cls_cnt 2 2006.168.08:04:20.35#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.168.08:04:20.41#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.168.08:04:20.41#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.168.08:04:20.41#ibcon#enter wrdev, iclass 34, count 2 2006.168.08:04:20.41#ibcon#first serial, iclass 34, count 2 2006.168.08:04:20.41#ibcon#enter sib2, iclass 34, count 2 2006.168.08:04:20.41#ibcon#flushed, iclass 34, count 2 2006.168.08:04:20.41#ibcon#about to write, iclass 34, count 2 2006.168.08:04:20.41#ibcon#wrote, iclass 34, count 2 2006.168.08:04:20.41#ibcon#about to read 3, iclass 34, count 2 2006.168.08:04:20.43#ibcon#read 3, iclass 34, count 2 2006.168.08:04:20.43#ibcon#about to read 4, iclass 34, count 2 2006.168.08:04:20.43#ibcon#read 4, iclass 34, count 2 2006.168.08:04:20.43#ibcon#about to read 5, iclass 34, count 2 2006.168.08:04:20.43#ibcon#read 5, iclass 34, count 2 2006.168.08:04:20.43#ibcon#about to read 6, iclass 34, count 2 2006.168.08:04:20.43#ibcon#read 6, iclass 34, count 2 2006.168.08:04:20.43#ibcon#end of sib2, iclass 34, count 2 2006.168.08:04:20.43#ibcon#*mode == 0, iclass 34, count 2 2006.168.08:04:20.43#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.168.08:04:20.43#ibcon#[25=AT08-07\r\n] 2006.168.08:04:20.43#ibcon#*before write, iclass 34, count 2 2006.168.08:04:20.43#ibcon#enter sib2, iclass 34, count 2 2006.168.08:04:20.43#ibcon#flushed, iclass 34, count 2 2006.168.08:04:20.43#ibcon#about to write, iclass 34, count 2 2006.168.08:04:20.43#ibcon#wrote, iclass 34, count 2 2006.168.08:04:20.43#ibcon#about to read 3, iclass 34, count 2 2006.168.08:04:20.46#ibcon#read 3, iclass 34, count 2 2006.168.08:04:20.46#ibcon#about to read 4, iclass 34, count 2 2006.168.08:04:20.46#ibcon#read 4, iclass 34, count 2 2006.168.08:04:20.46#ibcon#about to read 5, iclass 34, count 2 2006.168.08:04:20.46#ibcon#read 5, iclass 34, count 2 2006.168.08:04:20.46#ibcon#about to read 6, iclass 34, count 2 2006.168.08:04:20.46#ibcon#read 6, iclass 34, count 2 2006.168.08:04:20.46#ibcon#end of sib2, iclass 34, count 2 2006.168.08:04:20.46#ibcon#*after write, iclass 34, count 2 2006.168.08:04:20.46#ibcon#*before return 0, iclass 34, count 2 2006.168.08:04:20.46#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.168.08:04:20.46#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.168.08:04:20.46#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.168.08:04:20.46#ibcon#ireg 7 cls_cnt 0 2006.168.08:04:20.46#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.168.08:04:20.58#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.168.08:04:20.58#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.168.08:04:20.58#ibcon#enter wrdev, iclass 34, count 0 2006.168.08:04:20.58#ibcon#first serial, iclass 34, count 0 2006.168.08:04:20.58#ibcon#enter sib2, iclass 34, count 0 2006.168.08:04:20.58#ibcon#flushed, iclass 34, count 0 2006.168.08:04:20.58#ibcon#about to write, iclass 34, count 0 2006.168.08:04:20.58#ibcon#wrote, iclass 34, count 0 2006.168.08:04:20.58#ibcon#about to read 3, iclass 34, count 0 2006.168.08:04:20.60#ibcon#read 3, iclass 34, count 0 2006.168.08:04:20.60#ibcon#about to read 4, iclass 34, count 0 2006.168.08:04:20.60#ibcon#read 4, iclass 34, count 0 2006.168.08:04:20.60#ibcon#about to read 5, iclass 34, count 0 2006.168.08:04:20.60#ibcon#read 5, iclass 34, count 0 2006.168.08:04:20.60#ibcon#about to read 6, iclass 34, count 0 2006.168.08:04:20.60#ibcon#read 6, iclass 34, count 0 2006.168.08:04:20.60#ibcon#end of sib2, iclass 34, count 0 2006.168.08:04:20.60#ibcon#*mode == 0, iclass 34, count 0 2006.168.08:04:20.60#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.168.08:04:20.60#ibcon#[25=USB\r\n] 2006.168.08:04:20.60#ibcon#*before write, iclass 34, count 0 2006.168.08:04:20.60#ibcon#enter sib2, iclass 34, count 0 2006.168.08:04:20.60#ibcon#flushed, iclass 34, count 0 2006.168.08:04:20.60#ibcon#about to write, iclass 34, count 0 2006.168.08:04:20.60#ibcon#wrote, iclass 34, count 0 2006.168.08:04:20.60#ibcon#about to read 3, iclass 34, count 0 2006.168.08:04:20.63#ibcon#read 3, iclass 34, count 0 2006.168.08:04:20.63#ibcon#about to read 4, iclass 34, count 0 2006.168.08:04:20.63#ibcon#read 4, iclass 34, count 0 2006.168.08:04:20.63#ibcon#about to read 5, iclass 34, count 0 2006.168.08:04:20.63#ibcon#read 5, iclass 34, count 0 2006.168.08:04:20.63#ibcon#about to read 6, iclass 34, count 0 2006.168.08:04:20.63#ibcon#read 6, iclass 34, count 0 2006.168.08:04:20.63#ibcon#end of sib2, iclass 34, count 0 2006.168.08:04:20.63#ibcon#*after write, iclass 34, count 0 2006.168.08:04:20.63#ibcon#*before return 0, iclass 34, count 0 2006.168.08:04:20.63#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.168.08:04:20.63#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.168.08:04:20.63#ibcon#about to clear, iclass 34 cls_cnt 0 2006.168.08:04:20.63#ibcon#cleared, iclass 34 cls_cnt 0 2006.168.08:04:20.63$vc4f8/vblo=1,632.99 2006.168.08:04:20.63#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.168.08:04:20.63#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.168.08:04:20.63#ibcon#ireg 17 cls_cnt 0 2006.168.08:04:20.63#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.168.08:04:20.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.168.08:04:20.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.168.08:04:20.63#ibcon#enter wrdev, iclass 36, count 0 2006.168.08:04:20.63#ibcon#first serial, iclass 36, count 0 2006.168.08:04:20.63#ibcon#enter sib2, iclass 36, count 0 2006.168.08:04:20.63#ibcon#flushed, iclass 36, count 0 2006.168.08:04:20.63#ibcon#about to write, iclass 36, count 0 2006.168.08:04:20.63#ibcon#wrote, iclass 36, count 0 2006.168.08:04:20.63#ibcon#about to read 3, iclass 36, count 0 2006.168.08:04:20.65#ibcon#read 3, iclass 36, count 0 2006.168.08:04:20.65#ibcon#about to read 4, iclass 36, count 0 2006.168.08:04:20.65#ibcon#read 4, iclass 36, count 0 2006.168.08:04:20.65#ibcon#about to read 5, iclass 36, count 0 2006.168.08:04:20.65#ibcon#read 5, iclass 36, count 0 2006.168.08:04:20.65#ibcon#about to read 6, iclass 36, count 0 2006.168.08:04:20.65#ibcon#read 6, iclass 36, count 0 2006.168.08:04:20.65#ibcon#end of sib2, iclass 36, count 0 2006.168.08:04:20.65#ibcon#*mode == 0, iclass 36, count 0 2006.168.08:04:20.65#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.168.08:04:20.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.08:04:20.65#ibcon#*before write, iclass 36, count 0 2006.168.08:04:20.65#ibcon#enter sib2, iclass 36, count 0 2006.168.08:04:20.65#ibcon#flushed, iclass 36, count 0 2006.168.08:04:20.65#ibcon#about to write, iclass 36, count 0 2006.168.08:04:20.65#ibcon#wrote, iclass 36, count 0 2006.168.08:04:20.65#ibcon#about to read 3, iclass 36, count 0 2006.168.08:04:20.69#ibcon#read 3, iclass 36, count 0 2006.168.08:04:20.69#ibcon#about to read 4, iclass 36, count 0 2006.168.08:04:20.69#ibcon#read 4, iclass 36, count 0 2006.168.08:04:20.69#ibcon#about to read 5, iclass 36, count 0 2006.168.08:04:20.69#ibcon#read 5, iclass 36, count 0 2006.168.08:04:20.69#ibcon#about to read 6, iclass 36, count 0 2006.168.08:04:20.69#ibcon#read 6, iclass 36, count 0 2006.168.08:04:20.69#ibcon#end of sib2, iclass 36, count 0 2006.168.08:04:20.69#ibcon#*after write, iclass 36, count 0 2006.168.08:04:20.69#ibcon#*before return 0, iclass 36, count 0 2006.168.08:04:20.69#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.168.08:04:20.69#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.168.08:04:20.69#ibcon#about to clear, iclass 36 cls_cnt 0 2006.168.08:04:20.69#ibcon#cleared, iclass 36 cls_cnt 0 2006.168.08:04:20.69$vc4f8/vb=1,4 2006.168.08:04:20.69#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.168.08:04:20.69#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.168.08:04:20.69#ibcon#ireg 11 cls_cnt 2 2006.168.08:04:20.69#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.168.08:04:20.69#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.168.08:04:20.69#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.168.08:04:20.69#ibcon#enter wrdev, iclass 38, count 2 2006.168.08:04:20.69#ibcon#first serial, iclass 38, count 2 2006.168.08:04:20.69#ibcon#enter sib2, iclass 38, count 2 2006.168.08:04:20.69#ibcon#flushed, iclass 38, count 2 2006.168.08:04:20.69#ibcon#about to write, iclass 38, count 2 2006.168.08:04:20.69#ibcon#wrote, iclass 38, count 2 2006.168.08:04:20.69#ibcon#about to read 3, iclass 38, count 2 2006.168.08:04:20.71#ibcon#read 3, iclass 38, count 2 2006.168.08:04:20.71#ibcon#about to read 4, iclass 38, count 2 2006.168.08:04:20.71#ibcon#read 4, iclass 38, count 2 2006.168.08:04:20.71#ibcon#about to read 5, iclass 38, count 2 2006.168.08:04:20.71#ibcon#read 5, iclass 38, count 2 2006.168.08:04:20.71#ibcon#about to read 6, iclass 38, count 2 2006.168.08:04:20.71#ibcon#read 6, iclass 38, count 2 2006.168.08:04:20.71#ibcon#end of sib2, iclass 38, count 2 2006.168.08:04:20.71#ibcon#*mode == 0, iclass 38, count 2 2006.168.08:04:20.71#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.168.08:04:20.71#ibcon#[27=AT01-04\r\n] 2006.168.08:04:20.71#ibcon#*before write, iclass 38, count 2 2006.168.08:04:20.71#ibcon#enter sib2, iclass 38, count 2 2006.168.08:04:20.71#ibcon#flushed, iclass 38, count 2 2006.168.08:04:20.71#ibcon#about to write, iclass 38, count 2 2006.168.08:04:20.71#ibcon#wrote, iclass 38, count 2 2006.168.08:04:20.71#ibcon#about to read 3, iclass 38, count 2 2006.168.08:04:20.74#ibcon#read 3, iclass 38, count 2 2006.168.08:04:20.74#ibcon#about to read 4, iclass 38, count 2 2006.168.08:04:20.74#ibcon#read 4, iclass 38, count 2 2006.168.08:04:20.74#ibcon#about to read 5, iclass 38, count 2 2006.168.08:04:20.74#ibcon#read 5, iclass 38, count 2 2006.168.08:04:20.74#ibcon#about to read 6, iclass 38, count 2 2006.168.08:04:20.74#ibcon#read 6, iclass 38, count 2 2006.168.08:04:20.74#ibcon#end of sib2, iclass 38, count 2 2006.168.08:04:20.74#ibcon#*after write, iclass 38, count 2 2006.168.08:04:20.74#ibcon#*before return 0, iclass 38, count 2 2006.168.08:04:20.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.168.08:04:20.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.168.08:04:20.74#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.168.08:04:20.74#ibcon#ireg 7 cls_cnt 0 2006.168.08:04:20.74#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.168.08:04:20.86#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.168.08:04:20.86#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.168.08:04:20.86#ibcon#enter wrdev, iclass 38, count 0 2006.168.08:04:20.86#ibcon#first serial, iclass 38, count 0 2006.168.08:04:20.86#ibcon#enter sib2, iclass 38, count 0 2006.168.08:04:20.86#ibcon#flushed, iclass 38, count 0 2006.168.08:04:20.86#ibcon#about to write, iclass 38, count 0 2006.168.08:04:20.86#ibcon#wrote, iclass 38, count 0 2006.168.08:04:20.86#ibcon#about to read 3, iclass 38, count 0 2006.168.08:04:20.88#ibcon#read 3, iclass 38, count 0 2006.168.08:04:20.88#ibcon#about to read 4, iclass 38, count 0 2006.168.08:04:20.88#ibcon#read 4, iclass 38, count 0 2006.168.08:04:20.88#ibcon#about to read 5, iclass 38, count 0 2006.168.08:04:20.88#ibcon#read 5, iclass 38, count 0 2006.168.08:04:20.88#ibcon#about to read 6, iclass 38, count 0 2006.168.08:04:20.88#ibcon#read 6, iclass 38, count 0 2006.168.08:04:20.88#ibcon#end of sib2, iclass 38, count 0 2006.168.08:04:20.88#ibcon#*mode == 0, iclass 38, count 0 2006.168.08:04:20.88#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.168.08:04:20.88#ibcon#[27=USB\r\n] 2006.168.08:04:20.88#ibcon#*before write, iclass 38, count 0 2006.168.08:04:20.88#ibcon#enter sib2, iclass 38, count 0 2006.168.08:04:20.88#ibcon#flushed, iclass 38, count 0 2006.168.08:04:20.88#ibcon#about to write, iclass 38, count 0 2006.168.08:04:20.88#ibcon#wrote, iclass 38, count 0 2006.168.08:04:20.88#ibcon#about to read 3, iclass 38, count 0 2006.168.08:04:20.91#ibcon#read 3, iclass 38, count 0 2006.168.08:04:20.91#ibcon#about to read 4, iclass 38, count 0 2006.168.08:04:20.91#ibcon#read 4, iclass 38, count 0 2006.168.08:04:20.91#ibcon#about to read 5, iclass 38, count 0 2006.168.08:04:20.91#ibcon#read 5, iclass 38, count 0 2006.168.08:04:20.91#ibcon#about to read 6, iclass 38, count 0 2006.168.08:04:20.91#ibcon#read 6, iclass 38, count 0 2006.168.08:04:20.91#ibcon#end of sib2, iclass 38, count 0 2006.168.08:04:20.91#ibcon#*after write, iclass 38, count 0 2006.168.08:04:20.91#ibcon#*before return 0, iclass 38, count 0 2006.168.08:04:20.91#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.168.08:04:20.91#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.168.08:04:20.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.168.08:04:20.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.168.08:04:20.91$vc4f8/vblo=2,640.99 2006.168.08:04:20.91#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.168.08:04:20.91#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.168.08:04:20.91#ibcon#ireg 17 cls_cnt 0 2006.168.08:04:20.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:04:20.91#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:04:20.91#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:04:20.91#ibcon#enter wrdev, iclass 40, count 0 2006.168.08:04:20.91#ibcon#first serial, iclass 40, count 0 2006.168.08:04:20.91#ibcon#enter sib2, iclass 40, count 0 2006.168.08:04:20.91#ibcon#flushed, iclass 40, count 0 2006.168.08:04:20.91#ibcon#about to write, iclass 40, count 0 2006.168.08:04:20.91#ibcon#wrote, iclass 40, count 0 2006.168.08:04:20.91#ibcon#about to read 3, iclass 40, count 0 2006.168.08:04:20.93#ibcon#read 3, iclass 40, count 0 2006.168.08:04:20.93#ibcon#about to read 4, iclass 40, count 0 2006.168.08:04:20.93#ibcon#read 4, iclass 40, count 0 2006.168.08:04:20.93#ibcon#about to read 5, iclass 40, count 0 2006.168.08:04:20.93#ibcon#read 5, iclass 40, count 0 2006.168.08:04:20.93#ibcon#about to read 6, iclass 40, count 0 2006.168.08:04:20.93#ibcon#read 6, iclass 40, count 0 2006.168.08:04:20.93#ibcon#end of sib2, iclass 40, count 0 2006.168.08:04:20.93#ibcon#*mode == 0, iclass 40, count 0 2006.168.08:04:20.93#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.168.08:04:20.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.08:04:20.93#ibcon#*before write, iclass 40, count 0 2006.168.08:04:20.93#ibcon#enter sib2, iclass 40, count 0 2006.168.08:04:20.93#ibcon#flushed, iclass 40, count 0 2006.168.08:04:20.93#ibcon#about to write, iclass 40, count 0 2006.168.08:04:20.93#ibcon#wrote, iclass 40, count 0 2006.168.08:04:20.93#ibcon#about to read 3, iclass 40, count 0 2006.168.08:04:20.97#ibcon#read 3, iclass 40, count 0 2006.168.08:04:20.97#ibcon#about to read 4, iclass 40, count 0 2006.168.08:04:20.97#ibcon#read 4, iclass 40, count 0 2006.168.08:04:20.97#ibcon#about to read 5, iclass 40, count 0 2006.168.08:04:20.97#ibcon#read 5, iclass 40, count 0 2006.168.08:04:20.97#ibcon#about to read 6, iclass 40, count 0 2006.168.08:04:20.97#ibcon#read 6, iclass 40, count 0 2006.168.08:04:20.97#ibcon#end of sib2, iclass 40, count 0 2006.168.08:04:20.97#ibcon#*after write, iclass 40, count 0 2006.168.08:04:20.97#ibcon#*before return 0, iclass 40, count 0 2006.168.08:04:20.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:04:20.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:04:20.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.168.08:04:20.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.168.08:04:20.97$vc4f8/vb=2,4 2006.168.08:04:20.97#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.168.08:04:20.97#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.168.08:04:20.97#ibcon#ireg 11 cls_cnt 2 2006.168.08:04:20.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.168.08:04:21.03#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.168.08:04:21.03#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.168.08:04:21.03#ibcon#enter wrdev, iclass 4, count 2 2006.168.08:04:21.03#ibcon#first serial, iclass 4, count 2 2006.168.08:04:21.03#ibcon#enter sib2, iclass 4, count 2 2006.168.08:04:21.03#ibcon#flushed, iclass 4, count 2 2006.168.08:04:21.03#ibcon#about to write, iclass 4, count 2 2006.168.08:04:21.03#ibcon#wrote, iclass 4, count 2 2006.168.08:04:21.03#ibcon#about to read 3, iclass 4, count 2 2006.168.08:04:21.05#ibcon#read 3, iclass 4, count 2 2006.168.08:04:21.05#ibcon#about to read 4, iclass 4, count 2 2006.168.08:04:21.05#ibcon#read 4, iclass 4, count 2 2006.168.08:04:21.05#ibcon#about to read 5, iclass 4, count 2 2006.168.08:04:21.05#ibcon#read 5, iclass 4, count 2 2006.168.08:04:21.05#ibcon#about to read 6, iclass 4, count 2 2006.168.08:04:21.05#ibcon#read 6, iclass 4, count 2 2006.168.08:04:21.05#ibcon#end of sib2, iclass 4, count 2 2006.168.08:04:21.05#ibcon#*mode == 0, iclass 4, count 2 2006.168.08:04:21.05#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.168.08:04:21.05#ibcon#[27=AT02-04\r\n] 2006.168.08:04:21.05#ibcon#*before write, iclass 4, count 2 2006.168.08:04:21.05#ibcon#enter sib2, iclass 4, count 2 2006.168.08:04:21.05#ibcon#flushed, iclass 4, count 2 2006.168.08:04:21.05#ibcon#about to write, iclass 4, count 2 2006.168.08:04:21.05#ibcon#wrote, iclass 4, count 2 2006.168.08:04:21.05#ibcon#about to read 3, iclass 4, count 2 2006.168.08:04:21.08#ibcon#read 3, iclass 4, count 2 2006.168.08:04:21.08#ibcon#about to read 4, iclass 4, count 2 2006.168.08:04:21.08#ibcon#read 4, iclass 4, count 2 2006.168.08:04:21.08#ibcon#about to read 5, iclass 4, count 2 2006.168.08:04:21.08#ibcon#read 5, iclass 4, count 2 2006.168.08:04:21.08#ibcon#about to read 6, iclass 4, count 2 2006.168.08:04:21.08#ibcon#read 6, iclass 4, count 2 2006.168.08:04:21.08#ibcon#end of sib2, iclass 4, count 2 2006.168.08:04:21.08#ibcon#*after write, iclass 4, count 2 2006.168.08:04:21.08#ibcon#*before return 0, iclass 4, count 2 2006.168.08:04:21.08#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.168.08:04:21.08#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.168.08:04:21.08#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.168.08:04:21.08#ibcon#ireg 7 cls_cnt 0 2006.168.08:04:21.08#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.168.08:04:21.20#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.168.08:04:21.20#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.168.08:04:21.20#ibcon#enter wrdev, iclass 4, count 0 2006.168.08:04:21.20#ibcon#first serial, iclass 4, count 0 2006.168.08:04:21.20#ibcon#enter sib2, iclass 4, count 0 2006.168.08:04:21.20#ibcon#flushed, iclass 4, count 0 2006.168.08:04:21.20#ibcon#about to write, iclass 4, count 0 2006.168.08:04:21.20#ibcon#wrote, iclass 4, count 0 2006.168.08:04:21.20#ibcon#about to read 3, iclass 4, count 0 2006.168.08:04:21.22#ibcon#read 3, iclass 4, count 0 2006.168.08:04:21.22#ibcon#about to read 4, iclass 4, count 0 2006.168.08:04:21.22#ibcon#read 4, iclass 4, count 0 2006.168.08:04:21.22#ibcon#about to read 5, iclass 4, count 0 2006.168.08:04:21.22#ibcon#read 5, iclass 4, count 0 2006.168.08:04:21.22#ibcon#about to read 6, iclass 4, count 0 2006.168.08:04:21.22#ibcon#read 6, iclass 4, count 0 2006.168.08:04:21.22#ibcon#end of sib2, iclass 4, count 0 2006.168.08:04:21.22#ibcon#*mode == 0, iclass 4, count 0 2006.168.08:04:21.22#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.168.08:04:21.22#ibcon#[27=USB\r\n] 2006.168.08:04:21.22#ibcon#*before write, iclass 4, count 0 2006.168.08:04:21.22#ibcon#enter sib2, iclass 4, count 0 2006.168.08:04:21.22#ibcon#flushed, iclass 4, count 0 2006.168.08:04:21.22#ibcon#about to write, iclass 4, count 0 2006.168.08:04:21.22#ibcon#wrote, iclass 4, count 0 2006.168.08:04:21.22#ibcon#about to read 3, iclass 4, count 0 2006.168.08:04:21.25#ibcon#read 3, iclass 4, count 0 2006.168.08:04:21.25#ibcon#about to read 4, iclass 4, count 0 2006.168.08:04:21.25#ibcon#read 4, iclass 4, count 0 2006.168.08:04:21.25#ibcon#about to read 5, iclass 4, count 0 2006.168.08:04:21.25#ibcon#read 5, iclass 4, count 0 2006.168.08:04:21.25#ibcon#about to read 6, iclass 4, count 0 2006.168.08:04:21.25#ibcon#read 6, iclass 4, count 0 2006.168.08:04:21.25#ibcon#end of sib2, iclass 4, count 0 2006.168.08:04:21.25#ibcon#*after write, iclass 4, count 0 2006.168.08:04:21.25#ibcon#*before return 0, iclass 4, count 0 2006.168.08:04:21.25#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.168.08:04:21.25#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.168.08:04:21.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.168.08:04:21.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.168.08:04:21.25$vc4f8/vblo=3,656.99 2006.168.08:04:21.25#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.168.08:04:21.25#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.168.08:04:21.25#ibcon#ireg 17 cls_cnt 0 2006.168.08:04:21.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.168.08:04:21.25#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.168.08:04:21.25#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.168.08:04:21.25#ibcon#enter wrdev, iclass 6, count 0 2006.168.08:04:21.25#ibcon#first serial, iclass 6, count 0 2006.168.08:04:21.25#ibcon#enter sib2, iclass 6, count 0 2006.168.08:04:21.25#ibcon#flushed, iclass 6, count 0 2006.168.08:04:21.25#ibcon#about to write, iclass 6, count 0 2006.168.08:04:21.25#ibcon#wrote, iclass 6, count 0 2006.168.08:04:21.25#ibcon#about to read 3, iclass 6, count 0 2006.168.08:04:21.27#ibcon#read 3, iclass 6, count 0 2006.168.08:04:21.27#ibcon#about to read 4, iclass 6, count 0 2006.168.08:04:21.27#ibcon#read 4, iclass 6, count 0 2006.168.08:04:21.27#ibcon#about to read 5, iclass 6, count 0 2006.168.08:04:21.27#ibcon#read 5, iclass 6, count 0 2006.168.08:04:21.27#ibcon#about to read 6, iclass 6, count 0 2006.168.08:04:21.27#ibcon#read 6, iclass 6, count 0 2006.168.08:04:21.27#ibcon#end of sib2, iclass 6, count 0 2006.168.08:04:21.27#ibcon#*mode == 0, iclass 6, count 0 2006.168.08:04:21.27#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.168.08:04:21.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.08:04:21.27#ibcon#*before write, iclass 6, count 0 2006.168.08:04:21.27#ibcon#enter sib2, iclass 6, count 0 2006.168.08:04:21.27#ibcon#flushed, iclass 6, count 0 2006.168.08:04:21.27#ibcon#about to write, iclass 6, count 0 2006.168.08:04:21.27#ibcon#wrote, iclass 6, count 0 2006.168.08:04:21.27#ibcon#about to read 3, iclass 6, count 0 2006.168.08:04:21.31#ibcon#read 3, iclass 6, count 0 2006.168.08:04:21.31#ibcon#about to read 4, iclass 6, count 0 2006.168.08:04:21.31#ibcon#read 4, iclass 6, count 0 2006.168.08:04:21.31#ibcon#about to read 5, iclass 6, count 0 2006.168.08:04:21.31#ibcon#read 5, iclass 6, count 0 2006.168.08:04:21.31#ibcon#about to read 6, iclass 6, count 0 2006.168.08:04:21.31#ibcon#read 6, iclass 6, count 0 2006.168.08:04:21.31#ibcon#end of sib2, iclass 6, count 0 2006.168.08:04:21.31#ibcon#*after write, iclass 6, count 0 2006.168.08:04:21.31#ibcon#*before return 0, iclass 6, count 0 2006.168.08:04:21.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.168.08:04:21.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.168.08:04:21.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.168.08:04:21.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.168.08:04:21.31$vc4f8/vb=3,4 2006.168.08:04:21.31#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.168.08:04:21.31#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.168.08:04:21.31#ibcon#ireg 11 cls_cnt 2 2006.168.08:04:21.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.168.08:04:21.37#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.168.08:04:21.37#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.168.08:04:21.37#ibcon#enter wrdev, iclass 10, count 2 2006.168.08:04:21.37#ibcon#first serial, iclass 10, count 2 2006.168.08:04:21.37#ibcon#enter sib2, iclass 10, count 2 2006.168.08:04:21.37#ibcon#flushed, iclass 10, count 2 2006.168.08:04:21.37#ibcon#about to write, iclass 10, count 2 2006.168.08:04:21.37#ibcon#wrote, iclass 10, count 2 2006.168.08:04:21.37#ibcon#about to read 3, iclass 10, count 2 2006.168.08:04:21.39#ibcon#read 3, iclass 10, count 2 2006.168.08:04:21.39#ibcon#about to read 4, iclass 10, count 2 2006.168.08:04:21.39#ibcon#read 4, iclass 10, count 2 2006.168.08:04:21.39#ibcon#about to read 5, iclass 10, count 2 2006.168.08:04:21.39#ibcon#read 5, iclass 10, count 2 2006.168.08:04:21.39#ibcon#about to read 6, iclass 10, count 2 2006.168.08:04:21.39#ibcon#read 6, iclass 10, count 2 2006.168.08:04:21.39#ibcon#end of sib2, iclass 10, count 2 2006.168.08:04:21.39#ibcon#*mode == 0, iclass 10, count 2 2006.168.08:04:21.39#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.168.08:04:21.39#ibcon#[27=AT03-04\r\n] 2006.168.08:04:21.39#ibcon#*before write, iclass 10, count 2 2006.168.08:04:21.39#ibcon#enter sib2, iclass 10, count 2 2006.168.08:04:21.39#ibcon#flushed, iclass 10, count 2 2006.168.08:04:21.39#ibcon#about to write, iclass 10, count 2 2006.168.08:04:21.39#ibcon#wrote, iclass 10, count 2 2006.168.08:04:21.39#ibcon#about to read 3, iclass 10, count 2 2006.168.08:04:21.42#ibcon#read 3, iclass 10, count 2 2006.168.08:04:21.42#ibcon#about to read 4, iclass 10, count 2 2006.168.08:04:21.42#ibcon#read 4, iclass 10, count 2 2006.168.08:04:21.42#ibcon#about to read 5, iclass 10, count 2 2006.168.08:04:21.42#ibcon#read 5, iclass 10, count 2 2006.168.08:04:21.42#ibcon#about to read 6, iclass 10, count 2 2006.168.08:04:21.42#ibcon#read 6, iclass 10, count 2 2006.168.08:04:21.42#ibcon#end of sib2, iclass 10, count 2 2006.168.08:04:21.42#ibcon#*after write, iclass 10, count 2 2006.168.08:04:21.42#ibcon#*before return 0, iclass 10, count 2 2006.168.08:04:21.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.168.08:04:21.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.168.08:04:21.42#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.168.08:04:21.42#ibcon#ireg 7 cls_cnt 0 2006.168.08:04:21.42#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.168.08:04:21.54#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.168.08:04:21.54#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.168.08:04:21.54#ibcon#enter wrdev, iclass 10, count 0 2006.168.08:04:21.54#ibcon#first serial, iclass 10, count 0 2006.168.08:04:21.54#ibcon#enter sib2, iclass 10, count 0 2006.168.08:04:21.54#ibcon#flushed, iclass 10, count 0 2006.168.08:04:21.54#ibcon#about to write, iclass 10, count 0 2006.168.08:04:21.54#ibcon#wrote, iclass 10, count 0 2006.168.08:04:21.54#ibcon#about to read 3, iclass 10, count 0 2006.168.08:04:21.56#ibcon#read 3, iclass 10, count 0 2006.168.08:04:21.56#ibcon#about to read 4, iclass 10, count 0 2006.168.08:04:21.56#ibcon#read 4, iclass 10, count 0 2006.168.08:04:21.56#ibcon#about to read 5, iclass 10, count 0 2006.168.08:04:21.56#ibcon#read 5, iclass 10, count 0 2006.168.08:04:21.56#ibcon#about to read 6, iclass 10, count 0 2006.168.08:04:21.56#ibcon#read 6, iclass 10, count 0 2006.168.08:04:21.56#ibcon#end of sib2, iclass 10, count 0 2006.168.08:04:21.56#ibcon#*mode == 0, iclass 10, count 0 2006.168.08:04:21.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.168.08:04:21.56#ibcon#[27=USB\r\n] 2006.168.08:04:21.56#ibcon#*before write, iclass 10, count 0 2006.168.08:04:21.56#ibcon#enter sib2, iclass 10, count 0 2006.168.08:04:21.56#ibcon#flushed, iclass 10, count 0 2006.168.08:04:21.56#ibcon#about to write, iclass 10, count 0 2006.168.08:04:21.56#ibcon#wrote, iclass 10, count 0 2006.168.08:04:21.56#ibcon#about to read 3, iclass 10, count 0 2006.168.08:04:21.59#ibcon#read 3, iclass 10, count 0 2006.168.08:04:21.59#ibcon#about to read 4, iclass 10, count 0 2006.168.08:04:21.59#ibcon#read 4, iclass 10, count 0 2006.168.08:04:21.59#ibcon#about to read 5, iclass 10, count 0 2006.168.08:04:21.59#ibcon#read 5, iclass 10, count 0 2006.168.08:04:21.59#ibcon#about to read 6, iclass 10, count 0 2006.168.08:04:21.59#ibcon#read 6, iclass 10, count 0 2006.168.08:04:21.59#ibcon#end of sib2, iclass 10, count 0 2006.168.08:04:21.59#ibcon#*after write, iclass 10, count 0 2006.168.08:04:21.59#ibcon#*before return 0, iclass 10, count 0 2006.168.08:04:21.59#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.168.08:04:21.59#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.168.08:04:21.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.168.08:04:21.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.168.08:04:21.59$vc4f8/vblo=4,712.99 2006.168.08:04:21.59#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.168.08:04:21.59#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.168.08:04:21.59#ibcon#ireg 17 cls_cnt 0 2006.168.08:04:21.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.168.08:04:21.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.168.08:04:21.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.168.08:04:21.59#ibcon#enter wrdev, iclass 12, count 0 2006.168.08:04:21.59#ibcon#first serial, iclass 12, count 0 2006.168.08:04:21.59#ibcon#enter sib2, iclass 12, count 0 2006.168.08:04:21.59#ibcon#flushed, iclass 12, count 0 2006.168.08:04:21.59#ibcon#about to write, iclass 12, count 0 2006.168.08:04:21.59#ibcon#wrote, iclass 12, count 0 2006.168.08:04:21.59#ibcon#about to read 3, iclass 12, count 0 2006.168.08:04:21.61#ibcon#read 3, iclass 12, count 0 2006.168.08:04:21.61#ibcon#about to read 4, iclass 12, count 0 2006.168.08:04:21.61#ibcon#read 4, iclass 12, count 0 2006.168.08:04:21.61#ibcon#about to read 5, iclass 12, count 0 2006.168.08:04:21.61#ibcon#read 5, iclass 12, count 0 2006.168.08:04:21.61#ibcon#about to read 6, iclass 12, count 0 2006.168.08:04:21.61#ibcon#read 6, iclass 12, count 0 2006.168.08:04:21.61#ibcon#end of sib2, iclass 12, count 0 2006.168.08:04:21.61#ibcon#*mode == 0, iclass 12, count 0 2006.168.08:04:21.61#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.168.08:04:21.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.08:04:21.61#ibcon#*before write, iclass 12, count 0 2006.168.08:04:21.61#ibcon#enter sib2, iclass 12, count 0 2006.168.08:04:21.61#ibcon#flushed, iclass 12, count 0 2006.168.08:04:21.61#ibcon#about to write, iclass 12, count 0 2006.168.08:04:21.61#ibcon#wrote, iclass 12, count 0 2006.168.08:04:21.61#ibcon#about to read 3, iclass 12, count 0 2006.168.08:04:21.65#ibcon#read 3, iclass 12, count 0 2006.168.08:04:21.65#ibcon#about to read 4, iclass 12, count 0 2006.168.08:04:21.65#ibcon#read 4, iclass 12, count 0 2006.168.08:04:21.65#ibcon#about to read 5, iclass 12, count 0 2006.168.08:04:21.65#ibcon#read 5, iclass 12, count 0 2006.168.08:04:21.65#ibcon#about to read 6, iclass 12, count 0 2006.168.08:04:21.65#ibcon#read 6, iclass 12, count 0 2006.168.08:04:21.65#ibcon#end of sib2, iclass 12, count 0 2006.168.08:04:21.65#ibcon#*after write, iclass 12, count 0 2006.168.08:04:21.65#ibcon#*before return 0, iclass 12, count 0 2006.168.08:04:21.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.168.08:04:21.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.168.08:04:21.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.168.08:04:21.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.168.08:04:21.65$vc4f8/vb=4,4 2006.168.08:04:21.65#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.168.08:04:21.65#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.168.08:04:21.65#ibcon#ireg 11 cls_cnt 2 2006.168.08:04:21.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.168.08:04:21.71#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.168.08:04:21.71#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.168.08:04:21.71#ibcon#enter wrdev, iclass 14, count 2 2006.168.08:04:21.71#ibcon#first serial, iclass 14, count 2 2006.168.08:04:21.71#ibcon#enter sib2, iclass 14, count 2 2006.168.08:04:21.71#ibcon#flushed, iclass 14, count 2 2006.168.08:04:21.71#ibcon#about to write, iclass 14, count 2 2006.168.08:04:21.71#ibcon#wrote, iclass 14, count 2 2006.168.08:04:21.71#ibcon#about to read 3, iclass 14, count 2 2006.168.08:04:21.73#ibcon#read 3, iclass 14, count 2 2006.168.08:04:21.73#ibcon#about to read 4, iclass 14, count 2 2006.168.08:04:21.73#ibcon#read 4, iclass 14, count 2 2006.168.08:04:21.73#ibcon#about to read 5, iclass 14, count 2 2006.168.08:04:21.73#ibcon#read 5, iclass 14, count 2 2006.168.08:04:21.73#ibcon#about to read 6, iclass 14, count 2 2006.168.08:04:21.73#ibcon#read 6, iclass 14, count 2 2006.168.08:04:21.73#ibcon#end of sib2, iclass 14, count 2 2006.168.08:04:21.73#ibcon#*mode == 0, iclass 14, count 2 2006.168.08:04:21.73#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.168.08:04:21.73#ibcon#[27=AT04-04\r\n] 2006.168.08:04:21.73#ibcon#*before write, iclass 14, count 2 2006.168.08:04:21.73#ibcon#enter sib2, iclass 14, count 2 2006.168.08:04:21.73#ibcon#flushed, iclass 14, count 2 2006.168.08:04:21.73#ibcon#about to write, iclass 14, count 2 2006.168.08:04:21.73#ibcon#wrote, iclass 14, count 2 2006.168.08:04:21.73#ibcon#about to read 3, iclass 14, count 2 2006.168.08:04:21.76#ibcon#read 3, iclass 14, count 2 2006.168.08:04:21.76#ibcon#about to read 4, iclass 14, count 2 2006.168.08:04:21.76#ibcon#read 4, iclass 14, count 2 2006.168.08:04:21.76#ibcon#about to read 5, iclass 14, count 2 2006.168.08:04:21.76#ibcon#read 5, iclass 14, count 2 2006.168.08:04:21.76#ibcon#about to read 6, iclass 14, count 2 2006.168.08:04:21.76#ibcon#read 6, iclass 14, count 2 2006.168.08:04:21.76#ibcon#end of sib2, iclass 14, count 2 2006.168.08:04:21.76#ibcon#*after write, iclass 14, count 2 2006.168.08:04:21.76#ibcon#*before return 0, iclass 14, count 2 2006.168.08:04:21.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.168.08:04:21.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.168.08:04:21.76#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.168.08:04:21.76#ibcon#ireg 7 cls_cnt 0 2006.168.08:04:21.76#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.168.08:04:21.88#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.168.08:04:21.88#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.168.08:04:21.88#ibcon#enter wrdev, iclass 14, count 0 2006.168.08:04:21.88#ibcon#first serial, iclass 14, count 0 2006.168.08:04:21.88#ibcon#enter sib2, iclass 14, count 0 2006.168.08:04:21.88#ibcon#flushed, iclass 14, count 0 2006.168.08:04:21.88#ibcon#about to write, iclass 14, count 0 2006.168.08:04:21.88#ibcon#wrote, iclass 14, count 0 2006.168.08:04:21.88#ibcon#about to read 3, iclass 14, count 0 2006.168.08:04:21.90#ibcon#read 3, iclass 14, count 0 2006.168.08:04:21.90#ibcon#about to read 4, iclass 14, count 0 2006.168.08:04:21.90#ibcon#read 4, iclass 14, count 0 2006.168.08:04:21.90#ibcon#about to read 5, iclass 14, count 0 2006.168.08:04:21.90#ibcon#read 5, iclass 14, count 0 2006.168.08:04:21.90#ibcon#about to read 6, iclass 14, count 0 2006.168.08:04:21.90#ibcon#read 6, iclass 14, count 0 2006.168.08:04:21.90#ibcon#end of sib2, iclass 14, count 0 2006.168.08:04:21.90#ibcon#*mode == 0, iclass 14, count 0 2006.168.08:04:21.90#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.168.08:04:21.90#ibcon#[27=USB\r\n] 2006.168.08:04:21.90#ibcon#*before write, iclass 14, count 0 2006.168.08:04:21.90#ibcon#enter sib2, iclass 14, count 0 2006.168.08:04:21.90#ibcon#flushed, iclass 14, count 0 2006.168.08:04:21.90#ibcon#about to write, iclass 14, count 0 2006.168.08:04:21.90#ibcon#wrote, iclass 14, count 0 2006.168.08:04:21.90#ibcon#about to read 3, iclass 14, count 0 2006.168.08:04:21.93#ibcon#read 3, iclass 14, count 0 2006.168.08:04:21.93#ibcon#about to read 4, iclass 14, count 0 2006.168.08:04:21.93#ibcon#read 4, iclass 14, count 0 2006.168.08:04:21.93#ibcon#about to read 5, iclass 14, count 0 2006.168.08:04:21.93#ibcon#read 5, iclass 14, count 0 2006.168.08:04:21.93#ibcon#about to read 6, iclass 14, count 0 2006.168.08:04:21.93#ibcon#read 6, iclass 14, count 0 2006.168.08:04:21.93#ibcon#end of sib2, iclass 14, count 0 2006.168.08:04:21.93#ibcon#*after write, iclass 14, count 0 2006.168.08:04:21.93#ibcon#*before return 0, iclass 14, count 0 2006.168.08:04:21.93#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.168.08:04:21.93#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.168.08:04:21.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.168.08:04:21.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.168.08:04:21.93$vc4f8/vblo=5,744.99 2006.168.08:04:21.93#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.168.08:04:21.93#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.168.08:04:21.93#ibcon#ireg 17 cls_cnt 0 2006.168.08:04:21.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.168.08:04:21.93#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.168.08:04:21.93#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.168.08:04:21.93#ibcon#enter wrdev, iclass 16, count 0 2006.168.08:04:21.93#ibcon#first serial, iclass 16, count 0 2006.168.08:04:21.93#ibcon#enter sib2, iclass 16, count 0 2006.168.08:04:21.93#ibcon#flushed, iclass 16, count 0 2006.168.08:04:21.93#ibcon#about to write, iclass 16, count 0 2006.168.08:04:21.93#ibcon#wrote, iclass 16, count 0 2006.168.08:04:21.93#ibcon#about to read 3, iclass 16, count 0 2006.168.08:04:21.95#ibcon#read 3, iclass 16, count 0 2006.168.08:04:21.95#ibcon#about to read 4, iclass 16, count 0 2006.168.08:04:21.95#ibcon#read 4, iclass 16, count 0 2006.168.08:04:21.95#ibcon#about to read 5, iclass 16, count 0 2006.168.08:04:21.95#ibcon#read 5, iclass 16, count 0 2006.168.08:04:21.95#ibcon#about to read 6, iclass 16, count 0 2006.168.08:04:21.95#ibcon#read 6, iclass 16, count 0 2006.168.08:04:21.95#ibcon#end of sib2, iclass 16, count 0 2006.168.08:04:21.95#ibcon#*mode == 0, iclass 16, count 0 2006.168.08:04:21.95#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.168.08:04:21.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.08:04:21.95#ibcon#*before write, iclass 16, count 0 2006.168.08:04:21.95#ibcon#enter sib2, iclass 16, count 0 2006.168.08:04:21.95#ibcon#flushed, iclass 16, count 0 2006.168.08:04:21.95#ibcon#about to write, iclass 16, count 0 2006.168.08:04:21.95#ibcon#wrote, iclass 16, count 0 2006.168.08:04:21.95#ibcon#about to read 3, iclass 16, count 0 2006.168.08:04:21.99#ibcon#read 3, iclass 16, count 0 2006.168.08:04:21.99#ibcon#about to read 4, iclass 16, count 0 2006.168.08:04:21.99#ibcon#read 4, iclass 16, count 0 2006.168.08:04:21.99#ibcon#about to read 5, iclass 16, count 0 2006.168.08:04:21.99#ibcon#read 5, iclass 16, count 0 2006.168.08:04:21.99#ibcon#about to read 6, iclass 16, count 0 2006.168.08:04:21.99#ibcon#read 6, iclass 16, count 0 2006.168.08:04:21.99#ibcon#end of sib2, iclass 16, count 0 2006.168.08:04:21.99#ibcon#*after write, iclass 16, count 0 2006.168.08:04:21.99#ibcon#*before return 0, iclass 16, count 0 2006.168.08:04:21.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.168.08:04:21.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.168.08:04:21.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.168.08:04:21.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.168.08:04:21.99$vc4f8/vb=5,4 2006.168.08:04:21.99#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.168.08:04:21.99#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.168.08:04:21.99#ibcon#ireg 11 cls_cnt 2 2006.168.08:04:21.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.168.08:04:22.05#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.168.08:04:22.05#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.168.08:04:22.05#ibcon#enter wrdev, iclass 18, count 2 2006.168.08:04:22.05#ibcon#first serial, iclass 18, count 2 2006.168.08:04:22.05#ibcon#enter sib2, iclass 18, count 2 2006.168.08:04:22.05#ibcon#flushed, iclass 18, count 2 2006.168.08:04:22.05#ibcon#about to write, iclass 18, count 2 2006.168.08:04:22.05#ibcon#wrote, iclass 18, count 2 2006.168.08:04:22.05#ibcon#about to read 3, iclass 18, count 2 2006.168.08:04:22.07#ibcon#read 3, iclass 18, count 2 2006.168.08:04:22.07#ibcon#about to read 4, iclass 18, count 2 2006.168.08:04:22.07#ibcon#read 4, iclass 18, count 2 2006.168.08:04:22.07#ibcon#about to read 5, iclass 18, count 2 2006.168.08:04:22.07#ibcon#read 5, iclass 18, count 2 2006.168.08:04:22.07#ibcon#about to read 6, iclass 18, count 2 2006.168.08:04:22.07#ibcon#read 6, iclass 18, count 2 2006.168.08:04:22.07#ibcon#end of sib2, iclass 18, count 2 2006.168.08:04:22.07#ibcon#*mode == 0, iclass 18, count 2 2006.168.08:04:22.07#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.168.08:04:22.07#ibcon#[27=AT05-04\r\n] 2006.168.08:04:22.07#ibcon#*before write, iclass 18, count 2 2006.168.08:04:22.07#ibcon#enter sib2, iclass 18, count 2 2006.168.08:04:22.07#ibcon#flushed, iclass 18, count 2 2006.168.08:04:22.07#ibcon#about to write, iclass 18, count 2 2006.168.08:04:22.07#ibcon#wrote, iclass 18, count 2 2006.168.08:04:22.07#ibcon#about to read 3, iclass 18, count 2 2006.168.08:04:22.10#ibcon#read 3, iclass 18, count 2 2006.168.08:04:22.10#ibcon#about to read 4, iclass 18, count 2 2006.168.08:04:22.10#ibcon#read 4, iclass 18, count 2 2006.168.08:04:22.10#ibcon#about to read 5, iclass 18, count 2 2006.168.08:04:22.10#ibcon#read 5, iclass 18, count 2 2006.168.08:04:22.10#ibcon#about to read 6, iclass 18, count 2 2006.168.08:04:22.10#ibcon#read 6, iclass 18, count 2 2006.168.08:04:22.10#ibcon#end of sib2, iclass 18, count 2 2006.168.08:04:22.10#ibcon#*after write, iclass 18, count 2 2006.168.08:04:22.10#ibcon#*before return 0, iclass 18, count 2 2006.168.08:04:22.10#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.168.08:04:22.10#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.168.08:04:22.10#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.168.08:04:22.10#ibcon#ireg 7 cls_cnt 0 2006.168.08:04:22.10#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.168.08:04:22.22#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.168.08:04:22.22#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.168.08:04:22.22#ibcon#enter wrdev, iclass 18, count 0 2006.168.08:04:22.22#ibcon#first serial, iclass 18, count 0 2006.168.08:04:22.22#ibcon#enter sib2, iclass 18, count 0 2006.168.08:04:22.22#ibcon#flushed, iclass 18, count 0 2006.168.08:04:22.22#ibcon#about to write, iclass 18, count 0 2006.168.08:04:22.22#ibcon#wrote, iclass 18, count 0 2006.168.08:04:22.22#ibcon#about to read 3, iclass 18, count 0 2006.168.08:04:22.24#ibcon#read 3, iclass 18, count 0 2006.168.08:04:22.24#ibcon#about to read 4, iclass 18, count 0 2006.168.08:04:22.24#ibcon#read 4, iclass 18, count 0 2006.168.08:04:22.24#ibcon#about to read 5, iclass 18, count 0 2006.168.08:04:22.24#ibcon#read 5, iclass 18, count 0 2006.168.08:04:22.24#ibcon#about to read 6, iclass 18, count 0 2006.168.08:04:22.24#ibcon#read 6, iclass 18, count 0 2006.168.08:04:22.24#ibcon#end of sib2, iclass 18, count 0 2006.168.08:04:22.24#ibcon#*mode == 0, iclass 18, count 0 2006.168.08:04:22.24#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.08:04:22.24#ibcon#[27=USB\r\n] 2006.168.08:04:22.24#ibcon#*before write, iclass 18, count 0 2006.168.08:04:22.24#ibcon#enter sib2, iclass 18, count 0 2006.168.08:04:22.24#ibcon#flushed, iclass 18, count 0 2006.168.08:04:22.24#ibcon#about to write, iclass 18, count 0 2006.168.08:04:22.24#ibcon#wrote, iclass 18, count 0 2006.168.08:04:22.24#ibcon#about to read 3, iclass 18, count 0 2006.168.08:04:22.27#ibcon#read 3, iclass 18, count 0 2006.168.08:04:22.27#ibcon#about to read 4, iclass 18, count 0 2006.168.08:04:22.27#ibcon#read 4, iclass 18, count 0 2006.168.08:04:22.27#ibcon#about to read 5, iclass 18, count 0 2006.168.08:04:22.27#ibcon#read 5, iclass 18, count 0 2006.168.08:04:22.27#ibcon#about to read 6, iclass 18, count 0 2006.168.08:04:22.27#ibcon#read 6, iclass 18, count 0 2006.168.08:04:22.27#ibcon#end of sib2, iclass 18, count 0 2006.168.08:04:22.27#ibcon#*after write, iclass 18, count 0 2006.168.08:04:22.27#ibcon#*before return 0, iclass 18, count 0 2006.168.08:04:22.27#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.168.08:04:22.27#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.168.08:04:22.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.08:04:22.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.08:04:22.27$vc4f8/vblo=6,752.99 2006.168.08:04:22.27#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.168.08:04:22.27#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.168.08:04:22.27#ibcon#ireg 17 cls_cnt 0 2006.168.08:04:22.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:04:22.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:04:22.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:04:22.27#ibcon#enter wrdev, iclass 20, count 0 2006.168.08:04:22.27#ibcon#first serial, iclass 20, count 0 2006.168.08:04:22.27#ibcon#enter sib2, iclass 20, count 0 2006.168.08:04:22.27#ibcon#flushed, iclass 20, count 0 2006.168.08:04:22.27#ibcon#about to write, iclass 20, count 0 2006.168.08:04:22.27#ibcon#wrote, iclass 20, count 0 2006.168.08:04:22.27#ibcon#about to read 3, iclass 20, count 0 2006.168.08:04:22.29#ibcon#read 3, iclass 20, count 0 2006.168.08:04:22.29#ibcon#about to read 4, iclass 20, count 0 2006.168.08:04:22.29#ibcon#read 4, iclass 20, count 0 2006.168.08:04:22.29#ibcon#about to read 5, iclass 20, count 0 2006.168.08:04:22.29#ibcon#read 5, iclass 20, count 0 2006.168.08:04:22.29#ibcon#about to read 6, iclass 20, count 0 2006.168.08:04:22.29#ibcon#read 6, iclass 20, count 0 2006.168.08:04:22.29#ibcon#end of sib2, iclass 20, count 0 2006.168.08:04:22.29#ibcon#*mode == 0, iclass 20, count 0 2006.168.08:04:22.29#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.168.08:04:22.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.08:04:22.29#ibcon#*before write, iclass 20, count 0 2006.168.08:04:22.29#ibcon#enter sib2, iclass 20, count 0 2006.168.08:04:22.29#ibcon#flushed, iclass 20, count 0 2006.168.08:04:22.29#ibcon#about to write, iclass 20, count 0 2006.168.08:04:22.29#ibcon#wrote, iclass 20, count 0 2006.168.08:04:22.29#ibcon#about to read 3, iclass 20, count 0 2006.168.08:04:22.33#ibcon#read 3, iclass 20, count 0 2006.168.08:04:22.33#ibcon#about to read 4, iclass 20, count 0 2006.168.08:04:22.33#ibcon#read 4, iclass 20, count 0 2006.168.08:04:22.33#ibcon#about to read 5, iclass 20, count 0 2006.168.08:04:22.33#ibcon#read 5, iclass 20, count 0 2006.168.08:04:22.33#ibcon#about to read 6, iclass 20, count 0 2006.168.08:04:22.33#ibcon#read 6, iclass 20, count 0 2006.168.08:04:22.33#ibcon#end of sib2, iclass 20, count 0 2006.168.08:04:22.33#ibcon#*after write, iclass 20, count 0 2006.168.08:04:22.33#ibcon#*before return 0, iclass 20, count 0 2006.168.08:04:22.33#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:04:22.33#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:04:22.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.168.08:04:22.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.168.08:04:22.33$vc4f8/vb=6,4 2006.168.08:04:22.33#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.168.08:04:22.33#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.168.08:04:22.33#ibcon#ireg 11 cls_cnt 2 2006.168.08:04:22.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.168.08:04:22.39#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.168.08:04:22.39#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.168.08:04:22.39#ibcon#enter wrdev, iclass 22, count 2 2006.168.08:04:22.39#ibcon#first serial, iclass 22, count 2 2006.168.08:04:22.39#ibcon#enter sib2, iclass 22, count 2 2006.168.08:04:22.39#ibcon#flushed, iclass 22, count 2 2006.168.08:04:22.39#ibcon#about to write, iclass 22, count 2 2006.168.08:04:22.39#ibcon#wrote, iclass 22, count 2 2006.168.08:04:22.39#ibcon#about to read 3, iclass 22, count 2 2006.168.08:04:22.41#ibcon#read 3, iclass 22, count 2 2006.168.08:04:22.41#ibcon#about to read 4, iclass 22, count 2 2006.168.08:04:22.41#ibcon#read 4, iclass 22, count 2 2006.168.08:04:22.41#ibcon#about to read 5, iclass 22, count 2 2006.168.08:04:22.41#ibcon#read 5, iclass 22, count 2 2006.168.08:04:22.41#ibcon#about to read 6, iclass 22, count 2 2006.168.08:04:22.41#ibcon#read 6, iclass 22, count 2 2006.168.08:04:22.41#ibcon#end of sib2, iclass 22, count 2 2006.168.08:04:22.41#ibcon#*mode == 0, iclass 22, count 2 2006.168.08:04:22.41#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.168.08:04:22.41#ibcon#[27=AT06-04\r\n] 2006.168.08:04:22.41#ibcon#*before write, iclass 22, count 2 2006.168.08:04:22.41#ibcon#enter sib2, iclass 22, count 2 2006.168.08:04:22.41#ibcon#flushed, iclass 22, count 2 2006.168.08:04:22.41#ibcon#about to write, iclass 22, count 2 2006.168.08:04:22.41#ibcon#wrote, iclass 22, count 2 2006.168.08:04:22.41#ibcon#about to read 3, iclass 22, count 2 2006.168.08:04:22.44#ibcon#read 3, iclass 22, count 2 2006.168.08:04:22.44#ibcon#about to read 4, iclass 22, count 2 2006.168.08:04:22.44#ibcon#read 4, iclass 22, count 2 2006.168.08:04:22.44#ibcon#about to read 5, iclass 22, count 2 2006.168.08:04:22.44#ibcon#read 5, iclass 22, count 2 2006.168.08:04:22.44#ibcon#about to read 6, iclass 22, count 2 2006.168.08:04:22.44#ibcon#read 6, iclass 22, count 2 2006.168.08:04:22.44#ibcon#end of sib2, iclass 22, count 2 2006.168.08:04:22.44#ibcon#*after write, iclass 22, count 2 2006.168.08:04:22.44#ibcon#*before return 0, iclass 22, count 2 2006.168.08:04:22.44#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.168.08:04:22.44#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.168.08:04:22.44#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.168.08:04:22.44#ibcon#ireg 7 cls_cnt 0 2006.168.08:04:22.44#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.168.08:04:22.56#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.168.08:04:22.56#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.168.08:04:22.56#ibcon#enter wrdev, iclass 22, count 0 2006.168.08:04:22.56#ibcon#first serial, iclass 22, count 0 2006.168.08:04:22.56#ibcon#enter sib2, iclass 22, count 0 2006.168.08:04:22.56#ibcon#flushed, iclass 22, count 0 2006.168.08:04:22.56#ibcon#about to write, iclass 22, count 0 2006.168.08:04:22.56#ibcon#wrote, iclass 22, count 0 2006.168.08:04:22.56#ibcon#about to read 3, iclass 22, count 0 2006.168.08:04:22.58#ibcon#read 3, iclass 22, count 0 2006.168.08:04:22.58#ibcon#about to read 4, iclass 22, count 0 2006.168.08:04:22.58#ibcon#read 4, iclass 22, count 0 2006.168.08:04:22.58#ibcon#about to read 5, iclass 22, count 0 2006.168.08:04:22.58#ibcon#read 5, iclass 22, count 0 2006.168.08:04:22.58#ibcon#about to read 6, iclass 22, count 0 2006.168.08:04:22.58#ibcon#read 6, iclass 22, count 0 2006.168.08:04:22.58#ibcon#end of sib2, iclass 22, count 0 2006.168.08:04:22.58#ibcon#*mode == 0, iclass 22, count 0 2006.168.08:04:22.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.168.08:04:22.58#ibcon#[27=USB\r\n] 2006.168.08:04:22.58#ibcon#*before write, iclass 22, count 0 2006.168.08:04:22.58#ibcon#enter sib2, iclass 22, count 0 2006.168.08:04:22.58#ibcon#flushed, iclass 22, count 0 2006.168.08:04:22.58#ibcon#about to write, iclass 22, count 0 2006.168.08:04:22.58#ibcon#wrote, iclass 22, count 0 2006.168.08:04:22.58#ibcon#about to read 3, iclass 22, count 0 2006.168.08:04:22.61#ibcon#read 3, iclass 22, count 0 2006.168.08:04:22.61#ibcon#about to read 4, iclass 22, count 0 2006.168.08:04:22.61#ibcon#read 4, iclass 22, count 0 2006.168.08:04:22.61#ibcon#about to read 5, iclass 22, count 0 2006.168.08:04:22.61#ibcon#read 5, iclass 22, count 0 2006.168.08:04:22.61#ibcon#about to read 6, iclass 22, count 0 2006.168.08:04:22.61#ibcon#read 6, iclass 22, count 0 2006.168.08:04:22.61#ibcon#end of sib2, iclass 22, count 0 2006.168.08:04:22.61#ibcon#*after write, iclass 22, count 0 2006.168.08:04:22.61#ibcon#*before return 0, iclass 22, count 0 2006.168.08:04:22.61#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.168.08:04:22.61#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.168.08:04:22.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.168.08:04:22.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.168.08:04:22.61$vc4f8/vabw=wide 2006.168.08:04:22.61#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.168.08:04:22.61#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.168.08:04:22.61#ibcon#ireg 8 cls_cnt 0 2006.168.08:04:22.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.168.08:04:22.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.168.08:04:22.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.168.08:04:22.61#ibcon#enter wrdev, iclass 24, count 0 2006.168.08:04:22.61#ibcon#first serial, iclass 24, count 0 2006.168.08:04:22.61#ibcon#enter sib2, iclass 24, count 0 2006.168.08:04:22.61#ibcon#flushed, iclass 24, count 0 2006.168.08:04:22.61#ibcon#about to write, iclass 24, count 0 2006.168.08:04:22.61#ibcon#wrote, iclass 24, count 0 2006.168.08:04:22.61#ibcon#about to read 3, iclass 24, count 0 2006.168.08:04:22.63#ibcon#read 3, iclass 24, count 0 2006.168.08:04:22.63#ibcon#about to read 4, iclass 24, count 0 2006.168.08:04:22.63#ibcon#read 4, iclass 24, count 0 2006.168.08:04:22.63#ibcon#about to read 5, iclass 24, count 0 2006.168.08:04:22.63#ibcon#read 5, iclass 24, count 0 2006.168.08:04:22.63#ibcon#about to read 6, iclass 24, count 0 2006.168.08:04:22.63#ibcon#read 6, iclass 24, count 0 2006.168.08:04:22.63#ibcon#end of sib2, iclass 24, count 0 2006.168.08:04:22.63#ibcon#*mode == 0, iclass 24, count 0 2006.168.08:04:22.63#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.168.08:04:22.63#ibcon#[25=BW32\r\n] 2006.168.08:04:22.63#ibcon#*before write, iclass 24, count 0 2006.168.08:04:22.63#ibcon#enter sib2, iclass 24, count 0 2006.168.08:04:22.63#ibcon#flushed, iclass 24, count 0 2006.168.08:04:22.63#ibcon#about to write, iclass 24, count 0 2006.168.08:04:22.63#ibcon#wrote, iclass 24, count 0 2006.168.08:04:22.63#ibcon#about to read 3, iclass 24, count 0 2006.168.08:04:22.66#ibcon#read 3, iclass 24, count 0 2006.168.08:04:22.66#ibcon#about to read 4, iclass 24, count 0 2006.168.08:04:22.66#ibcon#read 4, iclass 24, count 0 2006.168.08:04:22.66#ibcon#about to read 5, iclass 24, count 0 2006.168.08:04:22.66#ibcon#read 5, iclass 24, count 0 2006.168.08:04:22.66#ibcon#about to read 6, iclass 24, count 0 2006.168.08:04:22.66#ibcon#read 6, iclass 24, count 0 2006.168.08:04:22.66#ibcon#end of sib2, iclass 24, count 0 2006.168.08:04:22.66#ibcon#*after write, iclass 24, count 0 2006.168.08:04:22.66#ibcon#*before return 0, iclass 24, count 0 2006.168.08:04:22.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.168.08:04:22.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.168.08:04:22.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.168.08:04:22.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.168.08:04:22.66$vc4f8/vbbw=wide 2006.168.08:04:22.66#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.168.08:04:22.66#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.168.08:04:22.66#ibcon#ireg 8 cls_cnt 0 2006.168.08:04:22.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:04:22.73#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:04:22.73#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:04:22.73#ibcon#enter wrdev, iclass 26, count 0 2006.168.08:04:22.73#ibcon#first serial, iclass 26, count 0 2006.168.08:04:22.73#ibcon#enter sib2, iclass 26, count 0 2006.168.08:04:22.73#ibcon#flushed, iclass 26, count 0 2006.168.08:04:22.73#ibcon#about to write, iclass 26, count 0 2006.168.08:04:22.73#ibcon#wrote, iclass 26, count 0 2006.168.08:04:22.73#ibcon#about to read 3, iclass 26, count 0 2006.168.08:04:22.75#ibcon#read 3, iclass 26, count 0 2006.168.08:04:22.75#ibcon#about to read 4, iclass 26, count 0 2006.168.08:04:22.75#ibcon#read 4, iclass 26, count 0 2006.168.08:04:22.75#ibcon#about to read 5, iclass 26, count 0 2006.168.08:04:22.75#ibcon#read 5, iclass 26, count 0 2006.168.08:04:22.75#ibcon#about to read 6, iclass 26, count 0 2006.168.08:04:22.75#ibcon#read 6, iclass 26, count 0 2006.168.08:04:22.75#ibcon#end of sib2, iclass 26, count 0 2006.168.08:04:22.75#ibcon#*mode == 0, iclass 26, count 0 2006.168.08:04:22.75#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.168.08:04:22.75#ibcon#[27=BW32\r\n] 2006.168.08:04:22.75#ibcon#*before write, iclass 26, count 0 2006.168.08:04:22.75#ibcon#enter sib2, iclass 26, count 0 2006.168.08:04:22.75#ibcon#flushed, iclass 26, count 0 2006.168.08:04:22.75#ibcon#about to write, iclass 26, count 0 2006.168.08:04:22.75#ibcon#wrote, iclass 26, count 0 2006.168.08:04:22.75#ibcon#about to read 3, iclass 26, count 0 2006.168.08:04:22.78#ibcon#read 3, iclass 26, count 0 2006.168.08:04:22.78#ibcon#about to read 4, iclass 26, count 0 2006.168.08:04:22.78#ibcon#read 4, iclass 26, count 0 2006.168.08:04:22.78#ibcon#about to read 5, iclass 26, count 0 2006.168.08:04:22.78#ibcon#read 5, iclass 26, count 0 2006.168.08:04:22.78#ibcon#about to read 6, iclass 26, count 0 2006.168.08:04:22.78#ibcon#read 6, iclass 26, count 0 2006.168.08:04:22.78#ibcon#end of sib2, iclass 26, count 0 2006.168.08:04:22.78#ibcon#*after write, iclass 26, count 0 2006.168.08:04:22.78#ibcon#*before return 0, iclass 26, count 0 2006.168.08:04:22.78#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:04:22.78#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:04:22.78#ibcon#about to clear, iclass 26 cls_cnt 0 2006.168.08:04:22.78#ibcon#cleared, iclass 26 cls_cnt 0 2006.168.08:04:22.78$4f8m12a/ifd4f 2006.168.08:04:22.78$ifd4f/lo= 2006.168.08:04:22.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.08:04:22.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.08:04:22.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.08:04:22.78$ifd4f/patch= 2006.168.08:04:22.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.08:04:22.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.08:04:22.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.08:04:22.78$4f8m12a/"form=m,16.000,1:2 2006.168.08:04:22.78$4f8m12a/"tpicd 2006.168.08:04:22.78$4f8m12a/echo=off 2006.168.08:04:22.78$4f8m12a/xlog=off 2006.168.08:04:22.78:!2006.168.08:04:50 2006.168.08:04:33.14#trakl#Source acquired 2006.168.08:04:35.14#flagr#flagr/antenna,acquired 2006.168.08:04:50.00:preob 2006.168.08:04:51.14/onsource/TRACKING 2006.168.08:04:51.14:!2006.168.08:05:00 2006.168.08:05:00.00:data_valid=on 2006.168.08:05:00.00:midob 2006.168.08:05:00.14/onsource/TRACKING 2006.168.08:05:00.14/wx/26.98,1004.4,74 2006.168.08:05:00.36/cable/+6.4721E-03 2006.168.08:05:01.45/va/01,08,usb,yes,29,31 2006.168.08:05:01.45/va/02,07,usb,yes,29,31 2006.168.08:05:01.45/va/03,06,usb,yes,31,31 2006.168.08:05:01.45/va/04,07,usb,yes,30,32 2006.168.08:05:01.45/va/05,07,usb,yes,30,32 2006.168.08:05:01.45/va/06,06,usb,yes,29,29 2006.168.08:05:01.45/va/07,06,usb,yes,30,29 2006.168.08:05:01.45/va/08,07,usb,yes,28,27 2006.168.08:05:01.68/valo/01,532.99,yes,locked 2006.168.08:05:01.68/valo/02,572.99,yes,locked 2006.168.08:05:01.68/valo/03,672.99,yes,locked 2006.168.08:05:01.68/valo/04,832.99,yes,locked 2006.168.08:05:01.68/valo/05,652.99,yes,locked 2006.168.08:05:01.68/valo/06,772.99,yes,locked 2006.168.08:05:01.68/valo/07,832.99,yes,locked 2006.168.08:05:01.68/valo/08,852.99,yes,locked 2006.168.08:05:02.77/vb/01,04,usb,yes,29,27 2006.168.08:05:02.77/vb/02,04,usb,yes,30,32 2006.168.08:05:02.77/vb/03,04,usb,yes,27,30 2006.168.08:05:02.77/vb/04,04,usb,yes,28,28 2006.168.08:05:02.77/vb/05,04,usb,yes,27,30 2006.168.08:05:02.77/vb/06,04,usb,yes,28,30 2006.168.08:05:02.77/vb/07,04,usb,yes,29,29 2006.168.08:05:02.77/vb/08,04,usb,yes,28,30 2006.168.08:05:03.00/vblo/01,632.99,yes,locked 2006.168.08:05:03.00/vblo/02,640.99,yes,locked 2006.168.08:05:03.00/vblo/03,656.99,yes,locked 2006.168.08:05:03.00/vblo/04,712.99,yes,locked 2006.168.08:05:03.00/vblo/05,744.99,yes,locked 2006.168.08:05:03.00/vblo/06,752.99,yes,locked 2006.168.08:05:03.00/vblo/07,734.99,yes,locked 2006.168.08:05:03.00/vblo/08,744.99,yes,locked 2006.168.08:05:03.15/vabw/8 2006.168.08:05:03.30/vbbw/8 2006.168.08:05:03.39/xfe/off,on,14.2 2006.168.08:05:03.79/ifatt/23,28,28,28 2006.168.08:05:04.07/fmout-gps/S +4.20E-07 2006.168.08:05:04.15:!2006.168.08:06:00 2006.168.08:06:00.00:data_valid=off 2006.168.08:06:00.00:postob 2006.168.08:06:00.17/cable/+6.4726E-03 2006.168.08:06:00.17/wx/26.97,1004.4,74 2006.168.08:06:01.07/fmout-gps/S +4.20E-07 2006.168.08:06:01.07:scan_name=168-0806,k06168,60 2006.168.08:06:01.08:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.168.08:06:01.14#flagr#flagr/antenna,new-source 2006.168.08:06:02.14:checkk5 2006.168.08:06:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.168.08:06:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.168.08:06:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.168.08:06:03.64/chk_autoobs//k5ts4/ autoobs is running! 2006.168.08:06:04.01/chk_obsdata//k5ts1/T1680805??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.168.08:06:04.39/chk_obsdata//k5ts2/T1680805??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.168.08:06:04.76/chk_obsdata//k5ts3/T1680805??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.168.08:06:05.13/chk_obsdata//k5ts4/T1680805??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.168.08:06:05.82/k5log//k5ts1_log_newline 2006.168.08:06:06.51/k5log//k5ts2_log_newline 2006.168.08:06:07.21/k5log//k5ts3_log_newline 2006.168.08:06:07.90/k5log//k5ts4_log_newline 2006.168.08:06:07.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.08:06:07.92:4f8m12a=2 2006.168.08:06:07.92$4f8m12a/echo=on 2006.168.08:06:07.92$4f8m12a/pcalon 2006.168.08:06:07.92$pcalon/"no phase cal control is implemented here 2006.168.08:06:07.92$4f8m12a/"tpicd=stop 2006.168.08:06:07.92$4f8m12a/vc4f8 2006.168.08:06:07.92$vc4f8/valo=1,532.99 2006.168.08:06:07.92#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.168.08:06:07.92#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.168.08:06:07.92#ibcon#ireg 17 cls_cnt 0 2006.168.08:06:07.92#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:06:07.92#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:06:07.92#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:06:07.92#ibcon#enter wrdev, iclass 37, count 0 2006.168.08:06:07.92#ibcon#first serial, iclass 37, count 0 2006.168.08:06:07.92#ibcon#enter sib2, iclass 37, count 0 2006.168.08:06:07.92#ibcon#flushed, iclass 37, count 0 2006.168.08:06:07.92#ibcon#about to write, iclass 37, count 0 2006.168.08:06:07.92#ibcon#wrote, iclass 37, count 0 2006.168.08:06:07.92#ibcon#about to read 3, iclass 37, count 0 2006.168.08:06:07.97#ibcon#read 3, iclass 37, count 0 2006.168.08:06:07.97#ibcon#about to read 4, iclass 37, count 0 2006.168.08:06:07.97#ibcon#read 4, iclass 37, count 0 2006.168.08:06:07.97#ibcon#about to read 5, iclass 37, count 0 2006.168.08:06:07.97#ibcon#read 5, iclass 37, count 0 2006.168.08:06:07.97#ibcon#about to read 6, iclass 37, count 0 2006.168.08:06:07.97#ibcon#read 6, iclass 37, count 0 2006.168.08:06:07.97#ibcon#end of sib2, iclass 37, count 0 2006.168.08:06:07.97#ibcon#*mode == 0, iclass 37, count 0 2006.168.08:06:07.97#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.168.08:06:07.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.08:06:07.97#ibcon#*before write, iclass 37, count 0 2006.168.08:06:07.97#ibcon#enter sib2, iclass 37, count 0 2006.168.08:06:07.97#ibcon#flushed, iclass 37, count 0 2006.168.08:06:07.97#ibcon#about to write, iclass 37, count 0 2006.168.08:06:07.97#ibcon#wrote, iclass 37, count 0 2006.168.08:06:07.97#ibcon#about to read 3, iclass 37, count 0 2006.168.08:06:08.01#ibcon#read 3, iclass 37, count 0 2006.168.08:06:08.01#ibcon#about to read 4, iclass 37, count 0 2006.168.08:06:08.01#ibcon#read 4, iclass 37, count 0 2006.168.08:06:08.01#ibcon#about to read 5, iclass 37, count 0 2006.168.08:06:08.01#ibcon#read 5, iclass 37, count 0 2006.168.08:06:08.01#ibcon#about to read 6, iclass 37, count 0 2006.168.08:06:08.01#ibcon#read 6, iclass 37, count 0 2006.168.08:06:08.01#ibcon#end of sib2, iclass 37, count 0 2006.168.08:06:08.01#ibcon#*after write, iclass 37, count 0 2006.168.08:06:08.01#ibcon#*before return 0, iclass 37, count 0 2006.168.08:06:08.01#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:06:08.01#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:06:08.01#ibcon#about to clear, iclass 37 cls_cnt 0 2006.168.08:06:08.01#ibcon#cleared, iclass 37 cls_cnt 0 2006.168.08:06:08.01$vc4f8/va=1,8 2006.168.08:06:08.01#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.168.08:06:08.01#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.168.08:06:08.01#ibcon#ireg 11 cls_cnt 2 2006.168.08:06:08.01#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.168.08:06:08.01#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.168.08:06:08.01#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.168.08:06:08.01#ibcon#enter wrdev, iclass 39, count 2 2006.168.08:06:08.01#ibcon#first serial, iclass 39, count 2 2006.168.08:06:08.01#ibcon#enter sib2, iclass 39, count 2 2006.168.08:06:08.01#ibcon#flushed, iclass 39, count 2 2006.168.08:06:08.01#ibcon#about to write, iclass 39, count 2 2006.168.08:06:08.01#ibcon#wrote, iclass 39, count 2 2006.168.08:06:08.01#ibcon#about to read 3, iclass 39, count 2 2006.168.08:06:08.03#ibcon#read 3, iclass 39, count 2 2006.168.08:06:08.03#ibcon#about to read 4, iclass 39, count 2 2006.168.08:06:08.03#ibcon#read 4, iclass 39, count 2 2006.168.08:06:08.03#ibcon#about to read 5, iclass 39, count 2 2006.168.08:06:08.03#ibcon#read 5, iclass 39, count 2 2006.168.08:06:08.03#ibcon#about to read 6, iclass 39, count 2 2006.168.08:06:08.03#ibcon#read 6, iclass 39, count 2 2006.168.08:06:08.03#ibcon#end of sib2, iclass 39, count 2 2006.168.08:06:08.03#ibcon#*mode == 0, iclass 39, count 2 2006.168.08:06:08.03#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.168.08:06:08.03#ibcon#[25=AT01-08\r\n] 2006.168.08:06:08.03#ibcon#*before write, iclass 39, count 2 2006.168.08:06:08.03#ibcon#enter sib2, iclass 39, count 2 2006.168.08:06:08.03#ibcon#flushed, iclass 39, count 2 2006.168.08:06:08.03#ibcon#about to write, iclass 39, count 2 2006.168.08:06:08.03#ibcon#wrote, iclass 39, count 2 2006.168.08:06:08.03#ibcon#about to read 3, iclass 39, count 2 2006.168.08:06:08.06#ibcon#read 3, iclass 39, count 2 2006.168.08:06:08.06#ibcon#about to read 4, iclass 39, count 2 2006.168.08:06:08.06#ibcon#read 4, iclass 39, count 2 2006.168.08:06:08.06#ibcon#about to read 5, iclass 39, count 2 2006.168.08:06:08.06#ibcon#read 5, iclass 39, count 2 2006.168.08:06:08.06#ibcon#about to read 6, iclass 39, count 2 2006.168.08:06:08.06#ibcon#read 6, iclass 39, count 2 2006.168.08:06:08.06#ibcon#end of sib2, iclass 39, count 2 2006.168.08:06:08.06#ibcon#*after write, iclass 39, count 2 2006.168.08:06:08.06#ibcon#*before return 0, iclass 39, count 2 2006.168.08:06:08.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.168.08:06:08.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.168.08:06:08.06#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.168.08:06:08.06#ibcon#ireg 7 cls_cnt 0 2006.168.08:06:08.06#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.168.08:06:08.18#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.168.08:06:08.18#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.168.08:06:08.18#ibcon#enter wrdev, iclass 39, count 0 2006.168.08:06:08.18#ibcon#first serial, iclass 39, count 0 2006.168.08:06:08.18#ibcon#enter sib2, iclass 39, count 0 2006.168.08:06:08.18#ibcon#flushed, iclass 39, count 0 2006.168.08:06:08.18#ibcon#about to write, iclass 39, count 0 2006.168.08:06:08.18#ibcon#wrote, iclass 39, count 0 2006.168.08:06:08.18#ibcon#about to read 3, iclass 39, count 0 2006.168.08:06:08.20#ibcon#read 3, iclass 39, count 0 2006.168.08:06:08.20#ibcon#about to read 4, iclass 39, count 0 2006.168.08:06:08.20#ibcon#read 4, iclass 39, count 0 2006.168.08:06:08.20#ibcon#about to read 5, iclass 39, count 0 2006.168.08:06:08.20#ibcon#read 5, iclass 39, count 0 2006.168.08:06:08.20#ibcon#about to read 6, iclass 39, count 0 2006.168.08:06:08.20#ibcon#read 6, iclass 39, count 0 2006.168.08:06:08.20#ibcon#end of sib2, iclass 39, count 0 2006.168.08:06:08.20#ibcon#*mode == 0, iclass 39, count 0 2006.168.08:06:08.20#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.168.08:06:08.20#ibcon#[25=USB\r\n] 2006.168.08:06:08.20#ibcon#*before write, iclass 39, count 0 2006.168.08:06:08.20#ibcon#enter sib2, iclass 39, count 0 2006.168.08:06:08.20#ibcon#flushed, iclass 39, count 0 2006.168.08:06:08.20#ibcon#about to write, iclass 39, count 0 2006.168.08:06:08.20#ibcon#wrote, iclass 39, count 0 2006.168.08:06:08.20#ibcon#about to read 3, iclass 39, count 0 2006.168.08:06:08.23#ibcon#read 3, iclass 39, count 0 2006.168.08:06:08.23#ibcon#about to read 4, iclass 39, count 0 2006.168.08:06:08.23#ibcon#read 4, iclass 39, count 0 2006.168.08:06:08.23#ibcon#about to read 5, iclass 39, count 0 2006.168.08:06:08.23#ibcon#read 5, iclass 39, count 0 2006.168.08:06:08.23#ibcon#about to read 6, iclass 39, count 0 2006.168.08:06:08.23#ibcon#read 6, iclass 39, count 0 2006.168.08:06:08.23#ibcon#end of sib2, iclass 39, count 0 2006.168.08:06:08.23#ibcon#*after write, iclass 39, count 0 2006.168.08:06:08.23#ibcon#*before return 0, iclass 39, count 0 2006.168.08:06:08.23#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.168.08:06:08.23#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.168.08:06:08.23#ibcon#about to clear, iclass 39 cls_cnt 0 2006.168.08:06:08.23#ibcon#cleared, iclass 39 cls_cnt 0 2006.168.08:06:08.23$vc4f8/valo=2,572.99 2006.168.08:06:08.23#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.168.08:06:08.23#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.168.08:06:08.23#ibcon#ireg 17 cls_cnt 0 2006.168.08:06:08.23#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.168.08:06:08.23#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.168.08:06:08.23#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.168.08:06:08.23#ibcon#enter wrdev, iclass 3, count 0 2006.168.08:06:08.23#ibcon#first serial, iclass 3, count 0 2006.168.08:06:08.23#ibcon#enter sib2, iclass 3, count 0 2006.168.08:06:08.23#ibcon#flushed, iclass 3, count 0 2006.168.08:06:08.23#ibcon#about to write, iclass 3, count 0 2006.168.08:06:08.23#ibcon#wrote, iclass 3, count 0 2006.168.08:06:08.23#ibcon#about to read 3, iclass 3, count 0 2006.168.08:06:08.25#ibcon#read 3, iclass 3, count 0 2006.168.08:06:08.25#ibcon#about to read 4, iclass 3, count 0 2006.168.08:06:08.25#ibcon#read 4, iclass 3, count 0 2006.168.08:06:08.25#ibcon#about to read 5, iclass 3, count 0 2006.168.08:06:08.25#ibcon#read 5, iclass 3, count 0 2006.168.08:06:08.25#ibcon#about to read 6, iclass 3, count 0 2006.168.08:06:08.25#ibcon#read 6, iclass 3, count 0 2006.168.08:06:08.25#ibcon#end of sib2, iclass 3, count 0 2006.168.08:06:08.25#ibcon#*mode == 0, iclass 3, count 0 2006.168.08:06:08.25#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.168.08:06:08.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.08:06:08.25#ibcon#*before write, iclass 3, count 0 2006.168.08:06:08.25#ibcon#enter sib2, iclass 3, count 0 2006.168.08:06:08.25#ibcon#flushed, iclass 3, count 0 2006.168.08:06:08.25#ibcon#about to write, iclass 3, count 0 2006.168.08:06:08.25#ibcon#wrote, iclass 3, count 0 2006.168.08:06:08.25#ibcon#about to read 3, iclass 3, count 0 2006.168.08:06:08.29#ibcon#read 3, iclass 3, count 0 2006.168.08:06:08.29#ibcon#about to read 4, iclass 3, count 0 2006.168.08:06:08.29#ibcon#read 4, iclass 3, count 0 2006.168.08:06:08.29#ibcon#about to read 5, iclass 3, count 0 2006.168.08:06:08.29#ibcon#read 5, iclass 3, count 0 2006.168.08:06:08.29#ibcon#about to read 6, iclass 3, count 0 2006.168.08:06:08.29#ibcon#read 6, iclass 3, count 0 2006.168.08:06:08.29#ibcon#end of sib2, iclass 3, count 0 2006.168.08:06:08.29#ibcon#*after write, iclass 3, count 0 2006.168.08:06:08.29#ibcon#*before return 0, iclass 3, count 0 2006.168.08:06:08.29#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.168.08:06:08.29#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.168.08:06:08.29#ibcon#about to clear, iclass 3 cls_cnt 0 2006.168.08:06:08.29#ibcon#cleared, iclass 3 cls_cnt 0 2006.168.08:06:08.29$vc4f8/va=2,7 2006.168.08:06:08.29#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.168.08:06:08.29#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.168.08:06:08.29#ibcon#ireg 11 cls_cnt 2 2006.168.08:06:08.29#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.168.08:06:08.35#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.168.08:06:08.35#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.168.08:06:08.35#ibcon#enter wrdev, iclass 5, count 2 2006.168.08:06:08.35#ibcon#first serial, iclass 5, count 2 2006.168.08:06:08.35#ibcon#enter sib2, iclass 5, count 2 2006.168.08:06:08.35#ibcon#flushed, iclass 5, count 2 2006.168.08:06:08.35#ibcon#about to write, iclass 5, count 2 2006.168.08:06:08.35#ibcon#wrote, iclass 5, count 2 2006.168.08:06:08.35#ibcon#about to read 3, iclass 5, count 2 2006.168.08:06:08.37#ibcon#read 3, iclass 5, count 2 2006.168.08:06:08.37#ibcon#about to read 4, iclass 5, count 2 2006.168.08:06:08.37#ibcon#read 4, iclass 5, count 2 2006.168.08:06:08.37#ibcon#about to read 5, iclass 5, count 2 2006.168.08:06:08.37#ibcon#read 5, iclass 5, count 2 2006.168.08:06:08.37#ibcon#about to read 6, iclass 5, count 2 2006.168.08:06:08.37#ibcon#read 6, iclass 5, count 2 2006.168.08:06:08.37#ibcon#end of sib2, iclass 5, count 2 2006.168.08:06:08.37#ibcon#*mode == 0, iclass 5, count 2 2006.168.08:06:08.37#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.168.08:06:08.37#ibcon#[25=AT02-07\r\n] 2006.168.08:06:08.37#ibcon#*before write, iclass 5, count 2 2006.168.08:06:08.37#ibcon#enter sib2, iclass 5, count 2 2006.168.08:06:08.37#ibcon#flushed, iclass 5, count 2 2006.168.08:06:08.37#ibcon#about to write, iclass 5, count 2 2006.168.08:06:08.37#ibcon#wrote, iclass 5, count 2 2006.168.08:06:08.37#ibcon#about to read 3, iclass 5, count 2 2006.168.08:06:08.40#ibcon#read 3, iclass 5, count 2 2006.168.08:06:08.40#ibcon#about to read 4, iclass 5, count 2 2006.168.08:06:08.40#ibcon#read 4, iclass 5, count 2 2006.168.08:06:08.40#ibcon#about to read 5, iclass 5, count 2 2006.168.08:06:08.40#ibcon#read 5, iclass 5, count 2 2006.168.08:06:08.40#ibcon#about to read 6, iclass 5, count 2 2006.168.08:06:08.40#ibcon#read 6, iclass 5, count 2 2006.168.08:06:08.40#ibcon#end of sib2, iclass 5, count 2 2006.168.08:06:08.40#ibcon#*after write, iclass 5, count 2 2006.168.08:06:08.40#ibcon#*before return 0, iclass 5, count 2 2006.168.08:06:08.40#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.168.08:06:08.40#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.168.08:06:08.40#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.168.08:06:08.40#ibcon#ireg 7 cls_cnt 0 2006.168.08:06:08.40#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.168.08:06:08.52#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.168.08:06:08.52#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.168.08:06:08.52#ibcon#enter wrdev, iclass 5, count 0 2006.168.08:06:08.52#ibcon#first serial, iclass 5, count 0 2006.168.08:06:08.52#ibcon#enter sib2, iclass 5, count 0 2006.168.08:06:08.52#ibcon#flushed, iclass 5, count 0 2006.168.08:06:08.52#ibcon#about to write, iclass 5, count 0 2006.168.08:06:08.52#ibcon#wrote, iclass 5, count 0 2006.168.08:06:08.52#ibcon#about to read 3, iclass 5, count 0 2006.168.08:06:08.54#ibcon#read 3, iclass 5, count 0 2006.168.08:06:08.54#ibcon#about to read 4, iclass 5, count 0 2006.168.08:06:08.54#ibcon#read 4, iclass 5, count 0 2006.168.08:06:08.54#ibcon#about to read 5, iclass 5, count 0 2006.168.08:06:08.54#ibcon#read 5, iclass 5, count 0 2006.168.08:06:08.54#ibcon#about to read 6, iclass 5, count 0 2006.168.08:06:08.54#ibcon#read 6, iclass 5, count 0 2006.168.08:06:08.54#ibcon#end of sib2, iclass 5, count 0 2006.168.08:06:08.54#ibcon#*mode == 0, iclass 5, count 0 2006.168.08:06:08.54#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.168.08:06:08.54#ibcon#[25=USB\r\n] 2006.168.08:06:08.54#ibcon#*before write, iclass 5, count 0 2006.168.08:06:08.54#ibcon#enter sib2, iclass 5, count 0 2006.168.08:06:08.54#ibcon#flushed, iclass 5, count 0 2006.168.08:06:08.54#ibcon#about to write, iclass 5, count 0 2006.168.08:06:08.54#ibcon#wrote, iclass 5, count 0 2006.168.08:06:08.54#ibcon#about to read 3, iclass 5, count 0 2006.168.08:06:08.57#ibcon#read 3, iclass 5, count 0 2006.168.08:06:08.57#ibcon#about to read 4, iclass 5, count 0 2006.168.08:06:08.57#ibcon#read 4, iclass 5, count 0 2006.168.08:06:08.57#ibcon#about to read 5, iclass 5, count 0 2006.168.08:06:08.57#ibcon#read 5, iclass 5, count 0 2006.168.08:06:08.57#ibcon#about to read 6, iclass 5, count 0 2006.168.08:06:08.57#ibcon#read 6, iclass 5, count 0 2006.168.08:06:08.57#ibcon#end of sib2, iclass 5, count 0 2006.168.08:06:08.57#ibcon#*after write, iclass 5, count 0 2006.168.08:06:08.57#ibcon#*before return 0, iclass 5, count 0 2006.168.08:06:08.57#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.168.08:06:08.57#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.168.08:06:08.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.168.08:06:08.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.168.08:06:08.57$vc4f8/valo=3,672.99 2006.168.08:06:08.57#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.168.08:06:08.57#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.168.08:06:08.57#ibcon#ireg 17 cls_cnt 0 2006.168.08:06:08.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.168.08:06:08.57#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.168.08:06:08.57#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.168.08:06:08.57#ibcon#enter wrdev, iclass 7, count 0 2006.168.08:06:08.57#ibcon#first serial, iclass 7, count 0 2006.168.08:06:08.57#ibcon#enter sib2, iclass 7, count 0 2006.168.08:06:08.57#ibcon#flushed, iclass 7, count 0 2006.168.08:06:08.57#ibcon#about to write, iclass 7, count 0 2006.168.08:06:08.57#ibcon#wrote, iclass 7, count 0 2006.168.08:06:08.57#ibcon#about to read 3, iclass 7, count 0 2006.168.08:06:08.59#ibcon#read 3, iclass 7, count 0 2006.168.08:06:08.59#ibcon#about to read 4, iclass 7, count 0 2006.168.08:06:08.59#ibcon#read 4, iclass 7, count 0 2006.168.08:06:08.59#ibcon#about to read 5, iclass 7, count 0 2006.168.08:06:08.59#ibcon#read 5, iclass 7, count 0 2006.168.08:06:08.59#ibcon#about to read 6, iclass 7, count 0 2006.168.08:06:08.59#ibcon#read 6, iclass 7, count 0 2006.168.08:06:08.59#ibcon#end of sib2, iclass 7, count 0 2006.168.08:06:08.59#ibcon#*mode == 0, iclass 7, count 0 2006.168.08:06:08.59#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.168.08:06:08.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.08:06:08.59#ibcon#*before write, iclass 7, count 0 2006.168.08:06:08.59#ibcon#enter sib2, iclass 7, count 0 2006.168.08:06:08.59#ibcon#flushed, iclass 7, count 0 2006.168.08:06:08.59#ibcon#about to write, iclass 7, count 0 2006.168.08:06:08.59#ibcon#wrote, iclass 7, count 0 2006.168.08:06:08.59#ibcon#about to read 3, iclass 7, count 0 2006.168.08:06:08.63#ibcon#read 3, iclass 7, count 0 2006.168.08:06:08.63#ibcon#about to read 4, iclass 7, count 0 2006.168.08:06:08.63#ibcon#read 4, iclass 7, count 0 2006.168.08:06:08.63#ibcon#about to read 5, iclass 7, count 0 2006.168.08:06:08.63#ibcon#read 5, iclass 7, count 0 2006.168.08:06:08.63#ibcon#about to read 6, iclass 7, count 0 2006.168.08:06:08.63#ibcon#read 6, iclass 7, count 0 2006.168.08:06:08.63#ibcon#end of sib2, iclass 7, count 0 2006.168.08:06:08.63#ibcon#*after write, iclass 7, count 0 2006.168.08:06:08.63#ibcon#*before return 0, iclass 7, count 0 2006.168.08:06:08.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.168.08:06:08.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.168.08:06:08.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.168.08:06:08.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.168.08:06:08.63$vc4f8/va=3,6 2006.168.08:06:08.63#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.168.08:06:08.63#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.168.08:06:08.63#ibcon#ireg 11 cls_cnt 2 2006.168.08:06:08.63#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.168.08:06:08.69#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.168.08:06:08.69#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.168.08:06:08.69#ibcon#enter wrdev, iclass 11, count 2 2006.168.08:06:08.69#ibcon#first serial, iclass 11, count 2 2006.168.08:06:08.69#ibcon#enter sib2, iclass 11, count 2 2006.168.08:06:08.69#ibcon#flushed, iclass 11, count 2 2006.168.08:06:08.69#ibcon#about to write, iclass 11, count 2 2006.168.08:06:08.69#ibcon#wrote, iclass 11, count 2 2006.168.08:06:08.69#ibcon#about to read 3, iclass 11, count 2 2006.168.08:06:08.71#ibcon#read 3, iclass 11, count 2 2006.168.08:06:08.71#ibcon#about to read 4, iclass 11, count 2 2006.168.08:06:08.71#ibcon#read 4, iclass 11, count 2 2006.168.08:06:08.71#ibcon#about to read 5, iclass 11, count 2 2006.168.08:06:08.71#ibcon#read 5, iclass 11, count 2 2006.168.08:06:08.71#ibcon#about to read 6, iclass 11, count 2 2006.168.08:06:08.71#ibcon#read 6, iclass 11, count 2 2006.168.08:06:08.71#ibcon#end of sib2, iclass 11, count 2 2006.168.08:06:08.71#ibcon#*mode == 0, iclass 11, count 2 2006.168.08:06:08.71#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.168.08:06:08.71#ibcon#[25=AT03-06\r\n] 2006.168.08:06:08.71#ibcon#*before write, iclass 11, count 2 2006.168.08:06:08.71#ibcon#enter sib2, iclass 11, count 2 2006.168.08:06:08.71#ibcon#flushed, iclass 11, count 2 2006.168.08:06:08.71#ibcon#about to write, iclass 11, count 2 2006.168.08:06:08.71#ibcon#wrote, iclass 11, count 2 2006.168.08:06:08.71#ibcon#about to read 3, iclass 11, count 2 2006.168.08:06:08.74#ibcon#read 3, iclass 11, count 2 2006.168.08:06:08.74#ibcon#about to read 4, iclass 11, count 2 2006.168.08:06:08.74#ibcon#read 4, iclass 11, count 2 2006.168.08:06:08.74#ibcon#about to read 5, iclass 11, count 2 2006.168.08:06:08.74#ibcon#read 5, iclass 11, count 2 2006.168.08:06:08.74#ibcon#about to read 6, iclass 11, count 2 2006.168.08:06:08.74#ibcon#read 6, iclass 11, count 2 2006.168.08:06:08.74#ibcon#end of sib2, iclass 11, count 2 2006.168.08:06:08.74#ibcon#*after write, iclass 11, count 2 2006.168.08:06:08.74#ibcon#*before return 0, iclass 11, count 2 2006.168.08:06:08.74#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.168.08:06:08.74#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.168.08:06:08.74#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.168.08:06:08.74#ibcon#ireg 7 cls_cnt 0 2006.168.08:06:08.74#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.168.08:06:08.86#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.168.08:06:08.86#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.168.08:06:08.86#ibcon#enter wrdev, iclass 11, count 0 2006.168.08:06:08.86#ibcon#first serial, iclass 11, count 0 2006.168.08:06:08.86#ibcon#enter sib2, iclass 11, count 0 2006.168.08:06:08.86#ibcon#flushed, iclass 11, count 0 2006.168.08:06:08.86#ibcon#about to write, iclass 11, count 0 2006.168.08:06:08.86#ibcon#wrote, iclass 11, count 0 2006.168.08:06:08.86#ibcon#about to read 3, iclass 11, count 0 2006.168.08:06:08.88#ibcon#read 3, iclass 11, count 0 2006.168.08:06:08.88#ibcon#about to read 4, iclass 11, count 0 2006.168.08:06:08.88#ibcon#read 4, iclass 11, count 0 2006.168.08:06:08.88#ibcon#about to read 5, iclass 11, count 0 2006.168.08:06:08.88#ibcon#read 5, iclass 11, count 0 2006.168.08:06:08.88#ibcon#about to read 6, iclass 11, count 0 2006.168.08:06:08.88#ibcon#read 6, iclass 11, count 0 2006.168.08:06:08.88#ibcon#end of sib2, iclass 11, count 0 2006.168.08:06:08.88#ibcon#*mode == 0, iclass 11, count 0 2006.168.08:06:08.88#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.168.08:06:08.88#ibcon#[25=USB\r\n] 2006.168.08:06:08.88#ibcon#*before write, iclass 11, count 0 2006.168.08:06:08.88#ibcon#enter sib2, iclass 11, count 0 2006.168.08:06:08.88#ibcon#flushed, iclass 11, count 0 2006.168.08:06:08.88#ibcon#about to write, iclass 11, count 0 2006.168.08:06:08.88#ibcon#wrote, iclass 11, count 0 2006.168.08:06:08.88#ibcon#about to read 3, iclass 11, count 0 2006.168.08:06:08.91#ibcon#read 3, iclass 11, count 0 2006.168.08:06:08.91#ibcon#about to read 4, iclass 11, count 0 2006.168.08:06:08.91#ibcon#read 4, iclass 11, count 0 2006.168.08:06:08.91#ibcon#about to read 5, iclass 11, count 0 2006.168.08:06:08.91#ibcon#read 5, iclass 11, count 0 2006.168.08:06:08.91#ibcon#about to read 6, iclass 11, count 0 2006.168.08:06:08.91#ibcon#read 6, iclass 11, count 0 2006.168.08:06:08.91#ibcon#end of sib2, iclass 11, count 0 2006.168.08:06:08.91#ibcon#*after write, iclass 11, count 0 2006.168.08:06:08.91#ibcon#*before return 0, iclass 11, count 0 2006.168.08:06:08.91#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.168.08:06:08.91#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.168.08:06:08.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.168.08:06:08.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.168.08:06:08.91$vc4f8/valo=4,832.99 2006.168.08:06:08.91#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.168.08:06:08.91#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.168.08:06:08.91#ibcon#ireg 17 cls_cnt 0 2006.168.08:06:08.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.168.08:06:08.91#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.168.08:06:08.91#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.168.08:06:08.91#ibcon#enter wrdev, iclass 13, count 0 2006.168.08:06:08.91#ibcon#first serial, iclass 13, count 0 2006.168.08:06:08.91#ibcon#enter sib2, iclass 13, count 0 2006.168.08:06:08.91#ibcon#flushed, iclass 13, count 0 2006.168.08:06:08.91#ibcon#about to write, iclass 13, count 0 2006.168.08:06:08.91#ibcon#wrote, iclass 13, count 0 2006.168.08:06:08.91#ibcon#about to read 3, iclass 13, count 0 2006.168.08:06:08.93#ibcon#read 3, iclass 13, count 0 2006.168.08:06:08.93#ibcon#about to read 4, iclass 13, count 0 2006.168.08:06:08.93#ibcon#read 4, iclass 13, count 0 2006.168.08:06:08.93#ibcon#about to read 5, iclass 13, count 0 2006.168.08:06:08.93#ibcon#read 5, iclass 13, count 0 2006.168.08:06:08.93#ibcon#about to read 6, iclass 13, count 0 2006.168.08:06:08.93#ibcon#read 6, iclass 13, count 0 2006.168.08:06:08.93#ibcon#end of sib2, iclass 13, count 0 2006.168.08:06:08.93#ibcon#*mode == 0, iclass 13, count 0 2006.168.08:06:08.93#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.168.08:06:08.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.08:06:08.93#ibcon#*before write, iclass 13, count 0 2006.168.08:06:08.93#ibcon#enter sib2, iclass 13, count 0 2006.168.08:06:08.93#ibcon#flushed, iclass 13, count 0 2006.168.08:06:08.93#ibcon#about to write, iclass 13, count 0 2006.168.08:06:08.93#ibcon#wrote, iclass 13, count 0 2006.168.08:06:08.93#ibcon#about to read 3, iclass 13, count 0 2006.168.08:06:08.97#ibcon#read 3, iclass 13, count 0 2006.168.08:06:08.97#ibcon#about to read 4, iclass 13, count 0 2006.168.08:06:08.97#ibcon#read 4, iclass 13, count 0 2006.168.08:06:08.97#ibcon#about to read 5, iclass 13, count 0 2006.168.08:06:08.97#ibcon#read 5, iclass 13, count 0 2006.168.08:06:08.97#ibcon#about to read 6, iclass 13, count 0 2006.168.08:06:08.97#ibcon#read 6, iclass 13, count 0 2006.168.08:06:08.97#ibcon#end of sib2, iclass 13, count 0 2006.168.08:06:08.97#ibcon#*after write, iclass 13, count 0 2006.168.08:06:08.97#ibcon#*before return 0, iclass 13, count 0 2006.168.08:06:08.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.168.08:06:08.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.168.08:06:08.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.168.08:06:08.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.168.08:06:08.97$vc4f8/va=4,7 2006.168.08:06:08.97#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.168.08:06:08.97#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.168.08:06:08.97#ibcon#ireg 11 cls_cnt 2 2006.168.08:06:08.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.168.08:06:09.03#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.168.08:06:09.03#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.168.08:06:09.03#ibcon#enter wrdev, iclass 15, count 2 2006.168.08:06:09.03#ibcon#first serial, iclass 15, count 2 2006.168.08:06:09.03#ibcon#enter sib2, iclass 15, count 2 2006.168.08:06:09.03#ibcon#flushed, iclass 15, count 2 2006.168.08:06:09.03#ibcon#about to write, iclass 15, count 2 2006.168.08:06:09.03#ibcon#wrote, iclass 15, count 2 2006.168.08:06:09.03#ibcon#about to read 3, iclass 15, count 2 2006.168.08:06:09.05#ibcon#read 3, iclass 15, count 2 2006.168.08:06:09.05#ibcon#about to read 4, iclass 15, count 2 2006.168.08:06:09.05#ibcon#read 4, iclass 15, count 2 2006.168.08:06:09.05#ibcon#about to read 5, iclass 15, count 2 2006.168.08:06:09.05#ibcon#read 5, iclass 15, count 2 2006.168.08:06:09.05#ibcon#about to read 6, iclass 15, count 2 2006.168.08:06:09.05#ibcon#read 6, iclass 15, count 2 2006.168.08:06:09.05#ibcon#end of sib2, iclass 15, count 2 2006.168.08:06:09.05#ibcon#*mode == 0, iclass 15, count 2 2006.168.08:06:09.05#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.168.08:06:09.05#ibcon#[25=AT04-07\r\n] 2006.168.08:06:09.05#ibcon#*before write, iclass 15, count 2 2006.168.08:06:09.05#ibcon#enter sib2, iclass 15, count 2 2006.168.08:06:09.05#ibcon#flushed, iclass 15, count 2 2006.168.08:06:09.05#ibcon#about to write, iclass 15, count 2 2006.168.08:06:09.05#ibcon#wrote, iclass 15, count 2 2006.168.08:06:09.05#ibcon#about to read 3, iclass 15, count 2 2006.168.08:06:09.08#ibcon#read 3, iclass 15, count 2 2006.168.08:06:09.08#ibcon#about to read 4, iclass 15, count 2 2006.168.08:06:09.08#ibcon#read 4, iclass 15, count 2 2006.168.08:06:09.08#ibcon#about to read 5, iclass 15, count 2 2006.168.08:06:09.08#ibcon#read 5, iclass 15, count 2 2006.168.08:06:09.08#ibcon#about to read 6, iclass 15, count 2 2006.168.08:06:09.08#ibcon#read 6, iclass 15, count 2 2006.168.08:06:09.08#ibcon#end of sib2, iclass 15, count 2 2006.168.08:06:09.08#ibcon#*after write, iclass 15, count 2 2006.168.08:06:09.08#ibcon#*before return 0, iclass 15, count 2 2006.168.08:06:09.08#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.168.08:06:09.08#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.168.08:06:09.08#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.168.08:06:09.08#ibcon#ireg 7 cls_cnt 0 2006.168.08:06:09.08#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.168.08:06:09.20#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.168.08:06:09.20#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.168.08:06:09.20#ibcon#enter wrdev, iclass 15, count 0 2006.168.08:06:09.20#ibcon#first serial, iclass 15, count 0 2006.168.08:06:09.20#ibcon#enter sib2, iclass 15, count 0 2006.168.08:06:09.20#ibcon#flushed, iclass 15, count 0 2006.168.08:06:09.20#ibcon#about to write, iclass 15, count 0 2006.168.08:06:09.20#ibcon#wrote, iclass 15, count 0 2006.168.08:06:09.20#ibcon#about to read 3, iclass 15, count 0 2006.168.08:06:09.22#ibcon#read 3, iclass 15, count 0 2006.168.08:06:09.22#ibcon#about to read 4, iclass 15, count 0 2006.168.08:06:09.22#ibcon#read 4, iclass 15, count 0 2006.168.08:06:09.22#ibcon#about to read 5, iclass 15, count 0 2006.168.08:06:09.22#ibcon#read 5, iclass 15, count 0 2006.168.08:06:09.22#ibcon#about to read 6, iclass 15, count 0 2006.168.08:06:09.22#ibcon#read 6, iclass 15, count 0 2006.168.08:06:09.22#ibcon#end of sib2, iclass 15, count 0 2006.168.08:06:09.22#ibcon#*mode == 0, iclass 15, count 0 2006.168.08:06:09.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.168.08:06:09.22#ibcon#[25=USB\r\n] 2006.168.08:06:09.22#ibcon#*before write, iclass 15, count 0 2006.168.08:06:09.22#ibcon#enter sib2, iclass 15, count 0 2006.168.08:06:09.22#ibcon#flushed, iclass 15, count 0 2006.168.08:06:09.22#ibcon#about to write, iclass 15, count 0 2006.168.08:06:09.22#ibcon#wrote, iclass 15, count 0 2006.168.08:06:09.22#ibcon#about to read 3, iclass 15, count 0 2006.168.08:06:09.25#ibcon#read 3, iclass 15, count 0 2006.168.08:06:09.25#ibcon#about to read 4, iclass 15, count 0 2006.168.08:06:09.25#ibcon#read 4, iclass 15, count 0 2006.168.08:06:09.25#ibcon#about to read 5, iclass 15, count 0 2006.168.08:06:09.25#ibcon#read 5, iclass 15, count 0 2006.168.08:06:09.25#ibcon#about to read 6, iclass 15, count 0 2006.168.08:06:09.25#ibcon#read 6, iclass 15, count 0 2006.168.08:06:09.25#ibcon#end of sib2, iclass 15, count 0 2006.168.08:06:09.25#ibcon#*after write, iclass 15, count 0 2006.168.08:06:09.25#ibcon#*before return 0, iclass 15, count 0 2006.168.08:06:09.25#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.168.08:06:09.25#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.168.08:06:09.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.168.08:06:09.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.168.08:06:09.25$vc4f8/valo=5,652.99 2006.168.08:06:09.25#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.168.08:06:09.25#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.168.08:06:09.25#ibcon#ireg 17 cls_cnt 0 2006.168.08:06:09.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:06:09.25#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:06:09.25#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:06:09.25#ibcon#enter wrdev, iclass 17, count 0 2006.168.08:06:09.25#ibcon#first serial, iclass 17, count 0 2006.168.08:06:09.25#ibcon#enter sib2, iclass 17, count 0 2006.168.08:06:09.25#ibcon#flushed, iclass 17, count 0 2006.168.08:06:09.25#ibcon#about to write, iclass 17, count 0 2006.168.08:06:09.25#ibcon#wrote, iclass 17, count 0 2006.168.08:06:09.25#ibcon#about to read 3, iclass 17, count 0 2006.168.08:06:09.27#ibcon#read 3, iclass 17, count 0 2006.168.08:06:09.27#ibcon#about to read 4, iclass 17, count 0 2006.168.08:06:09.27#ibcon#read 4, iclass 17, count 0 2006.168.08:06:09.27#ibcon#about to read 5, iclass 17, count 0 2006.168.08:06:09.27#ibcon#read 5, iclass 17, count 0 2006.168.08:06:09.27#ibcon#about to read 6, iclass 17, count 0 2006.168.08:06:09.27#ibcon#read 6, iclass 17, count 0 2006.168.08:06:09.27#ibcon#end of sib2, iclass 17, count 0 2006.168.08:06:09.27#ibcon#*mode == 0, iclass 17, count 0 2006.168.08:06:09.27#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.168.08:06:09.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.08:06:09.27#ibcon#*before write, iclass 17, count 0 2006.168.08:06:09.27#ibcon#enter sib2, iclass 17, count 0 2006.168.08:06:09.27#ibcon#flushed, iclass 17, count 0 2006.168.08:06:09.27#ibcon#about to write, iclass 17, count 0 2006.168.08:06:09.27#ibcon#wrote, iclass 17, count 0 2006.168.08:06:09.27#ibcon#about to read 3, iclass 17, count 0 2006.168.08:06:09.31#ibcon#read 3, iclass 17, count 0 2006.168.08:06:09.31#ibcon#about to read 4, iclass 17, count 0 2006.168.08:06:09.31#ibcon#read 4, iclass 17, count 0 2006.168.08:06:09.31#ibcon#about to read 5, iclass 17, count 0 2006.168.08:06:09.31#ibcon#read 5, iclass 17, count 0 2006.168.08:06:09.31#ibcon#about to read 6, iclass 17, count 0 2006.168.08:06:09.31#ibcon#read 6, iclass 17, count 0 2006.168.08:06:09.31#ibcon#end of sib2, iclass 17, count 0 2006.168.08:06:09.31#ibcon#*after write, iclass 17, count 0 2006.168.08:06:09.31#ibcon#*before return 0, iclass 17, count 0 2006.168.08:06:09.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:06:09.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:06:09.31#ibcon#about to clear, iclass 17 cls_cnt 0 2006.168.08:06:09.31#ibcon#cleared, iclass 17 cls_cnt 0 2006.168.08:06:09.31$vc4f8/va=5,7 2006.168.08:06:09.31#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.168.08:06:09.31#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.168.08:06:09.31#ibcon#ireg 11 cls_cnt 2 2006.168.08:06:09.31#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:06:09.37#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:06:09.37#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:06:09.37#ibcon#enter wrdev, iclass 19, count 2 2006.168.08:06:09.37#ibcon#first serial, iclass 19, count 2 2006.168.08:06:09.37#ibcon#enter sib2, iclass 19, count 2 2006.168.08:06:09.37#ibcon#flushed, iclass 19, count 2 2006.168.08:06:09.37#ibcon#about to write, iclass 19, count 2 2006.168.08:06:09.37#ibcon#wrote, iclass 19, count 2 2006.168.08:06:09.37#ibcon#about to read 3, iclass 19, count 2 2006.168.08:06:09.39#ibcon#read 3, iclass 19, count 2 2006.168.08:06:09.39#ibcon#about to read 4, iclass 19, count 2 2006.168.08:06:09.39#ibcon#read 4, iclass 19, count 2 2006.168.08:06:09.39#ibcon#about to read 5, iclass 19, count 2 2006.168.08:06:09.39#ibcon#read 5, iclass 19, count 2 2006.168.08:06:09.39#ibcon#about to read 6, iclass 19, count 2 2006.168.08:06:09.39#ibcon#read 6, iclass 19, count 2 2006.168.08:06:09.39#ibcon#end of sib2, iclass 19, count 2 2006.168.08:06:09.39#ibcon#*mode == 0, iclass 19, count 2 2006.168.08:06:09.39#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.168.08:06:09.39#ibcon#[25=AT05-07\r\n] 2006.168.08:06:09.39#ibcon#*before write, iclass 19, count 2 2006.168.08:06:09.39#ibcon#enter sib2, iclass 19, count 2 2006.168.08:06:09.39#ibcon#flushed, iclass 19, count 2 2006.168.08:06:09.39#ibcon#about to write, iclass 19, count 2 2006.168.08:06:09.39#ibcon#wrote, iclass 19, count 2 2006.168.08:06:09.39#ibcon#about to read 3, iclass 19, count 2 2006.168.08:06:09.42#ibcon#read 3, iclass 19, count 2 2006.168.08:06:09.42#ibcon#about to read 4, iclass 19, count 2 2006.168.08:06:09.42#ibcon#read 4, iclass 19, count 2 2006.168.08:06:09.42#ibcon#about to read 5, iclass 19, count 2 2006.168.08:06:09.42#ibcon#read 5, iclass 19, count 2 2006.168.08:06:09.42#ibcon#about to read 6, iclass 19, count 2 2006.168.08:06:09.42#ibcon#read 6, iclass 19, count 2 2006.168.08:06:09.42#ibcon#end of sib2, iclass 19, count 2 2006.168.08:06:09.42#ibcon#*after write, iclass 19, count 2 2006.168.08:06:09.42#ibcon#*before return 0, iclass 19, count 2 2006.168.08:06:09.42#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:06:09.42#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:06:09.42#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.168.08:06:09.42#ibcon#ireg 7 cls_cnt 0 2006.168.08:06:09.42#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:06:09.55#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:06:09.55#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:06:09.55#ibcon#enter wrdev, iclass 19, count 0 2006.168.08:06:09.55#ibcon#first serial, iclass 19, count 0 2006.168.08:06:09.55#ibcon#enter sib2, iclass 19, count 0 2006.168.08:06:09.55#ibcon#flushed, iclass 19, count 0 2006.168.08:06:09.55#ibcon#about to write, iclass 19, count 0 2006.168.08:06:09.55#ibcon#wrote, iclass 19, count 0 2006.168.08:06:09.55#ibcon#about to read 3, iclass 19, count 0 2006.168.08:06:09.57#ibcon#read 3, iclass 19, count 0 2006.168.08:06:09.57#ibcon#about to read 4, iclass 19, count 0 2006.168.08:06:09.57#ibcon#read 4, iclass 19, count 0 2006.168.08:06:09.57#ibcon#about to read 5, iclass 19, count 0 2006.168.08:06:09.57#ibcon#read 5, iclass 19, count 0 2006.168.08:06:09.57#ibcon#about to read 6, iclass 19, count 0 2006.168.08:06:09.57#ibcon#read 6, iclass 19, count 0 2006.168.08:06:09.57#ibcon#end of sib2, iclass 19, count 0 2006.168.08:06:09.57#ibcon#*mode == 0, iclass 19, count 0 2006.168.08:06:09.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.168.08:06:09.57#ibcon#[25=USB\r\n] 2006.168.08:06:09.57#ibcon#*before write, iclass 19, count 0 2006.168.08:06:09.57#ibcon#enter sib2, iclass 19, count 0 2006.168.08:06:09.57#ibcon#flushed, iclass 19, count 0 2006.168.08:06:09.57#ibcon#about to write, iclass 19, count 0 2006.168.08:06:09.57#ibcon#wrote, iclass 19, count 0 2006.168.08:06:09.57#ibcon#about to read 3, iclass 19, count 0 2006.168.08:06:09.60#ibcon#read 3, iclass 19, count 0 2006.168.08:06:09.60#ibcon#about to read 4, iclass 19, count 0 2006.168.08:06:09.60#ibcon#read 4, iclass 19, count 0 2006.168.08:06:09.60#ibcon#about to read 5, iclass 19, count 0 2006.168.08:06:09.60#ibcon#read 5, iclass 19, count 0 2006.168.08:06:09.60#ibcon#about to read 6, iclass 19, count 0 2006.168.08:06:09.60#ibcon#read 6, iclass 19, count 0 2006.168.08:06:09.60#ibcon#end of sib2, iclass 19, count 0 2006.168.08:06:09.60#ibcon#*after write, iclass 19, count 0 2006.168.08:06:09.60#ibcon#*before return 0, iclass 19, count 0 2006.168.08:06:09.60#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:06:09.60#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:06:09.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.168.08:06:09.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.168.08:06:09.60$vc4f8/valo=6,772.99 2006.168.08:06:09.60#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.168.08:06:09.60#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.168.08:06:09.60#ibcon#ireg 17 cls_cnt 0 2006.168.08:06:09.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:06:09.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:06:09.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:06:09.60#ibcon#enter wrdev, iclass 21, count 0 2006.168.08:06:09.60#ibcon#first serial, iclass 21, count 0 2006.168.08:06:09.60#ibcon#enter sib2, iclass 21, count 0 2006.168.08:06:09.60#ibcon#flushed, iclass 21, count 0 2006.168.08:06:09.60#ibcon#about to write, iclass 21, count 0 2006.168.08:06:09.60#ibcon#wrote, iclass 21, count 0 2006.168.08:06:09.60#ibcon#about to read 3, iclass 21, count 0 2006.168.08:06:09.62#ibcon#read 3, iclass 21, count 0 2006.168.08:06:09.62#ibcon#about to read 4, iclass 21, count 0 2006.168.08:06:09.62#ibcon#read 4, iclass 21, count 0 2006.168.08:06:09.62#ibcon#about to read 5, iclass 21, count 0 2006.168.08:06:09.62#ibcon#read 5, iclass 21, count 0 2006.168.08:06:09.62#ibcon#about to read 6, iclass 21, count 0 2006.168.08:06:09.62#ibcon#read 6, iclass 21, count 0 2006.168.08:06:09.62#ibcon#end of sib2, iclass 21, count 0 2006.168.08:06:09.62#ibcon#*mode == 0, iclass 21, count 0 2006.168.08:06:09.62#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.168.08:06:09.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.08:06:09.62#ibcon#*before write, iclass 21, count 0 2006.168.08:06:09.62#ibcon#enter sib2, iclass 21, count 0 2006.168.08:06:09.62#ibcon#flushed, iclass 21, count 0 2006.168.08:06:09.62#ibcon#about to write, iclass 21, count 0 2006.168.08:06:09.62#ibcon#wrote, iclass 21, count 0 2006.168.08:06:09.62#ibcon#about to read 3, iclass 21, count 0 2006.168.08:06:09.66#ibcon#read 3, iclass 21, count 0 2006.168.08:06:09.66#ibcon#about to read 4, iclass 21, count 0 2006.168.08:06:09.66#ibcon#read 4, iclass 21, count 0 2006.168.08:06:09.66#ibcon#about to read 5, iclass 21, count 0 2006.168.08:06:09.66#ibcon#read 5, iclass 21, count 0 2006.168.08:06:09.66#ibcon#about to read 6, iclass 21, count 0 2006.168.08:06:09.66#ibcon#read 6, iclass 21, count 0 2006.168.08:06:09.66#ibcon#end of sib2, iclass 21, count 0 2006.168.08:06:09.66#ibcon#*after write, iclass 21, count 0 2006.168.08:06:09.66#ibcon#*before return 0, iclass 21, count 0 2006.168.08:06:09.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:06:09.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:06:09.66#ibcon#about to clear, iclass 21 cls_cnt 0 2006.168.08:06:09.66#ibcon#cleared, iclass 21 cls_cnt 0 2006.168.08:06:09.66$vc4f8/va=6,6 2006.168.08:06:09.66#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.168.08:06:09.66#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.168.08:06:09.66#ibcon#ireg 11 cls_cnt 2 2006.168.08:06:09.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.168.08:06:09.72#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.168.08:06:09.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.168.08:06:09.72#ibcon#enter wrdev, iclass 23, count 2 2006.168.08:06:09.72#ibcon#first serial, iclass 23, count 2 2006.168.08:06:09.72#ibcon#enter sib2, iclass 23, count 2 2006.168.08:06:09.72#ibcon#flushed, iclass 23, count 2 2006.168.08:06:09.72#ibcon#about to write, iclass 23, count 2 2006.168.08:06:09.72#ibcon#wrote, iclass 23, count 2 2006.168.08:06:09.72#ibcon#about to read 3, iclass 23, count 2 2006.168.08:06:09.74#ibcon#read 3, iclass 23, count 2 2006.168.08:06:09.74#ibcon#about to read 4, iclass 23, count 2 2006.168.08:06:09.74#ibcon#read 4, iclass 23, count 2 2006.168.08:06:09.74#ibcon#about to read 5, iclass 23, count 2 2006.168.08:06:09.74#ibcon#read 5, iclass 23, count 2 2006.168.08:06:09.74#ibcon#about to read 6, iclass 23, count 2 2006.168.08:06:09.74#ibcon#read 6, iclass 23, count 2 2006.168.08:06:09.74#ibcon#end of sib2, iclass 23, count 2 2006.168.08:06:09.74#ibcon#*mode == 0, iclass 23, count 2 2006.168.08:06:09.74#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.168.08:06:09.74#ibcon#[25=AT06-06\r\n] 2006.168.08:06:09.74#ibcon#*before write, iclass 23, count 2 2006.168.08:06:09.74#ibcon#enter sib2, iclass 23, count 2 2006.168.08:06:09.74#ibcon#flushed, iclass 23, count 2 2006.168.08:06:09.74#ibcon#about to write, iclass 23, count 2 2006.168.08:06:09.74#ibcon#wrote, iclass 23, count 2 2006.168.08:06:09.74#ibcon#about to read 3, iclass 23, count 2 2006.168.08:06:09.77#ibcon#read 3, iclass 23, count 2 2006.168.08:06:09.77#ibcon#about to read 4, iclass 23, count 2 2006.168.08:06:09.77#ibcon#read 4, iclass 23, count 2 2006.168.08:06:09.77#ibcon#about to read 5, iclass 23, count 2 2006.168.08:06:09.77#ibcon#read 5, iclass 23, count 2 2006.168.08:06:09.77#ibcon#about to read 6, iclass 23, count 2 2006.168.08:06:09.77#ibcon#read 6, iclass 23, count 2 2006.168.08:06:09.77#ibcon#end of sib2, iclass 23, count 2 2006.168.08:06:09.77#ibcon#*after write, iclass 23, count 2 2006.168.08:06:09.77#ibcon#*before return 0, iclass 23, count 2 2006.168.08:06:09.77#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.168.08:06:09.77#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.168.08:06:09.77#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.168.08:06:09.77#ibcon#ireg 7 cls_cnt 0 2006.168.08:06:09.77#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.168.08:06:09.89#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.168.08:06:09.89#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.168.08:06:09.89#ibcon#enter wrdev, iclass 23, count 0 2006.168.08:06:09.89#ibcon#first serial, iclass 23, count 0 2006.168.08:06:09.89#ibcon#enter sib2, iclass 23, count 0 2006.168.08:06:09.89#ibcon#flushed, iclass 23, count 0 2006.168.08:06:09.89#ibcon#about to write, iclass 23, count 0 2006.168.08:06:09.89#ibcon#wrote, iclass 23, count 0 2006.168.08:06:09.89#ibcon#about to read 3, iclass 23, count 0 2006.168.08:06:09.91#ibcon#read 3, iclass 23, count 0 2006.168.08:06:09.91#ibcon#about to read 4, iclass 23, count 0 2006.168.08:06:09.91#ibcon#read 4, iclass 23, count 0 2006.168.08:06:09.91#ibcon#about to read 5, iclass 23, count 0 2006.168.08:06:09.91#ibcon#read 5, iclass 23, count 0 2006.168.08:06:09.91#ibcon#about to read 6, iclass 23, count 0 2006.168.08:06:09.91#ibcon#read 6, iclass 23, count 0 2006.168.08:06:09.91#ibcon#end of sib2, iclass 23, count 0 2006.168.08:06:09.91#ibcon#*mode == 0, iclass 23, count 0 2006.168.08:06:09.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.168.08:06:09.91#ibcon#[25=USB\r\n] 2006.168.08:06:09.91#ibcon#*before write, iclass 23, count 0 2006.168.08:06:09.91#ibcon#enter sib2, iclass 23, count 0 2006.168.08:06:09.91#ibcon#flushed, iclass 23, count 0 2006.168.08:06:09.91#ibcon#about to write, iclass 23, count 0 2006.168.08:06:09.91#ibcon#wrote, iclass 23, count 0 2006.168.08:06:09.91#ibcon#about to read 3, iclass 23, count 0 2006.168.08:06:09.94#ibcon#read 3, iclass 23, count 0 2006.168.08:06:09.94#ibcon#about to read 4, iclass 23, count 0 2006.168.08:06:09.94#ibcon#read 4, iclass 23, count 0 2006.168.08:06:09.94#ibcon#about to read 5, iclass 23, count 0 2006.168.08:06:09.94#ibcon#read 5, iclass 23, count 0 2006.168.08:06:09.94#ibcon#about to read 6, iclass 23, count 0 2006.168.08:06:09.94#ibcon#read 6, iclass 23, count 0 2006.168.08:06:09.94#ibcon#end of sib2, iclass 23, count 0 2006.168.08:06:09.94#ibcon#*after write, iclass 23, count 0 2006.168.08:06:09.94#ibcon#*before return 0, iclass 23, count 0 2006.168.08:06:09.94#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.168.08:06:09.94#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.168.08:06:09.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.168.08:06:09.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.168.08:06:09.94$vc4f8/valo=7,832.99 2006.168.08:06:09.94#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.168.08:06:09.94#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.168.08:06:09.94#ibcon#ireg 17 cls_cnt 0 2006.168.08:06:09.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.168.08:06:09.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.168.08:06:09.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.168.08:06:09.94#ibcon#enter wrdev, iclass 25, count 0 2006.168.08:06:09.94#ibcon#first serial, iclass 25, count 0 2006.168.08:06:09.94#ibcon#enter sib2, iclass 25, count 0 2006.168.08:06:09.94#ibcon#flushed, iclass 25, count 0 2006.168.08:06:09.94#ibcon#about to write, iclass 25, count 0 2006.168.08:06:09.94#ibcon#wrote, iclass 25, count 0 2006.168.08:06:09.94#ibcon#about to read 3, iclass 25, count 0 2006.168.08:06:09.96#ibcon#read 3, iclass 25, count 0 2006.168.08:06:09.96#ibcon#about to read 4, iclass 25, count 0 2006.168.08:06:09.96#ibcon#read 4, iclass 25, count 0 2006.168.08:06:09.96#ibcon#about to read 5, iclass 25, count 0 2006.168.08:06:09.96#ibcon#read 5, iclass 25, count 0 2006.168.08:06:09.96#ibcon#about to read 6, iclass 25, count 0 2006.168.08:06:09.96#ibcon#read 6, iclass 25, count 0 2006.168.08:06:09.96#ibcon#end of sib2, iclass 25, count 0 2006.168.08:06:09.96#ibcon#*mode == 0, iclass 25, count 0 2006.168.08:06:09.96#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.168.08:06:09.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.08:06:09.96#ibcon#*before write, iclass 25, count 0 2006.168.08:06:09.96#ibcon#enter sib2, iclass 25, count 0 2006.168.08:06:09.96#ibcon#flushed, iclass 25, count 0 2006.168.08:06:09.96#ibcon#about to write, iclass 25, count 0 2006.168.08:06:09.96#ibcon#wrote, iclass 25, count 0 2006.168.08:06:09.96#ibcon#about to read 3, iclass 25, count 0 2006.168.08:06:10.00#ibcon#read 3, iclass 25, count 0 2006.168.08:06:10.00#ibcon#about to read 4, iclass 25, count 0 2006.168.08:06:10.00#ibcon#read 4, iclass 25, count 0 2006.168.08:06:10.00#ibcon#about to read 5, iclass 25, count 0 2006.168.08:06:10.00#ibcon#read 5, iclass 25, count 0 2006.168.08:06:10.00#ibcon#about to read 6, iclass 25, count 0 2006.168.08:06:10.00#ibcon#read 6, iclass 25, count 0 2006.168.08:06:10.00#ibcon#end of sib2, iclass 25, count 0 2006.168.08:06:10.00#ibcon#*after write, iclass 25, count 0 2006.168.08:06:10.00#ibcon#*before return 0, iclass 25, count 0 2006.168.08:06:10.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.168.08:06:10.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.168.08:06:10.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.168.08:06:10.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.168.08:06:10.00$vc4f8/va=7,6 2006.168.08:06:10.00#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.168.08:06:10.00#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.168.08:06:10.00#ibcon#ireg 11 cls_cnt 2 2006.168.08:06:10.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.168.08:06:10.06#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.168.08:06:10.06#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.168.08:06:10.06#ibcon#enter wrdev, iclass 27, count 2 2006.168.08:06:10.06#ibcon#first serial, iclass 27, count 2 2006.168.08:06:10.06#ibcon#enter sib2, iclass 27, count 2 2006.168.08:06:10.06#ibcon#flushed, iclass 27, count 2 2006.168.08:06:10.06#ibcon#about to write, iclass 27, count 2 2006.168.08:06:10.06#ibcon#wrote, iclass 27, count 2 2006.168.08:06:10.06#ibcon#about to read 3, iclass 27, count 2 2006.168.08:06:10.08#ibcon#read 3, iclass 27, count 2 2006.168.08:06:10.08#ibcon#about to read 4, iclass 27, count 2 2006.168.08:06:10.08#ibcon#read 4, iclass 27, count 2 2006.168.08:06:10.08#ibcon#about to read 5, iclass 27, count 2 2006.168.08:06:10.08#ibcon#read 5, iclass 27, count 2 2006.168.08:06:10.08#ibcon#about to read 6, iclass 27, count 2 2006.168.08:06:10.08#ibcon#read 6, iclass 27, count 2 2006.168.08:06:10.08#ibcon#end of sib2, iclass 27, count 2 2006.168.08:06:10.08#ibcon#*mode == 0, iclass 27, count 2 2006.168.08:06:10.08#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.168.08:06:10.08#ibcon#[25=AT07-06\r\n] 2006.168.08:06:10.08#ibcon#*before write, iclass 27, count 2 2006.168.08:06:10.08#ibcon#enter sib2, iclass 27, count 2 2006.168.08:06:10.08#ibcon#flushed, iclass 27, count 2 2006.168.08:06:10.08#ibcon#about to write, iclass 27, count 2 2006.168.08:06:10.08#ibcon#wrote, iclass 27, count 2 2006.168.08:06:10.08#ibcon#about to read 3, iclass 27, count 2 2006.168.08:06:10.11#ibcon#read 3, iclass 27, count 2 2006.168.08:06:10.11#ibcon#about to read 4, iclass 27, count 2 2006.168.08:06:10.11#ibcon#read 4, iclass 27, count 2 2006.168.08:06:10.11#ibcon#about to read 5, iclass 27, count 2 2006.168.08:06:10.11#ibcon#read 5, iclass 27, count 2 2006.168.08:06:10.11#ibcon#about to read 6, iclass 27, count 2 2006.168.08:06:10.11#ibcon#read 6, iclass 27, count 2 2006.168.08:06:10.11#ibcon#end of sib2, iclass 27, count 2 2006.168.08:06:10.11#ibcon#*after write, iclass 27, count 2 2006.168.08:06:10.11#ibcon#*before return 0, iclass 27, count 2 2006.168.08:06:10.11#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.168.08:06:10.11#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.168.08:06:10.11#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.168.08:06:10.11#ibcon#ireg 7 cls_cnt 0 2006.168.08:06:10.11#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.168.08:06:10.23#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.168.08:06:10.23#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.168.08:06:10.23#ibcon#enter wrdev, iclass 27, count 0 2006.168.08:06:10.23#ibcon#first serial, iclass 27, count 0 2006.168.08:06:10.23#ibcon#enter sib2, iclass 27, count 0 2006.168.08:06:10.23#ibcon#flushed, iclass 27, count 0 2006.168.08:06:10.23#ibcon#about to write, iclass 27, count 0 2006.168.08:06:10.23#ibcon#wrote, iclass 27, count 0 2006.168.08:06:10.23#ibcon#about to read 3, iclass 27, count 0 2006.168.08:06:10.25#ibcon#read 3, iclass 27, count 0 2006.168.08:06:10.25#ibcon#about to read 4, iclass 27, count 0 2006.168.08:06:10.25#ibcon#read 4, iclass 27, count 0 2006.168.08:06:10.25#ibcon#about to read 5, iclass 27, count 0 2006.168.08:06:10.25#ibcon#read 5, iclass 27, count 0 2006.168.08:06:10.25#ibcon#about to read 6, iclass 27, count 0 2006.168.08:06:10.25#ibcon#read 6, iclass 27, count 0 2006.168.08:06:10.25#ibcon#end of sib2, iclass 27, count 0 2006.168.08:06:10.25#ibcon#*mode == 0, iclass 27, count 0 2006.168.08:06:10.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.168.08:06:10.25#ibcon#[25=USB\r\n] 2006.168.08:06:10.25#ibcon#*before write, iclass 27, count 0 2006.168.08:06:10.25#ibcon#enter sib2, iclass 27, count 0 2006.168.08:06:10.25#ibcon#flushed, iclass 27, count 0 2006.168.08:06:10.25#ibcon#about to write, iclass 27, count 0 2006.168.08:06:10.25#ibcon#wrote, iclass 27, count 0 2006.168.08:06:10.25#ibcon#about to read 3, iclass 27, count 0 2006.168.08:06:10.28#ibcon#read 3, iclass 27, count 0 2006.168.08:06:10.28#ibcon#about to read 4, iclass 27, count 0 2006.168.08:06:10.28#ibcon#read 4, iclass 27, count 0 2006.168.08:06:10.28#ibcon#about to read 5, iclass 27, count 0 2006.168.08:06:10.28#ibcon#read 5, iclass 27, count 0 2006.168.08:06:10.28#ibcon#about to read 6, iclass 27, count 0 2006.168.08:06:10.28#ibcon#read 6, iclass 27, count 0 2006.168.08:06:10.28#ibcon#end of sib2, iclass 27, count 0 2006.168.08:06:10.28#ibcon#*after write, iclass 27, count 0 2006.168.08:06:10.28#ibcon#*before return 0, iclass 27, count 0 2006.168.08:06:10.28#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.168.08:06:10.28#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.168.08:06:10.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.168.08:06:10.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.168.08:06:10.28$vc4f8/valo=8,852.99 2006.168.08:06:10.28#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.168.08:06:10.28#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.168.08:06:10.28#ibcon#ireg 17 cls_cnt 0 2006.168.08:06:10.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.168.08:06:10.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.168.08:06:10.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.168.08:06:10.28#ibcon#enter wrdev, iclass 29, count 0 2006.168.08:06:10.28#ibcon#first serial, iclass 29, count 0 2006.168.08:06:10.28#ibcon#enter sib2, iclass 29, count 0 2006.168.08:06:10.28#ibcon#flushed, iclass 29, count 0 2006.168.08:06:10.28#ibcon#about to write, iclass 29, count 0 2006.168.08:06:10.28#ibcon#wrote, iclass 29, count 0 2006.168.08:06:10.28#ibcon#about to read 3, iclass 29, count 0 2006.168.08:06:10.30#ibcon#read 3, iclass 29, count 0 2006.168.08:06:10.30#ibcon#about to read 4, iclass 29, count 0 2006.168.08:06:10.30#ibcon#read 4, iclass 29, count 0 2006.168.08:06:10.30#ibcon#about to read 5, iclass 29, count 0 2006.168.08:06:10.30#ibcon#read 5, iclass 29, count 0 2006.168.08:06:10.30#ibcon#about to read 6, iclass 29, count 0 2006.168.08:06:10.30#ibcon#read 6, iclass 29, count 0 2006.168.08:06:10.30#ibcon#end of sib2, iclass 29, count 0 2006.168.08:06:10.30#ibcon#*mode == 0, iclass 29, count 0 2006.168.08:06:10.30#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.168.08:06:10.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.08:06:10.30#ibcon#*before write, iclass 29, count 0 2006.168.08:06:10.30#ibcon#enter sib2, iclass 29, count 0 2006.168.08:06:10.30#ibcon#flushed, iclass 29, count 0 2006.168.08:06:10.30#ibcon#about to write, iclass 29, count 0 2006.168.08:06:10.30#ibcon#wrote, iclass 29, count 0 2006.168.08:06:10.30#ibcon#about to read 3, iclass 29, count 0 2006.168.08:06:10.34#ibcon#read 3, iclass 29, count 0 2006.168.08:06:10.34#ibcon#about to read 4, iclass 29, count 0 2006.168.08:06:10.34#ibcon#read 4, iclass 29, count 0 2006.168.08:06:10.34#ibcon#about to read 5, iclass 29, count 0 2006.168.08:06:10.34#ibcon#read 5, iclass 29, count 0 2006.168.08:06:10.34#ibcon#about to read 6, iclass 29, count 0 2006.168.08:06:10.34#ibcon#read 6, iclass 29, count 0 2006.168.08:06:10.34#ibcon#end of sib2, iclass 29, count 0 2006.168.08:06:10.34#ibcon#*after write, iclass 29, count 0 2006.168.08:06:10.34#ibcon#*before return 0, iclass 29, count 0 2006.168.08:06:10.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.168.08:06:10.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.168.08:06:10.34#ibcon#about to clear, iclass 29 cls_cnt 0 2006.168.08:06:10.34#ibcon#cleared, iclass 29 cls_cnt 0 2006.168.08:06:10.34$vc4f8/va=8,7 2006.168.08:06:10.34#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.168.08:06:10.34#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.168.08:06:10.34#ibcon#ireg 11 cls_cnt 2 2006.168.08:06:10.34#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.168.08:06:10.40#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.168.08:06:10.40#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.168.08:06:10.40#ibcon#enter wrdev, iclass 31, count 2 2006.168.08:06:10.40#ibcon#first serial, iclass 31, count 2 2006.168.08:06:10.40#ibcon#enter sib2, iclass 31, count 2 2006.168.08:06:10.40#ibcon#flushed, iclass 31, count 2 2006.168.08:06:10.40#ibcon#about to write, iclass 31, count 2 2006.168.08:06:10.40#ibcon#wrote, iclass 31, count 2 2006.168.08:06:10.40#ibcon#about to read 3, iclass 31, count 2 2006.168.08:06:10.42#ibcon#read 3, iclass 31, count 2 2006.168.08:06:10.42#ibcon#about to read 4, iclass 31, count 2 2006.168.08:06:10.42#ibcon#read 4, iclass 31, count 2 2006.168.08:06:10.42#ibcon#about to read 5, iclass 31, count 2 2006.168.08:06:10.42#ibcon#read 5, iclass 31, count 2 2006.168.08:06:10.42#ibcon#about to read 6, iclass 31, count 2 2006.168.08:06:10.42#ibcon#read 6, iclass 31, count 2 2006.168.08:06:10.42#ibcon#end of sib2, iclass 31, count 2 2006.168.08:06:10.42#ibcon#*mode == 0, iclass 31, count 2 2006.168.08:06:10.42#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.168.08:06:10.42#ibcon#[25=AT08-07\r\n] 2006.168.08:06:10.42#ibcon#*before write, iclass 31, count 2 2006.168.08:06:10.42#ibcon#enter sib2, iclass 31, count 2 2006.168.08:06:10.42#ibcon#flushed, iclass 31, count 2 2006.168.08:06:10.42#ibcon#about to write, iclass 31, count 2 2006.168.08:06:10.42#ibcon#wrote, iclass 31, count 2 2006.168.08:06:10.42#ibcon#about to read 3, iclass 31, count 2 2006.168.08:06:10.45#ibcon#read 3, iclass 31, count 2 2006.168.08:06:10.45#ibcon#about to read 4, iclass 31, count 2 2006.168.08:06:10.45#ibcon#read 4, iclass 31, count 2 2006.168.08:06:10.45#ibcon#about to read 5, iclass 31, count 2 2006.168.08:06:10.45#ibcon#read 5, iclass 31, count 2 2006.168.08:06:10.45#ibcon#about to read 6, iclass 31, count 2 2006.168.08:06:10.45#ibcon#read 6, iclass 31, count 2 2006.168.08:06:10.45#ibcon#end of sib2, iclass 31, count 2 2006.168.08:06:10.45#ibcon#*after write, iclass 31, count 2 2006.168.08:06:10.45#ibcon#*before return 0, iclass 31, count 2 2006.168.08:06:10.45#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.168.08:06:10.45#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.168.08:06:10.45#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.168.08:06:10.45#ibcon#ireg 7 cls_cnt 0 2006.168.08:06:10.45#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.168.08:06:10.57#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.168.08:06:10.57#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.168.08:06:10.57#ibcon#enter wrdev, iclass 31, count 0 2006.168.08:06:10.57#ibcon#first serial, iclass 31, count 0 2006.168.08:06:10.57#ibcon#enter sib2, iclass 31, count 0 2006.168.08:06:10.57#ibcon#flushed, iclass 31, count 0 2006.168.08:06:10.57#ibcon#about to write, iclass 31, count 0 2006.168.08:06:10.57#ibcon#wrote, iclass 31, count 0 2006.168.08:06:10.57#ibcon#about to read 3, iclass 31, count 0 2006.168.08:06:10.59#ibcon#read 3, iclass 31, count 0 2006.168.08:06:10.59#ibcon#about to read 4, iclass 31, count 0 2006.168.08:06:10.59#ibcon#read 4, iclass 31, count 0 2006.168.08:06:10.59#ibcon#about to read 5, iclass 31, count 0 2006.168.08:06:10.59#ibcon#read 5, iclass 31, count 0 2006.168.08:06:10.59#ibcon#about to read 6, iclass 31, count 0 2006.168.08:06:10.59#ibcon#read 6, iclass 31, count 0 2006.168.08:06:10.59#ibcon#end of sib2, iclass 31, count 0 2006.168.08:06:10.59#ibcon#*mode == 0, iclass 31, count 0 2006.168.08:06:10.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.168.08:06:10.59#ibcon#[25=USB\r\n] 2006.168.08:06:10.59#ibcon#*before write, iclass 31, count 0 2006.168.08:06:10.59#ibcon#enter sib2, iclass 31, count 0 2006.168.08:06:10.59#ibcon#flushed, iclass 31, count 0 2006.168.08:06:10.59#ibcon#about to write, iclass 31, count 0 2006.168.08:06:10.59#ibcon#wrote, iclass 31, count 0 2006.168.08:06:10.59#ibcon#about to read 3, iclass 31, count 0 2006.168.08:06:10.62#ibcon#read 3, iclass 31, count 0 2006.168.08:06:10.62#ibcon#about to read 4, iclass 31, count 0 2006.168.08:06:10.62#ibcon#read 4, iclass 31, count 0 2006.168.08:06:10.62#ibcon#about to read 5, iclass 31, count 0 2006.168.08:06:10.62#ibcon#read 5, iclass 31, count 0 2006.168.08:06:10.62#ibcon#about to read 6, iclass 31, count 0 2006.168.08:06:10.62#ibcon#read 6, iclass 31, count 0 2006.168.08:06:10.62#ibcon#end of sib2, iclass 31, count 0 2006.168.08:06:10.62#ibcon#*after write, iclass 31, count 0 2006.168.08:06:10.62#ibcon#*before return 0, iclass 31, count 0 2006.168.08:06:10.62#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.168.08:06:10.62#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.168.08:06:10.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.168.08:06:10.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.168.08:06:10.62$vc4f8/vblo=1,632.99 2006.168.08:06:10.62#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.168.08:06:10.62#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.168.08:06:10.62#ibcon#ireg 17 cls_cnt 0 2006.168.08:06:10.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:06:10.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:06:10.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:06:10.62#ibcon#enter wrdev, iclass 33, count 0 2006.168.08:06:10.62#ibcon#first serial, iclass 33, count 0 2006.168.08:06:10.62#ibcon#enter sib2, iclass 33, count 0 2006.168.08:06:10.62#ibcon#flushed, iclass 33, count 0 2006.168.08:06:10.62#ibcon#about to write, iclass 33, count 0 2006.168.08:06:10.62#ibcon#wrote, iclass 33, count 0 2006.168.08:06:10.62#ibcon#about to read 3, iclass 33, count 0 2006.168.08:06:10.64#ibcon#read 3, iclass 33, count 0 2006.168.08:06:10.64#ibcon#about to read 4, iclass 33, count 0 2006.168.08:06:10.64#ibcon#read 4, iclass 33, count 0 2006.168.08:06:10.64#ibcon#about to read 5, iclass 33, count 0 2006.168.08:06:10.64#ibcon#read 5, iclass 33, count 0 2006.168.08:06:10.64#ibcon#about to read 6, iclass 33, count 0 2006.168.08:06:10.64#ibcon#read 6, iclass 33, count 0 2006.168.08:06:10.64#ibcon#end of sib2, iclass 33, count 0 2006.168.08:06:10.64#ibcon#*mode == 0, iclass 33, count 0 2006.168.08:06:10.64#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.168.08:06:10.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.08:06:10.64#ibcon#*before write, iclass 33, count 0 2006.168.08:06:10.64#ibcon#enter sib2, iclass 33, count 0 2006.168.08:06:10.64#ibcon#flushed, iclass 33, count 0 2006.168.08:06:10.64#ibcon#about to write, iclass 33, count 0 2006.168.08:06:10.64#ibcon#wrote, iclass 33, count 0 2006.168.08:06:10.64#ibcon#about to read 3, iclass 33, count 0 2006.168.08:06:10.68#ibcon#read 3, iclass 33, count 0 2006.168.08:06:10.68#ibcon#about to read 4, iclass 33, count 0 2006.168.08:06:10.68#ibcon#read 4, iclass 33, count 0 2006.168.08:06:10.68#ibcon#about to read 5, iclass 33, count 0 2006.168.08:06:10.68#ibcon#read 5, iclass 33, count 0 2006.168.08:06:10.68#ibcon#about to read 6, iclass 33, count 0 2006.168.08:06:10.68#ibcon#read 6, iclass 33, count 0 2006.168.08:06:10.68#ibcon#end of sib2, iclass 33, count 0 2006.168.08:06:10.68#ibcon#*after write, iclass 33, count 0 2006.168.08:06:10.68#ibcon#*before return 0, iclass 33, count 0 2006.168.08:06:10.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:06:10.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:06:10.68#ibcon#about to clear, iclass 33 cls_cnt 0 2006.168.08:06:10.68#ibcon#cleared, iclass 33 cls_cnt 0 2006.168.08:06:10.68$vc4f8/vb=1,4 2006.168.08:06:10.68#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.168.08:06:10.68#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.168.08:06:10.68#ibcon#ireg 11 cls_cnt 2 2006.168.08:06:10.68#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.168.08:06:10.68#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.168.08:06:10.68#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.168.08:06:10.68#ibcon#enter wrdev, iclass 35, count 2 2006.168.08:06:10.68#ibcon#first serial, iclass 35, count 2 2006.168.08:06:10.68#ibcon#enter sib2, iclass 35, count 2 2006.168.08:06:10.68#ibcon#flushed, iclass 35, count 2 2006.168.08:06:10.68#ibcon#about to write, iclass 35, count 2 2006.168.08:06:10.68#ibcon#wrote, iclass 35, count 2 2006.168.08:06:10.68#ibcon#about to read 3, iclass 35, count 2 2006.168.08:06:10.70#ibcon#read 3, iclass 35, count 2 2006.168.08:06:10.70#ibcon#about to read 4, iclass 35, count 2 2006.168.08:06:10.70#ibcon#read 4, iclass 35, count 2 2006.168.08:06:10.70#ibcon#about to read 5, iclass 35, count 2 2006.168.08:06:10.70#ibcon#read 5, iclass 35, count 2 2006.168.08:06:10.70#ibcon#about to read 6, iclass 35, count 2 2006.168.08:06:10.70#ibcon#read 6, iclass 35, count 2 2006.168.08:06:10.70#ibcon#end of sib2, iclass 35, count 2 2006.168.08:06:10.70#ibcon#*mode == 0, iclass 35, count 2 2006.168.08:06:10.70#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.168.08:06:10.70#ibcon#[27=AT01-04\r\n] 2006.168.08:06:10.70#ibcon#*before write, iclass 35, count 2 2006.168.08:06:10.70#ibcon#enter sib2, iclass 35, count 2 2006.168.08:06:10.70#ibcon#flushed, iclass 35, count 2 2006.168.08:06:10.70#ibcon#about to write, iclass 35, count 2 2006.168.08:06:10.70#ibcon#wrote, iclass 35, count 2 2006.168.08:06:10.70#ibcon#about to read 3, iclass 35, count 2 2006.168.08:06:10.73#ibcon#read 3, iclass 35, count 2 2006.168.08:06:10.73#ibcon#about to read 4, iclass 35, count 2 2006.168.08:06:10.73#ibcon#read 4, iclass 35, count 2 2006.168.08:06:10.73#ibcon#about to read 5, iclass 35, count 2 2006.168.08:06:10.73#ibcon#read 5, iclass 35, count 2 2006.168.08:06:10.73#ibcon#about to read 6, iclass 35, count 2 2006.168.08:06:10.73#ibcon#read 6, iclass 35, count 2 2006.168.08:06:10.73#ibcon#end of sib2, iclass 35, count 2 2006.168.08:06:10.73#ibcon#*after write, iclass 35, count 2 2006.168.08:06:10.73#ibcon#*before return 0, iclass 35, count 2 2006.168.08:06:10.73#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.168.08:06:10.73#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.168.08:06:10.73#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.168.08:06:10.73#ibcon#ireg 7 cls_cnt 0 2006.168.08:06:10.73#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.168.08:06:10.85#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.168.08:06:10.85#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.168.08:06:10.85#ibcon#enter wrdev, iclass 35, count 0 2006.168.08:06:10.85#ibcon#first serial, iclass 35, count 0 2006.168.08:06:10.85#ibcon#enter sib2, iclass 35, count 0 2006.168.08:06:10.85#ibcon#flushed, iclass 35, count 0 2006.168.08:06:10.85#ibcon#about to write, iclass 35, count 0 2006.168.08:06:10.85#ibcon#wrote, iclass 35, count 0 2006.168.08:06:10.85#ibcon#about to read 3, iclass 35, count 0 2006.168.08:06:10.87#ibcon#read 3, iclass 35, count 0 2006.168.08:06:10.87#ibcon#about to read 4, iclass 35, count 0 2006.168.08:06:10.87#ibcon#read 4, iclass 35, count 0 2006.168.08:06:10.87#ibcon#about to read 5, iclass 35, count 0 2006.168.08:06:10.87#ibcon#read 5, iclass 35, count 0 2006.168.08:06:10.87#ibcon#about to read 6, iclass 35, count 0 2006.168.08:06:10.87#ibcon#read 6, iclass 35, count 0 2006.168.08:06:10.87#ibcon#end of sib2, iclass 35, count 0 2006.168.08:06:10.87#ibcon#*mode == 0, iclass 35, count 0 2006.168.08:06:10.87#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.168.08:06:10.87#ibcon#[27=USB\r\n] 2006.168.08:06:10.87#ibcon#*before write, iclass 35, count 0 2006.168.08:06:10.87#ibcon#enter sib2, iclass 35, count 0 2006.168.08:06:10.87#ibcon#flushed, iclass 35, count 0 2006.168.08:06:10.87#ibcon#about to write, iclass 35, count 0 2006.168.08:06:10.87#ibcon#wrote, iclass 35, count 0 2006.168.08:06:10.87#ibcon#about to read 3, iclass 35, count 0 2006.168.08:06:10.90#ibcon#read 3, iclass 35, count 0 2006.168.08:06:10.90#ibcon#about to read 4, iclass 35, count 0 2006.168.08:06:10.90#ibcon#read 4, iclass 35, count 0 2006.168.08:06:10.90#ibcon#about to read 5, iclass 35, count 0 2006.168.08:06:10.90#ibcon#read 5, iclass 35, count 0 2006.168.08:06:10.90#ibcon#about to read 6, iclass 35, count 0 2006.168.08:06:10.90#ibcon#read 6, iclass 35, count 0 2006.168.08:06:10.90#ibcon#end of sib2, iclass 35, count 0 2006.168.08:06:10.90#ibcon#*after write, iclass 35, count 0 2006.168.08:06:10.90#ibcon#*before return 0, iclass 35, count 0 2006.168.08:06:10.90#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.168.08:06:10.90#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.168.08:06:10.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.168.08:06:10.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.168.08:06:10.90$vc4f8/vblo=2,640.99 2006.168.08:06:10.90#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.168.08:06:10.90#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.168.08:06:10.90#ibcon#ireg 17 cls_cnt 0 2006.168.08:06:10.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:06:10.90#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:06:10.90#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:06:10.90#ibcon#enter wrdev, iclass 37, count 0 2006.168.08:06:10.90#ibcon#first serial, iclass 37, count 0 2006.168.08:06:10.90#ibcon#enter sib2, iclass 37, count 0 2006.168.08:06:10.90#ibcon#flushed, iclass 37, count 0 2006.168.08:06:10.90#ibcon#about to write, iclass 37, count 0 2006.168.08:06:10.90#ibcon#wrote, iclass 37, count 0 2006.168.08:06:10.90#ibcon#about to read 3, iclass 37, count 0 2006.168.08:06:10.92#ibcon#read 3, iclass 37, count 0 2006.168.08:06:10.92#ibcon#about to read 4, iclass 37, count 0 2006.168.08:06:10.92#ibcon#read 4, iclass 37, count 0 2006.168.08:06:10.92#ibcon#about to read 5, iclass 37, count 0 2006.168.08:06:10.92#ibcon#read 5, iclass 37, count 0 2006.168.08:06:10.92#ibcon#about to read 6, iclass 37, count 0 2006.168.08:06:10.92#ibcon#read 6, iclass 37, count 0 2006.168.08:06:10.92#ibcon#end of sib2, iclass 37, count 0 2006.168.08:06:10.92#ibcon#*mode == 0, iclass 37, count 0 2006.168.08:06:10.92#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.168.08:06:10.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.08:06:10.92#ibcon#*before write, iclass 37, count 0 2006.168.08:06:10.92#ibcon#enter sib2, iclass 37, count 0 2006.168.08:06:10.92#ibcon#flushed, iclass 37, count 0 2006.168.08:06:10.92#ibcon#about to write, iclass 37, count 0 2006.168.08:06:10.92#ibcon#wrote, iclass 37, count 0 2006.168.08:06:10.92#ibcon#about to read 3, iclass 37, count 0 2006.168.08:06:10.96#ibcon#read 3, iclass 37, count 0 2006.168.08:06:10.96#ibcon#about to read 4, iclass 37, count 0 2006.168.08:06:10.96#ibcon#read 4, iclass 37, count 0 2006.168.08:06:10.96#ibcon#about to read 5, iclass 37, count 0 2006.168.08:06:10.96#ibcon#read 5, iclass 37, count 0 2006.168.08:06:10.96#ibcon#about to read 6, iclass 37, count 0 2006.168.08:06:10.96#ibcon#read 6, iclass 37, count 0 2006.168.08:06:10.96#ibcon#end of sib2, iclass 37, count 0 2006.168.08:06:10.96#ibcon#*after write, iclass 37, count 0 2006.168.08:06:10.96#ibcon#*before return 0, iclass 37, count 0 2006.168.08:06:10.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:06:10.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:06:10.96#ibcon#about to clear, iclass 37 cls_cnt 0 2006.168.08:06:10.96#ibcon#cleared, iclass 37 cls_cnt 0 2006.168.08:06:10.96$vc4f8/vb=2,4 2006.168.08:06:10.96#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.168.08:06:10.96#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.168.08:06:10.96#ibcon#ireg 11 cls_cnt 2 2006.168.08:06:10.96#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.168.08:06:11.02#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.168.08:06:11.02#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.168.08:06:11.02#ibcon#enter wrdev, iclass 39, count 2 2006.168.08:06:11.02#ibcon#first serial, iclass 39, count 2 2006.168.08:06:11.02#ibcon#enter sib2, iclass 39, count 2 2006.168.08:06:11.02#ibcon#flushed, iclass 39, count 2 2006.168.08:06:11.02#ibcon#about to write, iclass 39, count 2 2006.168.08:06:11.02#ibcon#wrote, iclass 39, count 2 2006.168.08:06:11.02#ibcon#about to read 3, iclass 39, count 2 2006.168.08:06:11.04#ibcon#read 3, iclass 39, count 2 2006.168.08:06:11.04#ibcon#about to read 4, iclass 39, count 2 2006.168.08:06:11.04#ibcon#read 4, iclass 39, count 2 2006.168.08:06:11.04#ibcon#about to read 5, iclass 39, count 2 2006.168.08:06:11.04#ibcon#read 5, iclass 39, count 2 2006.168.08:06:11.04#ibcon#about to read 6, iclass 39, count 2 2006.168.08:06:11.04#ibcon#read 6, iclass 39, count 2 2006.168.08:06:11.04#ibcon#end of sib2, iclass 39, count 2 2006.168.08:06:11.04#ibcon#*mode == 0, iclass 39, count 2 2006.168.08:06:11.04#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.168.08:06:11.04#ibcon#[27=AT02-04\r\n] 2006.168.08:06:11.04#ibcon#*before write, iclass 39, count 2 2006.168.08:06:11.04#ibcon#enter sib2, iclass 39, count 2 2006.168.08:06:11.04#ibcon#flushed, iclass 39, count 2 2006.168.08:06:11.04#ibcon#about to write, iclass 39, count 2 2006.168.08:06:11.04#ibcon#wrote, iclass 39, count 2 2006.168.08:06:11.04#ibcon#about to read 3, iclass 39, count 2 2006.168.08:06:11.07#ibcon#read 3, iclass 39, count 2 2006.168.08:06:11.07#ibcon#about to read 4, iclass 39, count 2 2006.168.08:06:11.07#ibcon#read 4, iclass 39, count 2 2006.168.08:06:11.07#ibcon#about to read 5, iclass 39, count 2 2006.168.08:06:11.07#ibcon#read 5, iclass 39, count 2 2006.168.08:06:11.07#ibcon#about to read 6, iclass 39, count 2 2006.168.08:06:11.07#ibcon#read 6, iclass 39, count 2 2006.168.08:06:11.07#ibcon#end of sib2, iclass 39, count 2 2006.168.08:06:11.07#ibcon#*after write, iclass 39, count 2 2006.168.08:06:11.07#ibcon#*before return 0, iclass 39, count 2 2006.168.08:06:11.07#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.168.08:06:11.07#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.168.08:06:11.07#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.168.08:06:11.07#ibcon#ireg 7 cls_cnt 0 2006.168.08:06:11.07#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.168.08:06:11.19#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.168.08:06:11.19#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.168.08:06:11.19#ibcon#enter wrdev, iclass 39, count 0 2006.168.08:06:11.19#ibcon#first serial, iclass 39, count 0 2006.168.08:06:11.19#ibcon#enter sib2, iclass 39, count 0 2006.168.08:06:11.19#ibcon#flushed, iclass 39, count 0 2006.168.08:06:11.19#ibcon#about to write, iclass 39, count 0 2006.168.08:06:11.19#ibcon#wrote, iclass 39, count 0 2006.168.08:06:11.19#ibcon#about to read 3, iclass 39, count 0 2006.168.08:06:11.21#ibcon#read 3, iclass 39, count 0 2006.168.08:06:11.21#ibcon#about to read 4, iclass 39, count 0 2006.168.08:06:11.21#ibcon#read 4, iclass 39, count 0 2006.168.08:06:11.21#ibcon#about to read 5, iclass 39, count 0 2006.168.08:06:11.21#ibcon#read 5, iclass 39, count 0 2006.168.08:06:11.21#ibcon#about to read 6, iclass 39, count 0 2006.168.08:06:11.21#ibcon#read 6, iclass 39, count 0 2006.168.08:06:11.21#ibcon#end of sib2, iclass 39, count 0 2006.168.08:06:11.21#ibcon#*mode == 0, iclass 39, count 0 2006.168.08:06:11.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.168.08:06:11.21#ibcon#[27=USB\r\n] 2006.168.08:06:11.21#ibcon#*before write, iclass 39, count 0 2006.168.08:06:11.21#ibcon#enter sib2, iclass 39, count 0 2006.168.08:06:11.21#ibcon#flushed, iclass 39, count 0 2006.168.08:06:11.21#ibcon#about to write, iclass 39, count 0 2006.168.08:06:11.21#ibcon#wrote, iclass 39, count 0 2006.168.08:06:11.21#ibcon#about to read 3, iclass 39, count 0 2006.168.08:06:11.24#ibcon#read 3, iclass 39, count 0 2006.168.08:06:11.24#ibcon#about to read 4, iclass 39, count 0 2006.168.08:06:11.24#ibcon#read 4, iclass 39, count 0 2006.168.08:06:11.24#ibcon#about to read 5, iclass 39, count 0 2006.168.08:06:11.24#ibcon#read 5, iclass 39, count 0 2006.168.08:06:11.24#ibcon#about to read 6, iclass 39, count 0 2006.168.08:06:11.24#ibcon#read 6, iclass 39, count 0 2006.168.08:06:11.24#ibcon#end of sib2, iclass 39, count 0 2006.168.08:06:11.24#ibcon#*after write, iclass 39, count 0 2006.168.08:06:11.24#ibcon#*before return 0, iclass 39, count 0 2006.168.08:06:11.24#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.168.08:06:11.24#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.168.08:06:11.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.168.08:06:11.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.168.08:06:11.24$vc4f8/vblo=3,656.99 2006.168.08:06:11.24#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.168.08:06:11.24#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.168.08:06:11.24#ibcon#ireg 17 cls_cnt 0 2006.168.08:06:11.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.168.08:06:11.24#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.168.08:06:11.24#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.168.08:06:11.24#ibcon#enter wrdev, iclass 3, count 0 2006.168.08:06:11.24#ibcon#first serial, iclass 3, count 0 2006.168.08:06:11.24#ibcon#enter sib2, iclass 3, count 0 2006.168.08:06:11.24#ibcon#flushed, iclass 3, count 0 2006.168.08:06:11.24#ibcon#about to write, iclass 3, count 0 2006.168.08:06:11.24#ibcon#wrote, iclass 3, count 0 2006.168.08:06:11.24#ibcon#about to read 3, iclass 3, count 0 2006.168.08:06:11.26#ibcon#read 3, iclass 3, count 0 2006.168.08:06:11.26#ibcon#about to read 4, iclass 3, count 0 2006.168.08:06:11.26#ibcon#read 4, iclass 3, count 0 2006.168.08:06:11.26#ibcon#about to read 5, iclass 3, count 0 2006.168.08:06:11.26#ibcon#read 5, iclass 3, count 0 2006.168.08:06:11.26#ibcon#about to read 6, iclass 3, count 0 2006.168.08:06:11.26#ibcon#read 6, iclass 3, count 0 2006.168.08:06:11.26#ibcon#end of sib2, iclass 3, count 0 2006.168.08:06:11.26#ibcon#*mode == 0, iclass 3, count 0 2006.168.08:06:11.26#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.168.08:06:11.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.08:06:11.26#ibcon#*before write, iclass 3, count 0 2006.168.08:06:11.26#ibcon#enter sib2, iclass 3, count 0 2006.168.08:06:11.26#ibcon#flushed, iclass 3, count 0 2006.168.08:06:11.26#ibcon#about to write, iclass 3, count 0 2006.168.08:06:11.26#ibcon#wrote, iclass 3, count 0 2006.168.08:06:11.26#ibcon#about to read 3, iclass 3, count 0 2006.168.08:06:11.30#ibcon#read 3, iclass 3, count 0 2006.168.08:06:11.30#ibcon#about to read 4, iclass 3, count 0 2006.168.08:06:11.30#ibcon#read 4, iclass 3, count 0 2006.168.08:06:11.30#ibcon#about to read 5, iclass 3, count 0 2006.168.08:06:11.30#ibcon#read 5, iclass 3, count 0 2006.168.08:06:11.30#ibcon#about to read 6, iclass 3, count 0 2006.168.08:06:11.30#ibcon#read 6, iclass 3, count 0 2006.168.08:06:11.30#ibcon#end of sib2, iclass 3, count 0 2006.168.08:06:11.30#ibcon#*after write, iclass 3, count 0 2006.168.08:06:11.30#ibcon#*before return 0, iclass 3, count 0 2006.168.08:06:11.30#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.168.08:06:11.30#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.168.08:06:11.30#ibcon#about to clear, iclass 3 cls_cnt 0 2006.168.08:06:11.30#ibcon#cleared, iclass 3 cls_cnt 0 2006.168.08:06:11.30$vc4f8/vb=3,4 2006.168.08:06:11.30#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.168.08:06:11.30#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.168.08:06:11.30#ibcon#ireg 11 cls_cnt 2 2006.168.08:06:11.30#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.168.08:06:11.36#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.168.08:06:11.36#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.168.08:06:11.36#ibcon#enter wrdev, iclass 5, count 2 2006.168.08:06:11.36#ibcon#first serial, iclass 5, count 2 2006.168.08:06:11.36#ibcon#enter sib2, iclass 5, count 2 2006.168.08:06:11.36#ibcon#flushed, iclass 5, count 2 2006.168.08:06:11.36#ibcon#about to write, iclass 5, count 2 2006.168.08:06:11.36#ibcon#wrote, iclass 5, count 2 2006.168.08:06:11.36#ibcon#about to read 3, iclass 5, count 2 2006.168.08:06:11.38#ibcon#read 3, iclass 5, count 2 2006.168.08:06:11.38#ibcon#about to read 4, iclass 5, count 2 2006.168.08:06:11.38#ibcon#read 4, iclass 5, count 2 2006.168.08:06:11.38#ibcon#about to read 5, iclass 5, count 2 2006.168.08:06:11.38#ibcon#read 5, iclass 5, count 2 2006.168.08:06:11.38#ibcon#about to read 6, iclass 5, count 2 2006.168.08:06:11.38#ibcon#read 6, iclass 5, count 2 2006.168.08:06:11.38#ibcon#end of sib2, iclass 5, count 2 2006.168.08:06:11.38#ibcon#*mode == 0, iclass 5, count 2 2006.168.08:06:11.38#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.168.08:06:11.38#ibcon#[27=AT03-04\r\n] 2006.168.08:06:11.38#ibcon#*before write, iclass 5, count 2 2006.168.08:06:11.38#ibcon#enter sib2, iclass 5, count 2 2006.168.08:06:11.38#ibcon#flushed, iclass 5, count 2 2006.168.08:06:11.38#ibcon#about to write, iclass 5, count 2 2006.168.08:06:11.38#ibcon#wrote, iclass 5, count 2 2006.168.08:06:11.38#ibcon#about to read 3, iclass 5, count 2 2006.168.08:06:11.41#ibcon#read 3, iclass 5, count 2 2006.168.08:06:11.41#ibcon#about to read 4, iclass 5, count 2 2006.168.08:06:11.41#ibcon#read 4, iclass 5, count 2 2006.168.08:06:11.41#ibcon#about to read 5, iclass 5, count 2 2006.168.08:06:11.41#ibcon#read 5, iclass 5, count 2 2006.168.08:06:11.41#ibcon#about to read 6, iclass 5, count 2 2006.168.08:06:11.41#ibcon#read 6, iclass 5, count 2 2006.168.08:06:11.41#ibcon#end of sib2, iclass 5, count 2 2006.168.08:06:11.41#ibcon#*after write, iclass 5, count 2 2006.168.08:06:11.41#ibcon#*before return 0, iclass 5, count 2 2006.168.08:06:11.41#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.168.08:06:11.41#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.168.08:06:11.41#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.168.08:06:11.41#ibcon#ireg 7 cls_cnt 0 2006.168.08:06:11.41#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.168.08:06:11.53#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.168.08:06:11.53#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.168.08:06:11.53#ibcon#enter wrdev, iclass 5, count 0 2006.168.08:06:11.53#ibcon#first serial, iclass 5, count 0 2006.168.08:06:11.53#ibcon#enter sib2, iclass 5, count 0 2006.168.08:06:11.53#ibcon#flushed, iclass 5, count 0 2006.168.08:06:11.53#ibcon#about to write, iclass 5, count 0 2006.168.08:06:11.53#ibcon#wrote, iclass 5, count 0 2006.168.08:06:11.53#ibcon#about to read 3, iclass 5, count 0 2006.168.08:06:11.55#ibcon#read 3, iclass 5, count 0 2006.168.08:06:11.55#ibcon#about to read 4, iclass 5, count 0 2006.168.08:06:11.55#ibcon#read 4, iclass 5, count 0 2006.168.08:06:11.55#ibcon#about to read 5, iclass 5, count 0 2006.168.08:06:11.55#ibcon#read 5, iclass 5, count 0 2006.168.08:06:11.55#ibcon#about to read 6, iclass 5, count 0 2006.168.08:06:11.55#ibcon#read 6, iclass 5, count 0 2006.168.08:06:11.55#ibcon#end of sib2, iclass 5, count 0 2006.168.08:06:11.55#ibcon#*mode == 0, iclass 5, count 0 2006.168.08:06:11.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.168.08:06:11.55#ibcon#[27=USB\r\n] 2006.168.08:06:11.55#ibcon#*before write, iclass 5, count 0 2006.168.08:06:11.55#ibcon#enter sib2, iclass 5, count 0 2006.168.08:06:11.55#ibcon#flushed, iclass 5, count 0 2006.168.08:06:11.55#ibcon#about to write, iclass 5, count 0 2006.168.08:06:11.55#ibcon#wrote, iclass 5, count 0 2006.168.08:06:11.55#ibcon#about to read 3, iclass 5, count 0 2006.168.08:06:11.58#ibcon#read 3, iclass 5, count 0 2006.168.08:06:11.58#ibcon#about to read 4, iclass 5, count 0 2006.168.08:06:11.58#ibcon#read 4, iclass 5, count 0 2006.168.08:06:11.58#ibcon#about to read 5, iclass 5, count 0 2006.168.08:06:11.58#ibcon#read 5, iclass 5, count 0 2006.168.08:06:11.58#ibcon#about to read 6, iclass 5, count 0 2006.168.08:06:11.58#ibcon#read 6, iclass 5, count 0 2006.168.08:06:11.58#ibcon#end of sib2, iclass 5, count 0 2006.168.08:06:11.58#ibcon#*after write, iclass 5, count 0 2006.168.08:06:11.58#ibcon#*before return 0, iclass 5, count 0 2006.168.08:06:11.58#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.168.08:06:11.58#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.168.08:06:11.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.168.08:06:11.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.168.08:06:11.58$vc4f8/vblo=4,712.99 2006.168.08:06:11.58#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.168.08:06:11.58#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.168.08:06:11.58#ibcon#ireg 17 cls_cnt 0 2006.168.08:06:11.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.168.08:06:11.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.168.08:06:11.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.168.08:06:11.58#ibcon#enter wrdev, iclass 7, count 0 2006.168.08:06:11.58#ibcon#first serial, iclass 7, count 0 2006.168.08:06:11.58#ibcon#enter sib2, iclass 7, count 0 2006.168.08:06:11.58#ibcon#flushed, iclass 7, count 0 2006.168.08:06:11.58#ibcon#about to write, iclass 7, count 0 2006.168.08:06:11.58#ibcon#wrote, iclass 7, count 0 2006.168.08:06:11.58#ibcon#about to read 3, iclass 7, count 0 2006.168.08:06:11.60#ibcon#read 3, iclass 7, count 0 2006.168.08:06:11.60#ibcon#about to read 4, iclass 7, count 0 2006.168.08:06:11.60#ibcon#read 4, iclass 7, count 0 2006.168.08:06:11.60#ibcon#about to read 5, iclass 7, count 0 2006.168.08:06:11.60#ibcon#read 5, iclass 7, count 0 2006.168.08:06:11.60#ibcon#about to read 6, iclass 7, count 0 2006.168.08:06:11.60#ibcon#read 6, iclass 7, count 0 2006.168.08:06:11.60#ibcon#end of sib2, iclass 7, count 0 2006.168.08:06:11.60#ibcon#*mode == 0, iclass 7, count 0 2006.168.08:06:11.60#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.168.08:06:11.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.08:06:11.60#ibcon#*before write, iclass 7, count 0 2006.168.08:06:11.60#ibcon#enter sib2, iclass 7, count 0 2006.168.08:06:11.60#ibcon#flushed, iclass 7, count 0 2006.168.08:06:11.60#ibcon#about to write, iclass 7, count 0 2006.168.08:06:11.60#ibcon#wrote, iclass 7, count 0 2006.168.08:06:11.60#ibcon#about to read 3, iclass 7, count 0 2006.168.08:06:11.64#ibcon#read 3, iclass 7, count 0 2006.168.08:06:11.64#ibcon#about to read 4, iclass 7, count 0 2006.168.08:06:11.64#ibcon#read 4, iclass 7, count 0 2006.168.08:06:11.64#ibcon#about to read 5, iclass 7, count 0 2006.168.08:06:11.64#ibcon#read 5, iclass 7, count 0 2006.168.08:06:11.64#ibcon#about to read 6, iclass 7, count 0 2006.168.08:06:11.64#ibcon#read 6, iclass 7, count 0 2006.168.08:06:11.64#ibcon#end of sib2, iclass 7, count 0 2006.168.08:06:11.64#ibcon#*after write, iclass 7, count 0 2006.168.08:06:11.64#ibcon#*before return 0, iclass 7, count 0 2006.168.08:06:11.64#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.168.08:06:11.64#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.168.08:06:11.64#ibcon#about to clear, iclass 7 cls_cnt 0 2006.168.08:06:11.64#ibcon#cleared, iclass 7 cls_cnt 0 2006.168.08:06:11.64$vc4f8/vb=4,4 2006.168.08:06:11.64#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.168.08:06:11.64#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.168.08:06:11.64#ibcon#ireg 11 cls_cnt 2 2006.168.08:06:11.64#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.168.08:06:11.70#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.168.08:06:11.70#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.168.08:06:11.70#ibcon#enter wrdev, iclass 11, count 2 2006.168.08:06:11.70#ibcon#first serial, iclass 11, count 2 2006.168.08:06:11.70#ibcon#enter sib2, iclass 11, count 2 2006.168.08:06:11.70#ibcon#flushed, iclass 11, count 2 2006.168.08:06:11.70#ibcon#about to write, iclass 11, count 2 2006.168.08:06:11.70#ibcon#wrote, iclass 11, count 2 2006.168.08:06:11.70#ibcon#about to read 3, iclass 11, count 2 2006.168.08:06:11.72#ibcon#read 3, iclass 11, count 2 2006.168.08:06:11.72#ibcon#about to read 4, iclass 11, count 2 2006.168.08:06:11.72#ibcon#read 4, iclass 11, count 2 2006.168.08:06:11.72#ibcon#about to read 5, iclass 11, count 2 2006.168.08:06:11.72#ibcon#read 5, iclass 11, count 2 2006.168.08:06:11.72#ibcon#about to read 6, iclass 11, count 2 2006.168.08:06:11.72#ibcon#read 6, iclass 11, count 2 2006.168.08:06:11.72#ibcon#end of sib2, iclass 11, count 2 2006.168.08:06:11.72#ibcon#*mode == 0, iclass 11, count 2 2006.168.08:06:11.72#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.168.08:06:11.72#ibcon#[27=AT04-04\r\n] 2006.168.08:06:11.72#ibcon#*before write, iclass 11, count 2 2006.168.08:06:11.72#ibcon#enter sib2, iclass 11, count 2 2006.168.08:06:11.72#ibcon#flushed, iclass 11, count 2 2006.168.08:06:11.72#ibcon#about to write, iclass 11, count 2 2006.168.08:06:11.72#ibcon#wrote, iclass 11, count 2 2006.168.08:06:11.72#ibcon#about to read 3, iclass 11, count 2 2006.168.08:06:11.75#ibcon#read 3, iclass 11, count 2 2006.168.08:06:11.75#ibcon#about to read 4, iclass 11, count 2 2006.168.08:06:11.75#ibcon#read 4, iclass 11, count 2 2006.168.08:06:11.75#ibcon#about to read 5, iclass 11, count 2 2006.168.08:06:11.75#ibcon#read 5, iclass 11, count 2 2006.168.08:06:11.75#ibcon#about to read 6, iclass 11, count 2 2006.168.08:06:11.75#ibcon#read 6, iclass 11, count 2 2006.168.08:06:11.75#ibcon#end of sib2, iclass 11, count 2 2006.168.08:06:11.75#ibcon#*after write, iclass 11, count 2 2006.168.08:06:11.75#ibcon#*before return 0, iclass 11, count 2 2006.168.08:06:11.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.168.08:06:11.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.168.08:06:11.75#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.168.08:06:11.75#ibcon#ireg 7 cls_cnt 0 2006.168.08:06:11.75#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.168.08:06:11.87#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.168.08:06:11.87#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.168.08:06:11.87#ibcon#enter wrdev, iclass 11, count 0 2006.168.08:06:11.87#ibcon#first serial, iclass 11, count 0 2006.168.08:06:11.87#ibcon#enter sib2, iclass 11, count 0 2006.168.08:06:11.87#ibcon#flushed, iclass 11, count 0 2006.168.08:06:11.87#ibcon#about to write, iclass 11, count 0 2006.168.08:06:11.87#ibcon#wrote, iclass 11, count 0 2006.168.08:06:11.87#ibcon#about to read 3, iclass 11, count 0 2006.168.08:06:11.89#ibcon#read 3, iclass 11, count 0 2006.168.08:06:11.89#ibcon#about to read 4, iclass 11, count 0 2006.168.08:06:11.89#ibcon#read 4, iclass 11, count 0 2006.168.08:06:11.89#ibcon#about to read 5, iclass 11, count 0 2006.168.08:06:11.89#ibcon#read 5, iclass 11, count 0 2006.168.08:06:11.89#ibcon#about to read 6, iclass 11, count 0 2006.168.08:06:11.89#ibcon#read 6, iclass 11, count 0 2006.168.08:06:11.89#ibcon#end of sib2, iclass 11, count 0 2006.168.08:06:11.89#ibcon#*mode == 0, iclass 11, count 0 2006.168.08:06:11.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.168.08:06:11.89#ibcon#[27=USB\r\n] 2006.168.08:06:11.89#ibcon#*before write, iclass 11, count 0 2006.168.08:06:11.89#ibcon#enter sib2, iclass 11, count 0 2006.168.08:06:11.89#ibcon#flushed, iclass 11, count 0 2006.168.08:06:11.89#ibcon#about to write, iclass 11, count 0 2006.168.08:06:11.89#ibcon#wrote, iclass 11, count 0 2006.168.08:06:11.89#ibcon#about to read 3, iclass 11, count 0 2006.168.08:06:11.92#ibcon#read 3, iclass 11, count 0 2006.168.08:06:11.92#ibcon#about to read 4, iclass 11, count 0 2006.168.08:06:11.92#ibcon#read 4, iclass 11, count 0 2006.168.08:06:11.92#ibcon#about to read 5, iclass 11, count 0 2006.168.08:06:11.92#ibcon#read 5, iclass 11, count 0 2006.168.08:06:11.92#ibcon#about to read 6, iclass 11, count 0 2006.168.08:06:11.92#ibcon#read 6, iclass 11, count 0 2006.168.08:06:11.92#ibcon#end of sib2, iclass 11, count 0 2006.168.08:06:11.92#ibcon#*after write, iclass 11, count 0 2006.168.08:06:11.92#ibcon#*before return 0, iclass 11, count 0 2006.168.08:06:11.92#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.168.08:06:11.92#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.168.08:06:11.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.168.08:06:11.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.168.08:06:11.92$vc4f8/vblo=5,744.99 2006.168.08:06:11.92#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.168.08:06:11.92#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.168.08:06:11.92#ibcon#ireg 17 cls_cnt 0 2006.168.08:06:11.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.168.08:06:11.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.168.08:06:11.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.168.08:06:11.92#ibcon#enter wrdev, iclass 13, count 0 2006.168.08:06:11.92#ibcon#first serial, iclass 13, count 0 2006.168.08:06:11.92#ibcon#enter sib2, iclass 13, count 0 2006.168.08:06:11.92#ibcon#flushed, iclass 13, count 0 2006.168.08:06:11.92#ibcon#about to write, iclass 13, count 0 2006.168.08:06:11.92#ibcon#wrote, iclass 13, count 0 2006.168.08:06:11.92#ibcon#about to read 3, iclass 13, count 0 2006.168.08:06:11.94#ibcon#read 3, iclass 13, count 0 2006.168.08:06:11.94#ibcon#about to read 4, iclass 13, count 0 2006.168.08:06:11.94#ibcon#read 4, iclass 13, count 0 2006.168.08:06:11.94#ibcon#about to read 5, iclass 13, count 0 2006.168.08:06:11.94#ibcon#read 5, iclass 13, count 0 2006.168.08:06:11.94#ibcon#about to read 6, iclass 13, count 0 2006.168.08:06:11.94#ibcon#read 6, iclass 13, count 0 2006.168.08:06:11.94#ibcon#end of sib2, iclass 13, count 0 2006.168.08:06:11.94#ibcon#*mode == 0, iclass 13, count 0 2006.168.08:06:11.94#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.168.08:06:11.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.08:06:11.94#ibcon#*before write, iclass 13, count 0 2006.168.08:06:11.94#ibcon#enter sib2, iclass 13, count 0 2006.168.08:06:11.94#ibcon#flushed, iclass 13, count 0 2006.168.08:06:11.94#ibcon#about to write, iclass 13, count 0 2006.168.08:06:11.94#ibcon#wrote, iclass 13, count 0 2006.168.08:06:11.94#ibcon#about to read 3, iclass 13, count 0 2006.168.08:06:11.98#ibcon#read 3, iclass 13, count 0 2006.168.08:06:11.98#ibcon#about to read 4, iclass 13, count 0 2006.168.08:06:11.98#ibcon#read 4, iclass 13, count 0 2006.168.08:06:11.98#ibcon#about to read 5, iclass 13, count 0 2006.168.08:06:11.98#ibcon#read 5, iclass 13, count 0 2006.168.08:06:11.98#ibcon#about to read 6, iclass 13, count 0 2006.168.08:06:11.98#ibcon#read 6, iclass 13, count 0 2006.168.08:06:11.98#ibcon#end of sib2, iclass 13, count 0 2006.168.08:06:11.98#ibcon#*after write, iclass 13, count 0 2006.168.08:06:11.98#ibcon#*before return 0, iclass 13, count 0 2006.168.08:06:11.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.168.08:06:11.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.168.08:06:11.98#ibcon#about to clear, iclass 13 cls_cnt 0 2006.168.08:06:11.98#ibcon#cleared, iclass 13 cls_cnt 0 2006.168.08:06:11.98$vc4f8/vb=5,4 2006.168.08:06:11.98#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.168.08:06:11.98#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.168.08:06:11.98#ibcon#ireg 11 cls_cnt 2 2006.168.08:06:11.98#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.168.08:06:12.04#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.168.08:06:12.04#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.168.08:06:12.04#ibcon#enter wrdev, iclass 15, count 2 2006.168.08:06:12.04#ibcon#first serial, iclass 15, count 2 2006.168.08:06:12.04#ibcon#enter sib2, iclass 15, count 2 2006.168.08:06:12.04#ibcon#flushed, iclass 15, count 2 2006.168.08:06:12.04#ibcon#about to write, iclass 15, count 2 2006.168.08:06:12.04#ibcon#wrote, iclass 15, count 2 2006.168.08:06:12.04#ibcon#about to read 3, iclass 15, count 2 2006.168.08:06:12.06#ibcon#read 3, iclass 15, count 2 2006.168.08:06:12.06#ibcon#about to read 4, iclass 15, count 2 2006.168.08:06:12.06#ibcon#read 4, iclass 15, count 2 2006.168.08:06:12.06#ibcon#about to read 5, iclass 15, count 2 2006.168.08:06:12.06#ibcon#read 5, iclass 15, count 2 2006.168.08:06:12.06#ibcon#about to read 6, iclass 15, count 2 2006.168.08:06:12.06#ibcon#read 6, iclass 15, count 2 2006.168.08:06:12.06#ibcon#end of sib2, iclass 15, count 2 2006.168.08:06:12.06#ibcon#*mode == 0, iclass 15, count 2 2006.168.08:06:12.06#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.168.08:06:12.06#ibcon#[27=AT05-04\r\n] 2006.168.08:06:12.06#ibcon#*before write, iclass 15, count 2 2006.168.08:06:12.06#ibcon#enter sib2, iclass 15, count 2 2006.168.08:06:12.06#ibcon#flushed, iclass 15, count 2 2006.168.08:06:12.06#ibcon#about to write, iclass 15, count 2 2006.168.08:06:12.06#ibcon#wrote, iclass 15, count 2 2006.168.08:06:12.06#ibcon#about to read 3, iclass 15, count 2 2006.168.08:06:12.09#ibcon#read 3, iclass 15, count 2 2006.168.08:06:12.09#ibcon#about to read 4, iclass 15, count 2 2006.168.08:06:12.09#ibcon#read 4, iclass 15, count 2 2006.168.08:06:12.09#ibcon#about to read 5, iclass 15, count 2 2006.168.08:06:12.09#ibcon#read 5, iclass 15, count 2 2006.168.08:06:12.09#ibcon#about to read 6, iclass 15, count 2 2006.168.08:06:12.09#ibcon#read 6, iclass 15, count 2 2006.168.08:06:12.09#ibcon#end of sib2, iclass 15, count 2 2006.168.08:06:12.09#ibcon#*after write, iclass 15, count 2 2006.168.08:06:12.09#ibcon#*before return 0, iclass 15, count 2 2006.168.08:06:12.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.168.08:06:12.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.168.08:06:12.09#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.168.08:06:12.09#ibcon#ireg 7 cls_cnt 0 2006.168.08:06:12.09#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.168.08:06:12.21#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.168.08:06:12.21#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.168.08:06:12.21#ibcon#enter wrdev, iclass 15, count 0 2006.168.08:06:12.21#ibcon#first serial, iclass 15, count 0 2006.168.08:06:12.21#ibcon#enter sib2, iclass 15, count 0 2006.168.08:06:12.21#ibcon#flushed, iclass 15, count 0 2006.168.08:06:12.21#ibcon#about to write, iclass 15, count 0 2006.168.08:06:12.21#ibcon#wrote, iclass 15, count 0 2006.168.08:06:12.21#ibcon#about to read 3, iclass 15, count 0 2006.168.08:06:12.23#ibcon#read 3, iclass 15, count 0 2006.168.08:06:12.23#ibcon#about to read 4, iclass 15, count 0 2006.168.08:06:12.23#ibcon#read 4, iclass 15, count 0 2006.168.08:06:12.23#ibcon#about to read 5, iclass 15, count 0 2006.168.08:06:12.23#ibcon#read 5, iclass 15, count 0 2006.168.08:06:12.23#ibcon#about to read 6, iclass 15, count 0 2006.168.08:06:12.23#ibcon#read 6, iclass 15, count 0 2006.168.08:06:12.23#ibcon#end of sib2, iclass 15, count 0 2006.168.08:06:12.23#ibcon#*mode == 0, iclass 15, count 0 2006.168.08:06:12.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.168.08:06:12.23#ibcon#[27=USB\r\n] 2006.168.08:06:12.23#ibcon#*before write, iclass 15, count 0 2006.168.08:06:12.23#ibcon#enter sib2, iclass 15, count 0 2006.168.08:06:12.23#ibcon#flushed, iclass 15, count 0 2006.168.08:06:12.23#ibcon#about to write, iclass 15, count 0 2006.168.08:06:12.23#ibcon#wrote, iclass 15, count 0 2006.168.08:06:12.23#ibcon#about to read 3, iclass 15, count 0 2006.168.08:06:12.26#ibcon#read 3, iclass 15, count 0 2006.168.08:06:12.26#ibcon#about to read 4, iclass 15, count 0 2006.168.08:06:12.26#ibcon#read 4, iclass 15, count 0 2006.168.08:06:12.26#ibcon#about to read 5, iclass 15, count 0 2006.168.08:06:12.26#ibcon#read 5, iclass 15, count 0 2006.168.08:06:12.26#ibcon#about to read 6, iclass 15, count 0 2006.168.08:06:12.26#ibcon#read 6, iclass 15, count 0 2006.168.08:06:12.26#ibcon#end of sib2, iclass 15, count 0 2006.168.08:06:12.26#ibcon#*after write, iclass 15, count 0 2006.168.08:06:12.26#ibcon#*before return 0, iclass 15, count 0 2006.168.08:06:12.26#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.168.08:06:12.26#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.168.08:06:12.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.168.08:06:12.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.168.08:06:12.26$vc4f8/vblo=6,752.99 2006.168.08:06:12.26#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.168.08:06:12.26#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.168.08:06:12.26#ibcon#ireg 17 cls_cnt 0 2006.168.08:06:12.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:06:12.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:06:12.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:06:12.26#ibcon#enter wrdev, iclass 17, count 0 2006.168.08:06:12.26#ibcon#first serial, iclass 17, count 0 2006.168.08:06:12.26#ibcon#enter sib2, iclass 17, count 0 2006.168.08:06:12.26#ibcon#flushed, iclass 17, count 0 2006.168.08:06:12.26#ibcon#about to write, iclass 17, count 0 2006.168.08:06:12.26#ibcon#wrote, iclass 17, count 0 2006.168.08:06:12.26#ibcon#about to read 3, iclass 17, count 0 2006.168.08:06:12.28#ibcon#read 3, iclass 17, count 0 2006.168.08:06:12.28#ibcon#about to read 4, iclass 17, count 0 2006.168.08:06:12.28#ibcon#read 4, iclass 17, count 0 2006.168.08:06:12.28#ibcon#about to read 5, iclass 17, count 0 2006.168.08:06:12.28#ibcon#read 5, iclass 17, count 0 2006.168.08:06:12.28#ibcon#about to read 6, iclass 17, count 0 2006.168.08:06:12.28#ibcon#read 6, iclass 17, count 0 2006.168.08:06:12.28#ibcon#end of sib2, iclass 17, count 0 2006.168.08:06:12.28#ibcon#*mode == 0, iclass 17, count 0 2006.168.08:06:12.28#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.168.08:06:12.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.08:06:12.28#ibcon#*before write, iclass 17, count 0 2006.168.08:06:12.28#ibcon#enter sib2, iclass 17, count 0 2006.168.08:06:12.28#ibcon#flushed, iclass 17, count 0 2006.168.08:06:12.28#ibcon#about to write, iclass 17, count 0 2006.168.08:06:12.28#ibcon#wrote, iclass 17, count 0 2006.168.08:06:12.28#ibcon#about to read 3, iclass 17, count 0 2006.168.08:06:12.32#ibcon#read 3, iclass 17, count 0 2006.168.08:06:12.32#ibcon#about to read 4, iclass 17, count 0 2006.168.08:06:12.32#ibcon#read 4, iclass 17, count 0 2006.168.08:06:12.32#ibcon#about to read 5, iclass 17, count 0 2006.168.08:06:12.32#ibcon#read 5, iclass 17, count 0 2006.168.08:06:12.32#ibcon#about to read 6, iclass 17, count 0 2006.168.08:06:12.32#ibcon#read 6, iclass 17, count 0 2006.168.08:06:12.32#ibcon#end of sib2, iclass 17, count 0 2006.168.08:06:12.32#ibcon#*after write, iclass 17, count 0 2006.168.08:06:12.32#ibcon#*before return 0, iclass 17, count 0 2006.168.08:06:12.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:06:12.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:06:12.32#ibcon#about to clear, iclass 17 cls_cnt 0 2006.168.08:06:12.32#ibcon#cleared, iclass 17 cls_cnt 0 2006.168.08:06:12.32$vc4f8/vb=6,4 2006.168.08:06:12.32#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.168.08:06:12.32#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.168.08:06:12.32#ibcon#ireg 11 cls_cnt 2 2006.168.08:06:12.32#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:06:12.38#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:06:12.38#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:06:12.38#ibcon#enter wrdev, iclass 19, count 2 2006.168.08:06:12.38#ibcon#first serial, iclass 19, count 2 2006.168.08:06:12.38#ibcon#enter sib2, iclass 19, count 2 2006.168.08:06:12.38#ibcon#flushed, iclass 19, count 2 2006.168.08:06:12.38#ibcon#about to write, iclass 19, count 2 2006.168.08:06:12.38#ibcon#wrote, iclass 19, count 2 2006.168.08:06:12.38#ibcon#about to read 3, iclass 19, count 2 2006.168.08:06:12.40#ibcon#read 3, iclass 19, count 2 2006.168.08:06:12.40#ibcon#about to read 4, iclass 19, count 2 2006.168.08:06:12.40#ibcon#read 4, iclass 19, count 2 2006.168.08:06:12.40#ibcon#about to read 5, iclass 19, count 2 2006.168.08:06:12.40#ibcon#read 5, iclass 19, count 2 2006.168.08:06:12.40#ibcon#about to read 6, iclass 19, count 2 2006.168.08:06:12.40#ibcon#read 6, iclass 19, count 2 2006.168.08:06:12.40#ibcon#end of sib2, iclass 19, count 2 2006.168.08:06:12.40#ibcon#*mode == 0, iclass 19, count 2 2006.168.08:06:12.40#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.168.08:06:12.40#ibcon#[27=AT06-04\r\n] 2006.168.08:06:12.40#ibcon#*before write, iclass 19, count 2 2006.168.08:06:12.40#ibcon#enter sib2, iclass 19, count 2 2006.168.08:06:12.40#ibcon#flushed, iclass 19, count 2 2006.168.08:06:12.40#ibcon#about to write, iclass 19, count 2 2006.168.08:06:12.40#ibcon#wrote, iclass 19, count 2 2006.168.08:06:12.40#ibcon#about to read 3, iclass 19, count 2 2006.168.08:06:12.43#ibcon#read 3, iclass 19, count 2 2006.168.08:06:12.43#ibcon#about to read 4, iclass 19, count 2 2006.168.08:06:12.43#ibcon#read 4, iclass 19, count 2 2006.168.08:06:12.43#ibcon#about to read 5, iclass 19, count 2 2006.168.08:06:12.43#ibcon#read 5, iclass 19, count 2 2006.168.08:06:12.43#ibcon#about to read 6, iclass 19, count 2 2006.168.08:06:12.43#ibcon#read 6, iclass 19, count 2 2006.168.08:06:12.43#ibcon#end of sib2, iclass 19, count 2 2006.168.08:06:12.43#ibcon#*after write, iclass 19, count 2 2006.168.08:06:12.43#ibcon#*before return 0, iclass 19, count 2 2006.168.08:06:12.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:06:12.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:06:12.43#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.168.08:06:12.43#ibcon#ireg 7 cls_cnt 0 2006.168.08:06:12.43#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:06:12.55#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:06:12.55#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:06:12.55#ibcon#enter wrdev, iclass 19, count 0 2006.168.08:06:12.55#ibcon#first serial, iclass 19, count 0 2006.168.08:06:12.55#ibcon#enter sib2, iclass 19, count 0 2006.168.08:06:12.55#ibcon#flushed, iclass 19, count 0 2006.168.08:06:12.55#ibcon#about to write, iclass 19, count 0 2006.168.08:06:12.55#ibcon#wrote, iclass 19, count 0 2006.168.08:06:12.55#ibcon#about to read 3, iclass 19, count 0 2006.168.08:06:12.57#ibcon#read 3, iclass 19, count 0 2006.168.08:06:12.57#ibcon#about to read 4, iclass 19, count 0 2006.168.08:06:12.57#ibcon#read 4, iclass 19, count 0 2006.168.08:06:12.57#ibcon#about to read 5, iclass 19, count 0 2006.168.08:06:12.57#ibcon#read 5, iclass 19, count 0 2006.168.08:06:12.57#ibcon#about to read 6, iclass 19, count 0 2006.168.08:06:12.57#ibcon#read 6, iclass 19, count 0 2006.168.08:06:12.57#ibcon#end of sib2, iclass 19, count 0 2006.168.08:06:12.57#ibcon#*mode == 0, iclass 19, count 0 2006.168.08:06:12.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.168.08:06:12.57#ibcon#[27=USB\r\n] 2006.168.08:06:12.57#ibcon#*before write, iclass 19, count 0 2006.168.08:06:12.57#ibcon#enter sib2, iclass 19, count 0 2006.168.08:06:12.57#ibcon#flushed, iclass 19, count 0 2006.168.08:06:12.57#ibcon#about to write, iclass 19, count 0 2006.168.08:06:12.57#ibcon#wrote, iclass 19, count 0 2006.168.08:06:12.57#ibcon#about to read 3, iclass 19, count 0 2006.168.08:06:12.60#ibcon#read 3, iclass 19, count 0 2006.168.08:06:12.60#ibcon#about to read 4, iclass 19, count 0 2006.168.08:06:12.60#ibcon#read 4, iclass 19, count 0 2006.168.08:06:12.60#ibcon#about to read 5, iclass 19, count 0 2006.168.08:06:12.60#ibcon#read 5, iclass 19, count 0 2006.168.08:06:12.60#ibcon#about to read 6, iclass 19, count 0 2006.168.08:06:12.60#ibcon#read 6, iclass 19, count 0 2006.168.08:06:12.60#ibcon#end of sib2, iclass 19, count 0 2006.168.08:06:12.60#ibcon#*after write, iclass 19, count 0 2006.168.08:06:12.60#ibcon#*before return 0, iclass 19, count 0 2006.168.08:06:12.60#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:06:12.60#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:06:12.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.168.08:06:12.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.168.08:06:12.60$vc4f8/vabw=wide 2006.168.08:06:12.60#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.168.08:06:12.60#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.168.08:06:12.60#ibcon#ireg 8 cls_cnt 0 2006.168.08:06:12.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:06:12.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:06:12.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:06:12.60#ibcon#enter wrdev, iclass 21, count 0 2006.168.08:06:12.60#ibcon#first serial, iclass 21, count 0 2006.168.08:06:12.60#ibcon#enter sib2, iclass 21, count 0 2006.168.08:06:12.60#ibcon#flushed, iclass 21, count 0 2006.168.08:06:12.60#ibcon#about to write, iclass 21, count 0 2006.168.08:06:12.60#ibcon#wrote, iclass 21, count 0 2006.168.08:06:12.60#ibcon#about to read 3, iclass 21, count 0 2006.168.08:06:12.62#ibcon#read 3, iclass 21, count 0 2006.168.08:06:12.62#ibcon#about to read 4, iclass 21, count 0 2006.168.08:06:12.62#ibcon#read 4, iclass 21, count 0 2006.168.08:06:12.62#ibcon#about to read 5, iclass 21, count 0 2006.168.08:06:12.62#ibcon#read 5, iclass 21, count 0 2006.168.08:06:12.62#ibcon#about to read 6, iclass 21, count 0 2006.168.08:06:12.62#ibcon#read 6, iclass 21, count 0 2006.168.08:06:12.62#ibcon#end of sib2, iclass 21, count 0 2006.168.08:06:12.62#ibcon#*mode == 0, iclass 21, count 0 2006.168.08:06:12.62#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.168.08:06:12.62#ibcon#[25=BW32\r\n] 2006.168.08:06:12.62#ibcon#*before write, iclass 21, count 0 2006.168.08:06:12.62#ibcon#enter sib2, iclass 21, count 0 2006.168.08:06:12.62#ibcon#flushed, iclass 21, count 0 2006.168.08:06:12.62#ibcon#about to write, iclass 21, count 0 2006.168.08:06:12.62#ibcon#wrote, iclass 21, count 0 2006.168.08:06:12.62#ibcon#about to read 3, iclass 21, count 0 2006.168.08:06:12.65#ibcon#read 3, iclass 21, count 0 2006.168.08:06:12.65#ibcon#about to read 4, iclass 21, count 0 2006.168.08:06:12.65#ibcon#read 4, iclass 21, count 0 2006.168.08:06:12.65#ibcon#about to read 5, iclass 21, count 0 2006.168.08:06:12.65#ibcon#read 5, iclass 21, count 0 2006.168.08:06:12.65#ibcon#about to read 6, iclass 21, count 0 2006.168.08:06:12.65#ibcon#read 6, iclass 21, count 0 2006.168.08:06:12.65#ibcon#end of sib2, iclass 21, count 0 2006.168.08:06:12.65#ibcon#*after write, iclass 21, count 0 2006.168.08:06:12.65#ibcon#*before return 0, iclass 21, count 0 2006.168.08:06:12.65#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:06:12.65#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:06:12.65#ibcon#about to clear, iclass 21 cls_cnt 0 2006.168.08:06:12.65#ibcon#cleared, iclass 21 cls_cnt 0 2006.168.08:06:12.65$vc4f8/vbbw=wide 2006.168.08:06:12.65#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.168.08:06:12.65#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.168.08:06:12.65#ibcon#ireg 8 cls_cnt 0 2006.168.08:06:12.65#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:06:12.72#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:06:12.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:06:12.72#ibcon#enter wrdev, iclass 23, count 0 2006.168.08:06:12.72#ibcon#first serial, iclass 23, count 0 2006.168.08:06:12.72#ibcon#enter sib2, iclass 23, count 0 2006.168.08:06:12.72#ibcon#flushed, iclass 23, count 0 2006.168.08:06:12.72#ibcon#about to write, iclass 23, count 0 2006.168.08:06:12.72#ibcon#wrote, iclass 23, count 0 2006.168.08:06:12.72#ibcon#about to read 3, iclass 23, count 0 2006.168.08:06:12.74#ibcon#read 3, iclass 23, count 0 2006.168.08:06:12.74#ibcon#about to read 4, iclass 23, count 0 2006.168.08:06:12.74#ibcon#read 4, iclass 23, count 0 2006.168.08:06:12.74#ibcon#about to read 5, iclass 23, count 0 2006.168.08:06:12.74#ibcon#read 5, iclass 23, count 0 2006.168.08:06:12.74#ibcon#about to read 6, iclass 23, count 0 2006.168.08:06:12.74#ibcon#read 6, iclass 23, count 0 2006.168.08:06:12.74#ibcon#end of sib2, iclass 23, count 0 2006.168.08:06:12.74#ibcon#*mode == 0, iclass 23, count 0 2006.168.08:06:12.74#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.168.08:06:12.74#ibcon#[27=BW32\r\n] 2006.168.08:06:12.74#ibcon#*before write, iclass 23, count 0 2006.168.08:06:12.74#ibcon#enter sib2, iclass 23, count 0 2006.168.08:06:12.74#ibcon#flushed, iclass 23, count 0 2006.168.08:06:12.74#ibcon#about to write, iclass 23, count 0 2006.168.08:06:12.74#ibcon#wrote, iclass 23, count 0 2006.168.08:06:12.74#ibcon#about to read 3, iclass 23, count 0 2006.168.08:06:12.77#ibcon#read 3, iclass 23, count 0 2006.168.08:06:12.77#ibcon#about to read 4, iclass 23, count 0 2006.168.08:06:12.77#ibcon#read 4, iclass 23, count 0 2006.168.08:06:12.77#ibcon#about to read 5, iclass 23, count 0 2006.168.08:06:12.77#ibcon#read 5, iclass 23, count 0 2006.168.08:06:12.77#ibcon#about to read 6, iclass 23, count 0 2006.168.08:06:12.77#ibcon#read 6, iclass 23, count 0 2006.168.08:06:12.77#ibcon#end of sib2, iclass 23, count 0 2006.168.08:06:12.77#ibcon#*after write, iclass 23, count 0 2006.168.08:06:12.77#ibcon#*before return 0, iclass 23, count 0 2006.168.08:06:12.77#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:06:12.77#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:06:12.77#ibcon#about to clear, iclass 23 cls_cnt 0 2006.168.08:06:12.77#ibcon#cleared, iclass 23 cls_cnt 0 2006.168.08:06:12.77$4f8m12a/ifd4f 2006.168.08:06:12.77$ifd4f/lo= 2006.168.08:06:12.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.08:06:12.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.08:06:12.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.08:06:12.77$ifd4f/patch= 2006.168.08:06:12.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.08:06:12.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.08:06:12.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.08:06:12.77$4f8m12a/"form=m,16.000,1:2 2006.168.08:06:12.77$4f8m12a/"tpicd 2006.168.08:06:12.77$4f8m12a/echo=off 2006.168.08:06:12.77$4f8m12a/xlog=off 2006.168.08:06:12.77:!2006.168.08:06:40 2006.168.08:06:24.14#trakl#Source acquired 2006.168.08:06:25.14#flagr#flagr/antenna,acquired 2006.168.08:06:40.00:preob 2006.168.08:06:41.14/onsource/TRACKING 2006.168.08:06:41.14:!2006.168.08:06:50 2006.168.08:06:50.00:data_valid=on 2006.168.08:06:50.00:midob 2006.168.08:06:50.14/onsource/TRACKING 2006.168.08:06:50.14/wx/26.97,1004.4,73 2006.168.08:06:50.21/cable/+6.4720E-03 2006.168.08:06:51.30/va/01,08,usb,yes,29,31 2006.168.08:06:51.30/va/02,07,usb,yes,30,31 2006.168.08:06:51.30/va/03,06,usb,yes,31,31 2006.168.08:06:51.30/va/04,07,usb,yes,30,33 2006.168.08:06:51.30/va/05,07,usb,yes,30,32 2006.168.08:06:51.30/va/06,06,usb,yes,29,29 2006.168.08:06:51.30/va/07,06,usb,yes,30,30 2006.168.08:06:51.30/va/08,07,usb,yes,28,28 2006.168.08:06:51.53/valo/01,532.99,yes,locked 2006.168.08:06:51.53/valo/02,572.99,yes,locked 2006.168.08:06:51.53/valo/03,672.99,yes,locked 2006.168.08:06:51.53/valo/04,832.99,yes,locked 2006.168.08:06:51.53/valo/05,652.99,yes,locked 2006.168.08:06:51.53/valo/06,772.99,yes,locked 2006.168.08:06:51.53/valo/07,832.99,yes,locked 2006.168.08:06:51.53/valo/08,852.99,yes,locked 2006.168.08:06:52.62/vb/01,04,usb,yes,29,28 2006.168.08:06:52.62/vb/02,04,usb,yes,31,32 2006.168.08:06:52.62/vb/03,04,usb,yes,27,31 2006.168.08:06:52.62/vb/04,04,usb,yes,28,28 2006.168.08:06:52.62/vb/05,04,usb,yes,27,31 2006.168.08:06:52.62/vb/06,04,usb,yes,28,31 2006.168.08:06:52.62/vb/07,04,usb,yes,30,30 2006.168.08:06:52.62/vb/08,04,usb,yes,28,31 2006.168.08:06:52.85/vblo/01,632.99,yes,locked 2006.168.08:06:52.85/vblo/02,640.99,yes,locked 2006.168.08:06:52.85/vblo/03,656.99,yes,locked 2006.168.08:06:52.85/vblo/04,712.99,yes,locked 2006.168.08:06:52.85/vblo/05,744.99,yes,locked 2006.168.08:06:52.85/vblo/06,752.99,yes,locked 2006.168.08:06:52.85/vblo/07,734.99,yes,locked 2006.168.08:06:52.85/vblo/08,744.99,yes,locked 2006.168.08:06:53.00/vabw/8 2006.168.08:06:53.15/vbbw/8 2006.168.08:06:53.24/xfe/off,on,14.2 2006.168.08:06:53.62/ifatt/23,28,28,28 2006.168.08:06:54.07/fmout-gps/S +4.19E-07 2006.168.08:06:54.11:!2006.168.08:07:50 2006.168.08:07:50.00:data_valid=off 2006.168.08:07:50.00:postob 2006.168.08:07:50.16/cable/+6.4709E-03 2006.168.08:07:50.16/wx/26.97,1004.4,75 2006.168.08:07:51.07/fmout-gps/S +4.18E-07 2006.168.08:07:51.07:scan_name=168-0808,k06168,60 2006.168.08:07:51.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.168.08:07:51.14#flagr#flagr/antenna,new-source 2006.168.08:07:52.14:checkk5 2006.168.08:07:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.168.08:07:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.168.08:07:53.28/chk_autoobs//k5ts3/ autoobs is running! 2006.168.08:07:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.168.08:07:54.02/chk_obsdata//k5ts1/T1680806??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:07:54.40/chk_obsdata//k5ts2/T1680806??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:07:54.77/chk_obsdata//k5ts3/T1680806??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:07:55.14/chk_obsdata//k5ts4/T1680806??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:07:55.83/k5log//k5ts1_log_newline 2006.168.08:07:56.52/k5log//k5ts2_log_newline 2006.168.08:07:57.22/k5log//k5ts3_log_newline 2006.168.08:07:57.91/k5log//k5ts4_log_newline 2006.168.08:07:57.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.08:07:57.93:4f8m12a=2 2006.168.08:07:57.93$4f8m12a/echo=on 2006.168.08:07:57.93$4f8m12a/pcalon 2006.168.08:07:57.93$pcalon/"no phase cal control is implemented here 2006.168.08:07:57.93$4f8m12a/"tpicd=stop 2006.168.08:07:57.93$4f8m12a/vc4f8 2006.168.08:07:57.93$vc4f8/valo=1,532.99 2006.168.08:07:57.93#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.168.08:07:57.93#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.168.08:07:57.93#ibcon#ireg 17 cls_cnt 0 2006.168.08:07:57.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:07:57.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:07:57.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:07:57.93#ibcon#enter wrdev, iclass 34, count 0 2006.168.08:07:57.93#ibcon#first serial, iclass 34, count 0 2006.168.08:07:57.93#ibcon#enter sib2, iclass 34, count 0 2006.168.08:07:57.93#ibcon#flushed, iclass 34, count 0 2006.168.08:07:57.93#ibcon#about to write, iclass 34, count 0 2006.168.08:07:57.93#ibcon#wrote, iclass 34, count 0 2006.168.08:07:57.93#ibcon#about to read 3, iclass 34, count 0 2006.168.08:07:57.98#ibcon#read 3, iclass 34, count 0 2006.168.08:07:57.98#ibcon#about to read 4, iclass 34, count 0 2006.168.08:07:57.98#ibcon#read 4, iclass 34, count 0 2006.168.08:07:57.98#ibcon#about to read 5, iclass 34, count 0 2006.168.08:07:57.98#ibcon#read 5, iclass 34, count 0 2006.168.08:07:57.98#ibcon#about to read 6, iclass 34, count 0 2006.168.08:07:57.98#ibcon#read 6, iclass 34, count 0 2006.168.08:07:57.98#ibcon#end of sib2, iclass 34, count 0 2006.168.08:07:57.98#ibcon#*mode == 0, iclass 34, count 0 2006.168.08:07:57.98#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.168.08:07:57.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.08:07:57.98#ibcon#*before write, iclass 34, count 0 2006.168.08:07:57.98#ibcon#enter sib2, iclass 34, count 0 2006.168.08:07:57.98#ibcon#flushed, iclass 34, count 0 2006.168.08:07:57.98#ibcon#about to write, iclass 34, count 0 2006.168.08:07:57.98#ibcon#wrote, iclass 34, count 0 2006.168.08:07:57.98#ibcon#about to read 3, iclass 34, count 0 2006.168.08:07:58.03#ibcon#read 3, iclass 34, count 0 2006.168.08:07:58.03#ibcon#about to read 4, iclass 34, count 0 2006.168.08:07:58.03#ibcon#read 4, iclass 34, count 0 2006.168.08:07:58.03#ibcon#about to read 5, iclass 34, count 0 2006.168.08:07:58.03#ibcon#read 5, iclass 34, count 0 2006.168.08:07:58.03#ibcon#about to read 6, iclass 34, count 0 2006.168.08:07:58.03#ibcon#read 6, iclass 34, count 0 2006.168.08:07:58.03#ibcon#end of sib2, iclass 34, count 0 2006.168.08:07:58.03#ibcon#*after write, iclass 34, count 0 2006.168.08:07:58.03#ibcon#*before return 0, iclass 34, count 0 2006.168.08:07:58.03#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:07:58.03#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:07:58.03#ibcon#about to clear, iclass 34 cls_cnt 0 2006.168.08:07:58.03#ibcon#cleared, iclass 34 cls_cnt 0 2006.168.08:07:58.03$vc4f8/va=1,8 2006.168.08:07:58.03#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.168.08:07:58.03#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.168.08:07:58.03#ibcon#ireg 11 cls_cnt 2 2006.168.08:07:58.03#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:07:58.03#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:07:58.03#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:07:58.03#ibcon#enter wrdev, iclass 36, count 2 2006.168.08:07:58.03#ibcon#first serial, iclass 36, count 2 2006.168.08:07:58.03#ibcon#enter sib2, iclass 36, count 2 2006.168.08:07:58.03#ibcon#flushed, iclass 36, count 2 2006.168.08:07:58.03#ibcon#about to write, iclass 36, count 2 2006.168.08:07:58.03#ibcon#wrote, iclass 36, count 2 2006.168.08:07:58.03#ibcon#about to read 3, iclass 36, count 2 2006.168.08:07:58.05#ibcon#read 3, iclass 36, count 2 2006.168.08:07:58.05#ibcon#about to read 4, iclass 36, count 2 2006.168.08:07:58.05#ibcon#read 4, iclass 36, count 2 2006.168.08:07:58.05#ibcon#about to read 5, iclass 36, count 2 2006.168.08:07:58.05#ibcon#read 5, iclass 36, count 2 2006.168.08:07:58.05#ibcon#about to read 6, iclass 36, count 2 2006.168.08:07:58.05#ibcon#read 6, iclass 36, count 2 2006.168.08:07:58.05#ibcon#end of sib2, iclass 36, count 2 2006.168.08:07:58.05#ibcon#*mode == 0, iclass 36, count 2 2006.168.08:07:58.05#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.168.08:07:58.05#ibcon#[25=AT01-08\r\n] 2006.168.08:07:58.05#ibcon#*before write, iclass 36, count 2 2006.168.08:07:58.05#ibcon#enter sib2, iclass 36, count 2 2006.168.08:07:58.05#ibcon#flushed, iclass 36, count 2 2006.168.08:07:58.06#ibcon#about to write, iclass 36, count 2 2006.168.08:07:58.06#ibcon#wrote, iclass 36, count 2 2006.168.08:07:58.06#ibcon#about to read 3, iclass 36, count 2 2006.168.08:07:58.09#ibcon#read 3, iclass 36, count 2 2006.168.08:07:58.09#ibcon#about to read 4, iclass 36, count 2 2006.168.08:07:58.09#ibcon#read 4, iclass 36, count 2 2006.168.08:07:58.09#ibcon#about to read 5, iclass 36, count 2 2006.168.08:07:58.09#ibcon#read 5, iclass 36, count 2 2006.168.08:07:58.09#ibcon#about to read 6, iclass 36, count 2 2006.168.08:07:58.09#ibcon#read 6, iclass 36, count 2 2006.168.08:07:58.09#ibcon#end of sib2, iclass 36, count 2 2006.168.08:07:58.09#ibcon#*after write, iclass 36, count 2 2006.168.08:07:58.09#ibcon#*before return 0, iclass 36, count 2 2006.168.08:07:58.09#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:07:58.09#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:07:58.09#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.168.08:07:58.09#ibcon#ireg 7 cls_cnt 0 2006.168.08:07:58.09#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:07:58.21#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:07:58.21#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:07:58.21#ibcon#enter wrdev, iclass 36, count 0 2006.168.08:07:58.21#ibcon#first serial, iclass 36, count 0 2006.168.08:07:58.21#ibcon#enter sib2, iclass 36, count 0 2006.168.08:07:58.21#ibcon#flushed, iclass 36, count 0 2006.168.08:07:58.21#ibcon#about to write, iclass 36, count 0 2006.168.08:07:58.21#ibcon#wrote, iclass 36, count 0 2006.168.08:07:58.21#ibcon#about to read 3, iclass 36, count 0 2006.168.08:07:58.23#ibcon#read 3, iclass 36, count 0 2006.168.08:07:58.23#ibcon#about to read 4, iclass 36, count 0 2006.168.08:07:58.23#ibcon#read 4, iclass 36, count 0 2006.168.08:07:58.23#ibcon#about to read 5, iclass 36, count 0 2006.168.08:07:58.23#ibcon#read 5, iclass 36, count 0 2006.168.08:07:58.23#ibcon#about to read 6, iclass 36, count 0 2006.168.08:07:58.23#ibcon#read 6, iclass 36, count 0 2006.168.08:07:58.23#ibcon#end of sib2, iclass 36, count 0 2006.168.08:07:58.23#ibcon#*mode == 0, iclass 36, count 0 2006.168.08:07:58.23#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.168.08:07:58.23#ibcon#[25=USB\r\n] 2006.168.08:07:58.23#ibcon#*before write, iclass 36, count 0 2006.168.08:07:58.23#ibcon#enter sib2, iclass 36, count 0 2006.168.08:07:58.23#ibcon#flushed, iclass 36, count 0 2006.168.08:07:58.23#ibcon#about to write, iclass 36, count 0 2006.168.08:07:58.23#ibcon#wrote, iclass 36, count 0 2006.168.08:07:58.23#ibcon#about to read 3, iclass 36, count 0 2006.168.08:07:58.26#ibcon#read 3, iclass 36, count 0 2006.168.08:07:58.26#ibcon#about to read 4, iclass 36, count 0 2006.168.08:07:58.26#ibcon#read 4, iclass 36, count 0 2006.168.08:07:58.26#ibcon#about to read 5, iclass 36, count 0 2006.168.08:07:58.26#ibcon#read 5, iclass 36, count 0 2006.168.08:07:58.26#ibcon#about to read 6, iclass 36, count 0 2006.168.08:07:58.26#ibcon#read 6, iclass 36, count 0 2006.168.08:07:58.26#ibcon#end of sib2, iclass 36, count 0 2006.168.08:07:58.26#ibcon#*after write, iclass 36, count 0 2006.168.08:07:58.26#ibcon#*before return 0, iclass 36, count 0 2006.168.08:07:58.26#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:07:58.26#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:07:58.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.168.08:07:58.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.168.08:07:58.26$vc4f8/valo=2,572.99 2006.168.08:07:58.26#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.168.08:07:58.26#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.168.08:07:58.26#ibcon#ireg 17 cls_cnt 0 2006.168.08:07:58.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:07:58.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:07:58.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:07:58.26#ibcon#enter wrdev, iclass 38, count 0 2006.168.08:07:58.26#ibcon#first serial, iclass 38, count 0 2006.168.08:07:58.26#ibcon#enter sib2, iclass 38, count 0 2006.168.08:07:58.26#ibcon#flushed, iclass 38, count 0 2006.168.08:07:58.26#ibcon#about to write, iclass 38, count 0 2006.168.08:07:58.26#ibcon#wrote, iclass 38, count 0 2006.168.08:07:58.26#ibcon#about to read 3, iclass 38, count 0 2006.168.08:07:58.28#ibcon#read 3, iclass 38, count 0 2006.168.08:07:58.28#ibcon#about to read 4, iclass 38, count 0 2006.168.08:07:58.28#ibcon#read 4, iclass 38, count 0 2006.168.08:07:58.28#ibcon#about to read 5, iclass 38, count 0 2006.168.08:07:58.28#ibcon#read 5, iclass 38, count 0 2006.168.08:07:58.28#ibcon#about to read 6, iclass 38, count 0 2006.168.08:07:58.28#ibcon#read 6, iclass 38, count 0 2006.168.08:07:58.28#ibcon#end of sib2, iclass 38, count 0 2006.168.08:07:58.28#ibcon#*mode == 0, iclass 38, count 0 2006.168.08:07:58.28#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.168.08:07:58.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.08:07:58.28#ibcon#*before write, iclass 38, count 0 2006.168.08:07:58.28#ibcon#enter sib2, iclass 38, count 0 2006.168.08:07:58.28#ibcon#flushed, iclass 38, count 0 2006.168.08:07:58.28#ibcon#about to write, iclass 38, count 0 2006.168.08:07:58.28#ibcon#wrote, iclass 38, count 0 2006.168.08:07:58.28#ibcon#about to read 3, iclass 38, count 0 2006.168.08:07:58.32#ibcon#read 3, iclass 38, count 0 2006.168.08:07:58.32#ibcon#about to read 4, iclass 38, count 0 2006.168.08:07:58.32#ibcon#read 4, iclass 38, count 0 2006.168.08:07:58.32#ibcon#about to read 5, iclass 38, count 0 2006.168.08:07:58.32#ibcon#read 5, iclass 38, count 0 2006.168.08:07:58.32#ibcon#about to read 6, iclass 38, count 0 2006.168.08:07:58.32#ibcon#read 6, iclass 38, count 0 2006.168.08:07:58.32#ibcon#end of sib2, iclass 38, count 0 2006.168.08:07:58.32#ibcon#*after write, iclass 38, count 0 2006.168.08:07:58.32#ibcon#*before return 0, iclass 38, count 0 2006.168.08:07:58.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:07:58.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:07:58.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.168.08:07:58.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.168.08:07:58.32$vc4f8/va=2,7 2006.168.08:07:58.32#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.168.08:07:58.32#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.168.08:07:58.32#ibcon#ireg 11 cls_cnt 2 2006.168.08:07:58.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:07:58.39#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:07:58.39#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:07:58.39#ibcon#enter wrdev, iclass 40, count 2 2006.168.08:07:58.39#ibcon#first serial, iclass 40, count 2 2006.168.08:07:58.39#ibcon#enter sib2, iclass 40, count 2 2006.168.08:07:58.39#ibcon#flushed, iclass 40, count 2 2006.168.08:07:58.39#ibcon#about to write, iclass 40, count 2 2006.168.08:07:58.39#ibcon#wrote, iclass 40, count 2 2006.168.08:07:58.39#ibcon#about to read 3, iclass 40, count 2 2006.168.08:07:58.40#ibcon#read 3, iclass 40, count 2 2006.168.08:07:58.40#ibcon#about to read 4, iclass 40, count 2 2006.168.08:07:58.40#ibcon#read 4, iclass 40, count 2 2006.168.08:07:58.40#ibcon#about to read 5, iclass 40, count 2 2006.168.08:07:58.40#ibcon#read 5, iclass 40, count 2 2006.168.08:07:58.40#ibcon#about to read 6, iclass 40, count 2 2006.168.08:07:58.40#ibcon#read 6, iclass 40, count 2 2006.168.08:07:58.40#ibcon#end of sib2, iclass 40, count 2 2006.168.08:07:58.40#ibcon#*mode == 0, iclass 40, count 2 2006.168.08:07:58.40#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.168.08:07:58.40#ibcon#[25=AT02-07\r\n] 2006.168.08:07:58.40#ibcon#*before write, iclass 40, count 2 2006.168.08:07:58.40#ibcon#enter sib2, iclass 40, count 2 2006.168.08:07:58.40#ibcon#flushed, iclass 40, count 2 2006.168.08:07:58.40#ibcon#about to write, iclass 40, count 2 2006.168.08:07:58.40#ibcon#wrote, iclass 40, count 2 2006.168.08:07:58.40#ibcon#about to read 3, iclass 40, count 2 2006.168.08:07:58.43#ibcon#read 3, iclass 40, count 2 2006.168.08:07:58.43#ibcon#about to read 4, iclass 40, count 2 2006.168.08:07:58.43#ibcon#read 4, iclass 40, count 2 2006.168.08:07:58.43#ibcon#about to read 5, iclass 40, count 2 2006.168.08:07:58.43#ibcon#read 5, iclass 40, count 2 2006.168.08:07:58.43#ibcon#about to read 6, iclass 40, count 2 2006.168.08:07:58.43#ibcon#read 6, iclass 40, count 2 2006.168.08:07:58.43#ibcon#end of sib2, iclass 40, count 2 2006.168.08:07:58.43#ibcon#*after write, iclass 40, count 2 2006.168.08:07:58.43#ibcon#*before return 0, iclass 40, count 2 2006.168.08:07:58.43#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:07:58.43#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:07:58.43#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.168.08:07:58.43#ibcon#ireg 7 cls_cnt 0 2006.168.08:07:58.43#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:07:58.55#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:07:58.55#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:07:58.55#ibcon#enter wrdev, iclass 40, count 0 2006.168.08:07:58.55#ibcon#first serial, iclass 40, count 0 2006.168.08:07:58.55#ibcon#enter sib2, iclass 40, count 0 2006.168.08:07:58.55#ibcon#flushed, iclass 40, count 0 2006.168.08:07:58.55#ibcon#about to write, iclass 40, count 0 2006.168.08:07:58.55#ibcon#wrote, iclass 40, count 0 2006.168.08:07:58.55#ibcon#about to read 3, iclass 40, count 0 2006.168.08:07:58.57#ibcon#read 3, iclass 40, count 0 2006.168.08:07:58.57#ibcon#about to read 4, iclass 40, count 0 2006.168.08:07:58.57#ibcon#read 4, iclass 40, count 0 2006.168.08:07:58.57#ibcon#about to read 5, iclass 40, count 0 2006.168.08:07:58.57#ibcon#read 5, iclass 40, count 0 2006.168.08:07:58.57#ibcon#about to read 6, iclass 40, count 0 2006.168.08:07:58.57#ibcon#read 6, iclass 40, count 0 2006.168.08:07:58.57#ibcon#end of sib2, iclass 40, count 0 2006.168.08:07:58.57#ibcon#*mode == 0, iclass 40, count 0 2006.168.08:07:58.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.168.08:07:58.57#ibcon#[25=USB\r\n] 2006.168.08:07:58.57#ibcon#*before write, iclass 40, count 0 2006.168.08:07:58.57#ibcon#enter sib2, iclass 40, count 0 2006.168.08:07:58.57#ibcon#flushed, iclass 40, count 0 2006.168.08:07:58.57#ibcon#about to write, iclass 40, count 0 2006.168.08:07:58.57#ibcon#wrote, iclass 40, count 0 2006.168.08:07:58.57#ibcon#about to read 3, iclass 40, count 0 2006.168.08:07:58.60#ibcon#read 3, iclass 40, count 0 2006.168.08:07:58.60#ibcon#about to read 4, iclass 40, count 0 2006.168.08:07:58.60#ibcon#read 4, iclass 40, count 0 2006.168.08:07:58.60#ibcon#about to read 5, iclass 40, count 0 2006.168.08:07:58.60#ibcon#read 5, iclass 40, count 0 2006.168.08:07:58.60#ibcon#about to read 6, iclass 40, count 0 2006.168.08:07:58.60#ibcon#read 6, iclass 40, count 0 2006.168.08:07:58.60#ibcon#end of sib2, iclass 40, count 0 2006.168.08:07:58.60#ibcon#*after write, iclass 40, count 0 2006.168.08:07:58.60#ibcon#*before return 0, iclass 40, count 0 2006.168.08:07:58.60#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:07:58.60#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:07:58.60#ibcon#about to clear, iclass 40 cls_cnt 0 2006.168.08:07:58.60#ibcon#cleared, iclass 40 cls_cnt 0 2006.168.08:07:58.60$vc4f8/valo=3,672.99 2006.168.08:07:58.60#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.168.08:07:58.60#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.168.08:07:58.60#ibcon#ireg 17 cls_cnt 0 2006.168.08:07:58.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:07:58.60#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:07:58.60#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:07:58.60#ibcon#enter wrdev, iclass 4, count 0 2006.168.08:07:58.60#ibcon#first serial, iclass 4, count 0 2006.168.08:07:58.60#ibcon#enter sib2, iclass 4, count 0 2006.168.08:07:58.60#ibcon#flushed, iclass 4, count 0 2006.168.08:07:58.60#ibcon#about to write, iclass 4, count 0 2006.168.08:07:58.60#ibcon#wrote, iclass 4, count 0 2006.168.08:07:58.60#ibcon#about to read 3, iclass 4, count 0 2006.168.08:07:58.62#ibcon#read 3, iclass 4, count 0 2006.168.08:07:58.62#ibcon#about to read 4, iclass 4, count 0 2006.168.08:07:58.62#ibcon#read 4, iclass 4, count 0 2006.168.08:07:58.62#ibcon#about to read 5, iclass 4, count 0 2006.168.08:07:58.62#ibcon#read 5, iclass 4, count 0 2006.168.08:07:58.62#ibcon#about to read 6, iclass 4, count 0 2006.168.08:07:58.62#ibcon#read 6, iclass 4, count 0 2006.168.08:07:58.62#ibcon#end of sib2, iclass 4, count 0 2006.168.08:07:58.62#ibcon#*mode == 0, iclass 4, count 0 2006.168.08:07:58.62#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.168.08:07:58.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.08:07:58.62#ibcon#*before write, iclass 4, count 0 2006.168.08:07:58.62#ibcon#enter sib2, iclass 4, count 0 2006.168.08:07:58.62#ibcon#flushed, iclass 4, count 0 2006.168.08:07:58.62#ibcon#about to write, iclass 4, count 0 2006.168.08:07:58.62#ibcon#wrote, iclass 4, count 0 2006.168.08:07:58.62#ibcon#about to read 3, iclass 4, count 0 2006.168.08:07:58.66#ibcon#read 3, iclass 4, count 0 2006.168.08:07:58.66#ibcon#about to read 4, iclass 4, count 0 2006.168.08:07:58.66#ibcon#read 4, iclass 4, count 0 2006.168.08:07:58.66#ibcon#about to read 5, iclass 4, count 0 2006.168.08:07:58.66#ibcon#read 5, iclass 4, count 0 2006.168.08:07:58.66#ibcon#about to read 6, iclass 4, count 0 2006.168.08:07:58.66#ibcon#read 6, iclass 4, count 0 2006.168.08:07:58.66#ibcon#end of sib2, iclass 4, count 0 2006.168.08:07:58.66#ibcon#*after write, iclass 4, count 0 2006.168.08:07:58.66#ibcon#*before return 0, iclass 4, count 0 2006.168.08:07:58.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:07:58.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:07:58.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.168.08:07:58.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.168.08:07:58.66$vc4f8/va=3,6 2006.168.08:07:58.66#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.168.08:07:58.66#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.168.08:07:58.66#ibcon#ireg 11 cls_cnt 2 2006.168.08:07:58.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:07:58.73#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:07:58.73#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:07:58.73#ibcon#enter wrdev, iclass 6, count 2 2006.168.08:07:58.73#ibcon#first serial, iclass 6, count 2 2006.168.08:07:58.73#ibcon#enter sib2, iclass 6, count 2 2006.168.08:07:58.73#ibcon#flushed, iclass 6, count 2 2006.168.08:07:58.73#ibcon#about to write, iclass 6, count 2 2006.168.08:07:58.73#ibcon#wrote, iclass 6, count 2 2006.168.08:07:58.73#ibcon#about to read 3, iclass 6, count 2 2006.168.08:07:58.74#ibcon#read 3, iclass 6, count 2 2006.168.08:07:58.74#ibcon#about to read 4, iclass 6, count 2 2006.168.08:07:58.74#ibcon#read 4, iclass 6, count 2 2006.168.08:07:58.74#ibcon#about to read 5, iclass 6, count 2 2006.168.08:07:58.74#ibcon#read 5, iclass 6, count 2 2006.168.08:07:58.74#ibcon#about to read 6, iclass 6, count 2 2006.168.08:07:58.74#ibcon#read 6, iclass 6, count 2 2006.168.08:07:58.74#ibcon#end of sib2, iclass 6, count 2 2006.168.08:07:58.74#ibcon#*mode == 0, iclass 6, count 2 2006.168.08:07:58.74#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.168.08:07:58.74#ibcon#[25=AT03-06\r\n] 2006.168.08:07:58.74#ibcon#*before write, iclass 6, count 2 2006.168.08:07:58.74#ibcon#enter sib2, iclass 6, count 2 2006.168.08:07:58.74#ibcon#flushed, iclass 6, count 2 2006.168.08:07:58.74#ibcon#about to write, iclass 6, count 2 2006.168.08:07:58.74#ibcon#wrote, iclass 6, count 2 2006.168.08:07:58.74#ibcon#about to read 3, iclass 6, count 2 2006.168.08:07:58.77#ibcon#read 3, iclass 6, count 2 2006.168.08:07:58.77#ibcon#about to read 4, iclass 6, count 2 2006.168.08:07:58.77#ibcon#read 4, iclass 6, count 2 2006.168.08:07:58.77#ibcon#about to read 5, iclass 6, count 2 2006.168.08:07:58.77#ibcon#read 5, iclass 6, count 2 2006.168.08:07:58.77#ibcon#about to read 6, iclass 6, count 2 2006.168.08:07:58.77#ibcon#read 6, iclass 6, count 2 2006.168.08:07:58.77#ibcon#end of sib2, iclass 6, count 2 2006.168.08:07:58.77#ibcon#*after write, iclass 6, count 2 2006.168.08:07:58.77#ibcon#*before return 0, iclass 6, count 2 2006.168.08:07:58.77#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:07:58.77#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:07:58.77#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.168.08:07:58.77#ibcon#ireg 7 cls_cnt 0 2006.168.08:07:58.77#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:07:58.89#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:07:58.89#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:07:58.89#ibcon#enter wrdev, iclass 6, count 0 2006.168.08:07:58.89#ibcon#first serial, iclass 6, count 0 2006.168.08:07:58.89#ibcon#enter sib2, iclass 6, count 0 2006.168.08:07:58.89#ibcon#flushed, iclass 6, count 0 2006.168.08:07:58.89#ibcon#about to write, iclass 6, count 0 2006.168.08:07:58.89#ibcon#wrote, iclass 6, count 0 2006.168.08:07:58.89#ibcon#about to read 3, iclass 6, count 0 2006.168.08:07:58.91#ibcon#read 3, iclass 6, count 0 2006.168.08:07:58.91#ibcon#about to read 4, iclass 6, count 0 2006.168.08:07:58.91#ibcon#read 4, iclass 6, count 0 2006.168.08:07:58.91#ibcon#about to read 5, iclass 6, count 0 2006.168.08:07:58.91#ibcon#read 5, iclass 6, count 0 2006.168.08:07:58.91#ibcon#about to read 6, iclass 6, count 0 2006.168.08:07:58.91#ibcon#read 6, iclass 6, count 0 2006.168.08:07:58.91#ibcon#end of sib2, iclass 6, count 0 2006.168.08:07:58.91#ibcon#*mode == 0, iclass 6, count 0 2006.168.08:07:58.91#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.168.08:07:58.91#ibcon#[25=USB\r\n] 2006.168.08:07:58.91#ibcon#*before write, iclass 6, count 0 2006.168.08:07:58.91#ibcon#enter sib2, iclass 6, count 0 2006.168.08:07:58.91#ibcon#flushed, iclass 6, count 0 2006.168.08:07:58.91#ibcon#about to write, iclass 6, count 0 2006.168.08:07:58.91#ibcon#wrote, iclass 6, count 0 2006.168.08:07:58.91#ibcon#about to read 3, iclass 6, count 0 2006.168.08:07:58.94#ibcon#read 3, iclass 6, count 0 2006.168.08:07:58.94#ibcon#about to read 4, iclass 6, count 0 2006.168.08:07:58.94#ibcon#read 4, iclass 6, count 0 2006.168.08:07:58.94#ibcon#about to read 5, iclass 6, count 0 2006.168.08:07:58.94#ibcon#read 5, iclass 6, count 0 2006.168.08:07:58.94#ibcon#about to read 6, iclass 6, count 0 2006.168.08:07:58.94#ibcon#read 6, iclass 6, count 0 2006.168.08:07:58.94#ibcon#end of sib2, iclass 6, count 0 2006.168.08:07:58.94#ibcon#*after write, iclass 6, count 0 2006.168.08:07:58.94#ibcon#*before return 0, iclass 6, count 0 2006.168.08:07:58.94#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:07:58.94#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:07:58.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.168.08:07:58.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.168.08:07:58.94$vc4f8/valo=4,832.99 2006.168.08:07:58.94#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.168.08:07:58.94#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.168.08:07:58.94#ibcon#ireg 17 cls_cnt 0 2006.168.08:07:58.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:07:58.94#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:07:58.94#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:07:58.94#ibcon#enter wrdev, iclass 10, count 0 2006.168.08:07:58.94#ibcon#first serial, iclass 10, count 0 2006.168.08:07:58.94#ibcon#enter sib2, iclass 10, count 0 2006.168.08:07:58.94#ibcon#flushed, iclass 10, count 0 2006.168.08:07:58.94#ibcon#about to write, iclass 10, count 0 2006.168.08:07:58.94#ibcon#wrote, iclass 10, count 0 2006.168.08:07:58.94#ibcon#about to read 3, iclass 10, count 0 2006.168.08:07:58.96#ibcon#read 3, iclass 10, count 0 2006.168.08:07:58.96#ibcon#about to read 4, iclass 10, count 0 2006.168.08:07:58.96#ibcon#read 4, iclass 10, count 0 2006.168.08:07:58.96#ibcon#about to read 5, iclass 10, count 0 2006.168.08:07:58.96#ibcon#read 5, iclass 10, count 0 2006.168.08:07:58.96#ibcon#about to read 6, iclass 10, count 0 2006.168.08:07:58.96#ibcon#read 6, iclass 10, count 0 2006.168.08:07:58.96#ibcon#end of sib2, iclass 10, count 0 2006.168.08:07:58.96#ibcon#*mode == 0, iclass 10, count 0 2006.168.08:07:58.96#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.168.08:07:58.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.08:07:58.96#ibcon#*before write, iclass 10, count 0 2006.168.08:07:58.96#ibcon#enter sib2, iclass 10, count 0 2006.168.08:07:58.96#ibcon#flushed, iclass 10, count 0 2006.168.08:07:58.96#ibcon#about to write, iclass 10, count 0 2006.168.08:07:58.96#ibcon#wrote, iclass 10, count 0 2006.168.08:07:58.96#ibcon#about to read 3, iclass 10, count 0 2006.168.08:07:59.00#ibcon#read 3, iclass 10, count 0 2006.168.08:07:59.00#ibcon#about to read 4, iclass 10, count 0 2006.168.08:07:59.00#ibcon#read 4, iclass 10, count 0 2006.168.08:07:59.00#ibcon#about to read 5, iclass 10, count 0 2006.168.08:07:59.00#ibcon#read 5, iclass 10, count 0 2006.168.08:07:59.00#ibcon#about to read 6, iclass 10, count 0 2006.168.08:07:59.00#ibcon#read 6, iclass 10, count 0 2006.168.08:07:59.00#ibcon#end of sib2, iclass 10, count 0 2006.168.08:07:59.00#ibcon#*after write, iclass 10, count 0 2006.168.08:07:59.00#ibcon#*before return 0, iclass 10, count 0 2006.168.08:07:59.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:07:59.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:07:59.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.168.08:07:59.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.168.08:07:59.00$vc4f8/va=4,7 2006.168.08:07:59.00#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.168.08:07:59.00#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.168.08:07:59.00#ibcon#ireg 11 cls_cnt 2 2006.168.08:07:59.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:07:59.06#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:07:59.06#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:07:59.06#ibcon#enter wrdev, iclass 12, count 2 2006.168.08:07:59.06#ibcon#first serial, iclass 12, count 2 2006.168.08:07:59.06#ibcon#enter sib2, iclass 12, count 2 2006.168.08:07:59.06#ibcon#flushed, iclass 12, count 2 2006.168.08:07:59.06#ibcon#about to write, iclass 12, count 2 2006.168.08:07:59.06#ibcon#wrote, iclass 12, count 2 2006.168.08:07:59.06#ibcon#about to read 3, iclass 12, count 2 2006.168.08:07:59.08#ibcon#read 3, iclass 12, count 2 2006.168.08:07:59.08#ibcon#about to read 4, iclass 12, count 2 2006.168.08:07:59.08#ibcon#read 4, iclass 12, count 2 2006.168.08:07:59.08#ibcon#about to read 5, iclass 12, count 2 2006.168.08:07:59.08#ibcon#read 5, iclass 12, count 2 2006.168.08:07:59.08#ibcon#about to read 6, iclass 12, count 2 2006.168.08:07:59.08#ibcon#read 6, iclass 12, count 2 2006.168.08:07:59.08#ibcon#end of sib2, iclass 12, count 2 2006.168.08:07:59.08#ibcon#*mode == 0, iclass 12, count 2 2006.168.08:07:59.08#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.168.08:07:59.08#ibcon#[25=AT04-07\r\n] 2006.168.08:07:59.08#ibcon#*before write, iclass 12, count 2 2006.168.08:07:59.08#ibcon#enter sib2, iclass 12, count 2 2006.168.08:07:59.08#ibcon#flushed, iclass 12, count 2 2006.168.08:07:59.08#ibcon#about to write, iclass 12, count 2 2006.168.08:07:59.08#ibcon#wrote, iclass 12, count 2 2006.168.08:07:59.08#ibcon#about to read 3, iclass 12, count 2 2006.168.08:07:59.11#ibcon#read 3, iclass 12, count 2 2006.168.08:07:59.11#ibcon#about to read 4, iclass 12, count 2 2006.168.08:07:59.11#ibcon#read 4, iclass 12, count 2 2006.168.08:07:59.11#ibcon#about to read 5, iclass 12, count 2 2006.168.08:07:59.11#ibcon#read 5, iclass 12, count 2 2006.168.08:07:59.11#ibcon#about to read 6, iclass 12, count 2 2006.168.08:07:59.11#ibcon#read 6, iclass 12, count 2 2006.168.08:07:59.11#ibcon#end of sib2, iclass 12, count 2 2006.168.08:07:59.11#ibcon#*after write, iclass 12, count 2 2006.168.08:07:59.11#ibcon#*before return 0, iclass 12, count 2 2006.168.08:07:59.11#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:07:59.11#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:07:59.11#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.168.08:07:59.11#ibcon#ireg 7 cls_cnt 0 2006.168.08:07:59.11#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:07:59.23#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:07:59.23#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:07:59.23#ibcon#enter wrdev, iclass 12, count 0 2006.168.08:07:59.23#ibcon#first serial, iclass 12, count 0 2006.168.08:07:59.23#ibcon#enter sib2, iclass 12, count 0 2006.168.08:07:59.23#ibcon#flushed, iclass 12, count 0 2006.168.08:07:59.23#ibcon#about to write, iclass 12, count 0 2006.168.08:07:59.23#ibcon#wrote, iclass 12, count 0 2006.168.08:07:59.23#ibcon#about to read 3, iclass 12, count 0 2006.168.08:07:59.27#ibcon#read 3, iclass 12, count 0 2006.168.08:07:59.27#ibcon#about to read 4, iclass 12, count 0 2006.168.08:07:59.27#ibcon#read 4, iclass 12, count 0 2006.168.08:07:59.27#ibcon#about to read 5, iclass 12, count 0 2006.168.08:07:59.27#ibcon#read 5, iclass 12, count 0 2006.168.08:07:59.27#ibcon#about to read 6, iclass 12, count 0 2006.168.08:07:59.27#ibcon#read 6, iclass 12, count 0 2006.168.08:07:59.27#ibcon#end of sib2, iclass 12, count 0 2006.168.08:07:59.27#ibcon#*mode == 0, iclass 12, count 0 2006.168.08:07:59.27#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.168.08:07:59.27#ibcon#[25=USB\r\n] 2006.168.08:07:59.27#ibcon#*before write, iclass 12, count 0 2006.168.08:07:59.27#ibcon#enter sib2, iclass 12, count 0 2006.168.08:07:59.27#ibcon#flushed, iclass 12, count 0 2006.168.08:07:59.27#ibcon#about to write, iclass 12, count 0 2006.168.08:07:59.27#ibcon#wrote, iclass 12, count 0 2006.168.08:07:59.27#ibcon#about to read 3, iclass 12, count 0 2006.168.08:07:59.30#ibcon#read 3, iclass 12, count 0 2006.168.08:07:59.30#ibcon#about to read 4, iclass 12, count 0 2006.168.08:07:59.30#ibcon#read 4, iclass 12, count 0 2006.168.08:07:59.30#ibcon#about to read 5, iclass 12, count 0 2006.168.08:07:59.30#ibcon#read 5, iclass 12, count 0 2006.168.08:07:59.30#ibcon#about to read 6, iclass 12, count 0 2006.168.08:07:59.30#ibcon#read 6, iclass 12, count 0 2006.168.08:07:59.30#ibcon#end of sib2, iclass 12, count 0 2006.168.08:07:59.30#ibcon#*after write, iclass 12, count 0 2006.168.08:07:59.30#ibcon#*before return 0, iclass 12, count 0 2006.168.08:07:59.30#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:07:59.30#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:07:59.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.168.08:07:59.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.168.08:07:59.30$vc4f8/valo=5,652.99 2006.168.08:07:59.30#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.168.08:07:59.30#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.168.08:07:59.30#ibcon#ireg 17 cls_cnt 0 2006.168.08:07:59.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:07:59.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:07:59.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:07:59.30#ibcon#enter wrdev, iclass 14, count 0 2006.168.08:07:59.30#ibcon#first serial, iclass 14, count 0 2006.168.08:07:59.30#ibcon#enter sib2, iclass 14, count 0 2006.168.08:07:59.30#ibcon#flushed, iclass 14, count 0 2006.168.08:07:59.30#ibcon#about to write, iclass 14, count 0 2006.168.08:07:59.30#ibcon#wrote, iclass 14, count 0 2006.168.08:07:59.30#ibcon#about to read 3, iclass 14, count 0 2006.168.08:07:59.32#ibcon#read 3, iclass 14, count 0 2006.168.08:07:59.32#ibcon#about to read 4, iclass 14, count 0 2006.168.08:07:59.32#ibcon#read 4, iclass 14, count 0 2006.168.08:07:59.32#ibcon#about to read 5, iclass 14, count 0 2006.168.08:07:59.32#ibcon#read 5, iclass 14, count 0 2006.168.08:07:59.32#ibcon#about to read 6, iclass 14, count 0 2006.168.08:07:59.32#ibcon#read 6, iclass 14, count 0 2006.168.08:07:59.32#ibcon#end of sib2, iclass 14, count 0 2006.168.08:07:59.32#ibcon#*mode == 0, iclass 14, count 0 2006.168.08:07:59.32#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.168.08:07:59.32#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.08:07:59.32#ibcon#*before write, iclass 14, count 0 2006.168.08:07:59.32#ibcon#enter sib2, iclass 14, count 0 2006.168.08:07:59.32#ibcon#flushed, iclass 14, count 0 2006.168.08:07:59.32#ibcon#about to write, iclass 14, count 0 2006.168.08:07:59.32#ibcon#wrote, iclass 14, count 0 2006.168.08:07:59.32#ibcon#about to read 3, iclass 14, count 0 2006.168.08:07:59.37#ibcon#read 3, iclass 14, count 0 2006.168.08:07:59.37#ibcon#about to read 4, iclass 14, count 0 2006.168.08:07:59.37#ibcon#read 4, iclass 14, count 0 2006.168.08:07:59.37#ibcon#about to read 5, iclass 14, count 0 2006.168.08:07:59.37#ibcon#read 5, iclass 14, count 0 2006.168.08:07:59.37#ibcon#about to read 6, iclass 14, count 0 2006.168.08:07:59.37#ibcon#read 6, iclass 14, count 0 2006.168.08:07:59.37#ibcon#end of sib2, iclass 14, count 0 2006.168.08:07:59.37#ibcon#*after write, iclass 14, count 0 2006.168.08:07:59.37#ibcon#*before return 0, iclass 14, count 0 2006.168.08:07:59.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:07:59.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:07:59.37#ibcon#about to clear, iclass 14 cls_cnt 0 2006.168.08:07:59.37#ibcon#cleared, iclass 14 cls_cnt 0 2006.168.08:07:59.37$vc4f8/va=5,7 2006.168.08:07:59.37#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.168.08:07:59.37#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.168.08:07:59.37#ibcon#ireg 11 cls_cnt 2 2006.168.08:07:59.37#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:07:59.41#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:07:59.41#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:07:59.41#ibcon#enter wrdev, iclass 16, count 2 2006.168.08:07:59.41#ibcon#first serial, iclass 16, count 2 2006.168.08:07:59.41#ibcon#enter sib2, iclass 16, count 2 2006.168.08:07:59.41#ibcon#flushed, iclass 16, count 2 2006.168.08:07:59.41#ibcon#about to write, iclass 16, count 2 2006.168.08:07:59.41#ibcon#wrote, iclass 16, count 2 2006.168.08:07:59.41#ibcon#about to read 3, iclass 16, count 2 2006.168.08:07:59.43#ibcon#read 3, iclass 16, count 2 2006.168.08:07:59.43#ibcon#about to read 4, iclass 16, count 2 2006.168.08:07:59.43#ibcon#read 4, iclass 16, count 2 2006.168.08:07:59.43#ibcon#about to read 5, iclass 16, count 2 2006.168.08:07:59.43#ibcon#read 5, iclass 16, count 2 2006.168.08:07:59.43#ibcon#about to read 6, iclass 16, count 2 2006.168.08:07:59.43#ibcon#read 6, iclass 16, count 2 2006.168.08:07:59.43#ibcon#end of sib2, iclass 16, count 2 2006.168.08:07:59.43#ibcon#*mode == 0, iclass 16, count 2 2006.168.08:07:59.43#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.168.08:07:59.43#ibcon#[25=AT05-07\r\n] 2006.168.08:07:59.43#ibcon#*before write, iclass 16, count 2 2006.168.08:07:59.43#ibcon#enter sib2, iclass 16, count 2 2006.168.08:07:59.43#ibcon#flushed, iclass 16, count 2 2006.168.08:07:59.43#ibcon#about to write, iclass 16, count 2 2006.168.08:07:59.43#ibcon#wrote, iclass 16, count 2 2006.168.08:07:59.43#ibcon#about to read 3, iclass 16, count 2 2006.168.08:07:59.46#ibcon#read 3, iclass 16, count 2 2006.168.08:07:59.46#ibcon#about to read 4, iclass 16, count 2 2006.168.08:07:59.46#ibcon#read 4, iclass 16, count 2 2006.168.08:07:59.46#ibcon#about to read 5, iclass 16, count 2 2006.168.08:07:59.46#ibcon#read 5, iclass 16, count 2 2006.168.08:07:59.46#ibcon#about to read 6, iclass 16, count 2 2006.168.08:07:59.46#ibcon#read 6, iclass 16, count 2 2006.168.08:07:59.46#ibcon#end of sib2, iclass 16, count 2 2006.168.08:07:59.46#ibcon#*after write, iclass 16, count 2 2006.168.08:07:59.46#ibcon#*before return 0, iclass 16, count 2 2006.168.08:07:59.46#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:07:59.46#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:07:59.46#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.168.08:07:59.46#ibcon#ireg 7 cls_cnt 0 2006.168.08:07:59.46#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:07:59.58#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:07:59.58#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:07:59.58#ibcon#enter wrdev, iclass 16, count 0 2006.168.08:07:59.58#ibcon#first serial, iclass 16, count 0 2006.168.08:07:59.58#ibcon#enter sib2, iclass 16, count 0 2006.168.08:07:59.58#ibcon#flushed, iclass 16, count 0 2006.168.08:07:59.58#ibcon#about to write, iclass 16, count 0 2006.168.08:07:59.58#ibcon#wrote, iclass 16, count 0 2006.168.08:07:59.58#ibcon#about to read 3, iclass 16, count 0 2006.168.08:07:59.60#ibcon#read 3, iclass 16, count 0 2006.168.08:07:59.60#ibcon#about to read 4, iclass 16, count 0 2006.168.08:07:59.60#ibcon#read 4, iclass 16, count 0 2006.168.08:07:59.60#ibcon#about to read 5, iclass 16, count 0 2006.168.08:07:59.60#ibcon#read 5, iclass 16, count 0 2006.168.08:07:59.60#ibcon#about to read 6, iclass 16, count 0 2006.168.08:07:59.60#ibcon#read 6, iclass 16, count 0 2006.168.08:07:59.60#ibcon#end of sib2, iclass 16, count 0 2006.168.08:07:59.60#ibcon#*mode == 0, iclass 16, count 0 2006.168.08:07:59.60#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.168.08:07:59.60#ibcon#[25=USB\r\n] 2006.168.08:07:59.60#ibcon#*before write, iclass 16, count 0 2006.168.08:07:59.60#ibcon#enter sib2, iclass 16, count 0 2006.168.08:07:59.60#ibcon#flushed, iclass 16, count 0 2006.168.08:07:59.60#ibcon#about to write, iclass 16, count 0 2006.168.08:07:59.60#ibcon#wrote, iclass 16, count 0 2006.168.08:07:59.60#ibcon#about to read 3, iclass 16, count 0 2006.168.08:07:59.63#ibcon#read 3, iclass 16, count 0 2006.168.08:07:59.63#ibcon#about to read 4, iclass 16, count 0 2006.168.08:07:59.63#ibcon#read 4, iclass 16, count 0 2006.168.08:07:59.63#ibcon#about to read 5, iclass 16, count 0 2006.168.08:07:59.63#ibcon#read 5, iclass 16, count 0 2006.168.08:07:59.63#ibcon#about to read 6, iclass 16, count 0 2006.168.08:07:59.63#ibcon#read 6, iclass 16, count 0 2006.168.08:07:59.63#ibcon#end of sib2, iclass 16, count 0 2006.168.08:07:59.63#ibcon#*after write, iclass 16, count 0 2006.168.08:07:59.63#ibcon#*before return 0, iclass 16, count 0 2006.168.08:07:59.63#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:07:59.63#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:07:59.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.168.08:07:59.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.168.08:07:59.63$vc4f8/valo=6,772.99 2006.168.08:07:59.63#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.168.08:07:59.63#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.168.08:07:59.63#ibcon#ireg 17 cls_cnt 0 2006.168.08:07:59.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:07:59.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:07:59.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:07:59.63#ibcon#enter wrdev, iclass 18, count 0 2006.168.08:07:59.63#ibcon#first serial, iclass 18, count 0 2006.168.08:07:59.63#ibcon#enter sib2, iclass 18, count 0 2006.168.08:07:59.63#ibcon#flushed, iclass 18, count 0 2006.168.08:07:59.63#ibcon#about to write, iclass 18, count 0 2006.168.08:07:59.63#ibcon#wrote, iclass 18, count 0 2006.168.08:07:59.63#ibcon#about to read 3, iclass 18, count 0 2006.168.08:07:59.65#ibcon#read 3, iclass 18, count 0 2006.168.08:07:59.65#ibcon#about to read 4, iclass 18, count 0 2006.168.08:07:59.65#ibcon#read 4, iclass 18, count 0 2006.168.08:07:59.65#ibcon#about to read 5, iclass 18, count 0 2006.168.08:07:59.65#ibcon#read 5, iclass 18, count 0 2006.168.08:07:59.65#ibcon#about to read 6, iclass 18, count 0 2006.168.08:07:59.65#ibcon#read 6, iclass 18, count 0 2006.168.08:07:59.65#ibcon#end of sib2, iclass 18, count 0 2006.168.08:07:59.65#ibcon#*mode == 0, iclass 18, count 0 2006.168.08:07:59.65#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.08:07:59.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.08:07:59.65#ibcon#*before write, iclass 18, count 0 2006.168.08:07:59.65#ibcon#enter sib2, iclass 18, count 0 2006.168.08:07:59.65#ibcon#flushed, iclass 18, count 0 2006.168.08:07:59.65#ibcon#about to write, iclass 18, count 0 2006.168.08:07:59.65#ibcon#wrote, iclass 18, count 0 2006.168.08:07:59.65#ibcon#about to read 3, iclass 18, count 0 2006.168.08:07:59.69#ibcon#read 3, iclass 18, count 0 2006.168.08:07:59.69#ibcon#about to read 4, iclass 18, count 0 2006.168.08:07:59.69#ibcon#read 4, iclass 18, count 0 2006.168.08:07:59.69#ibcon#about to read 5, iclass 18, count 0 2006.168.08:07:59.69#ibcon#read 5, iclass 18, count 0 2006.168.08:07:59.69#ibcon#about to read 6, iclass 18, count 0 2006.168.08:07:59.69#ibcon#read 6, iclass 18, count 0 2006.168.08:07:59.69#ibcon#end of sib2, iclass 18, count 0 2006.168.08:07:59.69#ibcon#*after write, iclass 18, count 0 2006.168.08:07:59.69#ibcon#*before return 0, iclass 18, count 0 2006.168.08:07:59.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:07:59.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:07:59.69#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.08:07:59.69#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.08:07:59.69$vc4f8/va=6,6 2006.168.08:07:59.69#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.168.08:07:59.69#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.168.08:07:59.69#ibcon#ireg 11 cls_cnt 2 2006.168.08:07:59.69#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:07:59.76#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:07:59.76#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:07:59.76#ibcon#enter wrdev, iclass 20, count 2 2006.168.08:07:59.76#ibcon#first serial, iclass 20, count 2 2006.168.08:07:59.76#ibcon#enter sib2, iclass 20, count 2 2006.168.08:07:59.76#ibcon#flushed, iclass 20, count 2 2006.168.08:07:59.76#ibcon#about to write, iclass 20, count 2 2006.168.08:07:59.76#ibcon#wrote, iclass 20, count 2 2006.168.08:07:59.76#ibcon#about to read 3, iclass 20, count 2 2006.168.08:07:59.78#ibcon#read 3, iclass 20, count 2 2006.168.08:07:59.78#ibcon#about to read 4, iclass 20, count 2 2006.168.08:07:59.78#ibcon#read 4, iclass 20, count 2 2006.168.08:07:59.78#ibcon#about to read 5, iclass 20, count 2 2006.168.08:07:59.78#ibcon#read 5, iclass 20, count 2 2006.168.08:07:59.78#ibcon#about to read 6, iclass 20, count 2 2006.168.08:07:59.78#ibcon#read 6, iclass 20, count 2 2006.168.08:07:59.78#ibcon#end of sib2, iclass 20, count 2 2006.168.08:07:59.78#ibcon#*mode == 0, iclass 20, count 2 2006.168.08:07:59.78#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.168.08:07:59.78#ibcon#[25=AT06-06\r\n] 2006.168.08:07:59.78#ibcon#*before write, iclass 20, count 2 2006.168.08:07:59.78#ibcon#enter sib2, iclass 20, count 2 2006.168.08:07:59.78#ibcon#flushed, iclass 20, count 2 2006.168.08:07:59.78#ibcon#about to write, iclass 20, count 2 2006.168.08:07:59.78#ibcon#wrote, iclass 20, count 2 2006.168.08:07:59.78#ibcon#about to read 3, iclass 20, count 2 2006.168.08:07:59.81#ibcon#read 3, iclass 20, count 2 2006.168.08:07:59.81#ibcon#about to read 4, iclass 20, count 2 2006.168.08:07:59.81#ibcon#read 4, iclass 20, count 2 2006.168.08:07:59.81#ibcon#about to read 5, iclass 20, count 2 2006.168.08:07:59.81#ibcon#read 5, iclass 20, count 2 2006.168.08:07:59.81#ibcon#about to read 6, iclass 20, count 2 2006.168.08:07:59.81#ibcon#read 6, iclass 20, count 2 2006.168.08:07:59.81#ibcon#end of sib2, iclass 20, count 2 2006.168.08:07:59.81#ibcon#*after write, iclass 20, count 2 2006.168.08:07:59.81#ibcon#*before return 0, iclass 20, count 2 2006.168.08:07:59.81#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:07:59.81#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:07:59.81#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.168.08:07:59.81#ibcon#ireg 7 cls_cnt 0 2006.168.08:07:59.81#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:07:59.93#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:07:59.93#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:07:59.93#ibcon#enter wrdev, iclass 20, count 0 2006.168.08:07:59.93#ibcon#first serial, iclass 20, count 0 2006.168.08:07:59.93#ibcon#enter sib2, iclass 20, count 0 2006.168.08:07:59.93#ibcon#flushed, iclass 20, count 0 2006.168.08:07:59.93#ibcon#about to write, iclass 20, count 0 2006.168.08:07:59.93#ibcon#wrote, iclass 20, count 0 2006.168.08:07:59.93#ibcon#about to read 3, iclass 20, count 0 2006.168.08:07:59.95#ibcon#read 3, iclass 20, count 0 2006.168.08:07:59.95#ibcon#about to read 4, iclass 20, count 0 2006.168.08:07:59.95#ibcon#read 4, iclass 20, count 0 2006.168.08:07:59.95#ibcon#about to read 5, iclass 20, count 0 2006.168.08:07:59.95#ibcon#read 5, iclass 20, count 0 2006.168.08:07:59.95#ibcon#about to read 6, iclass 20, count 0 2006.168.08:07:59.95#ibcon#read 6, iclass 20, count 0 2006.168.08:07:59.95#ibcon#end of sib2, iclass 20, count 0 2006.168.08:07:59.95#ibcon#*mode == 0, iclass 20, count 0 2006.168.08:07:59.95#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.168.08:07:59.95#ibcon#[25=USB\r\n] 2006.168.08:07:59.95#ibcon#*before write, iclass 20, count 0 2006.168.08:07:59.95#ibcon#enter sib2, iclass 20, count 0 2006.168.08:07:59.95#ibcon#flushed, iclass 20, count 0 2006.168.08:07:59.95#ibcon#about to write, iclass 20, count 0 2006.168.08:07:59.95#ibcon#wrote, iclass 20, count 0 2006.168.08:07:59.95#ibcon#about to read 3, iclass 20, count 0 2006.168.08:07:59.98#ibcon#read 3, iclass 20, count 0 2006.168.08:07:59.98#ibcon#about to read 4, iclass 20, count 0 2006.168.08:07:59.98#ibcon#read 4, iclass 20, count 0 2006.168.08:07:59.98#ibcon#about to read 5, iclass 20, count 0 2006.168.08:07:59.98#ibcon#read 5, iclass 20, count 0 2006.168.08:07:59.98#ibcon#about to read 6, iclass 20, count 0 2006.168.08:07:59.98#ibcon#read 6, iclass 20, count 0 2006.168.08:07:59.98#ibcon#end of sib2, iclass 20, count 0 2006.168.08:07:59.98#ibcon#*after write, iclass 20, count 0 2006.168.08:07:59.98#ibcon#*before return 0, iclass 20, count 0 2006.168.08:07:59.98#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:07:59.98#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:07:59.98#ibcon#about to clear, iclass 20 cls_cnt 0 2006.168.08:07:59.98#ibcon#cleared, iclass 20 cls_cnt 0 2006.168.08:07:59.98$vc4f8/valo=7,832.99 2006.168.08:07:59.98#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.168.08:07:59.98#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.168.08:07:59.98#ibcon#ireg 17 cls_cnt 0 2006.168.08:07:59.98#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:07:59.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:07:59.98#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:07:59.98#ibcon#enter wrdev, iclass 22, count 0 2006.168.08:07:59.98#ibcon#first serial, iclass 22, count 0 2006.168.08:07:59.98#ibcon#enter sib2, iclass 22, count 0 2006.168.08:07:59.98#ibcon#flushed, iclass 22, count 0 2006.168.08:07:59.98#ibcon#about to write, iclass 22, count 0 2006.168.08:07:59.98#ibcon#wrote, iclass 22, count 0 2006.168.08:07:59.98#ibcon#about to read 3, iclass 22, count 0 2006.168.08:08:00.00#ibcon#read 3, iclass 22, count 0 2006.168.08:08:00.00#ibcon#about to read 4, iclass 22, count 0 2006.168.08:08:00.00#ibcon#read 4, iclass 22, count 0 2006.168.08:08:00.00#ibcon#about to read 5, iclass 22, count 0 2006.168.08:08:00.00#ibcon#read 5, iclass 22, count 0 2006.168.08:08:00.00#ibcon#about to read 6, iclass 22, count 0 2006.168.08:08:00.00#ibcon#read 6, iclass 22, count 0 2006.168.08:08:00.00#ibcon#end of sib2, iclass 22, count 0 2006.168.08:08:00.00#ibcon#*mode == 0, iclass 22, count 0 2006.168.08:08:00.00#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.168.08:08:00.00#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.08:08:00.00#ibcon#*before write, iclass 22, count 0 2006.168.08:08:00.00#ibcon#enter sib2, iclass 22, count 0 2006.168.08:08:00.00#ibcon#flushed, iclass 22, count 0 2006.168.08:08:00.00#ibcon#about to write, iclass 22, count 0 2006.168.08:08:00.00#ibcon#wrote, iclass 22, count 0 2006.168.08:08:00.00#ibcon#about to read 3, iclass 22, count 0 2006.168.08:08:00.04#ibcon#read 3, iclass 22, count 0 2006.168.08:08:00.04#ibcon#about to read 4, iclass 22, count 0 2006.168.08:08:00.04#ibcon#read 4, iclass 22, count 0 2006.168.08:08:00.04#ibcon#about to read 5, iclass 22, count 0 2006.168.08:08:00.04#ibcon#read 5, iclass 22, count 0 2006.168.08:08:00.04#ibcon#about to read 6, iclass 22, count 0 2006.168.08:08:00.04#ibcon#read 6, iclass 22, count 0 2006.168.08:08:00.04#ibcon#end of sib2, iclass 22, count 0 2006.168.08:08:00.04#ibcon#*after write, iclass 22, count 0 2006.168.08:08:00.04#ibcon#*before return 0, iclass 22, count 0 2006.168.08:08:00.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:08:00.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:08:00.04#ibcon#about to clear, iclass 22 cls_cnt 0 2006.168.08:08:00.04#ibcon#cleared, iclass 22 cls_cnt 0 2006.168.08:08:00.04$vc4f8/va=7,6 2006.168.08:08:00.04#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.168.08:08:00.04#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.168.08:08:00.04#ibcon#ireg 11 cls_cnt 2 2006.168.08:08:00.04#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:08:00.10#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:08:00.10#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:08:00.10#ibcon#enter wrdev, iclass 24, count 2 2006.168.08:08:00.10#ibcon#first serial, iclass 24, count 2 2006.168.08:08:00.10#ibcon#enter sib2, iclass 24, count 2 2006.168.08:08:00.10#ibcon#flushed, iclass 24, count 2 2006.168.08:08:00.10#ibcon#about to write, iclass 24, count 2 2006.168.08:08:00.10#ibcon#wrote, iclass 24, count 2 2006.168.08:08:00.10#ibcon#about to read 3, iclass 24, count 2 2006.168.08:08:00.13#ibcon#read 3, iclass 24, count 2 2006.168.08:08:00.13#ibcon#about to read 4, iclass 24, count 2 2006.168.08:08:00.13#ibcon#read 4, iclass 24, count 2 2006.168.08:08:00.13#ibcon#about to read 5, iclass 24, count 2 2006.168.08:08:00.13#ibcon#read 5, iclass 24, count 2 2006.168.08:08:00.13#ibcon#about to read 6, iclass 24, count 2 2006.168.08:08:00.13#ibcon#read 6, iclass 24, count 2 2006.168.08:08:00.13#ibcon#end of sib2, iclass 24, count 2 2006.168.08:08:00.13#ibcon#*mode == 0, iclass 24, count 2 2006.168.08:08:00.13#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.168.08:08:00.13#ibcon#[25=AT07-06\r\n] 2006.168.08:08:00.13#ibcon#*before write, iclass 24, count 2 2006.168.08:08:00.13#ibcon#enter sib2, iclass 24, count 2 2006.168.08:08:00.13#ibcon#flushed, iclass 24, count 2 2006.168.08:08:00.13#ibcon#about to write, iclass 24, count 2 2006.168.08:08:00.13#ibcon#wrote, iclass 24, count 2 2006.168.08:08:00.13#ibcon#about to read 3, iclass 24, count 2 2006.168.08:08:00.16#ibcon#read 3, iclass 24, count 2 2006.168.08:08:00.16#ibcon#about to read 4, iclass 24, count 2 2006.168.08:08:00.16#ibcon#read 4, iclass 24, count 2 2006.168.08:08:00.16#ibcon#about to read 5, iclass 24, count 2 2006.168.08:08:00.16#ibcon#read 5, iclass 24, count 2 2006.168.08:08:00.16#ibcon#about to read 6, iclass 24, count 2 2006.168.08:08:00.16#ibcon#read 6, iclass 24, count 2 2006.168.08:08:00.16#ibcon#end of sib2, iclass 24, count 2 2006.168.08:08:00.16#ibcon#*after write, iclass 24, count 2 2006.168.08:08:00.16#ibcon#*before return 0, iclass 24, count 2 2006.168.08:08:00.16#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:08:00.16#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:08:00.16#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.168.08:08:00.16#ibcon#ireg 7 cls_cnt 0 2006.168.08:08:00.16#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:08:00.28#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:08:00.28#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:08:00.28#ibcon#enter wrdev, iclass 24, count 0 2006.168.08:08:00.28#ibcon#first serial, iclass 24, count 0 2006.168.08:08:00.28#ibcon#enter sib2, iclass 24, count 0 2006.168.08:08:00.28#ibcon#flushed, iclass 24, count 0 2006.168.08:08:00.28#ibcon#about to write, iclass 24, count 0 2006.168.08:08:00.28#ibcon#wrote, iclass 24, count 0 2006.168.08:08:00.28#ibcon#about to read 3, iclass 24, count 0 2006.168.08:08:00.30#ibcon#read 3, iclass 24, count 0 2006.168.08:08:00.30#ibcon#about to read 4, iclass 24, count 0 2006.168.08:08:00.30#ibcon#read 4, iclass 24, count 0 2006.168.08:08:00.30#ibcon#about to read 5, iclass 24, count 0 2006.168.08:08:00.30#ibcon#read 5, iclass 24, count 0 2006.168.08:08:00.30#ibcon#about to read 6, iclass 24, count 0 2006.168.08:08:00.30#ibcon#read 6, iclass 24, count 0 2006.168.08:08:00.30#ibcon#end of sib2, iclass 24, count 0 2006.168.08:08:00.30#ibcon#*mode == 0, iclass 24, count 0 2006.168.08:08:00.30#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.168.08:08:00.30#ibcon#[25=USB\r\n] 2006.168.08:08:00.30#ibcon#*before write, iclass 24, count 0 2006.168.08:08:00.30#ibcon#enter sib2, iclass 24, count 0 2006.168.08:08:00.30#ibcon#flushed, iclass 24, count 0 2006.168.08:08:00.30#ibcon#about to write, iclass 24, count 0 2006.168.08:08:00.30#ibcon#wrote, iclass 24, count 0 2006.168.08:08:00.30#ibcon#about to read 3, iclass 24, count 0 2006.168.08:08:00.33#ibcon#read 3, iclass 24, count 0 2006.168.08:08:00.33#ibcon#about to read 4, iclass 24, count 0 2006.168.08:08:00.33#ibcon#read 4, iclass 24, count 0 2006.168.08:08:00.33#ibcon#about to read 5, iclass 24, count 0 2006.168.08:08:00.33#ibcon#read 5, iclass 24, count 0 2006.168.08:08:00.33#ibcon#about to read 6, iclass 24, count 0 2006.168.08:08:00.33#ibcon#read 6, iclass 24, count 0 2006.168.08:08:00.33#ibcon#end of sib2, iclass 24, count 0 2006.168.08:08:00.33#ibcon#*after write, iclass 24, count 0 2006.168.08:08:00.33#ibcon#*before return 0, iclass 24, count 0 2006.168.08:08:00.33#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:08:00.33#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:08:00.33#ibcon#about to clear, iclass 24 cls_cnt 0 2006.168.08:08:00.33#ibcon#cleared, iclass 24 cls_cnt 0 2006.168.08:08:00.33$vc4f8/valo=8,852.99 2006.168.08:08:00.33#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.168.08:08:00.33#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.168.08:08:00.33#ibcon#ireg 17 cls_cnt 0 2006.168.08:08:00.33#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:08:00.33#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:08:00.33#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:08:00.33#ibcon#enter wrdev, iclass 26, count 0 2006.168.08:08:00.33#ibcon#first serial, iclass 26, count 0 2006.168.08:08:00.33#ibcon#enter sib2, iclass 26, count 0 2006.168.08:08:00.33#ibcon#flushed, iclass 26, count 0 2006.168.08:08:00.33#ibcon#about to write, iclass 26, count 0 2006.168.08:08:00.33#ibcon#wrote, iclass 26, count 0 2006.168.08:08:00.33#ibcon#about to read 3, iclass 26, count 0 2006.168.08:08:00.35#ibcon#read 3, iclass 26, count 0 2006.168.08:08:00.35#ibcon#about to read 4, iclass 26, count 0 2006.168.08:08:00.35#ibcon#read 4, iclass 26, count 0 2006.168.08:08:00.35#ibcon#about to read 5, iclass 26, count 0 2006.168.08:08:00.35#ibcon#read 5, iclass 26, count 0 2006.168.08:08:00.35#ibcon#about to read 6, iclass 26, count 0 2006.168.08:08:00.35#ibcon#read 6, iclass 26, count 0 2006.168.08:08:00.35#ibcon#end of sib2, iclass 26, count 0 2006.168.08:08:00.35#ibcon#*mode == 0, iclass 26, count 0 2006.168.08:08:00.35#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.168.08:08:00.35#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.08:08:00.35#ibcon#*before write, iclass 26, count 0 2006.168.08:08:00.35#ibcon#enter sib2, iclass 26, count 0 2006.168.08:08:00.35#ibcon#flushed, iclass 26, count 0 2006.168.08:08:00.35#ibcon#about to write, iclass 26, count 0 2006.168.08:08:00.35#ibcon#wrote, iclass 26, count 0 2006.168.08:08:00.35#ibcon#about to read 3, iclass 26, count 0 2006.168.08:08:00.39#ibcon#read 3, iclass 26, count 0 2006.168.08:08:00.39#ibcon#about to read 4, iclass 26, count 0 2006.168.08:08:00.39#ibcon#read 4, iclass 26, count 0 2006.168.08:08:00.39#ibcon#about to read 5, iclass 26, count 0 2006.168.08:08:00.39#ibcon#read 5, iclass 26, count 0 2006.168.08:08:00.39#ibcon#about to read 6, iclass 26, count 0 2006.168.08:08:00.39#ibcon#read 6, iclass 26, count 0 2006.168.08:08:00.39#ibcon#end of sib2, iclass 26, count 0 2006.168.08:08:00.39#ibcon#*after write, iclass 26, count 0 2006.168.08:08:00.39#ibcon#*before return 0, iclass 26, count 0 2006.168.08:08:00.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:08:00.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:08:00.39#ibcon#about to clear, iclass 26 cls_cnt 0 2006.168.08:08:00.39#ibcon#cleared, iclass 26 cls_cnt 0 2006.168.08:08:00.39$vc4f8/va=8,7 2006.168.08:08:00.39#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.168.08:08:00.39#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.168.08:08:00.39#ibcon#ireg 11 cls_cnt 2 2006.168.08:08:00.39#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:08:00.45#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:08:00.45#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:08:00.45#ibcon#enter wrdev, iclass 28, count 2 2006.168.08:08:00.45#ibcon#first serial, iclass 28, count 2 2006.168.08:08:00.45#ibcon#enter sib2, iclass 28, count 2 2006.168.08:08:00.45#ibcon#flushed, iclass 28, count 2 2006.168.08:08:00.45#ibcon#about to write, iclass 28, count 2 2006.168.08:08:00.45#ibcon#wrote, iclass 28, count 2 2006.168.08:08:00.45#ibcon#about to read 3, iclass 28, count 2 2006.168.08:08:00.47#ibcon#read 3, iclass 28, count 2 2006.168.08:08:00.47#ibcon#about to read 4, iclass 28, count 2 2006.168.08:08:00.47#ibcon#read 4, iclass 28, count 2 2006.168.08:08:00.47#ibcon#about to read 5, iclass 28, count 2 2006.168.08:08:00.47#ibcon#read 5, iclass 28, count 2 2006.168.08:08:00.47#ibcon#about to read 6, iclass 28, count 2 2006.168.08:08:00.47#ibcon#read 6, iclass 28, count 2 2006.168.08:08:00.47#ibcon#end of sib2, iclass 28, count 2 2006.168.08:08:00.47#ibcon#*mode == 0, iclass 28, count 2 2006.168.08:08:00.47#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.168.08:08:00.47#ibcon#[25=AT08-07\r\n] 2006.168.08:08:00.47#ibcon#*before write, iclass 28, count 2 2006.168.08:08:00.47#ibcon#enter sib2, iclass 28, count 2 2006.168.08:08:00.47#ibcon#flushed, iclass 28, count 2 2006.168.08:08:00.47#ibcon#about to write, iclass 28, count 2 2006.168.08:08:00.47#ibcon#wrote, iclass 28, count 2 2006.168.08:08:00.47#ibcon#about to read 3, iclass 28, count 2 2006.168.08:08:00.50#ibcon#read 3, iclass 28, count 2 2006.168.08:08:00.50#ibcon#about to read 4, iclass 28, count 2 2006.168.08:08:00.50#ibcon#read 4, iclass 28, count 2 2006.168.08:08:00.50#ibcon#about to read 5, iclass 28, count 2 2006.168.08:08:00.50#ibcon#read 5, iclass 28, count 2 2006.168.08:08:00.50#ibcon#about to read 6, iclass 28, count 2 2006.168.08:08:00.50#ibcon#read 6, iclass 28, count 2 2006.168.08:08:00.50#ibcon#end of sib2, iclass 28, count 2 2006.168.08:08:00.50#ibcon#*after write, iclass 28, count 2 2006.168.08:08:00.50#ibcon#*before return 0, iclass 28, count 2 2006.168.08:08:00.50#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:08:00.50#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:08:00.50#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.168.08:08:00.50#ibcon#ireg 7 cls_cnt 0 2006.168.08:08:00.50#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:08:00.62#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:08:00.62#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:08:00.62#ibcon#enter wrdev, iclass 28, count 0 2006.168.08:08:00.62#ibcon#first serial, iclass 28, count 0 2006.168.08:08:00.62#ibcon#enter sib2, iclass 28, count 0 2006.168.08:08:00.62#ibcon#flushed, iclass 28, count 0 2006.168.08:08:00.62#ibcon#about to write, iclass 28, count 0 2006.168.08:08:00.62#ibcon#wrote, iclass 28, count 0 2006.168.08:08:00.62#ibcon#about to read 3, iclass 28, count 0 2006.168.08:08:00.64#ibcon#read 3, iclass 28, count 0 2006.168.08:08:00.64#ibcon#about to read 4, iclass 28, count 0 2006.168.08:08:00.64#ibcon#read 4, iclass 28, count 0 2006.168.08:08:00.64#ibcon#about to read 5, iclass 28, count 0 2006.168.08:08:00.64#ibcon#read 5, iclass 28, count 0 2006.168.08:08:00.64#ibcon#about to read 6, iclass 28, count 0 2006.168.08:08:00.64#ibcon#read 6, iclass 28, count 0 2006.168.08:08:00.64#ibcon#end of sib2, iclass 28, count 0 2006.168.08:08:00.64#ibcon#*mode == 0, iclass 28, count 0 2006.168.08:08:00.64#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.168.08:08:00.64#ibcon#[25=USB\r\n] 2006.168.08:08:00.64#ibcon#*before write, iclass 28, count 0 2006.168.08:08:00.64#ibcon#enter sib2, iclass 28, count 0 2006.168.08:08:00.64#ibcon#flushed, iclass 28, count 0 2006.168.08:08:00.64#ibcon#about to write, iclass 28, count 0 2006.168.08:08:00.64#ibcon#wrote, iclass 28, count 0 2006.168.08:08:00.64#ibcon#about to read 3, iclass 28, count 0 2006.168.08:08:00.67#ibcon#read 3, iclass 28, count 0 2006.168.08:08:00.67#ibcon#about to read 4, iclass 28, count 0 2006.168.08:08:00.67#ibcon#read 4, iclass 28, count 0 2006.168.08:08:00.67#ibcon#about to read 5, iclass 28, count 0 2006.168.08:08:00.67#ibcon#read 5, iclass 28, count 0 2006.168.08:08:00.67#ibcon#about to read 6, iclass 28, count 0 2006.168.08:08:00.67#ibcon#read 6, iclass 28, count 0 2006.168.08:08:00.67#ibcon#end of sib2, iclass 28, count 0 2006.168.08:08:00.67#ibcon#*after write, iclass 28, count 0 2006.168.08:08:00.67#ibcon#*before return 0, iclass 28, count 0 2006.168.08:08:00.67#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:08:00.67#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:08:00.67#ibcon#about to clear, iclass 28 cls_cnt 0 2006.168.08:08:00.67#ibcon#cleared, iclass 28 cls_cnt 0 2006.168.08:08:00.67$vc4f8/vblo=1,632.99 2006.168.08:08:00.67#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.168.08:08:00.67#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.168.08:08:00.67#ibcon#ireg 17 cls_cnt 0 2006.168.08:08:00.67#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:08:00.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:08:00.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:08:00.67#ibcon#enter wrdev, iclass 30, count 0 2006.168.08:08:00.67#ibcon#first serial, iclass 30, count 0 2006.168.08:08:00.67#ibcon#enter sib2, iclass 30, count 0 2006.168.08:08:00.67#ibcon#flushed, iclass 30, count 0 2006.168.08:08:00.67#ibcon#about to write, iclass 30, count 0 2006.168.08:08:00.67#ibcon#wrote, iclass 30, count 0 2006.168.08:08:00.67#ibcon#about to read 3, iclass 30, count 0 2006.168.08:08:00.69#ibcon#read 3, iclass 30, count 0 2006.168.08:08:00.69#ibcon#about to read 4, iclass 30, count 0 2006.168.08:08:00.69#ibcon#read 4, iclass 30, count 0 2006.168.08:08:00.69#ibcon#about to read 5, iclass 30, count 0 2006.168.08:08:00.69#ibcon#read 5, iclass 30, count 0 2006.168.08:08:00.69#ibcon#about to read 6, iclass 30, count 0 2006.168.08:08:00.69#ibcon#read 6, iclass 30, count 0 2006.168.08:08:00.69#ibcon#end of sib2, iclass 30, count 0 2006.168.08:08:00.69#ibcon#*mode == 0, iclass 30, count 0 2006.168.08:08:00.69#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.168.08:08:00.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.08:08:00.69#ibcon#*before write, iclass 30, count 0 2006.168.08:08:00.69#ibcon#enter sib2, iclass 30, count 0 2006.168.08:08:00.69#ibcon#flushed, iclass 30, count 0 2006.168.08:08:00.69#ibcon#about to write, iclass 30, count 0 2006.168.08:08:00.69#ibcon#wrote, iclass 30, count 0 2006.168.08:08:00.69#ibcon#about to read 3, iclass 30, count 0 2006.168.08:08:00.73#ibcon#read 3, iclass 30, count 0 2006.168.08:08:00.73#ibcon#about to read 4, iclass 30, count 0 2006.168.08:08:00.73#ibcon#read 4, iclass 30, count 0 2006.168.08:08:00.73#ibcon#about to read 5, iclass 30, count 0 2006.168.08:08:00.73#ibcon#read 5, iclass 30, count 0 2006.168.08:08:00.73#ibcon#about to read 6, iclass 30, count 0 2006.168.08:08:00.73#ibcon#read 6, iclass 30, count 0 2006.168.08:08:00.73#ibcon#end of sib2, iclass 30, count 0 2006.168.08:08:00.73#ibcon#*after write, iclass 30, count 0 2006.168.08:08:00.73#ibcon#*before return 0, iclass 30, count 0 2006.168.08:08:00.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:08:00.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:08:00.73#ibcon#about to clear, iclass 30 cls_cnt 0 2006.168.08:08:00.73#ibcon#cleared, iclass 30 cls_cnt 0 2006.168.08:08:00.73$vc4f8/vb=1,4 2006.168.08:08:00.73#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.168.08:08:00.73#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.168.08:08:00.73#ibcon#ireg 11 cls_cnt 2 2006.168.08:08:00.73#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:08:00.73#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:08:00.73#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:08:00.73#ibcon#enter wrdev, iclass 32, count 2 2006.168.08:08:00.73#ibcon#first serial, iclass 32, count 2 2006.168.08:08:00.73#ibcon#enter sib2, iclass 32, count 2 2006.168.08:08:00.73#ibcon#flushed, iclass 32, count 2 2006.168.08:08:00.73#ibcon#about to write, iclass 32, count 2 2006.168.08:08:00.73#ibcon#wrote, iclass 32, count 2 2006.168.08:08:00.73#ibcon#about to read 3, iclass 32, count 2 2006.168.08:08:00.75#ibcon#read 3, iclass 32, count 2 2006.168.08:08:00.75#ibcon#about to read 4, iclass 32, count 2 2006.168.08:08:00.75#ibcon#read 4, iclass 32, count 2 2006.168.08:08:00.75#ibcon#about to read 5, iclass 32, count 2 2006.168.08:08:00.75#ibcon#read 5, iclass 32, count 2 2006.168.08:08:00.75#ibcon#about to read 6, iclass 32, count 2 2006.168.08:08:00.75#ibcon#read 6, iclass 32, count 2 2006.168.08:08:00.75#ibcon#end of sib2, iclass 32, count 2 2006.168.08:08:00.75#ibcon#*mode == 0, iclass 32, count 2 2006.168.08:08:00.75#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.168.08:08:00.75#ibcon#[27=AT01-04\r\n] 2006.168.08:08:00.75#ibcon#*before write, iclass 32, count 2 2006.168.08:08:00.75#ibcon#enter sib2, iclass 32, count 2 2006.168.08:08:00.75#ibcon#flushed, iclass 32, count 2 2006.168.08:08:00.75#ibcon#about to write, iclass 32, count 2 2006.168.08:08:00.75#ibcon#wrote, iclass 32, count 2 2006.168.08:08:00.75#ibcon#about to read 3, iclass 32, count 2 2006.168.08:08:00.78#ibcon#read 3, iclass 32, count 2 2006.168.08:08:00.78#ibcon#about to read 4, iclass 32, count 2 2006.168.08:08:00.78#ibcon#read 4, iclass 32, count 2 2006.168.08:08:00.78#ibcon#about to read 5, iclass 32, count 2 2006.168.08:08:00.78#ibcon#read 5, iclass 32, count 2 2006.168.08:08:00.78#ibcon#about to read 6, iclass 32, count 2 2006.168.08:08:00.78#ibcon#read 6, iclass 32, count 2 2006.168.08:08:00.78#ibcon#end of sib2, iclass 32, count 2 2006.168.08:08:00.78#ibcon#*after write, iclass 32, count 2 2006.168.08:08:00.78#ibcon#*before return 0, iclass 32, count 2 2006.168.08:08:00.78#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:08:00.78#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:08:00.78#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.168.08:08:00.78#ibcon#ireg 7 cls_cnt 0 2006.168.08:08:00.78#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:08:00.90#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:08:00.90#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:08:00.90#ibcon#enter wrdev, iclass 32, count 0 2006.168.08:08:00.90#ibcon#first serial, iclass 32, count 0 2006.168.08:08:00.90#ibcon#enter sib2, iclass 32, count 0 2006.168.08:08:00.90#ibcon#flushed, iclass 32, count 0 2006.168.08:08:00.90#ibcon#about to write, iclass 32, count 0 2006.168.08:08:00.90#ibcon#wrote, iclass 32, count 0 2006.168.08:08:00.90#ibcon#about to read 3, iclass 32, count 0 2006.168.08:08:00.92#ibcon#read 3, iclass 32, count 0 2006.168.08:08:00.92#ibcon#about to read 4, iclass 32, count 0 2006.168.08:08:00.92#ibcon#read 4, iclass 32, count 0 2006.168.08:08:00.92#ibcon#about to read 5, iclass 32, count 0 2006.168.08:08:00.92#ibcon#read 5, iclass 32, count 0 2006.168.08:08:00.92#ibcon#about to read 6, iclass 32, count 0 2006.168.08:08:00.92#ibcon#read 6, iclass 32, count 0 2006.168.08:08:00.92#ibcon#end of sib2, iclass 32, count 0 2006.168.08:08:00.92#ibcon#*mode == 0, iclass 32, count 0 2006.168.08:08:00.92#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.168.08:08:00.92#ibcon#[27=USB\r\n] 2006.168.08:08:00.92#ibcon#*before write, iclass 32, count 0 2006.168.08:08:00.92#ibcon#enter sib2, iclass 32, count 0 2006.168.08:08:00.92#ibcon#flushed, iclass 32, count 0 2006.168.08:08:00.92#ibcon#about to write, iclass 32, count 0 2006.168.08:08:00.92#ibcon#wrote, iclass 32, count 0 2006.168.08:08:00.92#ibcon#about to read 3, iclass 32, count 0 2006.168.08:08:00.95#ibcon#read 3, iclass 32, count 0 2006.168.08:08:00.95#ibcon#about to read 4, iclass 32, count 0 2006.168.08:08:00.95#ibcon#read 4, iclass 32, count 0 2006.168.08:08:00.95#ibcon#about to read 5, iclass 32, count 0 2006.168.08:08:00.95#ibcon#read 5, iclass 32, count 0 2006.168.08:08:00.95#ibcon#about to read 6, iclass 32, count 0 2006.168.08:08:00.95#ibcon#read 6, iclass 32, count 0 2006.168.08:08:00.95#ibcon#end of sib2, iclass 32, count 0 2006.168.08:08:00.95#ibcon#*after write, iclass 32, count 0 2006.168.08:08:00.95#ibcon#*before return 0, iclass 32, count 0 2006.168.08:08:00.95#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:08:00.95#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:08:00.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.168.08:08:00.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.168.08:08:00.95$vc4f8/vblo=2,640.99 2006.168.08:08:00.95#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.168.08:08:00.95#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.168.08:08:00.95#ibcon#ireg 17 cls_cnt 0 2006.168.08:08:00.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:08:00.95#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:08:00.95#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:08:00.95#ibcon#enter wrdev, iclass 34, count 0 2006.168.08:08:00.95#ibcon#first serial, iclass 34, count 0 2006.168.08:08:00.95#ibcon#enter sib2, iclass 34, count 0 2006.168.08:08:00.95#ibcon#flushed, iclass 34, count 0 2006.168.08:08:00.95#ibcon#about to write, iclass 34, count 0 2006.168.08:08:00.95#ibcon#wrote, iclass 34, count 0 2006.168.08:08:00.95#ibcon#about to read 3, iclass 34, count 0 2006.168.08:08:00.97#ibcon#read 3, iclass 34, count 0 2006.168.08:08:00.97#ibcon#about to read 4, iclass 34, count 0 2006.168.08:08:00.97#ibcon#read 4, iclass 34, count 0 2006.168.08:08:00.97#ibcon#about to read 5, iclass 34, count 0 2006.168.08:08:00.97#ibcon#read 5, iclass 34, count 0 2006.168.08:08:00.97#ibcon#about to read 6, iclass 34, count 0 2006.168.08:08:00.97#ibcon#read 6, iclass 34, count 0 2006.168.08:08:00.97#ibcon#end of sib2, iclass 34, count 0 2006.168.08:08:00.97#ibcon#*mode == 0, iclass 34, count 0 2006.168.08:08:00.97#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.168.08:08:00.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.08:08:00.97#ibcon#*before write, iclass 34, count 0 2006.168.08:08:00.97#ibcon#enter sib2, iclass 34, count 0 2006.168.08:08:00.97#ibcon#flushed, iclass 34, count 0 2006.168.08:08:00.97#ibcon#about to write, iclass 34, count 0 2006.168.08:08:00.97#ibcon#wrote, iclass 34, count 0 2006.168.08:08:00.97#ibcon#about to read 3, iclass 34, count 0 2006.168.08:08:01.01#ibcon#read 3, iclass 34, count 0 2006.168.08:08:01.01#ibcon#about to read 4, iclass 34, count 0 2006.168.08:08:01.01#ibcon#read 4, iclass 34, count 0 2006.168.08:08:01.01#ibcon#about to read 5, iclass 34, count 0 2006.168.08:08:01.01#ibcon#read 5, iclass 34, count 0 2006.168.08:08:01.01#ibcon#about to read 6, iclass 34, count 0 2006.168.08:08:01.01#ibcon#read 6, iclass 34, count 0 2006.168.08:08:01.01#ibcon#end of sib2, iclass 34, count 0 2006.168.08:08:01.01#ibcon#*after write, iclass 34, count 0 2006.168.08:08:01.01#ibcon#*before return 0, iclass 34, count 0 2006.168.08:08:01.01#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:08:01.01#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:08:01.01#ibcon#about to clear, iclass 34 cls_cnt 0 2006.168.08:08:01.01#ibcon#cleared, iclass 34 cls_cnt 0 2006.168.08:08:01.01$vc4f8/vb=2,4 2006.168.08:08:01.01#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.168.08:08:01.01#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.168.08:08:01.01#ibcon#ireg 11 cls_cnt 2 2006.168.08:08:01.01#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:08:01.07#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:08:01.07#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:08:01.07#ibcon#enter wrdev, iclass 36, count 2 2006.168.08:08:01.07#ibcon#first serial, iclass 36, count 2 2006.168.08:08:01.07#ibcon#enter sib2, iclass 36, count 2 2006.168.08:08:01.07#ibcon#flushed, iclass 36, count 2 2006.168.08:08:01.07#ibcon#about to write, iclass 36, count 2 2006.168.08:08:01.07#ibcon#wrote, iclass 36, count 2 2006.168.08:08:01.07#ibcon#about to read 3, iclass 36, count 2 2006.168.08:08:01.09#ibcon#read 3, iclass 36, count 2 2006.168.08:08:01.09#ibcon#about to read 4, iclass 36, count 2 2006.168.08:08:01.09#ibcon#read 4, iclass 36, count 2 2006.168.08:08:01.09#ibcon#about to read 5, iclass 36, count 2 2006.168.08:08:01.09#ibcon#read 5, iclass 36, count 2 2006.168.08:08:01.09#ibcon#about to read 6, iclass 36, count 2 2006.168.08:08:01.09#ibcon#read 6, iclass 36, count 2 2006.168.08:08:01.09#ibcon#end of sib2, iclass 36, count 2 2006.168.08:08:01.09#ibcon#*mode == 0, iclass 36, count 2 2006.168.08:08:01.09#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.168.08:08:01.09#ibcon#[27=AT02-04\r\n] 2006.168.08:08:01.09#ibcon#*before write, iclass 36, count 2 2006.168.08:08:01.09#ibcon#enter sib2, iclass 36, count 2 2006.168.08:08:01.09#ibcon#flushed, iclass 36, count 2 2006.168.08:08:01.09#ibcon#about to write, iclass 36, count 2 2006.168.08:08:01.09#ibcon#wrote, iclass 36, count 2 2006.168.08:08:01.09#ibcon#about to read 3, iclass 36, count 2 2006.168.08:08:01.12#ibcon#read 3, iclass 36, count 2 2006.168.08:08:01.12#ibcon#about to read 4, iclass 36, count 2 2006.168.08:08:01.12#ibcon#read 4, iclass 36, count 2 2006.168.08:08:01.12#ibcon#about to read 5, iclass 36, count 2 2006.168.08:08:01.12#ibcon#read 5, iclass 36, count 2 2006.168.08:08:01.12#ibcon#about to read 6, iclass 36, count 2 2006.168.08:08:01.12#ibcon#read 6, iclass 36, count 2 2006.168.08:08:01.12#ibcon#end of sib2, iclass 36, count 2 2006.168.08:08:01.12#ibcon#*after write, iclass 36, count 2 2006.168.08:08:01.12#ibcon#*before return 0, iclass 36, count 2 2006.168.08:08:01.12#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:08:01.12#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:08:01.12#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.168.08:08:01.12#ibcon#ireg 7 cls_cnt 0 2006.168.08:08:01.12#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:08:01.24#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:08:01.24#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:08:01.24#ibcon#enter wrdev, iclass 36, count 0 2006.168.08:08:01.24#ibcon#first serial, iclass 36, count 0 2006.168.08:08:01.24#ibcon#enter sib2, iclass 36, count 0 2006.168.08:08:01.24#ibcon#flushed, iclass 36, count 0 2006.168.08:08:01.24#ibcon#about to write, iclass 36, count 0 2006.168.08:08:01.24#ibcon#wrote, iclass 36, count 0 2006.168.08:08:01.24#ibcon#about to read 3, iclass 36, count 0 2006.168.08:08:01.26#ibcon#read 3, iclass 36, count 0 2006.168.08:08:01.26#ibcon#about to read 4, iclass 36, count 0 2006.168.08:08:01.26#ibcon#read 4, iclass 36, count 0 2006.168.08:08:01.26#ibcon#about to read 5, iclass 36, count 0 2006.168.08:08:01.26#ibcon#read 5, iclass 36, count 0 2006.168.08:08:01.26#ibcon#about to read 6, iclass 36, count 0 2006.168.08:08:01.26#ibcon#read 6, iclass 36, count 0 2006.168.08:08:01.26#ibcon#end of sib2, iclass 36, count 0 2006.168.08:08:01.26#ibcon#*mode == 0, iclass 36, count 0 2006.168.08:08:01.26#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.168.08:08:01.26#ibcon#[27=USB\r\n] 2006.168.08:08:01.26#ibcon#*before write, iclass 36, count 0 2006.168.08:08:01.26#ibcon#enter sib2, iclass 36, count 0 2006.168.08:08:01.26#ibcon#flushed, iclass 36, count 0 2006.168.08:08:01.26#ibcon#about to write, iclass 36, count 0 2006.168.08:08:01.26#ibcon#wrote, iclass 36, count 0 2006.168.08:08:01.26#ibcon#about to read 3, iclass 36, count 0 2006.168.08:08:01.29#ibcon#read 3, iclass 36, count 0 2006.168.08:08:01.29#ibcon#about to read 4, iclass 36, count 0 2006.168.08:08:01.29#ibcon#read 4, iclass 36, count 0 2006.168.08:08:01.29#ibcon#about to read 5, iclass 36, count 0 2006.168.08:08:01.29#ibcon#read 5, iclass 36, count 0 2006.168.08:08:01.29#ibcon#about to read 6, iclass 36, count 0 2006.168.08:08:01.29#ibcon#read 6, iclass 36, count 0 2006.168.08:08:01.29#ibcon#end of sib2, iclass 36, count 0 2006.168.08:08:01.29#ibcon#*after write, iclass 36, count 0 2006.168.08:08:01.29#ibcon#*before return 0, iclass 36, count 0 2006.168.08:08:01.29#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:08:01.29#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:08:01.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.168.08:08:01.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.168.08:08:01.29$vc4f8/vblo=3,656.99 2006.168.08:08:01.29#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.168.08:08:01.29#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.168.08:08:01.29#ibcon#ireg 17 cls_cnt 0 2006.168.08:08:01.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:08:01.29#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:08:01.29#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:08:01.29#ibcon#enter wrdev, iclass 38, count 0 2006.168.08:08:01.29#ibcon#first serial, iclass 38, count 0 2006.168.08:08:01.29#ibcon#enter sib2, iclass 38, count 0 2006.168.08:08:01.29#ibcon#flushed, iclass 38, count 0 2006.168.08:08:01.29#ibcon#about to write, iclass 38, count 0 2006.168.08:08:01.29#ibcon#wrote, iclass 38, count 0 2006.168.08:08:01.29#ibcon#about to read 3, iclass 38, count 0 2006.168.08:08:01.31#ibcon#read 3, iclass 38, count 0 2006.168.08:08:01.31#ibcon#about to read 4, iclass 38, count 0 2006.168.08:08:01.31#ibcon#read 4, iclass 38, count 0 2006.168.08:08:01.31#ibcon#about to read 5, iclass 38, count 0 2006.168.08:08:01.31#ibcon#read 5, iclass 38, count 0 2006.168.08:08:01.31#ibcon#about to read 6, iclass 38, count 0 2006.168.08:08:01.31#ibcon#read 6, iclass 38, count 0 2006.168.08:08:01.31#ibcon#end of sib2, iclass 38, count 0 2006.168.08:08:01.31#ibcon#*mode == 0, iclass 38, count 0 2006.168.08:08:01.31#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.168.08:08:01.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.08:08:01.31#ibcon#*before write, iclass 38, count 0 2006.168.08:08:01.31#ibcon#enter sib2, iclass 38, count 0 2006.168.08:08:01.31#ibcon#flushed, iclass 38, count 0 2006.168.08:08:01.31#ibcon#about to write, iclass 38, count 0 2006.168.08:08:01.31#ibcon#wrote, iclass 38, count 0 2006.168.08:08:01.31#ibcon#about to read 3, iclass 38, count 0 2006.168.08:08:01.35#ibcon#read 3, iclass 38, count 0 2006.168.08:08:01.35#ibcon#about to read 4, iclass 38, count 0 2006.168.08:08:01.35#ibcon#read 4, iclass 38, count 0 2006.168.08:08:01.35#ibcon#about to read 5, iclass 38, count 0 2006.168.08:08:01.35#ibcon#read 5, iclass 38, count 0 2006.168.08:08:01.35#ibcon#about to read 6, iclass 38, count 0 2006.168.08:08:01.35#ibcon#read 6, iclass 38, count 0 2006.168.08:08:01.35#ibcon#end of sib2, iclass 38, count 0 2006.168.08:08:01.35#ibcon#*after write, iclass 38, count 0 2006.168.08:08:01.35#ibcon#*before return 0, iclass 38, count 0 2006.168.08:08:01.35#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:08:01.35#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:08:01.35#ibcon#about to clear, iclass 38 cls_cnt 0 2006.168.08:08:01.35#ibcon#cleared, iclass 38 cls_cnt 0 2006.168.08:08:01.35$vc4f8/vb=3,4 2006.168.08:08:01.35#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.168.08:08:01.35#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.168.08:08:01.35#ibcon#ireg 11 cls_cnt 2 2006.168.08:08:01.35#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:08:01.42#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:08:01.42#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:08:01.42#ibcon#enter wrdev, iclass 40, count 2 2006.168.08:08:01.42#ibcon#first serial, iclass 40, count 2 2006.168.08:08:01.42#ibcon#enter sib2, iclass 40, count 2 2006.168.08:08:01.42#ibcon#flushed, iclass 40, count 2 2006.168.08:08:01.42#ibcon#about to write, iclass 40, count 2 2006.168.08:08:01.42#ibcon#wrote, iclass 40, count 2 2006.168.08:08:01.42#ibcon#about to read 3, iclass 40, count 2 2006.168.08:08:01.43#ibcon#read 3, iclass 40, count 2 2006.168.08:08:01.43#ibcon#about to read 4, iclass 40, count 2 2006.168.08:08:01.43#ibcon#read 4, iclass 40, count 2 2006.168.08:08:01.43#ibcon#about to read 5, iclass 40, count 2 2006.168.08:08:01.43#ibcon#read 5, iclass 40, count 2 2006.168.08:08:01.43#ibcon#about to read 6, iclass 40, count 2 2006.168.08:08:01.43#ibcon#read 6, iclass 40, count 2 2006.168.08:08:01.43#ibcon#end of sib2, iclass 40, count 2 2006.168.08:08:01.43#ibcon#*mode == 0, iclass 40, count 2 2006.168.08:08:01.43#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.168.08:08:01.43#ibcon#[27=AT03-04\r\n] 2006.168.08:08:01.43#ibcon#*before write, iclass 40, count 2 2006.168.08:08:01.43#ibcon#enter sib2, iclass 40, count 2 2006.168.08:08:01.43#ibcon#flushed, iclass 40, count 2 2006.168.08:08:01.43#ibcon#about to write, iclass 40, count 2 2006.168.08:08:01.43#ibcon#wrote, iclass 40, count 2 2006.168.08:08:01.43#ibcon#about to read 3, iclass 40, count 2 2006.168.08:08:01.46#ibcon#read 3, iclass 40, count 2 2006.168.08:08:01.46#ibcon#about to read 4, iclass 40, count 2 2006.168.08:08:01.46#ibcon#read 4, iclass 40, count 2 2006.168.08:08:01.46#ibcon#about to read 5, iclass 40, count 2 2006.168.08:08:01.46#ibcon#read 5, iclass 40, count 2 2006.168.08:08:01.46#ibcon#about to read 6, iclass 40, count 2 2006.168.08:08:01.46#ibcon#read 6, iclass 40, count 2 2006.168.08:08:01.46#ibcon#end of sib2, iclass 40, count 2 2006.168.08:08:01.46#ibcon#*after write, iclass 40, count 2 2006.168.08:08:01.46#ibcon#*before return 0, iclass 40, count 2 2006.168.08:08:01.46#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:08:01.46#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:08:01.46#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.168.08:08:01.46#ibcon#ireg 7 cls_cnt 0 2006.168.08:08:01.46#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:08:01.58#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:08:01.58#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:08:01.58#ibcon#enter wrdev, iclass 40, count 0 2006.168.08:08:01.58#ibcon#first serial, iclass 40, count 0 2006.168.08:08:01.58#ibcon#enter sib2, iclass 40, count 0 2006.168.08:08:01.58#ibcon#flushed, iclass 40, count 0 2006.168.08:08:01.58#ibcon#about to write, iclass 40, count 0 2006.168.08:08:01.58#ibcon#wrote, iclass 40, count 0 2006.168.08:08:01.58#ibcon#about to read 3, iclass 40, count 0 2006.168.08:08:01.60#ibcon#read 3, iclass 40, count 0 2006.168.08:08:01.60#ibcon#about to read 4, iclass 40, count 0 2006.168.08:08:01.60#ibcon#read 4, iclass 40, count 0 2006.168.08:08:01.60#ibcon#about to read 5, iclass 40, count 0 2006.168.08:08:01.60#ibcon#read 5, iclass 40, count 0 2006.168.08:08:01.60#ibcon#about to read 6, iclass 40, count 0 2006.168.08:08:01.60#ibcon#read 6, iclass 40, count 0 2006.168.08:08:01.60#ibcon#end of sib2, iclass 40, count 0 2006.168.08:08:01.60#ibcon#*mode == 0, iclass 40, count 0 2006.168.08:08:01.60#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.168.08:08:01.60#ibcon#[27=USB\r\n] 2006.168.08:08:01.60#ibcon#*before write, iclass 40, count 0 2006.168.08:08:01.60#ibcon#enter sib2, iclass 40, count 0 2006.168.08:08:01.60#ibcon#flushed, iclass 40, count 0 2006.168.08:08:01.60#ibcon#about to write, iclass 40, count 0 2006.168.08:08:01.60#ibcon#wrote, iclass 40, count 0 2006.168.08:08:01.60#ibcon#about to read 3, iclass 40, count 0 2006.168.08:08:01.63#ibcon#read 3, iclass 40, count 0 2006.168.08:08:01.63#ibcon#about to read 4, iclass 40, count 0 2006.168.08:08:01.63#ibcon#read 4, iclass 40, count 0 2006.168.08:08:01.63#ibcon#about to read 5, iclass 40, count 0 2006.168.08:08:01.63#ibcon#read 5, iclass 40, count 0 2006.168.08:08:01.63#ibcon#about to read 6, iclass 40, count 0 2006.168.08:08:01.63#ibcon#read 6, iclass 40, count 0 2006.168.08:08:01.63#ibcon#end of sib2, iclass 40, count 0 2006.168.08:08:01.63#ibcon#*after write, iclass 40, count 0 2006.168.08:08:01.63#ibcon#*before return 0, iclass 40, count 0 2006.168.08:08:01.63#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:08:01.63#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:08:01.63#ibcon#about to clear, iclass 40 cls_cnt 0 2006.168.08:08:01.63#ibcon#cleared, iclass 40 cls_cnt 0 2006.168.08:08:01.63$vc4f8/vblo=4,712.99 2006.168.08:08:01.63#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.168.08:08:01.63#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.168.08:08:01.63#ibcon#ireg 17 cls_cnt 0 2006.168.08:08:01.63#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:08:01.63#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:08:01.63#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:08:01.63#ibcon#enter wrdev, iclass 4, count 0 2006.168.08:08:01.63#ibcon#first serial, iclass 4, count 0 2006.168.08:08:01.63#ibcon#enter sib2, iclass 4, count 0 2006.168.08:08:01.63#ibcon#flushed, iclass 4, count 0 2006.168.08:08:01.63#ibcon#about to write, iclass 4, count 0 2006.168.08:08:01.63#ibcon#wrote, iclass 4, count 0 2006.168.08:08:01.63#ibcon#about to read 3, iclass 4, count 0 2006.168.08:08:01.65#ibcon#read 3, iclass 4, count 0 2006.168.08:08:01.65#ibcon#about to read 4, iclass 4, count 0 2006.168.08:08:01.65#ibcon#read 4, iclass 4, count 0 2006.168.08:08:01.65#ibcon#about to read 5, iclass 4, count 0 2006.168.08:08:01.65#ibcon#read 5, iclass 4, count 0 2006.168.08:08:01.65#ibcon#about to read 6, iclass 4, count 0 2006.168.08:08:01.65#ibcon#read 6, iclass 4, count 0 2006.168.08:08:01.65#ibcon#end of sib2, iclass 4, count 0 2006.168.08:08:01.65#ibcon#*mode == 0, iclass 4, count 0 2006.168.08:08:01.65#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.168.08:08:01.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.08:08:01.65#ibcon#*before write, iclass 4, count 0 2006.168.08:08:01.65#ibcon#enter sib2, iclass 4, count 0 2006.168.08:08:01.65#ibcon#flushed, iclass 4, count 0 2006.168.08:08:01.65#ibcon#about to write, iclass 4, count 0 2006.168.08:08:01.65#ibcon#wrote, iclass 4, count 0 2006.168.08:08:01.65#ibcon#about to read 3, iclass 4, count 0 2006.168.08:08:01.69#ibcon#read 3, iclass 4, count 0 2006.168.08:08:01.69#ibcon#about to read 4, iclass 4, count 0 2006.168.08:08:01.69#ibcon#read 4, iclass 4, count 0 2006.168.08:08:01.69#ibcon#about to read 5, iclass 4, count 0 2006.168.08:08:01.69#ibcon#read 5, iclass 4, count 0 2006.168.08:08:01.69#ibcon#about to read 6, iclass 4, count 0 2006.168.08:08:01.69#ibcon#read 6, iclass 4, count 0 2006.168.08:08:01.69#ibcon#end of sib2, iclass 4, count 0 2006.168.08:08:01.69#ibcon#*after write, iclass 4, count 0 2006.168.08:08:01.69#ibcon#*before return 0, iclass 4, count 0 2006.168.08:08:01.69#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:08:01.69#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:08:01.69#ibcon#about to clear, iclass 4 cls_cnt 0 2006.168.08:08:01.69#ibcon#cleared, iclass 4 cls_cnt 0 2006.168.08:08:01.69$vc4f8/vb=4,4 2006.168.08:08:01.69#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.168.08:08:01.69#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.168.08:08:01.69#ibcon#ireg 11 cls_cnt 2 2006.168.08:08:01.69#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:08:01.75#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:08:01.75#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:08:01.75#ibcon#enter wrdev, iclass 6, count 2 2006.168.08:08:01.75#ibcon#first serial, iclass 6, count 2 2006.168.08:08:01.75#ibcon#enter sib2, iclass 6, count 2 2006.168.08:08:01.75#ibcon#flushed, iclass 6, count 2 2006.168.08:08:01.75#ibcon#about to write, iclass 6, count 2 2006.168.08:08:01.75#ibcon#wrote, iclass 6, count 2 2006.168.08:08:01.75#ibcon#about to read 3, iclass 6, count 2 2006.168.08:08:01.77#ibcon#read 3, iclass 6, count 2 2006.168.08:08:01.77#ibcon#about to read 4, iclass 6, count 2 2006.168.08:08:01.77#ibcon#read 4, iclass 6, count 2 2006.168.08:08:01.77#ibcon#about to read 5, iclass 6, count 2 2006.168.08:08:01.77#ibcon#read 5, iclass 6, count 2 2006.168.08:08:01.77#ibcon#about to read 6, iclass 6, count 2 2006.168.08:08:01.77#ibcon#read 6, iclass 6, count 2 2006.168.08:08:01.77#ibcon#end of sib2, iclass 6, count 2 2006.168.08:08:01.77#ibcon#*mode == 0, iclass 6, count 2 2006.168.08:08:01.77#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.168.08:08:01.77#ibcon#[27=AT04-04\r\n] 2006.168.08:08:01.77#ibcon#*before write, iclass 6, count 2 2006.168.08:08:01.77#ibcon#enter sib2, iclass 6, count 2 2006.168.08:08:01.77#ibcon#flushed, iclass 6, count 2 2006.168.08:08:01.77#ibcon#about to write, iclass 6, count 2 2006.168.08:08:01.77#ibcon#wrote, iclass 6, count 2 2006.168.08:08:01.77#ibcon#about to read 3, iclass 6, count 2 2006.168.08:08:01.80#ibcon#read 3, iclass 6, count 2 2006.168.08:08:01.80#ibcon#about to read 4, iclass 6, count 2 2006.168.08:08:01.80#ibcon#read 4, iclass 6, count 2 2006.168.08:08:01.80#ibcon#about to read 5, iclass 6, count 2 2006.168.08:08:01.80#ibcon#read 5, iclass 6, count 2 2006.168.08:08:01.80#ibcon#about to read 6, iclass 6, count 2 2006.168.08:08:01.80#ibcon#read 6, iclass 6, count 2 2006.168.08:08:01.80#ibcon#end of sib2, iclass 6, count 2 2006.168.08:08:01.80#ibcon#*after write, iclass 6, count 2 2006.168.08:08:01.80#ibcon#*before return 0, iclass 6, count 2 2006.168.08:08:01.80#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:08:01.80#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:08:01.80#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.168.08:08:01.80#ibcon#ireg 7 cls_cnt 0 2006.168.08:08:01.80#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:08:01.92#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:08:01.92#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:08:01.92#ibcon#enter wrdev, iclass 6, count 0 2006.168.08:08:01.92#ibcon#first serial, iclass 6, count 0 2006.168.08:08:01.92#ibcon#enter sib2, iclass 6, count 0 2006.168.08:08:01.92#ibcon#flushed, iclass 6, count 0 2006.168.08:08:01.92#ibcon#about to write, iclass 6, count 0 2006.168.08:08:01.92#ibcon#wrote, iclass 6, count 0 2006.168.08:08:01.92#ibcon#about to read 3, iclass 6, count 0 2006.168.08:08:01.94#ibcon#read 3, iclass 6, count 0 2006.168.08:08:01.94#ibcon#about to read 4, iclass 6, count 0 2006.168.08:08:01.94#ibcon#read 4, iclass 6, count 0 2006.168.08:08:01.94#ibcon#about to read 5, iclass 6, count 0 2006.168.08:08:01.94#ibcon#read 5, iclass 6, count 0 2006.168.08:08:01.94#ibcon#about to read 6, iclass 6, count 0 2006.168.08:08:01.94#ibcon#read 6, iclass 6, count 0 2006.168.08:08:01.94#ibcon#end of sib2, iclass 6, count 0 2006.168.08:08:01.94#ibcon#*mode == 0, iclass 6, count 0 2006.168.08:08:01.94#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.168.08:08:01.94#ibcon#[27=USB\r\n] 2006.168.08:08:01.94#ibcon#*before write, iclass 6, count 0 2006.168.08:08:01.94#ibcon#enter sib2, iclass 6, count 0 2006.168.08:08:01.94#ibcon#flushed, iclass 6, count 0 2006.168.08:08:01.94#ibcon#about to write, iclass 6, count 0 2006.168.08:08:01.94#ibcon#wrote, iclass 6, count 0 2006.168.08:08:01.94#ibcon#about to read 3, iclass 6, count 0 2006.168.08:08:01.97#ibcon#read 3, iclass 6, count 0 2006.168.08:08:01.97#ibcon#about to read 4, iclass 6, count 0 2006.168.08:08:01.97#ibcon#read 4, iclass 6, count 0 2006.168.08:08:01.97#ibcon#about to read 5, iclass 6, count 0 2006.168.08:08:01.97#ibcon#read 5, iclass 6, count 0 2006.168.08:08:01.97#ibcon#about to read 6, iclass 6, count 0 2006.168.08:08:01.97#ibcon#read 6, iclass 6, count 0 2006.168.08:08:01.97#ibcon#end of sib2, iclass 6, count 0 2006.168.08:08:01.97#ibcon#*after write, iclass 6, count 0 2006.168.08:08:01.97#ibcon#*before return 0, iclass 6, count 0 2006.168.08:08:01.97#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:08:01.97#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:08:01.97#ibcon#about to clear, iclass 6 cls_cnt 0 2006.168.08:08:01.97#ibcon#cleared, iclass 6 cls_cnt 0 2006.168.08:08:01.97$vc4f8/vblo=5,744.99 2006.168.08:08:01.97#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.168.08:08:01.97#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.168.08:08:01.97#ibcon#ireg 17 cls_cnt 0 2006.168.08:08:01.97#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:08:01.97#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:08:01.97#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:08:01.97#ibcon#enter wrdev, iclass 10, count 0 2006.168.08:08:01.97#ibcon#first serial, iclass 10, count 0 2006.168.08:08:01.97#ibcon#enter sib2, iclass 10, count 0 2006.168.08:08:01.97#ibcon#flushed, iclass 10, count 0 2006.168.08:08:01.97#ibcon#about to write, iclass 10, count 0 2006.168.08:08:01.97#ibcon#wrote, iclass 10, count 0 2006.168.08:08:01.97#ibcon#about to read 3, iclass 10, count 0 2006.168.08:08:01.99#ibcon#read 3, iclass 10, count 0 2006.168.08:08:01.99#ibcon#about to read 4, iclass 10, count 0 2006.168.08:08:01.99#ibcon#read 4, iclass 10, count 0 2006.168.08:08:01.99#ibcon#about to read 5, iclass 10, count 0 2006.168.08:08:01.99#ibcon#read 5, iclass 10, count 0 2006.168.08:08:01.99#ibcon#about to read 6, iclass 10, count 0 2006.168.08:08:01.99#ibcon#read 6, iclass 10, count 0 2006.168.08:08:01.99#ibcon#end of sib2, iclass 10, count 0 2006.168.08:08:01.99#ibcon#*mode == 0, iclass 10, count 0 2006.168.08:08:01.99#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.168.08:08:01.99#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.08:08:01.99#ibcon#*before write, iclass 10, count 0 2006.168.08:08:01.99#ibcon#enter sib2, iclass 10, count 0 2006.168.08:08:01.99#ibcon#flushed, iclass 10, count 0 2006.168.08:08:01.99#ibcon#about to write, iclass 10, count 0 2006.168.08:08:01.99#ibcon#wrote, iclass 10, count 0 2006.168.08:08:01.99#ibcon#about to read 3, iclass 10, count 0 2006.168.08:08:02.03#ibcon#read 3, iclass 10, count 0 2006.168.08:08:02.03#ibcon#about to read 4, iclass 10, count 0 2006.168.08:08:02.03#ibcon#read 4, iclass 10, count 0 2006.168.08:08:02.03#ibcon#about to read 5, iclass 10, count 0 2006.168.08:08:02.03#ibcon#read 5, iclass 10, count 0 2006.168.08:08:02.03#ibcon#about to read 6, iclass 10, count 0 2006.168.08:08:02.03#ibcon#read 6, iclass 10, count 0 2006.168.08:08:02.03#ibcon#end of sib2, iclass 10, count 0 2006.168.08:08:02.03#ibcon#*after write, iclass 10, count 0 2006.168.08:08:02.03#ibcon#*before return 0, iclass 10, count 0 2006.168.08:08:02.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:08:02.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:08:02.03#ibcon#about to clear, iclass 10 cls_cnt 0 2006.168.08:08:02.03#ibcon#cleared, iclass 10 cls_cnt 0 2006.168.08:08:02.03$vc4f8/vb=5,4 2006.168.08:08:02.03#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.168.08:08:02.03#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.168.08:08:02.03#ibcon#ireg 11 cls_cnt 2 2006.168.08:08:02.03#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:08:02.10#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:08:02.10#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:08:02.10#ibcon#enter wrdev, iclass 12, count 2 2006.168.08:08:02.10#ibcon#first serial, iclass 12, count 2 2006.168.08:08:02.10#ibcon#enter sib2, iclass 12, count 2 2006.168.08:08:02.10#ibcon#flushed, iclass 12, count 2 2006.168.08:08:02.10#ibcon#about to write, iclass 12, count 2 2006.168.08:08:02.10#ibcon#wrote, iclass 12, count 2 2006.168.08:08:02.10#ibcon#about to read 3, iclass 12, count 2 2006.168.08:08:02.11#ibcon#read 3, iclass 12, count 2 2006.168.08:08:02.11#ibcon#about to read 4, iclass 12, count 2 2006.168.08:08:02.11#ibcon#read 4, iclass 12, count 2 2006.168.08:08:02.11#ibcon#about to read 5, iclass 12, count 2 2006.168.08:08:02.11#ibcon#read 5, iclass 12, count 2 2006.168.08:08:02.11#ibcon#about to read 6, iclass 12, count 2 2006.168.08:08:02.11#ibcon#read 6, iclass 12, count 2 2006.168.08:08:02.11#ibcon#end of sib2, iclass 12, count 2 2006.168.08:08:02.11#ibcon#*mode == 0, iclass 12, count 2 2006.168.08:08:02.11#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.168.08:08:02.11#ibcon#[27=AT05-04\r\n] 2006.168.08:08:02.11#ibcon#*before write, iclass 12, count 2 2006.168.08:08:02.11#ibcon#enter sib2, iclass 12, count 2 2006.168.08:08:02.11#ibcon#flushed, iclass 12, count 2 2006.168.08:08:02.11#ibcon#about to write, iclass 12, count 2 2006.168.08:08:02.11#ibcon#wrote, iclass 12, count 2 2006.168.08:08:02.11#ibcon#about to read 3, iclass 12, count 2 2006.168.08:08:02.14#ibcon#read 3, iclass 12, count 2 2006.168.08:08:02.14#ibcon#about to read 4, iclass 12, count 2 2006.168.08:08:02.14#ibcon#read 4, iclass 12, count 2 2006.168.08:08:02.14#ibcon#about to read 5, iclass 12, count 2 2006.168.08:08:02.14#ibcon#read 5, iclass 12, count 2 2006.168.08:08:02.14#ibcon#about to read 6, iclass 12, count 2 2006.168.08:08:02.14#ibcon#read 6, iclass 12, count 2 2006.168.08:08:02.14#ibcon#end of sib2, iclass 12, count 2 2006.168.08:08:02.14#ibcon#*after write, iclass 12, count 2 2006.168.08:08:02.14#ibcon#*before return 0, iclass 12, count 2 2006.168.08:08:02.14#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:08:02.14#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:08:02.14#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.168.08:08:02.14#ibcon#ireg 7 cls_cnt 0 2006.168.08:08:02.14#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:08:02.26#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:08:02.26#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:08:02.26#ibcon#enter wrdev, iclass 12, count 0 2006.168.08:08:02.26#ibcon#first serial, iclass 12, count 0 2006.168.08:08:02.26#ibcon#enter sib2, iclass 12, count 0 2006.168.08:08:02.26#ibcon#flushed, iclass 12, count 0 2006.168.08:08:02.26#ibcon#about to write, iclass 12, count 0 2006.168.08:08:02.26#ibcon#wrote, iclass 12, count 0 2006.168.08:08:02.26#ibcon#about to read 3, iclass 12, count 0 2006.168.08:08:02.28#ibcon#read 3, iclass 12, count 0 2006.168.08:08:02.28#ibcon#about to read 4, iclass 12, count 0 2006.168.08:08:02.28#ibcon#read 4, iclass 12, count 0 2006.168.08:08:02.28#ibcon#about to read 5, iclass 12, count 0 2006.168.08:08:02.28#ibcon#read 5, iclass 12, count 0 2006.168.08:08:02.28#ibcon#about to read 6, iclass 12, count 0 2006.168.08:08:02.28#ibcon#read 6, iclass 12, count 0 2006.168.08:08:02.28#ibcon#end of sib2, iclass 12, count 0 2006.168.08:08:02.28#ibcon#*mode == 0, iclass 12, count 0 2006.168.08:08:02.28#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.168.08:08:02.28#ibcon#[27=USB\r\n] 2006.168.08:08:02.28#ibcon#*before write, iclass 12, count 0 2006.168.08:08:02.28#ibcon#enter sib2, iclass 12, count 0 2006.168.08:08:02.28#ibcon#flushed, iclass 12, count 0 2006.168.08:08:02.28#ibcon#about to write, iclass 12, count 0 2006.168.08:08:02.28#ibcon#wrote, iclass 12, count 0 2006.168.08:08:02.28#ibcon#about to read 3, iclass 12, count 0 2006.168.08:08:02.31#ibcon#read 3, iclass 12, count 0 2006.168.08:08:02.31#ibcon#about to read 4, iclass 12, count 0 2006.168.08:08:02.31#ibcon#read 4, iclass 12, count 0 2006.168.08:08:02.31#ibcon#about to read 5, iclass 12, count 0 2006.168.08:08:02.31#ibcon#read 5, iclass 12, count 0 2006.168.08:08:02.31#ibcon#about to read 6, iclass 12, count 0 2006.168.08:08:02.31#ibcon#read 6, iclass 12, count 0 2006.168.08:08:02.31#ibcon#end of sib2, iclass 12, count 0 2006.168.08:08:02.31#ibcon#*after write, iclass 12, count 0 2006.168.08:08:02.31#ibcon#*before return 0, iclass 12, count 0 2006.168.08:08:02.31#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:08:02.31#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:08:02.31#ibcon#about to clear, iclass 12 cls_cnt 0 2006.168.08:08:02.31#ibcon#cleared, iclass 12 cls_cnt 0 2006.168.08:08:02.31$vc4f8/vblo=6,752.99 2006.168.08:08:02.31#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.168.08:08:02.31#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.168.08:08:02.31#ibcon#ireg 17 cls_cnt 0 2006.168.08:08:02.31#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:08:02.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:08:02.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:08:02.31#ibcon#enter wrdev, iclass 14, count 0 2006.168.08:08:02.31#ibcon#first serial, iclass 14, count 0 2006.168.08:08:02.31#ibcon#enter sib2, iclass 14, count 0 2006.168.08:08:02.31#ibcon#flushed, iclass 14, count 0 2006.168.08:08:02.31#ibcon#about to write, iclass 14, count 0 2006.168.08:08:02.31#ibcon#wrote, iclass 14, count 0 2006.168.08:08:02.31#ibcon#about to read 3, iclass 14, count 0 2006.168.08:08:02.33#ibcon#read 3, iclass 14, count 0 2006.168.08:08:02.33#ibcon#about to read 4, iclass 14, count 0 2006.168.08:08:02.33#ibcon#read 4, iclass 14, count 0 2006.168.08:08:02.33#ibcon#about to read 5, iclass 14, count 0 2006.168.08:08:02.33#ibcon#read 5, iclass 14, count 0 2006.168.08:08:02.33#ibcon#about to read 6, iclass 14, count 0 2006.168.08:08:02.33#ibcon#read 6, iclass 14, count 0 2006.168.08:08:02.33#ibcon#end of sib2, iclass 14, count 0 2006.168.08:08:02.33#ibcon#*mode == 0, iclass 14, count 0 2006.168.08:08:02.33#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.168.08:08:02.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.08:08:02.33#ibcon#*before write, iclass 14, count 0 2006.168.08:08:02.33#ibcon#enter sib2, iclass 14, count 0 2006.168.08:08:02.33#ibcon#flushed, iclass 14, count 0 2006.168.08:08:02.33#ibcon#about to write, iclass 14, count 0 2006.168.08:08:02.33#ibcon#wrote, iclass 14, count 0 2006.168.08:08:02.33#ibcon#about to read 3, iclass 14, count 0 2006.168.08:08:02.37#ibcon#read 3, iclass 14, count 0 2006.168.08:08:02.37#ibcon#about to read 4, iclass 14, count 0 2006.168.08:08:02.37#ibcon#read 4, iclass 14, count 0 2006.168.08:08:02.37#ibcon#about to read 5, iclass 14, count 0 2006.168.08:08:02.37#ibcon#read 5, iclass 14, count 0 2006.168.08:08:02.37#ibcon#about to read 6, iclass 14, count 0 2006.168.08:08:02.37#ibcon#read 6, iclass 14, count 0 2006.168.08:08:02.37#ibcon#end of sib2, iclass 14, count 0 2006.168.08:08:02.37#ibcon#*after write, iclass 14, count 0 2006.168.08:08:02.37#ibcon#*before return 0, iclass 14, count 0 2006.168.08:08:02.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:08:02.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:08:02.37#ibcon#about to clear, iclass 14 cls_cnt 0 2006.168.08:08:02.37#ibcon#cleared, iclass 14 cls_cnt 0 2006.168.08:08:02.37$vc4f8/vb=6,4 2006.168.08:08:02.37#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.168.08:08:02.37#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.168.08:08:02.37#ibcon#ireg 11 cls_cnt 2 2006.168.08:08:02.37#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:08:02.43#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:08:02.43#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:08:02.43#ibcon#enter wrdev, iclass 16, count 2 2006.168.08:08:02.43#ibcon#first serial, iclass 16, count 2 2006.168.08:08:02.43#ibcon#enter sib2, iclass 16, count 2 2006.168.08:08:02.43#ibcon#flushed, iclass 16, count 2 2006.168.08:08:02.43#ibcon#about to write, iclass 16, count 2 2006.168.08:08:02.43#ibcon#wrote, iclass 16, count 2 2006.168.08:08:02.43#ibcon#about to read 3, iclass 16, count 2 2006.168.08:08:02.45#ibcon#read 3, iclass 16, count 2 2006.168.08:08:02.45#ibcon#about to read 4, iclass 16, count 2 2006.168.08:08:02.45#ibcon#read 4, iclass 16, count 2 2006.168.08:08:02.45#ibcon#about to read 5, iclass 16, count 2 2006.168.08:08:02.45#ibcon#read 5, iclass 16, count 2 2006.168.08:08:02.45#ibcon#about to read 6, iclass 16, count 2 2006.168.08:08:02.45#ibcon#read 6, iclass 16, count 2 2006.168.08:08:02.45#ibcon#end of sib2, iclass 16, count 2 2006.168.08:08:02.45#ibcon#*mode == 0, iclass 16, count 2 2006.168.08:08:02.45#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.168.08:08:02.45#ibcon#[27=AT06-04\r\n] 2006.168.08:08:02.45#ibcon#*before write, iclass 16, count 2 2006.168.08:08:02.45#ibcon#enter sib2, iclass 16, count 2 2006.168.08:08:02.45#ibcon#flushed, iclass 16, count 2 2006.168.08:08:02.45#ibcon#about to write, iclass 16, count 2 2006.168.08:08:02.45#ibcon#wrote, iclass 16, count 2 2006.168.08:08:02.45#ibcon#about to read 3, iclass 16, count 2 2006.168.08:08:02.48#ibcon#read 3, iclass 16, count 2 2006.168.08:08:02.48#ibcon#about to read 4, iclass 16, count 2 2006.168.08:08:02.48#ibcon#read 4, iclass 16, count 2 2006.168.08:08:02.48#ibcon#about to read 5, iclass 16, count 2 2006.168.08:08:02.48#ibcon#read 5, iclass 16, count 2 2006.168.08:08:02.48#ibcon#about to read 6, iclass 16, count 2 2006.168.08:08:02.48#ibcon#read 6, iclass 16, count 2 2006.168.08:08:02.48#ibcon#end of sib2, iclass 16, count 2 2006.168.08:08:02.48#ibcon#*after write, iclass 16, count 2 2006.168.08:08:02.48#ibcon#*before return 0, iclass 16, count 2 2006.168.08:08:02.48#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:08:02.48#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:08:02.48#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.168.08:08:02.48#ibcon#ireg 7 cls_cnt 0 2006.168.08:08:02.48#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:08:02.60#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:08:02.60#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:08:02.60#ibcon#enter wrdev, iclass 16, count 0 2006.168.08:08:02.60#ibcon#first serial, iclass 16, count 0 2006.168.08:08:02.60#ibcon#enter sib2, iclass 16, count 0 2006.168.08:08:02.60#ibcon#flushed, iclass 16, count 0 2006.168.08:08:02.60#ibcon#about to write, iclass 16, count 0 2006.168.08:08:02.60#ibcon#wrote, iclass 16, count 0 2006.168.08:08:02.60#ibcon#about to read 3, iclass 16, count 0 2006.168.08:08:02.62#ibcon#read 3, iclass 16, count 0 2006.168.08:08:02.62#ibcon#about to read 4, iclass 16, count 0 2006.168.08:08:02.62#ibcon#read 4, iclass 16, count 0 2006.168.08:08:02.62#ibcon#about to read 5, iclass 16, count 0 2006.168.08:08:02.62#ibcon#read 5, iclass 16, count 0 2006.168.08:08:02.62#ibcon#about to read 6, iclass 16, count 0 2006.168.08:08:02.62#ibcon#read 6, iclass 16, count 0 2006.168.08:08:02.62#ibcon#end of sib2, iclass 16, count 0 2006.168.08:08:02.62#ibcon#*mode == 0, iclass 16, count 0 2006.168.08:08:02.62#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.168.08:08:02.62#ibcon#[27=USB\r\n] 2006.168.08:08:02.62#ibcon#*before write, iclass 16, count 0 2006.168.08:08:02.62#ibcon#enter sib2, iclass 16, count 0 2006.168.08:08:02.62#ibcon#flushed, iclass 16, count 0 2006.168.08:08:02.62#ibcon#about to write, iclass 16, count 0 2006.168.08:08:02.62#ibcon#wrote, iclass 16, count 0 2006.168.08:08:02.62#ibcon#about to read 3, iclass 16, count 0 2006.168.08:08:02.65#ibcon#read 3, iclass 16, count 0 2006.168.08:08:02.65#ibcon#about to read 4, iclass 16, count 0 2006.168.08:08:02.65#ibcon#read 4, iclass 16, count 0 2006.168.08:08:02.65#ibcon#about to read 5, iclass 16, count 0 2006.168.08:08:02.65#ibcon#read 5, iclass 16, count 0 2006.168.08:08:02.65#ibcon#about to read 6, iclass 16, count 0 2006.168.08:08:02.65#ibcon#read 6, iclass 16, count 0 2006.168.08:08:02.65#ibcon#end of sib2, iclass 16, count 0 2006.168.08:08:02.65#ibcon#*after write, iclass 16, count 0 2006.168.08:08:02.65#ibcon#*before return 0, iclass 16, count 0 2006.168.08:08:02.65#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:08:02.65#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:08:02.65#ibcon#about to clear, iclass 16 cls_cnt 0 2006.168.08:08:02.65#ibcon#cleared, iclass 16 cls_cnt 0 2006.168.08:08:02.65$vc4f8/vabw=wide 2006.168.08:08:02.65#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.168.08:08:02.65#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.168.08:08:02.65#ibcon#ireg 8 cls_cnt 0 2006.168.08:08:02.65#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:08:02.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:08:02.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:08:02.65#ibcon#enter wrdev, iclass 18, count 0 2006.168.08:08:02.65#ibcon#first serial, iclass 18, count 0 2006.168.08:08:02.65#ibcon#enter sib2, iclass 18, count 0 2006.168.08:08:02.65#ibcon#flushed, iclass 18, count 0 2006.168.08:08:02.65#ibcon#about to write, iclass 18, count 0 2006.168.08:08:02.65#ibcon#wrote, iclass 18, count 0 2006.168.08:08:02.65#ibcon#about to read 3, iclass 18, count 0 2006.168.08:08:02.67#ibcon#read 3, iclass 18, count 0 2006.168.08:08:02.67#ibcon#about to read 4, iclass 18, count 0 2006.168.08:08:02.67#ibcon#read 4, iclass 18, count 0 2006.168.08:08:02.67#ibcon#about to read 5, iclass 18, count 0 2006.168.08:08:02.67#ibcon#read 5, iclass 18, count 0 2006.168.08:08:02.67#ibcon#about to read 6, iclass 18, count 0 2006.168.08:08:02.67#ibcon#read 6, iclass 18, count 0 2006.168.08:08:02.67#ibcon#end of sib2, iclass 18, count 0 2006.168.08:08:02.67#ibcon#*mode == 0, iclass 18, count 0 2006.168.08:08:02.67#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.08:08:02.67#ibcon#[25=BW32\r\n] 2006.168.08:08:02.67#ibcon#*before write, iclass 18, count 0 2006.168.08:08:02.67#ibcon#enter sib2, iclass 18, count 0 2006.168.08:08:02.67#ibcon#flushed, iclass 18, count 0 2006.168.08:08:02.67#ibcon#about to write, iclass 18, count 0 2006.168.08:08:02.67#ibcon#wrote, iclass 18, count 0 2006.168.08:08:02.67#ibcon#about to read 3, iclass 18, count 0 2006.168.08:08:02.70#ibcon#read 3, iclass 18, count 0 2006.168.08:08:02.70#ibcon#about to read 4, iclass 18, count 0 2006.168.08:08:02.70#ibcon#read 4, iclass 18, count 0 2006.168.08:08:02.70#ibcon#about to read 5, iclass 18, count 0 2006.168.08:08:02.70#ibcon#read 5, iclass 18, count 0 2006.168.08:08:02.70#ibcon#about to read 6, iclass 18, count 0 2006.168.08:08:02.70#ibcon#read 6, iclass 18, count 0 2006.168.08:08:02.70#ibcon#end of sib2, iclass 18, count 0 2006.168.08:08:02.70#ibcon#*after write, iclass 18, count 0 2006.168.08:08:02.70#ibcon#*before return 0, iclass 18, count 0 2006.168.08:08:02.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:08:02.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:08:02.70#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.08:08:02.70#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.08:08:02.70$vc4f8/vbbw=wide 2006.168.08:08:02.70#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.168.08:08:02.70#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.168.08:08:02.70#ibcon#ireg 8 cls_cnt 0 2006.168.08:08:02.70#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:08:02.78#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:08:02.78#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:08:02.78#ibcon#enter wrdev, iclass 20, count 0 2006.168.08:08:02.78#ibcon#first serial, iclass 20, count 0 2006.168.08:08:02.78#ibcon#enter sib2, iclass 20, count 0 2006.168.08:08:02.78#ibcon#flushed, iclass 20, count 0 2006.168.08:08:02.78#ibcon#about to write, iclass 20, count 0 2006.168.08:08:02.78#ibcon#wrote, iclass 20, count 0 2006.168.08:08:02.78#ibcon#about to read 3, iclass 20, count 0 2006.168.08:08:02.79#ibcon#read 3, iclass 20, count 0 2006.168.08:08:02.79#ibcon#about to read 4, iclass 20, count 0 2006.168.08:08:02.79#ibcon#read 4, iclass 20, count 0 2006.168.08:08:02.79#ibcon#about to read 5, iclass 20, count 0 2006.168.08:08:02.79#ibcon#read 5, iclass 20, count 0 2006.168.08:08:02.79#ibcon#about to read 6, iclass 20, count 0 2006.168.08:08:02.79#ibcon#read 6, iclass 20, count 0 2006.168.08:08:02.79#ibcon#end of sib2, iclass 20, count 0 2006.168.08:08:02.79#ibcon#*mode == 0, iclass 20, count 0 2006.168.08:08:02.79#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.168.08:08:02.79#ibcon#[27=BW32\r\n] 2006.168.08:08:02.79#ibcon#*before write, iclass 20, count 0 2006.168.08:08:02.79#ibcon#enter sib2, iclass 20, count 0 2006.168.08:08:02.79#ibcon#flushed, iclass 20, count 0 2006.168.08:08:02.79#ibcon#about to write, iclass 20, count 0 2006.168.08:08:02.79#ibcon#wrote, iclass 20, count 0 2006.168.08:08:02.79#ibcon#about to read 3, iclass 20, count 0 2006.168.08:08:02.82#ibcon#read 3, iclass 20, count 0 2006.168.08:08:02.82#ibcon#about to read 4, iclass 20, count 0 2006.168.08:08:02.82#ibcon#read 4, iclass 20, count 0 2006.168.08:08:02.82#ibcon#about to read 5, iclass 20, count 0 2006.168.08:08:02.82#ibcon#read 5, iclass 20, count 0 2006.168.08:08:02.82#ibcon#about to read 6, iclass 20, count 0 2006.168.08:08:02.82#ibcon#read 6, iclass 20, count 0 2006.168.08:08:02.82#ibcon#end of sib2, iclass 20, count 0 2006.168.08:08:02.82#ibcon#*after write, iclass 20, count 0 2006.168.08:08:02.82#ibcon#*before return 0, iclass 20, count 0 2006.168.08:08:02.82#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:08:02.82#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:08:02.82#ibcon#about to clear, iclass 20 cls_cnt 0 2006.168.08:08:02.82#ibcon#cleared, iclass 20 cls_cnt 0 2006.168.08:08:02.82$4f8m12a/ifd4f 2006.168.08:08:02.82$ifd4f/lo= 2006.168.08:08:02.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.08:08:02.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.08:08:02.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.08:08:02.82$ifd4f/patch= 2006.168.08:08:02.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.08:08:02.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.08:08:02.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.08:08:02.82$4f8m12a/"form=m,16.000,1:2 2006.168.08:08:02.82$4f8m12a/"tpicd 2006.168.08:08:02.82$4f8m12a/echo=off 2006.168.08:08:02.82$4f8m12a/xlog=off 2006.168.08:08:02.82:!2006.168.08:08:30 2006.168.08:08:12.14#trakl#Source acquired 2006.168.08:08:12.14#flagr#flagr/antenna,acquired 2006.168.08:08:30.00:preob 2006.168.08:08:31.14/onsource/TRACKING 2006.168.08:08:31.14:!2006.168.08:08:40 2006.168.08:08:40.00:data_valid=on 2006.168.08:08:40.00:midob 2006.168.08:08:40.14/onsource/TRACKING 2006.168.08:08:40.14/wx/26.96,1004.4,74 2006.168.08:08:40.29/cable/+6.4709E-03 2006.168.08:08:41.38/va/01,08,usb,yes,30,32 2006.168.08:08:41.38/va/02,07,usb,yes,30,32 2006.168.08:08:41.38/va/03,06,usb,yes,32,32 2006.168.08:08:41.38/va/04,07,usb,yes,31,33 2006.168.08:08:41.38/va/05,07,usb,yes,31,33 2006.168.08:08:41.38/va/06,06,usb,yes,30,30 2006.168.08:08:41.38/va/07,06,usb,yes,31,30 2006.168.08:08:41.38/va/08,07,usb,yes,29,29 2006.168.08:08:41.61/valo/01,532.99,yes,locked 2006.168.08:08:41.61/valo/02,572.99,yes,locked 2006.168.08:08:41.61/valo/03,672.99,yes,locked 2006.168.08:08:41.61/valo/04,832.99,yes,locked 2006.168.08:08:41.61/valo/05,652.99,yes,locked 2006.168.08:08:41.61/valo/06,772.99,yes,locked 2006.168.08:08:41.61/valo/07,832.99,yes,locked 2006.168.08:08:41.61/valo/08,852.99,yes,locked 2006.168.08:08:42.70/vb/01,04,usb,yes,30,28 2006.168.08:08:42.70/vb/02,04,usb,yes,32,33 2006.168.08:08:42.70/vb/03,04,usb,yes,28,32 2006.168.08:08:42.70/vb/04,04,usb,yes,29,29 2006.168.08:08:42.70/vb/05,04,usb,yes,27,31 2006.168.08:08:42.70/vb/06,04,usb,yes,28,31 2006.168.08:08:42.70/vb/07,04,usb,yes,30,30 2006.168.08:08:42.70/vb/08,04,usb,yes,28,31 2006.168.08:08:42.94/vblo/01,632.99,yes,locked 2006.168.08:08:42.94/vblo/02,640.99,yes,locked 2006.168.08:08:42.94/vblo/03,656.99,yes,locked 2006.168.08:08:42.94/vblo/04,712.99,yes,locked 2006.168.08:08:42.94/vblo/05,744.99,yes,locked 2006.168.08:08:42.94/vblo/06,752.99,yes,locked 2006.168.08:08:42.94/vblo/07,734.99,yes,locked 2006.168.08:08:42.94/vblo/08,744.99,yes,locked 2006.168.08:08:43.09/vabw/8 2006.168.08:08:43.24/vbbw/8 2006.168.08:08:43.33/xfe/off,on,15.2 2006.168.08:08:43.70/ifatt/23,28,28,28 2006.168.08:08:44.08/fmout-gps/S +4.19E-07 2006.168.08:08:44.12:!2006.168.08:09:40 2006.168.08:09:40.00:data_valid=off 2006.168.08:09:40.00:postob 2006.168.08:09:40.16/cable/+6.4717E-03 2006.168.08:09:40.16/wx/26.96,1004.5,75 2006.168.08:09:41.08/fmout-gps/S +4.18E-07 2006.168.08:09:41.08:scan_name=168-0810,k06168,60 2006.168.08:09:41.08:source=0743+259,074625.87,254902.1,2000.0,ccw 2006.168.08:09:41.13#flagr#flagr/antenna,new-source 2006.168.08:09:42.13:checkk5 2006.168.08:09:42.47/chk_autoobs//k5ts1/ autoobs is running! 2006.168.08:09:42.85/chk_autoobs//k5ts2/ autoobs is running! 2006.168.08:09:43.23/chk_autoobs//k5ts3/ autoobs is running! 2006.168.08:09:43.60/chk_autoobs//k5ts4/ autoobs is running! 2006.168.08:09:43.97/chk_obsdata//k5ts1/T1680808??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:09:44.33/chk_obsdata//k5ts2/T1680808??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:09:44.71/chk_obsdata//k5ts3/T1680808??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:09:45.08/chk_obsdata//k5ts4/T1680808??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:09:45.77/k5log//k5ts1_log_newline 2006.168.08:09:46.46/k5log//k5ts2_log_newline 2006.168.08:09:47.15/k5log//k5ts3_log_newline 2006.168.08:09:47.84/k5log//k5ts4_log_newline 2006.168.08:09:47.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.08:09:47.86:4f8m12a=2 2006.168.08:09:47.86$4f8m12a/echo=on 2006.168.08:09:47.86$4f8m12a/pcalon 2006.168.08:09:47.86$pcalon/"no phase cal control is implemented here 2006.168.08:09:47.86$4f8m12a/"tpicd=stop 2006.168.08:09:47.86$4f8m12a/vc4f8 2006.168.08:09:47.86$vc4f8/valo=1,532.99 2006.168.08:09:47.86#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.168.08:09:47.86#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.168.08:09:47.86#ibcon#ireg 17 cls_cnt 0 2006.168.08:09:47.86#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:09:47.86#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:09:47.86#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:09:47.86#ibcon#enter wrdev, iclass 27, count 0 2006.168.08:09:47.86#ibcon#first serial, iclass 27, count 0 2006.168.08:09:47.86#ibcon#enter sib2, iclass 27, count 0 2006.168.08:09:47.86#ibcon#flushed, iclass 27, count 0 2006.168.08:09:47.86#ibcon#about to write, iclass 27, count 0 2006.168.08:09:47.86#ibcon#wrote, iclass 27, count 0 2006.168.08:09:47.86#ibcon#about to read 3, iclass 27, count 0 2006.168.08:09:47.88#ibcon#read 3, iclass 27, count 0 2006.168.08:09:47.88#ibcon#about to read 4, iclass 27, count 0 2006.168.08:09:47.88#ibcon#read 4, iclass 27, count 0 2006.168.08:09:47.88#ibcon#about to read 5, iclass 27, count 0 2006.168.08:09:47.88#ibcon#read 5, iclass 27, count 0 2006.168.08:09:47.88#ibcon#about to read 6, iclass 27, count 0 2006.168.08:09:47.88#ibcon#read 6, iclass 27, count 0 2006.168.08:09:47.88#ibcon#end of sib2, iclass 27, count 0 2006.168.08:09:47.88#ibcon#*mode == 0, iclass 27, count 0 2006.168.08:09:47.88#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.168.08:09:47.88#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.08:09:47.88#ibcon#*before write, iclass 27, count 0 2006.168.08:09:47.88#ibcon#enter sib2, iclass 27, count 0 2006.168.08:09:47.88#ibcon#flushed, iclass 27, count 0 2006.168.08:09:47.88#ibcon#about to write, iclass 27, count 0 2006.168.08:09:47.88#ibcon#wrote, iclass 27, count 0 2006.168.08:09:47.88#ibcon#about to read 3, iclass 27, count 0 2006.168.08:09:47.93#ibcon#read 3, iclass 27, count 0 2006.168.08:09:47.93#ibcon#about to read 4, iclass 27, count 0 2006.168.08:09:47.93#ibcon#read 4, iclass 27, count 0 2006.168.08:09:47.93#ibcon#about to read 5, iclass 27, count 0 2006.168.08:09:47.93#ibcon#read 5, iclass 27, count 0 2006.168.08:09:47.93#ibcon#about to read 6, iclass 27, count 0 2006.168.08:09:47.93#ibcon#read 6, iclass 27, count 0 2006.168.08:09:47.93#ibcon#end of sib2, iclass 27, count 0 2006.168.08:09:47.93#ibcon#*after write, iclass 27, count 0 2006.168.08:09:47.93#ibcon#*before return 0, iclass 27, count 0 2006.168.08:09:47.93#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:09:47.93#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:09:47.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.168.08:09:47.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.168.08:09:47.93$vc4f8/va=1,8 2006.168.08:09:47.93#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.168.08:09:47.93#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.168.08:09:47.93#ibcon#ireg 11 cls_cnt 2 2006.168.08:09:47.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:09:47.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:09:47.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:09:47.93#ibcon#enter wrdev, iclass 29, count 2 2006.168.08:09:47.93#ibcon#first serial, iclass 29, count 2 2006.168.08:09:47.93#ibcon#enter sib2, iclass 29, count 2 2006.168.08:09:47.93#ibcon#flushed, iclass 29, count 2 2006.168.08:09:47.93#ibcon#about to write, iclass 29, count 2 2006.168.08:09:47.93#ibcon#wrote, iclass 29, count 2 2006.168.08:09:47.93#ibcon#about to read 3, iclass 29, count 2 2006.168.08:09:47.95#ibcon#read 3, iclass 29, count 2 2006.168.08:09:47.95#ibcon#about to read 4, iclass 29, count 2 2006.168.08:09:47.95#ibcon#read 4, iclass 29, count 2 2006.168.08:09:47.95#ibcon#about to read 5, iclass 29, count 2 2006.168.08:09:47.95#ibcon#read 5, iclass 29, count 2 2006.168.08:09:47.95#ibcon#about to read 6, iclass 29, count 2 2006.168.08:09:47.95#ibcon#read 6, iclass 29, count 2 2006.168.08:09:47.95#ibcon#end of sib2, iclass 29, count 2 2006.168.08:09:47.95#ibcon#*mode == 0, iclass 29, count 2 2006.168.08:09:47.95#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.168.08:09:47.95#ibcon#[25=AT01-08\r\n] 2006.168.08:09:47.95#ibcon#*before write, iclass 29, count 2 2006.168.08:09:47.95#ibcon#enter sib2, iclass 29, count 2 2006.168.08:09:47.95#ibcon#flushed, iclass 29, count 2 2006.168.08:09:47.95#ibcon#about to write, iclass 29, count 2 2006.168.08:09:47.95#ibcon#wrote, iclass 29, count 2 2006.168.08:09:47.95#ibcon#about to read 3, iclass 29, count 2 2006.168.08:09:47.98#ibcon#read 3, iclass 29, count 2 2006.168.08:09:47.98#ibcon#about to read 4, iclass 29, count 2 2006.168.08:09:47.98#ibcon#read 4, iclass 29, count 2 2006.168.08:09:47.98#ibcon#about to read 5, iclass 29, count 2 2006.168.08:09:47.98#ibcon#read 5, iclass 29, count 2 2006.168.08:09:47.98#ibcon#about to read 6, iclass 29, count 2 2006.168.08:09:47.98#ibcon#read 6, iclass 29, count 2 2006.168.08:09:47.98#ibcon#end of sib2, iclass 29, count 2 2006.168.08:09:47.98#ibcon#*after write, iclass 29, count 2 2006.168.08:09:47.98#ibcon#*before return 0, iclass 29, count 2 2006.168.08:09:47.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:09:47.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:09:47.98#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.168.08:09:47.98#ibcon#ireg 7 cls_cnt 0 2006.168.08:09:47.98#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:09:48.10#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:09:48.10#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:09:48.10#ibcon#enter wrdev, iclass 29, count 0 2006.168.08:09:48.10#ibcon#first serial, iclass 29, count 0 2006.168.08:09:48.10#ibcon#enter sib2, iclass 29, count 0 2006.168.08:09:48.10#ibcon#flushed, iclass 29, count 0 2006.168.08:09:48.10#ibcon#about to write, iclass 29, count 0 2006.168.08:09:48.10#ibcon#wrote, iclass 29, count 0 2006.168.08:09:48.10#ibcon#about to read 3, iclass 29, count 0 2006.168.08:09:48.12#ibcon#read 3, iclass 29, count 0 2006.168.08:09:48.12#ibcon#about to read 4, iclass 29, count 0 2006.168.08:09:48.12#ibcon#read 4, iclass 29, count 0 2006.168.08:09:48.12#ibcon#about to read 5, iclass 29, count 0 2006.168.08:09:48.12#ibcon#read 5, iclass 29, count 0 2006.168.08:09:48.12#ibcon#about to read 6, iclass 29, count 0 2006.168.08:09:48.12#ibcon#read 6, iclass 29, count 0 2006.168.08:09:48.12#ibcon#end of sib2, iclass 29, count 0 2006.168.08:09:48.12#ibcon#*mode == 0, iclass 29, count 0 2006.168.08:09:48.12#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.168.08:09:48.12#ibcon#[25=USB\r\n] 2006.168.08:09:48.12#ibcon#*before write, iclass 29, count 0 2006.168.08:09:48.12#ibcon#enter sib2, iclass 29, count 0 2006.168.08:09:48.12#ibcon#flushed, iclass 29, count 0 2006.168.08:09:48.12#ibcon#about to write, iclass 29, count 0 2006.168.08:09:48.12#ibcon#wrote, iclass 29, count 0 2006.168.08:09:48.12#ibcon#about to read 3, iclass 29, count 0 2006.168.08:09:48.15#ibcon#read 3, iclass 29, count 0 2006.168.08:09:48.15#ibcon#about to read 4, iclass 29, count 0 2006.168.08:09:48.15#ibcon#read 4, iclass 29, count 0 2006.168.08:09:48.15#ibcon#about to read 5, iclass 29, count 0 2006.168.08:09:48.15#ibcon#read 5, iclass 29, count 0 2006.168.08:09:48.15#ibcon#about to read 6, iclass 29, count 0 2006.168.08:09:48.15#ibcon#read 6, iclass 29, count 0 2006.168.08:09:48.15#ibcon#end of sib2, iclass 29, count 0 2006.168.08:09:48.15#ibcon#*after write, iclass 29, count 0 2006.168.08:09:48.15#ibcon#*before return 0, iclass 29, count 0 2006.168.08:09:48.15#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:09:48.15#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:09:48.15#ibcon#about to clear, iclass 29 cls_cnt 0 2006.168.08:09:48.15#ibcon#cleared, iclass 29 cls_cnt 0 2006.168.08:09:48.15$vc4f8/valo=2,572.99 2006.168.08:09:48.15#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.168.08:09:48.15#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.168.08:09:48.15#ibcon#ireg 17 cls_cnt 0 2006.168.08:09:48.15#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:09:48.15#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:09:48.15#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:09:48.15#ibcon#enter wrdev, iclass 31, count 0 2006.168.08:09:48.15#ibcon#first serial, iclass 31, count 0 2006.168.08:09:48.15#ibcon#enter sib2, iclass 31, count 0 2006.168.08:09:48.15#ibcon#flushed, iclass 31, count 0 2006.168.08:09:48.15#ibcon#about to write, iclass 31, count 0 2006.168.08:09:48.15#ibcon#wrote, iclass 31, count 0 2006.168.08:09:48.15#ibcon#about to read 3, iclass 31, count 0 2006.168.08:09:48.17#ibcon#read 3, iclass 31, count 0 2006.168.08:09:48.17#ibcon#about to read 4, iclass 31, count 0 2006.168.08:09:48.17#ibcon#read 4, iclass 31, count 0 2006.168.08:09:48.17#ibcon#about to read 5, iclass 31, count 0 2006.168.08:09:48.17#ibcon#read 5, iclass 31, count 0 2006.168.08:09:48.17#ibcon#about to read 6, iclass 31, count 0 2006.168.08:09:48.17#ibcon#read 6, iclass 31, count 0 2006.168.08:09:48.17#ibcon#end of sib2, iclass 31, count 0 2006.168.08:09:48.17#ibcon#*mode == 0, iclass 31, count 0 2006.168.08:09:48.17#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.168.08:09:48.17#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.08:09:48.17#ibcon#*before write, iclass 31, count 0 2006.168.08:09:48.17#ibcon#enter sib2, iclass 31, count 0 2006.168.08:09:48.17#ibcon#flushed, iclass 31, count 0 2006.168.08:09:48.17#ibcon#about to write, iclass 31, count 0 2006.168.08:09:48.17#ibcon#wrote, iclass 31, count 0 2006.168.08:09:48.17#ibcon#about to read 3, iclass 31, count 0 2006.168.08:09:48.21#ibcon#read 3, iclass 31, count 0 2006.168.08:09:48.21#ibcon#about to read 4, iclass 31, count 0 2006.168.08:09:48.21#ibcon#read 4, iclass 31, count 0 2006.168.08:09:48.21#ibcon#about to read 5, iclass 31, count 0 2006.168.08:09:48.21#ibcon#read 5, iclass 31, count 0 2006.168.08:09:48.21#ibcon#about to read 6, iclass 31, count 0 2006.168.08:09:48.21#ibcon#read 6, iclass 31, count 0 2006.168.08:09:48.21#ibcon#end of sib2, iclass 31, count 0 2006.168.08:09:48.21#ibcon#*after write, iclass 31, count 0 2006.168.08:09:48.21#ibcon#*before return 0, iclass 31, count 0 2006.168.08:09:48.21#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:09:48.21#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:09:48.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.168.08:09:48.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.168.08:09:48.21$vc4f8/va=2,7 2006.168.08:09:48.21#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.168.08:09:48.21#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.168.08:09:48.21#ibcon#ireg 11 cls_cnt 2 2006.168.08:09:48.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.168.08:09:48.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.168.08:09:48.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.168.08:09:48.27#ibcon#enter wrdev, iclass 33, count 2 2006.168.08:09:48.27#ibcon#first serial, iclass 33, count 2 2006.168.08:09:48.27#ibcon#enter sib2, iclass 33, count 2 2006.168.08:09:48.27#ibcon#flushed, iclass 33, count 2 2006.168.08:09:48.27#ibcon#about to write, iclass 33, count 2 2006.168.08:09:48.27#ibcon#wrote, iclass 33, count 2 2006.168.08:09:48.27#ibcon#about to read 3, iclass 33, count 2 2006.168.08:09:48.30#ibcon#read 3, iclass 33, count 2 2006.168.08:09:48.30#ibcon#about to read 4, iclass 33, count 2 2006.168.08:09:48.30#ibcon#read 4, iclass 33, count 2 2006.168.08:09:48.30#ibcon#about to read 5, iclass 33, count 2 2006.168.08:09:48.30#ibcon#read 5, iclass 33, count 2 2006.168.08:09:48.30#ibcon#about to read 6, iclass 33, count 2 2006.168.08:09:48.30#ibcon#read 6, iclass 33, count 2 2006.168.08:09:48.30#ibcon#end of sib2, iclass 33, count 2 2006.168.08:09:48.30#ibcon#*mode == 0, iclass 33, count 2 2006.168.08:09:48.30#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.168.08:09:48.30#ibcon#[25=AT02-07\r\n] 2006.168.08:09:48.30#ibcon#*before write, iclass 33, count 2 2006.168.08:09:48.30#ibcon#enter sib2, iclass 33, count 2 2006.168.08:09:48.30#ibcon#flushed, iclass 33, count 2 2006.168.08:09:48.30#ibcon#about to write, iclass 33, count 2 2006.168.08:09:48.30#ibcon#wrote, iclass 33, count 2 2006.168.08:09:48.30#ibcon#about to read 3, iclass 33, count 2 2006.168.08:09:48.33#ibcon#read 3, iclass 33, count 2 2006.168.08:09:48.33#ibcon#about to read 4, iclass 33, count 2 2006.168.08:09:48.33#ibcon#read 4, iclass 33, count 2 2006.168.08:09:48.33#ibcon#about to read 5, iclass 33, count 2 2006.168.08:09:48.33#ibcon#read 5, iclass 33, count 2 2006.168.08:09:48.33#ibcon#about to read 6, iclass 33, count 2 2006.168.08:09:48.33#ibcon#read 6, iclass 33, count 2 2006.168.08:09:48.33#ibcon#end of sib2, iclass 33, count 2 2006.168.08:09:48.33#ibcon#*after write, iclass 33, count 2 2006.168.08:09:48.33#ibcon#*before return 0, iclass 33, count 2 2006.168.08:09:48.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.168.08:09:48.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.168.08:09:48.33#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.168.08:09:48.33#ibcon#ireg 7 cls_cnt 0 2006.168.08:09:48.33#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.168.08:09:48.45#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.168.08:09:48.45#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.168.08:09:48.45#ibcon#enter wrdev, iclass 33, count 0 2006.168.08:09:48.45#ibcon#first serial, iclass 33, count 0 2006.168.08:09:48.45#ibcon#enter sib2, iclass 33, count 0 2006.168.08:09:48.45#ibcon#flushed, iclass 33, count 0 2006.168.08:09:48.45#ibcon#about to write, iclass 33, count 0 2006.168.08:09:48.45#ibcon#wrote, iclass 33, count 0 2006.168.08:09:48.45#ibcon#about to read 3, iclass 33, count 0 2006.168.08:09:48.47#ibcon#read 3, iclass 33, count 0 2006.168.08:09:48.47#ibcon#about to read 4, iclass 33, count 0 2006.168.08:09:48.47#ibcon#read 4, iclass 33, count 0 2006.168.08:09:48.47#ibcon#about to read 5, iclass 33, count 0 2006.168.08:09:48.47#ibcon#read 5, iclass 33, count 0 2006.168.08:09:48.47#ibcon#about to read 6, iclass 33, count 0 2006.168.08:09:48.47#ibcon#read 6, iclass 33, count 0 2006.168.08:09:48.47#ibcon#end of sib2, iclass 33, count 0 2006.168.08:09:48.47#ibcon#*mode == 0, iclass 33, count 0 2006.168.08:09:48.47#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.168.08:09:48.47#ibcon#[25=USB\r\n] 2006.168.08:09:48.47#ibcon#*before write, iclass 33, count 0 2006.168.08:09:48.47#ibcon#enter sib2, iclass 33, count 0 2006.168.08:09:48.47#ibcon#flushed, iclass 33, count 0 2006.168.08:09:48.47#ibcon#about to write, iclass 33, count 0 2006.168.08:09:48.47#ibcon#wrote, iclass 33, count 0 2006.168.08:09:48.47#ibcon#about to read 3, iclass 33, count 0 2006.168.08:09:48.50#ibcon#read 3, iclass 33, count 0 2006.168.08:09:48.50#ibcon#about to read 4, iclass 33, count 0 2006.168.08:09:48.50#ibcon#read 4, iclass 33, count 0 2006.168.08:09:48.50#ibcon#about to read 5, iclass 33, count 0 2006.168.08:09:48.50#ibcon#read 5, iclass 33, count 0 2006.168.08:09:48.50#ibcon#about to read 6, iclass 33, count 0 2006.168.08:09:48.50#ibcon#read 6, iclass 33, count 0 2006.168.08:09:48.50#ibcon#end of sib2, iclass 33, count 0 2006.168.08:09:48.50#ibcon#*after write, iclass 33, count 0 2006.168.08:09:48.50#ibcon#*before return 0, iclass 33, count 0 2006.168.08:09:48.50#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.168.08:09:48.50#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.168.08:09:48.50#ibcon#about to clear, iclass 33 cls_cnt 0 2006.168.08:09:48.50#ibcon#cleared, iclass 33 cls_cnt 0 2006.168.08:09:48.50$vc4f8/valo=3,672.99 2006.168.08:09:48.50#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.168.08:09:48.50#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.168.08:09:48.50#ibcon#ireg 17 cls_cnt 0 2006.168.08:09:48.50#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.168.08:09:48.50#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.168.08:09:48.50#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.168.08:09:48.50#ibcon#enter wrdev, iclass 35, count 0 2006.168.08:09:48.50#ibcon#first serial, iclass 35, count 0 2006.168.08:09:48.50#ibcon#enter sib2, iclass 35, count 0 2006.168.08:09:48.50#ibcon#flushed, iclass 35, count 0 2006.168.08:09:48.50#ibcon#about to write, iclass 35, count 0 2006.168.08:09:48.50#ibcon#wrote, iclass 35, count 0 2006.168.08:09:48.50#ibcon#about to read 3, iclass 35, count 0 2006.168.08:09:48.52#ibcon#read 3, iclass 35, count 0 2006.168.08:09:48.52#ibcon#about to read 4, iclass 35, count 0 2006.168.08:09:48.52#ibcon#read 4, iclass 35, count 0 2006.168.08:09:48.52#ibcon#about to read 5, iclass 35, count 0 2006.168.08:09:48.52#ibcon#read 5, iclass 35, count 0 2006.168.08:09:48.52#ibcon#about to read 6, iclass 35, count 0 2006.168.08:09:48.52#ibcon#read 6, iclass 35, count 0 2006.168.08:09:48.52#ibcon#end of sib2, iclass 35, count 0 2006.168.08:09:48.52#ibcon#*mode == 0, iclass 35, count 0 2006.168.08:09:48.52#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.168.08:09:48.52#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.08:09:48.52#ibcon#*before write, iclass 35, count 0 2006.168.08:09:48.52#ibcon#enter sib2, iclass 35, count 0 2006.168.08:09:48.52#ibcon#flushed, iclass 35, count 0 2006.168.08:09:48.52#ibcon#about to write, iclass 35, count 0 2006.168.08:09:48.52#ibcon#wrote, iclass 35, count 0 2006.168.08:09:48.52#ibcon#about to read 3, iclass 35, count 0 2006.168.08:09:48.56#ibcon#read 3, iclass 35, count 0 2006.168.08:09:48.56#ibcon#about to read 4, iclass 35, count 0 2006.168.08:09:48.56#ibcon#read 4, iclass 35, count 0 2006.168.08:09:48.56#ibcon#about to read 5, iclass 35, count 0 2006.168.08:09:48.56#ibcon#read 5, iclass 35, count 0 2006.168.08:09:48.56#ibcon#about to read 6, iclass 35, count 0 2006.168.08:09:48.56#ibcon#read 6, iclass 35, count 0 2006.168.08:09:48.56#ibcon#end of sib2, iclass 35, count 0 2006.168.08:09:48.56#ibcon#*after write, iclass 35, count 0 2006.168.08:09:48.56#ibcon#*before return 0, iclass 35, count 0 2006.168.08:09:48.56#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.168.08:09:48.56#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.168.08:09:48.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.168.08:09:48.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.168.08:09:48.56$vc4f8/va=3,6 2006.168.08:09:48.56#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.168.08:09:48.56#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.168.08:09:48.56#ibcon#ireg 11 cls_cnt 2 2006.168.08:09:48.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.168.08:09:48.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.168.08:09:48.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.168.08:09:48.62#ibcon#enter wrdev, iclass 37, count 2 2006.168.08:09:48.62#ibcon#first serial, iclass 37, count 2 2006.168.08:09:48.62#ibcon#enter sib2, iclass 37, count 2 2006.168.08:09:48.62#ibcon#flushed, iclass 37, count 2 2006.168.08:09:48.62#ibcon#about to write, iclass 37, count 2 2006.168.08:09:48.62#ibcon#wrote, iclass 37, count 2 2006.168.08:09:48.62#ibcon#about to read 3, iclass 37, count 2 2006.168.08:09:48.64#ibcon#read 3, iclass 37, count 2 2006.168.08:09:48.64#ibcon#about to read 4, iclass 37, count 2 2006.168.08:09:48.64#ibcon#read 4, iclass 37, count 2 2006.168.08:09:48.64#ibcon#about to read 5, iclass 37, count 2 2006.168.08:09:48.64#ibcon#read 5, iclass 37, count 2 2006.168.08:09:48.64#ibcon#about to read 6, iclass 37, count 2 2006.168.08:09:48.64#ibcon#read 6, iclass 37, count 2 2006.168.08:09:48.64#ibcon#end of sib2, iclass 37, count 2 2006.168.08:09:48.64#ibcon#*mode == 0, iclass 37, count 2 2006.168.08:09:48.64#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.168.08:09:48.64#ibcon#[25=AT03-06\r\n] 2006.168.08:09:48.64#ibcon#*before write, iclass 37, count 2 2006.168.08:09:48.64#ibcon#enter sib2, iclass 37, count 2 2006.168.08:09:48.64#ibcon#flushed, iclass 37, count 2 2006.168.08:09:48.64#ibcon#about to write, iclass 37, count 2 2006.168.08:09:48.64#ibcon#wrote, iclass 37, count 2 2006.168.08:09:48.64#ibcon#about to read 3, iclass 37, count 2 2006.168.08:09:48.67#ibcon#read 3, iclass 37, count 2 2006.168.08:09:48.67#ibcon#about to read 4, iclass 37, count 2 2006.168.08:09:48.67#ibcon#read 4, iclass 37, count 2 2006.168.08:09:48.67#ibcon#about to read 5, iclass 37, count 2 2006.168.08:09:48.67#ibcon#read 5, iclass 37, count 2 2006.168.08:09:48.67#ibcon#about to read 6, iclass 37, count 2 2006.168.08:09:48.67#ibcon#read 6, iclass 37, count 2 2006.168.08:09:48.67#ibcon#end of sib2, iclass 37, count 2 2006.168.08:09:48.67#ibcon#*after write, iclass 37, count 2 2006.168.08:09:48.67#ibcon#*before return 0, iclass 37, count 2 2006.168.08:09:48.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.168.08:09:48.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.168.08:09:48.67#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.168.08:09:48.67#ibcon#ireg 7 cls_cnt 0 2006.168.08:09:48.67#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.168.08:09:48.73#abcon#<5=/08 1.6 3.8 26.96 751004.5\r\n> 2006.168.08:09:48.75#abcon#{5=INTERFACE CLEAR} 2006.168.08:09:48.79#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.168.08:09:48.79#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.168.08:09:48.79#ibcon#enter wrdev, iclass 37, count 0 2006.168.08:09:48.79#ibcon#first serial, iclass 37, count 0 2006.168.08:09:48.79#ibcon#enter sib2, iclass 37, count 0 2006.168.08:09:48.79#ibcon#flushed, iclass 37, count 0 2006.168.08:09:48.79#ibcon#about to write, iclass 37, count 0 2006.168.08:09:48.79#ibcon#wrote, iclass 37, count 0 2006.168.08:09:48.79#ibcon#about to read 3, iclass 37, count 0 2006.168.08:09:48.81#ibcon#read 3, iclass 37, count 0 2006.168.08:09:48.81#ibcon#about to read 4, iclass 37, count 0 2006.168.08:09:48.81#ibcon#read 4, iclass 37, count 0 2006.168.08:09:48.81#ibcon#about to read 5, iclass 37, count 0 2006.168.08:09:48.81#ibcon#read 5, iclass 37, count 0 2006.168.08:09:48.81#ibcon#about to read 6, iclass 37, count 0 2006.168.08:09:48.81#ibcon#read 6, iclass 37, count 0 2006.168.08:09:48.81#ibcon#end of sib2, iclass 37, count 0 2006.168.08:09:48.81#ibcon#*mode == 0, iclass 37, count 0 2006.168.08:09:48.81#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.168.08:09:48.81#ibcon#[25=USB\r\n] 2006.168.08:09:48.81#ibcon#*before write, iclass 37, count 0 2006.168.08:09:48.81#ibcon#enter sib2, iclass 37, count 0 2006.168.08:09:48.81#ibcon#flushed, iclass 37, count 0 2006.168.08:09:48.81#ibcon#about to write, iclass 37, count 0 2006.168.08:09:48.81#ibcon#wrote, iclass 37, count 0 2006.168.08:09:48.81#ibcon#about to read 3, iclass 37, count 0 2006.168.08:09:48.81#abcon#[5=S1D000X0/0*\r\n] 2006.168.08:09:48.84#ibcon#read 3, iclass 37, count 0 2006.168.08:09:48.84#ibcon#about to read 4, iclass 37, count 0 2006.168.08:09:48.84#ibcon#read 4, iclass 37, count 0 2006.168.08:09:48.84#ibcon#about to read 5, iclass 37, count 0 2006.168.08:09:48.84#ibcon#read 5, iclass 37, count 0 2006.168.08:09:48.84#ibcon#about to read 6, iclass 37, count 0 2006.168.08:09:48.84#ibcon#read 6, iclass 37, count 0 2006.168.08:09:48.84#ibcon#end of sib2, iclass 37, count 0 2006.168.08:09:48.84#ibcon#*after write, iclass 37, count 0 2006.168.08:09:48.84#ibcon#*before return 0, iclass 37, count 0 2006.168.08:09:48.84#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.168.08:09:48.84#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.168.08:09:48.84#ibcon#about to clear, iclass 37 cls_cnt 0 2006.168.08:09:48.84#ibcon#cleared, iclass 37 cls_cnt 0 2006.168.08:09:48.84$vc4f8/valo=4,832.99 2006.168.08:09:48.84#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.168.08:09:48.84#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.168.08:09:48.84#ibcon#ireg 17 cls_cnt 0 2006.168.08:09:48.84#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.168.08:09:48.84#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.168.08:09:48.84#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.168.08:09:48.84#ibcon#enter wrdev, iclass 5, count 0 2006.168.08:09:48.84#ibcon#first serial, iclass 5, count 0 2006.168.08:09:48.84#ibcon#enter sib2, iclass 5, count 0 2006.168.08:09:48.84#ibcon#flushed, iclass 5, count 0 2006.168.08:09:48.84#ibcon#about to write, iclass 5, count 0 2006.168.08:09:48.84#ibcon#wrote, iclass 5, count 0 2006.168.08:09:48.84#ibcon#about to read 3, iclass 5, count 0 2006.168.08:09:48.86#ibcon#read 3, iclass 5, count 0 2006.168.08:09:48.86#ibcon#about to read 4, iclass 5, count 0 2006.168.08:09:48.86#ibcon#read 4, iclass 5, count 0 2006.168.08:09:48.86#ibcon#about to read 5, iclass 5, count 0 2006.168.08:09:48.86#ibcon#read 5, iclass 5, count 0 2006.168.08:09:48.86#ibcon#about to read 6, iclass 5, count 0 2006.168.08:09:48.86#ibcon#read 6, iclass 5, count 0 2006.168.08:09:48.86#ibcon#end of sib2, iclass 5, count 0 2006.168.08:09:48.86#ibcon#*mode == 0, iclass 5, count 0 2006.168.08:09:48.86#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.168.08:09:48.86#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.08:09:48.86#ibcon#*before write, iclass 5, count 0 2006.168.08:09:48.86#ibcon#enter sib2, iclass 5, count 0 2006.168.08:09:48.86#ibcon#flushed, iclass 5, count 0 2006.168.08:09:48.86#ibcon#about to write, iclass 5, count 0 2006.168.08:09:48.86#ibcon#wrote, iclass 5, count 0 2006.168.08:09:48.86#ibcon#about to read 3, iclass 5, count 0 2006.168.08:09:48.90#ibcon#read 3, iclass 5, count 0 2006.168.08:09:48.90#ibcon#about to read 4, iclass 5, count 0 2006.168.08:09:48.90#ibcon#read 4, iclass 5, count 0 2006.168.08:09:48.90#ibcon#about to read 5, iclass 5, count 0 2006.168.08:09:48.90#ibcon#read 5, iclass 5, count 0 2006.168.08:09:48.90#ibcon#about to read 6, iclass 5, count 0 2006.168.08:09:48.90#ibcon#read 6, iclass 5, count 0 2006.168.08:09:48.90#ibcon#end of sib2, iclass 5, count 0 2006.168.08:09:48.90#ibcon#*after write, iclass 5, count 0 2006.168.08:09:48.90#ibcon#*before return 0, iclass 5, count 0 2006.168.08:09:48.90#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.168.08:09:48.90#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.168.08:09:48.90#ibcon#about to clear, iclass 5 cls_cnt 0 2006.168.08:09:48.90#ibcon#cleared, iclass 5 cls_cnt 0 2006.168.08:09:48.90$vc4f8/va=4,7 2006.168.08:09:48.90#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.168.08:09:48.90#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.168.08:09:48.90#ibcon#ireg 11 cls_cnt 2 2006.168.08:09:48.90#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.168.08:09:48.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.168.08:09:48.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.168.08:09:48.96#ibcon#enter wrdev, iclass 7, count 2 2006.168.08:09:48.96#ibcon#first serial, iclass 7, count 2 2006.168.08:09:48.96#ibcon#enter sib2, iclass 7, count 2 2006.168.08:09:48.96#ibcon#flushed, iclass 7, count 2 2006.168.08:09:48.96#ibcon#about to write, iclass 7, count 2 2006.168.08:09:48.96#ibcon#wrote, iclass 7, count 2 2006.168.08:09:48.96#ibcon#about to read 3, iclass 7, count 2 2006.168.08:09:48.98#ibcon#read 3, iclass 7, count 2 2006.168.08:09:48.98#ibcon#about to read 4, iclass 7, count 2 2006.168.08:09:48.98#ibcon#read 4, iclass 7, count 2 2006.168.08:09:48.98#ibcon#about to read 5, iclass 7, count 2 2006.168.08:09:48.98#ibcon#read 5, iclass 7, count 2 2006.168.08:09:48.98#ibcon#about to read 6, iclass 7, count 2 2006.168.08:09:48.98#ibcon#read 6, iclass 7, count 2 2006.168.08:09:48.98#ibcon#end of sib2, iclass 7, count 2 2006.168.08:09:48.98#ibcon#*mode == 0, iclass 7, count 2 2006.168.08:09:48.98#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.168.08:09:48.98#ibcon#[25=AT04-07\r\n] 2006.168.08:09:48.98#ibcon#*before write, iclass 7, count 2 2006.168.08:09:48.98#ibcon#enter sib2, iclass 7, count 2 2006.168.08:09:48.98#ibcon#flushed, iclass 7, count 2 2006.168.08:09:48.98#ibcon#about to write, iclass 7, count 2 2006.168.08:09:48.98#ibcon#wrote, iclass 7, count 2 2006.168.08:09:48.98#ibcon#about to read 3, iclass 7, count 2 2006.168.08:09:49.01#ibcon#read 3, iclass 7, count 2 2006.168.08:09:49.01#ibcon#about to read 4, iclass 7, count 2 2006.168.08:09:49.01#ibcon#read 4, iclass 7, count 2 2006.168.08:09:49.01#ibcon#about to read 5, iclass 7, count 2 2006.168.08:09:49.01#ibcon#read 5, iclass 7, count 2 2006.168.08:09:49.01#ibcon#about to read 6, iclass 7, count 2 2006.168.08:09:49.01#ibcon#read 6, iclass 7, count 2 2006.168.08:09:49.01#ibcon#end of sib2, iclass 7, count 2 2006.168.08:09:49.01#ibcon#*after write, iclass 7, count 2 2006.168.08:09:49.01#ibcon#*before return 0, iclass 7, count 2 2006.168.08:09:49.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.168.08:09:49.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.168.08:09:49.01#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.168.08:09:49.01#ibcon#ireg 7 cls_cnt 0 2006.168.08:09:49.01#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.168.08:09:49.13#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.168.08:09:49.13#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.168.08:09:49.13#ibcon#enter wrdev, iclass 7, count 0 2006.168.08:09:49.13#ibcon#first serial, iclass 7, count 0 2006.168.08:09:49.13#ibcon#enter sib2, iclass 7, count 0 2006.168.08:09:49.13#ibcon#flushed, iclass 7, count 0 2006.168.08:09:49.13#ibcon#about to write, iclass 7, count 0 2006.168.08:09:49.13#ibcon#wrote, iclass 7, count 0 2006.168.08:09:49.13#ibcon#about to read 3, iclass 7, count 0 2006.168.08:09:49.15#ibcon#read 3, iclass 7, count 0 2006.168.08:09:49.15#ibcon#about to read 4, iclass 7, count 0 2006.168.08:09:49.15#ibcon#read 4, iclass 7, count 0 2006.168.08:09:49.15#ibcon#about to read 5, iclass 7, count 0 2006.168.08:09:49.15#ibcon#read 5, iclass 7, count 0 2006.168.08:09:49.15#ibcon#about to read 6, iclass 7, count 0 2006.168.08:09:49.15#ibcon#read 6, iclass 7, count 0 2006.168.08:09:49.15#ibcon#end of sib2, iclass 7, count 0 2006.168.08:09:49.15#ibcon#*mode == 0, iclass 7, count 0 2006.168.08:09:49.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.168.08:09:49.15#ibcon#[25=USB\r\n] 2006.168.08:09:49.15#ibcon#*before write, iclass 7, count 0 2006.168.08:09:49.15#ibcon#enter sib2, iclass 7, count 0 2006.168.08:09:49.15#ibcon#flushed, iclass 7, count 0 2006.168.08:09:49.15#ibcon#about to write, iclass 7, count 0 2006.168.08:09:49.15#ibcon#wrote, iclass 7, count 0 2006.168.08:09:49.15#ibcon#about to read 3, iclass 7, count 0 2006.168.08:09:49.18#ibcon#read 3, iclass 7, count 0 2006.168.08:09:49.18#ibcon#about to read 4, iclass 7, count 0 2006.168.08:09:49.18#ibcon#read 4, iclass 7, count 0 2006.168.08:09:49.18#ibcon#about to read 5, iclass 7, count 0 2006.168.08:09:49.18#ibcon#read 5, iclass 7, count 0 2006.168.08:09:49.18#ibcon#about to read 6, iclass 7, count 0 2006.168.08:09:49.18#ibcon#read 6, iclass 7, count 0 2006.168.08:09:49.18#ibcon#end of sib2, iclass 7, count 0 2006.168.08:09:49.18#ibcon#*after write, iclass 7, count 0 2006.168.08:09:49.18#ibcon#*before return 0, iclass 7, count 0 2006.168.08:09:49.18#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.168.08:09:49.18#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.168.08:09:49.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.168.08:09:49.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.168.08:09:49.18$vc4f8/valo=5,652.99 2006.168.08:09:49.18#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.168.08:09:49.18#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.168.08:09:49.18#ibcon#ireg 17 cls_cnt 0 2006.168.08:09:49.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.168.08:09:49.18#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.168.08:09:49.18#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.168.08:09:49.18#ibcon#enter wrdev, iclass 11, count 0 2006.168.08:09:49.18#ibcon#first serial, iclass 11, count 0 2006.168.08:09:49.18#ibcon#enter sib2, iclass 11, count 0 2006.168.08:09:49.18#ibcon#flushed, iclass 11, count 0 2006.168.08:09:49.18#ibcon#about to write, iclass 11, count 0 2006.168.08:09:49.18#ibcon#wrote, iclass 11, count 0 2006.168.08:09:49.18#ibcon#about to read 3, iclass 11, count 0 2006.168.08:09:49.20#ibcon#read 3, iclass 11, count 0 2006.168.08:09:49.20#ibcon#about to read 4, iclass 11, count 0 2006.168.08:09:49.20#ibcon#read 4, iclass 11, count 0 2006.168.08:09:49.20#ibcon#about to read 5, iclass 11, count 0 2006.168.08:09:49.20#ibcon#read 5, iclass 11, count 0 2006.168.08:09:49.20#ibcon#about to read 6, iclass 11, count 0 2006.168.08:09:49.20#ibcon#read 6, iclass 11, count 0 2006.168.08:09:49.20#ibcon#end of sib2, iclass 11, count 0 2006.168.08:09:49.20#ibcon#*mode == 0, iclass 11, count 0 2006.168.08:09:49.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.168.08:09:49.20#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.08:09:49.20#ibcon#*before write, iclass 11, count 0 2006.168.08:09:49.20#ibcon#enter sib2, iclass 11, count 0 2006.168.08:09:49.20#ibcon#flushed, iclass 11, count 0 2006.168.08:09:49.20#ibcon#about to write, iclass 11, count 0 2006.168.08:09:49.20#ibcon#wrote, iclass 11, count 0 2006.168.08:09:49.20#ibcon#about to read 3, iclass 11, count 0 2006.168.08:09:49.24#ibcon#read 3, iclass 11, count 0 2006.168.08:09:49.24#ibcon#about to read 4, iclass 11, count 0 2006.168.08:09:49.24#ibcon#read 4, iclass 11, count 0 2006.168.08:09:49.24#ibcon#about to read 5, iclass 11, count 0 2006.168.08:09:49.24#ibcon#read 5, iclass 11, count 0 2006.168.08:09:49.24#ibcon#about to read 6, iclass 11, count 0 2006.168.08:09:49.24#ibcon#read 6, iclass 11, count 0 2006.168.08:09:49.24#ibcon#end of sib2, iclass 11, count 0 2006.168.08:09:49.24#ibcon#*after write, iclass 11, count 0 2006.168.08:09:49.24#ibcon#*before return 0, iclass 11, count 0 2006.168.08:09:49.24#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.168.08:09:49.24#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.168.08:09:49.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.168.08:09:49.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.168.08:09:49.24$vc4f8/va=5,7 2006.168.08:09:49.24#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.168.08:09:49.24#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.168.08:09:49.24#ibcon#ireg 11 cls_cnt 2 2006.168.08:09:49.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.168.08:09:49.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.168.08:09:49.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.168.08:09:49.30#ibcon#enter wrdev, iclass 13, count 2 2006.168.08:09:49.30#ibcon#first serial, iclass 13, count 2 2006.168.08:09:49.30#ibcon#enter sib2, iclass 13, count 2 2006.168.08:09:49.30#ibcon#flushed, iclass 13, count 2 2006.168.08:09:49.30#ibcon#about to write, iclass 13, count 2 2006.168.08:09:49.30#ibcon#wrote, iclass 13, count 2 2006.168.08:09:49.30#ibcon#about to read 3, iclass 13, count 2 2006.168.08:09:49.32#ibcon#read 3, iclass 13, count 2 2006.168.08:09:49.32#ibcon#about to read 4, iclass 13, count 2 2006.168.08:09:49.32#ibcon#read 4, iclass 13, count 2 2006.168.08:09:49.32#ibcon#about to read 5, iclass 13, count 2 2006.168.08:09:49.32#ibcon#read 5, iclass 13, count 2 2006.168.08:09:49.32#ibcon#about to read 6, iclass 13, count 2 2006.168.08:09:49.32#ibcon#read 6, iclass 13, count 2 2006.168.08:09:49.32#ibcon#end of sib2, iclass 13, count 2 2006.168.08:09:49.32#ibcon#*mode == 0, iclass 13, count 2 2006.168.08:09:49.32#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.168.08:09:49.32#ibcon#[25=AT05-07\r\n] 2006.168.08:09:49.32#ibcon#*before write, iclass 13, count 2 2006.168.08:09:49.32#ibcon#enter sib2, iclass 13, count 2 2006.168.08:09:49.32#ibcon#flushed, iclass 13, count 2 2006.168.08:09:49.32#ibcon#about to write, iclass 13, count 2 2006.168.08:09:49.32#ibcon#wrote, iclass 13, count 2 2006.168.08:09:49.32#ibcon#about to read 3, iclass 13, count 2 2006.168.08:09:49.35#ibcon#read 3, iclass 13, count 2 2006.168.08:09:49.35#ibcon#about to read 4, iclass 13, count 2 2006.168.08:09:49.35#ibcon#read 4, iclass 13, count 2 2006.168.08:09:49.35#ibcon#about to read 5, iclass 13, count 2 2006.168.08:09:49.35#ibcon#read 5, iclass 13, count 2 2006.168.08:09:49.35#ibcon#about to read 6, iclass 13, count 2 2006.168.08:09:49.35#ibcon#read 6, iclass 13, count 2 2006.168.08:09:49.35#ibcon#end of sib2, iclass 13, count 2 2006.168.08:09:49.35#ibcon#*after write, iclass 13, count 2 2006.168.08:09:49.35#ibcon#*before return 0, iclass 13, count 2 2006.168.08:09:49.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.168.08:09:49.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.168.08:09:49.35#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.168.08:09:49.35#ibcon#ireg 7 cls_cnt 0 2006.168.08:09:49.35#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.168.08:09:49.47#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.168.08:09:49.47#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.168.08:09:49.47#ibcon#enter wrdev, iclass 13, count 0 2006.168.08:09:49.47#ibcon#first serial, iclass 13, count 0 2006.168.08:09:49.47#ibcon#enter sib2, iclass 13, count 0 2006.168.08:09:49.47#ibcon#flushed, iclass 13, count 0 2006.168.08:09:49.47#ibcon#about to write, iclass 13, count 0 2006.168.08:09:49.47#ibcon#wrote, iclass 13, count 0 2006.168.08:09:49.47#ibcon#about to read 3, iclass 13, count 0 2006.168.08:09:49.49#ibcon#read 3, iclass 13, count 0 2006.168.08:09:49.49#ibcon#about to read 4, iclass 13, count 0 2006.168.08:09:49.49#ibcon#read 4, iclass 13, count 0 2006.168.08:09:49.49#ibcon#about to read 5, iclass 13, count 0 2006.168.08:09:49.49#ibcon#read 5, iclass 13, count 0 2006.168.08:09:49.49#ibcon#about to read 6, iclass 13, count 0 2006.168.08:09:49.49#ibcon#read 6, iclass 13, count 0 2006.168.08:09:49.49#ibcon#end of sib2, iclass 13, count 0 2006.168.08:09:49.49#ibcon#*mode == 0, iclass 13, count 0 2006.168.08:09:49.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.168.08:09:49.49#ibcon#[25=USB\r\n] 2006.168.08:09:49.49#ibcon#*before write, iclass 13, count 0 2006.168.08:09:49.49#ibcon#enter sib2, iclass 13, count 0 2006.168.08:09:49.49#ibcon#flushed, iclass 13, count 0 2006.168.08:09:49.49#ibcon#about to write, iclass 13, count 0 2006.168.08:09:49.49#ibcon#wrote, iclass 13, count 0 2006.168.08:09:49.49#ibcon#about to read 3, iclass 13, count 0 2006.168.08:09:49.52#ibcon#read 3, iclass 13, count 0 2006.168.08:09:49.52#ibcon#about to read 4, iclass 13, count 0 2006.168.08:09:49.52#ibcon#read 4, iclass 13, count 0 2006.168.08:09:49.52#ibcon#about to read 5, iclass 13, count 0 2006.168.08:09:49.52#ibcon#read 5, iclass 13, count 0 2006.168.08:09:49.52#ibcon#about to read 6, iclass 13, count 0 2006.168.08:09:49.52#ibcon#read 6, iclass 13, count 0 2006.168.08:09:49.52#ibcon#end of sib2, iclass 13, count 0 2006.168.08:09:49.52#ibcon#*after write, iclass 13, count 0 2006.168.08:09:49.52#ibcon#*before return 0, iclass 13, count 0 2006.168.08:09:49.52#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.168.08:09:49.52#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.168.08:09:49.52#ibcon#about to clear, iclass 13 cls_cnt 0 2006.168.08:09:49.52#ibcon#cleared, iclass 13 cls_cnt 0 2006.168.08:09:49.52$vc4f8/valo=6,772.99 2006.168.08:09:49.52#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.168.08:09:49.52#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.168.08:09:49.52#ibcon#ireg 17 cls_cnt 0 2006.168.08:09:49.52#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:09:49.52#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:09:49.52#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:09:49.52#ibcon#enter wrdev, iclass 15, count 0 2006.168.08:09:49.52#ibcon#first serial, iclass 15, count 0 2006.168.08:09:49.52#ibcon#enter sib2, iclass 15, count 0 2006.168.08:09:49.52#ibcon#flushed, iclass 15, count 0 2006.168.08:09:49.52#ibcon#about to write, iclass 15, count 0 2006.168.08:09:49.52#ibcon#wrote, iclass 15, count 0 2006.168.08:09:49.52#ibcon#about to read 3, iclass 15, count 0 2006.168.08:09:49.54#ibcon#read 3, iclass 15, count 0 2006.168.08:09:49.54#ibcon#about to read 4, iclass 15, count 0 2006.168.08:09:49.54#ibcon#read 4, iclass 15, count 0 2006.168.08:09:49.54#ibcon#about to read 5, iclass 15, count 0 2006.168.08:09:49.54#ibcon#read 5, iclass 15, count 0 2006.168.08:09:49.54#ibcon#about to read 6, iclass 15, count 0 2006.168.08:09:49.54#ibcon#read 6, iclass 15, count 0 2006.168.08:09:49.54#ibcon#end of sib2, iclass 15, count 0 2006.168.08:09:49.54#ibcon#*mode == 0, iclass 15, count 0 2006.168.08:09:49.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.168.08:09:49.54#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.08:09:49.54#ibcon#*before write, iclass 15, count 0 2006.168.08:09:49.54#ibcon#enter sib2, iclass 15, count 0 2006.168.08:09:49.54#ibcon#flushed, iclass 15, count 0 2006.168.08:09:49.54#ibcon#about to write, iclass 15, count 0 2006.168.08:09:49.54#ibcon#wrote, iclass 15, count 0 2006.168.08:09:49.54#ibcon#about to read 3, iclass 15, count 0 2006.168.08:09:49.58#ibcon#read 3, iclass 15, count 0 2006.168.08:09:49.58#ibcon#about to read 4, iclass 15, count 0 2006.168.08:09:49.58#ibcon#read 4, iclass 15, count 0 2006.168.08:09:49.58#ibcon#about to read 5, iclass 15, count 0 2006.168.08:09:49.58#ibcon#read 5, iclass 15, count 0 2006.168.08:09:49.58#ibcon#about to read 6, iclass 15, count 0 2006.168.08:09:49.58#ibcon#read 6, iclass 15, count 0 2006.168.08:09:49.58#ibcon#end of sib2, iclass 15, count 0 2006.168.08:09:49.58#ibcon#*after write, iclass 15, count 0 2006.168.08:09:49.58#ibcon#*before return 0, iclass 15, count 0 2006.168.08:09:49.58#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:09:49.58#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:09:49.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.168.08:09:49.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.168.08:09:49.58$vc4f8/va=6,6 2006.168.08:09:49.58#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.168.08:09:49.58#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.168.08:09:49.58#ibcon#ireg 11 cls_cnt 2 2006.168.08:09:49.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.168.08:09:49.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.168.08:09:49.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.168.08:09:49.64#ibcon#enter wrdev, iclass 17, count 2 2006.168.08:09:49.64#ibcon#first serial, iclass 17, count 2 2006.168.08:09:49.64#ibcon#enter sib2, iclass 17, count 2 2006.168.08:09:49.64#ibcon#flushed, iclass 17, count 2 2006.168.08:09:49.64#ibcon#about to write, iclass 17, count 2 2006.168.08:09:49.64#ibcon#wrote, iclass 17, count 2 2006.168.08:09:49.64#ibcon#about to read 3, iclass 17, count 2 2006.168.08:09:49.66#ibcon#read 3, iclass 17, count 2 2006.168.08:09:49.66#ibcon#about to read 4, iclass 17, count 2 2006.168.08:09:49.66#ibcon#read 4, iclass 17, count 2 2006.168.08:09:49.66#ibcon#about to read 5, iclass 17, count 2 2006.168.08:09:49.66#ibcon#read 5, iclass 17, count 2 2006.168.08:09:49.66#ibcon#about to read 6, iclass 17, count 2 2006.168.08:09:49.66#ibcon#read 6, iclass 17, count 2 2006.168.08:09:49.66#ibcon#end of sib2, iclass 17, count 2 2006.168.08:09:49.66#ibcon#*mode == 0, iclass 17, count 2 2006.168.08:09:49.66#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.168.08:09:49.66#ibcon#[25=AT06-06\r\n] 2006.168.08:09:49.66#ibcon#*before write, iclass 17, count 2 2006.168.08:09:49.66#ibcon#enter sib2, iclass 17, count 2 2006.168.08:09:49.66#ibcon#flushed, iclass 17, count 2 2006.168.08:09:49.66#ibcon#about to write, iclass 17, count 2 2006.168.08:09:49.66#ibcon#wrote, iclass 17, count 2 2006.168.08:09:49.66#ibcon#about to read 3, iclass 17, count 2 2006.168.08:09:49.69#ibcon#read 3, iclass 17, count 2 2006.168.08:09:49.69#ibcon#about to read 4, iclass 17, count 2 2006.168.08:09:49.69#ibcon#read 4, iclass 17, count 2 2006.168.08:09:49.69#ibcon#about to read 5, iclass 17, count 2 2006.168.08:09:49.69#ibcon#read 5, iclass 17, count 2 2006.168.08:09:49.69#ibcon#about to read 6, iclass 17, count 2 2006.168.08:09:49.69#ibcon#read 6, iclass 17, count 2 2006.168.08:09:49.69#ibcon#end of sib2, iclass 17, count 2 2006.168.08:09:49.69#ibcon#*after write, iclass 17, count 2 2006.168.08:09:49.69#ibcon#*before return 0, iclass 17, count 2 2006.168.08:09:49.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.168.08:09:49.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.168.08:09:49.69#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.168.08:09:49.69#ibcon#ireg 7 cls_cnt 0 2006.168.08:09:49.69#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.168.08:09:49.81#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.168.08:09:49.81#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.168.08:09:49.81#ibcon#enter wrdev, iclass 17, count 0 2006.168.08:09:49.81#ibcon#first serial, iclass 17, count 0 2006.168.08:09:49.81#ibcon#enter sib2, iclass 17, count 0 2006.168.08:09:49.81#ibcon#flushed, iclass 17, count 0 2006.168.08:09:49.81#ibcon#about to write, iclass 17, count 0 2006.168.08:09:49.81#ibcon#wrote, iclass 17, count 0 2006.168.08:09:49.81#ibcon#about to read 3, iclass 17, count 0 2006.168.08:09:49.83#ibcon#read 3, iclass 17, count 0 2006.168.08:09:49.83#ibcon#about to read 4, iclass 17, count 0 2006.168.08:09:49.83#ibcon#read 4, iclass 17, count 0 2006.168.08:09:49.83#ibcon#about to read 5, iclass 17, count 0 2006.168.08:09:49.83#ibcon#read 5, iclass 17, count 0 2006.168.08:09:49.83#ibcon#about to read 6, iclass 17, count 0 2006.168.08:09:49.83#ibcon#read 6, iclass 17, count 0 2006.168.08:09:49.83#ibcon#end of sib2, iclass 17, count 0 2006.168.08:09:49.83#ibcon#*mode == 0, iclass 17, count 0 2006.168.08:09:49.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.168.08:09:49.83#ibcon#[25=USB\r\n] 2006.168.08:09:49.83#ibcon#*before write, iclass 17, count 0 2006.168.08:09:49.83#ibcon#enter sib2, iclass 17, count 0 2006.168.08:09:49.83#ibcon#flushed, iclass 17, count 0 2006.168.08:09:49.83#ibcon#about to write, iclass 17, count 0 2006.168.08:09:49.83#ibcon#wrote, iclass 17, count 0 2006.168.08:09:49.83#ibcon#about to read 3, iclass 17, count 0 2006.168.08:09:49.86#ibcon#read 3, iclass 17, count 0 2006.168.08:09:49.86#ibcon#about to read 4, iclass 17, count 0 2006.168.08:09:49.86#ibcon#read 4, iclass 17, count 0 2006.168.08:09:49.86#ibcon#about to read 5, iclass 17, count 0 2006.168.08:09:49.86#ibcon#read 5, iclass 17, count 0 2006.168.08:09:49.86#ibcon#about to read 6, iclass 17, count 0 2006.168.08:09:49.86#ibcon#read 6, iclass 17, count 0 2006.168.08:09:49.86#ibcon#end of sib2, iclass 17, count 0 2006.168.08:09:49.86#ibcon#*after write, iclass 17, count 0 2006.168.08:09:49.86#ibcon#*before return 0, iclass 17, count 0 2006.168.08:09:49.86#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.168.08:09:49.86#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.168.08:09:49.86#ibcon#about to clear, iclass 17 cls_cnt 0 2006.168.08:09:49.86#ibcon#cleared, iclass 17 cls_cnt 0 2006.168.08:09:49.86$vc4f8/valo=7,832.99 2006.168.08:09:49.86#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.168.08:09:49.86#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.168.08:09:49.86#ibcon#ireg 17 cls_cnt 0 2006.168.08:09:49.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.168.08:09:49.86#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.168.08:09:49.86#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.168.08:09:49.86#ibcon#enter wrdev, iclass 19, count 0 2006.168.08:09:49.86#ibcon#first serial, iclass 19, count 0 2006.168.08:09:49.86#ibcon#enter sib2, iclass 19, count 0 2006.168.08:09:49.86#ibcon#flushed, iclass 19, count 0 2006.168.08:09:49.86#ibcon#about to write, iclass 19, count 0 2006.168.08:09:49.86#ibcon#wrote, iclass 19, count 0 2006.168.08:09:49.86#ibcon#about to read 3, iclass 19, count 0 2006.168.08:09:49.88#ibcon#read 3, iclass 19, count 0 2006.168.08:09:49.88#ibcon#about to read 4, iclass 19, count 0 2006.168.08:09:49.88#ibcon#read 4, iclass 19, count 0 2006.168.08:09:49.88#ibcon#about to read 5, iclass 19, count 0 2006.168.08:09:49.88#ibcon#read 5, iclass 19, count 0 2006.168.08:09:49.88#ibcon#about to read 6, iclass 19, count 0 2006.168.08:09:49.88#ibcon#read 6, iclass 19, count 0 2006.168.08:09:49.88#ibcon#end of sib2, iclass 19, count 0 2006.168.08:09:49.88#ibcon#*mode == 0, iclass 19, count 0 2006.168.08:09:49.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.168.08:09:49.88#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.08:09:49.88#ibcon#*before write, iclass 19, count 0 2006.168.08:09:49.88#ibcon#enter sib2, iclass 19, count 0 2006.168.08:09:49.88#ibcon#flushed, iclass 19, count 0 2006.168.08:09:49.88#ibcon#about to write, iclass 19, count 0 2006.168.08:09:49.88#ibcon#wrote, iclass 19, count 0 2006.168.08:09:49.88#ibcon#about to read 3, iclass 19, count 0 2006.168.08:09:49.92#ibcon#read 3, iclass 19, count 0 2006.168.08:09:49.92#ibcon#about to read 4, iclass 19, count 0 2006.168.08:09:49.92#ibcon#read 4, iclass 19, count 0 2006.168.08:09:49.92#ibcon#about to read 5, iclass 19, count 0 2006.168.08:09:49.92#ibcon#read 5, iclass 19, count 0 2006.168.08:09:49.92#ibcon#about to read 6, iclass 19, count 0 2006.168.08:09:49.92#ibcon#read 6, iclass 19, count 0 2006.168.08:09:49.92#ibcon#end of sib2, iclass 19, count 0 2006.168.08:09:49.92#ibcon#*after write, iclass 19, count 0 2006.168.08:09:49.92#ibcon#*before return 0, iclass 19, count 0 2006.168.08:09:49.92#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.168.08:09:49.92#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.168.08:09:49.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.168.08:09:49.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.168.08:09:49.92$vc4f8/va=7,6 2006.168.08:09:49.92#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.168.08:09:49.92#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.168.08:09:49.92#ibcon#ireg 11 cls_cnt 2 2006.168.08:09:49.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.168.08:09:49.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.168.08:09:49.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.168.08:09:49.98#ibcon#enter wrdev, iclass 21, count 2 2006.168.08:09:49.98#ibcon#first serial, iclass 21, count 2 2006.168.08:09:49.98#ibcon#enter sib2, iclass 21, count 2 2006.168.08:09:49.98#ibcon#flushed, iclass 21, count 2 2006.168.08:09:49.98#ibcon#about to write, iclass 21, count 2 2006.168.08:09:49.98#ibcon#wrote, iclass 21, count 2 2006.168.08:09:49.98#ibcon#about to read 3, iclass 21, count 2 2006.168.08:09:50.00#ibcon#read 3, iclass 21, count 2 2006.168.08:09:50.00#ibcon#about to read 4, iclass 21, count 2 2006.168.08:09:50.00#ibcon#read 4, iclass 21, count 2 2006.168.08:09:50.00#ibcon#about to read 5, iclass 21, count 2 2006.168.08:09:50.00#ibcon#read 5, iclass 21, count 2 2006.168.08:09:50.00#ibcon#about to read 6, iclass 21, count 2 2006.168.08:09:50.00#ibcon#read 6, iclass 21, count 2 2006.168.08:09:50.00#ibcon#end of sib2, iclass 21, count 2 2006.168.08:09:50.00#ibcon#*mode == 0, iclass 21, count 2 2006.168.08:09:50.00#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.168.08:09:50.00#ibcon#[25=AT07-06\r\n] 2006.168.08:09:50.00#ibcon#*before write, iclass 21, count 2 2006.168.08:09:50.00#ibcon#enter sib2, iclass 21, count 2 2006.168.08:09:50.00#ibcon#flushed, iclass 21, count 2 2006.168.08:09:50.00#ibcon#about to write, iclass 21, count 2 2006.168.08:09:50.00#ibcon#wrote, iclass 21, count 2 2006.168.08:09:50.00#ibcon#about to read 3, iclass 21, count 2 2006.168.08:09:50.03#ibcon#read 3, iclass 21, count 2 2006.168.08:09:50.03#ibcon#about to read 4, iclass 21, count 2 2006.168.08:09:50.03#ibcon#read 4, iclass 21, count 2 2006.168.08:09:50.03#ibcon#about to read 5, iclass 21, count 2 2006.168.08:09:50.03#ibcon#read 5, iclass 21, count 2 2006.168.08:09:50.03#ibcon#about to read 6, iclass 21, count 2 2006.168.08:09:50.03#ibcon#read 6, iclass 21, count 2 2006.168.08:09:50.03#ibcon#end of sib2, iclass 21, count 2 2006.168.08:09:50.03#ibcon#*after write, iclass 21, count 2 2006.168.08:09:50.03#ibcon#*before return 0, iclass 21, count 2 2006.168.08:09:50.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.168.08:09:50.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.168.08:09:50.03#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.168.08:09:50.03#ibcon#ireg 7 cls_cnt 0 2006.168.08:09:50.03#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.168.08:09:50.15#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.168.08:09:50.15#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.168.08:09:50.15#ibcon#enter wrdev, iclass 21, count 0 2006.168.08:09:50.15#ibcon#first serial, iclass 21, count 0 2006.168.08:09:50.15#ibcon#enter sib2, iclass 21, count 0 2006.168.08:09:50.15#ibcon#flushed, iclass 21, count 0 2006.168.08:09:50.15#ibcon#about to write, iclass 21, count 0 2006.168.08:09:50.15#ibcon#wrote, iclass 21, count 0 2006.168.08:09:50.15#ibcon#about to read 3, iclass 21, count 0 2006.168.08:09:50.17#ibcon#read 3, iclass 21, count 0 2006.168.08:09:50.17#ibcon#about to read 4, iclass 21, count 0 2006.168.08:09:50.17#ibcon#read 4, iclass 21, count 0 2006.168.08:09:50.17#ibcon#about to read 5, iclass 21, count 0 2006.168.08:09:50.17#ibcon#read 5, iclass 21, count 0 2006.168.08:09:50.17#ibcon#about to read 6, iclass 21, count 0 2006.168.08:09:50.17#ibcon#read 6, iclass 21, count 0 2006.168.08:09:50.17#ibcon#end of sib2, iclass 21, count 0 2006.168.08:09:50.17#ibcon#*mode == 0, iclass 21, count 0 2006.168.08:09:50.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.168.08:09:50.17#ibcon#[25=USB\r\n] 2006.168.08:09:50.17#ibcon#*before write, iclass 21, count 0 2006.168.08:09:50.17#ibcon#enter sib2, iclass 21, count 0 2006.168.08:09:50.17#ibcon#flushed, iclass 21, count 0 2006.168.08:09:50.17#ibcon#about to write, iclass 21, count 0 2006.168.08:09:50.17#ibcon#wrote, iclass 21, count 0 2006.168.08:09:50.17#ibcon#about to read 3, iclass 21, count 0 2006.168.08:09:50.21#ibcon#read 3, iclass 21, count 0 2006.168.08:09:50.21#ibcon#about to read 4, iclass 21, count 0 2006.168.08:09:50.21#ibcon#read 4, iclass 21, count 0 2006.168.08:09:50.21#ibcon#about to read 5, iclass 21, count 0 2006.168.08:09:50.21#ibcon#read 5, iclass 21, count 0 2006.168.08:09:50.21#ibcon#about to read 6, iclass 21, count 0 2006.168.08:09:50.21#ibcon#read 6, iclass 21, count 0 2006.168.08:09:50.21#ibcon#end of sib2, iclass 21, count 0 2006.168.08:09:50.21#ibcon#*after write, iclass 21, count 0 2006.168.08:09:50.21#ibcon#*before return 0, iclass 21, count 0 2006.168.08:09:50.21#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.168.08:09:50.21#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.168.08:09:50.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.168.08:09:50.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.168.08:09:50.21$vc4f8/valo=8,852.99 2006.168.08:09:50.21#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.168.08:09:50.21#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.168.08:09:50.21#ibcon#ireg 17 cls_cnt 0 2006.168.08:09:50.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:09:50.21#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:09:50.21#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:09:50.21#ibcon#enter wrdev, iclass 23, count 0 2006.168.08:09:50.21#ibcon#first serial, iclass 23, count 0 2006.168.08:09:50.21#ibcon#enter sib2, iclass 23, count 0 2006.168.08:09:50.21#ibcon#flushed, iclass 23, count 0 2006.168.08:09:50.21#ibcon#about to write, iclass 23, count 0 2006.168.08:09:50.21#ibcon#wrote, iclass 23, count 0 2006.168.08:09:50.21#ibcon#about to read 3, iclass 23, count 0 2006.168.08:09:50.22#ibcon#read 3, iclass 23, count 0 2006.168.08:09:50.22#ibcon#about to read 4, iclass 23, count 0 2006.168.08:09:50.22#ibcon#read 4, iclass 23, count 0 2006.168.08:09:50.22#ibcon#about to read 5, iclass 23, count 0 2006.168.08:09:50.22#ibcon#read 5, iclass 23, count 0 2006.168.08:09:50.22#ibcon#about to read 6, iclass 23, count 0 2006.168.08:09:50.22#ibcon#read 6, iclass 23, count 0 2006.168.08:09:50.22#ibcon#end of sib2, iclass 23, count 0 2006.168.08:09:50.22#ibcon#*mode == 0, iclass 23, count 0 2006.168.08:09:50.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.168.08:09:50.22#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.08:09:50.22#ibcon#*before write, iclass 23, count 0 2006.168.08:09:50.22#ibcon#enter sib2, iclass 23, count 0 2006.168.08:09:50.22#ibcon#flushed, iclass 23, count 0 2006.168.08:09:50.22#ibcon#about to write, iclass 23, count 0 2006.168.08:09:50.22#ibcon#wrote, iclass 23, count 0 2006.168.08:09:50.22#ibcon#about to read 3, iclass 23, count 0 2006.168.08:09:50.26#ibcon#read 3, iclass 23, count 0 2006.168.08:09:50.26#ibcon#about to read 4, iclass 23, count 0 2006.168.08:09:50.26#ibcon#read 4, iclass 23, count 0 2006.168.08:09:50.26#ibcon#about to read 5, iclass 23, count 0 2006.168.08:09:50.26#ibcon#read 5, iclass 23, count 0 2006.168.08:09:50.26#ibcon#about to read 6, iclass 23, count 0 2006.168.08:09:50.26#ibcon#read 6, iclass 23, count 0 2006.168.08:09:50.26#ibcon#end of sib2, iclass 23, count 0 2006.168.08:09:50.26#ibcon#*after write, iclass 23, count 0 2006.168.08:09:50.26#ibcon#*before return 0, iclass 23, count 0 2006.168.08:09:50.26#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:09:50.26#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:09:50.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.168.08:09:50.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.168.08:09:50.26$vc4f8/va=8,7 2006.168.08:09:50.26#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.168.08:09:50.26#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.168.08:09:50.26#ibcon#ireg 11 cls_cnt 2 2006.168.08:09:50.26#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:09:50.33#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:09:50.33#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:09:50.33#ibcon#enter wrdev, iclass 25, count 2 2006.168.08:09:50.33#ibcon#first serial, iclass 25, count 2 2006.168.08:09:50.33#ibcon#enter sib2, iclass 25, count 2 2006.168.08:09:50.33#ibcon#flushed, iclass 25, count 2 2006.168.08:09:50.33#ibcon#about to write, iclass 25, count 2 2006.168.08:09:50.33#ibcon#wrote, iclass 25, count 2 2006.168.08:09:50.33#ibcon#about to read 3, iclass 25, count 2 2006.168.08:09:50.35#ibcon#read 3, iclass 25, count 2 2006.168.08:09:50.35#ibcon#about to read 4, iclass 25, count 2 2006.168.08:09:50.35#ibcon#read 4, iclass 25, count 2 2006.168.08:09:50.35#ibcon#about to read 5, iclass 25, count 2 2006.168.08:09:50.35#ibcon#read 5, iclass 25, count 2 2006.168.08:09:50.35#ibcon#about to read 6, iclass 25, count 2 2006.168.08:09:50.35#ibcon#read 6, iclass 25, count 2 2006.168.08:09:50.35#ibcon#end of sib2, iclass 25, count 2 2006.168.08:09:50.35#ibcon#*mode == 0, iclass 25, count 2 2006.168.08:09:50.35#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.168.08:09:50.35#ibcon#[25=AT08-07\r\n] 2006.168.08:09:50.35#ibcon#*before write, iclass 25, count 2 2006.168.08:09:50.35#ibcon#enter sib2, iclass 25, count 2 2006.168.08:09:50.35#ibcon#flushed, iclass 25, count 2 2006.168.08:09:50.35#ibcon#about to write, iclass 25, count 2 2006.168.08:09:50.35#ibcon#wrote, iclass 25, count 2 2006.168.08:09:50.35#ibcon#about to read 3, iclass 25, count 2 2006.168.08:09:50.38#ibcon#read 3, iclass 25, count 2 2006.168.08:09:50.38#ibcon#about to read 4, iclass 25, count 2 2006.168.08:09:50.38#ibcon#read 4, iclass 25, count 2 2006.168.08:09:50.38#ibcon#about to read 5, iclass 25, count 2 2006.168.08:09:50.38#ibcon#read 5, iclass 25, count 2 2006.168.08:09:50.38#ibcon#about to read 6, iclass 25, count 2 2006.168.08:09:50.38#ibcon#read 6, iclass 25, count 2 2006.168.08:09:50.38#ibcon#end of sib2, iclass 25, count 2 2006.168.08:09:50.38#ibcon#*after write, iclass 25, count 2 2006.168.08:09:50.38#ibcon#*before return 0, iclass 25, count 2 2006.168.08:09:50.38#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:09:50.38#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:09:50.38#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.168.08:09:50.38#ibcon#ireg 7 cls_cnt 0 2006.168.08:09:50.38#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:09:50.50#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:09:50.50#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:09:50.50#ibcon#enter wrdev, iclass 25, count 0 2006.168.08:09:50.50#ibcon#first serial, iclass 25, count 0 2006.168.08:09:50.50#ibcon#enter sib2, iclass 25, count 0 2006.168.08:09:50.50#ibcon#flushed, iclass 25, count 0 2006.168.08:09:50.50#ibcon#about to write, iclass 25, count 0 2006.168.08:09:50.50#ibcon#wrote, iclass 25, count 0 2006.168.08:09:50.50#ibcon#about to read 3, iclass 25, count 0 2006.168.08:09:50.52#ibcon#read 3, iclass 25, count 0 2006.168.08:09:50.52#ibcon#about to read 4, iclass 25, count 0 2006.168.08:09:50.52#ibcon#read 4, iclass 25, count 0 2006.168.08:09:50.52#ibcon#about to read 5, iclass 25, count 0 2006.168.08:09:50.52#ibcon#read 5, iclass 25, count 0 2006.168.08:09:50.52#ibcon#about to read 6, iclass 25, count 0 2006.168.08:09:50.52#ibcon#read 6, iclass 25, count 0 2006.168.08:09:50.52#ibcon#end of sib2, iclass 25, count 0 2006.168.08:09:50.52#ibcon#*mode == 0, iclass 25, count 0 2006.168.08:09:50.52#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.168.08:09:50.52#ibcon#[25=USB\r\n] 2006.168.08:09:50.52#ibcon#*before write, iclass 25, count 0 2006.168.08:09:50.52#ibcon#enter sib2, iclass 25, count 0 2006.168.08:09:50.52#ibcon#flushed, iclass 25, count 0 2006.168.08:09:50.52#ibcon#about to write, iclass 25, count 0 2006.168.08:09:50.52#ibcon#wrote, iclass 25, count 0 2006.168.08:09:50.52#ibcon#about to read 3, iclass 25, count 0 2006.168.08:09:50.55#ibcon#read 3, iclass 25, count 0 2006.168.08:09:50.55#ibcon#about to read 4, iclass 25, count 0 2006.168.08:09:50.55#ibcon#read 4, iclass 25, count 0 2006.168.08:09:50.55#ibcon#about to read 5, iclass 25, count 0 2006.168.08:09:50.55#ibcon#read 5, iclass 25, count 0 2006.168.08:09:50.55#ibcon#about to read 6, iclass 25, count 0 2006.168.08:09:50.55#ibcon#read 6, iclass 25, count 0 2006.168.08:09:50.55#ibcon#end of sib2, iclass 25, count 0 2006.168.08:09:50.55#ibcon#*after write, iclass 25, count 0 2006.168.08:09:50.55#ibcon#*before return 0, iclass 25, count 0 2006.168.08:09:50.55#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:09:50.55#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:09:50.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.168.08:09:50.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.168.08:09:50.55$vc4f8/vblo=1,632.99 2006.168.08:09:50.55#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.168.08:09:50.55#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.168.08:09:50.55#ibcon#ireg 17 cls_cnt 0 2006.168.08:09:50.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:09:50.55#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:09:50.55#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:09:50.55#ibcon#enter wrdev, iclass 27, count 0 2006.168.08:09:50.55#ibcon#first serial, iclass 27, count 0 2006.168.08:09:50.55#ibcon#enter sib2, iclass 27, count 0 2006.168.08:09:50.55#ibcon#flushed, iclass 27, count 0 2006.168.08:09:50.55#ibcon#about to write, iclass 27, count 0 2006.168.08:09:50.55#ibcon#wrote, iclass 27, count 0 2006.168.08:09:50.55#ibcon#about to read 3, iclass 27, count 0 2006.168.08:09:50.57#ibcon#read 3, iclass 27, count 0 2006.168.08:09:50.57#ibcon#about to read 4, iclass 27, count 0 2006.168.08:09:50.57#ibcon#read 4, iclass 27, count 0 2006.168.08:09:50.57#ibcon#about to read 5, iclass 27, count 0 2006.168.08:09:50.57#ibcon#read 5, iclass 27, count 0 2006.168.08:09:50.57#ibcon#about to read 6, iclass 27, count 0 2006.168.08:09:50.57#ibcon#read 6, iclass 27, count 0 2006.168.08:09:50.57#ibcon#end of sib2, iclass 27, count 0 2006.168.08:09:50.57#ibcon#*mode == 0, iclass 27, count 0 2006.168.08:09:50.57#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.168.08:09:50.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.08:09:50.57#ibcon#*before write, iclass 27, count 0 2006.168.08:09:50.57#ibcon#enter sib2, iclass 27, count 0 2006.168.08:09:50.57#ibcon#flushed, iclass 27, count 0 2006.168.08:09:50.57#ibcon#about to write, iclass 27, count 0 2006.168.08:09:50.57#ibcon#wrote, iclass 27, count 0 2006.168.08:09:50.57#ibcon#about to read 3, iclass 27, count 0 2006.168.08:09:50.61#ibcon#read 3, iclass 27, count 0 2006.168.08:09:50.61#ibcon#about to read 4, iclass 27, count 0 2006.168.08:09:50.61#ibcon#read 4, iclass 27, count 0 2006.168.08:09:50.61#ibcon#about to read 5, iclass 27, count 0 2006.168.08:09:50.61#ibcon#read 5, iclass 27, count 0 2006.168.08:09:50.61#ibcon#about to read 6, iclass 27, count 0 2006.168.08:09:50.61#ibcon#read 6, iclass 27, count 0 2006.168.08:09:50.61#ibcon#end of sib2, iclass 27, count 0 2006.168.08:09:50.61#ibcon#*after write, iclass 27, count 0 2006.168.08:09:50.61#ibcon#*before return 0, iclass 27, count 0 2006.168.08:09:50.61#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:09:50.61#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:09:50.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.168.08:09:50.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.168.08:09:50.61$vc4f8/vb=1,4 2006.168.08:09:50.61#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.168.08:09:50.61#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.168.08:09:50.61#ibcon#ireg 11 cls_cnt 2 2006.168.08:09:50.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:09:50.61#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:09:50.61#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:09:50.61#ibcon#enter wrdev, iclass 29, count 2 2006.168.08:09:50.61#ibcon#first serial, iclass 29, count 2 2006.168.08:09:50.61#ibcon#enter sib2, iclass 29, count 2 2006.168.08:09:50.61#ibcon#flushed, iclass 29, count 2 2006.168.08:09:50.61#ibcon#about to write, iclass 29, count 2 2006.168.08:09:50.61#ibcon#wrote, iclass 29, count 2 2006.168.08:09:50.61#ibcon#about to read 3, iclass 29, count 2 2006.168.08:09:50.63#ibcon#read 3, iclass 29, count 2 2006.168.08:09:50.63#ibcon#about to read 4, iclass 29, count 2 2006.168.08:09:50.63#ibcon#read 4, iclass 29, count 2 2006.168.08:09:50.63#ibcon#about to read 5, iclass 29, count 2 2006.168.08:09:50.63#ibcon#read 5, iclass 29, count 2 2006.168.08:09:50.63#ibcon#about to read 6, iclass 29, count 2 2006.168.08:09:50.63#ibcon#read 6, iclass 29, count 2 2006.168.08:09:50.63#ibcon#end of sib2, iclass 29, count 2 2006.168.08:09:50.63#ibcon#*mode == 0, iclass 29, count 2 2006.168.08:09:50.63#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.168.08:09:50.63#ibcon#[27=AT01-04\r\n] 2006.168.08:09:50.63#ibcon#*before write, iclass 29, count 2 2006.168.08:09:50.63#ibcon#enter sib2, iclass 29, count 2 2006.168.08:09:50.63#ibcon#flushed, iclass 29, count 2 2006.168.08:09:50.63#ibcon#about to write, iclass 29, count 2 2006.168.08:09:50.63#ibcon#wrote, iclass 29, count 2 2006.168.08:09:50.63#ibcon#about to read 3, iclass 29, count 2 2006.168.08:09:50.66#ibcon#read 3, iclass 29, count 2 2006.168.08:09:50.66#ibcon#about to read 4, iclass 29, count 2 2006.168.08:09:50.66#ibcon#read 4, iclass 29, count 2 2006.168.08:09:50.66#ibcon#about to read 5, iclass 29, count 2 2006.168.08:09:50.66#ibcon#read 5, iclass 29, count 2 2006.168.08:09:50.66#ibcon#about to read 6, iclass 29, count 2 2006.168.08:09:50.66#ibcon#read 6, iclass 29, count 2 2006.168.08:09:50.66#ibcon#end of sib2, iclass 29, count 2 2006.168.08:09:50.66#ibcon#*after write, iclass 29, count 2 2006.168.08:09:50.66#ibcon#*before return 0, iclass 29, count 2 2006.168.08:09:50.66#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:09:50.66#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:09:50.66#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.168.08:09:50.66#ibcon#ireg 7 cls_cnt 0 2006.168.08:09:50.66#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:09:50.78#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:09:50.78#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:09:50.78#ibcon#enter wrdev, iclass 29, count 0 2006.168.08:09:50.78#ibcon#first serial, iclass 29, count 0 2006.168.08:09:50.78#ibcon#enter sib2, iclass 29, count 0 2006.168.08:09:50.78#ibcon#flushed, iclass 29, count 0 2006.168.08:09:50.78#ibcon#about to write, iclass 29, count 0 2006.168.08:09:50.78#ibcon#wrote, iclass 29, count 0 2006.168.08:09:50.78#ibcon#about to read 3, iclass 29, count 0 2006.168.08:09:50.80#ibcon#read 3, iclass 29, count 0 2006.168.08:09:50.80#ibcon#about to read 4, iclass 29, count 0 2006.168.08:09:50.80#ibcon#read 4, iclass 29, count 0 2006.168.08:09:50.80#ibcon#about to read 5, iclass 29, count 0 2006.168.08:09:50.80#ibcon#read 5, iclass 29, count 0 2006.168.08:09:50.80#ibcon#about to read 6, iclass 29, count 0 2006.168.08:09:50.80#ibcon#read 6, iclass 29, count 0 2006.168.08:09:50.80#ibcon#end of sib2, iclass 29, count 0 2006.168.08:09:50.80#ibcon#*mode == 0, iclass 29, count 0 2006.168.08:09:50.80#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.168.08:09:50.80#ibcon#[27=USB\r\n] 2006.168.08:09:50.80#ibcon#*before write, iclass 29, count 0 2006.168.08:09:50.80#ibcon#enter sib2, iclass 29, count 0 2006.168.08:09:50.80#ibcon#flushed, iclass 29, count 0 2006.168.08:09:50.80#ibcon#about to write, iclass 29, count 0 2006.168.08:09:50.80#ibcon#wrote, iclass 29, count 0 2006.168.08:09:50.80#ibcon#about to read 3, iclass 29, count 0 2006.168.08:09:50.83#ibcon#read 3, iclass 29, count 0 2006.168.08:09:50.83#ibcon#about to read 4, iclass 29, count 0 2006.168.08:09:50.83#ibcon#read 4, iclass 29, count 0 2006.168.08:09:50.83#ibcon#about to read 5, iclass 29, count 0 2006.168.08:09:50.83#ibcon#read 5, iclass 29, count 0 2006.168.08:09:50.83#ibcon#about to read 6, iclass 29, count 0 2006.168.08:09:50.83#ibcon#read 6, iclass 29, count 0 2006.168.08:09:50.83#ibcon#end of sib2, iclass 29, count 0 2006.168.08:09:50.83#ibcon#*after write, iclass 29, count 0 2006.168.08:09:50.83#ibcon#*before return 0, iclass 29, count 0 2006.168.08:09:50.83#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:09:50.83#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:09:50.83#ibcon#about to clear, iclass 29 cls_cnt 0 2006.168.08:09:50.83#ibcon#cleared, iclass 29 cls_cnt 0 2006.168.08:09:50.83$vc4f8/vblo=2,640.99 2006.168.08:09:50.83#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.168.08:09:50.83#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.168.08:09:50.83#ibcon#ireg 17 cls_cnt 0 2006.168.08:09:50.83#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:09:50.83#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:09:50.83#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:09:50.83#ibcon#enter wrdev, iclass 31, count 0 2006.168.08:09:50.83#ibcon#first serial, iclass 31, count 0 2006.168.08:09:50.83#ibcon#enter sib2, iclass 31, count 0 2006.168.08:09:50.83#ibcon#flushed, iclass 31, count 0 2006.168.08:09:50.83#ibcon#about to write, iclass 31, count 0 2006.168.08:09:50.83#ibcon#wrote, iclass 31, count 0 2006.168.08:09:50.83#ibcon#about to read 3, iclass 31, count 0 2006.168.08:09:50.85#ibcon#read 3, iclass 31, count 0 2006.168.08:09:50.85#ibcon#about to read 4, iclass 31, count 0 2006.168.08:09:50.85#ibcon#read 4, iclass 31, count 0 2006.168.08:09:50.85#ibcon#about to read 5, iclass 31, count 0 2006.168.08:09:50.85#ibcon#read 5, iclass 31, count 0 2006.168.08:09:50.85#ibcon#about to read 6, iclass 31, count 0 2006.168.08:09:50.85#ibcon#read 6, iclass 31, count 0 2006.168.08:09:50.85#ibcon#end of sib2, iclass 31, count 0 2006.168.08:09:50.85#ibcon#*mode == 0, iclass 31, count 0 2006.168.08:09:50.85#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.168.08:09:50.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.08:09:50.85#ibcon#*before write, iclass 31, count 0 2006.168.08:09:50.85#ibcon#enter sib2, iclass 31, count 0 2006.168.08:09:50.85#ibcon#flushed, iclass 31, count 0 2006.168.08:09:50.85#ibcon#about to write, iclass 31, count 0 2006.168.08:09:50.85#ibcon#wrote, iclass 31, count 0 2006.168.08:09:50.85#ibcon#about to read 3, iclass 31, count 0 2006.168.08:09:50.89#ibcon#read 3, iclass 31, count 0 2006.168.08:09:50.89#ibcon#about to read 4, iclass 31, count 0 2006.168.08:09:50.89#ibcon#read 4, iclass 31, count 0 2006.168.08:09:50.89#ibcon#about to read 5, iclass 31, count 0 2006.168.08:09:50.89#ibcon#read 5, iclass 31, count 0 2006.168.08:09:50.89#ibcon#about to read 6, iclass 31, count 0 2006.168.08:09:50.89#ibcon#read 6, iclass 31, count 0 2006.168.08:09:50.89#ibcon#end of sib2, iclass 31, count 0 2006.168.08:09:50.89#ibcon#*after write, iclass 31, count 0 2006.168.08:09:50.89#ibcon#*before return 0, iclass 31, count 0 2006.168.08:09:50.89#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:09:50.89#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:09:50.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.168.08:09:50.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.168.08:09:50.89$vc4f8/vb=2,4 2006.168.08:09:50.89#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.168.08:09:50.89#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.168.08:09:50.89#ibcon#ireg 11 cls_cnt 2 2006.168.08:09:50.89#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.168.08:09:50.95#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.168.08:09:50.95#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.168.08:09:50.95#ibcon#enter wrdev, iclass 33, count 2 2006.168.08:09:50.95#ibcon#first serial, iclass 33, count 2 2006.168.08:09:50.95#ibcon#enter sib2, iclass 33, count 2 2006.168.08:09:50.95#ibcon#flushed, iclass 33, count 2 2006.168.08:09:50.95#ibcon#about to write, iclass 33, count 2 2006.168.08:09:50.95#ibcon#wrote, iclass 33, count 2 2006.168.08:09:50.95#ibcon#about to read 3, iclass 33, count 2 2006.168.08:09:50.97#ibcon#read 3, iclass 33, count 2 2006.168.08:09:50.97#ibcon#about to read 4, iclass 33, count 2 2006.168.08:09:50.97#ibcon#read 4, iclass 33, count 2 2006.168.08:09:50.97#ibcon#about to read 5, iclass 33, count 2 2006.168.08:09:50.97#ibcon#read 5, iclass 33, count 2 2006.168.08:09:50.97#ibcon#about to read 6, iclass 33, count 2 2006.168.08:09:50.97#ibcon#read 6, iclass 33, count 2 2006.168.08:09:50.97#ibcon#end of sib2, iclass 33, count 2 2006.168.08:09:50.97#ibcon#*mode == 0, iclass 33, count 2 2006.168.08:09:50.97#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.168.08:09:50.97#ibcon#[27=AT02-04\r\n] 2006.168.08:09:50.97#ibcon#*before write, iclass 33, count 2 2006.168.08:09:50.97#ibcon#enter sib2, iclass 33, count 2 2006.168.08:09:50.97#ibcon#flushed, iclass 33, count 2 2006.168.08:09:50.97#ibcon#about to write, iclass 33, count 2 2006.168.08:09:50.97#ibcon#wrote, iclass 33, count 2 2006.168.08:09:50.97#ibcon#about to read 3, iclass 33, count 2 2006.168.08:09:51.00#ibcon#read 3, iclass 33, count 2 2006.168.08:09:51.00#ibcon#about to read 4, iclass 33, count 2 2006.168.08:09:51.00#ibcon#read 4, iclass 33, count 2 2006.168.08:09:51.00#ibcon#about to read 5, iclass 33, count 2 2006.168.08:09:51.00#ibcon#read 5, iclass 33, count 2 2006.168.08:09:51.00#ibcon#about to read 6, iclass 33, count 2 2006.168.08:09:51.00#ibcon#read 6, iclass 33, count 2 2006.168.08:09:51.00#ibcon#end of sib2, iclass 33, count 2 2006.168.08:09:51.00#ibcon#*after write, iclass 33, count 2 2006.168.08:09:51.00#ibcon#*before return 0, iclass 33, count 2 2006.168.08:09:51.00#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.168.08:09:51.00#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.168.08:09:51.00#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.168.08:09:51.00#ibcon#ireg 7 cls_cnt 0 2006.168.08:09:51.00#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.168.08:09:51.12#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.168.08:09:51.12#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.168.08:09:51.12#ibcon#enter wrdev, iclass 33, count 0 2006.168.08:09:51.12#ibcon#first serial, iclass 33, count 0 2006.168.08:09:51.12#ibcon#enter sib2, iclass 33, count 0 2006.168.08:09:51.12#ibcon#flushed, iclass 33, count 0 2006.168.08:09:51.12#ibcon#about to write, iclass 33, count 0 2006.168.08:09:51.12#ibcon#wrote, iclass 33, count 0 2006.168.08:09:51.12#ibcon#about to read 3, iclass 33, count 0 2006.168.08:09:51.14#ibcon#read 3, iclass 33, count 0 2006.168.08:09:51.14#ibcon#about to read 4, iclass 33, count 0 2006.168.08:09:51.14#ibcon#read 4, iclass 33, count 0 2006.168.08:09:51.14#ibcon#about to read 5, iclass 33, count 0 2006.168.08:09:51.14#ibcon#read 5, iclass 33, count 0 2006.168.08:09:51.14#ibcon#about to read 6, iclass 33, count 0 2006.168.08:09:51.14#ibcon#read 6, iclass 33, count 0 2006.168.08:09:51.14#ibcon#end of sib2, iclass 33, count 0 2006.168.08:09:51.14#ibcon#*mode == 0, iclass 33, count 0 2006.168.08:09:51.14#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.168.08:09:51.14#ibcon#[27=USB\r\n] 2006.168.08:09:51.14#ibcon#*before write, iclass 33, count 0 2006.168.08:09:51.14#ibcon#enter sib2, iclass 33, count 0 2006.168.08:09:51.14#ibcon#flushed, iclass 33, count 0 2006.168.08:09:51.14#ibcon#about to write, iclass 33, count 0 2006.168.08:09:51.14#ibcon#wrote, iclass 33, count 0 2006.168.08:09:51.14#ibcon#about to read 3, iclass 33, count 0 2006.168.08:09:51.17#ibcon#read 3, iclass 33, count 0 2006.168.08:09:51.17#ibcon#about to read 4, iclass 33, count 0 2006.168.08:09:51.17#ibcon#read 4, iclass 33, count 0 2006.168.08:09:51.17#ibcon#about to read 5, iclass 33, count 0 2006.168.08:09:51.17#ibcon#read 5, iclass 33, count 0 2006.168.08:09:51.17#ibcon#about to read 6, iclass 33, count 0 2006.168.08:09:51.17#ibcon#read 6, iclass 33, count 0 2006.168.08:09:51.17#ibcon#end of sib2, iclass 33, count 0 2006.168.08:09:51.17#ibcon#*after write, iclass 33, count 0 2006.168.08:09:51.17#ibcon#*before return 0, iclass 33, count 0 2006.168.08:09:51.17#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.168.08:09:51.17#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.168.08:09:51.17#ibcon#about to clear, iclass 33 cls_cnt 0 2006.168.08:09:51.17#ibcon#cleared, iclass 33 cls_cnt 0 2006.168.08:09:51.17$vc4f8/vblo=3,656.99 2006.168.08:09:51.17#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.168.08:09:51.17#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.168.08:09:51.17#ibcon#ireg 17 cls_cnt 0 2006.168.08:09:51.17#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.168.08:09:51.17#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.168.08:09:51.17#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.168.08:09:51.17#ibcon#enter wrdev, iclass 35, count 0 2006.168.08:09:51.17#ibcon#first serial, iclass 35, count 0 2006.168.08:09:51.17#ibcon#enter sib2, iclass 35, count 0 2006.168.08:09:51.17#ibcon#flushed, iclass 35, count 0 2006.168.08:09:51.17#ibcon#about to write, iclass 35, count 0 2006.168.08:09:51.17#ibcon#wrote, iclass 35, count 0 2006.168.08:09:51.17#ibcon#about to read 3, iclass 35, count 0 2006.168.08:09:51.19#ibcon#read 3, iclass 35, count 0 2006.168.08:09:51.19#ibcon#about to read 4, iclass 35, count 0 2006.168.08:09:51.19#ibcon#read 4, iclass 35, count 0 2006.168.08:09:51.19#ibcon#about to read 5, iclass 35, count 0 2006.168.08:09:51.19#ibcon#read 5, iclass 35, count 0 2006.168.08:09:51.19#ibcon#about to read 6, iclass 35, count 0 2006.168.08:09:51.19#ibcon#read 6, iclass 35, count 0 2006.168.08:09:51.19#ibcon#end of sib2, iclass 35, count 0 2006.168.08:09:51.19#ibcon#*mode == 0, iclass 35, count 0 2006.168.08:09:51.19#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.168.08:09:51.19#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.08:09:51.19#ibcon#*before write, iclass 35, count 0 2006.168.08:09:51.19#ibcon#enter sib2, iclass 35, count 0 2006.168.08:09:51.19#ibcon#flushed, iclass 35, count 0 2006.168.08:09:51.19#ibcon#about to write, iclass 35, count 0 2006.168.08:09:51.19#ibcon#wrote, iclass 35, count 0 2006.168.08:09:51.19#ibcon#about to read 3, iclass 35, count 0 2006.168.08:09:51.23#ibcon#read 3, iclass 35, count 0 2006.168.08:09:51.23#ibcon#about to read 4, iclass 35, count 0 2006.168.08:09:51.23#ibcon#read 4, iclass 35, count 0 2006.168.08:09:51.23#ibcon#about to read 5, iclass 35, count 0 2006.168.08:09:51.23#ibcon#read 5, iclass 35, count 0 2006.168.08:09:51.23#ibcon#about to read 6, iclass 35, count 0 2006.168.08:09:51.23#ibcon#read 6, iclass 35, count 0 2006.168.08:09:51.23#ibcon#end of sib2, iclass 35, count 0 2006.168.08:09:51.23#ibcon#*after write, iclass 35, count 0 2006.168.08:09:51.23#ibcon#*before return 0, iclass 35, count 0 2006.168.08:09:51.23#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.168.08:09:51.23#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.168.08:09:51.23#ibcon#about to clear, iclass 35 cls_cnt 0 2006.168.08:09:51.23#ibcon#cleared, iclass 35 cls_cnt 0 2006.168.08:09:51.23$vc4f8/vb=3,4 2006.168.08:09:51.23#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.168.08:09:51.23#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.168.08:09:51.23#ibcon#ireg 11 cls_cnt 2 2006.168.08:09:51.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.168.08:09:51.29#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.168.08:09:51.29#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.168.08:09:51.29#ibcon#enter wrdev, iclass 37, count 2 2006.168.08:09:51.29#ibcon#first serial, iclass 37, count 2 2006.168.08:09:51.29#ibcon#enter sib2, iclass 37, count 2 2006.168.08:09:51.29#ibcon#flushed, iclass 37, count 2 2006.168.08:09:51.29#ibcon#about to write, iclass 37, count 2 2006.168.08:09:51.29#ibcon#wrote, iclass 37, count 2 2006.168.08:09:51.29#ibcon#about to read 3, iclass 37, count 2 2006.168.08:09:51.31#ibcon#read 3, iclass 37, count 2 2006.168.08:09:51.31#ibcon#about to read 4, iclass 37, count 2 2006.168.08:09:51.31#ibcon#read 4, iclass 37, count 2 2006.168.08:09:51.31#ibcon#about to read 5, iclass 37, count 2 2006.168.08:09:51.31#ibcon#read 5, iclass 37, count 2 2006.168.08:09:51.31#ibcon#about to read 6, iclass 37, count 2 2006.168.08:09:51.31#ibcon#read 6, iclass 37, count 2 2006.168.08:09:51.31#ibcon#end of sib2, iclass 37, count 2 2006.168.08:09:51.31#ibcon#*mode == 0, iclass 37, count 2 2006.168.08:09:51.31#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.168.08:09:51.31#ibcon#[27=AT03-04\r\n] 2006.168.08:09:51.31#ibcon#*before write, iclass 37, count 2 2006.168.08:09:51.31#ibcon#enter sib2, iclass 37, count 2 2006.168.08:09:51.31#ibcon#flushed, iclass 37, count 2 2006.168.08:09:51.31#ibcon#about to write, iclass 37, count 2 2006.168.08:09:51.31#ibcon#wrote, iclass 37, count 2 2006.168.08:09:51.31#ibcon#about to read 3, iclass 37, count 2 2006.168.08:09:51.34#ibcon#read 3, iclass 37, count 2 2006.168.08:09:51.34#ibcon#about to read 4, iclass 37, count 2 2006.168.08:09:51.34#ibcon#read 4, iclass 37, count 2 2006.168.08:09:51.34#ibcon#about to read 5, iclass 37, count 2 2006.168.08:09:51.34#ibcon#read 5, iclass 37, count 2 2006.168.08:09:51.34#ibcon#about to read 6, iclass 37, count 2 2006.168.08:09:51.34#ibcon#read 6, iclass 37, count 2 2006.168.08:09:51.34#ibcon#end of sib2, iclass 37, count 2 2006.168.08:09:51.34#ibcon#*after write, iclass 37, count 2 2006.168.08:09:51.34#ibcon#*before return 0, iclass 37, count 2 2006.168.08:09:51.34#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.168.08:09:51.34#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.168.08:09:51.34#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.168.08:09:51.34#ibcon#ireg 7 cls_cnt 0 2006.168.08:09:51.34#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.168.08:09:51.46#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.168.08:09:51.46#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.168.08:09:51.46#ibcon#enter wrdev, iclass 37, count 0 2006.168.08:09:51.46#ibcon#first serial, iclass 37, count 0 2006.168.08:09:51.46#ibcon#enter sib2, iclass 37, count 0 2006.168.08:09:51.46#ibcon#flushed, iclass 37, count 0 2006.168.08:09:51.46#ibcon#about to write, iclass 37, count 0 2006.168.08:09:51.46#ibcon#wrote, iclass 37, count 0 2006.168.08:09:51.46#ibcon#about to read 3, iclass 37, count 0 2006.168.08:09:51.48#ibcon#read 3, iclass 37, count 0 2006.168.08:09:51.48#ibcon#about to read 4, iclass 37, count 0 2006.168.08:09:51.48#ibcon#read 4, iclass 37, count 0 2006.168.08:09:51.48#ibcon#about to read 5, iclass 37, count 0 2006.168.08:09:51.48#ibcon#read 5, iclass 37, count 0 2006.168.08:09:51.48#ibcon#about to read 6, iclass 37, count 0 2006.168.08:09:51.48#ibcon#read 6, iclass 37, count 0 2006.168.08:09:51.48#ibcon#end of sib2, iclass 37, count 0 2006.168.08:09:51.48#ibcon#*mode == 0, iclass 37, count 0 2006.168.08:09:51.48#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.168.08:09:51.48#ibcon#[27=USB\r\n] 2006.168.08:09:51.48#ibcon#*before write, iclass 37, count 0 2006.168.08:09:51.48#ibcon#enter sib2, iclass 37, count 0 2006.168.08:09:51.48#ibcon#flushed, iclass 37, count 0 2006.168.08:09:51.48#ibcon#about to write, iclass 37, count 0 2006.168.08:09:51.48#ibcon#wrote, iclass 37, count 0 2006.168.08:09:51.48#ibcon#about to read 3, iclass 37, count 0 2006.168.08:09:51.51#ibcon#read 3, iclass 37, count 0 2006.168.08:09:51.51#ibcon#about to read 4, iclass 37, count 0 2006.168.08:09:51.51#ibcon#read 4, iclass 37, count 0 2006.168.08:09:51.51#ibcon#about to read 5, iclass 37, count 0 2006.168.08:09:51.51#ibcon#read 5, iclass 37, count 0 2006.168.08:09:51.51#ibcon#about to read 6, iclass 37, count 0 2006.168.08:09:51.51#ibcon#read 6, iclass 37, count 0 2006.168.08:09:51.51#ibcon#end of sib2, iclass 37, count 0 2006.168.08:09:51.51#ibcon#*after write, iclass 37, count 0 2006.168.08:09:51.51#ibcon#*before return 0, iclass 37, count 0 2006.168.08:09:51.51#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.168.08:09:51.51#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.168.08:09:51.51#ibcon#about to clear, iclass 37 cls_cnt 0 2006.168.08:09:51.51#ibcon#cleared, iclass 37 cls_cnt 0 2006.168.08:09:51.51$vc4f8/vblo=4,712.99 2006.168.08:09:51.51#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.168.08:09:51.51#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.168.08:09:51.51#ibcon#ireg 17 cls_cnt 0 2006.168.08:09:51.51#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.168.08:09:51.51#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.168.08:09:51.51#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.168.08:09:51.51#ibcon#enter wrdev, iclass 39, count 0 2006.168.08:09:51.51#ibcon#first serial, iclass 39, count 0 2006.168.08:09:51.51#ibcon#enter sib2, iclass 39, count 0 2006.168.08:09:51.51#ibcon#flushed, iclass 39, count 0 2006.168.08:09:51.51#ibcon#about to write, iclass 39, count 0 2006.168.08:09:51.51#ibcon#wrote, iclass 39, count 0 2006.168.08:09:51.51#ibcon#about to read 3, iclass 39, count 0 2006.168.08:09:51.53#ibcon#read 3, iclass 39, count 0 2006.168.08:09:51.53#ibcon#about to read 4, iclass 39, count 0 2006.168.08:09:51.53#ibcon#read 4, iclass 39, count 0 2006.168.08:09:51.53#ibcon#about to read 5, iclass 39, count 0 2006.168.08:09:51.53#ibcon#read 5, iclass 39, count 0 2006.168.08:09:51.53#ibcon#about to read 6, iclass 39, count 0 2006.168.08:09:51.53#ibcon#read 6, iclass 39, count 0 2006.168.08:09:51.53#ibcon#end of sib2, iclass 39, count 0 2006.168.08:09:51.53#ibcon#*mode == 0, iclass 39, count 0 2006.168.08:09:51.53#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.168.08:09:51.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.08:09:51.53#ibcon#*before write, iclass 39, count 0 2006.168.08:09:51.53#ibcon#enter sib2, iclass 39, count 0 2006.168.08:09:51.53#ibcon#flushed, iclass 39, count 0 2006.168.08:09:51.53#ibcon#about to write, iclass 39, count 0 2006.168.08:09:51.53#ibcon#wrote, iclass 39, count 0 2006.168.08:09:51.53#ibcon#about to read 3, iclass 39, count 0 2006.168.08:09:51.57#ibcon#read 3, iclass 39, count 0 2006.168.08:09:51.57#ibcon#about to read 4, iclass 39, count 0 2006.168.08:09:51.57#ibcon#read 4, iclass 39, count 0 2006.168.08:09:51.57#ibcon#about to read 5, iclass 39, count 0 2006.168.08:09:51.57#ibcon#read 5, iclass 39, count 0 2006.168.08:09:51.57#ibcon#about to read 6, iclass 39, count 0 2006.168.08:09:51.57#ibcon#read 6, iclass 39, count 0 2006.168.08:09:51.57#ibcon#end of sib2, iclass 39, count 0 2006.168.08:09:51.57#ibcon#*after write, iclass 39, count 0 2006.168.08:09:51.57#ibcon#*before return 0, iclass 39, count 0 2006.168.08:09:51.57#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.168.08:09:51.57#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.168.08:09:51.57#ibcon#about to clear, iclass 39 cls_cnt 0 2006.168.08:09:51.57#ibcon#cleared, iclass 39 cls_cnt 0 2006.168.08:09:51.57$vc4f8/vb=4,4 2006.168.08:09:51.57#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.168.08:09:51.57#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.168.08:09:51.57#ibcon#ireg 11 cls_cnt 2 2006.168.08:09:51.57#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.168.08:09:51.63#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.168.08:09:51.63#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.168.08:09:51.63#ibcon#enter wrdev, iclass 3, count 2 2006.168.08:09:51.63#ibcon#first serial, iclass 3, count 2 2006.168.08:09:51.63#ibcon#enter sib2, iclass 3, count 2 2006.168.08:09:51.63#ibcon#flushed, iclass 3, count 2 2006.168.08:09:51.63#ibcon#about to write, iclass 3, count 2 2006.168.08:09:51.63#ibcon#wrote, iclass 3, count 2 2006.168.08:09:51.63#ibcon#about to read 3, iclass 3, count 2 2006.168.08:09:51.65#ibcon#read 3, iclass 3, count 2 2006.168.08:09:51.65#ibcon#about to read 4, iclass 3, count 2 2006.168.08:09:51.65#ibcon#read 4, iclass 3, count 2 2006.168.08:09:51.65#ibcon#about to read 5, iclass 3, count 2 2006.168.08:09:51.65#ibcon#read 5, iclass 3, count 2 2006.168.08:09:51.65#ibcon#about to read 6, iclass 3, count 2 2006.168.08:09:51.65#ibcon#read 6, iclass 3, count 2 2006.168.08:09:51.65#ibcon#end of sib2, iclass 3, count 2 2006.168.08:09:51.65#ibcon#*mode == 0, iclass 3, count 2 2006.168.08:09:51.65#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.168.08:09:51.65#ibcon#[27=AT04-04\r\n] 2006.168.08:09:51.65#ibcon#*before write, iclass 3, count 2 2006.168.08:09:51.65#ibcon#enter sib2, iclass 3, count 2 2006.168.08:09:51.65#ibcon#flushed, iclass 3, count 2 2006.168.08:09:51.65#ibcon#about to write, iclass 3, count 2 2006.168.08:09:51.65#ibcon#wrote, iclass 3, count 2 2006.168.08:09:51.65#ibcon#about to read 3, iclass 3, count 2 2006.168.08:09:51.68#ibcon#read 3, iclass 3, count 2 2006.168.08:09:51.68#ibcon#about to read 4, iclass 3, count 2 2006.168.08:09:51.68#ibcon#read 4, iclass 3, count 2 2006.168.08:09:51.68#ibcon#about to read 5, iclass 3, count 2 2006.168.08:09:51.68#ibcon#read 5, iclass 3, count 2 2006.168.08:09:51.68#ibcon#about to read 6, iclass 3, count 2 2006.168.08:09:51.68#ibcon#read 6, iclass 3, count 2 2006.168.08:09:51.68#ibcon#end of sib2, iclass 3, count 2 2006.168.08:09:51.68#ibcon#*after write, iclass 3, count 2 2006.168.08:09:51.68#ibcon#*before return 0, iclass 3, count 2 2006.168.08:09:51.68#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.168.08:09:51.68#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.168.08:09:51.68#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.168.08:09:51.68#ibcon#ireg 7 cls_cnt 0 2006.168.08:09:51.68#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.168.08:09:51.80#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.168.08:09:51.80#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.168.08:09:51.80#ibcon#enter wrdev, iclass 3, count 0 2006.168.08:09:51.80#ibcon#first serial, iclass 3, count 0 2006.168.08:09:51.80#ibcon#enter sib2, iclass 3, count 0 2006.168.08:09:51.80#ibcon#flushed, iclass 3, count 0 2006.168.08:09:51.80#ibcon#about to write, iclass 3, count 0 2006.168.08:09:51.80#ibcon#wrote, iclass 3, count 0 2006.168.08:09:51.80#ibcon#about to read 3, iclass 3, count 0 2006.168.08:09:51.82#ibcon#read 3, iclass 3, count 0 2006.168.08:09:51.82#ibcon#about to read 4, iclass 3, count 0 2006.168.08:09:51.82#ibcon#read 4, iclass 3, count 0 2006.168.08:09:51.82#ibcon#about to read 5, iclass 3, count 0 2006.168.08:09:51.82#ibcon#read 5, iclass 3, count 0 2006.168.08:09:51.82#ibcon#about to read 6, iclass 3, count 0 2006.168.08:09:51.82#ibcon#read 6, iclass 3, count 0 2006.168.08:09:51.82#ibcon#end of sib2, iclass 3, count 0 2006.168.08:09:51.82#ibcon#*mode == 0, iclass 3, count 0 2006.168.08:09:51.82#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.168.08:09:51.82#ibcon#[27=USB\r\n] 2006.168.08:09:51.82#ibcon#*before write, iclass 3, count 0 2006.168.08:09:51.82#ibcon#enter sib2, iclass 3, count 0 2006.168.08:09:51.82#ibcon#flushed, iclass 3, count 0 2006.168.08:09:51.82#ibcon#about to write, iclass 3, count 0 2006.168.08:09:51.82#ibcon#wrote, iclass 3, count 0 2006.168.08:09:51.82#ibcon#about to read 3, iclass 3, count 0 2006.168.08:09:51.85#ibcon#read 3, iclass 3, count 0 2006.168.08:09:51.85#ibcon#about to read 4, iclass 3, count 0 2006.168.08:09:51.85#ibcon#read 4, iclass 3, count 0 2006.168.08:09:51.85#ibcon#about to read 5, iclass 3, count 0 2006.168.08:09:51.85#ibcon#read 5, iclass 3, count 0 2006.168.08:09:51.85#ibcon#about to read 6, iclass 3, count 0 2006.168.08:09:51.85#ibcon#read 6, iclass 3, count 0 2006.168.08:09:51.85#ibcon#end of sib2, iclass 3, count 0 2006.168.08:09:51.85#ibcon#*after write, iclass 3, count 0 2006.168.08:09:51.85#ibcon#*before return 0, iclass 3, count 0 2006.168.08:09:51.85#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.168.08:09:51.85#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.168.08:09:51.85#ibcon#about to clear, iclass 3 cls_cnt 0 2006.168.08:09:51.85#ibcon#cleared, iclass 3 cls_cnt 0 2006.168.08:09:51.85$vc4f8/vblo=5,744.99 2006.168.08:09:51.85#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.168.08:09:51.85#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.168.08:09:51.85#ibcon#ireg 17 cls_cnt 0 2006.168.08:09:51.85#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.168.08:09:51.85#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.168.08:09:51.85#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.168.08:09:51.85#ibcon#enter wrdev, iclass 5, count 0 2006.168.08:09:51.85#ibcon#first serial, iclass 5, count 0 2006.168.08:09:51.85#ibcon#enter sib2, iclass 5, count 0 2006.168.08:09:51.85#ibcon#flushed, iclass 5, count 0 2006.168.08:09:51.85#ibcon#about to write, iclass 5, count 0 2006.168.08:09:51.85#ibcon#wrote, iclass 5, count 0 2006.168.08:09:51.85#ibcon#about to read 3, iclass 5, count 0 2006.168.08:09:51.87#ibcon#read 3, iclass 5, count 0 2006.168.08:09:51.87#ibcon#about to read 4, iclass 5, count 0 2006.168.08:09:51.87#ibcon#read 4, iclass 5, count 0 2006.168.08:09:51.87#ibcon#about to read 5, iclass 5, count 0 2006.168.08:09:51.87#ibcon#read 5, iclass 5, count 0 2006.168.08:09:51.87#ibcon#about to read 6, iclass 5, count 0 2006.168.08:09:51.87#ibcon#read 6, iclass 5, count 0 2006.168.08:09:51.87#ibcon#end of sib2, iclass 5, count 0 2006.168.08:09:51.87#ibcon#*mode == 0, iclass 5, count 0 2006.168.08:09:51.87#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.168.08:09:51.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.08:09:51.87#ibcon#*before write, iclass 5, count 0 2006.168.08:09:51.87#ibcon#enter sib2, iclass 5, count 0 2006.168.08:09:51.87#ibcon#flushed, iclass 5, count 0 2006.168.08:09:51.87#ibcon#about to write, iclass 5, count 0 2006.168.08:09:51.87#ibcon#wrote, iclass 5, count 0 2006.168.08:09:51.87#ibcon#about to read 3, iclass 5, count 0 2006.168.08:09:51.91#ibcon#read 3, iclass 5, count 0 2006.168.08:09:51.91#ibcon#about to read 4, iclass 5, count 0 2006.168.08:09:51.91#ibcon#read 4, iclass 5, count 0 2006.168.08:09:51.91#ibcon#about to read 5, iclass 5, count 0 2006.168.08:09:51.91#ibcon#read 5, iclass 5, count 0 2006.168.08:09:51.91#ibcon#about to read 6, iclass 5, count 0 2006.168.08:09:51.91#ibcon#read 6, iclass 5, count 0 2006.168.08:09:51.91#ibcon#end of sib2, iclass 5, count 0 2006.168.08:09:51.91#ibcon#*after write, iclass 5, count 0 2006.168.08:09:51.91#ibcon#*before return 0, iclass 5, count 0 2006.168.08:09:51.91#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.168.08:09:51.91#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.168.08:09:51.91#ibcon#about to clear, iclass 5 cls_cnt 0 2006.168.08:09:51.91#ibcon#cleared, iclass 5 cls_cnt 0 2006.168.08:09:51.91$vc4f8/vb=5,4 2006.168.08:09:51.91#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.168.08:09:51.91#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.168.08:09:51.91#ibcon#ireg 11 cls_cnt 2 2006.168.08:09:51.91#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.168.08:09:51.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.168.08:09:51.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.168.08:09:51.97#ibcon#enter wrdev, iclass 7, count 2 2006.168.08:09:51.97#ibcon#first serial, iclass 7, count 2 2006.168.08:09:51.97#ibcon#enter sib2, iclass 7, count 2 2006.168.08:09:51.97#ibcon#flushed, iclass 7, count 2 2006.168.08:09:51.97#ibcon#about to write, iclass 7, count 2 2006.168.08:09:51.97#ibcon#wrote, iclass 7, count 2 2006.168.08:09:51.97#ibcon#about to read 3, iclass 7, count 2 2006.168.08:09:51.99#ibcon#read 3, iclass 7, count 2 2006.168.08:09:51.99#ibcon#about to read 4, iclass 7, count 2 2006.168.08:09:51.99#ibcon#read 4, iclass 7, count 2 2006.168.08:09:51.99#ibcon#about to read 5, iclass 7, count 2 2006.168.08:09:51.99#ibcon#read 5, iclass 7, count 2 2006.168.08:09:51.99#ibcon#about to read 6, iclass 7, count 2 2006.168.08:09:51.99#ibcon#read 6, iclass 7, count 2 2006.168.08:09:51.99#ibcon#end of sib2, iclass 7, count 2 2006.168.08:09:51.99#ibcon#*mode == 0, iclass 7, count 2 2006.168.08:09:51.99#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.168.08:09:51.99#ibcon#[27=AT05-04\r\n] 2006.168.08:09:51.99#ibcon#*before write, iclass 7, count 2 2006.168.08:09:51.99#ibcon#enter sib2, iclass 7, count 2 2006.168.08:09:51.99#ibcon#flushed, iclass 7, count 2 2006.168.08:09:51.99#ibcon#about to write, iclass 7, count 2 2006.168.08:09:51.99#ibcon#wrote, iclass 7, count 2 2006.168.08:09:51.99#ibcon#about to read 3, iclass 7, count 2 2006.168.08:09:52.02#ibcon#read 3, iclass 7, count 2 2006.168.08:09:52.02#ibcon#about to read 4, iclass 7, count 2 2006.168.08:09:52.02#ibcon#read 4, iclass 7, count 2 2006.168.08:09:52.02#ibcon#about to read 5, iclass 7, count 2 2006.168.08:09:52.02#ibcon#read 5, iclass 7, count 2 2006.168.08:09:52.02#ibcon#about to read 6, iclass 7, count 2 2006.168.08:09:52.02#ibcon#read 6, iclass 7, count 2 2006.168.08:09:52.02#ibcon#end of sib2, iclass 7, count 2 2006.168.08:09:52.02#ibcon#*after write, iclass 7, count 2 2006.168.08:09:52.02#ibcon#*before return 0, iclass 7, count 2 2006.168.08:09:52.02#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.168.08:09:52.02#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.168.08:09:52.02#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.168.08:09:52.02#ibcon#ireg 7 cls_cnt 0 2006.168.08:09:52.02#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.168.08:09:52.14#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.168.08:09:52.14#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.168.08:09:52.14#ibcon#enter wrdev, iclass 7, count 0 2006.168.08:09:52.14#ibcon#first serial, iclass 7, count 0 2006.168.08:09:52.14#ibcon#enter sib2, iclass 7, count 0 2006.168.08:09:52.14#ibcon#flushed, iclass 7, count 0 2006.168.08:09:52.14#ibcon#about to write, iclass 7, count 0 2006.168.08:09:52.14#ibcon#wrote, iclass 7, count 0 2006.168.08:09:52.14#ibcon#about to read 3, iclass 7, count 0 2006.168.08:09:52.16#ibcon#read 3, iclass 7, count 0 2006.168.08:09:52.16#ibcon#about to read 4, iclass 7, count 0 2006.168.08:09:52.16#ibcon#read 4, iclass 7, count 0 2006.168.08:09:52.16#ibcon#about to read 5, iclass 7, count 0 2006.168.08:09:52.16#ibcon#read 5, iclass 7, count 0 2006.168.08:09:52.16#ibcon#about to read 6, iclass 7, count 0 2006.168.08:09:52.16#ibcon#read 6, iclass 7, count 0 2006.168.08:09:52.16#ibcon#end of sib2, iclass 7, count 0 2006.168.08:09:52.16#ibcon#*mode == 0, iclass 7, count 0 2006.168.08:09:52.16#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.168.08:09:52.16#ibcon#[27=USB\r\n] 2006.168.08:09:52.16#ibcon#*before write, iclass 7, count 0 2006.168.08:09:52.16#ibcon#enter sib2, iclass 7, count 0 2006.168.08:09:52.16#ibcon#flushed, iclass 7, count 0 2006.168.08:09:52.16#ibcon#about to write, iclass 7, count 0 2006.168.08:09:52.16#ibcon#wrote, iclass 7, count 0 2006.168.08:09:52.16#ibcon#about to read 3, iclass 7, count 0 2006.168.08:09:52.19#ibcon#read 3, iclass 7, count 0 2006.168.08:09:52.19#ibcon#about to read 4, iclass 7, count 0 2006.168.08:09:52.19#ibcon#read 4, iclass 7, count 0 2006.168.08:09:52.19#ibcon#about to read 5, iclass 7, count 0 2006.168.08:09:52.19#ibcon#read 5, iclass 7, count 0 2006.168.08:09:52.19#ibcon#about to read 6, iclass 7, count 0 2006.168.08:09:52.19#ibcon#read 6, iclass 7, count 0 2006.168.08:09:52.19#ibcon#end of sib2, iclass 7, count 0 2006.168.08:09:52.19#ibcon#*after write, iclass 7, count 0 2006.168.08:09:52.19#ibcon#*before return 0, iclass 7, count 0 2006.168.08:09:52.19#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.168.08:09:52.19#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.168.08:09:52.19#ibcon#about to clear, iclass 7 cls_cnt 0 2006.168.08:09:52.19#ibcon#cleared, iclass 7 cls_cnt 0 2006.168.08:09:52.19$vc4f8/vblo=6,752.99 2006.168.08:09:52.19#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.168.08:09:52.19#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.168.08:09:52.19#ibcon#ireg 17 cls_cnt 0 2006.168.08:09:52.19#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.168.08:09:52.19#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.168.08:09:52.19#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.168.08:09:52.19#ibcon#enter wrdev, iclass 11, count 0 2006.168.08:09:52.19#ibcon#first serial, iclass 11, count 0 2006.168.08:09:52.19#ibcon#enter sib2, iclass 11, count 0 2006.168.08:09:52.19#ibcon#flushed, iclass 11, count 0 2006.168.08:09:52.19#ibcon#about to write, iclass 11, count 0 2006.168.08:09:52.19#ibcon#wrote, iclass 11, count 0 2006.168.08:09:52.19#ibcon#about to read 3, iclass 11, count 0 2006.168.08:09:52.21#ibcon#read 3, iclass 11, count 0 2006.168.08:09:52.21#ibcon#about to read 4, iclass 11, count 0 2006.168.08:09:52.21#ibcon#read 4, iclass 11, count 0 2006.168.08:09:52.21#ibcon#about to read 5, iclass 11, count 0 2006.168.08:09:52.21#ibcon#read 5, iclass 11, count 0 2006.168.08:09:52.21#ibcon#about to read 6, iclass 11, count 0 2006.168.08:09:52.21#ibcon#read 6, iclass 11, count 0 2006.168.08:09:52.21#ibcon#end of sib2, iclass 11, count 0 2006.168.08:09:52.21#ibcon#*mode == 0, iclass 11, count 0 2006.168.08:09:52.21#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.168.08:09:52.21#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.08:09:52.21#ibcon#*before write, iclass 11, count 0 2006.168.08:09:52.21#ibcon#enter sib2, iclass 11, count 0 2006.168.08:09:52.21#ibcon#flushed, iclass 11, count 0 2006.168.08:09:52.21#ibcon#about to write, iclass 11, count 0 2006.168.08:09:52.21#ibcon#wrote, iclass 11, count 0 2006.168.08:09:52.21#ibcon#about to read 3, iclass 11, count 0 2006.168.08:09:52.25#ibcon#read 3, iclass 11, count 0 2006.168.08:09:52.25#ibcon#about to read 4, iclass 11, count 0 2006.168.08:09:52.25#ibcon#read 4, iclass 11, count 0 2006.168.08:09:52.25#ibcon#about to read 5, iclass 11, count 0 2006.168.08:09:52.25#ibcon#read 5, iclass 11, count 0 2006.168.08:09:52.25#ibcon#about to read 6, iclass 11, count 0 2006.168.08:09:52.25#ibcon#read 6, iclass 11, count 0 2006.168.08:09:52.25#ibcon#end of sib2, iclass 11, count 0 2006.168.08:09:52.25#ibcon#*after write, iclass 11, count 0 2006.168.08:09:52.25#ibcon#*before return 0, iclass 11, count 0 2006.168.08:09:52.25#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.168.08:09:52.25#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.168.08:09:52.25#ibcon#about to clear, iclass 11 cls_cnt 0 2006.168.08:09:52.25#ibcon#cleared, iclass 11 cls_cnt 0 2006.168.08:09:52.25$vc4f8/vb=6,4 2006.168.08:09:52.25#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.168.08:09:52.25#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.168.08:09:52.25#ibcon#ireg 11 cls_cnt 2 2006.168.08:09:52.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.168.08:09:52.31#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.168.08:09:52.31#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.168.08:09:52.31#ibcon#enter wrdev, iclass 13, count 2 2006.168.08:09:52.31#ibcon#first serial, iclass 13, count 2 2006.168.08:09:52.31#ibcon#enter sib2, iclass 13, count 2 2006.168.08:09:52.31#ibcon#flushed, iclass 13, count 2 2006.168.08:09:52.31#ibcon#about to write, iclass 13, count 2 2006.168.08:09:52.31#ibcon#wrote, iclass 13, count 2 2006.168.08:09:52.31#ibcon#about to read 3, iclass 13, count 2 2006.168.08:09:52.33#ibcon#read 3, iclass 13, count 2 2006.168.08:09:52.33#ibcon#about to read 4, iclass 13, count 2 2006.168.08:09:52.33#ibcon#read 4, iclass 13, count 2 2006.168.08:09:52.33#ibcon#about to read 5, iclass 13, count 2 2006.168.08:09:52.33#ibcon#read 5, iclass 13, count 2 2006.168.08:09:52.33#ibcon#about to read 6, iclass 13, count 2 2006.168.08:09:52.33#ibcon#read 6, iclass 13, count 2 2006.168.08:09:52.33#ibcon#end of sib2, iclass 13, count 2 2006.168.08:09:52.33#ibcon#*mode == 0, iclass 13, count 2 2006.168.08:09:52.33#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.168.08:09:52.33#ibcon#[27=AT06-04\r\n] 2006.168.08:09:52.33#ibcon#*before write, iclass 13, count 2 2006.168.08:09:52.33#ibcon#enter sib2, iclass 13, count 2 2006.168.08:09:52.33#ibcon#flushed, iclass 13, count 2 2006.168.08:09:52.33#ibcon#about to write, iclass 13, count 2 2006.168.08:09:52.33#ibcon#wrote, iclass 13, count 2 2006.168.08:09:52.33#ibcon#about to read 3, iclass 13, count 2 2006.168.08:09:52.36#ibcon#read 3, iclass 13, count 2 2006.168.08:09:52.36#ibcon#about to read 4, iclass 13, count 2 2006.168.08:09:52.36#ibcon#read 4, iclass 13, count 2 2006.168.08:09:52.36#ibcon#about to read 5, iclass 13, count 2 2006.168.08:09:52.36#ibcon#read 5, iclass 13, count 2 2006.168.08:09:52.36#ibcon#about to read 6, iclass 13, count 2 2006.168.08:09:52.36#ibcon#read 6, iclass 13, count 2 2006.168.08:09:52.36#ibcon#end of sib2, iclass 13, count 2 2006.168.08:09:52.36#ibcon#*after write, iclass 13, count 2 2006.168.08:09:52.36#ibcon#*before return 0, iclass 13, count 2 2006.168.08:09:52.36#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.168.08:09:52.36#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.168.08:09:52.36#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.168.08:09:52.36#ibcon#ireg 7 cls_cnt 0 2006.168.08:09:52.36#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.168.08:09:52.48#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.168.08:09:52.48#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.168.08:09:52.48#ibcon#enter wrdev, iclass 13, count 0 2006.168.08:09:52.48#ibcon#first serial, iclass 13, count 0 2006.168.08:09:52.48#ibcon#enter sib2, iclass 13, count 0 2006.168.08:09:52.48#ibcon#flushed, iclass 13, count 0 2006.168.08:09:52.48#ibcon#about to write, iclass 13, count 0 2006.168.08:09:52.48#ibcon#wrote, iclass 13, count 0 2006.168.08:09:52.48#ibcon#about to read 3, iclass 13, count 0 2006.168.08:09:52.50#ibcon#read 3, iclass 13, count 0 2006.168.08:09:52.50#ibcon#about to read 4, iclass 13, count 0 2006.168.08:09:52.50#ibcon#read 4, iclass 13, count 0 2006.168.08:09:52.50#ibcon#about to read 5, iclass 13, count 0 2006.168.08:09:52.50#ibcon#read 5, iclass 13, count 0 2006.168.08:09:52.50#ibcon#about to read 6, iclass 13, count 0 2006.168.08:09:52.50#ibcon#read 6, iclass 13, count 0 2006.168.08:09:52.50#ibcon#end of sib2, iclass 13, count 0 2006.168.08:09:52.50#ibcon#*mode == 0, iclass 13, count 0 2006.168.08:09:52.50#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.168.08:09:52.50#ibcon#[27=USB\r\n] 2006.168.08:09:52.50#ibcon#*before write, iclass 13, count 0 2006.168.08:09:52.50#ibcon#enter sib2, iclass 13, count 0 2006.168.08:09:52.50#ibcon#flushed, iclass 13, count 0 2006.168.08:09:52.50#ibcon#about to write, iclass 13, count 0 2006.168.08:09:52.50#ibcon#wrote, iclass 13, count 0 2006.168.08:09:52.50#ibcon#about to read 3, iclass 13, count 0 2006.168.08:09:52.53#ibcon#read 3, iclass 13, count 0 2006.168.08:09:52.53#ibcon#about to read 4, iclass 13, count 0 2006.168.08:09:52.53#ibcon#read 4, iclass 13, count 0 2006.168.08:09:52.53#ibcon#about to read 5, iclass 13, count 0 2006.168.08:09:52.53#ibcon#read 5, iclass 13, count 0 2006.168.08:09:52.53#ibcon#about to read 6, iclass 13, count 0 2006.168.08:09:52.53#ibcon#read 6, iclass 13, count 0 2006.168.08:09:52.53#ibcon#end of sib2, iclass 13, count 0 2006.168.08:09:52.53#ibcon#*after write, iclass 13, count 0 2006.168.08:09:52.53#ibcon#*before return 0, iclass 13, count 0 2006.168.08:09:52.53#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.168.08:09:52.53#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.168.08:09:52.53#ibcon#about to clear, iclass 13 cls_cnt 0 2006.168.08:09:52.53#ibcon#cleared, iclass 13 cls_cnt 0 2006.168.08:09:52.53$vc4f8/vabw=wide 2006.168.08:09:52.53#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.168.08:09:52.53#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.168.08:09:52.53#ibcon#ireg 8 cls_cnt 0 2006.168.08:09:52.53#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:09:52.53#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:09:52.53#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:09:52.53#ibcon#enter wrdev, iclass 15, count 0 2006.168.08:09:52.53#ibcon#first serial, iclass 15, count 0 2006.168.08:09:52.53#ibcon#enter sib2, iclass 15, count 0 2006.168.08:09:52.53#ibcon#flushed, iclass 15, count 0 2006.168.08:09:52.53#ibcon#about to write, iclass 15, count 0 2006.168.08:09:52.53#ibcon#wrote, iclass 15, count 0 2006.168.08:09:52.53#ibcon#about to read 3, iclass 15, count 0 2006.168.08:09:52.55#ibcon#read 3, iclass 15, count 0 2006.168.08:09:52.55#ibcon#about to read 4, iclass 15, count 0 2006.168.08:09:52.55#ibcon#read 4, iclass 15, count 0 2006.168.08:09:52.55#ibcon#about to read 5, iclass 15, count 0 2006.168.08:09:52.55#ibcon#read 5, iclass 15, count 0 2006.168.08:09:52.55#ibcon#about to read 6, iclass 15, count 0 2006.168.08:09:52.55#ibcon#read 6, iclass 15, count 0 2006.168.08:09:52.55#ibcon#end of sib2, iclass 15, count 0 2006.168.08:09:52.55#ibcon#*mode == 0, iclass 15, count 0 2006.168.08:09:52.55#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.168.08:09:52.55#ibcon#[25=BW32\r\n] 2006.168.08:09:52.55#ibcon#*before write, iclass 15, count 0 2006.168.08:09:52.55#ibcon#enter sib2, iclass 15, count 0 2006.168.08:09:52.55#ibcon#flushed, iclass 15, count 0 2006.168.08:09:52.55#ibcon#about to write, iclass 15, count 0 2006.168.08:09:52.55#ibcon#wrote, iclass 15, count 0 2006.168.08:09:52.55#ibcon#about to read 3, iclass 15, count 0 2006.168.08:09:52.58#ibcon#read 3, iclass 15, count 0 2006.168.08:09:52.58#ibcon#about to read 4, iclass 15, count 0 2006.168.08:09:52.58#ibcon#read 4, iclass 15, count 0 2006.168.08:09:52.58#ibcon#about to read 5, iclass 15, count 0 2006.168.08:09:52.58#ibcon#read 5, iclass 15, count 0 2006.168.08:09:52.58#ibcon#about to read 6, iclass 15, count 0 2006.168.08:09:52.58#ibcon#read 6, iclass 15, count 0 2006.168.08:09:52.58#ibcon#end of sib2, iclass 15, count 0 2006.168.08:09:52.58#ibcon#*after write, iclass 15, count 0 2006.168.08:09:52.58#ibcon#*before return 0, iclass 15, count 0 2006.168.08:09:52.58#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:09:52.58#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:09:52.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.168.08:09:52.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.168.08:09:52.58$vc4f8/vbbw=wide 2006.168.08:09:52.58#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.168.08:09:52.58#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.168.08:09:52.58#ibcon#ireg 8 cls_cnt 0 2006.168.08:09:52.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:09:52.65#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:09:52.65#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:09:52.65#ibcon#enter wrdev, iclass 17, count 0 2006.168.08:09:52.65#ibcon#first serial, iclass 17, count 0 2006.168.08:09:52.65#ibcon#enter sib2, iclass 17, count 0 2006.168.08:09:52.65#ibcon#flushed, iclass 17, count 0 2006.168.08:09:52.65#ibcon#about to write, iclass 17, count 0 2006.168.08:09:52.65#ibcon#wrote, iclass 17, count 0 2006.168.08:09:52.65#ibcon#about to read 3, iclass 17, count 0 2006.168.08:09:52.68#ibcon#read 3, iclass 17, count 0 2006.168.08:09:52.68#ibcon#about to read 4, iclass 17, count 0 2006.168.08:09:52.68#ibcon#read 4, iclass 17, count 0 2006.168.08:09:52.68#ibcon#about to read 5, iclass 17, count 0 2006.168.08:09:52.68#ibcon#read 5, iclass 17, count 0 2006.168.08:09:52.68#ibcon#about to read 6, iclass 17, count 0 2006.168.08:09:52.68#ibcon#read 6, iclass 17, count 0 2006.168.08:09:52.68#ibcon#end of sib2, iclass 17, count 0 2006.168.08:09:52.68#ibcon#*mode == 0, iclass 17, count 0 2006.168.08:09:52.68#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.168.08:09:52.68#ibcon#[27=BW32\r\n] 2006.168.08:09:52.68#ibcon#*before write, iclass 17, count 0 2006.168.08:09:52.68#ibcon#enter sib2, iclass 17, count 0 2006.168.08:09:52.68#ibcon#flushed, iclass 17, count 0 2006.168.08:09:52.68#ibcon#about to write, iclass 17, count 0 2006.168.08:09:52.68#ibcon#wrote, iclass 17, count 0 2006.168.08:09:52.68#ibcon#about to read 3, iclass 17, count 0 2006.168.08:09:52.71#ibcon#read 3, iclass 17, count 0 2006.168.08:09:52.71#ibcon#about to read 4, iclass 17, count 0 2006.168.08:09:52.71#ibcon#read 4, iclass 17, count 0 2006.168.08:09:52.71#ibcon#about to read 5, iclass 17, count 0 2006.168.08:09:52.71#ibcon#read 5, iclass 17, count 0 2006.168.08:09:52.71#ibcon#about to read 6, iclass 17, count 0 2006.168.08:09:52.71#ibcon#read 6, iclass 17, count 0 2006.168.08:09:52.71#ibcon#end of sib2, iclass 17, count 0 2006.168.08:09:52.71#ibcon#*after write, iclass 17, count 0 2006.168.08:09:52.71#ibcon#*before return 0, iclass 17, count 0 2006.168.08:09:52.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:09:52.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:09:52.71#ibcon#about to clear, iclass 17 cls_cnt 0 2006.168.08:09:52.71#ibcon#cleared, iclass 17 cls_cnt 0 2006.168.08:09:52.71$4f8m12a/ifd4f 2006.168.08:09:52.71$ifd4f/lo= 2006.168.08:09:52.71$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.08:09:52.71$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.08:09:52.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.08:09:52.71$ifd4f/patch= 2006.168.08:09:52.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.08:09:52.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.08:09:52.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.08:09:52.71$4f8m12a/"form=m,16.000,1:2 2006.168.08:09:52.71$4f8m12a/"tpicd 2006.168.08:09:52.71$4f8m12a/echo=off 2006.168.08:09:52.71$4f8m12a/xlog=off 2006.168.08:09:52.71:!2006.168.08:10:20 2006.168.08:10:01.13#trakl#Source acquired 2006.168.08:10:02.13#flagr#flagr/antenna,acquired 2006.168.08:10:20.00:preob 2006.168.08:10:21.13/onsource/TRACKING 2006.168.08:10:21.13:!2006.168.08:10:30 2006.168.08:10:30.00:data_valid=on 2006.168.08:10:30.00:midob 2006.168.08:10:30.13/onsource/TRACKING 2006.168.08:10:30.13/wx/26.96,1004.5,75 2006.168.08:10:30.24/cable/+6.4705E-03 2006.168.08:10:31.33/va/01,08,usb,yes,29,30 2006.168.08:10:31.33/va/02,07,usb,yes,29,30 2006.168.08:10:31.33/va/03,06,usb,yes,30,31 2006.168.08:10:31.33/va/04,07,usb,yes,30,32 2006.168.08:10:31.33/va/05,07,usb,yes,29,31 2006.168.08:10:31.33/va/06,06,usb,yes,29,28 2006.168.08:10:31.33/va/07,06,usb,yes,29,29 2006.168.08:10:31.33/va/08,07,usb,yes,28,27 2006.168.08:10:31.56/valo/01,532.99,yes,locked 2006.168.08:10:31.56/valo/02,572.99,yes,locked 2006.168.08:10:31.56/valo/03,672.99,yes,locked 2006.168.08:10:31.56/valo/04,832.99,yes,locked 2006.168.08:10:31.56/valo/05,652.99,yes,locked 2006.168.08:10:31.56/valo/06,772.99,yes,locked 2006.168.08:10:31.56/valo/07,832.99,yes,locked 2006.168.08:10:31.56/valo/08,852.99,yes,locked 2006.168.08:10:32.65/vb/01,04,usb,yes,29,28 2006.168.08:10:32.65/vb/02,04,usb,yes,31,32 2006.168.08:10:32.65/vb/03,04,usb,yes,27,31 2006.168.08:10:32.65/vb/04,04,usb,yes,28,28 2006.168.08:10:32.65/vb/05,04,usb,yes,26,30 2006.168.08:10:32.65/vb/06,04,usb,yes,27,30 2006.168.08:10:32.65/vb/07,04,usb,yes,29,29 2006.168.08:10:32.65/vb/08,04,usb,yes,27,30 2006.168.08:10:32.89/vblo/01,632.99,yes,locked 2006.168.08:10:32.89/vblo/02,640.99,yes,locked 2006.168.08:10:32.89/vblo/03,656.99,yes,locked 2006.168.08:10:32.89/vblo/04,712.99,yes,locked 2006.168.08:10:32.89/vblo/05,744.99,yes,locked 2006.168.08:10:32.89/vblo/06,752.99,yes,locked 2006.168.08:10:32.89/vblo/07,734.99,yes,locked 2006.168.08:10:32.89/vblo/08,744.99,yes,locked 2006.168.08:10:33.04/vabw/8 2006.168.08:10:33.19/vbbw/8 2006.168.08:10:33.28/xfe/off,on,15.2 2006.168.08:10:33.67/ifatt/23,28,28,28 2006.168.08:10:34.08/fmout-gps/S +4.19E-07 2006.168.08:10:34.16:!2006.168.08:11:30 2006.168.08:11:30.00:data_valid=off 2006.168.08:11:30.00:postob 2006.168.08:11:30.17/cable/+6.4717E-03 2006.168.08:11:30.17/wx/26.96,1004.6,75 2006.168.08:11:31.08/fmout-gps/S +4.19E-07 2006.168.08:11:31.08:scan_name=168-0812,k06168,60 2006.168.08:11:31.09:source=0748+126,075052.05,123104.8,2000.0,ccw 2006.168.08:11:31.14#flagr#flagr/antenna,new-source 2006.168.08:11:32.14:checkk5 2006.168.08:11:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.168.08:11:32.90/chk_autoobs//k5ts2/ autoobs is running! 2006.168.08:11:33.28/chk_autoobs//k5ts3/ autoobs is running! 2006.168.08:11:33.66/chk_autoobs//k5ts4/ autoobs is running! 2006.168.08:11:34.03/chk_obsdata//k5ts1/T1680810??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.168.08:11:34.39/chk_obsdata//k5ts2/T1680810??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.168.08:11:34.76/chk_obsdata//k5ts3/T1680810??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.168.08:11:35.13/chk_obsdata//k5ts4/T1680810??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.168.08:11:35.83/k5log//k5ts1_log_newline 2006.168.08:11:36.52/k5log//k5ts2_log_newline 2006.168.08:11:37.21/k5log//k5ts3_log_newline 2006.168.08:11:37.90/k5log//k5ts4_log_newline 2006.168.08:11:37.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.08:11:37.92:4f8m12a=2 2006.168.08:11:37.92$4f8m12a/echo=on 2006.168.08:11:37.92$4f8m12a/pcalon 2006.168.08:11:37.92$pcalon/"no phase cal control is implemented here 2006.168.08:11:37.92$4f8m12a/"tpicd=stop 2006.168.08:11:37.92$4f8m12a/vc4f8 2006.168.08:11:37.92$vc4f8/valo=1,532.99 2006.168.08:11:37.92#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.168.08:11:37.92#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.168.08:11:37.92#ibcon#ireg 17 cls_cnt 0 2006.168.08:11:37.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.168.08:11:37.92#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.168.08:11:37.92#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.168.08:11:37.92#ibcon#enter wrdev, iclass 24, count 0 2006.168.08:11:37.92#ibcon#first serial, iclass 24, count 0 2006.168.08:11:37.92#ibcon#enter sib2, iclass 24, count 0 2006.168.08:11:37.92#ibcon#flushed, iclass 24, count 0 2006.168.08:11:37.92#ibcon#about to write, iclass 24, count 0 2006.168.08:11:37.92#ibcon#wrote, iclass 24, count 0 2006.168.08:11:37.92#ibcon#about to read 3, iclass 24, count 0 2006.168.08:11:37.94#ibcon#read 3, iclass 24, count 0 2006.168.08:11:37.94#ibcon#about to read 4, iclass 24, count 0 2006.168.08:11:37.94#ibcon#read 4, iclass 24, count 0 2006.168.08:11:37.94#ibcon#about to read 5, iclass 24, count 0 2006.168.08:11:37.94#ibcon#read 5, iclass 24, count 0 2006.168.08:11:37.94#ibcon#about to read 6, iclass 24, count 0 2006.168.08:11:37.94#ibcon#read 6, iclass 24, count 0 2006.168.08:11:37.94#ibcon#end of sib2, iclass 24, count 0 2006.168.08:11:37.94#ibcon#*mode == 0, iclass 24, count 0 2006.168.08:11:37.94#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.168.08:11:37.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.08:11:37.94#ibcon#*before write, iclass 24, count 0 2006.168.08:11:37.94#ibcon#enter sib2, iclass 24, count 0 2006.168.08:11:37.94#ibcon#flushed, iclass 24, count 0 2006.168.08:11:37.94#ibcon#about to write, iclass 24, count 0 2006.168.08:11:37.94#ibcon#wrote, iclass 24, count 0 2006.168.08:11:37.94#ibcon#about to read 3, iclass 24, count 0 2006.168.08:11:37.99#ibcon#read 3, iclass 24, count 0 2006.168.08:11:37.99#ibcon#about to read 4, iclass 24, count 0 2006.168.08:11:37.99#ibcon#read 4, iclass 24, count 0 2006.168.08:11:37.99#ibcon#about to read 5, iclass 24, count 0 2006.168.08:11:37.99#ibcon#read 5, iclass 24, count 0 2006.168.08:11:37.99#ibcon#about to read 6, iclass 24, count 0 2006.168.08:11:37.99#ibcon#read 6, iclass 24, count 0 2006.168.08:11:37.99#ibcon#end of sib2, iclass 24, count 0 2006.168.08:11:37.99#ibcon#*after write, iclass 24, count 0 2006.168.08:11:37.99#ibcon#*before return 0, iclass 24, count 0 2006.168.08:11:37.99#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.168.08:11:37.99#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.168.08:11:37.99#ibcon#about to clear, iclass 24 cls_cnt 0 2006.168.08:11:37.99#ibcon#cleared, iclass 24 cls_cnt 0 2006.168.08:11:37.99$vc4f8/va=1,8 2006.168.08:11:37.99#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.168.08:11:37.99#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.168.08:11:37.99#ibcon#ireg 11 cls_cnt 2 2006.168.08:11:37.99#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.168.08:11:37.99#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.168.08:11:37.99#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.168.08:11:37.99#ibcon#enter wrdev, iclass 26, count 2 2006.168.08:11:37.99#ibcon#first serial, iclass 26, count 2 2006.168.08:11:37.99#ibcon#enter sib2, iclass 26, count 2 2006.168.08:11:37.99#ibcon#flushed, iclass 26, count 2 2006.168.08:11:37.99#ibcon#about to write, iclass 26, count 2 2006.168.08:11:37.99#ibcon#wrote, iclass 26, count 2 2006.168.08:11:37.99#ibcon#about to read 3, iclass 26, count 2 2006.168.08:11:38.01#ibcon#read 3, iclass 26, count 2 2006.168.08:11:38.01#ibcon#about to read 4, iclass 26, count 2 2006.168.08:11:38.01#ibcon#read 4, iclass 26, count 2 2006.168.08:11:38.01#ibcon#about to read 5, iclass 26, count 2 2006.168.08:11:38.01#ibcon#read 5, iclass 26, count 2 2006.168.08:11:38.01#ibcon#about to read 6, iclass 26, count 2 2006.168.08:11:38.01#ibcon#read 6, iclass 26, count 2 2006.168.08:11:38.01#ibcon#end of sib2, iclass 26, count 2 2006.168.08:11:38.01#ibcon#*mode == 0, iclass 26, count 2 2006.168.08:11:38.01#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.168.08:11:38.01#ibcon#[25=AT01-08\r\n] 2006.168.08:11:38.01#ibcon#*before write, iclass 26, count 2 2006.168.08:11:38.01#ibcon#enter sib2, iclass 26, count 2 2006.168.08:11:38.01#ibcon#flushed, iclass 26, count 2 2006.168.08:11:38.01#ibcon#about to write, iclass 26, count 2 2006.168.08:11:38.01#ibcon#wrote, iclass 26, count 2 2006.168.08:11:38.01#ibcon#about to read 3, iclass 26, count 2 2006.168.08:11:38.04#ibcon#read 3, iclass 26, count 2 2006.168.08:11:38.04#ibcon#about to read 4, iclass 26, count 2 2006.168.08:11:38.04#ibcon#read 4, iclass 26, count 2 2006.168.08:11:38.04#ibcon#about to read 5, iclass 26, count 2 2006.168.08:11:38.04#ibcon#read 5, iclass 26, count 2 2006.168.08:11:38.04#ibcon#about to read 6, iclass 26, count 2 2006.168.08:11:38.04#ibcon#read 6, iclass 26, count 2 2006.168.08:11:38.04#ibcon#end of sib2, iclass 26, count 2 2006.168.08:11:38.04#ibcon#*after write, iclass 26, count 2 2006.168.08:11:38.04#ibcon#*before return 0, iclass 26, count 2 2006.168.08:11:38.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.168.08:11:38.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.168.08:11:38.04#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.168.08:11:38.04#ibcon#ireg 7 cls_cnt 0 2006.168.08:11:38.04#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.168.08:11:38.16#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.168.08:11:38.16#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.168.08:11:38.16#ibcon#enter wrdev, iclass 26, count 0 2006.168.08:11:38.16#ibcon#first serial, iclass 26, count 0 2006.168.08:11:38.16#ibcon#enter sib2, iclass 26, count 0 2006.168.08:11:38.16#ibcon#flushed, iclass 26, count 0 2006.168.08:11:38.16#ibcon#about to write, iclass 26, count 0 2006.168.08:11:38.16#ibcon#wrote, iclass 26, count 0 2006.168.08:11:38.16#ibcon#about to read 3, iclass 26, count 0 2006.168.08:11:38.18#ibcon#read 3, iclass 26, count 0 2006.168.08:11:38.18#ibcon#about to read 4, iclass 26, count 0 2006.168.08:11:38.18#ibcon#read 4, iclass 26, count 0 2006.168.08:11:38.18#ibcon#about to read 5, iclass 26, count 0 2006.168.08:11:38.18#ibcon#read 5, iclass 26, count 0 2006.168.08:11:38.18#ibcon#about to read 6, iclass 26, count 0 2006.168.08:11:38.18#ibcon#read 6, iclass 26, count 0 2006.168.08:11:38.18#ibcon#end of sib2, iclass 26, count 0 2006.168.08:11:38.18#ibcon#*mode == 0, iclass 26, count 0 2006.168.08:11:38.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.168.08:11:38.18#ibcon#[25=USB\r\n] 2006.168.08:11:38.18#ibcon#*before write, iclass 26, count 0 2006.168.08:11:38.18#ibcon#enter sib2, iclass 26, count 0 2006.168.08:11:38.18#ibcon#flushed, iclass 26, count 0 2006.168.08:11:38.18#ibcon#about to write, iclass 26, count 0 2006.168.08:11:38.18#ibcon#wrote, iclass 26, count 0 2006.168.08:11:38.18#ibcon#about to read 3, iclass 26, count 0 2006.168.08:11:38.21#ibcon#read 3, iclass 26, count 0 2006.168.08:11:38.21#ibcon#about to read 4, iclass 26, count 0 2006.168.08:11:38.21#ibcon#read 4, iclass 26, count 0 2006.168.08:11:38.21#ibcon#about to read 5, iclass 26, count 0 2006.168.08:11:38.21#ibcon#read 5, iclass 26, count 0 2006.168.08:11:38.21#ibcon#about to read 6, iclass 26, count 0 2006.168.08:11:38.21#ibcon#read 6, iclass 26, count 0 2006.168.08:11:38.21#ibcon#end of sib2, iclass 26, count 0 2006.168.08:11:38.21#ibcon#*after write, iclass 26, count 0 2006.168.08:11:38.21#ibcon#*before return 0, iclass 26, count 0 2006.168.08:11:38.21#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.168.08:11:38.21#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.168.08:11:38.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.168.08:11:38.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.168.08:11:38.21$vc4f8/valo=2,572.99 2006.168.08:11:38.21#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.168.08:11:38.21#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.168.08:11:38.21#ibcon#ireg 17 cls_cnt 0 2006.168.08:11:38.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.168.08:11:38.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.168.08:11:38.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.168.08:11:38.21#ibcon#enter wrdev, iclass 28, count 0 2006.168.08:11:38.21#ibcon#first serial, iclass 28, count 0 2006.168.08:11:38.21#ibcon#enter sib2, iclass 28, count 0 2006.168.08:11:38.21#ibcon#flushed, iclass 28, count 0 2006.168.08:11:38.21#ibcon#about to write, iclass 28, count 0 2006.168.08:11:38.21#ibcon#wrote, iclass 28, count 0 2006.168.08:11:38.21#ibcon#about to read 3, iclass 28, count 0 2006.168.08:11:38.23#ibcon#read 3, iclass 28, count 0 2006.168.08:11:38.23#ibcon#about to read 4, iclass 28, count 0 2006.168.08:11:38.23#ibcon#read 4, iclass 28, count 0 2006.168.08:11:38.23#ibcon#about to read 5, iclass 28, count 0 2006.168.08:11:38.23#ibcon#read 5, iclass 28, count 0 2006.168.08:11:38.23#ibcon#about to read 6, iclass 28, count 0 2006.168.08:11:38.23#ibcon#read 6, iclass 28, count 0 2006.168.08:11:38.23#ibcon#end of sib2, iclass 28, count 0 2006.168.08:11:38.23#ibcon#*mode == 0, iclass 28, count 0 2006.168.08:11:38.23#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.168.08:11:38.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.08:11:38.23#ibcon#*before write, iclass 28, count 0 2006.168.08:11:38.23#ibcon#enter sib2, iclass 28, count 0 2006.168.08:11:38.23#ibcon#flushed, iclass 28, count 0 2006.168.08:11:38.23#ibcon#about to write, iclass 28, count 0 2006.168.08:11:38.23#ibcon#wrote, iclass 28, count 0 2006.168.08:11:38.23#ibcon#about to read 3, iclass 28, count 0 2006.168.08:11:38.27#ibcon#read 3, iclass 28, count 0 2006.168.08:11:38.27#ibcon#about to read 4, iclass 28, count 0 2006.168.08:11:38.27#ibcon#read 4, iclass 28, count 0 2006.168.08:11:38.27#ibcon#about to read 5, iclass 28, count 0 2006.168.08:11:38.27#ibcon#read 5, iclass 28, count 0 2006.168.08:11:38.27#ibcon#about to read 6, iclass 28, count 0 2006.168.08:11:38.27#ibcon#read 6, iclass 28, count 0 2006.168.08:11:38.27#ibcon#end of sib2, iclass 28, count 0 2006.168.08:11:38.27#ibcon#*after write, iclass 28, count 0 2006.168.08:11:38.27#ibcon#*before return 0, iclass 28, count 0 2006.168.08:11:38.27#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.168.08:11:38.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.168.08:11:38.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.168.08:11:38.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.168.08:11:38.27$vc4f8/va=2,7 2006.168.08:11:38.27#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.168.08:11:38.27#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.168.08:11:38.27#ibcon#ireg 11 cls_cnt 2 2006.168.08:11:38.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.168.08:11:38.33#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.168.08:11:38.33#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.168.08:11:38.33#ibcon#enter wrdev, iclass 30, count 2 2006.168.08:11:38.33#ibcon#first serial, iclass 30, count 2 2006.168.08:11:38.33#ibcon#enter sib2, iclass 30, count 2 2006.168.08:11:38.33#ibcon#flushed, iclass 30, count 2 2006.168.08:11:38.33#ibcon#about to write, iclass 30, count 2 2006.168.08:11:38.33#ibcon#wrote, iclass 30, count 2 2006.168.08:11:38.33#ibcon#about to read 3, iclass 30, count 2 2006.168.08:11:38.35#ibcon#read 3, iclass 30, count 2 2006.168.08:11:38.35#ibcon#about to read 4, iclass 30, count 2 2006.168.08:11:38.35#ibcon#read 4, iclass 30, count 2 2006.168.08:11:38.35#ibcon#about to read 5, iclass 30, count 2 2006.168.08:11:38.35#ibcon#read 5, iclass 30, count 2 2006.168.08:11:38.35#ibcon#about to read 6, iclass 30, count 2 2006.168.08:11:38.35#ibcon#read 6, iclass 30, count 2 2006.168.08:11:38.35#ibcon#end of sib2, iclass 30, count 2 2006.168.08:11:38.35#ibcon#*mode == 0, iclass 30, count 2 2006.168.08:11:38.35#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.168.08:11:38.35#ibcon#[25=AT02-07\r\n] 2006.168.08:11:38.35#ibcon#*before write, iclass 30, count 2 2006.168.08:11:38.35#ibcon#enter sib2, iclass 30, count 2 2006.168.08:11:38.35#ibcon#flushed, iclass 30, count 2 2006.168.08:11:38.35#ibcon#about to write, iclass 30, count 2 2006.168.08:11:38.35#ibcon#wrote, iclass 30, count 2 2006.168.08:11:38.35#ibcon#about to read 3, iclass 30, count 2 2006.168.08:11:38.38#ibcon#read 3, iclass 30, count 2 2006.168.08:11:38.38#ibcon#about to read 4, iclass 30, count 2 2006.168.08:11:38.38#ibcon#read 4, iclass 30, count 2 2006.168.08:11:38.38#ibcon#about to read 5, iclass 30, count 2 2006.168.08:11:38.38#ibcon#read 5, iclass 30, count 2 2006.168.08:11:38.38#ibcon#about to read 6, iclass 30, count 2 2006.168.08:11:38.38#ibcon#read 6, iclass 30, count 2 2006.168.08:11:38.38#ibcon#end of sib2, iclass 30, count 2 2006.168.08:11:38.38#ibcon#*after write, iclass 30, count 2 2006.168.08:11:38.38#ibcon#*before return 0, iclass 30, count 2 2006.168.08:11:38.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.168.08:11:38.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.168.08:11:38.38#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.168.08:11:38.38#ibcon#ireg 7 cls_cnt 0 2006.168.08:11:38.38#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.168.08:11:38.50#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.168.08:11:38.50#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.168.08:11:38.50#ibcon#enter wrdev, iclass 30, count 0 2006.168.08:11:38.50#ibcon#first serial, iclass 30, count 0 2006.168.08:11:38.50#ibcon#enter sib2, iclass 30, count 0 2006.168.08:11:38.50#ibcon#flushed, iclass 30, count 0 2006.168.08:11:38.50#ibcon#about to write, iclass 30, count 0 2006.168.08:11:38.50#ibcon#wrote, iclass 30, count 0 2006.168.08:11:38.50#ibcon#about to read 3, iclass 30, count 0 2006.168.08:11:38.52#ibcon#read 3, iclass 30, count 0 2006.168.08:11:38.52#ibcon#about to read 4, iclass 30, count 0 2006.168.08:11:38.52#ibcon#read 4, iclass 30, count 0 2006.168.08:11:38.52#ibcon#about to read 5, iclass 30, count 0 2006.168.08:11:38.52#ibcon#read 5, iclass 30, count 0 2006.168.08:11:38.52#ibcon#about to read 6, iclass 30, count 0 2006.168.08:11:38.52#ibcon#read 6, iclass 30, count 0 2006.168.08:11:38.52#ibcon#end of sib2, iclass 30, count 0 2006.168.08:11:38.52#ibcon#*mode == 0, iclass 30, count 0 2006.168.08:11:38.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.168.08:11:38.52#ibcon#[25=USB\r\n] 2006.168.08:11:38.52#ibcon#*before write, iclass 30, count 0 2006.168.08:11:38.52#ibcon#enter sib2, iclass 30, count 0 2006.168.08:11:38.52#ibcon#flushed, iclass 30, count 0 2006.168.08:11:38.52#ibcon#about to write, iclass 30, count 0 2006.168.08:11:38.52#ibcon#wrote, iclass 30, count 0 2006.168.08:11:38.52#ibcon#about to read 3, iclass 30, count 0 2006.168.08:11:38.55#ibcon#read 3, iclass 30, count 0 2006.168.08:11:38.55#ibcon#about to read 4, iclass 30, count 0 2006.168.08:11:38.55#ibcon#read 4, iclass 30, count 0 2006.168.08:11:38.55#ibcon#about to read 5, iclass 30, count 0 2006.168.08:11:38.55#ibcon#read 5, iclass 30, count 0 2006.168.08:11:38.55#ibcon#about to read 6, iclass 30, count 0 2006.168.08:11:38.55#ibcon#read 6, iclass 30, count 0 2006.168.08:11:38.55#ibcon#end of sib2, iclass 30, count 0 2006.168.08:11:38.55#ibcon#*after write, iclass 30, count 0 2006.168.08:11:38.55#ibcon#*before return 0, iclass 30, count 0 2006.168.08:11:38.55#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.168.08:11:38.55#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.168.08:11:38.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.168.08:11:38.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.168.08:11:38.55$vc4f8/valo=3,672.99 2006.168.08:11:38.55#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.168.08:11:38.55#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.168.08:11:38.55#ibcon#ireg 17 cls_cnt 0 2006.168.08:11:38.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:11:38.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:11:38.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:11:38.55#ibcon#enter wrdev, iclass 32, count 0 2006.168.08:11:38.55#ibcon#first serial, iclass 32, count 0 2006.168.08:11:38.55#ibcon#enter sib2, iclass 32, count 0 2006.168.08:11:38.55#ibcon#flushed, iclass 32, count 0 2006.168.08:11:38.55#ibcon#about to write, iclass 32, count 0 2006.168.08:11:38.55#ibcon#wrote, iclass 32, count 0 2006.168.08:11:38.55#ibcon#about to read 3, iclass 32, count 0 2006.168.08:11:38.57#ibcon#read 3, iclass 32, count 0 2006.168.08:11:38.57#ibcon#about to read 4, iclass 32, count 0 2006.168.08:11:38.57#ibcon#read 4, iclass 32, count 0 2006.168.08:11:38.57#ibcon#about to read 5, iclass 32, count 0 2006.168.08:11:38.57#ibcon#read 5, iclass 32, count 0 2006.168.08:11:38.57#ibcon#about to read 6, iclass 32, count 0 2006.168.08:11:38.57#ibcon#read 6, iclass 32, count 0 2006.168.08:11:38.57#ibcon#end of sib2, iclass 32, count 0 2006.168.08:11:38.57#ibcon#*mode == 0, iclass 32, count 0 2006.168.08:11:38.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.168.08:11:38.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.08:11:38.57#ibcon#*before write, iclass 32, count 0 2006.168.08:11:38.57#ibcon#enter sib2, iclass 32, count 0 2006.168.08:11:38.57#ibcon#flushed, iclass 32, count 0 2006.168.08:11:38.57#ibcon#about to write, iclass 32, count 0 2006.168.08:11:38.57#ibcon#wrote, iclass 32, count 0 2006.168.08:11:38.57#ibcon#about to read 3, iclass 32, count 0 2006.168.08:11:38.61#ibcon#read 3, iclass 32, count 0 2006.168.08:11:38.61#ibcon#about to read 4, iclass 32, count 0 2006.168.08:11:38.61#ibcon#read 4, iclass 32, count 0 2006.168.08:11:38.61#ibcon#about to read 5, iclass 32, count 0 2006.168.08:11:38.61#ibcon#read 5, iclass 32, count 0 2006.168.08:11:38.61#ibcon#about to read 6, iclass 32, count 0 2006.168.08:11:38.61#ibcon#read 6, iclass 32, count 0 2006.168.08:11:38.61#ibcon#end of sib2, iclass 32, count 0 2006.168.08:11:38.61#ibcon#*after write, iclass 32, count 0 2006.168.08:11:38.61#ibcon#*before return 0, iclass 32, count 0 2006.168.08:11:38.61#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:11:38.61#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:11:38.61#ibcon#about to clear, iclass 32 cls_cnt 0 2006.168.08:11:38.61#ibcon#cleared, iclass 32 cls_cnt 0 2006.168.08:11:38.61$vc4f8/va=3,6 2006.168.08:11:38.61#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.168.08:11:38.61#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.168.08:11:38.61#ibcon#ireg 11 cls_cnt 2 2006.168.08:11:38.61#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.168.08:11:38.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.168.08:11:38.68#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.168.08:11:38.68#ibcon#enter wrdev, iclass 34, count 2 2006.168.08:11:38.68#ibcon#first serial, iclass 34, count 2 2006.168.08:11:38.68#ibcon#enter sib2, iclass 34, count 2 2006.168.08:11:38.68#ibcon#flushed, iclass 34, count 2 2006.168.08:11:38.68#ibcon#about to write, iclass 34, count 2 2006.168.08:11:38.68#ibcon#wrote, iclass 34, count 2 2006.168.08:11:38.68#ibcon#about to read 3, iclass 34, count 2 2006.168.08:11:38.69#ibcon#read 3, iclass 34, count 2 2006.168.08:11:38.69#ibcon#about to read 4, iclass 34, count 2 2006.168.08:11:38.69#ibcon#read 4, iclass 34, count 2 2006.168.08:11:38.69#ibcon#about to read 5, iclass 34, count 2 2006.168.08:11:38.69#ibcon#read 5, iclass 34, count 2 2006.168.08:11:38.69#ibcon#about to read 6, iclass 34, count 2 2006.168.08:11:38.69#ibcon#read 6, iclass 34, count 2 2006.168.08:11:38.69#ibcon#end of sib2, iclass 34, count 2 2006.168.08:11:38.69#ibcon#*mode == 0, iclass 34, count 2 2006.168.08:11:38.69#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.168.08:11:38.69#ibcon#[25=AT03-06\r\n] 2006.168.08:11:38.69#ibcon#*before write, iclass 34, count 2 2006.168.08:11:38.69#ibcon#enter sib2, iclass 34, count 2 2006.168.08:11:38.69#ibcon#flushed, iclass 34, count 2 2006.168.08:11:38.69#ibcon#about to write, iclass 34, count 2 2006.168.08:11:38.69#ibcon#wrote, iclass 34, count 2 2006.168.08:11:38.69#ibcon#about to read 3, iclass 34, count 2 2006.168.08:11:38.72#ibcon#read 3, iclass 34, count 2 2006.168.08:11:38.72#ibcon#about to read 4, iclass 34, count 2 2006.168.08:11:38.72#ibcon#read 4, iclass 34, count 2 2006.168.08:11:38.72#ibcon#about to read 5, iclass 34, count 2 2006.168.08:11:38.72#ibcon#read 5, iclass 34, count 2 2006.168.08:11:38.72#ibcon#about to read 6, iclass 34, count 2 2006.168.08:11:38.72#ibcon#read 6, iclass 34, count 2 2006.168.08:11:38.72#ibcon#end of sib2, iclass 34, count 2 2006.168.08:11:38.72#ibcon#*after write, iclass 34, count 2 2006.168.08:11:38.72#ibcon#*before return 0, iclass 34, count 2 2006.168.08:11:38.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.168.08:11:38.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.168.08:11:38.72#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.168.08:11:38.72#ibcon#ireg 7 cls_cnt 0 2006.168.08:11:38.72#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.168.08:11:38.84#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.168.08:11:38.84#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.168.08:11:38.84#ibcon#enter wrdev, iclass 34, count 0 2006.168.08:11:38.84#ibcon#first serial, iclass 34, count 0 2006.168.08:11:38.84#ibcon#enter sib2, iclass 34, count 0 2006.168.08:11:38.84#ibcon#flushed, iclass 34, count 0 2006.168.08:11:38.84#ibcon#about to write, iclass 34, count 0 2006.168.08:11:38.84#ibcon#wrote, iclass 34, count 0 2006.168.08:11:38.84#ibcon#about to read 3, iclass 34, count 0 2006.168.08:11:38.86#ibcon#read 3, iclass 34, count 0 2006.168.08:11:38.86#ibcon#about to read 4, iclass 34, count 0 2006.168.08:11:38.86#ibcon#read 4, iclass 34, count 0 2006.168.08:11:38.86#ibcon#about to read 5, iclass 34, count 0 2006.168.08:11:38.86#ibcon#read 5, iclass 34, count 0 2006.168.08:11:38.86#ibcon#about to read 6, iclass 34, count 0 2006.168.08:11:38.86#ibcon#read 6, iclass 34, count 0 2006.168.08:11:38.86#ibcon#end of sib2, iclass 34, count 0 2006.168.08:11:38.86#ibcon#*mode == 0, iclass 34, count 0 2006.168.08:11:38.86#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.168.08:11:38.86#ibcon#[25=USB\r\n] 2006.168.08:11:38.86#ibcon#*before write, iclass 34, count 0 2006.168.08:11:38.86#ibcon#enter sib2, iclass 34, count 0 2006.168.08:11:38.86#ibcon#flushed, iclass 34, count 0 2006.168.08:11:38.86#ibcon#about to write, iclass 34, count 0 2006.168.08:11:38.86#ibcon#wrote, iclass 34, count 0 2006.168.08:11:38.86#ibcon#about to read 3, iclass 34, count 0 2006.168.08:11:38.89#ibcon#read 3, iclass 34, count 0 2006.168.08:11:38.89#ibcon#about to read 4, iclass 34, count 0 2006.168.08:11:38.89#ibcon#read 4, iclass 34, count 0 2006.168.08:11:38.89#ibcon#about to read 5, iclass 34, count 0 2006.168.08:11:38.89#ibcon#read 5, iclass 34, count 0 2006.168.08:11:38.89#ibcon#about to read 6, iclass 34, count 0 2006.168.08:11:38.89#ibcon#read 6, iclass 34, count 0 2006.168.08:11:38.89#ibcon#end of sib2, iclass 34, count 0 2006.168.08:11:38.89#ibcon#*after write, iclass 34, count 0 2006.168.08:11:38.89#ibcon#*before return 0, iclass 34, count 0 2006.168.08:11:38.89#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.168.08:11:38.89#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.168.08:11:38.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.168.08:11:38.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.168.08:11:38.89$vc4f8/valo=4,832.99 2006.168.08:11:38.89#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.168.08:11:38.89#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.168.08:11:38.89#ibcon#ireg 17 cls_cnt 0 2006.168.08:11:38.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.168.08:11:38.89#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.168.08:11:38.89#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.168.08:11:38.89#ibcon#enter wrdev, iclass 36, count 0 2006.168.08:11:38.89#ibcon#first serial, iclass 36, count 0 2006.168.08:11:38.89#ibcon#enter sib2, iclass 36, count 0 2006.168.08:11:38.89#ibcon#flushed, iclass 36, count 0 2006.168.08:11:38.89#ibcon#about to write, iclass 36, count 0 2006.168.08:11:38.89#ibcon#wrote, iclass 36, count 0 2006.168.08:11:38.89#ibcon#about to read 3, iclass 36, count 0 2006.168.08:11:38.91#ibcon#read 3, iclass 36, count 0 2006.168.08:11:38.91#ibcon#about to read 4, iclass 36, count 0 2006.168.08:11:38.91#ibcon#read 4, iclass 36, count 0 2006.168.08:11:38.91#ibcon#about to read 5, iclass 36, count 0 2006.168.08:11:38.91#ibcon#read 5, iclass 36, count 0 2006.168.08:11:38.91#ibcon#about to read 6, iclass 36, count 0 2006.168.08:11:38.91#ibcon#read 6, iclass 36, count 0 2006.168.08:11:38.91#ibcon#end of sib2, iclass 36, count 0 2006.168.08:11:38.91#ibcon#*mode == 0, iclass 36, count 0 2006.168.08:11:38.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.168.08:11:38.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.08:11:38.91#ibcon#*before write, iclass 36, count 0 2006.168.08:11:38.91#ibcon#enter sib2, iclass 36, count 0 2006.168.08:11:38.91#ibcon#flushed, iclass 36, count 0 2006.168.08:11:38.91#ibcon#about to write, iclass 36, count 0 2006.168.08:11:38.91#ibcon#wrote, iclass 36, count 0 2006.168.08:11:38.91#ibcon#about to read 3, iclass 36, count 0 2006.168.08:11:38.95#ibcon#read 3, iclass 36, count 0 2006.168.08:11:38.95#ibcon#about to read 4, iclass 36, count 0 2006.168.08:11:38.95#ibcon#read 4, iclass 36, count 0 2006.168.08:11:38.95#ibcon#about to read 5, iclass 36, count 0 2006.168.08:11:38.95#ibcon#read 5, iclass 36, count 0 2006.168.08:11:38.95#ibcon#about to read 6, iclass 36, count 0 2006.168.08:11:38.95#ibcon#read 6, iclass 36, count 0 2006.168.08:11:38.95#ibcon#end of sib2, iclass 36, count 0 2006.168.08:11:38.95#ibcon#*after write, iclass 36, count 0 2006.168.08:11:38.95#ibcon#*before return 0, iclass 36, count 0 2006.168.08:11:38.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.168.08:11:38.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.168.08:11:38.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.168.08:11:38.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.168.08:11:38.95$vc4f8/va=4,7 2006.168.08:11:38.95#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.168.08:11:38.95#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.168.08:11:38.95#ibcon#ireg 11 cls_cnt 2 2006.168.08:11:38.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.168.08:11:39.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.168.08:11:39.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.168.08:11:39.01#ibcon#enter wrdev, iclass 38, count 2 2006.168.08:11:39.01#ibcon#first serial, iclass 38, count 2 2006.168.08:11:39.01#ibcon#enter sib2, iclass 38, count 2 2006.168.08:11:39.01#ibcon#flushed, iclass 38, count 2 2006.168.08:11:39.01#ibcon#about to write, iclass 38, count 2 2006.168.08:11:39.01#ibcon#wrote, iclass 38, count 2 2006.168.08:11:39.01#ibcon#about to read 3, iclass 38, count 2 2006.168.08:11:39.03#ibcon#read 3, iclass 38, count 2 2006.168.08:11:39.03#ibcon#about to read 4, iclass 38, count 2 2006.168.08:11:39.03#ibcon#read 4, iclass 38, count 2 2006.168.08:11:39.03#ibcon#about to read 5, iclass 38, count 2 2006.168.08:11:39.03#ibcon#read 5, iclass 38, count 2 2006.168.08:11:39.03#ibcon#about to read 6, iclass 38, count 2 2006.168.08:11:39.03#ibcon#read 6, iclass 38, count 2 2006.168.08:11:39.03#ibcon#end of sib2, iclass 38, count 2 2006.168.08:11:39.03#ibcon#*mode == 0, iclass 38, count 2 2006.168.08:11:39.03#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.168.08:11:39.03#ibcon#[25=AT04-07\r\n] 2006.168.08:11:39.03#ibcon#*before write, iclass 38, count 2 2006.168.08:11:39.03#ibcon#enter sib2, iclass 38, count 2 2006.168.08:11:39.03#ibcon#flushed, iclass 38, count 2 2006.168.08:11:39.03#ibcon#about to write, iclass 38, count 2 2006.168.08:11:39.03#ibcon#wrote, iclass 38, count 2 2006.168.08:11:39.03#ibcon#about to read 3, iclass 38, count 2 2006.168.08:11:39.06#ibcon#read 3, iclass 38, count 2 2006.168.08:11:39.06#ibcon#about to read 4, iclass 38, count 2 2006.168.08:11:39.06#ibcon#read 4, iclass 38, count 2 2006.168.08:11:39.06#ibcon#about to read 5, iclass 38, count 2 2006.168.08:11:39.06#ibcon#read 5, iclass 38, count 2 2006.168.08:11:39.06#ibcon#about to read 6, iclass 38, count 2 2006.168.08:11:39.06#ibcon#read 6, iclass 38, count 2 2006.168.08:11:39.06#ibcon#end of sib2, iclass 38, count 2 2006.168.08:11:39.06#ibcon#*after write, iclass 38, count 2 2006.168.08:11:39.06#ibcon#*before return 0, iclass 38, count 2 2006.168.08:11:39.06#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.168.08:11:39.06#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.168.08:11:39.06#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.168.08:11:39.06#ibcon#ireg 7 cls_cnt 0 2006.168.08:11:39.06#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.168.08:11:39.18#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.168.08:11:39.18#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.168.08:11:39.18#ibcon#enter wrdev, iclass 38, count 0 2006.168.08:11:39.18#ibcon#first serial, iclass 38, count 0 2006.168.08:11:39.18#ibcon#enter sib2, iclass 38, count 0 2006.168.08:11:39.18#ibcon#flushed, iclass 38, count 0 2006.168.08:11:39.18#ibcon#about to write, iclass 38, count 0 2006.168.08:11:39.18#ibcon#wrote, iclass 38, count 0 2006.168.08:11:39.18#ibcon#about to read 3, iclass 38, count 0 2006.168.08:11:39.20#ibcon#read 3, iclass 38, count 0 2006.168.08:11:39.20#ibcon#about to read 4, iclass 38, count 0 2006.168.08:11:39.20#ibcon#read 4, iclass 38, count 0 2006.168.08:11:39.20#ibcon#about to read 5, iclass 38, count 0 2006.168.08:11:39.20#ibcon#read 5, iclass 38, count 0 2006.168.08:11:39.20#ibcon#about to read 6, iclass 38, count 0 2006.168.08:11:39.20#ibcon#read 6, iclass 38, count 0 2006.168.08:11:39.20#ibcon#end of sib2, iclass 38, count 0 2006.168.08:11:39.20#ibcon#*mode == 0, iclass 38, count 0 2006.168.08:11:39.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.168.08:11:39.20#ibcon#[25=USB\r\n] 2006.168.08:11:39.20#ibcon#*before write, iclass 38, count 0 2006.168.08:11:39.20#ibcon#enter sib2, iclass 38, count 0 2006.168.08:11:39.20#ibcon#flushed, iclass 38, count 0 2006.168.08:11:39.20#ibcon#about to write, iclass 38, count 0 2006.168.08:11:39.20#ibcon#wrote, iclass 38, count 0 2006.168.08:11:39.20#ibcon#about to read 3, iclass 38, count 0 2006.168.08:11:39.23#ibcon#read 3, iclass 38, count 0 2006.168.08:11:39.23#ibcon#about to read 4, iclass 38, count 0 2006.168.08:11:39.23#ibcon#read 4, iclass 38, count 0 2006.168.08:11:39.23#ibcon#about to read 5, iclass 38, count 0 2006.168.08:11:39.23#ibcon#read 5, iclass 38, count 0 2006.168.08:11:39.23#ibcon#about to read 6, iclass 38, count 0 2006.168.08:11:39.23#ibcon#read 6, iclass 38, count 0 2006.168.08:11:39.23#ibcon#end of sib2, iclass 38, count 0 2006.168.08:11:39.23#ibcon#*after write, iclass 38, count 0 2006.168.08:11:39.23#ibcon#*before return 0, iclass 38, count 0 2006.168.08:11:39.23#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.168.08:11:39.23#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.168.08:11:39.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.168.08:11:39.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.168.08:11:39.23$vc4f8/valo=5,652.99 2006.168.08:11:39.23#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.168.08:11:39.23#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.168.08:11:39.23#ibcon#ireg 17 cls_cnt 0 2006.168.08:11:39.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:11:39.23#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:11:39.23#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:11:39.23#ibcon#enter wrdev, iclass 40, count 0 2006.168.08:11:39.23#ibcon#first serial, iclass 40, count 0 2006.168.08:11:39.23#ibcon#enter sib2, iclass 40, count 0 2006.168.08:11:39.23#ibcon#flushed, iclass 40, count 0 2006.168.08:11:39.23#ibcon#about to write, iclass 40, count 0 2006.168.08:11:39.23#ibcon#wrote, iclass 40, count 0 2006.168.08:11:39.23#ibcon#about to read 3, iclass 40, count 0 2006.168.08:11:39.25#ibcon#read 3, iclass 40, count 0 2006.168.08:11:39.25#ibcon#about to read 4, iclass 40, count 0 2006.168.08:11:39.25#ibcon#read 4, iclass 40, count 0 2006.168.08:11:39.25#ibcon#about to read 5, iclass 40, count 0 2006.168.08:11:39.25#ibcon#read 5, iclass 40, count 0 2006.168.08:11:39.25#ibcon#about to read 6, iclass 40, count 0 2006.168.08:11:39.25#ibcon#read 6, iclass 40, count 0 2006.168.08:11:39.25#ibcon#end of sib2, iclass 40, count 0 2006.168.08:11:39.25#ibcon#*mode == 0, iclass 40, count 0 2006.168.08:11:39.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.168.08:11:39.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.08:11:39.25#ibcon#*before write, iclass 40, count 0 2006.168.08:11:39.25#ibcon#enter sib2, iclass 40, count 0 2006.168.08:11:39.25#ibcon#flushed, iclass 40, count 0 2006.168.08:11:39.25#ibcon#about to write, iclass 40, count 0 2006.168.08:11:39.25#ibcon#wrote, iclass 40, count 0 2006.168.08:11:39.25#ibcon#about to read 3, iclass 40, count 0 2006.168.08:11:39.29#ibcon#read 3, iclass 40, count 0 2006.168.08:11:39.29#ibcon#about to read 4, iclass 40, count 0 2006.168.08:11:39.29#ibcon#read 4, iclass 40, count 0 2006.168.08:11:39.29#ibcon#about to read 5, iclass 40, count 0 2006.168.08:11:39.29#ibcon#read 5, iclass 40, count 0 2006.168.08:11:39.29#ibcon#about to read 6, iclass 40, count 0 2006.168.08:11:39.29#ibcon#read 6, iclass 40, count 0 2006.168.08:11:39.29#ibcon#end of sib2, iclass 40, count 0 2006.168.08:11:39.29#ibcon#*after write, iclass 40, count 0 2006.168.08:11:39.29#ibcon#*before return 0, iclass 40, count 0 2006.168.08:11:39.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:11:39.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:11:39.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.168.08:11:39.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.168.08:11:39.29$vc4f8/va=5,7 2006.168.08:11:39.29#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.168.08:11:39.29#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.168.08:11:39.29#ibcon#ireg 11 cls_cnt 2 2006.168.08:11:39.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.168.08:11:39.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.168.08:11:39.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.168.08:11:39.35#ibcon#enter wrdev, iclass 4, count 2 2006.168.08:11:39.35#ibcon#first serial, iclass 4, count 2 2006.168.08:11:39.35#ibcon#enter sib2, iclass 4, count 2 2006.168.08:11:39.35#ibcon#flushed, iclass 4, count 2 2006.168.08:11:39.35#ibcon#about to write, iclass 4, count 2 2006.168.08:11:39.35#ibcon#wrote, iclass 4, count 2 2006.168.08:11:39.35#ibcon#about to read 3, iclass 4, count 2 2006.168.08:11:39.37#ibcon#read 3, iclass 4, count 2 2006.168.08:11:39.37#ibcon#about to read 4, iclass 4, count 2 2006.168.08:11:39.37#ibcon#read 4, iclass 4, count 2 2006.168.08:11:39.37#ibcon#about to read 5, iclass 4, count 2 2006.168.08:11:39.37#ibcon#read 5, iclass 4, count 2 2006.168.08:11:39.37#ibcon#about to read 6, iclass 4, count 2 2006.168.08:11:39.37#ibcon#read 6, iclass 4, count 2 2006.168.08:11:39.37#ibcon#end of sib2, iclass 4, count 2 2006.168.08:11:39.37#ibcon#*mode == 0, iclass 4, count 2 2006.168.08:11:39.37#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.168.08:11:39.37#ibcon#[25=AT05-07\r\n] 2006.168.08:11:39.37#ibcon#*before write, iclass 4, count 2 2006.168.08:11:39.37#ibcon#enter sib2, iclass 4, count 2 2006.168.08:11:39.37#ibcon#flushed, iclass 4, count 2 2006.168.08:11:39.37#ibcon#about to write, iclass 4, count 2 2006.168.08:11:39.37#ibcon#wrote, iclass 4, count 2 2006.168.08:11:39.37#ibcon#about to read 3, iclass 4, count 2 2006.168.08:11:39.40#ibcon#read 3, iclass 4, count 2 2006.168.08:11:39.40#ibcon#about to read 4, iclass 4, count 2 2006.168.08:11:39.40#ibcon#read 4, iclass 4, count 2 2006.168.08:11:39.40#ibcon#about to read 5, iclass 4, count 2 2006.168.08:11:39.40#ibcon#read 5, iclass 4, count 2 2006.168.08:11:39.40#ibcon#about to read 6, iclass 4, count 2 2006.168.08:11:39.40#ibcon#read 6, iclass 4, count 2 2006.168.08:11:39.40#ibcon#end of sib2, iclass 4, count 2 2006.168.08:11:39.40#ibcon#*after write, iclass 4, count 2 2006.168.08:11:39.40#ibcon#*before return 0, iclass 4, count 2 2006.168.08:11:39.40#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.168.08:11:39.40#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.168.08:11:39.40#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.168.08:11:39.40#ibcon#ireg 7 cls_cnt 0 2006.168.08:11:39.40#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.168.08:11:39.52#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.168.08:11:39.52#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.168.08:11:39.52#ibcon#enter wrdev, iclass 4, count 0 2006.168.08:11:39.52#ibcon#first serial, iclass 4, count 0 2006.168.08:11:39.52#ibcon#enter sib2, iclass 4, count 0 2006.168.08:11:39.52#ibcon#flushed, iclass 4, count 0 2006.168.08:11:39.52#ibcon#about to write, iclass 4, count 0 2006.168.08:11:39.52#ibcon#wrote, iclass 4, count 0 2006.168.08:11:39.52#ibcon#about to read 3, iclass 4, count 0 2006.168.08:11:39.54#ibcon#read 3, iclass 4, count 0 2006.168.08:11:39.54#ibcon#about to read 4, iclass 4, count 0 2006.168.08:11:39.54#ibcon#read 4, iclass 4, count 0 2006.168.08:11:39.54#ibcon#about to read 5, iclass 4, count 0 2006.168.08:11:39.54#ibcon#read 5, iclass 4, count 0 2006.168.08:11:39.54#ibcon#about to read 6, iclass 4, count 0 2006.168.08:11:39.54#ibcon#read 6, iclass 4, count 0 2006.168.08:11:39.54#ibcon#end of sib2, iclass 4, count 0 2006.168.08:11:39.54#ibcon#*mode == 0, iclass 4, count 0 2006.168.08:11:39.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.168.08:11:39.54#ibcon#[25=USB\r\n] 2006.168.08:11:39.54#ibcon#*before write, iclass 4, count 0 2006.168.08:11:39.54#ibcon#enter sib2, iclass 4, count 0 2006.168.08:11:39.54#ibcon#flushed, iclass 4, count 0 2006.168.08:11:39.54#ibcon#about to write, iclass 4, count 0 2006.168.08:11:39.54#ibcon#wrote, iclass 4, count 0 2006.168.08:11:39.54#ibcon#about to read 3, iclass 4, count 0 2006.168.08:11:39.57#ibcon#read 3, iclass 4, count 0 2006.168.08:11:39.57#ibcon#about to read 4, iclass 4, count 0 2006.168.08:11:39.57#ibcon#read 4, iclass 4, count 0 2006.168.08:11:39.57#ibcon#about to read 5, iclass 4, count 0 2006.168.08:11:39.57#ibcon#read 5, iclass 4, count 0 2006.168.08:11:39.57#ibcon#about to read 6, iclass 4, count 0 2006.168.08:11:39.57#ibcon#read 6, iclass 4, count 0 2006.168.08:11:39.57#ibcon#end of sib2, iclass 4, count 0 2006.168.08:11:39.57#ibcon#*after write, iclass 4, count 0 2006.168.08:11:39.57#ibcon#*before return 0, iclass 4, count 0 2006.168.08:11:39.57#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.168.08:11:39.57#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.168.08:11:39.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.168.08:11:39.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.168.08:11:39.57$vc4f8/valo=6,772.99 2006.168.08:11:39.57#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.168.08:11:39.57#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.168.08:11:39.57#ibcon#ireg 17 cls_cnt 0 2006.168.08:11:39.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.168.08:11:39.57#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.168.08:11:39.57#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.168.08:11:39.57#ibcon#enter wrdev, iclass 6, count 0 2006.168.08:11:39.57#ibcon#first serial, iclass 6, count 0 2006.168.08:11:39.57#ibcon#enter sib2, iclass 6, count 0 2006.168.08:11:39.57#ibcon#flushed, iclass 6, count 0 2006.168.08:11:39.57#ibcon#about to write, iclass 6, count 0 2006.168.08:11:39.57#ibcon#wrote, iclass 6, count 0 2006.168.08:11:39.57#ibcon#about to read 3, iclass 6, count 0 2006.168.08:11:39.59#ibcon#read 3, iclass 6, count 0 2006.168.08:11:39.59#ibcon#about to read 4, iclass 6, count 0 2006.168.08:11:39.59#ibcon#read 4, iclass 6, count 0 2006.168.08:11:39.59#ibcon#about to read 5, iclass 6, count 0 2006.168.08:11:39.59#ibcon#read 5, iclass 6, count 0 2006.168.08:11:39.59#ibcon#about to read 6, iclass 6, count 0 2006.168.08:11:39.59#ibcon#read 6, iclass 6, count 0 2006.168.08:11:39.59#ibcon#end of sib2, iclass 6, count 0 2006.168.08:11:39.59#ibcon#*mode == 0, iclass 6, count 0 2006.168.08:11:39.59#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.168.08:11:39.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.08:11:39.59#ibcon#*before write, iclass 6, count 0 2006.168.08:11:39.59#ibcon#enter sib2, iclass 6, count 0 2006.168.08:11:39.59#ibcon#flushed, iclass 6, count 0 2006.168.08:11:39.59#ibcon#about to write, iclass 6, count 0 2006.168.08:11:39.59#ibcon#wrote, iclass 6, count 0 2006.168.08:11:39.59#ibcon#about to read 3, iclass 6, count 0 2006.168.08:11:39.63#ibcon#read 3, iclass 6, count 0 2006.168.08:11:39.63#ibcon#about to read 4, iclass 6, count 0 2006.168.08:11:39.63#ibcon#read 4, iclass 6, count 0 2006.168.08:11:39.63#ibcon#about to read 5, iclass 6, count 0 2006.168.08:11:39.63#ibcon#read 5, iclass 6, count 0 2006.168.08:11:39.63#ibcon#about to read 6, iclass 6, count 0 2006.168.08:11:39.63#ibcon#read 6, iclass 6, count 0 2006.168.08:11:39.63#ibcon#end of sib2, iclass 6, count 0 2006.168.08:11:39.63#ibcon#*after write, iclass 6, count 0 2006.168.08:11:39.63#ibcon#*before return 0, iclass 6, count 0 2006.168.08:11:39.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.168.08:11:39.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.168.08:11:39.63#ibcon#about to clear, iclass 6 cls_cnt 0 2006.168.08:11:39.63#ibcon#cleared, iclass 6 cls_cnt 0 2006.168.08:11:39.63$vc4f8/va=6,6 2006.168.08:11:39.63#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.168.08:11:39.63#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.168.08:11:39.63#ibcon#ireg 11 cls_cnt 2 2006.168.08:11:39.63#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.168.08:11:39.69#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.168.08:11:39.69#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.168.08:11:39.69#ibcon#enter wrdev, iclass 10, count 2 2006.168.08:11:39.69#ibcon#first serial, iclass 10, count 2 2006.168.08:11:39.69#ibcon#enter sib2, iclass 10, count 2 2006.168.08:11:39.69#ibcon#flushed, iclass 10, count 2 2006.168.08:11:39.69#ibcon#about to write, iclass 10, count 2 2006.168.08:11:39.69#ibcon#wrote, iclass 10, count 2 2006.168.08:11:39.69#ibcon#about to read 3, iclass 10, count 2 2006.168.08:11:39.71#ibcon#read 3, iclass 10, count 2 2006.168.08:11:39.71#ibcon#about to read 4, iclass 10, count 2 2006.168.08:11:39.71#ibcon#read 4, iclass 10, count 2 2006.168.08:11:39.71#ibcon#about to read 5, iclass 10, count 2 2006.168.08:11:39.71#ibcon#read 5, iclass 10, count 2 2006.168.08:11:39.71#ibcon#about to read 6, iclass 10, count 2 2006.168.08:11:39.71#ibcon#read 6, iclass 10, count 2 2006.168.08:11:39.71#ibcon#end of sib2, iclass 10, count 2 2006.168.08:11:39.71#ibcon#*mode == 0, iclass 10, count 2 2006.168.08:11:39.71#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.168.08:11:39.71#ibcon#[25=AT06-06\r\n] 2006.168.08:11:39.71#ibcon#*before write, iclass 10, count 2 2006.168.08:11:39.71#ibcon#enter sib2, iclass 10, count 2 2006.168.08:11:39.71#ibcon#flushed, iclass 10, count 2 2006.168.08:11:39.71#ibcon#about to write, iclass 10, count 2 2006.168.08:11:39.71#ibcon#wrote, iclass 10, count 2 2006.168.08:11:39.71#ibcon#about to read 3, iclass 10, count 2 2006.168.08:11:39.74#ibcon#read 3, iclass 10, count 2 2006.168.08:11:39.74#ibcon#about to read 4, iclass 10, count 2 2006.168.08:11:39.74#ibcon#read 4, iclass 10, count 2 2006.168.08:11:39.74#ibcon#about to read 5, iclass 10, count 2 2006.168.08:11:39.74#ibcon#read 5, iclass 10, count 2 2006.168.08:11:39.74#ibcon#about to read 6, iclass 10, count 2 2006.168.08:11:39.74#ibcon#read 6, iclass 10, count 2 2006.168.08:11:39.74#ibcon#end of sib2, iclass 10, count 2 2006.168.08:11:39.74#ibcon#*after write, iclass 10, count 2 2006.168.08:11:39.74#ibcon#*before return 0, iclass 10, count 2 2006.168.08:11:39.74#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.168.08:11:39.74#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.168.08:11:39.74#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.168.08:11:39.74#ibcon#ireg 7 cls_cnt 0 2006.168.08:11:39.74#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.168.08:11:39.86#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.168.08:11:39.86#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.168.08:11:39.86#ibcon#enter wrdev, iclass 10, count 0 2006.168.08:11:39.86#ibcon#first serial, iclass 10, count 0 2006.168.08:11:39.86#ibcon#enter sib2, iclass 10, count 0 2006.168.08:11:39.86#ibcon#flushed, iclass 10, count 0 2006.168.08:11:39.86#ibcon#about to write, iclass 10, count 0 2006.168.08:11:39.86#ibcon#wrote, iclass 10, count 0 2006.168.08:11:39.86#ibcon#about to read 3, iclass 10, count 0 2006.168.08:11:39.88#ibcon#read 3, iclass 10, count 0 2006.168.08:11:39.88#ibcon#about to read 4, iclass 10, count 0 2006.168.08:11:39.88#ibcon#read 4, iclass 10, count 0 2006.168.08:11:39.88#ibcon#about to read 5, iclass 10, count 0 2006.168.08:11:39.88#ibcon#read 5, iclass 10, count 0 2006.168.08:11:39.88#ibcon#about to read 6, iclass 10, count 0 2006.168.08:11:39.88#ibcon#read 6, iclass 10, count 0 2006.168.08:11:39.88#ibcon#end of sib2, iclass 10, count 0 2006.168.08:11:39.88#ibcon#*mode == 0, iclass 10, count 0 2006.168.08:11:39.88#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.168.08:11:39.88#ibcon#[25=USB\r\n] 2006.168.08:11:39.88#ibcon#*before write, iclass 10, count 0 2006.168.08:11:39.88#ibcon#enter sib2, iclass 10, count 0 2006.168.08:11:39.88#ibcon#flushed, iclass 10, count 0 2006.168.08:11:39.88#ibcon#about to write, iclass 10, count 0 2006.168.08:11:39.88#ibcon#wrote, iclass 10, count 0 2006.168.08:11:39.88#ibcon#about to read 3, iclass 10, count 0 2006.168.08:11:39.91#ibcon#read 3, iclass 10, count 0 2006.168.08:11:39.91#ibcon#about to read 4, iclass 10, count 0 2006.168.08:11:39.91#ibcon#read 4, iclass 10, count 0 2006.168.08:11:39.91#ibcon#about to read 5, iclass 10, count 0 2006.168.08:11:39.91#ibcon#read 5, iclass 10, count 0 2006.168.08:11:39.91#ibcon#about to read 6, iclass 10, count 0 2006.168.08:11:39.91#ibcon#read 6, iclass 10, count 0 2006.168.08:11:39.91#ibcon#end of sib2, iclass 10, count 0 2006.168.08:11:39.91#ibcon#*after write, iclass 10, count 0 2006.168.08:11:39.91#ibcon#*before return 0, iclass 10, count 0 2006.168.08:11:39.91#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.168.08:11:39.91#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.168.08:11:39.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.168.08:11:39.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.168.08:11:39.91$vc4f8/valo=7,832.99 2006.168.08:11:39.91#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.168.08:11:39.91#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.168.08:11:39.91#ibcon#ireg 17 cls_cnt 0 2006.168.08:11:39.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.168.08:11:39.91#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.168.08:11:39.91#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.168.08:11:39.91#ibcon#enter wrdev, iclass 12, count 0 2006.168.08:11:39.91#ibcon#first serial, iclass 12, count 0 2006.168.08:11:39.91#ibcon#enter sib2, iclass 12, count 0 2006.168.08:11:39.91#ibcon#flushed, iclass 12, count 0 2006.168.08:11:39.91#ibcon#about to write, iclass 12, count 0 2006.168.08:11:39.91#ibcon#wrote, iclass 12, count 0 2006.168.08:11:39.91#ibcon#about to read 3, iclass 12, count 0 2006.168.08:11:39.93#ibcon#read 3, iclass 12, count 0 2006.168.08:11:39.93#ibcon#about to read 4, iclass 12, count 0 2006.168.08:11:39.93#ibcon#read 4, iclass 12, count 0 2006.168.08:11:39.93#ibcon#about to read 5, iclass 12, count 0 2006.168.08:11:39.93#ibcon#read 5, iclass 12, count 0 2006.168.08:11:39.93#ibcon#about to read 6, iclass 12, count 0 2006.168.08:11:39.93#ibcon#read 6, iclass 12, count 0 2006.168.08:11:39.93#ibcon#end of sib2, iclass 12, count 0 2006.168.08:11:39.93#ibcon#*mode == 0, iclass 12, count 0 2006.168.08:11:39.93#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.168.08:11:39.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.08:11:39.93#ibcon#*before write, iclass 12, count 0 2006.168.08:11:39.93#ibcon#enter sib2, iclass 12, count 0 2006.168.08:11:39.93#ibcon#flushed, iclass 12, count 0 2006.168.08:11:39.93#ibcon#about to write, iclass 12, count 0 2006.168.08:11:39.93#ibcon#wrote, iclass 12, count 0 2006.168.08:11:39.93#ibcon#about to read 3, iclass 12, count 0 2006.168.08:11:39.97#ibcon#read 3, iclass 12, count 0 2006.168.08:11:39.97#ibcon#about to read 4, iclass 12, count 0 2006.168.08:11:39.97#ibcon#read 4, iclass 12, count 0 2006.168.08:11:39.97#ibcon#about to read 5, iclass 12, count 0 2006.168.08:11:39.97#ibcon#read 5, iclass 12, count 0 2006.168.08:11:39.97#ibcon#about to read 6, iclass 12, count 0 2006.168.08:11:39.97#ibcon#read 6, iclass 12, count 0 2006.168.08:11:39.97#ibcon#end of sib2, iclass 12, count 0 2006.168.08:11:39.97#ibcon#*after write, iclass 12, count 0 2006.168.08:11:39.97#ibcon#*before return 0, iclass 12, count 0 2006.168.08:11:39.97#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.168.08:11:39.97#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.168.08:11:39.97#ibcon#about to clear, iclass 12 cls_cnt 0 2006.168.08:11:39.97#ibcon#cleared, iclass 12 cls_cnt 0 2006.168.08:11:39.97$vc4f8/va=7,6 2006.168.08:11:39.97#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.168.08:11:39.97#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.168.08:11:39.97#ibcon#ireg 11 cls_cnt 2 2006.168.08:11:39.97#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.168.08:11:40.04#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.168.08:11:40.04#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.168.08:11:40.04#ibcon#enter wrdev, iclass 14, count 2 2006.168.08:11:40.04#ibcon#first serial, iclass 14, count 2 2006.168.08:11:40.04#ibcon#enter sib2, iclass 14, count 2 2006.168.08:11:40.04#ibcon#flushed, iclass 14, count 2 2006.168.08:11:40.04#ibcon#about to write, iclass 14, count 2 2006.168.08:11:40.04#ibcon#wrote, iclass 14, count 2 2006.168.08:11:40.04#ibcon#about to read 3, iclass 14, count 2 2006.168.08:11:40.05#ibcon#read 3, iclass 14, count 2 2006.168.08:11:40.05#ibcon#about to read 4, iclass 14, count 2 2006.168.08:11:40.05#ibcon#read 4, iclass 14, count 2 2006.168.08:11:40.05#ibcon#about to read 5, iclass 14, count 2 2006.168.08:11:40.05#ibcon#read 5, iclass 14, count 2 2006.168.08:11:40.05#ibcon#about to read 6, iclass 14, count 2 2006.168.08:11:40.05#ibcon#read 6, iclass 14, count 2 2006.168.08:11:40.05#ibcon#end of sib2, iclass 14, count 2 2006.168.08:11:40.05#ibcon#*mode == 0, iclass 14, count 2 2006.168.08:11:40.05#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.168.08:11:40.05#ibcon#[25=AT07-06\r\n] 2006.168.08:11:40.05#ibcon#*before write, iclass 14, count 2 2006.168.08:11:40.05#ibcon#enter sib2, iclass 14, count 2 2006.168.08:11:40.05#ibcon#flushed, iclass 14, count 2 2006.168.08:11:40.05#ibcon#about to write, iclass 14, count 2 2006.168.08:11:40.05#ibcon#wrote, iclass 14, count 2 2006.168.08:11:40.05#ibcon#about to read 3, iclass 14, count 2 2006.168.08:11:40.08#ibcon#read 3, iclass 14, count 2 2006.168.08:11:40.08#ibcon#about to read 4, iclass 14, count 2 2006.168.08:11:40.08#ibcon#read 4, iclass 14, count 2 2006.168.08:11:40.08#ibcon#about to read 5, iclass 14, count 2 2006.168.08:11:40.08#ibcon#read 5, iclass 14, count 2 2006.168.08:11:40.08#ibcon#about to read 6, iclass 14, count 2 2006.168.08:11:40.08#ibcon#read 6, iclass 14, count 2 2006.168.08:11:40.08#ibcon#end of sib2, iclass 14, count 2 2006.168.08:11:40.08#ibcon#*after write, iclass 14, count 2 2006.168.08:11:40.08#ibcon#*before return 0, iclass 14, count 2 2006.168.08:11:40.08#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.168.08:11:40.08#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.168.08:11:40.08#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.168.08:11:40.08#ibcon#ireg 7 cls_cnt 0 2006.168.08:11:40.08#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.168.08:11:40.20#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.168.08:11:40.20#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.168.08:11:40.20#ibcon#enter wrdev, iclass 14, count 0 2006.168.08:11:40.20#ibcon#first serial, iclass 14, count 0 2006.168.08:11:40.20#ibcon#enter sib2, iclass 14, count 0 2006.168.08:11:40.20#ibcon#flushed, iclass 14, count 0 2006.168.08:11:40.20#ibcon#about to write, iclass 14, count 0 2006.168.08:11:40.20#ibcon#wrote, iclass 14, count 0 2006.168.08:11:40.20#ibcon#about to read 3, iclass 14, count 0 2006.168.08:11:40.22#ibcon#read 3, iclass 14, count 0 2006.168.08:11:40.22#ibcon#about to read 4, iclass 14, count 0 2006.168.08:11:40.22#ibcon#read 4, iclass 14, count 0 2006.168.08:11:40.22#ibcon#about to read 5, iclass 14, count 0 2006.168.08:11:40.22#ibcon#read 5, iclass 14, count 0 2006.168.08:11:40.22#ibcon#about to read 6, iclass 14, count 0 2006.168.08:11:40.22#ibcon#read 6, iclass 14, count 0 2006.168.08:11:40.22#ibcon#end of sib2, iclass 14, count 0 2006.168.08:11:40.22#ibcon#*mode == 0, iclass 14, count 0 2006.168.08:11:40.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.168.08:11:40.22#ibcon#[25=USB\r\n] 2006.168.08:11:40.22#ibcon#*before write, iclass 14, count 0 2006.168.08:11:40.22#ibcon#enter sib2, iclass 14, count 0 2006.168.08:11:40.22#ibcon#flushed, iclass 14, count 0 2006.168.08:11:40.22#ibcon#about to write, iclass 14, count 0 2006.168.08:11:40.22#ibcon#wrote, iclass 14, count 0 2006.168.08:11:40.22#ibcon#about to read 3, iclass 14, count 0 2006.168.08:11:40.25#ibcon#read 3, iclass 14, count 0 2006.168.08:11:40.25#ibcon#about to read 4, iclass 14, count 0 2006.168.08:11:40.25#ibcon#read 4, iclass 14, count 0 2006.168.08:11:40.25#ibcon#about to read 5, iclass 14, count 0 2006.168.08:11:40.25#ibcon#read 5, iclass 14, count 0 2006.168.08:11:40.25#ibcon#about to read 6, iclass 14, count 0 2006.168.08:11:40.25#ibcon#read 6, iclass 14, count 0 2006.168.08:11:40.25#ibcon#end of sib2, iclass 14, count 0 2006.168.08:11:40.25#ibcon#*after write, iclass 14, count 0 2006.168.08:11:40.25#ibcon#*before return 0, iclass 14, count 0 2006.168.08:11:40.25#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.168.08:11:40.25#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.168.08:11:40.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.168.08:11:40.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.168.08:11:40.25$vc4f8/valo=8,852.99 2006.168.08:11:40.25#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.168.08:11:40.25#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.168.08:11:40.25#ibcon#ireg 17 cls_cnt 0 2006.168.08:11:40.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.168.08:11:40.25#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.168.08:11:40.25#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.168.08:11:40.25#ibcon#enter wrdev, iclass 16, count 0 2006.168.08:11:40.25#ibcon#first serial, iclass 16, count 0 2006.168.08:11:40.25#ibcon#enter sib2, iclass 16, count 0 2006.168.08:11:40.25#ibcon#flushed, iclass 16, count 0 2006.168.08:11:40.25#ibcon#about to write, iclass 16, count 0 2006.168.08:11:40.25#ibcon#wrote, iclass 16, count 0 2006.168.08:11:40.25#ibcon#about to read 3, iclass 16, count 0 2006.168.08:11:40.27#ibcon#read 3, iclass 16, count 0 2006.168.08:11:40.27#ibcon#about to read 4, iclass 16, count 0 2006.168.08:11:40.27#ibcon#read 4, iclass 16, count 0 2006.168.08:11:40.27#ibcon#about to read 5, iclass 16, count 0 2006.168.08:11:40.27#ibcon#read 5, iclass 16, count 0 2006.168.08:11:40.27#ibcon#about to read 6, iclass 16, count 0 2006.168.08:11:40.27#ibcon#read 6, iclass 16, count 0 2006.168.08:11:40.27#ibcon#end of sib2, iclass 16, count 0 2006.168.08:11:40.27#ibcon#*mode == 0, iclass 16, count 0 2006.168.08:11:40.27#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.168.08:11:40.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.08:11:40.27#ibcon#*before write, iclass 16, count 0 2006.168.08:11:40.27#ibcon#enter sib2, iclass 16, count 0 2006.168.08:11:40.27#ibcon#flushed, iclass 16, count 0 2006.168.08:11:40.27#ibcon#about to write, iclass 16, count 0 2006.168.08:11:40.27#ibcon#wrote, iclass 16, count 0 2006.168.08:11:40.27#ibcon#about to read 3, iclass 16, count 0 2006.168.08:11:40.31#ibcon#read 3, iclass 16, count 0 2006.168.08:11:40.31#ibcon#about to read 4, iclass 16, count 0 2006.168.08:11:40.31#ibcon#read 4, iclass 16, count 0 2006.168.08:11:40.31#ibcon#about to read 5, iclass 16, count 0 2006.168.08:11:40.31#ibcon#read 5, iclass 16, count 0 2006.168.08:11:40.31#ibcon#about to read 6, iclass 16, count 0 2006.168.08:11:40.31#ibcon#read 6, iclass 16, count 0 2006.168.08:11:40.31#ibcon#end of sib2, iclass 16, count 0 2006.168.08:11:40.31#ibcon#*after write, iclass 16, count 0 2006.168.08:11:40.31#ibcon#*before return 0, iclass 16, count 0 2006.168.08:11:40.31#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.168.08:11:40.31#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.168.08:11:40.31#ibcon#about to clear, iclass 16 cls_cnt 0 2006.168.08:11:40.31#ibcon#cleared, iclass 16 cls_cnt 0 2006.168.08:11:40.31$vc4f8/va=8,7 2006.168.08:11:40.31#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.168.08:11:40.31#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.168.08:11:40.31#ibcon#ireg 11 cls_cnt 2 2006.168.08:11:40.31#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.168.08:11:40.37#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.168.08:11:40.37#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.168.08:11:40.37#ibcon#enter wrdev, iclass 18, count 2 2006.168.08:11:40.37#ibcon#first serial, iclass 18, count 2 2006.168.08:11:40.37#ibcon#enter sib2, iclass 18, count 2 2006.168.08:11:40.37#ibcon#flushed, iclass 18, count 2 2006.168.08:11:40.37#ibcon#about to write, iclass 18, count 2 2006.168.08:11:40.37#ibcon#wrote, iclass 18, count 2 2006.168.08:11:40.37#ibcon#about to read 3, iclass 18, count 2 2006.168.08:11:40.39#ibcon#read 3, iclass 18, count 2 2006.168.08:11:40.39#ibcon#about to read 4, iclass 18, count 2 2006.168.08:11:40.39#ibcon#read 4, iclass 18, count 2 2006.168.08:11:40.39#ibcon#about to read 5, iclass 18, count 2 2006.168.08:11:40.39#ibcon#read 5, iclass 18, count 2 2006.168.08:11:40.39#ibcon#about to read 6, iclass 18, count 2 2006.168.08:11:40.39#ibcon#read 6, iclass 18, count 2 2006.168.08:11:40.39#ibcon#end of sib2, iclass 18, count 2 2006.168.08:11:40.39#ibcon#*mode == 0, iclass 18, count 2 2006.168.08:11:40.39#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.168.08:11:40.39#ibcon#[25=AT08-07\r\n] 2006.168.08:11:40.39#ibcon#*before write, iclass 18, count 2 2006.168.08:11:40.39#ibcon#enter sib2, iclass 18, count 2 2006.168.08:11:40.39#ibcon#flushed, iclass 18, count 2 2006.168.08:11:40.39#ibcon#about to write, iclass 18, count 2 2006.168.08:11:40.39#ibcon#wrote, iclass 18, count 2 2006.168.08:11:40.39#ibcon#about to read 3, iclass 18, count 2 2006.168.08:11:40.42#ibcon#read 3, iclass 18, count 2 2006.168.08:11:40.42#ibcon#about to read 4, iclass 18, count 2 2006.168.08:11:40.42#ibcon#read 4, iclass 18, count 2 2006.168.08:11:40.42#ibcon#about to read 5, iclass 18, count 2 2006.168.08:11:40.42#ibcon#read 5, iclass 18, count 2 2006.168.08:11:40.42#ibcon#about to read 6, iclass 18, count 2 2006.168.08:11:40.42#ibcon#read 6, iclass 18, count 2 2006.168.08:11:40.42#ibcon#end of sib2, iclass 18, count 2 2006.168.08:11:40.42#ibcon#*after write, iclass 18, count 2 2006.168.08:11:40.42#ibcon#*before return 0, iclass 18, count 2 2006.168.08:11:40.42#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.168.08:11:40.42#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.168.08:11:40.42#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.168.08:11:40.42#ibcon#ireg 7 cls_cnt 0 2006.168.08:11:40.42#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.168.08:11:40.54#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.168.08:11:40.54#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.168.08:11:40.54#ibcon#enter wrdev, iclass 18, count 0 2006.168.08:11:40.54#ibcon#first serial, iclass 18, count 0 2006.168.08:11:40.54#ibcon#enter sib2, iclass 18, count 0 2006.168.08:11:40.54#ibcon#flushed, iclass 18, count 0 2006.168.08:11:40.54#ibcon#about to write, iclass 18, count 0 2006.168.08:11:40.54#ibcon#wrote, iclass 18, count 0 2006.168.08:11:40.54#ibcon#about to read 3, iclass 18, count 0 2006.168.08:11:40.56#ibcon#read 3, iclass 18, count 0 2006.168.08:11:40.56#ibcon#about to read 4, iclass 18, count 0 2006.168.08:11:40.56#ibcon#read 4, iclass 18, count 0 2006.168.08:11:40.56#ibcon#about to read 5, iclass 18, count 0 2006.168.08:11:40.56#ibcon#read 5, iclass 18, count 0 2006.168.08:11:40.56#ibcon#about to read 6, iclass 18, count 0 2006.168.08:11:40.56#ibcon#read 6, iclass 18, count 0 2006.168.08:11:40.56#ibcon#end of sib2, iclass 18, count 0 2006.168.08:11:40.56#ibcon#*mode == 0, iclass 18, count 0 2006.168.08:11:40.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.08:11:40.56#ibcon#[25=USB\r\n] 2006.168.08:11:40.56#ibcon#*before write, iclass 18, count 0 2006.168.08:11:40.56#ibcon#enter sib2, iclass 18, count 0 2006.168.08:11:40.56#ibcon#flushed, iclass 18, count 0 2006.168.08:11:40.56#ibcon#about to write, iclass 18, count 0 2006.168.08:11:40.56#ibcon#wrote, iclass 18, count 0 2006.168.08:11:40.56#ibcon#about to read 3, iclass 18, count 0 2006.168.08:11:40.59#ibcon#read 3, iclass 18, count 0 2006.168.08:11:40.59#ibcon#about to read 4, iclass 18, count 0 2006.168.08:11:40.59#ibcon#read 4, iclass 18, count 0 2006.168.08:11:40.59#ibcon#about to read 5, iclass 18, count 0 2006.168.08:11:40.59#ibcon#read 5, iclass 18, count 0 2006.168.08:11:40.59#ibcon#about to read 6, iclass 18, count 0 2006.168.08:11:40.59#ibcon#read 6, iclass 18, count 0 2006.168.08:11:40.59#ibcon#end of sib2, iclass 18, count 0 2006.168.08:11:40.59#ibcon#*after write, iclass 18, count 0 2006.168.08:11:40.59#ibcon#*before return 0, iclass 18, count 0 2006.168.08:11:40.59#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.168.08:11:40.59#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.168.08:11:40.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.08:11:40.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.08:11:40.59$vc4f8/vblo=1,632.99 2006.168.08:11:40.59#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.168.08:11:40.59#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.168.08:11:40.59#ibcon#ireg 17 cls_cnt 0 2006.168.08:11:40.59#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:11:40.59#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:11:40.59#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:11:40.59#ibcon#enter wrdev, iclass 21, count 0 2006.168.08:11:40.59#ibcon#first serial, iclass 21, count 0 2006.168.08:11:40.59#ibcon#enter sib2, iclass 21, count 0 2006.168.08:11:40.59#ibcon#flushed, iclass 21, count 0 2006.168.08:11:40.59#ibcon#about to write, iclass 21, count 0 2006.168.08:11:40.59#ibcon#wrote, iclass 21, count 0 2006.168.08:11:40.59#ibcon#about to read 3, iclass 21, count 0 2006.168.08:11:40.60#abcon#<5=/08 1.5 3.8 26.96 751004.6\r\n> 2006.168.08:11:40.61#ibcon#read 3, iclass 21, count 0 2006.168.08:11:40.61#ibcon#about to read 4, iclass 21, count 0 2006.168.08:11:40.61#ibcon#read 4, iclass 21, count 0 2006.168.08:11:40.61#ibcon#about to read 5, iclass 21, count 0 2006.168.08:11:40.61#ibcon#read 5, iclass 21, count 0 2006.168.08:11:40.61#ibcon#about to read 6, iclass 21, count 0 2006.168.08:11:40.61#ibcon#read 6, iclass 21, count 0 2006.168.08:11:40.61#ibcon#end of sib2, iclass 21, count 0 2006.168.08:11:40.61#ibcon#*mode == 0, iclass 21, count 0 2006.168.08:11:40.61#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.168.08:11:40.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.08:11:40.61#ibcon#*before write, iclass 21, count 0 2006.168.08:11:40.61#ibcon#enter sib2, iclass 21, count 0 2006.168.08:11:40.61#ibcon#flushed, iclass 21, count 0 2006.168.08:11:40.61#ibcon#about to write, iclass 21, count 0 2006.168.08:11:40.61#ibcon#wrote, iclass 21, count 0 2006.168.08:11:40.61#ibcon#about to read 3, iclass 21, count 0 2006.168.08:11:40.62#abcon#{5=INTERFACE CLEAR} 2006.168.08:11:40.65#ibcon#read 3, iclass 21, count 0 2006.168.08:11:40.65#ibcon#about to read 4, iclass 21, count 0 2006.168.08:11:40.65#ibcon#read 4, iclass 21, count 0 2006.168.08:11:40.65#ibcon#about to read 5, iclass 21, count 0 2006.168.08:11:40.65#ibcon#read 5, iclass 21, count 0 2006.168.08:11:40.65#ibcon#about to read 6, iclass 21, count 0 2006.168.08:11:40.65#ibcon#read 6, iclass 21, count 0 2006.168.08:11:40.65#ibcon#end of sib2, iclass 21, count 0 2006.168.08:11:40.65#ibcon#*after write, iclass 21, count 0 2006.168.08:11:40.65#ibcon#*before return 0, iclass 21, count 0 2006.168.08:11:40.65#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:11:40.65#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:11:40.65#ibcon#about to clear, iclass 21 cls_cnt 0 2006.168.08:11:40.65#ibcon#cleared, iclass 21 cls_cnt 0 2006.168.08:11:40.65$vc4f8/vb=1,4 2006.168.08:11:40.65#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.168.08:11:40.65#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.168.08:11:40.65#ibcon#ireg 11 cls_cnt 2 2006.168.08:11:40.65#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:11:40.65#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:11:40.65#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:11:40.65#ibcon#enter wrdev, iclass 25, count 2 2006.168.08:11:40.65#ibcon#first serial, iclass 25, count 2 2006.168.08:11:40.65#ibcon#enter sib2, iclass 25, count 2 2006.168.08:11:40.65#ibcon#flushed, iclass 25, count 2 2006.168.08:11:40.65#ibcon#about to write, iclass 25, count 2 2006.168.08:11:40.65#ibcon#wrote, iclass 25, count 2 2006.168.08:11:40.65#ibcon#about to read 3, iclass 25, count 2 2006.168.08:11:40.67#ibcon#read 3, iclass 25, count 2 2006.168.08:11:40.67#ibcon#about to read 4, iclass 25, count 2 2006.168.08:11:40.67#ibcon#read 4, iclass 25, count 2 2006.168.08:11:40.67#ibcon#about to read 5, iclass 25, count 2 2006.168.08:11:40.67#ibcon#read 5, iclass 25, count 2 2006.168.08:11:40.67#ibcon#about to read 6, iclass 25, count 2 2006.168.08:11:40.67#ibcon#read 6, iclass 25, count 2 2006.168.08:11:40.67#ibcon#end of sib2, iclass 25, count 2 2006.168.08:11:40.67#ibcon#*mode == 0, iclass 25, count 2 2006.168.08:11:40.67#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.168.08:11:40.67#ibcon#[27=AT01-04\r\n] 2006.168.08:11:40.67#ibcon#*before write, iclass 25, count 2 2006.168.08:11:40.67#ibcon#enter sib2, iclass 25, count 2 2006.168.08:11:40.67#ibcon#flushed, iclass 25, count 2 2006.168.08:11:40.67#ibcon#about to write, iclass 25, count 2 2006.168.08:11:40.67#ibcon#wrote, iclass 25, count 2 2006.168.08:11:40.67#ibcon#about to read 3, iclass 25, count 2 2006.168.08:11:40.68#abcon#[5=S1D000X0/0*\r\n] 2006.168.08:11:40.70#ibcon#read 3, iclass 25, count 2 2006.168.08:11:40.70#ibcon#about to read 4, iclass 25, count 2 2006.168.08:11:40.70#ibcon#read 4, iclass 25, count 2 2006.168.08:11:40.70#ibcon#about to read 5, iclass 25, count 2 2006.168.08:11:40.70#ibcon#read 5, iclass 25, count 2 2006.168.08:11:40.70#ibcon#about to read 6, iclass 25, count 2 2006.168.08:11:40.70#ibcon#read 6, iclass 25, count 2 2006.168.08:11:40.70#ibcon#end of sib2, iclass 25, count 2 2006.168.08:11:40.70#ibcon#*after write, iclass 25, count 2 2006.168.08:11:40.70#ibcon#*before return 0, iclass 25, count 2 2006.168.08:11:40.70#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:11:40.70#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:11:40.70#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.168.08:11:40.70#ibcon#ireg 7 cls_cnt 0 2006.168.08:11:40.70#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:11:40.82#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:11:40.82#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:11:40.83#ibcon#enter wrdev, iclass 25, count 0 2006.168.08:11:40.83#ibcon#first serial, iclass 25, count 0 2006.168.08:11:40.83#ibcon#enter sib2, iclass 25, count 0 2006.168.08:11:40.83#ibcon#flushed, iclass 25, count 0 2006.168.08:11:40.83#ibcon#about to write, iclass 25, count 0 2006.168.08:11:40.83#ibcon#wrote, iclass 25, count 0 2006.168.08:11:40.83#ibcon#about to read 3, iclass 25, count 0 2006.168.08:11:40.84#ibcon#read 3, iclass 25, count 0 2006.168.08:11:40.84#ibcon#about to read 4, iclass 25, count 0 2006.168.08:11:40.84#ibcon#read 4, iclass 25, count 0 2006.168.08:11:40.84#ibcon#about to read 5, iclass 25, count 0 2006.168.08:11:40.84#ibcon#read 5, iclass 25, count 0 2006.168.08:11:40.84#ibcon#about to read 6, iclass 25, count 0 2006.168.08:11:40.84#ibcon#read 6, iclass 25, count 0 2006.168.08:11:40.84#ibcon#end of sib2, iclass 25, count 0 2006.168.08:11:40.84#ibcon#*mode == 0, iclass 25, count 0 2006.168.08:11:40.84#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.168.08:11:40.84#ibcon#[27=USB\r\n] 2006.168.08:11:40.84#ibcon#*before write, iclass 25, count 0 2006.168.08:11:40.84#ibcon#enter sib2, iclass 25, count 0 2006.168.08:11:40.84#ibcon#flushed, iclass 25, count 0 2006.168.08:11:40.84#ibcon#about to write, iclass 25, count 0 2006.168.08:11:40.84#ibcon#wrote, iclass 25, count 0 2006.168.08:11:40.84#ibcon#about to read 3, iclass 25, count 0 2006.168.08:11:40.87#ibcon#read 3, iclass 25, count 0 2006.168.08:11:40.87#ibcon#about to read 4, iclass 25, count 0 2006.168.08:11:40.87#ibcon#read 4, iclass 25, count 0 2006.168.08:11:40.87#ibcon#about to read 5, iclass 25, count 0 2006.168.08:11:40.87#ibcon#read 5, iclass 25, count 0 2006.168.08:11:40.87#ibcon#about to read 6, iclass 25, count 0 2006.168.08:11:40.87#ibcon#read 6, iclass 25, count 0 2006.168.08:11:40.87#ibcon#end of sib2, iclass 25, count 0 2006.168.08:11:40.87#ibcon#*after write, iclass 25, count 0 2006.168.08:11:40.87#ibcon#*before return 0, iclass 25, count 0 2006.168.08:11:40.87#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:11:40.87#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:11:40.87#ibcon#about to clear, iclass 25 cls_cnt 0 2006.168.08:11:40.87#ibcon#cleared, iclass 25 cls_cnt 0 2006.168.08:11:40.87$vc4f8/vblo=2,640.99 2006.168.08:11:40.87#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.168.08:11:40.87#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.168.08:11:40.87#ibcon#ireg 17 cls_cnt 0 2006.168.08:11:40.87#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.168.08:11:40.87#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.168.08:11:40.87#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.168.08:11:40.87#ibcon#enter wrdev, iclass 28, count 0 2006.168.08:11:40.87#ibcon#first serial, iclass 28, count 0 2006.168.08:11:40.87#ibcon#enter sib2, iclass 28, count 0 2006.168.08:11:40.87#ibcon#flushed, iclass 28, count 0 2006.168.08:11:40.87#ibcon#about to write, iclass 28, count 0 2006.168.08:11:40.87#ibcon#wrote, iclass 28, count 0 2006.168.08:11:40.87#ibcon#about to read 3, iclass 28, count 0 2006.168.08:11:40.89#ibcon#read 3, iclass 28, count 0 2006.168.08:11:40.89#ibcon#about to read 4, iclass 28, count 0 2006.168.08:11:40.89#ibcon#read 4, iclass 28, count 0 2006.168.08:11:40.89#ibcon#about to read 5, iclass 28, count 0 2006.168.08:11:40.89#ibcon#read 5, iclass 28, count 0 2006.168.08:11:40.89#ibcon#about to read 6, iclass 28, count 0 2006.168.08:11:40.89#ibcon#read 6, iclass 28, count 0 2006.168.08:11:40.89#ibcon#end of sib2, iclass 28, count 0 2006.168.08:11:40.89#ibcon#*mode == 0, iclass 28, count 0 2006.168.08:11:40.89#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.168.08:11:40.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.08:11:40.89#ibcon#*before write, iclass 28, count 0 2006.168.08:11:40.89#ibcon#enter sib2, iclass 28, count 0 2006.168.08:11:40.89#ibcon#flushed, iclass 28, count 0 2006.168.08:11:40.89#ibcon#about to write, iclass 28, count 0 2006.168.08:11:40.89#ibcon#wrote, iclass 28, count 0 2006.168.08:11:40.89#ibcon#about to read 3, iclass 28, count 0 2006.168.08:11:40.93#ibcon#read 3, iclass 28, count 0 2006.168.08:11:40.93#ibcon#about to read 4, iclass 28, count 0 2006.168.08:11:40.93#ibcon#read 4, iclass 28, count 0 2006.168.08:11:40.93#ibcon#about to read 5, iclass 28, count 0 2006.168.08:11:40.93#ibcon#read 5, iclass 28, count 0 2006.168.08:11:40.93#ibcon#about to read 6, iclass 28, count 0 2006.168.08:11:40.93#ibcon#read 6, iclass 28, count 0 2006.168.08:11:40.93#ibcon#end of sib2, iclass 28, count 0 2006.168.08:11:40.93#ibcon#*after write, iclass 28, count 0 2006.168.08:11:40.93#ibcon#*before return 0, iclass 28, count 0 2006.168.08:11:40.93#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.168.08:11:40.93#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.168.08:11:40.93#ibcon#about to clear, iclass 28 cls_cnt 0 2006.168.08:11:40.93#ibcon#cleared, iclass 28 cls_cnt 0 2006.168.08:11:40.93$vc4f8/vb=2,4 2006.168.08:11:40.93#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.168.08:11:40.93#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.168.08:11:40.93#ibcon#ireg 11 cls_cnt 2 2006.168.08:11:40.93#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.168.08:11:40.99#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.168.08:11:40.99#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.168.08:11:40.99#ibcon#enter wrdev, iclass 30, count 2 2006.168.08:11:40.99#ibcon#first serial, iclass 30, count 2 2006.168.08:11:40.99#ibcon#enter sib2, iclass 30, count 2 2006.168.08:11:40.99#ibcon#flushed, iclass 30, count 2 2006.168.08:11:40.99#ibcon#about to write, iclass 30, count 2 2006.168.08:11:40.99#ibcon#wrote, iclass 30, count 2 2006.168.08:11:40.99#ibcon#about to read 3, iclass 30, count 2 2006.168.08:11:41.01#ibcon#read 3, iclass 30, count 2 2006.168.08:11:41.01#ibcon#about to read 4, iclass 30, count 2 2006.168.08:11:41.01#ibcon#read 4, iclass 30, count 2 2006.168.08:11:41.01#ibcon#about to read 5, iclass 30, count 2 2006.168.08:11:41.01#ibcon#read 5, iclass 30, count 2 2006.168.08:11:41.01#ibcon#about to read 6, iclass 30, count 2 2006.168.08:11:41.01#ibcon#read 6, iclass 30, count 2 2006.168.08:11:41.01#ibcon#end of sib2, iclass 30, count 2 2006.168.08:11:41.01#ibcon#*mode == 0, iclass 30, count 2 2006.168.08:11:41.01#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.168.08:11:41.01#ibcon#[27=AT02-04\r\n] 2006.168.08:11:41.01#ibcon#*before write, iclass 30, count 2 2006.168.08:11:41.01#ibcon#enter sib2, iclass 30, count 2 2006.168.08:11:41.01#ibcon#flushed, iclass 30, count 2 2006.168.08:11:41.01#ibcon#about to write, iclass 30, count 2 2006.168.08:11:41.01#ibcon#wrote, iclass 30, count 2 2006.168.08:11:41.01#ibcon#about to read 3, iclass 30, count 2 2006.168.08:11:41.04#ibcon#read 3, iclass 30, count 2 2006.168.08:11:41.04#ibcon#about to read 4, iclass 30, count 2 2006.168.08:11:41.04#ibcon#read 4, iclass 30, count 2 2006.168.08:11:41.04#ibcon#about to read 5, iclass 30, count 2 2006.168.08:11:41.04#ibcon#read 5, iclass 30, count 2 2006.168.08:11:41.04#ibcon#about to read 6, iclass 30, count 2 2006.168.08:11:41.04#ibcon#read 6, iclass 30, count 2 2006.168.08:11:41.04#ibcon#end of sib2, iclass 30, count 2 2006.168.08:11:41.04#ibcon#*after write, iclass 30, count 2 2006.168.08:11:41.04#ibcon#*before return 0, iclass 30, count 2 2006.168.08:11:41.04#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.168.08:11:41.04#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.168.08:11:41.04#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.168.08:11:41.04#ibcon#ireg 7 cls_cnt 0 2006.168.08:11:41.04#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.168.08:11:41.16#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.168.08:11:41.16#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.168.08:11:41.16#ibcon#enter wrdev, iclass 30, count 0 2006.168.08:11:41.16#ibcon#first serial, iclass 30, count 0 2006.168.08:11:41.16#ibcon#enter sib2, iclass 30, count 0 2006.168.08:11:41.16#ibcon#flushed, iclass 30, count 0 2006.168.08:11:41.16#ibcon#about to write, iclass 30, count 0 2006.168.08:11:41.16#ibcon#wrote, iclass 30, count 0 2006.168.08:11:41.16#ibcon#about to read 3, iclass 30, count 0 2006.168.08:11:41.18#ibcon#read 3, iclass 30, count 0 2006.168.08:11:41.18#ibcon#about to read 4, iclass 30, count 0 2006.168.08:11:41.18#ibcon#read 4, iclass 30, count 0 2006.168.08:11:41.18#ibcon#about to read 5, iclass 30, count 0 2006.168.08:11:41.18#ibcon#read 5, iclass 30, count 0 2006.168.08:11:41.18#ibcon#about to read 6, iclass 30, count 0 2006.168.08:11:41.18#ibcon#read 6, iclass 30, count 0 2006.168.08:11:41.18#ibcon#end of sib2, iclass 30, count 0 2006.168.08:11:41.18#ibcon#*mode == 0, iclass 30, count 0 2006.168.08:11:41.18#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.168.08:11:41.18#ibcon#[27=USB\r\n] 2006.168.08:11:41.18#ibcon#*before write, iclass 30, count 0 2006.168.08:11:41.18#ibcon#enter sib2, iclass 30, count 0 2006.168.08:11:41.18#ibcon#flushed, iclass 30, count 0 2006.168.08:11:41.18#ibcon#about to write, iclass 30, count 0 2006.168.08:11:41.18#ibcon#wrote, iclass 30, count 0 2006.168.08:11:41.18#ibcon#about to read 3, iclass 30, count 0 2006.168.08:11:41.21#ibcon#read 3, iclass 30, count 0 2006.168.08:11:41.21#ibcon#about to read 4, iclass 30, count 0 2006.168.08:11:41.21#ibcon#read 4, iclass 30, count 0 2006.168.08:11:41.21#ibcon#about to read 5, iclass 30, count 0 2006.168.08:11:41.21#ibcon#read 5, iclass 30, count 0 2006.168.08:11:41.21#ibcon#about to read 6, iclass 30, count 0 2006.168.08:11:41.21#ibcon#read 6, iclass 30, count 0 2006.168.08:11:41.21#ibcon#end of sib2, iclass 30, count 0 2006.168.08:11:41.21#ibcon#*after write, iclass 30, count 0 2006.168.08:11:41.21#ibcon#*before return 0, iclass 30, count 0 2006.168.08:11:41.21#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.168.08:11:41.21#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.168.08:11:41.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.168.08:11:41.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.168.08:11:41.21$vc4f8/vblo=3,656.99 2006.168.08:11:41.21#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.168.08:11:41.21#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.168.08:11:41.21#ibcon#ireg 17 cls_cnt 0 2006.168.08:11:41.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:11:41.21#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:11:41.21#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:11:41.21#ibcon#enter wrdev, iclass 32, count 0 2006.168.08:11:41.21#ibcon#first serial, iclass 32, count 0 2006.168.08:11:41.21#ibcon#enter sib2, iclass 32, count 0 2006.168.08:11:41.21#ibcon#flushed, iclass 32, count 0 2006.168.08:11:41.21#ibcon#about to write, iclass 32, count 0 2006.168.08:11:41.21#ibcon#wrote, iclass 32, count 0 2006.168.08:11:41.21#ibcon#about to read 3, iclass 32, count 0 2006.168.08:11:41.23#ibcon#read 3, iclass 32, count 0 2006.168.08:11:41.23#ibcon#about to read 4, iclass 32, count 0 2006.168.08:11:41.23#ibcon#read 4, iclass 32, count 0 2006.168.08:11:41.23#ibcon#about to read 5, iclass 32, count 0 2006.168.08:11:41.23#ibcon#read 5, iclass 32, count 0 2006.168.08:11:41.23#ibcon#about to read 6, iclass 32, count 0 2006.168.08:11:41.23#ibcon#read 6, iclass 32, count 0 2006.168.08:11:41.23#ibcon#end of sib2, iclass 32, count 0 2006.168.08:11:41.23#ibcon#*mode == 0, iclass 32, count 0 2006.168.08:11:41.23#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.168.08:11:41.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.08:11:41.23#ibcon#*before write, iclass 32, count 0 2006.168.08:11:41.23#ibcon#enter sib2, iclass 32, count 0 2006.168.08:11:41.23#ibcon#flushed, iclass 32, count 0 2006.168.08:11:41.23#ibcon#about to write, iclass 32, count 0 2006.168.08:11:41.23#ibcon#wrote, iclass 32, count 0 2006.168.08:11:41.23#ibcon#about to read 3, iclass 32, count 0 2006.168.08:11:41.27#ibcon#read 3, iclass 32, count 0 2006.168.08:11:41.27#ibcon#about to read 4, iclass 32, count 0 2006.168.08:11:41.27#ibcon#read 4, iclass 32, count 0 2006.168.08:11:41.27#ibcon#about to read 5, iclass 32, count 0 2006.168.08:11:41.27#ibcon#read 5, iclass 32, count 0 2006.168.08:11:41.27#ibcon#about to read 6, iclass 32, count 0 2006.168.08:11:41.27#ibcon#read 6, iclass 32, count 0 2006.168.08:11:41.27#ibcon#end of sib2, iclass 32, count 0 2006.168.08:11:41.27#ibcon#*after write, iclass 32, count 0 2006.168.08:11:41.27#ibcon#*before return 0, iclass 32, count 0 2006.168.08:11:41.27#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:11:41.27#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:11:41.27#ibcon#about to clear, iclass 32 cls_cnt 0 2006.168.08:11:41.27#ibcon#cleared, iclass 32 cls_cnt 0 2006.168.08:11:41.27$vc4f8/vb=3,4 2006.168.08:11:41.27#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.168.08:11:41.27#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.168.08:11:41.27#ibcon#ireg 11 cls_cnt 2 2006.168.08:11:41.27#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.168.08:11:41.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.168.08:11:41.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.168.08:11:41.34#ibcon#enter wrdev, iclass 34, count 2 2006.168.08:11:41.34#ibcon#first serial, iclass 34, count 2 2006.168.08:11:41.34#ibcon#enter sib2, iclass 34, count 2 2006.168.08:11:41.34#ibcon#flushed, iclass 34, count 2 2006.168.08:11:41.34#ibcon#about to write, iclass 34, count 2 2006.168.08:11:41.34#ibcon#wrote, iclass 34, count 2 2006.168.08:11:41.34#ibcon#about to read 3, iclass 34, count 2 2006.168.08:11:41.35#ibcon#read 3, iclass 34, count 2 2006.168.08:11:41.35#ibcon#about to read 4, iclass 34, count 2 2006.168.08:11:41.35#ibcon#read 4, iclass 34, count 2 2006.168.08:11:41.35#ibcon#about to read 5, iclass 34, count 2 2006.168.08:11:41.35#ibcon#read 5, iclass 34, count 2 2006.168.08:11:41.35#ibcon#about to read 6, iclass 34, count 2 2006.168.08:11:41.35#ibcon#read 6, iclass 34, count 2 2006.168.08:11:41.35#ibcon#end of sib2, iclass 34, count 2 2006.168.08:11:41.35#ibcon#*mode == 0, iclass 34, count 2 2006.168.08:11:41.35#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.168.08:11:41.35#ibcon#[27=AT03-04\r\n] 2006.168.08:11:41.35#ibcon#*before write, iclass 34, count 2 2006.168.08:11:41.35#ibcon#enter sib2, iclass 34, count 2 2006.168.08:11:41.35#ibcon#flushed, iclass 34, count 2 2006.168.08:11:41.35#ibcon#about to write, iclass 34, count 2 2006.168.08:11:41.35#ibcon#wrote, iclass 34, count 2 2006.168.08:11:41.35#ibcon#about to read 3, iclass 34, count 2 2006.168.08:11:41.38#ibcon#read 3, iclass 34, count 2 2006.168.08:11:41.38#ibcon#about to read 4, iclass 34, count 2 2006.168.08:11:41.38#ibcon#read 4, iclass 34, count 2 2006.168.08:11:41.38#ibcon#about to read 5, iclass 34, count 2 2006.168.08:11:41.38#ibcon#read 5, iclass 34, count 2 2006.168.08:11:41.38#ibcon#about to read 6, iclass 34, count 2 2006.168.08:11:41.38#ibcon#read 6, iclass 34, count 2 2006.168.08:11:41.38#ibcon#end of sib2, iclass 34, count 2 2006.168.08:11:41.38#ibcon#*after write, iclass 34, count 2 2006.168.08:11:41.38#ibcon#*before return 0, iclass 34, count 2 2006.168.08:11:41.38#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.168.08:11:41.38#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.168.08:11:41.38#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.168.08:11:41.38#ibcon#ireg 7 cls_cnt 0 2006.168.08:11:41.38#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.168.08:11:41.50#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.168.08:11:41.50#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.168.08:11:41.50#ibcon#enter wrdev, iclass 34, count 0 2006.168.08:11:41.50#ibcon#first serial, iclass 34, count 0 2006.168.08:11:41.50#ibcon#enter sib2, iclass 34, count 0 2006.168.08:11:41.50#ibcon#flushed, iclass 34, count 0 2006.168.08:11:41.50#ibcon#about to write, iclass 34, count 0 2006.168.08:11:41.50#ibcon#wrote, iclass 34, count 0 2006.168.08:11:41.50#ibcon#about to read 3, iclass 34, count 0 2006.168.08:11:41.52#ibcon#read 3, iclass 34, count 0 2006.168.08:11:41.52#ibcon#about to read 4, iclass 34, count 0 2006.168.08:11:41.52#ibcon#read 4, iclass 34, count 0 2006.168.08:11:41.52#ibcon#about to read 5, iclass 34, count 0 2006.168.08:11:41.52#ibcon#read 5, iclass 34, count 0 2006.168.08:11:41.52#ibcon#about to read 6, iclass 34, count 0 2006.168.08:11:41.52#ibcon#read 6, iclass 34, count 0 2006.168.08:11:41.52#ibcon#end of sib2, iclass 34, count 0 2006.168.08:11:41.52#ibcon#*mode == 0, iclass 34, count 0 2006.168.08:11:41.52#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.168.08:11:41.52#ibcon#[27=USB\r\n] 2006.168.08:11:41.52#ibcon#*before write, iclass 34, count 0 2006.168.08:11:41.52#ibcon#enter sib2, iclass 34, count 0 2006.168.08:11:41.52#ibcon#flushed, iclass 34, count 0 2006.168.08:11:41.52#ibcon#about to write, iclass 34, count 0 2006.168.08:11:41.52#ibcon#wrote, iclass 34, count 0 2006.168.08:11:41.52#ibcon#about to read 3, iclass 34, count 0 2006.168.08:11:41.55#ibcon#read 3, iclass 34, count 0 2006.168.08:11:41.55#ibcon#about to read 4, iclass 34, count 0 2006.168.08:11:41.55#ibcon#read 4, iclass 34, count 0 2006.168.08:11:41.55#ibcon#about to read 5, iclass 34, count 0 2006.168.08:11:41.55#ibcon#read 5, iclass 34, count 0 2006.168.08:11:41.55#ibcon#about to read 6, iclass 34, count 0 2006.168.08:11:41.55#ibcon#read 6, iclass 34, count 0 2006.168.08:11:41.55#ibcon#end of sib2, iclass 34, count 0 2006.168.08:11:41.55#ibcon#*after write, iclass 34, count 0 2006.168.08:11:41.55#ibcon#*before return 0, iclass 34, count 0 2006.168.08:11:41.55#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.168.08:11:41.55#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.168.08:11:41.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.168.08:11:41.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.168.08:11:41.55$vc4f8/vblo=4,712.99 2006.168.08:11:41.55#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.168.08:11:41.55#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.168.08:11:41.55#ibcon#ireg 17 cls_cnt 0 2006.168.08:11:41.55#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.168.08:11:41.55#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.168.08:11:41.55#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.168.08:11:41.55#ibcon#enter wrdev, iclass 36, count 0 2006.168.08:11:41.55#ibcon#first serial, iclass 36, count 0 2006.168.08:11:41.55#ibcon#enter sib2, iclass 36, count 0 2006.168.08:11:41.55#ibcon#flushed, iclass 36, count 0 2006.168.08:11:41.55#ibcon#about to write, iclass 36, count 0 2006.168.08:11:41.55#ibcon#wrote, iclass 36, count 0 2006.168.08:11:41.55#ibcon#about to read 3, iclass 36, count 0 2006.168.08:11:41.57#ibcon#read 3, iclass 36, count 0 2006.168.08:11:41.57#ibcon#about to read 4, iclass 36, count 0 2006.168.08:11:41.57#ibcon#read 4, iclass 36, count 0 2006.168.08:11:41.57#ibcon#about to read 5, iclass 36, count 0 2006.168.08:11:41.57#ibcon#read 5, iclass 36, count 0 2006.168.08:11:41.57#ibcon#about to read 6, iclass 36, count 0 2006.168.08:11:41.57#ibcon#read 6, iclass 36, count 0 2006.168.08:11:41.57#ibcon#end of sib2, iclass 36, count 0 2006.168.08:11:41.57#ibcon#*mode == 0, iclass 36, count 0 2006.168.08:11:41.57#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.168.08:11:41.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.08:11:41.57#ibcon#*before write, iclass 36, count 0 2006.168.08:11:41.57#ibcon#enter sib2, iclass 36, count 0 2006.168.08:11:41.57#ibcon#flushed, iclass 36, count 0 2006.168.08:11:41.57#ibcon#about to write, iclass 36, count 0 2006.168.08:11:41.57#ibcon#wrote, iclass 36, count 0 2006.168.08:11:41.57#ibcon#about to read 3, iclass 36, count 0 2006.168.08:11:41.61#ibcon#read 3, iclass 36, count 0 2006.168.08:11:41.61#ibcon#about to read 4, iclass 36, count 0 2006.168.08:11:41.61#ibcon#read 4, iclass 36, count 0 2006.168.08:11:41.61#ibcon#about to read 5, iclass 36, count 0 2006.168.08:11:41.61#ibcon#read 5, iclass 36, count 0 2006.168.08:11:41.61#ibcon#about to read 6, iclass 36, count 0 2006.168.08:11:41.61#ibcon#read 6, iclass 36, count 0 2006.168.08:11:41.61#ibcon#end of sib2, iclass 36, count 0 2006.168.08:11:41.61#ibcon#*after write, iclass 36, count 0 2006.168.08:11:41.61#ibcon#*before return 0, iclass 36, count 0 2006.168.08:11:41.61#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.168.08:11:41.61#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.168.08:11:41.61#ibcon#about to clear, iclass 36 cls_cnt 0 2006.168.08:11:41.61#ibcon#cleared, iclass 36 cls_cnt 0 2006.168.08:11:41.61$vc4f8/vb=4,4 2006.168.08:11:41.61#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.168.08:11:41.61#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.168.08:11:41.61#ibcon#ireg 11 cls_cnt 2 2006.168.08:11:41.61#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.168.08:11:41.67#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.168.08:11:41.67#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.168.08:11:41.67#ibcon#enter wrdev, iclass 38, count 2 2006.168.08:11:41.67#ibcon#first serial, iclass 38, count 2 2006.168.08:11:41.67#ibcon#enter sib2, iclass 38, count 2 2006.168.08:11:41.67#ibcon#flushed, iclass 38, count 2 2006.168.08:11:41.67#ibcon#about to write, iclass 38, count 2 2006.168.08:11:41.67#ibcon#wrote, iclass 38, count 2 2006.168.08:11:41.67#ibcon#about to read 3, iclass 38, count 2 2006.168.08:11:41.69#ibcon#read 3, iclass 38, count 2 2006.168.08:11:41.69#ibcon#about to read 4, iclass 38, count 2 2006.168.08:11:41.69#ibcon#read 4, iclass 38, count 2 2006.168.08:11:41.69#ibcon#about to read 5, iclass 38, count 2 2006.168.08:11:41.69#ibcon#read 5, iclass 38, count 2 2006.168.08:11:41.69#ibcon#about to read 6, iclass 38, count 2 2006.168.08:11:41.69#ibcon#read 6, iclass 38, count 2 2006.168.08:11:41.69#ibcon#end of sib2, iclass 38, count 2 2006.168.08:11:41.69#ibcon#*mode == 0, iclass 38, count 2 2006.168.08:11:41.69#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.168.08:11:41.69#ibcon#[27=AT04-04\r\n] 2006.168.08:11:41.69#ibcon#*before write, iclass 38, count 2 2006.168.08:11:41.69#ibcon#enter sib2, iclass 38, count 2 2006.168.08:11:41.69#ibcon#flushed, iclass 38, count 2 2006.168.08:11:41.69#ibcon#about to write, iclass 38, count 2 2006.168.08:11:41.69#ibcon#wrote, iclass 38, count 2 2006.168.08:11:41.69#ibcon#about to read 3, iclass 38, count 2 2006.168.08:11:41.72#ibcon#read 3, iclass 38, count 2 2006.168.08:11:41.72#ibcon#about to read 4, iclass 38, count 2 2006.168.08:11:41.72#ibcon#read 4, iclass 38, count 2 2006.168.08:11:41.72#ibcon#about to read 5, iclass 38, count 2 2006.168.08:11:41.72#ibcon#read 5, iclass 38, count 2 2006.168.08:11:41.72#ibcon#about to read 6, iclass 38, count 2 2006.168.08:11:41.72#ibcon#read 6, iclass 38, count 2 2006.168.08:11:41.72#ibcon#end of sib2, iclass 38, count 2 2006.168.08:11:41.72#ibcon#*after write, iclass 38, count 2 2006.168.08:11:41.72#ibcon#*before return 0, iclass 38, count 2 2006.168.08:11:41.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.168.08:11:41.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.168.08:11:41.72#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.168.08:11:41.72#ibcon#ireg 7 cls_cnt 0 2006.168.08:11:41.72#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.168.08:11:41.84#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.168.08:11:41.84#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.168.08:11:41.84#ibcon#enter wrdev, iclass 38, count 0 2006.168.08:11:41.84#ibcon#first serial, iclass 38, count 0 2006.168.08:11:41.84#ibcon#enter sib2, iclass 38, count 0 2006.168.08:11:41.84#ibcon#flushed, iclass 38, count 0 2006.168.08:11:41.84#ibcon#about to write, iclass 38, count 0 2006.168.08:11:41.84#ibcon#wrote, iclass 38, count 0 2006.168.08:11:41.84#ibcon#about to read 3, iclass 38, count 0 2006.168.08:11:41.86#ibcon#read 3, iclass 38, count 0 2006.168.08:11:41.86#ibcon#about to read 4, iclass 38, count 0 2006.168.08:11:41.86#ibcon#read 4, iclass 38, count 0 2006.168.08:11:41.86#ibcon#about to read 5, iclass 38, count 0 2006.168.08:11:41.86#ibcon#read 5, iclass 38, count 0 2006.168.08:11:41.86#ibcon#about to read 6, iclass 38, count 0 2006.168.08:11:41.86#ibcon#read 6, iclass 38, count 0 2006.168.08:11:41.86#ibcon#end of sib2, iclass 38, count 0 2006.168.08:11:41.86#ibcon#*mode == 0, iclass 38, count 0 2006.168.08:11:41.86#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.168.08:11:41.86#ibcon#[27=USB\r\n] 2006.168.08:11:41.86#ibcon#*before write, iclass 38, count 0 2006.168.08:11:41.86#ibcon#enter sib2, iclass 38, count 0 2006.168.08:11:41.86#ibcon#flushed, iclass 38, count 0 2006.168.08:11:41.86#ibcon#about to write, iclass 38, count 0 2006.168.08:11:41.86#ibcon#wrote, iclass 38, count 0 2006.168.08:11:41.86#ibcon#about to read 3, iclass 38, count 0 2006.168.08:11:41.89#ibcon#read 3, iclass 38, count 0 2006.168.08:11:41.89#ibcon#about to read 4, iclass 38, count 0 2006.168.08:11:41.89#ibcon#read 4, iclass 38, count 0 2006.168.08:11:41.89#ibcon#about to read 5, iclass 38, count 0 2006.168.08:11:41.89#ibcon#read 5, iclass 38, count 0 2006.168.08:11:41.89#ibcon#about to read 6, iclass 38, count 0 2006.168.08:11:41.89#ibcon#read 6, iclass 38, count 0 2006.168.08:11:41.89#ibcon#end of sib2, iclass 38, count 0 2006.168.08:11:41.89#ibcon#*after write, iclass 38, count 0 2006.168.08:11:41.89#ibcon#*before return 0, iclass 38, count 0 2006.168.08:11:41.89#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.168.08:11:41.89#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.168.08:11:41.89#ibcon#about to clear, iclass 38 cls_cnt 0 2006.168.08:11:41.89#ibcon#cleared, iclass 38 cls_cnt 0 2006.168.08:11:41.89$vc4f8/vblo=5,744.99 2006.168.08:11:41.89#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.168.08:11:41.89#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.168.08:11:41.89#ibcon#ireg 17 cls_cnt 0 2006.168.08:11:41.89#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:11:41.89#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:11:41.89#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:11:41.89#ibcon#enter wrdev, iclass 40, count 0 2006.168.08:11:41.89#ibcon#first serial, iclass 40, count 0 2006.168.08:11:41.89#ibcon#enter sib2, iclass 40, count 0 2006.168.08:11:41.89#ibcon#flushed, iclass 40, count 0 2006.168.08:11:41.89#ibcon#about to write, iclass 40, count 0 2006.168.08:11:41.89#ibcon#wrote, iclass 40, count 0 2006.168.08:11:41.89#ibcon#about to read 3, iclass 40, count 0 2006.168.08:11:41.91#ibcon#read 3, iclass 40, count 0 2006.168.08:11:41.91#ibcon#about to read 4, iclass 40, count 0 2006.168.08:11:41.91#ibcon#read 4, iclass 40, count 0 2006.168.08:11:41.91#ibcon#about to read 5, iclass 40, count 0 2006.168.08:11:41.91#ibcon#read 5, iclass 40, count 0 2006.168.08:11:41.91#ibcon#about to read 6, iclass 40, count 0 2006.168.08:11:41.91#ibcon#read 6, iclass 40, count 0 2006.168.08:11:41.91#ibcon#end of sib2, iclass 40, count 0 2006.168.08:11:41.91#ibcon#*mode == 0, iclass 40, count 0 2006.168.08:11:41.91#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.168.08:11:41.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.08:11:41.91#ibcon#*before write, iclass 40, count 0 2006.168.08:11:41.91#ibcon#enter sib2, iclass 40, count 0 2006.168.08:11:41.91#ibcon#flushed, iclass 40, count 0 2006.168.08:11:41.91#ibcon#about to write, iclass 40, count 0 2006.168.08:11:41.91#ibcon#wrote, iclass 40, count 0 2006.168.08:11:41.91#ibcon#about to read 3, iclass 40, count 0 2006.168.08:11:41.95#ibcon#read 3, iclass 40, count 0 2006.168.08:11:41.95#ibcon#about to read 4, iclass 40, count 0 2006.168.08:11:41.95#ibcon#read 4, iclass 40, count 0 2006.168.08:11:41.95#ibcon#about to read 5, iclass 40, count 0 2006.168.08:11:41.95#ibcon#read 5, iclass 40, count 0 2006.168.08:11:41.95#ibcon#about to read 6, iclass 40, count 0 2006.168.08:11:41.95#ibcon#read 6, iclass 40, count 0 2006.168.08:11:41.95#ibcon#end of sib2, iclass 40, count 0 2006.168.08:11:41.95#ibcon#*after write, iclass 40, count 0 2006.168.08:11:41.95#ibcon#*before return 0, iclass 40, count 0 2006.168.08:11:41.95#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:11:41.95#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:11:41.95#ibcon#about to clear, iclass 40 cls_cnt 0 2006.168.08:11:41.95#ibcon#cleared, iclass 40 cls_cnt 0 2006.168.08:11:41.95$vc4f8/vb=5,4 2006.168.08:11:41.95#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.168.08:11:41.95#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.168.08:11:41.95#ibcon#ireg 11 cls_cnt 2 2006.168.08:11:41.95#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.168.08:11:42.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.168.08:11:42.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.168.08:11:42.02#ibcon#enter wrdev, iclass 4, count 2 2006.168.08:11:42.02#ibcon#first serial, iclass 4, count 2 2006.168.08:11:42.02#ibcon#enter sib2, iclass 4, count 2 2006.168.08:11:42.02#ibcon#flushed, iclass 4, count 2 2006.168.08:11:42.02#ibcon#about to write, iclass 4, count 2 2006.168.08:11:42.02#ibcon#wrote, iclass 4, count 2 2006.168.08:11:42.02#ibcon#about to read 3, iclass 4, count 2 2006.168.08:11:42.03#ibcon#read 3, iclass 4, count 2 2006.168.08:11:42.03#ibcon#about to read 4, iclass 4, count 2 2006.168.08:11:42.03#ibcon#read 4, iclass 4, count 2 2006.168.08:11:42.03#ibcon#about to read 5, iclass 4, count 2 2006.168.08:11:42.03#ibcon#read 5, iclass 4, count 2 2006.168.08:11:42.03#ibcon#about to read 6, iclass 4, count 2 2006.168.08:11:42.03#ibcon#read 6, iclass 4, count 2 2006.168.08:11:42.03#ibcon#end of sib2, iclass 4, count 2 2006.168.08:11:42.03#ibcon#*mode == 0, iclass 4, count 2 2006.168.08:11:42.03#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.168.08:11:42.03#ibcon#[27=AT05-04\r\n] 2006.168.08:11:42.03#ibcon#*before write, iclass 4, count 2 2006.168.08:11:42.03#ibcon#enter sib2, iclass 4, count 2 2006.168.08:11:42.03#ibcon#flushed, iclass 4, count 2 2006.168.08:11:42.03#ibcon#about to write, iclass 4, count 2 2006.168.08:11:42.03#ibcon#wrote, iclass 4, count 2 2006.168.08:11:42.03#ibcon#about to read 3, iclass 4, count 2 2006.168.08:11:42.06#ibcon#read 3, iclass 4, count 2 2006.168.08:11:42.06#ibcon#about to read 4, iclass 4, count 2 2006.168.08:11:42.06#ibcon#read 4, iclass 4, count 2 2006.168.08:11:42.06#ibcon#about to read 5, iclass 4, count 2 2006.168.08:11:42.06#ibcon#read 5, iclass 4, count 2 2006.168.08:11:42.06#ibcon#about to read 6, iclass 4, count 2 2006.168.08:11:42.06#ibcon#read 6, iclass 4, count 2 2006.168.08:11:42.06#ibcon#end of sib2, iclass 4, count 2 2006.168.08:11:42.06#ibcon#*after write, iclass 4, count 2 2006.168.08:11:42.06#ibcon#*before return 0, iclass 4, count 2 2006.168.08:11:42.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.168.08:11:42.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.168.08:11:42.06#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.168.08:11:42.06#ibcon#ireg 7 cls_cnt 0 2006.168.08:11:42.06#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.168.08:11:42.18#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.168.08:11:42.18#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.168.08:11:42.18#ibcon#enter wrdev, iclass 4, count 0 2006.168.08:11:42.18#ibcon#first serial, iclass 4, count 0 2006.168.08:11:42.18#ibcon#enter sib2, iclass 4, count 0 2006.168.08:11:42.18#ibcon#flushed, iclass 4, count 0 2006.168.08:11:42.18#ibcon#about to write, iclass 4, count 0 2006.168.08:11:42.18#ibcon#wrote, iclass 4, count 0 2006.168.08:11:42.18#ibcon#about to read 3, iclass 4, count 0 2006.168.08:11:42.22#ibcon#read 3, iclass 4, count 0 2006.168.08:11:42.22#ibcon#about to read 4, iclass 4, count 0 2006.168.08:11:42.22#ibcon#read 4, iclass 4, count 0 2006.168.08:11:42.22#ibcon#about to read 5, iclass 4, count 0 2006.168.08:11:42.22#ibcon#read 5, iclass 4, count 0 2006.168.08:11:42.22#ibcon#about to read 6, iclass 4, count 0 2006.168.08:11:42.22#ibcon#read 6, iclass 4, count 0 2006.168.08:11:42.22#ibcon#end of sib2, iclass 4, count 0 2006.168.08:11:42.22#ibcon#*mode == 0, iclass 4, count 0 2006.168.08:11:42.22#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.168.08:11:42.22#ibcon#[27=USB\r\n] 2006.168.08:11:42.22#ibcon#*before write, iclass 4, count 0 2006.168.08:11:42.22#ibcon#enter sib2, iclass 4, count 0 2006.168.08:11:42.22#ibcon#flushed, iclass 4, count 0 2006.168.08:11:42.22#ibcon#about to write, iclass 4, count 0 2006.168.08:11:42.22#ibcon#wrote, iclass 4, count 0 2006.168.08:11:42.22#ibcon#about to read 3, iclass 4, count 0 2006.168.08:11:42.25#ibcon#read 3, iclass 4, count 0 2006.168.08:11:42.25#ibcon#about to read 4, iclass 4, count 0 2006.168.08:11:42.25#ibcon#read 4, iclass 4, count 0 2006.168.08:11:42.25#ibcon#about to read 5, iclass 4, count 0 2006.168.08:11:42.25#ibcon#read 5, iclass 4, count 0 2006.168.08:11:42.25#ibcon#about to read 6, iclass 4, count 0 2006.168.08:11:42.25#ibcon#read 6, iclass 4, count 0 2006.168.08:11:42.25#ibcon#end of sib2, iclass 4, count 0 2006.168.08:11:42.25#ibcon#*after write, iclass 4, count 0 2006.168.08:11:42.25#ibcon#*before return 0, iclass 4, count 0 2006.168.08:11:42.25#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.168.08:11:42.25#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.168.08:11:42.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.168.08:11:42.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.168.08:11:42.25$vc4f8/vblo=6,752.99 2006.168.08:11:42.25#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.168.08:11:42.25#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.168.08:11:42.25#ibcon#ireg 17 cls_cnt 0 2006.168.08:11:42.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.168.08:11:42.25#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.168.08:11:42.25#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.168.08:11:42.25#ibcon#enter wrdev, iclass 6, count 0 2006.168.08:11:42.25#ibcon#first serial, iclass 6, count 0 2006.168.08:11:42.25#ibcon#enter sib2, iclass 6, count 0 2006.168.08:11:42.25#ibcon#flushed, iclass 6, count 0 2006.168.08:11:42.25#ibcon#about to write, iclass 6, count 0 2006.168.08:11:42.25#ibcon#wrote, iclass 6, count 0 2006.168.08:11:42.25#ibcon#about to read 3, iclass 6, count 0 2006.168.08:11:42.27#ibcon#read 3, iclass 6, count 0 2006.168.08:11:42.27#ibcon#about to read 4, iclass 6, count 0 2006.168.08:11:42.27#ibcon#read 4, iclass 6, count 0 2006.168.08:11:42.27#ibcon#about to read 5, iclass 6, count 0 2006.168.08:11:42.27#ibcon#read 5, iclass 6, count 0 2006.168.08:11:42.27#ibcon#about to read 6, iclass 6, count 0 2006.168.08:11:42.27#ibcon#read 6, iclass 6, count 0 2006.168.08:11:42.27#ibcon#end of sib2, iclass 6, count 0 2006.168.08:11:42.27#ibcon#*mode == 0, iclass 6, count 0 2006.168.08:11:42.27#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.168.08:11:42.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.08:11:42.27#ibcon#*before write, iclass 6, count 0 2006.168.08:11:42.27#ibcon#enter sib2, iclass 6, count 0 2006.168.08:11:42.27#ibcon#flushed, iclass 6, count 0 2006.168.08:11:42.27#ibcon#about to write, iclass 6, count 0 2006.168.08:11:42.27#ibcon#wrote, iclass 6, count 0 2006.168.08:11:42.27#ibcon#about to read 3, iclass 6, count 0 2006.168.08:11:42.31#ibcon#read 3, iclass 6, count 0 2006.168.08:11:42.31#ibcon#about to read 4, iclass 6, count 0 2006.168.08:11:42.31#ibcon#read 4, iclass 6, count 0 2006.168.08:11:42.31#ibcon#about to read 5, iclass 6, count 0 2006.168.08:11:42.31#ibcon#read 5, iclass 6, count 0 2006.168.08:11:42.31#ibcon#about to read 6, iclass 6, count 0 2006.168.08:11:42.31#ibcon#read 6, iclass 6, count 0 2006.168.08:11:42.31#ibcon#end of sib2, iclass 6, count 0 2006.168.08:11:42.31#ibcon#*after write, iclass 6, count 0 2006.168.08:11:42.31#ibcon#*before return 0, iclass 6, count 0 2006.168.08:11:42.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.168.08:11:42.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.168.08:11:42.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.168.08:11:42.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.168.08:11:42.31$vc4f8/vb=6,4 2006.168.08:11:42.31#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.168.08:11:42.31#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.168.08:11:42.31#ibcon#ireg 11 cls_cnt 2 2006.168.08:11:42.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.168.08:11:42.37#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.168.08:11:42.37#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.168.08:11:42.37#ibcon#enter wrdev, iclass 10, count 2 2006.168.08:11:42.37#ibcon#first serial, iclass 10, count 2 2006.168.08:11:42.37#ibcon#enter sib2, iclass 10, count 2 2006.168.08:11:42.37#ibcon#flushed, iclass 10, count 2 2006.168.08:11:42.37#ibcon#about to write, iclass 10, count 2 2006.168.08:11:42.37#ibcon#wrote, iclass 10, count 2 2006.168.08:11:42.37#ibcon#about to read 3, iclass 10, count 2 2006.168.08:11:42.39#ibcon#read 3, iclass 10, count 2 2006.168.08:11:42.39#ibcon#about to read 4, iclass 10, count 2 2006.168.08:11:42.39#ibcon#read 4, iclass 10, count 2 2006.168.08:11:42.39#ibcon#about to read 5, iclass 10, count 2 2006.168.08:11:42.39#ibcon#read 5, iclass 10, count 2 2006.168.08:11:42.39#ibcon#about to read 6, iclass 10, count 2 2006.168.08:11:42.39#ibcon#read 6, iclass 10, count 2 2006.168.08:11:42.39#ibcon#end of sib2, iclass 10, count 2 2006.168.08:11:42.39#ibcon#*mode == 0, iclass 10, count 2 2006.168.08:11:42.39#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.168.08:11:42.39#ibcon#[27=AT06-04\r\n] 2006.168.08:11:42.39#ibcon#*before write, iclass 10, count 2 2006.168.08:11:42.39#ibcon#enter sib2, iclass 10, count 2 2006.168.08:11:42.39#ibcon#flushed, iclass 10, count 2 2006.168.08:11:42.39#ibcon#about to write, iclass 10, count 2 2006.168.08:11:42.39#ibcon#wrote, iclass 10, count 2 2006.168.08:11:42.39#ibcon#about to read 3, iclass 10, count 2 2006.168.08:11:42.42#ibcon#read 3, iclass 10, count 2 2006.168.08:11:42.42#ibcon#about to read 4, iclass 10, count 2 2006.168.08:11:42.42#ibcon#read 4, iclass 10, count 2 2006.168.08:11:42.42#ibcon#about to read 5, iclass 10, count 2 2006.168.08:11:42.42#ibcon#read 5, iclass 10, count 2 2006.168.08:11:42.42#ibcon#about to read 6, iclass 10, count 2 2006.168.08:11:42.42#ibcon#read 6, iclass 10, count 2 2006.168.08:11:42.42#ibcon#end of sib2, iclass 10, count 2 2006.168.08:11:42.42#ibcon#*after write, iclass 10, count 2 2006.168.08:11:42.42#ibcon#*before return 0, iclass 10, count 2 2006.168.08:11:42.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.168.08:11:42.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.168.08:11:42.42#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.168.08:11:42.42#ibcon#ireg 7 cls_cnt 0 2006.168.08:11:42.42#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.168.08:11:42.54#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.168.08:11:42.54#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.168.08:11:42.54#ibcon#enter wrdev, iclass 10, count 0 2006.168.08:11:42.54#ibcon#first serial, iclass 10, count 0 2006.168.08:11:42.54#ibcon#enter sib2, iclass 10, count 0 2006.168.08:11:42.54#ibcon#flushed, iclass 10, count 0 2006.168.08:11:42.54#ibcon#about to write, iclass 10, count 0 2006.168.08:11:42.54#ibcon#wrote, iclass 10, count 0 2006.168.08:11:42.54#ibcon#about to read 3, iclass 10, count 0 2006.168.08:11:42.56#ibcon#read 3, iclass 10, count 0 2006.168.08:11:42.56#ibcon#about to read 4, iclass 10, count 0 2006.168.08:11:42.56#ibcon#read 4, iclass 10, count 0 2006.168.08:11:42.56#ibcon#about to read 5, iclass 10, count 0 2006.168.08:11:42.56#ibcon#read 5, iclass 10, count 0 2006.168.08:11:42.56#ibcon#about to read 6, iclass 10, count 0 2006.168.08:11:42.56#ibcon#read 6, iclass 10, count 0 2006.168.08:11:42.56#ibcon#end of sib2, iclass 10, count 0 2006.168.08:11:42.56#ibcon#*mode == 0, iclass 10, count 0 2006.168.08:11:42.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.168.08:11:42.56#ibcon#[27=USB\r\n] 2006.168.08:11:42.56#ibcon#*before write, iclass 10, count 0 2006.168.08:11:42.56#ibcon#enter sib2, iclass 10, count 0 2006.168.08:11:42.56#ibcon#flushed, iclass 10, count 0 2006.168.08:11:42.56#ibcon#about to write, iclass 10, count 0 2006.168.08:11:42.56#ibcon#wrote, iclass 10, count 0 2006.168.08:11:42.56#ibcon#about to read 3, iclass 10, count 0 2006.168.08:11:42.59#ibcon#read 3, iclass 10, count 0 2006.168.08:11:42.59#ibcon#about to read 4, iclass 10, count 0 2006.168.08:11:42.59#ibcon#read 4, iclass 10, count 0 2006.168.08:11:42.59#ibcon#about to read 5, iclass 10, count 0 2006.168.08:11:42.59#ibcon#read 5, iclass 10, count 0 2006.168.08:11:42.59#ibcon#about to read 6, iclass 10, count 0 2006.168.08:11:42.59#ibcon#read 6, iclass 10, count 0 2006.168.08:11:42.59#ibcon#end of sib2, iclass 10, count 0 2006.168.08:11:42.59#ibcon#*after write, iclass 10, count 0 2006.168.08:11:42.59#ibcon#*before return 0, iclass 10, count 0 2006.168.08:11:42.59#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.168.08:11:42.59#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.168.08:11:42.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.168.08:11:42.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.168.08:11:42.59$vc4f8/vabw=wide 2006.168.08:11:42.59#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.168.08:11:42.59#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.168.08:11:42.59#ibcon#ireg 8 cls_cnt 0 2006.168.08:11:42.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.168.08:11:42.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.168.08:11:42.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.168.08:11:42.59#ibcon#enter wrdev, iclass 12, count 0 2006.168.08:11:42.59#ibcon#first serial, iclass 12, count 0 2006.168.08:11:42.59#ibcon#enter sib2, iclass 12, count 0 2006.168.08:11:42.59#ibcon#flushed, iclass 12, count 0 2006.168.08:11:42.59#ibcon#about to write, iclass 12, count 0 2006.168.08:11:42.59#ibcon#wrote, iclass 12, count 0 2006.168.08:11:42.59#ibcon#about to read 3, iclass 12, count 0 2006.168.08:11:42.61#ibcon#read 3, iclass 12, count 0 2006.168.08:11:42.61#ibcon#about to read 4, iclass 12, count 0 2006.168.08:11:42.61#ibcon#read 4, iclass 12, count 0 2006.168.08:11:42.61#ibcon#about to read 5, iclass 12, count 0 2006.168.08:11:42.61#ibcon#read 5, iclass 12, count 0 2006.168.08:11:42.61#ibcon#about to read 6, iclass 12, count 0 2006.168.08:11:42.61#ibcon#read 6, iclass 12, count 0 2006.168.08:11:42.61#ibcon#end of sib2, iclass 12, count 0 2006.168.08:11:42.61#ibcon#*mode == 0, iclass 12, count 0 2006.168.08:11:42.61#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.168.08:11:42.61#ibcon#[25=BW32\r\n] 2006.168.08:11:42.61#ibcon#*before write, iclass 12, count 0 2006.168.08:11:42.61#ibcon#enter sib2, iclass 12, count 0 2006.168.08:11:42.61#ibcon#flushed, iclass 12, count 0 2006.168.08:11:42.61#ibcon#about to write, iclass 12, count 0 2006.168.08:11:42.61#ibcon#wrote, iclass 12, count 0 2006.168.08:11:42.61#ibcon#about to read 3, iclass 12, count 0 2006.168.08:11:42.64#ibcon#read 3, iclass 12, count 0 2006.168.08:11:42.64#ibcon#about to read 4, iclass 12, count 0 2006.168.08:11:42.64#ibcon#read 4, iclass 12, count 0 2006.168.08:11:42.64#ibcon#about to read 5, iclass 12, count 0 2006.168.08:11:42.64#ibcon#read 5, iclass 12, count 0 2006.168.08:11:42.64#ibcon#about to read 6, iclass 12, count 0 2006.168.08:11:42.64#ibcon#read 6, iclass 12, count 0 2006.168.08:11:42.64#ibcon#end of sib2, iclass 12, count 0 2006.168.08:11:42.64#ibcon#*after write, iclass 12, count 0 2006.168.08:11:42.64#ibcon#*before return 0, iclass 12, count 0 2006.168.08:11:42.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.168.08:11:42.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.168.08:11:42.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.168.08:11:42.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.168.08:11:42.64$vc4f8/vbbw=wide 2006.168.08:11:42.64#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.168.08:11:42.64#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.168.08:11:42.64#ibcon#ireg 8 cls_cnt 0 2006.168.08:11:42.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:11:42.71#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:11:42.72#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:11:42.72#ibcon#enter wrdev, iclass 14, count 0 2006.168.08:11:42.72#ibcon#first serial, iclass 14, count 0 2006.168.08:11:42.72#ibcon#enter sib2, iclass 14, count 0 2006.168.08:11:42.72#ibcon#flushed, iclass 14, count 0 2006.168.08:11:42.72#ibcon#about to write, iclass 14, count 0 2006.168.08:11:42.72#ibcon#wrote, iclass 14, count 0 2006.168.08:11:42.72#ibcon#about to read 3, iclass 14, count 0 2006.168.08:11:42.73#ibcon#read 3, iclass 14, count 0 2006.168.08:11:42.73#ibcon#about to read 4, iclass 14, count 0 2006.168.08:11:42.73#ibcon#read 4, iclass 14, count 0 2006.168.08:11:42.73#ibcon#about to read 5, iclass 14, count 0 2006.168.08:11:42.73#ibcon#read 5, iclass 14, count 0 2006.168.08:11:42.73#ibcon#about to read 6, iclass 14, count 0 2006.168.08:11:42.73#ibcon#read 6, iclass 14, count 0 2006.168.08:11:42.73#ibcon#end of sib2, iclass 14, count 0 2006.168.08:11:42.73#ibcon#*mode == 0, iclass 14, count 0 2006.168.08:11:42.73#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.168.08:11:42.73#ibcon#[27=BW32\r\n] 2006.168.08:11:42.73#ibcon#*before write, iclass 14, count 0 2006.168.08:11:42.73#ibcon#enter sib2, iclass 14, count 0 2006.168.08:11:42.73#ibcon#flushed, iclass 14, count 0 2006.168.08:11:42.73#ibcon#about to write, iclass 14, count 0 2006.168.08:11:42.73#ibcon#wrote, iclass 14, count 0 2006.168.08:11:42.73#ibcon#about to read 3, iclass 14, count 0 2006.168.08:11:42.76#ibcon#read 3, iclass 14, count 0 2006.168.08:11:42.76#ibcon#about to read 4, iclass 14, count 0 2006.168.08:11:42.76#ibcon#read 4, iclass 14, count 0 2006.168.08:11:42.76#ibcon#about to read 5, iclass 14, count 0 2006.168.08:11:42.76#ibcon#read 5, iclass 14, count 0 2006.168.08:11:42.76#ibcon#about to read 6, iclass 14, count 0 2006.168.08:11:42.76#ibcon#read 6, iclass 14, count 0 2006.168.08:11:42.76#ibcon#end of sib2, iclass 14, count 0 2006.168.08:11:42.76#ibcon#*after write, iclass 14, count 0 2006.168.08:11:42.76#ibcon#*before return 0, iclass 14, count 0 2006.168.08:11:42.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:11:42.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:11:42.76#ibcon#about to clear, iclass 14 cls_cnt 0 2006.168.08:11:42.76#ibcon#cleared, iclass 14 cls_cnt 0 2006.168.08:11:42.76$4f8m12a/ifd4f 2006.168.08:11:42.76$ifd4f/lo= 2006.168.08:11:42.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.08:11:42.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.08:11:42.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.08:11:42.76$ifd4f/patch= 2006.168.08:11:42.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.08:11:42.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.08:11:42.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.08:11:42.76$4f8m12a/"form=m,16.000,1:2 2006.168.08:11:42.76$4f8m12a/"tpicd 2006.168.08:11:42.76$4f8m12a/echo=off 2006.168.08:11:42.76$4f8m12a/xlog=off 2006.168.08:11:42.76:!2006.168.08:12:10 2006.168.08:11:49.14#trakl#Source acquired 2006.168.08:11:49.14#flagr#flagr/antenna,acquired 2006.168.08:12:10.00:preob 2006.168.08:12:11.14/onsource/TRACKING 2006.168.08:12:11.14:!2006.168.08:12:20 2006.168.08:12:20.00:data_valid=on 2006.168.08:12:20.00:midob 2006.168.08:12:20.14/onsource/TRACKING 2006.168.08:12:20.14/wx/26.95,1004.6,76 2006.168.08:12:20.36/cable/+6.4720E-03 2006.168.08:12:21.45/va/01,08,usb,yes,29,31 2006.168.08:12:21.45/va/02,07,usb,yes,29,31 2006.168.08:12:21.45/va/03,06,usb,yes,31,31 2006.168.08:12:21.45/va/04,07,usb,yes,30,32 2006.168.08:12:21.45/va/05,07,usb,yes,30,32 2006.168.08:12:21.45/va/06,06,usb,yes,29,29 2006.168.08:12:21.45/va/07,06,usb,yes,29,29 2006.168.08:12:21.45/va/08,07,usb,yes,28,27 2006.168.08:12:21.68/valo/01,532.99,yes,locked 2006.168.08:12:21.68/valo/02,572.99,yes,locked 2006.168.08:12:21.68/valo/03,672.99,yes,locked 2006.168.08:12:21.68/valo/04,832.99,yes,locked 2006.168.08:12:21.68/valo/05,652.99,yes,locked 2006.168.08:12:21.68/valo/06,772.99,yes,locked 2006.168.08:12:21.68/valo/07,832.99,yes,locked 2006.168.08:12:21.68/valo/08,852.99,yes,locked 2006.168.08:12:22.77/vb/01,04,usb,yes,29,28 2006.168.08:12:22.77/vb/02,04,usb,yes,31,32 2006.168.08:12:22.77/vb/03,04,usb,yes,27,31 2006.168.08:12:22.77/vb/04,04,usb,yes,28,28 2006.168.08:12:22.77/vb/05,04,usb,yes,27,31 2006.168.08:12:22.77/vb/06,04,usb,yes,28,30 2006.168.08:12:22.77/vb/07,04,usb,yes,30,30 2006.168.08:12:22.77/vb/08,04,usb,yes,27,31 2006.168.08:12:23.00/vblo/01,632.99,yes,locked 2006.168.08:12:23.00/vblo/02,640.99,yes,locked 2006.168.08:12:23.00/vblo/03,656.99,yes,locked 2006.168.08:12:23.00/vblo/04,712.99,yes,locked 2006.168.08:12:23.00/vblo/05,744.99,yes,locked 2006.168.08:12:23.00/vblo/06,752.99,yes,locked 2006.168.08:12:23.00/vblo/07,734.99,yes,locked 2006.168.08:12:23.00/vblo/08,744.99,yes,locked 2006.168.08:12:23.15/vabw/8 2006.168.08:12:23.30/vbbw/8 2006.168.08:12:23.46/xfe/off,on,15.0 2006.168.08:12:23.84/ifatt/23,28,28,28 2006.168.08:12:24.08/fmout-gps/S +4.18E-07 2006.168.08:12:24.16:!2006.168.08:13:20 2006.168.08:13:20.00:data_valid=off 2006.168.08:13:20.00:postob 2006.168.08:13:20.20/cable/+6.4724E-03 2006.168.08:13:20.20/wx/26.95,1004.6,76 2006.168.08:13:21.08/fmout-gps/S +4.18E-07 2006.168.08:13:21.08:scan_name=168-0814,k06168,60 2006.168.08:13:21.09:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.168.08:13:21.14#flagr#flagr/antenna,new-source 2006.168.08:13:22.14:checkk5 2006.168.08:13:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.168.08:13:22.90/chk_autoobs//k5ts2/ autoobs is running! 2006.168.08:13:23.28/chk_autoobs//k5ts3/ autoobs is running! 2006.168.08:13:23.66/chk_autoobs//k5ts4/ autoobs is running! 2006.168.08:13:24.04/chk_obsdata//k5ts1/T1680812??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:13:24.41/chk_obsdata//k5ts2/T1680812??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:13:24.78/chk_obsdata//k5ts3/T1680812??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:13:25.15/chk_obsdata//k5ts4/T1680812??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:13:25.85/k5log//k5ts1_log_newline 2006.168.08:13:26.54/k5log//k5ts2_log_newline 2006.168.08:13:27.23/k5log//k5ts3_log_newline 2006.168.08:13:27.92/k5log//k5ts4_log_newline 2006.168.08:13:27.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.08:13:27.94:4f8m12a=2 2006.168.08:13:27.94$4f8m12a/echo=on 2006.168.08:13:27.94$4f8m12a/pcalon 2006.168.08:13:27.94$pcalon/"no phase cal control is implemented here 2006.168.08:13:27.94$4f8m12a/"tpicd=stop 2006.168.08:13:27.94$4f8m12a/vc4f8 2006.168.08:13:27.94$vc4f8/valo=1,532.99 2006.168.08:13:27.94#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.168.08:13:27.94#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.168.08:13:27.94#ibcon#ireg 17 cls_cnt 0 2006.168.08:13:27.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:13:27.94#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:13:27.94#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:13:27.94#ibcon#enter wrdev, iclass 21, count 0 2006.168.08:13:27.94#ibcon#first serial, iclass 21, count 0 2006.168.08:13:27.94#ibcon#enter sib2, iclass 21, count 0 2006.168.08:13:27.94#ibcon#flushed, iclass 21, count 0 2006.168.08:13:27.94#ibcon#about to write, iclass 21, count 0 2006.168.08:13:27.94#ibcon#wrote, iclass 21, count 0 2006.168.08:13:27.94#ibcon#about to read 3, iclass 21, count 0 2006.168.08:13:27.96#ibcon#read 3, iclass 21, count 0 2006.168.08:13:27.96#ibcon#about to read 4, iclass 21, count 0 2006.168.08:13:27.96#ibcon#read 4, iclass 21, count 0 2006.168.08:13:27.96#ibcon#about to read 5, iclass 21, count 0 2006.168.08:13:27.96#ibcon#read 5, iclass 21, count 0 2006.168.08:13:27.96#ibcon#about to read 6, iclass 21, count 0 2006.168.08:13:27.96#ibcon#read 6, iclass 21, count 0 2006.168.08:13:27.96#ibcon#end of sib2, iclass 21, count 0 2006.168.08:13:27.96#ibcon#*mode == 0, iclass 21, count 0 2006.168.08:13:27.96#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.168.08:13:27.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.08:13:27.96#ibcon#*before write, iclass 21, count 0 2006.168.08:13:27.96#ibcon#enter sib2, iclass 21, count 0 2006.168.08:13:27.96#ibcon#flushed, iclass 21, count 0 2006.168.08:13:27.96#ibcon#about to write, iclass 21, count 0 2006.168.08:13:27.96#ibcon#wrote, iclass 21, count 0 2006.168.08:13:27.96#ibcon#about to read 3, iclass 21, count 0 2006.168.08:13:28.01#ibcon#read 3, iclass 21, count 0 2006.168.08:13:28.01#ibcon#about to read 4, iclass 21, count 0 2006.168.08:13:28.01#ibcon#read 4, iclass 21, count 0 2006.168.08:13:28.01#ibcon#about to read 5, iclass 21, count 0 2006.168.08:13:28.01#ibcon#read 5, iclass 21, count 0 2006.168.08:13:28.01#ibcon#about to read 6, iclass 21, count 0 2006.168.08:13:28.01#ibcon#read 6, iclass 21, count 0 2006.168.08:13:28.01#ibcon#end of sib2, iclass 21, count 0 2006.168.08:13:28.01#ibcon#*after write, iclass 21, count 0 2006.168.08:13:28.01#ibcon#*before return 0, iclass 21, count 0 2006.168.08:13:28.01#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:13:28.01#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:13:28.01#ibcon#about to clear, iclass 21 cls_cnt 0 2006.168.08:13:28.01#ibcon#cleared, iclass 21 cls_cnt 0 2006.168.08:13:28.01$vc4f8/va=1,8 2006.168.08:13:28.01#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.168.08:13:28.01#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.168.08:13:28.01#ibcon#ireg 11 cls_cnt 2 2006.168.08:13:28.01#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.168.08:13:28.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.168.08:13:28.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.168.08:13:28.01#ibcon#enter wrdev, iclass 23, count 2 2006.168.08:13:28.01#ibcon#first serial, iclass 23, count 2 2006.168.08:13:28.01#ibcon#enter sib2, iclass 23, count 2 2006.168.08:13:28.01#ibcon#flushed, iclass 23, count 2 2006.168.08:13:28.01#ibcon#about to write, iclass 23, count 2 2006.168.08:13:28.01#ibcon#wrote, iclass 23, count 2 2006.168.08:13:28.01#ibcon#about to read 3, iclass 23, count 2 2006.168.08:13:28.03#ibcon#read 3, iclass 23, count 2 2006.168.08:13:28.03#ibcon#about to read 4, iclass 23, count 2 2006.168.08:13:28.03#ibcon#read 4, iclass 23, count 2 2006.168.08:13:28.03#ibcon#about to read 5, iclass 23, count 2 2006.168.08:13:28.03#ibcon#read 5, iclass 23, count 2 2006.168.08:13:28.03#ibcon#about to read 6, iclass 23, count 2 2006.168.08:13:28.03#ibcon#read 6, iclass 23, count 2 2006.168.08:13:28.03#ibcon#end of sib2, iclass 23, count 2 2006.168.08:13:28.03#ibcon#*mode == 0, iclass 23, count 2 2006.168.08:13:28.03#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.168.08:13:28.03#ibcon#[25=AT01-08\r\n] 2006.168.08:13:28.03#ibcon#*before write, iclass 23, count 2 2006.168.08:13:28.03#ibcon#enter sib2, iclass 23, count 2 2006.168.08:13:28.03#ibcon#flushed, iclass 23, count 2 2006.168.08:13:28.03#ibcon#about to write, iclass 23, count 2 2006.168.08:13:28.03#ibcon#wrote, iclass 23, count 2 2006.168.08:13:28.03#ibcon#about to read 3, iclass 23, count 2 2006.168.08:13:28.06#ibcon#read 3, iclass 23, count 2 2006.168.08:13:28.06#ibcon#about to read 4, iclass 23, count 2 2006.168.08:13:28.06#ibcon#read 4, iclass 23, count 2 2006.168.08:13:28.06#ibcon#about to read 5, iclass 23, count 2 2006.168.08:13:28.06#ibcon#read 5, iclass 23, count 2 2006.168.08:13:28.06#ibcon#about to read 6, iclass 23, count 2 2006.168.08:13:28.06#ibcon#read 6, iclass 23, count 2 2006.168.08:13:28.06#ibcon#end of sib2, iclass 23, count 2 2006.168.08:13:28.06#ibcon#*after write, iclass 23, count 2 2006.168.08:13:28.06#ibcon#*before return 0, iclass 23, count 2 2006.168.08:13:28.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.168.08:13:28.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.168.08:13:28.06#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.168.08:13:28.06#ibcon#ireg 7 cls_cnt 0 2006.168.08:13:28.06#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.168.08:13:28.18#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.168.08:13:28.18#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.168.08:13:28.18#ibcon#enter wrdev, iclass 23, count 0 2006.168.08:13:28.18#ibcon#first serial, iclass 23, count 0 2006.168.08:13:28.18#ibcon#enter sib2, iclass 23, count 0 2006.168.08:13:28.18#ibcon#flushed, iclass 23, count 0 2006.168.08:13:28.18#ibcon#about to write, iclass 23, count 0 2006.168.08:13:28.18#ibcon#wrote, iclass 23, count 0 2006.168.08:13:28.18#ibcon#about to read 3, iclass 23, count 0 2006.168.08:13:28.20#ibcon#read 3, iclass 23, count 0 2006.168.08:13:28.20#ibcon#about to read 4, iclass 23, count 0 2006.168.08:13:28.20#ibcon#read 4, iclass 23, count 0 2006.168.08:13:28.20#ibcon#about to read 5, iclass 23, count 0 2006.168.08:13:28.20#ibcon#read 5, iclass 23, count 0 2006.168.08:13:28.20#ibcon#about to read 6, iclass 23, count 0 2006.168.08:13:28.20#ibcon#read 6, iclass 23, count 0 2006.168.08:13:28.20#ibcon#end of sib2, iclass 23, count 0 2006.168.08:13:28.20#ibcon#*mode == 0, iclass 23, count 0 2006.168.08:13:28.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.168.08:13:28.20#ibcon#[25=USB\r\n] 2006.168.08:13:28.20#ibcon#*before write, iclass 23, count 0 2006.168.08:13:28.20#ibcon#enter sib2, iclass 23, count 0 2006.168.08:13:28.20#ibcon#flushed, iclass 23, count 0 2006.168.08:13:28.20#ibcon#about to write, iclass 23, count 0 2006.168.08:13:28.20#ibcon#wrote, iclass 23, count 0 2006.168.08:13:28.20#ibcon#about to read 3, iclass 23, count 0 2006.168.08:13:28.23#ibcon#read 3, iclass 23, count 0 2006.168.08:13:28.23#ibcon#about to read 4, iclass 23, count 0 2006.168.08:13:28.23#ibcon#read 4, iclass 23, count 0 2006.168.08:13:28.23#ibcon#about to read 5, iclass 23, count 0 2006.168.08:13:28.23#ibcon#read 5, iclass 23, count 0 2006.168.08:13:28.23#ibcon#about to read 6, iclass 23, count 0 2006.168.08:13:28.23#ibcon#read 6, iclass 23, count 0 2006.168.08:13:28.23#ibcon#end of sib2, iclass 23, count 0 2006.168.08:13:28.23#ibcon#*after write, iclass 23, count 0 2006.168.08:13:28.23#ibcon#*before return 0, iclass 23, count 0 2006.168.08:13:28.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.168.08:13:28.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.168.08:13:28.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.168.08:13:28.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.168.08:13:28.23$vc4f8/valo=2,572.99 2006.168.08:13:28.23#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.168.08:13:28.23#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.168.08:13:28.23#ibcon#ireg 17 cls_cnt 0 2006.168.08:13:28.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.168.08:13:28.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.168.08:13:28.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.168.08:13:28.23#ibcon#enter wrdev, iclass 25, count 0 2006.168.08:13:28.23#ibcon#first serial, iclass 25, count 0 2006.168.08:13:28.23#ibcon#enter sib2, iclass 25, count 0 2006.168.08:13:28.23#ibcon#flushed, iclass 25, count 0 2006.168.08:13:28.23#ibcon#about to write, iclass 25, count 0 2006.168.08:13:28.23#ibcon#wrote, iclass 25, count 0 2006.168.08:13:28.23#ibcon#about to read 3, iclass 25, count 0 2006.168.08:13:28.25#ibcon#read 3, iclass 25, count 0 2006.168.08:13:28.25#ibcon#about to read 4, iclass 25, count 0 2006.168.08:13:28.25#ibcon#read 4, iclass 25, count 0 2006.168.08:13:28.25#ibcon#about to read 5, iclass 25, count 0 2006.168.08:13:28.25#ibcon#read 5, iclass 25, count 0 2006.168.08:13:28.25#ibcon#about to read 6, iclass 25, count 0 2006.168.08:13:28.25#ibcon#read 6, iclass 25, count 0 2006.168.08:13:28.25#ibcon#end of sib2, iclass 25, count 0 2006.168.08:13:28.25#ibcon#*mode == 0, iclass 25, count 0 2006.168.08:13:28.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.168.08:13:28.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.08:13:28.25#ibcon#*before write, iclass 25, count 0 2006.168.08:13:28.25#ibcon#enter sib2, iclass 25, count 0 2006.168.08:13:28.25#ibcon#flushed, iclass 25, count 0 2006.168.08:13:28.25#ibcon#about to write, iclass 25, count 0 2006.168.08:13:28.25#ibcon#wrote, iclass 25, count 0 2006.168.08:13:28.25#ibcon#about to read 3, iclass 25, count 0 2006.168.08:13:28.29#ibcon#read 3, iclass 25, count 0 2006.168.08:13:28.29#ibcon#about to read 4, iclass 25, count 0 2006.168.08:13:28.29#ibcon#read 4, iclass 25, count 0 2006.168.08:13:28.29#ibcon#about to read 5, iclass 25, count 0 2006.168.08:13:28.29#ibcon#read 5, iclass 25, count 0 2006.168.08:13:28.29#ibcon#about to read 6, iclass 25, count 0 2006.168.08:13:28.29#ibcon#read 6, iclass 25, count 0 2006.168.08:13:28.29#ibcon#end of sib2, iclass 25, count 0 2006.168.08:13:28.29#ibcon#*after write, iclass 25, count 0 2006.168.08:13:28.29#ibcon#*before return 0, iclass 25, count 0 2006.168.08:13:28.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.168.08:13:28.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.168.08:13:28.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.168.08:13:28.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.168.08:13:28.29$vc4f8/va=2,7 2006.168.08:13:28.29#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.168.08:13:28.29#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.168.08:13:28.29#ibcon#ireg 11 cls_cnt 2 2006.168.08:13:28.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.168.08:13:28.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.168.08:13:28.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.168.08:13:28.35#ibcon#enter wrdev, iclass 27, count 2 2006.168.08:13:28.35#ibcon#first serial, iclass 27, count 2 2006.168.08:13:28.35#ibcon#enter sib2, iclass 27, count 2 2006.168.08:13:28.35#ibcon#flushed, iclass 27, count 2 2006.168.08:13:28.35#ibcon#about to write, iclass 27, count 2 2006.168.08:13:28.35#ibcon#wrote, iclass 27, count 2 2006.168.08:13:28.35#ibcon#about to read 3, iclass 27, count 2 2006.168.08:13:28.37#ibcon#read 3, iclass 27, count 2 2006.168.08:13:28.37#ibcon#about to read 4, iclass 27, count 2 2006.168.08:13:28.37#ibcon#read 4, iclass 27, count 2 2006.168.08:13:28.37#ibcon#about to read 5, iclass 27, count 2 2006.168.08:13:28.37#ibcon#read 5, iclass 27, count 2 2006.168.08:13:28.37#ibcon#about to read 6, iclass 27, count 2 2006.168.08:13:28.37#ibcon#read 6, iclass 27, count 2 2006.168.08:13:28.37#ibcon#end of sib2, iclass 27, count 2 2006.168.08:13:28.37#ibcon#*mode == 0, iclass 27, count 2 2006.168.08:13:28.37#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.168.08:13:28.37#ibcon#[25=AT02-07\r\n] 2006.168.08:13:28.37#ibcon#*before write, iclass 27, count 2 2006.168.08:13:28.37#ibcon#enter sib2, iclass 27, count 2 2006.168.08:13:28.37#ibcon#flushed, iclass 27, count 2 2006.168.08:13:28.37#ibcon#about to write, iclass 27, count 2 2006.168.08:13:28.37#ibcon#wrote, iclass 27, count 2 2006.168.08:13:28.37#ibcon#about to read 3, iclass 27, count 2 2006.168.08:13:28.40#ibcon#read 3, iclass 27, count 2 2006.168.08:13:28.40#ibcon#about to read 4, iclass 27, count 2 2006.168.08:13:28.40#ibcon#read 4, iclass 27, count 2 2006.168.08:13:28.40#ibcon#about to read 5, iclass 27, count 2 2006.168.08:13:28.40#ibcon#read 5, iclass 27, count 2 2006.168.08:13:28.40#ibcon#about to read 6, iclass 27, count 2 2006.168.08:13:28.40#ibcon#read 6, iclass 27, count 2 2006.168.08:13:28.40#ibcon#end of sib2, iclass 27, count 2 2006.168.08:13:28.40#ibcon#*after write, iclass 27, count 2 2006.168.08:13:28.40#ibcon#*before return 0, iclass 27, count 2 2006.168.08:13:28.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.168.08:13:28.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.168.08:13:28.40#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.168.08:13:28.40#ibcon#ireg 7 cls_cnt 0 2006.168.08:13:28.40#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.168.08:13:28.52#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.168.08:13:28.52#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.168.08:13:28.52#ibcon#enter wrdev, iclass 27, count 0 2006.168.08:13:28.52#ibcon#first serial, iclass 27, count 0 2006.168.08:13:28.52#ibcon#enter sib2, iclass 27, count 0 2006.168.08:13:28.52#ibcon#flushed, iclass 27, count 0 2006.168.08:13:28.52#ibcon#about to write, iclass 27, count 0 2006.168.08:13:28.52#ibcon#wrote, iclass 27, count 0 2006.168.08:13:28.52#ibcon#about to read 3, iclass 27, count 0 2006.168.08:13:28.54#ibcon#read 3, iclass 27, count 0 2006.168.08:13:28.54#ibcon#about to read 4, iclass 27, count 0 2006.168.08:13:28.54#ibcon#read 4, iclass 27, count 0 2006.168.08:13:28.54#ibcon#about to read 5, iclass 27, count 0 2006.168.08:13:28.54#ibcon#read 5, iclass 27, count 0 2006.168.08:13:28.54#ibcon#about to read 6, iclass 27, count 0 2006.168.08:13:28.54#ibcon#read 6, iclass 27, count 0 2006.168.08:13:28.54#ibcon#end of sib2, iclass 27, count 0 2006.168.08:13:28.54#ibcon#*mode == 0, iclass 27, count 0 2006.168.08:13:28.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.168.08:13:28.54#ibcon#[25=USB\r\n] 2006.168.08:13:28.54#ibcon#*before write, iclass 27, count 0 2006.168.08:13:28.54#ibcon#enter sib2, iclass 27, count 0 2006.168.08:13:28.54#ibcon#flushed, iclass 27, count 0 2006.168.08:13:28.54#ibcon#about to write, iclass 27, count 0 2006.168.08:13:28.54#ibcon#wrote, iclass 27, count 0 2006.168.08:13:28.54#ibcon#about to read 3, iclass 27, count 0 2006.168.08:13:28.57#ibcon#read 3, iclass 27, count 0 2006.168.08:13:28.57#ibcon#about to read 4, iclass 27, count 0 2006.168.08:13:28.57#ibcon#read 4, iclass 27, count 0 2006.168.08:13:28.57#ibcon#about to read 5, iclass 27, count 0 2006.168.08:13:28.57#ibcon#read 5, iclass 27, count 0 2006.168.08:13:28.57#ibcon#about to read 6, iclass 27, count 0 2006.168.08:13:28.57#ibcon#read 6, iclass 27, count 0 2006.168.08:13:28.57#ibcon#end of sib2, iclass 27, count 0 2006.168.08:13:28.57#ibcon#*after write, iclass 27, count 0 2006.168.08:13:28.57#ibcon#*before return 0, iclass 27, count 0 2006.168.08:13:28.57#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.168.08:13:28.57#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.168.08:13:28.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.168.08:13:28.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.168.08:13:28.57$vc4f8/valo=3,672.99 2006.168.08:13:28.57#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.168.08:13:28.57#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.168.08:13:28.57#ibcon#ireg 17 cls_cnt 0 2006.168.08:13:28.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.168.08:13:28.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.168.08:13:28.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.168.08:13:28.57#ibcon#enter wrdev, iclass 29, count 0 2006.168.08:13:28.57#ibcon#first serial, iclass 29, count 0 2006.168.08:13:28.57#ibcon#enter sib2, iclass 29, count 0 2006.168.08:13:28.57#ibcon#flushed, iclass 29, count 0 2006.168.08:13:28.57#ibcon#about to write, iclass 29, count 0 2006.168.08:13:28.57#ibcon#wrote, iclass 29, count 0 2006.168.08:13:28.57#ibcon#about to read 3, iclass 29, count 0 2006.168.08:13:28.59#ibcon#read 3, iclass 29, count 0 2006.168.08:13:28.59#ibcon#about to read 4, iclass 29, count 0 2006.168.08:13:28.59#ibcon#read 4, iclass 29, count 0 2006.168.08:13:28.59#ibcon#about to read 5, iclass 29, count 0 2006.168.08:13:28.59#ibcon#read 5, iclass 29, count 0 2006.168.08:13:28.59#ibcon#about to read 6, iclass 29, count 0 2006.168.08:13:28.59#ibcon#read 6, iclass 29, count 0 2006.168.08:13:28.59#ibcon#end of sib2, iclass 29, count 0 2006.168.08:13:28.59#ibcon#*mode == 0, iclass 29, count 0 2006.168.08:13:28.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.168.08:13:28.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.08:13:28.59#ibcon#*before write, iclass 29, count 0 2006.168.08:13:28.59#ibcon#enter sib2, iclass 29, count 0 2006.168.08:13:28.59#ibcon#flushed, iclass 29, count 0 2006.168.08:13:28.59#ibcon#about to write, iclass 29, count 0 2006.168.08:13:28.59#ibcon#wrote, iclass 29, count 0 2006.168.08:13:28.59#ibcon#about to read 3, iclass 29, count 0 2006.168.08:13:28.63#ibcon#read 3, iclass 29, count 0 2006.168.08:13:28.63#ibcon#about to read 4, iclass 29, count 0 2006.168.08:13:28.63#ibcon#read 4, iclass 29, count 0 2006.168.08:13:28.63#ibcon#about to read 5, iclass 29, count 0 2006.168.08:13:28.63#ibcon#read 5, iclass 29, count 0 2006.168.08:13:28.63#ibcon#about to read 6, iclass 29, count 0 2006.168.08:13:28.63#ibcon#read 6, iclass 29, count 0 2006.168.08:13:28.63#ibcon#end of sib2, iclass 29, count 0 2006.168.08:13:28.63#ibcon#*after write, iclass 29, count 0 2006.168.08:13:28.63#ibcon#*before return 0, iclass 29, count 0 2006.168.08:13:28.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.168.08:13:28.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.168.08:13:28.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.168.08:13:28.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.168.08:13:28.63$vc4f8/va=3,6 2006.168.08:13:28.63#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.168.08:13:28.63#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.168.08:13:28.63#ibcon#ireg 11 cls_cnt 2 2006.168.08:13:28.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.168.08:13:28.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.168.08:13:28.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.168.08:13:28.69#ibcon#enter wrdev, iclass 31, count 2 2006.168.08:13:28.69#ibcon#first serial, iclass 31, count 2 2006.168.08:13:28.69#ibcon#enter sib2, iclass 31, count 2 2006.168.08:13:28.69#ibcon#flushed, iclass 31, count 2 2006.168.08:13:28.69#ibcon#about to write, iclass 31, count 2 2006.168.08:13:28.69#ibcon#wrote, iclass 31, count 2 2006.168.08:13:28.69#ibcon#about to read 3, iclass 31, count 2 2006.168.08:13:28.72#ibcon#read 3, iclass 31, count 2 2006.168.08:13:28.72#ibcon#about to read 4, iclass 31, count 2 2006.168.08:13:28.72#ibcon#read 4, iclass 31, count 2 2006.168.08:13:28.72#ibcon#about to read 5, iclass 31, count 2 2006.168.08:13:28.72#ibcon#read 5, iclass 31, count 2 2006.168.08:13:28.72#ibcon#about to read 6, iclass 31, count 2 2006.168.08:13:28.72#ibcon#read 6, iclass 31, count 2 2006.168.08:13:28.72#ibcon#end of sib2, iclass 31, count 2 2006.168.08:13:28.72#ibcon#*mode == 0, iclass 31, count 2 2006.168.08:13:28.72#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.168.08:13:28.72#ibcon#[25=AT03-06\r\n] 2006.168.08:13:28.72#ibcon#*before write, iclass 31, count 2 2006.168.08:13:28.72#ibcon#enter sib2, iclass 31, count 2 2006.168.08:13:28.72#ibcon#flushed, iclass 31, count 2 2006.168.08:13:28.72#ibcon#about to write, iclass 31, count 2 2006.168.08:13:28.72#ibcon#wrote, iclass 31, count 2 2006.168.08:13:28.72#ibcon#about to read 3, iclass 31, count 2 2006.168.08:13:28.75#ibcon#read 3, iclass 31, count 2 2006.168.08:13:28.75#ibcon#about to read 4, iclass 31, count 2 2006.168.08:13:28.75#ibcon#read 4, iclass 31, count 2 2006.168.08:13:28.75#ibcon#about to read 5, iclass 31, count 2 2006.168.08:13:28.75#ibcon#read 5, iclass 31, count 2 2006.168.08:13:28.75#ibcon#about to read 6, iclass 31, count 2 2006.168.08:13:28.75#ibcon#read 6, iclass 31, count 2 2006.168.08:13:28.75#ibcon#end of sib2, iclass 31, count 2 2006.168.08:13:28.75#ibcon#*after write, iclass 31, count 2 2006.168.08:13:28.75#ibcon#*before return 0, iclass 31, count 2 2006.168.08:13:28.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.168.08:13:28.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.168.08:13:28.75#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.168.08:13:28.75#ibcon#ireg 7 cls_cnt 0 2006.168.08:13:28.75#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.168.08:13:28.87#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.168.08:13:28.87#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.168.08:13:28.87#ibcon#enter wrdev, iclass 31, count 0 2006.168.08:13:28.87#ibcon#first serial, iclass 31, count 0 2006.168.08:13:28.87#ibcon#enter sib2, iclass 31, count 0 2006.168.08:13:28.87#ibcon#flushed, iclass 31, count 0 2006.168.08:13:28.87#ibcon#about to write, iclass 31, count 0 2006.168.08:13:28.87#ibcon#wrote, iclass 31, count 0 2006.168.08:13:28.87#ibcon#about to read 3, iclass 31, count 0 2006.168.08:13:28.89#ibcon#read 3, iclass 31, count 0 2006.168.08:13:28.89#ibcon#about to read 4, iclass 31, count 0 2006.168.08:13:28.89#ibcon#read 4, iclass 31, count 0 2006.168.08:13:28.89#ibcon#about to read 5, iclass 31, count 0 2006.168.08:13:28.89#ibcon#read 5, iclass 31, count 0 2006.168.08:13:28.89#ibcon#about to read 6, iclass 31, count 0 2006.168.08:13:28.89#ibcon#read 6, iclass 31, count 0 2006.168.08:13:28.89#ibcon#end of sib2, iclass 31, count 0 2006.168.08:13:28.89#ibcon#*mode == 0, iclass 31, count 0 2006.168.08:13:28.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.168.08:13:28.89#ibcon#[25=USB\r\n] 2006.168.08:13:28.89#ibcon#*before write, iclass 31, count 0 2006.168.08:13:28.89#ibcon#enter sib2, iclass 31, count 0 2006.168.08:13:28.89#ibcon#flushed, iclass 31, count 0 2006.168.08:13:28.89#ibcon#about to write, iclass 31, count 0 2006.168.08:13:28.89#ibcon#wrote, iclass 31, count 0 2006.168.08:13:28.89#ibcon#about to read 3, iclass 31, count 0 2006.168.08:13:28.92#ibcon#read 3, iclass 31, count 0 2006.168.08:13:28.92#ibcon#about to read 4, iclass 31, count 0 2006.168.08:13:28.92#ibcon#read 4, iclass 31, count 0 2006.168.08:13:28.92#ibcon#about to read 5, iclass 31, count 0 2006.168.08:13:28.92#ibcon#read 5, iclass 31, count 0 2006.168.08:13:28.92#ibcon#about to read 6, iclass 31, count 0 2006.168.08:13:28.92#ibcon#read 6, iclass 31, count 0 2006.168.08:13:28.92#ibcon#end of sib2, iclass 31, count 0 2006.168.08:13:28.92#ibcon#*after write, iclass 31, count 0 2006.168.08:13:28.92#ibcon#*before return 0, iclass 31, count 0 2006.168.08:13:28.92#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.168.08:13:28.92#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.168.08:13:28.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.168.08:13:28.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.168.08:13:28.92$vc4f8/valo=4,832.99 2006.168.08:13:28.92#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.168.08:13:28.92#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.168.08:13:28.92#ibcon#ireg 17 cls_cnt 0 2006.168.08:13:28.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:13:28.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:13:28.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:13:28.92#ibcon#enter wrdev, iclass 33, count 0 2006.168.08:13:28.92#ibcon#first serial, iclass 33, count 0 2006.168.08:13:28.92#ibcon#enter sib2, iclass 33, count 0 2006.168.08:13:28.92#ibcon#flushed, iclass 33, count 0 2006.168.08:13:28.92#ibcon#about to write, iclass 33, count 0 2006.168.08:13:28.92#ibcon#wrote, iclass 33, count 0 2006.168.08:13:28.92#ibcon#about to read 3, iclass 33, count 0 2006.168.08:13:28.94#ibcon#read 3, iclass 33, count 0 2006.168.08:13:28.94#ibcon#about to read 4, iclass 33, count 0 2006.168.08:13:28.94#ibcon#read 4, iclass 33, count 0 2006.168.08:13:28.94#ibcon#about to read 5, iclass 33, count 0 2006.168.08:13:28.94#ibcon#read 5, iclass 33, count 0 2006.168.08:13:28.94#ibcon#about to read 6, iclass 33, count 0 2006.168.08:13:28.94#ibcon#read 6, iclass 33, count 0 2006.168.08:13:28.94#ibcon#end of sib2, iclass 33, count 0 2006.168.08:13:28.94#ibcon#*mode == 0, iclass 33, count 0 2006.168.08:13:28.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.168.08:13:28.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.08:13:28.94#ibcon#*before write, iclass 33, count 0 2006.168.08:13:28.94#ibcon#enter sib2, iclass 33, count 0 2006.168.08:13:28.94#ibcon#flushed, iclass 33, count 0 2006.168.08:13:28.94#ibcon#about to write, iclass 33, count 0 2006.168.08:13:28.94#ibcon#wrote, iclass 33, count 0 2006.168.08:13:28.94#ibcon#about to read 3, iclass 33, count 0 2006.168.08:13:28.98#ibcon#read 3, iclass 33, count 0 2006.168.08:13:28.98#ibcon#about to read 4, iclass 33, count 0 2006.168.08:13:28.98#ibcon#read 4, iclass 33, count 0 2006.168.08:13:28.98#ibcon#about to read 5, iclass 33, count 0 2006.168.08:13:28.98#ibcon#read 5, iclass 33, count 0 2006.168.08:13:28.98#ibcon#about to read 6, iclass 33, count 0 2006.168.08:13:28.98#ibcon#read 6, iclass 33, count 0 2006.168.08:13:28.98#ibcon#end of sib2, iclass 33, count 0 2006.168.08:13:28.98#ibcon#*after write, iclass 33, count 0 2006.168.08:13:28.98#ibcon#*before return 0, iclass 33, count 0 2006.168.08:13:28.98#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:13:28.98#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:13:28.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.168.08:13:28.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.168.08:13:28.98$vc4f8/va=4,7 2006.168.08:13:28.98#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.168.08:13:28.98#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.168.08:13:28.98#ibcon#ireg 11 cls_cnt 2 2006.168.08:13:28.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.168.08:13:29.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.168.08:13:29.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.168.08:13:29.04#ibcon#enter wrdev, iclass 35, count 2 2006.168.08:13:29.04#ibcon#first serial, iclass 35, count 2 2006.168.08:13:29.04#ibcon#enter sib2, iclass 35, count 2 2006.168.08:13:29.04#ibcon#flushed, iclass 35, count 2 2006.168.08:13:29.04#ibcon#about to write, iclass 35, count 2 2006.168.08:13:29.04#ibcon#wrote, iclass 35, count 2 2006.168.08:13:29.04#ibcon#about to read 3, iclass 35, count 2 2006.168.08:13:29.06#ibcon#read 3, iclass 35, count 2 2006.168.08:13:29.06#ibcon#about to read 4, iclass 35, count 2 2006.168.08:13:29.06#ibcon#read 4, iclass 35, count 2 2006.168.08:13:29.06#ibcon#about to read 5, iclass 35, count 2 2006.168.08:13:29.06#ibcon#read 5, iclass 35, count 2 2006.168.08:13:29.06#ibcon#about to read 6, iclass 35, count 2 2006.168.08:13:29.06#ibcon#read 6, iclass 35, count 2 2006.168.08:13:29.06#ibcon#end of sib2, iclass 35, count 2 2006.168.08:13:29.06#ibcon#*mode == 0, iclass 35, count 2 2006.168.08:13:29.06#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.168.08:13:29.06#ibcon#[25=AT04-07\r\n] 2006.168.08:13:29.06#ibcon#*before write, iclass 35, count 2 2006.168.08:13:29.06#ibcon#enter sib2, iclass 35, count 2 2006.168.08:13:29.06#ibcon#flushed, iclass 35, count 2 2006.168.08:13:29.06#ibcon#about to write, iclass 35, count 2 2006.168.08:13:29.06#ibcon#wrote, iclass 35, count 2 2006.168.08:13:29.06#ibcon#about to read 3, iclass 35, count 2 2006.168.08:13:29.09#ibcon#read 3, iclass 35, count 2 2006.168.08:13:29.09#ibcon#about to read 4, iclass 35, count 2 2006.168.08:13:29.09#ibcon#read 4, iclass 35, count 2 2006.168.08:13:29.09#ibcon#about to read 5, iclass 35, count 2 2006.168.08:13:29.09#ibcon#read 5, iclass 35, count 2 2006.168.08:13:29.09#ibcon#about to read 6, iclass 35, count 2 2006.168.08:13:29.09#ibcon#read 6, iclass 35, count 2 2006.168.08:13:29.09#ibcon#end of sib2, iclass 35, count 2 2006.168.08:13:29.09#ibcon#*after write, iclass 35, count 2 2006.168.08:13:29.09#ibcon#*before return 0, iclass 35, count 2 2006.168.08:13:29.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.168.08:13:29.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.168.08:13:29.09#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.168.08:13:29.09#ibcon#ireg 7 cls_cnt 0 2006.168.08:13:29.09#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.168.08:13:29.21#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.168.08:13:29.21#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.168.08:13:29.21#ibcon#enter wrdev, iclass 35, count 0 2006.168.08:13:29.21#ibcon#first serial, iclass 35, count 0 2006.168.08:13:29.21#ibcon#enter sib2, iclass 35, count 0 2006.168.08:13:29.21#ibcon#flushed, iclass 35, count 0 2006.168.08:13:29.21#ibcon#about to write, iclass 35, count 0 2006.168.08:13:29.21#ibcon#wrote, iclass 35, count 0 2006.168.08:13:29.21#ibcon#about to read 3, iclass 35, count 0 2006.168.08:13:29.23#ibcon#read 3, iclass 35, count 0 2006.168.08:13:29.23#ibcon#about to read 4, iclass 35, count 0 2006.168.08:13:29.23#ibcon#read 4, iclass 35, count 0 2006.168.08:13:29.23#ibcon#about to read 5, iclass 35, count 0 2006.168.08:13:29.23#ibcon#read 5, iclass 35, count 0 2006.168.08:13:29.23#ibcon#about to read 6, iclass 35, count 0 2006.168.08:13:29.23#ibcon#read 6, iclass 35, count 0 2006.168.08:13:29.23#ibcon#end of sib2, iclass 35, count 0 2006.168.08:13:29.23#ibcon#*mode == 0, iclass 35, count 0 2006.168.08:13:29.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.168.08:13:29.23#ibcon#[25=USB\r\n] 2006.168.08:13:29.23#ibcon#*before write, iclass 35, count 0 2006.168.08:13:29.23#ibcon#enter sib2, iclass 35, count 0 2006.168.08:13:29.23#ibcon#flushed, iclass 35, count 0 2006.168.08:13:29.23#ibcon#about to write, iclass 35, count 0 2006.168.08:13:29.23#ibcon#wrote, iclass 35, count 0 2006.168.08:13:29.23#ibcon#about to read 3, iclass 35, count 0 2006.168.08:13:29.26#ibcon#read 3, iclass 35, count 0 2006.168.08:13:29.26#ibcon#about to read 4, iclass 35, count 0 2006.168.08:13:29.26#ibcon#read 4, iclass 35, count 0 2006.168.08:13:29.26#ibcon#about to read 5, iclass 35, count 0 2006.168.08:13:29.26#ibcon#read 5, iclass 35, count 0 2006.168.08:13:29.26#ibcon#about to read 6, iclass 35, count 0 2006.168.08:13:29.26#ibcon#read 6, iclass 35, count 0 2006.168.08:13:29.26#ibcon#end of sib2, iclass 35, count 0 2006.168.08:13:29.26#ibcon#*after write, iclass 35, count 0 2006.168.08:13:29.26#ibcon#*before return 0, iclass 35, count 0 2006.168.08:13:29.26#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.168.08:13:29.26#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.168.08:13:29.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.168.08:13:29.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.168.08:13:29.26$vc4f8/valo=5,652.99 2006.168.08:13:29.26#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.168.08:13:29.26#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.168.08:13:29.26#ibcon#ireg 17 cls_cnt 0 2006.168.08:13:29.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:13:29.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:13:29.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:13:29.26#ibcon#enter wrdev, iclass 37, count 0 2006.168.08:13:29.26#ibcon#first serial, iclass 37, count 0 2006.168.08:13:29.26#ibcon#enter sib2, iclass 37, count 0 2006.168.08:13:29.26#ibcon#flushed, iclass 37, count 0 2006.168.08:13:29.26#ibcon#about to write, iclass 37, count 0 2006.168.08:13:29.26#ibcon#wrote, iclass 37, count 0 2006.168.08:13:29.26#ibcon#about to read 3, iclass 37, count 0 2006.168.08:13:29.28#ibcon#read 3, iclass 37, count 0 2006.168.08:13:29.28#ibcon#about to read 4, iclass 37, count 0 2006.168.08:13:29.28#ibcon#read 4, iclass 37, count 0 2006.168.08:13:29.28#ibcon#about to read 5, iclass 37, count 0 2006.168.08:13:29.28#ibcon#read 5, iclass 37, count 0 2006.168.08:13:29.28#ibcon#about to read 6, iclass 37, count 0 2006.168.08:13:29.28#ibcon#read 6, iclass 37, count 0 2006.168.08:13:29.28#ibcon#end of sib2, iclass 37, count 0 2006.168.08:13:29.28#ibcon#*mode == 0, iclass 37, count 0 2006.168.08:13:29.28#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.168.08:13:29.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.08:13:29.28#ibcon#*before write, iclass 37, count 0 2006.168.08:13:29.28#ibcon#enter sib2, iclass 37, count 0 2006.168.08:13:29.28#ibcon#flushed, iclass 37, count 0 2006.168.08:13:29.28#ibcon#about to write, iclass 37, count 0 2006.168.08:13:29.28#ibcon#wrote, iclass 37, count 0 2006.168.08:13:29.28#ibcon#about to read 3, iclass 37, count 0 2006.168.08:13:29.32#ibcon#read 3, iclass 37, count 0 2006.168.08:13:29.32#ibcon#about to read 4, iclass 37, count 0 2006.168.08:13:29.32#ibcon#read 4, iclass 37, count 0 2006.168.08:13:29.32#ibcon#about to read 5, iclass 37, count 0 2006.168.08:13:29.32#ibcon#read 5, iclass 37, count 0 2006.168.08:13:29.32#ibcon#about to read 6, iclass 37, count 0 2006.168.08:13:29.32#ibcon#read 6, iclass 37, count 0 2006.168.08:13:29.32#ibcon#end of sib2, iclass 37, count 0 2006.168.08:13:29.32#ibcon#*after write, iclass 37, count 0 2006.168.08:13:29.32#ibcon#*before return 0, iclass 37, count 0 2006.168.08:13:29.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:13:29.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:13:29.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.168.08:13:29.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.168.08:13:29.32$vc4f8/va=5,7 2006.168.08:13:29.32#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.168.08:13:29.32#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.168.08:13:29.32#ibcon#ireg 11 cls_cnt 2 2006.168.08:13:29.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.168.08:13:29.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.168.08:13:29.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.168.08:13:29.38#ibcon#enter wrdev, iclass 39, count 2 2006.168.08:13:29.38#ibcon#first serial, iclass 39, count 2 2006.168.08:13:29.38#ibcon#enter sib2, iclass 39, count 2 2006.168.08:13:29.38#ibcon#flushed, iclass 39, count 2 2006.168.08:13:29.38#ibcon#about to write, iclass 39, count 2 2006.168.08:13:29.38#ibcon#wrote, iclass 39, count 2 2006.168.08:13:29.38#ibcon#about to read 3, iclass 39, count 2 2006.168.08:13:29.40#ibcon#read 3, iclass 39, count 2 2006.168.08:13:29.40#ibcon#about to read 4, iclass 39, count 2 2006.168.08:13:29.40#ibcon#read 4, iclass 39, count 2 2006.168.08:13:29.40#ibcon#about to read 5, iclass 39, count 2 2006.168.08:13:29.40#ibcon#read 5, iclass 39, count 2 2006.168.08:13:29.40#ibcon#about to read 6, iclass 39, count 2 2006.168.08:13:29.40#ibcon#read 6, iclass 39, count 2 2006.168.08:13:29.40#ibcon#end of sib2, iclass 39, count 2 2006.168.08:13:29.40#ibcon#*mode == 0, iclass 39, count 2 2006.168.08:13:29.40#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.168.08:13:29.40#ibcon#[25=AT05-07\r\n] 2006.168.08:13:29.40#ibcon#*before write, iclass 39, count 2 2006.168.08:13:29.40#ibcon#enter sib2, iclass 39, count 2 2006.168.08:13:29.40#ibcon#flushed, iclass 39, count 2 2006.168.08:13:29.40#ibcon#about to write, iclass 39, count 2 2006.168.08:13:29.40#ibcon#wrote, iclass 39, count 2 2006.168.08:13:29.40#ibcon#about to read 3, iclass 39, count 2 2006.168.08:13:29.43#ibcon#read 3, iclass 39, count 2 2006.168.08:13:29.43#ibcon#about to read 4, iclass 39, count 2 2006.168.08:13:29.43#ibcon#read 4, iclass 39, count 2 2006.168.08:13:29.43#ibcon#about to read 5, iclass 39, count 2 2006.168.08:13:29.43#ibcon#read 5, iclass 39, count 2 2006.168.08:13:29.43#ibcon#about to read 6, iclass 39, count 2 2006.168.08:13:29.43#ibcon#read 6, iclass 39, count 2 2006.168.08:13:29.43#ibcon#end of sib2, iclass 39, count 2 2006.168.08:13:29.43#ibcon#*after write, iclass 39, count 2 2006.168.08:13:29.43#ibcon#*before return 0, iclass 39, count 2 2006.168.08:13:29.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.168.08:13:29.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.168.08:13:29.43#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.168.08:13:29.43#ibcon#ireg 7 cls_cnt 0 2006.168.08:13:29.43#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.168.08:13:29.55#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.168.08:13:29.55#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.168.08:13:29.55#ibcon#enter wrdev, iclass 39, count 0 2006.168.08:13:29.55#ibcon#first serial, iclass 39, count 0 2006.168.08:13:29.55#ibcon#enter sib2, iclass 39, count 0 2006.168.08:13:29.55#ibcon#flushed, iclass 39, count 0 2006.168.08:13:29.55#ibcon#about to write, iclass 39, count 0 2006.168.08:13:29.55#ibcon#wrote, iclass 39, count 0 2006.168.08:13:29.55#ibcon#about to read 3, iclass 39, count 0 2006.168.08:13:29.57#ibcon#read 3, iclass 39, count 0 2006.168.08:13:29.57#ibcon#about to read 4, iclass 39, count 0 2006.168.08:13:29.57#ibcon#read 4, iclass 39, count 0 2006.168.08:13:29.57#ibcon#about to read 5, iclass 39, count 0 2006.168.08:13:29.57#ibcon#read 5, iclass 39, count 0 2006.168.08:13:29.57#ibcon#about to read 6, iclass 39, count 0 2006.168.08:13:29.57#ibcon#read 6, iclass 39, count 0 2006.168.08:13:29.57#ibcon#end of sib2, iclass 39, count 0 2006.168.08:13:29.57#ibcon#*mode == 0, iclass 39, count 0 2006.168.08:13:29.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.168.08:13:29.57#ibcon#[25=USB\r\n] 2006.168.08:13:29.57#ibcon#*before write, iclass 39, count 0 2006.168.08:13:29.57#ibcon#enter sib2, iclass 39, count 0 2006.168.08:13:29.57#ibcon#flushed, iclass 39, count 0 2006.168.08:13:29.57#ibcon#about to write, iclass 39, count 0 2006.168.08:13:29.57#ibcon#wrote, iclass 39, count 0 2006.168.08:13:29.57#ibcon#about to read 3, iclass 39, count 0 2006.168.08:13:29.60#ibcon#read 3, iclass 39, count 0 2006.168.08:13:29.60#ibcon#about to read 4, iclass 39, count 0 2006.168.08:13:29.60#ibcon#read 4, iclass 39, count 0 2006.168.08:13:29.60#ibcon#about to read 5, iclass 39, count 0 2006.168.08:13:29.60#ibcon#read 5, iclass 39, count 0 2006.168.08:13:29.60#ibcon#about to read 6, iclass 39, count 0 2006.168.08:13:29.60#ibcon#read 6, iclass 39, count 0 2006.168.08:13:29.60#ibcon#end of sib2, iclass 39, count 0 2006.168.08:13:29.60#ibcon#*after write, iclass 39, count 0 2006.168.08:13:29.60#ibcon#*before return 0, iclass 39, count 0 2006.168.08:13:29.60#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.168.08:13:29.60#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.168.08:13:29.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.168.08:13:29.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.168.08:13:29.60$vc4f8/valo=6,772.99 2006.168.08:13:29.60#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.168.08:13:29.60#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.168.08:13:29.60#ibcon#ireg 17 cls_cnt 0 2006.168.08:13:29.60#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.168.08:13:29.60#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.168.08:13:29.60#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.168.08:13:29.60#ibcon#enter wrdev, iclass 3, count 0 2006.168.08:13:29.60#ibcon#first serial, iclass 3, count 0 2006.168.08:13:29.60#ibcon#enter sib2, iclass 3, count 0 2006.168.08:13:29.60#ibcon#flushed, iclass 3, count 0 2006.168.08:13:29.60#ibcon#about to write, iclass 3, count 0 2006.168.08:13:29.60#ibcon#wrote, iclass 3, count 0 2006.168.08:13:29.60#ibcon#about to read 3, iclass 3, count 0 2006.168.08:13:29.62#ibcon#read 3, iclass 3, count 0 2006.168.08:13:29.62#ibcon#about to read 4, iclass 3, count 0 2006.168.08:13:29.62#ibcon#read 4, iclass 3, count 0 2006.168.08:13:29.62#ibcon#about to read 5, iclass 3, count 0 2006.168.08:13:29.62#ibcon#read 5, iclass 3, count 0 2006.168.08:13:29.62#ibcon#about to read 6, iclass 3, count 0 2006.168.08:13:29.62#ibcon#read 6, iclass 3, count 0 2006.168.08:13:29.62#ibcon#end of sib2, iclass 3, count 0 2006.168.08:13:29.62#ibcon#*mode == 0, iclass 3, count 0 2006.168.08:13:29.62#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.168.08:13:29.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.08:13:29.62#ibcon#*before write, iclass 3, count 0 2006.168.08:13:29.62#ibcon#enter sib2, iclass 3, count 0 2006.168.08:13:29.62#ibcon#flushed, iclass 3, count 0 2006.168.08:13:29.62#ibcon#about to write, iclass 3, count 0 2006.168.08:13:29.62#ibcon#wrote, iclass 3, count 0 2006.168.08:13:29.62#ibcon#about to read 3, iclass 3, count 0 2006.168.08:13:29.66#ibcon#read 3, iclass 3, count 0 2006.168.08:13:29.66#ibcon#about to read 4, iclass 3, count 0 2006.168.08:13:29.66#ibcon#read 4, iclass 3, count 0 2006.168.08:13:29.66#ibcon#about to read 5, iclass 3, count 0 2006.168.08:13:29.66#ibcon#read 5, iclass 3, count 0 2006.168.08:13:29.66#ibcon#about to read 6, iclass 3, count 0 2006.168.08:13:29.66#ibcon#read 6, iclass 3, count 0 2006.168.08:13:29.66#ibcon#end of sib2, iclass 3, count 0 2006.168.08:13:29.66#ibcon#*after write, iclass 3, count 0 2006.168.08:13:29.66#ibcon#*before return 0, iclass 3, count 0 2006.168.08:13:29.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.168.08:13:29.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.168.08:13:29.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.168.08:13:29.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.168.08:13:29.66$vc4f8/va=6,6 2006.168.08:13:29.66#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.168.08:13:29.66#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.168.08:13:29.66#ibcon#ireg 11 cls_cnt 2 2006.168.08:13:29.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.168.08:13:29.72#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.168.08:13:29.72#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.168.08:13:29.72#ibcon#enter wrdev, iclass 5, count 2 2006.168.08:13:29.72#ibcon#first serial, iclass 5, count 2 2006.168.08:13:29.72#ibcon#enter sib2, iclass 5, count 2 2006.168.08:13:29.72#ibcon#flushed, iclass 5, count 2 2006.168.08:13:29.72#ibcon#about to write, iclass 5, count 2 2006.168.08:13:29.72#ibcon#wrote, iclass 5, count 2 2006.168.08:13:29.72#ibcon#about to read 3, iclass 5, count 2 2006.168.08:13:29.74#ibcon#read 3, iclass 5, count 2 2006.168.08:13:29.74#ibcon#about to read 4, iclass 5, count 2 2006.168.08:13:29.74#ibcon#read 4, iclass 5, count 2 2006.168.08:13:29.74#ibcon#about to read 5, iclass 5, count 2 2006.168.08:13:29.74#ibcon#read 5, iclass 5, count 2 2006.168.08:13:29.74#ibcon#about to read 6, iclass 5, count 2 2006.168.08:13:29.74#ibcon#read 6, iclass 5, count 2 2006.168.08:13:29.74#ibcon#end of sib2, iclass 5, count 2 2006.168.08:13:29.74#ibcon#*mode == 0, iclass 5, count 2 2006.168.08:13:29.74#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.168.08:13:29.74#ibcon#[25=AT06-06\r\n] 2006.168.08:13:29.74#ibcon#*before write, iclass 5, count 2 2006.168.08:13:29.74#ibcon#enter sib2, iclass 5, count 2 2006.168.08:13:29.74#ibcon#flushed, iclass 5, count 2 2006.168.08:13:29.74#ibcon#about to write, iclass 5, count 2 2006.168.08:13:29.74#ibcon#wrote, iclass 5, count 2 2006.168.08:13:29.74#ibcon#about to read 3, iclass 5, count 2 2006.168.08:13:29.77#ibcon#read 3, iclass 5, count 2 2006.168.08:13:29.77#ibcon#about to read 4, iclass 5, count 2 2006.168.08:13:29.77#ibcon#read 4, iclass 5, count 2 2006.168.08:13:29.77#ibcon#about to read 5, iclass 5, count 2 2006.168.08:13:29.77#ibcon#read 5, iclass 5, count 2 2006.168.08:13:29.77#ibcon#about to read 6, iclass 5, count 2 2006.168.08:13:29.77#ibcon#read 6, iclass 5, count 2 2006.168.08:13:29.77#ibcon#end of sib2, iclass 5, count 2 2006.168.08:13:29.77#ibcon#*after write, iclass 5, count 2 2006.168.08:13:29.77#ibcon#*before return 0, iclass 5, count 2 2006.168.08:13:29.77#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.168.08:13:29.77#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.168.08:13:29.77#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.168.08:13:29.77#ibcon#ireg 7 cls_cnt 0 2006.168.08:13:29.77#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.168.08:13:29.89#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.168.08:13:29.89#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.168.08:13:29.89#ibcon#enter wrdev, iclass 5, count 0 2006.168.08:13:29.89#ibcon#first serial, iclass 5, count 0 2006.168.08:13:29.89#ibcon#enter sib2, iclass 5, count 0 2006.168.08:13:29.89#ibcon#flushed, iclass 5, count 0 2006.168.08:13:29.89#ibcon#about to write, iclass 5, count 0 2006.168.08:13:29.89#ibcon#wrote, iclass 5, count 0 2006.168.08:13:29.89#ibcon#about to read 3, iclass 5, count 0 2006.168.08:13:29.91#ibcon#read 3, iclass 5, count 0 2006.168.08:13:29.91#ibcon#about to read 4, iclass 5, count 0 2006.168.08:13:29.91#ibcon#read 4, iclass 5, count 0 2006.168.08:13:29.91#ibcon#about to read 5, iclass 5, count 0 2006.168.08:13:29.91#ibcon#read 5, iclass 5, count 0 2006.168.08:13:29.91#ibcon#about to read 6, iclass 5, count 0 2006.168.08:13:29.91#ibcon#read 6, iclass 5, count 0 2006.168.08:13:29.91#ibcon#end of sib2, iclass 5, count 0 2006.168.08:13:29.91#ibcon#*mode == 0, iclass 5, count 0 2006.168.08:13:29.91#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.168.08:13:29.91#ibcon#[25=USB\r\n] 2006.168.08:13:29.91#ibcon#*before write, iclass 5, count 0 2006.168.08:13:29.91#ibcon#enter sib2, iclass 5, count 0 2006.168.08:13:29.91#ibcon#flushed, iclass 5, count 0 2006.168.08:13:29.91#ibcon#about to write, iclass 5, count 0 2006.168.08:13:29.91#ibcon#wrote, iclass 5, count 0 2006.168.08:13:29.91#ibcon#about to read 3, iclass 5, count 0 2006.168.08:13:29.94#ibcon#read 3, iclass 5, count 0 2006.168.08:13:29.94#ibcon#about to read 4, iclass 5, count 0 2006.168.08:13:29.94#ibcon#read 4, iclass 5, count 0 2006.168.08:13:29.94#ibcon#about to read 5, iclass 5, count 0 2006.168.08:13:29.94#ibcon#read 5, iclass 5, count 0 2006.168.08:13:29.94#ibcon#about to read 6, iclass 5, count 0 2006.168.08:13:29.94#ibcon#read 6, iclass 5, count 0 2006.168.08:13:29.94#ibcon#end of sib2, iclass 5, count 0 2006.168.08:13:29.94#ibcon#*after write, iclass 5, count 0 2006.168.08:13:29.94#ibcon#*before return 0, iclass 5, count 0 2006.168.08:13:29.94#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.168.08:13:29.94#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.168.08:13:29.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.168.08:13:29.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.168.08:13:29.94$vc4f8/valo=7,832.99 2006.168.08:13:29.94#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.168.08:13:29.94#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.168.08:13:29.94#ibcon#ireg 17 cls_cnt 0 2006.168.08:13:29.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.168.08:13:29.94#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.168.08:13:29.94#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.168.08:13:29.94#ibcon#enter wrdev, iclass 7, count 0 2006.168.08:13:29.94#ibcon#first serial, iclass 7, count 0 2006.168.08:13:29.94#ibcon#enter sib2, iclass 7, count 0 2006.168.08:13:29.94#ibcon#flushed, iclass 7, count 0 2006.168.08:13:29.94#ibcon#about to write, iclass 7, count 0 2006.168.08:13:29.94#ibcon#wrote, iclass 7, count 0 2006.168.08:13:29.94#ibcon#about to read 3, iclass 7, count 0 2006.168.08:13:29.96#ibcon#read 3, iclass 7, count 0 2006.168.08:13:29.96#ibcon#about to read 4, iclass 7, count 0 2006.168.08:13:29.96#ibcon#read 4, iclass 7, count 0 2006.168.08:13:29.96#ibcon#about to read 5, iclass 7, count 0 2006.168.08:13:29.96#ibcon#read 5, iclass 7, count 0 2006.168.08:13:29.96#ibcon#about to read 6, iclass 7, count 0 2006.168.08:13:29.96#ibcon#read 6, iclass 7, count 0 2006.168.08:13:29.96#ibcon#end of sib2, iclass 7, count 0 2006.168.08:13:29.96#ibcon#*mode == 0, iclass 7, count 0 2006.168.08:13:29.96#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.168.08:13:29.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.08:13:29.96#ibcon#*before write, iclass 7, count 0 2006.168.08:13:29.96#ibcon#enter sib2, iclass 7, count 0 2006.168.08:13:29.96#ibcon#flushed, iclass 7, count 0 2006.168.08:13:29.96#ibcon#about to write, iclass 7, count 0 2006.168.08:13:29.96#ibcon#wrote, iclass 7, count 0 2006.168.08:13:29.96#ibcon#about to read 3, iclass 7, count 0 2006.168.08:13:30.00#ibcon#read 3, iclass 7, count 0 2006.168.08:13:30.00#ibcon#about to read 4, iclass 7, count 0 2006.168.08:13:30.00#ibcon#read 4, iclass 7, count 0 2006.168.08:13:30.00#ibcon#about to read 5, iclass 7, count 0 2006.168.08:13:30.00#ibcon#read 5, iclass 7, count 0 2006.168.08:13:30.00#ibcon#about to read 6, iclass 7, count 0 2006.168.08:13:30.00#ibcon#read 6, iclass 7, count 0 2006.168.08:13:30.00#ibcon#end of sib2, iclass 7, count 0 2006.168.08:13:30.00#ibcon#*after write, iclass 7, count 0 2006.168.08:13:30.00#ibcon#*before return 0, iclass 7, count 0 2006.168.08:13:30.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.168.08:13:30.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.168.08:13:30.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.168.08:13:30.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.168.08:13:30.00$vc4f8/va=7,6 2006.168.08:13:30.00#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.168.08:13:30.00#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.168.08:13:30.00#ibcon#ireg 11 cls_cnt 2 2006.168.08:13:30.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.168.08:13:30.06#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.168.08:13:30.06#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.168.08:13:30.06#ibcon#enter wrdev, iclass 11, count 2 2006.168.08:13:30.06#ibcon#first serial, iclass 11, count 2 2006.168.08:13:30.06#ibcon#enter sib2, iclass 11, count 2 2006.168.08:13:30.06#ibcon#flushed, iclass 11, count 2 2006.168.08:13:30.06#ibcon#about to write, iclass 11, count 2 2006.168.08:13:30.06#ibcon#wrote, iclass 11, count 2 2006.168.08:13:30.06#ibcon#about to read 3, iclass 11, count 2 2006.168.08:13:30.08#ibcon#read 3, iclass 11, count 2 2006.168.08:13:30.08#ibcon#about to read 4, iclass 11, count 2 2006.168.08:13:30.08#ibcon#read 4, iclass 11, count 2 2006.168.08:13:30.08#ibcon#about to read 5, iclass 11, count 2 2006.168.08:13:30.08#ibcon#read 5, iclass 11, count 2 2006.168.08:13:30.08#ibcon#about to read 6, iclass 11, count 2 2006.168.08:13:30.08#ibcon#read 6, iclass 11, count 2 2006.168.08:13:30.08#ibcon#end of sib2, iclass 11, count 2 2006.168.08:13:30.08#ibcon#*mode == 0, iclass 11, count 2 2006.168.08:13:30.08#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.168.08:13:30.08#ibcon#[25=AT07-06\r\n] 2006.168.08:13:30.08#ibcon#*before write, iclass 11, count 2 2006.168.08:13:30.08#ibcon#enter sib2, iclass 11, count 2 2006.168.08:13:30.08#ibcon#flushed, iclass 11, count 2 2006.168.08:13:30.08#ibcon#about to write, iclass 11, count 2 2006.168.08:13:30.08#ibcon#wrote, iclass 11, count 2 2006.168.08:13:30.08#ibcon#about to read 3, iclass 11, count 2 2006.168.08:13:30.11#ibcon#read 3, iclass 11, count 2 2006.168.08:13:30.11#ibcon#about to read 4, iclass 11, count 2 2006.168.08:13:30.11#ibcon#read 4, iclass 11, count 2 2006.168.08:13:30.11#ibcon#about to read 5, iclass 11, count 2 2006.168.08:13:30.11#ibcon#read 5, iclass 11, count 2 2006.168.08:13:30.11#ibcon#about to read 6, iclass 11, count 2 2006.168.08:13:30.11#ibcon#read 6, iclass 11, count 2 2006.168.08:13:30.11#ibcon#end of sib2, iclass 11, count 2 2006.168.08:13:30.11#ibcon#*after write, iclass 11, count 2 2006.168.08:13:30.11#ibcon#*before return 0, iclass 11, count 2 2006.168.08:13:30.11#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.168.08:13:30.11#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.168.08:13:30.11#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.168.08:13:30.11#ibcon#ireg 7 cls_cnt 0 2006.168.08:13:30.11#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.168.08:13:30.23#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.168.08:13:30.23#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.168.08:13:30.23#ibcon#enter wrdev, iclass 11, count 0 2006.168.08:13:30.23#ibcon#first serial, iclass 11, count 0 2006.168.08:13:30.23#ibcon#enter sib2, iclass 11, count 0 2006.168.08:13:30.23#ibcon#flushed, iclass 11, count 0 2006.168.08:13:30.23#ibcon#about to write, iclass 11, count 0 2006.168.08:13:30.23#ibcon#wrote, iclass 11, count 0 2006.168.08:13:30.23#ibcon#about to read 3, iclass 11, count 0 2006.168.08:13:30.25#ibcon#read 3, iclass 11, count 0 2006.168.08:13:30.25#ibcon#about to read 4, iclass 11, count 0 2006.168.08:13:30.25#ibcon#read 4, iclass 11, count 0 2006.168.08:13:30.25#ibcon#about to read 5, iclass 11, count 0 2006.168.08:13:30.25#ibcon#read 5, iclass 11, count 0 2006.168.08:13:30.25#ibcon#about to read 6, iclass 11, count 0 2006.168.08:13:30.25#ibcon#read 6, iclass 11, count 0 2006.168.08:13:30.25#ibcon#end of sib2, iclass 11, count 0 2006.168.08:13:30.25#ibcon#*mode == 0, iclass 11, count 0 2006.168.08:13:30.25#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.168.08:13:30.25#ibcon#[25=USB\r\n] 2006.168.08:13:30.25#ibcon#*before write, iclass 11, count 0 2006.168.08:13:30.25#ibcon#enter sib2, iclass 11, count 0 2006.168.08:13:30.25#ibcon#flushed, iclass 11, count 0 2006.168.08:13:30.25#ibcon#about to write, iclass 11, count 0 2006.168.08:13:30.25#ibcon#wrote, iclass 11, count 0 2006.168.08:13:30.25#ibcon#about to read 3, iclass 11, count 0 2006.168.08:13:30.28#ibcon#read 3, iclass 11, count 0 2006.168.08:13:30.28#ibcon#about to read 4, iclass 11, count 0 2006.168.08:13:30.28#ibcon#read 4, iclass 11, count 0 2006.168.08:13:30.28#ibcon#about to read 5, iclass 11, count 0 2006.168.08:13:30.28#ibcon#read 5, iclass 11, count 0 2006.168.08:13:30.28#ibcon#about to read 6, iclass 11, count 0 2006.168.08:13:30.28#ibcon#read 6, iclass 11, count 0 2006.168.08:13:30.28#ibcon#end of sib2, iclass 11, count 0 2006.168.08:13:30.28#ibcon#*after write, iclass 11, count 0 2006.168.08:13:30.28#ibcon#*before return 0, iclass 11, count 0 2006.168.08:13:30.28#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.168.08:13:30.28#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.168.08:13:30.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.168.08:13:30.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.168.08:13:30.28$vc4f8/valo=8,852.99 2006.168.08:13:30.28#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.168.08:13:30.28#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.168.08:13:30.28#ibcon#ireg 17 cls_cnt 0 2006.168.08:13:30.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.168.08:13:30.28#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.168.08:13:30.28#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.168.08:13:30.28#ibcon#enter wrdev, iclass 13, count 0 2006.168.08:13:30.28#ibcon#first serial, iclass 13, count 0 2006.168.08:13:30.28#ibcon#enter sib2, iclass 13, count 0 2006.168.08:13:30.28#ibcon#flushed, iclass 13, count 0 2006.168.08:13:30.28#ibcon#about to write, iclass 13, count 0 2006.168.08:13:30.28#ibcon#wrote, iclass 13, count 0 2006.168.08:13:30.28#ibcon#about to read 3, iclass 13, count 0 2006.168.08:13:30.30#ibcon#read 3, iclass 13, count 0 2006.168.08:13:30.30#ibcon#about to read 4, iclass 13, count 0 2006.168.08:13:30.30#ibcon#read 4, iclass 13, count 0 2006.168.08:13:30.30#ibcon#about to read 5, iclass 13, count 0 2006.168.08:13:30.30#ibcon#read 5, iclass 13, count 0 2006.168.08:13:30.30#ibcon#about to read 6, iclass 13, count 0 2006.168.08:13:30.30#ibcon#read 6, iclass 13, count 0 2006.168.08:13:30.30#ibcon#end of sib2, iclass 13, count 0 2006.168.08:13:30.30#ibcon#*mode == 0, iclass 13, count 0 2006.168.08:13:30.30#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.168.08:13:30.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.08:13:30.30#ibcon#*before write, iclass 13, count 0 2006.168.08:13:30.30#ibcon#enter sib2, iclass 13, count 0 2006.168.08:13:30.30#ibcon#flushed, iclass 13, count 0 2006.168.08:13:30.30#ibcon#about to write, iclass 13, count 0 2006.168.08:13:30.30#ibcon#wrote, iclass 13, count 0 2006.168.08:13:30.30#ibcon#about to read 3, iclass 13, count 0 2006.168.08:13:30.34#ibcon#read 3, iclass 13, count 0 2006.168.08:13:30.34#ibcon#about to read 4, iclass 13, count 0 2006.168.08:13:30.34#ibcon#read 4, iclass 13, count 0 2006.168.08:13:30.34#ibcon#about to read 5, iclass 13, count 0 2006.168.08:13:30.34#ibcon#read 5, iclass 13, count 0 2006.168.08:13:30.34#ibcon#about to read 6, iclass 13, count 0 2006.168.08:13:30.34#ibcon#read 6, iclass 13, count 0 2006.168.08:13:30.34#ibcon#end of sib2, iclass 13, count 0 2006.168.08:13:30.34#ibcon#*after write, iclass 13, count 0 2006.168.08:13:30.34#ibcon#*before return 0, iclass 13, count 0 2006.168.08:13:30.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.168.08:13:30.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.168.08:13:30.34#ibcon#about to clear, iclass 13 cls_cnt 0 2006.168.08:13:30.34#ibcon#cleared, iclass 13 cls_cnt 0 2006.168.08:13:30.34$vc4f8/va=8,7 2006.168.08:13:30.34#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.168.08:13:30.34#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.168.08:13:30.34#ibcon#ireg 11 cls_cnt 2 2006.168.08:13:30.34#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.168.08:13:30.40#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.168.08:13:30.40#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.168.08:13:30.40#ibcon#enter wrdev, iclass 15, count 2 2006.168.08:13:30.40#ibcon#first serial, iclass 15, count 2 2006.168.08:13:30.40#ibcon#enter sib2, iclass 15, count 2 2006.168.08:13:30.40#ibcon#flushed, iclass 15, count 2 2006.168.08:13:30.40#ibcon#about to write, iclass 15, count 2 2006.168.08:13:30.40#ibcon#wrote, iclass 15, count 2 2006.168.08:13:30.40#ibcon#about to read 3, iclass 15, count 2 2006.168.08:13:30.42#ibcon#read 3, iclass 15, count 2 2006.168.08:13:30.42#ibcon#about to read 4, iclass 15, count 2 2006.168.08:13:30.42#ibcon#read 4, iclass 15, count 2 2006.168.08:13:30.42#ibcon#about to read 5, iclass 15, count 2 2006.168.08:13:30.42#ibcon#read 5, iclass 15, count 2 2006.168.08:13:30.42#ibcon#about to read 6, iclass 15, count 2 2006.168.08:13:30.42#ibcon#read 6, iclass 15, count 2 2006.168.08:13:30.42#ibcon#end of sib2, iclass 15, count 2 2006.168.08:13:30.42#ibcon#*mode == 0, iclass 15, count 2 2006.168.08:13:30.42#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.168.08:13:30.42#ibcon#[25=AT08-07\r\n] 2006.168.08:13:30.42#ibcon#*before write, iclass 15, count 2 2006.168.08:13:30.42#ibcon#enter sib2, iclass 15, count 2 2006.168.08:13:30.42#ibcon#flushed, iclass 15, count 2 2006.168.08:13:30.42#ibcon#about to write, iclass 15, count 2 2006.168.08:13:30.42#ibcon#wrote, iclass 15, count 2 2006.168.08:13:30.42#ibcon#about to read 3, iclass 15, count 2 2006.168.08:13:30.45#ibcon#read 3, iclass 15, count 2 2006.168.08:13:30.45#ibcon#about to read 4, iclass 15, count 2 2006.168.08:13:30.45#ibcon#read 4, iclass 15, count 2 2006.168.08:13:30.45#ibcon#about to read 5, iclass 15, count 2 2006.168.08:13:30.45#ibcon#read 5, iclass 15, count 2 2006.168.08:13:30.45#ibcon#about to read 6, iclass 15, count 2 2006.168.08:13:30.45#ibcon#read 6, iclass 15, count 2 2006.168.08:13:30.45#ibcon#end of sib2, iclass 15, count 2 2006.168.08:13:30.45#ibcon#*after write, iclass 15, count 2 2006.168.08:13:30.45#ibcon#*before return 0, iclass 15, count 2 2006.168.08:13:30.45#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.168.08:13:30.45#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.168.08:13:30.45#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.168.08:13:30.45#ibcon#ireg 7 cls_cnt 0 2006.168.08:13:30.45#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.168.08:13:30.57#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.168.08:13:30.57#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.168.08:13:30.57#ibcon#enter wrdev, iclass 15, count 0 2006.168.08:13:30.57#ibcon#first serial, iclass 15, count 0 2006.168.08:13:30.57#ibcon#enter sib2, iclass 15, count 0 2006.168.08:13:30.57#ibcon#flushed, iclass 15, count 0 2006.168.08:13:30.57#ibcon#about to write, iclass 15, count 0 2006.168.08:13:30.57#ibcon#wrote, iclass 15, count 0 2006.168.08:13:30.57#ibcon#about to read 3, iclass 15, count 0 2006.168.08:13:30.59#ibcon#read 3, iclass 15, count 0 2006.168.08:13:30.59#ibcon#about to read 4, iclass 15, count 0 2006.168.08:13:30.59#ibcon#read 4, iclass 15, count 0 2006.168.08:13:30.59#ibcon#about to read 5, iclass 15, count 0 2006.168.08:13:30.59#ibcon#read 5, iclass 15, count 0 2006.168.08:13:30.59#ibcon#about to read 6, iclass 15, count 0 2006.168.08:13:30.59#ibcon#read 6, iclass 15, count 0 2006.168.08:13:30.59#ibcon#end of sib2, iclass 15, count 0 2006.168.08:13:30.59#ibcon#*mode == 0, iclass 15, count 0 2006.168.08:13:30.59#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.168.08:13:30.59#ibcon#[25=USB\r\n] 2006.168.08:13:30.59#ibcon#*before write, iclass 15, count 0 2006.168.08:13:30.59#ibcon#enter sib2, iclass 15, count 0 2006.168.08:13:30.59#ibcon#flushed, iclass 15, count 0 2006.168.08:13:30.59#ibcon#about to write, iclass 15, count 0 2006.168.08:13:30.59#ibcon#wrote, iclass 15, count 0 2006.168.08:13:30.59#ibcon#about to read 3, iclass 15, count 0 2006.168.08:13:30.62#ibcon#read 3, iclass 15, count 0 2006.168.08:13:30.62#ibcon#about to read 4, iclass 15, count 0 2006.168.08:13:30.62#ibcon#read 4, iclass 15, count 0 2006.168.08:13:30.62#ibcon#about to read 5, iclass 15, count 0 2006.168.08:13:30.62#ibcon#read 5, iclass 15, count 0 2006.168.08:13:30.62#ibcon#about to read 6, iclass 15, count 0 2006.168.08:13:30.62#ibcon#read 6, iclass 15, count 0 2006.168.08:13:30.62#ibcon#end of sib2, iclass 15, count 0 2006.168.08:13:30.62#ibcon#*after write, iclass 15, count 0 2006.168.08:13:30.62#ibcon#*before return 0, iclass 15, count 0 2006.168.08:13:30.62#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.168.08:13:30.62#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.168.08:13:30.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.168.08:13:30.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.168.08:13:30.62$vc4f8/vblo=1,632.99 2006.168.08:13:30.62#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.168.08:13:30.62#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.168.08:13:30.62#ibcon#ireg 17 cls_cnt 0 2006.168.08:13:30.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:13:30.62#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:13:30.62#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:13:30.62#ibcon#enter wrdev, iclass 17, count 0 2006.168.08:13:30.62#ibcon#first serial, iclass 17, count 0 2006.168.08:13:30.62#ibcon#enter sib2, iclass 17, count 0 2006.168.08:13:30.62#ibcon#flushed, iclass 17, count 0 2006.168.08:13:30.62#ibcon#about to write, iclass 17, count 0 2006.168.08:13:30.62#ibcon#wrote, iclass 17, count 0 2006.168.08:13:30.62#ibcon#about to read 3, iclass 17, count 0 2006.168.08:13:30.64#ibcon#read 3, iclass 17, count 0 2006.168.08:13:30.64#ibcon#about to read 4, iclass 17, count 0 2006.168.08:13:30.64#ibcon#read 4, iclass 17, count 0 2006.168.08:13:30.64#ibcon#about to read 5, iclass 17, count 0 2006.168.08:13:30.64#ibcon#read 5, iclass 17, count 0 2006.168.08:13:30.64#ibcon#about to read 6, iclass 17, count 0 2006.168.08:13:30.64#ibcon#read 6, iclass 17, count 0 2006.168.08:13:30.64#ibcon#end of sib2, iclass 17, count 0 2006.168.08:13:30.64#ibcon#*mode == 0, iclass 17, count 0 2006.168.08:13:30.64#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.168.08:13:30.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.08:13:30.64#ibcon#*before write, iclass 17, count 0 2006.168.08:13:30.64#ibcon#enter sib2, iclass 17, count 0 2006.168.08:13:30.64#ibcon#flushed, iclass 17, count 0 2006.168.08:13:30.64#ibcon#about to write, iclass 17, count 0 2006.168.08:13:30.64#ibcon#wrote, iclass 17, count 0 2006.168.08:13:30.64#ibcon#about to read 3, iclass 17, count 0 2006.168.08:13:30.68#ibcon#read 3, iclass 17, count 0 2006.168.08:13:30.68#ibcon#about to read 4, iclass 17, count 0 2006.168.08:13:30.68#ibcon#read 4, iclass 17, count 0 2006.168.08:13:30.68#ibcon#about to read 5, iclass 17, count 0 2006.168.08:13:30.68#ibcon#read 5, iclass 17, count 0 2006.168.08:13:30.68#ibcon#about to read 6, iclass 17, count 0 2006.168.08:13:30.68#ibcon#read 6, iclass 17, count 0 2006.168.08:13:30.68#ibcon#end of sib2, iclass 17, count 0 2006.168.08:13:30.68#ibcon#*after write, iclass 17, count 0 2006.168.08:13:30.68#ibcon#*before return 0, iclass 17, count 0 2006.168.08:13:30.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:13:30.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:13:30.68#ibcon#about to clear, iclass 17 cls_cnt 0 2006.168.08:13:30.68#ibcon#cleared, iclass 17 cls_cnt 0 2006.168.08:13:30.68$vc4f8/vb=1,4 2006.168.08:13:30.68#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.168.08:13:30.68#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.168.08:13:30.68#ibcon#ireg 11 cls_cnt 2 2006.168.08:13:30.68#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:13:30.68#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:13:30.68#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:13:30.68#ibcon#enter wrdev, iclass 19, count 2 2006.168.08:13:30.68#ibcon#first serial, iclass 19, count 2 2006.168.08:13:30.68#ibcon#enter sib2, iclass 19, count 2 2006.168.08:13:30.68#ibcon#flushed, iclass 19, count 2 2006.168.08:13:30.68#ibcon#about to write, iclass 19, count 2 2006.168.08:13:30.68#ibcon#wrote, iclass 19, count 2 2006.168.08:13:30.68#ibcon#about to read 3, iclass 19, count 2 2006.168.08:13:30.70#ibcon#read 3, iclass 19, count 2 2006.168.08:13:30.70#ibcon#about to read 4, iclass 19, count 2 2006.168.08:13:30.70#ibcon#read 4, iclass 19, count 2 2006.168.08:13:30.70#ibcon#about to read 5, iclass 19, count 2 2006.168.08:13:30.70#ibcon#read 5, iclass 19, count 2 2006.168.08:13:30.70#ibcon#about to read 6, iclass 19, count 2 2006.168.08:13:30.70#ibcon#read 6, iclass 19, count 2 2006.168.08:13:30.70#ibcon#end of sib2, iclass 19, count 2 2006.168.08:13:30.70#ibcon#*mode == 0, iclass 19, count 2 2006.168.08:13:30.70#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.168.08:13:30.70#ibcon#[27=AT01-04\r\n] 2006.168.08:13:30.70#ibcon#*before write, iclass 19, count 2 2006.168.08:13:30.70#ibcon#enter sib2, iclass 19, count 2 2006.168.08:13:30.70#ibcon#flushed, iclass 19, count 2 2006.168.08:13:30.70#ibcon#about to write, iclass 19, count 2 2006.168.08:13:30.70#ibcon#wrote, iclass 19, count 2 2006.168.08:13:30.70#ibcon#about to read 3, iclass 19, count 2 2006.168.08:13:30.73#ibcon#read 3, iclass 19, count 2 2006.168.08:13:30.73#ibcon#about to read 4, iclass 19, count 2 2006.168.08:13:30.73#ibcon#read 4, iclass 19, count 2 2006.168.08:13:30.73#ibcon#about to read 5, iclass 19, count 2 2006.168.08:13:30.73#ibcon#read 5, iclass 19, count 2 2006.168.08:13:30.73#ibcon#about to read 6, iclass 19, count 2 2006.168.08:13:30.73#ibcon#read 6, iclass 19, count 2 2006.168.08:13:30.73#ibcon#end of sib2, iclass 19, count 2 2006.168.08:13:30.73#ibcon#*after write, iclass 19, count 2 2006.168.08:13:30.73#ibcon#*before return 0, iclass 19, count 2 2006.168.08:13:30.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:13:30.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:13:30.73#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.168.08:13:30.73#ibcon#ireg 7 cls_cnt 0 2006.168.08:13:30.73#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:13:30.85#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:13:30.85#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:13:30.85#ibcon#enter wrdev, iclass 19, count 0 2006.168.08:13:30.85#ibcon#first serial, iclass 19, count 0 2006.168.08:13:30.85#ibcon#enter sib2, iclass 19, count 0 2006.168.08:13:30.85#ibcon#flushed, iclass 19, count 0 2006.168.08:13:30.85#ibcon#about to write, iclass 19, count 0 2006.168.08:13:30.85#ibcon#wrote, iclass 19, count 0 2006.168.08:13:30.85#ibcon#about to read 3, iclass 19, count 0 2006.168.08:13:30.87#ibcon#read 3, iclass 19, count 0 2006.168.08:13:30.87#ibcon#about to read 4, iclass 19, count 0 2006.168.08:13:30.87#ibcon#read 4, iclass 19, count 0 2006.168.08:13:30.87#ibcon#about to read 5, iclass 19, count 0 2006.168.08:13:30.87#ibcon#read 5, iclass 19, count 0 2006.168.08:13:30.87#ibcon#about to read 6, iclass 19, count 0 2006.168.08:13:30.87#ibcon#read 6, iclass 19, count 0 2006.168.08:13:30.87#ibcon#end of sib2, iclass 19, count 0 2006.168.08:13:30.87#ibcon#*mode == 0, iclass 19, count 0 2006.168.08:13:30.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.168.08:13:30.87#ibcon#[27=USB\r\n] 2006.168.08:13:30.87#ibcon#*before write, iclass 19, count 0 2006.168.08:13:30.87#ibcon#enter sib2, iclass 19, count 0 2006.168.08:13:30.87#ibcon#flushed, iclass 19, count 0 2006.168.08:13:30.87#ibcon#about to write, iclass 19, count 0 2006.168.08:13:30.87#ibcon#wrote, iclass 19, count 0 2006.168.08:13:30.87#ibcon#about to read 3, iclass 19, count 0 2006.168.08:13:30.90#ibcon#read 3, iclass 19, count 0 2006.168.08:13:30.90#ibcon#about to read 4, iclass 19, count 0 2006.168.08:13:30.90#ibcon#read 4, iclass 19, count 0 2006.168.08:13:30.90#ibcon#about to read 5, iclass 19, count 0 2006.168.08:13:30.90#ibcon#read 5, iclass 19, count 0 2006.168.08:13:30.90#ibcon#about to read 6, iclass 19, count 0 2006.168.08:13:30.90#ibcon#read 6, iclass 19, count 0 2006.168.08:13:30.90#ibcon#end of sib2, iclass 19, count 0 2006.168.08:13:30.90#ibcon#*after write, iclass 19, count 0 2006.168.08:13:30.90#ibcon#*before return 0, iclass 19, count 0 2006.168.08:13:30.90#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:13:30.90#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:13:30.90#ibcon#about to clear, iclass 19 cls_cnt 0 2006.168.08:13:30.90#ibcon#cleared, iclass 19 cls_cnt 0 2006.168.08:13:30.90$vc4f8/vblo=2,640.99 2006.168.08:13:30.90#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.168.08:13:30.90#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.168.08:13:30.90#ibcon#ireg 17 cls_cnt 0 2006.168.08:13:30.90#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:13:30.90#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:13:30.90#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:13:30.90#ibcon#enter wrdev, iclass 21, count 0 2006.168.08:13:30.90#ibcon#first serial, iclass 21, count 0 2006.168.08:13:30.90#ibcon#enter sib2, iclass 21, count 0 2006.168.08:13:30.90#ibcon#flushed, iclass 21, count 0 2006.168.08:13:30.90#ibcon#about to write, iclass 21, count 0 2006.168.08:13:30.90#ibcon#wrote, iclass 21, count 0 2006.168.08:13:30.90#ibcon#about to read 3, iclass 21, count 0 2006.168.08:13:30.92#ibcon#read 3, iclass 21, count 0 2006.168.08:13:30.92#ibcon#about to read 4, iclass 21, count 0 2006.168.08:13:30.92#ibcon#read 4, iclass 21, count 0 2006.168.08:13:30.92#ibcon#about to read 5, iclass 21, count 0 2006.168.08:13:30.92#ibcon#read 5, iclass 21, count 0 2006.168.08:13:30.92#ibcon#about to read 6, iclass 21, count 0 2006.168.08:13:30.92#ibcon#read 6, iclass 21, count 0 2006.168.08:13:30.92#ibcon#end of sib2, iclass 21, count 0 2006.168.08:13:30.92#ibcon#*mode == 0, iclass 21, count 0 2006.168.08:13:30.92#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.168.08:13:30.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.08:13:30.92#ibcon#*before write, iclass 21, count 0 2006.168.08:13:30.92#ibcon#enter sib2, iclass 21, count 0 2006.168.08:13:30.92#ibcon#flushed, iclass 21, count 0 2006.168.08:13:30.92#ibcon#about to write, iclass 21, count 0 2006.168.08:13:30.92#ibcon#wrote, iclass 21, count 0 2006.168.08:13:30.92#ibcon#about to read 3, iclass 21, count 0 2006.168.08:13:30.96#ibcon#read 3, iclass 21, count 0 2006.168.08:13:30.96#ibcon#about to read 4, iclass 21, count 0 2006.168.08:13:30.96#ibcon#read 4, iclass 21, count 0 2006.168.08:13:30.96#ibcon#about to read 5, iclass 21, count 0 2006.168.08:13:30.96#ibcon#read 5, iclass 21, count 0 2006.168.08:13:30.96#ibcon#about to read 6, iclass 21, count 0 2006.168.08:13:30.96#ibcon#read 6, iclass 21, count 0 2006.168.08:13:30.96#ibcon#end of sib2, iclass 21, count 0 2006.168.08:13:30.96#ibcon#*after write, iclass 21, count 0 2006.168.08:13:30.96#ibcon#*before return 0, iclass 21, count 0 2006.168.08:13:30.96#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:13:30.96#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:13:30.96#ibcon#about to clear, iclass 21 cls_cnt 0 2006.168.08:13:30.96#ibcon#cleared, iclass 21 cls_cnt 0 2006.168.08:13:30.96$vc4f8/vb=2,4 2006.168.08:13:30.96#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.168.08:13:30.96#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.168.08:13:30.96#ibcon#ireg 11 cls_cnt 2 2006.168.08:13:30.96#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.168.08:13:31.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.168.08:13:31.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.168.08:13:31.02#ibcon#enter wrdev, iclass 23, count 2 2006.168.08:13:31.02#ibcon#first serial, iclass 23, count 2 2006.168.08:13:31.02#ibcon#enter sib2, iclass 23, count 2 2006.168.08:13:31.02#ibcon#flushed, iclass 23, count 2 2006.168.08:13:31.02#ibcon#about to write, iclass 23, count 2 2006.168.08:13:31.02#ibcon#wrote, iclass 23, count 2 2006.168.08:13:31.02#ibcon#about to read 3, iclass 23, count 2 2006.168.08:13:31.04#ibcon#read 3, iclass 23, count 2 2006.168.08:13:31.04#ibcon#about to read 4, iclass 23, count 2 2006.168.08:13:31.04#ibcon#read 4, iclass 23, count 2 2006.168.08:13:31.04#ibcon#about to read 5, iclass 23, count 2 2006.168.08:13:31.04#ibcon#read 5, iclass 23, count 2 2006.168.08:13:31.04#ibcon#about to read 6, iclass 23, count 2 2006.168.08:13:31.04#ibcon#read 6, iclass 23, count 2 2006.168.08:13:31.04#ibcon#end of sib2, iclass 23, count 2 2006.168.08:13:31.04#ibcon#*mode == 0, iclass 23, count 2 2006.168.08:13:31.04#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.168.08:13:31.04#ibcon#[27=AT02-04\r\n] 2006.168.08:13:31.04#ibcon#*before write, iclass 23, count 2 2006.168.08:13:31.04#ibcon#enter sib2, iclass 23, count 2 2006.168.08:13:31.04#ibcon#flushed, iclass 23, count 2 2006.168.08:13:31.04#ibcon#about to write, iclass 23, count 2 2006.168.08:13:31.04#ibcon#wrote, iclass 23, count 2 2006.168.08:13:31.04#ibcon#about to read 3, iclass 23, count 2 2006.168.08:13:31.07#ibcon#read 3, iclass 23, count 2 2006.168.08:13:31.07#ibcon#about to read 4, iclass 23, count 2 2006.168.08:13:31.07#ibcon#read 4, iclass 23, count 2 2006.168.08:13:31.07#ibcon#about to read 5, iclass 23, count 2 2006.168.08:13:31.07#ibcon#read 5, iclass 23, count 2 2006.168.08:13:31.07#ibcon#about to read 6, iclass 23, count 2 2006.168.08:13:31.07#ibcon#read 6, iclass 23, count 2 2006.168.08:13:31.07#ibcon#end of sib2, iclass 23, count 2 2006.168.08:13:31.07#ibcon#*after write, iclass 23, count 2 2006.168.08:13:31.07#ibcon#*before return 0, iclass 23, count 2 2006.168.08:13:31.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.168.08:13:31.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.168.08:13:31.07#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.168.08:13:31.07#ibcon#ireg 7 cls_cnt 0 2006.168.08:13:31.07#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.168.08:13:31.19#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.168.08:13:31.19#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.168.08:13:31.19#ibcon#enter wrdev, iclass 23, count 0 2006.168.08:13:31.19#ibcon#first serial, iclass 23, count 0 2006.168.08:13:31.19#ibcon#enter sib2, iclass 23, count 0 2006.168.08:13:31.19#ibcon#flushed, iclass 23, count 0 2006.168.08:13:31.19#ibcon#about to write, iclass 23, count 0 2006.168.08:13:31.19#ibcon#wrote, iclass 23, count 0 2006.168.08:13:31.19#ibcon#about to read 3, iclass 23, count 0 2006.168.08:13:31.21#ibcon#read 3, iclass 23, count 0 2006.168.08:13:31.21#ibcon#about to read 4, iclass 23, count 0 2006.168.08:13:31.21#ibcon#read 4, iclass 23, count 0 2006.168.08:13:31.21#ibcon#about to read 5, iclass 23, count 0 2006.168.08:13:31.21#ibcon#read 5, iclass 23, count 0 2006.168.08:13:31.21#ibcon#about to read 6, iclass 23, count 0 2006.168.08:13:31.21#ibcon#read 6, iclass 23, count 0 2006.168.08:13:31.21#ibcon#end of sib2, iclass 23, count 0 2006.168.08:13:31.21#ibcon#*mode == 0, iclass 23, count 0 2006.168.08:13:31.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.168.08:13:31.21#ibcon#[27=USB\r\n] 2006.168.08:13:31.21#ibcon#*before write, iclass 23, count 0 2006.168.08:13:31.21#ibcon#enter sib2, iclass 23, count 0 2006.168.08:13:31.21#ibcon#flushed, iclass 23, count 0 2006.168.08:13:31.21#ibcon#about to write, iclass 23, count 0 2006.168.08:13:31.21#ibcon#wrote, iclass 23, count 0 2006.168.08:13:31.21#ibcon#about to read 3, iclass 23, count 0 2006.168.08:13:31.24#ibcon#read 3, iclass 23, count 0 2006.168.08:13:31.24#ibcon#about to read 4, iclass 23, count 0 2006.168.08:13:31.24#ibcon#read 4, iclass 23, count 0 2006.168.08:13:31.24#ibcon#about to read 5, iclass 23, count 0 2006.168.08:13:31.24#ibcon#read 5, iclass 23, count 0 2006.168.08:13:31.24#ibcon#about to read 6, iclass 23, count 0 2006.168.08:13:31.24#ibcon#read 6, iclass 23, count 0 2006.168.08:13:31.24#ibcon#end of sib2, iclass 23, count 0 2006.168.08:13:31.24#ibcon#*after write, iclass 23, count 0 2006.168.08:13:31.24#ibcon#*before return 0, iclass 23, count 0 2006.168.08:13:31.24#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.168.08:13:31.24#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.168.08:13:31.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.168.08:13:31.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.168.08:13:31.24$vc4f8/vblo=3,656.99 2006.168.08:13:31.24#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.168.08:13:31.24#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.168.08:13:31.24#ibcon#ireg 17 cls_cnt 0 2006.168.08:13:31.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.168.08:13:31.24#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.168.08:13:31.24#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.168.08:13:31.24#ibcon#enter wrdev, iclass 25, count 0 2006.168.08:13:31.24#ibcon#first serial, iclass 25, count 0 2006.168.08:13:31.24#ibcon#enter sib2, iclass 25, count 0 2006.168.08:13:31.24#ibcon#flushed, iclass 25, count 0 2006.168.08:13:31.24#ibcon#about to write, iclass 25, count 0 2006.168.08:13:31.24#ibcon#wrote, iclass 25, count 0 2006.168.08:13:31.24#ibcon#about to read 3, iclass 25, count 0 2006.168.08:13:31.26#ibcon#read 3, iclass 25, count 0 2006.168.08:13:31.26#ibcon#about to read 4, iclass 25, count 0 2006.168.08:13:31.26#ibcon#read 4, iclass 25, count 0 2006.168.08:13:31.26#ibcon#about to read 5, iclass 25, count 0 2006.168.08:13:31.26#ibcon#read 5, iclass 25, count 0 2006.168.08:13:31.26#ibcon#about to read 6, iclass 25, count 0 2006.168.08:13:31.26#ibcon#read 6, iclass 25, count 0 2006.168.08:13:31.26#ibcon#end of sib2, iclass 25, count 0 2006.168.08:13:31.26#ibcon#*mode == 0, iclass 25, count 0 2006.168.08:13:31.26#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.168.08:13:31.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.08:13:31.26#ibcon#*before write, iclass 25, count 0 2006.168.08:13:31.26#ibcon#enter sib2, iclass 25, count 0 2006.168.08:13:31.26#ibcon#flushed, iclass 25, count 0 2006.168.08:13:31.26#ibcon#about to write, iclass 25, count 0 2006.168.08:13:31.26#ibcon#wrote, iclass 25, count 0 2006.168.08:13:31.26#ibcon#about to read 3, iclass 25, count 0 2006.168.08:13:31.30#ibcon#read 3, iclass 25, count 0 2006.168.08:13:31.30#ibcon#about to read 4, iclass 25, count 0 2006.168.08:13:31.30#ibcon#read 4, iclass 25, count 0 2006.168.08:13:31.30#ibcon#about to read 5, iclass 25, count 0 2006.168.08:13:31.30#ibcon#read 5, iclass 25, count 0 2006.168.08:13:31.30#ibcon#about to read 6, iclass 25, count 0 2006.168.08:13:31.30#ibcon#read 6, iclass 25, count 0 2006.168.08:13:31.30#ibcon#end of sib2, iclass 25, count 0 2006.168.08:13:31.30#ibcon#*after write, iclass 25, count 0 2006.168.08:13:31.30#ibcon#*before return 0, iclass 25, count 0 2006.168.08:13:31.30#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.168.08:13:31.30#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.168.08:13:31.30#ibcon#about to clear, iclass 25 cls_cnt 0 2006.168.08:13:31.30#ibcon#cleared, iclass 25 cls_cnt 0 2006.168.08:13:31.30$vc4f8/vb=3,4 2006.168.08:13:31.30#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.168.08:13:31.30#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.168.08:13:31.30#ibcon#ireg 11 cls_cnt 2 2006.168.08:13:31.30#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.168.08:13:31.36#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.168.08:13:31.36#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.168.08:13:31.36#ibcon#enter wrdev, iclass 27, count 2 2006.168.08:13:31.36#ibcon#first serial, iclass 27, count 2 2006.168.08:13:31.36#ibcon#enter sib2, iclass 27, count 2 2006.168.08:13:31.36#ibcon#flushed, iclass 27, count 2 2006.168.08:13:31.36#ibcon#about to write, iclass 27, count 2 2006.168.08:13:31.36#ibcon#wrote, iclass 27, count 2 2006.168.08:13:31.36#ibcon#about to read 3, iclass 27, count 2 2006.168.08:13:31.38#ibcon#read 3, iclass 27, count 2 2006.168.08:13:31.38#ibcon#about to read 4, iclass 27, count 2 2006.168.08:13:31.38#ibcon#read 4, iclass 27, count 2 2006.168.08:13:31.38#ibcon#about to read 5, iclass 27, count 2 2006.168.08:13:31.38#ibcon#read 5, iclass 27, count 2 2006.168.08:13:31.38#ibcon#about to read 6, iclass 27, count 2 2006.168.08:13:31.38#ibcon#read 6, iclass 27, count 2 2006.168.08:13:31.38#ibcon#end of sib2, iclass 27, count 2 2006.168.08:13:31.38#ibcon#*mode == 0, iclass 27, count 2 2006.168.08:13:31.38#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.168.08:13:31.38#ibcon#[27=AT03-04\r\n] 2006.168.08:13:31.38#ibcon#*before write, iclass 27, count 2 2006.168.08:13:31.38#ibcon#enter sib2, iclass 27, count 2 2006.168.08:13:31.38#ibcon#flushed, iclass 27, count 2 2006.168.08:13:31.38#ibcon#about to write, iclass 27, count 2 2006.168.08:13:31.38#ibcon#wrote, iclass 27, count 2 2006.168.08:13:31.38#ibcon#about to read 3, iclass 27, count 2 2006.168.08:13:31.41#ibcon#read 3, iclass 27, count 2 2006.168.08:13:31.41#ibcon#about to read 4, iclass 27, count 2 2006.168.08:13:31.41#ibcon#read 4, iclass 27, count 2 2006.168.08:13:31.41#ibcon#about to read 5, iclass 27, count 2 2006.168.08:13:31.41#ibcon#read 5, iclass 27, count 2 2006.168.08:13:31.41#ibcon#about to read 6, iclass 27, count 2 2006.168.08:13:31.41#ibcon#read 6, iclass 27, count 2 2006.168.08:13:31.41#ibcon#end of sib2, iclass 27, count 2 2006.168.08:13:31.41#ibcon#*after write, iclass 27, count 2 2006.168.08:13:31.41#ibcon#*before return 0, iclass 27, count 2 2006.168.08:13:31.41#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.168.08:13:31.41#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.168.08:13:31.41#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.168.08:13:31.41#ibcon#ireg 7 cls_cnt 0 2006.168.08:13:31.41#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.168.08:13:31.53#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.168.08:13:31.53#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.168.08:13:31.53#ibcon#enter wrdev, iclass 27, count 0 2006.168.08:13:31.53#ibcon#first serial, iclass 27, count 0 2006.168.08:13:31.53#ibcon#enter sib2, iclass 27, count 0 2006.168.08:13:31.53#ibcon#flushed, iclass 27, count 0 2006.168.08:13:31.53#ibcon#about to write, iclass 27, count 0 2006.168.08:13:31.53#ibcon#wrote, iclass 27, count 0 2006.168.08:13:31.53#ibcon#about to read 3, iclass 27, count 0 2006.168.08:13:31.55#ibcon#read 3, iclass 27, count 0 2006.168.08:13:31.55#ibcon#about to read 4, iclass 27, count 0 2006.168.08:13:31.55#ibcon#read 4, iclass 27, count 0 2006.168.08:13:31.55#ibcon#about to read 5, iclass 27, count 0 2006.168.08:13:31.55#ibcon#read 5, iclass 27, count 0 2006.168.08:13:31.55#ibcon#about to read 6, iclass 27, count 0 2006.168.08:13:31.55#ibcon#read 6, iclass 27, count 0 2006.168.08:13:31.55#ibcon#end of sib2, iclass 27, count 0 2006.168.08:13:31.55#ibcon#*mode == 0, iclass 27, count 0 2006.168.08:13:31.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.168.08:13:31.55#ibcon#[27=USB\r\n] 2006.168.08:13:31.55#ibcon#*before write, iclass 27, count 0 2006.168.08:13:31.55#ibcon#enter sib2, iclass 27, count 0 2006.168.08:13:31.55#ibcon#flushed, iclass 27, count 0 2006.168.08:13:31.55#ibcon#about to write, iclass 27, count 0 2006.168.08:13:31.55#ibcon#wrote, iclass 27, count 0 2006.168.08:13:31.55#ibcon#about to read 3, iclass 27, count 0 2006.168.08:13:31.58#ibcon#read 3, iclass 27, count 0 2006.168.08:13:31.58#ibcon#about to read 4, iclass 27, count 0 2006.168.08:13:31.58#ibcon#read 4, iclass 27, count 0 2006.168.08:13:31.58#ibcon#about to read 5, iclass 27, count 0 2006.168.08:13:31.58#ibcon#read 5, iclass 27, count 0 2006.168.08:13:31.58#ibcon#about to read 6, iclass 27, count 0 2006.168.08:13:31.58#ibcon#read 6, iclass 27, count 0 2006.168.08:13:31.58#ibcon#end of sib2, iclass 27, count 0 2006.168.08:13:31.58#ibcon#*after write, iclass 27, count 0 2006.168.08:13:31.58#ibcon#*before return 0, iclass 27, count 0 2006.168.08:13:31.58#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.168.08:13:31.58#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.168.08:13:31.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.168.08:13:31.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.168.08:13:31.58$vc4f8/vblo=4,712.99 2006.168.08:13:31.58#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.168.08:13:31.58#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.168.08:13:31.58#ibcon#ireg 17 cls_cnt 0 2006.168.08:13:31.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.168.08:13:31.58#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.168.08:13:31.58#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.168.08:13:31.58#ibcon#enter wrdev, iclass 29, count 0 2006.168.08:13:31.58#ibcon#first serial, iclass 29, count 0 2006.168.08:13:31.58#ibcon#enter sib2, iclass 29, count 0 2006.168.08:13:31.58#ibcon#flushed, iclass 29, count 0 2006.168.08:13:31.58#ibcon#about to write, iclass 29, count 0 2006.168.08:13:31.58#ibcon#wrote, iclass 29, count 0 2006.168.08:13:31.58#ibcon#about to read 3, iclass 29, count 0 2006.168.08:13:31.60#ibcon#read 3, iclass 29, count 0 2006.168.08:13:31.60#ibcon#about to read 4, iclass 29, count 0 2006.168.08:13:31.60#ibcon#read 4, iclass 29, count 0 2006.168.08:13:31.60#ibcon#about to read 5, iclass 29, count 0 2006.168.08:13:31.60#ibcon#read 5, iclass 29, count 0 2006.168.08:13:31.60#ibcon#about to read 6, iclass 29, count 0 2006.168.08:13:31.60#ibcon#read 6, iclass 29, count 0 2006.168.08:13:31.60#ibcon#end of sib2, iclass 29, count 0 2006.168.08:13:31.60#ibcon#*mode == 0, iclass 29, count 0 2006.168.08:13:31.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.168.08:13:31.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.08:13:31.60#ibcon#*before write, iclass 29, count 0 2006.168.08:13:31.60#ibcon#enter sib2, iclass 29, count 0 2006.168.08:13:31.60#ibcon#flushed, iclass 29, count 0 2006.168.08:13:31.60#ibcon#about to write, iclass 29, count 0 2006.168.08:13:31.60#ibcon#wrote, iclass 29, count 0 2006.168.08:13:31.60#ibcon#about to read 3, iclass 29, count 0 2006.168.08:13:31.64#ibcon#read 3, iclass 29, count 0 2006.168.08:13:31.64#ibcon#about to read 4, iclass 29, count 0 2006.168.08:13:31.64#ibcon#read 4, iclass 29, count 0 2006.168.08:13:31.64#ibcon#about to read 5, iclass 29, count 0 2006.168.08:13:31.64#ibcon#read 5, iclass 29, count 0 2006.168.08:13:31.64#ibcon#about to read 6, iclass 29, count 0 2006.168.08:13:31.64#ibcon#read 6, iclass 29, count 0 2006.168.08:13:31.64#ibcon#end of sib2, iclass 29, count 0 2006.168.08:13:31.64#ibcon#*after write, iclass 29, count 0 2006.168.08:13:31.64#ibcon#*before return 0, iclass 29, count 0 2006.168.08:13:31.64#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.168.08:13:31.64#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.168.08:13:31.64#ibcon#about to clear, iclass 29 cls_cnt 0 2006.168.08:13:31.64#ibcon#cleared, iclass 29 cls_cnt 0 2006.168.08:13:31.64$vc4f8/vb=4,4 2006.168.08:13:31.64#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.168.08:13:31.64#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.168.08:13:31.64#ibcon#ireg 11 cls_cnt 2 2006.168.08:13:31.64#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.168.08:13:31.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.168.08:13:31.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.168.08:13:31.70#ibcon#enter wrdev, iclass 31, count 2 2006.168.08:13:31.70#ibcon#first serial, iclass 31, count 2 2006.168.08:13:31.70#ibcon#enter sib2, iclass 31, count 2 2006.168.08:13:31.70#ibcon#flushed, iclass 31, count 2 2006.168.08:13:31.70#ibcon#about to write, iclass 31, count 2 2006.168.08:13:31.70#ibcon#wrote, iclass 31, count 2 2006.168.08:13:31.70#ibcon#about to read 3, iclass 31, count 2 2006.168.08:13:31.72#ibcon#read 3, iclass 31, count 2 2006.168.08:13:31.72#ibcon#about to read 4, iclass 31, count 2 2006.168.08:13:31.72#ibcon#read 4, iclass 31, count 2 2006.168.08:13:31.72#ibcon#about to read 5, iclass 31, count 2 2006.168.08:13:31.72#ibcon#read 5, iclass 31, count 2 2006.168.08:13:31.72#ibcon#about to read 6, iclass 31, count 2 2006.168.08:13:31.72#ibcon#read 6, iclass 31, count 2 2006.168.08:13:31.72#ibcon#end of sib2, iclass 31, count 2 2006.168.08:13:31.72#ibcon#*mode == 0, iclass 31, count 2 2006.168.08:13:31.72#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.168.08:13:31.72#ibcon#[27=AT04-04\r\n] 2006.168.08:13:31.72#ibcon#*before write, iclass 31, count 2 2006.168.08:13:31.72#ibcon#enter sib2, iclass 31, count 2 2006.168.08:13:31.72#ibcon#flushed, iclass 31, count 2 2006.168.08:13:31.72#ibcon#about to write, iclass 31, count 2 2006.168.08:13:31.72#ibcon#wrote, iclass 31, count 2 2006.168.08:13:31.72#ibcon#about to read 3, iclass 31, count 2 2006.168.08:13:31.75#ibcon#read 3, iclass 31, count 2 2006.168.08:13:31.75#ibcon#about to read 4, iclass 31, count 2 2006.168.08:13:31.75#ibcon#read 4, iclass 31, count 2 2006.168.08:13:31.75#ibcon#about to read 5, iclass 31, count 2 2006.168.08:13:31.75#ibcon#read 5, iclass 31, count 2 2006.168.08:13:31.75#ibcon#about to read 6, iclass 31, count 2 2006.168.08:13:31.75#ibcon#read 6, iclass 31, count 2 2006.168.08:13:31.75#ibcon#end of sib2, iclass 31, count 2 2006.168.08:13:31.75#ibcon#*after write, iclass 31, count 2 2006.168.08:13:31.75#ibcon#*before return 0, iclass 31, count 2 2006.168.08:13:31.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.168.08:13:31.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.168.08:13:31.75#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.168.08:13:31.75#ibcon#ireg 7 cls_cnt 0 2006.168.08:13:31.75#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.168.08:13:31.87#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.168.08:13:31.87#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.168.08:13:31.87#ibcon#enter wrdev, iclass 31, count 0 2006.168.08:13:31.87#ibcon#first serial, iclass 31, count 0 2006.168.08:13:31.87#ibcon#enter sib2, iclass 31, count 0 2006.168.08:13:31.87#ibcon#flushed, iclass 31, count 0 2006.168.08:13:31.87#ibcon#about to write, iclass 31, count 0 2006.168.08:13:31.87#ibcon#wrote, iclass 31, count 0 2006.168.08:13:31.87#ibcon#about to read 3, iclass 31, count 0 2006.168.08:13:31.89#ibcon#read 3, iclass 31, count 0 2006.168.08:13:31.89#ibcon#about to read 4, iclass 31, count 0 2006.168.08:13:31.89#ibcon#read 4, iclass 31, count 0 2006.168.08:13:31.89#ibcon#about to read 5, iclass 31, count 0 2006.168.08:13:31.89#ibcon#read 5, iclass 31, count 0 2006.168.08:13:31.89#ibcon#about to read 6, iclass 31, count 0 2006.168.08:13:31.89#ibcon#read 6, iclass 31, count 0 2006.168.08:13:31.89#ibcon#end of sib2, iclass 31, count 0 2006.168.08:13:31.89#ibcon#*mode == 0, iclass 31, count 0 2006.168.08:13:31.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.168.08:13:31.89#ibcon#[27=USB\r\n] 2006.168.08:13:31.89#ibcon#*before write, iclass 31, count 0 2006.168.08:13:31.89#ibcon#enter sib2, iclass 31, count 0 2006.168.08:13:31.89#ibcon#flushed, iclass 31, count 0 2006.168.08:13:31.89#ibcon#about to write, iclass 31, count 0 2006.168.08:13:31.89#ibcon#wrote, iclass 31, count 0 2006.168.08:13:31.89#ibcon#about to read 3, iclass 31, count 0 2006.168.08:13:31.92#ibcon#read 3, iclass 31, count 0 2006.168.08:13:31.92#ibcon#about to read 4, iclass 31, count 0 2006.168.08:13:31.92#ibcon#read 4, iclass 31, count 0 2006.168.08:13:31.92#ibcon#about to read 5, iclass 31, count 0 2006.168.08:13:31.92#ibcon#read 5, iclass 31, count 0 2006.168.08:13:31.92#ibcon#about to read 6, iclass 31, count 0 2006.168.08:13:31.92#ibcon#read 6, iclass 31, count 0 2006.168.08:13:31.92#ibcon#end of sib2, iclass 31, count 0 2006.168.08:13:31.92#ibcon#*after write, iclass 31, count 0 2006.168.08:13:31.92#ibcon#*before return 0, iclass 31, count 0 2006.168.08:13:31.92#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.168.08:13:31.92#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.168.08:13:31.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.168.08:13:31.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.168.08:13:31.92$vc4f8/vblo=5,744.99 2006.168.08:13:31.92#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.168.08:13:31.92#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.168.08:13:31.92#ibcon#ireg 17 cls_cnt 0 2006.168.08:13:31.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:13:31.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:13:31.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:13:31.92#ibcon#enter wrdev, iclass 33, count 0 2006.168.08:13:31.92#ibcon#first serial, iclass 33, count 0 2006.168.08:13:31.92#ibcon#enter sib2, iclass 33, count 0 2006.168.08:13:31.92#ibcon#flushed, iclass 33, count 0 2006.168.08:13:31.92#ibcon#about to write, iclass 33, count 0 2006.168.08:13:31.92#ibcon#wrote, iclass 33, count 0 2006.168.08:13:31.92#ibcon#about to read 3, iclass 33, count 0 2006.168.08:13:31.94#ibcon#read 3, iclass 33, count 0 2006.168.08:13:31.94#ibcon#about to read 4, iclass 33, count 0 2006.168.08:13:31.94#ibcon#read 4, iclass 33, count 0 2006.168.08:13:31.94#ibcon#about to read 5, iclass 33, count 0 2006.168.08:13:31.94#ibcon#read 5, iclass 33, count 0 2006.168.08:13:31.94#ibcon#about to read 6, iclass 33, count 0 2006.168.08:13:31.94#ibcon#read 6, iclass 33, count 0 2006.168.08:13:31.94#ibcon#end of sib2, iclass 33, count 0 2006.168.08:13:31.94#ibcon#*mode == 0, iclass 33, count 0 2006.168.08:13:31.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.168.08:13:31.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.08:13:31.94#ibcon#*before write, iclass 33, count 0 2006.168.08:13:31.94#ibcon#enter sib2, iclass 33, count 0 2006.168.08:13:31.94#ibcon#flushed, iclass 33, count 0 2006.168.08:13:31.94#ibcon#about to write, iclass 33, count 0 2006.168.08:13:31.94#ibcon#wrote, iclass 33, count 0 2006.168.08:13:31.94#ibcon#about to read 3, iclass 33, count 0 2006.168.08:13:31.98#ibcon#read 3, iclass 33, count 0 2006.168.08:13:31.98#ibcon#about to read 4, iclass 33, count 0 2006.168.08:13:31.98#ibcon#read 4, iclass 33, count 0 2006.168.08:13:31.98#ibcon#about to read 5, iclass 33, count 0 2006.168.08:13:31.98#ibcon#read 5, iclass 33, count 0 2006.168.08:13:31.98#ibcon#about to read 6, iclass 33, count 0 2006.168.08:13:31.98#ibcon#read 6, iclass 33, count 0 2006.168.08:13:31.98#ibcon#end of sib2, iclass 33, count 0 2006.168.08:13:31.98#ibcon#*after write, iclass 33, count 0 2006.168.08:13:31.98#ibcon#*before return 0, iclass 33, count 0 2006.168.08:13:31.98#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:13:31.98#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:13:31.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.168.08:13:31.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.168.08:13:31.98$vc4f8/vb=5,4 2006.168.08:13:31.98#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.168.08:13:31.98#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.168.08:13:31.98#ibcon#ireg 11 cls_cnt 2 2006.168.08:13:31.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.168.08:13:32.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.168.08:13:32.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.168.08:13:32.04#ibcon#enter wrdev, iclass 35, count 2 2006.168.08:13:32.04#ibcon#first serial, iclass 35, count 2 2006.168.08:13:32.04#ibcon#enter sib2, iclass 35, count 2 2006.168.08:13:32.04#ibcon#flushed, iclass 35, count 2 2006.168.08:13:32.04#ibcon#about to write, iclass 35, count 2 2006.168.08:13:32.04#ibcon#wrote, iclass 35, count 2 2006.168.08:13:32.04#ibcon#about to read 3, iclass 35, count 2 2006.168.08:13:32.06#ibcon#read 3, iclass 35, count 2 2006.168.08:13:32.06#ibcon#about to read 4, iclass 35, count 2 2006.168.08:13:32.06#ibcon#read 4, iclass 35, count 2 2006.168.08:13:32.06#ibcon#about to read 5, iclass 35, count 2 2006.168.08:13:32.06#ibcon#read 5, iclass 35, count 2 2006.168.08:13:32.06#ibcon#about to read 6, iclass 35, count 2 2006.168.08:13:32.06#ibcon#read 6, iclass 35, count 2 2006.168.08:13:32.06#ibcon#end of sib2, iclass 35, count 2 2006.168.08:13:32.06#ibcon#*mode == 0, iclass 35, count 2 2006.168.08:13:32.06#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.168.08:13:32.06#ibcon#[27=AT05-04\r\n] 2006.168.08:13:32.06#ibcon#*before write, iclass 35, count 2 2006.168.08:13:32.06#ibcon#enter sib2, iclass 35, count 2 2006.168.08:13:32.06#ibcon#flushed, iclass 35, count 2 2006.168.08:13:32.06#ibcon#about to write, iclass 35, count 2 2006.168.08:13:32.06#ibcon#wrote, iclass 35, count 2 2006.168.08:13:32.06#ibcon#about to read 3, iclass 35, count 2 2006.168.08:13:32.09#ibcon#read 3, iclass 35, count 2 2006.168.08:13:32.09#ibcon#about to read 4, iclass 35, count 2 2006.168.08:13:32.09#ibcon#read 4, iclass 35, count 2 2006.168.08:13:32.09#ibcon#about to read 5, iclass 35, count 2 2006.168.08:13:32.09#ibcon#read 5, iclass 35, count 2 2006.168.08:13:32.09#ibcon#about to read 6, iclass 35, count 2 2006.168.08:13:32.09#ibcon#read 6, iclass 35, count 2 2006.168.08:13:32.09#ibcon#end of sib2, iclass 35, count 2 2006.168.08:13:32.09#ibcon#*after write, iclass 35, count 2 2006.168.08:13:32.09#ibcon#*before return 0, iclass 35, count 2 2006.168.08:13:32.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.168.08:13:32.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.168.08:13:32.09#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.168.08:13:32.09#ibcon#ireg 7 cls_cnt 0 2006.168.08:13:32.09#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.168.08:13:32.21#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.168.08:13:32.21#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.168.08:13:32.21#ibcon#enter wrdev, iclass 35, count 0 2006.168.08:13:32.21#ibcon#first serial, iclass 35, count 0 2006.168.08:13:32.21#ibcon#enter sib2, iclass 35, count 0 2006.168.08:13:32.21#ibcon#flushed, iclass 35, count 0 2006.168.08:13:32.21#ibcon#about to write, iclass 35, count 0 2006.168.08:13:32.21#ibcon#wrote, iclass 35, count 0 2006.168.08:13:32.21#ibcon#about to read 3, iclass 35, count 0 2006.168.08:13:32.23#ibcon#read 3, iclass 35, count 0 2006.168.08:13:32.23#ibcon#about to read 4, iclass 35, count 0 2006.168.08:13:32.23#ibcon#read 4, iclass 35, count 0 2006.168.08:13:32.23#ibcon#about to read 5, iclass 35, count 0 2006.168.08:13:32.23#ibcon#read 5, iclass 35, count 0 2006.168.08:13:32.23#ibcon#about to read 6, iclass 35, count 0 2006.168.08:13:32.23#ibcon#read 6, iclass 35, count 0 2006.168.08:13:32.23#ibcon#end of sib2, iclass 35, count 0 2006.168.08:13:32.23#ibcon#*mode == 0, iclass 35, count 0 2006.168.08:13:32.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.168.08:13:32.23#ibcon#[27=USB\r\n] 2006.168.08:13:32.23#ibcon#*before write, iclass 35, count 0 2006.168.08:13:32.23#ibcon#enter sib2, iclass 35, count 0 2006.168.08:13:32.23#ibcon#flushed, iclass 35, count 0 2006.168.08:13:32.23#ibcon#about to write, iclass 35, count 0 2006.168.08:13:32.23#ibcon#wrote, iclass 35, count 0 2006.168.08:13:32.23#ibcon#about to read 3, iclass 35, count 0 2006.168.08:13:32.26#ibcon#read 3, iclass 35, count 0 2006.168.08:13:32.26#ibcon#about to read 4, iclass 35, count 0 2006.168.08:13:32.26#ibcon#read 4, iclass 35, count 0 2006.168.08:13:32.26#ibcon#about to read 5, iclass 35, count 0 2006.168.08:13:32.26#ibcon#read 5, iclass 35, count 0 2006.168.08:13:32.26#ibcon#about to read 6, iclass 35, count 0 2006.168.08:13:32.26#ibcon#read 6, iclass 35, count 0 2006.168.08:13:32.26#ibcon#end of sib2, iclass 35, count 0 2006.168.08:13:32.26#ibcon#*after write, iclass 35, count 0 2006.168.08:13:32.26#ibcon#*before return 0, iclass 35, count 0 2006.168.08:13:32.26#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.168.08:13:32.26#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.168.08:13:32.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.168.08:13:32.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.168.08:13:32.26$vc4f8/vblo=6,752.99 2006.168.08:13:32.26#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.168.08:13:32.26#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.168.08:13:32.26#ibcon#ireg 17 cls_cnt 0 2006.168.08:13:32.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:13:32.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:13:32.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:13:32.26#ibcon#enter wrdev, iclass 37, count 0 2006.168.08:13:32.26#ibcon#first serial, iclass 37, count 0 2006.168.08:13:32.26#ibcon#enter sib2, iclass 37, count 0 2006.168.08:13:32.26#ibcon#flushed, iclass 37, count 0 2006.168.08:13:32.26#ibcon#about to write, iclass 37, count 0 2006.168.08:13:32.26#ibcon#wrote, iclass 37, count 0 2006.168.08:13:32.26#ibcon#about to read 3, iclass 37, count 0 2006.168.08:13:32.28#ibcon#read 3, iclass 37, count 0 2006.168.08:13:32.28#ibcon#about to read 4, iclass 37, count 0 2006.168.08:13:32.28#ibcon#read 4, iclass 37, count 0 2006.168.08:13:32.28#ibcon#about to read 5, iclass 37, count 0 2006.168.08:13:32.28#ibcon#read 5, iclass 37, count 0 2006.168.08:13:32.28#ibcon#about to read 6, iclass 37, count 0 2006.168.08:13:32.28#ibcon#read 6, iclass 37, count 0 2006.168.08:13:32.28#ibcon#end of sib2, iclass 37, count 0 2006.168.08:13:32.28#ibcon#*mode == 0, iclass 37, count 0 2006.168.08:13:32.28#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.168.08:13:32.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.08:13:32.28#ibcon#*before write, iclass 37, count 0 2006.168.08:13:32.28#ibcon#enter sib2, iclass 37, count 0 2006.168.08:13:32.28#ibcon#flushed, iclass 37, count 0 2006.168.08:13:32.28#ibcon#about to write, iclass 37, count 0 2006.168.08:13:32.28#ibcon#wrote, iclass 37, count 0 2006.168.08:13:32.28#ibcon#about to read 3, iclass 37, count 0 2006.168.08:13:32.32#ibcon#read 3, iclass 37, count 0 2006.168.08:13:32.32#ibcon#about to read 4, iclass 37, count 0 2006.168.08:13:32.32#ibcon#read 4, iclass 37, count 0 2006.168.08:13:32.32#ibcon#about to read 5, iclass 37, count 0 2006.168.08:13:32.32#ibcon#read 5, iclass 37, count 0 2006.168.08:13:32.32#ibcon#about to read 6, iclass 37, count 0 2006.168.08:13:32.32#ibcon#read 6, iclass 37, count 0 2006.168.08:13:32.32#ibcon#end of sib2, iclass 37, count 0 2006.168.08:13:32.32#ibcon#*after write, iclass 37, count 0 2006.168.08:13:32.32#ibcon#*before return 0, iclass 37, count 0 2006.168.08:13:32.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:13:32.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:13:32.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.168.08:13:32.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.168.08:13:32.32$vc4f8/vb=6,4 2006.168.08:13:32.32#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.168.08:13:32.32#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.168.08:13:32.32#ibcon#ireg 11 cls_cnt 2 2006.168.08:13:32.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.168.08:13:32.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.168.08:13:32.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.168.08:13:32.38#ibcon#enter wrdev, iclass 39, count 2 2006.168.08:13:32.38#ibcon#first serial, iclass 39, count 2 2006.168.08:13:32.38#ibcon#enter sib2, iclass 39, count 2 2006.168.08:13:32.38#ibcon#flushed, iclass 39, count 2 2006.168.08:13:32.38#ibcon#about to write, iclass 39, count 2 2006.168.08:13:32.38#ibcon#wrote, iclass 39, count 2 2006.168.08:13:32.38#ibcon#about to read 3, iclass 39, count 2 2006.168.08:13:32.40#ibcon#read 3, iclass 39, count 2 2006.168.08:13:32.40#ibcon#about to read 4, iclass 39, count 2 2006.168.08:13:32.40#ibcon#read 4, iclass 39, count 2 2006.168.08:13:32.40#ibcon#about to read 5, iclass 39, count 2 2006.168.08:13:32.40#ibcon#read 5, iclass 39, count 2 2006.168.08:13:32.40#ibcon#about to read 6, iclass 39, count 2 2006.168.08:13:32.40#ibcon#read 6, iclass 39, count 2 2006.168.08:13:32.40#ibcon#end of sib2, iclass 39, count 2 2006.168.08:13:32.40#ibcon#*mode == 0, iclass 39, count 2 2006.168.08:13:32.40#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.168.08:13:32.40#ibcon#[27=AT06-04\r\n] 2006.168.08:13:32.40#ibcon#*before write, iclass 39, count 2 2006.168.08:13:32.40#ibcon#enter sib2, iclass 39, count 2 2006.168.08:13:32.40#ibcon#flushed, iclass 39, count 2 2006.168.08:13:32.40#ibcon#about to write, iclass 39, count 2 2006.168.08:13:32.40#ibcon#wrote, iclass 39, count 2 2006.168.08:13:32.40#ibcon#about to read 3, iclass 39, count 2 2006.168.08:13:32.43#ibcon#read 3, iclass 39, count 2 2006.168.08:13:32.43#ibcon#about to read 4, iclass 39, count 2 2006.168.08:13:32.43#ibcon#read 4, iclass 39, count 2 2006.168.08:13:32.43#ibcon#about to read 5, iclass 39, count 2 2006.168.08:13:32.43#ibcon#read 5, iclass 39, count 2 2006.168.08:13:32.43#ibcon#about to read 6, iclass 39, count 2 2006.168.08:13:32.43#ibcon#read 6, iclass 39, count 2 2006.168.08:13:32.43#ibcon#end of sib2, iclass 39, count 2 2006.168.08:13:32.43#ibcon#*after write, iclass 39, count 2 2006.168.08:13:32.43#ibcon#*before return 0, iclass 39, count 2 2006.168.08:13:32.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.168.08:13:32.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.168.08:13:32.43#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.168.08:13:32.43#ibcon#ireg 7 cls_cnt 0 2006.168.08:13:32.43#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.168.08:13:32.47#abcon#<5=/08 1.4 3.8 26.95 761004.6\r\n> 2006.168.08:13:32.49#abcon#{5=INTERFACE CLEAR} 2006.168.08:13:32.55#abcon#[5=S1D000X0/0*\r\n] 2006.168.08:13:32.55#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.168.08:13:32.55#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.168.08:13:32.55#ibcon#enter wrdev, iclass 39, count 0 2006.168.08:13:32.55#ibcon#first serial, iclass 39, count 0 2006.168.08:13:32.55#ibcon#enter sib2, iclass 39, count 0 2006.168.08:13:32.55#ibcon#flushed, iclass 39, count 0 2006.168.08:13:32.55#ibcon#about to write, iclass 39, count 0 2006.168.08:13:32.55#ibcon#wrote, iclass 39, count 0 2006.168.08:13:32.55#ibcon#about to read 3, iclass 39, count 0 2006.168.08:13:32.57#ibcon#read 3, iclass 39, count 0 2006.168.08:13:32.57#ibcon#about to read 4, iclass 39, count 0 2006.168.08:13:32.57#ibcon#read 4, iclass 39, count 0 2006.168.08:13:32.57#ibcon#about to read 5, iclass 39, count 0 2006.168.08:13:32.57#ibcon#read 5, iclass 39, count 0 2006.168.08:13:32.57#ibcon#about to read 6, iclass 39, count 0 2006.168.08:13:32.57#ibcon#read 6, iclass 39, count 0 2006.168.08:13:32.57#ibcon#end of sib2, iclass 39, count 0 2006.168.08:13:32.57#ibcon#*mode == 0, iclass 39, count 0 2006.168.08:13:32.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.168.08:13:32.57#ibcon#[27=USB\r\n] 2006.168.08:13:32.57#ibcon#*before write, iclass 39, count 0 2006.168.08:13:32.57#ibcon#enter sib2, iclass 39, count 0 2006.168.08:13:32.57#ibcon#flushed, iclass 39, count 0 2006.168.08:13:32.57#ibcon#about to write, iclass 39, count 0 2006.168.08:13:32.57#ibcon#wrote, iclass 39, count 0 2006.168.08:13:32.57#ibcon#about to read 3, iclass 39, count 0 2006.168.08:13:32.60#ibcon#read 3, iclass 39, count 0 2006.168.08:13:32.60#ibcon#about to read 4, iclass 39, count 0 2006.168.08:13:32.60#ibcon#read 4, iclass 39, count 0 2006.168.08:13:32.60#ibcon#about to read 5, iclass 39, count 0 2006.168.08:13:32.60#ibcon#read 5, iclass 39, count 0 2006.168.08:13:32.60#ibcon#about to read 6, iclass 39, count 0 2006.168.08:13:32.60#ibcon#read 6, iclass 39, count 0 2006.168.08:13:32.60#ibcon#end of sib2, iclass 39, count 0 2006.168.08:13:32.60#ibcon#*after write, iclass 39, count 0 2006.168.08:13:32.60#ibcon#*before return 0, iclass 39, count 0 2006.168.08:13:32.60#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.168.08:13:32.60#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.168.08:13:32.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.168.08:13:32.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.168.08:13:32.60$vc4f8/vabw=wide 2006.168.08:13:32.60#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.168.08:13:32.60#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.168.08:13:32.60#ibcon#ireg 8 cls_cnt 0 2006.168.08:13:32.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.168.08:13:32.60#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.168.08:13:32.60#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.168.08:13:32.60#ibcon#enter wrdev, iclass 7, count 0 2006.168.08:13:32.60#ibcon#first serial, iclass 7, count 0 2006.168.08:13:32.60#ibcon#enter sib2, iclass 7, count 0 2006.168.08:13:32.60#ibcon#flushed, iclass 7, count 0 2006.168.08:13:32.60#ibcon#about to write, iclass 7, count 0 2006.168.08:13:32.60#ibcon#wrote, iclass 7, count 0 2006.168.08:13:32.60#ibcon#about to read 3, iclass 7, count 0 2006.168.08:13:32.62#ibcon#read 3, iclass 7, count 0 2006.168.08:13:32.62#ibcon#about to read 4, iclass 7, count 0 2006.168.08:13:32.62#ibcon#read 4, iclass 7, count 0 2006.168.08:13:32.62#ibcon#about to read 5, iclass 7, count 0 2006.168.08:13:32.62#ibcon#read 5, iclass 7, count 0 2006.168.08:13:32.62#ibcon#about to read 6, iclass 7, count 0 2006.168.08:13:32.62#ibcon#read 6, iclass 7, count 0 2006.168.08:13:32.62#ibcon#end of sib2, iclass 7, count 0 2006.168.08:13:32.62#ibcon#*mode == 0, iclass 7, count 0 2006.168.08:13:32.62#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.168.08:13:32.62#ibcon#[25=BW32\r\n] 2006.168.08:13:32.62#ibcon#*before write, iclass 7, count 0 2006.168.08:13:32.62#ibcon#enter sib2, iclass 7, count 0 2006.168.08:13:32.62#ibcon#flushed, iclass 7, count 0 2006.168.08:13:32.62#ibcon#about to write, iclass 7, count 0 2006.168.08:13:32.62#ibcon#wrote, iclass 7, count 0 2006.168.08:13:32.62#ibcon#about to read 3, iclass 7, count 0 2006.168.08:13:32.65#ibcon#read 3, iclass 7, count 0 2006.168.08:13:32.65#ibcon#about to read 4, iclass 7, count 0 2006.168.08:13:32.65#ibcon#read 4, iclass 7, count 0 2006.168.08:13:32.65#ibcon#about to read 5, iclass 7, count 0 2006.168.08:13:32.65#ibcon#read 5, iclass 7, count 0 2006.168.08:13:32.65#ibcon#about to read 6, iclass 7, count 0 2006.168.08:13:32.65#ibcon#read 6, iclass 7, count 0 2006.168.08:13:32.65#ibcon#end of sib2, iclass 7, count 0 2006.168.08:13:32.65#ibcon#*after write, iclass 7, count 0 2006.168.08:13:32.65#ibcon#*before return 0, iclass 7, count 0 2006.168.08:13:32.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.168.08:13:32.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.168.08:13:32.65#ibcon#about to clear, iclass 7 cls_cnt 0 2006.168.08:13:32.65#ibcon#cleared, iclass 7 cls_cnt 0 2006.168.08:13:32.65$vc4f8/vbbw=wide 2006.168.08:13:32.65#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.168.08:13:32.65#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.168.08:13:32.65#ibcon#ireg 8 cls_cnt 0 2006.168.08:13:32.65#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.168.08:13:32.72#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.168.08:13:32.72#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.168.08:13:32.72#ibcon#enter wrdev, iclass 11, count 0 2006.168.08:13:32.72#ibcon#first serial, iclass 11, count 0 2006.168.08:13:32.72#ibcon#enter sib2, iclass 11, count 0 2006.168.08:13:32.72#ibcon#flushed, iclass 11, count 0 2006.168.08:13:32.72#ibcon#about to write, iclass 11, count 0 2006.168.08:13:32.72#ibcon#wrote, iclass 11, count 0 2006.168.08:13:32.72#ibcon#about to read 3, iclass 11, count 0 2006.168.08:13:32.74#ibcon#read 3, iclass 11, count 0 2006.168.08:13:32.74#ibcon#about to read 4, iclass 11, count 0 2006.168.08:13:32.74#ibcon#read 4, iclass 11, count 0 2006.168.08:13:32.74#ibcon#about to read 5, iclass 11, count 0 2006.168.08:13:32.74#ibcon#read 5, iclass 11, count 0 2006.168.08:13:32.74#ibcon#about to read 6, iclass 11, count 0 2006.168.08:13:32.74#ibcon#read 6, iclass 11, count 0 2006.168.08:13:32.74#ibcon#end of sib2, iclass 11, count 0 2006.168.08:13:32.74#ibcon#*mode == 0, iclass 11, count 0 2006.168.08:13:32.74#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.168.08:13:32.74#ibcon#[27=BW32\r\n] 2006.168.08:13:32.74#ibcon#*before write, iclass 11, count 0 2006.168.08:13:32.74#ibcon#enter sib2, iclass 11, count 0 2006.168.08:13:32.74#ibcon#flushed, iclass 11, count 0 2006.168.08:13:32.74#ibcon#about to write, iclass 11, count 0 2006.168.08:13:32.74#ibcon#wrote, iclass 11, count 0 2006.168.08:13:32.74#ibcon#about to read 3, iclass 11, count 0 2006.168.08:13:32.77#ibcon#read 3, iclass 11, count 0 2006.168.08:13:32.77#ibcon#about to read 4, iclass 11, count 0 2006.168.08:13:32.77#ibcon#read 4, iclass 11, count 0 2006.168.08:13:32.77#ibcon#about to read 5, iclass 11, count 0 2006.168.08:13:32.77#ibcon#read 5, iclass 11, count 0 2006.168.08:13:32.77#ibcon#about to read 6, iclass 11, count 0 2006.168.08:13:32.77#ibcon#read 6, iclass 11, count 0 2006.168.08:13:32.77#ibcon#end of sib2, iclass 11, count 0 2006.168.08:13:32.77#ibcon#*after write, iclass 11, count 0 2006.168.08:13:32.77#ibcon#*before return 0, iclass 11, count 0 2006.168.08:13:32.77#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.168.08:13:32.77#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.168.08:13:32.77#ibcon#about to clear, iclass 11 cls_cnt 0 2006.168.08:13:32.77#ibcon#cleared, iclass 11 cls_cnt 0 2006.168.08:13:32.77$4f8m12a/ifd4f 2006.168.08:13:32.77$ifd4f/lo= 2006.168.08:13:32.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.08:13:32.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.08:13:32.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.08:13:32.77$ifd4f/patch= 2006.168.08:13:32.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.08:13:32.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.08:13:32.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.08:13:32.77$4f8m12a/"form=m,16.000,1:2 2006.168.08:13:32.77$4f8m12a/"tpicd 2006.168.08:13:32.77$4f8m12a/echo=off 2006.168.08:13:32.77$4f8m12a/xlog=off 2006.168.08:13:32.77:!2006.168.08:14:00 2006.168.08:13:42.14#trakl#Source acquired 2006.168.08:13:42.14#flagr#flagr/antenna,acquired 2006.168.08:14:00.00:preob 2006.168.08:14:01.14/onsource/TRACKING 2006.168.08:14:01.14:!2006.168.08:14:10 2006.168.08:14:10.00:data_valid=on 2006.168.08:14:10.00:midob 2006.168.08:14:10.14/onsource/TRACKING 2006.168.08:14:10.14/wx/26.94,1004.6,75 2006.168.08:14:10.25/cable/+6.4731E-03 2006.168.08:14:11.34/va/01,08,usb,yes,29,31 2006.168.08:14:11.34/va/02,07,usb,yes,29,31 2006.168.08:14:11.34/va/03,06,usb,yes,31,31 2006.168.08:14:11.34/va/04,07,usb,yes,30,32 2006.168.08:14:11.34/va/05,07,usb,yes,30,32 2006.168.08:14:11.34/va/06,06,usb,yes,29,29 2006.168.08:14:11.34/va/07,06,usb,yes,30,29 2006.168.08:14:11.34/va/08,07,usb,yes,28,28 2006.168.08:14:11.57/valo/01,532.99,yes,locked 2006.168.08:14:11.57/valo/02,572.99,yes,locked 2006.168.08:14:11.57/valo/03,672.99,yes,locked 2006.168.08:14:11.57/valo/04,832.99,yes,locked 2006.168.08:14:11.57/valo/05,652.99,yes,locked 2006.168.08:14:11.57/valo/06,772.99,yes,locked 2006.168.08:14:11.57/valo/07,832.99,yes,locked 2006.168.08:14:11.57/valo/08,852.99,yes,locked 2006.168.08:14:12.66/vb/01,04,usb,yes,29,28 2006.168.08:14:12.66/vb/02,04,usb,yes,31,32 2006.168.08:14:12.66/vb/03,04,usb,yes,27,31 2006.168.08:14:12.66/vb/04,04,usb,yes,28,28 2006.168.08:14:12.66/vb/05,04,usb,yes,27,30 2006.168.08:14:12.66/vb/06,04,usb,yes,27,30 2006.168.08:14:12.66/vb/07,04,usb,yes,29,29 2006.168.08:14:12.66/vb/08,04,usb,yes,27,30 2006.168.08:14:12.89/vblo/01,632.99,yes,locked 2006.168.08:14:12.89/vblo/02,640.99,yes,locked 2006.168.08:14:12.89/vblo/03,656.99,yes,locked 2006.168.08:14:12.89/vblo/04,712.99,yes,locked 2006.168.08:14:12.89/vblo/05,744.99,yes,locked 2006.168.08:14:12.89/vblo/06,752.99,yes,locked 2006.168.08:14:12.89/vblo/07,734.99,yes,locked 2006.168.08:14:12.89/vblo/08,744.99,yes,locked 2006.168.08:14:13.04/vabw/8 2006.168.08:14:13.19/vbbw/8 2006.168.08:14:13.28/xfe/off,on,14.5 2006.168.08:14:13.70/ifatt/23,28,28,28 2006.168.08:14:14.08/fmout-gps/S +4.18E-07 2006.168.08:14:14.16:!2006.168.08:15:10 2006.168.08:15:10.00:data_valid=off 2006.168.08:15:10.00:postob 2006.168.08:15:10.12/cable/+6.4716E-03 2006.168.08:15:10.12/wx/26.94,1004.6,75 2006.168.08:15:11.08/fmout-gps/S +4.17E-07 2006.168.08:15:11.08:scan_name=168-0816,k06168,60 2006.168.08:15:11.09:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.168.08:15:11.14#flagr#flagr/antenna,new-source 2006.168.08:15:12.14:checkk5 2006.168.08:15:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.168.08:15:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.168.08:15:13.29/chk_autoobs//k5ts3/ autoobs is running! 2006.168.08:15:13.66/chk_autoobs//k5ts4/ autoobs is running! 2006.168.08:15:14.03/chk_obsdata//k5ts1/T1680814??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:15:14.41/chk_obsdata//k5ts2/T1680814??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:15:14.77/chk_obsdata//k5ts3/T1680814??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:15:15.15/chk_obsdata//k5ts4/T1680814??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:15:15.84/k5log//k5ts1_log_newline 2006.168.08:15:16.54/k5log//k5ts2_log_newline 2006.168.08:15:17.22/k5log//k5ts3_log_newline 2006.168.08:15:17.94/k5log//k5ts4_log_newline 2006.168.08:15:17.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.08:15:17.96:4f8m12a=2 2006.168.08:15:17.96$4f8m12a/echo=on 2006.168.08:15:17.96$4f8m12a/pcalon 2006.168.08:15:17.96$pcalon/"no phase cal control is implemented here 2006.168.08:15:17.96$4f8m12a/"tpicd=stop 2006.168.08:15:17.96$4f8m12a/vc4f8 2006.168.08:15:17.96$vc4f8/valo=1,532.99 2006.168.08:15:17.96#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.168.08:15:17.96#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.168.08:15:17.96#ibcon#ireg 17 cls_cnt 0 2006.168.08:15:17.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:15:17.96#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:15:17.96#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:15:17.96#ibcon#enter wrdev, iclass 18, count 0 2006.168.08:15:17.96#ibcon#first serial, iclass 18, count 0 2006.168.08:15:17.96#ibcon#enter sib2, iclass 18, count 0 2006.168.08:15:17.96#ibcon#flushed, iclass 18, count 0 2006.168.08:15:17.96#ibcon#about to write, iclass 18, count 0 2006.168.08:15:17.96#ibcon#wrote, iclass 18, count 0 2006.168.08:15:17.96#ibcon#about to read 3, iclass 18, count 0 2006.168.08:15:17.98#ibcon#read 3, iclass 18, count 0 2006.168.08:15:17.98#ibcon#about to read 4, iclass 18, count 0 2006.168.08:15:17.98#ibcon#read 4, iclass 18, count 0 2006.168.08:15:17.98#ibcon#about to read 5, iclass 18, count 0 2006.168.08:15:17.98#ibcon#read 5, iclass 18, count 0 2006.168.08:15:17.98#ibcon#about to read 6, iclass 18, count 0 2006.168.08:15:17.98#ibcon#read 6, iclass 18, count 0 2006.168.08:15:17.98#ibcon#end of sib2, iclass 18, count 0 2006.168.08:15:17.98#ibcon#*mode == 0, iclass 18, count 0 2006.168.08:15:17.98#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.08:15:17.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.08:15:17.98#ibcon#*before write, iclass 18, count 0 2006.168.08:15:17.98#ibcon#enter sib2, iclass 18, count 0 2006.168.08:15:17.98#ibcon#flushed, iclass 18, count 0 2006.168.08:15:17.98#ibcon#about to write, iclass 18, count 0 2006.168.08:15:17.98#ibcon#wrote, iclass 18, count 0 2006.168.08:15:17.98#ibcon#about to read 3, iclass 18, count 0 2006.168.08:15:18.03#ibcon#read 3, iclass 18, count 0 2006.168.08:15:18.03#ibcon#about to read 4, iclass 18, count 0 2006.168.08:15:18.03#ibcon#read 4, iclass 18, count 0 2006.168.08:15:18.03#ibcon#about to read 5, iclass 18, count 0 2006.168.08:15:18.03#ibcon#read 5, iclass 18, count 0 2006.168.08:15:18.03#ibcon#about to read 6, iclass 18, count 0 2006.168.08:15:18.03#ibcon#read 6, iclass 18, count 0 2006.168.08:15:18.03#ibcon#end of sib2, iclass 18, count 0 2006.168.08:15:18.03#ibcon#*after write, iclass 18, count 0 2006.168.08:15:18.03#ibcon#*before return 0, iclass 18, count 0 2006.168.08:15:18.03#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:15:18.03#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:15:18.03#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.08:15:18.03#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.08:15:18.03$vc4f8/va=1,8 2006.168.08:15:18.03#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.168.08:15:18.03#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.168.08:15:18.03#ibcon#ireg 11 cls_cnt 2 2006.168.08:15:18.03#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:15:18.03#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:15:18.03#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:15:18.03#ibcon#enter wrdev, iclass 20, count 2 2006.168.08:15:18.03#ibcon#first serial, iclass 20, count 2 2006.168.08:15:18.03#ibcon#enter sib2, iclass 20, count 2 2006.168.08:15:18.03#ibcon#flushed, iclass 20, count 2 2006.168.08:15:18.03#ibcon#about to write, iclass 20, count 2 2006.168.08:15:18.03#ibcon#wrote, iclass 20, count 2 2006.168.08:15:18.03#ibcon#about to read 3, iclass 20, count 2 2006.168.08:15:18.05#ibcon#read 3, iclass 20, count 2 2006.168.08:15:18.05#ibcon#about to read 4, iclass 20, count 2 2006.168.08:15:18.05#ibcon#read 4, iclass 20, count 2 2006.168.08:15:18.05#ibcon#about to read 5, iclass 20, count 2 2006.168.08:15:18.05#ibcon#read 5, iclass 20, count 2 2006.168.08:15:18.05#ibcon#about to read 6, iclass 20, count 2 2006.168.08:15:18.05#ibcon#read 6, iclass 20, count 2 2006.168.08:15:18.05#ibcon#end of sib2, iclass 20, count 2 2006.168.08:15:18.05#ibcon#*mode == 0, iclass 20, count 2 2006.168.08:15:18.05#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.168.08:15:18.05#ibcon#[25=AT01-08\r\n] 2006.168.08:15:18.05#ibcon#*before write, iclass 20, count 2 2006.168.08:15:18.05#ibcon#enter sib2, iclass 20, count 2 2006.168.08:15:18.05#ibcon#flushed, iclass 20, count 2 2006.168.08:15:18.05#ibcon#about to write, iclass 20, count 2 2006.168.08:15:18.05#ibcon#wrote, iclass 20, count 2 2006.168.08:15:18.05#ibcon#about to read 3, iclass 20, count 2 2006.168.08:15:18.08#ibcon#read 3, iclass 20, count 2 2006.168.08:15:18.08#ibcon#about to read 4, iclass 20, count 2 2006.168.08:15:18.08#ibcon#read 4, iclass 20, count 2 2006.168.08:15:18.08#ibcon#about to read 5, iclass 20, count 2 2006.168.08:15:18.08#ibcon#read 5, iclass 20, count 2 2006.168.08:15:18.08#ibcon#about to read 6, iclass 20, count 2 2006.168.08:15:18.08#ibcon#read 6, iclass 20, count 2 2006.168.08:15:18.08#ibcon#end of sib2, iclass 20, count 2 2006.168.08:15:18.08#ibcon#*after write, iclass 20, count 2 2006.168.08:15:18.08#ibcon#*before return 0, iclass 20, count 2 2006.168.08:15:18.08#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:15:18.08#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:15:18.08#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.168.08:15:18.08#ibcon#ireg 7 cls_cnt 0 2006.168.08:15:18.08#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:15:18.20#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:15:18.20#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:15:18.20#ibcon#enter wrdev, iclass 20, count 0 2006.168.08:15:18.20#ibcon#first serial, iclass 20, count 0 2006.168.08:15:18.20#ibcon#enter sib2, iclass 20, count 0 2006.168.08:15:18.20#ibcon#flushed, iclass 20, count 0 2006.168.08:15:18.20#ibcon#about to write, iclass 20, count 0 2006.168.08:15:18.20#ibcon#wrote, iclass 20, count 0 2006.168.08:15:18.20#ibcon#about to read 3, iclass 20, count 0 2006.168.08:15:18.22#ibcon#read 3, iclass 20, count 0 2006.168.08:15:18.22#ibcon#about to read 4, iclass 20, count 0 2006.168.08:15:18.22#ibcon#read 4, iclass 20, count 0 2006.168.08:15:18.22#ibcon#about to read 5, iclass 20, count 0 2006.168.08:15:18.22#ibcon#read 5, iclass 20, count 0 2006.168.08:15:18.22#ibcon#about to read 6, iclass 20, count 0 2006.168.08:15:18.22#ibcon#read 6, iclass 20, count 0 2006.168.08:15:18.22#ibcon#end of sib2, iclass 20, count 0 2006.168.08:15:18.22#ibcon#*mode == 0, iclass 20, count 0 2006.168.08:15:18.22#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.168.08:15:18.22#ibcon#[25=USB\r\n] 2006.168.08:15:18.22#ibcon#*before write, iclass 20, count 0 2006.168.08:15:18.22#ibcon#enter sib2, iclass 20, count 0 2006.168.08:15:18.22#ibcon#flushed, iclass 20, count 0 2006.168.08:15:18.22#ibcon#about to write, iclass 20, count 0 2006.168.08:15:18.22#ibcon#wrote, iclass 20, count 0 2006.168.08:15:18.22#ibcon#about to read 3, iclass 20, count 0 2006.168.08:15:18.25#ibcon#read 3, iclass 20, count 0 2006.168.08:15:18.25#ibcon#about to read 4, iclass 20, count 0 2006.168.08:15:18.25#ibcon#read 4, iclass 20, count 0 2006.168.08:15:18.25#ibcon#about to read 5, iclass 20, count 0 2006.168.08:15:18.25#ibcon#read 5, iclass 20, count 0 2006.168.08:15:18.25#ibcon#about to read 6, iclass 20, count 0 2006.168.08:15:18.25#ibcon#read 6, iclass 20, count 0 2006.168.08:15:18.25#ibcon#end of sib2, iclass 20, count 0 2006.168.08:15:18.25#ibcon#*after write, iclass 20, count 0 2006.168.08:15:18.25#ibcon#*before return 0, iclass 20, count 0 2006.168.08:15:18.25#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:15:18.25#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:15:18.25#ibcon#about to clear, iclass 20 cls_cnt 0 2006.168.08:15:18.25#ibcon#cleared, iclass 20 cls_cnt 0 2006.168.08:15:18.25$vc4f8/valo=2,572.99 2006.168.08:15:18.25#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.168.08:15:18.25#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.168.08:15:18.25#ibcon#ireg 17 cls_cnt 0 2006.168.08:15:18.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:15:18.25#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:15:18.25#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:15:18.25#ibcon#enter wrdev, iclass 22, count 0 2006.168.08:15:18.25#ibcon#first serial, iclass 22, count 0 2006.168.08:15:18.25#ibcon#enter sib2, iclass 22, count 0 2006.168.08:15:18.25#ibcon#flushed, iclass 22, count 0 2006.168.08:15:18.25#ibcon#about to write, iclass 22, count 0 2006.168.08:15:18.25#ibcon#wrote, iclass 22, count 0 2006.168.08:15:18.25#ibcon#about to read 3, iclass 22, count 0 2006.168.08:15:18.27#ibcon#read 3, iclass 22, count 0 2006.168.08:15:18.27#ibcon#about to read 4, iclass 22, count 0 2006.168.08:15:18.27#ibcon#read 4, iclass 22, count 0 2006.168.08:15:18.27#ibcon#about to read 5, iclass 22, count 0 2006.168.08:15:18.27#ibcon#read 5, iclass 22, count 0 2006.168.08:15:18.27#ibcon#about to read 6, iclass 22, count 0 2006.168.08:15:18.27#ibcon#read 6, iclass 22, count 0 2006.168.08:15:18.27#ibcon#end of sib2, iclass 22, count 0 2006.168.08:15:18.27#ibcon#*mode == 0, iclass 22, count 0 2006.168.08:15:18.27#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.168.08:15:18.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.08:15:18.27#ibcon#*before write, iclass 22, count 0 2006.168.08:15:18.27#ibcon#enter sib2, iclass 22, count 0 2006.168.08:15:18.27#ibcon#flushed, iclass 22, count 0 2006.168.08:15:18.27#ibcon#about to write, iclass 22, count 0 2006.168.08:15:18.27#ibcon#wrote, iclass 22, count 0 2006.168.08:15:18.27#ibcon#about to read 3, iclass 22, count 0 2006.168.08:15:18.31#ibcon#read 3, iclass 22, count 0 2006.168.08:15:18.31#ibcon#about to read 4, iclass 22, count 0 2006.168.08:15:18.31#ibcon#read 4, iclass 22, count 0 2006.168.08:15:18.31#ibcon#about to read 5, iclass 22, count 0 2006.168.08:15:18.31#ibcon#read 5, iclass 22, count 0 2006.168.08:15:18.31#ibcon#about to read 6, iclass 22, count 0 2006.168.08:15:18.31#ibcon#read 6, iclass 22, count 0 2006.168.08:15:18.31#ibcon#end of sib2, iclass 22, count 0 2006.168.08:15:18.31#ibcon#*after write, iclass 22, count 0 2006.168.08:15:18.31#ibcon#*before return 0, iclass 22, count 0 2006.168.08:15:18.31#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:15:18.31#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:15:18.31#ibcon#about to clear, iclass 22 cls_cnt 0 2006.168.08:15:18.31#ibcon#cleared, iclass 22 cls_cnt 0 2006.168.08:15:18.31$vc4f8/va=2,7 2006.168.08:15:18.31#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.168.08:15:18.31#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.168.08:15:18.31#ibcon#ireg 11 cls_cnt 2 2006.168.08:15:18.31#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:15:18.37#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:15:18.37#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:15:18.37#ibcon#enter wrdev, iclass 24, count 2 2006.168.08:15:18.37#ibcon#first serial, iclass 24, count 2 2006.168.08:15:18.37#ibcon#enter sib2, iclass 24, count 2 2006.168.08:15:18.37#ibcon#flushed, iclass 24, count 2 2006.168.08:15:18.37#ibcon#about to write, iclass 24, count 2 2006.168.08:15:18.37#ibcon#wrote, iclass 24, count 2 2006.168.08:15:18.37#ibcon#about to read 3, iclass 24, count 2 2006.168.08:15:18.39#ibcon#read 3, iclass 24, count 2 2006.168.08:15:18.39#ibcon#about to read 4, iclass 24, count 2 2006.168.08:15:18.39#ibcon#read 4, iclass 24, count 2 2006.168.08:15:18.39#ibcon#about to read 5, iclass 24, count 2 2006.168.08:15:18.39#ibcon#read 5, iclass 24, count 2 2006.168.08:15:18.39#ibcon#about to read 6, iclass 24, count 2 2006.168.08:15:18.39#ibcon#read 6, iclass 24, count 2 2006.168.08:15:18.39#ibcon#end of sib2, iclass 24, count 2 2006.168.08:15:18.39#ibcon#*mode == 0, iclass 24, count 2 2006.168.08:15:18.39#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.168.08:15:18.39#ibcon#[25=AT02-07\r\n] 2006.168.08:15:18.39#ibcon#*before write, iclass 24, count 2 2006.168.08:15:18.39#ibcon#enter sib2, iclass 24, count 2 2006.168.08:15:18.39#ibcon#flushed, iclass 24, count 2 2006.168.08:15:18.39#ibcon#about to write, iclass 24, count 2 2006.168.08:15:18.39#ibcon#wrote, iclass 24, count 2 2006.168.08:15:18.39#ibcon#about to read 3, iclass 24, count 2 2006.168.08:15:18.42#ibcon#read 3, iclass 24, count 2 2006.168.08:15:18.42#ibcon#about to read 4, iclass 24, count 2 2006.168.08:15:18.42#ibcon#read 4, iclass 24, count 2 2006.168.08:15:18.42#ibcon#about to read 5, iclass 24, count 2 2006.168.08:15:18.42#ibcon#read 5, iclass 24, count 2 2006.168.08:15:18.42#ibcon#about to read 6, iclass 24, count 2 2006.168.08:15:18.42#ibcon#read 6, iclass 24, count 2 2006.168.08:15:18.42#ibcon#end of sib2, iclass 24, count 2 2006.168.08:15:18.42#ibcon#*after write, iclass 24, count 2 2006.168.08:15:18.42#ibcon#*before return 0, iclass 24, count 2 2006.168.08:15:18.42#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:15:18.42#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:15:18.42#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.168.08:15:18.42#ibcon#ireg 7 cls_cnt 0 2006.168.08:15:18.42#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:15:18.54#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:15:18.54#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:15:18.54#ibcon#enter wrdev, iclass 24, count 0 2006.168.08:15:18.54#ibcon#first serial, iclass 24, count 0 2006.168.08:15:18.54#ibcon#enter sib2, iclass 24, count 0 2006.168.08:15:18.54#ibcon#flushed, iclass 24, count 0 2006.168.08:15:18.54#ibcon#about to write, iclass 24, count 0 2006.168.08:15:18.54#ibcon#wrote, iclass 24, count 0 2006.168.08:15:18.54#ibcon#about to read 3, iclass 24, count 0 2006.168.08:15:18.56#ibcon#read 3, iclass 24, count 0 2006.168.08:15:18.56#ibcon#about to read 4, iclass 24, count 0 2006.168.08:15:18.56#ibcon#read 4, iclass 24, count 0 2006.168.08:15:18.56#ibcon#about to read 5, iclass 24, count 0 2006.168.08:15:18.56#ibcon#read 5, iclass 24, count 0 2006.168.08:15:18.56#ibcon#about to read 6, iclass 24, count 0 2006.168.08:15:18.56#ibcon#read 6, iclass 24, count 0 2006.168.08:15:18.56#ibcon#end of sib2, iclass 24, count 0 2006.168.08:15:18.56#ibcon#*mode == 0, iclass 24, count 0 2006.168.08:15:18.56#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.168.08:15:18.56#ibcon#[25=USB\r\n] 2006.168.08:15:18.56#ibcon#*before write, iclass 24, count 0 2006.168.08:15:18.56#ibcon#enter sib2, iclass 24, count 0 2006.168.08:15:18.56#ibcon#flushed, iclass 24, count 0 2006.168.08:15:18.56#ibcon#about to write, iclass 24, count 0 2006.168.08:15:18.56#ibcon#wrote, iclass 24, count 0 2006.168.08:15:18.56#ibcon#about to read 3, iclass 24, count 0 2006.168.08:15:18.59#ibcon#read 3, iclass 24, count 0 2006.168.08:15:18.59#ibcon#about to read 4, iclass 24, count 0 2006.168.08:15:18.59#ibcon#read 4, iclass 24, count 0 2006.168.08:15:18.59#ibcon#about to read 5, iclass 24, count 0 2006.168.08:15:18.59#ibcon#read 5, iclass 24, count 0 2006.168.08:15:18.59#ibcon#about to read 6, iclass 24, count 0 2006.168.08:15:18.59#ibcon#read 6, iclass 24, count 0 2006.168.08:15:18.59#ibcon#end of sib2, iclass 24, count 0 2006.168.08:15:18.59#ibcon#*after write, iclass 24, count 0 2006.168.08:15:18.59#ibcon#*before return 0, iclass 24, count 0 2006.168.08:15:18.59#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:15:18.59#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:15:18.59#ibcon#about to clear, iclass 24 cls_cnt 0 2006.168.08:15:18.59#ibcon#cleared, iclass 24 cls_cnt 0 2006.168.08:15:18.59$vc4f8/valo=3,672.99 2006.168.08:15:18.59#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.168.08:15:18.59#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.168.08:15:18.59#ibcon#ireg 17 cls_cnt 0 2006.168.08:15:18.59#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:15:18.59#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:15:18.59#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:15:18.59#ibcon#enter wrdev, iclass 26, count 0 2006.168.08:15:18.59#ibcon#first serial, iclass 26, count 0 2006.168.08:15:18.59#ibcon#enter sib2, iclass 26, count 0 2006.168.08:15:18.59#ibcon#flushed, iclass 26, count 0 2006.168.08:15:18.59#ibcon#about to write, iclass 26, count 0 2006.168.08:15:18.59#ibcon#wrote, iclass 26, count 0 2006.168.08:15:18.59#ibcon#about to read 3, iclass 26, count 0 2006.168.08:15:18.61#ibcon#read 3, iclass 26, count 0 2006.168.08:15:18.61#ibcon#about to read 4, iclass 26, count 0 2006.168.08:15:18.61#ibcon#read 4, iclass 26, count 0 2006.168.08:15:18.61#ibcon#about to read 5, iclass 26, count 0 2006.168.08:15:18.61#ibcon#read 5, iclass 26, count 0 2006.168.08:15:18.61#ibcon#about to read 6, iclass 26, count 0 2006.168.08:15:18.61#ibcon#read 6, iclass 26, count 0 2006.168.08:15:18.61#ibcon#end of sib2, iclass 26, count 0 2006.168.08:15:18.61#ibcon#*mode == 0, iclass 26, count 0 2006.168.08:15:18.61#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.168.08:15:18.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.08:15:18.61#ibcon#*before write, iclass 26, count 0 2006.168.08:15:18.61#ibcon#enter sib2, iclass 26, count 0 2006.168.08:15:18.61#ibcon#flushed, iclass 26, count 0 2006.168.08:15:18.61#ibcon#about to write, iclass 26, count 0 2006.168.08:15:18.61#ibcon#wrote, iclass 26, count 0 2006.168.08:15:18.61#ibcon#about to read 3, iclass 26, count 0 2006.168.08:15:18.65#ibcon#read 3, iclass 26, count 0 2006.168.08:15:18.65#ibcon#about to read 4, iclass 26, count 0 2006.168.08:15:18.65#ibcon#read 4, iclass 26, count 0 2006.168.08:15:18.65#ibcon#about to read 5, iclass 26, count 0 2006.168.08:15:18.65#ibcon#read 5, iclass 26, count 0 2006.168.08:15:18.65#ibcon#about to read 6, iclass 26, count 0 2006.168.08:15:18.65#ibcon#read 6, iclass 26, count 0 2006.168.08:15:18.65#ibcon#end of sib2, iclass 26, count 0 2006.168.08:15:18.65#ibcon#*after write, iclass 26, count 0 2006.168.08:15:18.65#ibcon#*before return 0, iclass 26, count 0 2006.168.08:15:18.65#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:15:18.65#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:15:18.65#ibcon#about to clear, iclass 26 cls_cnt 0 2006.168.08:15:18.65#ibcon#cleared, iclass 26 cls_cnt 0 2006.168.08:15:18.65$vc4f8/va=3,6 2006.168.08:15:18.65#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.168.08:15:18.65#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.168.08:15:18.65#ibcon#ireg 11 cls_cnt 2 2006.168.08:15:18.65#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:15:18.71#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:15:18.71#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:15:18.71#ibcon#enter wrdev, iclass 28, count 2 2006.168.08:15:18.71#ibcon#first serial, iclass 28, count 2 2006.168.08:15:18.71#ibcon#enter sib2, iclass 28, count 2 2006.168.08:15:18.71#ibcon#flushed, iclass 28, count 2 2006.168.08:15:18.71#ibcon#about to write, iclass 28, count 2 2006.168.08:15:18.71#ibcon#wrote, iclass 28, count 2 2006.168.08:15:18.71#ibcon#about to read 3, iclass 28, count 2 2006.168.08:15:18.73#ibcon#read 3, iclass 28, count 2 2006.168.08:15:18.73#ibcon#about to read 4, iclass 28, count 2 2006.168.08:15:18.73#ibcon#read 4, iclass 28, count 2 2006.168.08:15:18.73#ibcon#about to read 5, iclass 28, count 2 2006.168.08:15:18.73#ibcon#read 5, iclass 28, count 2 2006.168.08:15:18.73#ibcon#about to read 6, iclass 28, count 2 2006.168.08:15:18.73#ibcon#read 6, iclass 28, count 2 2006.168.08:15:18.73#ibcon#end of sib2, iclass 28, count 2 2006.168.08:15:18.73#ibcon#*mode == 0, iclass 28, count 2 2006.168.08:15:18.73#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.168.08:15:18.73#ibcon#[25=AT03-06\r\n] 2006.168.08:15:18.73#ibcon#*before write, iclass 28, count 2 2006.168.08:15:18.73#ibcon#enter sib2, iclass 28, count 2 2006.168.08:15:18.73#ibcon#flushed, iclass 28, count 2 2006.168.08:15:18.73#ibcon#about to write, iclass 28, count 2 2006.168.08:15:18.73#ibcon#wrote, iclass 28, count 2 2006.168.08:15:18.73#ibcon#about to read 3, iclass 28, count 2 2006.168.08:15:18.76#ibcon#read 3, iclass 28, count 2 2006.168.08:15:18.76#ibcon#about to read 4, iclass 28, count 2 2006.168.08:15:18.76#ibcon#read 4, iclass 28, count 2 2006.168.08:15:18.76#ibcon#about to read 5, iclass 28, count 2 2006.168.08:15:18.76#ibcon#read 5, iclass 28, count 2 2006.168.08:15:18.76#ibcon#about to read 6, iclass 28, count 2 2006.168.08:15:18.76#ibcon#read 6, iclass 28, count 2 2006.168.08:15:18.76#ibcon#end of sib2, iclass 28, count 2 2006.168.08:15:18.76#ibcon#*after write, iclass 28, count 2 2006.168.08:15:18.76#ibcon#*before return 0, iclass 28, count 2 2006.168.08:15:18.76#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:15:18.76#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:15:18.76#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.168.08:15:18.76#ibcon#ireg 7 cls_cnt 0 2006.168.08:15:18.76#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:15:18.88#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:15:18.88#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:15:18.88#ibcon#enter wrdev, iclass 28, count 0 2006.168.08:15:18.88#ibcon#first serial, iclass 28, count 0 2006.168.08:15:18.88#ibcon#enter sib2, iclass 28, count 0 2006.168.08:15:18.88#ibcon#flushed, iclass 28, count 0 2006.168.08:15:18.88#ibcon#about to write, iclass 28, count 0 2006.168.08:15:18.88#ibcon#wrote, iclass 28, count 0 2006.168.08:15:18.88#ibcon#about to read 3, iclass 28, count 0 2006.168.08:15:18.90#ibcon#read 3, iclass 28, count 0 2006.168.08:15:18.90#ibcon#about to read 4, iclass 28, count 0 2006.168.08:15:18.90#ibcon#read 4, iclass 28, count 0 2006.168.08:15:18.90#ibcon#about to read 5, iclass 28, count 0 2006.168.08:15:18.90#ibcon#read 5, iclass 28, count 0 2006.168.08:15:18.90#ibcon#about to read 6, iclass 28, count 0 2006.168.08:15:18.90#ibcon#read 6, iclass 28, count 0 2006.168.08:15:18.90#ibcon#end of sib2, iclass 28, count 0 2006.168.08:15:18.90#ibcon#*mode == 0, iclass 28, count 0 2006.168.08:15:18.90#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.168.08:15:18.90#ibcon#[25=USB\r\n] 2006.168.08:15:18.90#ibcon#*before write, iclass 28, count 0 2006.168.08:15:18.90#ibcon#enter sib2, iclass 28, count 0 2006.168.08:15:18.90#ibcon#flushed, iclass 28, count 0 2006.168.08:15:18.90#ibcon#about to write, iclass 28, count 0 2006.168.08:15:18.90#ibcon#wrote, iclass 28, count 0 2006.168.08:15:18.90#ibcon#about to read 3, iclass 28, count 0 2006.168.08:15:18.93#ibcon#read 3, iclass 28, count 0 2006.168.08:15:18.93#ibcon#about to read 4, iclass 28, count 0 2006.168.08:15:18.93#ibcon#read 4, iclass 28, count 0 2006.168.08:15:18.93#ibcon#about to read 5, iclass 28, count 0 2006.168.08:15:18.93#ibcon#read 5, iclass 28, count 0 2006.168.08:15:18.93#ibcon#about to read 6, iclass 28, count 0 2006.168.08:15:18.93#ibcon#read 6, iclass 28, count 0 2006.168.08:15:18.93#ibcon#end of sib2, iclass 28, count 0 2006.168.08:15:18.93#ibcon#*after write, iclass 28, count 0 2006.168.08:15:18.93#ibcon#*before return 0, iclass 28, count 0 2006.168.08:15:18.93#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:15:18.93#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:15:18.93#ibcon#about to clear, iclass 28 cls_cnt 0 2006.168.08:15:18.93#ibcon#cleared, iclass 28 cls_cnt 0 2006.168.08:15:18.93$vc4f8/valo=4,832.99 2006.168.08:15:18.93#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.168.08:15:18.93#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.168.08:15:18.93#ibcon#ireg 17 cls_cnt 0 2006.168.08:15:18.93#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:15:18.93#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:15:18.93#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:15:18.93#ibcon#enter wrdev, iclass 30, count 0 2006.168.08:15:18.93#ibcon#first serial, iclass 30, count 0 2006.168.08:15:18.93#ibcon#enter sib2, iclass 30, count 0 2006.168.08:15:18.93#ibcon#flushed, iclass 30, count 0 2006.168.08:15:18.93#ibcon#about to write, iclass 30, count 0 2006.168.08:15:18.93#ibcon#wrote, iclass 30, count 0 2006.168.08:15:18.93#ibcon#about to read 3, iclass 30, count 0 2006.168.08:15:18.95#ibcon#read 3, iclass 30, count 0 2006.168.08:15:18.95#ibcon#about to read 4, iclass 30, count 0 2006.168.08:15:18.95#ibcon#read 4, iclass 30, count 0 2006.168.08:15:18.95#ibcon#about to read 5, iclass 30, count 0 2006.168.08:15:18.95#ibcon#read 5, iclass 30, count 0 2006.168.08:15:18.95#ibcon#about to read 6, iclass 30, count 0 2006.168.08:15:18.95#ibcon#read 6, iclass 30, count 0 2006.168.08:15:18.95#ibcon#end of sib2, iclass 30, count 0 2006.168.08:15:18.95#ibcon#*mode == 0, iclass 30, count 0 2006.168.08:15:18.95#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.168.08:15:18.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.08:15:18.95#ibcon#*before write, iclass 30, count 0 2006.168.08:15:18.95#ibcon#enter sib2, iclass 30, count 0 2006.168.08:15:18.95#ibcon#flushed, iclass 30, count 0 2006.168.08:15:18.95#ibcon#about to write, iclass 30, count 0 2006.168.08:15:18.95#ibcon#wrote, iclass 30, count 0 2006.168.08:15:18.95#ibcon#about to read 3, iclass 30, count 0 2006.168.08:15:18.99#ibcon#read 3, iclass 30, count 0 2006.168.08:15:18.99#ibcon#about to read 4, iclass 30, count 0 2006.168.08:15:18.99#ibcon#read 4, iclass 30, count 0 2006.168.08:15:18.99#ibcon#about to read 5, iclass 30, count 0 2006.168.08:15:18.99#ibcon#read 5, iclass 30, count 0 2006.168.08:15:18.99#ibcon#about to read 6, iclass 30, count 0 2006.168.08:15:18.99#ibcon#read 6, iclass 30, count 0 2006.168.08:15:18.99#ibcon#end of sib2, iclass 30, count 0 2006.168.08:15:18.99#ibcon#*after write, iclass 30, count 0 2006.168.08:15:18.99#ibcon#*before return 0, iclass 30, count 0 2006.168.08:15:18.99#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:15:18.99#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:15:18.99#ibcon#about to clear, iclass 30 cls_cnt 0 2006.168.08:15:18.99#ibcon#cleared, iclass 30 cls_cnt 0 2006.168.08:15:18.99$vc4f8/va=4,7 2006.168.08:15:18.99#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.168.08:15:18.99#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.168.08:15:18.99#ibcon#ireg 11 cls_cnt 2 2006.168.08:15:18.99#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:15:19.05#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:15:19.05#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:15:19.05#ibcon#enter wrdev, iclass 32, count 2 2006.168.08:15:19.05#ibcon#first serial, iclass 32, count 2 2006.168.08:15:19.05#ibcon#enter sib2, iclass 32, count 2 2006.168.08:15:19.05#ibcon#flushed, iclass 32, count 2 2006.168.08:15:19.05#ibcon#about to write, iclass 32, count 2 2006.168.08:15:19.05#ibcon#wrote, iclass 32, count 2 2006.168.08:15:19.05#ibcon#about to read 3, iclass 32, count 2 2006.168.08:15:19.07#ibcon#read 3, iclass 32, count 2 2006.168.08:15:19.07#ibcon#about to read 4, iclass 32, count 2 2006.168.08:15:19.07#ibcon#read 4, iclass 32, count 2 2006.168.08:15:19.07#ibcon#about to read 5, iclass 32, count 2 2006.168.08:15:19.07#ibcon#read 5, iclass 32, count 2 2006.168.08:15:19.07#ibcon#about to read 6, iclass 32, count 2 2006.168.08:15:19.07#ibcon#read 6, iclass 32, count 2 2006.168.08:15:19.07#ibcon#end of sib2, iclass 32, count 2 2006.168.08:15:19.07#ibcon#*mode == 0, iclass 32, count 2 2006.168.08:15:19.07#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.168.08:15:19.07#ibcon#[25=AT04-07\r\n] 2006.168.08:15:19.07#ibcon#*before write, iclass 32, count 2 2006.168.08:15:19.07#ibcon#enter sib2, iclass 32, count 2 2006.168.08:15:19.07#ibcon#flushed, iclass 32, count 2 2006.168.08:15:19.07#ibcon#about to write, iclass 32, count 2 2006.168.08:15:19.07#ibcon#wrote, iclass 32, count 2 2006.168.08:15:19.07#ibcon#about to read 3, iclass 32, count 2 2006.168.08:15:19.10#ibcon#read 3, iclass 32, count 2 2006.168.08:15:19.10#ibcon#about to read 4, iclass 32, count 2 2006.168.08:15:19.10#ibcon#read 4, iclass 32, count 2 2006.168.08:15:19.10#ibcon#about to read 5, iclass 32, count 2 2006.168.08:15:19.10#ibcon#read 5, iclass 32, count 2 2006.168.08:15:19.10#ibcon#about to read 6, iclass 32, count 2 2006.168.08:15:19.10#ibcon#read 6, iclass 32, count 2 2006.168.08:15:19.10#ibcon#end of sib2, iclass 32, count 2 2006.168.08:15:19.10#ibcon#*after write, iclass 32, count 2 2006.168.08:15:19.10#ibcon#*before return 0, iclass 32, count 2 2006.168.08:15:19.10#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:15:19.10#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:15:19.10#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.168.08:15:19.10#ibcon#ireg 7 cls_cnt 0 2006.168.08:15:19.10#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:15:19.22#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:15:19.22#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:15:19.22#ibcon#enter wrdev, iclass 32, count 0 2006.168.08:15:19.22#ibcon#first serial, iclass 32, count 0 2006.168.08:15:19.22#ibcon#enter sib2, iclass 32, count 0 2006.168.08:15:19.22#ibcon#flushed, iclass 32, count 0 2006.168.08:15:19.22#ibcon#about to write, iclass 32, count 0 2006.168.08:15:19.22#ibcon#wrote, iclass 32, count 0 2006.168.08:15:19.22#ibcon#about to read 3, iclass 32, count 0 2006.168.08:15:19.24#ibcon#read 3, iclass 32, count 0 2006.168.08:15:19.24#ibcon#about to read 4, iclass 32, count 0 2006.168.08:15:19.24#ibcon#read 4, iclass 32, count 0 2006.168.08:15:19.24#ibcon#about to read 5, iclass 32, count 0 2006.168.08:15:19.24#ibcon#read 5, iclass 32, count 0 2006.168.08:15:19.24#ibcon#about to read 6, iclass 32, count 0 2006.168.08:15:19.24#ibcon#read 6, iclass 32, count 0 2006.168.08:15:19.24#ibcon#end of sib2, iclass 32, count 0 2006.168.08:15:19.24#ibcon#*mode == 0, iclass 32, count 0 2006.168.08:15:19.24#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.168.08:15:19.24#ibcon#[25=USB\r\n] 2006.168.08:15:19.24#ibcon#*before write, iclass 32, count 0 2006.168.08:15:19.24#ibcon#enter sib2, iclass 32, count 0 2006.168.08:15:19.24#ibcon#flushed, iclass 32, count 0 2006.168.08:15:19.24#ibcon#about to write, iclass 32, count 0 2006.168.08:15:19.24#ibcon#wrote, iclass 32, count 0 2006.168.08:15:19.24#ibcon#about to read 3, iclass 32, count 0 2006.168.08:15:19.27#ibcon#read 3, iclass 32, count 0 2006.168.08:15:19.27#ibcon#about to read 4, iclass 32, count 0 2006.168.08:15:19.27#ibcon#read 4, iclass 32, count 0 2006.168.08:15:19.27#ibcon#about to read 5, iclass 32, count 0 2006.168.08:15:19.27#ibcon#read 5, iclass 32, count 0 2006.168.08:15:19.27#ibcon#about to read 6, iclass 32, count 0 2006.168.08:15:19.27#ibcon#read 6, iclass 32, count 0 2006.168.08:15:19.27#ibcon#end of sib2, iclass 32, count 0 2006.168.08:15:19.27#ibcon#*after write, iclass 32, count 0 2006.168.08:15:19.27#ibcon#*before return 0, iclass 32, count 0 2006.168.08:15:19.27#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:15:19.27#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:15:19.27#ibcon#about to clear, iclass 32 cls_cnt 0 2006.168.08:15:19.27#ibcon#cleared, iclass 32 cls_cnt 0 2006.168.08:15:19.27$vc4f8/valo=5,652.99 2006.168.08:15:19.27#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.168.08:15:19.27#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.168.08:15:19.27#ibcon#ireg 17 cls_cnt 0 2006.168.08:15:19.27#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:15:19.27#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:15:19.27#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:15:19.27#ibcon#enter wrdev, iclass 34, count 0 2006.168.08:15:19.27#ibcon#first serial, iclass 34, count 0 2006.168.08:15:19.27#ibcon#enter sib2, iclass 34, count 0 2006.168.08:15:19.27#ibcon#flushed, iclass 34, count 0 2006.168.08:15:19.27#ibcon#about to write, iclass 34, count 0 2006.168.08:15:19.27#ibcon#wrote, iclass 34, count 0 2006.168.08:15:19.27#ibcon#about to read 3, iclass 34, count 0 2006.168.08:15:19.29#ibcon#read 3, iclass 34, count 0 2006.168.08:15:19.29#ibcon#about to read 4, iclass 34, count 0 2006.168.08:15:19.29#ibcon#read 4, iclass 34, count 0 2006.168.08:15:19.29#ibcon#about to read 5, iclass 34, count 0 2006.168.08:15:19.29#ibcon#read 5, iclass 34, count 0 2006.168.08:15:19.29#ibcon#about to read 6, iclass 34, count 0 2006.168.08:15:19.29#ibcon#read 6, iclass 34, count 0 2006.168.08:15:19.29#ibcon#end of sib2, iclass 34, count 0 2006.168.08:15:19.29#ibcon#*mode == 0, iclass 34, count 0 2006.168.08:15:19.29#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.168.08:15:19.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.08:15:19.29#ibcon#*before write, iclass 34, count 0 2006.168.08:15:19.29#ibcon#enter sib2, iclass 34, count 0 2006.168.08:15:19.29#ibcon#flushed, iclass 34, count 0 2006.168.08:15:19.29#ibcon#about to write, iclass 34, count 0 2006.168.08:15:19.29#ibcon#wrote, iclass 34, count 0 2006.168.08:15:19.29#ibcon#about to read 3, iclass 34, count 0 2006.168.08:15:19.33#ibcon#read 3, iclass 34, count 0 2006.168.08:15:19.33#ibcon#about to read 4, iclass 34, count 0 2006.168.08:15:19.33#ibcon#read 4, iclass 34, count 0 2006.168.08:15:19.33#ibcon#about to read 5, iclass 34, count 0 2006.168.08:15:19.33#ibcon#read 5, iclass 34, count 0 2006.168.08:15:19.33#ibcon#about to read 6, iclass 34, count 0 2006.168.08:15:19.33#ibcon#read 6, iclass 34, count 0 2006.168.08:15:19.33#ibcon#end of sib2, iclass 34, count 0 2006.168.08:15:19.33#ibcon#*after write, iclass 34, count 0 2006.168.08:15:19.33#ibcon#*before return 0, iclass 34, count 0 2006.168.08:15:19.33#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:15:19.33#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:15:19.33#ibcon#about to clear, iclass 34 cls_cnt 0 2006.168.08:15:19.33#ibcon#cleared, iclass 34 cls_cnt 0 2006.168.08:15:19.33$vc4f8/va=5,7 2006.168.08:15:19.33#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.168.08:15:19.33#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.168.08:15:19.33#ibcon#ireg 11 cls_cnt 2 2006.168.08:15:19.33#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:15:19.39#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:15:19.39#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:15:19.39#ibcon#enter wrdev, iclass 36, count 2 2006.168.08:15:19.39#ibcon#first serial, iclass 36, count 2 2006.168.08:15:19.39#ibcon#enter sib2, iclass 36, count 2 2006.168.08:15:19.39#ibcon#flushed, iclass 36, count 2 2006.168.08:15:19.39#ibcon#about to write, iclass 36, count 2 2006.168.08:15:19.39#ibcon#wrote, iclass 36, count 2 2006.168.08:15:19.39#ibcon#about to read 3, iclass 36, count 2 2006.168.08:15:19.41#ibcon#read 3, iclass 36, count 2 2006.168.08:15:19.41#ibcon#about to read 4, iclass 36, count 2 2006.168.08:15:19.41#ibcon#read 4, iclass 36, count 2 2006.168.08:15:19.41#ibcon#about to read 5, iclass 36, count 2 2006.168.08:15:19.41#ibcon#read 5, iclass 36, count 2 2006.168.08:15:19.41#ibcon#about to read 6, iclass 36, count 2 2006.168.08:15:19.41#ibcon#read 6, iclass 36, count 2 2006.168.08:15:19.41#ibcon#end of sib2, iclass 36, count 2 2006.168.08:15:19.41#ibcon#*mode == 0, iclass 36, count 2 2006.168.08:15:19.41#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.168.08:15:19.41#ibcon#[25=AT05-07\r\n] 2006.168.08:15:19.41#ibcon#*before write, iclass 36, count 2 2006.168.08:15:19.41#ibcon#enter sib2, iclass 36, count 2 2006.168.08:15:19.41#ibcon#flushed, iclass 36, count 2 2006.168.08:15:19.41#ibcon#about to write, iclass 36, count 2 2006.168.08:15:19.41#ibcon#wrote, iclass 36, count 2 2006.168.08:15:19.41#ibcon#about to read 3, iclass 36, count 2 2006.168.08:15:19.44#ibcon#read 3, iclass 36, count 2 2006.168.08:15:19.44#ibcon#about to read 4, iclass 36, count 2 2006.168.08:15:19.44#ibcon#read 4, iclass 36, count 2 2006.168.08:15:19.44#ibcon#about to read 5, iclass 36, count 2 2006.168.08:15:19.44#ibcon#read 5, iclass 36, count 2 2006.168.08:15:19.44#ibcon#about to read 6, iclass 36, count 2 2006.168.08:15:19.44#ibcon#read 6, iclass 36, count 2 2006.168.08:15:19.44#ibcon#end of sib2, iclass 36, count 2 2006.168.08:15:19.44#ibcon#*after write, iclass 36, count 2 2006.168.08:15:19.44#ibcon#*before return 0, iclass 36, count 2 2006.168.08:15:19.44#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:15:19.44#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:15:19.44#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.168.08:15:19.44#ibcon#ireg 7 cls_cnt 0 2006.168.08:15:19.44#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:15:19.56#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:15:19.56#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:15:19.56#ibcon#enter wrdev, iclass 36, count 0 2006.168.08:15:19.56#ibcon#first serial, iclass 36, count 0 2006.168.08:15:19.56#ibcon#enter sib2, iclass 36, count 0 2006.168.08:15:19.56#ibcon#flushed, iclass 36, count 0 2006.168.08:15:19.56#ibcon#about to write, iclass 36, count 0 2006.168.08:15:19.56#ibcon#wrote, iclass 36, count 0 2006.168.08:15:19.56#ibcon#about to read 3, iclass 36, count 0 2006.168.08:15:19.58#ibcon#read 3, iclass 36, count 0 2006.168.08:15:19.58#ibcon#about to read 4, iclass 36, count 0 2006.168.08:15:19.58#ibcon#read 4, iclass 36, count 0 2006.168.08:15:19.58#ibcon#about to read 5, iclass 36, count 0 2006.168.08:15:19.58#ibcon#read 5, iclass 36, count 0 2006.168.08:15:19.58#ibcon#about to read 6, iclass 36, count 0 2006.168.08:15:19.58#ibcon#read 6, iclass 36, count 0 2006.168.08:15:19.58#ibcon#end of sib2, iclass 36, count 0 2006.168.08:15:19.58#ibcon#*mode == 0, iclass 36, count 0 2006.168.08:15:19.58#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.168.08:15:19.58#ibcon#[25=USB\r\n] 2006.168.08:15:19.58#ibcon#*before write, iclass 36, count 0 2006.168.08:15:19.58#ibcon#enter sib2, iclass 36, count 0 2006.168.08:15:19.58#ibcon#flushed, iclass 36, count 0 2006.168.08:15:19.58#ibcon#about to write, iclass 36, count 0 2006.168.08:15:19.58#ibcon#wrote, iclass 36, count 0 2006.168.08:15:19.58#ibcon#about to read 3, iclass 36, count 0 2006.168.08:15:19.61#ibcon#read 3, iclass 36, count 0 2006.168.08:15:19.61#ibcon#about to read 4, iclass 36, count 0 2006.168.08:15:19.61#ibcon#read 4, iclass 36, count 0 2006.168.08:15:19.61#ibcon#about to read 5, iclass 36, count 0 2006.168.08:15:19.61#ibcon#read 5, iclass 36, count 0 2006.168.08:15:19.61#ibcon#about to read 6, iclass 36, count 0 2006.168.08:15:19.61#ibcon#read 6, iclass 36, count 0 2006.168.08:15:19.61#ibcon#end of sib2, iclass 36, count 0 2006.168.08:15:19.61#ibcon#*after write, iclass 36, count 0 2006.168.08:15:19.61#ibcon#*before return 0, iclass 36, count 0 2006.168.08:15:19.61#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:15:19.61#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:15:19.61#ibcon#about to clear, iclass 36 cls_cnt 0 2006.168.08:15:19.61#ibcon#cleared, iclass 36 cls_cnt 0 2006.168.08:15:19.61$vc4f8/valo=6,772.99 2006.168.08:15:19.61#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.168.08:15:19.61#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.168.08:15:19.61#ibcon#ireg 17 cls_cnt 0 2006.168.08:15:19.61#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:15:19.61#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:15:19.61#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:15:19.61#ibcon#enter wrdev, iclass 38, count 0 2006.168.08:15:19.61#ibcon#first serial, iclass 38, count 0 2006.168.08:15:19.61#ibcon#enter sib2, iclass 38, count 0 2006.168.08:15:19.61#ibcon#flushed, iclass 38, count 0 2006.168.08:15:19.61#ibcon#about to write, iclass 38, count 0 2006.168.08:15:19.61#ibcon#wrote, iclass 38, count 0 2006.168.08:15:19.61#ibcon#about to read 3, iclass 38, count 0 2006.168.08:15:19.63#ibcon#read 3, iclass 38, count 0 2006.168.08:15:19.63#ibcon#about to read 4, iclass 38, count 0 2006.168.08:15:19.63#ibcon#read 4, iclass 38, count 0 2006.168.08:15:19.63#ibcon#about to read 5, iclass 38, count 0 2006.168.08:15:19.63#ibcon#read 5, iclass 38, count 0 2006.168.08:15:19.63#ibcon#about to read 6, iclass 38, count 0 2006.168.08:15:19.63#ibcon#read 6, iclass 38, count 0 2006.168.08:15:19.63#ibcon#end of sib2, iclass 38, count 0 2006.168.08:15:19.63#ibcon#*mode == 0, iclass 38, count 0 2006.168.08:15:19.63#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.168.08:15:19.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.08:15:19.63#ibcon#*before write, iclass 38, count 0 2006.168.08:15:19.63#ibcon#enter sib2, iclass 38, count 0 2006.168.08:15:19.63#ibcon#flushed, iclass 38, count 0 2006.168.08:15:19.63#ibcon#about to write, iclass 38, count 0 2006.168.08:15:19.63#ibcon#wrote, iclass 38, count 0 2006.168.08:15:19.63#ibcon#about to read 3, iclass 38, count 0 2006.168.08:15:19.67#ibcon#read 3, iclass 38, count 0 2006.168.08:15:19.67#ibcon#about to read 4, iclass 38, count 0 2006.168.08:15:19.67#ibcon#read 4, iclass 38, count 0 2006.168.08:15:19.67#ibcon#about to read 5, iclass 38, count 0 2006.168.08:15:19.67#ibcon#read 5, iclass 38, count 0 2006.168.08:15:19.67#ibcon#about to read 6, iclass 38, count 0 2006.168.08:15:19.67#ibcon#read 6, iclass 38, count 0 2006.168.08:15:19.67#ibcon#end of sib2, iclass 38, count 0 2006.168.08:15:19.67#ibcon#*after write, iclass 38, count 0 2006.168.08:15:19.67#ibcon#*before return 0, iclass 38, count 0 2006.168.08:15:19.67#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:15:19.67#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:15:19.67#ibcon#about to clear, iclass 38 cls_cnt 0 2006.168.08:15:19.67#ibcon#cleared, iclass 38 cls_cnt 0 2006.168.08:15:19.67$vc4f8/va=6,6 2006.168.08:15:19.67#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.168.08:15:19.67#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.168.08:15:19.67#ibcon#ireg 11 cls_cnt 2 2006.168.08:15:19.67#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:15:19.73#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:15:19.73#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:15:19.73#ibcon#enter wrdev, iclass 40, count 2 2006.168.08:15:19.73#ibcon#first serial, iclass 40, count 2 2006.168.08:15:19.73#ibcon#enter sib2, iclass 40, count 2 2006.168.08:15:19.73#ibcon#flushed, iclass 40, count 2 2006.168.08:15:19.73#ibcon#about to write, iclass 40, count 2 2006.168.08:15:19.73#ibcon#wrote, iclass 40, count 2 2006.168.08:15:19.73#ibcon#about to read 3, iclass 40, count 2 2006.168.08:15:19.75#ibcon#read 3, iclass 40, count 2 2006.168.08:15:19.75#ibcon#about to read 4, iclass 40, count 2 2006.168.08:15:19.75#ibcon#read 4, iclass 40, count 2 2006.168.08:15:19.75#ibcon#about to read 5, iclass 40, count 2 2006.168.08:15:19.75#ibcon#read 5, iclass 40, count 2 2006.168.08:15:19.75#ibcon#about to read 6, iclass 40, count 2 2006.168.08:15:19.75#ibcon#read 6, iclass 40, count 2 2006.168.08:15:19.75#ibcon#end of sib2, iclass 40, count 2 2006.168.08:15:19.75#ibcon#*mode == 0, iclass 40, count 2 2006.168.08:15:19.75#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.168.08:15:19.75#ibcon#[25=AT06-06\r\n] 2006.168.08:15:19.75#ibcon#*before write, iclass 40, count 2 2006.168.08:15:19.75#ibcon#enter sib2, iclass 40, count 2 2006.168.08:15:19.75#ibcon#flushed, iclass 40, count 2 2006.168.08:15:19.75#ibcon#about to write, iclass 40, count 2 2006.168.08:15:19.75#ibcon#wrote, iclass 40, count 2 2006.168.08:15:19.75#ibcon#about to read 3, iclass 40, count 2 2006.168.08:15:19.78#ibcon#read 3, iclass 40, count 2 2006.168.08:15:19.78#ibcon#about to read 4, iclass 40, count 2 2006.168.08:15:19.78#ibcon#read 4, iclass 40, count 2 2006.168.08:15:19.78#ibcon#about to read 5, iclass 40, count 2 2006.168.08:15:19.78#ibcon#read 5, iclass 40, count 2 2006.168.08:15:19.78#ibcon#about to read 6, iclass 40, count 2 2006.168.08:15:19.78#ibcon#read 6, iclass 40, count 2 2006.168.08:15:19.78#ibcon#end of sib2, iclass 40, count 2 2006.168.08:15:19.78#ibcon#*after write, iclass 40, count 2 2006.168.08:15:19.78#ibcon#*before return 0, iclass 40, count 2 2006.168.08:15:19.78#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:15:19.78#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:15:19.78#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.168.08:15:19.78#ibcon#ireg 7 cls_cnt 0 2006.168.08:15:19.78#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:15:19.90#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:15:19.90#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:15:19.90#ibcon#enter wrdev, iclass 40, count 0 2006.168.08:15:19.90#ibcon#first serial, iclass 40, count 0 2006.168.08:15:19.90#ibcon#enter sib2, iclass 40, count 0 2006.168.08:15:19.90#ibcon#flushed, iclass 40, count 0 2006.168.08:15:19.90#ibcon#about to write, iclass 40, count 0 2006.168.08:15:19.90#ibcon#wrote, iclass 40, count 0 2006.168.08:15:19.90#ibcon#about to read 3, iclass 40, count 0 2006.168.08:15:19.92#ibcon#read 3, iclass 40, count 0 2006.168.08:15:19.92#ibcon#about to read 4, iclass 40, count 0 2006.168.08:15:19.92#ibcon#read 4, iclass 40, count 0 2006.168.08:15:19.92#ibcon#about to read 5, iclass 40, count 0 2006.168.08:15:19.92#ibcon#read 5, iclass 40, count 0 2006.168.08:15:19.92#ibcon#about to read 6, iclass 40, count 0 2006.168.08:15:19.92#ibcon#read 6, iclass 40, count 0 2006.168.08:15:19.92#ibcon#end of sib2, iclass 40, count 0 2006.168.08:15:19.92#ibcon#*mode == 0, iclass 40, count 0 2006.168.08:15:19.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.168.08:15:19.92#ibcon#[25=USB\r\n] 2006.168.08:15:19.92#ibcon#*before write, iclass 40, count 0 2006.168.08:15:19.92#ibcon#enter sib2, iclass 40, count 0 2006.168.08:15:19.92#ibcon#flushed, iclass 40, count 0 2006.168.08:15:19.92#ibcon#about to write, iclass 40, count 0 2006.168.08:15:19.92#ibcon#wrote, iclass 40, count 0 2006.168.08:15:19.92#ibcon#about to read 3, iclass 40, count 0 2006.168.08:15:19.95#ibcon#read 3, iclass 40, count 0 2006.168.08:15:19.95#ibcon#about to read 4, iclass 40, count 0 2006.168.08:15:19.95#ibcon#read 4, iclass 40, count 0 2006.168.08:15:19.95#ibcon#about to read 5, iclass 40, count 0 2006.168.08:15:19.95#ibcon#read 5, iclass 40, count 0 2006.168.08:15:19.95#ibcon#about to read 6, iclass 40, count 0 2006.168.08:15:19.95#ibcon#read 6, iclass 40, count 0 2006.168.08:15:19.95#ibcon#end of sib2, iclass 40, count 0 2006.168.08:15:19.95#ibcon#*after write, iclass 40, count 0 2006.168.08:15:19.95#ibcon#*before return 0, iclass 40, count 0 2006.168.08:15:19.95#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:15:19.95#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:15:19.95#ibcon#about to clear, iclass 40 cls_cnt 0 2006.168.08:15:19.95#ibcon#cleared, iclass 40 cls_cnt 0 2006.168.08:15:19.95$vc4f8/valo=7,832.99 2006.168.08:15:19.95#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.168.08:15:19.95#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.168.08:15:19.95#ibcon#ireg 17 cls_cnt 0 2006.168.08:15:19.95#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:15:19.95#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:15:19.95#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:15:19.95#ibcon#enter wrdev, iclass 4, count 0 2006.168.08:15:19.95#ibcon#first serial, iclass 4, count 0 2006.168.08:15:19.95#ibcon#enter sib2, iclass 4, count 0 2006.168.08:15:19.95#ibcon#flushed, iclass 4, count 0 2006.168.08:15:19.95#ibcon#about to write, iclass 4, count 0 2006.168.08:15:19.95#ibcon#wrote, iclass 4, count 0 2006.168.08:15:19.95#ibcon#about to read 3, iclass 4, count 0 2006.168.08:15:19.97#ibcon#read 3, iclass 4, count 0 2006.168.08:15:19.97#ibcon#about to read 4, iclass 4, count 0 2006.168.08:15:19.97#ibcon#read 4, iclass 4, count 0 2006.168.08:15:19.97#ibcon#about to read 5, iclass 4, count 0 2006.168.08:15:19.97#ibcon#read 5, iclass 4, count 0 2006.168.08:15:19.97#ibcon#about to read 6, iclass 4, count 0 2006.168.08:15:19.97#ibcon#read 6, iclass 4, count 0 2006.168.08:15:19.97#ibcon#end of sib2, iclass 4, count 0 2006.168.08:15:19.97#ibcon#*mode == 0, iclass 4, count 0 2006.168.08:15:19.97#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.168.08:15:19.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.08:15:19.97#ibcon#*before write, iclass 4, count 0 2006.168.08:15:19.97#ibcon#enter sib2, iclass 4, count 0 2006.168.08:15:19.97#ibcon#flushed, iclass 4, count 0 2006.168.08:15:19.97#ibcon#about to write, iclass 4, count 0 2006.168.08:15:19.97#ibcon#wrote, iclass 4, count 0 2006.168.08:15:19.97#ibcon#about to read 3, iclass 4, count 0 2006.168.08:15:20.01#ibcon#read 3, iclass 4, count 0 2006.168.08:15:20.01#ibcon#about to read 4, iclass 4, count 0 2006.168.08:15:20.01#ibcon#read 4, iclass 4, count 0 2006.168.08:15:20.01#ibcon#about to read 5, iclass 4, count 0 2006.168.08:15:20.01#ibcon#read 5, iclass 4, count 0 2006.168.08:15:20.01#ibcon#about to read 6, iclass 4, count 0 2006.168.08:15:20.01#ibcon#read 6, iclass 4, count 0 2006.168.08:15:20.01#ibcon#end of sib2, iclass 4, count 0 2006.168.08:15:20.01#ibcon#*after write, iclass 4, count 0 2006.168.08:15:20.01#ibcon#*before return 0, iclass 4, count 0 2006.168.08:15:20.01#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:15:20.01#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:15:20.01#ibcon#about to clear, iclass 4 cls_cnt 0 2006.168.08:15:20.01#ibcon#cleared, iclass 4 cls_cnt 0 2006.168.08:15:20.01$vc4f8/va=7,6 2006.168.08:15:20.01#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.168.08:15:20.01#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.168.08:15:20.01#ibcon#ireg 11 cls_cnt 2 2006.168.08:15:20.01#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:15:20.07#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:15:20.07#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:15:20.07#ibcon#enter wrdev, iclass 6, count 2 2006.168.08:15:20.07#ibcon#first serial, iclass 6, count 2 2006.168.08:15:20.07#ibcon#enter sib2, iclass 6, count 2 2006.168.08:15:20.07#ibcon#flushed, iclass 6, count 2 2006.168.08:15:20.07#ibcon#about to write, iclass 6, count 2 2006.168.08:15:20.07#ibcon#wrote, iclass 6, count 2 2006.168.08:15:20.07#ibcon#about to read 3, iclass 6, count 2 2006.168.08:15:20.09#ibcon#read 3, iclass 6, count 2 2006.168.08:15:20.09#ibcon#about to read 4, iclass 6, count 2 2006.168.08:15:20.09#ibcon#read 4, iclass 6, count 2 2006.168.08:15:20.09#ibcon#about to read 5, iclass 6, count 2 2006.168.08:15:20.09#ibcon#read 5, iclass 6, count 2 2006.168.08:15:20.09#ibcon#about to read 6, iclass 6, count 2 2006.168.08:15:20.09#ibcon#read 6, iclass 6, count 2 2006.168.08:15:20.09#ibcon#end of sib2, iclass 6, count 2 2006.168.08:15:20.09#ibcon#*mode == 0, iclass 6, count 2 2006.168.08:15:20.09#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.168.08:15:20.09#ibcon#[25=AT07-06\r\n] 2006.168.08:15:20.09#ibcon#*before write, iclass 6, count 2 2006.168.08:15:20.09#ibcon#enter sib2, iclass 6, count 2 2006.168.08:15:20.09#ibcon#flushed, iclass 6, count 2 2006.168.08:15:20.09#ibcon#about to write, iclass 6, count 2 2006.168.08:15:20.09#ibcon#wrote, iclass 6, count 2 2006.168.08:15:20.09#ibcon#about to read 3, iclass 6, count 2 2006.168.08:15:20.12#ibcon#read 3, iclass 6, count 2 2006.168.08:15:20.12#ibcon#about to read 4, iclass 6, count 2 2006.168.08:15:20.12#ibcon#read 4, iclass 6, count 2 2006.168.08:15:20.12#ibcon#about to read 5, iclass 6, count 2 2006.168.08:15:20.12#ibcon#read 5, iclass 6, count 2 2006.168.08:15:20.12#ibcon#about to read 6, iclass 6, count 2 2006.168.08:15:20.12#ibcon#read 6, iclass 6, count 2 2006.168.08:15:20.12#ibcon#end of sib2, iclass 6, count 2 2006.168.08:15:20.12#ibcon#*after write, iclass 6, count 2 2006.168.08:15:20.12#ibcon#*before return 0, iclass 6, count 2 2006.168.08:15:20.12#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:15:20.12#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:15:20.12#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.168.08:15:20.12#ibcon#ireg 7 cls_cnt 0 2006.168.08:15:20.12#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:15:20.24#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:15:20.24#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:15:20.24#ibcon#enter wrdev, iclass 6, count 0 2006.168.08:15:20.24#ibcon#first serial, iclass 6, count 0 2006.168.08:15:20.24#ibcon#enter sib2, iclass 6, count 0 2006.168.08:15:20.24#ibcon#flushed, iclass 6, count 0 2006.168.08:15:20.24#ibcon#about to write, iclass 6, count 0 2006.168.08:15:20.24#ibcon#wrote, iclass 6, count 0 2006.168.08:15:20.24#ibcon#about to read 3, iclass 6, count 0 2006.168.08:15:20.26#ibcon#read 3, iclass 6, count 0 2006.168.08:15:20.26#ibcon#about to read 4, iclass 6, count 0 2006.168.08:15:20.26#ibcon#read 4, iclass 6, count 0 2006.168.08:15:20.26#ibcon#about to read 5, iclass 6, count 0 2006.168.08:15:20.26#ibcon#read 5, iclass 6, count 0 2006.168.08:15:20.26#ibcon#about to read 6, iclass 6, count 0 2006.168.08:15:20.26#ibcon#read 6, iclass 6, count 0 2006.168.08:15:20.26#ibcon#end of sib2, iclass 6, count 0 2006.168.08:15:20.26#ibcon#*mode == 0, iclass 6, count 0 2006.168.08:15:20.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.168.08:15:20.26#ibcon#[25=USB\r\n] 2006.168.08:15:20.26#ibcon#*before write, iclass 6, count 0 2006.168.08:15:20.26#ibcon#enter sib2, iclass 6, count 0 2006.168.08:15:20.26#ibcon#flushed, iclass 6, count 0 2006.168.08:15:20.26#ibcon#about to write, iclass 6, count 0 2006.168.08:15:20.26#ibcon#wrote, iclass 6, count 0 2006.168.08:15:20.26#ibcon#about to read 3, iclass 6, count 0 2006.168.08:15:20.29#ibcon#read 3, iclass 6, count 0 2006.168.08:15:20.29#ibcon#about to read 4, iclass 6, count 0 2006.168.08:15:20.29#ibcon#read 4, iclass 6, count 0 2006.168.08:15:20.29#ibcon#about to read 5, iclass 6, count 0 2006.168.08:15:20.29#ibcon#read 5, iclass 6, count 0 2006.168.08:15:20.29#ibcon#about to read 6, iclass 6, count 0 2006.168.08:15:20.29#ibcon#read 6, iclass 6, count 0 2006.168.08:15:20.29#ibcon#end of sib2, iclass 6, count 0 2006.168.08:15:20.29#ibcon#*after write, iclass 6, count 0 2006.168.08:15:20.29#ibcon#*before return 0, iclass 6, count 0 2006.168.08:15:20.29#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:15:20.29#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:15:20.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.168.08:15:20.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.168.08:15:20.29$vc4f8/valo=8,852.99 2006.168.08:15:20.29#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.168.08:15:20.29#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.168.08:15:20.29#ibcon#ireg 17 cls_cnt 0 2006.168.08:15:20.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:15:20.29#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:15:20.29#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:15:20.29#ibcon#enter wrdev, iclass 10, count 0 2006.168.08:15:20.29#ibcon#first serial, iclass 10, count 0 2006.168.08:15:20.29#ibcon#enter sib2, iclass 10, count 0 2006.168.08:15:20.29#ibcon#flushed, iclass 10, count 0 2006.168.08:15:20.29#ibcon#about to write, iclass 10, count 0 2006.168.08:15:20.29#ibcon#wrote, iclass 10, count 0 2006.168.08:15:20.29#ibcon#about to read 3, iclass 10, count 0 2006.168.08:15:20.31#ibcon#read 3, iclass 10, count 0 2006.168.08:15:20.31#ibcon#about to read 4, iclass 10, count 0 2006.168.08:15:20.31#ibcon#read 4, iclass 10, count 0 2006.168.08:15:20.31#ibcon#about to read 5, iclass 10, count 0 2006.168.08:15:20.31#ibcon#read 5, iclass 10, count 0 2006.168.08:15:20.31#ibcon#about to read 6, iclass 10, count 0 2006.168.08:15:20.31#ibcon#read 6, iclass 10, count 0 2006.168.08:15:20.31#ibcon#end of sib2, iclass 10, count 0 2006.168.08:15:20.31#ibcon#*mode == 0, iclass 10, count 0 2006.168.08:15:20.31#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.168.08:15:20.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.08:15:20.31#ibcon#*before write, iclass 10, count 0 2006.168.08:15:20.31#ibcon#enter sib2, iclass 10, count 0 2006.168.08:15:20.31#ibcon#flushed, iclass 10, count 0 2006.168.08:15:20.31#ibcon#about to write, iclass 10, count 0 2006.168.08:15:20.31#ibcon#wrote, iclass 10, count 0 2006.168.08:15:20.31#ibcon#about to read 3, iclass 10, count 0 2006.168.08:15:20.35#ibcon#read 3, iclass 10, count 0 2006.168.08:15:20.35#ibcon#about to read 4, iclass 10, count 0 2006.168.08:15:20.35#ibcon#read 4, iclass 10, count 0 2006.168.08:15:20.35#ibcon#about to read 5, iclass 10, count 0 2006.168.08:15:20.35#ibcon#read 5, iclass 10, count 0 2006.168.08:15:20.35#ibcon#about to read 6, iclass 10, count 0 2006.168.08:15:20.35#ibcon#read 6, iclass 10, count 0 2006.168.08:15:20.35#ibcon#end of sib2, iclass 10, count 0 2006.168.08:15:20.35#ibcon#*after write, iclass 10, count 0 2006.168.08:15:20.35#ibcon#*before return 0, iclass 10, count 0 2006.168.08:15:20.35#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:15:20.35#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:15:20.35#ibcon#about to clear, iclass 10 cls_cnt 0 2006.168.08:15:20.35#ibcon#cleared, iclass 10 cls_cnt 0 2006.168.08:15:20.35$vc4f8/va=8,7 2006.168.08:15:20.35#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.168.08:15:20.35#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.168.08:15:20.35#ibcon#ireg 11 cls_cnt 2 2006.168.08:15:20.35#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:15:20.41#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:15:20.41#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:15:20.41#ibcon#enter wrdev, iclass 12, count 2 2006.168.08:15:20.41#ibcon#first serial, iclass 12, count 2 2006.168.08:15:20.41#ibcon#enter sib2, iclass 12, count 2 2006.168.08:15:20.41#ibcon#flushed, iclass 12, count 2 2006.168.08:15:20.41#ibcon#about to write, iclass 12, count 2 2006.168.08:15:20.41#ibcon#wrote, iclass 12, count 2 2006.168.08:15:20.41#ibcon#about to read 3, iclass 12, count 2 2006.168.08:15:20.43#ibcon#read 3, iclass 12, count 2 2006.168.08:15:20.43#ibcon#about to read 4, iclass 12, count 2 2006.168.08:15:20.43#ibcon#read 4, iclass 12, count 2 2006.168.08:15:20.43#ibcon#about to read 5, iclass 12, count 2 2006.168.08:15:20.43#ibcon#read 5, iclass 12, count 2 2006.168.08:15:20.43#ibcon#about to read 6, iclass 12, count 2 2006.168.08:15:20.43#ibcon#read 6, iclass 12, count 2 2006.168.08:15:20.43#ibcon#end of sib2, iclass 12, count 2 2006.168.08:15:20.43#ibcon#*mode == 0, iclass 12, count 2 2006.168.08:15:20.43#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.168.08:15:20.43#ibcon#[25=AT08-07\r\n] 2006.168.08:15:20.43#ibcon#*before write, iclass 12, count 2 2006.168.08:15:20.43#ibcon#enter sib2, iclass 12, count 2 2006.168.08:15:20.43#ibcon#flushed, iclass 12, count 2 2006.168.08:15:20.43#ibcon#about to write, iclass 12, count 2 2006.168.08:15:20.43#ibcon#wrote, iclass 12, count 2 2006.168.08:15:20.43#ibcon#about to read 3, iclass 12, count 2 2006.168.08:15:20.46#ibcon#read 3, iclass 12, count 2 2006.168.08:15:20.46#ibcon#about to read 4, iclass 12, count 2 2006.168.08:15:20.46#ibcon#read 4, iclass 12, count 2 2006.168.08:15:20.46#ibcon#about to read 5, iclass 12, count 2 2006.168.08:15:20.46#ibcon#read 5, iclass 12, count 2 2006.168.08:15:20.46#ibcon#about to read 6, iclass 12, count 2 2006.168.08:15:20.46#ibcon#read 6, iclass 12, count 2 2006.168.08:15:20.46#ibcon#end of sib2, iclass 12, count 2 2006.168.08:15:20.46#ibcon#*after write, iclass 12, count 2 2006.168.08:15:20.46#ibcon#*before return 0, iclass 12, count 2 2006.168.08:15:20.46#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:15:20.46#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:15:20.46#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.168.08:15:20.46#ibcon#ireg 7 cls_cnt 0 2006.168.08:15:20.46#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:15:20.58#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:15:20.58#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:15:20.58#ibcon#enter wrdev, iclass 12, count 0 2006.168.08:15:20.58#ibcon#first serial, iclass 12, count 0 2006.168.08:15:20.58#ibcon#enter sib2, iclass 12, count 0 2006.168.08:15:20.58#ibcon#flushed, iclass 12, count 0 2006.168.08:15:20.58#ibcon#about to write, iclass 12, count 0 2006.168.08:15:20.58#ibcon#wrote, iclass 12, count 0 2006.168.08:15:20.58#ibcon#about to read 3, iclass 12, count 0 2006.168.08:15:20.60#ibcon#read 3, iclass 12, count 0 2006.168.08:15:20.60#ibcon#about to read 4, iclass 12, count 0 2006.168.08:15:20.60#ibcon#read 4, iclass 12, count 0 2006.168.08:15:20.60#ibcon#about to read 5, iclass 12, count 0 2006.168.08:15:20.60#ibcon#read 5, iclass 12, count 0 2006.168.08:15:20.60#ibcon#about to read 6, iclass 12, count 0 2006.168.08:15:20.60#ibcon#read 6, iclass 12, count 0 2006.168.08:15:20.60#ibcon#end of sib2, iclass 12, count 0 2006.168.08:15:20.60#ibcon#*mode == 0, iclass 12, count 0 2006.168.08:15:20.60#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.168.08:15:20.60#ibcon#[25=USB\r\n] 2006.168.08:15:20.60#ibcon#*before write, iclass 12, count 0 2006.168.08:15:20.60#ibcon#enter sib2, iclass 12, count 0 2006.168.08:15:20.60#ibcon#flushed, iclass 12, count 0 2006.168.08:15:20.60#ibcon#about to write, iclass 12, count 0 2006.168.08:15:20.60#ibcon#wrote, iclass 12, count 0 2006.168.08:15:20.60#ibcon#about to read 3, iclass 12, count 0 2006.168.08:15:20.63#ibcon#read 3, iclass 12, count 0 2006.168.08:15:20.63#ibcon#about to read 4, iclass 12, count 0 2006.168.08:15:20.63#ibcon#read 4, iclass 12, count 0 2006.168.08:15:20.63#ibcon#about to read 5, iclass 12, count 0 2006.168.08:15:20.63#ibcon#read 5, iclass 12, count 0 2006.168.08:15:20.63#ibcon#about to read 6, iclass 12, count 0 2006.168.08:15:20.63#ibcon#read 6, iclass 12, count 0 2006.168.08:15:20.63#ibcon#end of sib2, iclass 12, count 0 2006.168.08:15:20.63#ibcon#*after write, iclass 12, count 0 2006.168.08:15:20.63#ibcon#*before return 0, iclass 12, count 0 2006.168.08:15:20.63#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:15:20.63#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:15:20.63#ibcon#about to clear, iclass 12 cls_cnt 0 2006.168.08:15:20.63#ibcon#cleared, iclass 12 cls_cnt 0 2006.168.08:15:20.63$vc4f8/vblo=1,632.99 2006.168.08:15:20.63#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.168.08:15:20.63#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.168.08:15:20.63#ibcon#ireg 17 cls_cnt 0 2006.168.08:15:20.63#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:15:20.63#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:15:20.63#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:15:20.63#ibcon#enter wrdev, iclass 14, count 0 2006.168.08:15:20.63#ibcon#first serial, iclass 14, count 0 2006.168.08:15:20.63#ibcon#enter sib2, iclass 14, count 0 2006.168.08:15:20.63#ibcon#flushed, iclass 14, count 0 2006.168.08:15:20.63#ibcon#about to write, iclass 14, count 0 2006.168.08:15:20.63#ibcon#wrote, iclass 14, count 0 2006.168.08:15:20.63#ibcon#about to read 3, iclass 14, count 0 2006.168.08:15:20.65#ibcon#read 3, iclass 14, count 0 2006.168.08:15:20.65#ibcon#about to read 4, iclass 14, count 0 2006.168.08:15:20.65#ibcon#read 4, iclass 14, count 0 2006.168.08:15:20.65#ibcon#about to read 5, iclass 14, count 0 2006.168.08:15:20.65#ibcon#read 5, iclass 14, count 0 2006.168.08:15:20.65#ibcon#about to read 6, iclass 14, count 0 2006.168.08:15:20.65#ibcon#read 6, iclass 14, count 0 2006.168.08:15:20.65#ibcon#end of sib2, iclass 14, count 0 2006.168.08:15:20.65#ibcon#*mode == 0, iclass 14, count 0 2006.168.08:15:20.65#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.168.08:15:20.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.08:15:20.65#ibcon#*before write, iclass 14, count 0 2006.168.08:15:20.65#ibcon#enter sib2, iclass 14, count 0 2006.168.08:15:20.65#ibcon#flushed, iclass 14, count 0 2006.168.08:15:20.65#ibcon#about to write, iclass 14, count 0 2006.168.08:15:20.65#ibcon#wrote, iclass 14, count 0 2006.168.08:15:20.65#ibcon#about to read 3, iclass 14, count 0 2006.168.08:15:20.69#ibcon#read 3, iclass 14, count 0 2006.168.08:15:20.69#ibcon#about to read 4, iclass 14, count 0 2006.168.08:15:20.69#ibcon#read 4, iclass 14, count 0 2006.168.08:15:20.69#ibcon#about to read 5, iclass 14, count 0 2006.168.08:15:20.69#ibcon#read 5, iclass 14, count 0 2006.168.08:15:20.69#ibcon#about to read 6, iclass 14, count 0 2006.168.08:15:20.69#ibcon#read 6, iclass 14, count 0 2006.168.08:15:20.69#ibcon#end of sib2, iclass 14, count 0 2006.168.08:15:20.69#ibcon#*after write, iclass 14, count 0 2006.168.08:15:20.69#ibcon#*before return 0, iclass 14, count 0 2006.168.08:15:20.69#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:15:20.69#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:15:20.69#ibcon#about to clear, iclass 14 cls_cnt 0 2006.168.08:15:20.69#ibcon#cleared, iclass 14 cls_cnt 0 2006.168.08:15:20.69$vc4f8/vb=1,4 2006.168.08:15:20.69#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.168.08:15:20.69#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.168.08:15:20.69#ibcon#ireg 11 cls_cnt 2 2006.168.08:15:20.69#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:15:20.69#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:15:20.69#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:15:20.69#ibcon#enter wrdev, iclass 16, count 2 2006.168.08:15:20.69#ibcon#first serial, iclass 16, count 2 2006.168.08:15:20.69#ibcon#enter sib2, iclass 16, count 2 2006.168.08:15:20.69#ibcon#flushed, iclass 16, count 2 2006.168.08:15:20.69#ibcon#about to write, iclass 16, count 2 2006.168.08:15:20.69#ibcon#wrote, iclass 16, count 2 2006.168.08:15:20.69#ibcon#about to read 3, iclass 16, count 2 2006.168.08:15:20.71#ibcon#read 3, iclass 16, count 2 2006.168.08:15:20.71#ibcon#about to read 4, iclass 16, count 2 2006.168.08:15:20.71#ibcon#read 4, iclass 16, count 2 2006.168.08:15:20.71#ibcon#about to read 5, iclass 16, count 2 2006.168.08:15:20.71#ibcon#read 5, iclass 16, count 2 2006.168.08:15:20.71#ibcon#about to read 6, iclass 16, count 2 2006.168.08:15:20.71#ibcon#read 6, iclass 16, count 2 2006.168.08:15:20.71#ibcon#end of sib2, iclass 16, count 2 2006.168.08:15:20.71#ibcon#*mode == 0, iclass 16, count 2 2006.168.08:15:20.71#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.168.08:15:20.71#ibcon#[27=AT01-04\r\n] 2006.168.08:15:20.71#ibcon#*before write, iclass 16, count 2 2006.168.08:15:20.71#ibcon#enter sib2, iclass 16, count 2 2006.168.08:15:20.71#ibcon#flushed, iclass 16, count 2 2006.168.08:15:20.71#ibcon#about to write, iclass 16, count 2 2006.168.08:15:20.71#ibcon#wrote, iclass 16, count 2 2006.168.08:15:20.71#ibcon#about to read 3, iclass 16, count 2 2006.168.08:15:20.74#ibcon#read 3, iclass 16, count 2 2006.168.08:15:20.74#ibcon#about to read 4, iclass 16, count 2 2006.168.08:15:20.74#ibcon#read 4, iclass 16, count 2 2006.168.08:15:20.74#ibcon#about to read 5, iclass 16, count 2 2006.168.08:15:20.74#ibcon#read 5, iclass 16, count 2 2006.168.08:15:20.74#ibcon#about to read 6, iclass 16, count 2 2006.168.08:15:20.74#ibcon#read 6, iclass 16, count 2 2006.168.08:15:20.74#ibcon#end of sib2, iclass 16, count 2 2006.168.08:15:20.74#ibcon#*after write, iclass 16, count 2 2006.168.08:15:20.74#ibcon#*before return 0, iclass 16, count 2 2006.168.08:15:20.74#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:15:20.74#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:15:20.74#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.168.08:15:20.74#ibcon#ireg 7 cls_cnt 0 2006.168.08:15:20.74#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:15:20.86#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:15:20.86#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:15:20.86#ibcon#enter wrdev, iclass 16, count 0 2006.168.08:15:20.86#ibcon#first serial, iclass 16, count 0 2006.168.08:15:20.86#ibcon#enter sib2, iclass 16, count 0 2006.168.08:15:20.86#ibcon#flushed, iclass 16, count 0 2006.168.08:15:20.86#ibcon#about to write, iclass 16, count 0 2006.168.08:15:20.86#ibcon#wrote, iclass 16, count 0 2006.168.08:15:20.86#ibcon#about to read 3, iclass 16, count 0 2006.168.08:15:20.88#ibcon#read 3, iclass 16, count 0 2006.168.08:15:20.88#ibcon#about to read 4, iclass 16, count 0 2006.168.08:15:20.88#ibcon#read 4, iclass 16, count 0 2006.168.08:15:20.88#ibcon#about to read 5, iclass 16, count 0 2006.168.08:15:20.88#ibcon#read 5, iclass 16, count 0 2006.168.08:15:20.88#ibcon#about to read 6, iclass 16, count 0 2006.168.08:15:20.88#ibcon#read 6, iclass 16, count 0 2006.168.08:15:20.88#ibcon#end of sib2, iclass 16, count 0 2006.168.08:15:20.88#ibcon#*mode == 0, iclass 16, count 0 2006.168.08:15:20.88#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.168.08:15:20.88#ibcon#[27=USB\r\n] 2006.168.08:15:20.88#ibcon#*before write, iclass 16, count 0 2006.168.08:15:20.88#ibcon#enter sib2, iclass 16, count 0 2006.168.08:15:20.88#ibcon#flushed, iclass 16, count 0 2006.168.08:15:20.88#ibcon#about to write, iclass 16, count 0 2006.168.08:15:20.88#ibcon#wrote, iclass 16, count 0 2006.168.08:15:20.88#ibcon#about to read 3, iclass 16, count 0 2006.168.08:15:20.91#ibcon#read 3, iclass 16, count 0 2006.168.08:15:20.91#ibcon#about to read 4, iclass 16, count 0 2006.168.08:15:20.91#ibcon#read 4, iclass 16, count 0 2006.168.08:15:20.91#ibcon#about to read 5, iclass 16, count 0 2006.168.08:15:20.91#ibcon#read 5, iclass 16, count 0 2006.168.08:15:20.91#ibcon#about to read 6, iclass 16, count 0 2006.168.08:15:20.91#ibcon#read 6, iclass 16, count 0 2006.168.08:15:20.91#ibcon#end of sib2, iclass 16, count 0 2006.168.08:15:20.91#ibcon#*after write, iclass 16, count 0 2006.168.08:15:20.91#ibcon#*before return 0, iclass 16, count 0 2006.168.08:15:20.91#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:15:20.91#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:15:20.91#ibcon#about to clear, iclass 16 cls_cnt 0 2006.168.08:15:20.91#ibcon#cleared, iclass 16 cls_cnt 0 2006.168.08:15:20.91$vc4f8/vblo=2,640.99 2006.168.08:15:20.91#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.168.08:15:20.91#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.168.08:15:20.91#ibcon#ireg 17 cls_cnt 0 2006.168.08:15:20.91#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:15:20.91#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:15:20.91#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:15:20.91#ibcon#enter wrdev, iclass 18, count 0 2006.168.08:15:20.91#ibcon#first serial, iclass 18, count 0 2006.168.08:15:20.91#ibcon#enter sib2, iclass 18, count 0 2006.168.08:15:20.91#ibcon#flushed, iclass 18, count 0 2006.168.08:15:20.91#ibcon#about to write, iclass 18, count 0 2006.168.08:15:20.91#ibcon#wrote, iclass 18, count 0 2006.168.08:15:20.91#ibcon#about to read 3, iclass 18, count 0 2006.168.08:15:20.93#ibcon#read 3, iclass 18, count 0 2006.168.08:15:20.93#ibcon#about to read 4, iclass 18, count 0 2006.168.08:15:20.93#ibcon#read 4, iclass 18, count 0 2006.168.08:15:20.93#ibcon#about to read 5, iclass 18, count 0 2006.168.08:15:20.93#ibcon#read 5, iclass 18, count 0 2006.168.08:15:20.93#ibcon#about to read 6, iclass 18, count 0 2006.168.08:15:20.93#ibcon#read 6, iclass 18, count 0 2006.168.08:15:20.93#ibcon#end of sib2, iclass 18, count 0 2006.168.08:15:20.93#ibcon#*mode == 0, iclass 18, count 0 2006.168.08:15:20.93#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.08:15:20.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.08:15:20.93#ibcon#*before write, iclass 18, count 0 2006.168.08:15:20.93#ibcon#enter sib2, iclass 18, count 0 2006.168.08:15:20.93#ibcon#flushed, iclass 18, count 0 2006.168.08:15:20.93#ibcon#about to write, iclass 18, count 0 2006.168.08:15:20.93#ibcon#wrote, iclass 18, count 0 2006.168.08:15:20.93#ibcon#about to read 3, iclass 18, count 0 2006.168.08:15:20.97#ibcon#read 3, iclass 18, count 0 2006.168.08:15:20.97#ibcon#about to read 4, iclass 18, count 0 2006.168.08:15:20.97#ibcon#read 4, iclass 18, count 0 2006.168.08:15:20.97#ibcon#about to read 5, iclass 18, count 0 2006.168.08:15:20.97#ibcon#read 5, iclass 18, count 0 2006.168.08:15:20.97#ibcon#about to read 6, iclass 18, count 0 2006.168.08:15:20.97#ibcon#read 6, iclass 18, count 0 2006.168.08:15:20.97#ibcon#end of sib2, iclass 18, count 0 2006.168.08:15:20.97#ibcon#*after write, iclass 18, count 0 2006.168.08:15:20.97#ibcon#*before return 0, iclass 18, count 0 2006.168.08:15:20.97#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:15:20.97#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:15:20.97#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.08:15:20.97#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.08:15:20.97$vc4f8/vb=2,4 2006.168.08:15:20.97#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.168.08:15:20.97#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.168.08:15:20.97#ibcon#ireg 11 cls_cnt 2 2006.168.08:15:20.97#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:15:21.03#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:15:21.03#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:15:21.03#ibcon#enter wrdev, iclass 20, count 2 2006.168.08:15:21.03#ibcon#first serial, iclass 20, count 2 2006.168.08:15:21.03#ibcon#enter sib2, iclass 20, count 2 2006.168.08:15:21.03#ibcon#flushed, iclass 20, count 2 2006.168.08:15:21.03#ibcon#about to write, iclass 20, count 2 2006.168.08:15:21.03#ibcon#wrote, iclass 20, count 2 2006.168.08:15:21.03#ibcon#about to read 3, iclass 20, count 2 2006.168.08:15:21.05#ibcon#read 3, iclass 20, count 2 2006.168.08:15:21.05#ibcon#about to read 4, iclass 20, count 2 2006.168.08:15:21.05#ibcon#read 4, iclass 20, count 2 2006.168.08:15:21.05#ibcon#about to read 5, iclass 20, count 2 2006.168.08:15:21.05#ibcon#read 5, iclass 20, count 2 2006.168.08:15:21.05#ibcon#about to read 6, iclass 20, count 2 2006.168.08:15:21.05#ibcon#read 6, iclass 20, count 2 2006.168.08:15:21.05#ibcon#end of sib2, iclass 20, count 2 2006.168.08:15:21.05#ibcon#*mode == 0, iclass 20, count 2 2006.168.08:15:21.05#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.168.08:15:21.05#ibcon#[27=AT02-04\r\n] 2006.168.08:15:21.05#ibcon#*before write, iclass 20, count 2 2006.168.08:15:21.05#ibcon#enter sib2, iclass 20, count 2 2006.168.08:15:21.05#ibcon#flushed, iclass 20, count 2 2006.168.08:15:21.05#ibcon#about to write, iclass 20, count 2 2006.168.08:15:21.05#ibcon#wrote, iclass 20, count 2 2006.168.08:15:21.05#ibcon#about to read 3, iclass 20, count 2 2006.168.08:15:21.08#ibcon#read 3, iclass 20, count 2 2006.168.08:15:21.08#ibcon#about to read 4, iclass 20, count 2 2006.168.08:15:21.08#ibcon#read 4, iclass 20, count 2 2006.168.08:15:21.08#ibcon#about to read 5, iclass 20, count 2 2006.168.08:15:21.08#ibcon#read 5, iclass 20, count 2 2006.168.08:15:21.08#ibcon#about to read 6, iclass 20, count 2 2006.168.08:15:21.08#ibcon#read 6, iclass 20, count 2 2006.168.08:15:21.08#ibcon#end of sib2, iclass 20, count 2 2006.168.08:15:21.08#ibcon#*after write, iclass 20, count 2 2006.168.08:15:21.08#ibcon#*before return 0, iclass 20, count 2 2006.168.08:15:21.08#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:15:21.08#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:15:21.08#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.168.08:15:21.08#ibcon#ireg 7 cls_cnt 0 2006.168.08:15:21.08#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:15:21.20#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:15:21.20#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:15:21.20#ibcon#enter wrdev, iclass 20, count 0 2006.168.08:15:21.20#ibcon#first serial, iclass 20, count 0 2006.168.08:15:21.20#ibcon#enter sib2, iclass 20, count 0 2006.168.08:15:21.20#ibcon#flushed, iclass 20, count 0 2006.168.08:15:21.20#ibcon#about to write, iclass 20, count 0 2006.168.08:15:21.20#ibcon#wrote, iclass 20, count 0 2006.168.08:15:21.20#ibcon#about to read 3, iclass 20, count 0 2006.168.08:15:21.22#ibcon#read 3, iclass 20, count 0 2006.168.08:15:21.22#ibcon#about to read 4, iclass 20, count 0 2006.168.08:15:21.22#ibcon#read 4, iclass 20, count 0 2006.168.08:15:21.22#ibcon#about to read 5, iclass 20, count 0 2006.168.08:15:21.22#ibcon#read 5, iclass 20, count 0 2006.168.08:15:21.22#ibcon#about to read 6, iclass 20, count 0 2006.168.08:15:21.22#ibcon#read 6, iclass 20, count 0 2006.168.08:15:21.22#ibcon#end of sib2, iclass 20, count 0 2006.168.08:15:21.22#ibcon#*mode == 0, iclass 20, count 0 2006.168.08:15:21.22#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.168.08:15:21.22#ibcon#[27=USB\r\n] 2006.168.08:15:21.22#ibcon#*before write, iclass 20, count 0 2006.168.08:15:21.22#ibcon#enter sib2, iclass 20, count 0 2006.168.08:15:21.22#ibcon#flushed, iclass 20, count 0 2006.168.08:15:21.22#ibcon#about to write, iclass 20, count 0 2006.168.08:15:21.22#ibcon#wrote, iclass 20, count 0 2006.168.08:15:21.22#ibcon#about to read 3, iclass 20, count 0 2006.168.08:15:21.25#ibcon#read 3, iclass 20, count 0 2006.168.08:15:21.25#ibcon#about to read 4, iclass 20, count 0 2006.168.08:15:21.25#ibcon#read 4, iclass 20, count 0 2006.168.08:15:21.25#ibcon#about to read 5, iclass 20, count 0 2006.168.08:15:21.25#ibcon#read 5, iclass 20, count 0 2006.168.08:15:21.25#ibcon#about to read 6, iclass 20, count 0 2006.168.08:15:21.25#ibcon#read 6, iclass 20, count 0 2006.168.08:15:21.25#ibcon#end of sib2, iclass 20, count 0 2006.168.08:15:21.25#ibcon#*after write, iclass 20, count 0 2006.168.08:15:21.25#ibcon#*before return 0, iclass 20, count 0 2006.168.08:15:21.25#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:15:21.25#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:15:21.25#ibcon#about to clear, iclass 20 cls_cnt 0 2006.168.08:15:21.25#ibcon#cleared, iclass 20 cls_cnt 0 2006.168.08:15:21.25$vc4f8/vblo=3,656.99 2006.168.08:15:21.25#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.168.08:15:21.25#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.168.08:15:21.25#ibcon#ireg 17 cls_cnt 0 2006.168.08:15:21.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:15:21.25#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:15:21.25#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:15:21.25#ibcon#enter wrdev, iclass 22, count 0 2006.168.08:15:21.25#ibcon#first serial, iclass 22, count 0 2006.168.08:15:21.25#ibcon#enter sib2, iclass 22, count 0 2006.168.08:15:21.25#ibcon#flushed, iclass 22, count 0 2006.168.08:15:21.25#ibcon#about to write, iclass 22, count 0 2006.168.08:15:21.25#ibcon#wrote, iclass 22, count 0 2006.168.08:15:21.25#ibcon#about to read 3, iclass 22, count 0 2006.168.08:15:21.27#ibcon#read 3, iclass 22, count 0 2006.168.08:15:21.27#ibcon#about to read 4, iclass 22, count 0 2006.168.08:15:21.27#ibcon#read 4, iclass 22, count 0 2006.168.08:15:21.27#ibcon#about to read 5, iclass 22, count 0 2006.168.08:15:21.27#ibcon#read 5, iclass 22, count 0 2006.168.08:15:21.27#ibcon#about to read 6, iclass 22, count 0 2006.168.08:15:21.27#ibcon#read 6, iclass 22, count 0 2006.168.08:15:21.27#ibcon#end of sib2, iclass 22, count 0 2006.168.08:15:21.27#ibcon#*mode == 0, iclass 22, count 0 2006.168.08:15:21.27#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.168.08:15:21.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.08:15:21.27#ibcon#*before write, iclass 22, count 0 2006.168.08:15:21.27#ibcon#enter sib2, iclass 22, count 0 2006.168.08:15:21.27#ibcon#flushed, iclass 22, count 0 2006.168.08:15:21.27#ibcon#about to write, iclass 22, count 0 2006.168.08:15:21.27#ibcon#wrote, iclass 22, count 0 2006.168.08:15:21.27#ibcon#about to read 3, iclass 22, count 0 2006.168.08:15:21.31#ibcon#read 3, iclass 22, count 0 2006.168.08:15:21.31#ibcon#about to read 4, iclass 22, count 0 2006.168.08:15:21.31#ibcon#read 4, iclass 22, count 0 2006.168.08:15:21.31#ibcon#about to read 5, iclass 22, count 0 2006.168.08:15:21.31#ibcon#read 5, iclass 22, count 0 2006.168.08:15:21.31#ibcon#about to read 6, iclass 22, count 0 2006.168.08:15:21.31#ibcon#read 6, iclass 22, count 0 2006.168.08:15:21.31#ibcon#end of sib2, iclass 22, count 0 2006.168.08:15:21.31#ibcon#*after write, iclass 22, count 0 2006.168.08:15:21.31#ibcon#*before return 0, iclass 22, count 0 2006.168.08:15:21.31#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:15:21.31#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:15:21.31#ibcon#about to clear, iclass 22 cls_cnt 0 2006.168.08:15:21.31#ibcon#cleared, iclass 22 cls_cnt 0 2006.168.08:15:21.31$vc4f8/vb=3,4 2006.168.08:15:21.31#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.168.08:15:21.31#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.168.08:15:21.31#ibcon#ireg 11 cls_cnt 2 2006.168.08:15:21.31#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:15:21.37#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:15:21.37#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:15:21.37#ibcon#enter wrdev, iclass 24, count 2 2006.168.08:15:21.37#ibcon#first serial, iclass 24, count 2 2006.168.08:15:21.37#ibcon#enter sib2, iclass 24, count 2 2006.168.08:15:21.37#ibcon#flushed, iclass 24, count 2 2006.168.08:15:21.37#ibcon#about to write, iclass 24, count 2 2006.168.08:15:21.37#ibcon#wrote, iclass 24, count 2 2006.168.08:15:21.37#ibcon#about to read 3, iclass 24, count 2 2006.168.08:15:21.39#ibcon#read 3, iclass 24, count 2 2006.168.08:15:21.39#ibcon#about to read 4, iclass 24, count 2 2006.168.08:15:21.39#ibcon#read 4, iclass 24, count 2 2006.168.08:15:21.39#ibcon#about to read 5, iclass 24, count 2 2006.168.08:15:21.39#ibcon#read 5, iclass 24, count 2 2006.168.08:15:21.39#ibcon#about to read 6, iclass 24, count 2 2006.168.08:15:21.39#ibcon#read 6, iclass 24, count 2 2006.168.08:15:21.39#ibcon#end of sib2, iclass 24, count 2 2006.168.08:15:21.39#ibcon#*mode == 0, iclass 24, count 2 2006.168.08:15:21.39#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.168.08:15:21.39#ibcon#[27=AT03-04\r\n] 2006.168.08:15:21.39#ibcon#*before write, iclass 24, count 2 2006.168.08:15:21.39#ibcon#enter sib2, iclass 24, count 2 2006.168.08:15:21.39#ibcon#flushed, iclass 24, count 2 2006.168.08:15:21.39#ibcon#about to write, iclass 24, count 2 2006.168.08:15:21.39#ibcon#wrote, iclass 24, count 2 2006.168.08:15:21.39#ibcon#about to read 3, iclass 24, count 2 2006.168.08:15:21.42#ibcon#read 3, iclass 24, count 2 2006.168.08:15:21.42#ibcon#about to read 4, iclass 24, count 2 2006.168.08:15:21.42#ibcon#read 4, iclass 24, count 2 2006.168.08:15:21.42#ibcon#about to read 5, iclass 24, count 2 2006.168.08:15:21.42#ibcon#read 5, iclass 24, count 2 2006.168.08:15:21.42#ibcon#about to read 6, iclass 24, count 2 2006.168.08:15:21.42#ibcon#read 6, iclass 24, count 2 2006.168.08:15:21.42#ibcon#end of sib2, iclass 24, count 2 2006.168.08:15:21.42#ibcon#*after write, iclass 24, count 2 2006.168.08:15:21.42#ibcon#*before return 0, iclass 24, count 2 2006.168.08:15:21.42#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:15:21.42#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:15:21.42#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.168.08:15:21.42#ibcon#ireg 7 cls_cnt 0 2006.168.08:15:21.42#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:15:21.54#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:15:21.54#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:15:21.54#ibcon#enter wrdev, iclass 24, count 0 2006.168.08:15:21.54#ibcon#first serial, iclass 24, count 0 2006.168.08:15:21.54#ibcon#enter sib2, iclass 24, count 0 2006.168.08:15:21.54#ibcon#flushed, iclass 24, count 0 2006.168.08:15:21.54#ibcon#about to write, iclass 24, count 0 2006.168.08:15:21.54#ibcon#wrote, iclass 24, count 0 2006.168.08:15:21.54#ibcon#about to read 3, iclass 24, count 0 2006.168.08:15:21.56#ibcon#read 3, iclass 24, count 0 2006.168.08:15:21.56#ibcon#about to read 4, iclass 24, count 0 2006.168.08:15:21.56#ibcon#read 4, iclass 24, count 0 2006.168.08:15:21.56#ibcon#about to read 5, iclass 24, count 0 2006.168.08:15:21.56#ibcon#read 5, iclass 24, count 0 2006.168.08:15:21.56#ibcon#about to read 6, iclass 24, count 0 2006.168.08:15:21.56#ibcon#read 6, iclass 24, count 0 2006.168.08:15:21.56#ibcon#end of sib2, iclass 24, count 0 2006.168.08:15:21.56#ibcon#*mode == 0, iclass 24, count 0 2006.168.08:15:21.56#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.168.08:15:21.56#ibcon#[27=USB\r\n] 2006.168.08:15:21.56#ibcon#*before write, iclass 24, count 0 2006.168.08:15:21.56#ibcon#enter sib2, iclass 24, count 0 2006.168.08:15:21.56#ibcon#flushed, iclass 24, count 0 2006.168.08:15:21.56#ibcon#about to write, iclass 24, count 0 2006.168.08:15:21.56#ibcon#wrote, iclass 24, count 0 2006.168.08:15:21.56#ibcon#about to read 3, iclass 24, count 0 2006.168.08:15:21.59#ibcon#read 3, iclass 24, count 0 2006.168.08:15:21.59#ibcon#about to read 4, iclass 24, count 0 2006.168.08:15:21.59#ibcon#read 4, iclass 24, count 0 2006.168.08:15:21.59#ibcon#about to read 5, iclass 24, count 0 2006.168.08:15:21.59#ibcon#read 5, iclass 24, count 0 2006.168.08:15:21.59#ibcon#about to read 6, iclass 24, count 0 2006.168.08:15:21.59#ibcon#read 6, iclass 24, count 0 2006.168.08:15:21.59#ibcon#end of sib2, iclass 24, count 0 2006.168.08:15:21.59#ibcon#*after write, iclass 24, count 0 2006.168.08:15:21.59#ibcon#*before return 0, iclass 24, count 0 2006.168.08:15:21.59#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:15:21.59#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:15:21.59#ibcon#about to clear, iclass 24 cls_cnt 0 2006.168.08:15:21.59#ibcon#cleared, iclass 24 cls_cnt 0 2006.168.08:15:21.59$vc4f8/vblo=4,712.99 2006.168.08:15:21.59#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.168.08:15:21.59#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.168.08:15:21.59#ibcon#ireg 17 cls_cnt 0 2006.168.08:15:21.59#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:15:21.59#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:15:21.59#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:15:21.59#ibcon#enter wrdev, iclass 26, count 0 2006.168.08:15:21.59#ibcon#first serial, iclass 26, count 0 2006.168.08:15:21.59#ibcon#enter sib2, iclass 26, count 0 2006.168.08:15:21.59#ibcon#flushed, iclass 26, count 0 2006.168.08:15:21.59#ibcon#about to write, iclass 26, count 0 2006.168.08:15:21.59#ibcon#wrote, iclass 26, count 0 2006.168.08:15:21.59#ibcon#about to read 3, iclass 26, count 0 2006.168.08:15:21.61#ibcon#read 3, iclass 26, count 0 2006.168.08:15:21.61#ibcon#about to read 4, iclass 26, count 0 2006.168.08:15:21.61#ibcon#read 4, iclass 26, count 0 2006.168.08:15:21.61#ibcon#about to read 5, iclass 26, count 0 2006.168.08:15:21.61#ibcon#read 5, iclass 26, count 0 2006.168.08:15:21.61#ibcon#about to read 6, iclass 26, count 0 2006.168.08:15:21.61#ibcon#read 6, iclass 26, count 0 2006.168.08:15:21.61#ibcon#end of sib2, iclass 26, count 0 2006.168.08:15:21.61#ibcon#*mode == 0, iclass 26, count 0 2006.168.08:15:21.61#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.168.08:15:21.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.08:15:21.61#ibcon#*before write, iclass 26, count 0 2006.168.08:15:21.61#ibcon#enter sib2, iclass 26, count 0 2006.168.08:15:21.61#ibcon#flushed, iclass 26, count 0 2006.168.08:15:21.61#ibcon#about to write, iclass 26, count 0 2006.168.08:15:21.61#ibcon#wrote, iclass 26, count 0 2006.168.08:15:21.61#ibcon#about to read 3, iclass 26, count 0 2006.168.08:15:21.65#ibcon#read 3, iclass 26, count 0 2006.168.08:15:21.65#ibcon#about to read 4, iclass 26, count 0 2006.168.08:15:21.65#ibcon#read 4, iclass 26, count 0 2006.168.08:15:21.65#ibcon#about to read 5, iclass 26, count 0 2006.168.08:15:21.65#ibcon#read 5, iclass 26, count 0 2006.168.08:15:21.65#ibcon#about to read 6, iclass 26, count 0 2006.168.08:15:21.65#ibcon#read 6, iclass 26, count 0 2006.168.08:15:21.65#ibcon#end of sib2, iclass 26, count 0 2006.168.08:15:21.65#ibcon#*after write, iclass 26, count 0 2006.168.08:15:21.65#ibcon#*before return 0, iclass 26, count 0 2006.168.08:15:21.65#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:15:21.65#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:15:21.65#ibcon#about to clear, iclass 26 cls_cnt 0 2006.168.08:15:21.65#ibcon#cleared, iclass 26 cls_cnt 0 2006.168.08:15:21.65$vc4f8/vb=4,4 2006.168.08:15:21.65#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.168.08:15:21.65#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.168.08:15:21.65#ibcon#ireg 11 cls_cnt 2 2006.168.08:15:21.65#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:15:21.71#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:15:21.71#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:15:21.71#ibcon#enter wrdev, iclass 28, count 2 2006.168.08:15:21.71#ibcon#first serial, iclass 28, count 2 2006.168.08:15:21.71#ibcon#enter sib2, iclass 28, count 2 2006.168.08:15:21.71#ibcon#flushed, iclass 28, count 2 2006.168.08:15:21.71#ibcon#about to write, iclass 28, count 2 2006.168.08:15:21.71#ibcon#wrote, iclass 28, count 2 2006.168.08:15:21.71#ibcon#about to read 3, iclass 28, count 2 2006.168.08:15:21.73#ibcon#read 3, iclass 28, count 2 2006.168.08:15:21.73#ibcon#about to read 4, iclass 28, count 2 2006.168.08:15:21.73#ibcon#read 4, iclass 28, count 2 2006.168.08:15:21.73#ibcon#about to read 5, iclass 28, count 2 2006.168.08:15:21.73#ibcon#read 5, iclass 28, count 2 2006.168.08:15:21.73#ibcon#about to read 6, iclass 28, count 2 2006.168.08:15:21.73#ibcon#read 6, iclass 28, count 2 2006.168.08:15:21.73#ibcon#end of sib2, iclass 28, count 2 2006.168.08:15:21.73#ibcon#*mode == 0, iclass 28, count 2 2006.168.08:15:21.73#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.168.08:15:21.73#ibcon#[27=AT04-04\r\n] 2006.168.08:15:21.73#ibcon#*before write, iclass 28, count 2 2006.168.08:15:21.73#ibcon#enter sib2, iclass 28, count 2 2006.168.08:15:21.73#ibcon#flushed, iclass 28, count 2 2006.168.08:15:21.73#ibcon#about to write, iclass 28, count 2 2006.168.08:15:21.73#ibcon#wrote, iclass 28, count 2 2006.168.08:15:21.73#ibcon#about to read 3, iclass 28, count 2 2006.168.08:15:21.76#ibcon#read 3, iclass 28, count 2 2006.168.08:15:21.76#ibcon#about to read 4, iclass 28, count 2 2006.168.08:15:21.76#ibcon#read 4, iclass 28, count 2 2006.168.08:15:21.76#ibcon#about to read 5, iclass 28, count 2 2006.168.08:15:21.76#ibcon#read 5, iclass 28, count 2 2006.168.08:15:21.76#ibcon#about to read 6, iclass 28, count 2 2006.168.08:15:21.76#ibcon#read 6, iclass 28, count 2 2006.168.08:15:21.76#ibcon#end of sib2, iclass 28, count 2 2006.168.08:15:21.76#ibcon#*after write, iclass 28, count 2 2006.168.08:15:21.76#ibcon#*before return 0, iclass 28, count 2 2006.168.08:15:21.76#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:15:21.76#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:15:21.76#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.168.08:15:21.76#ibcon#ireg 7 cls_cnt 0 2006.168.08:15:21.76#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:15:21.88#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:15:21.88#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:15:21.88#ibcon#enter wrdev, iclass 28, count 0 2006.168.08:15:21.88#ibcon#first serial, iclass 28, count 0 2006.168.08:15:21.88#ibcon#enter sib2, iclass 28, count 0 2006.168.08:15:21.88#ibcon#flushed, iclass 28, count 0 2006.168.08:15:21.88#ibcon#about to write, iclass 28, count 0 2006.168.08:15:21.88#ibcon#wrote, iclass 28, count 0 2006.168.08:15:21.88#ibcon#about to read 3, iclass 28, count 0 2006.168.08:15:21.90#ibcon#read 3, iclass 28, count 0 2006.168.08:15:21.90#ibcon#about to read 4, iclass 28, count 0 2006.168.08:15:21.90#ibcon#read 4, iclass 28, count 0 2006.168.08:15:21.90#ibcon#about to read 5, iclass 28, count 0 2006.168.08:15:21.90#ibcon#read 5, iclass 28, count 0 2006.168.08:15:21.90#ibcon#about to read 6, iclass 28, count 0 2006.168.08:15:21.90#ibcon#read 6, iclass 28, count 0 2006.168.08:15:21.90#ibcon#end of sib2, iclass 28, count 0 2006.168.08:15:21.90#ibcon#*mode == 0, iclass 28, count 0 2006.168.08:15:21.90#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.168.08:15:21.90#ibcon#[27=USB\r\n] 2006.168.08:15:21.90#ibcon#*before write, iclass 28, count 0 2006.168.08:15:21.90#ibcon#enter sib2, iclass 28, count 0 2006.168.08:15:21.90#ibcon#flushed, iclass 28, count 0 2006.168.08:15:21.90#ibcon#about to write, iclass 28, count 0 2006.168.08:15:21.90#ibcon#wrote, iclass 28, count 0 2006.168.08:15:21.90#ibcon#about to read 3, iclass 28, count 0 2006.168.08:15:21.93#ibcon#read 3, iclass 28, count 0 2006.168.08:15:21.93#ibcon#about to read 4, iclass 28, count 0 2006.168.08:15:21.93#ibcon#read 4, iclass 28, count 0 2006.168.08:15:21.93#ibcon#about to read 5, iclass 28, count 0 2006.168.08:15:21.93#ibcon#read 5, iclass 28, count 0 2006.168.08:15:21.93#ibcon#about to read 6, iclass 28, count 0 2006.168.08:15:21.93#ibcon#read 6, iclass 28, count 0 2006.168.08:15:21.93#ibcon#end of sib2, iclass 28, count 0 2006.168.08:15:21.93#ibcon#*after write, iclass 28, count 0 2006.168.08:15:21.93#ibcon#*before return 0, iclass 28, count 0 2006.168.08:15:21.93#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:15:21.93#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:15:21.93#ibcon#about to clear, iclass 28 cls_cnt 0 2006.168.08:15:21.93#ibcon#cleared, iclass 28 cls_cnt 0 2006.168.08:15:21.93$vc4f8/vblo=5,744.99 2006.168.08:15:21.93#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.168.08:15:21.93#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.168.08:15:21.93#ibcon#ireg 17 cls_cnt 0 2006.168.08:15:21.93#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:15:21.93#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:15:21.93#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:15:21.93#ibcon#enter wrdev, iclass 30, count 0 2006.168.08:15:21.93#ibcon#first serial, iclass 30, count 0 2006.168.08:15:21.93#ibcon#enter sib2, iclass 30, count 0 2006.168.08:15:21.93#ibcon#flushed, iclass 30, count 0 2006.168.08:15:21.93#ibcon#about to write, iclass 30, count 0 2006.168.08:15:21.93#ibcon#wrote, iclass 30, count 0 2006.168.08:15:21.93#ibcon#about to read 3, iclass 30, count 0 2006.168.08:15:21.95#ibcon#read 3, iclass 30, count 0 2006.168.08:15:21.95#ibcon#about to read 4, iclass 30, count 0 2006.168.08:15:21.95#ibcon#read 4, iclass 30, count 0 2006.168.08:15:21.95#ibcon#about to read 5, iclass 30, count 0 2006.168.08:15:21.95#ibcon#read 5, iclass 30, count 0 2006.168.08:15:21.95#ibcon#about to read 6, iclass 30, count 0 2006.168.08:15:21.95#ibcon#read 6, iclass 30, count 0 2006.168.08:15:21.95#ibcon#end of sib2, iclass 30, count 0 2006.168.08:15:21.95#ibcon#*mode == 0, iclass 30, count 0 2006.168.08:15:21.95#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.168.08:15:21.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.08:15:21.95#ibcon#*before write, iclass 30, count 0 2006.168.08:15:21.95#ibcon#enter sib2, iclass 30, count 0 2006.168.08:15:21.95#ibcon#flushed, iclass 30, count 0 2006.168.08:15:21.95#ibcon#about to write, iclass 30, count 0 2006.168.08:15:21.95#ibcon#wrote, iclass 30, count 0 2006.168.08:15:21.95#ibcon#about to read 3, iclass 30, count 0 2006.168.08:15:21.99#ibcon#read 3, iclass 30, count 0 2006.168.08:15:21.99#ibcon#about to read 4, iclass 30, count 0 2006.168.08:15:21.99#ibcon#read 4, iclass 30, count 0 2006.168.08:15:21.99#ibcon#about to read 5, iclass 30, count 0 2006.168.08:15:21.99#ibcon#read 5, iclass 30, count 0 2006.168.08:15:21.99#ibcon#about to read 6, iclass 30, count 0 2006.168.08:15:21.99#ibcon#read 6, iclass 30, count 0 2006.168.08:15:21.99#ibcon#end of sib2, iclass 30, count 0 2006.168.08:15:21.99#ibcon#*after write, iclass 30, count 0 2006.168.08:15:21.99#ibcon#*before return 0, iclass 30, count 0 2006.168.08:15:21.99#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:15:21.99#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:15:21.99#ibcon#about to clear, iclass 30 cls_cnt 0 2006.168.08:15:21.99#ibcon#cleared, iclass 30 cls_cnt 0 2006.168.08:15:21.99$vc4f8/vb=5,4 2006.168.08:15:21.99#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.168.08:15:21.99#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.168.08:15:21.99#ibcon#ireg 11 cls_cnt 2 2006.168.08:15:21.99#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:15:22.05#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:15:22.05#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:15:22.05#ibcon#enter wrdev, iclass 32, count 2 2006.168.08:15:22.05#ibcon#first serial, iclass 32, count 2 2006.168.08:15:22.05#ibcon#enter sib2, iclass 32, count 2 2006.168.08:15:22.05#ibcon#flushed, iclass 32, count 2 2006.168.08:15:22.05#ibcon#about to write, iclass 32, count 2 2006.168.08:15:22.05#ibcon#wrote, iclass 32, count 2 2006.168.08:15:22.05#ibcon#about to read 3, iclass 32, count 2 2006.168.08:15:22.07#ibcon#read 3, iclass 32, count 2 2006.168.08:15:22.07#ibcon#about to read 4, iclass 32, count 2 2006.168.08:15:22.07#ibcon#read 4, iclass 32, count 2 2006.168.08:15:22.07#ibcon#about to read 5, iclass 32, count 2 2006.168.08:15:22.07#ibcon#read 5, iclass 32, count 2 2006.168.08:15:22.07#ibcon#about to read 6, iclass 32, count 2 2006.168.08:15:22.07#ibcon#read 6, iclass 32, count 2 2006.168.08:15:22.07#ibcon#end of sib2, iclass 32, count 2 2006.168.08:15:22.07#ibcon#*mode == 0, iclass 32, count 2 2006.168.08:15:22.07#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.168.08:15:22.07#ibcon#[27=AT05-04\r\n] 2006.168.08:15:22.07#ibcon#*before write, iclass 32, count 2 2006.168.08:15:22.07#ibcon#enter sib2, iclass 32, count 2 2006.168.08:15:22.07#ibcon#flushed, iclass 32, count 2 2006.168.08:15:22.07#ibcon#about to write, iclass 32, count 2 2006.168.08:15:22.07#ibcon#wrote, iclass 32, count 2 2006.168.08:15:22.07#ibcon#about to read 3, iclass 32, count 2 2006.168.08:15:22.10#ibcon#read 3, iclass 32, count 2 2006.168.08:15:22.10#ibcon#about to read 4, iclass 32, count 2 2006.168.08:15:22.10#ibcon#read 4, iclass 32, count 2 2006.168.08:15:22.10#ibcon#about to read 5, iclass 32, count 2 2006.168.08:15:22.10#ibcon#read 5, iclass 32, count 2 2006.168.08:15:22.10#ibcon#about to read 6, iclass 32, count 2 2006.168.08:15:22.10#ibcon#read 6, iclass 32, count 2 2006.168.08:15:22.10#ibcon#end of sib2, iclass 32, count 2 2006.168.08:15:22.10#ibcon#*after write, iclass 32, count 2 2006.168.08:15:22.10#ibcon#*before return 0, iclass 32, count 2 2006.168.08:15:22.10#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:15:22.10#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:15:22.10#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.168.08:15:22.10#ibcon#ireg 7 cls_cnt 0 2006.168.08:15:22.10#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:15:22.22#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:15:22.22#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:15:22.22#ibcon#enter wrdev, iclass 32, count 0 2006.168.08:15:22.22#ibcon#first serial, iclass 32, count 0 2006.168.08:15:22.22#ibcon#enter sib2, iclass 32, count 0 2006.168.08:15:22.22#ibcon#flushed, iclass 32, count 0 2006.168.08:15:22.22#ibcon#about to write, iclass 32, count 0 2006.168.08:15:22.22#ibcon#wrote, iclass 32, count 0 2006.168.08:15:22.22#ibcon#about to read 3, iclass 32, count 0 2006.168.08:15:22.24#ibcon#read 3, iclass 32, count 0 2006.168.08:15:22.24#ibcon#about to read 4, iclass 32, count 0 2006.168.08:15:22.24#ibcon#read 4, iclass 32, count 0 2006.168.08:15:22.24#ibcon#about to read 5, iclass 32, count 0 2006.168.08:15:22.24#ibcon#read 5, iclass 32, count 0 2006.168.08:15:22.24#ibcon#about to read 6, iclass 32, count 0 2006.168.08:15:22.24#ibcon#read 6, iclass 32, count 0 2006.168.08:15:22.24#ibcon#end of sib2, iclass 32, count 0 2006.168.08:15:22.24#ibcon#*mode == 0, iclass 32, count 0 2006.168.08:15:22.24#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.168.08:15:22.24#ibcon#[27=USB\r\n] 2006.168.08:15:22.24#ibcon#*before write, iclass 32, count 0 2006.168.08:15:22.24#ibcon#enter sib2, iclass 32, count 0 2006.168.08:15:22.24#ibcon#flushed, iclass 32, count 0 2006.168.08:15:22.24#ibcon#about to write, iclass 32, count 0 2006.168.08:15:22.24#ibcon#wrote, iclass 32, count 0 2006.168.08:15:22.24#ibcon#about to read 3, iclass 32, count 0 2006.168.08:15:22.27#ibcon#read 3, iclass 32, count 0 2006.168.08:15:22.27#ibcon#about to read 4, iclass 32, count 0 2006.168.08:15:22.27#ibcon#read 4, iclass 32, count 0 2006.168.08:15:22.27#ibcon#about to read 5, iclass 32, count 0 2006.168.08:15:22.27#ibcon#read 5, iclass 32, count 0 2006.168.08:15:22.27#ibcon#about to read 6, iclass 32, count 0 2006.168.08:15:22.27#ibcon#read 6, iclass 32, count 0 2006.168.08:15:22.27#ibcon#end of sib2, iclass 32, count 0 2006.168.08:15:22.27#ibcon#*after write, iclass 32, count 0 2006.168.08:15:22.27#ibcon#*before return 0, iclass 32, count 0 2006.168.08:15:22.27#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:15:22.27#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:15:22.27#ibcon#about to clear, iclass 32 cls_cnt 0 2006.168.08:15:22.27#ibcon#cleared, iclass 32 cls_cnt 0 2006.168.08:15:22.27$vc4f8/vblo=6,752.99 2006.168.08:15:22.27#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.168.08:15:22.27#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.168.08:15:22.27#ibcon#ireg 17 cls_cnt 0 2006.168.08:15:22.27#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:15:22.27#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:15:22.27#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:15:22.27#ibcon#enter wrdev, iclass 34, count 0 2006.168.08:15:22.27#ibcon#first serial, iclass 34, count 0 2006.168.08:15:22.27#ibcon#enter sib2, iclass 34, count 0 2006.168.08:15:22.27#ibcon#flushed, iclass 34, count 0 2006.168.08:15:22.27#ibcon#about to write, iclass 34, count 0 2006.168.08:15:22.27#ibcon#wrote, iclass 34, count 0 2006.168.08:15:22.27#ibcon#about to read 3, iclass 34, count 0 2006.168.08:15:22.29#ibcon#read 3, iclass 34, count 0 2006.168.08:15:22.29#ibcon#about to read 4, iclass 34, count 0 2006.168.08:15:22.29#ibcon#read 4, iclass 34, count 0 2006.168.08:15:22.29#ibcon#about to read 5, iclass 34, count 0 2006.168.08:15:22.29#ibcon#read 5, iclass 34, count 0 2006.168.08:15:22.29#ibcon#about to read 6, iclass 34, count 0 2006.168.08:15:22.29#ibcon#read 6, iclass 34, count 0 2006.168.08:15:22.29#ibcon#end of sib2, iclass 34, count 0 2006.168.08:15:22.29#ibcon#*mode == 0, iclass 34, count 0 2006.168.08:15:22.29#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.168.08:15:22.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.08:15:22.29#ibcon#*before write, iclass 34, count 0 2006.168.08:15:22.29#ibcon#enter sib2, iclass 34, count 0 2006.168.08:15:22.29#ibcon#flushed, iclass 34, count 0 2006.168.08:15:22.29#ibcon#about to write, iclass 34, count 0 2006.168.08:15:22.29#ibcon#wrote, iclass 34, count 0 2006.168.08:15:22.29#ibcon#about to read 3, iclass 34, count 0 2006.168.08:15:22.33#ibcon#read 3, iclass 34, count 0 2006.168.08:15:22.33#ibcon#about to read 4, iclass 34, count 0 2006.168.08:15:22.33#ibcon#read 4, iclass 34, count 0 2006.168.08:15:22.33#ibcon#about to read 5, iclass 34, count 0 2006.168.08:15:22.33#ibcon#read 5, iclass 34, count 0 2006.168.08:15:22.33#ibcon#about to read 6, iclass 34, count 0 2006.168.08:15:22.33#ibcon#read 6, iclass 34, count 0 2006.168.08:15:22.33#ibcon#end of sib2, iclass 34, count 0 2006.168.08:15:22.33#ibcon#*after write, iclass 34, count 0 2006.168.08:15:22.33#ibcon#*before return 0, iclass 34, count 0 2006.168.08:15:22.33#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:15:22.33#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:15:22.33#ibcon#about to clear, iclass 34 cls_cnt 0 2006.168.08:15:22.33#ibcon#cleared, iclass 34 cls_cnt 0 2006.168.08:15:22.33$vc4f8/vb=6,4 2006.168.08:15:22.33#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.168.08:15:22.33#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.168.08:15:22.33#ibcon#ireg 11 cls_cnt 2 2006.168.08:15:22.33#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:15:22.39#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:15:22.39#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:15:22.39#ibcon#enter wrdev, iclass 36, count 2 2006.168.08:15:22.39#ibcon#first serial, iclass 36, count 2 2006.168.08:15:22.39#ibcon#enter sib2, iclass 36, count 2 2006.168.08:15:22.39#ibcon#flushed, iclass 36, count 2 2006.168.08:15:22.39#ibcon#about to write, iclass 36, count 2 2006.168.08:15:22.39#ibcon#wrote, iclass 36, count 2 2006.168.08:15:22.39#ibcon#about to read 3, iclass 36, count 2 2006.168.08:15:22.41#ibcon#read 3, iclass 36, count 2 2006.168.08:15:22.41#ibcon#about to read 4, iclass 36, count 2 2006.168.08:15:22.41#ibcon#read 4, iclass 36, count 2 2006.168.08:15:22.41#ibcon#about to read 5, iclass 36, count 2 2006.168.08:15:22.41#ibcon#read 5, iclass 36, count 2 2006.168.08:15:22.41#ibcon#about to read 6, iclass 36, count 2 2006.168.08:15:22.41#ibcon#read 6, iclass 36, count 2 2006.168.08:15:22.41#ibcon#end of sib2, iclass 36, count 2 2006.168.08:15:22.41#ibcon#*mode == 0, iclass 36, count 2 2006.168.08:15:22.41#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.168.08:15:22.41#ibcon#[27=AT06-04\r\n] 2006.168.08:15:22.41#ibcon#*before write, iclass 36, count 2 2006.168.08:15:22.41#ibcon#enter sib2, iclass 36, count 2 2006.168.08:15:22.41#ibcon#flushed, iclass 36, count 2 2006.168.08:15:22.41#ibcon#about to write, iclass 36, count 2 2006.168.08:15:22.41#ibcon#wrote, iclass 36, count 2 2006.168.08:15:22.41#ibcon#about to read 3, iclass 36, count 2 2006.168.08:15:22.44#ibcon#read 3, iclass 36, count 2 2006.168.08:15:22.44#ibcon#about to read 4, iclass 36, count 2 2006.168.08:15:22.44#ibcon#read 4, iclass 36, count 2 2006.168.08:15:22.44#ibcon#about to read 5, iclass 36, count 2 2006.168.08:15:22.44#ibcon#read 5, iclass 36, count 2 2006.168.08:15:22.44#ibcon#about to read 6, iclass 36, count 2 2006.168.08:15:22.44#ibcon#read 6, iclass 36, count 2 2006.168.08:15:22.44#ibcon#end of sib2, iclass 36, count 2 2006.168.08:15:22.44#ibcon#*after write, iclass 36, count 2 2006.168.08:15:22.44#ibcon#*before return 0, iclass 36, count 2 2006.168.08:15:22.44#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:15:22.44#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:15:22.44#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.168.08:15:22.44#ibcon#ireg 7 cls_cnt 0 2006.168.08:15:22.44#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:15:22.56#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:15:22.56#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:15:22.56#ibcon#enter wrdev, iclass 36, count 0 2006.168.08:15:22.56#ibcon#first serial, iclass 36, count 0 2006.168.08:15:22.56#ibcon#enter sib2, iclass 36, count 0 2006.168.08:15:22.56#ibcon#flushed, iclass 36, count 0 2006.168.08:15:22.56#ibcon#about to write, iclass 36, count 0 2006.168.08:15:22.56#ibcon#wrote, iclass 36, count 0 2006.168.08:15:22.56#ibcon#about to read 3, iclass 36, count 0 2006.168.08:15:22.58#ibcon#read 3, iclass 36, count 0 2006.168.08:15:22.58#ibcon#about to read 4, iclass 36, count 0 2006.168.08:15:22.58#ibcon#read 4, iclass 36, count 0 2006.168.08:15:22.58#ibcon#about to read 5, iclass 36, count 0 2006.168.08:15:22.58#ibcon#read 5, iclass 36, count 0 2006.168.08:15:22.58#ibcon#about to read 6, iclass 36, count 0 2006.168.08:15:22.58#ibcon#read 6, iclass 36, count 0 2006.168.08:15:22.58#ibcon#end of sib2, iclass 36, count 0 2006.168.08:15:22.58#ibcon#*mode == 0, iclass 36, count 0 2006.168.08:15:22.58#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.168.08:15:22.58#ibcon#[27=USB\r\n] 2006.168.08:15:22.58#ibcon#*before write, iclass 36, count 0 2006.168.08:15:22.58#ibcon#enter sib2, iclass 36, count 0 2006.168.08:15:22.58#ibcon#flushed, iclass 36, count 0 2006.168.08:15:22.58#ibcon#about to write, iclass 36, count 0 2006.168.08:15:22.58#ibcon#wrote, iclass 36, count 0 2006.168.08:15:22.58#ibcon#about to read 3, iclass 36, count 0 2006.168.08:15:22.61#ibcon#read 3, iclass 36, count 0 2006.168.08:15:22.61#ibcon#about to read 4, iclass 36, count 0 2006.168.08:15:22.61#ibcon#read 4, iclass 36, count 0 2006.168.08:15:22.61#ibcon#about to read 5, iclass 36, count 0 2006.168.08:15:22.61#ibcon#read 5, iclass 36, count 0 2006.168.08:15:22.61#ibcon#about to read 6, iclass 36, count 0 2006.168.08:15:22.61#ibcon#read 6, iclass 36, count 0 2006.168.08:15:22.61#ibcon#end of sib2, iclass 36, count 0 2006.168.08:15:22.61#ibcon#*after write, iclass 36, count 0 2006.168.08:15:22.61#ibcon#*before return 0, iclass 36, count 0 2006.168.08:15:22.61#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:15:22.61#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:15:22.61#ibcon#about to clear, iclass 36 cls_cnt 0 2006.168.08:15:22.61#ibcon#cleared, iclass 36 cls_cnt 0 2006.168.08:15:22.61$vc4f8/vabw=wide 2006.168.08:15:22.61#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.168.08:15:22.61#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.168.08:15:22.61#ibcon#ireg 8 cls_cnt 0 2006.168.08:15:22.61#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:15:22.61#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:15:22.61#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:15:22.61#ibcon#enter wrdev, iclass 38, count 0 2006.168.08:15:22.61#ibcon#first serial, iclass 38, count 0 2006.168.08:15:22.61#ibcon#enter sib2, iclass 38, count 0 2006.168.08:15:22.61#ibcon#flushed, iclass 38, count 0 2006.168.08:15:22.61#ibcon#about to write, iclass 38, count 0 2006.168.08:15:22.61#ibcon#wrote, iclass 38, count 0 2006.168.08:15:22.61#ibcon#about to read 3, iclass 38, count 0 2006.168.08:15:22.63#ibcon#read 3, iclass 38, count 0 2006.168.08:15:22.63#ibcon#about to read 4, iclass 38, count 0 2006.168.08:15:22.63#ibcon#read 4, iclass 38, count 0 2006.168.08:15:22.63#ibcon#about to read 5, iclass 38, count 0 2006.168.08:15:22.63#ibcon#read 5, iclass 38, count 0 2006.168.08:15:22.63#ibcon#about to read 6, iclass 38, count 0 2006.168.08:15:22.63#ibcon#read 6, iclass 38, count 0 2006.168.08:15:22.63#ibcon#end of sib2, iclass 38, count 0 2006.168.08:15:22.63#ibcon#*mode == 0, iclass 38, count 0 2006.168.08:15:22.63#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.168.08:15:22.63#ibcon#[25=BW32\r\n] 2006.168.08:15:22.63#ibcon#*before write, iclass 38, count 0 2006.168.08:15:22.63#ibcon#enter sib2, iclass 38, count 0 2006.168.08:15:22.63#ibcon#flushed, iclass 38, count 0 2006.168.08:15:22.63#ibcon#about to write, iclass 38, count 0 2006.168.08:15:22.63#ibcon#wrote, iclass 38, count 0 2006.168.08:15:22.63#ibcon#about to read 3, iclass 38, count 0 2006.168.08:15:22.66#ibcon#read 3, iclass 38, count 0 2006.168.08:15:22.66#ibcon#about to read 4, iclass 38, count 0 2006.168.08:15:22.66#ibcon#read 4, iclass 38, count 0 2006.168.08:15:22.66#ibcon#about to read 5, iclass 38, count 0 2006.168.08:15:22.66#ibcon#read 5, iclass 38, count 0 2006.168.08:15:22.66#ibcon#about to read 6, iclass 38, count 0 2006.168.08:15:22.66#ibcon#read 6, iclass 38, count 0 2006.168.08:15:22.66#ibcon#end of sib2, iclass 38, count 0 2006.168.08:15:22.66#ibcon#*after write, iclass 38, count 0 2006.168.08:15:22.66#ibcon#*before return 0, iclass 38, count 0 2006.168.08:15:22.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:15:22.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:15:22.66#ibcon#about to clear, iclass 38 cls_cnt 0 2006.168.08:15:22.66#ibcon#cleared, iclass 38 cls_cnt 0 2006.168.08:15:22.66$vc4f8/vbbw=wide 2006.168.08:15:22.66#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.168.08:15:22.66#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.168.08:15:22.66#ibcon#ireg 8 cls_cnt 0 2006.168.08:15:22.66#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:15:22.73#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:15:22.73#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:15:22.73#ibcon#enter wrdev, iclass 40, count 0 2006.168.08:15:22.73#ibcon#first serial, iclass 40, count 0 2006.168.08:15:22.73#ibcon#enter sib2, iclass 40, count 0 2006.168.08:15:22.73#ibcon#flushed, iclass 40, count 0 2006.168.08:15:22.73#ibcon#about to write, iclass 40, count 0 2006.168.08:15:22.73#ibcon#wrote, iclass 40, count 0 2006.168.08:15:22.73#ibcon#about to read 3, iclass 40, count 0 2006.168.08:15:22.75#ibcon#read 3, iclass 40, count 0 2006.168.08:15:22.75#ibcon#about to read 4, iclass 40, count 0 2006.168.08:15:22.75#ibcon#read 4, iclass 40, count 0 2006.168.08:15:22.75#ibcon#about to read 5, iclass 40, count 0 2006.168.08:15:22.75#ibcon#read 5, iclass 40, count 0 2006.168.08:15:22.75#ibcon#about to read 6, iclass 40, count 0 2006.168.08:15:22.75#ibcon#read 6, iclass 40, count 0 2006.168.08:15:22.75#ibcon#end of sib2, iclass 40, count 0 2006.168.08:15:22.75#ibcon#*mode == 0, iclass 40, count 0 2006.168.08:15:22.75#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.168.08:15:22.75#ibcon#[27=BW32\r\n] 2006.168.08:15:22.75#ibcon#*before write, iclass 40, count 0 2006.168.08:15:22.75#ibcon#enter sib2, iclass 40, count 0 2006.168.08:15:22.75#ibcon#flushed, iclass 40, count 0 2006.168.08:15:22.75#ibcon#about to write, iclass 40, count 0 2006.168.08:15:22.75#ibcon#wrote, iclass 40, count 0 2006.168.08:15:22.75#ibcon#about to read 3, iclass 40, count 0 2006.168.08:15:22.78#ibcon#read 3, iclass 40, count 0 2006.168.08:15:22.78#ibcon#about to read 4, iclass 40, count 0 2006.168.08:15:22.78#ibcon#read 4, iclass 40, count 0 2006.168.08:15:22.78#ibcon#about to read 5, iclass 40, count 0 2006.168.08:15:22.78#ibcon#read 5, iclass 40, count 0 2006.168.08:15:22.78#ibcon#about to read 6, iclass 40, count 0 2006.168.08:15:22.78#ibcon#read 6, iclass 40, count 0 2006.168.08:15:22.78#ibcon#end of sib2, iclass 40, count 0 2006.168.08:15:22.78#ibcon#*after write, iclass 40, count 0 2006.168.08:15:22.78#ibcon#*before return 0, iclass 40, count 0 2006.168.08:15:22.78#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:15:22.78#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:15:22.78#ibcon#about to clear, iclass 40 cls_cnt 0 2006.168.08:15:22.78#ibcon#cleared, iclass 40 cls_cnt 0 2006.168.08:15:22.78$4f8m12a/ifd4f 2006.168.08:15:22.78$ifd4f/lo= 2006.168.08:15:22.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.08:15:22.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.08:15:22.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.08:15:22.78$ifd4f/patch= 2006.168.08:15:22.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.08:15:22.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.08:15:22.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.08:15:22.78$4f8m12a/"form=m,16.000,1:2 2006.168.08:15:22.78$4f8m12a/"tpicd 2006.168.08:15:22.78$4f8m12a/echo=off 2006.168.08:15:22.78$4f8m12a/xlog=off 2006.168.08:15:22.78:!2006.168.08:15:50 2006.168.08:15:30.14#trakl#Source acquired 2006.168.08:15:32.14#flagr#flagr/antenna,acquired 2006.168.08:15:50.00:preob 2006.168.08:15:51.14/onsource/TRACKING 2006.168.08:15:51.14:!2006.168.08:16:00 2006.168.08:16:00.00:data_valid=on 2006.168.08:16:00.00:midob 2006.168.08:16:00.14/onsource/TRACKING 2006.168.08:16:00.14/wx/26.93,1004.6,75 2006.168.08:16:00.33/cable/+6.4713E-03 2006.168.08:16:01.42/va/01,08,usb,yes,28,30 2006.168.08:16:01.42/va/02,07,usb,yes,29,30 2006.168.08:16:01.42/va/03,06,usb,yes,30,30 2006.168.08:16:01.42/va/04,07,usb,yes,29,32 2006.168.08:16:01.42/va/05,07,usb,yes,29,31 2006.168.08:16:01.42/va/06,06,usb,yes,29,28 2006.168.08:16:01.42/va/07,06,usb,yes,29,29 2006.168.08:16:01.42/va/08,07,usb,yes,28,27 2006.168.08:16:01.65/valo/01,532.99,yes,locked 2006.168.08:16:01.65/valo/02,572.99,yes,locked 2006.168.08:16:01.65/valo/03,672.99,yes,locked 2006.168.08:16:01.65/valo/04,832.99,yes,locked 2006.168.08:16:01.65/valo/05,652.99,yes,locked 2006.168.08:16:01.65/valo/06,772.99,yes,locked 2006.168.08:16:01.65/valo/07,832.99,yes,locked 2006.168.08:16:01.65/valo/08,852.99,yes,locked 2006.168.08:16:02.74/vb/01,04,usb,yes,29,27 2006.168.08:16:02.74/vb/02,04,usb,yes,30,32 2006.168.08:16:02.74/vb/03,04,usb,yes,27,31 2006.168.08:16:02.74/vb/04,04,usb,yes,28,28 2006.168.08:16:02.74/vb/05,04,usb,yes,26,30 2006.168.08:16:02.74/vb/06,04,usb,yes,27,30 2006.168.08:16:02.74/vb/07,04,usb,yes,29,29 2006.168.08:16:02.74/vb/08,04,usb,yes,27,30 2006.168.08:16:02.97/vblo/01,632.99,yes,locked 2006.168.08:16:02.97/vblo/02,640.99,yes,locked 2006.168.08:16:02.97/vblo/03,656.99,yes,locked 2006.168.08:16:02.97/vblo/04,712.99,yes,locked 2006.168.08:16:02.97/vblo/05,744.99,yes,locked 2006.168.08:16:02.97/vblo/06,752.99,yes,locked 2006.168.08:16:02.97/vblo/07,734.99,yes,locked 2006.168.08:16:02.97/vblo/08,744.99,yes,locked 2006.168.08:16:03.12/vabw/8 2006.168.08:16:03.27/vbbw/8 2006.168.08:16:03.36/xfe/off,on,14.5 2006.168.08:16:03.76/ifatt/23,28,28,28 2006.168.08:16:04.08/fmout-gps/S +4.17E-07 2006.168.08:16:04.12:!2006.168.08:17:00 2006.168.08:17:00.00:data_valid=off 2006.168.08:17:00.00:postob 2006.168.08:17:00.18/cable/+6.4718E-03 2006.168.08:17:00.18/wx/26.91,1004.5,76 2006.168.08:17:01.08/fmout-gps/S +4.17E-07 2006.168.08:17:01.08:scan_name=168-0820,k06168,130 2006.168.08:17:01.08:source=0722+145,072516.81,142513.7,2000.0,ccw 2006.168.08:17:01.14#flagr#flagr/antenna,new-source 2006.168.08:17:02.14:checkk5 2006.168.08:17:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.168.08:17:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.168.08:17:03.28/chk_autoobs//k5ts3/ autoobs is running! 2006.168.08:17:03.65/chk_autoobs//k5ts4/ autoobs is running! 2006.168.08:17:04.02/chk_obsdata//k5ts1/T1680816??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.168.08:17:04.40/chk_obsdata//k5ts2/T1680816??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.168.08:17:04.77/chk_obsdata//k5ts3/T1680816??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.168.08:17:05.15/chk_obsdata//k5ts4/T1680816??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.168.08:17:05.85/k5log//k5ts1_log_newline 2006.168.08:17:06.56/k5log//k5ts2_log_newline 2006.168.08:17:07.26/k5log//k5ts3_log_newline 2006.168.08:17:07.95/k5log//k5ts4_log_newline 2006.168.08:17:07.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.08:17:07.97:4f8m12a=3 2006.168.08:17:07.97$4f8m12a/echo=on 2006.168.08:17:07.97$4f8m12a/pcalon 2006.168.08:17:07.97$pcalon/"no phase cal control is implemented here 2006.168.08:17:07.97$4f8m12a/"tpicd=stop 2006.168.08:17:07.97$4f8m12a/vc4f8 2006.168.08:17:07.97$vc4f8/valo=1,532.99 2006.168.08:17:07.98#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.168.08:17:07.98#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.168.08:17:07.98#ibcon#ireg 17 cls_cnt 0 2006.168.08:17:07.98#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:17:07.98#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:17:07.98#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:17:07.98#ibcon#enter wrdev, iclass 15, count 0 2006.168.08:17:07.98#ibcon#first serial, iclass 15, count 0 2006.168.08:17:07.98#ibcon#enter sib2, iclass 15, count 0 2006.168.08:17:07.98#ibcon#flushed, iclass 15, count 0 2006.168.08:17:07.98#ibcon#about to write, iclass 15, count 0 2006.168.08:17:07.98#ibcon#wrote, iclass 15, count 0 2006.168.08:17:07.98#ibcon#about to read 3, iclass 15, count 0 2006.168.08:17:08.02#ibcon#read 3, iclass 15, count 0 2006.168.08:17:08.02#ibcon#about to read 4, iclass 15, count 0 2006.168.08:17:08.02#ibcon#read 4, iclass 15, count 0 2006.168.08:17:08.02#ibcon#about to read 5, iclass 15, count 0 2006.168.08:17:08.02#ibcon#read 5, iclass 15, count 0 2006.168.08:17:08.02#ibcon#about to read 6, iclass 15, count 0 2006.168.08:17:08.02#ibcon#read 6, iclass 15, count 0 2006.168.08:17:08.02#ibcon#end of sib2, iclass 15, count 0 2006.168.08:17:08.02#ibcon#*mode == 0, iclass 15, count 0 2006.168.08:17:08.02#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.168.08:17:08.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.08:17:08.02#ibcon#*before write, iclass 15, count 0 2006.168.08:17:08.02#ibcon#enter sib2, iclass 15, count 0 2006.168.08:17:08.02#ibcon#flushed, iclass 15, count 0 2006.168.08:17:08.02#ibcon#about to write, iclass 15, count 0 2006.168.08:17:08.02#ibcon#wrote, iclass 15, count 0 2006.168.08:17:08.02#ibcon#about to read 3, iclass 15, count 0 2006.168.08:17:08.07#ibcon#read 3, iclass 15, count 0 2006.168.08:17:08.07#ibcon#about to read 4, iclass 15, count 0 2006.168.08:17:08.07#ibcon#read 4, iclass 15, count 0 2006.168.08:17:08.07#ibcon#about to read 5, iclass 15, count 0 2006.168.08:17:08.07#ibcon#read 5, iclass 15, count 0 2006.168.08:17:08.07#ibcon#about to read 6, iclass 15, count 0 2006.168.08:17:08.07#ibcon#read 6, iclass 15, count 0 2006.168.08:17:08.07#ibcon#end of sib2, iclass 15, count 0 2006.168.08:17:08.07#ibcon#*after write, iclass 15, count 0 2006.168.08:17:08.07#ibcon#*before return 0, iclass 15, count 0 2006.168.08:17:08.07#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:17:08.07#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:17:08.07#ibcon#about to clear, iclass 15 cls_cnt 0 2006.168.08:17:08.07#ibcon#cleared, iclass 15 cls_cnt 0 2006.168.08:17:08.07$vc4f8/va=1,8 2006.168.08:17:08.07#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.168.08:17:08.07#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.168.08:17:08.07#ibcon#ireg 11 cls_cnt 2 2006.168.08:17:08.07#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.168.08:17:08.07#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.168.08:17:08.07#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.168.08:17:08.07#ibcon#enter wrdev, iclass 17, count 2 2006.168.08:17:08.07#ibcon#first serial, iclass 17, count 2 2006.168.08:17:08.07#ibcon#enter sib2, iclass 17, count 2 2006.168.08:17:08.07#ibcon#flushed, iclass 17, count 2 2006.168.08:17:08.07#ibcon#about to write, iclass 17, count 2 2006.168.08:17:08.07#ibcon#wrote, iclass 17, count 2 2006.168.08:17:08.07#ibcon#about to read 3, iclass 17, count 2 2006.168.08:17:08.09#ibcon#read 3, iclass 17, count 2 2006.168.08:17:08.09#ibcon#about to read 4, iclass 17, count 2 2006.168.08:17:08.09#ibcon#read 4, iclass 17, count 2 2006.168.08:17:08.09#ibcon#about to read 5, iclass 17, count 2 2006.168.08:17:08.09#ibcon#read 5, iclass 17, count 2 2006.168.08:17:08.09#ibcon#about to read 6, iclass 17, count 2 2006.168.08:17:08.09#ibcon#read 6, iclass 17, count 2 2006.168.08:17:08.09#ibcon#end of sib2, iclass 17, count 2 2006.168.08:17:08.09#ibcon#*mode == 0, iclass 17, count 2 2006.168.08:17:08.09#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.168.08:17:08.09#ibcon#[25=AT01-08\r\n] 2006.168.08:17:08.09#ibcon#*before write, iclass 17, count 2 2006.168.08:17:08.09#ibcon#enter sib2, iclass 17, count 2 2006.168.08:17:08.09#ibcon#flushed, iclass 17, count 2 2006.168.08:17:08.09#ibcon#about to write, iclass 17, count 2 2006.168.08:17:08.09#ibcon#wrote, iclass 17, count 2 2006.168.08:17:08.09#ibcon#about to read 3, iclass 17, count 2 2006.168.08:17:08.13#ibcon#read 3, iclass 17, count 2 2006.168.08:17:08.13#ibcon#about to read 4, iclass 17, count 2 2006.168.08:17:08.13#ibcon#read 4, iclass 17, count 2 2006.168.08:17:08.13#ibcon#about to read 5, iclass 17, count 2 2006.168.08:17:08.13#ibcon#read 5, iclass 17, count 2 2006.168.08:17:08.13#ibcon#about to read 6, iclass 17, count 2 2006.168.08:17:08.13#ibcon#read 6, iclass 17, count 2 2006.168.08:17:08.13#ibcon#end of sib2, iclass 17, count 2 2006.168.08:17:08.13#ibcon#*after write, iclass 17, count 2 2006.168.08:17:08.13#ibcon#*before return 0, iclass 17, count 2 2006.168.08:17:08.13#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.168.08:17:08.13#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.168.08:17:08.13#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.168.08:17:08.13#ibcon#ireg 7 cls_cnt 0 2006.168.08:17:08.13#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.168.08:17:08.25#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.168.08:17:08.25#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.168.08:17:08.25#ibcon#enter wrdev, iclass 17, count 0 2006.168.08:17:08.25#ibcon#first serial, iclass 17, count 0 2006.168.08:17:08.25#ibcon#enter sib2, iclass 17, count 0 2006.168.08:17:08.25#ibcon#flushed, iclass 17, count 0 2006.168.08:17:08.25#ibcon#about to write, iclass 17, count 0 2006.168.08:17:08.25#ibcon#wrote, iclass 17, count 0 2006.168.08:17:08.25#ibcon#about to read 3, iclass 17, count 0 2006.168.08:17:08.27#ibcon#read 3, iclass 17, count 0 2006.168.08:17:08.27#ibcon#about to read 4, iclass 17, count 0 2006.168.08:17:08.27#ibcon#read 4, iclass 17, count 0 2006.168.08:17:08.27#ibcon#about to read 5, iclass 17, count 0 2006.168.08:17:08.27#ibcon#read 5, iclass 17, count 0 2006.168.08:17:08.27#ibcon#about to read 6, iclass 17, count 0 2006.168.08:17:08.27#ibcon#read 6, iclass 17, count 0 2006.168.08:17:08.27#ibcon#end of sib2, iclass 17, count 0 2006.168.08:17:08.27#ibcon#*mode == 0, iclass 17, count 0 2006.168.08:17:08.27#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.168.08:17:08.27#ibcon#[25=USB\r\n] 2006.168.08:17:08.27#ibcon#*before write, iclass 17, count 0 2006.168.08:17:08.27#ibcon#enter sib2, iclass 17, count 0 2006.168.08:17:08.27#ibcon#flushed, iclass 17, count 0 2006.168.08:17:08.27#ibcon#about to write, iclass 17, count 0 2006.168.08:17:08.27#ibcon#wrote, iclass 17, count 0 2006.168.08:17:08.27#ibcon#about to read 3, iclass 17, count 0 2006.168.08:17:08.30#ibcon#read 3, iclass 17, count 0 2006.168.08:17:08.30#ibcon#about to read 4, iclass 17, count 0 2006.168.08:17:08.30#ibcon#read 4, iclass 17, count 0 2006.168.08:17:08.30#ibcon#about to read 5, iclass 17, count 0 2006.168.08:17:08.30#ibcon#read 5, iclass 17, count 0 2006.168.08:17:08.30#ibcon#about to read 6, iclass 17, count 0 2006.168.08:17:08.30#ibcon#read 6, iclass 17, count 0 2006.168.08:17:08.30#ibcon#end of sib2, iclass 17, count 0 2006.168.08:17:08.30#ibcon#*after write, iclass 17, count 0 2006.168.08:17:08.30#ibcon#*before return 0, iclass 17, count 0 2006.168.08:17:08.30#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.168.08:17:08.30#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.168.08:17:08.30#ibcon#about to clear, iclass 17 cls_cnt 0 2006.168.08:17:08.30#ibcon#cleared, iclass 17 cls_cnt 0 2006.168.08:17:08.30$vc4f8/valo=2,572.99 2006.168.08:17:08.30#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.168.08:17:08.30#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.168.08:17:08.30#ibcon#ireg 17 cls_cnt 0 2006.168.08:17:08.30#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.168.08:17:08.30#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.168.08:17:08.30#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.168.08:17:08.30#ibcon#enter wrdev, iclass 19, count 0 2006.168.08:17:08.30#ibcon#first serial, iclass 19, count 0 2006.168.08:17:08.30#ibcon#enter sib2, iclass 19, count 0 2006.168.08:17:08.30#ibcon#flushed, iclass 19, count 0 2006.168.08:17:08.30#ibcon#about to write, iclass 19, count 0 2006.168.08:17:08.30#ibcon#wrote, iclass 19, count 0 2006.168.08:17:08.30#ibcon#about to read 3, iclass 19, count 0 2006.168.08:17:08.32#ibcon#read 3, iclass 19, count 0 2006.168.08:17:08.32#ibcon#about to read 4, iclass 19, count 0 2006.168.08:17:08.32#ibcon#read 4, iclass 19, count 0 2006.168.08:17:08.32#ibcon#about to read 5, iclass 19, count 0 2006.168.08:17:08.32#ibcon#read 5, iclass 19, count 0 2006.168.08:17:08.32#ibcon#about to read 6, iclass 19, count 0 2006.168.08:17:08.32#ibcon#read 6, iclass 19, count 0 2006.168.08:17:08.32#ibcon#end of sib2, iclass 19, count 0 2006.168.08:17:08.32#ibcon#*mode == 0, iclass 19, count 0 2006.168.08:17:08.32#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.168.08:17:08.32#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.08:17:08.32#ibcon#*before write, iclass 19, count 0 2006.168.08:17:08.32#ibcon#enter sib2, iclass 19, count 0 2006.168.08:17:08.32#ibcon#flushed, iclass 19, count 0 2006.168.08:17:08.32#ibcon#about to write, iclass 19, count 0 2006.168.08:17:08.32#ibcon#wrote, iclass 19, count 0 2006.168.08:17:08.32#ibcon#about to read 3, iclass 19, count 0 2006.168.08:17:08.36#ibcon#read 3, iclass 19, count 0 2006.168.08:17:08.36#ibcon#about to read 4, iclass 19, count 0 2006.168.08:17:08.36#ibcon#read 4, iclass 19, count 0 2006.168.08:17:08.36#ibcon#about to read 5, iclass 19, count 0 2006.168.08:17:08.36#ibcon#read 5, iclass 19, count 0 2006.168.08:17:08.36#ibcon#about to read 6, iclass 19, count 0 2006.168.08:17:08.36#ibcon#read 6, iclass 19, count 0 2006.168.08:17:08.36#ibcon#end of sib2, iclass 19, count 0 2006.168.08:17:08.36#ibcon#*after write, iclass 19, count 0 2006.168.08:17:08.36#ibcon#*before return 0, iclass 19, count 0 2006.168.08:17:08.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.168.08:17:08.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.168.08:17:08.36#ibcon#about to clear, iclass 19 cls_cnt 0 2006.168.08:17:08.36#ibcon#cleared, iclass 19 cls_cnt 0 2006.168.08:17:08.36$vc4f8/va=2,7 2006.168.08:17:08.36#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.168.08:17:08.36#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.168.08:17:08.36#ibcon#ireg 11 cls_cnt 2 2006.168.08:17:08.36#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.168.08:17:08.42#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.168.08:17:08.42#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.168.08:17:08.42#ibcon#enter wrdev, iclass 21, count 2 2006.168.08:17:08.42#ibcon#first serial, iclass 21, count 2 2006.168.08:17:08.42#ibcon#enter sib2, iclass 21, count 2 2006.168.08:17:08.42#ibcon#flushed, iclass 21, count 2 2006.168.08:17:08.42#ibcon#about to write, iclass 21, count 2 2006.168.08:17:08.42#ibcon#wrote, iclass 21, count 2 2006.168.08:17:08.42#ibcon#about to read 3, iclass 21, count 2 2006.168.08:17:08.44#ibcon#read 3, iclass 21, count 2 2006.168.08:17:08.44#ibcon#about to read 4, iclass 21, count 2 2006.168.08:17:08.44#ibcon#read 4, iclass 21, count 2 2006.168.08:17:08.44#ibcon#about to read 5, iclass 21, count 2 2006.168.08:17:08.44#ibcon#read 5, iclass 21, count 2 2006.168.08:17:08.44#ibcon#about to read 6, iclass 21, count 2 2006.168.08:17:08.44#ibcon#read 6, iclass 21, count 2 2006.168.08:17:08.44#ibcon#end of sib2, iclass 21, count 2 2006.168.08:17:08.44#ibcon#*mode == 0, iclass 21, count 2 2006.168.08:17:08.44#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.168.08:17:08.44#ibcon#[25=AT02-07\r\n] 2006.168.08:17:08.44#ibcon#*before write, iclass 21, count 2 2006.168.08:17:08.44#ibcon#enter sib2, iclass 21, count 2 2006.168.08:17:08.44#ibcon#flushed, iclass 21, count 2 2006.168.08:17:08.44#ibcon#about to write, iclass 21, count 2 2006.168.08:17:08.44#ibcon#wrote, iclass 21, count 2 2006.168.08:17:08.44#ibcon#about to read 3, iclass 21, count 2 2006.168.08:17:08.48#ibcon#read 3, iclass 21, count 2 2006.168.08:17:08.48#ibcon#about to read 4, iclass 21, count 2 2006.168.08:17:08.48#ibcon#read 4, iclass 21, count 2 2006.168.08:17:08.48#ibcon#about to read 5, iclass 21, count 2 2006.168.08:17:08.48#ibcon#read 5, iclass 21, count 2 2006.168.08:17:08.48#ibcon#about to read 6, iclass 21, count 2 2006.168.08:17:08.48#ibcon#read 6, iclass 21, count 2 2006.168.08:17:08.48#ibcon#end of sib2, iclass 21, count 2 2006.168.08:17:08.48#ibcon#*after write, iclass 21, count 2 2006.168.08:17:08.48#ibcon#*before return 0, iclass 21, count 2 2006.168.08:17:08.48#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.168.08:17:08.48#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.168.08:17:08.48#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.168.08:17:08.48#ibcon#ireg 7 cls_cnt 0 2006.168.08:17:08.48#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.168.08:17:08.60#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.168.08:17:08.60#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.168.08:17:08.60#ibcon#enter wrdev, iclass 21, count 0 2006.168.08:17:08.60#ibcon#first serial, iclass 21, count 0 2006.168.08:17:08.60#ibcon#enter sib2, iclass 21, count 0 2006.168.08:17:08.60#ibcon#flushed, iclass 21, count 0 2006.168.08:17:08.60#ibcon#about to write, iclass 21, count 0 2006.168.08:17:08.60#ibcon#wrote, iclass 21, count 0 2006.168.08:17:08.60#ibcon#about to read 3, iclass 21, count 0 2006.168.08:17:08.62#ibcon#read 3, iclass 21, count 0 2006.168.08:17:08.62#ibcon#about to read 4, iclass 21, count 0 2006.168.08:17:08.62#ibcon#read 4, iclass 21, count 0 2006.168.08:17:08.62#ibcon#about to read 5, iclass 21, count 0 2006.168.08:17:08.62#ibcon#read 5, iclass 21, count 0 2006.168.08:17:08.62#ibcon#about to read 6, iclass 21, count 0 2006.168.08:17:08.62#ibcon#read 6, iclass 21, count 0 2006.168.08:17:08.62#ibcon#end of sib2, iclass 21, count 0 2006.168.08:17:08.62#ibcon#*mode == 0, iclass 21, count 0 2006.168.08:17:08.62#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.168.08:17:08.62#ibcon#[25=USB\r\n] 2006.168.08:17:08.62#ibcon#*before write, iclass 21, count 0 2006.168.08:17:08.62#ibcon#enter sib2, iclass 21, count 0 2006.168.08:17:08.62#ibcon#flushed, iclass 21, count 0 2006.168.08:17:08.62#ibcon#about to write, iclass 21, count 0 2006.168.08:17:08.62#ibcon#wrote, iclass 21, count 0 2006.168.08:17:08.62#ibcon#about to read 3, iclass 21, count 0 2006.168.08:17:08.65#ibcon#read 3, iclass 21, count 0 2006.168.08:17:08.65#ibcon#about to read 4, iclass 21, count 0 2006.168.08:17:08.65#ibcon#read 4, iclass 21, count 0 2006.168.08:17:08.65#ibcon#about to read 5, iclass 21, count 0 2006.168.08:17:08.65#ibcon#read 5, iclass 21, count 0 2006.168.08:17:08.65#ibcon#about to read 6, iclass 21, count 0 2006.168.08:17:08.65#ibcon#read 6, iclass 21, count 0 2006.168.08:17:08.65#ibcon#end of sib2, iclass 21, count 0 2006.168.08:17:08.65#ibcon#*after write, iclass 21, count 0 2006.168.08:17:08.65#ibcon#*before return 0, iclass 21, count 0 2006.168.08:17:08.65#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.168.08:17:08.65#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.168.08:17:08.65#ibcon#about to clear, iclass 21 cls_cnt 0 2006.168.08:17:08.65#ibcon#cleared, iclass 21 cls_cnt 0 2006.168.08:17:08.65$vc4f8/valo=3,672.99 2006.168.08:17:08.65#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.168.08:17:08.65#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.168.08:17:08.65#ibcon#ireg 17 cls_cnt 0 2006.168.08:17:08.65#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:17:08.65#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:17:08.65#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:17:08.65#ibcon#enter wrdev, iclass 23, count 0 2006.168.08:17:08.65#ibcon#first serial, iclass 23, count 0 2006.168.08:17:08.65#ibcon#enter sib2, iclass 23, count 0 2006.168.08:17:08.65#ibcon#flushed, iclass 23, count 0 2006.168.08:17:08.65#ibcon#about to write, iclass 23, count 0 2006.168.08:17:08.65#ibcon#wrote, iclass 23, count 0 2006.168.08:17:08.65#ibcon#about to read 3, iclass 23, count 0 2006.168.08:17:08.67#ibcon#read 3, iclass 23, count 0 2006.168.08:17:08.67#ibcon#about to read 4, iclass 23, count 0 2006.168.08:17:08.67#ibcon#read 4, iclass 23, count 0 2006.168.08:17:08.67#ibcon#about to read 5, iclass 23, count 0 2006.168.08:17:08.67#ibcon#read 5, iclass 23, count 0 2006.168.08:17:08.67#ibcon#about to read 6, iclass 23, count 0 2006.168.08:17:08.67#ibcon#read 6, iclass 23, count 0 2006.168.08:17:08.67#ibcon#end of sib2, iclass 23, count 0 2006.168.08:17:08.67#ibcon#*mode == 0, iclass 23, count 0 2006.168.08:17:08.67#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.168.08:17:08.67#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.08:17:08.67#ibcon#*before write, iclass 23, count 0 2006.168.08:17:08.67#ibcon#enter sib2, iclass 23, count 0 2006.168.08:17:08.67#ibcon#flushed, iclass 23, count 0 2006.168.08:17:08.67#ibcon#about to write, iclass 23, count 0 2006.168.08:17:08.67#ibcon#wrote, iclass 23, count 0 2006.168.08:17:08.67#ibcon#about to read 3, iclass 23, count 0 2006.168.08:17:08.71#ibcon#read 3, iclass 23, count 0 2006.168.08:17:08.71#ibcon#about to read 4, iclass 23, count 0 2006.168.08:17:08.71#ibcon#read 4, iclass 23, count 0 2006.168.08:17:08.71#ibcon#about to read 5, iclass 23, count 0 2006.168.08:17:08.71#ibcon#read 5, iclass 23, count 0 2006.168.08:17:08.71#ibcon#about to read 6, iclass 23, count 0 2006.168.08:17:08.71#ibcon#read 6, iclass 23, count 0 2006.168.08:17:08.71#ibcon#end of sib2, iclass 23, count 0 2006.168.08:17:08.71#ibcon#*after write, iclass 23, count 0 2006.168.08:17:08.71#ibcon#*before return 0, iclass 23, count 0 2006.168.08:17:08.71#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:17:08.71#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:17:08.71#ibcon#about to clear, iclass 23 cls_cnt 0 2006.168.08:17:08.71#ibcon#cleared, iclass 23 cls_cnt 0 2006.168.08:17:08.71$vc4f8/va=3,6 2006.168.08:17:08.71#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.168.08:17:08.71#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.168.08:17:08.71#ibcon#ireg 11 cls_cnt 2 2006.168.08:17:08.71#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:17:08.77#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:17:08.77#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:17:08.77#ibcon#enter wrdev, iclass 25, count 2 2006.168.08:17:08.77#ibcon#first serial, iclass 25, count 2 2006.168.08:17:08.77#ibcon#enter sib2, iclass 25, count 2 2006.168.08:17:08.77#ibcon#flushed, iclass 25, count 2 2006.168.08:17:08.77#ibcon#about to write, iclass 25, count 2 2006.168.08:17:08.77#ibcon#wrote, iclass 25, count 2 2006.168.08:17:08.77#ibcon#about to read 3, iclass 25, count 2 2006.168.08:17:08.79#ibcon#read 3, iclass 25, count 2 2006.168.08:17:08.79#ibcon#about to read 4, iclass 25, count 2 2006.168.08:17:08.79#ibcon#read 4, iclass 25, count 2 2006.168.08:17:08.79#ibcon#about to read 5, iclass 25, count 2 2006.168.08:17:08.79#ibcon#read 5, iclass 25, count 2 2006.168.08:17:08.79#ibcon#about to read 6, iclass 25, count 2 2006.168.08:17:08.79#ibcon#read 6, iclass 25, count 2 2006.168.08:17:08.79#ibcon#end of sib2, iclass 25, count 2 2006.168.08:17:08.79#ibcon#*mode == 0, iclass 25, count 2 2006.168.08:17:08.79#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.168.08:17:08.79#ibcon#[25=AT03-06\r\n] 2006.168.08:17:08.79#ibcon#*before write, iclass 25, count 2 2006.168.08:17:08.79#ibcon#enter sib2, iclass 25, count 2 2006.168.08:17:08.79#ibcon#flushed, iclass 25, count 2 2006.168.08:17:08.79#ibcon#about to write, iclass 25, count 2 2006.168.08:17:08.79#ibcon#wrote, iclass 25, count 2 2006.168.08:17:08.79#ibcon#about to read 3, iclass 25, count 2 2006.168.08:17:08.82#ibcon#read 3, iclass 25, count 2 2006.168.08:17:08.82#ibcon#about to read 4, iclass 25, count 2 2006.168.08:17:08.82#ibcon#read 4, iclass 25, count 2 2006.168.08:17:08.82#ibcon#about to read 5, iclass 25, count 2 2006.168.08:17:08.82#ibcon#read 5, iclass 25, count 2 2006.168.08:17:08.82#ibcon#about to read 6, iclass 25, count 2 2006.168.08:17:08.82#ibcon#read 6, iclass 25, count 2 2006.168.08:17:08.82#ibcon#end of sib2, iclass 25, count 2 2006.168.08:17:08.82#ibcon#*after write, iclass 25, count 2 2006.168.08:17:08.82#ibcon#*before return 0, iclass 25, count 2 2006.168.08:17:08.82#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:17:08.82#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:17:08.82#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.168.08:17:08.82#ibcon#ireg 7 cls_cnt 0 2006.168.08:17:08.82#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:17:08.94#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:17:08.94#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:17:08.94#ibcon#enter wrdev, iclass 25, count 0 2006.168.08:17:08.94#ibcon#first serial, iclass 25, count 0 2006.168.08:17:08.94#ibcon#enter sib2, iclass 25, count 0 2006.168.08:17:08.94#ibcon#flushed, iclass 25, count 0 2006.168.08:17:08.94#ibcon#about to write, iclass 25, count 0 2006.168.08:17:08.94#ibcon#wrote, iclass 25, count 0 2006.168.08:17:08.94#ibcon#about to read 3, iclass 25, count 0 2006.168.08:17:08.96#ibcon#read 3, iclass 25, count 0 2006.168.08:17:08.96#ibcon#about to read 4, iclass 25, count 0 2006.168.08:17:08.96#ibcon#read 4, iclass 25, count 0 2006.168.08:17:08.96#ibcon#about to read 5, iclass 25, count 0 2006.168.08:17:08.96#ibcon#read 5, iclass 25, count 0 2006.168.08:17:08.96#ibcon#about to read 6, iclass 25, count 0 2006.168.08:17:08.96#ibcon#read 6, iclass 25, count 0 2006.168.08:17:08.96#ibcon#end of sib2, iclass 25, count 0 2006.168.08:17:08.96#ibcon#*mode == 0, iclass 25, count 0 2006.168.08:17:08.96#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.168.08:17:08.96#ibcon#[25=USB\r\n] 2006.168.08:17:08.96#ibcon#*before write, iclass 25, count 0 2006.168.08:17:08.96#ibcon#enter sib2, iclass 25, count 0 2006.168.08:17:08.96#ibcon#flushed, iclass 25, count 0 2006.168.08:17:08.96#ibcon#about to write, iclass 25, count 0 2006.168.08:17:08.96#ibcon#wrote, iclass 25, count 0 2006.168.08:17:08.96#ibcon#about to read 3, iclass 25, count 0 2006.168.08:17:08.99#ibcon#read 3, iclass 25, count 0 2006.168.08:17:08.99#ibcon#about to read 4, iclass 25, count 0 2006.168.08:17:08.99#ibcon#read 4, iclass 25, count 0 2006.168.08:17:08.99#ibcon#about to read 5, iclass 25, count 0 2006.168.08:17:08.99#ibcon#read 5, iclass 25, count 0 2006.168.08:17:08.99#ibcon#about to read 6, iclass 25, count 0 2006.168.08:17:08.99#ibcon#read 6, iclass 25, count 0 2006.168.08:17:08.99#ibcon#end of sib2, iclass 25, count 0 2006.168.08:17:08.99#ibcon#*after write, iclass 25, count 0 2006.168.08:17:08.99#ibcon#*before return 0, iclass 25, count 0 2006.168.08:17:08.99#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:17:08.99#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:17:08.99#ibcon#about to clear, iclass 25 cls_cnt 0 2006.168.08:17:08.99#ibcon#cleared, iclass 25 cls_cnt 0 2006.168.08:17:08.99$vc4f8/valo=4,832.99 2006.168.08:17:08.99#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.168.08:17:08.99#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.168.08:17:08.99#ibcon#ireg 17 cls_cnt 0 2006.168.08:17:08.99#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:17:08.99#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:17:08.99#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:17:08.99#ibcon#enter wrdev, iclass 27, count 0 2006.168.08:17:08.99#ibcon#first serial, iclass 27, count 0 2006.168.08:17:08.99#ibcon#enter sib2, iclass 27, count 0 2006.168.08:17:08.99#ibcon#flushed, iclass 27, count 0 2006.168.08:17:08.99#ibcon#about to write, iclass 27, count 0 2006.168.08:17:08.99#ibcon#wrote, iclass 27, count 0 2006.168.08:17:08.99#ibcon#about to read 3, iclass 27, count 0 2006.168.08:17:09.01#ibcon#read 3, iclass 27, count 0 2006.168.08:17:09.01#ibcon#about to read 4, iclass 27, count 0 2006.168.08:17:09.01#ibcon#read 4, iclass 27, count 0 2006.168.08:17:09.01#ibcon#about to read 5, iclass 27, count 0 2006.168.08:17:09.01#ibcon#read 5, iclass 27, count 0 2006.168.08:17:09.01#ibcon#about to read 6, iclass 27, count 0 2006.168.08:17:09.01#ibcon#read 6, iclass 27, count 0 2006.168.08:17:09.01#ibcon#end of sib2, iclass 27, count 0 2006.168.08:17:09.01#ibcon#*mode == 0, iclass 27, count 0 2006.168.08:17:09.01#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.168.08:17:09.01#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.08:17:09.01#ibcon#*before write, iclass 27, count 0 2006.168.08:17:09.01#ibcon#enter sib2, iclass 27, count 0 2006.168.08:17:09.01#ibcon#flushed, iclass 27, count 0 2006.168.08:17:09.01#ibcon#about to write, iclass 27, count 0 2006.168.08:17:09.01#ibcon#wrote, iclass 27, count 0 2006.168.08:17:09.01#ibcon#about to read 3, iclass 27, count 0 2006.168.08:17:09.05#ibcon#read 3, iclass 27, count 0 2006.168.08:17:09.05#ibcon#about to read 4, iclass 27, count 0 2006.168.08:17:09.05#ibcon#read 4, iclass 27, count 0 2006.168.08:17:09.05#ibcon#about to read 5, iclass 27, count 0 2006.168.08:17:09.05#ibcon#read 5, iclass 27, count 0 2006.168.08:17:09.05#ibcon#about to read 6, iclass 27, count 0 2006.168.08:17:09.05#ibcon#read 6, iclass 27, count 0 2006.168.08:17:09.05#ibcon#end of sib2, iclass 27, count 0 2006.168.08:17:09.05#ibcon#*after write, iclass 27, count 0 2006.168.08:17:09.05#ibcon#*before return 0, iclass 27, count 0 2006.168.08:17:09.05#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:17:09.05#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:17:09.05#ibcon#about to clear, iclass 27 cls_cnt 0 2006.168.08:17:09.05#ibcon#cleared, iclass 27 cls_cnt 0 2006.168.08:17:09.05$vc4f8/va=4,7 2006.168.08:17:09.05#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.168.08:17:09.05#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.168.08:17:09.05#ibcon#ireg 11 cls_cnt 2 2006.168.08:17:09.05#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:17:09.11#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:17:09.11#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:17:09.11#ibcon#enter wrdev, iclass 29, count 2 2006.168.08:17:09.11#ibcon#first serial, iclass 29, count 2 2006.168.08:17:09.11#ibcon#enter sib2, iclass 29, count 2 2006.168.08:17:09.11#ibcon#flushed, iclass 29, count 2 2006.168.08:17:09.11#ibcon#about to write, iclass 29, count 2 2006.168.08:17:09.11#ibcon#wrote, iclass 29, count 2 2006.168.08:17:09.11#ibcon#about to read 3, iclass 29, count 2 2006.168.08:17:09.13#ibcon#read 3, iclass 29, count 2 2006.168.08:17:09.13#ibcon#about to read 4, iclass 29, count 2 2006.168.08:17:09.13#ibcon#read 4, iclass 29, count 2 2006.168.08:17:09.13#ibcon#about to read 5, iclass 29, count 2 2006.168.08:17:09.13#ibcon#read 5, iclass 29, count 2 2006.168.08:17:09.13#ibcon#about to read 6, iclass 29, count 2 2006.168.08:17:09.13#ibcon#read 6, iclass 29, count 2 2006.168.08:17:09.13#ibcon#end of sib2, iclass 29, count 2 2006.168.08:17:09.13#ibcon#*mode == 0, iclass 29, count 2 2006.168.08:17:09.13#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.168.08:17:09.13#ibcon#[25=AT04-07\r\n] 2006.168.08:17:09.13#ibcon#*before write, iclass 29, count 2 2006.168.08:17:09.13#ibcon#enter sib2, iclass 29, count 2 2006.168.08:17:09.13#ibcon#flushed, iclass 29, count 2 2006.168.08:17:09.13#ibcon#about to write, iclass 29, count 2 2006.168.08:17:09.13#ibcon#wrote, iclass 29, count 2 2006.168.08:17:09.13#ibcon#about to read 3, iclass 29, count 2 2006.168.08:17:09.16#ibcon#read 3, iclass 29, count 2 2006.168.08:17:09.16#ibcon#about to read 4, iclass 29, count 2 2006.168.08:17:09.16#ibcon#read 4, iclass 29, count 2 2006.168.08:17:09.16#ibcon#about to read 5, iclass 29, count 2 2006.168.08:17:09.16#ibcon#read 5, iclass 29, count 2 2006.168.08:17:09.16#ibcon#about to read 6, iclass 29, count 2 2006.168.08:17:09.16#ibcon#read 6, iclass 29, count 2 2006.168.08:17:09.16#ibcon#end of sib2, iclass 29, count 2 2006.168.08:17:09.16#ibcon#*after write, iclass 29, count 2 2006.168.08:17:09.16#ibcon#*before return 0, iclass 29, count 2 2006.168.08:17:09.16#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:17:09.16#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:17:09.16#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.168.08:17:09.16#ibcon#ireg 7 cls_cnt 0 2006.168.08:17:09.16#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:17:09.28#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:17:09.28#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:17:09.28#ibcon#enter wrdev, iclass 29, count 0 2006.168.08:17:09.28#ibcon#first serial, iclass 29, count 0 2006.168.08:17:09.28#ibcon#enter sib2, iclass 29, count 0 2006.168.08:17:09.28#ibcon#flushed, iclass 29, count 0 2006.168.08:17:09.28#ibcon#about to write, iclass 29, count 0 2006.168.08:17:09.28#ibcon#wrote, iclass 29, count 0 2006.168.08:17:09.28#ibcon#about to read 3, iclass 29, count 0 2006.168.08:17:09.30#ibcon#read 3, iclass 29, count 0 2006.168.08:17:09.30#ibcon#about to read 4, iclass 29, count 0 2006.168.08:17:09.30#ibcon#read 4, iclass 29, count 0 2006.168.08:17:09.30#ibcon#about to read 5, iclass 29, count 0 2006.168.08:17:09.30#ibcon#read 5, iclass 29, count 0 2006.168.08:17:09.30#ibcon#about to read 6, iclass 29, count 0 2006.168.08:17:09.30#ibcon#read 6, iclass 29, count 0 2006.168.08:17:09.30#ibcon#end of sib2, iclass 29, count 0 2006.168.08:17:09.30#ibcon#*mode == 0, iclass 29, count 0 2006.168.08:17:09.30#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.168.08:17:09.30#ibcon#[25=USB\r\n] 2006.168.08:17:09.30#ibcon#*before write, iclass 29, count 0 2006.168.08:17:09.30#ibcon#enter sib2, iclass 29, count 0 2006.168.08:17:09.30#ibcon#flushed, iclass 29, count 0 2006.168.08:17:09.30#ibcon#about to write, iclass 29, count 0 2006.168.08:17:09.30#ibcon#wrote, iclass 29, count 0 2006.168.08:17:09.30#ibcon#about to read 3, iclass 29, count 0 2006.168.08:17:09.33#ibcon#read 3, iclass 29, count 0 2006.168.08:17:09.33#ibcon#about to read 4, iclass 29, count 0 2006.168.08:17:09.33#ibcon#read 4, iclass 29, count 0 2006.168.08:17:09.33#ibcon#about to read 5, iclass 29, count 0 2006.168.08:17:09.33#ibcon#read 5, iclass 29, count 0 2006.168.08:17:09.33#ibcon#about to read 6, iclass 29, count 0 2006.168.08:17:09.33#ibcon#read 6, iclass 29, count 0 2006.168.08:17:09.33#ibcon#end of sib2, iclass 29, count 0 2006.168.08:17:09.33#ibcon#*after write, iclass 29, count 0 2006.168.08:17:09.33#ibcon#*before return 0, iclass 29, count 0 2006.168.08:17:09.33#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:17:09.33#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:17:09.33#ibcon#about to clear, iclass 29 cls_cnt 0 2006.168.08:17:09.33#ibcon#cleared, iclass 29 cls_cnt 0 2006.168.08:17:09.33$vc4f8/valo=5,652.99 2006.168.08:17:09.33#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.168.08:17:09.33#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.168.08:17:09.33#ibcon#ireg 17 cls_cnt 0 2006.168.08:17:09.33#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:17:09.33#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:17:09.33#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:17:09.33#ibcon#enter wrdev, iclass 31, count 0 2006.168.08:17:09.33#ibcon#first serial, iclass 31, count 0 2006.168.08:17:09.33#ibcon#enter sib2, iclass 31, count 0 2006.168.08:17:09.33#ibcon#flushed, iclass 31, count 0 2006.168.08:17:09.33#ibcon#about to write, iclass 31, count 0 2006.168.08:17:09.33#ibcon#wrote, iclass 31, count 0 2006.168.08:17:09.33#ibcon#about to read 3, iclass 31, count 0 2006.168.08:17:09.35#ibcon#read 3, iclass 31, count 0 2006.168.08:17:09.35#ibcon#about to read 4, iclass 31, count 0 2006.168.08:17:09.35#ibcon#read 4, iclass 31, count 0 2006.168.08:17:09.35#ibcon#about to read 5, iclass 31, count 0 2006.168.08:17:09.35#ibcon#read 5, iclass 31, count 0 2006.168.08:17:09.35#ibcon#about to read 6, iclass 31, count 0 2006.168.08:17:09.35#ibcon#read 6, iclass 31, count 0 2006.168.08:17:09.35#ibcon#end of sib2, iclass 31, count 0 2006.168.08:17:09.35#ibcon#*mode == 0, iclass 31, count 0 2006.168.08:17:09.35#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.168.08:17:09.35#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.08:17:09.35#ibcon#*before write, iclass 31, count 0 2006.168.08:17:09.35#ibcon#enter sib2, iclass 31, count 0 2006.168.08:17:09.35#ibcon#flushed, iclass 31, count 0 2006.168.08:17:09.35#ibcon#about to write, iclass 31, count 0 2006.168.08:17:09.35#ibcon#wrote, iclass 31, count 0 2006.168.08:17:09.35#ibcon#about to read 3, iclass 31, count 0 2006.168.08:17:09.39#ibcon#read 3, iclass 31, count 0 2006.168.08:17:09.39#ibcon#about to read 4, iclass 31, count 0 2006.168.08:17:09.39#ibcon#read 4, iclass 31, count 0 2006.168.08:17:09.39#ibcon#about to read 5, iclass 31, count 0 2006.168.08:17:09.39#ibcon#read 5, iclass 31, count 0 2006.168.08:17:09.39#ibcon#about to read 6, iclass 31, count 0 2006.168.08:17:09.39#ibcon#read 6, iclass 31, count 0 2006.168.08:17:09.39#ibcon#end of sib2, iclass 31, count 0 2006.168.08:17:09.39#ibcon#*after write, iclass 31, count 0 2006.168.08:17:09.39#ibcon#*before return 0, iclass 31, count 0 2006.168.08:17:09.39#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:17:09.39#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:17:09.39#ibcon#about to clear, iclass 31 cls_cnt 0 2006.168.08:17:09.39#ibcon#cleared, iclass 31 cls_cnt 0 2006.168.08:17:09.39$vc4f8/va=5,7 2006.168.08:17:09.39#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.168.08:17:09.39#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.168.08:17:09.39#ibcon#ireg 11 cls_cnt 2 2006.168.08:17:09.39#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.168.08:17:09.45#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.168.08:17:09.45#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.168.08:17:09.45#ibcon#enter wrdev, iclass 33, count 2 2006.168.08:17:09.45#ibcon#first serial, iclass 33, count 2 2006.168.08:17:09.45#ibcon#enter sib2, iclass 33, count 2 2006.168.08:17:09.45#ibcon#flushed, iclass 33, count 2 2006.168.08:17:09.45#ibcon#about to write, iclass 33, count 2 2006.168.08:17:09.45#ibcon#wrote, iclass 33, count 2 2006.168.08:17:09.45#ibcon#about to read 3, iclass 33, count 2 2006.168.08:17:09.47#ibcon#read 3, iclass 33, count 2 2006.168.08:17:09.47#ibcon#about to read 4, iclass 33, count 2 2006.168.08:17:09.47#ibcon#read 4, iclass 33, count 2 2006.168.08:17:09.47#ibcon#about to read 5, iclass 33, count 2 2006.168.08:17:09.47#ibcon#read 5, iclass 33, count 2 2006.168.08:17:09.47#ibcon#about to read 6, iclass 33, count 2 2006.168.08:17:09.47#ibcon#read 6, iclass 33, count 2 2006.168.08:17:09.47#ibcon#end of sib2, iclass 33, count 2 2006.168.08:17:09.47#ibcon#*mode == 0, iclass 33, count 2 2006.168.08:17:09.47#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.168.08:17:09.47#ibcon#[25=AT05-07\r\n] 2006.168.08:17:09.47#ibcon#*before write, iclass 33, count 2 2006.168.08:17:09.47#ibcon#enter sib2, iclass 33, count 2 2006.168.08:17:09.47#ibcon#flushed, iclass 33, count 2 2006.168.08:17:09.47#ibcon#about to write, iclass 33, count 2 2006.168.08:17:09.47#ibcon#wrote, iclass 33, count 2 2006.168.08:17:09.47#ibcon#about to read 3, iclass 33, count 2 2006.168.08:17:09.50#ibcon#read 3, iclass 33, count 2 2006.168.08:17:09.50#ibcon#about to read 4, iclass 33, count 2 2006.168.08:17:09.50#ibcon#read 4, iclass 33, count 2 2006.168.08:17:09.50#ibcon#about to read 5, iclass 33, count 2 2006.168.08:17:09.50#ibcon#read 5, iclass 33, count 2 2006.168.08:17:09.50#ibcon#about to read 6, iclass 33, count 2 2006.168.08:17:09.50#ibcon#read 6, iclass 33, count 2 2006.168.08:17:09.50#ibcon#end of sib2, iclass 33, count 2 2006.168.08:17:09.50#ibcon#*after write, iclass 33, count 2 2006.168.08:17:09.50#ibcon#*before return 0, iclass 33, count 2 2006.168.08:17:09.50#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.168.08:17:09.50#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.168.08:17:09.50#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.168.08:17:09.50#ibcon#ireg 7 cls_cnt 0 2006.168.08:17:09.50#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.168.08:17:09.62#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.168.08:17:09.62#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.168.08:17:09.62#ibcon#enter wrdev, iclass 33, count 0 2006.168.08:17:09.62#ibcon#first serial, iclass 33, count 0 2006.168.08:17:09.62#ibcon#enter sib2, iclass 33, count 0 2006.168.08:17:09.62#ibcon#flushed, iclass 33, count 0 2006.168.08:17:09.62#ibcon#about to write, iclass 33, count 0 2006.168.08:17:09.62#ibcon#wrote, iclass 33, count 0 2006.168.08:17:09.62#ibcon#about to read 3, iclass 33, count 0 2006.168.08:17:09.64#ibcon#read 3, iclass 33, count 0 2006.168.08:17:09.64#ibcon#about to read 4, iclass 33, count 0 2006.168.08:17:09.64#ibcon#read 4, iclass 33, count 0 2006.168.08:17:09.64#ibcon#about to read 5, iclass 33, count 0 2006.168.08:17:09.64#ibcon#read 5, iclass 33, count 0 2006.168.08:17:09.64#ibcon#about to read 6, iclass 33, count 0 2006.168.08:17:09.64#ibcon#read 6, iclass 33, count 0 2006.168.08:17:09.64#ibcon#end of sib2, iclass 33, count 0 2006.168.08:17:09.64#ibcon#*mode == 0, iclass 33, count 0 2006.168.08:17:09.64#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.168.08:17:09.64#ibcon#[25=USB\r\n] 2006.168.08:17:09.64#ibcon#*before write, iclass 33, count 0 2006.168.08:17:09.64#ibcon#enter sib2, iclass 33, count 0 2006.168.08:17:09.64#ibcon#flushed, iclass 33, count 0 2006.168.08:17:09.64#ibcon#about to write, iclass 33, count 0 2006.168.08:17:09.64#ibcon#wrote, iclass 33, count 0 2006.168.08:17:09.64#ibcon#about to read 3, iclass 33, count 0 2006.168.08:17:09.67#ibcon#read 3, iclass 33, count 0 2006.168.08:17:09.67#ibcon#about to read 4, iclass 33, count 0 2006.168.08:17:09.67#ibcon#read 4, iclass 33, count 0 2006.168.08:17:09.67#ibcon#about to read 5, iclass 33, count 0 2006.168.08:17:09.67#ibcon#read 5, iclass 33, count 0 2006.168.08:17:09.67#ibcon#about to read 6, iclass 33, count 0 2006.168.08:17:09.67#ibcon#read 6, iclass 33, count 0 2006.168.08:17:09.67#ibcon#end of sib2, iclass 33, count 0 2006.168.08:17:09.67#ibcon#*after write, iclass 33, count 0 2006.168.08:17:09.67#ibcon#*before return 0, iclass 33, count 0 2006.168.08:17:09.67#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.168.08:17:09.67#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.168.08:17:09.67#ibcon#about to clear, iclass 33 cls_cnt 0 2006.168.08:17:09.67#ibcon#cleared, iclass 33 cls_cnt 0 2006.168.08:17:09.67$vc4f8/valo=6,772.99 2006.168.08:17:09.67#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.168.08:17:09.67#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.168.08:17:09.67#ibcon#ireg 17 cls_cnt 0 2006.168.08:17:09.67#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.168.08:17:09.67#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.168.08:17:09.67#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.168.08:17:09.67#ibcon#enter wrdev, iclass 35, count 0 2006.168.08:17:09.67#ibcon#first serial, iclass 35, count 0 2006.168.08:17:09.67#ibcon#enter sib2, iclass 35, count 0 2006.168.08:17:09.67#ibcon#flushed, iclass 35, count 0 2006.168.08:17:09.67#ibcon#about to write, iclass 35, count 0 2006.168.08:17:09.67#ibcon#wrote, iclass 35, count 0 2006.168.08:17:09.67#ibcon#about to read 3, iclass 35, count 0 2006.168.08:17:09.69#ibcon#read 3, iclass 35, count 0 2006.168.08:17:09.69#ibcon#about to read 4, iclass 35, count 0 2006.168.08:17:09.69#ibcon#read 4, iclass 35, count 0 2006.168.08:17:09.69#ibcon#about to read 5, iclass 35, count 0 2006.168.08:17:09.69#ibcon#read 5, iclass 35, count 0 2006.168.08:17:09.69#ibcon#about to read 6, iclass 35, count 0 2006.168.08:17:09.69#ibcon#read 6, iclass 35, count 0 2006.168.08:17:09.69#ibcon#end of sib2, iclass 35, count 0 2006.168.08:17:09.69#ibcon#*mode == 0, iclass 35, count 0 2006.168.08:17:09.69#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.168.08:17:09.69#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.08:17:09.69#ibcon#*before write, iclass 35, count 0 2006.168.08:17:09.69#ibcon#enter sib2, iclass 35, count 0 2006.168.08:17:09.69#ibcon#flushed, iclass 35, count 0 2006.168.08:17:09.69#ibcon#about to write, iclass 35, count 0 2006.168.08:17:09.69#ibcon#wrote, iclass 35, count 0 2006.168.08:17:09.69#ibcon#about to read 3, iclass 35, count 0 2006.168.08:17:09.73#ibcon#read 3, iclass 35, count 0 2006.168.08:17:09.73#ibcon#about to read 4, iclass 35, count 0 2006.168.08:17:09.73#ibcon#read 4, iclass 35, count 0 2006.168.08:17:09.73#ibcon#about to read 5, iclass 35, count 0 2006.168.08:17:09.73#ibcon#read 5, iclass 35, count 0 2006.168.08:17:09.73#ibcon#about to read 6, iclass 35, count 0 2006.168.08:17:09.73#ibcon#read 6, iclass 35, count 0 2006.168.08:17:09.73#ibcon#end of sib2, iclass 35, count 0 2006.168.08:17:09.73#ibcon#*after write, iclass 35, count 0 2006.168.08:17:09.73#ibcon#*before return 0, iclass 35, count 0 2006.168.08:17:09.73#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.168.08:17:09.73#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.168.08:17:09.73#ibcon#about to clear, iclass 35 cls_cnt 0 2006.168.08:17:09.73#ibcon#cleared, iclass 35 cls_cnt 0 2006.168.08:17:09.73$vc4f8/va=6,6 2006.168.08:17:09.73#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.168.08:17:09.73#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.168.08:17:09.73#ibcon#ireg 11 cls_cnt 2 2006.168.08:17:09.73#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.168.08:17:09.79#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.168.08:17:09.79#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.168.08:17:09.79#ibcon#enter wrdev, iclass 37, count 2 2006.168.08:17:09.79#ibcon#first serial, iclass 37, count 2 2006.168.08:17:09.79#ibcon#enter sib2, iclass 37, count 2 2006.168.08:17:09.79#ibcon#flushed, iclass 37, count 2 2006.168.08:17:09.79#ibcon#about to write, iclass 37, count 2 2006.168.08:17:09.79#ibcon#wrote, iclass 37, count 2 2006.168.08:17:09.79#ibcon#about to read 3, iclass 37, count 2 2006.168.08:17:09.81#ibcon#read 3, iclass 37, count 2 2006.168.08:17:09.81#ibcon#about to read 4, iclass 37, count 2 2006.168.08:17:09.81#ibcon#read 4, iclass 37, count 2 2006.168.08:17:09.81#ibcon#about to read 5, iclass 37, count 2 2006.168.08:17:09.81#ibcon#read 5, iclass 37, count 2 2006.168.08:17:09.81#ibcon#about to read 6, iclass 37, count 2 2006.168.08:17:09.81#ibcon#read 6, iclass 37, count 2 2006.168.08:17:09.81#ibcon#end of sib2, iclass 37, count 2 2006.168.08:17:09.81#ibcon#*mode == 0, iclass 37, count 2 2006.168.08:17:09.81#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.168.08:17:09.81#ibcon#[25=AT06-06\r\n] 2006.168.08:17:09.81#ibcon#*before write, iclass 37, count 2 2006.168.08:17:09.81#ibcon#enter sib2, iclass 37, count 2 2006.168.08:17:09.81#ibcon#flushed, iclass 37, count 2 2006.168.08:17:09.81#ibcon#about to write, iclass 37, count 2 2006.168.08:17:09.81#ibcon#wrote, iclass 37, count 2 2006.168.08:17:09.81#ibcon#about to read 3, iclass 37, count 2 2006.168.08:17:09.84#ibcon#read 3, iclass 37, count 2 2006.168.08:17:09.84#ibcon#about to read 4, iclass 37, count 2 2006.168.08:17:09.84#ibcon#read 4, iclass 37, count 2 2006.168.08:17:09.84#ibcon#about to read 5, iclass 37, count 2 2006.168.08:17:09.84#ibcon#read 5, iclass 37, count 2 2006.168.08:17:09.84#ibcon#about to read 6, iclass 37, count 2 2006.168.08:17:09.84#ibcon#read 6, iclass 37, count 2 2006.168.08:17:09.84#ibcon#end of sib2, iclass 37, count 2 2006.168.08:17:09.84#ibcon#*after write, iclass 37, count 2 2006.168.08:17:09.84#ibcon#*before return 0, iclass 37, count 2 2006.168.08:17:09.84#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.168.08:17:09.84#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.168.08:17:09.84#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.168.08:17:09.84#ibcon#ireg 7 cls_cnt 0 2006.168.08:17:09.84#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.168.08:17:09.96#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.168.08:17:09.96#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.168.08:17:09.96#ibcon#enter wrdev, iclass 37, count 0 2006.168.08:17:09.96#ibcon#first serial, iclass 37, count 0 2006.168.08:17:09.96#ibcon#enter sib2, iclass 37, count 0 2006.168.08:17:09.96#ibcon#flushed, iclass 37, count 0 2006.168.08:17:09.96#ibcon#about to write, iclass 37, count 0 2006.168.08:17:09.96#ibcon#wrote, iclass 37, count 0 2006.168.08:17:09.96#ibcon#about to read 3, iclass 37, count 0 2006.168.08:17:09.98#ibcon#read 3, iclass 37, count 0 2006.168.08:17:09.98#ibcon#about to read 4, iclass 37, count 0 2006.168.08:17:09.98#ibcon#read 4, iclass 37, count 0 2006.168.08:17:09.98#ibcon#about to read 5, iclass 37, count 0 2006.168.08:17:09.98#ibcon#read 5, iclass 37, count 0 2006.168.08:17:09.98#ibcon#about to read 6, iclass 37, count 0 2006.168.08:17:09.98#ibcon#read 6, iclass 37, count 0 2006.168.08:17:09.98#ibcon#end of sib2, iclass 37, count 0 2006.168.08:17:09.98#ibcon#*mode == 0, iclass 37, count 0 2006.168.08:17:09.98#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.168.08:17:09.98#ibcon#[25=USB\r\n] 2006.168.08:17:09.98#ibcon#*before write, iclass 37, count 0 2006.168.08:17:09.98#ibcon#enter sib2, iclass 37, count 0 2006.168.08:17:09.98#ibcon#flushed, iclass 37, count 0 2006.168.08:17:09.98#ibcon#about to write, iclass 37, count 0 2006.168.08:17:09.98#ibcon#wrote, iclass 37, count 0 2006.168.08:17:09.98#ibcon#about to read 3, iclass 37, count 0 2006.168.08:17:10.01#ibcon#read 3, iclass 37, count 0 2006.168.08:17:10.01#ibcon#about to read 4, iclass 37, count 0 2006.168.08:17:10.01#ibcon#read 4, iclass 37, count 0 2006.168.08:17:10.01#ibcon#about to read 5, iclass 37, count 0 2006.168.08:17:10.01#ibcon#read 5, iclass 37, count 0 2006.168.08:17:10.01#ibcon#about to read 6, iclass 37, count 0 2006.168.08:17:10.01#ibcon#read 6, iclass 37, count 0 2006.168.08:17:10.01#ibcon#end of sib2, iclass 37, count 0 2006.168.08:17:10.01#ibcon#*after write, iclass 37, count 0 2006.168.08:17:10.01#ibcon#*before return 0, iclass 37, count 0 2006.168.08:17:10.01#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.168.08:17:10.01#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.168.08:17:10.01#ibcon#about to clear, iclass 37 cls_cnt 0 2006.168.08:17:10.01#ibcon#cleared, iclass 37 cls_cnt 0 2006.168.08:17:10.01$vc4f8/valo=7,832.99 2006.168.08:17:10.01#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.168.08:17:10.01#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.168.08:17:10.01#ibcon#ireg 17 cls_cnt 0 2006.168.08:17:10.01#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.168.08:17:10.01#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.168.08:17:10.01#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.168.08:17:10.01#ibcon#enter wrdev, iclass 39, count 0 2006.168.08:17:10.01#ibcon#first serial, iclass 39, count 0 2006.168.08:17:10.01#ibcon#enter sib2, iclass 39, count 0 2006.168.08:17:10.01#ibcon#flushed, iclass 39, count 0 2006.168.08:17:10.01#ibcon#about to write, iclass 39, count 0 2006.168.08:17:10.01#ibcon#wrote, iclass 39, count 0 2006.168.08:17:10.01#ibcon#about to read 3, iclass 39, count 0 2006.168.08:17:10.03#ibcon#read 3, iclass 39, count 0 2006.168.08:17:10.03#ibcon#about to read 4, iclass 39, count 0 2006.168.08:17:10.03#ibcon#read 4, iclass 39, count 0 2006.168.08:17:10.03#ibcon#about to read 5, iclass 39, count 0 2006.168.08:17:10.03#ibcon#read 5, iclass 39, count 0 2006.168.08:17:10.03#ibcon#about to read 6, iclass 39, count 0 2006.168.08:17:10.03#ibcon#read 6, iclass 39, count 0 2006.168.08:17:10.03#ibcon#end of sib2, iclass 39, count 0 2006.168.08:17:10.03#ibcon#*mode == 0, iclass 39, count 0 2006.168.08:17:10.03#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.168.08:17:10.03#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.08:17:10.03#ibcon#*before write, iclass 39, count 0 2006.168.08:17:10.03#ibcon#enter sib2, iclass 39, count 0 2006.168.08:17:10.03#ibcon#flushed, iclass 39, count 0 2006.168.08:17:10.03#ibcon#about to write, iclass 39, count 0 2006.168.08:17:10.03#ibcon#wrote, iclass 39, count 0 2006.168.08:17:10.03#ibcon#about to read 3, iclass 39, count 0 2006.168.08:17:10.07#ibcon#read 3, iclass 39, count 0 2006.168.08:17:10.07#ibcon#about to read 4, iclass 39, count 0 2006.168.08:17:10.07#ibcon#read 4, iclass 39, count 0 2006.168.08:17:10.07#ibcon#about to read 5, iclass 39, count 0 2006.168.08:17:10.07#ibcon#read 5, iclass 39, count 0 2006.168.08:17:10.07#ibcon#about to read 6, iclass 39, count 0 2006.168.08:17:10.07#ibcon#read 6, iclass 39, count 0 2006.168.08:17:10.07#ibcon#end of sib2, iclass 39, count 0 2006.168.08:17:10.07#ibcon#*after write, iclass 39, count 0 2006.168.08:17:10.07#ibcon#*before return 0, iclass 39, count 0 2006.168.08:17:10.07#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.168.08:17:10.07#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.168.08:17:10.07#ibcon#about to clear, iclass 39 cls_cnt 0 2006.168.08:17:10.07#ibcon#cleared, iclass 39 cls_cnt 0 2006.168.08:17:10.07$vc4f8/va=7,6 2006.168.08:17:10.07#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.168.08:17:10.07#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.168.08:17:10.07#ibcon#ireg 11 cls_cnt 2 2006.168.08:17:10.07#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.168.08:17:10.13#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.168.08:17:10.13#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.168.08:17:10.13#ibcon#enter wrdev, iclass 3, count 2 2006.168.08:17:10.13#ibcon#first serial, iclass 3, count 2 2006.168.08:17:10.13#ibcon#enter sib2, iclass 3, count 2 2006.168.08:17:10.13#ibcon#flushed, iclass 3, count 2 2006.168.08:17:10.13#ibcon#about to write, iclass 3, count 2 2006.168.08:17:10.13#ibcon#wrote, iclass 3, count 2 2006.168.08:17:10.13#ibcon#about to read 3, iclass 3, count 2 2006.168.08:17:10.15#ibcon#read 3, iclass 3, count 2 2006.168.08:17:10.15#ibcon#about to read 4, iclass 3, count 2 2006.168.08:17:10.15#ibcon#read 4, iclass 3, count 2 2006.168.08:17:10.15#ibcon#about to read 5, iclass 3, count 2 2006.168.08:17:10.15#ibcon#read 5, iclass 3, count 2 2006.168.08:17:10.15#ibcon#about to read 6, iclass 3, count 2 2006.168.08:17:10.15#ibcon#read 6, iclass 3, count 2 2006.168.08:17:10.15#ibcon#end of sib2, iclass 3, count 2 2006.168.08:17:10.15#ibcon#*mode == 0, iclass 3, count 2 2006.168.08:17:10.15#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.168.08:17:10.15#ibcon#[25=AT07-06\r\n] 2006.168.08:17:10.15#ibcon#*before write, iclass 3, count 2 2006.168.08:17:10.15#ibcon#enter sib2, iclass 3, count 2 2006.168.08:17:10.15#ibcon#flushed, iclass 3, count 2 2006.168.08:17:10.15#ibcon#about to write, iclass 3, count 2 2006.168.08:17:10.15#ibcon#wrote, iclass 3, count 2 2006.168.08:17:10.15#ibcon#about to read 3, iclass 3, count 2 2006.168.08:17:10.18#ibcon#read 3, iclass 3, count 2 2006.168.08:17:10.18#ibcon#about to read 4, iclass 3, count 2 2006.168.08:17:10.18#ibcon#read 4, iclass 3, count 2 2006.168.08:17:10.18#ibcon#about to read 5, iclass 3, count 2 2006.168.08:17:10.18#ibcon#read 5, iclass 3, count 2 2006.168.08:17:10.18#ibcon#about to read 6, iclass 3, count 2 2006.168.08:17:10.18#ibcon#read 6, iclass 3, count 2 2006.168.08:17:10.18#ibcon#end of sib2, iclass 3, count 2 2006.168.08:17:10.18#ibcon#*after write, iclass 3, count 2 2006.168.08:17:10.18#ibcon#*before return 0, iclass 3, count 2 2006.168.08:17:10.18#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.168.08:17:10.18#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.168.08:17:10.18#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.168.08:17:10.18#ibcon#ireg 7 cls_cnt 0 2006.168.08:17:10.18#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.168.08:17:10.30#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.168.08:17:10.30#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.168.08:17:10.30#ibcon#enter wrdev, iclass 3, count 0 2006.168.08:17:10.30#ibcon#first serial, iclass 3, count 0 2006.168.08:17:10.30#ibcon#enter sib2, iclass 3, count 0 2006.168.08:17:10.30#ibcon#flushed, iclass 3, count 0 2006.168.08:17:10.30#ibcon#about to write, iclass 3, count 0 2006.168.08:17:10.30#ibcon#wrote, iclass 3, count 0 2006.168.08:17:10.30#ibcon#about to read 3, iclass 3, count 0 2006.168.08:17:10.32#ibcon#read 3, iclass 3, count 0 2006.168.08:17:10.32#ibcon#about to read 4, iclass 3, count 0 2006.168.08:17:10.32#ibcon#read 4, iclass 3, count 0 2006.168.08:17:10.32#ibcon#about to read 5, iclass 3, count 0 2006.168.08:17:10.32#ibcon#read 5, iclass 3, count 0 2006.168.08:17:10.32#ibcon#about to read 6, iclass 3, count 0 2006.168.08:17:10.32#ibcon#read 6, iclass 3, count 0 2006.168.08:17:10.32#ibcon#end of sib2, iclass 3, count 0 2006.168.08:17:10.32#ibcon#*mode == 0, iclass 3, count 0 2006.168.08:17:10.32#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.168.08:17:10.32#ibcon#[25=USB\r\n] 2006.168.08:17:10.32#ibcon#*before write, iclass 3, count 0 2006.168.08:17:10.32#ibcon#enter sib2, iclass 3, count 0 2006.168.08:17:10.32#ibcon#flushed, iclass 3, count 0 2006.168.08:17:10.32#ibcon#about to write, iclass 3, count 0 2006.168.08:17:10.32#ibcon#wrote, iclass 3, count 0 2006.168.08:17:10.32#ibcon#about to read 3, iclass 3, count 0 2006.168.08:17:10.35#ibcon#read 3, iclass 3, count 0 2006.168.08:17:10.35#ibcon#about to read 4, iclass 3, count 0 2006.168.08:17:10.35#ibcon#read 4, iclass 3, count 0 2006.168.08:17:10.35#ibcon#about to read 5, iclass 3, count 0 2006.168.08:17:10.35#ibcon#read 5, iclass 3, count 0 2006.168.08:17:10.35#ibcon#about to read 6, iclass 3, count 0 2006.168.08:17:10.35#ibcon#read 6, iclass 3, count 0 2006.168.08:17:10.35#ibcon#end of sib2, iclass 3, count 0 2006.168.08:17:10.35#ibcon#*after write, iclass 3, count 0 2006.168.08:17:10.35#ibcon#*before return 0, iclass 3, count 0 2006.168.08:17:10.35#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.168.08:17:10.35#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.168.08:17:10.35#ibcon#about to clear, iclass 3 cls_cnt 0 2006.168.08:17:10.35#ibcon#cleared, iclass 3 cls_cnt 0 2006.168.08:17:10.35$vc4f8/valo=8,852.99 2006.168.08:17:10.35#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.168.08:17:10.35#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.168.08:17:10.35#ibcon#ireg 17 cls_cnt 0 2006.168.08:17:10.35#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.168.08:17:10.35#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.168.08:17:10.35#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.168.08:17:10.35#ibcon#enter wrdev, iclass 5, count 0 2006.168.08:17:10.35#ibcon#first serial, iclass 5, count 0 2006.168.08:17:10.35#ibcon#enter sib2, iclass 5, count 0 2006.168.08:17:10.35#ibcon#flushed, iclass 5, count 0 2006.168.08:17:10.35#ibcon#about to write, iclass 5, count 0 2006.168.08:17:10.35#ibcon#wrote, iclass 5, count 0 2006.168.08:17:10.35#ibcon#about to read 3, iclass 5, count 0 2006.168.08:17:10.37#ibcon#read 3, iclass 5, count 0 2006.168.08:17:10.37#ibcon#about to read 4, iclass 5, count 0 2006.168.08:17:10.37#ibcon#read 4, iclass 5, count 0 2006.168.08:17:10.37#ibcon#about to read 5, iclass 5, count 0 2006.168.08:17:10.37#ibcon#read 5, iclass 5, count 0 2006.168.08:17:10.37#ibcon#about to read 6, iclass 5, count 0 2006.168.08:17:10.37#ibcon#read 6, iclass 5, count 0 2006.168.08:17:10.37#ibcon#end of sib2, iclass 5, count 0 2006.168.08:17:10.37#ibcon#*mode == 0, iclass 5, count 0 2006.168.08:17:10.37#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.168.08:17:10.37#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.08:17:10.37#ibcon#*before write, iclass 5, count 0 2006.168.08:17:10.37#ibcon#enter sib2, iclass 5, count 0 2006.168.08:17:10.37#ibcon#flushed, iclass 5, count 0 2006.168.08:17:10.37#ibcon#about to write, iclass 5, count 0 2006.168.08:17:10.37#ibcon#wrote, iclass 5, count 0 2006.168.08:17:10.37#ibcon#about to read 3, iclass 5, count 0 2006.168.08:17:10.41#ibcon#read 3, iclass 5, count 0 2006.168.08:17:10.41#ibcon#about to read 4, iclass 5, count 0 2006.168.08:17:10.41#ibcon#read 4, iclass 5, count 0 2006.168.08:17:10.41#ibcon#about to read 5, iclass 5, count 0 2006.168.08:17:10.41#ibcon#read 5, iclass 5, count 0 2006.168.08:17:10.41#ibcon#about to read 6, iclass 5, count 0 2006.168.08:17:10.41#ibcon#read 6, iclass 5, count 0 2006.168.08:17:10.41#ibcon#end of sib2, iclass 5, count 0 2006.168.08:17:10.41#ibcon#*after write, iclass 5, count 0 2006.168.08:17:10.41#ibcon#*before return 0, iclass 5, count 0 2006.168.08:17:10.41#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.168.08:17:10.41#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.168.08:17:10.41#ibcon#about to clear, iclass 5 cls_cnt 0 2006.168.08:17:10.41#ibcon#cleared, iclass 5 cls_cnt 0 2006.168.08:17:10.41$vc4f8/va=8,7 2006.168.08:17:10.41#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.168.08:17:10.41#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.168.08:17:10.41#ibcon#ireg 11 cls_cnt 2 2006.168.08:17:10.41#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.168.08:17:10.47#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.168.08:17:10.47#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.168.08:17:10.47#ibcon#enter wrdev, iclass 7, count 2 2006.168.08:17:10.47#ibcon#first serial, iclass 7, count 2 2006.168.08:17:10.47#ibcon#enter sib2, iclass 7, count 2 2006.168.08:17:10.47#ibcon#flushed, iclass 7, count 2 2006.168.08:17:10.47#ibcon#about to write, iclass 7, count 2 2006.168.08:17:10.47#ibcon#wrote, iclass 7, count 2 2006.168.08:17:10.47#ibcon#about to read 3, iclass 7, count 2 2006.168.08:17:10.49#ibcon#read 3, iclass 7, count 2 2006.168.08:17:10.49#ibcon#about to read 4, iclass 7, count 2 2006.168.08:17:10.49#ibcon#read 4, iclass 7, count 2 2006.168.08:17:10.49#ibcon#about to read 5, iclass 7, count 2 2006.168.08:17:10.49#ibcon#read 5, iclass 7, count 2 2006.168.08:17:10.49#ibcon#about to read 6, iclass 7, count 2 2006.168.08:17:10.49#ibcon#read 6, iclass 7, count 2 2006.168.08:17:10.49#ibcon#end of sib2, iclass 7, count 2 2006.168.08:17:10.49#ibcon#*mode == 0, iclass 7, count 2 2006.168.08:17:10.49#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.168.08:17:10.49#ibcon#[25=AT08-07\r\n] 2006.168.08:17:10.49#ibcon#*before write, iclass 7, count 2 2006.168.08:17:10.49#ibcon#enter sib2, iclass 7, count 2 2006.168.08:17:10.49#ibcon#flushed, iclass 7, count 2 2006.168.08:17:10.49#ibcon#about to write, iclass 7, count 2 2006.168.08:17:10.49#ibcon#wrote, iclass 7, count 2 2006.168.08:17:10.49#ibcon#about to read 3, iclass 7, count 2 2006.168.08:17:10.53#ibcon#read 3, iclass 7, count 2 2006.168.08:17:10.53#ibcon#about to read 4, iclass 7, count 2 2006.168.08:17:10.53#ibcon#read 4, iclass 7, count 2 2006.168.08:17:10.53#ibcon#about to read 5, iclass 7, count 2 2006.168.08:17:10.53#ibcon#read 5, iclass 7, count 2 2006.168.08:17:10.53#ibcon#about to read 6, iclass 7, count 2 2006.168.08:17:10.53#ibcon#read 6, iclass 7, count 2 2006.168.08:17:10.53#ibcon#end of sib2, iclass 7, count 2 2006.168.08:17:10.53#ibcon#*after write, iclass 7, count 2 2006.168.08:17:10.53#ibcon#*before return 0, iclass 7, count 2 2006.168.08:17:10.53#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.168.08:17:10.53#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.168.08:17:10.53#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.168.08:17:10.53#ibcon#ireg 7 cls_cnt 0 2006.168.08:17:10.53#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.168.08:17:10.65#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.168.08:17:10.65#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.168.08:17:10.65#ibcon#enter wrdev, iclass 7, count 0 2006.168.08:17:10.65#ibcon#first serial, iclass 7, count 0 2006.168.08:17:10.65#ibcon#enter sib2, iclass 7, count 0 2006.168.08:17:10.65#ibcon#flushed, iclass 7, count 0 2006.168.08:17:10.65#ibcon#about to write, iclass 7, count 0 2006.168.08:17:10.65#ibcon#wrote, iclass 7, count 0 2006.168.08:17:10.65#ibcon#about to read 3, iclass 7, count 0 2006.168.08:17:10.67#ibcon#read 3, iclass 7, count 0 2006.168.08:17:10.67#ibcon#about to read 4, iclass 7, count 0 2006.168.08:17:10.67#ibcon#read 4, iclass 7, count 0 2006.168.08:17:10.67#ibcon#about to read 5, iclass 7, count 0 2006.168.08:17:10.67#ibcon#read 5, iclass 7, count 0 2006.168.08:17:10.67#ibcon#about to read 6, iclass 7, count 0 2006.168.08:17:10.67#ibcon#read 6, iclass 7, count 0 2006.168.08:17:10.67#ibcon#end of sib2, iclass 7, count 0 2006.168.08:17:10.67#ibcon#*mode == 0, iclass 7, count 0 2006.168.08:17:10.67#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.168.08:17:10.67#ibcon#[25=USB\r\n] 2006.168.08:17:10.67#ibcon#*before write, iclass 7, count 0 2006.168.08:17:10.67#ibcon#enter sib2, iclass 7, count 0 2006.168.08:17:10.67#ibcon#flushed, iclass 7, count 0 2006.168.08:17:10.67#ibcon#about to write, iclass 7, count 0 2006.168.08:17:10.67#ibcon#wrote, iclass 7, count 0 2006.168.08:17:10.67#ibcon#about to read 3, iclass 7, count 0 2006.168.08:17:10.70#ibcon#read 3, iclass 7, count 0 2006.168.08:17:10.70#ibcon#about to read 4, iclass 7, count 0 2006.168.08:17:10.70#ibcon#read 4, iclass 7, count 0 2006.168.08:17:10.70#ibcon#about to read 5, iclass 7, count 0 2006.168.08:17:10.70#ibcon#read 5, iclass 7, count 0 2006.168.08:17:10.70#ibcon#about to read 6, iclass 7, count 0 2006.168.08:17:10.70#ibcon#read 6, iclass 7, count 0 2006.168.08:17:10.70#ibcon#end of sib2, iclass 7, count 0 2006.168.08:17:10.70#ibcon#*after write, iclass 7, count 0 2006.168.08:17:10.70#ibcon#*before return 0, iclass 7, count 0 2006.168.08:17:10.70#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.168.08:17:10.70#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.168.08:17:10.70#ibcon#about to clear, iclass 7 cls_cnt 0 2006.168.08:17:10.70#ibcon#cleared, iclass 7 cls_cnt 0 2006.168.08:17:10.70$vc4f8/vblo=1,632.99 2006.168.08:17:10.70#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.168.08:17:10.70#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.168.08:17:10.70#ibcon#ireg 17 cls_cnt 0 2006.168.08:17:10.70#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.168.08:17:10.70#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.168.08:17:10.70#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.168.08:17:10.70#ibcon#enter wrdev, iclass 11, count 0 2006.168.08:17:10.70#ibcon#first serial, iclass 11, count 0 2006.168.08:17:10.70#ibcon#enter sib2, iclass 11, count 0 2006.168.08:17:10.70#ibcon#flushed, iclass 11, count 0 2006.168.08:17:10.70#ibcon#about to write, iclass 11, count 0 2006.168.08:17:10.70#ibcon#wrote, iclass 11, count 0 2006.168.08:17:10.70#ibcon#about to read 3, iclass 11, count 0 2006.168.08:17:10.72#ibcon#read 3, iclass 11, count 0 2006.168.08:17:10.72#ibcon#about to read 4, iclass 11, count 0 2006.168.08:17:10.72#ibcon#read 4, iclass 11, count 0 2006.168.08:17:10.72#ibcon#about to read 5, iclass 11, count 0 2006.168.08:17:10.72#ibcon#read 5, iclass 11, count 0 2006.168.08:17:10.72#ibcon#about to read 6, iclass 11, count 0 2006.168.08:17:10.72#ibcon#read 6, iclass 11, count 0 2006.168.08:17:10.72#ibcon#end of sib2, iclass 11, count 0 2006.168.08:17:10.72#ibcon#*mode == 0, iclass 11, count 0 2006.168.08:17:10.72#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.168.08:17:10.72#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.08:17:10.72#ibcon#*before write, iclass 11, count 0 2006.168.08:17:10.72#ibcon#enter sib2, iclass 11, count 0 2006.168.08:17:10.72#ibcon#flushed, iclass 11, count 0 2006.168.08:17:10.72#ibcon#about to write, iclass 11, count 0 2006.168.08:17:10.72#ibcon#wrote, iclass 11, count 0 2006.168.08:17:10.72#ibcon#about to read 3, iclass 11, count 0 2006.168.08:17:10.76#ibcon#read 3, iclass 11, count 0 2006.168.08:17:10.76#ibcon#about to read 4, iclass 11, count 0 2006.168.08:17:10.76#ibcon#read 4, iclass 11, count 0 2006.168.08:17:10.76#ibcon#about to read 5, iclass 11, count 0 2006.168.08:17:10.76#ibcon#read 5, iclass 11, count 0 2006.168.08:17:10.76#ibcon#about to read 6, iclass 11, count 0 2006.168.08:17:10.76#ibcon#read 6, iclass 11, count 0 2006.168.08:17:10.76#ibcon#end of sib2, iclass 11, count 0 2006.168.08:17:10.76#ibcon#*after write, iclass 11, count 0 2006.168.08:17:10.76#ibcon#*before return 0, iclass 11, count 0 2006.168.08:17:10.76#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.168.08:17:10.76#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.168.08:17:10.76#ibcon#about to clear, iclass 11 cls_cnt 0 2006.168.08:17:10.76#ibcon#cleared, iclass 11 cls_cnt 0 2006.168.08:17:10.76$vc4f8/vb=1,4 2006.168.08:17:10.76#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.168.08:17:10.76#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.168.08:17:10.76#ibcon#ireg 11 cls_cnt 2 2006.168.08:17:10.76#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.168.08:17:10.76#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.168.08:17:10.76#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.168.08:17:10.76#ibcon#enter wrdev, iclass 13, count 2 2006.168.08:17:10.76#ibcon#first serial, iclass 13, count 2 2006.168.08:17:10.76#ibcon#enter sib2, iclass 13, count 2 2006.168.08:17:10.76#ibcon#flushed, iclass 13, count 2 2006.168.08:17:10.76#ibcon#about to write, iclass 13, count 2 2006.168.08:17:10.76#ibcon#wrote, iclass 13, count 2 2006.168.08:17:10.76#ibcon#about to read 3, iclass 13, count 2 2006.168.08:17:10.78#ibcon#read 3, iclass 13, count 2 2006.168.08:17:10.78#ibcon#about to read 4, iclass 13, count 2 2006.168.08:17:10.78#ibcon#read 4, iclass 13, count 2 2006.168.08:17:10.78#ibcon#about to read 5, iclass 13, count 2 2006.168.08:17:10.78#ibcon#read 5, iclass 13, count 2 2006.168.08:17:10.78#ibcon#about to read 6, iclass 13, count 2 2006.168.08:17:10.78#ibcon#read 6, iclass 13, count 2 2006.168.08:17:10.78#ibcon#end of sib2, iclass 13, count 2 2006.168.08:17:10.78#ibcon#*mode == 0, iclass 13, count 2 2006.168.08:17:10.78#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.168.08:17:10.78#ibcon#[27=AT01-04\r\n] 2006.168.08:17:10.78#ibcon#*before write, iclass 13, count 2 2006.168.08:17:10.78#ibcon#enter sib2, iclass 13, count 2 2006.168.08:17:10.78#ibcon#flushed, iclass 13, count 2 2006.168.08:17:10.78#ibcon#about to write, iclass 13, count 2 2006.168.08:17:10.78#ibcon#wrote, iclass 13, count 2 2006.168.08:17:10.78#ibcon#about to read 3, iclass 13, count 2 2006.168.08:17:10.81#ibcon#read 3, iclass 13, count 2 2006.168.08:17:10.81#ibcon#about to read 4, iclass 13, count 2 2006.168.08:17:10.81#ibcon#read 4, iclass 13, count 2 2006.168.08:17:10.81#ibcon#about to read 5, iclass 13, count 2 2006.168.08:17:10.81#ibcon#read 5, iclass 13, count 2 2006.168.08:17:10.81#ibcon#about to read 6, iclass 13, count 2 2006.168.08:17:10.81#ibcon#read 6, iclass 13, count 2 2006.168.08:17:10.81#ibcon#end of sib2, iclass 13, count 2 2006.168.08:17:10.81#ibcon#*after write, iclass 13, count 2 2006.168.08:17:10.81#ibcon#*before return 0, iclass 13, count 2 2006.168.08:17:10.81#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.168.08:17:10.81#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.168.08:17:10.81#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.168.08:17:10.81#ibcon#ireg 7 cls_cnt 0 2006.168.08:17:10.81#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.168.08:17:10.93#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.168.08:17:10.93#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.168.08:17:10.93#ibcon#enter wrdev, iclass 13, count 0 2006.168.08:17:10.93#ibcon#first serial, iclass 13, count 0 2006.168.08:17:10.93#ibcon#enter sib2, iclass 13, count 0 2006.168.08:17:10.93#ibcon#flushed, iclass 13, count 0 2006.168.08:17:10.93#ibcon#about to write, iclass 13, count 0 2006.168.08:17:10.93#ibcon#wrote, iclass 13, count 0 2006.168.08:17:10.93#ibcon#about to read 3, iclass 13, count 0 2006.168.08:17:10.95#ibcon#read 3, iclass 13, count 0 2006.168.08:17:10.95#ibcon#about to read 4, iclass 13, count 0 2006.168.08:17:10.95#ibcon#read 4, iclass 13, count 0 2006.168.08:17:10.95#ibcon#about to read 5, iclass 13, count 0 2006.168.08:17:10.95#ibcon#read 5, iclass 13, count 0 2006.168.08:17:10.95#ibcon#about to read 6, iclass 13, count 0 2006.168.08:17:10.95#ibcon#read 6, iclass 13, count 0 2006.168.08:17:10.95#ibcon#end of sib2, iclass 13, count 0 2006.168.08:17:10.95#ibcon#*mode == 0, iclass 13, count 0 2006.168.08:17:10.95#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.168.08:17:10.95#ibcon#[27=USB\r\n] 2006.168.08:17:10.95#ibcon#*before write, iclass 13, count 0 2006.168.08:17:10.95#ibcon#enter sib2, iclass 13, count 0 2006.168.08:17:10.95#ibcon#flushed, iclass 13, count 0 2006.168.08:17:10.95#ibcon#about to write, iclass 13, count 0 2006.168.08:17:10.95#ibcon#wrote, iclass 13, count 0 2006.168.08:17:10.95#ibcon#about to read 3, iclass 13, count 0 2006.168.08:17:10.98#ibcon#read 3, iclass 13, count 0 2006.168.08:17:10.98#ibcon#about to read 4, iclass 13, count 0 2006.168.08:17:10.98#ibcon#read 4, iclass 13, count 0 2006.168.08:17:10.98#ibcon#about to read 5, iclass 13, count 0 2006.168.08:17:10.98#ibcon#read 5, iclass 13, count 0 2006.168.08:17:10.98#ibcon#about to read 6, iclass 13, count 0 2006.168.08:17:10.98#ibcon#read 6, iclass 13, count 0 2006.168.08:17:10.98#ibcon#end of sib2, iclass 13, count 0 2006.168.08:17:10.98#ibcon#*after write, iclass 13, count 0 2006.168.08:17:10.98#ibcon#*before return 0, iclass 13, count 0 2006.168.08:17:10.98#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.168.08:17:10.98#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.168.08:17:10.98#ibcon#about to clear, iclass 13 cls_cnt 0 2006.168.08:17:10.98#ibcon#cleared, iclass 13 cls_cnt 0 2006.168.08:17:10.98$vc4f8/vblo=2,640.99 2006.168.08:17:10.98#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.168.08:17:10.98#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.168.08:17:10.98#ibcon#ireg 17 cls_cnt 0 2006.168.08:17:10.98#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:17:10.98#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:17:10.98#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:17:10.98#ibcon#enter wrdev, iclass 15, count 0 2006.168.08:17:10.98#ibcon#first serial, iclass 15, count 0 2006.168.08:17:10.98#ibcon#enter sib2, iclass 15, count 0 2006.168.08:17:10.98#ibcon#flushed, iclass 15, count 0 2006.168.08:17:10.98#ibcon#about to write, iclass 15, count 0 2006.168.08:17:10.98#ibcon#wrote, iclass 15, count 0 2006.168.08:17:10.98#ibcon#about to read 3, iclass 15, count 0 2006.168.08:17:11.00#ibcon#read 3, iclass 15, count 0 2006.168.08:17:11.00#ibcon#about to read 4, iclass 15, count 0 2006.168.08:17:11.00#ibcon#read 4, iclass 15, count 0 2006.168.08:17:11.00#ibcon#about to read 5, iclass 15, count 0 2006.168.08:17:11.00#ibcon#read 5, iclass 15, count 0 2006.168.08:17:11.00#ibcon#about to read 6, iclass 15, count 0 2006.168.08:17:11.00#ibcon#read 6, iclass 15, count 0 2006.168.08:17:11.00#ibcon#end of sib2, iclass 15, count 0 2006.168.08:17:11.00#ibcon#*mode == 0, iclass 15, count 0 2006.168.08:17:11.00#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.168.08:17:11.00#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.08:17:11.00#ibcon#*before write, iclass 15, count 0 2006.168.08:17:11.00#ibcon#enter sib2, iclass 15, count 0 2006.168.08:17:11.00#ibcon#flushed, iclass 15, count 0 2006.168.08:17:11.00#ibcon#about to write, iclass 15, count 0 2006.168.08:17:11.00#ibcon#wrote, iclass 15, count 0 2006.168.08:17:11.00#ibcon#about to read 3, iclass 15, count 0 2006.168.08:17:11.04#ibcon#read 3, iclass 15, count 0 2006.168.08:17:11.04#ibcon#about to read 4, iclass 15, count 0 2006.168.08:17:11.04#ibcon#read 4, iclass 15, count 0 2006.168.08:17:11.04#ibcon#about to read 5, iclass 15, count 0 2006.168.08:17:11.04#ibcon#read 5, iclass 15, count 0 2006.168.08:17:11.04#ibcon#about to read 6, iclass 15, count 0 2006.168.08:17:11.04#ibcon#read 6, iclass 15, count 0 2006.168.08:17:11.04#ibcon#end of sib2, iclass 15, count 0 2006.168.08:17:11.04#ibcon#*after write, iclass 15, count 0 2006.168.08:17:11.04#ibcon#*before return 0, iclass 15, count 0 2006.168.08:17:11.04#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:17:11.04#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.168.08:17:11.04#ibcon#about to clear, iclass 15 cls_cnt 0 2006.168.08:17:11.04#ibcon#cleared, iclass 15 cls_cnt 0 2006.168.08:17:11.04$vc4f8/vb=2,4 2006.168.08:17:11.04#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.168.08:17:11.04#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.168.08:17:11.04#ibcon#ireg 11 cls_cnt 2 2006.168.08:17:11.04#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.168.08:17:11.10#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.168.08:17:11.10#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.168.08:17:11.10#ibcon#enter wrdev, iclass 17, count 2 2006.168.08:17:11.10#ibcon#first serial, iclass 17, count 2 2006.168.08:17:11.10#ibcon#enter sib2, iclass 17, count 2 2006.168.08:17:11.10#ibcon#flushed, iclass 17, count 2 2006.168.08:17:11.10#ibcon#about to write, iclass 17, count 2 2006.168.08:17:11.10#ibcon#wrote, iclass 17, count 2 2006.168.08:17:11.10#ibcon#about to read 3, iclass 17, count 2 2006.168.08:17:11.12#ibcon#read 3, iclass 17, count 2 2006.168.08:17:11.12#ibcon#about to read 4, iclass 17, count 2 2006.168.08:17:11.12#ibcon#read 4, iclass 17, count 2 2006.168.08:17:11.12#ibcon#about to read 5, iclass 17, count 2 2006.168.08:17:11.12#ibcon#read 5, iclass 17, count 2 2006.168.08:17:11.12#ibcon#about to read 6, iclass 17, count 2 2006.168.08:17:11.12#ibcon#read 6, iclass 17, count 2 2006.168.08:17:11.12#ibcon#end of sib2, iclass 17, count 2 2006.168.08:17:11.12#ibcon#*mode == 0, iclass 17, count 2 2006.168.08:17:11.12#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.168.08:17:11.12#ibcon#[27=AT02-04\r\n] 2006.168.08:17:11.12#ibcon#*before write, iclass 17, count 2 2006.168.08:17:11.12#ibcon#enter sib2, iclass 17, count 2 2006.168.08:17:11.12#ibcon#flushed, iclass 17, count 2 2006.168.08:17:11.12#ibcon#about to write, iclass 17, count 2 2006.168.08:17:11.12#ibcon#wrote, iclass 17, count 2 2006.168.08:17:11.12#ibcon#about to read 3, iclass 17, count 2 2006.168.08:17:11.15#ibcon#read 3, iclass 17, count 2 2006.168.08:17:11.15#ibcon#about to read 4, iclass 17, count 2 2006.168.08:17:11.15#ibcon#read 4, iclass 17, count 2 2006.168.08:17:11.15#ibcon#about to read 5, iclass 17, count 2 2006.168.08:17:11.15#ibcon#read 5, iclass 17, count 2 2006.168.08:17:11.15#ibcon#about to read 6, iclass 17, count 2 2006.168.08:17:11.15#ibcon#read 6, iclass 17, count 2 2006.168.08:17:11.15#ibcon#end of sib2, iclass 17, count 2 2006.168.08:17:11.15#ibcon#*after write, iclass 17, count 2 2006.168.08:17:11.15#ibcon#*before return 0, iclass 17, count 2 2006.168.08:17:11.15#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.168.08:17:11.15#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.168.08:17:11.15#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.168.08:17:11.15#ibcon#ireg 7 cls_cnt 0 2006.168.08:17:11.15#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.168.08:17:11.27#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.168.08:17:11.27#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.168.08:17:11.27#ibcon#enter wrdev, iclass 17, count 0 2006.168.08:17:11.27#ibcon#first serial, iclass 17, count 0 2006.168.08:17:11.27#ibcon#enter sib2, iclass 17, count 0 2006.168.08:17:11.27#ibcon#flushed, iclass 17, count 0 2006.168.08:17:11.27#ibcon#about to write, iclass 17, count 0 2006.168.08:17:11.27#ibcon#wrote, iclass 17, count 0 2006.168.08:17:11.27#ibcon#about to read 3, iclass 17, count 0 2006.168.08:17:11.29#ibcon#read 3, iclass 17, count 0 2006.168.08:17:11.29#ibcon#about to read 4, iclass 17, count 0 2006.168.08:17:11.29#ibcon#read 4, iclass 17, count 0 2006.168.08:17:11.29#ibcon#about to read 5, iclass 17, count 0 2006.168.08:17:11.29#ibcon#read 5, iclass 17, count 0 2006.168.08:17:11.29#ibcon#about to read 6, iclass 17, count 0 2006.168.08:17:11.29#ibcon#read 6, iclass 17, count 0 2006.168.08:17:11.29#ibcon#end of sib2, iclass 17, count 0 2006.168.08:17:11.29#ibcon#*mode == 0, iclass 17, count 0 2006.168.08:17:11.29#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.168.08:17:11.29#ibcon#[27=USB\r\n] 2006.168.08:17:11.29#ibcon#*before write, iclass 17, count 0 2006.168.08:17:11.29#ibcon#enter sib2, iclass 17, count 0 2006.168.08:17:11.29#ibcon#flushed, iclass 17, count 0 2006.168.08:17:11.29#ibcon#about to write, iclass 17, count 0 2006.168.08:17:11.29#ibcon#wrote, iclass 17, count 0 2006.168.08:17:11.29#ibcon#about to read 3, iclass 17, count 0 2006.168.08:17:11.32#ibcon#read 3, iclass 17, count 0 2006.168.08:17:11.32#ibcon#about to read 4, iclass 17, count 0 2006.168.08:17:11.32#ibcon#read 4, iclass 17, count 0 2006.168.08:17:11.32#ibcon#about to read 5, iclass 17, count 0 2006.168.08:17:11.32#ibcon#read 5, iclass 17, count 0 2006.168.08:17:11.32#ibcon#about to read 6, iclass 17, count 0 2006.168.08:17:11.32#ibcon#read 6, iclass 17, count 0 2006.168.08:17:11.32#ibcon#end of sib2, iclass 17, count 0 2006.168.08:17:11.32#ibcon#*after write, iclass 17, count 0 2006.168.08:17:11.32#ibcon#*before return 0, iclass 17, count 0 2006.168.08:17:11.32#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.168.08:17:11.32#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.168.08:17:11.32#ibcon#about to clear, iclass 17 cls_cnt 0 2006.168.08:17:11.32#ibcon#cleared, iclass 17 cls_cnt 0 2006.168.08:17:11.32$vc4f8/vblo=3,656.99 2006.168.08:17:11.32#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.168.08:17:11.32#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.168.08:17:11.32#ibcon#ireg 17 cls_cnt 0 2006.168.08:17:11.32#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.168.08:17:11.32#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.168.08:17:11.32#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.168.08:17:11.32#ibcon#enter wrdev, iclass 19, count 0 2006.168.08:17:11.32#ibcon#first serial, iclass 19, count 0 2006.168.08:17:11.32#ibcon#enter sib2, iclass 19, count 0 2006.168.08:17:11.32#ibcon#flushed, iclass 19, count 0 2006.168.08:17:11.32#ibcon#about to write, iclass 19, count 0 2006.168.08:17:11.32#ibcon#wrote, iclass 19, count 0 2006.168.08:17:11.32#ibcon#about to read 3, iclass 19, count 0 2006.168.08:17:11.34#ibcon#read 3, iclass 19, count 0 2006.168.08:17:11.34#ibcon#about to read 4, iclass 19, count 0 2006.168.08:17:11.34#ibcon#read 4, iclass 19, count 0 2006.168.08:17:11.34#ibcon#about to read 5, iclass 19, count 0 2006.168.08:17:11.34#ibcon#read 5, iclass 19, count 0 2006.168.08:17:11.34#ibcon#about to read 6, iclass 19, count 0 2006.168.08:17:11.34#ibcon#read 6, iclass 19, count 0 2006.168.08:17:11.34#ibcon#end of sib2, iclass 19, count 0 2006.168.08:17:11.34#ibcon#*mode == 0, iclass 19, count 0 2006.168.08:17:11.34#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.168.08:17:11.34#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.08:17:11.34#ibcon#*before write, iclass 19, count 0 2006.168.08:17:11.34#ibcon#enter sib2, iclass 19, count 0 2006.168.08:17:11.34#ibcon#flushed, iclass 19, count 0 2006.168.08:17:11.34#ibcon#about to write, iclass 19, count 0 2006.168.08:17:11.34#ibcon#wrote, iclass 19, count 0 2006.168.08:17:11.34#ibcon#about to read 3, iclass 19, count 0 2006.168.08:17:11.38#ibcon#read 3, iclass 19, count 0 2006.168.08:17:11.38#ibcon#about to read 4, iclass 19, count 0 2006.168.08:17:11.38#ibcon#read 4, iclass 19, count 0 2006.168.08:17:11.38#ibcon#about to read 5, iclass 19, count 0 2006.168.08:17:11.38#ibcon#read 5, iclass 19, count 0 2006.168.08:17:11.38#ibcon#about to read 6, iclass 19, count 0 2006.168.08:17:11.38#ibcon#read 6, iclass 19, count 0 2006.168.08:17:11.38#ibcon#end of sib2, iclass 19, count 0 2006.168.08:17:11.38#ibcon#*after write, iclass 19, count 0 2006.168.08:17:11.38#ibcon#*before return 0, iclass 19, count 0 2006.168.08:17:11.38#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.168.08:17:11.38#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.168.08:17:11.38#ibcon#about to clear, iclass 19 cls_cnt 0 2006.168.08:17:11.38#ibcon#cleared, iclass 19 cls_cnt 0 2006.168.08:17:11.38$vc4f8/vb=3,4 2006.168.08:17:11.38#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.168.08:17:11.38#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.168.08:17:11.38#ibcon#ireg 11 cls_cnt 2 2006.168.08:17:11.38#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.168.08:17:11.44#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.168.08:17:11.44#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.168.08:17:11.44#ibcon#enter wrdev, iclass 21, count 2 2006.168.08:17:11.44#ibcon#first serial, iclass 21, count 2 2006.168.08:17:11.44#ibcon#enter sib2, iclass 21, count 2 2006.168.08:17:11.44#ibcon#flushed, iclass 21, count 2 2006.168.08:17:11.44#ibcon#about to write, iclass 21, count 2 2006.168.08:17:11.44#ibcon#wrote, iclass 21, count 2 2006.168.08:17:11.44#ibcon#about to read 3, iclass 21, count 2 2006.168.08:17:11.46#ibcon#read 3, iclass 21, count 2 2006.168.08:17:11.46#ibcon#about to read 4, iclass 21, count 2 2006.168.08:17:11.46#ibcon#read 4, iclass 21, count 2 2006.168.08:17:11.46#ibcon#about to read 5, iclass 21, count 2 2006.168.08:17:11.46#ibcon#read 5, iclass 21, count 2 2006.168.08:17:11.46#ibcon#about to read 6, iclass 21, count 2 2006.168.08:17:11.46#ibcon#read 6, iclass 21, count 2 2006.168.08:17:11.46#ibcon#end of sib2, iclass 21, count 2 2006.168.08:17:11.46#ibcon#*mode == 0, iclass 21, count 2 2006.168.08:17:11.46#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.168.08:17:11.46#ibcon#[27=AT03-04\r\n] 2006.168.08:17:11.46#ibcon#*before write, iclass 21, count 2 2006.168.08:17:11.46#ibcon#enter sib2, iclass 21, count 2 2006.168.08:17:11.46#ibcon#flushed, iclass 21, count 2 2006.168.08:17:11.46#ibcon#about to write, iclass 21, count 2 2006.168.08:17:11.46#ibcon#wrote, iclass 21, count 2 2006.168.08:17:11.46#ibcon#about to read 3, iclass 21, count 2 2006.168.08:17:11.49#ibcon#read 3, iclass 21, count 2 2006.168.08:17:11.49#ibcon#about to read 4, iclass 21, count 2 2006.168.08:17:11.49#ibcon#read 4, iclass 21, count 2 2006.168.08:17:11.49#ibcon#about to read 5, iclass 21, count 2 2006.168.08:17:11.49#ibcon#read 5, iclass 21, count 2 2006.168.08:17:11.49#ibcon#about to read 6, iclass 21, count 2 2006.168.08:17:11.49#ibcon#read 6, iclass 21, count 2 2006.168.08:17:11.49#ibcon#end of sib2, iclass 21, count 2 2006.168.08:17:11.49#ibcon#*after write, iclass 21, count 2 2006.168.08:17:11.49#ibcon#*before return 0, iclass 21, count 2 2006.168.08:17:11.49#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.168.08:17:11.49#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.168.08:17:11.49#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.168.08:17:11.49#ibcon#ireg 7 cls_cnt 0 2006.168.08:17:11.49#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.168.08:17:11.61#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.168.08:17:11.61#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.168.08:17:11.61#ibcon#enter wrdev, iclass 21, count 0 2006.168.08:17:11.61#ibcon#first serial, iclass 21, count 0 2006.168.08:17:11.61#ibcon#enter sib2, iclass 21, count 0 2006.168.08:17:11.61#ibcon#flushed, iclass 21, count 0 2006.168.08:17:11.61#ibcon#about to write, iclass 21, count 0 2006.168.08:17:11.61#ibcon#wrote, iclass 21, count 0 2006.168.08:17:11.61#ibcon#about to read 3, iclass 21, count 0 2006.168.08:17:11.63#ibcon#read 3, iclass 21, count 0 2006.168.08:17:11.63#ibcon#about to read 4, iclass 21, count 0 2006.168.08:17:11.63#ibcon#read 4, iclass 21, count 0 2006.168.08:17:11.63#ibcon#about to read 5, iclass 21, count 0 2006.168.08:17:11.63#ibcon#read 5, iclass 21, count 0 2006.168.08:17:11.63#ibcon#about to read 6, iclass 21, count 0 2006.168.08:17:11.63#ibcon#read 6, iclass 21, count 0 2006.168.08:17:11.63#ibcon#end of sib2, iclass 21, count 0 2006.168.08:17:11.63#ibcon#*mode == 0, iclass 21, count 0 2006.168.08:17:11.63#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.168.08:17:11.63#ibcon#[27=USB\r\n] 2006.168.08:17:11.63#ibcon#*before write, iclass 21, count 0 2006.168.08:17:11.63#ibcon#enter sib2, iclass 21, count 0 2006.168.08:17:11.63#ibcon#flushed, iclass 21, count 0 2006.168.08:17:11.63#ibcon#about to write, iclass 21, count 0 2006.168.08:17:11.63#ibcon#wrote, iclass 21, count 0 2006.168.08:17:11.63#ibcon#about to read 3, iclass 21, count 0 2006.168.08:17:11.66#ibcon#read 3, iclass 21, count 0 2006.168.08:17:11.66#ibcon#about to read 4, iclass 21, count 0 2006.168.08:17:11.66#ibcon#read 4, iclass 21, count 0 2006.168.08:17:11.66#ibcon#about to read 5, iclass 21, count 0 2006.168.08:17:11.66#ibcon#read 5, iclass 21, count 0 2006.168.08:17:11.66#ibcon#about to read 6, iclass 21, count 0 2006.168.08:17:11.66#ibcon#read 6, iclass 21, count 0 2006.168.08:17:11.66#ibcon#end of sib2, iclass 21, count 0 2006.168.08:17:11.66#ibcon#*after write, iclass 21, count 0 2006.168.08:17:11.66#ibcon#*before return 0, iclass 21, count 0 2006.168.08:17:11.66#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.168.08:17:11.66#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.168.08:17:11.66#ibcon#about to clear, iclass 21 cls_cnt 0 2006.168.08:17:11.66#ibcon#cleared, iclass 21 cls_cnt 0 2006.168.08:17:11.66$vc4f8/vblo=4,712.99 2006.168.08:17:11.66#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.168.08:17:11.66#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.168.08:17:11.66#ibcon#ireg 17 cls_cnt 0 2006.168.08:17:11.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:17:11.66#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:17:11.66#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:17:11.66#ibcon#enter wrdev, iclass 23, count 0 2006.168.08:17:11.66#ibcon#first serial, iclass 23, count 0 2006.168.08:17:11.66#ibcon#enter sib2, iclass 23, count 0 2006.168.08:17:11.66#ibcon#flushed, iclass 23, count 0 2006.168.08:17:11.66#ibcon#about to write, iclass 23, count 0 2006.168.08:17:11.66#ibcon#wrote, iclass 23, count 0 2006.168.08:17:11.66#ibcon#about to read 3, iclass 23, count 0 2006.168.08:17:11.68#ibcon#read 3, iclass 23, count 0 2006.168.08:17:11.68#ibcon#about to read 4, iclass 23, count 0 2006.168.08:17:11.68#ibcon#read 4, iclass 23, count 0 2006.168.08:17:11.68#ibcon#about to read 5, iclass 23, count 0 2006.168.08:17:11.68#ibcon#read 5, iclass 23, count 0 2006.168.08:17:11.68#ibcon#about to read 6, iclass 23, count 0 2006.168.08:17:11.68#ibcon#read 6, iclass 23, count 0 2006.168.08:17:11.68#ibcon#end of sib2, iclass 23, count 0 2006.168.08:17:11.68#ibcon#*mode == 0, iclass 23, count 0 2006.168.08:17:11.68#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.168.08:17:11.68#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.08:17:11.68#ibcon#*before write, iclass 23, count 0 2006.168.08:17:11.68#ibcon#enter sib2, iclass 23, count 0 2006.168.08:17:11.68#ibcon#flushed, iclass 23, count 0 2006.168.08:17:11.68#ibcon#about to write, iclass 23, count 0 2006.168.08:17:11.68#ibcon#wrote, iclass 23, count 0 2006.168.08:17:11.68#ibcon#about to read 3, iclass 23, count 0 2006.168.08:17:11.72#ibcon#read 3, iclass 23, count 0 2006.168.08:17:11.72#ibcon#about to read 4, iclass 23, count 0 2006.168.08:17:11.72#ibcon#read 4, iclass 23, count 0 2006.168.08:17:11.72#ibcon#about to read 5, iclass 23, count 0 2006.168.08:17:11.72#ibcon#read 5, iclass 23, count 0 2006.168.08:17:11.72#ibcon#about to read 6, iclass 23, count 0 2006.168.08:17:11.72#ibcon#read 6, iclass 23, count 0 2006.168.08:17:11.72#ibcon#end of sib2, iclass 23, count 0 2006.168.08:17:11.72#ibcon#*after write, iclass 23, count 0 2006.168.08:17:11.72#ibcon#*before return 0, iclass 23, count 0 2006.168.08:17:11.72#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:17:11.72#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.168.08:17:11.72#ibcon#about to clear, iclass 23 cls_cnt 0 2006.168.08:17:11.72#ibcon#cleared, iclass 23 cls_cnt 0 2006.168.08:17:11.72$vc4f8/vb=4,4 2006.168.08:17:11.72#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.168.08:17:11.72#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.168.08:17:11.72#ibcon#ireg 11 cls_cnt 2 2006.168.08:17:11.72#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:17:11.78#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:17:11.78#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:17:11.78#ibcon#enter wrdev, iclass 25, count 2 2006.168.08:17:11.78#ibcon#first serial, iclass 25, count 2 2006.168.08:17:11.78#ibcon#enter sib2, iclass 25, count 2 2006.168.08:17:11.78#ibcon#flushed, iclass 25, count 2 2006.168.08:17:11.78#ibcon#about to write, iclass 25, count 2 2006.168.08:17:11.78#ibcon#wrote, iclass 25, count 2 2006.168.08:17:11.78#ibcon#about to read 3, iclass 25, count 2 2006.168.08:17:11.80#ibcon#read 3, iclass 25, count 2 2006.168.08:17:11.80#ibcon#about to read 4, iclass 25, count 2 2006.168.08:17:11.80#ibcon#read 4, iclass 25, count 2 2006.168.08:17:11.80#ibcon#about to read 5, iclass 25, count 2 2006.168.08:17:11.80#ibcon#read 5, iclass 25, count 2 2006.168.08:17:11.80#ibcon#about to read 6, iclass 25, count 2 2006.168.08:17:11.80#ibcon#read 6, iclass 25, count 2 2006.168.08:17:11.80#ibcon#end of sib2, iclass 25, count 2 2006.168.08:17:11.80#ibcon#*mode == 0, iclass 25, count 2 2006.168.08:17:11.80#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.168.08:17:11.80#ibcon#[27=AT04-04\r\n] 2006.168.08:17:11.80#ibcon#*before write, iclass 25, count 2 2006.168.08:17:11.80#ibcon#enter sib2, iclass 25, count 2 2006.168.08:17:11.80#ibcon#flushed, iclass 25, count 2 2006.168.08:17:11.80#ibcon#about to write, iclass 25, count 2 2006.168.08:17:11.80#ibcon#wrote, iclass 25, count 2 2006.168.08:17:11.80#ibcon#about to read 3, iclass 25, count 2 2006.168.08:17:11.83#ibcon#read 3, iclass 25, count 2 2006.168.08:17:11.83#ibcon#about to read 4, iclass 25, count 2 2006.168.08:17:11.83#ibcon#read 4, iclass 25, count 2 2006.168.08:17:11.83#ibcon#about to read 5, iclass 25, count 2 2006.168.08:17:11.83#ibcon#read 5, iclass 25, count 2 2006.168.08:17:11.83#ibcon#about to read 6, iclass 25, count 2 2006.168.08:17:11.83#ibcon#read 6, iclass 25, count 2 2006.168.08:17:11.83#ibcon#end of sib2, iclass 25, count 2 2006.168.08:17:11.83#ibcon#*after write, iclass 25, count 2 2006.168.08:17:11.83#ibcon#*before return 0, iclass 25, count 2 2006.168.08:17:11.83#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:17:11.83#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.168.08:17:11.83#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.168.08:17:11.83#ibcon#ireg 7 cls_cnt 0 2006.168.08:17:11.83#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:17:11.95#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:17:11.95#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:17:11.95#ibcon#enter wrdev, iclass 25, count 0 2006.168.08:17:11.95#ibcon#first serial, iclass 25, count 0 2006.168.08:17:11.95#ibcon#enter sib2, iclass 25, count 0 2006.168.08:17:11.95#ibcon#flushed, iclass 25, count 0 2006.168.08:17:11.95#ibcon#about to write, iclass 25, count 0 2006.168.08:17:11.95#ibcon#wrote, iclass 25, count 0 2006.168.08:17:11.95#ibcon#about to read 3, iclass 25, count 0 2006.168.08:17:11.97#ibcon#read 3, iclass 25, count 0 2006.168.08:17:11.97#ibcon#about to read 4, iclass 25, count 0 2006.168.08:17:11.97#ibcon#read 4, iclass 25, count 0 2006.168.08:17:11.97#ibcon#about to read 5, iclass 25, count 0 2006.168.08:17:11.97#ibcon#read 5, iclass 25, count 0 2006.168.08:17:11.97#ibcon#about to read 6, iclass 25, count 0 2006.168.08:17:11.97#ibcon#read 6, iclass 25, count 0 2006.168.08:17:11.97#ibcon#end of sib2, iclass 25, count 0 2006.168.08:17:11.97#ibcon#*mode == 0, iclass 25, count 0 2006.168.08:17:11.97#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.168.08:17:11.97#ibcon#[27=USB\r\n] 2006.168.08:17:11.97#ibcon#*before write, iclass 25, count 0 2006.168.08:17:11.97#ibcon#enter sib2, iclass 25, count 0 2006.168.08:17:11.97#ibcon#flushed, iclass 25, count 0 2006.168.08:17:11.97#ibcon#about to write, iclass 25, count 0 2006.168.08:17:11.97#ibcon#wrote, iclass 25, count 0 2006.168.08:17:11.97#ibcon#about to read 3, iclass 25, count 0 2006.168.08:17:12.00#ibcon#read 3, iclass 25, count 0 2006.168.08:17:12.00#ibcon#about to read 4, iclass 25, count 0 2006.168.08:17:12.00#ibcon#read 4, iclass 25, count 0 2006.168.08:17:12.00#ibcon#about to read 5, iclass 25, count 0 2006.168.08:17:12.00#ibcon#read 5, iclass 25, count 0 2006.168.08:17:12.00#ibcon#about to read 6, iclass 25, count 0 2006.168.08:17:12.00#ibcon#read 6, iclass 25, count 0 2006.168.08:17:12.00#ibcon#end of sib2, iclass 25, count 0 2006.168.08:17:12.00#ibcon#*after write, iclass 25, count 0 2006.168.08:17:12.00#ibcon#*before return 0, iclass 25, count 0 2006.168.08:17:12.00#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:17:12.00#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.168.08:17:12.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.168.08:17:12.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.168.08:17:12.00$vc4f8/vblo=5,744.99 2006.168.08:17:12.00#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.168.08:17:12.00#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.168.08:17:12.00#ibcon#ireg 17 cls_cnt 0 2006.168.08:17:12.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:17:12.00#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:17:12.00#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:17:12.00#ibcon#enter wrdev, iclass 27, count 0 2006.168.08:17:12.00#ibcon#first serial, iclass 27, count 0 2006.168.08:17:12.00#ibcon#enter sib2, iclass 27, count 0 2006.168.08:17:12.00#ibcon#flushed, iclass 27, count 0 2006.168.08:17:12.00#ibcon#about to write, iclass 27, count 0 2006.168.08:17:12.00#ibcon#wrote, iclass 27, count 0 2006.168.08:17:12.00#ibcon#about to read 3, iclass 27, count 0 2006.168.08:17:12.02#ibcon#read 3, iclass 27, count 0 2006.168.08:17:12.02#ibcon#about to read 4, iclass 27, count 0 2006.168.08:17:12.02#ibcon#read 4, iclass 27, count 0 2006.168.08:17:12.02#ibcon#about to read 5, iclass 27, count 0 2006.168.08:17:12.02#ibcon#read 5, iclass 27, count 0 2006.168.08:17:12.02#ibcon#about to read 6, iclass 27, count 0 2006.168.08:17:12.02#ibcon#read 6, iclass 27, count 0 2006.168.08:17:12.02#ibcon#end of sib2, iclass 27, count 0 2006.168.08:17:12.02#ibcon#*mode == 0, iclass 27, count 0 2006.168.08:17:12.02#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.168.08:17:12.02#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.08:17:12.02#ibcon#*before write, iclass 27, count 0 2006.168.08:17:12.02#ibcon#enter sib2, iclass 27, count 0 2006.168.08:17:12.02#ibcon#flushed, iclass 27, count 0 2006.168.08:17:12.02#ibcon#about to write, iclass 27, count 0 2006.168.08:17:12.02#ibcon#wrote, iclass 27, count 0 2006.168.08:17:12.02#ibcon#about to read 3, iclass 27, count 0 2006.168.08:17:12.06#ibcon#read 3, iclass 27, count 0 2006.168.08:17:12.06#ibcon#about to read 4, iclass 27, count 0 2006.168.08:17:12.06#ibcon#read 4, iclass 27, count 0 2006.168.08:17:12.06#ibcon#about to read 5, iclass 27, count 0 2006.168.08:17:12.06#ibcon#read 5, iclass 27, count 0 2006.168.08:17:12.06#ibcon#about to read 6, iclass 27, count 0 2006.168.08:17:12.06#ibcon#read 6, iclass 27, count 0 2006.168.08:17:12.06#ibcon#end of sib2, iclass 27, count 0 2006.168.08:17:12.06#ibcon#*after write, iclass 27, count 0 2006.168.08:17:12.06#ibcon#*before return 0, iclass 27, count 0 2006.168.08:17:12.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:17:12.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.168.08:17:12.06#ibcon#about to clear, iclass 27 cls_cnt 0 2006.168.08:17:12.06#ibcon#cleared, iclass 27 cls_cnt 0 2006.168.08:17:12.06$vc4f8/vb=5,4 2006.168.08:17:12.06#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.168.08:17:12.06#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.168.08:17:12.06#ibcon#ireg 11 cls_cnt 2 2006.168.08:17:12.06#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:17:12.12#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:17:12.12#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:17:12.12#ibcon#enter wrdev, iclass 29, count 2 2006.168.08:17:12.12#ibcon#first serial, iclass 29, count 2 2006.168.08:17:12.12#ibcon#enter sib2, iclass 29, count 2 2006.168.08:17:12.12#ibcon#flushed, iclass 29, count 2 2006.168.08:17:12.12#ibcon#about to write, iclass 29, count 2 2006.168.08:17:12.12#ibcon#wrote, iclass 29, count 2 2006.168.08:17:12.12#ibcon#about to read 3, iclass 29, count 2 2006.168.08:17:12.14#ibcon#read 3, iclass 29, count 2 2006.168.08:17:12.14#ibcon#about to read 4, iclass 29, count 2 2006.168.08:17:12.14#ibcon#read 4, iclass 29, count 2 2006.168.08:17:12.14#ibcon#about to read 5, iclass 29, count 2 2006.168.08:17:12.14#ibcon#read 5, iclass 29, count 2 2006.168.08:17:12.14#ibcon#about to read 6, iclass 29, count 2 2006.168.08:17:12.14#ibcon#read 6, iclass 29, count 2 2006.168.08:17:12.14#ibcon#end of sib2, iclass 29, count 2 2006.168.08:17:12.14#ibcon#*mode == 0, iclass 29, count 2 2006.168.08:17:12.14#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.168.08:17:12.14#ibcon#[27=AT05-04\r\n] 2006.168.08:17:12.14#ibcon#*before write, iclass 29, count 2 2006.168.08:17:12.14#ibcon#enter sib2, iclass 29, count 2 2006.168.08:17:12.14#ibcon#flushed, iclass 29, count 2 2006.168.08:17:12.14#ibcon#about to write, iclass 29, count 2 2006.168.08:17:12.14#ibcon#wrote, iclass 29, count 2 2006.168.08:17:12.14#ibcon#about to read 3, iclass 29, count 2 2006.168.08:17:12.17#ibcon#read 3, iclass 29, count 2 2006.168.08:17:12.17#ibcon#about to read 4, iclass 29, count 2 2006.168.08:17:12.17#ibcon#read 4, iclass 29, count 2 2006.168.08:17:12.17#ibcon#about to read 5, iclass 29, count 2 2006.168.08:17:12.17#ibcon#read 5, iclass 29, count 2 2006.168.08:17:12.17#ibcon#about to read 6, iclass 29, count 2 2006.168.08:17:12.17#ibcon#read 6, iclass 29, count 2 2006.168.08:17:12.17#ibcon#end of sib2, iclass 29, count 2 2006.168.08:17:12.17#ibcon#*after write, iclass 29, count 2 2006.168.08:17:12.17#ibcon#*before return 0, iclass 29, count 2 2006.168.08:17:12.17#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:17:12.17#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.168.08:17:12.17#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.168.08:17:12.17#ibcon#ireg 7 cls_cnt 0 2006.168.08:17:12.17#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:17:12.29#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:17:12.29#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:17:12.29#ibcon#enter wrdev, iclass 29, count 0 2006.168.08:17:12.29#ibcon#first serial, iclass 29, count 0 2006.168.08:17:12.29#ibcon#enter sib2, iclass 29, count 0 2006.168.08:17:12.29#ibcon#flushed, iclass 29, count 0 2006.168.08:17:12.29#ibcon#about to write, iclass 29, count 0 2006.168.08:17:12.29#ibcon#wrote, iclass 29, count 0 2006.168.08:17:12.29#ibcon#about to read 3, iclass 29, count 0 2006.168.08:17:12.31#ibcon#read 3, iclass 29, count 0 2006.168.08:17:12.31#ibcon#about to read 4, iclass 29, count 0 2006.168.08:17:12.31#ibcon#read 4, iclass 29, count 0 2006.168.08:17:12.31#ibcon#about to read 5, iclass 29, count 0 2006.168.08:17:12.31#ibcon#read 5, iclass 29, count 0 2006.168.08:17:12.31#ibcon#about to read 6, iclass 29, count 0 2006.168.08:17:12.31#ibcon#read 6, iclass 29, count 0 2006.168.08:17:12.31#ibcon#end of sib2, iclass 29, count 0 2006.168.08:17:12.31#ibcon#*mode == 0, iclass 29, count 0 2006.168.08:17:12.31#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.168.08:17:12.31#ibcon#[27=USB\r\n] 2006.168.08:17:12.31#ibcon#*before write, iclass 29, count 0 2006.168.08:17:12.31#ibcon#enter sib2, iclass 29, count 0 2006.168.08:17:12.31#ibcon#flushed, iclass 29, count 0 2006.168.08:17:12.31#ibcon#about to write, iclass 29, count 0 2006.168.08:17:12.31#ibcon#wrote, iclass 29, count 0 2006.168.08:17:12.31#ibcon#about to read 3, iclass 29, count 0 2006.168.08:17:12.34#ibcon#read 3, iclass 29, count 0 2006.168.08:17:12.34#ibcon#about to read 4, iclass 29, count 0 2006.168.08:17:12.34#ibcon#read 4, iclass 29, count 0 2006.168.08:17:12.34#ibcon#about to read 5, iclass 29, count 0 2006.168.08:17:12.34#ibcon#read 5, iclass 29, count 0 2006.168.08:17:12.34#ibcon#about to read 6, iclass 29, count 0 2006.168.08:17:12.34#ibcon#read 6, iclass 29, count 0 2006.168.08:17:12.34#ibcon#end of sib2, iclass 29, count 0 2006.168.08:17:12.34#ibcon#*after write, iclass 29, count 0 2006.168.08:17:12.34#ibcon#*before return 0, iclass 29, count 0 2006.168.08:17:12.34#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:17:12.34#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.168.08:17:12.34#ibcon#about to clear, iclass 29 cls_cnt 0 2006.168.08:17:12.34#ibcon#cleared, iclass 29 cls_cnt 0 2006.168.08:17:12.34$vc4f8/vblo=6,752.99 2006.168.08:17:12.34#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.168.08:17:12.34#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.168.08:17:12.34#ibcon#ireg 17 cls_cnt 0 2006.168.08:17:12.34#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:17:12.34#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:17:12.34#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:17:12.34#ibcon#enter wrdev, iclass 31, count 0 2006.168.08:17:12.34#ibcon#first serial, iclass 31, count 0 2006.168.08:17:12.34#ibcon#enter sib2, iclass 31, count 0 2006.168.08:17:12.34#ibcon#flushed, iclass 31, count 0 2006.168.08:17:12.34#ibcon#about to write, iclass 31, count 0 2006.168.08:17:12.34#ibcon#wrote, iclass 31, count 0 2006.168.08:17:12.34#ibcon#about to read 3, iclass 31, count 0 2006.168.08:17:12.36#ibcon#read 3, iclass 31, count 0 2006.168.08:17:12.36#ibcon#about to read 4, iclass 31, count 0 2006.168.08:17:12.36#ibcon#read 4, iclass 31, count 0 2006.168.08:17:12.36#ibcon#about to read 5, iclass 31, count 0 2006.168.08:17:12.36#ibcon#read 5, iclass 31, count 0 2006.168.08:17:12.36#ibcon#about to read 6, iclass 31, count 0 2006.168.08:17:12.36#ibcon#read 6, iclass 31, count 0 2006.168.08:17:12.36#ibcon#end of sib2, iclass 31, count 0 2006.168.08:17:12.36#ibcon#*mode == 0, iclass 31, count 0 2006.168.08:17:12.36#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.168.08:17:12.36#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.08:17:12.36#ibcon#*before write, iclass 31, count 0 2006.168.08:17:12.36#ibcon#enter sib2, iclass 31, count 0 2006.168.08:17:12.36#ibcon#flushed, iclass 31, count 0 2006.168.08:17:12.36#ibcon#about to write, iclass 31, count 0 2006.168.08:17:12.36#ibcon#wrote, iclass 31, count 0 2006.168.08:17:12.36#ibcon#about to read 3, iclass 31, count 0 2006.168.08:17:12.40#ibcon#read 3, iclass 31, count 0 2006.168.08:17:12.40#ibcon#about to read 4, iclass 31, count 0 2006.168.08:17:12.40#ibcon#read 4, iclass 31, count 0 2006.168.08:17:12.40#ibcon#about to read 5, iclass 31, count 0 2006.168.08:17:12.40#ibcon#read 5, iclass 31, count 0 2006.168.08:17:12.40#ibcon#about to read 6, iclass 31, count 0 2006.168.08:17:12.40#ibcon#read 6, iclass 31, count 0 2006.168.08:17:12.40#ibcon#end of sib2, iclass 31, count 0 2006.168.08:17:12.40#ibcon#*after write, iclass 31, count 0 2006.168.08:17:12.40#ibcon#*before return 0, iclass 31, count 0 2006.168.08:17:12.40#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:17:12.40#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.168.08:17:12.40#ibcon#about to clear, iclass 31 cls_cnt 0 2006.168.08:17:12.40#ibcon#cleared, iclass 31 cls_cnt 0 2006.168.08:17:12.40$vc4f8/vb=6,4 2006.168.08:17:12.40#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.168.08:17:12.40#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.168.08:17:12.40#ibcon#ireg 11 cls_cnt 2 2006.168.08:17:12.40#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.168.08:17:12.46#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.168.08:17:12.46#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.168.08:17:12.46#ibcon#enter wrdev, iclass 33, count 2 2006.168.08:17:12.46#ibcon#first serial, iclass 33, count 2 2006.168.08:17:12.46#ibcon#enter sib2, iclass 33, count 2 2006.168.08:17:12.46#ibcon#flushed, iclass 33, count 2 2006.168.08:17:12.46#ibcon#about to write, iclass 33, count 2 2006.168.08:17:12.46#ibcon#wrote, iclass 33, count 2 2006.168.08:17:12.46#ibcon#about to read 3, iclass 33, count 2 2006.168.08:17:12.48#ibcon#read 3, iclass 33, count 2 2006.168.08:17:12.48#ibcon#about to read 4, iclass 33, count 2 2006.168.08:17:12.48#ibcon#read 4, iclass 33, count 2 2006.168.08:17:12.48#ibcon#about to read 5, iclass 33, count 2 2006.168.08:17:12.48#ibcon#read 5, iclass 33, count 2 2006.168.08:17:12.48#ibcon#about to read 6, iclass 33, count 2 2006.168.08:17:12.48#ibcon#read 6, iclass 33, count 2 2006.168.08:17:12.48#ibcon#end of sib2, iclass 33, count 2 2006.168.08:17:12.48#ibcon#*mode == 0, iclass 33, count 2 2006.168.08:17:12.48#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.168.08:17:12.48#ibcon#[27=AT06-04\r\n] 2006.168.08:17:12.48#ibcon#*before write, iclass 33, count 2 2006.168.08:17:12.48#ibcon#enter sib2, iclass 33, count 2 2006.168.08:17:12.48#ibcon#flushed, iclass 33, count 2 2006.168.08:17:12.48#ibcon#about to write, iclass 33, count 2 2006.168.08:17:12.48#ibcon#wrote, iclass 33, count 2 2006.168.08:17:12.48#ibcon#about to read 3, iclass 33, count 2 2006.168.08:17:12.51#ibcon#read 3, iclass 33, count 2 2006.168.08:17:12.51#ibcon#about to read 4, iclass 33, count 2 2006.168.08:17:12.51#ibcon#read 4, iclass 33, count 2 2006.168.08:17:12.51#ibcon#about to read 5, iclass 33, count 2 2006.168.08:17:12.51#ibcon#read 5, iclass 33, count 2 2006.168.08:17:12.51#ibcon#about to read 6, iclass 33, count 2 2006.168.08:17:12.51#ibcon#read 6, iclass 33, count 2 2006.168.08:17:12.51#ibcon#end of sib2, iclass 33, count 2 2006.168.08:17:12.51#ibcon#*after write, iclass 33, count 2 2006.168.08:17:12.51#ibcon#*before return 0, iclass 33, count 2 2006.168.08:17:12.51#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.168.08:17:12.51#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.168.08:17:12.51#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.168.08:17:12.51#ibcon#ireg 7 cls_cnt 0 2006.168.08:17:12.51#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.168.08:17:12.63#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.168.08:17:12.63#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.168.08:17:12.63#ibcon#enter wrdev, iclass 33, count 0 2006.168.08:17:12.63#ibcon#first serial, iclass 33, count 0 2006.168.08:17:12.63#ibcon#enter sib2, iclass 33, count 0 2006.168.08:17:12.63#ibcon#flushed, iclass 33, count 0 2006.168.08:17:12.63#ibcon#about to write, iclass 33, count 0 2006.168.08:17:12.63#ibcon#wrote, iclass 33, count 0 2006.168.08:17:12.63#ibcon#about to read 3, iclass 33, count 0 2006.168.08:17:12.65#ibcon#read 3, iclass 33, count 0 2006.168.08:17:12.65#ibcon#about to read 4, iclass 33, count 0 2006.168.08:17:12.65#ibcon#read 4, iclass 33, count 0 2006.168.08:17:12.65#ibcon#about to read 5, iclass 33, count 0 2006.168.08:17:12.65#ibcon#read 5, iclass 33, count 0 2006.168.08:17:12.65#ibcon#about to read 6, iclass 33, count 0 2006.168.08:17:12.65#ibcon#read 6, iclass 33, count 0 2006.168.08:17:12.65#ibcon#end of sib2, iclass 33, count 0 2006.168.08:17:12.65#ibcon#*mode == 0, iclass 33, count 0 2006.168.08:17:12.65#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.168.08:17:12.65#ibcon#[27=USB\r\n] 2006.168.08:17:12.65#ibcon#*before write, iclass 33, count 0 2006.168.08:17:12.65#ibcon#enter sib2, iclass 33, count 0 2006.168.08:17:12.65#ibcon#flushed, iclass 33, count 0 2006.168.08:17:12.65#ibcon#about to write, iclass 33, count 0 2006.168.08:17:12.65#ibcon#wrote, iclass 33, count 0 2006.168.08:17:12.65#ibcon#about to read 3, iclass 33, count 0 2006.168.08:17:12.68#ibcon#read 3, iclass 33, count 0 2006.168.08:17:12.68#ibcon#about to read 4, iclass 33, count 0 2006.168.08:17:12.68#ibcon#read 4, iclass 33, count 0 2006.168.08:17:12.68#ibcon#about to read 5, iclass 33, count 0 2006.168.08:17:12.68#ibcon#read 5, iclass 33, count 0 2006.168.08:17:12.68#ibcon#about to read 6, iclass 33, count 0 2006.168.08:17:12.68#ibcon#read 6, iclass 33, count 0 2006.168.08:17:12.68#ibcon#end of sib2, iclass 33, count 0 2006.168.08:17:12.68#ibcon#*after write, iclass 33, count 0 2006.168.08:17:12.68#ibcon#*before return 0, iclass 33, count 0 2006.168.08:17:12.68#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.168.08:17:12.68#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.168.08:17:12.68#ibcon#about to clear, iclass 33 cls_cnt 0 2006.168.08:17:12.68#ibcon#cleared, iclass 33 cls_cnt 0 2006.168.08:17:12.68$vc4f8/vabw=wide 2006.168.08:17:12.68#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.168.08:17:12.68#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.168.08:17:12.68#ibcon#ireg 8 cls_cnt 0 2006.168.08:17:12.68#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.168.08:17:12.68#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.168.08:17:12.68#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.168.08:17:12.68#ibcon#enter wrdev, iclass 35, count 0 2006.168.08:17:12.68#ibcon#first serial, iclass 35, count 0 2006.168.08:17:12.68#ibcon#enter sib2, iclass 35, count 0 2006.168.08:17:12.68#ibcon#flushed, iclass 35, count 0 2006.168.08:17:12.68#ibcon#about to write, iclass 35, count 0 2006.168.08:17:12.68#ibcon#wrote, iclass 35, count 0 2006.168.08:17:12.68#ibcon#about to read 3, iclass 35, count 0 2006.168.08:17:12.70#ibcon#read 3, iclass 35, count 0 2006.168.08:17:12.70#ibcon#about to read 4, iclass 35, count 0 2006.168.08:17:12.70#ibcon#read 4, iclass 35, count 0 2006.168.08:17:12.70#ibcon#about to read 5, iclass 35, count 0 2006.168.08:17:12.70#ibcon#read 5, iclass 35, count 0 2006.168.08:17:12.70#ibcon#about to read 6, iclass 35, count 0 2006.168.08:17:12.70#ibcon#read 6, iclass 35, count 0 2006.168.08:17:12.70#ibcon#end of sib2, iclass 35, count 0 2006.168.08:17:12.70#ibcon#*mode == 0, iclass 35, count 0 2006.168.08:17:12.70#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.168.08:17:12.70#ibcon#[25=BW32\r\n] 2006.168.08:17:12.70#ibcon#*before write, iclass 35, count 0 2006.168.08:17:12.70#ibcon#enter sib2, iclass 35, count 0 2006.168.08:17:12.70#ibcon#flushed, iclass 35, count 0 2006.168.08:17:12.70#ibcon#about to write, iclass 35, count 0 2006.168.08:17:12.70#ibcon#wrote, iclass 35, count 0 2006.168.08:17:12.70#ibcon#about to read 3, iclass 35, count 0 2006.168.08:17:12.73#ibcon#read 3, iclass 35, count 0 2006.168.08:17:12.73#ibcon#about to read 4, iclass 35, count 0 2006.168.08:17:12.73#ibcon#read 4, iclass 35, count 0 2006.168.08:17:12.73#ibcon#about to read 5, iclass 35, count 0 2006.168.08:17:12.73#ibcon#read 5, iclass 35, count 0 2006.168.08:17:12.73#ibcon#about to read 6, iclass 35, count 0 2006.168.08:17:12.73#ibcon#read 6, iclass 35, count 0 2006.168.08:17:12.73#ibcon#end of sib2, iclass 35, count 0 2006.168.08:17:12.73#ibcon#*after write, iclass 35, count 0 2006.168.08:17:12.73#ibcon#*before return 0, iclass 35, count 0 2006.168.08:17:12.73#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.168.08:17:12.73#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.168.08:17:12.73#ibcon#about to clear, iclass 35 cls_cnt 0 2006.168.08:17:12.73#ibcon#cleared, iclass 35 cls_cnt 0 2006.168.08:17:12.73$vc4f8/vbbw=wide 2006.168.08:17:12.73#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.168.08:17:12.73#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.168.08:17:12.73#ibcon#ireg 8 cls_cnt 0 2006.168.08:17:12.73#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:17:12.80#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:17:12.80#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:17:12.80#ibcon#enter wrdev, iclass 37, count 0 2006.168.08:17:12.80#ibcon#first serial, iclass 37, count 0 2006.168.08:17:12.80#ibcon#enter sib2, iclass 37, count 0 2006.168.08:17:12.80#ibcon#flushed, iclass 37, count 0 2006.168.08:17:12.80#ibcon#about to write, iclass 37, count 0 2006.168.08:17:12.80#ibcon#wrote, iclass 37, count 0 2006.168.08:17:12.80#ibcon#about to read 3, iclass 37, count 0 2006.168.08:17:12.82#ibcon#read 3, iclass 37, count 0 2006.168.08:17:12.82#ibcon#about to read 4, iclass 37, count 0 2006.168.08:17:12.82#ibcon#read 4, iclass 37, count 0 2006.168.08:17:12.82#ibcon#about to read 5, iclass 37, count 0 2006.168.08:17:12.82#ibcon#read 5, iclass 37, count 0 2006.168.08:17:12.82#ibcon#about to read 6, iclass 37, count 0 2006.168.08:17:12.82#ibcon#read 6, iclass 37, count 0 2006.168.08:17:12.82#ibcon#end of sib2, iclass 37, count 0 2006.168.08:17:12.82#ibcon#*mode == 0, iclass 37, count 0 2006.168.08:17:12.82#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.168.08:17:12.82#ibcon#[27=BW32\r\n] 2006.168.08:17:12.82#ibcon#*before write, iclass 37, count 0 2006.168.08:17:12.82#ibcon#enter sib2, iclass 37, count 0 2006.168.08:17:12.82#ibcon#flushed, iclass 37, count 0 2006.168.08:17:12.82#ibcon#about to write, iclass 37, count 0 2006.168.08:17:12.82#ibcon#wrote, iclass 37, count 0 2006.168.08:17:12.82#ibcon#about to read 3, iclass 37, count 0 2006.168.08:17:12.85#ibcon#read 3, iclass 37, count 0 2006.168.08:17:12.85#ibcon#about to read 4, iclass 37, count 0 2006.168.08:17:12.85#ibcon#read 4, iclass 37, count 0 2006.168.08:17:12.85#ibcon#about to read 5, iclass 37, count 0 2006.168.08:17:12.85#ibcon#read 5, iclass 37, count 0 2006.168.08:17:12.85#ibcon#about to read 6, iclass 37, count 0 2006.168.08:17:12.85#ibcon#read 6, iclass 37, count 0 2006.168.08:17:12.85#ibcon#end of sib2, iclass 37, count 0 2006.168.08:17:12.85#ibcon#*after write, iclass 37, count 0 2006.168.08:17:12.85#ibcon#*before return 0, iclass 37, count 0 2006.168.08:17:12.85#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:17:12.85#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:17:12.85#ibcon#about to clear, iclass 37 cls_cnt 0 2006.168.08:17:12.85#ibcon#cleared, iclass 37 cls_cnt 0 2006.168.08:17:12.85$4f8m12a/ifd4f 2006.168.08:17:12.85$ifd4f/lo= 2006.168.08:17:12.85$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.08:17:12.85$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.08:17:12.85$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.08:17:12.85$ifd4f/patch= 2006.168.08:17:12.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.08:17:12.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.08:17:12.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.08:17:12.85$4f8m12a/"form=m,16.000,1:2 2006.168.08:17:12.85$4f8m12a/"tpicd 2006.168.08:17:12.85$4f8m12a/echo=off 2006.168.08:17:12.85$4f8m12a/xlog=off 2006.168.08:17:12.85:!2006.168.08:19:50 2006.168.08:17:27.14#trakl#Source acquired 2006.168.08:17:28.14#flagr#flagr/antenna,acquired 2006.168.08:19:50.00:preob 2006.168.08:19:50.14/onsource/TRACKING 2006.168.08:19:50.14:!2006.168.08:20:00 2006.168.08:20:00.00:data_valid=on 2006.168.08:20:00.00:midob 2006.168.08:20:01.14/onsource/TRACKING 2006.168.08:20:01.14/wx/26.87,1004.5,75 2006.168.08:20:01.33/cable/+6.4731E-03 2006.168.08:20:02.42/va/01,08,usb,yes,29,31 2006.168.08:20:02.42/va/02,07,usb,yes,30,31 2006.168.08:20:02.42/va/03,06,usb,yes,31,31 2006.168.08:20:02.42/va/04,07,usb,yes,30,33 2006.168.08:20:02.42/va/05,07,usb,yes,30,32 2006.168.08:20:02.42/va/06,06,usb,yes,29,29 2006.168.08:20:02.42/va/07,06,usb,yes,30,29 2006.168.08:20:02.42/va/08,07,usb,yes,28,28 2006.168.08:20:02.65/valo/01,532.99,yes,locked 2006.168.08:20:02.65/valo/02,572.99,yes,locked 2006.168.08:20:02.65/valo/03,672.99,yes,locked 2006.168.08:20:02.65/valo/04,832.99,yes,locked 2006.168.08:20:02.65/valo/05,652.99,yes,locked 2006.168.08:20:02.65/valo/06,772.99,yes,locked 2006.168.08:20:02.65/valo/07,832.99,yes,locked 2006.168.08:20:02.65/valo/08,852.99,yes,locked 2006.168.08:20:03.74/vb/01,04,usb,yes,29,28 2006.168.08:20:03.74/vb/02,04,usb,yes,31,32 2006.168.08:20:03.74/vb/03,04,usb,yes,27,31 2006.168.08:20:03.74/vb/04,04,usb,yes,28,28 2006.168.08:20:03.74/vb/05,04,usb,yes,27,31 2006.168.08:20:03.74/vb/06,04,usb,yes,28,31 2006.168.08:20:03.74/vb/07,04,usb,yes,30,30 2006.168.08:20:03.74/vb/08,04,usb,yes,27,31 2006.168.08:20:03.97/vblo/01,632.99,yes,locked 2006.168.08:20:03.97/vblo/02,640.99,yes,locked 2006.168.08:20:03.97/vblo/03,656.99,yes,locked 2006.168.08:20:03.97/vblo/04,712.99,yes,locked 2006.168.08:20:03.97/vblo/05,744.99,yes,locked 2006.168.08:20:03.97/vblo/06,752.99,yes,locked 2006.168.08:20:03.97/vblo/07,734.99,yes,locked 2006.168.08:20:03.97/vblo/08,744.99,yes,locked 2006.168.08:20:04.12/vabw/8 2006.168.08:20:04.27/vbbw/8 2006.168.08:20:04.36/xfe/off,on,14.7 2006.168.08:20:04.75/ifatt/23,28,28,28 2006.168.08:20:05.08/fmout-gps/S +4.17E-07 2006.168.08:20:05.16:!2006.168.08:22:10 2006.168.08:22:10.00:data_valid=off 2006.168.08:22:10.00:postob 2006.168.08:22:10.16/cable/+6.4721E-03 2006.168.08:22:10.16/wx/26.85,1004.5,75 2006.168.08:22:11.08/fmout-gps/S +4.16E-07 2006.168.08:22:11.08:scan_name=168-0824,k06168,60 2006.168.08:22:11.08:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.168.08:22:12.14#flagr#flagr/antenna,new-source 2006.168.08:22:12.14:checkk5 2006.168.08:22:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.168.08:22:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.168.08:22:13.28/chk_autoobs//k5ts3/ autoobs is running! 2006.168.08:22:13.66/chk_autoobs//k5ts4/ autoobs is running! 2006.168.08:22:14.03/chk_obsdata//k5ts1/T1680820??a.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.168.08:22:14.40/chk_obsdata//k5ts2/T1680820??b.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.168.08:22:14.76/chk_obsdata//k5ts3/T1680820??c.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.168.08:22:15.14/chk_obsdata//k5ts4/T1680820??d.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.168.08:22:15.86/k5log//k5ts1_log_newline 2006.168.08:22:16.55/k5log//k5ts2_log_newline 2006.168.08:22:17.26/k5log//k5ts3_log_newline 2006.168.08:22:17.95/k5log//k5ts4_log_newline 2006.168.08:22:17.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.08:22:17.97:4f8m12a=3 2006.168.08:22:17.97$4f8m12a/echo=on 2006.168.08:22:17.97$4f8m12a/pcalon 2006.168.08:22:17.97$pcalon/"no phase cal control is implemented here 2006.168.08:22:17.97$4f8m12a/"tpicd=stop 2006.168.08:22:17.97$4f8m12a/vc4f8 2006.168.08:22:17.97$vc4f8/valo=1,532.99 2006.168.08:22:17.98#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.168.08:22:17.98#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.168.08:22:17.98#ibcon#ireg 17 cls_cnt 0 2006.168.08:22:17.98#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.168.08:22:17.98#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.168.08:22:17.98#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.168.08:22:17.98#ibcon#enter wrdev, iclass 16, count 0 2006.168.08:22:17.98#ibcon#first serial, iclass 16, count 0 2006.168.08:22:17.98#ibcon#enter sib2, iclass 16, count 0 2006.168.08:22:17.98#ibcon#flushed, iclass 16, count 0 2006.168.08:22:17.98#ibcon#about to write, iclass 16, count 0 2006.168.08:22:17.98#ibcon#wrote, iclass 16, count 0 2006.168.08:22:17.98#ibcon#about to read 3, iclass 16, count 0 2006.168.08:22:18.02#ibcon#read 3, iclass 16, count 0 2006.168.08:22:18.02#ibcon#about to read 4, iclass 16, count 0 2006.168.08:22:18.02#ibcon#read 4, iclass 16, count 0 2006.168.08:22:18.02#ibcon#about to read 5, iclass 16, count 0 2006.168.08:22:18.02#ibcon#read 5, iclass 16, count 0 2006.168.08:22:18.02#ibcon#about to read 6, iclass 16, count 0 2006.168.08:22:18.02#ibcon#read 6, iclass 16, count 0 2006.168.08:22:18.02#ibcon#end of sib2, iclass 16, count 0 2006.168.08:22:18.02#ibcon#*mode == 0, iclass 16, count 0 2006.168.08:22:18.02#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.168.08:22:18.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.08:22:18.02#ibcon#*before write, iclass 16, count 0 2006.168.08:22:18.02#ibcon#enter sib2, iclass 16, count 0 2006.168.08:22:18.02#ibcon#flushed, iclass 16, count 0 2006.168.08:22:18.02#ibcon#about to write, iclass 16, count 0 2006.168.08:22:18.02#ibcon#wrote, iclass 16, count 0 2006.168.08:22:18.02#ibcon#about to read 3, iclass 16, count 0 2006.168.08:22:18.07#ibcon#read 3, iclass 16, count 0 2006.168.08:22:18.07#ibcon#about to read 4, iclass 16, count 0 2006.168.08:22:18.07#ibcon#read 4, iclass 16, count 0 2006.168.08:22:18.07#ibcon#about to read 5, iclass 16, count 0 2006.168.08:22:18.07#ibcon#read 5, iclass 16, count 0 2006.168.08:22:18.07#ibcon#about to read 6, iclass 16, count 0 2006.168.08:22:18.07#ibcon#read 6, iclass 16, count 0 2006.168.08:22:18.07#ibcon#end of sib2, iclass 16, count 0 2006.168.08:22:18.07#ibcon#*after write, iclass 16, count 0 2006.168.08:22:18.07#ibcon#*before return 0, iclass 16, count 0 2006.168.08:22:18.07#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.168.08:22:18.07#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.168.08:22:18.07#ibcon#about to clear, iclass 16 cls_cnt 0 2006.168.08:22:18.07#ibcon#cleared, iclass 16 cls_cnt 0 2006.168.08:22:18.07$vc4f8/va=1,8 2006.168.08:22:18.07#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.168.08:22:18.07#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.168.08:22:18.07#ibcon#ireg 11 cls_cnt 2 2006.168.08:22:18.07#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.168.08:22:18.07#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.168.08:22:18.07#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.168.08:22:18.07#ibcon#enter wrdev, iclass 18, count 2 2006.168.08:22:18.07#ibcon#first serial, iclass 18, count 2 2006.168.08:22:18.07#ibcon#enter sib2, iclass 18, count 2 2006.168.08:22:18.07#ibcon#flushed, iclass 18, count 2 2006.168.08:22:18.07#ibcon#about to write, iclass 18, count 2 2006.168.08:22:18.07#ibcon#wrote, iclass 18, count 2 2006.168.08:22:18.07#ibcon#about to read 3, iclass 18, count 2 2006.168.08:22:18.09#ibcon#read 3, iclass 18, count 2 2006.168.08:22:18.09#ibcon#about to read 4, iclass 18, count 2 2006.168.08:22:18.09#ibcon#read 4, iclass 18, count 2 2006.168.08:22:18.09#ibcon#about to read 5, iclass 18, count 2 2006.168.08:22:18.09#ibcon#read 5, iclass 18, count 2 2006.168.08:22:18.09#ibcon#about to read 6, iclass 18, count 2 2006.168.08:22:18.09#ibcon#read 6, iclass 18, count 2 2006.168.08:22:18.09#ibcon#end of sib2, iclass 18, count 2 2006.168.08:22:18.09#ibcon#*mode == 0, iclass 18, count 2 2006.168.08:22:18.09#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.168.08:22:18.09#ibcon#[25=AT01-08\r\n] 2006.168.08:22:18.09#ibcon#*before write, iclass 18, count 2 2006.168.08:22:18.09#ibcon#enter sib2, iclass 18, count 2 2006.168.08:22:18.09#ibcon#flushed, iclass 18, count 2 2006.168.08:22:18.09#ibcon#about to write, iclass 18, count 2 2006.168.08:22:18.09#ibcon#wrote, iclass 18, count 2 2006.168.08:22:18.09#ibcon#about to read 3, iclass 18, count 2 2006.168.08:22:18.13#ibcon#read 3, iclass 18, count 2 2006.168.08:22:18.13#ibcon#about to read 4, iclass 18, count 2 2006.168.08:22:18.13#ibcon#read 4, iclass 18, count 2 2006.168.08:22:18.13#ibcon#about to read 5, iclass 18, count 2 2006.168.08:22:18.13#ibcon#read 5, iclass 18, count 2 2006.168.08:22:18.13#ibcon#about to read 6, iclass 18, count 2 2006.168.08:22:18.13#ibcon#read 6, iclass 18, count 2 2006.168.08:22:18.13#ibcon#end of sib2, iclass 18, count 2 2006.168.08:22:18.13#ibcon#*after write, iclass 18, count 2 2006.168.08:22:18.13#ibcon#*before return 0, iclass 18, count 2 2006.168.08:22:18.13#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.168.08:22:18.13#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.168.08:22:18.13#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.168.08:22:18.13#ibcon#ireg 7 cls_cnt 0 2006.168.08:22:18.13#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.168.08:22:18.25#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.168.08:22:18.25#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.168.08:22:18.25#ibcon#enter wrdev, iclass 18, count 0 2006.168.08:22:18.25#ibcon#first serial, iclass 18, count 0 2006.168.08:22:18.25#ibcon#enter sib2, iclass 18, count 0 2006.168.08:22:18.25#ibcon#flushed, iclass 18, count 0 2006.168.08:22:18.25#ibcon#about to write, iclass 18, count 0 2006.168.08:22:18.25#ibcon#wrote, iclass 18, count 0 2006.168.08:22:18.25#ibcon#about to read 3, iclass 18, count 0 2006.168.08:22:18.27#ibcon#read 3, iclass 18, count 0 2006.168.08:22:18.27#ibcon#about to read 4, iclass 18, count 0 2006.168.08:22:18.27#ibcon#read 4, iclass 18, count 0 2006.168.08:22:18.27#ibcon#about to read 5, iclass 18, count 0 2006.168.08:22:18.27#ibcon#read 5, iclass 18, count 0 2006.168.08:22:18.27#ibcon#about to read 6, iclass 18, count 0 2006.168.08:22:18.27#ibcon#read 6, iclass 18, count 0 2006.168.08:22:18.27#ibcon#end of sib2, iclass 18, count 0 2006.168.08:22:18.27#ibcon#*mode == 0, iclass 18, count 0 2006.168.08:22:18.27#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.08:22:18.27#ibcon#[25=USB\r\n] 2006.168.08:22:18.27#ibcon#*before write, iclass 18, count 0 2006.168.08:22:18.27#ibcon#enter sib2, iclass 18, count 0 2006.168.08:22:18.27#ibcon#flushed, iclass 18, count 0 2006.168.08:22:18.27#ibcon#about to write, iclass 18, count 0 2006.168.08:22:18.27#ibcon#wrote, iclass 18, count 0 2006.168.08:22:18.27#ibcon#about to read 3, iclass 18, count 0 2006.168.08:22:18.30#ibcon#read 3, iclass 18, count 0 2006.168.08:22:18.30#ibcon#about to read 4, iclass 18, count 0 2006.168.08:22:18.30#ibcon#read 4, iclass 18, count 0 2006.168.08:22:18.30#ibcon#about to read 5, iclass 18, count 0 2006.168.08:22:18.30#ibcon#read 5, iclass 18, count 0 2006.168.08:22:18.30#ibcon#about to read 6, iclass 18, count 0 2006.168.08:22:18.30#ibcon#read 6, iclass 18, count 0 2006.168.08:22:18.30#ibcon#end of sib2, iclass 18, count 0 2006.168.08:22:18.30#ibcon#*after write, iclass 18, count 0 2006.168.08:22:18.30#ibcon#*before return 0, iclass 18, count 0 2006.168.08:22:18.30#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.168.08:22:18.30#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.168.08:22:18.30#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.08:22:18.30#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.08:22:18.30$vc4f8/valo=2,572.99 2006.168.08:22:18.30#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.168.08:22:18.30#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.168.08:22:18.30#ibcon#ireg 17 cls_cnt 0 2006.168.08:22:18.30#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:22:18.30#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:22:18.30#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:22:18.30#ibcon#enter wrdev, iclass 20, count 0 2006.168.08:22:18.30#ibcon#first serial, iclass 20, count 0 2006.168.08:22:18.30#ibcon#enter sib2, iclass 20, count 0 2006.168.08:22:18.30#ibcon#flushed, iclass 20, count 0 2006.168.08:22:18.30#ibcon#about to write, iclass 20, count 0 2006.168.08:22:18.30#ibcon#wrote, iclass 20, count 0 2006.168.08:22:18.30#ibcon#about to read 3, iclass 20, count 0 2006.168.08:22:18.32#ibcon#read 3, iclass 20, count 0 2006.168.08:22:18.32#ibcon#about to read 4, iclass 20, count 0 2006.168.08:22:18.32#ibcon#read 4, iclass 20, count 0 2006.168.08:22:18.32#ibcon#about to read 5, iclass 20, count 0 2006.168.08:22:18.32#ibcon#read 5, iclass 20, count 0 2006.168.08:22:18.32#ibcon#about to read 6, iclass 20, count 0 2006.168.08:22:18.32#ibcon#read 6, iclass 20, count 0 2006.168.08:22:18.32#ibcon#end of sib2, iclass 20, count 0 2006.168.08:22:18.32#ibcon#*mode == 0, iclass 20, count 0 2006.168.08:22:18.32#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.168.08:22:18.32#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.08:22:18.32#ibcon#*before write, iclass 20, count 0 2006.168.08:22:18.32#ibcon#enter sib2, iclass 20, count 0 2006.168.08:22:18.32#ibcon#flushed, iclass 20, count 0 2006.168.08:22:18.32#ibcon#about to write, iclass 20, count 0 2006.168.08:22:18.32#ibcon#wrote, iclass 20, count 0 2006.168.08:22:18.32#ibcon#about to read 3, iclass 20, count 0 2006.168.08:22:18.36#ibcon#read 3, iclass 20, count 0 2006.168.08:22:18.36#ibcon#about to read 4, iclass 20, count 0 2006.168.08:22:18.36#ibcon#read 4, iclass 20, count 0 2006.168.08:22:18.36#ibcon#about to read 5, iclass 20, count 0 2006.168.08:22:18.36#ibcon#read 5, iclass 20, count 0 2006.168.08:22:18.36#ibcon#about to read 6, iclass 20, count 0 2006.168.08:22:18.36#ibcon#read 6, iclass 20, count 0 2006.168.08:22:18.36#ibcon#end of sib2, iclass 20, count 0 2006.168.08:22:18.36#ibcon#*after write, iclass 20, count 0 2006.168.08:22:18.36#ibcon#*before return 0, iclass 20, count 0 2006.168.08:22:18.36#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:22:18.36#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:22:18.36#ibcon#about to clear, iclass 20 cls_cnt 0 2006.168.08:22:18.36#ibcon#cleared, iclass 20 cls_cnt 0 2006.168.08:22:18.36$vc4f8/va=2,7 2006.168.08:22:18.36#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.168.08:22:18.36#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.168.08:22:18.36#ibcon#ireg 11 cls_cnt 2 2006.168.08:22:18.36#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.168.08:22:18.42#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.168.08:22:18.42#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.168.08:22:18.42#ibcon#enter wrdev, iclass 22, count 2 2006.168.08:22:18.42#ibcon#first serial, iclass 22, count 2 2006.168.08:22:18.42#ibcon#enter sib2, iclass 22, count 2 2006.168.08:22:18.42#ibcon#flushed, iclass 22, count 2 2006.168.08:22:18.42#ibcon#about to write, iclass 22, count 2 2006.168.08:22:18.42#ibcon#wrote, iclass 22, count 2 2006.168.08:22:18.42#ibcon#about to read 3, iclass 22, count 2 2006.168.08:22:18.44#ibcon#read 3, iclass 22, count 2 2006.168.08:22:18.44#ibcon#about to read 4, iclass 22, count 2 2006.168.08:22:18.44#ibcon#read 4, iclass 22, count 2 2006.168.08:22:18.44#ibcon#about to read 5, iclass 22, count 2 2006.168.08:22:18.44#ibcon#read 5, iclass 22, count 2 2006.168.08:22:18.44#ibcon#about to read 6, iclass 22, count 2 2006.168.08:22:18.44#ibcon#read 6, iclass 22, count 2 2006.168.08:22:18.44#ibcon#end of sib2, iclass 22, count 2 2006.168.08:22:18.44#ibcon#*mode == 0, iclass 22, count 2 2006.168.08:22:18.44#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.168.08:22:18.44#ibcon#[25=AT02-07\r\n] 2006.168.08:22:18.44#ibcon#*before write, iclass 22, count 2 2006.168.08:22:18.44#ibcon#enter sib2, iclass 22, count 2 2006.168.08:22:18.44#ibcon#flushed, iclass 22, count 2 2006.168.08:22:18.44#ibcon#about to write, iclass 22, count 2 2006.168.08:22:18.44#ibcon#wrote, iclass 22, count 2 2006.168.08:22:18.44#ibcon#about to read 3, iclass 22, count 2 2006.168.08:22:18.47#ibcon#read 3, iclass 22, count 2 2006.168.08:22:18.47#ibcon#about to read 4, iclass 22, count 2 2006.168.08:22:18.47#ibcon#read 4, iclass 22, count 2 2006.168.08:22:18.47#ibcon#about to read 5, iclass 22, count 2 2006.168.08:22:18.47#ibcon#read 5, iclass 22, count 2 2006.168.08:22:18.47#ibcon#about to read 6, iclass 22, count 2 2006.168.08:22:18.47#ibcon#read 6, iclass 22, count 2 2006.168.08:22:18.47#ibcon#end of sib2, iclass 22, count 2 2006.168.08:22:18.47#ibcon#*after write, iclass 22, count 2 2006.168.08:22:18.47#ibcon#*before return 0, iclass 22, count 2 2006.168.08:22:18.47#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.168.08:22:18.47#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.168.08:22:18.47#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.168.08:22:18.47#ibcon#ireg 7 cls_cnt 0 2006.168.08:22:18.47#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.168.08:22:18.59#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.168.08:22:18.59#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.168.08:22:18.59#ibcon#enter wrdev, iclass 22, count 0 2006.168.08:22:18.59#ibcon#first serial, iclass 22, count 0 2006.168.08:22:18.59#ibcon#enter sib2, iclass 22, count 0 2006.168.08:22:18.59#ibcon#flushed, iclass 22, count 0 2006.168.08:22:18.59#ibcon#about to write, iclass 22, count 0 2006.168.08:22:18.59#ibcon#wrote, iclass 22, count 0 2006.168.08:22:18.59#ibcon#about to read 3, iclass 22, count 0 2006.168.08:22:18.61#ibcon#read 3, iclass 22, count 0 2006.168.08:22:18.61#ibcon#about to read 4, iclass 22, count 0 2006.168.08:22:18.61#ibcon#read 4, iclass 22, count 0 2006.168.08:22:18.61#ibcon#about to read 5, iclass 22, count 0 2006.168.08:22:18.61#ibcon#read 5, iclass 22, count 0 2006.168.08:22:18.61#ibcon#about to read 6, iclass 22, count 0 2006.168.08:22:18.61#ibcon#read 6, iclass 22, count 0 2006.168.08:22:18.61#ibcon#end of sib2, iclass 22, count 0 2006.168.08:22:18.61#ibcon#*mode == 0, iclass 22, count 0 2006.168.08:22:18.61#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.168.08:22:18.61#ibcon#[25=USB\r\n] 2006.168.08:22:18.61#ibcon#*before write, iclass 22, count 0 2006.168.08:22:18.61#ibcon#enter sib2, iclass 22, count 0 2006.168.08:22:18.61#ibcon#flushed, iclass 22, count 0 2006.168.08:22:18.61#ibcon#about to write, iclass 22, count 0 2006.168.08:22:18.61#ibcon#wrote, iclass 22, count 0 2006.168.08:22:18.61#ibcon#about to read 3, iclass 22, count 0 2006.168.08:22:18.64#ibcon#read 3, iclass 22, count 0 2006.168.08:22:18.64#ibcon#about to read 4, iclass 22, count 0 2006.168.08:22:18.64#ibcon#read 4, iclass 22, count 0 2006.168.08:22:18.64#ibcon#about to read 5, iclass 22, count 0 2006.168.08:22:18.64#ibcon#read 5, iclass 22, count 0 2006.168.08:22:18.64#ibcon#about to read 6, iclass 22, count 0 2006.168.08:22:18.64#ibcon#read 6, iclass 22, count 0 2006.168.08:22:18.64#ibcon#end of sib2, iclass 22, count 0 2006.168.08:22:18.64#ibcon#*after write, iclass 22, count 0 2006.168.08:22:18.64#ibcon#*before return 0, iclass 22, count 0 2006.168.08:22:18.64#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.168.08:22:18.64#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.168.08:22:18.64#ibcon#about to clear, iclass 22 cls_cnt 0 2006.168.08:22:18.64#ibcon#cleared, iclass 22 cls_cnt 0 2006.168.08:22:18.64$vc4f8/valo=3,672.99 2006.168.08:22:18.64#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.168.08:22:18.64#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.168.08:22:18.64#ibcon#ireg 17 cls_cnt 0 2006.168.08:22:18.64#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.168.08:22:18.64#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.168.08:22:18.64#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.168.08:22:18.64#ibcon#enter wrdev, iclass 24, count 0 2006.168.08:22:18.64#ibcon#first serial, iclass 24, count 0 2006.168.08:22:18.64#ibcon#enter sib2, iclass 24, count 0 2006.168.08:22:18.64#ibcon#flushed, iclass 24, count 0 2006.168.08:22:18.64#ibcon#about to write, iclass 24, count 0 2006.168.08:22:18.64#ibcon#wrote, iclass 24, count 0 2006.168.08:22:18.64#ibcon#about to read 3, iclass 24, count 0 2006.168.08:22:18.66#ibcon#read 3, iclass 24, count 0 2006.168.08:22:18.66#ibcon#about to read 4, iclass 24, count 0 2006.168.08:22:18.66#ibcon#read 4, iclass 24, count 0 2006.168.08:22:18.66#ibcon#about to read 5, iclass 24, count 0 2006.168.08:22:18.66#ibcon#read 5, iclass 24, count 0 2006.168.08:22:18.66#ibcon#about to read 6, iclass 24, count 0 2006.168.08:22:18.66#ibcon#read 6, iclass 24, count 0 2006.168.08:22:18.66#ibcon#end of sib2, iclass 24, count 0 2006.168.08:22:18.66#ibcon#*mode == 0, iclass 24, count 0 2006.168.08:22:18.66#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.168.08:22:18.66#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.08:22:18.66#ibcon#*before write, iclass 24, count 0 2006.168.08:22:18.66#ibcon#enter sib2, iclass 24, count 0 2006.168.08:22:18.66#ibcon#flushed, iclass 24, count 0 2006.168.08:22:18.66#ibcon#about to write, iclass 24, count 0 2006.168.08:22:18.66#ibcon#wrote, iclass 24, count 0 2006.168.08:22:18.66#ibcon#about to read 3, iclass 24, count 0 2006.168.08:22:18.70#ibcon#read 3, iclass 24, count 0 2006.168.08:22:18.70#ibcon#about to read 4, iclass 24, count 0 2006.168.08:22:18.70#ibcon#read 4, iclass 24, count 0 2006.168.08:22:18.70#ibcon#about to read 5, iclass 24, count 0 2006.168.08:22:18.70#ibcon#read 5, iclass 24, count 0 2006.168.08:22:18.70#ibcon#about to read 6, iclass 24, count 0 2006.168.08:22:18.70#ibcon#read 6, iclass 24, count 0 2006.168.08:22:18.70#ibcon#end of sib2, iclass 24, count 0 2006.168.08:22:18.70#ibcon#*after write, iclass 24, count 0 2006.168.08:22:18.70#ibcon#*before return 0, iclass 24, count 0 2006.168.08:22:18.70#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.168.08:22:18.70#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.168.08:22:18.70#ibcon#about to clear, iclass 24 cls_cnt 0 2006.168.08:22:18.70#ibcon#cleared, iclass 24 cls_cnt 0 2006.168.08:22:18.70$vc4f8/va=3,6 2006.168.08:22:18.70#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.168.08:22:18.70#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.168.08:22:18.70#ibcon#ireg 11 cls_cnt 2 2006.168.08:22:18.70#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.168.08:22:18.76#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.168.08:22:18.76#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.168.08:22:18.76#ibcon#enter wrdev, iclass 26, count 2 2006.168.08:22:18.76#ibcon#first serial, iclass 26, count 2 2006.168.08:22:18.76#ibcon#enter sib2, iclass 26, count 2 2006.168.08:22:18.76#ibcon#flushed, iclass 26, count 2 2006.168.08:22:18.76#ibcon#about to write, iclass 26, count 2 2006.168.08:22:18.76#ibcon#wrote, iclass 26, count 2 2006.168.08:22:18.76#ibcon#about to read 3, iclass 26, count 2 2006.168.08:22:18.78#ibcon#read 3, iclass 26, count 2 2006.168.08:22:18.78#ibcon#about to read 4, iclass 26, count 2 2006.168.08:22:18.78#ibcon#read 4, iclass 26, count 2 2006.168.08:22:18.78#ibcon#about to read 5, iclass 26, count 2 2006.168.08:22:18.78#ibcon#read 5, iclass 26, count 2 2006.168.08:22:18.78#ibcon#about to read 6, iclass 26, count 2 2006.168.08:22:18.78#ibcon#read 6, iclass 26, count 2 2006.168.08:22:18.78#ibcon#end of sib2, iclass 26, count 2 2006.168.08:22:18.78#ibcon#*mode == 0, iclass 26, count 2 2006.168.08:22:18.78#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.168.08:22:18.78#ibcon#[25=AT03-06\r\n] 2006.168.08:22:18.78#ibcon#*before write, iclass 26, count 2 2006.168.08:22:18.78#ibcon#enter sib2, iclass 26, count 2 2006.168.08:22:18.78#ibcon#flushed, iclass 26, count 2 2006.168.08:22:18.78#ibcon#about to write, iclass 26, count 2 2006.168.08:22:18.78#ibcon#wrote, iclass 26, count 2 2006.168.08:22:18.78#ibcon#about to read 3, iclass 26, count 2 2006.168.08:22:18.81#ibcon#read 3, iclass 26, count 2 2006.168.08:22:18.81#ibcon#about to read 4, iclass 26, count 2 2006.168.08:22:18.81#ibcon#read 4, iclass 26, count 2 2006.168.08:22:18.81#ibcon#about to read 5, iclass 26, count 2 2006.168.08:22:18.81#ibcon#read 5, iclass 26, count 2 2006.168.08:22:18.81#ibcon#about to read 6, iclass 26, count 2 2006.168.08:22:18.81#ibcon#read 6, iclass 26, count 2 2006.168.08:22:18.81#ibcon#end of sib2, iclass 26, count 2 2006.168.08:22:18.81#ibcon#*after write, iclass 26, count 2 2006.168.08:22:18.81#ibcon#*before return 0, iclass 26, count 2 2006.168.08:22:18.81#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.168.08:22:18.81#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.168.08:22:18.81#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.168.08:22:18.81#ibcon#ireg 7 cls_cnt 0 2006.168.08:22:18.81#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.168.08:22:18.93#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.168.08:22:18.93#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.168.08:22:18.93#ibcon#enter wrdev, iclass 26, count 0 2006.168.08:22:18.93#ibcon#first serial, iclass 26, count 0 2006.168.08:22:18.93#ibcon#enter sib2, iclass 26, count 0 2006.168.08:22:18.93#ibcon#flushed, iclass 26, count 0 2006.168.08:22:18.93#ibcon#about to write, iclass 26, count 0 2006.168.08:22:18.93#ibcon#wrote, iclass 26, count 0 2006.168.08:22:18.93#ibcon#about to read 3, iclass 26, count 0 2006.168.08:22:18.95#ibcon#read 3, iclass 26, count 0 2006.168.08:22:18.95#ibcon#about to read 4, iclass 26, count 0 2006.168.08:22:18.95#ibcon#read 4, iclass 26, count 0 2006.168.08:22:18.95#ibcon#about to read 5, iclass 26, count 0 2006.168.08:22:18.95#ibcon#read 5, iclass 26, count 0 2006.168.08:22:18.95#ibcon#about to read 6, iclass 26, count 0 2006.168.08:22:18.95#ibcon#read 6, iclass 26, count 0 2006.168.08:22:18.95#ibcon#end of sib2, iclass 26, count 0 2006.168.08:22:18.95#ibcon#*mode == 0, iclass 26, count 0 2006.168.08:22:18.95#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.168.08:22:18.95#ibcon#[25=USB\r\n] 2006.168.08:22:18.95#ibcon#*before write, iclass 26, count 0 2006.168.08:22:18.95#ibcon#enter sib2, iclass 26, count 0 2006.168.08:22:18.95#ibcon#flushed, iclass 26, count 0 2006.168.08:22:18.95#ibcon#about to write, iclass 26, count 0 2006.168.08:22:18.95#ibcon#wrote, iclass 26, count 0 2006.168.08:22:18.95#ibcon#about to read 3, iclass 26, count 0 2006.168.08:22:18.98#ibcon#read 3, iclass 26, count 0 2006.168.08:22:18.98#ibcon#about to read 4, iclass 26, count 0 2006.168.08:22:18.98#ibcon#read 4, iclass 26, count 0 2006.168.08:22:18.98#ibcon#about to read 5, iclass 26, count 0 2006.168.08:22:18.98#ibcon#read 5, iclass 26, count 0 2006.168.08:22:18.98#ibcon#about to read 6, iclass 26, count 0 2006.168.08:22:18.98#ibcon#read 6, iclass 26, count 0 2006.168.08:22:18.98#ibcon#end of sib2, iclass 26, count 0 2006.168.08:22:18.98#ibcon#*after write, iclass 26, count 0 2006.168.08:22:18.98#ibcon#*before return 0, iclass 26, count 0 2006.168.08:22:18.98#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.168.08:22:18.98#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.168.08:22:18.98#ibcon#about to clear, iclass 26 cls_cnt 0 2006.168.08:22:18.98#ibcon#cleared, iclass 26 cls_cnt 0 2006.168.08:22:18.98$vc4f8/valo=4,832.99 2006.168.08:22:18.98#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.168.08:22:18.98#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.168.08:22:18.98#ibcon#ireg 17 cls_cnt 0 2006.168.08:22:18.98#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.168.08:22:18.98#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.168.08:22:18.98#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.168.08:22:18.98#ibcon#enter wrdev, iclass 28, count 0 2006.168.08:22:18.98#ibcon#first serial, iclass 28, count 0 2006.168.08:22:18.98#ibcon#enter sib2, iclass 28, count 0 2006.168.08:22:18.98#ibcon#flushed, iclass 28, count 0 2006.168.08:22:18.98#ibcon#about to write, iclass 28, count 0 2006.168.08:22:18.98#ibcon#wrote, iclass 28, count 0 2006.168.08:22:18.98#ibcon#about to read 3, iclass 28, count 0 2006.168.08:22:19.00#ibcon#read 3, iclass 28, count 0 2006.168.08:22:19.00#ibcon#about to read 4, iclass 28, count 0 2006.168.08:22:19.00#ibcon#read 4, iclass 28, count 0 2006.168.08:22:19.00#ibcon#about to read 5, iclass 28, count 0 2006.168.08:22:19.00#ibcon#read 5, iclass 28, count 0 2006.168.08:22:19.00#ibcon#about to read 6, iclass 28, count 0 2006.168.08:22:19.00#ibcon#read 6, iclass 28, count 0 2006.168.08:22:19.00#ibcon#end of sib2, iclass 28, count 0 2006.168.08:22:19.00#ibcon#*mode == 0, iclass 28, count 0 2006.168.08:22:19.00#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.168.08:22:19.00#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.08:22:19.00#ibcon#*before write, iclass 28, count 0 2006.168.08:22:19.00#ibcon#enter sib2, iclass 28, count 0 2006.168.08:22:19.00#ibcon#flushed, iclass 28, count 0 2006.168.08:22:19.00#ibcon#about to write, iclass 28, count 0 2006.168.08:22:19.00#ibcon#wrote, iclass 28, count 0 2006.168.08:22:19.00#ibcon#about to read 3, iclass 28, count 0 2006.168.08:22:19.04#ibcon#read 3, iclass 28, count 0 2006.168.08:22:19.04#ibcon#about to read 4, iclass 28, count 0 2006.168.08:22:19.04#ibcon#read 4, iclass 28, count 0 2006.168.08:22:19.04#ibcon#about to read 5, iclass 28, count 0 2006.168.08:22:19.04#ibcon#read 5, iclass 28, count 0 2006.168.08:22:19.04#ibcon#about to read 6, iclass 28, count 0 2006.168.08:22:19.04#ibcon#read 6, iclass 28, count 0 2006.168.08:22:19.04#ibcon#end of sib2, iclass 28, count 0 2006.168.08:22:19.04#ibcon#*after write, iclass 28, count 0 2006.168.08:22:19.04#ibcon#*before return 0, iclass 28, count 0 2006.168.08:22:19.04#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.168.08:22:19.04#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.168.08:22:19.04#ibcon#about to clear, iclass 28 cls_cnt 0 2006.168.08:22:19.04#ibcon#cleared, iclass 28 cls_cnt 0 2006.168.08:22:19.04$vc4f8/va=4,7 2006.168.08:22:19.04#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.168.08:22:19.04#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.168.08:22:19.04#ibcon#ireg 11 cls_cnt 2 2006.168.08:22:19.04#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.168.08:22:19.10#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.168.08:22:19.10#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.168.08:22:19.10#ibcon#enter wrdev, iclass 30, count 2 2006.168.08:22:19.10#ibcon#first serial, iclass 30, count 2 2006.168.08:22:19.10#ibcon#enter sib2, iclass 30, count 2 2006.168.08:22:19.10#ibcon#flushed, iclass 30, count 2 2006.168.08:22:19.10#ibcon#about to write, iclass 30, count 2 2006.168.08:22:19.10#ibcon#wrote, iclass 30, count 2 2006.168.08:22:19.10#ibcon#about to read 3, iclass 30, count 2 2006.168.08:22:19.12#ibcon#read 3, iclass 30, count 2 2006.168.08:22:19.12#ibcon#about to read 4, iclass 30, count 2 2006.168.08:22:19.12#ibcon#read 4, iclass 30, count 2 2006.168.08:22:19.12#ibcon#about to read 5, iclass 30, count 2 2006.168.08:22:19.12#ibcon#read 5, iclass 30, count 2 2006.168.08:22:19.12#ibcon#about to read 6, iclass 30, count 2 2006.168.08:22:19.12#ibcon#read 6, iclass 30, count 2 2006.168.08:22:19.12#ibcon#end of sib2, iclass 30, count 2 2006.168.08:22:19.12#ibcon#*mode == 0, iclass 30, count 2 2006.168.08:22:19.12#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.168.08:22:19.12#ibcon#[25=AT04-07\r\n] 2006.168.08:22:19.12#ibcon#*before write, iclass 30, count 2 2006.168.08:22:19.12#ibcon#enter sib2, iclass 30, count 2 2006.168.08:22:19.12#ibcon#flushed, iclass 30, count 2 2006.168.08:22:19.12#ibcon#about to write, iclass 30, count 2 2006.168.08:22:19.12#ibcon#wrote, iclass 30, count 2 2006.168.08:22:19.12#ibcon#about to read 3, iclass 30, count 2 2006.168.08:22:19.15#ibcon#read 3, iclass 30, count 2 2006.168.08:22:19.15#ibcon#about to read 4, iclass 30, count 2 2006.168.08:22:19.15#ibcon#read 4, iclass 30, count 2 2006.168.08:22:19.15#ibcon#about to read 5, iclass 30, count 2 2006.168.08:22:19.15#ibcon#read 5, iclass 30, count 2 2006.168.08:22:19.15#ibcon#about to read 6, iclass 30, count 2 2006.168.08:22:19.15#ibcon#read 6, iclass 30, count 2 2006.168.08:22:19.15#ibcon#end of sib2, iclass 30, count 2 2006.168.08:22:19.15#ibcon#*after write, iclass 30, count 2 2006.168.08:22:19.15#ibcon#*before return 0, iclass 30, count 2 2006.168.08:22:19.15#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.168.08:22:19.15#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.168.08:22:19.15#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.168.08:22:19.15#ibcon#ireg 7 cls_cnt 0 2006.168.08:22:19.15#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.168.08:22:19.27#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.168.08:22:19.27#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.168.08:22:19.27#ibcon#enter wrdev, iclass 30, count 0 2006.168.08:22:19.27#ibcon#first serial, iclass 30, count 0 2006.168.08:22:19.27#ibcon#enter sib2, iclass 30, count 0 2006.168.08:22:19.27#ibcon#flushed, iclass 30, count 0 2006.168.08:22:19.27#ibcon#about to write, iclass 30, count 0 2006.168.08:22:19.27#ibcon#wrote, iclass 30, count 0 2006.168.08:22:19.27#ibcon#about to read 3, iclass 30, count 0 2006.168.08:22:19.29#ibcon#read 3, iclass 30, count 0 2006.168.08:22:19.29#ibcon#about to read 4, iclass 30, count 0 2006.168.08:22:19.29#ibcon#read 4, iclass 30, count 0 2006.168.08:22:19.29#ibcon#about to read 5, iclass 30, count 0 2006.168.08:22:19.29#ibcon#read 5, iclass 30, count 0 2006.168.08:22:19.29#ibcon#about to read 6, iclass 30, count 0 2006.168.08:22:19.29#ibcon#read 6, iclass 30, count 0 2006.168.08:22:19.29#ibcon#end of sib2, iclass 30, count 0 2006.168.08:22:19.29#ibcon#*mode == 0, iclass 30, count 0 2006.168.08:22:19.29#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.168.08:22:19.29#ibcon#[25=USB\r\n] 2006.168.08:22:19.29#ibcon#*before write, iclass 30, count 0 2006.168.08:22:19.29#ibcon#enter sib2, iclass 30, count 0 2006.168.08:22:19.29#ibcon#flushed, iclass 30, count 0 2006.168.08:22:19.29#ibcon#about to write, iclass 30, count 0 2006.168.08:22:19.29#ibcon#wrote, iclass 30, count 0 2006.168.08:22:19.29#ibcon#about to read 3, iclass 30, count 0 2006.168.08:22:19.32#ibcon#read 3, iclass 30, count 0 2006.168.08:22:19.32#ibcon#about to read 4, iclass 30, count 0 2006.168.08:22:19.32#ibcon#read 4, iclass 30, count 0 2006.168.08:22:19.32#ibcon#about to read 5, iclass 30, count 0 2006.168.08:22:19.32#ibcon#read 5, iclass 30, count 0 2006.168.08:22:19.32#ibcon#about to read 6, iclass 30, count 0 2006.168.08:22:19.32#ibcon#read 6, iclass 30, count 0 2006.168.08:22:19.32#ibcon#end of sib2, iclass 30, count 0 2006.168.08:22:19.32#ibcon#*after write, iclass 30, count 0 2006.168.08:22:19.32#ibcon#*before return 0, iclass 30, count 0 2006.168.08:22:19.32#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.168.08:22:19.32#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.168.08:22:19.32#ibcon#about to clear, iclass 30 cls_cnt 0 2006.168.08:22:19.32#ibcon#cleared, iclass 30 cls_cnt 0 2006.168.08:22:19.32$vc4f8/valo=5,652.99 2006.168.08:22:19.32#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.168.08:22:19.32#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.168.08:22:19.32#ibcon#ireg 17 cls_cnt 0 2006.168.08:22:19.32#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:22:19.32#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:22:19.32#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:22:19.32#ibcon#enter wrdev, iclass 32, count 0 2006.168.08:22:19.32#ibcon#first serial, iclass 32, count 0 2006.168.08:22:19.32#ibcon#enter sib2, iclass 32, count 0 2006.168.08:22:19.32#ibcon#flushed, iclass 32, count 0 2006.168.08:22:19.32#ibcon#about to write, iclass 32, count 0 2006.168.08:22:19.32#ibcon#wrote, iclass 32, count 0 2006.168.08:22:19.32#ibcon#about to read 3, iclass 32, count 0 2006.168.08:22:19.34#ibcon#read 3, iclass 32, count 0 2006.168.08:22:19.34#ibcon#about to read 4, iclass 32, count 0 2006.168.08:22:19.34#ibcon#read 4, iclass 32, count 0 2006.168.08:22:19.34#ibcon#about to read 5, iclass 32, count 0 2006.168.08:22:19.34#ibcon#read 5, iclass 32, count 0 2006.168.08:22:19.34#ibcon#about to read 6, iclass 32, count 0 2006.168.08:22:19.34#ibcon#read 6, iclass 32, count 0 2006.168.08:22:19.34#ibcon#end of sib2, iclass 32, count 0 2006.168.08:22:19.34#ibcon#*mode == 0, iclass 32, count 0 2006.168.08:22:19.34#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.168.08:22:19.34#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.08:22:19.34#ibcon#*before write, iclass 32, count 0 2006.168.08:22:19.34#ibcon#enter sib2, iclass 32, count 0 2006.168.08:22:19.34#ibcon#flushed, iclass 32, count 0 2006.168.08:22:19.34#ibcon#about to write, iclass 32, count 0 2006.168.08:22:19.34#ibcon#wrote, iclass 32, count 0 2006.168.08:22:19.34#ibcon#about to read 3, iclass 32, count 0 2006.168.08:22:19.38#ibcon#read 3, iclass 32, count 0 2006.168.08:22:19.38#ibcon#about to read 4, iclass 32, count 0 2006.168.08:22:19.38#ibcon#read 4, iclass 32, count 0 2006.168.08:22:19.38#ibcon#about to read 5, iclass 32, count 0 2006.168.08:22:19.38#ibcon#read 5, iclass 32, count 0 2006.168.08:22:19.38#ibcon#about to read 6, iclass 32, count 0 2006.168.08:22:19.38#ibcon#read 6, iclass 32, count 0 2006.168.08:22:19.38#ibcon#end of sib2, iclass 32, count 0 2006.168.08:22:19.38#ibcon#*after write, iclass 32, count 0 2006.168.08:22:19.38#ibcon#*before return 0, iclass 32, count 0 2006.168.08:22:19.38#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:22:19.38#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:22:19.38#ibcon#about to clear, iclass 32 cls_cnt 0 2006.168.08:22:19.38#ibcon#cleared, iclass 32 cls_cnt 0 2006.168.08:22:19.38$vc4f8/va=5,7 2006.168.08:22:19.38#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.168.08:22:19.38#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.168.08:22:19.38#ibcon#ireg 11 cls_cnt 2 2006.168.08:22:19.38#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.168.08:22:19.44#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.168.08:22:19.44#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.168.08:22:19.44#ibcon#enter wrdev, iclass 34, count 2 2006.168.08:22:19.44#ibcon#first serial, iclass 34, count 2 2006.168.08:22:19.44#ibcon#enter sib2, iclass 34, count 2 2006.168.08:22:19.44#ibcon#flushed, iclass 34, count 2 2006.168.08:22:19.44#ibcon#about to write, iclass 34, count 2 2006.168.08:22:19.44#ibcon#wrote, iclass 34, count 2 2006.168.08:22:19.44#ibcon#about to read 3, iclass 34, count 2 2006.168.08:22:19.46#ibcon#read 3, iclass 34, count 2 2006.168.08:22:19.46#ibcon#about to read 4, iclass 34, count 2 2006.168.08:22:19.46#ibcon#read 4, iclass 34, count 2 2006.168.08:22:19.46#ibcon#about to read 5, iclass 34, count 2 2006.168.08:22:19.46#ibcon#read 5, iclass 34, count 2 2006.168.08:22:19.46#ibcon#about to read 6, iclass 34, count 2 2006.168.08:22:19.46#ibcon#read 6, iclass 34, count 2 2006.168.08:22:19.46#ibcon#end of sib2, iclass 34, count 2 2006.168.08:22:19.46#ibcon#*mode == 0, iclass 34, count 2 2006.168.08:22:19.46#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.168.08:22:19.46#ibcon#[25=AT05-07\r\n] 2006.168.08:22:19.46#ibcon#*before write, iclass 34, count 2 2006.168.08:22:19.46#ibcon#enter sib2, iclass 34, count 2 2006.168.08:22:19.46#ibcon#flushed, iclass 34, count 2 2006.168.08:22:19.46#ibcon#about to write, iclass 34, count 2 2006.168.08:22:19.46#ibcon#wrote, iclass 34, count 2 2006.168.08:22:19.46#ibcon#about to read 3, iclass 34, count 2 2006.168.08:22:19.49#ibcon#read 3, iclass 34, count 2 2006.168.08:22:19.49#ibcon#about to read 4, iclass 34, count 2 2006.168.08:22:19.49#ibcon#read 4, iclass 34, count 2 2006.168.08:22:19.49#ibcon#about to read 5, iclass 34, count 2 2006.168.08:22:19.49#ibcon#read 5, iclass 34, count 2 2006.168.08:22:19.49#ibcon#about to read 6, iclass 34, count 2 2006.168.08:22:19.49#ibcon#read 6, iclass 34, count 2 2006.168.08:22:19.49#ibcon#end of sib2, iclass 34, count 2 2006.168.08:22:19.49#ibcon#*after write, iclass 34, count 2 2006.168.08:22:19.49#ibcon#*before return 0, iclass 34, count 2 2006.168.08:22:19.49#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.168.08:22:19.49#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.168.08:22:19.49#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.168.08:22:19.49#ibcon#ireg 7 cls_cnt 0 2006.168.08:22:19.49#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.168.08:22:19.61#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.168.08:22:19.61#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.168.08:22:19.61#ibcon#enter wrdev, iclass 34, count 0 2006.168.08:22:19.61#ibcon#first serial, iclass 34, count 0 2006.168.08:22:19.61#ibcon#enter sib2, iclass 34, count 0 2006.168.08:22:19.61#ibcon#flushed, iclass 34, count 0 2006.168.08:22:19.61#ibcon#about to write, iclass 34, count 0 2006.168.08:22:19.61#ibcon#wrote, iclass 34, count 0 2006.168.08:22:19.61#ibcon#about to read 3, iclass 34, count 0 2006.168.08:22:19.63#ibcon#read 3, iclass 34, count 0 2006.168.08:22:19.63#ibcon#about to read 4, iclass 34, count 0 2006.168.08:22:19.63#ibcon#read 4, iclass 34, count 0 2006.168.08:22:19.63#ibcon#about to read 5, iclass 34, count 0 2006.168.08:22:19.63#ibcon#read 5, iclass 34, count 0 2006.168.08:22:19.63#ibcon#about to read 6, iclass 34, count 0 2006.168.08:22:19.63#ibcon#read 6, iclass 34, count 0 2006.168.08:22:19.63#ibcon#end of sib2, iclass 34, count 0 2006.168.08:22:19.63#ibcon#*mode == 0, iclass 34, count 0 2006.168.08:22:19.63#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.168.08:22:19.63#ibcon#[25=USB\r\n] 2006.168.08:22:19.63#ibcon#*before write, iclass 34, count 0 2006.168.08:22:19.63#ibcon#enter sib2, iclass 34, count 0 2006.168.08:22:19.63#ibcon#flushed, iclass 34, count 0 2006.168.08:22:19.63#ibcon#about to write, iclass 34, count 0 2006.168.08:22:19.63#ibcon#wrote, iclass 34, count 0 2006.168.08:22:19.63#ibcon#about to read 3, iclass 34, count 0 2006.168.08:22:19.66#ibcon#read 3, iclass 34, count 0 2006.168.08:22:19.66#ibcon#about to read 4, iclass 34, count 0 2006.168.08:22:19.66#ibcon#read 4, iclass 34, count 0 2006.168.08:22:19.66#ibcon#about to read 5, iclass 34, count 0 2006.168.08:22:19.66#ibcon#read 5, iclass 34, count 0 2006.168.08:22:19.66#ibcon#about to read 6, iclass 34, count 0 2006.168.08:22:19.66#ibcon#read 6, iclass 34, count 0 2006.168.08:22:19.66#ibcon#end of sib2, iclass 34, count 0 2006.168.08:22:19.66#ibcon#*after write, iclass 34, count 0 2006.168.08:22:19.66#ibcon#*before return 0, iclass 34, count 0 2006.168.08:22:19.66#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.168.08:22:19.66#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.168.08:22:19.66#ibcon#about to clear, iclass 34 cls_cnt 0 2006.168.08:22:19.66#ibcon#cleared, iclass 34 cls_cnt 0 2006.168.08:22:19.66$vc4f8/valo=6,772.99 2006.168.08:22:19.66#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.168.08:22:19.66#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.168.08:22:19.66#ibcon#ireg 17 cls_cnt 0 2006.168.08:22:19.66#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.168.08:22:19.66#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.168.08:22:19.66#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.168.08:22:19.66#ibcon#enter wrdev, iclass 36, count 0 2006.168.08:22:19.66#ibcon#first serial, iclass 36, count 0 2006.168.08:22:19.66#ibcon#enter sib2, iclass 36, count 0 2006.168.08:22:19.66#ibcon#flushed, iclass 36, count 0 2006.168.08:22:19.66#ibcon#about to write, iclass 36, count 0 2006.168.08:22:19.66#ibcon#wrote, iclass 36, count 0 2006.168.08:22:19.66#ibcon#about to read 3, iclass 36, count 0 2006.168.08:22:19.68#ibcon#read 3, iclass 36, count 0 2006.168.08:22:19.68#ibcon#about to read 4, iclass 36, count 0 2006.168.08:22:19.68#ibcon#read 4, iclass 36, count 0 2006.168.08:22:19.68#ibcon#about to read 5, iclass 36, count 0 2006.168.08:22:19.68#ibcon#read 5, iclass 36, count 0 2006.168.08:22:19.68#ibcon#about to read 6, iclass 36, count 0 2006.168.08:22:19.68#ibcon#read 6, iclass 36, count 0 2006.168.08:22:19.68#ibcon#end of sib2, iclass 36, count 0 2006.168.08:22:19.68#ibcon#*mode == 0, iclass 36, count 0 2006.168.08:22:19.68#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.168.08:22:19.68#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.08:22:19.68#ibcon#*before write, iclass 36, count 0 2006.168.08:22:19.68#ibcon#enter sib2, iclass 36, count 0 2006.168.08:22:19.68#ibcon#flushed, iclass 36, count 0 2006.168.08:22:19.68#ibcon#about to write, iclass 36, count 0 2006.168.08:22:19.68#ibcon#wrote, iclass 36, count 0 2006.168.08:22:19.68#ibcon#about to read 3, iclass 36, count 0 2006.168.08:22:19.72#ibcon#read 3, iclass 36, count 0 2006.168.08:22:19.72#ibcon#about to read 4, iclass 36, count 0 2006.168.08:22:19.72#ibcon#read 4, iclass 36, count 0 2006.168.08:22:19.72#ibcon#about to read 5, iclass 36, count 0 2006.168.08:22:19.72#ibcon#read 5, iclass 36, count 0 2006.168.08:22:19.72#ibcon#about to read 6, iclass 36, count 0 2006.168.08:22:19.72#ibcon#read 6, iclass 36, count 0 2006.168.08:22:19.72#ibcon#end of sib2, iclass 36, count 0 2006.168.08:22:19.72#ibcon#*after write, iclass 36, count 0 2006.168.08:22:19.72#ibcon#*before return 0, iclass 36, count 0 2006.168.08:22:19.72#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.168.08:22:19.72#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.168.08:22:19.72#ibcon#about to clear, iclass 36 cls_cnt 0 2006.168.08:22:19.72#ibcon#cleared, iclass 36 cls_cnt 0 2006.168.08:22:19.72$vc4f8/va=6,6 2006.168.08:22:19.72#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.168.08:22:19.72#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.168.08:22:19.72#ibcon#ireg 11 cls_cnt 2 2006.168.08:22:19.72#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.168.08:22:19.78#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.168.08:22:19.78#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.168.08:22:19.78#ibcon#enter wrdev, iclass 38, count 2 2006.168.08:22:19.78#ibcon#first serial, iclass 38, count 2 2006.168.08:22:19.78#ibcon#enter sib2, iclass 38, count 2 2006.168.08:22:19.78#ibcon#flushed, iclass 38, count 2 2006.168.08:22:19.78#ibcon#about to write, iclass 38, count 2 2006.168.08:22:19.78#ibcon#wrote, iclass 38, count 2 2006.168.08:22:19.78#ibcon#about to read 3, iclass 38, count 2 2006.168.08:22:19.80#ibcon#read 3, iclass 38, count 2 2006.168.08:22:19.80#ibcon#about to read 4, iclass 38, count 2 2006.168.08:22:19.80#ibcon#read 4, iclass 38, count 2 2006.168.08:22:19.80#ibcon#about to read 5, iclass 38, count 2 2006.168.08:22:19.80#ibcon#read 5, iclass 38, count 2 2006.168.08:22:19.80#ibcon#about to read 6, iclass 38, count 2 2006.168.08:22:19.80#ibcon#read 6, iclass 38, count 2 2006.168.08:22:19.80#ibcon#end of sib2, iclass 38, count 2 2006.168.08:22:19.80#ibcon#*mode == 0, iclass 38, count 2 2006.168.08:22:19.80#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.168.08:22:19.80#ibcon#[25=AT06-06\r\n] 2006.168.08:22:19.80#ibcon#*before write, iclass 38, count 2 2006.168.08:22:19.80#ibcon#enter sib2, iclass 38, count 2 2006.168.08:22:19.80#ibcon#flushed, iclass 38, count 2 2006.168.08:22:19.80#ibcon#about to write, iclass 38, count 2 2006.168.08:22:19.80#ibcon#wrote, iclass 38, count 2 2006.168.08:22:19.80#ibcon#about to read 3, iclass 38, count 2 2006.168.08:22:19.83#ibcon#read 3, iclass 38, count 2 2006.168.08:22:19.83#ibcon#about to read 4, iclass 38, count 2 2006.168.08:22:19.83#ibcon#read 4, iclass 38, count 2 2006.168.08:22:19.83#ibcon#about to read 5, iclass 38, count 2 2006.168.08:22:19.83#ibcon#read 5, iclass 38, count 2 2006.168.08:22:19.83#ibcon#about to read 6, iclass 38, count 2 2006.168.08:22:19.83#ibcon#read 6, iclass 38, count 2 2006.168.08:22:19.83#ibcon#end of sib2, iclass 38, count 2 2006.168.08:22:19.83#ibcon#*after write, iclass 38, count 2 2006.168.08:22:19.83#ibcon#*before return 0, iclass 38, count 2 2006.168.08:22:19.83#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.168.08:22:19.83#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.168.08:22:19.83#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.168.08:22:19.83#ibcon#ireg 7 cls_cnt 0 2006.168.08:22:19.83#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.168.08:22:19.95#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.168.08:22:19.95#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.168.08:22:19.95#ibcon#enter wrdev, iclass 38, count 0 2006.168.08:22:19.95#ibcon#first serial, iclass 38, count 0 2006.168.08:22:19.95#ibcon#enter sib2, iclass 38, count 0 2006.168.08:22:19.95#ibcon#flushed, iclass 38, count 0 2006.168.08:22:19.95#ibcon#about to write, iclass 38, count 0 2006.168.08:22:19.95#ibcon#wrote, iclass 38, count 0 2006.168.08:22:19.95#ibcon#about to read 3, iclass 38, count 0 2006.168.08:22:19.97#ibcon#read 3, iclass 38, count 0 2006.168.08:22:19.97#ibcon#about to read 4, iclass 38, count 0 2006.168.08:22:19.97#ibcon#read 4, iclass 38, count 0 2006.168.08:22:19.97#ibcon#about to read 5, iclass 38, count 0 2006.168.08:22:19.97#ibcon#read 5, iclass 38, count 0 2006.168.08:22:19.97#ibcon#about to read 6, iclass 38, count 0 2006.168.08:22:19.97#ibcon#read 6, iclass 38, count 0 2006.168.08:22:19.97#ibcon#end of sib2, iclass 38, count 0 2006.168.08:22:19.97#ibcon#*mode == 0, iclass 38, count 0 2006.168.08:22:19.97#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.168.08:22:19.97#ibcon#[25=USB\r\n] 2006.168.08:22:19.97#ibcon#*before write, iclass 38, count 0 2006.168.08:22:19.97#ibcon#enter sib2, iclass 38, count 0 2006.168.08:22:19.97#ibcon#flushed, iclass 38, count 0 2006.168.08:22:19.97#ibcon#about to write, iclass 38, count 0 2006.168.08:22:19.97#ibcon#wrote, iclass 38, count 0 2006.168.08:22:19.97#ibcon#about to read 3, iclass 38, count 0 2006.168.08:22:20.00#ibcon#read 3, iclass 38, count 0 2006.168.08:22:20.00#ibcon#about to read 4, iclass 38, count 0 2006.168.08:22:20.00#ibcon#read 4, iclass 38, count 0 2006.168.08:22:20.00#ibcon#about to read 5, iclass 38, count 0 2006.168.08:22:20.00#ibcon#read 5, iclass 38, count 0 2006.168.08:22:20.00#ibcon#about to read 6, iclass 38, count 0 2006.168.08:22:20.00#ibcon#read 6, iclass 38, count 0 2006.168.08:22:20.00#ibcon#end of sib2, iclass 38, count 0 2006.168.08:22:20.00#ibcon#*after write, iclass 38, count 0 2006.168.08:22:20.00#ibcon#*before return 0, iclass 38, count 0 2006.168.08:22:20.00#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.168.08:22:20.00#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.168.08:22:20.00#ibcon#about to clear, iclass 38 cls_cnt 0 2006.168.08:22:20.00#ibcon#cleared, iclass 38 cls_cnt 0 2006.168.08:22:20.00$vc4f8/valo=7,832.99 2006.168.08:22:20.00#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.168.08:22:20.00#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.168.08:22:20.00#ibcon#ireg 17 cls_cnt 0 2006.168.08:22:20.00#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:22:20.00#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:22:20.00#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:22:20.00#ibcon#enter wrdev, iclass 40, count 0 2006.168.08:22:20.00#ibcon#first serial, iclass 40, count 0 2006.168.08:22:20.00#ibcon#enter sib2, iclass 40, count 0 2006.168.08:22:20.00#ibcon#flushed, iclass 40, count 0 2006.168.08:22:20.00#ibcon#about to write, iclass 40, count 0 2006.168.08:22:20.00#ibcon#wrote, iclass 40, count 0 2006.168.08:22:20.00#ibcon#about to read 3, iclass 40, count 0 2006.168.08:22:20.02#ibcon#read 3, iclass 40, count 0 2006.168.08:22:20.02#ibcon#about to read 4, iclass 40, count 0 2006.168.08:22:20.02#ibcon#read 4, iclass 40, count 0 2006.168.08:22:20.02#ibcon#about to read 5, iclass 40, count 0 2006.168.08:22:20.02#ibcon#read 5, iclass 40, count 0 2006.168.08:22:20.02#ibcon#about to read 6, iclass 40, count 0 2006.168.08:22:20.02#ibcon#read 6, iclass 40, count 0 2006.168.08:22:20.02#ibcon#end of sib2, iclass 40, count 0 2006.168.08:22:20.02#ibcon#*mode == 0, iclass 40, count 0 2006.168.08:22:20.02#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.168.08:22:20.02#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.08:22:20.02#ibcon#*before write, iclass 40, count 0 2006.168.08:22:20.02#ibcon#enter sib2, iclass 40, count 0 2006.168.08:22:20.02#ibcon#flushed, iclass 40, count 0 2006.168.08:22:20.02#ibcon#about to write, iclass 40, count 0 2006.168.08:22:20.02#ibcon#wrote, iclass 40, count 0 2006.168.08:22:20.02#ibcon#about to read 3, iclass 40, count 0 2006.168.08:22:20.06#ibcon#read 3, iclass 40, count 0 2006.168.08:22:20.06#ibcon#about to read 4, iclass 40, count 0 2006.168.08:22:20.06#ibcon#read 4, iclass 40, count 0 2006.168.08:22:20.06#ibcon#about to read 5, iclass 40, count 0 2006.168.08:22:20.06#ibcon#read 5, iclass 40, count 0 2006.168.08:22:20.06#ibcon#about to read 6, iclass 40, count 0 2006.168.08:22:20.06#ibcon#read 6, iclass 40, count 0 2006.168.08:22:20.06#ibcon#end of sib2, iclass 40, count 0 2006.168.08:22:20.06#ibcon#*after write, iclass 40, count 0 2006.168.08:22:20.06#ibcon#*before return 0, iclass 40, count 0 2006.168.08:22:20.06#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:22:20.06#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:22:20.06#ibcon#about to clear, iclass 40 cls_cnt 0 2006.168.08:22:20.06#ibcon#cleared, iclass 40 cls_cnt 0 2006.168.08:22:20.06$vc4f8/va=7,6 2006.168.08:22:20.06#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.168.08:22:20.06#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.168.08:22:20.06#ibcon#ireg 11 cls_cnt 2 2006.168.08:22:20.06#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.168.08:22:20.12#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.168.08:22:20.12#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.168.08:22:20.12#ibcon#enter wrdev, iclass 4, count 2 2006.168.08:22:20.12#ibcon#first serial, iclass 4, count 2 2006.168.08:22:20.12#ibcon#enter sib2, iclass 4, count 2 2006.168.08:22:20.12#ibcon#flushed, iclass 4, count 2 2006.168.08:22:20.12#ibcon#about to write, iclass 4, count 2 2006.168.08:22:20.12#ibcon#wrote, iclass 4, count 2 2006.168.08:22:20.12#ibcon#about to read 3, iclass 4, count 2 2006.168.08:22:20.14#ibcon#read 3, iclass 4, count 2 2006.168.08:22:20.14#ibcon#about to read 4, iclass 4, count 2 2006.168.08:22:20.14#ibcon#read 4, iclass 4, count 2 2006.168.08:22:20.14#ibcon#about to read 5, iclass 4, count 2 2006.168.08:22:20.14#ibcon#read 5, iclass 4, count 2 2006.168.08:22:20.14#ibcon#about to read 6, iclass 4, count 2 2006.168.08:22:20.14#ibcon#read 6, iclass 4, count 2 2006.168.08:22:20.14#ibcon#end of sib2, iclass 4, count 2 2006.168.08:22:20.14#ibcon#*mode == 0, iclass 4, count 2 2006.168.08:22:20.14#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.168.08:22:20.14#ibcon#[25=AT07-06\r\n] 2006.168.08:22:20.14#ibcon#*before write, iclass 4, count 2 2006.168.08:22:20.14#ibcon#enter sib2, iclass 4, count 2 2006.168.08:22:20.14#ibcon#flushed, iclass 4, count 2 2006.168.08:22:20.14#ibcon#about to write, iclass 4, count 2 2006.168.08:22:20.14#ibcon#wrote, iclass 4, count 2 2006.168.08:22:20.14#ibcon#about to read 3, iclass 4, count 2 2006.168.08:22:20.17#ibcon#read 3, iclass 4, count 2 2006.168.08:22:20.17#ibcon#about to read 4, iclass 4, count 2 2006.168.08:22:20.17#ibcon#read 4, iclass 4, count 2 2006.168.08:22:20.17#ibcon#about to read 5, iclass 4, count 2 2006.168.08:22:20.17#ibcon#read 5, iclass 4, count 2 2006.168.08:22:20.17#ibcon#about to read 6, iclass 4, count 2 2006.168.08:22:20.17#ibcon#read 6, iclass 4, count 2 2006.168.08:22:20.17#ibcon#end of sib2, iclass 4, count 2 2006.168.08:22:20.17#ibcon#*after write, iclass 4, count 2 2006.168.08:22:20.17#ibcon#*before return 0, iclass 4, count 2 2006.168.08:22:20.17#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.168.08:22:20.17#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.168.08:22:20.17#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.168.08:22:20.17#ibcon#ireg 7 cls_cnt 0 2006.168.08:22:20.17#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.168.08:22:20.29#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.168.08:22:20.29#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.168.08:22:20.29#ibcon#enter wrdev, iclass 4, count 0 2006.168.08:22:20.29#ibcon#first serial, iclass 4, count 0 2006.168.08:22:20.29#ibcon#enter sib2, iclass 4, count 0 2006.168.08:22:20.29#ibcon#flushed, iclass 4, count 0 2006.168.08:22:20.29#ibcon#about to write, iclass 4, count 0 2006.168.08:22:20.29#ibcon#wrote, iclass 4, count 0 2006.168.08:22:20.29#ibcon#about to read 3, iclass 4, count 0 2006.168.08:22:20.31#ibcon#read 3, iclass 4, count 0 2006.168.08:22:20.31#ibcon#about to read 4, iclass 4, count 0 2006.168.08:22:20.31#ibcon#read 4, iclass 4, count 0 2006.168.08:22:20.31#ibcon#about to read 5, iclass 4, count 0 2006.168.08:22:20.31#ibcon#read 5, iclass 4, count 0 2006.168.08:22:20.31#ibcon#about to read 6, iclass 4, count 0 2006.168.08:22:20.31#ibcon#read 6, iclass 4, count 0 2006.168.08:22:20.31#ibcon#end of sib2, iclass 4, count 0 2006.168.08:22:20.31#ibcon#*mode == 0, iclass 4, count 0 2006.168.08:22:20.31#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.168.08:22:20.31#ibcon#[25=USB\r\n] 2006.168.08:22:20.31#ibcon#*before write, iclass 4, count 0 2006.168.08:22:20.31#ibcon#enter sib2, iclass 4, count 0 2006.168.08:22:20.31#ibcon#flushed, iclass 4, count 0 2006.168.08:22:20.31#ibcon#about to write, iclass 4, count 0 2006.168.08:22:20.31#ibcon#wrote, iclass 4, count 0 2006.168.08:22:20.31#ibcon#about to read 3, iclass 4, count 0 2006.168.08:22:20.34#ibcon#read 3, iclass 4, count 0 2006.168.08:22:20.34#ibcon#about to read 4, iclass 4, count 0 2006.168.08:22:20.34#ibcon#read 4, iclass 4, count 0 2006.168.08:22:20.34#ibcon#about to read 5, iclass 4, count 0 2006.168.08:22:20.34#ibcon#read 5, iclass 4, count 0 2006.168.08:22:20.34#ibcon#about to read 6, iclass 4, count 0 2006.168.08:22:20.34#ibcon#read 6, iclass 4, count 0 2006.168.08:22:20.34#ibcon#end of sib2, iclass 4, count 0 2006.168.08:22:20.34#ibcon#*after write, iclass 4, count 0 2006.168.08:22:20.34#ibcon#*before return 0, iclass 4, count 0 2006.168.08:22:20.34#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.168.08:22:20.34#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.168.08:22:20.34#ibcon#about to clear, iclass 4 cls_cnt 0 2006.168.08:22:20.34#ibcon#cleared, iclass 4 cls_cnt 0 2006.168.08:22:20.34$vc4f8/valo=8,852.99 2006.168.08:22:20.34#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.168.08:22:20.34#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.168.08:22:20.34#ibcon#ireg 17 cls_cnt 0 2006.168.08:22:20.34#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.168.08:22:20.34#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.168.08:22:20.34#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.168.08:22:20.34#ibcon#enter wrdev, iclass 6, count 0 2006.168.08:22:20.34#ibcon#first serial, iclass 6, count 0 2006.168.08:22:20.34#ibcon#enter sib2, iclass 6, count 0 2006.168.08:22:20.34#ibcon#flushed, iclass 6, count 0 2006.168.08:22:20.34#ibcon#about to write, iclass 6, count 0 2006.168.08:22:20.34#ibcon#wrote, iclass 6, count 0 2006.168.08:22:20.34#ibcon#about to read 3, iclass 6, count 0 2006.168.08:22:20.36#ibcon#read 3, iclass 6, count 0 2006.168.08:22:20.36#ibcon#about to read 4, iclass 6, count 0 2006.168.08:22:20.36#ibcon#read 4, iclass 6, count 0 2006.168.08:22:20.36#ibcon#about to read 5, iclass 6, count 0 2006.168.08:22:20.36#ibcon#read 5, iclass 6, count 0 2006.168.08:22:20.36#ibcon#about to read 6, iclass 6, count 0 2006.168.08:22:20.36#ibcon#read 6, iclass 6, count 0 2006.168.08:22:20.36#ibcon#end of sib2, iclass 6, count 0 2006.168.08:22:20.36#ibcon#*mode == 0, iclass 6, count 0 2006.168.08:22:20.36#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.168.08:22:20.36#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.08:22:20.36#ibcon#*before write, iclass 6, count 0 2006.168.08:22:20.36#ibcon#enter sib2, iclass 6, count 0 2006.168.08:22:20.36#ibcon#flushed, iclass 6, count 0 2006.168.08:22:20.36#ibcon#about to write, iclass 6, count 0 2006.168.08:22:20.36#ibcon#wrote, iclass 6, count 0 2006.168.08:22:20.36#ibcon#about to read 3, iclass 6, count 0 2006.168.08:22:20.40#ibcon#read 3, iclass 6, count 0 2006.168.08:22:20.40#ibcon#about to read 4, iclass 6, count 0 2006.168.08:22:20.40#ibcon#read 4, iclass 6, count 0 2006.168.08:22:20.40#ibcon#about to read 5, iclass 6, count 0 2006.168.08:22:20.40#ibcon#read 5, iclass 6, count 0 2006.168.08:22:20.40#ibcon#about to read 6, iclass 6, count 0 2006.168.08:22:20.40#ibcon#read 6, iclass 6, count 0 2006.168.08:22:20.40#ibcon#end of sib2, iclass 6, count 0 2006.168.08:22:20.40#ibcon#*after write, iclass 6, count 0 2006.168.08:22:20.40#ibcon#*before return 0, iclass 6, count 0 2006.168.08:22:20.40#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.168.08:22:20.40#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.168.08:22:20.40#ibcon#about to clear, iclass 6 cls_cnt 0 2006.168.08:22:20.40#ibcon#cleared, iclass 6 cls_cnt 0 2006.168.08:22:20.40$vc4f8/va=8,7 2006.168.08:22:20.40#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.168.08:22:20.40#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.168.08:22:20.40#ibcon#ireg 11 cls_cnt 2 2006.168.08:22:20.40#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.168.08:22:20.46#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.168.08:22:20.46#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.168.08:22:20.46#ibcon#enter wrdev, iclass 10, count 2 2006.168.08:22:20.46#ibcon#first serial, iclass 10, count 2 2006.168.08:22:20.46#ibcon#enter sib2, iclass 10, count 2 2006.168.08:22:20.46#ibcon#flushed, iclass 10, count 2 2006.168.08:22:20.46#ibcon#about to write, iclass 10, count 2 2006.168.08:22:20.46#ibcon#wrote, iclass 10, count 2 2006.168.08:22:20.46#ibcon#about to read 3, iclass 10, count 2 2006.168.08:22:20.48#ibcon#read 3, iclass 10, count 2 2006.168.08:22:20.48#ibcon#about to read 4, iclass 10, count 2 2006.168.08:22:20.48#ibcon#read 4, iclass 10, count 2 2006.168.08:22:20.48#ibcon#about to read 5, iclass 10, count 2 2006.168.08:22:20.48#ibcon#read 5, iclass 10, count 2 2006.168.08:22:20.48#ibcon#about to read 6, iclass 10, count 2 2006.168.08:22:20.48#ibcon#read 6, iclass 10, count 2 2006.168.08:22:20.48#ibcon#end of sib2, iclass 10, count 2 2006.168.08:22:20.48#ibcon#*mode == 0, iclass 10, count 2 2006.168.08:22:20.48#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.168.08:22:20.48#ibcon#[25=AT08-07\r\n] 2006.168.08:22:20.48#ibcon#*before write, iclass 10, count 2 2006.168.08:22:20.48#ibcon#enter sib2, iclass 10, count 2 2006.168.08:22:20.48#ibcon#flushed, iclass 10, count 2 2006.168.08:22:20.48#ibcon#about to write, iclass 10, count 2 2006.168.08:22:20.48#ibcon#wrote, iclass 10, count 2 2006.168.08:22:20.48#ibcon#about to read 3, iclass 10, count 2 2006.168.08:22:20.51#ibcon#read 3, iclass 10, count 2 2006.168.08:22:20.51#ibcon#about to read 4, iclass 10, count 2 2006.168.08:22:20.51#ibcon#read 4, iclass 10, count 2 2006.168.08:22:20.51#ibcon#about to read 5, iclass 10, count 2 2006.168.08:22:20.51#ibcon#read 5, iclass 10, count 2 2006.168.08:22:20.51#ibcon#about to read 6, iclass 10, count 2 2006.168.08:22:20.51#ibcon#read 6, iclass 10, count 2 2006.168.08:22:20.51#ibcon#end of sib2, iclass 10, count 2 2006.168.08:22:20.51#ibcon#*after write, iclass 10, count 2 2006.168.08:22:20.51#ibcon#*before return 0, iclass 10, count 2 2006.168.08:22:20.51#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.168.08:22:20.51#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.168.08:22:20.51#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.168.08:22:20.51#ibcon#ireg 7 cls_cnt 0 2006.168.08:22:20.51#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.168.08:22:20.63#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.168.08:22:20.63#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.168.08:22:20.63#ibcon#enter wrdev, iclass 10, count 0 2006.168.08:22:20.63#ibcon#first serial, iclass 10, count 0 2006.168.08:22:20.63#ibcon#enter sib2, iclass 10, count 0 2006.168.08:22:20.63#ibcon#flushed, iclass 10, count 0 2006.168.08:22:20.63#ibcon#about to write, iclass 10, count 0 2006.168.08:22:20.63#ibcon#wrote, iclass 10, count 0 2006.168.08:22:20.63#ibcon#about to read 3, iclass 10, count 0 2006.168.08:22:20.65#ibcon#read 3, iclass 10, count 0 2006.168.08:22:20.65#ibcon#about to read 4, iclass 10, count 0 2006.168.08:22:20.65#ibcon#read 4, iclass 10, count 0 2006.168.08:22:20.65#ibcon#about to read 5, iclass 10, count 0 2006.168.08:22:20.65#ibcon#read 5, iclass 10, count 0 2006.168.08:22:20.65#ibcon#about to read 6, iclass 10, count 0 2006.168.08:22:20.65#ibcon#read 6, iclass 10, count 0 2006.168.08:22:20.65#ibcon#end of sib2, iclass 10, count 0 2006.168.08:22:20.65#ibcon#*mode == 0, iclass 10, count 0 2006.168.08:22:20.65#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.168.08:22:20.65#ibcon#[25=USB\r\n] 2006.168.08:22:20.65#ibcon#*before write, iclass 10, count 0 2006.168.08:22:20.65#ibcon#enter sib2, iclass 10, count 0 2006.168.08:22:20.65#ibcon#flushed, iclass 10, count 0 2006.168.08:22:20.65#ibcon#about to write, iclass 10, count 0 2006.168.08:22:20.65#ibcon#wrote, iclass 10, count 0 2006.168.08:22:20.65#ibcon#about to read 3, iclass 10, count 0 2006.168.08:22:20.68#ibcon#read 3, iclass 10, count 0 2006.168.08:22:20.68#ibcon#about to read 4, iclass 10, count 0 2006.168.08:22:20.68#ibcon#read 4, iclass 10, count 0 2006.168.08:22:20.68#ibcon#about to read 5, iclass 10, count 0 2006.168.08:22:20.68#ibcon#read 5, iclass 10, count 0 2006.168.08:22:20.68#ibcon#about to read 6, iclass 10, count 0 2006.168.08:22:20.68#ibcon#read 6, iclass 10, count 0 2006.168.08:22:20.68#ibcon#end of sib2, iclass 10, count 0 2006.168.08:22:20.68#ibcon#*after write, iclass 10, count 0 2006.168.08:22:20.68#ibcon#*before return 0, iclass 10, count 0 2006.168.08:22:20.68#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.168.08:22:20.68#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.168.08:22:20.68#ibcon#about to clear, iclass 10 cls_cnt 0 2006.168.08:22:20.68#ibcon#cleared, iclass 10 cls_cnt 0 2006.168.08:22:20.68$vc4f8/vblo=1,632.99 2006.168.08:22:20.68#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.168.08:22:20.68#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.168.08:22:20.68#ibcon#ireg 17 cls_cnt 0 2006.168.08:22:20.68#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.168.08:22:20.68#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.168.08:22:20.68#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.168.08:22:20.68#ibcon#enter wrdev, iclass 12, count 0 2006.168.08:22:20.68#ibcon#first serial, iclass 12, count 0 2006.168.08:22:20.68#ibcon#enter sib2, iclass 12, count 0 2006.168.08:22:20.68#ibcon#flushed, iclass 12, count 0 2006.168.08:22:20.68#ibcon#about to write, iclass 12, count 0 2006.168.08:22:20.68#ibcon#wrote, iclass 12, count 0 2006.168.08:22:20.68#ibcon#about to read 3, iclass 12, count 0 2006.168.08:22:20.70#ibcon#read 3, iclass 12, count 0 2006.168.08:22:20.70#ibcon#about to read 4, iclass 12, count 0 2006.168.08:22:20.70#ibcon#read 4, iclass 12, count 0 2006.168.08:22:20.70#ibcon#about to read 5, iclass 12, count 0 2006.168.08:22:20.70#ibcon#read 5, iclass 12, count 0 2006.168.08:22:20.70#ibcon#about to read 6, iclass 12, count 0 2006.168.08:22:20.70#ibcon#read 6, iclass 12, count 0 2006.168.08:22:20.70#ibcon#end of sib2, iclass 12, count 0 2006.168.08:22:20.70#ibcon#*mode == 0, iclass 12, count 0 2006.168.08:22:20.70#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.168.08:22:20.70#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.08:22:20.70#ibcon#*before write, iclass 12, count 0 2006.168.08:22:20.70#ibcon#enter sib2, iclass 12, count 0 2006.168.08:22:20.70#ibcon#flushed, iclass 12, count 0 2006.168.08:22:20.70#ibcon#about to write, iclass 12, count 0 2006.168.08:22:20.70#ibcon#wrote, iclass 12, count 0 2006.168.08:22:20.70#ibcon#about to read 3, iclass 12, count 0 2006.168.08:22:20.74#ibcon#read 3, iclass 12, count 0 2006.168.08:22:20.74#ibcon#about to read 4, iclass 12, count 0 2006.168.08:22:20.74#ibcon#read 4, iclass 12, count 0 2006.168.08:22:20.74#ibcon#about to read 5, iclass 12, count 0 2006.168.08:22:20.74#ibcon#read 5, iclass 12, count 0 2006.168.08:22:20.74#ibcon#about to read 6, iclass 12, count 0 2006.168.08:22:20.74#ibcon#read 6, iclass 12, count 0 2006.168.08:22:20.74#ibcon#end of sib2, iclass 12, count 0 2006.168.08:22:20.74#ibcon#*after write, iclass 12, count 0 2006.168.08:22:20.74#ibcon#*before return 0, iclass 12, count 0 2006.168.08:22:20.74#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.168.08:22:20.74#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.168.08:22:20.74#ibcon#about to clear, iclass 12 cls_cnt 0 2006.168.08:22:20.74#ibcon#cleared, iclass 12 cls_cnt 0 2006.168.08:22:20.74$vc4f8/vb=1,4 2006.168.08:22:20.74#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.168.08:22:20.74#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.168.08:22:20.74#ibcon#ireg 11 cls_cnt 2 2006.168.08:22:20.74#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.168.08:22:20.74#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.168.08:22:20.74#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.168.08:22:20.74#ibcon#enter wrdev, iclass 14, count 2 2006.168.08:22:20.74#ibcon#first serial, iclass 14, count 2 2006.168.08:22:20.74#ibcon#enter sib2, iclass 14, count 2 2006.168.08:22:20.74#ibcon#flushed, iclass 14, count 2 2006.168.08:22:20.74#ibcon#about to write, iclass 14, count 2 2006.168.08:22:20.74#ibcon#wrote, iclass 14, count 2 2006.168.08:22:20.74#ibcon#about to read 3, iclass 14, count 2 2006.168.08:22:20.76#ibcon#read 3, iclass 14, count 2 2006.168.08:22:20.76#ibcon#about to read 4, iclass 14, count 2 2006.168.08:22:20.76#ibcon#read 4, iclass 14, count 2 2006.168.08:22:20.76#ibcon#about to read 5, iclass 14, count 2 2006.168.08:22:20.76#ibcon#read 5, iclass 14, count 2 2006.168.08:22:20.76#ibcon#about to read 6, iclass 14, count 2 2006.168.08:22:20.76#ibcon#read 6, iclass 14, count 2 2006.168.08:22:20.76#ibcon#end of sib2, iclass 14, count 2 2006.168.08:22:20.76#ibcon#*mode == 0, iclass 14, count 2 2006.168.08:22:20.76#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.168.08:22:20.76#ibcon#[27=AT01-04\r\n] 2006.168.08:22:20.76#ibcon#*before write, iclass 14, count 2 2006.168.08:22:20.76#ibcon#enter sib2, iclass 14, count 2 2006.168.08:22:20.76#ibcon#flushed, iclass 14, count 2 2006.168.08:22:20.76#ibcon#about to write, iclass 14, count 2 2006.168.08:22:20.76#ibcon#wrote, iclass 14, count 2 2006.168.08:22:20.76#ibcon#about to read 3, iclass 14, count 2 2006.168.08:22:20.79#ibcon#read 3, iclass 14, count 2 2006.168.08:22:20.79#ibcon#about to read 4, iclass 14, count 2 2006.168.08:22:20.79#ibcon#read 4, iclass 14, count 2 2006.168.08:22:20.79#ibcon#about to read 5, iclass 14, count 2 2006.168.08:22:20.79#ibcon#read 5, iclass 14, count 2 2006.168.08:22:20.79#ibcon#about to read 6, iclass 14, count 2 2006.168.08:22:20.79#ibcon#read 6, iclass 14, count 2 2006.168.08:22:20.79#ibcon#end of sib2, iclass 14, count 2 2006.168.08:22:20.79#ibcon#*after write, iclass 14, count 2 2006.168.08:22:20.79#ibcon#*before return 0, iclass 14, count 2 2006.168.08:22:20.79#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.168.08:22:20.79#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.168.08:22:20.79#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.168.08:22:20.79#ibcon#ireg 7 cls_cnt 0 2006.168.08:22:20.79#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.168.08:22:20.91#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.168.08:22:20.91#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.168.08:22:20.91#ibcon#enter wrdev, iclass 14, count 0 2006.168.08:22:20.91#ibcon#first serial, iclass 14, count 0 2006.168.08:22:20.91#ibcon#enter sib2, iclass 14, count 0 2006.168.08:22:20.91#ibcon#flushed, iclass 14, count 0 2006.168.08:22:20.91#ibcon#about to write, iclass 14, count 0 2006.168.08:22:20.91#ibcon#wrote, iclass 14, count 0 2006.168.08:22:20.91#ibcon#about to read 3, iclass 14, count 0 2006.168.08:22:20.93#ibcon#read 3, iclass 14, count 0 2006.168.08:22:20.93#ibcon#about to read 4, iclass 14, count 0 2006.168.08:22:20.93#ibcon#read 4, iclass 14, count 0 2006.168.08:22:20.93#ibcon#about to read 5, iclass 14, count 0 2006.168.08:22:20.93#ibcon#read 5, iclass 14, count 0 2006.168.08:22:20.93#ibcon#about to read 6, iclass 14, count 0 2006.168.08:22:20.93#ibcon#read 6, iclass 14, count 0 2006.168.08:22:20.93#ibcon#end of sib2, iclass 14, count 0 2006.168.08:22:20.93#ibcon#*mode == 0, iclass 14, count 0 2006.168.08:22:20.93#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.168.08:22:20.93#ibcon#[27=USB\r\n] 2006.168.08:22:20.93#ibcon#*before write, iclass 14, count 0 2006.168.08:22:20.93#ibcon#enter sib2, iclass 14, count 0 2006.168.08:22:20.93#ibcon#flushed, iclass 14, count 0 2006.168.08:22:20.93#ibcon#about to write, iclass 14, count 0 2006.168.08:22:20.93#ibcon#wrote, iclass 14, count 0 2006.168.08:22:20.93#ibcon#about to read 3, iclass 14, count 0 2006.168.08:22:20.96#ibcon#read 3, iclass 14, count 0 2006.168.08:22:20.96#ibcon#about to read 4, iclass 14, count 0 2006.168.08:22:20.96#ibcon#read 4, iclass 14, count 0 2006.168.08:22:20.96#ibcon#about to read 5, iclass 14, count 0 2006.168.08:22:20.96#ibcon#read 5, iclass 14, count 0 2006.168.08:22:20.96#ibcon#about to read 6, iclass 14, count 0 2006.168.08:22:20.96#ibcon#read 6, iclass 14, count 0 2006.168.08:22:20.96#ibcon#end of sib2, iclass 14, count 0 2006.168.08:22:20.96#ibcon#*after write, iclass 14, count 0 2006.168.08:22:20.96#ibcon#*before return 0, iclass 14, count 0 2006.168.08:22:20.96#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.168.08:22:20.96#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.168.08:22:20.96#ibcon#about to clear, iclass 14 cls_cnt 0 2006.168.08:22:20.96#ibcon#cleared, iclass 14 cls_cnt 0 2006.168.08:22:20.96$vc4f8/vblo=2,640.99 2006.168.08:22:20.96#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.168.08:22:20.96#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.168.08:22:20.96#ibcon#ireg 17 cls_cnt 0 2006.168.08:22:20.96#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.168.08:22:20.96#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.168.08:22:20.96#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.168.08:22:20.96#ibcon#enter wrdev, iclass 16, count 0 2006.168.08:22:20.96#ibcon#first serial, iclass 16, count 0 2006.168.08:22:20.96#ibcon#enter sib2, iclass 16, count 0 2006.168.08:22:20.96#ibcon#flushed, iclass 16, count 0 2006.168.08:22:20.96#ibcon#about to write, iclass 16, count 0 2006.168.08:22:20.96#ibcon#wrote, iclass 16, count 0 2006.168.08:22:20.96#ibcon#about to read 3, iclass 16, count 0 2006.168.08:22:20.98#ibcon#read 3, iclass 16, count 0 2006.168.08:22:20.98#ibcon#about to read 4, iclass 16, count 0 2006.168.08:22:20.98#ibcon#read 4, iclass 16, count 0 2006.168.08:22:20.98#ibcon#about to read 5, iclass 16, count 0 2006.168.08:22:20.98#ibcon#read 5, iclass 16, count 0 2006.168.08:22:20.98#ibcon#about to read 6, iclass 16, count 0 2006.168.08:22:20.98#ibcon#read 6, iclass 16, count 0 2006.168.08:22:20.98#ibcon#end of sib2, iclass 16, count 0 2006.168.08:22:20.98#ibcon#*mode == 0, iclass 16, count 0 2006.168.08:22:20.98#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.168.08:22:20.98#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.08:22:20.98#ibcon#*before write, iclass 16, count 0 2006.168.08:22:20.98#ibcon#enter sib2, iclass 16, count 0 2006.168.08:22:20.98#ibcon#flushed, iclass 16, count 0 2006.168.08:22:20.98#ibcon#about to write, iclass 16, count 0 2006.168.08:22:20.98#ibcon#wrote, iclass 16, count 0 2006.168.08:22:20.98#ibcon#about to read 3, iclass 16, count 0 2006.168.08:22:21.02#ibcon#read 3, iclass 16, count 0 2006.168.08:22:21.02#ibcon#about to read 4, iclass 16, count 0 2006.168.08:22:21.02#ibcon#read 4, iclass 16, count 0 2006.168.08:22:21.02#ibcon#about to read 5, iclass 16, count 0 2006.168.08:22:21.02#ibcon#read 5, iclass 16, count 0 2006.168.08:22:21.02#ibcon#about to read 6, iclass 16, count 0 2006.168.08:22:21.02#ibcon#read 6, iclass 16, count 0 2006.168.08:22:21.02#ibcon#end of sib2, iclass 16, count 0 2006.168.08:22:21.02#ibcon#*after write, iclass 16, count 0 2006.168.08:22:21.02#ibcon#*before return 0, iclass 16, count 0 2006.168.08:22:21.02#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.168.08:22:21.02#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.168.08:22:21.02#ibcon#about to clear, iclass 16 cls_cnt 0 2006.168.08:22:21.02#ibcon#cleared, iclass 16 cls_cnt 0 2006.168.08:22:21.02$vc4f8/vb=2,4 2006.168.08:22:21.02#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.168.08:22:21.02#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.168.08:22:21.02#ibcon#ireg 11 cls_cnt 2 2006.168.08:22:21.02#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.168.08:22:21.08#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.168.08:22:21.08#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.168.08:22:21.08#ibcon#enter wrdev, iclass 18, count 2 2006.168.08:22:21.08#ibcon#first serial, iclass 18, count 2 2006.168.08:22:21.08#ibcon#enter sib2, iclass 18, count 2 2006.168.08:22:21.08#ibcon#flushed, iclass 18, count 2 2006.168.08:22:21.08#ibcon#about to write, iclass 18, count 2 2006.168.08:22:21.08#ibcon#wrote, iclass 18, count 2 2006.168.08:22:21.08#ibcon#about to read 3, iclass 18, count 2 2006.168.08:22:21.10#ibcon#read 3, iclass 18, count 2 2006.168.08:22:21.10#ibcon#about to read 4, iclass 18, count 2 2006.168.08:22:21.10#ibcon#read 4, iclass 18, count 2 2006.168.08:22:21.10#ibcon#about to read 5, iclass 18, count 2 2006.168.08:22:21.10#ibcon#read 5, iclass 18, count 2 2006.168.08:22:21.10#ibcon#about to read 6, iclass 18, count 2 2006.168.08:22:21.10#ibcon#read 6, iclass 18, count 2 2006.168.08:22:21.10#ibcon#end of sib2, iclass 18, count 2 2006.168.08:22:21.10#ibcon#*mode == 0, iclass 18, count 2 2006.168.08:22:21.10#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.168.08:22:21.10#ibcon#[27=AT02-04\r\n] 2006.168.08:22:21.10#ibcon#*before write, iclass 18, count 2 2006.168.08:22:21.10#ibcon#enter sib2, iclass 18, count 2 2006.168.08:22:21.10#ibcon#flushed, iclass 18, count 2 2006.168.08:22:21.10#ibcon#about to write, iclass 18, count 2 2006.168.08:22:21.10#ibcon#wrote, iclass 18, count 2 2006.168.08:22:21.10#ibcon#about to read 3, iclass 18, count 2 2006.168.08:22:21.13#ibcon#read 3, iclass 18, count 2 2006.168.08:22:21.13#ibcon#about to read 4, iclass 18, count 2 2006.168.08:22:21.13#ibcon#read 4, iclass 18, count 2 2006.168.08:22:21.13#ibcon#about to read 5, iclass 18, count 2 2006.168.08:22:21.13#ibcon#read 5, iclass 18, count 2 2006.168.08:22:21.13#ibcon#about to read 6, iclass 18, count 2 2006.168.08:22:21.13#ibcon#read 6, iclass 18, count 2 2006.168.08:22:21.13#ibcon#end of sib2, iclass 18, count 2 2006.168.08:22:21.13#ibcon#*after write, iclass 18, count 2 2006.168.08:22:21.13#ibcon#*before return 0, iclass 18, count 2 2006.168.08:22:21.13#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.168.08:22:21.13#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.168.08:22:21.13#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.168.08:22:21.13#ibcon#ireg 7 cls_cnt 0 2006.168.08:22:21.13#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.168.08:22:21.25#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.168.08:22:21.25#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.168.08:22:21.25#ibcon#enter wrdev, iclass 18, count 0 2006.168.08:22:21.25#ibcon#first serial, iclass 18, count 0 2006.168.08:22:21.25#ibcon#enter sib2, iclass 18, count 0 2006.168.08:22:21.25#ibcon#flushed, iclass 18, count 0 2006.168.08:22:21.25#ibcon#about to write, iclass 18, count 0 2006.168.08:22:21.25#ibcon#wrote, iclass 18, count 0 2006.168.08:22:21.25#ibcon#about to read 3, iclass 18, count 0 2006.168.08:22:21.27#ibcon#read 3, iclass 18, count 0 2006.168.08:22:21.27#ibcon#about to read 4, iclass 18, count 0 2006.168.08:22:21.27#ibcon#read 4, iclass 18, count 0 2006.168.08:22:21.27#ibcon#about to read 5, iclass 18, count 0 2006.168.08:22:21.27#ibcon#read 5, iclass 18, count 0 2006.168.08:22:21.27#ibcon#about to read 6, iclass 18, count 0 2006.168.08:22:21.27#ibcon#read 6, iclass 18, count 0 2006.168.08:22:21.27#ibcon#end of sib2, iclass 18, count 0 2006.168.08:22:21.27#ibcon#*mode == 0, iclass 18, count 0 2006.168.08:22:21.27#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.08:22:21.27#ibcon#[27=USB\r\n] 2006.168.08:22:21.27#ibcon#*before write, iclass 18, count 0 2006.168.08:22:21.27#ibcon#enter sib2, iclass 18, count 0 2006.168.08:22:21.27#ibcon#flushed, iclass 18, count 0 2006.168.08:22:21.27#ibcon#about to write, iclass 18, count 0 2006.168.08:22:21.27#ibcon#wrote, iclass 18, count 0 2006.168.08:22:21.27#ibcon#about to read 3, iclass 18, count 0 2006.168.08:22:21.30#ibcon#read 3, iclass 18, count 0 2006.168.08:22:21.30#ibcon#about to read 4, iclass 18, count 0 2006.168.08:22:21.30#ibcon#read 4, iclass 18, count 0 2006.168.08:22:21.30#ibcon#about to read 5, iclass 18, count 0 2006.168.08:22:21.30#ibcon#read 5, iclass 18, count 0 2006.168.08:22:21.30#ibcon#about to read 6, iclass 18, count 0 2006.168.08:22:21.30#ibcon#read 6, iclass 18, count 0 2006.168.08:22:21.30#ibcon#end of sib2, iclass 18, count 0 2006.168.08:22:21.30#ibcon#*after write, iclass 18, count 0 2006.168.08:22:21.30#ibcon#*before return 0, iclass 18, count 0 2006.168.08:22:21.30#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.168.08:22:21.30#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.168.08:22:21.30#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.08:22:21.30#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.08:22:21.30$vc4f8/vblo=3,656.99 2006.168.08:22:21.30#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.168.08:22:21.30#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.168.08:22:21.30#ibcon#ireg 17 cls_cnt 0 2006.168.08:22:21.30#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:22:21.30#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:22:21.30#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:22:21.30#ibcon#enter wrdev, iclass 20, count 0 2006.168.08:22:21.30#ibcon#first serial, iclass 20, count 0 2006.168.08:22:21.30#ibcon#enter sib2, iclass 20, count 0 2006.168.08:22:21.30#ibcon#flushed, iclass 20, count 0 2006.168.08:22:21.30#ibcon#about to write, iclass 20, count 0 2006.168.08:22:21.30#ibcon#wrote, iclass 20, count 0 2006.168.08:22:21.30#ibcon#about to read 3, iclass 20, count 0 2006.168.08:22:21.32#ibcon#read 3, iclass 20, count 0 2006.168.08:22:21.32#ibcon#about to read 4, iclass 20, count 0 2006.168.08:22:21.32#ibcon#read 4, iclass 20, count 0 2006.168.08:22:21.32#ibcon#about to read 5, iclass 20, count 0 2006.168.08:22:21.32#ibcon#read 5, iclass 20, count 0 2006.168.08:22:21.32#ibcon#about to read 6, iclass 20, count 0 2006.168.08:22:21.32#ibcon#read 6, iclass 20, count 0 2006.168.08:22:21.32#ibcon#end of sib2, iclass 20, count 0 2006.168.08:22:21.32#ibcon#*mode == 0, iclass 20, count 0 2006.168.08:22:21.32#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.168.08:22:21.32#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.08:22:21.32#ibcon#*before write, iclass 20, count 0 2006.168.08:22:21.32#ibcon#enter sib2, iclass 20, count 0 2006.168.08:22:21.32#ibcon#flushed, iclass 20, count 0 2006.168.08:22:21.32#ibcon#about to write, iclass 20, count 0 2006.168.08:22:21.32#ibcon#wrote, iclass 20, count 0 2006.168.08:22:21.32#ibcon#about to read 3, iclass 20, count 0 2006.168.08:22:21.36#ibcon#read 3, iclass 20, count 0 2006.168.08:22:21.36#ibcon#about to read 4, iclass 20, count 0 2006.168.08:22:21.36#ibcon#read 4, iclass 20, count 0 2006.168.08:22:21.36#ibcon#about to read 5, iclass 20, count 0 2006.168.08:22:21.36#ibcon#read 5, iclass 20, count 0 2006.168.08:22:21.36#ibcon#about to read 6, iclass 20, count 0 2006.168.08:22:21.36#ibcon#read 6, iclass 20, count 0 2006.168.08:22:21.36#ibcon#end of sib2, iclass 20, count 0 2006.168.08:22:21.36#ibcon#*after write, iclass 20, count 0 2006.168.08:22:21.36#ibcon#*before return 0, iclass 20, count 0 2006.168.08:22:21.36#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:22:21.36#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.168.08:22:21.36#ibcon#about to clear, iclass 20 cls_cnt 0 2006.168.08:22:21.36#ibcon#cleared, iclass 20 cls_cnt 0 2006.168.08:22:21.36$vc4f8/vb=3,4 2006.168.08:22:21.36#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.168.08:22:21.36#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.168.08:22:21.36#ibcon#ireg 11 cls_cnt 2 2006.168.08:22:21.36#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.168.08:22:21.42#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.168.08:22:21.42#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.168.08:22:21.42#ibcon#enter wrdev, iclass 22, count 2 2006.168.08:22:21.42#ibcon#first serial, iclass 22, count 2 2006.168.08:22:21.42#ibcon#enter sib2, iclass 22, count 2 2006.168.08:22:21.42#ibcon#flushed, iclass 22, count 2 2006.168.08:22:21.42#ibcon#about to write, iclass 22, count 2 2006.168.08:22:21.42#ibcon#wrote, iclass 22, count 2 2006.168.08:22:21.42#ibcon#about to read 3, iclass 22, count 2 2006.168.08:22:21.44#ibcon#read 3, iclass 22, count 2 2006.168.08:22:21.44#ibcon#about to read 4, iclass 22, count 2 2006.168.08:22:21.44#ibcon#read 4, iclass 22, count 2 2006.168.08:22:21.44#ibcon#about to read 5, iclass 22, count 2 2006.168.08:22:21.44#ibcon#read 5, iclass 22, count 2 2006.168.08:22:21.44#ibcon#about to read 6, iclass 22, count 2 2006.168.08:22:21.44#ibcon#read 6, iclass 22, count 2 2006.168.08:22:21.44#ibcon#end of sib2, iclass 22, count 2 2006.168.08:22:21.44#ibcon#*mode == 0, iclass 22, count 2 2006.168.08:22:21.44#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.168.08:22:21.44#ibcon#[27=AT03-04\r\n] 2006.168.08:22:21.44#ibcon#*before write, iclass 22, count 2 2006.168.08:22:21.44#ibcon#enter sib2, iclass 22, count 2 2006.168.08:22:21.44#ibcon#flushed, iclass 22, count 2 2006.168.08:22:21.44#ibcon#about to write, iclass 22, count 2 2006.168.08:22:21.44#ibcon#wrote, iclass 22, count 2 2006.168.08:22:21.44#ibcon#about to read 3, iclass 22, count 2 2006.168.08:22:21.45#abcon#<5=/08 1.4 3.8 26.85 751004.5\r\n> 2006.168.08:22:21.47#abcon#{5=INTERFACE CLEAR} 2006.168.08:22:21.47#ibcon#read 3, iclass 22, count 2 2006.168.08:22:21.47#ibcon#about to read 4, iclass 22, count 2 2006.168.08:22:21.47#ibcon#read 4, iclass 22, count 2 2006.168.08:22:21.47#ibcon#about to read 5, iclass 22, count 2 2006.168.08:22:21.47#ibcon#read 5, iclass 22, count 2 2006.168.08:22:21.47#ibcon#about to read 6, iclass 22, count 2 2006.168.08:22:21.47#ibcon#read 6, iclass 22, count 2 2006.168.08:22:21.47#ibcon#end of sib2, iclass 22, count 2 2006.168.08:22:21.47#ibcon#*after write, iclass 22, count 2 2006.168.08:22:21.47#ibcon#*before return 0, iclass 22, count 2 2006.168.08:22:21.47#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.168.08:22:21.47#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.168.08:22:21.47#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.168.08:22:21.47#ibcon#ireg 7 cls_cnt 0 2006.168.08:22:21.47#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.168.08:22:21.53#abcon#[5=S1D000X0/0*\r\n] 2006.168.08:22:21.59#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.168.08:22:21.59#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.168.08:22:21.59#ibcon#enter wrdev, iclass 22, count 0 2006.168.08:22:21.59#ibcon#first serial, iclass 22, count 0 2006.168.08:22:21.59#ibcon#enter sib2, iclass 22, count 0 2006.168.08:22:21.59#ibcon#flushed, iclass 22, count 0 2006.168.08:22:21.59#ibcon#about to write, iclass 22, count 0 2006.168.08:22:21.59#ibcon#wrote, iclass 22, count 0 2006.168.08:22:21.59#ibcon#about to read 3, iclass 22, count 0 2006.168.08:22:21.62#ibcon#read 3, iclass 22, count 0 2006.168.08:22:21.62#ibcon#about to read 4, iclass 22, count 0 2006.168.08:22:21.62#ibcon#read 4, iclass 22, count 0 2006.168.08:22:21.62#ibcon#about to read 5, iclass 22, count 0 2006.168.08:22:21.62#ibcon#read 5, iclass 22, count 0 2006.168.08:22:21.62#ibcon#about to read 6, iclass 22, count 0 2006.168.08:22:21.62#ibcon#read 6, iclass 22, count 0 2006.168.08:22:21.62#ibcon#end of sib2, iclass 22, count 0 2006.168.08:22:21.62#ibcon#*mode == 0, iclass 22, count 0 2006.168.08:22:21.62#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.168.08:22:21.62#ibcon#[27=USB\r\n] 2006.168.08:22:21.62#ibcon#*before write, iclass 22, count 0 2006.168.08:22:21.62#ibcon#enter sib2, iclass 22, count 0 2006.168.08:22:21.62#ibcon#flushed, iclass 22, count 0 2006.168.08:22:21.62#ibcon#about to write, iclass 22, count 0 2006.168.08:22:21.62#ibcon#wrote, iclass 22, count 0 2006.168.08:22:21.62#ibcon#about to read 3, iclass 22, count 0 2006.168.08:22:21.66#ibcon#read 3, iclass 22, count 0 2006.168.08:22:21.66#ibcon#about to read 4, iclass 22, count 0 2006.168.08:22:21.66#ibcon#read 4, iclass 22, count 0 2006.168.08:22:21.66#ibcon#about to read 5, iclass 22, count 0 2006.168.08:22:21.66#ibcon#read 5, iclass 22, count 0 2006.168.08:22:21.66#ibcon#about to read 6, iclass 22, count 0 2006.168.08:22:21.66#ibcon#read 6, iclass 22, count 0 2006.168.08:22:21.66#ibcon#end of sib2, iclass 22, count 0 2006.168.08:22:21.66#ibcon#*after write, iclass 22, count 0 2006.168.08:22:21.66#ibcon#*before return 0, iclass 22, count 0 2006.168.08:22:21.66#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.168.08:22:21.66#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.168.08:22:21.66#ibcon#about to clear, iclass 22 cls_cnt 0 2006.168.08:22:21.66#ibcon#cleared, iclass 22 cls_cnt 0 2006.168.08:22:21.66$vc4f8/vblo=4,712.99 2006.168.08:22:21.66#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.168.08:22:21.66#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.168.08:22:21.66#ibcon#ireg 17 cls_cnt 0 2006.168.08:22:21.66#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.168.08:22:21.66#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.168.08:22:21.66#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.168.08:22:21.66#ibcon#enter wrdev, iclass 28, count 0 2006.168.08:22:21.66#ibcon#first serial, iclass 28, count 0 2006.168.08:22:21.66#ibcon#enter sib2, iclass 28, count 0 2006.168.08:22:21.66#ibcon#flushed, iclass 28, count 0 2006.168.08:22:21.66#ibcon#about to write, iclass 28, count 0 2006.168.08:22:21.66#ibcon#wrote, iclass 28, count 0 2006.168.08:22:21.66#ibcon#about to read 3, iclass 28, count 0 2006.168.08:22:21.68#ibcon#read 3, iclass 28, count 0 2006.168.08:22:21.68#ibcon#about to read 4, iclass 28, count 0 2006.168.08:22:21.68#ibcon#read 4, iclass 28, count 0 2006.168.08:22:21.68#ibcon#about to read 5, iclass 28, count 0 2006.168.08:22:21.68#ibcon#read 5, iclass 28, count 0 2006.168.08:22:21.68#ibcon#about to read 6, iclass 28, count 0 2006.168.08:22:21.68#ibcon#read 6, iclass 28, count 0 2006.168.08:22:21.68#ibcon#end of sib2, iclass 28, count 0 2006.168.08:22:21.68#ibcon#*mode == 0, iclass 28, count 0 2006.168.08:22:21.68#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.168.08:22:21.68#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.08:22:21.68#ibcon#*before write, iclass 28, count 0 2006.168.08:22:21.68#ibcon#enter sib2, iclass 28, count 0 2006.168.08:22:21.68#ibcon#flushed, iclass 28, count 0 2006.168.08:22:21.68#ibcon#about to write, iclass 28, count 0 2006.168.08:22:21.68#ibcon#wrote, iclass 28, count 0 2006.168.08:22:21.68#ibcon#about to read 3, iclass 28, count 0 2006.168.08:22:21.72#ibcon#read 3, iclass 28, count 0 2006.168.08:22:21.72#ibcon#about to read 4, iclass 28, count 0 2006.168.08:22:21.72#ibcon#read 4, iclass 28, count 0 2006.168.08:22:21.72#ibcon#about to read 5, iclass 28, count 0 2006.168.08:22:21.72#ibcon#read 5, iclass 28, count 0 2006.168.08:22:21.72#ibcon#about to read 6, iclass 28, count 0 2006.168.08:22:21.72#ibcon#read 6, iclass 28, count 0 2006.168.08:22:21.72#ibcon#end of sib2, iclass 28, count 0 2006.168.08:22:21.72#ibcon#*after write, iclass 28, count 0 2006.168.08:22:21.72#ibcon#*before return 0, iclass 28, count 0 2006.168.08:22:21.72#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.168.08:22:21.72#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.168.08:22:21.72#ibcon#about to clear, iclass 28 cls_cnt 0 2006.168.08:22:21.72#ibcon#cleared, iclass 28 cls_cnt 0 2006.168.08:22:21.72$vc4f8/vb=4,4 2006.168.08:22:21.72#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.168.08:22:21.72#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.168.08:22:21.72#ibcon#ireg 11 cls_cnt 2 2006.168.08:22:21.72#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.168.08:22:21.78#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.168.08:22:21.78#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.168.08:22:21.78#ibcon#enter wrdev, iclass 30, count 2 2006.168.08:22:21.78#ibcon#first serial, iclass 30, count 2 2006.168.08:22:21.78#ibcon#enter sib2, iclass 30, count 2 2006.168.08:22:21.78#ibcon#flushed, iclass 30, count 2 2006.168.08:22:21.78#ibcon#about to write, iclass 30, count 2 2006.168.08:22:21.78#ibcon#wrote, iclass 30, count 2 2006.168.08:22:21.78#ibcon#about to read 3, iclass 30, count 2 2006.168.08:22:21.80#ibcon#read 3, iclass 30, count 2 2006.168.08:22:21.80#ibcon#about to read 4, iclass 30, count 2 2006.168.08:22:21.80#ibcon#read 4, iclass 30, count 2 2006.168.08:22:21.80#ibcon#about to read 5, iclass 30, count 2 2006.168.08:22:21.80#ibcon#read 5, iclass 30, count 2 2006.168.08:22:21.80#ibcon#about to read 6, iclass 30, count 2 2006.168.08:22:21.80#ibcon#read 6, iclass 30, count 2 2006.168.08:22:21.80#ibcon#end of sib2, iclass 30, count 2 2006.168.08:22:21.80#ibcon#*mode == 0, iclass 30, count 2 2006.168.08:22:21.80#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.168.08:22:21.80#ibcon#[27=AT04-04\r\n] 2006.168.08:22:21.80#ibcon#*before write, iclass 30, count 2 2006.168.08:22:21.80#ibcon#enter sib2, iclass 30, count 2 2006.168.08:22:21.80#ibcon#flushed, iclass 30, count 2 2006.168.08:22:21.80#ibcon#about to write, iclass 30, count 2 2006.168.08:22:21.80#ibcon#wrote, iclass 30, count 2 2006.168.08:22:21.80#ibcon#about to read 3, iclass 30, count 2 2006.168.08:22:21.83#ibcon#read 3, iclass 30, count 2 2006.168.08:22:21.83#ibcon#about to read 4, iclass 30, count 2 2006.168.08:22:21.83#ibcon#read 4, iclass 30, count 2 2006.168.08:22:21.83#ibcon#about to read 5, iclass 30, count 2 2006.168.08:22:21.83#ibcon#read 5, iclass 30, count 2 2006.168.08:22:21.83#ibcon#about to read 6, iclass 30, count 2 2006.168.08:22:21.83#ibcon#read 6, iclass 30, count 2 2006.168.08:22:21.83#ibcon#end of sib2, iclass 30, count 2 2006.168.08:22:21.83#ibcon#*after write, iclass 30, count 2 2006.168.08:22:21.83#ibcon#*before return 0, iclass 30, count 2 2006.168.08:22:21.83#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.168.08:22:21.83#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.168.08:22:21.83#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.168.08:22:21.83#ibcon#ireg 7 cls_cnt 0 2006.168.08:22:21.83#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.168.08:22:21.95#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.168.08:22:21.95#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.168.08:22:21.95#ibcon#enter wrdev, iclass 30, count 0 2006.168.08:22:21.95#ibcon#first serial, iclass 30, count 0 2006.168.08:22:21.95#ibcon#enter sib2, iclass 30, count 0 2006.168.08:22:21.95#ibcon#flushed, iclass 30, count 0 2006.168.08:22:21.95#ibcon#about to write, iclass 30, count 0 2006.168.08:22:21.95#ibcon#wrote, iclass 30, count 0 2006.168.08:22:21.95#ibcon#about to read 3, iclass 30, count 0 2006.168.08:22:21.97#ibcon#read 3, iclass 30, count 0 2006.168.08:22:21.97#ibcon#about to read 4, iclass 30, count 0 2006.168.08:22:21.97#ibcon#read 4, iclass 30, count 0 2006.168.08:22:21.97#ibcon#about to read 5, iclass 30, count 0 2006.168.08:22:21.97#ibcon#read 5, iclass 30, count 0 2006.168.08:22:21.97#ibcon#about to read 6, iclass 30, count 0 2006.168.08:22:21.97#ibcon#read 6, iclass 30, count 0 2006.168.08:22:21.97#ibcon#end of sib2, iclass 30, count 0 2006.168.08:22:21.97#ibcon#*mode == 0, iclass 30, count 0 2006.168.08:22:21.97#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.168.08:22:21.97#ibcon#[27=USB\r\n] 2006.168.08:22:21.97#ibcon#*before write, iclass 30, count 0 2006.168.08:22:21.97#ibcon#enter sib2, iclass 30, count 0 2006.168.08:22:21.97#ibcon#flushed, iclass 30, count 0 2006.168.08:22:21.97#ibcon#about to write, iclass 30, count 0 2006.168.08:22:21.97#ibcon#wrote, iclass 30, count 0 2006.168.08:22:21.97#ibcon#about to read 3, iclass 30, count 0 2006.168.08:22:22.00#ibcon#read 3, iclass 30, count 0 2006.168.08:22:22.00#ibcon#about to read 4, iclass 30, count 0 2006.168.08:22:22.00#ibcon#read 4, iclass 30, count 0 2006.168.08:22:22.00#ibcon#about to read 5, iclass 30, count 0 2006.168.08:22:22.00#ibcon#read 5, iclass 30, count 0 2006.168.08:22:22.00#ibcon#about to read 6, iclass 30, count 0 2006.168.08:22:22.00#ibcon#read 6, iclass 30, count 0 2006.168.08:22:22.00#ibcon#end of sib2, iclass 30, count 0 2006.168.08:22:22.00#ibcon#*after write, iclass 30, count 0 2006.168.08:22:22.00#ibcon#*before return 0, iclass 30, count 0 2006.168.08:22:22.00#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.168.08:22:22.00#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.168.08:22:22.00#ibcon#about to clear, iclass 30 cls_cnt 0 2006.168.08:22:22.00#ibcon#cleared, iclass 30 cls_cnt 0 2006.168.08:22:22.00$vc4f8/vblo=5,744.99 2006.168.08:22:22.00#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.168.08:22:22.00#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.168.08:22:22.00#ibcon#ireg 17 cls_cnt 0 2006.168.08:22:22.00#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:22:22.00#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:22:22.00#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:22:22.00#ibcon#enter wrdev, iclass 32, count 0 2006.168.08:22:22.00#ibcon#first serial, iclass 32, count 0 2006.168.08:22:22.00#ibcon#enter sib2, iclass 32, count 0 2006.168.08:22:22.00#ibcon#flushed, iclass 32, count 0 2006.168.08:22:22.00#ibcon#about to write, iclass 32, count 0 2006.168.08:22:22.00#ibcon#wrote, iclass 32, count 0 2006.168.08:22:22.00#ibcon#about to read 3, iclass 32, count 0 2006.168.08:22:22.02#ibcon#read 3, iclass 32, count 0 2006.168.08:22:22.02#ibcon#about to read 4, iclass 32, count 0 2006.168.08:22:22.02#ibcon#read 4, iclass 32, count 0 2006.168.08:22:22.02#ibcon#about to read 5, iclass 32, count 0 2006.168.08:22:22.02#ibcon#read 5, iclass 32, count 0 2006.168.08:22:22.02#ibcon#about to read 6, iclass 32, count 0 2006.168.08:22:22.02#ibcon#read 6, iclass 32, count 0 2006.168.08:22:22.02#ibcon#end of sib2, iclass 32, count 0 2006.168.08:22:22.02#ibcon#*mode == 0, iclass 32, count 0 2006.168.08:22:22.02#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.168.08:22:22.02#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.08:22:22.02#ibcon#*before write, iclass 32, count 0 2006.168.08:22:22.02#ibcon#enter sib2, iclass 32, count 0 2006.168.08:22:22.02#ibcon#flushed, iclass 32, count 0 2006.168.08:22:22.02#ibcon#about to write, iclass 32, count 0 2006.168.08:22:22.02#ibcon#wrote, iclass 32, count 0 2006.168.08:22:22.02#ibcon#about to read 3, iclass 32, count 0 2006.168.08:22:22.06#ibcon#read 3, iclass 32, count 0 2006.168.08:22:22.06#ibcon#about to read 4, iclass 32, count 0 2006.168.08:22:22.06#ibcon#read 4, iclass 32, count 0 2006.168.08:22:22.06#ibcon#about to read 5, iclass 32, count 0 2006.168.08:22:22.06#ibcon#read 5, iclass 32, count 0 2006.168.08:22:22.06#ibcon#about to read 6, iclass 32, count 0 2006.168.08:22:22.06#ibcon#read 6, iclass 32, count 0 2006.168.08:22:22.06#ibcon#end of sib2, iclass 32, count 0 2006.168.08:22:22.06#ibcon#*after write, iclass 32, count 0 2006.168.08:22:22.06#ibcon#*before return 0, iclass 32, count 0 2006.168.08:22:22.06#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:22:22.06#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:22:22.06#ibcon#about to clear, iclass 32 cls_cnt 0 2006.168.08:22:22.06#ibcon#cleared, iclass 32 cls_cnt 0 2006.168.08:22:22.06$vc4f8/vb=5,4 2006.168.08:22:22.06#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.168.08:22:22.06#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.168.08:22:22.06#ibcon#ireg 11 cls_cnt 2 2006.168.08:22:22.06#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.168.08:22:22.12#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.168.08:22:22.12#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.168.08:22:22.12#ibcon#enter wrdev, iclass 34, count 2 2006.168.08:22:22.12#ibcon#first serial, iclass 34, count 2 2006.168.08:22:22.12#ibcon#enter sib2, iclass 34, count 2 2006.168.08:22:22.12#ibcon#flushed, iclass 34, count 2 2006.168.08:22:22.12#ibcon#about to write, iclass 34, count 2 2006.168.08:22:22.12#ibcon#wrote, iclass 34, count 2 2006.168.08:22:22.12#ibcon#about to read 3, iclass 34, count 2 2006.168.08:22:22.14#ibcon#read 3, iclass 34, count 2 2006.168.08:22:22.14#ibcon#about to read 4, iclass 34, count 2 2006.168.08:22:22.14#ibcon#read 4, iclass 34, count 2 2006.168.08:22:22.14#ibcon#about to read 5, iclass 34, count 2 2006.168.08:22:22.14#ibcon#read 5, iclass 34, count 2 2006.168.08:22:22.14#ibcon#about to read 6, iclass 34, count 2 2006.168.08:22:22.14#ibcon#read 6, iclass 34, count 2 2006.168.08:22:22.14#ibcon#end of sib2, iclass 34, count 2 2006.168.08:22:22.14#ibcon#*mode == 0, iclass 34, count 2 2006.168.08:22:22.14#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.168.08:22:22.14#ibcon#[27=AT05-04\r\n] 2006.168.08:22:22.14#ibcon#*before write, iclass 34, count 2 2006.168.08:22:22.14#ibcon#enter sib2, iclass 34, count 2 2006.168.08:22:22.14#ibcon#flushed, iclass 34, count 2 2006.168.08:22:22.14#ibcon#about to write, iclass 34, count 2 2006.168.08:22:22.14#ibcon#wrote, iclass 34, count 2 2006.168.08:22:22.14#ibcon#about to read 3, iclass 34, count 2 2006.168.08:22:22.17#ibcon#read 3, iclass 34, count 2 2006.168.08:22:22.17#ibcon#about to read 4, iclass 34, count 2 2006.168.08:22:22.17#ibcon#read 4, iclass 34, count 2 2006.168.08:22:22.17#ibcon#about to read 5, iclass 34, count 2 2006.168.08:22:22.17#ibcon#read 5, iclass 34, count 2 2006.168.08:22:22.17#ibcon#about to read 6, iclass 34, count 2 2006.168.08:22:22.17#ibcon#read 6, iclass 34, count 2 2006.168.08:22:22.17#ibcon#end of sib2, iclass 34, count 2 2006.168.08:22:22.17#ibcon#*after write, iclass 34, count 2 2006.168.08:22:22.17#ibcon#*before return 0, iclass 34, count 2 2006.168.08:22:22.17#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.168.08:22:22.17#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.168.08:22:22.17#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.168.08:22:22.17#ibcon#ireg 7 cls_cnt 0 2006.168.08:22:22.17#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.168.08:22:22.29#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.168.08:22:22.29#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.168.08:22:22.29#ibcon#enter wrdev, iclass 34, count 0 2006.168.08:22:22.29#ibcon#first serial, iclass 34, count 0 2006.168.08:22:22.29#ibcon#enter sib2, iclass 34, count 0 2006.168.08:22:22.29#ibcon#flushed, iclass 34, count 0 2006.168.08:22:22.29#ibcon#about to write, iclass 34, count 0 2006.168.08:22:22.29#ibcon#wrote, iclass 34, count 0 2006.168.08:22:22.29#ibcon#about to read 3, iclass 34, count 0 2006.168.08:22:22.31#ibcon#read 3, iclass 34, count 0 2006.168.08:22:22.31#ibcon#about to read 4, iclass 34, count 0 2006.168.08:22:22.31#ibcon#read 4, iclass 34, count 0 2006.168.08:22:22.31#ibcon#about to read 5, iclass 34, count 0 2006.168.08:22:22.31#ibcon#read 5, iclass 34, count 0 2006.168.08:22:22.31#ibcon#about to read 6, iclass 34, count 0 2006.168.08:22:22.31#ibcon#read 6, iclass 34, count 0 2006.168.08:22:22.31#ibcon#end of sib2, iclass 34, count 0 2006.168.08:22:22.31#ibcon#*mode == 0, iclass 34, count 0 2006.168.08:22:22.31#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.168.08:22:22.31#ibcon#[27=USB\r\n] 2006.168.08:22:22.31#ibcon#*before write, iclass 34, count 0 2006.168.08:22:22.31#ibcon#enter sib2, iclass 34, count 0 2006.168.08:22:22.31#ibcon#flushed, iclass 34, count 0 2006.168.08:22:22.31#ibcon#about to write, iclass 34, count 0 2006.168.08:22:22.31#ibcon#wrote, iclass 34, count 0 2006.168.08:22:22.31#ibcon#about to read 3, iclass 34, count 0 2006.168.08:22:22.34#ibcon#read 3, iclass 34, count 0 2006.168.08:22:22.34#ibcon#about to read 4, iclass 34, count 0 2006.168.08:22:22.34#ibcon#read 4, iclass 34, count 0 2006.168.08:22:22.34#ibcon#about to read 5, iclass 34, count 0 2006.168.08:22:22.34#ibcon#read 5, iclass 34, count 0 2006.168.08:22:22.34#ibcon#about to read 6, iclass 34, count 0 2006.168.08:22:22.34#ibcon#read 6, iclass 34, count 0 2006.168.08:22:22.34#ibcon#end of sib2, iclass 34, count 0 2006.168.08:22:22.34#ibcon#*after write, iclass 34, count 0 2006.168.08:22:22.34#ibcon#*before return 0, iclass 34, count 0 2006.168.08:22:22.34#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.168.08:22:22.34#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.168.08:22:22.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.168.08:22:22.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.168.08:22:22.34$vc4f8/vblo=6,752.99 2006.168.08:22:22.34#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.168.08:22:22.34#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.168.08:22:22.34#ibcon#ireg 17 cls_cnt 0 2006.168.08:22:22.34#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.168.08:22:22.34#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.168.08:22:22.34#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.168.08:22:22.34#ibcon#enter wrdev, iclass 36, count 0 2006.168.08:22:22.34#ibcon#first serial, iclass 36, count 0 2006.168.08:22:22.34#ibcon#enter sib2, iclass 36, count 0 2006.168.08:22:22.34#ibcon#flushed, iclass 36, count 0 2006.168.08:22:22.34#ibcon#about to write, iclass 36, count 0 2006.168.08:22:22.34#ibcon#wrote, iclass 36, count 0 2006.168.08:22:22.34#ibcon#about to read 3, iclass 36, count 0 2006.168.08:22:22.36#ibcon#read 3, iclass 36, count 0 2006.168.08:22:22.36#ibcon#about to read 4, iclass 36, count 0 2006.168.08:22:22.36#ibcon#read 4, iclass 36, count 0 2006.168.08:22:22.36#ibcon#about to read 5, iclass 36, count 0 2006.168.08:22:22.36#ibcon#read 5, iclass 36, count 0 2006.168.08:22:22.36#ibcon#about to read 6, iclass 36, count 0 2006.168.08:22:22.36#ibcon#read 6, iclass 36, count 0 2006.168.08:22:22.36#ibcon#end of sib2, iclass 36, count 0 2006.168.08:22:22.36#ibcon#*mode == 0, iclass 36, count 0 2006.168.08:22:22.36#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.168.08:22:22.36#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.08:22:22.36#ibcon#*before write, iclass 36, count 0 2006.168.08:22:22.36#ibcon#enter sib2, iclass 36, count 0 2006.168.08:22:22.36#ibcon#flushed, iclass 36, count 0 2006.168.08:22:22.36#ibcon#about to write, iclass 36, count 0 2006.168.08:22:22.36#ibcon#wrote, iclass 36, count 0 2006.168.08:22:22.36#ibcon#about to read 3, iclass 36, count 0 2006.168.08:22:22.40#ibcon#read 3, iclass 36, count 0 2006.168.08:22:22.40#ibcon#about to read 4, iclass 36, count 0 2006.168.08:22:22.40#ibcon#read 4, iclass 36, count 0 2006.168.08:22:22.40#ibcon#about to read 5, iclass 36, count 0 2006.168.08:22:22.40#ibcon#read 5, iclass 36, count 0 2006.168.08:22:22.40#ibcon#about to read 6, iclass 36, count 0 2006.168.08:22:22.40#ibcon#read 6, iclass 36, count 0 2006.168.08:22:22.40#ibcon#end of sib2, iclass 36, count 0 2006.168.08:22:22.40#ibcon#*after write, iclass 36, count 0 2006.168.08:22:22.40#ibcon#*before return 0, iclass 36, count 0 2006.168.08:22:22.40#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.168.08:22:22.40#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.168.08:22:22.40#ibcon#about to clear, iclass 36 cls_cnt 0 2006.168.08:22:22.40#ibcon#cleared, iclass 36 cls_cnt 0 2006.168.08:22:22.40$vc4f8/vb=6,4 2006.168.08:22:22.40#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.168.08:22:22.40#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.168.08:22:22.40#ibcon#ireg 11 cls_cnt 2 2006.168.08:22:22.40#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.168.08:22:22.46#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.168.08:22:22.46#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.168.08:22:22.46#ibcon#enter wrdev, iclass 38, count 2 2006.168.08:22:22.46#ibcon#first serial, iclass 38, count 2 2006.168.08:22:22.46#ibcon#enter sib2, iclass 38, count 2 2006.168.08:22:22.46#ibcon#flushed, iclass 38, count 2 2006.168.08:22:22.46#ibcon#about to write, iclass 38, count 2 2006.168.08:22:22.46#ibcon#wrote, iclass 38, count 2 2006.168.08:22:22.46#ibcon#about to read 3, iclass 38, count 2 2006.168.08:22:22.48#ibcon#read 3, iclass 38, count 2 2006.168.08:22:22.48#ibcon#about to read 4, iclass 38, count 2 2006.168.08:22:22.48#ibcon#read 4, iclass 38, count 2 2006.168.08:22:22.48#ibcon#about to read 5, iclass 38, count 2 2006.168.08:22:22.48#ibcon#read 5, iclass 38, count 2 2006.168.08:22:22.48#ibcon#about to read 6, iclass 38, count 2 2006.168.08:22:22.48#ibcon#read 6, iclass 38, count 2 2006.168.08:22:22.48#ibcon#end of sib2, iclass 38, count 2 2006.168.08:22:22.48#ibcon#*mode == 0, iclass 38, count 2 2006.168.08:22:22.48#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.168.08:22:22.48#ibcon#[27=AT06-04\r\n] 2006.168.08:22:22.48#ibcon#*before write, iclass 38, count 2 2006.168.08:22:22.48#ibcon#enter sib2, iclass 38, count 2 2006.168.08:22:22.48#ibcon#flushed, iclass 38, count 2 2006.168.08:22:22.48#ibcon#about to write, iclass 38, count 2 2006.168.08:22:22.48#ibcon#wrote, iclass 38, count 2 2006.168.08:22:22.48#ibcon#about to read 3, iclass 38, count 2 2006.168.08:22:22.51#ibcon#read 3, iclass 38, count 2 2006.168.08:22:22.51#ibcon#about to read 4, iclass 38, count 2 2006.168.08:22:22.51#ibcon#read 4, iclass 38, count 2 2006.168.08:22:22.51#ibcon#about to read 5, iclass 38, count 2 2006.168.08:22:22.51#ibcon#read 5, iclass 38, count 2 2006.168.08:22:22.51#ibcon#about to read 6, iclass 38, count 2 2006.168.08:22:22.51#ibcon#read 6, iclass 38, count 2 2006.168.08:22:22.51#ibcon#end of sib2, iclass 38, count 2 2006.168.08:22:22.51#ibcon#*after write, iclass 38, count 2 2006.168.08:22:22.51#ibcon#*before return 0, iclass 38, count 2 2006.168.08:22:22.51#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.168.08:22:22.51#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.168.08:22:22.51#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.168.08:22:22.51#ibcon#ireg 7 cls_cnt 0 2006.168.08:22:22.51#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.168.08:22:22.63#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.168.08:22:22.63#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.168.08:22:22.63#ibcon#enter wrdev, iclass 38, count 0 2006.168.08:22:22.63#ibcon#first serial, iclass 38, count 0 2006.168.08:22:22.63#ibcon#enter sib2, iclass 38, count 0 2006.168.08:22:22.63#ibcon#flushed, iclass 38, count 0 2006.168.08:22:22.63#ibcon#about to write, iclass 38, count 0 2006.168.08:22:22.63#ibcon#wrote, iclass 38, count 0 2006.168.08:22:22.63#ibcon#about to read 3, iclass 38, count 0 2006.168.08:22:22.65#ibcon#read 3, iclass 38, count 0 2006.168.08:22:22.65#ibcon#about to read 4, iclass 38, count 0 2006.168.08:22:22.65#ibcon#read 4, iclass 38, count 0 2006.168.08:22:22.65#ibcon#about to read 5, iclass 38, count 0 2006.168.08:22:22.65#ibcon#read 5, iclass 38, count 0 2006.168.08:22:22.65#ibcon#about to read 6, iclass 38, count 0 2006.168.08:22:22.65#ibcon#read 6, iclass 38, count 0 2006.168.08:22:22.65#ibcon#end of sib2, iclass 38, count 0 2006.168.08:22:22.65#ibcon#*mode == 0, iclass 38, count 0 2006.168.08:22:22.65#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.168.08:22:22.65#ibcon#[27=USB\r\n] 2006.168.08:22:22.65#ibcon#*before write, iclass 38, count 0 2006.168.08:22:22.65#ibcon#enter sib2, iclass 38, count 0 2006.168.08:22:22.65#ibcon#flushed, iclass 38, count 0 2006.168.08:22:22.65#ibcon#about to write, iclass 38, count 0 2006.168.08:22:22.65#ibcon#wrote, iclass 38, count 0 2006.168.08:22:22.65#ibcon#about to read 3, iclass 38, count 0 2006.168.08:22:22.68#ibcon#read 3, iclass 38, count 0 2006.168.08:22:22.68#ibcon#about to read 4, iclass 38, count 0 2006.168.08:22:22.68#ibcon#read 4, iclass 38, count 0 2006.168.08:22:22.68#ibcon#about to read 5, iclass 38, count 0 2006.168.08:22:22.68#ibcon#read 5, iclass 38, count 0 2006.168.08:22:22.68#ibcon#about to read 6, iclass 38, count 0 2006.168.08:22:22.68#ibcon#read 6, iclass 38, count 0 2006.168.08:22:22.68#ibcon#end of sib2, iclass 38, count 0 2006.168.08:22:22.68#ibcon#*after write, iclass 38, count 0 2006.168.08:22:22.68#ibcon#*before return 0, iclass 38, count 0 2006.168.08:22:22.68#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.168.08:22:22.68#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.168.08:22:22.68#ibcon#about to clear, iclass 38 cls_cnt 0 2006.168.08:22:22.68#ibcon#cleared, iclass 38 cls_cnt 0 2006.168.08:22:22.68$vc4f8/vabw=wide 2006.168.08:22:22.68#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.168.08:22:22.68#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.168.08:22:22.68#ibcon#ireg 8 cls_cnt 0 2006.168.08:22:22.68#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:22:22.68#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:22:22.68#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:22:22.68#ibcon#enter wrdev, iclass 40, count 0 2006.168.08:22:22.68#ibcon#first serial, iclass 40, count 0 2006.168.08:22:22.68#ibcon#enter sib2, iclass 40, count 0 2006.168.08:22:22.68#ibcon#flushed, iclass 40, count 0 2006.168.08:22:22.68#ibcon#about to write, iclass 40, count 0 2006.168.08:22:22.68#ibcon#wrote, iclass 40, count 0 2006.168.08:22:22.68#ibcon#about to read 3, iclass 40, count 0 2006.168.08:22:22.70#ibcon#read 3, iclass 40, count 0 2006.168.08:22:22.70#ibcon#about to read 4, iclass 40, count 0 2006.168.08:22:22.70#ibcon#read 4, iclass 40, count 0 2006.168.08:22:22.70#ibcon#about to read 5, iclass 40, count 0 2006.168.08:22:22.70#ibcon#read 5, iclass 40, count 0 2006.168.08:22:22.70#ibcon#about to read 6, iclass 40, count 0 2006.168.08:22:22.70#ibcon#read 6, iclass 40, count 0 2006.168.08:22:22.70#ibcon#end of sib2, iclass 40, count 0 2006.168.08:22:22.70#ibcon#*mode == 0, iclass 40, count 0 2006.168.08:22:22.70#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.168.08:22:22.70#ibcon#[25=BW32\r\n] 2006.168.08:22:22.70#ibcon#*before write, iclass 40, count 0 2006.168.08:22:22.70#ibcon#enter sib2, iclass 40, count 0 2006.168.08:22:22.70#ibcon#flushed, iclass 40, count 0 2006.168.08:22:22.70#ibcon#about to write, iclass 40, count 0 2006.168.08:22:22.70#ibcon#wrote, iclass 40, count 0 2006.168.08:22:22.70#ibcon#about to read 3, iclass 40, count 0 2006.168.08:22:22.73#ibcon#read 3, iclass 40, count 0 2006.168.08:22:22.73#ibcon#about to read 4, iclass 40, count 0 2006.168.08:22:22.73#ibcon#read 4, iclass 40, count 0 2006.168.08:22:22.73#ibcon#about to read 5, iclass 40, count 0 2006.168.08:22:22.73#ibcon#read 5, iclass 40, count 0 2006.168.08:22:22.73#ibcon#about to read 6, iclass 40, count 0 2006.168.08:22:22.73#ibcon#read 6, iclass 40, count 0 2006.168.08:22:22.73#ibcon#end of sib2, iclass 40, count 0 2006.168.08:22:22.73#ibcon#*after write, iclass 40, count 0 2006.168.08:22:22.73#ibcon#*before return 0, iclass 40, count 0 2006.168.08:22:22.73#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:22:22.73#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:22:22.73#ibcon#about to clear, iclass 40 cls_cnt 0 2006.168.08:22:22.73#ibcon#cleared, iclass 40 cls_cnt 0 2006.168.08:22:22.73$vc4f8/vbbw=wide 2006.168.08:22:22.73#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.168.08:22:22.73#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.168.08:22:22.73#ibcon#ireg 8 cls_cnt 0 2006.168.08:22:22.73#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:22:22.80#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:22:22.80#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:22:22.80#ibcon#enter wrdev, iclass 4, count 0 2006.168.08:22:22.80#ibcon#first serial, iclass 4, count 0 2006.168.08:22:22.80#ibcon#enter sib2, iclass 4, count 0 2006.168.08:22:22.80#ibcon#flushed, iclass 4, count 0 2006.168.08:22:22.80#ibcon#about to write, iclass 4, count 0 2006.168.08:22:22.80#ibcon#wrote, iclass 4, count 0 2006.168.08:22:22.80#ibcon#about to read 3, iclass 4, count 0 2006.168.08:22:22.82#ibcon#read 3, iclass 4, count 0 2006.168.08:22:22.82#ibcon#about to read 4, iclass 4, count 0 2006.168.08:22:22.82#ibcon#read 4, iclass 4, count 0 2006.168.08:22:22.82#ibcon#about to read 5, iclass 4, count 0 2006.168.08:22:22.82#ibcon#read 5, iclass 4, count 0 2006.168.08:22:22.82#ibcon#about to read 6, iclass 4, count 0 2006.168.08:22:22.82#ibcon#read 6, iclass 4, count 0 2006.168.08:22:22.82#ibcon#end of sib2, iclass 4, count 0 2006.168.08:22:22.82#ibcon#*mode == 0, iclass 4, count 0 2006.168.08:22:22.82#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.168.08:22:22.82#ibcon#[27=BW32\r\n] 2006.168.08:22:22.82#ibcon#*before write, iclass 4, count 0 2006.168.08:22:22.82#ibcon#enter sib2, iclass 4, count 0 2006.168.08:22:22.82#ibcon#flushed, iclass 4, count 0 2006.168.08:22:22.82#ibcon#about to write, iclass 4, count 0 2006.168.08:22:22.82#ibcon#wrote, iclass 4, count 0 2006.168.08:22:22.82#ibcon#about to read 3, iclass 4, count 0 2006.168.08:22:22.85#ibcon#read 3, iclass 4, count 0 2006.168.08:22:22.85#ibcon#about to read 4, iclass 4, count 0 2006.168.08:22:22.85#ibcon#read 4, iclass 4, count 0 2006.168.08:22:22.85#ibcon#about to read 5, iclass 4, count 0 2006.168.08:22:22.85#ibcon#read 5, iclass 4, count 0 2006.168.08:22:22.85#ibcon#about to read 6, iclass 4, count 0 2006.168.08:22:22.85#ibcon#read 6, iclass 4, count 0 2006.168.08:22:22.85#ibcon#end of sib2, iclass 4, count 0 2006.168.08:22:22.85#ibcon#*after write, iclass 4, count 0 2006.168.08:22:22.85#ibcon#*before return 0, iclass 4, count 0 2006.168.08:22:22.85#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:22:22.85#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:22:22.85#ibcon#about to clear, iclass 4 cls_cnt 0 2006.168.08:22:22.85#ibcon#cleared, iclass 4 cls_cnt 0 2006.168.08:22:22.85$4f8m12a/ifd4f 2006.168.08:22:22.85$ifd4f/lo= 2006.168.08:22:22.85$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.08:22:22.85$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.08:22:22.85$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.08:22:22.85$ifd4f/patch= 2006.168.08:22:22.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.08:22:22.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.08:22:22.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.08:22:22.85$4f8m12a/"form=m,16.000,1:2 2006.168.08:22:22.85$4f8m12a/"tpicd 2006.168.08:22:22.85$4f8m12a/echo=off 2006.168.08:22:22.85$4f8m12a/xlog=off 2006.168.08:22:22.85:!2006.168.08:24:30 2006.168.08:22:42.14#trakl#Source acquired 2006.168.08:22:43.14#flagr#flagr/antenna,acquired 2006.168.08:24:30.02:preob 2006.168.08:24:31.15/onsource/TRACKING 2006.168.08:24:31.15:!2006.168.08:24:40 2006.168.08:24:40.02:data_valid=on 2006.168.08:24:40.02:midob 2006.168.08:24:41.15/onsource/TRACKING 2006.168.08:24:41.15/wx/26.82,1004.6,75 2006.168.08:24:41.28/cable/+6.4719E-03 2006.168.08:24:42.37/va/01,08,usb,yes,30,31 2006.168.08:24:42.37/va/02,07,usb,yes,30,31 2006.168.08:24:42.37/va/03,06,usb,yes,31,32 2006.168.08:24:42.37/va/04,07,usb,yes,30,33 2006.168.08:24:42.37/va/05,07,usb,yes,31,32 2006.168.08:24:42.37/va/06,06,usb,yes,30,30 2006.168.08:24:42.37/va/07,06,usb,yes,30,30 2006.168.08:24:42.37/va/08,07,usb,yes,29,28 2006.168.08:24:42.60/valo/01,532.99,yes,locked 2006.168.08:24:42.60/valo/02,572.99,yes,locked 2006.168.08:24:42.60/valo/03,672.99,yes,locked 2006.168.08:24:42.60/valo/04,832.99,yes,locked 2006.168.08:24:42.60/valo/05,652.99,yes,locked 2006.168.08:24:42.60/valo/06,772.99,yes,locked 2006.168.08:24:42.60/valo/07,832.99,yes,locked 2006.168.08:24:42.60/valo/08,852.99,yes,locked 2006.168.08:24:43.69/vb/01,04,usb,yes,29,28 2006.168.08:24:43.69/vb/02,04,usb,yes,31,33 2006.168.08:24:43.69/vb/03,04,usb,yes,28,31 2006.168.08:24:43.69/vb/04,04,usb,yes,28,28 2006.168.08:24:43.69/vb/05,04,usb,yes,27,31 2006.168.08:24:43.69/vb/06,04,usb,yes,28,31 2006.168.08:24:43.69/vb/07,04,usb,yes,30,30 2006.168.08:24:43.69/vb/08,04,usb,yes,27,31 2006.168.08:24:43.92/vblo/01,632.99,yes,locked 2006.168.08:24:43.92/vblo/02,640.99,yes,locked 2006.168.08:24:43.92/vblo/03,656.99,yes,locked 2006.168.08:24:43.92/vblo/04,712.99,yes,locked 2006.168.08:24:43.92/vblo/05,744.99,yes,locked 2006.168.08:24:43.92/vblo/06,752.99,yes,locked 2006.168.08:24:43.92/vblo/07,734.99,yes,locked 2006.168.08:24:43.92/vblo/08,744.99,yes,locked 2006.168.08:24:44.07/vabw/8 2006.168.08:24:44.22/vbbw/8 2006.168.08:24:44.32/xfe/off,on,14.2 2006.168.08:24:44.71/ifatt/23,28,28,28 2006.168.08:24:45.07/fmout-gps/S +4.17E-07 2006.168.08:24:45.15:!2006.168.08:25:40 2006.168.08:25:40.02:data_valid=off 2006.168.08:25:40.02:postob 2006.168.08:25:40.10/cable/+6.4706E-03 2006.168.08:25:40.10/wx/26.81,1004.6,77 2006.168.08:25:41.07/fmout-gps/S +4.18E-07 2006.168.08:25:41.08:scan_name=168-0826,k06168,60 2006.168.08:25:41.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.168.08:25:42.15#flagr#flagr/antenna,new-source 2006.168.08:25:42.15:checkk5 2006.168.08:25:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.168.08:25:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.168.08:25:43.27/chk_autoobs//k5ts3/ autoobs is running! 2006.168.08:25:43.65/chk_autoobs//k5ts4/ autoobs is running! 2006.168.08:25:44.02/chk_obsdata//k5ts1/T1680824??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.168.08:25:44.39/chk_obsdata//k5ts2/T1680824??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.168.08:25:44.76/chk_obsdata//k5ts3/T1680824??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.168.08:25:45.13/chk_obsdata//k5ts4/T1680824??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.168.08:25:45.82/k5log//k5ts1_log_newline 2006.168.08:25:46.52/k5log//k5ts2_log_newline 2006.168.08:25:47.21/k5log//k5ts3_log_newline 2006.168.08:25:47.90/k5log//k5ts4_log_newline 2006.168.08:25:47.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.08:25:47.92:4f8m12a=3 2006.168.08:25:47.92$4f8m12a/echo=on 2006.168.08:25:47.92$4f8m12a/pcalon 2006.168.08:25:47.92$pcalon/"no phase cal control is implemented here 2006.168.08:25:47.92$4f8m12a/"tpicd=stop 2006.168.08:25:47.92$4f8m12a/vc4f8 2006.168.08:25:47.92$vc4f8/valo=1,532.99 2006.168.08:25:47.93#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.168.08:25:47.93#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.168.08:25:47.93#ibcon#ireg 17 cls_cnt 0 2006.168.08:25:47.93#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:25:47.93#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:25:47.93#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:25:47.93#ibcon#enter wrdev, iclass 17, count 0 2006.168.08:25:47.93#ibcon#first serial, iclass 17, count 0 2006.168.08:25:47.93#ibcon#enter sib2, iclass 17, count 0 2006.168.08:25:47.93#ibcon#flushed, iclass 17, count 0 2006.168.08:25:47.93#ibcon#about to write, iclass 17, count 0 2006.168.08:25:47.93#ibcon#wrote, iclass 17, count 0 2006.168.08:25:47.93#ibcon#about to read 3, iclass 17, count 0 2006.168.08:25:47.97#ibcon#read 3, iclass 17, count 0 2006.168.08:25:47.97#ibcon#about to read 4, iclass 17, count 0 2006.168.08:25:47.97#ibcon#read 4, iclass 17, count 0 2006.168.08:25:47.97#ibcon#about to read 5, iclass 17, count 0 2006.168.08:25:47.97#ibcon#read 5, iclass 17, count 0 2006.168.08:25:47.97#ibcon#about to read 6, iclass 17, count 0 2006.168.08:25:47.97#ibcon#read 6, iclass 17, count 0 2006.168.08:25:47.97#ibcon#end of sib2, iclass 17, count 0 2006.168.08:25:47.97#ibcon#*mode == 0, iclass 17, count 0 2006.168.08:25:47.97#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.168.08:25:47.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.08:25:47.97#ibcon#*before write, iclass 17, count 0 2006.168.08:25:47.97#ibcon#enter sib2, iclass 17, count 0 2006.168.08:25:47.97#ibcon#flushed, iclass 17, count 0 2006.168.08:25:47.97#ibcon#about to write, iclass 17, count 0 2006.168.08:25:47.97#ibcon#wrote, iclass 17, count 0 2006.168.08:25:47.97#ibcon#about to read 3, iclass 17, count 0 2006.168.08:25:48.01#ibcon#read 3, iclass 17, count 0 2006.168.08:25:48.01#ibcon#about to read 4, iclass 17, count 0 2006.168.08:25:48.01#ibcon#read 4, iclass 17, count 0 2006.168.08:25:48.01#ibcon#about to read 5, iclass 17, count 0 2006.168.08:25:48.01#ibcon#read 5, iclass 17, count 0 2006.168.08:25:48.01#ibcon#about to read 6, iclass 17, count 0 2006.168.08:25:48.01#ibcon#read 6, iclass 17, count 0 2006.168.08:25:48.01#ibcon#end of sib2, iclass 17, count 0 2006.168.08:25:48.01#ibcon#*after write, iclass 17, count 0 2006.168.08:25:48.01#ibcon#*before return 0, iclass 17, count 0 2006.168.08:25:48.01#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:25:48.01#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:25:48.01#ibcon#about to clear, iclass 17 cls_cnt 0 2006.168.08:25:48.01#ibcon#cleared, iclass 17 cls_cnt 0 2006.168.08:25:48.01$vc4f8/va=1,8 2006.168.08:25:48.02#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.168.08:25:48.02#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.168.08:25:48.02#ibcon#ireg 11 cls_cnt 2 2006.168.08:25:48.02#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:25:48.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:25:48.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:25:48.02#ibcon#enter wrdev, iclass 19, count 2 2006.168.08:25:48.02#ibcon#first serial, iclass 19, count 2 2006.168.08:25:48.02#ibcon#enter sib2, iclass 19, count 2 2006.168.08:25:48.02#ibcon#flushed, iclass 19, count 2 2006.168.08:25:48.02#ibcon#about to write, iclass 19, count 2 2006.168.08:25:48.02#ibcon#wrote, iclass 19, count 2 2006.168.08:25:48.02#ibcon#about to read 3, iclass 19, count 2 2006.168.08:25:48.03#ibcon#read 3, iclass 19, count 2 2006.168.08:25:48.03#ibcon#about to read 4, iclass 19, count 2 2006.168.08:25:48.03#ibcon#read 4, iclass 19, count 2 2006.168.08:25:48.03#ibcon#about to read 5, iclass 19, count 2 2006.168.08:25:48.03#ibcon#read 5, iclass 19, count 2 2006.168.08:25:48.03#ibcon#about to read 6, iclass 19, count 2 2006.168.08:25:48.03#ibcon#read 6, iclass 19, count 2 2006.168.08:25:48.03#ibcon#end of sib2, iclass 19, count 2 2006.168.08:25:48.03#ibcon#*mode == 0, iclass 19, count 2 2006.168.08:25:48.03#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.168.08:25:48.03#ibcon#[25=AT01-08\r\n] 2006.168.08:25:48.03#ibcon#*before write, iclass 19, count 2 2006.168.08:25:48.03#ibcon#enter sib2, iclass 19, count 2 2006.168.08:25:48.03#ibcon#flushed, iclass 19, count 2 2006.168.08:25:48.03#ibcon#about to write, iclass 19, count 2 2006.168.08:25:48.03#ibcon#wrote, iclass 19, count 2 2006.168.08:25:48.03#ibcon#about to read 3, iclass 19, count 2 2006.168.08:25:48.06#ibcon#read 3, iclass 19, count 2 2006.168.08:25:48.06#ibcon#about to read 4, iclass 19, count 2 2006.168.08:25:48.06#ibcon#read 4, iclass 19, count 2 2006.168.08:25:48.06#ibcon#about to read 5, iclass 19, count 2 2006.168.08:25:48.06#ibcon#read 5, iclass 19, count 2 2006.168.08:25:48.06#ibcon#about to read 6, iclass 19, count 2 2006.168.08:25:48.06#ibcon#read 6, iclass 19, count 2 2006.168.08:25:48.06#ibcon#end of sib2, iclass 19, count 2 2006.168.08:25:48.06#ibcon#*after write, iclass 19, count 2 2006.168.08:25:48.06#ibcon#*before return 0, iclass 19, count 2 2006.168.08:25:48.06#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:25:48.06#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:25:48.06#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.168.08:25:48.06#ibcon#ireg 7 cls_cnt 0 2006.168.08:25:48.06#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:25:48.18#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:25:48.18#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:25:48.18#ibcon#enter wrdev, iclass 19, count 0 2006.168.08:25:48.18#ibcon#first serial, iclass 19, count 0 2006.168.08:25:48.18#ibcon#enter sib2, iclass 19, count 0 2006.168.08:25:48.18#ibcon#flushed, iclass 19, count 0 2006.168.08:25:48.18#ibcon#about to write, iclass 19, count 0 2006.168.08:25:48.18#ibcon#wrote, iclass 19, count 0 2006.168.08:25:48.18#ibcon#about to read 3, iclass 19, count 0 2006.168.08:25:48.20#ibcon#read 3, iclass 19, count 0 2006.168.08:25:48.20#ibcon#about to read 4, iclass 19, count 0 2006.168.08:25:48.20#ibcon#read 4, iclass 19, count 0 2006.168.08:25:48.20#ibcon#about to read 5, iclass 19, count 0 2006.168.08:25:48.20#ibcon#read 5, iclass 19, count 0 2006.168.08:25:48.20#ibcon#about to read 6, iclass 19, count 0 2006.168.08:25:48.20#ibcon#read 6, iclass 19, count 0 2006.168.08:25:48.20#ibcon#end of sib2, iclass 19, count 0 2006.168.08:25:48.20#ibcon#*mode == 0, iclass 19, count 0 2006.168.08:25:48.20#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.168.08:25:48.20#ibcon#[25=USB\r\n] 2006.168.08:25:48.20#ibcon#*before write, iclass 19, count 0 2006.168.08:25:48.20#ibcon#enter sib2, iclass 19, count 0 2006.168.08:25:48.20#ibcon#flushed, iclass 19, count 0 2006.168.08:25:48.20#ibcon#about to write, iclass 19, count 0 2006.168.08:25:48.20#ibcon#wrote, iclass 19, count 0 2006.168.08:25:48.20#ibcon#about to read 3, iclass 19, count 0 2006.168.08:25:48.23#ibcon#read 3, iclass 19, count 0 2006.168.08:25:48.23#ibcon#about to read 4, iclass 19, count 0 2006.168.08:25:48.23#ibcon#read 4, iclass 19, count 0 2006.168.08:25:48.23#ibcon#about to read 5, iclass 19, count 0 2006.168.08:25:48.23#ibcon#read 5, iclass 19, count 0 2006.168.08:25:48.23#ibcon#about to read 6, iclass 19, count 0 2006.168.08:25:48.23#ibcon#read 6, iclass 19, count 0 2006.168.08:25:48.23#ibcon#end of sib2, iclass 19, count 0 2006.168.08:25:48.23#ibcon#*after write, iclass 19, count 0 2006.168.08:25:48.23#ibcon#*before return 0, iclass 19, count 0 2006.168.08:25:48.23#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:25:48.23#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:25:48.23#ibcon#about to clear, iclass 19 cls_cnt 0 2006.168.08:25:48.23#ibcon#cleared, iclass 19 cls_cnt 0 2006.168.08:25:48.23$vc4f8/valo=2,572.99 2006.168.08:25:48.24#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.168.08:25:48.24#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.168.08:25:48.24#ibcon#ireg 17 cls_cnt 0 2006.168.08:25:48.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:25:48.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:25:48.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:25:48.24#ibcon#enter wrdev, iclass 21, count 0 2006.168.08:25:48.24#ibcon#first serial, iclass 21, count 0 2006.168.08:25:48.24#ibcon#enter sib2, iclass 21, count 0 2006.168.08:25:48.24#ibcon#flushed, iclass 21, count 0 2006.168.08:25:48.24#ibcon#about to write, iclass 21, count 0 2006.168.08:25:48.24#ibcon#wrote, iclass 21, count 0 2006.168.08:25:48.24#ibcon#about to read 3, iclass 21, count 0 2006.168.08:25:48.26#ibcon#read 3, iclass 21, count 0 2006.168.08:25:48.26#ibcon#about to read 4, iclass 21, count 0 2006.168.08:25:48.26#ibcon#read 4, iclass 21, count 0 2006.168.08:25:48.26#ibcon#about to read 5, iclass 21, count 0 2006.168.08:25:48.26#ibcon#read 5, iclass 21, count 0 2006.168.08:25:48.26#ibcon#about to read 6, iclass 21, count 0 2006.168.08:25:48.26#ibcon#read 6, iclass 21, count 0 2006.168.08:25:48.26#ibcon#end of sib2, iclass 21, count 0 2006.168.08:25:48.26#ibcon#*mode == 0, iclass 21, count 0 2006.168.08:25:48.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.168.08:25:48.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.08:25:48.26#ibcon#*before write, iclass 21, count 0 2006.168.08:25:48.26#ibcon#enter sib2, iclass 21, count 0 2006.168.08:25:48.26#ibcon#flushed, iclass 21, count 0 2006.168.08:25:48.26#ibcon#about to write, iclass 21, count 0 2006.168.08:25:48.26#ibcon#wrote, iclass 21, count 0 2006.168.08:25:48.26#ibcon#about to read 3, iclass 21, count 0 2006.168.08:25:48.29#ibcon#read 3, iclass 21, count 0 2006.168.08:25:48.29#ibcon#about to read 4, iclass 21, count 0 2006.168.08:25:48.29#ibcon#read 4, iclass 21, count 0 2006.168.08:25:48.29#ibcon#about to read 5, iclass 21, count 0 2006.168.08:25:48.29#ibcon#read 5, iclass 21, count 0 2006.168.08:25:48.29#ibcon#about to read 6, iclass 21, count 0 2006.168.08:25:48.29#ibcon#read 6, iclass 21, count 0 2006.168.08:25:48.29#ibcon#end of sib2, iclass 21, count 0 2006.168.08:25:48.29#ibcon#*after write, iclass 21, count 0 2006.168.08:25:48.29#ibcon#*before return 0, iclass 21, count 0 2006.168.08:25:48.29#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:25:48.29#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:25:48.29#ibcon#about to clear, iclass 21 cls_cnt 0 2006.168.08:25:48.29#ibcon#cleared, iclass 21 cls_cnt 0 2006.168.08:25:48.30$vc4f8/va=2,7 2006.168.08:25:48.30#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.168.08:25:48.30#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.168.08:25:48.30#ibcon#ireg 11 cls_cnt 2 2006.168.08:25:48.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.168.08:25:48.35#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.168.08:25:48.35#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.168.08:25:48.35#ibcon#enter wrdev, iclass 23, count 2 2006.168.08:25:48.35#ibcon#first serial, iclass 23, count 2 2006.168.08:25:48.35#ibcon#enter sib2, iclass 23, count 2 2006.168.08:25:48.35#ibcon#flushed, iclass 23, count 2 2006.168.08:25:48.35#ibcon#about to write, iclass 23, count 2 2006.168.08:25:48.35#ibcon#wrote, iclass 23, count 2 2006.168.08:25:48.35#ibcon#about to read 3, iclass 23, count 2 2006.168.08:25:48.36#ibcon#read 3, iclass 23, count 2 2006.168.08:25:48.36#ibcon#about to read 4, iclass 23, count 2 2006.168.08:25:48.36#ibcon#read 4, iclass 23, count 2 2006.168.08:25:48.36#ibcon#about to read 5, iclass 23, count 2 2006.168.08:25:48.36#ibcon#read 5, iclass 23, count 2 2006.168.08:25:48.36#ibcon#about to read 6, iclass 23, count 2 2006.168.08:25:48.36#ibcon#read 6, iclass 23, count 2 2006.168.08:25:48.36#ibcon#end of sib2, iclass 23, count 2 2006.168.08:25:48.36#ibcon#*mode == 0, iclass 23, count 2 2006.168.08:25:48.36#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.168.08:25:48.36#ibcon#[25=AT02-07\r\n] 2006.168.08:25:48.36#ibcon#*before write, iclass 23, count 2 2006.168.08:25:48.36#ibcon#enter sib2, iclass 23, count 2 2006.168.08:25:48.36#ibcon#flushed, iclass 23, count 2 2006.168.08:25:48.36#ibcon#about to write, iclass 23, count 2 2006.168.08:25:48.36#ibcon#wrote, iclass 23, count 2 2006.168.08:25:48.36#ibcon#about to read 3, iclass 23, count 2 2006.168.08:25:48.39#ibcon#read 3, iclass 23, count 2 2006.168.08:25:48.39#ibcon#about to read 4, iclass 23, count 2 2006.168.08:25:48.39#ibcon#read 4, iclass 23, count 2 2006.168.08:25:48.39#ibcon#about to read 5, iclass 23, count 2 2006.168.08:25:48.39#ibcon#read 5, iclass 23, count 2 2006.168.08:25:48.39#ibcon#about to read 6, iclass 23, count 2 2006.168.08:25:48.39#ibcon#read 6, iclass 23, count 2 2006.168.08:25:48.39#ibcon#end of sib2, iclass 23, count 2 2006.168.08:25:48.39#ibcon#*after write, iclass 23, count 2 2006.168.08:25:48.39#ibcon#*before return 0, iclass 23, count 2 2006.168.08:25:48.39#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.168.08:25:48.39#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.168.08:25:48.39#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.168.08:25:48.39#ibcon#ireg 7 cls_cnt 0 2006.168.08:25:48.39#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.168.08:25:48.51#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.168.08:25:48.51#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.168.08:25:48.51#ibcon#enter wrdev, iclass 23, count 0 2006.168.08:25:48.51#ibcon#first serial, iclass 23, count 0 2006.168.08:25:48.51#ibcon#enter sib2, iclass 23, count 0 2006.168.08:25:48.51#ibcon#flushed, iclass 23, count 0 2006.168.08:25:48.51#ibcon#about to write, iclass 23, count 0 2006.168.08:25:48.51#ibcon#wrote, iclass 23, count 0 2006.168.08:25:48.51#ibcon#about to read 3, iclass 23, count 0 2006.168.08:25:48.53#ibcon#read 3, iclass 23, count 0 2006.168.08:25:48.53#ibcon#about to read 4, iclass 23, count 0 2006.168.08:25:48.53#ibcon#read 4, iclass 23, count 0 2006.168.08:25:48.53#ibcon#about to read 5, iclass 23, count 0 2006.168.08:25:48.53#ibcon#read 5, iclass 23, count 0 2006.168.08:25:48.53#ibcon#about to read 6, iclass 23, count 0 2006.168.08:25:48.53#ibcon#read 6, iclass 23, count 0 2006.168.08:25:48.53#ibcon#end of sib2, iclass 23, count 0 2006.168.08:25:48.53#ibcon#*mode == 0, iclass 23, count 0 2006.168.08:25:48.53#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.168.08:25:48.53#ibcon#[25=USB\r\n] 2006.168.08:25:48.53#ibcon#*before write, iclass 23, count 0 2006.168.08:25:48.53#ibcon#enter sib2, iclass 23, count 0 2006.168.08:25:48.53#ibcon#flushed, iclass 23, count 0 2006.168.08:25:48.53#ibcon#about to write, iclass 23, count 0 2006.168.08:25:48.53#ibcon#wrote, iclass 23, count 0 2006.168.08:25:48.53#ibcon#about to read 3, iclass 23, count 0 2006.168.08:25:48.56#ibcon#read 3, iclass 23, count 0 2006.168.08:25:48.56#ibcon#about to read 4, iclass 23, count 0 2006.168.08:25:48.56#ibcon#read 4, iclass 23, count 0 2006.168.08:25:48.56#ibcon#about to read 5, iclass 23, count 0 2006.168.08:25:48.56#ibcon#read 5, iclass 23, count 0 2006.168.08:25:48.56#ibcon#about to read 6, iclass 23, count 0 2006.168.08:25:48.56#ibcon#read 6, iclass 23, count 0 2006.168.08:25:48.56#ibcon#end of sib2, iclass 23, count 0 2006.168.08:25:48.56#ibcon#*after write, iclass 23, count 0 2006.168.08:25:48.56#ibcon#*before return 0, iclass 23, count 0 2006.168.08:25:48.56#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.168.08:25:48.56#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.168.08:25:48.56#ibcon#about to clear, iclass 23 cls_cnt 0 2006.168.08:25:48.56#ibcon#cleared, iclass 23 cls_cnt 0 2006.168.08:25:48.56$vc4f8/valo=3,672.99 2006.168.08:25:48.57#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.168.08:25:48.57#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.168.08:25:48.57#ibcon#ireg 17 cls_cnt 0 2006.168.08:25:48.57#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.168.08:25:48.57#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.168.08:25:48.57#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.168.08:25:48.57#ibcon#enter wrdev, iclass 25, count 0 2006.168.08:25:48.57#ibcon#first serial, iclass 25, count 0 2006.168.08:25:48.57#ibcon#enter sib2, iclass 25, count 0 2006.168.08:25:48.57#ibcon#flushed, iclass 25, count 0 2006.168.08:25:48.57#ibcon#about to write, iclass 25, count 0 2006.168.08:25:48.57#ibcon#wrote, iclass 25, count 0 2006.168.08:25:48.57#ibcon#about to read 3, iclass 25, count 0 2006.168.08:25:48.58#ibcon#read 3, iclass 25, count 0 2006.168.08:25:48.58#ibcon#about to read 4, iclass 25, count 0 2006.168.08:25:48.58#ibcon#read 4, iclass 25, count 0 2006.168.08:25:48.58#ibcon#about to read 5, iclass 25, count 0 2006.168.08:25:48.58#ibcon#read 5, iclass 25, count 0 2006.168.08:25:48.58#ibcon#about to read 6, iclass 25, count 0 2006.168.08:25:48.58#ibcon#read 6, iclass 25, count 0 2006.168.08:25:48.58#ibcon#end of sib2, iclass 25, count 0 2006.168.08:25:48.58#ibcon#*mode == 0, iclass 25, count 0 2006.168.08:25:48.58#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.168.08:25:48.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.08:25:48.58#ibcon#*before write, iclass 25, count 0 2006.168.08:25:48.58#ibcon#enter sib2, iclass 25, count 0 2006.168.08:25:48.58#ibcon#flushed, iclass 25, count 0 2006.168.08:25:48.58#ibcon#about to write, iclass 25, count 0 2006.168.08:25:48.58#ibcon#wrote, iclass 25, count 0 2006.168.08:25:48.58#ibcon#about to read 3, iclass 25, count 0 2006.168.08:25:48.63#ibcon#read 3, iclass 25, count 0 2006.168.08:25:48.63#ibcon#about to read 4, iclass 25, count 0 2006.168.08:25:48.63#ibcon#read 4, iclass 25, count 0 2006.168.08:25:48.63#ibcon#about to read 5, iclass 25, count 0 2006.168.08:25:48.63#ibcon#read 5, iclass 25, count 0 2006.168.08:25:48.63#ibcon#about to read 6, iclass 25, count 0 2006.168.08:25:48.63#ibcon#read 6, iclass 25, count 0 2006.168.08:25:48.63#ibcon#end of sib2, iclass 25, count 0 2006.168.08:25:48.63#ibcon#*after write, iclass 25, count 0 2006.168.08:25:48.63#ibcon#*before return 0, iclass 25, count 0 2006.168.08:25:48.63#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.168.08:25:48.63#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.168.08:25:48.63#ibcon#about to clear, iclass 25 cls_cnt 0 2006.168.08:25:48.63#ibcon#cleared, iclass 25 cls_cnt 0 2006.168.08:25:48.63$vc4f8/va=3,6 2006.168.08:25:48.63#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.168.08:25:48.63#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.168.08:25:48.63#ibcon#ireg 11 cls_cnt 2 2006.168.08:25:48.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.168.08:25:48.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.168.08:25:48.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.168.08:25:48.67#ibcon#enter wrdev, iclass 27, count 2 2006.168.08:25:48.67#ibcon#first serial, iclass 27, count 2 2006.168.08:25:48.67#ibcon#enter sib2, iclass 27, count 2 2006.168.08:25:48.67#ibcon#flushed, iclass 27, count 2 2006.168.08:25:48.67#ibcon#about to write, iclass 27, count 2 2006.168.08:25:48.67#ibcon#wrote, iclass 27, count 2 2006.168.08:25:48.67#ibcon#about to read 3, iclass 27, count 2 2006.168.08:25:48.70#ibcon#read 3, iclass 27, count 2 2006.168.08:25:48.70#ibcon#about to read 4, iclass 27, count 2 2006.168.08:25:48.70#ibcon#read 4, iclass 27, count 2 2006.168.08:25:48.70#ibcon#about to read 5, iclass 27, count 2 2006.168.08:25:48.70#ibcon#read 5, iclass 27, count 2 2006.168.08:25:48.70#ibcon#about to read 6, iclass 27, count 2 2006.168.08:25:48.70#ibcon#read 6, iclass 27, count 2 2006.168.08:25:48.70#ibcon#end of sib2, iclass 27, count 2 2006.168.08:25:48.70#ibcon#*mode == 0, iclass 27, count 2 2006.168.08:25:48.70#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.168.08:25:48.70#ibcon#[25=AT03-06\r\n] 2006.168.08:25:48.70#ibcon#*before write, iclass 27, count 2 2006.168.08:25:48.70#ibcon#enter sib2, iclass 27, count 2 2006.168.08:25:48.70#ibcon#flushed, iclass 27, count 2 2006.168.08:25:48.70#ibcon#about to write, iclass 27, count 2 2006.168.08:25:48.70#ibcon#wrote, iclass 27, count 2 2006.168.08:25:48.70#ibcon#about to read 3, iclass 27, count 2 2006.168.08:25:48.73#ibcon#read 3, iclass 27, count 2 2006.168.08:25:48.73#ibcon#about to read 4, iclass 27, count 2 2006.168.08:25:48.73#ibcon#read 4, iclass 27, count 2 2006.168.08:25:48.73#ibcon#about to read 5, iclass 27, count 2 2006.168.08:25:48.73#ibcon#read 5, iclass 27, count 2 2006.168.08:25:48.73#ibcon#about to read 6, iclass 27, count 2 2006.168.08:25:48.73#ibcon#read 6, iclass 27, count 2 2006.168.08:25:48.73#ibcon#end of sib2, iclass 27, count 2 2006.168.08:25:48.73#ibcon#*after write, iclass 27, count 2 2006.168.08:25:48.73#ibcon#*before return 0, iclass 27, count 2 2006.168.08:25:48.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.168.08:25:48.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.168.08:25:48.73#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.168.08:25:48.73#ibcon#ireg 7 cls_cnt 0 2006.168.08:25:48.73#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.168.08:25:48.85#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.168.08:25:48.85#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.168.08:25:48.85#ibcon#enter wrdev, iclass 27, count 0 2006.168.08:25:48.85#ibcon#first serial, iclass 27, count 0 2006.168.08:25:48.85#ibcon#enter sib2, iclass 27, count 0 2006.168.08:25:48.85#ibcon#flushed, iclass 27, count 0 2006.168.08:25:48.85#ibcon#about to write, iclass 27, count 0 2006.168.08:25:48.85#ibcon#wrote, iclass 27, count 0 2006.168.08:25:48.85#ibcon#about to read 3, iclass 27, count 0 2006.168.08:25:48.87#ibcon#read 3, iclass 27, count 0 2006.168.08:25:48.87#ibcon#about to read 4, iclass 27, count 0 2006.168.08:25:48.87#ibcon#read 4, iclass 27, count 0 2006.168.08:25:48.87#ibcon#about to read 5, iclass 27, count 0 2006.168.08:25:48.87#ibcon#read 5, iclass 27, count 0 2006.168.08:25:48.87#ibcon#about to read 6, iclass 27, count 0 2006.168.08:25:48.87#ibcon#read 6, iclass 27, count 0 2006.168.08:25:48.87#ibcon#end of sib2, iclass 27, count 0 2006.168.08:25:48.87#ibcon#*mode == 0, iclass 27, count 0 2006.168.08:25:48.87#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.168.08:25:48.87#ibcon#[25=USB\r\n] 2006.168.08:25:48.87#ibcon#*before write, iclass 27, count 0 2006.168.08:25:48.87#ibcon#enter sib2, iclass 27, count 0 2006.168.08:25:48.87#ibcon#flushed, iclass 27, count 0 2006.168.08:25:48.87#ibcon#about to write, iclass 27, count 0 2006.168.08:25:48.87#ibcon#wrote, iclass 27, count 0 2006.168.08:25:48.87#ibcon#about to read 3, iclass 27, count 0 2006.168.08:25:48.90#ibcon#read 3, iclass 27, count 0 2006.168.08:25:48.90#ibcon#about to read 4, iclass 27, count 0 2006.168.08:25:48.90#ibcon#read 4, iclass 27, count 0 2006.168.08:25:48.90#ibcon#about to read 5, iclass 27, count 0 2006.168.08:25:48.90#ibcon#read 5, iclass 27, count 0 2006.168.08:25:48.90#ibcon#about to read 6, iclass 27, count 0 2006.168.08:25:48.90#ibcon#read 6, iclass 27, count 0 2006.168.08:25:48.90#ibcon#end of sib2, iclass 27, count 0 2006.168.08:25:48.90#ibcon#*after write, iclass 27, count 0 2006.168.08:25:48.90#ibcon#*before return 0, iclass 27, count 0 2006.168.08:25:48.90#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.168.08:25:48.90#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.168.08:25:48.90#ibcon#about to clear, iclass 27 cls_cnt 0 2006.168.08:25:48.90#ibcon#cleared, iclass 27 cls_cnt 0 2006.168.08:25:48.90$vc4f8/valo=4,832.99 2006.168.08:25:48.91#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.168.08:25:48.91#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.168.08:25:48.91#ibcon#ireg 17 cls_cnt 0 2006.168.08:25:48.91#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.168.08:25:48.91#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.168.08:25:48.91#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.168.08:25:48.91#ibcon#enter wrdev, iclass 29, count 0 2006.168.08:25:48.91#ibcon#first serial, iclass 29, count 0 2006.168.08:25:48.91#ibcon#enter sib2, iclass 29, count 0 2006.168.08:25:48.91#ibcon#flushed, iclass 29, count 0 2006.168.08:25:48.91#ibcon#about to write, iclass 29, count 0 2006.168.08:25:48.91#ibcon#wrote, iclass 29, count 0 2006.168.08:25:48.91#ibcon#about to read 3, iclass 29, count 0 2006.168.08:25:48.92#ibcon#read 3, iclass 29, count 0 2006.168.08:25:48.92#ibcon#about to read 4, iclass 29, count 0 2006.168.08:25:48.92#ibcon#read 4, iclass 29, count 0 2006.168.08:25:48.92#ibcon#about to read 5, iclass 29, count 0 2006.168.08:25:48.92#ibcon#read 5, iclass 29, count 0 2006.168.08:25:48.92#ibcon#about to read 6, iclass 29, count 0 2006.168.08:25:48.92#ibcon#read 6, iclass 29, count 0 2006.168.08:25:48.92#ibcon#end of sib2, iclass 29, count 0 2006.168.08:25:48.92#ibcon#*mode == 0, iclass 29, count 0 2006.168.08:25:48.92#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.168.08:25:48.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.08:25:48.92#ibcon#*before write, iclass 29, count 0 2006.168.08:25:48.92#ibcon#enter sib2, iclass 29, count 0 2006.168.08:25:48.92#ibcon#flushed, iclass 29, count 0 2006.168.08:25:48.92#ibcon#about to write, iclass 29, count 0 2006.168.08:25:48.92#ibcon#wrote, iclass 29, count 0 2006.168.08:25:48.92#ibcon#about to read 3, iclass 29, count 0 2006.168.08:25:48.96#ibcon#read 3, iclass 29, count 0 2006.168.08:25:48.96#ibcon#about to read 4, iclass 29, count 0 2006.168.08:25:48.96#ibcon#read 4, iclass 29, count 0 2006.168.08:25:48.96#ibcon#about to read 5, iclass 29, count 0 2006.168.08:25:48.96#ibcon#read 5, iclass 29, count 0 2006.168.08:25:48.96#ibcon#about to read 6, iclass 29, count 0 2006.168.08:25:48.96#ibcon#read 6, iclass 29, count 0 2006.168.08:25:48.96#ibcon#end of sib2, iclass 29, count 0 2006.168.08:25:48.96#ibcon#*after write, iclass 29, count 0 2006.168.08:25:48.96#ibcon#*before return 0, iclass 29, count 0 2006.168.08:25:48.96#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.168.08:25:48.96#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.168.08:25:48.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.168.08:25:48.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.168.08:25:48.97$vc4f8/va=4,7 2006.168.08:25:48.97#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.168.08:25:48.97#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.168.08:25:48.97#ibcon#ireg 11 cls_cnt 2 2006.168.08:25:48.97#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.168.08:25:49.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.168.08:25:49.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.168.08:25:49.01#ibcon#enter wrdev, iclass 31, count 2 2006.168.08:25:49.01#ibcon#first serial, iclass 31, count 2 2006.168.08:25:49.01#ibcon#enter sib2, iclass 31, count 2 2006.168.08:25:49.01#ibcon#flushed, iclass 31, count 2 2006.168.08:25:49.01#ibcon#about to write, iclass 31, count 2 2006.168.08:25:49.01#ibcon#wrote, iclass 31, count 2 2006.168.08:25:49.01#ibcon#about to read 3, iclass 31, count 2 2006.168.08:25:49.03#ibcon#read 3, iclass 31, count 2 2006.168.08:25:49.03#ibcon#about to read 4, iclass 31, count 2 2006.168.08:25:49.03#ibcon#read 4, iclass 31, count 2 2006.168.08:25:49.03#ibcon#about to read 5, iclass 31, count 2 2006.168.08:25:49.03#ibcon#read 5, iclass 31, count 2 2006.168.08:25:49.03#ibcon#about to read 6, iclass 31, count 2 2006.168.08:25:49.03#ibcon#read 6, iclass 31, count 2 2006.168.08:25:49.03#ibcon#end of sib2, iclass 31, count 2 2006.168.08:25:49.03#ibcon#*mode == 0, iclass 31, count 2 2006.168.08:25:49.03#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.168.08:25:49.03#ibcon#[25=AT04-07\r\n] 2006.168.08:25:49.03#ibcon#*before write, iclass 31, count 2 2006.168.08:25:49.03#ibcon#enter sib2, iclass 31, count 2 2006.168.08:25:49.03#ibcon#flushed, iclass 31, count 2 2006.168.08:25:49.03#ibcon#about to write, iclass 31, count 2 2006.168.08:25:49.03#ibcon#wrote, iclass 31, count 2 2006.168.08:25:49.03#ibcon#about to read 3, iclass 31, count 2 2006.168.08:25:49.06#ibcon#read 3, iclass 31, count 2 2006.168.08:25:49.06#ibcon#about to read 4, iclass 31, count 2 2006.168.08:25:49.06#ibcon#read 4, iclass 31, count 2 2006.168.08:25:49.06#ibcon#about to read 5, iclass 31, count 2 2006.168.08:25:49.06#ibcon#read 5, iclass 31, count 2 2006.168.08:25:49.06#ibcon#about to read 6, iclass 31, count 2 2006.168.08:25:49.06#ibcon#read 6, iclass 31, count 2 2006.168.08:25:49.06#ibcon#end of sib2, iclass 31, count 2 2006.168.08:25:49.06#ibcon#*after write, iclass 31, count 2 2006.168.08:25:49.06#ibcon#*before return 0, iclass 31, count 2 2006.168.08:25:49.06#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.168.08:25:49.06#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.168.08:25:49.06#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.168.08:25:49.06#ibcon#ireg 7 cls_cnt 0 2006.168.08:25:49.06#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.168.08:25:49.18#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.168.08:25:49.18#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.168.08:25:49.18#ibcon#enter wrdev, iclass 31, count 0 2006.168.08:25:49.18#ibcon#first serial, iclass 31, count 0 2006.168.08:25:49.18#ibcon#enter sib2, iclass 31, count 0 2006.168.08:25:49.18#ibcon#flushed, iclass 31, count 0 2006.168.08:25:49.18#ibcon#about to write, iclass 31, count 0 2006.168.08:25:49.18#ibcon#wrote, iclass 31, count 0 2006.168.08:25:49.18#ibcon#about to read 3, iclass 31, count 0 2006.168.08:25:49.20#ibcon#read 3, iclass 31, count 0 2006.168.08:25:49.20#ibcon#about to read 4, iclass 31, count 0 2006.168.08:25:49.20#ibcon#read 4, iclass 31, count 0 2006.168.08:25:49.20#ibcon#about to read 5, iclass 31, count 0 2006.168.08:25:49.20#ibcon#read 5, iclass 31, count 0 2006.168.08:25:49.20#ibcon#about to read 6, iclass 31, count 0 2006.168.08:25:49.20#ibcon#read 6, iclass 31, count 0 2006.168.08:25:49.20#ibcon#end of sib2, iclass 31, count 0 2006.168.08:25:49.20#ibcon#*mode == 0, iclass 31, count 0 2006.168.08:25:49.20#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.168.08:25:49.20#ibcon#[25=USB\r\n] 2006.168.08:25:49.20#ibcon#*before write, iclass 31, count 0 2006.168.08:25:49.20#ibcon#enter sib2, iclass 31, count 0 2006.168.08:25:49.20#ibcon#flushed, iclass 31, count 0 2006.168.08:25:49.20#ibcon#about to write, iclass 31, count 0 2006.168.08:25:49.20#ibcon#wrote, iclass 31, count 0 2006.168.08:25:49.20#ibcon#about to read 3, iclass 31, count 0 2006.168.08:25:49.23#ibcon#read 3, iclass 31, count 0 2006.168.08:25:49.23#ibcon#about to read 4, iclass 31, count 0 2006.168.08:25:49.23#ibcon#read 4, iclass 31, count 0 2006.168.08:25:49.23#ibcon#about to read 5, iclass 31, count 0 2006.168.08:25:49.23#ibcon#read 5, iclass 31, count 0 2006.168.08:25:49.23#ibcon#about to read 6, iclass 31, count 0 2006.168.08:25:49.23#ibcon#read 6, iclass 31, count 0 2006.168.08:25:49.23#ibcon#end of sib2, iclass 31, count 0 2006.168.08:25:49.23#ibcon#*after write, iclass 31, count 0 2006.168.08:25:49.23#ibcon#*before return 0, iclass 31, count 0 2006.168.08:25:49.23#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.168.08:25:49.23#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.168.08:25:49.23#ibcon#about to clear, iclass 31 cls_cnt 0 2006.168.08:25:49.23#ibcon#cleared, iclass 31 cls_cnt 0 2006.168.08:25:49.23$vc4f8/valo=5,652.99 2006.168.08:25:49.24#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.168.08:25:49.24#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.168.08:25:49.24#ibcon#ireg 17 cls_cnt 0 2006.168.08:25:49.24#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:25:49.24#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:25:49.24#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:25:49.24#ibcon#enter wrdev, iclass 33, count 0 2006.168.08:25:49.24#ibcon#first serial, iclass 33, count 0 2006.168.08:25:49.24#ibcon#enter sib2, iclass 33, count 0 2006.168.08:25:49.24#ibcon#flushed, iclass 33, count 0 2006.168.08:25:49.24#ibcon#about to write, iclass 33, count 0 2006.168.08:25:49.24#ibcon#wrote, iclass 33, count 0 2006.168.08:25:49.24#ibcon#about to read 3, iclass 33, count 0 2006.168.08:25:49.25#ibcon#read 3, iclass 33, count 0 2006.168.08:25:49.25#ibcon#about to read 4, iclass 33, count 0 2006.168.08:25:49.25#ibcon#read 4, iclass 33, count 0 2006.168.08:25:49.25#ibcon#about to read 5, iclass 33, count 0 2006.168.08:25:49.25#ibcon#read 5, iclass 33, count 0 2006.168.08:25:49.25#ibcon#about to read 6, iclass 33, count 0 2006.168.08:25:49.25#ibcon#read 6, iclass 33, count 0 2006.168.08:25:49.25#ibcon#end of sib2, iclass 33, count 0 2006.168.08:25:49.25#ibcon#*mode == 0, iclass 33, count 0 2006.168.08:25:49.25#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.168.08:25:49.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.08:25:49.25#ibcon#*before write, iclass 33, count 0 2006.168.08:25:49.25#ibcon#enter sib2, iclass 33, count 0 2006.168.08:25:49.25#ibcon#flushed, iclass 33, count 0 2006.168.08:25:49.25#ibcon#about to write, iclass 33, count 0 2006.168.08:25:49.25#ibcon#wrote, iclass 33, count 0 2006.168.08:25:49.25#ibcon#about to read 3, iclass 33, count 0 2006.168.08:25:49.29#ibcon#read 3, iclass 33, count 0 2006.168.08:25:49.29#ibcon#about to read 4, iclass 33, count 0 2006.168.08:25:49.29#ibcon#read 4, iclass 33, count 0 2006.168.08:25:49.29#ibcon#about to read 5, iclass 33, count 0 2006.168.08:25:49.29#ibcon#read 5, iclass 33, count 0 2006.168.08:25:49.29#ibcon#about to read 6, iclass 33, count 0 2006.168.08:25:49.29#ibcon#read 6, iclass 33, count 0 2006.168.08:25:49.29#ibcon#end of sib2, iclass 33, count 0 2006.168.08:25:49.29#ibcon#*after write, iclass 33, count 0 2006.168.08:25:49.29#ibcon#*before return 0, iclass 33, count 0 2006.168.08:25:49.29#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:25:49.29#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:25:49.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.168.08:25:49.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.168.08:25:49.29$vc4f8/va=5,7 2006.168.08:25:49.29#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.168.08:25:49.30#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.168.08:25:49.30#ibcon#ireg 11 cls_cnt 2 2006.168.08:25:49.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.168.08:25:49.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.168.08:25:49.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.168.08:25:49.34#ibcon#enter wrdev, iclass 35, count 2 2006.168.08:25:49.34#ibcon#first serial, iclass 35, count 2 2006.168.08:25:49.34#ibcon#enter sib2, iclass 35, count 2 2006.168.08:25:49.34#ibcon#flushed, iclass 35, count 2 2006.168.08:25:49.34#ibcon#about to write, iclass 35, count 2 2006.168.08:25:49.34#ibcon#wrote, iclass 35, count 2 2006.168.08:25:49.34#ibcon#about to read 3, iclass 35, count 2 2006.168.08:25:49.36#ibcon#read 3, iclass 35, count 2 2006.168.08:25:49.36#ibcon#about to read 4, iclass 35, count 2 2006.168.08:25:49.36#ibcon#read 4, iclass 35, count 2 2006.168.08:25:49.36#ibcon#about to read 5, iclass 35, count 2 2006.168.08:25:49.36#ibcon#read 5, iclass 35, count 2 2006.168.08:25:49.36#ibcon#about to read 6, iclass 35, count 2 2006.168.08:25:49.36#ibcon#read 6, iclass 35, count 2 2006.168.08:25:49.36#ibcon#end of sib2, iclass 35, count 2 2006.168.08:25:49.36#ibcon#*mode == 0, iclass 35, count 2 2006.168.08:25:49.36#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.168.08:25:49.36#ibcon#[25=AT05-07\r\n] 2006.168.08:25:49.36#ibcon#*before write, iclass 35, count 2 2006.168.08:25:49.36#ibcon#enter sib2, iclass 35, count 2 2006.168.08:25:49.36#ibcon#flushed, iclass 35, count 2 2006.168.08:25:49.36#ibcon#about to write, iclass 35, count 2 2006.168.08:25:49.36#ibcon#wrote, iclass 35, count 2 2006.168.08:25:49.36#ibcon#about to read 3, iclass 35, count 2 2006.168.08:25:49.39#ibcon#read 3, iclass 35, count 2 2006.168.08:25:49.39#ibcon#about to read 4, iclass 35, count 2 2006.168.08:25:49.39#ibcon#read 4, iclass 35, count 2 2006.168.08:25:49.39#ibcon#about to read 5, iclass 35, count 2 2006.168.08:25:49.39#ibcon#read 5, iclass 35, count 2 2006.168.08:25:49.39#ibcon#about to read 6, iclass 35, count 2 2006.168.08:25:49.39#ibcon#read 6, iclass 35, count 2 2006.168.08:25:49.39#ibcon#end of sib2, iclass 35, count 2 2006.168.08:25:49.39#ibcon#*after write, iclass 35, count 2 2006.168.08:25:49.39#ibcon#*before return 0, iclass 35, count 2 2006.168.08:25:49.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.168.08:25:49.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.168.08:25:49.39#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.168.08:25:49.39#ibcon#ireg 7 cls_cnt 0 2006.168.08:25:49.39#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.168.08:25:49.52#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.168.08:25:49.52#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.168.08:25:49.52#ibcon#enter wrdev, iclass 35, count 0 2006.168.08:25:49.52#ibcon#first serial, iclass 35, count 0 2006.168.08:25:49.52#ibcon#enter sib2, iclass 35, count 0 2006.168.08:25:49.52#ibcon#flushed, iclass 35, count 0 2006.168.08:25:49.52#ibcon#about to write, iclass 35, count 0 2006.168.08:25:49.52#ibcon#wrote, iclass 35, count 0 2006.168.08:25:49.52#ibcon#about to read 3, iclass 35, count 0 2006.168.08:25:49.53#ibcon#read 3, iclass 35, count 0 2006.168.08:25:49.53#ibcon#about to read 4, iclass 35, count 0 2006.168.08:25:49.53#ibcon#read 4, iclass 35, count 0 2006.168.08:25:49.53#ibcon#about to read 5, iclass 35, count 0 2006.168.08:25:49.53#ibcon#read 5, iclass 35, count 0 2006.168.08:25:49.53#ibcon#about to read 6, iclass 35, count 0 2006.168.08:25:49.53#ibcon#read 6, iclass 35, count 0 2006.168.08:25:49.53#ibcon#end of sib2, iclass 35, count 0 2006.168.08:25:49.53#ibcon#*mode == 0, iclass 35, count 0 2006.168.08:25:49.53#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.168.08:25:49.53#ibcon#[25=USB\r\n] 2006.168.08:25:49.53#ibcon#*before write, iclass 35, count 0 2006.168.08:25:49.53#ibcon#enter sib2, iclass 35, count 0 2006.168.08:25:49.53#ibcon#flushed, iclass 35, count 0 2006.168.08:25:49.53#ibcon#about to write, iclass 35, count 0 2006.168.08:25:49.53#ibcon#wrote, iclass 35, count 0 2006.168.08:25:49.53#ibcon#about to read 3, iclass 35, count 0 2006.168.08:25:49.56#ibcon#read 3, iclass 35, count 0 2006.168.08:25:49.56#ibcon#about to read 4, iclass 35, count 0 2006.168.08:25:49.56#ibcon#read 4, iclass 35, count 0 2006.168.08:25:49.56#ibcon#about to read 5, iclass 35, count 0 2006.168.08:25:49.56#ibcon#read 5, iclass 35, count 0 2006.168.08:25:49.56#ibcon#about to read 6, iclass 35, count 0 2006.168.08:25:49.56#ibcon#read 6, iclass 35, count 0 2006.168.08:25:49.56#ibcon#end of sib2, iclass 35, count 0 2006.168.08:25:49.56#ibcon#*after write, iclass 35, count 0 2006.168.08:25:49.56#ibcon#*before return 0, iclass 35, count 0 2006.168.08:25:49.56#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.168.08:25:49.56#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.168.08:25:49.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.168.08:25:49.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.168.08:25:49.56$vc4f8/valo=6,772.99 2006.168.08:25:49.57#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.168.08:25:49.57#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.168.08:25:49.57#ibcon#ireg 17 cls_cnt 0 2006.168.08:25:49.57#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:25:49.57#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:25:49.57#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:25:49.57#ibcon#enter wrdev, iclass 37, count 0 2006.168.08:25:49.57#ibcon#first serial, iclass 37, count 0 2006.168.08:25:49.57#ibcon#enter sib2, iclass 37, count 0 2006.168.08:25:49.57#ibcon#flushed, iclass 37, count 0 2006.168.08:25:49.57#ibcon#about to write, iclass 37, count 0 2006.168.08:25:49.57#ibcon#wrote, iclass 37, count 0 2006.168.08:25:49.57#ibcon#about to read 3, iclass 37, count 0 2006.168.08:25:49.58#ibcon#read 3, iclass 37, count 0 2006.168.08:25:49.58#ibcon#about to read 4, iclass 37, count 0 2006.168.08:25:49.58#ibcon#read 4, iclass 37, count 0 2006.168.08:25:49.58#ibcon#about to read 5, iclass 37, count 0 2006.168.08:25:49.58#ibcon#read 5, iclass 37, count 0 2006.168.08:25:49.58#ibcon#about to read 6, iclass 37, count 0 2006.168.08:25:49.58#ibcon#read 6, iclass 37, count 0 2006.168.08:25:49.58#ibcon#end of sib2, iclass 37, count 0 2006.168.08:25:49.58#ibcon#*mode == 0, iclass 37, count 0 2006.168.08:25:49.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.168.08:25:49.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.08:25:49.58#ibcon#*before write, iclass 37, count 0 2006.168.08:25:49.58#ibcon#enter sib2, iclass 37, count 0 2006.168.08:25:49.58#ibcon#flushed, iclass 37, count 0 2006.168.08:25:49.58#ibcon#about to write, iclass 37, count 0 2006.168.08:25:49.58#ibcon#wrote, iclass 37, count 0 2006.168.08:25:49.58#ibcon#about to read 3, iclass 37, count 0 2006.168.08:25:49.62#ibcon#read 3, iclass 37, count 0 2006.168.08:25:49.62#ibcon#about to read 4, iclass 37, count 0 2006.168.08:25:49.62#ibcon#read 4, iclass 37, count 0 2006.168.08:25:49.62#ibcon#about to read 5, iclass 37, count 0 2006.168.08:25:49.62#ibcon#read 5, iclass 37, count 0 2006.168.08:25:49.62#ibcon#about to read 6, iclass 37, count 0 2006.168.08:25:49.62#ibcon#read 6, iclass 37, count 0 2006.168.08:25:49.62#ibcon#end of sib2, iclass 37, count 0 2006.168.08:25:49.62#ibcon#*after write, iclass 37, count 0 2006.168.08:25:49.62#ibcon#*before return 0, iclass 37, count 0 2006.168.08:25:49.62#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:25:49.62#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:25:49.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.168.08:25:49.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.168.08:25:49.62$vc4f8/va=6,6 2006.168.08:25:49.62#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.168.08:25:49.62#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.168.08:25:49.63#ibcon#ireg 11 cls_cnt 2 2006.168.08:25:49.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.168.08:25:49.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.168.08:25:49.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.168.08:25:49.67#ibcon#enter wrdev, iclass 39, count 2 2006.168.08:25:49.67#ibcon#first serial, iclass 39, count 2 2006.168.08:25:49.67#ibcon#enter sib2, iclass 39, count 2 2006.168.08:25:49.67#ibcon#flushed, iclass 39, count 2 2006.168.08:25:49.67#ibcon#about to write, iclass 39, count 2 2006.168.08:25:49.67#ibcon#wrote, iclass 39, count 2 2006.168.08:25:49.67#ibcon#about to read 3, iclass 39, count 2 2006.168.08:25:49.69#ibcon#read 3, iclass 39, count 2 2006.168.08:25:49.69#ibcon#about to read 4, iclass 39, count 2 2006.168.08:25:49.69#ibcon#read 4, iclass 39, count 2 2006.168.08:25:49.69#ibcon#about to read 5, iclass 39, count 2 2006.168.08:25:49.69#ibcon#read 5, iclass 39, count 2 2006.168.08:25:49.69#ibcon#about to read 6, iclass 39, count 2 2006.168.08:25:49.69#ibcon#read 6, iclass 39, count 2 2006.168.08:25:49.69#ibcon#end of sib2, iclass 39, count 2 2006.168.08:25:49.69#ibcon#*mode == 0, iclass 39, count 2 2006.168.08:25:49.69#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.168.08:25:49.69#ibcon#[25=AT06-06\r\n] 2006.168.08:25:49.69#ibcon#*before write, iclass 39, count 2 2006.168.08:25:49.69#ibcon#enter sib2, iclass 39, count 2 2006.168.08:25:49.69#ibcon#flushed, iclass 39, count 2 2006.168.08:25:49.69#ibcon#about to write, iclass 39, count 2 2006.168.08:25:49.69#ibcon#wrote, iclass 39, count 2 2006.168.08:25:49.69#ibcon#about to read 3, iclass 39, count 2 2006.168.08:25:49.72#ibcon#read 3, iclass 39, count 2 2006.168.08:25:49.72#ibcon#about to read 4, iclass 39, count 2 2006.168.08:25:49.72#ibcon#read 4, iclass 39, count 2 2006.168.08:25:49.72#ibcon#about to read 5, iclass 39, count 2 2006.168.08:25:49.72#ibcon#read 5, iclass 39, count 2 2006.168.08:25:49.72#ibcon#about to read 6, iclass 39, count 2 2006.168.08:25:49.72#ibcon#read 6, iclass 39, count 2 2006.168.08:25:49.72#ibcon#end of sib2, iclass 39, count 2 2006.168.08:25:49.72#ibcon#*after write, iclass 39, count 2 2006.168.08:25:49.72#ibcon#*before return 0, iclass 39, count 2 2006.168.08:25:49.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.168.08:25:49.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.168.08:25:49.72#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.168.08:25:49.72#ibcon#ireg 7 cls_cnt 0 2006.168.08:25:49.72#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.168.08:25:49.84#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.168.08:25:49.84#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.168.08:25:49.84#ibcon#enter wrdev, iclass 39, count 0 2006.168.08:25:49.84#ibcon#first serial, iclass 39, count 0 2006.168.08:25:49.84#ibcon#enter sib2, iclass 39, count 0 2006.168.08:25:49.84#ibcon#flushed, iclass 39, count 0 2006.168.08:25:49.84#ibcon#about to write, iclass 39, count 0 2006.168.08:25:49.84#ibcon#wrote, iclass 39, count 0 2006.168.08:25:49.84#ibcon#about to read 3, iclass 39, count 0 2006.168.08:25:49.86#ibcon#read 3, iclass 39, count 0 2006.168.08:25:49.86#ibcon#about to read 4, iclass 39, count 0 2006.168.08:25:49.86#ibcon#read 4, iclass 39, count 0 2006.168.08:25:49.86#ibcon#about to read 5, iclass 39, count 0 2006.168.08:25:49.86#ibcon#read 5, iclass 39, count 0 2006.168.08:25:49.86#ibcon#about to read 6, iclass 39, count 0 2006.168.08:25:49.86#ibcon#read 6, iclass 39, count 0 2006.168.08:25:49.86#ibcon#end of sib2, iclass 39, count 0 2006.168.08:25:49.86#ibcon#*mode == 0, iclass 39, count 0 2006.168.08:25:49.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.168.08:25:49.86#ibcon#[25=USB\r\n] 2006.168.08:25:49.86#ibcon#*before write, iclass 39, count 0 2006.168.08:25:49.86#ibcon#enter sib2, iclass 39, count 0 2006.168.08:25:49.86#ibcon#flushed, iclass 39, count 0 2006.168.08:25:49.86#ibcon#about to write, iclass 39, count 0 2006.168.08:25:49.86#ibcon#wrote, iclass 39, count 0 2006.168.08:25:49.86#ibcon#about to read 3, iclass 39, count 0 2006.168.08:25:49.89#ibcon#read 3, iclass 39, count 0 2006.168.08:25:49.89#ibcon#about to read 4, iclass 39, count 0 2006.168.08:25:49.89#ibcon#read 4, iclass 39, count 0 2006.168.08:25:49.89#ibcon#about to read 5, iclass 39, count 0 2006.168.08:25:49.89#ibcon#read 5, iclass 39, count 0 2006.168.08:25:49.89#ibcon#about to read 6, iclass 39, count 0 2006.168.08:25:49.89#ibcon#read 6, iclass 39, count 0 2006.168.08:25:49.89#ibcon#end of sib2, iclass 39, count 0 2006.168.08:25:49.89#ibcon#*after write, iclass 39, count 0 2006.168.08:25:49.89#ibcon#*before return 0, iclass 39, count 0 2006.168.08:25:49.89#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.168.08:25:49.89#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.168.08:25:49.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.168.08:25:49.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.168.08:25:49.89$vc4f8/valo=7,832.99 2006.168.08:25:49.90#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.168.08:25:49.90#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.168.08:25:49.90#ibcon#ireg 17 cls_cnt 0 2006.168.08:25:49.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.168.08:25:49.90#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.168.08:25:49.90#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.168.08:25:49.90#ibcon#enter wrdev, iclass 3, count 0 2006.168.08:25:49.90#ibcon#first serial, iclass 3, count 0 2006.168.08:25:49.90#ibcon#enter sib2, iclass 3, count 0 2006.168.08:25:49.90#ibcon#flushed, iclass 3, count 0 2006.168.08:25:49.90#ibcon#about to write, iclass 3, count 0 2006.168.08:25:49.90#ibcon#wrote, iclass 3, count 0 2006.168.08:25:49.90#ibcon#about to read 3, iclass 3, count 0 2006.168.08:25:49.91#ibcon#read 3, iclass 3, count 0 2006.168.08:25:49.91#ibcon#about to read 4, iclass 3, count 0 2006.168.08:25:49.91#ibcon#read 4, iclass 3, count 0 2006.168.08:25:49.91#ibcon#about to read 5, iclass 3, count 0 2006.168.08:25:49.91#ibcon#read 5, iclass 3, count 0 2006.168.08:25:49.91#ibcon#about to read 6, iclass 3, count 0 2006.168.08:25:49.91#ibcon#read 6, iclass 3, count 0 2006.168.08:25:49.91#ibcon#end of sib2, iclass 3, count 0 2006.168.08:25:49.91#ibcon#*mode == 0, iclass 3, count 0 2006.168.08:25:49.91#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.168.08:25:49.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.08:25:49.91#ibcon#*before write, iclass 3, count 0 2006.168.08:25:49.91#ibcon#enter sib2, iclass 3, count 0 2006.168.08:25:49.91#ibcon#flushed, iclass 3, count 0 2006.168.08:25:49.91#ibcon#about to write, iclass 3, count 0 2006.168.08:25:49.91#ibcon#wrote, iclass 3, count 0 2006.168.08:25:49.91#ibcon#about to read 3, iclass 3, count 0 2006.168.08:25:49.95#ibcon#read 3, iclass 3, count 0 2006.168.08:25:49.95#ibcon#about to read 4, iclass 3, count 0 2006.168.08:25:49.95#ibcon#read 4, iclass 3, count 0 2006.168.08:25:49.95#ibcon#about to read 5, iclass 3, count 0 2006.168.08:25:49.95#ibcon#read 5, iclass 3, count 0 2006.168.08:25:49.95#ibcon#about to read 6, iclass 3, count 0 2006.168.08:25:49.95#ibcon#read 6, iclass 3, count 0 2006.168.08:25:49.95#ibcon#end of sib2, iclass 3, count 0 2006.168.08:25:49.95#ibcon#*after write, iclass 3, count 0 2006.168.08:25:49.95#ibcon#*before return 0, iclass 3, count 0 2006.168.08:25:49.95#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.168.08:25:49.95#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.168.08:25:49.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.168.08:25:49.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.168.08:25:49.95$vc4f8/va=7,6 2006.168.08:25:49.95#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.168.08:25:49.96#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.168.08:25:49.96#ibcon#ireg 11 cls_cnt 2 2006.168.08:25:49.96#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.168.08:25:50.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.168.08:25:50.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.168.08:25:50.00#ibcon#enter wrdev, iclass 5, count 2 2006.168.08:25:50.00#ibcon#first serial, iclass 5, count 2 2006.168.08:25:50.00#ibcon#enter sib2, iclass 5, count 2 2006.168.08:25:50.00#ibcon#flushed, iclass 5, count 2 2006.168.08:25:50.00#ibcon#about to write, iclass 5, count 2 2006.168.08:25:50.00#ibcon#wrote, iclass 5, count 2 2006.168.08:25:50.00#ibcon#about to read 3, iclass 5, count 2 2006.168.08:25:50.02#ibcon#read 3, iclass 5, count 2 2006.168.08:25:50.02#ibcon#about to read 4, iclass 5, count 2 2006.168.08:25:50.02#ibcon#read 4, iclass 5, count 2 2006.168.08:25:50.02#ibcon#about to read 5, iclass 5, count 2 2006.168.08:25:50.02#ibcon#read 5, iclass 5, count 2 2006.168.08:25:50.02#ibcon#about to read 6, iclass 5, count 2 2006.168.08:25:50.02#ibcon#read 6, iclass 5, count 2 2006.168.08:25:50.02#ibcon#end of sib2, iclass 5, count 2 2006.168.08:25:50.02#ibcon#*mode == 0, iclass 5, count 2 2006.168.08:25:50.02#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.168.08:25:50.02#ibcon#[25=AT07-06\r\n] 2006.168.08:25:50.02#ibcon#*before write, iclass 5, count 2 2006.168.08:25:50.02#ibcon#enter sib2, iclass 5, count 2 2006.168.08:25:50.02#ibcon#flushed, iclass 5, count 2 2006.168.08:25:50.02#ibcon#about to write, iclass 5, count 2 2006.168.08:25:50.02#ibcon#wrote, iclass 5, count 2 2006.168.08:25:50.02#ibcon#about to read 3, iclass 5, count 2 2006.168.08:25:50.05#ibcon#read 3, iclass 5, count 2 2006.168.08:25:50.05#ibcon#about to read 4, iclass 5, count 2 2006.168.08:25:50.05#ibcon#read 4, iclass 5, count 2 2006.168.08:25:50.05#ibcon#about to read 5, iclass 5, count 2 2006.168.08:25:50.05#ibcon#read 5, iclass 5, count 2 2006.168.08:25:50.05#ibcon#about to read 6, iclass 5, count 2 2006.168.08:25:50.05#ibcon#read 6, iclass 5, count 2 2006.168.08:25:50.05#ibcon#end of sib2, iclass 5, count 2 2006.168.08:25:50.05#ibcon#*after write, iclass 5, count 2 2006.168.08:25:50.05#ibcon#*before return 0, iclass 5, count 2 2006.168.08:25:50.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.168.08:25:50.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.168.08:25:50.05#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.168.08:25:50.05#ibcon#ireg 7 cls_cnt 0 2006.168.08:25:50.05#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.168.08:25:50.17#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.168.08:25:50.17#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.168.08:25:50.17#ibcon#enter wrdev, iclass 5, count 0 2006.168.08:25:50.17#ibcon#first serial, iclass 5, count 0 2006.168.08:25:50.17#ibcon#enter sib2, iclass 5, count 0 2006.168.08:25:50.17#ibcon#flushed, iclass 5, count 0 2006.168.08:25:50.17#ibcon#about to write, iclass 5, count 0 2006.168.08:25:50.17#ibcon#wrote, iclass 5, count 0 2006.168.08:25:50.17#ibcon#about to read 3, iclass 5, count 0 2006.168.08:25:50.19#ibcon#read 3, iclass 5, count 0 2006.168.08:25:50.19#ibcon#about to read 4, iclass 5, count 0 2006.168.08:25:50.19#ibcon#read 4, iclass 5, count 0 2006.168.08:25:50.19#ibcon#about to read 5, iclass 5, count 0 2006.168.08:25:50.19#ibcon#read 5, iclass 5, count 0 2006.168.08:25:50.19#ibcon#about to read 6, iclass 5, count 0 2006.168.08:25:50.19#ibcon#read 6, iclass 5, count 0 2006.168.08:25:50.19#ibcon#end of sib2, iclass 5, count 0 2006.168.08:25:50.19#ibcon#*mode == 0, iclass 5, count 0 2006.168.08:25:50.19#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.168.08:25:50.19#ibcon#[25=USB\r\n] 2006.168.08:25:50.19#ibcon#*before write, iclass 5, count 0 2006.168.08:25:50.19#ibcon#enter sib2, iclass 5, count 0 2006.168.08:25:50.19#ibcon#flushed, iclass 5, count 0 2006.168.08:25:50.19#ibcon#about to write, iclass 5, count 0 2006.168.08:25:50.19#ibcon#wrote, iclass 5, count 0 2006.168.08:25:50.19#ibcon#about to read 3, iclass 5, count 0 2006.168.08:25:50.22#ibcon#read 3, iclass 5, count 0 2006.168.08:25:50.22#ibcon#about to read 4, iclass 5, count 0 2006.168.08:25:50.22#ibcon#read 4, iclass 5, count 0 2006.168.08:25:50.22#ibcon#about to read 5, iclass 5, count 0 2006.168.08:25:50.22#ibcon#read 5, iclass 5, count 0 2006.168.08:25:50.22#ibcon#about to read 6, iclass 5, count 0 2006.168.08:25:50.22#ibcon#read 6, iclass 5, count 0 2006.168.08:25:50.22#ibcon#end of sib2, iclass 5, count 0 2006.168.08:25:50.22#ibcon#*after write, iclass 5, count 0 2006.168.08:25:50.22#ibcon#*before return 0, iclass 5, count 0 2006.168.08:25:50.22#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.168.08:25:50.22#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.168.08:25:50.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.168.08:25:50.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.168.08:25:50.22$vc4f8/valo=8,852.99 2006.168.08:25:50.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.168.08:25:50.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.168.08:25:50.23#ibcon#ireg 17 cls_cnt 0 2006.168.08:25:50.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.168.08:25:50.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.168.08:25:50.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.168.08:25:50.23#ibcon#enter wrdev, iclass 7, count 0 2006.168.08:25:50.23#ibcon#first serial, iclass 7, count 0 2006.168.08:25:50.23#ibcon#enter sib2, iclass 7, count 0 2006.168.08:25:50.23#ibcon#flushed, iclass 7, count 0 2006.168.08:25:50.23#ibcon#about to write, iclass 7, count 0 2006.168.08:25:50.23#ibcon#wrote, iclass 7, count 0 2006.168.08:25:50.23#ibcon#about to read 3, iclass 7, count 0 2006.168.08:25:50.25#ibcon#read 3, iclass 7, count 0 2006.168.08:25:50.25#ibcon#about to read 4, iclass 7, count 0 2006.168.08:25:50.25#ibcon#read 4, iclass 7, count 0 2006.168.08:25:50.25#ibcon#about to read 5, iclass 7, count 0 2006.168.08:25:50.25#ibcon#read 5, iclass 7, count 0 2006.168.08:25:50.25#ibcon#about to read 6, iclass 7, count 0 2006.168.08:25:50.25#ibcon#read 6, iclass 7, count 0 2006.168.08:25:50.25#ibcon#end of sib2, iclass 7, count 0 2006.168.08:25:50.25#ibcon#*mode == 0, iclass 7, count 0 2006.168.08:25:50.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.168.08:25:50.25#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.08:25:50.25#ibcon#*before write, iclass 7, count 0 2006.168.08:25:50.25#ibcon#enter sib2, iclass 7, count 0 2006.168.08:25:50.25#ibcon#flushed, iclass 7, count 0 2006.168.08:25:50.25#ibcon#about to write, iclass 7, count 0 2006.168.08:25:50.25#ibcon#wrote, iclass 7, count 0 2006.168.08:25:50.25#ibcon#about to read 3, iclass 7, count 0 2006.168.08:25:50.28#ibcon#read 3, iclass 7, count 0 2006.168.08:25:50.28#ibcon#about to read 4, iclass 7, count 0 2006.168.08:25:50.28#ibcon#read 4, iclass 7, count 0 2006.168.08:25:50.28#ibcon#about to read 5, iclass 7, count 0 2006.168.08:25:50.28#ibcon#read 5, iclass 7, count 0 2006.168.08:25:50.28#ibcon#about to read 6, iclass 7, count 0 2006.168.08:25:50.28#ibcon#read 6, iclass 7, count 0 2006.168.08:25:50.28#ibcon#end of sib2, iclass 7, count 0 2006.168.08:25:50.28#ibcon#*after write, iclass 7, count 0 2006.168.08:25:50.28#ibcon#*before return 0, iclass 7, count 0 2006.168.08:25:50.28#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.168.08:25:50.28#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.168.08:25:50.28#ibcon#about to clear, iclass 7 cls_cnt 0 2006.168.08:25:50.28#ibcon#cleared, iclass 7 cls_cnt 0 2006.168.08:25:50.28$vc4f8/va=8,7 2006.168.08:25:50.29#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.168.08:25:50.29#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.168.08:25:50.29#ibcon#ireg 11 cls_cnt 2 2006.168.08:25:50.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.168.08:25:50.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.168.08:25:50.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.168.08:25:50.34#ibcon#enter wrdev, iclass 11, count 2 2006.168.08:25:50.34#ibcon#first serial, iclass 11, count 2 2006.168.08:25:50.34#ibcon#enter sib2, iclass 11, count 2 2006.168.08:25:50.34#ibcon#flushed, iclass 11, count 2 2006.168.08:25:50.34#ibcon#about to write, iclass 11, count 2 2006.168.08:25:50.34#ibcon#wrote, iclass 11, count 2 2006.168.08:25:50.34#ibcon#about to read 3, iclass 11, count 2 2006.168.08:25:50.35#ibcon#read 3, iclass 11, count 2 2006.168.08:25:50.35#ibcon#about to read 4, iclass 11, count 2 2006.168.08:25:50.35#ibcon#read 4, iclass 11, count 2 2006.168.08:25:50.35#ibcon#about to read 5, iclass 11, count 2 2006.168.08:25:50.35#ibcon#read 5, iclass 11, count 2 2006.168.08:25:50.35#ibcon#about to read 6, iclass 11, count 2 2006.168.08:25:50.35#ibcon#read 6, iclass 11, count 2 2006.168.08:25:50.35#ibcon#end of sib2, iclass 11, count 2 2006.168.08:25:50.35#ibcon#*mode == 0, iclass 11, count 2 2006.168.08:25:50.35#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.168.08:25:50.35#ibcon#[25=AT08-07\r\n] 2006.168.08:25:50.35#ibcon#*before write, iclass 11, count 2 2006.168.08:25:50.35#ibcon#enter sib2, iclass 11, count 2 2006.168.08:25:50.35#ibcon#flushed, iclass 11, count 2 2006.168.08:25:50.35#ibcon#about to write, iclass 11, count 2 2006.168.08:25:50.35#ibcon#wrote, iclass 11, count 2 2006.168.08:25:50.35#ibcon#about to read 3, iclass 11, count 2 2006.168.08:25:50.38#ibcon#read 3, iclass 11, count 2 2006.168.08:25:50.38#ibcon#about to read 4, iclass 11, count 2 2006.168.08:25:50.38#ibcon#read 4, iclass 11, count 2 2006.168.08:25:50.38#ibcon#about to read 5, iclass 11, count 2 2006.168.08:25:50.38#ibcon#read 5, iclass 11, count 2 2006.168.08:25:50.38#ibcon#about to read 6, iclass 11, count 2 2006.168.08:25:50.38#ibcon#read 6, iclass 11, count 2 2006.168.08:25:50.38#ibcon#end of sib2, iclass 11, count 2 2006.168.08:25:50.38#ibcon#*after write, iclass 11, count 2 2006.168.08:25:50.38#ibcon#*before return 0, iclass 11, count 2 2006.168.08:25:50.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.168.08:25:50.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.168.08:25:50.38#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.168.08:25:50.38#ibcon#ireg 7 cls_cnt 0 2006.168.08:25:50.38#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.168.08:25:50.50#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.168.08:25:50.50#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.168.08:25:50.50#ibcon#enter wrdev, iclass 11, count 0 2006.168.08:25:50.50#ibcon#first serial, iclass 11, count 0 2006.168.08:25:50.50#ibcon#enter sib2, iclass 11, count 0 2006.168.08:25:50.50#ibcon#flushed, iclass 11, count 0 2006.168.08:25:50.50#ibcon#about to write, iclass 11, count 0 2006.168.08:25:50.50#ibcon#wrote, iclass 11, count 0 2006.168.08:25:50.50#ibcon#about to read 3, iclass 11, count 0 2006.168.08:25:50.52#ibcon#read 3, iclass 11, count 0 2006.168.08:25:50.52#ibcon#about to read 4, iclass 11, count 0 2006.168.08:25:50.52#ibcon#read 4, iclass 11, count 0 2006.168.08:25:50.52#ibcon#about to read 5, iclass 11, count 0 2006.168.08:25:50.52#ibcon#read 5, iclass 11, count 0 2006.168.08:25:50.52#ibcon#about to read 6, iclass 11, count 0 2006.168.08:25:50.52#ibcon#read 6, iclass 11, count 0 2006.168.08:25:50.52#ibcon#end of sib2, iclass 11, count 0 2006.168.08:25:50.52#ibcon#*mode == 0, iclass 11, count 0 2006.168.08:25:50.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.168.08:25:50.52#ibcon#[25=USB\r\n] 2006.168.08:25:50.52#ibcon#*before write, iclass 11, count 0 2006.168.08:25:50.52#ibcon#enter sib2, iclass 11, count 0 2006.168.08:25:50.52#ibcon#flushed, iclass 11, count 0 2006.168.08:25:50.52#ibcon#about to write, iclass 11, count 0 2006.168.08:25:50.52#ibcon#wrote, iclass 11, count 0 2006.168.08:25:50.52#ibcon#about to read 3, iclass 11, count 0 2006.168.08:25:50.55#ibcon#read 3, iclass 11, count 0 2006.168.08:25:50.55#ibcon#about to read 4, iclass 11, count 0 2006.168.08:25:50.55#ibcon#read 4, iclass 11, count 0 2006.168.08:25:50.55#ibcon#about to read 5, iclass 11, count 0 2006.168.08:25:50.55#ibcon#read 5, iclass 11, count 0 2006.168.08:25:50.55#ibcon#about to read 6, iclass 11, count 0 2006.168.08:25:50.55#ibcon#read 6, iclass 11, count 0 2006.168.08:25:50.55#ibcon#end of sib2, iclass 11, count 0 2006.168.08:25:50.55#ibcon#*after write, iclass 11, count 0 2006.168.08:25:50.55#ibcon#*before return 0, iclass 11, count 0 2006.168.08:25:50.55#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.168.08:25:50.55#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.168.08:25:50.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.168.08:25:50.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.168.08:25:50.55$vc4f8/vblo=1,632.99 2006.168.08:25:50.56#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.168.08:25:50.56#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.168.08:25:50.56#ibcon#ireg 17 cls_cnt 0 2006.168.08:25:50.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.168.08:25:50.56#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.168.08:25:50.56#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.168.08:25:50.56#ibcon#enter wrdev, iclass 13, count 0 2006.168.08:25:50.56#ibcon#first serial, iclass 13, count 0 2006.168.08:25:50.56#ibcon#enter sib2, iclass 13, count 0 2006.168.08:25:50.56#ibcon#flushed, iclass 13, count 0 2006.168.08:25:50.56#ibcon#about to write, iclass 13, count 0 2006.168.08:25:50.56#ibcon#wrote, iclass 13, count 0 2006.168.08:25:50.56#ibcon#about to read 3, iclass 13, count 0 2006.168.08:25:50.57#ibcon#read 3, iclass 13, count 0 2006.168.08:25:50.57#ibcon#about to read 4, iclass 13, count 0 2006.168.08:25:50.57#ibcon#read 4, iclass 13, count 0 2006.168.08:25:50.57#ibcon#about to read 5, iclass 13, count 0 2006.168.08:25:50.57#ibcon#read 5, iclass 13, count 0 2006.168.08:25:50.57#ibcon#about to read 6, iclass 13, count 0 2006.168.08:25:50.57#ibcon#read 6, iclass 13, count 0 2006.168.08:25:50.57#ibcon#end of sib2, iclass 13, count 0 2006.168.08:25:50.57#ibcon#*mode == 0, iclass 13, count 0 2006.168.08:25:50.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.168.08:25:50.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.08:25:50.57#ibcon#*before write, iclass 13, count 0 2006.168.08:25:50.57#ibcon#enter sib2, iclass 13, count 0 2006.168.08:25:50.57#ibcon#flushed, iclass 13, count 0 2006.168.08:25:50.57#ibcon#about to write, iclass 13, count 0 2006.168.08:25:50.57#ibcon#wrote, iclass 13, count 0 2006.168.08:25:50.57#ibcon#about to read 3, iclass 13, count 0 2006.168.08:25:50.61#ibcon#read 3, iclass 13, count 0 2006.168.08:25:50.61#ibcon#about to read 4, iclass 13, count 0 2006.168.08:25:50.61#ibcon#read 4, iclass 13, count 0 2006.168.08:25:50.61#ibcon#about to read 5, iclass 13, count 0 2006.168.08:25:50.61#ibcon#read 5, iclass 13, count 0 2006.168.08:25:50.61#ibcon#about to read 6, iclass 13, count 0 2006.168.08:25:50.61#ibcon#read 6, iclass 13, count 0 2006.168.08:25:50.61#ibcon#end of sib2, iclass 13, count 0 2006.168.08:25:50.61#ibcon#*after write, iclass 13, count 0 2006.168.08:25:50.61#ibcon#*before return 0, iclass 13, count 0 2006.168.08:25:50.61#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.168.08:25:50.61#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.168.08:25:50.61#ibcon#about to clear, iclass 13 cls_cnt 0 2006.168.08:25:50.61#ibcon#cleared, iclass 13 cls_cnt 0 2006.168.08:25:50.61$vc4f8/vb=1,4 2006.168.08:25:50.61#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.168.08:25:50.61#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.168.08:25:50.62#ibcon#ireg 11 cls_cnt 2 2006.168.08:25:50.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.168.08:25:50.62#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.168.08:25:50.62#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.168.08:25:50.62#ibcon#enter wrdev, iclass 15, count 2 2006.168.08:25:50.62#ibcon#first serial, iclass 15, count 2 2006.168.08:25:50.62#ibcon#enter sib2, iclass 15, count 2 2006.168.08:25:50.62#ibcon#flushed, iclass 15, count 2 2006.168.08:25:50.62#ibcon#about to write, iclass 15, count 2 2006.168.08:25:50.62#ibcon#wrote, iclass 15, count 2 2006.168.08:25:50.62#ibcon#about to read 3, iclass 15, count 2 2006.168.08:25:50.63#ibcon#read 3, iclass 15, count 2 2006.168.08:25:50.63#ibcon#about to read 4, iclass 15, count 2 2006.168.08:25:50.63#ibcon#read 4, iclass 15, count 2 2006.168.08:25:50.63#ibcon#about to read 5, iclass 15, count 2 2006.168.08:25:50.63#ibcon#read 5, iclass 15, count 2 2006.168.08:25:50.63#ibcon#about to read 6, iclass 15, count 2 2006.168.08:25:50.63#ibcon#read 6, iclass 15, count 2 2006.168.08:25:50.63#ibcon#end of sib2, iclass 15, count 2 2006.168.08:25:50.63#ibcon#*mode == 0, iclass 15, count 2 2006.168.08:25:50.63#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.168.08:25:50.63#ibcon#[27=AT01-04\r\n] 2006.168.08:25:50.63#ibcon#*before write, iclass 15, count 2 2006.168.08:25:50.63#ibcon#enter sib2, iclass 15, count 2 2006.168.08:25:50.63#ibcon#flushed, iclass 15, count 2 2006.168.08:25:50.63#ibcon#about to write, iclass 15, count 2 2006.168.08:25:50.63#ibcon#wrote, iclass 15, count 2 2006.168.08:25:50.63#ibcon#about to read 3, iclass 15, count 2 2006.168.08:25:50.66#ibcon#read 3, iclass 15, count 2 2006.168.08:25:50.66#ibcon#about to read 4, iclass 15, count 2 2006.168.08:25:50.66#ibcon#read 4, iclass 15, count 2 2006.168.08:25:50.66#ibcon#about to read 5, iclass 15, count 2 2006.168.08:25:50.66#ibcon#read 5, iclass 15, count 2 2006.168.08:25:50.66#ibcon#about to read 6, iclass 15, count 2 2006.168.08:25:50.66#ibcon#read 6, iclass 15, count 2 2006.168.08:25:50.66#ibcon#end of sib2, iclass 15, count 2 2006.168.08:25:50.66#ibcon#*after write, iclass 15, count 2 2006.168.08:25:50.66#ibcon#*before return 0, iclass 15, count 2 2006.168.08:25:50.66#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.168.08:25:50.66#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.168.08:25:50.66#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.168.08:25:50.66#ibcon#ireg 7 cls_cnt 0 2006.168.08:25:50.66#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.168.08:25:50.78#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.168.08:25:50.78#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.168.08:25:50.78#ibcon#enter wrdev, iclass 15, count 0 2006.168.08:25:50.78#ibcon#first serial, iclass 15, count 0 2006.168.08:25:50.78#ibcon#enter sib2, iclass 15, count 0 2006.168.08:25:50.78#ibcon#flushed, iclass 15, count 0 2006.168.08:25:50.78#ibcon#about to write, iclass 15, count 0 2006.168.08:25:50.78#ibcon#wrote, iclass 15, count 0 2006.168.08:25:50.78#ibcon#about to read 3, iclass 15, count 0 2006.168.08:25:50.80#ibcon#read 3, iclass 15, count 0 2006.168.08:25:50.80#ibcon#about to read 4, iclass 15, count 0 2006.168.08:25:50.80#ibcon#read 4, iclass 15, count 0 2006.168.08:25:50.80#ibcon#about to read 5, iclass 15, count 0 2006.168.08:25:50.80#ibcon#read 5, iclass 15, count 0 2006.168.08:25:50.80#ibcon#about to read 6, iclass 15, count 0 2006.168.08:25:50.80#ibcon#read 6, iclass 15, count 0 2006.168.08:25:50.80#ibcon#end of sib2, iclass 15, count 0 2006.168.08:25:50.80#ibcon#*mode == 0, iclass 15, count 0 2006.168.08:25:50.80#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.168.08:25:50.80#ibcon#[27=USB\r\n] 2006.168.08:25:50.80#ibcon#*before write, iclass 15, count 0 2006.168.08:25:50.80#ibcon#enter sib2, iclass 15, count 0 2006.168.08:25:50.80#ibcon#flushed, iclass 15, count 0 2006.168.08:25:50.80#ibcon#about to write, iclass 15, count 0 2006.168.08:25:50.80#ibcon#wrote, iclass 15, count 0 2006.168.08:25:50.80#ibcon#about to read 3, iclass 15, count 0 2006.168.08:25:50.83#ibcon#read 3, iclass 15, count 0 2006.168.08:25:50.83#ibcon#about to read 4, iclass 15, count 0 2006.168.08:25:50.83#ibcon#read 4, iclass 15, count 0 2006.168.08:25:50.83#ibcon#about to read 5, iclass 15, count 0 2006.168.08:25:50.83#ibcon#read 5, iclass 15, count 0 2006.168.08:25:50.83#ibcon#about to read 6, iclass 15, count 0 2006.168.08:25:50.83#ibcon#read 6, iclass 15, count 0 2006.168.08:25:50.83#ibcon#end of sib2, iclass 15, count 0 2006.168.08:25:50.83#ibcon#*after write, iclass 15, count 0 2006.168.08:25:50.83#ibcon#*before return 0, iclass 15, count 0 2006.168.08:25:50.83#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.168.08:25:50.83#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.168.08:25:50.83#ibcon#about to clear, iclass 15 cls_cnt 0 2006.168.08:25:50.83#ibcon#cleared, iclass 15 cls_cnt 0 2006.168.08:25:50.83$vc4f8/vblo=2,640.99 2006.168.08:25:50.84#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.168.08:25:50.84#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.168.08:25:50.84#ibcon#ireg 17 cls_cnt 0 2006.168.08:25:50.84#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:25:50.84#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:25:50.84#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:25:50.84#ibcon#enter wrdev, iclass 17, count 0 2006.168.08:25:50.84#ibcon#first serial, iclass 17, count 0 2006.168.08:25:50.84#ibcon#enter sib2, iclass 17, count 0 2006.168.08:25:50.84#ibcon#flushed, iclass 17, count 0 2006.168.08:25:50.84#ibcon#about to write, iclass 17, count 0 2006.168.08:25:50.84#ibcon#wrote, iclass 17, count 0 2006.168.08:25:50.84#ibcon#about to read 3, iclass 17, count 0 2006.168.08:25:50.85#ibcon#read 3, iclass 17, count 0 2006.168.08:25:50.85#ibcon#about to read 4, iclass 17, count 0 2006.168.08:25:50.85#ibcon#read 4, iclass 17, count 0 2006.168.08:25:50.85#ibcon#about to read 5, iclass 17, count 0 2006.168.08:25:50.85#ibcon#read 5, iclass 17, count 0 2006.168.08:25:50.85#ibcon#about to read 6, iclass 17, count 0 2006.168.08:25:50.85#ibcon#read 6, iclass 17, count 0 2006.168.08:25:50.85#ibcon#end of sib2, iclass 17, count 0 2006.168.08:25:50.85#ibcon#*mode == 0, iclass 17, count 0 2006.168.08:25:50.85#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.168.08:25:50.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.08:25:50.85#ibcon#*before write, iclass 17, count 0 2006.168.08:25:50.85#ibcon#enter sib2, iclass 17, count 0 2006.168.08:25:50.85#ibcon#flushed, iclass 17, count 0 2006.168.08:25:50.85#ibcon#about to write, iclass 17, count 0 2006.168.08:25:50.85#ibcon#wrote, iclass 17, count 0 2006.168.08:25:50.85#ibcon#about to read 3, iclass 17, count 0 2006.168.08:25:50.89#ibcon#read 3, iclass 17, count 0 2006.168.08:25:50.89#ibcon#about to read 4, iclass 17, count 0 2006.168.08:25:50.89#ibcon#read 4, iclass 17, count 0 2006.168.08:25:50.89#ibcon#about to read 5, iclass 17, count 0 2006.168.08:25:50.89#ibcon#read 5, iclass 17, count 0 2006.168.08:25:50.89#ibcon#about to read 6, iclass 17, count 0 2006.168.08:25:50.89#ibcon#read 6, iclass 17, count 0 2006.168.08:25:50.89#ibcon#end of sib2, iclass 17, count 0 2006.168.08:25:50.89#ibcon#*after write, iclass 17, count 0 2006.168.08:25:50.89#ibcon#*before return 0, iclass 17, count 0 2006.168.08:25:50.89#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:25:50.89#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.168.08:25:50.89#ibcon#about to clear, iclass 17 cls_cnt 0 2006.168.08:25:50.89#ibcon#cleared, iclass 17 cls_cnt 0 2006.168.08:25:50.89$vc4f8/vb=2,4 2006.168.08:25:50.89#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.168.08:25:50.90#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.168.08:25:50.90#ibcon#ireg 11 cls_cnt 2 2006.168.08:25:50.90#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:25:50.94#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:25:50.94#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:25:50.94#ibcon#enter wrdev, iclass 19, count 2 2006.168.08:25:50.94#ibcon#first serial, iclass 19, count 2 2006.168.08:25:50.94#ibcon#enter sib2, iclass 19, count 2 2006.168.08:25:50.94#ibcon#flushed, iclass 19, count 2 2006.168.08:25:50.94#ibcon#about to write, iclass 19, count 2 2006.168.08:25:50.94#ibcon#wrote, iclass 19, count 2 2006.168.08:25:50.94#ibcon#about to read 3, iclass 19, count 2 2006.168.08:25:50.96#ibcon#read 3, iclass 19, count 2 2006.168.08:25:50.96#ibcon#about to read 4, iclass 19, count 2 2006.168.08:25:50.96#ibcon#read 4, iclass 19, count 2 2006.168.08:25:50.96#ibcon#about to read 5, iclass 19, count 2 2006.168.08:25:50.96#ibcon#read 5, iclass 19, count 2 2006.168.08:25:50.96#ibcon#about to read 6, iclass 19, count 2 2006.168.08:25:50.96#ibcon#read 6, iclass 19, count 2 2006.168.08:25:50.96#ibcon#end of sib2, iclass 19, count 2 2006.168.08:25:50.96#ibcon#*mode == 0, iclass 19, count 2 2006.168.08:25:50.96#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.168.08:25:50.96#ibcon#[27=AT02-04\r\n] 2006.168.08:25:50.96#ibcon#*before write, iclass 19, count 2 2006.168.08:25:50.96#ibcon#enter sib2, iclass 19, count 2 2006.168.08:25:50.96#ibcon#flushed, iclass 19, count 2 2006.168.08:25:50.96#ibcon#about to write, iclass 19, count 2 2006.168.08:25:50.96#ibcon#wrote, iclass 19, count 2 2006.168.08:25:50.96#ibcon#about to read 3, iclass 19, count 2 2006.168.08:25:50.99#ibcon#read 3, iclass 19, count 2 2006.168.08:25:50.99#ibcon#about to read 4, iclass 19, count 2 2006.168.08:25:50.99#ibcon#read 4, iclass 19, count 2 2006.168.08:25:50.99#ibcon#about to read 5, iclass 19, count 2 2006.168.08:25:50.99#ibcon#read 5, iclass 19, count 2 2006.168.08:25:50.99#ibcon#about to read 6, iclass 19, count 2 2006.168.08:25:50.99#ibcon#read 6, iclass 19, count 2 2006.168.08:25:50.99#ibcon#end of sib2, iclass 19, count 2 2006.168.08:25:50.99#ibcon#*after write, iclass 19, count 2 2006.168.08:25:50.99#ibcon#*before return 0, iclass 19, count 2 2006.168.08:25:50.99#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:25:50.99#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:25:50.99#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.168.08:25:50.99#ibcon#ireg 7 cls_cnt 0 2006.168.08:25:50.99#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:25:51.11#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:25:51.11#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:25:51.11#ibcon#enter wrdev, iclass 19, count 0 2006.168.08:25:51.11#ibcon#first serial, iclass 19, count 0 2006.168.08:25:51.11#ibcon#enter sib2, iclass 19, count 0 2006.168.08:25:51.11#ibcon#flushed, iclass 19, count 0 2006.168.08:25:51.11#ibcon#about to write, iclass 19, count 0 2006.168.08:25:51.11#ibcon#wrote, iclass 19, count 0 2006.168.08:25:51.11#ibcon#about to read 3, iclass 19, count 0 2006.168.08:25:51.13#ibcon#read 3, iclass 19, count 0 2006.168.08:25:51.13#ibcon#about to read 4, iclass 19, count 0 2006.168.08:25:51.13#ibcon#read 4, iclass 19, count 0 2006.168.08:25:51.13#ibcon#about to read 5, iclass 19, count 0 2006.168.08:25:51.13#ibcon#read 5, iclass 19, count 0 2006.168.08:25:51.13#ibcon#about to read 6, iclass 19, count 0 2006.168.08:25:51.13#ibcon#read 6, iclass 19, count 0 2006.168.08:25:51.13#ibcon#end of sib2, iclass 19, count 0 2006.168.08:25:51.13#ibcon#*mode == 0, iclass 19, count 0 2006.168.08:25:51.13#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.168.08:25:51.13#ibcon#[27=USB\r\n] 2006.168.08:25:51.13#ibcon#*before write, iclass 19, count 0 2006.168.08:25:51.13#ibcon#enter sib2, iclass 19, count 0 2006.168.08:25:51.13#ibcon#flushed, iclass 19, count 0 2006.168.08:25:51.13#ibcon#about to write, iclass 19, count 0 2006.168.08:25:51.13#ibcon#wrote, iclass 19, count 0 2006.168.08:25:51.13#ibcon#about to read 3, iclass 19, count 0 2006.168.08:25:51.16#ibcon#read 3, iclass 19, count 0 2006.168.08:25:51.16#ibcon#about to read 4, iclass 19, count 0 2006.168.08:25:51.16#ibcon#read 4, iclass 19, count 0 2006.168.08:25:51.16#ibcon#about to read 5, iclass 19, count 0 2006.168.08:25:51.16#ibcon#read 5, iclass 19, count 0 2006.168.08:25:51.16#ibcon#about to read 6, iclass 19, count 0 2006.168.08:25:51.16#ibcon#read 6, iclass 19, count 0 2006.168.08:25:51.16#ibcon#end of sib2, iclass 19, count 0 2006.168.08:25:51.16#ibcon#*after write, iclass 19, count 0 2006.168.08:25:51.16#ibcon#*before return 0, iclass 19, count 0 2006.168.08:25:51.16#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:25:51.16#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:25:51.16#ibcon#about to clear, iclass 19 cls_cnt 0 2006.168.08:25:51.16#ibcon#cleared, iclass 19 cls_cnt 0 2006.168.08:25:51.16$vc4f8/vblo=3,656.99 2006.168.08:25:51.16#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.168.08:25:51.16#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.168.08:25:51.16#ibcon#ireg 17 cls_cnt 0 2006.168.08:25:51.16#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:25:51.17#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:25:51.17#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:25:51.17#ibcon#enter wrdev, iclass 21, count 0 2006.168.08:25:51.17#ibcon#first serial, iclass 21, count 0 2006.168.08:25:51.17#ibcon#enter sib2, iclass 21, count 0 2006.168.08:25:51.17#ibcon#flushed, iclass 21, count 0 2006.168.08:25:51.17#ibcon#about to write, iclass 21, count 0 2006.168.08:25:51.17#ibcon#wrote, iclass 21, count 0 2006.168.08:25:51.17#ibcon#about to read 3, iclass 21, count 0 2006.168.08:25:51.18#ibcon#read 3, iclass 21, count 0 2006.168.08:25:51.18#ibcon#about to read 4, iclass 21, count 0 2006.168.08:25:51.18#ibcon#read 4, iclass 21, count 0 2006.168.08:25:51.18#ibcon#about to read 5, iclass 21, count 0 2006.168.08:25:51.18#ibcon#read 5, iclass 21, count 0 2006.168.08:25:51.18#ibcon#about to read 6, iclass 21, count 0 2006.168.08:25:51.18#ibcon#read 6, iclass 21, count 0 2006.168.08:25:51.18#ibcon#end of sib2, iclass 21, count 0 2006.168.08:25:51.18#ibcon#*mode == 0, iclass 21, count 0 2006.168.08:25:51.18#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.168.08:25:51.18#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.08:25:51.18#ibcon#*before write, iclass 21, count 0 2006.168.08:25:51.18#ibcon#enter sib2, iclass 21, count 0 2006.168.08:25:51.18#ibcon#flushed, iclass 21, count 0 2006.168.08:25:51.18#ibcon#about to write, iclass 21, count 0 2006.168.08:25:51.18#ibcon#wrote, iclass 21, count 0 2006.168.08:25:51.18#ibcon#about to read 3, iclass 21, count 0 2006.168.08:25:51.22#ibcon#read 3, iclass 21, count 0 2006.168.08:25:51.22#ibcon#about to read 4, iclass 21, count 0 2006.168.08:25:51.22#ibcon#read 4, iclass 21, count 0 2006.168.08:25:51.22#ibcon#about to read 5, iclass 21, count 0 2006.168.08:25:51.22#ibcon#read 5, iclass 21, count 0 2006.168.08:25:51.22#ibcon#about to read 6, iclass 21, count 0 2006.168.08:25:51.22#ibcon#read 6, iclass 21, count 0 2006.168.08:25:51.22#ibcon#end of sib2, iclass 21, count 0 2006.168.08:25:51.22#ibcon#*after write, iclass 21, count 0 2006.168.08:25:51.22#ibcon#*before return 0, iclass 21, count 0 2006.168.08:25:51.22#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:25:51.22#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.168.08:25:51.22#ibcon#about to clear, iclass 21 cls_cnt 0 2006.168.08:25:51.22#ibcon#cleared, iclass 21 cls_cnt 0 2006.168.08:25:51.22$vc4f8/vb=3,4 2006.168.08:25:51.22#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.168.08:25:51.23#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.168.08:25:51.23#ibcon#ireg 11 cls_cnt 2 2006.168.08:25:51.23#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.168.08:25:51.27#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.168.08:25:51.27#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.168.08:25:51.27#ibcon#enter wrdev, iclass 23, count 2 2006.168.08:25:51.27#ibcon#first serial, iclass 23, count 2 2006.168.08:25:51.27#ibcon#enter sib2, iclass 23, count 2 2006.168.08:25:51.27#ibcon#flushed, iclass 23, count 2 2006.168.08:25:51.27#ibcon#about to write, iclass 23, count 2 2006.168.08:25:51.27#ibcon#wrote, iclass 23, count 2 2006.168.08:25:51.27#ibcon#about to read 3, iclass 23, count 2 2006.168.08:25:51.29#ibcon#read 3, iclass 23, count 2 2006.168.08:25:51.29#ibcon#about to read 4, iclass 23, count 2 2006.168.08:25:51.29#ibcon#read 4, iclass 23, count 2 2006.168.08:25:51.29#ibcon#about to read 5, iclass 23, count 2 2006.168.08:25:51.29#ibcon#read 5, iclass 23, count 2 2006.168.08:25:51.29#ibcon#about to read 6, iclass 23, count 2 2006.168.08:25:51.29#ibcon#read 6, iclass 23, count 2 2006.168.08:25:51.29#ibcon#end of sib2, iclass 23, count 2 2006.168.08:25:51.29#ibcon#*mode == 0, iclass 23, count 2 2006.168.08:25:51.29#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.168.08:25:51.29#ibcon#[27=AT03-04\r\n] 2006.168.08:25:51.29#ibcon#*before write, iclass 23, count 2 2006.168.08:25:51.29#ibcon#enter sib2, iclass 23, count 2 2006.168.08:25:51.29#ibcon#flushed, iclass 23, count 2 2006.168.08:25:51.29#ibcon#about to write, iclass 23, count 2 2006.168.08:25:51.29#ibcon#wrote, iclass 23, count 2 2006.168.08:25:51.29#ibcon#about to read 3, iclass 23, count 2 2006.168.08:25:51.32#ibcon#read 3, iclass 23, count 2 2006.168.08:25:51.32#ibcon#about to read 4, iclass 23, count 2 2006.168.08:25:51.32#ibcon#read 4, iclass 23, count 2 2006.168.08:25:51.32#ibcon#about to read 5, iclass 23, count 2 2006.168.08:25:51.32#ibcon#read 5, iclass 23, count 2 2006.168.08:25:51.32#ibcon#about to read 6, iclass 23, count 2 2006.168.08:25:51.32#ibcon#read 6, iclass 23, count 2 2006.168.08:25:51.32#ibcon#end of sib2, iclass 23, count 2 2006.168.08:25:51.32#ibcon#*after write, iclass 23, count 2 2006.168.08:25:51.32#ibcon#*before return 0, iclass 23, count 2 2006.168.08:25:51.32#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.168.08:25:51.32#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.168.08:25:51.32#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.168.08:25:51.32#ibcon#ireg 7 cls_cnt 0 2006.168.08:25:51.32#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.168.08:25:51.44#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.168.08:25:51.44#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.168.08:25:51.44#ibcon#enter wrdev, iclass 23, count 0 2006.168.08:25:51.44#ibcon#first serial, iclass 23, count 0 2006.168.08:25:51.44#ibcon#enter sib2, iclass 23, count 0 2006.168.08:25:51.44#ibcon#flushed, iclass 23, count 0 2006.168.08:25:51.44#ibcon#about to write, iclass 23, count 0 2006.168.08:25:51.44#ibcon#wrote, iclass 23, count 0 2006.168.08:25:51.44#ibcon#about to read 3, iclass 23, count 0 2006.168.08:25:51.46#ibcon#read 3, iclass 23, count 0 2006.168.08:25:51.46#ibcon#about to read 4, iclass 23, count 0 2006.168.08:25:51.46#ibcon#read 4, iclass 23, count 0 2006.168.08:25:51.46#ibcon#about to read 5, iclass 23, count 0 2006.168.08:25:51.46#ibcon#read 5, iclass 23, count 0 2006.168.08:25:51.46#ibcon#about to read 6, iclass 23, count 0 2006.168.08:25:51.46#ibcon#read 6, iclass 23, count 0 2006.168.08:25:51.46#ibcon#end of sib2, iclass 23, count 0 2006.168.08:25:51.46#ibcon#*mode == 0, iclass 23, count 0 2006.168.08:25:51.46#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.168.08:25:51.46#ibcon#[27=USB\r\n] 2006.168.08:25:51.46#ibcon#*before write, iclass 23, count 0 2006.168.08:25:51.46#ibcon#enter sib2, iclass 23, count 0 2006.168.08:25:51.46#ibcon#flushed, iclass 23, count 0 2006.168.08:25:51.46#ibcon#about to write, iclass 23, count 0 2006.168.08:25:51.46#ibcon#wrote, iclass 23, count 0 2006.168.08:25:51.46#ibcon#about to read 3, iclass 23, count 0 2006.168.08:25:51.49#ibcon#read 3, iclass 23, count 0 2006.168.08:25:51.49#ibcon#about to read 4, iclass 23, count 0 2006.168.08:25:51.49#ibcon#read 4, iclass 23, count 0 2006.168.08:25:51.49#ibcon#about to read 5, iclass 23, count 0 2006.168.08:25:51.49#ibcon#read 5, iclass 23, count 0 2006.168.08:25:51.49#ibcon#about to read 6, iclass 23, count 0 2006.168.08:25:51.49#ibcon#read 6, iclass 23, count 0 2006.168.08:25:51.49#ibcon#end of sib2, iclass 23, count 0 2006.168.08:25:51.49#ibcon#*after write, iclass 23, count 0 2006.168.08:25:51.49#ibcon#*before return 0, iclass 23, count 0 2006.168.08:25:51.49#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.168.08:25:51.49#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.168.08:25:51.49#ibcon#about to clear, iclass 23 cls_cnt 0 2006.168.08:25:51.49#ibcon#cleared, iclass 23 cls_cnt 0 2006.168.08:25:51.49$vc4f8/vblo=4,712.99 2006.168.08:25:51.50#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.168.08:25:51.50#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.168.08:25:51.50#ibcon#ireg 17 cls_cnt 0 2006.168.08:25:51.50#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.168.08:25:51.50#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.168.08:25:51.50#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.168.08:25:51.50#ibcon#enter wrdev, iclass 25, count 0 2006.168.08:25:51.50#ibcon#first serial, iclass 25, count 0 2006.168.08:25:51.50#ibcon#enter sib2, iclass 25, count 0 2006.168.08:25:51.50#ibcon#flushed, iclass 25, count 0 2006.168.08:25:51.50#ibcon#about to write, iclass 25, count 0 2006.168.08:25:51.50#ibcon#wrote, iclass 25, count 0 2006.168.08:25:51.50#ibcon#about to read 3, iclass 25, count 0 2006.168.08:25:51.51#ibcon#read 3, iclass 25, count 0 2006.168.08:25:51.51#ibcon#about to read 4, iclass 25, count 0 2006.168.08:25:51.51#ibcon#read 4, iclass 25, count 0 2006.168.08:25:51.51#ibcon#about to read 5, iclass 25, count 0 2006.168.08:25:51.51#ibcon#read 5, iclass 25, count 0 2006.168.08:25:51.51#ibcon#about to read 6, iclass 25, count 0 2006.168.08:25:51.51#ibcon#read 6, iclass 25, count 0 2006.168.08:25:51.51#ibcon#end of sib2, iclass 25, count 0 2006.168.08:25:51.51#ibcon#*mode == 0, iclass 25, count 0 2006.168.08:25:51.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.168.08:25:51.51#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.08:25:51.51#ibcon#*before write, iclass 25, count 0 2006.168.08:25:51.51#ibcon#enter sib2, iclass 25, count 0 2006.168.08:25:51.51#ibcon#flushed, iclass 25, count 0 2006.168.08:25:51.51#ibcon#about to write, iclass 25, count 0 2006.168.08:25:51.51#ibcon#wrote, iclass 25, count 0 2006.168.08:25:51.51#ibcon#about to read 3, iclass 25, count 0 2006.168.08:25:51.55#ibcon#read 3, iclass 25, count 0 2006.168.08:25:51.55#ibcon#about to read 4, iclass 25, count 0 2006.168.08:25:51.55#ibcon#read 4, iclass 25, count 0 2006.168.08:25:51.55#ibcon#about to read 5, iclass 25, count 0 2006.168.08:25:51.55#ibcon#read 5, iclass 25, count 0 2006.168.08:25:51.55#ibcon#about to read 6, iclass 25, count 0 2006.168.08:25:51.55#ibcon#read 6, iclass 25, count 0 2006.168.08:25:51.55#ibcon#end of sib2, iclass 25, count 0 2006.168.08:25:51.55#ibcon#*after write, iclass 25, count 0 2006.168.08:25:51.55#ibcon#*before return 0, iclass 25, count 0 2006.168.08:25:51.55#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.168.08:25:51.55#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.168.08:25:51.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.168.08:25:51.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.168.08:25:51.55$vc4f8/vb=4,4 2006.168.08:25:51.55#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.168.08:25:51.55#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.168.08:25:51.55#ibcon#ireg 11 cls_cnt 2 2006.168.08:25:51.56#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.168.08:25:51.60#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.168.08:25:51.60#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.168.08:25:51.60#ibcon#enter wrdev, iclass 27, count 2 2006.168.08:25:51.60#ibcon#first serial, iclass 27, count 2 2006.168.08:25:51.60#ibcon#enter sib2, iclass 27, count 2 2006.168.08:25:51.60#ibcon#flushed, iclass 27, count 2 2006.168.08:25:51.60#ibcon#about to write, iclass 27, count 2 2006.168.08:25:51.60#ibcon#wrote, iclass 27, count 2 2006.168.08:25:51.60#ibcon#about to read 3, iclass 27, count 2 2006.168.08:25:51.62#ibcon#read 3, iclass 27, count 2 2006.168.08:25:51.62#ibcon#about to read 4, iclass 27, count 2 2006.168.08:25:51.62#ibcon#read 4, iclass 27, count 2 2006.168.08:25:51.62#ibcon#about to read 5, iclass 27, count 2 2006.168.08:25:51.62#ibcon#read 5, iclass 27, count 2 2006.168.08:25:51.62#ibcon#about to read 6, iclass 27, count 2 2006.168.08:25:51.62#ibcon#read 6, iclass 27, count 2 2006.168.08:25:51.62#ibcon#end of sib2, iclass 27, count 2 2006.168.08:25:51.62#ibcon#*mode == 0, iclass 27, count 2 2006.168.08:25:51.62#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.168.08:25:51.62#ibcon#[27=AT04-04\r\n] 2006.168.08:25:51.62#ibcon#*before write, iclass 27, count 2 2006.168.08:25:51.62#ibcon#enter sib2, iclass 27, count 2 2006.168.08:25:51.62#ibcon#flushed, iclass 27, count 2 2006.168.08:25:51.62#ibcon#about to write, iclass 27, count 2 2006.168.08:25:51.62#ibcon#wrote, iclass 27, count 2 2006.168.08:25:51.62#ibcon#about to read 3, iclass 27, count 2 2006.168.08:25:51.65#ibcon#read 3, iclass 27, count 2 2006.168.08:25:51.65#ibcon#about to read 4, iclass 27, count 2 2006.168.08:25:51.65#ibcon#read 4, iclass 27, count 2 2006.168.08:25:51.65#ibcon#about to read 5, iclass 27, count 2 2006.168.08:25:51.65#ibcon#read 5, iclass 27, count 2 2006.168.08:25:51.65#ibcon#about to read 6, iclass 27, count 2 2006.168.08:25:51.65#ibcon#read 6, iclass 27, count 2 2006.168.08:25:51.65#ibcon#end of sib2, iclass 27, count 2 2006.168.08:25:51.65#ibcon#*after write, iclass 27, count 2 2006.168.08:25:51.65#ibcon#*before return 0, iclass 27, count 2 2006.168.08:25:51.65#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.168.08:25:51.65#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.168.08:25:51.65#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.168.08:25:51.65#ibcon#ireg 7 cls_cnt 0 2006.168.08:25:51.65#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.168.08:25:51.77#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.168.08:25:51.77#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.168.08:25:51.77#ibcon#enter wrdev, iclass 27, count 0 2006.168.08:25:51.77#ibcon#first serial, iclass 27, count 0 2006.168.08:25:51.77#ibcon#enter sib2, iclass 27, count 0 2006.168.08:25:51.77#ibcon#flushed, iclass 27, count 0 2006.168.08:25:51.77#ibcon#about to write, iclass 27, count 0 2006.168.08:25:51.77#ibcon#wrote, iclass 27, count 0 2006.168.08:25:51.77#ibcon#about to read 3, iclass 27, count 0 2006.168.08:25:51.79#ibcon#read 3, iclass 27, count 0 2006.168.08:25:51.79#ibcon#about to read 4, iclass 27, count 0 2006.168.08:25:51.79#ibcon#read 4, iclass 27, count 0 2006.168.08:25:51.79#ibcon#about to read 5, iclass 27, count 0 2006.168.08:25:51.79#ibcon#read 5, iclass 27, count 0 2006.168.08:25:51.79#ibcon#about to read 6, iclass 27, count 0 2006.168.08:25:51.79#ibcon#read 6, iclass 27, count 0 2006.168.08:25:51.79#ibcon#end of sib2, iclass 27, count 0 2006.168.08:25:51.79#ibcon#*mode == 0, iclass 27, count 0 2006.168.08:25:51.79#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.168.08:25:51.79#ibcon#[27=USB\r\n] 2006.168.08:25:51.79#ibcon#*before write, iclass 27, count 0 2006.168.08:25:51.79#ibcon#enter sib2, iclass 27, count 0 2006.168.08:25:51.79#ibcon#flushed, iclass 27, count 0 2006.168.08:25:51.79#ibcon#about to write, iclass 27, count 0 2006.168.08:25:51.79#ibcon#wrote, iclass 27, count 0 2006.168.08:25:51.79#ibcon#about to read 3, iclass 27, count 0 2006.168.08:25:51.82#ibcon#read 3, iclass 27, count 0 2006.168.08:25:51.82#ibcon#about to read 4, iclass 27, count 0 2006.168.08:25:51.82#ibcon#read 4, iclass 27, count 0 2006.168.08:25:51.82#ibcon#about to read 5, iclass 27, count 0 2006.168.08:25:51.82#ibcon#read 5, iclass 27, count 0 2006.168.08:25:51.82#ibcon#about to read 6, iclass 27, count 0 2006.168.08:25:51.82#ibcon#read 6, iclass 27, count 0 2006.168.08:25:51.82#ibcon#end of sib2, iclass 27, count 0 2006.168.08:25:51.82#ibcon#*after write, iclass 27, count 0 2006.168.08:25:51.82#ibcon#*before return 0, iclass 27, count 0 2006.168.08:25:51.82#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.168.08:25:51.82#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.168.08:25:51.82#ibcon#about to clear, iclass 27 cls_cnt 0 2006.168.08:25:51.82#ibcon#cleared, iclass 27 cls_cnt 0 2006.168.08:25:51.82$vc4f8/vblo=5,744.99 2006.168.08:25:51.83#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.168.08:25:51.83#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.168.08:25:51.83#ibcon#ireg 17 cls_cnt 0 2006.168.08:25:51.83#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.168.08:25:51.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.168.08:25:51.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.168.08:25:51.83#ibcon#enter wrdev, iclass 29, count 0 2006.168.08:25:51.83#ibcon#first serial, iclass 29, count 0 2006.168.08:25:51.83#ibcon#enter sib2, iclass 29, count 0 2006.168.08:25:51.83#ibcon#flushed, iclass 29, count 0 2006.168.08:25:51.83#ibcon#about to write, iclass 29, count 0 2006.168.08:25:51.83#ibcon#wrote, iclass 29, count 0 2006.168.08:25:51.83#ibcon#about to read 3, iclass 29, count 0 2006.168.08:25:51.84#ibcon#read 3, iclass 29, count 0 2006.168.08:25:51.84#ibcon#about to read 4, iclass 29, count 0 2006.168.08:25:51.84#ibcon#read 4, iclass 29, count 0 2006.168.08:25:51.84#ibcon#about to read 5, iclass 29, count 0 2006.168.08:25:51.84#ibcon#read 5, iclass 29, count 0 2006.168.08:25:51.84#ibcon#about to read 6, iclass 29, count 0 2006.168.08:25:51.84#ibcon#read 6, iclass 29, count 0 2006.168.08:25:51.84#ibcon#end of sib2, iclass 29, count 0 2006.168.08:25:51.84#ibcon#*mode == 0, iclass 29, count 0 2006.168.08:25:51.84#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.168.08:25:51.84#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.08:25:51.84#ibcon#*before write, iclass 29, count 0 2006.168.08:25:51.84#ibcon#enter sib2, iclass 29, count 0 2006.168.08:25:51.84#ibcon#flushed, iclass 29, count 0 2006.168.08:25:51.84#ibcon#about to write, iclass 29, count 0 2006.168.08:25:51.84#ibcon#wrote, iclass 29, count 0 2006.168.08:25:51.84#ibcon#about to read 3, iclass 29, count 0 2006.168.08:25:51.88#ibcon#read 3, iclass 29, count 0 2006.168.08:25:51.88#ibcon#about to read 4, iclass 29, count 0 2006.168.08:25:51.88#ibcon#read 4, iclass 29, count 0 2006.168.08:25:51.88#ibcon#about to read 5, iclass 29, count 0 2006.168.08:25:51.88#ibcon#read 5, iclass 29, count 0 2006.168.08:25:51.88#ibcon#about to read 6, iclass 29, count 0 2006.168.08:25:51.88#ibcon#read 6, iclass 29, count 0 2006.168.08:25:51.88#ibcon#end of sib2, iclass 29, count 0 2006.168.08:25:51.88#ibcon#*after write, iclass 29, count 0 2006.168.08:25:51.88#ibcon#*before return 0, iclass 29, count 0 2006.168.08:25:51.88#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.168.08:25:51.88#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.168.08:25:51.88#ibcon#about to clear, iclass 29 cls_cnt 0 2006.168.08:25:51.88#ibcon#cleared, iclass 29 cls_cnt 0 2006.168.08:25:51.88$vc4f8/vb=5,4 2006.168.08:25:51.89#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.168.08:25:51.89#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.168.08:25:51.89#ibcon#ireg 11 cls_cnt 2 2006.168.08:25:51.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.168.08:25:51.93#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.168.08:25:51.93#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.168.08:25:51.93#ibcon#enter wrdev, iclass 31, count 2 2006.168.08:25:51.93#ibcon#first serial, iclass 31, count 2 2006.168.08:25:51.93#ibcon#enter sib2, iclass 31, count 2 2006.168.08:25:51.93#ibcon#flushed, iclass 31, count 2 2006.168.08:25:51.93#ibcon#about to write, iclass 31, count 2 2006.168.08:25:51.93#ibcon#wrote, iclass 31, count 2 2006.168.08:25:51.93#ibcon#about to read 3, iclass 31, count 2 2006.168.08:25:51.95#ibcon#read 3, iclass 31, count 2 2006.168.08:25:51.95#ibcon#about to read 4, iclass 31, count 2 2006.168.08:25:51.95#ibcon#read 4, iclass 31, count 2 2006.168.08:25:51.95#ibcon#about to read 5, iclass 31, count 2 2006.168.08:25:51.95#ibcon#read 5, iclass 31, count 2 2006.168.08:25:51.95#ibcon#about to read 6, iclass 31, count 2 2006.168.08:25:51.95#ibcon#read 6, iclass 31, count 2 2006.168.08:25:51.95#ibcon#end of sib2, iclass 31, count 2 2006.168.08:25:51.95#ibcon#*mode == 0, iclass 31, count 2 2006.168.08:25:51.95#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.168.08:25:51.95#ibcon#[27=AT05-04\r\n] 2006.168.08:25:51.95#ibcon#*before write, iclass 31, count 2 2006.168.08:25:51.95#ibcon#enter sib2, iclass 31, count 2 2006.168.08:25:51.95#ibcon#flushed, iclass 31, count 2 2006.168.08:25:51.95#ibcon#about to write, iclass 31, count 2 2006.168.08:25:51.95#ibcon#wrote, iclass 31, count 2 2006.168.08:25:51.95#ibcon#about to read 3, iclass 31, count 2 2006.168.08:25:51.98#ibcon#read 3, iclass 31, count 2 2006.168.08:25:51.98#ibcon#about to read 4, iclass 31, count 2 2006.168.08:25:51.98#ibcon#read 4, iclass 31, count 2 2006.168.08:25:51.98#ibcon#about to read 5, iclass 31, count 2 2006.168.08:25:51.98#ibcon#read 5, iclass 31, count 2 2006.168.08:25:51.98#ibcon#about to read 6, iclass 31, count 2 2006.168.08:25:51.98#ibcon#read 6, iclass 31, count 2 2006.168.08:25:51.98#ibcon#end of sib2, iclass 31, count 2 2006.168.08:25:51.98#ibcon#*after write, iclass 31, count 2 2006.168.08:25:51.98#ibcon#*before return 0, iclass 31, count 2 2006.168.08:25:51.98#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.168.08:25:51.98#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.168.08:25:51.98#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.168.08:25:51.98#ibcon#ireg 7 cls_cnt 0 2006.168.08:25:51.98#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.168.08:25:52.10#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.168.08:25:52.10#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.168.08:25:52.10#ibcon#enter wrdev, iclass 31, count 0 2006.168.08:25:52.10#ibcon#first serial, iclass 31, count 0 2006.168.08:25:52.10#ibcon#enter sib2, iclass 31, count 0 2006.168.08:25:52.10#ibcon#flushed, iclass 31, count 0 2006.168.08:25:52.10#ibcon#about to write, iclass 31, count 0 2006.168.08:25:52.10#ibcon#wrote, iclass 31, count 0 2006.168.08:25:52.10#ibcon#about to read 3, iclass 31, count 0 2006.168.08:25:52.12#ibcon#read 3, iclass 31, count 0 2006.168.08:25:52.12#ibcon#about to read 4, iclass 31, count 0 2006.168.08:25:52.12#ibcon#read 4, iclass 31, count 0 2006.168.08:25:52.12#ibcon#about to read 5, iclass 31, count 0 2006.168.08:25:52.12#ibcon#read 5, iclass 31, count 0 2006.168.08:25:52.12#ibcon#about to read 6, iclass 31, count 0 2006.168.08:25:52.12#ibcon#read 6, iclass 31, count 0 2006.168.08:25:52.12#ibcon#end of sib2, iclass 31, count 0 2006.168.08:25:52.12#ibcon#*mode == 0, iclass 31, count 0 2006.168.08:25:52.12#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.168.08:25:52.12#ibcon#[27=USB\r\n] 2006.168.08:25:52.12#ibcon#*before write, iclass 31, count 0 2006.168.08:25:52.12#ibcon#enter sib2, iclass 31, count 0 2006.168.08:25:52.12#ibcon#flushed, iclass 31, count 0 2006.168.08:25:52.12#ibcon#about to write, iclass 31, count 0 2006.168.08:25:52.12#ibcon#wrote, iclass 31, count 0 2006.168.08:25:52.12#ibcon#about to read 3, iclass 31, count 0 2006.168.08:25:52.15#ibcon#read 3, iclass 31, count 0 2006.168.08:25:52.15#ibcon#about to read 4, iclass 31, count 0 2006.168.08:25:52.15#ibcon#read 4, iclass 31, count 0 2006.168.08:25:52.15#ibcon#about to read 5, iclass 31, count 0 2006.168.08:25:52.15#ibcon#read 5, iclass 31, count 0 2006.168.08:25:52.15#ibcon#about to read 6, iclass 31, count 0 2006.168.08:25:52.15#ibcon#read 6, iclass 31, count 0 2006.168.08:25:52.15#ibcon#end of sib2, iclass 31, count 0 2006.168.08:25:52.15#ibcon#*after write, iclass 31, count 0 2006.168.08:25:52.15#ibcon#*before return 0, iclass 31, count 0 2006.168.08:25:52.15#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.168.08:25:52.15#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.168.08:25:52.15#ibcon#about to clear, iclass 31 cls_cnt 0 2006.168.08:25:52.15#ibcon#cleared, iclass 31 cls_cnt 0 2006.168.08:25:52.15$vc4f8/vblo=6,752.99 2006.168.08:25:52.16#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.168.08:25:52.16#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.168.08:25:52.16#ibcon#ireg 17 cls_cnt 0 2006.168.08:25:52.16#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:25:52.16#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:25:52.16#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:25:52.16#ibcon#enter wrdev, iclass 33, count 0 2006.168.08:25:52.16#ibcon#first serial, iclass 33, count 0 2006.168.08:25:52.16#ibcon#enter sib2, iclass 33, count 0 2006.168.08:25:52.16#ibcon#flushed, iclass 33, count 0 2006.168.08:25:52.16#ibcon#about to write, iclass 33, count 0 2006.168.08:25:52.16#ibcon#wrote, iclass 33, count 0 2006.168.08:25:52.16#ibcon#about to read 3, iclass 33, count 0 2006.168.08:25:52.17#ibcon#read 3, iclass 33, count 0 2006.168.08:25:52.17#ibcon#about to read 4, iclass 33, count 0 2006.168.08:25:52.17#ibcon#read 4, iclass 33, count 0 2006.168.08:25:52.17#ibcon#about to read 5, iclass 33, count 0 2006.168.08:25:52.17#ibcon#read 5, iclass 33, count 0 2006.168.08:25:52.17#ibcon#about to read 6, iclass 33, count 0 2006.168.08:25:52.17#ibcon#read 6, iclass 33, count 0 2006.168.08:25:52.17#ibcon#end of sib2, iclass 33, count 0 2006.168.08:25:52.17#ibcon#*mode == 0, iclass 33, count 0 2006.168.08:25:52.17#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.168.08:25:52.17#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.08:25:52.17#ibcon#*before write, iclass 33, count 0 2006.168.08:25:52.17#ibcon#enter sib2, iclass 33, count 0 2006.168.08:25:52.17#ibcon#flushed, iclass 33, count 0 2006.168.08:25:52.17#ibcon#about to write, iclass 33, count 0 2006.168.08:25:52.17#ibcon#wrote, iclass 33, count 0 2006.168.08:25:52.17#ibcon#about to read 3, iclass 33, count 0 2006.168.08:25:52.21#ibcon#read 3, iclass 33, count 0 2006.168.08:25:52.21#ibcon#about to read 4, iclass 33, count 0 2006.168.08:25:52.21#ibcon#read 4, iclass 33, count 0 2006.168.08:25:52.21#ibcon#about to read 5, iclass 33, count 0 2006.168.08:25:52.21#ibcon#read 5, iclass 33, count 0 2006.168.08:25:52.21#ibcon#about to read 6, iclass 33, count 0 2006.168.08:25:52.21#ibcon#read 6, iclass 33, count 0 2006.168.08:25:52.21#ibcon#end of sib2, iclass 33, count 0 2006.168.08:25:52.21#ibcon#*after write, iclass 33, count 0 2006.168.08:25:52.21#ibcon#*before return 0, iclass 33, count 0 2006.168.08:25:52.21#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:25:52.21#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.168.08:25:52.21#ibcon#about to clear, iclass 33 cls_cnt 0 2006.168.08:25:52.21#ibcon#cleared, iclass 33 cls_cnt 0 2006.168.08:25:52.21$vc4f8/vb=6,4 2006.168.08:25:52.22#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.168.08:25:52.22#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.168.08:25:52.22#ibcon#ireg 11 cls_cnt 2 2006.168.08:25:52.22#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.168.08:25:52.26#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.168.08:25:52.26#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.168.08:25:52.26#ibcon#enter wrdev, iclass 35, count 2 2006.168.08:25:52.26#ibcon#first serial, iclass 35, count 2 2006.168.08:25:52.26#ibcon#enter sib2, iclass 35, count 2 2006.168.08:25:52.26#ibcon#flushed, iclass 35, count 2 2006.168.08:25:52.26#ibcon#about to write, iclass 35, count 2 2006.168.08:25:52.26#ibcon#wrote, iclass 35, count 2 2006.168.08:25:52.26#ibcon#about to read 3, iclass 35, count 2 2006.168.08:25:52.28#ibcon#read 3, iclass 35, count 2 2006.168.08:25:52.28#ibcon#about to read 4, iclass 35, count 2 2006.168.08:25:52.28#ibcon#read 4, iclass 35, count 2 2006.168.08:25:52.28#ibcon#about to read 5, iclass 35, count 2 2006.168.08:25:52.28#ibcon#read 5, iclass 35, count 2 2006.168.08:25:52.28#ibcon#about to read 6, iclass 35, count 2 2006.168.08:25:52.28#ibcon#read 6, iclass 35, count 2 2006.168.08:25:52.28#ibcon#end of sib2, iclass 35, count 2 2006.168.08:25:52.28#ibcon#*mode == 0, iclass 35, count 2 2006.168.08:25:52.28#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.168.08:25:52.28#ibcon#[27=AT06-04\r\n] 2006.168.08:25:52.28#ibcon#*before write, iclass 35, count 2 2006.168.08:25:52.28#ibcon#enter sib2, iclass 35, count 2 2006.168.08:25:52.28#ibcon#flushed, iclass 35, count 2 2006.168.08:25:52.28#ibcon#about to write, iclass 35, count 2 2006.168.08:25:52.28#ibcon#wrote, iclass 35, count 2 2006.168.08:25:52.28#ibcon#about to read 3, iclass 35, count 2 2006.168.08:25:52.31#ibcon#read 3, iclass 35, count 2 2006.168.08:25:52.31#ibcon#about to read 4, iclass 35, count 2 2006.168.08:25:52.31#ibcon#read 4, iclass 35, count 2 2006.168.08:25:52.31#ibcon#about to read 5, iclass 35, count 2 2006.168.08:25:52.31#ibcon#read 5, iclass 35, count 2 2006.168.08:25:52.31#ibcon#about to read 6, iclass 35, count 2 2006.168.08:25:52.31#ibcon#read 6, iclass 35, count 2 2006.168.08:25:52.31#ibcon#end of sib2, iclass 35, count 2 2006.168.08:25:52.31#ibcon#*after write, iclass 35, count 2 2006.168.08:25:52.31#ibcon#*before return 0, iclass 35, count 2 2006.168.08:25:52.31#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.168.08:25:52.31#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.168.08:25:52.31#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.168.08:25:52.31#ibcon#ireg 7 cls_cnt 0 2006.168.08:25:52.31#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.168.08:25:52.43#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.168.08:25:52.43#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.168.08:25:52.43#ibcon#enter wrdev, iclass 35, count 0 2006.168.08:25:52.43#ibcon#first serial, iclass 35, count 0 2006.168.08:25:52.43#ibcon#enter sib2, iclass 35, count 0 2006.168.08:25:52.43#ibcon#flushed, iclass 35, count 0 2006.168.08:25:52.43#ibcon#about to write, iclass 35, count 0 2006.168.08:25:52.43#ibcon#wrote, iclass 35, count 0 2006.168.08:25:52.43#ibcon#about to read 3, iclass 35, count 0 2006.168.08:25:52.45#ibcon#read 3, iclass 35, count 0 2006.168.08:25:52.45#ibcon#about to read 4, iclass 35, count 0 2006.168.08:25:52.45#ibcon#read 4, iclass 35, count 0 2006.168.08:25:52.45#ibcon#about to read 5, iclass 35, count 0 2006.168.08:25:52.45#ibcon#read 5, iclass 35, count 0 2006.168.08:25:52.45#ibcon#about to read 6, iclass 35, count 0 2006.168.08:25:52.45#ibcon#read 6, iclass 35, count 0 2006.168.08:25:52.45#ibcon#end of sib2, iclass 35, count 0 2006.168.08:25:52.45#ibcon#*mode == 0, iclass 35, count 0 2006.168.08:25:52.45#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.168.08:25:52.45#ibcon#[27=USB\r\n] 2006.168.08:25:52.45#ibcon#*before write, iclass 35, count 0 2006.168.08:25:52.45#ibcon#enter sib2, iclass 35, count 0 2006.168.08:25:52.45#ibcon#flushed, iclass 35, count 0 2006.168.08:25:52.45#ibcon#about to write, iclass 35, count 0 2006.168.08:25:52.45#ibcon#wrote, iclass 35, count 0 2006.168.08:25:52.45#ibcon#about to read 3, iclass 35, count 0 2006.168.08:25:52.48#ibcon#read 3, iclass 35, count 0 2006.168.08:25:52.48#ibcon#about to read 4, iclass 35, count 0 2006.168.08:25:52.48#ibcon#read 4, iclass 35, count 0 2006.168.08:25:52.48#ibcon#about to read 5, iclass 35, count 0 2006.168.08:25:52.48#ibcon#read 5, iclass 35, count 0 2006.168.08:25:52.48#ibcon#about to read 6, iclass 35, count 0 2006.168.08:25:52.48#ibcon#read 6, iclass 35, count 0 2006.168.08:25:52.48#ibcon#end of sib2, iclass 35, count 0 2006.168.08:25:52.48#ibcon#*after write, iclass 35, count 0 2006.168.08:25:52.48#ibcon#*before return 0, iclass 35, count 0 2006.168.08:25:52.48#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.168.08:25:52.48#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.168.08:25:52.48#ibcon#about to clear, iclass 35 cls_cnt 0 2006.168.08:25:52.48#ibcon#cleared, iclass 35 cls_cnt 0 2006.168.08:25:52.48$vc4f8/vabw=wide 2006.168.08:25:52.49#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.168.08:25:52.49#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.168.08:25:52.49#ibcon#ireg 8 cls_cnt 0 2006.168.08:25:52.49#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:25:52.49#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:25:52.49#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:25:52.49#ibcon#enter wrdev, iclass 37, count 0 2006.168.08:25:52.49#ibcon#first serial, iclass 37, count 0 2006.168.08:25:52.49#ibcon#enter sib2, iclass 37, count 0 2006.168.08:25:52.49#ibcon#flushed, iclass 37, count 0 2006.168.08:25:52.49#ibcon#about to write, iclass 37, count 0 2006.168.08:25:52.49#ibcon#wrote, iclass 37, count 0 2006.168.08:25:52.49#ibcon#about to read 3, iclass 37, count 0 2006.168.08:25:52.50#ibcon#read 3, iclass 37, count 0 2006.168.08:25:52.50#ibcon#about to read 4, iclass 37, count 0 2006.168.08:25:52.50#ibcon#read 4, iclass 37, count 0 2006.168.08:25:52.50#ibcon#about to read 5, iclass 37, count 0 2006.168.08:25:52.50#ibcon#read 5, iclass 37, count 0 2006.168.08:25:52.50#ibcon#about to read 6, iclass 37, count 0 2006.168.08:25:52.50#ibcon#read 6, iclass 37, count 0 2006.168.08:25:52.50#ibcon#end of sib2, iclass 37, count 0 2006.168.08:25:52.50#ibcon#*mode == 0, iclass 37, count 0 2006.168.08:25:52.50#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.168.08:25:52.50#ibcon#[25=BW32\r\n] 2006.168.08:25:52.50#ibcon#*before write, iclass 37, count 0 2006.168.08:25:52.50#ibcon#enter sib2, iclass 37, count 0 2006.168.08:25:52.50#ibcon#flushed, iclass 37, count 0 2006.168.08:25:52.50#ibcon#about to write, iclass 37, count 0 2006.168.08:25:52.50#ibcon#wrote, iclass 37, count 0 2006.168.08:25:52.50#ibcon#about to read 3, iclass 37, count 0 2006.168.08:25:52.53#ibcon#read 3, iclass 37, count 0 2006.168.08:25:52.53#ibcon#about to read 4, iclass 37, count 0 2006.168.08:25:52.53#ibcon#read 4, iclass 37, count 0 2006.168.08:25:52.53#ibcon#about to read 5, iclass 37, count 0 2006.168.08:25:52.53#ibcon#read 5, iclass 37, count 0 2006.168.08:25:52.53#ibcon#about to read 6, iclass 37, count 0 2006.168.08:25:52.53#ibcon#read 6, iclass 37, count 0 2006.168.08:25:52.53#ibcon#end of sib2, iclass 37, count 0 2006.168.08:25:52.53#ibcon#*after write, iclass 37, count 0 2006.168.08:25:52.53#ibcon#*before return 0, iclass 37, count 0 2006.168.08:25:52.53#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:25:52.53#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.168.08:25:52.53#ibcon#about to clear, iclass 37 cls_cnt 0 2006.168.08:25:52.53#ibcon#cleared, iclass 37 cls_cnt 0 2006.168.08:25:52.53$vc4f8/vbbw=wide 2006.168.08:25:52.54#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.168.08:25:52.54#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.168.08:25:52.54#ibcon#ireg 8 cls_cnt 0 2006.168.08:25:52.54#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.168.08:25:52.59#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.168.08:25:52.59#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.168.08:25:52.59#ibcon#enter wrdev, iclass 39, count 0 2006.168.08:25:52.59#ibcon#first serial, iclass 39, count 0 2006.168.08:25:52.59#ibcon#enter sib2, iclass 39, count 0 2006.168.08:25:52.59#ibcon#flushed, iclass 39, count 0 2006.168.08:25:52.59#ibcon#about to write, iclass 39, count 0 2006.168.08:25:52.59#ibcon#wrote, iclass 39, count 0 2006.168.08:25:52.59#ibcon#about to read 3, iclass 39, count 0 2006.168.08:25:52.61#ibcon#read 3, iclass 39, count 0 2006.168.08:25:52.61#ibcon#about to read 4, iclass 39, count 0 2006.168.08:25:52.61#ibcon#read 4, iclass 39, count 0 2006.168.08:25:52.61#ibcon#about to read 5, iclass 39, count 0 2006.168.08:25:52.61#ibcon#read 5, iclass 39, count 0 2006.168.08:25:52.61#ibcon#about to read 6, iclass 39, count 0 2006.168.08:25:52.61#ibcon#read 6, iclass 39, count 0 2006.168.08:25:52.61#ibcon#end of sib2, iclass 39, count 0 2006.168.08:25:52.61#ibcon#*mode == 0, iclass 39, count 0 2006.168.08:25:52.61#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.168.08:25:52.61#ibcon#[27=BW32\r\n] 2006.168.08:25:52.61#ibcon#*before write, iclass 39, count 0 2006.168.08:25:52.61#ibcon#enter sib2, iclass 39, count 0 2006.168.08:25:52.61#ibcon#flushed, iclass 39, count 0 2006.168.08:25:52.61#ibcon#about to write, iclass 39, count 0 2006.168.08:25:52.61#ibcon#wrote, iclass 39, count 0 2006.168.08:25:52.61#ibcon#about to read 3, iclass 39, count 0 2006.168.08:25:52.65#ibcon#read 3, iclass 39, count 0 2006.168.08:25:52.65#ibcon#about to read 4, iclass 39, count 0 2006.168.08:25:52.65#ibcon#read 4, iclass 39, count 0 2006.168.08:25:52.65#ibcon#about to read 5, iclass 39, count 0 2006.168.08:25:52.65#ibcon#read 5, iclass 39, count 0 2006.168.08:25:52.65#ibcon#about to read 6, iclass 39, count 0 2006.168.08:25:52.65#ibcon#read 6, iclass 39, count 0 2006.168.08:25:52.65#ibcon#end of sib2, iclass 39, count 0 2006.168.08:25:52.65#ibcon#*after write, iclass 39, count 0 2006.168.08:25:52.65#ibcon#*before return 0, iclass 39, count 0 2006.168.08:25:52.65#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.168.08:25:52.65#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.168.08:25:52.65#ibcon#about to clear, iclass 39 cls_cnt 0 2006.168.08:25:52.65#ibcon#cleared, iclass 39 cls_cnt 0 2006.168.08:25:52.65$4f8m12a/ifd4f 2006.168.08:25:52.65$ifd4f/lo= 2006.168.08:25:52.65$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.08:25:52.65$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.08:25:52.65$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.08:25:52.65$ifd4f/patch= 2006.168.08:25:52.65$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.08:25:52.65$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.08:25:52.65$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.08:25:52.65$4f8m12a/"form=m,16.000,1:2 2006.168.08:25:52.65$4f8m12a/"tpicd 2006.168.08:25:52.65$4f8m12a/echo=off 2006.168.08:25:52.65$4f8m12a/xlog=off 2006.168.08:25:52.65:!2006.168.08:26:30 2006.168.08:26:14.13#trakl#Source acquired 2006.168.08:26:14.13#flagr#flagr/antenna,acquired 2006.168.08:26:30.00:preob 2006.168.08:26:30.14/onsource/TRACKING 2006.168.08:26:30.14:!2006.168.08:26:40 2006.168.08:26:40.01:data_valid=on 2006.168.08:26:40.02:midob 2006.168.08:26:41.13/onsource/TRACKING 2006.168.08:26:41.14/wx/26.80,1004.6,75 2006.168.08:26:41.28/cable/+6.4711E-03 2006.168.08:26:42.37/va/01,08,usb,yes,30,32 2006.168.08:26:42.37/va/02,07,usb,yes,30,32 2006.168.08:26:42.37/va/03,06,usb,yes,32,32 2006.168.08:26:42.37/va/04,07,usb,yes,31,34 2006.168.08:26:42.37/va/05,07,usb,yes,32,34 2006.168.08:26:42.37/va/06,06,usb,yes,31,31 2006.168.08:26:42.37/va/07,06,usb,yes,31,31 2006.168.08:26:42.37/va/08,07,usb,yes,30,29 2006.168.08:26:42.60/valo/01,532.99,yes,locked 2006.168.08:26:42.60/valo/02,572.99,yes,locked 2006.168.08:26:42.60/valo/03,672.99,yes,locked 2006.168.08:26:42.60/valo/04,832.99,yes,locked 2006.168.08:26:42.60/valo/05,652.99,yes,locked 2006.168.08:26:42.60/valo/06,772.99,yes,locked 2006.168.08:26:42.60/valo/07,832.99,yes,locked 2006.168.08:26:42.60/valo/08,852.99,yes,locked 2006.168.08:26:43.69/vb/01,04,usb,yes,30,28 2006.168.08:26:43.69/vb/02,04,usb,yes,32,33 2006.168.08:26:43.69/vb/03,04,usb,yes,28,32 2006.168.08:26:43.69/vb/04,04,usb,yes,29,29 2006.168.08:26:43.69/vb/05,04,usb,yes,27,31 2006.168.08:26:43.69/vb/06,04,usb,yes,28,31 2006.168.08:26:43.69/vb/07,04,usb,yes,30,30 2006.168.08:26:43.69/vb/08,04,usb,yes,28,31 2006.168.08:26:43.92/vblo/01,632.99,yes,locked 2006.168.08:26:43.92/vblo/02,640.99,yes,locked 2006.168.08:26:43.92/vblo/03,656.99,yes,locked 2006.168.08:26:43.92/vblo/04,712.99,yes,locked 2006.168.08:26:43.92/vblo/05,744.99,yes,locked 2006.168.08:26:43.92/vblo/06,752.99,yes,locked 2006.168.08:26:43.92/vblo/07,734.99,yes,locked 2006.168.08:26:43.92/vblo/08,744.99,yes,locked 2006.168.08:26:44.07/vabw/8 2006.168.08:26:44.22/vbbw/8 2006.168.08:26:44.31/xfe/off,on,14.0 2006.168.08:26:44.69/ifatt/23,28,28,28 2006.168.08:26:45.07/fmout-gps/S +4.17E-07 2006.168.08:26:45.12:!2006.168.08:27:40 2006.168.08:27:40.01:data_valid=off 2006.168.08:27:40.02:postob 2006.168.08:27:40.13/cable/+6.4709E-03 2006.168.08:27:40.14/wx/26.79,1004.6,75 2006.168.08:27:41.07/fmout-gps/S +4.18E-07 2006.168.08:27:41.08:scan_name=168-0828,k06168,60 2006.168.08:27:41.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.168.08:27:41.13#flagr#flagr/antenna,new-source 2006.168.08:27:42.14:checkk5 2006.168.08:27:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.168.08:27:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.168.08:27:43.27/chk_autoobs//k5ts3/ autoobs is running! 2006.168.08:27:43.65/chk_autoobs//k5ts4/ autoobs is running! 2006.168.08:27:44.02/chk_obsdata//k5ts1/T1680826??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:27:44.39/chk_obsdata//k5ts2/T1680826??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:27:44.76/chk_obsdata//k5ts3/T1680826??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:27:45.13/chk_obsdata//k5ts4/T1680826??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:27:45.82/k5log//k5ts1_log_newline 2006.168.08:27:46.51/k5log//k5ts2_log_newline 2006.168.08:27:47.24/k5log//k5ts3_log_newline 2006.168.08:27:47.93/k5log//k5ts4_log_newline 2006.168.08:27:47.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.08:27:47.95:4f8m12a=3 2006.168.08:27:47.95$4f8m12a/echo=on 2006.168.08:27:47.95$4f8m12a/pcalon 2006.168.08:27:47.95$pcalon/"no phase cal control is implemented here 2006.168.08:27:47.95$4f8m12a/"tpicd=stop 2006.168.08:27:47.95$4f8m12a/vc4f8 2006.168.08:27:47.95$vc4f8/valo=1,532.99 2006.168.08:27:47.96#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.168.08:27:47.96#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.168.08:27:47.96#ibcon#ireg 17 cls_cnt 0 2006.168.08:27:47.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:27:47.96#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:27:47.96#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:27:47.96#ibcon#enter wrdev, iclass 18, count 0 2006.168.08:27:47.96#ibcon#first serial, iclass 18, count 0 2006.168.08:27:47.96#ibcon#enter sib2, iclass 18, count 0 2006.168.08:27:47.96#ibcon#flushed, iclass 18, count 0 2006.168.08:27:47.96#ibcon#about to write, iclass 18, count 0 2006.168.08:27:47.96#ibcon#wrote, iclass 18, count 0 2006.168.08:27:47.96#ibcon#about to read 3, iclass 18, count 0 2006.168.08:27:48.00#ibcon#read 3, iclass 18, count 0 2006.168.08:27:48.00#ibcon#about to read 4, iclass 18, count 0 2006.168.08:27:48.00#ibcon#read 4, iclass 18, count 0 2006.168.08:27:48.00#ibcon#about to read 5, iclass 18, count 0 2006.168.08:27:48.00#ibcon#read 5, iclass 18, count 0 2006.168.08:27:48.00#ibcon#about to read 6, iclass 18, count 0 2006.168.08:27:48.00#ibcon#read 6, iclass 18, count 0 2006.168.08:27:48.00#ibcon#end of sib2, iclass 18, count 0 2006.168.08:27:48.00#ibcon#*mode == 0, iclass 18, count 0 2006.168.08:27:48.00#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.08:27:48.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.08:27:48.00#ibcon#*before write, iclass 18, count 0 2006.168.08:27:48.00#ibcon#enter sib2, iclass 18, count 0 2006.168.08:27:48.00#ibcon#flushed, iclass 18, count 0 2006.168.08:27:48.00#ibcon#about to write, iclass 18, count 0 2006.168.08:27:48.00#ibcon#wrote, iclass 18, count 0 2006.168.08:27:48.00#ibcon#about to read 3, iclass 18, count 0 2006.168.08:27:48.04#ibcon#read 3, iclass 18, count 0 2006.168.08:27:48.04#ibcon#about to read 4, iclass 18, count 0 2006.168.08:27:48.04#ibcon#read 4, iclass 18, count 0 2006.168.08:27:48.04#ibcon#about to read 5, iclass 18, count 0 2006.168.08:27:48.04#ibcon#read 5, iclass 18, count 0 2006.168.08:27:48.04#ibcon#about to read 6, iclass 18, count 0 2006.168.08:27:48.04#ibcon#read 6, iclass 18, count 0 2006.168.08:27:48.04#ibcon#end of sib2, iclass 18, count 0 2006.168.08:27:48.04#ibcon#*after write, iclass 18, count 0 2006.168.08:27:48.04#ibcon#*before return 0, iclass 18, count 0 2006.168.08:27:48.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:27:48.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:27:48.04#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.08:27:48.04#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.08:27:48.04$vc4f8/va=1,8 2006.168.08:27:48.04#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.168.08:27:48.04#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.168.08:27:48.04#ibcon#ireg 11 cls_cnt 2 2006.168.08:27:48.04#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:27:48.04#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:27:48.04#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:27:48.04#ibcon#enter wrdev, iclass 20, count 2 2006.168.08:27:48.04#ibcon#first serial, iclass 20, count 2 2006.168.08:27:48.04#ibcon#enter sib2, iclass 20, count 2 2006.168.08:27:48.04#ibcon#flushed, iclass 20, count 2 2006.168.08:27:48.04#ibcon#about to write, iclass 20, count 2 2006.168.08:27:48.05#ibcon#wrote, iclass 20, count 2 2006.168.08:27:48.05#ibcon#about to read 3, iclass 20, count 2 2006.168.08:27:48.06#ibcon#read 3, iclass 20, count 2 2006.168.08:27:48.06#ibcon#about to read 4, iclass 20, count 2 2006.168.08:27:48.06#ibcon#read 4, iclass 20, count 2 2006.168.08:27:48.06#ibcon#about to read 5, iclass 20, count 2 2006.168.08:27:48.06#ibcon#read 5, iclass 20, count 2 2006.168.08:27:48.06#ibcon#about to read 6, iclass 20, count 2 2006.168.08:27:48.06#ibcon#read 6, iclass 20, count 2 2006.168.08:27:48.06#ibcon#end of sib2, iclass 20, count 2 2006.168.08:27:48.06#ibcon#*mode == 0, iclass 20, count 2 2006.168.08:27:48.06#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.168.08:27:48.06#ibcon#[25=AT01-08\r\n] 2006.168.08:27:48.06#ibcon#*before write, iclass 20, count 2 2006.168.08:27:48.06#ibcon#enter sib2, iclass 20, count 2 2006.168.08:27:48.06#ibcon#flushed, iclass 20, count 2 2006.168.08:27:48.06#ibcon#about to write, iclass 20, count 2 2006.168.08:27:48.06#ibcon#wrote, iclass 20, count 2 2006.168.08:27:48.06#ibcon#about to read 3, iclass 20, count 2 2006.168.08:27:48.10#ibcon#read 3, iclass 20, count 2 2006.168.08:27:48.10#ibcon#about to read 4, iclass 20, count 2 2006.168.08:27:48.10#ibcon#read 4, iclass 20, count 2 2006.168.08:27:48.10#ibcon#about to read 5, iclass 20, count 2 2006.168.08:27:48.10#ibcon#read 5, iclass 20, count 2 2006.168.08:27:48.10#ibcon#about to read 6, iclass 20, count 2 2006.168.08:27:48.10#ibcon#read 6, iclass 20, count 2 2006.168.08:27:48.10#ibcon#end of sib2, iclass 20, count 2 2006.168.08:27:48.10#ibcon#*after write, iclass 20, count 2 2006.168.08:27:48.10#ibcon#*before return 0, iclass 20, count 2 2006.168.08:27:48.10#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:27:48.10#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:27:48.10#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.168.08:27:48.10#ibcon#ireg 7 cls_cnt 0 2006.168.08:27:48.10#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:27:48.22#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:27:48.22#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:27:48.22#ibcon#enter wrdev, iclass 20, count 0 2006.168.08:27:48.22#ibcon#first serial, iclass 20, count 0 2006.168.08:27:48.22#ibcon#enter sib2, iclass 20, count 0 2006.168.08:27:48.22#ibcon#flushed, iclass 20, count 0 2006.168.08:27:48.22#ibcon#about to write, iclass 20, count 0 2006.168.08:27:48.22#ibcon#wrote, iclass 20, count 0 2006.168.08:27:48.22#ibcon#about to read 3, iclass 20, count 0 2006.168.08:27:48.23#ibcon#read 3, iclass 20, count 0 2006.168.08:27:48.23#ibcon#about to read 4, iclass 20, count 0 2006.168.08:27:48.23#ibcon#read 4, iclass 20, count 0 2006.168.08:27:48.23#ibcon#about to read 5, iclass 20, count 0 2006.168.08:27:48.23#ibcon#read 5, iclass 20, count 0 2006.168.08:27:48.23#ibcon#about to read 6, iclass 20, count 0 2006.168.08:27:48.23#ibcon#read 6, iclass 20, count 0 2006.168.08:27:48.23#ibcon#end of sib2, iclass 20, count 0 2006.168.08:27:48.23#ibcon#*mode == 0, iclass 20, count 0 2006.168.08:27:48.23#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.168.08:27:48.23#ibcon#[25=USB\r\n] 2006.168.08:27:48.23#ibcon#*before write, iclass 20, count 0 2006.168.08:27:48.23#ibcon#enter sib2, iclass 20, count 0 2006.168.08:27:48.23#ibcon#flushed, iclass 20, count 0 2006.168.08:27:48.23#ibcon#about to write, iclass 20, count 0 2006.168.08:27:48.23#ibcon#wrote, iclass 20, count 0 2006.168.08:27:48.23#ibcon#about to read 3, iclass 20, count 0 2006.168.08:27:48.26#ibcon#read 3, iclass 20, count 0 2006.168.08:27:48.26#ibcon#about to read 4, iclass 20, count 0 2006.168.08:27:48.26#ibcon#read 4, iclass 20, count 0 2006.168.08:27:48.26#ibcon#about to read 5, iclass 20, count 0 2006.168.08:27:48.26#ibcon#read 5, iclass 20, count 0 2006.168.08:27:48.26#ibcon#about to read 6, iclass 20, count 0 2006.168.08:27:48.26#ibcon#read 6, iclass 20, count 0 2006.168.08:27:48.26#ibcon#end of sib2, iclass 20, count 0 2006.168.08:27:48.26#ibcon#*after write, iclass 20, count 0 2006.168.08:27:48.26#ibcon#*before return 0, iclass 20, count 0 2006.168.08:27:48.26#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:27:48.26#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:27:48.26#ibcon#about to clear, iclass 20 cls_cnt 0 2006.168.08:27:48.26#ibcon#cleared, iclass 20 cls_cnt 0 2006.168.08:27:48.26$vc4f8/valo=2,572.99 2006.168.08:27:48.26#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.168.08:27:48.26#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.168.08:27:48.26#ibcon#ireg 17 cls_cnt 0 2006.168.08:27:48.26#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:27:48.26#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:27:48.26#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:27:48.26#ibcon#enter wrdev, iclass 22, count 0 2006.168.08:27:48.26#ibcon#first serial, iclass 22, count 0 2006.168.08:27:48.26#ibcon#enter sib2, iclass 22, count 0 2006.168.08:27:48.27#ibcon#flushed, iclass 22, count 0 2006.168.08:27:48.27#ibcon#about to write, iclass 22, count 0 2006.168.08:27:48.27#ibcon#wrote, iclass 22, count 0 2006.168.08:27:48.27#ibcon#about to read 3, iclass 22, count 0 2006.168.08:27:48.28#ibcon#read 3, iclass 22, count 0 2006.168.08:27:48.28#ibcon#about to read 4, iclass 22, count 0 2006.168.08:27:48.28#ibcon#read 4, iclass 22, count 0 2006.168.08:27:48.28#ibcon#about to read 5, iclass 22, count 0 2006.168.08:27:48.28#ibcon#read 5, iclass 22, count 0 2006.168.08:27:48.28#ibcon#about to read 6, iclass 22, count 0 2006.168.08:27:48.28#ibcon#read 6, iclass 22, count 0 2006.168.08:27:48.28#ibcon#end of sib2, iclass 22, count 0 2006.168.08:27:48.28#ibcon#*mode == 0, iclass 22, count 0 2006.168.08:27:48.28#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.168.08:27:48.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.08:27:48.28#ibcon#*before write, iclass 22, count 0 2006.168.08:27:48.28#ibcon#enter sib2, iclass 22, count 0 2006.168.08:27:48.28#ibcon#flushed, iclass 22, count 0 2006.168.08:27:48.28#ibcon#about to write, iclass 22, count 0 2006.168.08:27:48.28#ibcon#wrote, iclass 22, count 0 2006.168.08:27:48.28#ibcon#about to read 3, iclass 22, count 0 2006.168.08:27:48.32#ibcon#read 3, iclass 22, count 0 2006.168.08:27:48.32#ibcon#about to read 4, iclass 22, count 0 2006.168.08:27:48.32#ibcon#read 4, iclass 22, count 0 2006.168.08:27:48.32#ibcon#about to read 5, iclass 22, count 0 2006.168.08:27:48.32#ibcon#read 5, iclass 22, count 0 2006.168.08:27:48.32#ibcon#about to read 6, iclass 22, count 0 2006.168.08:27:48.32#ibcon#read 6, iclass 22, count 0 2006.168.08:27:48.32#ibcon#end of sib2, iclass 22, count 0 2006.168.08:27:48.32#ibcon#*after write, iclass 22, count 0 2006.168.08:27:48.32#ibcon#*before return 0, iclass 22, count 0 2006.168.08:27:48.32#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:27:48.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:27:48.33#ibcon#about to clear, iclass 22 cls_cnt 0 2006.168.08:27:48.33#ibcon#cleared, iclass 22 cls_cnt 0 2006.168.08:27:48.33$vc4f8/va=2,7 2006.168.08:27:48.33#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.168.08:27:48.33#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.168.08:27:48.33#ibcon#ireg 11 cls_cnt 2 2006.168.08:27:48.33#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:27:48.37#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:27:48.37#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:27:48.37#ibcon#enter wrdev, iclass 24, count 2 2006.168.08:27:48.37#ibcon#first serial, iclass 24, count 2 2006.168.08:27:48.37#ibcon#enter sib2, iclass 24, count 2 2006.168.08:27:48.37#ibcon#flushed, iclass 24, count 2 2006.168.08:27:48.37#ibcon#about to write, iclass 24, count 2 2006.168.08:27:48.37#ibcon#wrote, iclass 24, count 2 2006.168.08:27:48.37#ibcon#about to read 3, iclass 24, count 2 2006.168.08:27:48.40#ibcon#read 3, iclass 24, count 2 2006.168.08:27:48.40#ibcon#about to read 4, iclass 24, count 2 2006.168.08:27:48.40#ibcon#read 4, iclass 24, count 2 2006.168.08:27:48.40#ibcon#about to read 5, iclass 24, count 2 2006.168.08:27:48.40#ibcon#read 5, iclass 24, count 2 2006.168.08:27:48.40#ibcon#about to read 6, iclass 24, count 2 2006.168.08:27:48.40#ibcon#read 6, iclass 24, count 2 2006.168.08:27:48.40#ibcon#end of sib2, iclass 24, count 2 2006.168.08:27:48.40#ibcon#*mode == 0, iclass 24, count 2 2006.168.08:27:48.40#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.168.08:27:48.40#ibcon#[25=AT02-07\r\n] 2006.168.08:27:48.40#ibcon#*before write, iclass 24, count 2 2006.168.08:27:48.40#ibcon#enter sib2, iclass 24, count 2 2006.168.08:27:48.40#ibcon#flushed, iclass 24, count 2 2006.168.08:27:48.40#ibcon#about to write, iclass 24, count 2 2006.168.08:27:48.40#ibcon#wrote, iclass 24, count 2 2006.168.08:27:48.40#ibcon#about to read 3, iclass 24, count 2 2006.168.08:27:48.43#ibcon#read 3, iclass 24, count 2 2006.168.08:27:48.43#ibcon#about to read 4, iclass 24, count 2 2006.168.08:27:48.43#ibcon#read 4, iclass 24, count 2 2006.168.08:27:48.43#ibcon#about to read 5, iclass 24, count 2 2006.168.08:27:48.43#ibcon#read 5, iclass 24, count 2 2006.168.08:27:48.43#ibcon#about to read 6, iclass 24, count 2 2006.168.08:27:48.43#ibcon#read 6, iclass 24, count 2 2006.168.08:27:48.43#ibcon#end of sib2, iclass 24, count 2 2006.168.08:27:48.43#ibcon#*after write, iclass 24, count 2 2006.168.08:27:48.43#ibcon#*before return 0, iclass 24, count 2 2006.168.08:27:48.43#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:27:48.43#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:27:48.43#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.168.08:27:48.43#ibcon#ireg 7 cls_cnt 0 2006.168.08:27:48.43#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:27:48.55#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:27:48.55#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:27:48.55#ibcon#enter wrdev, iclass 24, count 0 2006.168.08:27:48.55#ibcon#first serial, iclass 24, count 0 2006.168.08:27:48.55#ibcon#enter sib2, iclass 24, count 0 2006.168.08:27:48.55#ibcon#flushed, iclass 24, count 0 2006.168.08:27:48.55#ibcon#about to write, iclass 24, count 0 2006.168.08:27:48.55#ibcon#wrote, iclass 24, count 0 2006.168.08:27:48.55#ibcon#about to read 3, iclass 24, count 0 2006.168.08:27:48.57#ibcon#read 3, iclass 24, count 0 2006.168.08:27:48.57#ibcon#about to read 4, iclass 24, count 0 2006.168.08:27:48.57#ibcon#read 4, iclass 24, count 0 2006.168.08:27:48.57#ibcon#about to read 5, iclass 24, count 0 2006.168.08:27:48.57#ibcon#read 5, iclass 24, count 0 2006.168.08:27:48.57#ibcon#about to read 6, iclass 24, count 0 2006.168.08:27:48.57#ibcon#read 6, iclass 24, count 0 2006.168.08:27:48.57#ibcon#end of sib2, iclass 24, count 0 2006.168.08:27:48.57#ibcon#*mode == 0, iclass 24, count 0 2006.168.08:27:48.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.168.08:27:48.57#ibcon#[25=USB\r\n] 2006.168.08:27:48.57#ibcon#*before write, iclass 24, count 0 2006.168.08:27:48.57#ibcon#enter sib2, iclass 24, count 0 2006.168.08:27:48.57#ibcon#flushed, iclass 24, count 0 2006.168.08:27:48.57#ibcon#about to write, iclass 24, count 0 2006.168.08:27:48.57#ibcon#wrote, iclass 24, count 0 2006.168.08:27:48.57#ibcon#about to read 3, iclass 24, count 0 2006.168.08:27:48.60#ibcon#read 3, iclass 24, count 0 2006.168.08:27:48.60#ibcon#about to read 4, iclass 24, count 0 2006.168.08:27:48.60#ibcon#read 4, iclass 24, count 0 2006.168.08:27:48.60#ibcon#about to read 5, iclass 24, count 0 2006.168.08:27:48.60#ibcon#read 5, iclass 24, count 0 2006.168.08:27:48.60#ibcon#about to read 6, iclass 24, count 0 2006.168.08:27:48.60#ibcon#read 6, iclass 24, count 0 2006.168.08:27:48.60#ibcon#end of sib2, iclass 24, count 0 2006.168.08:27:48.60#ibcon#*after write, iclass 24, count 0 2006.168.08:27:48.60#ibcon#*before return 0, iclass 24, count 0 2006.168.08:27:48.60#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:27:48.60#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:27:48.60#ibcon#about to clear, iclass 24 cls_cnt 0 2006.168.08:27:48.60#ibcon#cleared, iclass 24 cls_cnt 0 2006.168.08:27:48.60$vc4f8/valo=3,672.99 2006.168.08:27:48.60#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.168.08:27:48.60#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.168.08:27:48.60#ibcon#ireg 17 cls_cnt 0 2006.168.08:27:48.60#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:27:48.60#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:27:48.60#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:27:48.60#ibcon#enter wrdev, iclass 26, count 0 2006.168.08:27:48.60#ibcon#first serial, iclass 26, count 0 2006.168.08:27:48.60#ibcon#enter sib2, iclass 26, count 0 2006.168.08:27:48.61#ibcon#flushed, iclass 26, count 0 2006.168.08:27:48.61#ibcon#about to write, iclass 26, count 0 2006.168.08:27:48.61#ibcon#wrote, iclass 26, count 0 2006.168.08:27:48.61#ibcon#about to read 3, iclass 26, count 0 2006.168.08:27:48.62#ibcon#read 3, iclass 26, count 0 2006.168.08:27:48.62#ibcon#about to read 4, iclass 26, count 0 2006.168.08:27:48.62#ibcon#read 4, iclass 26, count 0 2006.168.08:27:48.62#ibcon#about to read 5, iclass 26, count 0 2006.168.08:27:48.62#ibcon#read 5, iclass 26, count 0 2006.168.08:27:48.62#ibcon#about to read 6, iclass 26, count 0 2006.168.08:27:48.62#ibcon#read 6, iclass 26, count 0 2006.168.08:27:48.62#ibcon#end of sib2, iclass 26, count 0 2006.168.08:27:48.62#ibcon#*mode == 0, iclass 26, count 0 2006.168.08:27:48.62#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.168.08:27:48.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.08:27:48.62#ibcon#*before write, iclass 26, count 0 2006.168.08:27:48.62#ibcon#enter sib2, iclass 26, count 0 2006.168.08:27:48.62#ibcon#flushed, iclass 26, count 0 2006.168.08:27:48.62#ibcon#about to write, iclass 26, count 0 2006.168.08:27:48.62#ibcon#wrote, iclass 26, count 0 2006.168.08:27:48.62#ibcon#about to read 3, iclass 26, count 0 2006.168.08:27:48.66#ibcon#read 3, iclass 26, count 0 2006.168.08:27:48.66#ibcon#about to read 4, iclass 26, count 0 2006.168.08:27:48.66#ibcon#read 4, iclass 26, count 0 2006.168.08:27:48.66#ibcon#about to read 5, iclass 26, count 0 2006.168.08:27:48.66#ibcon#read 5, iclass 26, count 0 2006.168.08:27:48.66#ibcon#about to read 6, iclass 26, count 0 2006.168.08:27:48.66#ibcon#read 6, iclass 26, count 0 2006.168.08:27:48.66#ibcon#end of sib2, iclass 26, count 0 2006.168.08:27:48.66#ibcon#*after write, iclass 26, count 0 2006.168.08:27:48.66#ibcon#*before return 0, iclass 26, count 0 2006.168.08:27:48.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:27:48.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:27:48.67#ibcon#about to clear, iclass 26 cls_cnt 0 2006.168.08:27:48.67#ibcon#cleared, iclass 26 cls_cnt 0 2006.168.08:27:48.67$vc4f8/va=3,6 2006.168.08:27:48.67#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.168.08:27:48.67#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.168.08:27:48.67#ibcon#ireg 11 cls_cnt 2 2006.168.08:27:48.67#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:27:48.71#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:27:48.71#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:27:48.71#ibcon#enter wrdev, iclass 28, count 2 2006.168.08:27:48.71#ibcon#first serial, iclass 28, count 2 2006.168.08:27:48.71#ibcon#enter sib2, iclass 28, count 2 2006.168.08:27:48.71#ibcon#flushed, iclass 28, count 2 2006.168.08:27:48.71#ibcon#about to write, iclass 28, count 2 2006.168.08:27:48.71#ibcon#wrote, iclass 28, count 2 2006.168.08:27:48.71#ibcon#about to read 3, iclass 28, count 2 2006.168.08:27:48.74#ibcon#read 3, iclass 28, count 2 2006.168.08:27:48.74#ibcon#about to read 4, iclass 28, count 2 2006.168.08:27:48.74#ibcon#read 4, iclass 28, count 2 2006.168.08:27:48.74#ibcon#about to read 5, iclass 28, count 2 2006.168.08:27:48.74#ibcon#read 5, iclass 28, count 2 2006.168.08:27:48.74#ibcon#about to read 6, iclass 28, count 2 2006.168.08:27:48.74#ibcon#read 6, iclass 28, count 2 2006.168.08:27:48.74#ibcon#end of sib2, iclass 28, count 2 2006.168.08:27:48.74#ibcon#*mode == 0, iclass 28, count 2 2006.168.08:27:48.74#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.168.08:27:48.74#ibcon#[25=AT03-06\r\n] 2006.168.08:27:48.74#ibcon#*before write, iclass 28, count 2 2006.168.08:27:48.74#ibcon#enter sib2, iclass 28, count 2 2006.168.08:27:48.74#ibcon#flushed, iclass 28, count 2 2006.168.08:27:48.74#ibcon#about to write, iclass 28, count 2 2006.168.08:27:48.74#ibcon#wrote, iclass 28, count 2 2006.168.08:27:48.74#ibcon#about to read 3, iclass 28, count 2 2006.168.08:27:48.77#ibcon#read 3, iclass 28, count 2 2006.168.08:27:48.77#ibcon#about to read 4, iclass 28, count 2 2006.168.08:27:48.77#ibcon#read 4, iclass 28, count 2 2006.168.08:27:48.77#ibcon#about to read 5, iclass 28, count 2 2006.168.08:27:48.77#ibcon#read 5, iclass 28, count 2 2006.168.08:27:48.77#ibcon#about to read 6, iclass 28, count 2 2006.168.08:27:48.77#ibcon#read 6, iclass 28, count 2 2006.168.08:27:48.77#ibcon#end of sib2, iclass 28, count 2 2006.168.08:27:48.77#ibcon#*after write, iclass 28, count 2 2006.168.08:27:48.77#ibcon#*before return 0, iclass 28, count 2 2006.168.08:27:48.77#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:27:48.77#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:27:48.77#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.168.08:27:48.77#ibcon#ireg 7 cls_cnt 0 2006.168.08:27:48.77#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:27:48.89#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:27:48.89#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:27:48.89#ibcon#enter wrdev, iclass 28, count 0 2006.168.08:27:48.89#ibcon#first serial, iclass 28, count 0 2006.168.08:27:48.89#ibcon#enter sib2, iclass 28, count 0 2006.168.08:27:48.89#ibcon#flushed, iclass 28, count 0 2006.168.08:27:48.89#ibcon#about to write, iclass 28, count 0 2006.168.08:27:48.89#ibcon#wrote, iclass 28, count 0 2006.168.08:27:48.89#ibcon#about to read 3, iclass 28, count 0 2006.168.08:27:48.91#ibcon#read 3, iclass 28, count 0 2006.168.08:27:48.91#ibcon#about to read 4, iclass 28, count 0 2006.168.08:27:48.91#ibcon#read 4, iclass 28, count 0 2006.168.08:27:48.91#ibcon#about to read 5, iclass 28, count 0 2006.168.08:27:48.91#ibcon#read 5, iclass 28, count 0 2006.168.08:27:48.91#ibcon#about to read 6, iclass 28, count 0 2006.168.08:27:48.91#ibcon#read 6, iclass 28, count 0 2006.168.08:27:48.91#ibcon#end of sib2, iclass 28, count 0 2006.168.08:27:48.91#ibcon#*mode == 0, iclass 28, count 0 2006.168.08:27:48.91#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.168.08:27:48.91#ibcon#[25=USB\r\n] 2006.168.08:27:48.91#ibcon#*before write, iclass 28, count 0 2006.168.08:27:48.91#ibcon#enter sib2, iclass 28, count 0 2006.168.08:27:48.91#ibcon#flushed, iclass 28, count 0 2006.168.08:27:48.91#ibcon#about to write, iclass 28, count 0 2006.168.08:27:48.91#ibcon#wrote, iclass 28, count 0 2006.168.08:27:48.91#ibcon#about to read 3, iclass 28, count 0 2006.168.08:27:48.94#ibcon#read 3, iclass 28, count 0 2006.168.08:27:48.94#ibcon#about to read 4, iclass 28, count 0 2006.168.08:27:48.94#ibcon#read 4, iclass 28, count 0 2006.168.08:27:48.94#ibcon#about to read 5, iclass 28, count 0 2006.168.08:27:48.94#ibcon#read 5, iclass 28, count 0 2006.168.08:27:48.94#ibcon#about to read 6, iclass 28, count 0 2006.168.08:27:48.94#ibcon#read 6, iclass 28, count 0 2006.168.08:27:48.94#ibcon#end of sib2, iclass 28, count 0 2006.168.08:27:48.94#ibcon#*after write, iclass 28, count 0 2006.168.08:27:48.94#ibcon#*before return 0, iclass 28, count 0 2006.168.08:27:48.94#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:27:48.94#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:27:48.94#ibcon#about to clear, iclass 28 cls_cnt 0 2006.168.08:27:48.94#ibcon#cleared, iclass 28 cls_cnt 0 2006.168.08:27:48.94$vc4f8/valo=4,832.99 2006.168.08:27:48.94#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.168.08:27:48.94#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.168.08:27:48.94#ibcon#ireg 17 cls_cnt 0 2006.168.08:27:48.94#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:27:48.94#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:27:48.94#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:27:48.94#ibcon#enter wrdev, iclass 30, count 0 2006.168.08:27:48.94#ibcon#first serial, iclass 30, count 0 2006.168.08:27:48.94#ibcon#enter sib2, iclass 30, count 0 2006.168.08:27:48.95#ibcon#flushed, iclass 30, count 0 2006.168.08:27:48.95#ibcon#about to write, iclass 30, count 0 2006.168.08:27:48.95#ibcon#wrote, iclass 30, count 0 2006.168.08:27:48.95#ibcon#about to read 3, iclass 30, count 0 2006.168.08:27:48.96#ibcon#read 3, iclass 30, count 0 2006.168.08:27:48.96#ibcon#about to read 4, iclass 30, count 0 2006.168.08:27:48.96#ibcon#read 4, iclass 30, count 0 2006.168.08:27:48.96#ibcon#about to read 5, iclass 30, count 0 2006.168.08:27:48.96#ibcon#read 5, iclass 30, count 0 2006.168.08:27:48.96#ibcon#about to read 6, iclass 30, count 0 2006.168.08:27:48.96#ibcon#read 6, iclass 30, count 0 2006.168.08:27:48.96#ibcon#end of sib2, iclass 30, count 0 2006.168.08:27:48.96#ibcon#*mode == 0, iclass 30, count 0 2006.168.08:27:48.96#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.168.08:27:48.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.08:27:48.96#ibcon#*before write, iclass 30, count 0 2006.168.08:27:48.96#ibcon#enter sib2, iclass 30, count 0 2006.168.08:27:48.96#ibcon#flushed, iclass 30, count 0 2006.168.08:27:48.96#ibcon#about to write, iclass 30, count 0 2006.168.08:27:48.96#ibcon#wrote, iclass 30, count 0 2006.168.08:27:48.96#ibcon#about to read 3, iclass 30, count 0 2006.168.08:27:49.00#ibcon#read 3, iclass 30, count 0 2006.168.08:27:49.00#ibcon#about to read 4, iclass 30, count 0 2006.168.08:27:49.00#ibcon#read 4, iclass 30, count 0 2006.168.08:27:49.00#ibcon#about to read 5, iclass 30, count 0 2006.168.08:27:49.00#ibcon#read 5, iclass 30, count 0 2006.168.08:27:49.00#ibcon#about to read 6, iclass 30, count 0 2006.168.08:27:49.00#ibcon#read 6, iclass 30, count 0 2006.168.08:27:49.00#ibcon#end of sib2, iclass 30, count 0 2006.168.08:27:49.00#ibcon#*after write, iclass 30, count 0 2006.168.08:27:49.00#ibcon#*before return 0, iclass 30, count 0 2006.168.08:27:49.00#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:27:49.00#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:27:49.00#ibcon#about to clear, iclass 30 cls_cnt 0 2006.168.08:27:49.00#ibcon#cleared, iclass 30 cls_cnt 0 2006.168.08:27:49.00$vc4f8/va=4,7 2006.168.08:27:49.00#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.168.08:27:49.00#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.168.08:27:49.00#ibcon#ireg 11 cls_cnt 2 2006.168.08:27:49.00#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:27:49.06#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:27:49.06#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:27:49.06#ibcon#enter wrdev, iclass 32, count 2 2006.168.08:27:49.06#ibcon#first serial, iclass 32, count 2 2006.168.08:27:49.06#ibcon#enter sib2, iclass 32, count 2 2006.168.08:27:49.06#ibcon#flushed, iclass 32, count 2 2006.168.08:27:49.06#ibcon#about to write, iclass 32, count 2 2006.168.08:27:49.06#ibcon#wrote, iclass 32, count 2 2006.168.08:27:49.06#ibcon#about to read 3, iclass 32, count 2 2006.168.08:27:49.08#ibcon#read 3, iclass 32, count 2 2006.168.08:27:49.08#ibcon#about to read 4, iclass 32, count 2 2006.168.08:27:49.08#ibcon#read 4, iclass 32, count 2 2006.168.08:27:49.08#ibcon#about to read 5, iclass 32, count 2 2006.168.08:27:49.08#ibcon#read 5, iclass 32, count 2 2006.168.08:27:49.08#ibcon#about to read 6, iclass 32, count 2 2006.168.08:27:49.08#ibcon#read 6, iclass 32, count 2 2006.168.08:27:49.08#ibcon#end of sib2, iclass 32, count 2 2006.168.08:27:49.08#ibcon#*mode == 0, iclass 32, count 2 2006.168.08:27:49.08#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.168.08:27:49.08#ibcon#[25=AT04-07\r\n] 2006.168.08:27:49.08#ibcon#*before write, iclass 32, count 2 2006.168.08:27:49.08#ibcon#enter sib2, iclass 32, count 2 2006.168.08:27:49.08#ibcon#flushed, iclass 32, count 2 2006.168.08:27:49.08#ibcon#about to write, iclass 32, count 2 2006.168.08:27:49.08#ibcon#wrote, iclass 32, count 2 2006.168.08:27:49.08#ibcon#about to read 3, iclass 32, count 2 2006.168.08:27:49.11#ibcon#read 3, iclass 32, count 2 2006.168.08:27:49.11#ibcon#about to read 4, iclass 32, count 2 2006.168.08:27:49.11#ibcon#read 4, iclass 32, count 2 2006.168.08:27:49.11#ibcon#about to read 5, iclass 32, count 2 2006.168.08:27:49.11#ibcon#read 5, iclass 32, count 2 2006.168.08:27:49.11#ibcon#about to read 6, iclass 32, count 2 2006.168.08:27:49.11#ibcon#read 6, iclass 32, count 2 2006.168.08:27:49.11#ibcon#end of sib2, iclass 32, count 2 2006.168.08:27:49.11#ibcon#*after write, iclass 32, count 2 2006.168.08:27:49.11#ibcon#*before return 0, iclass 32, count 2 2006.168.08:27:49.11#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:27:49.11#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:27:49.11#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.168.08:27:49.11#ibcon#ireg 7 cls_cnt 0 2006.168.08:27:49.11#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:27:49.23#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:27:49.23#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:27:49.23#ibcon#enter wrdev, iclass 32, count 0 2006.168.08:27:49.23#ibcon#first serial, iclass 32, count 0 2006.168.08:27:49.23#ibcon#enter sib2, iclass 32, count 0 2006.168.08:27:49.23#ibcon#flushed, iclass 32, count 0 2006.168.08:27:49.23#ibcon#about to write, iclass 32, count 0 2006.168.08:27:49.23#ibcon#wrote, iclass 32, count 0 2006.168.08:27:49.23#ibcon#about to read 3, iclass 32, count 0 2006.168.08:27:49.25#ibcon#read 3, iclass 32, count 0 2006.168.08:27:49.25#ibcon#about to read 4, iclass 32, count 0 2006.168.08:27:49.25#ibcon#read 4, iclass 32, count 0 2006.168.08:27:49.25#ibcon#about to read 5, iclass 32, count 0 2006.168.08:27:49.25#ibcon#read 5, iclass 32, count 0 2006.168.08:27:49.25#ibcon#about to read 6, iclass 32, count 0 2006.168.08:27:49.25#ibcon#read 6, iclass 32, count 0 2006.168.08:27:49.25#ibcon#end of sib2, iclass 32, count 0 2006.168.08:27:49.25#ibcon#*mode == 0, iclass 32, count 0 2006.168.08:27:49.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.168.08:27:49.25#ibcon#[25=USB\r\n] 2006.168.08:27:49.25#ibcon#*before write, iclass 32, count 0 2006.168.08:27:49.25#ibcon#enter sib2, iclass 32, count 0 2006.168.08:27:49.25#ibcon#flushed, iclass 32, count 0 2006.168.08:27:49.25#ibcon#about to write, iclass 32, count 0 2006.168.08:27:49.25#ibcon#wrote, iclass 32, count 0 2006.168.08:27:49.25#ibcon#about to read 3, iclass 32, count 0 2006.168.08:27:49.28#ibcon#read 3, iclass 32, count 0 2006.168.08:27:49.28#ibcon#about to read 4, iclass 32, count 0 2006.168.08:27:49.28#ibcon#read 4, iclass 32, count 0 2006.168.08:27:49.28#ibcon#about to read 5, iclass 32, count 0 2006.168.08:27:49.28#ibcon#read 5, iclass 32, count 0 2006.168.08:27:49.28#ibcon#about to read 6, iclass 32, count 0 2006.168.08:27:49.28#ibcon#read 6, iclass 32, count 0 2006.168.08:27:49.28#ibcon#end of sib2, iclass 32, count 0 2006.168.08:27:49.28#ibcon#*after write, iclass 32, count 0 2006.168.08:27:49.28#ibcon#*before return 0, iclass 32, count 0 2006.168.08:27:49.28#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:27:49.28#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:27:49.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.168.08:27:49.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.168.08:27:49.28$vc4f8/valo=5,652.99 2006.168.08:27:49.28#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.168.08:27:49.28#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.168.08:27:49.28#ibcon#ireg 17 cls_cnt 0 2006.168.08:27:49.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:27:49.28#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:27:49.28#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:27:49.28#ibcon#enter wrdev, iclass 34, count 0 2006.168.08:27:49.28#ibcon#first serial, iclass 34, count 0 2006.168.08:27:49.28#ibcon#enter sib2, iclass 34, count 0 2006.168.08:27:49.29#ibcon#flushed, iclass 34, count 0 2006.168.08:27:49.29#ibcon#about to write, iclass 34, count 0 2006.168.08:27:49.29#ibcon#wrote, iclass 34, count 0 2006.168.08:27:49.29#ibcon#about to read 3, iclass 34, count 0 2006.168.08:27:49.30#ibcon#read 3, iclass 34, count 0 2006.168.08:27:49.30#ibcon#about to read 4, iclass 34, count 0 2006.168.08:27:49.30#ibcon#read 4, iclass 34, count 0 2006.168.08:27:49.30#ibcon#about to read 5, iclass 34, count 0 2006.168.08:27:49.30#ibcon#read 5, iclass 34, count 0 2006.168.08:27:49.30#ibcon#about to read 6, iclass 34, count 0 2006.168.08:27:49.30#ibcon#read 6, iclass 34, count 0 2006.168.08:27:49.30#ibcon#end of sib2, iclass 34, count 0 2006.168.08:27:49.30#ibcon#*mode == 0, iclass 34, count 0 2006.168.08:27:49.30#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.168.08:27:49.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.08:27:49.30#ibcon#*before write, iclass 34, count 0 2006.168.08:27:49.30#ibcon#enter sib2, iclass 34, count 0 2006.168.08:27:49.30#ibcon#flushed, iclass 34, count 0 2006.168.08:27:49.30#ibcon#about to write, iclass 34, count 0 2006.168.08:27:49.30#ibcon#wrote, iclass 34, count 0 2006.168.08:27:49.30#ibcon#about to read 3, iclass 34, count 0 2006.168.08:27:49.34#ibcon#read 3, iclass 34, count 0 2006.168.08:27:49.34#ibcon#about to read 4, iclass 34, count 0 2006.168.08:27:49.34#ibcon#read 4, iclass 34, count 0 2006.168.08:27:49.34#ibcon#about to read 5, iclass 34, count 0 2006.168.08:27:49.34#ibcon#read 5, iclass 34, count 0 2006.168.08:27:49.34#ibcon#about to read 6, iclass 34, count 0 2006.168.08:27:49.34#ibcon#read 6, iclass 34, count 0 2006.168.08:27:49.34#ibcon#end of sib2, iclass 34, count 0 2006.168.08:27:49.34#ibcon#*after write, iclass 34, count 0 2006.168.08:27:49.34#ibcon#*before return 0, iclass 34, count 0 2006.168.08:27:49.34#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:27:49.34#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:27:49.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.168.08:27:49.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.168.08:27:49.34$vc4f8/va=5,7 2006.168.08:27:49.34#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.168.08:27:49.34#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.168.08:27:49.34#ibcon#ireg 11 cls_cnt 2 2006.168.08:27:49.34#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:27:49.40#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:27:49.40#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:27:49.40#ibcon#enter wrdev, iclass 36, count 2 2006.168.08:27:49.40#ibcon#first serial, iclass 36, count 2 2006.168.08:27:49.40#ibcon#enter sib2, iclass 36, count 2 2006.168.08:27:49.40#ibcon#flushed, iclass 36, count 2 2006.168.08:27:49.40#ibcon#about to write, iclass 36, count 2 2006.168.08:27:49.40#ibcon#wrote, iclass 36, count 2 2006.168.08:27:49.40#ibcon#about to read 3, iclass 36, count 2 2006.168.08:27:49.42#ibcon#read 3, iclass 36, count 2 2006.168.08:27:49.42#ibcon#about to read 4, iclass 36, count 2 2006.168.08:27:49.42#ibcon#read 4, iclass 36, count 2 2006.168.08:27:49.42#ibcon#about to read 5, iclass 36, count 2 2006.168.08:27:49.42#ibcon#read 5, iclass 36, count 2 2006.168.08:27:49.42#ibcon#about to read 6, iclass 36, count 2 2006.168.08:27:49.42#ibcon#read 6, iclass 36, count 2 2006.168.08:27:49.42#ibcon#end of sib2, iclass 36, count 2 2006.168.08:27:49.42#ibcon#*mode == 0, iclass 36, count 2 2006.168.08:27:49.42#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.168.08:27:49.42#ibcon#[25=AT05-07\r\n] 2006.168.08:27:49.42#ibcon#*before write, iclass 36, count 2 2006.168.08:27:49.42#ibcon#enter sib2, iclass 36, count 2 2006.168.08:27:49.42#ibcon#flushed, iclass 36, count 2 2006.168.08:27:49.42#ibcon#about to write, iclass 36, count 2 2006.168.08:27:49.42#ibcon#wrote, iclass 36, count 2 2006.168.08:27:49.42#ibcon#about to read 3, iclass 36, count 2 2006.168.08:27:49.45#ibcon#read 3, iclass 36, count 2 2006.168.08:27:49.45#ibcon#about to read 4, iclass 36, count 2 2006.168.08:27:49.45#ibcon#read 4, iclass 36, count 2 2006.168.08:27:49.45#ibcon#about to read 5, iclass 36, count 2 2006.168.08:27:49.45#ibcon#read 5, iclass 36, count 2 2006.168.08:27:49.45#ibcon#about to read 6, iclass 36, count 2 2006.168.08:27:49.45#ibcon#read 6, iclass 36, count 2 2006.168.08:27:49.45#ibcon#end of sib2, iclass 36, count 2 2006.168.08:27:49.45#ibcon#*after write, iclass 36, count 2 2006.168.08:27:49.45#ibcon#*before return 0, iclass 36, count 2 2006.168.08:27:49.45#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:27:49.45#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:27:49.45#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.168.08:27:49.45#ibcon#ireg 7 cls_cnt 0 2006.168.08:27:49.45#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:27:49.57#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:27:49.57#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:27:49.57#ibcon#enter wrdev, iclass 36, count 0 2006.168.08:27:49.57#ibcon#first serial, iclass 36, count 0 2006.168.08:27:49.57#ibcon#enter sib2, iclass 36, count 0 2006.168.08:27:49.57#ibcon#flushed, iclass 36, count 0 2006.168.08:27:49.57#ibcon#about to write, iclass 36, count 0 2006.168.08:27:49.57#ibcon#wrote, iclass 36, count 0 2006.168.08:27:49.57#ibcon#about to read 3, iclass 36, count 0 2006.168.08:27:49.59#ibcon#read 3, iclass 36, count 0 2006.168.08:27:49.59#ibcon#about to read 4, iclass 36, count 0 2006.168.08:27:49.59#ibcon#read 4, iclass 36, count 0 2006.168.08:27:49.59#ibcon#about to read 5, iclass 36, count 0 2006.168.08:27:49.59#ibcon#read 5, iclass 36, count 0 2006.168.08:27:49.59#ibcon#about to read 6, iclass 36, count 0 2006.168.08:27:49.59#ibcon#read 6, iclass 36, count 0 2006.168.08:27:49.59#ibcon#end of sib2, iclass 36, count 0 2006.168.08:27:49.59#ibcon#*mode == 0, iclass 36, count 0 2006.168.08:27:49.59#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.168.08:27:49.59#ibcon#[25=USB\r\n] 2006.168.08:27:49.59#ibcon#*before write, iclass 36, count 0 2006.168.08:27:49.59#ibcon#enter sib2, iclass 36, count 0 2006.168.08:27:49.59#ibcon#flushed, iclass 36, count 0 2006.168.08:27:49.59#ibcon#about to write, iclass 36, count 0 2006.168.08:27:49.59#ibcon#wrote, iclass 36, count 0 2006.168.08:27:49.59#ibcon#about to read 3, iclass 36, count 0 2006.168.08:27:49.62#ibcon#read 3, iclass 36, count 0 2006.168.08:27:49.62#ibcon#about to read 4, iclass 36, count 0 2006.168.08:27:49.62#ibcon#read 4, iclass 36, count 0 2006.168.08:27:49.62#ibcon#about to read 5, iclass 36, count 0 2006.168.08:27:49.62#ibcon#read 5, iclass 36, count 0 2006.168.08:27:49.62#ibcon#about to read 6, iclass 36, count 0 2006.168.08:27:49.62#ibcon#read 6, iclass 36, count 0 2006.168.08:27:49.62#ibcon#end of sib2, iclass 36, count 0 2006.168.08:27:49.62#ibcon#*after write, iclass 36, count 0 2006.168.08:27:49.62#ibcon#*before return 0, iclass 36, count 0 2006.168.08:27:49.62#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:27:49.62#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:27:49.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.168.08:27:49.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.168.08:27:49.62$vc4f8/valo=6,772.99 2006.168.08:27:49.62#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.168.08:27:49.62#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.168.08:27:49.62#ibcon#ireg 17 cls_cnt 0 2006.168.08:27:49.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:27:49.62#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:27:49.62#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:27:49.62#ibcon#enter wrdev, iclass 38, count 0 2006.168.08:27:49.62#ibcon#first serial, iclass 38, count 0 2006.168.08:27:49.62#ibcon#enter sib2, iclass 38, count 0 2006.168.08:27:49.63#ibcon#flushed, iclass 38, count 0 2006.168.08:27:49.63#ibcon#about to write, iclass 38, count 0 2006.168.08:27:49.63#ibcon#wrote, iclass 38, count 0 2006.168.08:27:49.63#ibcon#about to read 3, iclass 38, count 0 2006.168.08:27:49.64#ibcon#read 3, iclass 38, count 0 2006.168.08:27:49.64#ibcon#about to read 4, iclass 38, count 0 2006.168.08:27:49.64#ibcon#read 4, iclass 38, count 0 2006.168.08:27:49.64#ibcon#about to read 5, iclass 38, count 0 2006.168.08:27:49.64#ibcon#read 5, iclass 38, count 0 2006.168.08:27:49.64#ibcon#about to read 6, iclass 38, count 0 2006.168.08:27:49.64#ibcon#read 6, iclass 38, count 0 2006.168.08:27:49.64#ibcon#end of sib2, iclass 38, count 0 2006.168.08:27:49.64#ibcon#*mode == 0, iclass 38, count 0 2006.168.08:27:49.64#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.168.08:27:49.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.08:27:49.64#ibcon#*before write, iclass 38, count 0 2006.168.08:27:49.64#ibcon#enter sib2, iclass 38, count 0 2006.168.08:27:49.64#ibcon#flushed, iclass 38, count 0 2006.168.08:27:49.64#ibcon#about to write, iclass 38, count 0 2006.168.08:27:49.64#ibcon#wrote, iclass 38, count 0 2006.168.08:27:49.64#ibcon#about to read 3, iclass 38, count 0 2006.168.08:27:49.68#ibcon#read 3, iclass 38, count 0 2006.168.08:27:49.68#ibcon#about to read 4, iclass 38, count 0 2006.168.08:27:49.68#ibcon#read 4, iclass 38, count 0 2006.168.08:27:49.68#ibcon#about to read 5, iclass 38, count 0 2006.168.08:27:49.68#ibcon#read 5, iclass 38, count 0 2006.168.08:27:49.68#ibcon#about to read 6, iclass 38, count 0 2006.168.08:27:49.68#ibcon#read 6, iclass 38, count 0 2006.168.08:27:49.68#ibcon#end of sib2, iclass 38, count 0 2006.168.08:27:49.68#ibcon#*after write, iclass 38, count 0 2006.168.08:27:49.68#ibcon#*before return 0, iclass 38, count 0 2006.168.08:27:49.68#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:27:49.68#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:27:49.68#ibcon#about to clear, iclass 38 cls_cnt 0 2006.168.08:27:49.68#ibcon#cleared, iclass 38 cls_cnt 0 2006.168.08:27:49.69$vc4f8/va=6,6 2006.168.08:27:49.69#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.168.08:27:49.69#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.168.08:27:49.69#ibcon#ireg 11 cls_cnt 2 2006.168.08:27:49.69#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:27:49.73#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:27:49.73#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:27:49.73#ibcon#enter wrdev, iclass 40, count 2 2006.168.08:27:49.73#ibcon#first serial, iclass 40, count 2 2006.168.08:27:49.73#ibcon#enter sib2, iclass 40, count 2 2006.168.08:27:49.73#ibcon#flushed, iclass 40, count 2 2006.168.08:27:49.73#ibcon#about to write, iclass 40, count 2 2006.168.08:27:49.73#ibcon#wrote, iclass 40, count 2 2006.168.08:27:49.73#ibcon#about to read 3, iclass 40, count 2 2006.168.08:27:49.75#ibcon#read 3, iclass 40, count 2 2006.168.08:27:49.75#ibcon#about to read 4, iclass 40, count 2 2006.168.08:27:49.75#ibcon#read 4, iclass 40, count 2 2006.168.08:27:49.75#ibcon#about to read 5, iclass 40, count 2 2006.168.08:27:49.75#ibcon#read 5, iclass 40, count 2 2006.168.08:27:49.75#ibcon#about to read 6, iclass 40, count 2 2006.168.08:27:49.75#ibcon#read 6, iclass 40, count 2 2006.168.08:27:49.75#ibcon#end of sib2, iclass 40, count 2 2006.168.08:27:49.75#ibcon#*mode == 0, iclass 40, count 2 2006.168.08:27:49.75#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.168.08:27:49.75#ibcon#[25=AT06-06\r\n] 2006.168.08:27:49.75#ibcon#*before write, iclass 40, count 2 2006.168.08:27:49.75#ibcon#enter sib2, iclass 40, count 2 2006.168.08:27:49.75#ibcon#flushed, iclass 40, count 2 2006.168.08:27:49.75#ibcon#about to write, iclass 40, count 2 2006.168.08:27:49.75#ibcon#wrote, iclass 40, count 2 2006.168.08:27:49.75#ibcon#about to read 3, iclass 40, count 2 2006.168.08:27:49.78#ibcon#read 3, iclass 40, count 2 2006.168.08:27:49.78#ibcon#about to read 4, iclass 40, count 2 2006.168.08:27:49.78#ibcon#read 4, iclass 40, count 2 2006.168.08:27:49.78#ibcon#about to read 5, iclass 40, count 2 2006.168.08:27:49.78#ibcon#read 5, iclass 40, count 2 2006.168.08:27:49.78#ibcon#about to read 6, iclass 40, count 2 2006.168.08:27:49.78#ibcon#read 6, iclass 40, count 2 2006.168.08:27:49.78#ibcon#end of sib2, iclass 40, count 2 2006.168.08:27:49.78#ibcon#*after write, iclass 40, count 2 2006.168.08:27:49.78#ibcon#*before return 0, iclass 40, count 2 2006.168.08:27:49.78#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:27:49.78#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:27:49.78#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.168.08:27:49.78#ibcon#ireg 7 cls_cnt 0 2006.168.08:27:49.78#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:27:49.90#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:27:49.90#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:27:49.90#ibcon#enter wrdev, iclass 40, count 0 2006.168.08:27:49.90#ibcon#first serial, iclass 40, count 0 2006.168.08:27:49.90#ibcon#enter sib2, iclass 40, count 0 2006.168.08:27:49.90#ibcon#flushed, iclass 40, count 0 2006.168.08:27:49.90#ibcon#about to write, iclass 40, count 0 2006.168.08:27:49.90#ibcon#wrote, iclass 40, count 0 2006.168.08:27:49.90#ibcon#about to read 3, iclass 40, count 0 2006.168.08:27:49.92#ibcon#read 3, iclass 40, count 0 2006.168.08:27:49.92#ibcon#about to read 4, iclass 40, count 0 2006.168.08:27:49.92#ibcon#read 4, iclass 40, count 0 2006.168.08:27:49.92#ibcon#about to read 5, iclass 40, count 0 2006.168.08:27:49.92#ibcon#read 5, iclass 40, count 0 2006.168.08:27:49.92#ibcon#about to read 6, iclass 40, count 0 2006.168.08:27:49.92#ibcon#read 6, iclass 40, count 0 2006.168.08:27:49.92#ibcon#end of sib2, iclass 40, count 0 2006.168.08:27:49.92#ibcon#*mode == 0, iclass 40, count 0 2006.168.08:27:49.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.168.08:27:49.92#ibcon#[25=USB\r\n] 2006.168.08:27:49.92#ibcon#*before write, iclass 40, count 0 2006.168.08:27:49.92#ibcon#enter sib2, iclass 40, count 0 2006.168.08:27:49.92#ibcon#flushed, iclass 40, count 0 2006.168.08:27:49.92#ibcon#about to write, iclass 40, count 0 2006.168.08:27:49.92#ibcon#wrote, iclass 40, count 0 2006.168.08:27:49.92#ibcon#about to read 3, iclass 40, count 0 2006.168.08:27:49.95#ibcon#read 3, iclass 40, count 0 2006.168.08:27:49.95#ibcon#about to read 4, iclass 40, count 0 2006.168.08:27:49.95#ibcon#read 4, iclass 40, count 0 2006.168.08:27:49.95#ibcon#about to read 5, iclass 40, count 0 2006.168.08:27:49.95#ibcon#read 5, iclass 40, count 0 2006.168.08:27:49.95#ibcon#about to read 6, iclass 40, count 0 2006.168.08:27:49.95#ibcon#read 6, iclass 40, count 0 2006.168.08:27:49.95#ibcon#end of sib2, iclass 40, count 0 2006.168.08:27:49.95#ibcon#*after write, iclass 40, count 0 2006.168.08:27:49.95#ibcon#*before return 0, iclass 40, count 0 2006.168.08:27:49.95#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:27:49.95#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:27:49.95#ibcon#about to clear, iclass 40 cls_cnt 0 2006.168.08:27:49.95#ibcon#cleared, iclass 40 cls_cnt 0 2006.168.08:27:49.95$vc4f8/valo=7,832.99 2006.168.08:27:49.95#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.168.08:27:49.95#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.168.08:27:49.95#ibcon#ireg 17 cls_cnt 0 2006.168.08:27:49.95#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:27:49.95#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:27:49.95#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:27:49.95#ibcon#enter wrdev, iclass 4, count 0 2006.168.08:27:49.95#ibcon#first serial, iclass 4, count 0 2006.168.08:27:49.95#ibcon#enter sib2, iclass 4, count 0 2006.168.08:27:49.95#ibcon#flushed, iclass 4, count 0 2006.168.08:27:49.95#ibcon#about to write, iclass 4, count 0 2006.168.08:27:49.95#ibcon#wrote, iclass 4, count 0 2006.168.08:27:49.95#ibcon#about to read 3, iclass 4, count 0 2006.168.08:27:49.97#ibcon#read 3, iclass 4, count 0 2006.168.08:27:49.97#ibcon#about to read 4, iclass 4, count 0 2006.168.08:27:49.97#ibcon#read 4, iclass 4, count 0 2006.168.08:27:49.97#ibcon#about to read 5, iclass 4, count 0 2006.168.08:27:49.97#ibcon#read 5, iclass 4, count 0 2006.168.08:27:49.97#ibcon#about to read 6, iclass 4, count 0 2006.168.08:27:49.97#ibcon#read 6, iclass 4, count 0 2006.168.08:27:49.97#ibcon#end of sib2, iclass 4, count 0 2006.168.08:27:49.97#ibcon#*mode == 0, iclass 4, count 0 2006.168.08:27:49.97#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.168.08:27:49.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.08:27:49.97#ibcon#*before write, iclass 4, count 0 2006.168.08:27:49.97#ibcon#enter sib2, iclass 4, count 0 2006.168.08:27:49.97#ibcon#flushed, iclass 4, count 0 2006.168.08:27:49.97#ibcon#about to write, iclass 4, count 0 2006.168.08:27:49.97#ibcon#wrote, iclass 4, count 0 2006.168.08:27:49.97#ibcon#about to read 3, iclass 4, count 0 2006.168.08:27:50.01#ibcon#read 3, iclass 4, count 0 2006.168.08:27:50.01#ibcon#about to read 4, iclass 4, count 0 2006.168.08:27:50.01#ibcon#read 4, iclass 4, count 0 2006.168.08:27:50.01#ibcon#about to read 5, iclass 4, count 0 2006.168.08:27:50.01#ibcon#read 5, iclass 4, count 0 2006.168.08:27:50.01#ibcon#about to read 6, iclass 4, count 0 2006.168.08:27:50.01#ibcon#read 6, iclass 4, count 0 2006.168.08:27:50.01#ibcon#end of sib2, iclass 4, count 0 2006.168.08:27:50.01#ibcon#*after write, iclass 4, count 0 2006.168.08:27:50.01#ibcon#*before return 0, iclass 4, count 0 2006.168.08:27:50.01#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:27:50.01#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:27:50.01#ibcon#about to clear, iclass 4 cls_cnt 0 2006.168.08:27:50.01#ibcon#cleared, iclass 4 cls_cnt 0 2006.168.08:27:50.01$vc4f8/va=7,6 2006.168.08:27:50.01#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.168.08:27:50.01#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.168.08:27:50.01#ibcon#ireg 11 cls_cnt 2 2006.168.08:27:50.01#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:27:50.07#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:27:50.07#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:27:50.07#ibcon#enter wrdev, iclass 6, count 2 2006.168.08:27:50.07#ibcon#first serial, iclass 6, count 2 2006.168.08:27:50.07#ibcon#enter sib2, iclass 6, count 2 2006.168.08:27:50.07#ibcon#flushed, iclass 6, count 2 2006.168.08:27:50.07#ibcon#about to write, iclass 6, count 2 2006.168.08:27:50.07#ibcon#wrote, iclass 6, count 2 2006.168.08:27:50.07#ibcon#about to read 3, iclass 6, count 2 2006.168.08:27:50.09#ibcon#read 3, iclass 6, count 2 2006.168.08:27:50.09#ibcon#about to read 4, iclass 6, count 2 2006.168.08:27:50.09#ibcon#read 4, iclass 6, count 2 2006.168.08:27:50.09#ibcon#about to read 5, iclass 6, count 2 2006.168.08:27:50.09#ibcon#read 5, iclass 6, count 2 2006.168.08:27:50.09#ibcon#about to read 6, iclass 6, count 2 2006.168.08:27:50.09#ibcon#read 6, iclass 6, count 2 2006.168.08:27:50.09#ibcon#end of sib2, iclass 6, count 2 2006.168.08:27:50.09#ibcon#*mode == 0, iclass 6, count 2 2006.168.08:27:50.09#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.168.08:27:50.09#ibcon#[25=AT07-06\r\n] 2006.168.08:27:50.09#ibcon#*before write, iclass 6, count 2 2006.168.08:27:50.09#ibcon#enter sib2, iclass 6, count 2 2006.168.08:27:50.09#ibcon#flushed, iclass 6, count 2 2006.168.08:27:50.09#ibcon#about to write, iclass 6, count 2 2006.168.08:27:50.09#ibcon#wrote, iclass 6, count 2 2006.168.08:27:50.09#ibcon#about to read 3, iclass 6, count 2 2006.168.08:27:50.12#ibcon#read 3, iclass 6, count 2 2006.168.08:27:50.12#ibcon#about to read 4, iclass 6, count 2 2006.168.08:27:50.12#ibcon#read 4, iclass 6, count 2 2006.168.08:27:50.12#ibcon#about to read 5, iclass 6, count 2 2006.168.08:27:50.12#ibcon#read 5, iclass 6, count 2 2006.168.08:27:50.12#ibcon#about to read 6, iclass 6, count 2 2006.168.08:27:50.12#ibcon#read 6, iclass 6, count 2 2006.168.08:27:50.12#ibcon#end of sib2, iclass 6, count 2 2006.168.08:27:50.12#ibcon#*after write, iclass 6, count 2 2006.168.08:27:50.12#ibcon#*before return 0, iclass 6, count 2 2006.168.08:27:50.12#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:27:50.12#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:27:50.12#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.168.08:27:50.12#ibcon#ireg 7 cls_cnt 0 2006.168.08:27:50.12#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:27:50.24#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:27:50.24#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:27:50.24#ibcon#enter wrdev, iclass 6, count 0 2006.168.08:27:50.24#ibcon#first serial, iclass 6, count 0 2006.168.08:27:50.24#ibcon#enter sib2, iclass 6, count 0 2006.168.08:27:50.24#ibcon#flushed, iclass 6, count 0 2006.168.08:27:50.24#ibcon#about to write, iclass 6, count 0 2006.168.08:27:50.24#ibcon#wrote, iclass 6, count 0 2006.168.08:27:50.24#ibcon#about to read 3, iclass 6, count 0 2006.168.08:27:50.26#ibcon#read 3, iclass 6, count 0 2006.168.08:27:50.26#ibcon#about to read 4, iclass 6, count 0 2006.168.08:27:50.26#ibcon#read 4, iclass 6, count 0 2006.168.08:27:50.26#ibcon#about to read 5, iclass 6, count 0 2006.168.08:27:50.26#ibcon#read 5, iclass 6, count 0 2006.168.08:27:50.26#ibcon#about to read 6, iclass 6, count 0 2006.168.08:27:50.26#ibcon#read 6, iclass 6, count 0 2006.168.08:27:50.26#ibcon#end of sib2, iclass 6, count 0 2006.168.08:27:50.26#ibcon#*mode == 0, iclass 6, count 0 2006.168.08:27:50.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.168.08:27:50.26#ibcon#[25=USB\r\n] 2006.168.08:27:50.26#ibcon#*before write, iclass 6, count 0 2006.168.08:27:50.26#ibcon#enter sib2, iclass 6, count 0 2006.168.08:27:50.26#ibcon#flushed, iclass 6, count 0 2006.168.08:27:50.26#ibcon#about to write, iclass 6, count 0 2006.168.08:27:50.26#ibcon#wrote, iclass 6, count 0 2006.168.08:27:50.26#ibcon#about to read 3, iclass 6, count 0 2006.168.08:27:50.29#ibcon#read 3, iclass 6, count 0 2006.168.08:27:50.29#ibcon#about to read 4, iclass 6, count 0 2006.168.08:27:50.29#ibcon#read 4, iclass 6, count 0 2006.168.08:27:50.29#ibcon#about to read 5, iclass 6, count 0 2006.168.08:27:50.29#ibcon#read 5, iclass 6, count 0 2006.168.08:27:50.29#ibcon#about to read 6, iclass 6, count 0 2006.168.08:27:50.29#ibcon#read 6, iclass 6, count 0 2006.168.08:27:50.29#ibcon#end of sib2, iclass 6, count 0 2006.168.08:27:50.29#ibcon#*after write, iclass 6, count 0 2006.168.08:27:50.29#ibcon#*before return 0, iclass 6, count 0 2006.168.08:27:50.29#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:27:50.29#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:27:50.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.168.08:27:50.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.168.08:27:50.29$vc4f8/valo=8,852.99 2006.168.08:27:50.29#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.168.08:27:50.29#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.168.08:27:50.29#ibcon#ireg 17 cls_cnt 0 2006.168.08:27:50.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:27:50.29#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:27:50.29#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:27:50.29#ibcon#enter wrdev, iclass 10, count 0 2006.168.08:27:50.29#ibcon#first serial, iclass 10, count 0 2006.168.08:27:50.29#ibcon#enter sib2, iclass 10, count 0 2006.168.08:27:50.29#ibcon#flushed, iclass 10, count 0 2006.168.08:27:50.29#ibcon#about to write, iclass 10, count 0 2006.168.08:27:50.29#ibcon#wrote, iclass 10, count 0 2006.168.08:27:50.29#ibcon#about to read 3, iclass 10, count 0 2006.168.08:27:50.31#ibcon#read 3, iclass 10, count 0 2006.168.08:27:50.31#ibcon#about to read 4, iclass 10, count 0 2006.168.08:27:50.31#ibcon#read 4, iclass 10, count 0 2006.168.08:27:50.31#ibcon#about to read 5, iclass 10, count 0 2006.168.08:27:50.31#ibcon#read 5, iclass 10, count 0 2006.168.08:27:50.31#ibcon#about to read 6, iclass 10, count 0 2006.168.08:27:50.31#ibcon#read 6, iclass 10, count 0 2006.168.08:27:50.31#ibcon#end of sib2, iclass 10, count 0 2006.168.08:27:50.31#ibcon#*mode == 0, iclass 10, count 0 2006.168.08:27:50.31#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.168.08:27:50.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.08:27:50.31#ibcon#*before write, iclass 10, count 0 2006.168.08:27:50.31#ibcon#enter sib2, iclass 10, count 0 2006.168.08:27:50.31#ibcon#flushed, iclass 10, count 0 2006.168.08:27:50.31#ibcon#about to write, iclass 10, count 0 2006.168.08:27:50.31#ibcon#wrote, iclass 10, count 0 2006.168.08:27:50.31#ibcon#about to read 3, iclass 10, count 0 2006.168.08:27:50.35#ibcon#read 3, iclass 10, count 0 2006.168.08:27:50.35#ibcon#about to read 4, iclass 10, count 0 2006.168.08:27:50.35#ibcon#read 4, iclass 10, count 0 2006.168.08:27:50.35#ibcon#about to read 5, iclass 10, count 0 2006.168.08:27:50.35#ibcon#read 5, iclass 10, count 0 2006.168.08:27:50.35#ibcon#about to read 6, iclass 10, count 0 2006.168.08:27:50.35#ibcon#read 6, iclass 10, count 0 2006.168.08:27:50.35#ibcon#end of sib2, iclass 10, count 0 2006.168.08:27:50.35#ibcon#*after write, iclass 10, count 0 2006.168.08:27:50.35#ibcon#*before return 0, iclass 10, count 0 2006.168.08:27:50.35#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:27:50.35#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:27:50.35#ibcon#about to clear, iclass 10 cls_cnt 0 2006.168.08:27:50.35#ibcon#cleared, iclass 10 cls_cnt 0 2006.168.08:27:50.35$vc4f8/va=8,7 2006.168.08:27:50.35#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.168.08:27:50.35#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.168.08:27:50.35#ibcon#ireg 11 cls_cnt 2 2006.168.08:27:50.35#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:27:50.41#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:27:50.41#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:27:50.41#ibcon#enter wrdev, iclass 12, count 2 2006.168.08:27:50.41#ibcon#first serial, iclass 12, count 2 2006.168.08:27:50.41#ibcon#enter sib2, iclass 12, count 2 2006.168.08:27:50.41#ibcon#flushed, iclass 12, count 2 2006.168.08:27:50.41#ibcon#about to write, iclass 12, count 2 2006.168.08:27:50.41#ibcon#wrote, iclass 12, count 2 2006.168.08:27:50.41#ibcon#about to read 3, iclass 12, count 2 2006.168.08:27:50.43#ibcon#read 3, iclass 12, count 2 2006.168.08:27:50.43#ibcon#about to read 4, iclass 12, count 2 2006.168.08:27:50.43#ibcon#read 4, iclass 12, count 2 2006.168.08:27:50.43#ibcon#about to read 5, iclass 12, count 2 2006.168.08:27:50.43#ibcon#read 5, iclass 12, count 2 2006.168.08:27:50.43#ibcon#about to read 6, iclass 12, count 2 2006.168.08:27:50.43#ibcon#read 6, iclass 12, count 2 2006.168.08:27:50.43#ibcon#end of sib2, iclass 12, count 2 2006.168.08:27:50.43#ibcon#*mode == 0, iclass 12, count 2 2006.168.08:27:50.43#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.168.08:27:50.43#ibcon#[25=AT08-07\r\n] 2006.168.08:27:50.43#ibcon#*before write, iclass 12, count 2 2006.168.08:27:50.43#ibcon#enter sib2, iclass 12, count 2 2006.168.08:27:50.43#ibcon#flushed, iclass 12, count 2 2006.168.08:27:50.43#ibcon#about to write, iclass 12, count 2 2006.168.08:27:50.43#ibcon#wrote, iclass 12, count 2 2006.168.08:27:50.43#ibcon#about to read 3, iclass 12, count 2 2006.168.08:27:50.46#ibcon#read 3, iclass 12, count 2 2006.168.08:27:50.46#ibcon#about to read 4, iclass 12, count 2 2006.168.08:27:50.46#ibcon#read 4, iclass 12, count 2 2006.168.08:27:50.46#ibcon#about to read 5, iclass 12, count 2 2006.168.08:27:50.46#ibcon#read 5, iclass 12, count 2 2006.168.08:27:50.46#ibcon#about to read 6, iclass 12, count 2 2006.168.08:27:50.46#ibcon#read 6, iclass 12, count 2 2006.168.08:27:50.46#ibcon#end of sib2, iclass 12, count 2 2006.168.08:27:50.46#ibcon#*after write, iclass 12, count 2 2006.168.08:27:50.46#ibcon#*before return 0, iclass 12, count 2 2006.168.08:27:50.46#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:27:50.46#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:27:50.46#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.168.08:27:50.46#ibcon#ireg 7 cls_cnt 0 2006.168.08:27:50.46#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:27:50.58#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:27:50.58#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:27:50.58#ibcon#enter wrdev, iclass 12, count 0 2006.168.08:27:50.58#ibcon#first serial, iclass 12, count 0 2006.168.08:27:50.58#ibcon#enter sib2, iclass 12, count 0 2006.168.08:27:50.58#ibcon#flushed, iclass 12, count 0 2006.168.08:27:50.58#ibcon#about to write, iclass 12, count 0 2006.168.08:27:50.58#ibcon#wrote, iclass 12, count 0 2006.168.08:27:50.58#ibcon#about to read 3, iclass 12, count 0 2006.168.08:27:50.60#ibcon#read 3, iclass 12, count 0 2006.168.08:27:50.60#ibcon#about to read 4, iclass 12, count 0 2006.168.08:27:50.60#ibcon#read 4, iclass 12, count 0 2006.168.08:27:50.60#ibcon#about to read 5, iclass 12, count 0 2006.168.08:27:50.60#ibcon#read 5, iclass 12, count 0 2006.168.08:27:50.60#ibcon#about to read 6, iclass 12, count 0 2006.168.08:27:50.60#ibcon#read 6, iclass 12, count 0 2006.168.08:27:50.60#ibcon#end of sib2, iclass 12, count 0 2006.168.08:27:50.60#ibcon#*mode == 0, iclass 12, count 0 2006.168.08:27:50.60#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.168.08:27:50.60#ibcon#[25=USB\r\n] 2006.168.08:27:50.60#ibcon#*before write, iclass 12, count 0 2006.168.08:27:50.60#ibcon#enter sib2, iclass 12, count 0 2006.168.08:27:50.60#ibcon#flushed, iclass 12, count 0 2006.168.08:27:50.60#ibcon#about to write, iclass 12, count 0 2006.168.08:27:50.60#ibcon#wrote, iclass 12, count 0 2006.168.08:27:50.60#ibcon#about to read 3, iclass 12, count 0 2006.168.08:27:50.63#ibcon#read 3, iclass 12, count 0 2006.168.08:27:50.63#ibcon#about to read 4, iclass 12, count 0 2006.168.08:27:50.63#ibcon#read 4, iclass 12, count 0 2006.168.08:27:50.63#ibcon#about to read 5, iclass 12, count 0 2006.168.08:27:50.63#ibcon#read 5, iclass 12, count 0 2006.168.08:27:50.63#ibcon#about to read 6, iclass 12, count 0 2006.168.08:27:50.63#ibcon#read 6, iclass 12, count 0 2006.168.08:27:50.63#ibcon#end of sib2, iclass 12, count 0 2006.168.08:27:50.63#ibcon#*after write, iclass 12, count 0 2006.168.08:27:50.63#ibcon#*before return 0, iclass 12, count 0 2006.168.08:27:50.63#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:27:50.63#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:27:50.63#ibcon#about to clear, iclass 12 cls_cnt 0 2006.168.08:27:50.63#ibcon#cleared, iclass 12 cls_cnt 0 2006.168.08:27:50.63$vc4f8/vblo=1,632.99 2006.168.08:27:50.63#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.168.08:27:50.63#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.168.08:27:50.63#ibcon#ireg 17 cls_cnt 0 2006.168.08:27:50.63#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:27:50.63#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:27:50.63#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:27:50.63#ibcon#enter wrdev, iclass 14, count 0 2006.168.08:27:50.63#ibcon#first serial, iclass 14, count 0 2006.168.08:27:50.63#ibcon#enter sib2, iclass 14, count 0 2006.168.08:27:50.63#ibcon#flushed, iclass 14, count 0 2006.168.08:27:50.63#ibcon#about to write, iclass 14, count 0 2006.168.08:27:50.63#ibcon#wrote, iclass 14, count 0 2006.168.08:27:50.63#ibcon#about to read 3, iclass 14, count 0 2006.168.08:27:50.65#ibcon#read 3, iclass 14, count 0 2006.168.08:27:50.65#ibcon#about to read 4, iclass 14, count 0 2006.168.08:27:50.65#ibcon#read 4, iclass 14, count 0 2006.168.08:27:50.65#ibcon#about to read 5, iclass 14, count 0 2006.168.08:27:50.65#ibcon#read 5, iclass 14, count 0 2006.168.08:27:50.65#ibcon#about to read 6, iclass 14, count 0 2006.168.08:27:50.65#ibcon#read 6, iclass 14, count 0 2006.168.08:27:50.65#ibcon#end of sib2, iclass 14, count 0 2006.168.08:27:50.65#ibcon#*mode == 0, iclass 14, count 0 2006.168.08:27:50.65#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.168.08:27:50.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.08:27:50.65#ibcon#*before write, iclass 14, count 0 2006.168.08:27:50.65#ibcon#enter sib2, iclass 14, count 0 2006.168.08:27:50.65#ibcon#flushed, iclass 14, count 0 2006.168.08:27:50.65#ibcon#about to write, iclass 14, count 0 2006.168.08:27:50.65#ibcon#wrote, iclass 14, count 0 2006.168.08:27:50.65#ibcon#about to read 3, iclass 14, count 0 2006.168.08:27:50.69#ibcon#read 3, iclass 14, count 0 2006.168.08:27:50.69#ibcon#about to read 4, iclass 14, count 0 2006.168.08:27:50.69#ibcon#read 4, iclass 14, count 0 2006.168.08:27:50.69#ibcon#about to read 5, iclass 14, count 0 2006.168.08:27:50.69#ibcon#read 5, iclass 14, count 0 2006.168.08:27:50.69#ibcon#about to read 6, iclass 14, count 0 2006.168.08:27:50.69#ibcon#read 6, iclass 14, count 0 2006.168.08:27:50.69#ibcon#end of sib2, iclass 14, count 0 2006.168.08:27:50.69#ibcon#*after write, iclass 14, count 0 2006.168.08:27:50.69#ibcon#*before return 0, iclass 14, count 0 2006.168.08:27:50.69#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:27:50.69#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:27:50.69#ibcon#about to clear, iclass 14 cls_cnt 0 2006.168.08:27:50.69#ibcon#cleared, iclass 14 cls_cnt 0 2006.168.08:27:50.69$vc4f8/vb=1,4 2006.168.08:27:50.69#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.168.08:27:50.69#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.168.08:27:50.69#ibcon#ireg 11 cls_cnt 2 2006.168.08:27:50.69#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:27:50.69#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:27:50.69#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:27:50.69#ibcon#enter wrdev, iclass 16, count 2 2006.168.08:27:50.69#ibcon#first serial, iclass 16, count 2 2006.168.08:27:50.69#ibcon#enter sib2, iclass 16, count 2 2006.168.08:27:50.69#ibcon#flushed, iclass 16, count 2 2006.168.08:27:50.69#ibcon#about to write, iclass 16, count 2 2006.168.08:27:50.69#ibcon#wrote, iclass 16, count 2 2006.168.08:27:50.69#ibcon#about to read 3, iclass 16, count 2 2006.168.08:27:50.71#ibcon#read 3, iclass 16, count 2 2006.168.08:27:50.71#ibcon#about to read 4, iclass 16, count 2 2006.168.08:27:50.71#ibcon#read 4, iclass 16, count 2 2006.168.08:27:50.71#ibcon#about to read 5, iclass 16, count 2 2006.168.08:27:50.71#ibcon#read 5, iclass 16, count 2 2006.168.08:27:50.71#ibcon#about to read 6, iclass 16, count 2 2006.168.08:27:50.71#ibcon#read 6, iclass 16, count 2 2006.168.08:27:50.71#ibcon#end of sib2, iclass 16, count 2 2006.168.08:27:50.71#ibcon#*mode == 0, iclass 16, count 2 2006.168.08:27:50.71#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.168.08:27:50.71#ibcon#[27=AT01-04\r\n] 2006.168.08:27:50.71#ibcon#*before write, iclass 16, count 2 2006.168.08:27:50.71#ibcon#enter sib2, iclass 16, count 2 2006.168.08:27:50.71#ibcon#flushed, iclass 16, count 2 2006.168.08:27:50.71#ibcon#about to write, iclass 16, count 2 2006.168.08:27:50.71#ibcon#wrote, iclass 16, count 2 2006.168.08:27:50.71#ibcon#about to read 3, iclass 16, count 2 2006.168.08:27:50.74#ibcon#read 3, iclass 16, count 2 2006.168.08:27:50.74#ibcon#about to read 4, iclass 16, count 2 2006.168.08:27:50.74#ibcon#read 4, iclass 16, count 2 2006.168.08:27:50.74#ibcon#about to read 5, iclass 16, count 2 2006.168.08:27:50.74#ibcon#read 5, iclass 16, count 2 2006.168.08:27:50.74#ibcon#about to read 6, iclass 16, count 2 2006.168.08:27:50.74#ibcon#read 6, iclass 16, count 2 2006.168.08:27:50.74#ibcon#end of sib2, iclass 16, count 2 2006.168.08:27:50.74#ibcon#*after write, iclass 16, count 2 2006.168.08:27:50.74#ibcon#*before return 0, iclass 16, count 2 2006.168.08:27:50.74#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:27:50.74#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:27:50.74#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.168.08:27:50.74#ibcon#ireg 7 cls_cnt 0 2006.168.08:27:50.74#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:27:50.86#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:27:50.86#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:27:50.86#ibcon#enter wrdev, iclass 16, count 0 2006.168.08:27:50.86#ibcon#first serial, iclass 16, count 0 2006.168.08:27:50.86#ibcon#enter sib2, iclass 16, count 0 2006.168.08:27:50.86#ibcon#flushed, iclass 16, count 0 2006.168.08:27:50.86#ibcon#about to write, iclass 16, count 0 2006.168.08:27:50.86#ibcon#wrote, iclass 16, count 0 2006.168.08:27:50.86#ibcon#about to read 3, iclass 16, count 0 2006.168.08:27:50.88#ibcon#read 3, iclass 16, count 0 2006.168.08:27:50.88#ibcon#about to read 4, iclass 16, count 0 2006.168.08:27:50.88#ibcon#read 4, iclass 16, count 0 2006.168.08:27:50.88#ibcon#about to read 5, iclass 16, count 0 2006.168.08:27:50.88#ibcon#read 5, iclass 16, count 0 2006.168.08:27:50.88#ibcon#about to read 6, iclass 16, count 0 2006.168.08:27:50.88#ibcon#read 6, iclass 16, count 0 2006.168.08:27:50.88#ibcon#end of sib2, iclass 16, count 0 2006.168.08:27:50.88#ibcon#*mode == 0, iclass 16, count 0 2006.168.08:27:50.88#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.168.08:27:50.88#ibcon#[27=USB\r\n] 2006.168.08:27:50.88#ibcon#*before write, iclass 16, count 0 2006.168.08:27:50.88#ibcon#enter sib2, iclass 16, count 0 2006.168.08:27:50.88#ibcon#flushed, iclass 16, count 0 2006.168.08:27:50.88#ibcon#about to write, iclass 16, count 0 2006.168.08:27:50.88#ibcon#wrote, iclass 16, count 0 2006.168.08:27:50.88#ibcon#about to read 3, iclass 16, count 0 2006.168.08:27:50.91#ibcon#read 3, iclass 16, count 0 2006.168.08:27:50.91#ibcon#about to read 4, iclass 16, count 0 2006.168.08:27:50.91#ibcon#read 4, iclass 16, count 0 2006.168.08:27:50.91#ibcon#about to read 5, iclass 16, count 0 2006.168.08:27:50.91#ibcon#read 5, iclass 16, count 0 2006.168.08:27:50.91#ibcon#about to read 6, iclass 16, count 0 2006.168.08:27:50.91#ibcon#read 6, iclass 16, count 0 2006.168.08:27:50.91#ibcon#end of sib2, iclass 16, count 0 2006.168.08:27:50.91#ibcon#*after write, iclass 16, count 0 2006.168.08:27:50.91#ibcon#*before return 0, iclass 16, count 0 2006.168.08:27:50.91#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:27:50.91#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:27:50.91#ibcon#about to clear, iclass 16 cls_cnt 0 2006.168.08:27:50.91#ibcon#cleared, iclass 16 cls_cnt 0 2006.168.08:27:50.91$vc4f8/vblo=2,640.99 2006.168.08:27:50.91#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.168.08:27:50.91#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.168.08:27:50.91#ibcon#ireg 17 cls_cnt 0 2006.168.08:27:50.91#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:27:50.91#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:27:50.91#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:27:50.91#ibcon#enter wrdev, iclass 18, count 0 2006.168.08:27:50.91#ibcon#first serial, iclass 18, count 0 2006.168.08:27:50.91#ibcon#enter sib2, iclass 18, count 0 2006.168.08:27:50.91#ibcon#flushed, iclass 18, count 0 2006.168.08:27:50.91#ibcon#about to write, iclass 18, count 0 2006.168.08:27:50.91#ibcon#wrote, iclass 18, count 0 2006.168.08:27:50.91#ibcon#about to read 3, iclass 18, count 0 2006.168.08:27:50.93#ibcon#read 3, iclass 18, count 0 2006.168.08:27:50.93#ibcon#about to read 4, iclass 18, count 0 2006.168.08:27:50.93#ibcon#read 4, iclass 18, count 0 2006.168.08:27:50.93#ibcon#about to read 5, iclass 18, count 0 2006.168.08:27:50.93#ibcon#read 5, iclass 18, count 0 2006.168.08:27:50.93#ibcon#about to read 6, iclass 18, count 0 2006.168.08:27:50.93#ibcon#read 6, iclass 18, count 0 2006.168.08:27:50.93#ibcon#end of sib2, iclass 18, count 0 2006.168.08:27:50.93#ibcon#*mode == 0, iclass 18, count 0 2006.168.08:27:50.93#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.08:27:50.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.08:27:50.93#ibcon#*before write, iclass 18, count 0 2006.168.08:27:50.93#ibcon#enter sib2, iclass 18, count 0 2006.168.08:27:50.93#ibcon#flushed, iclass 18, count 0 2006.168.08:27:50.93#ibcon#about to write, iclass 18, count 0 2006.168.08:27:50.93#ibcon#wrote, iclass 18, count 0 2006.168.08:27:50.93#ibcon#about to read 3, iclass 18, count 0 2006.168.08:27:50.97#ibcon#read 3, iclass 18, count 0 2006.168.08:27:50.97#ibcon#about to read 4, iclass 18, count 0 2006.168.08:27:50.97#ibcon#read 4, iclass 18, count 0 2006.168.08:27:50.97#ibcon#about to read 5, iclass 18, count 0 2006.168.08:27:50.97#ibcon#read 5, iclass 18, count 0 2006.168.08:27:50.97#ibcon#about to read 6, iclass 18, count 0 2006.168.08:27:50.97#ibcon#read 6, iclass 18, count 0 2006.168.08:27:50.97#ibcon#end of sib2, iclass 18, count 0 2006.168.08:27:50.97#ibcon#*after write, iclass 18, count 0 2006.168.08:27:50.97#ibcon#*before return 0, iclass 18, count 0 2006.168.08:27:50.97#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:27:50.97#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:27:50.97#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.08:27:50.97#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.08:27:50.97$vc4f8/vb=2,4 2006.168.08:27:50.97#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.168.08:27:50.97#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.168.08:27:50.97#ibcon#ireg 11 cls_cnt 2 2006.168.08:27:50.97#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:27:51.03#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:27:51.03#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:27:51.03#ibcon#enter wrdev, iclass 20, count 2 2006.168.08:27:51.03#ibcon#first serial, iclass 20, count 2 2006.168.08:27:51.03#ibcon#enter sib2, iclass 20, count 2 2006.168.08:27:51.03#ibcon#flushed, iclass 20, count 2 2006.168.08:27:51.03#ibcon#about to write, iclass 20, count 2 2006.168.08:27:51.03#ibcon#wrote, iclass 20, count 2 2006.168.08:27:51.03#ibcon#about to read 3, iclass 20, count 2 2006.168.08:27:51.05#ibcon#read 3, iclass 20, count 2 2006.168.08:27:51.05#ibcon#about to read 4, iclass 20, count 2 2006.168.08:27:51.05#ibcon#read 4, iclass 20, count 2 2006.168.08:27:51.05#ibcon#about to read 5, iclass 20, count 2 2006.168.08:27:51.05#ibcon#read 5, iclass 20, count 2 2006.168.08:27:51.05#ibcon#about to read 6, iclass 20, count 2 2006.168.08:27:51.05#ibcon#read 6, iclass 20, count 2 2006.168.08:27:51.05#ibcon#end of sib2, iclass 20, count 2 2006.168.08:27:51.05#ibcon#*mode == 0, iclass 20, count 2 2006.168.08:27:51.05#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.168.08:27:51.05#ibcon#[27=AT02-04\r\n] 2006.168.08:27:51.05#ibcon#*before write, iclass 20, count 2 2006.168.08:27:51.05#ibcon#enter sib2, iclass 20, count 2 2006.168.08:27:51.05#ibcon#flushed, iclass 20, count 2 2006.168.08:27:51.05#ibcon#about to write, iclass 20, count 2 2006.168.08:27:51.05#ibcon#wrote, iclass 20, count 2 2006.168.08:27:51.05#ibcon#about to read 3, iclass 20, count 2 2006.168.08:27:51.08#ibcon#read 3, iclass 20, count 2 2006.168.08:27:51.08#ibcon#about to read 4, iclass 20, count 2 2006.168.08:27:51.08#ibcon#read 4, iclass 20, count 2 2006.168.08:27:51.08#ibcon#about to read 5, iclass 20, count 2 2006.168.08:27:51.08#ibcon#read 5, iclass 20, count 2 2006.168.08:27:51.08#ibcon#about to read 6, iclass 20, count 2 2006.168.08:27:51.08#ibcon#read 6, iclass 20, count 2 2006.168.08:27:51.08#ibcon#end of sib2, iclass 20, count 2 2006.168.08:27:51.08#ibcon#*after write, iclass 20, count 2 2006.168.08:27:51.08#ibcon#*before return 0, iclass 20, count 2 2006.168.08:27:51.08#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:27:51.08#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:27:51.08#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.168.08:27:51.08#ibcon#ireg 7 cls_cnt 0 2006.168.08:27:51.08#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:27:51.20#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:27:51.20#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:27:51.20#ibcon#enter wrdev, iclass 20, count 0 2006.168.08:27:51.20#ibcon#first serial, iclass 20, count 0 2006.168.08:27:51.20#ibcon#enter sib2, iclass 20, count 0 2006.168.08:27:51.20#ibcon#flushed, iclass 20, count 0 2006.168.08:27:51.20#ibcon#about to write, iclass 20, count 0 2006.168.08:27:51.20#ibcon#wrote, iclass 20, count 0 2006.168.08:27:51.20#ibcon#about to read 3, iclass 20, count 0 2006.168.08:27:51.22#ibcon#read 3, iclass 20, count 0 2006.168.08:27:51.22#ibcon#about to read 4, iclass 20, count 0 2006.168.08:27:51.22#ibcon#read 4, iclass 20, count 0 2006.168.08:27:51.22#ibcon#about to read 5, iclass 20, count 0 2006.168.08:27:51.22#ibcon#read 5, iclass 20, count 0 2006.168.08:27:51.22#ibcon#about to read 6, iclass 20, count 0 2006.168.08:27:51.22#ibcon#read 6, iclass 20, count 0 2006.168.08:27:51.22#ibcon#end of sib2, iclass 20, count 0 2006.168.08:27:51.22#ibcon#*mode == 0, iclass 20, count 0 2006.168.08:27:51.22#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.168.08:27:51.22#ibcon#[27=USB\r\n] 2006.168.08:27:51.22#ibcon#*before write, iclass 20, count 0 2006.168.08:27:51.22#ibcon#enter sib2, iclass 20, count 0 2006.168.08:27:51.22#ibcon#flushed, iclass 20, count 0 2006.168.08:27:51.22#ibcon#about to write, iclass 20, count 0 2006.168.08:27:51.22#ibcon#wrote, iclass 20, count 0 2006.168.08:27:51.22#ibcon#about to read 3, iclass 20, count 0 2006.168.08:27:51.25#ibcon#read 3, iclass 20, count 0 2006.168.08:27:51.25#ibcon#about to read 4, iclass 20, count 0 2006.168.08:27:51.25#ibcon#read 4, iclass 20, count 0 2006.168.08:27:51.25#ibcon#about to read 5, iclass 20, count 0 2006.168.08:27:51.25#ibcon#read 5, iclass 20, count 0 2006.168.08:27:51.25#ibcon#about to read 6, iclass 20, count 0 2006.168.08:27:51.25#ibcon#read 6, iclass 20, count 0 2006.168.08:27:51.25#ibcon#end of sib2, iclass 20, count 0 2006.168.08:27:51.25#ibcon#*after write, iclass 20, count 0 2006.168.08:27:51.25#ibcon#*before return 0, iclass 20, count 0 2006.168.08:27:51.25#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:27:51.25#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:27:51.25#ibcon#about to clear, iclass 20 cls_cnt 0 2006.168.08:27:51.25#ibcon#cleared, iclass 20 cls_cnt 0 2006.168.08:27:51.25$vc4f8/vblo=3,656.99 2006.168.08:27:51.25#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.168.08:27:51.25#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.168.08:27:51.25#ibcon#ireg 17 cls_cnt 0 2006.168.08:27:51.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:27:51.25#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:27:51.25#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:27:51.25#ibcon#enter wrdev, iclass 22, count 0 2006.168.08:27:51.25#ibcon#first serial, iclass 22, count 0 2006.168.08:27:51.25#ibcon#enter sib2, iclass 22, count 0 2006.168.08:27:51.25#ibcon#flushed, iclass 22, count 0 2006.168.08:27:51.25#ibcon#about to write, iclass 22, count 0 2006.168.08:27:51.25#ibcon#wrote, iclass 22, count 0 2006.168.08:27:51.25#ibcon#about to read 3, iclass 22, count 0 2006.168.08:27:51.27#ibcon#read 3, iclass 22, count 0 2006.168.08:27:51.27#ibcon#about to read 4, iclass 22, count 0 2006.168.08:27:51.27#ibcon#read 4, iclass 22, count 0 2006.168.08:27:51.27#ibcon#about to read 5, iclass 22, count 0 2006.168.08:27:51.27#ibcon#read 5, iclass 22, count 0 2006.168.08:27:51.27#ibcon#about to read 6, iclass 22, count 0 2006.168.08:27:51.27#ibcon#read 6, iclass 22, count 0 2006.168.08:27:51.27#ibcon#end of sib2, iclass 22, count 0 2006.168.08:27:51.27#ibcon#*mode == 0, iclass 22, count 0 2006.168.08:27:51.27#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.168.08:27:51.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.08:27:51.27#ibcon#*before write, iclass 22, count 0 2006.168.08:27:51.27#ibcon#enter sib2, iclass 22, count 0 2006.168.08:27:51.27#ibcon#flushed, iclass 22, count 0 2006.168.08:27:51.27#ibcon#about to write, iclass 22, count 0 2006.168.08:27:51.27#ibcon#wrote, iclass 22, count 0 2006.168.08:27:51.27#ibcon#about to read 3, iclass 22, count 0 2006.168.08:27:51.31#ibcon#read 3, iclass 22, count 0 2006.168.08:27:51.31#ibcon#about to read 4, iclass 22, count 0 2006.168.08:27:51.31#ibcon#read 4, iclass 22, count 0 2006.168.08:27:51.31#ibcon#about to read 5, iclass 22, count 0 2006.168.08:27:51.31#ibcon#read 5, iclass 22, count 0 2006.168.08:27:51.31#ibcon#about to read 6, iclass 22, count 0 2006.168.08:27:51.31#ibcon#read 6, iclass 22, count 0 2006.168.08:27:51.31#ibcon#end of sib2, iclass 22, count 0 2006.168.08:27:51.31#ibcon#*after write, iclass 22, count 0 2006.168.08:27:51.31#ibcon#*before return 0, iclass 22, count 0 2006.168.08:27:51.31#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:27:51.31#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:27:51.31#ibcon#about to clear, iclass 22 cls_cnt 0 2006.168.08:27:51.31#ibcon#cleared, iclass 22 cls_cnt 0 2006.168.08:27:51.32$vc4f8/vb=3,4 2006.168.08:27:51.32#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.168.08:27:51.32#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.168.08:27:51.32#ibcon#ireg 11 cls_cnt 2 2006.168.08:27:51.32#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:27:51.36#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:27:51.36#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:27:51.36#ibcon#enter wrdev, iclass 24, count 2 2006.168.08:27:51.36#ibcon#first serial, iclass 24, count 2 2006.168.08:27:51.36#ibcon#enter sib2, iclass 24, count 2 2006.168.08:27:51.36#ibcon#flushed, iclass 24, count 2 2006.168.08:27:51.36#ibcon#about to write, iclass 24, count 2 2006.168.08:27:51.36#ibcon#wrote, iclass 24, count 2 2006.168.08:27:51.36#ibcon#about to read 3, iclass 24, count 2 2006.168.08:27:51.38#ibcon#read 3, iclass 24, count 2 2006.168.08:27:51.38#ibcon#about to read 4, iclass 24, count 2 2006.168.08:27:51.38#ibcon#read 4, iclass 24, count 2 2006.168.08:27:51.38#ibcon#about to read 5, iclass 24, count 2 2006.168.08:27:51.38#ibcon#read 5, iclass 24, count 2 2006.168.08:27:51.38#ibcon#about to read 6, iclass 24, count 2 2006.168.08:27:51.38#ibcon#read 6, iclass 24, count 2 2006.168.08:27:51.38#ibcon#end of sib2, iclass 24, count 2 2006.168.08:27:51.38#ibcon#*mode == 0, iclass 24, count 2 2006.168.08:27:51.38#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.168.08:27:51.38#ibcon#[27=AT03-04\r\n] 2006.168.08:27:51.38#ibcon#*before write, iclass 24, count 2 2006.168.08:27:51.38#ibcon#enter sib2, iclass 24, count 2 2006.168.08:27:51.38#ibcon#flushed, iclass 24, count 2 2006.168.08:27:51.38#ibcon#about to write, iclass 24, count 2 2006.168.08:27:51.38#ibcon#wrote, iclass 24, count 2 2006.168.08:27:51.38#ibcon#about to read 3, iclass 24, count 2 2006.168.08:27:51.41#ibcon#read 3, iclass 24, count 2 2006.168.08:27:51.41#ibcon#about to read 4, iclass 24, count 2 2006.168.08:27:51.41#ibcon#read 4, iclass 24, count 2 2006.168.08:27:51.41#ibcon#about to read 5, iclass 24, count 2 2006.168.08:27:51.41#ibcon#read 5, iclass 24, count 2 2006.168.08:27:51.41#ibcon#about to read 6, iclass 24, count 2 2006.168.08:27:51.41#ibcon#read 6, iclass 24, count 2 2006.168.08:27:51.41#ibcon#end of sib2, iclass 24, count 2 2006.168.08:27:51.41#ibcon#*after write, iclass 24, count 2 2006.168.08:27:51.41#ibcon#*before return 0, iclass 24, count 2 2006.168.08:27:51.41#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:27:51.41#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:27:51.41#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.168.08:27:51.41#ibcon#ireg 7 cls_cnt 0 2006.168.08:27:51.41#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:27:51.53#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:27:51.53#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:27:51.53#ibcon#enter wrdev, iclass 24, count 0 2006.168.08:27:51.53#ibcon#first serial, iclass 24, count 0 2006.168.08:27:51.53#ibcon#enter sib2, iclass 24, count 0 2006.168.08:27:51.53#ibcon#flushed, iclass 24, count 0 2006.168.08:27:51.53#ibcon#about to write, iclass 24, count 0 2006.168.08:27:51.53#ibcon#wrote, iclass 24, count 0 2006.168.08:27:51.53#ibcon#about to read 3, iclass 24, count 0 2006.168.08:27:51.55#ibcon#read 3, iclass 24, count 0 2006.168.08:27:51.55#ibcon#about to read 4, iclass 24, count 0 2006.168.08:27:51.55#ibcon#read 4, iclass 24, count 0 2006.168.08:27:51.55#ibcon#about to read 5, iclass 24, count 0 2006.168.08:27:51.55#ibcon#read 5, iclass 24, count 0 2006.168.08:27:51.55#ibcon#about to read 6, iclass 24, count 0 2006.168.08:27:51.55#ibcon#read 6, iclass 24, count 0 2006.168.08:27:51.55#ibcon#end of sib2, iclass 24, count 0 2006.168.08:27:51.55#ibcon#*mode == 0, iclass 24, count 0 2006.168.08:27:51.55#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.168.08:27:51.55#ibcon#[27=USB\r\n] 2006.168.08:27:51.55#ibcon#*before write, iclass 24, count 0 2006.168.08:27:51.55#ibcon#enter sib2, iclass 24, count 0 2006.168.08:27:51.55#ibcon#flushed, iclass 24, count 0 2006.168.08:27:51.55#ibcon#about to write, iclass 24, count 0 2006.168.08:27:51.55#ibcon#wrote, iclass 24, count 0 2006.168.08:27:51.55#ibcon#about to read 3, iclass 24, count 0 2006.168.08:27:51.58#ibcon#read 3, iclass 24, count 0 2006.168.08:27:51.58#ibcon#about to read 4, iclass 24, count 0 2006.168.08:27:51.58#ibcon#read 4, iclass 24, count 0 2006.168.08:27:51.58#ibcon#about to read 5, iclass 24, count 0 2006.168.08:27:51.58#ibcon#read 5, iclass 24, count 0 2006.168.08:27:51.58#ibcon#about to read 6, iclass 24, count 0 2006.168.08:27:51.58#ibcon#read 6, iclass 24, count 0 2006.168.08:27:51.58#ibcon#end of sib2, iclass 24, count 0 2006.168.08:27:51.58#ibcon#*after write, iclass 24, count 0 2006.168.08:27:51.58#ibcon#*before return 0, iclass 24, count 0 2006.168.08:27:51.58#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:27:51.58#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:27:51.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.168.08:27:51.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.168.08:27:51.58$vc4f8/vblo=4,712.99 2006.168.08:27:51.58#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.168.08:27:51.58#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.168.08:27:51.58#ibcon#ireg 17 cls_cnt 0 2006.168.08:27:51.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:27:51.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:27:51.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:27:51.58#ibcon#enter wrdev, iclass 26, count 0 2006.168.08:27:51.58#ibcon#first serial, iclass 26, count 0 2006.168.08:27:51.58#ibcon#enter sib2, iclass 26, count 0 2006.168.08:27:51.58#ibcon#flushed, iclass 26, count 0 2006.168.08:27:51.58#ibcon#about to write, iclass 26, count 0 2006.168.08:27:51.58#ibcon#wrote, iclass 26, count 0 2006.168.08:27:51.58#ibcon#about to read 3, iclass 26, count 0 2006.168.08:27:51.60#ibcon#read 3, iclass 26, count 0 2006.168.08:27:51.60#ibcon#about to read 4, iclass 26, count 0 2006.168.08:27:51.60#ibcon#read 4, iclass 26, count 0 2006.168.08:27:51.60#ibcon#about to read 5, iclass 26, count 0 2006.168.08:27:51.60#ibcon#read 5, iclass 26, count 0 2006.168.08:27:51.60#ibcon#about to read 6, iclass 26, count 0 2006.168.08:27:51.60#ibcon#read 6, iclass 26, count 0 2006.168.08:27:51.60#ibcon#end of sib2, iclass 26, count 0 2006.168.08:27:51.60#ibcon#*mode == 0, iclass 26, count 0 2006.168.08:27:51.60#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.168.08:27:51.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.08:27:51.60#ibcon#*before write, iclass 26, count 0 2006.168.08:27:51.60#ibcon#enter sib2, iclass 26, count 0 2006.168.08:27:51.60#ibcon#flushed, iclass 26, count 0 2006.168.08:27:51.60#ibcon#about to write, iclass 26, count 0 2006.168.08:27:51.60#ibcon#wrote, iclass 26, count 0 2006.168.08:27:51.60#ibcon#about to read 3, iclass 26, count 0 2006.168.08:27:51.64#ibcon#read 3, iclass 26, count 0 2006.168.08:27:51.64#ibcon#about to read 4, iclass 26, count 0 2006.168.08:27:51.64#ibcon#read 4, iclass 26, count 0 2006.168.08:27:51.64#ibcon#about to read 5, iclass 26, count 0 2006.168.08:27:51.64#ibcon#read 5, iclass 26, count 0 2006.168.08:27:51.64#ibcon#about to read 6, iclass 26, count 0 2006.168.08:27:51.64#ibcon#read 6, iclass 26, count 0 2006.168.08:27:51.64#ibcon#end of sib2, iclass 26, count 0 2006.168.08:27:51.64#ibcon#*after write, iclass 26, count 0 2006.168.08:27:51.64#ibcon#*before return 0, iclass 26, count 0 2006.168.08:27:51.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:27:51.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:27:51.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.168.08:27:51.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.168.08:27:51.64$vc4f8/vb=4,4 2006.168.08:27:51.64#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.168.08:27:51.64#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.168.08:27:51.64#ibcon#ireg 11 cls_cnt 2 2006.168.08:27:51.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:27:51.70#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:27:51.70#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:27:51.70#ibcon#enter wrdev, iclass 28, count 2 2006.168.08:27:51.70#ibcon#first serial, iclass 28, count 2 2006.168.08:27:51.70#ibcon#enter sib2, iclass 28, count 2 2006.168.08:27:51.70#ibcon#flushed, iclass 28, count 2 2006.168.08:27:51.70#ibcon#about to write, iclass 28, count 2 2006.168.08:27:51.70#ibcon#wrote, iclass 28, count 2 2006.168.08:27:51.70#ibcon#about to read 3, iclass 28, count 2 2006.168.08:27:51.72#ibcon#read 3, iclass 28, count 2 2006.168.08:27:51.72#ibcon#about to read 4, iclass 28, count 2 2006.168.08:27:51.72#ibcon#read 4, iclass 28, count 2 2006.168.08:27:51.72#ibcon#about to read 5, iclass 28, count 2 2006.168.08:27:51.72#ibcon#read 5, iclass 28, count 2 2006.168.08:27:51.72#ibcon#about to read 6, iclass 28, count 2 2006.168.08:27:51.72#ibcon#read 6, iclass 28, count 2 2006.168.08:27:51.72#ibcon#end of sib2, iclass 28, count 2 2006.168.08:27:51.72#ibcon#*mode == 0, iclass 28, count 2 2006.168.08:27:51.72#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.168.08:27:51.72#ibcon#[27=AT04-04\r\n] 2006.168.08:27:51.72#ibcon#*before write, iclass 28, count 2 2006.168.08:27:51.72#ibcon#enter sib2, iclass 28, count 2 2006.168.08:27:51.72#ibcon#flushed, iclass 28, count 2 2006.168.08:27:51.72#ibcon#about to write, iclass 28, count 2 2006.168.08:27:51.72#ibcon#wrote, iclass 28, count 2 2006.168.08:27:51.72#ibcon#about to read 3, iclass 28, count 2 2006.168.08:27:51.75#ibcon#read 3, iclass 28, count 2 2006.168.08:27:51.75#ibcon#about to read 4, iclass 28, count 2 2006.168.08:27:51.75#ibcon#read 4, iclass 28, count 2 2006.168.08:27:51.75#ibcon#about to read 5, iclass 28, count 2 2006.168.08:27:51.75#ibcon#read 5, iclass 28, count 2 2006.168.08:27:51.75#ibcon#about to read 6, iclass 28, count 2 2006.168.08:27:51.75#ibcon#read 6, iclass 28, count 2 2006.168.08:27:51.75#ibcon#end of sib2, iclass 28, count 2 2006.168.08:27:51.75#ibcon#*after write, iclass 28, count 2 2006.168.08:27:51.75#ibcon#*before return 0, iclass 28, count 2 2006.168.08:27:51.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:27:51.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:27:51.75#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.168.08:27:51.75#ibcon#ireg 7 cls_cnt 0 2006.168.08:27:51.75#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:27:51.87#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:27:51.87#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:27:51.87#ibcon#enter wrdev, iclass 28, count 0 2006.168.08:27:51.87#ibcon#first serial, iclass 28, count 0 2006.168.08:27:51.87#ibcon#enter sib2, iclass 28, count 0 2006.168.08:27:51.87#ibcon#flushed, iclass 28, count 0 2006.168.08:27:51.87#ibcon#about to write, iclass 28, count 0 2006.168.08:27:51.87#ibcon#wrote, iclass 28, count 0 2006.168.08:27:51.87#ibcon#about to read 3, iclass 28, count 0 2006.168.08:27:51.89#ibcon#read 3, iclass 28, count 0 2006.168.08:27:51.89#ibcon#about to read 4, iclass 28, count 0 2006.168.08:27:51.89#ibcon#read 4, iclass 28, count 0 2006.168.08:27:51.89#ibcon#about to read 5, iclass 28, count 0 2006.168.08:27:51.89#ibcon#read 5, iclass 28, count 0 2006.168.08:27:51.89#ibcon#about to read 6, iclass 28, count 0 2006.168.08:27:51.89#ibcon#read 6, iclass 28, count 0 2006.168.08:27:51.89#ibcon#end of sib2, iclass 28, count 0 2006.168.08:27:51.89#ibcon#*mode == 0, iclass 28, count 0 2006.168.08:27:51.89#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.168.08:27:51.89#ibcon#[27=USB\r\n] 2006.168.08:27:51.89#ibcon#*before write, iclass 28, count 0 2006.168.08:27:51.89#ibcon#enter sib2, iclass 28, count 0 2006.168.08:27:51.89#ibcon#flushed, iclass 28, count 0 2006.168.08:27:51.89#ibcon#about to write, iclass 28, count 0 2006.168.08:27:51.89#ibcon#wrote, iclass 28, count 0 2006.168.08:27:51.89#ibcon#about to read 3, iclass 28, count 0 2006.168.08:27:51.92#ibcon#read 3, iclass 28, count 0 2006.168.08:27:51.92#ibcon#about to read 4, iclass 28, count 0 2006.168.08:27:51.92#ibcon#read 4, iclass 28, count 0 2006.168.08:27:51.92#ibcon#about to read 5, iclass 28, count 0 2006.168.08:27:51.92#ibcon#read 5, iclass 28, count 0 2006.168.08:27:51.92#ibcon#about to read 6, iclass 28, count 0 2006.168.08:27:51.92#ibcon#read 6, iclass 28, count 0 2006.168.08:27:51.92#ibcon#end of sib2, iclass 28, count 0 2006.168.08:27:51.92#ibcon#*after write, iclass 28, count 0 2006.168.08:27:51.92#ibcon#*before return 0, iclass 28, count 0 2006.168.08:27:51.92#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:27:51.92#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:27:51.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.168.08:27:51.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.168.08:27:51.92$vc4f8/vblo=5,744.99 2006.168.08:27:51.92#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.168.08:27:51.92#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.168.08:27:51.92#ibcon#ireg 17 cls_cnt 0 2006.168.08:27:51.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:27:51.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:27:51.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:27:51.92#ibcon#enter wrdev, iclass 30, count 0 2006.168.08:27:51.92#ibcon#first serial, iclass 30, count 0 2006.168.08:27:51.92#ibcon#enter sib2, iclass 30, count 0 2006.168.08:27:51.92#ibcon#flushed, iclass 30, count 0 2006.168.08:27:51.92#ibcon#about to write, iclass 30, count 0 2006.168.08:27:51.92#ibcon#wrote, iclass 30, count 0 2006.168.08:27:51.92#ibcon#about to read 3, iclass 30, count 0 2006.168.08:27:51.94#ibcon#read 3, iclass 30, count 0 2006.168.08:27:51.94#ibcon#about to read 4, iclass 30, count 0 2006.168.08:27:51.94#ibcon#read 4, iclass 30, count 0 2006.168.08:27:51.94#ibcon#about to read 5, iclass 30, count 0 2006.168.08:27:51.94#ibcon#read 5, iclass 30, count 0 2006.168.08:27:51.94#ibcon#about to read 6, iclass 30, count 0 2006.168.08:27:51.94#ibcon#read 6, iclass 30, count 0 2006.168.08:27:51.94#ibcon#end of sib2, iclass 30, count 0 2006.168.08:27:51.94#ibcon#*mode == 0, iclass 30, count 0 2006.168.08:27:51.94#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.168.08:27:51.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.08:27:51.94#ibcon#*before write, iclass 30, count 0 2006.168.08:27:51.94#ibcon#enter sib2, iclass 30, count 0 2006.168.08:27:51.94#ibcon#flushed, iclass 30, count 0 2006.168.08:27:51.94#ibcon#about to write, iclass 30, count 0 2006.168.08:27:51.94#ibcon#wrote, iclass 30, count 0 2006.168.08:27:51.94#ibcon#about to read 3, iclass 30, count 0 2006.168.08:27:51.98#ibcon#read 3, iclass 30, count 0 2006.168.08:27:51.98#ibcon#about to read 4, iclass 30, count 0 2006.168.08:27:51.98#ibcon#read 4, iclass 30, count 0 2006.168.08:27:51.98#ibcon#about to read 5, iclass 30, count 0 2006.168.08:27:51.98#ibcon#read 5, iclass 30, count 0 2006.168.08:27:51.98#ibcon#about to read 6, iclass 30, count 0 2006.168.08:27:51.98#ibcon#read 6, iclass 30, count 0 2006.168.08:27:51.98#ibcon#end of sib2, iclass 30, count 0 2006.168.08:27:51.98#ibcon#*after write, iclass 30, count 0 2006.168.08:27:51.98#ibcon#*before return 0, iclass 30, count 0 2006.168.08:27:51.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:27:51.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:27:51.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.168.08:27:51.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.168.08:27:51.98$vc4f8/vb=5,4 2006.168.08:27:51.98#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.168.08:27:51.98#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.168.08:27:51.98#ibcon#ireg 11 cls_cnt 2 2006.168.08:27:51.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:27:52.04#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:27:52.04#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:27:52.04#ibcon#enter wrdev, iclass 32, count 2 2006.168.08:27:52.04#ibcon#first serial, iclass 32, count 2 2006.168.08:27:52.04#ibcon#enter sib2, iclass 32, count 2 2006.168.08:27:52.04#ibcon#flushed, iclass 32, count 2 2006.168.08:27:52.04#ibcon#about to write, iclass 32, count 2 2006.168.08:27:52.04#ibcon#wrote, iclass 32, count 2 2006.168.08:27:52.04#ibcon#about to read 3, iclass 32, count 2 2006.168.08:27:52.06#ibcon#read 3, iclass 32, count 2 2006.168.08:27:52.06#ibcon#about to read 4, iclass 32, count 2 2006.168.08:27:52.06#ibcon#read 4, iclass 32, count 2 2006.168.08:27:52.06#ibcon#about to read 5, iclass 32, count 2 2006.168.08:27:52.06#ibcon#read 5, iclass 32, count 2 2006.168.08:27:52.06#ibcon#about to read 6, iclass 32, count 2 2006.168.08:27:52.06#ibcon#read 6, iclass 32, count 2 2006.168.08:27:52.06#ibcon#end of sib2, iclass 32, count 2 2006.168.08:27:52.06#ibcon#*mode == 0, iclass 32, count 2 2006.168.08:27:52.06#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.168.08:27:52.06#ibcon#[27=AT05-04\r\n] 2006.168.08:27:52.06#ibcon#*before write, iclass 32, count 2 2006.168.08:27:52.06#ibcon#enter sib2, iclass 32, count 2 2006.168.08:27:52.06#ibcon#flushed, iclass 32, count 2 2006.168.08:27:52.06#ibcon#about to write, iclass 32, count 2 2006.168.08:27:52.06#ibcon#wrote, iclass 32, count 2 2006.168.08:27:52.06#ibcon#about to read 3, iclass 32, count 2 2006.168.08:27:52.09#ibcon#read 3, iclass 32, count 2 2006.168.08:27:52.09#ibcon#about to read 4, iclass 32, count 2 2006.168.08:27:52.09#ibcon#read 4, iclass 32, count 2 2006.168.08:27:52.09#ibcon#about to read 5, iclass 32, count 2 2006.168.08:27:52.09#ibcon#read 5, iclass 32, count 2 2006.168.08:27:52.09#ibcon#about to read 6, iclass 32, count 2 2006.168.08:27:52.09#ibcon#read 6, iclass 32, count 2 2006.168.08:27:52.09#ibcon#end of sib2, iclass 32, count 2 2006.168.08:27:52.09#ibcon#*after write, iclass 32, count 2 2006.168.08:27:52.09#ibcon#*before return 0, iclass 32, count 2 2006.168.08:27:52.09#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:27:52.09#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:27:52.09#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.168.08:27:52.09#ibcon#ireg 7 cls_cnt 0 2006.168.08:27:52.09#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:27:52.21#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:27:52.21#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:27:52.21#ibcon#enter wrdev, iclass 32, count 0 2006.168.08:27:52.21#ibcon#first serial, iclass 32, count 0 2006.168.08:27:52.21#ibcon#enter sib2, iclass 32, count 0 2006.168.08:27:52.21#ibcon#flushed, iclass 32, count 0 2006.168.08:27:52.21#ibcon#about to write, iclass 32, count 0 2006.168.08:27:52.21#ibcon#wrote, iclass 32, count 0 2006.168.08:27:52.21#ibcon#about to read 3, iclass 32, count 0 2006.168.08:27:52.23#ibcon#read 3, iclass 32, count 0 2006.168.08:27:52.23#ibcon#about to read 4, iclass 32, count 0 2006.168.08:27:52.23#ibcon#read 4, iclass 32, count 0 2006.168.08:27:52.23#ibcon#about to read 5, iclass 32, count 0 2006.168.08:27:52.23#ibcon#read 5, iclass 32, count 0 2006.168.08:27:52.23#ibcon#about to read 6, iclass 32, count 0 2006.168.08:27:52.23#ibcon#read 6, iclass 32, count 0 2006.168.08:27:52.23#ibcon#end of sib2, iclass 32, count 0 2006.168.08:27:52.23#ibcon#*mode == 0, iclass 32, count 0 2006.168.08:27:52.23#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.168.08:27:52.23#ibcon#[27=USB\r\n] 2006.168.08:27:52.23#ibcon#*before write, iclass 32, count 0 2006.168.08:27:52.23#ibcon#enter sib2, iclass 32, count 0 2006.168.08:27:52.23#ibcon#flushed, iclass 32, count 0 2006.168.08:27:52.23#ibcon#about to write, iclass 32, count 0 2006.168.08:27:52.23#ibcon#wrote, iclass 32, count 0 2006.168.08:27:52.23#ibcon#about to read 3, iclass 32, count 0 2006.168.08:27:52.26#ibcon#read 3, iclass 32, count 0 2006.168.08:27:52.26#ibcon#about to read 4, iclass 32, count 0 2006.168.08:27:52.26#ibcon#read 4, iclass 32, count 0 2006.168.08:27:52.26#ibcon#about to read 5, iclass 32, count 0 2006.168.08:27:52.26#ibcon#read 5, iclass 32, count 0 2006.168.08:27:52.26#ibcon#about to read 6, iclass 32, count 0 2006.168.08:27:52.26#ibcon#read 6, iclass 32, count 0 2006.168.08:27:52.26#ibcon#end of sib2, iclass 32, count 0 2006.168.08:27:52.26#ibcon#*after write, iclass 32, count 0 2006.168.08:27:52.26#ibcon#*before return 0, iclass 32, count 0 2006.168.08:27:52.26#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:27:52.26#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:27:52.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.168.08:27:52.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.168.08:27:52.26$vc4f8/vblo=6,752.99 2006.168.08:27:52.26#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.168.08:27:52.26#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.168.08:27:52.26#ibcon#ireg 17 cls_cnt 0 2006.168.08:27:52.26#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:27:52.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:27:52.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:27:52.26#ibcon#enter wrdev, iclass 34, count 0 2006.168.08:27:52.26#ibcon#first serial, iclass 34, count 0 2006.168.08:27:52.26#ibcon#enter sib2, iclass 34, count 0 2006.168.08:27:52.26#ibcon#flushed, iclass 34, count 0 2006.168.08:27:52.26#ibcon#about to write, iclass 34, count 0 2006.168.08:27:52.26#ibcon#wrote, iclass 34, count 0 2006.168.08:27:52.26#ibcon#about to read 3, iclass 34, count 0 2006.168.08:27:52.28#ibcon#read 3, iclass 34, count 0 2006.168.08:27:52.28#ibcon#about to read 4, iclass 34, count 0 2006.168.08:27:52.28#ibcon#read 4, iclass 34, count 0 2006.168.08:27:52.28#ibcon#about to read 5, iclass 34, count 0 2006.168.08:27:52.28#ibcon#read 5, iclass 34, count 0 2006.168.08:27:52.28#ibcon#about to read 6, iclass 34, count 0 2006.168.08:27:52.28#ibcon#read 6, iclass 34, count 0 2006.168.08:27:52.28#ibcon#end of sib2, iclass 34, count 0 2006.168.08:27:52.28#ibcon#*mode == 0, iclass 34, count 0 2006.168.08:27:52.28#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.168.08:27:52.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.08:27:52.28#ibcon#*before write, iclass 34, count 0 2006.168.08:27:52.28#ibcon#enter sib2, iclass 34, count 0 2006.168.08:27:52.28#ibcon#flushed, iclass 34, count 0 2006.168.08:27:52.28#ibcon#about to write, iclass 34, count 0 2006.168.08:27:52.28#ibcon#wrote, iclass 34, count 0 2006.168.08:27:52.28#ibcon#about to read 3, iclass 34, count 0 2006.168.08:27:52.32#ibcon#read 3, iclass 34, count 0 2006.168.08:27:52.32#ibcon#about to read 4, iclass 34, count 0 2006.168.08:27:52.32#ibcon#read 4, iclass 34, count 0 2006.168.08:27:52.32#ibcon#about to read 5, iclass 34, count 0 2006.168.08:27:52.32#ibcon#read 5, iclass 34, count 0 2006.168.08:27:52.32#ibcon#about to read 6, iclass 34, count 0 2006.168.08:27:52.32#ibcon#read 6, iclass 34, count 0 2006.168.08:27:52.32#ibcon#end of sib2, iclass 34, count 0 2006.168.08:27:52.32#ibcon#*after write, iclass 34, count 0 2006.168.08:27:52.32#ibcon#*before return 0, iclass 34, count 0 2006.168.08:27:52.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:27:52.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:27:52.32#ibcon#about to clear, iclass 34 cls_cnt 0 2006.168.08:27:52.32#ibcon#cleared, iclass 34 cls_cnt 0 2006.168.08:27:52.32$vc4f8/vb=6,4 2006.168.08:27:52.32#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.168.08:27:52.32#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.168.08:27:52.32#ibcon#ireg 11 cls_cnt 2 2006.168.08:27:52.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:27:52.38#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:27:52.38#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:27:52.38#ibcon#enter wrdev, iclass 36, count 2 2006.168.08:27:52.38#ibcon#first serial, iclass 36, count 2 2006.168.08:27:52.38#ibcon#enter sib2, iclass 36, count 2 2006.168.08:27:52.38#ibcon#flushed, iclass 36, count 2 2006.168.08:27:52.38#ibcon#about to write, iclass 36, count 2 2006.168.08:27:52.38#ibcon#wrote, iclass 36, count 2 2006.168.08:27:52.38#ibcon#about to read 3, iclass 36, count 2 2006.168.08:27:52.40#ibcon#read 3, iclass 36, count 2 2006.168.08:27:52.40#ibcon#about to read 4, iclass 36, count 2 2006.168.08:27:52.40#ibcon#read 4, iclass 36, count 2 2006.168.08:27:52.40#ibcon#about to read 5, iclass 36, count 2 2006.168.08:27:52.40#ibcon#read 5, iclass 36, count 2 2006.168.08:27:52.40#ibcon#about to read 6, iclass 36, count 2 2006.168.08:27:52.40#ibcon#read 6, iclass 36, count 2 2006.168.08:27:52.40#ibcon#end of sib2, iclass 36, count 2 2006.168.08:27:52.40#ibcon#*mode == 0, iclass 36, count 2 2006.168.08:27:52.40#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.168.08:27:52.40#ibcon#[27=AT06-04\r\n] 2006.168.08:27:52.40#ibcon#*before write, iclass 36, count 2 2006.168.08:27:52.40#ibcon#enter sib2, iclass 36, count 2 2006.168.08:27:52.40#ibcon#flushed, iclass 36, count 2 2006.168.08:27:52.40#ibcon#about to write, iclass 36, count 2 2006.168.08:27:52.40#ibcon#wrote, iclass 36, count 2 2006.168.08:27:52.40#ibcon#about to read 3, iclass 36, count 2 2006.168.08:27:52.43#ibcon#read 3, iclass 36, count 2 2006.168.08:27:52.43#ibcon#about to read 4, iclass 36, count 2 2006.168.08:27:52.43#ibcon#read 4, iclass 36, count 2 2006.168.08:27:52.43#ibcon#about to read 5, iclass 36, count 2 2006.168.08:27:52.43#ibcon#read 5, iclass 36, count 2 2006.168.08:27:52.43#ibcon#about to read 6, iclass 36, count 2 2006.168.08:27:52.43#ibcon#read 6, iclass 36, count 2 2006.168.08:27:52.43#ibcon#end of sib2, iclass 36, count 2 2006.168.08:27:52.43#ibcon#*after write, iclass 36, count 2 2006.168.08:27:52.43#ibcon#*before return 0, iclass 36, count 2 2006.168.08:27:52.43#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:27:52.43#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:27:52.43#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.168.08:27:52.43#ibcon#ireg 7 cls_cnt 0 2006.168.08:27:52.43#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:27:52.55#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:27:52.55#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:27:52.55#ibcon#enter wrdev, iclass 36, count 0 2006.168.08:27:52.55#ibcon#first serial, iclass 36, count 0 2006.168.08:27:52.55#ibcon#enter sib2, iclass 36, count 0 2006.168.08:27:52.55#ibcon#flushed, iclass 36, count 0 2006.168.08:27:52.55#ibcon#about to write, iclass 36, count 0 2006.168.08:27:52.55#ibcon#wrote, iclass 36, count 0 2006.168.08:27:52.55#ibcon#about to read 3, iclass 36, count 0 2006.168.08:27:52.57#ibcon#read 3, iclass 36, count 0 2006.168.08:27:52.57#ibcon#about to read 4, iclass 36, count 0 2006.168.08:27:52.57#ibcon#read 4, iclass 36, count 0 2006.168.08:27:52.57#ibcon#about to read 5, iclass 36, count 0 2006.168.08:27:52.57#ibcon#read 5, iclass 36, count 0 2006.168.08:27:52.57#ibcon#about to read 6, iclass 36, count 0 2006.168.08:27:52.57#ibcon#read 6, iclass 36, count 0 2006.168.08:27:52.57#ibcon#end of sib2, iclass 36, count 0 2006.168.08:27:52.57#ibcon#*mode == 0, iclass 36, count 0 2006.168.08:27:52.57#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.168.08:27:52.57#ibcon#[27=USB\r\n] 2006.168.08:27:52.57#ibcon#*before write, iclass 36, count 0 2006.168.08:27:52.57#ibcon#enter sib2, iclass 36, count 0 2006.168.08:27:52.57#ibcon#flushed, iclass 36, count 0 2006.168.08:27:52.57#ibcon#about to write, iclass 36, count 0 2006.168.08:27:52.57#ibcon#wrote, iclass 36, count 0 2006.168.08:27:52.57#ibcon#about to read 3, iclass 36, count 0 2006.168.08:27:52.60#ibcon#read 3, iclass 36, count 0 2006.168.08:27:52.60#ibcon#about to read 4, iclass 36, count 0 2006.168.08:27:52.60#ibcon#read 4, iclass 36, count 0 2006.168.08:27:52.60#ibcon#about to read 5, iclass 36, count 0 2006.168.08:27:52.60#ibcon#read 5, iclass 36, count 0 2006.168.08:27:52.60#ibcon#about to read 6, iclass 36, count 0 2006.168.08:27:52.60#ibcon#read 6, iclass 36, count 0 2006.168.08:27:52.60#ibcon#end of sib2, iclass 36, count 0 2006.168.08:27:52.60#ibcon#*after write, iclass 36, count 0 2006.168.08:27:52.60#ibcon#*before return 0, iclass 36, count 0 2006.168.08:27:52.60#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:27:52.60#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:27:52.60#ibcon#about to clear, iclass 36 cls_cnt 0 2006.168.08:27:52.60#ibcon#cleared, iclass 36 cls_cnt 0 2006.168.08:27:52.60$vc4f8/vabw=wide 2006.168.08:27:52.60#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.168.08:27:52.60#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.168.08:27:52.60#ibcon#ireg 8 cls_cnt 0 2006.168.08:27:52.60#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:27:52.60#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:27:52.60#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:27:52.60#ibcon#enter wrdev, iclass 38, count 0 2006.168.08:27:52.60#ibcon#first serial, iclass 38, count 0 2006.168.08:27:52.60#ibcon#enter sib2, iclass 38, count 0 2006.168.08:27:52.60#ibcon#flushed, iclass 38, count 0 2006.168.08:27:52.60#ibcon#about to write, iclass 38, count 0 2006.168.08:27:52.60#ibcon#wrote, iclass 38, count 0 2006.168.08:27:52.60#ibcon#about to read 3, iclass 38, count 0 2006.168.08:27:52.62#ibcon#read 3, iclass 38, count 0 2006.168.08:27:52.62#ibcon#about to read 4, iclass 38, count 0 2006.168.08:27:52.62#ibcon#read 4, iclass 38, count 0 2006.168.08:27:52.62#ibcon#about to read 5, iclass 38, count 0 2006.168.08:27:52.62#ibcon#read 5, iclass 38, count 0 2006.168.08:27:52.62#ibcon#about to read 6, iclass 38, count 0 2006.168.08:27:52.62#ibcon#read 6, iclass 38, count 0 2006.168.08:27:52.62#ibcon#end of sib2, iclass 38, count 0 2006.168.08:27:52.62#ibcon#*mode == 0, iclass 38, count 0 2006.168.08:27:52.62#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.168.08:27:52.62#ibcon#[25=BW32\r\n] 2006.168.08:27:52.62#ibcon#*before write, iclass 38, count 0 2006.168.08:27:52.62#ibcon#enter sib2, iclass 38, count 0 2006.168.08:27:52.62#ibcon#flushed, iclass 38, count 0 2006.168.08:27:52.62#ibcon#about to write, iclass 38, count 0 2006.168.08:27:52.62#ibcon#wrote, iclass 38, count 0 2006.168.08:27:52.62#ibcon#about to read 3, iclass 38, count 0 2006.168.08:27:52.65#ibcon#read 3, iclass 38, count 0 2006.168.08:27:52.65#ibcon#about to read 4, iclass 38, count 0 2006.168.08:27:52.65#ibcon#read 4, iclass 38, count 0 2006.168.08:27:52.65#ibcon#about to read 5, iclass 38, count 0 2006.168.08:27:52.65#ibcon#read 5, iclass 38, count 0 2006.168.08:27:52.65#ibcon#about to read 6, iclass 38, count 0 2006.168.08:27:52.65#ibcon#read 6, iclass 38, count 0 2006.168.08:27:52.65#ibcon#end of sib2, iclass 38, count 0 2006.168.08:27:52.65#ibcon#*after write, iclass 38, count 0 2006.168.08:27:52.65#ibcon#*before return 0, iclass 38, count 0 2006.168.08:27:52.65#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:27:52.65#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:27:52.65#ibcon#about to clear, iclass 38 cls_cnt 0 2006.168.08:27:52.65#ibcon#cleared, iclass 38 cls_cnt 0 2006.168.08:27:52.65$vc4f8/vbbw=wide 2006.168.08:27:52.65#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.168.08:27:52.65#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.168.08:27:52.65#ibcon#ireg 8 cls_cnt 0 2006.168.08:27:52.65#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:27:52.72#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:27:52.72#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:27:52.72#ibcon#enter wrdev, iclass 40, count 0 2006.168.08:27:52.72#ibcon#first serial, iclass 40, count 0 2006.168.08:27:52.72#ibcon#enter sib2, iclass 40, count 0 2006.168.08:27:52.72#ibcon#flushed, iclass 40, count 0 2006.168.08:27:52.72#ibcon#about to write, iclass 40, count 0 2006.168.08:27:52.72#ibcon#wrote, iclass 40, count 0 2006.168.08:27:52.72#ibcon#about to read 3, iclass 40, count 0 2006.168.08:27:52.74#ibcon#read 3, iclass 40, count 0 2006.168.08:27:52.74#ibcon#about to read 4, iclass 40, count 0 2006.168.08:27:52.74#ibcon#read 4, iclass 40, count 0 2006.168.08:27:52.74#ibcon#about to read 5, iclass 40, count 0 2006.168.08:27:52.74#ibcon#read 5, iclass 40, count 0 2006.168.08:27:52.74#ibcon#about to read 6, iclass 40, count 0 2006.168.08:27:52.74#ibcon#read 6, iclass 40, count 0 2006.168.08:27:52.74#ibcon#end of sib2, iclass 40, count 0 2006.168.08:27:52.74#ibcon#*mode == 0, iclass 40, count 0 2006.168.08:27:52.74#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.168.08:27:52.74#ibcon#[27=BW32\r\n] 2006.168.08:27:52.74#ibcon#*before write, iclass 40, count 0 2006.168.08:27:52.74#ibcon#enter sib2, iclass 40, count 0 2006.168.08:27:52.74#ibcon#flushed, iclass 40, count 0 2006.168.08:27:52.74#ibcon#about to write, iclass 40, count 0 2006.168.08:27:52.74#ibcon#wrote, iclass 40, count 0 2006.168.08:27:52.74#ibcon#about to read 3, iclass 40, count 0 2006.168.08:27:52.77#ibcon#read 3, iclass 40, count 0 2006.168.08:27:52.77#ibcon#about to read 4, iclass 40, count 0 2006.168.08:27:52.77#ibcon#read 4, iclass 40, count 0 2006.168.08:27:52.77#ibcon#about to read 5, iclass 40, count 0 2006.168.08:27:52.77#ibcon#read 5, iclass 40, count 0 2006.168.08:27:52.77#ibcon#about to read 6, iclass 40, count 0 2006.168.08:27:52.77#ibcon#read 6, iclass 40, count 0 2006.168.08:27:52.77#ibcon#end of sib2, iclass 40, count 0 2006.168.08:27:52.77#ibcon#*after write, iclass 40, count 0 2006.168.08:27:52.77#ibcon#*before return 0, iclass 40, count 0 2006.168.08:27:52.77#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:27:52.77#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.168.08:27:52.77#ibcon#about to clear, iclass 40 cls_cnt 0 2006.168.08:27:52.77#ibcon#cleared, iclass 40 cls_cnt 0 2006.168.08:27:52.77$4f8m12a/ifd4f 2006.168.08:27:52.77$ifd4f/lo= 2006.168.08:27:52.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.08:27:52.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.08:27:52.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.08:27:52.78$ifd4f/patch= 2006.168.08:27:52.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.08:27:52.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.08:27:52.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.08:27:52.78$4f8m12a/"form=m,16.000,1:2 2006.168.08:27:52.78$4f8m12a/"tpicd 2006.168.08:27:52.78$4f8m12a/echo=off 2006.168.08:27:52.78$4f8m12a/xlog=off 2006.168.08:27:52.78:!2006.168.08:28:20 2006.168.08:27:58.13#trakl#Source acquired 2006.168.08:27:59.13#flagr#flagr/antenna,acquired 2006.168.08:28:20.01:preob 2006.168.08:28:21.14/onsource/TRACKING 2006.168.08:28:21.14:!2006.168.08:28:30 2006.168.08:28:30.00:data_valid=on 2006.168.08:28:30.00:midob 2006.168.08:28:30.14/onsource/TRACKING 2006.168.08:28:30.14/wx/26.77,1004.6,76 2006.168.08:28:30.28/cable/+6.4725E-03 2006.168.08:28:31.37/va/01,08,usb,yes,30,31 2006.168.08:28:31.37/va/02,07,usb,yes,30,31 2006.168.08:28:31.37/va/03,06,usb,yes,32,32 2006.168.08:28:31.37/va/04,07,usb,yes,31,33 2006.168.08:28:31.37/va/05,07,usb,yes,31,33 2006.168.08:28:31.37/va/06,06,usb,yes,30,30 2006.168.08:28:31.37/va/07,06,usb,yes,31,30 2006.168.08:28:31.37/va/08,07,usb,yes,29,29 2006.168.08:28:31.60/valo/01,532.99,yes,locked 2006.168.08:28:31.60/valo/02,572.99,yes,locked 2006.168.08:28:31.60/valo/03,672.99,yes,locked 2006.168.08:28:31.60/valo/04,832.99,yes,locked 2006.168.08:28:31.60/valo/05,652.99,yes,locked 2006.168.08:28:31.60/valo/06,772.99,yes,locked 2006.168.08:28:31.60/valo/07,832.99,yes,locked 2006.168.08:28:31.60/valo/08,852.99,yes,locked 2006.168.08:28:32.69/vb/01,04,usb,yes,29,28 2006.168.08:28:32.69/vb/02,04,usb,yes,31,33 2006.168.08:28:32.69/vb/03,04,usb,yes,28,31 2006.168.08:28:32.69/vb/04,04,usb,yes,28,29 2006.168.08:28:32.69/vb/05,04,usb,yes,27,31 2006.168.08:28:32.69/vb/06,04,usb,yes,28,31 2006.168.08:28:32.69/vb/07,04,usb,yes,30,30 2006.168.08:28:32.69/vb/08,04,usb,yes,28,31 2006.168.08:28:32.92/vblo/01,632.99,yes,locked 2006.168.08:28:32.92/vblo/02,640.99,yes,locked 2006.168.08:28:32.92/vblo/03,656.99,yes,locked 2006.168.08:28:32.92/vblo/04,712.99,yes,locked 2006.168.08:28:32.92/vblo/05,744.99,yes,locked 2006.168.08:28:32.92/vblo/06,752.99,yes,locked 2006.168.08:28:32.92/vblo/07,734.99,yes,locked 2006.168.08:28:32.92/vblo/08,744.99,yes,locked 2006.168.08:28:33.07/vabw/8 2006.168.08:28:33.22/vbbw/8 2006.168.08:28:33.33/xfe/off,on,14.7 2006.168.08:28:33.71/ifatt/23,28,28,28 2006.168.08:28:34.07/fmout-gps/S +4.18E-07 2006.168.08:28:34.15:!2006.168.08:29:30 2006.168.08:29:30.01:data_valid=off 2006.168.08:29:30.02:postob 2006.168.08:29:30.09/cable/+6.4705E-03 2006.168.08:29:30.10/wx/26.77,1004.6,76 2006.168.08:29:31.07/fmout-gps/S +4.18E-07 2006.168.08:29:31.08:scan_name=168-0830,k06168,60 2006.168.08:29:31.08:source=1803+784,180045.68,782804.0,2000.0,cw 2006.168.08:29:31.14#flagr#flagr/antenna,new-source 2006.168.08:29:32.14:checkk5 2006.168.08:29:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.168.08:29:32.90/chk_autoobs//k5ts2/ autoobs is running! 2006.168.08:29:33.28/chk_autoobs//k5ts3/ autoobs is running! 2006.168.08:29:33.66/chk_autoobs//k5ts4/ autoobs is running! 2006.168.08:29:34.02/chk_obsdata//k5ts1/T1680828??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:29:34.39/chk_obsdata//k5ts2/T1680828??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:29:34.76/chk_obsdata//k5ts3/T1680828??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:29:35.13/chk_obsdata//k5ts4/T1680828??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.168.08:29:35.83/k5log//k5ts1_log_newline 2006.168.08:29:36.52/k5log//k5ts2_log_newline 2006.168.08:29:37.22/k5log//k5ts3_log_newline 2006.168.08:29:37.91/k5log//k5ts4_log_newline 2006.168.08:29:37.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.08:29:37.93:4f8m12a=3 2006.168.08:29:37.93$4f8m12a/echo=on 2006.168.08:29:37.94$4f8m12a/pcalon 2006.168.08:29:37.94$pcalon/"no phase cal control is implemented here 2006.168.08:29:37.94$4f8m12a/"tpicd=stop 2006.168.08:29:37.94$4f8m12a/vc4f8 2006.168.08:29:37.94$vc4f8/valo=1,532.99 2006.168.08:29:37.94#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.168.08:29:37.94#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.168.08:29:37.94#ibcon#ireg 17 cls_cnt 0 2006.168.08:29:37.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:29:37.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:29:37.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:29:37.94#ibcon#enter wrdev, iclass 4, count 0 2006.168.08:29:37.94#ibcon#first serial, iclass 4, count 0 2006.168.08:29:37.94#ibcon#enter sib2, iclass 4, count 0 2006.168.08:29:37.94#ibcon#flushed, iclass 4, count 0 2006.168.08:29:37.94#ibcon#about to write, iclass 4, count 0 2006.168.08:29:37.94#ibcon#wrote, iclass 4, count 0 2006.168.08:29:37.94#ibcon#about to read 3, iclass 4, count 0 2006.168.08:29:37.98#ibcon#read 3, iclass 4, count 0 2006.168.08:29:37.98#ibcon#about to read 4, iclass 4, count 0 2006.168.08:29:37.98#ibcon#read 4, iclass 4, count 0 2006.168.08:29:37.98#ibcon#about to read 5, iclass 4, count 0 2006.168.08:29:37.98#ibcon#read 5, iclass 4, count 0 2006.168.08:29:37.98#ibcon#about to read 6, iclass 4, count 0 2006.168.08:29:37.98#ibcon#read 6, iclass 4, count 0 2006.168.08:29:37.98#ibcon#end of sib2, iclass 4, count 0 2006.168.08:29:37.98#ibcon#*mode == 0, iclass 4, count 0 2006.168.08:29:37.98#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.168.08:29:37.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.168.08:29:37.98#ibcon#*before write, iclass 4, count 0 2006.168.08:29:37.98#ibcon#enter sib2, iclass 4, count 0 2006.168.08:29:37.98#ibcon#flushed, iclass 4, count 0 2006.168.08:29:37.98#ibcon#about to write, iclass 4, count 0 2006.168.08:29:37.98#ibcon#wrote, iclass 4, count 0 2006.168.08:29:37.98#ibcon#about to read 3, iclass 4, count 0 2006.168.08:29:38.03#ibcon#read 3, iclass 4, count 0 2006.168.08:29:38.03#ibcon#about to read 4, iclass 4, count 0 2006.168.08:29:38.03#ibcon#read 4, iclass 4, count 0 2006.168.08:29:38.03#ibcon#about to read 5, iclass 4, count 0 2006.168.08:29:38.03#ibcon#read 5, iclass 4, count 0 2006.168.08:29:38.03#ibcon#about to read 6, iclass 4, count 0 2006.168.08:29:38.03#ibcon#read 6, iclass 4, count 0 2006.168.08:29:38.03#ibcon#end of sib2, iclass 4, count 0 2006.168.08:29:38.03#ibcon#*after write, iclass 4, count 0 2006.168.08:29:38.03#ibcon#*before return 0, iclass 4, count 0 2006.168.08:29:38.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:29:38.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:29:38.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.168.08:29:38.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.168.08:29:38.03$vc4f8/va=1,8 2006.168.08:29:38.03#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.168.08:29:38.03#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.168.08:29:38.03#ibcon#ireg 11 cls_cnt 2 2006.168.08:29:38.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:29:38.03#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:29:38.03#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:29:38.03#ibcon#enter wrdev, iclass 6, count 2 2006.168.08:29:38.03#ibcon#first serial, iclass 6, count 2 2006.168.08:29:38.03#ibcon#enter sib2, iclass 6, count 2 2006.168.08:29:38.03#ibcon#flushed, iclass 6, count 2 2006.168.08:29:38.03#ibcon#about to write, iclass 6, count 2 2006.168.08:29:38.03#ibcon#wrote, iclass 6, count 2 2006.168.08:29:38.03#ibcon#about to read 3, iclass 6, count 2 2006.168.08:29:38.06#ibcon#read 3, iclass 6, count 2 2006.168.08:29:38.06#ibcon#about to read 4, iclass 6, count 2 2006.168.08:29:38.06#ibcon#read 4, iclass 6, count 2 2006.168.08:29:38.06#ibcon#about to read 5, iclass 6, count 2 2006.168.08:29:38.06#ibcon#read 5, iclass 6, count 2 2006.168.08:29:38.06#ibcon#about to read 6, iclass 6, count 2 2006.168.08:29:38.06#ibcon#read 6, iclass 6, count 2 2006.168.08:29:38.06#ibcon#end of sib2, iclass 6, count 2 2006.168.08:29:38.06#ibcon#*mode == 0, iclass 6, count 2 2006.168.08:29:38.06#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.168.08:29:38.06#ibcon#[25=AT01-08\r\n] 2006.168.08:29:38.06#ibcon#*before write, iclass 6, count 2 2006.168.08:29:38.06#ibcon#enter sib2, iclass 6, count 2 2006.168.08:29:38.06#ibcon#flushed, iclass 6, count 2 2006.168.08:29:38.06#ibcon#about to write, iclass 6, count 2 2006.168.08:29:38.06#ibcon#wrote, iclass 6, count 2 2006.168.08:29:38.06#ibcon#about to read 3, iclass 6, count 2 2006.168.08:29:38.10#ibcon#read 3, iclass 6, count 2 2006.168.08:29:38.10#ibcon#about to read 4, iclass 6, count 2 2006.168.08:29:38.10#ibcon#read 4, iclass 6, count 2 2006.168.08:29:38.10#ibcon#about to read 5, iclass 6, count 2 2006.168.08:29:38.10#ibcon#read 5, iclass 6, count 2 2006.168.08:29:38.10#ibcon#about to read 6, iclass 6, count 2 2006.168.08:29:38.10#ibcon#read 6, iclass 6, count 2 2006.168.08:29:38.10#ibcon#end of sib2, iclass 6, count 2 2006.168.08:29:38.10#ibcon#*after write, iclass 6, count 2 2006.168.08:29:38.10#ibcon#*before return 0, iclass 6, count 2 2006.168.08:29:38.10#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:29:38.10#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:29:38.10#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.168.08:29:38.10#ibcon#ireg 7 cls_cnt 0 2006.168.08:29:38.10#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:29:38.21#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:29:38.21#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:29:38.21#ibcon#enter wrdev, iclass 6, count 0 2006.168.08:29:38.21#ibcon#first serial, iclass 6, count 0 2006.168.08:29:38.21#ibcon#enter sib2, iclass 6, count 0 2006.168.08:29:38.21#ibcon#flushed, iclass 6, count 0 2006.168.08:29:38.21#ibcon#about to write, iclass 6, count 0 2006.168.08:29:38.21#ibcon#wrote, iclass 6, count 0 2006.168.08:29:38.21#ibcon#about to read 3, iclass 6, count 0 2006.168.08:29:38.23#ibcon#read 3, iclass 6, count 0 2006.168.08:29:38.23#ibcon#about to read 4, iclass 6, count 0 2006.168.08:29:38.23#ibcon#read 4, iclass 6, count 0 2006.168.08:29:38.23#ibcon#about to read 5, iclass 6, count 0 2006.168.08:29:38.23#ibcon#read 5, iclass 6, count 0 2006.168.08:29:38.23#ibcon#about to read 6, iclass 6, count 0 2006.168.08:29:38.23#ibcon#read 6, iclass 6, count 0 2006.168.08:29:38.23#ibcon#end of sib2, iclass 6, count 0 2006.168.08:29:38.23#ibcon#*mode == 0, iclass 6, count 0 2006.168.08:29:38.23#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.168.08:29:38.23#ibcon#[25=USB\r\n] 2006.168.08:29:38.23#ibcon#*before write, iclass 6, count 0 2006.168.08:29:38.23#ibcon#enter sib2, iclass 6, count 0 2006.168.08:29:38.23#ibcon#flushed, iclass 6, count 0 2006.168.08:29:38.23#ibcon#about to write, iclass 6, count 0 2006.168.08:29:38.23#ibcon#wrote, iclass 6, count 0 2006.168.08:29:38.23#ibcon#about to read 3, iclass 6, count 0 2006.168.08:29:38.26#ibcon#read 3, iclass 6, count 0 2006.168.08:29:38.26#ibcon#about to read 4, iclass 6, count 0 2006.168.08:29:38.26#ibcon#read 4, iclass 6, count 0 2006.168.08:29:38.26#ibcon#about to read 5, iclass 6, count 0 2006.168.08:29:38.26#ibcon#read 5, iclass 6, count 0 2006.168.08:29:38.26#ibcon#about to read 6, iclass 6, count 0 2006.168.08:29:38.26#ibcon#read 6, iclass 6, count 0 2006.168.08:29:38.26#ibcon#end of sib2, iclass 6, count 0 2006.168.08:29:38.26#ibcon#*after write, iclass 6, count 0 2006.168.08:29:38.26#ibcon#*before return 0, iclass 6, count 0 2006.168.08:29:38.26#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:29:38.26#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:29:38.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.168.08:29:38.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.168.08:29:38.26$vc4f8/valo=2,572.99 2006.168.08:29:38.26#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.168.08:29:38.26#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.168.08:29:38.26#ibcon#ireg 17 cls_cnt 0 2006.168.08:29:38.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:29:38.26#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:29:38.26#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:29:38.26#ibcon#enter wrdev, iclass 10, count 0 2006.168.08:29:38.26#ibcon#first serial, iclass 10, count 0 2006.168.08:29:38.26#ibcon#enter sib2, iclass 10, count 0 2006.168.08:29:38.26#ibcon#flushed, iclass 10, count 0 2006.168.08:29:38.26#ibcon#about to write, iclass 10, count 0 2006.168.08:29:38.26#ibcon#wrote, iclass 10, count 0 2006.168.08:29:38.26#ibcon#about to read 3, iclass 10, count 0 2006.168.08:29:38.28#ibcon#read 3, iclass 10, count 0 2006.168.08:29:38.28#ibcon#about to read 4, iclass 10, count 0 2006.168.08:29:38.28#ibcon#read 4, iclass 10, count 0 2006.168.08:29:38.28#ibcon#about to read 5, iclass 10, count 0 2006.168.08:29:38.28#ibcon#read 5, iclass 10, count 0 2006.168.08:29:38.28#ibcon#about to read 6, iclass 10, count 0 2006.168.08:29:38.28#ibcon#read 6, iclass 10, count 0 2006.168.08:29:38.28#ibcon#end of sib2, iclass 10, count 0 2006.168.08:29:38.28#ibcon#*mode == 0, iclass 10, count 0 2006.168.08:29:38.28#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.168.08:29:38.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.168.08:29:38.28#ibcon#*before write, iclass 10, count 0 2006.168.08:29:38.28#ibcon#enter sib2, iclass 10, count 0 2006.168.08:29:38.28#ibcon#flushed, iclass 10, count 0 2006.168.08:29:38.28#ibcon#about to write, iclass 10, count 0 2006.168.08:29:38.28#ibcon#wrote, iclass 10, count 0 2006.168.08:29:38.28#ibcon#about to read 3, iclass 10, count 0 2006.168.08:29:38.32#ibcon#read 3, iclass 10, count 0 2006.168.08:29:38.32#ibcon#about to read 4, iclass 10, count 0 2006.168.08:29:38.32#ibcon#read 4, iclass 10, count 0 2006.168.08:29:38.32#ibcon#about to read 5, iclass 10, count 0 2006.168.08:29:38.32#ibcon#read 5, iclass 10, count 0 2006.168.08:29:38.32#ibcon#about to read 6, iclass 10, count 0 2006.168.08:29:38.32#ibcon#read 6, iclass 10, count 0 2006.168.08:29:38.32#ibcon#end of sib2, iclass 10, count 0 2006.168.08:29:38.32#ibcon#*after write, iclass 10, count 0 2006.168.08:29:38.32#ibcon#*before return 0, iclass 10, count 0 2006.168.08:29:38.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:29:38.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:29:38.32#ibcon#about to clear, iclass 10 cls_cnt 0 2006.168.08:29:38.32#ibcon#cleared, iclass 10 cls_cnt 0 2006.168.08:29:38.32$vc4f8/va=2,7 2006.168.08:29:38.32#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.168.08:29:38.32#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.168.08:29:38.32#ibcon#ireg 11 cls_cnt 2 2006.168.08:29:38.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:29:38.38#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:29:38.38#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:29:38.38#ibcon#enter wrdev, iclass 12, count 2 2006.168.08:29:38.38#ibcon#first serial, iclass 12, count 2 2006.168.08:29:38.38#ibcon#enter sib2, iclass 12, count 2 2006.168.08:29:38.38#ibcon#flushed, iclass 12, count 2 2006.168.08:29:38.38#ibcon#about to write, iclass 12, count 2 2006.168.08:29:38.38#ibcon#wrote, iclass 12, count 2 2006.168.08:29:38.38#ibcon#about to read 3, iclass 12, count 2 2006.168.08:29:38.41#ibcon#read 3, iclass 12, count 2 2006.168.08:29:38.41#ibcon#about to read 4, iclass 12, count 2 2006.168.08:29:38.41#ibcon#read 4, iclass 12, count 2 2006.168.08:29:38.41#ibcon#about to read 5, iclass 12, count 2 2006.168.08:29:38.41#ibcon#read 5, iclass 12, count 2 2006.168.08:29:38.41#ibcon#about to read 6, iclass 12, count 2 2006.168.08:29:38.41#ibcon#read 6, iclass 12, count 2 2006.168.08:29:38.41#ibcon#end of sib2, iclass 12, count 2 2006.168.08:29:38.41#ibcon#*mode == 0, iclass 12, count 2 2006.168.08:29:38.41#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.168.08:29:38.41#ibcon#[25=AT02-07\r\n] 2006.168.08:29:38.41#ibcon#*before write, iclass 12, count 2 2006.168.08:29:38.41#ibcon#enter sib2, iclass 12, count 2 2006.168.08:29:38.41#ibcon#flushed, iclass 12, count 2 2006.168.08:29:38.41#ibcon#about to write, iclass 12, count 2 2006.168.08:29:38.41#ibcon#wrote, iclass 12, count 2 2006.168.08:29:38.41#ibcon#about to read 3, iclass 12, count 2 2006.168.08:29:38.44#ibcon#read 3, iclass 12, count 2 2006.168.08:29:38.44#ibcon#about to read 4, iclass 12, count 2 2006.168.08:29:38.44#ibcon#read 4, iclass 12, count 2 2006.168.08:29:38.44#ibcon#about to read 5, iclass 12, count 2 2006.168.08:29:38.44#ibcon#read 5, iclass 12, count 2 2006.168.08:29:38.44#ibcon#about to read 6, iclass 12, count 2 2006.168.08:29:38.44#ibcon#read 6, iclass 12, count 2 2006.168.08:29:38.44#ibcon#end of sib2, iclass 12, count 2 2006.168.08:29:38.44#ibcon#*after write, iclass 12, count 2 2006.168.08:29:38.44#ibcon#*before return 0, iclass 12, count 2 2006.168.08:29:38.44#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:29:38.44#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:29:38.44#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.168.08:29:38.44#ibcon#ireg 7 cls_cnt 0 2006.168.08:29:38.44#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:29:38.56#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:29:38.56#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:29:38.56#ibcon#enter wrdev, iclass 12, count 0 2006.168.08:29:38.56#ibcon#first serial, iclass 12, count 0 2006.168.08:29:38.56#ibcon#enter sib2, iclass 12, count 0 2006.168.08:29:38.56#ibcon#flushed, iclass 12, count 0 2006.168.08:29:38.56#ibcon#about to write, iclass 12, count 0 2006.168.08:29:38.56#ibcon#wrote, iclass 12, count 0 2006.168.08:29:38.56#ibcon#about to read 3, iclass 12, count 0 2006.168.08:29:38.58#ibcon#read 3, iclass 12, count 0 2006.168.08:29:38.58#ibcon#about to read 4, iclass 12, count 0 2006.168.08:29:38.58#ibcon#read 4, iclass 12, count 0 2006.168.08:29:38.58#ibcon#about to read 5, iclass 12, count 0 2006.168.08:29:38.58#ibcon#read 5, iclass 12, count 0 2006.168.08:29:38.58#ibcon#about to read 6, iclass 12, count 0 2006.168.08:29:38.58#ibcon#read 6, iclass 12, count 0 2006.168.08:29:38.58#ibcon#end of sib2, iclass 12, count 0 2006.168.08:29:38.58#ibcon#*mode == 0, iclass 12, count 0 2006.168.08:29:38.58#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.168.08:29:38.58#ibcon#[25=USB\r\n] 2006.168.08:29:38.58#ibcon#*before write, iclass 12, count 0 2006.168.08:29:38.58#ibcon#enter sib2, iclass 12, count 0 2006.168.08:29:38.58#ibcon#flushed, iclass 12, count 0 2006.168.08:29:38.58#ibcon#about to write, iclass 12, count 0 2006.168.08:29:38.58#ibcon#wrote, iclass 12, count 0 2006.168.08:29:38.58#ibcon#about to read 3, iclass 12, count 0 2006.168.08:29:38.61#ibcon#read 3, iclass 12, count 0 2006.168.08:29:38.61#ibcon#about to read 4, iclass 12, count 0 2006.168.08:29:38.61#ibcon#read 4, iclass 12, count 0 2006.168.08:29:38.61#ibcon#about to read 5, iclass 12, count 0 2006.168.08:29:38.61#ibcon#read 5, iclass 12, count 0 2006.168.08:29:38.61#ibcon#about to read 6, iclass 12, count 0 2006.168.08:29:38.61#ibcon#read 6, iclass 12, count 0 2006.168.08:29:38.61#ibcon#end of sib2, iclass 12, count 0 2006.168.08:29:38.61#ibcon#*after write, iclass 12, count 0 2006.168.08:29:38.61#ibcon#*before return 0, iclass 12, count 0 2006.168.08:29:38.61#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:29:38.61#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:29:38.61#ibcon#about to clear, iclass 12 cls_cnt 0 2006.168.08:29:38.61#ibcon#cleared, iclass 12 cls_cnt 0 2006.168.08:29:38.61$vc4f8/valo=3,672.99 2006.168.08:29:38.61#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.168.08:29:38.61#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.168.08:29:38.61#ibcon#ireg 17 cls_cnt 0 2006.168.08:29:38.61#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:29:38.61#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:29:38.61#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:29:38.61#ibcon#enter wrdev, iclass 14, count 0 2006.168.08:29:38.61#ibcon#first serial, iclass 14, count 0 2006.168.08:29:38.61#ibcon#enter sib2, iclass 14, count 0 2006.168.08:29:38.61#ibcon#flushed, iclass 14, count 0 2006.168.08:29:38.61#ibcon#about to write, iclass 14, count 0 2006.168.08:29:38.61#ibcon#wrote, iclass 14, count 0 2006.168.08:29:38.61#ibcon#about to read 3, iclass 14, count 0 2006.168.08:29:38.63#ibcon#read 3, iclass 14, count 0 2006.168.08:29:38.63#ibcon#about to read 4, iclass 14, count 0 2006.168.08:29:38.63#ibcon#read 4, iclass 14, count 0 2006.168.08:29:38.63#ibcon#about to read 5, iclass 14, count 0 2006.168.08:29:38.63#ibcon#read 5, iclass 14, count 0 2006.168.08:29:38.63#ibcon#about to read 6, iclass 14, count 0 2006.168.08:29:38.63#ibcon#read 6, iclass 14, count 0 2006.168.08:29:38.63#ibcon#end of sib2, iclass 14, count 0 2006.168.08:29:38.63#ibcon#*mode == 0, iclass 14, count 0 2006.168.08:29:38.63#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.168.08:29:38.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.168.08:29:38.63#ibcon#*before write, iclass 14, count 0 2006.168.08:29:38.63#ibcon#enter sib2, iclass 14, count 0 2006.168.08:29:38.63#ibcon#flushed, iclass 14, count 0 2006.168.08:29:38.63#ibcon#about to write, iclass 14, count 0 2006.168.08:29:38.63#ibcon#wrote, iclass 14, count 0 2006.168.08:29:38.63#ibcon#about to read 3, iclass 14, count 0 2006.168.08:29:38.67#ibcon#read 3, iclass 14, count 0 2006.168.08:29:38.67#ibcon#about to read 4, iclass 14, count 0 2006.168.08:29:38.67#ibcon#read 4, iclass 14, count 0 2006.168.08:29:38.67#ibcon#about to read 5, iclass 14, count 0 2006.168.08:29:38.67#ibcon#read 5, iclass 14, count 0 2006.168.08:29:38.67#ibcon#about to read 6, iclass 14, count 0 2006.168.08:29:38.67#ibcon#read 6, iclass 14, count 0 2006.168.08:29:38.67#ibcon#end of sib2, iclass 14, count 0 2006.168.08:29:38.67#ibcon#*after write, iclass 14, count 0 2006.168.08:29:38.67#ibcon#*before return 0, iclass 14, count 0 2006.168.08:29:38.67#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:29:38.67#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:29:38.67#ibcon#about to clear, iclass 14 cls_cnt 0 2006.168.08:29:38.67#ibcon#cleared, iclass 14 cls_cnt 0 2006.168.08:29:38.67$vc4f8/va=3,6 2006.168.08:29:38.67#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.168.08:29:38.67#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.168.08:29:38.67#ibcon#ireg 11 cls_cnt 2 2006.168.08:29:38.67#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:29:38.74#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:29:38.74#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:29:38.74#ibcon#enter wrdev, iclass 16, count 2 2006.168.08:29:38.74#ibcon#first serial, iclass 16, count 2 2006.168.08:29:38.74#ibcon#enter sib2, iclass 16, count 2 2006.168.08:29:38.74#ibcon#flushed, iclass 16, count 2 2006.168.08:29:38.74#ibcon#about to write, iclass 16, count 2 2006.168.08:29:38.74#ibcon#wrote, iclass 16, count 2 2006.168.08:29:38.74#ibcon#about to read 3, iclass 16, count 2 2006.168.08:29:38.76#ibcon#read 3, iclass 16, count 2 2006.168.08:29:38.76#ibcon#about to read 4, iclass 16, count 2 2006.168.08:29:38.76#ibcon#read 4, iclass 16, count 2 2006.168.08:29:38.76#ibcon#about to read 5, iclass 16, count 2 2006.168.08:29:38.76#ibcon#read 5, iclass 16, count 2 2006.168.08:29:38.76#ibcon#about to read 6, iclass 16, count 2 2006.168.08:29:38.76#ibcon#read 6, iclass 16, count 2 2006.168.08:29:38.76#ibcon#end of sib2, iclass 16, count 2 2006.168.08:29:38.76#ibcon#*mode == 0, iclass 16, count 2 2006.168.08:29:38.76#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.168.08:29:38.76#ibcon#[25=AT03-06\r\n] 2006.168.08:29:38.76#ibcon#*before write, iclass 16, count 2 2006.168.08:29:38.76#ibcon#enter sib2, iclass 16, count 2 2006.168.08:29:38.76#ibcon#flushed, iclass 16, count 2 2006.168.08:29:38.76#ibcon#about to write, iclass 16, count 2 2006.168.08:29:38.76#ibcon#wrote, iclass 16, count 2 2006.168.08:29:38.76#ibcon#about to read 3, iclass 16, count 2 2006.168.08:29:38.78#ibcon#read 3, iclass 16, count 2 2006.168.08:29:38.78#ibcon#about to read 4, iclass 16, count 2 2006.168.08:29:38.78#ibcon#read 4, iclass 16, count 2 2006.168.08:29:38.78#ibcon#about to read 5, iclass 16, count 2 2006.168.08:29:38.78#ibcon#read 5, iclass 16, count 2 2006.168.08:29:38.78#ibcon#about to read 6, iclass 16, count 2 2006.168.08:29:38.78#ibcon#read 6, iclass 16, count 2 2006.168.08:29:38.78#ibcon#end of sib2, iclass 16, count 2 2006.168.08:29:38.78#ibcon#*after write, iclass 16, count 2 2006.168.08:29:38.78#ibcon#*before return 0, iclass 16, count 2 2006.168.08:29:38.78#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:29:38.78#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.168.08:29:38.78#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.168.08:29:38.78#ibcon#ireg 7 cls_cnt 0 2006.168.08:29:38.78#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:29:38.90#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:29:38.90#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:29:38.90#ibcon#enter wrdev, iclass 16, count 0 2006.168.08:29:38.90#ibcon#first serial, iclass 16, count 0 2006.168.08:29:38.90#ibcon#enter sib2, iclass 16, count 0 2006.168.08:29:38.90#ibcon#flushed, iclass 16, count 0 2006.168.08:29:38.90#ibcon#about to write, iclass 16, count 0 2006.168.08:29:38.90#ibcon#wrote, iclass 16, count 0 2006.168.08:29:38.90#ibcon#about to read 3, iclass 16, count 0 2006.168.08:29:38.92#ibcon#read 3, iclass 16, count 0 2006.168.08:29:38.92#ibcon#about to read 4, iclass 16, count 0 2006.168.08:29:38.92#ibcon#read 4, iclass 16, count 0 2006.168.08:29:38.92#ibcon#about to read 5, iclass 16, count 0 2006.168.08:29:38.92#ibcon#read 5, iclass 16, count 0 2006.168.08:29:38.92#ibcon#about to read 6, iclass 16, count 0 2006.168.08:29:38.92#ibcon#read 6, iclass 16, count 0 2006.168.08:29:38.92#ibcon#end of sib2, iclass 16, count 0 2006.168.08:29:38.92#ibcon#*mode == 0, iclass 16, count 0 2006.168.08:29:38.92#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.168.08:29:38.92#ibcon#[25=USB\r\n] 2006.168.08:29:38.92#ibcon#*before write, iclass 16, count 0 2006.168.08:29:38.92#ibcon#enter sib2, iclass 16, count 0 2006.168.08:29:38.92#ibcon#flushed, iclass 16, count 0 2006.168.08:29:38.92#ibcon#about to write, iclass 16, count 0 2006.168.08:29:38.92#ibcon#wrote, iclass 16, count 0 2006.168.08:29:38.92#ibcon#about to read 3, iclass 16, count 0 2006.168.08:29:38.95#ibcon#read 3, iclass 16, count 0 2006.168.08:29:38.95#ibcon#about to read 4, iclass 16, count 0 2006.168.08:29:38.95#ibcon#read 4, iclass 16, count 0 2006.168.08:29:38.95#ibcon#about to read 5, iclass 16, count 0 2006.168.08:29:38.95#ibcon#read 5, iclass 16, count 0 2006.168.08:29:38.95#ibcon#about to read 6, iclass 16, count 0 2006.168.08:29:38.95#ibcon#read 6, iclass 16, count 0 2006.168.08:29:38.95#ibcon#end of sib2, iclass 16, count 0 2006.168.08:29:38.95#ibcon#*after write, iclass 16, count 0 2006.168.08:29:38.95#ibcon#*before return 0, iclass 16, count 0 2006.168.08:29:38.95#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:29:38.95#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.168.08:29:38.95#ibcon#about to clear, iclass 16 cls_cnt 0 2006.168.08:29:38.95#ibcon#cleared, iclass 16 cls_cnt 0 2006.168.08:29:38.95$vc4f8/valo=4,832.99 2006.168.08:29:38.95#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.168.08:29:38.95#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.168.08:29:38.95#ibcon#ireg 17 cls_cnt 0 2006.168.08:29:38.95#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:29:38.95#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:29:38.95#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:29:38.95#ibcon#enter wrdev, iclass 18, count 0 2006.168.08:29:38.95#ibcon#first serial, iclass 18, count 0 2006.168.08:29:38.95#ibcon#enter sib2, iclass 18, count 0 2006.168.08:29:38.95#ibcon#flushed, iclass 18, count 0 2006.168.08:29:38.95#ibcon#about to write, iclass 18, count 0 2006.168.08:29:38.95#ibcon#wrote, iclass 18, count 0 2006.168.08:29:38.95#ibcon#about to read 3, iclass 18, count 0 2006.168.08:29:38.97#ibcon#read 3, iclass 18, count 0 2006.168.08:29:38.97#ibcon#about to read 4, iclass 18, count 0 2006.168.08:29:38.97#ibcon#read 4, iclass 18, count 0 2006.168.08:29:38.97#ibcon#about to read 5, iclass 18, count 0 2006.168.08:29:38.97#ibcon#read 5, iclass 18, count 0 2006.168.08:29:38.97#ibcon#about to read 6, iclass 18, count 0 2006.168.08:29:38.97#ibcon#read 6, iclass 18, count 0 2006.168.08:29:38.97#ibcon#end of sib2, iclass 18, count 0 2006.168.08:29:38.97#ibcon#*mode == 0, iclass 18, count 0 2006.168.08:29:38.97#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.168.08:29:38.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.168.08:29:38.97#ibcon#*before write, iclass 18, count 0 2006.168.08:29:38.97#ibcon#enter sib2, iclass 18, count 0 2006.168.08:29:38.97#ibcon#flushed, iclass 18, count 0 2006.168.08:29:38.97#ibcon#about to write, iclass 18, count 0 2006.168.08:29:38.97#ibcon#wrote, iclass 18, count 0 2006.168.08:29:38.97#ibcon#about to read 3, iclass 18, count 0 2006.168.08:29:39.01#ibcon#read 3, iclass 18, count 0 2006.168.08:29:39.01#ibcon#about to read 4, iclass 18, count 0 2006.168.08:29:39.01#ibcon#read 4, iclass 18, count 0 2006.168.08:29:39.01#ibcon#about to read 5, iclass 18, count 0 2006.168.08:29:39.01#ibcon#read 5, iclass 18, count 0 2006.168.08:29:39.01#ibcon#about to read 6, iclass 18, count 0 2006.168.08:29:39.01#ibcon#read 6, iclass 18, count 0 2006.168.08:29:39.01#ibcon#end of sib2, iclass 18, count 0 2006.168.08:29:39.01#ibcon#*after write, iclass 18, count 0 2006.168.08:29:39.01#ibcon#*before return 0, iclass 18, count 0 2006.168.08:29:39.01#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:29:39.01#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.168.08:29:39.01#ibcon#about to clear, iclass 18 cls_cnt 0 2006.168.08:29:39.01#ibcon#cleared, iclass 18 cls_cnt 0 2006.168.08:29:39.01$vc4f8/va=4,7 2006.168.08:29:39.01#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.168.08:29:39.01#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.168.08:29:39.01#ibcon#ireg 11 cls_cnt 2 2006.168.08:29:39.01#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:29:39.07#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:29:39.07#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:29:39.07#ibcon#enter wrdev, iclass 20, count 2 2006.168.08:29:39.07#ibcon#first serial, iclass 20, count 2 2006.168.08:29:39.07#ibcon#enter sib2, iclass 20, count 2 2006.168.08:29:39.07#ibcon#flushed, iclass 20, count 2 2006.168.08:29:39.07#ibcon#about to write, iclass 20, count 2 2006.168.08:29:39.07#ibcon#wrote, iclass 20, count 2 2006.168.08:29:39.07#ibcon#about to read 3, iclass 20, count 2 2006.168.08:29:39.09#ibcon#read 3, iclass 20, count 2 2006.168.08:29:39.09#ibcon#about to read 4, iclass 20, count 2 2006.168.08:29:39.09#ibcon#read 4, iclass 20, count 2 2006.168.08:29:39.09#ibcon#about to read 5, iclass 20, count 2 2006.168.08:29:39.09#ibcon#read 5, iclass 20, count 2 2006.168.08:29:39.09#ibcon#about to read 6, iclass 20, count 2 2006.168.08:29:39.09#ibcon#read 6, iclass 20, count 2 2006.168.08:29:39.09#ibcon#end of sib2, iclass 20, count 2 2006.168.08:29:39.09#ibcon#*mode == 0, iclass 20, count 2 2006.168.08:29:39.09#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.168.08:29:39.09#ibcon#[25=AT04-07\r\n] 2006.168.08:29:39.09#ibcon#*before write, iclass 20, count 2 2006.168.08:29:39.09#ibcon#enter sib2, iclass 20, count 2 2006.168.08:29:39.09#ibcon#flushed, iclass 20, count 2 2006.168.08:29:39.09#ibcon#about to write, iclass 20, count 2 2006.168.08:29:39.09#ibcon#wrote, iclass 20, count 2 2006.168.08:29:39.09#ibcon#about to read 3, iclass 20, count 2 2006.168.08:29:39.12#ibcon#read 3, iclass 20, count 2 2006.168.08:29:39.12#ibcon#about to read 4, iclass 20, count 2 2006.168.08:29:39.12#ibcon#read 4, iclass 20, count 2 2006.168.08:29:39.12#ibcon#about to read 5, iclass 20, count 2 2006.168.08:29:39.12#ibcon#read 5, iclass 20, count 2 2006.168.08:29:39.12#ibcon#about to read 6, iclass 20, count 2 2006.168.08:29:39.12#ibcon#read 6, iclass 20, count 2 2006.168.08:29:39.12#ibcon#end of sib2, iclass 20, count 2 2006.168.08:29:39.12#ibcon#*after write, iclass 20, count 2 2006.168.08:29:39.12#ibcon#*before return 0, iclass 20, count 2 2006.168.08:29:39.12#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:29:39.12#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.168.08:29:39.12#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.168.08:29:39.12#ibcon#ireg 7 cls_cnt 0 2006.168.08:29:39.12#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:29:39.24#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:29:39.24#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:29:39.24#ibcon#enter wrdev, iclass 20, count 0 2006.168.08:29:39.24#ibcon#first serial, iclass 20, count 0 2006.168.08:29:39.24#ibcon#enter sib2, iclass 20, count 0 2006.168.08:29:39.24#ibcon#flushed, iclass 20, count 0 2006.168.08:29:39.24#ibcon#about to write, iclass 20, count 0 2006.168.08:29:39.24#ibcon#wrote, iclass 20, count 0 2006.168.08:29:39.24#ibcon#about to read 3, iclass 20, count 0 2006.168.08:29:39.26#ibcon#read 3, iclass 20, count 0 2006.168.08:29:39.26#ibcon#about to read 4, iclass 20, count 0 2006.168.08:29:39.26#ibcon#read 4, iclass 20, count 0 2006.168.08:29:39.26#ibcon#about to read 5, iclass 20, count 0 2006.168.08:29:39.26#ibcon#read 5, iclass 20, count 0 2006.168.08:29:39.26#ibcon#about to read 6, iclass 20, count 0 2006.168.08:29:39.26#ibcon#read 6, iclass 20, count 0 2006.168.08:29:39.26#ibcon#end of sib2, iclass 20, count 0 2006.168.08:29:39.26#ibcon#*mode == 0, iclass 20, count 0 2006.168.08:29:39.26#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.168.08:29:39.26#ibcon#[25=USB\r\n] 2006.168.08:29:39.26#ibcon#*before write, iclass 20, count 0 2006.168.08:29:39.26#ibcon#enter sib2, iclass 20, count 0 2006.168.08:29:39.26#ibcon#flushed, iclass 20, count 0 2006.168.08:29:39.26#ibcon#about to write, iclass 20, count 0 2006.168.08:29:39.26#ibcon#wrote, iclass 20, count 0 2006.168.08:29:39.26#ibcon#about to read 3, iclass 20, count 0 2006.168.08:29:39.29#ibcon#read 3, iclass 20, count 0 2006.168.08:29:39.29#ibcon#about to read 4, iclass 20, count 0 2006.168.08:29:39.29#ibcon#read 4, iclass 20, count 0 2006.168.08:29:39.29#ibcon#about to read 5, iclass 20, count 0 2006.168.08:29:39.29#ibcon#read 5, iclass 20, count 0 2006.168.08:29:39.29#ibcon#about to read 6, iclass 20, count 0 2006.168.08:29:39.29#ibcon#read 6, iclass 20, count 0 2006.168.08:29:39.29#ibcon#end of sib2, iclass 20, count 0 2006.168.08:29:39.29#ibcon#*after write, iclass 20, count 0 2006.168.08:29:39.29#ibcon#*before return 0, iclass 20, count 0 2006.168.08:29:39.29#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:29:39.29#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.168.08:29:39.29#ibcon#about to clear, iclass 20 cls_cnt 0 2006.168.08:29:39.29#ibcon#cleared, iclass 20 cls_cnt 0 2006.168.08:29:39.29$vc4f8/valo=5,652.99 2006.168.08:29:39.29#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.168.08:29:39.29#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.168.08:29:39.29#ibcon#ireg 17 cls_cnt 0 2006.168.08:29:39.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:29:39.29#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:29:39.29#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:29:39.29#ibcon#enter wrdev, iclass 22, count 0 2006.168.08:29:39.29#ibcon#first serial, iclass 22, count 0 2006.168.08:29:39.29#ibcon#enter sib2, iclass 22, count 0 2006.168.08:29:39.29#ibcon#flushed, iclass 22, count 0 2006.168.08:29:39.29#ibcon#about to write, iclass 22, count 0 2006.168.08:29:39.29#ibcon#wrote, iclass 22, count 0 2006.168.08:29:39.29#ibcon#about to read 3, iclass 22, count 0 2006.168.08:29:39.31#ibcon#read 3, iclass 22, count 0 2006.168.08:29:39.31#ibcon#about to read 4, iclass 22, count 0 2006.168.08:29:39.31#ibcon#read 4, iclass 22, count 0 2006.168.08:29:39.31#ibcon#about to read 5, iclass 22, count 0 2006.168.08:29:39.31#ibcon#read 5, iclass 22, count 0 2006.168.08:29:39.31#ibcon#about to read 6, iclass 22, count 0 2006.168.08:29:39.31#ibcon#read 6, iclass 22, count 0 2006.168.08:29:39.31#ibcon#end of sib2, iclass 22, count 0 2006.168.08:29:39.31#ibcon#*mode == 0, iclass 22, count 0 2006.168.08:29:39.31#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.168.08:29:39.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.168.08:29:39.31#ibcon#*before write, iclass 22, count 0 2006.168.08:29:39.31#ibcon#enter sib2, iclass 22, count 0 2006.168.08:29:39.31#ibcon#flushed, iclass 22, count 0 2006.168.08:29:39.31#ibcon#about to write, iclass 22, count 0 2006.168.08:29:39.31#ibcon#wrote, iclass 22, count 0 2006.168.08:29:39.31#ibcon#about to read 3, iclass 22, count 0 2006.168.08:29:39.35#ibcon#read 3, iclass 22, count 0 2006.168.08:29:39.35#ibcon#about to read 4, iclass 22, count 0 2006.168.08:29:39.35#ibcon#read 4, iclass 22, count 0 2006.168.08:29:39.35#ibcon#about to read 5, iclass 22, count 0 2006.168.08:29:39.35#ibcon#read 5, iclass 22, count 0 2006.168.08:29:39.35#ibcon#about to read 6, iclass 22, count 0 2006.168.08:29:39.35#ibcon#read 6, iclass 22, count 0 2006.168.08:29:39.35#ibcon#end of sib2, iclass 22, count 0 2006.168.08:29:39.35#ibcon#*after write, iclass 22, count 0 2006.168.08:29:39.35#ibcon#*before return 0, iclass 22, count 0 2006.168.08:29:39.35#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:29:39.35#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:29:39.35#ibcon#about to clear, iclass 22 cls_cnt 0 2006.168.08:29:39.35#ibcon#cleared, iclass 22 cls_cnt 0 2006.168.08:29:39.35$vc4f8/va=5,7 2006.168.08:29:39.35#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.168.08:29:39.35#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.168.08:29:39.35#ibcon#ireg 11 cls_cnt 2 2006.168.08:29:39.35#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:29:39.42#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:29:39.42#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:29:39.42#ibcon#enter wrdev, iclass 24, count 2 2006.168.08:29:39.42#ibcon#first serial, iclass 24, count 2 2006.168.08:29:39.42#ibcon#enter sib2, iclass 24, count 2 2006.168.08:29:39.42#ibcon#flushed, iclass 24, count 2 2006.168.08:29:39.42#ibcon#about to write, iclass 24, count 2 2006.168.08:29:39.42#ibcon#wrote, iclass 24, count 2 2006.168.08:29:39.42#ibcon#about to read 3, iclass 24, count 2 2006.168.08:29:39.44#ibcon#read 3, iclass 24, count 2 2006.168.08:29:39.44#ibcon#about to read 4, iclass 24, count 2 2006.168.08:29:39.44#ibcon#read 4, iclass 24, count 2 2006.168.08:29:39.44#ibcon#about to read 5, iclass 24, count 2 2006.168.08:29:39.44#ibcon#read 5, iclass 24, count 2 2006.168.08:29:39.44#ibcon#about to read 6, iclass 24, count 2 2006.168.08:29:39.44#ibcon#read 6, iclass 24, count 2 2006.168.08:29:39.44#ibcon#end of sib2, iclass 24, count 2 2006.168.08:29:39.44#ibcon#*mode == 0, iclass 24, count 2 2006.168.08:29:39.44#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.168.08:29:39.44#ibcon#[25=AT05-07\r\n] 2006.168.08:29:39.44#ibcon#*before write, iclass 24, count 2 2006.168.08:29:39.44#ibcon#enter sib2, iclass 24, count 2 2006.168.08:29:39.44#ibcon#flushed, iclass 24, count 2 2006.168.08:29:39.44#ibcon#about to write, iclass 24, count 2 2006.168.08:29:39.44#ibcon#wrote, iclass 24, count 2 2006.168.08:29:39.44#ibcon#about to read 3, iclass 24, count 2 2006.168.08:29:39.46#ibcon#read 3, iclass 24, count 2 2006.168.08:29:39.46#ibcon#about to read 4, iclass 24, count 2 2006.168.08:29:39.46#ibcon#read 4, iclass 24, count 2 2006.168.08:29:39.46#ibcon#about to read 5, iclass 24, count 2 2006.168.08:29:39.46#ibcon#read 5, iclass 24, count 2 2006.168.08:29:39.46#ibcon#about to read 6, iclass 24, count 2 2006.168.08:29:39.46#ibcon#read 6, iclass 24, count 2 2006.168.08:29:39.46#ibcon#end of sib2, iclass 24, count 2 2006.168.08:29:39.46#ibcon#*after write, iclass 24, count 2 2006.168.08:29:39.46#ibcon#*before return 0, iclass 24, count 2 2006.168.08:29:39.46#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:29:39.46#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:29:39.46#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.168.08:29:39.46#ibcon#ireg 7 cls_cnt 0 2006.168.08:29:39.46#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:29:39.58#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:29:39.58#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:29:39.58#ibcon#enter wrdev, iclass 24, count 0 2006.168.08:29:39.58#ibcon#first serial, iclass 24, count 0 2006.168.08:29:39.58#ibcon#enter sib2, iclass 24, count 0 2006.168.08:29:39.58#ibcon#flushed, iclass 24, count 0 2006.168.08:29:39.58#ibcon#about to write, iclass 24, count 0 2006.168.08:29:39.58#ibcon#wrote, iclass 24, count 0 2006.168.08:29:39.58#ibcon#about to read 3, iclass 24, count 0 2006.168.08:29:39.60#ibcon#read 3, iclass 24, count 0 2006.168.08:29:39.60#ibcon#about to read 4, iclass 24, count 0 2006.168.08:29:39.60#ibcon#read 4, iclass 24, count 0 2006.168.08:29:39.60#ibcon#about to read 5, iclass 24, count 0 2006.168.08:29:39.60#ibcon#read 5, iclass 24, count 0 2006.168.08:29:39.60#ibcon#about to read 6, iclass 24, count 0 2006.168.08:29:39.60#ibcon#read 6, iclass 24, count 0 2006.168.08:29:39.60#ibcon#end of sib2, iclass 24, count 0 2006.168.08:29:39.60#ibcon#*mode == 0, iclass 24, count 0 2006.168.08:29:39.60#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.168.08:29:39.60#ibcon#[25=USB\r\n] 2006.168.08:29:39.60#ibcon#*before write, iclass 24, count 0 2006.168.08:29:39.60#ibcon#enter sib2, iclass 24, count 0 2006.168.08:29:39.60#ibcon#flushed, iclass 24, count 0 2006.168.08:29:39.60#ibcon#about to write, iclass 24, count 0 2006.168.08:29:39.60#ibcon#wrote, iclass 24, count 0 2006.168.08:29:39.60#ibcon#about to read 3, iclass 24, count 0 2006.168.08:29:39.63#ibcon#read 3, iclass 24, count 0 2006.168.08:29:39.63#ibcon#about to read 4, iclass 24, count 0 2006.168.08:29:39.63#ibcon#read 4, iclass 24, count 0 2006.168.08:29:39.63#ibcon#about to read 5, iclass 24, count 0 2006.168.08:29:39.63#ibcon#read 5, iclass 24, count 0 2006.168.08:29:39.63#ibcon#about to read 6, iclass 24, count 0 2006.168.08:29:39.63#ibcon#read 6, iclass 24, count 0 2006.168.08:29:39.63#ibcon#end of sib2, iclass 24, count 0 2006.168.08:29:39.63#ibcon#*after write, iclass 24, count 0 2006.168.08:29:39.63#ibcon#*before return 0, iclass 24, count 0 2006.168.08:29:39.63#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:29:39.63#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:29:39.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.168.08:29:39.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.168.08:29:39.63$vc4f8/valo=6,772.99 2006.168.08:29:39.63#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.168.08:29:39.63#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.168.08:29:39.63#ibcon#ireg 17 cls_cnt 0 2006.168.08:29:39.63#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:29:39.63#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:29:39.63#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:29:39.63#ibcon#enter wrdev, iclass 26, count 0 2006.168.08:29:39.63#ibcon#first serial, iclass 26, count 0 2006.168.08:29:39.63#ibcon#enter sib2, iclass 26, count 0 2006.168.08:29:39.63#ibcon#flushed, iclass 26, count 0 2006.168.08:29:39.63#ibcon#about to write, iclass 26, count 0 2006.168.08:29:39.63#ibcon#wrote, iclass 26, count 0 2006.168.08:29:39.63#ibcon#about to read 3, iclass 26, count 0 2006.168.08:29:39.65#ibcon#read 3, iclass 26, count 0 2006.168.08:29:39.65#ibcon#about to read 4, iclass 26, count 0 2006.168.08:29:39.65#ibcon#read 4, iclass 26, count 0 2006.168.08:29:39.65#ibcon#about to read 5, iclass 26, count 0 2006.168.08:29:39.65#ibcon#read 5, iclass 26, count 0 2006.168.08:29:39.65#ibcon#about to read 6, iclass 26, count 0 2006.168.08:29:39.65#ibcon#read 6, iclass 26, count 0 2006.168.08:29:39.65#ibcon#end of sib2, iclass 26, count 0 2006.168.08:29:39.65#ibcon#*mode == 0, iclass 26, count 0 2006.168.08:29:39.65#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.168.08:29:39.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.168.08:29:39.65#ibcon#*before write, iclass 26, count 0 2006.168.08:29:39.65#ibcon#enter sib2, iclass 26, count 0 2006.168.08:29:39.65#ibcon#flushed, iclass 26, count 0 2006.168.08:29:39.65#ibcon#about to write, iclass 26, count 0 2006.168.08:29:39.65#ibcon#wrote, iclass 26, count 0 2006.168.08:29:39.65#ibcon#about to read 3, iclass 26, count 0 2006.168.08:29:39.69#ibcon#read 3, iclass 26, count 0 2006.168.08:29:39.69#ibcon#about to read 4, iclass 26, count 0 2006.168.08:29:39.69#ibcon#read 4, iclass 26, count 0 2006.168.08:29:39.69#ibcon#about to read 5, iclass 26, count 0 2006.168.08:29:39.69#ibcon#read 5, iclass 26, count 0 2006.168.08:29:39.69#ibcon#about to read 6, iclass 26, count 0 2006.168.08:29:39.69#ibcon#read 6, iclass 26, count 0 2006.168.08:29:39.69#ibcon#end of sib2, iclass 26, count 0 2006.168.08:29:39.69#ibcon#*after write, iclass 26, count 0 2006.168.08:29:39.69#ibcon#*before return 0, iclass 26, count 0 2006.168.08:29:39.69#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:29:39.69#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:29:39.69#ibcon#about to clear, iclass 26 cls_cnt 0 2006.168.08:29:39.69#ibcon#cleared, iclass 26 cls_cnt 0 2006.168.08:29:39.69$vc4f8/va=6,6 2006.168.08:29:39.69#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.168.08:29:39.69#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.168.08:29:39.69#ibcon#ireg 11 cls_cnt 2 2006.168.08:29:39.69#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:29:39.76#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:29:39.76#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:29:39.76#ibcon#enter wrdev, iclass 28, count 2 2006.168.08:29:39.76#ibcon#first serial, iclass 28, count 2 2006.168.08:29:39.76#ibcon#enter sib2, iclass 28, count 2 2006.168.08:29:39.76#ibcon#flushed, iclass 28, count 2 2006.168.08:29:39.76#ibcon#about to write, iclass 28, count 2 2006.168.08:29:39.76#ibcon#wrote, iclass 28, count 2 2006.168.08:29:39.76#ibcon#about to read 3, iclass 28, count 2 2006.168.08:29:39.78#ibcon#read 3, iclass 28, count 2 2006.168.08:29:39.78#ibcon#about to read 4, iclass 28, count 2 2006.168.08:29:39.78#ibcon#read 4, iclass 28, count 2 2006.168.08:29:39.78#ibcon#about to read 5, iclass 28, count 2 2006.168.08:29:39.78#ibcon#read 5, iclass 28, count 2 2006.168.08:29:39.78#ibcon#about to read 6, iclass 28, count 2 2006.168.08:29:39.78#ibcon#read 6, iclass 28, count 2 2006.168.08:29:39.78#ibcon#end of sib2, iclass 28, count 2 2006.168.08:29:39.78#ibcon#*mode == 0, iclass 28, count 2 2006.168.08:29:39.78#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.168.08:29:39.78#ibcon#[25=AT06-06\r\n] 2006.168.08:29:39.78#ibcon#*before write, iclass 28, count 2 2006.168.08:29:39.78#ibcon#enter sib2, iclass 28, count 2 2006.168.08:29:39.78#ibcon#flushed, iclass 28, count 2 2006.168.08:29:39.78#ibcon#about to write, iclass 28, count 2 2006.168.08:29:39.78#ibcon#wrote, iclass 28, count 2 2006.168.08:29:39.78#ibcon#about to read 3, iclass 28, count 2 2006.168.08:29:39.80#ibcon#read 3, iclass 28, count 2 2006.168.08:29:39.80#ibcon#about to read 4, iclass 28, count 2 2006.168.08:29:39.80#ibcon#read 4, iclass 28, count 2 2006.168.08:29:39.80#ibcon#about to read 5, iclass 28, count 2 2006.168.08:29:39.80#ibcon#read 5, iclass 28, count 2 2006.168.08:29:39.80#ibcon#about to read 6, iclass 28, count 2 2006.168.08:29:39.80#ibcon#read 6, iclass 28, count 2 2006.168.08:29:39.80#ibcon#end of sib2, iclass 28, count 2 2006.168.08:29:39.80#ibcon#*after write, iclass 28, count 2 2006.168.08:29:39.80#ibcon#*before return 0, iclass 28, count 2 2006.168.08:29:39.80#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:29:39.80#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:29:39.80#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.168.08:29:39.80#ibcon#ireg 7 cls_cnt 0 2006.168.08:29:39.80#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:29:39.92#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:29:39.92#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:29:39.92#ibcon#enter wrdev, iclass 28, count 0 2006.168.08:29:39.92#ibcon#first serial, iclass 28, count 0 2006.168.08:29:39.92#ibcon#enter sib2, iclass 28, count 0 2006.168.08:29:39.92#ibcon#flushed, iclass 28, count 0 2006.168.08:29:39.92#ibcon#about to write, iclass 28, count 0 2006.168.08:29:39.92#ibcon#wrote, iclass 28, count 0 2006.168.08:29:39.92#ibcon#about to read 3, iclass 28, count 0 2006.168.08:29:39.94#ibcon#read 3, iclass 28, count 0 2006.168.08:29:39.94#ibcon#about to read 4, iclass 28, count 0 2006.168.08:29:39.94#ibcon#read 4, iclass 28, count 0 2006.168.08:29:39.94#ibcon#about to read 5, iclass 28, count 0 2006.168.08:29:39.94#ibcon#read 5, iclass 28, count 0 2006.168.08:29:39.94#ibcon#about to read 6, iclass 28, count 0 2006.168.08:29:39.94#ibcon#read 6, iclass 28, count 0 2006.168.08:29:39.94#ibcon#end of sib2, iclass 28, count 0 2006.168.08:29:39.94#ibcon#*mode == 0, iclass 28, count 0 2006.168.08:29:39.94#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.168.08:29:39.94#ibcon#[25=USB\r\n] 2006.168.08:29:39.94#ibcon#*before write, iclass 28, count 0 2006.168.08:29:39.94#ibcon#enter sib2, iclass 28, count 0 2006.168.08:29:39.94#ibcon#flushed, iclass 28, count 0 2006.168.08:29:39.94#ibcon#about to write, iclass 28, count 0 2006.168.08:29:39.94#ibcon#wrote, iclass 28, count 0 2006.168.08:29:39.94#ibcon#about to read 3, iclass 28, count 0 2006.168.08:29:39.97#ibcon#read 3, iclass 28, count 0 2006.168.08:29:39.97#ibcon#about to read 4, iclass 28, count 0 2006.168.08:29:39.97#ibcon#read 4, iclass 28, count 0 2006.168.08:29:39.97#ibcon#about to read 5, iclass 28, count 0 2006.168.08:29:39.97#ibcon#read 5, iclass 28, count 0 2006.168.08:29:39.97#ibcon#about to read 6, iclass 28, count 0 2006.168.08:29:39.97#ibcon#read 6, iclass 28, count 0 2006.168.08:29:39.97#ibcon#end of sib2, iclass 28, count 0 2006.168.08:29:39.97#ibcon#*after write, iclass 28, count 0 2006.168.08:29:39.97#ibcon#*before return 0, iclass 28, count 0 2006.168.08:29:39.97#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:29:39.97#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:29:39.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.168.08:29:39.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.168.08:29:39.97$vc4f8/valo=7,832.99 2006.168.08:29:39.97#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.168.08:29:39.97#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.168.08:29:39.97#ibcon#ireg 17 cls_cnt 0 2006.168.08:29:39.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:29:39.97#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:29:39.97#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:29:39.97#ibcon#enter wrdev, iclass 30, count 0 2006.168.08:29:39.97#ibcon#first serial, iclass 30, count 0 2006.168.08:29:39.97#ibcon#enter sib2, iclass 30, count 0 2006.168.08:29:39.97#ibcon#flushed, iclass 30, count 0 2006.168.08:29:39.97#ibcon#about to write, iclass 30, count 0 2006.168.08:29:39.97#ibcon#wrote, iclass 30, count 0 2006.168.08:29:39.97#ibcon#about to read 3, iclass 30, count 0 2006.168.08:29:39.99#ibcon#read 3, iclass 30, count 0 2006.168.08:29:39.99#ibcon#about to read 4, iclass 30, count 0 2006.168.08:29:39.99#ibcon#read 4, iclass 30, count 0 2006.168.08:29:39.99#ibcon#about to read 5, iclass 30, count 0 2006.168.08:29:39.99#ibcon#read 5, iclass 30, count 0 2006.168.08:29:39.99#ibcon#about to read 6, iclass 30, count 0 2006.168.08:29:39.99#ibcon#read 6, iclass 30, count 0 2006.168.08:29:39.99#ibcon#end of sib2, iclass 30, count 0 2006.168.08:29:39.99#ibcon#*mode == 0, iclass 30, count 0 2006.168.08:29:39.99#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.168.08:29:39.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.168.08:29:39.99#ibcon#*before write, iclass 30, count 0 2006.168.08:29:39.99#ibcon#enter sib2, iclass 30, count 0 2006.168.08:29:39.99#ibcon#flushed, iclass 30, count 0 2006.168.08:29:39.99#ibcon#about to write, iclass 30, count 0 2006.168.08:29:39.99#ibcon#wrote, iclass 30, count 0 2006.168.08:29:39.99#ibcon#about to read 3, iclass 30, count 0 2006.168.08:29:40.03#ibcon#read 3, iclass 30, count 0 2006.168.08:29:40.03#ibcon#about to read 4, iclass 30, count 0 2006.168.08:29:40.03#ibcon#read 4, iclass 30, count 0 2006.168.08:29:40.03#ibcon#about to read 5, iclass 30, count 0 2006.168.08:29:40.03#ibcon#read 5, iclass 30, count 0 2006.168.08:29:40.03#ibcon#about to read 6, iclass 30, count 0 2006.168.08:29:40.03#ibcon#read 6, iclass 30, count 0 2006.168.08:29:40.03#ibcon#end of sib2, iclass 30, count 0 2006.168.08:29:40.03#ibcon#*after write, iclass 30, count 0 2006.168.08:29:40.03#ibcon#*before return 0, iclass 30, count 0 2006.168.08:29:40.03#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:29:40.03#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:29:40.03#ibcon#about to clear, iclass 30 cls_cnt 0 2006.168.08:29:40.03#ibcon#cleared, iclass 30 cls_cnt 0 2006.168.08:29:40.03$vc4f8/va=7,6 2006.168.08:29:40.03#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.168.08:29:40.03#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.168.08:29:40.03#ibcon#ireg 11 cls_cnt 2 2006.168.08:29:40.03#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:29:40.10#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:29:40.10#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:29:40.10#ibcon#enter wrdev, iclass 32, count 2 2006.168.08:29:40.10#ibcon#first serial, iclass 32, count 2 2006.168.08:29:40.10#ibcon#enter sib2, iclass 32, count 2 2006.168.08:29:40.10#ibcon#flushed, iclass 32, count 2 2006.168.08:29:40.10#ibcon#about to write, iclass 32, count 2 2006.168.08:29:40.10#ibcon#wrote, iclass 32, count 2 2006.168.08:29:40.10#ibcon#about to read 3, iclass 32, count 2 2006.168.08:29:40.12#ibcon#read 3, iclass 32, count 2 2006.168.08:29:40.12#ibcon#about to read 4, iclass 32, count 2 2006.168.08:29:40.12#ibcon#read 4, iclass 32, count 2 2006.168.08:29:40.12#ibcon#about to read 5, iclass 32, count 2 2006.168.08:29:40.12#ibcon#read 5, iclass 32, count 2 2006.168.08:29:40.12#ibcon#about to read 6, iclass 32, count 2 2006.168.08:29:40.12#ibcon#read 6, iclass 32, count 2 2006.168.08:29:40.12#ibcon#end of sib2, iclass 32, count 2 2006.168.08:29:40.12#ibcon#*mode == 0, iclass 32, count 2 2006.168.08:29:40.12#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.168.08:29:40.12#ibcon#[25=AT07-06\r\n] 2006.168.08:29:40.12#ibcon#*before write, iclass 32, count 2 2006.168.08:29:40.12#ibcon#enter sib2, iclass 32, count 2 2006.168.08:29:40.12#ibcon#flushed, iclass 32, count 2 2006.168.08:29:40.12#ibcon#about to write, iclass 32, count 2 2006.168.08:29:40.12#ibcon#wrote, iclass 32, count 2 2006.168.08:29:40.12#ibcon#about to read 3, iclass 32, count 2 2006.168.08:29:40.14#ibcon#read 3, iclass 32, count 2 2006.168.08:29:40.14#ibcon#about to read 4, iclass 32, count 2 2006.168.08:29:40.14#ibcon#read 4, iclass 32, count 2 2006.168.08:29:40.14#ibcon#about to read 5, iclass 32, count 2 2006.168.08:29:40.14#ibcon#read 5, iclass 32, count 2 2006.168.08:29:40.14#ibcon#about to read 6, iclass 32, count 2 2006.168.08:29:40.14#ibcon#read 6, iclass 32, count 2 2006.168.08:29:40.14#ibcon#end of sib2, iclass 32, count 2 2006.168.08:29:40.14#ibcon#*after write, iclass 32, count 2 2006.168.08:29:40.14#ibcon#*before return 0, iclass 32, count 2 2006.168.08:29:40.14#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:29:40.14#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.168.08:29:40.14#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.168.08:29:40.14#ibcon#ireg 7 cls_cnt 0 2006.168.08:29:40.14#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:29:40.26#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:29:40.26#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:29:40.26#ibcon#enter wrdev, iclass 32, count 0 2006.168.08:29:40.26#ibcon#first serial, iclass 32, count 0 2006.168.08:29:40.26#ibcon#enter sib2, iclass 32, count 0 2006.168.08:29:40.26#ibcon#flushed, iclass 32, count 0 2006.168.08:29:40.26#ibcon#about to write, iclass 32, count 0 2006.168.08:29:40.26#ibcon#wrote, iclass 32, count 0 2006.168.08:29:40.26#ibcon#about to read 3, iclass 32, count 0 2006.168.08:29:40.28#ibcon#read 3, iclass 32, count 0 2006.168.08:29:40.28#ibcon#about to read 4, iclass 32, count 0 2006.168.08:29:40.28#ibcon#read 4, iclass 32, count 0 2006.168.08:29:40.28#ibcon#about to read 5, iclass 32, count 0 2006.168.08:29:40.28#ibcon#read 5, iclass 32, count 0 2006.168.08:29:40.28#ibcon#about to read 6, iclass 32, count 0 2006.168.08:29:40.28#ibcon#read 6, iclass 32, count 0 2006.168.08:29:40.28#ibcon#end of sib2, iclass 32, count 0 2006.168.08:29:40.28#ibcon#*mode == 0, iclass 32, count 0 2006.168.08:29:40.28#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.168.08:29:40.28#ibcon#[25=USB\r\n] 2006.168.08:29:40.28#ibcon#*before write, iclass 32, count 0 2006.168.08:29:40.28#ibcon#enter sib2, iclass 32, count 0 2006.168.08:29:40.28#ibcon#flushed, iclass 32, count 0 2006.168.08:29:40.28#ibcon#about to write, iclass 32, count 0 2006.168.08:29:40.28#ibcon#wrote, iclass 32, count 0 2006.168.08:29:40.28#ibcon#about to read 3, iclass 32, count 0 2006.168.08:29:40.31#ibcon#read 3, iclass 32, count 0 2006.168.08:29:40.31#ibcon#about to read 4, iclass 32, count 0 2006.168.08:29:40.31#ibcon#read 4, iclass 32, count 0 2006.168.08:29:40.31#ibcon#about to read 5, iclass 32, count 0 2006.168.08:29:40.31#ibcon#read 5, iclass 32, count 0 2006.168.08:29:40.31#ibcon#about to read 6, iclass 32, count 0 2006.168.08:29:40.31#ibcon#read 6, iclass 32, count 0 2006.168.08:29:40.31#ibcon#end of sib2, iclass 32, count 0 2006.168.08:29:40.31#ibcon#*after write, iclass 32, count 0 2006.168.08:29:40.31#ibcon#*before return 0, iclass 32, count 0 2006.168.08:29:40.31#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:29:40.31#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.168.08:29:40.31#ibcon#about to clear, iclass 32 cls_cnt 0 2006.168.08:29:40.31#ibcon#cleared, iclass 32 cls_cnt 0 2006.168.08:29:40.31$vc4f8/valo=8,852.99 2006.168.08:29:40.31#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.168.08:29:40.31#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.168.08:29:40.31#ibcon#ireg 17 cls_cnt 0 2006.168.08:29:40.31#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:29:40.31#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:29:40.31#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:29:40.31#ibcon#enter wrdev, iclass 34, count 0 2006.168.08:29:40.31#ibcon#first serial, iclass 34, count 0 2006.168.08:29:40.31#ibcon#enter sib2, iclass 34, count 0 2006.168.08:29:40.31#ibcon#flushed, iclass 34, count 0 2006.168.08:29:40.31#ibcon#about to write, iclass 34, count 0 2006.168.08:29:40.31#ibcon#wrote, iclass 34, count 0 2006.168.08:29:40.31#ibcon#about to read 3, iclass 34, count 0 2006.168.08:29:40.33#ibcon#read 3, iclass 34, count 0 2006.168.08:29:40.33#ibcon#about to read 4, iclass 34, count 0 2006.168.08:29:40.33#ibcon#read 4, iclass 34, count 0 2006.168.08:29:40.33#ibcon#about to read 5, iclass 34, count 0 2006.168.08:29:40.33#ibcon#read 5, iclass 34, count 0 2006.168.08:29:40.33#ibcon#about to read 6, iclass 34, count 0 2006.168.08:29:40.33#ibcon#read 6, iclass 34, count 0 2006.168.08:29:40.33#ibcon#end of sib2, iclass 34, count 0 2006.168.08:29:40.33#ibcon#*mode == 0, iclass 34, count 0 2006.168.08:29:40.33#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.168.08:29:40.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.168.08:29:40.33#ibcon#*before write, iclass 34, count 0 2006.168.08:29:40.33#ibcon#enter sib2, iclass 34, count 0 2006.168.08:29:40.33#ibcon#flushed, iclass 34, count 0 2006.168.08:29:40.33#ibcon#about to write, iclass 34, count 0 2006.168.08:29:40.33#ibcon#wrote, iclass 34, count 0 2006.168.08:29:40.33#ibcon#about to read 3, iclass 34, count 0 2006.168.08:29:40.37#ibcon#read 3, iclass 34, count 0 2006.168.08:29:40.37#ibcon#about to read 4, iclass 34, count 0 2006.168.08:29:40.37#ibcon#read 4, iclass 34, count 0 2006.168.08:29:40.37#ibcon#about to read 5, iclass 34, count 0 2006.168.08:29:40.37#ibcon#read 5, iclass 34, count 0 2006.168.08:29:40.37#ibcon#about to read 6, iclass 34, count 0 2006.168.08:29:40.37#ibcon#read 6, iclass 34, count 0 2006.168.08:29:40.37#ibcon#end of sib2, iclass 34, count 0 2006.168.08:29:40.37#ibcon#*after write, iclass 34, count 0 2006.168.08:29:40.37#ibcon#*before return 0, iclass 34, count 0 2006.168.08:29:40.37#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:29:40.37#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.168.08:29:40.37#ibcon#about to clear, iclass 34 cls_cnt 0 2006.168.08:29:40.37#ibcon#cleared, iclass 34 cls_cnt 0 2006.168.08:29:40.37$vc4f8/va=8,7 2006.168.08:29:40.37#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.168.08:29:40.37#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.168.08:29:40.37#ibcon#ireg 11 cls_cnt 2 2006.168.08:29:40.37#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:29:40.44#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:29:40.44#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:29:40.44#ibcon#enter wrdev, iclass 36, count 2 2006.168.08:29:40.44#ibcon#first serial, iclass 36, count 2 2006.168.08:29:40.44#ibcon#enter sib2, iclass 36, count 2 2006.168.08:29:40.44#ibcon#flushed, iclass 36, count 2 2006.168.08:29:40.44#ibcon#about to write, iclass 36, count 2 2006.168.08:29:40.44#ibcon#wrote, iclass 36, count 2 2006.168.08:29:40.44#ibcon#about to read 3, iclass 36, count 2 2006.168.08:29:40.46#ibcon#read 3, iclass 36, count 2 2006.168.08:29:40.46#ibcon#about to read 4, iclass 36, count 2 2006.168.08:29:40.46#ibcon#read 4, iclass 36, count 2 2006.168.08:29:40.46#ibcon#about to read 5, iclass 36, count 2 2006.168.08:29:40.46#ibcon#read 5, iclass 36, count 2 2006.168.08:29:40.46#ibcon#about to read 6, iclass 36, count 2 2006.168.08:29:40.46#ibcon#read 6, iclass 36, count 2 2006.168.08:29:40.46#ibcon#end of sib2, iclass 36, count 2 2006.168.08:29:40.46#ibcon#*mode == 0, iclass 36, count 2 2006.168.08:29:40.46#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.168.08:29:40.46#ibcon#[25=AT08-07\r\n] 2006.168.08:29:40.46#ibcon#*before write, iclass 36, count 2 2006.168.08:29:40.46#ibcon#enter sib2, iclass 36, count 2 2006.168.08:29:40.46#ibcon#flushed, iclass 36, count 2 2006.168.08:29:40.46#ibcon#about to write, iclass 36, count 2 2006.168.08:29:40.46#ibcon#wrote, iclass 36, count 2 2006.168.08:29:40.46#ibcon#about to read 3, iclass 36, count 2 2006.168.08:29:40.48#ibcon#read 3, iclass 36, count 2 2006.168.08:29:40.48#ibcon#about to read 4, iclass 36, count 2 2006.168.08:29:40.48#ibcon#read 4, iclass 36, count 2 2006.168.08:29:40.48#ibcon#about to read 5, iclass 36, count 2 2006.168.08:29:40.48#ibcon#read 5, iclass 36, count 2 2006.168.08:29:40.48#ibcon#about to read 6, iclass 36, count 2 2006.168.08:29:40.48#ibcon#read 6, iclass 36, count 2 2006.168.08:29:40.48#ibcon#end of sib2, iclass 36, count 2 2006.168.08:29:40.48#ibcon#*after write, iclass 36, count 2 2006.168.08:29:40.48#ibcon#*before return 0, iclass 36, count 2 2006.168.08:29:40.48#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:29:40.48#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.168.08:29:40.48#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.168.08:29:40.48#ibcon#ireg 7 cls_cnt 0 2006.168.08:29:40.48#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:29:40.60#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:29:40.60#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:29:40.60#ibcon#enter wrdev, iclass 36, count 0 2006.168.08:29:40.60#ibcon#first serial, iclass 36, count 0 2006.168.08:29:40.60#ibcon#enter sib2, iclass 36, count 0 2006.168.08:29:40.60#ibcon#flushed, iclass 36, count 0 2006.168.08:29:40.60#ibcon#about to write, iclass 36, count 0 2006.168.08:29:40.60#ibcon#wrote, iclass 36, count 0 2006.168.08:29:40.60#ibcon#about to read 3, iclass 36, count 0 2006.168.08:29:40.62#ibcon#read 3, iclass 36, count 0 2006.168.08:29:40.62#ibcon#about to read 4, iclass 36, count 0 2006.168.08:29:40.62#ibcon#read 4, iclass 36, count 0 2006.168.08:29:40.62#ibcon#about to read 5, iclass 36, count 0 2006.168.08:29:40.62#ibcon#read 5, iclass 36, count 0 2006.168.08:29:40.62#ibcon#about to read 6, iclass 36, count 0 2006.168.08:29:40.62#ibcon#read 6, iclass 36, count 0 2006.168.08:29:40.62#ibcon#end of sib2, iclass 36, count 0 2006.168.08:29:40.62#ibcon#*mode == 0, iclass 36, count 0 2006.168.08:29:40.62#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.168.08:29:40.62#ibcon#[25=USB\r\n] 2006.168.08:29:40.62#ibcon#*before write, iclass 36, count 0 2006.168.08:29:40.62#ibcon#enter sib2, iclass 36, count 0 2006.168.08:29:40.62#ibcon#flushed, iclass 36, count 0 2006.168.08:29:40.62#ibcon#about to write, iclass 36, count 0 2006.168.08:29:40.62#ibcon#wrote, iclass 36, count 0 2006.168.08:29:40.62#ibcon#about to read 3, iclass 36, count 0 2006.168.08:29:40.65#ibcon#read 3, iclass 36, count 0 2006.168.08:29:40.65#ibcon#about to read 4, iclass 36, count 0 2006.168.08:29:40.65#ibcon#read 4, iclass 36, count 0 2006.168.08:29:40.65#ibcon#about to read 5, iclass 36, count 0 2006.168.08:29:40.65#ibcon#read 5, iclass 36, count 0 2006.168.08:29:40.65#ibcon#about to read 6, iclass 36, count 0 2006.168.08:29:40.65#ibcon#read 6, iclass 36, count 0 2006.168.08:29:40.65#ibcon#end of sib2, iclass 36, count 0 2006.168.08:29:40.65#ibcon#*after write, iclass 36, count 0 2006.168.08:29:40.65#ibcon#*before return 0, iclass 36, count 0 2006.168.08:29:40.65#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:29:40.65#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.168.08:29:40.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.168.08:29:40.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.168.08:29:40.65$vc4f8/vblo=1,632.99 2006.168.08:29:40.65#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.168.08:29:40.65#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.168.08:29:40.65#ibcon#ireg 17 cls_cnt 0 2006.168.08:29:40.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:29:40.65#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:29:40.65#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:29:40.65#ibcon#enter wrdev, iclass 38, count 0 2006.168.08:29:40.65#ibcon#first serial, iclass 38, count 0 2006.168.08:29:40.65#ibcon#enter sib2, iclass 38, count 0 2006.168.08:29:40.65#ibcon#flushed, iclass 38, count 0 2006.168.08:29:40.65#ibcon#about to write, iclass 38, count 0 2006.168.08:29:40.65#ibcon#wrote, iclass 38, count 0 2006.168.08:29:40.65#ibcon#about to read 3, iclass 38, count 0 2006.168.08:29:40.67#ibcon#read 3, iclass 38, count 0 2006.168.08:29:40.67#ibcon#about to read 4, iclass 38, count 0 2006.168.08:29:40.67#ibcon#read 4, iclass 38, count 0 2006.168.08:29:40.67#ibcon#about to read 5, iclass 38, count 0 2006.168.08:29:40.67#ibcon#read 5, iclass 38, count 0 2006.168.08:29:40.67#ibcon#about to read 6, iclass 38, count 0 2006.168.08:29:40.67#ibcon#read 6, iclass 38, count 0 2006.168.08:29:40.67#ibcon#end of sib2, iclass 38, count 0 2006.168.08:29:40.67#ibcon#*mode == 0, iclass 38, count 0 2006.168.08:29:40.67#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.168.08:29:40.67#ibcon#[28=FRQ=01,632.99\r\n] 2006.168.08:29:40.67#ibcon#*before write, iclass 38, count 0 2006.168.08:29:40.67#ibcon#enter sib2, iclass 38, count 0 2006.168.08:29:40.67#ibcon#flushed, iclass 38, count 0 2006.168.08:29:40.67#ibcon#about to write, iclass 38, count 0 2006.168.08:29:40.67#ibcon#wrote, iclass 38, count 0 2006.168.08:29:40.67#ibcon#about to read 3, iclass 38, count 0 2006.168.08:29:40.71#ibcon#read 3, iclass 38, count 0 2006.168.08:29:40.71#ibcon#about to read 4, iclass 38, count 0 2006.168.08:29:40.71#ibcon#read 4, iclass 38, count 0 2006.168.08:29:40.71#ibcon#about to read 5, iclass 38, count 0 2006.168.08:29:40.71#ibcon#read 5, iclass 38, count 0 2006.168.08:29:40.71#ibcon#about to read 6, iclass 38, count 0 2006.168.08:29:40.71#ibcon#read 6, iclass 38, count 0 2006.168.08:29:40.71#ibcon#end of sib2, iclass 38, count 0 2006.168.08:29:40.71#ibcon#*after write, iclass 38, count 0 2006.168.08:29:40.71#ibcon#*before return 0, iclass 38, count 0 2006.168.08:29:40.71#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:29:40.71#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.168.08:29:40.71#ibcon#about to clear, iclass 38 cls_cnt 0 2006.168.08:29:40.71#ibcon#cleared, iclass 38 cls_cnt 0 2006.168.08:29:40.71$vc4f8/vb=1,4 2006.168.08:29:40.71#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.168.08:29:40.71#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.168.08:29:40.71#ibcon#ireg 11 cls_cnt 2 2006.168.08:29:40.71#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:29:40.71#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:29:40.71#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:29:40.71#ibcon#enter wrdev, iclass 40, count 2 2006.168.08:29:40.71#ibcon#first serial, iclass 40, count 2 2006.168.08:29:40.71#ibcon#enter sib2, iclass 40, count 2 2006.168.08:29:40.71#ibcon#flushed, iclass 40, count 2 2006.168.08:29:40.71#ibcon#about to write, iclass 40, count 2 2006.168.08:29:40.71#ibcon#wrote, iclass 40, count 2 2006.168.08:29:40.71#ibcon#about to read 3, iclass 40, count 2 2006.168.08:29:40.73#ibcon#read 3, iclass 40, count 2 2006.168.08:29:40.73#ibcon#about to read 4, iclass 40, count 2 2006.168.08:29:40.73#ibcon#read 4, iclass 40, count 2 2006.168.08:29:40.73#ibcon#about to read 5, iclass 40, count 2 2006.168.08:29:40.73#ibcon#read 5, iclass 40, count 2 2006.168.08:29:40.73#ibcon#about to read 6, iclass 40, count 2 2006.168.08:29:40.73#ibcon#read 6, iclass 40, count 2 2006.168.08:29:40.73#ibcon#end of sib2, iclass 40, count 2 2006.168.08:29:40.73#ibcon#*mode == 0, iclass 40, count 2 2006.168.08:29:40.73#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.168.08:29:40.73#ibcon#[27=AT01-04\r\n] 2006.168.08:29:40.73#ibcon#*before write, iclass 40, count 2 2006.168.08:29:40.73#ibcon#enter sib2, iclass 40, count 2 2006.168.08:29:40.73#ibcon#flushed, iclass 40, count 2 2006.168.08:29:40.73#ibcon#about to write, iclass 40, count 2 2006.168.08:29:40.73#ibcon#wrote, iclass 40, count 2 2006.168.08:29:40.73#ibcon#about to read 3, iclass 40, count 2 2006.168.08:29:40.76#ibcon#read 3, iclass 40, count 2 2006.168.08:29:40.76#ibcon#about to read 4, iclass 40, count 2 2006.168.08:29:40.76#ibcon#read 4, iclass 40, count 2 2006.168.08:29:40.76#ibcon#about to read 5, iclass 40, count 2 2006.168.08:29:40.76#ibcon#read 5, iclass 40, count 2 2006.168.08:29:40.76#ibcon#about to read 6, iclass 40, count 2 2006.168.08:29:40.76#ibcon#read 6, iclass 40, count 2 2006.168.08:29:40.76#ibcon#end of sib2, iclass 40, count 2 2006.168.08:29:40.76#ibcon#*after write, iclass 40, count 2 2006.168.08:29:40.76#ibcon#*before return 0, iclass 40, count 2 2006.168.08:29:40.76#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:29:40.76#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.168.08:29:40.76#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.168.08:29:40.76#ibcon#ireg 7 cls_cnt 0 2006.168.08:29:40.76#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:29:40.88#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:29:40.88#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:29:40.88#ibcon#enter wrdev, iclass 40, count 0 2006.168.08:29:40.88#ibcon#first serial, iclass 40, count 0 2006.168.08:29:40.88#ibcon#enter sib2, iclass 40, count 0 2006.168.08:29:40.88#ibcon#flushed, iclass 40, count 0 2006.168.08:29:40.88#ibcon#about to write, iclass 40, count 0 2006.168.08:29:40.88#ibcon#wrote, iclass 40, count 0 2006.168.08:29:40.88#ibcon#about to read 3, iclass 40, count 0 2006.168.08:29:40.90#ibcon#read 3, iclass 40, count 0 2006.168.08:29:40.90#ibcon#about to read 4, iclass 40, count 0 2006.168.08:29:40.90#ibcon#read 4, iclass 40, count 0 2006.168.08:29:40.90#ibcon#about to read 5, iclass 40, count 0 2006.168.08:29:40.90#ibcon#read 5, iclass 40, count 0 2006.168.08:29:40.90#ibcon#about to read 6, iclass 40, count 0 2006.168.08:29:40.90#ibcon#read 6, iclass 40, count 0 2006.168.08:29:40.90#ibcon#end of sib2, iclass 40, count 0 2006.168.08:29:40.90#ibcon#*mode == 0, iclass 40, count 0 2006.168.08:29:40.90#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.168.08:29:40.90#ibcon#[27=USB\r\n] 2006.168.08:29:40.90#ibcon#*before write, iclass 40, count 0 2006.168.08:29:40.90#ibcon#enter sib2, iclass 40, count 0 2006.168.08:29:40.90#ibcon#flushed, iclass 40, count 0 2006.168.08:29:40.90#ibcon#about to write, iclass 40, count 0 2006.168.08:29:40.90#ibcon#wrote, iclass 40, count 0 2006.168.08:29:40.90#ibcon#about to read 3, iclass 40, count 0 2006.168.08:29:40.93#ibcon#read 3, iclass 40, count 0 2006.168.08:29:40.93#ibcon#about to read 4, iclass 40, count 0 2006.168.08:29:40.93#ibcon#read 4, iclass 40, count 0 2006.168.08:29:40.93#ibcon#about to read 5, iclass 40, count 0 2006.168.08:29:40.93#ibcon#read 5, iclass 40, count 0 2006.168.08:29:40.93#ibcon#about to read 6, iclass 40, count 0 2006.168.08:29:40.93#ibcon#read 6, iclass 40, count 0 2006.168.08:29:40.93#ibcon#end of sib2, iclass 40, count 0 2006.168.08:29:40.93#ibcon#*after write, iclass 40, count 0 2006.168.08:29:40.93#ibcon#*before return 0, iclass 40, count 0 2006.168.08:29:40.93#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:29:40.93#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.168.08:29:40.93#ibcon#about to clear, iclass 40 cls_cnt 0 2006.168.08:29:40.93#ibcon#cleared, iclass 40 cls_cnt 0 2006.168.08:29:40.93$vc4f8/vblo=2,640.99 2006.168.08:29:40.93#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.168.08:29:40.93#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.168.08:29:40.93#ibcon#ireg 17 cls_cnt 0 2006.168.08:29:40.93#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:29:40.93#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:29:40.93#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:29:40.93#ibcon#enter wrdev, iclass 4, count 0 2006.168.08:29:40.93#ibcon#first serial, iclass 4, count 0 2006.168.08:29:40.93#ibcon#enter sib2, iclass 4, count 0 2006.168.08:29:40.93#ibcon#flushed, iclass 4, count 0 2006.168.08:29:40.93#ibcon#about to write, iclass 4, count 0 2006.168.08:29:40.93#ibcon#wrote, iclass 4, count 0 2006.168.08:29:40.93#ibcon#about to read 3, iclass 4, count 0 2006.168.08:29:40.95#ibcon#read 3, iclass 4, count 0 2006.168.08:29:40.95#ibcon#about to read 4, iclass 4, count 0 2006.168.08:29:40.95#ibcon#read 4, iclass 4, count 0 2006.168.08:29:40.95#ibcon#about to read 5, iclass 4, count 0 2006.168.08:29:40.95#ibcon#read 5, iclass 4, count 0 2006.168.08:29:40.95#ibcon#about to read 6, iclass 4, count 0 2006.168.08:29:40.95#ibcon#read 6, iclass 4, count 0 2006.168.08:29:40.95#ibcon#end of sib2, iclass 4, count 0 2006.168.08:29:40.95#ibcon#*mode == 0, iclass 4, count 0 2006.168.08:29:40.95#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.168.08:29:40.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.168.08:29:40.95#ibcon#*before write, iclass 4, count 0 2006.168.08:29:40.95#ibcon#enter sib2, iclass 4, count 0 2006.168.08:29:40.95#ibcon#flushed, iclass 4, count 0 2006.168.08:29:40.95#ibcon#about to write, iclass 4, count 0 2006.168.08:29:40.95#ibcon#wrote, iclass 4, count 0 2006.168.08:29:40.95#ibcon#about to read 3, iclass 4, count 0 2006.168.08:29:40.99#ibcon#read 3, iclass 4, count 0 2006.168.08:29:40.99#ibcon#about to read 4, iclass 4, count 0 2006.168.08:29:40.99#ibcon#read 4, iclass 4, count 0 2006.168.08:29:40.99#ibcon#about to read 5, iclass 4, count 0 2006.168.08:29:40.99#ibcon#read 5, iclass 4, count 0 2006.168.08:29:40.99#ibcon#about to read 6, iclass 4, count 0 2006.168.08:29:40.99#ibcon#read 6, iclass 4, count 0 2006.168.08:29:40.99#ibcon#end of sib2, iclass 4, count 0 2006.168.08:29:40.99#ibcon#*after write, iclass 4, count 0 2006.168.08:29:40.99#ibcon#*before return 0, iclass 4, count 0 2006.168.08:29:40.99#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:29:40.99#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.168.08:29:40.99#ibcon#about to clear, iclass 4 cls_cnt 0 2006.168.08:29:40.99#ibcon#cleared, iclass 4 cls_cnt 0 2006.168.08:29:40.99$vc4f8/vb=2,4 2006.168.08:29:40.99#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.168.08:29:40.99#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.168.08:29:40.99#ibcon#ireg 11 cls_cnt 2 2006.168.08:29:40.99#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:29:41.05#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:29:41.05#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:29:41.05#ibcon#enter wrdev, iclass 6, count 2 2006.168.08:29:41.05#ibcon#first serial, iclass 6, count 2 2006.168.08:29:41.05#ibcon#enter sib2, iclass 6, count 2 2006.168.08:29:41.05#ibcon#flushed, iclass 6, count 2 2006.168.08:29:41.05#ibcon#about to write, iclass 6, count 2 2006.168.08:29:41.05#ibcon#wrote, iclass 6, count 2 2006.168.08:29:41.05#ibcon#about to read 3, iclass 6, count 2 2006.168.08:29:41.07#ibcon#read 3, iclass 6, count 2 2006.168.08:29:41.07#ibcon#about to read 4, iclass 6, count 2 2006.168.08:29:41.07#ibcon#read 4, iclass 6, count 2 2006.168.08:29:41.07#ibcon#about to read 5, iclass 6, count 2 2006.168.08:29:41.07#ibcon#read 5, iclass 6, count 2 2006.168.08:29:41.07#ibcon#about to read 6, iclass 6, count 2 2006.168.08:29:41.07#ibcon#read 6, iclass 6, count 2 2006.168.08:29:41.07#ibcon#end of sib2, iclass 6, count 2 2006.168.08:29:41.07#ibcon#*mode == 0, iclass 6, count 2 2006.168.08:29:41.07#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.168.08:29:41.07#ibcon#[27=AT02-04\r\n] 2006.168.08:29:41.07#ibcon#*before write, iclass 6, count 2 2006.168.08:29:41.07#ibcon#enter sib2, iclass 6, count 2 2006.168.08:29:41.07#ibcon#flushed, iclass 6, count 2 2006.168.08:29:41.07#ibcon#about to write, iclass 6, count 2 2006.168.08:29:41.07#ibcon#wrote, iclass 6, count 2 2006.168.08:29:41.07#ibcon#about to read 3, iclass 6, count 2 2006.168.08:29:41.10#ibcon#read 3, iclass 6, count 2 2006.168.08:29:41.10#ibcon#about to read 4, iclass 6, count 2 2006.168.08:29:41.10#ibcon#read 4, iclass 6, count 2 2006.168.08:29:41.10#ibcon#about to read 5, iclass 6, count 2 2006.168.08:29:41.10#ibcon#read 5, iclass 6, count 2 2006.168.08:29:41.10#ibcon#about to read 6, iclass 6, count 2 2006.168.08:29:41.10#ibcon#read 6, iclass 6, count 2 2006.168.08:29:41.10#ibcon#end of sib2, iclass 6, count 2 2006.168.08:29:41.10#ibcon#*after write, iclass 6, count 2 2006.168.08:29:41.10#ibcon#*before return 0, iclass 6, count 2 2006.168.08:29:41.10#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:29:41.10#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.168.08:29:41.10#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.168.08:29:41.10#ibcon#ireg 7 cls_cnt 0 2006.168.08:29:41.10#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:29:41.22#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:29:41.22#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:29:41.22#ibcon#enter wrdev, iclass 6, count 0 2006.168.08:29:41.22#ibcon#first serial, iclass 6, count 0 2006.168.08:29:41.22#ibcon#enter sib2, iclass 6, count 0 2006.168.08:29:41.22#ibcon#flushed, iclass 6, count 0 2006.168.08:29:41.22#ibcon#about to write, iclass 6, count 0 2006.168.08:29:41.22#ibcon#wrote, iclass 6, count 0 2006.168.08:29:41.22#ibcon#about to read 3, iclass 6, count 0 2006.168.08:29:41.24#ibcon#read 3, iclass 6, count 0 2006.168.08:29:41.24#ibcon#about to read 4, iclass 6, count 0 2006.168.08:29:41.24#ibcon#read 4, iclass 6, count 0 2006.168.08:29:41.24#ibcon#about to read 5, iclass 6, count 0 2006.168.08:29:41.24#ibcon#read 5, iclass 6, count 0 2006.168.08:29:41.24#ibcon#about to read 6, iclass 6, count 0 2006.168.08:29:41.24#ibcon#read 6, iclass 6, count 0 2006.168.08:29:41.24#ibcon#end of sib2, iclass 6, count 0 2006.168.08:29:41.24#ibcon#*mode == 0, iclass 6, count 0 2006.168.08:29:41.24#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.168.08:29:41.24#ibcon#[27=USB\r\n] 2006.168.08:29:41.24#ibcon#*before write, iclass 6, count 0 2006.168.08:29:41.24#ibcon#enter sib2, iclass 6, count 0 2006.168.08:29:41.24#ibcon#flushed, iclass 6, count 0 2006.168.08:29:41.24#ibcon#about to write, iclass 6, count 0 2006.168.08:29:41.24#ibcon#wrote, iclass 6, count 0 2006.168.08:29:41.24#ibcon#about to read 3, iclass 6, count 0 2006.168.08:29:41.27#ibcon#read 3, iclass 6, count 0 2006.168.08:29:41.27#ibcon#about to read 4, iclass 6, count 0 2006.168.08:29:41.27#ibcon#read 4, iclass 6, count 0 2006.168.08:29:41.27#ibcon#about to read 5, iclass 6, count 0 2006.168.08:29:41.27#ibcon#read 5, iclass 6, count 0 2006.168.08:29:41.27#ibcon#about to read 6, iclass 6, count 0 2006.168.08:29:41.27#ibcon#read 6, iclass 6, count 0 2006.168.08:29:41.27#ibcon#end of sib2, iclass 6, count 0 2006.168.08:29:41.27#ibcon#*after write, iclass 6, count 0 2006.168.08:29:41.27#ibcon#*before return 0, iclass 6, count 0 2006.168.08:29:41.27#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:29:41.27#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.168.08:29:41.27#ibcon#about to clear, iclass 6 cls_cnt 0 2006.168.08:29:41.27#ibcon#cleared, iclass 6 cls_cnt 0 2006.168.08:29:41.27$vc4f8/vblo=3,656.99 2006.168.08:29:41.27#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.168.08:29:41.27#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.168.08:29:41.27#ibcon#ireg 17 cls_cnt 0 2006.168.08:29:41.27#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:29:41.27#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:29:41.27#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:29:41.27#ibcon#enter wrdev, iclass 10, count 0 2006.168.08:29:41.27#ibcon#first serial, iclass 10, count 0 2006.168.08:29:41.27#ibcon#enter sib2, iclass 10, count 0 2006.168.08:29:41.27#ibcon#flushed, iclass 10, count 0 2006.168.08:29:41.27#ibcon#about to write, iclass 10, count 0 2006.168.08:29:41.27#ibcon#wrote, iclass 10, count 0 2006.168.08:29:41.27#ibcon#about to read 3, iclass 10, count 0 2006.168.08:29:41.29#ibcon#read 3, iclass 10, count 0 2006.168.08:29:41.29#ibcon#about to read 4, iclass 10, count 0 2006.168.08:29:41.29#ibcon#read 4, iclass 10, count 0 2006.168.08:29:41.29#ibcon#about to read 5, iclass 10, count 0 2006.168.08:29:41.29#ibcon#read 5, iclass 10, count 0 2006.168.08:29:41.29#ibcon#about to read 6, iclass 10, count 0 2006.168.08:29:41.29#ibcon#read 6, iclass 10, count 0 2006.168.08:29:41.29#ibcon#end of sib2, iclass 10, count 0 2006.168.08:29:41.29#ibcon#*mode == 0, iclass 10, count 0 2006.168.08:29:41.29#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.168.08:29:41.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.168.08:29:41.29#ibcon#*before write, iclass 10, count 0 2006.168.08:29:41.29#ibcon#enter sib2, iclass 10, count 0 2006.168.08:29:41.29#ibcon#flushed, iclass 10, count 0 2006.168.08:29:41.29#ibcon#about to write, iclass 10, count 0 2006.168.08:29:41.29#ibcon#wrote, iclass 10, count 0 2006.168.08:29:41.29#ibcon#about to read 3, iclass 10, count 0 2006.168.08:29:41.33#ibcon#read 3, iclass 10, count 0 2006.168.08:29:41.33#ibcon#about to read 4, iclass 10, count 0 2006.168.08:29:41.33#ibcon#read 4, iclass 10, count 0 2006.168.08:29:41.33#ibcon#about to read 5, iclass 10, count 0 2006.168.08:29:41.33#ibcon#read 5, iclass 10, count 0 2006.168.08:29:41.33#ibcon#about to read 6, iclass 10, count 0 2006.168.08:29:41.33#ibcon#read 6, iclass 10, count 0 2006.168.08:29:41.33#ibcon#end of sib2, iclass 10, count 0 2006.168.08:29:41.33#ibcon#*after write, iclass 10, count 0 2006.168.08:29:41.33#ibcon#*before return 0, iclass 10, count 0 2006.168.08:29:41.33#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:29:41.33#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.168.08:29:41.33#ibcon#about to clear, iclass 10 cls_cnt 0 2006.168.08:29:41.33#ibcon#cleared, iclass 10 cls_cnt 0 2006.168.08:29:41.33$vc4f8/vb=3,4 2006.168.08:29:41.33#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.168.08:29:41.33#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.168.08:29:41.33#ibcon#ireg 11 cls_cnt 2 2006.168.08:29:41.33#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:29:41.40#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:29:41.40#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:29:41.40#ibcon#enter wrdev, iclass 12, count 2 2006.168.08:29:41.40#ibcon#first serial, iclass 12, count 2 2006.168.08:29:41.40#ibcon#enter sib2, iclass 12, count 2 2006.168.08:29:41.40#ibcon#flushed, iclass 12, count 2 2006.168.08:29:41.40#ibcon#about to write, iclass 12, count 2 2006.168.08:29:41.40#ibcon#wrote, iclass 12, count 2 2006.168.08:29:41.40#ibcon#about to read 3, iclass 12, count 2 2006.168.08:29:41.42#ibcon#read 3, iclass 12, count 2 2006.168.08:29:41.42#ibcon#about to read 4, iclass 12, count 2 2006.168.08:29:41.42#ibcon#read 4, iclass 12, count 2 2006.168.08:29:41.42#ibcon#about to read 5, iclass 12, count 2 2006.168.08:29:41.42#ibcon#read 5, iclass 12, count 2 2006.168.08:29:41.42#ibcon#about to read 6, iclass 12, count 2 2006.168.08:29:41.42#ibcon#read 6, iclass 12, count 2 2006.168.08:29:41.42#ibcon#end of sib2, iclass 12, count 2 2006.168.08:29:41.42#ibcon#*mode == 0, iclass 12, count 2 2006.168.08:29:41.42#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.168.08:29:41.42#ibcon#[27=AT03-04\r\n] 2006.168.08:29:41.42#ibcon#*before write, iclass 12, count 2 2006.168.08:29:41.42#ibcon#enter sib2, iclass 12, count 2 2006.168.08:29:41.42#ibcon#flushed, iclass 12, count 2 2006.168.08:29:41.42#ibcon#about to write, iclass 12, count 2 2006.168.08:29:41.42#ibcon#wrote, iclass 12, count 2 2006.168.08:29:41.42#ibcon#about to read 3, iclass 12, count 2 2006.168.08:29:41.44#ibcon#read 3, iclass 12, count 2 2006.168.08:29:41.44#ibcon#about to read 4, iclass 12, count 2 2006.168.08:29:41.44#ibcon#read 4, iclass 12, count 2 2006.168.08:29:41.44#ibcon#about to read 5, iclass 12, count 2 2006.168.08:29:41.44#ibcon#read 5, iclass 12, count 2 2006.168.08:29:41.44#ibcon#about to read 6, iclass 12, count 2 2006.168.08:29:41.44#ibcon#read 6, iclass 12, count 2 2006.168.08:29:41.44#ibcon#end of sib2, iclass 12, count 2 2006.168.08:29:41.44#ibcon#*after write, iclass 12, count 2 2006.168.08:29:41.44#ibcon#*before return 0, iclass 12, count 2 2006.168.08:29:41.44#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:29:41.44#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.168.08:29:41.44#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.168.08:29:41.44#ibcon#ireg 7 cls_cnt 0 2006.168.08:29:41.44#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:29:41.56#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:29:41.56#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:29:41.56#ibcon#enter wrdev, iclass 12, count 0 2006.168.08:29:41.56#ibcon#first serial, iclass 12, count 0 2006.168.08:29:41.56#ibcon#enter sib2, iclass 12, count 0 2006.168.08:29:41.56#ibcon#flushed, iclass 12, count 0 2006.168.08:29:41.56#ibcon#about to write, iclass 12, count 0 2006.168.08:29:41.56#ibcon#wrote, iclass 12, count 0 2006.168.08:29:41.56#ibcon#about to read 3, iclass 12, count 0 2006.168.08:29:41.58#ibcon#read 3, iclass 12, count 0 2006.168.08:29:41.58#ibcon#about to read 4, iclass 12, count 0 2006.168.08:29:41.58#ibcon#read 4, iclass 12, count 0 2006.168.08:29:41.58#ibcon#about to read 5, iclass 12, count 0 2006.168.08:29:41.58#ibcon#read 5, iclass 12, count 0 2006.168.08:29:41.58#ibcon#about to read 6, iclass 12, count 0 2006.168.08:29:41.58#ibcon#read 6, iclass 12, count 0 2006.168.08:29:41.58#ibcon#end of sib2, iclass 12, count 0 2006.168.08:29:41.58#ibcon#*mode == 0, iclass 12, count 0 2006.168.08:29:41.58#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.168.08:29:41.58#ibcon#[27=USB\r\n] 2006.168.08:29:41.58#ibcon#*before write, iclass 12, count 0 2006.168.08:29:41.58#ibcon#enter sib2, iclass 12, count 0 2006.168.08:29:41.58#ibcon#flushed, iclass 12, count 0 2006.168.08:29:41.58#ibcon#about to write, iclass 12, count 0 2006.168.08:29:41.58#ibcon#wrote, iclass 12, count 0 2006.168.08:29:41.58#ibcon#about to read 3, iclass 12, count 0 2006.168.08:29:41.61#ibcon#read 3, iclass 12, count 0 2006.168.08:29:41.61#ibcon#about to read 4, iclass 12, count 0 2006.168.08:29:41.61#ibcon#read 4, iclass 12, count 0 2006.168.08:29:41.61#ibcon#about to read 5, iclass 12, count 0 2006.168.08:29:41.61#ibcon#read 5, iclass 12, count 0 2006.168.08:29:41.61#ibcon#about to read 6, iclass 12, count 0 2006.168.08:29:41.61#ibcon#read 6, iclass 12, count 0 2006.168.08:29:41.61#ibcon#end of sib2, iclass 12, count 0 2006.168.08:29:41.61#ibcon#*after write, iclass 12, count 0 2006.168.08:29:41.61#ibcon#*before return 0, iclass 12, count 0 2006.168.08:29:41.61#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:29:41.61#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.168.08:29:41.61#ibcon#about to clear, iclass 12 cls_cnt 0 2006.168.08:29:41.61#ibcon#cleared, iclass 12 cls_cnt 0 2006.168.08:29:41.61$vc4f8/vblo=4,712.99 2006.168.08:29:41.61#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.168.08:29:41.61#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.168.08:29:41.61#ibcon#ireg 17 cls_cnt 0 2006.168.08:29:41.61#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:29:41.61#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:29:41.61#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:29:41.61#ibcon#enter wrdev, iclass 14, count 0 2006.168.08:29:41.61#ibcon#first serial, iclass 14, count 0 2006.168.08:29:41.61#ibcon#enter sib2, iclass 14, count 0 2006.168.08:29:41.61#ibcon#flushed, iclass 14, count 0 2006.168.08:29:41.61#ibcon#about to write, iclass 14, count 0 2006.168.08:29:41.61#ibcon#wrote, iclass 14, count 0 2006.168.08:29:41.61#ibcon#about to read 3, iclass 14, count 0 2006.168.08:29:41.63#ibcon#read 3, iclass 14, count 0 2006.168.08:29:41.63#ibcon#about to read 4, iclass 14, count 0 2006.168.08:29:41.63#ibcon#read 4, iclass 14, count 0 2006.168.08:29:41.63#ibcon#about to read 5, iclass 14, count 0 2006.168.08:29:41.63#ibcon#read 5, iclass 14, count 0 2006.168.08:29:41.63#ibcon#about to read 6, iclass 14, count 0 2006.168.08:29:41.63#ibcon#read 6, iclass 14, count 0 2006.168.08:29:41.63#ibcon#end of sib2, iclass 14, count 0 2006.168.08:29:41.63#ibcon#*mode == 0, iclass 14, count 0 2006.168.08:29:41.63#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.168.08:29:41.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.168.08:29:41.63#ibcon#*before write, iclass 14, count 0 2006.168.08:29:41.63#ibcon#enter sib2, iclass 14, count 0 2006.168.08:29:41.63#ibcon#flushed, iclass 14, count 0 2006.168.08:29:41.63#ibcon#about to write, iclass 14, count 0 2006.168.08:29:41.63#ibcon#wrote, iclass 14, count 0 2006.168.08:29:41.63#ibcon#about to read 3, iclass 14, count 0 2006.168.08:29:41.67#abcon#<5=/08 1.4 5.0 26.76 761004.6\r\n> 2006.168.08:29:41.67#ibcon#read 3, iclass 14, count 0 2006.168.08:29:41.67#ibcon#about to read 4, iclass 14, count 0 2006.168.08:29:41.67#ibcon#read 4, iclass 14, count 0 2006.168.08:29:41.67#ibcon#about to read 5, iclass 14, count 0 2006.168.08:29:41.67#ibcon#read 5, iclass 14, count 0 2006.168.08:29:41.67#ibcon#about to read 6, iclass 14, count 0 2006.168.08:29:41.67#ibcon#read 6, iclass 14, count 0 2006.168.08:29:41.67#ibcon#end of sib2, iclass 14, count 0 2006.168.08:29:41.67#ibcon#*after write, iclass 14, count 0 2006.168.08:29:41.67#ibcon#*before return 0, iclass 14, count 0 2006.168.08:29:41.67#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:29:41.67#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.168.08:29:41.67#ibcon#about to clear, iclass 14 cls_cnt 0 2006.168.08:29:41.67#ibcon#cleared, iclass 14 cls_cnt 0 2006.168.08:29:41.67$vc4f8/vb=4,4 2006.168.08:29:41.67#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.168.08:29:41.67#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.168.08:29:41.67#ibcon#ireg 11 cls_cnt 2 2006.168.08:29:41.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:29:41.69#abcon#{5=INTERFACE CLEAR} 2006.168.08:29:41.73#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:29:41.73#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:29:41.73#ibcon#enter wrdev, iclass 19, count 2 2006.168.08:29:41.73#ibcon#first serial, iclass 19, count 2 2006.168.08:29:41.73#ibcon#enter sib2, iclass 19, count 2 2006.168.08:29:41.73#ibcon#flushed, iclass 19, count 2 2006.168.08:29:41.73#ibcon#about to write, iclass 19, count 2 2006.168.08:29:41.73#ibcon#wrote, iclass 19, count 2 2006.168.08:29:41.73#ibcon#about to read 3, iclass 19, count 2 2006.168.08:29:41.75#ibcon#read 3, iclass 19, count 2 2006.168.08:29:41.75#ibcon#about to read 4, iclass 19, count 2 2006.168.08:29:41.75#ibcon#read 4, iclass 19, count 2 2006.168.08:29:41.75#ibcon#about to read 5, iclass 19, count 2 2006.168.08:29:41.75#ibcon#read 5, iclass 19, count 2 2006.168.08:29:41.75#ibcon#about to read 6, iclass 19, count 2 2006.168.08:29:41.75#ibcon#read 6, iclass 19, count 2 2006.168.08:29:41.75#ibcon#end of sib2, iclass 19, count 2 2006.168.08:29:41.75#ibcon#*mode == 0, iclass 19, count 2 2006.168.08:29:41.75#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.168.08:29:41.75#ibcon#[27=AT04-04\r\n] 2006.168.08:29:41.75#ibcon#*before write, iclass 19, count 2 2006.168.08:29:41.75#ibcon#enter sib2, iclass 19, count 2 2006.168.08:29:41.75#ibcon#flushed, iclass 19, count 2 2006.168.08:29:41.75#ibcon#about to write, iclass 19, count 2 2006.168.08:29:41.75#ibcon#wrote, iclass 19, count 2 2006.168.08:29:41.75#ibcon#about to read 3, iclass 19, count 2 2006.168.08:29:41.75#abcon#[5=S1D000X0/0*\r\n] 2006.168.08:29:41.78#ibcon#read 3, iclass 19, count 2 2006.168.08:29:41.78#ibcon#about to read 4, iclass 19, count 2 2006.168.08:29:41.78#ibcon#read 4, iclass 19, count 2 2006.168.08:29:41.78#ibcon#about to read 5, iclass 19, count 2 2006.168.08:29:41.78#ibcon#read 5, iclass 19, count 2 2006.168.08:29:41.78#ibcon#about to read 6, iclass 19, count 2 2006.168.08:29:41.78#ibcon#read 6, iclass 19, count 2 2006.168.08:29:41.78#ibcon#end of sib2, iclass 19, count 2 2006.168.08:29:41.78#ibcon#*after write, iclass 19, count 2 2006.168.08:29:41.78#ibcon#*before return 0, iclass 19, count 2 2006.168.08:29:41.78#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:29:41.78#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.168.08:29:41.78#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.168.08:29:41.78#ibcon#ireg 7 cls_cnt 0 2006.168.08:29:41.78#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:29:41.90#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:29:41.90#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:29:41.90#ibcon#enter wrdev, iclass 19, count 0 2006.168.08:29:41.90#ibcon#first serial, iclass 19, count 0 2006.168.08:29:41.90#ibcon#enter sib2, iclass 19, count 0 2006.168.08:29:41.90#ibcon#flushed, iclass 19, count 0 2006.168.08:29:41.90#ibcon#about to write, iclass 19, count 0 2006.168.08:29:41.90#ibcon#wrote, iclass 19, count 0 2006.168.08:29:41.90#ibcon#about to read 3, iclass 19, count 0 2006.168.08:29:41.92#ibcon#read 3, iclass 19, count 0 2006.168.08:29:41.92#ibcon#about to read 4, iclass 19, count 0 2006.168.08:29:41.92#ibcon#read 4, iclass 19, count 0 2006.168.08:29:41.92#ibcon#about to read 5, iclass 19, count 0 2006.168.08:29:41.92#ibcon#read 5, iclass 19, count 0 2006.168.08:29:41.92#ibcon#about to read 6, iclass 19, count 0 2006.168.08:29:41.92#ibcon#read 6, iclass 19, count 0 2006.168.08:29:41.92#ibcon#end of sib2, iclass 19, count 0 2006.168.08:29:41.92#ibcon#*mode == 0, iclass 19, count 0 2006.168.08:29:41.92#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.168.08:29:41.92#ibcon#[27=USB\r\n] 2006.168.08:29:41.92#ibcon#*before write, iclass 19, count 0 2006.168.08:29:41.92#ibcon#enter sib2, iclass 19, count 0 2006.168.08:29:41.92#ibcon#flushed, iclass 19, count 0 2006.168.08:29:41.92#ibcon#about to write, iclass 19, count 0 2006.168.08:29:41.92#ibcon#wrote, iclass 19, count 0 2006.168.08:29:41.92#ibcon#about to read 3, iclass 19, count 0 2006.168.08:29:41.95#ibcon#read 3, iclass 19, count 0 2006.168.08:29:41.95#ibcon#about to read 4, iclass 19, count 0 2006.168.08:29:41.95#ibcon#read 4, iclass 19, count 0 2006.168.08:29:41.95#ibcon#about to read 5, iclass 19, count 0 2006.168.08:29:41.95#ibcon#read 5, iclass 19, count 0 2006.168.08:29:41.95#ibcon#about to read 6, iclass 19, count 0 2006.168.08:29:41.95#ibcon#read 6, iclass 19, count 0 2006.168.08:29:41.95#ibcon#end of sib2, iclass 19, count 0 2006.168.08:29:41.95#ibcon#*after write, iclass 19, count 0 2006.168.08:29:41.95#ibcon#*before return 0, iclass 19, count 0 2006.168.08:29:41.95#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:29:41.95#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.168.08:29:41.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.168.08:29:41.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.168.08:29:41.95$vc4f8/vblo=5,744.99 2006.168.08:29:41.95#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.168.08:29:41.95#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.168.08:29:41.95#ibcon#ireg 17 cls_cnt 0 2006.168.08:29:41.95#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:29:41.95#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:29:41.95#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:29:41.95#ibcon#enter wrdev, iclass 22, count 0 2006.168.08:29:41.95#ibcon#first serial, iclass 22, count 0 2006.168.08:29:41.95#ibcon#enter sib2, iclass 22, count 0 2006.168.08:29:41.95#ibcon#flushed, iclass 22, count 0 2006.168.08:29:41.95#ibcon#about to write, iclass 22, count 0 2006.168.08:29:41.95#ibcon#wrote, iclass 22, count 0 2006.168.08:29:41.95#ibcon#about to read 3, iclass 22, count 0 2006.168.08:29:41.97#ibcon#read 3, iclass 22, count 0 2006.168.08:29:41.97#ibcon#about to read 4, iclass 22, count 0 2006.168.08:29:41.97#ibcon#read 4, iclass 22, count 0 2006.168.08:29:41.97#ibcon#about to read 5, iclass 22, count 0 2006.168.08:29:41.97#ibcon#read 5, iclass 22, count 0 2006.168.08:29:41.97#ibcon#about to read 6, iclass 22, count 0 2006.168.08:29:41.97#ibcon#read 6, iclass 22, count 0 2006.168.08:29:41.97#ibcon#end of sib2, iclass 22, count 0 2006.168.08:29:41.97#ibcon#*mode == 0, iclass 22, count 0 2006.168.08:29:41.97#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.168.08:29:41.97#ibcon#[28=FRQ=05,744.99\r\n] 2006.168.08:29:41.97#ibcon#*before write, iclass 22, count 0 2006.168.08:29:41.97#ibcon#enter sib2, iclass 22, count 0 2006.168.08:29:41.97#ibcon#flushed, iclass 22, count 0 2006.168.08:29:41.97#ibcon#about to write, iclass 22, count 0 2006.168.08:29:41.97#ibcon#wrote, iclass 22, count 0 2006.168.08:29:41.97#ibcon#about to read 3, iclass 22, count 0 2006.168.08:29:42.01#ibcon#read 3, iclass 22, count 0 2006.168.08:29:42.01#ibcon#about to read 4, iclass 22, count 0 2006.168.08:29:42.01#ibcon#read 4, iclass 22, count 0 2006.168.08:29:42.01#ibcon#about to read 5, iclass 22, count 0 2006.168.08:29:42.01#ibcon#read 5, iclass 22, count 0 2006.168.08:29:42.01#ibcon#about to read 6, iclass 22, count 0 2006.168.08:29:42.01#ibcon#read 6, iclass 22, count 0 2006.168.08:29:42.01#ibcon#end of sib2, iclass 22, count 0 2006.168.08:29:42.01#ibcon#*after write, iclass 22, count 0 2006.168.08:29:42.01#ibcon#*before return 0, iclass 22, count 0 2006.168.08:29:42.01#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:29:42.01#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.168.08:29:42.01#ibcon#about to clear, iclass 22 cls_cnt 0 2006.168.08:29:42.01#ibcon#cleared, iclass 22 cls_cnt 0 2006.168.08:29:42.01$vc4f8/vb=5,4 2006.168.08:29:42.01#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.168.08:29:42.01#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.168.08:29:42.01#ibcon#ireg 11 cls_cnt 2 2006.168.08:29:42.01#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:29:42.08#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:29:42.08#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:29:42.08#ibcon#enter wrdev, iclass 24, count 2 2006.168.08:29:42.08#ibcon#first serial, iclass 24, count 2 2006.168.08:29:42.08#ibcon#enter sib2, iclass 24, count 2 2006.168.08:29:42.08#ibcon#flushed, iclass 24, count 2 2006.168.08:29:42.08#ibcon#about to write, iclass 24, count 2 2006.168.08:29:42.08#ibcon#wrote, iclass 24, count 2 2006.168.08:29:42.08#ibcon#about to read 3, iclass 24, count 2 2006.168.08:29:42.10#ibcon#read 3, iclass 24, count 2 2006.168.08:29:42.10#ibcon#about to read 4, iclass 24, count 2 2006.168.08:29:42.10#ibcon#read 4, iclass 24, count 2 2006.168.08:29:42.10#ibcon#about to read 5, iclass 24, count 2 2006.168.08:29:42.10#ibcon#read 5, iclass 24, count 2 2006.168.08:29:42.10#ibcon#about to read 6, iclass 24, count 2 2006.168.08:29:42.10#ibcon#read 6, iclass 24, count 2 2006.168.08:29:42.10#ibcon#end of sib2, iclass 24, count 2 2006.168.08:29:42.10#ibcon#*mode == 0, iclass 24, count 2 2006.168.08:29:42.10#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.168.08:29:42.10#ibcon#[27=AT05-04\r\n] 2006.168.08:29:42.10#ibcon#*before write, iclass 24, count 2 2006.168.08:29:42.10#ibcon#enter sib2, iclass 24, count 2 2006.168.08:29:42.10#ibcon#flushed, iclass 24, count 2 2006.168.08:29:42.10#ibcon#about to write, iclass 24, count 2 2006.168.08:29:42.10#ibcon#wrote, iclass 24, count 2 2006.168.08:29:42.10#ibcon#about to read 3, iclass 24, count 2 2006.168.08:29:42.12#ibcon#read 3, iclass 24, count 2 2006.168.08:29:42.12#ibcon#about to read 4, iclass 24, count 2 2006.168.08:29:42.12#ibcon#read 4, iclass 24, count 2 2006.168.08:29:42.12#ibcon#about to read 5, iclass 24, count 2 2006.168.08:29:42.12#ibcon#read 5, iclass 24, count 2 2006.168.08:29:42.12#ibcon#about to read 6, iclass 24, count 2 2006.168.08:29:42.12#ibcon#read 6, iclass 24, count 2 2006.168.08:29:42.12#ibcon#end of sib2, iclass 24, count 2 2006.168.08:29:42.12#ibcon#*after write, iclass 24, count 2 2006.168.08:29:42.12#ibcon#*before return 0, iclass 24, count 2 2006.168.08:29:42.12#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:29:42.12#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.168.08:29:42.12#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.168.08:29:42.12#ibcon#ireg 7 cls_cnt 0 2006.168.08:29:42.12#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:29:42.24#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:29:42.24#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:29:42.24#ibcon#enter wrdev, iclass 24, count 0 2006.168.08:29:42.24#ibcon#first serial, iclass 24, count 0 2006.168.08:29:42.24#ibcon#enter sib2, iclass 24, count 0 2006.168.08:29:42.24#ibcon#flushed, iclass 24, count 0 2006.168.08:29:42.24#ibcon#about to write, iclass 24, count 0 2006.168.08:29:42.24#ibcon#wrote, iclass 24, count 0 2006.168.08:29:42.24#ibcon#about to read 3, iclass 24, count 0 2006.168.08:29:42.26#ibcon#read 3, iclass 24, count 0 2006.168.08:29:42.26#ibcon#about to read 4, iclass 24, count 0 2006.168.08:29:42.26#ibcon#read 4, iclass 24, count 0 2006.168.08:29:42.26#ibcon#about to read 5, iclass 24, count 0 2006.168.08:29:42.26#ibcon#read 5, iclass 24, count 0 2006.168.08:29:42.26#ibcon#about to read 6, iclass 24, count 0 2006.168.08:29:42.26#ibcon#read 6, iclass 24, count 0 2006.168.08:29:42.26#ibcon#end of sib2, iclass 24, count 0 2006.168.08:29:42.26#ibcon#*mode == 0, iclass 24, count 0 2006.168.08:29:42.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.168.08:29:42.26#ibcon#[27=USB\r\n] 2006.168.08:29:42.26#ibcon#*before write, iclass 24, count 0 2006.168.08:29:42.26#ibcon#enter sib2, iclass 24, count 0 2006.168.08:29:42.26#ibcon#flushed, iclass 24, count 0 2006.168.08:29:42.26#ibcon#about to write, iclass 24, count 0 2006.168.08:29:42.26#ibcon#wrote, iclass 24, count 0 2006.168.08:29:42.26#ibcon#about to read 3, iclass 24, count 0 2006.168.08:29:42.29#ibcon#read 3, iclass 24, count 0 2006.168.08:29:42.29#ibcon#about to read 4, iclass 24, count 0 2006.168.08:29:42.29#ibcon#read 4, iclass 24, count 0 2006.168.08:29:42.29#ibcon#about to read 5, iclass 24, count 0 2006.168.08:29:42.29#ibcon#read 5, iclass 24, count 0 2006.168.08:29:42.29#ibcon#about to read 6, iclass 24, count 0 2006.168.08:29:42.29#ibcon#read 6, iclass 24, count 0 2006.168.08:29:42.29#ibcon#end of sib2, iclass 24, count 0 2006.168.08:29:42.29#ibcon#*after write, iclass 24, count 0 2006.168.08:29:42.29#ibcon#*before return 0, iclass 24, count 0 2006.168.08:29:42.29#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:29:42.29#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.168.08:29:42.29#ibcon#about to clear, iclass 24 cls_cnt 0 2006.168.08:29:42.29#ibcon#cleared, iclass 24 cls_cnt 0 2006.168.08:29:42.29$vc4f8/vblo=6,752.99 2006.168.08:29:42.29#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.168.08:29:42.29#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.168.08:29:42.29#ibcon#ireg 17 cls_cnt 0 2006.168.08:29:42.29#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:29:42.29#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:29:42.29#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:29:42.29#ibcon#enter wrdev, iclass 26, count 0 2006.168.08:29:42.29#ibcon#first serial, iclass 26, count 0 2006.168.08:29:42.29#ibcon#enter sib2, iclass 26, count 0 2006.168.08:29:42.29#ibcon#flushed, iclass 26, count 0 2006.168.08:29:42.29#ibcon#about to write, iclass 26, count 0 2006.168.08:29:42.29#ibcon#wrote, iclass 26, count 0 2006.168.08:29:42.29#ibcon#about to read 3, iclass 26, count 0 2006.168.08:29:42.31#ibcon#read 3, iclass 26, count 0 2006.168.08:29:42.31#ibcon#about to read 4, iclass 26, count 0 2006.168.08:29:42.31#ibcon#read 4, iclass 26, count 0 2006.168.08:29:42.31#ibcon#about to read 5, iclass 26, count 0 2006.168.08:29:42.31#ibcon#read 5, iclass 26, count 0 2006.168.08:29:42.31#ibcon#about to read 6, iclass 26, count 0 2006.168.08:29:42.31#ibcon#read 6, iclass 26, count 0 2006.168.08:29:42.31#ibcon#end of sib2, iclass 26, count 0 2006.168.08:29:42.31#ibcon#*mode == 0, iclass 26, count 0 2006.168.08:29:42.31#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.168.08:29:42.31#ibcon#[28=FRQ=06,752.99\r\n] 2006.168.08:29:42.31#ibcon#*before write, iclass 26, count 0 2006.168.08:29:42.31#ibcon#enter sib2, iclass 26, count 0 2006.168.08:29:42.31#ibcon#flushed, iclass 26, count 0 2006.168.08:29:42.31#ibcon#about to write, iclass 26, count 0 2006.168.08:29:42.31#ibcon#wrote, iclass 26, count 0 2006.168.08:29:42.31#ibcon#about to read 3, iclass 26, count 0 2006.168.08:29:42.35#ibcon#read 3, iclass 26, count 0 2006.168.08:29:42.35#ibcon#about to read 4, iclass 26, count 0 2006.168.08:29:42.35#ibcon#read 4, iclass 26, count 0 2006.168.08:29:42.35#ibcon#about to read 5, iclass 26, count 0 2006.168.08:29:42.35#ibcon#read 5, iclass 26, count 0 2006.168.08:29:42.35#ibcon#about to read 6, iclass 26, count 0 2006.168.08:29:42.35#ibcon#read 6, iclass 26, count 0 2006.168.08:29:42.35#ibcon#end of sib2, iclass 26, count 0 2006.168.08:29:42.35#ibcon#*after write, iclass 26, count 0 2006.168.08:29:42.35#ibcon#*before return 0, iclass 26, count 0 2006.168.08:29:42.35#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:29:42.35#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.168.08:29:42.35#ibcon#about to clear, iclass 26 cls_cnt 0 2006.168.08:29:42.35#ibcon#cleared, iclass 26 cls_cnt 0 2006.168.08:29:42.35$vc4f8/vb=6,4 2006.168.08:29:42.35#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.168.08:29:42.35#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.168.08:29:42.35#ibcon#ireg 11 cls_cnt 2 2006.168.08:29:42.35#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:29:42.42#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:29:42.42#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:29:42.42#ibcon#enter wrdev, iclass 28, count 2 2006.168.08:29:42.42#ibcon#first serial, iclass 28, count 2 2006.168.08:29:42.42#ibcon#enter sib2, iclass 28, count 2 2006.168.08:29:42.42#ibcon#flushed, iclass 28, count 2 2006.168.08:29:42.42#ibcon#about to write, iclass 28, count 2 2006.168.08:29:42.42#ibcon#wrote, iclass 28, count 2 2006.168.08:29:42.42#ibcon#about to read 3, iclass 28, count 2 2006.168.08:29:42.44#ibcon#read 3, iclass 28, count 2 2006.168.08:29:42.44#ibcon#about to read 4, iclass 28, count 2 2006.168.08:29:42.44#ibcon#read 4, iclass 28, count 2 2006.168.08:29:42.44#ibcon#about to read 5, iclass 28, count 2 2006.168.08:29:42.44#ibcon#read 5, iclass 28, count 2 2006.168.08:29:42.44#ibcon#about to read 6, iclass 28, count 2 2006.168.08:29:42.44#ibcon#read 6, iclass 28, count 2 2006.168.08:29:42.44#ibcon#end of sib2, iclass 28, count 2 2006.168.08:29:42.44#ibcon#*mode == 0, iclass 28, count 2 2006.168.08:29:42.44#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.168.08:29:42.44#ibcon#[27=AT06-04\r\n] 2006.168.08:29:42.44#ibcon#*before write, iclass 28, count 2 2006.168.08:29:42.44#ibcon#enter sib2, iclass 28, count 2 2006.168.08:29:42.44#ibcon#flushed, iclass 28, count 2 2006.168.08:29:42.44#ibcon#about to write, iclass 28, count 2 2006.168.08:29:42.44#ibcon#wrote, iclass 28, count 2 2006.168.08:29:42.44#ibcon#about to read 3, iclass 28, count 2 2006.168.08:29:42.46#ibcon#read 3, iclass 28, count 2 2006.168.08:29:42.46#ibcon#about to read 4, iclass 28, count 2 2006.168.08:29:42.46#ibcon#read 4, iclass 28, count 2 2006.168.08:29:42.46#ibcon#about to read 5, iclass 28, count 2 2006.168.08:29:42.46#ibcon#read 5, iclass 28, count 2 2006.168.08:29:42.46#ibcon#about to read 6, iclass 28, count 2 2006.168.08:29:42.46#ibcon#read 6, iclass 28, count 2 2006.168.08:29:42.46#ibcon#end of sib2, iclass 28, count 2 2006.168.08:29:42.46#ibcon#*after write, iclass 28, count 2 2006.168.08:29:42.46#ibcon#*before return 0, iclass 28, count 2 2006.168.08:29:42.46#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:29:42.46#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.168.08:29:42.46#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.168.08:29:42.46#ibcon#ireg 7 cls_cnt 0 2006.168.08:29:42.46#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:29:42.58#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:29:42.58#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:29:42.58#ibcon#enter wrdev, iclass 28, count 0 2006.168.08:29:42.58#ibcon#first serial, iclass 28, count 0 2006.168.08:29:42.58#ibcon#enter sib2, iclass 28, count 0 2006.168.08:29:42.58#ibcon#flushed, iclass 28, count 0 2006.168.08:29:42.58#ibcon#about to write, iclass 28, count 0 2006.168.08:29:42.58#ibcon#wrote, iclass 28, count 0 2006.168.08:29:42.58#ibcon#about to read 3, iclass 28, count 0 2006.168.08:29:42.60#ibcon#read 3, iclass 28, count 0 2006.168.08:29:42.60#ibcon#about to read 4, iclass 28, count 0 2006.168.08:29:42.60#ibcon#read 4, iclass 28, count 0 2006.168.08:29:42.60#ibcon#about to read 5, iclass 28, count 0 2006.168.08:29:42.60#ibcon#read 5, iclass 28, count 0 2006.168.08:29:42.60#ibcon#about to read 6, iclass 28, count 0 2006.168.08:29:42.60#ibcon#read 6, iclass 28, count 0 2006.168.08:29:42.60#ibcon#end of sib2, iclass 28, count 0 2006.168.08:29:42.60#ibcon#*mode == 0, iclass 28, count 0 2006.168.08:29:42.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.168.08:29:42.60#ibcon#[27=USB\r\n] 2006.168.08:29:42.60#ibcon#*before write, iclass 28, count 0 2006.168.08:29:42.60#ibcon#enter sib2, iclass 28, count 0 2006.168.08:29:42.60#ibcon#flushed, iclass 28, count 0 2006.168.08:29:42.60#ibcon#about to write, iclass 28, count 0 2006.168.08:29:42.60#ibcon#wrote, iclass 28, count 0 2006.168.08:29:42.60#ibcon#about to read 3, iclass 28, count 0 2006.168.08:29:42.63#ibcon#read 3, iclass 28, count 0 2006.168.08:29:42.63#ibcon#about to read 4, iclass 28, count 0 2006.168.08:29:42.63#ibcon#read 4, iclass 28, count 0 2006.168.08:29:42.63#ibcon#about to read 5, iclass 28, count 0 2006.168.08:29:42.63#ibcon#read 5, iclass 28, count 0 2006.168.08:29:42.63#ibcon#about to read 6, iclass 28, count 0 2006.168.08:29:42.63#ibcon#read 6, iclass 28, count 0 2006.168.08:29:42.63#ibcon#end of sib2, iclass 28, count 0 2006.168.08:29:42.63#ibcon#*after write, iclass 28, count 0 2006.168.08:29:42.63#ibcon#*before return 0, iclass 28, count 0 2006.168.08:29:42.63#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:29:42.63#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.168.08:29:42.63#ibcon#about to clear, iclass 28 cls_cnt 0 2006.168.08:29:42.63#ibcon#cleared, iclass 28 cls_cnt 0 2006.168.08:29:42.63$vc4f8/vabw=wide 2006.168.08:29:42.63#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.168.08:29:42.63#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.168.08:29:42.63#ibcon#ireg 8 cls_cnt 0 2006.168.08:29:42.63#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:29:42.63#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:29:42.63#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:29:42.63#ibcon#enter wrdev, iclass 30, count 0 2006.168.08:29:42.63#ibcon#first serial, iclass 30, count 0 2006.168.08:29:42.63#ibcon#enter sib2, iclass 30, count 0 2006.168.08:29:42.63#ibcon#flushed, iclass 30, count 0 2006.168.08:29:42.63#ibcon#about to write, iclass 30, count 0 2006.168.08:29:42.63#ibcon#wrote, iclass 30, count 0 2006.168.08:29:42.63#ibcon#about to read 3, iclass 30, count 0 2006.168.08:29:42.65#ibcon#read 3, iclass 30, count 0 2006.168.08:29:42.65#ibcon#about to read 4, iclass 30, count 0 2006.168.08:29:42.65#ibcon#read 4, iclass 30, count 0 2006.168.08:29:42.65#ibcon#about to read 5, iclass 30, count 0 2006.168.08:29:42.65#ibcon#read 5, iclass 30, count 0 2006.168.08:29:42.65#ibcon#about to read 6, iclass 30, count 0 2006.168.08:29:42.65#ibcon#read 6, iclass 30, count 0 2006.168.08:29:42.65#ibcon#end of sib2, iclass 30, count 0 2006.168.08:29:42.65#ibcon#*mode == 0, iclass 30, count 0 2006.168.08:29:42.65#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.168.08:29:42.65#ibcon#[25=BW32\r\n] 2006.168.08:29:42.65#ibcon#*before write, iclass 30, count 0 2006.168.08:29:42.65#ibcon#enter sib2, iclass 30, count 0 2006.168.08:29:42.65#ibcon#flushed, iclass 30, count 0 2006.168.08:29:42.65#ibcon#about to write, iclass 30, count 0 2006.168.08:29:42.65#ibcon#wrote, iclass 30, count 0 2006.168.08:29:42.65#ibcon#about to read 3, iclass 30, count 0 2006.168.08:29:42.68#ibcon#read 3, iclass 30, count 0 2006.168.08:29:42.68#ibcon#about to read 4, iclass 30, count 0 2006.168.08:29:42.68#ibcon#read 4, iclass 30, count 0 2006.168.08:29:42.68#ibcon#about to read 5, iclass 30, count 0 2006.168.08:29:42.68#ibcon#read 5, iclass 30, count 0 2006.168.08:29:42.68#ibcon#about to read 6, iclass 30, count 0 2006.168.08:29:42.68#ibcon#read 6, iclass 30, count 0 2006.168.08:29:42.68#ibcon#end of sib2, iclass 30, count 0 2006.168.08:29:42.68#ibcon#*after write, iclass 30, count 0 2006.168.08:29:42.68#ibcon#*before return 0, iclass 30, count 0 2006.168.08:29:42.68#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:29:42.68#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.168.08:29:42.68#ibcon#about to clear, iclass 30 cls_cnt 0 2006.168.08:29:42.68#ibcon#cleared, iclass 30 cls_cnt 0 2006.168.08:29:42.68$vc4f8/vbbw=wide 2006.168.08:29:42.68#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.168.08:29:42.68#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.168.08:29:42.68#ibcon#ireg 8 cls_cnt 0 2006.168.08:29:42.68#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:29:42.76#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:29:42.76#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:29:42.76#ibcon#enter wrdev, iclass 32, count 0 2006.168.08:29:42.76#ibcon#first serial, iclass 32, count 0 2006.168.08:29:42.76#ibcon#enter sib2, iclass 32, count 0 2006.168.08:29:42.76#ibcon#flushed, iclass 32, count 0 2006.168.08:29:42.76#ibcon#about to write, iclass 32, count 0 2006.168.08:29:42.76#ibcon#wrote, iclass 32, count 0 2006.168.08:29:42.76#ibcon#about to read 3, iclass 32, count 0 2006.168.08:29:42.78#ibcon#read 3, iclass 32, count 0 2006.168.08:29:42.78#ibcon#about to read 4, iclass 32, count 0 2006.168.08:29:42.78#ibcon#read 4, iclass 32, count 0 2006.168.08:29:42.78#ibcon#about to read 5, iclass 32, count 0 2006.168.08:29:42.78#ibcon#read 5, iclass 32, count 0 2006.168.08:29:42.78#ibcon#about to read 6, iclass 32, count 0 2006.168.08:29:42.78#ibcon#read 6, iclass 32, count 0 2006.168.08:29:42.78#ibcon#end of sib2, iclass 32, count 0 2006.168.08:29:42.78#ibcon#*mode == 0, iclass 32, count 0 2006.168.08:29:42.78#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.168.08:29:42.78#ibcon#[27=BW32\r\n] 2006.168.08:29:42.78#ibcon#*before write, iclass 32, count 0 2006.168.08:29:42.78#ibcon#enter sib2, iclass 32, count 0 2006.168.08:29:42.78#ibcon#flushed, iclass 32, count 0 2006.168.08:29:42.78#ibcon#about to write, iclass 32, count 0 2006.168.08:29:42.78#ibcon#wrote, iclass 32, count 0 2006.168.08:29:42.78#ibcon#about to read 3, iclass 32, count 0 2006.168.08:29:42.80#ibcon#read 3, iclass 32, count 0 2006.168.08:29:42.80#ibcon#about to read 4, iclass 32, count 0 2006.168.08:29:42.80#ibcon#read 4, iclass 32, count 0 2006.168.08:29:42.80#ibcon#about to read 5, iclass 32, count 0 2006.168.08:29:42.80#ibcon#read 5, iclass 32, count 0 2006.168.08:29:42.80#ibcon#about to read 6, iclass 32, count 0 2006.168.08:29:42.80#ibcon#read 6, iclass 32, count 0 2006.168.08:29:42.80#ibcon#end of sib2, iclass 32, count 0 2006.168.08:29:42.80#ibcon#*after write, iclass 32, count 0 2006.168.08:29:42.80#ibcon#*before return 0, iclass 32, count 0 2006.168.08:29:42.80#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:29:42.80#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.168.08:29:42.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.168.08:29:42.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.168.08:29:42.80$4f8m12a/ifd4f 2006.168.08:29:42.80$ifd4f/lo= 2006.168.08:29:42.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.168.08:29:42.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.168.08:29:42.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.168.08:29:42.80$ifd4f/patch= 2006.168.08:29:42.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.168.08:29:42.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.168.08:29:42.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.168.08:29:42.81$4f8m12a/"form=m,16.000,1:2 2006.168.08:29:42.81$4f8m12a/"tpicd 2006.168.08:29:42.81$4f8m12a/echo=off 2006.168.08:29:42.81$4f8m12a/xlog=off 2006.168.08:29:42.81:!2006.168.08:30:10 2006.168.08:29:45.14#trakl#Source acquired 2006.168.08:29:46.14#flagr#flagr/antenna,acquired 2006.168.08:30:10.01:preob 2006.168.08:30:11.14/onsource/TRACKING 2006.168.08:30:11.14:!2006.168.08:30:20 2006.168.08:30:20.00:data_valid=on 2006.168.08:30:20.00:midob 2006.168.08:30:20.14/onsource/TRACKING 2006.168.08:30:20.14/wx/26.76,1004.7,77 2006.168.08:30:20.29/cable/+6.4724E-03 2006.168.08:30:21.38/va/01,08,usb,yes,30,31 2006.168.08:30:21.38/va/02,07,usb,yes,30,31 2006.168.08:30:21.38/va/03,06,usb,yes,31,32 2006.168.08:30:21.38/va/04,07,usb,yes,30,33 2006.168.08:30:21.38/va/05,07,usb,yes,31,32 2006.168.08:30:21.38/va/06,06,usb,yes,30,30 2006.168.08:30:21.38/va/07,06,usb,yes,30,30 2006.168.08:30:21.38/va/08,07,usb,yes,29,28 2006.168.08:30:21.61/valo/01,532.99,yes,locked 2006.168.08:30:21.61/valo/02,572.99,yes,locked 2006.168.08:30:21.61/valo/03,672.99,yes,locked 2006.168.08:30:21.61/valo/04,832.99,yes,locked 2006.168.08:30:21.61/valo/05,652.99,yes,locked 2006.168.08:30:21.61/valo/06,772.99,yes,locked 2006.168.08:30:21.61/valo/07,832.99,yes,locked 2006.168.08:30:21.61/valo/08,852.99,yes,locked 2006.168.08:30:22.70/vb/01,04,usb,yes,29,28 2006.168.08:30:22.70/vb/02,04,usb,yes,31,32 2006.168.08:30:22.70/vb/03,04,usb,yes,27,31 2006.168.08:30:22.70/vb/04,04,usb,yes,28,28 2006.168.08:30:22.70/vb/05,04,usb,yes,27,31 2006.168.08:30:22.70/vb/06,04,usb,yes,28,31 2006.168.08:30:22.70/vb/07,04,usb,yes,30,30 2006.168.08:30:22.70/vb/08,04,usb,yes,27,31 2006.168.08:30:22.94/vblo/01,632.99,yes,locked 2006.168.08:30:22.94/vblo/02,640.99,yes,locked 2006.168.08:30:22.94/vblo/03,656.99,yes,locked 2006.168.08:30:22.94/vblo/04,712.99,yes,locked 2006.168.08:30:22.94/vblo/05,744.99,yes,locked 2006.168.08:30:22.94/vblo/06,752.99,yes,locked 2006.168.08:30:22.94/vblo/07,734.99,yes,locked 2006.168.08:30:22.94/vblo/08,744.99,yes,locked 2006.168.08:30:23.09/vabw/8 2006.168.08:30:23.24/vbbw/8 2006.168.08:30:23.33/xfe/off,on,15.2 2006.168.08:30:23.72/ifatt/23,28,28,28 2006.168.08:30:24.07/fmout-gps/S +4.17E-07 2006.168.08:30:24.12:!2006.168.08:31:20 2006.168.08:31:20.01:data_valid=off 2006.168.08:31:20.01:postob 2006.168.08:31:20.21/cable/+6.4729E-03 2006.168.08:31:20.21/wx/26.75,1004.7,76 2006.168.08:31:21.08/fmout-gps/S +4.17E-07 2006.168.08:31:21.08:checkk5last 2006.168.08:31:21.08&checkk5last/chk_obsdata=1 2006.168.08:31:21.08&checkk5last/chk_obsdata=2 2006.168.08:31:21.08&checkk5last/chk_obsdata=3 2006.168.08:31:21.08&checkk5last/chk_obsdata=4 2006.168.08:31:21.08&checkk5last/k5log=1 2006.168.08:31:21.08&checkk5last/k5log=2 2006.168.08:31:21.08&checkk5last/k5log=3 2006.168.08:31:21.08&checkk5last/k5log=4 2006.168.08:31:21.08&checkk5last/obsinfo 2006.168.08:31:21.44/chk_obsdata//k5ts1/T1680830??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.168.08:31:21.81/chk_obsdata//k5ts2/T1680830??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.168.08:31:22.18/chk_obsdata//k5ts3/T1680830??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.168.08:31:22.56/chk_obsdata//k5ts4/T1680830??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.168.08:31:23.25/k5log//k5ts1_log_newline 2006.168.08:31:23.94/k5log//k5ts2_log_newline 2006.168.08:31:24.63/k5log//k5ts3_log_newline 2006.168.08:31:25.32/k5log//k5ts4_log_newline 2006.168.08:31:25.35/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.168.08:31:25.35:"sched_end 2006.168.08:31:25.35:source=idle 2006.168.08:31:26.14:stow 2006.168.08:31:26.14&stow/source=idle 2006.168.08:31:26.14&stow/"this is stow command. 2006.168.08:31:26.14&stow/antenna=m3 2006.168.08:31:26.14#flagr#flagr/antenna,new-source 2006.168.08:31:29.01:!+10m 2006.168.08:41:29.02:standby 2006.168.08:41:29.02&standby/"this is standby command. 2006.168.08:41:29.02&standby/antenna=m0 2006.168.08:41:30.01:sy=cp /usr2/log/k06168ts.log /usr2/log_backup/ 2006.168.08:41:30.06:log=k06169ts