2006.161.08:41:41.11:Log Opened: Mark IV Field System Version 9.7.7 2006.161.08:41:41.11:location,TSUKUB32,-140.09,36.10,61.0 2006.161.08:41:41.11:horizon1,0.,5.,360. 2006.161.08:41:41.12:antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.161.08:41:41.12:equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.161.08:41:41.13:drivev11,330,270,no 2006.161.08:41:41.13:drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.161.08:41:41.13:drivev13,15.000,268,10.000,10.000,10.000 2006.161.08:41:41.14:drivev21,330,270,no 2006.161.08:41:41.14:drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.161.08:41:41.19:drivev23,15.000,268,10.000,10.000,10.000 2006.161.08:41:41.19:head10,all,all,all,odd,adaptive,no,5.0000,1 2006.161.08:41:41.20:head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.161.08:41:41.20:head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.161.08:41:41.20:head20,all,all,all,odd,adaptive,no,5.0000,1 2006.161.08:41:41.21:head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.161.08:41:41.21:head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.161.08:41:41.21:time,-0.364,101.533,rate 2006.161.08:41:41.22:flagr,200 2006.161.08:41:41.22:proc=k06162ts 2006.161.08:41:41.23:" k06162 2006 tsukub32 t ts 2006.161.08:41:41.27:" t tsukub32 azel .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 ts 108 2006.161.08:41:41.28:" ts tsukub32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.161.08:41:41.28:" 108 tsukub32 14 17400 2006.161.08:41:41.29:" drudg version 050216 compiled under fs 9.7.07 2006.161.08:41:41.29:" rack=k4-2/m4 recorder 1=k5 recorder 2=none 2006.161.08:41:41.29:!2006.162.07:19:50 2006.162.07:19:50.00:unstow 2006.162.07:19:50.00&unstow/antenna=e 2006.162.07:19:50.00&unstow/!+10s 2006.162.07:19:50.00&unstow/antenna=m2 2006.162.07:20:02.01:scan_name=162-0730,k06162,60 2006.162.07:20:02.01:source=3c371,180650.68,694928.1,2000.0,ccw 2006.162.07:20:02.02#antcn#PM 1 00019 2005 228 00 22 31 00 2006.162.07:20:02.02#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.162.07:20:02.02#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.162.07:20:02.02#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.162.07:20:02.02#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.162.07:20:02.02#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.162.07:20:03.14:ready_k5 2006.162.07:20:03.14&ready_k5/obsinfo=st 2006.162.07:20:03.14&ready_k5/autoobs=1 2006.162.07:20:03.14&ready_k5/autoobs=2 2006.162.07:20:03.14&ready_k5/autoobs=3 2006.162.07:20:03.14&ready_k5/autoobs=4 2006.162.07:20:03.14&ready_k5/obsinfo 2006.162.07:20:03.15/obsinfo=st/error_log.tmp was not found (or not removed). 2006.162.07:20:03.15#flagr#flagr/antenna,new-source 2006.162.07:20:06.99/autoobs//k5ts1/ autoobs started! 2006.162.07:20:10.35/autoobs//k5ts2/ autoobs started! 2006.162.07:20:13.98/autoobs//k5ts3/ autoobs started! 2006.162.07:20:18.48/autoobs//k5ts4/ autoobs started! 2006.162.07:20:18.51/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.07:20:18.51:4f8m12a=1 2006.162.07:20:18.51&4f8m12a/xlog=on 2006.162.07:20:18.51&4f8m12a/echo=on 2006.162.07:20:18.51&4f8m12a/pcalon 2006.162.07:20:18.51&4f8m12a/"tpicd=stop 2006.162.07:20:18.51&4f8m12a/vc4f8 2006.162.07:20:18.51&4f8m12a/ifd4f 2006.162.07:20:18.51&4f8m12a/"form=m,16.000,1:2 2006.162.07:20:18.51&4f8m12a/"tpicd 2006.162.07:20:18.51&4f8m12a/echo=off 2006.162.07:20:18.51&4f8m12a/xlog=off 2006.162.07:20:18.51$4f8m12a/echo=on 2006.162.07:20:18.51$4f8m12a/pcalon 2006.162.07:20:18.51&pcalon/"no phase cal control is implemented here 2006.162.07:20:18.51$pcalon/"no phase cal control is implemented here 2006.162.07:20:18.51$4f8m12a/"tpicd=stop 2006.162.07:20:18.51$4f8m12a/vc4f8 2006.162.07:20:18.51&vc4f8/valo=1,532.99 2006.162.07:20:18.51&vc4f8/va=1,8 2006.162.07:20:18.51&vc4f8/valo=2,572.99 2006.162.07:20:18.51&vc4f8/va=2,7 2006.162.07:20:18.51&vc4f8/valo=3,672.99 2006.162.07:20:18.51&vc4f8/va=3,6 2006.162.07:20:18.51&vc4f8/valo=4,832.99 2006.162.07:20:18.51&vc4f8/va=4,7 2006.162.07:20:18.51&vc4f8/valo=5,652.99 2006.162.07:20:18.51&vc4f8/va=5,7 2006.162.07:20:18.51&vc4f8/valo=6,772.99 2006.162.07:20:18.51&vc4f8/va=6,6 2006.162.07:20:18.51&vc4f8/valo=7,832.99 2006.162.07:20:18.51&vc4f8/va=7,6 2006.162.07:20:18.51&vc4f8/valo=8,852.99 2006.162.07:20:18.51&vc4f8/va=8,7 2006.162.07:20:18.51&vc4f8/vblo=1,632.99 2006.162.07:20:18.51&vc4f8/vb=1,4 2006.162.07:20:18.51&vc4f8/vblo=2,640.99 2006.162.07:20:18.51&vc4f8/vb=2,4 2006.162.07:20:18.51&vc4f8/vblo=3,656.99 2006.162.07:20:18.51&vc4f8/vb=3,4 2006.162.07:20:18.51&vc4f8/vblo=4,712.99 2006.162.07:20:18.51&vc4f8/vb=4,4 2006.162.07:20:18.51&vc4f8/vblo=5,744.99 2006.162.07:20:18.51&vc4f8/vb=5,4 2006.162.07:20:18.51&vc4f8/vblo=6,752.99 2006.162.07:20:18.51&vc4f8/vb=6,4 2006.162.07:20:18.51&vc4f8/vabw=wide 2006.162.07:20:18.51&vc4f8/vbbw=wide 2006.162.07:20:18.51$vc4f8/valo=1,532.99 2006.162.07:20:18.51#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.162.07:20:18.51#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.162.07:20:18.51#ibcon#ireg 17 cls_cnt 0 2006.162.07:20:18.51#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.162.07:20:18.51#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.162.07:20:18.51#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.162.07:20:18.51#ibcon#enter wrdev, iclass 5, count 0 2006.162.07:20:18.51#ibcon#first serial, iclass 5, count 0 2006.162.07:20:18.51#ibcon#enter sib2, iclass 5, count 0 2006.162.07:20:18.51#ibcon#flushed, iclass 5, count 0 2006.162.07:20:18.51#ibcon#about to write, iclass 5, count 0 2006.162.07:20:18.51#ibcon#wrote, iclass 5, count 0 2006.162.07:20:18.51#ibcon#about to read 3, iclass 5, count 0 2006.162.07:20:18.52#ibcon#read 3, iclass 5, count 0 2006.162.07:20:18.52#ibcon#about to read 4, iclass 5, count 0 2006.162.07:20:18.52#ibcon#read 4, iclass 5, count 0 2006.162.07:20:18.52#ibcon#about to read 5, iclass 5, count 0 2006.162.07:20:18.52#ibcon#read 5, iclass 5, count 0 2006.162.07:20:18.52#ibcon#about to read 6, iclass 5, count 0 2006.162.07:20:18.52#ibcon#read 6, iclass 5, count 0 2006.162.07:20:18.52#ibcon#end of sib2, iclass 5, count 0 2006.162.07:20:18.52#ibcon#*mode == 0, iclass 5, count 0 2006.162.07:20:18.52#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.162.07:20:18.52#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.07:20:18.52#ibcon#*before write, iclass 5, count 0 2006.162.07:20:18.52#ibcon#enter sib2, iclass 5, count 0 2006.162.07:20:18.52#ibcon#flushed, iclass 5, count 0 2006.162.07:20:18.52#ibcon#about to write, iclass 5, count 0 2006.162.07:20:18.52#ibcon#wrote, iclass 5, count 0 2006.162.07:20:18.52#ibcon#about to read 3, iclass 5, count 0 2006.162.07:20:18.57#ibcon#read 3, iclass 5, count 0 2006.162.07:20:18.57#ibcon#about to read 4, iclass 5, count 0 2006.162.07:20:18.57#ibcon#read 4, iclass 5, count 0 2006.162.07:20:18.57#ibcon#about to read 5, iclass 5, count 0 2006.162.07:20:18.57#ibcon#read 5, iclass 5, count 0 2006.162.07:20:18.57#ibcon#about to read 6, iclass 5, count 0 2006.162.07:20:18.57#ibcon#read 6, iclass 5, count 0 2006.162.07:20:18.57#ibcon#end of sib2, iclass 5, count 0 2006.162.07:20:18.57#ibcon#*after write, iclass 5, count 0 2006.162.07:20:18.57#ibcon#*before return 0, iclass 5, count 0 2006.162.07:20:18.57#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.162.07:20:18.57#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.162.07:20:18.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.162.07:20:18.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.162.07:20:18.57$vc4f8/va=1,8 2006.162.07:20:18.57#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.162.07:20:18.57#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.162.07:20:18.57#ibcon#ireg 11 cls_cnt 2 2006.162.07:20:18.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.162.07:20:18.57#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.162.07:20:18.57#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.162.07:20:18.57#ibcon#enter wrdev, iclass 7, count 2 2006.162.07:20:18.57#ibcon#first serial, iclass 7, count 2 2006.162.07:20:18.57#ibcon#enter sib2, iclass 7, count 2 2006.162.07:20:18.57#ibcon#flushed, iclass 7, count 2 2006.162.07:20:18.57#ibcon#about to write, iclass 7, count 2 2006.162.07:20:18.57#ibcon#wrote, iclass 7, count 2 2006.162.07:20:18.57#ibcon#about to read 3, iclass 7, count 2 2006.162.07:20:18.59#ibcon#read 3, iclass 7, count 2 2006.162.07:20:18.59#ibcon#about to read 4, iclass 7, count 2 2006.162.07:20:18.59#ibcon#read 4, iclass 7, count 2 2006.162.07:20:18.59#ibcon#about to read 5, iclass 7, count 2 2006.162.07:20:18.59#ibcon#read 5, iclass 7, count 2 2006.162.07:20:18.59#ibcon#about to read 6, iclass 7, count 2 2006.162.07:20:18.59#ibcon#read 6, iclass 7, count 2 2006.162.07:20:18.59#ibcon#end of sib2, iclass 7, count 2 2006.162.07:20:18.59#ibcon#*mode == 0, iclass 7, count 2 2006.162.07:20:18.59#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.162.07:20:18.59#ibcon#[25=AT01-08\r\n] 2006.162.07:20:18.59#ibcon#*before write, iclass 7, count 2 2006.162.07:20:18.59#ibcon#enter sib2, iclass 7, count 2 2006.162.07:20:18.59#ibcon#flushed, iclass 7, count 2 2006.162.07:20:18.59#ibcon#about to write, iclass 7, count 2 2006.162.07:20:18.59#ibcon#wrote, iclass 7, count 2 2006.162.07:20:18.59#ibcon#about to read 3, iclass 7, count 2 2006.162.07:20:18.62#ibcon#read 3, iclass 7, count 2 2006.162.07:20:18.62#ibcon#about to read 4, iclass 7, count 2 2006.162.07:20:18.62#ibcon#read 4, iclass 7, count 2 2006.162.07:20:18.62#ibcon#about to read 5, iclass 7, count 2 2006.162.07:20:18.62#ibcon#read 5, iclass 7, count 2 2006.162.07:20:18.62#ibcon#about to read 6, iclass 7, count 2 2006.162.07:20:18.62#ibcon#read 6, iclass 7, count 2 2006.162.07:20:18.62#ibcon#end of sib2, iclass 7, count 2 2006.162.07:20:18.62#ibcon#*after write, iclass 7, count 2 2006.162.07:20:18.62#ibcon#*before return 0, iclass 7, count 2 2006.162.07:20:18.62#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.162.07:20:18.62#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.162.07:20:18.62#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.162.07:20:18.62#ibcon#ireg 7 cls_cnt 0 2006.162.07:20:18.62#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.162.07:20:18.75#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.162.07:20:18.75#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.162.07:20:18.75#ibcon#enter wrdev, iclass 7, count 0 2006.162.07:20:18.75#ibcon#first serial, iclass 7, count 0 2006.162.07:20:18.75#ibcon#enter sib2, iclass 7, count 0 2006.162.07:20:18.75#ibcon#flushed, iclass 7, count 0 2006.162.07:20:18.75#ibcon#about to write, iclass 7, count 0 2006.162.07:20:18.75#ibcon#wrote, iclass 7, count 0 2006.162.07:20:18.75#ibcon#about to read 3, iclass 7, count 0 2006.162.07:20:18.76#ibcon#read 3, iclass 7, count 0 2006.162.07:20:18.76#ibcon#about to read 4, iclass 7, count 0 2006.162.07:20:18.76#ibcon#read 4, iclass 7, count 0 2006.162.07:20:18.76#ibcon#about to read 5, iclass 7, count 0 2006.162.07:20:18.76#ibcon#read 5, iclass 7, count 0 2006.162.07:20:18.76#ibcon#about to read 6, iclass 7, count 0 2006.162.07:20:18.76#ibcon#read 6, iclass 7, count 0 2006.162.07:20:18.76#ibcon#end of sib2, iclass 7, count 0 2006.162.07:20:18.76#ibcon#*mode == 0, iclass 7, count 0 2006.162.07:20:18.76#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.162.07:20:18.76#ibcon#[25=USB\r\n] 2006.162.07:20:18.76#ibcon#*before write, iclass 7, count 0 2006.162.07:20:18.76#ibcon#enter sib2, iclass 7, count 0 2006.162.07:20:18.76#ibcon#flushed, iclass 7, count 0 2006.162.07:20:18.76#ibcon#about to write, iclass 7, count 0 2006.162.07:20:18.76#ibcon#wrote, iclass 7, count 0 2006.162.07:20:18.76#ibcon#about to read 3, iclass 7, count 0 2006.162.07:20:18.79#ibcon#read 3, iclass 7, count 0 2006.162.07:20:18.79#ibcon#about to read 4, iclass 7, count 0 2006.162.07:20:18.79#ibcon#read 4, iclass 7, count 0 2006.162.07:20:18.79#ibcon#about to read 5, iclass 7, count 0 2006.162.07:20:18.79#ibcon#read 5, iclass 7, count 0 2006.162.07:20:18.79#ibcon#about to read 6, iclass 7, count 0 2006.162.07:20:18.79#ibcon#read 6, iclass 7, count 0 2006.162.07:20:18.79#ibcon#end of sib2, iclass 7, count 0 2006.162.07:20:18.79#ibcon#*after write, iclass 7, count 0 2006.162.07:20:18.79#ibcon#*before return 0, iclass 7, count 0 2006.162.07:20:18.79#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.162.07:20:18.79#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.162.07:20:18.79#ibcon#about to clear, iclass 7 cls_cnt 0 2006.162.07:20:18.79#ibcon#cleared, iclass 7 cls_cnt 0 2006.162.07:20:18.79$vc4f8/valo=2,572.99 2006.162.07:20:18.79#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.162.07:20:18.79#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.162.07:20:18.79#ibcon#ireg 17 cls_cnt 0 2006.162.07:20:18.79#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.162.07:20:18.79#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.162.07:20:18.79#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.162.07:20:18.79#ibcon#enter wrdev, iclass 11, count 0 2006.162.07:20:18.79#ibcon#first serial, iclass 11, count 0 2006.162.07:20:18.79#ibcon#enter sib2, iclass 11, count 0 2006.162.07:20:18.79#ibcon#flushed, iclass 11, count 0 2006.162.07:20:18.79#ibcon#about to write, iclass 11, count 0 2006.162.07:20:18.79#ibcon#wrote, iclass 11, count 0 2006.162.07:20:18.79#ibcon#about to read 3, iclass 11, count 0 2006.162.07:20:18.81#ibcon#read 3, iclass 11, count 0 2006.162.07:20:18.81#ibcon#about to read 4, iclass 11, count 0 2006.162.07:20:18.81#ibcon#read 4, iclass 11, count 0 2006.162.07:20:18.81#ibcon#about to read 5, iclass 11, count 0 2006.162.07:20:18.81#ibcon#read 5, iclass 11, count 0 2006.162.07:20:18.81#ibcon#about to read 6, iclass 11, count 0 2006.162.07:20:18.81#ibcon#read 6, iclass 11, count 0 2006.162.07:20:18.81#ibcon#end of sib2, iclass 11, count 0 2006.162.07:20:18.81#ibcon#*mode == 0, iclass 11, count 0 2006.162.07:20:18.81#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.162.07:20:18.81#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.07:20:18.81#ibcon#*before write, iclass 11, count 0 2006.162.07:20:18.81#ibcon#enter sib2, iclass 11, count 0 2006.162.07:20:18.81#ibcon#flushed, iclass 11, count 0 2006.162.07:20:18.81#ibcon#about to write, iclass 11, count 0 2006.162.07:20:18.81#ibcon#wrote, iclass 11, count 0 2006.162.07:20:18.81#ibcon#about to read 3, iclass 11, count 0 2006.162.07:20:18.85#ibcon#read 3, iclass 11, count 0 2006.162.07:20:18.85#ibcon#about to read 4, iclass 11, count 0 2006.162.07:20:18.85#ibcon#read 4, iclass 11, count 0 2006.162.07:20:18.85#ibcon#about to read 5, iclass 11, count 0 2006.162.07:20:18.85#ibcon#read 5, iclass 11, count 0 2006.162.07:20:18.85#ibcon#about to read 6, iclass 11, count 0 2006.162.07:20:18.85#ibcon#read 6, iclass 11, count 0 2006.162.07:20:18.85#ibcon#end of sib2, iclass 11, count 0 2006.162.07:20:18.85#ibcon#*after write, iclass 11, count 0 2006.162.07:20:18.85#ibcon#*before return 0, iclass 11, count 0 2006.162.07:20:18.85#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.162.07:20:18.86#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.162.07:20:18.86#ibcon#about to clear, iclass 11 cls_cnt 0 2006.162.07:20:18.86#ibcon#cleared, iclass 11 cls_cnt 0 2006.162.07:20:18.86$vc4f8/va=2,7 2006.162.07:20:18.86#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.162.07:20:18.86#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.162.07:20:18.86#ibcon#ireg 11 cls_cnt 2 2006.162.07:20:18.86#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.162.07:20:18.90#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.162.07:20:18.90#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.162.07:20:18.90#ibcon#enter wrdev, iclass 13, count 2 2006.162.07:20:18.90#ibcon#first serial, iclass 13, count 2 2006.162.07:20:18.90#ibcon#enter sib2, iclass 13, count 2 2006.162.07:20:18.90#ibcon#flushed, iclass 13, count 2 2006.162.07:20:18.90#ibcon#about to write, iclass 13, count 2 2006.162.07:20:18.90#ibcon#wrote, iclass 13, count 2 2006.162.07:20:18.90#ibcon#about to read 3, iclass 13, count 2 2006.162.07:20:18.93#ibcon#read 3, iclass 13, count 2 2006.162.07:20:18.93#ibcon#about to read 4, iclass 13, count 2 2006.162.07:20:18.93#ibcon#read 4, iclass 13, count 2 2006.162.07:20:18.93#ibcon#about to read 5, iclass 13, count 2 2006.162.07:20:18.93#ibcon#read 5, iclass 13, count 2 2006.162.07:20:18.93#ibcon#about to read 6, iclass 13, count 2 2006.162.07:20:18.93#ibcon#read 6, iclass 13, count 2 2006.162.07:20:18.93#ibcon#end of sib2, iclass 13, count 2 2006.162.07:20:18.93#ibcon#*mode == 0, iclass 13, count 2 2006.162.07:20:18.93#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.162.07:20:18.93#ibcon#[25=AT02-07\r\n] 2006.162.07:20:18.93#ibcon#*before write, iclass 13, count 2 2006.162.07:20:18.93#ibcon#enter sib2, iclass 13, count 2 2006.162.07:20:18.93#ibcon#flushed, iclass 13, count 2 2006.162.07:20:18.93#ibcon#about to write, iclass 13, count 2 2006.162.07:20:18.93#ibcon#wrote, iclass 13, count 2 2006.162.07:20:18.93#ibcon#about to read 3, iclass 13, count 2 2006.162.07:20:18.97#ibcon#read 3, iclass 13, count 2 2006.162.07:20:18.97#ibcon#about to read 4, iclass 13, count 2 2006.162.07:20:18.97#ibcon#read 4, iclass 13, count 2 2006.162.07:20:18.97#ibcon#about to read 5, iclass 13, count 2 2006.162.07:20:18.97#ibcon#read 5, iclass 13, count 2 2006.162.07:20:18.97#ibcon#about to read 6, iclass 13, count 2 2006.162.07:20:18.97#ibcon#read 6, iclass 13, count 2 2006.162.07:20:18.97#ibcon#end of sib2, iclass 13, count 2 2006.162.07:20:18.97#ibcon#*after write, iclass 13, count 2 2006.162.07:20:18.97#ibcon#*before return 0, iclass 13, count 2 2006.162.07:20:18.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.162.07:20:18.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.162.07:20:18.97#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.162.07:20:18.97#ibcon#ireg 7 cls_cnt 0 2006.162.07:20:18.97#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.162.07:20:19.08#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.162.07:20:19.08#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.162.07:20:19.08#ibcon#enter wrdev, iclass 13, count 0 2006.162.07:20:19.08#ibcon#first serial, iclass 13, count 0 2006.162.07:20:19.08#ibcon#enter sib2, iclass 13, count 0 2006.162.07:20:19.08#ibcon#flushed, iclass 13, count 0 2006.162.07:20:19.08#ibcon#about to write, iclass 13, count 0 2006.162.07:20:19.08#ibcon#wrote, iclass 13, count 0 2006.162.07:20:19.08#ibcon#about to read 3, iclass 13, count 0 2006.162.07:20:19.10#ibcon#read 3, iclass 13, count 0 2006.162.07:20:19.10#ibcon#about to read 4, iclass 13, count 0 2006.162.07:20:19.10#ibcon#read 4, iclass 13, count 0 2006.162.07:20:19.10#ibcon#about to read 5, iclass 13, count 0 2006.162.07:20:19.10#ibcon#read 5, iclass 13, count 0 2006.162.07:20:19.10#ibcon#about to read 6, iclass 13, count 0 2006.162.07:20:19.10#ibcon#read 6, iclass 13, count 0 2006.162.07:20:19.10#ibcon#end of sib2, iclass 13, count 0 2006.162.07:20:19.10#ibcon#*mode == 0, iclass 13, count 0 2006.162.07:20:19.10#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.162.07:20:19.10#ibcon#[25=USB\r\n] 2006.162.07:20:19.10#ibcon#*before write, iclass 13, count 0 2006.162.07:20:19.10#ibcon#enter sib2, iclass 13, count 0 2006.162.07:20:19.10#ibcon#flushed, iclass 13, count 0 2006.162.07:20:19.10#ibcon#about to write, iclass 13, count 0 2006.162.07:20:19.10#ibcon#wrote, iclass 13, count 0 2006.162.07:20:19.10#ibcon#about to read 3, iclass 13, count 0 2006.162.07:20:19.13#ibcon#read 3, iclass 13, count 0 2006.162.07:20:19.13#ibcon#about to read 4, iclass 13, count 0 2006.162.07:20:19.13#ibcon#read 4, iclass 13, count 0 2006.162.07:20:19.13#ibcon#about to read 5, iclass 13, count 0 2006.162.07:20:19.13#ibcon#read 5, iclass 13, count 0 2006.162.07:20:19.13#ibcon#about to read 6, iclass 13, count 0 2006.162.07:20:19.13#ibcon#read 6, iclass 13, count 0 2006.162.07:20:19.13#ibcon#end of sib2, iclass 13, count 0 2006.162.07:20:19.13#ibcon#*after write, iclass 13, count 0 2006.162.07:20:19.13#ibcon#*before return 0, iclass 13, count 0 2006.162.07:20:19.13#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.162.07:20:19.13#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.162.07:20:19.13#ibcon#about to clear, iclass 13 cls_cnt 0 2006.162.07:20:19.13#ibcon#cleared, iclass 13 cls_cnt 0 2006.162.07:20:19.13$vc4f8/valo=3,672.99 2006.162.07:20:19.13#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.162.07:20:19.13#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.162.07:20:19.13#ibcon#ireg 17 cls_cnt 0 2006.162.07:20:19.13#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:20:19.13#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:20:19.13#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:20:19.13#ibcon#enter wrdev, iclass 15, count 0 2006.162.07:20:19.13#ibcon#first serial, iclass 15, count 0 2006.162.07:20:19.13#ibcon#enter sib2, iclass 15, count 0 2006.162.07:20:19.13#ibcon#flushed, iclass 15, count 0 2006.162.07:20:19.13#ibcon#about to write, iclass 15, count 0 2006.162.07:20:19.13#ibcon#wrote, iclass 15, count 0 2006.162.07:20:19.13#ibcon#about to read 3, iclass 15, count 0 2006.162.07:20:19.15#ibcon#read 3, iclass 15, count 0 2006.162.07:20:19.15#ibcon#about to read 4, iclass 15, count 0 2006.162.07:20:19.15#ibcon#read 4, iclass 15, count 0 2006.162.07:20:19.15#ibcon#about to read 5, iclass 15, count 0 2006.162.07:20:19.15#ibcon#read 5, iclass 15, count 0 2006.162.07:20:19.15#ibcon#about to read 6, iclass 15, count 0 2006.162.07:20:19.15#ibcon#read 6, iclass 15, count 0 2006.162.07:20:19.15#ibcon#end of sib2, iclass 15, count 0 2006.162.07:20:19.15#ibcon#*mode == 0, iclass 15, count 0 2006.162.07:20:19.15#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.162.07:20:19.15#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.07:20:19.15#ibcon#*before write, iclass 15, count 0 2006.162.07:20:19.15#ibcon#enter sib2, iclass 15, count 0 2006.162.07:20:19.15#ibcon#flushed, iclass 15, count 0 2006.162.07:20:19.15#ibcon#about to write, iclass 15, count 0 2006.162.07:20:19.15#ibcon#wrote, iclass 15, count 0 2006.162.07:20:19.15#ibcon#about to read 3, iclass 15, count 0 2006.162.07:20:19.19#ibcon#read 3, iclass 15, count 0 2006.162.07:20:19.19#ibcon#about to read 4, iclass 15, count 0 2006.162.07:20:19.19#ibcon#read 4, iclass 15, count 0 2006.162.07:20:19.19#ibcon#about to read 5, iclass 15, count 0 2006.162.07:20:19.19#ibcon#read 5, iclass 15, count 0 2006.162.07:20:19.19#ibcon#about to read 6, iclass 15, count 0 2006.162.07:20:19.19#ibcon#read 6, iclass 15, count 0 2006.162.07:20:19.19#ibcon#end of sib2, iclass 15, count 0 2006.162.07:20:19.19#ibcon#*after write, iclass 15, count 0 2006.162.07:20:19.19#ibcon#*before return 0, iclass 15, count 0 2006.162.07:20:19.20#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:20:19.20#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:20:19.20#ibcon#about to clear, iclass 15 cls_cnt 0 2006.162.07:20:19.20#ibcon#cleared, iclass 15 cls_cnt 0 2006.162.07:20:19.20$vc4f8/va=3,6 2006.162.07:20:19.20#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.162.07:20:19.20#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.162.07:20:19.20#ibcon#ireg 11 cls_cnt 2 2006.162.07:20:19.20#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:20:19.24#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:20:19.24#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:20:19.24#ibcon#enter wrdev, iclass 17, count 2 2006.162.07:20:19.24#ibcon#first serial, iclass 17, count 2 2006.162.07:20:19.24#ibcon#enter sib2, iclass 17, count 2 2006.162.07:20:19.24#ibcon#flushed, iclass 17, count 2 2006.162.07:20:19.24#ibcon#about to write, iclass 17, count 2 2006.162.07:20:19.24#ibcon#wrote, iclass 17, count 2 2006.162.07:20:19.24#ibcon#about to read 3, iclass 17, count 2 2006.162.07:20:19.27#ibcon#read 3, iclass 17, count 2 2006.162.07:20:19.27#ibcon#about to read 4, iclass 17, count 2 2006.162.07:20:19.27#ibcon#read 4, iclass 17, count 2 2006.162.07:20:19.27#ibcon#about to read 5, iclass 17, count 2 2006.162.07:20:19.27#ibcon#read 5, iclass 17, count 2 2006.162.07:20:19.27#ibcon#about to read 6, iclass 17, count 2 2006.162.07:20:19.27#ibcon#read 6, iclass 17, count 2 2006.162.07:20:19.27#ibcon#end of sib2, iclass 17, count 2 2006.162.07:20:19.27#ibcon#*mode == 0, iclass 17, count 2 2006.162.07:20:19.27#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.162.07:20:19.27#ibcon#[25=AT03-06\r\n] 2006.162.07:20:19.27#ibcon#*before write, iclass 17, count 2 2006.162.07:20:19.27#ibcon#enter sib2, iclass 17, count 2 2006.162.07:20:19.27#ibcon#flushed, iclass 17, count 2 2006.162.07:20:19.27#ibcon#about to write, iclass 17, count 2 2006.162.07:20:19.27#ibcon#wrote, iclass 17, count 2 2006.162.07:20:19.27#ibcon#about to read 3, iclass 17, count 2 2006.162.07:20:19.30#ibcon#read 3, iclass 17, count 2 2006.162.07:20:19.30#ibcon#about to read 4, iclass 17, count 2 2006.162.07:20:19.30#ibcon#read 4, iclass 17, count 2 2006.162.07:20:19.30#ibcon#about to read 5, iclass 17, count 2 2006.162.07:20:19.30#ibcon#read 5, iclass 17, count 2 2006.162.07:20:19.30#ibcon#about to read 6, iclass 17, count 2 2006.162.07:20:19.30#ibcon#read 6, iclass 17, count 2 2006.162.07:20:19.30#ibcon#end of sib2, iclass 17, count 2 2006.162.07:20:19.30#ibcon#*after write, iclass 17, count 2 2006.162.07:20:19.30#ibcon#*before return 0, iclass 17, count 2 2006.162.07:20:19.30#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:20:19.30#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:20:19.30#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.162.07:20:19.30#ibcon#ireg 7 cls_cnt 0 2006.162.07:20:19.30#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:20:19.42#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:20:19.42#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:20:19.42#ibcon#enter wrdev, iclass 17, count 0 2006.162.07:20:19.42#ibcon#first serial, iclass 17, count 0 2006.162.07:20:19.42#ibcon#enter sib2, iclass 17, count 0 2006.162.07:20:19.42#ibcon#flushed, iclass 17, count 0 2006.162.07:20:19.42#ibcon#about to write, iclass 17, count 0 2006.162.07:20:19.42#ibcon#wrote, iclass 17, count 0 2006.162.07:20:19.42#ibcon#about to read 3, iclass 17, count 0 2006.162.07:20:19.44#ibcon#read 3, iclass 17, count 0 2006.162.07:20:19.44#ibcon#about to read 4, iclass 17, count 0 2006.162.07:20:19.44#ibcon#read 4, iclass 17, count 0 2006.162.07:20:19.44#ibcon#about to read 5, iclass 17, count 0 2006.162.07:20:19.44#ibcon#read 5, iclass 17, count 0 2006.162.07:20:19.44#ibcon#about to read 6, iclass 17, count 0 2006.162.07:20:19.44#ibcon#read 6, iclass 17, count 0 2006.162.07:20:19.44#ibcon#end of sib2, iclass 17, count 0 2006.162.07:20:19.44#ibcon#*mode == 0, iclass 17, count 0 2006.162.07:20:19.44#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.162.07:20:19.44#ibcon#[25=USB\r\n] 2006.162.07:20:19.44#ibcon#*before write, iclass 17, count 0 2006.162.07:20:19.44#ibcon#enter sib2, iclass 17, count 0 2006.162.07:20:19.44#ibcon#flushed, iclass 17, count 0 2006.162.07:20:19.44#ibcon#about to write, iclass 17, count 0 2006.162.07:20:19.44#ibcon#wrote, iclass 17, count 0 2006.162.07:20:19.44#ibcon#about to read 3, iclass 17, count 0 2006.162.07:20:19.47#ibcon#read 3, iclass 17, count 0 2006.162.07:20:19.47#ibcon#about to read 4, iclass 17, count 0 2006.162.07:20:19.47#ibcon#read 4, iclass 17, count 0 2006.162.07:20:19.47#ibcon#about to read 5, iclass 17, count 0 2006.162.07:20:19.47#ibcon#read 5, iclass 17, count 0 2006.162.07:20:19.47#ibcon#about to read 6, iclass 17, count 0 2006.162.07:20:19.47#ibcon#read 6, iclass 17, count 0 2006.162.07:20:19.47#ibcon#end of sib2, iclass 17, count 0 2006.162.07:20:19.47#ibcon#*after write, iclass 17, count 0 2006.162.07:20:19.47#ibcon#*before return 0, iclass 17, count 0 2006.162.07:20:19.47#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:20:19.47#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:20:19.47#ibcon#about to clear, iclass 17 cls_cnt 0 2006.162.07:20:19.47#ibcon#cleared, iclass 17 cls_cnt 0 2006.162.07:20:19.47$vc4f8/valo=4,832.99 2006.162.07:20:19.47#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.162.07:20:19.47#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.162.07:20:19.47#ibcon#ireg 17 cls_cnt 0 2006.162.07:20:19.47#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:20:19.47#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:20:19.47#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:20:19.47#ibcon#enter wrdev, iclass 19, count 0 2006.162.07:20:19.47#ibcon#first serial, iclass 19, count 0 2006.162.07:20:19.47#ibcon#enter sib2, iclass 19, count 0 2006.162.07:20:19.47#ibcon#flushed, iclass 19, count 0 2006.162.07:20:19.47#ibcon#about to write, iclass 19, count 0 2006.162.07:20:19.47#ibcon#wrote, iclass 19, count 0 2006.162.07:20:19.47#ibcon#about to read 3, iclass 19, count 0 2006.162.07:20:19.49#ibcon#read 3, iclass 19, count 0 2006.162.07:20:19.49#ibcon#about to read 4, iclass 19, count 0 2006.162.07:20:19.49#ibcon#read 4, iclass 19, count 0 2006.162.07:20:19.49#ibcon#about to read 5, iclass 19, count 0 2006.162.07:20:19.49#ibcon#read 5, iclass 19, count 0 2006.162.07:20:19.49#ibcon#about to read 6, iclass 19, count 0 2006.162.07:20:19.49#ibcon#read 6, iclass 19, count 0 2006.162.07:20:19.49#ibcon#end of sib2, iclass 19, count 0 2006.162.07:20:19.49#ibcon#*mode == 0, iclass 19, count 0 2006.162.07:20:19.49#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.162.07:20:19.49#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.07:20:19.49#ibcon#*before write, iclass 19, count 0 2006.162.07:20:19.49#ibcon#enter sib2, iclass 19, count 0 2006.162.07:20:19.49#ibcon#flushed, iclass 19, count 0 2006.162.07:20:19.49#ibcon#about to write, iclass 19, count 0 2006.162.07:20:19.49#ibcon#wrote, iclass 19, count 0 2006.162.07:20:19.49#ibcon#about to read 3, iclass 19, count 0 2006.162.07:20:19.53#ibcon#read 3, iclass 19, count 0 2006.162.07:20:19.53#ibcon#about to read 4, iclass 19, count 0 2006.162.07:20:19.53#ibcon#read 4, iclass 19, count 0 2006.162.07:20:19.53#ibcon#about to read 5, iclass 19, count 0 2006.162.07:20:19.53#ibcon#read 5, iclass 19, count 0 2006.162.07:20:19.53#ibcon#about to read 6, iclass 19, count 0 2006.162.07:20:19.53#ibcon#read 6, iclass 19, count 0 2006.162.07:20:19.53#ibcon#end of sib2, iclass 19, count 0 2006.162.07:20:19.53#ibcon#*after write, iclass 19, count 0 2006.162.07:20:19.53#ibcon#*before return 0, iclass 19, count 0 2006.162.07:20:19.53#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:20:19.53#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:20:19.53#ibcon#about to clear, iclass 19 cls_cnt 0 2006.162.07:20:19.53#ibcon#cleared, iclass 19 cls_cnt 0 2006.162.07:20:19.53$vc4f8/va=4,7 2006.162.07:20:19.53#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.162.07:20:19.53#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.162.07:20:19.53#ibcon#ireg 11 cls_cnt 2 2006.162.07:20:19.53#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:20:19.59#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:20:19.59#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:20:19.59#ibcon#enter wrdev, iclass 21, count 2 2006.162.07:20:19.59#ibcon#first serial, iclass 21, count 2 2006.162.07:20:19.59#ibcon#enter sib2, iclass 21, count 2 2006.162.07:20:19.59#ibcon#flushed, iclass 21, count 2 2006.162.07:20:19.59#ibcon#about to write, iclass 21, count 2 2006.162.07:20:19.59#ibcon#wrote, iclass 21, count 2 2006.162.07:20:19.59#ibcon#about to read 3, iclass 21, count 2 2006.162.07:20:19.61#ibcon#read 3, iclass 21, count 2 2006.162.07:20:19.61#ibcon#about to read 4, iclass 21, count 2 2006.162.07:20:19.61#ibcon#read 4, iclass 21, count 2 2006.162.07:20:19.61#ibcon#about to read 5, iclass 21, count 2 2006.162.07:20:19.61#ibcon#read 5, iclass 21, count 2 2006.162.07:20:19.61#ibcon#about to read 6, iclass 21, count 2 2006.162.07:20:19.61#ibcon#read 6, iclass 21, count 2 2006.162.07:20:19.61#ibcon#end of sib2, iclass 21, count 2 2006.162.07:20:19.61#ibcon#*mode == 0, iclass 21, count 2 2006.162.07:20:19.61#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.162.07:20:19.61#ibcon#[25=AT04-07\r\n] 2006.162.07:20:19.61#ibcon#*before write, iclass 21, count 2 2006.162.07:20:19.61#ibcon#enter sib2, iclass 21, count 2 2006.162.07:20:19.61#ibcon#flushed, iclass 21, count 2 2006.162.07:20:19.61#ibcon#about to write, iclass 21, count 2 2006.162.07:20:19.61#ibcon#wrote, iclass 21, count 2 2006.162.07:20:19.61#ibcon#about to read 3, iclass 21, count 2 2006.162.07:20:19.64#ibcon#read 3, iclass 21, count 2 2006.162.07:20:19.64#ibcon#about to read 4, iclass 21, count 2 2006.162.07:20:19.64#ibcon#read 4, iclass 21, count 2 2006.162.07:20:19.64#ibcon#about to read 5, iclass 21, count 2 2006.162.07:20:19.64#ibcon#read 5, iclass 21, count 2 2006.162.07:20:19.64#ibcon#about to read 6, iclass 21, count 2 2006.162.07:20:19.64#ibcon#read 6, iclass 21, count 2 2006.162.07:20:19.64#ibcon#end of sib2, iclass 21, count 2 2006.162.07:20:19.64#ibcon#*after write, iclass 21, count 2 2006.162.07:20:19.64#ibcon#*before return 0, iclass 21, count 2 2006.162.07:20:19.64#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:20:19.64#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:20:19.64#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.162.07:20:19.64#ibcon#ireg 7 cls_cnt 0 2006.162.07:20:19.64#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:20:19.76#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:20:19.76#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:20:19.76#ibcon#enter wrdev, iclass 21, count 0 2006.162.07:20:19.76#ibcon#first serial, iclass 21, count 0 2006.162.07:20:19.76#ibcon#enter sib2, iclass 21, count 0 2006.162.07:20:19.76#ibcon#flushed, iclass 21, count 0 2006.162.07:20:19.76#ibcon#about to write, iclass 21, count 0 2006.162.07:20:19.76#ibcon#wrote, iclass 21, count 0 2006.162.07:20:19.76#ibcon#about to read 3, iclass 21, count 0 2006.162.07:20:19.78#ibcon#read 3, iclass 21, count 0 2006.162.07:20:19.78#ibcon#about to read 4, iclass 21, count 0 2006.162.07:20:19.78#ibcon#read 4, iclass 21, count 0 2006.162.07:20:19.78#ibcon#about to read 5, iclass 21, count 0 2006.162.07:20:19.78#ibcon#read 5, iclass 21, count 0 2006.162.07:20:19.78#ibcon#about to read 6, iclass 21, count 0 2006.162.07:20:19.78#ibcon#read 6, iclass 21, count 0 2006.162.07:20:19.78#ibcon#end of sib2, iclass 21, count 0 2006.162.07:20:19.78#ibcon#*mode == 0, iclass 21, count 0 2006.162.07:20:19.78#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.162.07:20:19.78#ibcon#[25=USB\r\n] 2006.162.07:20:19.78#ibcon#*before write, iclass 21, count 0 2006.162.07:20:19.78#ibcon#enter sib2, iclass 21, count 0 2006.162.07:20:19.78#ibcon#flushed, iclass 21, count 0 2006.162.07:20:19.78#ibcon#about to write, iclass 21, count 0 2006.162.07:20:19.78#ibcon#wrote, iclass 21, count 0 2006.162.07:20:19.78#ibcon#about to read 3, iclass 21, count 0 2006.162.07:20:19.81#ibcon#read 3, iclass 21, count 0 2006.162.07:20:19.81#ibcon#about to read 4, iclass 21, count 0 2006.162.07:20:19.81#ibcon#read 4, iclass 21, count 0 2006.162.07:20:19.81#ibcon#about to read 5, iclass 21, count 0 2006.162.07:20:19.81#ibcon#read 5, iclass 21, count 0 2006.162.07:20:19.81#ibcon#about to read 6, iclass 21, count 0 2006.162.07:20:19.81#ibcon#read 6, iclass 21, count 0 2006.162.07:20:19.81#ibcon#end of sib2, iclass 21, count 0 2006.162.07:20:19.81#ibcon#*after write, iclass 21, count 0 2006.162.07:20:19.81#ibcon#*before return 0, iclass 21, count 0 2006.162.07:20:19.81#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:20:19.81#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:20:19.81#ibcon#about to clear, iclass 21 cls_cnt 0 2006.162.07:20:19.81#ibcon#cleared, iclass 21 cls_cnt 0 2006.162.07:20:19.81$vc4f8/valo=5,652.99 2006.162.07:20:19.81#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.162.07:20:19.81#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.162.07:20:19.81#ibcon#ireg 17 cls_cnt 0 2006.162.07:20:19.81#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:20:19.81#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:20:19.81#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:20:19.81#ibcon#enter wrdev, iclass 23, count 0 2006.162.07:20:19.81#ibcon#first serial, iclass 23, count 0 2006.162.07:20:19.81#ibcon#enter sib2, iclass 23, count 0 2006.162.07:20:19.81#ibcon#flushed, iclass 23, count 0 2006.162.07:20:19.81#ibcon#about to write, iclass 23, count 0 2006.162.07:20:19.81#ibcon#wrote, iclass 23, count 0 2006.162.07:20:19.81#ibcon#about to read 3, iclass 23, count 0 2006.162.07:20:19.83#ibcon#read 3, iclass 23, count 0 2006.162.07:20:19.83#ibcon#about to read 4, iclass 23, count 0 2006.162.07:20:19.83#ibcon#read 4, iclass 23, count 0 2006.162.07:20:19.83#ibcon#about to read 5, iclass 23, count 0 2006.162.07:20:19.83#ibcon#read 5, iclass 23, count 0 2006.162.07:20:19.83#ibcon#about to read 6, iclass 23, count 0 2006.162.07:20:19.83#ibcon#read 6, iclass 23, count 0 2006.162.07:20:19.83#ibcon#end of sib2, iclass 23, count 0 2006.162.07:20:19.83#ibcon#*mode == 0, iclass 23, count 0 2006.162.07:20:19.83#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.162.07:20:19.83#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.07:20:19.83#ibcon#*before write, iclass 23, count 0 2006.162.07:20:19.83#ibcon#enter sib2, iclass 23, count 0 2006.162.07:20:19.83#ibcon#flushed, iclass 23, count 0 2006.162.07:20:19.83#ibcon#about to write, iclass 23, count 0 2006.162.07:20:19.83#ibcon#wrote, iclass 23, count 0 2006.162.07:20:19.83#ibcon#about to read 3, iclass 23, count 0 2006.162.07:20:19.87#ibcon#read 3, iclass 23, count 0 2006.162.07:20:19.87#ibcon#about to read 4, iclass 23, count 0 2006.162.07:20:19.87#ibcon#read 4, iclass 23, count 0 2006.162.07:20:19.87#ibcon#about to read 5, iclass 23, count 0 2006.162.07:20:19.87#ibcon#read 5, iclass 23, count 0 2006.162.07:20:19.87#ibcon#about to read 6, iclass 23, count 0 2006.162.07:20:19.87#ibcon#read 6, iclass 23, count 0 2006.162.07:20:19.87#ibcon#end of sib2, iclass 23, count 0 2006.162.07:20:19.87#ibcon#*after write, iclass 23, count 0 2006.162.07:20:19.87#ibcon#*before return 0, iclass 23, count 0 2006.162.07:20:19.87#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:20:19.87#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:20:19.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.162.07:20:19.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.162.07:20:19.87$vc4f8/va=5,7 2006.162.07:20:19.87#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.162.07:20:19.87#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.162.07:20:19.87#ibcon#ireg 11 cls_cnt 2 2006.162.07:20:19.87#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.162.07:20:19.93#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.162.07:20:19.93#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.162.07:20:19.93#ibcon#enter wrdev, iclass 25, count 2 2006.162.07:20:19.93#ibcon#first serial, iclass 25, count 2 2006.162.07:20:19.93#ibcon#enter sib2, iclass 25, count 2 2006.162.07:20:19.93#ibcon#flushed, iclass 25, count 2 2006.162.07:20:19.93#ibcon#about to write, iclass 25, count 2 2006.162.07:20:19.93#ibcon#wrote, iclass 25, count 2 2006.162.07:20:19.93#ibcon#about to read 3, iclass 25, count 2 2006.162.07:20:19.95#ibcon#read 3, iclass 25, count 2 2006.162.07:20:19.95#ibcon#about to read 4, iclass 25, count 2 2006.162.07:20:19.95#ibcon#read 4, iclass 25, count 2 2006.162.07:20:19.95#ibcon#about to read 5, iclass 25, count 2 2006.162.07:20:19.95#ibcon#read 5, iclass 25, count 2 2006.162.07:20:19.95#ibcon#about to read 6, iclass 25, count 2 2006.162.07:20:19.95#ibcon#read 6, iclass 25, count 2 2006.162.07:20:19.95#ibcon#end of sib2, iclass 25, count 2 2006.162.07:20:19.95#ibcon#*mode == 0, iclass 25, count 2 2006.162.07:20:19.95#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.162.07:20:19.95#ibcon#[25=AT05-07\r\n] 2006.162.07:20:19.95#ibcon#*before write, iclass 25, count 2 2006.162.07:20:19.95#ibcon#enter sib2, iclass 25, count 2 2006.162.07:20:19.95#ibcon#flushed, iclass 25, count 2 2006.162.07:20:19.95#ibcon#about to write, iclass 25, count 2 2006.162.07:20:19.95#ibcon#wrote, iclass 25, count 2 2006.162.07:20:19.95#ibcon#about to read 3, iclass 25, count 2 2006.162.07:20:19.98#ibcon#read 3, iclass 25, count 2 2006.162.07:20:19.98#ibcon#about to read 4, iclass 25, count 2 2006.162.07:20:19.98#ibcon#read 4, iclass 25, count 2 2006.162.07:20:19.98#ibcon#about to read 5, iclass 25, count 2 2006.162.07:20:19.98#ibcon#read 5, iclass 25, count 2 2006.162.07:20:19.98#ibcon#about to read 6, iclass 25, count 2 2006.162.07:20:19.98#ibcon#read 6, iclass 25, count 2 2006.162.07:20:19.98#ibcon#end of sib2, iclass 25, count 2 2006.162.07:20:19.98#ibcon#*after write, iclass 25, count 2 2006.162.07:20:19.98#ibcon#*before return 0, iclass 25, count 2 2006.162.07:20:19.98#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.162.07:20:19.98#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.162.07:20:19.98#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.162.07:20:19.98#ibcon#ireg 7 cls_cnt 0 2006.162.07:20:19.98#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.162.07:20:20.10#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.162.07:20:20.10#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.162.07:20:20.10#ibcon#enter wrdev, iclass 25, count 0 2006.162.07:20:20.10#ibcon#first serial, iclass 25, count 0 2006.162.07:20:20.10#ibcon#enter sib2, iclass 25, count 0 2006.162.07:20:20.10#ibcon#flushed, iclass 25, count 0 2006.162.07:20:20.10#ibcon#about to write, iclass 25, count 0 2006.162.07:20:20.10#ibcon#wrote, iclass 25, count 0 2006.162.07:20:20.10#ibcon#about to read 3, iclass 25, count 0 2006.162.07:20:20.12#ibcon#read 3, iclass 25, count 0 2006.162.07:20:20.12#ibcon#about to read 4, iclass 25, count 0 2006.162.07:20:20.12#ibcon#read 4, iclass 25, count 0 2006.162.07:20:20.12#ibcon#about to read 5, iclass 25, count 0 2006.162.07:20:20.12#ibcon#read 5, iclass 25, count 0 2006.162.07:20:20.12#ibcon#about to read 6, iclass 25, count 0 2006.162.07:20:20.12#ibcon#read 6, iclass 25, count 0 2006.162.07:20:20.12#ibcon#end of sib2, iclass 25, count 0 2006.162.07:20:20.12#ibcon#*mode == 0, iclass 25, count 0 2006.162.07:20:20.12#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.162.07:20:20.12#ibcon#[25=USB\r\n] 2006.162.07:20:20.12#ibcon#*before write, iclass 25, count 0 2006.162.07:20:20.12#ibcon#enter sib2, iclass 25, count 0 2006.162.07:20:20.12#ibcon#flushed, iclass 25, count 0 2006.162.07:20:20.12#ibcon#about to write, iclass 25, count 0 2006.162.07:20:20.12#ibcon#wrote, iclass 25, count 0 2006.162.07:20:20.12#ibcon#about to read 3, iclass 25, count 0 2006.162.07:20:20.15#ibcon#read 3, iclass 25, count 0 2006.162.07:20:20.15#ibcon#about to read 4, iclass 25, count 0 2006.162.07:20:20.15#ibcon#read 4, iclass 25, count 0 2006.162.07:20:20.15#ibcon#about to read 5, iclass 25, count 0 2006.162.07:20:20.15#ibcon#read 5, iclass 25, count 0 2006.162.07:20:20.15#ibcon#about to read 6, iclass 25, count 0 2006.162.07:20:20.15#ibcon#read 6, iclass 25, count 0 2006.162.07:20:20.15#ibcon#end of sib2, iclass 25, count 0 2006.162.07:20:20.15#ibcon#*after write, iclass 25, count 0 2006.162.07:20:20.15#ibcon#*before return 0, iclass 25, count 0 2006.162.07:20:20.15#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.162.07:20:20.15#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.162.07:20:20.15#ibcon#about to clear, iclass 25 cls_cnt 0 2006.162.07:20:20.15#ibcon#cleared, iclass 25 cls_cnt 0 2006.162.07:20:20.15$vc4f8/valo=6,772.99 2006.162.07:20:20.15#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.162.07:20:20.15#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.162.07:20:20.15#ibcon#ireg 17 cls_cnt 0 2006.162.07:20:20.15#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:20:20.15#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:20:20.15#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:20:20.15#ibcon#enter wrdev, iclass 27, count 0 2006.162.07:20:20.15#ibcon#first serial, iclass 27, count 0 2006.162.07:20:20.15#ibcon#enter sib2, iclass 27, count 0 2006.162.07:20:20.15#ibcon#flushed, iclass 27, count 0 2006.162.07:20:20.15#ibcon#about to write, iclass 27, count 0 2006.162.07:20:20.15#ibcon#wrote, iclass 27, count 0 2006.162.07:20:20.15#ibcon#about to read 3, iclass 27, count 0 2006.162.07:20:20.18#ibcon#read 3, iclass 27, count 0 2006.162.07:20:20.18#ibcon#about to read 4, iclass 27, count 0 2006.162.07:20:20.18#ibcon#read 4, iclass 27, count 0 2006.162.07:20:20.18#ibcon#about to read 5, iclass 27, count 0 2006.162.07:20:20.18#ibcon#read 5, iclass 27, count 0 2006.162.07:20:20.18#ibcon#about to read 6, iclass 27, count 0 2006.162.07:20:20.18#ibcon#read 6, iclass 27, count 0 2006.162.07:20:20.18#ibcon#end of sib2, iclass 27, count 0 2006.162.07:20:20.18#ibcon#*mode == 0, iclass 27, count 0 2006.162.07:20:20.18#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.162.07:20:20.18#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.07:20:20.18#ibcon#*before write, iclass 27, count 0 2006.162.07:20:20.18#ibcon#enter sib2, iclass 27, count 0 2006.162.07:20:20.18#ibcon#flushed, iclass 27, count 0 2006.162.07:20:20.18#ibcon#about to write, iclass 27, count 0 2006.162.07:20:20.18#ibcon#wrote, iclass 27, count 0 2006.162.07:20:20.18#ibcon#about to read 3, iclass 27, count 0 2006.162.07:20:20.22#ibcon#read 3, iclass 27, count 0 2006.162.07:20:20.22#ibcon#about to read 4, iclass 27, count 0 2006.162.07:20:20.22#ibcon#read 4, iclass 27, count 0 2006.162.07:20:20.22#ibcon#about to read 5, iclass 27, count 0 2006.162.07:20:20.22#ibcon#read 5, iclass 27, count 0 2006.162.07:20:20.22#ibcon#about to read 6, iclass 27, count 0 2006.162.07:20:20.22#ibcon#read 6, iclass 27, count 0 2006.162.07:20:20.22#ibcon#end of sib2, iclass 27, count 0 2006.162.07:20:20.22#ibcon#*after write, iclass 27, count 0 2006.162.07:20:20.22#ibcon#*before return 0, iclass 27, count 0 2006.162.07:20:20.22#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:20:20.22#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:20:20.22#ibcon#about to clear, iclass 27 cls_cnt 0 2006.162.07:20:20.22#ibcon#cleared, iclass 27 cls_cnt 0 2006.162.07:20:20.22$vc4f8/va=6,6 2006.162.07:20:20.22#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.162.07:20:20.22#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.162.07:20:20.22#ibcon#ireg 11 cls_cnt 2 2006.162.07:20:20.22#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.162.07:20:20.27#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.162.07:20:20.27#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.162.07:20:20.27#ibcon#enter wrdev, iclass 29, count 2 2006.162.07:20:20.27#ibcon#first serial, iclass 29, count 2 2006.162.07:20:20.27#ibcon#enter sib2, iclass 29, count 2 2006.162.07:20:20.27#ibcon#flushed, iclass 29, count 2 2006.162.07:20:20.27#ibcon#about to write, iclass 29, count 2 2006.162.07:20:20.27#ibcon#wrote, iclass 29, count 2 2006.162.07:20:20.27#ibcon#about to read 3, iclass 29, count 2 2006.162.07:20:20.29#ibcon#read 3, iclass 29, count 2 2006.162.07:20:20.29#ibcon#about to read 4, iclass 29, count 2 2006.162.07:20:20.29#ibcon#read 4, iclass 29, count 2 2006.162.07:20:20.29#ibcon#about to read 5, iclass 29, count 2 2006.162.07:20:20.29#ibcon#read 5, iclass 29, count 2 2006.162.07:20:20.29#ibcon#about to read 6, iclass 29, count 2 2006.162.07:20:20.29#ibcon#read 6, iclass 29, count 2 2006.162.07:20:20.29#ibcon#end of sib2, iclass 29, count 2 2006.162.07:20:20.29#ibcon#*mode == 0, iclass 29, count 2 2006.162.07:20:20.29#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.162.07:20:20.29#ibcon#[25=AT06-06\r\n] 2006.162.07:20:20.29#ibcon#*before write, iclass 29, count 2 2006.162.07:20:20.29#ibcon#enter sib2, iclass 29, count 2 2006.162.07:20:20.29#ibcon#flushed, iclass 29, count 2 2006.162.07:20:20.29#ibcon#about to write, iclass 29, count 2 2006.162.07:20:20.29#ibcon#wrote, iclass 29, count 2 2006.162.07:20:20.29#ibcon#about to read 3, iclass 29, count 2 2006.162.07:20:20.32#ibcon#read 3, iclass 29, count 2 2006.162.07:20:20.32#ibcon#about to read 4, iclass 29, count 2 2006.162.07:20:20.32#ibcon#read 4, iclass 29, count 2 2006.162.07:20:20.32#ibcon#about to read 5, iclass 29, count 2 2006.162.07:20:20.32#ibcon#read 5, iclass 29, count 2 2006.162.07:20:20.32#ibcon#about to read 6, iclass 29, count 2 2006.162.07:20:20.32#ibcon#read 6, iclass 29, count 2 2006.162.07:20:20.32#ibcon#end of sib2, iclass 29, count 2 2006.162.07:20:20.32#ibcon#*after write, iclass 29, count 2 2006.162.07:20:20.32#ibcon#*before return 0, iclass 29, count 2 2006.162.07:20:20.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.162.07:20:20.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.162.07:20:20.32#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.162.07:20:20.32#ibcon#ireg 7 cls_cnt 0 2006.162.07:20:20.32#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.162.07:20:20.44#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.162.07:20:20.44#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.162.07:20:20.44#ibcon#enter wrdev, iclass 29, count 0 2006.162.07:20:20.44#ibcon#first serial, iclass 29, count 0 2006.162.07:20:20.44#ibcon#enter sib2, iclass 29, count 0 2006.162.07:20:20.44#ibcon#flushed, iclass 29, count 0 2006.162.07:20:20.44#ibcon#about to write, iclass 29, count 0 2006.162.07:20:20.44#ibcon#wrote, iclass 29, count 0 2006.162.07:20:20.44#ibcon#about to read 3, iclass 29, count 0 2006.162.07:20:20.46#ibcon#read 3, iclass 29, count 0 2006.162.07:20:20.46#ibcon#about to read 4, iclass 29, count 0 2006.162.07:20:20.46#ibcon#read 4, iclass 29, count 0 2006.162.07:20:20.46#ibcon#about to read 5, iclass 29, count 0 2006.162.07:20:20.46#ibcon#read 5, iclass 29, count 0 2006.162.07:20:20.46#ibcon#about to read 6, iclass 29, count 0 2006.162.07:20:20.46#ibcon#read 6, iclass 29, count 0 2006.162.07:20:20.46#ibcon#end of sib2, iclass 29, count 0 2006.162.07:20:20.46#ibcon#*mode == 0, iclass 29, count 0 2006.162.07:20:20.46#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.162.07:20:20.46#ibcon#[25=USB\r\n] 2006.162.07:20:20.46#ibcon#*before write, iclass 29, count 0 2006.162.07:20:20.46#ibcon#enter sib2, iclass 29, count 0 2006.162.07:20:20.46#ibcon#flushed, iclass 29, count 0 2006.162.07:20:20.46#ibcon#about to write, iclass 29, count 0 2006.162.07:20:20.46#ibcon#wrote, iclass 29, count 0 2006.162.07:20:20.46#ibcon#about to read 3, iclass 29, count 0 2006.162.07:20:20.49#ibcon#read 3, iclass 29, count 0 2006.162.07:20:20.49#ibcon#about to read 4, iclass 29, count 0 2006.162.07:20:20.49#ibcon#read 4, iclass 29, count 0 2006.162.07:20:20.49#ibcon#about to read 5, iclass 29, count 0 2006.162.07:20:20.49#ibcon#read 5, iclass 29, count 0 2006.162.07:20:20.49#ibcon#about to read 6, iclass 29, count 0 2006.162.07:20:20.49#ibcon#read 6, iclass 29, count 0 2006.162.07:20:20.49#ibcon#end of sib2, iclass 29, count 0 2006.162.07:20:20.49#ibcon#*after write, iclass 29, count 0 2006.162.07:20:20.49#ibcon#*before return 0, iclass 29, count 0 2006.162.07:20:20.49#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.162.07:20:20.49#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.162.07:20:20.49#ibcon#about to clear, iclass 29 cls_cnt 0 2006.162.07:20:20.49#ibcon#cleared, iclass 29 cls_cnt 0 2006.162.07:20:20.49$vc4f8/valo=7,832.99 2006.162.07:20:20.49#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.162.07:20:20.49#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.162.07:20:20.49#ibcon#ireg 17 cls_cnt 0 2006.162.07:20:20.49#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.162.07:20:20.49#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.162.07:20:20.49#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.162.07:20:20.49#ibcon#enter wrdev, iclass 31, count 0 2006.162.07:20:20.49#ibcon#first serial, iclass 31, count 0 2006.162.07:20:20.49#ibcon#enter sib2, iclass 31, count 0 2006.162.07:20:20.49#ibcon#flushed, iclass 31, count 0 2006.162.07:20:20.49#ibcon#about to write, iclass 31, count 0 2006.162.07:20:20.49#ibcon#wrote, iclass 31, count 0 2006.162.07:20:20.49#ibcon#about to read 3, iclass 31, count 0 2006.162.07:20:20.51#ibcon#read 3, iclass 31, count 0 2006.162.07:20:20.51#ibcon#about to read 4, iclass 31, count 0 2006.162.07:20:20.51#ibcon#read 4, iclass 31, count 0 2006.162.07:20:20.51#ibcon#about to read 5, iclass 31, count 0 2006.162.07:20:20.51#ibcon#read 5, iclass 31, count 0 2006.162.07:20:20.51#ibcon#about to read 6, iclass 31, count 0 2006.162.07:20:20.51#ibcon#read 6, iclass 31, count 0 2006.162.07:20:20.51#ibcon#end of sib2, iclass 31, count 0 2006.162.07:20:20.51#ibcon#*mode == 0, iclass 31, count 0 2006.162.07:20:20.51#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.162.07:20:20.51#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.07:20:20.51#ibcon#*before write, iclass 31, count 0 2006.162.07:20:20.51#ibcon#enter sib2, iclass 31, count 0 2006.162.07:20:20.51#ibcon#flushed, iclass 31, count 0 2006.162.07:20:20.51#ibcon#about to write, iclass 31, count 0 2006.162.07:20:20.51#ibcon#wrote, iclass 31, count 0 2006.162.07:20:20.51#ibcon#about to read 3, iclass 31, count 0 2006.162.07:20:20.55#ibcon#read 3, iclass 31, count 0 2006.162.07:20:20.55#ibcon#about to read 4, iclass 31, count 0 2006.162.07:20:20.55#ibcon#read 4, iclass 31, count 0 2006.162.07:20:20.55#ibcon#about to read 5, iclass 31, count 0 2006.162.07:20:20.55#ibcon#read 5, iclass 31, count 0 2006.162.07:20:20.55#ibcon#about to read 6, iclass 31, count 0 2006.162.07:20:20.55#ibcon#read 6, iclass 31, count 0 2006.162.07:20:20.55#ibcon#end of sib2, iclass 31, count 0 2006.162.07:20:20.55#ibcon#*after write, iclass 31, count 0 2006.162.07:20:20.55#ibcon#*before return 0, iclass 31, count 0 2006.162.07:20:20.55#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.162.07:20:20.55#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.162.07:20:20.55#ibcon#about to clear, iclass 31 cls_cnt 0 2006.162.07:20:20.55#ibcon#cleared, iclass 31 cls_cnt 0 2006.162.07:20:20.55$vc4f8/va=7,6 2006.162.07:20:20.55#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.162.07:20:20.55#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.162.07:20:20.55#ibcon#ireg 11 cls_cnt 2 2006.162.07:20:20.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.162.07:20:20.61#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.162.07:20:20.61#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.162.07:20:20.61#ibcon#enter wrdev, iclass 33, count 2 2006.162.07:20:20.61#ibcon#first serial, iclass 33, count 2 2006.162.07:20:20.61#ibcon#enter sib2, iclass 33, count 2 2006.162.07:20:20.61#ibcon#flushed, iclass 33, count 2 2006.162.07:20:20.61#ibcon#about to write, iclass 33, count 2 2006.162.07:20:20.61#ibcon#wrote, iclass 33, count 2 2006.162.07:20:20.61#ibcon#about to read 3, iclass 33, count 2 2006.162.07:20:20.63#ibcon#read 3, iclass 33, count 2 2006.162.07:20:20.63#ibcon#about to read 4, iclass 33, count 2 2006.162.07:20:20.63#ibcon#read 4, iclass 33, count 2 2006.162.07:20:20.63#ibcon#about to read 5, iclass 33, count 2 2006.162.07:20:20.63#ibcon#read 5, iclass 33, count 2 2006.162.07:20:20.63#ibcon#about to read 6, iclass 33, count 2 2006.162.07:20:20.63#ibcon#read 6, iclass 33, count 2 2006.162.07:20:20.63#ibcon#end of sib2, iclass 33, count 2 2006.162.07:20:20.63#ibcon#*mode == 0, iclass 33, count 2 2006.162.07:20:20.63#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.162.07:20:20.63#ibcon#[25=AT07-06\r\n] 2006.162.07:20:20.63#ibcon#*before write, iclass 33, count 2 2006.162.07:20:20.63#ibcon#enter sib2, iclass 33, count 2 2006.162.07:20:20.63#ibcon#flushed, iclass 33, count 2 2006.162.07:20:20.63#ibcon#about to write, iclass 33, count 2 2006.162.07:20:20.63#ibcon#wrote, iclass 33, count 2 2006.162.07:20:20.63#ibcon#about to read 3, iclass 33, count 2 2006.162.07:20:20.66#ibcon#read 3, iclass 33, count 2 2006.162.07:20:20.66#ibcon#about to read 4, iclass 33, count 2 2006.162.07:20:20.66#ibcon#read 4, iclass 33, count 2 2006.162.07:20:20.66#ibcon#about to read 5, iclass 33, count 2 2006.162.07:20:20.66#ibcon#read 5, iclass 33, count 2 2006.162.07:20:20.66#ibcon#about to read 6, iclass 33, count 2 2006.162.07:20:20.66#ibcon#read 6, iclass 33, count 2 2006.162.07:20:20.66#ibcon#end of sib2, iclass 33, count 2 2006.162.07:20:20.66#ibcon#*after write, iclass 33, count 2 2006.162.07:20:20.66#ibcon#*before return 0, iclass 33, count 2 2006.162.07:20:20.66#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.162.07:20:20.66#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.162.07:20:20.66#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.162.07:20:20.66#ibcon#ireg 7 cls_cnt 0 2006.162.07:20:20.66#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.162.07:20:20.78#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.162.07:20:20.78#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.162.07:20:20.78#ibcon#enter wrdev, iclass 33, count 0 2006.162.07:20:20.78#ibcon#first serial, iclass 33, count 0 2006.162.07:20:20.78#ibcon#enter sib2, iclass 33, count 0 2006.162.07:20:20.78#ibcon#flushed, iclass 33, count 0 2006.162.07:20:20.78#ibcon#about to write, iclass 33, count 0 2006.162.07:20:20.78#ibcon#wrote, iclass 33, count 0 2006.162.07:20:20.78#ibcon#about to read 3, iclass 33, count 0 2006.162.07:20:20.80#ibcon#read 3, iclass 33, count 0 2006.162.07:20:20.80#ibcon#about to read 4, iclass 33, count 0 2006.162.07:20:20.80#ibcon#read 4, iclass 33, count 0 2006.162.07:20:20.80#ibcon#about to read 5, iclass 33, count 0 2006.162.07:20:20.80#ibcon#read 5, iclass 33, count 0 2006.162.07:20:20.80#ibcon#about to read 6, iclass 33, count 0 2006.162.07:20:20.80#ibcon#read 6, iclass 33, count 0 2006.162.07:20:20.80#ibcon#end of sib2, iclass 33, count 0 2006.162.07:20:20.80#ibcon#*mode == 0, iclass 33, count 0 2006.162.07:20:20.80#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.162.07:20:20.80#ibcon#[25=USB\r\n] 2006.162.07:20:20.80#ibcon#*before write, iclass 33, count 0 2006.162.07:20:20.80#ibcon#enter sib2, iclass 33, count 0 2006.162.07:20:20.80#ibcon#flushed, iclass 33, count 0 2006.162.07:20:20.80#ibcon#about to write, iclass 33, count 0 2006.162.07:20:20.80#ibcon#wrote, iclass 33, count 0 2006.162.07:20:20.80#ibcon#about to read 3, iclass 33, count 0 2006.162.07:20:20.83#ibcon#read 3, iclass 33, count 0 2006.162.07:20:20.83#ibcon#about to read 4, iclass 33, count 0 2006.162.07:20:20.83#ibcon#read 4, iclass 33, count 0 2006.162.07:20:20.83#ibcon#about to read 5, iclass 33, count 0 2006.162.07:20:20.83#ibcon#read 5, iclass 33, count 0 2006.162.07:20:20.83#ibcon#about to read 6, iclass 33, count 0 2006.162.07:20:20.83#ibcon#read 6, iclass 33, count 0 2006.162.07:20:20.83#ibcon#end of sib2, iclass 33, count 0 2006.162.07:20:20.83#ibcon#*after write, iclass 33, count 0 2006.162.07:20:20.83#ibcon#*before return 0, iclass 33, count 0 2006.162.07:20:20.83#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.162.07:20:20.83#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.162.07:20:20.83#ibcon#about to clear, iclass 33 cls_cnt 0 2006.162.07:20:20.83#ibcon#cleared, iclass 33 cls_cnt 0 2006.162.07:20:20.83$vc4f8/valo=8,852.99 2006.162.07:20:20.83#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.162.07:20:20.83#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.162.07:20:20.83#ibcon#ireg 17 cls_cnt 0 2006.162.07:20:20.83#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.162.07:20:20.83#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.162.07:20:20.83#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.162.07:20:20.83#ibcon#enter wrdev, iclass 35, count 0 2006.162.07:20:20.83#ibcon#first serial, iclass 35, count 0 2006.162.07:20:20.83#ibcon#enter sib2, iclass 35, count 0 2006.162.07:20:20.83#ibcon#flushed, iclass 35, count 0 2006.162.07:20:20.83#ibcon#about to write, iclass 35, count 0 2006.162.07:20:20.83#ibcon#wrote, iclass 35, count 0 2006.162.07:20:20.83#ibcon#about to read 3, iclass 35, count 0 2006.162.07:20:20.85#ibcon#read 3, iclass 35, count 0 2006.162.07:20:20.85#ibcon#about to read 4, iclass 35, count 0 2006.162.07:20:20.85#ibcon#read 4, iclass 35, count 0 2006.162.07:20:20.85#ibcon#about to read 5, iclass 35, count 0 2006.162.07:20:20.85#ibcon#read 5, iclass 35, count 0 2006.162.07:20:20.85#ibcon#about to read 6, iclass 35, count 0 2006.162.07:20:20.85#ibcon#read 6, iclass 35, count 0 2006.162.07:20:20.85#ibcon#end of sib2, iclass 35, count 0 2006.162.07:20:20.85#ibcon#*mode == 0, iclass 35, count 0 2006.162.07:20:20.85#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.162.07:20:20.85#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.07:20:20.85#ibcon#*before write, iclass 35, count 0 2006.162.07:20:20.85#ibcon#enter sib2, iclass 35, count 0 2006.162.07:20:20.85#ibcon#flushed, iclass 35, count 0 2006.162.07:20:20.85#ibcon#about to write, iclass 35, count 0 2006.162.07:20:20.85#ibcon#wrote, iclass 35, count 0 2006.162.07:20:20.85#ibcon#about to read 3, iclass 35, count 0 2006.162.07:20:20.89#ibcon#read 3, iclass 35, count 0 2006.162.07:20:20.89#ibcon#about to read 4, iclass 35, count 0 2006.162.07:20:20.89#ibcon#read 4, iclass 35, count 0 2006.162.07:20:20.89#ibcon#about to read 5, iclass 35, count 0 2006.162.07:20:20.89#ibcon#read 5, iclass 35, count 0 2006.162.07:20:20.89#ibcon#about to read 6, iclass 35, count 0 2006.162.07:20:20.89#ibcon#read 6, iclass 35, count 0 2006.162.07:20:20.89#ibcon#end of sib2, iclass 35, count 0 2006.162.07:20:20.89#ibcon#*after write, iclass 35, count 0 2006.162.07:20:20.89#ibcon#*before return 0, iclass 35, count 0 2006.162.07:20:20.89#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.162.07:20:20.89#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.162.07:20:20.89#ibcon#about to clear, iclass 35 cls_cnt 0 2006.162.07:20:20.89#ibcon#cleared, iclass 35 cls_cnt 0 2006.162.07:20:20.89$vc4f8/va=8,7 2006.162.07:20:20.89#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.162.07:20:20.89#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.162.07:20:20.89#ibcon#ireg 11 cls_cnt 2 2006.162.07:20:20.89#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.162.07:20:20.95#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.162.07:20:20.95#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.162.07:20:20.95#ibcon#enter wrdev, iclass 37, count 2 2006.162.07:20:20.95#ibcon#first serial, iclass 37, count 2 2006.162.07:20:20.95#ibcon#enter sib2, iclass 37, count 2 2006.162.07:20:20.95#ibcon#flushed, iclass 37, count 2 2006.162.07:20:20.95#ibcon#about to write, iclass 37, count 2 2006.162.07:20:20.95#ibcon#wrote, iclass 37, count 2 2006.162.07:20:20.95#ibcon#about to read 3, iclass 37, count 2 2006.162.07:20:20.97#ibcon#read 3, iclass 37, count 2 2006.162.07:20:20.97#ibcon#about to read 4, iclass 37, count 2 2006.162.07:20:20.97#ibcon#read 4, iclass 37, count 2 2006.162.07:20:20.97#ibcon#about to read 5, iclass 37, count 2 2006.162.07:20:20.97#ibcon#read 5, iclass 37, count 2 2006.162.07:20:20.97#ibcon#about to read 6, iclass 37, count 2 2006.162.07:20:20.97#ibcon#read 6, iclass 37, count 2 2006.162.07:20:20.97#ibcon#end of sib2, iclass 37, count 2 2006.162.07:20:20.97#ibcon#*mode == 0, iclass 37, count 2 2006.162.07:20:20.97#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.162.07:20:20.97#ibcon#[25=AT08-07\r\n] 2006.162.07:20:20.97#ibcon#*before write, iclass 37, count 2 2006.162.07:20:20.97#ibcon#enter sib2, iclass 37, count 2 2006.162.07:20:20.97#ibcon#flushed, iclass 37, count 2 2006.162.07:20:20.97#ibcon#about to write, iclass 37, count 2 2006.162.07:20:20.97#ibcon#wrote, iclass 37, count 2 2006.162.07:20:20.97#ibcon#about to read 3, iclass 37, count 2 2006.162.07:20:21.00#ibcon#read 3, iclass 37, count 2 2006.162.07:20:21.00#ibcon#about to read 4, iclass 37, count 2 2006.162.07:20:21.00#ibcon#read 4, iclass 37, count 2 2006.162.07:20:21.00#ibcon#about to read 5, iclass 37, count 2 2006.162.07:20:21.00#ibcon#read 5, iclass 37, count 2 2006.162.07:20:21.00#ibcon#about to read 6, iclass 37, count 2 2006.162.07:20:21.00#ibcon#read 6, iclass 37, count 2 2006.162.07:20:21.00#ibcon#end of sib2, iclass 37, count 2 2006.162.07:20:21.00#ibcon#*after write, iclass 37, count 2 2006.162.07:20:21.00#ibcon#*before return 0, iclass 37, count 2 2006.162.07:20:21.00#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.162.07:20:21.00#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.162.07:20:21.00#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.162.07:20:21.00#ibcon#ireg 7 cls_cnt 0 2006.162.07:20:21.00#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.162.07:20:21.12#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.162.07:20:21.12#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.162.07:20:21.12#ibcon#enter wrdev, iclass 37, count 0 2006.162.07:20:21.12#ibcon#first serial, iclass 37, count 0 2006.162.07:20:21.12#ibcon#enter sib2, iclass 37, count 0 2006.162.07:20:21.12#ibcon#flushed, iclass 37, count 0 2006.162.07:20:21.12#ibcon#about to write, iclass 37, count 0 2006.162.07:20:21.12#ibcon#wrote, iclass 37, count 0 2006.162.07:20:21.12#ibcon#about to read 3, iclass 37, count 0 2006.162.07:20:21.14#ibcon#read 3, iclass 37, count 0 2006.162.07:20:21.14#ibcon#about to read 4, iclass 37, count 0 2006.162.07:20:21.14#ibcon#read 4, iclass 37, count 0 2006.162.07:20:21.14#ibcon#about to read 5, iclass 37, count 0 2006.162.07:20:21.14#ibcon#read 5, iclass 37, count 0 2006.162.07:20:21.14#ibcon#about to read 6, iclass 37, count 0 2006.162.07:20:21.14#ibcon#read 6, iclass 37, count 0 2006.162.07:20:21.14#ibcon#end of sib2, iclass 37, count 0 2006.162.07:20:21.14#ibcon#*mode == 0, iclass 37, count 0 2006.162.07:20:21.14#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.162.07:20:21.14#ibcon#[25=USB\r\n] 2006.162.07:20:21.14#ibcon#*before write, iclass 37, count 0 2006.162.07:20:21.14#ibcon#enter sib2, iclass 37, count 0 2006.162.07:20:21.14#ibcon#flushed, iclass 37, count 0 2006.162.07:20:21.14#ibcon#about to write, iclass 37, count 0 2006.162.07:20:21.14#ibcon#wrote, iclass 37, count 0 2006.162.07:20:21.14#ibcon#about to read 3, iclass 37, count 0 2006.162.07:20:21.17#ibcon#read 3, iclass 37, count 0 2006.162.07:20:21.17#ibcon#about to read 4, iclass 37, count 0 2006.162.07:20:21.17#ibcon#read 4, iclass 37, count 0 2006.162.07:20:21.17#ibcon#about to read 5, iclass 37, count 0 2006.162.07:20:21.17#ibcon#read 5, iclass 37, count 0 2006.162.07:20:21.17#ibcon#about to read 6, iclass 37, count 0 2006.162.07:20:21.17#ibcon#read 6, iclass 37, count 0 2006.162.07:20:21.17#ibcon#end of sib2, iclass 37, count 0 2006.162.07:20:21.17#ibcon#*after write, iclass 37, count 0 2006.162.07:20:21.17#ibcon#*before return 0, iclass 37, count 0 2006.162.07:20:21.17#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.162.07:20:21.17#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.162.07:20:21.17#ibcon#about to clear, iclass 37 cls_cnt 0 2006.162.07:20:21.17#ibcon#cleared, iclass 37 cls_cnt 0 2006.162.07:20:21.17$vc4f8/vblo=1,632.99 2006.162.07:20:21.17#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.162.07:20:21.17#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.162.07:20:21.17#ibcon#ireg 17 cls_cnt 0 2006.162.07:20:21.17#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.162.07:20:21.17#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.162.07:20:21.17#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.162.07:20:21.17#ibcon#enter wrdev, iclass 39, count 0 2006.162.07:20:21.17#ibcon#first serial, iclass 39, count 0 2006.162.07:20:21.17#ibcon#enter sib2, iclass 39, count 0 2006.162.07:20:21.17#ibcon#flushed, iclass 39, count 0 2006.162.07:20:21.17#ibcon#about to write, iclass 39, count 0 2006.162.07:20:21.17#ibcon#wrote, iclass 39, count 0 2006.162.07:20:21.17#ibcon#about to read 3, iclass 39, count 0 2006.162.07:20:21.19#ibcon#read 3, iclass 39, count 0 2006.162.07:20:21.19#ibcon#about to read 4, iclass 39, count 0 2006.162.07:20:21.19#ibcon#read 4, iclass 39, count 0 2006.162.07:20:21.19#ibcon#about to read 5, iclass 39, count 0 2006.162.07:20:21.19#ibcon#read 5, iclass 39, count 0 2006.162.07:20:21.19#ibcon#about to read 6, iclass 39, count 0 2006.162.07:20:21.19#ibcon#read 6, iclass 39, count 0 2006.162.07:20:21.19#ibcon#end of sib2, iclass 39, count 0 2006.162.07:20:21.19#ibcon#*mode == 0, iclass 39, count 0 2006.162.07:20:21.19#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.162.07:20:21.19#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.07:20:21.19#ibcon#*before write, iclass 39, count 0 2006.162.07:20:21.19#ibcon#enter sib2, iclass 39, count 0 2006.162.07:20:21.19#ibcon#flushed, iclass 39, count 0 2006.162.07:20:21.19#ibcon#about to write, iclass 39, count 0 2006.162.07:20:21.19#ibcon#wrote, iclass 39, count 0 2006.162.07:20:21.19#ibcon#about to read 3, iclass 39, count 0 2006.162.07:20:21.23#ibcon#read 3, iclass 39, count 0 2006.162.07:20:21.23#ibcon#about to read 4, iclass 39, count 0 2006.162.07:20:21.23#ibcon#read 4, iclass 39, count 0 2006.162.07:20:21.23#ibcon#about to read 5, iclass 39, count 0 2006.162.07:20:21.23#ibcon#read 5, iclass 39, count 0 2006.162.07:20:21.23#ibcon#about to read 6, iclass 39, count 0 2006.162.07:20:21.23#ibcon#read 6, iclass 39, count 0 2006.162.07:20:21.23#ibcon#end of sib2, iclass 39, count 0 2006.162.07:20:21.23#ibcon#*after write, iclass 39, count 0 2006.162.07:20:21.23#ibcon#*before return 0, iclass 39, count 0 2006.162.07:20:21.23#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.162.07:20:21.23#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.162.07:20:21.23#ibcon#about to clear, iclass 39 cls_cnt 0 2006.162.07:20:21.23#ibcon#cleared, iclass 39 cls_cnt 0 2006.162.07:20:21.23$vc4f8/vb=1,4 2006.162.07:20:21.23#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.162.07:20:21.23#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.162.07:20:21.23#ibcon#ireg 11 cls_cnt 2 2006.162.07:20:21.23#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.162.07:20:21.23#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.162.07:20:21.23#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.162.07:20:21.23#ibcon#enter wrdev, iclass 3, count 2 2006.162.07:20:21.23#ibcon#first serial, iclass 3, count 2 2006.162.07:20:21.23#ibcon#enter sib2, iclass 3, count 2 2006.162.07:20:21.23#ibcon#flushed, iclass 3, count 2 2006.162.07:20:21.23#ibcon#about to write, iclass 3, count 2 2006.162.07:20:21.23#ibcon#wrote, iclass 3, count 2 2006.162.07:20:21.23#ibcon#about to read 3, iclass 3, count 2 2006.162.07:20:21.25#ibcon#read 3, iclass 3, count 2 2006.162.07:20:21.25#ibcon#about to read 4, iclass 3, count 2 2006.162.07:20:21.25#ibcon#read 4, iclass 3, count 2 2006.162.07:20:21.25#ibcon#about to read 5, iclass 3, count 2 2006.162.07:20:21.25#ibcon#read 5, iclass 3, count 2 2006.162.07:20:21.25#ibcon#about to read 6, iclass 3, count 2 2006.162.07:20:21.25#ibcon#read 6, iclass 3, count 2 2006.162.07:20:21.25#ibcon#end of sib2, iclass 3, count 2 2006.162.07:20:21.25#ibcon#*mode == 0, iclass 3, count 2 2006.162.07:20:21.25#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.162.07:20:21.25#ibcon#[27=AT01-04\r\n] 2006.162.07:20:21.25#ibcon#*before write, iclass 3, count 2 2006.162.07:20:21.25#ibcon#enter sib2, iclass 3, count 2 2006.162.07:20:21.25#ibcon#flushed, iclass 3, count 2 2006.162.07:20:21.25#ibcon#about to write, iclass 3, count 2 2006.162.07:20:21.25#ibcon#wrote, iclass 3, count 2 2006.162.07:20:21.25#ibcon#about to read 3, iclass 3, count 2 2006.162.07:20:21.28#ibcon#read 3, iclass 3, count 2 2006.162.07:20:21.28#ibcon#about to read 4, iclass 3, count 2 2006.162.07:20:21.28#ibcon#read 4, iclass 3, count 2 2006.162.07:20:21.28#ibcon#about to read 5, iclass 3, count 2 2006.162.07:20:21.28#ibcon#read 5, iclass 3, count 2 2006.162.07:20:21.28#ibcon#about to read 6, iclass 3, count 2 2006.162.07:20:21.28#ibcon#read 6, iclass 3, count 2 2006.162.07:20:21.28#ibcon#end of sib2, iclass 3, count 2 2006.162.07:20:21.28#ibcon#*after write, iclass 3, count 2 2006.162.07:20:21.28#ibcon#*before return 0, iclass 3, count 2 2006.162.07:20:21.28#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.162.07:20:21.28#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.162.07:20:21.28#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.162.07:20:21.28#ibcon#ireg 7 cls_cnt 0 2006.162.07:20:21.28#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.162.07:20:21.40#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.162.07:20:21.40#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.162.07:20:21.40#ibcon#enter wrdev, iclass 3, count 0 2006.162.07:20:21.40#ibcon#first serial, iclass 3, count 0 2006.162.07:20:21.40#ibcon#enter sib2, iclass 3, count 0 2006.162.07:20:21.40#ibcon#flushed, iclass 3, count 0 2006.162.07:20:21.40#ibcon#about to write, iclass 3, count 0 2006.162.07:20:21.40#ibcon#wrote, iclass 3, count 0 2006.162.07:20:21.40#ibcon#about to read 3, iclass 3, count 0 2006.162.07:20:21.42#ibcon#read 3, iclass 3, count 0 2006.162.07:20:21.42#ibcon#about to read 4, iclass 3, count 0 2006.162.07:20:21.42#ibcon#read 4, iclass 3, count 0 2006.162.07:20:21.42#ibcon#about to read 5, iclass 3, count 0 2006.162.07:20:21.42#ibcon#read 5, iclass 3, count 0 2006.162.07:20:21.42#ibcon#about to read 6, iclass 3, count 0 2006.162.07:20:21.42#ibcon#read 6, iclass 3, count 0 2006.162.07:20:21.42#ibcon#end of sib2, iclass 3, count 0 2006.162.07:20:21.42#ibcon#*mode == 0, iclass 3, count 0 2006.162.07:20:21.42#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.162.07:20:21.42#ibcon#[27=USB\r\n] 2006.162.07:20:21.42#ibcon#*before write, iclass 3, count 0 2006.162.07:20:21.42#ibcon#enter sib2, iclass 3, count 0 2006.162.07:20:21.42#ibcon#flushed, iclass 3, count 0 2006.162.07:20:21.42#ibcon#about to write, iclass 3, count 0 2006.162.07:20:21.42#ibcon#wrote, iclass 3, count 0 2006.162.07:20:21.42#ibcon#about to read 3, iclass 3, count 0 2006.162.07:20:21.45#ibcon#read 3, iclass 3, count 0 2006.162.07:20:21.45#ibcon#about to read 4, iclass 3, count 0 2006.162.07:20:21.45#ibcon#read 4, iclass 3, count 0 2006.162.07:20:21.45#ibcon#about to read 5, iclass 3, count 0 2006.162.07:20:21.45#ibcon#read 5, iclass 3, count 0 2006.162.07:20:21.45#ibcon#about to read 6, iclass 3, count 0 2006.162.07:20:21.45#ibcon#read 6, iclass 3, count 0 2006.162.07:20:21.45#ibcon#end of sib2, iclass 3, count 0 2006.162.07:20:21.45#ibcon#*after write, iclass 3, count 0 2006.162.07:20:21.45#ibcon#*before return 0, iclass 3, count 0 2006.162.07:20:21.45#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.162.07:20:21.45#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.162.07:20:21.45#ibcon#about to clear, iclass 3 cls_cnt 0 2006.162.07:20:21.45#ibcon#cleared, iclass 3 cls_cnt 0 2006.162.07:20:21.45$vc4f8/vblo=2,640.99 2006.162.07:20:21.45#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.162.07:20:21.45#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.162.07:20:21.45#ibcon#ireg 17 cls_cnt 0 2006.162.07:20:21.45#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.162.07:20:21.45#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.162.07:20:21.45#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.162.07:20:21.45#ibcon#enter wrdev, iclass 5, count 0 2006.162.07:20:21.45#ibcon#first serial, iclass 5, count 0 2006.162.07:20:21.45#ibcon#enter sib2, iclass 5, count 0 2006.162.07:20:21.45#ibcon#flushed, iclass 5, count 0 2006.162.07:20:21.45#ibcon#about to write, iclass 5, count 0 2006.162.07:20:21.45#ibcon#wrote, iclass 5, count 0 2006.162.07:20:21.45#ibcon#about to read 3, iclass 5, count 0 2006.162.07:20:21.47#ibcon#read 3, iclass 5, count 0 2006.162.07:20:21.47#ibcon#about to read 4, iclass 5, count 0 2006.162.07:20:21.47#ibcon#read 4, iclass 5, count 0 2006.162.07:20:21.47#ibcon#about to read 5, iclass 5, count 0 2006.162.07:20:21.47#ibcon#read 5, iclass 5, count 0 2006.162.07:20:21.47#ibcon#about to read 6, iclass 5, count 0 2006.162.07:20:21.47#ibcon#read 6, iclass 5, count 0 2006.162.07:20:21.47#ibcon#end of sib2, iclass 5, count 0 2006.162.07:20:21.47#ibcon#*mode == 0, iclass 5, count 0 2006.162.07:20:21.47#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.162.07:20:21.47#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.07:20:21.47#ibcon#*before write, iclass 5, count 0 2006.162.07:20:21.47#ibcon#enter sib2, iclass 5, count 0 2006.162.07:20:21.47#ibcon#flushed, iclass 5, count 0 2006.162.07:20:21.47#ibcon#about to write, iclass 5, count 0 2006.162.07:20:21.47#ibcon#wrote, iclass 5, count 0 2006.162.07:20:21.47#ibcon#about to read 3, iclass 5, count 0 2006.162.07:20:21.51#ibcon#read 3, iclass 5, count 0 2006.162.07:20:21.51#ibcon#about to read 4, iclass 5, count 0 2006.162.07:20:21.51#ibcon#read 4, iclass 5, count 0 2006.162.07:20:21.51#ibcon#about to read 5, iclass 5, count 0 2006.162.07:20:21.51#ibcon#read 5, iclass 5, count 0 2006.162.07:20:21.51#ibcon#about to read 6, iclass 5, count 0 2006.162.07:20:21.51#ibcon#read 6, iclass 5, count 0 2006.162.07:20:21.51#ibcon#end of sib2, iclass 5, count 0 2006.162.07:20:21.51#ibcon#*after write, iclass 5, count 0 2006.162.07:20:21.51#ibcon#*before return 0, iclass 5, count 0 2006.162.07:20:21.51#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.162.07:20:21.51#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.162.07:20:21.51#ibcon#about to clear, iclass 5 cls_cnt 0 2006.162.07:20:21.51#ibcon#cleared, iclass 5 cls_cnt 0 2006.162.07:20:21.51$vc4f8/vb=2,4 2006.162.07:20:21.51#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.162.07:20:21.51#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.162.07:20:21.51#ibcon#ireg 11 cls_cnt 2 2006.162.07:20:21.51#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.162.07:20:21.57#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.162.07:20:21.57#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.162.07:20:21.57#ibcon#enter wrdev, iclass 7, count 2 2006.162.07:20:21.57#ibcon#first serial, iclass 7, count 2 2006.162.07:20:21.57#ibcon#enter sib2, iclass 7, count 2 2006.162.07:20:21.57#ibcon#flushed, iclass 7, count 2 2006.162.07:20:21.57#ibcon#about to write, iclass 7, count 2 2006.162.07:20:21.57#ibcon#wrote, iclass 7, count 2 2006.162.07:20:21.57#ibcon#about to read 3, iclass 7, count 2 2006.162.07:20:21.59#ibcon#read 3, iclass 7, count 2 2006.162.07:20:21.59#ibcon#about to read 4, iclass 7, count 2 2006.162.07:20:21.59#ibcon#read 4, iclass 7, count 2 2006.162.07:20:21.59#ibcon#about to read 5, iclass 7, count 2 2006.162.07:20:21.59#ibcon#read 5, iclass 7, count 2 2006.162.07:20:21.59#ibcon#about to read 6, iclass 7, count 2 2006.162.07:20:21.59#ibcon#read 6, iclass 7, count 2 2006.162.07:20:21.59#ibcon#end of sib2, iclass 7, count 2 2006.162.07:20:21.59#ibcon#*mode == 0, iclass 7, count 2 2006.162.07:20:21.59#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.162.07:20:21.59#ibcon#[27=AT02-04\r\n] 2006.162.07:20:21.59#ibcon#*before write, iclass 7, count 2 2006.162.07:20:21.59#ibcon#enter sib2, iclass 7, count 2 2006.162.07:20:21.59#ibcon#flushed, iclass 7, count 2 2006.162.07:20:21.59#ibcon#about to write, iclass 7, count 2 2006.162.07:20:21.59#ibcon#wrote, iclass 7, count 2 2006.162.07:20:21.59#ibcon#about to read 3, iclass 7, count 2 2006.162.07:20:21.62#ibcon#read 3, iclass 7, count 2 2006.162.07:20:21.62#ibcon#about to read 4, iclass 7, count 2 2006.162.07:20:21.62#ibcon#read 4, iclass 7, count 2 2006.162.07:20:21.62#ibcon#about to read 5, iclass 7, count 2 2006.162.07:20:21.62#ibcon#read 5, iclass 7, count 2 2006.162.07:20:21.62#ibcon#about to read 6, iclass 7, count 2 2006.162.07:20:21.62#ibcon#read 6, iclass 7, count 2 2006.162.07:20:21.62#ibcon#end of sib2, iclass 7, count 2 2006.162.07:20:21.62#ibcon#*after write, iclass 7, count 2 2006.162.07:20:21.62#ibcon#*before return 0, iclass 7, count 2 2006.162.07:20:21.62#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.162.07:20:21.62#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.162.07:20:21.62#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.162.07:20:21.62#ibcon#ireg 7 cls_cnt 0 2006.162.07:20:21.62#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.162.07:20:21.74#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.162.07:20:21.74#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.162.07:20:21.74#ibcon#enter wrdev, iclass 7, count 0 2006.162.07:20:21.74#ibcon#first serial, iclass 7, count 0 2006.162.07:20:21.74#ibcon#enter sib2, iclass 7, count 0 2006.162.07:20:21.74#ibcon#flushed, iclass 7, count 0 2006.162.07:20:21.74#ibcon#about to write, iclass 7, count 0 2006.162.07:20:21.74#ibcon#wrote, iclass 7, count 0 2006.162.07:20:21.74#ibcon#about to read 3, iclass 7, count 0 2006.162.07:20:21.76#ibcon#read 3, iclass 7, count 0 2006.162.07:20:21.76#ibcon#about to read 4, iclass 7, count 0 2006.162.07:20:21.76#ibcon#read 4, iclass 7, count 0 2006.162.07:20:21.76#ibcon#about to read 5, iclass 7, count 0 2006.162.07:20:21.76#ibcon#read 5, iclass 7, count 0 2006.162.07:20:21.76#ibcon#about to read 6, iclass 7, count 0 2006.162.07:20:21.76#ibcon#read 6, iclass 7, count 0 2006.162.07:20:21.76#ibcon#end of sib2, iclass 7, count 0 2006.162.07:20:21.76#ibcon#*mode == 0, iclass 7, count 0 2006.162.07:20:21.76#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.162.07:20:21.76#ibcon#[27=USB\r\n] 2006.162.07:20:21.76#ibcon#*before write, iclass 7, count 0 2006.162.07:20:21.76#ibcon#enter sib2, iclass 7, count 0 2006.162.07:20:21.76#ibcon#flushed, iclass 7, count 0 2006.162.07:20:21.76#ibcon#about to write, iclass 7, count 0 2006.162.07:20:21.76#ibcon#wrote, iclass 7, count 0 2006.162.07:20:21.76#ibcon#about to read 3, iclass 7, count 0 2006.162.07:20:21.79#ibcon#read 3, iclass 7, count 0 2006.162.07:20:21.79#ibcon#about to read 4, iclass 7, count 0 2006.162.07:20:21.79#ibcon#read 4, iclass 7, count 0 2006.162.07:20:21.79#ibcon#about to read 5, iclass 7, count 0 2006.162.07:20:21.79#ibcon#read 5, iclass 7, count 0 2006.162.07:20:21.79#ibcon#about to read 6, iclass 7, count 0 2006.162.07:20:21.79#ibcon#read 6, iclass 7, count 0 2006.162.07:20:21.79#ibcon#end of sib2, iclass 7, count 0 2006.162.07:20:21.79#ibcon#*after write, iclass 7, count 0 2006.162.07:20:21.79#ibcon#*before return 0, iclass 7, count 0 2006.162.07:20:21.79#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.162.07:20:21.79#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.162.07:20:21.79#ibcon#about to clear, iclass 7 cls_cnt 0 2006.162.07:20:21.79#ibcon#cleared, iclass 7 cls_cnt 0 2006.162.07:20:21.79$vc4f8/vblo=3,656.99 2006.162.07:20:21.79#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.162.07:20:21.79#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.162.07:20:21.79#ibcon#ireg 17 cls_cnt 0 2006.162.07:20:21.79#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.162.07:20:21.79#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.162.07:20:21.79#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.162.07:20:21.79#ibcon#enter wrdev, iclass 11, count 0 2006.162.07:20:21.79#ibcon#first serial, iclass 11, count 0 2006.162.07:20:21.79#ibcon#enter sib2, iclass 11, count 0 2006.162.07:20:21.79#ibcon#flushed, iclass 11, count 0 2006.162.07:20:21.79#ibcon#about to write, iclass 11, count 0 2006.162.07:20:21.79#ibcon#wrote, iclass 11, count 0 2006.162.07:20:21.79#ibcon#about to read 3, iclass 11, count 0 2006.162.07:20:21.81#ibcon#read 3, iclass 11, count 0 2006.162.07:20:21.81#ibcon#about to read 4, iclass 11, count 0 2006.162.07:20:21.81#ibcon#read 4, iclass 11, count 0 2006.162.07:20:21.81#ibcon#about to read 5, iclass 11, count 0 2006.162.07:20:21.81#ibcon#read 5, iclass 11, count 0 2006.162.07:20:21.81#ibcon#about to read 6, iclass 11, count 0 2006.162.07:20:21.81#ibcon#read 6, iclass 11, count 0 2006.162.07:20:21.81#ibcon#end of sib2, iclass 11, count 0 2006.162.07:20:21.81#ibcon#*mode == 0, iclass 11, count 0 2006.162.07:20:21.81#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.162.07:20:21.81#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.07:20:21.81#ibcon#*before write, iclass 11, count 0 2006.162.07:20:21.81#ibcon#enter sib2, iclass 11, count 0 2006.162.07:20:21.81#ibcon#flushed, iclass 11, count 0 2006.162.07:20:21.81#ibcon#about to write, iclass 11, count 0 2006.162.07:20:21.81#ibcon#wrote, iclass 11, count 0 2006.162.07:20:21.81#ibcon#about to read 3, iclass 11, count 0 2006.162.07:20:21.85#ibcon#read 3, iclass 11, count 0 2006.162.07:20:21.85#ibcon#about to read 4, iclass 11, count 0 2006.162.07:20:21.85#ibcon#read 4, iclass 11, count 0 2006.162.07:20:21.85#ibcon#about to read 5, iclass 11, count 0 2006.162.07:20:21.85#ibcon#read 5, iclass 11, count 0 2006.162.07:20:21.85#ibcon#about to read 6, iclass 11, count 0 2006.162.07:20:21.85#ibcon#read 6, iclass 11, count 0 2006.162.07:20:21.85#ibcon#end of sib2, iclass 11, count 0 2006.162.07:20:21.85#ibcon#*after write, iclass 11, count 0 2006.162.07:20:21.85#ibcon#*before return 0, iclass 11, count 0 2006.162.07:20:21.85#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.162.07:20:21.85#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.162.07:20:21.85#ibcon#about to clear, iclass 11 cls_cnt 0 2006.162.07:20:21.85#ibcon#cleared, iclass 11 cls_cnt 0 2006.162.07:20:21.85$vc4f8/vb=3,4 2006.162.07:20:21.85#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.162.07:20:21.85#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.162.07:20:21.85#ibcon#ireg 11 cls_cnt 2 2006.162.07:20:21.85#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.162.07:20:21.91#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.162.07:20:21.91#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.162.07:20:21.91#ibcon#enter wrdev, iclass 13, count 2 2006.162.07:20:21.91#ibcon#first serial, iclass 13, count 2 2006.162.07:20:21.91#ibcon#enter sib2, iclass 13, count 2 2006.162.07:20:21.91#ibcon#flushed, iclass 13, count 2 2006.162.07:20:21.91#ibcon#about to write, iclass 13, count 2 2006.162.07:20:21.91#ibcon#wrote, iclass 13, count 2 2006.162.07:20:21.91#ibcon#about to read 3, iclass 13, count 2 2006.162.07:20:21.93#ibcon#read 3, iclass 13, count 2 2006.162.07:20:21.93#ibcon#about to read 4, iclass 13, count 2 2006.162.07:20:21.93#ibcon#read 4, iclass 13, count 2 2006.162.07:20:21.93#ibcon#about to read 5, iclass 13, count 2 2006.162.07:20:21.93#ibcon#read 5, iclass 13, count 2 2006.162.07:20:21.93#ibcon#about to read 6, iclass 13, count 2 2006.162.07:20:21.93#ibcon#read 6, iclass 13, count 2 2006.162.07:20:21.93#ibcon#end of sib2, iclass 13, count 2 2006.162.07:20:21.93#ibcon#*mode == 0, iclass 13, count 2 2006.162.07:20:21.93#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.162.07:20:21.93#ibcon#[27=AT03-04\r\n] 2006.162.07:20:21.93#ibcon#*before write, iclass 13, count 2 2006.162.07:20:21.93#ibcon#enter sib2, iclass 13, count 2 2006.162.07:20:21.93#ibcon#flushed, iclass 13, count 2 2006.162.07:20:21.93#ibcon#about to write, iclass 13, count 2 2006.162.07:20:21.93#ibcon#wrote, iclass 13, count 2 2006.162.07:20:21.93#ibcon#about to read 3, iclass 13, count 2 2006.162.07:20:21.96#ibcon#read 3, iclass 13, count 2 2006.162.07:20:21.96#ibcon#about to read 4, iclass 13, count 2 2006.162.07:20:21.96#ibcon#read 4, iclass 13, count 2 2006.162.07:20:21.96#ibcon#about to read 5, iclass 13, count 2 2006.162.07:20:21.96#ibcon#read 5, iclass 13, count 2 2006.162.07:20:21.96#ibcon#about to read 6, iclass 13, count 2 2006.162.07:20:21.96#ibcon#read 6, iclass 13, count 2 2006.162.07:20:21.96#ibcon#end of sib2, iclass 13, count 2 2006.162.07:20:21.96#ibcon#*after write, iclass 13, count 2 2006.162.07:20:21.96#ibcon#*before return 0, iclass 13, count 2 2006.162.07:20:21.96#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.162.07:20:21.96#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.162.07:20:21.96#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.162.07:20:21.96#ibcon#ireg 7 cls_cnt 0 2006.162.07:20:21.96#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.162.07:20:22.08#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.162.07:20:22.08#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.162.07:20:22.08#ibcon#enter wrdev, iclass 13, count 0 2006.162.07:20:22.08#ibcon#first serial, iclass 13, count 0 2006.162.07:20:22.08#ibcon#enter sib2, iclass 13, count 0 2006.162.07:20:22.08#ibcon#flushed, iclass 13, count 0 2006.162.07:20:22.08#ibcon#about to write, iclass 13, count 0 2006.162.07:20:22.08#ibcon#wrote, iclass 13, count 0 2006.162.07:20:22.08#ibcon#about to read 3, iclass 13, count 0 2006.162.07:20:22.10#ibcon#read 3, iclass 13, count 0 2006.162.07:20:22.10#ibcon#about to read 4, iclass 13, count 0 2006.162.07:20:22.10#ibcon#read 4, iclass 13, count 0 2006.162.07:20:22.10#ibcon#about to read 5, iclass 13, count 0 2006.162.07:20:22.10#ibcon#read 5, iclass 13, count 0 2006.162.07:20:22.10#ibcon#about to read 6, iclass 13, count 0 2006.162.07:20:22.10#ibcon#read 6, iclass 13, count 0 2006.162.07:20:22.10#ibcon#end of sib2, iclass 13, count 0 2006.162.07:20:22.10#ibcon#*mode == 0, iclass 13, count 0 2006.162.07:20:22.10#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.162.07:20:22.10#ibcon#[27=USB\r\n] 2006.162.07:20:22.10#ibcon#*before write, iclass 13, count 0 2006.162.07:20:22.10#ibcon#enter sib2, iclass 13, count 0 2006.162.07:20:22.10#ibcon#flushed, iclass 13, count 0 2006.162.07:20:22.10#ibcon#about to write, iclass 13, count 0 2006.162.07:20:22.10#ibcon#wrote, iclass 13, count 0 2006.162.07:20:22.10#ibcon#about to read 3, iclass 13, count 0 2006.162.07:20:22.13#ibcon#read 3, iclass 13, count 0 2006.162.07:20:22.13#ibcon#about to read 4, iclass 13, count 0 2006.162.07:20:22.13#ibcon#read 4, iclass 13, count 0 2006.162.07:20:22.13#ibcon#about to read 5, iclass 13, count 0 2006.162.07:20:22.13#ibcon#read 5, iclass 13, count 0 2006.162.07:20:22.13#ibcon#about to read 6, iclass 13, count 0 2006.162.07:20:22.13#ibcon#read 6, iclass 13, count 0 2006.162.07:20:22.13#ibcon#end of sib2, iclass 13, count 0 2006.162.07:20:22.13#ibcon#*after write, iclass 13, count 0 2006.162.07:20:22.13#ibcon#*before return 0, iclass 13, count 0 2006.162.07:20:22.13#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.162.07:20:22.13#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.162.07:20:22.13#ibcon#about to clear, iclass 13 cls_cnt 0 2006.162.07:20:22.13#ibcon#cleared, iclass 13 cls_cnt 0 2006.162.07:20:22.13$vc4f8/vblo=4,712.99 2006.162.07:20:22.13#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.162.07:20:22.13#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.162.07:20:22.13#ibcon#ireg 17 cls_cnt 0 2006.162.07:20:22.13#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:20:22.13#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:20:22.13#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:20:22.13#ibcon#enter wrdev, iclass 15, count 0 2006.162.07:20:22.13#ibcon#first serial, iclass 15, count 0 2006.162.07:20:22.13#ibcon#enter sib2, iclass 15, count 0 2006.162.07:20:22.13#ibcon#flushed, iclass 15, count 0 2006.162.07:20:22.13#ibcon#about to write, iclass 15, count 0 2006.162.07:20:22.13#ibcon#wrote, iclass 15, count 0 2006.162.07:20:22.13#ibcon#about to read 3, iclass 15, count 0 2006.162.07:20:22.15#ibcon#read 3, iclass 15, count 0 2006.162.07:20:22.15#ibcon#about to read 4, iclass 15, count 0 2006.162.07:20:22.15#ibcon#read 4, iclass 15, count 0 2006.162.07:20:22.15#ibcon#about to read 5, iclass 15, count 0 2006.162.07:20:22.15#ibcon#read 5, iclass 15, count 0 2006.162.07:20:22.15#ibcon#about to read 6, iclass 15, count 0 2006.162.07:20:22.15#ibcon#read 6, iclass 15, count 0 2006.162.07:20:22.15#ibcon#end of sib2, iclass 15, count 0 2006.162.07:20:22.15#ibcon#*mode == 0, iclass 15, count 0 2006.162.07:20:22.15#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.162.07:20:22.15#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.07:20:22.15#ibcon#*before write, iclass 15, count 0 2006.162.07:20:22.15#ibcon#enter sib2, iclass 15, count 0 2006.162.07:20:22.15#ibcon#flushed, iclass 15, count 0 2006.162.07:20:22.15#ibcon#about to write, iclass 15, count 0 2006.162.07:20:22.15#ibcon#wrote, iclass 15, count 0 2006.162.07:20:22.15#ibcon#about to read 3, iclass 15, count 0 2006.162.07:20:22.19#ibcon#read 3, iclass 15, count 0 2006.162.07:20:22.19#ibcon#about to read 4, iclass 15, count 0 2006.162.07:20:22.19#ibcon#read 4, iclass 15, count 0 2006.162.07:20:22.19#ibcon#about to read 5, iclass 15, count 0 2006.162.07:20:22.19#ibcon#read 5, iclass 15, count 0 2006.162.07:20:22.19#ibcon#about to read 6, iclass 15, count 0 2006.162.07:20:22.19#ibcon#read 6, iclass 15, count 0 2006.162.07:20:22.19#ibcon#end of sib2, iclass 15, count 0 2006.162.07:20:22.19#ibcon#*after write, iclass 15, count 0 2006.162.07:20:22.19#ibcon#*before return 0, iclass 15, count 0 2006.162.07:20:22.19#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:20:22.19#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:20:22.19#ibcon#about to clear, iclass 15 cls_cnt 0 2006.162.07:20:22.19#ibcon#cleared, iclass 15 cls_cnt 0 2006.162.07:20:22.19$vc4f8/vb=4,4 2006.162.07:20:22.19#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.162.07:20:22.19#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.162.07:20:22.19#ibcon#ireg 11 cls_cnt 2 2006.162.07:20:22.19#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:20:22.25#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:20:22.25#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:20:22.25#ibcon#enter wrdev, iclass 17, count 2 2006.162.07:20:22.25#ibcon#first serial, iclass 17, count 2 2006.162.07:20:22.25#ibcon#enter sib2, iclass 17, count 2 2006.162.07:20:22.25#ibcon#flushed, iclass 17, count 2 2006.162.07:20:22.25#ibcon#about to write, iclass 17, count 2 2006.162.07:20:22.25#ibcon#wrote, iclass 17, count 2 2006.162.07:20:22.25#ibcon#about to read 3, iclass 17, count 2 2006.162.07:20:22.27#ibcon#read 3, iclass 17, count 2 2006.162.07:20:22.27#ibcon#about to read 4, iclass 17, count 2 2006.162.07:20:22.27#ibcon#read 4, iclass 17, count 2 2006.162.07:20:22.27#ibcon#about to read 5, iclass 17, count 2 2006.162.07:20:22.27#ibcon#read 5, iclass 17, count 2 2006.162.07:20:22.27#ibcon#about to read 6, iclass 17, count 2 2006.162.07:20:22.27#ibcon#read 6, iclass 17, count 2 2006.162.07:20:22.27#ibcon#end of sib2, iclass 17, count 2 2006.162.07:20:22.27#ibcon#*mode == 0, iclass 17, count 2 2006.162.07:20:22.27#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.162.07:20:22.27#ibcon#[27=AT04-04\r\n] 2006.162.07:20:22.27#ibcon#*before write, iclass 17, count 2 2006.162.07:20:22.27#ibcon#enter sib2, iclass 17, count 2 2006.162.07:20:22.27#ibcon#flushed, iclass 17, count 2 2006.162.07:20:22.27#ibcon#about to write, iclass 17, count 2 2006.162.07:20:22.27#ibcon#wrote, iclass 17, count 2 2006.162.07:20:22.27#ibcon#about to read 3, iclass 17, count 2 2006.162.07:20:22.30#ibcon#read 3, iclass 17, count 2 2006.162.07:20:22.30#ibcon#about to read 4, iclass 17, count 2 2006.162.07:20:22.30#ibcon#read 4, iclass 17, count 2 2006.162.07:20:22.30#ibcon#about to read 5, iclass 17, count 2 2006.162.07:20:22.30#ibcon#read 5, iclass 17, count 2 2006.162.07:20:22.30#ibcon#about to read 6, iclass 17, count 2 2006.162.07:20:22.30#ibcon#read 6, iclass 17, count 2 2006.162.07:20:22.30#ibcon#end of sib2, iclass 17, count 2 2006.162.07:20:22.30#ibcon#*after write, iclass 17, count 2 2006.162.07:20:22.30#ibcon#*before return 0, iclass 17, count 2 2006.162.07:20:22.30#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:20:22.30#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:20:22.30#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.162.07:20:22.30#ibcon#ireg 7 cls_cnt 0 2006.162.07:20:22.30#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:20:22.42#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:20:22.42#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:20:22.42#ibcon#enter wrdev, iclass 17, count 0 2006.162.07:20:22.42#ibcon#first serial, iclass 17, count 0 2006.162.07:20:22.42#ibcon#enter sib2, iclass 17, count 0 2006.162.07:20:22.42#ibcon#flushed, iclass 17, count 0 2006.162.07:20:22.42#ibcon#about to write, iclass 17, count 0 2006.162.07:20:22.42#ibcon#wrote, iclass 17, count 0 2006.162.07:20:22.42#ibcon#about to read 3, iclass 17, count 0 2006.162.07:20:22.44#ibcon#read 3, iclass 17, count 0 2006.162.07:20:22.44#ibcon#about to read 4, iclass 17, count 0 2006.162.07:20:22.44#ibcon#read 4, iclass 17, count 0 2006.162.07:20:22.44#ibcon#about to read 5, iclass 17, count 0 2006.162.07:20:22.44#ibcon#read 5, iclass 17, count 0 2006.162.07:20:22.44#ibcon#about to read 6, iclass 17, count 0 2006.162.07:20:22.44#ibcon#read 6, iclass 17, count 0 2006.162.07:20:22.44#ibcon#end of sib2, iclass 17, count 0 2006.162.07:20:22.44#ibcon#*mode == 0, iclass 17, count 0 2006.162.07:20:22.44#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.162.07:20:22.44#ibcon#[27=USB\r\n] 2006.162.07:20:22.44#ibcon#*before write, iclass 17, count 0 2006.162.07:20:22.44#ibcon#enter sib2, iclass 17, count 0 2006.162.07:20:22.44#ibcon#flushed, iclass 17, count 0 2006.162.07:20:22.44#ibcon#about to write, iclass 17, count 0 2006.162.07:20:22.44#ibcon#wrote, iclass 17, count 0 2006.162.07:20:22.44#ibcon#about to read 3, iclass 17, count 0 2006.162.07:20:22.47#ibcon#read 3, iclass 17, count 0 2006.162.07:20:22.47#ibcon#about to read 4, iclass 17, count 0 2006.162.07:20:22.47#ibcon#read 4, iclass 17, count 0 2006.162.07:20:22.47#ibcon#about to read 5, iclass 17, count 0 2006.162.07:20:22.47#ibcon#read 5, iclass 17, count 0 2006.162.07:20:22.47#ibcon#about to read 6, iclass 17, count 0 2006.162.07:20:22.47#ibcon#read 6, iclass 17, count 0 2006.162.07:20:22.47#ibcon#end of sib2, iclass 17, count 0 2006.162.07:20:22.47#ibcon#*after write, iclass 17, count 0 2006.162.07:20:22.47#ibcon#*before return 0, iclass 17, count 0 2006.162.07:20:22.47#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:20:22.47#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:20:22.47#ibcon#about to clear, iclass 17 cls_cnt 0 2006.162.07:20:22.47#ibcon#cleared, iclass 17 cls_cnt 0 2006.162.07:20:22.47$vc4f8/vblo=5,744.99 2006.162.07:20:22.47#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.162.07:20:22.47#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.162.07:20:22.47#ibcon#ireg 17 cls_cnt 0 2006.162.07:20:22.47#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:20:22.47#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:20:22.47#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:20:22.47#ibcon#enter wrdev, iclass 19, count 0 2006.162.07:20:22.47#ibcon#first serial, iclass 19, count 0 2006.162.07:20:22.47#ibcon#enter sib2, iclass 19, count 0 2006.162.07:20:22.47#ibcon#flushed, iclass 19, count 0 2006.162.07:20:22.47#ibcon#about to write, iclass 19, count 0 2006.162.07:20:22.47#ibcon#wrote, iclass 19, count 0 2006.162.07:20:22.47#ibcon#about to read 3, iclass 19, count 0 2006.162.07:20:22.49#ibcon#read 3, iclass 19, count 0 2006.162.07:20:22.49#ibcon#about to read 4, iclass 19, count 0 2006.162.07:20:22.49#ibcon#read 4, iclass 19, count 0 2006.162.07:20:22.49#ibcon#about to read 5, iclass 19, count 0 2006.162.07:20:22.49#ibcon#read 5, iclass 19, count 0 2006.162.07:20:22.49#ibcon#about to read 6, iclass 19, count 0 2006.162.07:20:22.49#ibcon#read 6, iclass 19, count 0 2006.162.07:20:22.49#ibcon#end of sib2, iclass 19, count 0 2006.162.07:20:22.49#ibcon#*mode == 0, iclass 19, count 0 2006.162.07:20:22.49#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.162.07:20:22.49#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.07:20:22.49#ibcon#*before write, iclass 19, count 0 2006.162.07:20:22.49#ibcon#enter sib2, iclass 19, count 0 2006.162.07:20:22.49#ibcon#flushed, iclass 19, count 0 2006.162.07:20:22.49#ibcon#about to write, iclass 19, count 0 2006.162.07:20:22.49#ibcon#wrote, iclass 19, count 0 2006.162.07:20:22.49#ibcon#about to read 3, iclass 19, count 0 2006.162.07:20:22.53#ibcon#read 3, iclass 19, count 0 2006.162.07:20:22.53#ibcon#about to read 4, iclass 19, count 0 2006.162.07:20:22.53#ibcon#read 4, iclass 19, count 0 2006.162.07:20:22.53#ibcon#about to read 5, iclass 19, count 0 2006.162.07:20:22.53#ibcon#read 5, iclass 19, count 0 2006.162.07:20:22.53#ibcon#about to read 6, iclass 19, count 0 2006.162.07:20:22.53#ibcon#read 6, iclass 19, count 0 2006.162.07:20:22.53#ibcon#end of sib2, iclass 19, count 0 2006.162.07:20:22.53#ibcon#*after write, iclass 19, count 0 2006.162.07:20:22.53#ibcon#*before return 0, iclass 19, count 0 2006.162.07:20:22.53#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:20:22.53#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:20:22.53#ibcon#about to clear, iclass 19 cls_cnt 0 2006.162.07:20:22.53#ibcon#cleared, iclass 19 cls_cnt 0 2006.162.07:20:22.53$vc4f8/vb=5,4 2006.162.07:20:22.53#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.162.07:20:22.53#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.162.07:20:22.53#ibcon#ireg 11 cls_cnt 2 2006.162.07:20:22.53#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:20:22.59#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:20:22.59#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:20:22.59#ibcon#enter wrdev, iclass 21, count 2 2006.162.07:20:22.59#ibcon#first serial, iclass 21, count 2 2006.162.07:20:22.59#ibcon#enter sib2, iclass 21, count 2 2006.162.07:20:22.59#ibcon#flushed, iclass 21, count 2 2006.162.07:20:22.59#ibcon#about to write, iclass 21, count 2 2006.162.07:20:22.59#ibcon#wrote, iclass 21, count 2 2006.162.07:20:22.59#ibcon#about to read 3, iclass 21, count 2 2006.162.07:20:22.61#ibcon#read 3, iclass 21, count 2 2006.162.07:20:22.61#ibcon#about to read 4, iclass 21, count 2 2006.162.07:20:22.61#ibcon#read 4, iclass 21, count 2 2006.162.07:20:22.61#ibcon#about to read 5, iclass 21, count 2 2006.162.07:20:22.61#ibcon#read 5, iclass 21, count 2 2006.162.07:20:22.61#ibcon#about to read 6, iclass 21, count 2 2006.162.07:20:22.61#ibcon#read 6, iclass 21, count 2 2006.162.07:20:22.61#ibcon#end of sib2, iclass 21, count 2 2006.162.07:20:22.61#ibcon#*mode == 0, iclass 21, count 2 2006.162.07:20:22.61#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.162.07:20:22.61#ibcon#[27=AT05-04\r\n] 2006.162.07:20:22.61#ibcon#*before write, iclass 21, count 2 2006.162.07:20:22.61#ibcon#enter sib2, iclass 21, count 2 2006.162.07:20:22.61#ibcon#flushed, iclass 21, count 2 2006.162.07:20:22.61#ibcon#about to write, iclass 21, count 2 2006.162.07:20:22.61#ibcon#wrote, iclass 21, count 2 2006.162.07:20:22.61#ibcon#about to read 3, iclass 21, count 2 2006.162.07:20:22.64#ibcon#read 3, iclass 21, count 2 2006.162.07:20:22.64#ibcon#about to read 4, iclass 21, count 2 2006.162.07:20:22.64#ibcon#read 4, iclass 21, count 2 2006.162.07:20:22.64#ibcon#about to read 5, iclass 21, count 2 2006.162.07:20:22.64#ibcon#read 5, iclass 21, count 2 2006.162.07:20:22.64#ibcon#about to read 6, iclass 21, count 2 2006.162.07:20:22.64#ibcon#read 6, iclass 21, count 2 2006.162.07:20:22.64#ibcon#end of sib2, iclass 21, count 2 2006.162.07:20:22.64#ibcon#*after write, iclass 21, count 2 2006.162.07:20:22.64#ibcon#*before return 0, iclass 21, count 2 2006.162.07:20:22.64#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:20:22.64#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:20:22.64#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.162.07:20:22.64#ibcon#ireg 7 cls_cnt 0 2006.162.07:20:22.64#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:20:22.76#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:20:22.76#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:20:22.76#ibcon#enter wrdev, iclass 21, count 0 2006.162.07:20:22.76#ibcon#first serial, iclass 21, count 0 2006.162.07:20:22.76#ibcon#enter sib2, iclass 21, count 0 2006.162.07:20:22.76#ibcon#flushed, iclass 21, count 0 2006.162.07:20:22.76#ibcon#about to write, iclass 21, count 0 2006.162.07:20:22.76#ibcon#wrote, iclass 21, count 0 2006.162.07:20:22.76#ibcon#about to read 3, iclass 21, count 0 2006.162.07:20:22.78#ibcon#read 3, iclass 21, count 0 2006.162.07:20:22.78#ibcon#about to read 4, iclass 21, count 0 2006.162.07:20:22.78#ibcon#read 4, iclass 21, count 0 2006.162.07:20:22.78#ibcon#about to read 5, iclass 21, count 0 2006.162.07:20:22.78#ibcon#read 5, iclass 21, count 0 2006.162.07:20:22.78#ibcon#about to read 6, iclass 21, count 0 2006.162.07:20:22.78#ibcon#read 6, iclass 21, count 0 2006.162.07:20:22.78#ibcon#end of sib2, iclass 21, count 0 2006.162.07:20:22.78#ibcon#*mode == 0, iclass 21, count 0 2006.162.07:20:22.78#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.162.07:20:22.78#ibcon#[27=USB\r\n] 2006.162.07:20:22.78#ibcon#*before write, iclass 21, count 0 2006.162.07:20:22.78#ibcon#enter sib2, iclass 21, count 0 2006.162.07:20:22.78#ibcon#flushed, iclass 21, count 0 2006.162.07:20:22.78#ibcon#about to write, iclass 21, count 0 2006.162.07:20:22.78#ibcon#wrote, iclass 21, count 0 2006.162.07:20:22.78#ibcon#about to read 3, iclass 21, count 0 2006.162.07:20:22.81#ibcon#read 3, iclass 21, count 0 2006.162.07:20:22.81#ibcon#about to read 4, iclass 21, count 0 2006.162.07:20:22.81#ibcon#read 4, iclass 21, count 0 2006.162.07:20:22.81#ibcon#about to read 5, iclass 21, count 0 2006.162.07:20:22.81#ibcon#read 5, iclass 21, count 0 2006.162.07:20:22.81#ibcon#about to read 6, iclass 21, count 0 2006.162.07:20:22.81#ibcon#read 6, iclass 21, count 0 2006.162.07:20:22.81#ibcon#end of sib2, iclass 21, count 0 2006.162.07:20:22.81#ibcon#*after write, iclass 21, count 0 2006.162.07:20:22.81#ibcon#*before return 0, iclass 21, count 0 2006.162.07:20:22.81#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:20:22.81#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:20:22.81#ibcon#about to clear, iclass 21 cls_cnt 0 2006.162.07:20:22.81#ibcon#cleared, iclass 21 cls_cnt 0 2006.162.07:20:22.81$vc4f8/vblo=6,752.99 2006.162.07:20:22.81#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.162.07:20:22.81#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.162.07:20:22.81#ibcon#ireg 17 cls_cnt 0 2006.162.07:20:22.81#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:20:22.81#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:20:22.81#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:20:22.81#ibcon#enter wrdev, iclass 23, count 0 2006.162.07:20:22.81#ibcon#first serial, iclass 23, count 0 2006.162.07:20:22.81#ibcon#enter sib2, iclass 23, count 0 2006.162.07:20:22.81#ibcon#flushed, iclass 23, count 0 2006.162.07:20:22.81#ibcon#about to write, iclass 23, count 0 2006.162.07:20:22.81#ibcon#wrote, iclass 23, count 0 2006.162.07:20:22.81#ibcon#about to read 3, iclass 23, count 0 2006.162.07:20:22.83#ibcon#read 3, iclass 23, count 0 2006.162.07:20:22.83#ibcon#about to read 4, iclass 23, count 0 2006.162.07:20:22.83#ibcon#read 4, iclass 23, count 0 2006.162.07:20:22.83#ibcon#about to read 5, iclass 23, count 0 2006.162.07:20:22.83#ibcon#read 5, iclass 23, count 0 2006.162.07:20:22.83#ibcon#about to read 6, iclass 23, count 0 2006.162.07:20:22.83#ibcon#read 6, iclass 23, count 0 2006.162.07:20:22.83#ibcon#end of sib2, iclass 23, count 0 2006.162.07:20:22.83#ibcon#*mode == 0, iclass 23, count 0 2006.162.07:20:22.83#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.162.07:20:22.83#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.07:20:22.83#ibcon#*before write, iclass 23, count 0 2006.162.07:20:22.83#ibcon#enter sib2, iclass 23, count 0 2006.162.07:20:22.83#ibcon#flushed, iclass 23, count 0 2006.162.07:20:22.83#ibcon#about to write, iclass 23, count 0 2006.162.07:20:22.83#ibcon#wrote, iclass 23, count 0 2006.162.07:20:22.83#ibcon#about to read 3, iclass 23, count 0 2006.162.07:20:22.87#ibcon#read 3, iclass 23, count 0 2006.162.07:20:22.87#ibcon#about to read 4, iclass 23, count 0 2006.162.07:20:22.87#ibcon#read 4, iclass 23, count 0 2006.162.07:20:22.87#ibcon#about to read 5, iclass 23, count 0 2006.162.07:20:22.87#ibcon#read 5, iclass 23, count 0 2006.162.07:20:22.87#ibcon#about to read 6, iclass 23, count 0 2006.162.07:20:22.87#ibcon#read 6, iclass 23, count 0 2006.162.07:20:22.87#ibcon#end of sib2, iclass 23, count 0 2006.162.07:20:22.87#ibcon#*after write, iclass 23, count 0 2006.162.07:20:22.87#ibcon#*before return 0, iclass 23, count 0 2006.162.07:20:22.87#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:20:22.87#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:20:22.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.162.07:20:22.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.162.07:20:22.87$vc4f8/vb=6,4 2006.162.07:20:22.87#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.162.07:20:22.87#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.162.07:20:22.87#ibcon#ireg 11 cls_cnt 2 2006.162.07:20:22.87#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.162.07:20:22.93#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.162.07:20:22.93#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.162.07:20:22.93#ibcon#enter wrdev, iclass 25, count 2 2006.162.07:20:22.93#ibcon#first serial, iclass 25, count 2 2006.162.07:20:22.93#ibcon#enter sib2, iclass 25, count 2 2006.162.07:20:22.93#ibcon#flushed, iclass 25, count 2 2006.162.07:20:22.93#ibcon#about to write, iclass 25, count 2 2006.162.07:20:22.93#ibcon#wrote, iclass 25, count 2 2006.162.07:20:22.93#ibcon#about to read 3, iclass 25, count 2 2006.162.07:20:22.95#ibcon#read 3, iclass 25, count 2 2006.162.07:20:22.95#ibcon#about to read 4, iclass 25, count 2 2006.162.07:20:22.95#ibcon#read 4, iclass 25, count 2 2006.162.07:20:22.95#ibcon#about to read 5, iclass 25, count 2 2006.162.07:20:22.95#ibcon#read 5, iclass 25, count 2 2006.162.07:20:22.95#ibcon#about to read 6, iclass 25, count 2 2006.162.07:20:22.95#ibcon#read 6, iclass 25, count 2 2006.162.07:20:22.95#ibcon#end of sib2, iclass 25, count 2 2006.162.07:20:22.95#ibcon#*mode == 0, iclass 25, count 2 2006.162.07:20:22.95#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.162.07:20:22.95#ibcon#[27=AT06-04\r\n] 2006.162.07:20:22.95#ibcon#*before write, iclass 25, count 2 2006.162.07:20:22.95#ibcon#enter sib2, iclass 25, count 2 2006.162.07:20:22.95#ibcon#flushed, iclass 25, count 2 2006.162.07:20:22.95#ibcon#about to write, iclass 25, count 2 2006.162.07:20:22.95#ibcon#wrote, iclass 25, count 2 2006.162.07:20:22.95#ibcon#about to read 3, iclass 25, count 2 2006.162.07:20:22.98#ibcon#read 3, iclass 25, count 2 2006.162.07:20:22.98#ibcon#about to read 4, iclass 25, count 2 2006.162.07:20:22.98#ibcon#read 4, iclass 25, count 2 2006.162.07:20:22.98#ibcon#about to read 5, iclass 25, count 2 2006.162.07:20:22.98#ibcon#read 5, iclass 25, count 2 2006.162.07:20:22.98#ibcon#about to read 6, iclass 25, count 2 2006.162.07:20:22.98#ibcon#read 6, iclass 25, count 2 2006.162.07:20:22.98#ibcon#end of sib2, iclass 25, count 2 2006.162.07:20:22.98#ibcon#*after write, iclass 25, count 2 2006.162.07:20:22.98#ibcon#*before return 0, iclass 25, count 2 2006.162.07:20:22.98#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.162.07:20:22.98#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.162.07:20:22.98#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.162.07:20:22.98#ibcon#ireg 7 cls_cnt 0 2006.162.07:20:22.98#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.162.07:20:23.10#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.162.07:20:23.10#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.162.07:20:23.10#ibcon#enter wrdev, iclass 25, count 0 2006.162.07:20:23.10#ibcon#first serial, iclass 25, count 0 2006.162.07:20:23.10#ibcon#enter sib2, iclass 25, count 0 2006.162.07:20:23.10#ibcon#flushed, iclass 25, count 0 2006.162.07:20:23.10#ibcon#about to write, iclass 25, count 0 2006.162.07:20:23.10#ibcon#wrote, iclass 25, count 0 2006.162.07:20:23.10#ibcon#about to read 3, iclass 25, count 0 2006.162.07:20:23.12#ibcon#read 3, iclass 25, count 0 2006.162.07:20:23.12#ibcon#about to read 4, iclass 25, count 0 2006.162.07:20:23.12#ibcon#read 4, iclass 25, count 0 2006.162.07:20:23.12#ibcon#about to read 5, iclass 25, count 0 2006.162.07:20:23.12#ibcon#read 5, iclass 25, count 0 2006.162.07:20:23.12#ibcon#about to read 6, iclass 25, count 0 2006.162.07:20:23.12#ibcon#read 6, iclass 25, count 0 2006.162.07:20:23.12#ibcon#end of sib2, iclass 25, count 0 2006.162.07:20:23.12#ibcon#*mode == 0, iclass 25, count 0 2006.162.07:20:23.12#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.162.07:20:23.12#ibcon#[27=USB\r\n] 2006.162.07:20:23.12#ibcon#*before write, iclass 25, count 0 2006.162.07:20:23.12#ibcon#enter sib2, iclass 25, count 0 2006.162.07:20:23.12#ibcon#flushed, iclass 25, count 0 2006.162.07:20:23.12#ibcon#about to write, iclass 25, count 0 2006.162.07:20:23.12#ibcon#wrote, iclass 25, count 0 2006.162.07:20:23.12#ibcon#about to read 3, iclass 25, count 0 2006.162.07:20:23.15#ibcon#read 3, iclass 25, count 0 2006.162.07:20:23.15#ibcon#about to read 4, iclass 25, count 0 2006.162.07:20:23.15#ibcon#read 4, iclass 25, count 0 2006.162.07:20:23.15#ibcon#about to read 5, iclass 25, count 0 2006.162.07:20:23.15#ibcon#read 5, iclass 25, count 0 2006.162.07:20:23.15#ibcon#about to read 6, iclass 25, count 0 2006.162.07:20:23.15#ibcon#read 6, iclass 25, count 0 2006.162.07:20:23.15#ibcon#end of sib2, iclass 25, count 0 2006.162.07:20:23.15#ibcon#*after write, iclass 25, count 0 2006.162.07:20:23.15#ibcon#*before return 0, iclass 25, count 0 2006.162.07:20:23.15#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.162.07:20:23.15#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.162.07:20:23.15#ibcon#about to clear, iclass 25 cls_cnt 0 2006.162.07:20:23.15#ibcon#cleared, iclass 25 cls_cnt 0 2006.162.07:20:23.15$vc4f8/vabw=wide 2006.162.07:20:23.15#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.162.07:20:23.15#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.162.07:20:23.15#ibcon#ireg 8 cls_cnt 0 2006.162.07:20:23.15#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:20:23.15#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:20:23.15#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:20:23.15#ibcon#enter wrdev, iclass 27, count 0 2006.162.07:20:23.15#ibcon#first serial, iclass 27, count 0 2006.162.07:20:23.15#ibcon#enter sib2, iclass 27, count 0 2006.162.07:20:23.15#ibcon#flushed, iclass 27, count 0 2006.162.07:20:23.15#ibcon#about to write, iclass 27, count 0 2006.162.07:20:23.15#ibcon#wrote, iclass 27, count 0 2006.162.07:20:23.15#ibcon#about to read 3, iclass 27, count 0 2006.162.07:20:23.17#ibcon#read 3, iclass 27, count 0 2006.162.07:20:23.17#ibcon#about to read 4, iclass 27, count 0 2006.162.07:20:23.17#ibcon#read 4, iclass 27, count 0 2006.162.07:20:23.17#ibcon#about to read 5, iclass 27, count 0 2006.162.07:20:23.17#ibcon#read 5, iclass 27, count 0 2006.162.07:20:23.17#ibcon#about to read 6, iclass 27, count 0 2006.162.07:20:23.17#ibcon#read 6, iclass 27, count 0 2006.162.07:20:23.17#ibcon#end of sib2, iclass 27, count 0 2006.162.07:20:23.17#ibcon#*mode == 0, iclass 27, count 0 2006.162.07:20:23.17#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.162.07:20:23.17#ibcon#[25=BW32\r\n] 2006.162.07:20:23.17#ibcon#*before write, iclass 27, count 0 2006.162.07:20:23.17#ibcon#enter sib2, iclass 27, count 0 2006.162.07:20:23.17#ibcon#flushed, iclass 27, count 0 2006.162.07:20:23.17#ibcon#about to write, iclass 27, count 0 2006.162.07:20:23.17#ibcon#wrote, iclass 27, count 0 2006.162.07:20:23.17#ibcon#about to read 3, iclass 27, count 0 2006.162.07:20:23.20#ibcon#read 3, iclass 27, count 0 2006.162.07:20:23.20#ibcon#about to read 4, iclass 27, count 0 2006.162.07:20:23.20#ibcon#read 4, iclass 27, count 0 2006.162.07:20:23.20#ibcon#about to read 5, iclass 27, count 0 2006.162.07:20:23.20#ibcon#read 5, iclass 27, count 0 2006.162.07:20:23.20#ibcon#about to read 6, iclass 27, count 0 2006.162.07:20:23.20#ibcon#read 6, iclass 27, count 0 2006.162.07:20:23.20#ibcon#end of sib2, iclass 27, count 0 2006.162.07:20:23.20#ibcon#*after write, iclass 27, count 0 2006.162.07:20:23.20#ibcon#*before return 0, iclass 27, count 0 2006.162.07:20:23.20#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:20:23.20#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:20:23.20#ibcon#about to clear, iclass 27 cls_cnt 0 2006.162.07:20:23.20#ibcon#cleared, iclass 27 cls_cnt 0 2006.162.07:20:23.20$vc4f8/vbbw=wide 2006.162.07:20:23.20#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.162.07:20:23.20#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.162.07:20:23.20#ibcon#ireg 8 cls_cnt 0 2006.162.07:20:23.20#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.162.07:20:23.27#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.162.07:20:23.27#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.162.07:20:23.27#ibcon#enter wrdev, iclass 29, count 0 2006.162.07:20:23.27#ibcon#first serial, iclass 29, count 0 2006.162.07:20:23.27#ibcon#enter sib2, iclass 29, count 0 2006.162.07:20:23.27#ibcon#flushed, iclass 29, count 0 2006.162.07:20:23.27#ibcon#about to write, iclass 29, count 0 2006.162.07:20:23.27#ibcon#wrote, iclass 29, count 0 2006.162.07:20:23.27#ibcon#about to read 3, iclass 29, count 0 2006.162.07:20:23.29#ibcon#read 3, iclass 29, count 0 2006.162.07:20:23.29#ibcon#about to read 4, iclass 29, count 0 2006.162.07:20:23.29#ibcon#read 4, iclass 29, count 0 2006.162.07:20:23.29#ibcon#about to read 5, iclass 29, count 0 2006.162.07:20:23.29#ibcon#read 5, iclass 29, count 0 2006.162.07:20:23.29#ibcon#about to read 6, iclass 29, count 0 2006.162.07:20:23.29#ibcon#read 6, iclass 29, count 0 2006.162.07:20:23.29#ibcon#end of sib2, iclass 29, count 0 2006.162.07:20:23.29#ibcon#*mode == 0, iclass 29, count 0 2006.162.07:20:23.29#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.162.07:20:23.29#ibcon#[27=BW32\r\n] 2006.162.07:20:23.29#ibcon#*before write, iclass 29, count 0 2006.162.07:20:23.29#ibcon#enter sib2, iclass 29, count 0 2006.162.07:20:23.29#ibcon#flushed, iclass 29, count 0 2006.162.07:20:23.29#ibcon#about to write, iclass 29, count 0 2006.162.07:20:23.29#ibcon#wrote, iclass 29, count 0 2006.162.07:20:23.29#ibcon#about to read 3, iclass 29, count 0 2006.162.07:20:23.32#ibcon#read 3, iclass 29, count 0 2006.162.07:20:23.32#ibcon#about to read 4, iclass 29, count 0 2006.162.07:20:23.32#ibcon#read 4, iclass 29, count 0 2006.162.07:20:23.32#ibcon#about to read 5, iclass 29, count 0 2006.162.07:20:23.32#ibcon#read 5, iclass 29, count 0 2006.162.07:20:23.32#ibcon#about to read 6, iclass 29, count 0 2006.162.07:20:23.32#ibcon#read 6, iclass 29, count 0 2006.162.07:20:23.32#ibcon#end of sib2, iclass 29, count 0 2006.162.07:20:23.32#ibcon#*after write, iclass 29, count 0 2006.162.07:20:23.32#ibcon#*before return 0, iclass 29, count 0 2006.162.07:20:23.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.162.07:20:23.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.162.07:20:23.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.162.07:20:23.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.162.07:20:23.32$4f8m12a/ifd4f 2006.162.07:20:23.32&ifd4f/lo= 2006.162.07:20:23.32&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.07:20:23.32&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.07:20:23.32&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.07:20:23.32&ifd4f/patch= 2006.162.07:20:23.32&ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.07:20:23.32&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.07:20:23.32&ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.07:20:23.32$ifd4f/lo= 2006.162.07:20:23.32$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.07:20:23.32$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.07:20:23.33$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.07:20:23.33$ifd4f/patch= 2006.162.07:20:23.33$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.07:20:23.33$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.07:20:23.33$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.07:20:23.33$4f8m12a/"form=m,16.000,1:2 2006.162.07:20:23.33$4f8m12a/"tpicd 2006.162.07:20:23.33$4f8m12a/echo=off 2006.162.07:20:23.33$4f8m12a/xlog=off 2006.162.07:20:23.33:!2006.162.07:29:50 2006.162.07:20:38.14#trakl#Source acquired 2006.162.07:20:38.14#flagr#flagr/antenna,acquired 2006.162.07:29:50.00:preob 2006.162.07:29:50.00&preob/onsource 2006.162.07:29:51.14/onsource/TRACKING 2006.162.07:29:51.14:!2006.162.07:30:00 2006.162.07:30:00.00:data_valid=on 2006.162.07:30:00.00:midob 2006.162.07:30:00.00&midob/onsource 2006.162.07:30:00.00&midob/wx 2006.162.07:30:00.00&midob/cable 2006.162.07:30:00.00&midob/va 2006.162.07:30:00.00&midob/valo 2006.162.07:30:00.00&midob/vb 2006.162.07:30:00.00&midob/vblo 2006.162.07:30:00.00&midob/vabw 2006.162.07:30:00.00&midob/vbbw 2006.162.07:30:00.00&midob/"form 2006.162.07:30:00.00&midob/xfe 2006.162.07:30:00.00&midob/ifatt 2006.162.07:30:00.00&midob/clockoff 2006.162.07:30:00.00&midob/sy=logmail 2006.162.07:30:00.00&midob/"sy=run setcl adapt & 2006.162.07:30:00.14/onsource/TRACKING 2006.162.07:30:00.14/wx/17.89,1007.2,100 2006.162.07:30:00.29/cable/+6.5323E-03 2006.162.07:30:01.38/va/01,08,usb,yes,41,43 2006.162.07:30:01.38/va/02,07,usb,yes,41,43 2006.162.07:30:01.38/va/03,06,usb,yes,44,44 2006.162.07:30:01.38/va/04,07,usb,yes,42,45 2006.162.07:30:01.38/va/05,07,usb,yes,45,48 2006.162.07:30:01.38/va/06,06,usb,yes,45,44 2006.162.07:30:01.38/va/07,06,usb,yes,45,45 2006.162.07:30:01.38/va/08,07,usb,yes,43,42 2006.162.07:30:01.61/valo/01,532.99,yes,locked 2006.162.07:30:01.61/valo/02,572.99,yes,locked 2006.162.07:30:01.61/valo/03,672.99,yes,locked 2006.162.07:30:01.61/valo/04,832.99,yes,locked 2006.162.07:30:01.61/valo/05,652.99,yes,locked 2006.162.07:30:01.61/valo/06,772.99,yes,locked 2006.162.07:30:01.61/valo/07,832.99,yes,locked 2006.162.07:30:01.61/valo/08,852.99,yes,locked 2006.162.07:30:02.70/vb/01,04,usb,yes,30,29 2006.162.07:30:02.70/vb/02,04,usb,yes,32,33 2006.162.07:30:02.70/vb/03,04,usb,yes,28,32 2006.162.07:30:02.70/vb/04,04,usb,yes,29,30 2006.162.07:30:02.70/vb/05,04,usb,yes,28,32 2006.162.07:30:02.70/vb/06,04,usb,yes,29,32 2006.162.07:30:02.70/vb/07,04,usb,yes,31,31 2006.162.07:30:02.70/vb/08,04,usb,yes,29,32 2006.162.07:30:02.93/vblo/01,632.99,yes,locked 2006.162.07:30:02.93/vblo/02,640.99,yes,locked 2006.162.07:30:02.93/vblo/03,656.99,yes,locked 2006.162.07:30:02.93/vblo/04,712.99,yes,locked 2006.162.07:30:02.93/vblo/05,744.99,yes,locked 2006.162.07:30:02.93/vblo/06,752.99,yes,locked 2006.162.07:30:02.93/vblo/07,734.99,yes,locked 2006.162.07:30:02.93/vblo/08,744.99,yes,locked 2006.162.07:30:03.08/vabw/8 2006.162.07:30:03.23/vbbw/8 2006.162.07:30:03.32/xfe/off,on,14.5 2006.162.07:30:03.69/ifatt/23,28,28,28 2006.162.07:30:03.69&clockoff/"gps-fmout=1p 2006.162.07:30:03.69&clockoff/fmout-gps=1p 2006.162.07:30:04.08/fmout-gps/S +4.50E-07 2006.162.07:30:04.17:!2006.162.07:31:00 2006.162.07:31:00.00:data_valid=off 2006.162.07:31:00.01:postob 2006.162.07:31:00.01&postob/cable 2006.162.07:31:00.01&postob/wx 2006.162.07:31:00.02&postob/clockoff 2006.162.07:31:00.09/cable/+6.5345E-03 2006.162.07:31:00.10/wx/17.90,1007.2,100 2006.162.07:31:01.08/fmout-gps/S +4.50E-07 2006.162.07:31:01.09:scan_name=162-0733,k06162,60 2006.162.07:31:01.09:source=0743+259,074625.87,254902.1,2000.0,ccw 2006.162.07:31:01.14#flagr#flagr/antenna,new-source 2006.162.07:31:02.14:checkk5 2006.162.07:31:02.15&checkk5/chk_autoobs=1 2006.162.07:31:02.15&checkk5/chk_autoobs=2 2006.162.07:31:02.15&checkk5/chk_autoobs=3 2006.162.07:31:02.15&checkk5/chk_autoobs=4 2006.162.07:31:02.15&checkk5/chk_obsdata=1 2006.162.07:31:02.15&checkk5/chk_obsdata=2 2006.162.07:31:02.15&checkk5/chk_obsdata=3 2006.162.07:31:02.15&checkk5/chk_obsdata=4 2006.162.07:31:02.15&checkk5/k5log=1 2006.162.07:31:02.15&checkk5/k5log=2 2006.162.07:31:02.15&checkk5/k5log=3 2006.162.07:31:02.15&checkk5/k5log=4 2006.162.07:31:02.15&checkk5/obsinfo 2006.162.07:31:02.60/chk_autoobs//k5ts1/ autoobs is running! 2006.162.07:31:03.08/chk_autoobs//k5ts2/ autoobs is running! 2006.162.07:31:03.53/chk_autoobs//k5ts3/ autoobs is running! 2006.162.07:31:03.97/chk_autoobs//k5ts4/ autoobs is running! 2006.162.07:31:04.42/chk_obsdata//k5ts1/T1620730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:31:04.86/chk_obsdata//k5ts2/T1620730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:31:05.26/chk_obsdata//k5ts3/T1620730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:31:05.65/chk_obsdata//k5ts4/T1620730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:31:06.47/k5log//k5ts1_log_newline 2006.162.07:31:07.29/k5log//k5ts2_log_newline 2006.162.07:31:08.08/k5log//k5ts3_log_newline 2006.162.07:31:08.85/k5log//k5ts4_log_newline 2006.162.07:31:08.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.07:31:08.88:4f8m12a=1 2006.162.07:31:08.88$4f8m12a/echo=on 2006.162.07:31:08.88$4f8m12a/pcalon 2006.162.07:31:08.88$pcalon/"no phase cal control is implemented here 2006.162.07:31:08.88$4f8m12a/"tpicd=stop 2006.162.07:31:08.88$4f8m12a/vc4f8 2006.162.07:31:08.88$vc4f8/valo=1,532.99 2006.162.07:31:08.88#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.162.07:31:08.88#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.162.07:31:08.88#ibcon#ireg 17 cls_cnt 0 2006.162.07:31:08.88#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:31:08.88#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:31:08.88#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:31:08.88#ibcon#enter wrdev, iclass 36, count 0 2006.162.07:31:08.88#ibcon#first serial, iclass 36, count 0 2006.162.07:31:08.88#ibcon#enter sib2, iclass 36, count 0 2006.162.07:31:08.88#ibcon#flushed, iclass 36, count 0 2006.162.07:31:08.88#ibcon#about to write, iclass 36, count 0 2006.162.07:31:08.88#ibcon#wrote, iclass 36, count 0 2006.162.07:31:08.88#ibcon#about to read 3, iclass 36, count 0 2006.162.07:31:08.93#ibcon#read 3, iclass 36, count 0 2006.162.07:31:08.93#ibcon#about to read 4, iclass 36, count 0 2006.162.07:31:08.93#ibcon#read 4, iclass 36, count 0 2006.162.07:31:08.93#ibcon#about to read 5, iclass 36, count 0 2006.162.07:31:08.93#ibcon#read 5, iclass 36, count 0 2006.162.07:31:08.93#ibcon#about to read 6, iclass 36, count 0 2006.162.07:31:08.93#ibcon#read 6, iclass 36, count 0 2006.162.07:31:08.93#ibcon#end of sib2, iclass 36, count 0 2006.162.07:31:08.93#ibcon#*mode == 0, iclass 36, count 0 2006.162.07:31:08.93#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.162.07:31:08.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.07:31:08.93#ibcon#*before write, iclass 36, count 0 2006.162.07:31:08.93#ibcon#enter sib2, iclass 36, count 0 2006.162.07:31:08.93#ibcon#flushed, iclass 36, count 0 2006.162.07:31:08.93#ibcon#about to write, iclass 36, count 0 2006.162.07:31:08.93#ibcon#wrote, iclass 36, count 0 2006.162.07:31:08.93#ibcon#about to read 3, iclass 36, count 0 2006.162.07:31:08.97#ibcon#read 3, iclass 36, count 0 2006.162.07:31:08.97#ibcon#about to read 4, iclass 36, count 0 2006.162.07:31:08.97#ibcon#read 4, iclass 36, count 0 2006.162.07:31:08.97#ibcon#about to read 5, iclass 36, count 0 2006.162.07:31:08.97#ibcon#read 5, iclass 36, count 0 2006.162.07:31:08.97#ibcon#about to read 6, iclass 36, count 0 2006.162.07:31:08.97#ibcon#read 6, iclass 36, count 0 2006.162.07:31:08.97#ibcon#end of sib2, iclass 36, count 0 2006.162.07:31:08.97#ibcon#*after write, iclass 36, count 0 2006.162.07:31:08.97#ibcon#*before return 0, iclass 36, count 0 2006.162.07:31:08.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:31:08.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:31:08.97#ibcon#about to clear, iclass 36 cls_cnt 0 2006.162.07:31:08.97#ibcon#cleared, iclass 36 cls_cnt 0 2006.162.07:31:08.97$vc4f8/va=1,8 2006.162.07:31:08.97#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.162.07:31:08.97#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.162.07:31:08.97#ibcon#ireg 11 cls_cnt 2 2006.162.07:31:08.97#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:31:08.97#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:31:08.97#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:31:08.97#ibcon#enter wrdev, iclass 38, count 2 2006.162.07:31:08.97#ibcon#first serial, iclass 38, count 2 2006.162.07:31:08.97#ibcon#enter sib2, iclass 38, count 2 2006.162.07:31:08.97#ibcon#flushed, iclass 38, count 2 2006.162.07:31:08.97#ibcon#about to write, iclass 38, count 2 2006.162.07:31:08.97#ibcon#wrote, iclass 38, count 2 2006.162.07:31:08.97#ibcon#about to read 3, iclass 38, count 2 2006.162.07:31:09.00#ibcon#read 3, iclass 38, count 2 2006.162.07:31:09.00#ibcon#about to read 4, iclass 38, count 2 2006.162.07:31:09.00#ibcon#read 4, iclass 38, count 2 2006.162.07:31:09.00#ibcon#about to read 5, iclass 38, count 2 2006.162.07:31:09.00#ibcon#read 5, iclass 38, count 2 2006.162.07:31:09.00#ibcon#about to read 6, iclass 38, count 2 2006.162.07:31:09.00#ibcon#read 6, iclass 38, count 2 2006.162.07:31:09.00#ibcon#end of sib2, iclass 38, count 2 2006.162.07:31:09.00#ibcon#*mode == 0, iclass 38, count 2 2006.162.07:31:09.00#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.162.07:31:09.00#ibcon#[25=AT01-08\r\n] 2006.162.07:31:09.00#ibcon#*before write, iclass 38, count 2 2006.162.07:31:09.00#ibcon#enter sib2, iclass 38, count 2 2006.162.07:31:09.00#ibcon#flushed, iclass 38, count 2 2006.162.07:31:09.00#ibcon#about to write, iclass 38, count 2 2006.162.07:31:09.00#ibcon#wrote, iclass 38, count 2 2006.162.07:31:09.00#ibcon#about to read 3, iclass 38, count 2 2006.162.07:31:09.03#ibcon#read 3, iclass 38, count 2 2006.162.07:31:09.03#ibcon#about to read 4, iclass 38, count 2 2006.162.07:31:09.03#ibcon#read 4, iclass 38, count 2 2006.162.07:31:09.03#ibcon#about to read 5, iclass 38, count 2 2006.162.07:31:09.03#ibcon#read 5, iclass 38, count 2 2006.162.07:31:09.03#ibcon#about to read 6, iclass 38, count 2 2006.162.07:31:09.03#ibcon#read 6, iclass 38, count 2 2006.162.07:31:09.03#ibcon#end of sib2, iclass 38, count 2 2006.162.07:31:09.03#ibcon#*after write, iclass 38, count 2 2006.162.07:31:09.03#ibcon#*before return 0, iclass 38, count 2 2006.162.07:31:09.03#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:31:09.03#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:31:09.03#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.162.07:31:09.03#ibcon#ireg 7 cls_cnt 0 2006.162.07:31:09.03#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:31:09.15#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:31:09.15#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:31:09.15#ibcon#enter wrdev, iclass 38, count 0 2006.162.07:31:09.15#ibcon#first serial, iclass 38, count 0 2006.162.07:31:09.15#ibcon#enter sib2, iclass 38, count 0 2006.162.07:31:09.15#ibcon#flushed, iclass 38, count 0 2006.162.07:31:09.15#ibcon#about to write, iclass 38, count 0 2006.162.07:31:09.15#ibcon#wrote, iclass 38, count 0 2006.162.07:31:09.15#ibcon#about to read 3, iclass 38, count 0 2006.162.07:31:09.17#ibcon#read 3, iclass 38, count 0 2006.162.07:31:09.17#ibcon#about to read 4, iclass 38, count 0 2006.162.07:31:09.17#ibcon#read 4, iclass 38, count 0 2006.162.07:31:09.17#ibcon#about to read 5, iclass 38, count 0 2006.162.07:31:09.17#ibcon#read 5, iclass 38, count 0 2006.162.07:31:09.17#ibcon#about to read 6, iclass 38, count 0 2006.162.07:31:09.17#ibcon#read 6, iclass 38, count 0 2006.162.07:31:09.17#ibcon#end of sib2, iclass 38, count 0 2006.162.07:31:09.17#ibcon#*mode == 0, iclass 38, count 0 2006.162.07:31:09.17#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.162.07:31:09.17#ibcon#[25=USB\r\n] 2006.162.07:31:09.17#ibcon#*before write, iclass 38, count 0 2006.162.07:31:09.17#ibcon#enter sib2, iclass 38, count 0 2006.162.07:31:09.17#ibcon#flushed, iclass 38, count 0 2006.162.07:31:09.17#ibcon#about to write, iclass 38, count 0 2006.162.07:31:09.17#ibcon#wrote, iclass 38, count 0 2006.162.07:31:09.17#ibcon#about to read 3, iclass 38, count 0 2006.162.07:31:09.20#ibcon#read 3, iclass 38, count 0 2006.162.07:31:09.20#ibcon#about to read 4, iclass 38, count 0 2006.162.07:31:09.20#ibcon#read 4, iclass 38, count 0 2006.162.07:31:09.20#ibcon#about to read 5, iclass 38, count 0 2006.162.07:31:09.20#ibcon#read 5, iclass 38, count 0 2006.162.07:31:09.20#ibcon#about to read 6, iclass 38, count 0 2006.162.07:31:09.20#ibcon#read 6, iclass 38, count 0 2006.162.07:31:09.20#ibcon#end of sib2, iclass 38, count 0 2006.162.07:31:09.20#ibcon#*after write, iclass 38, count 0 2006.162.07:31:09.20#ibcon#*before return 0, iclass 38, count 0 2006.162.07:31:09.20#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:31:09.20#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:31:09.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.162.07:31:09.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.162.07:31:09.20$vc4f8/valo=2,572.99 2006.162.07:31:09.21#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.162.07:31:09.21#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.162.07:31:09.21#ibcon#ireg 17 cls_cnt 0 2006.162.07:31:09.21#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:31:09.21#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:31:09.21#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:31:09.21#ibcon#enter wrdev, iclass 40, count 0 2006.162.07:31:09.21#ibcon#first serial, iclass 40, count 0 2006.162.07:31:09.21#ibcon#enter sib2, iclass 40, count 0 2006.162.07:31:09.21#ibcon#flushed, iclass 40, count 0 2006.162.07:31:09.21#ibcon#about to write, iclass 40, count 0 2006.162.07:31:09.21#ibcon#wrote, iclass 40, count 0 2006.162.07:31:09.21#ibcon#about to read 3, iclass 40, count 0 2006.162.07:31:09.22#ibcon#read 3, iclass 40, count 0 2006.162.07:31:09.22#ibcon#about to read 4, iclass 40, count 0 2006.162.07:31:09.22#ibcon#read 4, iclass 40, count 0 2006.162.07:31:09.22#ibcon#about to read 5, iclass 40, count 0 2006.162.07:31:09.22#ibcon#read 5, iclass 40, count 0 2006.162.07:31:09.22#ibcon#about to read 6, iclass 40, count 0 2006.162.07:31:09.22#ibcon#read 6, iclass 40, count 0 2006.162.07:31:09.22#ibcon#end of sib2, iclass 40, count 0 2006.162.07:31:09.22#ibcon#*mode == 0, iclass 40, count 0 2006.162.07:31:09.22#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.162.07:31:09.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.07:31:09.22#ibcon#*before write, iclass 40, count 0 2006.162.07:31:09.22#ibcon#enter sib2, iclass 40, count 0 2006.162.07:31:09.22#ibcon#flushed, iclass 40, count 0 2006.162.07:31:09.22#ibcon#about to write, iclass 40, count 0 2006.162.07:31:09.22#ibcon#wrote, iclass 40, count 0 2006.162.07:31:09.22#ibcon#about to read 3, iclass 40, count 0 2006.162.07:31:09.26#ibcon#read 3, iclass 40, count 0 2006.162.07:31:09.26#ibcon#about to read 4, iclass 40, count 0 2006.162.07:31:09.26#ibcon#read 4, iclass 40, count 0 2006.162.07:31:09.26#ibcon#about to read 5, iclass 40, count 0 2006.162.07:31:09.26#ibcon#read 5, iclass 40, count 0 2006.162.07:31:09.26#ibcon#about to read 6, iclass 40, count 0 2006.162.07:31:09.26#ibcon#read 6, iclass 40, count 0 2006.162.07:31:09.26#ibcon#end of sib2, iclass 40, count 0 2006.162.07:31:09.26#ibcon#*after write, iclass 40, count 0 2006.162.07:31:09.26#ibcon#*before return 0, iclass 40, count 0 2006.162.07:31:09.26#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:31:09.26#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:31:09.26#ibcon#about to clear, iclass 40 cls_cnt 0 2006.162.07:31:09.26#ibcon#cleared, iclass 40 cls_cnt 0 2006.162.07:31:09.26$vc4f8/va=2,7 2006.162.07:31:09.26#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.162.07:31:09.26#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.162.07:31:09.26#ibcon#ireg 11 cls_cnt 2 2006.162.07:31:09.26#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:31:09.33#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:31:09.33#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:31:09.33#ibcon#enter wrdev, iclass 4, count 2 2006.162.07:31:09.33#ibcon#first serial, iclass 4, count 2 2006.162.07:31:09.33#ibcon#enter sib2, iclass 4, count 2 2006.162.07:31:09.33#ibcon#flushed, iclass 4, count 2 2006.162.07:31:09.33#ibcon#about to write, iclass 4, count 2 2006.162.07:31:09.33#ibcon#wrote, iclass 4, count 2 2006.162.07:31:09.33#ibcon#about to read 3, iclass 4, count 2 2006.162.07:31:09.34#ibcon#read 3, iclass 4, count 2 2006.162.07:31:09.34#ibcon#about to read 4, iclass 4, count 2 2006.162.07:31:09.34#ibcon#read 4, iclass 4, count 2 2006.162.07:31:09.34#ibcon#about to read 5, iclass 4, count 2 2006.162.07:31:09.34#ibcon#read 5, iclass 4, count 2 2006.162.07:31:09.34#ibcon#about to read 6, iclass 4, count 2 2006.162.07:31:09.34#ibcon#read 6, iclass 4, count 2 2006.162.07:31:09.34#ibcon#end of sib2, iclass 4, count 2 2006.162.07:31:09.34#ibcon#*mode == 0, iclass 4, count 2 2006.162.07:31:09.34#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.162.07:31:09.34#ibcon#[25=AT02-07\r\n] 2006.162.07:31:09.34#ibcon#*before write, iclass 4, count 2 2006.162.07:31:09.34#ibcon#enter sib2, iclass 4, count 2 2006.162.07:31:09.34#ibcon#flushed, iclass 4, count 2 2006.162.07:31:09.34#ibcon#about to write, iclass 4, count 2 2006.162.07:31:09.34#ibcon#wrote, iclass 4, count 2 2006.162.07:31:09.34#ibcon#about to read 3, iclass 4, count 2 2006.162.07:31:09.37#ibcon#read 3, iclass 4, count 2 2006.162.07:31:09.37#ibcon#about to read 4, iclass 4, count 2 2006.162.07:31:09.37#ibcon#read 4, iclass 4, count 2 2006.162.07:31:09.37#ibcon#about to read 5, iclass 4, count 2 2006.162.07:31:09.37#ibcon#read 5, iclass 4, count 2 2006.162.07:31:09.37#ibcon#about to read 6, iclass 4, count 2 2006.162.07:31:09.37#ibcon#read 6, iclass 4, count 2 2006.162.07:31:09.37#ibcon#end of sib2, iclass 4, count 2 2006.162.07:31:09.37#ibcon#*after write, iclass 4, count 2 2006.162.07:31:09.37#ibcon#*before return 0, iclass 4, count 2 2006.162.07:31:09.37#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:31:09.37#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:31:09.37#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.162.07:31:09.37#ibcon#ireg 7 cls_cnt 0 2006.162.07:31:09.37#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:31:09.49#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:31:09.49#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:31:09.49#ibcon#enter wrdev, iclass 4, count 0 2006.162.07:31:09.49#ibcon#first serial, iclass 4, count 0 2006.162.07:31:09.49#ibcon#enter sib2, iclass 4, count 0 2006.162.07:31:09.49#ibcon#flushed, iclass 4, count 0 2006.162.07:31:09.49#ibcon#about to write, iclass 4, count 0 2006.162.07:31:09.49#ibcon#wrote, iclass 4, count 0 2006.162.07:31:09.49#ibcon#about to read 3, iclass 4, count 0 2006.162.07:31:09.51#ibcon#read 3, iclass 4, count 0 2006.162.07:31:09.51#ibcon#about to read 4, iclass 4, count 0 2006.162.07:31:09.51#ibcon#read 4, iclass 4, count 0 2006.162.07:31:09.51#ibcon#about to read 5, iclass 4, count 0 2006.162.07:31:09.51#ibcon#read 5, iclass 4, count 0 2006.162.07:31:09.51#ibcon#about to read 6, iclass 4, count 0 2006.162.07:31:09.51#ibcon#read 6, iclass 4, count 0 2006.162.07:31:09.51#ibcon#end of sib2, iclass 4, count 0 2006.162.07:31:09.51#ibcon#*mode == 0, iclass 4, count 0 2006.162.07:31:09.51#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.162.07:31:09.51#ibcon#[25=USB\r\n] 2006.162.07:31:09.51#ibcon#*before write, iclass 4, count 0 2006.162.07:31:09.51#ibcon#enter sib2, iclass 4, count 0 2006.162.07:31:09.51#ibcon#flushed, iclass 4, count 0 2006.162.07:31:09.51#ibcon#about to write, iclass 4, count 0 2006.162.07:31:09.51#ibcon#wrote, iclass 4, count 0 2006.162.07:31:09.51#ibcon#about to read 3, iclass 4, count 0 2006.162.07:31:09.54#ibcon#read 3, iclass 4, count 0 2006.162.07:31:09.54#ibcon#about to read 4, iclass 4, count 0 2006.162.07:31:09.54#ibcon#read 4, iclass 4, count 0 2006.162.07:31:09.54#ibcon#about to read 5, iclass 4, count 0 2006.162.07:31:09.54#ibcon#read 5, iclass 4, count 0 2006.162.07:31:09.54#ibcon#about to read 6, iclass 4, count 0 2006.162.07:31:09.54#ibcon#read 6, iclass 4, count 0 2006.162.07:31:09.54#ibcon#end of sib2, iclass 4, count 0 2006.162.07:31:09.54#ibcon#*after write, iclass 4, count 0 2006.162.07:31:09.54#ibcon#*before return 0, iclass 4, count 0 2006.162.07:31:09.54#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:31:09.54#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:31:09.54#ibcon#about to clear, iclass 4 cls_cnt 0 2006.162.07:31:09.54#ibcon#cleared, iclass 4 cls_cnt 0 2006.162.07:31:09.54$vc4f8/valo=3,672.99 2006.162.07:31:09.54#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.162.07:31:09.54#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.162.07:31:09.54#ibcon#ireg 17 cls_cnt 0 2006.162.07:31:09.54#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:31:09.54#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:31:09.54#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:31:09.54#ibcon#enter wrdev, iclass 6, count 0 2006.162.07:31:09.54#ibcon#first serial, iclass 6, count 0 2006.162.07:31:09.54#ibcon#enter sib2, iclass 6, count 0 2006.162.07:31:09.54#ibcon#flushed, iclass 6, count 0 2006.162.07:31:09.54#ibcon#about to write, iclass 6, count 0 2006.162.07:31:09.54#ibcon#wrote, iclass 6, count 0 2006.162.07:31:09.54#ibcon#about to read 3, iclass 6, count 0 2006.162.07:31:09.56#ibcon#read 3, iclass 6, count 0 2006.162.07:31:09.56#ibcon#about to read 4, iclass 6, count 0 2006.162.07:31:09.56#ibcon#read 4, iclass 6, count 0 2006.162.07:31:09.56#ibcon#about to read 5, iclass 6, count 0 2006.162.07:31:09.56#ibcon#read 5, iclass 6, count 0 2006.162.07:31:09.56#ibcon#about to read 6, iclass 6, count 0 2006.162.07:31:09.56#ibcon#read 6, iclass 6, count 0 2006.162.07:31:09.56#ibcon#end of sib2, iclass 6, count 0 2006.162.07:31:09.56#ibcon#*mode == 0, iclass 6, count 0 2006.162.07:31:09.56#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.162.07:31:09.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.07:31:09.56#ibcon#*before write, iclass 6, count 0 2006.162.07:31:09.56#ibcon#enter sib2, iclass 6, count 0 2006.162.07:31:09.56#ibcon#flushed, iclass 6, count 0 2006.162.07:31:09.56#ibcon#about to write, iclass 6, count 0 2006.162.07:31:09.56#ibcon#wrote, iclass 6, count 0 2006.162.07:31:09.56#ibcon#about to read 3, iclass 6, count 0 2006.162.07:31:09.60#ibcon#read 3, iclass 6, count 0 2006.162.07:31:09.60#ibcon#about to read 4, iclass 6, count 0 2006.162.07:31:09.60#ibcon#read 4, iclass 6, count 0 2006.162.07:31:09.60#ibcon#about to read 5, iclass 6, count 0 2006.162.07:31:09.60#ibcon#read 5, iclass 6, count 0 2006.162.07:31:09.60#ibcon#about to read 6, iclass 6, count 0 2006.162.07:31:09.60#ibcon#read 6, iclass 6, count 0 2006.162.07:31:09.60#ibcon#end of sib2, iclass 6, count 0 2006.162.07:31:09.60#ibcon#*after write, iclass 6, count 0 2006.162.07:31:09.60#ibcon#*before return 0, iclass 6, count 0 2006.162.07:31:09.60#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:31:09.60#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:31:09.60#ibcon#about to clear, iclass 6 cls_cnt 0 2006.162.07:31:09.60#ibcon#cleared, iclass 6 cls_cnt 0 2006.162.07:31:09.60$vc4f8/va=3,6 2006.162.07:31:09.60#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.162.07:31:09.60#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.162.07:31:09.60#ibcon#ireg 11 cls_cnt 2 2006.162.07:31:09.60#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:31:09.66#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:31:09.66#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:31:09.66#ibcon#enter wrdev, iclass 10, count 2 2006.162.07:31:09.66#ibcon#first serial, iclass 10, count 2 2006.162.07:31:09.66#ibcon#enter sib2, iclass 10, count 2 2006.162.07:31:09.66#ibcon#flushed, iclass 10, count 2 2006.162.07:31:09.66#ibcon#about to write, iclass 10, count 2 2006.162.07:31:09.66#ibcon#wrote, iclass 10, count 2 2006.162.07:31:09.66#ibcon#about to read 3, iclass 10, count 2 2006.162.07:31:09.69#ibcon#read 3, iclass 10, count 2 2006.162.07:31:09.69#ibcon#about to read 4, iclass 10, count 2 2006.162.07:31:09.69#ibcon#read 4, iclass 10, count 2 2006.162.07:31:09.69#ibcon#about to read 5, iclass 10, count 2 2006.162.07:31:09.69#ibcon#read 5, iclass 10, count 2 2006.162.07:31:09.69#ibcon#about to read 6, iclass 10, count 2 2006.162.07:31:09.69#ibcon#read 6, iclass 10, count 2 2006.162.07:31:09.69#ibcon#end of sib2, iclass 10, count 2 2006.162.07:31:09.69#ibcon#*mode == 0, iclass 10, count 2 2006.162.07:31:09.69#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.162.07:31:09.69#ibcon#[25=AT03-06\r\n] 2006.162.07:31:09.69#ibcon#*before write, iclass 10, count 2 2006.162.07:31:09.69#ibcon#enter sib2, iclass 10, count 2 2006.162.07:31:09.69#ibcon#flushed, iclass 10, count 2 2006.162.07:31:09.69#ibcon#about to write, iclass 10, count 2 2006.162.07:31:09.69#ibcon#wrote, iclass 10, count 2 2006.162.07:31:09.69#ibcon#about to read 3, iclass 10, count 2 2006.162.07:31:09.72#ibcon#read 3, iclass 10, count 2 2006.162.07:31:09.72#ibcon#about to read 4, iclass 10, count 2 2006.162.07:31:09.72#ibcon#read 4, iclass 10, count 2 2006.162.07:31:09.72#ibcon#about to read 5, iclass 10, count 2 2006.162.07:31:09.72#ibcon#read 5, iclass 10, count 2 2006.162.07:31:09.72#ibcon#about to read 6, iclass 10, count 2 2006.162.07:31:09.72#ibcon#read 6, iclass 10, count 2 2006.162.07:31:09.72#ibcon#end of sib2, iclass 10, count 2 2006.162.07:31:09.72#ibcon#*after write, iclass 10, count 2 2006.162.07:31:09.72#ibcon#*before return 0, iclass 10, count 2 2006.162.07:31:09.72#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:31:09.72#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:31:09.72#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.162.07:31:09.72#ibcon#ireg 7 cls_cnt 0 2006.162.07:31:09.72#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:31:09.84#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:31:09.84#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:31:09.84#ibcon#enter wrdev, iclass 10, count 0 2006.162.07:31:09.84#ibcon#first serial, iclass 10, count 0 2006.162.07:31:09.84#ibcon#enter sib2, iclass 10, count 0 2006.162.07:31:09.84#ibcon#flushed, iclass 10, count 0 2006.162.07:31:09.84#ibcon#about to write, iclass 10, count 0 2006.162.07:31:09.84#ibcon#wrote, iclass 10, count 0 2006.162.07:31:09.84#ibcon#about to read 3, iclass 10, count 0 2006.162.07:31:09.86#ibcon#read 3, iclass 10, count 0 2006.162.07:31:09.86#ibcon#about to read 4, iclass 10, count 0 2006.162.07:31:09.86#ibcon#read 4, iclass 10, count 0 2006.162.07:31:09.86#ibcon#about to read 5, iclass 10, count 0 2006.162.07:31:09.86#ibcon#read 5, iclass 10, count 0 2006.162.07:31:09.86#ibcon#about to read 6, iclass 10, count 0 2006.162.07:31:09.86#ibcon#read 6, iclass 10, count 0 2006.162.07:31:09.86#ibcon#end of sib2, iclass 10, count 0 2006.162.07:31:09.86#ibcon#*mode == 0, iclass 10, count 0 2006.162.07:31:09.86#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.162.07:31:09.86#ibcon#[25=USB\r\n] 2006.162.07:31:09.86#ibcon#*before write, iclass 10, count 0 2006.162.07:31:09.86#ibcon#enter sib2, iclass 10, count 0 2006.162.07:31:09.86#ibcon#flushed, iclass 10, count 0 2006.162.07:31:09.86#ibcon#about to write, iclass 10, count 0 2006.162.07:31:09.86#ibcon#wrote, iclass 10, count 0 2006.162.07:31:09.86#ibcon#about to read 3, iclass 10, count 0 2006.162.07:31:09.89#ibcon#read 3, iclass 10, count 0 2006.162.07:31:09.89#ibcon#about to read 4, iclass 10, count 0 2006.162.07:31:09.89#ibcon#read 4, iclass 10, count 0 2006.162.07:31:09.89#ibcon#about to read 5, iclass 10, count 0 2006.162.07:31:09.89#ibcon#read 5, iclass 10, count 0 2006.162.07:31:09.89#ibcon#about to read 6, iclass 10, count 0 2006.162.07:31:09.89#ibcon#read 6, iclass 10, count 0 2006.162.07:31:09.89#ibcon#end of sib2, iclass 10, count 0 2006.162.07:31:09.89#ibcon#*after write, iclass 10, count 0 2006.162.07:31:09.89#ibcon#*before return 0, iclass 10, count 0 2006.162.07:31:09.89#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:31:09.89#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:31:09.89#ibcon#about to clear, iclass 10 cls_cnt 0 2006.162.07:31:09.89#ibcon#cleared, iclass 10 cls_cnt 0 2006.162.07:31:09.89$vc4f8/valo=4,832.99 2006.162.07:31:09.89#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.162.07:31:09.89#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.162.07:31:09.89#ibcon#ireg 17 cls_cnt 0 2006.162.07:31:09.89#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:31:09.89#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:31:09.89#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:31:09.89#ibcon#enter wrdev, iclass 12, count 0 2006.162.07:31:09.89#ibcon#first serial, iclass 12, count 0 2006.162.07:31:09.89#ibcon#enter sib2, iclass 12, count 0 2006.162.07:31:09.89#ibcon#flushed, iclass 12, count 0 2006.162.07:31:09.89#ibcon#about to write, iclass 12, count 0 2006.162.07:31:09.89#ibcon#wrote, iclass 12, count 0 2006.162.07:31:09.89#ibcon#about to read 3, iclass 12, count 0 2006.162.07:31:09.91#ibcon#read 3, iclass 12, count 0 2006.162.07:31:09.91#ibcon#about to read 4, iclass 12, count 0 2006.162.07:31:09.91#ibcon#read 4, iclass 12, count 0 2006.162.07:31:09.91#ibcon#about to read 5, iclass 12, count 0 2006.162.07:31:09.91#ibcon#read 5, iclass 12, count 0 2006.162.07:31:09.91#ibcon#about to read 6, iclass 12, count 0 2006.162.07:31:09.91#ibcon#read 6, iclass 12, count 0 2006.162.07:31:09.91#ibcon#end of sib2, iclass 12, count 0 2006.162.07:31:09.91#ibcon#*mode == 0, iclass 12, count 0 2006.162.07:31:09.91#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.162.07:31:09.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.07:31:09.91#ibcon#*before write, iclass 12, count 0 2006.162.07:31:09.91#ibcon#enter sib2, iclass 12, count 0 2006.162.07:31:09.91#ibcon#flushed, iclass 12, count 0 2006.162.07:31:09.91#ibcon#about to write, iclass 12, count 0 2006.162.07:31:09.91#ibcon#wrote, iclass 12, count 0 2006.162.07:31:09.91#ibcon#about to read 3, iclass 12, count 0 2006.162.07:31:09.95#ibcon#read 3, iclass 12, count 0 2006.162.07:31:09.95#ibcon#about to read 4, iclass 12, count 0 2006.162.07:31:09.95#ibcon#read 4, iclass 12, count 0 2006.162.07:31:09.95#ibcon#about to read 5, iclass 12, count 0 2006.162.07:31:09.95#ibcon#read 5, iclass 12, count 0 2006.162.07:31:09.95#ibcon#about to read 6, iclass 12, count 0 2006.162.07:31:09.95#ibcon#read 6, iclass 12, count 0 2006.162.07:31:09.95#ibcon#end of sib2, iclass 12, count 0 2006.162.07:31:09.95#ibcon#*after write, iclass 12, count 0 2006.162.07:31:09.95#ibcon#*before return 0, iclass 12, count 0 2006.162.07:31:09.95#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:31:09.95#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:31:09.95#ibcon#about to clear, iclass 12 cls_cnt 0 2006.162.07:31:09.95#ibcon#cleared, iclass 12 cls_cnt 0 2006.162.07:31:09.95$vc4f8/va=4,7 2006.162.07:31:09.95#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.162.07:31:09.95#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.162.07:31:09.95#ibcon#ireg 11 cls_cnt 2 2006.162.07:31:09.95#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:31:10.01#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:31:10.01#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:31:10.01#ibcon#enter wrdev, iclass 14, count 2 2006.162.07:31:10.01#ibcon#first serial, iclass 14, count 2 2006.162.07:31:10.01#ibcon#enter sib2, iclass 14, count 2 2006.162.07:31:10.01#ibcon#flushed, iclass 14, count 2 2006.162.07:31:10.01#ibcon#about to write, iclass 14, count 2 2006.162.07:31:10.01#ibcon#wrote, iclass 14, count 2 2006.162.07:31:10.01#ibcon#about to read 3, iclass 14, count 2 2006.162.07:31:10.03#ibcon#read 3, iclass 14, count 2 2006.162.07:31:10.03#ibcon#about to read 4, iclass 14, count 2 2006.162.07:31:10.03#ibcon#read 4, iclass 14, count 2 2006.162.07:31:10.03#ibcon#about to read 5, iclass 14, count 2 2006.162.07:31:10.03#ibcon#read 5, iclass 14, count 2 2006.162.07:31:10.03#ibcon#about to read 6, iclass 14, count 2 2006.162.07:31:10.03#ibcon#read 6, iclass 14, count 2 2006.162.07:31:10.03#ibcon#end of sib2, iclass 14, count 2 2006.162.07:31:10.03#ibcon#*mode == 0, iclass 14, count 2 2006.162.07:31:10.03#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.162.07:31:10.03#ibcon#[25=AT04-07\r\n] 2006.162.07:31:10.03#ibcon#*before write, iclass 14, count 2 2006.162.07:31:10.03#ibcon#enter sib2, iclass 14, count 2 2006.162.07:31:10.03#ibcon#flushed, iclass 14, count 2 2006.162.07:31:10.03#ibcon#about to write, iclass 14, count 2 2006.162.07:31:10.03#ibcon#wrote, iclass 14, count 2 2006.162.07:31:10.03#ibcon#about to read 3, iclass 14, count 2 2006.162.07:31:10.06#ibcon#read 3, iclass 14, count 2 2006.162.07:31:10.06#ibcon#about to read 4, iclass 14, count 2 2006.162.07:31:10.06#ibcon#read 4, iclass 14, count 2 2006.162.07:31:10.06#ibcon#about to read 5, iclass 14, count 2 2006.162.07:31:10.06#ibcon#read 5, iclass 14, count 2 2006.162.07:31:10.06#ibcon#about to read 6, iclass 14, count 2 2006.162.07:31:10.06#ibcon#read 6, iclass 14, count 2 2006.162.07:31:10.06#ibcon#end of sib2, iclass 14, count 2 2006.162.07:31:10.06#ibcon#*after write, iclass 14, count 2 2006.162.07:31:10.06#ibcon#*before return 0, iclass 14, count 2 2006.162.07:31:10.06#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:31:10.06#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:31:10.06#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.162.07:31:10.06#ibcon#ireg 7 cls_cnt 0 2006.162.07:31:10.06#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:31:10.18#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:31:10.18#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:31:10.18#ibcon#enter wrdev, iclass 14, count 0 2006.162.07:31:10.18#ibcon#first serial, iclass 14, count 0 2006.162.07:31:10.18#ibcon#enter sib2, iclass 14, count 0 2006.162.07:31:10.18#ibcon#flushed, iclass 14, count 0 2006.162.07:31:10.18#ibcon#about to write, iclass 14, count 0 2006.162.07:31:10.18#ibcon#wrote, iclass 14, count 0 2006.162.07:31:10.18#ibcon#about to read 3, iclass 14, count 0 2006.162.07:31:10.20#ibcon#read 3, iclass 14, count 0 2006.162.07:31:10.20#ibcon#about to read 4, iclass 14, count 0 2006.162.07:31:10.20#ibcon#read 4, iclass 14, count 0 2006.162.07:31:10.20#ibcon#about to read 5, iclass 14, count 0 2006.162.07:31:10.20#ibcon#read 5, iclass 14, count 0 2006.162.07:31:10.20#ibcon#about to read 6, iclass 14, count 0 2006.162.07:31:10.20#ibcon#read 6, iclass 14, count 0 2006.162.07:31:10.20#ibcon#end of sib2, iclass 14, count 0 2006.162.07:31:10.20#ibcon#*mode == 0, iclass 14, count 0 2006.162.07:31:10.20#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.07:31:10.20#ibcon#[25=USB\r\n] 2006.162.07:31:10.20#ibcon#*before write, iclass 14, count 0 2006.162.07:31:10.20#ibcon#enter sib2, iclass 14, count 0 2006.162.07:31:10.20#ibcon#flushed, iclass 14, count 0 2006.162.07:31:10.20#ibcon#about to write, iclass 14, count 0 2006.162.07:31:10.20#ibcon#wrote, iclass 14, count 0 2006.162.07:31:10.20#ibcon#about to read 3, iclass 14, count 0 2006.162.07:31:10.23#ibcon#read 3, iclass 14, count 0 2006.162.07:31:10.23#ibcon#about to read 4, iclass 14, count 0 2006.162.07:31:10.23#ibcon#read 4, iclass 14, count 0 2006.162.07:31:10.23#ibcon#about to read 5, iclass 14, count 0 2006.162.07:31:10.23#ibcon#read 5, iclass 14, count 0 2006.162.07:31:10.23#ibcon#about to read 6, iclass 14, count 0 2006.162.07:31:10.23#ibcon#read 6, iclass 14, count 0 2006.162.07:31:10.23#ibcon#end of sib2, iclass 14, count 0 2006.162.07:31:10.23#ibcon#*after write, iclass 14, count 0 2006.162.07:31:10.23#ibcon#*before return 0, iclass 14, count 0 2006.162.07:31:10.23#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:31:10.23#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:31:10.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.07:31:10.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.07:31:10.23$vc4f8/valo=5,652.99 2006.162.07:31:10.23#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.162.07:31:10.23#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.162.07:31:10.23#ibcon#ireg 17 cls_cnt 0 2006.162.07:31:10.23#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:31:10.23#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:31:10.23#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:31:10.23#ibcon#enter wrdev, iclass 16, count 0 2006.162.07:31:10.23#ibcon#first serial, iclass 16, count 0 2006.162.07:31:10.23#ibcon#enter sib2, iclass 16, count 0 2006.162.07:31:10.23#ibcon#flushed, iclass 16, count 0 2006.162.07:31:10.23#ibcon#about to write, iclass 16, count 0 2006.162.07:31:10.23#ibcon#wrote, iclass 16, count 0 2006.162.07:31:10.23#ibcon#about to read 3, iclass 16, count 0 2006.162.07:31:10.25#ibcon#read 3, iclass 16, count 0 2006.162.07:31:10.25#ibcon#about to read 4, iclass 16, count 0 2006.162.07:31:10.25#ibcon#read 4, iclass 16, count 0 2006.162.07:31:10.25#ibcon#about to read 5, iclass 16, count 0 2006.162.07:31:10.25#ibcon#read 5, iclass 16, count 0 2006.162.07:31:10.25#ibcon#about to read 6, iclass 16, count 0 2006.162.07:31:10.25#ibcon#read 6, iclass 16, count 0 2006.162.07:31:10.25#ibcon#end of sib2, iclass 16, count 0 2006.162.07:31:10.25#ibcon#*mode == 0, iclass 16, count 0 2006.162.07:31:10.25#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.162.07:31:10.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.07:31:10.25#ibcon#*before write, iclass 16, count 0 2006.162.07:31:10.25#ibcon#enter sib2, iclass 16, count 0 2006.162.07:31:10.25#ibcon#flushed, iclass 16, count 0 2006.162.07:31:10.25#ibcon#about to write, iclass 16, count 0 2006.162.07:31:10.25#ibcon#wrote, iclass 16, count 0 2006.162.07:31:10.25#ibcon#about to read 3, iclass 16, count 0 2006.162.07:31:10.29#ibcon#read 3, iclass 16, count 0 2006.162.07:31:10.29#ibcon#about to read 4, iclass 16, count 0 2006.162.07:31:10.29#ibcon#read 4, iclass 16, count 0 2006.162.07:31:10.29#ibcon#about to read 5, iclass 16, count 0 2006.162.07:31:10.29#ibcon#read 5, iclass 16, count 0 2006.162.07:31:10.29#ibcon#about to read 6, iclass 16, count 0 2006.162.07:31:10.29#ibcon#read 6, iclass 16, count 0 2006.162.07:31:10.29#ibcon#end of sib2, iclass 16, count 0 2006.162.07:31:10.29#ibcon#*after write, iclass 16, count 0 2006.162.07:31:10.29#ibcon#*before return 0, iclass 16, count 0 2006.162.07:31:10.29#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:31:10.29#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:31:10.29#ibcon#about to clear, iclass 16 cls_cnt 0 2006.162.07:31:10.29#ibcon#cleared, iclass 16 cls_cnt 0 2006.162.07:31:10.29$vc4f8/va=5,7 2006.162.07:31:10.29#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.162.07:31:10.29#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.162.07:31:10.29#ibcon#ireg 11 cls_cnt 2 2006.162.07:31:10.29#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:31:10.35#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:31:10.35#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:31:10.35#ibcon#enter wrdev, iclass 18, count 2 2006.162.07:31:10.35#ibcon#first serial, iclass 18, count 2 2006.162.07:31:10.35#ibcon#enter sib2, iclass 18, count 2 2006.162.07:31:10.35#ibcon#flushed, iclass 18, count 2 2006.162.07:31:10.35#ibcon#about to write, iclass 18, count 2 2006.162.07:31:10.35#ibcon#wrote, iclass 18, count 2 2006.162.07:31:10.35#ibcon#about to read 3, iclass 18, count 2 2006.162.07:31:10.37#ibcon#read 3, iclass 18, count 2 2006.162.07:31:10.37#ibcon#about to read 4, iclass 18, count 2 2006.162.07:31:10.37#ibcon#read 4, iclass 18, count 2 2006.162.07:31:10.37#ibcon#about to read 5, iclass 18, count 2 2006.162.07:31:10.37#ibcon#read 5, iclass 18, count 2 2006.162.07:31:10.37#ibcon#about to read 6, iclass 18, count 2 2006.162.07:31:10.37#ibcon#read 6, iclass 18, count 2 2006.162.07:31:10.37#ibcon#end of sib2, iclass 18, count 2 2006.162.07:31:10.37#ibcon#*mode == 0, iclass 18, count 2 2006.162.07:31:10.37#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.162.07:31:10.37#ibcon#[25=AT05-07\r\n] 2006.162.07:31:10.37#ibcon#*before write, iclass 18, count 2 2006.162.07:31:10.37#ibcon#enter sib2, iclass 18, count 2 2006.162.07:31:10.37#ibcon#flushed, iclass 18, count 2 2006.162.07:31:10.37#ibcon#about to write, iclass 18, count 2 2006.162.07:31:10.37#ibcon#wrote, iclass 18, count 2 2006.162.07:31:10.37#ibcon#about to read 3, iclass 18, count 2 2006.162.07:31:10.40#ibcon#read 3, iclass 18, count 2 2006.162.07:31:10.40#ibcon#about to read 4, iclass 18, count 2 2006.162.07:31:10.40#ibcon#read 4, iclass 18, count 2 2006.162.07:31:10.40#ibcon#about to read 5, iclass 18, count 2 2006.162.07:31:10.40#ibcon#read 5, iclass 18, count 2 2006.162.07:31:10.40#ibcon#about to read 6, iclass 18, count 2 2006.162.07:31:10.40#ibcon#read 6, iclass 18, count 2 2006.162.07:31:10.40#ibcon#end of sib2, iclass 18, count 2 2006.162.07:31:10.40#ibcon#*after write, iclass 18, count 2 2006.162.07:31:10.40#ibcon#*before return 0, iclass 18, count 2 2006.162.07:31:10.40#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:31:10.40#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:31:10.40#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.162.07:31:10.40#ibcon#ireg 7 cls_cnt 0 2006.162.07:31:10.40#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:31:10.52#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:31:10.52#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:31:10.52#ibcon#enter wrdev, iclass 18, count 0 2006.162.07:31:10.52#ibcon#first serial, iclass 18, count 0 2006.162.07:31:10.52#ibcon#enter sib2, iclass 18, count 0 2006.162.07:31:10.52#ibcon#flushed, iclass 18, count 0 2006.162.07:31:10.52#ibcon#about to write, iclass 18, count 0 2006.162.07:31:10.52#ibcon#wrote, iclass 18, count 0 2006.162.07:31:10.52#ibcon#about to read 3, iclass 18, count 0 2006.162.07:31:10.54#ibcon#read 3, iclass 18, count 0 2006.162.07:31:10.54#ibcon#about to read 4, iclass 18, count 0 2006.162.07:31:10.54#ibcon#read 4, iclass 18, count 0 2006.162.07:31:10.54#ibcon#about to read 5, iclass 18, count 0 2006.162.07:31:10.54#ibcon#read 5, iclass 18, count 0 2006.162.07:31:10.54#ibcon#about to read 6, iclass 18, count 0 2006.162.07:31:10.54#ibcon#read 6, iclass 18, count 0 2006.162.07:31:10.54#ibcon#end of sib2, iclass 18, count 0 2006.162.07:31:10.54#ibcon#*mode == 0, iclass 18, count 0 2006.162.07:31:10.54#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.162.07:31:10.54#ibcon#[25=USB\r\n] 2006.162.07:31:10.54#ibcon#*before write, iclass 18, count 0 2006.162.07:31:10.54#ibcon#enter sib2, iclass 18, count 0 2006.162.07:31:10.54#ibcon#flushed, iclass 18, count 0 2006.162.07:31:10.54#ibcon#about to write, iclass 18, count 0 2006.162.07:31:10.54#ibcon#wrote, iclass 18, count 0 2006.162.07:31:10.54#ibcon#about to read 3, iclass 18, count 0 2006.162.07:31:10.57#ibcon#read 3, iclass 18, count 0 2006.162.07:31:10.57#ibcon#about to read 4, iclass 18, count 0 2006.162.07:31:10.57#ibcon#read 4, iclass 18, count 0 2006.162.07:31:10.57#ibcon#about to read 5, iclass 18, count 0 2006.162.07:31:10.57#ibcon#read 5, iclass 18, count 0 2006.162.07:31:10.57#ibcon#about to read 6, iclass 18, count 0 2006.162.07:31:10.57#ibcon#read 6, iclass 18, count 0 2006.162.07:31:10.57#ibcon#end of sib2, iclass 18, count 0 2006.162.07:31:10.57#ibcon#*after write, iclass 18, count 0 2006.162.07:31:10.57#ibcon#*before return 0, iclass 18, count 0 2006.162.07:31:10.57#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:31:10.57#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:31:10.57#ibcon#about to clear, iclass 18 cls_cnt 0 2006.162.07:31:10.57#ibcon#cleared, iclass 18 cls_cnt 0 2006.162.07:31:10.57$vc4f8/valo=6,772.99 2006.162.07:31:10.57#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.162.07:31:10.57#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.162.07:31:10.57#ibcon#ireg 17 cls_cnt 0 2006.162.07:31:10.57#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:31:10.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:31:10.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:31:10.57#ibcon#enter wrdev, iclass 20, count 0 2006.162.07:31:10.57#ibcon#first serial, iclass 20, count 0 2006.162.07:31:10.57#ibcon#enter sib2, iclass 20, count 0 2006.162.07:31:10.57#ibcon#flushed, iclass 20, count 0 2006.162.07:31:10.57#ibcon#about to write, iclass 20, count 0 2006.162.07:31:10.57#ibcon#wrote, iclass 20, count 0 2006.162.07:31:10.57#ibcon#about to read 3, iclass 20, count 0 2006.162.07:31:10.59#ibcon#read 3, iclass 20, count 0 2006.162.07:31:10.59#ibcon#about to read 4, iclass 20, count 0 2006.162.07:31:10.59#ibcon#read 4, iclass 20, count 0 2006.162.07:31:10.59#ibcon#about to read 5, iclass 20, count 0 2006.162.07:31:10.59#ibcon#read 5, iclass 20, count 0 2006.162.07:31:10.59#ibcon#about to read 6, iclass 20, count 0 2006.162.07:31:10.59#ibcon#read 6, iclass 20, count 0 2006.162.07:31:10.59#ibcon#end of sib2, iclass 20, count 0 2006.162.07:31:10.59#ibcon#*mode == 0, iclass 20, count 0 2006.162.07:31:10.59#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.07:31:10.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.07:31:10.59#ibcon#*before write, iclass 20, count 0 2006.162.07:31:10.59#ibcon#enter sib2, iclass 20, count 0 2006.162.07:31:10.59#ibcon#flushed, iclass 20, count 0 2006.162.07:31:10.59#ibcon#about to write, iclass 20, count 0 2006.162.07:31:10.59#ibcon#wrote, iclass 20, count 0 2006.162.07:31:10.59#ibcon#about to read 3, iclass 20, count 0 2006.162.07:31:10.63#ibcon#read 3, iclass 20, count 0 2006.162.07:31:10.63#ibcon#about to read 4, iclass 20, count 0 2006.162.07:31:10.63#ibcon#read 4, iclass 20, count 0 2006.162.07:31:10.63#ibcon#about to read 5, iclass 20, count 0 2006.162.07:31:10.63#ibcon#read 5, iclass 20, count 0 2006.162.07:31:10.63#ibcon#about to read 6, iclass 20, count 0 2006.162.07:31:10.63#ibcon#read 6, iclass 20, count 0 2006.162.07:31:10.63#ibcon#end of sib2, iclass 20, count 0 2006.162.07:31:10.63#ibcon#*after write, iclass 20, count 0 2006.162.07:31:10.63#ibcon#*before return 0, iclass 20, count 0 2006.162.07:31:10.63#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:31:10.63#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:31:10.63#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.07:31:10.63#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.07:31:10.63$vc4f8/va=6,6 2006.162.07:31:10.63#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.162.07:31:10.63#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.162.07:31:10.63#ibcon#ireg 11 cls_cnt 2 2006.162.07:31:10.63#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:31:10.69#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:31:10.69#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:31:10.69#ibcon#enter wrdev, iclass 22, count 2 2006.162.07:31:10.69#ibcon#first serial, iclass 22, count 2 2006.162.07:31:10.69#ibcon#enter sib2, iclass 22, count 2 2006.162.07:31:10.69#ibcon#flushed, iclass 22, count 2 2006.162.07:31:10.69#ibcon#about to write, iclass 22, count 2 2006.162.07:31:10.69#ibcon#wrote, iclass 22, count 2 2006.162.07:31:10.69#ibcon#about to read 3, iclass 22, count 2 2006.162.07:31:10.71#ibcon#read 3, iclass 22, count 2 2006.162.07:31:10.71#ibcon#about to read 4, iclass 22, count 2 2006.162.07:31:10.71#ibcon#read 4, iclass 22, count 2 2006.162.07:31:10.71#ibcon#about to read 5, iclass 22, count 2 2006.162.07:31:10.71#ibcon#read 5, iclass 22, count 2 2006.162.07:31:10.71#ibcon#about to read 6, iclass 22, count 2 2006.162.07:31:10.71#ibcon#read 6, iclass 22, count 2 2006.162.07:31:10.71#ibcon#end of sib2, iclass 22, count 2 2006.162.07:31:10.71#ibcon#*mode == 0, iclass 22, count 2 2006.162.07:31:10.71#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.162.07:31:10.71#ibcon#[25=AT06-06\r\n] 2006.162.07:31:10.71#ibcon#*before write, iclass 22, count 2 2006.162.07:31:10.71#ibcon#enter sib2, iclass 22, count 2 2006.162.07:31:10.71#ibcon#flushed, iclass 22, count 2 2006.162.07:31:10.71#ibcon#about to write, iclass 22, count 2 2006.162.07:31:10.71#ibcon#wrote, iclass 22, count 2 2006.162.07:31:10.71#ibcon#about to read 3, iclass 22, count 2 2006.162.07:31:10.74#ibcon#read 3, iclass 22, count 2 2006.162.07:31:10.74#ibcon#about to read 4, iclass 22, count 2 2006.162.07:31:10.74#ibcon#read 4, iclass 22, count 2 2006.162.07:31:10.74#ibcon#about to read 5, iclass 22, count 2 2006.162.07:31:10.74#ibcon#read 5, iclass 22, count 2 2006.162.07:31:10.74#ibcon#about to read 6, iclass 22, count 2 2006.162.07:31:10.74#ibcon#read 6, iclass 22, count 2 2006.162.07:31:10.74#ibcon#end of sib2, iclass 22, count 2 2006.162.07:31:10.74#ibcon#*after write, iclass 22, count 2 2006.162.07:31:10.74#ibcon#*before return 0, iclass 22, count 2 2006.162.07:31:10.74#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:31:10.74#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:31:10.74#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.162.07:31:10.74#ibcon#ireg 7 cls_cnt 0 2006.162.07:31:10.74#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:31:10.86#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:31:10.86#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:31:10.86#ibcon#enter wrdev, iclass 22, count 0 2006.162.07:31:10.86#ibcon#first serial, iclass 22, count 0 2006.162.07:31:10.86#ibcon#enter sib2, iclass 22, count 0 2006.162.07:31:10.86#ibcon#flushed, iclass 22, count 0 2006.162.07:31:10.86#ibcon#about to write, iclass 22, count 0 2006.162.07:31:10.86#ibcon#wrote, iclass 22, count 0 2006.162.07:31:10.86#ibcon#about to read 3, iclass 22, count 0 2006.162.07:31:10.88#ibcon#read 3, iclass 22, count 0 2006.162.07:31:10.88#ibcon#about to read 4, iclass 22, count 0 2006.162.07:31:10.88#ibcon#read 4, iclass 22, count 0 2006.162.07:31:10.88#ibcon#about to read 5, iclass 22, count 0 2006.162.07:31:10.88#ibcon#read 5, iclass 22, count 0 2006.162.07:31:10.88#ibcon#about to read 6, iclass 22, count 0 2006.162.07:31:10.88#ibcon#read 6, iclass 22, count 0 2006.162.07:31:10.88#ibcon#end of sib2, iclass 22, count 0 2006.162.07:31:10.88#ibcon#*mode == 0, iclass 22, count 0 2006.162.07:31:10.88#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.07:31:10.88#ibcon#[25=USB\r\n] 2006.162.07:31:10.88#ibcon#*before write, iclass 22, count 0 2006.162.07:31:10.88#ibcon#enter sib2, iclass 22, count 0 2006.162.07:31:10.88#ibcon#flushed, iclass 22, count 0 2006.162.07:31:10.88#ibcon#about to write, iclass 22, count 0 2006.162.07:31:10.88#ibcon#wrote, iclass 22, count 0 2006.162.07:31:10.88#ibcon#about to read 3, iclass 22, count 0 2006.162.07:31:10.91#ibcon#read 3, iclass 22, count 0 2006.162.07:31:10.91#ibcon#about to read 4, iclass 22, count 0 2006.162.07:31:10.91#ibcon#read 4, iclass 22, count 0 2006.162.07:31:10.91#ibcon#about to read 5, iclass 22, count 0 2006.162.07:31:10.91#ibcon#read 5, iclass 22, count 0 2006.162.07:31:10.91#ibcon#about to read 6, iclass 22, count 0 2006.162.07:31:10.91#ibcon#read 6, iclass 22, count 0 2006.162.07:31:10.91#ibcon#end of sib2, iclass 22, count 0 2006.162.07:31:10.91#ibcon#*after write, iclass 22, count 0 2006.162.07:31:10.91#ibcon#*before return 0, iclass 22, count 0 2006.162.07:31:10.91#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:31:10.91#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:31:10.91#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.07:31:10.91#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.07:31:10.91$vc4f8/valo=7,832.99 2006.162.07:31:10.91#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.162.07:31:10.91#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.162.07:31:10.91#ibcon#ireg 17 cls_cnt 0 2006.162.07:31:10.91#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:31:10.91#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:31:10.91#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:31:10.91#ibcon#enter wrdev, iclass 24, count 0 2006.162.07:31:10.91#ibcon#first serial, iclass 24, count 0 2006.162.07:31:10.91#ibcon#enter sib2, iclass 24, count 0 2006.162.07:31:10.91#ibcon#flushed, iclass 24, count 0 2006.162.07:31:10.91#ibcon#about to write, iclass 24, count 0 2006.162.07:31:10.91#ibcon#wrote, iclass 24, count 0 2006.162.07:31:10.91#ibcon#about to read 3, iclass 24, count 0 2006.162.07:31:10.93#ibcon#read 3, iclass 24, count 0 2006.162.07:31:10.93#ibcon#about to read 4, iclass 24, count 0 2006.162.07:31:10.93#ibcon#read 4, iclass 24, count 0 2006.162.07:31:10.93#ibcon#about to read 5, iclass 24, count 0 2006.162.07:31:10.93#ibcon#read 5, iclass 24, count 0 2006.162.07:31:10.93#ibcon#about to read 6, iclass 24, count 0 2006.162.07:31:10.93#ibcon#read 6, iclass 24, count 0 2006.162.07:31:10.93#ibcon#end of sib2, iclass 24, count 0 2006.162.07:31:10.93#ibcon#*mode == 0, iclass 24, count 0 2006.162.07:31:10.93#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.07:31:10.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.07:31:10.93#ibcon#*before write, iclass 24, count 0 2006.162.07:31:10.93#ibcon#enter sib2, iclass 24, count 0 2006.162.07:31:10.93#ibcon#flushed, iclass 24, count 0 2006.162.07:31:10.93#ibcon#about to write, iclass 24, count 0 2006.162.07:31:10.93#ibcon#wrote, iclass 24, count 0 2006.162.07:31:10.93#ibcon#about to read 3, iclass 24, count 0 2006.162.07:31:10.97#ibcon#read 3, iclass 24, count 0 2006.162.07:31:10.97#ibcon#about to read 4, iclass 24, count 0 2006.162.07:31:10.97#ibcon#read 4, iclass 24, count 0 2006.162.07:31:10.97#ibcon#about to read 5, iclass 24, count 0 2006.162.07:31:10.97#ibcon#read 5, iclass 24, count 0 2006.162.07:31:10.97#ibcon#about to read 6, iclass 24, count 0 2006.162.07:31:10.97#ibcon#read 6, iclass 24, count 0 2006.162.07:31:10.97#ibcon#end of sib2, iclass 24, count 0 2006.162.07:31:10.97#ibcon#*after write, iclass 24, count 0 2006.162.07:31:10.97#ibcon#*before return 0, iclass 24, count 0 2006.162.07:31:10.97#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:31:10.97#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:31:10.97#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.07:31:10.97#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.07:31:10.97$vc4f8/va=7,6 2006.162.07:31:10.97#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.162.07:31:10.97#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.162.07:31:10.97#ibcon#ireg 11 cls_cnt 2 2006.162.07:31:10.97#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:31:11.03#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:31:11.03#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:31:11.03#ibcon#enter wrdev, iclass 26, count 2 2006.162.07:31:11.03#ibcon#first serial, iclass 26, count 2 2006.162.07:31:11.03#ibcon#enter sib2, iclass 26, count 2 2006.162.07:31:11.03#ibcon#flushed, iclass 26, count 2 2006.162.07:31:11.03#ibcon#about to write, iclass 26, count 2 2006.162.07:31:11.03#ibcon#wrote, iclass 26, count 2 2006.162.07:31:11.03#ibcon#about to read 3, iclass 26, count 2 2006.162.07:31:11.05#ibcon#read 3, iclass 26, count 2 2006.162.07:31:11.05#ibcon#about to read 4, iclass 26, count 2 2006.162.07:31:11.05#ibcon#read 4, iclass 26, count 2 2006.162.07:31:11.05#ibcon#about to read 5, iclass 26, count 2 2006.162.07:31:11.05#ibcon#read 5, iclass 26, count 2 2006.162.07:31:11.05#ibcon#about to read 6, iclass 26, count 2 2006.162.07:31:11.05#ibcon#read 6, iclass 26, count 2 2006.162.07:31:11.05#ibcon#end of sib2, iclass 26, count 2 2006.162.07:31:11.05#ibcon#*mode == 0, iclass 26, count 2 2006.162.07:31:11.05#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.162.07:31:11.05#ibcon#[25=AT07-06\r\n] 2006.162.07:31:11.05#ibcon#*before write, iclass 26, count 2 2006.162.07:31:11.05#ibcon#enter sib2, iclass 26, count 2 2006.162.07:31:11.05#ibcon#flushed, iclass 26, count 2 2006.162.07:31:11.05#ibcon#about to write, iclass 26, count 2 2006.162.07:31:11.05#ibcon#wrote, iclass 26, count 2 2006.162.07:31:11.05#ibcon#about to read 3, iclass 26, count 2 2006.162.07:31:11.08#ibcon#read 3, iclass 26, count 2 2006.162.07:31:11.08#ibcon#about to read 4, iclass 26, count 2 2006.162.07:31:11.08#ibcon#read 4, iclass 26, count 2 2006.162.07:31:11.08#ibcon#about to read 5, iclass 26, count 2 2006.162.07:31:11.08#ibcon#read 5, iclass 26, count 2 2006.162.07:31:11.08#ibcon#about to read 6, iclass 26, count 2 2006.162.07:31:11.08#ibcon#read 6, iclass 26, count 2 2006.162.07:31:11.08#ibcon#end of sib2, iclass 26, count 2 2006.162.07:31:11.08#ibcon#*after write, iclass 26, count 2 2006.162.07:31:11.08#ibcon#*before return 0, iclass 26, count 2 2006.162.07:31:11.08#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:31:11.08#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:31:11.08#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.162.07:31:11.08#ibcon#ireg 7 cls_cnt 0 2006.162.07:31:11.08#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:31:11.20#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:31:11.20#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:31:11.20#ibcon#enter wrdev, iclass 26, count 0 2006.162.07:31:11.20#ibcon#first serial, iclass 26, count 0 2006.162.07:31:11.20#ibcon#enter sib2, iclass 26, count 0 2006.162.07:31:11.20#ibcon#flushed, iclass 26, count 0 2006.162.07:31:11.20#ibcon#about to write, iclass 26, count 0 2006.162.07:31:11.20#ibcon#wrote, iclass 26, count 0 2006.162.07:31:11.20#ibcon#about to read 3, iclass 26, count 0 2006.162.07:31:11.22#ibcon#read 3, iclass 26, count 0 2006.162.07:31:11.22#ibcon#about to read 4, iclass 26, count 0 2006.162.07:31:11.22#ibcon#read 4, iclass 26, count 0 2006.162.07:31:11.22#ibcon#about to read 5, iclass 26, count 0 2006.162.07:31:11.22#ibcon#read 5, iclass 26, count 0 2006.162.07:31:11.22#ibcon#about to read 6, iclass 26, count 0 2006.162.07:31:11.22#ibcon#read 6, iclass 26, count 0 2006.162.07:31:11.22#ibcon#end of sib2, iclass 26, count 0 2006.162.07:31:11.22#ibcon#*mode == 0, iclass 26, count 0 2006.162.07:31:11.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.162.07:31:11.22#ibcon#[25=USB\r\n] 2006.162.07:31:11.22#ibcon#*before write, iclass 26, count 0 2006.162.07:31:11.22#ibcon#enter sib2, iclass 26, count 0 2006.162.07:31:11.22#ibcon#flushed, iclass 26, count 0 2006.162.07:31:11.22#ibcon#about to write, iclass 26, count 0 2006.162.07:31:11.22#ibcon#wrote, iclass 26, count 0 2006.162.07:31:11.22#ibcon#about to read 3, iclass 26, count 0 2006.162.07:31:11.25#ibcon#read 3, iclass 26, count 0 2006.162.07:31:11.25#ibcon#about to read 4, iclass 26, count 0 2006.162.07:31:11.25#ibcon#read 4, iclass 26, count 0 2006.162.07:31:11.25#ibcon#about to read 5, iclass 26, count 0 2006.162.07:31:11.25#ibcon#read 5, iclass 26, count 0 2006.162.07:31:11.25#ibcon#about to read 6, iclass 26, count 0 2006.162.07:31:11.25#ibcon#read 6, iclass 26, count 0 2006.162.07:31:11.25#ibcon#end of sib2, iclass 26, count 0 2006.162.07:31:11.25#ibcon#*after write, iclass 26, count 0 2006.162.07:31:11.25#ibcon#*before return 0, iclass 26, count 0 2006.162.07:31:11.25#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:31:11.25#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:31:11.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.162.07:31:11.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.162.07:31:11.25$vc4f8/valo=8,852.99 2006.162.07:31:11.25#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.162.07:31:11.25#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.162.07:31:11.25#ibcon#ireg 17 cls_cnt 0 2006.162.07:31:11.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:31:11.25#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:31:11.25#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:31:11.25#ibcon#enter wrdev, iclass 28, count 0 2006.162.07:31:11.25#ibcon#first serial, iclass 28, count 0 2006.162.07:31:11.25#ibcon#enter sib2, iclass 28, count 0 2006.162.07:31:11.25#ibcon#flushed, iclass 28, count 0 2006.162.07:31:11.25#ibcon#about to write, iclass 28, count 0 2006.162.07:31:11.25#ibcon#wrote, iclass 28, count 0 2006.162.07:31:11.25#ibcon#about to read 3, iclass 28, count 0 2006.162.07:31:11.27#ibcon#read 3, iclass 28, count 0 2006.162.07:31:11.27#ibcon#about to read 4, iclass 28, count 0 2006.162.07:31:11.27#ibcon#read 4, iclass 28, count 0 2006.162.07:31:11.27#ibcon#about to read 5, iclass 28, count 0 2006.162.07:31:11.27#ibcon#read 5, iclass 28, count 0 2006.162.07:31:11.27#ibcon#about to read 6, iclass 28, count 0 2006.162.07:31:11.27#ibcon#read 6, iclass 28, count 0 2006.162.07:31:11.27#ibcon#end of sib2, iclass 28, count 0 2006.162.07:31:11.27#ibcon#*mode == 0, iclass 28, count 0 2006.162.07:31:11.27#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.162.07:31:11.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.07:31:11.27#ibcon#*before write, iclass 28, count 0 2006.162.07:31:11.27#ibcon#enter sib2, iclass 28, count 0 2006.162.07:31:11.27#ibcon#flushed, iclass 28, count 0 2006.162.07:31:11.27#ibcon#about to write, iclass 28, count 0 2006.162.07:31:11.27#ibcon#wrote, iclass 28, count 0 2006.162.07:31:11.27#ibcon#about to read 3, iclass 28, count 0 2006.162.07:31:11.31#ibcon#read 3, iclass 28, count 0 2006.162.07:31:11.31#ibcon#about to read 4, iclass 28, count 0 2006.162.07:31:11.31#ibcon#read 4, iclass 28, count 0 2006.162.07:31:11.31#ibcon#about to read 5, iclass 28, count 0 2006.162.07:31:11.31#ibcon#read 5, iclass 28, count 0 2006.162.07:31:11.31#ibcon#about to read 6, iclass 28, count 0 2006.162.07:31:11.31#ibcon#read 6, iclass 28, count 0 2006.162.07:31:11.31#ibcon#end of sib2, iclass 28, count 0 2006.162.07:31:11.31#ibcon#*after write, iclass 28, count 0 2006.162.07:31:11.31#ibcon#*before return 0, iclass 28, count 0 2006.162.07:31:11.31#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:31:11.31#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:31:11.31#ibcon#about to clear, iclass 28 cls_cnt 0 2006.162.07:31:11.31#ibcon#cleared, iclass 28 cls_cnt 0 2006.162.07:31:11.31$vc4f8/va=8,7 2006.162.07:31:11.31#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.162.07:31:11.31#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.162.07:31:11.31#ibcon#ireg 11 cls_cnt 2 2006.162.07:31:11.31#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:31:11.37#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:31:11.37#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:31:11.37#ibcon#enter wrdev, iclass 30, count 2 2006.162.07:31:11.37#ibcon#first serial, iclass 30, count 2 2006.162.07:31:11.37#ibcon#enter sib2, iclass 30, count 2 2006.162.07:31:11.37#ibcon#flushed, iclass 30, count 2 2006.162.07:31:11.37#ibcon#about to write, iclass 30, count 2 2006.162.07:31:11.37#ibcon#wrote, iclass 30, count 2 2006.162.07:31:11.37#ibcon#about to read 3, iclass 30, count 2 2006.162.07:31:11.39#ibcon#read 3, iclass 30, count 2 2006.162.07:31:11.39#ibcon#about to read 4, iclass 30, count 2 2006.162.07:31:11.39#ibcon#read 4, iclass 30, count 2 2006.162.07:31:11.39#ibcon#about to read 5, iclass 30, count 2 2006.162.07:31:11.39#ibcon#read 5, iclass 30, count 2 2006.162.07:31:11.39#ibcon#about to read 6, iclass 30, count 2 2006.162.07:31:11.39#ibcon#read 6, iclass 30, count 2 2006.162.07:31:11.39#ibcon#end of sib2, iclass 30, count 2 2006.162.07:31:11.39#ibcon#*mode == 0, iclass 30, count 2 2006.162.07:31:11.39#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.162.07:31:11.39#ibcon#[25=AT08-07\r\n] 2006.162.07:31:11.39#ibcon#*before write, iclass 30, count 2 2006.162.07:31:11.39#ibcon#enter sib2, iclass 30, count 2 2006.162.07:31:11.39#ibcon#flushed, iclass 30, count 2 2006.162.07:31:11.39#ibcon#about to write, iclass 30, count 2 2006.162.07:31:11.39#ibcon#wrote, iclass 30, count 2 2006.162.07:31:11.39#ibcon#about to read 3, iclass 30, count 2 2006.162.07:31:11.42#ibcon#read 3, iclass 30, count 2 2006.162.07:31:11.42#ibcon#about to read 4, iclass 30, count 2 2006.162.07:31:11.42#ibcon#read 4, iclass 30, count 2 2006.162.07:31:11.42#ibcon#about to read 5, iclass 30, count 2 2006.162.07:31:11.42#ibcon#read 5, iclass 30, count 2 2006.162.07:31:11.42#ibcon#about to read 6, iclass 30, count 2 2006.162.07:31:11.42#ibcon#read 6, iclass 30, count 2 2006.162.07:31:11.42#ibcon#end of sib2, iclass 30, count 2 2006.162.07:31:11.42#ibcon#*after write, iclass 30, count 2 2006.162.07:31:11.42#ibcon#*before return 0, iclass 30, count 2 2006.162.07:31:11.42#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:31:11.42#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:31:11.42#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.162.07:31:11.42#ibcon#ireg 7 cls_cnt 0 2006.162.07:31:11.42#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:31:11.54#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:31:11.54#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:31:11.54#ibcon#enter wrdev, iclass 30, count 0 2006.162.07:31:11.54#ibcon#first serial, iclass 30, count 0 2006.162.07:31:11.54#ibcon#enter sib2, iclass 30, count 0 2006.162.07:31:11.54#ibcon#flushed, iclass 30, count 0 2006.162.07:31:11.54#ibcon#about to write, iclass 30, count 0 2006.162.07:31:11.54#ibcon#wrote, iclass 30, count 0 2006.162.07:31:11.54#ibcon#about to read 3, iclass 30, count 0 2006.162.07:31:11.56#ibcon#read 3, iclass 30, count 0 2006.162.07:31:11.56#ibcon#about to read 4, iclass 30, count 0 2006.162.07:31:11.56#ibcon#read 4, iclass 30, count 0 2006.162.07:31:11.56#ibcon#about to read 5, iclass 30, count 0 2006.162.07:31:11.56#ibcon#read 5, iclass 30, count 0 2006.162.07:31:11.56#ibcon#about to read 6, iclass 30, count 0 2006.162.07:31:11.56#ibcon#read 6, iclass 30, count 0 2006.162.07:31:11.56#ibcon#end of sib2, iclass 30, count 0 2006.162.07:31:11.56#ibcon#*mode == 0, iclass 30, count 0 2006.162.07:31:11.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.162.07:31:11.56#ibcon#[25=USB\r\n] 2006.162.07:31:11.56#ibcon#*before write, iclass 30, count 0 2006.162.07:31:11.56#ibcon#enter sib2, iclass 30, count 0 2006.162.07:31:11.56#ibcon#flushed, iclass 30, count 0 2006.162.07:31:11.56#ibcon#about to write, iclass 30, count 0 2006.162.07:31:11.56#ibcon#wrote, iclass 30, count 0 2006.162.07:31:11.56#ibcon#about to read 3, iclass 30, count 0 2006.162.07:31:11.59#ibcon#read 3, iclass 30, count 0 2006.162.07:31:11.59#ibcon#about to read 4, iclass 30, count 0 2006.162.07:31:11.59#ibcon#read 4, iclass 30, count 0 2006.162.07:31:11.59#ibcon#about to read 5, iclass 30, count 0 2006.162.07:31:11.59#ibcon#read 5, iclass 30, count 0 2006.162.07:31:11.59#ibcon#about to read 6, iclass 30, count 0 2006.162.07:31:11.59#ibcon#read 6, iclass 30, count 0 2006.162.07:31:11.59#ibcon#end of sib2, iclass 30, count 0 2006.162.07:31:11.59#ibcon#*after write, iclass 30, count 0 2006.162.07:31:11.59#ibcon#*before return 0, iclass 30, count 0 2006.162.07:31:11.59#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:31:11.59#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:31:11.59#ibcon#about to clear, iclass 30 cls_cnt 0 2006.162.07:31:11.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.162.07:31:11.59$vc4f8/vblo=1,632.99 2006.162.07:31:11.59#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.162.07:31:11.59#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.162.07:31:11.59#ibcon#ireg 17 cls_cnt 0 2006.162.07:31:11.59#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:31:11.59#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:31:11.59#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:31:11.59#ibcon#enter wrdev, iclass 32, count 0 2006.162.07:31:11.59#ibcon#first serial, iclass 32, count 0 2006.162.07:31:11.59#ibcon#enter sib2, iclass 32, count 0 2006.162.07:31:11.59#ibcon#flushed, iclass 32, count 0 2006.162.07:31:11.59#ibcon#about to write, iclass 32, count 0 2006.162.07:31:11.59#ibcon#wrote, iclass 32, count 0 2006.162.07:31:11.59#ibcon#about to read 3, iclass 32, count 0 2006.162.07:31:11.61#ibcon#read 3, iclass 32, count 0 2006.162.07:31:11.61#ibcon#about to read 4, iclass 32, count 0 2006.162.07:31:11.61#ibcon#read 4, iclass 32, count 0 2006.162.07:31:11.61#ibcon#about to read 5, iclass 32, count 0 2006.162.07:31:11.61#ibcon#read 5, iclass 32, count 0 2006.162.07:31:11.61#ibcon#about to read 6, iclass 32, count 0 2006.162.07:31:11.61#ibcon#read 6, iclass 32, count 0 2006.162.07:31:11.61#ibcon#end of sib2, iclass 32, count 0 2006.162.07:31:11.61#ibcon#*mode == 0, iclass 32, count 0 2006.162.07:31:11.61#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.162.07:31:11.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.07:31:11.61#ibcon#*before write, iclass 32, count 0 2006.162.07:31:11.61#ibcon#enter sib2, iclass 32, count 0 2006.162.07:31:11.61#ibcon#flushed, iclass 32, count 0 2006.162.07:31:11.61#ibcon#about to write, iclass 32, count 0 2006.162.07:31:11.61#ibcon#wrote, iclass 32, count 0 2006.162.07:31:11.61#ibcon#about to read 3, iclass 32, count 0 2006.162.07:31:11.65#ibcon#read 3, iclass 32, count 0 2006.162.07:31:11.65#ibcon#about to read 4, iclass 32, count 0 2006.162.07:31:11.65#ibcon#read 4, iclass 32, count 0 2006.162.07:31:11.65#ibcon#about to read 5, iclass 32, count 0 2006.162.07:31:11.65#ibcon#read 5, iclass 32, count 0 2006.162.07:31:11.65#ibcon#about to read 6, iclass 32, count 0 2006.162.07:31:11.65#ibcon#read 6, iclass 32, count 0 2006.162.07:31:11.65#ibcon#end of sib2, iclass 32, count 0 2006.162.07:31:11.65#ibcon#*after write, iclass 32, count 0 2006.162.07:31:11.65#ibcon#*before return 0, iclass 32, count 0 2006.162.07:31:11.65#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:31:11.65#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:31:11.65#ibcon#about to clear, iclass 32 cls_cnt 0 2006.162.07:31:11.65#ibcon#cleared, iclass 32 cls_cnt 0 2006.162.07:31:11.65$vc4f8/vb=1,4 2006.162.07:31:11.65#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.162.07:31:11.65#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.162.07:31:11.65#ibcon#ireg 11 cls_cnt 2 2006.162.07:31:11.65#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.162.07:31:11.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.162.07:31:11.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.162.07:31:11.65#ibcon#enter wrdev, iclass 34, count 2 2006.162.07:31:11.65#ibcon#first serial, iclass 34, count 2 2006.162.07:31:11.65#ibcon#enter sib2, iclass 34, count 2 2006.162.07:31:11.65#ibcon#flushed, iclass 34, count 2 2006.162.07:31:11.65#ibcon#about to write, iclass 34, count 2 2006.162.07:31:11.65#ibcon#wrote, iclass 34, count 2 2006.162.07:31:11.65#ibcon#about to read 3, iclass 34, count 2 2006.162.07:31:11.67#ibcon#read 3, iclass 34, count 2 2006.162.07:31:11.67#ibcon#about to read 4, iclass 34, count 2 2006.162.07:31:11.67#ibcon#read 4, iclass 34, count 2 2006.162.07:31:11.67#ibcon#about to read 5, iclass 34, count 2 2006.162.07:31:11.67#ibcon#read 5, iclass 34, count 2 2006.162.07:31:11.67#ibcon#about to read 6, iclass 34, count 2 2006.162.07:31:11.67#ibcon#read 6, iclass 34, count 2 2006.162.07:31:11.67#ibcon#end of sib2, iclass 34, count 2 2006.162.07:31:11.67#ibcon#*mode == 0, iclass 34, count 2 2006.162.07:31:11.67#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.162.07:31:11.67#ibcon#[27=AT01-04\r\n] 2006.162.07:31:11.67#ibcon#*before write, iclass 34, count 2 2006.162.07:31:11.67#ibcon#enter sib2, iclass 34, count 2 2006.162.07:31:11.67#ibcon#flushed, iclass 34, count 2 2006.162.07:31:11.67#ibcon#about to write, iclass 34, count 2 2006.162.07:31:11.67#ibcon#wrote, iclass 34, count 2 2006.162.07:31:11.67#ibcon#about to read 3, iclass 34, count 2 2006.162.07:31:11.70#ibcon#read 3, iclass 34, count 2 2006.162.07:31:11.70#ibcon#about to read 4, iclass 34, count 2 2006.162.07:31:11.70#ibcon#read 4, iclass 34, count 2 2006.162.07:31:11.70#ibcon#about to read 5, iclass 34, count 2 2006.162.07:31:11.70#ibcon#read 5, iclass 34, count 2 2006.162.07:31:11.70#ibcon#about to read 6, iclass 34, count 2 2006.162.07:31:11.70#ibcon#read 6, iclass 34, count 2 2006.162.07:31:11.70#ibcon#end of sib2, iclass 34, count 2 2006.162.07:31:11.70#ibcon#*after write, iclass 34, count 2 2006.162.07:31:11.70#ibcon#*before return 0, iclass 34, count 2 2006.162.07:31:11.70#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.162.07:31:11.70#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.162.07:31:11.70#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.162.07:31:11.70#ibcon#ireg 7 cls_cnt 0 2006.162.07:31:11.70#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.162.07:31:11.82#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.162.07:31:11.82#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.162.07:31:11.82#ibcon#enter wrdev, iclass 34, count 0 2006.162.07:31:11.82#ibcon#first serial, iclass 34, count 0 2006.162.07:31:11.82#ibcon#enter sib2, iclass 34, count 0 2006.162.07:31:11.82#ibcon#flushed, iclass 34, count 0 2006.162.07:31:11.82#ibcon#about to write, iclass 34, count 0 2006.162.07:31:11.82#ibcon#wrote, iclass 34, count 0 2006.162.07:31:11.82#ibcon#about to read 3, iclass 34, count 0 2006.162.07:31:11.84#ibcon#read 3, iclass 34, count 0 2006.162.07:31:11.84#ibcon#about to read 4, iclass 34, count 0 2006.162.07:31:11.84#ibcon#read 4, iclass 34, count 0 2006.162.07:31:11.84#ibcon#about to read 5, iclass 34, count 0 2006.162.07:31:11.84#ibcon#read 5, iclass 34, count 0 2006.162.07:31:11.84#ibcon#about to read 6, iclass 34, count 0 2006.162.07:31:11.84#ibcon#read 6, iclass 34, count 0 2006.162.07:31:11.84#ibcon#end of sib2, iclass 34, count 0 2006.162.07:31:11.84#ibcon#*mode == 0, iclass 34, count 0 2006.162.07:31:11.84#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.162.07:31:11.84#ibcon#[27=USB\r\n] 2006.162.07:31:11.84#ibcon#*before write, iclass 34, count 0 2006.162.07:31:11.84#ibcon#enter sib2, iclass 34, count 0 2006.162.07:31:11.84#ibcon#flushed, iclass 34, count 0 2006.162.07:31:11.84#ibcon#about to write, iclass 34, count 0 2006.162.07:31:11.84#ibcon#wrote, iclass 34, count 0 2006.162.07:31:11.84#ibcon#about to read 3, iclass 34, count 0 2006.162.07:31:11.87#ibcon#read 3, iclass 34, count 0 2006.162.07:31:11.87#ibcon#about to read 4, iclass 34, count 0 2006.162.07:31:11.87#ibcon#read 4, iclass 34, count 0 2006.162.07:31:11.87#ibcon#about to read 5, iclass 34, count 0 2006.162.07:31:11.87#ibcon#read 5, iclass 34, count 0 2006.162.07:31:11.87#ibcon#about to read 6, iclass 34, count 0 2006.162.07:31:11.87#ibcon#read 6, iclass 34, count 0 2006.162.07:31:11.87#ibcon#end of sib2, iclass 34, count 0 2006.162.07:31:11.87#ibcon#*after write, iclass 34, count 0 2006.162.07:31:11.87#ibcon#*before return 0, iclass 34, count 0 2006.162.07:31:11.87#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.162.07:31:11.87#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.162.07:31:11.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.162.07:31:11.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.162.07:31:11.87$vc4f8/vblo=2,640.99 2006.162.07:31:11.87#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.162.07:31:11.87#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.162.07:31:11.87#ibcon#ireg 17 cls_cnt 0 2006.162.07:31:11.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:31:11.87#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:31:11.87#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:31:11.87#ibcon#enter wrdev, iclass 36, count 0 2006.162.07:31:11.87#ibcon#first serial, iclass 36, count 0 2006.162.07:31:11.87#ibcon#enter sib2, iclass 36, count 0 2006.162.07:31:11.87#ibcon#flushed, iclass 36, count 0 2006.162.07:31:11.87#ibcon#about to write, iclass 36, count 0 2006.162.07:31:11.87#ibcon#wrote, iclass 36, count 0 2006.162.07:31:11.87#ibcon#about to read 3, iclass 36, count 0 2006.162.07:31:11.89#ibcon#read 3, iclass 36, count 0 2006.162.07:31:11.89#ibcon#about to read 4, iclass 36, count 0 2006.162.07:31:11.89#ibcon#read 4, iclass 36, count 0 2006.162.07:31:11.89#ibcon#about to read 5, iclass 36, count 0 2006.162.07:31:11.89#ibcon#read 5, iclass 36, count 0 2006.162.07:31:11.89#ibcon#about to read 6, iclass 36, count 0 2006.162.07:31:11.89#ibcon#read 6, iclass 36, count 0 2006.162.07:31:11.89#ibcon#end of sib2, iclass 36, count 0 2006.162.07:31:11.89#ibcon#*mode == 0, iclass 36, count 0 2006.162.07:31:11.89#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.162.07:31:11.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.07:31:11.89#ibcon#*before write, iclass 36, count 0 2006.162.07:31:11.89#ibcon#enter sib2, iclass 36, count 0 2006.162.07:31:11.89#ibcon#flushed, iclass 36, count 0 2006.162.07:31:11.89#ibcon#about to write, iclass 36, count 0 2006.162.07:31:11.89#ibcon#wrote, iclass 36, count 0 2006.162.07:31:11.89#ibcon#about to read 3, iclass 36, count 0 2006.162.07:31:11.93#ibcon#read 3, iclass 36, count 0 2006.162.07:31:11.93#ibcon#about to read 4, iclass 36, count 0 2006.162.07:31:11.93#ibcon#read 4, iclass 36, count 0 2006.162.07:31:11.93#ibcon#about to read 5, iclass 36, count 0 2006.162.07:31:11.93#ibcon#read 5, iclass 36, count 0 2006.162.07:31:11.93#ibcon#about to read 6, iclass 36, count 0 2006.162.07:31:11.93#ibcon#read 6, iclass 36, count 0 2006.162.07:31:11.93#ibcon#end of sib2, iclass 36, count 0 2006.162.07:31:11.93#ibcon#*after write, iclass 36, count 0 2006.162.07:31:11.93#ibcon#*before return 0, iclass 36, count 0 2006.162.07:31:11.93#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:31:11.93#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:31:11.93#ibcon#about to clear, iclass 36 cls_cnt 0 2006.162.07:31:11.93#ibcon#cleared, iclass 36 cls_cnt 0 2006.162.07:31:11.93$vc4f8/vb=2,4 2006.162.07:31:11.93#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.162.07:31:11.93#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.162.07:31:11.93#ibcon#ireg 11 cls_cnt 2 2006.162.07:31:11.93#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:31:11.99#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:31:11.99#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:31:11.99#ibcon#enter wrdev, iclass 38, count 2 2006.162.07:31:11.99#ibcon#first serial, iclass 38, count 2 2006.162.07:31:11.99#ibcon#enter sib2, iclass 38, count 2 2006.162.07:31:11.99#ibcon#flushed, iclass 38, count 2 2006.162.07:31:11.99#ibcon#about to write, iclass 38, count 2 2006.162.07:31:11.99#ibcon#wrote, iclass 38, count 2 2006.162.07:31:11.99#ibcon#about to read 3, iclass 38, count 2 2006.162.07:31:12.01#ibcon#read 3, iclass 38, count 2 2006.162.07:31:12.01#ibcon#about to read 4, iclass 38, count 2 2006.162.07:31:12.01#ibcon#read 4, iclass 38, count 2 2006.162.07:31:12.01#ibcon#about to read 5, iclass 38, count 2 2006.162.07:31:12.01#ibcon#read 5, iclass 38, count 2 2006.162.07:31:12.01#ibcon#about to read 6, iclass 38, count 2 2006.162.07:31:12.01#ibcon#read 6, iclass 38, count 2 2006.162.07:31:12.01#ibcon#end of sib2, iclass 38, count 2 2006.162.07:31:12.01#ibcon#*mode == 0, iclass 38, count 2 2006.162.07:31:12.01#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.162.07:31:12.01#ibcon#[27=AT02-04\r\n] 2006.162.07:31:12.01#ibcon#*before write, iclass 38, count 2 2006.162.07:31:12.01#ibcon#enter sib2, iclass 38, count 2 2006.162.07:31:12.01#ibcon#flushed, iclass 38, count 2 2006.162.07:31:12.01#ibcon#about to write, iclass 38, count 2 2006.162.07:31:12.01#ibcon#wrote, iclass 38, count 2 2006.162.07:31:12.01#ibcon#about to read 3, iclass 38, count 2 2006.162.07:31:12.04#ibcon#read 3, iclass 38, count 2 2006.162.07:31:12.04#ibcon#about to read 4, iclass 38, count 2 2006.162.07:31:12.04#ibcon#read 4, iclass 38, count 2 2006.162.07:31:12.04#ibcon#about to read 5, iclass 38, count 2 2006.162.07:31:12.04#ibcon#read 5, iclass 38, count 2 2006.162.07:31:12.04#ibcon#about to read 6, iclass 38, count 2 2006.162.07:31:12.04#ibcon#read 6, iclass 38, count 2 2006.162.07:31:12.04#ibcon#end of sib2, iclass 38, count 2 2006.162.07:31:12.04#ibcon#*after write, iclass 38, count 2 2006.162.07:31:12.04#ibcon#*before return 0, iclass 38, count 2 2006.162.07:31:12.04#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:31:12.04#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:31:12.04#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.162.07:31:12.04#ibcon#ireg 7 cls_cnt 0 2006.162.07:31:12.04#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:31:12.16#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:31:12.16#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:31:12.16#ibcon#enter wrdev, iclass 38, count 0 2006.162.07:31:12.16#ibcon#first serial, iclass 38, count 0 2006.162.07:31:12.16#ibcon#enter sib2, iclass 38, count 0 2006.162.07:31:12.16#ibcon#flushed, iclass 38, count 0 2006.162.07:31:12.16#ibcon#about to write, iclass 38, count 0 2006.162.07:31:12.16#ibcon#wrote, iclass 38, count 0 2006.162.07:31:12.16#ibcon#about to read 3, iclass 38, count 0 2006.162.07:31:12.18#ibcon#read 3, iclass 38, count 0 2006.162.07:31:12.18#ibcon#about to read 4, iclass 38, count 0 2006.162.07:31:12.18#ibcon#read 4, iclass 38, count 0 2006.162.07:31:12.18#ibcon#about to read 5, iclass 38, count 0 2006.162.07:31:12.18#ibcon#read 5, iclass 38, count 0 2006.162.07:31:12.18#ibcon#about to read 6, iclass 38, count 0 2006.162.07:31:12.18#ibcon#read 6, iclass 38, count 0 2006.162.07:31:12.18#ibcon#end of sib2, iclass 38, count 0 2006.162.07:31:12.18#ibcon#*mode == 0, iclass 38, count 0 2006.162.07:31:12.18#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.162.07:31:12.18#ibcon#[27=USB\r\n] 2006.162.07:31:12.18#ibcon#*before write, iclass 38, count 0 2006.162.07:31:12.18#ibcon#enter sib2, iclass 38, count 0 2006.162.07:31:12.18#ibcon#flushed, iclass 38, count 0 2006.162.07:31:12.18#ibcon#about to write, iclass 38, count 0 2006.162.07:31:12.18#ibcon#wrote, iclass 38, count 0 2006.162.07:31:12.18#ibcon#about to read 3, iclass 38, count 0 2006.162.07:31:12.21#ibcon#read 3, iclass 38, count 0 2006.162.07:31:12.21#ibcon#about to read 4, iclass 38, count 0 2006.162.07:31:12.21#ibcon#read 4, iclass 38, count 0 2006.162.07:31:12.21#ibcon#about to read 5, iclass 38, count 0 2006.162.07:31:12.21#ibcon#read 5, iclass 38, count 0 2006.162.07:31:12.21#ibcon#about to read 6, iclass 38, count 0 2006.162.07:31:12.21#ibcon#read 6, iclass 38, count 0 2006.162.07:31:12.21#ibcon#end of sib2, iclass 38, count 0 2006.162.07:31:12.21#ibcon#*after write, iclass 38, count 0 2006.162.07:31:12.21#ibcon#*before return 0, iclass 38, count 0 2006.162.07:31:12.21#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:31:12.21#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:31:12.21#ibcon#about to clear, iclass 38 cls_cnt 0 2006.162.07:31:12.21#ibcon#cleared, iclass 38 cls_cnt 0 2006.162.07:31:12.21$vc4f8/vblo=3,656.99 2006.162.07:31:12.21#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.162.07:31:12.21#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.162.07:31:12.21#ibcon#ireg 17 cls_cnt 0 2006.162.07:31:12.21#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:31:12.21#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:31:12.21#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:31:12.21#ibcon#enter wrdev, iclass 40, count 0 2006.162.07:31:12.21#ibcon#first serial, iclass 40, count 0 2006.162.07:31:12.21#ibcon#enter sib2, iclass 40, count 0 2006.162.07:31:12.21#ibcon#flushed, iclass 40, count 0 2006.162.07:31:12.21#ibcon#about to write, iclass 40, count 0 2006.162.07:31:12.21#ibcon#wrote, iclass 40, count 0 2006.162.07:31:12.21#ibcon#about to read 3, iclass 40, count 0 2006.162.07:31:12.23#ibcon#read 3, iclass 40, count 0 2006.162.07:31:12.23#ibcon#about to read 4, iclass 40, count 0 2006.162.07:31:12.23#ibcon#read 4, iclass 40, count 0 2006.162.07:31:12.23#ibcon#about to read 5, iclass 40, count 0 2006.162.07:31:12.23#ibcon#read 5, iclass 40, count 0 2006.162.07:31:12.23#ibcon#about to read 6, iclass 40, count 0 2006.162.07:31:12.23#ibcon#read 6, iclass 40, count 0 2006.162.07:31:12.23#ibcon#end of sib2, iclass 40, count 0 2006.162.07:31:12.23#ibcon#*mode == 0, iclass 40, count 0 2006.162.07:31:12.23#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.162.07:31:12.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.07:31:12.23#ibcon#*before write, iclass 40, count 0 2006.162.07:31:12.23#ibcon#enter sib2, iclass 40, count 0 2006.162.07:31:12.23#ibcon#flushed, iclass 40, count 0 2006.162.07:31:12.23#ibcon#about to write, iclass 40, count 0 2006.162.07:31:12.23#ibcon#wrote, iclass 40, count 0 2006.162.07:31:12.23#ibcon#about to read 3, iclass 40, count 0 2006.162.07:31:12.27#ibcon#read 3, iclass 40, count 0 2006.162.07:31:12.27#ibcon#about to read 4, iclass 40, count 0 2006.162.07:31:12.27#ibcon#read 4, iclass 40, count 0 2006.162.07:31:12.27#ibcon#about to read 5, iclass 40, count 0 2006.162.07:31:12.27#ibcon#read 5, iclass 40, count 0 2006.162.07:31:12.27#ibcon#about to read 6, iclass 40, count 0 2006.162.07:31:12.27#ibcon#read 6, iclass 40, count 0 2006.162.07:31:12.27#ibcon#end of sib2, iclass 40, count 0 2006.162.07:31:12.27#ibcon#*after write, iclass 40, count 0 2006.162.07:31:12.27#ibcon#*before return 0, iclass 40, count 0 2006.162.07:31:12.27#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:31:12.27#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:31:12.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.162.07:31:12.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.162.07:31:12.27$vc4f8/vb=3,4 2006.162.07:31:12.27#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.162.07:31:12.27#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.162.07:31:12.27#ibcon#ireg 11 cls_cnt 2 2006.162.07:31:12.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:31:12.33#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:31:12.33#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:31:12.33#ibcon#enter wrdev, iclass 4, count 2 2006.162.07:31:12.33#ibcon#first serial, iclass 4, count 2 2006.162.07:31:12.33#ibcon#enter sib2, iclass 4, count 2 2006.162.07:31:12.33#ibcon#flushed, iclass 4, count 2 2006.162.07:31:12.33#ibcon#about to write, iclass 4, count 2 2006.162.07:31:12.33#ibcon#wrote, iclass 4, count 2 2006.162.07:31:12.33#ibcon#about to read 3, iclass 4, count 2 2006.162.07:31:12.35#ibcon#read 3, iclass 4, count 2 2006.162.07:31:12.35#ibcon#about to read 4, iclass 4, count 2 2006.162.07:31:12.35#ibcon#read 4, iclass 4, count 2 2006.162.07:31:12.35#ibcon#about to read 5, iclass 4, count 2 2006.162.07:31:12.35#ibcon#read 5, iclass 4, count 2 2006.162.07:31:12.35#ibcon#about to read 6, iclass 4, count 2 2006.162.07:31:12.35#ibcon#read 6, iclass 4, count 2 2006.162.07:31:12.35#ibcon#end of sib2, iclass 4, count 2 2006.162.07:31:12.35#ibcon#*mode == 0, iclass 4, count 2 2006.162.07:31:12.35#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.162.07:31:12.35#ibcon#[27=AT03-04\r\n] 2006.162.07:31:12.35#ibcon#*before write, iclass 4, count 2 2006.162.07:31:12.35#ibcon#enter sib2, iclass 4, count 2 2006.162.07:31:12.35#ibcon#flushed, iclass 4, count 2 2006.162.07:31:12.35#ibcon#about to write, iclass 4, count 2 2006.162.07:31:12.35#ibcon#wrote, iclass 4, count 2 2006.162.07:31:12.35#ibcon#about to read 3, iclass 4, count 2 2006.162.07:31:12.38#ibcon#read 3, iclass 4, count 2 2006.162.07:31:12.38#ibcon#about to read 4, iclass 4, count 2 2006.162.07:31:12.38#ibcon#read 4, iclass 4, count 2 2006.162.07:31:12.38#ibcon#about to read 5, iclass 4, count 2 2006.162.07:31:12.38#ibcon#read 5, iclass 4, count 2 2006.162.07:31:12.38#ibcon#about to read 6, iclass 4, count 2 2006.162.07:31:12.38#ibcon#read 6, iclass 4, count 2 2006.162.07:31:12.38#ibcon#end of sib2, iclass 4, count 2 2006.162.07:31:12.38#ibcon#*after write, iclass 4, count 2 2006.162.07:31:12.38#ibcon#*before return 0, iclass 4, count 2 2006.162.07:31:12.38#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:31:12.38#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:31:12.38#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.162.07:31:12.38#ibcon#ireg 7 cls_cnt 0 2006.162.07:31:12.38#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:31:12.50#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:31:12.50#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:31:12.50#ibcon#enter wrdev, iclass 4, count 0 2006.162.07:31:12.50#ibcon#first serial, iclass 4, count 0 2006.162.07:31:12.50#ibcon#enter sib2, iclass 4, count 0 2006.162.07:31:12.50#ibcon#flushed, iclass 4, count 0 2006.162.07:31:12.50#ibcon#about to write, iclass 4, count 0 2006.162.07:31:12.50#ibcon#wrote, iclass 4, count 0 2006.162.07:31:12.50#ibcon#about to read 3, iclass 4, count 0 2006.162.07:31:12.52#ibcon#read 3, iclass 4, count 0 2006.162.07:31:12.52#ibcon#about to read 4, iclass 4, count 0 2006.162.07:31:12.52#ibcon#read 4, iclass 4, count 0 2006.162.07:31:12.52#ibcon#about to read 5, iclass 4, count 0 2006.162.07:31:12.52#ibcon#read 5, iclass 4, count 0 2006.162.07:31:12.52#ibcon#about to read 6, iclass 4, count 0 2006.162.07:31:12.52#ibcon#read 6, iclass 4, count 0 2006.162.07:31:12.52#ibcon#end of sib2, iclass 4, count 0 2006.162.07:31:12.52#ibcon#*mode == 0, iclass 4, count 0 2006.162.07:31:12.52#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.162.07:31:12.52#ibcon#[27=USB\r\n] 2006.162.07:31:12.52#ibcon#*before write, iclass 4, count 0 2006.162.07:31:12.52#ibcon#enter sib2, iclass 4, count 0 2006.162.07:31:12.52#ibcon#flushed, iclass 4, count 0 2006.162.07:31:12.52#ibcon#about to write, iclass 4, count 0 2006.162.07:31:12.52#ibcon#wrote, iclass 4, count 0 2006.162.07:31:12.52#ibcon#about to read 3, iclass 4, count 0 2006.162.07:31:12.55#ibcon#read 3, iclass 4, count 0 2006.162.07:31:12.55#ibcon#about to read 4, iclass 4, count 0 2006.162.07:31:12.55#ibcon#read 4, iclass 4, count 0 2006.162.07:31:12.55#ibcon#about to read 5, iclass 4, count 0 2006.162.07:31:12.55#ibcon#read 5, iclass 4, count 0 2006.162.07:31:12.55#ibcon#about to read 6, iclass 4, count 0 2006.162.07:31:12.55#ibcon#read 6, iclass 4, count 0 2006.162.07:31:12.55#ibcon#end of sib2, iclass 4, count 0 2006.162.07:31:12.55#ibcon#*after write, iclass 4, count 0 2006.162.07:31:12.55#ibcon#*before return 0, iclass 4, count 0 2006.162.07:31:12.55#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:31:12.55#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:31:12.55#ibcon#about to clear, iclass 4 cls_cnt 0 2006.162.07:31:12.55#ibcon#cleared, iclass 4 cls_cnt 0 2006.162.07:31:12.55$vc4f8/vblo=4,712.99 2006.162.07:31:12.55#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.162.07:31:12.55#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.162.07:31:12.55#ibcon#ireg 17 cls_cnt 0 2006.162.07:31:12.55#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:31:12.55#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:31:12.55#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:31:12.55#ibcon#enter wrdev, iclass 6, count 0 2006.162.07:31:12.55#ibcon#first serial, iclass 6, count 0 2006.162.07:31:12.55#ibcon#enter sib2, iclass 6, count 0 2006.162.07:31:12.55#ibcon#flushed, iclass 6, count 0 2006.162.07:31:12.55#ibcon#about to write, iclass 6, count 0 2006.162.07:31:12.55#ibcon#wrote, iclass 6, count 0 2006.162.07:31:12.55#ibcon#about to read 3, iclass 6, count 0 2006.162.07:31:12.57#ibcon#read 3, iclass 6, count 0 2006.162.07:31:12.57#ibcon#about to read 4, iclass 6, count 0 2006.162.07:31:12.57#ibcon#read 4, iclass 6, count 0 2006.162.07:31:12.57#ibcon#about to read 5, iclass 6, count 0 2006.162.07:31:12.57#ibcon#read 5, iclass 6, count 0 2006.162.07:31:12.57#ibcon#about to read 6, iclass 6, count 0 2006.162.07:31:12.57#ibcon#read 6, iclass 6, count 0 2006.162.07:31:12.57#ibcon#end of sib2, iclass 6, count 0 2006.162.07:31:12.57#ibcon#*mode == 0, iclass 6, count 0 2006.162.07:31:12.57#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.162.07:31:12.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.07:31:12.57#ibcon#*before write, iclass 6, count 0 2006.162.07:31:12.57#ibcon#enter sib2, iclass 6, count 0 2006.162.07:31:12.57#ibcon#flushed, iclass 6, count 0 2006.162.07:31:12.57#ibcon#about to write, iclass 6, count 0 2006.162.07:31:12.57#ibcon#wrote, iclass 6, count 0 2006.162.07:31:12.57#ibcon#about to read 3, iclass 6, count 0 2006.162.07:31:12.61#ibcon#read 3, iclass 6, count 0 2006.162.07:31:12.61#ibcon#about to read 4, iclass 6, count 0 2006.162.07:31:12.61#ibcon#read 4, iclass 6, count 0 2006.162.07:31:12.61#ibcon#about to read 5, iclass 6, count 0 2006.162.07:31:12.61#ibcon#read 5, iclass 6, count 0 2006.162.07:31:12.61#ibcon#about to read 6, iclass 6, count 0 2006.162.07:31:12.61#ibcon#read 6, iclass 6, count 0 2006.162.07:31:12.61#ibcon#end of sib2, iclass 6, count 0 2006.162.07:31:12.61#ibcon#*after write, iclass 6, count 0 2006.162.07:31:12.61#ibcon#*before return 0, iclass 6, count 0 2006.162.07:31:12.61#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:31:12.61#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:31:12.61#ibcon#about to clear, iclass 6 cls_cnt 0 2006.162.07:31:12.61#ibcon#cleared, iclass 6 cls_cnt 0 2006.162.07:31:12.61$vc4f8/vb=4,4 2006.162.07:31:12.61#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.162.07:31:12.61#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.162.07:31:12.61#ibcon#ireg 11 cls_cnt 2 2006.162.07:31:12.61#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:31:12.67#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:31:12.67#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:31:12.67#ibcon#enter wrdev, iclass 10, count 2 2006.162.07:31:12.67#ibcon#first serial, iclass 10, count 2 2006.162.07:31:12.67#ibcon#enter sib2, iclass 10, count 2 2006.162.07:31:12.67#ibcon#flushed, iclass 10, count 2 2006.162.07:31:12.67#ibcon#about to write, iclass 10, count 2 2006.162.07:31:12.67#ibcon#wrote, iclass 10, count 2 2006.162.07:31:12.67#ibcon#about to read 3, iclass 10, count 2 2006.162.07:31:12.69#ibcon#read 3, iclass 10, count 2 2006.162.07:31:12.69#ibcon#about to read 4, iclass 10, count 2 2006.162.07:31:12.69#ibcon#read 4, iclass 10, count 2 2006.162.07:31:12.69#ibcon#about to read 5, iclass 10, count 2 2006.162.07:31:12.69#ibcon#read 5, iclass 10, count 2 2006.162.07:31:12.69#ibcon#about to read 6, iclass 10, count 2 2006.162.07:31:12.69#ibcon#read 6, iclass 10, count 2 2006.162.07:31:12.69#ibcon#end of sib2, iclass 10, count 2 2006.162.07:31:12.69#ibcon#*mode == 0, iclass 10, count 2 2006.162.07:31:12.69#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.162.07:31:12.69#ibcon#[27=AT04-04\r\n] 2006.162.07:31:12.69#ibcon#*before write, iclass 10, count 2 2006.162.07:31:12.69#ibcon#enter sib2, iclass 10, count 2 2006.162.07:31:12.69#ibcon#flushed, iclass 10, count 2 2006.162.07:31:12.69#ibcon#about to write, iclass 10, count 2 2006.162.07:31:12.69#ibcon#wrote, iclass 10, count 2 2006.162.07:31:12.69#ibcon#about to read 3, iclass 10, count 2 2006.162.07:31:12.72#ibcon#read 3, iclass 10, count 2 2006.162.07:31:12.72#ibcon#about to read 4, iclass 10, count 2 2006.162.07:31:12.72#ibcon#read 4, iclass 10, count 2 2006.162.07:31:12.72#ibcon#about to read 5, iclass 10, count 2 2006.162.07:31:12.72#ibcon#read 5, iclass 10, count 2 2006.162.07:31:12.72#ibcon#about to read 6, iclass 10, count 2 2006.162.07:31:12.72#ibcon#read 6, iclass 10, count 2 2006.162.07:31:12.72#ibcon#end of sib2, iclass 10, count 2 2006.162.07:31:12.72#ibcon#*after write, iclass 10, count 2 2006.162.07:31:12.72#ibcon#*before return 0, iclass 10, count 2 2006.162.07:31:12.72#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:31:12.72#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:31:12.72#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.162.07:31:12.72#ibcon#ireg 7 cls_cnt 0 2006.162.07:31:12.72#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:31:12.84#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:31:12.84#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:31:12.84#ibcon#enter wrdev, iclass 10, count 0 2006.162.07:31:12.84#ibcon#first serial, iclass 10, count 0 2006.162.07:31:12.84#ibcon#enter sib2, iclass 10, count 0 2006.162.07:31:12.84#ibcon#flushed, iclass 10, count 0 2006.162.07:31:12.84#ibcon#about to write, iclass 10, count 0 2006.162.07:31:12.84#ibcon#wrote, iclass 10, count 0 2006.162.07:31:12.84#ibcon#about to read 3, iclass 10, count 0 2006.162.07:31:12.86#ibcon#read 3, iclass 10, count 0 2006.162.07:31:12.86#ibcon#about to read 4, iclass 10, count 0 2006.162.07:31:12.86#ibcon#read 4, iclass 10, count 0 2006.162.07:31:12.86#ibcon#about to read 5, iclass 10, count 0 2006.162.07:31:12.86#ibcon#read 5, iclass 10, count 0 2006.162.07:31:12.86#ibcon#about to read 6, iclass 10, count 0 2006.162.07:31:12.86#ibcon#read 6, iclass 10, count 0 2006.162.07:31:12.86#ibcon#end of sib2, iclass 10, count 0 2006.162.07:31:12.86#ibcon#*mode == 0, iclass 10, count 0 2006.162.07:31:12.86#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.162.07:31:12.86#ibcon#[27=USB\r\n] 2006.162.07:31:12.86#ibcon#*before write, iclass 10, count 0 2006.162.07:31:12.86#ibcon#enter sib2, iclass 10, count 0 2006.162.07:31:12.86#ibcon#flushed, iclass 10, count 0 2006.162.07:31:12.86#ibcon#about to write, iclass 10, count 0 2006.162.07:31:12.86#ibcon#wrote, iclass 10, count 0 2006.162.07:31:12.86#ibcon#about to read 3, iclass 10, count 0 2006.162.07:31:12.89#ibcon#read 3, iclass 10, count 0 2006.162.07:31:12.89#ibcon#about to read 4, iclass 10, count 0 2006.162.07:31:12.89#ibcon#read 4, iclass 10, count 0 2006.162.07:31:12.89#ibcon#about to read 5, iclass 10, count 0 2006.162.07:31:12.89#ibcon#read 5, iclass 10, count 0 2006.162.07:31:12.89#ibcon#about to read 6, iclass 10, count 0 2006.162.07:31:12.89#ibcon#read 6, iclass 10, count 0 2006.162.07:31:12.89#ibcon#end of sib2, iclass 10, count 0 2006.162.07:31:12.89#ibcon#*after write, iclass 10, count 0 2006.162.07:31:12.89#ibcon#*before return 0, iclass 10, count 0 2006.162.07:31:12.89#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:31:12.89#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:31:12.89#ibcon#about to clear, iclass 10 cls_cnt 0 2006.162.07:31:12.89#ibcon#cleared, iclass 10 cls_cnt 0 2006.162.07:31:12.89$vc4f8/vblo=5,744.99 2006.162.07:31:12.89#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.162.07:31:12.89#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.162.07:31:12.89#ibcon#ireg 17 cls_cnt 0 2006.162.07:31:12.89#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:31:12.89#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:31:12.89#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:31:12.89#ibcon#enter wrdev, iclass 12, count 0 2006.162.07:31:12.89#ibcon#first serial, iclass 12, count 0 2006.162.07:31:12.89#ibcon#enter sib2, iclass 12, count 0 2006.162.07:31:12.89#ibcon#flushed, iclass 12, count 0 2006.162.07:31:12.89#ibcon#about to write, iclass 12, count 0 2006.162.07:31:12.89#ibcon#wrote, iclass 12, count 0 2006.162.07:31:12.89#ibcon#about to read 3, iclass 12, count 0 2006.162.07:31:12.91#ibcon#read 3, iclass 12, count 0 2006.162.07:31:12.91#ibcon#about to read 4, iclass 12, count 0 2006.162.07:31:12.91#ibcon#read 4, iclass 12, count 0 2006.162.07:31:12.91#ibcon#about to read 5, iclass 12, count 0 2006.162.07:31:12.91#ibcon#read 5, iclass 12, count 0 2006.162.07:31:12.91#ibcon#about to read 6, iclass 12, count 0 2006.162.07:31:12.91#ibcon#read 6, iclass 12, count 0 2006.162.07:31:12.91#ibcon#end of sib2, iclass 12, count 0 2006.162.07:31:12.91#ibcon#*mode == 0, iclass 12, count 0 2006.162.07:31:12.91#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.162.07:31:12.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.07:31:12.91#ibcon#*before write, iclass 12, count 0 2006.162.07:31:12.91#ibcon#enter sib2, iclass 12, count 0 2006.162.07:31:12.91#ibcon#flushed, iclass 12, count 0 2006.162.07:31:12.91#ibcon#about to write, iclass 12, count 0 2006.162.07:31:12.91#ibcon#wrote, iclass 12, count 0 2006.162.07:31:12.91#ibcon#about to read 3, iclass 12, count 0 2006.162.07:31:12.95#ibcon#read 3, iclass 12, count 0 2006.162.07:31:12.95#ibcon#about to read 4, iclass 12, count 0 2006.162.07:31:12.95#ibcon#read 4, iclass 12, count 0 2006.162.07:31:12.95#ibcon#about to read 5, iclass 12, count 0 2006.162.07:31:12.95#ibcon#read 5, iclass 12, count 0 2006.162.07:31:12.95#ibcon#about to read 6, iclass 12, count 0 2006.162.07:31:12.95#ibcon#read 6, iclass 12, count 0 2006.162.07:31:12.95#ibcon#end of sib2, iclass 12, count 0 2006.162.07:31:12.95#ibcon#*after write, iclass 12, count 0 2006.162.07:31:12.95#ibcon#*before return 0, iclass 12, count 0 2006.162.07:31:12.95#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:31:12.95#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:31:12.95#ibcon#about to clear, iclass 12 cls_cnt 0 2006.162.07:31:12.95#ibcon#cleared, iclass 12 cls_cnt 0 2006.162.07:31:12.95$vc4f8/vb=5,4 2006.162.07:31:12.95#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.162.07:31:12.95#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.162.07:31:12.95#ibcon#ireg 11 cls_cnt 2 2006.162.07:31:12.95#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:31:13.01#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:31:13.01#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:31:13.01#ibcon#enter wrdev, iclass 14, count 2 2006.162.07:31:13.01#ibcon#first serial, iclass 14, count 2 2006.162.07:31:13.01#ibcon#enter sib2, iclass 14, count 2 2006.162.07:31:13.01#ibcon#flushed, iclass 14, count 2 2006.162.07:31:13.01#ibcon#about to write, iclass 14, count 2 2006.162.07:31:13.01#ibcon#wrote, iclass 14, count 2 2006.162.07:31:13.01#ibcon#about to read 3, iclass 14, count 2 2006.162.07:31:13.03#ibcon#read 3, iclass 14, count 2 2006.162.07:31:13.03#ibcon#about to read 4, iclass 14, count 2 2006.162.07:31:13.03#ibcon#read 4, iclass 14, count 2 2006.162.07:31:13.03#ibcon#about to read 5, iclass 14, count 2 2006.162.07:31:13.03#ibcon#read 5, iclass 14, count 2 2006.162.07:31:13.03#ibcon#about to read 6, iclass 14, count 2 2006.162.07:31:13.03#ibcon#read 6, iclass 14, count 2 2006.162.07:31:13.03#ibcon#end of sib2, iclass 14, count 2 2006.162.07:31:13.03#ibcon#*mode == 0, iclass 14, count 2 2006.162.07:31:13.03#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.162.07:31:13.03#ibcon#[27=AT05-04\r\n] 2006.162.07:31:13.03#ibcon#*before write, iclass 14, count 2 2006.162.07:31:13.03#ibcon#enter sib2, iclass 14, count 2 2006.162.07:31:13.03#ibcon#flushed, iclass 14, count 2 2006.162.07:31:13.03#ibcon#about to write, iclass 14, count 2 2006.162.07:31:13.03#ibcon#wrote, iclass 14, count 2 2006.162.07:31:13.03#ibcon#about to read 3, iclass 14, count 2 2006.162.07:31:13.06#ibcon#read 3, iclass 14, count 2 2006.162.07:31:13.06#ibcon#about to read 4, iclass 14, count 2 2006.162.07:31:13.06#ibcon#read 4, iclass 14, count 2 2006.162.07:31:13.06#ibcon#about to read 5, iclass 14, count 2 2006.162.07:31:13.06#ibcon#read 5, iclass 14, count 2 2006.162.07:31:13.06#ibcon#about to read 6, iclass 14, count 2 2006.162.07:31:13.06#ibcon#read 6, iclass 14, count 2 2006.162.07:31:13.06#ibcon#end of sib2, iclass 14, count 2 2006.162.07:31:13.06#ibcon#*after write, iclass 14, count 2 2006.162.07:31:13.06#ibcon#*before return 0, iclass 14, count 2 2006.162.07:31:13.06#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:31:13.06#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:31:13.06#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.162.07:31:13.06#ibcon#ireg 7 cls_cnt 0 2006.162.07:31:13.06#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:31:13.18#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:31:13.18#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:31:13.18#ibcon#enter wrdev, iclass 14, count 0 2006.162.07:31:13.18#ibcon#first serial, iclass 14, count 0 2006.162.07:31:13.18#ibcon#enter sib2, iclass 14, count 0 2006.162.07:31:13.18#ibcon#flushed, iclass 14, count 0 2006.162.07:31:13.18#ibcon#about to write, iclass 14, count 0 2006.162.07:31:13.18#ibcon#wrote, iclass 14, count 0 2006.162.07:31:13.18#ibcon#about to read 3, iclass 14, count 0 2006.162.07:31:13.20#ibcon#read 3, iclass 14, count 0 2006.162.07:31:13.20#ibcon#about to read 4, iclass 14, count 0 2006.162.07:31:13.20#ibcon#read 4, iclass 14, count 0 2006.162.07:31:13.20#ibcon#about to read 5, iclass 14, count 0 2006.162.07:31:13.20#ibcon#read 5, iclass 14, count 0 2006.162.07:31:13.20#ibcon#about to read 6, iclass 14, count 0 2006.162.07:31:13.20#ibcon#read 6, iclass 14, count 0 2006.162.07:31:13.20#ibcon#end of sib2, iclass 14, count 0 2006.162.07:31:13.20#ibcon#*mode == 0, iclass 14, count 0 2006.162.07:31:13.20#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.07:31:13.20#ibcon#[27=USB\r\n] 2006.162.07:31:13.20#ibcon#*before write, iclass 14, count 0 2006.162.07:31:13.20#ibcon#enter sib2, iclass 14, count 0 2006.162.07:31:13.20#ibcon#flushed, iclass 14, count 0 2006.162.07:31:13.20#ibcon#about to write, iclass 14, count 0 2006.162.07:31:13.20#ibcon#wrote, iclass 14, count 0 2006.162.07:31:13.20#ibcon#about to read 3, iclass 14, count 0 2006.162.07:31:13.23#ibcon#read 3, iclass 14, count 0 2006.162.07:31:13.23#ibcon#about to read 4, iclass 14, count 0 2006.162.07:31:13.23#ibcon#read 4, iclass 14, count 0 2006.162.07:31:13.23#ibcon#about to read 5, iclass 14, count 0 2006.162.07:31:13.23#ibcon#read 5, iclass 14, count 0 2006.162.07:31:13.23#ibcon#about to read 6, iclass 14, count 0 2006.162.07:31:13.23#ibcon#read 6, iclass 14, count 0 2006.162.07:31:13.23#ibcon#end of sib2, iclass 14, count 0 2006.162.07:31:13.23#ibcon#*after write, iclass 14, count 0 2006.162.07:31:13.23#ibcon#*before return 0, iclass 14, count 0 2006.162.07:31:13.23#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:31:13.23#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:31:13.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.07:31:13.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.07:31:13.23$vc4f8/vblo=6,752.99 2006.162.07:31:13.23#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.162.07:31:13.23#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.162.07:31:13.23#ibcon#ireg 17 cls_cnt 0 2006.162.07:31:13.23#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:31:13.23#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:31:13.23#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:31:13.23#ibcon#enter wrdev, iclass 16, count 0 2006.162.07:31:13.23#ibcon#first serial, iclass 16, count 0 2006.162.07:31:13.23#ibcon#enter sib2, iclass 16, count 0 2006.162.07:31:13.23#ibcon#flushed, iclass 16, count 0 2006.162.07:31:13.23#ibcon#about to write, iclass 16, count 0 2006.162.07:31:13.23#ibcon#wrote, iclass 16, count 0 2006.162.07:31:13.23#ibcon#about to read 3, iclass 16, count 0 2006.162.07:31:13.25#ibcon#read 3, iclass 16, count 0 2006.162.07:31:13.25#ibcon#about to read 4, iclass 16, count 0 2006.162.07:31:13.25#ibcon#read 4, iclass 16, count 0 2006.162.07:31:13.25#ibcon#about to read 5, iclass 16, count 0 2006.162.07:31:13.25#ibcon#read 5, iclass 16, count 0 2006.162.07:31:13.25#ibcon#about to read 6, iclass 16, count 0 2006.162.07:31:13.25#ibcon#read 6, iclass 16, count 0 2006.162.07:31:13.25#ibcon#end of sib2, iclass 16, count 0 2006.162.07:31:13.25#ibcon#*mode == 0, iclass 16, count 0 2006.162.07:31:13.25#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.162.07:31:13.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.07:31:13.25#ibcon#*before write, iclass 16, count 0 2006.162.07:31:13.25#ibcon#enter sib2, iclass 16, count 0 2006.162.07:31:13.25#ibcon#flushed, iclass 16, count 0 2006.162.07:31:13.25#ibcon#about to write, iclass 16, count 0 2006.162.07:31:13.25#ibcon#wrote, iclass 16, count 0 2006.162.07:31:13.25#ibcon#about to read 3, iclass 16, count 0 2006.162.07:31:13.29#ibcon#read 3, iclass 16, count 0 2006.162.07:31:13.29#ibcon#about to read 4, iclass 16, count 0 2006.162.07:31:13.29#ibcon#read 4, iclass 16, count 0 2006.162.07:31:13.29#ibcon#about to read 5, iclass 16, count 0 2006.162.07:31:13.29#ibcon#read 5, iclass 16, count 0 2006.162.07:31:13.29#ibcon#about to read 6, iclass 16, count 0 2006.162.07:31:13.29#ibcon#read 6, iclass 16, count 0 2006.162.07:31:13.29#ibcon#end of sib2, iclass 16, count 0 2006.162.07:31:13.29#ibcon#*after write, iclass 16, count 0 2006.162.07:31:13.29#ibcon#*before return 0, iclass 16, count 0 2006.162.07:31:13.29#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:31:13.29#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:31:13.29#ibcon#about to clear, iclass 16 cls_cnt 0 2006.162.07:31:13.29#ibcon#cleared, iclass 16 cls_cnt 0 2006.162.07:31:13.29$vc4f8/vb=6,4 2006.162.07:31:13.29#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.162.07:31:13.29#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.162.07:31:13.29#ibcon#ireg 11 cls_cnt 2 2006.162.07:31:13.29#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:31:13.35#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:31:13.35#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:31:13.35#ibcon#enter wrdev, iclass 18, count 2 2006.162.07:31:13.35#ibcon#first serial, iclass 18, count 2 2006.162.07:31:13.35#ibcon#enter sib2, iclass 18, count 2 2006.162.07:31:13.35#ibcon#flushed, iclass 18, count 2 2006.162.07:31:13.35#ibcon#about to write, iclass 18, count 2 2006.162.07:31:13.35#ibcon#wrote, iclass 18, count 2 2006.162.07:31:13.35#ibcon#about to read 3, iclass 18, count 2 2006.162.07:31:13.37#ibcon#read 3, iclass 18, count 2 2006.162.07:31:13.37#ibcon#about to read 4, iclass 18, count 2 2006.162.07:31:13.37#ibcon#read 4, iclass 18, count 2 2006.162.07:31:13.37#ibcon#about to read 5, iclass 18, count 2 2006.162.07:31:13.37#ibcon#read 5, iclass 18, count 2 2006.162.07:31:13.37#ibcon#about to read 6, iclass 18, count 2 2006.162.07:31:13.37#ibcon#read 6, iclass 18, count 2 2006.162.07:31:13.37#ibcon#end of sib2, iclass 18, count 2 2006.162.07:31:13.37#ibcon#*mode == 0, iclass 18, count 2 2006.162.07:31:13.37#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.162.07:31:13.37#ibcon#[27=AT06-04\r\n] 2006.162.07:31:13.37#ibcon#*before write, iclass 18, count 2 2006.162.07:31:13.37#ibcon#enter sib2, iclass 18, count 2 2006.162.07:31:13.37#ibcon#flushed, iclass 18, count 2 2006.162.07:31:13.37#ibcon#about to write, iclass 18, count 2 2006.162.07:31:13.37#ibcon#wrote, iclass 18, count 2 2006.162.07:31:13.37#ibcon#about to read 3, iclass 18, count 2 2006.162.07:31:13.40#ibcon#read 3, iclass 18, count 2 2006.162.07:31:13.40#ibcon#about to read 4, iclass 18, count 2 2006.162.07:31:13.40#ibcon#read 4, iclass 18, count 2 2006.162.07:31:13.40#ibcon#about to read 5, iclass 18, count 2 2006.162.07:31:13.40#ibcon#read 5, iclass 18, count 2 2006.162.07:31:13.40#ibcon#about to read 6, iclass 18, count 2 2006.162.07:31:13.40#ibcon#read 6, iclass 18, count 2 2006.162.07:31:13.40#ibcon#end of sib2, iclass 18, count 2 2006.162.07:31:13.40#ibcon#*after write, iclass 18, count 2 2006.162.07:31:13.40#ibcon#*before return 0, iclass 18, count 2 2006.162.07:31:13.40#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:31:13.40#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:31:13.40#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.162.07:31:13.40#ibcon#ireg 7 cls_cnt 0 2006.162.07:31:13.40#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:31:13.52#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:31:13.52#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:31:13.52#ibcon#enter wrdev, iclass 18, count 0 2006.162.07:31:13.52#ibcon#first serial, iclass 18, count 0 2006.162.07:31:13.52#ibcon#enter sib2, iclass 18, count 0 2006.162.07:31:13.52#ibcon#flushed, iclass 18, count 0 2006.162.07:31:13.52#ibcon#about to write, iclass 18, count 0 2006.162.07:31:13.52#ibcon#wrote, iclass 18, count 0 2006.162.07:31:13.52#ibcon#about to read 3, iclass 18, count 0 2006.162.07:31:13.54#ibcon#read 3, iclass 18, count 0 2006.162.07:31:13.54#ibcon#about to read 4, iclass 18, count 0 2006.162.07:31:13.54#ibcon#read 4, iclass 18, count 0 2006.162.07:31:13.54#ibcon#about to read 5, iclass 18, count 0 2006.162.07:31:13.54#ibcon#read 5, iclass 18, count 0 2006.162.07:31:13.54#ibcon#about to read 6, iclass 18, count 0 2006.162.07:31:13.54#ibcon#read 6, iclass 18, count 0 2006.162.07:31:13.54#ibcon#end of sib2, iclass 18, count 0 2006.162.07:31:13.54#ibcon#*mode == 0, iclass 18, count 0 2006.162.07:31:13.54#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.162.07:31:13.54#ibcon#[27=USB\r\n] 2006.162.07:31:13.54#ibcon#*before write, iclass 18, count 0 2006.162.07:31:13.54#ibcon#enter sib2, iclass 18, count 0 2006.162.07:31:13.54#ibcon#flushed, iclass 18, count 0 2006.162.07:31:13.54#ibcon#about to write, iclass 18, count 0 2006.162.07:31:13.54#ibcon#wrote, iclass 18, count 0 2006.162.07:31:13.54#ibcon#about to read 3, iclass 18, count 0 2006.162.07:31:13.57#ibcon#read 3, iclass 18, count 0 2006.162.07:31:13.57#ibcon#about to read 4, iclass 18, count 0 2006.162.07:31:13.57#ibcon#read 4, iclass 18, count 0 2006.162.07:31:13.57#ibcon#about to read 5, iclass 18, count 0 2006.162.07:31:13.57#ibcon#read 5, iclass 18, count 0 2006.162.07:31:13.57#ibcon#about to read 6, iclass 18, count 0 2006.162.07:31:13.57#ibcon#read 6, iclass 18, count 0 2006.162.07:31:13.57#ibcon#end of sib2, iclass 18, count 0 2006.162.07:31:13.57#ibcon#*after write, iclass 18, count 0 2006.162.07:31:13.57#ibcon#*before return 0, iclass 18, count 0 2006.162.07:31:13.57#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:31:13.57#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:31:13.57#ibcon#about to clear, iclass 18 cls_cnt 0 2006.162.07:31:13.57#ibcon#cleared, iclass 18 cls_cnt 0 2006.162.07:31:13.57$vc4f8/vabw=wide 2006.162.07:31:13.57#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.162.07:31:13.57#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.162.07:31:13.57#ibcon#ireg 8 cls_cnt 0 2006.162.07:31:13.57#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:31:13.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:31:13.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:31:13.57#ibcon#enter wrdev, iclass 20, count 0 2006.162.07:31:13.57#ibcon#first serial, iclass 20, count 0 2006.162.07:31:13.57#ibcon#enter sib2, iclass 20, count 0 2006.162.07:31:13.57#ibcon#flushed, iclass 20, count 0 2006.162.07:31:13.57#ibcon#about to write, iclass 20, count 0 2006.162.07:31:13.57#ibcon#wrote, iclass 20, count 0 2006.162.07:31:13.57#ibcon#about to read 3, iclass 20, count 0 2006.162.07:31:13.59#ibcon#read 3, iclass 20, count 0 2006.162.07:31:13.59#ibcon#about to read 4, iclass 20, count 0 2006.162.07:31:13.59#ibcon#read 4, iclass 20, count 0 2006.162.07:31:13.59#ibcon#about to read 5, iclass 20, count 0 2006.162.07:31:13.59#ibcon#read 5, iclass 20, count 0 2006.162.07:31:13.59#ibcon#about to read 6, iclass 20, count 0 2006.162.07:31:13.59#ibcon#read 6, iclass 20, count 0 2006.162.07:31:13.59#ibcon#end of sib2, iclass 20, count 0 2006.162.07:31:13.59#ibcon#*mode == 0, iclass 20, count 0 2006.162.07:31:13.59#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.07:31:13.59#ibcon#[25=BW32\r\n] 2006.162.07:31:13.59#ibcon#*before write, iclass 20, count 0 2006.162.07:31:13.59#ibcon#enter sib2, iclass 20, count 0 2006.162.07:31:13.59#ibcon#flushed, iclass 20, count 0 2006.162.07:31:13.59#ibcon#about to write, iclass 20, count 0 2006.162.07:31:13.59#ibcon#wrote, iclass 20, count 0 2006.162.07:31:13.59#ibcon#about to read 3, iclass 20, count 0 2006.162.07:31:13.62#ibcon#read 3, iclass 20, count 0 2006.162.07:31:13.62#ibcon#about to read 4, iclass 20, count 0 2006.162.07:31:13.62#ibcon#read 4, iclass 20, count 0 2006.162.07:31:13.62#ibcon#about to read 5, iclass 20, count 0 2006.162.07:31:13.62#ibcon#read 5, iclass 20, count 0 2006.162.07:31:13.62#ibcon#about to read 6, iclass 20, count 0 2006.162.07:31:13.62#ibcon#read 6, iclass 20, count 0 2006.162.07:31:13.62#ibcon#end of sib2, iclass 20, count 0 2006.162.07:31:13.62#ibcon#*after write, iclass 20, count 0 2006.162.07:31:13.62#ibcon#*before return 0, iclass 20, count 0 2006.162.07:31:13.62#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:31:13.62#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:31:13.62#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.07:31:13.62#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.07:31:13.62$vc4f8/vbbw=wide 2006.162.07:31:13.62#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.162.07:31:13.62#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.162.07:31:13.62#ibcon#ireg 8 cls_cnt 0 2006.162.07:31:13.62#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:31:13.69#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:31:13.69#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:31:13.69#ibcon#enter wrdev, iclass 22, count 0 2006.162.07:31:13.69#ibcon#first serial, iclass 22, count 0 2006.162.07:31:13.69#ibcon#enter sib2, iclass 22, count 0 2006.162.07:31:13.69#ibcon#flushed, iclass 22, count 0 2006.162.07:31:13.69#ibcon#about to write, iclass 22, count 0 2006.162.07:31:13.69#ibcon#wrote, iclass 22, count 0 2006.162.07:31:13.69#ibcon#about to read 3, iclass 22, count 0 2006.162.07:31:13.71#ibcon#read 3, iclass 22, count 0 2006.162.07:31:13.71#ibcon#about to read 4, iclass 22, count 0 2006.162.07:31:13.71#ibcon#read 4, iclass 22, count 0 2006.162.07:31:13.71#ibcon#about to read 5, iclass 22, count 0 2006.162.07:31:13.71#ibcon#read 5, iclass 22, count 0 2006.162.07:31:13.71#ibcon#about to read 6, iclass 22, count 0 2006.162.07:31:13.71#ibcon#read 6, iclass 22, count 0 2006.162.07:31:13.71#ibcon#end of sib2, iclass 22, count 0 2006.162.07:31:13.71#ibcon#*mode == 0, iclass 22, count 0 2006.162.07:31:13.71#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.07:31:13.71#ibcon#[27=BW32\r\n] 2006.162.07:31:13.71#ibcon#*before write, iclass 22, count 0 2006.162.07:31:13.71#ibcon#enter sib2, iclass 22, count 0 2006.162.07:31:13.71#ibcon#flushed, iclass 22, count 0 2006.162.07:31:13.71#ibcon#about to write, iclass 22, count 0 2006.162.07:31:13.71#ibcon#wrote, iclass 22, count 0 2006.162.07:31:13.71#ibcon#about to read 3, iclass 22, count 0 2006.162.07:31:13.74#ibcon#read 3, iclass 22, count 0 2006.162.07:31:13.74#ibcon#about to read 4, iclass 22, count 0 2006.162.07:31:13.74#ibcon#read 4, iclass 22, count 0 2006.162.07:31:13.74#ibcon#about to read 5, iclass 22, count 0 2006.162.07:31:13.74#ibcon#read 5, iclass 22, count 0 2006.162.07:31:13.74#ibcon#about to read 6, iclass 22, count 0 2006.162.07:31:13.74#ibcon#read 6, iclass 22, count 0 2006.162.07:31:13.74#ibcon#end of sib2, iclass 22, count 0 2006.162.07:31:13.74#ibcon#*after write, iclass 22, count 0 2006.162.07:31:13.74#ibcon#*before return 0, iclass 22, count 0 2006.162.07:31:13.74#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:31:13.74#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:31:13.74#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.07:31:13.74#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.07:31:13.74$4f8m12a/ifd4f 2006.162.07:31:13.74$ifd4f/lo= 2006.162.07:31:13.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.07:31:13.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.07:31:13.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.07:31:13.74$ifd4f/patch= 2006.162.07:31:13.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.07:31:13.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.07:31:13.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.07:31:13.74$4f8m12a/"form=m,16.000,1:2 2006.162.07:31:13.74$4f8m12a/"tpicd 2006.162.07:31:13.74$4f8m12a/echo=off 2006.162.07:31:13.74$4f8m12a/xlog=off 2006.162.07:31:13.74:!2006.162.07:33:20 2006.162.07:31:49.14#trakl#Source acquired 2006.162.07:31:49.14#flagr#flagr/antenna,acquired 2006.162.07:33:20.00:preob 2006.162.07:33:20.13/onsource/TRACKING 2006.162.07:33:20.13:!2006.162.07:33:30 2006.162.07:33:30.00:data_valid=on 2006.162.07:33:30.00:midob 2006.162.07:33:31.13/onsource/TRACKING 2006.162.07:33:31.13/wx/17.90,1007.1,100 2006.162.07:33:31.28/cable/+6.5372E-03 2006.162.07:33:32.37/va/01,08,usb,yes,41,43 2006.162.07:33:32.37/va/02,07,usb,yes,41,43 2006.162.07:33:32.37/va/03,06,usb,yes,44,44 2006.162.07:33:32.37/va/04,07,usb,yes,43,45 2006.162.07:33:32.37/va/05,07,usb,yes,45,48 2006.162.07:33:32.37/va/06,06,usb,yes,45,44 2006.162.07:33:32.37/va/07,06,usb,yes,45,45 2006.162.07:33:32.37/va/08,07,usb,yes,43,42 2006.162.07:33:32.60/valo/01,532.99,yes,locked 2006.162.07:33:32.60/valo/02,572.99,yes,locked 2006.162.07:33:32.60/valo/03,672.99,yes,locked 2006.162.07:33:32.60/valo/04,832.99,yes,locked 2006.162.07:33:32.60/valo/05,652.99,yes,locked 2006.162.07:33:32.60/valo/06,772.99,yes,locked 2006.162.07:33:32.60/valo/07,832.99,yes,locked 2006.162.07:33:32.60/valo/08,852.99,yes,locked 2006.162.07:33:33.69/vb/01,04,usb,yes,29,28 2006.162.07:33:33.69/vb/02,04,usb,yes,31,33 2006.162.07:33:33.69/vb/03,04,usb,yes,27,31 2006.162.07:33:33.69/vb/04,04,usb,yes,28,29 2006.162.07:33:33.69/vb/05,04,usb,yes,27,31 2006.162.07:33:33.69/vb/06,04,usb,yes,28,31 2006.162.07:33:33.69/vb/07,04,usb,yes,30,30 2006.162.07:33:33.69/vb/08,04,usb,yes,28,31 2006.162.07:33:33.92/vblo/01,632.99,yes,locked 2006.162.07:33:33.92/vblo/02,640.99,yes,locked 2006.162.07:33:33.92/vblo/03,656.99,yes,locked 2006.162.07:33:33.92/vblo/04,712.99,yes,locked 2006.162.07:33:33.92/vblo/05,744.99,yes,locked 2006.162.07:33:33.92/vblo/06,752.99,yes,locked 2006.162.07:33:33.92/vblo/07,734.99,yes,locked 2006.162.07:33:33.92/vblo/08,744.99,yes,locked 2006.162.07:33:34.07/vabw/8 2006.162.07:33:34.22/vbbw/8 2006.162.07:33:34.31/xfe/off,on,14.7 2006.162.07:33:34.69/ifatt/23,28,28,28 2006.162.07:33:35.07/fmout-gps/S +4.50E-07 2006.162.07:33:35.11:!2006.162.07:34:30 2006.162.07:34:30.00:data_valid=off 2006.162.07:34:30.00:postob 2006.162.07:34:30.17/cable/+6.5360E-03 2006.162.07:34:30.17/wx/17.89,1007.1,100 2006.162.07:34:31.07/fmout-gps/S +4.49E-07 2006.162.07:34:31.07:scan_name=162-0735,k06162,100 2006.162.07:34:31.08:source=0458-020,050112.81,-015914.3,2000.0,ccw 2006.162.07:34:31.15#flagr#flagr/antenna,new-source 2006.162.07:34:32.13:checkk5 2006.162.07:34:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.162.07:34:32.92/chk_autoobs//k5ts2/ autoobs is running! 2006.162.07:34:33.34/chk_autoobs//k5ts3/ autoobs is running! 2006.162.07:34:33.77/chk_autoobs//k5ts4/ autoobs is running! 2006.162.07:34:34.31/chk_obsdata//k5ts1/T1620733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:34:34.71/chk_obsdata//k5ts2/T1620733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:34:35.10/chk_obsdata//k5ts3/T1620733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:34:35.51/chk_obsdata//k5ts4/T1620733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:34:37.20/k5log//k5ts1_log_newline 2006.162.07:34:38.02/k5log//k5ts2_log_newline 2006.162.07:34:38.83/k5log//k5ts3_log_newline 2006.162.07:34:39.62/k5log//k5ts4_log_newline 2006.162.07:34:39.65/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.07:34:39.65:4f8m12a=1 2006.162.07:34:39.65$4f8m12a/echo=on 2006.162.07:34:39.65$4f8m12a/pcalon 2006.162.07:34:39.65$pcalon/"no phase cal control is implemented here 2006.162.07:34:39.65$4f8m12a/"tpicd=stop 2006.162.07:34:39.65$4f8m12a/vc4f8 2006.162.07:34:39.65$vc4f8/valo=1,532.99 2006.162.07:34:39.65#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.162.07:34:39.65#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.162.07:34:39.65#ibcon#ireg 17 cls_cnt 0 2006.162.07:34:39.65#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.162.07:34:39.65#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.162.07:34:39.65#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.162.07:34:39.65#ibcon#enter wrdev, iclass 33, count 0 2006.162.07:34:39.65#ibcon#first serial, iclass 33, count 0 2006.162.07:34:39.65#ibcon#enter sib2, iclass 33, count 0 2006.162.07:34:39.65#ibcon#flushed, iclass 33, count 0 2006.162.07:34:39.65#ibcon#about to write, iclass 33, count 0 2006.162.07:34:39.65#ibcon#wrote, iclass 33, count 0 2006.162.07:34:39.65#ibcon#about to read 3, iclass 33, count 0 2006.162.07:34:39.70#ibcon#read 3, iclass 33, count 0 2006.162.07:34:39.70#ibcon#about to read 4, iclass 33, count 0 2006.162.07:34:39.70#ibcon#read 4, iclass 33, count 0 2006.162.07:34:39.70#ibcon#about to read 5, iclass 33, count 0 2006.162.07:34:39.70#ibcon#read 5, iclass 33, count 0 2006.162.07:34:39.70#ibcon#about to read 6, iclass 33, count 0 2006.162.07:34:39.70#ibcon#read 6, iclass 33, count 0 2006.162.07:34:39.70#ibcon#end of sib2, iclass 33, count 0 2006.162.07:34:39.70#ibcon#*mode == 0, iclass 33, count 0 2006.162.07:34:39.70#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.162.07:34:39.70#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.07:34:39.70#ibcon#*before write, iclass 33, count 0 2006.162.07:34:39.70#ibcon#enter sib2, iclass 33, count 0 2006.162.07:34:39.70#ibcon#flushed, iclass 33, count 0 2006.162.07:34:39.70#ibcon#about to write, iclass 33, count 0 2006.162.07:34:39.70#ibcon#wrote, iclass 33, count 0 2006.162.07:34:39.70#ibcon#about to read 3, iclass 33, count 0 2006.162.07:34:39.74#ibcon#read 3, iclass 33, count 0 2006.162.07:34:39.74#ibcon#about to read 4, iclass 33, count 0 2006.162.07:34:39.74#ibcon#read 4, iclass 33, count 0 2006.162.07:34:39.74#ibcon#about to read 5, iclass 33, count 0 2006.162.07:34:39.74#ibcon#read 5, iclass 33, count 0 2006.162.07:34:39.74#ibcon#about to read 6, iclass 33, count 0 2006.162.07:34:39.74#ibcon#read 6, iclass 33, count 0 2006.162.07:34:39.74#ibcon#end of sib2, iclass 33, count 0 2006.162.07:34:39.74#ibcon#*after write, iclass 33, count 0 2006.162.07:34:39.74#ibcon#*before return 0, iclass 33, count 0 2006.162.07:34:39.74#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.162.07:34:39.74#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.162.07:34:39.74#ibcon#about to clear, iclass 33 cls_cnt 0 2006.162.07:34:39.74#ibcon#cleared, iclass 33 cls_cnt 0 2006.162.07:34:39.74$vc4f8/va=1,8 2006.162.07:34:39.74#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.162.07:34:39.74#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.162.07:34:39.74#ibcon#ireg 11 cls_cnt 2 2006.162.07:34:39.74#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.162.07:34:39.74#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.162.07:34:39.74#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.162.07:34:39.74#ibcon#enter wrdev, iclass 35, count 2 2006.162.07:34:39.74#ibcon#first serial, iclass 35, count 2 2006.162.07:34:39.74#ibcon#enter sib2, iclass 35, count 2 2006.162.07:34:39.74#ibcon#flushed, iclass 35, count 2 2006.162.07:34:39.74#ibcon#about to write, iclass 35, count 2 2006.162.07:34:39.74#ibcon#wrote, iclass 35, count 2 2006.162.07:34:39.74#ibcon#about to read 3, iclass 35, count 2 2006.162.07:34:39.76#ibcon#read 3, iclass 35, count 2 2006.162.07:34:39.76#ibcon#about to read 4, iclass 35, count 2 2006.162.07:34:39.76#ibcon#read 4, iclass 35, count 2 2006.162.07:34:39.76#ibcon#about to read 5, iclass 35, count 2 2006.162.07:34:39.76#ibcon#read 5, iclass 35, count 2 2006.162.07:34:39.76#ibcon#about to read 6, iclass 35, count 2 2006.162.07:34:39.76#ibcon#read 6, iclass 35, count 2 2006.162.07:34:39.76#ibcon#end of sib2, iclass 35, count 2 2006.162.07:34:39.76#ibcon#*mode == 0, iclass 35, count 2 2006.162.07:34:39.76#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.162.07:34:39.76#ibcon#[25=AT01-08\r\n] 2006.162.07:34:39.76#ibcon#*before write, iclass 35, count 2 2006.162.07:34:39.76#ibcon#enter sib2, iclass 35, count 2 2006.162.07:34:39.76#ibcon#flushed, iclass 35, count 2 2006.162.07:34:39.76#ibcon#about to write, iclass 35, count 2 2006.162.07:34:39.76#ibcon#wrote, iclass 35, count 2 2006.162.07:34:39.76#ibcon#about to read 3, iclass 35, count 2 2006.162.07:34:39.79#ibcon#read 3, iclass 35, count 2 2006.162.07:34:39.79#ibcon#about to read 4, iclass 35, count 2 2006.162.07:34:39.79#ibcon#read 4, iclass 35, count 2 2006.162.07:34:39.79#ibcon#about to read 5, iclass 35, count 2 2006.162.07:34:39.79#ibcon#read 5, iclass 35, count 2 2006.162.07:34:39.79#ibcon#about to read 6, iclass 35, count 2 2006.162.07:34:39.79#ibcon#read 6, iclass 35, count 2 2006.162.07:34:39.79#ibcon#end of sib2, iclass 35, count 2 2006.162.07:34:39.79#ibcon#*after write, iclass 35, count 2 2006.162.07:34:39.79#ibcon#*before return 0, iclass 35, count 2 2006.162.07:34:39.79#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.162.07:34:39.79#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.162.07:34:39.79#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.162.07:34:39.79#ibcon#ireg 7 cls_cnt 0 2006.162.07:34:39.79#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.162.07:34:39.91#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.162.07:34:39.91#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.162.07:34:39.91#ibcon#enter wrdev, iclass 35, count 0 2006.162.07:34:39.91#ibcon#first serial, iclass 35, count 0 2006.162.07:34:39.91#ibcon#enter sib2, iclass 35, count 0 2006.162.07:34:39.91#ibcon#flushed, iclass 35, count 0 2006.162.07:34:39.91#ibcon#about to write, iclass 35, count 0 2006.162.07:34:39.91#ibcon#wrote, iclass 35, count 0 2006.162.07:34:39.91#ibcon#about to read 3, iclass 35, count 0 2006.162.07:34:39.93#ibcon#read 3, iclass 35, count 0 2006.162.07:34:39.93#ibcon#about to read 4, iclass 35, count 0 2006.162.07:34:39.93#ibcon#read 4, iclass 35, count 0 2006.162.07:34:39.93#ibcon#about to read 5, iclass 35, count 0 2006.162.07:34:39.93#ibcon#read 5, iclass 35, count 0 2006.162.07:34:39.93#ibcon#about to read 6, iclass 35, count 0 2006.162.07:34:39.93#ibcon#read 6, iclass 35, count 0 2006.162.07:34:39.93#ibcon#end of sib2, iclass 35, count 0 2006.162.07:34:39.93#ibcon#*mode == 0, iclass 35, count 0 2006.162.07:34:39.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.162.07:34:39.93#ibcon#[25=USB\r\n] 2006.162.07:34:39.93#ibcon#*before write, iclass 35, count 0 2006.162.07:34:39.93#ibcon#enter sib2, iclass 35, count 0 2006.162.07:34:39.93#ibcon#flushed, iclass 35, count 0 2006.162.07:34:39.93#ibcon#about to write, iclass 35, count 0 2006.162.07:34:39.93#ibcon#wrote, iclass 35, count 0 2006.162.07:34:39.93#ibcon#about to read 3, iclass 35, count 0 2006.162.07:34:39.96#ibcon#read 3, iclass 35, count 0 2006.162.07:34:39.96#ibcon#about to read 4, iclass 35, count 0 2006.162.07:34:39.96#ibcon#read 4, iclass 35, count 0 2006.162.07:34:39.96#ibcon#about to read 5, iclass 35, count 0 2006.162.07:34:39.96#ibcon#read 5, iclass 35, count 0 2006.162.07:34:39.96#ibcon#about to read 6, iclass 35, count 0 2006.162.07:34:39.96#ibcon#read 6, iclass 35, count 0 2006.162.07:34:39.96#ibcon#end of sib2, iclass 35, count 0 2006.162.07:34:39.96#ibcon#*after write, iclass 35, count 0 2006.162.07:34:39.96#ibcon#*before return 0, iclass 35, count 0 2006.162.07:34:39.96#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.162.07:34:39.96#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.162.07:34:39.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.162.07:34:39.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.162.07:34:39.96$vc4f8/valo=2,572.99 2006.162.07:34:39.96#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.162.07:34:39.96#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.162.07:34:39.96#ibcon#ireg 17 cls_cnt 0 2006.162.07:34:39.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.162.07:34:39.96#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.162.07:34:39.96#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.162.07:34:39.96#ibcon#enter wrdev, iclass 37, count 0 2006.162.07:34:39.96#ibcon#first serial, iclass 37, count 0 2006.162.07:34:39.96#ibcon#enter sib2, iclass 37, count 0 2006.162.07:34:39.96#ibcon#flushed, iclass 37, count 0 2006.162.07:34:39.96#ibcon#about to write, iclass 37, count 0 2006.162.07:34:39.96#ibcon#wrote, iclass 37, count 0 2006.162.07:34:39.96#ibcon#about to read 3, iclass 37, count 0 2006.162.07:34:39.98#ibcon#read 3, iclass 37, count 0 2006.162.07:34:39.98#ibcon#about to read 4, iclass 37, count 0 2006.162.07:34:39.98#ibcon#read 4, iclass 37, count 0 2006.162.07:34:39.98#ibcon#about to read 5, iclass 37, count 0 2006.162.07:34:39.98#ibcon#read 5, iclass 37, count 0 2006.162.07:34:39.98#ibcon#about to read 6, iclass 37, count 0 2006.162.07:34:39.98#ibcon#read 6, iclass 37, count 0 2006.162.07:34:39.98#ibcon#end of sib2, iclass 37, count 0 2006.162.07:34:39.98#ibcon#*mode == 0, iclass 37, count 0 2006.162.07:34:39.98#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.162.07:34:39.98#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.07:34:39.98#ibcon#*before write, iclass 37, count 0 2006.162.07:34:39.98#ibcon#enter sib2, iclass 37, count 0 2006.162.07:34:39.98#ibcon#flushed, iclass 37, count 0 2006.162.07:34:39.98#ibcon#about to write, iclass 37, count 0 2006.162.07:34:39.98#ibcon#wrote, iclass 37, count 0 2006.162.07:34:39.98#ibcon#about to read 3, iclass 37, count 0 2006.162.07:34:40.02#ibcon#read 3, iclass 37, count 0 2006.162.07:34:40.02#ibcon#about to read 4, iclass 37, count 0 2006.162.07:34:40.02#ibcon#read 4, iclass 37, count 0 2006.162.07:34:40.02#ibcon#about to read 5, iclass 37, count 0 2006.162.07:34:40.02#ibcon#read 5, iclass 37, count 0 2006.162.07:34:40.02#ibcon#about to read 6, iclass 37, count 0 2006.162.07:34:40.02#ibcon#read 6, iclass 37, count 0 2006.162.07:34:40.02#ibcon#end of sib2, iclass 37, count 0 2006.162.07:34:40.02#ibcon#*after write, iclass 37, count 0 2006.162.07:34:40.02#ibcon#*before return 0, iclass 37, count 0 2006.162.07:34:40.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.162.07:34:40.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.162.07:34:40.02#ibcon#about to clear, iclass 37 cls_cnt 0 2006.162.07:34:40.02#ibcon#cleared, iclass 37 cls_cnt 0 2006.162.07:34:40.02$vc4f8/va=2,7 2006.162.07:34:40.02#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.162.07:34:40.02#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.162.07:34:40.02#ibcon#ireg 11 cls_cnt 2 2006.162.07:34:40.02#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.162.07:34:40.08#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.162.07:34:40.08#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.162.07:34:40.08#ibcon#enter wrdev, iclass 39, count 2 2006.162.07:34:40.08#ibcon#first serial, iclass 39, count 2 2006.162.07:34:40.08#ibcon#enter sib2, iclass 39, count 2 2006.162.07:34:40.08#ibcon#flushed, iclass 39, count 2 2006.162.07:34:40.08#ibcon#about to write, iclass 39, count 2 2006.162.07:34:40.08#ibcon#wrote, iclass 39, count 2 2006.162.07:34:40.08#ibcon#about to read 3, iclass 39, count 2 2006.162.07:34:40.10#ibcon#read 3, iclass 39, count 2 2006.162.07:34:40.10#ibcon#about to read 4, iclass 39, count 2 2006.162.07:34:40.10#ibcon#read 4, iclass 39, count 2 2006.162.07:34:40.10#ibcon#about to read 5, iclass 39, count 2 2006.162.07:34:40.10#ibcon#read 5, iclass 39, count 2 2006.162.07:34:40.10#ibcon#about to read 6, iclass 39, count 2 2006.162.07:34:40.10#ibcon#read 6, iclass 39, count 2 2006.162.07:34:40.10#ibcon#end of sib2, iclass 39, count 2 2006.162.07:34:40.10#ibcon#*mode == 0, iclass 39, count 2 2006.162.07:34:40.10#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.162.07:34:40.10#ibcon#[25=AT02-07\r\n] 2006.162.07:34:40.10#ibcon#*before write, iclass 39, count 2 2006.162.07:34:40.10#ibcon#enter sib2, iclass 39, count 2 2006.162.07:34:40.10#ibcon#flushed, iclass 39, count 2 2006.162.07:34:40.10#ibcon#about to write, iclass 39, count 2 2006.162.07:34:40.10#ibcon#wrote, iclass 39, count 2 2006.162.07:34:40.10#ibcon#about to read 3, iclass 39, count 2 2006.162.07:34:40.13#ibcon#read 3, iclass 39, count 2 2006.162.07:34:40.13#ibcon#about to read 4, iclass 39, count 2 2006.162.07:34:40.13#ibcon#read 4, iclass 39, count 2 2006.162.07:34:40.13#ibcon#about to read 5, iclass 39, count 2 2006.162.07:34:40.13#ibcon#read 5, iclass 39, count 2 2006.162.07:34:40.13#ibcon#about to read 6, iclass 39, count 2 2006.162.07:34:40.13#ibcon#read 6, iclass 39, count 2 2006.162.07:34:40.13#ibcon#end of sib2, iclass 39, count 2 2006.162.07:34:40.13#ibcon#*after write, iclass 39, count 2 2006.162.07:34:40.13#ibcon#*before return 0, iclass 39, count 2 2006.162.07:34:40.13#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.162.07:34:40.13#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.162.07:34:40.13#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.162.07:34:40.13#ibcon#ireg 7 cls_cnt 0 2006.162.07:34:40.13#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.162.07:34:40.25#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.162.07:34:40.25#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.162.07:34:40.25#ibcon#enter wrdev, iclass 39, count 0 2006.162.07:34:40.25#ibcon#first serial, iclass 39, count 0 2006.162.07:34:40.25#ibcon#enter sib2, iclass 39, count 0 2006.162.07:34:40.25#ibcon#flushed, iclass 39, count 0 2006.162.07:34:40.25#ibcon#about to write, iclass 39, count 0 2006.162.07:34:40.25#ibcon#wrote, iclass 39, count 0 2006.162.07:34:40.25#ibcon#about to read 3, iclass 39, count 0 2006.162.07:34:40.27#ibcon#read 3, iclass 39, count 0 2006.162.07:34:40.27#ibcon#about to read 4, iclass 39, count 0 2006.162.07:34:40.27#ibcon#read 4, iclass 39, count 0 2006.162.07:34:40.27#ibcon#about to read 5, iclass 39, count 0 2006.162.07:34:40.27#ibcon#read 5, iclass 39, count 0 2006.162.07:34:40.27#ibcon#about to read 6, iclass 39, count 0 2006.162.07:34:40.27#ibcon#read 6, iclass 39, count 0 2006.162.07:34:40.27#ibcon#end of sib2, iclass 39, count 0 2006.162.07:34:40.27#ibcon#*mode == 0, iclass 39, count 0 2006.162.07:34:40.27#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.162.07:34:40.27#ibcon#[25=USB\r\n] 2006.162.07:34:40.27#ibcon#*before write, iclass 39, count 0 2006.162.07:34:40.27#ibcon#enter sib2, iclass 39, count 0 2006.162.07:34:40.27#ibcon#flushed, iclass 39, count 0 2006.162.07:34:40.27#ibcon#about to write, iclass 39, count 0 2006.162.07:34:40.27#ibcon#wrote, iclass 39, count 0 2006.162.07:34:40.27#ibcon#about to read 3, iclass 39, count 0 2006.162.07:34:40.30#ibcon#read 3, iclass 39, count 0 2006.162.07:34:40.30#ibcon#about to read 4, iclass 39, count 0 2006.162.07:34:40.30#ibcon#read 4, iclass 39, count 0 2006.162.07:34:40.30#ibcon#about to read 5, iclass 39, count 0 2006.162.07:34:40.30#ibcon#read 5, iclass 39, count 0 2006.162.07:34:40.30#ibcon#about to read 6, iclass 39, count 0 2006.162.07:34:40.30#ibcon#read 6, iclass 39, count 0 2006.162.07:34:40.30#ibcon#end of sib2, iclass 39, count 0 2006.162.07:34:40.30#ibcon#*after write, iclass 39, count 0 2006.162.07:34:40.30#ibcon#*before return 0, iclass 39, count 0 2006.162.07:34:40.30#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.162.07:34:40.30#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.162.07:34:40.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.162.07:34:40.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.162.07:34:40.30$vc4f8/valo=3,672.99 2006.162.07:34:40.30#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.162.07:34:40.30#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.162.07:34:40.30#ibcon#ireg 17 cls_cnt 0 2006.162.07:34:40.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.162.07:34:40.30#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.162.07:34:40.30#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.162.07:34:40.30#ibcon#enter wrdev, iclass 3, count 0 2006.162.07:34:40.30#ibcon#first serial, iclass 3, count 0 2006.162.07:34:40.30#ibcon#enter sib2, iclass 3, count 0 2006.162.07:34:40.30#ibcon#flushed, iclass 3, count 0 2006.162.07:34:40.30#ibcon#about to write, iclass 3, count 0 2006.162.07:34:40.30#ibcon#wrote, iclass 3, count 0 2006.162.07:34:40.30#ibcon#about to read 3, iclass 3, count 0 2006.162.07:34:40.32#ibcon#read 3, iclass 3, count 0 2006.162.07:34:40.32#ibcon#about to read 4, iclass 3, count 0 2006.162.07:34:40.32#ibcon#read 4, iclass 3, count 0 2006.162.07:34:40.32#ibcon#about to read 5, iclass 3, count 0 2006.162.07:34:40.32#ibcon#read 5, iclass 3, count 0 2006.162.07:34:40.32#ibcon#about to read 6, iclass 3, count 0 2006.162.07:34:40.32#ibcon#read 6, iclass 3, count 0 2006.162.07:34:40.32#ibcon#end of sib2, iclass 3, count 0 2006.162.07:34:40.32#ibcon#*mode == 0, iclass 3, count 0 2006.162.07:34:40.32#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.162.07:34:40.32#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.07:34:40.32#ibcon#*before write, iclass 3, count 0 2006.162.07:34:40.32#ibcon#enter sib2, iclass 3, count 0 2006.162.07:34:40.32#ibcon#flushed, iclass 3, count 0 2006.162.07:34:40.32#ibcon#about to write, iclass 3, count 0 2006.162.07:34:40.32#ibcon#wrote, iclass 3, count 0 2006.162.07:34:40.32#ibcon#about to read 3, iclass 3, count 0 2006.162.07:34:40.36#ibcon#read 3, iclass 3, count 0 2006.162.07:34:40.36#ibcon#about to read 4, iclass 3, count 0 2006.162.07:34:40.36#ibcon#read 4, iclass 3, count 0 2006.162.07:34:40.36#ibcon#about to read 5, iclass 3, count 0 2006.162.07:34:40.36#ibcon#read 5, iclass 3, count 0 2006.162.07:34:40.36#ibcon#about to read 6, iclass 3, count 0 2006.162.07:34:40.36#ibcon#read 6, iclass 3, count 0 2006.162.07:34:40.36#ibcon#end of sib2, iclass 3, count 0 2006.162.07:34:40.36#ibcon#*after write, iclass 3, count 0 2006.162.07:34:40.36#ibcon#*before return 0, iclass 3, count 0 2006.162.07:34:40.36#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.162.07:34:40.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.162.07:34:40.36#ibcon#about to clear, iclass 3 cls_cnt 0 2006.162.07:34:40.36#ibcon#cleared, iclass 3 cls_cnt 0 2006.162.07:34:40.36$vc4f8/va=3,6 2006.162.07:34:40.36#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.162.07:34:40.36#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.162.07:34:40.36#ibcon#ireg 11 cls_cnt 2 2006.162.07:34:40.36#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.162.07:34:40.42#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.162.07:34:40.42#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.162.07:34:40.42#ibcon#enter wrdev, iclass 5, count 2 2006.162.07:34:40.42#ibcon#first serial, iclass 5, count 2 2006.162.07:34:40.42#ibcon#enter sib2, iclass 5, count 2 2006.162.07:34:40.42#ibcon#flushed, iclass 5, count 2 2006.162.07:34:40.42#ibcon#about to write, iclass 5, count 2 2006.162.07:34:40.42#ibcon#wrote, iclass 5, count 2 2006.162.07:34:40.42#ibcon#about to read 3, iclass 5, count 2 2006.162.07:34:40.45#ibcon#read 3, iclass 5, count 2 2006.162.07:34:40.45#ibcon#about to read 4, iclass 5, count 2 2006.162.07:34:40.45#ibcon#read 4, iclass 5, count 2 2006.162.07:34:40.45#ibcon#about to read 5, iclass 5, count 2 2006.162.07:34:40.45#ibcon#read 5, iclass 5, count 2 2006.162.07:34:40.45#ibcon#about to read 6, iclass 5, count 2 2006.162.07:34:40.45#ibcon#read 6, iclass 5, count 2 2006.162.07:34:40.45#ibcon#end of sib2, iclass 5, count 2 2006.162.07:34:40.45#ibcon#*mode == 0, iclass 5, count 2 2006.162.07:34:40.45#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.162.07:34:40.45#ibcon#[25=AT03-06\r\n] 2006.162.07:34:40.45#ibcon#*before write, iclass 5, count 2 2006.162.07:34:40.45#ibcon#enter sib2, iclass 5, count 2 2006.162.07:34:40.45#ibcon#flushed, iclass 5, count 2 2006.162.07:34:40.45#ibcon#about to write, iclass 5, count 2 2006.162.07:34:40.45#ibcon#wrote, iclass 5, count 2 2006.162.07:34:40.45#ibcon#about to read 3, iclass 5, count 2 2006.162.07:34:40.48#ibcon#read 3, iclass 5, count 2 2006.162.07:34:40.48#ibcon#about to read 4, iclass 5, count 2 2006.162.07:34:40.48#ibcon#read 4, iclass 5, count 2 2006.162.07:34:40.48#ibcon#about to read 5, iclass 5, count 2 2006.162.07:34:40.48#ibcon#read 5, iclass 5, count 2 2006.162.07:34:40.48#ibcon#about to read 6, iclass 5, count 2 2006.162.07:34:40.48#ibcon#read 6, iclass 5, count 2 2006.162.07:34:40.48#ibcon#end of sib2, iclass 5, count 2 2006.162.07:34:40.48#ibcon#*after write, iclass 5, count 2 2006.162.07:34:40.48#ibcon#*before return 0, iclass 5, count 2 2006.162.07:34:40.48#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.162.07:34:40.48#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.162.07:34:40.48#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.162.07:34:40.48#ibcon#ireg 7 cls_cnt 0 2006.162.07:34:40.48#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.162.07:34:40.60#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.162.07:34:40.60#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.162.07:34:40.60#ibcon#enter wrdev, iclass 5, count 0 2006.162.07:34:40.60#ibcon#first serial, iclass 5, count 0 2006.162.07:34:40.60#ibcon#enter sib2, iclass 5, count 0 2006.162.07:34:40.60#ibcon#flushed, iclass 5, count 0 2006.162.07:34:40.60#ibcon#about to write, iclass 5, count 0 2006.162.07:34:40.60#ibcon#wrote, iclass 5, count 0 2006.162.07:34:40.60#ibcon#about to read 3, iclass 5, count 0 2006.162.07:34:40.62#ibcon#read 3, iclass 5, count 0 2006.162.07:34:40.62#ibcon#about to read 4, iclass 5, count 0 2006.162.07:34:40.62#ibcon#read 4, iclass 5, count 0 2006.162.07:34:40.62#ibcon#about to read 5, iclass 5, count 0 2006.162.07:34:40.62#ibcon#read 5, iclass 5, count 0 2006.162.07:34:40.62#ibcon#about to read 6, iclass 5, count 0 2006.162.07:34:40.62#ibcon#read 6, iclass 5, count 0 2006.162.07:34:40.62#ibcon#end of sib2, iclass 5, count 0 2006.162.07:34:40.62#ibcon#*mode == 0, iclass 5, count 0 2006.162.07:34:40.62#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.162.07:34:40.62#ibcon#[25=USB\r\n] 2006.162.07:34:40.62#ibcon#*before write, iclass 5, count 0 2006.162.07:34:40.62#ibcon#enter sib2, iclass 5, count 0 2006.162.07:34:40.62#ibcon#flushed, iclass 5, count 0 2006.162.07:34:40.62#ibcon#about to write, iclass 5, count 0 2006.162.07:34:40.62#ibcon#wrote, iclass 5, count 0 2006.162.07:34:40.62#ibcon#about to read 3, iclass 5, count 0 2006.162.07:34:40.65#ibcon#read 3, iclass 5, count 0 2006.162.07:34:40.65#ibcon#about to read 4, iclass 5, count 0 2006.162.07:34:40.65#ibcon#read 4, iclass 5, count 0 2006.162.07:34:40.65#ibcon#about to read 5, iclass 5, count 0 2006.162.07:34:40.65#ibcon#read 5, iclass 5, count 0 2006.162.07:34:40.65#ibcon#about to read 6, iclass 5, count 0 2006.162.07:34:40.65#ibcon#read 6, iclass 5, count 0 2006.162.07:34:40.65#ibcon#end of sib2, iclass 5, count 0 2006.162.07:34:40.65#ibcon#*after write, iclass 5, count 0 2006.162.07:34:40.65#ibcon#*before return 0, iclass 5, count 0 2006.162.07:34:40.65#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.162.07:34:40.65#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.162.07:34:40.65#ibcon#about to clear, iclass 5 cls_cnt 0 2006.162.07:34:40.65#ibcon#cleared, iclass 5 cls_cnt 0 2006.162.07:34:40.65$vc4f8/valo=4,832.99 2006.162.07:34:40.65#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.162.07:34:40.65#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.162.07:34:40.65#ibcon#ireg 17 cls_cnt 0 2006.162.07:34:40.65#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:34:40.65#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:34:40.65#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:34:40.65#ibcon#enter wrdev, iclass 7, count 0 2006.162.07:34:40.65#ibcon#first serial, iclass 7, count 0 2006.162.07:34:40.65#ibcon#enter sib2, iclass 7, count 0 2006.162.07:34:40.65#ibcon#flushed, iclass 7, count 0 2006.162.07:34:40.65#ibcon#about to write, iclass 7, count 0 2006.162.07:34:40.65#ibcon#wrote, iclass 7, count 0 2006.162.07:34:40.65#ibcon#about to read 3, iclass 7, count 0 2006.162.07:34:40.67#ibcon#read 3, iclass 7, count 0 2006.162.07:34:40.67#ibcon#about to read 4, iclass 7, count 0 2006.162.07:34:40.67#ibcon#read 4, iclass 7, count 0 2006.162.07:34:40.67#ibcon#about to read 5, iclass 7, count 0 2006.162.07:34:40.67#ibcon#read 5, iclass 7, count 0 2006.162.07:34:40.67#ibcon#about to read 6, iclass 7, count 0 2006.162.07:34:40.67#ibcon#read 6, iclass 7, count 0 2006.162.07:34:40.67#ibcon#end of sib2, iclass 7, count 0 2006.162.07:34:40.67#ibcon#*mode == 0, iclass 7, count 0 2006.162.07:34:40.67#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.162.07:34:40.67#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.07:34:40.67#ibcon#*before write, iclass 7, count 0 2006.162.07:34:40.67#ibcon#enter sib2, iclass 7, count 0 2006.162.07:34:40.67#ibcon#flushed, iclass 7, count 0 2006.162.07:34:40.67#ibcon#about to write, iclass 7, count 0 2006.162.07:34:40.67#ibcon#wrote, iclass 7, count 0 2006.162.07:34:40.67#ibcon#about to read 3, iclass 7, count 0 2006.162.07:34:40.71#ibcon#read 3, iclass 7, count 0 2006.162.07:34:40.71#ibcon#about to read 4, iclass 7, count 0 2006.162.07:34:40.71#ibcon#read 4, iclass 7, count 0 2006.162.07:34:40.71#ibcon#about to read 5, iclass 7, count 0 2006.162.07:34:40.71#ibcon#read 5, iclass 7, count 0 2006.162.07:34:40.71#ibcon#about to read 6, iclass 7, count 0 2006.162.07:34:40.71#ibcon#read 6, iclass 7, count 0 2006.162.07:34:40.71#ibcon#end of sib2, iclass 7, count 0 2006.162.07:34:40.71#ibcon#*after write, iclass 7, count 0 2006.162.07:34:40.71#ibcon#*before return 0, iclass 7, count 0 2006.162.07:34:40.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:34:40.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:34:40.71#ibcon#about to clear, iclass 7 cls_cnt 0 2006.162.07:34:40.71#ibcon#cleared, iclass 7 cls_cnt 0 2006.162.07:34:40.71$vc4f8/va=4,7 2006.162.07:34:40.71#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.162.07:34:40.71#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.162.07:34:40.71#ibcon#ireg 11 cls_cnt 2 2006.162.07:34:40.71#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:34:40.77#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:34:40.77#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:34:40.77#ibcon#enter wrdev, iclass 11, count 2 2006.162.07:34:40.77#ibcon#first serial, iclass 11, count 2 2006.162.07:34:40.77#ibcon#enter sib2, iclass 11, count 2 2006.162.07:34:40.77#ibcon#flushed, iclass 11, count 2 2006.162.07:34:40.77#ibcon#about to write, iclass 11, count 2 2006.162.07:34:40.77#ibcon#wrote, iclass 11, count 2 2006.162.07:34:40.77#ibcon#about to read 3, iclass 11, count 2 2006.162.07:34:40.79#ibcon#read 3, iclass 11, count 2 2006.162.07:34:40.79#ibcon#about to read 4, iclass 11, count 2 2006.162.07:34:40.79#ibcon#read 4, iclass 11, count 2 2006.162.07:34:40.79#ibcon#about to read 5, iclass 11, count 2 2006.162.07:34:40.79#ibcon#read 5, iclass 11, count 2 2006.162.07:34:40.79#ibcon#about to read 6, iclass 11, count 2 2006.162.07:34:40.79#ibcon#read 6, iclass 11, count 2 2006.162.07:34:40.79#ibcon#end of sib2, iclass 11, count 2 2006.162.07:34:40.79#ibcon#*mode == 0, iclass 11, count 2 2006.162.07:34:40.79#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.162.07:34:40.79#ibcon#[25=AT04-07\r\n] 2006.162.07:34:40.79#ibcon#*before write, iclass 11, count 2 2006.162.07:34:40.79#ibcon#enter sib2, iclass 11, count 2 2006.162.07:34:40.79#ibcon#flushed, iclass 11, count 2 2006.162.07:34:40.79#ibcon#about to write, iclass 11, count 2 2006.162.07:34:40.79#ibcon#wrote, iclass 11, count 2 2006.162.07:34:40.79#ibcon#about to read 3, iclass 11, count 2 2006.162.07:34:40.82#ibcon#read 3, iclass 11, count 2 2006.162.07:34:40.82#ibcon#about to read 4, iclass 11, count 2 2006.162.07:34:40.82#ibcon#read 4, iclass 11, count 2 2006.162.07:34:40.82#ibcon#about to read 5, iclass 11, count 2 2006.162.07:34:40.82#ibcon#read 5, iclass 11, count 2 2006.162.07:34:40.82#ibcon#about to read 6, iclass 11, count 2 2006.162.07:34:40.82#ibcon#read 6, iclass 11, count 2 2006.162.07:34:40.82#ibcon#end of sib2, iclass 11, count 2 2006.162.07:34:40.82#ibcon#*after write, iclass 11, count 2 2006.162.07:34:40.82#ibcon#*before return 0, iclass 11, count 2 2006.162.07:34:40.82#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:34:40.82#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:34:40.82#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.162.07:34:40.82#ibcon#ireg 7 cls_cnt 0 2006.162.07:34:40.82#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:34:40.94#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:34:40.94#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:34:40.94#ibcon#enter wrdev, iclass 11, count 0 2006.162.07:34:40.94#ibcon#first serial, iclass 11, count 0 2006.162.07:34:40.94#ibcon#enter sib2, iclass 11, count 0 2006.162.07:34:40.94#ibcon#flushed, iclass 11, count 0 2006.162.07:34:40.94#ibcon#about to write, iclass 11, count 0 2006.162.07:34:40.94#ibcon#wrote, iclass 11, count 0 2006.162.07:34:40.94#ibcon#about to read 3, iclass 11, count 0 2006.162.07:34:40.96#ibcon#read 3, iclass 11, count 0 2006.162.07:34:40.96#ibcon#about to read 4, iclass 11, count 0 2006.162.07:34:40.96#ibcon#read 4, iclass 11, count 0 2006.162.07:34:40.96#ibcon#about to read 5, iclass 11, count 0 2006.162.07:34:40.96#ibcon#read 5, iclass 11, count 0 2006.162.07:34:40.96#ibcon#about to read 6, iclass 11, count 0 2006.162.07:34:40.96#ibcon#read 6, iclass 11, count 0 2006.162.07:34:40.96#ibcon#end of sib2, iclass 11, count 0 2006.162.07:34:40.96#ibcon#*mode == 0, iclass 11, count 0 2006.162.07:34:40.96#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.162.07:34:40.96#ibcon#[25=USB\r\n] 2006.162.07:34:40.96#ibcon#*before write, iclass 11, count 0 2006.162.07:34:40.96#ibcon#enter sib2, iclass 11, count 0 2006.162.07:34:40.96#ibcon#flushed, iclass 11, count 0 2006.162.07:34:40.96#ibcon#about to write, iclass 11, count 0 2006.162.07:34:40.96#ibcon#wrote, iclass 11, count 0 2006.162.07:34:40.96#ibcon#about to read 3, iclass 11, count 0 2006.162.07:34:40.99#ibcon#read 3, iclass 11, count 0 2006.162.07:34:40.99#ibcon#about to read 4, iclass 11, count 0 2006.162.07:34:40.99#ibcon#read 4, iclass 11, count 0 2006.162.07:34:40.99#ibcon#about to read 5, iclass 11, count 0 2006.162.07:34:40.99#ibcon#read 5, iclass 11, count 0 2006.162.07:34:40.99#ibcon#about to read 6, iclass 11, count 0 2006.162.07:34:40.99#ibcon#read 6, iclass 11, count 0 2006.162.07:34:40.99#ibcon#end of sib2, iclass 11, count 0 2006.162.07:34:40.99#ibcon#*after write, iclass 11, count 0 2006.162.07:34:40.99#ibcon#*before return 0, iclass 11, count 0 2006.162.07:34:40.99#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:34:40.99#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:34:40.99#ibcon#about to clear, iclass 11 cls_cnt 0 2006.162.07:34:40.99#ibcon#cleared, iclass 11 cls_cnt 0 2006.162.07:34:40.99$vc4f8/valo=5,652.99 2006.162.07:34:40.99#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.162.07:34:40.99#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.162.07:34:40.99#ibcon#ireg 17 cls_cnt 0 2006.162.07:34:40.99#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:34:40.99#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:34:40.99#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:34:40.99#ibcon#enter wrdev, iclass 13, count 0 2006.162.07:34:40.99#ibcon#first serial, iclass 13, count 0 2006.162.07:34:40.99#ibcon#enter sib2, iclass 13, count 0 2006.162.07:34:40.99#ibcon#flushed, iclass 13, count 0 2006.162.07:34:40.99#ibcon#about to write, iclass 13, count 0 2006.162.07:34:40.99#ibcon#wrote, iclass 13, count 0 2006.162.07:34:40.99#ibcon#about to read 3, iclass 13, count 0 2006.162.07:34:41.01#ibcon#read 3, iclass 13, count 0 2006.162.07:34:41.01#ibcon#about to read 4, iclass 13, count 0 2006.162.07:34:41.01#ibcon#read 4, iclass 13, count 0 2006.162.07:34:41.01#ibcon#about to read 5, iclass 13, count 0 2006.162.07:34:41.01#ibcon#read 5, iclass 13, count 0 2006.162.07:34:41.01#ibcon#about to read 6, iclass 13, count 0 2006.162.07:34:41.01#ibcon#read 6, iclass 13, count 0 2006.162.07:34:41.01#ibcon#end of sib2, iclass 13, count 0 2006.162.07:34:41.01#ibcon#*mode == 0, iclass 13, count 0 2006.162.07:34:41.01#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.162.07:34:41.01#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.07:34:41.01#ibcon#*before write, iclass 13, count 0 2006.162.07:34:41.01#ibcon#enter sib2, iclass 13, count 0 2006.162.07:34:41.01#ibcon#flushed, iclass 13, count 0 2006.162.07:34:41.01#ibcon#about to write, iclass 13, count 0 2006.162.07:34:41.01#ibcon#wrote, iclass 13, count 0 2006.162.07:34:41.01#ibcon#about to read 3, iclass 13, count 0 2006.162.07:34:41.05#ibcon#read 3, iclass 13, count 0 2006.162.07:34:41.05#ibcon#about to read 4, iclass 13, count 0 2006.162.07:34:41.05#ibcon#read 4, iclass 13, count 0 2006.162.07:34:41.05#ibcon#about to read 5, iclass 13, count 0 2006.162.07:34:41.05#ibcon#read 5, iclass 13, count 0 2006.162.07:34:41.05#ibcon#about to read 6, iclass 13, count 0 2006.162.07:34:41.05#ibcon#read 6, iclass 13, count 0 2006.162.07:34:41.05#ibcon#end of sib2, iclass 13, count 0 2006.162.07:34:41.05#ibcon#*after write, iclass 13, count 0 2006.162.07:34:41.05#ibcon#*before return 0, iclass 13, count 0 2006.162.07:34:41.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:34:41.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:34:41.05#ibcon#about to clear, iclass 13 cls_cnt 0 2006.162.07:34:41.05#ibcon#cleared, iclass 13 cls_cnt 0 2006.162.07:34:41.05$vc4f8/va=5,7 2006.162.07:34:41.05#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.162.07:34:41.05#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.162.07:34:41.05#ibcon#ireg 11 cls_cnt 2 2006.162.07:34:41.05#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:34:41.11#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:34:41.11#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:34:41.11#ibcon#enter wrdev, iclass 15, count 2 2006.162.07:34:41.11#ibcon#first serial, iclass 15, count 2 2006.162.07:34:41.11#ibcon#enter sib2, iclass 15, count 2 2006.162.07:34:41.11#ibcon#flushed, iclass 15, count 2 2006.162.07:34:41.11#ibcon#about to write, iclass 15, count 2 2006.162.07:34:41.11#ibcon#wrote, iclass 15, count 2 2006.162.07:34:41.11#ibcon#about to read 3, iclass 15, count 2 2006.162.07:34:41.13#ibcon#read 3, iclass 15, count 2 2006.162.07:34:41.13#ibcon#about to read 4, iclass 15, count 2 2006.162.07:34:41.13#ibcon#read 4, iclass 15, count 2 2006.162.07:34:41.13#ibcon#about to read 5, iclass 15, count 2 2006.162.07:34:41.13#ibcon#read 5, iclass 15, count 2 2006.162.07:34:41.13#ibcon#about to read 6, iclass 15, count 2 2006.162.07:34:41.13#ibcon#read 6, iclass 15, count 2 2006.162.07:34:41.13#ibcon#end of sib2, iclass 15, count 2 2006.162.07:34:41.13#ibcon#*mode == 0, iclass 15, count 2 2006.162.07:34:41.13#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.162.07:34:41.13#ibcon#[25=AT05-07\r\n] 2006.162.07:34:41.13#ibcon#*before write, iclass 15, count 2 2006.162.07:34:41.13#ibcon#enter sib2, iclass 15, count 2 2006.162.07:34:41.13#ibcon#flushed, iclass 15, count 2 2006.162.07:34:41.13#ibcon#about to write, iclass 15, count 2 2006.162.07:34:41.13#ibcon#wrote, iclass 15, count 2 2006.162.07:34:41.13#ibcon#about to read 3, iclass 15, count 2 2006.162.07:34:41.16#ibcon#read 3, iclass 15, count 2 2006.162.07:34:41.16#ibcon#about to read 4, iclass 15, count 2 2006.162.07:34:41.16#ibcon#read 4, iclass 15, count 2 2006.162.07:34:41.16#ibcon#about to read 5, iclass 15, count 2 2006.162.07:34:41.16#ibcon#read 5, iclass 15, count 2 2006.162.07:34:41.16#ibcon#about to read 6, iclass 15, count 2 2006.162.07:34:41.16#ibcon#read 6, iclass 15, count 2 2006.162.07:34:41.16#ibcon#end of sib2, iclass 15, count 2 2006.162.07:34:41.16#ibcon#*after write, iclass 15, count 2 2006.162.07:34:41.16#ibcon#*before return 0, iclass 15, count 2 2006.162.07:34:41.16#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:34:41.16#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:34:41.16#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.162.07:34:41.16#ibcon#ireg 7 cls_cnt 0 2006.162.07:34:41.16#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:34:41.28#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:34:41.28#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:34:41.28#ibcon#enter wrdev, iclass 15, count 0 2006.162.07:34:41.28#ibcon#first serial, iclass 15, count 0 2006.162.07:34:41.28#ibcon#enter sib2, iclass 15, count 0 2006.162.07:34:41.28#ibcon#flushed, iclass 15, count 0 2006.162.07:34:41.28#ibcon#about to write, iclass 15, count 0 2006.162.07:34:41.28#ibcon#wrote, iclass 15, count 0 2006.162.07:34:41.28#ibcon#about to read 3, iclass 15, count 0 2006.162.07:34:41.30#ibcon#read 3, iclass 15, count 0 2006.162.07:34:41.30#ibcon#about to read 4, iclass 15, count 0 2006.162.07:34:41.30#ibcon#read 4, iclass 15, count 0 2006.162.07:34:41.30#ibcon#about to read 5, iclass 15, count 0 2006.162.07:34:41.30#ibcon#read 5, iclass 15, count 0 2006.162.07:34:41.30#ibcon#about to read 6, iclass 15, count 0 2006.162.07:34:41.30#ibcon#read 6, iclass 15, count 0 2006.162.07:34:41.30#ibcon#end of sib2, iclass 15, count 0 2006.162.07:34:41.30#ibcon#*mode == 0, iclass 15, count 0 2006.162.07:34:41.30#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.162.07:34:41.30#ibcon#[25=USB\r\n] 2006.162.07:34:41.30#ibcon#*before write, iclass 15, count 0 2006.162.07:34:41.30#ibcon#enter sib2, iclass 15, count 0 2006.162.07:34:41.30#ibcon#flushed, iclass 15, count 0 2006.162.07:34:41.30#ibcon#about to write, iclass 15, count 0 2006.162.07:34:41.30#ibcon#wrote, iclass 15, count 0 2006.162.07:34:41.30#ibcon#about to read 3, iclass 15, count 0 2006.162.07:34:41.33#ibcon#read 3, iclass 15, count 0 2006.162.07:34:41.33#ibcon#about to read 4, iclass 15, count 0 2006.162.07:34:41.33#ibcon#read 4, iclass 15, count 0 2006.162.07:34:41.33#ibcon#about to read 5, iclass 15, count 0 2006.162.07:34:41.33#ibcon#read 5, iclass 15, count 0 2006.162.07:34:41.33#ibcon#about to read 6, iclass 15, count 0 2006.162.07:34:41.33#ibcon#read 6, iclass 15, count 0 2006.162.07:34:41.33#ibcon#end of sib2, iclass 15, count 0 2006.162.07:34:41.33#ibcon#*after write, iclass 15, count 0 2006.162.07:34:41.33#ibcon#*before return 0, iclass 15, count 0 2006.162.07:34:41.33#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:34:41.33#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:34:41.33#ibcon#about to clear, iclass 15 cls_cnt 0 2006.162.07:34:41.33#ibcon#cleared, iclass 15 cls_cnt 0 2006.162.07:34:41.33$vc4f8/valo=6,772.99 2006.162.07:34:41.33#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.162.07:34:41.33#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.162.07:34:41.33#ibcon#ireg 17 cls_cnt 0 2006.162.07:34:41.33#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:34:41.33#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:34:41.33#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:34:41.33#ibcon#enter wrdev, iclass 17, count 0 2006.162.07:34:41.33#ibcon#first serial, iclass 17, count 0 2006.162.07:34:41.33#ibcon#enter sib2, iclass 17, count 0 2006.162.07:34:41.33#ibcon#flushed, iclass 17, count 0 2006.162.07:34:41.33#ibcon#about to write, iclass 17, count 0 2006.162.07:34:41.33#ibcon#wrote, iclass 17, count 0 2006.162.07:34:41.33#ibcon#about to read 3, iclass 17, count 0 2006.162.07:34:41.35#ibcon#read 3, iclass 17, count 0 2006.162.07:34:41.35#ibcon#about to read 4, iclass 17, count 0 2006.162.07:34:41.35#ibcon#read 4, iclass 17, count 0 2006.162.07:34:41.35#ibcon#about to read 5, iclass 17, count 0 2006.162.07:34:41.35#ibcon#read 5, iclass 17, count 0 2006.162.07:34:41.35#ibcon#about to read 6, iclass 17, count 0 2006.162.07:34:41.35#ibcon#read 6, iclass 17, count 0 2006.162.07:34:41.35#ibcon#end of sib2, iclass 17, count 0 2006.162.07:34:41.35#ibcon#*mode == 0, iclass 17, count 0 2006.162.07:34:41.35#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.162.07:34:41.35#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.07:34:41.35#ibcon#*before write, iclass 17, count 0 2006.162.07:34:41.35#ibcon#enter sib2, iclass 17, count 0 2006.162.07:34:41.35#ibcon#flushed, iclass 17, count 0 2006.162.07:34:41.35#ibcon#about to write, iclass 17, count 0 2006.162.07:34:41.35#ibcon#wrote, iclass 17, count 0 2006.162.07:34:41.35#ibcon#about to read 3, iclass 17, count 0 2006.162.07:34:41.39#ibcon#read 3, iclass 17, count 0 2006.162.07:34:41.39#ibcon#about to read 4, iclass 17, count 0 2006.162.07:34:41.39#ibcon#read 4, iclass 17, count 0 2006.162.07:34:41.39#ibcon#about to read 5, iclass 17, count 0 2006.162.07:34:41.39#ibcon#read 5, iclass 17, count 0 2006.162.07:34:41.39#ibcon#about to read 6, iclass 17, count 0 2006.162.07:34:41.39#ibcon#read 6, iclass 17, count 0 2006.162.07:34:41.39#ibcon#end of sib2, iclass 17, count 0 2006.162.07:34:41.39#ibcon#*after write, iclass 17, count 0 2006.162.07:34:41.39#ibcon#*before return 0, iclass 17, count 0 2006.162.07:34:41.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:34:41.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:34:41.39#ibcon#about to clear, iclass 17 cls_cnt 0 2006.162.07:34:41.39#ibcon#cleared, iclass 17 cls_cnt 0 2006.162.07:34:41.39$vc4f8/va=6,6 2006.162.07:34:41.39#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.162.07:34:41.39#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.162.07:34:41.39#ibcon#ireg 11 cls_cnt 2 2006.162.07:34:41.39#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:34:41.45#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:34:41.45#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:34:41.45#ibcon#enter wrdev, iclass 19, count 2 2006.162.07:34:41.45#ibcon#first serial, iclass 19, count 2 2006.162.07:34:41.45#ibcon#enter sib2, iclass 19, count 2 2006.162.07:34:41.45#ibcon#flushed, iclass 19, count 2 2006.162.07:34:41.45#ibcon#about to write, iclass 19, count 2 2006.162.07:34:41.45#ibcon#wrote, iclass 19, count 2 2006.162.07:34:41.45#ibcon#about to read 3, iclass 19, count 2 2006.162.07:34:41.47#ibcon#read 3, iclass 19, count 2 2006.162.07:34:41.47#ibcon#about to read 4, iclass 19, count 2 2006.162.07:34:41.47#ibcon#read 4, iclass 19, count 2 2006.162.07:34:41.47#ibcon#about to read 5, iclass 19, count 2 2006.162.07:34:41.47#ibcon#read 5, iclass 19, count 2 2006.162.07:34:41.47#ibcon#about to read 6, iclass 19, count 2 2006.162.07:34:41.47#ibcon#read 6, iclass 19, count 2 2006.162.07:34:41.47#ibcon#end of sib2, iclass 19, count 2 2006.162.07:34:41.47#ibcon#*mode == 0, iclass 19, count 2 2006.162.07:34:41.47#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.162.07:34:41.47#ibcon#[25=AT06-06\r\n] 2006.162.07:34:41.47#ibcon#*before write, iclass 19, count 2 2006.162.07:34:41.47#ibcon#enter sib2, iclass 19, count 2 2006.162.07:34:41.47#ibcon#flushed, iclass 19, count 2 2006.162.07:34:41.47#ibcon#about to write, iclass 19, count 2 2006.162.07:34:41.47#ibcon#wrote, iclass 19, count 2 2006.162.07:34:41.47#ibcon#about to read 3, iclass 19, count 2 2006.162.07:34:41.50#ibcon#read 3, iclass 19, count 2 2006.162.07:34:41.50#ibcon#about to read 4, iclass 19, count 2 2006.162.07:34:41.50#ibcon#read 4, iclass 19, count 2 2006.162.07:34:41.50#ibcon#about to read 5, iclass 19, count 2 2006.162.07:34:41.50#ibcon#read 5, iclass 19, count 2 2006.162.07:34:41.50#ibcon#about to read 6, iclass 19, count 2 2006.162.07:34:41.50#ibcon#read 6, iclass 19, count 2 2006.162.07:34:41.50#ibcon#end of sib2, iclass 19, count 2 2006.162.07:34:41.50#ibcon#*after write, iclass 19, count 2 2006.162.07:34:41.50#ibcon#*before return 0, iclass 19, count 2 2006.162.07:34:41.50#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:34:41.50#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:34:41.50#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.162.07:34:41.50#ibcon#ireg 7 cls_cnt 0 2006.162.07:34:41.50#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:34:41.62#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:34:41.62#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:34:41.62#ibcon#enter wrdev, iclass 19, count 0 2006.162.07:34:41.62#ibcon#first serial, iclass 19, count 0 2006.162.07:34:41.62#ibcon#enter sib2, iclass 19, count 0 2006.162.07:34:41.62#ibcon#flushed, iclass 19, count 0 2006.162.07:34:41.62#ibcon#about to write, iclass 19, count 0 2006.162.07:34:41.62#ibcon#wrote, iclass 19, count 0 2006.162.07:34:41.62#ibcon#about to read 3, iclass 19, count 0 2006.162.07:34:41.64#ibcon#read 3, iclass 19, count 0 2006.162.07:34:41.64#ibcon#about to read 4, iclass 19, count 0 2006.162.07:34:41.64#ibcon#read 4, iclass 19, count 0 2006.162.07:34:41.64#ibcon#about to read 5, iclass 19, count 0 2006.162.07:34:41.64#ibcon#read 5, iclass 19, count 0 2006.162.07:34:41.64#ibcon#about to read 6, iclass 19, count 0 2006.162.07:34:41.64#ibcon#read 6, iclass 19, count 0 2006.162.07:34:41.64#ibcon#end of sib2, iclass 19, count 0 2006.162.07:34:41.64#ibcon#*mode == 0, iclass 19, count 0 2006.162.07:34:41.64#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.162.07:34:41.64#ibcon#[25=USB\r\n] 2006.162.07:34:41.64#ibcon#*before write, iclass 19, count 0 2006.162.07:34:41.64#ibcon#enter sib2, iclass 19, count 0 2006.162.07:34:41.64#ibcon#flushed, iclass 19, count 0 2006.162.07:34:41.64#ibcon#about to write, iclass 19, count 0 2006.162.07:34:41.64#ibcon#wrote, iclass 19, count 0 2006.162.07:34:41.64#ibcon#about to read 3, iclass 19, count 0 2006.162.07:34:41.67#ibcon#read 3, iclass 19, count 0 2006.162.07:34:41.67#ibcon#about to read 4, iclass 19, count 0 2006.162.07:34:41.67#ibcon#read 4, iclass 19, count 0 2006.162.07:34:41.67#ibcon#about to read 5, iclass 19, count 0 2006.162.07:34:41.67#ibcon#read 5, iclass 19, count 0 2006.162.07:34:41.67#ibcon#about to read 6, iclass 19, count 0 2006.162.07:34:41.67#ibcon#read 6, iclass 19, count 0 2006.162.07:34:41.67#ibcon#end of sib2, iclass 19, count 0 2006.162.07:34:41.67#ibcon#*after write, iclass 19, count 0 2006.162.07:34:41.67#ibcon#*before return 0, iclass 19, count 0 2006.162.07:34:41.67#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:34:41.67#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:34:41.67#ibcon#about to clear, iclass 19 cls_cnt 0 2006.162.07:34:41.67#ibcon#cleared, iclass 19 cls_cnt 0 2006.162.07:34:41.67$vc4f8/valo=7,832.99 2006.162.07:34:41.67#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.162.07:34:41.67#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.162.07:34:41.67#ibcon#ireg 17 cls_cnt 0 2006.162.07:34:41.67#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:34:41.67#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:34:41.67#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:34:41.67#ibcon#enter wrdev, iclass 21, count 0 2006.162.07:34:41.67#ibcon#first serial, iclass 21, count 0 2006.162.07:34:41.67#ibcon#enter sib2, iclass 21, count 0 2006.162.07:34:41.67#ibcon#flushed, iclass 21, count 0 2006.162.07:34:41.67#ibcon#about to write, iclass 21, count 0 2006.162.07:34:41.67#ibcon#wrote, iclass 21, count 0 2006.162.07:34:41.67#ibcon#about to read 3, iclass 21, count 0 2006.162.07:34:41.69#ibcon#read 3, iclass 21, count 0 2006.162.07:34:41.69#ibcon#about to read 4, iclass 21, count 0 2006.162.07:34:41.69#ibcon#read 4, iclass 21, count 0 2006.162.07:34:41.69#ibcon#about to read 5, iclass 21, count 0 2006.162.07:34:41.69#ibcon#read 5, iclass 21, count 0 2006.162.07:34:41.69#ibcon#about to read 6, iclass 21, count 0 2006.162.07:34:41.69#ibcon#read 6, iclass 21, count 0 2006.162.07:34:41.69#ibcon#end of sib2, iclass 21, count 0 2006.162.07:34:41.69#ibcon#*mode == 0, iclass 21, count 0 2006.162.07:34:41.69#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.162.07:34:41.69#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.07:34:41.69#ibcon#*before write, iclass 21, count 0 2006.162.07:34:41.69#ibcon#enter sib2, iclass 21, count 0 2006.162.07:34:41.69#ibcon#flushed, iclass 21, count 0 2006.162.07:34:41.69#ibcon#about to write, iclass 21, count 0 2006.162.07:34:41.69#ibcon#wrote, iclass 21, count 0 2006.162.07:34:41.69#ibcon#about to read 3, iclass 21, count 0 2006.162.07:34:41.73#ibcon#read 3, iclass 21, count 0 2006.162.07:34:41.73#ibcon#about to read 4, iclass 21, count 0 2006.162.07:34:41.73#ibcon#read 4, iclass 21, count 0 2006.162.07:34:41.73#ibcon#about to read 5, iclass 21, count 0 2006.162.07:34:41.73#ibcon#read 5, iclass 21, count 0 2006.162.07:34:41.73#ibcon#about to read 6, iclass 21, count 0 2006.162.07:34:41.73#ibcon#read 6, iclass 21, count 0 2006.162.07:34:41.73#ibcon#end of sib2, iclass 21, count 0 2006.162.07:34:41.73#ibcon#*after write, iclass 21, count 0 2006.162.07:34:41.73#ibcon#*before return 0, iclass 21, count 0 2006.162.07:34:41.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:34:41.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:34:41.73#ibcon#about to clear, iclass 21 cls_cnt 0 2006.162.07:34:41.73#ibcon#cleared, iclass 21 cls_cnt 0 2006.162.07:34:41.73$vc4f8/va=7,6 2006.162.07:34:41.73#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.162.07:34:41.73#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.162.07:34:41.73#ibcon#ireg 11 cls_cnt 2 2006.162.07:34:41.73#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.162.07:34:41.79#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.162.07:34:41.79#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.162.07:34:41.79#ibcon#enter wrdev, iclass 23, count 2 2006.162.07:34:41.79#ibcon#first serial, iclass 23, count 2 2006.162.07:34:41.79#ibcon#enter sib2, iclass 23, count 2 2006.162.07:34:41.79#ibcon#flushed, iclass 23, count 2 2006.162.07:34:41.79#ibcon#about to write, iclass 23, count 2 2006.162.07:34:41.79#ibcon#wrote, iclass 23, count 2 2006.162.07:34:41.79#ibcon#about to read 3, iclass 23, count 2 2006.162.07:34:41.81#ibcon#read 3, iclass 23, count 2 2006.162.07:34:41.81#ibcon#about to read 4, iclass 23, count 2 2006.162.07:34:41.81#ibcon#read 4, iclass 23, count 2 2006.162.07:34:41.81#ibcon#about to read 5, iclass 23, count 2 2006.162.07:34:41.81#ibcon#read 5, iclass 23, count 2 2006.162.07:34:41.81#ibcon#about to read 6, iclass 23, count 2 2006.162.07:34:41.81#ibcon#read 6, iclass 23, count 2 2006.162.07:34:41.81#ibcon#end of sib2, iclass 23, count 2 2006.162.07:34:41.81#ibcon#*mode == 0, iclass 23, count 2 2006.162.07:34:41.81#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.162.07:34:41.81#ibcon#[25=AT07-06\r\n] 2006.162.07:34:41.81#ibcon#*before write, iclass 23, count 2 2006.162.07:34:41.81#ibcon#enter sib2, iclass 23, count 2 2006.162.07:34:41.81#ibcon#flushed, iclass 23, count 2 2006.162.07:34:41.81#ibcon#about to write, iclass 23, count 2 2006.162.07:34:41.81#ibcon#wrote, iclass 23, count 2 2006.162.07:34:41.81#ibcon#about to read 3, iclass 23, count 2 2006.162.07:34:41.84#ibcon#read 3, iclass 23, count 2 2006.162.07:34:41.84#ibcon#about to read 4, iclass 23, count 2 2006.162.07:34:41.84#ibcon#read 4, iclass 23, count 2 2006.162.07:34:41.84#ibcon#about to read 5, iclass 23, count 2 2006.162.07:34:41.84#ibcon#read 5, iclass 23, count 2 2006.162.07:34:41.84#ibcon#about to read 6, iclass 23, count 2 2006.162.07:34:41.84#ibcon#read 6, iclass 23, count 2 2006.162.07:34:41.84#ibcon#end of sib2, iclass 23, count 2 2006.162.07:34:41.84#ibcon#*after write, iclass 23, count 2 2006.162.07:34:41.84#ibcon#*before return 0, iclass 23, count 2 2006.162.07:34:41.84#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.162.07:34:41.84#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.162.07:34:41.84#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.162.07:34:41.84#ibcon#ireg 7 cls_cnt 0 2006.162.07:34:41.84#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.162.07:34:41.96#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.162.07:34:41.96#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.162.07:34:41.96#ibcon#enter wrdev, iclass 23, count 0 2006.162.07:34:41.96#ibcon#first serial, iclass 23, count 0 2006.162.07:34:41.96#ibcon#enter sib2, iclass 23, count 0 2006.162.07:34:41.96#ibcon#flushed, iclass 23, count 0 2006.162.07:34:41.96#ibcon#about to write, iclass 23, count 0 2006.162.07:34:41.96#ibcon#wrote, iclass 23, count 0 2006.162.07:34:41.96#ibcon#about to read 3, iclass 23, count 0 2006.162.07:34:41.98#ibcon#read 3, iclass 23, count 0 2006.162.07:34:41.98#ibcon#about to read 4, iclass 23, count 0 2006.162.07:34:41.98#ibcon#read 4, iclass 23, count 0 2006.162.07:34:41.98#ibcon#about to read 5, iclass 23, count 0 2006.162.07:34:41.98#ibcon#read 5, iclass 23, count 0 2006.162.07:34:41.98#ibcon#about to read 6, iclass 23, count 0 2006.162.07:34:41.98#ibcon#read 6, iclass 23, count 0 2006.162.07:34:41.98#ibcon#end of sib2, iclass 23, count 0 2006.162.07:34:41.98#ibcon#*mode == 0, iclass 23, count 0 2006.162.07:34:41.98#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.162.07:34:41.98#ibcon#[25=USB\r\n] 2006.162.07:34:41.98#ibcon#*before write, iclass 23, count 0 2006.162.07:34:41.98#ibcon#enter sib2, iclass 23, count 0 2006.162.07:34:41.98#ibcon#flushed, iclass 23, count 0 2006.162.07:34:41.98#ibcon#about to write, iclass 23, count 0 2006.162.07:34:41.98#ibcon#wrote, iclass 23, count 0 2006.162.07:34:41.98#ibcon#about to read 3, iclass 23, count 0 2006.162.07:34:42.01#ibcon#read 3, iclass 23, count 0 2006.162.07:34:42.01#ibcon#about to read 4, iclass 23, count 0 2006.162.07:34:42.01#ibcon#read 4, iclass 23, count 0 2006.162.07:34:42.01#ibcon#about to read 5, iclass 23, count 0 2006.162.07:34:42.01#ibcon#read 5, iclass 23, count 0 2006.162.07:34:42.01#ibcon#about to read 6, iclass 23, count 0 2006.162.07:34:42.01#ibcon#read 6, iclass 23, count 0 2006.162.07:34:42.01#ibcon#end of sib2, iclass 23, count 0 2006.162.07:34:42.01#ibcon#*after write, iclass 23, count 0 2006.162.07:34:42.01#ibcon#*before return 0, iclass 23, count 0 2006.162.07:34:42.01#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.162.07:34:42.01#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.162.07:34:42.01#ibcon#about to clear, iclass 23 cls_cnt 0 2006.162.07:34:42.01#ibcon#cleared, iclass 23 cls_cnt 0 2006.162.07:34:42.01$vc4f8/valo=8,852.99 2006.162.07:34:42.01#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.162.07:34:42.01#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.162.07:34:42.01#ibcon#ireg 17 cls_cnt 0 2006.162.07:34:42.01#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:34:42.01#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:34:42.01#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:34:42.01#ibcon#enter wrdev, iclass 25, count 0 2006.162.07:34:42.01#ibcon#first serial, iclass 25, count 0 2006.162.07:34:42.01#ibcon#enter sib2, iclass 25, count 0 2006.162.07:34:42.01#ibcon#flushed, iclass 25, count 0 2006.162.07:34:42.01#ibcon#about to write, iclass 25, count 0 2006.162.07:34:42.01#ibcon#wrote, iclass 25, count 0 2006.162.07:34:42.01#ibcon#about to read 3, iclass 25, count 0 2006.162.07:34:42.03#ibcon#read 3, iclass 25, count 0 2006.162.07:34:42.03#ibcon#about to read 4, iclass 25, count 0 2006.162.07:34:42.03#ibcon#read 4, iclass 25, count 0 2006.162.07:34:42.03#ibcon#about to read 5, iclass 25, count 0 2006.162.07:34:42.03#ibcon#read 5, iclass 25, count 0 2006.162.07:34:42.03#ibcon#about to read 6, iclass 25, count 0 2006.162.07:34:42.03#ibcon#read 6, iclass 25, count 0 2006.162.07:34:42.03#ibcon#end of sib2, iclass 25, count 0 2006.162.07:34:42.03#ibcon#*mode == 0, iclass 25, count 0 2006.162.07:34:42.03#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.162.07:34:42.03#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.07:34:42.03#ibcon#*before write, iclass 25, count 0 2006.162.07:34:42.03#ibcon#enter sib2, iclass 25, count 0 2006.162.07:34:42.03#ibcon#flushed, iclass 25, count 0 2006.162.07:34:42.03#ibcon#about to write, iclass 25, count 0 2006.162.07:34:42.03#ibcon#wrote, iclass 25, count 0 2006.162.07:34:42.03#ibcon#about to read 3, iclass 25, count 0 2006.162.07:34:42.07#abcon#<5=/02 1.2 3.7 17.891001007.2\r\n> 2006.162.07:34:42.07#ibcon#read 3, iclass 25, count 0 2006.162.07:34:42.07#ibcon#about to read 4, iclass 25, count 0 2006.162.07:34:42.07#ibcon#read 4, iclass 25, count 0 2006.162.07:34:42.07#ibcon#about to read 5, iclass 25, count 0 2006.162.07:34:42.07#ibcon#read 5, iclass 25, count 0 2006.162.07:34:42.07#ibcon#about to read 6, iclass 25, count 0 2006.162.07:34:42.07#ibcon#read 6, iclass 25, count 0 2006.162.07:34:42.07#ibcon#end of sib2, iclass 25, count 0 2006.162.07:34:42.07#ibcon#*after write, iclass 25, count 0 2006.162.07:34:42.07#ibcon#*before return 0, iclass 25, count 0 2006.162.07:34:42.07#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:34:42.07#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:34:42.07#ibcon#about to clear, iclass 25 cls_cnt 0 2006.162.07:34:42.07#ibcon#cleared, iclass 25 cls_cnt 0 2006.162.07:34:42.07$vc4f8/va=8,7 2006.162.07:34:42.07#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.162.07:34:42.07#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.162.07:34:42.07#ibcon#ireg 11 cls_cnt 2 2006.162.07:34:42.07#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:34:42.09#abcon#{5=INTERFACE CLEAR} 2006.162.07:34:42.13#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:34:42.13#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:34:42.13#ibcon#enter wrdev, iclass 30, count 2 2006.162.07:34:42.13#ibcon#first serial, iclass 30, count 2 2006.162.07:34:42.13#ibcon#enter sib2, iclass 30, count 2 2006.162.07:34:42.13#ibcon#flushed, iclass 30, count 2 2006.162.07:34:42.13#ibcon#about to write, iclass 30, count 2 2006.162.07:34:42.13#ibcon#wrote, iclass 30, count 2 2006.162.07:34:42.13#ibcon#about to read 3, iclass 30, count 2 2006.162.07:34:42.15#ibcon#read 3, iclass 30, count 2 2006.162.07:34:42.15#ibcon#about to read 4, iclass 30, count 2 2006.162.07:34:42.15#ibcon#read 4, iclass 30, count 2 2006.162.07:34:42.15#ibcon#about to read 5, iclass 30, count 2 2006.162.07:34:42.15#ibcon#read 5, iclass 30, count 2 2006.162.07:34:42.15#ibcon#about to read 6, iclass 30, count 2 2006.162.07:34:42.15#ibcon#read 6, iclass 30, count 2 2006.162.07:34:42.15#ibcon#end of sib2, iclass 30, count 2 2006.162.07:34:42.15#ibcon#*mode == 0, iclass 30, count 2 2006.162.07:34:42.15#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.162.07:34:42.15#ibcon#[25=AT08-07\r\n] 2006.162.07:34:42.15#ibcon#*before write, iclass 30, count 2 2006.162.07:34:42.15#ibcon#enter sib2, iclass 30, count 2 2006.162.07:34:42.15#ibcon#flushed, iclass 30, count 2 2006.162.07:34:42.15#ibcon#about to write, iclass 30, count 2 2006.162.07:34:42.15#ibcon#wrote, iclass 30, count 2 2006.162.07:34:42.15#ibcon#about to read 3, iclass 30, count 2 2006.162.07:34:42.15#abcon#[5=S1D000X0/0*\r\n] 2006.162.07:34:42.18#ibcon#read 3, iclass 30, count 2 2006.162.07:34:42.18#ibcon#about to read 4, iclass 30, count 2 2006.162.07:34:42.18#ibcon#read 4, iclass 30, count 2 2006.162.07:34:42.18#ibcon#about to read 5, iclass 30, count 2 2006.162.07:34:42.18#ibcon#read 5, iclass 30, count 2 2006.162.07:34:42.18#ibcon#about to read 6, iclass 30, count 2 2006.162.07:34:42.18#ibcon#read 6, iclass 30, count 2 2006.162.07:34:42.18#ibcon#end of sib2, iclass 30, count 2 2006.162.07:34:42.18#ibcon#*after write, iclass 30, count 2 2006.162.07:34:42.18#ibcon#*before return 0, iclass 30, count 2 2006.162.07:34:42.18#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:34:42.18#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:34:42.18#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.162.07:34:42.18#ibcon#ireg 7 cls_cnt 0 2006.162.07:34:42.18#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:34:42.30#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:34:42.30#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:34:42.30#ibcon#enter wrdev, iclass 30, count 0 2006.162.07:34:42.30#ibcon#first serial, iclass 30, count 0 2006.162.07:34:42.30#ibcon#enter sib2, iclass 30, count 0 2006.162.07:34:42.30#ibcon#flushed, iclass 30, count 0 2006.162.07:34:42.30#ibcon#about to write, iclass 30, count 0 2006.162.07:34:42.30#ibcon#wrote, iclass 30, count 0 2006.162.07:34:42.30#ibcon#about to read 3, iclass 30, count 0 2006.162.07:34:42.32#ibcon#read 3, iclass 30, count 0 2006.162.07:34:42.32#ibcon#about to read 4, iclass 30, count 0 2006.162.07:34:42.32#ibcon#read 4, iclass 30, count 0 2006.162.07:34:42.32#ibcon#about to read 5, iclass 30, count 0 2006.162.07:34:42.32#ibcon#read 5, iclass 30, count 0 2006.162.07:34:42.32#ibcon#about to read 6, iclass 30, count 0 2006.162.07:34:42.32#ibcon#read 6, iclass 30, count 0 2006.162.07:34:42.32#ibcon#end of sib2, iclass 30, count 0 2006.162.07:34:42.32#ibcon#*mode == 0, iclass 30, count 0 2006.162.07:34:42.32#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.162.07:34:42.32#ibcon#[25=USB\r\n] 2006.162.07:34:42.32#ibcon#*before write, iclass 30, count 0 2006.162.07:34:42.32#ibcon#enter sib2, iclass 30, count 0 2006.162.07:34:42.32#ibcon#flushed, iclass 30, count 0 2006.162.07:34:42.32#ibcon#about to write, iclass 30, count 0 2006.162.07:34:42.32#ibcon#wrote, iclass 30, count 0 2006.162.07:34:42.32#ibcon#about to read 3, iclass 30, count 0 2006.162.07:34:42.35#ibcon#read 3, iclass 30, count 0 2006.162.07:34:42.35#ibcon#about to read 4, iclass 30, count 0 2006.162.07:34:42.35#ibcon#read 4, iclass 30, count 0 2006.162.07:34:42.35#ibcon#about to read 5, iclass 30, count 0 2006.162.07:34:42.35#ibcon#read 5, iclass 30, count 0 2006.162.07:34:42.35#ibcon#about to read 6, iclass 30, count 0 2006.162.07:34:42.35#ibcon#read 6, iclass 30, count 0 2006.162.07:34:42.35#ibcon#end of sib2, iclass 30, count 0 2006.162.07:34:42.35#ibcon#*after write, iclass 30, count 0 2006.162.07:34:42.35#ibcon#*before return 0, iclass 30, count 0 2006.162.07:34:42.35#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:34:42.35#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:34:42.35#ibcon#about to clear, iclass 30 cls_cnt 0 2006.162.07:34:42.35#ibcon#cleared, iclass 30 cls_cnt 0 2006.162.07:34:42.35$vc4f8/vblo=1,632.99 2006.162.07:34:42.35#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.162.07:34:42.35#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.162.07:34:42.35#ibcon#ireg 17 cls_cnt 0 2006.162.07:34:42.35#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.162.07:34:42.35#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.162.07:34:42.35#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.162.07:34:42.35#ibcon#enter wrdev, iclass 33, count 0 2006.162.07:34:42.35#ibcon#first serial, iclass 33, count 0 2006.162.07:34:42.35#ibcon#enter sib2, iclass 33, count 0 2006.162.07:34:42.35#ibcon#flushed, iclass 33, count 0 2006.162.07:34:42.35#ibcon#about to write, iclass 33, count 0 2006.162.07:34:42.35#ibcon#wrote, iclass 33, count 0 2006.162.07:34:42.35#ibcon#about to read 3, iclass 33, count 0 2006.162.07:34:42.37#ibcon#read 3, iclass 33, count 0 2006.162.07:34:42.37#ibcon#about to read 4, iclass 33, count 0 2006.162.07:34:42.37#ibcon#read 4, iclass 33, count 0 2006.162.07:34:42.37#ibcon#about to read 5, iclass 33, count 0 2006.162.07:34:42.37#ibcon#read 5, iclass 33, count 0 2006.162.07:34:42.37#ibcon#about to read 6, iclass 33, count 0 2006.162.07:34:42.37#ibcon#read 6, iclass 33, count 0 2006.162.07:34:42.37#ibcon#end of sib2, iclass 33, count 0 2006.162.07:34:42.37#ibcon#*mode == 0, iclass 33, count 0 2006.162.07:34:42.37#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.162.07:34:42.37#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.07:34:42.37#ibcon#*before write, iclass 33, count 0 2006.162.07:34:42.37#ibcon#enter sib2, iclass 33, count 0 2006.162.07:34:42.37#ibcon#flushed, iclass 33, count 0 2006.162.07:34:42.37#ibcon#about to write, iclass 33, count 0 2006.162.07:34:42.37#ibcon#wrote, iclass 33, count 0 2006.162.07:34:42.37#ibcon#about to read 3, iclass 33, count 0 2006.162.07:34:42.41#ibcon#read 3, iclass 33, count 0 2006.162.07:34:42.41#ibcon#about to read 4, iclass 33, count 0 2006.162.07:34:42.41#ibcon#read 4, iclass 33, count 0 2006.162.07:34:42.41#ibcon#about to read 5, iclass 33, count 0 2006.162.07:34:42.41#ibcon#read 5, iclass 33, count 0 2006.162.07:34:42.41#ibcon#about to read 6, iclass 33, count 0 2006.162.07:34:42.41#ibcon#read 6, iclass 33, count 0 2006.162.07:34:42.41#ibcon#end of sib2, iclass 33, count 0 2006.162.07:34:42.41#ibcon#*after write, iclass 33, count 0 2006.162.07:34:42.41#ibcon#*before return 0, iclass 33, count 0 2006.162.07:34:42.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.162.07:34:42.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.162.07:34:42.41#ibcon#about to clear, iclass 33 cls_cnt 0 2006.162.07:34:42.41#ibcon#cleared, iclass 33 cls_cnt 0 2006.162.07:34:42.41$vc4f8/vb=1,4 2006.162.07:34:42.41#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.162.07:34:42.41#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.162.07:34:42.41#ibcon#ireg 11 cls_cnt 2 2006.162.07:34:42.41#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.162.07:34:42.41#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.162.07:34:42.41#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.162.07:34:42.41#ibcon#enter wrdev, iclass 35, count 2 2006.162.07:34:42.41#ibcon#first serial, iclass 35, count 2 2006.162.07:34:42.41#ibcon#enter sib2, iclass 35, count 2 2006.162.07:34:42.41#ibcon#flushed, iclass 35, count 2 2006.162.07:34:42.41#ibcon#about to write, iclass 35, count 2 2006.162.07:34:42.41#ibcon#wrote, iclass 35, count 2 2006.162.07:34:42.41#ibcon#about to read 3, iclass 35, count 2 2006.162.07:34:42.43#ibcon#read 3, iclass 35, count 2 2006.162.07:34:42.43#ibcon#about to read 4, iclass 35, count 2 2006.162.07:34:42.43#ibcon#read 4, iclass 35, count 2 2006.162.07:34:42.43#ibcon#about to read 5, iclass 35, count 2 2006.162.07:34:42.43#ibcon#read 5, iclass 35, count 2 2006.162.07:34:42.43#ibcon#about to read 6, iclass 35, count 2 2006.162.07:34:42.43#ibcon#read 6, iclass 35, count 2 2006.162.07:34:42.43#ibcon#end of sib2, iclass 35, count 2 2006.162.07:34:42.43#ibcon#*mode == 0, iclass 35, count 2 2006.162.07:34:42.43#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.162.07:34:42.43#ibcon#[27=AT01-04\r\n] 2006.162.07:34:42.43#ibcon#*before write, iclass 35, count 2 2006.162.07:34:42.43#ibcon#enter sib2, iclass 35, count 2 2006.162.07:34:42.43#ibcon#flushed, iclass 35, count 2 2006.162.07:34:42.43#ibcon#about to write, iclass 35, count 2 2006.162.07:34:42.43#ibcon#wrote, iclass 35, count 2 2006.162.07:34:42.43#ibcon#about to read 3, iclass 35, count 2 2006.162.07:34:42.46#ibcon#read 3, iclass 35, count 2 2006.162.07:34:42.46#ibcon#about to read 4, iclass 35, count 2 2006.162.07:34:42.46#ibcon#read 4, iclass 35, count 2 2006.162.07:34:42.46#ibcon#about to read 5, iclass 35, count 2 2006.162.07:34:42.46#ibcon#read 5, iclass 35, count 2 2006.162.07:34:42.46#ibcon#about to read 6, iclass 35, count 2 2006.162.07:34:42.46#ibcon#read 6, iclass 35, count 2 2006.162.07:34:42.46#ibcon#end of sib2, iclass 35, count 2 2006.162.07:34:42.46#ibcon#*after write, iclass 35, count 2 2006.162.07:34:42.46#ibcon#*before return 0, iclass 35, count 2 2006.162.07:34:42.46#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.162.07:34:42.46#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.162.07:34:42.46#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.162.07:34:42.46#ibcon#ireg 7 cls_cnt 0 2006.162.07:34:42.46#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.162.07:34:42.58#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.162.07:34:42.58#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.162.07:34:42.58#ibcon#enter wrdev, iclass 35, count 0 2006.162.07:34:42.58#ibcon#first serial, iclass 35, count 0 2006.162.07:34:42.58#ibcon#enter sib2, iclass 35, count 0 2006.162.07:34:42.58#ibcon#flushed, iclass 35, count 0 2006.162.07:34:42.58#ibcon#about to write, iclass 35, count 0 2006.162.07:34:42.58#ibcon#wrote, iclass 35, count 0 2006.162.07:34:42.58#ibcon#about to read 3, iclass 35, count 0 2006.162.07:34:42.60#ibcon#read 3, iclass 35, count 0 2006.162.07:34:42.60#ibcon#about to read 4, iclass 35, count 0 2006.162.07:34:42.60#ibcon#read 4, iclass 35, count 0 2006.162.07:34:42.60#ibcon#about to read 5, iclass 35, count 0 2006.162.07:34:42.60#ibcon#read 5, iclass 35, count 0 2006.162.07:34:42.60#ibcon#about to read 6, iclass 35, count 0 2006.162.07:34:42.60#ibcon#read 6, iclass 35, count 0 2006.162.07:34:42.60#ibcon#end of sib2, iclass 35, count 0 2006.162.07:34:42.60#ibcon#*mode == 0, iclass 35, count 0 2006.162.07:34:42.60#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.162.07:34:42.60#ibcon#[27=USB\r\n] 2006.162.07:34:42.60#ibcon#*before write, iclass 35, count 0 2006.162.07:34:42.60#ibcon#enter sib2, iclass 35, count 0 2006.162.07:34:42.60#ibcon#flushed, iclass 35, count 0 2006.162.07:34:42.60#ibcon#about to write, iclass 35, count 0 2006.162.07:34:42.60#ibcon#wrote, iclass 35, count 0 2006.162.07:34:42.60#ibcon#about to read 3, iclass 35, count 0 2006.162.07:34:42.63#ibcon#read 3, iclass 35, count 0 2006.162.07:34:42.63#ibcon#about to read 4, iclass 35, count 0 2006.162.07:34:42.63#ibcon#read 4, iclass 35, count 0 2006.162.07:34:42.63#ibcon#about to read 5, iclass 35, count 0 2006.162.07:34:42.63#ibcon#read 5, iclass 35, count 0 2006.162.07:34:42.63#ibcon#about to read 6, iclass 35, count 0 2006.162.07:34:42.63#ibcon#read 6, iclass 35, count 0 2006.162.07:34:42.63#ibcon#end of sib2, iclass 35, count 0 2006.162.07:34:42.63#ibcon#*after write, iclass 35, count 0 2006.162.07:34:42.63#ibcon#*before return 0, iclass 35, count 0 2006.162.07:34:42.63#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.162.07:34:42.63#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.162.07:34:42.63#ibcon#about to clear, iclass 35 cls_cnt 0 2006.162.07:34:42.63#ibcon#cleared, iclass 35 cls_cnt 0 2006.162.07:34:42.63$vc4f8/vblo=2,640.99 2006.162.07:34:42.63#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.162.07:34:42.63#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.162.07:34:42.63#ibcon#ireg 17 cls_cnt 0 2006.162.07:34:42.63#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.162.07:34:42.63#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.162.07:34:42.63#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.162.07:34:42.63#ibcon#enter wrdev, iclass 37, count 0 2006.162.07:34:42.63#ibcon#first serial, iclass 37, count 0 2006.162.07:34:42.63#ibcon#enter sib2, iclass 37, count 0 2006.162.07:34:42.63#ibcon#flushed, iclass 37, count 0 2006.162.07:34:42.63#ibcon#about to write, iclass 37, count 0 2006.162.07:34:42.63#ibcon#wrote, iclass 37, count 0 2006.162.07:34:42.63#ibcon#about to read 3, iclass 37, count 0 2006.162.07:34:42.65#ibcon#read 3, iclass 37, count 0 2006.162.07:34:42.65#ibcon#about to read 4, iclass 37, count 0 2006.162.07:34:42.65#ibcon#read 4, iclass 37, count 0 2006.162.07:34:42.65#ibcon#about to read 5, iclass 37, count 0 2006.162.07:34:42.65#ibcon#read 5, iclass 37, count 0 2006.162.07:34:42.65#ibcon#about to read 6, iclass 37, count 0 2006.162.07:34:42.65#ibcon#read 6, iclass 37, count 0 2006.162.07:34:42.65#ibcon#end of sib2, iclass 37, count 0 2006.162.07:34:42.65#ibcon#*mode == 0, iclass 37, count 0 2006.162.07:34:42.65#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.162.07:34:42.65#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.07:34:42.65#ibcon#*before write, iclass 37, count 0 2006.162.07:34:42.65#ibcon#enter sib2, iclass 37, count 0 2006.162.07:34:42.65#ibcon#flushed, iclass 37, count 0 2006.162.07:34:42.65#ibcon#about to write, iclass 37, count 0 2006.162.07:34:42.65#ibcon#wrote, iclass 37, count 0 2006.162.07:34:42.65#ibcon#about to read 3, iclass 37, count 0 2006.162.07:34:42.69#ibcon#read 3, iclass 37, count 0 2006.162.07:34:42.69#ibcon#about to read 4, iclass 37, count 0 2006.162.07:34:42.69#ibcon#read 4, iclass 37, count 0 2006.162.07:34:42.69#ibcon#about to read 5, iclass 37, count 0 2006.162.07:34:42.69#ibcon#read 5, iclass 37, count 0 2006.162.07:34:42.69#ibcon#about to read 6, iclass 37, count 0 2006.162.07:34:42.69#ibcon#read 6, iclass 37, count 0 2006.162.07:34:42.69#ibcon#end of sib2, iclass 37, count 0 2006.162.07:34:42.69#ibcon#*after write, iclass 37, count 0 2006.162.07:34:42.69#ibcon#*before return 0, iclass 37, count 0 2006.162.07:34:42.69#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.162.07:34:42.69#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.162.07:34:42.69#ibcon#about to clear, iclass 37 cls_cnt 0 2006.162.07:34:42.69#ibcon#cleared, iclass 37 cls_cnt 0 2006.162.07:34:42.69$vc4f8/vb=2,4 2006.162.07:34:42.69#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.162.07:34:42.69#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.162.07:34:42.69#ibcon#ireg 11 cls_cnt 2 2006.162.07:34:42.69#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.162.07:34:42.75#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.162.07:34:42.75#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.162.07:34:42.75#ibcon#enter wrdev, iclass 39, count 2 2006.162.07:34:42.75#ibcon#first serial, iclass 39, count 2 2006.162.07:34:42.75#ibcon#enter sib2, iclass 39, count 2 2006.162.07:34:42.75#ibcon#flushed, iclass 39, count 2 2006.162.07:34:42.75#ibcon#about to write, iclass 39, count 2 2006.162.07:34:42.75#ibcon#wrote, iclass 39, count 2 2006.162.07:34:42.75#ibcon#about to read 3, iclass 39, count 2 2006.162.07:34:42.77#ibcon#read 3, iclass 39, count 2 2006.162.07:34:42.77#ibcon#about to read 4, iclass 39, count 2 2006.162.07:34:42.77#ibcon#read 4, iclass 39, count 2 2006.162.07:34:42.77#ibcon#about to read 5, iclass 39, count 2 2006.162.07:34:42.77#ibcon#read 5, iclass 39, count 2 2006.162.07:34:42.77#ibcon#about to read 6, iclass 39, count 2 2006.162.07:34:42.77#ibcon#read 6, iclass 39, count 2 2006.162.07:34:42.77#ibcon#end of sib2, iclass 39, count 2 2006.162.07:34:42.77#ibcon#*mode == 0, iclass 39, count 2 2006.162.07:34:42.77#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.162.07:34:42.77#ibcon#[27=AT02-04\r\n] 2006.162.07:34:42.77#ibcon#*before write, iclass 39, count 2 2006.162.07:34:42.77#ibcon#enter sib2, iclass 39, count 2 2006.162.07:34:42.77#ibcon#flushed, iclass 39, count 2 2006.162.07:34:42.77#ibcon#about to write, iclass 39, count 2 2006.162.07:34:42.77#ibcon#wrote, iclass 39, count 2 2006.162.07:34:42.77#ibcon#about to read 3, iclass 39, count 2 2006.162.07:34:42.80#ibcon#read 3, iclass 39, count 2 2006.162.07:34:42.80#ibcon#about to read 4, iclass 39, count 2 2006.162.07:34:42.80#ibcon#read 4, iclass 39, count 2 2006.162.07:34:42.80#ibcon#about to read 5, iclass 39, count 2 2006.162.07:34:42.80#ibcon#read 5, iclass 39, count 2 2006.162.07:34:42.80#ibcon#about to read 6, iclass 39, count 2 2006.162.07:34:42.80#ibcon#read 6, iclass 39, count 2 2006.162.07:34:42.80#ibcon#end of sib2, iclass 39, count 2 2006.162.07:34:42.80#ibcon#*after write, iclass 39, count 2 2006.162.07:34:42.80#ibcon#*before return 0, iclass 39, count 2 2006.162.07:34:42.80#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.162.07:34:42.80#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.162.07:34:42.80#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.162.07:34:42.80#ibcon#ireg 7 cls_cnt 0 2006.162.07:34:42.80#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.162.07:34:42.92#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.162.07:34:42.92#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.162.07:34:42.92#ibcon#enter wrdev, iclass 39, count 0 2006.162.07:34:42.92#ibcon#first serial, iclass 39, count 0 2006.162.07:34:42.92#ibcon#enter sib2, iclass 39, count 0 2006.162.07:34:42.92#ibcon#flushed, iclass 39, count 0 2006.162.07:34:42.92#ibcon#about to write, iclass 39, count 0 2006.162.07:34:42.92#ibcon#wrote, iclass 39, count 0 2006.162.07:34:42.92#ibcon#about to read 3, iclass 39, count 0 2006.162.07:34:42.94#ibcon#read 3, iclass 39, count 0 2006.162.07:34:42.94#ibcon#about to read 4, iclass 39, count 0 2006.162.07:34:42.94#ibcon#read 4, iclass 39, count 0 2006.162.07:34:42.94#ibcon#about to read 5, iclass 39, count 0 2006.162.07:34:42.94#ibcon#read 5, iclass 39, count 0 2006.162.07:34:42.94#ibcon#about to read 6, iclass 39, count 0 2006.162.07:34:42.94#ibcon#read 6, iclass 39, count 0 2006.162.07:34:42.94#ibcon#end of sib2, iclass 39, count 0 2006.162.07:34:42.94#ibcon#*mode == 0, iclass 39, count 0 2006.162.07:34:42.94#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.162.07:34:42.94#ibcon#[27=USB\r\n] 2006.162.07:34:42.94#ibcon#*before write, iclass 39, count 0 2006.162.07:34:42.94#ibcon#enter sib2, iclass 39, count 0 2006.162.07:34:42.94#ibcon#flushed, iclass 39, count 0 2006.162.07:34:42.94#ibcon#about to write, iclass 39, count 0 2006.162.07:34:42.94#ibcon#wrote, iclass 39, count 0 2006.162.07:34:42.94#ibcon#about to read 3, iclass 39, count 0 2006.162.07:34:42.97#ibcon#read 3, iclass 39, count 0 2006.162.07:34:42.97#ibcon#about to read 4, iclass 39, count 0 2006.162.07:34:42.97#ibcon#read 4, iclass 39, count 0 2006.162.07:34:42.97#ibcon#about to read 5, iclass 39, count 0 2006.162.07:34:42.97#ibcon#read 5, iclass 39, count 0 2006.162.07:34:42.97#ibcon#about to read 6, iclass 39, count 0 2006.162.07:34:42.97#ibcon#read 6, iclass 39, count 0 2006.162.07:34:42.97#ibcon#end of sib2, iclass 39, count 0 2006.162.07:34:42.97#ibcon#*after write, iclass 39, count 0 2006.162.07:34:42.97#ibcon#*before return 0, iclass 39, count 0 2006.162.07:34:42.97#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.162.07:34:42.97#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.162.07:34:42.97#ibcon#about to clear, iclass 39 cls_cnt 0 2006.162.07:34:42.97#ibcon#cleared, iclass 39 cls_cnt 0 2006.162.07:34:42.97$vc4f8/vblo=3,656.99 2006.162.07:34:42.97#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.162.07:34:42.97#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.162.07:34:42.97#ibcon#ireg 17 cls_cnt 0 2006.162.07:34:42.97#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.162.07:34:42.97#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.162.07:34:42.97#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.162.07:34:42.97#ibcon#enter wrdev, iclass 3, count 0 2006.162.07:34:42.97#ibcon#first serial, iclass 3, count 0 2006.162.07:34:42.97#ibcon#enter sib2, iclass 3, count 0 2006.162.07:34:42.97#ibcon#flushed, iclass 3, count 0 2006.162.07:34:42.97#ibcon#about to write, iclass 3, count 0 2006.162.07:34:42.97#ibcon#wrote, iclass 3, count 0 2006.162.07:34:42.97#ibcon#about to read 3, iclass 3, count 0 2006.162.07:34:42.99#ibcon#read 3, iclass 3, count 0 2006.162.07:34:42.99#ibcon#about to read 4, iclass 3, count 0 2006.162.07:34:42.99#ibcon#read 4, iclass 3, count 0 2006.162.07:34:42.99#ibcon#about to read 5, iclass 3, count 0 2006.162.07:34:42.99#ibcon#read 5, iclass 3, count 0 2006.162.07:34:42.99#ibcon#about to read 6, iclass 3, count 0 2006.162.07:34:42.99#ibcon#read 6, iclass 3, count 0 2006.162.07:34:42.99#ibcon#end of sib2, iclass 3, count 0 2006.162.07:34:42.99#ibcon#*mode == 0, iclass 3, count 0 2006.162.07:34:42.99#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.162.07:34:42.99#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.07:34:42.99#ibcon#*before write, iclass 3, count 0 2006.162.07:34:42.99#ibcon#enter sib2, iclass 3, count 0 2006.162.07:34:42.99#ibcon#flushed, iclass 3, count 0 2006.162.07:34:42.99#ibcon#about to write, iclass 3, count 0 2006.162.07:34:42.99#ibcon#wrote, iclass 3, count 0 2006.162.07:34:42.99#ibcon#about to read 3, iclass 3, count 0 2006.162.07:34:43.03#ibcon#read 3, iclass 3, count 0 2006.162.07:34:43.03#ibcon#about to read 4, iclass 3, count 0 2006.162.07:34:43.03#ibcon#read 4, iclass 3, count 0 2006.162.07:34:43.03#ibcon#about to read 5, iclass 3, count 0 2006.162.07:34:43.03#ibcon#read 5, iclass 3, count 0 2006.162.07:34:43.03#ibcon#about to read 6, iclass 3, count 0 2006.162.07:34:43.03#ibcon#read 6, iclass 3, count 0 2006.162.07:34:43.03#ibcon#end of sib2, iclass 3, count 0 2006.162.07:34:43.03#ibcon#*after write, iclass 3, count 0 2006.162.07:34:43.03#ibcon#*before return 0, iclass 3, count 0 2006.162.07:34:43.03#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.162.07:34:43.03#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.162.07:34:43.03#ibcon#about to clear, iclass 3 cls_cnt 0 2006.162.07:34:43.03#ibcon#cleared, iclass 3 cls_cnt 0 2006.162.07:34:43.03$vc4f8/vb=3,4 2006.162.07:34:43.03#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.162.07:34:43.03#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.162.07:34:43.03#ibcon#ireg 11 cls_cnt 2 2006.162.07:34:43.03#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.162.07:34:43.09#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.162.07:34:43.09#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.162.07:34:43.09#ibcon#enter wrdev, iclass 5, count 2 2006.162.07:34:43.09#ibcon#first serial, iclass 5, count 2 2006.162.07:34:43.09#ibcon#enter sib2, iclass 5, count 2 2006.162.07:34:43.09#ibcon#flushed, iclass 5, count 2 2006.162.07:34:43.09#ibcon#about to write, iclass 5, count 2 2006.162.07:34:43.09#ibcon#wrote, iclass 5, count 2 2006.162.07:34:43.09#ibcon#about to read 3, iclass 5, count 2 2006.162.07:34:43.11#ibcon#read 3, iclass 5, count 2 2006.162.07:34:43.11#ibcon#about to read 4, iclass 5, count 2 2006.162.07:34:43.11#ibcon#read 4, iclass 5, count 2 2006.162.07:34:43.11#ibcon#about to read 5, iclass 5, count 2 2006.162.07:34:43.11#ibcon#read 5, iclass 5, count 2 2006.162.07:34:43.11#ibcon#about to read 6, iclass 5, count 2 2006.162.07:34:43.11#ibcon#read 6, iclass 5, count 2 2006.162.07:34:43.11#ibcon#end of sib2, iclass 5, count 2 2006.162.07:34:43.11#ibcon#*mode == 0, iclass 5, count 2 2006.162.07:34:43.11#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.162.07:34:43.11#ibcon#[27=AT03-04\r\n] 2006.162.07:34:43.11#ibcon#*before write, iclass 5, count 2 2006.162.07:34:43.11#ibcon#enter sib2, iclass 5, count 2 2006.162.07:34:43.11#ibcon#flushed, iclass 5, count 2 2006.162.07:34:43.11#ibcon#about to write, iclass 5, count 2 2006.162.07:34:43.11#ibcon#wrote, iclass 5, count 2 2006.162.07:34:43.11#ibcon#about to read 3, iclass 5, count 2 2006.162.07:34:43.14#ibcon#read 3, iclass 5, count 2 2006.162.07:34:43.14#ibcon#about to read 4, iclass 5, count 2 2006.162.07:34:43.14#ibcon#read 4, iclass 5, count 2 2006.162.07:34:43.14#ibcon#about to read 5, iclass 5, count 2 2006.162.07:34:43.14#ibcon#read 5, iclass 5, count 2 2006.162.07:34:43.14#ibcon#about to read 6, iclass 5, count 2 2006.162.07:34:43.14#ibcon#read 6, iclass 5, count 2 2006.162.07:34:43.14#ibcon#end of sib2, iclass 5, count 2 2006.162.07:34:43.14#ibcon#*after write, iclass 5, count 2 2006.162.07:34:43.14#ibcon#*before return 0, iclass 5, count 2 2006.162.07:34:43.14#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.162.07:34:43.14#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.162.07:34:43.14#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.162.07:34:43.14#ibcon#ireg 7 cls_cnt 0 2006.162.07:34:43.14#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.162.07:34:43.26#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.162.07:34:43.26#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.162.07:34:43.26#ibcon#enter wrdev, iclass 5, count 0 2006.162.07:34:43.26#ibcon#first serial, iclass 5, count 0 2006.162.07:34:43.26#ibcon#enter sib2, iclass 5, count 0 2006.162.07:34:43.26#ibcon#flushed, iclass 5, count 0 2006.162.07:34:43.26#ibcon#about to write, iclass 5, count 0 2006.162.07:34:43.26#ibcon#wrote, iclass 5, count 0 2006.162.07:34:43.26#ibcon#about to read 3, iclass 5, count 0 2006.162.07:34:43.28#ibcon#read 3, iclass 5, count 0 2006.162.07:34:43.28#ibcon#about to read 4, iclass 5, count 0 2006.162.07:34:43.28#ibcon#read 4, iclass 5, count 0 2006.162.07:34:43.28#ibcon#about to read 5, iclass 5, count 0 2006.162.07:34:43.28#ibcon#read 5, iclass 5, count 0 2006.162.07:34:43.28#ibcon#about to read 6, iclass 5, count 0 2006.162.07:34:43.28#ibcon#read 6, iclass 5, count 0 2006.162.07:34:43.28#ibcon#end of sib2, iclass 5, count 0 2006.162.07:34:43.28#ibcon#*mode == 0, iclass 5, count 0 2006.162.07:34:43.28#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.162.07:34:43.28#ibcon#[27=USB\r\n] 2006.162.07:34:43.28#ibcon#*before write, iclass 5, count 0 2006.162.07:34:43.28#ibcon#enter sib2, iclass 5, count 0 2006.162.07:34:43.28#ibcon#flushed, iclass 5, count 0 2006.162.07:34:43.28#ibcon#about to write, iclass 5, count 0 2006.162.07:34:43.28#ibcon#wrote, iclass 5, count 0 2006.162.07:34:43.28#ibcon#about to read 3, iclass 5, count 0 2006.162.07:34:43.31#ibcon#read 3, iclass 5, count 0 2006.162.07:34:43.31#ibcon#about to read 4, iclass 5, count 0 2006.162.07:34:43.31#ibcon#read 4, iclass 5, count 0 2006.162.07:34:43.31#ibcon#about to read 5, iclass 5, count 0 2006.162.07:34:43.31#ibcon#read 5, iclass 5, count 0 2006.162.07:34:43.31#ibcon#about to read 6, iclass 5, count 0 2006.162.07:34:43.31#ibcon#read 6, iclass 5, count 0 2006.162.07:34:43.31#ibcon#end of sib2, iclass 5, count 0 2006.162.07:34:43.31#ibcon#*after write, iclass 5, count 0 2006.162.07:34:43.31#ibcon#*before return 0, iclass 5, count 0 2006.162.07:34:43.31#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.162.07:34:43.31#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.162.07:34:43.31#ibcon#about to clear, iclass 5 cls_cnt 0 2006.162.07:34:43.31#ibcon#cleared, iclass 5 cls_cnt 0 2006.162.07:34:43.31$vc4f8/vblo=4,712.99 2006.162.07:34:43.31#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.162.07:34:43.31#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.162.07:34:43.31#ibcon#ireg 17 cls_cnt 0 2006.162.07:34:43.31#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:34:43.31#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:34:43.31#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:34:43.31#ibcon#enter wrdev, iclass 7, count 0 2006.162.07:34:43.31#ibcon#first serial, iclass 7, count 0 2006.162.07:34:43.31#ibcon#enter sib2, iclass 7, count 0 2006.162.07:34:43.31#ibcon#flushed, iclass 7, count 0 2006.162.07:34:43.31#ibcon#about to write, iclass 7, count 0 2006.162.07:34:43.31#ibcon#wrote, iclass 7, count 0 2006.162.07:34:43.31#ibcon#about to read 3, iclass 7, count 0 2006.162.07:34:43.33#ibcon#read 3, iclass 7, count 0 2006.162.07:34:43.33#ibcon#about to read 4, iclass 7, count 0 2006.162.07:34:43.33#ibcon#read 4, iclass 7, count 0 2006.162.07:34:43.33#ibcon#about to read 5, iclass 7, count 0 2006.162.07:34:43.33#ibcon#read 5, iclass 7, count 0 2006.162.07:34:43.33#ibcon#about to read 6, iclass 7, count 0 2006.162.07:34:43.33#ibcon#read 6, iclass 7, count 0 2006.162.07:34:43.33#ibcon#end of sib2, iclass 7, count 0 2006.162.07:34:43.33#ibcon#*mode == 0, iclass 7, count 0 2006.162.07:34:43.33#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.162.07:34:43.33#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.07:34:43.33#ibcon#*before write, iclass 7, count 0 2006.162.07:34:43.33#ibcon#enter sib2, iclass 7, count 0 2006.162.07:34:43.33#ibcon#flushed, iclass 7, count 0 2006.162.07:34:43.33#ibcon#about to write, iclass 7, count 0 2006.162.07:34:43.33#ibcon#wrote, iclass 7, count 0 2006.162.07:34:43.33#ibcon#about to read 3, iclass 7, count 0 2006.162.07:34:43.37#ibcon#read 3, iclass 7, count 0 2006.162.07:34:43.37#ibcon#about to read 4, iclass 7, count 0 2006.162.07:34:43.37#ibcon#read 4, iclass 7, count 0 2006.162.07:34:43.37#ibcon#about to read 5, iclass 7, count 0 2006.162.07:34:43.37#ibcon#read 5, iclass 7, count 0 2006.162.07:34:43.37#ibcon#about to read 6, iclass 7, count 0 2006.162.07:34:43.37#ibcon#read 6, iclass 7, count 0 2006.162.07:34:43.37#ibcon#end of sib2, iclass 7, count 0 2006.162.07:34:43.37#ibcon#*after write, iclass 7, count 0 2006.162.07:34:43.37#ibcon#*before return 0, iclass 7, count 0 2006.162.07:34:43.37#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:34:43.37#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:34:43.37#ibcon#about to clear, iclass 7 cls_cnt 0 2006.162.07:34:43.37#ibcon#cleared, iclass 7 cls_cnt 0 2006.162.07:34:43.37$vc4f8/vb=4,4 2006.162.07:34:43.37#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.162.07:34:43.37#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.162.07:34:43.37#ibcon#ireg 11 cls_cnt 2 2006.162.07:34:43.37#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:34:43.43#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:34:43.43#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:34:43.43#ibcon#enter wrdev, iclass 11, count 2 2006.162.07:34:43.43#ibcon#first serial, iclass 11, count 2 2006.162.07:34:43.43#ibcon#enter sib2, iclass 11, count 2 2006.162.07:34:43.43#ibcon#flushed, iclass 11, count 2 2006.162.07:34:43.43#ibcon#about to write, iclass 11, count 2 2006.162.07:34:43.43#ibcon#wrote, iclass 11, count 2 2006.162.07:34:43.43#ibcon#about to read 3, iclass 11, count 2 2006.162.07:34:43.45#ibcon#read 3, iclass 11, count 2 2006.162.07:34:43.45#ibcon#about to read 4, iclass 11, count 2 2006.162.07:34:43.45#ibcon#read 4, iclass 11, count 2 2006.162.07:34:43.45#ibcon#about to read 5, iclass 11, count 2 2006.162.07:34:43.45#ibcon#read 5, iclass 11, count 2 2006.162.07:34:43.45#ibcon#about to read 6, iclass 11, count 2 2006.162.07:34:43.45#ibcon#read 6, iclass 11, count 2 2006.162.07:34:43.45#ibcon#end of sib2, iclass 11, count 2 2006.162.07:34:43.45#ibcon#*mode == 0, iclass 11, count 2 2006.162.07:34:43.45#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.162.07:34:43.45#ibcon#[27=AT04-04\r\n] 2006.162.07:34:43.45#ibcon#*before write, iclass 11, count 2 2006.162.07:34:43.45#ibcon#enter sib2, iclass 11, count 2 2006.162.07:34:43.45#ibcon#flushed, iclass 11, count 2 2006.162.07:34:43.45#ibcon#about to write, iclass 11, count 2 2006.162.07:34:43.45#ibcon#wrote, iclass 11, count 2 2006.162.07:34:43.45#ibcon#about to read 3, iclass 11, count 2 2006.162.07:34:43.48#ibcon#read 3, iclass 11, count 2 2006.162.07:34:43.48#ibcon#about to read 4, iclass 11, count 2 2006.162.07:34:43.48#ibcon#read 4, iclass 11, count 2 2006.162.07:34:43.48#ibcon#about to read 5, iclass 11, count 2 2006.162.07:34:43.48#ibcon#read 5, iclass 11, count 2 2006.162.07:34:43.48#ibcon#about to read 6, iclass 11, count 2 2006.162.07:34:43.48#ibcon#read 6, iclass 11, count 2 2006.162.07:34:43.48#ibcon#end of sib2, iclass 11, count 2 2006.162.07:34:43.48#ibcon#*after write, iclass 11, count 2 2006.162.07:34:43.48#ibcon#*before return 0, iclass 11, count 2 2006.162.07:34:43.48#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:34:43.48#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:34:43.48#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.162.07:34:43.48#ibcon#ireg 7 cls_cnt 0 2006.162.07:34:43.48#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:34:43.60#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:34:43.60#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:34:43.60#ibcon#enter wrdev, iclass 11, count 0 2006.162.07:34:43.60#ibcon#first serial, iclass 11, count 0 2006.162.07:34:43.60#ibcon#enter sib2, iclass 11, count 0 2006.162.07:34:43.60#ibcon#flushed, iclass 11, count 0 2006.162.07:34:43.60#ibcon#about to write, iclass 11, count 0 2006.162.07:34:43.60#ibcon#wrote, iclass 11, count 0 2006.162.07:34:43.60#ibcon#about to read 3, iclass 11, count 0 2006.162.07:34:43.62#ibcon#read 3, iclass 11, count 0 2006.162.07:34:43.62#ibcon#about to read 4, iclass 11, count 0 2006.162.07:34:43.62#ibcon#read 4, iclass 11, count 0 2006.162.07:34:43.62#ibcon#about to read 5, iclass 11, count 0 2006.162.07:34:43.62#ibcon#read 5, iclass 11, count 0 2006.162.07:34:43.62#ibcon#about to read 6, iclass 11, count 0 2006.162.07:34:43.62#ibcon#read 6, iclass 11, count 0 2006.162.07:34:43.62#ibcon#end of sib2, iclass 11, count 0 2006.162.07:34:43.62#ibcon#*mode == 0, iclass 11, count 0 2006.162.07:34:43.62#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.162.07:34:43.62#ibcon#[27=USB\r\n] 2006.162.07:34:43.62#ibcon#*before write, iclass 11, count 0 2006.162.07:34:43.62#ibcon#enter sib2, iclass 11, count 0 2006.162.07:34:43.62#ibcon#flushed, iclass 11, count 0 2006.162.07:34:43.62#ibcon#about to write, iclass 11, count 0 2006.162.07:34:43.62#ibcon#wrote, iclass 11, count 0 2006.162.07:34:43.62#ibcon#about to read 3, iclass 11, count 0 2006.162.07:34:43.65#ibcon#read 3, iclass 11, count 0 2006.162.07:34:43.65#ibcon#about to read 4, iclass 11, count 0 2006.162.07:34:43.65#ibcon#read 4, iclass 11, count 0 2006.162.07:34:43.65#ibcon#about to read 5, iclass 11, count 0 2006.162.07:34:43.65#ibcon#read 5, iclass 11, count 0 2006.162.07:34:43.65#ibcon#about to read 6, iclass 11, count 0 2006.162.07:34:43.65#ibcon#read 6, iclass 11, count 0 2006.162.07:34:43.65#ibcon#end of sib2, iclass 11, count 0 2006.162.07:34:43.65#ibcon#*after write, iclass 11, count 0 2006.162.07:34:43.65#ibcon#*before return 0, iclass 11, count 0 2006.162.07:34:43.65#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:34:43.65#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:34:43.65#ibcon#about to clear, iclass 11 cls_cnt 0 2006.162.07:34:43.65#ibcon#cleared, iclass 11 cls_cnt 0 2006.162.07:34:43.65$vc4f8/vblo=5,744.99 2006.162.07:34:43.65#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.162.07:34:43.65#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.162.07:34:43.65#ibcon#ireg 17 cls_cnt 0 2006.162.07:34:43.65#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:34:43.65#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:34:43.65#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:34:43.65#ibcon#enter wrdev, iclass 13, count 0 2006.162.07:34:43.65#ibcon#first serial, iclass 13, count 0 2006.162.07:34:43.65#ibcon#enter sib2, iclass 13, count 0 2006.162.07:34:43.65#ibcon#flushed, iclass 13, count 0 2006.162.07:34:43.65#ibcon#about to write, iclass 13, count 0 2006.162.07:34:43.65#ibcon#wrote, iclass 13, count 0 2006.162.07:34:43.65#ibcon#about to read 3, iclass 13, count 0 2006.162.07:34:43.67#ibcon#read 3, iclass 13, count 0 2006.162.07:34:43.67#ibcon#about to read 4, iclass 13, count 0 2006.162.07:34:43.67#ibcon#read 4, iclass 13, count 0 2006.162.07:34:43.67#ibcon#about to read 5, iclass 13, count 0 2006.162.07:34:43.67#ibcon#read 5, iclass 13, count 0 2006.162.07:34:43.67#ibcon#about to read 6, iclass 13, count 0 2006.162.07:34:43.67#ibcon#read 6, iclass 13, count 0 2006.162.07:34:43.67#ibcon#end of sib2, iclass 13, count 0 2006.162.07:34:43.67#ibcon#*mode == 0, iclass 13, count 0 2006.162.07:34:43.67#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.162.07:34:43.67#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.07:34:43.67#ibcon#*before write, iclass 13, count 0 2006.162.07:34:43.67#ibcon#enter sib2, iclass 13, count 0 2006.162.07:34:43.67#ibcon#flushed, iclass 13, count 0 2006.162.07:34:43.67#ibcon#about to write, iclass 13, count 0 2006.162.07:34:43.67#ibcon#wrote, iclass 13, count 0 2006.162.07:34:43.67#ibcon#about to read 3, iclass 13, count 0 2006.162.07:34:43.71#ibcon#read 3, iclass 13, count 0 2006.162.07:34:43.71#ibcon#about to read 4, iclass 13, count 0 2006.162.07:34:43.71#ibcon#read 4, iclass 13, count 0 2006.162.07:34:43.71#ibcon#about to read 5, iclass 13, count 0 2006.162.07:34:43.71#ibcon#read 5, iclass 13, count 0 2006.162.07:34:43.71#ibcon#about to read 6, iclass 13, count 0 2006.162.07:34:43.71#ibcon#read 6, iclass 13, count 0 2006.162.07:34:43.71#ibcon#end of sib2, iclass 13, count 0 2006.162.07:34:43.71#ibcon#*after write, iclass 13, count 0 2006.162.07:34:43.71#ibcon#*before return 0, iclass 13, count 0 2006.162.07:34:43.71#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:34:43.71#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:34:43.71#ibcon#about to clear, iclass 13 cls_cnt 0 2006.162.07:34:43.71#ibcon#cleared, iclass 13 cls_cnt 0 2006.162.07:34:43.71$vc4f8/vb=5,4 2006.162.07:34:43.71#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.162.07:34:43.71#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.162.07:34:43.71#ibcon#ireg 11 cls_cnt 2 2006.162.07:34:43.71#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:34:43.77#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:34:43.77#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:34:43.77#ibcon#enter wrdev, iclass 15, count 2 2006.162.07:34:43.77#ibcon#first serial, iclass 15, count 2 2006.162.07:34:43.77#ibcon#enter sib2, iclass 15, count 2 2006.162.07:34:43.77#ibcon#flushed, iclass 15, count 2 2006.162.07:34:43.77#ibcon#about to write, iclass 15, count 2 2006.162.07:34:43.77#ibcon#wrote, iclass 15, count 2 2006.162.07:34:43.77#ibcon#about to read 3, iclass 15, count 2 2006.162.07:34:43.79#ibcon#read 3, iclass 15, count 2 2006.162.07:34:43.79#ibcon#about to read 4, iclass 15, count 2 2006.162.07:34:43.79#ibcon#read 4, iclass 15, count 2 2006.162.07:34:43.79#ibcon#about to read 5, iclass 15, count 2 2006.162.07:34:43.79#ibcon#read 5, iclass 15, count 2 2006.162.07:34:43.79#ibcon#about to read 6, iclass 15, count 2 2006.162.07:34:43.79#ibcon#read 6, iclass 15, count 2 2006.162.07:34:43.79#ibcon#end of sib2, iclass 15, count 2 2006.162.07:34:43.79#ibcon#*mode == 0, iclass 15, count 2 2006.162.07:34:43.79#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.162.07:34:43.79#ibcon#[27=AT05-04\r\n] 2006.162.07:34:43.79#ibcon#*before write, iclass 15, count 2 2006.162.07:34:43.79#ibcon#enter sib2, iclass 15, count 2 2006.162.07:34:43.79#ibcon#flushed, iclass 15, count 2 2006.162.07:34:43.79#ibcon#about to write, iclass 15, count 2 2006.162.07:34:43.79#ibcon#wrote, iclass 15, count 2 2006.162.07:34:43.79#ibcon#about to read 3, iclass 15, count 2 2006.162.07:34:43.82#ibcon#read 3, iclass 15, count 2 2006.162.07:34:43.82#ibcon#about to read 4, iclass 15, count 2 2006.162.07:34:43.82#ibcon#read 4, iclass 15, count 2 2006.162.07:34:43.82#ibcon#about to read 5, iclass 15, count 2 2006.162.07:34:43.82#ibcon#read 5, iclass 15, count 2 2006.162.07:34:43.82#ibcon#about to read 6, iclass 15, count 2 2006.162.07:34:43.82#ibcon#read 6, iclass 15, count 2 2006.162.07:34:43.82#ibcon#end of sib2, iclass 15, count 2 2006.162.07:34:43.82#ibcon#*after write, iclass 15, count 2 2006.162.07:34:43.82#ibcon#*before return 0, iclass 15, count 2 2006.162.07:34:43.82#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:34:43.82#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:34:43.82#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.162.07:34:43.82#ibcon#ireg 7 cls_cnt 0 2006.162.07:34:43.82#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:34:43.94#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:34:43.94#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:34:43.94#ibcon#enter wrdev, iclass 15, count 0 2006.162.07:34:43.94#ibcon#first serial, iclass 15, count 0 2006.162.07:34:43.94#ibcon#enter sib2, iclass 15, count 0 2006.162.07:34:43.94#ibcon#flushed, iclass 15, count 0 2006.162.07:34:43.94#ibcon#about to write, iclass 15, count 0 2006.162.07:34:43.94#ibcon#wrote, iclass 15, count 0 2006.162.07:34:43.94#ibcon#about to read 3, iclass 15, count 0 2006.162.07:34:43.96#ibcon#read 3, iclass 15, count 0 2006.162.07:34:43.96#ibcon#about to read 4, iclass 15, count 0 2006.162.07:34:43.96#ibcon#read 4, iclass 15, count 0 2006.162.07:34:43.96#ibcon#about to read 5, iclass 15, count 0 2006.162.07:34:43.96#ibcon#read 5, iclass 15, count 0 2006.162.07:34:43.96#ibcon#about to read 6, iclass 15, count 0 2006.162.07:34:43.96#ibcon#read 6, iclass 15, count 0 2006.162.07:34:43.96#ibcon#end of sib2, iclass 15, count 0 2006.162.07:34:43.96#ibcon#*mode == 0, iclass 15, count 0 2006.162.07:34:43.96#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.162.07:34:43.96#ibcon#[27=USB\r\n] 2006.162.07:34:43.96#ibcon#*before write, iclass 15, count 0 2006.162.07:34:43.96#ibcon#enter sib2, iclass 15, count 0 2006.162.07:34:43.96#ibcon#flushed, iclass 15, count 0 2006.162.07:34:43.96#ibcon#about to write, iclass 15, count 0 2006.162.07:34:43.96#ibcon#wrote, iclass 15, count 0 2006.162.07:34:43.96#ibcon#about to read 3, iclass 15, count 0 2006.162.07:34:43.99#ibcon#read 3, iclass 15, count 0 2006.162.07:34:43.99#ibcon#about to read 4, iclass 15, count 0 2006.162.07:34:43.99#ibcon#read 4, iclass 15, count 0 2006.162.07:34:43.99#ibcon#about to read 5, iclass 15, count 0 2006.162.07:34:43.99#ibcon#read 5, iclass 15, count 0 2006.162.07:34:43.99#ibcon#about to read 6, iclass 15, count 0 2006.162.07:34:43.99#ibcon#read 6, iclass 15, count 0 2006.162.07:34:43.99#ibcon#end of sib2, iclass 15, count 0 2006.162.07:34:43.99#ibcon#*after write, iclass 15, count 0 2006.162.07:34:43.99#ibcon#*before return 0, iclass 15, count 0 2006.162.07:34:43.99#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:34:43.99#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:34:43.99#ibcon#about to clear, iclass 15 cls_cnt 0 2006.162.07:34:43.99#ibcon#cleared, iclass 15 cls_cnt 0 2006.162.07:34:43.99$vc4f8/vblo=6,752.99 2006.162.07:34:43.99#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.162.07:34:43.99#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.162.07:34:43.99#ibcon#ireg 17 cls_cnt 0 2006.162.07:34:43.99#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:34:43.99#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:34:43.99#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:34:43.99#ibcon#enter wrdev, iclass 17, count 0 2006.162.07:34:43.99#ibcon#first serial, iclass 17, count 0 2006.162.07:34:43.99#ibcon#enter sib2, iclass 17, count 0 2006.162.07:34:43.99#ibcon#flushed, iclass 17, count 0 2006.162.07:34:43.99#ibcon#about to write, iclass 17, count 0 2006.162.07:34:43.99#ibcon#wrote, iclass 17, count 0 2006.162.07:34:43.99#ibcon#about to read 3, iclass 17, count 0 2006.162.07:34:44.01#ibcon#read 3, iclass 17, count 0 2006.162.07:34:44.01#ibcon#about to read 4, iclass 17, count 0 2006.162.07:34:44.01#ibcon#read 4, iclass 17, count 0 2006.162.07:34:44.01#ibcon#about to read 5, iclass 17, count 0 2006.162.07:34:44.01#ibcon#read 5, iclass 17, count 0 2006.162.07:34:44.01#ibcon#about to read 6, iclass 17, count 0 2006.162.07:34:44.01#ibcon#read 6, iclass 17, count 0 2006.162.07:34:44.01#ibcon#end of sib2, iclass 17, count 0 2006.162.07:34:44.01#ibcon#*mode == 0, iclass 17, count 0 2006.162.07:34:44.01#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.162.07:34:44.01#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.07:34:44.01#ibcon#*before write, iclass 17, count 0 2006.162.07:34:44.01#ibcon#enter sib2, iclass 17, count 0 2006.162.07:34:44.01#ibcon#flushed, iclass 17, count 0 2006.162.07:34:44.01#ibcon#about to write, iclass 17, count 0 2006.162.07:34:44.01#ibcon#wrote, iclass 17, count 0 2006.162.07:34:44.01#ibcon#about to read 3, iclass 17, count 0 2006.162.07:34:44.05#ibcon#read 3, iclass 17, count 0 2006.162.07:34:44.05#ibcon#about to read 4, iclass 17, count 0 2006.162.07:34:44.05#ibcon#read 4, iclass 17, count 0 2006.162.07:34:44.05#ibcon#about to read 5, iclass 17, count 0 2006.162.07:34:44.05#ibcon#read 5, iclass 17, count 0 2006.162.07:34:44.05#ibcon#about to read 6, iclass 17, count 0 2006.162.07:34:44.05#ibcon#read 6, iclass 17, count 0 2006.162.07:34:44.05#ibcon#end of sib2, iclass 17, count 0 2006.162.07:34:44.05#ibcon#*after write, iclass 17, count 0 2006.162.07:34:44.05#ibcon#*before return 0, iclass 17, count 0 2006.162.07:34:44.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:34:44.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:34:44.05#ibcon#about to clear, iclass 17 cls_cnt 0 2006.162.07:34:44.05#ibcon#cleared, iclass 17 cls_cnt 0 2006.162.07:34:44.05$vc4f8/vb=6,4 2006.162.07:34:44.05#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.162.07:34:44.05#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.162.07:34:44.05#ibcon#ireg 11 cls_cnt 2 2006.162.07:34:44.05#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:34:44.11#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:34:44.11#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:34:44.11#ibcon#enter wrdev, iclass 19, count 2 2006.162.07:34:44.11#ibcon#first serial, iclass 19, count 2 2006.162.07:34:44.11#ibcon#enter sib2, iclass 19, count 2 2006.162.07:34:44.11#ibcon#flushed, iclass 19, count 2 2006.162.07:34:44.11#ibcon#about to write, iclass 19, count 2 2006.162.07:34:44.11#ibcon#wrote, iclass 19, count 2 2006.162.07:34:44.11#ibcon#about to read 3, iclass 19, count 2 2006.162.07:34:44.13#ibcon#read 3, iclass 19, count 2 2006.162.07:34:44.13#ibcon#about to read 4, iclass 19, count 2 2006.162.07:34:44.13#ibcon#read 4, iclass 19, count 2 2006.162.07:34:44.13#ibcon#about to read 5, iclass 19, count 2 2006.162.07:34:44.13#ibcon#read 5, iclass 19, count 2 2006.162.07:34:44.13#ibcon#about to read 6, iclass 19, count 2 2006.162.07:34:44.13#ibcon#read 6, iclass 19, count 2 2006.162.07:34:44.13#ibcon#end of sib2, iclass 19, count 2 2006.162.07:34:44.13#ibcon#*mode == 0, iclass 19, count 2 2006.162.07:34:44.13#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.162.07:34:44.13#ibcon#[27=AT06-04\r\n] 2006.162.07:34:44.13#ibcon#*before write, iclass 19, count 2 2006.162.07:34:44.13#ibcon#enter sib2, iclass 19, count 2 2006.162.07:34:44.13#ibcon#flushed, iclass 19, count 2 2006.162.07:34:44.13#ibcon#about to write, iclass 19, count 2 2006.162.07:34:44.13#ibcon#wrote, iclass 19, count 2 2006.162.07:34:44.13#ibcon#about to read 3, iclass 19, count 2 2006.162.07:34:44.16#ibcon#read 3, iclass 19, count 2 2006.162.07:34:44.16#ibcon#about to read 4, iclass 19, count 2 2006.162.07:34:44.16#ibcon#read 4, iclass 19, count 2 2006.162.07:34:44.16#ibcon#about to read 5, iclass 19, count 2 2006.162.07:34:44.16#ibcon#read 5, iclass 19, count 2 2006.162.07:34:44.16#ibcon#about to read 6, iclass 19, count 2 2006.162.07:34:44.16#ibcon#read 6, iclass 19, count 2 2006.162.07:34:44.16#ibcon#end of sib2, iclass 19, count 2 2006.162.07:34:44.16#ibcon#*after write, iclass 19, count 2 2006.162.07:34:44.16#ibcon#*before return 0, iclass 19, count 2 2006.162.07:34:44.16#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:34:44.16#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:34:44.16#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.162.07:34:44.16#ibcon#ireg 7 cls_cnt 0 2006.162.07:34:44.16#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:34:44.28#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:34:44.28#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:34:44.28#ibcon#enter wrdev, iclass 19, count 0 2006.162.07:34:44.28#ibcon#first serial, iclass 19, count 0 2006.162.07:34:44.28#ibcon#enter sib2, iclass 19, count 0 2006.162.07:34:44.28#ibcon#flushed, iclass 19, count 0 2006.162.07:34:44.28#ibcon#about to write, iclass 19, count 0 2006.162.07:34:44.28#ibcon#wrote, iclass 19, count 0 2006.162.07:34:44.28#ibcon#about to read 3, iclass 19, count 0 2006.162.07:34:44.30#ibcon#read 3, iclass 19, count 0 2006.162.07:34:44.30#ibcon#about to read 4, iclass 19, count 0 2006.162.07:34:44.30#ibcon#read 4, iclass 19, count 0 2006.162.07:34:44.30#ibcon#about to read 5, iclass 19, count 0 2006.162.07:34:44.30#ibcon#read 5, iclass 19, count 0 2006.162.07:34:44.30#ibcon#about to read 6, iclass 19, count 0 2006.162.07:34:44.30#ibcon#read 6, iclass 19, count 0 2006.162.07:34:44.30#ibcon#end of sib2, iclass 19, count 0 2006.162.07:34:44.30#ibcon#*mode == 0, iclass 19, count 0 2006.162.07:34:44.30#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.162.07:34:44.30#ibcon#[27=USB\r\n] 2006.162.07:34:44.30#ibcon#*before write, iclass 19, count 0 2006.162.07:34:44.30#ibcon#enter sib2, iclass 19, count 0 2006.162.07:34:44.30#ibcon#flushed, iclass 19, count 0 2006.162.07:34:44.30#ibcon#about to write, iclass 19, count 0 2006.162.07:34:44.30#ibcon#wrote, iclass 19, count 0 2006.162.07:34:44.30#ibcon#about to read 3, iclass 19, count 0 2006.162.07:34:44.33#ibcon#read 3, iclass 19, count 0 2006.162.07:34:44.33#ibcon#about to read 4, iclass 19, count 0 2006.162.07:34:44.33#ibcon#read 4, iclass 19, count 0 2006.162.07:34:44.33#ibcon#about to read 5, iclass 19, count 0 2006.162.07:34:44.33#ibcon#read 5, iclass 19, count 0 2006.162.07:34:44.33#ibcon#about to read 6, iclass 19, count 0 2006.162.07:34:44.33#ibcon#read 6, iclass 19, count 0 2006.162.07:34:44.33#ibcon#end of sib2, iclass 19, count 0 2006.162.07:34:44.33#ibcon#*after write, iclass 19, count 0 2006.162.07:34:44.33#ibcon#*before return 0, iclass 19, count 0 2006.162.07:34:44.33#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:34:44.33#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:34:44.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.162.07:34:44.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.162.07:34:44.33$vc4f8/vabw=wide 2006.162.07:34:44.33#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.162.07:34:44.33#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.162.07:34:44.33#ibcon#ireg 8 cls_cnt 0 2006.162.07:34:44.33#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:34:44.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:34:44.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:34:44.33#ibcon#enter wrdev, iclass 21, count 0 2006.162.07:34:44.33#ibcon#first serial, iclass 21, count 0 2006.162.07:34:44.33#ibcon#enter sib2, iclass 21, count 0 2006.162.07:34:44.33#ibcon#flushed, iclass 21, count 0 2006.162.07:34:44.33#ibcon#about to write, iclass 21, count 0 2006.162.07:34:44.33#ibcon#wrote, iclass 21, count 0 2006.162.07:34:44.33#ibcon#about to read 3, iclass 21, count 0 2006.162.07:34:44.35#ibcon#read 3, iclass 21, count 0 2006.162.07:34:44.35#ibcon#about to read 4, iclass 21, count 0 2006.162.07:34:44.35#ibcon#read 4, iclass 21, count 0 2006.162.07:34:44.35#ibcon#about to read 5, iclass 21, count 0 2006.162.07:34:44.35#ibcon#read 5, iclass 21, count 0 2006.162.07:34:44.35#ibcon#about to read 6, iclass 21, count 0 2006.162.07:34:44.35#ibcon#read 6, iclass 21, count 0 2006.162.07:34:44.35#ibcon#end of sib2, iclass 21, count 0 2006.162.07:34:44.35#ibcon#*mode == 0, iclass 21, count 0 2006.162.07:34:44.35#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.162.07:34:44.35#ibcon#[25=BW32\r\n] 2006.162.07:34:44.35#ibcon#*before write, iclass 21, count 0 2006.162.07:34:44.35#ibcon#enter sib2, iclass 21, count 0 2006.162.07:34:44.35#ibcon#flushed, iclass 21, count 0 2006.162.07:34:44.35#ibcon#about to write, iclass 21, count 0 2006.162.07:34:44.35#ibcon#wrote, iclass 21, count 0 2006.162.07:34:44.35#ibcon#about to read 3, iclass 21, count 0 2006.162.07:34:44.38#ibcon#read 3, iclass 21, count 0 2006.162.07:34:44.38#ibcon#about to read 4, iclass 21, count 0 2006.162.07:34:44.38#ibcon#read 4, iclass 21, count 0 2006.162.07:34:44.38#ibcon#about to read 5, iclass 21, count 0 2006.162.07:34:44.38#ibcon#read 5, iclass 21, count 0 2006.162.07:34:44.38#ibcon#about to read 6, iclass 21, count 0 2006.162.07:34:44.38#ibcon#read 6, iclass 21, count 0 2006.162.07:34:44.38#ibcon#end of sib2, iclass 21, count 0 2006.162.07:34:44.38#ibcon#*after write, iclass 21, count 0 2006.162.07:34:44.38#ibcon#*before return 0, iclass 21, count 0 2006.162.07:34:44.38#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:34:44.38#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:34:44.38#ibcon#about to clear, iclass 21 cls_cnt 0 2006.162.07:34:44.38#ibcon#cleared, iclass 21 cls_cnt 0 2006.162.07:34:44.38$vc4f8/vbbw=wide 2006.162.07:34:44.38#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.162.07:34:44.38#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.162.07:34:44.38#ibcon#ireg 8 cls_cnt 0 2006.162.07:34:44.38#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:34:44.45#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:34:44.45#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:34:44.45#ibcon#enter wrdev, iclass 23, count 0 2006.162.07:34:44.45#ibcon#first serial, iclass 23, count 0 2006.162.07:34:44.45#ibcon#enter sib2, iclass 23, count 0 2006.162.07:34:44.45#ibcon#flushed, iclass 23, count 0 2006.162.07:34:44.45#ibcon#about to write, iclass 23, count 0 2006.162.07:34:44.45#ibcon#wrote, iclass 23, count 0 2006.162.07:34:44.45#ibcon#about to read 3, iclass 23, count 0 2006.162.07:34:44.47#ibcon#read 3, iclass 23, count 0 2006.162.07:34:44.47#ibcon#about to read 4, iclass 23, count 0 2006.162.07:34:44.47#ibcon#read 4, iclass 23, count 0 2006.162.07:34:44.47#ibcon#about to read 5, iclass 23, count 0 2006.162.07:34:44.47#ibcon#read 5, iclass 23, count 0 2006.162.07:34:44.47#ibcon#about to read 6, iclass 23, count 0 2006.162.07:34:44.47#ibcon#read 6, iclass 23, count 0 2006.162.07:34:44.47#ibcon#end of sib2, iclass 23, count 0 2006.162.07:34:44.47#ibcon#*mode == 0, iclass 23, count 0 2006.162.07:34:44.47#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.162.07:34:44.47#ibcon#[27=BW32\r\n] 2006.162.07:34:44.47#ibcon#*before write, iclass 23, count 0 2006.162.07:34:44.47#ibcon#enter sib2, iclass 23, count 0 2006.162.07:34:44.47#ibcon#flushed, iclass 23, count 0 2006.162.07:34:44.47#ibcon#about to write, iclass 23, count 0 2006.162.07:34:44.47#ibcon#wrote, iclass 23, count 0 2006.162.07:34:44.47#ibcon#about to read 3, iclass 23, count 0 2006.162.07:34:44.50#ibcon#read 3, iclass 23, count 0 2006.162.07:34:44.50#ibcon#about to read 4, iclass 23, count 0 2006.162.07:34:44.50#ibcon#read 4, iclass 23, count 0 2006.162.07:34:44.50#ibcon#about to read 5, iclass 23, count 0 2006.162.07:34:44.50#ibcon#read 5, iclass 23, count 0 2006.162.07:34:44.50#ibcon#about to read 6, iclass 23, count 0 2006.162.07:34:44.50#ibcon#read 6, iclass 23, count 0 2006.162.07:34:44.50#ibcon#end of sib2, iclass 23, count 0 2006.162.07:34:44.50#ibcon#*after write, iclass 23, count 0 2006.162.07:34:44.50#ibcon#*before return 0, iclass 23, count 0 2006.162.07:34:44.50#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:34:44.50#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:34:44.50#ibcon#about to clear, iclass 23 cls_cnt 0 2006.162.07:34:44.50#ibcon#cleared, iclass 23 cls_cnt 0 2006.162.07:34:44.50$4f8m12a/ifd4f 2006.162.07:34:44.50$ifd4f/lo= 2006.162.07:34:44.50$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.07:34:44.50$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.07:34:44.50$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.07:34:44.50$ifd4f/patch= 2006.162.07:34:44.50$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.07:34:44.50$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.07:34:44.50$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.07:34:44.50$4f8m12a/"form=m,16.000,1:2 2006.162.07:34:44.50$4f8m12a/"tpicd 2006.162.07:34:44.50$4f8m12a/echo=off 2006.162.07:34:44.50$4f8m12a/xlog=off 2006.162.07:34:44.50:!2006.162.07:35:20 2006.162.07:35:00.14#trakl#Source acquired 2006.162.07:35:01.14#flagr#flagr/antenna,acquired 2006.162.07:35:20.00:preob 2006.162.07:35:20.14/onsource/TRACKING 2006.162.07:35:20.14:!2006.162.07:35:30 2006.162.07:35:30.00:data_valid=on 2006.162.07:35:30.00:midob 2006.162.07:35:31.14/onsource/TRACKING 2006.162.07:35:31.14/wx/17.89,1007.1,100 2006.162.07:35:31.25/cable/+6.5352E-03 2006.162.07:35:32.34/va/01,08,usb,yes,47,50 2006.162.07:35:32.34/va/02,07,usb,yes,48,50 2006.162.07:35:32.34/va/03,06,usb,yes,51,51 2006.162.07:35:32.34/va/04,07,usb,yes,49,53 2006.162.07:35:32.34/va/05,07,usb,yes,52,55 2006.162.07:35:32.34/va/06,06,usb,yes,52,51 2006.162.07:35:32.34/va/07,06,usb,yes,52,52 2006.162.07:35:32.34/va/08,07,usb,yes,50,49 2006.162.07:35:32.57/valo/01,532.99,yes,locked 2006.162.07:35:32.57/valo/02,572.99,yes,locked 2006.162.07:35:32.57/valo/03,672.99,yes,locked 2006.162.07:35:32.57/valo/04,832.99,yes,locked 2006.162.07:35:32.57/valo/05,652.99,yes,locked 2006.162.07:35:32.57/valo/06,772.99,yes,locked 2006.162.07:35:32.57/valo/07,832.99,yes,locked 2006.162.07:35:32.57/valo/08,852.99,yes,locked 2006.162.07:35:33.66/vb/01,04,usb,yes,30,29 2006.162.07:35:33.66/vb/02,04,usb,yes,31,34 2006.162.07:35:33.66/vb/03,04,usb,yes,28,31 2006.162.07:35:33.66/vb/04,04,usb,yes,29,29 2006.162.07:35:33.66/vb/05,04,usb,yes,27,31 2006.162.07:35:33.66/vb/06,04,usb,yes,28,31 2006.162.07:35:33.66/vb/07,04,usb,yes,30,30 2006.162.07:35:33.66/vb/08,04,usb,yes,28,31 2006.162.07:35:33.89/vblo/01,632.99,yes,locked 2006.162.07:35:33.89/vblo/02,640.99,yes,locked 2006.162.07:35:33.89/vblo/03,656.99,yes,locked 2006.162.07:35:33.89/vblo/04,712.99,yes,locked 2006.162.07:35:33.89/vblo/05,744.99,yes,locked 2006.162.07:35:33.89/vblo/06,752.99,yes,locked 2006.162.07:35:33.89/vblo/07,734.99,yes,locked 2006.162.07:35:33.89/vblo/08,744.99,yes,locked 2006.162.07:35:34.04/vabw/8 2006.162.07:35:34.19/vbbw/8 2006.162.07:35:34.28/xfe/off,on,15.2 2006.162.07:35:34.66/ifatt/23,28,28,28 2006.162.07:35:35.07/fmout-gps/S +4.50E-07 2006.162.07:35:35.15:!2006.162.07:37:10 2006.162.07:37:10.00:data_valid=off 2006.162.07:37:10.00:postob 2006.162.07:37:10.17/cable/+6.5357E-03 2006.162.07:37:10.17/wx/17.89,1007.2,100 2006.162.07:37:11.07/fmout-gps/S +4.49E-07 2006.162.07:37:11.07:scan_name=162-0738,k06162,60 2006.162.07:37:11.08:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.162.07:37:12.14#flagr#flagr/antenna,new-source 2006.162.07:37:12.14:checkk5 2006.162.07:37:12.57/chk_autoobs//k5ts1/ autoobs is running! 2006.162.07:37:13.00/chk_autoobs//k5ts2/ autoobs is running! 2006.162.07:37:13.42/chk_autoobs//k5ts3/ autoobs is running! 2006.162.07:37:13.86/chk_autoobs//k5ts4/ autoobs is running! 2006.162.07:37:14.29/chk_obsdata//k5ts1/T1620735??a.dat file size is correct (nominal:800MB, actual:792MB). 2006.162.07:37:14.70/chk_obsdata//k5ts2/T1620735??b.dat file size is correct (nominal:800MB, actual:792MB). 2006.162.07:37:15.10/chk_obsdata//k5ts3/T1620735??c.dat file size is correct (nominal:800MB, actual:792MB). 2006.162.07:37:15.55/chk_obsdata//k5ts4/T1620735??d.dat file size is correct (nominal:800MB, actual:792MB). 2006.162.07:37:16.31/k5log//k5ts1_log_newline 2006.162.07:37:17.06/k5log//k5ts2_log_newline 2006.162.07:37:18.15/k5log//k5ts3_log_newline 2006.162.07:37:19.17/k5log//k5ts4_log_newline 2006.162.07:37:19.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.07:37:19.23:4f8m12a=1 2006.162.07:37:19.23$4f8m12a/echo=on 2006.162.07:37:19.23$4f8m12a/pcalon 2006.162.07:37:19.23$pcalon/"no phase cal control is implemented here 2006.162.07:37:19.23$4f8m12a/"tpicd=stop 2006.162.07:37:19.23$4f8m12a/vc4f8 2006.162.07:37:19.23$vc4f8/valo=1,532.99 2006.162.07:37:19.24#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.162.07:37:19.24#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.162.07:37:19.24#ibcon#ireg 17 cls_cnt 0 2006.162.07:37:19.24#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.07:37:19.24#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.07:37:19.24#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.07:37:19.24#ibcon#enter wrdev, iclass 14, count 0 2006.162.07:37:19.24#ibcon#first serial, iclass 14, count 0 2006.162.07:37:19.24#ibcon#enter sib2, iclass 14, count 0 2006.162.07:37:19.24#ibcon#flushed, iclass 14, count 0 2006.162.07:37:19.24#ibcon#about to write, iclass 14, count 0 2006.162.07:37:19.24#ibcon#wrote, iclass 14, count 0 2006.162.07:37:19.24#ibcon#about to read 3, iclass 14, count 0 2006.162.07:37:19.26#ibcon#read 3, iclass 14, count 0 2006.162.07:37:19.26#ibcon#about to read 4, iclass 14, count 0 2006.162.07:37:19.26#ibcon#read 4, iclass 14, count 0 2006.162.07:37:19.26#ibcon#about to read 5, iclass 14, count 0 2006.162.07:37:19.26#ibcon#read 5, iclass 14, count 0 2006.162.07:37:19.26#ibcon#about to read 6, iclass 14, count 0 2006.162.07:37:19.26#ibcon#read 6, iclass 14, count 0 2006.162.07:37:19.26#ibcon#end of sib2, iclass 14, count 0 2006.162.07:37:19.26#ibcon#*mode == 0, iclass 14, count 0 2006.162.07:37:19.26#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.07:37:19.26#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.07:37:19.26#ibcon#*before write, iclass 14, count 0 2006.162.07:37:19.26#ibcon#enter sib2, iclass 14, count 0 2006.162.07:37:19.26#ibcon#flushed, iclass 14, count 0 2006.162.07:37:19.26#ibcon#about to write, iclass 14, count 0 2006.162.07:37:19.26#ibcon#wrote, iclass 14, count 0 2006.162.07:37:19.26#ibcon#about to read 3, iclass 14, count 0 2006.162.07:37:19.31#ibcon#read 3, iclass 14, count 0 2006.162.07:37:19.31#ibcon#about to read 4, iclass 14, count 0 2006.162.07:37:19.31#ibcon#read 4, iclass 14, count 0 2006.162.07:37:19.31#ibcon#about to read 5, iclass 14, count 0 2006.162.07:37:19.31#ibcon#read 5, iclass 14, count 0 2006.162.07:37:19.31#ibcon#about to read 6, iclass 14, count 0 2006.162.07:37:19.31#ibcon#read 6, iclass 14, count 0 2006.162.07:37:19.31#ibcon#end of sib2, iclass 14, count 0 2006.162.07:37:19.31#ibcon#*after write, iclass 14, count 0 2006.162.07:37:19.31#ibcon#*before return 0, iclass 14, count 0 2006.162.07:37:19.31#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.07:37:19.31#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.162.07:37:19.31#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.07:37:19.31#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.07:37:19.31$vc4f8/va=1,8 2006.162.07:37:19.31#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.162.07:37:19.31#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.162.07:37:19.31#ibcon#ireg 11 cls_cnt 2 2006.162.07:37:19.31#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.162.07:37:19.31#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.162.07:37:19.31#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.162.07:37:19.31#ibcon#enter wrdev, iclass 16, count 2 2006.162.07:37:19.31#ibcon#first serial, iclass 16, count 2 2006.162.07:37:19.31#ibcon#enter sib2, iclass 16, count 2 2006.162.07:37:19.31#ibcon#flushed, iclass 16, count 2 2006.162.07:37:19.31#ibcon#about to write, iclass 16, count 2 2006.162.07:37:19.32#ibcon#wrote, iclass 16, count 2 2006.162.07:37:19.32#ibcon#about to read 3, iclass 16, count 2 2006.162.07:37:19.33#ibcon#read 3, iclass 16, count 2 2006.162.07:37:19.33#ibcon#about to read 4, iclass 16, count 2 2006.162.07:37:19.33#ibcon#read 4, iclass 16, count 2 2006.162.07:37:19.33#ibcon#about to read 5, iclass 16, count 2 2006.162.07:37:19.33#ibcon#read 5, iclass 16, count 2 2006.162.07:37:19.33#ibcon#about to read 6, iclass 16, count 2 2006.162.07:37:19.33#ibcon#read 6, iclass 16, count 2 2006.162.07:37:19.33#ibcon#end of sib2, iclass 16, count 2 2006.162.07:37:19.33#ibcon#*mode == 0, iclass 16, count 2 2006.162.07:37:19.33#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.162.07:37:19.33#ibcon#[25=AT01-08\r\n] 2006.162.07:37:19.33#ibcon#*before write, iclass 16, count 2 2006.162.07:37:19.33#ibcon#enter sib2, iclass 16, count 2 2006.162.07:37:19.33#ibcon#flushed, iclass 16, count 2 2006.162.07:37:19.33#ibcon#about to write, iclass 16, count 2 2006.162.07:37:19.33#ibcon#wrote, iclass 16, count 2 2006.162.07:37:19.33#ibcon#about to read 3, iclass 16, count 2 2006.162.07:37:19.36#ibcon#read 3, iclass 16, count 2 2006.162.07:37:19.36#ibcon#about to read 4, iclass 16, count 2 2006.162.07:37:19.36#ibcon#read 4, iclass 16, count 2 2006.162.07:37:19.36#ibcon#about to read 5, iclass 16, count 2 2006.162.07:37:19.36#ibcon#read 5, iclass 16, count 2 2006.162.07:37:19.36#ibcon#about to read 6, iclass 16, count 2 2006.162.07:37:19.36#ibcon#read 6, iclass 16, count 2 2006.162.07:37:19.36#ibcon#end of sib2, iclass 16, count 2 2006.162.07:37:19.36#ibcon#*after write, iclass 16, count 2 2006.162.07:37:19.36#ibcon#*before return 0, iclass 16, count 2 2006.162.07:37:19.36#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.162.07:37:19.36#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.162.07:37:19.36#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.162.07:37:19.36#ibcon#ireg 7 cls_cnt 0 2006.162.07:37:19.36#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.162.07:37:19.48#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.162.07:37:19.48#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.162.07:37:19.48#ibcon#enter wrdev, iclass 16, count 0 2006.162.07:37:19.48#ibcon#first serial, iclass 16, count 0 2006.162.07:37:19.48#ibcon#enter sib2, iclass 16, count 0 2006.162.07:37:19.48#ibcon#flushed, iclass 16, count 0 2006.162.07:37:19.48#ibcon#about to write, iclass 16, count 0 2006.162.07:37:19.48#ibcon#wrote, iclass 16, count 0 2006.162.07:37:19.48#ibcon#about to read 3, iclass 16, count 0 2006.162.07:37:19.50#ibcon#read 3, iclass 16, count 0 2006.162.07:37:19.50#ibcon#about to read 4, iclass 16, count 0 2006.162.07:37:19.50#ibcon#read 4, iclass 16, count 0 2006.162.07:37:19.50#ibcon#about to read 5, iclass 16, count 0 2006.162.07:37:19.50#ibcon#read 5, iclass 16, count 0 2006.162.07:37:19.50#ibcon#about to read 6, iclass 16, count 0 2006.162.07:37:19.50#ibcon#read 6, iclass 16, count 0 2006.162.07:37:19.50#ibcon#end of sib2, iclass 16, count 0 2006.162.07:37:19.50#ibcon#*mode == 0, iclass 16, count 0 2006.162.07:37:19.50#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.162.07:37:19.50#ibcon#[25=USB\r\n] 2006.162.07:37:19.50#ibcon#*before write, iclass 16, count 0 2006.162.07:37:19.50#ibcon#enter sib2, iclass 16, count 0 2006.162.07:37:19.50#ibcon#flushed, iclass 16, count 0 2006.162.07:37:19.50#ibcon#about to write, iclass 16, count 0 2006.162.07:37:19.50#ibcon#wrote, iclass 16, count 0 2006.162.07:37:19.50#ibcon#about to read 3, iclass 16, count 0 2006.162.07:37:19.53#ibcon#read 3, iclass 16, count 0 2006.162.07:37:19.53#ibcon#about to read 4, iclass 16, count 0 2006.162.07:37:19.53#ibcon#read 4, iclass 16, count 0 2006.162.07:37:19.53#ibcon#about to read 5, iclass 16, count 0 2006.162.07:37:19.53#ibcon#read 5, iclass 16, count 0 2006.162.07:37:19.53#ibcon#about to read 6, iclass 16, count 0 2006.162.07:37:19.53#ibcon#read 6, iclass 16, count 0 2006.162.07:37:19.53#ibcon#end of sib2, iclass 16, count 0 2006.162.07:37:19.53#ibcon#*after write, iclass 16, count 0 2006.162.07:37:19.53#ibcon#*before return 0, iclass 16, count 0 2006.162.07:37:19.53#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.162.07:37:19.53#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.162.07:37:19.53#ibcon#about to clear, iclass 16 cls_cnt 0 2006.162.07:37:19.53#ibcon#cleared, iclass 16 cls_cnt 0 2006.162.07:37:19.53$vc4f8/valo=2,572.99 2006.162.07:37:19.53#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.162.07:37:19.53#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.162.07:37:19.53#ibcon#ireg 17 cls_cnt 0 2006.162.07:37:19.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:37:19.53#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:37:19.53#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:37:19.53#ibcon#enter wrdev, iclass 18, count 0 2006.162.07:37:19.53#ibcon#first serial, iclass 18, count 0 2006.162.07:37:19.53#ibcon#enter sib2, iclass 18, count 0 2006.162.07:37:19.53#ibcon#flushed, iclass 18, count 0 2006.162.07:37:19.53#ibcon#about to write, iclass 18, count 0 2006.162.07:37:19.53#ibcon#wrote, iclass 18, count 0 2006.162.07:37:19.53#ibcon#about to read 3, iclass 18, count 0 2006.162.07:37:19.55#ibcon#read 3, iclass 18, count 0 2006.162.07:37:19.55#ibcon#about to read 4, iclass 18, count 0 2006.162.07:37:19.55#ibcon#read 4, iclass 18, count 0 2006.162.07:37:19.55#ibcon#about to read 5, iclass 18, count 0 2006.162.07:37:19.55#ibcon#read 5, iclass 18, count 0 2006.162.07:37:19.55#ibcon#about to read 6, iclass 18, count 0 2006.162.07:37:19.55#ibcon#read 6, iclass 18, count 0 2006.162.07:37:19.55#ibcon#end of sib2, iclass 18, count 0 2006.162.07:37:19.55#ibcon#*mode == 0, iclass 18, count 0 2006.162.07:37:19.55#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.162.07:37:19.55#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.07:37:19.55#ibcon#*before write, iclass 18, count 0 2006.162.07:37:19.55#ibcon#enter sib2, iclass 18, count 0 2006.162.07:37:19.55#ibcon#flushed, iclass 18, count 0 2006.162.07:37:19.55#ibcon#about to write, iclass 18, count 0 2006.162.07:37:19.55#ibcon#wrote, iclass 18, count 0 2006.162.07:37:19.55#ibcon#about to read 3, iclass 18, count 0 2006.162.07:37:19.59#ibcon#read 3, iclass 18, count 0 2006.162.07:37:19.59#ibcon#about to read 4, iclass 18, count 0 2006.162.07:37:19.59#ibcon#read 4, iclass 18, count 0 2006.162.07:37:19.59#ibcon#about to read 5, iclass 18, count 0 2006.162.07:37:19.59#ibcon#read 5, iclass 18, count 0 2006.162.07:37:19.59#ibcon#about to read 6, iclass 18, count 0 2006.162.07:37:19.59#ibcon#read 6, iclass 18, count 0 2006.162.07:37:19.59#ibcon#end of sib2, iclass 18, count 0 2006.162.07:37:19.59#ibcon#*after write, iclass 18, count 0 2006.162.07:37:19.59#ibcon#*before return 0, iclass 18, count 0 2006.162.07:37:19.59#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:37:19.59#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:37:19.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.162.07:37:19.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.162.07:37:19.59$vc4f8/va=2,7 2006.162.07:37:19.59#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.162.07:37:19.59#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.162.07:37:19.59#ibcon#ireg 11 cls_cnt 2 2006.162.07:37:19.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:37:19.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:37:19.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:37:19.66#ibcon#enter wrdev, iclass 20, count 2 2006.162.07:37:19.66#ibcon#first serial, iclass 20, count 2 2006.162.07:37:19.66#ibcon#enter sib2, iclass 20, count 2 2006.162.07:37:19.66#ibcon#flushed, iclass 20, count 2 2006.162.07:37:19.66#ibcon#about to write, iclass 20, count 2 2006.162.07:37:19.66#ibcon#wrote, iclass 20, count 2 2006.162.07:37:19.66#ibcon#about to read 3, iclass 20, count 2 2006.162.07:37:19.67#ibcon#read 3, iclass 20, count 2 2006.162.07:37:19.67#ibcon#about to read 4, iclass 20, count 2 2006.162.07:37:19.67#ibcon#read 4, iclass 20, count 2 2006.162.07:37:19.67#ibcon#about to read 5, iclass 20, count 2 2006.162.07:37:19.67#ibcon#read 5, iclass 20, count 2 2006.162.07:37:19.67#ibcon#about to read 6, iclass 20, count 2 2006.162.07:37:19.67#ibcon#read 6, iclass 20, count 2 2006.162.07:37:19.67#ibcon#end of sib2, iclass 20, count 2 2006.162.07:37:19.67#ibcon#*mode == 0, iclass 20, count 2 2006.162.07:37:19.67#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.162.07:37:19.67#ibcon#[25=AT02-07\r\n] 2006.162.07:37:19.67#ibcon#*before write, iclass 20, count 2 2006.162.07:37:19.67#ibcon#enter sib2, iclass 20, count 2 2006.162.07:37:19.67#ibcon#flushed, iclass 20, count 2 2006.162.07:37:19.67#ibcon#about to write, iclass 20, count 2 2006.162.07:37:19.67#ibcon#wrote, iclass 20, count 2 2006.162.07:37:19.67#ibcon#about to read 3, iclass 20, count 2 2006.162.07:37:19.70#ibcon#read 3, iclass 20, count 2 2006.162.07:37:19.70#ibcon#about to read 4, iclass 20, count 2 2006.162.07:37:19.70#ibcon#read 4, iclass 20, count 2 2006.162.07:37:19.70#ibcon#about to read 5, iclass 20, count 2 2006.162.07:37:19.70#ibcon#read 5, iclass 20, count 2 2006.162.07:37:19.70#ibcon#about to read 6, iclass 20, count 2 2006.162.07:37:19.70#ibcon#read 6, iclass 20, count 2 2006.162.07:37:19.70#ibcon#end of sib2, iclass 20, count 2 2006.162.07:37:19.70#ibcon#*after write, iclass 20, count 2 2006.162.07:37:19.70#ibcon#*before return 0, iclass 20, count 2 2006.162.07:37:19.70#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:37:19.70#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:37:19.70#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.162.07:37:19.70#ibcon#ireg 7 cls_cnt 0 2006.162.07:37:19.70#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:37:19.82#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:37:19.82#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:37:19.82#ibcon#enter wrdev, iclass 20, count 0 2006.162.07:37:19.82#ibcon#first serial, iclass 20, count 0 2006.162.07:37:19.82#ibcon#enter sib2, iclass 20, count 0 2006.162.07:37:19.82#ibcon#flushed, iclass 20, count 0 2006.162.07:37:19.82#ibcon#about to write, iclass 20, count 0 2006.162.07:37:19.82#ibcon#wrote, iclass 20, count 0 2006.162.07:37:19.82#ibcon#about to read 3, iclass 20, count 0 2006.162.07:37:19.84#ibcon#read 3, iclass 20, count 0 2006.162.07:37:19.84#ibcon#about to read 4, iclass 20, count 0 2006.162.07:37:19.84#ibcon#read 4, iclass 20, count 0 2006.162.07:37:19.84#ibcon#about to read 5, iclass 20, count 0 2006.162.07:37:19.84#ibcon#read 5, iclass 20, count 0 2006.162.07:37:19.84#ibcon#about to read 6, iclass 20, count 0 2006.162.07:37:19.84#ibcon#read 6, iclass 20, count 0 2006.162.07:37:19.84#ibcon#end of sib2, iclass 20, count 0 2006.162.07:37:19.84#ibcon#*mode == 0, iclass 20, count 0 2006.162.07:37:19.84#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.07:37:19.84#ibcon#[25=USB\r\n] 2006.162.07:37:19.84#ibcon#*before write, iclass 20, count 0 2006.162.07:37:19.84#ibcon#enter sib2, iclass 20, count 0 2006.162.07:37:19.84#ibcon#flushed, iclass 20, count 0 2006.162.07:37:19.84#ibcon#about to write, iclass 20, count 0 2006.162.07:37:19.84#ibcon#wrote, iclass 20, count 0 2006.162.07:37:19.84#ibcon#about to read 3, iclass 20, count 0 2006.162.07:37:19.87#ibcon#read 3, iclass 20, count 0 2006.162.07:37:19.87#ibcon#about to read 4, iclass 20, count 0 2006.162.07:37:19.87#ibcon#read 4, iclass 20, count 0 2006.162.07:37:19.87#ibcon#about to read 5, iclass 20, count 0 2006.162.07:37:19.87#ibcon#read 5, iclass 20, count 0 2006.162.07:37:19.87#ibcon#about to read 6, iclass 20, count 0 2006.162.07:37:19.87#ibcon#read 6, iclass 20, count 0 2006.162.07:37:19.87#ibcon#end of sib2, iclass 20, count 0 2006.162.07:37:19.87#ibcon#*after write, iclass 20, count 0 2006.162.07:37:19.87#ibcon#*before return 0, iclass 20, count 0 2006.162.07:37:19.87#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:37:19.87#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:37:19.87#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.07:37:19.87#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.07:37:19.87$vc4f8/valo=3,672.99 2006.162.07:37:19.87#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.162.07:37:19.87#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.162.07:37:19.87#ibcon#ireg 17 cls_cnt 0 2006.162.07:37:19.87#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:37:19.87#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:37:19.87#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:37:19.87#ibcon#enter wrdev, iclass 22, count 0 2006.162.07:37:19.87#ibcon#first serial, iclass 22, count 0 2006.162.07:37:19.87#ibcon#enter sib2, iclass 22, count 0 2006.162.07:37:19.87#ibcon#flushed, iclass 22, count 0 2006.162.07:37:19.87#ibcon#about to write, iclass 22, count 0 2006.162.07:37:19.87#ibcon#wrote, iclass 22, count 0 2006.162.07:37:19.87#ibcon#about to read 3, iclass 22, count 0 2006.162.07:37:19.89#ibcon#read 3, iclass 22, count 0 2006.162.07:37:19.89#ibcon#about to read 4, iclass 22, count 0 2006.162.07:37:19.89#ibcon#read 4, iclass 22, count 0 2006.162.07:37:19.89#ibcon#about to read 5, iclass 22, count 0 2006.162.07:37:19.89#ibcon#read 5, iclass 22, count 0 2006.162.07:37:19.89#ibcon#about to read 6, iclass 22, count 0 2006.162.07:37:19.89#ibcon#read 6, iclass 22, count 0 2006.162.07:37:19.89#ibcon#end of sib2, iclass 22, count 0 2006.162.07:37:19.89#ibcon#*mode == 0, iclass 22, count 0 2006.162.07:37:19.89#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.07:37:19.89#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.07:37:19.89#ibcon#*before write, iclass 22, count 0 2006.162.07:37:19.89#ibcon#enter sib2, iclass 22, count 0 2006.162.07:37:19.89#ibcon#flushed, iclass 22, count 0 2006.162.07:37:19.89#ibcon#about to write, iclass 22, count 0 2006.162.07:37:19.89#ibcon#wrote, iclass 22, count 0 2006.162.07:37:19.89#ibcon#about to read 3, iclass 22, count 0 2006.162.07:37:19.93#ibcon#read 3, iclass 22, count 0 2006.162.07:37:19.93#ibcon#about to read 4, iclass 22, count 0 2006.162.07:37:19.93#ibcon#read 4, iclass 22, count 0 2006.162.07:37:19.93#ibcon#about to read 5, iclass 22, count 0 2006.162.07:37:19.93#ibcon#read 5, iclass 22, count 0 2006.162.07:37:19.93#ibcon#about to read 6, iclass 22, count 0 2006.162.07:37:19.93#ibcon#read 6, iclass 22, count 0 2006.162.07:37:19.93#ibcon#end of sib2, iclass 22, count 0 2006.162.07:37:19.93#ibcon#*after write, iclass 22, count 0 2006.162.07:37:19.93#ibcon#*before return 0, iclass 22, count 0 2006.162.07:37:19.93#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:37:19.93#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:37:19.93#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.07:37:19.93#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.07:37:19.93$vc4f8/va=3,6 2006.162.07:37:19.93#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.162.07:37:19.93#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.162.07:37:19.93#ibcon#ireg 11 cls_cnt 2 2006.162.07:37:19.93#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:37:20.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:37:20.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:37:20.00#ibcon#enter wrdev, iclass 24, count 2 2006.162.07:37:20.00#ibcon#first serial, iclass 24, count 2 2006.162.07:37:20.00#ibcon#enter sib2, iclass 24, count 2 2006.162.07:37:20.00#ibcon#flushed, iclass 24, count 2 2006.162.07:37:20.00#ibcon#about to write, iclass 24, count 2 2006.162.07:37:20.00#ibcon#wrote, iclass 24, count 2 2006.162.07:37:20.00#ibcon#about to read 3, iclass 24, count 2 2006.162.07:37:20.01#ibcon#read 3, iclass 24, count 2 2006.162.07:37:20.01#ibcon#about to read 4, iclass 24, count 2 2006.162.07:37:20.01#ibcon#read 4, iclass 24, count 2 2006.162.07:37:20.01#ibcon#about to read 5, iclass 24, count 2 2006.162.07:37:20.01#ibcon#read 5, iclass 24, count 2 2006.162.07:37:20.01#ibcon#about to read 6, iclass 24, count 2 2006.162.07:37:20.01#ibcon#read 6, iclass 24, count 2 2006.162.07:37:20.01#ibcon#end of sib2, iclass 24, count 2 2006.162.07:37:20.01#ibcon#*mode == 0, iclass 24, count 2 2006.162.07:37:20.01#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.162.07:37:20.01#ibcon#[25=AT03-06\r\n] 2006.162.07:37:20.01#ibcon#*before write, iclass 24, count 2 2006.162.07:37:20.01#ibcon#enter sib2, iclass 24, count 2 2006.162.07:37:20.01#ibcon#flushed, iclass 24, count 2 2006.162.07:37:20.01#ibcon#about to write, iclass 24, count 2 2006.162.07:37:20.01#ibcon#wrote, iclass 24, count 2 2006.162.07:37:20.01#ibcon#about to read 3, iclass 24, count 2 2006.162.07:37:20.04#ibcon#read 3, iclass 24, count 2 2006.162.07:37:20.04#ibcon#about to read 4, iclass 24, count 2 2006.162.07:37:20.04#ibcon#read 4, iclass 24, count 2 2006.162.07:37:20.04#ibcon#about to read 5, iclass 24, count 2 2006.162.07:37:20.04#ibcon#read 5, iclass 24, count 2 2006.162.07:37:20.04#ibcon#about to read 6, iclass 24, count 2 2006.162.07:37:20.04#ibcon#read 6, iclass 24, count 2 2006.162.07:37:20.04#ibcon#end of sib2, iclass 24, count 2 2006.162.07:37:20.04#ibcon#*after write, iclass 24, count 2 2006.162.07:37:20.04#ibcon#*before return 0, iclass 24, count 2 2006.162.07:37:20.04#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:37:20.04#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:37:20.04#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.162.07:37:20.04#ibcon#ireg 7 cls_cnt 0 2006.162.07:37:20.04#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:37:20.16#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:37:20.16#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:37:20.16#ibcon#enter wrdev, iclass 24, count 0 2006.162.07:37:20.16#ibcon#first serial, iclass 24, count 0 2006.162.07:37:20.16#ibcon#enter sib2, iclass 24, count 0 2006.162.07:37:20.16#ibcon#flushed, iclass 24, count 0 2006.162.07:37:20.16#ibcon#about to write, iclass 24, count 0 2006.162.07:37:20.16#ibcon#wrote, iclass 24, count 0 2006.162.07:37:20.16#ibcon#about to read 3, iclass 24, count 0 2006.162.07:37:20.18#ibcon#read 3, iclass 24, count 0 2006.162.07:37:20.18#ibcon#about to read 4, iclass 24, count 0 2006.162.07:37:20.18#ibcon#read 4, iclass 24, count 0 2006.162.07:37:20.18#ibcon#about to read 5, iclass 24, count 0 2006.162.07:37:20.18#ibcon#read 5, iclass 24, count 0 2006.162.07:37:20.18#ibcon#about to read 6, iclass 24, count 0 2006.162.07:37:20.18#ibcon#read 6, iclass 24, count 0 2006.162.07:37:20.18#ibcon#end of sib2, iclass 24, count 0 2006.162.07:37:20.18#ibcon#*mode == 0, iclass 24, count 0 2006.162.07:37:20.18#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.07:37:20.18#ibcon#[25=USB\r\n] 2006.162.07:37:20.18#ibcon#*before write, iclass 24, count 0 2006.162.07:37:20.18#ibcon#enter sib2, iclass 24, count 0 2006.162.07:37:20.18#ibcon#flushed, iclass 24, count 0 2006.162.07:37:20.18#ibcon#about to write, iclass 24, count 0 2006.162.07:37:20.18#ibcon#wrote, iclass 24, count 0 2006.162.07:37:20.18#ibcon#about to read 3, iclass 24, count 0 2006.162.07:37:20.21#ibcon#read 3, iclass 24, count 0 2006.162.07:37:20.21#ibcon#about to read 4, iclass 24, count 0 2006.162.07:37:20.21#ibcon#read 4, iclass 24, count 0 2006.162.07:37:20.21#ibcon#about to read 5, iclass 24, count 0 2006.162.07:37:20.21#ibcon#read 5, iclass 24, count 0 2006.162.07:37:20.21#ibcon#about to read 6, iclass 24, count 0 2006.162.07:37:20.21#ibcon#read 6, iclass 24, count 0 2006.162.07:37:20.21#ibcon#end of sib2, iclass 24, count 0 2006.162.07:37:20.21#ibcon#*after write, iclass 24, count 0 2006.162.07:37:20.21#ibcon#*before return 0, iclass 24, count 0 2006.162.07:37:20.21#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:37:20.21#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:37:20.21#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.07:37:20.21#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.07:37:20.21$vc4f8/valo=4,832.99 2006.162.07:37:20.21#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.162.07:37:20.21#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.162.07:37:20.21#ibcon#ireg 17 cls_cnt 0 2006.162.07:37:20.21#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:37:20.21#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:37:20.21#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:37:20.21#ibcon#enter wrdev, iclass 26, count 0 2006.162.07:37:20.21#ibcon#first serial, iclass 26, count 0 2006.162.07:37:20.21#ibcon#enter sib2, iclass 26, count 0 2006.162.07:37:20.21#ibcon#flushed, iclass 26, count 0 2006.162.07:37:20.21#ibcon#about to write, iclass 26, count 0 2006.162.07:37:20.21#ibcon#wrote, iclass 26, count 0 2006.162.07:37:20.21#ibcon#about to read 3, iclass 26, count 0 2006.162.07:37:20.23#ibcon#read 3, iclass 26, count 0 2006.162.07:37:20.23#ibcon#about to read 4, iclass 26, count 0 2006.162.07:37:20.23#ibcon#read 4, iclass 26, count 0 2006.162.07:37:20.23#ibcon#about to read 5, iclass 26, count 0 2006.162.07:37:20.23#ibcon#read 5, iclass 26, count 0 2006.162.07:37:20.23#ibcon#about to read 6, iclass 26, count 0 2006.162.07:37:20.23#ibcon#read 6, iclass 26, count 0 2006.162.07:37:20.23#ibcon#end of sib2, iclass 26, count 0 2006.162.07:37:20.23#ibcon#*mode == 0, iclass 26, count 0 2006.162.07:37:20.23#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.162.07:37:20.23#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.07:37:20.23#ibcon#*before write, iclass 26, count 0 2006.162.07:37:20.23#ibcon#enter sib2, iclass 26, count 0 2006.162.07:37:20.23#ibcon#flushed, iclass 26, count 0 2006.162.07:37:20.23#ibcon#about to write, iclass 26, count 0 2006.162.07:37:20.23#ibcon#wrote, iclass 26, count 0 2006.162.07:37:20.23#ibcon#about to read 3, iclass 26, count 0 2006.162.07:37:20.27#ibcon#read 3, iclass 26, count 0 2006.162.07:37:20.27#ibcon#about to read 4, iclass 26, count 0 2006.162.07:37:20.27#ibcon#read 4, iclass 26, count 0 2006.162.07:37:20.27#ibcon#about to read 5, iclass 26, count 0 2006.162.07:37:20.27#ibcon#read 5, iclass 26, count 0 2006.162.07:37:20.27#ibcon#about to read 6, iclass 26, count 0 2006.162.07:37:20.27#ibcon#read 6, iclass 26, count 0 2006.162.07:37:20.27#ibcon#end of sib2, iclass 26, count 0 2006.162.07:37:20.27#ibcon#*after write, iclass 26, count 0 2006.162.07:37:20.27#ibcon#*before return 0, iclass 26, count 0 2006.162.07:37:20.27#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:37:20.27#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:37:20.27#ibcon#about to clear, iclass 26 cls_cnt 0 2006.162.07:37:20.27#ibcon#cleared, iclass 26 cls_cnt 0 2006.162.07:37:20.27$vc4f8/va=4,7 2006.162.07:37:20.27#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.162.07:37:20.27#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.162.07:37:20.27#ibcon#ireg 11 cls_cnt 2 2006.162.07:37:20.27#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.162.07:37:20.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.162.07:37:20.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.162.07:37:20.33#ibcon#enter wrdev, iclass 28, count 2 2006.162.07:37:20.33#ibcon#first serial, iclass 28, count 2 2006.162.07:37:20.33#ibcon#enter sib2, iclass 28, count 2 2006.162.07:37:20.33#ibcon#flushed, iclass 28, count 2 2006.162.07:37:20.33#ibcon#about to write, iclass 28, count 2 2006.162.07:37:20.33#ibcon#wrote, iclass 28, count 2 2006.162.07:37:20.33#ibcon#about to read 3, iclass 28, count 2 2006.162.07:37:20.35#ibcon#read 3, iclass 28, count 2 2006.162.07:37:20.35#ibcon#about to read 4, iclass 28, count 2 2006.162.07:37:20.35#ibcon#read 4, iclass 28, count 2 2006.162.07:37:20.35#ibcon#about to read 5, iclass 28, count 2 2006.162.07:37:20.35#ibcon#read 5, iclass 28, count 2 2006.162.07:37:20.35#ibcon#about to read 6, iclass 28, count 2 2006.162.07:37:20.35#ibcon#read 6, iclass 28, count 2 2006.162.07:37:20.35#ibcon#end of sib2, iclass 28, count 2 2006.162.07:37:20.35#ibcon#*mode == 0, iclass 28, count 2 2006.162.07:37:20.35#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.162.07:37:20.35#ibcon#[25=AT04-07\r\n] 2006.162.07:37:20.35#ibcon#*before write, iclass 28, count 2 2006.162.07:37:20.35#ibcon#enter sib2, iclass 28, count 2 2006.162.07:37:20.35#ibcon#flushed, iclass 28, count 2 2006.162.07:37:20.35#ibcon#about to write, iclass 28, count 2 2006.162.07:37:20.35#ibcon#wrote, iclass 28, count 2 2006.162.07:37:20.35#ibcon#about to read 3, iclass 28, count 2 2006.162.07:37:20.38#ibcon#read 3, iclass 28, count 2 2006.162.07:37:20.38#ibcon#about to read 4, iclass 28, count 2 2006.162.07:37:20.38#ibcon#read 4, iclass 28, count 2 2006.162.07:37:20.38#ibcon#about to read 5, iclass 28, count 2 2006.162.07:37:20.38#ibcon#read 5, iclass 28, count 2 2006.162.07:37:20.38#ibcon#about to read 6, iclass 28, count 2 2006.162.07:37:20.38#ibcon#read 6, iclass 28, count 2 2006.162.07:37:20.38#ibcon#end of sib2, iclass 28, count 2 2006.162.07:37:20.38#ibcon#*after write, iclass 28, count 2 2006.162.07:37:20.38#ibcon#*before return 0, iclass 28, count 2 2006.162.07:37:20.38#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.162.07:37:20.38#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.162.07:37:20.38#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.162.07:37:20.38#ibcon#ireg 7 cls_cnt 0 2006.162.07:37:20.38#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.162.07:37:20.50#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.162.07:37:20.50#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.162.07:37:20.50#ibcon#enter wrdev, iclass 28, count 0 2006.162.07:37:20.50#ibcon#first serial, iclass 28, count 0 2006.162.07:37:20.50#ibcon#enter sib2, iclass 28, count 0 2006.162.07:37:20.50#ibcon#flushed, iclass 28, count 0 2006.162.07:37:20.50#ibcon#about to write, iclass 28, count 0 2006.162.07:37:20.50#ibcon#wrote, iclass 28, count 0 2006.162.07:37:20.50#ibcon#about to read 3, iclass 28, count 0 2006.162.07:37:20.52#ibcon#read 3, iclass 28, count 0 2006.162.07:37:20.52#ibcon#about to read 4, iclass 28, count 0 2006.162.07:37:20.52#ibcon#read 4, iclass 28, count 0 2006.162.07:37:20.52#ibcon#about to read 5, iclass 28, count 0 2006.162.07:37:20.52#ibcon#read 5, iclass 28, count 0 2006.162.07:37:20.52#ibcon#about to read 6, iclass 28, count 0 2006.162.07:37:20.52#ibcon#read 6, iclass 28, count 0 2006.162.07:37:20.52#ibcon#end of sib2, iclass 28, count 0 2006.162.07:37:20.52#ibcon#*mode == 0, iclass 28, count 0 2006.162.07:37:20.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.162.07:37:20.52#ibcon#[25=USB\r\n] 2006.162.07:37:20.52#ibcon#*before write, iclass 28, count 0 2006.162.07:37:20.52#ibcon#enter sib2, iclass 28, count 0 2006.162.07:37:20.52#ibcon#flushed, iclass 28, count 0 2006.162.07:37:20.52#ibcon#about to write, iclass 28, count 0 2006.162.07:37:20.52#ibcon#wrote, iclass 28, count 0 2006.162.07:37:20.52#ibcon#about to read 3, iclass 28, count 0 2006.162.07:37:20.55#ibcon#read 3, iclass 28, count 0 2006.162.07:37:20.55#ibcon#about to read 4, iclass 28, count 0 2006.162.07:37:20.55#ibcon#read 4, iclass 28, count 0 2006.162.07:37:20.55#ibcon#about to read 5, iclass 28, count 0 2006.162.07:37:20.55#ibcon#read 5, iclass 28, count 0 2006.162.07:37:20.55#ibcon#about to read 6, iclass 28, count 0 2006.162.07:37:20.55#ibcon#read 6, iclass 28, count 0 2006.162.07:37:20.55#ibcon#end of sib2, iclass 28, count 0 2006.162.07:37:20.55#ibcon#*after write, iclass 28, count 0 2006.162.07:37:20.55#ibcon#*before return 0, iclass 28, count 0 2006.162.07:37:20.55#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.162.07:37:20.55#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.162.07:37:20.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.162.07:37:20.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.162.07:37:20.55$vc4f8/valo=5,652.99 2006.162.07:37:20.55#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.162.07:37:20.55#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.162.07:37:20.55#ibcon#ireg 17 cls_cnt 0 2006.162.07:37:20.55#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.162.07:37:20.55#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.162.07:37:20.55#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.162.07:37:20.55#ibcon#enter wrdev, iclass 30, count 0 2006.162.07:37:20.55#ibcon#first serial, iclass 30, count 0 2006.162.07:37:20.55#ibcon#enter sib2, iclass 30, count 0 2006.162.07:37:20.55#ibcon#flushed, iclass 30, count 0 2006.162.07:37:20.55#ibcon#about to write, iclass 30, count 0 2006.162.07:37:20.55#ibcon#wrote, iclass 30, count 0 2006.162.07:37:20.55#ibcon#about to read 3, iclass 30, count 0 2006.162.07:37:20.57#ibcon#read 3, iclass 30, count 0 2006.162.07:37:20.57#ibcon#about to read 4, iclass 30, count 0 2006.162.07:37:20.57#ibcon#read 4, iclass 30, count 0 2006.162.07:37:20.57#ibcon#about to read 5, iclass 30, count 0 2006.162.07:37:20.57#ibcon#read 5, iclass 30, count 0 2006.162.07:37:20.57#ibcon#about to read 6, iclass 30, count 0 2006.162.07:37:20.57#ibcon#read 6, iclass 30, count 0 2006.162.07:37:20.57#ibcon#end of sib2, iclass 30, count 0 2006.162.07:37:20.57#ibcon#*mode == 0, iclass 30, count 0 2006.162.07:37:20.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.162.07:37:20.57#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.07:37:20.57#ibcon#*before write, iclass 30, count 0 2006.162.07:37:20.57#ibcon#enter sib2, iclass 30, count 0 2006.162.07:37:20.57#ibcon#flushed, iclass 30, count 0 2006.162.07:37:20.57#ibcon#about to write, iclass 30, count 0 2006.162.07:37:20.57#ibcon#wrote, iclass 30, count 0 2006.162.07:37:20.57#ibcon#about to read 3, iclass 30, count 0 2006.162.07:37:20.61#ibcon#read 3, iclass 30, count 0 2006.162.07:37:20.61#ibcon#about to read 4, iclass 30, count 0 2006.162.07:37:20.61#ibcon#read 4, iclass 30, count 0 2006.162.07:37:20.61#ibcon#about to read 5, iclass 30, count 0 2006.162.07:37:20.61#ibcon#read 5, iclass 30, count 0 2006.162.07:37:20.61#ibcon#about to read 6, iclass 30, count 0 2006.162.07:37:20.61#ibcon#read 6, iclass 30, count 0 2006.162.07:37:20.61#ibcon#end of sib2, iclass 30, count 0 2006.162.07:37:20.61#ibcon#*after write, iclass 30, count 0 2006.162.07:37:20.61#ibcon#*before return 0, iclass 30, count 0 2006.162.07:37:20.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.162.07:37:20.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.162.07:37:20.61#ibcon#about to clear, iclass 30 cls_cnt 0 2006.162.07:37:20.61#ibcon#cleared, iclass 30 cls_cnt 0 2006.162.07:37:20.61$vc4f8/va=5,7 2006.162.07:37:20.61#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.162.07:37:20.61#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.162.07:37:20.61#ibcon#ireg 11 cls_cnt 2 2006.162.07:37:20.61#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.162.07:37:20.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.162.07:37:20.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.162.07:37:20.67#ibcon#enter wrdev, iclass 32, count 2 2006.162.07:37:20.67#ibcon#first serial, iclass 32, count 2 2006.162.07:37:20.67#ibcon#enter sib2, iclass 32, count 2 2006.162.07:37:20.67#ibcon#flushed, iclass 32, count 2 2006.162.07:37:20.67#ibcon#about to write, iclass 32, count 2 2006.162.07:37:20.67#ibcon#wrote, iclass 32, count 2 2006.162.07:37:20.67#ibcon#about to read 3, iclass 32, count 2 2006.162.07:37:20.69#ibcon#read 3, iclass 32, count 2 2006.162.07:37:20.69#ibcon#about to read 4, iclass 32, count 2 2006.162.07:37:20.69#ibcon#read 4, iclass 32, count 2 2006.162.07:37:20.69#ibcon#about to read 5, iclass 32, count 2 2006.162.07:37:20.69#ibcon#read 5, iclass 32, count 2 2006.162.07:37:20.69#ibcon#about to read 6, iclass 32, count 2 2006.162.07:37:20.69#ibcon#read 6, iclass 32, count 2 2006.162.07:37:20.69#ibcon#end of sib2, iclass 32, count 2 2006.162.07:37:20.69#ibcon#*mode == 0, iclass 32, count 2 2006.162.07:37:20.69#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.162.07:37:20.69#ibcon#[25=AT05-07\r\n] 2006.162.07:37:20.69#ibcon#*before write, iclass 32, count 2 2006.162.07:37:20.69#ibcon#enter sib2, iclass 32, count 2 2006.162.07:37:20.69#ibcon#flushed, iclass 32, count 2 2006.162.07:37:20.69#ibcon#about to write, iclass 32, count 2 2006.162.07:37:20.69#ibcon#wrote, iclass 32, count 2 2006.162.07:37:20.69#ibcon#about to read 3, iclass 32, count 2 2006.162.07:37:20.72#ibcon#read 3, iclass 32, count 2 2006.162.07:37:20.72#ibcon#about to read 4, iclass 32, count 2 2006.162.07:37:20.72#ibcon#read 4, iclass 32, count 2 2006.162.07:37:20.72#ibcon#about to read 5, iclass 32, count 2 2006.162.07:37:20.72#ibcon#read 5, iclass 32, count 2 2006.162.07:37:20.72#ibcon#about to read 6, iclass 32, count 2 2006.162.07:37:20.72#ibcon#read 6, iclass 32, count 2 2006.162.07:37:20.72#ibcon#end of sib2, iclass 32, count 2 2006.162.07:37:20.72#ibcon#*after write, iclass 32, count 2 2006.162.07:37:20.72#ibcon#*before return 0, iclass 32, count 2 2006.162.07:37:20.72#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.162.07:37:20.72#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.162.07:37:20.72#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.162.07:37:20.72#ibcon#ireg 7 cls_cnt 0 2006.162.07:37:20.72#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.162.07:37:20.84#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.162.07:37:20.84#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.162.07:37:20.84#ibcon#enter wrdev, iclass 32, count 0 2006.162.07:37:20.84#ibcon#first serial, iclass 32, count 0 2006.162.07:37:20.84#ibcon#enter sib2, iclass 32, count 0 2006.162.07:37:20.84#ibcon#flushed, iclass 32, count 0 2006.162.07:37:20.84#ibcon#about to write, iclass 32, count 0 2006.162.07:37:20.84#ibcon#wrote, iclass 32, count 0 2006.162.07:37:20.84#ibcon#about to read 3, iclass 32, count 0 2006.162.07:37:20.86#ibcon#read 3, iclass 32, count 0 2006.162.07:37:20.86#ibcon#about to read 4, iclass 32, count 0 2006.162.07:37:20.86#ibcon#read 4, iclass 32, count 0 2006.162.07:37:20.86#ibcon#about to read 5, iclass 32, count 0 2006.162.07:37:20.86#ibcon#read 5, iclass 32, count 0 2006.162.07:37:20.86#ibcon#about to read 6, iclass 32, count 0 2006.162.07:37:20.86#ibcon#read 6, iclass 32, count 0 2006.162.07:37:20.86#ibcon#end of sib2, iclass 32, count 0 2006.162.07:37:20.86#ibcon#*mode == 0, iclass 32, count 0 2006.162.07:37:20.86#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.162.07:37:20.86#ibcon#[25=USB\r\n] 2006.162.07:37:20.86#ibcon#*before write, iclass 32, count 0 2006.162.07:37:20.86#ibcon#enter sib2, iclass 32, count 0 2006.162.07:37:20.86#ibcon#flushed, iclass 32, count 0 2006.162.07:37:20.86#ibcon#about to write, iclass 32, count 0 2006.162.07:37:20.86#ibcon#wrote, iclass 32, count 0 2006.162.07:37:20.86#ibcon#about to read 3, iclass 32, count 0 2006.162.07:37:20.89#ibcon#read 3, iclass 32, count 0 2006.162.07:37:20.89#ibcon#about to read 4, iclass 32, count 0 2006.162.07:37:20.89#ibcon#read 4, iclass 32, count 0 2006.162.07:37:20.89#ibcon#about to read 5, iclass 32, count 0 2006.162.07:37:20.89#ibcon#read 5, iclass 32, count 0 2006.162.07:37:20.89#ibcon#about to read 6, iclass 32, count 0 2006.162.07:37:20.89#ibcon#read 6, iclass 32, count 0 2006.162.07:37:20.89#ibcon#end of sib2, iclass 32, count 0 2006.162.07:37:20.89#ibcon#*after write, iclass 32, count 0 2006.162.07:37:20.89#ibcon#*before return 0, iclass 32, count 0 2006.162.07:37:20.89#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.162.07:37:20.89#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.162.07:37:20.89#ibcon#about to clear, iclass 32 cls_cnt 0 2006.162.07:37:20.89#ibcon#cleared, iclass 32 cls_cnt 0 2006.162.07:37:20.89$vc4f8/valo=6,772.99 2006.162.07:37:20.89#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.162.07:37:20.89#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.162.07:37:20.89#ibcon#ireg 17 cls_cnt 0 2006.162.07:37:20.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.162.07:37:20.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.162.07:37:20.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.162.07:37:20.89#ibcon#enter wrdev, iclass 34, count 0 2006.162.07:37:20.89#ibcon#first serial, iclass 34, count 0 2006.162.07:37:20.89#ibcon#enter sib2, iclass 34, count 0 2006.162.07:37:20.89#ibcon#flushed, iclass 34, count 0 2006.162.07:37:20.89#ibcon#about to write, iclass 34, count 0 2006.162.07:37:20.89#ibcon#wrote, iclass 34, count 0 2006.162.07:37:20.89#ibcon#about to read 3, iclass 34, count 0 2006.162.07:37:20.91#ibcon#read 3, iclass 34, count 0 2006.162.07:37:20.91#ibcon#about to read 4, iclass 34, count 0 2006.162.07:37:20.91#ibcon#read 4, iclass 34, count 0 2006.162.07:37:20.91#ibcon#about to read 5, iclass 34, count 0 2006.162.07:37:20.91#ibcon#read 5, iclass 34, count 0 2006.162.07:37:20.91#ibcon#about to read 6, iclass 34, count 0 2006.162.07:37:20.91#ibcon#read 6, iclass 34, count 0 2006.162.07:37:20.91#ibcon#end of sib2, iclass 34, count 0 2006.162.07:37:20.91#ibcon#*mode == 0, iclass 34, count 0 2006.162.07:37:20.91#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.162.07:37:20.91#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.07:37:20.91#ibcon#*before write, iclass 34, count 0 2006.162.07:37:20.91#ibcon#enter sib2, iclass 34, count 0 2006.162.07:37:20.91#ibcon#flushed, iclass 34, count 0 2006.162.07:37:20.91#ibcon#about to write, iclass 34, count 0 2006.162.07:37:20.91#ibcon#wrote, iclass 34, count 0 2006.162.07:37:20.91#ibcon#about to read 3, iclass 34, count 0 2006.162.07:37:20.95#ibcon#read 3, iclass 34, count 0 2006.162.07:37:20.95#ibcon#about to read 4, iclass 34, count 0 2006.162.07:37:20.95#ibcon#read 4, iclass 34, count 0 2006.162.07:37:20.95#ibcon#about to read 5, iclass 34, count 0 2006.162.07:37:20.95#ibcon#read 5, iclass 34, count 0 2006.162.07:37:20.95#ibcon#about to read 6, iclass 34, count 0 2006.162.07:37:20.95#ibcon#read 6, iclass 34, count 0 2006.162.07:37:20.95#ibcon#end of sib2, iclass 34, count 0 2006.162.07:37:20.95#ibcon#*after write, iclass 34, count 0 2006.162.07:37:20.95#ibcon#*before return 0, iclass 34, count 0 2006.162.07:37:20.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.162.07:37:20.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.162.07:37:20.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.162.07:37:20.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.162.07:37:20.95$vc4f8/va=6,6 2006.162.07:37:20.95#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.162.07:37:20.95#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.162.07:37:20.95#ibcon#ireg 11 cls_cnt 2 2006.162.07:37:20.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.162.07:37:21.01#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.162.07:37:21.01#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.162.07:37:21.01#ibcon#enter wrdev, iclass 36, count 2 2006.162.07:37:21.01#ibcon#first serial, iclass 36, count 2 2006.162.07:37:21.01#ibcon#enter sib2, iclass 36, count 2 2006.162.07:37:21.01#ibcon#flushed, iclass 36, count 2 2006.162.07:37:21.01#ibcon#about to write, iclass 36, count 2 2006.162.07:37:21.01#ibcon#wrote, iclass 36, count 2 2006.162.07:37:21.01#ibcon#about to read 3, iclass 36, count 2 2006.162.07:37:21.03#ibcon#read 3, iclass 36, count 2 2006.162.07:37:21.03#ibcon#about to read 4, iclass 36, count 2 2006.162.07:37:21.03#ibcon#read 4, iclass 36, count 2 2006.162.07:37:21.03#ibcon#about to read 5, iclass 36, count 2 2006.162.07:37:21.03#ibcon#read 5, iclass 36, count 2 2006.162.07:37:21.03#ibcon#about to read 6, iclass 36, count 2 2006.162.07:37:21.03#ibcon#read 6, iclass 36, count 2 2006.162.07:37:21.03#ibcon#end of sib2, iclass 36, count 2 2006.162.07:37:21.03#ibcon#*mode == 0, iclass 36, count 2 2006.162.07:37:21.03#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.162.07:37:21.03#ibcon#[25=AT06-06\r\n] 2006.162.07:37:21.03#ibcon#*before write, iclass 36, count 2 2006.162.07:37:21.03#ibcon#enter sib2, iclass 36, count 2 2006.162.07:37:21.03#ibcon#flushed, iclass 36, count 2 2006.162.07:37:21.03#ibcon#about to write, iclass 36, count 2 2006.162.07:37:21.03#ibcon#wrote, iclass 36, count 2 2006.162.07:37:21.03#ibcon#about to read 3, iclass 36, count 2 2006.162.07:37:21.06#ibcon#read 3, iclass 36, count 2 2006.162.07:37:21.06#ibcon#about to read 4, iclass 36, count 2 2006.162.07:37:21.06#ibcon#read 4, iclass 36, count 2 2006.162.07:37:21.06#ibcon#about to read 5, iclass 36, count 2 2006.162.07:37:21.06#ibcon#read 5, iclass 36, count 2 2006.162.07:37:21.06#ibcon#about to read 6, iclass 36, count 2 2006.162.07:37:21.06#ibcon#read 6, iclass 36, count 2 2006.162.07:37:21.06#ibcon#end of sib2, iclass 36, count 2 2006.162.07:37:21.06#ibcon#*after write, iclass 36, count 2 2006.162.07:37:21.06#ibcon#*before return 0, iclass 36, count 2 2006.162.07:37:21.06#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.162.07:37:21.06#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.162.07:37:21.06#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.162.07:37:21.06#ibcon#ireg 7 cls_cnt 0 2006.162.07:37:21.06#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.162.07:37:21.18#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.162.07:37:21.18#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.162.07:37:21.18#ibcon#enter wrdev, iclass 36, count 0 2006.162.07:37:21.18#ibcon#first serial, iclass 36, count 0 2006.162.07:37:21.18#ibcon#enter sib2, iclass 36, count 0 2006.162.07:37:21.18#ibcon#flushed, iclass 36, count 0 2006.162.07:37:21.18#ibcon#about to write, iclass 36, count 0 2006.162.07:37:21.18#ibcon#wrote, iclass 36, count 0 2006.162.07:37:21.18#ibcon#about to read 3, iclass 36, count 0 2006.162.07:37:21.20#ibcon#read 3, iclass 36, count 0 2006.162.07:37:21.20#ibcon#about to read 4, iclass 36, count 0 2006.162.07:37:21.20#ibcon#read 4, iclass 36, count 0 2006.162.07:37:21.20#ibcon#about to read 5, iclass 36, count 0 2006.162.07:37:21.20#ibcon#read 5, iclass 36, count 0 2006.162.07:37:21.20#ibcon#about to read 6, iclass 36, count 0 2006.162.07:37:21.20#ibcon#read 6, iclass 36, count 0 2006.162.07:37:21.20#ibcon#end of sib2, iclass 36, count 0 2006.162.07:37:21.20#ibcon#*mode == 0, iclass 36, count 0 2006.162.07:37:21.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.162.07:37:21.20#ibcon#[25=USB\r\n] 2006.162.07:37:21.20#ibcon#*before write, iclass 36, count 0 2006.162.07:37:21.20#ibcon#enter sib2, iclass 36, count 0 2006.162.07:37:21.20#ibcon#flushed, iclass 36, count 0 2006.162.07:37:21.20#ibcon#about to write, iclass 36, count 0 2006.162.07:37:21.20#ibcon#wrote, iclass 36, count 0 2006.162.07:37:21.20#ibcon#about to read 3, iclass 36, count 0 2006.162.07:37:21.23#ibcon#read 3, iclass 36, count 0 2006.162.07:37:21.23#ibcon#about to read 4, iclass 36, count 0 2006.162.07:37:21.23#ibcon#read 4, iclass 36, count 0 2006.162.07:37:21.23#ibcon#about to read 5, iclass 36, count 0 2006.162.07:37:21.23#ibcon#read 5, iclass 36, count 0 2006.162.07:37:21.23#ibcon#about to read 6, iclass 36, count 0 2006.162.07:37:21.23#ibcon#read 6, iclass 36, count 0 2006.162.07:37:21.23#ibcon#end of sib2, iclass 36, count 0 2006.162.07:37:21.23#ibcon#*after write, iclass 36, count 0 2006.162.07:37:21.23#ibcon#*before return 0, iclass 36, count 0 2006.162.07:37:21.23#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.162.07:37:21.23#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.162.07:37:21.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.162.07:37:21.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.162.07:37:21.23$vc4f8/valo=7,832.99 2006.162.07:37:21.23#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.162.07:37:21.23#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.162.07:37:21.23#ibcon#ireg 17 cls_cnt 0 2006.162.07:37:21.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.162.07:37:21.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.162.07:37:21.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.162.07:37:21.23#ibcon#enter wrdev, iclass 38, count 0 2006.162.07:37:21.23#ibcon#first serial, iclass 38, count 0 2006.162.07:37:21.23#ibcon#enter sib2, iclass 38, count 0 2006.162.07:37:21.23#ibcon#flushed, iclass 38, count 0 2006.162.07:37:21.23#ibcon#about to write, iclass 38, count 0 2006.162.07:37:21.23#ibcon#wrote, iclass 38, count 0 2006.162.07:37:21.23#ibcon#about to read 3, iclass 38, count 0 2006.162.07:37:21.25#ibcon#read 3, iclass 38, count 0 2006.162.07:37:21.25#ibcon#about to read 4, iclass 38, count 0 2006.162.07:37:21.25#ibcon#read 4, iclass 38, count 0 2006.162.07:37:21.25#ibcon#about to read 5, iclass 38, count 0 2006.162.07:37:21.25#ibcon#read 5, iclass 38, count 0 2006.162.07:37:21.25#ibcon#about to read 6, iclass 38, count 0 2006.162.07:37:21.25#ibcon#read 6, iclass 38, count 0 2006.162.07:37:21.25#ibcon#end of sib2, iclass 38, count 0 2006.162.07:37:21.25#ibcon#*mode == 0, iclass 38, count 0 2006.162.07:37:21.25#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.162.07:37:21.25#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.07:37:21.25#ibcon#*before write, iclass 38, count 0 2006.162.07:37:21.25#ibcon#enter sib2, iclass 38, count 0 2006.162.07:37:21.25#ibcon#flushed, iclass 38, count 0 2006.162.07:37:21.25#ibcon#about to write, iclass 38, count 0 2006.162.07:37:21.25#ibcon#wrote, iclass 38, count 0 2006.162.07:37:21.25#ibcon#about to read 3, iclass 38, count 0 2006.162.07:37:21.29#ibcon#read 3, iclass 38, count 0 2006.162.07:37:21.29#ibcon#about to read 4, iclass 38, count 0 2006.162.07:37:21.29#ibcon#read 4, iclass 38, count 0 2006.162.07:37:21.29#ibcon#about to read 5, iclass 38, count 0 2006.162.07:37:21.29#ibcon#read 5, iclass 38, count 0 2006.162.07:37:21.29#ibcon#about to read 6, iclass 38, count 0 2006.162.07:37:21.29#ibcon#read 6, iclass 38, count 0 2006.162.07:37:21.29#ibcon#end of sib2, iclass 38, count 0 2006.162.07:37:21.29#ibcon#*after write, iclass 38, count 0 2006.162.07:37:21.29#ibcon#*before return 0, iclass 38, count 0 2006.162.07:37:21.29#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.162.07:37:21.29#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.162.07:37:21.29#ibcon#about to clear, iclass 38 cls_cnt 0 2006.162.07:37:21.29#ibcon#cleared, iclass 38 cls_cnt 0 2006.162.07:37:21.29$vc4f8/va=7,6 2006.162.07:37:21.29#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.162.07:37:21.29#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.162.07:37:21.29#ibcon#ireg 11 cls_cnt 2 2006.162.07:37:21.29#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.162.07:37:21.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.162.07:37:21.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.162.07:37:21.35#ibcon#enter wrdev, iclass 40, count 2 2006.162.07:37:21.35#ibcon#first serial, iclass 40, count 2 2006.162.07:37:21.35#ibcon#enter sib2, iclass 40, count 2 2006.162.07:37:21.35#ibcon#flushed, iclass 40, count 2 2006.162.07:37:21.35#ibcon#about to write, iclass 40, count 2 2006.162.07:37:21.35#ibcon#wrote, iclass 40, count 2 2006.162.07:37:21.35#ibcon#about to read 3, iclass 40, count 2 2006.162.07:37:21.37#ibcon#read 3, iclass 40, count 2 2006.162.07:37:21.37#ibcon#about to read 4, iclass 40, count 2 2006.162.07:37:21.37#ibcon#read 4, iclass 40, count 2 2006.162.07:37:21.37#ibcon#about to read 5, iclass 40, count 2 2006.162.07:37:21.37#ibcon#read 5, iclass 40, count 2 2006.162.07:37:21.37#ibcon#about to read 6, iclass 40, count 2 2006.162.07:37:21.37#ibcon#read 6, iclass 40, count 2 2006.162.07:37:21.37#ibcon#end of sib2, iclass 40, count 2 2006.162.07:37:21.37#ibcon#*mode == 0, iclass 40, count 2 2006.162.07:37:21.37#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.162.07:37:21.37#ibcon#[25=AT07-06\r\n] 2006.162.07:37:21.37#ibcon#*before write, iclass 40, count 2 2006.162.07:37:21.37#ibcon#enter sib2, iclass 40, count 2 2006.162.07:37:21.37#ibcon#flushed, iclass 40, count 2 2006.162.07:37:21.37#ibcon#about to write, iclass 40, count 2 2006.162.07:37:21.37#ibcon#wrote, iclass 40, count 2 2006.162.07:37:21.37#ibcon#about to read 3, iclass 40, count 2 2006.162.07:37:21.40#ibcon#read 3, iclass 40, count 2 2006.162.07:37:21.40#ibcon#about to read 4, iclass 40, count 2 2006.162.07:37:21.40#ibcon#read 4, iclass 40, count 2 2006.162.07:37:21.40#ibcon#about to read 5, iclass 40, count 2 2006.162.07:37:21.40#ibcon#read 5, iclass 40, count 2 2006.162.07:37:21.40#ibcon#about to read 6, iclass 40, count 2 2006.162.07:37:21.40#ibcon#read 6, iclass 40, count 2 2006.162.07:37:21.40#ibcon#end of sib2, iclass 40, count 2 2006.162.07:37:21.40#ibcon#*after write, iclass 40, count 2 2006.162.07:37:21.40#ibcon#*before return 0, iclass 40, count 2 2006.162.07:37:21.40#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.162.07:37:21.40#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.162.07:37:21.40#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.162.07:37:21.40#ibcon#ireg 7 cls_cnt 0 2006.162.07:37:21.40#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.162.07:37:21.52#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.162.07:37:21.52#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.162.07:37:21.52#ibcon#enter wrdev, iclass 40, count 0 2006.162.07:37:21.52#ibcon#first serial, iclass 40, count 0 2006.162.07:37:21.52#ibcon#enter sib2, iclass 40, count 0 2006.162.07:37:21.52#ibcon#flushed, iclass 40, count 0 2006.162.07:37:21.52#ibcon#about to write, iclass 40, count 0 2006.162.07:37:21.52#ibcon#wrote, iclass 40, count 0 2006.162.07:37:21.52#ibcon#about to read 3, iclass 40, count 0 2006.162.07:37:21.55#ibcon#read 3, iclass 40, count 0 2006.162.07:37:21.55#ibcon#about to read 4, iclass 40, count 0 2006.162.07:37:21.55#ibcon#read 4, iclass 40, count 0 2006.162.07:37:21.55#ibcon#about to read 5, iclass 40, count 0 2006.162.07:37:21.55#ibcon#read 5, iclass 40, count 0 2006.162.07:37:21.55#ibcon#about to read 6, iclass 40, count 0 2006.162.07:37:21.55#ibcon#read 6, iclass 40, count 0 2006.162.07:37:21.55#ibcon#end of sib2, iclass 40, count 0 2006.162.07:37:21.55#ibcon#*mode == 0, iclass 40, count 0 2006.162.07:37:21.55#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.162.07:37:21.55#ibcon#[25=USB\r\n] 2006.162.07:37:21.55#ibcon#*before write, iclass 40, count 0 2006.162.07:37:21.55#ibcon#enter sib2, iclass 40, count 0 2006.162.07:37:21.55#ibcon#flushed, iclass 40, count 0 2006.162.07:37:21.55#ibcon#about to write, iclass 40, count 0 2006.162.07:37:21.55#ibcon#wrote, iclass 40, count 0 2006.162.07:37:21.55#ibcon#about to read 3, iclass 40, count 0 2006.162.07:37:21.57#ibcon#read 3, iclass 40, count 0 2006.162.07:37:21.57#ibcon#about to read 4, iclass 40, count 0 2006.162.07:37:21.57#ibcon#read 4, iclass 40, count 0 2006.162.07:37:21.57#ibcon#about to read 5, iclass 40, count 0 2006.162.07:37:21.57#ibcon#read 5, iclass 40, count 0 2006.162.07:37:21.57#ibcon#about to read 6, iclass 40, count 0 2006.162.07:37:21.57#ibcon#read 6, iclass 40, count 0 2006.162.07:37:21.57#ibcon#end of sib2, iclass 40, count 0 2006.162.07:37:21.57#ibcon#*after write, iclass 40, count 0 2006.162.07:37:21.57#ibcon#*before return 0, iclass 40, count 0 2006.162.07:37:21.57#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.162.07:37:21.57#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.162.07:37:21.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.162.07:37:21.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.162.07:37:21.57$vc4f8/valo=8,852.99 2006.162.07:37:21.57#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.162.07:37:21.57#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.162.07:37:21.57#ibcon#ireg 17 cls_cnt 0 2006.162.07:37:21.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.162.07:37:21.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.162.07:37:21.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.162.07:37:21.57#ibcon#enter wrdev, iclass 4, count 0 2006.162.07:37:21.57#ibcon#first serial, iclass 4, count 0 2006.162.07:37:21.57#ibcon#enter sib2, iclass 4, count 0 2006.162.07:37:21.57#ibcon#flushed, iclass 4, count 0 2006.162.07:37:21.57#ibcon#about to write, iclass 4, count 0 2006.162.07:37:21.57#ibcon#wrote, iclass 4, count 0 2006.162.07:37:21.57#ibcon#about to read 3, iclass 4, count 0 2006.162.07:37:21.59#ibcon#read 3, iclass 4, count 0 2006.162.07:37:21.59#ibcon#about to read 4, iclass 4, count 0 2006.162.07:37:21.59#ibcon#read 4, iclass 4, count 0 2006.162.07:37:21.59#ibcon#about to read 5, iclass 4, count 0 2006.162.07:37:21.59#ibcon#read 5, iclass 4, count 0 2006.162.07:37:21.59#ibcon#about to read 6, iclass 4, count 0 2006.162.07:37:21.59#ibcon#read 6, iclass 4, count 0 2006.162.07:37:21.59#ibcon#end of sib2, iclass 4, count 0 2006.162.07:37:21.59#ibcon#*mode == 0, iclass 4, count 0 2006.162.07:37:21.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.162.07:37:21.59#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.07:37:21.59#ibcon#*before write, iclass 4, count 0 2006.162.07:37:21.59#ibcon#enter sib2, iclass 4, count 0 2006.162.07:37:21.59#ibcon#flushed, iclass 4, count 0 2006.162.07:37:21.59#ibcon#about to write, iclass 4, count 0 2006.162.07:37:21.59#ibcon#wrote, iclass 4, count 0 2006.162.07:37:21.59#ibcon#about to read 3, iclass 4, count 0 2006.162.07:37:21.63#ibcon#read 3, iclass 4, count 0 2006.162.07:37:21.63#ibcon#about to read 4, iclass 4, count 0 2006.162.07:37:21.63#ibcon#read 4, iclass 4, count 0 2006.162.07:37:21.63#ibcon#about to read 5, iclass 4, count 0 2006.162.07:37:21.63#ibcon#read 5, iclass 4, count 0 2006.162.07:37:21.63#ibcon#about to read 6, iclass 4, count 0 2006.162.07:37:21.63#ibcon#read 6, iclass 4, count 0 2006.162.07:37:21.63#ibcon#end of sib2, iclass 4, count 0 2006.162.07:37:21.63#ibcon#*after write, iclass 4, count 0 2006.162.07:37:21.63#ibcon#*before return 0, iclass 4, count 0 2006.162.07:37:21.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.162.07:37:21.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.162.07:37:21.63#ibcon#about to clear, iclass 4 cls_cnt 0 2006.162.07:37:21.63#ibcon#cleared, iclass 4 cls_cnt 0 2006.162.07:37:21.63$vc4f8/va=8,7 2006.162.07:37:21.63#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.162.07:37:21.63#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.162.07:37:21.63#ibcon#ireg 11 cls_cnt 2 2006.162.07:37:21.63#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.162.07:37:21.69#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.162.07:37:21.69#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.162.07:37:21.69#ibcon#enter wrdev, iclass 6, count 2 2006.162.07:37:21.69#ibcon#first serial, iclass 6, count 2 2006.162.07:37:21.69#ibcon#enter sib2, iclass 6, count 2 2006.162.07:37:21.69#ibcon#flushed, iclass 6, count 2 2006.162.07:37:21.69#ibcon#about to write, iclass 6, count 2 2006.162.07:37:21.69#ibcon#wrote, iclass 6, count 2 2006.162.07:37:21.69#ibcon#about to read 3, iclass 6, count 2 2006.162.07:37:21.71#ibcon#read 3, iclass 6, count 2 2006.162.07:37:21.71#ibcon#about to read 4, iclass 6, count 2 2006.162.07:37:21.71#ibcon#read 4, iclass 6, count 2 2006.162.07:37:21.71#ibcon#about to read 5, iclass 6, count 2 2006.162.07:37:21.71#ibcon#read 5, iclass 6, count 2 2006.162.07:37:21.71#ibcon#about to read 6, iclass 6, count 2 2006.162.07:37:21.71#ibcon#read 6, iclass 6, count 2 2006.162.07:37:21.71#ibcon#end of sib2, iclass 6, count 2 2006.162.07:37:21.71#ibcon#*mode == 0, iclass 6, count 2 2006.162.07:37:21.71#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.162.07:37:21.71#ibcon#[25=AT08-07\r\n] 2006.162.07:37:21.71#ibcon#*before write, iclass 6, count 2 2006.162.07:37:21.71#ibcon#enter sib2, iclass 6, count 2 2006.162.07:37:21.71#ibcon#flushed, iclass 6, count 2 2006.162.07:37:21.71#ibcon#about to write, iclass 6, count 2 2006.162.07:37:21.71#ibcon#wrote, iclass 6, count 2 2006.162.07:37:21.71#ibcon#about to read 3, iclass 6, count 2 2006.162.07:37:21.74#ibcon#read 3, iclass 6, count 2 2006.162.07:37:21.74#ibcon#about to read 4, iclass 6, count 2 2006.162.07:37:21.74#ibcon#read 4, iclass 6, count 2 2006.162.07:37:21.74#ibcon#about to read 5, iclass 6, count 2 2006.162.07:37:21.74#ibcon#read 5, iclass 6, count 2 2006.162.07:37:21.74#ibcon#about to read 6, iclass 6, count 2 2006.162.07:37:21.74#ibcon#read 6, iclass 6, count 2 2006.162.07:37:21.74#ibcon#end of sib2, iclass 6, count 2 2006.162.07:37:21.74#ibcon#*after write, iclass 6, count 2 2006.162.07:37:21.74#ibcon#*before return 0, iclass 6, count 2 2006.162.07:37:21.74#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.162.07:37:21.74#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.162.07:37:21.74#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.162.07:37:21.74#ibcon#ireg 7 cls_cnt 0 2006.162.07:37:21.74#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.162.07:37:21.86#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.162.07:37:21.86#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.162.07:37:21.86#ibcon#enter wrdev, iclass 6, count 0 2006.162.07:37:21.86#ibcon#first serial, iclass 6, count 0 2006.162.07:37:21.86#ibcon#enter sib2, iclass 6, count 0 2006.162.07:37:21.86#ibcon#flushed, iclass 6, count 0 2006.162.07:37:21.86#ibcon#about to write, iclass 6, count 0 2006.162.07:37:21.86#ibcon#wrote, iclass 6, count 0 2006.162.07:37:21.86#ibcon#about to read 3, iclass 6, count 0 2006.162.07:37:21.88#ibcon#read 3, iclass 6, count 0 2006.162.07:37:21.88#ibcon#about to read 4, iclass 6, count 0 2006.162.07:37:21.88#ibcon#read 4, iclass 6, count 0 2006.162.07:37:21.88#ibcon#about to read 5, iclass 6, count 0 2006.162.07:37:21.88#ibcon#read 5, iclass 6, count 0 2006.162.07:37:21.88#ibcon#about to read 6, iclass 6, count 0 2006.162.07:37:21.88#ibcon#read 6, iclass 6, count 0 2006.162.07:37:21.88#ibcon#end of sib2, iclass 6, count 0 2006.162.07:37:21.88#ibcon#*mode == 0, iclass 6, count 0 2006.162.07:37:21.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.162.07:37:21.88#ibcon#[25=USB\r\n] 2006.162.07:37:21.88#ibcon#*before write, iclass 6, count 0 2006.162.07:37:21.88#ibcon#enter sib2, iclass 6, count 0 2006.162.07:37:21.88#ibcon#flushed, iclass 6, count 0 2006.162.07:37:21.88#ibcon#about to write, iclass 6, count 0 2006.162.07:37:21.88#ibcon#wrote, iclass 6, count 0 2006.162.07:37:21.88#ibcon#about to read 3, iclass 6, count 0 2006.162.07:37:21.91#ibcon#read 3, iclass 6, count 0 2006.162.07:37:21.91#ibcon#about to read 4, iclass 6, count 0 2006.162.07:37:21.91#ibcon#read 4, iclass 6, count 0 2006.162.07:37:21.91#ibcon#about to read 5, iclass 6, count 0 2006.162.07:37:21.91#ibcon#read 5, iclass 6, count 0 2006.162.07:37:21.91#ibcon#about to read 6, iclass 6, count 0 2006.162.07:37:21.91#ibcon#read 6, iclass 6, count 0 2006.162.07:37:21.91#ibcon#end of sib2, iclass 6, count 0 2006.162.07:37:21.91#ibcon#*after write, iclass 6, count 0 2006.162.07:37:21.91#ibcon#*before return 0, iclass 6, count 0 2006.162.07:37:21.91#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.162.07:37:21.91#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.162.07:37:21.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.162.07:37:21.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.162.07:37:21.91$vc4f8/vblo=1,632.99 2006.162.07:37:21.91#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.162.07:37:21.91#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.162.07:37:21.91#ibcon#ireg 17 cls_cnt 0 2006.162.07:37:21.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.162.07:37:21.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.162.07:37:21.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.162.07:37:21.91#ibcon#enter wrdev, iclass 10, count 0 2006.162.07:37:21.91#ibcon#first serial, iclass 10, count 0 2006.162.07:37:21.91#ibcon#enter sib2, iclass 10, count 0 2006.162.07:37:21.91#ibcon#flushed, iclass 10, count 0 2006.162.07:37:21.91#ibcon#about to write, iclass 10, count 0 2006.162.07:37:21.91#ibcon#wrote, iclass 10, count 0 2006.162.07:37:21.91#ibcon#about to read 3, iclass 10, count 0 2006.162.07:37:21.93#ibcon#read 3, iclass 10, count 0 2006.162.07:37:21.93#ibcon#about to read 4, iclass 10, count 0 2006.162.07:37:21.93#ibcon#read 4, iclass 10, count 0 2006.162.07:37:21.93#ibcon#about to read 5, iclass 10, count 0 2006.162.07:37:21.93#ibcon#read 5, iclass 10, count 0 2006.162.07:37:21.93#ibcon#about to read 6, iclass 10, count 0 2006.162.07:37:21.93#ibcon#read 6, iclass 10, count 0 2006.162.07:37:21.93#ibcon#end of sib2, iclass 10, count 0 2006.162.07:37:21.93#ibcon#*mode == 0, iclass 10, count 0 2006.162.07:37:21.93#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.162.07:37:21.93#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.07:37:21.93#ibcon#*before write, iclass 10, count 0 2006.162.07:37:21.93#ibcon#enter sib2, iclass 10, count 0 2006.162.07:37:21.93#ibcon#flushed, iclass 10, count 0 2006.162.07:37:21.93#ibcon#about to write, iclass 10, count 0 2006.162.07:37:21.93#ibcon#wrote, iclass 10, count 0 2006.162.07:37:21.93#ibcon#about to read 3, iclass 10, count 0 2006.162.07:37:21.97#ibcon#read 3, iclass 10, count 0 2006.162.07:37:21.97#ibcon#about to read 4, iclass 10, count 0 2006.162.07:37:21.97#ibcon#read 4, iclass 10, count 0 2006.162.07:37:21.97#ibcon#about to read 5, iclass 10, count 0 2006.162.07:37:21.97#ibcon#read 5, iclass 10, count 0 2006.162.07:37:21.97#ibcon#about to read 6, iclass 10, count 0 2006.162.07:37:21.97#ibcon#read 6, iclass 10, count 0 2006.162.07:37:21.97#ibcon#end of sib2, iclass 10, count 0 2006.162.07:37:21.97#ibcon#*after write, iclass 10, count 0 2006.162.07:37:21.97#ibcon#*before return 0, iclass 10, count 0 2006.162.07:37:21.97#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.162.07:37:21.97#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.162.07:37:21.97#ibcon#about to clear, iclass 10 cls_cnt 0 2006.162.07:37:21.97#ibcon#cleared, iclass 10 cls_cnt 0 2006.162.07:37:21.97$vc4f8/vb=1,4 2006.162.07:37:21.97#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.162.07:37:21.97#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.162.07:37:21.97#ibcon#ireg 11 cls_cnt 2 2006.162.07:37:21.97#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.162.07:37:21.97#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.162.07:37:21.97#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.162.07:37:21.97#ibcon#enter wrdev, iclass 12, count 2 2006.162.07:37:21.97#ibcon#first serial, iclass 12, count 2 2006.162.07:37:21.97#ibcon#enter sib2, iclass 12, count 2 2006.162.07:37:21.97#ibcon#flushed, iclass 12, count 2 2006.162.07:37:21.97#ibcon#about to write, iclass 12, count 2 2006.162.07:37:21.97#ibcon#wrote, iclass 12, count 2 2006.162.07:37:21.97#ibcon#about to read 3, iclass 12, count 2 2006.162.07:37:21.99#ibcon#read 3, iclass 12, count 2 2006.162.07:37:21.99#ibcon#about to read 4, iclass 12, count 2 2006.162.07:37:21.99#ibcon#read 4, iclass 12, count 2 2006.162.07:37:21.99#ibcon#about to read 5, iclass 12, count 2 2006.162.07:37:21.99#ibcon#read 5, iclass 12, count 2 2006.162.07:37:21.99#ibcon#about to read 6, iclass 12, count 2 2006.162.07:37:21.99#ibcon#read 6, iclass 12, count 2 2006.162.07:37:21.99#ibcon#end of sib2, iclass 12, count 2 2006.162.07:37:21.99#ibcon#*mode == 0, iclass 12, count 2 2006.162.07:37:21.99#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.162.07:37:21.99#ibcon#[27=AT01-04\r\n] 2006.162.07:37:21.99#ibcon#*before write, iclass 12, count 2 2006.162.07:37:21.99#ibcon#enter sib2, iclass 12, count 2 2006.162.07:37:21.99#ibcon#flushed, iclass 12, count 2 2006.162.07:37:21.99#ibcon#about to write, iclass 12, count 2 2006.162.07:37:21.99#ibcon#wrote, iclass 12, count 2 2006.162.07:37:21.99#ibcon#about to read 3, iclass 12, count 2 2006.162.07:37:22.02#ibcon#read 3, iclass 12, count 2 2006.162.07:37:22.02#ibcon#about to read 4, iclass 12, count 2 2006.162.07:37:22.02#ibcon#read 4, iclass 12, count 2 2006.162.07:37:22.02#ibcon#about to read 5, iclass 12, count 2 2006.162.07:37:22.02#ibcon#read 5, iclass 12, count 2 2006.162.07:37:22.02#ibcon#about to read 6, iclass 12, count 2 2006.162.07:37:22.02#ibcon#read 6, iclass 12, count 2 2006.162.07:37:22.02#ibcon#end of sib2, iclass 12, count 2 2006.162.07:37:22.02#ibcon#*after write, iclass 12, count 2 2006.162.07:37:22.02#ibcon#*before return 0, iclass 12, count 2 2006.162.07:37:22.02#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.162.07:37:22.02#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.162.07:37:22.02#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.162.07:37:22.02#ibcon#ireg 7 cls_cnt 0 2006.162.07:37:22.02#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.162.07:37:22.14#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.162.07:37:22.14#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.162.07:37:22.14#ibcon#enter wrdev, iclass 12, count 0 2006.162.07:37:22.14#ibcon#first serial, iclass 12, count 0 2006.162.07:37:22.14#ibcon#enter sib2, iclass 12, count 0 2006.162.07:37:22.14#ibcon#flushed, iclass 12, count 0 2006.162.07:37:22.14#ibcon#about to write, iclass 12, count 0 2006.162.07:37:22.14#ibcon#wrote, iclass 12, count 0 2006.162.07:37:22.14#ibcon#about to read 3, iclass 12, count 0 2006.162.07:37:22.16#ibcon#read 3, iclass 12, count 0 2006.162.07:37:22.16#ibcon#about to read 4, iclass 12, count 0 2006.162.07:37:22.16#ibcon#read 4, iclass 12, count 0 2006.162.07:37:22.16#ibcon#about to read 5, iclass 12, count 0 2006.162.07:37:22.16#ibcon#read 5, iclass 12, count 0 2006.162.07:37:22.16#ibcon#about to read 6, iclass 12, count 0 2006.162.07:37:22.16#ibcon#read 6, iclass 12, count 0 2006.162.07:37:22.16#ibcon#end of sib2, iclass 12, count 0 2006.162.07:37:22.16#ibcon#*mode == 0, iclass 12, count 0 2006.162.07:37:22.16#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.162.07:37:22.16#ibcon#[27=USB\r\n] 2006.162.07:37:22.16#ibcon#*before write, iclass 12, count 0 2006.162.07:37:22.16#ibcon#enter sib2, iclass 12, count 0 2006.162.07:37:22.16#ibcon#flushed, iclass 12, count 0 2006.162.07:37:22.16#ibcon#about to write, iclass 12, count 0 2006.162.07:37:22.16#ibcon#wrote, iclass 12, count 0 2006.162.07:37:22.16#ibcon#about to read 3, iclass 12, count 0 2006.162.07:37:22.19#ibcon#read 3, iclass 12, count 0 2006.162.07:37:22.19#ibcon#about to read 4, iclass 12, count 0 2006.162.07:37:22.19#ibcon#read 4, iclass 12, count 0 2006.162.07:37:22.19#ibcon#about to read 5, iclass 12, count 0 2006.162.07:37:22.19#ibcon#read 5, iclass 12, count 0 2006.162.07:37:22.19#ibcon#about to read 6, iclass 12, count 0 2006.162.07:37:22.19#ibcon#read 6, iclass 12, count 0 2006.162.07:37:22.19#ibcon#end of sib2, iclass 12, count 0 2006.162.07:37:22.19#ibcon#*after write, iclass 12, count 0 2006.162.07:37:22.19#ibcon#*before return 0, iclass 12, count 0 2006.162.07:37:22.19#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.162.07:37:22.19#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.162.07:37:22.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.162.07:37:22.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.162.07:37:22.19$vc4f8/vblo=2,640.99 2006.162.07:37:22.19#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.162.07:37:22.19#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.162.07:37:22.19#ibcon#ireg 17 cls_cnt 0 2006.162.07:37:22.19#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.07:37:22.19#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.07:37:22.19#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.07:37:22.19#ibcon#enter wrdev, iclass 14, count 0 2006.162.07:37:22.19#ibcon#first serial, iclass 14, count 0 2006.162.07:37:22.19#ibcon#enter sib2, iclass 14, count 0 2006.162.07:37:22.19#ibcon#flushed, iclass 14, count 0 2006.162.07:37:22.19#ibcon#about to write, iclass 14, count 0 2006.162.07:37:22.19#ibcon#wrote, iclass 14, count 0 2006.162.07:37:22.19#ibcon#about to read 3, iclass 14, count 0 2006.162.07:37:22.21#ibcon#read 3, iclass 14, count 0 2006.162.07:37:22.21#ibcon#about to read 4, iclass 14, count 0 2006.162.07:37:22.21#ibcon#read 4, iclass 14, count 0 2006.162.07:37:22.21#ibcon#about to read 5, iclass 14, count 0 2006.162.07:37:22.21#ibcon#read 5, iclass 14, count 0 2006.162.07:37:22.21#ibcon#about to read 6, iclass 14, count 0 2006.162.07:37:22.21#ibcon#read 6, iclass 14, count 0 2006.162.07:37:22.21#ibcon#end of sib2, iclass 14, count 0 2006.162.07:37:22.21#ibcon#*mode == 0, iclass 14, count 0 2006.162.07:37:22.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.07:37:22.21#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.07:37:22.21#ibcon#*before write, iclass 14, count 0 2006.162.07:37:22.21#ibcon#enter sib2, iclass 14, count 0 2006.162.07:37:22.21#ibcon#flushed, iclass 14, count 0 2006.162.07:37:22.21#ibcon#about to write, iclass 14, count 0 2006.162.07:37:22.21#ibcon#wrote, iclass 14, count 0 2006.162.07:37:22.21#ibcon#about to read 3, iclass 14, count 0 2006.162.07:37:22.25#ibcon#read 3, iclass 14, count 0 2006.162.07:37:22.25#ibcon#about to read 4, iclass 14, count 0 2006.162.07:37:22.25#ibcon#read 4, iclass 14, count 0 2006.162.07:37:22.25#ibcon#about to read 5, iclass 14, count 0 2006.162.07:37:22.25#ibcon#read 5, iclass 14, count 0 2006.162.07:37:22.25#ibcon#about to read 6, iclass 14, count 0 2006.162.07:37:22.25#ibcon#read 6, iclass 14, count 0 2006.162.07:37:22.25#ibcon#end of sib2, iclass 14, count 0 2006.162.07:37:22.25#ibcon#*after write, iclass 14, count 0 2006.162.07:37:22.25#ibcon#*before return 0, iclass 14, count 0 2006.162.07:37:22.25#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.07:37:22.25#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.162.07:37:22.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.07:37:22.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.07:37:22.25$vc4f8/vb=2,4 2006.162.07:37:22.25#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.162.07:37:22.25#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.162.07:37:22.25#ibcon#ireg 11 cls_cnt 2 2006.162.07:37:22.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.162.07:37:22.31#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.162.07:37:22.31#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.162.07:37:22.31#ibcon#enter wrdev, iclass 16, count 2 2006.162.07:37:22.31#ibcon#first serial, iclass 16, count 2 2006.162.07:37:22.31#ibcon#enter sib2, iclass 16, count 2 2006.162.07:37:22.31#ibcon#flushed, iclass 16, count 2 2006.162.07:37:22.31#ibcon#about to write, iclass 16, count 2 2006.162.07:37:22.31#ibcon#wrote, iclass 16, count 2 2006.162.07:37:22.31#ibcon#about to read 3, iclass 16, count 2 2006.162.07:37:22.33#ibcon#read 3, iclass 16, count 2 2006.162.07:37:22.33#ibcon#about to read 4, iclass 16, count 2 2006.162.07:37:22.33#ibcon#read 4, iclass 16, count 2 2006.162.07:37:22.33#ibcon#about to read 5, iclass 16, count 2 2006.162.07:37:22.33#ibcon#read 5, iclass 16, count 2 2006.162.07:37:22.33#ibcon#about to read 6, iclass 16, count 2 2006.162.07:37:22.33#ibcon#read 6, iclass 16, count 2 2006.162.07:37:22.33#ibcon#end of sib2, iclass 16, count 2 2006.162.07:37:22.33#ibcon#*mode == 0, iclass 16, count 2 2006.162.07:37:22.33#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.162.07:37:22.33#ibcon#[27=AT02-04\r\n] 2006.162.07:37:22.33#ibcon#*before write, iclass 16, count 2 2006.162.07:37:22.33#ibcon#enter sib2, iclass 16, count 2 2006.162.07:37:22.33#ibcon#flushed, iclass 16, count 2 2006.162.07:37:22.33#ibcon#about to write, iclass 16, count 2 2006.162.07:37:22.33#ibcon#wrote, iclass 16, count 2 2006.162.07:37:22.33#ibcon#about to read 3, iclass 16, count 2 2006.162.07:37:22.36#ibcon#read 3, iclass 16, count 2 2006.162.07:37:22.36#ibcon#about to read 4, iclass 16, count 2 2006.162.07:37:22.36#ibcon#read 4, iclass 16, count 2 2006.162.07:37:22.36#ibcon#about to read 5, iclass 16, count 2 2006.162.07:37:22.36#ibcon#read 5, iclass 16, count 2 2006.162.07:37:22.36#ibcon#about to read 6, iclass 16, count 2 2006.162.07:37:22.36#ibcon#read 6, iclass 16, count 2 2006.162.07:37:22.36#ibcon#end of sib2, iclass 16, count 2 2006.162.07:37:22.36#ibcon#*after write, iclass 16, count 2 2006.162.07:37:22.36#ibcon#*before return 0, iclass 16, count 2 2006.162.07:37:22.36#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.162.07:37:22.36#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.162.07:37:22.36#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.162.07:37:22.36#ibcon#ireg 7 cls_cnt 0 2006.162.07:37:22.36#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.162.07:37:22.48#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.162.07:37:22.48#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.162.07:37:22.48#ibcon#enter wrdev, iclass 16, count 0 2006.162.07:37:22.48#ibcon#first serial, iclass 16, count 0 2006.162.07:37:22.48#ibcon#enter sib2, iclass 16, count 0 2006.162.07:37:22.48#ibcon#flushed, iclass 16, count 0 2006.162.07:37:22.48#ibcon#about to write, iclass 16, count 0 2006.162.07:37:22.48#ibcon#wrote, iclass 16, count 0 2006.162.07:37:22.48#ibcon#about to read 3, iclass 16, count 0 2006.162.07:37:22.50#ibcon#read 3, iclass 16, count 0 2006.162.07:37:22.50#ibcon#about to read 4, iclass 16, count 0 2006.162.07:37:22.50#ibcon#read 4, iclass 16, count 0 2006.162.07:37:22.50#ibcon#about to read 5, iclass 16, count 0 2006.162.07:37:22.50#ibcon#read 5, iclass 16, count 0 2006.162.07:37:22.50#ibcon#about to read 6, iclass 16, count 0 2006.162.07:37:22.50#ibcon#read 6, iclass 16, count 0 2006.162.07:37:22.50#ibcon#end of sib2, iclass 16, count 0 2006.162.07:37:22.50#ibcon#*mode == 0, iclass 16, count 0 2006.162.07:37:22.50#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.162.07:37:22.50#ibcon#[27=USB\r\n] 2006.162.07:37:22.50#ibcon#*before write, iclass 16, count 0 2006.162.07:37:22.50#ibcon#enter sib2, iclass 16, count 0 2006.162.07:37:22.50#ibcon#flushed, iclass 16, count 0 2006.162.07:37:22.50#ibcon#about to write, iclass 16, count 0 2006.162.07:37:22.50#ibcon#wrote, iclass 16, count 0 2006.162.07:37:22.50#ibcon#about to read 3, iclass 16, count 0 2006.162.07:37:22.53#ibcon#read 3, iclass 16, count 0 2006.162.07:37:22.53#ibcon#about to read 4, iclass 16, count 0 2006.162.07:37:22.53#ibcon#read 4, iclass 16, count 0 2006.162.07:37:22.53#ibcon#about to read 5, iclass 16, count 0 2006.162.07:37:22.53#ibcon#read 5, iclass 16, count 0 2006.162.07:37:22.53#ibcon#about to read 6, iclass 16, count 0 2006.162.07:37:22.53#ibcon#read 6, iclass 16, count 0 2006.162.07:37:22.53#ibcon#end of sib2, iclass 16, count 0 2006.162.07:37:22.53#ibcon#*after write, iclass 16, count 0 2006.162.07:37:22.53#ibcon#*before return 0, iclass 16, count 0 2006.162.07:37:22.53#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.162.07:37:22.53#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.162.07:37:22.53#ibcon#about to clear, iclass 16 cls_cnt 0 2006.162.07:37:22.53#ibcon#cleared, iclass 16 cls_cnt 0 2006.162.07:37:22.53$vc4f8/vblo=3,656.99 2006.162.07:37:22.53#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.162.07:37:22.53#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.162.07:37:22.53#ibcon#ireg 17 cls_cnt 0 2006.162.07:37:22.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:37:22.53#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:37:22.53#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:37:22.53#ibcon#enter wrdev, iclass 18, count 0 2006.162.07:37:22.53#ibcon#first serial, iclass 18, count 0 2006.162.07:37:22.53#ibcon#enter sib2, iclass 18, count 0 2006.162.07:37:22.53#ibcon#flushed, iclass 18, count 0 2006.162.07:37:22.53#ibcon#about to write, iclass 18, count 0 2006.162.07:37:22.53#ibcon#wrote, iclass 18, count 0 2006.162.07:37:22.53#ibcon#about to read 3, iclass 18, count 0 2006.162.07:37:22.55#ibcon#read 3, iclass 18, count 0 2006.162.07:37:22.55#ibcon#about to read 4, iclass 18, count 0 2006.162.07:37:22.55#ibcon#read 4, iclass 18, count 0 2006.162.07:37:22.55#ibcon#about to read 5, iclass 18, count 0 2006.162.07:37:22.55#ibcon#read 5, iclass 18, count 0 2006.162.07:37:22.55#ibcon#about to read 6, iclass 18, count 0 2006.162.07:37:22.55#ibcon#read 6, iclass 18, count 0 2006.162.07:37:22.55#ibcon#end of sib2, iclass 18, count 0 2006.162.07:37:22.55#ibcon#*mode == 0, iclass 18, count 0 2006.162.07:37:22.55#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.162.07:37:22.55#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.07:37:22.55#ibcon#*before write, iclass 18, count 0 2006.162.07:37:22.55#ibcon#enter sib2, iclass 18, count 0 2006.162.07:37:22.55#ibcon#flushed, iclass 18, count 0 2006.162.07:37:22.55#ibcon#about to write, iclass 18, count 0 2006.162.07:37:22.55#ibcon#wrote, iclass 18, count 0 2006.162.07:37:22.55#ibcon#about to read 3, iclass 18, count 0 2006.162.07:37:22.59#ibcon#read 3, iclass 18, count 0 2006.162.07:37:22.59#ibcon#about to read 4, iclass 18, count 0 2006.162.07:37:22.59#ibcon#read 4, iclass 18, count 0 2006.162.07:37:22.59#ibcon#about to read 5, iclass 18, count 0 2006.162.07:37:22.59#ibcon#read 5, iclass 18, count 0 2006.162.07:37:22.59#ibcon#about to read 6, iclass 18, count 0 2006.162.07:37:22.59#ibcon#read 6, iclass 18, count 0 2006.162.07:37:22.59#ibcon#end of sib2, iclass 18, count 0 2006.162.07:37:22.59#ibcon#*after write, iclass 18, count 0 2006.162.07:37:22.59#ibcon#*before return 0, iclass 18, count 0 2006.162.07:37:22.59#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:37:22.59#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:37:22.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.162.07:37:22.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.162.07:37:22.59$vc4f8/vb=3,4 2006.162.07:37:22.59#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.162.07:37:22.59#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.162.07:37:22.59#ibcon#ireg 11 cls_cnt 2 2006.162.07:37:22.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:37:22.65#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:37:22.65#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:37:22.65#ibcon#enter wrdev, iclass 20, count 2 2006.162.07:37:22.65#ibcon#first serial, iclass 20, count 2 2006.162.07:37:22.65#ibcon#enter sib2, iclass 20, count 2 2006.162.07:37:22.65#ibcon#flushed, iclass 20, count 2 2006.162.07:37:22.65#ibcon#about to write, iclass 20, count 2 2006.162.07:37:22.65#ibcon#wrote, iclass 20, count 2 2006.162.07:37:22.65#ibcon#about to read 3, iclass 20, count 2 2006.162.07:37:22.67#ibcon#read 3, iclass 20, count 2 2006.162.07:37:22.67#ibcon#about to read 4, iclass 20, count 2 2006.162.07:37:22.67#ibcon#read 4, iclass 20, count 2 2006.162.07:37:22.67#ibcon#about to read 5, iclass 20, count 2 2006.162.07:37:22.67#ibcon#read 5, iclass 20, count 2 2006.162.07:37:22.67#ibcon#about to read 6, iclass 20, count 2 2006.162.07:37:22.67#ibcon#read 6, iclass 20, count 2 2006.162.07:37:22.67#ibcon#end of sib2, iclass 20, count 2 2006.162.07:37:22.67#ibcon#*mode == 0, iclass 20, count 2 2006.162.07:37:22.67#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.162.07:37:22.67#ibcon#[27=AT03-04\r\n] 2006.162.07:37:22.67#ibcon#*before write, iclass 20, count 2 2006.162.07:37:22.67#ibcon#enter sib2, iclass 20, count 2 2006.162.07:37:22.67#ibcon#flushed, iclass 20, count 2 2006.162.07:37:22.67#ibcon#about to write, iclass 20, count 2 2006.162.07:37:22.67#ibcon#wrote, iclass 20, count 2 2006.162.07:37:22.67#ibcon#about to read 3, iclass 20, count 2 2006.162.07:37:22.70#ibcon#read 3, iclass 20, count 2 2006.162.07:37:22.70#ibcon#about to read 4, iclass 20, count 2 2006.162.07:37:22.70#ibcon#read 4, iclass 20, count 2 2006.162.07:37:22.70#ibcon#about to read 5, iclass 20, count 2 2006.162.07:37:22.70#ibcon#read 5, iclass 20, count 2 2006.162.07:37:22.70#ibcon#about to read 6, iclass 20, count 2 2006.162.07:37:22.70#ibcon#read 6, iclass 20, count 2 2006.162.07:37:22.70#ibcon#end of sib2, iclass 20, count 2 2006.162.07:37:22.70#ibcon#*after write, iclass 20, count 2 2006.162.07:37:22.70#ibcon#*before return 0, iclass 20, count 2 2006.162.07:37:22.70#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:37:22.70#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:37:22.70#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.162.07:37:22.70#ibcon#ireg 7 cls_cnt 0 2006.162.07:37:22.70#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:37:22.82#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:37:22.82#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:37:22.82#ibcon#enter wrdev, iclass 20, count 0 2006.162.07:37:22.82#ibcon#first serial, iclass 20, count 0 2006.162.07:37:22.82#ibcon#enter sib2, iclass 20, count 0 2006.162.07:37:22.82#ibcon#flushed, iclass 20, count 0 2006.162.07:37:22.82#ibcon#about to write, iclass 20, count 0 2006.162.07:37:22.82#ibcon#wrote, iclass 20, count 0 2006.162.07:37:22.82#ibcon#about to read 3, iclass 20, count 0 2006.162.07:37:22.84#ibcon#read 3, iclass 20, count 0 2006.162.07:37:22.84#ibcon#about to read 4, iclass 20, count 0 2006.162.07:37:22.84#ibcon#read 4, iclass 20, count 0 2006.162.07:37:22.84#ibcon#about to read 5, iclass 20, count 0 2006.162.07:37:22.84#ibcon#read 5, iclass 20, count 0 2006.162.07:37:22.84#ibcon#about to read 6, iclass 20, count 0 2006.162.07:37:22.84#ibcon#read 6, iclass 20, count 0 2006.162.07:37:22.84#ibcon#end of sib2, iclass 20, count 0 2006.162.07:37:22.84#ibcon#*mode == 0, iclass 20, count 0 2006.162.07:37:22.84#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.07:37:22.84#ibcon#[27=USB\r\n] 2006.162.07:37:22.84#ibcon#*before write, iclass 20, count 0 2006.162.07:37:22.84#ibcon#enter sib2, iclass 20, count 0 2006.162.07:37:22.84#ibcon#flushed, iclass 20, count 0 2006.162.07:37:22.84#ibcon#about to write, iclass 20, count 0 2006.162.07:37:22.84#ibcon#wrote, iclass 20, count 0 2006.162.07:37:22.84#ibcon#about to read 3, iclass 20, count 0 2006.162.07:37:22.87#ibcon#read 3, iclass 20, count 0 2006.162.07:37:22.87#ibcon#about to read 4, iclass 20, count 0 2006.162.07:37:22.87#ibcon#read 4, iclass 20, count 0 2006.162.07:37:22.87#ibcon#about to read 5, iclass 20, count 0 2006.162.07:37:22.87#ibcon#read 5, iclass 20, count 0 2006.162.07:37:22.87#ibcon#about to read 6, iclass 20, count 0 2006.162.07:37:22.87#ibcon#read 6, iclass 20, count 0 2006.162.07:37:22.87#ibcon#end of sib2, iclass 20, count 0 2006.162.07:37:22.87#ibcon#*after write, iclass 20, count 0 2006.162.07:37:22.87#ibcon#*before return 0, iclass 20, count 0 2006.162.07:37:22.87#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:37:22.87#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:37:22.87#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.07:37:22.87#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.07:37:22.87$vc4f8/vblo=4,712.99 2006.162.07:37:22.87#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.162.07:37:22.87#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.162.07:37:22.87#ibcon#ireg 17 cls_cnt 0 2006.162.07:37:22.87#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:37:22.87#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:37:22.87#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:37:22.87#ibcon#enter wrdev, iclass 22, count 0 2006.162.07:37:22.87#ibcon#first serial, iclass 22, count 0 2006.162.07:37:22.87#ibcon#enter sib2, iclass 22, count 0 2006.162.07:37:22.87#ibcon#flushed, iclass 22, count 0 2006.162.07:37:22.87#ibcon#about to write, iclass 22, count 0 2006.162.07:37:22.87#ibcon#wrote, iclass 22, count 0 2006.162.07:37:22.87#ibcon#about to read 3, iclass 22, count 0 2006.162.07:37:22.89#ibcon#read 3, iclass 22, count 0 2006.162.07:37:22.89#ibcon#about to read 4, iclass 22, count 0 2006.162.07:37:22.89#ibcon#read 4, iclass 22, count 0 2006.162.07:37:22.89#ibcon#about to read 5, iclass 22, count 0 2006.162.07:37:22.89#ibcon#read 5, iclass 22, count 0 2006.162.07:37:22.89#ibcon#about to read 6, iclass 22, count 0 2006.162.07:37:22.89#ibcon#read 6, iclass 22, count 0 2006.162.07:37:22.89#ibcon#end of sib2, iclass 22, count 0 2006.162.07:37:22.89#ibcon#*mode == 0, iclass 22, count 0 2006.162.07:37:22.89#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.07:37:22.89#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.07:37:22.89#ibcon#*before write, iclass 22, count 0 2006.162.07:37:22.89#ibcon#enter sib2, iclass 22, count 0 2006.162.07:37:22.89#ibcon#flushed, iclass 22, count 0 2006.162.07:37:22.89#ibcon#about to write, iclass 22, count 0 2006.162.07:37:22.89#ibcon#wrote, iclass 22, count 0 2006.162.07:37:22.89#ibcon#about to read 3, iclass 22, count 0 2006.162.07:37:22.93#ibcon#read 3, iclass 22, count 0 2006.162.07:37:22.93#ibcon#about to read 4, iclass 22, count 0 2006.162.07:37:22.93#ibcon#read 4, iclass 22, count 0 2006.162.07:37:22.93#ibcon#about to read 5, iclass 22, count 0 2006.162.07:37:22.93#ibcon#read 5, iclass 22, count 0 2006.162.07:37:22.93#ibcon#about to read 6, iclass 22, count 0 2006.162.07:37:22.93#ibcon#read 6, iclass 22, count 0 2006.162.07:37:22.93#ibcon#end of sib2, iclass 22, count 0 2006.162.07:37:22.93#ibcon#*after write, iclass 22, count 0 2006.162.07:37:22.93#ibcon#*before return 0, iclass 22, count 0 2006.162.07:37:22.93#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:37:22.93#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:37:22.93#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.07:37:22.93#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.07:37:22.93$vc4f8/vb=4,4 2006.162.07:37:22.93#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.162.07:37:22.93#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.162.07:37:22.93#ibcon#ireg 11 cls_cnt 2 2006.162.07:37:22.93#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:37:22.99#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:37:22.99#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:37:22.99#ibcon#enter wrdev, iclass 24, count 2 2006.162.07:37:22.99#ibcon#first serial, iclass 24, count 2 2006.162.07:37:22.99#ibcon#enter sib2, iclass 24, count 2 2006.162.07:37:22.99#ibcon#flushed, iclass 24, count 2 2006.162.07:37:22.99#ibcon#about to write, iclass 24, count 2 2006.162.07:37:22.99#ibcon#wrote, iclass 24, count 2 2006.162.07:37:22.99#ibcon#about to read 3, iclass 24, count 2 2006.162.07:37:23.01#ibcon#read 3, iclass 24, count 2 2006.162.07:37:23.01#ibcon#about to read 4, iclass 24, count 2 2006.162.07:37:23.01#ibcon#read 4, iclass 24, count 2 2006.162.07:37:23.01#ibcon#about to read 5, iclass 24, count 2 2006.162.07:37:23.01#ibcon#read 5, iclass 24, count 2 2006.162.07:37:23.01#ibcon#about to read 6, iclass 24, count 2 2006.162.07:37:23.01#ibcon#read 6, iclass 24, count 2 2006.162.07:37:23.01#ibcon#end of sib2, iclass 24, count 2 2006.162.07:37:23.01#ibcon#*mode == 0, iclass 24, count 2 2006.162.07:37:23.01#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.162.07:37:23.01#ibcon#[27=AT04-04\r\n] 2006.162.07:37:23.01#ibcon#*before write, iclass 24, count 2 2006.162.07:37:23.01#ibcon#enter sib2, iclass 24, count 2 2006.162.07:37:23.01#ibcon#flushed, iclass 24, count 2 2006.162.07:37:23.01#ibcon#about to write, iclass 24, count 2 2006.162.07:37:23.01#ibcon#wrote, iclass 24, count 2 2006.162.07:37:23.01#ibcon#about to read 3, iclass 24, count 2 2006.162.07:37:23.04#ibcon#read 3, iclass 24, count 2 2006.162.07:37:23.04#ibcon#about to read 4, iclass 24, count 2 2006.162.07:37:23.04#ibcon#read 4, iclass 24, count 2 2006.162.07:37:23.04#ibcon#about to read 5, iclass 24, count 2 2006.162.07:37:23.04#ibcon#read 5, iclass 24, count 2 2006.162.07:37:23.04#ibcon#about to read 6, iclass 24, count 2 2006.162.07:37:23.04#ibcon#read 6, iclass 24, count 2 2006.162.07:37:23.04#ibcon#end of sib2, iclass 24, count 2 2006.162.07:37:23.04#ibcon#*after write, iclass 24, count 2 2006.162.07:37:23.04#ibcon#*before return 0, iclass 24, count 2 2006.162.07:37:23.04#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:37:23.04#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:37:23.04#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.162.07:37:23.04#ibcon#ireg 7 cls_cnt 0 2006.162.07:37:23.04#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:37:23.16#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:37:23.16#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:37:23.16#ibcon#enter wrdev, iclass 24, count 0 2006.162.07:37:23.16#ibcon#first serial, iclass 24, count 0 2006.162.07:37:23.16#ibcon#enter sib2, iclass 24, count 0 2006.162.07:37:23.16#ibcon#flushed, iclass 24, count 0 2006.162.07:37:23.16#ibcon#about to write, iclass 24, count 0 2006.162.07:37:23.16#ibcon#wrote, iclass 24, count 0 2006.162.07:37:23.16#ibcon#about to read 3, iclass 24, count 0 2006.162.07:37:23.18#ibcon#read 3, iclass 24, count 0 2006.162.07:37:23.18#ibcon#about to read 4, iclass 24, count 0 2006.162.07:37:23.18#ibcon#read 4, iclass 24, count 0 2006.162.07:37:23.18#ibcon#about to read 5, iclass 24, count 0 2006.162.07:37:23.18#ibcon#read 5, iclass 24, count 0 2006.162.07:37:23.18#ibcon#about to read 6, iclass 24, count 0 2006.162.07:37:23.18#ibcon#read 6, iclass 24, count 0 2006.162.07:37:23.18#ibcon#end of sib2, iclass 24, count 0 2006.162.07:37:23.18#ibcon#*mode == 0, iclass 24, count 0 2006.162.07:37:23.18#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.07:37:23.18#ibcon#[27=USB\r\n] 2006.162.07:37:23.18#ibcon#*before write, iclass 24, count 0 2006.162.07:37:23.18#ibcon#enter sib2, iclass 24, count 0 2006.162.07:37:23.18#ibcon#flushed, iclass 24, count 0 2006.162.07:37:23.18#ibcon#about to write, iclass 24, count 0 2006.162.07:37:23.18#ibcon#wrote, iclass 24, count 0 2006.162.07:37:23.18#ibcon#about to read 3, iclass 24, count 0 2006.162.07:37:23.21#ibcon#read 3, iclass 24, count 0 2006.162.07:37:23.21#ibcon#about to read 4, iclass 24, count 0 2006.162.07:37:23.21#ibcon#read 4, iclass 24, count 0 2006.162.07:37:23.21#ibcon#about to read 5, iclass 24, count 0 2006.162.07:37:23.21#ibcon#read 5, iclass 24, count 0 2006.162.07:37:23.21#ibcon#about to read 6, iclass 24, count 0 2006.162.07:37:23.21#ibcon#read 6, iclass 24, count 0 2006.162.07:37:23.21#ibcon#end of sib2, iclass 24, count 0 2006.162.07:37:23.21#ibcon#*after write, iclass 24, count 0 2006.162.07:37:23.21#ibcon#*before return 0, iclass 24, count 0 2006.162.07:37:23.21#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:37:23.21#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:37:23.21#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.07:37:23.21#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.07:37:23.21$vc4f8/vblo=5,744.99 2006.162.07:37:23.21#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.162.07:37:23.21#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.162.07:37:23.21#ibcon#ireg 17 cls_cnt 0 2006.162.07:37:23.21#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:37:23.21#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:37:23.21#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:37:23.21#ibcon#enter wrdev, iclass 26, count 0 2006.162.07:37:23.21#ibcon#first serial, iclass 26, count 0 2006.162.07:37:23.21#ibcon#enter sib2, iclass 26, count 0 2006.162.07:37:23.21#ibcon#flushed, iclass 26, count 0 2006.162.07:37:23.21#ibcon#about to write, iclass 26, count 0 2006.162.07:37:23.21#ibcon#wrote, iclass 26, count 0 2006.162.07:37:23.21#ibcon#about to read 3, iclass 26, count 0 2006.162.07:37:23.23#ibcon#read 3, iclass 26, count 0 2006.162.07:37:23.23#ibcon#about to read 4, iclass 26, count 0 2006.162.07:37:23.23#ibcon#read 4, iclass 26, count 0 2006.162.07:37:23.23#ibcon#about to read 5, iclass 26, count 0 2006.162.07:37:23.23#ibcon#read 5, iclass 26, count 0 2006.162.07:37:23.23#ibcon#about to read 6, iclass 26, count 0 2006.162.07:37:23.23#ibcon#read 6, iclass 26, count 0 2006.162.07:37:23.23#ibcon#end of sib2, iclass 26, count 0 2006.162.07:37:23.23#ibcon#*mode == 0, iclass 26, count 0 2006.162.07:37:23.23#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.162.07:37:23.23#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.07:37:23.23#ibcon#*before write, iclass 26, count 0 2006.162.07:37:23.23#ibcon#enter sib2, iclass 26, count 0 2006.162.07:37:23.23#ibcon#flushed, iclass 26, count 0 2006.162.07:37:23.23#ibcon#about to write, iclass 26, count 0 2006.162.07:37:23.23#ibcon#wrote, iclass 26, count 0 2006.162.07:37:23.23#ibcon#about to read 3, iclass 26, count 0 2006.162.07:37:23.27#ibcon#read 3, iclass 26, count 0 2006.162.07:37:23.27#ibcon#about to read 4, iclass 26, count 0 2006.162.07:37:23.27#ibcon#read 4, iclass 26, count 0 2006.162.07:37:23.27#ibcon#about to read 5, iclass 26, count 0 2006.162.07:37:23.27#ibcon#read 5, iclass 26, count 0 2006.162.07:37:23.27#ibcon#about to read 6, iclass 26, count 0 2006.162.07:37:23.27#ibcon#read 6, iclass 26, count 0 2006.162.07:37:23.27#ibcon#end of sib2, iclass 26, count 0 2006.162.07:37:23.27#ibcon#*after write, iclass 26, count 0 2006.162.07:37:23.27#ibcon#*before return 0, iclass 26, count 0 2006.162.07:37:23.27#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:37:23.27#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:37:23.27#ibcon#about to clear, iclass 26 cls_cnt 0 2006.162.07:37:23.27#ibcon#cleared, iclass 26 cls_cnt 0 2006.162.07:37:23.27$vc4f8/vb=5,4 2006.162.07:37:23.27#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.162.07:37:23.27#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.162.07:37:23.27#ibcon#ireg 11 cls_cnt 2 2006.162.07:37:23.27#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.162.07:37:23.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.162.07:37:23.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.162.07:37:23.33#ibcon#enter wrdev, iclass 28, count 2 2006.162.07:37:23.33#ibcon#first serial, iclass 28, count 2 2006.162.07:37:23.33#ibcon#enter sib2, iclass 28, count 2 2006.162.07:37:23.33#ibcon#flushed, iclass 28, count 2 2006.162.07:37:23.33#ibcon#about to write, iclass 28, count 2 2006.162.07:37:23.33#ibcon#wrote, iclass 28, count 2 2006.162.07:37:23.33#ibcon#about to read 3, iclass 28, count 2 2006.162.07:37:23.35#ibcon#read 3, iclass 28, count 2 2006.162.07:37:23.35#ibcon#about to read 4, iclass 28, count 2 2006.162.07:37:23.35#ibcon#read 4, iclass 28, count 2 2006.162.07:37:23.35#ibcon#about to read 5, iclass 28, count 2 2006.162.07:37:23.35#ibcon#read 5, iclass 28, count 2 2006.162.07:37:23.35#ibcon#about to read 6, iclass 28, count 2 2006.162.07:37:23.35#ibcon#read 6, iclass 28, count 2 2006.162.07:37:23.35#ibcon#end of sib2, iclass 28, count 2 2006.162.07:37:23.35#ibcon#*mode == 0, iclass 28, count 2 2006.162.07:37:23.35#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.162.07:37:23.35#ibcon#[27=AT05-04\r\n] 2006.162.07:37:23.35#ibcon#*before write, iclass 28, count 2 2006.162.07:37:23.35#ibcon#enter sib2, iclass 28, count 2 2006.162.07:37:23.35#ibcon#flushed, iclass 28, count 2 2006.162.07:37:23.35#ibcon#about to write, iclass 28, count 2 2006.162.07:37:23.35#ibcon#wrote, iclass 28, count 2 2006.162.07:37:23.35#ibcon#about to read 3, iclass 28, count 2 2006.162.07:37:23.38#ibcon#read 3, iclass 28, count 2 2006.162.07:37:23.38#ibcon#about to read 4, iclass 28, count 2 2006.162.07:37:23.38#ibcon#read 4, iclass 28, count 2 2006.162.07:37:23.38#ibcon#about to read 5, iclass 28, count 2 2006.162.07:37:23.38#ibcon#read 5, iclass 28, count 2 2006.162.07:37:23.38#ibcon#about to read 6, iclass 28, count 2 2006.162.07:37:23.38#ibcon#read 6, iclass 28, count 2 2006.162.07:37:23.38#ibcon#end of sib2, iclass 28, count 2 2006.162.07:37:23.38#ibcon#*after write, iclass 28, count 2 2006.162.07:37:23.38#ibcon#*before return 0, iclass 28, count 2 2006.162.07:37:23.38#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.162.07:37:23.38#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.162.07:37:23.38#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.162.07:37:23.38#ibcon#ireg 7 cls_cnt 0 2006.162.07:37:23.38#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.162.07:37:23.50#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.162.07:37:23.50#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.162.07:37:23.50#ibcon#enter wrdev, iclass 28, count 0 2006.162.07:37:23.50#ibcon#first serial, iclass 28, count 0 2006.162.07:37:23.50#ibcon#enter sib2, iclass 28, count 0 2006.162.07:37:23.50#ibcon#flushed, iclass 28, count 0 2006.162.07:37:23.50#ibcon#about to write, iclass 28, count 0 2006.162.07:37:23.50#ibcon#wrote, iclass 28, count 0 2006.162.07:37:23.50#ibcon#about to read 3, iclass 28, count 0 2006.162.07:37:23.52#ibcon#read 3, iclass 28, count 0 2006.162.07:37:23.52#ibcon#about to read 4, iclass 28, count 0 2006.162.07:37:23.52#ibcon#read 4, iclass 28, count 0 2006.162.07:37:23.52#ibcon#about to read 5, iclass 28, count 0 2006.162.07:37:23.52#ibcon#read 5, iclass 28, count 0 2006.162.07:37:23.52#ibcon#about to read 6, iclass 28, count 0 2006.162.07:37:23.52#ibcon#read 6, iclass 28, count 0 2006.162.07:37:23.52#ibcon#end of sib2, iclass 28, count 0 2006.162.07:37:23.52#ibcon#*mode == 0, iclass 28, count 0 2006.162.07:37:23.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.162.07:37:23.52#ibcon#[27=USB\r\n] 2006.162.07:37:23.52#ibcon#*before write, iclass 28, count 0 2006.162.07:37:23.52#ibcon#enter sib2, iclass 28, count 0 2006.162.07:37:23.52#ibcon#flushed, iclass 28, count 0 2006.162.07:37:23.52#ibcon#about to write, iclass 28, count 0 2006.162.07:37:23.52#ibcon#wrote, iclass 28, count 0 2006.162.07:37:23.52#ibcon#about to read 3, iclass 28, count 0 2006.162.07:37:23.55#ibcon#read 3, iclass 28, count 0 2006.162.07:37:23.55#ibcon#about to read 4, iclass 28, count 0 2006.162.07:37:23.55#ibcon#read 4, iclass 28, count 0 2006.162.07:37:23.55#ibcon#about to read 5, iclass 28, count 0 2006.162.07:37:23.55#ibcon#read 5, iclass 28, count 0 2006.162.07:37:23.55#ibcon#about to read 6, iclass 28, count 0 2006.162.07:37:23.55#ibcon#read 6, iclass 28, count 0 2006.162.07:37:23.55#ibcon#end of sib2, iclass 28, count 0 2006.162.07:37:23.55#ibcon#*after write, iclass 28, count 0 2006.162.07:37:23.55#ibcon#*before return 0, iclass 28, count 0 2006.162.07:37:23.55#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.162.07:37:23.55#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.162.07:37:23.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.162.07:37:23.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.162.07:37:23.55$vc4f8/vblo=6,752.99 2006.162.07:37:23.55#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.162.07:37:23.55#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.162.07:37:23.55#ibcon#ireg 17 cls_cnt 0 2006.162.07:37:23.55#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.162.07:37:23.55#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.162.07:37:23.55#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.162.07:37:23.55#ibcon#enter wrdev, iclass 30, count 0 2006.162.07:37:23.55#ibcon#first serial, iclass 30, count 0 2006.162.07:37:23.55#ibcon#enter sib2, iclass 30, count 0 2006.162.07:37:23.55#ibcon#flushed, iclass 30, count 0 2006.162.07:37:23.55#ibcon#about to write, iclass 30, count 0 2006.162.07:37:23.55#ibcon#wrote, iclass 30, count 0 2006.162.07:37:23.55#ibcon#about to read 3, iclass 30, count 0 2006.162.07:37:23.57#ibcon#read 3, iclass 30, count 0 2006.162.07:37:23.57#ibcon#about to read 4, iclass 30, count 0 2006.162.07:37:23.57#ibcon#read 4, iclass 30, count 0 2006.162.07:37:23.57#ibcon#about to read 5, iclass 30, count 0 2006.162.07:37:23.57#ibcon#read 5, iclass 30, count 0 2006.162.07:37:23.57#ibcon#about to read 6, iclass 30, count 0 2006.162.07:37:23.57#ibcon#read 6, iclass 30, count 0 2006.162.07:37:23.57#ibcon#end of sib2, iclass 30, count 0 2006.162.07:37:23.57#ibcon#*mode == 0, iclass 30, count 0 2006.162.07:37:23.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.162.07:37:23.57#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.07:37:23.57#ibcon#*before write, iclass 30, count 0 2006.162.07:37:23.57#ibcon#enter sib2, iclass 30, count 0 2006.162.07:37:23.57#ibcon#flushed, iclass 30, count 0 2006.162.07:37:23.57#ibcon#about to write, iclass 30, count 0 2006.162.07:37:23.57#ibcon#wrote, iclass 30, count 0 2006.162.07:37:23.57#ibcon#about to read 3, iclass 30, count 0 2006.162.07:37:23.61#ibcon#read 3, iclass 30, count 0 2006.162.07:37:23.61#ibcon#about to read 4, iclass 30, count 0 2006.162.07:37:23.61#ibcon#read 4, iclass 30, count 0 2006.162.07:37:23.61#ibcon#about to read 5, iclass 30, count 0 2006.162.07:37:23.61#ibcon#read 5, iclass 30, count 0 2006.162.07:37:23.61#ibcon#about to read 6, iclass 30, count 0 2006.162.07:37:23.61#ibcon#read 6, iclass 30, count 0 2006.162.07:37:23.61#ibcon#end of sib2, iclass 30, count 0 2006.162.07:37:23.61#ibcon#*after write, iclass 30, count 0 2006.162.07:37:23.61#ibcon#*before return 0, iclass 30, count 0 2006.162.07:37:23.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.162.07:37:23.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.162.07:37:23.61#ibcon#about to clear, iclass 30 cls_cnt 0 2006.162.07:37:23.61#ibcon#cleared, iclass 30 cls_cnt 0 2006.162.07:37:23.61$vc4f8/vb=6,4 2006.162.07:37:23.61#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.162.07:37:23.61#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.162.07:37:23.61#ibcon#ireg 11 cls_cnt 2 2006.162.07:37:23.61#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.162.07:37:23.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.162.07:37:23.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.162.07:37:23.67#ibcon#enter wrdev, iclass 32, count 2 2006.162.07:37:23.67#ibcon#first serial, iclass 32, count 2 2006.162.07:37:23.67#ibcon#enter sib2, iclass 32, count 2 2006.162.07:37:23.67#ibcon#flushed, iclass 32, count 2 2006.162.07:37:23.67#ibcon#about to write, iclass 32, count 2 2006.162.07:37:23.67#ibcon#wrote, iclass 32, count 2 2006.162.07:37:23.67#ibcon#about to read 3, iclass 32, count 2 2006.162.07:37:23.69#ibcon#read 3, iclass 32, count 2 2006.162.07:37:23.69#ibcon#about to read 4, iclass 32, count 2 2006.162.07:37:23.69#ibcon#read 4, iclass 32, count 2 2006.162.07:37:23.69#ibcon#about to read 5, iclass 32, count 2 2006.162.07:37:23.69#ibcon#read 5, iclass 32, count 2 2006.162.07:37:23.69#ibcon#about to read 6, iclass 32, count 2 2006.162.07:37:23.69#ibcon#read 6, iclass 32, count 2 2006.162.07:37:23.69#ibcon#end of sib2, iclass 32, count 2 2006.162.07:37:23.69#ibcon#*mode == 0, iclass 32, count 2 2006.162.07:37:23.69#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.162.07:37:23.69#ibcon#[27=AT06-04\r\n] 2006.162.07:37:23.69#ibcon#*before write, iclass 32, count 2 2006.162.07:37:23.69#ibcon#enter sib2, iclass 32, count 2 2006.162.07:37:23.69#ibcon#flushed, iclass 32, count 2 2006.162.07:37:23.69#ibcon#about to write, iclass 32, count 2 2006.162.07:37:23.69#ibcon#wrote, iclass 32, count 2 2006.162.07:37:23.69#ibcon#about to read 3, iclass 32, count 2 2006.162.07:37:23.72#ibcon#read 3, iclass 32, count 2 2006.162.07:37:23.72#ibcon#about to read 4, iclass 32, count 2 2006.162.07:37:23.72#ibcon#read 4, iclass 32, count 2 2006.162.07:37:23.72#ibcon#about to read 5, iclass 32, count 2 2006.162.07:37:23.72#ibcon#read 5, iclass 32, count 2 2006.162.07:37:23.72#ibcon#about to read 6, iclass 32, count 2 2006.162.07:37:23.72#ibcon#read 6, iclass 32, count 2 2006.162.07:37:23.72#ibcon#end of sib2, iclass 32, count 2 2006.162.07:37:23.72#ibcon#*after write, iclass 32, count 2 2006.162.07:37:23.72#ibcon#*before return 0, iclass 32, count 2 2006.162.07:37:23.72#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.162.07:37:23.72#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.162.07:37:23.72#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.162.07:37:23.72#ibcon#ireg 7 cls_cnt 0 2006.162.07:37:23.72#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.162.07:37:23.84#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.162.07:37:23.84#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.162.07:37:23.84#ibcon#enter wrdev, iclass 32, count 0 2006.162.07:37:23.84#ibcon#first serial, iclass 32, count 0 2006.162.07:37:23.84#ibcon#enter sib2, iclass 32, count 0 2006.162.07:37:23.84#ibcon#flushed, iclass 32, count 0 2006.162.07:37:23.84#ibcon#about to write, iclass 32, count 0 2006.162.07:37:23.84#ibcon#wrote, iclass 32, count 0 2006.162.07:37:23.84#ibcon#about to read 3, iclass 32, count 0 2006.162.07:37:23.86#ibcon#read 3, iclass 32, count 0 2006.162.07:37:23.86#ibcon#about to read 4, iclass 32, count 0 2006.162.07:37:23.86#ibcon#read 4, iclass 32, count 0 2006.162.07:37:23.86#ibcon#about to read 5, iclass 32, count 0 2006.162.07:37:23.86#ibcon#read 5, iclass 32, count 0 2006.162.07:37:23.86#ibcon#about to read 6, iclass 32, count 0 2006.162.07:37:23.86#ibcon#read 6, iclass 32, count 0 2006.162.07:37:23.86#ibcon#end of sib2, iclass 32, count 0 2006.162.07:37:23.86#ibcon#*mode == 0, iclass 32, count 0 2006.162.07:37:23.86#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.162.07:37:23.86#ibcon#[27=USB\r\n] 2006.162.07:37:23.86#ibcon#*before write, iclass 32, count 0 2006.162.07:37:23.86#ibcon#enter sib2, iclass 32, count 0 2006.162.07:37:23.86#ibcon#flushed, iclass 32, count 0 2006.162.07:37:23.86#ibcon#about to write, iclass 32, count 0 2006.162.07:37:23.86#ibcon#wrote, iclass 32, count 0 2006.162.07:37:23.86#ibcon#about to read 3, iclass 32, count 0 2006.162.07:37:23.89#ibcon#read 3, iclass 32, count 0 2006.162.07:37:23.89#ibcon#about to read 4, iclass 32, count 0 2006.162.07:37:23.89#ibcon#read 4, iclass 32, count 0 2006.162.07:37:23.89#ibcon#about to read 5, iclass 32, count 0 2006.162.07:37:23.89#ibcon#read 5, iclass 32, count 0 2006.162.07:37:23.89#ibcon#about to read 6, iclass 32, count 0 2006.162.07:37:23.89#ibcon#read 6, iclass 32, count 0 2006.162.07:37:23.89#ibcon#end of sib2, iclass 32, count 0 2006.162.07:37:23.89#ibcon#*after write, iclass 32, count 0 2006.162.07:37:23.89#ibcon#*before return 0, iclass 32, count 0 2006.162.07:37:23.89#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.162.07:37:23.89#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.162.07:37:23.89#ibcon#about to clear, iclass 32 cls_cnt 0 2006.162.07:37:23.89#ibcon#cleared, iclass 32 cls_cnt 0 2006.162.07:37:23.89$vc4f8/vabw=wide 2006.162.07:37:23.89#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.162.07:37:23.89#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.162.07:37:23.89#ibcon#ireg 8 cls_cnt 0 2006.162.07:37:23.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.162.07:37:23.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.162.07:37:23.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.162.07:37:23.89#ibcon#enter wrdev, iclass 34, count 0 2006.162.07:37:23.89#ibcon#first serial, iclass 34, count 0 2006.162.07:37:23.89#ibcon#enter sib2, iclass 34, count 0 2006.162.07:37:23.89#ibcon#flushed, iclass 34, count 0 2006.162.07:37:23.89#ibcon#about to write, iclass 34, count 0 2006.162.07:37:23.89#ibcon#wrote, iclass 34, count 0 2006.162.07:37:23.89#ibcon#about to read 3, iclass 34, count 0 2006.162.07:37:23.91#ibcon#read 3, iclass 34, count 0 2006.162.07:37:23.91#ibcon#about to read 4, iclass 34, count 0 2006.162.07:37:23.91#ibcon#read 4, iclass 34, count 0 2006.162.07:37:23.91#ibcon#about to read 5, iclass 34, count 0 2006.162.07:37:23.91#ibcon#read 5, iclass 34, count 0 2006.162.07:37:23.91#ibcon#about to read 6, iclass 34, count 0 2006.162.07:37:23.91#ibcon#read 6, iclass 34, count 0 2006.162.07:37:23.91#ibcon#end of sib2, iclass 34, count 0 2006.162.07:37:23.91#ibcon#*mode == 0, iclass 34, count 0 2006.162.07:37:23.91#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.162.07:37:23.91#ibcon#[25=BW32\r\n] 2006.162.07:37:23.91#ibcon#*before write, iclass 34, count 0 2006.162.07:37:23.91#ibcon#enter sib2, iclass 34, count 0 2006.162.07:37:23.91#ibcon#flushed, iclass 34, count 0 2006.162.07:37:23.91#ibcon#about to write, iclass 34, count 0 2006.162.07:37:23.91#ibcon#wrote, iclass 34, count 0 2006.162.07:37:23.91#ibcon#about to read 3, iclass 34, count 0 2006.162.07:37:23.94#ibcon#read 3, iclass 34, count 0 2006.162.07:37:23.94#ibcon#about to read 4, iclass 34, count 0 2006.162.07:37:23.94#ibcon#read 4, iclass 34, count 0 2006.162.07:37:23.94#ibcon#about to read 5, iclass 34, count 0 2006.162.07:37:23.94#ibcon#read 5, iclass 34, count 0 2006.162.07:37:23.94#ibcon#about to read 6, iclass 34, count 0 2006.162.07:37:23.94#ibcon#read 6, iclass 34, count 0 2006.162.07:37:23.94#ibcon#end of sib2, iclass 34, count 0 2006.162.07:37:23.94#ibcon#*after write, iclass 34, count 0 2006.162.07:37:23.94#ibcon#*before return 0, iclass 34, count 0 2006.162.07:37:23.94#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.162.07:37:23.94#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.162.07:37:23.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.162.07:37:23.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.162.07:37:23.94$vc4f8/vbbw=wide 2006.162.07:37:23.94#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.162.07:37:23.94#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.162.07:37:23.94#ibcon#ireg 8 cls_cnt 0 2006.162.07:37:23.94#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:37:24.01#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:37:24.01#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:37:24.01#ibcon#enter wrdev, iclass 36, count 0 2006.162.07:37:24.01#ibcon#first serial, iclass 36, count 0 2006.162.07:37:24.01#ibcon#enter sib2, iclass 36, count 0 2006.162.07:37:24.01#ibcon#flushed, iclass 36, count 0 2006.162.07:37:24.01#ibcon#about to write, iclass 36, count 0 2006.162.07:37:24.01#ibcon#wrote, iclass 36, count 0 2006.162.07:37:24.01#ibcon#about to read 3, iclass 36, count 0 2006.162.07:37:24.03#ibcon#read 3, iclass 36, count 0 2006.162.07:37:24.03#ibcon#about to read 4, iclass 36, count 0 2006.162.07:37:24.03#ibcon#read 4, iclass 36, count 0 2006.162.07:37:24.03#ibcon#about to read 5, iclass 36, count 0 2006.162.07:37:24.03#ibcon#read 5, iclass 36, count 0 2006.162.07:37:24.03#ibcon#about to read 6, iclass 36, count 0 2006.162.07:37:24.03#ibcon#read 6, iclass 36, count 0 2006.162.07:37:24.03#ibcon#end of sib2, iclass 36, count 0 2006.162.07:37:24.03#ibcon#*mode == 0, iclass 36, count 0 2006.162.07:37:24.03#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.162.07:37:24.03#ibcon#[27=BW32\r\n] 2006.162.07:37:24.03#ibcon#*before write, iclass 36, count 0 2006.162.07:37:24.03#ibcon#enter sib2, iclass 36, count 0 2006.162.07:37:24.03#ibcon#flushed, iclass 36, count 0 2006.162.07:37:24.03#ibcon#about to write, iclass 36, count 0 2006.162.07:37:24.03#ibcon#wrote, iclass 36, count 0 2006.162.07:37:24.03#ibcon#about to read 3, iclass 36, count 0 2006.162.07:37:24.06#ibcon#read 3, iclass 36, count 0 2006.162.07:37:24.06#ibcon#about to read 4, iclass 36, count 0 2006.162.07:37:24.06#ibcon#read 4, iclass 36, count 0 2006.162.07:37:24.06#ibcon#about to read 5, iclass 36, count 0 2006.162.07:37:24.06#ibcon#read 5, iclass 36, count 0 2006.162.07:37:24.06#ibcon#about to read 6, iclass 36, count 0 2006.162.07:37:24.06#ibcon#read 6, iclass 36, count 0 2006.162.07:37:24.06#ibcon#end of sib2, iclass 36, count 0 2006.162.07:37:24.06#ibcon#*after write, iclass 36, count 0 2006.162.07:37:24.06#ibcon#*before return 0, iclass 36, count 0 2006.162.07:37:24.06#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:37:24.06#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:37:24.06#ibcon#about to clear, iclass 36 cls_cnt 0 2006.162.07:37:24.06#ibcon#cleared, iclass 36 cls_cnt 0 2006.162.07:37:24.06$4f8m12a/ifd4f 2006.162.07:37:24.06$ifd4f/lo= 2006.162.07:37:24.06$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.07:37:24.06$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.07:37:24.06$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.07:37:24.06$ifd4f/patch= 2006.162.07:37:24.06$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.07:37:24.06$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.07:37:24.06$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.07:37:24.06$4f8m12a/"form=m,16.000,1:2 2006.162.07:37:24.06$4f8m12a/"tpicd 2006.162.07:37:24.06$4f8m12a/echo=off 2006.162.07:37:24.06$4f8m12a/xlog=off 2006.162.07:37:24.06:!2006.162.07:38:00 2006.162.07:37:45.14#trakl#Source acquired 2006.162.07:37:46.14#flagr#flagr/antenna,acquired 2006.162.07:38:00.00:preob 2006.162.07:38:00.14/onsource/TRACKING 2006.162.07:38:00.14:!2006.162.07:38:10 2006.162.07:38:10.00:data_valid=on 2006.162.07:38:10.00:midob 2006.162.07:38:10.14/onsource/TRACKING 2006.162.07:38:10.14/wx/17.89,1007.2,100 2006.162.07:38:10.22/cable/+6.5352E-03 2006.162.07:38:11.31/va/01,08,usb,yes,39,42 2006.162.07:38:11.31/va/02,07,usb,yes,40,42 2006.162.07:38:11.31/va/03,06,usb,yes,42,42 2006.162.07:38:11.31/va/04,07,usb,yes,41,44 2006.162.07:38:11.31/va/05,07,usb,yes,44,46 2006.162.07:38:11.31/va/06,06,usb,yes,43,43 2006.162.07:38:11.31/va/07,06,usb,yes,43,43 2006.162.07:38:11.31/va/08,07,usb,yes,41,41 2006.162.07:38:11.54/valo/01,532.99,yes,locked 2006.162.07:38:11.54/valo/02,572.99,yes,locked 2006.162.07:38:11.54/valo/03,672.99,yes,locked 2006.162.07:38:11.54/valo/04,832.99,yes,locked 2006.162.07:38:11.54/valo/05,652.99,yes,locked 2006.162.07:38:11.54/valo/06,772.99,yes,locked 2006.162.07:38:11.54/valo/07,832.99,yes,locked 2006.162.07:38:11.54/valo/08,852.99,yes,locked 2006.162.07:38:12.63/vb/01,04,usb,yes,30,28 2006.162.07:38:12.63/vb/02,04,usb,yes,31,33 2006.162.07:38:12.63/vb/03,04,usb,yes,28,32 2006.162.07:38:12.63/vb/04,04,usb,yes,29,29 2006.162.07:38:12.63/vb/05,04,usb,yes,27,31 2006.162.07:38:12.63/vb/06,04,usb,yes,28,31 2006.162.07:38:12.63/vb/07,04,usb,yes,30,30 2006.162.07:38:12.63/vb/08,04,usb,yes,28,31 2006.162.07:38:12.87/vblo/01,632.99,yes,locked 2006.162.07:38:12.87/vblo/02,640.99,yes,locked 2006.162.07:38:12.87/vblo/03,656.99,yes,locked 2006.162.07:38:12.87/vblo/04,712.99,yes,locked 2006.162.07:38:12.87/vblo/05,744.99,yes,locked 2006.162.07:38:12.87/vblo/06,752.99,yes,locked 2006.162.07:38:12.87/vblo/07,734.99,yes,locked 2006.162.07:38:12.87/vblo/08,744.99,yes,locked 2006.162.07:38:13.02/vabw/8 2006.162.07:38:13.17/vbbw/8 2006.162.07:38:13.26/xfe/off,on,14.7 2006.162.07:38:13.64/ifatt/23,28,28,28 2006.162.07:38:14.08/fmout-gps/S +4.50E-07 2006.162.07:38:14.14:!2006.162.07:39:10 2006.162.07:39:10.01:data_valid=off 2006.162.07:39:10.01:postob 2006.162.07:39:10.10/cable/+6.5341E-03 2006.162.07:39:10.10/wx/17.90,1007.3,100 2006.162.07:39:11.08/fmout-gps/S +4.49E-07 2006.162.07:39:11.08:scan_name=162-0740,k06162,60 2006.162.07:39:11.09:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.162.07:39:11.14#flagr#flagr/antenna,new-source 2006.162.07:39:12.14:checkk5 2006.162.07:39:12.58/chk_autoobs//k5ts1/ autoobs is running! 2006.162.07:39:13.02/chk_autoobs//k5ts2/ autoobs is running! 2006.162.07:39:13.51/chk_autoobs//k5ts3/ autoobs is running! 2006.162.07:39:13.95/chk_autoobs//k5ts4/ autoobs is running! 2006.162.07:39:14.59/chk_obsdata//k5ts1/T1620738??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:39:14.98/chk_obsdata//k5ts2/T1620738??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:39:15.40/chk_obsdata//k5ts3/T1620738??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:39:15.85/chk_obsdata//k5ts4/T1620738??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:39:17.10/k5log//k5ts1_log_newline 2006.162.07:39:18.13/k5log//k5ts2_log_newline 2006.162.07:39:19.29/k5log//k5ts3_log_newline 2006.162.07:39:20.07/k5log//k5ts4_log_newline 2006.162.07:39:20.10/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.07:39:20.10:4f8m12a=1 2006.162.07:39:20.10$4f8m12a/echo=on 2006.162.07:39:20.10$4f8m12a/pcalon 2006.162.07:39:20.10$pcalon/"no phase cal control is implemented here 2006.162.07:39:20.10$4f8m12a/"tpicd=stop 2006.162.07:39:20.10$4f8m12a/vc4f8 2006.162.07:39:20.10$vc4f8/valo=1,532.99 2006.162.07:39:20.11#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.162.07:39:20.11#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.162.07:39:20.11#ibcon#ireg 17 cls_cnt 0 2006.162.07:39:20.11#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:39:20.11#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:39:20.11#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:39:20.11#ibcon#enter wrdev, iclass 15, count 0 2006.162.07:39:20.11#ibcon#first serial, iclass 15, count 0 2006.162.07:39:20.11#ibcon#enter sib2, iclass 15, count 0 2006.162.07:39:20.11#ibcon#flushed, iclass 15, count 0 2006.162.07:39:20.11#ibcon#about to write, iclass 15, count 0 2006.162.07:39:20.11#ibcon#wrote, iclass 15, count 0 2006.162.07:39:20.11#ibcon#about to read 3, iclass 15, count 0 2006.162.07:39:20.15#ibcon#read 3, iclass 15, count 0 2006.162.07:39:20.15#ibcon#about to read 4, iclass 15, count 0 2006.162.07:39:20.15#ibcon#read 4, iclass 15, count 0 2006.162.07:39:20.15#ibcon#about to read 5, iclass 15, count 0 2006.162.07:39:20.15#ibcon#read 5, iclass 15, count 0 2006.162.07:39:20.15#ibcon#about to read 6, iclass 15, count 0 2006.162.07:39:20.15#ibcon#read 6, iclass 15, count 0 2006.162.07:39:20.15#ibcon#end of sib2, iclass 15, count 0 2006.162.07:39:20.15#ibcon#*mode == 0, iclass 15, count 0 2006.162.07:39:20.15#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.162.07:39:20.15#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.07:39:20.15#ibcon#*before write, iclass 15, count 0 2006.162.07:39:20.15#ibcon#enter sib2, iclass 15, count 0 2006.162.07:39:20.15#ibcon#flushed, iclass 15, count 0 2006.162.07:39:20.15#ibcon#about to write, iclass 15, count 0 2006.162.07:39:20.15#ibcon#wrote, iclass 15, count 0 2006.162.07:39:20.15#ibcon#about to read 3, iclass 15, count 0 2006.162.07:39:20.19#ibcon#read 3, iclass 15, count 0 2006.162.07:39:20.19#ibcon#about to read 4, iclass 15, count 0 2006.162.07:39:20.19#ibcon#read 4, iclass 15, count 0 2006.162.07:39:20.19#ibcon#about to read 5, iclass 15, count 0 2006.162.07:39:20.19#ibcon#read 5, iclass 15, count 0 2006.162.07:39:20.19#ibcon#about to read 6, iclass 15, count 0 2006.162.07:39:20.19#ibcon#read 6, iclass 15, count 0 2006.162.07:39:20.19#ibcon#end of sib2, iclass 15, count 0 2006.162.07:39:20.19#ibcon#*after write, iclass 15, count 0 2006.162.07:39:20.19#ibcon#*before return 0, iclass 15, count 0 2006.162.07:39:20.19#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:39:20.19#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:39:20.19#ibcon#about to clear, iclass 15 cls_cnt 0 2006.162.07:39:20.19#ibcon#cleared, iclass 15 cls_cnt 0 2006.162.07:39:20.19$vc4f8/va=1,8 2006.162.07:39:20.19#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.162.07:39:20.19#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.162.07:39:20.19#ibcon#ireg 11 cls_cnt 2 2006.162.07:39:20.19#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:39:20.19#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:39:20.19#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:39:20.19#ibcon#enter wrdev, iclass 17, count 2 2006.162.07:39:20.19#ibcon#first serial, iclass 17, count 2 2006.162.07:39:20.19#ibcon#enter sib2, iclass 17, count 2 2006.162.07:39:20.19#ibcon#flushed, iclass 17, count 2 2006.162.07:39:20.19#ibcon#about to write, iclass 17, count 2 2006.162.07:39:20.19#ibcon#wrote, iclass 17, count 2 2006.162.07:39:20.19#ibcon#about to read 3, iclass 17, count 2 2006.162.07:39:20.21#ibcon#read 3, iclass 17, count 2 2006.162.07:39:20.21#ibcon#about to read 4, iclass 17, count 2 2006.162.07:39:20.21#ibcon#read 4, iclass 17, count 2 2006.162.07:39:20.21#ibcon#about to read 5, iclass 17, count 2 2006.162.07:39:20.21#ibcon#read 5, iclass 17, count 2 2006.162.07:39:20.21#ibcon#about to read 6, iclass 17, count 2 2006.162.07:39:20.21#ibcon#read 6, iclass 17, count 2 2006.162.07:39:20.21#ibcon#end of sib2, iclass 17, count 2 2006.162.07:39:20.21#ibcon#*mode == 0, iclass 17, count 2 2006.162.07:39:20.21#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.162.07:39:20.21#ibcon#[25=AT01-08\r\n] 2006.162.07:39:20.21#ibcon#*before write, iclass 17, count 2 2006.162.07:39:20.21#ibcon#enter sib2, iclass 17, count 2 2006.162.07:39:20.21#ibcon#flushed, iclass 17, count 2 2006.162.07:39:20.21#ibcon#about to write, iclass 17, count 2 2006.162.07:39:20.21#ibcon#wrote, iclass 17, count 2 2006.162.07:39:20.21#ibcon#about to read 3, iclass 17, count 2 2006.162.07:39:20.24#ibcon#read 3, iclass 17, count 2 2006.162.07:39:20.24#ibcon#about to read 4, iclass 17, count 2 2006.162.07:39:20.24#ibcon#read 4, iclass 17, count 2 2006.162.07:39:20.24#ibcon#about to read 5, iclass 17, count 2 2006.162.07:39:20.24#ibcon#read 5, iclass 17, count 2 2006.162.07:39:20.24#ibcon#about to read 6, iclass 17, count 2 2006.162.07:39:20.24#ibcon#read 6, iclass 17, count 2 2006.162.07:39:20.24#ibcon#end of sib2, iclass 17, count 2 2006.162.07:39:20.24#ibcon#*after write, iclass 17, count 2 2006.162.07:39:20.24#ibcon#*before return 0, iclass 17, count 2 2006.162.07:39:20.24#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:39:20.24#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:39:20.24#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.162.07:39:20.24#ibcon#ireg 7 cls_cnt 0 2006.162.07:39:20.24#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:39:20.36#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:39:20.36#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:39:20.36#ibcon#enter wrdev, iclass 17, count 0 2006.162.07:39:20.36#ibcon#first serial, iclass 17, count 0 2006.162.07:39:20.36#ibcon#enter sib2, iclass 17, count 0 2006.162.07:39:20.36#ibcon#flushed, iclass 17, count 0 2006.162.07:39:20.36#ibcon#about to write, iclass 17, count 0 2006.162.07:39:20.36#ibcon#wrote, iclass 17, count 0 2006.162.07:39:20.36#ibcon#about to read 3, iclass 17, count 0 2006.162.07:39:20.38#ibcon#read 3, iclass 17, count 0 2006.162.07:39:20.38#ibcon#about to read 4, iclass 17, count 0 2006.162.07:39:20.38#ibcon#read 4, iclass 17, count 0 2006.162.07:39:20.38#ibcon#about to read 5, iclass 17, count 0 2006.162.07:39:20.38#ibcon#read 5, iclass 17, count 0 2006.162.07:39:20.38#ibcon#about to read 6, iclass 17, count 0 2006.162.07:39:20.38#ibcon#read 6, iclass 17, count 0 2006.162.07:39:20.38#ibcon#end of sib2, iclass 17, count 0 2006.162.07:39:20.38#ibcon#*mode == 0, iclass 17, count 0 2006.162.07:39:20.38#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.162.07:39:20.38#ibcon#[25=USB\r\n] 2006.162.07:39:20.38#ibcon#*before write, iclass 17, count 0 2006.162.07:39:20.38#ibcon#enter sib2, iclass 17, count 0 2006.162.07:39:20.38#ibcon#flushed, iclass 17, count 0 2006.162.07:39:20.38#ibcon#about to write, iclass 17, count 0 2006.162.07:39:20.38#ibcon#wrote, iclass 17, count 0 2006.162.07:39:20.38#ibcon#about to read 3, iclass 17, count 0 2006.162.07:39:20.41#ibcon#read 3, iclass 17, count 0 2006.162.07:39:20.41#ibcon#about to read 4, iclass 17, count 0 2006.162.07:39:20.41#ibcon#read 4, iclass 17, count 0 2006.162.07:39:20.41#ibcon#about to read 5, iclass 17, count 0 2006.162.07:39:20.41#ibcon#read 5, iclass 17, count 0 2006.162.07:39:20.41#ibcon#about to read 6, iclass 17, count 0 2006.162.07:39:20.41#ibcon#read 6, iclass 17, count 0 2006.162.07:39:20.41#ibcon#end of sib2, iclass 17, count 0 2006.162.07:39:20.41#ibcon#*after write, iclass 17, count 0 2006.162.07:39:20.41#ibcon#*before return 0, iclass 17, count 0 2006.162.07:39:20.41#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:39:20.41#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:39:20.41#ibcon#about to clear, iclass 17 cls_cnt 0 2006.162.07:39:20.41#ibcon#cleared, iclass 17 cls_cnt 0 2006.162.07:39:20.41$vc4f8/valo=2,572.99 2006.162.07:39:20.41#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.162.07:39:20.41#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.162.07:39:20.41#ibcon#ireg 17 cls_cnt 0 2006.162.07:39:20.41#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:39:20.41#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:39:20.41#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:39:20.41#ibcon#enter wrdev, iclass 19, count 0 2006.162.07:39:20.41#ibcon#first serial, iclass 19, count 0 2006.162.07:39:20.41#ibcon#enter sib2, iclass 19, count 0 2006.162.07:39:20.41#ibcon#flushed, iclass 19, count 0 2006.162.07:39:20.41#ibcon#about to write, iclass 19, count 0 2006.162.07:39:20.41#ibcon#wrote, iclass 19, count 0 2006.162.07:39:20.41#ibcon#about to read 3, iclass 19, count 0 2006.162.07:39:20.43#ibcon#read 3, iclass 19, count 0 2006.162.07:39:20.43#ibcon#about to read 4, iclass 19, count 0 2006.162.07:39:20.43#ibcon#read 4, iclass 19, count 0 2006.162.07:39:20.43#ibcon#about to read 5, iclass 19, count 0 2006.162.07:39:20.43#ibcon#read 5, iclass 19, count 0 2006.162.07:39:20.43#ibcon#about to read 6, iclass 19, count 0 2006.162.07:39:20.43#ibcon#read 6, iclass 19, count 0 2006.162.07:39:20.43#ibcon#end of sib2, iclass 19, count 0 2006.162.07:39:20.43#ibcon#*mode == 0, iclass 19, count 0 2006.162.07:39:20.43#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.162.07:39:20.43#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.07:39:20.43#ibcon#*before write, iclass 19, count 0 2006.162.07:39:20.43#ibcon#enter sib2, iclass 19, count 0 2006.162.07:39:20.43#ibcon#flushed, iclass 19, count 0 2006.162.07:39:20.43#ibcon#about to write, iclass 19, count 0 2006.162.07:39:20.43#ibcon#wrote, iclass 19, count 0 2006.162.07:39:20.43#ibcon#about to read 3, iclass 19, count 0 2006.162.07:39:20.47#ibcon#read 3, iclass 19, count 0 2006.162.07:39:20.47#ibcon#about to read 4, iclass 19, count 0 2006.162.07:39:20.47#ibcon#read 4, iclass 19, count 0 2006.162.07:39:20.47#ibcon#about to read 5, iclass 19, count 0 2006.162.07:39:20.47#ibcon#read 5, iclass 19, count 0 2006.162.07:39:20.47#ibcon#about to read 6, iclass 19, count 0 2006.162.07:39:20.47#ibcon#read 6, iclass 19, count 0 2006.162.07:39:20.47#ibcon#end of sib2, iclass 19, count 0 2006.162.07:39:20.47#ibcon#*after write, iclass 19, count 0 2006.162.07:39:20.47#ibcon#*before return 0, iclass 19, count 0 2006.162.07:39:20.47#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:39:20.47#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:39:20.47#ibcon#about to clear, iclass 19 cls_cnt 0 2006.162.07:39:20.47#ibcon#cleared, iclass 19 cls_cnt 0 2006.162.07:39:20.47$vc4f8/va=2,7 2006.162.07:39:20.47#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.162.07:39:20.47#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.162.07:39:20.47#ibcon#ireg 11 cls_cnt 2 2006.162.07:39:20.47#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:39:20.53#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:39:20.53#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:39:20.53#ibcon#enter wrdev, iclass 21, count 2 2006.162.07:39:20.53#ibcon#first serial, iclass 21, count 2 2006.162.07:39:20.53#ibcon#enter sib2, iclass 21, count 2 2006.162.07:39:20.53#ibcon#flushed, iclass 21, count 2 2006.162.07:39:20.53#ibcon#about to write, iclass 21, count 2 2006.162.07:39:20.53#ibcon#wrote, iclass 21, count 2 2006.162.07:39:20.53#ibcon#about to read 3, iclass 21, count 2 2006.162.07:39:20.56#ibcon#read 3, iclass 21, count 2 2006.162.07:39:20.56#ibcon#about to read 4, iclass 21, count 2 2006.162.07:39:20.56#ibcon#read 4, iclass 21, count 2 2006.162.07:39:20.56#ibcon#about to read 5, iclass 21, count 2 2006.162.07:39:20.56#ibcon#read 5, iclass 21, count 2 2006.162.07:39:20.56#ibcon#about to read 6, iclass 21, count 2 2006.162.07:39:20.56#ibcon#read 6, iclass 21, count 2 2006.162.07:39:20.56#ibcon#end of sib2, iclass 21, count 2 2006.162.07:39:20.56#ibcon#*mode == 0, iclass 21, count 2 2006.162.07:39:20.56#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.162.07:39:20.56#ibcon#[25=AT02-07\r\n] 2006.162.07:39:20.56#ibcon#*before write, iclass 21, count 2 2006.162.07:39:20.56#ibcon#enter sib2, iclass 21, count 2 2006.162.07:39:20.56#ibcon#flushed, iclass 21, count 2 2006.162.07:39:20.56#ibcon#about to write, iclass 21, count 2 2006.162.07:39:20.56#ibcon#wrote, iclass 21, count 2 2006.162.07:39:20.56#ibcon#about to read 3, iclass 21, count 2 2006.162.07:39:20.59#ibcon#read 3, iclass 21, count 2 2006.162.07:39:20.59#ibcon#about to read 4, iclass 21, count 2 2006.162.07:39:20.59#ibcon#read 4, iclass 21, count 2 2006.162.07:39:20.59#ibcon#about to read 5, iclass 21, count 2 2006.162.07:39:20.59#ibcon#read 5, iclass 21, count 2 2006.162.07:39:20.59#ibcon#about to read 6, iclass 21, count 2 2006.162.07:39:20.59#ibcon#read 6, iclass 21, count 2 2006.162.07:39:20.59#ibcon#end of sib2, iclass 21, count 2 2006.162.07:39:20.59#ibcon#*after write, iclass 21, count 2 2006.162.07:39:20.59#ibcon#*before return 0, iclass 21, count 2 2006.162.07:39:20.59#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:39:20.59#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:39:20.59#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.162.07:39:20.59#ibcon#ireg 7 cls_cnt 0 2006.162.07:39:20.59#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:39:20.71#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:39:20.71#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:39:20.71#ibcon#enter wrdev, iclass 21, count 0 2006.162.07:39:20.71#ibcon#first serial, iclass 21, count 0 2006.162.07:39:20.71#ibcon#enter sib2, iclass 21, count 0 2006.162.07:39:20.71#ibcon#flushed, iclass 21, count 0 2006.162.07:39:20.71#ibcon#about to write, iclass 21, count 0 2006.162.07:39:20.71#ibcon#wrote, iclass 21, count 0 2006.162.07:39:20.71#ibcon#about to read 3, iclass 21, count 0 2006.162.07:39:20.73#ibcon#read 3, iclass 21, count 0 2006.162.07:39:20.73#ibcon#about to read 4, iclass 21, count 0 2006.162.07:39:20.73#ibcon#read 4, iclass 21, count 0 2006.162.07:39:20.73#ibcon#about to read 5, iclass 21, count 0 2006.162.07:39:20.73#ibcon#read 5, iclass 21, count 0 2006.162.07:39:20.73#ibcon#about to read 6, iclass 21, count 0 2006.162.07:39:20.73#ibcon#read 6, iclass 21, count 0 2006.162.07:39:20.73#ibcon#end of sib2, iclass 21, count 0 2006.162.07:39:20.73#ibcon#*mode == 0, iclass 21, count 0 2006.162.07:39:20.73#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.162.07:39:20.73#ibcon#[25=USB\r\n] 2006.162.07:39:20.73#ibcon#*before write, iclass 21, count 0 2006.162.07:39:20.73#ibcon#enter sib2, iclass 21, count 0 2006.162.07:39:20.73#ibcon#flushed, iclass 21, count 0 2006.162.07:39:20.73#ibcon#about to write, iclass 21, count 0 2006.162.07:39:20.73#ibcon#wrote, iclass 21, count 0 2006.162.07:39:20.73#ibcon#about to read 3, iclass 21, count 0 2006.162.07:39:20.76#ibcon#read 3, iclass 21, count 0 2006.162.07:39:20.76#ibcon#about to read 4, iclass 21, count 0 2006.162.07:39:20.76#ibcon#read 4, iclass 21, count 0 2006.162.07:39:20.76#ibcon#about to read 5, iclass 21, count 0 2006.162.07:39:20.76#ibcon#read 5, iclass 21, count 0 2006.162.07:39:20.76#ibcon#about to read 6, iclass 21, count 0 2006.162.07:39:20.76#ibcon#read 6, iclass 21, count 0 2006.162.07:39:20.76#ibcon#end of sib2, iclass 21, count 0 2006.162.07:39:20.76#ibcon#*after write, iclass 21, count 0 2006.162.07:39:20.76#ibcon#*before return 0, iclass 21, count 0 2006.162.07:39:20.76#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:39:20.76#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:39:20.76#ibcon#about to clear, iclass 21 cls_cnt 0 2006.162.07:39:20.76#ibcon#cleared, iclass 21 cls_cnt 0 2006.162.07:39:20.76$vc4f8/valo=3,672.99 2006.162.07:39:20.76#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.162.07:39:20.76#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.162.07:39:20.76#ibcon#ireg 17 cls_cnt 0 2006.162.07:39:20.76#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:39:20.76#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:39:20.76#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:39:20.76#ibcon#enter wrdev, iclass 23, count 0 2006.162.07:39:20.76#ibcon#first serial, iclass 23, count 0 2006.162.07:39:20.76#ibcon#enter sib2, iclass 23, count 0 2006.162.07:39:20.76#ibcon#flushed, iclass 23, count 0 2006.162.07:39:20.76#ibcon#about to write, iclass 23, count 0 2006.162.07:39:20.76#ibcon#wrote, iclass 23, count 0 2006.162.07:39:20.76#ibcon#about to read 3, iclass 23, count 0 2006.162.07:39:20.78#ibcon#read 3, iclass 23, count 0 2006.162.07:39:20.78#ibcon#about to read 4, iclass 23, count 0 2006.162.07:39:20.78#ibcon#read 4, iclass 23, count 0 2006.162.07:39:20.78#ibcon#about to read 5, iclass 23, count 0 2006.162.07:39:20.78#ibcon#read 5, iclass 23, count 0 2006.162.07:39:20.78#ibcon#about to read 6, iclass 23, count 0 2006.162.07:39:20.78#ibcon#read 6, iclass 23, count 0 2006.162.07:39:20.78#ibcon#end of sib2, iclass 23, count 0 2006.162.07:39:20.78#ibcon#*mode == 0, iclass 23, count 0 2006.162.07:39:20.78#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.162.07:39:20.78#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.07:39:20.78#ibcon#*before write, iclass 23, count 0 2006.162.07:39:20.78#ibcon#enter sib2, iclass 23, count 0 2006.162.07:39:20.78#ibcon#flushed, iclass 23, count 0 2006.162.07:39:20.78#ibcon#about to write, iclass 23, count 0 2006.162.07:39:20.78#ibcon#wrote, iclass 23, count 0 2006.162.07:39:20.78#ibcon#about to read 3, iclass 23, count 0 2006.162.07:39:20.82#ibcon#read 3, iclass 23, count 0 2006.162.07:39:20.82#ibcon#about to read 4, iclass 23, count 0 2006.162.07:39:20.82#ibcon#read 4, iclass 23, count 0 2006.162.07:39:20.82#ibcon#about to read 5, iclass 23, count 0 2006.162.07:39:20.82#ibcon#read 5, iclass 23, count 0 2006.162.07:39:20.82#ibcon#about to read 6, iclass 23, count 0 2006.162.07:39:20.82#ibcon#read 6, iclass 23, count 0 2006.162.07:39:20.82#ibcon#end of sib2, iclass 23, count 0 2006.162.07:39:20.82#ibcon#*after write, iclass 23, count 0 2006.162.07:39:20.82#ibcon#*before return 0, iclass 23, count 0 2006.162.07:39:20.82#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:39:20.82#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:39:20.82#ibcon#about to clear, iclass 23 cls_cnt 0 2006.162.07:39:20.82#ibcon#cleared, iclass 23 cls_cnt 0 2006.162.07:39:20.82$vc4f8/va=3,6 2006.162.07:39:20.82#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.162.07:39:20.82#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.162.07:39:20.82#ibcon#ireg 11 cls_cnt 2 2006.162.07:39:20.82#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.162.07:39:20.88#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.162.07:39:20.88#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.162.07:39:20.88#ibcon#enter wrdev, iclass 25, count 2 2006.162.07:39:20.88#ibcon#first serial, iclass 25, count 2 2006.162.07:39:20.88#ibcon#enter sib2, iclass 25, count 2 2006.162.07:39:20.88#ibcon#flushed, iclass 25, count 2 2006.162.07:39:20.88#ibcon#about to write, iclass 25, count 2 2006.162.07:39:20.88#ibcon#wrote, iclass 25, count 2 2006.162.07:39:20.88#ibcon#about to read 3, iclass 25, count 2 2006.162.07:39:20.91#ibcon#read 3, iclass 25, count 2 2006.162.07:39:20.91#ibcon#about to read 4, iclass 25, count 2 2006.162.07:39:20.91#ibcon#read 4, iclass 25, count 2 2006.162.07:39:20.91#ibcon#about to read 5, iclass 25, count 2 2006.162.07:39:20.91#ibcon#read 5, iclass 25, count 2 2006.162.07:39:20.91#ibcon#about to read 6, iclass 25, count 2 2006.162.07:39:20.91#ibcon#read 6, iclass 25, count 2 2006.162.07:39:20.91#ibcon#end of sib2, iclass 25, count 2 2006.162.07:39:20.91#ibcon#*mode == 0, iclass 25, count 2 2006.162.07:39:20.91#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.162.07:39:20.91#ibcon#[25=AT03-06\r\n] 2006.162.07:39:20.91#ibcon#*before write, iclass 25, count 2 2006.162.07:39:20.91#ibcon#enter sib2, iclass 25, count 2 2006.162.07:39:20.91#ibcon#flushed, iclass 25, count 2 2006.162.07:39:20.91#ibcon#about to write, iclass 25, count 2 2006.162.07:39:20.91#ibcon#wrote, iclass 25, count 2 2006.162.07:39:20.91#ibcon#about to read 3, iclass 25, count 2 2006.162.07:39:20.94#ibcon#read 3, iclass 25, count 2 2006.162.07:39:20.94#ibcon#about to read 4, iclass 25, count 2 2006.162.07:39:20.94#ibcon#read 4, iclass 25, count 2 2006.162.07:39:20.94#ibcon#about to read 5, iclass 25, count 2 2006.162.07:39:20.94#ibcon#read 5, iclass 25, count 2 2006.162.07:39:20.94#ibcon#about to read 6, iclass 25, count 2 2006.162.07:39:20.94#ibcon#read 6, iclass 25, count 2 2006.162.07:39:20.94#ibcon#end of sib2, iclass 25, count 2 2006.162.07:39:20.94#ibcon#*after write, iclass 25, count 2 2006.162.07:39:20.94#ibcon#*before return 0, iclass 25, count 2 2006.162.07:39:20.94#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.162.07:39:20.94#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.162.07:39:20.94#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.162.07:39:20.94#ibcon#ireg 7 cls_cnt 0 2006.162.07:39:20.94#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.162.07:39:21.06#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.162.07:39:21.06#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.162.07:39:21.06#ibcon#enter wrdev, iclass 25, count 0 2006.162.07:39:21.06#ibcon#first serial, iclass 25, count 0 2006.162.07:39:21.06#ibcon#enter sib2, iclass 25, count 0 2006.162.07:39:21.06#ibcon#flushed, iclass 25, count 0 2006.162.07:39:21.06#ibcon#about to write, iclass 25, count 0 2006.162.07:39:21.06#ibcon#wrote, iclass 25, count 0 2006.162.07:39:21.06#ibcon#about to read 3, iclass 25, count 0 2006.162.07:39:21.08#ibcon#read 3, iclass 25, count 0 2006.162.07:39:21.08#ibcon#about to read 4, iclass 25, count 0 2006.162.07:39:21.08#ibcon#read 4, iclass 25, count 0 2006.162.07:39:21.08#ibcon#about to read 5, iclass 25, count 0 2006.162.07:39:21.08#ibcon#read 5, iclass 25, count 0 2006.162.07:39:21.08#ibcon#about to read 6, iclass 25, count 0 2006.162.07:39:21.08#ibcon#read 6, iclass 25, count 0 2006.162.07:39:21.08#ibcon#end of sib2, iclass 25, count 0 2006.162.07:39:21.08#ibcon#*mode == 0, iclass 25, count 0 2006.162.07:39:21.08#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.162.07:39:21.08#ibcon#[25=USB\r\n] 2006.162.07:39:21.08#ibcon#*before write, iclass 25, count 0 2006.162.07:39:21.08#ibcon#enter sib2, iclass 25, count 0 2006.162.07:39:21.08#ibcon#flushed, iclass 25, count 0 2006.162.07:39:21.08#ibcon#about to write, iclass 25, count 0 2006.162.07:39:21.08#ibcon#wrote, iclass 25, count 0 2006.162.07:39:21.08#ibcon#about to read 3, iclass 25, count 0 2006.162.07:39:21.11#ibcon#read 3, iclass 25, count 0 2006.162.07:39:21.11#ibcon#about to read 4, iclass 25, count 0 2006.162.07:39:21.11#ibcon#read 4, iclass 25, count 0 2006.162.07:39:21.11#ibcon#about to read 5, iclass 25, count 0 2006.162.07:39:21.11#ibcon#read 5, iclass 25, count 0 2006.162.07:39:21.11#ibcon#about to read 6, iclass 25, count 0 2006.162.07:39:21.11#ibcon#read 6, iclass 25, count 0 2006.162.07:39:21.11#ibcon#end of sib2, iclass 25, count 0 2006.162.07:39:21.11#ibcon#*after write, iclass 25, count 0 2006.162.07:39:21.11#ibcon#*before return 0, iclass 25, count 0 2006.162.07:39:21.11#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.162.07:39:21.11#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.162.07:39:21.11#ibcon#about to clear, iclass 25 cls_cnt 0 2006.162.07:39:21.11#ibcon#cleared, iclass 25 cls_cnt 0 2006.162.07:39:21.11$vc4f8/valo=4,832.99 2006.162.07:39:21.11#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.162.07:39:21.11#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.162.07:39:21.11#ibcon#ireg 17 cls_cnt 0 2006.162.07:39:21.11#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:39:21.11#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:39:21.11#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:39:21.11#ibcon#enter wrdev, iclass 27, count 0 2006.162.07:39:21.11#ibcon#first serial, iclass 27, count 0 2006.162.07:39:21.11#ibcon#enter sib2, iclass 27, count 0 2006.162.07:39:21.11#ibcon#flushed, iclass 27, count 0 2006.162.07:39:21.11#ibcon#about to write, iclass 27, count 0 2006.162.07:39:21.11#ibcon#wrote, iclass 27, count 0 2006.162.07:39:21.11#ibcon#about to read 3, iclass 27, count 0 2006.162.07:39:21.13#ibcon#read 3, iclass 27, count 0 2006.162.07:39:21.13#ibcon#about to read 4, iclass 27, count 0 2006.162.07:39:21.13#ibcon#read 4, iclass 27, count 0 2006.162.07:39:21.13#ibcon#about to read 5, iclass 27, count 0 2006.162.07:39:21.13#ibcon#read 5, iclass 27, count 0 2006.162.07:39:21.13#ibcon#about to read 6, iclass 27, count 0 2006.162.07:39:21.13#ibcon#read 6, iclass 27, count 0 2006.162.07:39:21.13#ibcon#end of sib2, iclass 27, count 0 2006.162.07:39:21.13#ibcon#*mode == 0, iclass 27, count 0 2006.162.07:39:21.13#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.162.07:39:21.13#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.07:39:21.13#ibcon#*before write, iclass 27, count 0 2006.162.07:39:21.13#ibcon#enter sib2, iclass 27, count 0 2006.162.07:39:21.13#ibcon#flushed, iclass 27, count 0 2006.162.07:39:21.13#ibcon#about to write, iclass 27, count 0 2006.162.07:39:21.13#ibcon#wrote, iclass 27, count 0 2006.162.07:39:21.13#ibcon#about to read 3, iclass 27, count 0 2006.162.07:39:21.17#ibcon#read 3, iclass 27, count 0 2006.162.07:39:21.17#ibcon#about to read 4, iclass 27, count 0 2006.162.07:39:21.17#ibcon#read 4, iclass 27, count 0 2006.162.07:39:21.17#ibcon#about to read 5, iclass 27, count 0 2006.162.07:39:21.17#ibcon#read 5, iclass 27, count 0 2006.162.07:39:21.17#ibcon#about to read 6, iclass 27, count 0 2006.162.07:39:21.17#ibcon#read 6, iclass 27, count 0 2006.162.07:39:21.17#ibcon#end of sib2, iclass 27, count 0 2006.162.07:39:21.17#ibcon#*after write, iclass 27, count 0 2006.162.07:39:21.17#ibcon#*before return 0, iclass 27, count 0 2006.162.07:39:21.17#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:39:21.17#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:39:21.17#ibcon#about to clear, iclass 27 cls_cnt 0 2006.162.07:39:21.17#ibcon#cleared, iclass 27 cls_cnt 0 2006.162.07:39:21.17$vc4f8/va=4,7 2006.162.07:39:21.17#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.162.07:39:21.17#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.162.07:39:21.17#ibcon#ireg 11 cls_cnt 2 2006.162.07:39:21.17#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.162.07:39:21.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.162.07:39:21.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.162.07:39:21.23#ibcon#enter wrdev, iclass 29, count 2 2006.162.07:39:21.23#ibcon#first serial, iclass 29, count 2 2006.162.07:39:21.23#ibcon#enter sib2, iclass 29, count 2 2006.162.07:39:21.23#ibcon#flushed, iclass 29, count 2 2006.162.07:39:21.23#ibcon#about to write, iclass 29, count 2 2006.162.07:39:21.23#ibcon#wrote, iclass 29, count 2 2006.162.07:39:21.23#ibcon#about to read 3, iclass 29, count 2 2006.162.07:39:21.25#ibcon#read 3, iclass 29, count 2 2006.162.07:39:21.25#ibcon#about to read 4, iclass 29, count 2 2006.162.07:39:21.25#ibcon#read 4, iclass 29, count 2 2006.162.07:39:21.25#ibcon#about to read 5, iclass 29, count 2 2006.162.07:39:21.25#ibcon#read 5, iclass 29, count 2 2006.162.07:39:21.25#ibcon#about to read 6, iclass 29, count 2 2006.162.07:39:21.25#ibcon#read 6, iclass 29, count 2 2006.162.07:39:21.25#ibcon#end of sib2, iclass 29, count 2 2006.162.07:39:21.25#ibcon#*mode == 0, iclass 29, count 2 2006.162.07:39:21.25#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.162.07:39:21.25#ibcon#[25=AT04-07\r\n] 2006.162.07:39:21.25#ibcon#*before write, iclass 29, count 2 2006.162.07:39:21.25#ibcon#enter sib2, iclass 29, count 2 2006.162.07:39:21.25#ibcon#flushed, iclass 29, count 2 2006.162.07:39:21.25#ibcon#about to write, iclass 29, count 2 2006.162.07:39:21.25#ibcon#wrote, iclass 29, count 2 2006.162.07:39:21.25#ibcon#about to read 3, iclass 29, count 2 2006.162.07:39:21.28#ibcon#read 3, iclass 29, count 2 2006.162.07:39:21.28#ibcon#about to read 4, iclass 29, count 2 2006.162.07:39:21.28#ibcon#read 4, iclass 29, count 2 2006.162.07:39:21.28#ibcon#about to read 5, iclass 29, count 2 2006.162.07:39:21.28#ibcon#read 5, iclass 29, count 2 2006.162.07:39:21.28#ibcon#about to read 6, iclass 29, count 2 2006.162.07:39:21.28#ibcon#read 6, iclass 29, count 2 2006.162.07:39:21.28#ibcon#end of sib2, iclass 29, count 2 2006.162.07:39:21.28#ibcon#*after write, iclass 29, count 2 2006.162.07:39:21.28#ibcon#*before return 0, iclass 29, count 2 2006.162.07:39:21.28#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.162.07:39:21.28#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.162.07:39:21.28#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.162.07:39:21.28#ibcon#ireg 7 cls_cnt 0 2006.162.07:39:21.28#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.162.07:39:21.40#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.162.07:39:21.40#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.162.07:39:21.40#ibcon#enter wrdev, iclass 29, count 0 2006.162.07:39:21.40#ibcon#first serial, iclass 29, count 0 2006.162.07:39:21.40#ibcon#enter sib2, iclass 29, count 0 2006.162.07:39:21.40#ibcon#flushed, iclass 29, count 0 2006.162.07:39:21.40#ibcon#about to write, iclass 29, count 0 2006.162.07:39:21.40#ibcon#wrote, iclass 29, count 0 2006.162.07:39:21.40#ibcon#about to read 3, iclass 29, count 0 2006.162.07:39:21.42#ibcon#read 3, iclass 29, count 0 2006.162.07:39:21.42#ibcon#about to read 4, iclass 29, count 0 2006.162.07:39:21.42#ibcon#read 4, iclass 29, count 0 2006.162.07:39:21.42#ibcon#about to read 5, iclass 29, count 0 2006.162.07:39:21.42#ibcon#read 5, iclass 29, count 0 2006.162.07:39:21.42#ibcon#about to read 6, iclass 29, count 0 2006.162.07:39:21.42#ibcon#read 6, iclass 29, count 0 2006.162.07:39:21.42#ibcon#end of sib2, iclass 29, count 0 2006.162.07:39:21.42#ibcon#*mode == 0, iclass 29, count 0 2006.162.07:39:21.42#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.162.07:39:21.42#ibcon#[25=USB\r\n] 2006.162.07:39:21.42#ibcon#*before write, iclass 29, count 0 2006.162.07:39:21.42#ibcon#enter sib2, iclass 29, count 0 2006.162.07:39:21.42#ibcon#flushed, iclass 29, count 0 2006.162.07:39:21.42#ibcon#about to write, iclass 29, count 0 2006.162.07:39:21.42#ibcon#wrote, iclass 29, count 0 2006.162.07:39:21.42#ibcon#about to read 3, iclass 29, count 0 2006.162.07:39:21.45#ibcon#read 3, iclass 29, count 0 2006.162.07:39:21.45#ibcon#about to read 4, iclass 29, count 0 2006.162.07:39:21.45#ibcon#read 4, iclass 29, count 0 2006.162.07:39:21.45#ibcon#about to read 5, iclass 29, count 0 2006.162.07:39:21.45#ibcon#read 5, iclass 29, count 0 2006.162.07:39:21.45#ibcon#about to read 6, iclass 29, count 0 2006.162.07:39:21.45#ibcon#read 6, iclass 29, count 0 2006.162.07:39:21.45#ibcon#end of sib2, iclass 29, count 0 2006.162.07:39:21.45#ibcon#*after write, iclass 29, count 0 2006.162.07:39:21.45#ibcon#*before return 0, iclass 29, count 0 2006.162.07:39:21.45#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.162.07:39:21.45#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.162.07:39:21.45#ibcon#about to clear, iclass 29 cls_cnt 0 2006.162.07:39:21.45#ibcon#cleared, iclass 29 cls_cnt 0 2006.162.07:39:21.45$vc4f8/valo=5,652.99 2006.162.07:39:21.45#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.162.07:39:21.45#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.162.07:39:21.45#ibcon#ireg 17 cls_cnt 0 2006.162.07:39:21.45#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.162.07:39:21.45#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.162.07:39:21.45#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.162.07:39:21.45#ibcon#enter wrdev, iclass 31, count 0 2006.162.07:39:21.45#ibcon#first serial, iclass 31, count 0 2006.162.07:39:21.45#ibcon#enter sib2, iclass 31, count 0 2006.162.07:39:21.45#ibcon#flushed, iclass 31, count 0 2006.162.07:39:21.45#ibcon#about to write, iclass 31, count 0 2006.162.07:39:21.45#ibcon#wrote, iclass 31, count 0 2006.162.07:39:21.45#ibcon#about to read 3, iclass 31, count 0 2006.162.07:39:21.47#ibcon#read 3, iclass 31, count 0 2006.162.07:39:21.47#ibcon#about to read 4, iclass 31, count 0 2006.162.07:39:21.47#ibcon#read 4, iclass 31, count 0 2006.162.07:39:21.47#ibcon#about to read 5, iclass 31, count 0 2006.162.07:39:21.47#ibcon#read 5, iclass 31, count 0 2006.162.07:39:21.47#ibcon#about to read 6, iclass 31, count 0 2006.162.07:39:21.47#ibcon#read 6, iclass 31, count 0 2006.162.07:39:21.47#ibcon#end of sib2, iclass 31, count 0 2006.162.07:39:21.47#ibcon#*mode == 0, iclass 31, count 0 2006.162.07:39:21.47#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.162.07:39:21.47#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.07:39:21.47#ibcon#*before write, iclass 31, count 0 2006.162.07:39:21.47#ibcon#enter sib2, iclass 31, count 0 2006.162.07:39:21.47#ibcon#flushed, iclass 31, count 0 2006.162.07:39:21.47#ibcon#about to write, iclass 31, count 0 2006.162.07:39:21.47#ibcon#wrote, iclass 31, count 0 2006.162.07:39:21.47#ibcon#about to read 3, iclass 31, count 0 2006.162.07:39:21.51#ibcon#read 3, iclass 31, count 0 2006.162.07:39:21.51#ibcon#about to read 4, iclass 31, count 0 2006.162.07:39:21.51#ibcon#read 4, iclass 31, count 0 2006.162.07:39:21.51#ibcon#about to read 5, iclass 31, count 0 2006.162.07:39:21.51#ibcon#read 5, iclass 31, count 0 2006.162.07:39:21.51#ibcon#about to read 6, iclass 31, count 0 2006.162.07:39:21.51#ibcon#read 6, iclass 31, count 0 2006.162.07:39:21.51#ibcon#end of sib2, iclass 31, count 0 2006.162.07:39:21.51#ibcon#*after write, iclass 31, count 0 2006.162.07:39:21.51#ibcon#*before return 0, iclass 31, count 0 2006.162.07:39:21.51#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.162.07:39:21.51#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.162.07:39:21.51#ibcon#about to clear, iclass 31 cls_cnt 0 2006.162.07:39:21.51#ibcon#cleared, iclass 31 cls_cnt 0 2006.162.07:39:21.51$vc4f8/va=5,7 2006.162.07:39:21.51#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.162.07:39:21.51#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.162.07:39:21.51#ibcon#ireg 11 cls_cnt 2 2006.162.07:39:21.51#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.162.07:39:21.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.162.07:39:21.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.162.07:39:21.57#ibcon#enter wrdev, iclass 33, count 2 2006.162.07:39:21.57#ibcon#first serial, iclass 33, count 2 2006.162.07:39:21.57#ibcon#enter sib2, iclass 33, count 2 2006.162.07:39:21.57#ibcon#flushed, iclass 33, count 2 2006.162.07:39:21.57#ibcon#about to write, iclass 33, count 2 2006.162.07:39:21.57#ibcon#wrote, iclass 33, count 2 2006.162.07:39:21.57#ibcon#about to read 3, iclass 33, count 2 2006.162.07:39:21.60#ibcon#read 3, iclass 33, count 2 2006.162.07:39:21.60#ibcon#about to read 4, iclass 33, count 2 2006.162.07:39:21.60#ibcon#read 4, iclass 33, count 2 2006.162.07:39:21.60#ibcon#about to read 5, iclass 33, count 2 2006.162.07:39:21.60#ibcon#read 5, iclass 33, count 2 2006.162.07:39:21.60#ibcon#about to read 6, iclass 33, count 2 2006.162.07:39:21.60#ibcon#read 6, iclass 33, count 2 2006.162.07:39:21.60#ibcon#end of sib2, iclass 33, count 2 2006.162.07:39:21.60#ibcon#*mode == 0, iclass 33, count 2 2006.162.07:39:21.60#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.162.07:39:21.60#ibcon#[25=AT05-07\r\n] 2006.162.07:39:21.60#ibcon#*before write, iclass 33, count 2 2006.162.07:39:21.60#ibcon#enter sib2, iclass 33, count 2 2006.162.07:39:21.60#ibcon#flushed, iclass 33, count 2 2006.162.07:39:21.60#ibcon#about to write, iclass 33, count 2 2006.162.07:39:21.60#ibcon#wrote, iclass 33, count 2 2006.162.07:39:21.60#ibcon#about to read 3, iclass 33, count 2 2006.162.07:39:21.63#ibcon#read 3, iclass 33, count 2 2006.162.07:39:21.63#ibcon#about to read 4, iclass 33, count 2 2006.162.07:39:21.63#ibcon#read 4, iclass 33, count 2 2006.162.07:39:21.63#ibcon#about to read 5, iclass 33, count 2 2006.162.07:39:21.63#ibcon#read 5, iclass 33, count 2 2006.162.07:39:21.63#ibcon#about to read 6, iclass 33, count 2 2006.162.07:39:21.63#ibcon#read 6, iclass 33, count 2 2006.162.07:39:21.63#ibcon#end of sib2, iclass 33, count 2 2006.162.07:39:21.63#ibcon#*after write, iclass 33, count 2 2006.162.07:39:21.63#ibcon#*before return 0, iclass 33, count 2 2006.162.07:39:21.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.162.07:39:21.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.162.07:39:21.63#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.162.07:39:21.63#ibcon#ireg 7 cls_cnt 0 2006.162.07:39:21.63#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.162.07:39:21.75#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.162.07:39:21.75#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.162.07:39:21.75#ibcon#enter wrdev, iclass 33, count 0 2006.162.07:39:21.75#ibcon#first serial, iclass 33, count 0 2006.162.07:39:21.75#ibcon#enter sib2, iclass 33, count 0 2006.162.07:39:21.75#ibcon#flushed, iclass 33, count 0 2006.162.07:39:21.75#ibcon#about to write, iclass 33, count 0 2006.162.07:39:21.75#ibcon#wrote, iclass 33, count 0 2006.162.07:39:21.75#ibcon#about to read 3, iclass 33, count 0 2006.162.07:39:21.77#ibcon#read 3, iclass 33, count 0 2006.162.07:39:21.77#ibcon#about to read 4, iclass 33, count 0 2006.162.07:39:21.77#ibcon#read 4, iclass 33, count 0 2006.162.07:39:21.77#ibcon#about to read 5, iclass 33, count 0 2006.162.07:39:21.77#ibcon#read 5, iclass 33, count 0 2006.162.07:39:21.77#ibcon#about to read 6, iclass 33, count 0 2006.162.07:39:21.77#ibcon#read 6, iclass 33, count 0 2006.162.07:39:21.77#ibcon#end of sib2, iclass 33, count 0 2006.162.07:39:21.77#ibcon#*mode == 0, iclass 33, count 0 2006.162.07:39:21.77#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.162.07:39:21.77#ibcon#[25=USB\r\n] 2006.162.07:39:21.77#ibcon#*before write, iclass 33, count 0 2006.162.07:39:21.77#ibcon#enter sib2, iclass 33, count 0 2006.162.07:39:21.77#ibcon#flushed, iclass 33, count 0 2006.162.07:39:21.77#ibcon#about to write, iclass 33, count 0 2006.162.07:39:21.77#ibcon#wrote, iclass 33, count 0 2006.162.07:39:21.77#ibcon#about to read 3, iclass 33, count 0 2006.162.07:39:21.80#ibcon#read 3, iclass 33, count 0 2006.162.07:39:21.80#ibcon#about to read 4, iclass 33, count 0 2006.162.07:39:21.80#ibcon#read 4, iclass 33, count 0 2006.162.07:39:21.80#ibcon#about to read 5, iclass 33, count 0 2006.162.07:39:21.80#ibcon#read 5, iclass 33, count 0 2006.162.07:39:21.80#ibcon#about to read 6, iclass 33, count 0 2006.162.07:39:21.80#ibcon#read 6, iclass 33, count 0 2006.162.07:39:21.80#ibcon#end of sib2, iclass 33, count 0 2006.162.07:39:21.80#ibcon#*after write, iclass 33, count 0 2006.162.07:39:21.80#ibcon#*before return 0, iclass 33, count 0 2006.162.07:39:21.80#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.162.07:39:21.80#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.162.07:39:21.80#ibcon#about to clear, iclass 33 cls_cnt 0 2006.162.07:39:21.80#ibcon#cleared, iclass 33 cls_cnt 0 2006.162.07:39:21.80$vc4f8/valo=6,772.99 2006.162.07:39:21.80#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.162.07:39:21.80#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.162.07:39:21.80#ibcon#ireg 17 cls_cnt 0 2006.162.07:39:21.80#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.162.07:39:21.80#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.162.07:39:21.80#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.162.07:39:21.80#ibcon#enter wrdev, iclass 35, count 0 2006.162.07:39:21.80#ibcon#first serial, iclass 35, count 0 2006.162.07:39:21.80#ibcon#enter sib2, iclass 35, count 0 2006.162.07:39:21.80#ibcon#flushed, iclass 35, count 0 2006.162.07:39:21.80#ibcon#about to write, iclass 35, count 0 2006.162.07:39:21.80#ibcon#wrote, iclass 35, count 0 2006.162.07:39:21.80#ibcon#about to read 3, iclass 35, count 0 2006.162.07:39:21.82#ibcon#read 3, iclass 35, count 0 2006.162.07:39:21.82#ibcon#about to read 4, iclass 35, count 0 2006.162.07:39:21.82#ibcon#read 4, iclass 35, count 0 2006.162.07:39:21.82#ibcon#about to read 5, iclass 35, count 0 2006.162.07:39:21.82#ibcon#read 5, iclass 35, count 0 2006.162.07:39:21.82#ibcon#about to read 6, iclass 35, count 0 2006.162.07:39:21.82#ibcon#read 6, iclass 35, count 0 2006.162.07:39:21.82#ibcon#end of sib2, iclass 35, count 0 2006.162.07:39:21.82#ibcon#*mode == 0, iclass 35, count 0 2006.162.07:39:21.82#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.162.07:39:21.82#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.07:39:21.82#ibcon#*before write, iclass 35, count 0 2006.162.07:39:21.82#ibcon#enter sib2, iclass 35, count 0 2006.162.07:39:21.82#ibcon#flushed, iclass 35, count 0 2006.162.07:39:21.82#ibcon#about to write, iclass 35, count 0 2006.162.07:39:21.82#ibcon#wrote, iclass 35, count 0 2006.162.07:39:21.82#ibcon#about to read 3, iclass 35, count 0 2006.162.07:39:21.86#ibcon#read 3, iclass 35, count 0 2006.162.07:39:21.86#ibcon#about to read 4, iclass 35, count 0 2006.162.07:39:21.86#ibcon#read 4, iclass 35, count 0 2006.162.07:39:21.86#ibcon#about to read 5, iclass 35, count 0 2006.162.07:39:21.86#ibcon#read 5, iclass 35, count 0 2006.162.07:39:21.86#ibcon#about to read 6, iclass 35, count 0 2006.162.07:39:21.86#ibcon#read 6, iclass 35, count 0 2006.162.07:39:21.86#ibcon#end of sib2, iclass 35, count 0 2006.162.07:39:21.86#ibcon#*after write, iclass 35, count 0 2006.162.07:39:21.86#ibcon#*before return 0, iclass 35, count 0 2006.162.07:39:21.86#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.162.07:39:21.86#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.162.07:39:21.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.162.07:39:21.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.162.07:39:21.86$vc4f8/va=6,6 2006.162.07:39:21.86#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.162.07:39:21.86#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.162.07:39:21.86#ibcon#ireg 11 cls_cnt 2 2006.162.07:39:21.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.162.07:39:21.92#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.162.07:39:21.92#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.162.07:39:21.92#ibcon#enter wrdev, iclass 37, count 2 2006.162.07:39:21.92#ibcon#first serial, iclass 37, count 2 2006.162.07:39:21.92#ibcon#enter sib2, iclass 37, count 2 2006.162.07:39:21.92#ibcon#flushed, iclass 37, count 2 2006.162.07:39:21.92#ibcon#about to write, iclass 37, count 2 2006.162.07:39:21.92#ibcon#wrote, iclass 37, count 2 2006.162.07:39:21.92#ibcon#about to read 3, iclass 37, count 2 2006.162.07:39:21.94#ibcon#read 3, iclass 37, count 2 2006.162.07:39:21.94#ibcon#about to read 4, iclass 37, count 2 2006.162.07:39:21.94#ibcon#read 4, iclass 37, count 2 2006.162.07:39:21.94#ibcon#about to read 5, iclass 37, count 2 2006.162.07:39:21.94#ibcon#read 5, iclass 37, count 2 2006.162.07:39:21.94#ibcon#about to read 6, iclass 37, count 2 2006.162.07:39:21.94#ibcon#read 6, iclass 37, count 2 2006.162.07:39:21.94#ibcon#end of sib2, iclass 37, count 2 2006.162.07:39:21.94#ibcon#*mode == 0, iclass 37, count 2 2006.162.07:39:21.94#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.162.07:39:21.94#ibcon#[25=AT06-06\r\n] 2006.162.07:39:21.94#ibcon#*before write, iclass 37, count 2 2006.162.07:39:21.94#ibcon#enter sib2, iclass 37, count 2 2006.162.07:39:21.94#ibcon#flushed, iclass 37, count 2 2006.162.07:39:21.94#ibcon#about to write, iclass 37, count 2 2006.162.07:39:21.94#ibcon#wrote, iclass 37, count 2 2006.162.07:39:21.94#ibcon#about to read 3, iclass 37, count 2 2006.162.07:39:21.97#ibcon#read 3, iclass 37, count 2 2006.162.07:39:21.97#ibcon#about to read 4, iclass 37, count 2 2006.162.07:39:21.97#ibcon#read 4, iclass 37, count 2 2006.162.07:39:21.97#ibcon#about to read 5, iclass 37, count 2 2006.162.07:39:21.97#ibcon#read 5, iclass 37, count 2 2006.162.07:39:21.97#ibcon#about to read 6, iclass 37, count 2 2006.162.07:39:21.97#ibcon#read 6, iclass 37, count 2 2006.162.07:39:21.97#ibcon#end of sib2, iclass 37, count 2 2006.162.07:39:21.97#ibcon#*after write, iclass 37, count 2 2006.162.07:39:21.97#ibcon#*before return 0, iclass 37, count 2 2006.162.07:39:21.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.162.07:39:21.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.162.07:39:21.97#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.162.07:39:21.97#ibcon#ireg 7 cls_cnt 0 2006.162.07:39:21.97#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.162.07:39:22.09#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.162.07:39:22.09#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.162.07:39:22.09#ibcon#enter wrdev, iclass 37, count 0 2006.162.07:39:22.09#ibcon#first serial, iclass 37, count 0 2006.162.07:39:22.09#ibcon#enter sib2, iclass 37, count 0 2006.162.07:39:22.09#ibcon#flushed, iclass 37, count 0 2006.162.07:39:22.09#ibcon#about to write, iclass 37, count 0 2006.162.07:39:22.09#ibcon#wrote, iclass 37, count 0 2006.162.07:39:22.09#ibcon#about to read 3, iclass 37, count 0 2006.162.07:39:22.11#ibcon#read 3, iclass 37, count 0 2006.162.07:39:22.11#ibcon#about to read 4, iclass 37, count 0 2006.162.07:39:22.11#ibcon#read 4, iclass 37, count 0 2006.162.07:39:22.11#ibcon#about to read 5, iclass 37, count 0 2006.162.07:39:22.11#ibcon#read 5, iclass 37, count 0 2006.162.07:39:22.11#ibcon#about to read 6, iclass 37, count 0 2006.162.07:39:22.11#ibcon#read 6, iclass 37, count 0 2006.162.07:39:22.11#ibcon#end of sib2, iclass 37, count 0 2006.162.07:39:22.11#ibcon#*mode == 0, iclass 37, count 0 2006.162.07:39:22.11#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.162.07:39:22.11#ibcon#[25=USB\r\n] 2006.162.07:39:22.11#ibcon#*before write, iclass 37, count 0 2006.162.07:39:22.11#ibcon#enter sib2, iclass 37, count 0 2006.162.07:39:22.11#ibcon#flushed, iclass 37, count 0 2006.162.07:39:22.11#ibcon#about to write, iclass 37, count 0 2006.162.07:39:22.11#ibcon#wrote, iclass 37, count 0 2006.162.07:39:22.11#ibcon#about to read 3, iclass 37, count 0 2006.162.07:39:22.14#ibcon#read 3, iclass 37, count 0 2006.162.07:39:22.14#ibcon#about to read 4, iclass 37, count 0 2006.162.07:39:22.14#ibcon#read 4, iclass 37, count 0 2006.162.07:39:22.14#ibcon#about to read 5, iclass 37, count 0 2006.162.07:39:22.14#ibcon#read 5, iclass 37, count 0 2006.162.07:39:22.14#ibcon#about to read 6, iclass 37, count 0 2006.162.07:39:22.14#ibcon#read 6, iclass 37, count 0 2006.162.07:39:22.14#ibcon#end of sib2, iclass 37, count 0 2006.162.07:39:22.14#ibcon#*after write, iclass 37, count 0 2006.162.07:39:22.14#ibcon#*before return 0, iclass 37, count 0 2006.162.07:39:22.14#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.162.07:39:22.14#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.162.07:39:22.14#ibcon#about to clear, iclass 37 cls_cnt 0 2006.162.07:39:22.14#ibcon#cleared, iclass 37 cls_cnt 0 2006.162.07:39:22.14$vc4f8/valo=7,832.99 2006.162.07:39:22.14#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.162.07:39:22.14#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.162.07:39:22.14#ibcon#ireg 17 cls_cnt 0 2006.162.07:39:22.14#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.162.07:39:22.14#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.162.07:39:22.14#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.162.07:39:22.14#ibcon#enter wrdev, iclass 39, count 0 2006.162.07:39:22.14#ibcon#first serial, iclass 39, count 0 2006.162.07:39:22.14#ibcon#enter sib2, iclass 39, count 0 2006.162.07:39:22.14#ibcon#flushed, iclass 39, count 0 2006.162.07:39:22.14#ibcon#about to write, iclass 39, count 0 2006.162.07:39:22.14#ibcon#wrote, iclass 39, count 0 2006.162.07:39:22.14#ibcon#about to read 3, iclass 39, count 0 2006.162.07:39:22.16#ibcon#read 3, iclass 39, count 0 2006.162.07:39:22.16#ibcon#about to read 4, iclass 39, count 0 2006.162.07:39:22.16#ibcon#read 4, iclass 39, count 0 2006.162.07:39:22.16#ibcon#about to read 5, iclass 39, count 0 2006.162.07:39:22.16#ibcon#read 5, iclass 39, count 0 2006.162.07:39:22.16#ibcon#about to read 6, iclass 39, count 0 2006.162.07:39:22.16#ibcon#read 6, iclass 39, count 0 2006.162.07:39:22.16#ibcon#end of sib2, iclass 39, count 0 2006.162.07:39:22.16#ibcon#*mode == 0, iclass 39, count 0 2006.162.07:39:22.16#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.162.07:39:22.16#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.07:39:22.16#ibcon#*before write, iclass 39, count 0 2006.162.07:39:22.16#ibcon#enter sib2, iclass 39, count 0 2006.162.07:39:22.16#ibcon#flushed, iclass 39, count 0 2006.162.07:39:22.16#ibcon#about to write, iclass 39, count 0 2006.162.07:39:22.16#ibcon#wrote, iclass 39, count 0 2006.162.07:39:22.16#ibcon#about to read 3, iclass 39, count 0 2006.162.07:39:22.20#ibcon#read 3, iclass 39, count 0 2006.162.07:39:22.20#ibcon#about to read 4, iclass 39, count 0 2006.162.07:39:22.20#ibcon#read 4, iclass 39, count 0 2006.162.07:39:22.20#ibcon#about to read 5, iclass 39, count 0 2006.162.07:39:22.20#ibcon#read 5, iclass 39, count 0 2006.162.07:39:22.20#ibcon#about to read 6, iclass 39, count 0 2006.162.07:39:22.20#ibcon#read 6, iclass 39, count 0 2006.162.07:39:22.20#ibcon#end of sib2, iclass 39, count 0 2006.162.07:39:22.20#ibcon#*after write, iclass 39, count 0 2006.162.07:39:22.20#ibcon#*before return 0, iclass 39, count 0 2006.162.07:39:22.20#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.162.07:39:22.20#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.162.07:39:22.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.162.07:39:22.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.162.07:39:22.20$vc4f8/va=7,6 2006.162.07:39:22.20#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.162.07:39:22.20#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.162.07:39:22.20#ibcon#ireg 11 cls_cnt 2 2006.162.07:39:22.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.162.07:39:22.26#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.162.07:39:22.26#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.162.07:39:22.26#ibcon#enter wrdev, iclass 3, count 2 2006.162.07:39:22.26#ibcon#first serial, iclass 3, count 2 2006.162.07:39:22.26#ibcon#enter sib2, iclass 3, count 2 2006.162.07:39:22.26#ibcon#flushed, iclass 3, count 2 2006.162.07:39:22.26#ibcon#about to write, iclass 3, count 2 2006.162.07:39:22.26#ibcon#wrote, iclass 3, count 2 2006.162.07:39:22.26#ibcon#about to read 3, iclass 3, count 2 2006.162.07:39:22.29#ibcon#read 3, iclass 3, count 2 2006.162.07:39:22.29#ibcon#about to read 4, iclass 3, count 2 2006.162.07:39:22.29#ibcon#read 4, iclass 3, count 2 2006.162.07:39:22.29#ibcon#about to read 5, iclass 3, count 2 2006.162.07:39:22.29#ibcon#read 5, iclass 3, count 2 2006.162.07:39:22.29#ibcon#about to read 6, iclass 3, count 2 2006.162.07:39:22.29#ibcon#read 6, iclass 3, count 2 2006.162.07:39:22.29#ibcon#end of sib2, iclass 3, count 2 2006.162.07:39:22.29#ibcon#*mode == 0, iclass 3, count 2 2006.162.07:39:22.29#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.162.07:39:22.29#ibcon#[25=AT07-06\r\n] 2006.162.07:39:22.29#ibcon#*before write, iclass 3, count 2 2006.162.07:39:22.29#ibcon#enter sib2, iclass 3, count 2 2006.162.07:39:22.29#ibcon#flushed, iclass 3, count 2 2006.162.07:39:22.29#ibcon#about to write, iclass 3, count 2 2006.162.07:39:22.29#ibcon#wrote, iclass 3, count 2 2006.162.07:39:22.29#ibcon#about to read 3, iclass 3, count 2 2006.162.07:39:22.32#ibcon#read 3, iclass 3, count 2 2006.162.07:39:22.32#ibcon#about to read 4, iclass 3, count 2 2006.162.07:39:22.32#ibcon#read 4, iclass 3, count 2 2006.162.07:39:22.32#ibcon#about to read 5, iclass 3, count 2 2006.162.07:39:22.32#ibcon#read 5, iclass 3, count 2 2006.162.07:39:22.32#ibcon#about to read 6, iclass 3, count 2 2006.162.07:39:22.32#ibcon#read 6, iclass 3, count 2 2006.162.07:39:22.32#ibcon#end of sib2, iclass 3, count 2 2006.162.07:39:22.32#ibcon#*after write, iclass 3, count 2 2006.162.07:39:22.32#ibcon#*before return 0, iclass 3, count 2 2006.162.07:39:22.32#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.162.07:39:22.32#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.162.07:39:22.32#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.162.07:39:22.32#ibcon#ireg 7 cls_cnt 0 2006.162.07:39:22.32#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.162.07:39:22.44#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.162.07:39:22.44#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.162.07:39:22.44#ibcon#enter wrdev, iclass 3, count 0 2006.162.07:39:22.44#ibcon#first serial, iclass 3, count 0 2006.162.07:39:22.44#ibcon#enter sib2, iclass 3, count 0 2006.162.07:39:22.44#ibcon#flushed, iclass 3, count 0 2006.162.07:39:22.44#ibcon#about to write, iclass 3, count 0 2006.162.07:39:22.44#ibcon#wrote, iclass 3, count 0 2006.162.07:39:22.44#ibcon#about to read 3, iclass 3, count 0 2006.162.07:39:22.46#ibcon#read 3, iclass 3, count 0 2006.162.07:39:22.46#ibcon#about to read 4, iclass 3, count 0 2006.162.07:39:22.46#ibcon#read 4, iclass 3, count 0 2006.162.07:39:22.46#ibcon#about to read 5, iclass 3, count 0 2006.162.07:39:22.46#ibcon#read 5, iclass 3, count 0 2006.162.07:39:22.46#ibcon#about to read 6, iclass 3, count 0 2006.162.07:39:22.46#ibcon#read 6, iclass 3, count 0 2006.162.07:39:22.46#ibcon#end of sib2, iclass 3, count 0 2006.162.07:39:22.46#ibcon#*mode == 0, iclass 3, count 0 2006.162.07:39:22.46#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.162.07:39:22.46#ibcon#[25=USB\r\n] 2006.162.07:39:22.46#ibcon#*before write, iclass 3, count 0 2006.162.07:39:22.46#ibcon#enter sib2, iclass 3, count 0 2006.162.07:39:22.46#ibcon#flushed, iclass 3, count 0 2006.162.07:39:22.46#ibcon#about to write, iclass 3, count 0 2006.162.07:39:22.46#ibcon#wrote, iclass 3, count 0 2006.162.07:39:22.46#ibcon#about to read 3, iclass 3, count 0 2006.162.07:39:22.49#ibcon#read 3, iclass 3, count 0 2006.162.07:39:22.49#ibcon#about to read 4, iclass 3, count 0 2006.162.07:39:22.49#ibcon#read 4, iclass 3, count 0 2006.162.07:39:22.49#ibcon#about to read 5, iclass 3, count 0 2006.162.07:39:22.49#ibcon#read 5, iclass 3, count 0 2006.162.07:39:22.49#ibcon#about to read 6, iclass 3, count 0 2006.162.07:39:22.49#ibcon#read 6, iclass 3, count 0 2006.162.07:39:22.49#ibcon#end of sib2, iclass 3, count 0 2006.162.07:39:22.49#ibcon#*after write, iclass 3, count 0 2006.162.07:39:22.49#ibcon#*before return 0, iclass 3, count 0 2006.162.07:39:22.49#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.162.07:39:22.49#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.162.07:39:22.49#ibcon#about to clear, iclass 3 cls_cnt 0 2006.162.07:39:22.49#ibcon#cleared, iclass 3 cls_cnt 0 2006.162.07:39:22.49$vc4f8/valo=8,852.99 2006.162.07:39:22.49#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.162.07:39:22.49#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.162.07:39:22.49#ibcon#ireg 17 cls_cnt 0 2006.162.07:39:22.49#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.162.07:39:22.49#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.162.07:39:22.49#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.162.07:39:22.49#ibcon#enter wrdev, iclass 5, count 0 2006.162.07:39:22.49#ibcon#first serial, iclass 5, count 0 2006.162.07:39:22.49#ibcon#enter sib2, iclass 5, count 0 2006.162.07:39:22.49#ibcon#flushed, iclass 5, count 0 2006.162.07:39:22.49#ibcon#about to write, iclass 5, count 0 2006.162.07:39:22.49#ibcon#wrote, iclass 5, count 0 2006.162.07:39:22.49#ibcon#about to read 3, iclass 5, count 0 2006.162.07:39:22.52#ibcon#read 3, iclass 5, count 0 2006.162.07:39:22.52#ibcon#about to read 4, iclass 5, count 0 2006.162.07:39:22.52#ibcon#read 4, iclass 5, count 0 2006.162.07:39:22.52#ibcon#about to read 5, iclass 5, count 0 2006.162.07:39:22.52#ibcon#read 5, iclass 5, count 0 2006.162.07:39:22.52#ibcon#about to read 6, iclass 5, count 0 2006.162.07:39:22.52#ibcon#read 6, iclass 5, count 0 2006.162.07:39:22.52#ibcon#end of sib2, iclass 5, count 0 2006.162.07:39:22.52#ibcon#*mode == 0, iclass 5, count 0 2006.162.07:39:22.52#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.162.07:39:22.52#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.07:39:22.52#ibcon#*before write, iclass 5, count 0 2006.162.07:39:22.52#ibcon#enter sib2, iclass 5, count 0 2006.162.07:39:22.52#ibcon#flushed, iclass 5, count 0 2006.162.07:39:22.52#ibcon#about to write, iclass 5, count 0 2006.162.07:39:22.52#ibcon#wrote, iclass 5, count 0 2006.162.07:39:22.52#ibcon#about to read 3, iclass 5, count 0 2006.162.07:39:22.56#ibcon#read 3, iclass 5, count 0 2006.162.07:39:22.56#ibcon#about to read 4, iclass 5, count 0 2006.162.07:39:22.56#ibcon#read 4, iclass 5, count 0 2006.162.07:39:22.56#ibcon#about to read 5, iclass 5, count 0 2006.162.07:39:22.56#ibcon#read 5, iclass 5, count 0 2006.162.07:39:22.56#ibcon#about to read 6, iclass 5, count 0 2006.162.07:39:22.56#ibcon#read 6, iclass 5, count 0 2006.162.07:39:22.56#ibcon#end of sib2, iclass 5, count 0 2006.162.07:39:22.56#ibcon#*after write, iclass 5, count 0 2006.162.07:39:22.56#ibcon#*before return 0, iclass 5, count 0 2006.162.07:39:22.56#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.162.07:39:22.56#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.162.07:39:22.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.162.07:39:22.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.162.07:39:22.56$vc4f8/va=8,7 2006.162.07:39:22.56#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.162.07:39:22.56#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.162.07:39:22.56#ibcon#ireg 11 cls_cnt 2 2006.162.07:39:22.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.162.07:39:22.61#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.162.07:39:22.61#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.162.07:39:22.61#ibcon#enter wrdev, iclass 7, count 2 2006.162.07:39:22.61#ibcon#first serial, iclass 7, count 2 2006.162.07:39:22.61#ibcon#enter sib2, iclass 7, count 2 2006.162.07:39:22.61#ibcon#flushed, iclass 7, count 2 2006.162.07:39:22.61#ibcon#about to write, iclass 7, count 2 2006.162.07:39:22.61#ibcon#wrote, iclass 7, count 2 2006.162.07:39:22.61#ibcon#about to read 3, iclass 7, count 2 2006.162.07:39:22.63#ibcon#read 3, iclass 7, count 2 2006.162.07:39:22.63#ibcon#about to read 4, iclass 7, count 2 2006.162.07:39:22.63#ibcon#read 4, iclass 7, count 2 2006.162.07:39:22.63#ibcon#about to read 5, iclass 7, count 2 2006.162.07:39:22.63#ibcon#read 5, iclass 7, count 2 2006.162.07:39:22.63#ibcon#about to read 6, iclass 7, count 2 2006.162.07:39:22.63#ibcon#read 6, iclass 7, count 2 2006.162.07:39:22.63#ibcon#end of sib2, iclass 7, count 2 2006.162.07:39:22.63#ibcon#*mode == 0, iclass 7, count 2 2006.162.07:39:22.63#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.162.07:39:22.63#ibcon#[25=AT08-07\r\n] 2006.162.07:39:22.63#ibcon#*before write, iclass 7, count 2 2006.162.07:39:22.63#ibcon#enter sib2, iclass 7, count 2 2006.162.07:39:22.63#ibcon#flushed, iclass 7, count 2 2006.162.07:39:22.63#ibcon#about to write, iclass 7, count 2 2006.162.07:39:22.63#ibcon#wrote, iclass 7, count 2 2006.162.07:39:22.63#ibcon#about to read 3, iclass 7, count 2 2006.162.07:39:22.66#ibcon#read 3, iclass 7, count 2 2006.162.07:39:22.66#ibcon#about to read 4, iclass 7, count 2 2006.162.07:39:22.66#ibcon#read 4, iclass 7, count 2 2006.162.07:39:22.66#ibcon#about to read 5, iclass 7, count 2 2006.162.07:39:22.66#ibcon#read 5, iclass 7, count 2 2006.162.07:39:22.66#ibcon#about to read 6, iclass 7, count 2 2006.162.07:39:22.66#ibcon#read 6, iclass 7, count 2 2006.162.07:39:22.66#ibcon#end of sib2, iclass 7, count 2 2006.162.07:39:22.66#ibcon#*after write, iclass 7, count 2 2006.162.07:39:22.66#ibcon#*before return 0, iclass 7, count 2 2006.162.07:39:22.66#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.162.07:39:22.66#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.162.07:39:22.66#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.162.07:39:22.66#ibcon#ireg 7 cls_cnt 0 2006.162.07:39:22.66#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.162.07:39:22.78#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.162.07:39:22.78#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.162.07:39:22.78#ibcon#enter wrdev, iclass 7, count 0 2006.162.07:39:22.78#ibcon#first serial, iclass 7, count 0 2006.162.07:39:22.78#ibcon#enter sib2, iclass 7, count 0 2006.162.07:39:22.78#ibcon#flushed, iclass 7, count 0 2006.162.07:39:22.78#ibcon#about to write, iclass 7, count 0 2006.162.07:39:22.78#ibcon#wrote, iclass 7, count 0 2006.162.07:39:22.78#ibcon#about to read 3, iclass 7, count 0 2006.162.07:39:22.80#ibcon#read 3, iclass 7, count 0 2006.162.07:39:22.80#ibcon#about to read 4, iclass 7, count 0 2006.162.07:39:22.80#ibcon#read 4, iclass 7, count 0 2006.162.07:39:22.80#ibcon#about to read 5, iclass 7, count 0 2006.162.07:39:22.80#ibcon#read 5, iclass 7, count 0 2006.162.07:39:22.80#ibcon#about to read 6, iclass 7, count 0 2006.162.07:39:22.80#ibcon#read 6, iclass 7, count 0 2006.162.07:39:22.80#ibcon#end of sib2, iclass 7, count 0 2006.162.07:39:22.80#ibcon#*mode == 0, iclass 7, count 0 2006.162.07:39:22.80#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.162.07:39:22.80#ibcon#[25=USB\r\n] 2006.162.07:39:22.80#ibcon#*before write, iclass 7, count 0 2006.162.07:39:22.80#ibcon#enter sib2, iclass 7, count 0 2006.162.07:39:22.80#ibcon#flushed, iclass 7, count 0 2006.162.07:39:22.80#ibcon#about to write, iclass 7, count 0 2006.162.07:39:22.80#ibcon#wrote, iclass 7, count 0 2006.162.07:39:22.80#ibcon#about to read 3, iclass 7, count 0 2006.162.07:39:22.83#ibcon#read 3, iclass 7, count 0 2006.162.07:39:22.83#ibcon#about to read 4, iclass 7, count 0 2006.162.07:39:22.83#ibcon#read 4, iclass 7, count 0 2006.162.07:39:22.83#ibcon#about to read 5, iclass 7, count 0 2006.162.07:39:22.83#ibcon#read 5, iclass 7, count 0 2006.162.07:39:22.83#ibcon#about to read 6, iclass 7, count 0 2006.162.07:39:22.83#ibcon#read 6, iclass 7, count 0 2006.162.07:39:22.83#ibcon#end of sib2, iclass 7, count 0 2006.162.07:39:22.83#ibcon#*after write, iclass 7, count 0 2006.162.07:39:22.83#ibcon#*before return 0, iclass 7, count 0 2006.162.07:39:22.83#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.162.07:39:22.83#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.162.07:39:22.83#ibcon#about to clear, iclass 7 cls_cnt 0 2006.162.07:39:22.83#ibcon#cleared, iclass 7 cls_cnt 0 2006.162.07:39:22.83$vc4f8/vblo=1,632.99 2006.162.07:39:22.83#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.162.07:39:22.83#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.162.07:39:22.83#ibcon#ireg 17 cls_cnt 0 2006.162.07:39:22.83#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.162.07:39:22.83#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.162.07:39:22.83#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.162.07:39:22.83#ibcon#enter wrdev, iclass 11, count 0 2006.162.07:39:22.83#ibcon#first serial, iclass 11, count 0 2006.162.07:39:22.83#ibcon#enter sib2, iclass 11, count 0 2006.162.07:39:22.83#ibcon#flushed, iclass 11, count 0 2006.162.07:39:22.83#ibcon#about to write, iclass 11, count 0 2006.162.07:39:22.83#ibcon#wrote, iclass 11, count 0 2006.162.07:39:22.83#ibcon#about to read 3, iclass 11, count 0 2006.162.07:39:22.85#ibcon#read 3, iclass 11, count 0 2006.162.07:39:22.85#ibcon#about to read 4, iclass 11, count 0 2006.162.07:39:22.85#ibcon#read 4, iclass 11, count 0 2006.162.07:39:22.85#ibcon#about to read 5, iclass 11, count 0 2006.162.07:39:22.85#ibcon#read 5, iclass 11, count 0 2006.162.07:39:22.85#ibcon#about to read 6, iclass 11, count 0 2006.162.07:39:22.85#ibcon#read 6, iclass 11, count 0 2006.162.07:39:22.85#ibcon#end of sib2, iclass 11, count 0 2006.162.07:39:22.85#ibcon#*mode == 0, iclass 11, count 0 2006.162.07:39:22.85#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.162.07:39:22.85#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.07:39:22.85#ibcon#*before write, iclass 11, count 0 2006.162.07:39:22.85#ibcon#enter sib2, iclass 11, count 0 2006.162.07:39:22.85#ibcon#flushed, iclass 11, count 0 2006.162.07:39:22.85#ibcon#about to write, iclass 11, count 0 2006.162.07:39:22.85#ibcon#wrote, iclass 11, count 0 2006.162.07:39:22.85#ibcon#about to read 3, iclass 11, count 0 2006.162.07:39:22.89#ibcon#read 3, iclass 11, count 0 2006.162.07:39:22.89#ibcon#about to read 4, iclass 11, count 0 2006.162.07:39:22.89#ibcon#read 4, iclass 11, count 0 2006.162.07:39:22.89#ibcon#about to read 5, iclass 11, count 0 2006.162.07:39:22.89#ibcon#read 5, iclass 11, count 0 2006.162.07:39:22.89#ibcon#about to read 6, iclass 11, count 0 2006.162.07:39:22.89#ibcon#read 6, iclass 11, count 0 2006.162.07:39:22.89#ibcon#end of sib2, iclass 11, count 0 2006.162.07:39:22.89#ibcon#*after write, iclass 11, count 0 2006.162.07:39:22.89#ibcon#*before return 0, iclass 11, count 0 2006.162.07:39:22.89#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.162.07:39:22.89#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.162.07:39:22.89#ibcon#about to clear, iclass 11 cls_cnt 0 2006.162.07:39:22.89#ibcon#cleared, iclass 11 cls_cnt 0 2006.162.07:39:22.89$vc4f8/vb=1,4 2006.162.07:39:22.89#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.162.07:39:22.89#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.162.07:39:22.89#ibcon#ireg 11 cls_cnt 2 2006.162.07:39:22.89#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.162.07:39:22.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.162.07:39:22.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.162.07:39:22.89#ibcon#enter wrdev, iclass 13, count 2 2006.162.07:39:22.89#ibcon#first serial, iclass 13, count 2 2006.162.07:39:22.89#ibcon#enter sib2, iclass 13, count 2 2006.162.07:39:22.89#ibcon#flushed, iclass 13, count 2 2006.162.07:39:22.89#ibcon#about to write, iclass 13, count 2 2006.162.07:39:22.89#ibcon#wrote, iclass 13, count 2 2006.162.07:39:22.89#ibcon#about to read 3, iclass 13, count 2 2006.162.07:39:22.91#ibcon#read 3, iclass 13, count 2 2006.162.07:39:22.91#ibcon#about to read 4, iclass 13, count 2 2006.162.07:39:22.91#ibcon#read 4, iclass 13, count 2 2006.162.07:39:22.91#ibcon#about to read 5, iclass 13, count 2 2006.162.07:39:22.91#ibcon#read 5, iclass 13, count 2 2006.162.07:39:22.91#ibcon#about to read 6, iclass 13, count 2 2006.162.07:39:22.91#ibcon#read 6, iclass 13, count 2 2006.162.07:39:22.91#ibcon#end of sib2, iclass 13, count 2 2006.162.07:39:22.91#ibcon#*mode == 0, iclass 13, count 2 2006.162.07:39:22.91#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.162.07:39:22.91#ibcon#[27=AT01-04\r\n] 2006.162.07:39:22.91#ibcon#*before write, iclass 13, count 2 2006.162.07:39:22.91#ibcon#enter sib2, iclass 13, count 2 2006.162.07:39:22.91#ibcon#flushed, iclass 13, count 2 2006.162.07:39:22.91#ibcon#about to write, iclass 13, count 2 2006.162.07:39:22.91#ibcon#wrote, iclass 13, count 2 2006.162.07:39:22.91#ibcon#about to read 3, iclass 13, count 2 2006.162.07:39:22.94#ibcon#read 3, iclass 13, count 2 2006.162.07:39:22.94#ibcon#about to read 4, iclass 13, count 2 2006.162.07:39:22.94#ibcon#read 4, iclass 13, count 2 2006.162.07:39:22.94#ibcon#about to read 5, iclass 13, count 2 2006.162.07:39:22.94#ibcon#read 5, iclass 13, count 2 2006.162.07:39:22.94#ibcon#about to read 6, iclass 13, count 2 2006.162.07:39:22.94#ibcon#read 6, iclass 13, count 2 2006.162.07:39:22.94#ibcon#end of sib2, iclass 13, count 2 2006.162.07:39:22.94#ibcon#*after write, iclass 13, count 2 2006.162.07:39:22.94#ibcon#*before return 0, iclass 13, count 2 2006.162.07:39:22.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.162.07:39:22.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.162.07:39:22.94#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.162.07:39:22.94#ibcon#ireg 7 cls_cnt 0 2006.162.07:39:22.94#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.162.07:39:23.06#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.162.07:39:23.06#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.162.07:39:23.06#ibcon#enter wrdev, iclass 13, count 0 2006.162.07:39:23.06#ibcon#first serial, iclass 13, count 0 2006.162.07:39:23.06#ibcon#enter sib2, iclass 13, count 0 2006.162.07:39:23.06#ibcon#flushed, iclass 13, count 0 2006.162.07:39:23.06#ibcon#about to write, iclass 13, count 0 2006.162.07:39:23.06#ibcon#wrote, iclass 13, count 0 2006.162.07:39:23.06#ibcon#about to read 3, iclass 13, count 0 2006.162.07:39:23.08#ibcon#read 3, iclass 13, count 0 2006.162.07:39:23.08#ibcon#about to read 4, iclass 13, count 0 2006.162.07:39:23.08#ibcon#read 4, iclass 13, count 0 2006.162.07:39:23.08#ibcon#about to read 5, iclass 13, count 0 2006.162.07:39:23.08#ibcon#read 5, iclass 13, count 0 2006.162.07:39:23.08#ibcon#about to read 6, iclass 13, count 0 2006.162.07:39:23.08#ibcon#read 6, iclass 13, count 0 2006.162.07:39:23.08#ibcon#end of sib2, iclass 13, count 0 2006.162.07:39:23.08#ibcon#*mode == 0, iclass 13, count 0 2006.162.07:39:23.08#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.162.07:39:23.08#ibcon#[27=USB\r\n] 2006.162.07:39:23.08#ibcon#*before write, iclass 13, count 0 2006.162.07:39:23.08#ibcon#enter sib2, iclass 13, count 0 2006.162.07:39:23.08#ibcon#flushed, iclass 13, count 0 2006.162.07:39:23.08#ibcon#about to write, iclass 13, count 0 2006.162.07:39:23.08#ibcon#wrote, iclass 13, count 0 2006.162.07:39:23.08#ibcon#about to read 3, iclass 13, count 0 2006.162.07:39:23.11#ibcon#read 3, iclass 13, count 0 2006.162.07:39:23.11#ibcon#about to read 4, iclass 13, count 0 2006.162.07:39:23.11#ibcon#read 4, iclass 13, count 0 2006.162.07:39:23.11#ibcon#about to read 5, iclass 13, count 0 2006.162.07:39:23.11#ibcon#read 5, iclass 13, count 0 2006.162.07:39:23.11#ibcon#about to read 6, iclass 13, count 0 2006.162.07:39:23.11#ibcon#read 6, iclass 13, count 0 2006.162.07:39:23.11#ibcon#end of sib2, iclass 13, count 0 2006.162.07:39:23.11#ibcon#*after write, iclass 13, count 0 2006.162.07:39:23.11#ibcon#*before return 0, iclass 13, count 0 2006.162.07:39:23.11#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.162.07:39:23.11#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.162.07:39:23.11#ibcon#about to clear, iclass 13 cls_cnt 0 2006.162.07:39:23.11#ibcon#cleared, iclass 13 cls_cnt 0 2006.162.07:39:23.11$vc4f8/vblo=2,640.99 2006.162.07:39:23.11#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.162.07:39:23.11#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.162.07:39:23.11#ibcon#ireg 17 cls_cnt 0 2006.162.07:39:23.11#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:39:23.11#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:39:23.11#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:39:23.11#ibcon#enter wrdev, iclass 15, count 0 2006.162.07:39:23.11#ibcon#first serial, iclass 15, count 0 2006.162.07:39:23.11#ibcon#enter sib2, iclass 15, count 0 2006.162.07:39:23.11#ibcon#flushed, iclass 15, count 0 2006.162.07:39:23.11#ibcon#about to write, iclass 15, count 0 2006.162.07:39:23.11#ibcon#wrote, iclass 15, count 0 2006.162.07:39:23.11#ibcon#about to read 3, iclass 15, count 0 2006.162.07:39:23.13#ibcon#read 3, iclass 15, count 0 2006.162.07:39:23.13#ibcon#about to read 4, iclass 15, count 0 2006.162.07:39:23.13#ibcon#read 4, iclass 15, count 0 2006.162.07:39:23.13#ibcon#about to read 5, iclass 15, count 0 2006.162.07:39:23.13#ibcon#read 5, iclass 15, count 0 2006.162.07:39:23.13#ibcon#about to read 6, iclass 15, count 0 2006.162.07:39:23.13#ibcon#read 6, iclass 15, count 0 2006.162.07:39:23.13#ibcon#end of sib2, iclass 15, count 0 2006.162.07:39:23.13#ibcon#*mode == 0, iclass 15, count 0 2006.162.07:39:23.13#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.162.07:39:23.13#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.07:39:23.13#ibcon#*before write, iclass 15, count 0 2006.162.07:39:23.13#ibcon#enter sib2, iclass 15, count 0 2006.162.07:39:23.13#ibcon#flushed, iclass 15, count 0 2006.162.07:39:23.13#ibcon#about to write, iclass 15, count 0 2006.162.07:39:23.13#ibcon#wrote, iclass 15, count 0 2006.162.07:39:23.13#ibcon#about to read 3, iclass 15, count 0 2006.162.07:39:23.17#ibcon#read 3, iclass 15, count 0 2006.162.07:39:23.17#ibcon#about to read 4, iclass 15, count 0 2006.162.07:39:23.17#ibcon#read 4, iclass 15, count 0 2006.162.07:39:23.17#ibcon#about to read 5, iclass 15, count 0 2006.162.07:39:23.17#ibcon#read 5, iclass 15, count 0 2006.162.07:39:23.17#ibcon#about to read 6, iclass 15, count 0 2006.162.07:39:23.17#ibcon#read 6, iclass 15, count 0 2006.162.07:39:23.17#ibcon#end of sib2, iclass 15, count 0 2006.162.07:39:23.17#ibcon#*after write, iclass 15, count 0 2006.162.07:39:23.17#ibcon#*before return 0, iclass 15, count 0 2006.162.07:39:23.17#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:39:23.17#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:39:23.17#ibcon#about to clear, iclass 15 cls_cnt 0 2006.162.07:39:23.17#ibcon#cleared, iclass 15 cls_cnt 0 2006.162.07:39:23.17$vc4f8/vb=2,4 2006.162.07:39:23.17#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.162.07:39:23.17#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.162.07:39:23.17#ibcon#ireg 11 cls_cnt 2 2006.162.07:39:23.17#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:39:23.23#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:39:23.23#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:39:23.23#ibcon#enter wrdev, iclass 17, count 2 2006.162.07:39:23.23#ibcon#first serial, iclass 17, count 2 2006.162.07:39:23.23#ibcon#enter sib2, iclass 17, count 2 2006.162.07:39:23.23#ibcon#flushed, iclass 17, count 2 2006.162.07:39:23.23#ibcon#about to write, iclass 17, count 2 2006.162.07:39:23.23#ibcon#wrote, iclass 17, count 2 2006.162.07:39:23.23#ibcon#about to read 3, iclass 17, count 2 2006.162.07:39:23.25#ibcon#read 3, iclass 17, count 2 2006.162.07:39:23.25#ibcon#about to read 4, iclass 17, count 2 2006.162.07:39:23.25#ibcon#read 4, iclass 17, count 2 2006.162.07:39:23.25#ibcon#about to read 5, iclass 17, count 2 2006.162.07:39:23.25#ibcon#read 5, iclass 17, count 2 2006.162.07:39:23.25#ibcon#about to read 6, iclass 17, count 2 2006.162.07:39:23.25#ibcon#read 6, iclass 17, count 2 2006.162.07:39:23.25#ibcon#end of sib2, iclass 17, count 2 2006.162.07:39:23.25#ibcon#*mode == 0, iclass 17, count 2 2006.162.07:39:23.25#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.162.07:39:23.25#ibcon#[27=AT02-04\r\n] 2006.162.07:39:23.25#ibcon#*before write, iclass 17, count 2 2006.162.07:39:23.25#ibcon#enter sib2, iclass 17, count 2 2006.162.07:39:23.25#ibcon#flushed, iclass 17, count 2 2006.162.07:39:23.25#ibcon#about to write, iclass 17, count 2 2006.162.07:39:23.25#ibcon#wrote, iclass 17, count 2 2006.162.07:39:23.25#ibcon#about to read 3, iclass 17, count 2 2006.162.07:39:23.28#ibcon#read 3, iclass 17, count 2 2006.162.07:39:23.28#ibcon#about to read 4, iclass 17, count 2 2006.162.07:39:23.28#ibcon#read 4, iclass 17, count 2 2006.162.07:39:23.28#ibcon#about to read 5, iclass 17, count 2 2006.162.07:39:23.28#ibcon#read 5, iclass 17, count 2 2006.162.07:39:23.28#ibcon#about to read 6, iclass 17, count 2 2006.162.07:39:23.28#ibcon#read 6, iclass 17, count 2 2006.162.07:39:23.28#ibcon#end of sib2, iclass 17, count 2 2006.162.07:39:23.28#ibcon#*after write, iclass 17, count 2 2006.162.07:39:23.28#ibcon#*before return 0, iclass 17, count 2 2006.162.07:39:23.28#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:39:23.28#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:39:23.28#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.162.07:39:23.28#ibcon#ireg 7 cls_cnt 0 2006.162.07:39:23.28#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:39:23.40#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:39:23.40#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:39:23.40#ibcon#enter wrdev, iclass 17, count 0 2006.162.07:39:23.40#ibcon#first serial, iclass 17, count 0 2006.162.07:39:23.40#ibcon#enter sib2, iclass 17, count 0 2006.162.07:39:23.40#ibcon#flushed, iclass 17, count 0 2006.162.07:39:23.40#ibcon#about to write, iclass 17, count 0 2006.162.07:39:23.40#ibcon#wrote, iclass 17, count 0 2006.162.07:39:23.40#ibcon#about to read 3, iclass 17, count 0 2006.162.07:39:23.42#ibcon#read 3, iclass 17, count 0 2006.162.07:39:23.42#ibcon#about to read 4, iclass 17, count 0 2006.162.07:39:23.42#ibcon#read 4, iclass 17, count 0 2006.162.07:39:23.42#ibcon#about to read 5, iclass 17, count 0 2006.162.07:39:23.42#ibcon#read 5, iclass 17, count 0 2006.162.07:39:23.42#ibcon#about to read 6, iclass 17, count 0 2006.162.07:39:23.42#ibcon#read 6, iclass 17, count 0 2006.162.07:39:23.42#ibcon#end of sib2, iclass 17, count 0 2006.162.07:39:23.42#ibcon#*mode == 0, iclass 17, count 0 2006.162.07:39:23.42#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.162.07:39:23.42#ibcon#[27=USB\r\n] 2006.162.07:39:23.42#ibcon#*before write, iclass 17, count 0 2006.162.07:39:23.42#ibcon#enter sib2, iclass 17, count 0 2006.162.07:39:23.42#ibcon#flushed, iclass 17, count 0 2006.162.07:39:23.42#ibcon#about to write, iclass 17, count 0 2006.162.07:39:23.42#ibcon#wrote, iclass 17, count 0 2006.162.07:39:23.42#ibcon#about to read 3, iclass 17, count 0 2006.162.07:39:23.45#ibcon#read 3, iclass 17, count 0 2006.162.07:39:23.45#ibcon#about to read 4, iclass 17, count 0 2006.162.07:39:23.45#ibcon#read 4, iclass 17, count 0 2006.162.07:39:23.45#ibcon#about to read 5, iclass 17, count 0 2006.162.07:39:23.45#ibcon#read 5, iclass 17, count 0 2006.162.07:39:23.45#ibcon#about to read 6, iclass 17, count 0 2006.162.07:39:23.45#ibcon#read 6, iclass 17, count 0 2006.162.07:39:23.45#ibcon#end of sib2, iclass 17, count 0 2006.162.07:39:23.45#ibcon#*after write, iclass 17, count 0 2006.162.07:39:23.45#ibcon#*before return 0, iclass 17, count 0 2006.162.07:39:23.45#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:39:23.45#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:39:23.45#ibcon#about to clear, iclass 17 cls_cnt 0 2006.162.07:39:23.45#ibcon#cleared, iclass 17 cls_cnt 0 2006.162.07:39:23.45$vc4f8/vblo=3,656.99 2006.162.07:39:23.45#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.162.07:39:23.45#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.162.07:39:23.45#ibcon#ireg 17 cls_cnt 0 2006.162.07:39:23.45#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:39:23.45#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:39:23.45#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:39:23.45#ibcon#enter wrdev, iclass 19, count 0 2006.162.07:39:23.45#ibcon#first serial, iclass 19, count 0 2006.162.07:39:23.45#ibcon#enter sib2, iclass 19, count 0 2006.162.07:39:23.45#ibcon#flushed, iclass 19, count 0 2006.162.07:39:23.45#ibcon#about to write, iclass 19, count 0 2006.162.07:39:23.45#ibcon#wrote, iclass 19, count 0 2006.162.07:39:23.45#ibcon#about to read 3, iclass 19, count 0 2006.162.07:39:23.47#ibcon#read 3, iclass 19, count 0 2006.162.07:39:23.47#ibcon#about to read 4, iclass 19, count 0 2006.162.07:39:23.47#ibcon#read 4, iclass 19, count 0 2006.162.07:39:23.47#ibcon#about to read 5, iclass 19, count 0 2006.162.07:39:23.47#ibcon#read 5, iclass 19, count 0 2006.162.07:39:23.47#ibcon#about to read 6, iclass 19, count 0 2006.162.07:39:23.47#ibcon#read 6, iclass 19, count 0 2006.162.07:39:23.47#ibcon#end of sib2, iclass 19, count 0 2006.162.07:39:23.47#ibcon#*mode == 0, iclass 19, count 0 2006.162.07:39:23.47#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.162.07:39:23.47#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.07:39:23.47#ibcon#*before write, iclass 19, count 0 2006.162.07:39:23.47#ibcon#enter sib2, iclass 19, count 0 2006.162.07:39:23.47#ibcon#flushed, iclass 19, count 0 2006.162.07:39:23.47#ibcon#about to write, iclass 19, count 0 2006.162.07:39:23.47#ibcon#wrote, iclass 19, count 0 2006.162.07:39:23.47#ibcon#about to read 3, iclass 19, count 0 2006.162.07:39:23.51#ibcon#read 3, iclass 19, count 0 2006.162.07:39:23.51#ibcon#about to read 4, iclass 19, count 0 2006.162.07:39:23.51#ibcon#read 4, iclass 19, count 0 2006.162.07:39:23.51#ibcon#about to read 5, iclass 19, count 0 2006.162.07:39:23.51#ibcon#read 5, iclass 19, count 0 2006.162.07:39:23.51#ibcon#about to read 6, iclass 19, count 0 2006.162.07:39:23.51#ibcon#read 6, iclass 19, count 0 2006.162.07:39:23.51#ibcon#end of sib2, iclass 19, count 0 2006.162.07:39:23.51#ibcon#*after write, iclass 19, count 0 2006.162.07:39:23.51#ibcon#*before return 0, iclass 19, count 0 2006.162.07:39:23.51#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:39:23.51#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:39:23.51#ibcon#about to clear, iclass 19 cls_cnt 0 2006.162.07:39:23.51#ibcon#cleared, iclass 19 cls_cnt 0 2006.162.07:39:23.51$vc4f8/vb=3,4 2006.162.07:39:23.51#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.162.07:39:23.51#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.162.07:39:23.51#ibcon#ireg 11 cls_cnt 2 2006.162.07:39:23.51#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:39:23.57#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:39:23.57#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:39:23.57#ibcon#enter wrdev, iclass 21, count 2 2006.162.07:39:23.57#ibcon#first serial, iclass 21, count 2 2006.162.07:39:23.57#ibcon#enter sib2, iclass 21, count 2 2006.162.07:39:23.57#ibcon#flushed, iclass 21, count 2 2006.162.07:39:23.57#ibcon#about to write, iclass 21, count 2 2006.162.07:39:23.57#ibcon#wrote, iclass 21, count 2 2006.162.07:39:23.57#ibcon#about to read 3, iclass 21, count 2 2006.162.07:39:23.59#ibcon#read 3, iclass 21, count 2 2006.162.07:39:23.59#ibcon#about to read 4, iclass 21, count 2 2006.162.07:39:23.59#ibcon#read 4, iclass 21, count 2 2006.162.07:39:23.59#ibcon#about to read 5, iclass 21, count 2 2006.162.07:39:23.59#ibcon#read 5, iclass 21, count 2 2006.162.07:39:23.59#ibcon#about to read 6, iclass 21, count 2 2006.162.07:39:23.59#ibcon#read 6, iclass 21, count 2 2006.162.07:39:23.59#ibcon#end of sib2, iclass 21, count 2 2006.162.07:39:23.59#ibcon#*mode == 0, iclass 21, count 2 2006.162.07:39:23.59#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.162.07:39:23.59#ibcon#[27=AT03-04\r\n] 2006.162.07:39:23.59#ibcon#*before write, iclass 21, count 2 2006.162.07:39:23.59#ibcon#enter sib2, iclass 21, count 2 2006.162.07:39:23.59#ibcon#flushed, iclass 21, count 2 2006.162.07:39:23.59#ibcon#about to write, iclass 21, count 2 2006.162.07:39:23.59#ibcon#wrote, iclass 21, count 2 2006.162.07:39:23.59#ibcon#about to read 3, iclass 21, count 2 2006.162.07:39:23.62#ibcon#read 3, iclass 21, count 2 2006.162.07:39:23.62#ibcon#about to read 4, iclass 21, count 2 2006.162.07:39:23.62#ibcon#read 4, iclass 21, count 2 2006.162.07:39:23.62#ibcon#about to read 5, iclass 21, count 2 2006.162.07:39:23.62#ibcon#read 5, iclass 21, count 2 2006.162.07:39:23.62#ibcon#about to read 6, iclass 21, count 2 2006.162.07:39:23.62#ibcon#read 6, iclass 21, count 2 2006.162.07:39:23.62#ibcon#end of sib2, iclass 21, count 2 2006.162.07:39:23.62#ibcon#*after write, iclass 21, count 2 2006.162.07:39:23.62#ibcon#*before return 0, iclass 21, count 2 2006.162.07:39:23.62#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:39:23.62#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:39:23.62#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.162.07:39:23.62#ibcon#ireg 7 cls_cnt 0 2006.162.07:39:23.62#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:39:23.74#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:39:23.74#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:39:23.74#ibcon#enter wrdev, iclass 21, count 0 2006.162.07:39:23.74#ibcon#first serial, iclass 21, count 0 2006.162.07:39:23.74#ibcon#enter sib2, iclass 21, count 0 2006.162.07:39:23.74#ibcon#flushed, iclass 21, count 0 2006.162.07:39:23.74#ibcon#about to write, iclass 21, count 0 2006.162.07:39:23.74#ibcon#wrote, iclass 21, count 0 2006.162.07:39:23.74#ibcon#about to read 3, iclass 21, count 0 2006.162.07:39:23.76#ibcon#read 3, iclass 21, count 0 2006.162.07:39:23.76#ibcon#about to read 4, iclass 21, count 0 2006.162.07:39:23.76#ibcon#read 4, iclass 21, count 0 2006.162.07:39:23.76#ibcon#about to read 5, iclass 21, count 0 2006.162.07:39:23.76#ibcon#read 5, iclass 21, count 0 2006.162.07:39:23.76#ibcon#about to read 6, iclass 21, count 0 2006.162.07:39:23.76#ibcon#read 6, iclass 21, count 0 2006.162.07:39:23.76#ibcon#end of sib2, iclass 21, count 0 2006.162.07:39:23.76#ibcon#*mode == 0, iclass 21, count 0 2006.162.07:39:23.76#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.162.07:39:23.76#ibcon#[27=USB\r\n] 2006.162.07:39:23.76#ibcon#*before write, iclass 21, count 0 2006.162.07:39:23.76#ibcon#enter sib2, iclass 21, count 0 2006.162.07:39:23.76#ibcon#flushed, iclass 21, count 0 2006.162.07:39:23.76#ibcon#about to write, iclass 21, count 0 2006.162.07:39:23.76#ibcon#wrote, iclass 21, count 0 2006.162.07:39:23.76#ibcon#about to read 3, iclass 21, count 0 2006.162.07:39:23.79#ibcon#read 3, iclass 21, count 0 2006.162.07:39:23.79#ibcon#about to read 4, iclass 21, count 0 2006.162.07:39:23.79#ibcon#read 4, iclass 21, count 0 2006.162.07:39:23.79#ibcon#about to read 5, iclass 21, count 0 2006.162.07:39:23.79#ibcon#read 5, iclass 21, count 0 2006.162.07:39:23.79#ibcon#about to read 6, iclass 21, count 0 2006.162.07:39:23.79#ibcon#read 6, iclass 21, count 0 2006.162.07:39:23.79#ibcon#end of sib2, iclass 21, count 0 2006.162.07:39:23.79#ibcon#*after write, iclass 21, count 0 2006.162.07:39:23.79#ibcon#*before return 0, iclass 21, count 0 2006.162.07:39:23.79#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:39:23.79#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:39:23.79#ibcon#about to clear, iclass 21 cls_cnt 0 2006.162.07:39:23.79#ibcon#cleared, iclass 21 cls_cnt 0 2006.162.07:39:23.79$vc4f8/vblo=4,712.99 2006.162.07:39:23.79#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.162.07:39:23.79#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.162.07:39:23.79#ibcon#ireg 17 cls_cnt 0 2006.162.07:39:23.79#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:39:23.79#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:39:23.79#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:39:23.79#ibcon#enter wrdev, iclass 23, count 0 2006.162.07:39:23.79#ibcon#first serial, iclass 23, count 0 2006.162.07:39:23.79#ibcon#enter sib2, iclass 23, count 0 2006.162.07:39:23.79#ibcon#flushed, iclass 23, count 0 2006.162.07:39:23.79#ibcon#about to write, iclass 23, count 0 2006.162.07:39:23.79#ibcon#wrote, iclass 23, count 0 2006.162.07:39:23.79#ibcon#about to read 3, iclass 23, count 0 2006.162.07:39:23.81#ibcon#read 3, iclass 23, count 0 2006.162.07:39:23.81#ibcon#about to read 4, iclass 23, count 0 2006.162.07:39:23.81#ibcon#read 4, iclass 23, count 0 2006.162.07:39:23.81#ibcon#about to read 5, iclass 23, count 0 2006.162.07:39:23.81#ibcon#read 5, iclass 23, count 0 2006.162.07:39:23.81#ibcon#about to read 6, iclass 23, count 0 2006.162.07:39:23.81#ibcon#read 6, iclass 23, count 0 2006.162.07:39:23.81#ibcon#end of sib2, iclass 23, count 0 2006.162.07:39:23.81#ibcon#*mode == 0, iclass 23, count 0 2006.162.07:39:23.81#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.162.07:39:23.81#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.07:39:23.81#ibcon#*before write, iclass 23, count 0 2006.162.07:39:23.81#ibcon#enter sib2, iclass 23, count 0 2006.162.07:39:23.81#ibcon#flushed, iclass 23, count 0 2006.162.07:39:23.81#ibcon#about to write, iclass 23, count 0 2006.162.07:39:23.81#ibcon#wrote, iclass 23, count 0 2006.162.07:39:23.81#ibcon#about to read 3, iclass 23, count 0 2006.162.07:39:23.85#ibcon#read 3, iclass 23, count 0 2006.162.07:39:23.85#ibcon#about to read 4, iclass 23, count 0 2006.162.07:39:23.85#ibcon#read 4, iclass 23, count 0 2006.162.07:39:23.85#ibcon#about to read 5, iclass 23, count 0 2006.162.07:39:23.85#ibcon#read 5, iclass 23, count 0 2006.162.07:39:23.85#ibcon#about to read 6, iclass 23, count 0 2006.162.07:39:23.85#ibcon#read 6, iclass 23, count 0 2006.162.07:39:23.85#ibcon#end of sib2, iclass 23, count 0 2006.162.07:39:23.85#ibcon#*after write, iclass 23, count 0 2006.162.07:39:23.85#ibcon#*before return 0, iclass 23, count 0 2006.162.07:39:23.85#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:39:23.85#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:39:23.85#ibcon#about to clear, iclass 23 cls_cnt 0 2006.162.07:39:23.85#ibcon#cleared, iclass 23 cls_cnt 0 2006.162.07:39:23.85$vc4f8/vb=4,4 2006.162.07:39:23.85#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.162.07:39:23.85#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.162.07:39:23.85#ibcon#ireg 11 cls_cnt 2 2006.162.07:39:23.85#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.162.07:39:23.91#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.162.07:39:23.91#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.162.07:39:23.91#ibcon#enter wrdev, iclass 25, count 2 2006.162.07:39:23.91#ibcon#first serial, iclass 25, count 2 2006.162.07:39:23.91#ibcon#enter sib2, iclass 25, count 2 2006.162.07:39:23.91#ibcon#flushed, iclass 25, count 2 2006.162.07:39:23.91#ibcon#about to write, iclass 25, count 2 2006.162.07:39:23.91#ibcon#wrote, iclass 25, count 2 2006.162.07:39:23.91#ibcon#about to read 3, iclass 25, count 2 2006.162.07:39:23.93#ibcon#read 3, iclass 25, count 2 2006.162.07:39:23.93#ibcon#about to read 4, iclass 25, count 2 2006.162.07:39:23.93#ibcon#read 4, iclass 25, count 2 2006.162.07:39:23.93#ibcon#about to read 5, iclass 25, count 2 2006.162.07:39:23.93#ibcon#read 5, iclass 25, count 2 2006.162.07:39:23.93#ibcon#about to read 6, iclass 25, count 2 2006.162.07:39:23.93#ibcon#read 6, iclass 25, count 2 2006.162.07:39:23.93#ibcon#end of sib2, iclass 25, count 2 2006.162.07:39:23.93#ibcon#*mode == 0, iclass 25, count 2 2006.162.07:39:23.93#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.162.07:39:23.93#ibcon#[27=AT04-04\r\n] 2006.162.07:39:23.93#ibcon#*before write, iclass 25, count 2 2006.162.07:39:23.93#ibcon#enter sib2, iclass 25, count 2 2006.162.07:39:23.93#ibcon#flushed, iclass 25, count 2 2006.162.07:39:23.93#ibcon#about to write, iclass 25, count 2 2006.162.07:39:23.93#ibcon#wrote, iclass 25, count 2 2006.162.07:39:23.93#ibcon#about to read 3, iclass 25, count 2 2006.162.07:39:23.96#ibcon#read 3, iclass 25, count 2 2006.162.07:39:23.96#ibcon#about to read 4, iclass 25, count 2 2006.162.07:39:23.96#ibcon#read 4, iclass 25, count 2 2006.162.07:39:23.96#ibcon#about to read 5, iclass 25, count 2 2006.162.07:39:23.96#ibcon#read 5, iclass 25, count 2 2006.162.07:39:23.96#ibcon#about to read 6, iclass 25, count 2 2006.162.07:39:23.96#ibcon#read 6, iclass 25, count 2 2006.162.07:39:23.96#ibcon#end of sib2, iclass 25, count 2 2006.162.07:39:23.96#ibcon#*after write, iclass 25, count 2 2006.162.07:39:23.96#ibcon#*before return 0, iclass 25, count 2 2006.162.07:39:23.96#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.162.07:39:23.96#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.162.07:39:23.96#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.162.07:39:23.96#ibcon#ireg 7 cls_cnt 0 2006.162.07:39:23.96#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.162.07:39:24.08#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.162.07:39:24.08#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.162.07:39:24.08#ibcon#enter wrdev, iclass 25, count 0 2006.162.07:39:24.08#ibcon#first serial, iclass 25, count 0 2006.162.07:39:24.08#ibcon#enter sib2, iclass 25, count 0 2006.162.07:39:24.08#ibcon#flushed, iclass 25, count 0 2006.162.07:39:24.08#ibcon#about to write, iclass 25, count 0 2006.162.07:39:24.08#ibcon#wrote, iclass 25, count 0 2006.162.07:39:24.08#ibcon#about to read 3, iclass 25, count 0 2006.162.07:39:24.10#ibcon#read 3, iclass 25, count 0 2006.162.07:39:24.10#ibcon#about to read 4, iclass 25, count 0 2006.162.07:39:24.10#ibcon#read 4, iclass 25, count 0 2006.162.07:39:24.10#ibcon#about to read 5, iclass 25, count 0 2006.162.07:39:24.10#ibcon#read 5, iclass 25, count 0 2006.162.07:39:24.10#ibcon#about to read 6, iclass 25, count 0 2006.162.07:39:24.10#ibcon#read 6, iclass 25, count 0 2006.162.07:39:24.10#ibcon#end of sib2, iclass 25, count 0 2006.162.07:39:24.10#ibcon#*mode == 0, iclass 25, count 0 2006.162.07:39:24.10#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.162.07:39:24.10#ibcon#[27=USB\r\n] 2006.162.07:39:24.10#ibcon#*before write, iclass 25, count 0 2006.162.07:39:24.10#ibcon#enter sib2, iclass 25, count 0 2006.162.07:39:24.10#ibcon#flushed, iclass 25, count 0 2006.162.07:39:24.10#ibcon#about to write, iclass 25, count 0 2006.162.07:39:24.10#ibcon#wrote, iclass 25, count 0 2006.162.07:39:24.10#ibcon#about to read 3, iclass 25, count 0 2006.162.07:39:24.13#ibcon#read 3, iclass 25, count 0 2006.162.07:39:24.13#ibcon#about to read 4, iclass 25, count 0 2006.162.07:39:24.13#ibcon#read 4, iclass 25, count 0 2006.162.07:39:24.13#ibcon#about to read 5, iclass 25, count 0 2006.162.07:39:24.13#ibcon#read 5, iclass 25, count 0 2006.162.07:39:24.13#ibcon#about to read 6, iclass 25, count 0 2006.162.07:39:24.13#ibcon#read 6, iclass 25, count 0 2006.162.07:39:24.13#ibcon#end of sib2, iclass 25, count 0 2006.162.07:39:24.13#ibcon#*after write, iclass 25, count 0 2006.162.07:39:24.13#ibcon#*before return 0, iclass 25, count 0 2006.162.07:39:24.13#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.162.07:39:24.13#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.162.07:39:24.13#ibcon#about to clear, iclass 25 cls_cnt 0 2006.162.07:39:24.13#ibcon#cleared, iclass 25 cls_cnt 0 2006.162.07:39:24.13$vc4f8/vblo=5,744.99 2006.162.07:39:24.13#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.162.07:39:24.13#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.162.07:39:24.13#ibcon#ireg 17 cls_cnt 0 2006.162.07:39:24.13#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:39:24.13#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:39:24.13#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:39:24.13#ibcon#enter wrdev, iclass 27, count 0 2006.162.07:39:24.13#ibcon#first serial, iclass 27, count 0 2006.162.07:39:24.13#ibcon#enter sib2, iclass 27, count 0 2006.162.07:39:24.13#ibcon#flushed, iclass 27, count 0 2006.162.07:39:24.13#ibcon#about to write, iclass 27, count 0 2006.162.07:39:24.13#ibcon#wrote, iclass 27, count 0 2006.162.07:39:24.13#ibcon#about to read 3, iclass 27, count 0 2006.162.07:39:24.15#ibcon#read 3, iclass 27, count 0 2006.162.07:39:24.15#ibcon#about to read 4, iclass 27, count 0 2006.162.07:39:24.15#ibcon#read 4, iclass 27, count 0 2006.162.07:39:24.15#ibcon#about to read 5, iclass 27, count 0 2006.162.07:39:24.15#ibcon#read 5, iclass 27, count 0 2006.162.07:39:24.15#ibcon#about to read 6, iclass 27, count 0 2006.162.07:39:24.15#ibcon#read 6, iclass 27, count 0 2006.162.07:39:24.15#ibcon#end of sib2, iclass 27, count 0 2006.162.07:39:24.15#ibcon#*mode == 0, iclass 27, count 0 2006.162.07:39:24.15#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.162.07:39:24.15#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.07:39:24.15#ibcon#*before write, iclass 27, count 0 2006.162.07:39:24.15#ibcon#enter sib2, iclass 27, count 0 2006.162.07:39:24.15#ibcon#flushed, iclass 27, count 0 2006.162.07:39:24.15#ibcon#about to write, iclass 27, count 0 2006.162.07:39:24.15#ibcon#wrote, iclass 27, count 0 2006.162.07:39:24.15#ibcon#about to read 3, iclass 27, count 0 2006.162.07:39:24.19#ibcon#read 3, iclass 27, count 0 2006.162.07:39:24.19#ibcon#about to read 4, iclass 27, count 0 2006.162.07:39:24.19#ibcon#read 4, iclass 27, count 0 2006.162.07:39:24.19#ibcon#about to read 5, iclass 27, count 0 2006.162.07:39:24.19#ibcon#read 5, iclass 27, count 0 2006.162.07:39:24.19#ibcon#about to read 6, iclass 27, count 0 2006.162.07:39:24.19#ibcon#read 6, iclass 27, count 0 2006.162.07:39:24.19#ibcon#end of sib2, iclass 27, count 0 2006.162.07:39:24.19#ibcon#*after write, iclass 27, count 0 2006.162.07:39:24.19#ibcon#*before return 0, iclass 27, count 0 2006.162.07:39:24.19#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:39:24.19#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:39:24.19#ibcon#about to clear, iclass 27 cls_cnt 0 2006.162.07:39:24.19#ibcon#cleared, iclass 27 cls_cnt 0 2006.162.07:39:24.19$vc4f8/vb=5,4 2006.162.07:39:24.19#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.162.07:39:24.19#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.162.07:39:24.19#ibcon#ireg 11 cls_cnt 2 2006.162.07:39:24.19#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.162.07:39:24.25#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.162.07:39:24.25#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.162.07:39:24.25#ibcon#enter wrdev, iclass 29, count 2 2006.162.07:39:24.25#ibcon#first serial, iclass 29, count 2 2006.162.07:39:24.25#ibcon#enter sib2, iclass 29, count 2 2006.162.07:39:24.25#ibcon#flushed, iclass 29, count 2 2006.162.07:39:24.25#ibcon#about to write, iclass 29, count 2 2006.162.07:39:24.25#ibcon#wrote, iclass 29, count 2 2006.162.07:39:24.25#ibcon#about to read 3, iclass 29, count 2 2006.162.07:39:24.27#ibcon#read 3, iclass 29, count 2 2006.162.07:39:24.27#ibcon#about to read 4, iclass 29, count 2 2006.162.07:39:24.27#ibcon#read 4, iclass 29, count 2 2006.162.07:39:24.27#ibcon#about to read 5, iclass 29, count 2 2006.162.07:39:24.27#ibcon#read 5, iclass 29, count 2 2006.162.07:39:24.27#ibcon#about to read 6, iclass 29, count 2 2006.162.07:39:24.27#ibcon#read 6, iclass 29, count 2 2006.162.07:39:24.27#ibcon#end of sib2, iclass 29, count 2 2006.162.07:39:24.27#ibcon#*mode == 0, iclass 29, count 2 2006.162.07:39:24.27#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.162.07:39:24.27#ibcon#[27=AT05-04\r\n] 2006.162.07:39:24.27#ibcon#*before write, iclass 29, count 2 2006.162.07:39:24.27#ibcon#enter sib2, iclass 29, count 2 2006.162.07:39:24.27#ibcon#flushed, iclass 29, count 2 2006.162.07:39:24.27#ibcon#about to write, iclass 29, count 2 2006.162.07:39:24.27#ibcon#wrote, iclass 29, count 2 2006.162.07:39:24.27#ibcon#about to read 3, iclass 29, count 2 2006.162.07:39:24.30#ibcon#read 3, iclass 29, count 2 2006.162.07:39:24.30#ibcon#about to read 4, iclass 29, count 2 2006.162.07:39:24.30#ibcon#read 4, iclass 29, count 2 2006.162.07:39:24.30#ibcon#about to read 5, iclass 29, count 2 2006.162.07:39:24.30#ibcon#read 5, iclass 29, count 2 2006.162.07:39:24.30#ibcon#about to read 6, iclass 29, count 2 2006.162.07:39:24.30#ibcon#read 6, iclass 29, count 2 2006.162.07:39:24.30#ibcon#end of sib2, iclass 29, count 2 2006.162.07:39:24.30#ibcon#*after write, iclass 29, count 2 2006.162.07:39:24.30#ibcon#*before return 0, iclass 29, count 2 2006.162.07:39:24.30#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.162.07:39:24.30#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.162.07:39:24.30#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.162.07:39:24.30#ibcon#ireg 7 cls_cnt 0 2006.162.07:39:24.30#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.162.07:39:24.42#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.162.07:39:24.42#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.162.07:39:24.42#ibcon#enter wrdev, iclass 29, count 0 2006.162.07:39:24.42#ibcon#first serial, iclass 29, count 0 2006.162.07:39:24.42#ibcon#enter sib2, iclass 29, count 0 2006.162.07:39:24.42#ibcon#flushed, iclass 29, count 0 2006.162.07:39:24.42#ibcon#about to write, iclass 29, count 0 2006.162.07:39:24.42#ibcon#wrote, iclass 29, count 0 2006.162.07:39:24.42#ibcon#about to read 3, iclass 29, count 0 2006.162.07:39:24.44#ibcon#read 3, iclass 29, count 0 2006.162.07:39:24.44#ibcon#about to read 4, iclass 29, count 0 2006.162.07:39:24.44#ibcon#read 4, iclass 29, count 0 2006.162.07:39:24.44#ibcon#about to read 5, iclass 29, count 0 2006.162.07:39:24.44#ibcon#read 5, iclass 29, count 0 2006.162.07:39:24.44#ibcon#about to read 6, iclass 29, count 0 2006.162.07:39:24.44#ibcon#read 6, iclass 29, count 0 2006.162.07:39:24.44#ibcon#end of sib2, iclass 29, count 0 2006.162.07:39:24.44#ibcon#*mode == 0, iclass 29, count 0 2006.162.07:39:24.44#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.162.07:39:24.44#ibcon#[27=USB\r\n] 2006.162.07:39:24.44#ibcon#*before write, iclass 29, count 0 2006.162.07:39:24.44#ibcon#enter sib2, iclass 29, count 0 2006.162.07:39:24.44#ibcon#flushed, iclass 29, count 0 2006.162.07:39:24.44#ibcon#about to write, iclass 29, count 0 2006.162.07:39:24.44#ibcon#wrote, iclass 29, count 0 2006.162.07:39:24.44#ibcon#about to read 3, iclass 29, count 0 2006.162.07:39:24.47#ibcon#read 3, iclass 29, count 0 2006.162.07:39:24.47#ibcon#about to read 4, iclass 29, count 0 2006.162.07:39:24.47#ibcon#read 4, iclass 29, count 0 2006.162.07:39:24.47#ibcon#about to read 5, iclass 29, count 0 2006.162.07:39:24.47#ibcon#read 5, iclass 29, count 0 2006.162.07:39:24.47#ibcon#about to read 6, iclass 29, count 0 2006.162.07:39:24.47#ibcon#read 6, iclass 29, count 0 2006.162.07:39:24.47#ibcon#end of sib2, iclass 29, count 0 2006.162.07:39:24.47#ibcon#*after write, iclass 29, count 0 2006.162.07:39:24.47#ibcon#*before return 0, iclass 29, count 0 2006.162.07:39:24.47#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.162.07:39:24.47#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.162.07:39:24.47#ibcon#about to clear, iclass 29 cls_cnt 0 2006.162.07:39:24.47#ibcon#cleared, iclass 29 cls_cnt 0 2006.162.07:39:24.47$vc4f8/vblo=6,752.99 2006.162.07:39:24.47#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.162.07:39:24.47#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.162.07:39:24.47#ibcon#ireg 17 cls_cnt 0 2006.162.07:39:24.47#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.162.07:39:24.47#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.162.07:39:24.47#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.162.07:39:24.47#ibcon#enter wrdev, iclass 31, count 0 2006.162.07:39:24.47#ibcon#first serial, iclass 31, count 0 2006.162.07:39:24.47#ibcon#enter sib2, iclass 31, count 0 2006.162.07:39:24.47#ibcon#flushed, iclass 31, count 0 2006.162.07:39:24.47#ibcon#about to write, iclass 31, count 0 2006.162.07:39:24.47#ibcon#wrote, iclass 31, count 0 2006.162.07:39:24.47#ibcon#about to read 3, iclass 31, count 0 2006.162.07:39:24.49#ibcon#read 3, iclass 31, count 0 2006.162.07:39:24.49#ibcon#about to read 4, iclass 31, count 0 2006.162.07:39:24.49#ibcon#read 4, iclass 31, count 0 2006.162.07:39:24.49#ibcon#about to read 5, iclass 31, count 0 2006.162.07:39:24.49#ibcon#read 5, iclass 31, count 0 2006.162.07:39:24.49#ibcon#about to read 6, iclass 31, count 0 2006.162.07:39:24.49#ibcon#read 6, iclass 31, count 0 2006.162.07:39:24.49#ibcon#end of sib2, iclass 31, count 0 2006.162.07:39:24.49#ibcon#*mode == 0, iclass 31, count 0 2006.162.07:39:24.49#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.162.07:39:24.49#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.07:39:24.49#ibcon#*before write, iclass 31, count 0 2006.162.07:39:24.49#ibcon#enter sib2, iclass 31, count 0 2006.162.07:39:24.49#ibcon#flushed, iclass 31, count 0 2006.162.07:39:24.49#ibcon#about to write, iclass 31, count 0 2006.162.07:39:24.49#ibcon#wrote, iclass 31, count 0 2006.162.07:39:24.49#ibcon#about to read 3, iclass 31, count 0 2006.162.07:39:24.53#ibcon#read 3, iclass 31, count 0 2006.162.07:39:24.53#ibcon#about to read 4, iclass 31, count 0 2006.162.07:39:24.53#ibcon#read 4, iclass 31, count 0 2006.162.07:39:24.53#ibcon#about to read 5, iclass 31, count 0 2006.162.07:39:24.53#ibcon#read 5, iclass 31, count 0 2006.162.07:39:24.53#ibcon#about to read 6, iclass 31, count 0 2006.162.07:39:24.53#ibcon#read 6, iclass 31, count 0 2006.162.07:39:24.53#ibcon#end of sib2, iclass 31, count 0 2006.162.07:39:24.53#ibcon#*after write, iclass 31, count 0 2006.162.07:39:24.53#ibcon#*before return 0, iclass 31, count 0 2006.162.07:39:24.53#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.162.07:39:24.53#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.162.07:39:24.53#ibcon#about to clear, iclass 31 cls_cnt 0 2006.162.07:39:24.53#ibcon#cleared, iclass 31 cls_cnt 0 2006.162.07:39:24.53$vc4f8/vb=6,4 2006.162.07:39:24.53#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.162.07:39:24.53#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.162.07:39:24.53#ibcon#ireg 11 cls_cnt 2 2006.162.07:39:24.53#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.162.07:39:24.59#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.162.07:39:24.59#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.162.07:39:24.59#ibcon#enter wrdev, iclass 33, count 2 2006.162.07:39:24.59#ibcon#first serial, iclass 33, count 2 2006.162.07:39:24.59#ibcon#enter sib2, iclass 33, count 2 2006.162.07:39:24.59#ibcon#flushed, iclass 33, count 2 2006.162.07:39:24.59#ibcon#about to write, iclass 33, count 2 2006.162.07:39:24.59#ibcon#wrote, iclass 33, count 2 2006.162.07:39:24.59#ibcon#about to read 3, iclass 33, count 2 2006.162.07:39:24.61#ibcon#read 3, iclass 33, count 2 2006.162.07:39:24.61#ibcon#about to read 4, iclass 33, count 2 2006.162.07:39:24.61#ibcon#read 4, iclass 33, count 2 2006.162.07:39:24.61#ibcon#about to read 5, iclass 33, count 2 2006.162.07:39:24.61#ibcon#read 5, iclass 33, count 2 2006.162.07:39:24.61#ibcon#about to read 6, iclass 33, count 2 2006.162.07:39:24.61#ibcon#read 6, iclass 33, count 2 2006.162.07:39:24.61#ibcon#end of sib2, iclass 33, count 2 2006.162.07:39:24.61#ibcon#*mode == 0, iclass 33, count 2 2006.162.07:39:24.61#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.162.07:39:24.61#ibcon#[27=AT06-04\r\n] 2006.162.07:39:24.61#ibcon#*before write, iclass 33, count 2 2006.162.07:39:24.61#ibcon#enter sib2, iclass 33, count 2 2006.162.07:39:24.61#ibcon#flushed, iclass 33, count 2 2006.162.07:39:24.61#ibcon#about to write, iclass 33, count 2 2006.162.07:39:24.61#ibcon#wrote, iclass 33, count 2 2006.162.07:39:24.61#ibcon#about to read 3, iclass 33, count 2 2006.162.07:39:24.64#ibcon#read 3, iclass 33, count 2 2006.162.07:39:24.64#ibcon#about to read 4, iclass 33, count 2 2006.162.07:39:24.64#ibcon#read 4, iclass 33, count 2 2006.162.07:39:24.64#ibcon#about to read 5, iclass 33, count 2 2006.162.07:39:24.64#ibcon#read 5, iclass 33, count 2 2006.162.07:39:24.64#ibcon#about to read 6, iclass 33, count 2 2006.162.07:39:24.64#ibcon#read 6, iclass 33, count 2 2006.162.07:39:24.64#ibcon#end of sib2, iclass 33, count 2 2006.162.07:39:24.64#ibcon#*after write, iclass 33, count 2 2006.162.07:39:24.64#ibcon#*before return 0, iclass 33, count 2 2006.162.07:39:24.64#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.162.07:39:24.64#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.162.07:39:24.64#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.162.07:39:24.64#ibcon#ireg 7 cls_cnt 0 2006.162.07:39:24.64#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.162.07:39:24.76#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.162.07:39:24.76#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.162.07:39:24.76#ibcon#enter wrdev, iclass 33, count 0 2006.162.07:39:24.76#ibcon#first serial, iclass 33, count 0 2006.162.07:39:24.76#ibcon#enter sib2, iclass 33, count 0 2006.162.07:39:24.76#ibcon#flushed, iclass 33, count 0 2006.162.07:39:24.76#ibcon#about to write, iclass 33, count 0 2006.162.07:39:24.76#ibcon#wrote, iclass 33, count 0 2006.162.07:39:24.76#ibcon#about to read 3, iclass 33, count 0 2006.162.07:39:24.78#ibcon#read 3, iclass 33, count 0 2006.162.07:39:24.78#ibcon#about to read 4, iclass 33, count 0 2006.162.07:39:24.78#ibcon#read 4, iclass 33, count 0 2006.162.07:39:24.78#ibcon#about to read 5, iclass 33, count 0 2006.162.07:39:24.78#ibcon#read 5, iclass 33, count 0 2006.162.07:39:24.78#ibcon#about to read 6, iclass 33, count 0 2006.162.07:39:24.78#ibcon#read 6, iclass 33, count 0 2006.162.07:39:24.78#ibcon#end of sib2, iclass 33, count 0 2006.162.07:39:24.78#ibcon#*mode == 0, iclass 33, count 0 2006.162.07:39:24.78#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.162.07:39:24.78#ibcon#[27=USB\r\n] 2006.162.07:39:24.78#ibcon#*before write, iclass 33, count 0 2006.162.07:39:24.78#ibcon#enter sib2, iclass 33, count 0 2006.162.07:39:24.78#ibcon#flushed, iclass 33, count 0 2006.162.07:39:24.78#ibcon#about to write, iclass 33, count 0 2006.162.07:39:24.78#ibcon#wrote, iclass 33, count 0 2006.162.07:39:24.78#ibcon#about to read 3, iclass 33, count 0 2006.162.07:39:24.81#ibcon#read 3, iclass 33, count 0 2006.162.07:39:24.81#ibcon#about to read 4, iclass 33, count 0 2006.162.07:39:24.81#ibcon#read 4, iclass 33, count 0 2006.162.07:39:24.81#ibcon#about to read 5, iclass 33, count 0 2006.162.07:39:24.81#ibcon#read 5, iclass 33, count 0 2006.162.07:39:24.81#ibcon#about to read 6, iclass 33, count 0 2006.162.07:39:24.81#ibcon#read 6, iclass 33, count 0 2006.162.07:39:24.81#ibcon#end of sib2, iclass 33, count 0 2006.162.07:39:24.81#ibcon#*after write, iclass 33, count 0 2006.162.07:39:24.81#ibcon#*before return 0, iclass 33, count 0 2006.162.07:39:24.81#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.162.07:39:24.81#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.162.07:39:24.81#ibcon#about to clear, iclass 33 cls_cnt 0 2006.162.07:39:24.81#ibcon#cleared, iclass 33 cls_cnt 0 2006.162.07:39:24.81$vc4f8/vabw=wide 2006.162.07:39:24.81#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.162.07:39:24.81#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.162.07:39:24.81#ibcon#ireg 8 cls_cnt 0 2006.162.07:39:24.81#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.162.07:39:24.81#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.162.07:39:24.81#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.162.07:39:24.81#ibcon#enter wrdev, iclass 35, count 0 2006.162.07:39:24.81#ibcon#first serial, iclass 35, count 0 2006.162.07:39:24.81#ibcon#enter sib2, iclass 35, count 0 2006.162.07:39:24.81#ibcon#flushed, iclass 35, count 0 2006.162.07:39:24.81#ibcon#about to write, iclass 35, count 0 2006.162.07:39:24.81#ibcon#wrote, iclass 35, count 0 2006.162.07:39:24.81#ibcon#about to read 3, iclass 35, count 0 2006.162.07:39:24.83#ibcon#read 3, iclass 35, count 0 2006.162.07:39:24.83#ibcon#about to read 4, iclass 35, count 0 2006.162.07:39:24.83#ibcon#read 4, iclass 35, count 0 2006.162.07:39:24.83#ibcon#about to read 5, iclass 35, count 0 2006.162.07:39:24.83#ibcon#read 5, iclass 35, count 0 2006.162.07:39:24.83#ibcon#about to read 6, iclass 35, count 0 2006.162.07:39:24.83#ibcon#read 6, iclass 35, count 0 2006.162.07:39:24.83#ibcon#end of sib2, iclass 35, count 0 2006.162.07:39:24.83#ibcon#*mode == 0, iclass 35, count 0 2006.162.07:39:24.83#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.162.07:39:24.83#ibcon#[25=BW32\r\n] 2006.162.07:39:24.83#ibcon#*before write, iclass 35, count 0 2006.162.07:39:24.83#ibcon#enter sib2, iclass 35, count 0 2006.162.07:39:24.83#ibcon#flushed, iclass 35, count 0 2006.162.07:39:24.83#ibcon#about to write, iclass 35, count 0 2006.162.07:39:24.83#ibcon#wrote, iclass 35, count 0 2006.162.07:39:24.83#ibcon#about to read 3, iclass 35, count 0 2006.162.07:39:24.86#ibcon#read 3, iclass 35, count 0 2006.162.07:39:24.86#ibcon#about to read 4, iclass 35, count 0 2006.162.07:39:24.86#ibcon#read 4, iclass 35, count 0 2006.162.07:39:24.86#ibcon#about to read 5, iclass 35, count 0 2006.162.07:39:24.86#ibcon#read 5, iclass 35, count 0 2006.162.07:39:24.86#ibcon#about to read 6, iclass 35, count 0 2006.162.07:39:24.86#ibcon#read 6, iclass 35, count 0 2006.162.07:39:24.86#ibcon#end of sib2, iclass 35, count 0 2006.162.07:39:24.86#ibcon#*after write, iclass 35, count 0 2006.162.07:39:24.86#ibcon#*before return 0, iclass 35, count 0 2006.162.07:39:24.86#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.162.07:39:24.86#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.162.07:39:24.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.162.07:39:24.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.162.07:39:24.86$vc4f8/vbbw=wide 2006.162.07:39:24.86#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.162.07:39:24.86#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.162.07:39:24.86#ibcon#ireg 8 cls_cnt 0 2006.162.07:39:24.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.162.07:39:24.93#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.162.07:39:24.93#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.162.07:39:24.93#ibcon#enter wrdev, iclass 37, count 0 2006.162.07:39:24.93#ibcon#first serial, iclass 37, count 0 2006.162.07:39:24.93#ibcon#enter sib2, iclass 37, count 0 2006.162.07:39:24.93#ibcon#flushed, iclass 37, count 0 2006.162.07:39:24.93#ibcon#about to write, iclass 37, count 0 2006.162.07:39:24.93#ibcon#wrote, iclass 37, count 0 2006.162.07:39:24.93#ibcon#about to read 3, iclass 37, count 0 2006.162.07:39:24.95#ibcon#read 3, iclass 37, count 0 2006.162.07:39:24.95#ibcon#about to read 4, iclass 37, count 0 2006.162.07:39:24.95#ibcon#read 4, iclass 37, count 0 2006.162.07:39:24.95#ibcon#about to read 5, iclass 37, count 0 2006.162.07:39:24.95#ibcon#read 5, iclass 37, count 0 2006.162.07:39:24.95#ibcon#about to read 6, iclass 37, count 0 2006.162.07:39:24.95#ibcon#read 6, iclass 37, count 0 2006.162.07:39:24.95#ibcon#end of sib2, iclass 37, count 0 2006.162.07:39:24.95#ibcon#*mode == 0, iclass 37, count 0 2006.162.07:39:24.95#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.162.07:39:24.95#ibcon#[27=BW32\r\n] 2006.162.07:39:24.95#ibcon#*before write, iclass 37, count 0 2006.162.07:39:24.95#ibcon#enter sib2, iclass 37, count 0 2006.162.07:39:24.95#ibcon#flushed, iclass 37, count 0 2006.162.07:39:24.95#ibcon#about to write, iclass 37, count 0 2006.162.07:39:24.95#ibcon#wrote, iclass 37, count 0 2006.162.07:39:24.95#ibcon#about to read 3, iclass 37, count 0 2006.162.07:39:24.98#ibcon#read 3, iclass 37, count 0 2006.162.07:39:24.98#ibcon#about to read 4, iclass 37, count 0 2006.162.07:39:24.98#ibcon#read 4, iclass 37, count 0 2006.162.07:39:24.98#ibcon#about to read 5, iclass 37, count 0 2006.162.07:39:24.98#ibcon#read 5, iclass 37, count 0 2006.162.07:39:24.98#ibcon#about to read 6, iclass 37, count 0 2006.162.07:39:24.98#ibcon#read 6, iclass 37, count 0 2006.162.07:39:24.98#ibcon#end of sib2, iclass 37, count 0 2006.162.07:39:24.98#ibcon#*after write, iclass 37, count 0 2006.162.07:39:24.98#ibcon#*before return 0, iclass 37, count 0 2006.162.07:39:24.98#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.162.07:39:24.98#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.162.07:39:24.98#ibcon#about to clear, iclass 37 cls_cnt 0 2006.162.07:39:24.98#ibcon#cleared, iclass 37 cls_cnt 0 2006.162.07:39:24.98$4f8m12a/ifd4f 2006.162.07:39:24.98$ifd4f/lo= 2006.162.07:39:24.98$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.07:39:24.98$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.07:39:24.98$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.07:39:24.98$ifd4f/patch= 2006.162.07:39:24.98$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.07:39:24.98$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.07:39:24.98$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.07:39:24.98$4f8m12a/"form=m,16.000,1:2 2006.162.07:39:24.98$4f8m12a/"tpicd 2006.162.07:39:24.98$4f8m12a/echo=off 2006.162.07:39:24.98$4f8m12a/xlog=off 2006.162.07:39:24.98:!2006.162.07:39:50 2006.162.07:39:35.14#trakl#Source acquired 2006.162.07:39:35.14#flagr#flagr/antenna,acquired 2006.162.07:39:50.00:preob 2006.162.07:39:51.14/onsource/TRACKING 2006.162.07:39:51.14:!2006.162.07:40:00 2006.162.07:40:00.00:data_valid=on 2006.162.07:40:00.00:midob 2006.162.07:40:00.14/onsource/TRACKING 2006.162.07:40:00.14/wx/17.91,1007.3,100 2006.162.07:40:00.21/cable/+6.5351E-03 2006.162.07:40:01.30/va/01,08,usb,yes,45,47 2006.162.07:40:01.30/va/02,07,usb,yes,46,48 2006.162.07:40:01.30/va/03,06,usb,yes,48,49 2006.162.07:40:01.30/va/04,07,usb,yes,47,50 2006.162.07:40:01.30/va/05,07,usb,yes,50,53 2006.162.07:40:01.30/va/06,06,usb,yes,50,49 2006.162.07:40:01.30/va/07,06,usb,yes,50,50 2006.162.07:40:01.30/va/08,07,usb,yes,48,47 2006.162.07:40:01.53/valo/01,532.99,yes,locked 2006.162.07:40:01.53/valo/02,572.99,yes,locked 2006.162.07:40:01.53/valo/03,672.99,yes,locked 2006.162.07:40:01.53/valo/04,832.99,yes,locked 2006.162.07:40:01.53/valo/05,652.99,yes,locked 2006.162.07:40:01.53/valo/06,772.99,yes,locked 2006.162.07:40:01.53/valo/07,832.99,yes,locked 2006.162.07:40:01.53/valo/08,852.99,yes,locked 2006.162.07:40:02.62/vb/01,04,usb,yes,32,31 2006.162.07:40:02.62/vb/02,04,usb,yes,34,35 2006.162.07:40:02.62/vb/03,04,usb,yes,30,34 2006.162.07:40:02.62/vb/04,04,usb,yes,31,32 2006.162.07:40:02.62/vb/05,04,usb,yes,30,34 2006.162.07:40:02.62/vb/06,04,usb,yes,31,34 2006.162.07:40:02.62/vb/07,04,usb,yes,33,33 2006.162.07:40:02.62/vb/08,04,usb,yes,30,34 2006.162.07:40:02.86/vblo/01,632.99,yes,locked 2006.162.07:40:02.86/vblo/02,640.99,yes,locked 2006.162.07:40:02.86/vblo/03,656.99,yes,locked 2006.162.07:40:02.86/vblo/04,712.99,yes,locked 2006.162.07:40:02.86/vblo/05,744.99,yes,locked 2006.162.07:40:02.86/vblo/06,752.99,yes,locked 2006.162.07:40:02.86/vblo/07,734.99,yes,locked 2006.162.07:40:02.86/vblo/08,744.99,yes,locked 2006.162.07:40:03.01/vabw/8 2006.162.07:40:03.16/vbbw/8 2006.162.07:40:03.25/xfe/off,on,15.0 2006.162.07:40:03.62/ifatt/23,28,28,28 2006.162.07:40:04.08/fmout-gps/S +4.49E-07 2006.162.07:40:04.12:!2006.162.07:41:00 2006.162.07:41:00.01:data_valid=off 2006.162.07:41:00.01:postob 2006.162.07:41:00.09/cable/+6.5342E-03 2006.162.07:41:00.09/wx/17.93,1007.2,100 2006.162.07:41:01.08/fmout-gps/S +4.48E-07 2006.162.07:41:01.08:scan_name=162-0741,k06162,70 2006.162.07:41:01.09:source=1053+815,105811.54,811432.7,2000.0,neutral 2006.162.07:41:01.14#flagr#flagr/antenna,new-source 2006.162.07:41:02.13:checkk5 2006.162.07:41:02.69/chk_autoobs//k5ts1/ autoobs is running! 2006.162.07:41:03.11/chk_autoobs//k5ts2/ autoobs is running! 2006.162.07:41:03.55/chk_autoobs//k5ts3/ autoobs is running! 2006.162.07:41:03.97/chk_autoobs//k5ts4/ autoobs is running! 2006.162.07:41:04.78/chk_obsdata//k5ts1/T1620740??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:41:05.20/chk_obsdata//k5ts2/T1620740??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:41:05.71/chk_obsdata//k5ts3/T1620740??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:41:06.16/chk_obsdata//k5ts4/T1620740??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:41:07.27/k5log//k5ts1_log_newline 2006.162.07:41:08.07/k5log//k5ts2_log_newline 2006.162.07:41:08.82/k5log//k5ts3_log_newline 2006.162.07:41:09.58/k5log//k5ts4_log_newline 2006.162.07:41:09.61/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.07:41:09.61:4f8m12a=1 2006.162.07:41:09.61$4f8m12a/echo=on 2006.162.07:41:09.61$4f8m12a/pcalon 2006.162.07:41:09.61$pcalon/"no phase cal control is implemented here 2006.162.07:41:09.61$4f8m12a/"tpicd=stop 2006.162.07:41:09.61$4f8m12a/vc4f8 2006.162.07:41:09.61$vc4f8/valo=1,532.99 2006.162.07:41:09.62#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.162.07:41:09.62#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.162.07:41:09.62#ibcon#ireg 17 cls_cnt 0 2006.162.07:41:09.62#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:41:09.62#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:41:09.62#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:41:09.62#ibcon#enter wrdev, iclass 12, count 0 2006.162.07:41:09.62#ibcon#first serial, iclass 12, count 0 2006.162.07:41:09.62#ibcon#enter sib2, iclass 12, count 0 2006.162.07:41:09.62#ibcon#flushed, iclass 12, count 0 2006.162.07:41:09.62#ibcon#about to write, iclass 12, count 0 2006.162.07:41:09.62#ibcon#wrote, iclass 12, count 0 2006.162.07:41:09.62#ibcon#about to read 3, iclass 12, count 0 2006.162.07:41:09.65#ibcon#read 3, iclass 12, count 0 2006.162.07:41:09.66#ibcon#about to read 4, iclass 12, count 0 2006.162.07:41:09.66#ibcon#read 4, iclass 12, count 0 2006.162.07:41:09.66#ibcon#about to read 5, iclass 12, count 0 2006.162.07:41:09.66#ibcon#read 5, iclass 12, count 0 2006.162.07:41:09.66#ibcon#about to read 6, iclass 12, count 0 2006.162.07:41:09.66#ibcon#read 6, iclass 12, count 0 2006.162.07:41:09.66#ibcon#end of sib2, iclass 12, count 0 2006.162.07:41:09.66#ibcon#*mode == 0, iclass 12, count 0 2006.162.07:41:09.66#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.162.07:41:09.66#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.07:41:09.66#ibcon#*before write, iclass 12, count 0 2006.162.07:41:09.66#ibcon#enter sib2, iclass 12, count 0 2006.162.07:41:09.66#ibcon#flushed, iclass 12, count 0 2006.162.07:41:09.66#ibcon#about to write, iclass 12, count 0 2006.162.07:41:09.66#ibcon#wrote, iclass 12, count 0 2006.162.07:41:09.66#ibcon#about to read 3, iclass 12, count 0 2006.162.07:41:09.70#ibcon#read 3, iclass 12, count 0 2006.162.07:41:09.70#ibcon#about to read 4, iclass 12, count 0 2006.162.07:41:09.70#ibcon#read 4, iclass 12, count 0 2006.162.07:41:09.70#ibcon#about to read 5, iclass 12, count 0 2006.162.07:41:09.70#ibcon#read 5, iclass 12, count 0 2006.162.07:41:09.70#ibcon#about to read 6, iclass 12, count 0 2006.162.07:41:09.70#ibcon#read 6, iclass 12, count 0 2006.162.07:41:09.70#ibcon#end of sib2, iclass 12, count 0 2006.162.07:41:09.70#ibcon#*after write, iclass 12, count 0 2006.162.07:41:09.70#ibcon#*before return 0, iclass 12, count 0 2006.162.07:41:09.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:41:09.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:41:09.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.162.07:41:09.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.162.07:41:09.70$vc4f8/va=1,8 2006.162.07:41:09.70#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.162.07:41:09.70#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.162.07:41:09.70#ibcon#ireg 11 cls_cnt 2 2006.162.07:41:09.70#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:41:09.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:41:09.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:41:09.70#ibcon#enter wrdev, iclass 14, count 2 2006.162.07:41:09.70#ibcon#first serial, iclass 14, count 2 2006.162.07:41:09.70#ibcon#enter sib2, iclass 14, count 2 2006.162.07:41:09.70#ibcon#flushed, iclass 14, count 2 2006.162.07:41:09.70#ibcon#about to write, iclass 14, count 2 2006.162.07:41:09.70#ibcon#wrote, iclass 14, count 2 2006.162.07:41:09.70#ibcon#about to read 3, iclass 14, count 2 2006.162.07:41:09.72#ibcon#read 3, iclass 14, count 2 2006.162.07:41:09.72#ibcon#about to read 4, iclass 14, count 2 2006.162.07:41:09.72#ibcon#read 4, iclass 14, count 2 2006.162.07:41:09.72#ibcon#about to read 5, iclass 14, count 2 2006.162.07:41:09.72#ibcon#read 5, iclass 14, count 2 2006.162.07:41:09.72#ibcon#about to read 6, iclass 14, count 2 2006.162.07:41:09.72#ibcon#read 6, iclass 14, count 2 2006.162.07:41:09.72#ibcon#end of sib2, iclass 14, count 2 2006.162.07:41:09.72#ibcon#*mode == 0, iclass 14, count 2 2006.162.07:41:09.72#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.162.07:41:09.72#ibcon#[25=AT01-08\r\n] 2006.162.07:41:09.72#ibcon#*before write, iclass 14, count 2 2006.162.07:41:09.72#ibcon#enter sib2, iclass 14, count 2 2006.162.07:41:09.72#ibcon#flushed, iclass 14, count 2 2006.162.07:41:09.72#ibcon#about to write, iclass 14, count 2 2006.162.07:41:09.72#ibcon#wrote, iclass 14, count 2 2006.162.07:41:09.72#ibcon#about to read 3, iclass 14, count 2 2006.162.07:41:09.75#ibcon#read 3, iclass 14, count 2 2006.162.07:41:09.75#ibcon#about to read 4, iclass 14, count 2 2006.162.07:41:09.75#ibcon#read 4, iclass 14, count 2 2006.162.07:41:09.75#ibcon#about to read 5, iclass 14, count 2 2006.162.07:41:09.75#ibcon#read 5, iclass 14, count 2 2006.162.07:41:09.75#ibcon#about to read 6, iclass 14, count 2 2006.162.07:41:09.75#ibcon#read 6, iclass 14, count 2 2006.162.07:41:09.75#ibcon#end of sib2, iclass 14, count 2 2006.162.07:41:09.75#ibcon#*after write, iclass 14, count 2 2006.162.07:41:09.75#ibcon#*before return 0, iclass 14, count 2 2006.162.07:41:09.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:41:09.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:41:09.75#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.162.07:41:09.75#ibcon#ireg 7 cls_cnt 0 2006.162.07:41:09.75#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:41:09.87#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:41:09.87#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:41:09.87#ibcon#enter wrdev, iclass 14, count 0 2006.162.07:41:09.87#ibcon#first serial, iclass 14, count 0 2006.162.07:41:09.87#ibcon#enter sib2, iclass 14, count 0 2006.162.07:41:09.87#ibcon#flushed, iclass 14, count 0 2006.162.07:41:09.87#ibcon#about to write, iclass 14, count 0 2006.162.07:41:09.87#ibcon#wrote, iclass 14, count 0 2006.162.07:41:09.87#ibcon#about to read 3, iclass 14, count 0 2006.162.07:41:09.89#ibcon#read 3, iclass 14, count 0 2006.162.07:41:09.89#ibcon#about to read 4, iclass 14, count 0 2006.162.07:41:09.89#ibcon#read 4, iclass 14, count 0 2006.162.07:41:09.89#ibcon#about to read 5, iclass 14, count 0 2006.162.07:41:09.89#ibcon#read 5, iclass 14, count 0 2006.162.07:41:09.89#ibcon#about to read 6, iclass 14, count 0 2006.162.07:41:09.89#ibcon#read 6, iclass 14, count 0 2006.162.07:41:09.89#ibcon#end of sib2, iclass 14, count 0 2006.162.07:41:09.89#ibcon#*mode == 0, iclass 14, count 0 2006.162.07:41:09.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.07:41:09.89#ibcon#[25=USB\r\n] 2006.162.07:41:09.89#ibcon#*before write, iclass 14, count 0 2006.162.07:41:09.89#ibcon#enter sib2, iclass 14, count 0 2006.162.07:41:09.89#ibcon#flushed, iclass 14, count 0 2006.162.07:41:09.89#ibcon#about to write, iclass 14, count 0 2006.162.07:41:09.89#ibcon#wrote, iclass 14, count 0 2006.162.07:41:09.89#ibcon#about to read 3, iclass 14, count 0 2006.162.07:41:09.92#ibcon#read 3, iclass 14, count 0 2006.162.07:41:09.92#ibcon#about to read 4, iclass 14, count 0 2006.162.07:41:09.92#ibcon#read 4, iclass 14, count 0 2006.162.07:41:09.92#ibcon#about to read 5, iclass 14, count 0 2006.162.07:41:09.92#ibcon#read 5, iclass 14, count 0 2006.162.07:41:09.92#ibcon#about to read 6, iclass 14, count 0 2006.162.07:41:09.92#ibcon#read 6, iclass 14, count 0 2006.162.07:41:09.92#ibcon#end of sib2, iclass 14, count 0 2006.162.07:41:09.92#ibcon#*after write, iclass 14, count 0 2006.162.07:41:09.92#ibcon#*before return 0, iclass 14, count 0 2006.162.07:41:09.92#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:41:09.92#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:41:09.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.07:41:09.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.07:41:09.92$vc4f8/valo=2,572.99 2006.162.07:41:09.92#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.162.07:41:09.92#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.162.07:41:09.92#ibcon#ireg 17 cls_cnt 0 2006.162.07:41:09.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:41:09.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:41:09.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:41:09.92#ibcon#enter wrdev, iclass 16, count 0 2006.162.07:41:09.92#ibcon#first serial, iclass 16, count 0 2006.162.07:41:09.92#ibcon#enter sib2, iclass 16, count 0 2006.162.07:41:09.92#ibcon#flushed, iclass 16, count 0 2006.162.07:41:09.92#ibcon#about to write, iclass 16, count 0 2006.162.07:41:09.92#ibcon#wrote, iclass 16, count 0 2006.162.07:41:09.92#ibcon#about to read 3, iclass 16, count 0 2006.162.07:41:09.94#ibcon#read 3, iclass 16, count 0 2006.162.07:41:09.94#ibcon#about to read 4, iclass 16, count 0 2006.162.07:41:09.94#ibcon#read 4, iclass 16, count 0 2006.162.07:41:09.94#ibcon#about to read 5, iclass 16, count 0 2006.162.07:41:09.94#ibcon#read 5, iclass 16, count 0 2006.162.07:41:09.94#ibcon#about to read 6, iclass 16, count 0 2006.162.07:41:09.94#ibcon#read 6, iclass 16, count 0 2006.162.07:41:09.94#ibcon#end of sib2, iclass 16, count 0 2006.162.07:41:09.94#ibcon#*mode == 0, iclass 16, count 0 2006.162.07:41:09.94#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.162.07:41:09.94#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.07:41:09.94#ibcon#*before write, iclass 16, count 0 2006.162.07:41:09.94#ibcon#enter sib2, iclass 16, count 0 2006.162.07:41:09.94#ibcon#flushed, iclass 16, count 0 2006.162.07:41:09.94#ibcon#about to write, iclass 16, count 0 2006.162.07:41:09.94#ibcon#wrote, iclass 16, count 0 2006.162.07:41:09.94#ibcon#about to read 3, iclass 16, count 0 2006.162.07:41:09.98#ibcon#read 3, iclass 16, count 0 2006.162.07:41:09.98#ibcon#about to read 4, iclass 16, count 0 2006.162.07:41:09.98#ibcon#read 4, iclass 16, count 0 2006.162.07:41:09.98#ibcon#about to read 5, iclass 16, count 0 2006.162.07:41:09.98#ibcon#read 5, iclass 16, count 0 2006.162.07:41:09.98#ibcon#about to read 6, iclass 16, count 0 2006.162.07:41:09.98#ibcon#read 6, iclass 16, count 0 2006.162.07:41:09.98#ibcon#end of sib2, iclass 16, count 0 2006.162.07:41:09.98#ibcon#*after write, iclass 16, count 0 2006.162.07:41:09.98#ibcon#*before return 0, iclass 16, count 0 2006.162.07:41:09.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:41:09.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:41:09.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.162.07:41:09.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.162.07:41:09.98$vc4f8/va=2,7 2006.162.07:41:09.98#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.162.07:41:09.98#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.162.07:41:09.98#ibcon#ireg 11 cls_cnt 2 2006.162.07:41:09.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:41:10.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:41:10.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:41:10.04#ibcon#enter wrdev, iclass 18, count 2 2006.162.07:41:10.04#ibcon#first serial, iclass 18, count 2 2006.162.07:41:10.04#ibcon#enter sib2, iclass 18, count 2 2006.162.07:41:10.04#ibcon#flushed, iclass 18, count 2 2006.162.07:41:10.04#ibcon#about to write, iclass 18, count 2 2006.162.07:41:10.04#ibcon#wrote, iclass 18, count 2 2006.162.07:41:10.04#ibcon#about to read 3, iclass 18, count 2 2006.162.07:41:10.07#ibcon#read 3, iclass 18, count 2 2006.162.07:41:10.07#ibcon#about to read 4, iclass 18, count 2 2006.162.07:41:10.07#ibcon#read 4, iclass 18, count 2 2006.162.07:41:10.07#ibcon#about to read 5, iclass 18, count 2 2006.162.07:41:10.07#ibcon#read 5, iclass 18, count 2 2006.162.07:41:10.07#ibcon#about to read 6, iclass 18, count 2 2006.162.07:41:10.07#ibcon#read 6, iclass 18, count 2 2006.162.07:41:10.07#ibcon#end of sib2, iclass 18, count 2 2006.162.07:41:10.07#ibcon#*mode == 0, iclass 18, count 2 2006.162.07:41:10.07#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.162.07:41:10.07#ibcon#[25=AT02-07\r\n] 2006.162.07:41:10.07#ibcon#*before write, iclass 18, count 2 2006.162.07:41:10.07#ibcon#enter sib2, iclass 18, count 2 2006.162.07:41:10.07#ibcon#flushed, iclass 18, count 2 2006.162.07:41:10.07#ibcon#about to write, iclass 18, count 2 2006.162.07:41:10.07#ibcon#wrote, iclass 18, count 2 2006.162.07:41:10.07#ibcon#about to read 3, iclass 18, count 2 2006.162.07:41:10.10#ibcon#read 3, iclass 18, count 2 2006.162.07:41:10.10#ibcon#about to read 4, iclass 18, count 2 2006.162.07:41:10.10#ibcon#read 4, iclass 18, count 2 2006.162.07:41:10.10#ibcon#about to read 5, iclass 18, count 2 2006.162.07:41:10.10#ibcon#read 5, iclass 18, count 2 2006.162.07:41:10.10#ibcon#about to read 6, iclass 18, count 2 2006.162.07:41:10.10#ibcon#read 6, iclass 18, count 2 2006.162.07:41:10.10#ibcon#end of sib2, iclass 18, count 2 2006.162.07:41:10.10#ibcon#*after write, iclass 18, count 2 2006.162.07:41:10.10#ibcon#*before return 0, iclass 18, count 2 2006.162.07:41:10.10#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:41:10.10#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:41:10.10#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.162.07:41:10.10#ibcon#ireg 7 cls_cnt 0 2006.162.07:41:10.10#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:41:10.22#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:41:10.22#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:41:10.22#ibcon#enter wrdev, iclass 18, count 0 2006.162.07:41:10.22#ibcon#first serial, iclass 18, count 0 2006.162.07:41:10.22#ibcon#enter sib2, iclass 18, count 0 2006.162.07:41:10.22#ibcon#flushed, iclass 18, count 0 2006.162.07:41:10.22#ibcon#about to write, iclass 18, count 0 2006.162.07:41:10.22#ibcon#wrote, iclass 18, count 0 2006.162.07:41:10.22#ibcon#about to read 3, iclass 18, count 0 2006.162.07:41:10.24#ibcon#read 3, iclass 18, count 0 2006.162.07:41:10.24#ibcon#about to read 4, iclass 18, count 0 2006.162.07:41:10.24#ibcon#read 4, iclass 18, count 0 2006.162.07:41:10.24#ibcon#about to read 5, iclass 18, count 0 2006.162.07:41:10.24#ibcon#read 5, iclass 18, count 0 2006.162.07:41:10.24#ibcon#about to read 6, iclass 18, count 0 2006.162.07:41:10.24#ibcon#read 6, iclass 18, count 0 2006.162.07:41:10.24#ibcon#end of sib2, iclass 18, count 0 2006.162.07:41:10.24#ibcon#*mode == 0, iclass 18, count 0 2006.162.07:41:10.24#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.162.07:41:10.24#ibcon#[25=USB\r\n] 2006.162.07:41:10.24#ibcon#*before write, iclass 18, count 0 2006.162.07:41:10.24#ibcon#enter sib2, iclass 18, count 0 2006.162.07:41:10.24#ibcon#flushed, iclass 18, count 0 2006.162.07:41:10.24#ibcon#about to write, iclass 18, count 0 2006.162.07:41:10.24#ibcon#wrote, iclass 18, count 0 2006.162.07:41:10.24#ibcon#about to read 3, iclass 18, count 0 2006.162.07:41:10.27#ibcon#read 3, iclass 18, count 0 2006.162.07:41:10.27#ibcon#about to read 4, iclass 18, count 0 2006.162.07:41:10.27#ibcon#read 4, iclass 18, count 0 2006.162.07:41:10.27#ibcon#about to read 5, iclass 18, count 0 2006.162.07:41:10.27#ibcon#read 5, iclass 18, count 0 2006.162.07:41:10.27#ibcon#about to read 6, iclass 18, count 0 2006.162.07:41:10.27#ibcon#read 6, iclass 18, count 0 2006.162.07:41:10.27#ibcon#end of sib2, iclass 18, count 0 2006.162.07:41:10.27#ibcon#*after write, iclass 18, count 0 2006.162.07:41:10.27#ibcon#*before return 0, iclass 18, count 0 2006.162.07:41:10.27#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:41:10.27#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:41:10.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.162.07:41:10.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.162.07:41:10.27$vc4f8/valo=3,672.99 2006.162.07:41:10.27#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.162.07:41:10.27#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.162.07:41:10.27#ibcon#ireg 17 cls_cnt 0 2006.162.07:41:10.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:41:10.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:41:10.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:41:10.27#ibcon#enter wrdev, iclass 20, count 0 2006.162.07:41:10.27#ibcon#first serial, iclass 20, count 0 2006.162.07:41:10.27#ibcon#enter sib2, iclass 20, count 0 2006.162.07:41:10.27#ibcon#flushed, iclass 20, count 0 2006.162.07:41:10.27#ibcon#about to write, iclass 20, count 0 2006.162.07:41:10.27#ibcon#wrote, iclass 20, count 0 2006.162.07:41:10.27#ibcon#about to read 3, iclass 20, count 0 2006.162.07:41:10.29#ibcon#read 3, iclass 20, count 0 2006.162.07:41:10.29#ibcon#about to read 4, iclass 20, count 0 2006.162.07:41:10.29#ibcon#read 4, iclass 20, count 0 2006.162.07:41:10.29#ibcon#about to read 5, iclass 20, count 0 2006.162.07:41:10.29#ibcon#read 5, iclass 20, count 0 2006.162.07:41:10.29#ibcon#about to read 6, iclass 20, count 0 2006.162.07:41:10.29#ibcon#read 6, iclass 20, count 0 2006.162.07:41:10.29#ibcon#end of sib2, iclass 20, count 0 2006.162.07:41:10.29#ibcon#*mode == 0, iclass 20, count 0 2006.162.07:41:10.29#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.07:41:10.29#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.07:41:10.29#ibcon#*before write, iclass 20, count 0 2006.162.07:41:10.29#ibcon#enter sib2, iclass 20, count 0 2006.162.07:41:10.29#ibcon#flushed, iclass 20, count 0 2006.162.07:41:10.29#ibcon#about to write, iclass 20, count 0 2006.162.07:41:10.29#ibcon#wrote, iclass 20, count 0 2006.162.07:41:10.29#ibcon#about to read 3, iclass 20, count 0 2006.162.07:41:10.33#ibcon#read 3, iclass 20, count 0 2006.162.07:41:10.33#ibcon#about to read 4, iclass 20, count 0 2006.162.07:41:10.33#ibcon#read 4, iclass 20, count 0 2006.162.07:41:10.33#ibcon#about to read 5, iclass 20, count 0 2006.162.07:41:10.33#ibcon#read 5, iclass 20, count 0 2006.162.07:41:10.33#ibcon#about to read 6, iclass 20, count 0 2006.162.07:41:10.33#ibcon#read 6, iclass 20, count 0 2006.162.07:41:10.33#ibcon#end of sib2, iclass 20, count 0 2006.162.07:41:10.33#ibcon#*after write, iclass 20, count 0 2006.162.07:41:10.33#ibcon#*before return 0, iclass 20, count 0 2006.162.07:41:10.33#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:41:10.33#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:41:10.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.07:41:10.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.07:41:10.33$vc4f8/va=3,6 2006.162.07:41:10.33#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.162.07:41:10.33#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.162.07:41:10.33#ibcon#ireg 11 cls_cnt 2 2006.162.07:41:10.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:41:10.39#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:41:10.39#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:41:10.39#ibcon#enter wrdev, iclass 22, count 2 2006.162.07:41:10.39#ibcon#first serial, iclass 22, count 2 2006.162.07:41:10.39#ibcon#enter sib2, iclass 22, count 2 2006.162.07:41:10.39#ibcon#flushed, iclass 22, count 2 2006.162.07:41:10.39#ibcon#about to write, iclass 22, count 2 2006.162.07:41:10.39#ibcon#wrote, iclass 22, count 2 2006.162.07:41:10.39#ibcon#about to read 3, iclass 22, count 2 2006.162.07:41:10.41#ibcon#read 3, iclass 22, count 2 2006.162.07:41:10.41#ibcon#about to read 4, iclass 22, count 2 2006.162.07:41:10.41#ibcon#read 4, iclass 22, count 2 2006.162.07:41:10.41#ibcon#about to read 5, iclass 22, count 2 2006.162.07:41:10.41#ibcon#read 5, iclass 22, count 2 2006.162.07:41:10.41#ibcon#about to read 6, iclass 22, count 2 2006.162.07:41:10.41#ibcon#read 6, iclass 22, count 2 2006.162.07:41:10.41#ibcon#end of sib2, iclass 22, count 2 2006.162.07:41:10.41#ibcon#*mode == 0, iclass 22, count 2 2006.162.07:41:10.41#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.162.07:41:10.41#ibcon#[25=AT03-06\r\n] 2006.162.07:41:10.41#ibcon#*before write, iclass 22, count 2 2006.162.07:41:10.41#ibcon#enter sib2, iclass 22, count 2 2006.162.07:41:10.41#ibcon#flushed, iclass 22, count 2 2006.162.07:41:10.41#ibcon#about to write, iclass 22, count 2 2006.162.07:41:10.41#ibcon#wrote, iclass 22, count 2 2006.162.07:41:10.41#ibcon#about to read 3, iclass 22, count 2 2006.162.07:41:10.44#ibcon#read 3, iclass 22, count 2 2006.162.07:41:10.44#ibcon#about to read 4, iclass 22, count 2 2006.162.07:41:10.44#ibcon#read 4, iclass 22, count 2 2006.162.07:41:10.44#ibcon#about to read 5, iclass 22, count 2 2006.162.07:41:10.44#ibcon#read 5, iclass 22, count 2 2006.162.07:41:10.44#ibcon#about to read 6, iclass 22, count 2 2006.162.07:41:10.44#ibcon#read 6, iclass 22, count 2 2006.162.07:41:10.44#ibcon#end of sib2, iclass 22, count 2 2006.162.07:41:10.44#ibcon#*after write, iclass 22, count 2 2006.162.07:41:10.44#ibcon#*before return 0, iclass 22, count 2 2006.162.07:41:10.44#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:41:10.44#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:41:10.44#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.162.07:41:10.44#ibcon#ireg 7 cls_cnt 0 2006.162.07:41:10.44#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:41:10.56#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:41:10.56#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:41:10.56#ibcon#enter wrdev, iclass 22, count 0 2006.162.07:41:10.56#ibcon#first serial, iclass 22, count 0 2006.162.07:41:10.56#ibcon#enter sib2, iclass 22, count 0 2006.162.07:41:10.56#ibcon#flushed, iclass 22, count 0 2006.162.07:41:10.56#ibcon#about to write, iclass 22, count 0 2006.162.07:41:10.56#ibcon#wrote, iclass 22, count 0 2006.162.07:41:10.56#ibcon#about to read 3, iclass 22, count 0 2006.162.07:41:10.58#ibcon#read 3, iclass 22, count 0 2006.162.07:41:10.58#ibcon#about to read 4, iclass 22, count 0 2006.162.07:41:10.58#ibcon#read 4, iclass 22, count 0 2006.162.07:41:10.58#ibcon#about to read 5, iclass 22, count 0 2006.162.07:41:10.58#ibcon#read 5, iclass 22, count 0 2006.162.07:41:10.58#ibcon#about to read 6, iclass 22, count 0 2006.162.07:41:10.58#ibcon#read 6, iclass 22, count 0 2006.162.07:41:10.58#ibcon#end of sib2, iclass 22, count 0 2006.162.07:41:10.58#ibcon#*mode == 0, iclass 22, count 0 2006.162.07:41:10.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.07:41:10.58#ibcon#[25=USB\r\n] 2006.162.07:41:10.58#ibcon#*before write, iclass 22, count 0 2006.162.07:41:10.58#ibcon#enter sib2, iclass 22, count 0 2006.162.07:41:10.58#ibcon#flushed, iclass 22, count 0 2006.162.07:41:10.58#ibcon#about to write, iclass 22, count 0 2006.162.07:41:10.58#ibcon#wrote, iclass 22, count 0 2006.162.07:41:10.58#ibcon#about to read 3, iclass 22, count 0 2006.162.07:41:10.61#ibcon#read 3, iclass 22, count 0 2006.162.07:41:10.61#ibcon#about to read 4, iclass 22, count 0 2006.162.07:41:10.61#ibcon#read 4, iclass 22, count 0 2006.162.07:41:10.61#ibcon#about to read 5, iclass 22, count 0 2006.162.07:41:10.61#ibcon#read 5, iclass 22, count 0 2006.162.07:41:10.61#ibcon#about to read 6, iclass 22, count 0 2006.162.07:41:10.61#ibcon#read 6, iclass 22, count 0 2006.162.07:41:10.61#ibcon#end of sib2, iclass 22, count 0 2006.162.07:41:10.61#ibcon#*after write, iclass 22, count 0 2006.162.07:41:10.61#ibcon#*before return 0, iclass 22, count 0 2006.162.07:41:10.61#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:41:10.61#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:41:10.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.07:41:10.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.07:41:10.61$vc4f8/valo=4,832.99 2006.162.07:41:10.61#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.162.07:41:10.61#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.162.07:41:10.61#ibcon#ireg 17 cls_cnt 0 2006.162.07:41:10.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:41:10.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:41:10.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:41:10.61#ibcon#enter wrdev, iclass 24, count 0 2006.162.07:41:10.61#ibcon#first serial, iclass 24, count 0 2006.162.07:41:10.61#ibcon#enter sib2, iclass 24, count 0 2006.162.07:41:10.61#ibcon#flushed, iclass 24, count 0 2006.162.07:41:10.61#ibcon#about to write, iclass 24, count 0 2006.162.07:41:10.61#ibcon#wrote, iclass 24, count 0 2006.162.07:41:10.61#ibcon#about to read 3, iclass 24, count 0 2006.162.07:41:10.63#ibcon#read 3, iclass 24, count 0 2006.162.07:41:10.63#ibcon#about to read 4, iclass 24, count 0 2006.162.07:41:10.63#ibcon#read 4, iclass 24, count 0 2006.162.07:41:10.63#ibcon#about to read 5, iclass 24, count 0 2006.162.07:41:10.63#ibcon#read 5, iclass 24, count 0 2006.162.07:41:10.63#ibcon#about to read 6, iclass 24, count 0 2006.162.07:41:10.63#ibcon#read 6, iclass 24, count 0 2006.162.07:41:10.63#ibcon#end of sib2, iclass 24, count 0 2006.162.07:41:10.63#ibcon#*mode == 0, iclass 24, count 0 2006.162.07:41:10.63#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.07:41:10.63#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.07:41:10.63#ibcon#*before write, iclass 24, count 0 2006.162.07:41:10.63#ibcon#enter sib2, iclass 24, count 0 2006.162.07:41:10.63#ibcon#flushed, iclass 24, count 0 2006.162.07:41:10.63#ibcon#about to write, iclass 24, count 0 2006.162.07:41:10.63#ibcon#wrote, iclass 24, count 0 2006.162.07:41:10.63#ibcon#about to read 3, iclass 24, count 0 2006.162.07:41:10.67#ibcon#read 3, iclass 24, count 0 2006.162.07:41:10.67#ibcon#about to read 4, iclass 24, count 0 2006.162.07:41:10.67#ibcon#read 4, iclass 24, count 0 2006.162.07:41:10.67#ibcon#about to read 5, iclass 24, count 0 2006.162.07:41:10.67#ibcon#read 5, iclass 24, count 0 2006.162.07:41:10.67#ibcon#about to read 6, iclass 24, count 0 2006.162.07:41:10.67#ibcon#read 6, iclass 24, count 0 2006.162.07:41:10.67#ibcon#end of sib2, iclass 24, count 0 2006.162.07:41:10.67#ibcon#*after write, iclass 24, count 0 2006.162.07:41:10.67#ibcon#*before return 0, iclass 24, count 0 2006.162.07:41:10.67#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:41:10.67#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:41:10.67#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.07:41:10.67#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.07:41:10.67$vc4f8/va=4,7 2006.162.07:41:10.67#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.162.07:41:10.67#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.162.07:41:10.67#ibcon#ireg 11 cls_cnt 2 2006.162.07:41:10.67#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:41:10.73#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:41:10.73#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:41:10.73#ibcon#enter wrdev, iclass 26, count 2 2006.162.07:41:10.73#ibcon#first serial, iclass 26, count 2 2006.162.07:41:10.73#ibcon#enter sib2, iclass 26, count 2 2006.162.07:41:10.73#ibcon#flushed, iclass 26, count 2 2006.162.07:41:10.73#ibcon#about to write, iclass 26, count 2 2006.162.07:41:10.73#ibcon#wrote, iclass 26, count 2 2006.162.07:41:10.73#ibcon#about to read 3, iclass 26, count 2 2006.162.07:41:10.75#ibcon#read 3, iclass 26, count 2 2006.162.07:41:10.75#ibcon#about to read 4, iclass 26, count 2 2006.162.07:41:10.75#ibcon#read 4, iclass 26, count 2 2006.162.07:41:10.75#ibcon#about to read 5, iclass 26, count 2 2006.162.07:41:10.75#ibcon#read 5, iclass 26, count 2 2006.162.07:41:10.75#ibcon#about to read 6, iclass 26, count 2 2006.162.07:41:10.75#ibcon#read 6, iclass 26, count 2 2006.162.07:41:10.75#ibcon#end of sib2, iclass 26, count 2 2006.162.07:41:10.75#ibcon#*mode == 0, iclass 26, count 2 2006.162.07:41:10.75#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.162.07:41:10.75#ibcon#[25=AT04-07\r\n] 2006.162.07:41:10.75#ibcon#*before write, iclass 26, count 2 2006.162.07:41:10.75#ibcon#enter sib2, iclass 26, count 2 2006.162.07:41:10.75#ibcon#flushed, iclass 26, count 2 2006.162.07:41:10.75#ibcon#about to write, iclass 26, count 2 2006.162.07:41:10.75#ibcon#wrote, iclass 26, count 2 2006.162.07:41:10.75#ibcon#about to read 3, iclass 26, count 2 2006.162.07:41:10.78#ibcon#read 3, iclass 26, count 2 2006.162.07:41:10.78#ibcon#about to read 4, iclass 26, count 2 2006.162.07:41:10.78#ibcon#read 4, iclass 26, count 2 2006.162.07:41:10.78#ibcon#about to read 5, iclass 26, count 2 2006.162.07:41:10.78#ibcon#read 5, iclass 26, count 2 2006.162.07:41:10.78#ibcon#about to read 6, iclass 26, count 2 2006.162.07:41:10.78#ibcon#read 6, iclass 26, count 2 2006.162.07:41:10.78#ibcon#end of sib2, iclass 26, count 2 2006.162.07:41:10.78#ibcon#*after write, iclass 26, count 2 2006.162.07:41:10.78#ibcon#*before return 0, iclass 26, count 2 2006.162.07:41:10.78#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:41:10.78#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:41:10.78#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.162.07:41:10.78#ibcon#ireg 7 cls_cnt 0 2006.162.07:41:10.78#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:41:10.90#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:41:10.90#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:41:10.90#ibcon#enter wrdev, iclass 26, count 0 2006.162.07:41:10.90#ibcon#first serial, iclass 26, count 0 2006.162.07:41:10.90#ibcon#enter sib2, iclass 26, count 0 2006.162.07:41:10.90#ibcon#flushed, iclass 26, count 0 2006.162.07:41:10.90#ibcon#about to write, iclass 26, count 0 2006.162.07:41:10.90#ibcon#wrote, iclass 26, count 0 2006.162.07:41:10.90#ibcon#about to read 3, iclass 26, count 0 2006.162.07:41:10.92#ibcon#read 3, iclass 26, count 0 2006.162.07:41:10.92#ibcon#about to read 4, iclass 26, count 0 2006.162.07:41:10.92#ibcon#read 4, iclass 26, count 0 2006.162.07:41:10.92#ibcon#about to read 5, iclass 26, count 0 2006.162.07:41:10.92#ibcon#read 5, iclass 26, count 0 2006.162.07:41:10.92#ibcon#about to read 6, iclass 26, count 0 2006.162.07:41:10.92#ibcon#read 6, iclass 26, count 0 2006.162.07:41:10.92#ibcon#end of sib2, iclass 26, count 0 2006.162.07:41:10.92#ibcon#*mode == 0, iclass 26, count 0 2006.162.07:41:10.92#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.162.07:41:10.92#ibcon#[25=USB\r\n] 2006.162.07:41:10.92#ibcon#*before write, iclass 26, count 0 2006.162.07:41:10.92#ibcon#enter sib2, iclass 26, count 0 2006.162.07:41:10.92#ibcon#flushed, iclass 26, count 0 2006.162.07:41:10.92#ibcon#about to write, iclass 26, count 0 2006.162.07:41:10.92#ibcon#wrote, iclass 26, count 0 2006.162.07:41:10.92#ibcon#about to read 3, iclass 26, count 0 2006.162.07:41:10.95#ibcon#read 3, iclass 26, count 0 2006.162.07:41:10.95#ibcon#about to read 4, iclass 26, count 0 2006.162.07:41:10.95#ibcon#read 4, iclass 26, count 0 2006.162.07:41:10.95#ibcon#about to read 5, iclass 26, count 0 2006.162.07:41:10.95#ibcon#read 5, iclass 26, count 0 2006.162.07:41:10.95#ibcon#about to read 6, iclass 26, count 0 2006.162.07:41:10.95#ibcon#read 6, iclass 26, count 0 2006.162.07:41:10.95#ibcon#end of sib2, iclass 26, count 0 2006.162.07:41:10.95#ibcon#*after write, iclass 26, count 0 2006.162.07:41:10.95#ibcon#*before return 0, iclass 26, count 0 2006.162.07:41:10.95#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:41:10.95#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:41:10.95#ibcon#about to clear, iclass 26 cls_cnt 0 2006.162.07:41:10.95#ibcon#cleared, iclass 26 cls_cnt 0 2006.162.07:41:10.95$vc4f8/valo=5,652.99 2006.162.07:41:10.95#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.162.07:41:10.95#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.162.07:41:10.95#ibcon#ireg 17 cls_cnt 0 2006.162.07:41:10.95#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:41:10.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:41:10.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:41:10.95#ibcon#enter wrdev, iclass 28, count 0 2006.162.07:41:10.95#ibcon#first serial, iclass 28, count 0 2006.162.07:41:10.95#ibcon#enter sib2, iclass 28, count 0 2006.162.07:41:10.95#ibcon#flushed, iclass 28, count 0 2006.162.07:41:10.95#ibcon#about to write, iclass 28, count 0 2006.162.07:41:10.95#ibcon#wrote, iclass 28, count 0 2006.162.07:41:10.95#ibcon#about to read 3, iclass 28, count 0 2006.162.07:41:10.97#ibcon#read 3, iclass 28, count 0 2006.162.07:41:10.97#ibcon#about to read 4, iclass 28, count 0 2006.162.07:41:10.97#ibcon#read 4, iclass 28, count 0 2006.162.07:41:10.97#ibcon#about to read 5, iclass 28, count 0 2006.162.07:41:10.97#ibcon#read 5, iclass 28, count 0 2006.162.07:41:10.97#ibcon#about to read 6, iclass 28, count 0 2006.162.07:41:10.97#ibcon#read 6, iclass 28, count 0 2006.162.07:41:10.97#ibcon#end of sib2, iclass 28, count 0 2006.162.07:41:10.97#ibcon#*mode == 0, iclass 28, count 0 2006.162.07:41:10.97#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.162.07:41:10.97#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.07:41:10.97#ibcon#*before write, iclass 28, count 0 2006.162.07:41:10.97#ibcon#enter sib2, iclass 28, count 0 2006.162.07:41:10.97#ibcon#flushed, iclass 28, count 0 2006.162.07:41:10.97#ibcon#about to write, iclass 28, count 0 2006.162.07:41:10.97#ibcon#wrote, iclass 28, count 0 2006.162.07:41:10.97#ibcon#about to read 3, iclass 28, count 0 2006.162.07:41:11.01#ibcon#read 3, iclass 28, count 0 2006.162.07:41:11.01#ibcon#about to read 4, iclass 28, count 0 2006.162.07:41:11.01#ibcon#read 4, iclass 28, count 0 2006.162.07:41:11.01#ibcon#about to read 5, iclass 28, count 0 2006.162.07:41:11.01#ibcon#read 5, iclass 28, count 0 2006.162.07:41:11.01#ibcon#about to read 6, iclass 28, count 0 2006.162.07:41:11.01#ibcon#read 6, iclass 28, count 0 2006.162.07:41:11.01#ibcon#end of sib2, iclass 28, count 0 2006.162.07:41:11.01#ibcon#*after write, iclass 28, count 0 2006.162.07:41:11.01#ibcon#*before return 0, iclass 28, count 0 2006.162.07:41:11.01#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:41:11.01#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:41:11.01#ibcon#about to clear, iclass 28 cls_cnt 0 2006.162.07:41:11.01#ibcon#cleared, iclass 28 cls_cnt 0 2006.162.07:41:11.01$vc4f8/va=5,7 2006.162.07:41:11.01#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.162.07:41:11.01#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.162.07:41:11.01#ibcon#ireg 11 cls_cnt 2 2006.162.07:41:11.01#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:41:11.07#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:41:11.07#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:41:11.07#ibcon#enter wrdev, iclass 30, count 2 2006.162.07:41:11.07#ibcon#first serial, iclass 30, count 2 2006.162.07:41:11.07#ibcon#enter sib2, iclass 30, count 2 2006.162.07:41:11.07#ibcon#flushed, iclass 30, count 2 2006.162.07:41:11.07#ibcon#about to write, iclass 30, count 2 2006.162.07:41:11.08#ibcon#wrote, iclass 30, count 2 2006.162.07:41:11.08#ibcon#about to read 3, iclass 30, count 2 2006.162.07:41:11.09#ibcon#read 3, iclass 30, count 2 2006.162.07:41:11.09#ibcon#about to read 4, iclass 30, count 2 2006.162.07:41:11.09#ibcon#read 4, iclass 30, count 2 2006.162.07:41:11.09#ibcon#about to read 5, iclass 30, count 2 2006.162.07:41:11.09#ibcon#read 5, iclass 30, count 2 2006.162.07:41:11.09#ibcon#about to read 6, iclass 30, count 2 2006.162.07:41:11.09#ibcon#read 6, iclass 30, count 2 2006.162.07:41:11.09#ibcon#end of sib2, iclass 30, count 2 2006.162.07:41:11.09#ibcon#*mode == 0, iclass 30, count 2 2006.162.07:41:11.09#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.162.07:41:11.09#ibcon#[25=AT05-07\r\n] 2006.162.07:41:11.09#ibcon#*before write, iclass 30, count 2 2006.162.07:41:11.09#ibcon#enter sib2, iclass 30, count 2 2006.162.07:41:11.09#ibcon#flushed, iclass 30, count 2 2006.162.07:41:11.09#ibcon#about to write, iclass 30, count 2 2006.162.07:41:11.09#ibcon#wrote, iclass 30, count 2 2006.162.07:41:11.09#ibcon#about to read 3, iclass 30, count 2 2006.162.07:41:11.12#ibcon#read 3, iclass 30, count 2 2006.162.07:41:11.12#ibcon#about to read 4, iclass 30, count 2 2006.162.07:41:11.12#ibcon#read 4, iclass 30, count 2 2006.162.07:41:11.12#ibcon#about to read 5, iclass 30, count 2 2006.162.07:41:11.12#ibcon#read 5, iclass 30, count 2 2006.162.07:41:11.12#ibcon#about to read 6, iclass 30, count 2 2006.162.07:41:11.12#ibcon#read 6, iclass 30, count 2 2006.162.07:41:11.12#ibcon#end of sib2, iclass 30, count 2 2006.162.07:41:11.12#ibcon#*after write, iclass 30, count 2 2006.162.07:41:11.12#ibcon#*before return 0, iclass 30, count 2 2006.162.07:41:11.12#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:41:11.12#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:41:11.12#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.162.07:41:11.12#ibcon#ireg 7 cls_cnt 0 2006.162.07:41:11.12#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:41:11.24#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:41:11.24#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:41:11.24#ibcon#enter wrdev, iclass 30, count 0 2006.162.07:41:11.24#ibcon#first serial, iclass 30, count 0 2006.162.07:41:11.24#ibcon#enter sib2, iclass 30, count 0 2006.162.07:41:11.24#ibcon#flushed, iclass 30, count 0 2006.162.07:41:11.24#ibcon#about to write, iclass 30, count 0 2006.162.07:41:11.24#ibcon#wrote, iclass 30, count 0 2006.162.07:41:11.24#ibcon#about to read 3, iclass 30, count 0 2006.162.07:41:11.26#ibcon#read 3, iclass 30, count 0 2006.162.07:41:11.26#ibcon#about to read 4, iclass 30, count 0 2006.162.07:41:11.26#ibcon#read 4, iclass 30, count 0 2006.162.07:41:11.26#ibcon#about to read 5, iclass 30, count 0 2006.162.07:41:11.26#ibcon#read 5, iclass 30, count 0 2006.162.07:41:11.26#ibcon#about to read 6, iclass 30, count 0 2006.162.07:41:11.26#ibcon#read 6, iclass 30, count 0 2006.162.07:41:11.26#ibcon#end of sib2, iclass 30, count 0 2006.162.07:41:11.26#ibcon#*mode == 0, iclass 30, count 0 2006.162.07:41:11.26#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.162.07:41:11.26#ibcon#[25=USB\r\n] 2006.162.07:41:11.26#ibcon#*before write, iclass 30, count 0 2006.162.07:41:11.26#ibcon#enter sib2, iclass 30, count 0 2006.162.07:41:11.26#ibcon#flushed, iclass 30, count 0 2006.162.07:41:11.26#ibcon#about to write, iclass 30, count 0 2006.162.07:41:11.26#ibcon#wrote, iclass 30, count 0 2006.162.07:41:11.26#ibcon#about to read 3, iclass 30, count 0 2006.162.07:41:11.29#ibcon#read 3, iclass 30, count 0 2006.162.07:41:11.29#ibcon#about to read 4, iclass 30, count 0 2006.162.07:41:11.29#ibcon#read 4, iclass 30, count 0 2006.162.07:41:11.29#ibcon#about to read 5, iclass 30, count 0 2006.162.07:41:11.29#ibcon#read 5, iclass 30, count 0 2006.162.07:41:11.29#ibcon#about to read 6, iclass 30, count 0 2006.162.07:41:11.29#ibcon#read 6, iclass 30, count 0 2006.162.07:41:11.29#ibcon#end of sib2, iclass 30, count 0 2006.162.07:41:11.29#ibcon#*after write, iclass 30, count 0 2006.162.07:41:11.29#ibcon#*before return 0, iclass 30, count 0 2006.162.07:41:11.29#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:41:11.29#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:41:11.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.162.07:41:11.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.162.07:41:11.29$vc4f8/valo=6,772.99 2006.162.07:41:11.29#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.162.07:41:11.29#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.162.07:41:11.29#ibcon#ireg 17 cls_cnt 0 2006.162.07:41:11.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:41:11.29#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:41:11.29#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:41:11.29#ibcon#enter wrdev, iclass 32, count 0 2006.162.07:41:11.29#ibcon#first serial, iclass 32, count 0 2006.162.07:41:11.29#ibcon#enter sib2, iclass 32, count 0 2006.162.07:41:11.29#ibcon#flushed, iclass 32, count 0 2006.162.07:41:11.29#ibcon#about to write, iclass 32, count 0 2006.162.07:41:11.29#ibcon#wrote, iclass 32, count 0 2006.162.07:41:11.29#ibcon#about to read 3, iclass 32, count 0 2006.162.07:41:11.31#ibcon#read 3, iclass 32, count 0 2006.162.07:41:11.31#ibcon#about to read 4, iclass 32, count 0 2006.162.07:41:11.31#ibcon#read 4, iclass 32, count 0 2006.162.07:41:11.31#ibcon#about to read 5, iclass 32, count 0 2006.162.07:41:11.31#ibcon#read 5, iclass 32, count 0 2006.162.07:41:11.31#ibcon#about to read 6, iclass 32, count 0 2006.162.07:41:11.31#ibcon#read 6, iclass 32, count 0 2006.162.07:41:11.31#ibcon#end of sib2, iclass 32, count 0 2006.162.07:41:11.31#ibcon#*mode == 0, iclass 32, count 0 2006.162.07:41:11.31#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.162.07:41:11.31#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.07:41:11.31#ibcon#*before write, iclass 32, count 0 2006.162.07:41:11.31#ibcon#enter sib2, iclass 32, count 0 2006.162.07:41:11.31#ibcon#flushed, iclass 32, count 0 2006.162.07:41:11.31#ibcon#about to write, iclass 32, count 0 2006.162.07:41:11.31#ibcon#wrote, iclass 32, count 0 2006.162.07:41:11.31#ibcon#about to read 3, iclass 32, count 0 2006.162.07:41:11.35#ibcon#read 3, iclass 32, count 0 2006.162.07:41:11.35#ibcon#about to read 4, iclass 32, count 0 2006.162.07:41:11.35#ibcon#read 4, iclass 32, count 0 2006.162.07:41:11.35#ibcon#about to read 5, iclass 32, count 0 2006.162.07:41:11.35#ibcon#read 5, iclass 32, count 0 2006.162.07:41:11.35#ibcon#about to read 6, iclass 32, count 0 2006.162.07:41:11.35#ibcon#read 6, iclass 32, count 0 2006.162.07:41:11.35#ibcon#end of sib2, iclass 32, count 0 2006.162.07:41:11.35#ibcon#*after write, iclass 32, count 0 2006.162.07:41:11.35#ibcon#*before return 0, iclass 32, count 0 2006.162.07:41:11.35#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:41:11.35#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:41:11.35#ibcon#about to clear, iclass 32 cls_cnt 0 2006.162.07:41:11.35#ibcon#cleared, iclass 32 cls_cnt 0 2006.162.07:41:11.35$vc4f8/va=6,6 2006.162.07:41:11.35#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.162.07:41:11.35#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.162.07:41:11.35#ibcon#ireg 11 cls_cnt 2 2006.162.07:41:11.35#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.162.07:41:11.41#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.162.07:41:11.41#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.162.07:41:11.41#ibcon#enter wrdev, iclass 34, count 2 2006.162.07:41:11.41#ibcon#first serial, iclass 34, count 2 2006.162.07:41:11.41#ibcon#enter sib2, iclass 34, count 2 2006.162.07:41:11.41#ibcon#flushed, iclass 34, count 2 2006.162.07:41:11.41#ibcon#about to write, iclass 34, count 2 2006.162.07:41:11.41#ibcon#wrote, iclass 34, count 2 2006.162.07:41:11.41#ibcon#about to read 3, iclass 34, count 2 2006.162.07:41:11.43#ibcon#read 3, iclass 34, count 2 2006.162.07:41:11.43#ibcon#about to read 4, iclass 34, count 2 2006.162.07:41:11.43#ibcon#read 4, iclass 34, count 2 2006.162.07:41:11.43#ibcon#about to read 5, iclass 34, count 2 2006.162.07:41:11.43#ibcon#read 5, iclass 34, count 2 2006.162.07:41:11.43#ibcon#about to read 6, iclass 34, count 2 2006.162.07:41:11.43#ibcon#read 6, iclass 34, count 2 2006.162.07:41:11.43#ibcon#end of sib2, iclass 34, count 2 2006.162.07:41:11.43#ibcon#*mode == 0, iclass 34, count 2 2006.162.07:41:11.43#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.162.07:41:11.43#ibcon#[25=AT06-06\r\n] 2006.162.07:41:11.43#ibcon#*before write, iclass 34, count 2 2006.162.07:41:11.43#ibcon#enter sib2, iclass 34, count 2 2006.162.07:41:11.43#ibcon#flushed, iclass 34, count 2 2006.162.07:41:11.43#ibcon#about to write, iclass 34, count 2 2006.162.07:41:11.43#ibcon#wrote, iclass 34, count 2 2006.162.07:41:11.43#ibcon#about to read 3, iclass 34, count 2 2006.162.07:41:11.46#ibcon#read 3, iclass 34, count 2 2006.162.07:41:11.46#ibcon#about to read 4, iclass 34, count 2 2006.162.07:41:11.46#ibcon#read 4, iclass 34, count 2 2006.162.07:41:11.46#ibcon#about to read 5, iclass 34, count 2 2006.162.07:41:11.46#ibcon#read 5, iclass 34, count 2 2006.162.07:41:11.46#ibcon#about to read 6, iclass 34, count 2 2006.162.07:41:11.46#ibcon#read 6, iclass 34, count 2 2006.162.07:41:11.46#ibcon#end of sib2, iclass 34, count 2 2006.162.07:41:11.46#ibcon#*after write, iclass 34, count 2 2006.162.07:41:11.46#ibcon#*before return 0, iclass 34, count 2 2006.162.07:41:11.46#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.162.07:41:11.46#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.162.07:41:11.46#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.162.07:41:11.46#ibcon#ireg 7 cls_cnt 0 2006.162.07:41:11.46#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.162.07:41:11.58#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.162.07:41:11.58#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.162.07:41:11.58#ibcon#enter wrdev, iclass 34, count 0 2006.162.07:41:11.58#ibcon#first serial, iclass 34, count 0 2006.162.07:41:11.58#ibcon#enter sib2, iclass 34, count 0 2006.162.07:41:11.58#ibcon#flushed, iclass 34, count 0 2006.162.07:41:11.58#ibcon#about to write, iclass 34, count 0 2006.162.07:41:11.58#ibcon#wrote, iclass 34, count 0 2006.162.07:41:11.58#ibcon#about to read 3, iclass 34, count 0 2006.162.07:41:11.60#ibcon#read 3, iclass 34, count 0 2006.162.07:41:11.60#ibcon#about to read 4, iclass 34, count 0 2006.162.07:41:11.60#ibcon#read 4, iclass 34, count 0 2006.162.07:41:11.60#ibcon#about to read 5, iclass 34, count 0 2006.162.07:41:11.60#ibcon#read 5, iclass 34, count 0 2006.162.07:41:11.60#ibcon#about to read 6, iclass 34, count 0 2006.162.07:41:11.60#ibcon#read 6, iclass 34, count 0 2006.162.07:41:11.60#ibcon#end of sib2, iclass 34, count 0 2006.162.07:41:11.60#ibcon#*mode == 0, iclass 34, count 0 2006.162.07:41:11.60#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.162.07:41:11.60#ibcon#[25=USB\r\n] 2006.162.07:41:11.60#ibcon#*before write, iclass 34, count 0 2006.162.07:41:11.60#ibcon#enter sib2, iclass 34, count 0 2006.162.07:41:11.60#ibcon#flushed, iclass 34, count 0 2006.162.07:41:11.60#ibcon#about to write, iclass 34, count 0 2006.162.07:41:11.60#ibcon#wrote, iclass 34, count 0 2006.162.07:41:11.60#ibcon#about to read 3, iclass 34, count 0 2006.162.07:41:11.63#ibcon#read 3, iclass 34, count 0 2006.162.07:41:11.63#ibcon#about to read 4, iclass 34, count 0 2006.162.07:41:11.63#ibcon#read 4, iclass 34, count 0 2006.162.07:41:11.63#ibcon#about to read 5, iclass 34, count 0 2006.162.07:41:11.63#ibcon#read 5, iclass 34, count 0 2006.162.07:41:11.63#ibcon#about to read 6, iclass 34, count 0 2006.162.07:41:11.63#ibcon#read 6, iclass 34, count 0 2006.162.07:41:11.63#ibcon#end of sib2, iclass 34, count 0 2006.162.07:41:11.63#ibcon#*after write, iclass 34, count 0 2006.162.07:41:11.63#ibcon#*before return 0, iclass 34, count 0 2006.162.07:41:11.63#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.162.07:41:11.63#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.162.07:41:11.63#ibcon#about to clear, iclass 34 cls_cnt 0 2006.162.07:41:11.63#ibcon#cleared, iclass 34 cls_cnt 0 2006.162.07:41:11.63$vc4f8/valo=7,832.99 2006.162.07:41:11.63#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.162.07:41:11.63#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.162.07:41:11.63#ibcon#ireg 17 cls_cnt 0 2006.162.07:41:11.63#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:41:11.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:41:11.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:41:11.63#ibcon#enter wrdev, iclass 36, count 0 2006.162.07:41:11.63#ibcon#first serial, iclass 36, count 0 2006.162.07:41:11.63#ibcon#enter sib2, iclass 36, count 0 2006.162.07:41:11.63#ibcon#flushed, iclass 36, count 0 2006.162.07:41:11.63#ibcon#about to write, iclass 36, count 0 2006.162.07:41:11.63#ibcon#wrote, iclass 36, count 0 2006.162.07:41:11.63#ibcon#about to read 3, iclass 36, count 0 2006.162.07:41:11.65#ibcon#read 3, iclass 36, count 0 2006.162.07:41:11.65#ibcon#about to read 4, iclass 36, count 0 2006.162.07:41:11.65#ibcon#read 4, iclass 36, count 0 2006.162.07:41:11.65#ibcon#about to read 5, iclass 36, count 0 2006.162.07:41:11.65#ibcon#read 5, iclass 36, count 0 2006.162.07:41:11.65#ibcon#about to read 6, iclass 36, count 0 2006.162.07:41:11.65#ibcon#read 6, iclass 36, count 0 2006.162.07:41:11.65#ibcon#end of sib2, iclass 36, count 0 2006.162.07:41:11.65#ibcon#*mode == 0, iclass 36, count 0 2006.162.07:41:11.65#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.162.07:41:11.65#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.07:41:11.65#ibcon#*before write, iclass 36, count 0 2006.162.07:41:11.65#ibcon#enter sib2, iclass 36, count 0 2006.162.07:41:11.65#ibcon#flushed, iclass 36, count 0 2006.162.07:41:11.65#ibcon#about to write, iclass 36, count 0 2006.162.07:41:11.65#ibcon#wrote, iclass 36, count 0 2006.162.07:41:11.65#ibcon#about to read 3, iclass 36, count 0 2006.162.07:41:11.69#ibcon#read 3, iclass 36, count 0 2006.162.07:41:11.69#ibcon#about to read 4, iclass 36, count 0 2006.162.07:41:11.69#ibcon#read 4, iclass 36, count 0 2006.162.07:41:11.69#ibcon#about to read 5, iclass 36, count 0 2006.162.07:41:11.69#ibcon#read 5, iclass 36, count 0 2006.162.07:41:11.69#ibcon#about to read 6, iclass 36, count 0 2006.162.07:41:11.69#ibcon#read 6, iclass 36, count 0 2006.162.07:41:11.69#ibcon#end of sib2, iclass 36, count 0 2006.162.07:41:11.69#ibcon#*after write, iclass 36, count 0 2006.162.07:41:11.69#ibcon#*before return 0, iclass 36, count 0 2006.162.07:41:11.69#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:41:11.69#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:41:11.69#ibcon#about to clear, iclass 36 cls_cnt 0 2006.162.07:41:11.69#ibcon#cleared, iclass 36 cls_cnt 0 2006.162.07:41:11.69$vc4f8/va=7,6 2006.162.07:41:11.69#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.162.07:41:11.69#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.162.07:41:11.69#ibcon#ireg 11 cls_cnt 2 2006.162.07:41:11.69#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:41:11.75#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:41:11.75#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:41:11.75#ibcon#enter wrdev, iclass 38, count 2 2006.162.07:41:11.75#ibcon#first serial, iclass 38, count 2 2006.162.07:41:11.75#ibcon#enter sib2, iclass 38, count 2 2006.162.07:41:11.75#ibcon#flushed, iclass 38, count 2 2006.162.07:41:11.75#ibcon#about to write, iclass 38, count 2 2006.162.07:41:11.75#ibcon#wrote, iclass 38, count 2 2006.162.07:41:11.75#ibcon#about to read 3, iclass 38, count 2 2006.162.07:41:11.77#ibcon#read 3, iclass 38, count 2 2006.162.07:41:11.77#ibcon#about to read 4, iclass 38, count 2 2006.162.07:41:11.77#ibcon#read 4, iclass 38, count 2 2006.162.07:41:11.77#ibcon#about to read 5, iclass 38, count 2 2006.162.07:41:11.77#ibcon#read 5, iclass 38, count 2 2006.162.07:41:11.77#ibcon#about to read 6, iclass 38, count 2 2006.162.07:41:11.77#ibcon#read 6, iclass 38, count 2 2006.162.07:41:11.77#ibcon#end of sib2, iclass 38, count 2 2006.162.07:41:11.77#ibcon#*mode == 0, iclass 38, count 2 2006.162.07:41:11.77#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.162.07:41:11.77#ibcon#[25=AT07-06\r\n] 2006.162.07:41:11.77#ibcon#*before write, iclass 38, count 2 2006.162.07:41:11.77#ibcon#enter sib2, iclass 38, count 2 2006.162.07:41:11.77#ibcon#flushed, iclass 38, count 2 2006.162.07:41:11.77#ibcon#about to write, iclass 38, count 2 2006.162.07:41:11.77#ibcon#wrote, iclass 38, count 2 2006.162.07:41:11.77#ibcon#about to read 3, iclass 38, count 2 2006.162.07:41:11.80#ibcon#read 3, iclass 38, count 2 2006.162.07:41:11.80#ibcon#about to read 4, iclass 38, count 2 2006.162.07:41:11.80#ibcon#read 4, iclass 38, count 2 2006.162.07:41:11.80#ibcon#about to read 5, iclass 38, count 2 2006.162.07:41:11.80#ibcon#read 5, iclass 38, count 2 2006.162.07:41:11.80#ibcon#about to read 6, iclass 38, count 2 2006.162.07:41:11.80#ibcon#read 6, iclass 38, count 2 2006.162.07:41:11.80#ibcon#end of sib2, iclass 38, count 2 2006.162.07:41:11.80#ibcon#*after write, iclass 38, count 2 2006.162.07:41:11.80#ibcon#*before return 0, iclass 38, count 2 2006.162.07:41:11.80#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:41:11.80#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:41:11.80#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.162.07:41:11.80#ibcon#ireg 7 cls_cnt 0 2006.162.07:41:11.80#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:41:11.92#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:41:11.92#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:41:11.92#ibcon#enter wrdev, iclass 38, count 0 2006.162.07:41:11.92#ibcon#first serial, iclass 38, count 0 2006.162.07:41:11.92#ibcon#enter sib2, iclass 38, count 0 2006.162.07:41:11.92#ibcon#flushed, iclass 38, count 0 2006.162.07:41:11.92#ibcon#about to write, iclass 38, count 0 2006.162.07:41:11.92#ibcon#wrote, iclass 38, count 0 2006.162.07:41:11.92#ibcon#about to read 3, iclass 38, count 0 2006.162.07:41:11.94#ibcon#read 3, iclass 38, count 0 2006.162.07:41:11.94#ibcon#about to read 4, iclass 38, count 0 2006.162.07:41:11.94#ibcon#read 4, iclass 38, count 0 2006.162.07:41:11.94#ibcon#about to read 5, iclass 38, count 0 2006.162.07:41:11.94#ibcon#read 5, iclass 38, count 0 2006.162.07:41:11.94#ibcon#about to read 6, iclass 38, count 0 2006.162.07:41:11.94#ibcon#read 6, iclass 38, count 0 2006.162.07:41:11.94#ibcon#end of sib2, iclass 38, count 0 2006.162.07:41:11.94#ibcon#*mode == 0, iclass 38, count 0 2006.162.07:41:11.94#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.162.07:41:11.94#ibcon#[25=USB\r\n] 2006.162.07:41:11.94#ibcon#*before write, iclass 38, count 0 2006.162.07:41:11.94#ibcon#enter sib2, iclass 38, count 0 2006.162.07:41:11.94#ibcon#flushed, iclass 38, count 0 2006.162.07:41:11.94#ibcon#about to write, iclass 38, count 0 2006.162.07:41:11.94#ibcon#wrote, iclass 38, count 0 2006.162.07:41:11.94#ibcon#about to read 3, iclass 38, count 0 2006.162.07:41:11.97#ibcon#read 3, iclass 38, count 0 2006.162.07:41:11.97#ibcon#about to read 4, iclass 38, count 0 2006.162.07:41:11.97#ibcon#read 4, iclass 38, count 0 2006.162.07:41:11.97#ibcon#about to read 5, iclass 38, count 0 2006.162.07:41:11.97#ibcon#read 5, iclass 38, count 0 2006.162.07:41:11.97#ibcon#about to read 6, iclass 38, count 0 2006.162.07:41:11.97#ibcon#read 6, iclass 38, count 0 2006.162.07:41:11.97#ibcon#end of sib2, iclass 38, count 0 2006.162.07:41:11.97#ibcon#*after write, iclass 38, count 0 2006.162.07:41:11.97#ibcon#*before return 0, iclass 38, count 0 2006.162.07:41:11.97#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:41:11.97#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:41:11.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.162.07:41:11.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.162.07:41:11.97$vc4f8/valo=8,852.99 2006.162.07:41:11.97#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.162.07:41:11.97#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.162.07:41:11.97#ibcon#ireg 17 cls_cnt 0 2006.162.07:41:11.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:41:11.97#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:41:11.97#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:41:11.97#ibcon#enter wrdev, iclass 40, count 0 2006.162.07:41:11.97#ibcon#first serial, iclass 40, count 0 2006.162.07:41:11.97#ibcon#enter sib2, iclass 40, count 0 2006.162.07:41:11.97#ibcon#flushed, iclass 40, count 0 2006.162.07:41:11.97#ibcon#about to write, iclass 40, count 0 2006.162.07:41:11.97#ibcon#wrote, iclass 40, count 0 2006.162.07:41:11.97#ibcon#about to read 3, iclass 40, count 0 2006.162.07:41:11.99#ibcon#read 3, iclass 40, count 0 2006.162.07:41:11.99#ibcon#about to read 4, iclass 40, count 0 2006.162.07:41:11.99#ibcon#read 4, iclass 40, count 0 2006.162.07:41:11.99#ibcon#about to read 5, iclass 40, count 0 2006.162.07:41:11.99#ibcon#read 5, iclass 40, count 0 2006.162.07:41:11.99#ibcon#about to read 6, iclass 40, count 0 2006.162.07:41:11.99#ibcon#read 6, iclass 40, count 0 2006.162.07:41:11.99#ibcon#end of sib2, iclass 40, count 0 2006.162.07:41:11.99#ibcon#*mode == 0, iclass 40, count 0 2006.162.07:41:11.99#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.162.07:41:11.99#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.07:41:11.99#ibcon#*before write, iclass 40, count 0 2006.162.07:41:11.99#ibcon#enter sib2, iclass 40, count 0 2006.162.07:41:11.99#ibcon#flushed, iclass 40, count 0 2006.162.07:41:11.99#ibcon#about to write, iclass 40, count 0 2006.162.07:41:11.99#ibcon#wrote, iclass 40, count 0 2006.162.07:41:11.99#ibcon#about to read 3, iclass 40, count 0 2006.162.07:41:12.03#ibcon#read 3, iclass 40, count 0 2006.162.07:41:12.03#ibcon#about to read 4, iclass 40, count 0 2006.162.07:41:12.03#ibcon#read 4, iclass 40, count 0 2006.162.07:41:12.03#ibcon#about to read 5, iclass 40, count 0 2006.162.07:41:12.03#ibcon#read 5, iclass 40, count 0 2006.162.07:41:12.03#ibcon#about to read 6, iclass 40, count 0 2006.162.07:41:12.03#ibcon#read 6, iclass 40, count 0 2006.162.07:41:12.03#ibcon#end of sib2, iclass 40, count 0 2006.162.07:41:12.03#ibcon#*after write, iclass 40, count 0 2006.162.07:41:12.03#ibcon#*before return 0, iclass 40, count 0 2006.162.07:41:12.03#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:41:12.03#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:41:12.03#ibcon#about to clear, iclass 40 cls_cnt 0 2006.162.07:41:12.03#ibcon#cleared, iclass 40 cls_cnt 0 2006.162.07:41:12.03$vc4f8/va=8,7 2006.162.07:41:12.03#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.162.07:41:12.03#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.162.07:41:12.03#ibcon#ireg 11 cls_cnt 2 2006.162.07:41:12.03#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:41:12.09#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:41:12.09#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:41:12.09#ibcon#enter wrdev, iclass 4, count 2 2006.162.07:41:12.09#ibcon#first serial, iclass 4, count 2 2006.162.07:41:12.09#ibcon#enter sib2, iclass 4, count 2 2006.162.07:41:12.09#ibcon#flushed, iclass 4, count 2 2006.162.07:41:12.09#ibcon#about to write, iclass 4, count 2 2006.162.07:41:12.09#ibcon#wrote, iclass 4, count 2 2006.162.07:41:12.09#ibcon#about to read 3, iclass 4, count 2 2006.162.07:41:12.11#ibcon#read 3, iclass 4, count 2 2006.162.07:41:12.11#ibcon#about to read 4, iclass 4, count 2 2006.162.07:41:12.11#ibcon#read 4, iclass 4, count 2 2006.162.07:41:12.11#ibcon#about to read 5, iclass 4, count 2 2006.162.07:41:12.11#ibcon#read 5, iclass 4, count 2 2006.162.07:41:12.11#ibcon#about to read 6, iclass 4, count 2 2006.162.07:41:12.11#ibcon#read 6, iclass 4, count 2 2006.162.07:41:12.11#ibcon#end of sib2, iclass 4, count 2 2006.162.07:41:12.11#ibcon#*mode == 0, iclass 4, count 2 2006.162.07:41:12.11#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.162.07:41:12.11#ibcon#[25=AT08-07\r\n] 2006.162.07:41:12.11#ibcon#*before write, iclass 4, count 2 2006.162.07:41:12.11#ibcon#enter sib2, iclass 4, count 2 2006.162.07:41:12.11#ibcon#flushed, iclass 4, count 2 2006.162.07:41:12.11#ibcon#about to write, iclass 4, count 2 2006.162.07:41:12.11#ibcon#wrote, iclass 4, count 2 2006.162.07:41:12.11#ibcon#about to read 3, iclass 4, count 2 2006.162.07:41:12.14#ibcon#read 3, iclass 4, count 2 2006.162.07:41:12.14#ibcon#about to read 4, iclass 4, count 2 2006.162.07:41:12.14#ibcon#read 4, iclass 4, count 2 2006.162.07:41:12.14#ibcon#about to read 5, iclass 4, count 2 2006.162.07:41:12.14#ibcon#read 5, iclass 4, count 2 2006.162.07:41:12.14#ibcon#about to read 6, iclass 4, count 2 2006.162.07:41:12.14#ibcon#read 6, iclass 4, count 2 2006.162.07:41:12.14#ibcon#end of sib2, iclass 4, count 2 2006.162.07:41:12.14#ibcon#*after write, iclass 4, count 2 2006.162.07:41:12.14#ibcon#*before return 0, iclass 4, count 2 2006.162.07:41:12.14#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:41:12.14#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:41:12.14#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.162.07:41:12.14#ibcon#ireg 7 cls_cnt 0 2006.162.07:41:12.14#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:41:12.26#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:41:12.26#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:41:12.26#ibcon#enter wrdev, iclass 4, count 0 2006.162.07:41:12.26#ibcon#first serial, iclass 4, count 0 2006.162.07:41:12.26#ibcon#enter sib2, iclass 4, count 0 2006.162.07:41:12.26#ibcon#flushed, iclass 4, count 0 2006.162.07:41:12.26#ibcon#about to write, iclass 4, count 0 2006.162.07:41:12.26#ibcon#wrote, iclass 4, count 0 2006.162.07:41:12.26#ibcon#about to read 3, iclass 4, count 0 2006.162.07:41:12.28#ibcon#read 3, iclass 4, count 0 2006.162.07:41:12.28#ibcon#about to read 4, iclass 4, count 0 2006.162.07:41:12.28#ibcon#read 4, iclass 4, count 0 2006.162.07:41:12.28#ibcon#about to read 5, iclass 4, count 0 2006.162.07:41:12.28#ibcon#read 5, iclass 4, count 0 2006.162.07:41:12.28#ibcon#about to read 6, iclass 4, count 0 2006.162.07:41:12.28#ibcon#read 6, iclass 4, count 0 2006.162.07:41:12.28#ibcon#end of sib2, iclass 4, count 0 2006.162.07:41:12.28#ibcon#*mode == 0, iclass 4, count 0 2006.162.07:41:12.28#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.162.07:41:12.28#ibcon#[25=USB\r\n] 2006.162.07:41:12.28#ibcon#*before write, iclass 4, count 0 2006.162.07:41:12.28#ibcon#enter sib2, iclass 4, count 0 2006.162.07:41:12.28#ibcon#flushed, iclass 4, count 0 2006.162.07:41:12.28#ibcon#about to write, iclass 4, count 0 2006.162.07:41:12.28#ibcon#wrote, iclass 4, count 0 2006.162.07:41:12.28#ibcon#about to read 3, iclass 4, count 0 2006.162.07:41:12.31#ibcon#read 3, iclass 4, count 0 2006.162.07:41:12.31#ibcon#about to read 4, iclass 4, count 0 2006.162.07:41:12.31#ibcon#read 4, iclass 4, count 0 2006.162.07:41:12.31#ibcon#about to read 5, iclass 4, count 0 2006.162.07:41:12.31#ibcon#read 5, iclass 4, count 0 2006.162.07:41:12.31#ibcon#about to read 6, iclass 4, count 0 2006.162.07:41:12.31#ibcon#read 6, iclass 4, count 0 2006.162.07:41:12.31#ibcon#end of sib2, iclass 4, count 0 2006.162.07:41:12.31#ibcon#*after write, iclass 4, count 0 2006.162.07:41:12.31#ibcon#*before return 0, iclass 4, count 0 2006.162.07:41:12.31#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:41:12.31#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:41:12.31#ibcon#about to clear, iclass 4 cls_cnt 0 2006.162.07:41:12.31#ibcon#cleared, iclass 4 cls_cnt 0 2006.162.07:41:12.31$vc4f8/vblo=1,632.99 2006.162.07:41:12.31#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.162.07:41:12.31#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.162.07:41:12.31#ibcon#ireg 17 cls_cnt 0 2006.162.07:41:12.31#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:41:12.31#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:41:12.31#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:41:12.31#ibcon#enter wrdev, iclass 6, count 0 2006.162.07:41:12.31#ibcon#first serial, iclass 6, count 0 2006.162.07:41:12.31#ibcon#enter sib2, iclass 6, count 0 2006.162.07:41:12.31#ibcon#flushed, iclass 6, count 0 2006.162.07:41:12.31#ibcon#about to write, iclass 6, count 0 2006.162.07:41:12.31#ibcon#wrote, iclass 6, count 0 2006.162.07:41:12.31#ibcon#about to read 3, iclass 6, count 0 2006.162.07:41:12.33#ibcon#read 3, iclass 6, count 0 2006.162.07:41:12.33#ibcon#about to read 4, iclass 6, count 0 2006.162.07:41:12.33#ibcon#read 4, iclass 6, count 0 2006.162.07:41:12.33#ibcon#about to read 5, iclass 6, count 0 2006.162.07:41:12.33#ibcon#read 5, iclass 6, count 0 2006.162.07:41:12.33#ibcon#about to read 6, iclass 6, count 0 2006.162.07:41:12.33#ibcon#read 6, iclass 6, count 0 2006.162.07:41:12.33#ibcon#end of sib2, iclass 6, count 0 2006.162.07:41:12.33#ibcon#*mode == 0, iclass 6, count 0 2006.162.07:41:12.33#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.162.07:41:12.33#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.07:41:12.33#ibcon#*before write, iclass 6, count 0 2006.162.07:41:12.33#ibcon#enter sib2, iclass 6, count 0 2006.162.07:41:12.33#ibcon#flushed, iclass 6, count 0 2006.162.07:41:12.33#ibcon#about to write, iclass 6, count 0 2006.162.07:41:12.33#ibcon#wrote, iclass 6, count 0 2006.162.07:41:12.33#ibcon#about to read 3, iclass 6, count 0 2006.162.07:41:12.37#ibcon#read 3, iclass 6, count 0 2006.162.07:41:12.37#ibcon#about to read 4, iclass 6, count 0 2006.162.07:41:12.37#ibcon#read 4, iclass 6, count 0 2006.162.07:41:12.37#ibcon#about to read 5, iclass 6, count 0 2006.162.07:41:12.37#ibcon#read 5, iclass 6, count 0 2006.162.07:41:12.37#ibcon#about to read 6, iclass 6, count 0 2006.162.07:41:12.37#ibcon#read 6, iclass 6, count 0 2006.162.07:41:12.37#ibcon#end of sib2, iclass 6, count 0 2006.162.07:41:12.37#ibcon#*after write, iclass 6, count 0 2006.162.07:41:12.37#ibcon#*before return 0, iclass 6, count 0 2006.162.07:41:12.37#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:41:12.37#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:41:12.37#ibcon#about to clear, iclass 6 cls_cnt 0 2006.162.07:41:12.37#ibcon#cleared, iclass 6 cls_cnt 0 2006.162.07:41:12.37$vc4f8/vb=1,4 2006.162.07:41:12.37#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.162.07:41:12.37#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.162.07:41:12.37#ibcon#ireg 11 cls_cnt 2 2006.162.07:41:12.37#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:41:12.37#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:41:12.37#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:41:12.37#ibcon#enter wrdev, iclass 10, count 2 2006.162.07:41:12.37#ibcon#first serial, iclass 10, count 2 2006.162.07:41:12.37#ibcon#enter sib2, iclass 10, count 2 2006.162.07:41:12.37#ibcon#flushed, iclass 10, count 2 2006.162.07:41:12.37#ibcon#about to write, iclass 10, count 2 2006.162.07:41:12.37#ibcon#wrote, iclass 10, count 2 2006.162.07:41:12.37#ibcon#about to read 3, iclass 10, count 2 2006.162.07:41:12.39#ibcon#read 3, iclass 10, count 2 2006.162.07:41:12.39#ibcon#about to read 4, iclass 10, count 2 2006.162.07:41:12.39#ibcon#read 4, iclass 10, count 2 2006.162.07:41:12.39#ibcon#about to read 5, iclass 10, count 2 2006.162.07:41:12.39#ibcon#read 5, iclass 10, count 2 2006.162.07:41:12.39#ibcon#about to read 6, iclass 10, count 2 2006.162.07:41:12.39#ibcon#read 6, iclass 10, count 2 2006.162.07:41:12.39#ibcon#end of sib2, iclass 10, count 2 2006.162.07:41:12.39#ibcon#*mode == 0, iclass 10, count 2 2006.162.07:41:12.39#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.162.07:41:12.39#ibcon#[27=AT01-04\r\n] 2006.162.07:41:12.39#ibcon#*before write, iclass 10, count 2 2006.162.07:41:12.39#ibcon#enter sib2, iclass 10, count 2 2006.162.07:41:12.39#ibcon#flushed, iclass 10, count 2 2006.162.07:41:12.39#ibcon#about to write, iclass 10, count 2 2006.162.07:41:12.39#ibcon#wrote, iclass 10, count 2 2006.162.07:41:12.39#ibcon#about to read 3, iclass 10, count 2 2006.162.07:41:12.42#ibcon#read 3, iclass 10, count 2 2006.162.07:41:12.42#ibcon#about to read 4, iclass 10, count 2 2006.162.07:41:12.42#ibcon#read 4, iclass 10, count 2 2006.162.07:41:12.42#ibcon#about to read 5, iclass 10, count 2 2006.162.07:41:12.42#ibcon#read 5, iclass 10, count 2 2006.162.07:41:12.42#ibcon#about to read 6, iclass 10, count 2 2006.162.07:41:12.42#ibcon#read 6, iclass 10, count 2 2006.162.07:41:12.42#ibcon#end of sib2, iclass 10, count 2 2006.162.07:41:12.42#ibcon#*after write, iclass 10, count 2 2006.162.07:41:12.42#ibcon#*before return 0, iclass 10, count 2 2006.162.07:41:12.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:41:12.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:41:12.42#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.162.07:41:12.42#ibcon#ireg 7 cls_cnt 0 2006.162.07:41:12.42#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:41:12.54#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:41:12.54#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:41:12.54#ibcon#enter wrdev, iclass 10, count 0 2006.162.07:41:12.54#ibcon#first serial, iclass 10, count 0 2006.162.07:41:12.54#ibcon#enter sib2, iclass 10, count 0 2006.162.07:41:12.54#ibcon#flushed, iclass 10, count 0 2006.162.07:41:12.54#ibcon#about to write, iclass 10, count 0 2006.162.07:41:12.54#ibcon#wrote, iclass 10, count 0 2006.162.07:41:12.54#ibcon#about to read 3, iclass 10, count 0 2006.162.07:41:12.56#ibcon#read 3, iclass 10, count 0 2006.162.07:41:12.56#ibcon#about to read 4, iclass 10, count 0 2006.162.07:41:12.56#ibcon#read 4, iclass 10, count 0 2006.162.07:41:12.56#ibcon#about to read 5, iclass 10, count 0 2006.162.07:41:12.56#ibcon#read 5, iclass 10, count 0 2006.162.07:41:12.56#ibcon#about to read 6, iclass 10, count 0 2006.162.07:41:12.56#ibcon#read 6, iclass 10, count 0 2006.162.07:41:12.56#ibcon#end of sib2, iclass 10, count 0 2006.162.07:41:12.56#ibcon#*mode == 0, iclass 10, count 0 2006.162.07:41:12.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.162.07:41:12.56#ibcon#[27=USB\r\n] 2006.162.07:41:12.56#ibcon#*before write, iclass 10, count 0 2006.162.07:41:12.56#ibcon#enter sib2, iclass 10, count 0 2006.162.07:41:12.56#ibcon#flushed, iclass 10, count 0 2006.162.07:41:12.56#ibcon#about to write, iclass 10, count 0 2006.162.07:41:12.56#ibcon#wrote, iclass 10, count 0 2006.162.07:41:12.56#ibcon#about to read 3, iclass 10, count 0 2006.162.07:41:12.59#ibcon#read 3, iclass 10, count 0 2006.162.07:41:12.59#ibcon#about to read 4, iclass 10, count 0 2006.162.07:41:12.59#ibcon#read 4, iclass 10, count 0 2006.162.07:41:12.59#ibcon#about to read 5, iclass 10, count 0 2006.162.07:41:12.59#ibcon#read 5, iclass 10, count 0 2006.162.07:41:12.59#ibcon#about to read 6, iclass 10, count 0 2006.162.07:41:12.59#ibcon#read 6, iclass 10, count 0 2006.162.07:41:12.59#ibcon#end of sib2, iclass 10, count 0 2006.162.07:41:12.59#ibcon#*after write, iclass 10, count 0 2006.162.07:41:12.59#ibcon#*before return 0, iclass 10, count 0 2006.162.07:41:12.59#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:41:12.59#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:41:12.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.162.07:41:12.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.162.07:41:12.59$vc4f8/vblo=2,640.99 2006.162.07:41:12.59#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.162.07:41:12.59#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.162.07:41:12.59#ibcon#ireg 17 cls_cnt 0 2006.162.07:41:12.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:41:12.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:41:12.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:41:12.59#ibcon#enter wrdev, iclass 12, count 0 2006.162.07:41:12.59#ibcon#first serial, iclass 12, count 0 2006.162.07:41:12.59#ibcon#enter sib2, iclass 12, count 0 2006.162.07:41:12.59#ibcon#flushed, iclass 12, count 0 2006.162.07:41:12.59#ibcon#about to write, iclass 12, count 0 2006.162.07:41:12.59#ibcon#wrote, iclass 12, count 0 2006.162.07:41:12.59#ibcon#about to read 3, iclass 12, count 0 2006.162.07:41:12.61#ibcon#read 3, iclass 12, count 0 2006.162.07:41:12.61#ibcon#about to read 4, iclass 12, count 0 2006.162.07:41:12.61#ibcon#read 4, iclass 12, count 0 2006.162.07:41:12.61#ibcon#about to read 5, iclass 12, count 0 2006.162.07:41:12.61#ibcon#read 5, iclass 12, count 0 2006.162.07:41:12.61#ibcon#about to read 6, iclass 12, count 0 2006.162.07:41:12.61#ibcon#read 6, iclass 12, count 0 2006.162.07:41:12.61#ibcon#end of sib2, iclass 12, count 0 2006.162.07:41:12.61#ibcon#*mode == 0, iclass 12, count 0 2006.162.07:41:12.61#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.162.07:41:12.61#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.07:41:12.61#ibcon#*before write, iclass 12, count 0 2006.162.07:41:12.61#ibcon#enter sib2, iclass 12, count 0 2006.162.07:41:12.61#ibcon#flushed, iclass 12, count 0 2006.162.07:41:12.61#ibcon#about to write, iclass 12, count 0 2006.162.07:41:12.61#ibcon#wrote, iclass 12, count 0 2006.162.07:41:12.61#ibcon#about to read 3, iclass 12, count 0 2006.162.07:41:12.65#ibcon#read 3, iclass 12, count 0 2006.162.07:41:12.65#ibcon#about to read 4, iclass 12, count 0 2006.162.07:41:12.65#ibcon#read 4, iclass 12, count 0 2006.162.07:41:12.65#ibcon#about to read 5, iclass 12, count 0 2006.162.07:41:12.65#ibcon#read 5, iclass 12, count 0 2006.162.07:41:12.65#ibcon#about to read 6, iclass 12, count 0 2006.162.07:41:12.65#ibcon#read 6, iclass 12, count 0 2006.162.07:41:12.65#ibcon#end of sib2, iclass 12, count 0 2006.162.07:41:12.65#ibcon#*after write, iclass 12, count 0 2006.162.07:41:12.65#ibcon#*before return 0, iclass 12, count 0 2006.162.07:41:12.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:41:12.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:41:12.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.162.07:41:12.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.162.07:41:12.65$vc4f8/vb=2,4 2006.162.07:41:12.65#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.162.07:41:12.65#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.162.07:41:12.65#ibcon#ireg 11 cls_cnt 2 2006.162.07:41:12.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:41:12.71#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:41:12.71#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:41:12.71#ibcon#enter wrdev, iclass 14, count 2 2006.162.07:41:12.71#ibcon#first serial, iclass 14, count 2 2006.162.07:41:12.71#ibcon#enter sib2, iclass 14, count 2 2006.162.07:41:12.71#ibcon#flushed, iclass 14, count 2 2006.162.07:41:12.71#ibcon#about to write, iclass 14, count 2 2006.162.07:41:12.71#ibcon#wrote, iclass 14, count 2 2006.162.07:41:12.71#ibcon#about to read 3, iclass 14, count 2 2006.162.07:41:12.73#ibcon#read 3, iclass 14, count 2 2006.162.07:41:12.73#ibcon#about to read 4, iclass 14, count 2 2006.162.07:41:12.73#ibcon#read 4, iclass 14, count 2 2006.162.07:41:12.73#ibcon#about to read 5, iclass 14, count 2 2006.162.07:41:12.73#ibcon#read 5, iclass 14, count 2 2006.162.07:41:12.73#ibcon#about to read 6, iclass 14, count 2 2006.162.07:41:12.73#ibcon#read 6, iclass 14, count 2 2006.162.07:41:12.73#ibcon#end of sib2, iclass 14, count 2 2006.162.07:41:12.73#ibcon#*mode == 0, iclass 14, count 2 2006.162.07:41:12.73#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.162.07:41:12.73#ibcon#[27=AT02-04\r\n] 2006.162.07:41:12.73#ibcon#*before write, iclass 14, count 2 2006.162.07:41:12.73#ibcon#enter sib2, iclass 14, count 2 2006.162.07:41:12.73#ibcon#flushed, iclass 14, count 2 2006.162.07:41:12.73#ibcon#about to write, iclass 14, count 2 2006.162.07:41:12.73#ibcon#wrote, iclass 14, count 2 2006.162.07:41:12.73#ibcon#about to read 3, iclass 14, count 2 2006.162.07:41:12.76#ibcon#read 3, iclass 14, count 2 2006.162.07:41:12.76#ibcon#about to read 4, iclass 14, count 2 2006.162.07:41:12.76#ibcon#read 4, iclass 14, count 2 2006.162.07:41:12.76#ibcon#about to read 5, iclass 14, count 2 2006.162.07:41:12.76#ibcon#read 5, iclass 14, count 2 2006.162.07:41:12.76#ibcon#about to read 6, iclass 14, count 2 2006.162.07:41:12.76#ibcon#read 6, iclass 14, count 2 2006.162.07:41:12.76#ibcon#end of sib2, iclass 14, count 2 2006.162.07:41:12.76#ibcon#*after write, iclass 14, count 2 2006.162.07:41:12.76#ibcon#*before return 0, iclass 14, count 2 2006.162.07:41:12.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:41:12.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:41:12.76#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.162.07:41:12.76#ibcon#ireg 7 cls_cnt 0 2006.162.07:41:12.76#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:41:12.88#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:41:12.88#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:41:12.88#ibcon#enter wrdev, iclass 14, count 0 2006.162.07:41:12.88#ibcon#first serial, iclass 14, count 0 2006.162.07:41:12.88#ibcon#enter sib2, iclass 14, count 0 2006.162.07:41:12.88#ibcon#flushed, iclass 14, count 0 2006.162.07:41:12.88#ibcon#about to write, iclass 14, count 0 2006.162.07:41:12.88#ibcon#wrote, iclass 14, count 0 2006.162.07:41:12.88#ibcon#about to read 3, iclass 14, count 0 2006.162.07:41:12.90#ibcon#read 3, iclass 14, count 0 2006.162.07:41:12.90#ibcon#about to read 4, iclass 14, count 0 2006.162.07:41:12.90#ibcon#read 4, iclass 14, count 0 2006.162.07:41:12.90#ibcon#about to read 5, iclass 14, count 0 2006.162.07:41:12.90#ibcon#read 5, iclass 14, count 0 2006.162.07:41:12.90#ibcon#about to read 6, iclass 14, count 0 2006.162.07:41:12.90#ibcon#read 6, iclass 14, count 0 2006.162.07:41:12.90#ibcon#end of sib2, iclass 14, count 0 2006.162.07:41:12.90#ibcon#*mode == 0, iclass 14, count 0 2006.162.07:41:12.90#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.07:41:12.90#ibcon#[27=USB\r\n] 2006.162.07:41:12.90#ibcon#*before write, iclass 14, count 0 2006.162.07:41:12.90#ibcon#enter sib2, iclass 14, count 0 2006.162.07:41:12.90#ibcon#flushed, iclass 14, count 0 2006.162.07:41:12.90#ibcon#about to write, iclass 14, count 0 2006.162.07:41:12.90#ibcon#wrote, iclass 14, count 0 2006.162.07:41:12.90#ibcon#about to read 3, iclass 14, count 0 2006.162.07:41:12.93#ibcon#read 3, iclass 14, count 0 2006.162.07:41:12.93#ibcon#about to read 4, iclass 14, count 0 2006.162.07:41:12.93#ibcon#read 4, iclass 14, count 0 2006.162.07:41:12.93#ibcon#about to read 5, iclass 14, count 0 2006.162.07:41:12.93#ibcon#read 5, iclass 14, count 0 2006.162.07:41:12.93#ibcon#about to read 6, iclass 14, count 0 2006.162.07:41:12.93#ibcon#read 6, iclass 14, count 0 2006.162.07:41:12.93#ibcon#end of sib2, iclass 14, count 0 2006.162.07:41:12.93#ibcon#*after write, iclass 14, count 0 2006.162.07:41:12.93#ibcon#*before return 0, iclass 14, count 0 2006.162.07:41:12.93#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:41:12.93#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:41:12.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.07:41:12.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.07:41:12.93$vc4f8/vblo=3,656.99 2006.162.07:41:12.93#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.162.07:41:12.93#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.162.07:41:12.93#ibcon#ireg 17 cls_cnt 0 2006.162.07:41:12.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:41:12.93#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:41:12.93#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:41:12.93#ibcon#enter wrdev, iclass 16, count 0 2006.162.07:41:12.93#ibcon#first serial, iclass 16, count 0 2006.162.07:41:12.93#ibcon#enter sib2, iclass 16, count 0 2006.162.07:41:12.93#ibcon#flushed, iclass 16, count 0 2006.162.07:41:12.93#ibcon#about to write, iclass 16, count 0 2006.162.07:41:12.93#ibcon#wrote, iclass 16, count 0 2006.162.07:41:12.93#ibcon#about to read 3, iclass 16, count 0 2006.162.07:41:12.95#ibcon#read 3, iclass 16, count 0 2006.162.07:41:12.95#ibcon#about to read 4, iclass 16, count 0 2006.162.07:41:12.95#ibcon#read 4, iclass 16, count 0 2006.162.07:41:12.95#ibcon#about to read 5, iclass 16, count 0 2006.162.07:41:12.95#ibcon#read 5, iclass 16, count 0 2006.162.07:41:12.95#ibcon#about to read 6, iclass 16, count 0 2006.162.07:41:12.95#ibcon#read 6, iclass 16, count 0 2006.162.07:41:12.95#ibcon#end of sib2, iclass 16, count 0 2006.162.07:41:12.95#ibcon#*mode == 0, iclass 16, count 0 2006.162.07:41:12.95#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.162.07:41:12.95#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.07:41:12.95#ibcon#*before write, iclass 16, count 0 2006.162.07:41:12.95#ibcon#enter sib2, iclass 16, count 0 2006.162.07:41:12.95#ibcon#flushed, iclass 16, count 0 2006.162.07:41:12.95#ibcon#about to write, iclass 16, count 0 2006.162.07:41:12.95#ibcon#wrote, iclass 16, count 0 2006.162.07:41:12.95#ibcon#about to read 3, iclass 16, count 0 2006.162.07:41:12.99#ibcon#read 3, iclass 16, count 0 2006.162.07:41:12.99#ibcon#about to read 4, iclass 16, count 0 2006.162.07:41:12.99#ibcon#read 4, iclass 16, count 0 2006.162.07:41:12.99#ibcon#about to read 5, iclass 16, count 0 2006.162.07:41:12.99#ibcon#read 5, iclass 16, count 0 2006.162.07:41:12.99#ibcon#about to read 6, iclass 16, count 0 2006.162.07:41:12.99#ibcon#read 6, iclass 16, count 0 2006.162.07:41:12.99#ibcon#end of sib2, iclass 16, count 0 2006.162.07:41:12.99#ibcon#*after write, iclass 16, count 0 2006.162.07:41:12.99#ibcon#*before return 0, iclass 16, count 0 2006.162.07:41:12.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:41:12.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:41:12.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.162.07:41:12.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.162.07:41:12.99$vc4f8/vb=3,4 2006.162.07:41:12.99#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.162.07:41:12.99#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.162.07:41:12.99#ibcon#ireg 11 cls_cnt 2 2006.162.07:41:12.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:41:13.06#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:41:13.06#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:41:13.06#ibcon#enter wrdev, iclass 18, count 2 2006.162.07:41:13.06#ibcon#first serial, iclass 18, count 2 2006.162.07:41:13.06#ibcon#enter sib2, iclass 18, count 2 2006.162.07:41:13.06#ibcon#flushed, iclass 18, count 2 2006.162.07:41:13.06#ibcon#about to write, iclass 18, count 2 2006.162.07:41:13.06#ibcon#wrote, iclass 18, count 2 2006.162.07:41:13.06#ibcon#about to read 3, iclass 18, count 2 2006.162.07:41:13.07#ibcon#read 3, iclass 18, count 2 2006.162.07:41:13.07#ibcon#about to read 4, iclass 18, count 2 2006.162.07:41:13.07#ibcon#read 4, iclass 18, count 2 2006.162.07:41:13.07#ibcon#about to read 5, iclass 18, count 2 2006.162.07:41:13.07#ibcon#read 5, iclass 18, count 2 2006.162.07:41:13.07#ibcon#about to read 6, iclass 18, count 2 2006.162.07:41:13.07#ibcon#read 6, iclass 18, count 2 2006.162.07:41:13.07#ibcon#end of sib2, iclass 18, count 2 2006.162.07:41:13.07#ibcon#*mode == 0, iclass 18, count 2 2006.162.07:41:13.07#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.162.07:41:13.07#ibcon#[27=AT03-04\r\n] 2006.162.07:41:13.07#ibcon#*before write, iclass 18, count 2 2006.162.07:41:13.07#ibcon#enter sib2, iclass 18, count 2 2006.162.07:41:13.07#ibcon#flushed, iclass 18, count 2 2006.162.07:41:13.07#ibcon#about to write, iclass 18, count 2 2006.162.07:41:13.07#ibcon#wrote, iclass 18, count 2 2006.162.07:41:13.07#ibcon#about to read 3, iclass 18, count 2 2006.162.07:41:13.10#ibcon#read 3, iclass 18, count 2 2006.162.07:41:13.10#ibcon#about to read 4, iclass 18, count 2 2006.162.07:41:13.10#ibcon#read 4, iclass 18, count 2 2006.162.07:41:13.10#ibcon#about to read 5, iclass 18, count 2 2006.162.07:41:13.10#ibcon#read 5, iclass 18, count 2 2006.162.07:41:13.10#ibcon#about to read 6, iclass 18, count 2 2006.162.07:41:13.10#ibcon#read 6, iclass 18, count 2 2006.162.07:41:13.10#ibcon#end of sib2, iclass 18, count 2 2006.162.07:41:13.10#ibcon#*after write, iclass 18, count 2 2006.162.07:41:13.10#ibcon#*before return 0, iclass 18, count 2 2006.162.07:41:13.10#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:41:13.10#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:41:13.10#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.162.07:41:13.10#ibcon#ireg 7 cls_cnt 0 2006.162.07:41:13.10#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:41:13.22#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:41:13.22#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:41:13.22#ibcon#enter wrdev, iclass 18, count 0 2006.162.07:41:13.22#ibcon#first serial, iclass 18, count 0 2006.162.07:41:13.22#ibcon#enter sib2, iclass 18, count 0 2006.162.07:41:13.22#ibcon#flushed, iclass 18, count 0 2006.162.07:41:13.22#ibcon#about to write, iclass 18, count 0 2006.162.07:41:13.22#ibcon#wrote, iclass 18, count 0 2006.162.07:41:13.22#ibcon#about to read 3, iclass 18, count 0 2006.162.07:41:13.24#ibcon#read 3, iclass 18, count 0 2006.162.07:41:13.24#ibcon#about to read 4, iclass 18, count 0 2006.162.07:41:13.24#ibcon#read 4, iclass 18, count 0 2006.162.07:41:13.24#ibcon#about to read 5, iclass 18, count 0 2006.162.07:41:13.24#ibcon#read 5, iclass 18, count 0 2006.162.07:41:13.24#ibcon#about to read 6, iclass 18, count 0 2006.162.07:41:13.24#ibcon#read 6, iclass 18, count 0 2006.162.07:41:13.24#ibcon#end of sib2, iclass 18, count 0 2006.162.07:41:13.24#ibcon#*mode == 0, iclass 18, count 0 2006.162.07:41:13.24#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.162.07:41:13.24#ibcon#[27=USB\r\n] 2006.162.07:41:13.24#ibcon#*before write, iclass 18, count 0 2006.162.07:41:13.24#ibcon#enter sib2, iclass 18, count 0 2006.162.07:41:13.24#ibcon#flushed, iclass 18, count 0 2006.162.07:41:13.24#ibcon#about to write, iclass 18, count 0 2006.162.07:41:13.24#ibcon#wrote, iclass 18, count 0 2006.162.07:41:13.24#ibcon#about to read 3, iclass 18, count 0 2006.162.07:41:13.27#ibcon#read 3, iclass 18, count 0 2006.162.07:41:13.27#ibcon#about to read 4, iclass 18, count 0 2006.162.07:41:13.27#ibcon#read 4, iclass 18, count 0 2006.162.07:41:13.27#ibcon#about to read 5, iclass 18, count 0 2006.162.07:41:13.27#ibcon#read 5, iclass 18, count 0 2006.162.07:41:13.27#ibcon#about to read 6, iclass 18, count 0 2006.162.07:41:13.27#ibcon#read 6, iclass 18, count 0 2006.162.07:41:13.27#ibcon#end of sib2, iclass 18, count 0 2006.162.07:41:13.27#ibcon#*after write, iclass 18, count 0 2006.162.07:41:13.27#ibcon#*before return 0, iclass 18, count 0 2006.162.07:41:13.27#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:41:13.27#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:41:13.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.162.07:41:13.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.162.07:41:13.27$vc4f8/vblo=4,712.99 2006.162.07:41:13.27#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.162.07:41:13.27#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.162.07:41:13.27#ibcon#ireg 17 cls_cnt 0 2006.162.07:41:13.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:41:13.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:41:13.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:41:13.27#ibcon#enter wrdev, iclass 20, count 0 2006.162.07:41:13.27#ibcon#first serial, iclass 20, count 0 2006.162.07:41:13.27#ibcon#enter sib2, iclass 20, count 0 2006.162.07:41:13.27#ibcon#flushed, iclass 20, count 0 2006.162.07:41:13.27#ibcon#about to write, iclass 20, count 0 2006.162.07:41:13.27#ibcon#wrote, iclass 20, count 0 2006.162.07:41:13.27#ibcon#about to read 3, iclass 20, count 0 2006.162.07:41:13.29#ibcon#read 3, iclass 20, count 0 2006.162.07:41:13.29#ibcon#about to read 4, iclass 20, count 0 2006.162.07:41:13.29#ibcon#read 4, iclass 20, count 0 2006.162.07:41:13.29#ibcon#about to read 5, iclass 20, count 0 2006.162.07:41:13.29#ibcon#read 5, iclass 20, count 0 2006.162.07:41:13.29#ibcon#about to read 6, iclass 20, count 0 2006.162.07:41:13.29#ibcon#read 6, iclass 20, count 0 2006.162.07:41:13.29#ibcon#end of sib2, iclass 20, count 0 2006.162.07:41:13.29#ibcon#*mode == 0, iclass 20, count 0 2006.162.07:41:13.29#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.07:41:13.29#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.07:41:13.29#ibcon#*before write, iclass 20, count 0 2006.162.07:41:13.29#ibcon#enter sib2, iclass 20, count 0 2006.162.07:41:13.29#ibcon#flushed, iclass 20, count 0 2006.162.07:41:13.29#ibcon#about to write, iclass 20, count 0 2006.162.07:41:13.29#ibcon#wrote, iclass 20, count 0 2006.162.07:41:13.29#ibcon#about to read 3, iclass 20, count 0 2006.162.07:41:13.33#ibcon#read 3, iclass 20, count 0 2006.162.07:41:13.33#ibcon#about to read 4, iclass 20, count 0 2006.162.07:41:13.33#ibcon#read 4, iclass 20, count 0 2006.162.07:41:13.33#ibcon#about to read 5, iclass 20, count 0 2006.162.07:41:13.33#ibcon#read 5, iclass 20, count 0 2006.162.07:41:13.33#ibcon#about to read 6, iclass 20, count 0 2006.162.07:41:13.33#ibcon#read 6, iclass 20, count 0 2006.162.07:41:13.33#ibcon#end of sib2, iclass 20, count 0 2006.162.07:41:13.33#ibcon#*after write, iclass 20, count 0 2006.162.07:41:13.33#ibcon#*before return 0, iclass 20, count 0 2006.162.07:41:13.33#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:41:13.33#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:41:13.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.07:41:13.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.07:41:13.33$vc4f8/vb=4,4 2006.162.07:41:13.33#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.162.07:41:13.33#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.162.07:41:13.33#ibcon#ireg 11 cls_cnt 2 2006.162.07:41:13.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:41:13.39#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:41:13.39#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:41:13.39#ibcon#enter wrdev, iclass 22, count 2 2006.162.07:41:13.39#ibcon#first serial, iclass 22, count 2 2006.162.07:41:13.39#ibcon#enter sib2, iclass 22, count 2 2006.162.07:41:13.39#ibcon#flushed, iclass 22, count 2 2006.162.07:41:13.39#ibcon#about to write, iclass 22, count 2 2006.162.07:41:13.39#ibcon#wrote, iclass 22, count 2 2006.162.07:41:13.39#ibcon#about to read 3, iclass 22, count 2 2006.162.07:41:13.41#ibcon#read 3, iclass 22, count 2 2006.162.07:41:13.41#ibcon#about to read 4, iclass 22, count 2 2006.162.07:41:13.41#ibcon#read 4, iclass 22, count 2 2006.162.07:41:13.41#ibcon#about to read 5, iclass 22, count 2 2006.162.07:41:13.41#ibcon#read 5, iclass 22, count 2 2006.162.07:41:13.41#ibcon#about to read 6, iclass 22, count 2 2006.162.07:41:13.41#ibcon#read 6, iclass 22, count 2 2006.162.07:41:13.41#ibcon#end of sib2, iclass 22, count 2 2006.162.07:41:13.41#ibcon#*mode == 0, iclass 22, count 2 2006.162.07:41:13.41#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.162.07:41:13.41#ibcon#[27=AT04-04\r\n] 2006.162.07:41:13.41#ibcon#*before write, iclass 22, count 2 2006.162.07:41:13.41#ibcon#enter sib2, iclass 22, count 2 2006.162.07:41:13.41#ibcon#flushed, iclass 22, count 2 2006.162.07:41:13.41#ibcon#about to write, iclass 22, count 2 2006.162.07:41:13.41#ibcon#wrote, iclass 22, count 2 2006.162.07:41:13.41#ibcon#about to read 3, iclass 22, count 2 2006.162.07:41:13.44#ibcon#read 3, iclass 22, count 2 2006.162.07:41:13.44#ibcon#about to read 4, iclass 22, count 2 2006.162.07:41:13.44#ibcon#read 4, iclass 22, count 2 2006.162.07:41:13.44#ibcon#about to read 5, iclass 22, count 2 2006.162.07:41:13.44#ibcon#read 5, iclass 22, count 2 2006.162.07:41:13.44#ibcon#about to read 6, iclass 22, count 2 2006.162.07:41:13.44#ibcon#read 6, iclass 22, count 2 2006.162.07:41:13.44#ibcon#end of sib2, iclass 22, count 2 2006.162.07:41:13.44#ibcon#*after write, iclass 22, count 2 2006.162.07:41:13.44#ibcon#*before return 0, iclass 22, count 2 2006.162.07:41:13.44#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:41:13.44#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:41:13.44#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.162.07:41:13.44#ibcon#ireg 7 cls_cnt 0 2006.162.07:41:13.44#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:41:13.56#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:41:13.56#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:41:13.56#ibcon#enter wrdev, iclass 22, count 0 2006.162.07:41:13.56#ibcon#first serial, iclass 22, count 0 2006.162.07:41:13.56#ibcon#enter sib2, iclass 22, count 0 2006.162.07:41:13.56#ibcon#flushed, iclass 22, count 0 2006.162.07:41:13.56#ibcon#about to write, iclass 22, count 0 2006.162.07:41:13.56#ibcon#wrote, iclass 22, count 0 2006.162.07:41:13.56#ibcon#about to read 3, iclass 22, count 0 2006.162.07:41:13.58#ibcon#read 3, iclass 22, count 0 2006.162.07:41:13.58#ibcon#about to read 4, iclass 22, count 0 2006.162.07:41:13.58#ibcon#read 4, iclass 22, count 0 2006.162.07:41:13.58#ibcon#about to read 5, iclass 22, count 0 2006.162.07:41:13.58#ibcon#read 5, iclass 22, count 0 2006.162.07:41:13.58#ibcon#about to read 6, iclass 22, count 0 2006.162.07:41:13.58#ibcon#read 6, iclass 22, count 0 2006.162.07:41:13.58#ibcon#end of sib2, iclass 22, count 0 2006.162.07:41:13.58#ibcon#*mode == 0, iclass 22, count 0 2006.162.07:41:13.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.07:41:13.58#ibcon#[27=USB\r\n] 2006.162.07:41:13.58#ibcon#*before write, iclass 22, count 0 2006.162.07:41:13.58#ibcon#enter sib2, iclass 22, count 0 2006.162.07:41:13.58#ibcon#flushed, iclass 22, count 0 2006.162.07:41:13.58#ibcon#about to write, iclass 22, count 0 2006.162.07:41:13.58#ibcon#wrote, iclass 22, count 0 2006.162.07:41:13.58#ibcon#about to read 3, iclass 22, count 0 2006.162.07:41:13.61#ibcon#read 3, iclass 22, count 0 2006.162.07:41:13.61#ibcon#about to read 4, iclass 22, count 0 2006.162.07:41:13.61#ibcon#read 4, iclass 22, count 0 2006.162.07:41:13.61#ibcon#about to read 5, iclass 22, count 0 2006.162.07:41:13.61#ibcon#read 5, iclass 22, count 0 2006.162.07:41:13.61#ibcon#about to read 6, iclass 22, count 0 2006.162.07:41:13.61#ibcon#read 6, iclass 22, count 0 2006.162.07:41:13.61#ibcon#end of sib2, iclass 22, count 0 2006.162.07:41:13.61#ibcon#*after write, iclass 22, count 0 2006.162.07:41:13.61#ibcon#*before return 0, iclass 22, count 0 2006.162.07:41:13.61#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:41:13.61#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:41:13.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.07:41:13.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.07:41:13.61$vc4f8/vblo=5,744.99 2006.162.07:41:13.61#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.162.07:41:13.61#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.162.07:41:13.61#ibcon#ireg 17 cls_cnt 0 2006.162.07:41:13.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:41:13.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:41:13.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:41:13.61#ibcon#enter wrdev, iclass 24, count 0 2006.162.07:41:13.61#ibcon#first serial, iclass 24, count 0 2006.162.07:41:13.61#ibcon#enter sib2, iclass 24, count 0 2006.162.07:41:13.61#ibcon#flushed, iclass 24, count 0 2006.162.07:41:13.61#ibcon#about to write, iclass 24, count 0 2006.162.07:41:13.61#ibcon#wrote, iclass 24, count 0 2006.162.07:41:13.61#ibcon#about to read 3, iclass 24, count 0 2006.162.07:41:13.63#ibcon#read 3, iclass 24, count 0 2006.162.07:41:13.63#ibcon#about to read 4, iclass 24, count 0 2006.162.07:41:13.63#ibcon#read 4, iclass 24, count 0 2006.162.07:41:13.63#ibcon#about to read 5, iclass 24, count 0 2006.162.07:41:13.63#ibcon#read 5, iclass 24, count 0 2006.162.07:41:13.63#ibcon#about to read 6, iclass 24, count 0 2006.162.07:41:13.63#ibcon#read 6, iclass 24, count 0 2006.162.07:41:13.63#ibcon#end of sib2, iclass 24, count 0 2006.162.07:41:13.63#ibcon#*mode == 0, iclass 24, count 0 2006.162.07:41:13.63#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.07:41:13.63#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.07:41:13.63#ibcon#*before write, iclass 24, count 0 2006.162.07:41:13.63#ibcon#enter sib2, iclass 24, count 0 2006.162.07:41:13.63#ibcon#flushed, iclass 24, count 0 2006.162.07:41:13.63#ibcon#about to write, iclass 24, count 0 2006.162.07:41:13.63#ibcon#wrote, iclass 24, count 0 2006.162.07:41:13.63#ibcon#about to read 3, iclass 24, count 0 2006.162.07:41:13.67#ibcon#read 3, iclass 24, count 0 2006.162.07:41:13.67#ibcon#about to read 4, iclass 24, count 0 2006.162.07:41:13.67#ibcon#read 4, iclass 24, count 0 2006.162.07:41:13.67#ibcon#about to read 5, iclass 24, count 0 2006.162.07:41:13.67#ibcon#read 5, iclass 24, count 0 2006.162.07:41:13.67#ibcon#about to read 6, iclass 24, count 0 2006.162.07:41:13.67#ibcon#read 6, iclass 24, count 0 2006.162.07:41:13.67#ibcon#end of sib2, iclass 24, count 0 2006.162.07:41:13.67#ibcon#*after write, iclass 24, count 0 2006.162.07:41:13.67#ibcon#*before return 0, iclass 24, count 0 2006.162.07:41:13.67#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:41:13.67#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:41:13.67#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.07:41:13.67#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.07:41:13.67$vc4f8/vb=5,4 2006.162.07:41:13.67#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.162.07:41:13.67#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.162.07:41:13.67#ibcon#ireg 11 cls_cnt 2 2006.162.07:41:13.67#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:41:13.73#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:41:13.73#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:41:13.73#ibcon#enter wrdev, iclass 26, count 2 2006.162.07:41:13.73#ibcon#first serial, iclass 26, count 2 2006.162.07:41:13.73#ibcon#enter sib2, iclass 26, count 2 2006.162.07:41:13.73#ibcon#flushed, iclass 26, count 2 2006.162.07:41:13.73#ibcon#about to write, iclass 26, count 2 2006.162.07:41:13.73#ibcon#wrote, iclass 26, count 2 2006.162.07:41:13.73#ibcon#about to read 3, iclass 26, count 2 2006.162.07:41:13.76#ibcon#read 3, iclass 26, count 2 2006.162.07:41:13.76#ibcon#about to read 4, iclass 26, count 2 2006.162.07:41:13.76#ibcon#read 4, iclass 26, count 2 2006.162.07:41:13.76#ibcon#about to read 5, iclass 26, count 2 2006.162.07:41:13.76#ibcon#read 5, iclass 26, count 2 2006.162.07:41:13.76#ibcon#about to read 6, iclass 26, count 2 2006.162.07:41:13.76#ibcon#read 6, iclass 26, count 2 2006.162.07:41:13.76#ibcon#end of sib2, iclass 26, count 2 2006.162.07:41:13.76#ibcon#*mode == 0, iclass 26, count 2 2006.162.07:41:13.76#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.162.07:41:13.76#ibcon#[27=AT05-04\r\n] 2006.162.07:41:13.76#ibcon#*before write, iclass 26, count 2 2006.162.07:41:13.76#ibcon#enter sib2, iclass 26, count 2 2006.162.07:41:13.76#ibcon#flushed, iclass 26, count 2 2006.162.07:41:13.76#ibcon#about to write, iclass 26, count 2 2006.162.07:41:13.76#ibcon#wrote, iclass 26, count 2 2006.162.07:41:13.76#ibcon#about to read 3, iclass 26, count 2 2006.162.07:41:13.79#ibcon#read 3, iclass 26, count 2 2006.162.07:41:13.79#ibcon#about to read 4, iclass 26, count 2 2006.162.07:41:13.79#ibcon#read 4, iclass 26, count 2 2006.162.07:41:13.79#ibcon#about to read 5, iclass 26, count 2 2006.162.07:41:13.79#ibcon#read 5, iclass 26, count 2 2006.162.07:41:13.79#ibcon#about to read 6, iclass 26, count 2 2006.162.07:41:13.79#ibcon#read 6, iclass 26, count 2 2006.162.07:41:13.79#ibcon#end of sib2, iclass 26, count 2 2006.162.07:41:13.79#ibcon#*after write, iclass 26, count 2 2006.162.07:41:13.79#ibcon#*before return 0, iclass 26, count 2 2006.162.07:41:13.79#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:41:13.79#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:41:13.79#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.162.07:41:13.79#ibcon#ireg 7 cls_cnt 0 2006.162.07:41:13.79#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:41:13.91#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:41:13.91#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:41:13.91#ibcon#enter wrdev, iclass 26, count 0 2006.162.07:41:13.91#ibcon#first serial, iclass 26, count 0 2006.162.07:41:13.91#ibcon#enter sib2, iclass 26, count 0 2006.162.07:41:13.91#ibcon#flushed, iclass 26, count 0 2006.162.07:41:13.91#ibcon#about to write, iclass 26, count 0 2006.162.07:41:13.91#ibcon#wrote, iclass 26, count 0 2006.162.07:41:13.91#ibcon#about to read 3, iclass 26, count 0 2006.162.07:41:13.93#ibcon#read 3, iclass 26, count 0 2006.162.07:41:13.93#ibcon#about to read 4, iclass 26, count 0 2006.162.07:41:13.93#ibcon#read 4, iclass 26, count 0 2006.162.07:41:13.93#ibcon#about to read 5, iclass 26, count 0 2006.162.07:41:13.93#ibcon#read 5, iclass 26, count 0 2006.162.07:41:13.93#ibcon#about to read 6, iclass 26, count 0 2006.162.07:41:13.93#ibcon#read 6, iclass 26, count 0 2006.162.07:41:13.93#ibcon#end of sib2, iclass 26, count 0 2006.162.07:41:13.93#ibcon#*mode == 0, iclass 26, count 0 2006.162.07:41:13.93#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.162.07:41:13.93#ibcon#[27=USB\r\n] 2006.162.07:41:13.93#ibcon#*before write, iclass 26, count 0 2006.162.07:41:13.93#ibcon#enter sib2, iclass 26, count 0 2006.162.07:41:13.93#ibcon#flushed, iclass 26, count 0 2006.162.07:41:13.93#ibcon#about to write, iclass 26, count 0 2006.162.07:41:13.93#ibcon#wrote, iclass 26, count 0 2006.162.07:41:13.93#ibcon#about to read 3, iclass 26, count 0 2006.162.07:41:13.96#ibcon#read 3, iclass 26, count 0 2006.162.07:41:13.96#ibcon#about to read 4, iclass 26, count 0 2006.162.07:41:13.96#ibcon#read 4, iclass 26, count 0 2006.162.07:41:13.96#ibcon#about to read 5, iclass 26, count 0 2006.162.07:41:13.96#ibcon#read 5, iclass 26, count 0 2006.162.07:41:13.96#ibcon#about to read 6, iclass 26, count 0 2006.162.07:41:13.96#ibcon#read 6, iclass 26, count 0 2006.162.07:41:13.96#ibcon#end of sib2, iclass 26, count 0 2006.162.07:41:13.96#ibcon#*after write, iclass 26, count 0 2006.162.07:41:13.96#ibcon#*before return 0, iclass 26, count 0 2006.162.07:41:13.96#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:41:13.96#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:41:13.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.162.07:41:13.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.162.07:41:13.96$vc4f8/vblo=6,752.99 2006.162.07:41:13.96#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.162.07:41:13.96#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.162.07:41:13.96#ibcon#ireg 17 cls_cnt 0 2006.162.07:41:13.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:41:13.96#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:41:13.96#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:41:13.96#ibcon#enter wrdev, iclass 28, count 0 2006.162.07:41:13.96#ibcon#first serial, iclass 28, count 0 2006.162.07:41:13.96#ibcon#enter sib2, iclass 28, count 0 2006.162.07:41:13.96#ibcon#flushed, iclass 28, count 0 2006.162.07:41:13.96#ibcon#about to write, iclass 28, count 0 2006.162.07:41:13.96#ibcon#wrote, iclass 28, count 0 2006.162.07:41:13.96#ibcon#about to read 3, iclass 28, count 0 2006.162.07:41:13.98#ibcon#read 3, iclass 28, count 0 2006.162.07:41:13.98#ibcon#about to read 4, iclass 28, count 0 2006.162.07:41:13.98#ibcon#read 4, iclass 28, count 0 2006.162.07:41:13.98#ibcon#about to read 5, iclass 28, count 0 2006.162.07:41:13.98#ibcon#read 5, iclass 28, count 0 2006.162.07:41:13.98#ibcon#about to read 6, iclass 28, count 0 2006.162.07:41:13.98#ibcon#read 6, iclass 28, count 0 2006.162.07:41:13.98#ibcon#end of sib2, iclass 28, count 0 2006.162.07:41:13.98#ibcon#*mode == 0, iclass 28, count 0 2006.162.07:41:13.98#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.162.07:41:13.98#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.07:41:13.98#ibcon#*before write, iclass 28, count 0 2006.162.07:41:13.98#ibcon#enter sib2, iclass 28, count 0 2006.162.07:41:13.98#ibcon#flushed, iclass 28, count 0 2006.162.07:41:13.98#ibcon#about to write, iclass 28, count 0 2006.162.07:41:13.98#ibcon#wrote, iclass 28, count 0 2006.162.07:41:13.98#ibcon#about to read 3, iclass 28, count 0 2006.162.07:41:14.02#ibcon#read 3, iclass 28, count 0 2006.162.07:41:14.02#ibcon#about to read 4, iclass 28, count 0 2006.162.07:41:14.02#ibcon#read 4, iclass 28, count 0 2006.162.07:41:14.02#ibcon#about to read 5, iclass 28, count 0 2006.162.07:41:14.02#ibcon#read 5, iclass 28, count 0 2006.162.07:41:14.02#ibcon#about to read 6, iclass 28, count 0 2006.162.07:41:14.02#ibcon#read 6, iclass 28, count 0 2006.162.07:41:14.02#ibcon#end of sib2, iclass 28, count 0 2006.162.07:41:14.02#ibcon#*after write, iclass 28, count 0 2006.162.07:41:14.02#ibcon#*before return 0, iclass 28, count 0 2006.162.07:41:14.02#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:41:14.02#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:41:14.02#ibcon#about to clear, iclass 28 cls_cnt 0 2006.162.07:41:14.02#ibcon#cleared, iclass 28 cls_cnt 0 2006.162.07:41:14.02$vc4f8/vb=6,4 2006.162.07:41:14.02#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.162.07:41:14.02#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.162.07:41:14.02#ibcon#ireg 11 cls_cnt 2 2006.162.07:41:14.02#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:41:14.08#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:41:14.08#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:41:14.08#ibcon#enter wrdev, iclass 30, count 2 2006.162.07:41:14.08#ibcon#first serial, iclass 30, count 2 2006.162.07:41:14.08#ibcon#enter sib2, iclass 30, count 2 2006.162.07:41:14.08#ibcon#flushed, iclass 30, count 2 2006.162.07:41:14.08#ibcon#about to write, iclass 30, count 2 2006.162.07:41:14.08#ibcon#wrote, iclass 30, count 2 2006.162.07:41:14.08#ibcon#about to read 3, iclass 30, count 2 2006.162.07:41:14.10#ibcon#read 3, iclass 30, count 2 2006.162.07:41:14.10#ibcon#about to read 4, iclass 30, count 2 2006.162.07:41:14.10#ibcon#read 4, iclass 30, count 2 2006.162.07:41:14.10#ibcon#about to read 5, iclass 30, count 2 2006.162.07:41:14.10#ibcon#read 5, iclass 30, count 2 2006.162.07:41:14.10#ibcon#about to read 6, iclass 30, count 2 2006.162.07:41:14.10#ibcon#read 6, iclass 30, count 2 2006.162.07:41:14.10#ibcon#end of sib2, iclass 30, count 2 2006.162.07:41:14.10#ibcon#*mode == 0, iclass 30, count 2 2006.162.07:41:14.10#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.162.07:41:14.10#ibcon#[27=AT06-04\r\n] 2006.162.07:41:14.10#ibcon#*before write, iclass 30, count 2 2006.162.07:41:14.10#ibcon#enter sib2, iclass 30, count 2 2006.162.07:41:14.10#ibcon#flushed, iclass 30, count 2 2006.162.07:41:14.10#ibcon#about to write, iclass 30, count 2 2006.162.07:41:14.10#ibcon#wrote, iclass 30, count 2 2006.162.07:41:14.10#ibcon#about to read 3, iclass 30, count 2 2006.162.07:41:14.13#ibcon#read 3, iclass 30, count 2 2006.162.07:41:14.13#ibcon#about to read 4, iclass 30, count 2 2006.162.07:41:14.13#ibcon#read 4, iclass 30, count 2 2006.162.07:41:14.13#ibcon#about to read 5, iclass 30, count 2 2006.162.07:41:14.13#ibcon#read 5, iclass 30, count 2 2006.162.07:41:14.13#ibcon#about to read 6, iclass 30, count 2 2006.162.07:41:14.13#ibcon#read 6, iclass 30, count 2 2006.162.07:41:14.13#ibcon#end of sib2, iclass 30, count 2 2006.162.07:41:14.13#ibcon#*after write, iclass 30, count 2 2006.162.07:41:14.13#ibcon#*before return 0, iclass 30, count 2 2006.162.07:41:14.13#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:41:14.13#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:41:14.13#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.162.07:41:14.13#ibcon#ireg 7 cls_cnt 0 2006.162.07:41:14.13#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:41:14.25#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:41:14.25#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:41:14.25#ibcon#enter wrdev, iclass 30, count 0 2006.162.07:41:14.25#ibcon#first serial, iclass 30, count 0 2006.162.07:41:14.25#ibcon#enter sib2, iclass 30, count 0 2006.162.07:41:14.25#ibcon#flushed, iclass 30, count 0 2006.162.07:41:14.25#ibcon#about to write, iclass 30, count 0 2006.162.07:41:14.25#ibcon#wrote, iclass 30, count 0 2006.162.07:41:14.25#ibcon#about to read 3, iclass 30, count 0 2006.162.07:41:14.27#ibcon#read 3, iclass 30, count 0 2006.162.07:41:14.27#ibcon#about to read 4, iclass 30, count 0 2006.162.07:41:14.27#ibcon#read 4, iclass 30, count 0 2006.162.07:41:14.27#ibcon#about to read 5, iclass 30, count 0 2006.162.07:41:14.27#ibcon#read 5, iclass 30, count 0 2006.162.07:41:14.27#ibcon#about to read 6, iclass 30, count 0 2006.162.07:41:14.27#ibcon#read 6, iclass 30, count 0 2006.162.07:41:14.27#ibcon#end of sib2, iclass 30, count 0 2006.162.07:41:14.27#ibcon#*mode == 0, iclass 30, count 0 2006.162.07:41:14.27#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.162.07:41:14.27#ibcon#[27=USB\r\n] 2006.162.07:41:14.27#ibcon#*before write, iclass 30, count 0 2006.162.07:41:14.27#ibcon#enter sib2, iclass 30, count 0 2006.162.07:41:14.27#ibcon#flushed, iclass 30, count 0 2006.162.07:41:14.27#ibcon#about to write, iclass 30, count 0 2006.162.07:41:14.27#ibcon#wrote, iclass 30, count 0 2006.162.07:41:14.27#ibcon#about to read 3, iclass 30, count 0 2006.162.07:41:14.30#ibcon#read 3, iclass 30, count 0 2006.162.07:41:14.30#ibcon#about to read 4, iclass 30, count 0 2006.162.07:41:14.30#ibcon#read 4, iclass 30, count 0 2006.162.07:41:14.30#ibcon#about to read 5, iclass 30, count 0 2006.162.07:41:14.30#ibcon#read 5, iclass 30, count 0 2006.162.07:41:14.30#ibcon#about to read 6, iclass 30, count 0 2006.162.07:41:14.30#ibcon#read 6, iclass 30, count 0 2006.162.07:41:14.30#ibcon#end of sib2, iclass 30, count 0 2006.162.07:41:14.30#ibcon#*after write, iclass 30, count 0 2006.162.07:41:14.30#ibcon#*before return 0, iclass 30, count 0 2006.162.07:41:14.30#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:41:14.30#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:41:14.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.162.07:41:14.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.162.07:41:14.30$vc4f8/vabw=wide 2006.162.07:41:14.30#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.162.07:41:14.30#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.162.07:41:14.30#ibcon#ireg 8 cls_cnt 0 2006.162.07:41:14.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:41:14.30#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:41:14.30#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:41:14.30#ibcon#enter wrdev, iclass 32, count 0 2006.162.07:41:14.30#ibcon#first serial, iclass 32, count 0 2006.162.07:41:14.30#ibcon#enter sib2, iclass 32, count 0 2006.162.07:41:14.30#ibcon#flushed, iclass 32, count 0 2006.162.07:41:14.30#ibcon#about to write, iclass 32, count 0 2006.162.07:41:14.30#ibcon#wrote, iclass 32, count 0 2006.162.07:41:14.30#ibcon#about to read 3, iclass 32, count 0 2006.162.07:41:14.32#ibcon#read 3, iclass 32, count 0 2006.162.07:41:14.32#ibcon#about to read 4, iclass 32, count 0 2006.162.07:41:14.32#ibcon#read 4, iclass 32, count 0 2006.162.07:41:14.32#ibcon#about to read 5, iclass 32, count 0 2006.162.07:41:14.32#ibcon#read 5, iclass 32, count 0 2006.162.07:41:14.32#ibcon#about to read 6, iclass 32, count 0 2006.162.07:41:14.32#ibcon#read 6, iclass 32, count 0 2006.162.07:41:14.32#ibcon#end of sib2, iclass 32, count 0 2006.162.07:41:14.32#ibcon#*mode == 0, iclass 32, count 0 2006.162.07:41:14.32#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.162.07:41:14.32#ibcon#[25=BW32\r\n] 2006.162.07:41:14.32#ibcon#*before write, iclass 32, count 0 2006.162.07:41:14.32#ibcon#enter sib2, iclass 32, count 0 2006.162.07:41:14.32#ibcon#flushed, iclass 32, count 0 2006.162.07:41:14.32#ibcon#about to write, iclass 32, count 0 2006.162.07:41:14.32#ibcon#wrote, iclass 32, count 0 2006.162.07:41:14.32#ibcon#about to read 3, iclass 32, count 0 2006.162.07:41:14.35#ibcon#read 3, iclass 32, count 0 2006.162.07:41:14.35#ibcon#about to read 4, iclass 32, count 0 2006.162.07:41:14.35#ibcon#read 4, iclass 32, count 0 2006.162.07:41:14.35#ibcon#about to read 5, iclass 32, count 0 2006.162.07:41:14.35#ibcon#read 5, iclass 32, count 0 2006.162.07:41:14.35#ibcon#about to read 6, iclass 32, count 0 2006.162.07:41:14.35#ibcon#read 6, iclass 32, count 0 2006.162.07:41:14.35#ibcon#end of sib2, iclass 32, count 0 2006.162.07:41:14.35#ibcon#*after write, iclass 32, count 0 2006.162.07:41:14.35#ibcon#*before return 0, iclass 32, count 0 2006.162.07:41:14.35#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:41:14.35#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:41:14.35#ibcon#about to clear, iclass 32 cls_cnt 0 2006.162.07:41:14.35#ibcon#cleared, iclass 32 cls_cnt 0 2006.162.07:41:14.35$vc4f8/vbbw=wide 2006.162.07:41:14.35#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.162.07:41:14.35#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.162.07:41:14.35#ibcon#ireg 8 cls_cnt 0 2006.162.07:41:14.35#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.162.07:41:14.42#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.162.07:41:14.42#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.162.07:41:14.42#ibcon#enter wrdev, iclass 34, count 0 2006.162.07:41:14.42#ibcon#first serial, iclass 34, count 0 2006.162.07:41:14.42#ibcon#enter sib2, iclass 34, count 0 2006.162.07:41:14.42#ibcon#flushed, iclass 34, count 0 2006.162.07:41:14.42#ibcon#about to write, iclass 34, count 0 2006.162.07:41:14.42#ibcon#wrote, iclass 34, count 0 2006.162.07:41:14.42#ibcon#about to read 3, iclass 34, count 0 2006.162.07:41:14.44#ibcon#read 3, iclass 34, count 0 2006.162.07:41:14.44#ibcon#about to read 4, iclass 34, count 0 2006.162.07:41:14.44#ibcon#read 4, iclass 34, count 0 2006.162.07:41:14.44#ibcon#about to read 5, iclass 34, count 0 2006.162.07:41:14.44#ibcon#read 5, iclass 34, count 0 2006.162.07:41:14.44#ibcon#about to read 6, iclass 34, count 0 2006.162.07:41:14.44#ibcon#read 6, iclass 34, count 0 2006.162.07:41:14.44#ibcon#end of sib2, iclass 34, count 0 2006.162.07:41:14.44#ibcon#*mode == 0, iclass 34, count 0 2006.162.07:41:14.44#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.162.07:41:14.44#ibcon#[27=BW32\r\n] 2006.162.07:41:14.44#ibcon#*before write, iclass 34, count 0 2006.162.07:41:14.44#ibcon#enter sib2, iclass 34, count 0 2006.162.07:41:14.44#ibcon#flushed, iclass 34, count 0 2006.162.07:41:14.44#ibcon#about to write, iclass 34, count 0 2006.162.07:41:14.44#ibcon#wrote, iclass 34, count 0 2006.162.07:41:14.44#ibcon#about to read 3, iclass 34, count 0 2006.162.07:41:14.47#ibcon#read 3, iclass 34, count 0 2006.162.07:41:14.47#ibcon#about to read 4, iclass 34, count 0 2006.162.07:41:14.47#ibcon#read 4, iclass 34, count 0 2006.162.07:41:14.47#ibcon#about to read 5, iclass 34, count 0 2006.162.07:41:14.47#ibcon#read 5, iclass 34, count 0 2006.162.07:41:14.47#ibcon#about to read 6, iclass 34, count 0 2006.162.07:41:14.47#ibcon#read 6, iclass 34, count 0 2006.162.07:41:14.47#ibcon#end of sib2, iclass 34, count 0 2006.162.07:41:14.47#ibcon#*after write, iclass 34, count 0 2006.162.07:41:14.47#ibcon#*before return 0, iclass 34, count 0 2006.162.07:41:14.47#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.162.07:41:14.47#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.162.07:41:14.47#ibcon#about to clear, iclass 34 cls_cnt 0 2006.162.07:41:14.47#ibcon#cleared, iclass 34 cls_cnt 0 2006.162.07:41:14.47$4f8m12a/ifd4f 2006.162.07:41:14.47$ifd4f/lo= 2006.162.07:41:14.47$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.07:41:14.47$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.07:41:14.47$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.07:41:14.47$ifd4f/patch= 2006.162.07:41:14.47$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.07:41:14.47$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.07:41:14.47$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.07:41:14.47$4f8m12a/"form=m,16.000,1:2 2006.162.07:41:14.47$4f8m12a/"tpicd 2006.162.07:41:14.47$4f8m12a/echo=off 2006.162.07:41:14.47$4f8m12a/xlog=off 2006.162.07:41:14.47:!2006.162.07:41:40 2006.162.07:41:24.13#trakl#Source acquired 2006.162.07:41:25.13#flagr#flagr/antenna,acquired 2006.162.07:41:40.00:preob 2006.162.07:41:41.13/onsource/TRACKING 2006.162.07:41:41.13:!2006.162.07:41:50 2006.162.07:41:50.00:data_valid=on 2006.162.07:41:50.00:midob 2006.162.07:41:50.13/onsource/TRACKING 2006.162.07:41:50.13/wx/17.92,1007.2,100 2006.162.07:41:50.24/cable/+6.5336E-03 2006.162.07:41:51.33/va/01,08,usb,yes,38,40 2006.162.07:41:51.33/va/02,07,usb,yes,38,40 2006.162.07:41:51.33/va/03,06,usb,yes,40,41 2006.162.07:41:51.33/va/04,07,usb,yes,39,42 2006.162.07:41:51.33/va/05,07,usb,yes,42,44 2006.162.07:41:51.33/va/06,06,usb,yes,41,41 2006.162.07:41:51.33/va/07,06,usb,yes,42,41 2006.162.07:41:51.33/va/08,07,usb,yes,39,39 2006.162.07:41:51.56/valo/01,532.99,yes,locked 2006.162.07:41:51.56/valo/02,572.99,yes,locked 2006.162.07:41:51.56/valo/03,672.99,yes,locked 2006.162.07:41:51.56/valo/04,832.99,yes,locked 2006.162.07:41:51.56/valo/05,652.99,yes,locked 2006.162.07:41:51.56/valo/06,772.99,yes,locked 2006.162.07:41:51.56/valo/07,832.99,yes,locked 2006.162.07:41:51.56/valo/08,852.99,yes,locked 2006.162.07:41:52.65/vb/01,04,usb,yes,29,28 2006.162.07:41:52.65/vb/02,04,usb,yes,31,33 2006.162.07:41:52.65/vb/03,04,usb,yes,27,31 2006.162.07:41:52.65/vb/04,04,usb,yes,28,29 2006.162.07:41:52.65/vb/05,04,usb,yes,27,31 2006.162.07:41:52.65/vb/06,04,usb,yes,28,31 2006.162.07:41:52.65/vb/07,04,usb,yes,30,30 2006.162.07:41:52.65/vb/08,04,usb,yes,27,31 2006.162.07:41:52.88/vblo/01,632.99,yes,locked 2006.162.07:41:52.88/vblo/02,640.99,yes,locked 2006.162.07:41:52.88/vblo/03,656.99,yes,locked 2006.162.07:41:52.88/vblo/04,712.99,yes,locked 2006.162.07:41:52.88/vblo/05,744.99,yes,locked 2006.162.07:41:52.88/vblo/06,752.99,yes,locked 2006.162.07:41:52.88/vblo/07,734.99,yes,locked 2006.162.07:41:52.88/vblo/08,744.99,yes,locked 2006.162.07:41:53.03/vabw/8 2006.162.07:41:53.18/vbbw/8 2006.162.07:41:53.27/xfe/off,on,15.0 2006.162.07:41:53.67/ifatt/23,28,28,28 2006.162.07:41:54.08/fmout-gps/S +4.49E-07 2006.162.07:41:54.16:!2006.162.07:43:00 2006.162.07:43:00.00:data_valid=off 2006.162.07:43:00.00:postob 2006.162.07:43:00.13/cable/+6.5346E-03 2006.162.07:43:00.13/wx/17.91,1007.2,100 2006.162.07:43:01.08/fmout-gps/S +4.48E-07 2006.162.07:43:01.08:scan_name=162-0743,k06162,60 2006.162.07:43:01.09:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.162.07:43:02.14#flagr#flagr/antenna,new-source 2006.162.07:43:02.14:checkk5 2006.162.07:43:02.59/chk_autoobs//k5ts1/ autoobs is running! 2006.162.07:43:03.09/chk_autoobs//k5ts2/ autoobs is running! 2006.162.07:43:03.51/chk_autoobs//k5ts3/ autoobs is running! 2006.162.07:43:03.96/chk_autoobs//k5ts4/ autoobs is running! 2006.162.07:43:04.60/chk_obsdata//k5ts1/T1620741??a.dat file size is correct (nominal:560MB, actual:552MB). 2006.162.07:43:05.04/chk_obsdata//k5ts2/T1620741??b.dat file size is correct (nominal:560MB, actual:552MB). 2006.162.07:43:05.42/chk_obsdata//k5ts3/T1620741??c.dat file size is correct (nominal:560MB, actual:552MB). 2006.162.07:43:05.87/chk_obsdata//k5ts4/T1620741??d.dat file size is correct (nominal:560MB, actual:552MB). 2006.162.07:43:06.74/k5log//k5ts1_log_newline 2006.162.07:43:07.53/k5log//k5ts2_log_newline 2006.162.07:43:08.31/k5log//k5ts3_log_newline 2006.162.07:43:09.21/k5log//k5ts4_log_newline 2006.162.07:43:09.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.07:43:09.24:4f8m12a=1 2006.162.07:43:09.24$4f8m12a/echo=on 2006.162.07:43:09.24$4f8m12a/pcalon 2006.162.07:43:09.24$pcalon/"no phase cal control is implemented here 2006.162.07:43:09.24$4f8m12a/"tpicd=stop 2006.162.07:43:09.24$4f8m12a/vc4f8 2006.162.07:43:09.24$vc4f8/valo=1,532.99 2006.162.07:43:09.25#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.162.07:43:09.25#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.162.07:43:09.25#ibcon#ireg 17 cls_cnt 0 2006.162.07:43:09.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:43:09.25#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:43:09.25#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:43:09.25#ibcon#enter wrdev, iclass 7, count 0 2006.162.07:43:09.25#ibcon#first serial, iclass 7, count 0 2006.162.07:43:09.25#ibcon#enter sib2, iclass 7, count 0 2006.162.07:43:09.25#ibcon#flushed, iclass 7, count 0 2006.162.07:43:09.25#ibcon#about to write, iclass 7, count 0 2006.162.07:43:09.25#ibcon#wrote, iclass 7, count 0 2006.162.07:43:09.25#ibcon#about to read 3, iclass 7, count 0 2006.162.07:43:09.29#ibcon#read 3, iclass 7, count 0 2006.162.07:43:09.29#ibcon#about to read 4, iclass 7, count 0 2006.162.07:43:09.29#ibcon#read 4, iclass 7, count 0 2006.162.07:43:09.29#ibcon#about to read 5, iclass 7, count 0 2006.162.07:43:09.29#ibcon#read 5, iclass 7, count 0 2006.162.07:43:09.29#ibcon#about to read 6, iclass 7, count 0 2006.162.07:43:09.29#ibcon#read 6, iclass 7, count 0 2006.162.07:43:09.29#ibcon#end of sib2, iclass 7, count 0 2006.162.07:43:09.29#ibcon#*mode == 0, iclass 7, count 0 2006.162.07:43:09.29#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.162.07:43:09.29#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.07:43:09.29#ibcon#*before write, iclass 7, count 0 2006.162.07:43:09.29#ibcon#enter sib2, iclass 7, count 0 2006.162.07:43:09.29#ibcon#flushed, iclass 7, count 0 2006.162.07:43:09.29#ibcon#about to write, iclass 7, count 0 2006.162.07:43:09.29#ibcon#wrote, iclass 7, count 0 2006.162.07:43:09.29#ibcon#about to read 3, iclass 7, count 0 2006.162.07:43:09.33#ibcon#read 3, iclass 7, count 0 2006.162.07:43:09.33#ibcon#about to read 4, iclass 7, count 0 2006.162.07:43:09.33#ibcon#read 4, iclass 7, count 0 2006.162.07:43:09.33#ibcon#about to read 5, iclass 7, count 0 2006.162.07:43:09.33#ibcon#read 5, iclass 7, count 0 2006.162.07:43:09.33#ibcon#about to read 6, iclass 7, count 0 2006.162.07:43:09.33#ibcon#read 6, iclass 7, count 0 2006.162.07:43:09.33#ibcon#end of sib2, iclass 7, count 0 2006.162.07:43:09.33#ibcon#*after write, iclass 7, count 0 2006.162.07:43:09.33#ibcon#*before return 0, iclass 7, count 0 2006.162.07:43:09.33#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:43:09.33#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:43:09.33#ibcon#about to clear, iclass 7 cls_cnt 0 2006.162.07:43:09.33#ibcon#cleared, iclass 7 cls_cnt 0 2006.162.07:43:09.33$vc4f8/va=1,8 2006.162.07:43:09.33#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.162.07:43:09.33#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.162.07:43:09.33#ibcon#ireg 11 cls_cnt 2 2006.162.07:43:09.33#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:43:09.33#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:43:09.33#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:43:09.33#ibcon#enter wrdev, iclass 11, count 2 2006.162.07:43:09.33#ibcon#first serial, iclass 11, count 2 2006.162.07:43:09.33#ibcon#enter sib2, iclass 11, count 2 2006.162.07:43:09.33#ibcon#flushed, iclass 11, count 2 2006.162.07:43:09.33#ibcon#about to write, iclass 11, count 2 2006.162.07:43:09.33#ibcon#wrote, iclass 11, count 2 2006.162.07:43:09.33#ibcon#about to read 3, iclass 11, count 2 2006.162.07:43:09.35#ibcon#read 3, iclass 11, count 2 2006.162.07:43:09.35#ibcon#about to read 4, iclass 11, count 2 2006.162.07:43:09.35#ibcon#read 4, iclass 11, count 2 2006.162.07:43:09.35#ibcon#about to read 5, iclass 11, count 2 2006.162.07:43:09.35#ibcon#read 5, iclass 11, count 2 2006.162.07:43:09.35#ibcon#about to read 6, iclass 11, count 2 2006.162.07:43:09.35#ibcon#read 6, iclass 11, count 2 2006.162.07:43:09.35#ibcon#end of sib2, iclass 11, count 2 2006.162.07:43:09.35#ibcon#*mode == 0, iclass 11, count 2 2006.162.07:43:09.35#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.162.07:43:09.35#ibcon#[25=AT01-08\r\n] 2006.162.07:43:09.35#ibcon#*before write, iclass 11, count 2 2006.162.07:43:09.35#ibcon#enter sib2, iclass 11, count 2 2006.162.07:43:09.35#ibcon#flushed, iclass 11, count 2 2006.162.07:43:09.35#ibcon#about to write, iclass 11, count 2 2006.162.07:43:09.35#ibcon#wrote, iclass 11, count 2 2006.162.07:43:09.35#ibcon#about to read 3, iclass 11, count 2 2006.162.07:43:09.38#ibcon#read 3, iclass 11, count 2 2006.162.07:43:09.38#ibcon#about to read 4, iclass 11, count 2 2006.162.07:43:09.38#ibcon#read 4, iclass 11, count 2 2006.162.07:43:09.38#ibcon#about to read 5, iclass 11, count 2 2006.162.07:43:09.38#ibcon#read 5, iclass 11, count 2 2006.162.07:43:09.38#ibcon#about to read 6, iclass 11, count 2 2006.162.07:43:09.38#ibcon#read 6, iclass 11, count 2 2006.162.07:43:09.38#ibcon#end of sib2, iclass 11, count 2 2006.162.07:43:09.38#ibcon#*after write, iclass 11, count 2 2006.162.07:43:09.38#ibcon#*before return 0, iclass 11, count 2 2006.162.07:43:09.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:43:09.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:43:09.38#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.162.07:43:09.38#ibcon#ireg 7 cls_cnt 0 2006.162.07:43:09.38#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:43:09.50#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:43:09.50#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:43:09.50#ibcon#enter wrdev, iclass 11, count 0 2006.162.07:43:09.50#ibcon#first serial, iclass 11, count 0 2006.162.07:43:09.50#ibcon#enter sib2, iclass 11, count 0 2006.162.07:43:09.50#ibcon#flushed, iclass 11, count 0 2006.162.07:43:09.50#ibcon#about to write, iclass 11, count 0 2006.162.07:43:09.50#ibcon#wrote, iclass 11, count 0 2006.162.07:43:09.50#ibcon#about to read 3, iclass 11, count 0 2006.162.07:43:09.52#ibcon#read 3, iclass 11, count 0 2006.162.07:43:09.52#ibcon#about to read 4, iclass 11, count 0 2006.162.07:43:09.52#ibcon#read 4, iclass 11, count 0 2006.162.07:43:09.52#ibcon#about to read 5, iclass 11, count 0 2006.162.07:43:09.52#ibcon#read 5, iclass 11, count 0 2006.162.07:43:09.52#ibcon#about to read 6, iclass 11, count 0 2006.162.07:43:09.52#ibcon#read 6, iclass 11, count 0 2006.162.07:43:09.52#ibcon#end of sib2, iclass 11, count 0 2006.162.07:43:09.52#ibcon#*mode == 0, iclass 11, count 0 2006.162.07:43:09.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.162.07:43:09.52#ibcon#[25=USB\r\n] 2006.162.07:43:09.52#ibcon#*before write, iclass 11, count 0 2006.162.07:43:09.52#ibcon#enter sib2, iclass 11, count 0 2006.162.07:43:09.52#ibcon#flushed, iclass 11, count 0 2006.162.07:43:09.52#ibcon#about to write, iclass 11, count 0 2006.162.07:43:09.52#ibcon#wrote, iclass 11, count 0 2006.162.07:43:09.52#ibcon#about to read 3, iclass 11, count 0 2006.162.07:43:09.55#ibcon#read 3, iclass 11, count 0 2006.162.07:43:09.55#ibcon#about to read 4, iclass 11, count 0 2006.162.07:43:09.55#ibcon#read 4, iclass 11, count 0 2006.162.07:43:09.55#ibcon#about to read 5, iclass 11, count 0 2006.162.07:43:09.55#ibcon#read 5, iclass 11, count 0 2006.162.07:43:09.55#ibcon#about to read 6, iclass 11, count 0 2006.162.07:43:09.55#ibcon#read 6, iclass 11, count 0 2006.162.07:43:09.55#ibcon#end of sib2, iclass 11, count 0 2006.162.07:43:09.55#ibcon#*after write, iclass 11, count 0 2006.162.07:43:09.55#ibcon#*before return 0, iclass 11, count 0 2006.162.07:43:09.55#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:43:09.55#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:43:09.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.162.07:43:09.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.162.07:43:09.55$vc4f8/valo=2,572.99 2006.162.07:43:09.55#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.162.07:43:09.55#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.162.07:43:09.55#ibcon#ireg 17 cls_cnt 0 2006.162.07:43:09.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:43:09.55#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:43:09.55#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:43:09.55#ibcon#enter wrdev, iclass 13, count 0 2006.162.07:43:09.55#ibcon#first serial, iclass 13, count 0 2006.162.07:43:09.55#ibcon#enter sib2, iclass 13, count 0 2006.162.07:43:09.55#ibcon#flushed, iclass 13, count 0 2006.162.07:43:09.55#ibcon#about to write, iclass 13, count 0 2006.162.07:43:09.55#ibcon#wrote, iclass 13, count 0 2006.162.07:43:09.55#ibcon#about to read 3, iclass 13, count 0 2006.162.07:43:09.57#ibcon#read 3, iclass 13, count 0 2006.162.07:43:09.57#ibcon#about to read 4, iclass 13, count 0 2006.162.07:43:09.57#ibcon#read 4, iclass 13, count 0 2006.162.07:43:09.57#ibcon#about to read 5, iclass 13, count 0 2006.162.07:43:09.57#ibcon#read 5, iclass 13, count 0 2006.162.07:43:09.57#ibcon#about to read 6, iclass 13, count 0 2006.162.07:43:09.57#ibcon#read 6, iclass 13, count 0 2006.162.07:43:09.57#ibcon#end of sib2, iclass 13, count 0 2006.162.07:43:09.57#ibcon#*mode == 0, iclass 13, count 0 2006.162.07:43:09.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.162.07:43:09.57#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.07:43:09.57#ibcon#*before write, iclass 13, count 0 2006.162.07:43:09.57#ibcon#enter sib2, iclass 13, count 0 2006.162.07:43:09.57#ibcon#flushed, iclass 13, count 0 2006.162.07:43:09.57#ibcon#about to write, iclass 13, count 0 2006.162.07:43:09.57#ibcon#wrote, iclass 13, count 0 2006.162.07:43:09.57#ibcon#about to read 3, iclass 13, count 0 2006.162.07:43:09.61#ibcon#read 3, iclass 13, count 0 2006.162.07:43:09.61#ibcon#about to read 4, iclass 13, count 0 2006.162.07:43:09.61#ibcon#read 4, iclass 13, count 0 2006.162.07:43:09.61#ibcon#about to read 5, iclass 13, count 0 2006.162.07:43:09.61#ibcon#read 5, iclass 13, count 0 2006.162.07:43:09.61#ibcon#about to read 6, iclass 13, count 0 2006.162.07:43:09.61#ibcon#read 6, iclass 13, count 0 2006.162.07:43:09.61#ibcon#end of sib2, iclass 13, count 0 2006.162.07:43:09.61#ibcon#*after write, iclass 13, count 0 2006.162.07:43:09.61#ibcon#*before return 0, iclass 13, count 0 2006.162.07:43:09.61#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:43:09.61#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:43:09.61#ibcon#about to clear, iclass 13 cls_cnt 0 2006.162.07:43:09.61#ibcon#cleared, iclass 13 cls_cnt 0 2006.162.07:43:09.61$vc4f8/va=2,7 2006.162.07:43:09.61#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.162.07:43:09.61#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.162.07:43:09.61#ibcon#ireg 11 cls_cnt 2 2006.162.07:43:09.61#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:43:09.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:43:09.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:43:09.67#ibcon#enter wrdev, iclass 15, count 2 2006.162.07:43:09.67#ibcon#first serial, iclass 15, count 2 2006.162.07:43:09.67#ibcon#enter sib2, iclass 15, count 2 2006.162.07:43:09.67#ibcon#flushed, iclass 15, count 2 2006.162.07:43:09.67#ibcon#about to write, iclass 15, count 2 2006.162.07:43:09.67#ibcon#wrote, iclass 15, count 2 2006.162.07:43:09.67#ibcon#about to read 3, iclass 15, count 2 2006.162.07:43:09.70#ibcon#read 3, iclass 15, count 2 2006.162.07:43:09.70#ibcon#about to read 4, iclass 15, count 2 2006.162.07:43:09.70#ibcon#read 4, iclass 15, count 2 2006.162.07:43:09.70#ibcon#about to read 5, iclass 15, count 2 2006.162.07:43:09.70#ibcon#read 5, iclass 15, count 2 2006.162.07:43:09.70#ibcon#about to read 6, iclass 15, count 2 2006.162.07:43:09.70#ibcon#read 6, iclass 15, count 2 2006.162.07:43:09.70#ibcon#end of sib2, iclass 15, count 2 2006.162.07:43:09.70#ibcon#*mode == 0, iclass 15, count 2 2006.162.07:43:09.70#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.162.07:43:09.70#ibcon#[25=AT02-07\r\n] 2006.162.07:43:09.70#ibcon#*before write, iclass 15, count 2 2006.162.07:43:09.70#ibcon#enter sib2, iclass 15, count 2 2006.162.07:43:09.70#ibcon#flushed, iclass 15, count 2 2006.162.07:43:09.70#ibcon#about to write, iclass 15, count 2 2006.162.07:43:09.70#ibcon#wrote, iclass 15, count 2 2006.162.07:43:09.70#ibcon#about to read 3, iclass 15, count 2 2006.162.07:43:09.73#ibcon#read 3, iclass 15, count 2 2006.162.07:43:09.73#ibcon#about to read 4, iclass 15, count 2 2006.162.07:43:09.73#ibcon#read 4, iclass 15, count 2 2006.162.07:43:09.73#ibcon#about to read 5, iclass 15, count 2 2006.162.07:43:09.73#ibcon#read 5, iclass 15, count 2 2006.162.07:43:09.73#ibcon#about to read 6, iclass 15, count 2 2006.162.07:43:09.73#ibcon#read 6, iclass 15, count 2 2006.162.07:43:09.73#ibcon#end of sib2, iclass 15, count 2 2006.162.07:43:09.73#ibcon#*after write, iclass 15, count 2 2006.162.07:43:09.73#ibcon#*before return 0, iclass 15, count 2 2006.162.07:43:09.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:43:09.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:43:09.73#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.162.07:43:09.73#ibcon#ireg 7 cls_cnt 0 2006.162.07:43:09.73#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:43:09.85#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:43:09.85#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:43:09.85#ibcon#enter wrdev, iclass 15, count 0 2006.162.07:43:09.85#ibcon#first serial, iclass 15, count 0 2006.162.07:43:09.85#ibcon#enter sib2, iclass 15, count 0 2006.162.07:43:09.85#ibcon#flushed, iclass 15, count 0 2006.162.07:43:09.85#ibcon#about to write, iclass 15, count 0 2006.162.07:43:09.85#ibcon#wrote, iclass 15, count 0 2006.162.07:43:09.85#ibcon#about to read 3, iclass 15, count 0 2006.162.07:43:09.87#ibcon#read 3, iclass 15, count 0 2006.162.07:43:09.87#ibcon#about to read 4, iclass 15, count 0 2006.162.07:43:09.87#ibcon#read 4, iclass 15, count 0 2006.162.07:43:09.87#ibcon#about to read 5, iclass 15, count 0 2006.162.07:43:09.87#ibcon#read 5, iclass 15, count 0 2006.162.07:43:09.87#ibcon#about to read 6, iclass 15, count 0 2006.162.07:43:09.87#ibcon#read 6, iclass 15, count 0 2006.162.07:43:09.87#ibcon#end of sib2, iclass 15, count 0 2006.162.07:43:09.87#ibcon#*mode == 0, iclass 15, count 0 2006.162.07:43:09.87#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.162.07:43:09.87#ibcon#[25=USB\r\n] 2006.162.07:43:09.87#ibcon#*before write, iclass 15, count 0 2006.162.07:43:09.87#ibcon#enter sib2, iclass 15, count 0 2006.162.07:43:09.87#ibcon#flushed, iclass 15, count 0 2006.162.07:43:09.87#ibcon#about to write, iclass 15, count 0 2006.162.07:43:09.87#ibcon#wrote, iclass 15, count 0 2006.162.07:43:09.87#ibcon#about to read 3, iclass 15, count 0 2006.162.07:43:09.90#ibcon#read 3, iclass 15, count 0 2006.162.07:43:09.90#ibcon#about to read 4, iclass 15, count 0 2006.162.07:43:09.90#ibcon#read 4, iclass 15, count 0 2006.162.07:43:09.90#ibcon#about to read 5, iclass 15, count 0 2006.162.07:43:09.90#ibcon#read 5, iclass 15, count 0 2006.162.07:43:09.90#ibcon#about to read 6, iclass 15, count 0 2006.162.07:43:09.90#ibcon#read 6, iclass 15, count 0 2006.162.07:43:09.90#ibcon#end of sib2, iclass 15, count 0 2006.162.07:43:09.90#ibcon#*after write, iclass 15, count 0 2006.162.07:43:09.90#ibcon#*before return 0, iclass 15, count 0 2006.162.07:43:09.90#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:43:09.90#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:43:09.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.162.07:43:09.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.162.07:43:09.90$vc4f8/valo=3,672.99 2006.162.07:43:09.90#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.162.07:43:09.90#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.162.07:43:09.90#ibcon#ireg 17 cls_cnt 0 2006.162.07:43:09.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:43:09.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:43:09.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:43:09.90#ibcon#enter wrdev, iclass 17, count 0 2006.162.07:43:09.90#ibcon#first serial, iclass 17, count 0 2006.162.07:43:09.90#ibcon#enter sib2, iclass 17, count 0 2006.162.07:43:09.90#ibcon#flushed, iclass 17, count 0 2006.162.07:43:09.90#ibcon#about to write, iclass 17, count 0 2006.162.07:43:09.90#ibcon#wrote, iclass 17, count 0 2006.162.07:43:09.90#ibcon#about to read 3, iclass 17, count 0 2006.162.07:43:09.92#ibcon#read 3, iclass 17, count 0 2006.162.07:43:09.92#ibcon#about to read 4, iclass 17, count 0 2006.162.07:43:09.92#ibcon#read 4, iclass 17, count 0 2006.162.07:43:09.92#ibcon#about to read 5, iclass 17, count 0 2006.162.07:43:09.92#ibcon#read 5, iclass 17, count 0 2006.162.07:43:09.92#ibcon#about to read 6, iclass 17, count 0 2006.162.07:43:09.92#ibcon#read 6, iclass 17, count 0 2006.162.07:43:09.92#ibcon#end of sib2, iclass 17, count 0 2006.162.07:43:09.92#ibcon#*mode == 0, iclass 17, count 0 2006.162.07:43:09.92#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.162.07:43:09.92#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.07:43:09.92#ibcon#*before write, iclass 17, count 0 2006.162.07:43:09.92#ibcon#enter sib2, iclass 17, count 0 2006.162.07:43:09.92#ibcon#flushed, iclass 17, count 0 2006.162.07:43:09.92#ibcon#about to write, iclass 17, count 0 2006.162.07:43:09.92#ibcon#wrote, iclass 17, count 0 2006.162.07:43:09.92#ibcon#about to read 3, iclass 17, count 0 2006.162.07:43:09.96#ibcon#read 3, iclass 17, count 0 2006.162.07:43:09.96#ibcon#about to read 4, iclass 17, count 0 2006.162.07:43:09.96#ibcon#read 4, iclass 17, count 0 2006.162.07:43:09.96#ibcon#about to read 5, iclass 17, count 0 2006.162.07:43:09.96#ibcon#read 5, iclass 17, count 0 2006.162.07:43:09.96#ibcon#about to read 6, iclass 17, count 0 2006.162.07:43:09.96#ibcon#read 6, iclass 17, count 0 2006.162.07:43:09.96#ibcon#end of sib2, iclass 17, count 0 2006.162.07:43:09.96#ibcon#*after write, iclass 17, count 0 2006.162.07:43:09.96#ibcon#*before return 0, iclass 17, count 0 2006.162.07:43:09.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:43:09.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:43:09.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.162.07:43:09.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.162.07:43:09.96$vc4f8/va=3,6 2006.162.07:43:09.96#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.162.07:43:09.96#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.162.07:43:09.96#ibcon#ireg 11 cls_cnt 2 2006.162.07:43:09.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:43:10.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:43:10.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:43:10.02#ibcon#enter wrdev, iclass 19, count 2 2006.162.07:43:10.02#ibcon#first serial, iclass 19, count 2 2006.162.07:43:10.02#ibcon#enter sib2, iclass 19, count 2 2006.162.07:43:10.02#ibcon#flushed, iclass 19, count 2 2006.162.07:43:10.02#ibcon#about to write, iclass 19, count 2 2006.162.07:43:10.02#ibcon#wrote, iclass 19, count 2 2006.162.07:43:10.02#ibcon#about to read 3, iclass 19, count 2 2006.162.07:43:10.04#ibcon#read 3, iclass 19, count 2 2006.162.07:43:10.04#ibcon#about to read 4, iclass 19, count 2 2006.162.07:43:10.04#ibcon#read 4, iclass 19, count 2 2006.162.07:43:10.04#ibcon#about to read 5, iclass 19, count 2 2006.162.07:43:10.04#ibcon#read 5, iclass 19, count 2 2006.162.07:43:10.04#ibcon#about to read 6, iclass 19, count 2 2006.162.07:43:10.04#ibcon#read 6, iclass 19, count 2 2006.162.07:43:10.04#ibcon#end of sib2, iclass 19, count 2 2006.162.07:43:10.04#ibcon#*mode == 0, iclass 19, count 2 2006.162.07:43:10.04#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.162.07:43:10.04#ibcon#[25=AT03-06\r\n] 2006.162.07:43:10.04#ibcon#*before write, iclass 19, count 2 2006.162.07:43:10.04#ibcon#enter sib2, iclass 19, count 2 2006.162.07:43:10.04#ibcon#flushed, iclass 19, count 2 2006.162.07:43:10.04#ibcon#about to write, iclass 19, count 2 2006.162.07:43:10.04#ibcon#wrote, iclass 19, count 2 2006.162.07:43:10.04#ibcon#about to read 3, iclass 19, count 2 2006.162.07:43:10.07#ibcon#read 3, iclass 19, count 2 2006.162.07:43:10.07#ibcon#about to read 4, iclass 19, count 2 2006.162.07:43:10.07#ibcon#read 4, iclass 19, count 2 2006.162.07:43:10.07#ibcon#about to read 5, iclass 19, count 2 2006.162.07:43:10.07#ibcon#read 5, iclass 19, count 2 2006.162.07:43:10.07#ibcon#about to read 6, iclass 19, count 2 2006.162.07:43:10.07#ibcon#read 6, iclass 19, count 2 2006.162.07:43:10.07#ibcon#end of sib2, iclass 19, count 2 2006.162.07:43:10.07#ibcon#*after write, iclass 19, count 2 2006.162.07:43:10.07#ibcon#*before return 0, iclass 19, count 2 2006.162.07:43:10.07#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:43:10.07#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:43:10.07#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.162.07:43:10.07#ibcon#ireg 7 cls_cnt 0 2006.162.07:43:10.07#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:43:10.19#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:43:10.19#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:43:10.19#ibcon#enter wrdev, iclass 19, count 0 2006.162.07:43:10.19#ibcon#first serial, iclass 19, count 0 2006.162.07:43:10.19#ibcon#enter sib2, iclass 19, count 0 2006.162.07:43:10.19#ibcon#flushed, iclass 19, count 0 2006.162.07:43:10.19#ibcon#about to write, iclass 19, count 0 2006.162.07:43:10.19#ibcon#wrote, iclass 19, count 0 2006.162.07:43:10.19#ibcon#about to read 3, iclass 19, count 0 2006.162.07:43:10.21#ibcon#read 3, iclass 19, count 0 2006.162.07:43:10.21#ibcon#about to read 4, iclass 19, count 0 2006.162.07:43:10.21#ibcon#read 4, iclass 19, count 0 2006.162.07:43:10.21#ibcon#about to read 5, iclass 19, count 0 2006.162.07:43:10.21#ibcon#read 5, iclass 19, count 0 2006.162.07:43:10.21#ibcon#about to read 6, iclass 19, count 0 2006.162.07:43:10.21#ibcon#read 6, iclass 19, count 0 2006.162.07:43:10.21#ibcon#end of sib2, iclass 19, count 0 2006.162.07:43:10.21#ibcon#*mode == 0, iclass 19, count 0 2006.162.07:43:10.21#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.162.07:43:10.21#ibcon#[25=USB\r\n] 2006.162.07:43:10.21#ibcon#*before write, iclass 19, count 0 2006.162.07:43:10.21#ibcon#enter sib2, iclass 19, count 0 2006.162.07:43:10.21#ibcon#flushed, iclass 19, count 0 2006.162.07:43:10.21#ibcon#about to write, iclass 19, count 0 2006.162.07:43:10.21#ibcon#wrote, iclass 19, count 0 2006.162.07:43:10.21#ibcon#about to read 3, iclass 19, count 0 2006.162.07:43:10.24#ibcon#read 3, iclass 19, count 0 2006.162.07:43:10.24#ibcon#about to read 4, iclass 19, count 0 2006.162.07:43:10.24#ibcon#read 4, iclass 19, count 0 2006.162.07:43:10.24#ibcon#about to read 5, iclass 19, count 0 2006.162.07:43:10.24#ibcon#read 5, iclass 19, count 0 2006.162.07:43:10.24#ibcon#about to read 6, iclass 19, count 0 2006.162.07:43:10.24#ibcon#read 6, iclass 19, count 0 2006.162.07:43:10.24#ibcon#end of sib2, iclass 19, count 0 2006.162.07:43:10.24#ibcon#*after write, iclass 19, count 0 2006.162.07:43:10.24#ibcon#*before return 0, iclass 19, count 0 2006.162.07:43:10.24#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:43:10.24#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:43:10.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.162.07:43:10.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.162.07:43:10.24$vc4f8/valo=4,832.99 2006.162.07:43:10.24#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.162.07:43:10.24#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.162.07:43:10.24#ibcon#ireg 17 cls_cnt 0 2006.162.07:43:10.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:43:10.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:43:10.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:43:10.24#ibcon#enter wrdev, iclass 21, count 0 2006.162.07:43:10.24#ibcon#first serial, iclass 21, count 0 2006.162.07:43:10.24#ibcon#enter sib2, iclass 21, count 0 2006.162.07:43:10.24#ibcon#flushed, iclass 21, count 0 2006.162.07:43:10.24#ibcon#about to write, iclass 21, count 0 2006.162.07:43:10.24#ibcon#wrote, iclass 21, count 0 2006.162.07:43:10.24#ibcon#about to read 3, iclass 21, count 0 2006.162.07:43:10.26#ibcon#read 3, iclass 21, count 0 2006.162.07:43:10.26#ibcon#about to read 4, iclass 21, count 0 2006.162.07:43:10.26#ibcon#read 4, iclass 21, count 0 2006.162.07:43:10.26#ibcon#about to read 5, iclass 21, count 0 2006.162.07:43:10.26#ibcon#read 5, iclass 21, count 0 2006.162.07:43:10.26#ibcon#about to read 6, iclass 21, count 0 2006.162.07:43:10.26#ibcon#read 6, iclass 21, count 0 2006.162.07:43:10.26#ibcon#end of sib2, iclass 21, count 0 2006.162.07:43:10.26#ibcon#*mode == 0, iclass 21, count 0 2006.162.07:43:10.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.162.07:43:10.26#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.07:43:10.26#ibcon#*before write, iclass 21, count 0 2006.162.07:43:10.26#ibcon#enter sib2, iclass 21, count 0 2006.162.07:43:10.26#ibcon#flushed, iclass 21, count 0 2006.162.07:43:10.26#ibcon#about to write, iclass 21, count 0 2006.162.07:43:10.26#ibcon#wrote, iclass 21, count 0 2006.162.07:43:10.26#ibcon#about to read 3, iclass 21, count 0 2006.162.07:43:10.30#ibcon#read 3, iclass 21, count 0 2006.162.07:43:10.30#ibcon#about to read 4, iclass 21, count 0 2006.162.07:43:10.30#ibcon#read 4, iclass 21, count 0 2006.162.07:43:10.30#ibcon#about to read 5, iclass 21, count 0 2006.162.07:43:10.30#ibcon#read 5, iclass 21, count 0 2006.162.07:43:10.30#ibcon#about to read 6, iclass 21, count 0 2006.162.07:43:10.30#ibcon#read 6, iclass 21, count 0 2006.162.07:43:10.30#ibcon#end of sib2, iclass 21, count 0 2006.162.07:43:10.30#ibcon#*after write, iclass 21, count 0 2006.162.07:43:10.30#ibcon#*before return 0, iclass 21, count 0 2006.162.07:43:10.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:43:10.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:43:10.30#ibcon#about to clear, iclass 21 cls_cnt 0 2006.162.07:43:10.30#ibcon#cleared, iclass 21 cls_cnt 0 2006.162.07:43:10.30$vc4f8/va=4,7 2006.162.07:43:10.30#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.162.07:43:10.30#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.162.07:43:10.30#ibcon#ireg 11 cls_cnt 2 2006.162.07:43:10.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.162.07:43:10.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.162.07:43:10.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.162.07:43:10.36#ibcon#enter wrdev, iclass 23, count 2 2006.162.07:43:10.36#ibcon#first serial, iclass 23, count 2 2006.162.07:43:10.36#ibcon#enter sib2, iclass 23, count 2 2006.162.07:43:10.36#ibcon#flushed, iclass 23, count 2 2006.162.07:43:10.36#ibcon#about to write, iclass 23, count 2 2006.162.07:43:10.36#ibcon#wrote, iclass 23, count 2 2006.162.07:43:10.36#ibcon#about to read 3, iclass 23, count 2 2006.162.07:43:10.38#ibcon#read 3, iclass 23, count 2 2006.162.07:43:10.38#ibcon#about to read 4, iclass 23, count 2 2006.162.07:43:10.38#ibcon#read 4, iclass 23, count 2 2006.162.07:43:10.38#ibcon#about to read 5, iclass 23, count 2 2006.162.07:43:10.38#ibcon#read 5, iclass 23, count 2 2006.162.07:43:10.38#ibcon#about to read 6, iclass 23, count 2 2006.162.07:43:10.38#ibcon#read 6, iclass 23, count 2 2006.162.07:43:10.38#ibcon#end of sib2, iclass 23, count 2 2006.162.07:43:10.38#ibcon#*mode == 0, iclass 23, count 2 2006.162.07:43:10.38#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.162.07:43:10.38#ibcon#[25=AT04-07\r\n] 2006.162.07:43:10.38#ibcon#*before write, iclass 23, count 2 2006.162.07:43:10.38#ibcon#enter sib2, iclass 23, count 2 2006.162.07:43:10.38#ibcon#flushed, iclass 23, count 2 2006.162.07:43:10.38#ibcon#about to write, iclass 23, count 2 2006.162.07:43:10.38#ibcon#wrote, iclass 23, count 2 2006.162.07:43:10.38#ibcon#about to read 3, iclass 23, count 2 2006.162.07:43:10.41#ibcon#read 3, iclass 23, count 2 2006.162.07:43:10.41#ibcon#about to read 4, iclass 23, count 2 2006.162.07:43:10.41#ibcon#read 4, iclass 23, count 2 2006.162.07:43:10.41#ibcon#about to read 5, iclass 23, count 2 2006.162.07:43:10.41#ibcon#read 5, iclass 23, count 2 2006.162.07:43:10.41#ibcon#about to read 6, iclass 23, count 2 2006.162.07:43:10.41#ibcon#read 6, iclass 23, count 2 2006.162.07:43:10.41#ibcon#end of sib2, iclass 23, count 2 2006.162.07:43:10.41#ibcon#*after write, iclass 23, count 2 2006.162.07:43:10.41#ibcon#*before return 0, iclass 23, count 2 2006.162.07:43:10.41#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.162.07:43:10.41#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.162.07:43:10.41#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.162.07:43:10.41#ibcon#ireg 7 cls_cnt 0 2006.162.07:43:10.41#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.162.07:43:10.53#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.162.07:43:10.53#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.162.07:43:10.53#ibcon#enter wrdev, iclass 23, count 0 2006.162.07:43:10.53#ibcon#first serial, iclass 23, count 0 2006.162.07:43:10.53#ibcon#enter sib2, iclass 23, count 0 2006.162.07:43:10.53#ibcon#flushed, iclass 23, count 0 2006.162.07:43:10.53#ibcon#about to write, iclass 23, count 0 2006.162.07:43:10.53#ibcon#wrote, iclass 23, count 0 2006.162.07:43:10.53#ibcon#about to read 3, iclass 23, count 0 2006.162.07:43:10.55#ibcon#read 3, iclass 23, count 0 2006.162.07:43:10.55#ibcon#about to read 4, iclass 23, count 0 2006.162.07:43:10.55#ibcon#read 4, iclass 23, count 0 2006.162.07:43:10.55#ibcon#about to read 5, iclass 23, count 0 2006.162.07:43:10.55#ibcon#read 5, iclass 23, count 0 2006.162.07:43:10.55#ibcon#about to read 6, iclass 23, count 0 2006.162.07:43:10.55#ibcon#read 6, iclass 23, count 0 2006.162.07:43:10.55#ibcon#end of sib2, iclass 23, count 0 2006.162.07:43:10.55#ibcon#*mode == 0, iclass 23, count 0 2006.162.07:43:10.55#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.162.07:43:10.55#ibcon#[25=USB\r\n] 2006.162.07:43:10.55#ibcon#*before write, iclass 23, count 0 2006.162.07:43:10.55#ibcon#enter sib2, iclass 23, count 0 2006.162.07:43:10.55#ibcon#flushed, iclass 23, count 0 2006.162.07:43:10.55#ibcon#about to write, iclass 23, count 0 2006.162.07:43:10.55#ibcon#wrote, iclass 23, count 0 2006.162.07:43:10.55#ibcon#about to read 3, iclass 23, count 0 2006.162.07:43:10.58#ibcon#read 3, iclass 23, count 0 2006.162.07:43:10.58#ibcon#about to read 4, iclass 23, count 0 2006.162.07:43:10.58#ibcon#read 4, iclass 23, count 0 2006.162.07:43:10.58#ibcon#about to read 5, iclass 23, count 0 2006.162.07:43:10.58#ibcon#read 5, iclass 23, count 0 2006.162.07:43:10.58#ibcon#about to read 6, iclass 23, count 0 2006.162.07:43:10.58#ibcon#read 6, iclass 23, count 0 2006.162.07:43:10.58#ibcon#end of sib2, iclass 23, count 0 2006.162.07:43:10.58#ibcon#*after write, iclass 23, count 0 2006.162.07:43:10.58#ibcon#*before return 0, iclass 23, count 0 2006.162.07:43:10.58#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.162.07:43:10.58#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.162.07:43:10.58#ibcon#about to clear, iclass 23 cls_cnt 0 2006.162.07:43:10.58#ibcon#cleared, iclass 23 cls_cnt 0 2006.162.07:43:10.58$vc4f8/valo=5,652.99 2006.162.07:43:10.58#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.162.07:43:10.58#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.162.07:43:10.58#ibcon#ireg 17 cls_cnt 0 2006.162.07:43:10.58#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:43:10.58#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:43:10.58#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:43:10.58#ibcon#enter wrdev, iclass 25, count 0 2006.162.07:43:10.58#ibcon#first serial, iclass 25, count 0 2006.162.07:43:10.58#ibcon#enter sib2, iclass 25, count 0 2006.162.07:43:10.58#ibcon#flushed, iclass 25, count 0 2006.162.07:43:10.58#ibcon#about to write, iclass 25, count 0 2006.162.07:43:10.58#ibcon#wrote, iclass 25, count 0 2006.162.07:43:10.58#ibcon#about to read 3, iclass 25, count 0 2006.162.07:43:10.60#ibcon#read 3, iclass 25, count 0 2006.162.07:43:10.60#ibcon#about to read 4, iclass 25, count 0 2006.162.07:43:10.60#ibcon#read 4, iclass 25, count 0 2006.162.07:43:10.60#ibcon#about to read 5, iclass 25, count 0 2006.162.07:43:10.60#ibcon#read 5, iclass 25, count 0 2006.162.07:43:10.60#ibcon#about to read 6, iclass 25, count 0 2006.162.07:43:10.60#ibcon#read 6, iclass 25, count 0 2006.162.07:43:10.60#ibcon#end of sib2, iclass 25, count 0 2006.162.07:43:10.60#ibcon#*mode == 0, iclass 25, count 0 2006.162.07:43:10.60#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.162.07:43:10.60#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.07:43:10.60#ibcon#*before write, iclass 25, count 0 2006.162.07:43:10.60#ibcon#enter sib2, iclass 25, count 0 2006.162.07:43:10.60#ibcon#flushed, iclass 25, count 0 2006.162.07:43:10.60#ibcon#about to write, iclass 25, count 0 2006.162.07:43:10.60#ibcon#wrote, iclass 25, count 0 2006.162.07:43:10.60#ibcon#about to read 3, iclass 25, count 0 2006.162.07:43:10.64#ibcon#read 3, iclass 25, count 0 2006.162.07:43:10.64#ibcon#about to read 4, iclass 25, count 0 2006.162.07:43:10.64#ibcon#read 4, iclass 25, count 0 2006.162.07:43:10.64#ibcon#about to read 5, iclass 25, count 0 2006.162.07:43:10.64#ibcon#read 5, iclass 25, count 0 2006.162.07:43:10.64#ibcon#about to read 6, iclass 25, count 0 2006.162.07:43:10.64#ibcon#read 6, iclass 25, count 0 2006.162.07:43:10.64#ibcon#end of sib2, iclass 25, count 0 2006.162.07:43:10.64#ibcon#*after write, iclass 25, count 0 2006.162.07:43:10.64#ibcon#*before return 0, iclass 25, count 0 2006.162.07:43:10.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:43:10.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:43:10.64#ibcon#about to clear, iclass 25 cls_cnt 0 2006.162.07:43:10.64#ibcon#cleared, iclass 25 cls_cnt 0 2006.162.07:43:10.64$vc4f8/va=5,7 2006.162.07:43:10.64#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.162.07:43:10.64#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.162.07:43:10.64#ibcon#ireg 11 cls_cnt 2 2006.162.07:43:10.64#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.162.07:43:10.70#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.162.07:43:10.70#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.162.07:43:10.70#ibcon#enter wrdev, iclass 27, count 2 2006.162.07:43:10.70#ibcon#first serial, iclass 27, count 2 2006.162.07:43:10.70#ibcon#enter sib2, iclass 27, count 2 2006.162.07:43:10.70#ibcon#flushed, iclass 27, count 2 2006.162.07:43:10.70#ibcon#about to write, iclass 27, count 2 2006.162.07:43:10.70#ibcon#wrote, iclass 27, count 2 2006.162.07:43:10.70#ibcon#about to read 3, iclass 27, count 2 2006.162.07:43:10.71#abcon#<5=/03 1.2 3.0 17.901001007.2\r\n> 2006.162.07:43:10.72#ibcon#read 3, iclass 27, count 2 2006.162.07:43:10.72#ibcon#about to read 4, iclass 27, count 2 2006.162.07:43:10.72#ibcon#read 4, iclass 27, count 2 2006.162.07:43:10.72#ibcon#about to read 5, iclass 27, count 2 2006.162.07:43:10.72#ibcon#read 5, iclass 27, count 2 2006.162.07:43:10.72#ibcon#about to read 6, iclass 27, count 2 2006.162.07:43:10.72#ibcon#read 6, iclass 27, count 2 2006.162.07:43:10.72#ibcon#end of sib2, iclass 27, count 2 2006.162.07:43:10.72#ibcon#*mode == 0, iclass 27, count 2 2006.162.07:43:10.72#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.162.07:43:10.72#ibcon#[25=AT05-07\r\n] 2006.162.07:43:10.72#ibcon#*before write, iclass 27, count 2 2006.162.07:43:10.72#ibcon#enter sib2, iclass 27, count 2 2006.162.07:43:10.72#ibcon#flushed, iclass 27, count 2 2006.162.07:43:10.72#ibcon#about to write, iclass 27, count 2 2006.162.07:43:10.72#ibcon#wrote, iclass 27, count 2 2006.162.07:43:10.72#ibcon#about to read 3, iclass 27, count 2 2006.162.07:43:10.73#abcon#{5=INTERFACE CLEAR} 2006.162.07:43:10.75#ibcon#read 3, iclass 27, count 2 2006.162.07:43:10.75#ibcon#about to read 4, iclass 27, count 2 2006.162.07:43:10.75#ibcon#read 4, iclass 27, count 2 2006.162.07:43:10.75#ibcon#about to read 5, iclass 27, count 2 2006.162.07:43:10.75#ibcon#read 5, iclass 27, count 2 2006.162.07:43:10.75#ibcon#about to read 6, iclass 27, count 2 2006.162.07:43:10.75#ibcon#read 6, iclass 27, count 2 2006.162.07:43:10.75#ibcon#end of sib2, iclass 27, count 2 2006.162.07:43:10.75#ibcon#*after write, iclass 27, count 2 2006.162.07:43:10.75#ibcon#*before return 0, iclass 27, count 2 2006.162.07:43:10.75#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.162.07:43:10.75#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.162.07:43:10.75#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.162.07:43:10.75#ibcon#ireg 7 cls_cnt 0 2006.162.07:43:10.75#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.162.07:43:10.79#abcon#[5=S1D000X0/0*\r\n] 2006.162.07:43:10.87#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.162.07:43:10.87#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.162.07:43:10.87#ibcon#enter wrdev, iclass 27, count 0 2006.162.07:43:10.87#ibcon#first serial, iclass 27, count 0 2006.162.07:43:10.87#ibcon#enter sib2, iclass 27, count 0 2006.162.07:43:10.87#ibcon#flushed, iclass 27, count 0 2006.162.07:43:10.87#ibcon#about to write, iclass 27, count 0 2006.162.07:43:10.87#ibcon#wrote, iclass 27, count 0 2006.162.07:43:10.87#ibcon#about to read 3, iclass 27, count 0 2006.162.07:43:10.89#ibcon#read 3, iclass 27, count 0 2006.162.07:43:10.89#ibcon#about to read 4, iclass 27, count 0 2006.162.07:43:10.89#ibcon#read 4, iclass 27, count 0 2006.162.07:43:10.89#ibcon#about to read 5, iclass 27, count 0 2006.162.07:43:10.89#ibcon#read 5, iclass 27, count 0 2006.162.07:43:10.89#ibcon#about to read 6, iclass 27, count 0 2006.162.07:43:10.89#ibcon#read 6, iclass 27, count 0 2006.162.07:43:10.89#ibcon#end of sib2, iclass 27, count 0 2006.162.07:43:10.89#ibcon#*mode == 0, iclass 27, count 0 2006.162.07:43:10.89#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.162.07:43:10.89#ibcon#[25=USB\r\n] 2006.162.07:43:10.89#ibcon#*before write, iclass 27, count 0 2006.162.07:43:10.89#ibcon#enter sib2, iclass 27, count 0 2006.162.07:43:10.89#ibcon#flushed, iclass 27, count 0 2006.162.07:43:10.89#ibcon#about to write, iclass 27, count 0 2006.162.07:43:10.89#ibcon#wrote, iclass 27, count 0 2006.162.07:43:10.89#ibcon#about to read 3, iclass 27, count 0 2006.162.07:43:10.92#ibcon#read 3, iclass 27, count 0 2006.162.07:43:10.92#ibcon#about to read 4, iclass 27, count 0 2006.162.07:43:10.92#ibcon#read 4, iclass 27, count 0 2006.162.07:43:10.92#ibcon#about to read 5, iclass 27, count 0 2006.162.07:43:10.92#ibcon#read 5, iclass 27, count 0 2006.162.07:43:10.92#ibcon#about to read 6, iclass 27, count 0 2006.162.07:43:10.92#ibcon#read 6, iclass 27, count 0 2006.162.07:43:10.92#ibcon#end of sib2, iclass 27, count 0 2006.162.07:43:10.92#ibcon#*after write, iclass 27, count 0 2006.162.07:43:10.92#ibcon#*before return 0, iclass 27, count 0 2006.162.07:43:10.92#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.162.07:43:10.92#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.162.07:43:10.92#ibcon#about to clear, iclass 27 cls_cnt 0 2006.162.07:43:10.92#ibcon#cleared, iclass 27 cls_cnt 0 2006.162.07:43:10.92$vc4f8/valo=6,772.99 2006.162.07:43:10.92#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.162.07:43:10.92#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.162.07:43:10.92#ibcon#ireg 17 cls_cnt 0 2006.162.07:43:10.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.162.07:43:10.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.162.07:43:10.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.162.07:43:10.92#ibcon#enter wrdev, iclass 33, count 0 2006.162.07:43:10.92#ibcon#first serial, iclass 33, count 0 2006.162.07:43:10.92#ibcon#enter sib2, iclass 33, count 0 2006.162.07:43:10.92#ibcon#flushed, iclass 33, count 0 2006.162.07:43:10.92#ibcon#about to write, iclass 33, count 0 2006.162.07:43:10.92#ibcon#wrote, iclass 33, count 0 2006.162.07:43:10.92#ibcon#about to read 3, iclass 33, count 0 2006.162.07:43:10.94#ibcon#read 3, iclass 33, count 0 2006.162.07:43:10.94#ibcon#about to read 4, iclass 33, count 0 2006.162.07:43:10.94#ibcon#read 4, iclass 33, count 0 2006.162.07:43:10.94#ibcon#about to read 5, iclass 33, count 0 2006.162.07:43:10.94#ibcon#read 5, iclass 33, count 0 2006.162.07:43:10.94#ibcon#about to read 6, iclass 33, count 0 2006.162.07:43:10.94#ibcon#read 6, iclass 33, count 0 2006.162.07:43:10.94#ibcon#end of sib2, iclass 33, count 0 2006.162.07:43:10.94#ibcon#*mode == 0, iclass 33, count 0 2006.162.07:43:10.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.162.07:43:10.94#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.07:43:10.94#ibcon#*before write, iclass 33, count 0 2006.162.07:43:10.94#ibcon#enter sib2, iclass 33, count 0 2006.162.07:43:10.94#ibcon#flushed, iclass 33, count 0 2006.162.07:43:10.94#ibcon#about to write, iclass 33, count 0 2006.162.07:43:10.94#ibcon#wrote, iclass 33, count 0 2006.162.07:43:10.94#ibcon#about to read 3, iclass 33, count 0 2006.162.07:43:10.98#ibcon#read 3, iclass 33, count 0 2006.162.07:43:10.98#ibcon#about to read 4, iclass 33, count 0 2006.162.07:43:10.98#ibcon#read 4, iclass 33, count 0 2006.162.07:43:10.98#ibcon#about to read 5, iclass 33, count 0 2006.162.07:43:10.98#ibcon#read 5, iclass 33, count 0 2006.162.07:43:10.98#ibcon#about to read 6, iclass 33, count 0 2006.162.07:43:10.98#ibcon#read 6, iclass 33, count 0 2006.162.07:43:10.98#ibcon#end of sib2, iclass 33, count 0 2006.162.07:43:10.98#ibcon#*after write, iclass 33, count 0 2006.162.07:43:10.98#ibcon#*before return 0, iclass 33, count 0 2006.162.07:43:10.98#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.162.07:43:10.98#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.162.07:43:10.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.162.07:43:10.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.162.07:43:10.98$vc4f8/va=6,6 2006.162.07:43:10.98#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.162.07:43:10.98#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.162.07:43:10.98#ibcon#ireg 11 cls_cnt 2 2006.162.07:43:10.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.162.07:43:11.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.162.07:43:11.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.162.07:43:11.04#ibcon#enter wrdev, iclass 35, count 2 2006.162.07:43:11.04#ibcon#first serial, iclass 35, count 2 2006.162.07:43:11.04#ibcon#enter sib2, iclass 35, count 2 2006.162.07:43:11.04#ibcon#flushed, iclass 35, count 2 2006.162.07:43:11.04#ibcon#about to write, iclass 35, count 2 2006.162.07:43:11.04#ibcon#wrote, iclass 35, count 2 2006.162.07:43:11.04#ibcon#about to read 3, iclass 35, count 2 2006.162.07:43:11.06#ibcon#read 3, iclass 35, count 2 2006.162.07:43:11.06#ibcon#about to read 4, iclass 35, count 2 2006.162.07:43:11.06#ibcon#read 4, iclass 35, count 2 2006.162.07:43:11.06#ibcon#about to read 5, iclass 35, count 2 2006.162.07:43:11.06#ibcon#read 5, iclass 35, count 2 2006.162.07:43:11.06#ibcon#about to read 6, iclass 35, count 2 2006.162.07:43:11.06#ibcon#read 6, iclass 35, count 2 2006.162.07:43:11.06#ibcon#end of sib2, iclass 35, count 2 2006.162.07:43:11.06#ibcon#*mode == 0, iclass 35, count 2 2006.162.07:43:11.06#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.162.07:43:11.06#ibcon#[25=AT06-06\r\n] 2006.162.07:43:11.06#ibcon#*before write, iclass 35, count 2 2006.162.07:43:11.06#ibcon#enter sib2, iclass 35, count 2 2006.162.07:43:11.06#ibcon#flushed, iclass 35, count 2 2006.162.07:43:11.06#ibcon#about to write, iclass 35, count 2 2006.162.07:43:11.06#ibcon#wrote, iclass 35, count 2 2006.162.07:43:11.06#ibcon#about to read 3, iclass 35, count 2 2006.162.07:43:11.09#ibcon#read 3, iclass 35, count 2 2006.162.07:43:11.09#ibcon#about to read 4, iclass 35, count 2 2006.162.07:43:11.09#ibcon#read 4, iclass 35, count 2 2006.162.07:43:11.09#ibcon#about to read 5, iclass 35, count 2 2006.162.07:43:11.09#ibcon#read 5, iclass 35, count 2 2006.162.07:43:11.09#ibcon#about to read 6, iclass 35, count 2 2006.162.07:43:11.09#ibcon#read 6, iclass 35, count 2 2006.162.07:43:11.09#ibcon#end of sib2, iclass 35, count 2 2006.162.07:43:11.09#ibcon#*after write, iclass 35, count 2 2006.162.07:43:11.09#ibcon#*before return 0, iclass 35, count 2 2006.162.07:43:11.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.162.07:43:11.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.162.07:43:11.09#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.162.07:43:11.09#ibcon#ireg 7 cls_cnt 0 2006.162.07:43:11.09#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.162.07:43:11.21#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.162.07:43:11.21#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.162.07:43:11.21#ibcon#enter wrdev, iclass 35, count 0 2006.162.07:43:11.21#ibcon#first serial, iclass 35, count 0 2006.162.07:43:11.21#ibcon#enter sib2, iclass 35, count 0 2006.162.07:43:11.21#ibcon#flushed, iclass 35, count 0 2006.162.07:43:11.21#ibcon#about to write, iclass 35, count 0 2006.162.07:43:11.21#ibcon#wrote, iclass 35, count 0 2006.162.07:43:11.21#ibcon#about to read 3, iclass 35, count 0 2006.162.07:43:11.23#ibcon#read 3, iclass 35, count 0 2006.162.07:43:11.23#ibcon#about to read 4, iclass 35, count 0 2006.162.07:43:11.23#ibcon#read 4, iclass 35, count 0 2006.162.07:43:11.23#ibcon#about to read 5, iclass 35, count 0 2006.162.07:43:11.23#ibcon#read 5, iclass 35, count 0 2006.162.07:43:11.23#ibcon#about to read 6, iclass 35, count 0 2006.162.07:43:11.23#ibcon#read 6, iclass 35, count 0 2006.162.07:43:11.23#ibcon#end of sib2, iclass 35, count 0 2006.162.07:43:11.23#ibcon#*mode == 0, iclass 35, count 0 2006.162.07:43:11.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.162.07:43:11.23#ibcon#[25=USB\r\n] 2006.162.07:43:11.23#ibcon#*before write, iclass 35, count 0 2006.162.07:43:11.23#ibcon#enter sib2, iclass 35, count 0 2006.162.07:43:11.23#ibcon#flushed, iclass 35, count 0 2006.162.07:43:11.23#ibcon#about to write, iclass 35, count 0 2006.162.07:43:11.23#ibcon#wrote, iclass 35, count 0 2006.162.07:43:11.23#ibcon#about to read 3, iclass 35, count 0 2006.162.07:43:11.26#ibcon#read 3, iclass 35, count 0 2006.162.07:43:11.26#ibcon#about to read 4, iclass 35, count 0 2006.162.07:43:11.26#ibcon#read 4, iclass 35, count 0 2006.162.07:43:11.26#ibcon#about to read 5, iclass 35, count 0 2006.162.07:43:11.26#ibcon#read 5, iclass 35, count 0 2006.162.07:43:11.26#ibcon#about to read 6, iclass 35, count 0 2006.162.07:43:11.26#ibcon#read 6, iclass 35, count 0 2006.162.07:43:11.26#ibcon#end of sib2, iclass 35, count 0 2006.162.07:43:11.26#ibcon#*after write, iclass 35, count 0 2006.162.07:43:11.26#ibcon#*before return 0, iclass 35, count 0 2006.162.07:43:11.26#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.162.07:43:11.26#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.162.07:43:11.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.162.07:43:11.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.162.07:43:11.26$vc4f8/valo=7,832.99 2006.162.07:43:11.26#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.162.07:43:11.26#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.162.07:43:11.26#ibcon#ireg 17 cls_cnt 0 2006.162.07:43:11.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.162.07:43:11.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.162.07:43:11.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.162.07:43:11.26#ibcon#enter wrdev, iclass 37, count 0 2006.162.07:43:11.26#ibcon#first serial, iclass 37, count 0 2006.162.07:43:11.26#ibcon#enter sib2, iclass 37, count 0 2006.162.07:43:11.26#ibcon#flushed, iclass 37, count 0 2006.162.07:43:11.26#ibcon#about to write, iclass 37, count 0 2006.162.07:43:11.26#ibcon#wrote, iclass 37, count 0 2006.162.07:43:11.26#ibcon#about to read 3, iclass 37, count 0 2006.162.07:43:11.28#ibcon#read 3, iclass 37, count 0 2006.162.07:43:11.28#ibcon#about to read 4, iclass 37, count 0 2006.162.07:43:11.28#ibcon#read 4, iclass 37, count 0 2006.162.07:43:11.28#ibcon#about to read 5, iclass 37, count 0 2006.162.07:43:11.28#ibcon#read 5, iclass 37, count 0 2006.162.07:43:11.28#ibcon#about to read 6, iclass 37, count 0 2006.162.07:43:11.28#ibcon#read 6, iclass 37, count 0 2006.162.07:43:11.28#ibcon#end of sib2, iclass 37, count 0 2006.162.07:43:11.28#ibcon#*mode == 0, iclass 37, count 0 2006.162.07:43:11.28#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.162.07:43:11.28#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.07:43:11.28#ibcon#*before write, iclass 37, count 0 2006.162.07:43:11.28#ibcon#enter sib2, iclass 37, count 0 2006.162.07:43:11.28#ibcon#flushed, iclass 37, count 0 2006.162.07:43:11.28#ibcon#about to write, iclass 37, count 0 2006.162.07:43:11.28#ibcon#wrote, iclass 37, count 0 2006.162.07:43:11.28#ibcon#about to read 3, iclass 37, count 0 2006.162.07:43:11.32#ibcon#read 3, iclass 37, count 0 2006.162.07:43:11.32#ibcon#about to read 4, iclass 37, count 0 2006.162.07:43:11.32#ibcon#read 4, iclass 37, count 0 2006.162.07:43:11.32#ibcon#about to read 5, iclass 37, count 0 2006.162.07:43:11.32#ibcon#read 5, iclass 37, count 0 2006.162.07:43:11.32#ibcon#about to read 6, iclass 37, count 0 2006.162.07:43:11.32#ibcon#read 6, iclass 37, count 0 2006.162.07:43:11.32#ibcon#end of sib2, iclass 37, count 0 2006.162.07:43:11.32#ibcon#*after write, iclass 37, count 0 2006.162.07:43:11.32#ibcon#*before return 0, iclass 37, count 0 2006.162.07:43:11.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.162.07:43:11.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.162.07:43:11.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.162.07:43:11.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.162.07:43:11.32$vc4f8/va=7,6 2006.162.07:43:11.32#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.162.07:43:11.32#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.162.07:43:11.32#ibcon#ireg 11 cls_cnt 2 2006.162.07:43:11.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.162.07:43:11.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.162.07:43:11.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.162.07:43:11.38#ibcon#enter wrdev, iclass 39, count 2 2006.162.07:43:11.38#ibcon#first serial, iclass 39, count 2 2006.162.07:43:11.38#ibcon#enter sib2, iclass 39, count 2 2006.162.07:43:11.38#ibcon#flushed, iclass 39, count 2 2006.162.07:43:11.38#ibcon#about to write, iclass 39, count 2 2006.162.07:43:11.38#ibcon#wrote, iclass 39, count 2 2006.162.07:43:11.38#ibcon#about to read 3, iclass 39, count 2 2006.162.07:43:11.40#ibcon#read 3, iclass 39, count 2 2006.162.07:43:11.40#ibcon#about to read 4, iclass 39, count 2 2006.162.07:43:11.40#ibcon#read 4, iclass 39, count 2 2006.162.07:43:11.40#ibcon#about to read 5, iclass 39, count 2 2006.162.07:43:11.40#ibcon#read 5, iclass 39, count 2 2006.162.07:43:11.40#ibcon#about to read 6, iclass 39, count 2 2006.162.07:43:11.40#ibcon#read 6, iclass 39, count 2 2006.162.07:43:11.40#ibcon#end of sib2, iclass 39, count 2 2006.162.07:43:11.40#ibcon#*mode == 0, iclass 39, count 2 2006.162.07:43:11.40#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.162.07:43:11.40#ibcon#[25=AT07-06\r\n] 2006.162.07:43:11.40#ibcon#*before write, iclass 39, count 2 2006.162.07:43:11.40#ibcon#enter sib2, iclass 39, count 2 2006.162.07:43:11.40#ibcon#flushed, iclass 39, count 2 2006.162.07:43:11.40#ibcon#about to write, iclass 39, count 2 2006.162.07:43:11.40#ibcon#wrote, iclass 39, count 2 2006.162.07:43:11.40#ibcon#about to read 3, iclass 39, count 2 2006.162.07:43:11.43#ibcon#read 3, iclass 39, count 2 2006.162.07:43:11.43#ibcon#about to read 4, iclass 39, count 2 2006.162.07:43:11.43#ibcon#read 4, iclass 39, count 2 2006.162.07:43:11.43#ibcon#about to read 5, iclass 39, count 2 2006.162.07:43:11.43#ibcon#read 5, iclass 39, count 2 2006.162.07:43:11.43#ibcon#about to read 6, iclass 39, count 2 2006.162.07:43:11.43#ibcon#read 6, iclass 39, count 2 2006.162.07:43:11.43#ibcon#end of sib2, iclass 39, count 2 2006.162.07:43:11.43#ibcon#*after write, iclass 39, count 2 2006.162.07:43:11.43#ibcon#*before return 0, iclass 39, count 2 2006.162.07:43:11.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.162.07:43:11.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.162.07:43:11.43#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.162.07:43:11.43#ibcon#ireg 7 cls_cnt 0 2006.162.07:43:11.43#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.162.07:43:11.55#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.162.07:43:11.55#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.162.07:43:11.55#ibcon#enter wrdev, iclass 39, count 0 2006.162.07:43:11.55#ibcon#first serial, iclass 39, count 0 2006.162.07:43:11.55#ibcon#enter sib2, iclass 39, count 0 2006.162.07:43:11.55#ibcon#flushed, iclass 39, count 0 2006.162.07:43:11.55#ibcon#about to write, iclass 39, count 0 2006.162.07:43:11.55#ibcon#wrote, iclass 39, count 0 2006.162.07:43:11.55#ibcon#about to read 3, iclass 39, count 0 2006.162.07:43:11.57#ibcon#read 3, iclass 39, count 0 2006.162.07:43:11.57#ibcon#about to read 4, iclass 39, count 0 2006.162.07:43:11.57#ibcon#read 4, iclass 39, count 0 2006.162.07:43:11.57#ibcon#about to read 5, iclass 39, count 0 2006.162.07:43:11.57#ibcon#read 5, iclass 39, count 0 2006.162.07:43:11.57#ibcon#about to read 6, iclass 39, count 0 2006.162.07:43:11.57#ibcon#read 6, iclass 39, count 0 2006.162.07:43:11.57#ibcon#end of sib2, iclass 39, count 0 2006.162.07:43:11.57#ibcon#*mode == 0, iclass 39, count 0 2006.162.07:43:11.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.162.07:43:11.57#ibcon#[25=USB\r\n] 2006.162.07:43:11.57#ibcon#*before write, iclass 39, count 0 2006.162.07:43:11.57#ibcon#enter sib2, iclass 39, count 0 2006.162.07:43:11.57#ibcon#flushed, iclass 39, count 0 2006.162.07:43:11.57#ibcon#about to write, iclass 39, count 0 2006.162.07:43:11.57#ibcon#wrote, iclass 39, count 0 2006.162.07:43:11.57#ibcon#about to read 3, iclass 39, count 0 2006.162.07:43:11.60#ibcon#read 3, iclass 39, count 0 2006.162.07:43:11.60#ibcon#about to read 4, iclass 39, count 0 2006.162.07:43:11.60#ibcon#read 4, iclass 39, count 0 2006.162.07:43:11.60#ibcon#about to read 5, iclass 39, count 0 2006.162.07:43:11.60#ibcon#read 5, iclass 39, count 0 2006.162.07:43:11.60#ibcon#about to read 6, iclass 39, count 0 2006.162.07:43:11.60#ibcon#read 6, iclass 39, count 0 2006.162.07:43:11.60#ibcon#end of sib2, iclass 39, count 0 2006.162.07:43:11.60#ibcon#*after write, iclass 39, count 0 2006.162.07:43:11.60#ibcon#*before return 0, iclass 39, count 0 2006.162.07:43:11.60#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.162.07:43:11.60#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.162.07:43:11.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.162.07:43:11.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.162.07:43:11.60$vc4f8/valo=8,852.99 2006.162.07:43:11.60#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.162.07:43:11.60#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.162.07:43:11.60#ibcon#ireg 17 cls_cnt 0 2006.162.07:43:11.60#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.162.07:43:11.60#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.162.07:43:11.60#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.162.07:43:11.60#ibcon#enter wrdev, iclass 3, count 0 2006.162.07:43:11.60#ibcon#first serial, iclass 3, count 0 2006.162.07:43:11.60#ibcon#enter sib2, iclass 3, count 0 2006.162.07:43:11.60#ibcon#flushed, iclass 3, count 0 2006.162.07:43:11.60#ibcon#about to write, iclass 3, count 0 2006.162.07:43:11.60#ibcon#wrote, iclass 3, count 0 2006.162.07:43:11.60#ibcon#about to read 3, iclass 3, count 0 2006.162.07:43:11.62#ibcon#read 3, iclass 3, count 0 2006.162.07:43:11.62#ibcon#about to read 4, iclass 3, count 0 2006.162.07:43:11.62#ibcon#read 4, iclass 3, count 0 2006.162.07:43:11.62#ibcon#about to read 5, iclass 3, count 0 2006.162.07:43:11.62#ibcon#read 5, iclass 3, count 0 2006.162.07:43:11.62#ibcon#about to read 6, iclass 3, count 0 2006.162.07:43:11.62#ibcon#read 6, iclass 3, count 0 2006.162.07:43:11.62#ibcon#end of sib2, iclass 3, count 0 2006.162.07:43:11.62#ibcon#*mode == 0, iclass 3, count 0 2006.162.07:43:11.62#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.162.07:43:11.62#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.07:43:11.62#ibcon#*before write, iclass 3, count 0 2006.162.07:43:11.62#ibcon#enter sib2, iclass 3, count 0 2006.162.07:43:11.62#ibcon#flushed, iclass 3, count 0 2006.162.07:43:11.62#ibcon#about to write, iclass 3, count 0 2006.162.07:43:11.62#ibcon#wrote, iclass 3, count 0 2006.162.07:43:11.62#ibcon#about to read 3, iclass 3, count 0 2006.162.07:43:11.66#ibcon#read 3, iclass 3, count 0 2006.162.07:43:11.66#ibcon#about to read 4, iclass 3, count 0 2006.162.07:43:11.66#ibcon#read 4, iclass 3, count 0 2006.162.07:43:11.66#ibcon#about to read 5, iclass 3, count 0 2006.162.07:43:11.66#ibcon#read 5, iclass 3, count 0 2006.162.07:43:11.66#ibcon#about to read 6, iclass 3, count 0 2006.162.07:43:11.66#ibcon#read 6, iclass 3, count 0 2006.162.07:43:11.66#ibcon#end of sib2, iclass 3, count 0 2006.162.07:43:11.66#ibcon#*after write, iclass 3, count 0 2006.162.07:43:11.66#ibcon#*before return 0, iclass 3, count 0 2006.162.07:43:11.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.162.07:43:11.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.162.07:43:11.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.162.07:43:11.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.162.07:43:11.66$vc4f8/va=8,7 2006.162.07:43:11.66#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.162.07:43:11.66#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.162.07:43:11.66#ibcon#ireg 11 cls_cnt 2 2006.162.07:43:11.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.162.07:43:11.72#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.162.07:43:11.72#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.162.07:43:11.72#ibcon#enter wrdev, iclass 5, count 2 2006.162.07:43:11.72#ibcon#first serial, iclass 5, count 2 2006.162.07:43:11.72#ibcon#enter sib2, iclass 5, count 2 2006.162.07:43:11.72#ibcon#flushed, iclass 5, count 2 2006.162.07:43:11.72#ibcon#about to write, iclass 5, count 2 2006.162.07:43:11.72#ibcon#wrote, iclass 5, count 2 2006.162.07:43:11.72#ibcon#about to read 3, iclass 5, count 2 2006.162.07:43:11.74#ibcon#read 3, iclass 5, count 2 2006.162.07:43:11.74#ibcon#about to read 4, iclass 5, count 2 2006.162.07:43:11.74#ibcon#read 4, iclass 5, count 2 2006.162.07:43:11.74#ibcon#about to read 5, iclass 5, count 2 2006.162.07:43:11.74#ibcon#read 5, iclass 5, count 2 2006.162.07:43:11.74#ibcon#about to read 6, iclass 5, count 2 2006.162.07:43:11.74#ibcon#read 6, iclass 5, count 2 2006.162.07:43:11.74#ibcon#end of sib2, iclass 5, count 2 2006.162.07:43:11.74#ibcon#*mode == 0, iclass 5, count 2 2006.162.07:43:11.74#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.162.07:43:11.74#ibcon#[25=AT08-07\r\n] 2006.162.07:43:11.74#ibcon#*before write, iclass 5, count 2 2006.162.07:43:11.74#ibcon#enter sib2, iclass 5, count 2 2006.162.07:43:11.74#ibcon#flushed, iclass 5, count 2 2006.162.07:43:11.74#ibcon#about to write, iclass 5, count 2 2006.162.07:43:11.74#ibcon#wrote, iclass 5, count 2 2006.162.07:43:11.74#ibcon#about to read 3, iclass 5, count 2 2006.162.07:43:11.77#ibcon#read 3, iclass 5, count 2 2006.162.07:43:11.77#ibcon#about to read 4, iclass 5, count 2 2006.162.07:43:11.77#ibcon#read 4, iclass 5, count 2 2006.162.07:43:11.77#ibcon#about to read 5, iclass 5, count 2 2006.162.07:43:11.77#ibcon#read 5, iclass 5, count 2 2006.162.07:43:11.77#ibcon#about to read 6, iclass 5, count 2 2006.162.07:43:11.77#ibcon#read 6, iclass 5, count 2 2006.162.07:43:11.77#ibcon#end of sib2, iclass 5, count 2 2006.162.07:43:11.77#ibcon#*after write, iclass 5, count 2 2006.162.07:43:11.77#ibcon#*before return 0, iclass 5, count 2 2006.162.07:43:11.77#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.162.07:43:11.77#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.162.07:43:11.77#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.162.07:43:11.77#ibcon#ireg 7 cls_cnt 0 2006.162.07:43:11.77#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.162.07:43:11.89#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.162.07:43:11.89#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.162.07:43:11.89#ibcon#enter wrdev, iclass 5, count 0 2006.162.07:43:11.89#ibcon#first serial, iclass 5, count 0 2006.162.07:43:11.89#ibcon#enter sib2, iclass 5, count 0 2006.162.07:43:11.89#ibcon#flushed, iclass 5, count 0 2006.162.07:43:11.89#ibcon#about to write, iclass 5, count 0 2006.162.07:43:11.89#ibcon#wrote, iclass 5, count 0 2006.162.07:43:11.89#ibcon#about to read 3, iclass 5, count 0 2006.162.07:43:11.91#ibcon#read 3, iclass 5, count 0 2006.162.07:43:11.91#ibcon#about to read 4, iclass 5, count 0 2006.162.07:43:11.91#ibcon#read 4, iclass 5, count 0 2006.162.07:43:11.91#ibcon#about to read 5, iclass 5, count 0 2006.162.07:43:11.91#ibcon#read 5, iclass 5, count 0 2006.162.07:43:11.91#ibcon#about to read 6, iclass 5, count 0 2006.162.07:43:11.91#ibcon#read 6, iclass 5, count 0 2006.162.07:43:11.91#ibcon#end of sib2, iclass 5, count 0 2006.162.07:43:11.91#ibcon#*mode == 0, iclass 5, count 0 2006.162.07:43:11.91#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.162.07:43:11.91#ibcon#[25=USB\r\n] 2006.162.07:43:11.91#ibcon#*before write, iclass 5, count 0 2006.162.07:43:11.91#ibcon#enter sib2, iclass 5, count 0 2006.162.07:43:11.91#ibcon#flushed, iclass 5, count 0 2006.162.07:43:11.91#ibcon#about to write, iclass 5, count 0 2006.162.07:43:11.91#ibcon#wrote, iclass 5, count 0 2006.162.07:43:11.91#ibcon#about to read 3, iclass 5, count 0 2006.162.07:43:11.94#ibcon#read 3, iclass 5, count 0 2006.162.07:43:11.94#ibcon#about to read 4, iclass 5, count 0 2006.162.07:43:11.94#ibcon#read 4, iclass 5, count 0 2006.162.07:43:11.94#ibcon#about to read 5, iclass 5, count 0 2006.162.07:43:11.94#ibcon#read 5, iclass 5, count 0 2006.162.07:43:11.94#ibcon#about to read 6, iclass 5, count 0 2006.162.07:43:11.94#ibcon#read 6, iclass 5, count 0 2006.162.07:43:11.94#ibcon#end of sib2, iclass 5, count 0 2006.162.07:43:11.94#ibcon#*after write, iclass 5, count 0 2006.162.07:43:11.94#ibcon#*before return 0, iclass 5, count 0 2006.162.07:43:11.94#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.162.07:43:11.94#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.162.07:43:11.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.162.07:43:11.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.162.07:43:11.94$vc4f8/vblo=1,632.99 2006.162.07:43:11.94#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.162.07:43:11.94#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.162.07:43:11.94#ibcon#ireg 17 cls_cnt 0 2006.162.07:43:11.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:43:11.94#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:43:11.94#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:43:11.94#ibcon#enter wrdev, iclass 7, count 0 2006.162.07:43:11.94#ibcon#first serial, iclass 7, count 0 2006.162.07:43:11.94#ibcon#enter sib2, iclass 7, count 0 2006.162.07:43:11.94#ibcon#flushed, iclass 7, count 0 2006.162.07:43:11.94#ibcon#about to write, iclass 7, count 0 2006.162.07:43:11.94#ibcon#wrote, iclass 7, count 0 2006.162.07:43:11.94#ibcon#about to read 3, iclass 7, count 0 2006.162.07:43:11.96#ibcon#read 3, iclass 7, count 0 2006.162.07:43:11.96#ibcon#about to read 4, iclass 7, count 0 2006.162.07:43:11.96#ibcon#read 4, iclass 7, count 0 2006.162.07:43:11.96#ibcon#about to read 5, iclass 7, count 0 2006.162.07:43:11.96#ibcon#read 5, iclass 7, count 0 2006.162.07:43:11.96#ibcon#about to read 6, iclass 7, count 0 2006.162.07:43:11.96#ibcon#read 6, iclass 7, count 0 2006.162.07:43:11.96#ibcon#end of sib2, iclass 7, count 0 2006.162.07:43:11.96#ibcon#*mode == 0, iclass 7, count 0 2006.162.07:43:11.96#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.162.07:43:11.96#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.07:43:11.96#ibcon#*before write, iclass 7, count 0 2006.162.07:43:11.96#ibcon#enter sib2, iclass 7, count 0 2006.162.07:43:11.96#ibcon#flushed, iclass 7, count 0 2006.162.07:43:11.96#ibcon#about to write, iclass 7, count 0 2006.162.07:43:11.96#ibcon#wrote, iclass 7, count 0 2006.162.07:43:11.96#ibcon#about to read 3, iclass 7, count 0 2006.162.07:43:12.00#ibcon#read 3, iclass 7, count 0 2006.162.07:43:12.00#ibcon#about to read 4, iclass 7, count 0 2006.162.07:43:12.00#ibcon#read 4, iclass 7, count 0 2006.162.07:43:12.00#ibcon#about to read 5, iclass 7, count 0 2006.162.07:43:12.00#ibcon#read 5, iclass 7, count 0 2006.162.07:43:12.00#ibcon#about to read 6, iclass 7, count 0 2006.162.07:43:12.00#ibcon#read 6, iclass 7, count 0 2006.162.07:43:12.00#ibcon#end of sib2, iclass 7, count 0 2006.162.07:43:12.00#ibcon#*after write, iclass 7, count 0 2006.162.07:43:12.00#ibcon#*before return 0, iclass 7, count 0 2006.162.07:43:12.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:43:12.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:43:12.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.162.07:43:12.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.162.07:43:12.00$vc4f8/vb=1,4 2006.162.07:43:12.00#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.162.07:43:12.00#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.162.07:43:12.00#ibcon#ireg 11 cls_cnt 2 2006.162.07:43:12.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:43:12.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:43:12.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:43:12.00#ibcon#enter wrdev, iclass 11, count 2 2006.162.07:43:12.00#ibcon#first serial, iclass 11, count 2 2006.162.07:43:12.00#ibcon#enter sib2, iclass 11, count 2 2006.162.07:43:12.00#ibcon#flushed, iclass 11, count 2 2006.162.07:43:12.00#ibcon#about to write, iclass 11, count 2 2006.162.07:43:12.00#ibcon#wrote, iclass 11, count 2 2006.162.07:43:12.00#ibcon#about to read 3, iclass 11, count 2 2006.162.07:43:12.02#ibcon#read 3, iclass 11, count 2 2006.162.07:43:12.02#ibcon#about to read 4, iclass 11, count 2 2006.162.07:43:12.02#ibcon#read 4, iclass 11, count 2 2006.162.07:43:12.02#ibcon#about to read 5, iclass 11, count 2 2006.162.07:43:12.02#ibcon#read 5, iclass 11, count 2 2006.162.07:43:12.02#ibcon#about to read 6, iclass 11, count 2 2006.162.07:43:12.02#ibcon#read 6, iclass 11, count 2 2006.162.07:43:12.02#ibcon#end of sib2, iclass 11, count 2 2006.162.07:43:12.02#ibcon#*mode == 0, iclass 11, count 2 2006.162.07:43:12.02#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.162.07:43:12.02#ibcon#[27=AT01-04\r\n] 2006.162.07:43:12.02#ibcon#*before write, iclass 11, count 2 2006.162.07:43:12.02#ibcon#enter sib2, iclass 11, count 2 2006.162.07:43:12.02#ibcon#flushed, iclass 11, count 2 2006.162.07:43:12.02#ibcon#about to write, iclass 11, count 2 2006.162.07:43:12.02#ibcon#wrote, iclass 11, count 2 2006.162.07:43:12.02#ibcon#about to read 3, iclass 11, count 2 2006.162.07:43:12.05#ibcon#read 3, iclass 11, count 2 2006.162.07:43:12.05#ibcon#about to read 4, iclass 11, count 2 2006.162.07:43:12.05#ibcon#read 4, iclass 11, count 2 2006.162.07:43:12.05#ibcon#about to read 5, iclass 11, count 2 2006.162.07:43:12.05#ibcon#read 5, iclass 11, count 2 2006.162.07:43:12.05#ibcon#about to read 6, iclass 11, count 2 2006.162.07:43:12.05#ibcon#read 6, iclass 11, count 2 2006.162.07:43:12.05#ibcon#end of sib2, iclass 11, count 2 2006.162.07:43:12.05#ibcon#*after write, iclass 11, count 2 2006.162.07:43:12.05#ibcon#*before return 0, iclass 11, count 2 2006.162.07:43:12.05#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:43:12.05#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:43:12.05#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.162.07:43:12.05#ibcon#ireg 7 cls_cnt 0 2006.162.07:43:12.05#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:43:12.17#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:43:12.17#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:43:12.17#ibcon#enter wrdev, iclass 11, count 0 2006.162.07:43:12.17#ibcon#first serial, iclass 11, count 0 2006.162.07:43:12.17#ibcon#enter sib2, iclass 11, count 0 2006.162.07:43:12.17#ibcon#flushed, iclass 11, count 0 2006.162.07:43:12.17#ibcon#about to write, iclass 11, count 0 2006.162.07:43:12.17#ibcon#wrote, iclass 11, count 0 2006.162.07:43:12.17#ibcon#about to read 3, iclass 11, count 0 2006.162.07:43:12.19#ibcon#read 3, iclass 11, count 0 2006.162.07:43:12.19#ibcon#about to read 4, iclass 11, count 0 2006.162.07:43:12.19#ibcon#read 4, iclass 11, count 0 2006.162.07:43:12.19#ibcon#about to read 5, iclass 11, count 0 2006.162.07:43:12.19#ibcon#read 5, iclass 11, count 0 2006.162.07:43:12.19#ibcon#about to read 6, iclass 11, count 0 2006.162.07:43:12.19#ibcon#read 6, iclass 11, count 0 2006.162.07:43:12.19#ibcon#end of sib2, iclass 11, count 0 2006.162.07:43:12.19#ibcon#*mode == 0, iclass 11, count 0 2006.162.07:43:12.19#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.162.07:43:12.19#ibcon#[27=USB\r\n] 2006.162.07:43:12.19#ibcon#*before write, iclass 11, count 0 2006.162.07:43:12.19#ibcon#enter sib2, iclass 11, count 0 2006.162.07:43:12.19#ibcon#flushed, iclass 11, count 0 2006.162.07:43:12.19#ibcon#about to write, iclass 11, count 0 2006.162.07:43:12.19#ibcon#wrote, iclass 11, count 0 2006.162.07:43:12.19#ibcon#about to read 3, iclass 11, count 0 2006.162.07:43:12.22#ibcon#read 3, iclass 11, count 0 2006.162.07:43:12.22#ibcon#about to read 4, iclass 11, count 0 2006.162.07:43:12.22#ibcon#read 4, iclass 11, count 0 2006.162.07:43:12.22#ibcon#about to read 5, iclass 11, count 0 2006.162.07:43:12.22#ibcon#read 5, iclass 11, count 0 2006.162.07:43:12.22#ibcon#about to read 6, iclass 11, count 0 2006.162.07:43:12.22#ibcon#read 6, iclass 11, count 0 2006.162.07:43:12.22#ibcon#end of sib2, iclass 11, count 0 2006.162.07:43:12.22#ibcon#*after write, iclass 11, count 0 2006.162.07:43:12.22#ibcon#*before return 0, iclass 11, count 0 2006.162.07:43:12.22#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:43:12.22#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:43:12.22#ibcon#about to clear, iclass 11 cls_cnt 0 2006.162.07:43:12.22#ibcon#cleared, iclass 11 cls_cnt 0 2006.162.07:43:12.22$vc4f8/vblo=2,640.99 2006.162.07:43:12.22#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.162.07:43:12.22#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.162.07:43:12.22#ibcon#ireg 17 cls_cnt 0 2006.162.07:43:12.22#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:43:12.22#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:43:12.22#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:43:12.22#ibcon#enter wrdev, iclass 13, count 0 2006.162.07:43:12.22#ibcon#first serial, iclass 13, count 0 2006.162.07:43:12.22#ibcon#enter sib2, iclass 13, count 0 2006.162.07:43:12.22#ibcon#flushed, iclass 13, count 0 2006.162.07:43:12.22#ibcon#about to write, iclass 13, count 0 2006.162.07:43:12.22#ibcon#wrote, iclass 13, count 0 2006.162.07:43:12.22#ibcon#about to read 3, iclass 13, count 0 2006.162.07:43:12.24#ibcon#read 3, iclass 13, count 0 2006.162.07:43:12.24#ibcon#about to read 4, iclass 13, count 0 2006.162.07:43:12.24#ibcon#read 4, iclass 13, count 0 2006.162.07:43:12.24#ibcon#about to read 5, iclass 13, count 0 2006.162.07:43:12.24#ibcon#read 5, iclass 13, count 0 2006.162.07:43:12.24#ibcon#about to read 6, iclass 13, count 0 2006.162.07:43:12.24#ibcon#read 6, iclass 13, count 0 2006.162.07:43:12.24#ibcon#end of sib2, iclass 13, count 0 2006.162.07:43:12.24#ibcon#*mode == 0, iclass 13, count 0 2006.162.07:43:12.24#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.162.07:43:12.24#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.07:43:12.24#ibcon#*before write, iclass 13, count 0 2006.162.07:43:12.24#ibcon#enter sib2, iclass 13, count 0 2006.162.07:43:12.24#ibcon#flushed, iclass 13, count 0 2006.162.07:43:12.24#ibcon#about to write, iclass 13, count 0 2006.162.07:43:12.24#ibcon#wrote, iclass 13, count 0 2006.162.07:43:12.24#ibcon#about to read 3, iclass 13, count 0 2006.162.07:43:12.28#ibcon#read 3, iclass 13, count 0 2006.162.07:43:12.28#ibcon#about to read 4, iclass 13, count 0 2006.162.07:43:12.28#ibcon#read 4, iclass 13, count 0 2006.162.07:43:12.28#ibcon#about to read 5, iclass 13, count 0 2006.162.07:43:12.28#ibcon#read 5, iclass 13, count 0 2006.162.07:43:12.28#ibcon#about to read 6, iclass 13, count 0 2006.162.07:43:12.28#ibcon#read 6, iclass 13, count 0 2006.162.07:43:12.28#ibcon#end of sib2, iclass 13, count 0 2006.162.07:43:12.28#ibcon#*after write, iclass 13, count 0 2006.162.07:43:12.28#ibcon#*before return 0, iclass 13, count 0 2006.162.07:43:12.28#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:43:12.28#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:43:12.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.162.07:43:12.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.162.07:43:12.28$vc4f8/vb=2,4 2006.162.07:43:12.28#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.162.07:43:12.28#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.162.07:43:12.28#ibcon#ireg 11 cls_cnt 2 2006.162.07:43:12.28#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:43:12.34#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:43:12.34#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:43:12.34#ibcon#enter wrdev, iclass 15, count 2 2006.162.07:43:12.34#ibcon#first serial, iclass 15, count 2 2006.162.07:43:12.34#ibcon#enter sib2, iclass 15, count 2 2006.162.07:43:12.34#ibcon#flushed, iclass 15, count 2 2006.162.07:43:12.34#ibcon#about to write, iclass 15, count 2 2006.162.07:43:12.34#ibcon#wrote, iclass 15, count 2 2006.162.07:43:12.34#ibcon#about to read 3, iclass 15, count 2 2006.162.07:43:12.36#ibcon#read 3, iclass 15, count 2 2006.162.07:43:12.36#ibcon#about to read 4, iclass 15, count 2 2006.162.07:43:12.36#ibcon#read 4, iclass 15, count 2 2006.162.07:43:12.36#ibcon#about to read 5, iclass 15, count 2 2006.162.07:43:12.36#ibcon#read 5, iclass 15, count 2 2006.162.07:43:12.36#ibcon#about to read 6, iclass 15, count 2 2006.162.07:43:12.36#ibcon#read 6, iclass 15, count 2 2006.162.07:43:12.36#ibcon#end of sib2, iclass 15, count 2 2006.162.07:43:12.36#ibcon#*mode == 0, iclass 15, count 2 2006.162.07:43:12.36#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.162.07:43:12.36#ibcon#[27=AT02-04\r\n] 2006.162.07:43:12.36#ibcon#*before write, iclass 15, count 2 2006.162.07:43:12.36#ibcon#enter sib2, iclass 15, count 2 2006.162.07:43:12.36#ibcon#flushed, iclass 15, count 2 2006.162.07:43:12.36#ibcon#about to write, iclass 15, count 2 2006.162.07:43:12.36#ibcon#wrote, iclass 15, count 2 2006.162.07:43:12.36#ibcon#about to read 3, iclass 15, count 2 2006.162.07:43:12.39#ibcon#read 3, iclass 15, count 2 2006.162.07:43:12.39#ibcon#about to read 4, iclass 15, count 2 2006.162.07:43:12.39#ibcon#read 4, iclass 15, count 2 2006.162.07:43:12.39#ibcon#about to read 5, iclass 15, count 2 2006.162.07:43:12.39#ibcon#read 5, iclass 15, count 2 2006.162.07:43:12.39#ibcon#about to read 6, iclass 15, count 2 2006.162.07:43:12.39#ibcon#read 6, iclass 15, count 2 2006.162.07:43:12.39#ibcon#end of sib2, iclass 15, count 2 2006.162.07:43:12.39#ibcon#*after write, iclass 15, count 2 2006.162.07:43:12.39#ibcon#*before return 0, iclass 15, count 2 2006.162.07:43:12.39#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:43:12.39#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:43:12.39#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.162.07:43:12.39#ibcon#ireg 7 cls_cnt 0 2006.162.07:43:12.39#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:43:12.51#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:43:12.51#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:43:12.51#ibcon#enter wrdev, iclass 15, count 0 2006.162.07:43:12.51#ibcon#first serial, iclass 15, count 0 2006.162.07:43:12.51#ibcon#enter sib2, iclass 15, count 0 2006.162.07:43:12.51#ibcon#flushed, iclass 15, count 0 2006.162.07:43:12.51#ibcon#about to write, iclass 15, count 0 2006.162.07:43:12.51#ibcon#wrote, iclass 15, count 0 2006.162.07:43:12.51#ibcon#about to read 3, iclass 15, count 0 2006.162.07:43:12.53#ibcon#read 3, iclass 15, count 0 2006.162.07:43:12.53#ibcon#about to read 4, iclass 15, count 0 2006.162.07:43:12.53#ibcon#read 4, iclass 15, count 0 2006.162.07:43:12.53#ibcon#about to read 5, iclass 15, count 0 2006.162.07:43:12.53#ibcon#read 5, iclass 15, count 0 2006.162.07:43:12.53#ibcon#about to read 6, iclass 15, count 0 2006.162.07:43:12.53#ibcon#read 6, iclass 15, count 0 2006.162.07:43:12.53#ibcon#end of sib2, iclass 15, count 0 2006.162.07:43:12.53#ibcon#*mode == 0, iclass 15, count 0 2006.162.07:43:12.53#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.162.07:43:12.53#ibcon#[27=USB\r\n] 2006.162.07:43:12.53#ibcon#*before write, iclass 15, count 0 2006.162.07:43:12.53#ibcon#enter sib2, iclass 15, count 0 2006.162.07:43:12.53#ibcon#flushed, iclass 15, count 0 2006.162.07:43:12.53#ibcon#about to write, iclass 15, count 0 2006.162.07:43:12.53#ibcon#wrote, iclass 15, count 0 2006.162.07:43:12.53#ibcon#about to read 3, iclass 15, count 0 2006.162.07:43:12.56#ibcon#read 3, iclass 15, count 0 2006.162.07:43:12.56#ibcon#about to read 4, iclass 15, count 0 2006.162.07:43:12.56#ibcon#read 4, iclass 15, count 0 2006.162.07:43:12.56#ibcon#about to read 5, iclass 15, count 0 2006.162.07:43:12.56#ibcon#read 5, iclass 15, count 0 2006.162.07:43:12.56#ibcon#about to read 6, iclass 15, count 0 2006.162.07:43:12.56#ibcon#read 6, iclass 15, count 0 2006.162.07:43:12.56#ibcon#end of sib2, iclass 15, count 0 2006.162.07:43:12.56#ibcon#*after write, iclass 15, count 0 2006.162.07:43:12.56#ibcon#*before return 0, iclass 15, count 0 2006.162.07:43:12.56#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:43:12.56#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:43:12.56#ibcon#about to clear, iclass 15 cls_cnt 0 2006.162.07:43:12.56#ibcon#cleared, iclass 15 cls_cnt 0 2006.162.07:43:12.56$vc4f8/vblo=3,656.99 2006.162.07:43:12.56#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.162.07:43:12.56#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.162.07:43:12.56#ibcon#ireg 17 cls_cnt 0 2006.162.07:43:12.56#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:43:12.56#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:43:12.56#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:43:12.56#ibcon#enter wrdev, iclass 17, count 0 2006.162.07:43:12.56#ibcon#first serial, iclass 17, count 0 2006.162.07:43:12.56#ibcon#enter sib2, iclass 17, count 0 2006.162.07:43:12.56#ibcon#flushed, iclass 17, count 0 2006.162.07:43:12.56#ibcon#about to write, iclass 17, count 0 2006.162.07:43:12.56#ibcon#wrote, iclass 17, count 0 2006.162.07:43:12.56#ibcon#about to read 3, iclass 17, count 0 2006.162.07:43:12.58#ibcon#read 3, iclass 17, count 0 2006.162.07:43:12.58#ibcon#about to read 4, iclass 17, count 0 2006.162.07:43:12.58#ibcon#read 4, iclass 17, count 0 2006.162.07:43:12.58#ibcon#about to read 5, iclass 17, count 0 2006.162.07:43:12.58#ibcon#read 5, iclass 17, count 0 2006.162.07:43:12.58#ibcon#about to read 6, iclass 17, count 0 2006.162.07:43:12.58#ibcon#read 6, iclass 17, count 0 2006.162.07:43:12.58#ibcon#end of sib2, iclass 17, count 0 2006.162.07:43:12.58#ibcon#*mode == 0, iclass 17, count 0 2006.162.07:43:12.58#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.162.07:43:12.58#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.07:43:12.58#ibcon#*before write, iclass 17, count 0 2006.162.07:43:12.58#ibcon#enter sib2, iclass 17, count 0 2006.162.07:43:12.58#ibcon#flushed, iclass 17, count 0 2006.162.07:43:12.58#ibcon#about to write, iclass 17, count 0 2006.162.07:43:12.58#ibcon#wrote, iclass 17, count 0 2006.162.07:43:12.58#ibcon#about to read 3, iclass 17, count 0 2006.162.07:43:12.62#ibcon#read 3, iclass 17, count 0 2006.162.07:43:12.62#ibcon#about to read 4, iclass 17, count 0 2006.162.07:43:12.62#ibcon#read 4, iclass 17, count 0 2006.162.07:43:12.62#ibcon#about to read 5, iclass 17, count 0 2006.162.07:43:12.62#ibcon#read 5, iclass 17, count 0 2006.162.07:43:12.62#ibcon#about to read 6, iclass 17, count 0 2006.162.07:43:12.62#ibcon#read 6, iclass 17, count 0 2006.162.07:43:12.62#ibcon#end of sib2, iclass 17, count 0 2006.162.07:43:12.62#ibcon#*after write, iclass 17, count 0 2006.162.07:43:12.62#ibcon#*before return 0, iclass 17, count 0 2006.162.07:43:12.62#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:43:12.62#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:43:12.62#ibcon#about to clear, iclass 17 cls_cnt 0 2006.162.07:43:12.62#ibcon#cleared, iclass 17 cls_cnt 0 2006.162.07:43:12.62$vc4f8/vb=3,4 2006.162.07:43:12.62#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.162.07:43:12.62#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.162.07:43:12.62#ibcon#ireg 11 cls_cnt 2 2006.162.07:43:12.62#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:43:12.68#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:43:12.68#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:43:12.68#ibcon#enter wrdev, iclass 19, count 2 2006.162.07:43:12.68#ibcon#first serial, iclass 19, count 2 2006.162.07:43:12.68#ibcon#enter sib2, iclass 19, count 2 2006.162.07:43:12.68#ibcon#flushed, iclass 19, count 2 2006.162.07:43:12.68#ibcon#about to write, iclass 19, count 2 2006.162.07:43:12.68#ibcon#wrote, iclass 19, count 2 2006.162.07:43:12.68#ibcon#about to read 3, iclass 19, count 2 2006.162.07:43:12.70#ibcon#read 3, iclass 19, count 2 2006.162.07:43:12.70#ibcon#about to read 4, iclass 19, count 2 2006.162.07:43:12.70#ibcon#read 4, iclass 19, count 2 2006.162.07:43:12.70#ibcon#about to read 5, iclass 19, count 2 2006.162.07:43:12.70#ibcon#read 5, iclass 19, count 2 2006.162.07:43:12.70#ibcon#about to read 6, iclass 19, count 2 2006.162.07:43:12.70#ibcon#read 6, iclass 19, count 2 2006.162.07:43:12.70#ibcon#end of sib2, iclass 19, count 2 2006.162.07:43:12.70#ibcon#*mode == 0, iclass 19, count 2 2006.162.07:43:12.70#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.162.07:43:12.70#ibcon#[27=AT03-04\r\n] 2006.162.07:43:12.70#ibcon#*before write, iclass 19, count 2 2006.162.07:43:12.70#ibcon#enter sib2, iclass 19, count 2 2006.162.07:43:12.70#ibcon#flushed, iclass 19, count 2 2006.162.07:43:12.70#ibcon#about to write, iclass 19, count 2 2006.162.07:43:12.70#ibcon#wrote, iclass 19, count 2 2006.162.07:43:12.70#ibcon#about to read 3, iclass 19, count 2 2006.162.07:43:12.73#ibcon#read 3, iclass 19, count 2 2006.162.07:43:12.73#ibcon#about to read 4, iclass 19, count 2 2006.162.07:43:12.73#ibcon#read 4, iclass 19, count 2 2006.162.07:43:12.73#ibcon#about to read 5, iclass 19, count 2 2006.162.07:43:12.73#ibcon#read 5, iclass 19, count 2 2006.162.07:43:12.73#ibcon#about to read 6, iclass 19, count 2 2006.162.07:43:12.73#ibcon#read 6, iclass 19, count 2 2006.162.07:43:12.73#ibcon#end of sib2, iclass 19, count 2 2006.162.07:43:12.73#ibcon#*after write, iclass 19, count 2 2006.162.07:43:12.73#ibcon#*before return 0, iclass 19, count 2 2006.162.07:43:12.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:43:12.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:43:12.73#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.162.07:43:12.73#ibcon#ireg 7 cls_cnt 0 2006.162.07:43:12.73#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:43:12.85#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:43:12.85#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:43:12.85#ibcon#enter wrdev, iclass 19, count 0 2006.162.07:43:12.85#ibcon#first serial, iclass 19, count 0 2006.162.07:43:12.85#ibcon#enter sib2, iclass 19, count 0 2006.162.07:43:12.85#ibcon#flushed, iclass 19, count 0 2006.162.07:43:12.85#ibcon#about to write, iclass 19, count 0 2006.162.07:43:12.85#ibcon#wrote, iclass 19, count 0 2006.162.07:43:12.85#ibcon#about to read 3, iclass 19, count 0 2006.162.07:43:12.87#ibcon#read 3, iclass 19, count 0 2006.162.07:43:12.87#ibcon#about to read 4, iclass 19, count 0 2006.162.07:43:12.87#ibcon#read 4, iclass 19, count 0 2006.162.07:43:12.87#ibcon#about to read 5, iclass 19, count 0 2006.162.07:43:12.87#ibcon#read 5, iclass 19, count 0 2006.162.07:43:12.87#ibcon#about to read 6, iclass 19, count 0 2006.162.07:43:12.87#ibcon#read 6, iclass 19, count 0 2006.162.07:43:12.87#ibcon#end of sib2, iclass 19, count 0 2006.162.07:43:12.87#ibcon#*mode == 0, iclass 19, count 0 2006.162.07:43:12.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.162.07:43:12.87#ibcon#[27=USB\r\n] 2006.162.07:43:12.87#ibcon#*before write, iclass 19, count 0 2006.162.07:43:12.87#ibcon#enter sib2, iclass 19, count 0 2006.162.07:43:12.87#ibcon#flushed, iclass 19, count 0 2006.162.07:43:12.87#ibcon#about to write, iclass 19, count 0 2006.162.07:43:12.87#ibcon#wrote, iclass 19, count 0 2006.162.07:43:12.87#ibcon#about to read 3, iclass 19, count 0 2006.162.07:43:12.90#ibcon#read 3, iclass 19, count 0 2006.162.07:43:12.90#ibcon#about to read 4, iclass 19, count 0 2006.162.07:43:12.90#ibcon#read 4, iclass 19, count 0 2006.162.07:43:12.90#ibcon#about to read 5, iclass 19, count 0 2006.162.07:43:12.90#ibcon#read 5, iclass 19, count 0 2006.162.07:43:12.90#ibcon#about to read 6, iclass 19, count 0 2006.162.07:43:12.90#ibcon#read 6, iclass 19, count 0 2006.162.07:43:12.90#ibcon#end of sib2, iclass 19, count 0 2006.162.07:43:12.90#ibcon#*after write, iclass 19, count 0 2006.162.07:43:12.90#ibcon#*before return 0, iclass 19, count 0 2006.162.07:43:12.90#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:43:12.90#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:43:12.90#ibcon#about to clear, iclass 19 cls_cnt 0 2006.162.07:43:12.90#ibcon#cleared, iclass 19 cls_cnt 0 2006.162.07:43:12.90$vc4f8/vblo=4,712.99 2006.162.07:43:12.90#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.162.07:43:12.90#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.162.07:43:12.90#ibcon#ireg 17 cls_cnt 0 2006.162.07:43:12.90#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:43:12.90#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:43:12.90#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:43:12.90#ibcon#enter wrdev, iclass 21, count 0 2006.162.07:43:12.90#ibcon#first serial, iclass 21, count 0 2006.162.07:43:12.90#ibcon#enter sib2, iclass 21, count 0 2006.162.07:43:12.90#ibcon#flushed, iclass 21, count 0 2006.162.07:43:12.90#ibcon#about to write, iclass 21, count 0 2006.162.07:43:12.90#ibcon#wrote, iclass 21, count 0 2006.162.07:43:12.90#ibcon#about to read 3, iclass 21, count 0 2006.162.07:43:12.92#ibcon#read 3, iclass 21, count 0 2006.162.07:43:12.92#ibcon#about to read 4, iclass 21, count 0 2006.162.07:43:12.92#ibcon#read 4, iclass 21, count 0 2006.162.07:43:12.92#ibcon#about to read 5, iclass 21, count 0 2006.162.07:43:12.92#ibcon#read 5, iclass 21, count 0 2006.162.07:43:12.92#ibcon#about to read 6, iclass 21, count 0 2006.162.07:43:12.92#ibcon#read 6, iclass 21, count 0 2006.162.07:43:12.92#ibcon#end of sib2, iclass 21, count 0 2006.162.07:43:12.92#ibcon#*mode == 0, iclass 21, count 0 2006.162.07:43:12.92#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.162.07:43:12.92#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.07:43:12.92#ibcon#*before write, iclass 21, count 0 2006.162.07:43:12.92#ibcon#enter sib2, iclass 21, count 0 2006.162.07:43:12.92#ibcon#flushed, iclass 21, count 0 2006.162.07:43:12.92#ibcon#about to write, iclass 21, count 0 2006.162.07:43:12.92#ibcon#wrote, iclass 21, count 0 2006.162.07:43:12.92#ibcon#about to read 3, iclass 21, count 0 2006.162.07:43:12.96#ibcon#read 3, iclass 21, count 0 2006.162.07:43:12.96#ibcon#about to read 4, iclass 21, count 0 2006.162.07:43:12.96#ibcon#read 4, iclass 21, count 0 2006.162.07:43:12.96#ibcon#about to read 5, iclass 21, count 0 2006.162.07:43:12.96#ibcon#read 5, iclass 21, count 0 2006.162.07:43:12.96#ibcon#about to read 6, iclass 21, count 0 2006.162.07:43:12.96#ibcon#read 6, iclass 21, count 0 2006.162.07:43:12.96#ibcon#end of sib2, iclass 21, count 0 2006.162.07:43:12.96#ibcon#*after write, iclass 21, count 0 2006.162.07:43:12.96#ibcon#*before return 0, iclass 21, count 0 2006.162.07:43:12.96#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:43:12.96#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:43:12.96#ibcon#about to clear, iclass 21 cls_cnt 0 2006.162.07:43:12.96#ibcon#cleared, iclass 21 cls_cnt 0 2006.162.07:43:12.96$vc4f8/vb=4,4 2006.162.07:43:12.96#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.162.07:43:12.96#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.162.07:43:12.96#ibcon#ireg 11 cls_cnt 2 2006.162.07:43:12.96#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.162.07:43:13.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.162.07:43:13.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.162.07:43:13.02#ibcon#enter wrdev, iclass 23, count 2 2006.162.07:43:13.02#ibcon#first serial, iclass 23, count 2 2006.162.07:43:13.02#ibcon#enter sib2, iclass 23, count 2 2006.162.07:43:13.02#ibcon#flushed, iclass 23, count 2 2006.162.07:43:13.02#ibcon#about to write, iclass 23, count 2 2006.162.07:43:13.02#ibcon#wrote, iclass 23, count 2 2006.162.07:43:13.02#ibcon#about to read 3, iclass 23, count 2 2006.162.07:43:13.04#ibcon#read 3, iclass 23, count 2 2006.162.07:43:13.04#ibcon#about to read 4, iclass 23, count 2 2006.162.07:43:13.04#ibcon#read 4, iclass 23, count 2 2006.162.07:43:13.04#ibcon#about to read 5, iclass 23, count 2 2006.162.07:43:13.04#ibcon#read 5, iclass 23, count 2 2006.162.07:43:13.04#ibcon#about to read 6, iclass 23, count 2 2006.162.07:43:13.04#ibcon#read 6, iclass 23, count 2 2006.162.07:43:13.04#ibcon#end of sib2, iclass 23, count 2 2006.162.07:43:13.04#ibcon#*mode == 0, iclass 23, count 2 2006.162.07:43:13.04#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.162.07:43:13.04#ibcon#[27=AT04-04\r\n] 2006.162.07:43:13.04#ibcon#*before write, iclass 23, count 2 2006.162.07:43:13.04#ibcon#enter sib2, iclass 23, count 2 2006.162.07:43:13.04#ibcon#flushed, iclass 23, count 2 2006.162.07:43:13.04#ibcon#about to write, iclass 23, count 2 2006.162.07:43:13.04#ibcon#wrote, iclass 23, count 2 2006.162.07:43:13.04#ibcon#about to read 3, iclass 23, count 2 2006.162.07:43:13.07#ibcon#read 3, iclass 23, count 2 2006.162.07:43:13.07#ibcon#about to read 4, iclass 23, count 2 2006.162.07:43:13.07#ibcon#read 4, iclass 23, count 2 2006.162.07:43:13.07#ibcon#about to read 5, iclass 23, count 2 2006.162.07:43:13.07#ibcon#read 5, iclass 23, count 2 2006.162.07:43:13.07#ibcon#about to read 6, iclass 23, count 2 2006.162.07:43:13.07#ibcon#read 6, iclass 23, count 2 2006.162.07:43:13.07#ibcon#end of sib2, iclass 23, count 2 2006.162.07:43:13.07#ibcon#*after write, iclass 23, count 2 2006.162.07:43:13.07#ibcon#*before return 0, iclass 23, count 2 2006.162.07:43:13.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.162.07:43:13.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.162.07:43:13.07#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.162.07:43:13.07#ibcon#ireg 7 cls_cnt 0 2006.162.07:43:13.07#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.162.07:43:13.19#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.162.07:43:13.19#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.162.07:43:13.19#ibcon#enter wrdev, iclass 23, count 0 2006.162.07:43:13.19#ibcon#first serial, iclass 23, count 0 2006.162.07:43:13.19#ibcon#enter sib2, iclass 23, count 0 2006.162.07:43:13.19#ibcon#flushed, iclass 23, count 0 2006.162.07:43:13.19#ibcon#about to write, iclass 23, count 0 2006.162.07:43:13.19#ibcon#wrote, iclass 23, count 0 2006.162.07:43:13.19#ibcon#about to read 3, iclass 23, count 0 2006.162.07:43:13.21#ibcon#read 3, iclass 23, count 0 2006.162.07:43:13.21#ibcon#about to read 4, iclass 23, count 0 2006.162.07:43:13.21#ibcon#read 4, iclass 23, count 0 2006.162.07:43:13.21#ibcon#about to read 5, iclass 23, count 0 2006.162.07:43:13.21#ibcon#read 5, iclass 23, count 0 2006.162.07:43:13.21#ibcon#about to read 6, iclass 23, count 0 2006.162.07:43:13.21#ibcon#read 6, iclass 23, count 0 2006.162.07:43:13.21#ibcon#end of sib2, iclass 23, count 0 2006.162.07:43:13.21#ibcon#*mode == 0, iclass 23, count 0 2006.162.07:43:13.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.162.07:43:13.21#ibcon#[27=USB\r\n] 2006.162.07:43:13.21#ibcon#*before write, iclass 23, count 0 2006.162.07:43:13.21#ibcon#enter sib2, iclass 23, count 0 2006.162.07:43:13.21#ibcon#flushed, iclass 23, count 0 2006.162.07:43:13.21#ibcon#about to write, iclass 23, count 0 2006.162.07:43:13.21#ibcon#wrote, iclass 23, count 0 2006.162.07:43:13.21#ibcon#about to read 3, iclass 23, count 0 2006.162.07:43:13.24#ibcon#read 3, iclass 23, count 0 2006.162.07:43:13.24#ibcon#about to read 4, iclass 23, count 0 2006.162.07:43:13.24#ibcon#read 4, iclass 23, count 0 2006.162.07:43:13.24#ibcon#about to read 5, iclass 23, count 0 2006.162.07:43:13.24#ibcon#read 5, iclass 23, count 0 2006.162.07:43:13.24#ibcon#about to read 6, iclass 23, count 0 2006.162.07:43:13.24#ibcon#read 6, iclass 23, count 0 2006.162.07:43:13.24#ibcon#end of sib2, iclass 23, count 0 2006.162.07:43:13.24#ibcon#*after write, iclass 23, count 0 2006.162.07:43:13.24#ibcon#*before return 0, iclass 23, count 0 2006.162.07:43:13.24#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.162.07:43:13.24#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.162.07:43:13.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.162.07:43:13.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.162.07:43:13.24$vc4f8/vblo=5,744.99 2006.162.07:43:13.24#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.162.07:43:13.24#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.162.07:43:13.24#ibcon#ireg 17 cls_cnt 0 2006.162.07:43:13.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:43:13.24#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:43:13.24#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:43:13.24#ibcon#enter wrdev, iclass 25, count 0 2006.162.07:43:13.24#ibcon#first serial, iclass 25, count 0 2006.162.07:43:13.24#ibcon#enter sib2, iclass 25, count 0 2006.162.07:43:13.24#ibcon#flushed, iclass 25, count 0 2006.162.07:43:13.24#ibcon#about to write, iclass 25, count 0 2006.162.07:43:13.24#ibcon#wrote, iclass 25, count 0 2006.162.07:43:13.24#ibcon#about to read 3, iclass 25, count 0 2006.162.07:43:13.26#ibcon#read 3, iclass 25, count 0 2006.162.07:43:13.26#ibcon#about to read 4, iclass 25, count 0 2006.162.07:43:13.26#ibcon#read 4, iclass 25, count 0 2006.162.07:43:13.26#ibcon#about to read 5, iclass 25, count 0 2006.162.07:43:13.26#ibcon#read 5, iclass 25, count 0 2006.162.07:43:13.26#ibcon#about to read 6, iclass 25, count 0 2006.162.07:43:13.26#ibcon#read 6, iclass 25, count 0 2006.162.07:43:13.26#ibcon#end of sib2, iclass 25, count 0 2006.162.07:43:13.26#ibcon#*mode == 0, iclass 25, count 0 2006.162.07:43:13.26#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.162.07:43:13.26#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.07:43:13.26#ibcon#*before write, iclass 25, count 0 2006.162.07:43:13.26#ibcon#enter sib2, iclass 25, count 0 2006.162.07:43:13.26#ibcon#flushed, iclass 25, count 0 2006.162.07:43:13.26#ibcon#about to write, iclass 25, count 0 2006.162.07:43:13.26#ibcon#wrote, iclass 25, count 0 2006.162.07:43:13.26#ibcon#about to read 3, iclass 25, count 0 2006.162.07:43:13.30#ibcon#read 3, iclass 25, count 0 2006.162.07:43:13.30#ibcon#about to read 4, iclass 25, count 0 2006.162.07:43:13.30#ibcon#read 4, iclass 25, count 0 2006.162.07:43:13.30#ibcon#about to read 5, iclass 25, count 0 2006.162.07:43:13.30#ibcon#read 5, iclass 25, count 0 2006.162.07:43:13.30#ibcon#about to read 6, iclass 25, count 0 2006.162.07:43:13.30#ibcon#read 6, iclass 25, count 0 2006.162.07:43:13.30#ibcon#end of sib2, iclass 25, count 0 2006.162.07:43:13.30#ibcon#*after write, iclass 25, count 0 2006.162.07:43:13.30#ibcon#*before return 0, iclass 25, count 0 2006.162.07:43:13.30#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:43:13.30#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:43:13.30#ibcon#about to clear, iclass 25 cls_cnt 0 2006.162.07:43:13.30#ibcon#cleared, iclass 25 cls_cnt 0 2006.162.07:43:13.30$vc4f8/vb=5,4 2006.162.07:43:13.30#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.162.07:43:13.30#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.162.07:43:13.30#ibcon#ireg 11 cls_cnt 2 2006.162.07:43:13.30#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.162.07:43:13.36#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.162.07:43:13.36#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.162.07:43:13.36#ibcon#enter wrdev, iclass 27, count 2 2006.162.07:43:13.36#ibcon#first serial, iclass 27, count 2 2006.162.07:43:13.36#ibcon#enter sib2, iclass 27, count 2 2006.162.07:43:13.36#ibcon#flushed, iclass 27, count 2 2006.162.07:43:13.36#ibcon#about to write, iclass 27, count 2 2006.162.07:43:13.36#ibcon#wrote, iclass 27, count 2 2006.162.07:43:13.36#ibcon#about to read 3, iclass 27, count 2 2006.162.07:43:13.38#ibcon#read 3, iclass 27, count 2 2006.162.07:43:13.38#ibcon#about to read 4, iclass 27, count 2 2006.162.07:43:13.38#ibcon#read 4, iclass 27, count 2 2006.162.07:43:13.38#ibcon#about to read 5, iclass 27, count 2 2006.162.07:43:13.38#ibcon#read 5, iclass 27, count 2 2006.162.07:43:13.38#ibcon#about to read 6, iclass 27, count 2 2006.162.07:43:13.38#ibcon#read 6, iclass 27, count 2 2006.162.07:43:13.38#ibcon#end of sib2, iclass 27, count 2 2006.162.07:43:13.38#ibcon#*mode == 0, iclass 27, count 2 2006.162.07:43:13.38#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.162.07:43:13.38#ibcon#[27=AT05-04\r\n] 2006.162.07:43:13.38#ibcon#*before write, iclass 27, count 2 2006.162.07:43:13.38#ibcon#enter sib2, iclass 27, count 2 2006.162.07:43:13.38#ibcon#flushed, iclass 27, count 2 2006.162.07:43:13.38#ibcon#about to write, iclass 27, count 2 2006.162.07:43:13.38#ibcon#wrote, iclass 27, count 2 2006.162.07:43:13.38#ibcon#about to read 3, iclass 27, count 2 2006.162.07:43:13.41#ibcon#read 3, iclass 27, count 2 2006.162.07:43:13.41#ibcon#about to read 4, iclass 27, count 2 2006.162.07:43:13.41#ibcon#read 4, iclass 27, count 2 2006.162.07:43:13.41#ibcon#about to read 5, iclass 27, count 2 2006.162.07:43:13.41#ibcon#read 5, iclass 27, count 2 2006.162.07:43:13.41#ibcon#about to read 6, iclass 27, count 2 2006.162.07:43:13.41#ibcon#read 6, iclass 27, count 2 2006.162.07:43:13.41#ibcon#end of sib2, iclass 27, count 2 2006.162.07:43:13.41#ibcon#*after write, iclass 27, count 2 2006.162.07:43:13.41#ibcon#*before return 0, iclass 27, count 2 2006.162.07:43:13.41#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.162.07:43:13.41#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.162.07:43:13.41#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.162.07:43:13.41#ibcon#ireg 7 cls_cnt 0 2006.162.07:43:13.41#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.162.07:43:13.53#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.162.07:43:13.53#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.162.07:43:13.53#ibcon#enter wrdev, iclass 27, count 0 2006.162.07:43:13.53#ibcon#first serial, iclass 27, count 0 2006.162.07:43:13.53#ibcon#enter sib2, iclass 27, count 0 2006.162.07:43:13.53#ibcon#flushed, iclass 27, count 0 2006.162.07:43:13.53#ibcon#about to write, iclass 27, count 0 2006.162.07:43:13.53#ibcon#wrote, iclass 27, count 0 2006.162.07:43:13.53#ibcon#about to read 3, iclass 27, count 0 2006.162.07:43:13.55#ibcon#read 3, iclass 27, count 0 2006.162.07:43:13.55#ibcon#about to read 4, iclass 27, count 0 2006.162.07:43:13.55#ibcon#read 4, iclass 27, count 0 2006.162.07:43:13.55#ibcon#about to read 5, iclass 27, count 0 2006.162.07:43:13.55#ibcon#read 5, iclass 27, count 0 2006.162.07:43:13.55#ibcon#about to read 6, iclass 27, count 0 2006.162.07:43:13.55#ibcon#read 6, iclass 27, count 0 2006.162.07:43:13.55#ibcon#end of sib2, iclass 27, count 0 2006.162.07:43:13.55#ibcon#*mode == 0, iclass 27, count 0 2006.162.07:43:13.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.162.07:43:13.55#ibcon#[27=USB\r\n] 2006.162.07:43:13.55#ibcon#*before write, iclass 27, count 0 2006.162.07:43:13.55#ibcon#enter sib2, iclass 27, count 0 2006.162.07:43:13.55#ibcon#flushed, iclass 27, count 0 2006.162.07:43:13.55#ibcon#about to write, iclass 27, count 0 2006.162.07:43:13.55#ibcon#wrote, iclass 27, count 0 2006.162.07:43:13.55#ibcon#about to read 3, iclass 27, count 0 2006.162.07:43:13.58#ibcon#read 3, iclass 27, count 0 2006.162.07:43:13.58#ibcon#about to read 4, iclass 27, count 0 2006.162.07:43:13.58#ibcon#read 4, iclass 27, count 0 2006.162.07:43:13.58#ibcon#about to read 5, iclass 27, count 0 2006.162.07:43:13.58#ibcon#read 5, iclass 27, count 0 2006.162.07:43:13.58#ibcon#about to read 6, iclass 27, count 0 2006.162.07:43:13.58#ibcon#read 6, iclass 27, count 0 2006.162.07:43:13.58#ibcon#end of sib2, iclass 27, count 0 2006.162.07:43:13.58#ibcon#*after write, iclass 27, count 0 2006.162.07:43:13.58#ibcon#*before return 0, iclass 27, count 0 2006.162.07:43:13.58#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.162.07:43:13.58#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.162.07:43:13.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.162.07:43:13.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.162.07:43:13.58$vc4f8/vblo=6,752.99 2006.162.07:43:13.58#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.162.07:43:13.58#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.162.07:43:13.58#ibcon#ireg 17 cls_cnt 0 2006.162.07:43:13.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.162.07:43:13.58#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.162.07:43:13.58#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.162.07:43:13.58#ibcon#enter wrdev, iclass 29, count 0 2006.162.07:43:13.58#ibcon#first serial, iclass 29, count 0 2006.162.07:43:13.58#ibcon#enter sib2, iclass 29, count 0 2006.162.07:43:13.58#ibcon#flushed, iclass 29, count 0 2006.162.07:43:13.58#ibcon#about to write, iclass 29, count 0 2006.162.07:43:13.58#ibcon#wrote, iclass 29, count 0 2006.162.07:43:13.58#ibcon#about to read 3, iclass 29, count 0 2006.162.07:43:13.60#ibcon#read 3, iclass 29, count 0 2006.162.07:43:13.60#ibcon#about to read 4, iclass 29, count 0 2006.162.07:43:13.60#ibcon#read 4, iclass 29, count 0 2006.162.07:43:13.60#ibcon#about to read 5, iclass 29, count 0 2006.162.07:43:13.60#ibcon#read 5, iclass 29, count 0 2006.162.07:43:13.60#ibcon#about to read 6, iclass 29, count 0 2006.162.07:43:13.60#ibcon#read 6, iclass 29, count 0 2006.162.07:43:13.60#ibcon#end of sib2, iclass 29, count 0 2006.162.07:43:13.60#ibcon#*mode == 0, iclass 29, count 0 2006.162.07:43:13.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.162.07:43:13.60#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.07:43:13.60#ibcon#*before write, iclass 29, count 0 2006.162.07:43:13.60#ibcon#enter sib2, iclass 29, count 0 2006.162.07:43:13.60#ibcon#flushed, iclass 29, count 0 2006.162.07:43:13.60#ibcon#about to write, iclass 29, count 0 2006.162.07:43:13.60#ibcon#wrote, iclass 29, count 0 2006.162.07:43:13.60#ibcon#about to read 3, iclass 29, count 0 2006.162.07:43:13.64#ibcon#read 3, iclass 29, count 0 2006.162.07:43:13.64#ibcon#about to read 4, iclass 29, count 0 2006.162.07:43:13.64#ibcon#read 4, iclass 29, count 0 2006.162.07:43:13.64#ibcon#about to read 5, iclass 29, count 0 2006.162.07:43:13.64#ibcon#read 5, iclass 29, count 0 2006.162.07:43:13.64#ibcon#about to read 6, iclass 29, count 0 2006.162.07:43:13.64#ibcon#read 6, iclass 29, count 0 2006.162.07:43:13.64#ibcon#end of sib2, iclass 29, count 0 2006.162.07:43:13.64#ibcon#*after write, iclass 29, count 0 2006.162.07:43:13.64#ibcon#*before return 0, iclass 29, count 0 2006.162.07:43:13.64#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.162.07:43:13.64#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.162.07:43:13.64#ibcon#about to clear, iclass 29 cls_cnt 0 2006.162.07:43:13.64#ibcon#cleared, iclass 29 cls_cnt 0 2006.162.07:43:13.64$vc4f8/vb=6,4 2006.162.07:43:13.64#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.162.07:43:13.64#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.162.07:43:13.64#ibcon#ireg 11 cls_cnt 2 2006.162.07:43:13.64#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.162.07:43:13.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.162.07:43:13.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.162.07:43:13.70#ibcon#enter wrdev, iclass 31, count 2 2006.162.07:43:13.70#ibcon#first serial, iclass 31, count 2 2006.162.07:43:13.70#ibcon#enter sib2, iclass 31, count 2 2006.162.07:43:13.70#ibcon#flushed, iclass 31, count 2 2006.162.07:43:13.70#ibcon#about to write, iclass 31, count 2 2006.162.07:43:13.70#ibcon#wrote, iclass 31, count 2 2006.162.07:43:13.70#ibcon#about to read 3, iclass 31, count 2 2006.162.07:43:13.72#ibcon#read 3, iclass 31, count 2 2006.162.07:43:13.72#ibcon#about to read 4, iclass 31, count 2 2006.162.07:43:13.72#ibcon#read 4, iclass 31, count 2 2006.162.07:43:13.72#ibcon#about to read 5, iclass 31, count 2 2006.162.07:43:13.72#ibcon#read 5, iclass 31, count 2 2006.162.07:43:13.72#ibcon#about to read 6, iclass 31, count 2 2006.162.07:43:13.72#ibcon#read 6, iclass 31, count 2 2006.162.07:43:13.72#ibcon#end of sib2, iclass 31, count 2 2006.162.07:43:13.72#ibcon#*mode == 0, iclass 31, count 2 2006.162.07:43:13.72#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.162.07:43:13.72#ibcon#[27=AT06-04\r\n] 2006.162.07:43:13.72#ibcon#*before write, iclass 31, count 2 2006.162.07:43:13.72#ibcon#enter sib2, iclass 31, count 2 2006.162.07:43:13.72#ibcon#flushed, iclass 31, count 2 2006.162.07:43:13.72#ibcon#about to write, iclass 31, count 2 2006.162.07:43:13.72#ibcon#wrote, iclass 31, count 2 2006.162.07:43:13.72#ibcon#about to read 3, iclass 31, count 2 2006.162.07:43:13.75#ibcon#read 3, iclass 31, count 2 2006.162.07:43:13.75#ibcon#about to read 4, iclass 31, count 2 2006.162.07:43:13.75#ibcon#read 4, iclass 31, count 2 2006.162.07:43:13.75#ibcon#about to read 5, iclass 31, count 2 2006.162.07:43:13.75#ibcon#read 5, iclass 31, count 2 2006.162.07:43:13.75#ibcon#about to read 6, iclass 31, count 2 2006.162.07:43:13.75#ibcon#read 6, iclass 31, count 2 2006.162.07:43:13.75#ibcon#end of sib2, iclass 31, count 2 2006.162.07:43:13.75#ibcon#*after write, iclass 31, count 2 2006.162.07:43:13.75#ibcon#*before return 0, iclass 31, count 2 2006.162.07:43:13.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.162.07:43:13.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.162.07:43:13.75#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.162.07:43:13.75#ibcon#ireg 7 cls_cnt 0 2006.162.07:43:13.75#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.162.07:43:13.87#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.162.07:43:13.87#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.162.07:43:13.87#ibcon#enter wrdev, iclass 31, count 0 2006.162.07:43:13.87#ibcon#first serial, iclass 31, count 0 2006.162.07:43:13.87#ibcon#enter sib2, iclass 31, count 0 2006.162.07:43:13.87#ibcon#flushed, iclass 31, count 0 2006.162.07:43:13.87#ibcon#about to write, iclass 31, count 0 2006.162.07:43:13.87#ibcon#wrote, iclass 31, count 0 2006.162.07:43:13.87#ibcon#about to read 3, iclass 31, count 0 2006.162.07:43:13.89#ibcon#read 3, iclass 31, count 0 2006.162.07:43:13.89#ibcon#about to read 4, iclass 31, count 0 2006.162.07:43:13.89#ibcon#read 4, iclass 31, count 0 2006.162.07:43:13.89#ibcon#about to read 5, iclass 31, count 0 2006.162.07:43:13.89#ibcon#read 5, iclass 31, count 0 2006.162.07:43:13.89#ibcon#about to read 6, iclass 31, count 0 2006.162.07:43:13.89#ibcon#read 6, iclass 31, count 0 2006.162.07:43:13.89#ibcon#end of sib2, iclass 31, count 0 2006.162.07:43:13.89#ibcon#*mode == 0, iclass 31, count 0 2006.162.07:43:13.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.162.07:43:13.89#ibcon#[27=USB\r\n] 2006.162.07:43:13.89#ibcon#*before write, iclass 31, count 0 2006.162.07:43:13.89#ibcon#enter sib2, iclass 31, count 0 2006.162.07:43:13.89#ibcon#flushed, iclass 31, count 0 2006.162.07:43:13.89#ibcon#about to write, iclass 31, count 0 2006.162.07:43:13.89#ibcon#wrote, iclass 31, count 0 2006.162.07:43:13.89#ibcon#about to read 3, iclass 31, count 0 2006.162.07:43:13.92#ibcon#read 3, iclass 31, count 0 2006.162.07:43:13.92#ibcon#about to read 4, iclass 31, count 0 2006.162.07:43:13.92#ibcon#read 4, iclass 31, count 0 2006.162.07:43:13.92#ibcon#about to read 5, iclass 31, count 0 2006.162.07:43:13.92#ibcon#read 5, iclass 31, count 0 2006.162.07:43:13.92#ibcon#about to read 6, iclass 31, count 0 2006.162.07:43:13.92#ibcon#read 6, iclass 31, count 0 2006.162.07:43:13.92#ibcon#end of sib2, iclass 31, count 0 2006.162.07:43:13.92#ibcon#*after write, iclass 31, count 0 2006.162.07:43:13.92#ibcon#*before return 0, iclass 31, count 0 2006.162.07:43:13.92#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.162.07:43:13.92#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.162.07:43:13.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.162.07:43:13.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.162.07:43:13.92$vc4f8/vabw=wide 2006.162.07:43:13.92#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.162.07:43:13.92#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.162.07:43:13.92#ibcon#ireg 8 cls_cnt 0 2006.162.07:43:13.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.162.07:43:13.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.162.07:43:13.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.162.07:43:13.92#ibcon#enter wrdev, iclass 33, count 0 2006.162.07:43:13.92#ibcon#first serial, iclass 33, count 0 2006.162.07:43:13.92#ibcon#enter sib2, iclass 33, count 0 2006.162.07:43:13.92#ibcon#flushed, iclass 33, count 0 2006.162.07:43:13.92#ibcon#about to write, iclass 33, count 0 2006.162.07:43:13.92#ibcon#wrote, iclass 33, count 0 2006.162.07:43:13.92#ibcon#about to read 3, iclass 33, count 0 2006.162.07:43:13.94#ibcon#read 3, iclass 33, count 0 2006.162.07:43:13.94#ibcon#about to read 4, iclass 33, count 0 2006.162.07:43:13.94#ibcon#read 4, iclass 33, count 0 2006.162.07:43:13.94#ibcon#about to read 5, iclass 33, count 0 2006.162.07:43:13.94#ibcon#read 5, iclass 33, count 0 2006.162.07:43:13.94#ibcon#about to read 6, iclass 33, count 0 2006.162.07:43:13.94#ibcon#read 6, iclass 33, count 0 2006.162.07:43:13.94#ibcon#end of sib2, iclass 33, count 0 2006.162.07:43:13.94#ibcon#*mode == 0, iclass 33, count 0 2006.162.07:43:13.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.162.07:43:13.94#ibcon#[25=BW32\r\n] 2006.162.07:43:13.94#ibcon#*before write, iclass 33, count 0 2006.162.07:43:13.94#ibcon#enter sib2, iclass 33, count 0 2006.162.07:43:13.94#ibcon#flushed, iclass 33, count 0 2006.162.07:43:13.94#ibcon#about to write, iclass 33, count 0 2006.162.07:43:13.94#ibcon#wrote, iclass 33, count 0 2006.162.07:43:13.94#ibcon#about to read 3, iclass 33, count 0 2006.162.07:43:13.97#ibcon#read 3, iclass 33, count 0 2006.162.07:43:13.97#ibcon#about to read 4, iclass 33, count 0 2006.162.07:43:13.97#ibcon#read 4, iclass 33, count 0 2006.162.07:43:13.97#ibcon#about to read 5, iclass 33, count 0 2006.162.07:43:13.97#ibcon#read 5, iclass 33, count 0 2006.162.07:43:13.97#ibcon#about to read 6, iclass 33, count 0 2006.162.07:43:13.97#ibcon#read 6, iclass 33, count 0 2006.162.07:43:13.97#ibcon#end of sib2, iclass 33, count 0 2006.162.07:43:13.97#ibcon#*after write, iclass 33, count 0 2006.162.07:43:13.97#ibcon#*before return 0, iclass 33, count 0 2006.162.07:43:13.97#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.162.07:43:13.97#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.162.07:43:13.97#ibcon#about to clear, iclass 33 cls_cnt 0 2006.162.07:43:13.97#ibcon#cleared, iclass 33 cls_cnt 0 2006.162.07:43:13.97$vc4f8/vbbw=wide 2006.162.07:43:13.97#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.162.07:43:13.97#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.162.07:43:13.97#ibcon#ireg 8 cls_cnt 0 2006.162.07:43:13.97#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.162.07:43:14.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.162.07:43:14.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.162.07:43:14.04#ibcon#enter wrdev, iclass 35, count 0 2006.162.07:43:14.04#ibcon#first serial, iclass 35, count 0 2006.162.07:43:14.04#ibcon#enter sib2, iclass 35, count 0 2006.162.07:43:14.04#ibcon#flushed, iclass 35, count 0 2006.162.07:43:14.04#ibcon#about to write, iclass 35, count 0 2006.162.07:43:14.04#ibcon#wrote, iclass 35, count 0 2006.162.07:43:14.04#ibcon#about to read 3, iclass 35, count 0 2006.162.07:43:14.06#ibcon#read 3, iclass 35, count 0 2006.162.07:43:14.06#ibcon#about to read 4, iclass 35, count 0 2006.162.07:43:14.06#ibcon#read 4, iclass 35, count 0 2006.162.07:43:14.06#ibcon#about to read 5, iclass 35, count 0 2006.162.07:43:14.06#ibcon#read 5, iclass 35, count 0 2006.162.07:43:14.06#ibcon#about to read 6, iclass 35, count 0 2006.162.07:43:14.06#ibcon#read 6, iclass 35, count 0 2006.162.07:43:14.06#ibcon#end of sib2, iclass 35, count 0 2006.162.07:43:14.06#ibcon#*mode == 0, iclass 35, count 0 2006.162.07:43:14.06#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.162.07:43:14.06#ibcon#[27=BW32\r\n] 2006.162.07:43:14.06#ibcon#*before write, iclass 35, count 0 2006.162.07:43:14.06#ibcon#enter sib2, iclass 35, count 0 2006.162.07:43:14.06#ibcon#flushed, iclass 35, count 0 2006.162.07:43:14.06#ibcon#about to write, iclass 35, count 0 2006.162.07:43:14.06#ibcon#wrote, iclass 35, count 0 2006.162.07:43:14.06#ibcon#about to read 3, iclass 35, count 0 2006.162.07:43:14.09#ibcon#read 3, iclass 35, count 0 2006.162.07:43:14.09#ibcon#about to read 4, iclass 35, count 0 2006.162.07:43:14.09#ibcon#read 4, iclass 35, count 0 2006.162.07:43:14.09#ibcon#about to read 5, iclass 35, count 0 2006.162.07:43:14.09#ibcon#read 5, iclass 35, count 0 2006.162.07:43:14.09#ibcon#about to read 6, iclass 35, count 0 2006.162.07:43:14.09#ibcon#read 6, iclass 35, count 0 2006.162.07:43:14.09#ibcon#end of sib2, iclass 35, count 0 2006.162.07:43:14.09#ibcon#*after write, iclass 35, count 0 2006.162.07:43:14.09#ibcon#*before return 0, iclass 35, count 0 2006.162.07:43:14.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.162.07:43:14.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.162.07:43:14.09#ibcon#about to clear, iclass 35 cls_cnt 0 2006.162.07:43:14.09#ibcon#cleared, iclass 35 cls_cnt 0 2006.162.07:43:14.09$4f8m12a/ifd4f 2006.162.07:43:14.09$ifd4f/lo= 2006.162.07:43:14.09$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.07:43:14.09$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.07:43:14.09$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.07:43:14.09$ifd4f/patch= 2006.162.07:43:14.09$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.07:43:14.09$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.07:43:14.09$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.07:43:14.09$4f8m12a/"form=m,16.000,1:2 2006.162.07:43:14.09$4f8m12a/"tpicd 2006.162.07:43:14.09$4f8m12a/echo=off 2006.162.07:43:14.09$4f8m12a/xlog=off 2006.162.07:43:14.09:!2006.162.07:43:40 2006.162.07:43:23.14#trakl#Source acquired 2006.162.07:43:24.14#flagr#flagr/antenna,acquired 2006.162.07:43:40.00:preob 2006.162.07:43:40.14/onsource/TRACKING 2006.162.07:43:40.14:!2006.162.07:43:50 2006.162.07:43:50.00:data_valid=on 2006.162.07:43:50.00:midob 2006.162.07:43:51.14/onsource/TRACKING 2006.162.07:43:51.14/wx/17.90,1007.2,100 2006.162.07:43:51.32/cable/+6.5365E-03 2006.162.07:43:52.41/va/01,08,usb,yes,40,43 2006.162.07:43:52.41/va/02,07,usb,yes,41,43 2006.162.07:43:52.41/va/03,06,usb,yes,43,43 2006.162.07:43:52.41/va/04,07,usb,yes,42,45 2006.162.07:43:52.41/va/05,07,usb,yes,45,47 2006.162.07:43:52.41/va/06,06,usb,yes,44,44 2006.162.07:43:52.41/va/07,06,usb,yes,44,44 2006.162.07:43:52.41/va/08,07,usb,yes,42,42 2006.162.07:43:52.64/valo/01,532.99,yes,locked 2006.162.07:43:52.64/valo/02,572.99,yes,locked 2006.162.07:43:52.64/valo/03,672.99,yes,locked 2006.162.07:43:52.64/valo/04,832.99,yes,locked 2006.162.07:43:52.64/valo/05,652.99,yes,locked 2006.162.07:43:52.64/valo/06,772.99,yes,locked 2006.162.07:43:52.64/valo/07,832.99,yes,locked 2006.162.07:43:52.64/valo/08,852.99,yes,locked 2006.162.07:43:53.73/vb/01,04,usb,yes,29,28 2006.162.07:43:53.73/vb/02,04,usb,yes,31,33 2006.162.07:43:53.73/vb/03,04,usb,yes,28,31 2006.162.07:43:53.73/vb/04,04,usb,yes,28,29 2006.162.07:43:53.73/vb/05,04,usb,yes,27,31 2006.162.07:43:53.73/vb/06,04,usb,yes,28,31 2006.162.07:43:53.73/vb/07,04,usb,yes,30,30 2006.162.07:43:53.73/vb/08,04,usb,yes,28,31 2006.162.07:43:53.96/vblo/01,632.99,yes,locked 2006.162.07:43:53.96/vblo/02,640.99,yes,locked 2006.162.07:43:53.96/vblo/03,656.99,yes,locked 2006.162.07:43:53.96/vblo/04,712.99,yes,locked 2006.162.07:43:53.96/vblo/05,744.99,yes,locked 2006.162.07:43:53.96/vblo/06,752.99,yes,locked 2006.162.07:43:53.96/vblo/07,734.99,yes,locked 2006.162.07:43:53.96/vblo/08,744.99,yes,locked 2006.162.07:43:54.11/vabw/8 2006.162.07:43:54.26/vbbw/8 2006.162.07:43:54.40/xfe/off,on,14.5 2006.162.07:43:54.78/ifatt/23,28,28,28 2006.162.07:43:55.08/fmout-gps/S +4.48E-07 2006.162.07:43:55.12:!2006.162.07:44:50 2006.162.07:44:50.00:data_valid=off 2006.162.07:44:50.00:postob 2006.162.07:44:50.21/cable/+6.5362E-03 2006.162.07:44:50.21/wx/17.89,1007.2,100 2006.162.07:44:51.08/fmout-gps/S +4.48E-07 2006.162.07:44:51.08:scan_name=162-0745,k06162,60 2006.162.07:44:51.09:source=0749+540,075301.38,535300.0,2000.0,ccw 2006.162.07:44:51.14#flagr#flagr/antenna,new-source 2006.162.07:44:52.14:checkk5 2006.162.07:44:52.58/chk_autoobs//k5ts1/ autoobs is running! 2006.162.07:44:53.01/chk_autoobs//k5ts2/ autoobs is running! 2006.162.07:44:53.40/chk_autoobs//k5ts3/ autoobs is running! 2006.162.07:44:54.06/chk_autoobs//k5ts4/ autoobs is running! 2006.162.07:44:54.48/chk_obsdata//k5ts1/T1620743??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:44:54.92/chk_obsdata//k5ts2/T1620743??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:44:55.36/chk_obsdata//k5ts3/T1620743??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:44:55.82/chk_obsdata//k5ts4/T1620743??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:44:56.56/k5log//k5ts1_log_newline 2006.162.07:44:57.34/k5log//k5ts2_log_newline 2006.162.07:44:58.10/k5log//k5ts3_log_newline 2006.162.07:44:58.98/k5log//k5ts4_log_newline 2006.162.07:44:59.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.07:44:59.00:4f8m12a=1 2006.162.07:44:59.00$4f8m12a/echo=on 2006.162.07:44:59.00$4f8m12a/pcalon 2006.162.07:44:59.00$pcalon/"no phase cal control is implemented here 2006.162.07:44:59.00$4f8m12a/"tpicd=stop 2006.162.07:44:59.00$4f8m12a/vc4f8 2006.162.07:44:59.00$vc4f8/valo=1,532.99 2006.162.07:44:59.01#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.162.07:44:59.01#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.162.07:44:59.01#ibcon#ireg 17 cls_cnt 0 2006.162.07:44:59.01#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.162.07:44:59.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.162.07:44:59.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.162.07:44:59.01#ibcon#enter wrdev, iclass 4, count 0 2006.162.07:44:59.01#ibcon#first serial, iclass 4, count 0 2006.162.07:44:59.01#ibcon#enter sib2, iclass 4, count 0 2006.162.07:44:59.01#ibcon#flushed, iclass 4, count 0 2006.162.07:44:59.01#ibcon#about to write, iclass 4, count 0 2006.162.07:44:59.01#ibcon#wrote, iclass 4, count 0 2006.162.07:44:59.01#ibcon#about to read 3, iclass 4, count 0 2006.162.07:44:59.05#ibcon#read 3, iclass 4, count 0 2006.162.07:44:59.05#ibcon#about to read 4, iclass 4, count 0 2006.162.07:44:59.05#ibcon#read 4, iclass 4, count 0 2006.162.07:44:59.05#ibcon#about to read 5, iclass 4, count 0 2006.162.07:44:59.05#ibcon#read 5, iclass 4, count 0 2006.162.07:44:59.05#ibcon#about to read 6, iclass 4, count 0 2006.162.07:44:59.05#ibcon#read 6, iclass 4, count 0 2006.162.07:44:59.05#ibcon#end of sib2, iclass 4, count 0 2006.162.07:44:59.05#ibcon#*mode == 0, iclass 4, count 0 2006.162.07:44:59.05#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.162.07:44:59.05#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.07:44:59.05#ibcon#*before write, iclass 4, count 0 2006.162.07:44:59.05#ibcon#enter sib2, iclass 4, count 0 2006.162.07:44:59.05#ibcon#flushed, iclass 4, count 0 2006.162.07:44:59.05#ibcon#about to write, iclass 4, count 0 2006.162.07:44:59.05#ibcon#wrote, iclass 4, count 0 2006.162.07:44:59.05#ibcon#about to read 3, iclass 4, count 0 2006.162.07:44:59.10#ibcon#read 3, iclass 4, count 0 2006.162.07:44:59.10#ibcon#about to read 4, iclass 4, count 0 2006.162.07:44:59.10#ibcon#read 4, iclass 4, count 0 2006.162.07:44:59.10#ibcon#about to read 5, iclass 4, count 0 2006.162.07:44:59.10#ibcon#read 5, iclass 4, count 0 2006.162.07:44:59.10#ibcon#about to read 6, iclass 4, count 0 2006.162.07:44:59.10#ibcon#read 6, iclass 4, count 0 2006.162.07:44:59.10#ibcon#end of sib2, iclass 4, count 0 2006.162.07:44:59.10#ibcon#*after write, iclass 4, count 0 2006.162.07:44:59.10#ibcon#*before return 0, iclass 4, count 0 2006.162.07:44:59.10#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.162.07:44:59.10#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.162.07:44:59.10#ibcon#about to clear, iclass 4 cls_cnt 0 2006.162.07:44:59.10#ibcon#cleared, iclass 4 cls_cnt 0 2006.162.07:44:59.10$vc4f8/va=1,8 2006.162.07:44:59.10#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.162.07:44:59.10#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.162.07:44:59.10#ibcon#ireg 11 cls_cnt 2 2006.162.07:44:59.10#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.162.07:44:59.10#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.162.07:44:59.10#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.162.07:44:59.10#ibcon#enter wrdev, iclass 6, count 2 2006.162.07:44:59.10#ibcon#first serial, iclass 6, count 2 2006.162.07:44:59.10#ibcon#enter sib2, iclass 6, count 2 2006.162.07:44:59.10#ibcon#flushed, iclass 6, count 2 2006.162.07:44:59.10#ibcon#about to write, iclass 6, count 2 2006.162.07:44:59.10#ibcon#wrote, iclass 6, count 2 2006.162.07:44:59.10#ibcon#about to read 3, iclass 6, count 2 2006.162.07:44:59.12#ibcon#read 3, iclass 6, count 2 2006.162.07:44:59.12#ibcon#about to read 4, iclass 6, count 2 2006.162.07:44:59.12#ibcon#read 4, iclass 6, count 2 2006.162.07:44:59.12#ibcon#about to read 5, iclass 6, count 2 2006.162.07:44:59.12#ibcon#read 5, iclass 6, count 2 2006.162.07:44:59.12#ibcon#about to read 6, iclass 6, count 2 2006.162.07:44:59.12#ibcon#read 6, iclass 6, count 2 2006.162.07:44:59.12#ibcon#end of sib2, iclass 6, count 2 2006.162.07:44:59.12#ibcon#*mode == 0, iclass 6, count 2 2006.162.07:44:59.12#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.162.07:44:59.12#ibcon#[25=AT01-08\r\n] 2006.162.07:44:59.12#ibcon#*before write, iclass 6, count 2 2006.162.07:44:59.12#ibcon#enter sib2, iclass 6, count 2 2006.162.07:44:59.12#ibcon#flushed, iclass 6, count 2 2006.162.07:44:59.12#ibcon#about to write, iclass 6, count 2 2006.162.07:44:59.12#ibcon#wrote, iclass 6, count 2 2006.162.07:44:59.12#ibcon#about to read 3, iclass 6, count 2 2006.162.07:44:59.15#ibcon#read 3, iclass 6, count 2 2006.162.07:44:59.15#ibcon#about to read 4, iclass 6, count 2 2006.162.07:44:59.15#ibcon#read 4, iclass 6, count 2 2006.162.07:44:59.15#ibcon#about to read 5, iclass 6, count 2 2006.162.07:44:59.15#ibcon#read 5, iclass 6, count 2 2006.162.07:44:59.15#ibcon#about to read 6, iclass 6, count 2 2006.162.07:44:59.15#ibcon#read 6, iclass 6, count 2 2006.162.07:44:59.15#ibcon#end of sib2, iclass 6, count 2 2006.162.07:44:59.15#ibcon#*after write, iclass 6, count 2 2006.162.07:44:59.15#ibcon#*before return 0, iclass 6, count 2 2006.162.07:44:59.15#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.162.07:44:59.15#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.162.07:44:59.15#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.162.07:44:59.15#ibcon#ireg 7 cls_cnt 0 2006.162.07:44:59.15#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.162.07:44:59.27#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.162.07:44:59.27#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.162.07:44:59.27#ibcon#enter wrdev, iclass 6, count 0 2006.162.07:44:59.27#ibcon#first serial, iclass 6, count 0 2006.162.07:44:59.27#ibcon#enter sib2, iclass 6, count 0 2006.162.07:44:59.27#ibcon#flushed, iclass 6, count 0 2006.162.07:44:59.27#ibcon#about to write, iclass 6, count 0 2006.162.07:44:59.27#ibcon#wrote, iclass 6, count 0 2006.162.07:44:59.27#ibcon#about to read 3, iclass 6, count 0 2006.162.07:44:59.29#ibcon#read 3, iclass 6, count 0 2006.162.07:44:59.29#ibcon#about to read 4, iclass 6, count 0 2006.162.07:44:59.29#ibcon#read 4, iclass 6, count 0 2006.162.07:44:59.29#ibcon#about to read 5, iclass 6, count 0 2006.162.07:44:59.29#ibcon#read 5, iclass 6, count 0 2006.162.07:44:59.29#ibcon#about to read 6, iclass 6, count 0 2006.162.07:44:59.29#ibcon#read 6, iclass 6, count 0 2006.162.07:44:59.29#ibcon#end of sib2, iclass 6, count 0 2006.162.07:44:59.29#ibcon#*mode == 0, iclass 6, count 0 2006.162.07:44:59.29#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.162.07:44:59.29#ibcon#[25=USB\r\n] 2006.162.07:44:59.29#ibcon#*before write, iclass 6, count 0 2006.162.07:44:59.29#ibcon#enter sib2, iclass 6, count 0 2006.162.07:44:59.29#ibcon#flushed, iclass 6, count 0 2006.162.07:44:59.29#ibcon#about to write, iclass 6, count 0 2006.162.07:44:59.29#ibcon#wrote, iclass 6, count 0 2006.162.07:44:59.29#ibcon#about to read 3, iclass 6, count 0 2006.162.07:44:59.32#ibcon#read 3, iclass 6, count 0 2006.162.07:44:59.32#ibcon#about to read 4, iclass 6, count 0 2006.162.07:44:59.32#ibcon#read 4, iclass 6, count 0 2006.162.07:44:59.32#ibcon#about to read 5, iclass 6, count 0 2006.162.07:44:59.32#ibcon#read 5, iclass 6, count 0 2006.162.07:44:59.32#ibcon#about to read 6, iclass 6, count 0 2006.162.07:44:59.32#ibcon#read 6, iclass 6, count 0 2006.162.07:44:59.32#ibcon#end of sib2, iclass 6, count 0 2006.162.07:44:59.32#ibcon#*after write, iclass 6, count 0 2006.162.07:44:59.32#ibcon#*before return 0, iclass 6, count 0 2006.162.07:44:59.32#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.162.07:44:59.32#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.162.07:44:59.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.162.07:44:59.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.162.07:44:59.32$vc4f8/valo=2,572.99 2006.162.07:44:59.32#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.162.07:44:59.32#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.162.07:44:59.32#ibcon#ireg 17 cls_cnt 0 2006.162.07:44:59.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.162.07:44:59.32#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.162.07:44:59.32#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.162.07:44:59.32#ibcon#enter wrdev, iclass 10, count 0 2006.162.07:44:59.32#ibcon#first serial, iclass 10, count 0 2006.162.07:44:59.32#ibcon#enter sib2, iclass 10, count 0 2006.162.07:44:59.32#ibcon#flushed, iclass 10, count 0 2006.162.07:44:59.32#ibcon#about to write, iclass 10, count 0 2006.162.07:44:59.32#ibcon#wrote, iclass 10, count 0 2006.162.07:44:59.32#ibcon#about to read 3, iclass 10, count 0 2006.162.07:44:59.34#ibcon#read 3, iclass 10, count 0 2006.162.07:44:59.34#ibcon#about to read 4, iclass 10, count 0 2006.162.07:44:59.34#ibcon#read 4, iclass 10, count 0 2006.162.07:44:59.34#ibcon#about to read 5, iclass 10, count 0 2006.162.07:44:59.34#ibcon#read 5, iclass 10, count 0 2006.162.07:44:59.34#ibcon#about to read 6, iclass 10, count 0 2006.162.07:44:59.34#ibcon#read 6, iclass 10, count 0 2006.162.07:44:59.34#ibcon#end of sib2, iclass 10, count 0 2006.162.07:44:59.34#ibcon#*mode == 0, iclass 10, count 0 2006.162.07:44:59.34#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.162.07:44:59.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.07:44:59.34#ibcon#*before write, iclass 10, count 0 2006.162.07:44:59.34#ibcon#enter sib2, iclass 10, count 0 2006.162.07:44:59.34#ibcon#flushed, iclass 10, count 0 2006.162.07:44:59.34#ibcon#about to write, iclass 10, count 0 2006.162.07:44:59.34#ibcon#wrote, iclass 10, count 0 2006.162.07:44:59.34#ibcon#about to read 3, iclass 10, count 0 2006.162.07:44:59.38#ibcon#read 3, iclass 10, count 0 2006.162.07:44:59.38#ibcon#about to read 4, iclass 10, count 0 2006.162.07:44:59.38#ibcon#read 4, iclass 10, count 0 2006.162.07:44:59.38#ibcon#about to read 5, iclass 10, count 0 2006.162.07:44:59.38#ibcon#read 5, iclass 10, count 0 2006.162.07:44:59.38#ibcon#about to read 6, iclass 10, count 0 2006.162.07:44:59.38#ibcon#read 6, iclass 10, count 0 2006.162.07:44:59.38#ibcon#end of sib2, iclass 10, count 0 2006.162.07:44:59.38#ibcon#*after write, iclass 10, count 0 2006.162.07:44:59.38#ibcon#*before return 0, iclass 10, count 0 2006.162.07:44:59.38#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.162.07:44:59.38#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.162.07:44:59.38#ibcon#about to clear, iclass 10 cls_cnt 0 2006.162.07:44:59.38#ibcon#cleared, iclass 10 cls_cnt 0 2006.162.07:44:59.38$vc4f8/va=2,7 2006.162.07:44:59.38#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.162.07:44:59.38#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.162.07:44:59.38#ibcon#ireg 11 cls_cnt 2 2006.162.07:44:59.38#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.162.07:44:59.44#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.162.07:44:59.44#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.162.07:44:59.44#ibcon#enter wrdev, iclass 12, count 2 2006.162.07:44:59.44#ibcon#first serial, iclass 12, count 2 2006.162.07:44:59.44#ibcon#enter sib2, iclass 12, count 2 2006.162.07:44:59.44#ibcon#flushed, iclass 12, count 2 2006.162.07:44:59.44#ibcon#about to write, iclass 12, count 2 2006.162.07:44:59.44#ibcon#wrote, iclass 12, count 2 2006.162.07:44:59.44#ibcon#about to read 3, iclass 12, count 2 2006.162.07:44:59.46#ibcon#read 3, iclass 12, count 2 2006.162.07:44:59.46#ibcon#about to read 4, iclass 12, count 2 2006.162.07:44:59.46#ibcon#read 4, iclass 12, count 2 2006.162.07:44:59.46#ibcon#about to read 5, iclass 12, count 2 2006.162.07:44:59.46#ibcon#read 5, iclass 12, count 2 2006.162.07:44:59.46#ibcon#about to read 6, iclass 12, count 2 2006.162.07:44:59.46#ibcon#read 6, iclass 12, count 2 2006.162.07:44:59.46#ibcon#end of sib2, iclass 12, count 2 2006.162.07:44:59.46#ibcon#*mode == 0, iclass 12, count 2 2006.162.07:44:59.46#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.162.07:44:59.46#ibcon#[25=AT02-07\r\n] 2006.162.07:44:59.46#ibcon#*before write, iclass 12, count 2 2006.162.07:44:59.46#ibcon#enter sib2, iclass 12, count 2 2006.162.07:44:59.46#ibcon#flushed, iclass 12, count 2 2006.162.07:44:59.46#ibcon#about to write, iclass 12, count 2 2006.162.07:44:59.46#ibcon#wrote, iclass 12, count 2 2006.162.07:44:59.46#ibcon#about to read 3, iclass 12, count 2 2006.162.07:44:59.49#ibcon#read 3, iclass 12, count 2 2006.162.07:44:59.49#ibcon#about to read 4, iclass 12, count 2 2006.162.07:44:59.49#ibcon#read 4, iclass 12, count 2 2006.162.07:44:59.49#ibcon#about to read 5, iclass 12, count 2 2006.162.07:44:59.49#ibcon#read 5, iclass 12, count 2 2006.162.07:44:59.49#ibcon#about to read 6, iclass 12, count 2 2006.162.07:44:59.49#ibcon#read 6, iclass 12, count 2 2006.162.07:44:59.49#ibcon#end of sib2, iclass 12, count 2 2006.162.07:44:59.49#ibcon#*after write, iclass 12, count 2 2006.162.07:44:59.49#ibcon#*before return 0, iclass 12, count 2 2006.162.07:44:59.49#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.162.07:44:59.49#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.162.07:44:59.49#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.162.07:44:59.49#ibcon#ireg 7 cls_cnt 0 2006.162.07:44:59.49#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.162.07:44:59.61#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.162.07:44:59.61#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.162.07:44:59.61#ibcon#enter wrdev, iclass 12, count 0 2006.162.07:44:59.61#ibcon#first serial, iclass 12, count 0 2006.162.07:44:59.61#ibcon#enter sib2, iclass 12, count 0 2006.162.07:44:59.61#ibcon#flushed, iclass 12, count 0 2006.162.07:44:59.61#ibcon#about to write, iclass 12, count 0 2006.162.07:44:59.61#ibcon#wrote, iclass 12, count 0 2006.162.07:44:59.61#ibcon#about to read 3, iclass 12, count 0 2006.162.07:44:59.63#ibcon#read 3, iclass 12, count 0 2006.162.07:44:59.63#ibcon#about to read 4, iclass 12, count 0 2006.162.07:44:59.63#ibcon#read 4, iclass 12, count 0 2006.162.07:44:59.63#ibcon#about to read 5, iclass 12, count 0 2006.162.07:44:59.63#ibcon#read 5, iclass 12, count 0 2006.162.07:44:59.63#ibcon#about to read 6, iclass 12, count 0 2006.162.07:44:59.63#ibcon#read 6, iclass 12, count 0 2006.162.07:44:59.63#ibcon#end of sib2, iclass 12, count 0 2006.162.07:44:59.63#ibcon#*mode == 0, iclass 12, count 0 2006.162.07:44:59.63#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.162.07:44:59.63#ibcon#[25=USB\r\n] 2006.162.07:44:59.63#ibcon#*before write, iclass 12, count 0 2006.162.07:44:59.63#ibcon#enter sib2, iclass 12, count 0 2006.162.07:44:59.63#ibcon#flushed, iclass 12, count 0 2006.162.07:44:59.63#ibcon#about to write, iclass 12, count 0 2006.162.07:44:59.63#ibcon#wrote, iclass 12, count 0 2006.162.07:44:59.63#ibcon#about to read 3, iclass 12, count 0 2006.162.07:44:59.66#ibcon#read 3, iclass 12, count 0 2006.162.07:44:59.66#ibcon#about to read 4, iclass 12, count 0 2006.162.07:44:59.66#ibcon#read 4, iclass 12, count 0 2006.162.07:44:59.66#ibcon#about to read 5, iclass 12, count 0 2006.162.07:44:59.66#ibcon#read 5, iclass 12, count 0 2006.162.07:44:59.66#ibcon#about to read 6, iclass 12, count 0 2006.162.07:44:59.66#ibcon#read 6, iclass 12, count 0 2006.162.07:44:59.66#ibcon#end of sib2, iclass 12, count 0 2006.162.07:44:59.66#ibcon#*after write, iclass 12, count 0 2006.162.07:44:59.66#ibcon#*before return 0, iclass 12, count 0 2006.162.07:44:59.66#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.162.07:44:59.66#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.162.07:44:59.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.162.07:44:59.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.162.07:44:59.66$vc4f8/valo=3,672.99 2006.162.07:44:59.66#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.162.07:44:59.66#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.162.07:44:59.66#ibcon#ireg 17 cls_cnt 0 2006.162.07:44:59.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.07:44:59.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.07:44:59.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.07:44:59.66#ibcon#enter wrdev, iclass 14, count 0 2006.162.07:44:59.66#ibcon#first serial, iclass 14, count 0 2006.162.07:44:59.66#ibcon#enter sib2, iclass 14, count 0 2006.162.07:44:59.66#ibcon#flushed, iclass 14, count 0 2006.162.07:44:59.66#ibcon#about to write, iclass 14, count 0 2006.162.07:44:59.66#ibcon#wrote, iclass 14, count 0 2006.162.07:44:59.66#ibcon#about to read 3, iclass 14, count 0 2006.162.07:44:59.68#ibcon#read 3, iclass 14, count 0 2006.162.07:44:59.68#ibcon#about to read 4, iclass 14, count 0 2006.162.07:44:59.69#ibcon#read 4, iclass 14, count 0 2006.162.07:44:59.69#ibcon#about to read 5, iclass 14, count 0 2006.162.07:44:59.69#ibcon#read 5, iclass 14, count 0 2006.162.07:44:59.69#ibcon#about to read 6, iclass 14, count 0 2006.162.07:44:59.69#ibcon#read 6, iclass 14, count 0 2006.162.07:44:59.69#ibcon#end of sib2, iclass 14, count 0 2006.162.07:44:59.69#ibcon#*mode == 0, iclass 14, count 0 2006.162.07:44:59.69#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.07:44:59.69#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.07:44:59.69#ibcon#*before write, iclass 14, count 0 2006.162.07:44:59.69#ibcon#enter sib2, iclass 14, count 0 2006.162.07:44:59.69#ibcon#flushed, iclass 14, count 0 2006.162.07:44:59.69#ibcon#about to write, iclass 14, count 0 2006.162.07:44:59.69#ibcon#wrote, iclass 14, count 0 2006.162.07:44:59.69#ibcon#about to read 3, iclass 14, count 0 2006.162.07:44:59.73#ibcon#read 3, iclass 14, count 0 2006.162.07:44:59.73#ibcon#about to read 4, iclass 14, count 0 2006.162.07:44:59.73#ibcon#read 4, iclass 14, count 0 2006.162.07:44:59.73#ibcon#about to read 5, iclass 14, count 0 2006.162.07:44:59.73#ibcon#read 5, iclass 14, count 0 2006.162.07:44:59.73#ibcon#about to read 6, iclass 14, count 0 2006.162.07:44:59.73#ibcon#read 6, iclass 14, count 0 2006.162.07:44:59.73#ibcon#end of sib2, iclass 14, count 0 2006.162.07:44:59.73#ibcon#*after write, iclass 14, count 0 2006.162.07:44:59.73#ibcon#*before return 0, iclass 14, count 0 2006.162.07:44:59.73#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.07:44:59.73#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.162.07:44:59.73#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.07:44:59.73#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.07:44:59.73$vc4f8/va=3,6 2006.162.07:44:59.73#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.162.07:44:59.73#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.162.07:44:59.73#ibcon#ireg 11 cls_cnt 2 2006.162.07:44:59.73#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.162.07:44:59.78#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.162.07:44:59.78#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.162.07:44:59.78#ibcon#enter wrdev, iclass 16, count 2 2006.162.07:44:59.78#ibcon#first serial, iclass 16, count 2 2006.162.07:44:59.78#ibcon#enter sib2, iclass 16, count 2 2006.162.07:44:59.78#ibcon#flushed, iclass 16, count 2 2006.162.07:44:59.78#ibcon#about to write, iclass 16, count 2 2006.162.07:44:59.78#ibcon#wrote, iclass 16, count 2 2006.162.07:44:59.78#ibcon#about to read 3, iclass 16, count 2 2006.162.07:44:59.80#ibcon#read 3, iclass 16, count 2 2006.162.07:44:59.80#ibcon#about to read 4, iclass 16, count 2 2006.162.07:44:59.80#ibcon#read 4, iclass 16, count 2 2006.162.07:44:59.80#ibcon#about to read 5, iclass 16, count 2 2006.162.07:44:59.80#ibcon#read 5, iclass 16, count 2 2006.162.07:44:59.80#ibcon#about to read 6, iclass 16, count 2 2006.162.07:44:59.80#ibcon#read 6, iclass 16, count 2 2006.162.07:44:59.80#ibcon#end of sib2, iclass 16, count 2 2006.162.07:44:59.80#ibcon#*mode == 0, iclass 16, count 2 2006.162.07:44:59.80#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.162.07:44:59.80#ibcon#[25=AT03-06\r\n] 2006.162.07:44:59.80#ibcon#*before write, iclass 16, count 2 2006.162.07:44:59.80#ibcon#enter sib2, iclass 16, count 2 2006.162.07:44:59.80#ibcon#flushed, iclass 16, count 2 2006.162.07:44:59.80#ibcon#about to write, iclass 16, count 2 2006.162.07:44:59.81#ibcon#wrote, iclass 16, count 2 2006.162.07:44:59.81#ibcon#about to read 3, iclass 16, count 2 2006.162.07:44:59.84#ibcon#read 3, iclass 16, count 2 2006.162.07:44:59.84#ibcon#about to read 4, iclass 16, count 2 2006.162.07:44:59.84#ibcon#read 4, iclass 16, count 2 2006.162.07:44:59.84#ibcon#about to read 5, iclass 16, count 2 2006.162.07:44:59.84#ibcon#read 5, iclass 16, count 2 2006.162.07:44:59.84#ibcon#about to read 6, iclass 16, count 2 2006.162.07:44:59.84#ibcon#read 6, iclass 16, count 2 2006.162.07:44:59.84#ibcon#end of sib2, iclass 16, count 2 2006.162.07:44:59.84#ibcon#*after write, iclass 16, count 2 2006.162.07:44:59.84#ibcon#*before return 0, iclass 16, count 2 2006.162.07:44:59.84#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.162.07:44:59.84#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.162.07:44:59.84#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.162.07:44:59.84#ibcon#ireg 7 cls_cnt 0 2006.162.07:44:59.84#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.162.07:44:59.96#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.162.07:44:59.96#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.162.07:44:59.96#ibcon#enter wrdev, iclass 16, count 0 2006.162.07:44:59.96#ibcon#first serial, iclass 16, count 0 2006.162.07:44:59.96#ibcon#enter sib2, iclass 16, count 0 2006.162.07:44:59.96#ibcon#flushed, iclass 16, count 0 2006.162.07:44:59.96#ibcon#about to write, iclass 16, count 0 2006.162.07:44:59.96#ibcon#wrote, iclass 16, count 0 2006.162.07:44:59.96#ibcon#about to read 3, iclass 16, count 0 2006.162.07:44:59.98#ibcon#read 3, iclass 16, count 0 2006.162.07:44:59.98#ibcon#about to read 4, iclass 16, count 0 2006.162.07:44:59.98#ibcon#read 4, iclass 16, count 0 2006.162.07:44:59.98#ibcon#about to read 5, iclass 16, count 0 2006.162.07:44:59.98#ibcon#read 5, iclass 16, count 0 2006.162.07:44:59.98#ibcon#about to read 6, iclass 16, count 0 2006.162.07:44:59.98#ibcon#read 6, iclass 16, count 0 2006.162.07:44:59.98#ibcon#end of sib2, iclass 16, count 0 2006.162.07:44:59.98#ibcon#*mode == 0, iclass 16, count 0 2006.162.07:44:59.98#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.162.07:44:59.98#ibcon#[25=USB\r\n] 2006.162.07:44:59.98#ibcon#*before write, iclass 16, count 0 2006.162.07:44:59.98#ibcon#enter sib2, iclass 16, count 0 2006.162.07:44:59.98#ibcon#flushed, iclass 16, count 0 2006.162.07:44:59.98#ibcon#about to write, iclass 16, count 0 2006.162.07:44:59.98#ibcon#wrote, iclass 16, count 0 2006.162.07:44:59.98#ibcon#about to read 3, iclass 16, count 0 2006.162.07:45:00.01#ibcon#read 3, iclass 16, count 0 2006.162.07:45:00.01#ibcon#about to read 4, iclass 16, count 0 2006.162.07:45:00.01#ibcon#read 4, iclass 16, count 0 2006.162.07:45:00.01#ibcon#about to read 5, iclass 16, count 0 2006.162.07:45:00.01#ibcon#read 5, iclass 16, count 0 2006.162.07:45:00.01#ibcon#about to read 6, iclass 16, count 0 2006.162.07:45:00.01#ibcon#read 6, iclass 16, count 0 2006.162.07:45:00.01#ibcon#end of sib2, iclass 16, count 0 2006.162.07:45:00.01#ibcon#*after write, iclass 16, count 0 2006.162.07:45:00.01#ibcon#*before return 0, iclass 16, count 0 2006.162.07:45:00.01#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.162.07:45:00.01#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.162.07:45:00.01#ibcon#about to clear, iclass 16 cls_cnt 0 2006.162.07:45:00.01#ibcon#cleared, iclass 16 cls_cnt 0 2006.162.07:45:00.01$vc4f8/valo=4,832.99 2006.162.07:45:00.01#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.162.07:45:00.01#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.162.07:45:00.01#ibcon#ireg 17 cls_cnt 0 2006.162.07:45:00.01#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:45:00.01#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:45:00.01#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:45:00.01#ibcon#enter wrdev, iclass 18, count 0 2006.162.07:45:00.01#ibcon#first serial, iclass 18, count 0 2006.162.07:45:00.01#ibcon#enter sib2, iclass 18, count 0 2006.162.07:45:00.01#ibcon#flushed, iclass 18, count 0 2006.162.07:45:00.01#ibcon#about to write, iclass 18, count 0 2006.162.07:45:00.01#ibcon#wrote, iclass 18, count 0 2006.162.07:45:00.01#ibcon#about to read 3, iclass 18, count 0 2006.162.07:45:00.03#ibcon#read 3, iclass 18, count 0 2006.162.07:45:00.03#ibcon#about to read 4, iclass 18, count 0 2006.162.07:45:00.03#ibcon#read 4, iclass 18, count 0 2006.162.07:45:00.03#ibcon#about to read 5, iclass 18, count 0 2006.162.07:45:00.03#ibcon#read 5, iclass 18, count 0 2006.162.07:45:00.03#ibcon#about to read 6, iclass 18, count 0 2006.162.07:45:00.03#ibcon#read 6, iclass 18, count 0 2006.162.07:45:00.03#ibcon#end of sib2, iclass 18, count 0 2006.162.07:45:00.03#ibcon#*mode == 0, iclass 18, count 0 2006.162.07:45:00.03#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.162.07:45:00.03#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.07:45:00.03#ibcon#*before write, iclass 18, count 0 2006.162.07:45:00.03#ibcon#enter sib2, iclass 18, count 0 2006.162.07:45:00.03#ibcon#flushed, iclass 18, count 0 2006.162.07:45:00.03#ibcon#about to write, iclass 18, count 0 2006.162.07:45:00.03#ibcon#wrote, iclass 18, count 0 2006.162.07:45:00.03#ibcon#about to read 3, iclass 18, count 0 2006.162.07:45:00.07#ibcon#read 3, iclass 18, count 0 2006.162.07:45:00.07#ibcon#about to read 4, iclass 18, count 0 2006.162.07:45:00.07#ibcon#read 4, iclass 18, count 0 2006.162.07:45:00.07#ibcon#about to read 5, iclass 18, count 0 2006.162.07:45:00.07#ibcon#read 5, iclass 18, count 0 2006.162.07:45:00.07#ibcon#about to read 6, iclass 18, count 0 2006.162.07:45:00.07#ibcon#read 6, iclass 18, count 0 2006.162.07:45:00.07#ibcon#end of sib2, iclass 18, count 0 2006.162.07:45:00.07#ibcon#*after write, iclass 18, count 0 2006.162.07:45:00.07#ibcon#*before return 0, iclass 18, count 0 2006.162.07:45:00.07#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:45:00.07#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:45:00.07#ibcon#about to clear, iclass 18 cls_cnt 0 2006.162.07:45:00.07#ibcon#cleared, iclass 18 cls_cnt 0 2006.162.07:45:00.07$vc4f8/va=4,7 2006.162.07:45:00.07#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.162.07:45:00.07#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.162.07:45:00.07#ibcon#ireg 11 cls_cnt 2 2006.162.07:45:00.07#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:45:00.13#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:45:00.13#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:45:00.13#ibcon#enter wrdev, iclass 20, count 2 2006.162.07:45:00.13#ibcon#first serial, iclass 20, count 2 2006.162.07:45:00.13#ibcon#enter sib2, iclass 20, count 2 2006.162.07:45:00.13#ibcon#flushed, iclass 20, count 2 2006.162.07:45:00.13#ibcon#about to write, iclass 20, count 2 2006.162.07:45:00.13#ibcon#wrote, iclass 20, count 2 2006.162.07:45:00.13#ibcon#about to read 3, iclass 20, count 2 2006.162.07:45:00.15#ibcon#read 3, iclass 20, count 2 2006.162.07:45:00.15#ibcon#about to read 4, iclass 20, count 2 2006.162.07:45:00.15#ibcon#read 4, iclass 20, count 2 2006.162.07:45:00.15#ibcon#about to read 5, iclass 20, count 2 2006.162.07:45:00.15#ibcon#read 5, iclass 20, count 2 2006.162.07:45:00.15#ibcon#about to read 6, iclass 20, count 2 2006.162.07:45:00.15#ibcon#read 6, iclass 20, count 2 2006.162.07:45:00.15#ibcon#end of sib2, iclass 20, count 2 2006.162.07:45:00.15#ibcon#*mode == 0, iclass 20, count 2 2006.162.07:45:00.15#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.162.07:45:00.15#ibcon#[25=AT04-07\r\n] 2006.162.07:45:00.15#ibcon#*before write, iclass 20, count 2 2006.162.07:45:00.15#ibcon#enter sib2, iclass 20, count 2 2006.162.07:45:00.15#ibcon#flushed, iclass 20, count 2 2006.162.07:45:00.15#ibcon#about to write, iclass 20, count 2 2006.162.07:45:00.15#ibcon#wrote, iclass 20, count 2 2006.162.07:45:00.15#ibcon#about to read 3, iclass 20, count 2 2006.162.07:45:00.18#ibcon#read 3, iclass 20, count 2 2006.162.07:45:00.18#ibcon#about to read 4, iclass 20, count 2 2006.162.07:45:00.18#ibcon#read 4, iclass 20, count 2 2006.162.07:45:00.18#ibcon#about to read 5, iclass 20, count 2 2006.162.07:45:00.18#ibcon#read 5, iclass 20, count 2 2006.162.07:45:00.18#ibcon#about to read 6, iclass 20, count 2 2006.162.07:45:00.18#ibcon#read 6, iclass 20, count 2 2006.162.07:45:00.18#ibcon#end of sib2, iclass 20, count 2 2006.162.07:45:00.18#ibcon#*after write, iclass 20, count 2 2006.162.07:45:00.18#ibcon#*before return 0, iclass 20, count 2 2006.162.07:45:00.18#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:45:00.18#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:45:00.18#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.162.07:45:00.18#ibcon#ireg 7 cls_cnt 0 2006.162.07:45:00.18#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:45:00.30#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:45:00.30#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:45:00.30#ibcon#enter wrdev, iclass 20, count 0 2006.162.07:45:00.30#ibcon#first serial, iclass 20, count 0 2006.162.07:45:00.30#ibcon#enter sib2, iclass 20, count 0 2006.162.07:45:00.30#ibcon#flushed, iclass 20, count 0 2006.162.07:45:00.30#ibcon#about to write, iclass 20, count 0 2006.162.07:45:00.30#ibcon#wrote, iclass 20, count 0 2006.162.07:45:00.30#ibcon#about to read 3, iclass 20, count 0 2006.162.07:45:00.32#ibcon#read 3, iclass 20, count 0 2006.162.07:45:00.32#ibcon#about to read 4, iclass 20, count 0 2006.162.07:45:00.32#ibcon#read 4, iclass 20, count 0 2006.162.07:45:00.32#ibcon#about to read 5, iclass 20, count 0 2006.162.07:45:00.32#ibcon#read 5, iclass 20, count 0 2006.162.07:45:00.32#ibcon#about to read 6, iclass 20, count 0 2006.162.07:45:00.32#ibcon#read 6, iclass 20, count 0 2006.162.07:45:00.32#ibcon#end of sib2, iclass 20, count 0 2006.162.07:45:00.32#ibcon#*mode == 0, iclass 20, count 0 2006.162.07:45:00.32#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.07:45:00.32#ibcon#[25=USB\r\n] 2006.162.07:45:00.32#ibcon#*before write, iclass 20, count 0 2006.162.07:45:00.32#ibcon#enter sib2, iclass 20, count 0 2006.162.07:45:00.32#ibcon#flushed, iclass 20, count 0 2006.162.07:45:00.32#ibcon#about to write, iclass 20, count 0 2006.162.07:45:00.32#ibcon#wrote, iclass 20, count 0 2006.162.07:45:00.32#ibcon#about to read 3, iclass 20, count 0 2006.162.07:45:00.35#ibcon#read 3, iclass 20, count 0 2006.162.07:45:00.35#ibcon#about to read 4, iclass 20, count 0 2006.162.07:45:00.35#ibcon#read 4, iclass 20, count 0 2006.162.07:45:00.35#ibcon#about to read 5, iclass 20, count 0 2006.162.07:45:00.35#ibcon#read 5, iclass 20, count 0 2006.162.07:45:00.35#ibcon#about to read 6, iclass 20, count 0 2006.162.07:45:00.35#ibcon#read 6, iclass 20, count 0 2006.162.07:45:00.35#ibcon#end of sib2, iclass 20, count 0 2006.162.07:45:00.35#ibcon#*after write, iclass 20, count 0 2006.162.07:45:00.35#ibcon#*before return 0, iclass 20, count 0 2006.162.07:45:00.35#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:45:00.35#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:45:00.35#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.07:45:00.35#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.07:45:00.35$vc4f8/valo=5,652.99 2006.162.07:45:00.35#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.162.07:45:00.35#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.162.07:45:00.35#ibcon#ireg 17 cls_cnt 0 2006.162.07:45:00.35#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:45:00.35#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:45:00.35#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:45:00.35#ibcon#enter wrdev, iclass 22, count 0 2006.162.07:45:00.35#ibcon#first serial, iclass 22, count 0 2006.162.07:45:00.35#ibcon#enter sib2, iclass 22, count 0 2006.162.07:45:00.35#ibcon#flushed, iclass 22, count 0 2006.162.07:45:00.35#ibcon#about to write, iclass 22, count 0 2006.162.07:45:00.35#ibcon#wrote, iclass 22, count 0 2006.162.07:45:00.35#ibcon#about to read 3, iclass 22, count 0 2006.162.07:45:00.37#ibcon#read 3, iclass 22, count 0 2006.162.07:45:00.37#ibcon#about to read 4, iclass 22, count 0 2006.162.07:45:00.37#ibcon#read 4, iclass 22, count 0 2006.162.07:45:00.37#ibcon#about to read 5, iclass 22, count 0 2006.162.07:45:00.37#ibcon#read 5, iclass 22, count 0 2006.162.07:45:00.37#ibcon#about to read 6, iclass 22, count 0 2006.162.07:45:00.37#ibcon#read 6, iclass 22, count 0 2006.162.07:45:00.37#ibcon#end of sib2, iclass 22, count 0 2006.162.07:45:00.37#ibcon#*mode == 0, iclass 22, count 0 2006.162.07:45:00.37#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.07:45:00.37#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.07:45:00.37#ibcon#*before write, iclass 22, count 0 2006.162.07:45:00.37#ibcon#enter sib2, iclass 22, count 0 2006.162.07:45:00.37#ibcon#flushed, iclass 22, count 0 2006.162.07:45:00.37#ibcon#about to write, iclass 22, count 0 2006.162.07:45:00.37#ibcon#wrote, iclass 22, count 0 2006.162.07:45:00.37#ibcon#about to read 3, iclass 22, count 0 2006.162.07:45:00.41#ibcon#read 3, iclass 22, count 0 2006.162.07:45:00.41#ibcon#about to read 4, iclass 22, count 0 2006.162.07:45:00.41#ibcon#read 4, iclass 22, count 0 2006.162.07:45:00.41#ibcon#about to read 5, iclass 22, count 0 2006.162.07:45:00.41#ibcon#read 5, iclass 22, count 0 2006.162.07:45:00.41#ibcon#about to read 6, iclass 22, count 0 2006.162.07:45:00.41#ibcon#read 6, iclass 22, count 0 2006.162.07:45:00.41#ibcon#end of sib2, iclass 22, count 0 2006.162.07:45:00.41#ibcon#*after write, iclass 22, count 0 2006.162.07:45:00.41#ibcon#*before return 0, iclass 22, count 0 2006.162.07:45:00.41#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:45:00.41#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:45:00.41#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.07:45:00.41#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.07:45:00.41$vc4f8/va=5,7 2006.162.07:45:00.41#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.162.07:45:00.41#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.162.07:45:00.41#ibcon#ireg 11 cls_cnt 2 2006.162.07:45:00.41#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:45:00.47#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:45:00.47#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:45:00.47#ibcon#enter wrdev, iclass 24, count 2 2006.162.07:45:00.47#ibcon#first serial, iclass 24, count 2 2006.162.07:45:00.47#ibcon#enter sib2, iclass 24, count 2 2006.162.07:45:00.47#ibcon#flushed, iclass 24, count 2 2006.162.07:45:00.47#ibcon#about to write, iclass 24, count 2 2006.162.07:45:00.47#ibcon#wrote, iclass 24, count 2 2006.162.07:45:00.47#ibcon#about to read 3, iclass 24, count 2 2006.162.07:45:00.49#ibcon#read 3, iclass 24, count 2 2006.162.07:45:00.49#ibcon#about to read 4, iclass 24, count 2 2006.162.07:45:00.49#ibcon#read 4, iclass 24, count 2 2006.162.07:45:00.49#ibcon#about to read 5, iclass 24, count 2 2006.162.07:45:00.49#ibcon#read 5, iclass 24, count 2 2006.162.07:45:00.49#ibcon#about to read 6, iclass 24, count 2 2006.162.07:45:00.49#ibcon#read 6, iclass 24, count 2 2006.162.07:45:00.49#ibcon#end of sib2, iclass 24, count 2 2006.162.07:45:00.49#ibcon#*mode == 0, iclass 24, count 2 2006.162.07:45:00.49#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.162.07:45:00.49#ibcon#[25=AT05-07\r\n] 2006.162.07:45:00.49#ibcon#*before write, iclass 24, count 2 2006.162.07:45:00.49#ibcon#enter sib2, iclass 24, count 2 2006.162.07:45:00.49#ibcon#flushed, iclass 24, count 2 2006.162.07:45:00.49#ibcon#about to write, iclass 24, count 2 2006.162.07:45:00.49#ibcon#wrote, iclass 24, count 2 2006.162.07:45:00.49#ibcon#about to read 3, iclass 24, count 2 2006.162.07:45:00.53#ibcon#read 3, iclass 24, count 2 2006.162.07:45:00.53#ibcon#about to read 4, iclass 24, count 2 2006.162.07:45:00.53#ibcon#read 4, iclass 24, count 2 2006.162.07:45:00.53#ibcon#about to read 5, iclass 24, count 2 2006.162.07:45:00.53#ibcon#read 5, iclass 24, count 2 2006.162.07:45:00.53#ibcon#about to read 6, iclass 24, count 2 2006.162.07:45:00.53#ibcon#read 6, iclass 24, count 2 2006.162.07:45:00.53#ibcon#end of sib2, iclass 24, count 2 2006.162.07:45:00.53#ibcon#*after write, iclass 24, count 2 2006.162.07:45:00.53#ibcon#*before return 0, iclass 24, count 2 2006.162.07:45:00.53#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:45:00.53#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:45:00.53#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.162.07:45:00.53#ibcon#ireg 7 cls_cnt 0 2006.162.07:45:00.53#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:45:00.65#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:45:00.65#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:45:00.65#ibcon#enter wrdev, iclass 24, count 0 2006.162.07:45:00.65#ibcon#first serial, iclass 24, count 0 2006.162.07:45:00.65#ibcon#enter sib2, iclass 24, count 0 2006.162.07:45:00.65#ibcon#flushed, iclass 24, count 0 2006.162.07:45:00.65#ibcon#about to write, iclass 24, count 0 2006.162.07:45:00.65#ibcon#wrote, iclass 24, count 0 2006.162.07:45:00.65#ibcon#about to read 3, iclass 24, count 0 2006.162.07:45:00.67#ibcon#read 3, iclass 24, count 0 2006.162.07:45:00.67#ibcon#about to read 4, iclass 24, count 0 2006.162.07:45:00.67#ibcon#read 4, iclass 24, count 0 2006.162.07:45:00.67#ibcon#about to read 5, iclass 24, count 0 2006.162.07:45:00.67#ibcon#read 5, iclass 24, count 0 2006.162.07:45:00.67#ibcon#about to read 6, iclass 24, count 0 2006.162.07:45:00.67#ibcon#read 6, iclass 24, count 0 2006.162.07:45:00.67#ibcon#end of sib2, iclass 24, count 0 2006.162.07:45:00.67#ibcon#*mode == 0, iclass 24, count 0 2006.162.07:45:00.67#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.07:45:00.67#ibcon#[25=USB\r\n] 2006.162.07:45:00.67#ibcon#*before write, iclass 24, count 0 2006.162.07:45:00.67#ibcon#enter sib2, iclass 24, count 0 2006.162.07:45:00.67#ibcon#flushed, iclass 24, count 0 2006.162.07:45:00.67#ibcon#about to write, iclass 24, count 0 2006.162.07:45:00.67#ibcon#wrote, iclass 24, count 0 2006.162.07:45:00.67#ibcon#about to read 3, iclass 24, count 0 2006.162.07:45:00.70#ibcon#read 3, iclass 24, count 0 2006.162.07:45:00.70#ibcon#about to read 4, iclass 24, count 0 2006.162.07:45:00.70#ibcon#read 4, iclass 24, count 0 2006.162.07:45:00.70#ibcon#about to read 5, iclass 24, count 0 2006.162.07:45:00.70#ibcon#read 5, iclass 24, count 0 2006.162.07:45:00.70#ibcon#about to read 6, iclass 24, count 0 2006.162.07:45:00.70#ibcon#read 6, iclass 24, count 0 2006.162.07:45:00.70#ibcon#end of sib2, iclass 24, count 0 2006.162.07:45:00.70#ibcon#*after write, iclass 24, count 0 2006.162.07:45:00.70#ibcon#*before return 0, iclass 24, count 0 2006.162.07:45:00.70#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:45:00.70#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:45:00.70#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.07:45:00.70#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.07:45:00.70$vc4f8/valo=6,772.99 2006.162.07:45:00.70#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.162.07:45:00.70#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.162.07:45:00.70#ibcon#ireg 17 cls_cnt 0 2006.162.07:45:00.70#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:45:00.70#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:45:00.70#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:45:00.70#ibcon#enter wrdev, iclass 26, count 0 2006.162.07:45:00.70#ibcon#first serial, iclass 26, count 0 2006.162.07:45:00.70#ibcon#enter sib2, iclass 26, count 0 2006.162.07:45:00.70#ibcon#flushed, iclass 26, count 0 2006.162.07:45:00.70#ibcon#about to write, iclass 26, count 0 2006.162.07:45:00.70#ibcon#wrote, iclass 26, count 0 2006.162.07:45:00.70#ibcon#about to read 3, iclass 26, count 0 2006.162.07:45:00.72#ibcon#read 3, iclass 26, count 0 2006.162.07:45:00.73#ibcon#about to read 4, iclass 26, count 0 2006.162.07:45:00.73#ibcon#read 4, iclass 26, count 0 2006.162.07:45:00.73#ibcon#about to read 5, iclass 26, count 0 2006.162.07:45:00.73#ibcon#read 5, iclass 26, count 0 2006.162.07:45:00.73#ibcon#about to read 6, iclass 26, count 0 2006.162.07:45:00.73#ibcon#read 6, iclass 26, count 0 2006.162.07:45:00.73#ibcon#end of sib2, iclass 26, count 0 2006.162.07:45:00.73#ibcon#*mode == 0, iclass 26, count 0 2006.162.07:45:00.73#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.162.07:45:00.73#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.07:45:00.73#ibcon#*before write, iclass 26, count 0 2006.162.07:45:00.73#ibcon#enter sib2, iclass 26, count 0 2006.162.07:45:00.73#ibcon#flushed, iclass 26, count 0 2006.162.07:45:00.73#ibcon#about to write, iclass 26, count 0 2006.162.07:45:00.73#ibcon#wrote, iclass 26, count 0 2006.162.07:45:00.73#ibcon#about to read 3, iclass 26, count 0 2006.162.07:45:00.77#ibcon#read 3, iclass 26, count 0 2006.162.07:45:00.77#ibcon#about to read 4, iclass 26, count 0 2006.162.07:45:00.77#ibcon#read 4, iclass 26, count 0 2006.162.07:45:00.77#ibcon#about to read 5, iclass 26, count 0 2006.162.07:45:00.77#ibcon#read 5, iclass 26, count 0 2006.162.07:45:00.77#ibcon#about to read 6, iclass 26, count 0 2006.162.07:45:00.77#ibcon#read 6, iclass 26, count 0 2006.162.07:45:00.77#ibcon#end of sib2, iclass 26, count 0 2006.162.07:45:00.77#ibcon#*after write, iclass 26, count 0 2006.162.07:45:00.77#ibcon#*before return 0, iclass 26, count 0 2006.162.07:45:00.77#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:45:00.77#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:45:00.77#ibcon#about to clear, iclass 26 cls_cnt 0 2006.162.07:45:00.77#ibcon#cleared, iclass 26 cls_cnt 0 2006.162.07:45:00.77$vc4f8/va=6,6 2006.162.07:45:00.77#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.162.07:45:00.77#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.162.07:45:00.77#ibcon#ireg 11 cls_cnt 2 2006.162.07:45:00.77#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.162.07:45:00.82#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.162.07:45:00.82#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.162.07:45:00.82#ibcon#enter wrdev, iclass 28, count 2 2006.162.07:45:00.82#ibcon#first serial, iclass 28, count 2 2006.162.07:45:00.82#ibcon#enter sib2, iclass 28, count 2 2006.162.07:45:00.82#ibcon#flushed, iclass 28, count 2 2006.162.07:45:00.82#ibcon#about to write, iclass 28, count 2 2006.162.07:45:00.82#ibcon#wrote, iclass 28, count 2 2006.162.07:45:00.82#ibcon#about to read 3, iclass 28, count 2 2006.162.07:45:00.84#ibcon#read 3, iclass 28, count 2 2006.162.07:45:00.84#ibcon#about to read 4, iclass 28, count 2 2006.162.07:45:00.84#ibcon#read 4, iclass 28, count 2 2006.162.07:45:00.84#ibcon#about to read 5, iclass 28, count 2 2006.162.07:45:00.84#ibcon#read 5, iclass 28, count 2 2006.162.07:45:00.84#ibcon#about to read 6, iclass 28, count 2 2006.162.07:45:00.84#ibcon#read 6, iclass 28, count 2 2006.162.07:45:00.84#ibcon#end of sib2, iclass 28, count 2 2006.162.07:45:00.84#ibcon#*mode == 0, iclass 28, count 2 2006.162.07:45:00.84#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.162.07:45:00.84#ibcon#[25=AT06-06\r\n] 2006.162.07:45:00.84#ibcon#*before write, iclass 28, count 2 2006.162.07:45:00.84#ibcon#enter sib2, iclass 28, count 2 2006.162.07:45:00.84#ibcon#flushed, iclass 28, count 2 2006.162.07:45:00.84#ibcon#about to write, iclass 28, count 2 2006.162.07:45:00.84#ibcon#wrote, iclass 28, count 2 2006.162.07:45:00.84#ibcon#about to read 3, iclass 28, count 2 2006.162.07:45:00.87#ibcon#read 3, iclass 28, count 2 2006.162.07:45:00.87#ibcon#about to read 4, iclass 28, count 2 2006.162.07:45:00.87#ibcon#read 4, iclass 28, count 2 2006.162.07:45:00.87#ibcon#about to read 5, iclass 28, count 2 2006.162.07:45:00.87#ibcon#read 5, iclass 28, count 2 2006.162.07:45:00.87#ibcon#about to read 6, iclass 28, count 2 2006.162.07:45:00.87#ibcon#read 6, iclass 28, count 2 2006.162.07:45:00.87#ibcon#end of sib2, iclass 28, count 2 2006.162.07:45:00.87#ibcon#*after write, iclass 28, count 2 2006.162.07:45:00.87#ibcon#*before return 0, iclass 28, count 2 2006.162.07:45:00.87#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.162.07:45:00.87#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.162.07:45:00.87#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.162.07:45:00.87#ibcon#ireg 7 cls_cnt 0 2006.162.07:45:00.87#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.162.07:45:00.99#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.162.07:45:00.99#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.162.07:45:00.99#ibcon#enter wrdev, iclass 28, count 0 2006.162.07:45:00.99#ibcon#first serial, iclass 28, count 0 2006.162.07:45:00.99#ibcon#enter sib2, iclass 28, count 0 2006.162.07:45:00.99#ibcon#flushed, iclass 28, count 0 2006.162.07:45:00.99#ibcon#about to write, iclass 28, count 0 2006.162.07:45:00.99#ibcon#wrote, iclass 28, count 0 2006.162.07:45:00.99#ibcon#about to read 3, iclass 28, count 0 2006.162.07:45:01.01#ibcon#read 3, iclass 28, count 0 2006.162.07:45:01.01#ibcon#about to read 4, iclass 28, count 0 2006.162.07:45:01.01#ibcon#read 4, iclass 28, count 0 2006.162.07:45:01.01#ibcon#about to read 5, iclass 28, count 0 2006.162.07:45:01.01#ibcon#read 5, iclass 28, count 0 2006.162.07:45:01.01#ibcon#about to read 6, iclass 28, count 0 2006.162.07:45:01.01#ibcon#read 6, iclass 28, count 0 2006.162.07:45:01.01#ibcon#end of sib2, iclass 28, count 0 2006.162.07:45:01.01#ibcon#*mode == 0, iclass 28, count 0 2006.162.07:45:01.01#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.162.07:45:01.01#ibcon#[25=USB\r\n] 2006.162.07:45:01.01#ibcon#*before write, iclass 28, count 0 2006.162.07:45:01.01#ibcon#enter sib2, iclass 28, count 0 2006.162.07:45:01.01#ibcon#flushed, iclass 28, count 0 2006.162.07:45:01.01#ibcon#about to write, iclass 28, count 0 2006.162.07:45:01.01#ibcon#wrote, iclass 28, count 0 2006.162.07:45:01.01#ibcon#about to read 3, iclass 28, count 0 2006.162.07:45:01.04#ibcon#read 3, iclass 28, count 0 2006.162.07:45:01.04#ibcon#about to read 4, iclass 28, count 0 2006.162.07:45:01.04#ibcon#read 4, iclass 28, count 0 2006.162.07:45:01.04#ibcon#about to read 5, iclass 28, count 0 2006.162.07:45:01.04#ibcon#read 5, iclass 28, count 0 2006.162.07:45:01.04#ibcon#about to read 6, iclass 28, count 0 2006.162.07:45:01.04#ibcon#read 6, iclass 28, count 0 2006.162.07:45:01.04#ibcon#end of sib2, iclass 28, count 0 2006.162.07:45:01.04#ibcon#*after write, iclass 28, count 0 2006.162.07:45:01.04#ibcon#*before return 0, iclass 28, count 0 2006.162.07:45:01.04#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.162.07:45:01.04#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.162.07:45:01.04#ibcon#about to clear, iclass 28 cls_cnt 0 2006.162.07:45:01.04#ibcon#cleared, iclass 28 cls_cnt 0 2006.162.07:45:01.04$vc4f8/valo=7,832.99 2006.162.07:45:01.04#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.162.07:45:01.04#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.162.07:45:01.04#ibcon#ireg 17 cls_cnt 0 2006.162.07:45:01.04#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.162.07:45:01.04#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.162.07:45:01.04#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.162.07:45:01.04#ibcon#enter wrdev, iclass 30, count 0 2006.162.07:45:01.04#ibcon#first serial, iclass 30, count 0 2006.162.07:45:01.04#ibcon#enter sib2, iclass 30, count 0 2006.162.07:45:01.04#ibcon#flushed, iclass 30, count 0 2006.162.07:45:01.04#ibcon#about to write, iclass 30, count 0 2006.162.07:45:01.04#ibcon#wrote, iclass 30, count 0 2006.162.07:45:01.04#ibcon#about to read 3, iclass 30, count 0 2006.162.07:45:01.06#ibcon#read 3, iclass 30, count 0 2006.162.07:45:01.06#ibcon#about to read 4, iclass 30, count 0 2006.162.07:45:01.06#ibcon#read 4, iclass 30, count 0 2006.162.07:45:01.06#ibcon#about to read 5, iclass 30, count 0 2006.162.07:45:01.06#ibcon#read 5, iclass 30, count 0 2006.162.07:45:01.06#ibcon#about to read 6, iclass 30, count 0 2006.162.07:45:01.06#ibcon#read 6, iclass 30, count 0 2006.162.07:45:01.06#ibcon#end of sib2, iclass 30, count 0 2006.162.07:45:01.06#ibcon#*mode == 0, iclass 30, count 0 2006.162.07:45:01.06#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.162.07:45:01.06#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.07:45:01.06#ibcon#*before write, iclass 30, count 0 2006.162.07:45:01.06#ibcon#enter sib2, iclass 30, count 0 2006.162.07:45:01.06#ibcon#flushed, iclass 30, count 0 2006.162.07:45:01.06#ibcon#about to write, iclass 30, count 0 2006.162.07:45:01.06#ibcon#wrote, iclass 30, count 0 2006.162.07:45:01.06#ibcon#about to read 3, iclass 30, count 0 2006.162.07:45:01.10#ibcon#read 3, iclass 30, count 0 2006.162.07:45:01.10#ibcon#about to read 4, iclass 30, count 0 2006.162.07:45:01.10#ibcon#read 4, iclass 30, count 0 2006.162.07:45:01.10#ibcon#about to read 5, iclass 30, count 0 2006.162.07:45:01.10#ibcon#read 5, iclass 30, count 0 2006.162.07:45:01.10#ibcon#about to read 6, iclass 30, count 0 2006.162.07:45:01.10#ibcon#read 6, iclass 30, count 0 2006.162.07:45:01.10#ibcon#end of sib2, iclass 30, count 0 2006.162.07:45:01.10#ibcon#*after write, iclass 30, count 0 2006.162.07:45:01.10#ibcon#*before return 0, iclass 30, count 0 2006.162.07:45:01.10#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.162.07:45:01.10#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.162.07:45:01.10#ibcon#about to clear, iclass 30 cls_cnt 0 2006.162.07:45:01.10#ibcon#cleared, iclass 30 cls_cnt 0 2006.162.07:45:01.10$vc4f8/va=7,6 2006.162.07:45:01.10#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.162.07:45:01.10#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.162.07:45:01.10#ibcon#ireg 11 cls_cnt 2 2006.162.07:45:01.10#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.162.07:45:01.16#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.162.07:45:01.16#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.162.07:45:01.16#ibcon#enter wrdev, iclass 32, count 2 2006.162.07:45:01.16#ibcon#first serial, iclass 32, count 2 2006.162.07:45:01.16#ibcon#enter sib2, iclass 32, count 2 2006.162.07:45:01.16#ibcon#flushed, iclass 32, count 2 2006.162.07:45:01.16#ibcon#about to write, iclass 32, count 2 2006.162.07:45:01.16#ibcon#wrote, iclass 32, count 2 2006.162.07:45:01.16#ibcon#about to read 3, iclass 32, count 2 2006.162.07:45:01.18#ibcon#read 3, iclass 32, count 2 2006.162.07:45:01.18#ibcon#about to read 4, iclass 32, count 2 2006.162.07:45:01.18#ibcon#read 4, iclass 32, count 2 2006.162.07:45:01.18#ibcon#about to read 5, iclass 32, count 2 2006.162.07:45:01.18#ibcon#read 5, iclass 32, count 2 2006.162.07:45:01.18#ibcon#about to read 6, iclass 32, count 2 2006.162.07:45:01.18#ibcon#read 6, iclass 32, count 2 2006.162.07:45:01.18#ibcon#end of sib2, iclass 32, count 2 2006.162.07:45:01.18#ibcon#*mode == 0, iclass 32, count 2 2006.162.07:45:01.18#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.162.07:45:01.18#ibcon#[25=AT07-06\r\n] 2006.162.07:45:01.18#ibcon#*before write, iclass 32, count 2 2006.162.07:45:01.18#ibcon#enter sib2, iclass 32, count 2 2006.162.07:45:01.18#ibcon#flushed, iclass 32, count 2 2006.162.07:45:01.18#ibcon#about to write, iclass 32, count 2 2006.162.07:45:01.18#ibcon#wrote, iclass 32, count 2 2006.162.07:45:01.18#ibcon#about to read 3, iclass 32, count 2 2006.162.07:45:01.21#ibcon#read 3, iclass 32, count 2 2006.162.07:45:01.21#ibcon#about to read 4, iclass 32, count 2 2006.162.07:45:01.21#ibcon#read 4, iclass 32, count 2 2006.162.07:45:01.21#ibcon#about to read 5, iclass 32, count 2 2006.162.07:45:01.21#ibcon#read 5, iclass 32, count 2 2006.162.07:45:01.21#ibcon#about to read 6, iclass 32, count 2 2006.162.07:45:01.21#ibcon#read 6, iclass 32, count 2 2006.162.07:45:01.21#ibcon#end of sib2, iclass 32, count 2 2006.162.07:45:01.21#ibcon#*after write, iclass 32, count 2 2006.162.07:45:01.21#ibcon#*before return 0, iclass 32, count 2 2006.162.07:45:01.21#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.162.07:45:01.21#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.162.07:45:01.21#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.162.07:45:01.21#ibcon#ireg 7 cls_cnt 0 2006.162.07:45:01.21#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.162.07:45:01.33#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.162.07:45:01.33#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.162.07:45:01.33#ibcon#enter wrdev, iclass 32, count 0 2006.162.07:45:01.33#ibcon#first serial, iclass 32, count 0 2006.162.07:45:01.33#ibcon#enter sib2, iclass 32, count 0 2006.162.07:45:01.33#ibcon#flushed, iclass 32, count 0 2006.162.07:45:01.33#ibcon#about to write, iclass 32, count 0 2006.162.07:45:01.33#ibcon#wrote, iclass 32, count 0 2006.162.07:45:01.33#ibcon#about to read 3, iclass 32, count 0 2006.162.07:45:01.35#ibcon#read 3, iclass 32, count 0 2006.162.07:45:01.35#ibcon#about to read 4, iclass 32, count 0 2006.162.07:45:01.35#ibcon#read 4, iclass 32, count 0 2006.162.07:45:01.35#ibcon#about to read 5, iclass 32, count 0 2006.162.07:45:01.35#ibcon#read 5, iclass 32, count 0 2006.162.07:45:01.35#ibcon#about to read 6, iclass 32, count 0 2006.162.07:45:01.35#ibcon#read 6, iclass 32, count 0 2006.162.07:45:01.35#ibcon#end of sib2, iclass 32, count 0 2006.162.07:45:01.35#ibcon#*mode == 0, iclass 32, count 0 2006.162.07:45:01.35#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.162.07:45:01.35#ibcon#[25=USB\r\n] 2006.162.07:45:01.35#ibcon#*before write, iclass 32, count 0 2006.162.07:45:01.35#ibcon#enter sib2, iclass 32, count 0 2006.162.07:45:01.35#ibcon#flushed, iclass 32, count 0 2006.162.07:45:01.35#ibcon#about to write, iclass 32, count 0 2006.162.07:45:01.35#ibcon#wrote, iclass 32, count 0 2006.162.07:45:01.35#ibcon#about to read 3, iclass 32, count 0 2006.162.07:45:01.38#ibcon#read 3, iclass 32, count 0 2006.162.07:45:01.38#ibcon#about to read 4, iclass 32, count 0 2006.162.07:45:01.38#ibcon#read 4, iclass 32, count 0 2006.162.07:45:01.38#ibcon#about to read 5, iclass 32, count 0 2006.162.07:45:01.38#ibcon#read 5, iclass 32, count 0 2006.162.07:45:01.38#ibcon#about to read 6, iclass 32, count 0 2006.162.07:45:01.38#ibcon#read 6, iclass 32, count 0 2006.162.07:45:01.38#ibcon#end of sib2, iclass 32, count 0 2006.162.07:45:01.38#ibcon#*after write, iclass 32, count 0 2006.162.07:45:01.38#ibcon#*before return 0, iclass 32, count 0 2006.162.07:45:01.38#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.162.07:45:01.38#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.162.07:45:01.38#ibcon#about to clear, iclass 32 cls_cnt 0 2006.162.07:45:01.38#ibcon#cleared, iclass 32 cls_cnt 0 2006.162.07:45:01.38$vc4f8/valo=8,852.99 2006.162.07:45:01.38#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.162.07:45:01.38#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.162.07:45:01.38#ibcon#ireg 17 cls_cnt 0 2006.162.07:45:01.38#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.162.07:45:01.38#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.162.07:45:01.38#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.162.07:45:01.38#ibcon#enter wrdev, iclass 34, count 0 2006.162.07:45:01.38#ibcon#first serial, iclass 34, count 0 2006.162.07:45:01.38#ibcon#enter sib2, iclass 34, count 0 2006.162.07:45:01.38#ibcon#flushed, iclass 34, count 0 2006.162.07:45:01.38#ibcon#about to write, iclass 34, count 0 2006.162.07:45:01.38#ibcon#wrote, iclass 34, count 0 2006.162.07:45:01.38#ibcon#about to read 3, iclass 34, count 0 2006.162.07:45:01.40#ibcon#read 3, iclass 34, count 0 2006.162.07:45:01.40#ibcon#about to read 4, iclass 34, count 0 2006.162.07:45:01.41#ibcon#read 4, iclass 34, count 0 2006.162.07:45:01.41#ibcon#about to read 5, iclass 34, count 0 2006.162.07:45:01.41#ibcon#read 5, iclass 34, count 0 2006.162.07:45:01.41#ibcon#about to read 6, iclass 34, count 0 2006.162.07:45:01.41#ibcon#read 6, iclass 34, count 0 2006.162.07:45:01.41#ibcon#end of sib2, iclass 34, count 0 2006.162.07:45:01.41#ibcon#*mode == 0, iclass 34, count 0 2006.162.07:45:01.41#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.162.07:45:01.41#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.07:45:01.41#ibcon#*before write, iclass 34, count 0 2006.162.07:45:01.41#ibcon#enter sib2, iclass 34, count 0 2006.162.07:45:01.41#ibcon#flushed, iclass 34, count 0 2006.162.07:45:01.41#ibcon#about to write, iclass 34, count 0 2006.162.07:45:01.41#ibcon#wrote, iclass 34, count 0 2006.162.07:45:01.41#ibcon#about to read 3, iclass 34, count 0 2006.162.07:45:01.45#ibcon#read 3, iclass 34, count 0 2006.162.07:45:01.45#ibcon#about to read 4, iclass 34, count 0 2006.162.07:45:01.45#ibcon#read 4, iclass 34, count 0 2006.162.07:45:01.45#ibcon#about to read 5, iclass 34, count 0 2006.162.07:45:01.45#ibcon#read 5, iclass 34, count 0 2006.162.07:45:01.45#ibcon#about to read 6, iclass 34, count 0 2006.162.07:45:01.45#ibcon#read 6, iclass 34, count 0 2006.162.07:45:01.45#ibcon#end of sib2, iclass 34, count 0 2006.162.07:45:01.45#ibcon#*after write, iclass 34, count 0 2006.162.07:45:01.45#ibcon#*before return 0, iclass 34, count 0 2006.162.07:45:01.45#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.162.07:45:01.45#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.162.07:45:01.45#ibcon#about to clear, iclass 34 cls_cnt 0 2006.162.07:45:01.45#ibcon#cleared, iclass 34 cls_cnt 0 2006.162.07:45:01.45$vc4f8/va=8,7 2006.162.07:45:01.45#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.162.07:45:01.45#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.162.07:45:01.45#ibcon#ireg 11 cls_cnt 2 2006.162.07:45:01.45#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.162.07:45:01.50#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.162.07:45:01.50#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.162.07:45:01.50#ibcon#enter wrdev, iclass 36, count 2 2006.162.07:45:01.50#ibcon#first serial, iclass 36, count 2 2006.162.07:45:01.50#ibcon#enter sib2, iclass 36, count 2 2006.162.07:45:01.50#ibcon#flushed, iclass 36, count 2 2006.162.07:45:01.50#ibcon#about to write, iclass 36, count 2 2006.162.07:45:01.50#ibcon#wrote, iclass 36, count 2 2006.162.07:45:01.50#ibcon#about to read 3, iclass 36, count 2 2006.162.07:45:01.52#ibcon#read 3, iclass 36, count 2 2006.162.07:45:01.52#ibcon#about to read 4, iclass 36, count 2 2006.162.07:45:01.52#ibcon#read 4, iclass 36, count 2 2006.162.07:45:01.52#ibcon#about to read 5, iclass 36, count 2 2006.162.07:45:01.52#ibcon#read 5, iclass 36, count 2 2006.162.07:45:01.52#ibcon#about to read 6, iclass 36, count 2 2006.162.07:45:01.52#ibcon#read 6, iclass 36, count 2 2006.162.07:45:01.52#ibcon#end of sib2, iclass 36, count 2 2006.162.07:45:01.52#ibcon#*mode == 0, iclass 36, count 2 2006.162.07:45:01.52#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.162.07:45:01.52#ibcon#[25=AT08-07\r\n] 2006.162.07:45:01.52#ibcon#*before write, iclass 36, count 2 2006.162.07:45:01.52#ibcon#enter sib2, iclass 36, count 2 2006.162.07:45:01.52#ibcon#flushed, iclass 36, count 2 2006.162.07:45:01.52#ibcon#about to write, iclass 36, count 2 2006.162.07:45:01.52#ibcon#wrote, iclass 36, count 2 2006.162.07:45:01.52#ibcon#about to read 3, iclass 36, count 2 2006.162.07:45:01.55#ibcon#read 3, iclass 36, count 2 2006.162.07:45:01.55#ibcon#about to read 4, iclass 36, count 2 2006.162.07:45:01.55#ibcon#read 4, iclass 36, count 2 2006.162.07:45:01.55#ibcon#about to read 5, iclass 36, count 2 2006.162.07:45:01.55#ibcon#read 5, iclass 36, count 2 2006.162.07:45:01.55#ibcon#about to read 6, iclass 36, count 2 2006.162.07:45:01.55#ibcon#read 6, iclass 36, count 2 2006.162.07:45:01.55#ibcon#end of sib2, iclass 36, count 2 2006.162.07:45:01.55#ibcon#*after write, iclass 36, count 2 2006.162.07:45:01.55#ibcon#*before return 0, iclass 36, count 2 2006.162.07:45:01.55#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.162.07:45:01.55#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.162.07:45:01.55#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.162.07:45:01.55#ibcon#ireg 7 cls_cnt 0 2006.162.07:45:01.55#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.162.07:45:01.67#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.162.07:45:01.67#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.162.07:45:01.67#ibcon#enter wrdev, iclass 36, count 0 2006.162.07:45:01.67#ibcon#first serial, iclass 36, count 0 2006.162.07:45:01.67#ibcon#enter sib2, iclass 36, count 0 2006.162.07:45:01.67#ibcon#flushed, iclass 36, count 0 2006.162.07:45:01.67#ibcon#about to write, iclass 36, count 0 2006.162.07:45:01.67#ibcon#wrote, iclass 36, count 0 2006.162.07:45:01.67#ibcon#about to read 3, iclass 36, count 0 2006.162.07:45:01.69#ibcon#read 3, iclass 36, count 0 2006.162.07:45:01.69#ibcon#about to read 4, iclass 36, count 0 2006.162.07:45:01.69#ibcon#read 4, iclass 36, count 0 2006.162.07:45:01.69#ibcon#about to read 5, iclass 36, count 0 2006.162.07:45:01.69#ibcon#read 5, iclass 36, count 0 2006.162.07:45:01.69#ibcon#about to read 6, iclass 36, count 0 2006.162.07:45:01.69#ibcon#read 6, iclass 36, count 0 2006.162.07:45:01.69#ibcon#end of sib2, iclass 36, count 0 2006.162.07:45:01.69#ibcon#*mode == 0, iclass 36, count 0 2006.162.07:45:01.69#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.162.07:45:01.69#ibcon#[25=USB\r\n] 2006.162.07:45:01.69#ibcon#*before write, iclass 36, count 0 2006.162.07:45:01.69#ibcon#enter sib2, iclass 36, count 0 2006.162.07:45:01.69#ibcon#flushed, iclass 36, count 0 2006.162.07:45:01.69#ibcon#about to write, iclass 36, count 0 2006.162.07:45:01.69#ibcon#wrote, iclass 36, count 0 2006.162.07:45:01.69#ibcon#about to read 3, iclass 36, count 0 2006.162.07:45:01.72#ibcon#read 3, iclass 36, count 0 2006.162.07:45:01.72#ibcon#about to read 4, iclass 36, count 0 2006.162.07:45:01.72#ibcon#read 4, iclass 36, count 0 2006.162.07:45:01.72#ibcon#about to read 5, iclass 36, count 0 2006.162.07:45:01.72#ibcon#read 5, iclass 36, count 0 2006.162.07:45:01.72#ibcon#about to read 6, iclass 36, count 0 2006.162.07:45:01.72#ibcon#read 6, iclass 36, count 0 2006.162.07:45:01.72#ibcon#end of sib2, iclass 36, count 0 2006.162.07:45:01.72#ibcon#*after write, iclass 36, count 0 2006.162.07:45:01.72#ibcon#*before return 0, iclass 36, count 0 2006.162.07:45:01.72#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.162.07:45:01.72#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.162.07:45:01.72#ibcon#about to clear, iclass 36 cls_cnt 0 2006.162.07:45:01.72#ibcon#cleared, iclass 36 cls_cnt 0 2006.162.07:45:01.72$vc4f8/vblo=1,632.99 2006.162.07:45:01.72#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.162.07:45:01.72#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.162.07:45:01.72#ibcon#ireg 17 cls_cnt 0 2006.162.07:45:01.72#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.162.07:45:01.72#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.162.07:45:01.72#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.162.07:45:01.72#ibcon#enter wrdev, iclass 38, count 0 2006.162.07:45:01.72#ibcon#first serial, iclass 38, count 0 2006.162.07:45:01.72#ibcon#enter sib2, iclass 38, count 0 2006.162.07:45:01.72#ibcon#flushed, iclass 38, count 0 2006.162.07:45:01.72#ibcon#about to write, iclass 38, count 0 2006.162.07:45:01.72#ibcon#wrote, iclass 38, count 0 2006.162.07:45:01.72#ibcon#about to read 3, iclass 38, count 0 2006.162.07:45:01.74#ibcon#read 3, iclass 38, count 0 2006.162.07:45:01.74#ibcon#about to read 4, iclass 38, count 0 2006.162.07:45:01.74#ibcon#read 4, iclass 38, count 0 2006.162.07:45:01.74#ibcon#about to read 5, iclass 38, count 0 2006.162.07:45:01.74#ibcon#read 5, iclass 38, count 0 2006.162.07:45:01.74#ibcon#about to read 6, iclass 38, count 0 2006.162.07:45:01.74#ibcon#read 6, iclass 38, count 0 2006.162.07:45:01.74#ibcon#end of sib2, iclass 38, count 0 2006.162.07:45:01.74#ibcon#*mode == 0, iclass 38, count 0 2006.162.07:45:01.74#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.162.07:45:01.74#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.07:45:01.74#ibcon#*before write, iclass 38, count 0 2006.162.07:45:01.74#ibcon#enter sib2, iclass 38, count 0 2006.162.07:45:01.74#ibcon#flushed, iclass 38, count 0 2006.162.07:45:01.74#ibcon#about to write, iclass 38, count 0 2006.162.07:45:01.74#ibcon#wrote, iclass 38, count 0 2006.162.07:45:01.74#ibcon#about to read 3, iclass 38, count 0 2006.162.07:45:01.78#ibcon#read 3, iclass 38, count 0 2006.162.07:45:01.78#ibcon#about to read 4, iclass 38, count 0 2006.162.07:45:01.78#ibcon#read 4, iclass 38, count 0 2006.162.07:45:01.78#ibcon#about to read 5, iclass 38, count 0 2006.162.07:45:01.78#ibcon#read 5, iclass 38, count 0 2006.162.07:45:01.78#ibcon#about to read 6, iclass 38, count 0 2006.162.07:45:01.78#ibcon#read 6, iclass 38, count 0 2006.162.07:45:01.78#ibcon#end of sib2, iclass 38, count 0 2006.162.07:45:01.78#ibcon#*after write, iclass 38, count 0 2006.162.07:45:01.78#ibcon#*before return 0, iclass 38, count 0 2006.162.07:45:01.78#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.162.07:45:01.78#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.162.07:45:01.78#ibcon#about to clear, iclass 38 cls_cnt 0 2006.162.07:45:01.78#ibcon#cleared, iclass 38 cls_cnt 0 2006.162.07:45:01.78$vc4f8/vb=1,4 2006.162.07:45:01.78#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.162.07:45:01.78#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.162.07:45:01.78#ibcon#ireg 11 cls_cnt 2 2006.162.07:45:01.78#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.162.07:45:01.78#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.162.07:45:01.78#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.162.07:45:01.78#ibcon#enter wrdev, iclass 40, count 2 2006.162.07:45:01.78#ibcon#first serial, iclass 40, count 2 2006.162.07:45:01.78#ibcon#enter sib2, iclass 40, count 2 2006.162.07:45:01.78#ibcon#flushed, iclass 40, count 2 2006.162.07:45:01.78#ibcon#about to write, iclass 40, count 2 2006.162.07:45:01.78#ibcon#wrote, iclass 40, count 2 2006.162.07:45:01.78#ibcon#about to read 3, iclass 40, count 2 2006.162.07:45:01.80#ibcon#read 3, iclass 40, count 2 2006.162.07:45:01.80#ibcon#about to read 4, iclass 40, count 2 2006.162.07:45:01.80#ibcon#read 4, iclass 40, count 2 2006.162.07:45:01.80#ibcon#about to read 5, iclass 40, count 2 2006.162.07:45:01.80#ibcon#read 5, iclass 40, count 2 2006.162.07:45:01.80#ibcon#about to read 6, iclass 40, count 2 2006.162.07:45:01.80#ibcon#read 6, iclass 40, count 2 2006.162.07:45:01.80#ibcon#end of sib2, iclass 40, count 2 2006.162.07:45:01.80#ibcon#*mode == 0, iclass 40, count 2 2006.162.07:45:01.80#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.162.07:45:01.80#ibcon#[27=AT01-04\r\n] 2006.162.07:45:01.80#ibcon#*before write, iclass 40, count 2 2006.162.07:45:01.80#ibcon#enter sib2, iclass 40, count 2 2006.162.07:45:01.80#ibcon#flushed, iclass 40, count 2 2006.162.07:45:01.80#ibcon#about to write, iclass 40, count 2 2006.162.07:45:01.80#ibcon#wrote, iclass 40, count 2 2006.162.07:45:01.80#ibcon#about to read 3, iclass 40, count 2 2006.162.07:45:01.83#ibcon#read 3, iclass 40, count 2 2006.162.07:45:01.83#ibcon#about to read 4, iclass 40, count 2 2006.162.07:45:01.83#ibcon#read 4, iclass 40, count 2 2006.162.07:45:01.83#ibcon#about to read 5, iclass 40, count 2 2006.162.07:45:01.83#ibcon#read 5, iclass 40, count 2 2006.162.07:45:01.83#ibcon#about to read 6, iclass 40, count 2 2006.162.07:45:01.83#ibcon#read 6, iclass 40, count 2 2006.162.07:45:01.83#ibcon#end of sib2, iclass 40, count 2 2006.162.07:45:01.83#ibcon#*after write, iclass 40, count 2 2006.162.07:45:01.83#ibcon#*before return 0, iclass 40, count 2 2006.162.07:45:01.83#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.162.07:45:01.83#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.162.07:45:01.83#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.162.07:45:01.83#ibcon#ireg 7 cls_cnt 0 2006.162.07:45:01.83#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.162.07:45:01.95#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.162.07:45:01.95#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.162.07:45:01.95#ibcon#enter wrdev, iclass 40, count 0 2006.162.07:45:01.95#ibcon#first serial, iclass 40, count 0 2006.162.07:45:01.95#ibcon#enter sib2, iclass 40, count 0 2006.162.07:45:01.95#ibcon#flushed, iclass 40, count 0 2006.162.07:45:01.95#ibcon#about to write, iclass 40, count 0 2006.162.07:45:01.95#ibcon#wrote, iclass 40, count 0 2006.162.07:45:01.95#ibcon#about to read 3, iclass 40, count 0 2006.162.07:45:01.97#ibcon#read 3, iclass 40, count 0 2006.162.07:45:01.97#ibcon#about to read 4, iclass 40, count 0 2006.162.07:45:01.97#ibcon#read 4, iclass 40, count 0 2006.162.07:45:01.97#ibcon#about to read 5, iclass 40, count 0 2006.162.07:45:01.97#ibcon#read 5, iclass 40, count 0 2006.162.07:45:01.97#ibcon#about to read 6, iclass 40, count 0 2006.162.07:45:01.97#ibcon#read 6, iclass 40, count 0 2006.162.07:45:01.97#ibcon#end of sib2, iclass 40, count 0 2006.162.07:45:01.97#ibcon#*mode == 0, iclass 40, count 0 2006.162.07:45:01.97#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.162.07:45:01.97#ibcon#[27=USB\r\n] 2006.162.07:45:01.97#ibcon#*before write, iclass 40, count 0 2006.162.07:45:01.97#ibcon#enter sib2, iclass 40, count 0 2006.162.07:45:01.97#ibcon#flushed, iclass 40, count 0 2006.162.07:45:01.97#ibcon#about to write, iclass 40, count 0 2006.162.07:45:01.97#ibcon#wrote, iclass 40, count 0 2006.162.07:45:01.97#ibcon#about to read 3, iclass 40, count 0 2006.162.07:45:02.00#ibcon#read 3, iclass 40, count 0 2006.162.07:45:02.00#ibcon#about to read 4, iclass 40, count 0 2006.162.07:45:02.00#ibcon#read 4, iclass 40, count 0 2006.162.07:45:02.00#ibcon#about to read 5, iclass 40, count 0 2006.162.07:45:02.00#ibcon#read 5, iclass 40, count 0 2006.162.07:45:02.00#ibcon#about to read 6, iclass 40, count 0 2006.162.07:45:02.00#ibcon#read 6, iclass 40, count 0 2006.162.07:45:02.00#ibcon#end of sib2, iclass 40, count 0 2006.162.07:45:02.00#ibcon#*after write, iclass 40, count 0 2006.162.07:45:02.00#ibcon#*before return 0, iclass 40, count 0 2006.162.07:45:02.00#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.162.07:45:02.00#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.162.07:45:02.00#ibcon#about to clear, iclass 40 cls_cnt 0 2006.162.07:45:02.00#ibcon#cleared, iclass 40 cls_cnt 0 2006.162.07:45:02.00$vc4f8/vblo=2,640.99 2006.162.07:45:02.00#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.162.07:45:02.00#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.162.07:45:02.00#ibcon#ireg 17 cls_cnt 0 2006.162.07:45:02.00#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.162.07:45:02.00#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.162.07:45:02.00#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.162.07:45:02.00#ibcon#enter wrdev, iclass 4, count 0 2006.162.07:45:02.00#ibcon#first serial, iclass 4, count 0 2006.162.07:45:02.00#ibcon#enter sib2, iclass 4, count 0 2006.162.07:45:02.00#ibcon#flushed, iclass 4, count 0 2006.162.07:45:02.00#ibcon#about to write, iclass 4, count 0 2006.162.07:45:02.00#ibcon#wrote, iclass 4, count 0 2006.162.07:45:02.00#ibcon#about to read 3, iclass 4, count 0 2006.162.07:45:02.02#ibcon#read 3, iclass 4, count 0 2006.162.07:45:02.02#ibcon#about to read 4, iclass 4, count 0 2006.162.07:45:02.02#ibcon#read 4, iclass 4, count 0 2006.162.07:45:02.02#ibcon#about to read 5, iclass 4, count 0 2006.162.07:45:02.02#ibcon#read 5, iclass 4, count 0 2006.162.07:45:02.02#ibcon#about to read 6, iclass 4, count 0 2006.162.07:45:02.02#ibcon#read 6, iclass 4, count 0 2006.162.07:45:02.02#ibcon#end of sib2, iclass 4, count 0 2006.162.07:45:02.02#ibcon#*mode == 0, iclass 4, count 0 2006.162.07:45:02.02#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.162.07:45:02.02#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.07:45:02.02#ibcon#*before write, iclass 4, count 0 2006.162.07:45:02.02#ibcon#enter sib2, iclass 4, count 0 2006.162.07:45:02.02#ibcon#flushed, iclass 4, count 0 2006.162.07:45:02.02#ibcon#about to write, iclass 4, count 0 2006.162.07:45:02.02#ibcon#wrote, iclass 4, count 0 2006.162.07:45:02.02#ibcon#about to read 3, iclass 4, count 0 2006.162.07:45:02.06#ibcon#read 3, iclass 4, count 0 2006.162.07:45:02.06#ibcon#about to read 4, iclass 4, count 0 2006.162.07:45:02.06#ibcon#read 4, iclass 4, count 0 2006.162.07:45:02.06#ibcon#about to read 5, iclass 4, count 0 2006.162.07:45:02.06#ibcon#read 5, iclass 4, count 0 2006.162.07:45:02.06#ibcon#about to read 6, iclass 4, count 0 2006.162.07:45:02.06#ibcon#read 6, iclass 4, count 0 2006.162.07:45:02.06#ibcon#end of sib2, iclass 4, count 0 2006.162.07:45:02.06#ibcon#*after write, iclass 4, count 0 2006.162.07:45:02.06#ibcon#*before return 0, iclass 4, count 0 2006.162.07:45:02.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.162.07:45:02.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.162.07:45:02.06#ibcon#about to clear, iclass 4 cls_cnt 0 2006.162.07:45:02.06#ibcon#cleared, iclass 4 cls_cnt 0 2006.162.07:45:02.06$vc4f8/vb=2,4 2006.162.07:45:02.06#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.162.07:45:02.06#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.162.07:45:02.06#ibcon#ireg 11 cls_cnt 2 2006.162.07:45:02.06#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.162.07:45:02.12#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.162.07:45:02.12#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.162.07:45:02.12#ibcon#enter wrdev, iclass 6, count 2 2006.162.07:45:02.12#ibcon#first serial, iclass 6, count 2 2006.162.07:45:02.12#ibcon#enter sib2, iclass 6, count 2 2006.162.07:45:02.12#ibcon#flushed, iclass 6, count 2 2006.162.07:45:02.12#ibcon#about to write, iclass 6, count 2 2006.162.07:45:02.12#ibcon#wrote, iclass 6, count 2 2006.162.07:45:02.12#ibcon#about to read 3, iclass 6, count 2 2006.162.07:45:02.14#ibcon#read 3, iclass 6, count 2 2006.162.07:45:02.14#ibcon#about to read 4, iclass 6, count 2 2006.162.07:45:02.14#ibcon#read 4, iclass 6, count 2 2006.162.07:45:02.14#ibcon#about to read 5, iclass 6, count 2 2006.162.07:45:02.14#ibcon#read 5, iclass 6, count 2 2006.162.07:45:02.14#ibcon#about to read 6, iclass 6, count 2 2006.162.07:45:02.14#ibcon#read 6, iclass 6, count 2 2006.162.07:45:02.14#ibcon#end of sib2, iclass 6, count 2 2006.162.07:45:02.14#ibcon#*mode == 0, iclass 6, count 2 2006.162.07:45:02.14#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.162.07:45:02.14#ibcon#[27=AT02-04\r\n] 2006.162.07:45:02.14#ibcon#*before write, iclass 6, count 2 2006.162.07:45:02.14#ibcon#enter sib2, iclass 6, count 2 2006.162.07:45:02.14#ibcon#flushed, iclass 6, count 2 2006.162.07:45:02.14#ibcon#about to write, iclass 6, count 2 2006.162.07:45:02.14#ibcon#wrote, iclass 6, count 2 2006.162.07:45:02.14#ibcon#about to read 3, iclass 6, count 2 2006.162.07:45:02.17#ibcon#read 3, iclass 6, count 2 2006.162.07:45:02.17#ibcon#about to read 4, iclass 6, count 2 2006.162.07:45:02.17#ibcon#read 4, iclass 6, count 2 2006.162.07:45:02.17#ibcon#about to read 5, iclass 6, count 2 2006.162.07:45:02.17#ibcon#read 5, iclass 6, count 2 2006.162.07:45:02.17#ibcon#about to read 6, iclass 6, count 2 2006.162.07:45:02.17#ibcon#read 6, iclass 6, count 2 2006.162.07:45:02.17#ibcon#end of sib2, iclass 6, count 2 2006.162.07:45:02.17#ibcon#*after write, iclass 6, count 2 2006.162.07:45:02.17#ibcon#*before return 0, iclass 6, count 2 2006.162.07:45:02.17#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.162.07:45:02.17#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.162.07:45:02.17#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.162.07:45:02.17#ibcon#ireg 7 cls_cnt 0 2006.162.07:45:02.17#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.162.07:45:02.29#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.162.07:45:02.29#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.162.07:45:02.29#ibcon#enter wrdev, iclass 6, count 0 2006.162.07:45:02.29#ibcon#first serial, iclass 6, count 0 2006.162.07:45:02.29#ibcon#enter sib2, iclass 6, count 0 2006.162.07:45:02.29#ibcon#flushed, iclass 6, count 0 2006.162.07:45:02.29#ibcon#about to write, iclass 6, count 0 2006.162.07:45:02.29#ibcon#wrote, iclass 6, count 0 2006.162.07:45:02.29#ibcon#about to read 3, iclass 6, count 0 2006.162.07:45:02.31#ibcon#read 3, iclass 6, count 0 2006.162.07:45:02.31#ibcon#about to read 4, iclass 6, count 0 2006.162.07:45:02.31#ibcon#read 4, iclass 6, count 0 2006.162.07:45:02.31#ibcon#about to read 5, iclass 6, count 0 2006.162.07:45:02.31#ibcon#read 5, iclass 6, count 0 2006.162.07:45:02.31#ibcon#about to read 6, iclass 6, count 0 2006.162.07:45:02.31#ibcon#read 6, iclass 6, count 0 2006.162.07:45:02.31#ibcon#end of sib2, iclass 6, count 0 2006.162.07:45:02.31#ibcon#*mode == 0, iclass 6, count 0 2006.162.07:45:02.31#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.162.07:45:02.31#ibcon#[27=USB\r\n] 2006.162.07:45:02.31#ibcon#*before write, iclass 6, count 0 2006.162.07:45:02.31#ibcon#enter sib2, iclass 6, count 0 2006.162.07:45:02.31#ibcon#flushed, iclass 6, count 0 2006.162.07:45:02.31#ibcon#about to write, iclass 6, count 0 2006.162.07:45:02.31#ibcon#wrote, iclass 6, count 0 2006.162.07:45:02.31#ibcon#about to read 3, iclass 6, count 0 2006.162.07:45:02.34#ibcon#read 3, iclass 6, count 0 2006.162.07:45:02.34#ibcon#about to read 4, iclass 6, count 0 2006.162.07:45:02.34#ibcon#read 4, iclass 6, count 0 2006.162.07:45:02.34#ibcon#about to read 5, iclass 6, count 0 2006.162.07:45:02.34#ibcon#read 5, iclass 6, count 0 2006.162.07:45:02.34#ibcon#about to read 6, iclass 6, count 0 2006.162.07:45:02.34#ibcon#read 6, iclass 6, count 0 2006.162.07:45:02.34#ibcon#end of sib2, iclass 6, count 0 2006.162.07:45:02.34#ibcon#*after write, iclass 6, count 0 2006.162.07:45:02.34#ibcon#*before return 0, iclass 6, count 0 2006.162.07:45:02.34#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.162.07:45:02.34#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.162.07:45:02.34#ibcon#about to clear, iclass 6 cls_cnt 0 2006.162.07:45:02.34#ibcon#cleared, iclass 6 cls_cnt 0 2006.162.07:45:02.34$vc4f8/vblo=3,656.99 2006.162.07:45:02.34#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.162.07:45:02.34#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.162.07:45:02.34#ibcon#ireg 17 cls_cnt 0 2006.162.07:45:02.34#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.162.07:45:02.34#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.162.07:45:02.34#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.162.07:45:02.34#ibcon#enter wrdev, iclass 10, count 0 2006.162.07:45:02.34#ibcon#first serial, iclass 10, count 0 2006.162.07:45:02.34#ibcon#enter sib2, iclass 10, count 0 2006.162.07:45:02.34#ibcon#flushed, iclass 10, count 0 2006.162.07:45:02.34#ibcon#about to write, iclass 10, count 0 2006.162.07:45:02.34#ibcon#wrote, iclass 10, count 0 2006.162.07:45:02.34#ibcon#about to read 3, iclass 10, count 0 2006.162.07:45:02.36#ibcon#read 3, iclass 10, count 0 2006.162.07:45:02.36#ibcon#about to read 4, iclass 10, count 0 2006.162.07:45:02.36#ibcon#read 4, iclass 10, count 0 2006.162.07:45:02.36#ibcon#about to read 5, iclass 10, count 0 2006.162.07:45:02.36#ibcon#read 5, iclass 10, count 0 2006.162.07:45:02.36#ibcon#about to read 6, iclass 10, count 0 2006.162.07:45:02.36#ibcon#read 6, iclass 10, count 0 2006.162.07:45:02.36#ibcon#end of sib2, iclass 10, count 0 2006.162.07:45:02.36#ibcon#*mode == 0, iclass 10, count 0 2006.162.07:45:02.36#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.162.07:45:02.36#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.07:45:02.36#ibcon#*before write, iclass 10, count 0 2006.162.07:45:02.36#ibcon#enter sib2, iclass 10, count 0 2006.162.07:45:02.36#ibcon#flushed, iclass 10, count 0 2006.162.07:45:02.36#ibcon#about to write, iclass 10, count 0 2006.162.07:45:02.36#ibcon#wrote, iclass 10, count 0 2006.162.07:45:02.36#ibcon#about to read 3, iclass 10, count 0 2006.162.07:45:02.40#ibcon#read 3, iclass 10, count 0 2006.162.07:45:02.40#ibcon#about to read 4, iclass 10, count 0 2006.162.07:45:02.40#ibcon#read 4, iclass 10, count 0 2006.162.07:45:02.40#ibcon#about to read 5, iclass 10, count 0 2006.162.07:45:02.40#ibcon#read 5, iclass 10, count 0 2006.162.07:45:02.40#ibcon#about to read 6, iclass 10, count 0 2006.162.07:45:02.40#ibcon#read 6, iclass 10, count 0 2006.162.07:45:02.40#ibcon#end of sib2, iclass 10, count 0 2006.162.07:45:02.40#ibcon#*after write, iclass 10, count 0 2006.162.07:45:02.40#ibcon#*before return 0, iclass 10, count 0 2006.162.07:45:02.40#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.162.07:45:02.40#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.162.07:45:02.40#ibcon#about to clear, iclass 10 cls_cnt 0 2006.162.07:45:02.40#ibcon#cleared, iclass 10 cls_cnt 0 2006.162.07:45:02.40$vc4f8/vb=3,4 2006.162.07:45:02.40#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.162.07:45:02.40#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.162.07:45:02.40#ibcon#ireg 11 cls_cnt 2 2006.162.07:45:02.40#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.162.07:45:02.46#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.162.07:45:02.46#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.162.07:45:02.46#ibcon#enter wrdev, iclass 12, count 2 2006.162.07:45:02.46#ibcon#first serial, iclass 12, count 2 2006.162.07:45:02.46#ibcon#enter sib2, iclass 12, count 2 2006.162.07:45:02.46#ibcon#flushed, iclass 12, count 2 2006.162.07:45:02.46#ibcon#about to write, iclass 12, count 2 2006.162.07:45:02.46#ibcon#wrote, iclass 12, count 2 2006.162.07:45:02.46#ibcon#about to read 3, iclass 12, count 2 2006.162.07:45:02.48#ibcon#read 3, iclass 12, count 2 2006.162.07:45:02.48#ibcon#about to read 4, iclass 12, count 2 2006.162.07:45:02.48#ibcon#read 4, iclass 12, count 2 2006.162.07:45:02.48#ibcon#about to read 5, iclass 12, count 2 2006.162.07:45:02.48#ibcon#read 5, iclass 12, count 2 2006.162.07:45:02.48#ibcon#about to read 6, iclass 12, count 2 2006.162.07:45:02.48#ibcon#read 6, iclass 12, count 2 2006.162.07:45:02.48#ibcon#end of sib2, iclass 12, count 2 2006.162.07:45:02.48#ibcon#*mode == 0, iclass 12, count 2 2006.162.07:45:02.48#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.162.07:45:02.48#ibcon#[27=AT03-04\r\n] 2006.162.07:45:02.48#ibcon#*before write, iclass 12, count 2 2006.162.07:45:02.48#ibcon#enter sib2, iclass 12, count 2 2006.162.07:45:02.48#ibcon#flushed, iclass 12, count 2 2006.162.07:45:02.48#ibcon#about to write, iclass 12, count 2 2006.162.07:45:02.48#ibcon#wrote, iclass 12, count 2 2006.162.07:45:02.48#ibcon#about to read 3, iclass 12, count 2 2006.162.07:45:02.51#ibcon#read 3, iclass 12, count 2 2006.162.07:45:02.51#ibcon#about to read 4, iclass 12, count 2 2006.162.07:45:02.51#ibcon#read 4, iclass 12, count 2 2006.162.07:45:02.51#ibcon#about to read 5, iclass 12, count 2 2006.162.07:45:02.51#ibcon#read 5, iclass 12, count 2 2006.162.07:45:02.51#ibcon#about to read 6, iclass 12, count 2 2006.162.07:45:02.51#ibcon#read 6, iclass 12, count 2 2006.162.07:45:02.51#ibcon#end of sib2, iclass 12, count 2 2006.162.07:45:02.51#ibcon#*after write, iclass 12, count 2 2006.162.07:45:02.51#ibcon#*before return 0, iclass 12, count 2 2006.162.07:45:02.51#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.162.07:45:02.51#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.162.07:45:02.51#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.162.07:45:02.51#ibcon#ireg 7 cls_cnt 0 2006.162.07:45:02.51#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.162.07:45:02.59#abcon#<5=/03 1.4 3.0 17.891001007.2\r\n> 2006.162.07:45:02.61#abcon#{5=INTERFACE CLEAR} 2006.162.07:45:02.63#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.162.07:45:02.63#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.162.07:45:02.63#ibcon#enter wrdev, iclass 12, count 0 2006.162.07:45:02.63#ibcon#first serial, iclass 12, count 0 2006.162.07:45:02.63#ibcon#enter sib2, iclass 12, count 0 2006.162.07:45:02.63#ibcon#flushed, iclass 12, count 0 2006.162.07:45:02.63#ibcon#about to write, iclass 12, count 0 2006.162.07:45:02.63#ibcon#wrote, iclass 12, count 0 2006.162.07:45:02.63#ibcon#about to read 3, iclass 12, count 0 2006.162.07:45:02.65#ibcon#read 3, iclass 12, count 0 2006.162.07:45:02.65#ibcon#about to read 4, iclass 12, count 0 2006.162.07:45:02.65#ibcon#read 4, iclass 12, count 0 2006.162.07:45:02.65#ibcon#about to read 5, iclass 12, count 0 2006.162.07:45:02.65#ibcon#read 5, iclass 12, count 0 2006.162.07:45:02.65#ibcon#about to read 6, iclass 12, count 0 2006.162.07:45:02.65#ibcon#read 6, iclass 12, count 0 2006.162.07:45:02.65#ibcon#end of sib2, iclass 12, count 0 2006.162.07:45:02.65#ibcon#*mode == 0, iclass 12, count 0 2006.162.07:45:02.65#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.162.07:45:02.65#ibcon#[27=USB\r\n] 2006.162.07:45:02.65#ibcon#*before write, iclass 12, count 0 2006.162.07:45:02.65#ibcon#enter sib2, iclass 12, count 0 2006.162.07:45:02.65#ibcon#flushed, iclass 12, count 0 2006.162.07:45:02.65#ibcon#about to write, iclass 12, count 0 2006.162.07:45:02.65#ibcon#wrote, iclass 12, count 0 2006.162.07:45:02.65#ibcon#about to read 3, iclass 12, count 0 2006.162.07:45:02.67#abcon#[5=S1D000X0/0*\r\n] 2006.162.07:45:02.68#ibcon#read 3, iclass 12, count 0 2006.162.07:45:02.68#ibcon#about to read 4, iclass 12, count 0 2006.162.07:45:02.68#ibcon#read 4, iclass 12, count 0 2006.162.07:45:02.68#ibcon#about to read 5, iclass 12, count 0 2006.162.07:45:02.68#ibcon#read 5, iclass 12, count 0 2006.162.07:45:02.68#ibcon#about to read 6, iclass 12, count 0 2006.162.07:45:02.68#ibcon#read 6, iclass 12, count 0 2006.162.07:45:02.68#ibcon#end of sib2, iclass 12, count 0 2006.162.07:45:02.68#ibcon#*after write, iclass 12, count 0 2006.162.07:45:02.68#ibcon#*before return 0, iclass 12, count 0 2006.162.07:45:02.68#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.162.07:45:02.68#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.162.07:45:02.68#ibcon#about to clear, iclass 12 cls_cnt 0 2006.162.07:45:02.68#ibcon#cleared, iclass 12 cls_cnt 0 2006.162.07:45:02.68$vc4f8/vblo=4,712.99 2006.162.07:45:02.68#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.162.07:45:02.68#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.162.07:45:02.68#ibcon#ireg 17 cls_cnt 0 2006.162.07:45:02.68#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:45:02.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:45:02.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:45:02.68#ibcon#enter wrdev, iclass 18, count 0 2006.162.07:45:02.68#ibcon#first serial, iclass 18, count 0 2006.162.07:45:02.68#ibcon#enter sib2, iclass 18, count 0 2006.162.07:45:02.68#ibcon#flushed, iclass 18, count 0 2006.162.07:45:02.68#ibcon#about to write, iclass 18, count 0 2006.162.07:45:02.68#ibcon#wrote, iclass 18, count 0 2006.162.07:45:02.68#ibcon#about to read 3, iclass 18, count 0 2006.162.07:45:02.70#ibcon#read 3, iclass 18, count 0 2006.162.07:45:02.70#ibcon#about to read 4, iclass 18, count 0 2006.162.07:45:02.70#ibcon#read 4, iclass 18, count 0 2006.162.07:45:02.70#ibcon#about to read 5, iclass 18, count 0 2006.162.07:45:02.70#ibcon#read 5, iclass 18, count 0 2006.162.07:45:02.70#ibcon#about to read 6, iclass 18, count 0 2006.162.07:45:02.70#ibcon#read 6, iclass 18, count 0 2006.162.07:45:02.70#ibcon#end of sib2, iclass 18, count 0 2006.162.07:45:02.70#ibcon#*mode == 0, iclass 18, count 0 2006.162.07:45:02.70#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.162.07:45:02.70#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.07:45:02.70#ibcon#*before write, iclass 18, count 0 2006.162.07:45:02.70#ibcon#enter sib2, iclass 18, count 0 2006.162.07:45:02.70#ibcon#flushed, iclass 18, count 0 2006.162.07:45:02.70#ibcon#about to write, iclass 18, count 0 2006.162.07:45:02.70#ibcon#wrote, iclass 18, count 0 2006.162.07:45:02.70#ibcon#about to read 3, iclass 18, count 0 2006.162.07:45:02.74#ibcon#read 3, iclass 18, count 0 2006.162.07:45:02.74#ibcon#about to read 4, iclass 18, count 0 2006.162.07:45:02.74#ibcon#read 4, iclass 18, count 0 2006.162.07:45:02.74#ibcon#about to read 5, iclass 18, count 0 2006.162.07:45:02.74#ibcon#read 5, iclass 18, count 0 2006.162.07:45:02.74#ibcon#about to read 6, iclass 18, count 0 2006.162.07:45:02.74#ibcon#read 6, iclass 18, count 0 2006.162.07:45:02.74#ibcon#end of sib2, iclass 18, count 0 2006.162.07:45:02.74#ibcon#*after write, iclass 18, count 0 2006.162.07:45:02.74#ibcon#*before return 0, iclass 18, count 0 2006.162.07:45:02.74#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:45:02.74#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:45:02.74#ibcon#about to clear, iclass 18 cls_cnt 0 2006.162.07:45:02.74#ibcon#cleared, iclass 18 cls_cnt 0 2006.162.07:45:02.74$vc4f8/vb=4,4 2006.162.07:45:02.74#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.162.07:45:02.74#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.162.07:45:02.74#ibcon#ireg 11 cls_cnt 2 2006.162.07:45:02.74#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:45:02.80#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:45:02.80#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:45:02.80#ibcon#enter wrdev, iclass 20, count 2 2006.162.07:45:02.80#ibcon#first serial, iclass 20, count 2 2006.162.07:45:02.80#ibcon#enter sib2, iclass 20, count 2 2006.162.07:45:02.80#ibcon#flushed, iclass 20, count 2 2006.162.07:45:02.80#ibcon#about to write, iclass 20, count 2 2006.162.07:45:02.80#ibcon#wrote, iclass 20, count 2 2006.162.07:45:02.80#ibcon#about to read 3, iclass 20, count 2 2006.162.07:45:02.82#ibcon#read 3, iclass 20, count 2 2006.162.07:45:02.82#ibcon#about to read 4, iclass 20, count 2 2006.162.07:45:02.82#ibcon#read 4, iclass 20, count 2 2006.162.07:45:02.82#ibcon#about to read 5, iclass 20, count 2 2006.162.07:45:02.82#ibcon#read 5, iclass 20, count 2 2006.162.07:45:02.82#ibcon#about to read 6, iclass 20, count 2 2006.162.07:45:02.82#ibcon#read 6, iclass 20, count 2 2006.162.07:45:02.82#ibcon#end of sib2, iclass 20, count 2 2006.162.07:45:02.82#ibcon#*mode == 0, iclass 20, count 2 2006.162.07:45:02.82#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.162.07:45:02.82#ibcon#[27=AT04-04\r\n] 2006.162.07:45:02.82#ibcon#*before write, iclass 20, count 2 2006.162.07:45:02.82#ibcon#enter sib2, iclass 20, count 2 2006.162.07:45:02.82#ibcon#flushed, iclass 20, count 2 2006.162.07:45:02.82#ibcon#about to write, iclass 20, count 2 2006.162.07:45:02.82#ibcon#wrote, iclass 20, count 2 2006.162.07:45:02.82#ibcon#about to read 3, iclass 20, count 2 2006.162.07:45:02.85#ibcon#read 3, iclass 20, count 2 2006.162.07:45:02.85#ibcon#about to read 4, iclass 20, count 2 2006.162.07:45:02.85#ibcon#read 4, iclass 20, count 2 2006.162.07:45:02.85#ibcon#about to read 5, iclass 20, count 2 2006.162.07:45:02.85#ibcon#read 5, iclass 20, count 2 2006.162.07:45:02.85#ibcon#about to read 6, iclass 20, count 2 2006.162.07:45:02.85#ibcon#read 6, iclass 20, count 2 2006.162.07:45:02.85#ibcon#end of sib2, iclass 20, count 2 2006.162.07:45:02.85#ibcon#*after write, iclass 20, count 2 2006.162.07:45:02.85#ibcon#*before return 0, iclass 20, count 2 2006.162.07:45:02.85#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:45:02.85#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:45:02.85#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.162.07:45:02.85#ibcon#ireg 7 cls_cnt 0 2006.162.07:45:02.85#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:45:02.97#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:45:02.97#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:45:02.97#ibcon#enter wrdev, iclass 20, count 0 2006.162.07:45:02.97#ibcon#first serial, iclass 20, count 0 2006.162.07:45:02.97#ibcon#enter sib2, iclass 20, count 0 2006.162.07:45:02.97#ibcon#flushed, iclass 20, count 0 2006.162.07:45:02.97#ibcon#about to write, iclass 20, count 0 2006.162.07:45:02.97#ibcon#wrote, iclass 20, count 0 2006.162.07:45:02.97#ibcon#about to read 3, iclass 20, count 0 2006.162.07:45:02.99#ibcon#read 3, iclass 20, count 0 2006.162.07:45:02.99#ibcon#about to read 4, iclass 20, count 0 2006.162.07:45:02.99#ibcon#read 4, iclass 20, count 0 2006.162.07:45:02.99#ibcon#about to read 5, iclass 20, count 0 2006.162.07:45:02.99#ibcon#read 5, iclass 20, count 0 2006.162.07:45:02.99#ibcon#about to read 6, iclass 20, count 0 2006.162.07:45:02.99#ibcon#read 6, iclass 20, count 0 2006.162.07:45:02.99#ibcon#end of sib2, iclass 20, count 0 2006.162.07:45:02.99#ibcon#*mode == 0, iclass 20, count 0 2006.162.07:45:02.99#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.07:45:02.99#ibcon#[27=USB\r\n] 2006.162.07:45:02.99#ibcon#*before write, iclass 20, count 0 2006.162.07:45:02.99#ibcon#enter sib2, iclass 20, count 0 2006.162.07:45:02.99#ibcon#flushed, iclass 20, count 0 2006.162.07:45:02.99#ibcon#about to write, iclass 20, count 0 2006.162.07:45:02.99#ibcon#wrote, iclass 20, count 0 2006.162.07:45:02.99#ibcon#about to read 3, iclass 20, count 0 2006.162.07:45:03.02#ibcon#read 3, iclass 20, count 0 2006.162.07:45:03.02#ibcon#about to read 4, iclass 20, count 0 2006.162.07:45:03.02#ibcon#read 4, iclass 20, count 0 2006.162.07:45:03.02#ibcon#about to read 5, iclass 20, count 0 2006.162.07:45:03.02#ibcon#read 5, iclass 20, count 0 2006.162.07:45:03.02#ibcon#about to read 6, iclass 20, count 0 2006.162.07:45:03.02#ibcon#read 6, iclass 20, count 0 2006.162.07:45:03.02#ibcon#end of sib2, iclass 20, count 0 2006.162.07:45:03.02#ibcon#*after write, iclass 20, count 0 2006.162.07:45:03.02#ibcon#*before return 0, iclass 20, count 0 2006.162.07:45:03.02#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:45:03.02#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:45:03.02#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.07:45:03.02#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.07:45:03.02$vc4f8/vblo=5,744.99 2006.162.07:45:03.02#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.162.07:45:03.02#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.162.07:45:03.02#ibcon#ireg 17 cls_cnt 0 2006.162.07:45:03.02#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:45:03.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:45:03.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:45:03.02#ibcon#enter wrdev, iclass 22, count 0 2006.162.07:45:03.02#ibcon#first serial, iclass 22, count 0 2006.162.07:45:03.02#ibcon#enter sib2, iclass 22, count 0 2006.162.07:45:03.02#ibcon#flushed, iclass 22, count 0 2006.162.07:45:03.02#ibcon#about to write, iclass 22, count 0 2006.162.07:45:03.02#ibcon#wrote, iclass 22, count 0 2006.162.07:45:03.02#ibcon#about to read 3, iclass 22, count 0 2006.162.07:45:03.04#ibcon#read 3, iclass 22, count 0 2006.162.07:45:03.04#ibcon#about to read 4, iclass 22, count 0 2006.162.07:45:03.04#ibcon#read 4, iclass 22, count 0 2006.162.07:45:03.04#ibcon#about to read 5, iclass 22, count 0 2006.162.07:45:03.04#ibcon#read 5, iclass 22, count 0 2006.162.07:45:03.04#ibcon#about to read 6, iclass 22, count 0 2006.162.07:45:03.04#ibcon#read 6, iclass 22, count 0 2006.162.07:45:03.04#ibcon#end of sib2, iclass 22, count 0 2006.162.07:45:03.04#ibcon#*mode == 0, iclass 22, count 0 2006.162.07:45:03.04#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.07:45:03.04#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.07:45:03.04#ibcon#*before write, iclass 22, count 0 2006.162.07:45:03.04#ibcon#enter sib2, iclass 22, count 0 2006.162.07:45:03.04#ibcon#flushed, iclass 22, count 0 2006.162.07:45:03.04#ibcon#about to write, iclass 22, count 0 2006.162.07:45:03.04#ibcon#wrote, iclass 22, count 0 2006.162.07:45:03.04#ibcon#about to read 3, iclass 22, count 0 2006.162.07:45:03.08#ibcon#read 3, iclass 22, count 0 2006.162.07:45:03.08#ibcon#about to read 4, iclass 22, count 0 2006.162.07:45:03.08#ibcon#read 4, iclass 22, count 0 2006.162.07:45:03.08#ibcon#about to read 5, iclass 22, count 0 2006.162.07:45:03.08#ibcon#read 5, iclass 22, count 0 2006.162.07:45:03.08#ibcon#about to read 6, iclass 22, count 0 2006.162.07:45:03.08#ibcon#read 6, iclass 22, count 0 2006.162.07:45:03.08#ibcon#end of sib2, iclass 22, count 0 2006.162.07:45:03.08#ibcon#*after write, iclass 22, count 0 2006.162.07:45:03.08#ibcon#*before return 0, iclass 22, count 0 2006.162.07:45:03.08#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:45:03.08#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:45:03.08#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.07:45:03.08#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.07:45:03.08$vc4f8/vb=5,4 2006.162.07:45:03.08#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.162.07:45:03.08#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.162.07:45:03.08#ibcon#ireg 11 cls_cnt 2 2006.162.07:45:03.08#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:45:03.14#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:45:03.14#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:45:03.14#ibcon#enter wrdev, iclass 24, count 2 2006.162.07:45:03.14#ibcon#first serial, iclass 24, count 2 2006.162.07:45:03.14#ibcon#enter sib2, iclass 24, count 2 2006.162.07:45:03.14#ibcon#flushed, iclass 24, count 2 2006.162.07:45:03.14#ibcon#about to write, iclass 24, count 2 2006.162.07:45:03.14#ibcon#wrote, iclass 24, count 2 2006.162.07:45:03.14#ibcon#about to read 3, iclass 24, count 2 2006.162.07:45:03.16#ibcon#read 3, iclass 24, count 2 2006.162.07:45:03.16#ibcon#about to read 4, iclass 24, count 2 2006.162.07:45:03.16#ibcon#read 4, iclass 24, count 2 2006.162.07:45:03.16#ibcon#about to read 5, iclass 24, count 2 2006.162.07:45:03.16#ibcon#read 5, iclass 24, count 2 2006.162.07:45:03.16#ibcon#about to read 6, iclass 24, count 2 2006.162.07:45:03.16#ibcon#read 6, iclass 24, count 2 2006.162.07:45:03.16#ibcon#end of sib2, iclass 24, count 2 2006.162.07:45:03.16#ibcon#*mode == 0, iclass 24, count 2 2006.162.07:45:03.16#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.162.07:45:03.16#ibcon#[27=AT05-04\r\n] 2006.162.07:45:03.16#ibcon#*before write, iclass 24, count 2 2006.162.07:45:03.16#ibcon#enter sib2, iclass 24, count 2 2006.162.07:45:03.16#ibcon#flushed, iclass 24, count 2 2006.162.07:45:03.16#ibcon#about to write, iclass 24, count 2 2006.162.07:45:03.16#ibcon#wrote, iclass 24, count 2 2006.162.07:45:03.16#ibcon#about to read 3, iclass 24, count 2 2006.162.07:45:03.19#ibcon#read 3, iclass 24, count 2 2006.162.07:45:03.19#ibcon#about to read 4, iclass 24, count 2 2006.162.07:45:03.19#ibcon#read 4, iclass 24, count 2 2006.162.07:45:03.19#ibcon#about to read 5, iclass 24, count 2 2006.162.07:45:03.19#ibcon#read 5, iclass 24, count 2 2006.162.07:45:03.19#ibcon#about to read 6, iclass 24, count 2 2006.162.07:45:03.19#ibcon#read 6, iclass 24, count 2 2006.162.07:45:03.19#ibcon#end of sib2, iclass 24, count 2 2006.162.07:45:03.19#ibcon#*after write, iclass 24, count 2 2006.162.07:45:03.19#ibcon#*before return 0, iclass 24, count 2 2006.162.07:45:03.19#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:45:03.19#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:45:03.19#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.162.07:45:03.19#ibcon#ireg 7 cls_cnt 0 2006.162.07:45:03.19#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:45:03.31#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:45:03.31#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:45:03.31#ibcon#enter wrdev, iclass 24, count 0 2006.162.07:45:03.31#ibcon#first serial, iclass 24, count 0 2006.162.07:45:03.31#ibcon#enter sib2, iclass 24, count 0 2006.162.07:45:03.31#ibcon#flushed, iclass 24, count 0 2006.162.07:45:03.31#ibcon#about to write, iclass 24, count 0 2006.162.07:45:03.31#ibcon#wrote, iclass 24, count 0 2006.162.07:45:03.31#ibcon#about to read 3, iclass 24, count 0 2006.162.07:45:03.33#ibcon#read 3, iclass 24, count 0 2006.162.07:45:03.33#ibcon#about to read 4, iclass 24, count 0 2006.162.07:45:03.33#ibcon#read 4, iclass 24, count 0 2006.162.07:45:03.33#ibcon#about to read 5, iclass 24, count 0 2006.162.07:45:03.33#ibcon#read 5, iclass 24, count 0 2006.162.07:45:03.33#ibcon#about to read 6, iclass 24, count 0 2006.162.07:45:03.33#ibcon#read 6, iclass 24, count 0 2006.162.07:45:03.33#ibcon#end of sib2, iclass 24, count 0 2006.162.07:45:03.33#ibcon#*mode == 0, iclass 24, count 0 2006.162.07:45:03.33#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.07:45:03.33#ibcon#[27=USB\r\n] 2006.162.07:45:03.33#ibcon#*before write, iclass 24, count 0 2006.162.07:45:03.33#ibcon#enter sib2, iclass 24, count 0 2006.162.07:45:03.33#ibcon#flushed, iclass 24, count 0 2006.162.07:45:03.33#ibcon#about to write, iclass 24, count 0 2006.162.07:45:03.33#ibcon#wrote, iclass 24, count 0 2006.162.07:45:03.33#ibcon#about to read 3, iclass 24, count 0 2006.162.07:45:03.36#ibcon#read 3, iclass 24, count 0 2006.162.07:45:03.36#ibcon#about to read 4, iclass 24, count 0 2006.162.07:45:03.36#ibcon#read 4, iclass 24, count 0 2006.162.07:45:03.36#ibcon#about to read 5, iclass 24, count 0 2006.162.07:45:03.36#ibcon#read 5, iclass 24, count 0 2006.162.07:45:03.36#ibcon#about to read 6, iclass 24, count 0 2006.162.07:45:03.36#ibcon#read 6, iclass 24, count 0 2006.162.07:45:03.36#ibcon#end of sib2, iclass 24, count 0 2006.162.07:45:03.36#ibcon#*after write, iclass 24, count 0 2006.162.07:45:03.36#ibcon#*before return 0, iclass 24, count 0 2006.162.07:45:03.36#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:45:03.36#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:45:03.36#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.07:45:03.36#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.07:45:03.36$vc4f8/vblo=6,752.99 2006.162.07:45:03.36#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.162.07:45:03.36#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.162.07:45:03.36#ibcon#ireg 17 cls_cnt 0 2006.162.07:45:03.36#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:45:03.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:45:03.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:45:03.36#ibcon#enter wrdev, iclass 26, count 0 2006.162.07:45:03.36#ibcon#first serial, iclass 26, count 0 2006.162.07:45:03.36#ibcon#enter sib2, iclass 26, count 0 2006.162.07:45:03.36#ibcon#flushed, iclass 26, count 0 2006.162.07:45:03.36#ibcon#about to write, iclass 26, count 0 2006.162.07:45:03.36#ibcon#wrote, iclass 26, count 0 2006.162.07:45:03.36#ibcon#about to read 3, iclass 26, count 0 2006.162.07:45:03.38#ibcon#read 3, iclass 26, count 0 2006.162.07:45:03.38#ibcon#about to read 4, iclass 26, count 0 2006.162.07:45:03.38#ibcon#read 4, iclass 26, count 0 2006.162.07:45:03.38#ibcon#about to read 5, iclass 26, count 0 2006.162.07:45:03.38#ibcon#read 5, iclass 26, count 0 2006.162.07:45:03.38#ibcon#about to read 6, iclass 26, count 0 2006.162.07:45:03.38#ibcon#read 6, iclass 26, count 0 2006.162.07:45:03.38#ibcon#end of sib2, iclass 26, count 0 2006.162.07:45:03.38#ibcon#*mode == 0, iclass 26, count 0 2006.162.07:45:03.38#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.162.07:45:03.38#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.07:45:03.38#ibcon#*before write, iclass 26, count 0 2006.162.07:45:03.38#ibcon#enter sib2, iclass 26, count 0 2006.162.07:45:03.38#ibcon#flushed, iclass 26, count 0 2006.162.07:45:03.38#ibcon#about to write, iclass 26, count 0 2006.162.07:45:03.38#ibcon#wrote, iclass 26, count 0 2006.162.07:45:03.38#ibcon#about to read 3, iclass 26, count 0 2006.162.07:45:03.42#ibcon#read 3, iclass 26, count 0 2006.162.07:45:03.42#ibcon#about to read 4, iclass 26, count 0 2006.162.07:45:03.42#ibcon#read 4, iclass 26, count 0 2006.162.07:45:03.42#ibcon#about to read 5, iclass 26, count 0 2006.162.07:45:03.42#ibcon#read 5, iclass 26, count 0 2006.162.07:45:03.42#ibcon#about to read 6, iclass 26, count 0 2006.162.07:45:03.42#ibcon#read 6, iclass 26, count 0 2006.162.07:45:03.42#ibcon#end of sib2, iclass 26, count 0 2006.162.07:45:03.42#ibcon#*after write, iclass 26, count 0 2006.162.07:45:03.42#ibcon#*before return 0, iclass 26, count 0 2006.162.07:45:03.42#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:45:03.42#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:45:03.42#ibcon#about to clear, iclass 26 cls_cnt 0 2006.162.07:45:03.42#ibcon#cleared, iclass 26 cls_cnt 0 2006.162.07:45:03.42$vc4f8/vb=6,4 2006.162.07:45:03.42#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.162.07:45:03.42#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.162.07:45:03.42#ibcon#ireg 11 cls_cnt 2 2006.162.07:45:03.42#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.162.07:45:03.48#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.162.07:45:03.48#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.162.07:45:03.48#ibcon#enter wrdev, iclass 28, count 2 2006.162.07:45:03.48#ibcon#first serial, iclass 28, count 2 2006.162.07:45:03.48#ibcon#enter sib2, iclass 28, count 2 2006.162.07:45:03.48#ibcon#flushed, iclass 28, count 2 2006.162.07:45:03.48#ibcon#about to write, iclass 28, count 2 2006.162.07:45:03.48#ibcon#wrote, iclass 28, count 2 2006.162.07:45:03.48#ibcon#about to read 3, iclass 28, count 2 2006.162.07:45:03.50#ibcon#read 3, iclass 28, count 2 2006.162.07:45:03.50#ibcon#about to read 4, iclass 28, count 2 2006.162.07:45:03.50#ibcon#read 4, iclass 28, count 2 2006.162.07:45:03.50#ibcon#about to read 5, iclass 28, count 2 2006.162.07:45:03.50#ibcon#read 5, iclass 28, count 2 2006.162.07:45:03.50#ibcon#about to read 6, iclass 28, count 2 2006.162.07:45:03.50#ibcon#read 6, iclass 28, count 2 2006.162.07:45:03.50#ibcon#end of sib2, iclass 28, count 2 2006.162.07:45:03.50#ibcon#*mode == 0, iclass 28, count 2 2006.162.07:45:03.50#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.162.07:45:03.50#ibcon#[27=AT06-04\r\n] 2006.162.07:45:03.50#ibcon#*before write, iclass 28, count 2 2006.162.07:45:03.50#ibcon#enter sib2, iclass 28, count 2 2006.162.07:45:03.50#ibcon#flushed, iclass 28, count 2 2006.162.07:45:03.50#ibcon#about to write, iclass 28, count 2 2006.162.07:45:03.50#ibcon#wrote, iclass 28, count 2 2006.162.07:45:03.50#ibcon#about to read 3, iclass 28, count 2 2006.162.07:45:03.53#ibcon#read 3, iclass 28, count 2 2006.162.07:45:03.53#ibcon#about to read 4, iclass 28, count 2 2006.162.07:45:03.53#ibcon#read 4, iclass 28, count 2 2006.162.07:45:03.53#ibcon#about to read 5, iclass 28, count 2 2006.162.07:45:03.53#ibcon#read 5, iclass 28, count 2 2006.162.07:45:03.53#ibcon#about to read 6, iclass 28, count 2 2006.162.07:45:03.53#ibcon#read 6, iclass 28, count 2 2006.162.07:45:03.53#ibcon#end of sib2, iclass 28, count 2 2006.162.07:45:03.53#ibcon#*after write, iclass 28, count 2 2006.162.07:45:03.53#ibcon#*before return 0, iclass 28, count 2 2006.162.07:45:03.53#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.162.07:45:03.53#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.162.07:45:03.53#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.162.07:45:03.53#ibcon#ireg 7 cls_cnt 0 2006.162.07:45:03.53#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.162.07:45:03.65#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.162.07:45:03.65#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.162.07:45:03.65#ibcon#enter wrdev, iclass 28, count 0 2006.162.07:45:03.65#ibcon#first serial, iclass 28, count 0 2006.162.07:45:03.65#ibcon#enter sib2, iclass 28, count 0 2006.162.07:45:03.65#ibcon#flushed, iclass 28, count 0 2006.162.07:45:03.65#ibcon#about to write, iclass 28, count 0 2006.162.07:45:03.65#ibcon#wrote, iclass 28, count 0 2006.162.07:45:03.65#ibcon#about to read 3, iclass 28, count 0 2006.162.07:45:03.67#ibcon#read 3, iclass 28, count 0 2006.162.07:45:03.67#ibcon#about to read 4, iclass 28, count 0 2006.162.07:45:03.67#ibcon#read 4, iclass 28, count 0 2006.162.07:45:03.67#ibcon#about to read 5, iclass 28, count 0 2006.162.07:45:03.67#ibcon#read 5, iclass 28, count 0 2006.162.07:45:03.67#ibcon#about to read 6, iclass 28, count 0 2006.162.07:45:03.67#ibcon#read 6, iclass 28, count 0 2006.162.07:45:03.67#ibcon#end of sib2, iclass 28, count 0 2006.162.07:45:03.67#ibcon#*mode == 0, iclass 28, count 0 2006.162.07:45:03.67#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.162.07:45:03.67#ibcon#[27=USB\r\n] 2006.162.07:45:03.67#ibcon#*before write, iclass 28, count 0 2006.162.07:45:03.67#ibcon#enter sib2, iclass 28, count 0 2006.162.07:45:03.67#ibcon#flushed, iclass 28, count 0 2006.162.07:45:03.67#ibcon#about to write, iclass 28, count 0 2006.162.07:45:03.67#ibcon#wrote, iclass 28, count 0 2006.162.07:45:03.67#ibcon#about to read 3, iclass 28, count 0 2006.162.07:45:03.70#ibcon#read 3, iclass 28, count 0 2006.162.07:45:03.70#ibcon#about to read 4, iclass 28, count 0 2006.162.07:45:03.70#ibcon#read 4, iclass 28, count 0 2006.162.07:45:03.70#ibcon#about to read 5, iclass 28, count 0 2006.162.07:45:03.70#ibcon#read 5, iclass 28, count 0 2006.162.07:45:03.70#ibcon#about to read 6, iclass 28, count 0 2006.162.07:45:03.70#ibcon#read 6, iclass 28, count 0 2006.162.07:45:03.70#ibcon#end of sib2, iclass 28, count 0 2006.162.07:45:03.70#ibcon#*after write, iclass 28, count 0 2006.162.07:45:03.70#ibcon#*before return 0, iclass 28, count 0 2006.162.07:45:03.70#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.162.07:45:03.70#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.162.07:45:03.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.162.07:45:03.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.162.07:45:03.70$vc4f8/vabw=wide 2006.162.07:45:03.70#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.162.07:45:03.70#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.162.07:45:03.70#ibcon#ireg 8 cls_cnt 0 2006.162.07:45:03.70#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.162.07:45:03.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.162.07:45:03.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.162.07:45:03.70#ibcon#enter wrdev, iclass 30, count 0 2006.162.07:45:03.70#ibcon#first serial, iclass 30, count 0 2006.162.07:45:03.70#ibcon#enter sib2, iclass 30, count 0 2006.162.07:45:03.70#ibcon#flushed, iclass 30, count 0 2006.162.07:45:03.70#ibcon#about to write, iclass 30, count 0 2006.162.07:45:03.70#ibcon#wrote, iclass 30, count 0 2006.162.07:45:03.70#ibcon#about to read 3, iclass 30, count 0 2006.162.07:45:03.72#ibcon#read 3, iclass 30, count 0 2006.162.07:45:03.72#ibcon#about to read 4, iclass 30, count 0 2006.162.07:45:03.72#ibcon#read 4, iclass 30, count 0 2006.162.07:45:03.72#ibcon#about to read 5, iclass 30, count 0 2006.162.07:45:03.72#ibcon#read 5, iclass 30, count 0 2006.162.07:45:03.72#ibcon#about to read 6, iclass 30, count 0 2006.162.07:45:03.72#ibcon#read 6, iclass 30, count 0 2006.162.07:45:03.72#ibcon#end of sib2, iclass 30, count 0 2006.162.07:45:03.72#ibcon#*mode == 0, iclass 30, count 0 2006.162.07:45:03.72#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.162.07:45:03.72#ibcon#[25=BW32\r\n] 2006.162.07:45:03.72#ibcon#*before write, iclass 30, count 0 2006.162.07:45:03.72#ibcon#enter sib2, iclass 30, count 0 2006.162.07:45:03.72#ibcon#flushed, iclass 30, count 0 2006.162.07:45:03.72#ibcon#about to write, iclass 30, count 0 2006.162.07:45:03.72#ibcon#wrote, iclass 30, count 0 2006.162.07:45:03.72#ibcon#about to read 3, iclass 30, count 0 2006.162.07:45:03.75#ibcon#read 3, iclass 30, count 0 2006.162.07:45:03.75#ibcon#about to read 4, iclass 30, count 0 2006.162.07:45:03.75#ibcon#read 4, iclass 30, count 0 2006.162.07:45:03.75#ibcon#about to read 5, iclass 30, count 0 2006.162.07:45:03.75#ibcon#read 5, iclass 30, count 0 2006.162.07:45:03.75#ibcon#about to read 6, iclass 30, count 0 2006.162.07:45:03.75#ibcon#read 6, iclass 30, count 0 2006.162.07:45:03.75#ibcon#end of sib2, iclass 30, count 0 2006.162.07:45:03.75#ibcon#*after write, iclass 30, count 0 2006.162.07:45:03.75#ibcon#*before return 0, iclass 30, count 0 2006.162.07:45:03.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.162.07:45:03.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.162.07:45:03.75#ibcon#about to clear, iclass 30 cls_cnt 0 2006.162.07:45:03.75#ibcon#cleared, iclass 30 cls_cnt 0 2006.162.07:45:03.75$vc4f8/vbbw=wide 2006.162.07:45:03.75#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.162.07:45:03.75#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.162.07:45:03.75#ibcon#ireg 8 cls_cnt 0 2006.162.07:45:03.75#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:45:03.82#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:45:03.82#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:45:03.82#ibcon#enter wrdev, iclass 32, count 0 2006.162.07:45:03.82#ibcon#first serial, iclass 32, count 0 2006.162.07:45:03.82#ibcon#enter sib2, iclass 32, count 0 2006.162.07:45:03.82#ibcon#flushed, iclass 32, count 0 2006.162.07:45:03.82#ibcon#about to write, iclass 32, count 0 2006.162.07:45:03.82#ibcon#wrote, iclass 32, count 0 2006.162.07:45:03.82#ibcon#about to read 3, iclass 32, count 0 2006.162.07:45:03.84#ibcon#read 3, iclass 32, count 0 2006.162.07:45:03.84#ibcon#about to read 4, iclass 32, count 0 2006.162.07:45:03.84#ibcon#read 4, iclass 32, count 0 2006.162.07:45:03.84#ibcon#about to read 5, iclass 32, count 0 2006.162.07:45:03.84#ibcon#read 5, iclass 32, count 0 2006.162.07:45:03.84#ibcon#about to read 6, iclass 32, count 0 2006.162.07:45:03.84#ibcon#read 6, iclass 32, count 0 2006.162.07:45:03.84#ibcon#end of sib2, iclass 32, count 0 2006.162.07:45:03.84#ibcon#*mode == 0, iclass 32, count 0 2006.162.07:45:03.84#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.162.07:45:03.84#ibcon#[27=BW32\r\n] 2006.162.07:45:03.84#ibcon#*before write, iclass 32, count 0 2006.162.07:45:03.84#ibcon#enter sib2, iclass 32, count 0 2006.162.07:45:03.84#ibcon#flushed, iclass 32, count 0 2006.162.07:45:03.84#ibcon#about to write, iclass 32, count 0 2006.162.07:45:03.84#ibcon#wrote, iclass 32, count 0 2006.162.07:45:03.84#ibcon#about to read 3, iclass 32, count 0 2006.162.07:45:03.87#ibcon#read 3, iclass 32, count 0 2006.162.07:45:03.87#ibcon#about to read 4, iclass 32, count 0 2006.162.07:45:03.87#ibcon#read 4, iclass 32, count 0 2006.162.07:45:03.87#ibcon#about to read 5, iclass 32, count 0 2006.162.07:45:03.87#ibcon#read 5, iclass 32, count 0 2006.162.07:45:03.87#ibcon#about to read 6, iclass 32, count 0 2006.162.07:45:03.87#ibcon#read 6, iclass 32, count 0 2006.162.07:45:03.87#ibcon#end of sib2, iclass 32, count 0 2006.162.07:45:03.87#ibcon#*after write, iclass 32, count 0 2006.162.07:45:03.87#ibcon#*before return 0, iclass 32, count 0 2006.162.07:45:03.87#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:45:03.87#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:45:03.87#ibcon#about to clear, iclass 32 cls_cnt 0 2006.162.07:45:03.87#ibcon#cleared, iclass 32 cls_cnt 0 2006.162.07:45:03.87$4f8m12a/ifd4f 2006.162.07:45:03.87$ifd4f/lo= 2006.162.07:45:03.87$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.07:45:03.87$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.07:45:03.87$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.07:45:03.87$ifd4f/patch= 2006.162.07:45:03.87$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.07:45:03.87$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.07:45:03.87$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.07:45:03.87$4f8m12a/"form=m,16.000,1:2 2006.162.07:45:03.87$4f8m12a/"tpicd 2006.162.07:45:03.87$4f8m12a/echo=off 2006.162.07:45:03.87$4f8m12a/xlog=off 2006.162.07:45:03.87:!2006.162.07:45:30 2006.162.07:45:10.14#trakl#Source acquired 2006.162.07:45:12.14#flagr#flagr/antenna,acquired 2006.162.07:45:30.00:preob 2006.162.07:45:31.14/onsource/TRACKING 2006.162.07:45:31.14:!2006.162.07:45:40 2006.162.07:45:40.00:data_valid=on 2006.162.07:45:40.00:midob 2006.162.07:45:40.14/onsource/TRACKING 2006.162.07:45:40.14/wx/17.88,1007.2,100 2006.162.07:45:40.32/cable/+6.5354E-03 2006.162.07:45:41.41/va/01,08,usb,yes,39,42 2006.162.07:45:41.41/va/02,07,usb,yes,40,42 2006.162.07:45:41.41/va/03,06,usb,yes,42,42 2006.162.07:45:41.41/va/04,07,usb,yes,41,44 2006.162.07:45:41.41/va/05,07,usb,yes,44,47 2006.162.07:45:41.41/va/06,06,usb,yes,44,43 2006.162.07:45:41.41/va/07,06,usb,yes,44,44 2006.162.07:45:41.41/va/08,07,usb,yes,42,41 2006.162.07:45:41.64/valo/01,532.99,yes,locked 2006.162.07:45:41.64/valo/02,572.99,yes,locked 2006.162.07:45:41.64/valo/03,672.99,yes,locked 2006.162.07:45:41.64/valo/04,832.99,yes,locked 2006.162.07:45:41.64/valo/05,652.99,yes,locked 2006.162.07:45:41.64/valo/06,772.99,yes,locked 2006.162.07:45:41.64/valo/07,832.99,yes,locked 2006.162.07:45:41.64/valo/08,852.99,yes,locked 2006.162.07:45:42.73/vb/01,04,usb,yes,29,28 2006.162.07:45:42.73/vb/02,04,usb,yes,31,32 2006.162.07:45:42.73/vb/03,04,usb,yes,27,31 2006.162.07:45:42.73/vb/04,04,usb,yes,29,28 2006.162.07:45:42.73/vb/05,04,usb,yes,27,31 2006.162.07:45:42.73/vb/06,04,usb,yes,28,30 2006.162.07:45:42.73/vb/07,04,usb,yes,30,30 2006.162.07:45:42.73/vb/08,04,usb,yes,27,31 2006.162.07:45:42.96/vblo/01,632.99,yes,locked 2006.162.07:45:42.96/vblo/02,640.99,yes,locked 2006.162.07:45:42.96/vblo/03,656.99,yes,locked 2006.162.07:45:42.96/vblo/04,712.99,yes,locked 2006.162.07:45:42.96/vblo/05,744.99,yes,locked 2006.162.07:45:42.96/vblo/06,752.99,yes,locked 2006.162.07:45:42.96/vblo/07,734.99,yes,locked 2006.162.07:45:42.96/vblo/08,744.99,yes,locked 2006.162.07:45:43.11/vabw/8 2006.162.07:45:43.26/vbbw/8 2006.162.07:45:43.35/xfe/off,on,14.2 2006.162.07:45:43.78/ifatt/23,28,28,28 2006.162.07:45:44.08/fmout-gps/S +4.49E-07 2006.162.07:45:44.16:!2006.162.07:46:40 2006.162.07:46:40.00:data_valid=off 2006.162.07:46:40.00:postob 2006.162.07:46:40.12/cable/+6.5365E-03 2006.162.07:46:40.12/wx/17.88,1007.2,100 2006.162.07:46:41.08/fmout-gps/S +4.48E-07 2006.162.07:46:41.08:scan_name=162-0747,k06162,60 2006.162.07:46:41.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.162.07:46:41.14#flagr#flagr/antenna,new-source 2006.162.07:46:42.14:checkk5 2006.162.07:46:42.54/chk_autoobs//k5ts1/ autoobs is running! 2006.162.07:46:42.92/chk_autoobs//k5ts2/ autoobs is running! 2006.162.07:46:43.31/chk_autoobs//k5ts3/ autoobs is running! 2006.162.07:46:43.97/chk_autoobs//k5ts4/ autoobs is running! 2006.162.07:46:44.41/chk_obsdata//k5ts1/T1620745??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:46:44.86/chk_obsdata//k5ts2/T1620745??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:46:45.31/chk_obsdata//k5ts3/T1620745??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:46:45.74/chk_obsdata//k5ts4/T1620745??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:46:46.52/k5log//k5ts1_log_newline 2006.162.07:46:47.30/k5log//k5ts2_log_newline 2006.162.07:46:48.33/k5log//k5ts3_log_newline 2006.162.07:46:49.09/k5log//k5ts4_log_newline 2006.162.07:46:49.12/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.07:46:49.12:4f8m12a=1 2006.162.07:46:49.12$4f8m12a/echo=on 2006.162.07:46:49.12$4f8m12a/pcalon 2006.162.07:46:49.12$pcalon/"no phase cal control is implemented here 2006.162.07:46:49.12$4f8m12a/"tpicd=stop 2006.162.07:46:49.12$4f8m12a/vc4f8 2006.162.07:46:49.12$vc4f8/valo=1,532.99 2006.162.07:46:49.13#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.162.07:46:49.13#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.162.07:46:49.13#ibcon#ireg 17 cls_cnt 0 2006.162.07:46:49.13#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.162.07:46:49.13#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.162.07:46:49.13#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.162.07:46:49.13#ibcon#enter wrdev, iclass 39, count 0 2006.162.07:46:49.13#ibcon#first serial, iclass 39, count 0 2006.162.07:46:49.13#ibcon#enter sib2, iclass 39, count 0 2006.162.07:46:49.13#ibcon#flushed, iclass 39, count 0 2006.162.07:46:49.13#ibcon#about to write, iclass 39, count 0 2006.162.07:46:49.13#ibcon#wrote, iclass 39, count 0 2006.162.07:46:49.13#ibcon#about to read 3, iclass 39, count 0 2006.162.07:46:49.17#ibcon#read 3, iclass 39, count 0 2006.162.07:46:49.17#ibcon#about to read 4, iclass 39, count 0 2006.162.07:46:49.17#ibcon#read 4, iclass 39, count 0 2006.162.07:46:49.17#ibcon#about to read 5, iclass 39, count 0 2006.162.07:46:49.17#ibcon#read 5, iclass 39, count 0 2006.162.07:46:49.17#ibcon#about to read 6, iclass 39, count 0 2006.162.07:46:49.17#ibcon#read 6, iclass 39, count 0 2006.162.07:46:49.17#ibcon#end of sib2, iclass 39, count 0 2006.162.07:46:49.17#ibcon#*mode == 0, iclass 39, count 0 2006.162.07:46:49.17#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.162.07:46:49.17#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.07:46:49.17#ibcon#*before write, iclass 39, count 0 2006.162.07:46:49.17#ibcon#enter sib2, iclass 39, count 0 2006.162.07:46:49.17#ibcon#flushed, iclass 39, count 0 2006.162.07:46:49.17#ibcon#about to write, iclass 39, count 0 2006.162.07:46:49.17#ibcon#wrote, iclass 39, count 0 2006.162.07:46:49.17#ibcon#about to read 3, iclass 39, count 0 2006.162.07:46:49.22#ibcon#read 3, iclass 39, count 0 2006.162.07:46:49.22#ibcon#about to read 4, iclass 39, count 0 2006.162.07:46:49.22#ibcon#read 4, iclass 39, count 0 2006.162.07:46:49.22#ibcon#about to read 5, iclass 39, count 0 2006.162.07:46:49.22#ibcon#read 5, iclass 39, count 0 2006.162.07:46:49.22#ibcon#about to read 6, iclass 39, count 0 2006.162.07:46:49.22#ibcon#read 6, iclass 39, count 0 2006.162.07:46:49.22#ibcon#end of sib2, iclass 39, count 0 2006.162.07:46:49.22#ibcon#*after write, iclass 39, count 0 2006.162.07:46:49.22#ibcon#*before return 0, iclass 39, count 0 2006.162.07:46:49.22#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.162.07:46:49.22#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.162.07:46:49.22#ibcon#about to clear, iclass 39 cls_cnt 0 2006.162.07:46:49.22#ibcon#cleared, iclass 39 cls_cnt 0 2006.162.07:46:49.22$vc4f8/va=1,8 2006.162.07:46:49.22#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.162.07:46:49.22#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.162.07:46:49.22#ibcon#ireg 11 cls_cnt 2 2006.162.07:46:49.22#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.162.07:46:49.22#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.162.07:46:49.22#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.162.07:46:49.22#ibcon#enter wrdev, iclass 3, count 2 2006.162.07:46:49.22#ibcon#first serial, iclass 3, count 2 2006.162.07:46:49.22#ibcon#enter sib2, iclass 3, count 2 2006.162.07:46:49.22#ibcon#flushed, iclass 3, count 2 2006.162.07:46:49.22#ibcon#about to write, iclass 3, count 2 2006.162.07:46:49.22#ibcon#wrote, iclass 3, count 2 2006.162.07:46:49.22#ibcon#about to read 3, iclass 3, count 2 2006.162.07:46:49.24#ibcon#read 3, iclass 3, count 2 2006.162.07:46:49.24#ibcon#about to read 4, iclass 3, count 2 2006.162.07:46:49.24#ibcon#read 4, iclass 3, count 2 2006.162.07:46:49.24#ibcon#about to read 5, iclass 3, count 2 2006.162.07:46:49.24#ibcon#read 5, iclass 3, count 2 2006.162.07:46:49.24#ibcon#about to read 6, iclass 3, count 2 2006.162.07:46:49.24#ibcon#read 6, iclass 3, count 2 2006.162.07:46:49.24#ibcon#end of sib2, iclass 3, count 2 2006.162.07:46:49.24#ibcon#*mode == 0, iclass 3, count 2 2006.162.07:46:49.24#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.162.07:46:49.24#ibcon#[25=AT01-08\r\n] 2006.162.07:46:49.24#ibcon#*before write, iclass 3, count 2 2006.162.07:46:49.24#ibcon#enter sib2, iclass 3, count 2 2006.162.07:46:49.24#ibcon#flushed, iclass 3, count 2 2006.162.07:46:49.24#ibcon#about to write, iclass 3, count 2 2006.162.07:46:49.24#ibcon#wrote, iclass 3, count 2 2006.162.07:46:49.24#ibcon#about to read 3, iclass 3, count 2 2006.162.07:46:49.28#ibcon#read 3, iclass 3, count 2 2006.162.07:46:49.28#ibcon#about to read 4, iclass 3, count 2 2006.162.07:46:49.28#ibcon#read 4, iclass 3, count 2 2006.162.07:46:49.28#ibcon#about to read 5, iclass 3, count 2 2006.162.07:46:49.28#ibcon#read 5, iclass 3, count 2 2006.162.07:46:49.28#ibcon#about to read 6, iclass 3, count 2 2006.162.07:46:49.28#ibcon#read 6, iclass 3, count 2 2006.162.07:46:49.28#ibcon#end of sib2, iclass 3, count 2 2006.162.07:46:49.28#ibcon#*after write, iclass 3, count 2 2006.162.07:46:49.28#ibcon#*before return 0, iclass 3, count 2 2006.162.07:46:49.28#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.162.07:46:49.28#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.162.07:46:49.28#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.162.07:46:49.28#ibcon#ireg 7 cls_cnt 0 2006.162.07:46:49.28#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.162.07:46:49.40#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.162.07:46:49.40#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.162.07:46:49.40#ibcon#enter wrdev, iclass 3, count 0 2006.162.07:46:49.40#ibcon#first serial, iclass 3, count 0 2006.162.07:46:49.40#ibcon#enter sib2, iclass 3, count 0 2006.162.07:46:49.40#ibcon#flushed, iclass 3, count 0 2006.162.07:46:49.40#ibcon#about to write, iclass 3, count 0 2006.162.07:46:49.40#ibcon#wrote, iclass 3, count 0 2006.162.07:46:49.40#ibcon#about to read 3, iclass 3, count 0 2006.162.07:46:49.42#ibcon#read 3, iclass 3, count 0 2006.162.07:46:49.42#ibcon#about to read 4, iclass 3, count 0 2006.162.07:46:49.42#ibcon#read 4, iclass 3, count 0 2006.162.07:46:49.42#ibcon#about to read 5, iclass 3, count 0 2006.162.07:46:49.42#ibcon#read 5, iclass 3, count 0 2006.162.07:46:49.42#ibcon#about to read 6, iclass 3, count 0 2006.162.07:46:49.42#ibcon#read 6, iclass 3, count 0 2006.162.07:46:49.42#ibcon#end of sib2, iclass 3, count 0 2006.162.07:46:49.42#ibcon#*mode == 0, iclass 3, count 0 2006.162.07:46:49.42#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.162.07:46:49.42#ibcon#[25=USB\r\n] 2006.162.07:46:49.42#ibcon#*before write, iclass 3, count 0 2006.162.07:46:49.42#ibcon#enter sib2, iclass 3, count 0 2006.162.07:46:49.42#ibcon#flushed, iclass 3, count 0 2006.162.07:46:49.42#ibcon#about to write, iclass 3, count 0 2006.162.07:46:49.42#ibcon#wrote, iclass 3, count 0 2006.162.07:46:49.42#ibcon#about to read 3, iclass 3, count 0 2006.162.07:46:49.45#ibcon#read 3, iclass 3, count 0 2006.162.07:46:49.45#ibcon#about to read 4, iclass 3, count 0 2006.162.07:46:49.45#ibcon#read 4, iclass 3, count 0 2006.162.07:46:49.45#ibcon#about to read 5, iclass 3, count 0 2006.162.07:46:49.45#ibcon#read 5, iclass 3, count 0 2006.162.07:46:49.45#ibcon#about to read 6, iclass 3, count 0 2006.162.07:46:49.45#ibcon#read 6, iclass 3, count 0 2006.162.07:46:49.45#ibcon#end of sib2, iclass 3, count 0 2006.162.07:46:49.45#ibcon#*after write, iclass 3, count 0 2006.162.07:46:49.45#ibcon#*before return 0, iclass 3, count 0 2006.162.07:46:49.45#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.162.07:46:49.45#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.162.07:46:49.45#ibcon#about to clear, iclass 3 cls_cnt 0 2006.162.07:46:49.45#ibcon#cleared, iclass 3 cls_cnt 0 2006.162.07:46:49.45$vc4f8/valo=2,572.99 2006.162.07:46:49.45#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.162.07:46:49.45#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.162.07:46:49.45#ibcon#ireg 17 cls_cnt 0 2006.162.07:46:49.45#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.162.07:46:49.45#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.162.07:46:49.45#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.162.07:46:49.45#ibcon#enter wrdev, iclass 5, count 0 2006.162.07:46:49.45#ibcon#first serial, iclass 5, count 0 2006.162.07:46:49.45#ibcon#enter sib2, iclass 5, count 0 2006.162.07:46:49.45#ibcon#flushed, iclass 5, count 0 2006.162.07:46:49.45#ibcon#about to write, iclass 5, count 0 2006.162.07:46:49.45#ibcon#wrote, iclass 5, count 0 2006.162.07:46:49.45#ibcon#about to read 3, iclass 5, count 0 2006.162.07:46:49.47#ibcon#read 3, iclass 5, count 0 2006.162.07:46:49.47#ibcon#about to read 4, iclass 5, count 0 2006.162.07:46:49.47#ibcon#read 4, iclass 5, count 0 2006.162.07:46:49.47#ibcon#about to read 5, iclass 5, count 0 2006.162.07:46:49.47#ibcon#read 5, iclass 5, count 0 2006.162.07:46:49.47#ibcon#about to read 6, iclass 5, count 0 2006.162.07:46:49.47#ibcon#read 6, iclass 5, count 0 2006.162.07:46:49.47#ibcon#end of sib2, iclass 5, count 0 2006.162.07:46:49.47#ibcon#*mode == 0, iclass 5, count 0 2006.162.07:46:49.47#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.162.07:46:49.47#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.07:46:49.47#ibcon#*before write, iclass 5, count 0 2006.162.07:46:49.47#ibcon#enter sib2, iclass 5, count 0 2006.162.07:46:49.47#ibcon#flushed, iclass 5, count 0 2006.162.07:46:49.47#ibcon#about to write, iclass 5, count 0 2006.162.07:46:49.47#ibcon#wrote, iclass 5, count 0 2006.162.07:46:49.47#ibcon#about to read 3, iclass 5, count 0 2006.162.07:46:49.51#ibcon#read 3, iclass 5, count 0 2006.162.07:46:49.51#ibcon#about to read 4, iclass 5, count 0 2006.162.07:46:49.51#ibcon#read 4, iclass 5, count 0 2006.162.07:46:49.51#ibcon#about to read 5, iclass 5, count 0 2006.162.07:46:49.51#ibcon#read 5, iclass 5, count 0 2006.162.07:46:49.51#ibcon#about to read 6, iclass 5, count 0 2006.162.07:46:49.51#ibcon#read 6, iclass 5, count 0 2006.162.07:46:49.51#ibcon#end of sib2, iclass 5, count 0 2006.162.07:46:49.51#ibcon#*after write, iclass 5, count 0 2006.162.07:46:49.51#ibcon#*before return 0, iclass 5, count 0 2006.162.07:46:49.51#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.162.07:46:49.51#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.162.07:46:49.51#ibcon#about to clear, iclass 5 cls_cnt 0 2006.162.07:46:49.51#ibcon#cleared, iclass 5 cls_cnt 0 2006.162.07:46:49.51$vc4f8/va=2,7 2006.162.07:46:49.51#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.162.07:46:49.51#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.162.07:46:49.51#ibcon#ireg 11 cls_cnt 2 2006.162.07:46:49.51#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.162.07:46:49.57#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.162.07:46:49.57#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.162.07:46:49.57#ibcon#enter wrdev, iclass 7, count 2 2006.162.07:46:49.57#ibcon#first serial, iclass 7, count 2 2006.162.07:46:49.57#ibcon#enter sib2, iclass 7, count 2 2006.162.07:46:49.57#ibcon#flushed, iclass 7, count 2 2006.162.07:46:49.57#ibcon#about to write, iclass 7, count 2 2006.162.07:46:49.57#ibcon#wrote, iclass 7, count 2 2006.162.07:46:49.57#ibcon#about to read 3, iclass 7, count 2 2006.162.07:46:49.59#ibcon#read 3, iclass 7, count 2 2006.162.07:46:49.59#ibcon#about to read 4, iclass 7, count 2 2006.162.07:46:49.59#ibcon#read 4, iclass 7, count 2 2006.162.07:46:49.59#ibcon#about to read 5, iclass 7, count 2 2006.162.07:46:49.59#ibcon#read 5, iclass 7, count 2 2006.162.07:46:49.59#ibcon#about to read 6, iclass 7, count 2 2006.162.07:46:49.59#ibcon#read 6, iclass 7, count 2 2006.162.07:46:49.59#ibcon#end of sib2, iclass 7, count 2 2006.162.07:46:49.59#ibcon#*mode == 0, iclass 7, count 2 2006.162.07:46:49.59#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.162.07:46:49.59#ibcon#[25=AT02-07\r\n] 2006.162.07:46:49.59#ibcon#*before write, iclass 7, count 2 2006.162.07:46:49.59#ibcon#enter sib2, iclass 7, count 2 2006.162.07:46:49.59#ibcon#flushed, iclass 7, count 2 2006.162.07:46:49.59#ibcon#about to write, iclass 7, count 2 2006.162.07:46:49.59#ibcon#wrote, iclass 7, count 2 2006.162.07:46:49.59#ibcon#about to read 3, iclass 7, count 2 2006.162.07:46:49.63#ibcon#read 3, iclass 7, count 2 2006.162.07:46:49.63#ibcon#about to read 4, iclass 7, count 2 2006.162.07:46:49.63#ibcon#read 4, iclass 7, count 2 2006.162.07:46:49.63#ibcon#about to read 5, iclass 7, count 2 2006.162.07:46:49.63#ibcon#read 5, iclass 7, count 2 2006.162.07:46:49.63#ibcon#about to read 6, iclass 7, count 2 2006.162.07:46:49.63#ibcon#read 6, iclass 7, count 2 2006.162.07:46:49.63#ibcon#end of sib2, iclass 7, count 2 2006.162.07:46:49.63#ibcon#*after write, iclass 7, count 2 2006.162.07:46:49.63#ibcon#*before return 0, iclass 7, count 2 2006.162.07:46:49.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.162.07:46:49.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.162.07:46:49.63#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.162.07:46:49.63#ibcon#ireg 7 cls_cnt 0 2006.162.07:46:49.63#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.162.07:46:49.75#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.162.07:46:49.75#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.162.07:46:49.75#ibcon#enter wrdev, iclass 7, count 0 2006.162.07:46:49.75#ibcon#first serial, iclass 7, count 0 2006.162.07:46:49.75#ibcon#enter sib2, iclass 7, count 0 2006.162.07:46:49.75#ibcon#flushed, iclass 7, count 0 2006.162.07:46:49.75#ibcon#about to write, iclass 7, count 0 2006.162.07:46:49.75#ibcon#wrote, iclass 7, count 0 2006.162.07:46:49.75#ibcon#about to read 3, iclass 7, count 0 2006.162.07:46:49.77#ibcon#read 3, iclass 7, count 0 2006.162.07:46:49.77#ibcon#about to read 4, iclass 7, count 0 2006.162.07:46:49.77#ibcon#read 4, iclass 7, count 0 2006.162.07:46:49.77#ibcon#about to read 5, iclass 7, count 0 2006.162.07:46:49.77#ibcon#read 5, iclass 7, count 0 2006.162.07:46:49.77#ibcon#about to read 6, iclass 7, count 0 2006.162.07:46:49.77#ibcon#read 6, iclass 7, count 0 2006.162.07:46:49.77#ibcon#end of sib2, iclass 7, count 0 2006.162.07:46:49.77#ibcon#*mode == 0, iclass 7, count 0 2006.162.07:46:49.77#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.162.07:46:49.77#ibcon#[25=USB\r\n] 2006.162.07:46:49.77#ibcon#*before write, iclass 7, count 0 2006.162.07:46:49.77#ibcon#enter sib2, iclass 7, count 0 2006.162.07:46:49.77#ibcon#flushed, iclass 7, count 0 2006.162.07:46:49.77#ibcon#about to write, iclass 7, count 0 2006.162.07:46:49.77#ibcon#wrote, iclass 7, count 0 2006.162.07:46:49.77#ibcon#about to read 3, iclass 7, count 0 2006.162.07:46:49.80#ibcon#read 3, iclass 7, count 0 2006.162.07:46:49.80#ibcon#about to read 4, iclass 7, count 0 2006.162.07:46:49.80#ibcon#read 4, iclass 7, count 0 2006.162.07:46:49.80#ibcon#about to read 5, iclass 7, count 0 2006.162.07:46:49.80#ibcon#read 5, iclass 7, count 0 2006.162.07:46:49.80#ibcon#about to read 6, iclass 7, count 0 2006.162.07:46:49.80#ibcon#read 6, iclass 7, count 0 2006.162.07:46:49.80#ibcon#end of sib2, iclass 7, count 0 2006.162.07:46:49.80#ibcon#*after write, iclass 7, count 0 2006.162.07:46:49.80#ibcon#*before return 0, iclass 7, count 0 2006.162.07:46:49.80#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.162.07:46:49.80#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.162.07:46:49.80#ibcon#about to clear, iclass 7 cls_cnt 0 2006.162.07:46:49.80#ibcon#cleared, iclass 7 cls_cnt 0 2006.162.07:46:49.80$vc4f8/valo=3,672.99 2006.162.07:46:49.80#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.162.07:46:49.80#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.162.07:46:49.80#ibcon#ireg 17 cls_cnt 0 2006.162.07:46:49.80#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.162.07:46:49.80#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.162.07:46:49.80#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.162.07:46:49.80#ibcon#enter wrdev, iclass 11, count 0 2006.162.07:46:49.80#ibcon#first serial, iclass 11, count 0 2006.162.07:46:49.80#ibcon#enter sib2, iclass 11, count 0 2006.162.07:46:49.80#ibcon#flushed, iclass 11, count 0 2006.162.07:46:49.80#ibcon#about to write, iclass 11, count 0 2006.162.07:46:49.80#ibcon#wrote, iclass 11, count 0 2006.162.07:46:49.80#ibcon#about to read 3, iclass 11, count 0 2006.162.07:46:49.82#ibcon#read 3, iclass 11, count 0 2006.162.07:46:49.82#ibcon#about to read 4, iclass 11, count 0 2006.162.07:46:49.82#ibcon#read 4, iclass 11, count 0 2006.162.07:46:49.82#ibcon#about to read 5, iclass 11, count 0 2006.162.07:46:49.82#ibcon#read 5, iclass 11, count 0 2006.162.07:46:49.82#ibcon#about to read 6, iclass 11, count 0 2006.162.07:46:49.82#ibcon#read 6, iclass 11, count 0 2006.162.07:46:49.82#ibcon#end of sib2, iclass 11, count 0 2006.162.07:46:49.82#ibcon#*mode == 0, iclass 11, count 0 2006.162.07:46:49.82#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.162.07:46:49.82#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.07:46:49.82#ibcon#*before write, iclass 11, count 0 2006.162.07:46:49.82#ibcon#enter sib2, iclass 11, count 0 2006.162.07:46:49.82#ibcon#flushed, iclass 11, count 0 2006.162.07:46:49.82#ibcon#about to write, iclass 11, count 0 2006.162.07:46:49.82#ibcon#wrote, iclass 11, count 0 2006.162.07:46:49.82#ibcon#about to read 3, iclass 11, count 0 2006.162.07:46:49.87#ibcon#read 3, iclass 11, count 0 2006.162.07:46:49.87#ibcon#about to read 4, iclass 11, count 0 2006.162.07:46:49.87#ibcon#read 4, iclass 11, count 0 2006.162.07:46:49.87#ibcon#about to read 5, iclass 11, count 0 2006.162.07:46:49.87#ibcon#read 5, iclass 11, count 0 2006.162.07:46:49.87#ibcon#about to read 6, iclass 11, count 0 2006.162.07:46:49.87#ibcon#read 6, iclass 11, count 0 2006.162.07:46:49.87#ibcon#end of sib2, iclass 11, count 0 2006.162.07:46:49.87#ibcon#*after write, iclass 11, count 0 2006.162.07:46:49.87#ibcon#*before return 0, iclass 11, count 0 2006.162.07:46:49.87#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.162.07:46:49.87#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.162.07:46:49.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.162.07:46:49.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.162.07:46:49.87$vc4f8/va=3,6 2006.162.07:46:49.87#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.162.07:46:49.87#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.162.07:46:49.87#ibcon#ireg 11 cls_cnt 2 2006.162.07:46:49.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.162.07:46:49.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.162.07:46:49.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.162.07:46:49.92#ibcon#enter wrdev, iclass 13, count 2 2006.162.07:46:49.92#ibcon#first serial, iclass 13, count 2 2006.162.07:46:49.92#ibcon#enter sib2, iclass 13, count 2 2006.162.07:46:49.92#ibcon#flushed, iclass 13, count 2 2006.162.07:46:49.92#ibcon#about to write, iclass 13, count 2 2006.162.07:46:49.92#ibcon#wrote, iclass 13, count 2 2006.162.07:46:49.92#ibcon#about to read 3, iclass 13, count 2 2006.162.07:46:49.94#ibcon#read 3, iclass 13, count 2 2006.162.07:46:49.94#ibcon#about to read 4, iclass 13, count 2 2006.162.07:46:49.94#ibcon#read 4, iclass 13, count 2 2006.162.07:46:49.94#ibcon#about to read 5, iclass 13, count 2 2006.162.07:46:49.94#ibcon#read 5, iclass 13, count 2 2006.162.07:46:49.94#ibcon#about to read 6, iclass 13, count 2 2006.162.07:46:49.94#ibcon#read 6, iclass 13, count 2 2006.162.07:46:49.94#ibcon#end of sib2, iclass 13, count 2 2006.162.07:46:49.94#ibcon#*mode == 0, iclass 13, count 2 2006.162.07:46:49.94#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.162.07:46:49.94#ibcon#[25=AT03-06\r\n] 2006.162.07:46:49.94#ibcon#*before write, iclass 13, count 2 2006.162.07:46:49.94#ibcon#enter sib2, iclass 13, count 2 2006.162.07:46:49.94#ibcon#flushed, iclass 13, count 2 2006.162.07:46:49.94#ibcon#about to write, iclass 13, count 2 2006.162.07:46:49.94#ibcon#wrote, iclass 13, count 2 2006.162.07:46:49.94#ibcon#about to read 3, iclass 13, count 2 2006.162.07:46:49.98#ibcon#read 3, iclass 13, count 2 2006.162.07:46:49.98#ibcon#about to read 4, iclass 13, count 2 2006.162.07:46:49.98#ibcon#read 4, iclass 13, count 2 2006.162.07:46:49.98#ibcon#about to read 5, iclass 13, count 2 2006.162.07:46:49.98#ibcon#read 5, iclass 13, count 2 2006.162.07:46:49.98#ibcon#about to read 6, iclass 13, count 2 2006.162.07:46:49.98#ibcon#read 6, iclass 13, count 2 2006.162.07:46:49.98#ibcon#end of sib2, iclass 13, count 2 2006.162.07:46:49.98#ibcon#*after write, iclass 13, count 2 2006.162.07:46:49.98#ibcon#*before return 0, iclass 13, count 2 2006.162.07:46:49.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.162.07:46:49.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.162.07:46:49.98#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.162.07:46:49.98#ibcon#ireg 7 cls_cnt 0 2006.162.07:46:49.98#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.162.07:46:50.10#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.162.07:46:50.10#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.162.07:46:50.10#ibcon#enter wrdev, iclass 13, count 0 2006.162.07:46:50.10#ibcon#first serial, iclass 13, count 0 2006.162.07:46:50.10#ibcon#enter sib2, iclass 13, count 0 2006.162.07:46:50.10#ibcon#flushed, iclass 13, count 0 2006.162.07:46:50.10#ibcon#about to write, iclass 13, count 0 2006.162.07:46:50.10#ibcon#wrote, iclass 13, count 0 2006.162.07:46:50.10#ibcon#about to read 3, iclass 13, count 0 2006.162.07:46:50.12#ibcon#read 3, iclass 13, count 0 2006.162.07:46:50.12#ibcon#about to read 4, iclass 13, count 0 2006.162.07:46:50.12#ibcon#read 4, iclass 13, count 0 2006.162.07:46:50.12#ibcon#about to read 5, iclass 13, count 0 2006.162.07:46:50.12#ibcon#read 5, iclass 13, count 0 2006.162.07:46:50.12#ibcon#about to read 6, iclass 13, count 0 2006.162.07:46:50.12#ibcon#read 6, iclass 13, count 0 2006.162.07:46:50.12#ibcon#end of sib2, iclass 13, count 0 2006.162.07:46:50.12#ibcon#*mode == 0, iclass 13, count 0 2006.162.07:46:50.12#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.162.07:46:50.12#ibcon#[25=USB\r\n] 2006.162.07:46:50.12#ibcon#*before write, iclass 13, count 0 2006.162.07:46:50.12#ibcon#enter sib2, iclass 13, count 0 2006.162.07:46:50.12#ibcon#flushed, iclass 13, count 0 2006.162.07:46:50.12#ibcon#about to write, iclass 13, count 0 2006.162.07:46:50.12#ibcon#wrote, iclass 13, count 0 2006.162.07:46:50.12#ibcon#about to read 3, iclass 13, count 0 2006.162.07:46:50.15#ibcon#read 3, iclass 13, count 0 2006.162.07:46:50.15#ibcon#about to read 4, iclass 13, count 0 2006.162.07:46:50.15#ibcon#read 4, iclass 13, count 0 2006.162.07:46:50.15#ibcon#about to read 5, iclass 13, count 0 2006.162.07:46:50.15#ibcon#read 5, iclass 13, count 0 2006.162.07:46:50.15#ibcon#about to read 6, iclass 13, count 0 2006.162.07:46:50.15#ibcon#read 6, iclass 13, count 0 2006.162.07:46:50.15#ibcon#end of sib2, iclass 13, count 0 2006.162.07:46:50.15#ibcon#*after write, iclass 13, count 0 2006.162.07:46:50.15#ibcon#*before return 0, iclass 13, count 0 2006.162.07:46:50.15#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.162.07:46:50.15#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.162.07:46:50.15#ibcon#about to clear, iclass 13 cls_cnt 0 2006.162.07:46:50.15#ibcon#cleared, iclass 13 cls_cnt 0 2006.162.07:46:50.15$vc4f8/valo=4,832.99 2006.162.07:46:50.15#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.162.07:46:50.15#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.162.07:46:50.15#ibcon#ireg 17 cls_cnt 0 2006.162.07:46:50.15#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:46:50.15#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:46:50.15#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:46:50.15#ibcon#enter wrdev, iclass 15, count 0 2006.162.07:46:50.15#ibcon#first serial, iclass 15, count 0 2006.162.07:46:50.15#ibcon#enter sib2, iclass 15, count 0 2006.162.07:46:50.15#ibcon#flushed, iclass 15, count 0 2006.162.07:46:50.15#ibcon#about to write, iclass 15, count 0 2006.162.07:46:50.15#ibcon#wrote, iclass 15, count 0 2006.162.07:46:50.15#ibcon#about to read 3, iclass 15, count 0 2006.162.07:46:50.17#ibcon#read 3, iclass 15, count 0 2006.162.07:46:50.17#ibcon#about to read 4, iclass 15, count 0 2006.162.07:46:50.17#ibcon#read 4, iclass 15, count 0 2006.162.07:46:50.17#ibcon#about to read 5, iclass 15, count 0 2006.162.07:46:50.17#ibcon#read 5, iclass 15, count 0 2006.162.07:46:50.17#ibcon#about to read 6, iclass 15, count 0 2006.162.07:46:50.17#ibcon#read 6, iclass 15, count 0 2006.162.07:46:50.17#ibcon#end of sib2, iclass 15, count 0 2006.162.07:46:50.17#ibcon#*mode == 0, iclass 15, count 0 2006.162.07:46:50.17#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.162.07:46:50.17#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.07:46:50.17#ibcon#*before write, iclass 15, count 0 2006.162.07:46:50.17#ibcon#enter sib2, iclass 15, count 0 2006.162.07:46:50.17#ibcon#flushed, iclass 15, count 0 2006.162.07:46:50.17#ibcon#about to write, iclass 15, count 0 2006.162.07:46:50.17#ibcon#wrote, iclass 15, count 0 2006.162.07:46:50.17#ibcon#about to read 3, iclass 15, count 0 2006.162.07:46:50.21#ibcon#read 3, iclass 15, count 0 2006.162.07:46:50.21#ibcon#about to read 4, iclass 15, count 0 2006.162.07:46:50.21#ibcon#read 4, iclass 15, count 0 2006.162.07:46:50.21#ibcon#about to read 5, iclass 15, count 0 2006.162.07:46:50.21#ibcon#read 5, iclass 15, count 0 2006.162.07:46:50.21#ibcon#about to read 6, iclass 15, count 0 2006.162.07:46:50.21#ibcon#read 6, iclass 15, count 0 2006.162.07:46:50.21#ibcon#end of sib2, iclass 15, count 0 2006.162.07:46:50.21#ibcon#*after write, iclass 15, count 0 2006.162.07:46:50.21#ibcon#*before return 0, iclass 15, count 0 2006.162.07:46:50.21#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:46:50.21#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:46:50.21#ibcon#about to clear, iclass 15 cls_cnt 0 2006.162.07:46:50.21#ibcon#cleared, iclass 15 cls_cnt 0 2006.162.07:46:50.21$vc4f8/va=4,7 2006.162.07:46:50.21#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.162.07:46:50.21#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.162.07:46:50.21#ibcon#ireg 11 cls_cnt 2 2006.162.07:46:50.21#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:46:50.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:46:50.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:46:50.27#ibcon#enter wrdev, iclass 17, count 2 2006.162.07:46:50.27#ibcon#first serial, iclass 17, count 2 2006.162.07:46:50.27#ibcon#enter sib2, iclass 17, count 2 2006.162.07:46:50.27#ibcon#flushed, iclass 17, count 2 2006.162.07:46:50.27#ibcon#about to write, iclass 17, count 2 2006.162.07:46:50.27#ibcon#wrote, iclass 17, count 2 2006.162.07:46:50.27#ibcon#about to read 3, iclass 17, count 2 2006.162.07:46:50.29#ibcon#read 3, iclass 17, count 2 2006.162.07:46:50.29#ibcon#about to read 4, iclass 17, count 2 2006.162.07:46:50.29#ibcon#read 4, iclass 17, count 2 2006.162.07:46:50.29#ibcon#about to read 5, iclass 17, count 2 2006.162.07:46:50.29#ibcon#read 5, iclass 17, count 2 2006.162.07:46:50.29#ibcon#about to read 6, iclass 17, count 2 2006.162.07:46:50.29#ibcon#read 6, iclass 17, count 2 2006.162.07:46:50.29#ibcon#end of sib2, iclass 17, count 2 2006.162.07:46:50.29#ibcon#*mode == 0, iclass 17, count 2 2006.162.07:46:50.29#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.162.07:46:50.29#ibcon#[25=AT04-07\r\n] 2006.162.07:46:50.29#ibcon#*before write, iclass 17, count 2 2006.162.07:46:50.29#ibcon#enter sib2, iclass 17, count 2 2006.162.07:46:50.29#ibcon#flushed, iclass 17, count 2 2006.162.07:46:50.29#ibcon#about to write, iclass 17, count 2 2006.162.07:46:50.29#ibcon#wrote, iclass 17, count 2 2006.162.07:46:50.29#ibcon#about to read 3, iclass 17, count 2 2006.162.07:46:50.32#ibcon#read 3, iclass 17, count 2 2006.162.07:46:50.32#ibcon#about to read 4, iclass 17, count 2 2006.162.07:46:50.32#ibcon#read 4, iclass 17, count 2 2006.162.07:46:50.32#ibcon#about to read 5, iclass 17, count 2 2006.162.07:46:50.32#ibcon#read 5, iclass 17, count 2 2006.162.07:46:50.32#ibcon#about to read 6, iclass 17, count 2 2006.162.07:46:50.32#ibcon#read 6, iclass 17, count 2 2006.162.07:46:50.32#ibcon#end of sib2, iclass 17, count 2 2006.162.07:46:50.32#ibcon#*after write, iclass 17, count 2 2006.162.07:46:50.32#ibcon#*before return 0, iclass 17, count 2 2006.162.07:46:50.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:46:50.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:46:50.32#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.162.07:46:50.32#ibcon#ireg 7 cls_cnt 0 2006.162.07:46:50.32#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:46:50.44#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:46:50.44#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:46:50.44#ibcon#enter wrdev, iclass 17, count 0 2006.162.07:46:50.44#ibcon#first serial, iclass 17, count 0 2006.162.07:46:50.44#ibcon#enter sib2, iclass 17, count 0 2006.162.07:46:50.44#ibcon#flushed, iclass 17, count 0 2006.162.07:46:50.44#ibcon#about to write, iclass 17, count 0 2006.162.07:46:50.44#ibcon#wrote, iclass 17, count 0 2006.162.07:46:50.44#ibcon#about to read 3, iclass 17, count 0 2006.162.07:46:50.46#ibcon#read 3, iclass 17, count 0 2006.162.07:46:50.46#ibcon#about to read 4, iclass 17, count 0 2006.162.07:46:50.46#ibcon#read 4, iclass 17, count 0 2006.162.07:46:50.46#ibcon#about to read 5, iclass 17, count 0 2006.162.07:46:50.46#ibcon#read 5, iclass 17, count 0 2006.162.07:46:50.46#ibcon#about to read 6, iclass 17, count 0 2006.162.07:46:50.46#ibcon#read 6, iclass 17, count 0 2006.162.07:46:50.46#ibcon#end of sib2, iclass 17, count 0 2006.162.07:46:50.46#ibcon#*mode == 0, iclass 17, count 0 2006.162.07:46:50.46#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.162.07:46:50.46#ibcon#[25=USB\r\n] 2006.162.07:46:50.46#ibcon#*before write, iclass 17, count 0 2006.162.07:46:50.46#ibcon#enter sib2, iclass 17, count 0 2006.162.07:46:50.46#ibcon#flushed, iclass 17, count 0 2006.162.07:46:50.46#ibcon#about to write, iclass 17, count 0 2006.162.07:46:50.46#ibcon#wrote, iclass 17, count 0 2006.162.07:46:50.46#ibcon#about to read 3, iclass 17, count 0 2006.162.07:46:50.49#ibcon#read 3, iclass 17, count 0 2006.162.07:46:50.49#ibcon#about to read 4, iclass 17, count 0 2006.162.07:46:50.49#ibcon#read 4, iclass 17, count 0 2006.162.07:46:50.49#ibcon#about to read 5, iclass 17, count 0 2006.162.07:46:50.49#ibcon#read 5, iclass 17, count 0 2006.162.07:46:50.49#ibcon#about to read 6, iclass 17, count 0 2006.162.07:46:50.49#ibcon#read 6, iclass 17, count 0 2006.162.07:46:50.49#ibcon#end of sib2, iclass 17, count 0 2006.162.07:46:50.49#ibcon#*after write, iclass 17, count 0 2006.162.07:46:50.49#ibcon#*before return 0, iclass 17, count 0 2006.162.07:46:50.49#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:46:50.49#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:46:50.49#ibcon#about to clear, iclass 17 cls_cnt 0 2006.162.07:46:50.49#ibcon#cleared, iclass 17 cls_cnt 0 2006.162.07:46:50.49$vc4f8/valo=5,652.99 2006.162.07:46:50.49#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.162.07:46:50.49#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.162.07:46:50.49#ibcon#ireg 17 cls_cnt 0 2006.162.07:46:50.49#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:46:50.49#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:46:50.49#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:46:50.49#ibcon#enter wrdev, iclass 19, count 0 2006.162.07:46:50.49#ibcon#first serial, iclass 19, count 0 2006.162.07:46:50.49#ibcon#enter sib2, iclass 19, count 0 2006.162.07:46:50.49#ibcon#flushed, iclass 19, count 0 2006.162.07:46:50.49#ibcon#about to write, iclass 19, count 0 2006.162.07:46:50.49#ibcon#wrote, iclass 19, count 0 2006.162.07:46:50.49#ibcon#about to read 3, iclass 19, count 0 2006.162.07:46:50.51#ibcon#read 3, iclass 19, count 0 2006.162.07:46:50.51#ibcon#about to read 4, iclass 19, count 0 2006.162.07:46:50.51#ibcon#read 4, iclass 19, count 0 2006.162.07:46:50.51#ibcon#about to read 5, iclass 19, count 0 2006.162.07:46:50.51#ibcon#read 5, iclass 19, count 0 2006.162.07:46:50.51#ibcon#about to read 6, iclass 19, count 0 2006.162.07:46:50.51#ibcon#read 6, iclass 19, count 0 2006.162.07:46:50.51#ibcon#end of sib2, iclass 19, count 0 2006.162.07:46:50.51#ibcon#*mode == 0, iclass 19, count 0 2006.162.07:46:50.51#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.162.07:46:50.51#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.07:46:50.51#ibcon#*before write, iclass 19, count 0 2006.162.07:46:50.51#ibcon#enter sib2, iclass 19, count 0 2006.162.07:46:50.51#ibcon#flushed, iclass 19, count 0 2006.162.07:46:50.51#ibcon#about to write, iclass 19, count 0 2006.162.07:46:50.51#ibcon#wrote, iclass 19, count 0 2006.162.07:46:50.51#ibcon#about to read 3, iclass 19, count 0 2006.162.07:46:50.55#ibcon#read 3, iclass 19, count 0 2006.162.07:46:50.55#ibcon#about to read 4, iclass 19, count 0 2006.162.07:46:50.55#ibcon#read 4, iclass 19, count 0 2006.162.07:46:50.55#ibcon#about to read 5, iclass 19, count 0 2006.162.07:46:50.55#ibcon#read 5, iclass 19, count 0 2006.162.07:46:50.55#ibcon#about to read 6, iclass 19, count 0 2006.162.07:46:50.55#ibcon#read 6, iclass 19, count 0 2006.162.07:46:50.55#ibcon#end of sib2, iclass 19, count 0 2006.162.07:46:50.55#ibcon#*after write, iclass 19, count 0 2006.162.07:46:50.55#ibcon#*before return 0, iclass 19, count 0 2006.162.07:46:50.55#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:46:50.55#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:46:50.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.162.07:46:50.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.162.07:46:50.55$vc4f8/va=5,7 2006.162.07:46:50.55#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.162.07:46:50.55#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.162.07:46:50.55#ibcon#ireg 11 cls_cnt 2 2006.162.07:46:50.55#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:46:50.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:46:50.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:46:50.61#ibcon#enter wrdev, iclass 21, count 2 2006.162.07:46:50.61#ibcon#first serial, iclass 21, count 2 2006.162.07:46:50.61#ibcon#enter sib2, iclass 21, count 2 2006.162.07:46:50.61#ibcon#flushed, iclass 21, count 2 2006.162.07:46:50.61#ibcon#about to write, iclass 21, count 2 2006.162.07:46:50.61#ibcon#wrote, iclass 21, count 2 2006.162.07:46:50.61#ibcon#about to read 3, iclass 21, count 2 2006.162.07:46:50.63#ibcon#read 3, iclass 21, count 2 2006.162.07:46:50.63#ibcon#about to read 4, iclass 21, count 2 2006.162.07:46:50.63#ibcon#read 4, iclass 21, count 2 2006.162.07:46:50.63#ibcon#about to read 5, iclass 21, count 2 2006.162.07:46:50.63#ibcon#read 5, iclass 21, count 2 2006.162.07:46:50.63#ibcon#about to read 6, iclass 21, count 2 2006.162.07:46:50.63#ibcon#read 6, iclass 21, count 2 2006.162.07:46:50.63#ibcon#end of sib2, iclass 21, count 2 2006.162.07:46:50.63#ibcon#*mode == 0, iclass 21, count 2 2006.162.07:46:50.63#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.162.07:46:50.63#ibcon#[25=AT05-07\r\n] 2006.162.07:46:50.63#ibcon#*before write, iclass 21, count 2 2006.162.07:46:50.63#ibcon#enter sib2, iclass 21, count 2 2006.162.07:46:50.63#ibcon#flushed, iclass 21, count 2 2006.162.07:46:50.63#ibcon#about to write, iclass 21, count 2 2006.162.07:46:50.63#ibcon#wrote, iclass 21, count 2 2006.162.07:46:50.63#ibcon#about to read 3, iclass 21, count 2 2006.162.07:46:50.67#ibcon#read 3, iclass 21, count 2 2006.162.07:46:50.67#ibcon#about to read 4, iclass 21, count 2 2006.162.07:46:50.67#ibcon#read 4, iclass 21, count 2 2006.162.07:46:50.67#ibcon#about to read 5, iclass 21, count 2 2006.162.07:46:50.67#ibcon#read 5, iclass 21, count 2 2006.162.07:46:50.67#ibcon#about to read 6, iclass 21, count 2 2006.162.07:46:50.67#ibcon#read 6, iclass 21, count 2 2006.162.07:46:50.67#ibcon#end of sib2, iclass 21, count 2 2006.162.07:46:50.67#ibcon#*after write, iclass 21, count 2 2006.162.07:46:50.67#ibcon#*before return 0, iclass 21, count 2 2006.162.07:46:50.67#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:46:50.67#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:46:50.67#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.162.07:46:50.67#ibcon#ireg 7 cls_cnt 0 2006.162.07:46:50.67#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:46:50.79#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:46:50.79#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:46:50.79#ibcon#enter wrdev, iclass 21, count 0 2006.162.07:46:50.79#ibcon#first serial, iclass 21, count 0 2006.162.07:46:50.79#ibcon#enter sib2, iclass 21, count 0 2006.162.07:46:50.79#ibcon#flushed, iclass 21, count 0 2006.162.07:46:50.79#ibcon#about to write, iclass 21, count 0 2006.162.07:46:50.79#ibcon#wrote, iclass 21, count 0 2006.162.07:46:50.79#ibcon#about to read 3, iclass 21, count 0 2006.162.07:46:50.81#ibcon#read 3, iclass 21, count 0 2006.162.07:46:50.81#ibcon#about to read 4, iclass 21, count 0 2006.162.07:46:50.81#ibcon#read 4, iclass 21, count 0 2006.162.07:46:50.81#ibcon#about to read 5, iclass 21, count 0 2006.162.07:46:50.81#ibcon#read 5, iclass 21, count 0 2006.162.07:46:50.81#ibcon#about to read 6, iclass 21, count 0 2006.162.07:46:50.81#ibcon#read 6, iclass 21, count 0 2006.162.07:46:50.81#ibcon#end of sib2, iclass 21, count 0 2006.162.07:46:50.81#ibcon#*mode == 0, iclass 21, count 0 2006.162.07:46:50.81#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.162.07:46:50.81#ibcon#[25=USB\r\n] 2006.162.07:46:50.81#ibcon#*before write, iclass 21, count 0 2006.162.07:46:50.81#ibcon#enter sib2, iclass 21, count 0 2006.162.07:46:50.81#ibcon#flushed, iclass 21, count 0 2006.162.07:46:50.81#ibcon#about to write, iclass 21, count 0 2006.162.07:46:50.81#ibcon#wrote, iclass 21, count 0 2006.162.07:46:50.81#ibcon#about to read 3, iclass 21, count 0 2006.162.07:46:50.84#ibcon#read 3, iclass 21, count 0 2006.162.07:46:50.84#ibcon#about to read 4, iclass 21, count 0 2006.162.07:46:50.84#ibcon#read 4, iclass 21, count 0 2006.162.07:46:50.84#ibcon#about to read 5, iclass 21, count 0 2006.162.07:46:50.84#ibcon#read 5, iclass 21, count 0 2006.162.07:46:50.84#ibcon#about to read 6, iclass 21, count 0 2006.162.07:46:50.84#ibcon#read 6, iclass 21, count 0 2006.162.07:46:50.84#ibcon#end of sib2, iclass 21, count 0 2006.162.07:46:50.84#ibcon#*after write, iclass 21, count 0 2006.162.07:46:50.84#ibcon#*before return 0, iclass 21, count 0 2006.162.07:46:50.84#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:46:50.84#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:46:50.84#ibcon#about to clear, iclass 21 cls_cnt 0 2006.162.07:46:50.84#ibcon#cleared, iclass 21 cls_cnt 0 2006.162.07:46:50.84$vc4f8/valo=6,772.99 2006.162.07:46:50.84#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.162.07:46:50.84#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.162.07:46:50.84#ibcon#ireg 17 cls_cnt 0 2006.162.07:46:50.84#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:46:50.84#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:46:50.84#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:46:50.84#ibcon#enter wrdev, iclass 23, count 0 2006.162.07:46:50.84#ibcon#first serial, iclass 23, count 0 2006.162.07:46:50.84#ibcon#enter sib2, iclass 23, count 0 2006.162.07:46:50.84#ibcon#flushed, iclass 23, count 0 2006.162.07:46:50.84#ibcon#about to write, iclass 23, count 0 2006.162.07:46:50.84#ibcon#wrote, iclass 23, count 0 2006.162.07:46:50.84#ibcon#about to read 3, iclass 23, count 0 2006.162.07:46:50.86#ibcon#read 3, iclass 23, count 0 2006.162.07:46:50.86#ibcon#about to read 4, iclass 23, count 0 2006.162.07:46:50.86#ibcon#read 4, iclass 23, count 0 2006.162.07:46:50.86#ibcon#about to read 5, iclass 23, count 0 2006.162.07:46:50.86#ibcon#read 5, iclass 23, count 0 2006.162.07:46:50.86#ibcon#about to read 6, iclass 23, count 0 2006.162.07:46:50.86#ibcon#read 6, iclass 23, count 0 2006.162.07:46:50.86#ibcon#end of sib2, iclass 23, count 0 2006.162.07:46:50.86#ibcon#*mode == 0, iclass 23, count 0 2006.162.07:46:50.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.162.07:46:50.86#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.07:46:50.86#ibcon#*before write, iclass 23, count 0 2006.162.07:46:50.86#ibcon#enter sib2, iclass 23, count 0 2006.162.07:46:50.86#ibcon#flushed, iclass 23, count 0 2006.162.07:46:50.86#ibcon#about to write, iclass 23, count 0 2006.162.07:46:50.86#ibcon#wrote, iclass 23, count 0 2006.162.07:46:50.86#ibcon#about to read 3, iclass 23, count 0 2006.162.07:46:50.90#ibcon#read 3, iclass 23, count 0 2006.162.07:46:50.90#ibcon#about to read 4, iclass 23, count 0 2006.162.07:46:50.90#ibcon#read 4, iclass 23, count 0 2006.162.07:46:50.90#ibcon#about to read 5, iclass 23, count 0 2006.162.07:46:50.90#ibcon#read 5, iclass 23, count 0 2006.162.07:46:50.90#ibcon#about to read 6, iclass 23, count 0 2006.162.07:46:50.90#ibcon#read 6, iclass 23, count 0 2006.162.07:46:50.90#ibcon#end of sib2, iclass 23, count 0 2006.162.07:46:50.90#ibcon#*after write, iclass 23, count 0 2006.162.07:46:50.90#ibcon#*before return 0, iclass 23, count 0 2006.162.07:46:50.90#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:46:50.90#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:46:50.90#ibcon#about to clear, iclass 23 cls_cnt 0 2006.162.07:46:50.90#ibcon#cleared, iclass 23 cls_cnt 0 2006.162.07:46:50.90$vc4f8/va=6,6 2006.162.07:46:50.90#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.162.07:46:50.90#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.162.07:46:50.90#ibcon#ireg 11 cls_cnt 2 2006.162.07:46:50.90#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.162.07:46:50.96#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.162.07:46:50.96#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.162.07:46:50.96#ibcon#enter wrdev, iclass 25, count 2 2006.162.07:46:50.96#ibcon#first serial, iclass 25, count 2 2006.162.07:46:50.96#ibcon#enter sib2, iclass 25, count 2 2006.162.07:46:50.96#ibcon#flushed, iclass 25, count 2 2006.162.07:46:50.96#ibcon#about to write, iclass 25, count 2 2006.162.07:46:50.96#ibcon#wrote, iclass 25, count 2 2006.162.07:46:50.96#ibcon#about to read 3, iclass 25, count 2 2006.162.07:46:50.98#ibcon#read 3, iclass 25, count 2 2006.162.07:46:50.98#ibcon#about to read 4, iclass 25, count 2 2006.162.07:46:50.98#ibcon#read 4, iclass 25, count 2 2006.162.07:46:50.98#ibcon#about to read 5, iclass 25, count 2 2006.162.07:46:50.98#ibcon#read 5, iclass 25, count 2 2006.162.07:46:50.98#ibcon#about to read 6, iclass 25, count 2 2006.162.07:46:50.98#ibcon#read 6, iclass 25, count 2 2006.162.07:46:50.98#ibcon#end of sib2, iclass 25, count 2 2006.162.07:46:50.98#ibcon#*mode == 0, iclass 25, count 2 2006.162.07:46:50.98#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.162.07:46:50.98#ibcon#[25=AT06-06\r\n] 2006.162.07:46:50.98#ibcon#*before write, iclass 25, count 2 2006.162.07:46:50.98#ibcon#enter sib2, iclass 25, count 2 2006.162.07:46:50.98#ibcon#flushed, iclass 25, count 2 2006.162.07:46:50.98#ibcon#about to write, iclass 25, count 2 2006.162.07:46:50.98#ibcon#wrote, iclass 25, count 2 2006.162.07:46:50.98#ibcon#about to read 3, iclass 25, count 2 2006.162.07:46:51.01#ibcon#read 3, iclass 25, count 2 2006.162.07:46:51.01#ibcon#about to read 4, iclass 25, count 2 2006.162.07:46:51.01#ibcon#read 4, iclass 25, count 2 2006.162.07:46:51.01#ibcon#about to read 5, iclass 25, count 2 2006.162.07:46:51.01#ibcon#read 5, iclass 25, count 2 2006.162.07:46:51.01#ibcon#about to read 6, iclass 25, count 2 2006.162.07:46:51.01#ibcon#read 6, iclass 25, count 2 2006.162.07:46:51.01#ibcon#end of sib2, iclass 25, count 2 2006.162.07:46:51.01#ibcon#*after write, iclass 25, count 2 2006.162.07:46:51.01#ibcon#*before return 0, iclass 25, count 2 2006.162.07:46:51.01#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.162.07:46:51.01#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.162.07:46:51.01#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.162.07:46:51.01#ibcon#ireg 7 cls_cnt 0 2006.162.07:46:51.01#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.162.07:46:51.13#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.162.07:46:51.13#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.162.07:46:51.13#ibcon#enter wrdev, iclass 25, count 0 2006.162.07:46:51.13#ibcon#first serial, iclass 25, count 0 2006.162.07:46:51.13#ibcon#enter sib2, iclass 25, count 0 2006.162.07:46:51.13#ibcon#flushed, iclass 25, count 0 2006.162.07:46:51.13#ibcon#about to write, iclass 25, count 0 2006.162.07:46:51.13#ibcon#wrote, iclass 25, count 0 2006.162.07:46:51.13#ibcon#about to read 3, iclass 25, count 0 2006.162.07:46:51.15#ibcon#read 3, iclass 25, count 0 2006.162.07:46:51.15#ibcon#about to read 4, iclass 25, count 0 2006.162.07:46:51.15#ibcon#read 4, iclass 25, count 0 2006.162.07:46:51.15#ibcon#about to read 5, iclass 25, count 0 2006.162.07:46:51.15#ibcon#read 5, iclass 25, count 0 2006.162.07:46:51.15#ibcon#about to read 6, iclass 25, count 0 2006.162.07:46:51.15#ibcon#read 6, iclass 25, count 0 2006.162.07:46:51.15#ibcon#end of sib2, iclass 25, count 0 2006.162.07:46:51.15#ibcon#*mode == 0, iclass 25, count 0 2006.162.07:46:51.15#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.162.07:46:51.15#ibcon#[25=USB\r\n] 2006.162.07:46:51.15#ibcon#*before write, iclass 25, count 0 2006.162.07:46:51.15#ibcon#enter sib2, iclass 25, count 0 2006.162.07:46:51.15#ibcon#flushed, iclass 25, count 0 2006.162.07:46:51.15#ibcon#about to write, iclass 25, count 0 2006.162.07:46:51.15#ibcon#wrote, iclass 25, count 0 2006.162.07:46:51.15#ibcon#about to read 3, iclass 25, count 0 2006.162.07:46:51.18#ibcon#read 3, iclass 25, count 0 2006.162.07:46:51.18#ibcon#about to read 4, iclass 25, count 0 2006.162.07:46:51.18#ibcon#read 4, iclass 25, count 0 2006.162.07:46:51.18#ibcon#about to read 5, iclass 25, count 0 2006.162.07:46:51.18#ibcon#read 5, iclass 25, count 0 2006.162.07:46:51.18#ibcon#about to read 6, iclass 25, count 0 2006.162.07:46:51.18#ibcon#read 6, iclass 25, count 0 2006.162.07:46:51.18#ibcon#end of sib2, iclass 25, count 0 2006.162.07:46:51.18#ibcon#*after write, iclass 25, count 0 2006.162.07:46:51.18#ibcon#*before return 0, iclass 25, count 0 2006.162.07:46:51.18#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.162.07:46:51.18#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.162.07:46:51.18#ibcon#about to clear, iclass 25 cls_cnt 0 2006.162.07:46:51.18#ibcon#cleared, iclass 25 cls_cnt 0 2006.162.07:46:51.18$vc4f8/valo=7,832.99 2006.162.07:46:51.18#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.162.07:46:51.18#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.162.07:46:51.18#ibcon#ireg 17 cls_cnt 0 2006.162.07:46:51.18#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:46:51.18#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:46:51.18#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:46:51.18#ibcon#enter wrdev, iclass 27, count 0 2006.162.07:46:51.18#ibcon#first serial, iclass 27, count 0 2006.162.07:46:51.18#ibcon#enter sib2, iclass 27, count 0 2006.162.07:46:51.18#ibcon#flushed, iclass 27, count 0 2006.162.07:46:51.18#ibcon#about to write, iclass 27, count 0 2006.162.07:46:51.18#ibcon#wrote, iclass 27, count 0 2006.162.07:46:51.18#ibcon#about to read 3, iclass 27, count 0 2006.162.07:46:51.20#ibcon#read 3, iclass 27, count 0 2006.162.07:46:51.20#ibcon#about to read 4, iclass 27, count 0 2006.162.07:46:51.20#ibcon#read 4, iclass 27, count 0 2006.162.07:46:51.20#ibcon#about to read 5, iclass 27, count 0 2006.162.07:46:51.20#ibcon#read 5, iclass 27, count 0 2006.162.07:46:51.20#ibcon#about to read 6, iclass 27, count 0 2006.162.07:46:51.20#ibcon#read 6, iclass 27, count 0 2006.162.07:46:51.20#ibcon#end of sib2, iclass 27, count 0 2006.162.07:46:51.20#ibcon#*mode == 0, iclass 27, count 0 2006.162.07:46:51.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.162.07:46:51.20#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.07:46:51.20#ibcon#*before write, iclass 27, count 0 2006.162.07:46:51.20#ibcon#enter sib2, iclass 27, count 0 2006.162.07:46:51.20#ibcon#flushed, iclass 27, count 0 2006.162.07:46:51.20#ibcon#about to write, iclass 27, count 0 2006.162.07:46:51.20#ibcon#wrote, iclass 27, count 0 2006.162.07:46:51.20#ibcon#about to read 3, iclass 27, count 0 2006.162.07:46:51.24#ibcon#read 3, iclass 27, count 0 2006.162.07:46:51.24#ibcon#about to read 4, iclass 27, count 0 2006.162.07:46:51.24#ibcon#read 4, iclass 27, count 0 2006.162.07:46:51.24#ibcon#about to read 5, iclass 27, count 0 2006.162.07:46:51.24#ibcon#read 5, iclass 27, count 0 2006.162.07:46:51.24#ibcon#about to read 6, iclass 27, count 0 2006.162.07:46:51.24#ibcon#read 6, iclass 27, count 0 2006.162.07:46:51.24#ibcon#end of sib2, iclass 27, count 0 2006.162.07:46:51.24#ibcon#*after write, iclass 27, count 0 2006.162.07:46:51.24#ibcon#*before return 0, iclass 27, count 0 2006.162.07:46:51.24#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:46:51.24#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:46:51.24#ibcon#about to clear, iclass 27 cls_cnt 0 2006.162.07:46:51.24#ibcon#cleared, iclass 27 cls_cnt 0 2006.162.07:46:51.24$vc4f8/va=7,6 2006.162.07:46:51.24#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.162.07:46:51.24#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.162.07:46:51.24#ibcon#ireg 11 cls_cnt 2 2006.162.07:46:51.24#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.162.07:46:51.30#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.162.07:46:51.30#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.162.07:46:51.30#ibcon#enter wrdev, iclass 29, count 2 2006.162.07:46:51.30#ibcon#first serial, iclass 29, count 2 2006.162.07:46:51.30#ibcon#enter sib2, iclass 29, count 2 2006.162.07:46:51.30#ibcon#flushed, iclass 29, count 2 2006.162.07:46:51.30#ibcon#about to write, iclass 29, count 2 2006.162.07:46:51.30#ibcon#wrote, iclass 29, count 2 2006.162.07:46:51.30#ibcon#about to read 3, iclass 29, count 2 2006.162.07:46:51.32#ibcon#read 3, iclass 29, count 2 2006.162.07:46:51.32#ibcon#about to read 4, iclass 29, count 2 2006.162.07:46:51.32#ibcon#read 4, iclass 29, count 2 2006.162.07:46:51.32#ibcon#about to read 5, iclass 29, count 2 2006.162.07:46:51.32#ibcon#read 5, iclass 29, count 2 2006.162.07:46:51.32#ibcon#about to read 6, iclass 29, count 2 2006.162.07:46:51.32#ibcon#read 6, iclass 29, count 2 2006.162.07:46:51.32#ibcon#end of sib2, iclass 29, count 2 2006.162.07:46:51.32#ibcon#*mode == 0, iclass 29, count 2 2006.162.07:46:51.32#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.162.07:46:51.32#ibcon#[25=AT07-06\r\n] 2006.162.07:46:51.32#ibcon#*before write, iclass 29, count 2 2006.162.07:46:51.32#ibcon#enter sib2, iclass 29, count 2 2006.162.07:46:51.32#ibcon#flushed, iclass 29, count 2 2006.162.07:46:51.32#ibcon#about to write, iclass 29, count 2 2006.162.07:46:51.32#ibcon#wrote, iclass 29, count 2 2006.162.07:46:51.32#ibcon#about to read 3, iclass 29, count 2 2006.162.07:46:51.36#ibcon#read 3, iclass 29, count 2 2006.162.07:46:51.36#ibcon#about to read 4, iclass 29, count 2 2006.162.07:46:51.36#ibcon#read 4, iclass 29, count 2 2006.162.07:46:51.36#ibcon#about to read 5, iclass 29, count 2 2006.162.07:46:51.36#ibcon#read 5, iclass 29, count 2 2006.162.07:46:51.36#ibcon#about to read 6, iclass 29, count 2 2006.162.07:46:51.36#ibcon#read 6, iclass 29, count 2 2006.162.07:46:51.36#ibcon#end of sib2, iclass 29, count 2 2006.162.07:46:51.36#ibcon#*after write, iclass 29, count 2 2006.162.07:46:51.36#ibcon#*before return 0, iclass 29, count 2 2006.162.07:46:51.36#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.162.07:46:51.36#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.162.07:46:51.36#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.162.07:46:51.36#ibcon#ireg 7 cls_cnt 0 2006.162.07:46:51.36#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.162.07:46:51.48#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.162.07:46:51.48#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.162.07:46:51.48#ibcon#enter wrdev, iclass 29, count 0 2006.162.07:46:51.48#ibcon#first serial, iclass 29, count 0 2006.162.07:46:51.48#ibcon#enter sib2, iclass 29, count 0 2006.162.07:46:51.48#ibcon#flushed, iclass 29, count 0 2006.162.07:46:51.48#ibcon#about to write, iclass 29, count 0 2006.162.07:46:51.48#ibcon#wrote, iclass 29, count 0 2006.162.07:46:51.48#ibcon#about to read 3, iclass 29, count 0 2006.162.07:46:51.50#ibcon#read 3, iclass 29, count 0 2006.162.07:46:51.50#ibcon#about to read 4, iclass 29, count 0 2006.162.07:46:51.50#ibcon#read 4, iclass 29, count 0 2006.162.07:46:51.50#ibcon#about to read 5, iclass 29, count 0 2006.162.07:46:51.50#ibcon#read 5, iclass 29, count 0 2006.162.07:46:51.50#ibcon#about to read 6, iclass 29, count 0 2006.162.07:46:51.50#ibcon#read 6, iclass 29, count 0 2006.162.07:46:51.50#ibcon#end of sib2, iclass 29, count 0 2006.162.07:46:51.50#ibcon#*mode == 0, iclass 29, count 0 2006.162.07:46:51.50#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.162.07:46:51.50#ibcon#[25=USB\r\n] 2006.162.07:46:51.50#ibcon#*before write, iclass 29, count 0 2006.162.07:46:51.50#ibcon#enter sib2, iclass 29, count 0 2006.162.07:46:51.50#ibcon#flushed, iclass 29, count 0 2006.162.07:46:51.50#ibcon#about to write, iclass 29, count 0 2006.162.07:46:51.50#ibcon#wrote, iclass 29, count 0 2006.162.07:46:51.50#ibcon#about to read 3, iclass 29, count 0 2006.162.07:46:51.53#ibcon#read 3, iclass 29, count 0 2006.162.07:46:51.53#ibcon#about to read 4, iclass 29, count 0 2006.162.07:46:51.53#ibcon#read 4, iclass 29, count 0 2006.162.07:46:51.53#ibcon#about to read 5, iclass 29, count 0 2006.162.07:46:51.53#ibcon#read 5, iclass 29, count 0 2006.162.07:46:51.53#ibcon#about to read 6, iclass 29, count 0 2006.162.07:46:51.53#ibcon#read 6, iclass 29, count 0 2006.162.07:46:51.53#ibcon#end of sib2, iclass 29, count 0 2006.162.07:46:51.53#ibcon#*after write, iclass 29, count 0 2006.162.07:46:51.53#ibcon#*before return 0, iclass 29, count 0 2006.162.07:46:51.53#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.162.07:46:51.53#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.162.07:46:51.53#ibcon#about to clear, iclass 29 cls_cnt 0 2006.162.07:46:51.53#ibcon#cleared, iclass 29 cls_cnt 0 2006.162.07:46:51.53$vc4f8/valo=8,852.99 2006.162.07:46:51.53#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.162.07:46:51.53#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.162.07:46:51.53#ibcon#ireg 17 cls_cnt 0 2006.162.07:46:51.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.162.07:46:51.53#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.162.07:46:51.53#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.162.07:46:51.53#ibcon#enter wrdev, iclass 31, count 0 2006.162.07:46:51.53#ibcon#first serial, iclass 31, count 0 2006.162.07:46:51.53#ibcon#enter sib2, iclass 31, count 0 2006.162.07:46:51.53#ibcon#flushed, iclass 31, count 0 2006.162.07:46:51.53#ibcon#about to write, iclass 31, count 0 2006.162.07:46:51.53#ibcon#wrote, iclass 31, count 0 2006.162.07:46:51.53#ibcon#about to read 3, iclass 31, count 0 2006.162.07:46:51.55#ibcon#read 3, iclass 31, count 0 2006.162.07:46:51.55#ibcon#about to read 4, iclass 31, count 0 2006.162.07:46:51.55#ibcon#read 4, iclass 31, count 0 2006.162.07:46:51.55#ibcon#about to read 5, iclass 31, count 0 2006.162.07:46:51.55#ibcon#read 5, iclass 31, count 0 2006.162.07:46:51.55#ibcon#about to read 6, iclass 31, count 0 2006.162.07:46:51.55#ibcon#read 6, iclass 31, count 0 2006.162.07:46:51.55#ibcon#end of sib2, iclass 31, count 0 2006.162.07:46:51.55#ibcon#*mode == 0, iclass 31, count 0 2006.162.07:46:51.55#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.162.07:46:51.55#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.07:46:51.55#ibcon#*before write, iclass 31, count 0 2006.162.07:46:51.55#ibcon#enter sib2, iclass 31, count 0 2006.162.07:46:51.55#ibcon#flushed, iclass 31, count 0 2006.162.07:46:51.55#ibcon#about to write, iclass 31, count 0 2006.162.07:46:51.55#ibcon#wrote, iclass 31, count 0 2006.162.07:46:51.55#ibcon#about to read 3, iclass 31, count 0 2006.162.07:46:51.59#ibcon#read 3, iclass 31, count 0 2006.162.07:46:51.59#ibcon#about to read 4, iclass 31, count 0 2006.162.07:46:51.59#ibcon#read 4, iclass 31, count 0 2006.162.07:46:51.59#ibcon#about to read 5, iclass 31, count 0 2006.162.07:46:51.59#ibcon#read 5, iclass 31, count 0 2006.162.07:46:51.59#ibcon#about to read 6, iclass 31, count 0 2006.162.07:46:51.59#ibcon#read 6, iclass 31, count 0 2006.162.07:46:51.59#ibcon#end of sib2, iclass 31, count 0 2006.162.07:46:51.59#ibcon#*after write, iclass 31, count 0 2006.162.07:46:51.59#ibcon#*before return 0, iclass 31, count 0 2006.162.07:46:51.59#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.162.07:46:51.59#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.162.07:46:51.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.162.07:46:51.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.162.07:46:51.59$vc4f8/va=8,7 2006.162.07:46:51.59#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.162.07:46:51.59#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.162.07:46:51.59#ibcon#ireg 11 cls_cnt 2 2006.162.07:46:51.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.162.07:46:51.65#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.162.07:46:51.65#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.162.07:46:51.65#ibcon#enter wrdev, iclass 33, count 2 2006.162.07:46:51.65#ibcon#first serial, iclass 33, count 2 2006.162.07:46:51.65#ibcon#enter sib2, iclass 33, count 2 2006.162.07:46:51.65#ibcon#flushed, iclass 33, count 2 2006.162.07:46:51.65#ibcon#about to write, iclass 33, count 2 2006.162.07:46:51.65#ibcon#wrote, iclass 33, count 2 2006.162.07:46:51.65#ibcon#about to read 3, iclass 33, count 2 2006.162.07:46:51.67#ibcon#read 3, iclass 33, count 2 2006.162.07:46:51.67#ibcon#about to read 4, iclass 33, count 2 2006.162.07:46:51.67#ibcon#read 4, iclass 33, count 2 2006.162.07:46:51.67#ibcon#about to read 5, iclass 33, count 2 2006.162.07:46:51.67#ibcon#read 5, iclass 33, count 2 2006.162.07:46:51.67#ibcon#about to read 6, iclass 33, count 2 2006.162.07:46:51.67#ibcon#read 6, iclass 33, count 2 2006.162.07:46:51.67#ibcon#end of sib2, iclass 33, count 2 2006.162.07:46:51.67#ibcon#*mode == 0, iclass 33, count 2 2006.162.07:46:51.67#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.162.07:46:51.67#ibcon#[25=AT08-07\r\n] 2006.162.07:46:51.67#ibcon#*before write, iclass 33, count 2 2006.162.07:46:51.67#ibcon#enter sib2, iclass 33, count 2 2006.162.07:46:51.67#ibcon#flushed, iclass 33, count 2 2006.162.07:46:51.67#ibcon#about to write, iclass 33, count 2 2006.162.07:46:51.67#ibcon#wrote, iclass 33, count 2 2006.162.07:46:51.67#ibcon#about to read 3, iclass 33, count 2 2006.162.07:46:51.70#ibcon#read 3, iclass 33, count 2 2006.162.07:46:51.70#ibcon#about to read 4, iclass 33, count 2 2006.162.07:46:51.70#ibcon#read 4, iclass 33, count 2 2006.162.07:46:51.70#ibcon#about to read 5, iclass 33, count 2 2006.162.07:46:51.70#ibcon#read 5, iclass 33, count 2 2006.162.07:46:51.70#ibcon#about to read 6, iclass 33, count 2 2006.162.07:46:51.70#ibcon#read 6, iclass 33, count 2 2006.162.07:46:51.70#ibcon#end of sib2, iclass 33, count 2 2006.162.07:46:51.70#ibcon#*after write, iclass 33, count 2 2006.162.07:46:51.70#ibcon#*before return 0, iclass 33, count 2 2006.162.07:46:51.70#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.162.07:46:51.70#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.162.07:46:51.70#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.162.07:46:51.70#ibcon#ireg 7 cls_cnt 0 2006.162.07:46:51.70#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.162.07:46:51.82#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.162.07:46:51.82#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.162.07:46:51.82#ibcon#enter wrdev, iclass 33, count 0 2006.162.07:46:51.82#ibcon#first serial, iclass 33, count 0 2006.162.07:46:51.82#ibcon#enter sib2, iclass 33, count 0 2006.162.07:46:51.82#ibcon#flushed, iclass 33, count 0 2006.162.07:46:51.82#ibcon#about to write, iclass 33, count 0 2006.162.07:46:51.82#ibcon#wrote, iclass 33, count 0 2006.162.07:46:51.82#ibcon#about to read 3, iclass 33, count 0 2006.162.07:46:51.84#ibcon#read 3, iclass 33, count 0 2006.162.07:46:51.84#ibcon#about to read 4, iclass 33, count 0 2006.162.07:46:51.84#ibcon#read 4, iclass 33, count 0 2006.162.07:46:51.84#ibcon#about to read 5, iclass 33, count 0 2006.162.07:46:51.84#ibcon#read 5, iclass 33, count 0 2006.162.07:46:51.84#ibcon#about to read 6, iclass 33, count 0 2006.162.07:46:51.84#ibcon#read 6, iclass 33, count 0 2006.162.07:46:51.84#ibcon#end of sib2, iclass 33, count 0 2006.162.07:46:51.84#ibcon#*mode == 0, iclass 33, count 0 2006.162.07:46:51.84#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.162.07:46:51.84#ibcon#[25=USB\r\n] 2006.162.07:46:51.84#ibcon#*before write, iclass 33, count 0 2006.162.07:46:51.84#ibcon#enter sib2, iclass 33, count 0 2006.162.07:46:51.84#ibcon#flushed, iclass 33, count 0 2006.162.07:46:51.84#ibcon#about to write, iclass 33, count 0 2006.162.07:46:51.84#ibcon#wrote, iclass 33, count 0 2006.162.07:46:51.84#ibcon#about to read 3, iclass 33, count 0 2006.162.07:46:51.87#ibcon#read 3, iclass 33, count 0 2006.162.07:46:51.87#ibcon#about to read 4, iclass 33, count 0 2006.162.07:46:51.87#ibcon#read 4, iclass 33, count 0 2006.162.07:46:51.87#ibcon#about to read 5, iclass 33, count 0 2006.162.07:46:51.87#ibcon#read 5, iclass 33, count 0 2006.162.07:46:51.87#ibcon#about to read 6, iclass 33, count 0 2006.162.07:46:51.87#ibcon#read 6, iclass 33, count 0 2006.162.07:46:51.87#ibcon#end of sib2, iclass 33, count 0 2006.162.07:46:51.87#ibcon#*after write, iclass 33, count 0 2006.162.07:46:51.87#ibcon#*before return 0, iclass 33, count 0 2006.162.07:46:51.87#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.162.07:46:51.87#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.162.07:46:51.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.162.07:46:51.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.162.07:46:51.87$vc4f8/vblo=1,632.99 2006.162.07:46:51.87#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.162.07:46:51.87#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.162.07:46:51.87#ibcon#ireg 17 cls_cnt 0 2006.162.07:46:51.87#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.162.07:46:51.87#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.162.07:46:51.87#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.162.07:46:51.87#ibcon#enter wrdev, iclass 35, count 0 2006.162.07:46:51.87#ibcon#first serial, iclass 35, count 0 2006.162.07:46:51.87#ibcon#enter sib2, iclass 35, count 0 2006.162.07:46:51.87#ibcon#flushed, iclass 35, count 0 2006.162.07:46:51.87#ibcon#about to write, iclass 35, count 0 2006.162.07:46:51.87#ibcon#wrote, iclass 35, count 0 2006.162.07:46:51.87#ibcon#about to read 3, iclass 35, count 0 2006.162.07:46:51.89#ibcon#read 3, iclass 35, count 0 2006.162.07:46:51.89#ibcon#about to read 4, iclass 35, count 0 2006.162.07:46:51.89#ibcon#read 4, iclass 35, count 0 2006.162.07:46:51.89#ibcon#about to read 5, iclass 35, count 0 2006.162.07:46:51.89#ibcon#read 5, iclass 35, count 0 2006.162.07:46:51.89#ibcon#about to read 6, iclass 35, count 0 2006.162.07:46:51.89#ibcon#read 6, iclass 35, count 0 2006.162.07:46:51.89#ibcon#end of sib2, iclass 35, count 0 2006.162.07:46:51.89#ibcon#*mode == 0, iclass 35, count 0 2006.162.07:46:51.89#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.162.07:46:51.89#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.07:46:51.89#ibcon#*before write, iclass 35, count 0 2006.162.07:46:51.89#ibcon#enter sib2, iclass 35, count 0 2006.162.07:46:51.89#ibcon#flushed, iclass 35, count 0 2006.162.07:46:51.89#ibcon#about to write, iclass 35, count 0 2006.162.07:46:51.89#ibcon#wrote, iclass 35, count 0 2006.162.07:46:51.89#ibcon#about to read 3, iclass 35, count 0 2006.162.07:46:51.93#ibcon#read 3, iclass 35, count 0 2006.162.07:46:51.93#ibcon#about to read 4, iclass 35, count 0 2006.162.07:46:51.93#ibcon#read 4, iclass 35, count 0 2006.162.07:46:51.93#ibcon#about to read 5, iclass 35, count 0 2006.162.07:46:51.93#ibcon#read 5, iclass 35, count 0 2006.162.07:46:51.93#ibcon#about to read 6, iclass 35, count 0 2006.162.07:46:51.93#ibcon#read 6, iclass 35, count 0 2006.162.07:46:51.93#ibcon#end of sib2, iclass 35, count 0 2006.162.07:46:51.93#ibcon#*after write, iclass 35, count 0 2006.162.07:46:51.93#ibcon#*before return 0, iclass 35, count 0 2006.162.07:46:51.93#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.162.07:46:51.93#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.162.07:46:51.93#ibcon#about to clear, iclass 35 cls_cnt 0 2006.162.07:46:51.93#ibcon#cleared, iclass 35 cls_cnt 0 2006.162.07:46:51.93$vc4f8/vb=1,4 2006.162.07:46:51.93#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.162.07:46:51.93#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.162.07:46:51.93#ibcon#ireg 11 cls_cnt 2 2006.162.07:46:51.93#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.162.07:46:51.93#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.162.07:46:51.93#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.162.07:46:51.93#ibcon#enter wrdev, iclass 37, count 2 2006.162.07:46:51.93#ibcon#first serial, iclass 37, count 2 2006.162.07:46:51.93#ibcon#enter sib2, iclass 37, count 2 2006.162.07:46:51.93#ibcon#flushed, iclass 37, count 2 2006.162.07:46:51.93#ibcon#about to write, iclass 37, count 2 2006.162.07:46:51.93#ibcon#wrote, iclass 37, count 2 2006.162.07:46:51.93#ibcon#about to read 3, iclass 37, count 2 2006.162.07:46:51.95#ibcon#read 3, iclass 37, count 2 2006.162.07:46:51.95#ibcon#about to read 4, iclass 37, count 2 2006.162.07:46:51.95#ibcon#read 4, iclass 37, count 2 2006.162.07:46:51.95#ibcon#about to read 5, iclass 37, count 2 2006.162.07:46:51.95#ibcon#read 5, iclass 37, count 2 2006.162.07:46:51.95#ibcon#about to read 6, iclass 37, count 2 2006.162.07:46:51.95#ibcon#read 6, iclass 37, count 2 2006.162.07:46:51.95#ibcon#end of sib2, iclass 37, count 2 2006.162.07:46:51.95#ibcon#*mode == 0, iclass 37, count 2 2006.162.07:46:51.95#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.162.07:46:51.95#ibcon#[27=AT01-04\r\n] 2006.162.07:46:51.95#ibcon#*before write, iclass 37, count 2 2006.162.07:46:51.95#ibcon#enter sib2, iclass 37, count 2 2006.162.07:46:51.95#ibcon#flushed, iclass 37, count 2 2006.162.07:46:51.95#ibcon#about to write, iclass 37, count 2 2006.162.07:46:51.95#ibcon#wrote, iclass 37, count 2 2006.162.07:46:51.95#ibcon#about to read 3, iclass 37, count 2 2006.162.07:46:51.98#ibcon#read 3, iclass 37, count 2 2006.162.07:46:51.98#ibcon#about to read 4, iclass 37, count 2 2006.162.07:46:51.98#ibcon#read 4, iclass 37, count 2 2006.162.07:46:51.98#ibcon#about to read 5, iclass 37, count 2 2006.162.07:46:51.98#ibcon#read 5, iclass 37, count 2 2006.162.07:46:51.98#ibcon#about to read 6, iclass 37, count 2 2006.162.07:46:51.98#ibcon#read 6, iclass 37, count 2 2006.162.07:46:51.98#ibcon#end of sib2, iclass 37, count 2 2006.162.07:46:51.98#ibcon#*after write, iclass 37, count 2 2006.162.07:46:51.98#ibcon#*before return 0, iclass 37, count 2 2006.162.07:46:51.98#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.162.07:46:51.98#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.162.07:46:51.98#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.162.07:46:51.98#ibcon#ireg 7 cls_cnt 0 2006.162.07:46:51.98#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.162.07:46:52.11#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.162.07:46:52.11#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.162.07:46:52.11#ibcon#enter wrdev, iclass 37, count 0 2006.162.07:46:52.11#ibcon#first serial, iclass 37, count 0 2006.162.07:46:52.11#ibcon#enter sib2, iclass 37, count 0 2006.162.07:46:52.11#ibcon#flushed, iclass 37, count 0 2006.162.07:46:52.11#ibcon#about to write, iclass 37, count 0 2006.162.07:46:52.11#ibcon#wrote, iclass 37, count 0 2006.162.07:46:52.11#ibcon#about to read 3, iclass 37, count 0 2006.162.07:46:52.13#ibcon#read 3, iclass 37, count 0 2006.162.07:46:52.13#ibcon#about to read 4, iclass 37, count 0 2006.162.07:46:52.13#ibcon#read 4, iclass 37, count 0 2006.162.07:46:52.13#ibcon#about to read 5, iclass 37, count 0 2006.162.07:46:52.13#ibcon#read 5, iclass 37, count 0 2006.162.07:46:52.13#ibcon#about to read 6, iclass 37, count 0 2006.162.07:46:52.13#ibcon#read 6, iclass 37, count 0 2006.162.07:46:52.13#ibcon#end of sib2, iclass 37, count 0 2006.162.07:46:52.13#ibcon#*mode == 0, iclass 37, count 0 2006.162.07:46:52.13#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.162.07:46:52.13#ibcon#[27=USB\r\n] 2006.162.07:46:52.13#ibcon#*before write, iclass 37, count 0 2006.162.07:46:52.13#ibcon#enter sib2, iclass 37, count 0 2006.162.07:46:52.13#ibcon#flushed, iclass 37, count 0 2006.162.07:46:52.13#ibcon#about to write, iclass 37, count 0 2006.162.07:46:52.13#ibcon#wrote, iclass 37, count 0 2006.162.07:46:52.13#ibcon#about to read 3, iclass 37, count 0 2006.162.07:46:52.16#ibcon#read 3, iclass 37, count 0 2006.162.07:46:52.16#ibcon#about to read 4, iclass 37, count 0 2006.162.07:46:52.16#ibcon#read 4, iclass 37, count 0 2006.162.07:46:52.16#ibcon#about to read 5, iclass 37, count 0 2006.162.07:46:52.16#ibcon#read 5, iclass 37, count 0 2006.162.07:46:52.16#ibcon#about to read 6, iclass 37, count 0 2006.162.07:46:52.16#ibcon#read 6, iclass 37, count 0 2006.162.07:46:52.16#ibcon#end of sib2, iclass 37, count 0 2006.162.07:46:52.16#ibcon#*after write, iclass 37, count 0 2006.162.07:46:52.16#ibcon#*before return 0, iclass 37, count 0 2006.162.07:46:52.16#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.162.07:46:52.16#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.162.07:46:52.16#ibcon#about to clear, iclass 37 cls_cnt 0 2006.162.07:46:52.16#ibcon#cleared, iclass 37 cls_cnt 0 2006.162.07:46:52.16$vc4f8/vblo=2,640.99 2006.162.07:46:52.16#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.162.07:46:52.16#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.162.07:46:52.16#ibcon#ireg 17 cls_cnt 0 2006.162.07:46:52.16#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.162.07:46:52.16#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.162.07:46:52.16#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.162.07:46:52.16#ibcon#enter wrdev, iclass 39, count 0 2006.162.07:46:52.16#ibcon#first serial, iclass 39, count 0 2006.162.07:46:52.16#ibcon#enter sib2, iclass 39, count 0 2006.162.07:46:52.16#ibcon#flushed, iclass 39, count 0 2006.162.07:46:52.16#ibcon#about to write, iclass 39, count 0 2006.162.07:46:52.16#ibcon#wrote, iclass 39, count 0 2006.162.07:46:52.16#ibcon#about to read 3, iclass 39, count 0 2006.162.07:46:52.18#ibcon#read 3, iclass 39, count 0 2006.162.07:46:52.18#ibcon#about to read 4, iclass 39, count 0 2006.162.07:46:52.18#ibcon#read 4, iclass 39, count 0 2006.162.07:46:52.18#ibcon#about to read 5, iclass 39, count 0 2006.162.07:46:52.18#ibcon#read 5, iclass 39, count 0 2006.162.07:46:52.18#ibcon#about to read 6, iclass 39, count 0 2006.162.07:46:52.18#ibcon#read 6, iclass 39, count 0 2006.162.07:46:52.18#ibcon#end of sib2, iclass 39, count 0 2006.162.07:46:52.18#ibcon#*mode == 0, iclass 39, count 0 2006.162.07:46:52.18#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.162.07:46:52.18#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.07:46:52.18#ibcon#*before write, iclass 39, count 0 2006.162.07:46:52.18#ibcon#enter sib2, iclass 39, count 0 2006.162.07:46:52.18#ibcon#flushed, iclass 39, count 0 2006.162.07:46:52.18#ibcon#about to write, iclass 39, count 0 2006.162.07:46:52.18#ibcon#wrote, iclass 39, count 0 2006.162.07:46:52.18#ibcon#about to read 3, iclass 39, count 0 2006.162.07:46:52.22#ibcon#read 3, iclass 39, count 0 2006.162.07:46:52.22#ibcon#about to read 4, iclass 39, count 0 2006.162.07:46:52.22#ibcon#read 4, iclass 39, count 0 2006.162.07:46:52.22#ibcon#about to read 5, iclass 39, count 0 2006.162.07:46:52.22#ibcon#read 5, iclass 39, count 0 2006.162.07:46:52.22#ibcon#about to read 6, iclass 39, count 0 2006.162.07:46:52.22#ibcon#read 6, iclass 39, count 0 2006.162.07:46:52.22#ibcon#end of sib2, iclass 39, count 0 2006.162.07:46:52.22#ibcon#*after write, iclass 39, count 0 2006.162.07:46:52.22#ibcon#*before return 0, iclass 39, count 0 2006.162.07:46:52.22#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.162.07:46:52.22#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.162.07:46:52.22#ibcon#about to clear, iclass 39 cls_cnt 0 2006.162.07:46:52.22#ibcon#cleared, iclass 39 cls_cnt 0 2006.162.07:46:52.22$vc4f8/vb=2,4 2006.162.07:46:52.22#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.162.07:46:52.22#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.162.07:46:52.22#ibcon#ireg 11 cls_cnt 2 2006.162.07:46:52.22#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.162.07:46:52.28#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.162.07:46:52.28#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.162.07:46:52.28#ibcon#enter wrdev, iclass 3, count 2 2006.162.07:46:52.28#ibcon#first serial, iclass 3, count 2 2006.162.07:46:52.28#ibcon#enter sib2, iclass 3, count 2 2006.162.07:46:52.28#ibcon#flushed, iclass 3, count 2 2006.162.07:46:52.28#ibcon#about to write, iclass 3, count 2 2006.162.07:46:52.28#ibcon#wrote, iclass 3, count 2 2006.162.07:46:52.28#ibcon#about to read 3, iclass 3, count 2 2006.162.07:46:52.30#ibcon#read 3, iclass 3, count 2 2006.162.07:46:52.30#ibcon#about to read 4, iclass 3, count 2 2006.162.07:46:52.30#ibcon#read 4, iclass 3, count 2 2006.162.07:46:52.30#ibcon#about to read 5, iclass 3, count 2 2006.162.07:46:52.30#ibcon#read 5, iclass 3, count 2 2006.162.07:46:52.30#ibcon#about to read 6, iclass 3, count 2 2006.162.07:46:52.30#ibcon#read 6, iclass 3, count 2 2006.162.07:46:52.30#ibcon#end of sib2, iclass 3, count 2 2006.162.07:46:52.30#ibcon#*mode == 0, iclass 3, count 2 2006.162.07:46:52.30#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.162.07:46:52.30#ibcon#[27=AT02-04\r\n] 2006.162.07:46:52.30#ibcon#*before write, iclass 3, count 2 2006.162.07:46:52.30#ibcon#enter sib2, iclass 3, count 2 2006.162.07:46:52.30#ibcon#flushed, iclass 3, count 2 2006.162.07:46:52.30#ibcon#about to write, iclass 3, count 2 2006.162.07:46:52.30#ibcon#wrote, iclass 3, count 2 2006.162.07:46:52.30#ibcon#about to read 3, iclass 3, count 2 2006.162.07:46:52.33#ibcon#read 3, iclass 3, count 2 2006.162.07:46:52.33#ibcon#about to read 4, iclass 3, count 2 2006.162.07:46:52.33#ibcon#read 4, iclass 3, count 2 2006.162.07:46:52.33#ibcon#about to read 5, iclass 3, count 2 2006.162.07:46:52.33#ibcon#read 5, iclass 3, count 2 2006.162.07:46:52.33#ibcon#about to read 6, iclass 3, count 2 2006.162.07:46:52.33#ibcon#read 6, iclass 3, count 2 2006.162.07:46:52.33#ibcon#end of sib2, iclass 3, count 2 2006.162.07:46:52.33#ibcon#*after write, iclass 3, count 2 2006.162.07:46:52.33#ibcon#*before return 0, iclass 3, count 2 2006.162.07:46:52.33#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.162.07:46:52.33#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.162.07:46:52.33#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.162.07:46:52.33#ibcon#ireg 7 cls_cnt 0 2006.162.07:46:52.33#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.162.07:46:52.45#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.162.07:46:52.45#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.162.07:46:52.45#ibcon#enter wrdev, iclass 3, count 0 2006.162.07:46:52.45#ibcon#first serial, iclass 3, count 0 2006.162.07:46:52.45#ibcon#enter sib2, iclass 3, count 0 2006.162.07:46:52.45#ibcon#flushed, iclass 3, count 0 2006.162.07:46:52.45#ibcon#about to write, iclass 3, count 0 2006.162.07:46:52.45#ibcon#wrote, iclass 3, count 0 2006.162.07:46:52.45#ibcon#about to read 3, iclass 3, count 0 2006.162.07:46:52.47#ibcon#read 3, iclass 3, count 0 2006.162.07:46:52.47#ibcon#about to read 4, iclass 3, count 0 2006.162.07:46:52.47#ibcon#read 4, iclass 3, count 0 2006.162.07:46:52.47#ibcon#about to read 5, iclass 3, count 0 2006.162.07:46:52.47#ibcon#read 5, iclass 3, count 0 2006.162.07:46:52.47#ibcon#about to read 6, iclass 3, count 0 2006.162.07:46:52.47#ibcon#read 6, iclass 3, count 0 2006.162.07:46:52.47#ibcon#end of sib2, iclass 3, count 0 2006.162.07:46:52.47#ibcon#*mode == 0, iclass 3, count 0 2006.162.07:46:52.47#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.162.07:46:52.47#ibcon#[27=USB\r\n] 2006.162.07:46:52.47#ibcon#*before write, iclass 3, count 0 2006.162.07:46:52.47#ibcon#enter sib2, iclass 3, count 0 2006.162.07:46:52.47#ibcon#flushed, iclass 3, count 0 2006.162.07:46:52.47#ibcon#about to write, iclass 3, count 0 2006.162.07:46:52.47#ibcon#wrote, iclass 3, count 0 2006.162.07:46:52.47#ibcon#about to read 3, iclass 3, count 0 2006.162.07:46:52.50#ibcon#read 3, iclass 3, count 0 2006.162.07:46:52.50#ibcon#about to read 4, iclass 3, count 0 2006.162.07:46:52.50#ibcon#read 4, iclass 3, count 0 2006.162.07:46:52.50#ibcon#about to read 5, iclass 3, count 0 2006.162.07:46:52.50#ibcon#read 5, iclass 3, count 0 2006.162.07:46:52.50#ibcon#about to read 6, iclass 3, count 0 2006.162.07:46:52.50#ibcon#read 6, iclass 3, count 0 2006.162.07:46:52.50#ibcon#end of sib2, iclass 3, count 0 2006.162.07:46:52.50#ibcon#*after write, iclass 3, count 0 2006.162.07:46:52.50#ibcon#*before return 0, iclass 3, count 0 2006.162.07:46:52.50#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.162.07:46:52.50#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.162.07:46:52.50#ibcon#about to clear, iclass 3 cls_cnt 0 2006.162.07:46:52.50#ibcon#cleared, iclass 3 cls_cnt 0 2006.162.07:46:52.50$vc4f8/vblo=3,656.99 2006.162.07:46:52.50#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.162.07:46:52.50#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.162.07:46:52.50#ibcon#ireg 17 cls_cnt 0 2006.162.07:46:52.50#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.162.07:46:52.50#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.162.07:46:52.50#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.162.07:46:52.50#ibcon#enter wrdev, iclass 5, count 0 2006.162.07:46:52.50#ibcon#first serial, iclass 5, count 0 2006.162.07:46:52.50#ibcon#enter sib2, iclass 5, count 0 2006.162.07:46:52.50#ibcon#flushed, iclass 5, count 0 2006.162.07:46:52.50#ibcon#about to write, iclass 5, count 0 2006.162.07:46:52.50#ibcon#wrote, iclass 5, count 0 2006.162.07:46:52.50#ibcon#about to read 3, iclass 5, count 0 2006.162.07:46:52.52#ibcon#read 3, iclass 5, count 0 2006.162.07:46:52.52#ibcon#about to read 4, iclass 5, count 0 2006.162.07:46:52.52#ibcon#read 4, iclass 5, count 0 2006.162.07:46:52.52#ibcon#about to read 5, iclass 5, count 0 2006.162.07:46:52.52#ibcon#read 5, iclass 5, count 0 2006.162.07:46:52.52#ibcon#about to read 6, iclass 5, count 0 2006.162.07:46:52.52#ibcon#read 6, iclass 5, count 0 2006.162.07:46:52.52#ibcon#end of sib2, iclass 5, count 0 2006.162.07:46:52.52#ibcon#*mode == 0, iclass 5, count 0 2006.162.07:46:52.52#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.162.07:46:52.52#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.07:46:52.52#ibcon#*before write, iclass 5, count 0 2006.162.07:46:52.52#ibcon#enter sib2, iclass 5, count 0 2006.162.07:46:52.52#ibcon#flushed, iclass 5, count 0 2006.162.07:46:52.52#ibcon#about to write, iclass 5, count 0 2006.162.07:46:52.52#ibcon#wrote, iclass 5, count 0 2006.162.07:46:52.52#ibcon#about to read 3, iclass 5, count 0 2006.162.07:46:52.56#ibcon#read 3, iclass 5, count 0 2006.162.07:46:52.56#ibcon#about to read 4, iclass 5, count 0 2006.162.07:46:52.56#ibcon#read 4, iclass 5, count 0 2006.162.07:46:52.56#ibcon#about to read 5, iclass 5, count 0 2006.162.07:46:52.56#ibcon#read 5, iclass 5, count 0 2006.162.07:46:52.56#ibcon#about to read 6, iclass 5, count 0 2006.162.07:46:52.56#ibcon#read 6, iclass 5, count 0 2006.162.07:46:52.56#ibcon#end of sib2, iclass 5, count 0 2006.162.07:46:52.56#ibcon#*after write, iclass 5, count 0 2006.162.07:46:52.56#ibcon#*before return 0, iclass 5, count 0 2006.162.07:46:52.56#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.162.07:46:52.56#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.162.07:46:52.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.162.07:46:52.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.162.07:46:52.56$vc4f8/vb=3,4 2006.162.07:46:52.56#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.162.07:46:52.56#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.162.07:46:52.56#ibcon#ireg 11 cls_cnt 2 2006.162.07:46:52.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.162.07:46:52.62#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.162.07:46:52.62#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.162.07:46:52.62#ibcon#enter wrdev, iclass 7, count 2 2006.162.07:46:52.62#ibcon#first serial, iclass 7, count 2 2006.162.07:46:52.62#ibcon#enter sib2, iclass 7, count 2 2006.162.07:46:52.62#ibcon#flushed, iclass 7, count 2 2006.162.07:46:52.62#ibcon#about to write, iclass 7, count 2 2006.162.07:46:52.62#ibcon#wrote, iclass 7, count 2 2006.162.07:46:52.62#ibcon#about to read 3, iclass 7, count 2 2006.162.07:46:52.64#ibcon#read 3, iclass 7, count 2 2006.162.07:46:52.64#ibcon#about to read 4, iclass 7, count 2 2006.162.07:46:52.64#ibcon#read 4, iclass 7, count 2 2006.162.07:46:52.64#ibcon#about to read 5, iclass 7, count 2 2006.162.07:46:52.64#ibcon#read 5, iclass 7, count 2 2006.162.07:46:52.64#ibcon#about to read 6, iclass 7, count 2 2006.162.07:46:52.64#ibcon#read 6, iclass 7, count 2 2006.162.07:46:52.64#ibcon#end of sib2, iclass 7, count 2 2006.162.07:46:52.64#ibcon#*mode == 0, iclass 7, count 2 2006.162.07:46:52.64#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.162.07:46:52.64#ibcon#[27=AT03-04\r\n] 2006.162.07:46:52.64#ibcon#*before write, iclass 7, count 2 2006.162.07:46:52.64#ibcon#enter sib2, iclass 7, count 2 2006.162.07:46:52.64#ibcon#flushed, iclass 7, count 2 2006.162.07:46:52.64#ibcon#about to write, iclass 7, count 2 2006.162.07:46:52.64#ibcon#wrote, iclass 7, count 2 2006.162.07:46:52.64#ibcon#about to read 3, iclass 7, count 2 2006.162.07:46:52.67#ibcon#read 3, iclass 7, count 2 2006.162.07:46:52.67#ibcon#about to read 4, iclass 7, count 2 2006.162.07:46:52.67#ibcon#read 4, iclass 7, count 2 2006.162.07:46:52.67#ibcon#about to read 5, iclass 7, count 2 2006.162.07:46:52.67#ibcon#read 5, iclass 7, count 2 2006.162.07:46:52.67#ibcon#about to read 6, iclass 7, count 2 2006.162.07:46:52.67#ibcon#read 6, iclass 7, count 2 2006.162.07:46:52.67#ibcon#end of sib2, iclass 7, count 2 2006.162.07:46:52.67#ibcon#*after write, iclass 7, count 2 2006.162.07:46:52.67#ibcon#*before return 0, iclass 7, count 2 2006.162.07:46:52.67#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.162.07:46:52.67#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.162.07:46:52.67#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.162.07:46:52.67#ibcon#ireg 7 cls_cnt 0 2006.162.07:46:52.67#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.162.07:46:52.79#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.162.07:46:52.79#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.162.07:46:52.79#ibcon#enter wrdev, iclass 7, count 0 2006.162.07:46:52.79#ibcon#first serial, iclass 7, count 0 2006.162.07:46:52.79#ibcon#enter sib2, iclass 7, count 0 2006.162.07:46:52.79#ibcon#flushed, iclass 7, count 0 2006.162.07:46:52.79#ibcon#about to write, iclass 7, count 0 2006.162.07:46:52.79#ibcon#wrote, iclass 7, count 0 2006.162.07:46:52.79#ibcon#about to read 3, iclass 7, count 0 2006.162.07:46:52.81#ibcon#read 3, iclass 7, count 0 2006.162.07:46:52.81#ibcon#about to read 4, iclass 7, count 0 2006.162.07:46:52.81#ibcon#read 4, iclass 7, count 0 2006.162.07:46:52.81#ibcon#about to read 5, iclass 7, count 0 2006.162.07:46:52.81#ibcon#read 5, iclass 7, count 0 2006.162.07:46:52.81#ibcon#about to read 6, iclass 7, count 0 2006.162.07:46:52.81#ibcon#read 6, iclass 7, count 0 2006.162.07:46:52.81#ibcon#end of sib2, iclass 7, count 0 2006.162.07:46:52.81#ibcon#*mode == 0, iclass 7, count 0 2006.162.07:46:52.81#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.162.07:46:52.81#ibcon#[27=USB\r\n] 2006.162.07:46:52.81#ibcon#*before write, iclass 7, count 0 2006.162.07:46:52.81#ibcon#enter sib2, iclass 7, count 0 2006.162.07:46:52.81#ibcon#flushed, iclass 7, count 0 2006.162.07:46:52.81#ibcon#about to write, iclass 7, count 0 2006.162.07:46:52.81#ibcon#wrote, iclass 7, count 0 2006.162.07:46:52.81#ibcon#about to read 3, iclass 7, count 0 2006.162.07:46:52.84#ibcon#read 3, iclass 7, count 0 2006.162.07:46:52.84#ibcon#about to read 4, iclass 7, count 0 2006.162.07:46:52.84#ibcon#read 4, iclass 7, count 0 2006.162.07:46:52.84#ibcon#about to read 5, iclass 7, count 0 2006.162.07:46:52.84#ibcon#read 5, iclass 7, count 0 2006.162.07:46:52.84#ibcon#about to read 6, iclass 7, count 0 2006.162.07:46:52.84#ibcon#read 6, iclass 7, count 0 2006.162.07:46:52.84#ibcon#end of sib2, iclass 7, count 0 2006.162.07:46:52.84#ibcon#*after write, iclass 7, count 0 2006.162.07:46:52.84#ibcon#*before return 0, iclass 7, count 0 2006.162.07:46:52.84#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.162.07:46:52.84#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.162.07:46:52.84#ibcon#about to clear, iclass 7 cls_cnt 0 2006.162.07:46:52.84#ibcon#cleared, iclass 7 cls_cnt 0 2006.162.07:46:52.84$vc4f8/vblo=4,712.99 2006.162.07:46:52.84#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.162.07:46:52.84#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.162.07:46:52.84#ibcon#ireg 17 cls_cnt 0 2006.162.07:46:52.84#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.162.07:46:52.84#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.162.07:46:52.84#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.162.07:46:52.84#ibcon#enter wrdev, iclass 11, count 0 2006.162.07:46:52.84#ibcon#first serial, iclass 11, count 0 2006.162.07:46:52.84#ibcon#enter sib2, iclass 11, count 0 2006.162.07:46:52.84#ibcon#flushed, iclass 11, count 0 2006.162.07:46:52.84#ibcon#about to write, iclass 11, count 0 2006.162.07:46:52.84#ibcon#wrote, iclass 11, count 0 2006.162.07:46:52.84#ibcon#about to read 3, iclass 11, count 0 2006.162.07:46:52.86#ibcon#read 3, iclass 11, count 0 2006.162.07:46:52.86#ibcon#about to read 4, iclass 11, count 0 2006.162.07:46:52.86#ibcon#read 4, iclass 11, count 0 2006.162.07:46:52.86#ibcon#about to read 5, iclass 11, count 0 2006.162.07:46:52.86#ibcon#read 5, iclass 11, count 0 2006.162.07:46:52.86#ibcon#about to read 6, iclass 11, count 0 2006.162.07:46:52.86#ibcon#read 6, iclass 11, count 0 2006.162.07:46:52.86#ibcon#end of sib2, iclass 11, count 0 2006.162.07:46:52.86#ibcon#*mode == 0, iclass 11, count 0 2006.162.07:46:52.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.162.07:46:52.86#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.07:46:52.86#ibcon#*before write, iclass 11, count 0 2006.162.07:46:52.86#ibcon#enter sib2, iclass 11, count 0 2006.162.07:46:52.86#ibcon#flushed, iclass 11, count 0 2006.162.07:46:52.86#ibcon#about to write, iclass 11, count 0 2006.162.07:46:52.86#ibcon#wrote, iclass 11, count 0 2006.162.07:46:52.86#ibcon#about to read 3, iclass 11, count 0 2006.162.07:46:52.90#ibcon#read 3, iclass 11, count 0 2006.162.07:46:52.90#ibcon#about to read 4, iclass 11, count 0 2006.162.07:46:52.90#ibcon#read 4, iclass 11, count 0 2006.162.07:46:52.90#ibcon#about to read 5, iclass 11, count 0 2006.162.07:46:52.90#ibcon#read 5, iclass 11, count 0 2006.162.07:46:52.90#ibcon#about to read 6, iclass 11, count 0 2006.162.07:46:52.90#ibcon#read 6, iclass 11, count 0 2006.162.07:46:52.90#ibcon#end of sib2, iclass 11, count 0 2006.162.07:46:52.90#ibcon#*after write, iclass 11, count 0 2006.162.07:46:52.90#ibcon#*before return 0, iclass 11, count 0 2006.162.07:46:52.90#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.162.07:46:52.90#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.162.07:46:52.90#ibcon#about to clear, iclass 11 cls_cnt 0 2006.162.07:46:52.90#ibcon#cleared, iclass 11 cls_cnt 0 2006.162.07:46:52.90$vc4f8/vb=4,4 2006.162.07:46:52.90#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.162.07:46:52.90#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.162.07:46:52.90#ibcon#ireg 11 cls_cnt 2 2006.162.07:46:52.90#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.162.07:46:52.96#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.162.07:46:52.96#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.162.07:46:52.96#ibcon#enter wrdev, iclass 13, count 2 2006.162.07:46:52.96#ibcon#first serial, iclass 13, count 2 2006.162.07:46:52.96#ibcon#enter sib2, iclass 13, count 2 2006.162.07:46:52.96#ibcon#flushed, iclass 13, count 2 2006.162.07:46:52.96#ibcon#about to write, iclass 13, count 2 2006.162.07:46:52.96#ibcon#wrote, iclass 13, count 2 2006.162.07:46:52.96#ibcon#about to read 3, iclass 13, count 2 2006.162.07:46:52.98#ibcon#read 3, iclass 13, count 2 2006.162.07:46:52.98#ibcon#about to read 4, iclass 13, count 2 2006.162.07:46:52.98#ibcon#read 4, iclass 13, count 2 2006.162.07:46:52.98#ibcon#about to read 5, iclass 13, count 2 2006.162.07:46:52.98#ibcon#read 5, iclass 13, count 2 2006.162.07:46:52.98#ibcon#about to read 6, iclass 13, count 2 2006.162.07:46:52.98#ibcon#read 6, iclass 13, count 2 2006.162.07:46:52.98#ibcon#end of sib2, iclass 13, count 2 2006.162.07:46:52.98#ibcon#*mode == 0, iclass 13, count 2 2006.162.07:46:52.98#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.162.07:46:52.98#ibcon#[27=AT04-04\r\n] 2006.162.07:46:52.98#ibcon#*before write, iclass 13, count 2 2006.162.07:46:52.98#ibcon#enter sib2, iclass 13, count 2 2006.162.07:46:52.98#ibcon#flushed, iclass 13, count 2 2006.162.07:46:52.98#ibcon#about to write, iclass 13, count 2 2006.162.07:46:52.98#ibcon#wrote, iclass 13, count 2 2006.162.07:46:52.98#ibcon#about to read 3, iclass 13, count 2 2006.162.07:46:53.01#ibcon#read 3, iclass 13, count 2 2006.162.07:46:53.01#ibcon#about to read 4, iclass 13, count 2 2006.162.07:46:53.01#ibcon#read 4, iclass 13, count 2 2006.162.07:46:53.01#ibcon#about to read 5, iclass 13, count 2 2006.162.07:46:53.01#ibcon#read 5, iclass 13, count 2 2006.162.07:46:53.01#ibcon#about to read 6, iclass 13, count 2 2006.162.07:46:53.01#ibcon#read 6, iclass 13, count 2 2006.162.07:46:53.01#ibcon#end of sib2, iclass 13, count 2 2006.162.07:46:53.01#ibcon#*after write, iclass 13, count 2 2006.162.07:46:53.01#ibcon#*before return 0, iclass 13, count 2 2006.162.07:46:53.01#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.162.07:46:53.01#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.162.07:46:53.01#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.162.07:46:53.01#ibcon#ireg 7 cls_cnt 0 2006.162.07:46:53.01#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.162.07:46:53.13#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.162.07:46:53.13#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.162.07:46:53.13#ibcon#enter wrdev, iclass 13, count 0 2006.162.07:46:53.13#ibcon#first serial, iclass 13, count 0 2006.162.07:46:53.13#ibcon#enter sib2, iclass 13, count 0 2006.162.07:46:53.13#ibcon#flushed, iclass 13, count 0 2006.162.07:46:53.13#ibcon#about to write, iclass 13, count 0 2006.162.07:46:53.13#ibcon#wrote, iclass 13, count 0 2006.162.07:46:53.13#ibcon#about to read 3, iclass 13, count 0 2006.162.07:46:53.15#ibcon#read 3, iclass 13, count 0 2006.162.07:46:53.15#ibcon#about to read 4, iclass 13, count 0 2006.162.07:46:53.15#ibcon#read 4, iclass 13, count 0 2006.162.07:46:53.15#ibcon#about to read 5, iclass 13, count 0 2006.162.07:46:53.15#ibcon#read 5, iclass 13, count 0 2006.162.07:46:53.15#ibcon#about to read 6, iclass 13, count 0 2006.162.07:46:53.15#ibcon#read 6, iclass 13, count 0 2006.162.07:46:53.15#ibcon#end of sib2, iclass 13, count 0 2006.162.07:46:53.15#ibcon#*mode == 0, iclass 13, count 0 2006.162.07:46:53.15#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.162.07:46:53.15#ibcon#[27=USB\r\n] 2006.162.07:46:53.15#ibcon#*before write, iclass 13, count 0 2006.162.07:46:53.15#ibcon#enter sib2, iclass 13, count 0 2006.162.07:46:53.15#ibcon#flushed, iclass 13, count 0 2006.162.07:46:53.15#ibcon#about to write, iclass 13, count 0 2006.162.07:46:53.15#ibcon#wrote, iclass 13, count 0 2006.162.07:46:53.15#ibcon#about to read 3, iclass 13, count 0 2006.162.07:46:53.18#ibcon#read 3, iclass 13, count 0 2006.162.07:46:53.18#ibcon#about to read 4, iclass 13, count 0 2006.162.07:46:53.18#ibcon#read 4, iclass 13, count 0 2006.162.07:46:53.18#ibcon#about to read 5, iclass 13, count 0 2006.162.07:46:53.18#ibcon#read 5, iclass 13, count 0 2006.162.07:46:53.18#ibcon#about to read 6, iclass 13, count 0 2006.162.07:46:53.18#ibcon#read 6, iclass 13, count 0 2006.162.07:46:53.18#ibcon#end of sib2, iclass 13, count 0 2006.162.07:46:53.18#ibcon#*after write, iclass 13, count 0 2006.162.07:46:53.18#ibcon#*before return 0, iclass 13, count 0 2006.162.07:46:53.18#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.162.07:46:53.18#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.162.07:46:53.18#ibcon#about to clear, iclass 13 cls_cnt 0 2006.162.07:46:53.18#ibcon#cleared, iclass 13 cls_cnt 0 2006.162.07:46:53.18$vc4f8/vblo=5,744.99 2006.162.07:46:53.18#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.162.07:46:53.18#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.162.07:46:53.18#ibcon#ireg 17 cls_cnt 0 2006.162.07:46:53.18#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:46:53.18#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:46:53.18#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:46:53.18#ibcon#enter wrdev, iclass 15, count 0 2006.162.07:46:53.18#ibcon#first serial, iclass 15, count 0 2006.162.07:46:53.18#ibcon#enter sib2, iclass 15, count 0 2006.162.07:46:53.18#ibcon#flushed, iclass 15, count 0 2006.162.07:46:53.18#ibcon#about to write, iclass 15, count 0 2006.162.07:46:53.18#ibcon#wrote, iclass 15, count 0 2006.162.07:46:53.18#ibcon#about to read 3, iclass 15, count 0 2006.162.07:46:53.20#ibcon#read 3, iclass 15, count 0 2006.162.07:46:53.20#ibcon#about to read 4, iclass 15, count 0 2006.162.07:46:53.20#ibcon#read 4, iclass 15, count 0 2006.162.07:46:53.20#ibcon#about to read 5, iclass 15, count 0 2006.162.07:46:53.20#ibcon#read 5, iclass 15, count 0 2006.162.07:46:53.20#ibcon#about to read 6, iclass 15, count 0 2006.162.07:46:53.20#ibcon#read 6, iclass 15, count 0 2006.162.07:46:53.20#ibcon#end of sib2, iclass 15, count 0 2006.162.07:46:53.20#ibcon#*mode == 0, iclass 15, count 0 2006.162.07:46:53.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.162.07:46:53.20#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.07:46:53.20#ibcon#*before write, iclass 15, count 0 2006.162.07:46:53.20#ibcon#enter sib2, iclass 15, count 0 2006.162.07:46:53.20#ibcon#flushed, iclass 15, count 0 2006.162.07:46:53.20#ibcon#about to write, iclass 15, count 0 2006.162.07:46:53.20#ibcon#wrote, iclass 15, count 0 2006.162.07:46:53.20#ibcon#about to read 3, iclass 15, count 0 2006.162.07:46:53.24#ibcon#read 3, iclass 15, count 0 2006.162.07:46:53.24#ibcon#about to read 4, iclass 15, count 0 2006.162.07:46:53.24#ibcon#read 4, iclass 15, count 0 2006.162.07:46:53.24#ibcon#about to read 5, iclass 15, count 0 2006.162.07:46:53.24#ibcon#read 5, iclass 15, count 0 2006.162.07:46:53.24#ibcon#about to read 6, iclass 15, count 0 2006.162.07:46:53.24#ibcon#read 6, iclass 15, count 0 2006.162.07:46:53.24#ibcon#end of sib2, iclass 15, count 0 2006.162.07:46:53.24#ibcon#*after write, iclass 15, count 0 2006.162.07:46:53.24#ibcon#*before return 0, iclass 15, count 0 2006.162.07:46:53.24#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:46:53.24#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.162.07:46:53.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.162.07:46:53.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.162.07:46:53.24$vc4f8/vb=5,4 2006.162.07:46:53.24#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.162.07:46:53.24#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.162.07:46:53.24#ibcon#ireg 11 cls_cnt 2 2006.162.07:46:53.24#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:46:53.30#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:46:53.30#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:46:53.30#ibcon#enter wrdev, iclass 17, count 2 2006.162.07:46:53.30#ibcon#first serial, iclass 17, count 2 2006.162.07:46:53.30#ibcon#enter sib2, iclass 17, count 2 2006.162.07:46:53.30#ibcon#flushed, iclass 17, count 2 2006.162.07:46:53.30#ibcon#about to write, iclass 17, count 2 2006.162.07:46:53.30#ibcon#wrote, iclass 17, count 2 2006.162.07:46:53.30#ibcon#about to read 3, iclass 17, count 2 2006.162.07:46:53.32#ibcon#read 3, iclass 17, count 2 2006.162.07:46:53.32#ibcon#about to read 4, iclass 17, count 2 2006.162.07:46:53.32#ibcon#read 4, iclass 17, count 2 2006.162.07:46:53.32#ibcon#about to read 5, iclass 17, count 2 2006.162.07:46:53.32#ibcon#read 5, iclass 17, count 2 2006.162.07:46:53.32#ibcon#about to read 6, iclass 17, count 2 2006.162.07:46:53.32#ibcon#read 6, iclass 17, count 2 2006.162.07:46:53.32#ibcon#end of sib2, iclass 17, count 2 2006.162.07:46:53.32#ibcon#*mode == 0, iclass 17, count 2 2006.162.07:46:53.32#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.162.07:46:53.32#ibcon#[27=AT05-04\r\n] 2006.162.07:46:53.32#ibcon#*before write, iclass 17, count 2 2006.162.07:46:53.32#ibcon#enter sib2, iclass 17, count 2 2006.162.07:46:53.32#ibcon#flushed, iclass 17, count 2 2006.162.07:46:53.32#ibcon#about to write, iclass 17, count 2 2006.162.07:46:53.32#ibcon#wrote, iclass 17, count 2 2006.162.07:46:53.32#ibcon#about to read 3, iclass 17, count 2 2006.162.07:46:53.35#ibcon#read 3, iclass 17, count 2 2006.162.07:46:53.35#ibcon#about to read 4, iclass 17, count 2 2006.162.07:46:53.35#ibcon#read 4, iclass 17, count 2 2006.162.07:46:53.35#ibcon#about to read 5, iclass 17, count 2 2006.162.07:46:53.35#ibcon#read 5, iclass 17, count 2 2006.162.07:46:53.35#ibcon#about to read 6, iclass 17, count 2 2006.162.07:46:53.35#ibcon#read 6, iclass 17, count 2 2006.162.07:46:53.35#ibcon#end of sib2, iclass 17, count 2 2006.162.07:46:53.35#ibcon#*after write, iclass 17, count 2 2006.162.07:46:53.35#ibcon#*before return 0, iclass 17, count 2 2006.162.07:46:53.35#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:46:53.35#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.162.07:46:53.35#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.162.07:46:53.35#ibcon#ireg 7 cls_cnt 0 2006.162.07:46:53.35#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:46:53.47#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:46:53.47#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:46:53.47#ibcon#enter wrdev, iclass 17, count 0 2006.162.07:46:53.47#ibcon#first serial, iclass 17, count 0 2006.162.07:46:53.47#ibcon#enter sib2, iclass 17, count 0 2006.162.07:46:53.47#ibcon#flushed, iclass 17, count 0 2006.162.07:46:53.47#ibcon#about to write, iclass 17, count 0 2006.162.07:46:53.47#ibcon#wrote, iclass 17, count 0 2006.162.07:46:53.47#ibcon#about to read 3, iclass 17, count 0 2006.162.07:46:53.49#ibcon#read 3, iclass 17, count 0 2006.162.07:46:53.49#ibcon#about to read 4, iclass 17, count 0 2006.162.07:46:53.49#ibcon#read 4, iclass 17, count 0 2006.162.07:46:53.49#ibcon#about to read 5, iclass 17, count 0 2006.162.07:46:53.49#ibcon#read 5, iclass 17, count 0 2006.162.07:46:53.49#ibcon#about to read 6, iclass 17, count 0 2006.162.07:46:53.49#ibcon#read 6, iclass 17, count 0 2006.162.07:46:53.49#ibcon#end of sib2, iclass 17, count 0 2006.162.07:46:53.49#ibcon#*mode == 0, iclass 17, count 0 2006.162.07:46:53.49#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.162.07:46:53.49#ibcon#[27=USB\r\n] 2006.162.07:46:53.49#ibcon#*before write, iclass 17, count 0 2006.162.07:46:53.49#ibcon#enter sib2, iclass 17, count 0 2006.162.07:46:53.49#ibcon#flushed, iclass 17, count 0 2006.162.07:46:53.49#ibcon#about to write, iclass 17, count 0 2006.162.07:46:53.49#ibcon#wrote, iclass 17, count 0 2006.162.07:46:53.49#ibcon#about to read 3, iclass 17, count 0 2006.162.07:46:53.52#ibcon#read 3, iclass 17, count 0 2006.162.07:46:53.52#ibcon#about to read 4, iclass 17, count 0 2006.162.07:46:53.52#ibcon#read 4, iclass 17, count 0 2006.162.07:46:53.52#ibcon#about to read 5, iclass 17, count 0 2006.162.07:46:53.52#ibcon#read 5, iclass 17, count 0 2006.162.07:46:53.52#ibcon#about to read 6, iclass 17, count 0 2006.162.07:46:53.52#ibcon#read 6, iclass 17, count 0 2006.162.07:46:53.52#ibcon#end of sib2, iclass 17, count 0 2006.162.07:46:53.52#ibcon#*after write, iclass 17, count 0 2006.162.07:46:53.52#ibcon#*before return 0, iclass 17, count 0 2006.162.07:46:53.52#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:46:53.52#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.162.07:46:53.52#ibcon#about to clear, iclass 17 cls_cnt 0 2006.162.07:46:53.52#ibcon#cleared, iclass 17 cls_cnt 0 2006.162.07:46:53.52$vc4f8/vblo=6,752.99 2006.162.07:46:53.52#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.162.07:46:53.52#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.162.07:46:53.52#ibcon#ireg 17 cls_cnt 0 2006.162.07:46:53.52#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:46:53.52#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:46:53.52#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:46:53.52#ibcon#enter wrdev, iclass 19, count 0 2006.162.07:46:53.52#ibcon#first serial, iclass 19, count 0 2006.162.07:46:53.52#ibcon#enter sib2, iclass 19, count 0 2006.162.07:46:53.52#ibcon#flushed, iclass 19, count 0 2006.162.07:46:53.52#ibcon#about to write, iclass 19, count 0 2006.162.07:46:53.52#ibcon#wrote, iclass 19, count 0 2006.162.07:46:53.52#ibcon#about to read 3, iclass 19, count 0 2006.162.07:46:53.54#ibcon#read 3, iclass 19, count 0 2006.162.07:46:53.54#ibcon#about to read 4, iclass 19, count 0 2006.162.07:46:53.54#ibcon#read 4, iclass 19, count 0 2006.162.07:46:53.54#ibcon#about to read 5, iclass 19, count 0 2006.162.07:46:53.54#ibcon#read 5, iclass 19, count 0 2006.162.07:46:53.54#ibcon#about to read 6, iclass 19, count 0 2006.162.07:46:53.54#ibcon#read 6, iclass 19, count 0 2006.162.07:46:53.54#ibcon#end of sib2, iclass 19, count 0 2006.162.07:46:53.54#ibcon#*mode == 0, iclass 19, count 0 2006.162.07:46:53.54#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.162.07:46:53.54#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.07:46:53.54#ibcon#*before write, iclass 19, count 0 2006.162.07:46:53.54#ibcon#enter sib2, iclass 19, count 0 2006.162.07:46:53.54#ibcon#flushed, iclass 19, count 0 2006.162.07:46:53.54#ibcon#about to write, iclass 19, count 0 2006.162.07:46:53.54#ibcon#wrote, iclass 19, count 0 2006.162.07:46:53.54#ibcon#about to read 3, iclass 19, count 0 2006.162.07:46:53.58#ibcon#read 3, iclass 19, count 0 2006.162.07:46:53.58#ibcon#about to read 4, iclass 19, count 0 2006.162.07:46:53.58#ibcon#read 4, iclass 19, count 0 2006.162.07:46:53.58#ibcon#about to read 5, iclass 19, count 0 2006.162.07:46:53.58#ibcon#read 5, iclass 19, count 0 2006.162.07:46:53.58#ibcon#about to read 6, iclass 19, count 0 2006.162.07:46:53.58#ibcon#read 6, iclass 19, count 0 2006.162.07:46:53.58#ibcon#end of sib2, iclass 19, count 0 2006.162.07:46:53.58#ibcon#*after write, iclass 19, count 0 2006.162.07:46:53.58#ibcon#*before return 0, iclass 19, count 0 2006.162.07:46:53.58#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:46:53.58#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.162.07:46:53.58#ibcon#about to clear, iclass 19 cls_cnt 0 2006.162.07:46:53.58#ibcon#cleared, iclass 19 cls_cnt 0 2006.162.07:46:53.58$vc4f8/vb=6,4 2006.162.07:46:53.58#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.162.07:46:53.58#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.162.07:46:53.58#ibcon#ireg 11 cls_cnt 2 2006.162.07:46:53.58#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:46:53.64#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:46:53.64#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:46:53.64#ibcon#enter wrdev, iclass 21, count 2 2006.162.07:46:53.64#ibcon#first serial, iclass 21, count 2 2006.162.07:46:53.64#ibcon#enter sib2, iclass 21, count 2 2006.162.07:46:53.64#ibcon#flushed, iclass 21, count 2 2006.162.07:46:53.64#ibcon#about to write, iclass 21, count 2 2006.162.07:46:53.64#ibcon#wrote, iclass 21, count 2 2006.162.07:46:53.64#ibcon#about to read 3, iclass 21, count 2 2006.162.07:46:53.66#ibcon#read 3, iclass 21, count 2 2006.162.07:46:53.66#ibcon#about to read 4, iclass 21, count 2 2006.162.07:46:53.66#ibcon#read 4, iclass 21, count 2 2006.162.07:46:53.66#ibcon#about to read 5, iclass 21, count 2 2006.162.07:46:53.66#ibcon#read 5, iclass 21, count 2 2006.162.07:46:53.66#ibcon#about to read 6, iclass 21, count 2 2006.162.07:46:53.66#ibcon#read 6, iclass 21, count 2 2006.162.07:46:53.66#ibcon#end of sib2, iclass 21, count 2 2006.162.07:46:53.66#ibcon#*mode == 0, iclass 21, count 2 2006.162.07:46:53.66#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.162.07:46:53.66#ibcon#[27=AT06-04\r\n] 2006.162.07:46:53.66#ibcon#*before write, iclass 21, count 2 2006.162.07:46:53.66#ibcon#enter sib2, iclass 21, count 2 2006.162.07:46:53.66#ibcon#flushed, iclass 21, count 2 2006.162.07:46:53.66#ibcon#about to write, iclass 21, count 2 2006.162.07:46:53.66#ibcon#wrote, iclass 21, count 2 2006.162.07:46:53.66#ibcon#about to read 3, iclass 21, count 2 2006.162.07:46:53.69#ibcon#read 3, iclass 21, count 2 2006.162.07:46:53.69#ibcon#about to read 4, iclass 21, count 2 2006.162.07:46:53.69#ibcon#read 4, iclass 21, count 2 2006.162.07:46:53.69#ibcon#about to read 5, iclass 21, count 2 2006.162.07:46:53.69#ibcon#read 5, iclass 21, count 2 2006.162.07:46:53.69#ibcon#about to read 6, iclass 21, count 2 2006.162.07:46:53.69#ibcon#read 6, iclass 21, count 2 2006.162.07:46:53.69#ibcon#end of sib2, iclass 21, count 2 2006.162.07:46:53.69#ibcon#*after write, iclass 21, count 2 2006.162.07:46:53.69#ibcon#*before return 0, iclass 21, count 2 2006.162.07:46:53.69#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:46:53.69#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.162.07:46:53.69#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.162.07:46:53.69#ibcon#ireg 7 cls_cnt 0 2006.162.07:46:53.69#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:46:53.81#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:46:53.81#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:46:53.81#ibcon#enter wrdev, iclass 21, count 0 2006.162.07:46:53.81#ibcon#first serial, iclass 21, count 0 2006.162.07:46:53.81#ibcon#enter sib2, iclass 21, count 0 2006.162.07:46:53.81#ibcon#flushed, iclass 21, count 0 2006.162.07:46:53.81#ibcon#about to write, iclass 21, count 0 2006.162.07:46:53.81#ibcon#wrote, iclass 21, count 0 2006.162.07:46:53.81#ibcon#about to read 3, iclass 21, count 0 2006.162.07:46:53.83#ibcon#read 3, iclass 21, count 0 2006.162.07:46:53.83#ibcon#about to read 4, iclass 21, count 0 2006.162.07:46:53.83#ibcon#read 4, iclass 21, count 0 2006.162.07:46:53.83#ibcon#about to read 5, iclass 21, count 0 2006.162.07:46:53.83#ibcon#read 5, iclass 21, count 0 2006.162.07:46:53.83#ibcon#about to read 6, iclass 21, count 0 2006.162.07:46:53.83#ibcon#read 6, iclass 21, count 0 2006.162.07:46:53.83#ibcon#end of sib2, iclass 21, count 0 2006.162.07:46:53.83#ibcon#*mode == 0, iclass 21, count 0 2006.162.07:46:53.83#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.162.07:46:53.83#ibcon#[27=USB\r\n] 2006.162.07:46:53.83#ibcon#*before write, iclass 21, count 0 2006.162.07:46:53.83#ibcon#enter sib2, iclass 21, count 0 2006.162.07:46:53.83#ibcon#flushed, iclass 21, count 0 2006.162.07:46:53.83#ibcon#about to write, iclass 21, count 0 2006.162.07:46:53.83#ibcon#wrote, iclass 21, count 0 2006.162.07:46:53.83#ibcon#about to read 3, iclass 21, count 0 2006.162.07:46:53.86#ibcon#read 3, iclass 21, count 0 2006.162.07:46:53.86#ibcon#about to read 4, iclass 21, count 0 2006.162.07:46:53.86#ibcon#read 4, iclass 21, count 0 2006.162.07:46:53.86#ibcon#about to read 5, iclass 21, count 0 2006.162.07:46:53.86#ibcon#read 5, iclass 21, count 0 2006.162.07:46:53.86#ibcon#about to read 6, iclass 21, count 0 2006.162.07:46:53.86#ibcon#read 6, iclass 21, count 0 2006.162.07:46:53.86#ibcon#end of sib2, iclass 21, count 0 2006.162.07:46:53.86#ibcon#*after write, iclass 21, count 0 2006.162.07:46:53.86#ibcon#*before return 0, iclass 21, count 0 2006.162.07:46:53.86#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:46:53.86#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.162.07:46:53.86#ibcon#about to clear, iclass 21 cls_cnt 0 2006.162.07:46:53.86#ibcon#cleared, iclass 21 cls_cnt 0 2006.162.07:46:53.86$vc4f8/vabw=wide 2006.162.07:46:53.86#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.162.07:46:53.86#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.162.07:46:53.86#ibcon#ireg 8 cls_cnt 0 2006.162.07:46:53.86#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:46:53.86#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:46:53.86#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:46:53.86#ibcon#enter wrdev, iclass 23, count 0 2006.162.07:46:53.86#ibcon#first serial, iclass 23, count 0 2006.162.07:46:53.86#ibcon#enter sib2, iclass 23, count 0 2006.162.07:46:53.86#ibcon#flushed, iclass 23, count 0 2006.162.07:46:53.86#ibcon#about to write, iclass 23, count 0 2006.162.07:46:53.86#ibcon#wrote, iclass 23, count 0 2006.162.07:46:53.86#ibcon#about to read 3, iclass 23, count 0 2006.162.07:46:53.88#ibcon#read 3, iclass 23, count 0 2006.162.07:46:53.88#ibcon#about to read 4, iclass 23, count 0 2006.162.07:46:53.88#ibcon#read 4, iclass 23, count 0 2006.162.07:46:53.88#ibcon#about to read 5, iclass 23, count 0 2006.162.07:46:53.88#ibcon#read 5, iclass 23, count 0 2006.162.07:46:53.88#ibcon#about to read 6, iclass 23, count 0 2006.162.07:46:53.88#ibcon#read 6, iclass 23, count 0 2006.162.07:46:53.88#ibcon#end of sib2, iclass 23, count 0 2006.162.07:46:53.88#ibcon#*mode == 0, iclass 23, count 0 2006.162.07:46:53.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.162.07:46:53.88#ibcon#[25=BW32\r\n] 2006.162.07:46:53.88#ibcon#*before write, iclass 23, count 0 2006.162.07:46:53.88#ibcon#enter sib2, iclass 23, count 0 2006.162.07:46:53.88#ibcon#flushed, iclass 23, count 0 2006.162.07:46:53.88#ibcon#about to write, iclass 23, count 0 2006.162.07:46:53.88#ibcon#wrote, iclass 23, count 0 2006.162.07:46:53.88#ibcon#about to read 3, iclass 23, count 0 2006.162.07:46:53.91#ibcon#read 3, iclass 23, count 0 2006.162.07:46:53.91#ibcon#about to read 4, iclass 23, count 0 2006.162.07:46:53.91#ibcon#read 4, iclass 23, count 0 2006.162.07:46:53.91#ibcon#about to read 5, iclass 23, count 0 2006.162.07:46:53.91#ibcon#read 5, iclass 23, count 0 2006.162.07:46:53.91#ibcon#about to read 6, iclass 23, count 0 2006.162.07:46:53.91#ibcon#read 6, iclass 23, count 0 2006.162.07:46:53.91#ibcon#end of sib2, iclass 23, count 0 2006.162.07:46:53.91#ibcon#*after write, iclass 23, count 0 2006.162.07:46:53.91#ibcon#*before return 0, iclass 23, count 0 2006.162.07:46:53.91#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:46:53.91#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.162.07:46:53.91#ibcon#about to clear, iclass 23 cls_cnt 0 2006.162.07:46:53.91#ibcon#cleared, iclass 23 cls_cnt 0 2006.162.07:46:53.91$vc4f8/vbbw=wide 2006.162.07:46:53.91#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.162.07:46:53.91#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.162.07:46:53.91#ibcon#ireg 8 cls_cnt 0 2006.162.07:46:53.91#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:46:53.98#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:46:53.98#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:46:53.98#ibcon#enter wrdev, iclass 25, count 0 2006.162.07:46:53.98#ibcon#first serial, iclass 25, count 0 2006.162.07:46:53.98#ibcon#enter sib2, iclass 25, count 0 2006.162.07:46:53.98#ibcon#flushed, iclass 25, count 0 2006.162.07:46:53.98#ibcon#about to write, iclass 25, count 0 2006.162.07:46:53.98#ibcon#wrote, iclass 25, count 0 2006.162.07:46:53.98#ibcon#about to read 3, iclass 25, count 0 2006.162.07:46:54.00#ibcon#read 3, iclass 25, count 0 2006.162.07:46:54.00#ibcon#about to read 4, iclass 25, count 0 2006.162.07:46:54.00#ibcon#read 4, iclass 25, count 0 2006.162.07:46:54.00#ibcon#about to read 5, iclass 25, count 0 2006.162.07:46:54.00#ibcon#read 5, iclass 25, count 0 2006.162.07:46:54.00#ibcon#about to read 6, iclass 25, count 0 2006.162.07:46:54.00#ibcon#read 6, iclass 25, count 0 2006.162.07:46:54.00#ibcon#end of sib2, iclass 25, count 0 2006.162.07:46:54.00#ibcon#*mode == 0, iclass 25, count 0 2006.162.07:46:54.00#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.162.07:46:54.00#ibcon#[27=BW32\r\n] 2006.162.07:46:54.00#ibcon#*before write, iclass 25, count 0 2006.162.07:46:54.00#ibcon#enter sib2, iclass 25, count 0 2006.162.07:46:54.00#ibcon#flushed, iclass 25, count 0 2006.162.07:46:54.00#ibcon#about to write, iclass 25, count 0 2006.162.07:46:54.00#ibcon#wrote, iclass 25, count 0 2006.162.07:46:54.00#ibcon#about to read 3, iclass 25, count 0 2006.162.07:46:54.03#ibcon#read 3, iclass 25, count 0 2006.162.07:46:54.03#ibcon#about to read 4, iclass 25, count 0 2006.162.07:46:54.03#ibcon#read 4, iclass 25, count 0 2006.162.07:46:54.03#ibcon#about to read 5, iclass 25, count 0 2006.162.07:46:54.03#ibcon#read 5, iclass 25, count 0 2006.162.07:46:54.03#ibcon#about to read 6, iclass 25, count 0 2006.162.07:46:54.03#ibcon#read 6, iclass 25, count 0 2006.162.07:46:54.03#ibcon#end of sib2, iclass 25, count 0 2006.162.07:46:54.03#ibcon#*after write, iclass 25, count 0 2006.162.07:46:54.03#ibcon#*before return 0, iclass 25, count 0 2006.162.07:46:54.03#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:46:54.03#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:46:54.03#ibcon#about to clear, iclass 25 cls_cnt 0 2006.162.07:46:54.03#ibcon#cleared, iclass 25 cls_cnt 0 2006.162.07:46:54.03$4f8m12a/ifd4f 2006.162.07:46:54.03$ifd4f/lo= 2006.162.07:46:54.03$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.07:46:54.03$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.07:46:54.03$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.07:46:54.03$ifd4f/patch= 2006.162.07:46:54.03$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.07:46:54.03$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.07:46:54.03$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.07:46:54.03$4f8m12a/"form=m,16.000,1:2 2006.162.07:46:54.03$4f8m12a/"tpicd 2006.162.07:46:54.03$4f8m12a/echo=off 2006.162.07:46:54.03$4f8m12a/xlog=off 2006.162.07:46:54.03:!2006.162.07:47:20 2006.162.07:47:00.14#trakl#Source acquired 2006.162.07:47:02.14#flagr#flagr/antenna,acquired 2006.162.07:47:20.00:preob 2006.162.07:47:21.14/onsource/TRACKING 2006.162.07:47:21.14:!2006.162.07:47:30 2006.162.07:47:30.00:data_valid=on 2006.162.07:47:30.00:midob 2006.162.07:47:30.14/onsource/TRACKING 2006.162.07:47:30.14/wx/17.87,1007.3,100 2006.162.07:47:30.34/cable/+6.5377E-03 2006.162.07:47:31.43/va/01,08,usb,yes,39,42 2006.162.07:47:31.43/va/02,07,usb,yes,40,42 2006.162.07:47:31.43/va/03,06,usb,yes,42,43 2006.162.07:47:31.43/va/04,07,usb,yes,41,44 2006.162.07:47:31.43/va/05,07,usb,yes,44,47 2006.162.07:47:31.43/va/06,06,usb,yes,43,43 2006.162.07:47:31.43/va/07,06,usb,yes,44,44 2006.162.07:47:31.43/va/08,07,usb,yes,42,41 2006.162.07:47:31.66/valo/01,532.99,yes,locked 2006.162.07:47:31.66/valo/02,572.99,yes,locked 2006.162.07:47:31.66/valo/03,672.99,yes,locked 2006.162.07:47:31.66/valo/04,832.99,yes,locked 2006.162.07:47:31.66/valo/05,652.99,yes,locked 2006.162.07:47:31.66/valo/06,772.99,yes,locked 2006.162.07:47:31.66/valo/07,832.99,yes,locked 2006.162.07:47:31.66/valo/08,852.99,yes,locked 2006.162.07:47:32.75/vb/01,04,usb,yes,29,28 2006.162.07:47:32.75/vb/02,04,usb,yes,31,33 2006.162.07:47:32.75/vb/03,04,usb,yes,27,31 2006.162.07:47:32.75/vb/04,04,usb,yes,28,29 2006.162.07:47:32.75/vb/05,04,usb,yes,27,31 2006.162.07:47:32.75/vb/06,04,usb,yes,28,30 2006.162.07:47:32.75/vb/07,04,usb,yes,30,30 2006.162.07:47:32.75/vb/08,04,usb,yes,27,31 2006.162.07:47:32.98/vblo/01,632.99,yes,locked 2006.162.07:47:32.98/vblo/02,640.99,yes,locked 2006.162.07:47:32.98/vblo/03,656.99,yes,locked 2006.162.07:47:32.98/vblo/04,712.99,yes,locked 2006.162.07:47:32.98/vblo/05,744.99,yes,locked 2006.162.07:47:32.98/vblo/06,752.99,yes,locked 2006.162.07:47:32.98/vblo/07,734.99,yes,locked 2006.162.07:47:32.98/vblo/08,744.99,yes,locked 2006.162.07:47:33.13/vabw/8 2006.162.07:47:33.28/vbbw/8 2006.162.07:47:33.37/xfe/off,on,14.7 2006.162.07:47:33.75/ifatt/23,28,28,28 2006.162.07:47:34.08/fmout-gps/S +4.48E-07 2006.162.07:47:34.12:!2006.162.07:48:30 2006.162.07:48:30.00:data_valid=off 2006.162.07:48:30.00:postob 2006.162.07:48:30.07/cable/+6.5379E-03 2006.162.07:48:30.08/wx/17.87,1007.2,100 2006.162.07:48:31.07/fmout-gps/S +4.47E-07 2006.162.07:48:31.07:scan_name=162-0749,k06162,140 2006.162.07:48:31.07:source=0722+145,072516.81,142513.7,2000.0,ccw 2006.162.07:48:31.14#flagr#flagr/antenna,new-source 2006.162.07:48:32.14:checkk5 2006.162.07:48:32.53/chk_autoobs//k5ts1/ autoobs is running! 2006.162.07:48:32.98/chk_autoobs//k5ts2/ autoobs is running! 2006.162.07:48:33.61/chk_autoobs//k5ts3/ autoobs is running! 2006.162.07:48:34.06/chk_autoobs//k5ts4/ autoobs is running! 2006.162.07:48:34.49/chk_obsdata//k5ts1/T1620747??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:48:34.99/chk_obsdata//k5ts2/T1620747??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:48:35.40/chk_obsdata//k5ts3/T1620747??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:48:35.85/chk_obsdata//k5ts4/T1620747??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:48:36.62/k5log//k5ts1_log_newline 2006.162.07:48:37.62/k5log//k5ts2_log_newline 2006.162.07:48:38.80/k5log//k5ts3_log_newline 2006.162.07:48:39.89/k5log//k5ts4_log_newline 2006.162.07:48:39.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.07:48:39.92:4f8m12a=1 2006.162.07:48:39.92$4f8m12a/echo=on 2006.162.07:48:39.92$4f8m12a/pcalon 2006.162.07:48:39.92$pcalon/"no phase cal control is implemented here 2006.162.07:48:39.92$4f8m12a/"tpicd=stop 2006.162.07:48:39.92$4f8m12a/vc4f8 2006.162.07:48:39.92$vc4f8/valo=1,532.99 2006.162.07:48:39.92#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.162.07:48:39.92#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.162.07:48:39.92#ibcon#ireg 17 cls_cnt 0 2006.162.07:48:39.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:48:39.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:48:39.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:48:39.92#ibcon#enter wrdev, iclass 36, count 0 2006.162.07:48:39.92#ibcon#first serial, iclass 36, count 0 2006.162.07:48:39.92#ibcon#enter sib2, iclass 36, count 0 2006.162.07:48:39.92#ibcon#flushed, iclass 36, count 0 2006.162.07:48:39.92#ibcon#about to write, iclass 36, count 0 2006.162.07:48:39.92#ibcon#wrote, iclass 36, count 0 2006.162.07:48:39.92#ibcon#about to read 3, iclass 36, count 0 2006.162.07:48:39.97#ibcon#read 3, iclass 36, count 0 2006.162.07:48:39.97#ibcon#about to read 4, iclass 36, count 0 2006.162.07:48:39.97#ibcon#read 4, iclass 36, count 0 2006.162.07:48:39.97#ibcon#about to read 5, iclass 36, count 0 2006.162.07:48:39.97#ibcon#read 5, iclass 36, count 0 2006.162.07:48:39.97#ibcon#about to read 6, iclass 36, count 0 2006.162.07:48:39.97#ibcon#read 6, iclass 36, count 0 2006.162.07:48:39.97#ibcon#end of sib2, iclass 36, count 0 2006.162.07:48:39.97#ibcon#*mode == 0, iclass 36, count 0 2006.162.07:48:39.97#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.162.07:48:39.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.07:48:39.97#ibcon#*before write, iclass 36, count 0 2006.162.07:48:39.97#ibcon#enter sib2, iclass 36, count 0 2006.162.07:48:39.97#ibcon#flushed, iclass 36, count 0 2006.162.07:48:39.97#ibcon#about to write, iclass 36, count 0 2006.162.07:48:39.97#ibcon#wrote, iclass 36, count 0 2006.162.07:48:39.97#ibcon#about to read 3, iclass 36, count 0 2006.162.07:48:40.02#ibcon#read 3, iclass 36, count 0 2006.162.07:48:40.02#ibcon#about to read 4, iclass 36, count 0 2006.162.07:48:40.02#ibcon#read 4, iclass 36, count 0 2006.162.07:48:40.02#ibcon#about to read 5, iclass 36, count 0 2006.162.07:48:40.02#ibcon#read 5, iclass 36, count 0 2006.162.07:48:40.02#ibcon#about to read 6, iclass 36, count 0 2006.162.07:48:40.02#ibcon#read 6, iclass 36, count 0 2006.162.07:48:40.02#ibcon#end of sib2, iclass 36, count 0 2006.162.07:48:40.02#ibcon#*after write, iclass 36, count 0 2006.162.07:48:40.02#ibcon#*before return 0, iclass 36, count 0 2006.162.07:48:40.02#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:48:40.02#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:48:40.02#ibcon#about to clear, iclass 36 cls_cnt 0 2006.162.07:48:40.02#ibcon#cleared, iclass 36 cls_cnt 0 2006.162.07:48:40.02$vc4f8/va=1,8 2006.162.07:48:40.02#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.162.07:48:40.02#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.162.07:48:40.02#ibcon#ireg 11 cls_cnt 2 2006.162.07:48:40.02#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:48:40.02#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:48:40.02#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:48:40.02#ibcon#enter wrdev, iclass 38, count 2 2006.162.07:48:40.02#ibcon#first serial, iclass 38, count 2 2006.162.07:48:40.02#ibcon#enter sib2, iclass 38, count 2 2006.162.07:48:40.02#ibcon#flushed, iclass 38, count 2 2006.162.07:48:40.02#ibcon#about to write, iclass 38, count 2 2006.162.07:48:40.02#ibcon#wrote, iclass 38, count 2 2006.162.07:48:40.02#ibcon#about to read 3, iclass 38, count 2 2006.162.07:48:40.04#ibcon#read 3, iclass 38, count 2 2006.162.07:48:40.04#ibcon#about to read 4, iclass 38, count 2 2006.162.07:48:40.04#ibcon#read 4, iclass 38, count 2 2006.162.07:48:40.04#ibcon#about to read 5, iclass 38, count 2 2006.162.07:48:40.04#ibcon#read 5, iclass 38, count 2 2006.162.07:48:40.04#ibcon#about to read 6, iclass 38, count 2 2006.162.07:48:40.04#ibcon#read 6, iclass 38, count 2 2006.162.07:48:40.04#ibcon#end of sib2, iclass 38, count 2 2006.162.07:48:40.04#ibcon#*mode == 0, iclass 38, count 2 2006.162.07:48:40.04#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.162.07:48:40.04#ibcon#[25=AT01-08\r\n] 2006.162.07:48:40.04#ibcon#*before write, iclass 38, count 2 2006.162.07:48:40.04#ibcon#enter sib2, iclass 38, count 2 2006.162.07:48:40.04#ibcon#flushed, iclass 38, count 2 2006.162.07:48:40.04#ibcon#about to write, iclass 38, count 2 2006.162.07:48:40.04#ibcon#wrote, iclass 38, count 2 2006.162.07:48:40.04#ibcon#about to read 3, iclass 38, count 2 2006.162.07:48:40.08#ibcon#read 3, iclass 38, count 2 2006.162.07:48:40.08#ibcon#about to read 4, iclass 38, count 2 2006.162.07:48:40.08#ibcon#read 4, iclass 38, count 2 2006.162.07:48:40.08#ibcon#about to read 5, iclass 38, count 2 2006.162.07:48:40.08#ibcon#read 5, iclass 38, count 2 2006.162.07:48:40.08#ibcon#about to read 6, iclass 38, count 2 2006.162.07:48:40.08#ibcon#read 6, iclass 38, count 2 2006.162.07:48:40.08#ibcon#end of sib2, iclass 38, count 2 2006.162.07:48:40.08#ibcon#*after write, iclass 38, count 2 2006.162.07:48:40.08#ibcon#*before return 0, iclass 38, count 2 2006.162.07:48:40.08#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:48:40.08#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:48:40.08#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.162.07:48:40.08#ibcon#ireg 7 cls_cnt 0 2006.162.07:48:40.08#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:48:40.20#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:48:40.20#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:48:40.20#ibcon#enter wrdev, iclass 38, count 0 2006.162.07:48:40.20#ibcon#first serial, iclass 38, count 0 2006.162.07:48:40.20#ibcon#enter sib2, iclass 38, count 0 2006.162.07:48:40.20#ibcon#flushed, iclass 38, count 0 2006.162.07:48:40.20#ibcon#about to write, iclass 38, count 0 2006.162.07:48:40.20#ibcon#wrote, iclass 38, count 0 2006.162.07:48:40.20#ibcon#about to read 3, iclass 38, count 0 2006.162.07:48:40.22#ibcon#read 3, iclass 38, count 0 2006.162.07:48:40.22#ibcon#about to read 4, iclass 38, count 0 2006.162.07:48:40.22#ibcon#read 4, iclass 38, count 0 2006.162.07:48:40.22#ibcon#about to read 5, iclass 38, count 0 2006.162.07:48:40.22#ibcon#read 5, iclass 38, count 0 2006.162.07:48:40.22#ibcon#about to read 6, iclass 38, count 0 2006.162.07:48:40.22#ibcon#read 6, iclass 38, count 0 2006.162.07:48:40.22#ibcon#end of sib2, iclass 38, count 0 2006.162.07:48:40.22#ibcon#*mode == 0, iclass 38, count 0 2006.162.07:48:40.22#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.162.07:48:40.22#ibcon#[25=USB\r\n] 2006.162.07:48:40.22#ibcon#*before write, iclass 38, count 0 2006.162.07:48:40.22#ibcon#enter sib2, iclass 38, count 0 2006.162.07:48:40.22#ibcon#flushed, iclass 38, count 0 2006.162.07:48:40.22#ibcon#about to write, iclass 38, count 0 2006.162.07:48:40.22#ibcon#wrote, iclass 38, count 0 2006.162.07:48:40.22#ibcon#about to read 3, iclass 38, count 0 2006.162.07:48:40.25#ibcon#read 3, iclass 38, count 0 2006.162.07:48:40.25#ibcon#about to read 4, iclass 38, count 0 2006.162.07:48:40.25#ibcon#read 4, iclass 38, count 0 2006.162.07:48:40.25#ibcon#about to read 5, iclass 38, count 0 2006.162.07:48:40.25#ibcon#read 5, iclass 38, count 0 2006.162.07:48:40.25#ibcon#about to read 6, iclass 38, count 0 2006.162.07:48:40.25#ibcon#read 6, iclass 38, count 0 2006.162.07:48:40.25#ibcon#end of sib2, iclass 38, count 0 2006.162.07:48:40.25#ibcon#*after write, iclass 38, count 0 2006.162.07:48:40.25#ibcon#*before return 0, iclass 38, count 0 2006.162.07:48:40.25#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:48:40.25#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:48:40.25#ibcon#about to clear, iclass 38 cls_cnt 0 2006.162.07:48:40.25#ibcon#cleared, iclass 38 cls_cnt 0 2006.162.07:48:40.25$vc4f8/valo=2,572.99 2006.162.07:48:40.25#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.162.07:48:40.25#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.162.07:48:40.25#ibcon#ireg 17 cls_cnt 0 2006.162.07:48:40.25#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:48:40.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:48:40.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:48:40.25#ibcon#enter wrdev, iclass 40, count 0 2006.162.07:48:40.25#ibcon#first serial, iclass 40, count 0 2006.162.07:48:40.25#ibcon#enter sib2, iclass 40, count 0 2006.162.07:48:40.25#ibcon#flushed, iclass 40, count 0 2006.162.07:48:40.25#ibcon#about to write, iclass 40, count 0 2006.162.07:48:40.25#ibcon#wrote, iclass 40, count 0 2006.162.07:48:40.25#ibcon#about to read 3, iclass 40, count 0 2006.162.07:48:40.27#ibcon#read 3, iclass 40, count 0 2006.162.07:48:40.27#ibcon#about to read 4, iclass 40, count 0 2006.162.07:48:40.27#ibcon#read 4, iclass 40, count 0 2006.162.07:48:40.27#ibcon#about to read 5, iclass 40, count 0 2006.162.07:48:40.27#ibcon#read 5, iclass 40, count 0 2006.162.07:48:40.27#ibcon#about to read 6, iclass 40, count 0 2006.162.07:48:40.27#ibcon#read 6, iclass 40, count 0 2006.162.07:48:40.27#ibcon#end of sib2, iclass 40, count 0 2006.162.07:48:40.27#ibcon#*mode == 0, iclass 40, count 0 2006.162.07:48:40.27#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.162.07:48:40.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.07:48:40.27#ibcon#*before write, iclass 40, count 0 2006.162.07:48:40.27#ibcon#enter sib2, iclass 40, count 0 2006.162.07:48:40.27#ibcon#flushed, iclass 40, count 0 2006.162.07:48:40.27#ibcon#about to write, iclass 40, count 0 2006.162.07:48:40.27#ibcon#wrote, iclass 40, count 0 2006.162.07:48:40.27#ibcon#about to read 3, iclass 40, count 0 2006.162.07:48:40.31#ibcon#read 3, iclass 40, count 0 2006.162.07:48:40.31#ibcon#about to read 4, iclass 40, count 0 2006.162.07:48:40.31#ibcon#read 4, iclass 40, count 0 2006.162.07:48:40.31#ibcon#about to read 5, iclass 40, count 0 2006.162.07:48:40.31#ibcon#read 5, iclass 40, count 0 2006.162.07:48:40.31#ibcon#about to read 6, iclass 40, count 0 2006.162.07:48:40.31#ibcon#read 6, iclass 40, count 0 2006.162.07:48:40.31#ibcon#end of sib2, iclass 40, count 0 2006.162.07:48:40.31#ibcon#*after write, iclass 40, count 0 2006.162.07:48:40.31#ibcon#*before return 0, iclass 40, count 0 2006.162.07:48:40.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:48:40.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:48:40.31#ibcon#about to clear, iclass 40 cls_cnt 0 2006.162.07:48:40.31#ibcon#cleared, iclass 40 cls_cnt 0 2006.162.07:48:40.31$vc4f8/va=2,7 2006.162.07:48:40.31#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.162.07:48:40.31#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.162.07:48:40.31#ibcon#ireg 11 cls_cnt 2 2006.162.07:48:40.31#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:48:40.37#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:48:40.37#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:48:40.37#ibcon#enter wrdev, iclass 4, count 2 2006.162.07:48:40.37#ibcon#first serial, iclass 4, count 2 2006.162.07:48:40.37#ibcon#enter sib2, iclass 4, count 2 2006.162.07:48:40.37#ibcon#flushed, iclass 4, count 2 2006.162.07:48:40.37#ibcon#about to write, iclass 4, count 2 2006.162.07:48:40.37#ibcon#wrote, iclass 4, count 2 2006.162.07:48:40.37#ibcon#about to read 3, iclass 4, count 2 2006.162.07:48:40.39#ibcon#read 3, iclass 4, count 2 2006.162.07:48:40.39#ibcon#about to read 4, iclass 4, count 2 2006.162.07:48:40.39#ibcon#read 4, iclass 4, count 2 2006.162.07:48:40.39#ibcon#about to read 5, iclass 4, count 2 2006.162.07:48:40.39#ibcon#read 5, iclass 4, count 2 2006.162.07:48:40.39#ibcon#about to read 6, iclass 4, count 2 2006.162.07:48:40.39#ibcon#read 6, iclass 4, count 2 2006.162.07:48:40.39#ibcon#end of sib2, iclass 4, count 2 2006.162.07:48:40.39#ibcon#*mode == 0, iclass 4, count 2 2006.162.07:48:40.39#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.162.07:48:40.39#ibcon#[25=AT02-07\r\n] 2006.162.07:48:40.39#ibcon#*before write, iclass 4, count 2 2006.162.07:48:40.39#ibcon#enter sib2, iclass 4, count 2 2006.162.07:48:40.39#ibcon#flushed, iclass 4, count 2 2006.162.07:48:40.39#ibcon#about to write, iclass 4, count 2 2006.162.07:48:40.39#ibcon#wrote, iclass 4, count 2 2006.162.07:48:40.39#ibcon#about to read 3, iclass 4, count 2 2006.162.07:48:40.42#ibcon#read 3, iclass 4, count 2 2006.162.07:48:40.42#ibcon#about to read 4, iclass 4, count 2 2006.162.07:48:40.42#ibcon#read 4, iclass 4, count 2 2006.162.07:48:40.42#ibcon#about to read 5, iclass 4, count 2 2006.162.07:48:40.42#ibcon#read 5, iclass 4, count 2 2006.162.07:48:40.42#ibcon#about to read 6, iclass 4, count 2 2006.162.07:48:40.42#ibcon#read 6, iclass 4, count 2 2006.162.07:48:40.42#ibcon#end of sib2, iclass 4, count 2 2006.162.07:48:40.42#ibcon#*after write, iclass 4, count 2 2006.162.07:48:40.42#ibcon#*before return 0, iclass 4, count 2 2006.162.07:48:40.42#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:48:40.42#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:48:40.42#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.162.07:48:40.42#ibcon#ireg 7 cls_cnt 0 2006.162.07:48:40.42#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:48:40.54#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:48:40.54#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:48:40.54#ibcon#enter wrdev, iclass 4, count 0 2006.162.07:48:40.54#ibcon#first serial, iclass 4, count 0 2006.162.07:48:40.54#ibcon#enter sib2, iclass 4, count 0 2006.162.07:48:40.54#ibcon#flushed, iclass 4, count 0 2006.162.07:48:40.54#ibcon#about to write, iclass 4, count 0 2006.162.07:48:40.54#ibcon#wrote, iclass 4, count 0 2006.162.07:48:40.54#ibcon#about to read 3, iclass 4, count 0 2006.162.07:48:40.56#ibcon#read 3, iclass 4, count 0 2006.162.07:48:40.56#ibcon#about to read 4, iclass 4, count 0 2006.162.07:48:40.56#ibcon#read 4, iclass 4, count 0 2006.162.07:48:40.56#ibcon#about to read 5, iclass 4, count 0 2006.162.07:48:40.56#ibcon#read 5, iclass 4, count 0 2006.162.07:48:40.56#ibcon#about to read 6, iclass 4, count 0 2006.162.07:48:40.56#ibcon#read 6, iclass 4, count 0 2006.162.07:48:40.56#ibcon#end of sib2, iclass 4, count 0 2006.162.07:48:40.56#ibcon#*mode == 0, iclass 4, count 0 2006.162.07:48:40.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.162.07:48:40.56#ibcon#[25=USB\r\n] 2006.162.07:48:40.56#ibcon#*before write, iclass 4, count 0 2006.162.07:48:40.56#ibcon#enter sib2, iclass 4, count 0 2006.162.07:48:40.56#ibcon#flushed, iclass 4, count 0 2006.162.07:48:40.56#ibcon#about to write, iclass 4, count 0 2006.162.07:48:40.56#ibcon#wrote, iclass 4, count 0 2006.162.07:48:40.56#ibcon#about to read 3, iclass 4, count 0 2006.162.07:48:40.59#ibcon#read 3, iclass 4, count 0 2006.162.07:48:40.59#ibcon#about to read 4, iclass 4, count 0 2006.162.07:48:40.59#ibcon#read 4, iclass 4, count 0 2006.162.07:48:40.59#ibcon#about to read 5, iclass 4, count 0 2006.162.07:48:40.59#ibcon#read 5, iclass 4, count 0 2006.162.07:48:40.59#ibcon#about to read 6, iclass 4, count 0 2006.162.07:48:40.59#ibcon#read 6, iclass 4, count 0 2006.162.07:48:40.59#ibcon#end of sib2, iclass 4, count 0 2006.162.07:48:40.59#ibcon#*after write, iclass 4, count 0 2006.162.07:48:40.59#ibcon#*before return 0, iclass 4, count 0 2006.162.07:48:40.59#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:48:40.59#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:48:40.59#ibcon#about to clear, iclass 4 cls_cnt 0 2006.162.07:48:40.59#ibcon#cleared, iclass 4 cls_cnt 0 2006.162.07:48:40.59$vc4f8/valo=3,672.99 2006.162.07:48:40.59#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.162.07:48:40.59#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.162.07:48:40.59#ibcon#ireg 17 cls_cnt 0 2006.162.07:48:40.59#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:48:40.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:48:40.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:48:40.59#ibcon#enter wrdev, iclass 6, count 0 2006.162.07:48:40.59#ibcon#first serial, iclass 6, count 0 2006.162.07:48:40.59#ibcon#enter sib2, iclass 6, count 0 2006.162.07:48:40.59#ibcon#flushed, iclass 6, count 0 2006.162.07:48:40.59#ibcon#about to write, iclass 6, count 0 2006.162.07:48:40.59#ibcon#wrote, iclass 6, count 0 2006.162.07:48:40.59#ibcon#about to read 3, iclass 6, count 0 2006.162.07:48:40.61#ibcon#read 3, iclass 6, count 0 2006.162.07:48:40.61#ibcon#about to read 4, iclass 6, count 0 2006.162.07:48:40.61#ibcon#read 4, iclass 6, count 0 2006.162.07:48:40.61#ibcon#about to read 5, iclass 6, count 0 2006.162.07:48:40.61#ibcon#read 5, iclass 6, count 0 2006.162.07:48:40.61#ibcon#about to read 6, iclass 6, count 0 2006.162.07:48:40.61#ibcon#read 6, iclass 6, count 0 2006.162.07:48:40.61#ibcon#end of sib2, iclass 6, count 0 2006.162.07:48:40.61#ibcon#*mode == 0, iclass 6, count 0 2006.162.07:48:40.61#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.162.07:48:40.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.07:48:40.61#ibcon#*before write, iclass 6, count 0 2006.162.07:48:40.61#ibcon#enter sib2, iclass 6, count 0 2006.162.07:48:40.61#ibcon#flushed, iclass 6, count 0 2006.162.07:48:40.61#ibcon#about to write, iclass 6, count 0 2006.162.07:48:40.61#ibcon#wrote, iclass 6, count 0 2006.162.07:48:40.61#ibcon#about to read 3, iclass 6, count 0 2006.162.07:48:40.65#ibcon#read 3, iclass 6, count 0 2006.162.07:48:40.65#ibcon#about to read 4, iclass 6, count 0 2006.162.07:48:40.65#ibcon#read 4, iclass 6, count 0 2006.162.07:48:40.65#ibcon#about to read 5, iclass 6, count 0 2006.162.07:48:40.65#ibcon#read 5, iclass 6, count 0 2006.162.07:48:40.65#ibcon#about to read 6, iclass 6, count 0 2006.162.07:48:40.65#ibcon#read 6, iclass 6, count 0 2006.162.07:48:40.65#ibcon#end of sib2, iclass 6, count 0 2006.162.07:48:40.65#ibcon#*after write, iclass 6, count 0 2006.162.07:48:40.65#ibcon#*before return 0, iclass 6, count 0 2006.162.07:48:40.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:48:40.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:48:40.65#ibcon#about to clear, iclass 6 cls_cnt 0 2006.162.07:48:40.65#ibcon#cleared, iclass 6 cls_cnt 0 2006.162.07:48:40.65$vc4f8/va=3,6 2006.162.07:48:40.65#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.162.07:48:40.65#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.162.07:48:40.65#ibcon#ireg 11 cls_cnt 2 2006.162.07:48:40.65#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:48:40.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:48:40.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:48:40.71#ibcon#enter wrdev, iclass 10, count 2 2006.162.07:48:40.71#ibcon#first serial, iclass 10, count 2 2006.162.07:48:40.71#ibcon#enter sib2, iclass 10, count 2 2006.162.07:48:40.71#ibcon#flushed, iclass 10, count 2 2006.162.07:48:40.71#ibcon#about to write, iclass 10, count 2 2006.162.07:48:40.71#ibcon#wrote, iclass 10, count 2 2006.162.07:48:40.71#ibcon#about to read 3, iclass 10, count 2 2006.162.07:48:40.73#ibcon#read 3, iclass 10, count 2 2006.162.07:48:40.73#ibcon#about to read 4, iclass 10, count 2 2006.162.07:48:40.73#ibcon#read 4, iclass 10, count 2 2006.162.07:48:40.73#ibcon#about to read 5, iclass 10, count 2 2006.162.07:48:40.73#ibcon#read 5, iclass 10, count 2 2006.162.07:48:40.73#ibcon#about to read 6, iclass 10, count 2 2006.162.07:48:40.73#ibcon#read 6, iclass 10, count 2 2006.162.07:48:40.73#ibcon#end of sib2, iclass 10, count 2 2006.162.07:48:40.73#ibcon#*mode == 0, iclass 10, count 2 2006.162.07:48:40.73#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.162.07:48:40.73#ibcon#[25=AT03-06\r\n] 2006.162.07:48:40.73#ibcon#*before write, iclass 10, count 2 2006.162.07:48:40.73#ibcon#enter sib2, iclass 10, count 2 2006.162.07:48:40.73#ibcon#flushed, iclass 10, count 2 2006.162.07:48:40.73#ibcon#about to write, iclass 10, count 2 2006.162.07:48:40.73#ibcon#wrote, iclass 10, count 2 2006.162.07:48:40.73#ibcon#about to read 3, iclass 10, count 2 2006.162.07:48:40.76#ibcon#read 3, iclass 10, count 2 2006.162.07:48:40.76#ibcon#about to read 4, iclass 10, count 2 2006.162.07:48:40.76#ibcon#read 4, iclass 10, count 2 2006.162.07:48:40.76#ibcon#about to read 5, iclass 10, count 2 2006.162.07:48:40.76#ibcon#read 5, iclass 10, count 2 2006.162.07:48:40.76#ibcon#about to read 6, iclass 10, count 2 2006.162.07:48:40.76#ibcon#read 6, iclass 10, count 2 2006.162.07:48:40.76#ibcon#end of sib2, iclass 10, count 2 2006.162.07:48:40.76#ibcon#*after write, iclass 10, count 2 2006.162.07:48:40.76#ibcon#*before return 0, iclass 10, count 2 2006.162.07:48:40.76#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:48:40.76#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:48:40.76#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.162.07:48:40.76#ibcon#ireg 7 cls_cnt 0 2006.162.07:48:40.76#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:48:40.88#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:48:40.88#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:48:40.88#ibcon#enter wrdev, iclass 10, count 0 2006.162.07:48:40.88#ibcon#first serial, iclass 10, count 0 2006.162.07:48:40.88#ibcon#enter sib2, iclass 10, count 0 2006.162.07:48:40.88#ibcon#flushed, iclass 10, count 0 2006.162.07:48:40.88#ibcon#about to write, iclass 10, count 0 2006.162.07:48:40.88#ibcon#wrote, iclass 10, count 0 2006.162.07:48:40.88#ibcon#about to read 3, iclass 10, count 0 2006.162.07:48:40.90#ibcon#read 3, iclass 10, count 0 2006.162.07:48:40.90#ibcon#about to read 4, iclass 10, count 0 2006.162.07:48:40.90#ibcon#read 4, iclass 10, count 0 2006.162.07:48:40.90#ibcon#about to read 5, iclass 10, count 0 2006.162.07:48:40.90#ibcon#read 5, iclass 10, count 0 2006.162.07:48:40.90#ibcon#about to read 6, iclass 10, count 0 2006.162.07:48:40.90#ibcon#read 6, iclass 10, count 0 2006.162.07:48:40.90#ibcon#end of sib2, iclass 10, count 0 2006.162.07:48:40.90#ibcon#*mode == 0, iclass 10, count 0 2006.162.07:48:40.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.162.07:48:40.90#ibcon#[25=USB\r\n] 2006.162.07:48:40.90#ibcon#*before write, iclass 10, count 0 2006.162.07:48:40.90#ibcon#enter sib2, iclass 10, count 0 2006.162.07:48:40.90#ibcon#flushed, iclass 10, count 0 2006.162.07:48:40.90#ibcon#about to write, iclass 10, count 0 2006.162.07:48:40.90#ibcon#wrote, iclass 10, count 0 2006.162.07:48:40.90#ibcon#about to read 3, iclass 10, count 0 2006.162.07:48:40.93#ibcon#read 3, iclass 10, count 0 2006.162.07:48:40.93#ibcon#about to read 4, iclass 10, count 0 2006.162.07:48:40.93#ibcon#read 4, iclass 10, count 0 2006.162.07:48:40.93#ibcon#about to read 5, iclass 10, count 0 2006.162.07:48:40.93#ibcon#read 5, iclass 10, count 0 2006.162.07:48:40.93#ibcon#about to read 6, iclass 10, count 0 2006.162.07:48:40.93#ibcon#read 6, iclass 10, count 0 2006.162.07:48:40.93#ibcon#end of sib2, iclass 10, count 0 2006.162.07:48:40.93#ibcon#*after write, iclass 10, count 0 2006.162.07:48:40.93#ibcon#*before return 0, iclass 10, count 0 2006.162.07:48:40.93#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:48:40.93#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:48:40.93#ibcon#about to clear, iclass 10 cls_cnt 0 2006.162.07:48:40.93#ibcon#cleared, iclass 10 cls_cnt 0 2006.162.07:48:40.93$vc4f8/valo=4,832.99 2006.162.07:48:40.93#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.162.07:48:40.93#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.162.07:48:40.93#ibcon#ireg 17 cls_cnt 0 2006.162.07:48:40.93#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:48:40.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:48:40.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:48:40.93#ibcon#enter wrdev, iclass 12, count 0 2006.162.07:48:40.93#ibcon#first serial, iclass 12, count 0 2006.162.07:48:40.93#ibcon#enter sib2, iclass 12, count 0 2006.162.07:48:40.93#ibcon#flushed, iclass 12, count 0 2006.162.07:48:40.93#ibcon#about to write, iclass 12, count 0 2006.162.07:48:40.93#ibcon#wrote, iclass 12, count 0 2006.162.07:48:40.93#ibcon#about to read 3, iclass 12, count 0 2006.162.07:48:40.95#ibcon#read 3, iclass 12, count 0 2006.162.07:48:40.95#ibcon#about to read 4, iclass 12, count 0 2006.162.07:48:40.95#ibcon#read 4, iclass 12, count 0 2006.162.07:48:40.95#ibcon#about to read 5, iclass 12, count 0 2006.162.07:48:40.95#ibcon#read 5, iclass 12, count 0 2006.162.07:48:40.95#ibcon#about to read 6, iclass 12, count 0 2006.162.07:48:40.95#ibcon#read 6, iclass 12, count 0 2006.162.07:48:40.95#ibcon#end of sib2, iclass 12, count 0 2006.162.07:48:40.95#ibcon#*mode == 0, iclass 12, count 0 2006.162.07:48:40.95#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.162.07:48:40.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.07:48:40.95#ibcon#*before write, iclass 12, count 0 2006.162.07:48:40.95#ibcon#enter sib2, iclass 12, count 0 2006.162.07:48:40.95#ibcon#flushed, iclass 12, count 0 2006.162.07:48:40.95#ibcon#about to write, iclass 12, count 0 2006.162.07:48:40.95#ibcon#wrote, iclass 12, count 0 2006.162.07:48:40.95#ibcon#about to read 3, iclass 12, count 0 2006.162.07:48:40.99#ibcon#read 3, iclass 12, count 0 2006.162.07:48:40.99#ibcon#about to read 4, iclass 12, count 0 2006.162.07:48:40.99#ibcon#read 4, iclass 12, count 0 2006.162.07:48:40.99#ibcon#about to read 5, iclass 12, count 0 2006.162.07:48:40.99#ibcon#read 5, iclass 12, count 0 2006.162.07:48:40.99#ibcon#about to read 6, iclass 12, count 0 2006.162.07:48:40.99#ibcon#read 6, iclass 12, count 0 2006.162.07:48:40.99#ibcon#end of sib2, iclass 12, count 0 2006.162.07:48:40.99#ibcon#*after write, iclass 12, count 0 2006.162.07:48:40.99#ibcon#*before return 0, iclass 12, count 0 2006.162.07:48:40.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:48:40.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:48:40.99#ibcon#about to clear, iclass 12 cls_cnt 0 2006.162.07:48:40.99#ibcon#cleared, iclass 12 cls_cnt 0 2006.162.07:48:40.99$vc4f8/va=4,7 2006.162.07:48:40.99#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.162.07:48:40.99#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.162.07:48:40.99#ibcon#ireg 11 cls_cnt 2 2006.162.07:48:40.99#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:48:41.05#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:48:41.05#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:48:41.05#ibcon#enter wrdev, iclass 14, count 2 2006.162.07:48:41.05#ibcon#first serial, iclass 14, count 2 2006.162.07:48:41.05#ibcon#enter sib2, iclass 14, count 2 2006.162.07:48:41.05#ibcon#flushed, iclass 14, count 2 2006.162.07:48:41.05#ibcon#about to write, iclass 14, count 2 2006.162.07:48:41.05#ibcon#wrote, iclass 14, count 2 2006.162.07:48:41.05#ibcon#about to read 3, iclass 14, count 2 2006.162.07:48:41.07#ibcon#read 3, iclass 14, count 2 2006.162.07:48:41.07#ibcon#about to read 4, iclass 14, count 2 2006.162.07:48:41.07#ibcon#read 4, iclass 14, count 2 2006.162.07:48:41.07#ibcon#about to read 5, iclass 14, count 2 2006.162.07:48:41.07#ibcon#read 5, iclass 14, count 2 2006.162.07:48:41.07#ibcon#about to read 6, iclass 14, count 2 2006.162.07:48:41.07#ibcon#read 6, iclass 14, count 2 2006.162.07:48:41.07#ibcon#end of sib2, iclass 14, count 2 2006.162.07:48:41.07#ibcon#*mode == 0, iclass 14, count 2 2006.162.07:48:41.07#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.162.07:48:41.07#ibcon#[25=AT04-07\r\n] 2006.162.07:48:41.07#ibcon#*before write, iclass 14, count 2 2006.162.07:48:41.07#ibcon#enter sib2, iclass 14, count 2 2006.162.07:48:41.07#ibcon#flushed, iclass 14, count 2 2006.162.07:48:41.07#ibcon#about to write, iclass 14, count 2 2006.162.07:48:41.07#ibcon#wrote, iclass 14, count 2 2006.162.07:48:41.07#ibcon#about to read 3, iclass 14, count 2 2006.162.07:48:41.10#ibcon#read 3, iclass 14, count 2 2006.162.07:48:41.10#ibcon#about to read 4, iclass 14, count 2 2006.162.07:48:41.10#ibcon#read 4, iclass 14, count 2 2006.162.07:48:41.10#ibcon#about to read 5, iclass 14, count 2 2006.162.07:48:41.10#ibcon#read 5, iclass 14, count 2 2006.162.07:48:41.10#ibcon#about to read 6, iclass 14, count 2 2006.162.07:48:41.10#ibcon#read 6, iclass 14, count 2 2006.162.07:48:41.10#ibcon#end of sib2, iclass 14, count 2 2006.162.07:48:41.10#ibcon#*after write, iclass 14, count 2 2006.162.07:48:41.10#ibcon#*before return 0, iclass 14, count 2 2006.162.07:48:41.10#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:48:41.10#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:48:41.10#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.162.07:48:41.10#ibcon#ireg 7 cls_cnt 0 2006.162.07:48:41.10#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:48:41.22#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:48:41.22#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:48:41.22#ibcon#enter wrdev, iclass 14, count 0 2006.162.07:48:41.22#ibcon#first serial, iclass 14, count 0 2006.162.07:48:41.22#ibcon#enter sib2, iclass 14, count 0 2006.162.07:48:41.22#ibcon#flushed, iclass 14, count 0 2006.162.07:48:41.22#ibcon#about to write, iclass 14, count 0 2006.162.07:48:41.22#ibcon#wrote, iclass 14, count 0 2006.162.07:48:41.22#ibcon#about to read 3, iclass 14, count 0 2006.162.07:48:41.24#ibcon#read 3, iclass 14, count 0 2006.162.07:48:41.24#ibcon#about to read 4, iclass 14, count 0 2006.162.07:48:41.24#ibcon#read 4, iclass 14, count 0 2006.162.07:48:41.24#ibcon#about to read 5, iclass 14, count 0 2006.162.07:48:41.24#ibcon#read 5, iclass 14, count 0 2006.162.07:48:41.24#ibcon#about to read 6, iclass 14, count 0 2006.162.07:48:41.24#ibcon#read 6, iclass 14, count 0 2006.162.07:48:41.24#ibcon#end of sib2, iclass 14, count 0 2006.162.07:48:41.24#ibcon#*mode == 0, iclass 14, count 0 2006.162.07:48:41.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.07:48:41.24#ibcon#[25=USB\r\n] 2006.162.07:48:41.24#ibcon#*before write, iclass 14, count 0 2006.162.07:48:41.24#ibcon#enter sib2, iclass 14, count 0 2006.162.07:48:41.24#ibcon#flushed, iclass 14, count 0 2006.162.07:48:41.24#ibcon#about to write, iclass 14, count 0 2006.162.07:48:41.24#ibcon#wrote, iclass 14, count 0 2006.162.07:48:41.24#ibcon#about to read 3, iclass 14, count 0 2006.162.07:48:41.27#ibcon#read 3, iclass 14, count 0 2006.162.07:48:41.27#ibcon#about to read 4, iclass 14, count 0 2006.162.07:48:41.27#ibcon#read 4, iclass 14, count 0 2006.162.07:48:41.27#ibcon#about to read 5, iclass 14, count 0 2006.162.07:48:41.27#ibcon#read 5, iclass 14, count 0 2006.162.07:48:41.27#ibcon#about to read 6, iclass 14, count 0 2006.162.07:48:41.27#ibcon#read 6, iclass 14, count 0 2006.162.07:48:41.27#ibcon#end of sib2, iclass 14, count 0 2006.162.07:48:41.27#ibcon#*after write, iclass 14, count 0 2006.162.07:48:41.27#ibcon#*before return 0, iclass 14, count 0 2006.162.07:48:41.27#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:48:41.27#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:48:41.27#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.07:48:41.27#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.07:48:41.27$vc4f8/valo=5,652.99 2006.162.07:48:41.27#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.162.07:48:41.27#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.162.07:48:41.27#ibcon#ireg 17 cls_cnt 0 2006.162.07:48:41.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:48:41.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:48:41.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:48:41.27#ibcon#enter wrdev, iclass 16, count 0 2006.162.07:48:41.27#ibcon#first serial, iclass 16, count 0 2006.162.07:48:41.27#ibcon#enter sib2, iclass 16, count 0 2006.162.07:48:41.27#ibcon#flushed, iclass 16, count 0 2006.162.07:48:41.27#ibcon#about to write, iclass 16, count 0 2006.162.07:48:41.27#ibcon#wrote, iclass 16, count 0 2006.162.07:48:41.27#ibcon#about to read 3, iclass 16, count 0 2006.162.07:48:41.29#ibcon#read 3, iclass 16, count 0 2006.162.07:48:41.29#ibcon#about to read 4, iclass 16, count 0 2006.162.07:48:41.29#ibcon#read 4, iclass 16, count 0 2006.162.07:48:41.29#ibcon#about to read 5, iclass 16, count 0 2006.162.07:48:41.29#ibcon#read 5, iclass 16, count 0 2006.162.07:48:41.29#ibcon#about to read 6, iclass 16, count 0 2006.162.07:48:41.29#ibcon#read 6, iclass 16, count 0 2006.162.07:48:41.29#ibcon#end of sib2, iclass 16, count 0 2006.162.07:48:41.29#ibcon#*mode == 0, iclass 16, count 0 2006.162.07:48:41.29#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.162.07:48:41.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.07:48:41.29#ibcon#*before write, iclass 16, count 0 2006.162.07:48:41.29#ibcon#enter sib2, iclass 16, count 0 2006.162.07:48:41.29#ibcon#flushed, iclass 16, count 0 2006.162.07:48:41.29#ibcon#about to write, iclass 16, count 0 2006.162.07:48:41.29#ibcon#wrote, iclass 16, count 0 2006.162.07:48:41.29#ibcon#about to read 3, iclass 16, count 0 2006.162.07:48:41.33#ibcon#read 3, iclass 16, count 0 2006.162.07:48:41.33#ibcon#about to read 4, iclass 16, count 0 2006.162.07:48:41.33#ibcon#read 4, iclass 16, count 0 2006.162.07:48:41.33#ibcon#about to read 5, iclass 16, count 0 2006.162.07:48:41.33#ibcon#read 5, iclass 16, count 0 2006.162.07:48:41.33#ibcon#about to read 6, iclass 16, count 0 2006.162.07:48:41.33#ibcon#read 6, iclass 16, count 0 2006.162.07:48:41.33#ibcon#end of sib2, iclass 16, count 0 2006.162.07:48:41.33#ibcon#*after write, iclass 16, count 0 2006.162.07:48:41.33#ibcon#*before return 0, iclass 16, count 0 2006.162.07:48:41.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:48:41.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:48:41.33#ibcon#about to clear, iclass 16 cls_cnt 0 2006.162.07:48:41.33#ibcon#cleared, iclass 16 cls_cnt 0 2006.162.07:48:41.33$vc4f8/va=5,7 2006.162.07:48:41.33#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.162.07:48:41.33#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.162.07:48:41.33#ibcon#ireg 11 cls_cnt 2 2006.162.07:48:41.33#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:48:41.39#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:48:41.39#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:48:41.39#ibcon#enter wrdev, iclass 18, count 2 2006.162.07:48:41.39#ibcon#first serial, iclass 18, count 2 2006.162.07:48:41.39#ibcon#enter sib2, iclass 18, count 2 2006.162.07:48:41.39#ibcon#flushed, iclass 18, count 2 2006.162.07:48:41.39#ibcon#about to write, iclass 18, count 2 2006.162.07:48:41.39#ibcon#wrote, iclass 18, count 2 2006.162.07:48:41.39#ibcon#about to read 3, iclass 18, count 2 2006.162.07:48:41.41#ibcon#read 3, iclass 18, count 2 2006.162.07:48:41.41#ibcon#about to read 4, iclass 18, count 2 2006.162.07:48:41.41#ibcon#read 4, iclass 18, count 2 2006.162.07:48:41.41#ibcon#about to read 5, iclass 18, count 2 2006.162.07:48:41.41#ibcon#read 5, iclass 18, count 2 2006.162.07:48:41.41#ibcon#about to read 6, iclass 18, count 2 2006.162.07:48:41.41#ibcon#read 6, iclass 18, count 2 2006.162.07:48:41.41#ibcon#end of sib2, iclass 18, count 2 2006.162.07:48:41.41#ibcon#*mode == 0, iclass 18, count 2 2006.162.07:48:41.41#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.162.07:48:41.41#ibcon#[25=AT05-07\r\n] 2006.162.07:48:41.41#ibcon#*before write, iclass 18, count 2 2006.162.07:48:41.41#ibcon#enter sib2, iclass 18, count 2 2006.162.07:48:41.41#ibcon#flushed, iclass 18, count 2 2006.162.07:48:41.41#ibcon#about to write, iclass 18, count 2 2006.162.07:48:41.41#ibcon#wrote, iclass 18, count 2 2006.162.07:48:41.41#ibcon#about to read 3, iclass 18, count 2 2006.162.07:48:41.44#ibcon#read 3, iclass 18, count 2 2006.162.07:48:41.44#ibcon#about to read 4, iclass 18, count 2 2006.162.07:48:41.44#ibcon#read 4, iclass 18, count 2 2006.162.07:48:41.44#ibcon#about to read 5, iclass 18, count 2 2006.162.07:48:41.44#ibcon#read 5, iclass 18, count 2 2006.162.07:48:41.44#ibcon#about to read 6, iclass 18, count 2 2006.162.07:48:41.44#ibcon#read 6, iclass 18, count 2 2006.162.07:48:41.44#ibcon#end of sib2, iclass 18, count 2 2006.162.07:48:41.44#ibcon#*after write, iclass 18, count 2 2006.162.07:48:41.44#ibcon#*before return 0, iclass 18, count 2 2006.162.07:48:41.44#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:48:41.44#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:48:41.44#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.162.07:48:41.44#ibcon#ireg 7 cls_cnt 0 2006.162.07:48:41.44#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:48:41.56#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:48:41.56#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:48:41.56#ibcon#enter wrdev, iclass 18, count 0 2006.162.07:48:41.56#ibcon#first serial, iclass 18, count 0 2006.162.07:48:41.56#ibcon#enter sib2, iclass 18, count 0 2006.162.07:48:41.56#ibcon#flushed, iclass 18, count 0 2006.162.07:48:41.56#ibcon#about to write, iclass 18, count 0 2006.162.07:48:41.56#ibcon#wrote, iclass 18, count 0 2006.162.07:48:41.56#ibcon#about to read 3, iclass 18, count 0 2006.162.07:48:41.58#ibcon#read 3, iclass 18, count 0 2006.162.07:48:41.58#ibcon#about to read 4, iclass 18, count 0 2006.162.07:48:41.58#ibcon#read 4, iclass 18, count 0 2006.162.07:48:41.58#ibcon#about to read 5, iclass 18, count 0 2006.162.07:48:41.58#ibcon#read 5, iclass 18, count 0 2006.162.07:48:41.58#ibcon#about to read 6, iclass 18, count 0 2006.162.07:48:41.58#ibcon#read 6, iclass 18, count 0 2006.162.07:48:41.58#ibcon#end of sib2, iclass 18, count 0 2006.162.07:48:41.58#ibcon#*mode == 0, iclass 18, count 0 2006.162.07:48:41.58#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.162.07:48:41.58#ibcon#[25=USB\r\n] 2006.162.07:48:41.58#ibcon#*before write, iclass 18, count 0 2006.162.07:48:41.58#ibcon#enter sib2, iclass 18, count 0 2006.162.07:48:41.58#ibcon#flushed, iclass 18, count 0 2006.162.07:48:41.58#ibcon#about to write, iclass 18, count 0 2006.162.07:48:41.58#ibcon#wrote, iclass 18, count 0 2006.162.07:48:41.58#ibcon#about to read 3, iclass 18, count 0 2006.162.07:48:41.61#ibcon#read 3, iclass 18, count 0 2006.162.07:48:41.61#ibcon#about to read 4, iclass 18, count 0 2006.162.07:48:41.61#ibcon#read 4, iclass 18, count 0 2006.162.07:48:41.61#ibcon#about to read 5, iclass 18, count 0 2006.162.07:48:41.61#ibcon#read 5, iclass 18, count 0 2006.162.07:48:41.61#ibcon#about to read 6, iclass 18, count 0 2006.162.07:48:41.61#ibcon#read 6, iclass 18, count 0 2006.162.07:48:41.61#ibcon#end of sib2, iclass 18, count 0 2006.162.07:48:41.61#ibcon#*after write, iclass 18, count 0 2006.162.07:48:41.61#ibcon#*before return 0, iclass 18, count 0 2006.162.07:48:41.61#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:48:41.61#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:48:41.61#ibcon#about to clear, iclass 18 cls_cnt 0 2006.162.07:48:41.61#ibcon#cleared, iclass 18 cls_cnt 0 2006.162.07:48:41.61$vc4f8/valo=6,772.99 2006.162.07:48:41.61#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.162.07:48:41.61#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.162.07:48:41.61#ibcon#ireg 17 cls_cnt 0 2006.162.07:48:41.61#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:48:41.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:48:41.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:48:41.61#ibcon#enter wrdev, iclass 20, count 0 2006.162.07:48:41.61#ibcon#first serial, iclass 20, count 0 2006.162.07:48:41.61#ibcon#enter sib2, iclass 20, count 0 2006.162.07:48:41.61#ibcon#flushed, iclass 20, count 0 2006.162.07:48:41.61#ibcon#about to write, iclass 20, count 0 2006.162.07:48:41.61#ibcon#wrote, iclass 20, count 0 2006.162.07:48:41.61#ibcon#about to read 3, iclass 20, count 0 2006.162.07:48:41.63#ibcon#read 3, iclass 20, count 0 2006.162.07:48:41.63#ibcon#about to read 4, iclass 20, count 0 2006.162.07:48:41.63#ibcon#read 4, iclass 20, count 0 2006.162.07:48:41.63#ibcon#about to read 5, iclass 20, count 0 2006.162.07:48:41.63#ibcon#read 5, iclass 20, count 0 2006.162.07:48:41.63#ibcon#about to read 6, iclass 20, count 0 2006.162.07:48:41.63#ibcon#read 6, iclass 20, count 0 2006.162.07:48:41.63#ibcon#end of sib2, iclass 20, count 0 2006.162.07:48:41.63#ibcon#*mode == 0, iclass 20, count 0 2006.162.07:48:41.63#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.07:48:41.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.07:48:41.63#ibcon#*before write, iclass 20, count 0 2006.162.07:48:41.63#ibcon#enter sib2, iclass 20, count 0 2006.162.07:48:41.63#ibcon#flushed, iclass 20, count 0 2006.162.07:48:41.63#ibcon#about to write, iclass 20, count 0 2006.162.07:48:41.63#ibcon#wrote, iclass 20, count 0 2006.162.07:48:41.63#ibcon#about to read 3, iclass 20, count 0 2006.162.07:48:41.67#ibcon#read 3, iclass 20, count 0 2006.162.07:48:41.67#ibcon#about to read 4, iclass 20, count 0 2006.162.07:48:41.67#ibcon#read 4, iclass 20, count 0 2006.162.07:48:41.67#ibcon#about to read 5, iclass 20, count 0 2006.162.07:48:41.67#ibcon#read 5, iclass 20, count 0 2006.162.07:48:41.67#ibcon#about to read 6, iclass 20, count 0 2006.162.07:48:41.67#ibcon#read 6, iclass 20, count 0 2006.162.07:48:41.67#ibcon#end of sib2, iclass 20, count 0 2006.162.07:48:41.67#ibcon#*after write, iclass 20, count 0 2006.162.07:48:41.67#ibcon#*before return 0, iclass 20, count 0 2006.162.07:48:41.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:48:41.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:48:41.67#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.07:48:41.67#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.07:48:41.67$vc4f8/va=6,6 2006.162.07:48:41.67#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.162.07:48:41.67#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.162.07:48:41.67#ibcon#ireg 11 cls_cnt 2 2006.162.07:48:41.67#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:48:41.73#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:48:41.73#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:48:41.73#ibcon#enter wrdev, iclass 22, count 2 2006.162.07:48:41.73#ibcon#first serial, iclass 22, count 2 2006.162.07:48:41.73#ibcon#enter sib2, iclass 22, count 2 2006.162.07:48:41.73#ibcon#flushed, iclass 22, count 2 2006.162.07:48:41.73#ibcon#about to write, iclass 22, count 2 2006.162.07:48:41.73#ibcon#wrote, iclass 22, count 2 2006.162.07:48:41.73#ibcon#about to read 3, iclass 22, count 2 2006.162.07:48:41.75#ibcon#read 3, iclass 22, count 2 2006.162.07:48:41.75#ibcon#about to read 4, iclass 22, count 2 2006.162.07:48:41.75#ibcon#read 4, iclass 22, count 2 2006.162.07:48:41.75#ibcon#about to read 5, iclass 22, count 2 2006.162.07:48:41.75#ibcon#read 5, iclass 22, count 2 2006.162.07:48:41.75#ibcon#about to read 6, iclass 22, count 2 2006.162.07:48:41.75#ibcon#read 6, iclass 22, count 2 2006.162.07:48:41.75#ibcon#end of sib2, iclass 22, count 2 2006.162.07:48:41.75#ibcon#*mode == 0, iclass 22, count 2 2006.162.07:48:41.75#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.162.07:48:41.75#ibcon#[25=AT06-06\r\n] 2006.162.07:48:41.75#ibcon#*before write, iclass 22, count 2 2006.162.07:48:41.75#ibcon#enter sib2, iclass 22, count 2 2006.162.07:48:41.75#ibcon#flushed, iclass 22, count 2 2006.162.07:48:41.75#ibcon#about to write, iclass 22, count 2 2006.162.07:48:41.75#ibcon#wrote, iclass 22, count 2 2006.162.07:48:41.75#ibcon#about to read 3, iclass 22, count 2 2006.162.07:48:41.78#ibcon#read 3, iclass 22, count 2 2006.162.07:48:41.78#ibcon#about to read 4, iclass 22, count 2 2006.162.07:48:41.78#ibcon#read 4, iclass 22, count 2 2006.162.07:48:41.78#ibcon#about to read 5, iclass 22, count 2 2006.162.07:48:41.78#ibcon#read 5, iclass 22, count 2 2006.162.07:48:41.78#ibcon#about to read 6, iclass 22, count 2 2006.162.07:48:41.78#ibcon#read 6, iclass 22, count 2 2006.162.07:48:41.78#ibcon#end of sib2, iclass 22, count 2 2006.162.07:48:41.78#ibcon#*after write, iclass 22, count 2 2006.162.07:48:41.78#ibcon#*before return 0, iclass 22, count 2 2006.162.07:48:41.78#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:48:41.78#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:48:41.78#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.162.07:48:41.78#ibcon#ireg 7 cls_cnt 0 2006.162.07:48:41.78#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:48:41.90#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:48:41.90#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:48:41.90#ibcon#enter wrdev, iclass 22, count 0 2006.162.07:48:41.90#ibcon#first serial, iclass 22, count 0 2006.162.07:48:41.90#ibcon#enter sib2, iclass 22, count 0 2006.162.07:48:41.90#ibcon#flushed, iclass 22, count 0 2006.162.07:48:41.90#ibcon#about to write, iclass 22, count 0 2006.162.07:48:41.90#ibcon#wrote, iclass 22, count 0 2006.162.07:48:41.90#ibcon#about to read 3, iclass 22, count 0 2006.162.07:48:41.92#ibcon#read 3, iclass 22, count 0 2006.162.07:48:41.92#ibcon#about to read 4, iclass 22, count 0 2006.162.07:48:41.92#ibcon#read 4, iclass 22, count 0 2006.162.07:48:41.92#ibcon#about to read 5, iclass 22, count 0 2006.162.07:48:41.92#ibcon#read 5, iclass 22, count 0 2006.162.07:48:41.92#ibcon#about to read 6, iclass 22, count 0 2006.162.07:48:41.92#ibcon#read 6, iclass 22, count 0 2006.162.07:48:41.92#ibcon#end of sib2, iclass 22, count 0 2006.162.07:48:41.92#ibcon#*mode == 0, iclass 22, count 0 2006.162.07:48:41.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.07:48:41.92#ibcon#[25=USB\r\n] 2006.162.07:48:41.92#ibcon#*before write, iclass 22, count 0 2006.162.07:48:41.92#ibcon#enter sib2, iclass 22, count 0 2006.162.07:48:41.92#ibcon#flushed, iclass 22, count 0 2006.162.07:48:41.92#ibcon#about to write, iclass 22, count 0 2006.162.07:48:41.92#ibcon#wrote, iclass 22, count 0 2006.162.07:48:41.92#ibcon#about to read 3, iclass 22, count 0 2006.162.07:48:41.95#ibcon#read 3, iclass 22, count 0 2006.162.07:48:41.95#ibcon#about to read 4, iclass 22, count 0 2006.162.07:48:41.95#ibcon#read 4, iclass 22, count 0 2006.162.07:48:41.95#ibcon#about to read 5, iclass 22, count 0 2006.162.07:48:41.95#ibcon#read 5, iclass 22, count 0 2006.162.07:48:41.95#ibcon#about to read 6, iclass 22, count 0 2006.162.07:48:41.95#ibcon#read 6, iclass 22, count 0 2006.162.07:48:41.95#ibcon#end of sib2, iclass 22, count 0 2006.162.07:48:41.95#ibcon#*after write, iclass 22, count 0 2006.162.07:48:41.95#ibcon#*before return 0, iclass 22, count 0 2006.162.07:48:41.95#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:48:41.95#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:48:41.95#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.07:48:41.95#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.07:48:41.95$vc4f8/valo=7,832.99 2006.162.07:48:41.95#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.162.07:48:41.95#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.162.07:48:41.95#ibcon#ireg 17 cls_cnt 0 2006.162.07:48:41.95#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:48:41.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:48:41.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:48:41.95#ibcon#enter wrdev, iclass 24, count 0 2006.162.07:48:41.95#ibcon#first serial, iclass 24, count 0 2006.162.07:48:41.95#ibcon#enter sib2, iclass 24, count 0 2006.162.07:48:41.95#ibcon#flushed, iclass 24, count 0 2006.162.07:48:41.95#ibcon#about to write, iclass 24, count 0 2006.162.07:48:41.95#ibcon#wrote, iclass 24, count 0 2006.162.07:48:41.95#ibcon#about to read 3, iclass 24, count 0 2006.162.07:48:41.97#ibcon#read 3, iclass 24, count 0 2006.162.07:48:41.97#ibcon#about to read 4, iclass 24, count 0 2006.162.07:48:41.97#ibcon#read 4, iclass 24, count 0 2006.162.07:48:41.97#ibcon#about to read 5, iclass 24, count 0 2006.162.07:48:41.97#ibcon#read 5, iclass 24, count 0 2006.162.07:48:41.97#ibcon#about to read 6, iclass 24, count 0 2006.162.07:48:41.97#ibcon#read 6, iclass 24, count 0 2006.162.07:48:41.97#ibcon#end of sib2, iclass 24, count 0 2006.162.07:48:41.97#ibcon#*mode == 0, iclass 24, count 0 2006.162.07:48:41.97#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.07:48:41.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.07:48:41.97#ibcon#*before write, iclass 24, count 0 2006.162.07:48:41.97#ibcon#enter sib2, iclass 24, count 0 2006.162.07:48:41.97#ibcon#flushed, iclass 24, count 0 2006.162.07:48:41.97#ibcon#about to write, iclass 24, count 0 2006.162.07:48:41.97#ibcon#wrote, iclass 24, count 0 2006.162.07:48:41.97#ibcon#about to read 3, iclass 24, count 0 2006.162.07:48:42.01#ibcon#read 3, iclass 24, count 0 2006.162.07:48:42.01#ibcon#about to read 4, iclass 24, count 0 2006.162.07:48:42.01#ibcon#read 4, iclass 24, count 0 2006.162.07:48:42.01#ibcon#about to read 5, iclass 24, count 0 2006.162.07:48:42.01#ibcon#read 5, iclass 24, count 0 2006.162.07:48:42.01#ibcon#about to read 6, iclass 24, count 0 2006.162.07:48:42.01#ibcon#read 6, iclass 24, count 0 2006.162.07:48:42.01#ibcon#end of sib2, iclass 24, count 0 2006.162.07:48:42.01#ibcon#*after write, iclass 24, count 0 2006.162.07:48:42.01#ibcon#*before return 0, iclass 24, count 0 2006.162.07:48:42.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:48:42.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:48:42.01#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.07:48:42.01#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.07:48:42.01$vc4f8/va=7,6 2006.162.07:48:42.01#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.162.07:48:42.01#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.162.07:48:42.01#ibcon#ireg 11 cls_cnt 2 2006.162.07:48:42.01#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:48:42.07#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:48:42.07#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:48:42.07#ibcon#enter wrdev, iclass 26, count 2 2006.162.07:48:42.07#ibcon#first serial, iclass 26, count 2 2006.162.07:48:42.07#ibcon#enter sib2, iclass 26, count 2 2006.162.07:48:42.07#ibcon#flushed, iclass 26, count 2 2006.162.07:48:42.07#ibcon#about to write, iclass 26, count 2 2006.162.07:48:42.07#ibcon#wrote, iclass 26, count 2 2006.162.07:48:42.07#ibcon#about to read 3, iclass 26, count 2 2006.162.07:48:42.09#ibcon#read 3, iclass 26, count 2 2006.162.07:48:42.09#ibcon#about to read 4, iclass 26, count 2 2006.162.07:48:42.09#ibcon#read 4, iclass 26, count 2 2006.162.07:48:42.09#ibcon#about to read 5, iclass 26, count 2 2006.162.07:48:42.09#ibcon#read 5, iclass 26, count 2 2006.162.07:48:42.09#ibcon#about to read 6, iclass 26, count 2 2006.162.07:48:42.09#ibcon#read 6, iclass 26, count 2 2006.162.07:48:42.09#ibcon#end of sib2, iclass 26, count 2 2006.162.07:48:42.09#ibcon#*mode == 0, iclass 26, count 2 2006.162.07:48:42.09#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.162.07:48:42.09#ibcon#[25=AT07-06\r\n] 2006.162.07:48:42.09#ibcon#*before write, iclass 26, count 2 2006.162.07:48:42.09#ibcon#enter sib2, iclass 26, count 2 2006.162.07:48:42.09#ibcon#flushed, iclass 26, count 2 2006.162.07:48:42.09#ibcon#about to write, iclass 26, count 2 2006.162.07:48:42.09#ibcon#wrote, iclass 26, count 2 2006.162.07:48:42.09#ibcon#about to read 3, iclass 26, count 2 2006.162.07:48:42.12#ibcon#read 3, iclass 26, count 2 2006.162.07:48:42.12#ibcon#about to read 4, iclass 26, count 2 2006.162.07:48:42.12#ibcon#read 4, iclass 26, count 2 2006.162.07:48:42.12#ibcon#about to read 5, iclass 26, count 2 2006.162.07:48:42.12#ibcon#read 5, iclass 26, count 2 2006.162.07:48:42.12#ibcon#about to read 6, iclass 26, count 2 2006.162.07:48:42.12#ibcon#read 6, iclass 26, count 2 2006.162.07:48:42.12#ibcon#end of sib2, iclass 26, count 2 2006.162.07:48:42.12#ibcon#*after write, iclass 26, count 2 2006.162.07:48:42.12#ibcon#*before return 0, iclass 26, count 2 2006.162.07:48:42.12#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:48:42.12#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:48:42.12#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.162.07:48:42.12#ibcon#ireg 7 cls_cnt 0 2006.162.07:48:42.12#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:48:42.24#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:48:42.24#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:48:42.24#ibcon#enter wrdev, iclass 26, count 0 2006.162.07:48:42.24#ibcon#first serial, iclass 26, count 0 2006.162.07:48:42.24#ibcon#enter sib2, iclass 26, count 0 2006.162.07:48:42.24#ibcon#flushed, iclass 26, count 0 2006.162.07:48:42.24#ibcon#about to write, iclass 26, count 0 2006.162.07:48:42.24#ibcon#wrote, iclass 26, count 0 2006.162.07:48:42.24#ibcon#about to read 3, iclass 26, count 0 2006.162.07:48:42.26#ibcon#read 3, iclass 26, count 0 2006.162.07:48:42.26#ibcon#about to read 4, iclass 26, count 0 2006.162.07:48:42.26#ibcon#read 4, iclass 26, count 0 2006.162.07:48:42.26#ibcon#about to read 5, iclass 26, count 0 2006.162.07:48:42.26#ibcon#read 5, iclass 26, count 0 2006.162.07:48:42.26#ibcon#about to read 6, iclass 26, count 0 2006.162.07:48:42.26#ibcon#read 6, iclass 26, count 0 2006.162.07:48:42.26#ibcon#end of sib2, iclass 26, count 0 2006.162.07:48:42.26#ibcon#*mode == 0, iclass 26, count 0 2006.162.07:48:42.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.162.07:48:42.26#ibcon#[25=USB\r\n] 2006.162.07:48:42.26#ibcon#*before write, iclass 26, count 0 2006.162.07:48:42.26#ibcon#enter sib2, iclass 26, count 0 2006.162.07:48:42.26#ibcon#flushed, iclass 26, count 0 2006.162.07:48:42.26#ibcon#about to write, iclass 26, count 0 2006.162.07:48:42.26#ibcon#wrote, iclass 26, count 0 2006.162.07:48:42.26#ibcon#about to read 3, iclass 26, count 0 2006.162.07:48:42.29#ibcon#read 3, iclass 26, count 0 2006.162.07:48:42.29#ibcon#about to read 4, iclass 26, count 0 2006.162.07:48:42.29#ibcon#read 4, iclass 26, count 0 2006.162.07:48:42.29#ibcon#about to read 5, iclass 26, count 0 2006.162.07:48:42.29#ibcon#read 5, iclass 26, count 0 2006.162.07:48:42.29#ibcon#about to read 6, iclass 26, count 0 2006.162.07:48:42.29#ibcon#read 6, iclass 26, count 0 2006.162.07:48:42.29#ibcon#end of sib2, iclass 26, count 0 2006.162.07:48:42.29#ibcon#*after write, iclass 26, count 0 2006.162.07:48:42.29#ibcon#*before return 0, iclass 26, count 0 2006.162.07:48:42.29#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:48:42.29#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:48:42.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.162.07:48:42.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.162.07:48:42.29$vc4f8/valo=8,852.99 2006.162.07:48:42.29#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.162.07:48:42.29#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.162.07:48:42.29#ibcon#ireg 17 cls_cnt 0 2006.162.07:48:42.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:48:42.29#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:48:42.29#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:48:42.29#ibcon#enter wrdev, iclass 28, count 0 2006.162.07:48:42.29#ibcon#first serial, iclass 28, count 0 2006.162.07:48:42.29#ibcon#enter sib2, iclass 28, count 0 2006.162.07:48:42.29#ibcon#flushed, iclass 28, count 0 2006.162.07:48:42.29#ibcon#about to write, iclass 28, count 0 2006.162.07:48:42.29#ibcon#wrote, iclass 28, count 0 2006.162.07:48:42.29#ibcon#about to read 3, iclass 28, count 0 2006.162.07:48:42.31#ibcon#read 3, iclass 28, count 0 2006.162.07:48:42.31#ibcon#about to read 4, iclass 28, count 0 2006.162.07:48:42.31#ibcon#read 4, iclass 28, count 0 2006.162.07:48:42.31#ibcon#about to read 5, iclass 28, count 0 2006.162.07:48:42.31#ibcon#read 5, iclass 28, count 0 2006.162.07:48:42.31#ibcon#about to read 6, iclass 28, count 0 2006.162.07:48:42.31#ibcon#read 6, iclass 28, count 0 2006.162.07:48:42.31#ibcon#end of sib2, iclass 28, count 0 2006.162.07:48:42.31#ibcon#*mode == 0, iclass 28, count 0 2006.162.07:48:42.31#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.162.07:48:42.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.07:48:42.31#ibcon#*before write, iclass 28, count 0 2006.162.07:48:42.31#ibcon#enter sib2, iclass 28, count 0 2006.162.07:48:42.31#ibcon#flushed, iclass 28, count 0 2006.162.07:48:42.31#ibcon#about to write, iclass 28, count 0 2006.162.07:48:42.31#ibcon#wrote, iclass 28, count 0 2006.162.07:48:42.31#ibcon#about to read 3, iclass 28, count 0 2006.162.07:48:42.35#ibcon#read 3, iclass 28, count 0 2006.162.07:48:42.35#ibcon#about to read 4, iclass 28, count 0 2006.162.07:48:42.35#ibcon#read 4, iclass 28, count 0 2006.162.07:48:42.35#ibcon#about to read 5, iclass 28, count 0 2006.162.07:48:42.35#ibcon#read 5, iclass 28, count 0 2006.162.07:48:42.35#ibcon#about to read 6, iclass 28, count 0 2006.162.07:48:42.35#ibcon#read 6, iclass 28, count 0 2006.162.07:48:42.35#ibcon#end of sib2, iclass 28, count 0 2006.162.07:48:42.35#ibcon#*after write, iclass 28, count 0 2006.162.07:48:42.35#ibcon#*before return 0, iclass 28, count 0 2006.162.07:48:42.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:48:42.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:48:42.35#ibcon#about to clear, iclass 28 cls_cnt 0 2006.162.07:48:42.35#ibcon#cleared, iclass 28 cls_cnt 0 2006.162.07:48:42.35$vc4f8/va=8,7 2006.162.07:48:42.35#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.162.07:48:42.35#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.162.07:48:42.35#ibcon#ireg 11 cls_cnt 2 2006.162.07:48:42.35#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:48:42.41#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:48:42.41#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:48:42.41#ibcon#enter wrdev, iclass 30, count 2 2006.162.07:48:42.41#ibcon#first serial, iclass 30, count 2 2006.162.07:48:42.41#ibcon#enter sib2, iclass 30, count 2 2006.162.07:48:42.41#ibcon#flushed, iclass 30, count 2 2006.162.07:48:42.41#ibcon#about to write, iclass 30, count 2 2006.162.07:48:42.41#ibcon#wrote, iclass 30, count 2 2006.162.07:48:42.41#ibcon#about to read 3, iclass 30, count 2 2006.162.07:48:42.43#ibcon#read 3, iclass 30, count 2 2006.162.07:48:42.43#ibcon#about to read 4, iclass 30, count 2 2006.162.07:48:42.43#ibcon#read 4, iclass 30, count 2 2006.162.07:48:42.43#ibcon#about to read 5, iclass 30, count 2 2006.162.07:48:42.43#ibcon#read 5, iclass 30, count 2 2006.162.07:48:42.43#ibcon#about to read 6, iclass 30, count 2 2006.162.07:48:42.43#ibcon#read 6, iclass 30, count 2 2006.162.07:48:42.43#ibcon#end of sib2, iclass 30, count 2 2006.162.07:48:42.43#ibcon#*mode == 0, iclass 30, count 2 2006.162.07:48:42.43#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.162.07:48:42.43#ibcon#[25=AT08-07\r\n] 2006.162.07:48:42.43#ibcon#*before write, iclass 30, count 2 2006.162.07:48:42.43#ibcon#enter sib2, iclass 30, count 2 2006.162.07:48:42.43#ibcon#flushed, iclass 30, count 2 2006.162.07:48:42.43#ibcon#about to write, iclass 30, count 2 2006.162.07:48:42.43#ibcon#wrote, iclass 30, count 2 2006.162.07:48:42.43#ibcon#about to read 3, iclass 30, count 2 2006.162.07:48:42.46#ibcon#read 3, iclass 30, count 2 2006.162.07:48:42.46#ibcon#about to read 4, iclass 30, count 2 2006.162.07:48:42.46#ibcon#read 4, iclass 30, count 2 2006.162.07:48:42.46#ibcon#about to read 5, iclass 30, count 2 2006.162.07:48:42.46#ibcon#read 5, iclass 30, count 2 2006.162.07:48:42.46#ibcon#about to read 6, iclass 30, count 2 2006.162.07:48:42.46#ibcon#read 6, iclass 30, count 2 2006.162.07:48:42.46#ibcon#end of sib2, iclass 30, count 2 2006.162.07:48:42.46#ibcon#*after write, iclass 30, count 2 2006.162.07:48:42.46#ibcon#*before return 0, iclass 30, count 2 2006.162.07:48:42.46#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:48:42.46#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:48:42.46#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.162.07:48:42.46#ibcon#ireg 7 cls_cnt 0 2006.162.07:48:42.46#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:48:42.58#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:48:42.58#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:48:42.58#ibcon#enter wrdev, iclass 30, count 0 2006.162.07:48:42.58#ibcon#first serial, iclass 30, count 0 2006.162.07:48:42.58#ibcon#enter sib2, iclass 30, count 0 2006.162.07:48:42.58#ibcon#flushed, iclass 30, count 0 2006.162.07:48:42.58#ibcon#about to write, iclass 30, count 0 2006.162.07:48:42.58#ibcon#wrote, iclass 30, count 0 2006.162.07:48:42.58#ibcon#about to read 3, iclass 30, count 0 2006.162.07:48:42.60#ibcon#read 3, iclass 30, count 0 2006.162.07:48:42.60#ibcon#about to read 4, iclass 30, count 0 2006.162.07:48:42.60#ibcon#read 4, iclass 30, count 0 2006.162.07:48:42.60#ibcon#about to read 5, iclass 30, count 0 2006.162.07:48:42.60#ibcon#read 5, iclass 30, count 0 2006.162.07:48:42.60#ibcon#about to read 6, iclass 30, count 0 2006.162.07:48:42.60#ibcon#read 6, iclass 30, count 0 2006.162.07:48:42.60#ibcon#end of sib2, iclass 30, count 0 2006.162.07:48:42.60#ibcon#*mode == 0, iclass 30, count 0 2006.162.07:48:42.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.162.07:48:42.60#ibcon#[25=USB\r\n] 2006.162.07:48:42.60#ibcon#*before write, iclass 30, count 0 2006.162.07:48:42.60#ibcon#enter sib2, iclass 30, count 0 2006.162.07:48:42.60#ibcon#flushed, iclass 30, count 0 2006.162.07:48:42.60#ibcon#about to write, iclass 30, count 0 2006.162.07:48:42.60#ibcon#wrote, iclass 30, count 0 2006.162.07:48:42.60#ibcon#about to read 3, iclass 30, count 0 2006.162.07:48:42.63#ibcon#read 3, iclass 30, count 0 2006.162.07:48:42.63#ibcon#about to read 4, iclass 30, count 0 2006.162.07:48:42.63#ibcon#read 4, iclass 30, count 0 2006.162.07:48:42.63#ibcon#about to read 5, iclass 30, count 0 2006.162.07:48:42.63#ibcon#read 5, iclass 30, count 0 2006.162.07:48:42.63#ibcon#about to read 6, iclass 30, count 0 2006.162.07:48:42.63#ibcon#read 6, iclass 30, count 0 2006.162.07:48:42.63#ibcon#end of sib2, iclass 30, count 0 2006.162.07:48:42.63#ibcon#*after write, iclass 30, count 0 2006.162.07:48:42.63#ibcon#*before return 0, iclass 30, count 0 2006.162.07:48:42.63#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:48:42.63#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:48:42.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.162.07:48:42.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.162.07:48:42.63$vc4f8/vblo=1,632.99 2006.162.07:48:42.63#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.162.07:48:42.63#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.162.07:48:42.63#ibcon#ireg 17 cls_cnt 0 2006.162.07:48:42.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:48:42.63#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:48:42.63#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:48:42.63#ibcon#enter wrdev, iclass 32, count 0 2006.162.07:48:42.63#ibcon#first serial, iclass 32, count 0 2006.162.07:48:42.63#ibcon#enter sib2, iclass 32, count 0 2006.162.07:48:42.63#ibcon#flushed, iclass 32, count 0 2006.162.07:48:42.63#ibcon#about to write, iclass 32, count 0 2006.162.07:48:42.63#ibcon#wrote, iclass 32, count 0 2006.162.07:48:42.63#ibcon#about to read 3, iclass 32, count 0 2006.162.07:48:42.65#ibcon#read 3, iclass 32, count 0 2006.162.07:48:42.65#ibcon#about to read 4, iclass 32, count 0 2006.162.07:48:42.65#ibcon#read 4, iclass 32, count 0 2006.162.07:48:42.65#ibcon#about to read 5, iclass 32, count 0 2006.162.07:48:42.65#ibcon#read 5, iclass 32, count 0 2006.162.07:48:42.65#ibcon#about to read 6, iclass 32, count 0 2006.162.07:48:42.65#ibcon#read 6, iclass 32, count 0 2006.162.07:48:42.65#ibcon#end of sib2, iclass 32, count 0 2006.162.07:48:42.65#ibcon#*mode == 0, iclass 32, count 0 2006.162.07:48:42.65#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.162.07:48:42.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.07:48:42.65#ibcon#*before write, iclass 32, count 0 2006.162.07:48:42.65#ibcon#enter sib2, iclass 32, count 0 2006.162.07:48:42.65#ibcon#flushed, iclass 32, count 0 2006.162.07:48:42.65#ibcon#about to write, iclass 32, count 0 2006.162.07:48:42.65#ibcon#wrote, iclass 32, count 0 2006.162.07:48:42.65#ibcon#about to read 3, iclass 32, count 0 2006.162.07:48:42.69#ibcon#read 3, iclass 32, count 0 2006.162.07:48:42.69#ibcon#about to read 4, iclass 32, count 0 2006.162.07:48:42.69#ibcon#read 4, iclass 32, count 0 2006.162.07:48:42.69#ibcon#about to read 5, iclass 32, count 0 2006.162.07:48:42.69#ibcon#read 5, iclass 32, count 0 2006.162.07:48:42.69#ibcon#about to read 6, iclass 32, count 0 2006.162.07:48:42.69#ibcon#read 6, iclass 32, count 0 2006.162.07:48:42.69#ibcon#end of sib2, iclass 32, count 0 2006.162.07:48:42.69#ibcon#*after write, iclass 32, count 0 2006.162.07:48:42.69#ibcon#*before return 0, iclass 32, count 0 2006.162.07:48:42.69#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:48:42.69#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:48:42.69#ibcon#about to clear, iclass 32 cls_cnt 0 2006.162.07:48:42.69#ibcon#cleared, iclass 32 cls_cnt 0 2006.162.07:48:42.69$vc4f8/vb=1,4 2006.162.07:48:42.69#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.162.07:48:42.69#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.162.07:48:42.69#ibcon#ireg 11 cls_cnt 2 2006.162.07:48:42.69#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.162.07:48:42.69#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.162.07:48:42.69#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.162.07:48:42.69#ibcon#enter wrdev, iclass 34, count 2 2006.162.07:48:42.69#ibcon#first serial, iclass 34, count 2 2006.162.07:48:42.69#ibcon#enter sib2, iclass 34, count 2 2006.162.07:48:42.69#ibcon#flushed, iclass 34, count 2 2006.162.07:48:42.69#ibcon#about to write, iclass 34, count 2 2006.162.07:48:42.69#ibcon#wrote, iclass 34, count 2 2006.162.07:48:42.69#ibcon#about to read 3, iclass 34, count 2 2006.162.07:48:42.71#ibcon#read 3, iclass 34, count 2 2006.162.07:48:42.71#ibcon#about to read 4, iclass 34, count 2 2006.162.07:48:42.71#ibcon#read 4, iclass 34, count 2 2006.162.07:48:42.71#ibcon#about to read 5, iclass 34, count 2 2006.162.07:48:42.71#ibcon#read 5, iclass 34, count 2 2006.162.07:48:42.71#ibcon#about to read 6, iclass 34, count 2 2006.162.07:48:42.71#ibcon#read 6, iclass 34, count 2 2006.162.07:48:42.71#ibcon#end of sib2, iclass 34, count 2 2006.162.07:48:42.71#ibcon#*mode == 0, iclass 34, count 2 2006.162.07:48:42.71#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.162.07:48:42.71#ibcon#[27=AT01-04\r\n] 2006.162.07:48:42.71#ibcon#*before write, iclass 34, count 2 2006.162.07:48:42.71#ibcon#enter sib2, iclass 34, count 2 2006.162.07:48:42.71#ibcon#flushed, iclass 34, count 2 2006.162.07:48:42.71#ibcon#about to write, iclass 34, count 2 2006.162.07:48:42.71#ibcon#wrote, iclass 34, count 2 2006.162.07:48:42.71#ibcon#about to read 3, iclass 34, count 2 2006.162.07:48:42.74#ibcon#read 3, iclass 34, count 2 2006.162.07:48:42.74#ibcon#about to read 4, iclass 34, count 2 2006.162.07:48:42.74#ibcon#read 4, iclass 34, count 2 2006.162.07:48:42.74#ibcon#about to read 5, iclass 34, count 2 2006.162.07:48:42.74#ibcon#read 5, iclass 34, count 2 2006.162.07:48:42.74#ibcon#about to read 6, iclass 34, count 2 2006.162.07:48:42.74#ibcon#read 6, iclass 34, count 2 2006.162.07:48:42.74#ibcon#end of sib2, iclass 34, count 2 2006.162.07:48:42.74#ibcon#*after write, iclass 34, count 2 2006.162.07:48:42.74#ibcon#*before return 0, iclass 34, count 2 2006.162.07:48:42.74#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.162.07:48:42.74#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.162.07:48:42.74#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.162.07:48:42.74#ibcon#ireg 7 cls_cnt 0 2006.162.07:48:42.74#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.162.07:48:42.86#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.162.07:48:42.86#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.162.07:48:42.86#ibcon#enter wrdev, iclass 34, count 0 2006.162.07:48:42.86#ibcon#first serial, iclass 34, count 0 2006.162.07:48:42.86#ibcon#enter sib2, iclass 34, count 0 2006.162.07:48:42.86#ibcon#flushed, iclass 34, count 0 2006.162.07:48:42.86#ibcon#about to write, iclass 34, count 0 2006.162.07:48:42.86#ibcon#wrote, iclass 34, count 0 2006.162.07:48:42.86#ibcon#about to read 3, iclass 34, count 0 2006.162.07:48:42.88#ibcon#read 3, iclass 34, count 0 2006.162.07:48:42.88#ibcon#about to read 4, iclass 34, count 0 2006.162.07:48:42.88#ibcon#read 4, iclass 34, count 0 2006.162.07:48:42.88#ibcon#about to read 5, iclass 34, count 0 2006.162.07:48:42.88#ibcon#read 5, iclass 34, count 0 2006.162.07:48:42.88#ibcon#about to read 6, iclass 34, count 0 2006.162.07:48:42.88#ibcon#read 6, iclass 34, count 0 2006.162.07:48:42.88#ibcon#end of sib2, iclass 34, count 0 2006.162.07:48:42.88#ibcon#*mode == 0, iclass 34, count 0 2006.162.07:48:42.88#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.162.07:48:42.88#ibcon#[27=USB\r\n] 2006.162.07:48:42.88#ibcon#*before write, iclass 34, count 0 2006.162.07:48:42.88#ibcon#enter sib2, iclass 34, count 0 2006.162.07:48:42.88#ibcon#flushed, iclass 34, count 0 2006.162.07:48:42.88#ibcon#about to write, iclass 34, count 0 2006.162.07:48:42.88#ibcon#wrote, iclass 34, count 0 2006.162.07:48:42.88#ibcon#about to read 3, iclass 34, count 0 2006.162.07:48:42.91#ibcon#read 3, iclass 34, count 0 2006.162.07:48:42.91#ibcon#about to read 4, iclass 34, count 0 2006.162.07:48:42.91#ibcon#read 4, iclass 34, count 0 2006.162.07:48:42.91#ibcon#about to read 5, iclass 34, count 0 2006.162.07:48:42.91#ibcon#read 5, iclass 34, count 0 2006.162.07:48:42.91#ibcon#about to read 6, iclass 34, count 0 2006.162.07:48:42.91#ibcon#read 6, iclass 34, count 0 2006.162.07:48:42.91#ibcon#end of sib2, iclass 34, count 0 2006.162.07:48:42.91#ibcon#*after write, iclass 34, count 0 2006.162.07:48:42.91#ibcon#*before return 0, iclass 34, count 0 2006.162.07:48:42.91#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.162.07:48:42.91#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.162.07:48:42.91#ibcon#about to clear, iclass 34 cls_cnt 0 2006.162.07:48:42.91#ibcon#cleared, iclass 34 cls_cnt 0 2006.162.07:48:42.91$vc4f8/vblo=2,640.99 2006.162.07:48:42.91#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.162.07:48:42.91#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.162.07:48:42.91#ibcon#ireg 17 cls_cnt 0 2006.162.07:48:42.91#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:48:42.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:48:42.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:48:42.91#ibcon#enter wrdev, iclass 36, count 0 2006.162.07:48:42.91#ibcon#first serial, iclass 36, count 0 2006.162.07:48:42.91#ibcon#enter sib2, iclass 36, count 0 2006.162.07:48:42.91#ibcon#flushed, iclass 36, count 0 2006.162.07:48:42.91#ibcon#about to write, iclass 36, count 0 2006.162.07:48:42.91#ibcon#wrote, iclass 36, count 0 2006.162.07:48:42.91#ibcon#about to read 3, iclass 36, count 0 2006.162.07:48:42.93#ibcon#read 3, iclass 36, count 0 2006.162.07:48:42.93#ibcon#about to read 4, iclass 36, count 0 2006.162.07:48:42.93#ibcon#read 4, iclass 36, count 0 2006.162.07:48:42.93#ibcon#about to read 5, iclass 36, count 0 2006.162.07:48:42.93#ibcon#read 5, iclass 36, count 0 2006.162.07:48:42.93#ibcon#about to read 6, iclass 36, count 0 2006.162.07:48:42.93#ibcon#read 6, iclass 36, count 0 2006.162.07:48:42.93#ibcon#end of sib2, iclass 36, count 0 2006.162.07:48:42.93#ibcon#*mode == 0, iclass 36, count 0 2006.162.07:48:42.93#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.162.07:48:42.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.07:48:42.93#ibcon#*before write, iclass 36, count 0 2006.162.07:48:42.93#ibcon#enter sib2, iclass 36, count 0 2006.162.07:48:42.93#ibcon#flushed, iclass 36, count 0 2006.162.07:48:42.93#ibcon#about to write, iclass 36, count 0 2006.162.07:48:42.93#ibcon#wrote, iclass 36, count 0 2006.162.07:48:42.93#ibcon#about to read 3, iclass 36, count 0 2006.162.07:48:42.97#ibcon#read 3, iclass 36, count 0 2006.162.07:48:42.97#ibcon#about to read 4, iclass 36, count 0 2006.162.07:48:42.97#ibcon#read 4, iclass 36, count 0 2006.162.07:48:42.97#ibcon#about to read 5, iclass 36, count 0 2006.162.07:48:42.97#ibcon#read 5, iclass 36, count 0 2006.162.07:48:42.97#ibcon#about to read 6, iclass 36, count 0 2006.162.07:48:42.97#ibcon#read 6, iclass 36, count 0 2006.162.07:48:42.97#ibcon#end of sib2, iclass 36, count 0 2006.162.07:48:42.97#ibcon#*after write, iclass 36, count 0 2006.162.07:48:42.97#ibcon#*before return 0, iclass 36, count 0 2006.162.07:48:42.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:48:42.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:48:42.97#ibcon#about to clear, iclass 36 cls_cnt 0 2006.162.07:48:42.97#ibcon#cleared, iclass 36 cls_cnt 0 2006.162.07:48:42.97$vc4f8/vb=2,4 2006.162.07:48:42.97#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.162.07:48:42.97#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.162.07:48:42.97#ibcon#ireg 11 cls_cnt 2 2006.162.07:48:42.97#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:48:43.03#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:48:43.03#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:48:43.03#ibcon#enter wrdev, iclass 38, count 2 2006.162.07:48:43.03#ibcon#first serial, iclass 38, count 2 2006.162.07:48:43.03#ibcon#enter sib2, iclass 38, count 2 2006.162.07:48:43.03#ibcon#flushed, iclass 38, count 2 2006.162.07:48:43.03#ibcon#about to write, iclass 38, count 2 2006.162.07:48:43.03#ibcon#wrote, iclass 38, count 2 2006.162.07:48:43.03#ibcon#about to read 3, iclass 38, count 2 2006.162.07:48:43.05#ibcon#read 3, iclass 38, count 2 2006.162.07:48:43.05#ibcon#about to read 4, iclass 38, count 2 2006.162.07:48:43.05#ibcon#read 4, iclass 38, count 2 2006.162.07:48:43.05#ibcon#about to read 5, iclass 38, count 2 2006.162.07:48:43.05#ibcon#read 5, iclass 38, count 2 2006.162.07:48:43.05#ibcon#about to read 6, iclass 38, count 2 2006.162.07:48:43.05#ibcon#read 6, iclass 38, count 2 2006.162.07:48:43.05#ibcon#end of sib2, iclass 38, count 2 2006.162.07:48:43.05#ibcon#*mode == 0, iclass 38, count 2 2006.162.07:48:43.05#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.162.07:48:43.05#ibcon#[27=AT02-04\r\n] 2006.162.07:48:43.05#ibcon#*before write, iclass 38, count 2 2006.162.07:48:43.05#ibcon#enter sib2, iclass 38, count 2 2006.162.07:48:43.05#ibcon#flushed, iclass 38, count 2 2006.162.07:48:43.05#ibcon#about to write, iclass 38, count 2 2006.162.07:48:43.05#ibcon#wrote, iclass 38, count 2 2006.162.07:48:43.05#ibcon#about to read 3, iclass 38, count 2 2006.162.07:48:43.08#ibcon#read 3, iclass 38, count 2 2006.162.07:48:43.08#ibcon#about to read 4, iclass 38, count 2 2006.162.07:48:43.08#ibcon#read 4, iclass 38, count 2 2006.162.07:48:43.08#ibcon#about to read 5, iclass 38, count 2 2006.162.07:48:43.08#ibcon#read 5, iclass 38, count 2 2006.162.07:48:43.08#ibcon#about to read 6, iclass 38, count 2 2006.162.07:48:43.08#ibcon#read 6, iclass 38, count 2 2006.162.07:48:43.08#ibcon#end of sib2, iclass 38, count 2 2006.162.07:48:43.08#ibcon#*after write, iclass 38, count 2 2006.162.07:48:43.08#ibcon#*before return 0, iclass 38, count 2 2006.162.07:48:43.08#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:48:43.08#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:48:43.08#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.162.07:48:43.08#ibcon#ireg 7 cls_cnt 0 2006.162.07:48:43.08#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:48:43.20#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:48:43.20#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:48:43.20#ibcon#enter wrdev, iclass 38, count 0 2006.162.07:48:43.20#ibcon#first serial, iclass 38, count 0 2006.162.07:48:43.20#ibcon#enter sib2, iclass 38, count 0 2006.162.07:48:43.20#ibcon#flushed, iclass 38, count 0 2006.162.07:48:43.20#ibcon#about to write, iclass 38, count 0 2006.162.07:48:43.20#ibcon#wrote, iclass 38, count 0 2006.162.07:48:43.20#ibcon#about to read 3, iclass 38, count 0 2006.162.07:48:43.22#ibcon#read 3, iclass 38, count 0 2006.162.07:48:43.22#ibcon#about to read 4, iclass 38, count 0 2006.162.07:48:43.22#ibcon#read 4, iclass 38, count 0 2006.162.07:48:43.22#ibcon#about to read 5, iclass 38, count 0 2006.162.07:48:43.22#ibcon#read 5, iclass 38, count 0 2006.162.07:48:43.22#ibcon#about to read 6, iclass 38, count 0 2006.162.07:48:43.22#ibcon#read 6, iclass 38, count 0 2006.162.07:48:43.22#ibcon#end of sib2, iclass 38, count 0 2006.162.07:48:43.22#ibcon#*mode == 0, iclass 38, count 0 2006.162.07:48:43.22#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.162.07:48:43.22#ibcon#[27=USB\r\n] 2006.162.07:48:43.22#ibcon#*before write, iclass 38, count 0 2006.162.07:48:43.22#ibcon#enter sib2, iclass 38, count 0 2006.162.07:48:43.22#ibcon#flushed, iclass 38, count 0 2006.162.07:48:43.22#ibcon#about to write, iclass 38, count 0 2006.162.07:48:43.22#ibcon#wrote, iclass 38, count 0 2006.162.07:48:43.22#ibcon#about to read 3, iclass 38, count 0 2006.162.07:48:43.25#ibcon#read 3, iclass 38, count 0 2006.162.07:48:43.25#ibcon#about to read 4, iclass 38, count 0 2006.162.07:48:43.25#ibcon#read 4, iclass 38, count 0 2006.162.07:48:43.25#ibcon#about to read 5, iclass 38, count 0 2006.162.07:48:43.25#ibcon#read 5, iclass 38, count 0 2006.162.07:48:43.25#ibcon#about to read 6, iclass 38, count 0 2006.162.07:48:43.25#ibcon#read 6, iclass 38, count 0 2006.162.07:48:43.25#ibcon#end of sib2, iclass 38, count 0 2006.162.07:48:43.25#ibcon#*after write, iclass 38, count 0 2006.162.07:48:43.25#ibcon#*before return 0, iclass 38, count 0 2006.162.07:48:43.25#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:48:43.25#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:48:43.25#ibcon#about to clear, iclass 38 cls_cnt 0 2006.162.07:48:43.25#ibcon#cleared, iclass 38 cls_cnt 0 2006.162.07:48:43.25$vc4f8/vblo=3,656.99 2006.162.07:48:43.25#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.162.07:48:43.25#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.162.07:48:43.25#ibcon#ireg 17 cls_cnt 0 2006.162.07:48:43.25#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:48:43.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:48:43.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:48:43.25#ibcon#enter wrdev, iclass 40, count 0 2006.162.07:48:43.25#ibcon#first serial, iclass 40, count 0 2006.162.07:48:43.25#ibcon#enter sib2, iclass 40, count 0 2006.162.07:48:43.25#ibcon#flushed, iclass 40, count 0 2006.162.07:48:43.25#ibcon#about to write, iclass 40, count 0 2006.162.07:48:43.25#ibcon#wrote, iclass 40, count 0 2006.162.07:48:43.25#ibcon#about to read 3, iclass 40, count 0 2006.162.07:48:43.27#ibcon#read 3, iclass 40, count 0 2006.162.07:48:43.27#ibcon#about to read 4, iclass 40, count 0 2006.162.07:48:43.27#ibcon#read 4, iclass 40, count 0 2006.162.07:48:43.27#ibcon#about to read 5, iclass 40, count 0 2006.162.07:48:43.27#ibcon#read 5, iclass 40, count 0 2006.162.07:48:43.27#ibcon#about to read 6, iclass 40, count 0 2006.162.07:48:43.27#ibcon#read 6, iclass 40, count 0 2006.162.07:48:43.27#ibcon#end of sib2, iclass 40, count 0 2006.162.07:48:43.27#ibcon#*mode == 0, iclass 40, count 0 2006.162.07:48:43.27#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.162.07:48:43.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.07:48:43.27#ibcon#*before write, iclass 40, count 0 2006.162.07:48:43.27#ibcon#enter sib2, iclass 40, count 0 2006.162.07:48:43.27#ibcon#flushed, iclass 40, count 0 2006.162.07:48:43.27#ibcon#about to write, iclass 40, count 0 2006.162.07:48:43.27#ibcon#wrote, iclass 40, count 0 2006.162.07:48:43.27#ibcon#about to read 3, iclass 40, count 0 2006.162.07:48:43.31#ibcon#read 3, iclass 40, count 0 2006.162.07:48:43.31#ibcon#about to read 4, iclass 40, count 0 2006.162.07:48:43.31#ibcon#read 4, iclass 40, count 0 2006.162.07:48:43.31#ibcon#about to read 5, iclass 40, count 0 2006.162.07:48:43.31#ibcon#read 5, iclass 40, count 0 2006.162.07:48:43.31#ibcon#about to read 6, iclass 40, count 0 2006.162.07:48:43.31#ibcon#read 6, iclass 40, count 0 2006.162.07:48:43.31#ibcon#end of sib2, iclass 40, count 0 2006.162.07:48:43.31#ibcon#*after write, iclass 40, count 0 2006.162.07:48:43.31#ibcon#*before return 0, iclass 40, count 0 2006.162.07:48:43.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:48:43.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:48:43.31#ibcon#about to clear, iclass 40 cls_cnt 0 2006.162.07:48:43.31#ibcon#cleared, iclass 40 cls_cnt 0 2006.162.07:48:43.31$vc4f8/vb=3,4 2006.162.07:48:43.31#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.162.07:48:43.31#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.162.07:48:43.31#ibcon#ireg 11 cls_cnt 2 2006.162.07:48:43.31#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:48:43.37#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:48:43.37#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:48:43.37#ibcon#enter wrdev, iclass 4, count 2 2006.162.07:48:43.37#ibcon#first serial, iclass 4, count 2 2006.162.07:48:43.37#ibcon#enter sib2, iclass 4, count 2 2006.162.07:48:43.37#ibcon#flushed, iclass 4, count 2 2006.162.07:48:43.37#ibcon#about to write, iclass 4, count 2 2006.162.07:48:43.37#ibcon#wrote, iclass 4, count 2 2006.162.07:48:43.37#ibcon#about to read 3, iclass 4, count 2 2006.162.07:48:43.39#ibcon#read 3, iclass 4, count 2 2006.162.07:48:43.39#ibcon#about to read 4, iclass 4, count 2 2006.162.07:48:43.39#ibcon#read 4, iclass 4, count 2 2006.162.07:48:43.39#ibcon#about to read 5, iclass 4, count 2 2006.162.07:48:43.39#ibcon#read 5, iclass 4, count 2 2006.162.07:48:43.39#ibcon#about to read 6, iclass 4, count 2 2006.162.07:48:43.39#ibcon#read 6, iclass 4, count 2 2006.162.07:48:43.39#ibcon#end of sib2, iclass 4, count 2 2006.162.07:48:43.39#ibcon#*mode == 0, iclass 4, count 2 2006.162.07:48:43.39#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.162.07:48:43.39#ibcon#[27=AT03-04\r\n] 2006.162.07:48:43.39#ibcon#*before write, iclass 4, count 2 2006.162.07:48:43.39#ibcon#enter sib2, iclass 4, count 2 2006.162.07:48:43.39#ibcon#flushed, iclass 4, count 2 2006.162.07:48:43.39#ibcon#about to write, iclass 4, count 2 2006.162.07:48:43.39#ibcon#wrote, iclass 4, count 2 2006.162.07:48:43.39#ibcon#about to read 3, iclass 4, count 2 2006.162.07:48:43.42#ibcon#read 3, iclass 4, count 2 2006.162.07:48:43.42#ibcon#about to read 4, iclass 4, count 2 2006.162.07:48:43.42#ibcon#read 4, iclass 4, count 2 2006.162.07:48:43.42#ibcon#about to read 5, iclass 4, count 2 2006.162.07:48:43.42#ibcon#read 5, iclass 4, count 2 2006.162.07:48:43.42#ibcon#about to read 6, iclass 4, count 2 2006.162.07:48:43.42#ibcon#read 6, iclass 4, count 2 2006.162.07:48:43.42#ibcon#end of sib2, iclass 4, count 2 2006.162.07:48:43.42#ibcon#*after write, iclass 4, count 2 2006.162.07:48:43.42#ibcon#*before return 0, iclass 4, count 2 2006.162.07:48:43.42#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:48:43.42#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:48:43.42#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.162.07:48:43.42#ibcon#ireg 7 cls_cnt 0 2006.162.07:48:43.42#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:48:43.54#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:48:43.54#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:48:43.54#ibcon#enter wrdev, iclass 4, count 0 2006.162.07:48:43.54#ibcon#first serial, iclass 4, count 0 2006.162.07:48:43.54#ibcon#enter sib2, iclass 4, count 0 2006.162.07:48:43.54#ibcon#flushed, iclass 4, count 0 2006.162.07:48:43.54#ibcon#about to write, iclass 4, count 0 2006.162.07:48:43.54#ibcon#wrote, iclass 4, count 0 2006.162.07:48:43.54#ibcon#about to read 3, iclass 4, count 0 2006.162.07:48:43.56#ibcon#read 3, iclass 4, count 0 2006.162.07:48:43.56#ibcon#about to read 4, iclass 4, count 0 2006.162.07:48:43.56#ibcon#read 4, iclass 4, count 0 2006.162.07:48:43.56#ibcon#about to read 5, iclass 4, count 0 2006.162.07:48:43.56#ibcon#read 5, iclass 4, count 0 2006.162.07:48:43.56#ibcon#about to read 6, iclass 4, count 0 2006.162.07:48:43.56#ibcon#read 6, iclass 4, count 0 2006.162.07:48:43.56#ibcon#end of sib2, iclass 4, count 0 2006.162.07:48:43.56#ibcon#*mode == 0, iclass 4, count 0 2006.162.07:48:43.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.162.07:48:43.56#ibcon#[27=USB\r\n] 2006.162.07:48:43.56#ibcon#*before write, iclass 4, count 0 2006.162.07:48:43.56#ibcon#enter sib2, iclass 4, count 0 2006.162.07:48:43.56#ibcon#flushed, iclass 4, count 0 2006.162.07:48:43.56#ibcon#about to write, iclass 4, count 0 2006.162.07:48:43.56#ibcon#wrote, iclass 4, count 0 2006.162.07:48:43.56#ibcon#about to read 3, iclass 4, count 0 2006.162.07:48:43.59#ibcon#read 3, iclass 4, count 0 2006.162.07:48:43.59#ibcon#about to read 4, iclass 4, count 0 2006.162.07:48:43.59#ibcon#read 4, iclass 4, count 0 2006.162.07:48:43.59#ibcon#about to read 5, iclass 4, count 0 2006.162.07:48:43.59#ibcon#read 5, iclass 4, count 0 2006.162.07:48:43.59#ibcon#about to read 6, iclass 4, count 0 2006.162.07:48:43.59#ibcon#read 6, iclass 4, count 0 2006.162.07:48:43.59#ibcon#end of sib2, iclass 4, count 0 2006.162.07:48:43.59#ibcon#*after write, iclass 4, count 0 2006.162.07:48:43.59#ibcon#*before return 0, iclass 4, count 0 2006.162.07:48:43.59#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:48:43.59#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:48:43.59#ibcon#about to clear, iclass 4 cls_cnt 0 2006.162.07:48:43.59#ibcon#cleared, iclass 4 cls_cnt 0 2006.162.07:48:43.59$vc4f8/vblo=4,712.99 2006.162.07:48:43.59#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.162.07:48:43.59#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.162.07:48:43.59#ibcon#ireg 17 cls_cnt 0 2006.162.07:48:43.59#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:48:43.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:48:43.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:48:43.59#ibcon#enter wrdev, iclass 6, count 0 2006.162.07:48:43.59#ibcon#first serial, iclass 6, count 0 2006.162.07:48:43.59#ibcon#enter sib2, iclass 6, count 0 2006.162.07:48:43.59#ibcon#flushed, iclass 6, count 0 2006.162.07:48:43.59#ibcon#about to write, iclass 6, count 0 2006.162.07:48:43.59#ibcon#wrote, iclass 6, count 0 2006.162.07:48:43.59#ibcon#about to read 3, iclass 6, count 0 2006.162.07:48:43.61#ibcon#read 3, iclass 6, count 0 2006.162.07:48:43.61#ibcon#about to read 4, iclass 6, count 0 2006.162.07:48:43.61#ibcon#read 4, iclass 6, count 0 2006.162.07:48:43.61#ibcon#about to read 5, iclass 6, count 0 2006.162.07:48:43.61#ibcon#read 5, iclass 6, count 0 2006.162.07:48:43.61#ibcon#about to read 6, iclass 6, count 0 2006.162.07:48:43.61#ibcon#read 6, iclass 6, count 0 2006.162.07:48:43.61#ibcon#end of sib2, iclass 6, count 0 2006.162.07:48:43.61#ibcon#*mode == 0, iclass 6, count 0 2006.162.07:48:43.61#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.162.07:48:43.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.07:48:43.61#ibcon#*before write, iclass 6, count 0 2006.162.07:48:43.61#ibcon#enter sib2, iclass 6, count 0 2006.162.07:48:43.61#ibcon#flushed, iclass 6, count 0 2006.162.07:48:43.61#ibcon#about to write, iclass 6, count 0 2006.162.07:48:43.61#ibcon#wrote, iclass 6, count 0 2006.162.07:48:43.61#ibcon#about to read 3, iclass 6, count 0 2006.162.07:48:43.65#ibcon#read 3, iclass 6, count 0 2006.162.07:48:43.65#ibcon#about to read 4, iclass 6, count 0 2006.162.07:48:43.65#ibcon#read 4, iclass 6, count 0 2006.162.07:48:43.65#ibcon#about to read 5, iclass 6, count 0 2006.162.07:48:43.65#ibcon#read 5, iclass 6, count 0 2006.162.07:48:43.65#ibcon#about to read 6, iclass 6, count 0 2006.162.07:48:43.65#ibcon#read 6, iclass 6, count 0 2006.162.07:48:43.65#ibcon#end of sib2, iclass 6, count 0 2006.162.07:48:43.65#ibcon#*after write, iclass 6, count 0 2006.162.07:48:43.65#ibcon#*before return 0, iclass 6, count 0 2006.162.07:48:43.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:48:43.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:48:43.65#ibcon#about to clear, iclass 6 cls_cnt 0 2006.162.07:48:43.65#ibcon#cleared, iclass 6 cls_cnt 0 2006.162.07:48:43.65$vc4f8/vb=4,4 2006.162.07:48:43.65#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.162.07:48:43.65#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.162.07:48:43.65#ibcon#ireg 11 cls_cnt 2 2006.162.07:48:43.65#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:48:43.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:48:43.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:48:43.71#ibcon#enter wrdev, iclass 10, count 2 2006.162.07:48:43.71#ibcon#first serial, iclass 10, count 2 2006.162.07:48:43.71#ibcon#enter sib2, iclass 10, count 2 2006.162.07:48:43.71#ibcon#flushed, iclass 10, count 2 2006.162.07:48:43.71#ibcon#about to write, iclass 10, count 2 2006.162.07:48:43.71#ibcon#wrote, iclass 10, count 2 2006.162.07:48:43.71#ibcon#about to read 3, iclass 10, count 2 2006.162.07:48:43.73#ibcon#read 3, iclass 10, count 2 2006.162.07:48:43.73#ibcon#about to read 4, iclass 10, count 2 2006.162.07:48:43.73#ibcon#read 4, iclass 10, count 2 2006.162.07:48:43.73#ibcon#about to read 5, iclass 10, count 2 2006.162.07:48:43.73#ibcon#read 5, iclass 10, count 2 2006.162.07:48:43.73#ibcon#about to read 6, iclass 10, count 2 2006.162.07:48:43.73#ibcon#read 6, iclass 10, count 2 2006.162.07:48:43.73#ibcon#end of sib2, iclass 10, count 2 2006.162.07:48:43.73#ibcon#*mode == 0, iclass 10, count 2 2006.162.07:48:43.73#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.162.07:48:43.73#ibcon#[27=AT04-04\r\n] 2006.162.07:48:43.73#ibcon#*before write, iclass 10, count 2 2006.162.07:48:43.73#ibcon#enter sib2, iclass 10, count 2 2006.162.07:48:43.73#ibcon#flushed, iclass 10, count 2 2006.162.07:48:43.73#ibcon#about to write, iclass 10, count 2 2006.162.07:48:43.73#ibcon#wrote, iclass 10, count 2 2006.162.07:48:43.73#ibcon#about to read 3, iclass 10, count 2 2006.162.07:48:43.76#ibcon#read 3, iclass 10, count 2 2006.162.07:48:43.76#ibcon#about to read 4, iclass 10, count 2 2006.162.07:48:43.76#ibcon#read 4, iclass 10, count 2 2006.162.07:48:43.76#ibcon#about to read 5, iclass 10, count 2 2006.162.07:48:43.76#ibcon#read 5, iclass 10, count 2 2006.162.07:48:43.76#ibcon#about to read 6, iclass 10, count 2 2006.162.07:48:43.76#ibcon#read 6, iclass 10, count 2 2006.162.07:48:43.76#ibcon#end of sib2, iclass 10, count 2 2006.162.07:48:43.76#ibcon#*after write, iclass 10, count 2 2006.162.07:48:43.76#ibcon#*before return 0, iclass 10, count 2 2006.162.07:48:43.76#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:48:43.76#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:48:43.76#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.162.07:48:43.76#ibcon#ireg 7 cls_cnt 0 2006.162.07:48:43.76#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:48:43.88#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:48:43.88#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:48:43.88#ibcon#enter wrdev, iclass 10, count 0 2006.162.07:48:43.88#ibcon#first serial, iclass 10, count 0 2006.162.07:48:43.88#ibcon#enter sib2, iclass 10, count 0 2006.162.07:48:43.88#ibcon#flushed, iclass 10, count 0 2006.162.07:48:43.88#ibcon#about to write, iclass 10, count 0 2006.162.07:48:43.88#ibcon#wrote, iclass 10, count 0 2006.162.07:48:43.88#ibcon#about to read 3, iclass 10, count 0 2006.162.07:48:43.90#ibcon#read 3, iclass 10, count 0 2006.162.07:48:43.90#ibcon#about to read 4, iclass 10, count 0 2006.162.07:48:43.90#ibcon#read 4, iclass 10, count 0 2006.162.07:48:43.90#ibcon#about to read 5, iclass 10, count 0 2006.162.07:48:43.90#ibcon#read 5, iclass 10, count 0 2006.162.07:48:43.90#ibcon#about to read 6, iclass 10, count 0 2006.162.07:48:43.90#ibcon#read 6, iclass 10, count 0 2006.162.07:48:43.90#ibcon#end of sib2, iclass 10, count 0 2006.162.07:48:43.90#ibcon#*mode == 0, iclass 10, count 0 2006.162.07:48:43.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.162.07:48:43.90#ibcon#[27=USB\r\n] 2006.162.07:48:43.90#ibcon#*before write, iclass 10, count 0 2006.162.07:48:43.90#ibcon#enter sib2, iclass 10, count 0 2006.162.07:48:43.90#ibcon#flushed, iclass 10, count 0 2006.162.07:48:43.90#ibcon#about to write, iclass 10, count 0 2006.162.07:48:43.90#ibcon#wrote, iclass 10, count 0 2006.162.07:48:43.90#ibcon#about to read 3, iclass 10, count 0 2006.162.07:48:43.93#ibcon#read 3, iclass 10, count 0 2006.162.07:48:43.93#ibcon#about to read 4, iclass 10, count 0 2006.162.07:48:43.93#ibcon#read 4, iclass 10, count 0 2006.162.07:48:43.93#ibcon#about to read 5, iclass 10, count 0 2006.162.07:48:43.93#ibcon#read 5, iclass 10, count 0 2006.162.07:48:43.93#ibcon#about to read 6, iclass 10, count 0 2006.162.07:48:43.93#ibcon#read 6, iclass 10, count 0 2006.162.07:48:43.93#ibcon#end of sib2, iclass 10, count 0 2006.162.07:48:43.93#ibcon#*after write, iclass 10, count 0 2006.162.07:48:43.93#ibcon#*before return 0, iclass 10, count 0 2006.162.07:48:43.93#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:48:43.93#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:48:43.93#ibcon#about to clear, iclass 10 cls_cnt 0 2006.162.07:48:43.93#ibcon#cleared, iclass 10 cls_cnt 0 2006.162.07:48:43.93$vc4f8/vblo=5,744.99 2006.162.07:48:43.93#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.162.07:48:43.93#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.162.07:48:43.93#ibcon#ireg 17 cls_cnt 0 2006.162.07:48:43.93#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:48:43.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:48:43.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:48:43.93#ibcon#enter wrdev, iclass 12, count 0 2006.162.07:48:43.93#ibcon#first serial, iclass 12, count 0 2006.162.07:48:43.93#ibcon#enter sib2, iclass 12, count 0 2006.162.07:48:43.93#ibcon#flushed, iclass 12, count 0 2006.162.07:48:43.93#ibcon#about to write, iclass 12, count 0 2006.162.07:48:43.93#ibcon#wrote, iclass 12, count 0 2006.162.07:48:43.93#ibcon#about to read 3, iclass 12, count 0 2006.162.07:48:43.95#ibcon#read 3, iclass 12, count 0 2006.162.07:48:43.95#ibcon#about to read 4, iclass 12, count 0 2006.162.07:48:43.95#ibcon#read 4, iclass 12, count 0 2006.162.07:48:43.95#ibcon#about to read 5, iclass 12, count 0 2006.162.07:48:43.95#ibcon#read 5, iclass 12, count 0 2006.162.07:48:43.95#ibcon#about to read 6, iclass 12, count 0 2006.162.07:48:43.95#ibcon#read 6, iclass 12, count 0 2006.162.07:48:43.95#ibcon#end of sib2, iclass 12, count 0 2006.162.07:48:43.95#ibcon#*mode == 0, iclass 12, count 0 2006.162.07:48:43.95#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.162.07:48:43.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.07:48:43.95#ibcon#*before write, iclass 12, count 0 2006.162.07:48:43.95#ibcon#enter sib2, iclass 12, count 0 2006.162.07:48:43.95#ibcon#flushed, iclass 12, count 0 2006.162.07:48:43.95#ibcon#about to write, iclass 12, count 0 2006.162.07:48:43.95#ibcon#wrote, iclass 12, count 0 2006.162.07:48:43.95#ibcon#about to read 3, iclass 12, count 0 2006.162.07:48:43.99#ibcon#read 3, iclass 12, count 0 2006.162.07:48:43.99#ibcon#about to read 4, iclass 12, count 0 2006.162.07:48:43.99#ibcon#read 4, iclass 12, count 0 2006.162.07:48:43.99#ibcon#about to read 5, iclass 12, count 0 2006.162.07:48:43.99#ibcon#read 5, iclass 12, count 0 2006.162.07:48:43.99#ibcon#about to read 6, iclass 12, count 0 2006.162.07:48:43.99#ibcon#read 6, iclass 12, count 0 2006.162.07:48:43.99#ibcon#end of sib2, iclass 12, count 0 2006.162.07:48:43.99#ibcon#*after write, iclass 12, count 0 2006.162.07:48:43.99#ibcon#*before return 0, iclass 12, count 0 2006.162.07:48:43.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:48:43.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:48:43.99#ibcon#about to clear, iclass 12 cls_cnt 0 2006.162.07:48:43.99#ibcon#cleared, iclass 12 cls_cnt 0 2006.162.07:48:43.99$vc4f8/vb=5,4 2006.162.07:48:43.99#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.162.07:48:43.99#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.162.07:48:43.99#ibcon#ireg 11 cls_cnt 2 2006.162.07:48:43.99#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:48:44.05#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:48:44.05#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:48:44.05#ibcon#enter wrdev, iclass 14, count 2 2006.162.07:48:44.05#ibcon#first serial, iclass 14, count 2 2006.162.07:48:44.05#ibcon#enter sib2, iclass 14, count 2 2006.162.07:48:44.05#ibcon#flushed, iclass 14, count 2 2006.162.07:48:44.05#ibcon#about to write, iclass 14, count 2 2006.162.07:48:44.05#ibcon#wrote, iclass 14, count 2 2006.162.07:48:44.05#ibcon#about to read 3, iclass 14, count 2 2006.162.07:48:44.07#ibcon#read 3, iclass 14, count 2 2006.162.07:48:44.07#ibcon#about to read 4, iclass 14, count 2 2006.162.07:48:44.07#ibcon#read 4, iclass 14, count 2 2006.162.07:48:44.07#ibcon#about to read 5, iclass 14, count 2 2006.162.07:48:44.07#ibcon#read 5, iclass 14, count 2 2006.162.07:48:44.07#ibcon#about to read 6, iclass 14, count 2 2006.162.07:48:44.07#ibcon#read 6, iclass 14, count 2 2006.162.07:48:44.07#ibcon#end of sib2, iclass 14, count 2 2006.162.07:48:44.07#ibcon#*mode == 0, iclass 14, count 2 2006.162.07:48:44.07#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.162.07:48:44.07#ibcon#[27=AT05-04\r\n] 2006.162.07:48:44.07#ibcon#*before write, iclass 14, count 2 2006.162.07:48:44.07#ibcon#enter sib2, iclass 14, count 2 2006.162.07:48:44.07#ibcon#flushed, iclass 14, count 2 2006.162.07:48:44.07#ibcon#about to write, iclass 14, count 2 2006.162.07:48:44.07#ibcon#wrote, iclass 14, count 2 2006.162.07:48:44.07#ibcon#about to read 3, iclass 14, count 2 2006.162.07:48:44.10#ibcon#read 3, iclass 14, count 2 2006.162.07:48:44.10#ibcon#about to read 4, iclass 14, count 2 2006.162.07:48:44.10#ibcon#read 4, iclass 14, count 2 2006.162.07:48:44.10#ibcon#about to read 5, iclass 14, count 2 2006.162.07:48:44.10#ibcon#read 5, iclass 14, count 2 2006.162.07:48:44.10#ibcon#about to read 6, iclass 14, count 2 2006.162.07:48:44.10#ibcon#read 6, iclass 14, count 2 2006.162.07:48:44.10#ibcon#end of sib2, iclass 14, count 2 2006.162.07:48:44.10#ibcon#*after write, iclass 14, count 2 2006.162.07:48:44.10#ibcon#*before return 0, iclass 14, count 2 2006.162.07:48:44.10#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:48:44.10#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:48:44.10#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.162.07:48:44.10#ibcon#ireg 7 cls_cnt 0 2006.162.07:48:44.10#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:48:44.22#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:48:44.22#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:48:44.22#ibcon#enter wrdev, iclass 14, count 0 2006.162.07:48:44.22#ibcon#first serial, iclass 14, count 0 2006.162.07:48:44.22#ibcon#enter sib2, iclass 14, count 0 2006.162.07:48:44.22#ibcon#flushed, iclass 14, count 0 2006.162.07:48:44.22#ibcon#about to write, iclass 14, count 0 2006.162.07:48:44.22#ibcon#wrote, iclass 14, count 0 2006.162.07:48:44.22#ibcon#about to read 3, iclass 14, count 0 2006.162.07:48:44.24#ibcon#read 3, iclass 14, count 0 2006.162.07:48:44.24#ibcon#about to read 4, iclass 14, count 0 2006.162.07:48:44.24#ibcon#read 4, iclass 14, count 0 2006.162.07:48:44.24#ibcon#about to read 5, iclass 14, count 0 2006.162.07:48:44.24#ibcon#read 5, iclass 14, count 0 2006.162.07:48:44.24#ibcon#about to read 6, iclass 14, count 0 2006.162.07:48:44.24#ibcon#read 6, iclass 14, count 0 2006.162.07:48:44.24#ibcon#end of sib2, iclass 14, count 0 2006.162.07:48:44.24#ibcon#*mode == 0, iclass 14, count 0 2006.162.07:48:44.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.07:48:44.24#ibcon#[27=USB\r\n] 2006.162.07:48:44.24#ibcon#*before write, iclass 14, count 0 2006.162.07:48:44.24#ibcon#enter sib2, iclass 14, count 0 2006.162.07:48:44.24#ibcon#flushed, iclass 14, count 0 2006.162.07:48:44.24#ibcon#about to write, iclass 14, count 0 2006.162.07:48:44.24#ibcon#wrote, iclass 14, count 0 2006.162.07:48:44.24#ibcon#about to read 3, iclass 14, count 0 2006.162.07:48:44.27#ibcon#read 3, iclass 14, count 0 2006.162.07:48:44.27#ibcon#about to read 4, iclass 14, count 0 2006.162.07:48:44.27#ibcon#read 4, iclass 14, count 0 2006.162.07:48:44.27#ibcon#about to read 5, iclass 14, count 0 2006.162.07:48:44.27#ibcon#read 5, iclass 14, count 0 2006.162.07:48:44.27#ibcon#about to read 6, iclass 14, count 0 2006.162.07:48:44.27#ibcon#read 6, iclass 14, count 0 2006.162.07:48:44.27#ibcon#end of sib2, iclass 14, count 0 2006.162.07:48:44.27#ibcon#*after write, iclass 14, count 0 2006.162.07:48:44.27#ibcon#*before return 0, iclass 14, count 0 2006.162.07:48:44.27#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:48:44.27#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:48:44.27#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.07:48:44.27#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.07:48:44.27$vc4f8/vblo=6,752.99 2006.162.07:48:44.27#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.162.07:48:44.27#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.162.07:48:44.27#ibcon#ireg 17 cls_cnt 0 2006.162.07:48:44.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:48:44.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:48:44.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:48:44.27#ibcon#enter wrdev, iclass 16, count 0 2006.162.07:48:44.27#ibcon#first serial, iclass 16, count 0 2006.162.07:48:44.27#ibcon#enter sib2, iclass 16, count 0 2006.162.07:48:44.27#ibcon#flushed, iclass 16, count 0 2006.162.07:48:44.27#ibcon#about to write, iclass 16, count 0 2006.162.07:48:44.27#ibcon#wrote, iclass 16, count 0 2006.162.07:48:44.27#ibcon#about to read 3, iclass 16, count 0 2006.162.07:48:44.29#ibcon#read 3, iclass 16, count 0 2006.162.07:48:44.29#ibcon#about to read 4, iclass 16, count 0 2006.162.07:48:44.29#ibcon#read 4, iclass 16, count 0 2006.162.07:48:44.29#ibcon#about to read 5, iclass 16, count 0 2006.162.07:48:44.29#ibcon#read 5, iclass 16, count 0 2006.162.07:48:44.29#ibcon#about to read 6, iclass 16, count 0 2006.162.07:48:44.29#ibcon#read 6, iclass 16, count 0 2006.162.07:48:44.29#ibcon#end of sib2, iclass 16, count 0 2006.162.07:48:44.29#ibcon#*mode == 0, iclass 16, count 0 2006.162.07:48:44.29#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.162.07:48:44.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.07:48:44.29#ibcon#*before write, iclass 16, count 0 2006.162.07:48:44.29#ibcon#enter sib2, iclass 16, count 0 2006.162.07:48:44.29#ibcon#flushed, iclass 16, count 0 2006.162.07:48:44.29#ibcon#about to write, iclass 16, count 0 2006.162.07:48:44.29#ibcon#wrote, iclass 16, count 0 2006.162.07:48:44.29#ibcon#about to read 3, iclass 16, count 0 2006.162.07:48:44.33#ibcon#read 3, iclass 16, count 0 2006.162.07:48:44.33#ibcon#about to read 4, iclass 16, count 0 2006.162.07:48:44.33#ibcon#read 4, iclass 16, count 0 2006.162.07:48:44.33#ibcon#about to read 5, iclass 16, count 0 2006.162.07:48:44.33#ibcon#read 5, iclass 16, count 0 2006.162.07:48:44.33#ibcon#about to read 6, iclass 16, count 0 2006.162.07:48:44.33#ibcon#read 6, iclass 16, count 0 2006.162.07:48:44.33#ibcon#end of sib2, iclass 16, count 0 2006.162.07:48:44.33#ibcon#*after write, iclass 16, count 0 2006.162.07:48:44.33#ibcon#*before return 0, iclass 16, count 0 2006.162.07:48:44.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:48:44.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.162.07:48:44.33#ibcon#about to clear, iclass 16 cls_cnt 0 2006.162.07:48:44.33#ibcon#cleared, iclass 16 cls_cnt 0 2006.162.07:48:44.33$vc4f8/vb=6,4 2006.162.07:48:44.33#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.162.07:48:44.33#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.162.07:48:44.33#ibcon#ireg 11 cls_cnt 2 2006.162.07:48:44.33#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:48:44.39#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:48:44.39#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:48:44.39#ibcon#enter wrdev, iclass 18, count 2 2006.162.07:48:44.39#ibcon#first serial, iclass 18, count 2 2006.162.07:48:44.39#ibcon#enter sib2, iclass 18, count 2 2006.162.07:48:44.39#ibcon#flushed, iclass 18, count 2 2006.162.07:48:44.39#ibcon#about to write, iclass 18, count 2 2006.162.07:48:44.39#ibcon#wrote, iclass 18, count 2 2006.162.07:48:44.39#ibcon#about to read 3, iclass 18, count 2 2006.162.07:48:44.41#ibcon#read 3, iclass 18, count 2 2006.162.07:48:44.41#ibcon#about to read 4, iclass 18, count 2 2006.162.07:48:44.41#ibcon#read 4, iclass 18, count 2 2006.162.07:48:44.41#ibcon#about to read 5, iclass 18, count 2 2006.162.07:48:44.41#ibcon#read 5, iclass 18, count 2 2006.162.07:48:44.41#ibcon#about to read 6, iclass 18, count 2 2006.162.07:48:44.41#ibcon#read 6, iclass 18, count 2 2006.162.07:48:44.41#ibcon#end of sib2, iclass 18, count 2 2006.162.07:48:44.41#ibcon#*mode == 0, iclass 18, count 2 2006.162.07:48:44.41#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.162.07:48:44.41#ibcon#[27=AT06-04\r\n] 2006.162.07:48:44.41#ibcon#*before write, iclass 18, count 2 2006.162.07:48:44.41#ibcon#enter sib2, iclass 18, count 2 2006.162.07:48:44.41#ibcon#flushed, iclass 18, count 2 2006.162.07:48:44.41#ibcon#about to write, iclass 18, count 2 2006.162.07:48:44.41#ibcon#wrote, iclass 18, count 2 2006.162.07:48:44.41#ibcon#about to read 3, iclass 18, count 2 2006.162.07:48:44.44#ibcon#read 3, iclass 18, count 2 2006.162.07:48:44.44#ibcon#about to read 4, iclass 18, count 2 2006.162.07:48:44.44#ibcon#read 4, iclass 18, count 2 2006.162.07:48:44.44#ibcon#about to read 5, iclass 18, count 2 2006.162.07:48:44.44#ibcon#read 5, iclass 18, count 2 2006.162.07:48:44.44#ibcon#about to read 6, iclass 18, count 2 2006.162.07:48:44.44#ibcon#read 6, iclass 18, count 2 2006.162.07:48:44.44#ibcon#end of sib2, iclass 18, count 2 2006.162.07:48:44.44#ibcon#*after write, iclass 18, count 2 2006.162.07:48:44.44#ibcon#*before return 0, iclass 18, count 2 2006.162.07:48:44.44#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:48:44.44#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.162.07:48:44.44#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.162.07:48:44.44#ibcon#ireg 7 cls_cnt 0 2006.162.07:48:44.44#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:48:44.56#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:48:44.56#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:48:44.56#ibcon#enter wrdev, iclass 18, count 0 2006.162.07:48:44.56#ibcon#first serial, iclass 18, count 0 2006.162.07:48:44.56#ibcon#enter sib2, iclass 18, count 0 2006.162.07:48:44.56#ibcon#flushed, iclass 18, count 0 2006.162.07:48:44.56#ibcon#about to write, iclass 18, count 0 2006.162.07:48:44.56#ibcon#wrote, iclass 18, count 0 2006.162.07:48:44.56#ibcon#about to read 3, iclass 18, count 0 2006.162.07:48:44.58#ibcon#read 3, iclass 18, count 0 2006.162.07:48:44.58#ibcon#about to read 4, iclass 18, count 0 2006.162.07:48:44.58#ibcon#read 4, iclass 18, count 0 2006.162.07:48:44.58#ibcon#about to read 5, iclass 18, count 0 2006.162.07:48:44.58#ibcon#read 5, iclass 18, count 0 2006.162.07:48:44.58#ibcon#about to read 6, iclass 18, count 0 2006.162.07:48:44.58#ibcon#read 6, iclass 18, count 0 2006.162.07:48:44.58#ibcon#end of sib2, iclass 18, count 0 2006.162.07:48:44.58#ibcon#*mode == 0, iclass 18, count 0 2006.162.07:48:44.58#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.162.07:48:44.58#ibcon#[27=USB\r\n] 2006.162.07:48:44.58#ibcon#*before write, iclass 18, count 0 2006.162.07:48:44.58#ibcon#enter sib2, iclass 18, count 0 2006.162.07:48:44.58#ibcon#flushed, iclass 18, count 0 2006.162.07:48:44.58#ibcon#about to write, iclass 18, count 0 2006.162.07:48:44.58#ibcon#wrote, iclass 18, count 0 2006.162.07:48:44.58#ibcon#about to read 3, iclass 18, count 0 2006.162.07:48:44.61#ibcon#read 3, iclass 18, count 0 2006.162.07:48:44.61#ibcon#about to read 4, iclass 18, count 0 2006.162.07:48:44.61#ibcon#read 4, iclass 18, count 0 2006.162.07:48:44.61#ibcon#about to read 5, iclass 18, count 0 2006.162.07:48:44.61#ibcon#read 5, iclass 18, count 0 2006.162.07:48:44.61#ibcon#about to read 6, iclass 18, count 0 2006.162.07:48:44.61#ibcon#read 6, iclass 18, count 0 2006.162.07:48:44.61#ibcon#end of sib2, iclass 18, count 0 2006.162.07:48:44.61#ibcon#*after write, iclass 18, count 0 2006.162.07:48:44.61#ibcon#*before return 0, iclass 18, count 0 2006.162.07:48:44.61#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:48:44.61#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.162.07:48:44.61#ibcon#about to clear, iclass 18 cls_cnt 0 2006.162.07:48:44.61#ibcon#cleared, iclass 18 cls_cnt 0 2006.162.07:48:44.61$vc4f8/vabw=wide 2006.162.07:48:44.61#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.162.07:48:44.61#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.162.07:48:44.61#ibcon#ireg 8 cls_cnt 0 2006.162.07:48:44.61#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:48:44.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:48:44.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:48:44.61#ibcon#enter wrdev, iclass 20, count 0 2006.162.07:48:44.61#ibcon#first serial, iclass 20, count 0 2006.162.07:48:44.61#ibcon#enter sib2, iclass 20, count 0 2006.162.07:48:44.61#ibcon#flushed, iclass 20, count 0 2006.162.07:48:44.61#ibcon#about to write, iclass 20, count 0 2006.162.07:48:44.61#ibcon#wrote, iclass 20, count 0 2006.162.07:48:44.61#ibcon#about to read 3, iclass 20, count 0 2006.162.07:48:44.63#ibcon#read 3, iclass 20, count 0 2006.162.07:48:44.63#ibcon#about to read 4, iclass 20, count 0 2006.162.07:48:44.63#ibcon#read 4, iclass 20, count 0 2006.162.07:48:44.63#ibcon#about to read 5, iclass 20, count 0 2006.162.07:48:44.63#ibcon#read 5, iclass 20, count 0 2006.162.07:48:44.63#ibcon#about to read 6, iclass 20, count 0 2006.162.07:48:44.63#ibcon#read 6, iclass 20, count 0 2006.162.07:48:44.63#ibcon#end of sib2, iclass 20, count 0 2006.162.07:48:44.63#ibcon#*mode == 0, iclass 20, count 0 2006.162.07:48:44.63#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.07:48:44.63#ibcon#[25=BW32\r\n] 2006.162.07:48:44.63#ibcon#*before write, iclass 20, count 0 2006.162.07:48:44.63#ibcon#enter sib2, iclass 20, count 0 2006.162.07:48:44.63#ibcon#flushed, iclass 20, count 0 2006.162.07:48:44.63#ibcon#about to write, iclass 20, count 0 2006.162.07:48:44.63#ibcon#wrote, iclass 20, count 0 2006.162.07:48:44.63#ibcon#about to read 3, iclass 20, count 0 2006.162.07:48:44.66#ibcon#read 3, iclass 20, count 0 2006.162.07:48:44.66#ibcon#about to read 4, iclass 20, count 0 2006.162.07:48:44.66#ibcon#read 4, iclass 20, count 0 2006.162.07:48:44.66#ibcon#about to read 5, iclass 20, count 0 2006.162.07:48:44.66#ibcon#read 5, iclass 20, count 0 2006.162.07:48:44.66#ibcon#about to read 6, iclass 20, count 0 2006.162.07:48:44.66#ibcon#read 6, iclass 20, count 0 2006.162.07:48:44.66#ibcon#end of sib2, iclass 20, count 0 2006.162.07:48:44.66#ibcon#*after write, iclass 20, count 0 2006.162.07:48:44.66#ibcon#*before return 0, iclass 20, count 0 2006.162.07:48:44.66#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:48:44.66#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:48:44.66#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.07:48:44.66#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.07:48:44.66$vc4f8/vbbw=wide 2006.162.07:48:44.66#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.162.07:48:44.66#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.162.07:48:44.66#ibcon#ireg 8 cls_cnt 0 2006.162.07:48:44.66#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:48:44.73#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:48:44.73#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:48:44.73#ibcon#enter wrdev, iclass 22, count 0 2006.162.07:48:44.73#ibcon#first serial, iclass 22, count 0 2006.162.07:48:44.73#ibcon#enter sib2, iclass 22, count 0 2006.162.07:48:44.73#ibcon#flushed, iclass 22, count 0 2006.162.07:48:44.73#ibcon#about to write, iclass 22, count 0 2006.162.07:48:44.73#ibcon#wrote, iclass 22, count 0 2006.162.07:48:44.73#ibcon#about to read 3, iclass 22, count 0 2006.162.07:48:44.75#ibcon#read 3, iclass 22, count 0 2006.162.07:48:44.75#ibcon#about to read 4, iclass 22, count 0 2006.162.07:48:44.75#ibcon#read 4, iclass 22, count 0 2006.162.07:48:44.75#ibcon#about to read 5, iclass 22, count 0 2006.162.07:48:44.75#ibcon#read 5, iclass 22, count 0 2006.162.07:48:44.75#ibcon#about to read 6, iclass 22, count 0 2006.162.07:48:44.75#ibcon#read 6, iclass 22, count 0 2006.162.07:48:44.75#ibcon#end of sib2, iclass 22, count 0 2006.162.07:48:44.75#ibcon#*mode == 0, iclass 22, count 0 2006.162.07:48:44.75#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.07:48:44.75#ibcon#[27=BW32\r\n] 2006.162.07:48:44.75#ibcon#*before write, iclass 22, count 0 2006.162.07:48:44.75#ibcon#enter sib2, iclass 22, count 0 2006.162.07:48:44.75#ibcon#flushed, iclass 22, count 0 2006.162.07:48:44.75#ibcon#about to write, iclass 22, count 0 2006.162.07:48:44.75#ibcon#wrote, iclass 22, count 0 2006.162.07:48:44.75#ibcon#about to read 3, iclass 22, count 0 2006.162.07:48:44.78#ibcon#read 3, iclass 22, count 0 2006.162.07:48:44.78#ibcon#about to read 4, iclass 22, count 0 2006.162.07:48:44.78#ibcon#read 4, iclass 22, count 0 2006.162.07:48:44.78#ibcon#about to read 5, iclass 22, count 0 2006.162.07:48:44.78#ibcon#read 5, iclass 22, count 0 2006.162.07:48:44.78#ibcon#about to read 6, iclass 22, count 0 2006.162.07:48:44.78#ibcon#read 6, iclass 22, count 0 2006.162.07:48:44.78#ibcon#end of sib2, iclass 22, count 0 2006.162.07:48:44.78#ibcon#*after write, iclass 22, count 0 2006.162.07:48:44.78#ibcon#*before return 0, iclass 22, count 0 2006.162.07:48:44.78#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:48:44.78#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:48:44.78#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.07:48:44.78#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.07:48:44.78$4f8m12a/ifd4f 2006.162.07:48:44.78$ifd4f/lo= 2006.162.07:48:44.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.07:48:44.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.07:48:44.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.07:48:44.78$ifd4f/patch= 2006.162.07:48:44.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.07:48:44.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.07:48:44.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.07:48:44.78$4f8m12a/"form=m,16.000,1:2 2006.162.07:48:44.78$4f8m12a/"tpicd 2006.162.07:48:44.78$4f8m12a/echo=off 2006.162.07:48:44.78$4f8m12a/xlog=off 2006.162.07:48:44.78:!2006.162.07:49:10 2006.162.07:48:55.14#trakl#Source acquired 2006.162.07:48:55.14#flagr#flagr/antenna,acquired 2006.162.07:49:10.00:preob 2006.162.07:49:11.14/onsource/TRACKING 2006.162.07:49:11.14:!2006.162.07:49:20 2006.162.07:49:20.00:data_valid=on 2006.162.07:49:20.00:midob 2006.162.07:49:20.14/onsource/TRACKING 2006.162.07:49:20.14/wx/17.87,1007.2,100 2006.162.07:49:20.21/cable/+6.5365E-03 2006.162.07:49:21.30/va/01,08,usb,yes,39,41 2006.162.07:49:21.30/va/02,07,usb,yes,39,41 2006.162.07:49:21.30/va/03,06,usb,yes,42,42 2006.162.07:49:21.30/va/04,07,usb,yes,40,43 2006.162.07:49:21.30/va/05,07,usb,yes,43,45 2006.162.07:49:21.30/va/06,06,usb,yes,42,42 2006.162.07:49:21.30/va/07,06,usb,yes,42,42 2006.162.07:49:21.30/va/08,07,usb,yes,40,40 2006.162.07:49:21.53/valo/01,532.99,yes,locked 2006.162.07:49:21.53/valo/02,572.99,yes,locked 2006.162.07:49:21.53/valo/03,672.99,yes,locked 2006.162.07:49:21.53/valo/04,832.99,yes,locked 2006.162.07:49:21.53/valo/05,652.99,yes,locked 2006.162.07:49:21.53/valo/06,772.99,yes,locked 2006.162.07:49:21.53/valo/07,832.99,yes,locked 2006.162.07:49:21.53/valo/08,852.99,yes,locked 2006.162.07:49:22.62/vb/01,04,usb,yes,29,28 2006.162.07:49:22.62/vb/02,04,usb,yes,31,32 2006.162.07:49:22.62/vb/03,04,usb,yes,27,31 2006.162.07:49:22.62/vb/04,04,usb,yes,28,28 2006.162.07:49:22.62/vb/05,04,usb,yes,27,31 2006.162.07:49:22.62/vb/06,04,usb,yes,28,31 2006.162.07:49:22.62/vb/07,04,usb,yes,30,30 2006.162.07:49:22.62/vb/08,04,usb,yes,27,31 2006.162.07:49:22.85/vblo/01,632.99,yes,locked 2006.162.07:49:22.85/vblo/02,640.99,yes,locked 2006.162.07:49:22.85/vblo/03,656.99,yes,locked 2006.162.07:49:22.85/vblo/04,712.99,yes,locked 2006.162.07:49:22.85/vblo/05,744.99,yes,locked 2006.162.07:49:22.85/vblo/06,752.99,yes,locked 2006.162.07:49:22.85/vblo/07,734.99,yes,locked 2006.162.07:49:22.85/vblo/08,744.99,yes,locked 2006.162.07:49:23.00/vabw/8 2006.162.07:49:23.15/vbbw/8 2006.162.07:49:23.24/xfe/off,on,15.2 2006.162.07:49:23.62/ifatt/23,28,28,28 2006.162.07:49:24.07/fmout-gps/S +4.46E-07 2006.162.07:49:24.15:!2006.162.07:51:40 2006.162.07:51:40.00:data_valid=off 2006.162.07:51:40.00:postob 2006.162.07:51:40.18/cable/+6.5352E-03 2006.162.07:51:40.22/wx/17.87,1007.2,100 2006.162.07:51:41.08/fmout-gps/S +4.48E-07 2006.162.07:51:41.08:scan_name=162-0753,k06162,60 2006.162.07:51:41.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.162.07:51:42.14#flagr#flagr/antenna,new-source 2006.162.07:51:42.14:checkk5 2006.162.07:51:42.53/chk_autoobs//k5ts1/ autoobs is running! 2006.162.07:51:42.92/chk_autoobs//k5ts2/ autoobs is running! 2006.162.07:51:43.54/chk_autoobs//k5ts3/ autoobs is running! 2006.162.07:51:44.00/chk_autoobs//k5ts4/ autoobs is running! 2006.162.07:51:44.71/chk_obsdata//k5ts1/T1620749??a.dat file size is correct (nominal:1120MB, actual:1112MB). 2006.162.07:51:45.12/chk_obsdata//k5ts2/T1620749??b.dat file size is correct (nominal:1120MB, actual:1112MB). 2006.162.07:51:45.55/chk_obsdata//k5ts3/T1620749??c.dat file size is correct (nominal:1120MB, actual:1112MB). 2006.162.07:51:45.99/chk_obsdata//k5ts4/T1620749??d.dat file size is correct (nominal:1120MB, actual:1112MB). 2006.162.07:51:46.99/k5log//k5ts1_log_newline 2006.162.07:51:48.26/k5log//k5ts2_log_newline 2006.162.07:51:49.02/k5log//k5ts3_log_newline 2006.162.07:51:50.29/k5log//k5ts4_log_newline 2006.162.07:51:50.32/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.07:51:50.32:4f8m12a=2 2006.162.07:51:50.32$4f8m12a/echo=on 2006.162.07:51:50.32$4f8m12a/pcalon 2006.162.07:51:50.32$pcalon/"no phase cal control is implemented here 2006.162.07:51:50.32$4f8m12a/"tpicd=stop 2006.162.07:51:50.32$4f8m12a/vc4f8 2006.162.07:51:50.32$vc4f8/valo=1,532.99 2006.162.07:51:50.32#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.162.07:51:50.32#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.162.07:51:50.32#ibcon#ireg 17 cls_cnt 0 2006.162.07:51:50.32#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:51:50.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:51:50.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:51:50.32#ibcon#enter wrdev, iclass 20, count 0 2006.162.07:51:50.32#ibcon#first serial, iclass 20, count 0 2006.162.07:51:50.32#ibcon#enter sib2, iclass 20, count 0 2006.162.07:51:50.32#ibcon#flushed, iclass 20, count 0 2006.162.07:51:50.32#ibcon#about to write, iclass 20, count 0 2006.162.07:51:50.32#ibcon#wrote, iclass 20, count 0 2006.162.07:51:50.32#ibcon#about to read 3, iclass 20, count 0 2006.162.07:51:50.34#ibcon#read 3, iclass 20, count 0 2006.162.07:51:50.34#ibcon#about to read 4, iclass 20, count 0 2006.162.07:51:50.34#ibcon#read 4, iclass 20, count 0 2006.162.07:51:50.34#ibcon#about to read 5, iclass 20, count 0 2006.162.07:51:50.34#ibcon#read 5, iclass 20, count 0 2006.162.07:51:50.34#ibcon#about to read 6, iclass 20, count 0 2006.162.07:51:50.34#ibcon#read 6, iclass 20, count 0 2006.162.07:51:50.34#ibcon#end of sib2, iclass 20, count 0 2006.162.07:51:50.34#ibcon#*mode == 0, iclass 20, count 0 2006.162.07:51:50.34#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.07:51:50.34#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.07:51:50.34#ibcon#*before write, iclass 20, count 0 2006.162.07:51:50.34#ibcon#enter sib2, iclass 20, count 0 2006.162.07:51:50.34#ibcon#flushed, iclass 20, count 0 2006.162.07:51:50.34#ibcon#about to write, iclass 20, count 0 2006.162.07:51:50.34#ibcon#wrote, iclass 20, count 0 2006.162.07:51:50.34#ibcon#about to read 3, iclass 20, count 0 2006.162.07:51:50.39#ibcon#read 3, iclass 20, count 0 2006.162.07:51:50.39#ibcon#about to read 4, iclass 20, count 0 2006.162.07:51:50.39#ibcon#read 4, iclass 20, count 0 2006.162.07:51:50.39#ibcon#about to read 5, iclass 20, count 0 2006.162.07:51:50.39#ibcon#read 5, iclass 20, count 0 2006.162.07:51:50.39#ibcon#about to read 6, iclass 20, count 0 2006.162.07:51:50.39#ibcon#read 6, iclass 20, count 0 2006.162.07:51:50.39#ibcon#end of sib2, iclass 20, count 0 2006.162.07:51:50.39#ibcon#*after write, iclass 20, count 0 2006.162.07:51:50.39#ibcon#*before return 0, iclass 20, count 0 2006.162.07:51:50.39#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:51:50.39#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:51:50.39#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.07:51:50.39#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.07:51:50.39$vc4f8/va=1,8 2006.162.07:51:50.39#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.162.07:51:50.39#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.162.07:51:50.39#ibcon#ireg 11 cls_cnt 2 2006.162.07:51:50.39#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:51:50.39#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:51:50.39#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:51:50.39#ibcon#enter wrdev, iclass 22, count 2 2006.162.07:51:50.39#ibcon#first serial, iclass 22, count 2 2006.162.07:51:50.39#ibcon#enter sib2, iclass 22, count 2 2006.162.07:51:50.39#ibcon#flushed, iclass 22, count 2 2006.162.07:51:50.39#ibcon#about to write, iclass 22, count 2 2006.162.07:51:50.39#ibcon#wrote, iclass 22, count 2 2006.162.07:51:50.39#ibcon#about to read 3, iclass 22, count 2 2006.162.07:51:50.41#ibcon#read 3, iclass 22, count 2 2006.162.07:51:50.41#ibcon#about to read 4, iclass 22, count 2 2006.162.07:51:50.41#ibcon#read 4, iclass 22, count 2 2006.162.07:51:50.41#ibcon#about to read 5, iclass 22, count 2 2006.162.07:51:50.41#ibcon#read 5, iclass 22, count 2 2006.162.07:51:50.41#ibcon#about to read 6, iclass 22, count 2 2006.162.07:51:50.41#ibcon#read 6, iclass 22, count 2 2006.162.07:51:50.41#ibcon#end of sib2, iclass 22, count 2 2006.162.07:51:50.41#ibcon#*mode == 0, iclass 22, count 2 2006.162.07:51:50.41#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.162.07:51:50.41#ibcon#[25=AT01-08\r\n] 2006.162.07:51:50.41#ibcon#*before write, iclass 22, count 2 2006.162.07:51:50.41#ibcon#enter sib2, iclass 22, count 2 2006.162.07:51:50.41#ibcon#flushed, iclass 22, count 2 2006.162.07:51:50.41#ibcon#about to write, iclass 22, count 2 2006.162.07:51:50.41#ibcon#wrote, iclass 22, count 2 2006.162.07:51:50.41#ibcon#about to read 3, iclass 22, count 2 2006.162.07:51:50.44#ibcon#read 3, iclass 22, count 2 2006.162.07:51:50.44#ibcon#about to read 4, iclass 22, count 2 2006.162.07:51:50.44#ibcon#read 4, iclass 22, count 2 2006.162.07:51:50.44#ibcon#about to read 5, iclass 22, count 2 2006.162.07:51:50.44#ibcon#read 5, iclass 22, count 2 2006.162.07:51:50.44#ibcon#about to read 6, iclass 22, count 2 2006.162.07:51:50.44#ibcon#read 6, iclass 22, count 2 2006.162.07:51:50.44#ibcon#end of sib2, iclass 22, count 2 2006.162.07:51:50.44#ibcon#*after write, iclass 22, count 2 2006.162.07:51:50.44#ibcon#*before return 0, iclass 22, count 2 2006.162.07:51:50.44#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:51:50.44#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:51:50.44#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.162.07:51:50.44#ibcon#ireg 7 cls_cnt 0 2006.162.07:51:50.44#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:51:50.56#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:51:50.56#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:51:50.56#ibcon#enter wrdev, iclass 22, count 0 2006.162.07:51:50.56#ibcon#first serial, iclass 22, count 0 2006.162.07:51:50.56#ibcon#enter sib2, iclass 22, count 0 2006.162.07:51:50.56#ibcon#flushed, iclass 22, count 0 2006.162.07:51:50.56#ibcon#about to write, iclass 22, count 0 2006.162.07:51:50.56#ibcon#wrote, iclass 22, count 0 2006.162.07:51:50.56#ibcon#about to read 3, iclass 22, count 0 2006.162.07:51:50.58#ibcon#read 3, iclass 22, count 0 2006.162.07:51:50.58#ibcon#about to read 4, iclass 22, count 0 2006.162.07:51:50.58#ibcon#read 4, iclass 22, count 0 2006.162.07:51:50.58#ibcon#about to read 5, iclass 22, count 0 2006.162.07:51:50.58#ibcon#read 5, iclass 22, count 0 2006.162.07:51:50.58#ibcon#about to read 6, iclass 22, count 0 2006.162.07:51:50.58#ibcon#read 6, iclass 22, count 0 2006.162.07:51:50.58#ibcon#end of sib2, iclass 22, count 0 2006.162.07:51:50.58#ibcon#*mode == 0, iclass 22, count 0 2006.162.07:51:50.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.07:51:50.58#ibcon#[25=USB\r\n] 2006.162.07:51:50.58#ibcon#*before write, iclass 22, count 0 2006.162.07:51:50.58#ibcon#enter sib2, iclass 22, count 0 2006.162.07:51:50.58#ibcon#flushed, iclass 22, count 0 2006.162.07:51:50.58#ibcon#about to write, iclass 22, count 0 2006.162.07:51:50.58#ibcon#wrote, iclass 22, count 0 2006.162.07:51:50.58#ibcon#about to read 3, iclass 22, count 0 2006.162.07:51:50.61#ibcon#read 3, iclass 22, count 0 2006.162.07:51:50.61#ibcon#about to read 4, iclass 22, count 0 2006.162.07:51:50.61#ibcon#read 4, iclass 22, count 0 2006.162.07:51:50.61#ibcon#about to read 5, iclass 22, count 0 2006.162.07:51:50.61#ibcon#read 5, iclass 22, count 0 2006.162.07:51:50.61#ibcon#about to read 6, iclass 22, count 0 2006.162.07:51:50.61#ibcon#read 6, iclass 22, count 0 2006.162.07:51:50.61#ibcon#end of sib2, iclass 22, count 0 2006.162.07:51:50.61#ibcon#*after write, iclass 22, count 0 2006.162.07:51:50.61#ibcon#*before return 0, iclass 22, count 0 2006.162.07:51:50.61#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:51:50.61#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:51:50.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.07:51:50.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.07:51:50.61$vc4f8/valo=2,572.99 2006.162.07:51:50.61#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.162.07:51:50.61#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.162.07:51:50.61#ibcon#ireg 17 cls_cnt 0 2006.162.07:51:50.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:51:50.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:51:50.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:51:50.61#ibcon#enter wrdev, iclass 24, count 0 2006.162.07:51:50.61#ibcon#first serial, iclass 24, count 0 2006.162.07:51:50.61#ibcon#enter sib2, iclass 24, count 0 2006.162.07:51:50.61#ibcon#flushed, iclass 24, count 0 2006.162.07:51:50.61#ibcon#about to write, iclass 24, count 0 2006.162.07:51:50.61#ibcon#wrote, iclass 24, count 0 2006.162.07:51:50.61#ibcon#about to read 3, iclass 24, count 0 2006.162.07:51:50.63#ibcon#read 3, iclass 24, count 0 2006.162.07:51:50.63#ibcon#about to read 4, iclass 24, count 0 2006.162.07:51:50.63#ibcon#read 4, iclass 24, count 0 2006.162.07:51:50.63#ibcon#about to read 5, iclass 24, count 0 2006.162.07:51:50.63#ibcon#read 5, iclass 24, count 0 2006.162.07:51:50.63#ibcon#about to read 6, iclass 24, count 0 2006.162.07:51:50.63#ibcon#read 6, iclass 24, count 0 2006.162.07:51:50.63#ibcon#end of sib2, iclass 24, count 0 2006.162.07:51:50.63#ibcon#*mode == 0, iclass 24, count 0 2006.162.07:51:50.63#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.07:51:50.63#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.07:51:50.63#ibcon#*before write, iclass 24, count 0 2006.162.07:51:50.63#ibcon#enter sib2, iclass 24, count 0 2006.162.07:51:50.63#ibcon#flushed, iclass 24, count 0 2006.162.07:51:50.63#ibcon#about to write, iclass 24, count 0 2006.162.07:51:50.63#ibcon#wrote, iclass 24, count 0 2006.162.07:51:50.63#ibcon#about to read 3, iclass 24, count 0 2006.162.07:51:50.67#ibcon#read 3, iclass 24, count 0 2006.162.07:51:50.67#ibcon#about to read 4, iclass 24, count 0 2006.162.07:51:50.67#ibcon#read 4, iclass 24, count 0 2006.162.07:51:50.67#ibcon#about to read 5, iclass 24, count 0 2006.162.07:51:50.67#ibcon#read 5, iclass 24, count 0 2006.162.07:51:50.67#ibcon#about to read 6, iclass 24, count 0 2006.162.07:51:50.67#ibcon#read 6, iclass 24, count 0 2006.162.07:51:50.67#ibcon#end of sib2, iclass 24, count 0 2006.162.07:51:50.67#ibcon#*after write, iclass 24, count 0 2006.162.07:51:50.67#ibcon#*before return 0, iclass 24, count 0 2006.162.07:51:50.67#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:51:50.67#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:51:50.67#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.07:51:50.67#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.07:51:50.67$vc4f8/va=2,7 2006.162.07:51:50.67#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.162.07:51:50.67#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.162.07:51:50.67#ibcon#ireg 11 cls_cnt 2 2006.162.07:51:50.67#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:51:50.73#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:51:50.73#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:51:50.73#ibcon#enter wrdev, iclass 26, count 2 2006.162.07:51:50.73#ibcon#first serial, iclass 26, count 2 2006.162.07:51:50.73#ibcon#enter sib2, iclass 26, count 2 2006.162.07:51:50.73#ibcon#flushed, iclass 26, count 2 2006.162.07:51:50.73#ibcon#about to write, iclass 26, count 2 2006.162.07:51:50.73#ibcon#wrote, iclass 26, count 2 2006.162.07:51:50.73#ibcon#about to read 3, iclass 26, count 2 2006.162.07:51:50.75#ibcon#read 3, iclass 26, count 2 2006.162.07:51:50.75#ibcon#about to read 4, iclass 26, count 2 2006.162.07:51:50.75#ibcon#read 4, iclass 26, count 2 2006.162.07:51:50.75#ibcon#about to read 5, iclass 26, count 2 2006.162.07:51:50.75#ibcon#read 5, iclass 26, count 2 2006.162.07:51:50.75#ibcon#about to read 6, iclass 26, count 2 2006.162.07:51:50.75#ibcon#read 6, iclass 26, count 2 2006.162.07:51:50.75#ibcon#end of sib2, iclass 26, count 2 2006.162.07:51:50.75#ibcon#*mode == 0, iclass 26, count 2 2006.162.07:51:50.75#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.162.07:51:50.75#ibcon#[25=AT02-07\r\n] 2006.162.07:51:50.75#ibcon#*before write, iclass 26, count 2 2006.162.07:51:50.75#ibcon#enter sib2, iclass 26, count 2 2006.162.07:51:50.75#ibcon#flushed, iclass 26, count 2 2006.162.07:51:50.75#ibcon#about to write, iclass 26, count 2 2006.162.07:51:50.75#ibcon#wrote, iclass 26, count 2 2006.162.07:51:50.75#ibcon#about to read 3, iclass 26, count 2 2006.162.07:51:50.79#ibcon#read 3, iclass 26, count 2 2006.162.07:51:50.79#ibcon#about to read 4, iclass 26, count 2 2006.162.07:51:50.79#ibcon#read 4, iclass 26, count 2 2006.162.07:51:50.79#ibcon#about to read 5, iclass 26, count 2 2006.162.07:51:50.79#ibcon#read 5, iclass 26, count 2 2006.162.07:51:50.79#ibcon#about to read 6, iclass 26, count 2 2006.162.07:51:50.79#ibcon#read 6, iclass 26, count 2 2006.162.07:51:50.79#ibcon#end of sib2, iclass 26, count 2 2006.162.07:51:50.79#ibcon#*after write, iclass 26, count 2 2006.162.07:51:50.79#ibcon#*before return 0, iclass 26, count 2 2006.162.07:51:50.79#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:51:50.79#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:51:50.79#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.162.07:51:50.79#ibcon#ireg 7 cls_cnt 0 2006.162.07:51:50.79#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:51:50.91#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:51:50.91#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:51:50.91#ibcon#enter wrdev, iclass 26, count 0 2006.162.07:51:50.91#ibcon#first serial, iclass 26, count 0 2006.162.07:51:50.91#ibcon#enter sib2, iclass 26, count 0 2006.162.07:51:50.91#ibcon#flushed, iclass 26, count 0 2006.162.07:51:50.91#ibcon#about to write, iclass 26, count 0 2006.162.07:51:50.91#ibcon#wrote, iclass 26, count 0 2006.162.07:51:50.91#ibcon#about to read 3, iclass 26, count 0 2006.162.07:51:50.93#ibcon#read 3, iclass 26, count 0 2006.162.07:51:50.93#ibcon#about to read 4, iclass 26, count 0 2006.162.07:51:50.93#ibcon#read 4, iclass 26, count 0 2006.162.07:51:50.93#ibcon#about to read 5, iclass 26, count 0 2006.162.07:51:50.93#ibcon#read 5, iclass 26, count 0 2006.162.07:51:50.93#ibcon#about to read 6, iclass 26, count 0 2006.162.07:51:50.93#ibcon#read 6, iclass 26, count 0 2006.162.07:51:50.93#ibcon#end of sib2, iclass 26, count 0 2006.162.07:51:50.93#ibcon#*mode == 0, iclass 26, count 0 2006.162.07:51:50.93#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.162.07:51:50.93#ibcon#[25=USB\r\n] 2006.162.07:51:50.93#ibcon#*before write, iclass 26, count 0 2006.162.07:51:50.93#ibcon#enter sib2, iclass 26, count 0 2006.162.07:51:50.93#ibcon#flushed, iclass 26, count 0 2006.162.07:51:50.93#ibcon#about to write, iclass 26, count 0 2006.162.07:51:50.93#ibcon#wrote, iclass 26, count 0 2006.162.07:51:50.93#ibcon#about to read 3, iclass 26, count 0 2006.162.07:51:50.96#ibcon#read 3, iclass 26, count 0 2006.162.07:51:50.96#ibcon#about to read 4, iclass 26, count 0 2006.162.07:51:50.96#ibcon#read 4, iclass 26, count 0 2006.162.07:51:50.96#ibcon#about to read 5, iclass 26, count 0 2006.162.07:51:50.96#ibcon#read 5, iclass 26, count 0 2006.162.07:51:50.96#ibcon#about to read 6, iclass 26, count 0 2006.162.07:51:50.96#ibcon#read 6, iclass 26, count 0 2006.162.07:51:50.96#ibcon#end of sib2, iclass 26, count 0 2006.162.07:51:50.96#ibcon#*after write, iclass 26, count 0 2006.162.07:51:50.96#ibcon#*before return 0, iclass 26, count 0 2006.162.07:51:50.96#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:51:50.96#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:51:50.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.162.07:51:50.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.162.07:51:50.96$vc4f8/valo=3,672.99 2006.162.07:51:50.96#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.162.07:51:50.96#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.162.07:51:50.96#ibcon#ireg 17 cls_cnt 0 2006.162.07:51:50.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:51:50.96#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:51:50.96#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:51:50.96#ibcon#enter wrdev, iclass 28, count 0 2006.162.07:51:50.96#ibcon#first serial, iclass 28, count 0 2006.162.07:51:50.96#ibcon#enter sib2, iclass 28, count 0 2006.162.07:51:50.96#ibcon#flushed, iclass 28, count 0 2006.162.07:51:50.96#ibcon#about to write, iclass 28, count 0 2006.162.07:51:50.96#ibcon#wrote, iclass 28, count 0 2006.162.07:51:50.96#ibcon#about to read 3, iclass 28, count 0 2006.162.07:51:50.98#ibcon#read 3, iclass 28, count 0 2006.162.07:51:50.98#ibcon#about to read 4, iclass 28, count 0 2006.162.07:51:50.98#ibcon#read 4, iclass 28, count 0 2006.162.07:51:50.98#ibcon#about to read 5, iclass 28, count 0 2006.162.07:51:50.98#ibcon#read 5, iclass 28, count 0 2006.162.07:51:50.98#ibcon#about to read 6, iclass 28, count 0 2006.162.07:51:50.98#ibcon#read 6, iclass 28, count 0 2006.162.07:51:50.98#ibcon#end of sib2, iclass 28, count 0 2006.162.07:51:50.98#ibcon#*mode == 0, iclass 28, count 0 2006.162.07:51:50.98#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.162.07:51:50.98#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.07:51:50.98#ibcon#*before write, iclass 28, count 0 2006.162.07:51:50.98#ibcon#enter sib2, iclass 28, count 0 2006.162.07:51:50.98#ibcon#flushed, iclass 28, count 0 2006.162.07:51:50.98#ibcon#about to write, iclass 28, count 0 2006.162.07:51:50.98#ibcon#wrote, iclass 28, count 0 2006.162.07:51:50.98#ibcon#about to read 3, iclass 28, count 0 2006.162.07:51:51.02#ibcon#read 3, iclass 28, count 0 2006.162.07:51:51.02#ibcon#about to read 4, iclass 28, count 0 2006.162.07:51:51.02#ibcon#read 4, iclass 28, count 0 2006.162.07:51:51.02#ibcon#about to read 5, iclass 28, count 0 2006.162.07:51:51.02#ibcon#read 5, iclass 28, count 0 2006.162.07:51:51.02#ibcon#about to read 6, iclass 28, count 0 2006.162.07:51:51.02#ibcon#read 6, iclass 28, count 0 2006.162.07:51:51.02#ibcon#end of sib2, iclass 28, count 0 2006.162.07:51:51.02#ibcon#*after write, iclass 28, count 0 2006.162.07:51:51.02#ibcon#*before return 0, iclass 28, count 0 2006.162.07:51:51.02#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:51:51.02#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:51:51.02#ibcon#about to clear, iclass 28 cls_cnt 0 2006.162.07:51:51.02#ibcon#cleared, iclass 28 cls_cnt 0 2006.162.07:51:51.02$vc4f8/va=3,6 2006.162.07:51:51.02#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.162.07:51:51.02#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.162.07:51:51.02#ibcon#ireg 11 cls_cnt 2 2006.162.07:51:51.02#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:51:51.08#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:51:51.08#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:51:51.08#ibcon#enter wrdev, iclass 30, count 2 2006.162.07:51:51.08#ibcon#first serial, iclass 30, count 2 2006.162.07:51:51.08#ibcon#enter sib2, iclass 30, count 2 2006.162.07:51:51.08#ibcon#flushed, iclass 30, count 2 2006.162.07:51:51.08#ibcon#about to write, iclass 30, count 2 2006.162.07:51:51.08#ibcon#wrote, iclass 30, count 2 2006.162.07:51:51.08#ibcon#about to read 3, iclass 30, count 2 2006.162.07:51:51.10#ibcon#read 3, iclass 30, count 2 2006.162.07:51:51.10#ibcon#about to read 4, iclass 30, count 2 2006.162.07:51:51.10#ibcon#read 4, iclass 30, count 2 2006.162.07:51:51.10#ibcon#about to read 5, iclass 30, count 2 2006.162.07:51:51.10#ibcon#read 5, iclass 30, count 2 2006.162.07:51:51.10#ibcon#about to read 6, iclass 30, count 2 2006.162.07:51:51.10#ibcon#read 6, iclass 30, count 2 2006.162.07:51:51.10#ibcon#end of sib2, iclass 30, count 2 2006.162.07:51:51.10#ibcon#*mode == 0, iclass 30, count 2 2006.162.07:51:51.10#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.162.07:51:51.10#ibcon#[25=AT03-06\r\n] 2006.162.07:51:51.10#ibcon#*before write, iclass 30, count 2 2006.162.07:51:51.10#ibcon#enter sib2, iclass 30, count 2 2006.162.07:51:51.10#ibcon#flushed, iclass 30, count 2 2006.162.07:51:51.10#ibcon#about to write, iclass 30, count 2 2006.162.07:51:51.10#ibcon#wrote, iclass 30, count 2 2006.162.07:51:51.10#ibcon#about to read 3, iclass 30, count 2 2006.162.07:51:51.13#ibcon#read 3, iclass 30, count 2 2006.162.07:51:51.13#ibcon#about to read 4, iclass 30, count 2 2006.162.07:51:51.13#ibcon#read 4, iclass 30, count 2 2006.162.07:51:51.13#ibcon#about to read 5, iclass 30, count 2 2006.162.07:51:51.13#ibcon#read 5, iclass 30, count 2 2006.162.07:51:51.13#ibcon#about to read 6, iclass 30, count 2 2006.162.07:51:51.13#ibcon#read 6, iclass 30, count 2 2006.162.07:51:51.13#ibcon#end of sib2, iclass 30, count 2 2006.162.07:51:51.13#ibcon#*after write, iclass 30, count 2 2006.162.07:51:51.13#ibcon#*before return 0, iclass 30, count 2 2006.162.07:51:51.13#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:51:51.13#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:51:51.13#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.162.07:51:51.13#ibcon#ireg 7 cls_cnt 0 2006.162.07:51:51.13#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:51:51.25#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:51:51.25#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:51:51.25#ibcon#enter wrdev, iclass 30, count 0 2006.162.07:51:51.25#ibcon#first serial, iclass 30, count 0 2006.162.07:51:51.25#ibcon#enter sib2, iclass 30, count 0 2006.162.07:51:51.25#ibcon#flushed, iclass 30, count 0 2006.162.07:51:51.25#ibcon#about to write, iclass 30, count 0 2006.162.07:51:51.25#ibcon#wrote, iclass 30, count 0 2006.162.07:51:51.25#ibcon#about to read 3, iclass 30, count 0 2006.162.07:51:51.27#ibcon#read 3, iclass 30, count 0 2006.162.07:51:51.27#ibcon#about to read 4, iclass 30, count 0 2006.162.07:51:51.27#ibcon#read 4, iclass 30, count 0 2006.162.07:51:51.27#ibcon#about to read 5, iclass 30, count 0 2006.162.07:51:51.27#ibcon#read 5, iclass 30, count 0 2006.162.07:51:51.27#ibcon#about to read 6, iclass 30, count 0 2006.162.07:51:51.27#ibcon#read 6, iclass 30, count 0 2006.162.07:51:51.27#ibcon#end of sib2, iclass 30, count 0 2006.162.07:51:51.27#ibcon#*mode == 0, iclass 30, count 0 2006.162.07:51:51.27#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.162.07:51:51.27#ibcon#[25=USB\r\n] 2006.162.07:51:51.27#ibcon#*before write, iclass 30, count 0 2006.162.07:51:51.27#ibcon#enter sib2, iclass 30, count 0 2006.162.07:51:51.27#ibcon#flushed, iclass 30, count 0 2006.162.07:51:51.27#ibcon#about to write, iclass 30, count 0 2006.162.07:51:51.27#ibcon#wrote, iclass 30, count 0 2006.162.07:51:51.27#ibcon#about to read 3, iclass 30, count 0 2006.162.07:51:51.30#ibcon#read 3, iclass 30, count 0 2006.162.07:51:51.30#ibcon#about to read 4, iclass 30, count 0 2006.162.07:51:51.30#ibcon#read 4, iclass 30, count 0 2006.162.07:51:51.30#ibcon#about to read 5, iclass 30, count 0 2006.162.07:51:51.30#ibcon#read 5, iclass 30, count 0 2006.162.07:51:51.30#ibcon#about to read 6, iclass 30, count 0 2006.162.07:51:51.30#ibcon#read 6, iclass 30, count 0 2006.162.07:51:51.30#ibcon#end of sib2, iclass 30, count 0 2006.162.07:51:51.30#ibcon#*after write, iclass 30, count 0 2006.162.07:51:51.30#ibcon#*before return 0, iclass 30, count 0 2006.162.07:51:51.30#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:51:51.30#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:51:51.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.162.07:51:51.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.162.07:51:51.30$vc4f8/valo=4,832.99 2006.162.07:51:51.30#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.162.07:51:51.30#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.162.07:51:51.30#ibcon#ireg 17 cls_cnt 0 2006.162.07:51:51.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:51:51.30#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:51:51.30#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:51:51.30#ibcon#enter wrdev, iclass 32, count 0 2006.162.07:51:51.30#ibcon#first serial, iclass 32, count 0 2006.162.07:51:51.30#ibcon#enter sib2, iclass 32, count 0 2006.162.07:51:51.30#ibcon#flushed, iclass 32, count 0 2006.162.07:51:51.30#ibcon#about to write, iclass 32, count 0 2006.162.07:51:51.30#ibcon#wrote, iclass 32, count 0 2006.162.07:51:51.30#ibcon#about to read 3, iclass 32, count 0 2006.162.07:51:51.32#ibcon#read 3, iclass 32, count 0 2006.162.07:51:51.32#ibcon#about to read 4, iclass 32, count 0 2006.162.07:51:51.32#ibcon#read 4, iclass 32, count 0 2006.162.07:51:51.32#ibcon#about to read 5, iclass 32, count 0 2006.162.07:51:51.32#ibcon#read 5, iclass 32, count 0 2006.162.07:51:51.32#ibcon#about to read 6, iclass 32, count 0 2006.162.07:51:51.32#ibcon#read 6, iclass 32, count 0 2006.162.07:51:51.32#ibcon#end of sib2, iclass 32, count 0 2006.162.07:51:51.32#ibcon#*mode == 0, iclass 32, count 0 2006.162.07:51:51.32#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.162.07:51:51.32#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.07:51:51.32#ibcon#*before write, iclass 32, count 0 2006.162.07:51:51.32#ibcon#enter sib2, iclass 32, count 0 2006.162.07:51:51.32#ibcon#flushed, iclass 32, count 0 2006.162.07:51:51.32#ibcon#about to write, iclass 32, count 0 2006.162.07:51:51.32#ibcon#wrote, iclass 32, count 0 2006.162.07:51:51.32#ibcon#about to read 3, iclass 32, count 0 2006.162.07:51:51.36#ibcon#read 3, iclass 32, count 0 2006.162.07:51:51.36#ibcon#about to read 4, iclass 32, count 0 2006.162.07:51:51.36#ibcon#read 4, iclass 32, count 0 2006.162.07:51:51.36#ibcon#about to read 5, iclass 32, count 0 2006.162.07:51:51.36#ibcon#read 5, iclass 32, count 0 2006.162.07:51:51.36#ibcon#about to read 6, iclass 32, count 0 2006.162.07:51:51.36#ibcon#read 6, iclass 32, count 0 2006.162.07:51:51.36#ibcon#end of sib2, iclass 32, count 0 2006.162.07:51:51.36#ibcon#*after write, iclass 32, count 0 2006.162.07:51:51.36#ibcon#*before return 0, iclass 32, count 0 2006.162.07:51:51.36#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:51:51.36#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:51:51.36#ibcon#about to clear, iclass 32 cls_cnt 0 2006.162.07:51:51.36#ibcon#cleared, iclass 32 cls_cnt 0 2006.162.07:51:51.36$vc4f8/va=4,7 2006.162.07:51:51.36#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.162.07:51:51.36#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.162.07:51:51.36#ibcon#ireg 11 cls_cnt 2 2006.162.07:51:51.36#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.162.07:51:51.42#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.162.07:51:51.42#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.162.07:51:51.42#ibcon#enter wrdev, iclass 34, count 2 2006.162.07:51:51.42#ibcon#first serial, iclass 34, count 2 2006.162.07:51:51.42#ibcon#enter sib2, iclass 34, count 2 2006.162.07:51:51.42#ibcon#flushed, iclass 34, count 2 2006.162.07:51:51.42#ibcon#about to write, iclass 34, count 2 2006.162.07:51:51.42#ibcon#wrote, iclass 34, count 2 2006.162.07:51:51.42#ibcon#about to read 3, iclass 34, count 2 2006.162.07:51:51.44#ibcon#read 3, iclass 34, count 2 2006.162.07:51:51.44#ibcon#about to read 4, iclass 34, count 2 2006.162.07:51:51.44#ibcon#read 4, iclass 34, count 2 2006.162.07:51:51.44#ibcon#about to read 5, iclass 34, count 2 2006.162.07:51:51.44#ibcon#read 5, iclass 34, count 2 2006.162.07:51:51.44#ibcon#about to read 6, iclass 34, count 2 2006.162.07:51:51.44#ibcon#read 6, iclass 34, count 2 2006.162.07:51:51.44#ibcon#end of sib2, iclass 34, count 2 2006.162.07:51:51.44#ibcon#*mode == 0, iclass 34, count 2 2006.162.07:51:51.44#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.162.07:51:51.44#ibcon#[25=AT04-07\r\n] 2006.162.07:51:51.44#ibcon#*before write, iclass 34, count 2 2006.162.07:51:51.44#ibcon#enter sib2, iclass 34, count 2 2006.162.07:51:51.44#ibcon#flushed, iclass 34, count 2 2006.162.07:51:51.44#ibcon#about to write, iclass 34, count 2 2006.162.07:51:51.44#ibcon#wrote, iclass 34, count 2 2006.162.07:51:51.44#ibcon#about to read 3, iclass 34, count 2 2006.162.07:51:51.47#ibcon#read 3, iclass 34, count 2 2006.162.07:51:51.47#ibcon#about to read 4, iclass 34, count 2 2006.162.07:51:51.47#ibcon#read 4, iclass 34, count 2 2006.162.07:51:51.47#ibcon#about to read 5, iclass 34, count 2 2006.162.07:51:51.47#ibcon#read 5, iclass 34, count 2 2006.162.07:51:51.47#ibcon#about to read 6, iclass 34, count 2 2006.162.07:51:51.47#ibcon#read 6, iclass 34, count 2 2006.162.07:51:51.47#ibcon#end of sib2, iclass 34, count 2 2006.162.07:51:51.47#ibcon#*after write, iclass 34, count 2 2006.162.07:51:51.47#ibcon#*before return 0, iclass 34, count 2 2006.162.07:51:51.47#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.162.07:51:51.47#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.162.07:51:51.47#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.162.07:51:51.47#ibcon#ireg 7 cls_cnt 0 2006.162.07:51:51.47#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.162.07:51:51.59#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.162.07:51:51.59#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.162.07:51:51.59#ibcon#enter wrdev, iclass 34, count 0 2006.162.07:51:51.59#ibcon#first serial, iclass 34, count 0 2006.162.07:51:51.59#ibcon#enter sib2, iclass 34, count 0 2006.162.07:51:51.59#ibcon#flushed, iclass 34, count 0 2006.162.07:51:51.59#ibcon#about to write, iclass 34, count 0 2006.162.07:51:51.59#ibcon#wrote, iclass 34, count 0 2006.162.07:51:51.59#ibcon#about to read 3, iclass 34, count 0 2006.162.07:51:51.61#ibcon#read 3, iclass 34, count 0 2006.162.07:51:51.61#ibcon#about to read 4, iclass 34, count 0 2006.162.07:51:51.61#ibcon#read 4, iclass 34, count 0 2006.162.07:51:51.61#ibcon#about to read 5, iclass 34, count 0 2006.162.07:51:51.61#ibcon#read 5, iclass 34, count 0 2006.162.07:51:51.61#ibcon#about to read 6, iclass 34, count 0 2006.162.07:51:51.61#ibcon#read 6, iclass 34, count 0 2006.162.07:51:51.61#ibcon#end of sib2, iclass 34, count 0 2006.162.07:51:51.61#ibcon#*mode == 0, iclass 34, count 0 2006.162.07:51:51.61#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.162.07:51:51.61#ibcon#[25=USB\r\n] 2006.162.07:51:51.61#ibcon#*before write, iclass 34, count 0 2006.162.07:51:51.61#ibcon#enter sib2, iclass 34, count 0 2006.162.07:51:51.61#ibcon#flushed, iclass 34, count 0 2006.162.07:51:51.61#ibcon#about to write, iclass 34, count 0 2006.162.07:51:51.61#ibcon#wrote, iclass 34, count 0 2006.162.07:51:51.61#ibcon#about to read 3, iclass 34, count 0 2006.162.07:51:51.64#ibcon#read 3, iclass 34, count 0 2006.162.07:51:51.64#ibcon#about to read 4, iclass 34, count 0 2006.162.07:51:51.64#ibcon#read 4, iclass 34, count 0 2006.162.07:51:51.64#ibcon#about to read 5, iclass 34, count 0 2006.162.07:51:51.64#ibcon#read 5, iclass 34, count 0 2006.162.07:51:51.64#ibcon#about to read 6, iclass 34, count 0 2006.162.07:51:51.64#ibcon#read 6, iclass 34, count 0 2006.162.07:51:51.64#ibcon#end of sib2, iclass 34, count 0 2006.162.07:51:51.64#ibcon#*after write, iclass 34, count 0 2006.162.07:51:51.64#ibcon#*before return 0, iclass 34, count 0 2006.162.07:51:51.64#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.162.07:51:51.64#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.162.07:51:51.64#ibcon#about to clear, iclass 34 cls_cnt 0 2006.162.07:51:51.64#ibcon#cleared, iclass 34 cls_cnt 0 2006.162.07:51:51.64$vc4f8/valo=5,652.99 2006.162.07:51:51.64#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.162.07:51:51.64#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.162.07:51:51.64#ibcon#ireg 17 cls_cnt 0 2006.162.07:51:51.64#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:51:51.64#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:51:51.64#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:51:51.64#ibcon#enter wrdev, iclass 36, count 0 2006.162.07:51:51.64#ibcon#first serial, iclass 36, count 0 2006.162.07:51:51.64#ibcon#enter sib2, iclass 36, count 0 2006.162.07:51:51.64#ibcon#flushed, iclass 36, count 0 2006.162.07:51:51.64#ibcon#about to write, iclass 36, count 0 2006.162.07:51:51.64#ibcon#wrote, iclass 36, count 0 2006.162.07:51:51.64#ibcon#about to read 3, iclass 36, count 0 2006.162.07:51:51.66#ibcon#read 3, iclass 36, count 0 2006.162.07:51:51.66#ibcon#about to read 4, iclass 36, count 0 2006.162.07:51:51.66#ibcon#read 4, iclass 36, count 0 2006.162.07:51:51.66#ibcon#about to read 5, iclass 36, count 0 2006.162.07:51:51.66#ibcon#read 5, iclass 36, count 0 2006.162.07:51:51.66#ibcon#about to read 6, iclass 36, count 0 2006.162.07:51:51.66#ibcon#read 6, iclass 36, count 0 2006.162.07:51:51.66#ibcon#end of sib2, iclass 36, count 0 2006.162.07:51:51.66#ibcon#*mode == 0, iclass 36, count 0 2006.162.07:51:51.66#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.162.07:51:51.66#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.07:51:51.66#ibcon#*before write, iclass 36, count 0 2006.162.07:51:51.66#ibcon#enter sib2, iclass 36, count 0 2006.162.07:51:51.66#ibcon#flushed, iclass 36, count 0 2006.162.07:51:51.66#ibcon#about to write, iclass 36, count 0 2006.162.07:51:51.66#ibcon#wrote, iclass 36, count 0 2006.162.07:51:51.66#ibcon#about to read 3, iclass 36, count 0 2006.162.07:51:51.70#ibcon#read 3, iclass 36, count 0 2006.162.07:51:51.70#ibcon#about to read 4, iclass 36, count 0 2006.162.07:51:51.70#ibcon#read 4, iclass 36, count 0 2006.162.07:51:51.70#ibcon#about to read 5, iclass 36, count 0 2006.162.07:51:51.70#ibcon#read 5, iclass 36, count 0 2006.162.07:51:51.70#ibcon#about to read 6, iclass 36, count 0 2006.162.07:51:51.70#ibcon#read 6, iclass 36, count 0 2006.162.07:51:51.70#ibcon#end of sib2, iclass 36, count 0 2006.162.07:51:51.70#ibcon#*after write, iclass 36, count 0 2006.162.07:51:51.70#ibcon#*before return 0, iclass 36, count 0 2006.162.07:51:51.70#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:51:51.70#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:51:51.70#ibcon#about to clear, iclass 36 cls_cnt 0 2006.162.07:51:51.70#ibcon#cleared, iclass 36 cls_cnt 0 2006.162.07:51:51.70$vc4f8/va=5,7 2006.162.07:51:51.70#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.162.07:51:51.70#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.162.07:51:51.70#ibcon#ireg 11 cls_cnt 2 2006.162.07:51:51.70#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:51:51.76#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:51:51.76#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:51:51.76#ibcon#enter wrdev, iclass 38, count 2 2006.162.07:51:51.76#ibcon#first serial, iclass 38, count 2 2006.162.07:51:51.76#ibcon#enter sib2, iclass 38, count 2 2006.162.07:51:51.76#ibcon#flushed, iclass 38, count 2 2006.162.07:51:51.76#ibcon#about to write, iclass 38, count 2 2006.162.07:51:51.76#ibcon#wrote, iclass 38, count 2 2006.162.07:51:51.76#ibcon#about to read 3, iclass 38, count 2 2006.162.07:51:51.78#ibcon#read 3, iclass 38, count 2 2006.162.07:51:51.78#ibcon#about to read 4, iclass 38, count 2 2006.162.07:51:51.78#ibcon#read 4, iclass 38, count 2 2006.162.07:51:51.78#ibcon#about to read 5, iclass 38, count 2 2006.162.07:51:51.78#ibcon#read 5, iclass 38, count 2 2006.162.07:51:51.78#ibcon#about to read 6, iclass 38, count 2 2006.162.07:51:51.78#ibcon#read 6, iclass 38, count 2 2006.162.07:51:51.78#ibcon#end of sib2, iclass 38, count 2 2006.162.07:51:51.78#ibcon#*mode == 0, iclass 38, count 2 2006.162.07:51:51.78#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.162.07:51:51.78#ibcon#[25=AT05-07\r\n] 2006.162.07:51:51.78#ibcon#*before write, iclass 38, count 2 2006.162.07:51:51.78#ibcon#enter sib2, iclass 38, count 2 2006.162.07:51:51.78#ibcon#flushed, iclass 38, count 2 2006.162.07:51:51.78#ibcon#about to write, iclass 38, count 2 2006.162.07:51:51.78#ibcon#wrote, iclass 38, count 2 2006.162.07:51:51.78#ibcon#about to read 3, iclass 38, count 2 2006.162.07:51:51.81#ibcon#read 3, iclass 38, count 2 2006.162.07:51:51.81#ibcon#about to read 4, iclass 38, count 2 2006.162.07:51:51.81#ibcon#read 4, iclass 38, count 2 2006.162.07:51:51.81#ibcon#about to read 5, iclass 38, count 2 2006.162.07:51:51.81#ibcon#read 5, iclass 38, count 2 2006.162.07:51:51.81#ibcon#about to read 6, iclass 38, count 2 2006.162.07:51:51.81#ibcon#read 6, iclass 38, count 2 2006.162.07:51:51.81#ibcon#end of sib2, iclass 38, count 2 2006.162.07:51:51.81#ibcon#*after write, iclass 38, count 2 2006.162.07:51:51.81#ibcon#*before return 0, iclass 38, count 2 2006.162.07:51:51.81#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:51:51.81#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:51:51.81#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.162.07:51:51.81#ibcon#ireg 7 cls_cnt 0 2006.162.07:51:51.81#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:51:51.93#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:51:51.93#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:51:51.93#ibcon#enter wrdev, iclass 38, count 0 2006.162.07:51:51.93#ibcon#first serial, iclass 38, count 0 2006.162.07:51:51.93#ibcon#enter sib2, iclass 38, count 0 2006.162.07:51:51.93#ibcon#flushed, iclass 38, count 0 2006.162.07:51:51.93#ibcon#about to write, iclass 38, count 0 2006.162.07:51:51.93#ibcon#wrote, iclass 38, count 0 2006.162.07:51:51.93#ibcon#about to read 3, iclass 38, count 0 2006.162.07:51:51.95#ibcon#read 3, iclass 38, count 0 2006.162.07:51:51.95#ibcon#about to read 4, iclass 38, count 0 2006.162.07:51:51.95#ibcon#read 4, iclass 38, count 0 2006.162.07:51:51.95#ibcon#about to read 5, iclass 38, count 0 2006.162.07:51:51.95#ibcon#read 5, iclass 38, count 0 2006.162.07:51:51.95#ibcon#about to read 6, iclass 38, count 0 2006.162.07:51:51.95#ibcon#read 6, iclass 38, count 0 2006.162.07:51:51.95#ibcon#end of sib2, iclass 38, count 0 2006.162.07:51:51.95#ibcon#*mode == 0, iclass 38, count 0 2006.162.07:51:51.95#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.162.07:51:51.95#ibcon#[25=USB\r\n] 2006.162.07:51:51.95#ibcon#*before write, iclass 38, count 0 2006.162.07:51:51.95#ibcon#enter sib2, iclass 38, count 0 2006.162.07:51:51.95#ibcon#flushed, iclass 38, count 0 2006.162.07:51:51.95#ibcon#about to write, iclass 38, count 0 2006.162.07:51:51.95#ibcon#wrote, iclass 38, count 0 2006.162.07:51:51.95#ibcon#about to read 3, iclass 38, count 0 2006.162.07:51:51.98#ibcon#read 3, iclass 38, count 0 2006.162.07:51:51.98#ibcon#about to read 4, iclass 38, count 0 2006.162.07:51:51.98#ibcon#read 4, iclass 38, count 0 2006.162.07:51:51.98#ibcon#about to read 5, iclass 38, count 0 2006.162.07:51:51.98#ibcon#read 5, iclass 38, count 0 2006.162.07:51:51.98#ibcon#about to read 6, iclass 38, count 0 2006.162.07:51:51.98#ibcon#read 6, iclass 38, count 0 2006.162.07:51:51.98#ibcon#end of sib2, iclass 38, count 0 2006.162.07:51:51.98#ibcon#*after write, iclass 38, count 0 2006.162.07:51:51.98#ibcon#*before return 0, iclass 38, count 0 2006.162.07:51:51.98#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:51:51.98#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:51:51.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.162.07:51:51.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.162.07:51:51.98$vc4f8/valo=6,772.99 2006.162.07:51:51.98#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.162.07:51:51.98#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.162.07:51:51.98#ibcon#ireg 17 cls_cnt 0 2006.162.07:51:51.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:51:51.98#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:51:51.98#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:51:51.98#ibcon#enter wrdev, iclass 40, count 0 2006.162.07:51:51.98#ibcon#first serial, iclass 40, count 0 2006.162.07:51:51.98#ibcon#enter sib2, iclass 40, count 0 2006.162.07:51:51.98#ibcon#flushed, iclass 40, count 0 2006.162.07:51:51.98#ibcon#about to write, iclass 40, count 0 2006.162.07:51:51.98#ibcon#wrote, iclass 40, count 0 2006.162.07:51:51.98#ibcon#about to read 3, iclass 40, count 0 2006.162.07:51:52.00#ibcon#read 3, iclass 40, count 0 2006.162.07:51:52.00#ibcon#about to read 4, iclass 40, count 0 2006.162.07:51:52.00#ibcon#read 4, iclass 40, count 0 2006.162.07:51:52.00#ibcon#about to read 5, iclass 40, count 0 2006.162.07:51:52.00#ibcon#read 5, iclass 40, count 0 2006.162.07:51:52.00#ibcon#about to read 6, iclass 40, count 0 2006.162.07:51:52.00#ibcon#read 6, iclass 40, count 0 2006.162.07:51:52.00#ibcon#end of sib2, iclass 40, count 0 2006.162.07:51:52.00#ibcon#*mode == 0, iclass 40, count 0 2006.162.07:51:52.00#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.162.07:51:52.00#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.07:51:52.00#ibcon#*before write, iclass 40, count 0 2006.162.07:51:52.00#ibcon#enter sib2, iclass 40, count 0 2006.162.07:51:52.00#ibcon#flushed, iclass 40, count 0 2006.162.07:51:52.00#ibcon#about to write, iclass 40, count 0 2006.162.07:51:52.00#ibcon#wrote, iclass 40, count 0 2006.162.07:51:52.00#ibcon#about to read 3, iclass 40, count 0 2006.162.07:51:52.04#ibcon#read 3, iclass 40, count 0 2006.162.07:51:52.04#ibcon#about to read 4, iclass 40, count 0 2006.162.07:51:52.04#ibcon#read 4, iclass 40, count 0 2006.162.07:51:52.04#ibcon#about to read 5, iclass 40, count 0 2006.162.07:51:52.04#ibcon#read 5, iclass 40, count 0 2006.162.07:51:52.04#ibcon#about to read 6, iclass 40, count 0 2006.162.07:51:52.04#ibcon#read 6, iclass 40, count 0 2006.162.07:51:52.04#ibcon#end of sib2, iclass 40, count 0 2006.162.07:51:52.04#ibcon#*after write, iclass 40, count 0 2006.162.07:51:52.04#ibcon#*before return 0, iclass 40, count 0 2006.162.07:51:52.04#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:51:52.04#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:51:52.04#ibcon#about to clear, iclass 40 cls_cnt 0 2006.162.07:51:52.04#ibcon#cleared, iclass 40 cls_cnt 0 2006.162.07:51:52.04$vc4f8/va=6,6 2006.162.07:51:52.04#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.162.07:51:52.04#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.162.07:51:52.04#ibcon#ireg 11 cls_cnt 2 2006.162.07:51:52.04#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:51:52.10#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:51:52.10#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:51:52.10#ibcon#enter wrdev, iclass 4, count 2 2006.162.07:51:52.10#ibcon#first serial, iclass 4, count 2 2006.162.07:51:52.10#ibcon#enter sib2, iclass 4, count 2 2006.162.07:51:52.10#ibcon#flushed, iclass 4, count 2 2006.162.07:51:52.10#ibcon#about to write, iclass 4, count 2 2006.162.07:51:52.10#ibcon#wrote, iclass 4, count 2 2006.162.07:51:52.10#ibcon#about to read 3, iclass 4, count 2 2006.162.07:51:52.12#ibcon#read 3, iclass 4, count 2 2006.162.07:51:52.12#ibcon#about to read 4, iclass 4, count 2 2006.162.07:51:52.12#ibcon#read 4, iclass 4, count 2 2006.162.07:51:52.12#ibcon#about to read 5, iclass 4, count 2 2006.162.07:51:52.12#ibcon#read 5, iclass 4, count 2 2006.162.07:51:52.12#ibcon#about to read 6, iclass 4, count 2 2006.162.07:51:52.12#ibcon#read 6, iclass 4, count 2 2006.162.07:51:52.12#ibcon#end of sib2, iclass 4, count 2 2006.162.07:51:52.12#ibcon#*mode == 0, iclass 4, count 2 2006.162.07:51:52.12#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.162.07:51:52.12#ibcon#[25=AT06-06\r\n] 2006.162.07:51:52.12#ibcon#*before write, iclass 4, count 2 2006.162.07:51:52.12#ibcon#enter sib2, iclass 4, count 2 2006.162.07:51:52.12#ibcon#flushed, iclass 4, count 2 2006.162.07:51:52.12#ibcon#about to write, iclass 4, count 2 2006.162.07:51:52.12#ibcon#wrote, iclass 4, count 2 2006.162.07:51:52.12#ibcon#about to read 3, iclass 4, count 2 2006.162.07:51:52.15#ibcon#read 3, iclass 4, count 2 2006.162.07:51:52.15#ibcon#about to read 4, iclass 4, count 2 2006.162.07:51:52.15#ibcon#read 4, iclass 4, count 2 2006.162.07:51:52.15#ibcon#about to read 5, iclass 4, count 2 2006.162.07:51:52.15#ibcon#read 5, iclass 4, count 2 2006.162.07:51:52.15#ibcon#about to read 6, iclass 4, count 2 2006.162.07:51:52.15#ibcon#read 6, iclass 4, count 2 2006.162.07:51:52.15#ibcon#end of sib2, iclass 4, count 2 2006.162.07:51:52.15#ibcon#*after write, iclass 4, count 2 2006.162.07:51:52.15#ibcon#*before return 0, iclass 4, count 2 2006.162.07:51:52.15#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:51:52.15#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:51:52.15#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.162.07:51:52.15#ibcon#ireg 7 cls_cnt 0 2006.162.07:51:52.15#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:51:52.27#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:51:52.27#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:51:52.27#ibcon#enter wrdev, iclass 4, count 0 2006.162.07:51:52.27#ibcon#first serial, iclass 4, count 0 2006.162.07:51:52.27#ibcon#enter sib2, iclass 4, count 0 2006.162.07:51:52.27#ibcon#flushed, iclass 4, count 0 2006.162.07:51:52.27#ibcon#about to write, iclass 4, count 0 2006.162.07:51:52.27#ibcon#wrote, iclass 4, count 0 2006.162.07:51:52.27#ibcon#about to read 3, iclass 4, count 0 2006.162.07:51:52.29#ibcon#read 3, iclass 4, count 0 2006.162.07:51:52.29#ibcon#about to read 4, iclass 4, count 0 2006.162.07:51:52.29#ibcon#read 4, iclass 4, count 0 2006.162.07:51:52.29#ibcon#about to read 5, iclass 4, count 0 2006.162.07:51:52.29#ibcon#read 5, iclass 4, count 0 2006.162.07:51:52.29#ibcon#about to read 6, iclass 4, count 0 2006.162.07:51:52.29#ibcon#read 6, iclass 4, count 0 2006.162.07:51:52.29#ibcon#end of sib2, iclass 4, count 0 2006.162.07:51:52.29#ibcon#*mode == 0, iclass 4, count 0 2006.162.07:51:52.29#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.162.07:51:52.29#ibcon#[25=USB\r\n] 2006.162.07:51:52.29#ibcon#*before write, iclass 4, count 0 2006.162.07:51:52.29#ibcon#enter sib2, iclass 4, count 0 2006.162.07:51:52.29#ibcon#flushed, iclass 4, count 0 2006.162.07:51:52.29#ibcon#about to write, iclass 4, count 0 2006.162.07:51:52.29#ibcon#wrote, iclass 4, count 0 2006.162.07:51:52.29#ibcon#about to read 3, iclass 4, count 0 2006.162.07:51:52.32#ibcon#read 3, iclass 4, count 0 2006.162.07:51:52.32#ibcon#about to read 4, iclass 4, count 0 2006.162.07:51:52.32#ibcon#read 4, iclass 4, count 0 2006.162.07:51:52.32#ibcon#about to read 5, iclass 4, count 0 2006.162.07:51:52.32#ibcon#read 5, iclass 4, count 0 2006.162.07:51:52.32#ibcon#about to read 6, iclass 4, count 0 2006.162.07:51:52.32#ibcon#read 6, iclass 4, count 0 2006.162.07:51:52.32#ibcon#end of sib2, iclass 4, count 0 2006.162.07:51:52.32#ibcon#*after write, iclass 4, count 0 2006.162.07:51:52.32#ibcon#*before return 0, iclass 4, count 0 2006.162.07:51:52.32#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:51:52.32#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:51:52.32#ibcon#about to clear, iclass 4 cls_cnt 0 2006.162.07:51:52.32#ibcon#cleared, iclass 4 cls_cnt 0 2006.162.07:51:52.32$vc4f8/valo=7,832.99 2006.162.07:51:52.32#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.162.07:51:52.32#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.162.07:51:52.32#ibcon#ireg 17 cls_cnt 0 2006.162.07:51:52.32#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:51:52.32#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:51:52.32#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:51:52.32#ibcon#enter wrdev, iclass 6, count 0 2006.162.07:51:52.32#ibcon#first serial, iclass 6, count 0 2006.162.07:51:52.32#ibcon#enter sib2, iclass 6, count 0 2006.162.07:51:52.32#ibcon#flushed, iclass 6, count 0 2006.162.07:51:52.32#ibcon#about to write, iclass 6, count 0 2006.162.07:51:52.32#ibcon#wrote, iclass 6, count 0 2006.162.07:51:52.32#ibcon#about to read 3, iclass 6, count 0 2006.162.07:51:52.34#ibcon#read 3, iclass 6, count 0 2006.162.07:51:52.34#ibcon#about to read 4, iclass 6, count 0 2006.162.07:51:52.34#ibcon#read 4, iclass 6, count 0 2006.162.07:51:52.34#ibcon#about to read 5, iclass 6, count 0 2006.162.07:51:52.34#ibcon#read 5, iclass 6, count 0 2006.162.07:51:52.34#ibcon#about to read 6, iclass 6, count 0 2006.162.07:51:52.34#ibcon#read 6, iclass 6, count 0 2006.162.07:51:52.34#ibcon#end of sib2, iclass 6, count 0 2006.162.07:51:52.34#ibcon#*mode == 0, iclass 6, count 0 2006.162.07:51:52.34#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.162.07:51:52.34#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.07:51:52.34#ibcon#*before write, iclass 6, count 0 2006.162.07:51:52.34#ibcon#enter sib2, iclass 6, count 0 2006.162.07:51:52.34#ibcon#flushed, iclass 6, count 0 2006.162.07:51:52.34#ibcon#about to write, iclass 6, count 0 2006.162.07:51:52.34#ibcon#wrote, iclass 6, count 0 2006.162.07:51:52.34#ibcon#about to read 3, iclass 6, count 0 2006.162.07:51:52.38#ibcon#read 3, iclass 6, count 0 2006.162.07:51:52.38#ibcon#about to read 4, iclass 6, count 0 2006.162.07:51:52.38#ibcon#read 4, iclass 6, count 0 2006.162.07:51:52.38#ibcon#about to read 5, iclass 6, count 0 2006.162.07:51:52.38#ibcon#read 5, iclass 6, count 0 2006.162.07:51:52.38#ibcon#about to read 6, iclass 6, count 0 2006.162.07:51:52.38#ibcon#read 6, iclass 6, count 0 2006.162.07:51:52.38#ibcon#end of sib2, iclass 6, count 0 2006.162.07:51:52.38#ibcon#*after write, iclass 6, count 0 2006.162.07:51:52.38#ibcon#*before return 0, iclass 6, count 0 2006.162.07:51:52.38#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:51:52.38#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:51:52.38#ibcon#about to clear, iclass 6 cls_cnt 0 2006.162.07:51:52.38#ibcon#cleared, iclass 6 cls_cnt 0 2006.162.07:51:52.38$vc4f8/va=7,6 2006.162.07:51:52.38#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.162.07:51:52.38#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.162.07:51:52.38#ibcon#ireg 11 cls_cnt 2 2006.162.07:51:52.38#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:51:52.44#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:51:52.44#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:51:52.44#ibcon#enter wrdev, iclass 10, count 2 2006.162.07:51:52.44#ibcon#first serial, iclass 10, count 2 2006.162.07:51:52.44#ibcon#enter sib2, iclass 10, count 2 2006.162.07:51:52.44#ibcon#flushed, iclass 10, count 2 2006.162.07:51:52.44#ibcon#about to write, iclass 10, count 2 2006.162.07:51:52.44#ibcon#wrote, iclass 10, count 2 2006.162.07:51:52.44#ibcon#about to read 3, iclass 10, count 2 2006.162.07:51:52.46#ibcon#read 3, iclass 10, count 2 2006.162.07:51:52.46#ibcon#about to read 4, iclass 10, count 2 2006.162.07:51:52.46#ibcon#read 4, iclass 10, count 2 2006.162.07:51:52.46#ibcon#about to read 5, iclass 10, count 2 2006.162.07:51:52.46#ibcon#read 5, iclass 10, count 2 2006.162.07:51:52.46#ibcon#about to read 6, iclass 10, count 2 2006.162.07:51:52.46#ibcon#read 6, iclass 10, count 2 2006.162.07:51:52.46#ibcon#end of sib2, iclass 10, count 2 2006.162.07:51:52.46#ibcon#*mode == 0, iclass 10, count 2 2006.162.07:51:52.46#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.162.07:51:52.46#ibcon#[25=AT07-06\r\n] 2006.162.07:51:52.46#ibcon#*before write, iclass 10, count 2 2006.162.07:51:52.46#ibcon#enter sib2, iclass 10, count 2 2006.162.07:51:52.46#ibcon#flushed, iclass 10, count 2 2006.162.07:51:52.46#ibcon#about to write, iclass 10, count 2 2006.162.07:51:52.46#ibcon#wrote, iclass 10, count 2 2006.162.07:51:52.46#ibcon#about to read 3, iclass 10, count 2 2006.162.07:51:52.49#ibcon#read 3, iclass 10, count 2 2006.162.07:51:52.49#ibcon#about to read 4, iclass 10, count 2 2006.162.07:51:52.49#ibcon#read 4, iclass 10, count 2 2006.162.07:51:52.49#ibcon#about to read 5, iclass 10, count 2 2006.162.07:51:52.49#ibcon#read 5, iclass 10, count 2 2006.162.07:51:52.49#ibcon#about to read 6, iclass 10, count 2 2006.162.07:51:52.49#ibcon#read 6, iclass 10, count 2 2006.162.07:51:52.49#ibcon#end of sib2, iclass 10, count 2 2006.162.07:51:52.49#ibcon#*after write, iclass 10, count 2 2006.162.07:51:52.49#ibcon#*before return 0, iclass 10, count 2 2006.162.07:51:52.49#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:51:52.49#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.162.07:51:52.49#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.162.07:51:52.49#ibcon#ireg 7 cls_cnt 0 2006.162.07:51:52.49#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:51:52.61#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:51:52.61#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:51:52.61#ibcon#enter wrdev, iclass 10, count 0 2006.162.07:51:52.61#ibcon#first serial, iclass 10, count 0 2006.162.07:51:52.61#ibcon#enter sib2, iclass 10, count 0 2006.162.07:51:52.61#ibcon#flushed, iclass 10, count 0 2006.162.07:51:52.61#ibcon#about to write, iclass 10, count 0 2006.162.07:51:52.61#ibcon#wrote, iclass 10, count 0 2006.162.07:51:52.61#ibcon#about to read 3, iclass 10, count 0 2006.162.07:51:52.63#ibcon#read 3, iclass 10, count 0 2006.162.07:51:52.63#ibcon#about to read 4, iclass 10, count 0 2006.162.07:51:52.63#ibcon#read 4, iclass 10, count 0 2006.162.07:51:52.63#ibcon#about to read 5, iclass 10, count 0 2006.162.07:51:52.63#ibcon#read 5, iclass 10, count 0 2006.162.07:51:52.63#ibcon#about to read 6, iclass 10, count 0 2006.162.07:51:52.63#ibcon#read 6, iclass 10, count 0 2006.162.07:51:52.63#ibcon#end of sib2, iclass 10, count 0 2006.162.07:51:52.63#ibcon#*mode == 0, iclass 10, count 0 2006.162.07:51:52.63#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.162.07:51:52.63#ibcon#[25=USB\r\n] 2006.162.07:51:52.63#ibcon#*before write, iclass 10, count 0 2006.162.07:51:52.63#ibcon#enter sib2, iclass 10, count 0 2006.162.07:51:52.63#ibcon#flushed, iclass 10, count 0 2006.162.07:51:52.63#ibcon#about to write, iclass 10, count 0 2006.162.07:51:52.63#ibcon#wrote, iclass 10, count 0 2006.162.07:51:52.63#ibcon#about to read 3, iclass 10, count 0 2006.162.07:51:52.66#ibcon#read 3, iclass 10, count 0 2006.162.07:51:52.66#ibcon#about to read 4, iclass 10, count 0 2006.162.07:51:52.66#ibcon#read 4, iclass 10, count 0 2006.162.07:51:52.66#ibcon#about to read 5, iclass 10, count 0 2006.162.07:51:52.66#ibcon#read 5, iclass 10, count 0 2006.162.07:51:52.66#ibcon#about to read 6, iclass 10, count 0 2006.162.07:51:52.66#ibcon#read 6, iclass 10, count 0 2006.162.07:51:52.66#ibcon#end of sib2, iclass 10, count 0 2006.162.07:51:52.66#ibcon#*after write, iclass 10, count 0 2006.162.07:51:52.66#ibcon#*before return 0, iclass 10, count 0 2006.162.07:51:52.66#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:51:52.66#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.162.07:51:52.66#ibcon#about to clear, iclass 10 cls_cnt 0 2006.162.07:51:52.66#ibcon#cleared, iclass 10 cls_cnt 0 2006.162.07:51:52.66$vc4f8/valo=8,852.99 2006.162.07:51:52.66#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.162.07:51:52.66#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.162.07:51:52.66#ibcon#ireg 17 cls_cnt 0 2006.162.07:51:52.66#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:51:52.66#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:51:52.66#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:51:52.66#ibcon#enter wrdev, iclass 12, count 0 2006.162.07:51:52.66#ibcon#first serial, iclass 12, count 0 2006.162.07:51:52.66#ibcon#enter sib2, iclass 12, count 0 2006.162.07:51:52.66#ibcon#flushed, iclass 12, count 0 2006.162.07:51:52.66#ibcon#about to write, iclass 12, count 0 2006.162.07:51:52.66#ibcon#wrote, iclass 12, count 0 2006.162.07:51:52.66#ibcon#about to read 3, iclass 12, count 0 2006.162.07:51:52.68#ibcon#read 3, iclass 12, count 0 2006.162.07:51:52.68#ibcon#about to read 4, iclass 12, count 0 2006.162.07:51:52.68#ibcon#read 4, iclass 12, count 0 2006.162.07:51:52.68#ibcon#about to read 5, iclass 12, count 0 2006.162.07:51:52.68#ibcon#read 5, iclass 12, count 0 2006.162.07:51:52.68#ibcon#about to read 6, iclass 12, count 0 2006.162.07:51:52.68#ibcon#read 6, iclass 12, count 0 2006.162.07:51:52.68#ibcon#end of sib2, iclass 12, count 0 2006.162.07:51:52.68#ibcon#*mode == 0, iclass 12, count 0 2006.162.07:51:52.68#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.162.07:51:52.68#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.07:51:52.68#ibcon#*before write, iclass 12, count 0 2006.162.07:51:52.68#ibcon#enter sib2, iclass 12, count 0 2006.162.07:51:52.68#ibcon#flushed, iclass 12, count 0 2006.162.07:51:52.68#ibcon#about to write, iclass 12, count 0 2006.162.07:51:52.68#ibcon#wrote, iclass 12, count 0 2006.162.07:51:52.68#ibcon#about to read 3, iclass 12, count 0 2006.162.07:51:52.72#ibcon#read 3, iclass 12, count 0 2006.162.07:51:52.72#ibcon#about to read 4, iclass 12, count 0 2006.162.07:51:52.72#ibcon#read 4, iclass 12, count 0 2006.162.07:51:52.72#ibcon#about to read 5, iclass 12, count 0 2006.162.07:51:52.72#ibcon#read 5, iclass 12, count 0 2006.162.07:51:52.72#ibcon#about to read 6, iclass 12, count 0 2006.162.07:51:52.72#ibcon#read 6, iclass 12, count 0 2006.162.07:51:52.72#ibcon#end of sib2, iclass 12, count 0 2006.162.07:51:52.72#ibcon#*after write, iclass 12, count 0 2006.162.07:51:52.72#ibcon#*before return 0, iclass 12, count 0 2006.162.07:51:52.72#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:51:52.72#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.162.07:51:52.72#ibcon#about to clear, iclass 12 cls_cnt 0 2006.162.07:51:52.72#ibcon#cleared, iclass 12 cls_cnt 0 2006.162.07:51:52.72$vc4f8/va=8,7 2006.162.07:51:52.72#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.162.07:51:52.72#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.162.07:51:52.72#ibcon#ireg 11 cls_cnt 2 2006.162.07:51:52.72#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:51:52.78#abcon#<5=/03 1.7 3.4 17.871001007.2\r\n> 2006.162.07:51:52.78#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:51:52.78#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:51:52.78#ibcon#enter wrdev, iclass 14, count 2 2006.162.07:51:52.78#ibcon#first serial, iclass 14, count 2 2006.162.07:51:52.78#ibcon#enter sib2, iclass 14, count 2 2006.162.07:51:52.78#ibcon#flushed, iclass 14, count 2 2006.162.07:51:52.78#ibcon#about to write, iclass 14, count 2 2006.162.07:51:52.78#ibcon#wrote, iclass 14, count 2 2006.162.07:51:52.78#ibcon#about to read 3, iclass 14, count 2 2006.162.07:51:52.80#ibcon#read 3, iclass 14, count 2 2006.162.07:51:52.80#ibcon#about to read 4, iclass 14, count 2 2006.162.07:51:52.80#ibcon#read 4, iclass 14, count 2 2006.162.07:51:52.80#ibcon#about to read 5, iclass 14, count 2 2006.162.07:51:52.80#ibcon#read 5, iclass 14, count 2 2006.162.07:51:52.80#ibcon#about to read 6, iclass 14, count 2 2006.162.07:51:52.80#ibcon#read 6, iclass 14, count 2 2006.162.07:51:52.80#ibcon#end of sib2, iclass 14, count 2 2006.162.07:51:52.80#ibcon#*mode == 0, iclass 14, count 2 2006.162.07:51:52.80#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.162.07:51:52.80#ibcon#[25=AT08-07\r\n] 2006.162.07:51:52.80#ibcon#*before write, iclass 14, count 2 2006.162.07:51:52.80#ibcon#enter sib2, iclass 14, count 2 2006.162.07:51:52.80#ibcon#flushed, iclass 14, count 2 2006.162.07:51:52.80#ibcon#about to write, iclass 14, count 2 2006.162.07:51:52.80#ibcon#wrote, iclass 14, count 2 2006.162.07:51:52.80#ibcon#about to read 3, iclass 14, count 2 2006.162.07:51:52.80#abcon#{5=INTERFACE CLEAR} 2006.162.07:51:52.83#ibcon#read 3, iclass 14, count 2 2006.162.07:51:52.83#ibcon#about to read 4, iclass 14, count 2 2006.162.07:51:52.83#ibcon#read 4, iclass 14, count 2 2006.162.07:51:52.83#ibcon#about to read 5, iclass 14, count 2 2006.162.07:51:52.83#ibcon#read 5, iclass 14, count 2 2006.162.07:51:52.83#ibcon#about to read 6, iclass 14, count 2 2006.162.07:51:52.83#ibcon#read 6, iclass 14, count 2 2006.162.07:51:52.83#ibcon#end of sib2, iclass 14, count 2 2006.162.07:51:52.83#ibcon#*after write, iclass 14, count 2 2006.162.07:51:52.83#ibcon#*before return 0, iclass 14, count 2 2006.162.07:51:52.83#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:51:52.83#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.162.07:51:52.83#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.162.07:51:52.83#ibcon#ireg 7 cls_cnt 0 2006.162.07:51:52.83#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:51:52.86#abcon#[5=S1D000X0/0*\r\n] 2006.162.07:51:52.95#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:51:52.95#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:51:52.95#ibcon#enter wrdev, iclass 14, count 0 2006.162.07:51:52.95#ibcon#first serial, iclass 14, count 0 2006.162.07:51:52.95#ibcon#enter sib2, iclass 14, count 0 2006.162.07:51:52.95#ibcon#flushed, iclass 14, count 0 2006.162.07:51:52.95#ibcon#about to write, iclass 14, count 0 2006.162.07:51:52.95#ibcon#wrote, iclass 14, count 0 2006.162.07:51:52.95#ibcon#about to read 3, iclass 14, count 0 2006.162.07:51:52.98#ibcon#read 3, iclass 14, count 0 2006.162.07:51:52.98#ibcon#about to read 4, iclass 14, count 0 2006.162.07:51:52.98#ibcon#read 4, iclass 14, count 0 2006.162.07:51:52.98#ibcon#about to read 5, iclass 14, count 0 2006.162.07:51:52.98#ibcon#read 5, iclass 14, count 0 2006.162.07:51:52.98#ibcon#about to read 6, iclass 14, count 0 2006.162.07:51:52.98#ibcon#read 6, iclass 14, count 0 2006.162.07:51:52.98#ibcon#end of sib2, iclass 14, count 0 2006.162.07:51:52.98#ibcon#*mode == 0, iclass 14, count 0 2006.162.07:51:52.98#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.07:51:52.98#ibcon#[25=USB\r\n] 2006.162.07:51:52.98#ibcon#*before write, iclass 14, count 0 2006.162.07:51:52.98#ibcon#enter sib2, iclass 14, count 0 2006.162.07:51:52.98#ibcon#flushed, iclass 14, count 0 2006.162.07:51:52.98#ibcon#about to write, iclass 14, count 0 2006.162.07:51:52.98#ibcon#wrote, iclass 14, count 0 2006.162.07:51:52.98#ibcon#about to read 3, iclass 14, count 0 2006.162.07:51:53.02#ibcon#read 3, iclass 14, count 0 2006.162.07:51:53.02#ibcon#about to read 4, iclass 14, count 0 2006.162.07:51:53.02#ibcon#read 4, iclass 14, count 0 2006.162.07:51:53.02#ibcon#about to read 5, iclass 14, count 0 2006.162.07:51:53.02#ibcon#read 5, iclass 14, count 0 2006.162.07:51:53.02#ibcon#about to read 6, iclass 14, count 0 2006.162.07:51:53.02#ibcon#read 6, iclass 14, count 0 2006.162.07:51:53.02#ibcon#end of sib2, iclass 14, count 0 2006.162.07:51:53.02#ibcon#*after write, iclass 14, count 0 2006.162.07:51:53.02#ibcon#*before return 0, iclass 14, count 0 2006.162.07:51:53.02#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:51:53.02#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.162.07:51:53.02#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.07:51:53.02#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.07:51:53.02$vc4f8/vblo=1,632.99 2006.162.07:51:53.02#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.162.07:51:53.02#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.162.07:51:53.02#ibcon#ireg 17 cls_cnt 0 2006.162.07:51:53.02#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:51:53.02#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:51:53.02#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:51:53.02#ibcon#enter wrdev, iclass 20, count 0 2006.162.07:51:53.02#ibcon#first serial, iclass 20, count 0 2006.162.07:51:53.02#ibcon#enter sib2, iclass 20, count 0 2006.162.07:51:53.02#ibcon#flushed, iclass 20, count 0 2006.162.07:51:53.02#ibcon#about to write, iclass 20, count 0 2006.162.07:51:53.02#ibcon#wrote, iclass 20, count 0 2006.162.07:51:53.02#ibcon#about to read 3, iclass 20, count 0 2006.162.07:51:53.04#ibcon#read 3, iclass 20, count 0 2006.162.07:51:53.04#ibcon#about to read 4, iclass 20, count 0 2006.162.07:51:53.04#ibcon#read 4, iclass 20, count 0 2006.162.07:51:53.04#ibcon#about to read 5, iclass 20, count 0 2006.162.07:51:53.04#ibcon#read 5, iclass 20, count 0 2006.162.07:51:53.04#ibcon#about to read 6, iclass 20, count 0 2006.162.07:51:53.04#ibcon#read 6, iclass 20, count 0 2006.162.07:51:53.04#ibcon#end of sib2, iclass 20, count 0 2006.162.07:51:53.04#ibcon#*mode == 0, iclass 20, count 0 2006.162.07:51:53.04#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.07:51:53.04#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.07:51:53.04#ibcon#*before write, iclass 20, count 0 2006.162.07:51:53.04#ibcon#enter sib2, iclass 20, count 0 2006.162.07:51:53.04#ibcon#flushed, iclass 20, count 0 2006.162.07:51:53.04#ibcon#about to write, iclass 20, count 0 2006.162.07:51:53.04#ibcon#wrote, iclass 20, count 0 2006.162.07:51:53.04#ibcon#about to read 3, iclass 20, count 0 2006.162.07:51:53.08#ibcon#read 3, iclass 20, count 0 2006.162.07:51:53.08#ibcon#about to read 4, iclass 20, count 0 2006.162.07:51:53.08#ibcon#read 4, iclass 20, count 0 2006.162.07:51:53.08#ibcon#about to read 5, iclass 20, count 0 2006.162.07:51:53.08#ibcon#read 5, iclass 20, count 0 2006.162.07:51:53.08#ibcon#about to read 6, iclass 20, count 0 2006.162.07:51:53.08#ibcon#read 6, iclass 20, count 0 2006.162.07:51:53.08#ibcon#end of sib2, iclass 20, count 0 2006.162.07:51:53.08#ibcon#*after write, iclass 20, count 0 2006.162.07:51:53.08#ibcon#*before return 0, iclass 20, count 0 2006.162.07:51:53.08#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:51:53.08#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.162.07:51:53.08#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.07:51:53.08#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.07:51:53.08$vc4f8/vb=1,4 2006.162.07:51:53.08#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.162.07:51:53.08#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.162.07:51:53.08#ibcon#ireg 11 cls_cnt 2 2006.162.07:51:53.08#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:51:53.08#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:51:53.08#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:51:53.08#ibcon#enter wrdev, iclass 22, count 2 2006.162.07:51:53.08#ibcon#first serial, iclass 22, count 2 2006.162.07:51:53.08#ibcon#enter sib2, iclass 22, count 2 2006.162.07:51:53.08#ibcon#flushed, iclass 22, count 2 2006.162.07:51:53.08#ibcon#about to write, iclass 22, count 2 2006.162.07:51:53.08#ibcon#wrote, iclass 22, count 2 2006.162.07:51:53.08#ibcon#about to read 3, iclass 22, count 2 2006.162.07:51:53.10#ibcon#read 3, iclass 22, count 2 2006.162.07:51:53.10#ibcon#about to read 4, iclass 22, count 2 2006.162.07:51:53.10#ibcon#read 4, iclass 22, count 2 2006.162.07:51:53.10#ibcon#about to read 5, iclass 22, count 2 2006.162.07:51:53.10#ibcon#read 5, iclass 22, count 2 2006.162.07:51:53.10#ibcon#about to read 6, iclass 22, count 2 2006.162.07:51:53.10#ibcon#read 6, iclass 22, count 2 2006.162.07:51:53.10#ibcon#end of sib2, iclass 22, count 2 2006.162.07:51:53.10#ibcon#*mode == 0, iclass 22, count 2 2006.162.07:51:53.10#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.162.07:51:53.10#ibcon#[27=AT01-04\r\n] 2006.162.07:51:53.10#ibcon#*before write, iclass 22, count 2 2006.162.07:51:53.10#ibcon#enter sib2, iclass 22, count 2 2006.162.07:51:53.10#ibcon#flushed, iclass 22, count 2 2006.162.07:51:53.10#ibcon#about to write, iclass 22, count 2 2006.162.07:51:53.10#ibcon#wrote, iclass 22, count 2 2006.162.07:51:53.10#ibcon#about to read 3, iclass 22, count 2 2006.162.07:51:53.13#ibcon#read 3, iclass 22, count 2 2006.162.07:51:53.13#ibcon#about to read 4, iclass 22, count 2 2006.162.07:51:53.13#ibcon#read 4, iclass 22, count 2 2006.162.07:51:53.13#ibcon#about to read 5, iclass 22, count 2 2006.162.07:51:53.13#ibcon#read 5, iclass 22, count 2 2006.162.07:51:53.13#ibcon#about to read 6, iclass 22, count 2 2006.162.07:51:53.13#ibcon#read 6, iclass 22, count 2 2006.162.07:51:53.13#ibcon#end of sib2, iclass 22, count 2 2006.162.07:51:53.13#ibcon#*after write, iclass 22, count 2 2006.162.07:51:53.13#ibcon#*before return 0, iclass 22, count 2 2006.162.07:51:53.13#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:51:53.13#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.162.07:51:53.13#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.162.07:51:53.13#ibcon#ireg 7 cls_cnt 0 2006.162.07:51:53.13#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:51:53.25#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:51:53.25#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:51:53.25#ibcon#enter wrdev, iclass 22, count 0 2006.162.07:51:53.25#ibcon#first serial, iclass 22, count 0 2006.162.07:51:53.25#ibcon#enter sib2, iclass 22, count 0 2006.162.07:51:53.25#ibcon#flushed, iclass 22, count 0 2006.162.07:51:53.25#ibcon#about to write, iclass 22, count 0 2006.162.07:51:53.25#ibcon#wrote, iclass 22, count 0 2006.162.07:51:53.25#ibcon#about to read 3, iclass 22, count 0 2006.162.07:51:53.27#ibcon#read 3, iclass 22, count 0 2006.162.07:51:53.27#ibcon#about to read 4, iclass 22, count 0 2006.162.07:51:53.27#ibcon#read 4, iclass 22, count 0 2006.162.07:51:53.27#ibcon#about to read 5, iclass 22, count 0 2006.162.07:51:53.27#ibcon#read 5, iclass 22, count 0 2006.162.07:51:53.27#ibcon#about to read 6, iclass 22, count 0 2006.162.07:51:53.27#ibcon#read 6, iclass 22, count 0 2006.162.07:51:53.27#ibcon#end of sib2, iclass 22, count 0 2006.162.07:51:53.27#ibcon#*mode == 0, iclass 22, count 0 2006.162.07:51:53.27#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.07:51:53.27#ibcon#[27=USB\r\n] 2006.162.07:51:53.27#ibcon#*before write, iclass 22, count 0 2006.162.07:51:53.27#ibcon#enter sib2, iclass 22, count 0 2006.162.07:51:53.27#ibcon#flushed, iclass 22, count 0 2006.162.07:51:53.27#ibcon#about to write, iclass 22, count 0 2006.162.07:51:53.27#ibcon#wrote, iclass 22, count 0 2006.162.07:51:53.27#ibcon#about to read 3, iclass 22, count 0 2006.162.07:51:53.30#ibcon#read 3, iclass 22, count 0 2006.162.07:51:53.30#ibcon#about to read 4, iclass 22, count 0 2006.162.07:51:53.30#ibcon#read 4, iclass 22, count 0 2006.162.07:51:53.30#ibcon#about to read 5, iclass 22, count 0 2006.162.07:51:53.30#ibcon#read 5, iclass 22, count 0 2006.162.07:51:53.30#ibcon#about to read 6, iclass 22, count 0 2006.162.07:51:53.30#ibcon#read 6, iclass 22, count 0 2006.162.07:51:53.30#ibcon#end of sib2, iclass 22, count 0 2006.162.07:51:53.30#ibcon#*after write, iclass 22, count 0 2006.162.07:51:53.30#ibcon#*before return 0, iclass 22, count 0 2006.162.07:51:53.30#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:51:53.30#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.162.07:51:53.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.07:51:53.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.07:51:53.30$vc4f8/vblo=2,640.99 2006.162.07:51:53.30#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.162.07:51:53.30#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.162.07:51:53.30#ibcon#ireg 17 cls_cnt 0 2006.162.07:51:53.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:51:53.30#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:51:53.30#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:51:53.30#ibcon#enter wrdev, iclass 24, count 0 2006.162.07:51:53.30#ibcon#first serial, iclass 24, count 0 2006.162.07:51:53.30#ibcon#enter sib2, iclass 24, count 0 2006.162.07:51:53.30#ibcon#flushed, iclass 24, count 0 2006.162.07:51:53.30#ibcon#about to write, iclass 24, count 0 2006.162.07:51:53.30#ibcon#wrote, iclass 24, count 0 2006.162.07:51:53.30#ibcon#about to read 3, iclass 24, count 0 2006.162.07:51:53.32#ibcon#read 3, iclass 24, count 0 2006.162.07:51:53.32#ibcon#about to read 4, iclass 24, count 0 2006.162.07:51:53.32#ibcon#read 4, iclass 24, count 0 2006.162.07:51:53.32#ibcon#about to read 5, iclass 24, count 0 2006.162.07:51:53.32#ibcon#read 5, iclass 24, count 0 2006.162.07:51:53.32#ibcon#about to read 6, iclass 24, count 0 2006.162.07:51:53.32#ibcon#read 6, iclass 24, count 0 2006.162.07:51:53.32#ibcon#end of sib2, iclass 24, count 0 2006.162.07:51:53.32#ibcon#*mode == 0, iclass 24, count 0 2006.162.07:51:53.32#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.07:51:53.32#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.07:51:53.32#ibcon#*before write, iclass 24, count 0 2006.162.07:51:53.32#ibcon#enter sib2, iclass 24, count 0 2006.162.07:51:53.32#ibcon#flushed, iclass 24, count 0 2006.162.07:51:53.32#ibcon#about to write, iclass 24, count 0 2006.162.07:51:53.32#ibcon#wrote, iclass 24, count 0 2006.162.07:51:53.32#ibcon#about to read 3, iclass 24, count 0 2006.162.07:51:53.36#ibcon#read 3, iclass 24, count 0 2006.162.07:51:53.36#ibcon#about to read 4, iclass 24, count 0 2006.162.07:51:53.36#ibcon#read 4, iclass 24, count 0 2006.162.07:51:53.36#ibcon#about to read 5, iclass 24, count 0 2006.162.07:51:53.36#ibcon#read 5, iclass 24, count 0 2006.162.07:51:53.36#ibcon#about to read 6, iclass 24, count 0 2006.162.07:51:53.36#ibcon#read 6, iclass 24, count 0 2006.162.07:51:53.36#ibcon#end of sib2, iclass 24, count 0 2006.162.07:51:53.36#ibcon#*after write, iclass 24, count 0 2006.162.07:51:53.36#ibcon#*before return 0, iclass 24, count 0 2006.162.07:51:53.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:51:53.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.162.07:51:53.36#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.07:51:53.36#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.07:51:53.36$vc4f8/vb=2,4 2006.162.07:51:53.36#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.162.07:51:53.36#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.162.07:51:53.36#ibcon#ireg 11 cls_cnt 2 2006.162.07:51:53.36#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:51:53.42#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:51:53.42#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:51:53.42#ibcon#enter wrdev, iclass 26, count 2 2006.162.07:51:53.42#ibcon#first serial, iclass 26, count 2 2006.162.07:51:53.42#ibcon#enter sib2, iclass 26, count 2 2006.162.07:51:53.42#ibcon#flushed, iclass 26, count 2 2006.162.07:51:53.42#ibcon#about to write, iclass 26, count 2 2006.162.07:51:53.42#ibcon#wrote, iclass 26, count 2 2006.162.07:51:53.42#ibcon#about to read 3, iclass 26, count 2 2006.162.07:51:53.44#ibcon#read 3, iclass 26, count 2 2006.162.07:51:53.44#ibcon#about to read 4, iclass 26, count 2 2006.162.07:51:53.44#ibcon#read 4, iclass 26, count 2 2006.162.07:51:53.44#ibcon#about to read 5, iclass 26, count 2 2006.162.07:51:53.44#ibcon#read 5, iclass 26, count 2 2006.162.07:51:53.44#ibcon#about to read 6, iclass 26, count 2 2006.162.07:51:53.44#ibcon#read 6, iclass 26, count 2 2006.162.07:51:53.44#ibcon#end of sib2, iclass 26, count 2 2006.162.07:51:53.44#ibcon#*mode == 0, iclass 26, count 2 2006.162.07:51:53.44#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.162.07:51:53.44#ibcon#[27=AT02-04\r\n] 2006.162.07:51:53.44#ibcon#*before write, iclass 26, count 2 2006.162.07:51:53.44#ibcon#enter sib2, iclass 26, count 2 2006.162.07:51:53.44#ibcon#flushed, iclass 26, count 2 2006.162.07:51:53.44#ibcon#about to write, iclass 26, count 2 2006.162.07:51:53.44#ibcon#wrote, iclass 26, count 2 2006.162.07:51:53.44#ibcon#about to read 3, iclass 26, count 2 2006.162.07:51:53.47#ibcon#read 3, iclass 26, count 2 2006.162.07:51:53.47#ibcon#about to read 4, iclass 26, count 2 2006.162.07:51:53.47#ibcon#read 4, iclass 26, count 2 2006.162.07:51:53.47#ibcon#about to read 5, iclass 26, count 2 2006.162.07:51:53.47#ibcon#read 5, iclass 26, count 2 2006.162.07:51:53.47#ibcon#about to read 6, iclass 26, count 2 2006.162.07:51:53.47#ibcon#read 6, iclass 26, count 2 2006.162.07:51:53.47#ibcon#end of sib2, iclass 26, count 2 2006.162.07:51:53.47#ibcon#*after write, iclass 26, count 2 2006.162.07:51:53.47#ibcon#*before return 0, iclass 26, count 2 2006.162.07:51:53.47#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:51:53.47#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.162.07:51:53.47#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.162.07:51:53.47#ibcon#ireg 7 cls_cnt 0 2006.162.07:51:53.47#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:51:53.59#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:51:53.59#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:51:53.59#ibcon#enter wrdev, iclass 26, count 0 2006.162.07:51:53.59#ibcon#first serial, iclass 26, count 0 2006.162.07:51:53.59#ibcon#enter sib2, iclass 26, count 0 2006.162.07:51:53.59#ibcon#flushed, iclass 26, count 0 2006.162.07:51:53.59#ibcon#about to write, iclass 26, count 0 2006.162.07:51:53.59#ibcon#wrote, iclass 26, count 0 2006.162.07:51:53.59#ibcon#about to read 3, iclass 26, count 0 2006.162.07:51:53.61#ibcon#read 3, iclass 26, count 0 2006.162.07:51:53.61#ibcon#about to read 4, iclass 26, count 0 2006.162.07:51:53.61#ibcon#read 4, iclass 26, count 0 2006.162.07:51:53.61#ibcon#about to read 5, iclass 26, count 0 2006.162.07:51:53.61#ibcon#read 5, iclass 26, count 0 2006.162.07:51:53.61#ibcon#about to read 6, iclass 26, count 0 2006.162.07:51:53.61#ibcon#read 6, iclass 26, count 0 2006.162.07:51:53.61#ibcon#end of sib2, iclass 26, count 0 2006.162.07:51:53.61#ibcon#*mode == 0, iclass 26, count 0 2006.162.07:51:53.61#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.162.07:51:53.61#ibcon#[27=USB\r\n] 2006.162.07:51:53.61#ibcon#*before write, iclass 26, count 0 2006.162.07:51:53.61#ibcon#enter sib2, iclass 26, count 0 2006.162.07:51:53.61#ibcon#flushed, iclass 26, count 0 2006.162.07:51:53.61#ibcon#about to write, iclass 26, count 0 2006.162.07:51:53.61#ibcon#wrote, iclass 26, count 0 2006.162.07:51:53.61#ibcon#about to read 3, iclass 26, count 0 2006.162.07:51:53.64#ibcon#read 3, iclass 26, count 0 2006.162.07:51:53.64#ibcon#about to read 4, iclass 26, count 0 2006.162.07:51:53.64#ibcon#read 4, iclass 26, count 0 2006.162.07:51:53.64#ibcon#about to read 5, iclass 26, count 0 2006.162.07:51:53.64#ibcon#read 5, iclass 26, count 0 2006.162.07:51:53.64#ibcon#about to read 6, iclass 26, count 0 2006.162.07:51:53.64#ibcon#read 6, iclass 26, count 0 2006.162.07:51:53.64#ibcon#end of sib2, iclass 26, count 0 2006.162.07:51:53.64#ibcon#*after write, iclass 26, count 0 2006.162.07:51:53.64#ibcon#*before return 0, iclass 26, count 0 2006.162.07:51:53.64#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:51:53.64#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.162.07:51:53.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.162.07:51:53.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.162.07:51:53.64$vc4f8/vblo=3,656.99 2006.162.07:51:53.64#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.162.07:51:53.64#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.162.07:51:53.64#ibcon#ireg 17 cls_cnt 0 2006.162.07:51:53.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:51:53.64#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:51:53.64#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:51:53.64#ibcon#enter wrdev, iclass 28, count 0 2006.162.07:51:53.64#ibcon#first serial, iclass 28, count 0 2006.162.07:51:53.64#ibcon#enter sib2, iclass 28, count 0 2006.162.07:51:53.64#ibcon#flushed, iclass 28, count 0 2006.162.07:51:53.64#ibcon#about to write, iclass 28, count 0 2006.162.07:51:53.64#ibcon#wrote, iclass 28, count 0 2006.162.07:51:53.64#ibcon#about to read 3, iclass 28, count 0 2006.162.07:51:53.66#ibcon#read 3, iclass 28, count 0 2006.162.07:51:53.66#ibcon#about to read 4, iclass 28, count 0 2006.162.07:51:53.66#ibcon#read 4, iclass 28, count 0 2006.162.07:51:53.66#ibcon#about to read 5, iclass 28, count 0 2006.162.07:51:53.66#ibcon#read 5, iclass 28, count 0 2006.162.07:51:53.66#ibcon#about to read 6, iclass 28, count 0 2006.162.07:51:53.66#ibcon#read 6, iclass 28, count 0 2006.162.07:51:53.66#ibcon#end of sib2, iclass 28, count 0 2006.162.07:51:53.66#ibcon#*mode == 0, iclass 28, count 0 2006.162.07:51:53.66#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.162.07:51:53.66#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.07:51:53.66#ibcon#*before write, iclass 28, count 0 2006.162.07:51:53.66#ibcon#enter sib2, iclass 28, count 0 2006.162.07:51:53.66#ibcon#flushed, iclass 28, count 0 2006.162.07:51:53.66#ibcon#about to write, iclass 28, count 0 2006.162.07:51:53.66#ibcon#wrote, iclass 28, count 0 2006.162.07:51:53.66#ibcon#about to read 3, iclass 28, count 0 2006.162.07:51:53.70#ibcon#read 3, iclass 28, count 0 2006.162.07:51:53.70#ibcon#about to read 4, iclass 28, count 0 2006.162.07:51:53.70#ibcon#read 4, iclass 28, count 0 2006.162.07:51:53.70#ibcon#about to read 5, iclass 28, count 0 2006.162.07:51:53.70#ibcon#read 5, iclass 28, count 0 2006.162.07:51:53.70#ibcon#about to read 6, iclass 28, count 0 2006.162.07:51:53.70#ibcon#read 6, iclass 28, count 0 2006.162.07:51:53.70#ibcon#end of sib2, iclass 28, count 0 2006.162.07:51:53.70#ibcon#*after write, iclass 28, count 0 2006.162.07:51:53.70#ibcon#*before return 0, iclass 28, count 0 2006.162.07:51:53.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:51:53.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:51:53.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.162.07:51:53.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.162.07:51:53.70$vc4f8/vb=3,4 2006.162.07:51:53.70#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.162.07:51:53.70#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.162.07:51:53.70#ibcon#ireg 11 cls_cnt 2 2006.162.07:51:53.70#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:51:53.76#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:51:53.76#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:51:53.76#ibcon#enter wrdev, iclass 30, count 2 2006.162.07:51:53.76#ibcon#first serial, iclass 30, count 2 2006.162.07:51:53.76#ibcon#enter sib2, iclass 30, count 2 2006.162.07:51:53.76#ibcon#flushed, iclass 30, count 2 2006.162.07:51:53.76#ibcon#about to write, iclass 30, count 2 2006.162.07:51:53.76#ibcon#wrote, iclass 30, count 2 2006.162.07:51:53.76#ibcon#about to read 3, iclass 30, count 2 2006.162.07:51:53.78#ibcon#read 3, iclass 30, count 2 2006.162.07:51:53.78#ibcon#about to read 4, iclass 30, count 2 2006.162.07:51:53.78#ibcon#read 4, iclass 30, count 2 2006.162.07:51:53.78#ibcon#about to read 5, iclass 30, count 2 2006.162.07:51:53.78#ibcon#read 5, iclass 30, count 2 2006.162.07:51:53.78#ibcon#about to read 6, iclass 30, count 2 2006.162.07:51:53.78#ibcon#read 6, iclass 30, count 2 2006.162.07:51:53.78#ibcon#end of sib2, iclass 30, count 2 2006.162.07:51:53.78#ibcon#*mode == 0, iclass 30, count 2 2006.162.07:51:53.78#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.162.07:51:53.78#ibcon#[27=AT03-04\r\n] 2006.162.07:51:53.78#ibcon#*before write, iclass 30, count 2 2006.162.07:51:53.78#ibcon#enter sib2, iclass 30, count 2 2006.162.07:51:53.78#ibcon#flushed, iclass 30, count 2 2006.162.07:51:53.78#ibcon#about to write, iclass 30, count 2 2006.162.07:51:53.78#ibcon#wrote, iclass 30, count 2 2006.162.07:51:53.78#ibcon#about to read 3, iclass 30, count 2 2006.162.07:51:53.81#ibcon#read 3, iclass 30, count 2 2006.162.07:51:53.81#ibcon#about to read 4, iclass 30, count 2 2006.162.07:51:53.81#ibcon#read 4, iclass 30, count 2 2006.162.07:51:53.81#ibcon#about to read 5, iclass 30, count 2 2006.162.07:51:53.81#ibcon#read 5, iclass 30, count 2 2006.162.07:51:53.81#ibcon#about to read 6, iclass 30, count 2 2006.162.07:51:53.81#ibcon#read 6, iclass 30, count 2 2006.162.07:51:53.81#ibcon#end of sib2, iclass 30, count 2 2006.162.07:51:53.81#ibcon#*after write, iclass 30, count 2 2006.162.07:51:53.81#ibcon#*before return 0, iclass 30, count 2 2006.162.07:51:53.81#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:51:53.81#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.162.07:51:53.81#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.162.07:51:53.81#ibcon#ireg 7 cls_cnt 0 2006.162.07:51:53.81#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:51:53.93#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:51:53.93#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:51:53.93#ibcon#enter wrdev, iclass 30, count 0 2006.162.07:51:53.93#ibcon#first serial, iclass 30, count 0 2006.162.07:51:53.93#ibcon#enter sib2, iclass 30, count 0 2006.162.07:51:53.93#ibcon#flushed, iclass 30, count 0 2006.162.07:51:53.93#ibcon#about to write, iclass 30, count 0 2006.162.07:51:53.93#ibcon#wrote, iclass 30, count 0 2006.162.07:51:53.93#ibcon#about to read 3, iclass 30, count 0 2006.162.07:51:53.95#ibcon#read 3, iclass 30, count 0 2006.162.07:51:53.95#ibcon#about to read 4, iclass 30, count 0 2006.162.07:51:53.95#ibcon#read 4, iclass 30, count 0 2006.162.07:51:53.95#ibcon#about to read 5, iclass 30, count 0 2006.162.07:51:53.95#ibcon#read 5, iclass 30, count 0 2006.162.07:51:53.95#ibcon#about to read 6, iclass 30, count 0 2006.162.07:51:53.95#ibcon#read 6, iclass 30, count 0 2006.162.07:51:53.95#ibcon#end of sib2, iclass 30, count 0 2006.162.07:51:53.95#ibcon#*mode == 0, iclass 30, count 0 2006.162.07:51:53.95#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.162.07:51:53.95#ibcon#[27=USB\r\n] 2006.162.07:51:53.95#ibcon#*before write, iclass 30, count 0 2006.162.07:51:53.95#ibcon#enter sib2, iclass 30, count 0 2006.162.07:51:53.95#ibcon#flushed, iclass 30, count 0 2006.162.07:51:53.95#ibcon#about to write, iclass 30, count 0 2006.162.07:51:53.95#ibcon#wrote, iclass 30, count 0 2006.162.07:51:53.95#ibcon#about to read 3, iclass 30, count 0 2006.162.07:51:53.98#ibcon#read 3, iclass 30, count 0 2006.162.07:51:53.98#ibcon#about to read 4, iclass 30, count 0 2006.162.07:51:53.98#ibcon#read 4, iclass 30, count 0 2006.162.07:51:53.98#ibcon#about to read 5, iclass 30, count 0 2006.162.07:51:53.98#ibcon#read 5, iclass 30, count 0 2006.162.07:51:53.98#ibcon#about to read 6, iclass 30, count 0 2006.162.07:51:53.98#ibcon#read 6, iclass 30, count 0 2006.162.07:51:53.98#ibcon#end of sib2, iclass 30, count 0 2006.162.07:51:53.98#ibcon#*after write, iclass 30, count 0 2006.162.07:51:53.98#ibcon#*before return 0, iclass 30, count 0 2006.162.07:51:53.98#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:51:53.98#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.162.07:51:53.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.162.07:51:53.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.162.07:51:53.98$vc4f8/vblo=4,712.99 2006.162.07:51:53.98#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.162.07:51:53.98#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.162.07:51:53.98#ibcon#ireg 17 cls_cnt 0 2006.162.07:51:53.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:51:53.98#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:51:53.98#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:51:53.98#ibcon#enter wrdev, iclass 32, count 0 2006.162.07:51:53.98#ibcon#first serial, iclass 32, count 0 2006.162.07:51:53.98#ibcon#enter sib2, iclass 32, count 0 2006.162.07:51:53.98#ibcon#flushed, iclass 32, count 0 2006.162.07:51:53.98#ibcon#about to write, iclass 32, count 0 2006.162.07:51:53.98#ibcon#wrote, iclass 32, count 0 2006.162.07:51:53.98#ibcon#about to read 3, iclass 32, count 0 2006.162.07:51:54.00#ibcon#read 3, iclass 32, count 0 2006.162.07:51:54.00#ibcon#about to read 4, iclass 32, count 0 2006.162.07:51:54.00#ibcon#read 4, iclass 32, count 0 2006.162.07:51:54.00#ibcon#about to read 5, iclass 32, count 0 2006.162.07:51:54.00#ibcon#read 5, iclass 32, count 0 2006.162.07:51:54.00#ibcon#about to read 6, iclass 32, count 0 2006.162.07:51:54.00#ibcon#read 6, iclass 32, count 0 2006.162.07:51:54.00#ibcon#end of sib2, iclass 32, count 0 2006.162.07:51:54.00#ibcon#*mode == 0, iclass 32, count 0 2006.162.07:51:54.00#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.162.07:51:54.00#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.07:51:54.00#ibcon#*before write, iclass 32, count 0 2006.162.07:51:54.00#ibcon#enter sib2, iclass 32, count 0 2006.162.07:51:54.00#ibcon#flushed, iclass 32, count 0 2006.162.07:51:54.00#ibcon#about to write, iclass 32, count 0 2006.162.07:51:54.00#ibcon#wrote, iclass 32, count 0 2006.162.07:51:54.00#ibcon#about to read 3, iclass 32, count 0 2006.162.07:51:54.04#ibcon#read 3, iclass 32, count 0 2006.162.07:51:54.04#ibcon#about to read 4, iclass 32, count 0 2006.162.07:51:54.04#ibcon#read 4, iclass 32, count 0 2006.162.07:51:54.04#ibcon#about to read 5, iclass 32, count 0 2006.162.07:51:54.04#ibcon#read 5, iclass 32, count 0 2006.162.07:51:54.04#ibcon#about to read 6, iclass 32, count 0 2006.162.07:51:54.04#ibcon#read 6, iclass 32, count 0 2006.162.07:51:54.04#ibcon#end of sib2, iclass 32, count 0 2006.162.07:51:54.04#ibcon#*after write, iclass 32, count 0 2006.162.07:51:54.04#ibcon#*before return 0, iclass 32, count 0 2006.162.07:51:54.04#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:51:54.04#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.162.07:51:54.04#ibcon#about to clear, iclass 32 cls_cnt 0 2006.162.07:51:54.04#ibcon#cleared, iclass 32 cls_cnt 0 2006.162.07:51:54.04$vc4f8/vb=4,4 2006.162.07:51:54.04#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.162.07:51:54.04#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.162.07:51:54.04#ibcon#ireg 11 cls_cnt 2 2006.162.07:51:54.04#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.162.07:51:54.10#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.162.07:51:54.10#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.162.07:51:54.10#ibcon#enter wrdev, iclass 34, count 2 2006.162.07:51:54.10#ibcon#first serial, iclass 34, count 2 2006.162.07:51:54.10#ibcon#enter sib2, iclass 34, count 2 2006.162.07:51:54.10#ibcon#flushed, iclass 34, count 2 2006.162.07:51:54.10#ibcon#about to write, iclass 34, count 2 2006.162.07:51:54.10#ibcon#wrote, iclass 34, count 2 2006.162.07:51:54.10#ibcon#about to read 3, iclass 34, count 2 2006.162.07:51:54.12#ibcon#read 3, iclass 34, count 2 2006.162.07:51:54.12#ibcon#about to read 4, iclass 34, count 2 2006.162.07:51:54.12#ibcon#read 4, iclass 34, count 2 2006.162.07:51:54.12#ibcon#about to read 5, iclass 34, count 2 2006.162.07:51:54.12#ibcon#read 5, iclass 34, count 2 2006.162.07:51:54.12#ibcon#about to read 6, iclass 34, count 2 2006.162.07:51:54.12#ibcon#read 6, iclass 34, count 2 2006.162.07:51:54.12#ibcon#end of sib2, iclass 34, count 2 2006.162.07:51:54.12#ibcon#*mode == 0, iclass 34, count 2 2006.162.07:51:54.12#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.162.07:51:54.12#ibcon#[27=AT04-04\r\n] 2006.162.07:51:54.12#ibcon#*before write, iclass 34, count 2 2006.162.07:51:54.12#ibcon#enter sib2, iclass 34, count 2 2006.162.07:51:54.12#ibcon#flushed, iclass 34, count 2 2006.162.07:51:54.12#ibcon#about to write, iclass 34, count 2 2006.162.07:51:54.12#ibcon#wrote, iclass 34, count 2 2006.162.07:51:54.12#ibcon#about to read 3, iclass 34, count 2 2006.162.07:51:54.15#ibcon#read 3, iclass 34, count 2 2006.162.07:51:54.15#ibcon#about to read 4, iclass 34, count 2 2006.162.07:51:54.15#ibcon#read 4, iclass 34, count 2 2006.162.07:51:54.15#ibcon#about to read 5, iclass 34, count 2 2006.162.07:51:54.15#ibcon#read 5, iclass 34, count 2 2006.162.07:51:54.15#ibcon#about to read 6, iclass 34, count 2 2006.162.07:51:54.15#ibcon#read 6, iclass 34, count 2 2006.162.07:51:54.15#ibcon#end of sib2, iclass 34, count 2 2006.162.07:51:54.15#ibcon#*after write, iclass 34, count 2 2006.162.07:51:54.15#ibcon#*before return 0, iclass 34, count 2 2006.162.07:51:54.15#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.162.07:51:54.15#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.162.07:51:54.15#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.162.07:51:54.15#ibcon#ireg 7 cls_cnt 0 2006.162.07:51:54.15#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.162.07:51:54.27#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.162.07:51:54.27#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.162.07:51:54.27#ibcon#enter wrdev, iclass 34, count 0 2006.162.07:51:54.27#ibcon#first serial, iclass 34, count 0 2006.162.07:51:54.27#ibcon#enter sib2, iclass 34, count 0 2006.162.07:51:54.27#ibcon#flushed, iclass 34, count 0 2006.162.07:51:54.27#ibcon#about to write, iclass 34, count 0 2006.162.07:51:54.27#ibcon#wrote, iclass 34, count 0 2006.162.07:51:54.27#ibcon#about to read 3, iclass 34, count 0 2006.162.07:51:54.29#ibcon#read 3, iclass 34, count 0 2006.162.07:51:54.29#ibcon#about to read 4, iclass 34, count 0 2006.162.07:51:54.29#ibcon#read 4, iclass 34, count 0 2006.162.07:51:54.29#ibcon#about to read 5, iclass 34, count 0 2006.162.07:51:54.29#ibcon#read 5, iclass 34, count 0 2006.162.07:51:54.29#ibcon#about to read 6, iclass 34, count 0 2006.162.07:51:54.29#ibcon#read 6, iclass 34, count 0 2006.162.07:51:54.29#ibcon#end of sib2, iclass 34, count 0 2006.162.07:51:54.29#ibcon#*mode == 0, iclass 34, count 0 2006.162.07:51:54.29#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.162.07:51:54.29#ibcon#[27=USB\r\n] 2006.162.07:51:54.29#ibcon#*before write, iclass 34, count 0 2006.162.07:51:54.29#ibcon#enter sib2, iclass 34, count 0 2006.162.07:51:54.29#ibcon#flushed, iclass 34, count 0 2006.162.07:51:54.29#ibcon#about to write, iclass 34, count 0 2006.162.07:51:54.29#ibcon#wrote, iclass 34, count 0 2006.162.07:51:54.29#ibcon#about to read 3, iclass 34, count 0 2006.162.07:51:54.32#ibcon#read 3, iclass 34, count 0 2006.162.07:51:54.32#ibcon#about to read 4, iclass 34, count 0 2006.162.07:51:54.32#ibcon#read 4, iclass 34, count 0 2006.162.07:51:54.32#ibcon#about to read 5, iclass 34, count 0 2006.162.07:51:54.32#ibcon#read 5, iclass 34, count 0 2006.162.07:51:54.32#ibcon#about to read 6, iclass 34, count 0 2006.162.07:51:54.32#ibcon#read 6, iclass 34, count 0 2006.162.07:51:54.32#ibcon#end of sib2, iclass 34, count 0 2006.162.07:51:54.32#ibcon#*after write, iclass 34, count 0 2006.162.07:51:54.32#ibcon#*before return 0, iclass 34, count 0 2006.162.07:51:54.32#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.162.07:51:54.32#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.162.07:51:54.32#ibcon#about to clear, iclass 34 cls_cnt 0 2006.162.07:51:54.32#ibcon#cleared, iclass 34 cls_cnt 0 2006.162.07:51:54.32$vc4f8/vblo=5,744.99 2006.162.07:51:54.32#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.162.07:51:54.32#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.162.07:51:54.32#ibcon#ireg 17 cls_cnt 0 2006.162.07:51:54.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:51:54.32#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:51:54.32#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:51:54.32#ibcon#enter wrdev, iclass 36, count 0 2006.162.07:51:54.32#ibcon#first serial, iclass 36, count 0 2006.162.07:51:54.32#ibcon#enter sib2, iclass 36, count 0 2006.162.07:51:54.32#ibcon#flushed, iclass 36, count 0 2006.162.07:51:54.32#ibcon#about to write, iclass 36, count 0 2006.162.07:51:54.32#ibcon#wrote, iclass 36, count 0 2006.162.07:51:54.32#ibcon#about to read 3, iclass 36, count 0 2006.162.07:51:54.34#ibcon#read 3, iclass 36, count 0 2006.162.07:51:54.34#ibcon#about to read 4, iclass 36, count 0 2006.162.07:51:54.34#ibcon#read 4, iclass 36, count 0 2006.162.07:51:54.34#ibcon#about to read 5, iclass 36, count 0 2006.162.07:51:54.34#ibcon#read 5, iclass 36, count 0 2006.162.07:51:54.34#ibcon#about to read 6, iclass 36, count 0 2006.162.07:51:54.34#ibcon#read 6, iclass 36, count 0 2006.162.07:51:54.34#ibcon#end of sib2, iclass 36, count 0 2006.162.07:51:54.34#ibcon#*mode == 0, iclass 36, count 0 2006.162.07:51:54.34#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.162.07:51:54.34#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.07:51:54.34#ibcon#*before write, iclass 36, count 0 2006.162.07:51:54.34#ibcon#enter sib2, iclass 36, count 0 2006.162.07:51:54.34#ibcon#flushed, iclass 36, count 0 2006.162.07:51:54.34#ibcon#about to write, iclass 36, count 0 2006.162.07:51:54.34#ibcon#wrote, iclass 36, count 0 2006.162.07:51:54.34#ibcon#about to read 3, iclass 36, count 0 2006.162.07:51:54.38#ibcon#read 3, iclass 36, count 0 2006.162.07:51:54.38#ibcon#about to read 4, iclass 36, count 0 2006.162.07:51:54.38#ibcon#read 4, iclass 36, count 0 2006.162.07:51:54.38#ibcon#about to read 5, iclass 36, count 0 2006.162.07:51:54.38#ibcon#read 5, iclass 36, count 0 2006.162.07:51:54.38#ibcon#about to read 6, iclass 36, count 0 2006.162.07:51:54.38#ibcon#read 6, iclass 36, count 0 2006.162.07:51:54.38#ibcon#end of sib2, iclass 36, count 0 2006.162.07:51:54.38#ibcon#*after write, iclass 36, count 0 2006.162.07:51:54.38#ibcon#*before return 0, iclass 36, count 0 2006.162.07:51:54.38#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:51:54.38#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.162.07:51:54.38#ibcon#about to clear, iclass 36 cls_cnt 0 2006.162.07:51:54.38#ibcon#cleared, iclass 36 cls_cnt 0 2006.162.07:51:54.38$vc4f8/vb=5,4 2006.162.07:51:54.38#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.162.07:51:54.38#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.162.07:51:54.38#ibcon#ireg 11 cls_cnt 2 2006.162.07:51:54.38#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:51:54.44#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:51:54.44#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:51:54.44#ibcon#enter wrdev, iclass 38, count 2 2006.162.07:51:54.44#ibcon#first serial, iclass 38, count 2 2006.162.07:51:54.44#ibcon#enter sib2, iclass 38, count 2 2006.162.07:51:54.44#ibcon#flushed, iclass 38, count 2 2006.162.07:51:54.44#ibcon#about to write, iclass 38, count 2 2006.162.07:51:54.44#ibcon#wrote, iclass 38, count 2 2006.162.07:51:54.44#ibcon#about to read 3, iclass 38, count 2 2006.162.07:51:54.46#ibcon#read 3, iclass 38, count 2 2006.162.07:51:54.46#ibcon#about to read 4, iclass 38, count 2 2006.162.07:51:54.46#ibcon#read 4, iclass 38, count 2 2006.162.07:51:54.46#ibcon#about to read 5, iclass 38, count 2 2006.162.07:51:54.46#ibcon#read 5, iclass 38, count 2 2006.162.07:51:54.46#ibcon#about to read 6, iclass 38, count 2 2006.162.07:51:54.46#ibcon#read 6, iclass 38, count 2 2006.162.07:51:54.46#ibcon#end of sib2, iclass 38, count 2 2006.162.07:51:54.46#ibcon#*mode == 0, iclass 38, count 2 2006.162.07:51:54.46#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.162.07:51:54.46#ibcon#[27=AT05-04\r\n] 2006.162.07:51:54.46#ibcon#*before write, iclass 38, count 2 2006.162.07:51:54.46#ibcon#enter sib2, iclass 38, count 2 2006.162.07:51:54.46#ibcon#flushed, iclass 38, count 2 2006.162.07:51:54.46#ibcon#about to write, iclass 38, count 2 2006.162.07:51:54.46#ibcon#wrote, iclass 38, count 2 2006.162.07:51:54.46#ibcon#about to read 3, iclass 38, count 2 2006.162.07:51:54.49#ibcon#read 3, iclass 38, count 2 2006.162.07:51:54.49#ibcon#about to read 4, iclass 38, count 2 2006.162.07:51:54.49#ibcon#read 4, iclass 38, count 2 2006.162.07:51:54.49#ibcon#about to read 5, iclass 38, count 2 2006.162.07:51:54.49#ibcon#read 5, iclass 38, count 2 2006.162.07:51:54.49#ibcon#about to read 6, iclass 38, count 2 2006.162.07:51:54.49#ibcon#read 6, iclass 38, count 2 2006.162.07:51:54.49#ibcon#end of sib2, iclass 38, count 2 2006.162.07:51:54.49#ibcon#*after write, iclass 38, count 2 2006.162.07:51:54.49#ibcon#*before return 0, iclass 38, count 2 2006.162.07:51:54.49#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:51:54.49#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.162.07:51:54.49#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.162.07:51:54.49#ibcon#ireg 7 cls_cnt 0 2006.162.07:51:54.49#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:51:54.61#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:51:54.61#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:51:54.61#ibcon#enter wrdev, iclass 38, count 0 2006.162.07:51:54.61#ibcon#first serial, iclass 38, count 0 2006.162.07:51:54.61#ibcon#enter sib2, iclass 38, count 0 2006.162.07:51:54.61#ibcon#flushed, iclass 38, count 0 2006.162.07:51:54.61#ibcon#about to write, iclass 38, count 0 2006.162.07:51:54.61#ibcon#wrote, iclass 38, count 0 2006.162.07:51:54.61#ibcon#about to read 3, iclass 38, count 0 2006.162.07:51:54.63#ibcon#read 3, iclass 38, count 0 2006.162.07:51:54.63#ibcon#about to read 4, iclass 38, count 0 2006.162.07:51:54.63#ibcon#read 4, iclass 38, count 0 2006.162.07:51:54.63#ibcon#about to read 5, iclass 38, count 0 2006.162.07:51:54.63#ibcon#read 5, iclass 38, count 0 2006.162.07:51:54.63#ibcon#about to read 6, iclass 38, count 0 2006.162.07:51:54.63#ibcon#read 6, iclass 38, count 0 2006.162.07:51:54.63#ibcon#end of sib2, iclass 38, count 0 2006.162.07:51:54.63#ibcon#*mode == 0, iclass 38, count 0 2006.162.07:51:54.63#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.162.07:51:54.63#ibcon#[27=USB\r\n] 2006.162.07:51:54.63#ibcon#*before write, iclass 38, count 0 2006.162.07:51:54.63#ibcon#enter sib2, iclass 38, count 0 2006.162.07:51:54.63#ibcon#flushed, iclass 38, count 0 2006.162.07:51:54.63#ibcon#about to write, iclass 38, count 0 2006.162.07:51:54.63#ibcon#wrote, iclass 38, count 0 2006.162.07:51:54.63#ibcon#about to read 3, iclass 38, count 0 2006.162.07:51:54.66#ibcon#read 3, iclass 38, count 0 2006.162.07:51:54.66#ibcon#about to read 4, iclass 38, count 0 2006.162.07:51:54.66#ibcon#read 4, iclass 38, count 0 2006.162.07:51:54.66#ibcon#about to read 5, iclass 38, count 0 2006.162.07:51:54.66#ibcon#read 5, iclass 38, count 0 2006.162.07:51:54.66#ibcon#about to read 6, iclass 38, count 0 2006.162.07:51:54.66#ibcon#read 6, iclass 38, count 0 2006.162.07:51:54.66#ibcon#end of sib2, iclass 38, count 0 2006.162.07:51:54.66#ibcon#*after write, iclass 38, count 0 2006.162.07:51:54.66#ibcon#*before return 0, iclass 38, count 0 2006.162.07:51:54.66#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:51:54.66#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.162.07:51:54.66#ibcon#about to clear, iclass 38 cls_cnt 0 2006.162.07:51:54.66#ibcon#cleared, iclass 38 cls_cnt 0 2006.162.07:51:54.66$vc4f8/vblo=6,752.99 2006.162.07:51:54.66#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.162.07:51:54.66#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.162.07:51:54.66#ibcon#ireg 17 cls_cnt 0 2006.162.07:51:54.66#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:51:54.66#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:51:54.66#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:51:54.66#ibcon#enter wrdev, iclass 40, count 0 2006.162.07:51:54.66#ibcon#first serial, iclass 40, count 0 2006.162.07:51:54.66#ibcon#enter sib2, iclass 40, count 0 2006.162.07:51:54.66#ibcon#flushed, iclass 40, count 0 2006.162.07:51:54.66#ibcon#about to write, iclass 40, count 0 2006.162.07:51:54.66#ibcon#wrote, iclass 40, count 0 2006.162.07:51:54.66#ibcon#about to read 3, iclass 40, count 0 2006.162.07:51:54.68#ibcon#read 3, iclass 40, count 0 2006.162.07:51:54.68#ibcon#about to read 4, iclass 40, count 0 2006.162.07:51:54.68#ibcon#read 4, iclass 40, count 0 2006.162.07:51:54.68#ibcon#about to read 5, iclass 40, count 0 2006.162.07:51:54.68#ibcon#read 5, iclass 40, count 0 2006.162.07:51:54.68#ibcon#about to read 6, iclass 40, count 0 2006.162.07:51:54.68#ibcon#read 6, iclass 40, count 0 2006.162.07:51:54.68#ibcon#end of sib2, iclass 40, count 0 2006.162.07:51:54.68#ibcon#*mode == 0, iclass 40, count 0 2006.162.07:51:54.68#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.162.07:51:54.68#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.07:51:54.68#ibcon#*before write, iclass 40, count 0 2006.162.07:51:54.68#ibcon#enter sib2, iclass 40, count 0 2006.162.07:51:54.68#ibcon#flushed, iclass 40, count 0 2006.162.07:51:54.68#ibcon#about to write, iclass 40, count 0 2006.162.07:51:54.68#ibcon#wrote, iclass 40, count 0 2006.162.07:51:54.68#ibcon#about to read 3, iclass 40, count 0 2006.162.07:51:54.72#ibcon#read 3, iclass 40, count 0 2006.162.07:51:54.72#ibcon#about to read 4, iclass 40, count 0 2006.162.07:51:54.72#ibcon#read 4, iclass 40, count 0 2006.162.07:51:54.72#ibcon#about to read 5, iclass 40, count 0 2006.162.07:51:54.72#ibcon#read 5, iclass 40, count 0 2006.162.07:51:54.72#ibcon#about to read 6, iclass 40, count 0 2006.162.07:51:54.72#ibcon#read 6, iclass 40, count 0 2006.162.07:51:54.72#ibcon#end of sib2, iclass 40, count 0 2006.162.07:51:54.72#ibcon#*after write, iclass 40, count 0 2006.162.07:51:54.72#ibcon#*before return 0, iclass 40, count 0 2006.162.07:51:54.72#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:51:54.72#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.162.07:51:54.72#ibcon#about to clear, iclass 40 cls_cnt 0 2006.162.07:51:54.72#ibcon#cleared, iclass 40 cls_cnt 0 2006.162.07:51:54.72$vc4f8/vb=6,4 2006.162.07:51:54.72#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.162.07:51:54.72#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.162.07:51:54.72#ibcon#ireg 11 cls_cnt 2 2006.162.07:51:54.72#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:51:54.78#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:51:54.78#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:51:54.78#ibcon#enter wrdev, iclass 4, count 2 2006.162.07:51:54.78#ibcon#first serial, iclass 4, count 2 2006.162.07:51:54.78#ibcon#enter sib2, iclass 4, count 2 2006.162.07:51:54.78#ibcon#flushed, iclass 4, count 2 2006.162.07:51:54.78#ibcon#about to write, iclass 4, count 2 2006.162.07:51:54.78#ibcon#wrote, iclass 4, count 2 2006.162.07:51:54.78#ibcon#about to read 3, iclass 4, count 2 2006.162.07:51:54.80#ibcon#read 3, iclass 4, count 2 2006.162.07:51:54.80#ibcon#about to read 4, iclass 4, count 2 2006.162.07:51:54.80#ibcon#read 4, iclass 4, count 2 2006.162.07:51:54.80#ibcon#about to read 5, iclass 4, count 2 2006.162.07:51:54.80#ibcon#read 5, iclass 4, count 2 2006.162.07:51:54.80#ibcon#about to read 6, iclass 4, count 2 2006.162.07:51:54.80#ibcon#read 6, iclass 4, count 2 2006.162.07:51:54.80#ibcon#end of sib2, iclass 4, count 2 2006.162.07:51:54.80#ibcon#*mode == 0, iclass 4, count 2 2006.162.07:51:54.80#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.162.07:51:54.80#ibcon#[27=AT06-04\r\n] 2006.162.07:51:54.80#ibcon#*before write, iclass 4, count 2 2006.162.07:51:54.80#ibcon#enter sib2, iclass 4, count 2 2006.162.07:51:54.80#ibcon#flushed, iclass 4, count 2 2006.162.07:51:54.80#ibcon#about to write, iclass 4, count 2 2006.162.07:51:54.80#ibcon#wrote, iclass 4, count 2 2006.162.07:51:54.80#ibcon#about to read 3, iclass 4, count 2 2006.162.07:51:54.83#ibcon#read 3, iclass 4, count 2 2006.162.07:51:54.83#ibcon#about to read 4, iclass 4, count 2 2006.162.07:51:54.83#ibcon#read 4, iclass 4, count 2 2006.162.07:51:54.83#ibcon#about to read 5, iclass 4, count 2 2006.162.07:51:54.83#ibcon#read 5, iclass 4, count 2 2006.162.07:51:54.83#ibcon#about to read 6, iclass 4, count 2 2006.162.07:51:54.83#ibcon#read 6, iclass 4, count 2 2006.162.07:51:54.83#ibcon#end of sib2, iclass 4, count 2 2006.162.07:51:54.83#ibcon#*after write, iclass 4, count 2 2006.162.07:51:54.83#ibcon#*before return 0, iclass 4, count 2 2006.162.07:51:54.83#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:51:54.83#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.162.07:51:54.83#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.162.07:51:54.83#ibcon#ireg 7 cls_cnt 0 2006.162.07:51:54.83#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:51:54.95#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:51:54.95#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:51:54.95#ibcon#enter wrdev, iclass 4, count 0 2006.162.07:51:54.95#ibcon#first serial, iclass 4, count 0 2006.162.07:51:54.95#ibcon#enter sib2, iclass 4, count 0 2006.162.07:51:54.95#ibcon#flushed, iclass 4, count 0 2006.162.07:51:54.95#ibcon#about to write, iclass 4, count 0 2006.162.07:51:54.95#ibcon#wrote, iclass 4, count 0 2006.162.07:51:54.95#ibcon#about to read 3, iclass 4, count 0 2006.162.07:51:54.97#ibcon#read 3, iclass 4, count 0 2006.162.07:51:54.97#ibcon#about to read 4, iclass 4, count 0 2006.162.07:51:54.97#ibcon#read 4, iclass 4, count 0 2006.162.07:51:54.97#ibcon#about to read 5, iclass 4, count 0 2006.162.07:51:54.97#ibcon#read 5, iclass 4, count 0 2006.162.07:51:54.97#ibcon#about to read 6, iclass 4, count 0 2006.162.07:51:54.97#ibcon#read 6, iclass 4, count 0 2006.162.07:51:54.97#ibcon#end of sib2, iclass 4, count 0 2006.162.07:51:54.97#ibcon#*mode == 0, iclass 4, count 0 2006.162.07:51:54.97#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.162.07:51:54.97#ibcon#[27=USB\r\n] 2006.162.07:51:54.97#ibcon#*before write, iclass 4, count 0 2006.162.07:51:54.97#ibcon#enter sib2, iclass 4, count 0 2006.162.07:51:54.97#ibcon#flushed, iclass 4, count 0 2006.162.07:51:54.97#ibcon#about to write, iclass 4, count 0 2006.162.07:51:54.97#ibcon#wrote, iclass 4, count 0 2006.162.07:51:54.97#ibcon#about to read 3, iclass 4, count 0 2006.162.07:51:55.00#ibcon#read 3, iclass 4, count 0 2006.162.07:51:55.00#ibcon#about to read 4, iclass 4, count 0 2006.162.07:51:55.00#ibcon#read 4, iclass 4, count 0 2006.162.07:51:55.00#ibcon#about to read 5, iclass 4, count 0 2006.162.07:51:55.00#ibcon#read 5, iclass 4, count 0 2006.162.07:51:55.00#ibcon#about to read 6, iclass 4, count 0 2006.162.07:51:55.00#ibcon#read 6, iclass 4, count 0 2006.162.07:51:55.00#ibcon#end of sib2, iclass 4, count 0 2006.162.07:51:55.00#ibcon#*after write, iclass 4, count 0 2006.162.07:51:55.00#ibcon#*before return 0, iclass 4, count 0 2006.162.07:51:55.00#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:51:55.00#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.162.07:51:55.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.162.07:51:55.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.162.07:51:55.00$vc4f8/vabw=wide 2006.162.07:51:55.00#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.162.07:51:55.00#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.162.07:51:55.00#ibcon#ireg 8 cls_cnt 0 2006.162.07:51:55.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:51:55.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:51:55.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:51:55.00#ibcon#enter wrdev, iclass 6, count 0 2006.162.07:51:55.00#ibcon#first serial, iclass 6, count 0 2006.162.07:51:55.00#ibcon#enter sib2, iclass 6, count 0 2006.162.07:51:55.00#ibcon#flushed, iclass 6, count 0 2006.162.07:51:55.00#ibcon#about to write, iclass 6, count 0 2006.162.07:51:55.00#ibcon#wrote, iclass 6, count 0 2006.162.07:51:55.00#ibcon#about to read 3, iclass 6, count 0 2006.162.07:51:55.02#ibcon#read 3, iclass 6, count 0 2006.162.07:51:55.02#ibcon#about to read 4, iclass 6, count 0 2006.162.07:51:55.02#ibcon#read 4, iclass 6, count 0 2006.162.07:51:55.02#ibcon#about to read 5, iclass 6, count 0 2006.162.07:51:55.02#ibcon#read 5, iclass 6, count 0 2006.162.07:51:55.02#ibcon#about to read 6, iclass 6, count 0 2006.162.07:51:55.02#ibcon#read 6, iclass 6, count 0 2006.162.07:51:55.02#ibcon#end of sib2, iclass 6, count 0 2006.162.07:51:55.02#ibcon#*mode == 0, iclass 6, count 0 2006.162.07:51:55.02#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.162.07:51:55.02#ibcon#[25=BW32\r\n] 2006.162.07:51:55.02#ibcon#*before write, iclass 6, count 0 2006.162.07:51:55.02#ibcon#enter sib2, iclass 6, count 0 2006.162.07:51:55.02#ibcon#flushed, iclass 6, count 0 2006.162.07:51:55.02#ibcon#about to write, iclass 6, count 0 2006.162.07:51:55.02#ibcon#wrote, iclass 6, count 0 2006.162.07:51:55.02#ibcon#about to read 3, iclass 6, count 0 2006.162.07:51:55.05#ibcon#read 3, iclass 6, count 0 2006.162.07:51:55.05#ibcon#about to read 4, iclass 6, count 0 2006.162.07:51:55.05#ibcon#read 4, iclass 6, count 0 2006.162.07:51:55.05#ibcon#about to read 5, iclass 6, count 0 2006.162.07:51:55.05#ibcon#read 5, iclass 6, count 0 2006.162.07:51:55.05#ibcon#about to read 6, iclass 6, count 0 2006.162.07:51:55.05#ibcon#read 6, iclass 6, count 0 2006.162.07:51:55.05#ibcon#end of sib2, iclass 6, count 0 2006.162.07:51:55.05#ibcon#*after write, iclass 6, count 0 2006.162.07:51:55.05#ibcon#*before return 0, iclass 6, count 0 2006.162.07:51:55.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:51:55.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.162.07:51:55.05#ibcon#about to clear, iclass 6 cls_cnt 0 2006.162.07:51:55.05#ibcon#cleared, iclass 6 cls_cnt 0 2006.162.07:51:55.05$vc4f8/vbbw=wide 2006.162.07:51:55.05#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.162.07:51:55.05#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.162.07:51:55.05#ibcon#ireg 8 cls_cnt 0 2006.162.07:51:55.05#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.162.07:51:55.12#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.162.07:51:55.12#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.162.07:51:55.12#ibcon#enter wrdev, iclass 10, count 0 2006.162.07:51:55.12#ibcon#first serial, iclass 10, count 0 2006.162.07:51:55.12#ibcon#enter sib2, iclass 10, count 0 2006.162.07:51:55.12#ibcon#flushed, iclass 10, count 0 2006.162.07:51:55.12#ibcon#about to write, iclass 10, count 0 2006.162.07:51:55.12#ibcon#wrote, iclass 10, count 0 2006.162.07:51:55.12#ibcon#about to read 3, iclass 10, count 0 2006.162.07:51:55.14#ibcon#read 3, iclass 10, count 0 2006.162.07:51:55.14#ibcon#about to read 4, iclass 10, count 0 2006.162.07:51:55.14#ibcon#read 4, iclass 10, count 0 2006.162.07:51:55.14#ibcon#about to read 5, iclass 10, count 0 2006.162.07:51:55.14#ibcon#read 5, iclass 10, count 0 2006.162.07:51:55.14#ibcon#about to read 6, iclass 10, count 0 2006.162.07:51:55.14#ibcon#read 6, iclass 10, count 0 2006.162.07:51:55.14#ibcon#end of sib2, iclass 10, count 0 2006.162.07:51:55.14#ibcon#*mode == 0, iclass 10, count 0 2006.162.07:51:55.14#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.162.07:51:55.14#ibcon#[27=BW32\r\n] 2006.162.07:51:55.14#ibcon#*before write, iclass 10, count 0 2006.162.07:51:55.14#ibcon#enter sib2, iclass 10, count 0 2006.162.07:51:55.14#ibcon#flushed, iclass 10, count 0 2006.162.07:51:55.14#ibcon#about to write, iclass 10, count 0 2006.162.07:51:55.14#ibcon#wrote, iclass 10, count 0 2006.162.07:51:55.14#ibcon#about to read 3, iclass 10, count 0 2006.162.07:51:55.17#ibcon#read 3, iclass 10, count 0 2006.162.07:51:55.17#ibcon#about to read 4, iclass 10, count 0 2006.162.07:51:55.17#ibcon#read 4, iclass 10, count 0 2006.162.07:51:55.17#ibcon#about to read 5, iclass 10, count 0 2006.162.07:51:55.17#ibcon#read 5, iclass 10, count 0 2006.162.07:51:55.17#ibcon#about to read 6, iclass 10, count 0 2006.162.07:51:55.17#ibcon#read 6, iclass 10, count 0 2006.162.07:51:55.17#ibcon#end of sib2, iclass 10, count 0 2006.162.07:51:55.17#ibcon#*after write, iclass 10, count 0 2006.162.07:51:55.17#ibcon#*before return 0, iclass 10, count 0 2006.162.07:51:55.17#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.162.07:51:55.17#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.162.07:51:55.17#ibcon#about to clear, iclass 10 cls_cnt 0 2006.162.07:51:55.17#ibcon#cleared, iclass 10 cls_cnt 0 2006.162.07:51:55.17$4f8m12a/ifd4f 2006.162.07:51:55.17$ifd4f/lo= 2006.162.07:51:55.17$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.07:51:55.17$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.07:51:55.17$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.07:51:55.17$ifd4f/patch= 2006.162.07:51:55.17$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.07:51:55.17$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.07:51:55.17$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.07:51:55.17$4f8m12a/"form=m,16.000,1:2 2006.162.07:51:55.17$4f8m12a/"tpicd 2006.162.07:51:55.17$4f8m12a/echo=off 2006.162.07:51:55.17$4f8m12a/xlog=off 2006.162.07:51:55.17:!2006.162.07:53:20 2006.162.07:52:06.14#trakl#Source acquired 2006.162.07:52:08.14#flagr#flagr/antenna,acquired 2006.162.07:53:20.02:preob 2006.162.07:53:21.15/onsource/TRACKING 2006.162.07:53:21.15:!2006.162.07:53:30 2006.162.07:53:30.02:data_valid=on 2006.162.07:53:30.02:midob 2006.162.07:53:31.15/onsource/TRACKING 2006.162.07:53:31.15/wx/17.85,1007.2,100 2006.162.07:53:31.32/cable/+6.5372E-03 2006.162.07:53:32.41/va/01,08,usb,yes,38,40 2006.162.07:53:32.41/va/02,07,usb,yes,39,40 2006.162.07:53:32.41/va/03,06,usb,yes,41,41 2006.162.07:53:32.41/va/04,07,usb,yes,40,42 2006.162.07:53:32.41/va/05,07,usb,yes,42,45 2006.162.07:53:32.41/va/06,06,usb,yes,42,41 2006.162.07:53:32.41/va/07,06,usb,yes,42,42 2006.162.07:53:32.41/va/08,07,usb,yes,40,39 2006.162.07:53:32.64/valo/01,532.99,yes,locked 2006.162.07:53:32.64/valo/02,572.99,yes,locked 2006.162.07:53:32.64/valo/03,672.99,yes,locked 2006.162.07:53:32.64/valo/04,832.99,yes,locked 2006.162.07:53:32.64/valo/05,652.99,yes,locked 2006.162.07:53:32.65/valo/06,772.99,yes,locked 2006.162.07:53:32.65/valo/07,832.99,yes,locked 2006.162.07:53:32.65/valo/08,852.99,yes,locked 2006.162.07:53:33.73/vb/01,04,usb,yes,29,28 2006.162.07:53:33.73/vb/02,04,usb,yes,31,33 2006.162.07:53:33.73/vb/03,04,usb,yes,27,31 2006.162.07:53:33.73/vb/04,04,usb,yes,28,29 2006.162.07:53:33.73/vb/05,04,usb,yes,27,31 2006.162.07:53:33.73/vb/06,04,usb,yes,28,30 2006.162.07:53:33.73/vb/07,04,usb,yes,30,30 2006.162.07:53:33.73/vb/08,04,usb,yes,27,31 2006.162.07:53:33.97/vblo/01,632.99,yes,locked 2006.162.07:53:33.97/vblo/02,640.99,yes,locked 2006.162.07:53:33.97/vblo/03,656.99,yes,locked 2006.162.07:53:33.97/vblo/04,712.99,yes,locked 2006.162.07:53:33.97/vblo/05,744.99,yes,locked 2006.162.07:53:33.98/vblo/06,752.99,yes,locked 2006.162.07:53:33.98/vblo/07,734.99,yes,locked 2006.162.07:53:33.98/vblo/08,744.99,yes,locked 2006.162.07:53:34.12/vabw/8 2006.162.07:53:34.27/vbbw/8 2006.162.07:53:34.36/xfe/off,on,15.5 2006.162.07:53:34.74/ifatt/23,28,28,28 2006.162.07:53:35.06/fmout-gps/S +4.47E-07 2006.162.07:53:35.14:!2006.162.07:54:30 2006.162.07:54:30.02:data_valid=off 2006.162.07:54:30.02:postob 2006.162.07:54:30.21/cable/+6.5359E-03 2006.162.07:54:30.22/wx/17.84,1007.1,100 2006.162.07:54:31.07/fmout-gps/S +4.48E-07 2006.162.07:54:31.08:scan_name=162-0757,k06162,60 2006.162.07:54:31.08:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.162.07:54:32.15#flagr#flagr/antenna,new-source 2006.162.07:54:32.15:checkk5 2006.162.07:54:32.59/chk_autoobs//k5ts1/ autoobs is running! 2006.162.07:54:33.01/chk_autoobs//k5ts2/ autoobs is running! 2006.162.07:54:33.47/chk_autoobs//k5ts3/ autoobs is running! 2006.162.07:54:33.90/chk_autoobs//k5ts4/ autoobs is running! 2006.162.07:54:34.33/chk_obsdata//k5ts1/T1620753??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.162.07:54:34.74/chk_obsdata//k5ts2/T1620753??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.162.07:54:35.17/chk_obsdata//k5ts3/T1620753??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.162.07:54:35.58/chk_obsdata//k5ts4/T1620753??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.162.07:54:36.34/k5log//k5ts1_log_newline 2006.162.07:54:37.72/k5log//k5ts2_log_newline 2006.162.07:54:38.50/k5log//k5ts3_log_newline 2006.162.07:54:39.35/k5log//k5ts4_log_newline 2006.162.07:54:39.37/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.07:54:39.37:4f8m12a=2 2006.162.07:54:39.37$4f8m12a/echo=on 2006.162.07:54:39.37$4f8m12a/pcalon 2006.162.07:54:39.37$pcalon/"no phase cal control is implemented here 2006.162.07:54:39.37$4f8m12a/"tpicd=stop 2006.162.07:54:39.37$4f8m12a/vc4f8 2006.162.07:54:39.37$vc4f8/valo=1,532.99 2006.162.07:54:39.37#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.162.07:54:39.37#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.162.07:54:39.37#ibcon#ireg 17 cls_cnt 0 2006.162.07:54:39.37#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.162.07:54:39.37#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.162.07:54:39.37#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.162.07:54:39.37#ibcon#enter wrdev, iclass 3, count 0 2006.162.07:54:39.37#ibcon#first serial, iclass 3, count 0 2006.162.07:54:39.37#ibcon#enter sib2, iclass 3, count 0 2006.162.07:54:39.37#ibcon#flushed, iclass 3, count 0 2006.162.07:54:39.37#ibcon#about to write, iclass 3, count 0 2006.162.07:54:39.38#ibcon#wrote, iclass 3, count 0 2006.162.07:54:39.38#ibcon#about to read 3, iclass 3, count 0 2006.162.07:54:39.42#ibcon#read 3, iclass 3, count 0 2006.162.07:54:39.42#ibcon#about to read 4, iclass 3, count 0 2006.162.07:54:39.42#ibcon#read 4, iclass 3, count 0 2006.162.07:54:39.42#ibcon#about to read 5, iclass 3, count 0 2006.162.07:54:39.42#ibcon#read 5, iclass 3, count 0 2006.162.07:54:39.42#ibcon#about to read 6, iclass 3, count 0 2006.162.07:54:39.42#ibcon#read 6, iclass 3, count 0 2006.162.07:54:39.42#ibcon#end of sib2, iclass 3, count 0 2006.162.07:54:39.42#ibcon#*mode == 0, iclass 3, count 0 2006.162.07:54:39.42#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.162.07:54:39.42#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.07:54:39.42#ibcon#*before write, iclass 3, count 0 2006.162.07:54:39.42#ibcon#enter sib2, iclass 3, count 0 2006.162.07:54:39.42#ibcon#flushed, iclass 3, count 0 2006.162.07:54:39.42#ibcon#about to write, iclass 3, count 0 2006.162.07:54:39.42#ibcon#wrote, iclass 3, count 0 2006.162.07:54:39.42#ibcon#about to read 3, iclass 3, count 0 2006.162.07:54:39.46#ibcon#read 3, iclass 3, count 0 2006.162.07:54:39.46#ibcon#about to read 4, iclass 3, count 0 2006.162.07:54:39.46#ibcon#read 4, iclass 3, count 0 2006.162.07:54:39.46#ibcon#about to read 5, iclass 3, count 0 2006.162.07:54:39.46#ibcon#read 5, iclass 3, count 0 2006.162.07:54:39.46#ibcon#about to read 6, iclass 3, count 0 2006.162.07:54:39.46#ibcon#read 6, iclass 3, count 0 2006.162.07:54:39.46#ibcon#end of sib2, iclass 3, count 0 2006.162.07:54:39.46#ibcon#*after write, iclass 3, count 0 2006.162.07:54:39.46#ibcon#*before return 0, iclass 3, count 0 2006.162.07:54:39.46#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.162.07:54:39.46#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.162.07:54:39.46#ibcon#about to clear, iclass 3 cls_cnt 0 2006.162.07:54:39.46#ibcon#cleared, iclass 3 cls_cnt 0 2006.162.07:54:39.47$vc4f8/va=1,8 2006.162.07:54:39.47#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.162.07:54:39.47#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.162.07:54:39.47#ibcon#ireg 11 cls_cnt 2 2006.162.07:54:39.47#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.162.07:54:39.47#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.162.07:54:39.47#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.162.07:54:39.47#ibcon#enter wrdev, iclass 5, count 2 2006.162.07:54:39.47#ibcon#first serial, iclass 5, count 2 2006.162.07:54:39.47#ibcon#enter sib2, iclass 5, count 2 2006.162.07:54:39.47#ibcon#flushed, iclass 5, count 2 2006.162.07:54:39.47#ibcon#about to write, iclass 5, count 2 2006.162.07:54:39.47#ibcon#wrote, iclass 5, count 2 2006.162.07:54:39.47#ibcon#about to read 3, iclass 5, count 2 2006.162.07:54:39.49#ibcon#read 3, iclass 5, count 2 2006.162.07:54:39.49#ibcon#about to read 4, iclass 5, count 2 2006.162.07:54:39.49#ibcon#read 4, iclass 5, count 2 2006.162.07:54:39.49#ibcon#about to read 5, iclass 5, count 2 2006.162.07:54:39.49#ibcon#read 5, iclass 5, count 2 2006.162.07:54:39.49#ibcon#about to read 6, iclass 5, count 2 2006.162.07:54:39.49#ibcon#read 6, iclass 5, count 2 2006.162.07:54:39.49#ibcon#end of sib2, iclass 5, count 2 2006.162.07:54:39.49#ibcon#*mode == 0, iclass 5, count 2 2006.162.07:54:39.49#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.162.07:54:39.49#ibcon#[25=AT01-08\r\n] 2006.162.07:54:39.49#ibcon#*before write, iclass 5, count 2 2006.162.07:54:39.49#ibcon#enter sib2, iclass 5, count 2 2006.162.07:54:39.49#ibcon#flushed, iclass 5, count 2 2006.162.07:54:39.49#ibcon#about to write, iclass 5, count 2 2006.162.07:54:39.49#ibcon#wrote, iclass 5, count 2 2006.162.07:54:39.49#ibcon#about to read 3, iclass 5, count 2 2006.162.07:54:39.53#ibcon#read 3, iclass 5, count 2 2006.162.07:54:39.53#ibcon#about to read 4, iclass 5, count 2 2006.162.07:54:39.53#ibcon#read 4, iclass 5, count 2 2006.162.07:54:39.53#ibcon#about to read 5, iclass 5, count 2 2006.162.07:54:39.53#ibcon#read 5, iclass 5, count 2 2006.162.07:54:39.53#ibcon#about to read 6, iclass 5, count 2 2006.162.07:54:39.53#ibcon#read 6, iclass 5, count 2 2006.162.07:54:39.53#ibcon#end of sib2, iclass 5, count 2 2006.162.07:54:39.53#ibcon#*after write, iclass 5, count 2 2006.162.07:54:39.53#ibcon#*before return 0, iclass 5, count 2 2006.162.07:54:39.53#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.162.07:54:39.53#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.162.07:54:39.53#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.162.07:54:39.53#ibcon#ireg 7 cls_cnt 0 2006.162.07:54:39.53#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.162.07:54:39.64#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.162.07:54:39.64#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.162.07:54:39.64#ibcon#enter wrdev, iclass 5, count 0 2006.162.07:54:39.64#ibcon#first serial, iclass 5, count 0 2006.162.07:54:39.64#ibcon#enter sib2, iclass 5, count 0 2006.162.07:54:39.64#ibcon#flushed, iclass 5, count 0 2006.162.07:54:39.64#ibcon#about to write, iclass 5, count 0 2006.162.07:54:39.64#ibcon#wrote, iclass 5, count 0 2006.162.07:54:39.64#ibcon#about to read 3, iclass 5, count 0 2006.162.07:54:39.66#ibcon#read 3, iclass 5, count 0 2006.162.07:54:39.66#ibcon#about to read 4, iclass 5, count 0 2006.162.07:54:39.66#ibcon#read 4, iclass 5, count 0 2006.162.07:54:39.66#ibcon#about to read 5, iclass 5, count 0 2006.162.07:54:39.66#ibcon#read 5, iclass 5, count 0 2006.162.07:54:39.66#ibcon#about to read 6, iclass 5, count 0 2006.162.07:54:39.66#ibcon#read 6, iclass 5, count 0 2006.162.07:54:39.66#ibcon#end of sib2, iclass 5, count 0 2006.162.07:54:39.66#ibcon#*mode == 0, iclass 5, count 0 2006.162.07:54:39.66#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.162.07:54:39.66#ibcon#[25=USB\r\n] 2006.162.07:54:39.66#ibcon#*before write, iclass 5, count 0 2006.162.07:54:39.66#ibcon#enter sib2, iclass 5, count 0 2006.162.07:54:39.66#ibcon#flushed, iclass 5, count 0 2006.162.07:54:39.66#ibcon#about to write, iclass 5, count 0 2006.162.07:54:39.66#ibcon#wrote, iclass 5, count 0 2006.162.07:54:39.66#ibcon#about to read 3, iclass 5, count 0 2006.162.07:54:39.69#ibcon#read 3, iclass 5, count 0 2006.162.07:54:39.69#ibcon#about to read 4, iclass 5, count 0 2006.162.07:54:39.69#ibcon#read 4, iclass 5, count 0 2006.162.07:54:39.69#ibcon#about to read 5, iclass 5, count 0 2006.162.07:54:39.69#ibcon#read 5, iclass 5, count 0 2006.162.07:54:39.69#ibcon#about to read 6, iclass 5, count 0 2006.162.07:54:39.69#ibcon#read 6, iclass 5, count 0 2006.162.07:54:39.69#ibcon#end of sib2, iclass 5, count 0 2006.162.07:54:39.69#ibcon#*after write, iclass 5, count 0 2006.162.07:54:39.69#ibcon#*before return 0, iclass 5, count 0 2006.162.07:54:39.69#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.162.07:54:39.69#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.162.07:54:39.69#ibcon#about to clear, iclass 5 cls_cnt 0 2006.162.07:54:39.69#ibcon#cleared, iclass 5 cls_cnt 0 2006.162.07:54:39.70$vc4f8/valo=2,572.99 2006.162.07:54:39.70#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.162.07:54:39.70#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.162.07:54:39.70#ibcon#ireg 17 cls_cnt 0 2006.162.07:54:39.70#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:54:39.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:54:39.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:54:39.70#ibcon#enter wrdev, iclass 7, count 0 2006.162.07:54:39.70#ibcon#first serial, iclass 7, count 0 2006.162.07:54:39.70#ibcon#enter sib2, iclass 7, count 0 2006.162.07:54:39.70#ibcon#flushed, iclass 7, count 0 2006.162.07:54:39.70#ibcon#about to write, iclass 7, count 0 2006.162.07:54:39.70#ibcon#wrote, iclass 7, count 0 2006.162.07:54:39.70#ibcon#about to read 3, iclass 7, count 0 2006.162.07:54:39.72#ibcon#read 3, iclass 7, count 0 2006.162.07:54:39.72#ibcon#about to read 4, iclass 7, count 0 2006.162.07:54:39.72#ibcon#read 4, iclass 7, count 0 2006.162.07:54:39.72#ibcon#about to read 5, iclass 7, count 0 2006.162.07:54:39.72#ibcon#read 5, iclass 7, count 0 2006.162.07:54:39.72#ibcon#about to read 6, iclass 7, count 0 2006.162.07:54:39.72#ibcon#read 6, iclass 7, count 0 2006.162.07:54:39.72#ibcon#end of sib2, iclass 7, count 0 2006.162.07:54:39.72#ibcon#*mode == 0, iclass 7, count 0 2006.162.07:54:39.72#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.162.07:54:39.72#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.07:54:39.72#ibcon#*before write, iclass 7, count 0 2006.162.07:54:39.72#ibcon#enter sib2, iclass 7, count 0 2006.162.07:54:39.72#ibcon#flushed, iclass 7, count 0 2006.162.07:54:39.72#ibcon#about to write, iclass 7, count 0 2006.162.07:54:39.72#ibcon#wrote, iclass 7, count 0 2006.162.07:54:39.72#ibcon#about to read 3, iclass 7, count 0 2006.162.07:54:39.76#ibcon#read 3, iclass 7, count 0 2006.162.07:54:39.76#ibcon#about to read 4, iclass 7, count 0 2006.162.07:54:39.76#ibcon#read 4, iclass 7, count 0 2006.162.07:54:39.76#ibcon#about to read 5, iclass 7, count 0 2006.162.07:54:39.76#ibcon#read 5, iclass 7, count 0 2006.162.07:54:39.76#ibcon#about to read 6, iclass 7, count 0 2006.162.07:54:39.76#ibcon#read 6, iclass 7, count 0 2006.162.07:54:39.76#ibcon#end of sib2, iclass 7, count 0 2006.162.07:54:39.76#ibcon#*after write, iclass 7, count 0 2006.162.07:54:39.76#ibcon#*before return 0, iclass 7, count 0 2006.162.07:54:39.76#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:54:39.76#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:54:39.76#ibcon#about to clear, iclass 7 cls_cnt 0 2006.162.07:54:39.76#ibcon#cleared, iclass 7 cls_cnt 0 2006.162.07:54:39.76$vc4f8/va=2,7 2006.162.07:54:39.77#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.162.07:54:39.77#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.162.07:54:39.77#ibcon#ireg 11 cls_cnt 2 2006.162.07:54:39.77#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:54:39.80#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:54:39.80#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:54:39.80#ibcon#enter wrdev, iclass 11, count 2 2006.162.07:54:39.80#ibcon#first serial, iclass 11, count 2 2006.162.07:54:39.80#ibcon#enter sib2, iclass 11, count 2 2006.162.07:54:39.80#ibcon#flushed, iclass 11, count 2 2006.162.07:54:39.80#ibcon#about to write, iclass 11, count 2 2006.162.07:54:39.80#ibcon#wrote, iclass 11, count 2 2006.162.07:54:39.80#ibcon#about to read 3, iclass 11, count 2 2006.162.07:54:39.83#ibcon#read 3, iclass 11, count 2 2006.162.07:54:39.83#ibcon#about to read 4, iclass 11, count 2 2006.162.07:54:39.83#ibcon#read 4, iclass 11, count 2 2006.162.07:54:39.83#ibcon#about to read 5, iclass 11, count 2 2006.162.07:54:39.83#ibcon#read 5, iclass 11, count 2 2006.162.07:54:39.83#ibcon#about to read 6, iclass 11, count 2 2006.162.07:54:39.83#ibcon#read 6, iclass 11, count 2 2006.162.07:54:39.83#ibcon#end of sib2, iclass 11, count 2 2006.162.07:54:39.83#ibcon#*mode == 0, iclass 11, count 2 2006.162.07:54:39.83#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.162.07:54:39.83#ibcon#[25=AT02-07\r\n] 2006.162.07:54:39.83#ibcon#*before write, iclass 11, count 2 2006.162.07:54:39.83#ibcon#enter sib2, iclass 11, count 2 2006.162.07:54:39.83#ibcon#flushed, iclass 11, count 2 2006.162.07:54:39.83#ibcon#about to write, iclass 11, count 2 2006.162.07:54:39.83#ibcon#wrote, iclass 11, count 2 2006.162.07:54:39.83#ibcon#about to read 3, iclass 11, count 2 2006.162.07:54:39.86#ibcon#read 3, iclass 11, count 2 2006.162.07:54:39.86#ibcon#about to read 4, iclass 11, count 2 2006.162.07:54:39.86#ibcon#read 4, iclass 11, count 2 2006.162.07:54:39.86#ibcon#about to read 5, iclass 11, count 2 2006.162.07:54:39.86#ibcon#read 5, iclass 11, count 2 2006.162.07:54:39.86#ibcon#about to read 6, iclass 11, count 2 2006.162.07:54:39.86#ibcon#read 6, iclass 11, count 2 2006.162.07:54:39.86#ibcon#end of sib2, iclass 11, count 2 2006.162.07:54:39.86#ibcon#*after write, iclass 11, count 2 2006.162.07:54:39.86#ibcon#*before return 0, iclass 11, count 2 2006.162.07:54:39.86#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:54:39.86#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:54:39.86#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.162.07:54:39.86#ibcon#ireg 7 cls_cnt 0 2006.162.07:54:39.86#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:54:39.98#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:54:39.98#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:54:39.98#ibcon#enter wrdev, iclass 11, count 0 2006.162.07:54:39.98#ibcon#first serial, iclass 11, count 0 2006.162.07:54:39.98#ibcon#enter sib2, iclass 11, count 0 2006.162.07:54:39.98#ibcon#flushed, iclass 11, count 0 2006.162.07:54:39.98#ibcon#about to write, iclass 11, count 0 2006.162.07:54:39.98#ibcon#wrote, iclass 11, count 0 2006.162.07:54:39.98#ibcon#about to read 3, iclass 11, count 0 2006.162.07:54:40.00#ibcon#read 3, iclass 11, count 0 2006.162.07:54:40.00#ibcon#about to read 4, iclass 11, count 0 2006.162.07:54:40.00#ibcon#read 4, iclass 11, count 0 2006.162.07:54:40.00#ibcon#about to read 5, iclass 11, count 0 2006.162.07:54:40.00#ibcon#read 5, iclass 11, count 0 2006.162.07:54:40.00#ibcon#about to read 6, iclass 11, count 0 2006.162.07:54:40.00#ibcon#read 6, iclass 11, count 0 2006.162.07:54:40.00#ibcon#end of sib2, iclass 11, count 0 2006.162.07:54:40.00#ibcon#*mode == 0, iclass 11, count 0 2006.162.07:54:40.00#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.162.07:54:40.00#ibcon#[25=USB\r\n] 2006.162.07:54:40.00#ibcon#*before write, iclass 11, count 0 2006.162.07:54:40.00#ibcon#enter sib2, iclass 11, count 0 2006.162.07:54:40.00#ibcon#flushed, iclass 11, count 0 2006.162.07:54:40.00#ibcon#about to write, iclass 11, count 0 2006.162.07:54:40.00#ibcon#wrote, iclass 11, count 0 2006.162.07:54:40.00#ibcon#about to read 3, iclass 11, count 0 2006.162.07:54:40.03#ibcon#read 3, iclass 11, count 0 2006.162.07:54:40.03#ibcon#about to read 4, iclass 11, count 0 2006.162.07:54:40.03#ibcon#read 4, iclass 11, count 0 2006.162.07:54:40.03#ibcon#about to read 5, iclass 11, count 0 2006.162.07:54:40.03#ibcon#read 5, iclass 11, count 0 2006.162.07:54:40.03#ibcon#about to read 6, iclass 11, count 0 2006.162.07:54:40.03#ibcon#read 6, iclass 11, count 0 2006.162.07:54:40.03#ibcon#end of sib2, iclass 11, count 0 2006.162.07:54:40.03#ibcon#*after write, iclass 11, count 0 2006.162.07:54:40.03#ibcon#*before return 0, iclass 11, count 0 2006.162.07:54:40.03#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:54:40.03#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:54:40.03#ibcon#about to clear, iclass 11 cls_cnt 0 2006.162.07:54:40.03#ibcon#cleared, iclass 11 cls_cnt 0 2006.162.07:54:40.03$vc4f8/valo=3,672.99 2006.162.07:54:40.04#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.162.07:54:40.04#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.162.07:54:40.04#ibcon#ireg 17 cls_cnt 0 2006.162.07:54:40.04#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:54:40.04#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:54:40.04#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:54:40.04#ibcon#enter wrdev, iclass 13, count 0 2006.162.07:54:40.04#ibcon#first serial, iclass 13, count 0 2006.162.07:54:40.04#ibcon#enter sib2, iclass 13, count 0 2006.162.07:54:40.04#ibcon#flushed, iclass 13, count 0 2006.162.07:54:40.04#ibcon#about to write, iclass 13, count 0 2006.162.07:54:40.04#ibcon#wrote, iclass 13, count 0 2006.162.07:54:40.04#ibcon#about to read 3, iclass 13, count 0 2006.162.07:54:40.05#ibcon#read 3, iclass 13, count 0 2006.162.07:54:40.05#ibcon#about to read 4, iclass 13, count 0 2006.162.07:54:40.05#ibcon#read 4, iclass 13, count 0 2006.162.07:54:40.05#ibcon#about to read 5, iclass 13, count 0 2006.162.07:54:40.05#ibcon#read 5, iclass 13, count 0 2006.162.07:54:40.05#ibcon#about to read 6, iclass 13, count 0 2006.162.07:54:40.05#ibcon#read 6, iclass 13, count 0 2006.162.07:54:40.05#ibcon#end of sib2, iclass 13, count 0 2006.162.07:54:40.05#ibcon#*mode == 0, iclass 13, count 0 2006.162.07:54:40.05#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.162.07:54:40.05#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.07:54:40.05#ibcon#*before write, iclass 13, count 0 2006.162.07:54:40.05#ibcon#enter sib2, iclass 13, count 0 2006.162.07:54:40.05#ibcon#flushed, iclass 13, count 0 2006.162.07:54:40.05#ibcon#about to write, iclass 13, count 0 2006.162.07:54:40.05#ibcon#wrote, iclass 13, count 0 2006.162.07:54:40.05#ibcon#about to read 3, iclass 13, count 0 2006.162.07:54:40.10#ibcon#read 3, iclass 13, count 0 2006.162.07:54:40.10#ibcon#about to read 4, iclass 13, count 0 2006.162.07:54:40.10#ibcon#read 4, iclass 13, count 0 2006.162.07:54:40.10#ibcon#about to read 5, iclass 13, count 0 2006.162.07:54:40.10#ibcon#read 5, iclass 13, count 0 2006.162.07:54:40.10#ibcon#about to read 6, iclass 13, count 0 2006.162.07:54:40.10#ibcon#read 6, iclass 13, count 0 2006.162.07:54:40.10#ibcon#end of sib2, iclass 13, count 0 2006.162.07:54:40.10#ibcon#*after write, iclass 13, count 0 2006.162.07:54:40.10#ibcon#*before return 0, iclass 13, count 0 2006.162.07:54:40.10#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:54:40.10#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:54:40.10#ibcon#about to clear, iclass 13 cls_cnt 0 2006.162.07:54:40.10#ibcon#cleared, iclass 13 cls_cnt 0 2006.162.07:54:40.10$vc4f8/va=3,6 2006.162.07:54:40.10#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.162.07:54:40.10#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.162.07:54:40.10#ibcon#ireg 11 cls_cnt 2 2006.162.07:54:40.10#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:54:40.15#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:54:40.15#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:54:40.15#ibcon#enter wrdev, iclass 15, count 2 2006.162.07:54:40.15#ibcon#first serial, iclass 15, count 2 2006.162.07:54:40.15#ibcon#enter sib2, iclass 15, count 2 2006.162.07:54:40.15#ibcon#flushed, iclass 15, count 2 2006.162.07:54:40.15#ibcon#about to write, iclass 15, count 2 2006.162.07:54:40.15#ibcon#wrote, iclass 15, count 2 2006.162.07:54:40.15#ibcon#about to read 3, iclass 15, count 2 2006.162.07:54:40.16#ibcon#read 3, iclass 15, count 2 2006.162.07:54:40.16#ibcon#about to read 4, iclass 15, count 2 2006.162.07:54:40.16#ibcon#read 4, iclass 15, count 2 2006.162.07:54:40.16#ibcon#about to read 5, iclass 15, count 2 2006.162.07:54:40.16#ibcon#read 5, iclass 15, count 2 2006.162.07:54:40.16#ibcon#about to read 6, iclass 15, count 2 2006.162.07:54:40.16#ibcon#read 6, iclass 15, count 2 2006.162.07:54:40.16#ibcon#end of sib2, iclass 15, count 2 2006.162.07:54:40.16#ibcon#*mode == 0, iclass 15, count 2 2006.162.07:54:40.16#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.162.07:54:40.16#ibcon#[25=AT03-06\r\n] 2006.162.07:54:40.16#ibcon#*before write, iclass 15, count 2 2006.162.07:54:40.16#ibcon#enter sib2, iclass 15, count 2 2006.162.07:54:40.16#ibcon#flushed, iclass 15, count 2 2006.162.07:54:40.16#ibcon#about to write, iclass 15, count 2 2006.162.07:54:40.16#ibcon#wrote, iclass 15, count 2 2006.162.07:54:40.16#ibcon#about to read 3, iclass 15, count 2 2006.162.07:54:40.19#ibcon#read 3, iclass 15, count 2 2006.162.07:54:40.19#ibcon#about to read 4, iclass 15, count 2 2006.162.07:54:40.19#ibcon#read 4, iclass 15, count 2 2006.162.07:54:40.19#ibcon#about to read 5, iclass 15, count 2 2006.162.07:54:40.19#ibcon#read 5, iclass 15, count 2 2006.162.07:54:40.19#ibcon#about to read 6, iclass 15, count 2 2006.162.07:54:40.19#ibcon#read 6, iclass 15, count 2 2006.162.07:54:40.19#ibcon#end of sib2, iclass 15, count 2 2006.162.07:54:40.19#ibcon#*after write, iclass 15, count 2 2006.162.07:54:40.19#ibcon#*before return 0, iclass 15, count 2 2006.162.07:54:40.19#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:54:40.19#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:54:40.19#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.162.07:54:40.19#ibcon#ireg 7 cls_cnt 0 2006.162.07:54:40.19#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:54:40.31#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:54:40.31#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:54:40.31#ibcon#enter wrdev, iclass 15, count 0 2006.162.07:54:40.31#ibcon#first serial, iclass 15, count 0 2006.162.07:54:40.31#ibcon#enter sib2, iclass 15, count 0 2006.162.07:54:40.31#ibcon#flushed, iclass 15, count 0 2006.162.07:54:40.31#ibcon#about to write, iclass 15, count 0 2006.162.07:54:40.31#ibcon#wrote, iclass 15, count 0 2006.162.07:54:40.31#ibcon#about to read 3, iclass 15, count 0 2006.162.07:54:40.33#ibcon#read 3, iclass 15, count 0 2006.162.07:54:40.33#ibcon#about to read 4, iclass 15, count 0 2006.162.07:54:40.33#ibcon#read 4, iclass 15, count 0 2006.162.07:54:40.33#ibcon#about to read 5, iclass 15, count 0 2006.162.07:54:40.33#ibcon#read 5, iclass 15, count 0 2006.162.07:54:40.33#ibcon#about to read 6, iclass 15, count 0 2006.162.07:54:40.33#ibcon#read 6, iclass 15, count 0 2006.162.07:54:40.33#ibcon#end of sib2, iclass 15, count 0 2006.162.07:54:40.33#ibcon#*mode == 0, iclass 15, count 0 2006.162.07:54:40.33#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.162.07:54:40.33#ibcon#[25=USB\r\n] 2006.162.07:54:40.33#ibcon#*before write, iclass 15, count 0 2006.162.07:54:40.33#ibcon#enter sib2, iclass 15, count 0 2006.162.07:54:40.33#ibcon#flushed, iclass 15, count 0 2006.162.07:54:40.33#ibcon#about to write, iclass 15, count 0 2006.162.07:54:40.33#ibcon#wrote, iclass 15, count 0 2006.162.07:54:40.33#ibcon#about to read 3, iclass 15, count 0 2006.162.07:54:40.36#ibcon#read 3, iclass 15, count 0 2006.162.07:54:40.36#ibcon#about to read 4, iclass 15, count 0 2006.162.07:54:40.36#ibcon#read 4, iclass 15, count 0 2006.162.07:54:40.36#ibcon#about to read 5, iclass 15, count 0 2006.162.07:54:40.36#ibcon#read 5, iclass 15, count 0 2006.162.07:54:40.36#ibcon#about to read 6, iclass 15, count 0 2006.162.07:54:40.36#ibcon#read 6, iclass 15, count 0 2006.162.07:54:40.36#ibcon#end of sib2, iclass 15, count 0 2006.162.07:54:40.36#ibcon#*after write, iclass 15, count 0 2006.162.07:54:40.36#ibcon#*before return 0, iclass 15, count 0 2006.162.07:54:40.36#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:54:40.36#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:54:40.36#ibcon#about to clear, iclass 15 cls_cnt 0 2006.162.07:54:40.36#ibcon#cleared, iclass 15 cls_cnt 0 2006.162.07:54:40.37$vc4f8/valo=4,832.99 2006.162.07:54:40.37#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.162.07:54:40.37#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.162.07:54:40.37#ibcon#ireg 17 cls_cnt 0 2006.162.07:54:40.37#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:54:40.37#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:54:40.37#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:54:40.37#ibcon#enter wrdev, iclass 17, count 0 2006.162.07:54:40.37#ibcon#first serial, iclass 17, count 0 2006.162.07:54:40.37#ibcon#enter sib2, iclass 17, count 0 2006.162.07:54:40.37#ibcon#flushed, iclass 17, count 0 2006.162.07:54:40.37#ibcon#about to write, iclass 17, count 0 2006.162.07:54:40.37#ibcon#wrote, iclass 17, count 0 2006.162.07:54:40.37#ibcon#about to read 3, iclass 17, count 0 2006.162.07:54:40.38#ibcon#read 3, iclass 17, count 0 2006.162.07:54:40.38#ibcon#about to read 4, iclass 17, count 0 2006.162.07:54:40.38#ibcon#read 4, iclass 17, count 0 2006.162.07:54:40.38#ibcon#about to read 5, iclass 17, count 0 2006.162.07:54:40.38#ibcon#read 5, iclass 17, count 0 2006.162.07:54:40.38#ibcon#about to read 6, iclass 17, count 0 2006.162.07:54:40.38#ibcon#read 6, iclass 17, count 0 2006.162.07:54:40.38#ibcon#end of sib2, iclass 17, count 0 2006.162.07:54:40.38#ibcon#*mode == 0, iclass 17, count 0 2006.162.07:54:40.38#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.162.07:54:40.38#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.07:54:40.38#ibcon#*before write, iclass 17, count 0 2006.162.07:54:40.38#ibcon#enter sib2, iclass 17, count 0 2006.162.07:54:40.38#ibcon#flushed, iclass 17, count 0 2006.162.07:54:40.38#ibcon#about to write, iclass 17, count 0 2006.162.07:54:40.38#ibcon#wrote, iclass 17, count 0 2006.162.07:54:40.38#ibcon#about to read 3, iclass 17, count 0 2006.162.07:54:40.42#ibcon#read 3, iclass 17, count 0 2006.162.07:54:40.42#ibcon#about to read 4, iclass 17, count 0 2006.162.07:54:40.42#ibcon#read 4, iclass 17, count 0 2006.162.07:54:40.42#ibcon#about to read 5, iclass 17, count 0 2006.162.07:54:40.42#ibcon#read 5, iclass 17, count 0 2006.162.07:54:40.42#ibcon#about to read 6, iclass 17, count 0 2006.162.07:54:40.42#ibcon#read 6, iclass 17, count 0 2006.162.07:54:40.42#ibcon#end of sib2, iclass 17, count 0 2006.162.07:54:40.42#ibcon#*after write, iclass 17, count 0 2006.162.07:54:40.42#ibcon#*before return 0, iclass 17, count 0 2006.162.07:54:40.42#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:54:40.42#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:54:40.42#ibcon#about to clear, iclass 17 cls_cnt 0 2006.162.07:54:40.42#ibcon#cleared, iclass 17 cls_cnt 0 2006.162.07:54:40.42$vc4f8/va=4,7 2006.162.07:54:40.43#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.162.07:54:40.43#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.162.07:54:40.43#ibcon#ireg 11 cls_cnt 2 2006.162.07:54:40.43#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:54:40.47#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:54:40.47#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:54:40.47#ibcon#enter wrdev, iclass 19, count 2 2006.162.07:54:40.47#ibcon#first serial, iclass 19, count 2 2006.162.07:54:40.47#ibcon#enter sib2, iclass 19, count 2 2006.162.07:54:40.47#ibcon#flushed, iclass 19, count 2 2006.162.07:54:40.47#ibcon#about to write, iclass 19, count 2 2006.162.07:54:40.47#ibcon#wrote, iclass 19, count 2 2006.162.07:54:40.47#ibcon#about to read 3, iclass 19, count 2 2006.162.07:54:40.49#ibcon#read 3, iclass 19, count 2 2006.162.07:54:40.49#ibcon#about to read 4, iclass 19, count 2 2006.162.07:54:40.49#ibcon#read 4, iclass 19, count 2 2006.162.07:54:40.49#ibcon#about to read 5, iclass 19, count 2 2006.162.07:54:40.49#ibcon#read 5, iclass 19, count 2 2006.162.07:54:40.49#ibcon#about to read 6, iclass 19, count 2 2006.162.07:54:40.49#ibcon#read 6, iclass 19, count 2 2006.162.07:54:40.49#ibcon#end of sib2, iclass 19, count 2 2006.162.07:54:40.49#ibcon#*mode == 0, iclass 19, count 2 2006.162.07:54:40.49#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.162.07:54:40.49#ibcon#[25=AT04-07\r\n] 2006.162.07:54:40.49#ibcon#*before write, iclass 19, count 2 2006.162.07:54:40.49#ibcon#enter sib2, iclass 19, count 2 2006.162.07:54:40.49#ibcon#flushed, iclass 19, count 2 2006.162.07:54:40.49#ibcon#about to write, iclass 19, count 2 2006.162.07:54:40.49#ibcon#wrote, iclass 19, count 2 2006.162.07:54:40.49#ibcon#about to read 3, iclass 19, count 2 2006.162.07:54:40.52#ibcon#read 3, iclass 19, count 2 2006.162.07:54:40.52#ibcon#about to read 4, iclass 19, count 2 2006.162.07:54:40.52#ibcon#read 4, iclass 19, count 2 2006.162.07:54:40.52#ibcon#about to read 5, iclass 19, count 2 2006.162.07:54:40.52#ibcon#read 5, iclass 19, count 2 2006.162.07:54:40.52#ibcon#about to read 6, iclass 19, count 2 2006.162.07:54:40.52#ibcon#read 6, iclass 19, count 2 2006.162.07:54:40.52#ibcon#end of sib2, iclass 19, count 2 2006.162.07:54:40.52#ibcon#*after write, iclass 19, count 2 2006.162.07:54:40.52#ibcon#*before return 0, iclass 19, count 2 2006.162.07:54:40.52#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:54:40.52#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:54:40.52#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.162.07:54:40.52#ibcon#ireg 7 cls_cnt 0 2006.162.07:54:40.52#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:54:40.64#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:54:40.64#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:54:40.64#ibcon#enter wrdev, iclass 19, count 0 2006.162.07:54:40.64#ibcon#first serial, iclass 19, count 0 2006.162.07:54:40.64#ibcon#enter sib2, iclass 19, count 0 2006.162.07:54:40.64#ibcon#flushed, iclass 19, count 0 2006.162.07:54:40.64#ibcon#about to write, iclass 19, count 0 2006.162.07:54:40.64#ibcon#wrote, iclass 19, count 0 2006.162.07:54:40.64#ibcon#about to read 3, iclass 19, count 0 2006.162.07:54:40.66#ibcon#read 3, iclass 19, count 0 2006.162.07:54:40.66#ibcon#about to read 4, iclass 19, count 0 2006.162.07:54:40.66#ibcon#read 4, iclass 19, count 0 2006.162.07:54:40.66#ibcon#about to read 5, iclass 19, count 0 2006.162.07:54:40.66#ibcon#read 5, iclass 19, count 0 2006.162.07:54:40.66#ibcon#about to read 6, iclass 19, count 0 2006.162.07:54:40.66#ibcon#read 6, iclass 19, count 0 2006.162.07:54:40.66#ibcon#end of sib2, iclass 19, count 0 2006.162.07:54:40.66#ibcon#*mode == 0, iclass 19, count 0 2006.162.07:54:40.66#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.162.07:54:40.66#ibcon#[25=USB\r\n] 2006.162.07:54:40.66#ibcon#*before write, iclass 19, count 0 2006.162.07:54:40.66#ibcon#enter sib2, iclass 19, count 0 2006.162.07:54:40.66#ibcon#flushed, iclass 19, count 0 2006.162.07:54:40.66#ibcon#about to write, iclass 19, count 0 2006.162.07:54:40.66#ibcon#wrote, iclass 19, count 0 2006.162.07:54:40.66#ibcon#about to read 3, iclass 19, count 0 2006.162.07:54:40.69#ibcon#read 3, iclass 19, count 0 2006.162.07:54:40.69#ibcon#about to read 4, iclass 19, count 0 2006.162.07:54:40.69#ibcon#read 4, iclass 19, count 0 2006.162.07:54:40.69#ibcon#about to read 5, iclass 19, count 0 2006.162.07:54:40.69#ibcon#read 5, iclass 19, count 0 2006.162.07:54:40.69#ibcon#about to read 6, iclass 19, count 0 2006.162.07:54:40.69#ibcon#read 6, iclass 19, count 0 2006.162.07:54:40.69#ibcon#end of sib2, iclass 19, count 0 2006.162.07:54:40.69#ibcon#*after write, iclass 19, count 0 2006.162.07:54:40.69#ibcon#*before return 0, iclass 19, count 0 2006.162.07:54:40.69#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:54:40.69#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:54:40.69#ibcon#about to clear, iclass 19 cls_cnt 0 2006.162.07:54:40.69#ibcon#cleared, iclass 19 cls_cnt 0 2006.162.07:54:40.69$vc4f8/valo=5,652.99 2006.162.07:54:40.70#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.162.07:54:40.70#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.162.07:54:40.70#ibcon#ireg 17 cls_cnt 0 2006.162.07:54:40.70#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:54:40.70#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:54:40.70#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:54:40.70#ibcon#enter wrdev, iclass 21, count 0 2006.162.07:54:40.70#ibcon#first serial, iclass 21, count 0 2006.162.07:54:40.70#ibcon#enter sib2, iclass 21, count 0 2006.162.07:54:40.70#ibcon#flushed, iclass 21, count 0 2006.162.07:54:40.70#ibcon#about to write, iclass 21, count 0 2006.162.07:54:40.70#ibcon#wrote, iclass 21, count 0 2006.162.07:54:40.70#ibcon#about to read 3, iclass 21, count 0 2006.162.07:54:40.71#ibcon#read 3, iclass 21, count 0 2006.162.07:54:40.71#ibcon#about to read 4, iclass 21, count 0 2006.162.07:54:40.71#ibcon#read 4, iclass 21, count 0 2006.162.07:54:40.71#ibcon#about to read 5, iclass 21, count 0 2006.162.07:54:40.71#ibcon#read 5, iclass 21, count 0 2006.162.07:54:40.71#ibcon#about to read 6, iclass 21, count 0 2006.162.07:54:40.71#ibcon#read 6, iclass 21, count 0 2006.162.07:54:40.71#ibcon#end of sib2, iclass 21, count 0 2006.162.07:54:40.71#ibcon#*mode == 0, iclass 21, count 0 2006.162.07:54:40.71#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.162.07:54:40.71#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.07:54:40.71#ibcon#*before write, iclass 21, count 0 2006.162.07:54:40.71#ibcon#enter sib2, iclass 21, count 0 2006.162.07:54:40.71#ibcon#flushed, iclass 21, count 0 2006.162.07:54:40.71#ibcon#about to write, iclass 21, count 0 2006.162.07:54:40.71#ibcon#wrote, iclass 21, count 0 2006.162.07:54:40.71#ibcon#about to read 3, iclass 21, count 0 2006.162.07:54:40.75#ibcon#read 3, iclass 21, count 0 2006.162.07:54:40.75#ibcon#about to read 4, iclass 21, count 0 2006.162.07:54:40.75#ibcon#read 4, iclass 21, count 0 2006.162.07:54:40.75#ibcon#about to read 5, iclass 21, count 0 2006.162.07:54:40.75#ibcon#read 5, iclass 21, count 0 2006.162.07:54:40.75#ibcon#about to read 6, iclass 21, count 0 2006.162.07:54:40.75#ibcon#read 6, iclass 21, count 0 2006.162.07:54:40.75#ibcon#end of sib2, iclass 21, count 0 2006.162.07:54:40.75#ibcon#*after write, iclass 21, count 0 2006.162.07:54:40.75#ibcon#*before return 0, iclass 21, count 0 2006.162.07:54:40.75#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:54:40.75#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:54:40.75#ibcon#about to clear, iclass 21 cls_cnt 0 2006.162.07:54:40.75#ibcon#cleared, iclass 21 cls_cnt 0 2006.162.07:54:40.75$vc4f8/va=5,7 2006.162.07:54:40.76#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.162.07:54:40.76#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.162.07:54:40.76#ibcon#ireg 11 cls_cnt 2 2006.162.07:54:40.76#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.162.07:54:40.80#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.162.07:54:40.80#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.162.07:54:40.80#ibcon#enter wrdev, iclass 23, count 2 2006.162.07:54:40.80#ibcon#first serial, iclass 23, count 2 2006.162.07:54:40.80#ibcon#enter sib2, iclass 23, count 2 2006.162.07:54:40.80#ibcon#flushed, iclass 23, count 2 2006.162.07:54:40.80#ibcon#about to write, iclass 23, count 2 2006.162.07:54:40.80#ibcon#wrote, iclass 23, count 2 2006.162.07:54:40.80#ibcon#about to read 3, iclass 23, count 2 2006.162.07:54:40.82#ibcon#read 3, iclass 23, count 2 2006.162.07:54:40.82#ibcon#about to read 4, iclass 23, count 2 2006.162.07:54:40.82#ibcon#read 4, iclass 23, count 2 2006.162.07:54:40.82#ibcon#about to read 5, iclass 23, count 2 2006.162.07:54:40.82#ibcon#read 5, iclass 23, count 2 2006.162.07:54:40.82#ibcon#about to read 6, iclass 23, count 2 2006.162.07:54:40.82#ibcon#read 6, iclass 23, count 2 2006.162.07:54:40.82#ibcon#end of sib2, iclass 23, count 2 2006.162.07:54:40.82#ibcon#*mode == 0, iclass 23, count 2 2006.162.07:54:40.82#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.162.07:54:40.82#ibcon#[25=AT05-07\r\n] 2006.162.07:54:40.82#ibcon#*before write, iclass 23, count 2 2006.162.07:54:40.82#ibcon#enter sib2, iclass 23, count 2 2006.162.07:54:40.82#ibcon#flushed, iclass 23, count 2 2006.162.07:54:40.82#ibcon#about to write, iclass 23, count 2 2006.162.07:54:40.82#ibcon#wrote, iclass 23, count 2 2006.162.07:54:40.82#ibcon#about to read 3, iclass 23, count 2 2006.162.07:54:40.85#ibcon#read 3, iclass 23, count 2 2006.162.07:54:40.85#ibcon#about to read 4, iclass 23, count 2 2006.162.07:54:40.85#ibcon#read 4, iclass 23, count 2 2006.162.07:54:40.85#ibcon#about to read 5, iclass 23, count 2 2006.162.07:54:40.85#ibcon#read 5, iclass 23, count 2 2006.162.07:54:40.85#ibcon#about to read 6, iclass 23, count 2 2006.162.07:54:40.85#ibcon#read 6, iclass 23, count 2 2006.162.07:54:40.85#ibcon#end of sib2, iclass 23, count 2 2006.162.07:54:40.85#ibcon#*after write, iclass 23, count 2 2006.162.07:54:40.85#ibcon#*before return 0, iclass 23, count 2 2006.162.07:54:40.85#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.162.07:54:40.85#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.162.07:54:40.85#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.162.07:54:40.85#ibcon#ireg 7 cls_cnt 0 2006.162.07:54:40.85#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.162.07:54:40.97#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.162.07:54:40.97#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.162.07:54:40.97#ibcon#enter wrdev, iclass 23, count 0 2006.162.07:54:40.97#ibcon#first serial, iclass 23, count 0 2006.162.07:54:40.97#ibcon#enter sib2, iclass 23, count 0 2006.162.07:54:40.97#ibcon#flushed, iclass 23, count 0 2006.162.07:54:40.97#ibcon#about to write, iclass 23, count 0 2006.162.07:54:40.97#ibcon#wrote, iclass 23, count 0 2006.162.07:54:40.97#ibcon#about to read 3, iclass 23, count 0 2006.162.07:54:40.99#ibcon#read 3, iclass 23, count 0 2006.162.07:54:40.99#ibcon#about to read 4, iclass 23, count 0 2006.162.07:54:40.99#ibcon#read 4, iclass 23, count 0 2006.162.07:54:40.99#ibcon#about to read 5, iclass 23, count 0 2006.162.07:54:40.99#ibcon#read 5, iclass 23, count 0 2006.162.07:54:40.99#ibcon#about to read 6, iclass 23, count 0 2006.162.07:54:40.99#ibcon#read 6, iclass 23, count 0 2006.162.07:54:40.99#ibcon#end of sib2, iclass 23, count 0 2006.162.07:54:40.99#ibcon#*mode == 0, iclass 23, count 0 2006.162.07:54:40.99#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.162.07:54:40.99#ibcon#[25=USB\r\n] 2006.162.07:54:40.99#ibcon#*before write, iclass 23, count 0 2006.162.07:54:40.99#ibcon#enter sib2, iclass 23, count 0 2006.162.07:54:40.99#ibcon#flushed, iclass 23, count 0 2006.162.07:54:40.99#ibcon#about to write, iclass 23, count 0 2006.162.07:54:40.99#ibcon#wrote, iclass 23, count 0 2006.162.07:54:40.99#ibcon#about to read 3, iclass 23, count 0 2006.162.07:54:41.02#ibcon#read 3, iclass 23, count 0 2006.162.07:54:41.02#ibcon#about to read 4, iclass 23, count 0 2006.162.07:54:41.02#ibcon#read 4, iclass 23, count 0 2006.162.07:54:41.02#ibcon#about to read 5, iclass 23, count 0 2006.162.07:54:41.02#ibcon#read 5, iclass 23, count 0 2006.162.07:54:41.02#ibcon#about to read 6, iclass 23, count 0 2006.162.07:54:41.02#ibcon#read 6, iclass 23, count 0 2006.162.07:54:41.02#ibcon#end of sib2, iclass 23, count 0 2006.162.07:54:41.02#ibcon#*after write, iclass 23, count 0 2006.162.07:54:41.02#ibcon#*before return 0, iclass 23, count 0 2006.162.07:54:41.02#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.162.07:54:41.02#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.162.07:54:41.02#ibcon#about to clear, iclass 23 cls_cnt 0 2006.162.07:54:41.02#ibcon#cleared, iclass 23 cls_cnt 0 2006.162.07:54:41.02$vc4f8/valo=6,772.99 2006.162.07:54:41.03#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.162.07:54:41.03#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.162.07:54:41.03#ibcon#ireg 17 cls_cnt 0 2006.162.07:54:41.03#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:54:41.03#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:54:41.03#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:54:41.03#ibcon#enter wrdev, iclass 25, count 0 2006.162.07:54:41.03#ibcon#first serial, iclass 25, count 0 2006.162.07:54:41.03#ibcon#enter sib2, iclass 25, count 0 2006.162.07:54:41.03#ibcon#flushed, iclass 25, count 0 2006.162.07:54:41.03#ibcon#about to write, iclass 25, count 0 2006.162.07:54:41.03#ibcon#wrote, iclass 25, count 0 2006.162.07:54:41.03#ibcon#about to read 3, iclass 25, count 0 2006.162.07:54:41.04#ibcon#read 3, iclass 25, count 0 2006.162.07:54:41.04#ibcon#about to read 4, iclass 25, count 0 2006.162.07:54:41.04#ibcon#read 4, iclass 25, count 0 2006.162.07:54:41.04#ibcon#about to read 5, iclass 25, count 0 2006.162.07:54:41.04#ibcon#read 5, iclass 25, count 0 2006.162.07:54:41.04#ibcon#about to read 6, iclass 25, count 0 2006.162.07:54:41.04#ibcon#read 6, iclass 25, count 0 2006.162.07:54:41.04#ibcon#end of sib2, iclass 25, count 0 2006.162.07:54:41.04#ibcon#*mode == 0, iclass 25, count 0 2006.162.07:54:41.04#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.162.07:54:41.04#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.07:54:41.04#ibcon#*before write, iclass 25, count 0 2006.162.07:54:41.04#ibcon#enter sib2, iclass 25, count 0 2006.162.07:54:41.04#ibcon#flushed, iclass 25, count 0 2006.162.07:54:41.04#ibcon#about to write, iclass 25, count 0 2006.162.07:54:41.04#ibcon#wrote, iclass 25, count 0 2006.162.07:54:41.04#ibcon#about to read 3, iclass 25, count 0 2006.162.07:54:41.08#ibcon#read 3, iclass 25, count 0 2006.162.07:54:41.08#ibcon#about to read 4, iclass 25, count 0 2006.162.07:54:41.08#ibcon#read 4, iclass 25, count 0 2006.162.07:54:41.08#ibcon#about to read 5, iclass 25, count 0 2006.162.07:54:41.08#ibcon#read 5, iclass 25, count 0 2006.162.07:54:41.08#ibcon#about to read 6, iclass 25, count 0 2006.162.07:54:41.08#ibcon#read 6, iclass 25, count 0 2006.162.07:54:41.08#ibcon#end of sib2, iclass 25, count 0 2006.162.07:54:41.08#ibcon#*after write, iclass 25, count 0 2006.162.07:54:41.08#ibcon#*before return 0, iclass 25, count 0 2006.162.07:54:41.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:54:41.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:54:41.08#ibcon#about to clear, iclass 25 cls_cnt 0 2006.162.07:54:41.08#ibcon#cleared, iclass 25 cls_cnt 0 2006.162.07:54:41.09$vc4f8/va=6,6 2006.162.07:54:41.09#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.162.07:54:41.09#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.162.07:54:41.09#ibcon#ireg 11 cls_cnt 2 2006.162.07:54:41.09#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.162.07:54:41.13#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.162.07:54:41.13#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.162.07:54:41.13#ibcon#enter wrdev, iclass 27, count 2 2006.162.07:54:41.13#ibcon#first serial, iclass 27, count 2 2006.162.07:54:41.13#ibcon#enter sib2, iclass 27, count 2 2006.162.07:54:41.13#ibcon#flushed, iclass 27, count 2 2006.162.07:54:41.13#ibcon#about to write, iclass 27, count 2 2006.162.07:54:41.13#ibcon#wrote, iclass 27, count 2 2006.162.07:54:41.13#ibcon#about to read 3, iclass 27, count 2 2006.162.07:54:41.15#ibcon#read 3, iclass 27, count 2 2006.162.07:54:41.15#ibcon#about to read 4, iclass 27, count 2 2006.162.07:54:41.15#ibcon#read 4, iclass 27, count 2 2006.162.07:54:41.15#ibcon#about to read 5, iclass 27, count 2 2006.162.07:54:41.15#ibcon#read 5, iclass 27, count 2 2006.162.07:54:41.15#ibcon#about to read 6, iclass 27, count 2 2006.162.07:54:41.15#ibcon#read 6, iclass 27, count 2 2006.162.07:54:41.15#ibcon#end of sib2, iclass 27, count 2 2006.162.07:54:41.15#ibcon#*mode == 0, iclass 27, count 2 2006.162.07:54:41.15#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.162.07:54:41.15#ibcon#[25=AT06-06\r\n] 2006.162.07:54:41.15#ibcon#*before write, iclass 27, count 2 2006.162.07:54:41.15#ibcon#enter sib2, iclass 27, count 2 2006.162.07:54:41.15#ibcon#flushed, iclass 27, count 2 2006.162.07:54:41.15#ibcon#about to write, iclass 27, count 2 2006.162.07:54:41.15#ibcon#wrote, iclass 27, count 2 2006.162.07:54:41.15#ibcon#about to read 3, iclass 27, count 2 2006.162.07:54:41.18#ibcon#read 3, iclass 27, count 2 2006.162.07:54:41.18#ibcon#about to read 4, iclass 27, count 2 2006.162.07:54:41.18#ibcon#read 4, iclass 27, count 2 2006.162.07:54:41.18#ibcon#about to read 5, iclass 27, count 2 2006.162.07:54:41.18#ibcon#read 5, iclass 27, count 2 2006.162.07:54:41.18#ibcon#about to read 6, iclass 27, count 2 2006.162.07:54:41.18#ibcon#read 6, iclass 27, count 2 2006.162.07:54:41.18#ibcon#end of sib2, iclass 27, count 2 2006.162.07:54:41.18#ibcon#*after write, iclass 27, count 2 2006.162.07:54:41.18#ibcon#*before return 0, iclass 27, count 2 2006.162.07:54:41.18#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.162.07:54:41.18#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.162.07:54:41.18#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.162.07:54:41.18#ibcon#ireg 7 cls_cnt 0 2006.162.07:54:41.18#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.162.07:54:41.30#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.162.07:54:41.30#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.162.07:54:41.30#ibcon#enter wrdev, iclass 27, count 0 2006.162.07:54:41.30#ibcon#first serial, iclass 27, count 0 2006.162.07:54:41.30#ibcon#enter sib2, iclass 27, count 0 2006.162.07:54:41.30#ibcon#flushed, iclass 27, count 0 2006.162.07:54:41.30#ibcon#about to write, iclass 27, count 0 2006.162.07:54:41.30#ibcon#wrote, iclass 27, count 0 2006.162.07:54:41.30#ibcon#about to read 3, iclass 27, count 0 2006.162.07:54:41.32#ibcon#read 3, iclass 27, count 0 2006.162.07:54:41.32#ibcon#about to read 4, iclass 27, count 0 2006.162.07:54:41.32#ibcon#read 4, iclass 27, count 0 2006.162.07:54:41.32#ibcon#about to read 5, iclass 27, count 0 2006.162.07:54:41.32#ibcon#read 5, iclass 27, count 0 2006.162.07:54:41.32#ibcon#about to read 6, iclass 27, count 0 2006.162.07:54:41.32#ibcon#read 6, iclass 27, count 0 2006.162.07:54:41.32#ibcon#end of sib2, iclass 27, count 0 2006.162.07:54:41.32#ibcon#*mode == 0, iclass 27, count 0 2006.162.07:54:41.32#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.162.07:54:41.32#ibcon#[25=USB\r\n] 2006.162.07:54:41.32#ibcon#*before write, iclass 27, count 0 2006.162.07:54:41.32#ibcon#enter sib2, iclass 27, count 0 2006.162.07:54:41.32#ibcon#flushed, iclass 27, count 0 2006.162.07:54:41.32#ibcon#about to write, iclass 27, count 0 2006.162.07:54:41.32#ibcon#wrote, iclass 27, count 0 2006.162.07:54:41.32#ibcon#about to read 3, iclass 27, count 0 2006.162.07:54:41.35#ibcon#read 3, iclass 27, count 0 2006.162.07:54:41.35#ibcon#about to read 4, iclass 27, count 0 2006.162.07:54:41.35#ibcon#read 4, iclass 27, count 0 2006.162.07:54:41.35#ibcon#about to read 5, iclass 27, count 0 2006.162.07:54:41.35#ibcon#read 5, iclass 27, count 0 2006.162.07:54:41.35#ibcon#about to read 6, iclass 27, count 0 2006.162.07:54:41.35#ibcon#read 6, iclass 27, count 0 2006.162.07:54:41.35#ibcon#end of sib2, iclass 27, count 0 2006.162.07:54:41.35#ibcon#*after write, iclass 27, count 0 2006.162.07:54:41.35#ibcon#*before return 0, iclass 27, count 0 2006.162.07:54:41.35#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.162.07:54:41.35#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.162.07:54:41.35#ibcon#about to clear, iclass 27 cls_cnt 0 2006.162.07:54:41.35#ibcon#cleared, iclass 27 cls_cnt 0 2006.162.07:54:41.35$vc4f8/valo=7,832.99 2006.162.07:54:41.36#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.162.07:54:41.36#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.162.07:54:41.36#ibcon#ireg 17 cls_cnt 0 2006.162.07:54:41.36#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.162.07:54:41.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.162.07:54:41.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.162.07:54:41.36#ibcon#enter wrdev, iclass 29, count 0 2006.162.07:54:41.36#ibcon#first serial, iclass 29, count 0 2006.162.07:54:41.36#ibcon#enter sib2, iclass 29, count 0 2006.162.07:54:41.36#ibcon#flushed, iclass 29, count 0 2006.162.07:54:41.36#ibcon#about to write, iclass 29, count 0 2006.162.07:54:41.36#ibcon#wrote, iclass 29, count 0 2006.162.07:54:41.36#ibcon#about to read 3, iclass 29, count 0 2006.162.07:54:41.37#ibcon#read 3, iclass 29, count 0 2006.162.07:54:41.37#ibcon#about to read 4, iclass 29, count 0 2006.162.07:54:41.37#ibcon#read 4, iclass 29, count 0 2006.162.07:54:41.37#ibcon#about to read 5, iclass 29, count 0 2006.162.07:54:41.37#ibcon#read 5, iclass 29, count 0 2006.162.07:54:41.37#ibcon#about to read 6, iclass 29, count 0 2006.162.07:54:41.37#ibcon#read 6, iclass 29, count 0 2006.162.07:54:41.37#ibcon#end of sib2, iclass 29, count 0 2006.162.07:54:41.37#ibcon#*mode == 0, iclass 29, count 0 2006.162.07:54:41.37#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.162.07:54:41.37#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.07:54:41.37#ibcon#*before write, iclass 29, count 0 2006.162.07:54:41.37#ibcon#enter sib2, iclass 29, count 0 2006.162.07:54:41.37#ibcon#flushed, iclass 29, count 0 2006.162.07:54:41.37#ibcon#about to write, iclass 29, count 0 2006.162.07:54:41.37#ibcon#wrote, iclass 29, count 0 2006.162.07:54:41.37#ibcon#about to read 3, iclass 29, count 0 2006.162.07:54:41.41#ibcon#read 3, iclass 29, count 0 2006.162.07:54:41.41#ibcon#about to read 4, iclass 29, count 0 2006.162.07:54:41.41#ibcon#read 4, iclass 29, count 0 2006.162.07:54:41.41#ibcon#about to read 5, iclass 29, count 0 2006.162.07:54:41.41#ibcon#read 5, iclass 29, count 0 2006.162.07:54:41.41#ibcon#about to read 6, iclass 29, count 0 2006.162.07:54:41.41#ibcon#read 6, iclass 29, count 0 2006.162.07:54:41.41#ibcon#end of sib2, iclass 29, count 0 2006.162.07:54:41.41#ibcon#*after write, iclass 29, count 0 2006.162.07:54:41.41#ibcon#*before return 0, iclass 29, count 0 2006.162.07:54:41.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.162.07:54:41.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.162.07:54:41.41#ibcon#about to clear, iclass 29 cls_cnt 0 2006.162.07:54:41.41#ibcon#cleared, iclass 29 cls_cnt 0 2006.162.07:54:41.41$vc4f8/va=7,6 2006.162.07:54:41.42#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.162.07:54:41.42#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.162.07:54:41.42#ibcon#ireg 11 cls_cnt 2 2006.162.07:54:41.42#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.162.07:54:41.46#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.162.07:54:41.46#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.162.07:54:41.46#ibcon#enter wrdev, iclass 31, count 2 2006.162.07:54:41.46#ibcon#first serial, iclass 31, count 2 2006.162.07:54:41.46#ibcon#enter sib2, iclass 31, count 2 2006.162.07:54:41.46#ibcon#flushed, iclass 31, count 2 2006.162.07:54:41.46#ibcon#about to write, iclass 31, count 2 2006.162.07:54:41.46#ibcon#wrote, iclass 31, count 2 2006.162.07:54:41.46#ibcon#about to read 3, iclass 31, count 2 2006.162.07:54:41.48#ibcon#read 3, iclass 31, count 2 2006.162.07:54:41.48#ibcon#about to read 4, iclass 31, count 2 2006.162.07:54:41.48#ibcon#read 4, iclass 31, count 2 2006.162.07:54:41.48#ibcon#about to read 5, iclass 31, count 2 2006.162.07:54:41.48#ibcon#read 5, iclass 31, count 2 2006.162.07:54:41.48#ibcon#about to read 6, iclass 31, count 2 2006.162.07:54:41.48#ibcon#read 6, iclass 31, count 2 2006.162.07:54:41.48#ibcon#end of sib2, iclass 31, count 2 2006.162.07:54:41.48#ibcon#*mode == 0, iclass 31, count 2 2006.162.07:54:41.48#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.162.07:54:41.48#ibcon#[25=AT07-06\r\n] 2006.162.07:54:41.48#ibcon#*before write, iclass 31, count 2 2006.162.07:54:41.48#ibcon#enter sib2, iclass 31, count 2 2006.162.07:54:41.48#ibcon#flushed, iclass 31, count 2 2006.162.07:54:41.48#ibcon#about to write, iclass 31, count 2 2006.162.07:54:41.48#ibcon#wrote, iclass 31, count 2 2006.162.07:54:41.48#ibcon#about to read 3, iclass 31, count 2 2006.162.07:54:41.51#ibcon#read 3, iclass 31, count 2 2006.162.07:54:41.51#ibcon#about to read 4, iclass 31, count 2 2006.162.07:54:41.51#ibcon#read 4, iclass 31, count 2 2006.162.07:54:41.51#ibcon#about to read 5, iclass 31, count 2 2006.162.07:54:41.51#ibcon#read 5, iclass 31, count 2 2006.162.07:54:41.51#ibcon#about to read 6, iclass 31, count 2 2006.162.07:54:41.51#ibcon#read 6, iclass 31, count 2 2006.162.07:54:41.51#ibcon#end of sib2, iclass 31, count 2 2006.162.07:54:41.51#ibcon#*after write, iclass 31, count 2 2006.162.07:54:41.51#ibcon#*before return 0, iclass 31, count 2 2006.162.07:54:41.51#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.162.07:54:41.51#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.162.07:54:41.51#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.162.07:54:41.51#ibcon#ireg 7 cls_cnt 0 2006.162.07:54:41.51#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.162.07:54:41.63#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.162.07:54:41.63#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.162.07:54:41.63#ibcon#enter wrdev, iclass 31, count 0 2006.162.07:54:41.63#ibcon#first serial, iclass 31, count 0 2006.162.07:54:41.63#ibcon#enter sib2, iclass 31, count 0 2006.162.07:54:41.63#ibcon#flushed, iclass 31, count 0 2006.162.07:54:41.63#ibcon#about to write, iclass 31, count 0 2006.162.07:54:41.63#ibcon#wrote, iclass 31, count 0 2006.162.07:54:41.63#ibcon#about to read 3, iclass 31, count 0 2006.162.07:54:41.65#ibcon#read 3, iclass 31, count 0 2006.162.07:54:41.65#ibcon#about to read 4, iclass 31, count 0 2006.162.07:54:41.65#ibcon#read 4, iclass 31, count 0 2006.162.07:54:41.65#ibcon#about to read 5, iclass 31, count 0 2006.162.07:54:41.65#ibcon#read 5, iclass 31, count 0 2006.162.07:54:41.65#ibcon#about to read 6, iclass 31, count 0 2006.162.07:54:41.65#ibcon#read 6, iclass 31, count 0 2006.162.07:54:41.65#ibcon#end of sib2, iclass 31, count 0 2006.162.07:54:41.65#ibcon#*mode == 0, iclass 31, count 0 2006.162.07:54:41.65#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.162.07:54:41.65#ibcon#[25=USB\r\n] 2006.162.07:54:41.65#ibcon#*before write, iclass 31, count 0 2006.162.07:54:41.65#ibcon#enter sib2, iclass 31, count 0 2006.162.07:54:41.65#ibcon#flushed, iclass 31, count 0 2006.162.07:54:41.65#ibcon#about to write, iclass 31, count 0 2006.162.07:54:41.65#ibcon#wrote, iclass 31, count 0 2006.162.07:54:41.65#ibcon#about to read 3, iclass 31, count 0 2006.162.07:54:41.68#ibcon#read 3, iclass 31, count 0 2006.162.07:54:41.68#ibcon#about to read 4, iclass 31, count 0 2006.162.07:54:41.68#ibcon#read 4, iclass 31, count 0 2006.162.07:54:41.68#ibcon#about to read 5, iclass 31, count 0 2006.162.07:54:41.68#ibcon#read 5, iclass 31, count 0 2006.162.07:54:41.68#ibcon#about to read 6, iclass 31, count 0 2006.162.07:54:41.68#ibcon#read 6, iclass 31, count 0 2006.162.07:54:41.68#ibcon#end of sib2, iclass 31, count 0 2006.162.07:54:41.68#ibcon#*after write, iclass 31, count 0 2006.162.07:54:41.68#ibcon#*before return 0, iclass 31, count 0 2006.162.07:54:41.68#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.162.07:54:41.68#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.162.07:54:41.68#ibcon#about to clear, iclass 31 cls_cnt 0 2006.162.07:54:41.68#ibcon#cleared, iclass 31 cls_cnt 0 2006.162.07:54:41.68$vc4f8/valo=8,852.99 2006.162.07:54:41.69#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.162.07:54:41.69#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.162.07:54:41.69#ibcon#ireg 17 cls_cnt 0 2006.162.07:54:41.69#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.162.07:54:41.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.162.07:54:41.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.162.07:54:41.69#ibcon#enter wrdev, iclass 33, count 0 2006.162.07:54:41.69#ibcon#first serial, iclass 33, count 0 2006.162.07:54:41.69#ibcon#enter sib2, iclass 33, count 0 2006.162.07:54:41.69#ibcon#flushed, iclass 33, count 0 2006.162.07:54:41.69#ibcon#about to write, iclass 33, count 0 2006.162.07:54:41.69#ibcon#wrote, iclass 33, count 0 2006.162.07:54:41.69#ibcon#about to read 3, iclass 33, count 0 2006.162.07:54:41.70#ibcon#read 3, iclass 33, count 0 2006.162.07:54:41.70#ibcon#about to read 4, iclass 33, count 0 2006.162.07:54:41.70#ibcon#read 4, iclass 33, count 0 2006.162.07:54:41.70#ibcon#about to read 5, iclass 33, count 0 2006.162.07:54:41.70#ibcon#read 5, iclass 33, count 0 2006.162.07:54:41.70#ibcon#about to read 6, iclass 33, count 0 2006.162.07:54:41.70#ibcon#read 6, iclass 33, count 0 2006.162.07:54:41.70#ibcon#end of sib2, iclass 33, count 0 2006.162.07:54:41.70#ibcon#*mode == 0, iclass 33, count 0 2006.162.07:54:41.70#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.162.07:54:41.70#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.07:54:41.70#ibcon#*before write, iclass 33, count 0 2006.162.07:54:41.70#ibcon#enter sib2, iclass 33, count 0 2006.162.07:54:41.70#ibcon#flushed, iclass 33, count 0 2006.162.07:54:41.70#ibcon#about to write, iclass 33, count 0 2006.162.07:54:41.70#ibcon#wrote, iclass 33, count 0 2006.162.07:54:41.70#ibcon#about to read 3, iclass 33, count 0 2006.162.07:54:41.74#ibcon#read 3, iclass 33, count 0 2006.162.07:54:41.74#ibcon#about to read 4, iclass 33, count 0 2006.162.07:54:41.74#ibcon#read 4, iclass 33, count 0 2006.162.07:54:41.74#ibcon#about to read 5, iclass 33, count 0 2006.162.07:54:41.74#ibcon#read 5, iclass 33, count 0 2006.162.07:54:41.74#ibcon#about to read 6, iclass 33, count 0 2006.162.07:54:41.74#ibcon#read 6, iclass 33, count 0 2006.162.07:54:41.74#ibcon#end of sib2, iclass 33, count 0 2006.162.07:54:41.74#ibcon#*after write, iclass 33, count 0 2006.162.07:54:41.74#ibcon#*before return 0, iclass 33, count 0 2006.162.07:54:41.74#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.162.07:54:41.74#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.162.07:54:41.74#ibcon#about to clear, iclass 33 cls_cnt 0 2006.162.07:54:41.74#ibcon#cleared, iclass 33 cls_cnt 0 2006.162.07:54:41.74$vc4f8/va=8,7 2006.162.07:54:41.75#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.162.07:54:41.75#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.162.07:54:41.75#ibcon#ireg 11 cls_cnt 2 2006.162.07:54:41.75#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.162.07:54:41.79#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.162.07:54:41.79#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.162.07:54:41.79#ibcon#enter wrdev, iclass 35, count 2 2006.162.07:54:41.79#ibcon#first serial, iclass 35, count 2 2006.162.07:54:41.79#ibcon#enter sib2, iclass 35, count 2 2006.162.07:54:41.79#ibcon#flushed, iclass 35, count 2 2006.162.07:54:41.79#ibcon#about to write, iclass 35, count 2 2006.162.07:54:41.79#ibcon#wrote, iclass 35, count 2 2006.162.07:54:41.79#ibcon#about to read 3, iclass 35, count 2 2006.162.07:54:41.82#ibcon#read 3, iclass 35, count 2 2006.162.07:54:41.82#ibcon#about to read 4, iclass 35, count 2 2006.162.07:54:41.82#ibcon#read 4, iclass 35, count 2 2006.162.07:54:41.82#ibcon#about to read 5, iclass 35, count 2 2006.162.07:54:41.82#ibcon#read 5, iclass 35, count 2 2006.162.07:54:41.82#ibcon#about to read 6, iclass 35, count 2 2006.162.07:54:41.82#ibcon#read 6, iclass 35, count 2 2006.162.07:54:41.82#ibcon#end of sib2, iclass 35, count 2 2006.162.07:54:41.82#ibcon#*mode == 0, iclass 35, count 2 2006.162.07:54:41.82#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.162.07:54:41.82#ibcon#[25=AT08-07\r\n] 2006.162.07:54:41.82#ibcon#*before write, iclass 35, count 2 2006.162.07:54:41.82#ibcon#enter sib2, iclass 35, count 2 2006.162.07:54:41.82#ibcon#flushed, iclass 35, count 2 2006.162.07:54:41.82#ibcon#about to write, iclass 35, count 2 2006.162.07:54:41.82#ibcon#wrote, iclass 35, count 2 2006.162.07:54:41.82#ibcon#about to read 3, iclass 35, count 2 2006.162.07:54:41.85#ibcon#read 3, iclass 35, count 2 2006.162.07:54:41.85#ibcon#about to read 4, iclass 35, count 2 2006.162.07:54:41.85#ibcon#read 4, iclass 35, count 2 2006.162.07:54:41.85#ibcon#about to read 5, iclass 35, count 2 2006.162.07:54:41.85#ibcon#read 5, iclass 35, count 2 2006.162.07:54:41.85#ibcon#about to read 6, iclass 35, count 2 2006.162.07:54:41.85#ibcon#read 6, iclass 35, count 2 2006.162.07:54:41.85#ibcon#end of sib2, iclass 35, count 2 2006.162.07:54:41.85#ibcon#*after write, iclass 35, count 2 2006.162.07:54:41.85#ibcon#*before return 0, iclass 35, count 2 2006.162.07:54:41.85#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.162.07:54:41.85#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.162.07:54:41.85#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.162.07:54:41.85#ibcon#ireg 7 cls_cnt 0 2006.162.07:54:41.85#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.162.07:54:41.97#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.162.07:54:41.97#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.162.07:54:41.97#ibcon#enter wrdev, iclass 35, count 0 2006.162.07:54:41.97#ibcon#first serial, iclass 35, count 0 2006.162.07:54:41.97#ibcon#enter sib2, iclass 35, count 0 2006.162.07:54:41.97#ibcon#flushed, iclass 35, count 0 2006.162.07:54:41.97#ibcon#about to write, iclass 35, count 0 2006.162.07:54:41.97#ibcon#wrote, iclass 35, count 0 2006.162.07:54:41.97#ibcon#about to read 3, iclass 35, count 0 2006.162.07:54:41.99#ibcon#read 3, iclass 35, count 0 2006.162.07:54:41.99#ibcon#about to read 4, iclass 35, count 0 2006.162.07:54:41.99#ibcon#read 4, iclass 35, count 0 2006.162.07:54:41.99#ibcon#about to read 5, iclass 35, count 0 2006.162.07:54:41.99#ibcon#read 5, iclass 35, count 0 2006.162.07:54:41.99#ibcon#about to read 6, iclass 35, count 0 2006.162.07:54:41.99#ibcon#read 6, iclass 35, count 0 2006.162.07:54:41.99#ibcon#end of sib2, iclass 35, count 0 2006.162.07:54:41.99#ibcon#*mode == 0, iclass 35, count 0 2006.162.07:54:41.99#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.162.07:54:41.99#ibcon#[25=USB\r\n] 2006.162.07:54:41.99#ibcon#*before write, iclass 35, count 0 2006.162.07:54:41.99#ibcon#enter sib2, iclass 35, count 0 2006.162.07:54:41.99#ibcon#flushed, iclass 35, count 0 2006.162.07:54:41.99#ibcon#about to write, iclass 35, count 0 2006.162.07:54:41.99#ibcon#wrote, iclass 35, count 0 2006.162.07:54:41.99#ibcon#about to read 3, iclass 35, count 0 2006.162.07:54:42.02#ibcon#read 3, iclass 35, count 0 2006.162.07:54:42.02#ibcon#about to read 4, iclass 35, count 0 2006.162.07:54:42.02#ibcon#read 4, iclass 35, count 0 2006.162.07:54:42.02#ibcon#about to read 5, iclass 35, count 0 2006.162.07:54:42.02#ibcon#read 5, iclass 35, count 0 2006.162.07:54:42.02#ibcon#about to read 6, iclass 35, count 0 2006.162.07:54:42.02#ibcon#read 6, iclass 35, count 0 2006.162.07:54:42.02#ibcon#end of sib2, iclass 35, count 0 2006.162.07:54:42.02#ibcon#*after write, iclass 35, count 0 2006.162.07:54:42.02#ibcon#*before return 0, iclass 35, count 0 2006.162.07:54:42.02#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.162.07:54:42.02#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.162.07:54:42.02#ibcon#about to clear, iclass 35 cls_cnt 0 2006.162.07:54:42.02#ibcon#cleared, iclass 35 cls_cnt 0 2006.162.07:54:42.02$vc4f8/vblo=1,632.99 2006.162.07:54:42.03#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.162.07:54:42.03#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.162.07:54:42.03#ibcon#ireg 17 cls_cnt 0 2006.162.07:54:42.03#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.162.07:54:42.03#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.162.07:54:42.03#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.162.07:54:42.03#ibcon#enter wrdev, iclass 37, count 0 2006.162.07:54:42.03#ibcon#first serial, iclass 37, count 0 2006.162.07:54:42.03#ibcon#enter sib2, iclass 37, count 0 2006.162.07:54:42.03#ibcon#flushed, iclass 37, count 0 2006.162.07:54:42.03#ibcon#about to write, iclass 37, count 0 2006.162.07:54:42.03#ibcon#wrote, iclass 37, count 0 2006.162.07:54:42.03#ibcon#about to read 3, iclass 37, count 0 2006.162.07:54:42.04#ibcon#read 3, iclass 37, count 0 2006.162.07:54:42.04#ibcon#about to read 4, iclass 37, count 0 2006.162.07:54:42.04#ibcon#read 4, iclass 37, count 0 2006.162.07:54:42.04#ibcon#about to read 5, iclass 37, count 0 2006.162.07:54:42.04#ibcon#read 5, iclass 37, count 0 2006.162.07:54:42.04#ibcon#about to read 6, iclass 37, count 0 2006.162.07:54:42.04#ibcon#read 6, iclass 37, count 0 2006.162.07:54:42.04#ibcon#end of sib2, iclass 37, count 0 2006.162.07:54:42.04#ibcon#*mode == 0, iclass 37, count 0 2006.162.07:54:42.04#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.162.07:54:42.04#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.07:54:42.04#ibcon#*before write, iclass 37, count 0 2006.162.07:54:42.04#ibcon#enter sib2, iclass 37, count 0 2006.162.07:54:42.04#ibcon#flushed, iclass 37, count 0 2006.162.07:54:42.04#ibcon#about to write, iclass 37, count 0 2006.162.07:54:42.04#ibcon#wrote, iclass 37, count 0 2006.162.07:54:42.04#ibcon#about to read 3, iclass 37, count 0 2006.162.07:54:42.08#ibcon#read 3, iclass 37, count 0 2006.162.07:54:42.08#ibcon#about to read 4, iclass 37, count 0 2006.162.07:54:42.08#ibcon#read 4, iclass 37, count 0 2006.162.07:54:42.08#ibcon#about to read 5, iclass 37, count 0 2006.162.07:54:42.08#ibcon#read 5, iclass 37, count 0 2006.162.07:54:42.08#ibcon#about to read 6, iclass 37, count 0 2006.162.07:54:42.08#ibcon#read 6, iclass 37, count 0 2006.162.07:54:42.08#ibcon#end of sib2, iclass 37, count 0 2006.162.07:54:42.08#ibcon#*after write, iclass 37, count 0 2006.162.07:54:42.08#ibcon#*before return 0, iclass 37, count 0 2006.162.07:54:42.08#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.162.07:54:42.08#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.162.07:54:42.08#ibcon#about to clear, iclass 37 cls_cnt 0 2006.162.07:54:42.08#ibcon#cleared, iclass 37 cls_cnt 0 2006.162.07:54:42.09$vc4f8/vb=1,4 2006.162.07:54:42.09#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.162.07:54:42.09#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.162.07:54:42.09#ibcon#ireg 11 cls_cnt 2 2006.162.07:54:42.09#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.162.07:54:42.09#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.162.07:54:42.09#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.162.07:54:42.09#ibcon#enter wrdev, iclass 39, count 2 2006.162.07:54:42.09#ibcon#first serial, iclass 39, count 2 2006.162.07:54:42.09#ibcon#enter sib2, iclass 39, count 2 2006.162.07:54:42.09#ibcon#flushed, iclass 39, count 2 2006.162.07:54:42.09#ibcon#about to write, iclass 39, count 2 2006.162.07:54:42.09#ibcon#wrote, iclass 39, count 2 2006.162.07:54:42.09#ibcon#about to read 3, iclass 39, count 2 2006.162.07:54:42.10#ibcon#read 3, iclass 39, count 2 2006.162.07:54:42.10#ibcon#about to read 4, iclass 39, count 2 2006.162.07:54:42.10#ibcon#read 4, iclass 39, count 2 2006.162.07:54:42.10#ibcon#about to read 5, iclass 39, count 2 2006.162.07:54:42.10#ibcon#read 5, iclass 39, count 2 2006.162.07:54:42.10#ibcon#about to read 6, iclass 39, count 2 2006.162.07:54:42.10#ibcon#read 6, iclass 39, count 2 2006.162.07:54:42.10#ibcon#end of sib2, iclass 39, count 2 2006.162.07:54:42.10#ibcon#*mode == 0, iclass 39, count 2 2006.162.07:54:42.10#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.162.07:54:42.10#ibcon#[27=AT01-04\r\n] 2006.162.07:54:42.10#ibcon#*before write, iclass 39, count 2 2006.162.07:54:42.10#ibcon#enter sib2, iclass 39, count 2 2006.162.07:54:42.10#ibcon#flushed, iclass 39, count 2 2006.162.07:54:42.10#ibcon#about to write, iclass 39, count 2 2006.162.07:54:42.10#ibcon#wrote, iclass 39, count 2 2006.162.07:54:42.10#ibcon#about to read 3, iclass 39, count 2 2006.162.07:54:42.13#ibcon#read 3, iclass 39, count 2 2006.162.07:54:42.13#ibcon#about to read 4, iclass 39, count 2 2006.162.07:54:42.13#ibcon#read 4, iclass 39, count 2 2006.162.07:54:42.13#ibcon#about to read 5, iclass 39, count 2 2006.162.07:54:42.13#ibcon#read 5, iclass 39, count 2 2006.162.07:54:42.13#ibcon#about to read 6, iclass 39, count 2 2006.162.07:54:42.13#ibcon#read 6, iclass 39, count 2 2006.162.07:54:42.13#ibcon#end of sib2, iclass 39, count 2 2006.162.07:54:42.13#ibcon#*after write, iclass 39, count 2 2006.162.07:54:42.13#ibcon#*before return 0, iclass 39, count 2 2006.162.07:54:42.13#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.162.07:54:42.13#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.162.07:54:42.13#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.162.07:54:42.13#ibcon#ireg 7 cls_cnt 0 2006.162.07:54:42.13#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.162.07:54:42.25#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.162.07:54:42.25#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.162.07:54:42.25#ibcon#enter wrdev, iclass 39, count 0 2006.162.07:54:42.25#ibcon#first serial, iclass 39, count 0 2006.162.07:54:42.25#ibcon#enter sib2, iclass 39, count 0 2006.162.07:54:42.25#ibcon#flushed, iclass 39, count 0 2006.162.07:54:42.25#ibcon#about to write, iclass 39, count 0 2006.162.07:54:42.25#ibcon#wrote, iclass 39, count 0 2006.162.07:54:42.25#ibcon#about to read 3, iclass 39, count 0 2006.162.07:54:42.27#ibcon#read 3, iclass 39, count 0 2006.162.07:54:42.27#ibcon#about to read 4, iclass 39, count 0 2006.162.07:54:42.27#ibcon#read 4, iclass 39, count 0 2006.162.07:54:42.27#ibcon#about to read 5, iclass 39, count 0 2006.162.07:54:42.27#ibcon#read 5, iclass 39, count 0 2006.162.07:54:42.27#ibcon#about to read 6, iclass 39, count 0 2006.162.07:54:42.27#ibcon#read 6, iclass 39, count 0 2006.162.07:54:42.27#ibcon#end of sib2, iclass 39, count 0 2006.162.07:54:42.27#ibcon#*mode == 0, iclass 39, count 0 2006.162.07:54:42.27#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.162.07:54:42.27#ibcon#[27=USB\r\n] 2006.162.07:54:42.27#ibcon#*before write, iclass 39, count 0 2006.162.07:54:42.27#ibcon#enter sib2, iclass 39, count 0 2006.162.07:54:42.27#ibcon#flushed, iclass 39, count 0 2006.162.07:54:42.27#ibcon#about to write, iclass 39, count 0 2006.162.07:54:42.27#ibcon#wrote, iclass 39, count 0 2006.162.07:54:42.27#ibcon#about to read 3, iclass 39, count 0 2006.162.07:54:42.30#ibcon#read 3, iclass 39, count 0 2006.162.07:54:42.30#ibcon#about to read 4, iclass 39, count 0 2006.162.07:54:42.30#ibcon#read 4, iclass 39, count 0 2006.162.07:54:42.30#ibcon#about to read 5, iclass 39, count 0 2006.162.07:54:42.30#ibcon#read 5, iclass 39, count 0 2006.162.07:54:42.30#ibcon#about to read 6, iclass 39, count 0 2006.162.07:54:42.30#ibcon#read 6, iclass 39, count 0 2006.162.07:54:42.30#ibcon#end of sib2, iclass 39, count 0 2006.162.07:54:42.30#ibcon#*after write, iclass 39, count 0 2006.162.07:54:42.30#ibcon#*before return 0, iclass 39, count 0 2006.162.07:54:42.30#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.162.07:54:42.30#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.162.07:54:42.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.162.07:54:42.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.162.07:54:42.30$vc4f8/vblo=2,640.99 2006.162.07:54:42.31#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.162.07:54:42.31#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.162.07:54:42.31#ibcon#ireg 17 cls_cnt 0 2006.162.07:54:42.31#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.162.07:54:42.31#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.162.07:54:42.31#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.162.07:54:42.31#ibcon#enter wrdev, iclass 3, count 0 2006.162.07:54:42.31#ibcon#first serial, iclass 3, count 0 2006.162.07:54:42.31#ibcon#enter sib2, iclass 3, count 0 2006.162.07:54:42.31#ibcon#flushed, iclass 3, count 0 2006.162.07:54:42.31#ibcon#about to write, iclass 3, count 0 2006.162.07:54:42.31#ibcon#wrote, iclass 3, count 0 2006.162.07:54:42.31#ibcon#about to read 3, iclass 3, count 0 2006.162.07:54:42.32#ibcon#read 3, iclass 3, count 0 2006.162.07:54:42.32#ibcon#about to read 4, iclass 3, count 0 2006.162.07:54:42.32#ibcon#read 4, iclass 3, count 0 2006.162.07:54:42.32#ibcon#about to read 5, iclass 3, count 0 2006.162.07:54:42.32#ibcon#read 5, iclass 3, count 0 2006.162.07:54:42.32#ibcon#about to read 6, iclass 3, count 0 2006.162.07:54:42.32#ibcon#read 6, iclass 3, count 0 2006.162.07:54:42.32#ibcon#end of sib2, iclass 3, count 0 2006.162.07:54:42.32#ibcon#*mode == 0, iclass 3, count 0 2006.162.07:54:42.32#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.162.07:54:42.32#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.07:54:42.32#ibcon#*before write, iclass 3, count 0 2006.162.07:54:42.32#ibcon#enter sib2, iclass 3, count 0 2006.162.07:54:42.32#ibcon#flushed, iclass 3, count 0 2006.162.07:54:42.32#ibcon#about to write, iclass 3, count 0 2006.162.07:54:42.32#ibcon#wrote, iclass 3, count 0 2006.162.07:54:42.32#ibcon#about to read 3, iclass 3, count 0 2006.162.07:54:42.36#ibcon#read 3, iclass 3, count 0 2006.162.07:54:42.36#ibcon#about to read 4, iclass 3, count 0 2006.162.07:54:42.36#ibcon#read 4, iclass 3, count 0 2006.162.07:54:42.36#ibcon#about to read 5, iclass 3, count 0 2006.162.07:54:42.36#ibcon#read 5, iclass 3, count 0 2006.162.07:54:42.36#ibcon#about to read 6, iclass 3, count 0 2006.162.07:54:42.36#ibcon#read 6, iclass 3, count 0 2006.162.07:54:42.36#ibcon#end of sib2, iclass 3, count 0 2006.162.07:54:42.36#ibcon#*after write, iclass 3, count 0 2006.162.07:54:42.36#ibcon#*before return 0, iclass 3, count 0 2006.162.07:54:42.36#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.162.07:54:42.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.162.07:54:42.36#ibcon#about to clear, iclass 3 cls_cnt 0 2006.162.07:54:42.36#ibcon#cleared, iclass 3 cls_cnt 0 2006.162.07:54:42.36$vc4f8/vb=2,4 2006.162.07:54:42.37#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.162.07:54:42.37#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.162.07:54:42.37#ibcon#ireg 11 cls_cnt 2 2006.162.07:54:42.37#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.162.07:54:42.41#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.162.07:54:42.41#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.162.07:54:42.41#ibcon#enter wrdev, iclass 5, count 2 2006.162.07:54:42.41#ibcon#first serial, iclass 5, count 2 2006.162.07:54:42.41#ibcon#enter sib2, iclass 5, count 2 2006.162.07:54:42.41#ibcon#flushed, iclass 5, count 2 2006.162.07:54:42.41#ibcon#about to write, iclass 5, count 2 2006.162.07:54:42.41#ibcon#wrote, iclass 5, count 2 2006.162.07:54:42.41#ibcon#about to read 3, iclass 5, count 2 2006.162.07:54:42.43#ibcon#read 3, iclass 5, count 2 2006.162.07:54:42.43#ibcon#about to read 4, iclass 5, count 2 2006.162.07:54:42.43#ibcon#read 4, iclass 5, count 2 2006.162.07:54:42.43#ibcon#about to read 5, iclass 5, count 2 2006.162.07:54:42.43#ibcon#read 5, iclass 5, count 2 2006.162.07:54:42.43#ibcon#about to read 6, iclass 5, count 2 2006.162.07:54:42.43#ibcon#read 6, iclass 5, count 2 2006.162.07:54:42.43#ibcon#end of sib2, iclass 5, count 2 2006.162.07:54:42.43#ibcon#*mode == 0, iclass 5, count 2 2006.162.07:54:42.43#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.162.07:54:42.43#ibcon#[27=AT02-04\r\n] 2006.162.07:54:42.43#ibcon#*before write, iclass 5, count 2 2006.162.07:54:42.43#ibcon#enter sib2, iclass 5, count 2 2006.162.07:54:42.43#ibcon#flushed, iclass 5, count 2 2006.162.07:54:42.43#ibcon#about to write, iclass 5, count 2 2006.162.07:54:42.43#ibcon#wrote, iclass 5, count 2 2006.162.07:54:42.43#ibcon#about to read 3, iclass 5, count 2 2006.162.07:54:42.46#ibcon#read 3, iclass 5, count 2 2006.162.07:54:42.46#ibcon#about to read 4, iclass 5, count 2 2006.162.07:54:42.46#ibcon#read 4, iclass 5, count 2 2006.162.07:54:42.46#ibcon#about to read 5, iclass 5, count 2 2006.162.07:54:42.46#ibcon#read 5, iclass 5, count 2 2006.162.07:54:42.46#ibcon#about to read 6, iclass 5, count 2 2006.162.07:54:42.46#ibcon#read 6, iclass 5, count 2 2006.162.07:54:42.46#ibcon#end of sib2, iclass 5, count 2 2006.162.07:54:42.46#ibcon#*after write, iclass 5, count 2 2006.162.07:54:42.46#ibcon#*before return 0, iclass 5, count 2 2006.162.07:54:42.46#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.162.07:54:42.46#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.162.07:54:42.46#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.162.07:54:42.46#ibcon#ireg 7 cls_cnt 0 2006.162.07:54:42.46#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.162.07:54:42.58#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.162.07:54:42.58#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.162.07:54:42.58#ibcon#enter wrdev, iclass 5, count 0 2006.162.07:54:42.58#ibcon#first serial, iclass 5, count 0 2006.162.07:54:42.58#ibcon#enter sib2, iclass 5, count 0 2006.162.07:54:42.58#ibcon#flushed, iclass 5, count 0 2006.162.07:54:42.58#ibcon#about to write, iclass 5, count 0 2006.162.07:54:42.58#ibcon#wrote, iclass 5, count 0 2006.162.07:54:42.58#ibcon#about to read 3, iclass 5, count 0 2006.162.07:54:42.60#ibcon#read 3, iclass 5, count 0 2006.162.07:54:42.60#ibcon#about to read 4, iclass 5, count 0 2006.162.07:54:42.60#ibcon#read 4, iclass 5, count 0 2006.162.07:54:42.60#ibcon#about to read 5, iclass 5, count 0 2006.162.07:54:42.60#ibcon#read 5, iclass 5, count 0 2006.162.07:54:42.60#ibcon#about to read 6, iclass 5, count 0 2006.162.07:54:42.60#ibcon#read 6, iclass 5, count 0 2006.162.07:54:42.60#ibcon#end of sib2, iclass 5, count 0 2006.162.07:54:42.60#ibcon#*mode == 0, iclass 5, count 0 2006.162.07:54:42.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.162.07:54:42.60#ibcon#[27=USB\r\n] 2006.162.07:54:42.60#ibcon#*before write, iclass 5, count 0 2006.162.07:54:42.60#ibcon#enter sib2, iclass 5, count 0 2006.162.07:54:42.60#ibcon#flushed, iclass 5, count 0 2006.162.07:54:42.60#ibcon#about to write, iclass 5, count 0 2006.162.07:54:42.60#ibcon#wrote, iclass 5, count 0 2006.162.07:54:42.60#ibcon#about to read 3, iclass 5, count 0 2006.162.07:54:42.63#ibcon#read 3, iclass 5, count 0 2006.162.07:54:42.63#ibcon#about to read 4, iclass 5, count 0 2006.162.07:54:42.63#ibcon#read 4, iclass 5, count 0 2006.162.07:54:42.63#ibcon#about to read 5, iclass 5, count 0 2006.162.07:54:42.63#ibcon#read 5, iclass 5, count 0 2006.162.07:54:42.63#ibcon#about to read 6, iclass 5, count 0 2006.162.07:54:42.63#ibcon#read 6, iclass 5, count 0 2006.162.07:54:42.63#ibcon#end of sib2, iclass 5, count 0 2006.162.07:54:42.63#ibcon#*after write, iclass 5, count 0 2006.162.07:54:42.63#ibcon#*before return 0, iclass 5, count 0 2006.162.07:54:42.63#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.162.07:54:42.63#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.162.07:54:42.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.162.07:54:42.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.162.07:54:42.63$vc4f8/vblo=3,656.99 2006.162.07:54:42.64#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.162.07:54:42.64#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.162.07:54:42.64#ibcon#ireg 17 cls_cnt 0 2006.162.07:54:42.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:54:42.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:54:42.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:54:42.64#ibcon#enter wrdev, iclass 7, count 0 2006.162.07:54:42.64#ibcon#first serial, iclass 7, count 0 2006.162.07:54:42.64#ibcon#enter sib2, iclass 7, count 0 2006.162.07:54:42.64#ibcon#flushed, iclass 7, count 0 2006.162.07:54:42.64#ibcon#about to write, iclass 7, count 0 2006.162.07:54:42.64#ibcon#wrote, iclass 7, count 0 2006.162.07:54:42.64#ibcon#about to read 3, iclass 7, count 0 2006.162.07:54:42.65#ibcon#read 3, iclass 7, count 0 2006.162.07:54:42.65#ibcon#about to read 4, iclass 7, count 0 2006.162.07:54:42.65#ibcon#read 4, iclass 7, count 0 2006.162.07:54:42.65#ibcon#about to read 5, iclass 7, count 0 2006.162.07:54:42.65#ibcon#read 5, iclass 7, count 0 2006.162.07:54:42.65#ibcon#about to read 6, iclass 7, count 0 2006.162.07:54:42.65#ibcon#read 6, iclass 7, count 0 2006.162.07:54:42.65#ibcon#end of sib2, iclass 7, count 0 2006.162.07:54:42.65#ibcon#*mode == 0, iclass 7, count 0 2006.162.07:54:42.65#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.162.07:54:42.65#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.07:54:42.65#ibcon#*before write, iclass 7, count 0 2006.162.07:54:42.65#ibcon#enter sib2, iclass 7, count 0 2006.162.07:54:42.65#ibcon#flushed, iclass 7, count 0 2006.162.07:54:42.65#ibcon#about to write, iclass 7, count 0 2006.162.07:54:42.65#ibcon#wrote, iclass 7, count 0 2006.162.07:54:42.65#ibcon#about to read 3, iclass 7, count 0 2006.162.07:54:42.69#ibcon#read 3, iclass 7, count 0 2006.162.07:54:42.69#ibcon#about to read 4, iclass 7, count 0 2006.162.07:54:42.69#ibcon#read 4, iclass 7, count 0 2006.162.07:54:42.69#ibcon#about to read 5, iclass 7, count 0 2006.162.07:54:42.69#ibcon#read 5, iclass 7, count 0 2006.162.07:54:42.69#ibcon#about to read 6, iclass 7, count 0 2006.162.07:54:42.69#ibcon#read 6, iclass 7, count 0 2006.162.07:54:42.69#ibcon#end of sib2, iclass 7, count 0 2006.162.07:54:42.69#ibcon#*after write, iclass 7, count 0 2006.162.07:54:42.69#ibcon#*before return 0, iclass 7, count 0 2006.162.07:54:42.69#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:54:42.69#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.162.07:54:42.69#ibcon#about to clear, iclass 7 cls_cnt 0 2006.162.07:54:42.69#ibcon#cleared, iclass 7 cls_cnt 0 2006.162.07:54:42.69$vc4f8/vb=3,4 2006.162.07:54:42.70#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.162.07:54:42.70#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.162.07:54:42.70#ibcon#ireg 11 cls_cnt 2 2006.162.07:54:42.70#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:54:42.74#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:54:42.74#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:54:42.74#ibcon#enter wrdev, iclass 11, count 2 2006.162.07:54:42.74#ibcon#first serial, iclass 11, count 2 2006.162.07:54:42.74#ibcon#enter sib2, iclass 11, count 2 2006.162.07:54:42.74#ibcon#flushed, iclass 11, count 2 2006.162.07:54:42.74#ibcon#about to write, iclass 11, count 2 2006.162.07:54:42.74#ibcon#wrote, iclass 11, count 2 2006.162.07:54:42.74#ibcon#about to read 3, iclass 11, count 2 2006.162.07:54:42.76#ibcon#read 3, iclass 11, count 2 2006.162.07:54:42.76#ibcon#about to read 4, iclass 11, count 2 2006.162.07:54:42.76#ibcon#read 4, iclass 11, count 2 2006.162.07:54:42.76#ibcon#about to read 5, iclass 11, count 2 2006.162.07:54:42.76#ibcon#read 5, iclass 11, count 2 2006.162.07:54:42.76#ibcon#about to read 6, iclass 11, count 2 2006.162.07:54:42.76#ibcon#read 6, iclass 11, count 2 2006.162.07:54:42.76#ibcon#end of sib2, iclass 11, count 2 2006.162.07:54:42.76#ibcon#*mode == 0, iclass 11, count 2 2006.162.07:54:42.76#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.162.07:54:42.76#ibcon#[27=AT03-04\r\n] 2006.162.07:54:42.76#ibcon#*before write, iclass 11, count 2 2006.162.07:54:42.76#ibcon#enter sib2, iclass 11, count 2 2006.162.07:54:42.76#ibcon#flushed, iclass 11, count 2 2006.162.07:54:42.76#ibcon#about to write, iclass 11, count 2 2006.162.07:54:42.76#ibcon#wrote, iclass 11, count 2 2006.162.07:54:42.76#ibcon#about to read 3, iclass 11, count 2 2006.162.07:54:42.79#ibcon#read 3, iclass 11, count 2 2006.162.07:54:42.79#ibcon#about to read 4, iclass 11, count 2 2006.162.07:54:42.79#ibcon#read 4, iclass 11, count 2 2006.162.07:54:42.79#ibcon#about to read 5, iclass 11, count 2 2006.162.07:54:42.79#ibcon#read 5, iclass 11, count 2 2006.162.07:54:42.79#ibcon#about to read 6, iclass 11, count 2 2006.162.07:54:42.79#ibcon#read 6, iclass 11, count 2 2006.162.07:54:42.79#ibcon#end of sib2, iclass 11, count 2 2006.162.07:54:42.79#ibcon#*after write, iclass 11, count 2 2006.162.07:54:42.79#ibcon#*before return 0, iclass 11, count 2 2006.162.07:54:42.79#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:54:42.79#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.162.07:54:42.79#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.162.07:54:42.79#ibcon#ireg 7 cls_cnt 0 2006.162.07:54:42.79#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:54:42.91#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:54:42.91#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:54:42.91#ibcon#enter wrdev, iclass 11, count 0 2006.162.07:54:42.91#ibcon#first serial, iclass 11, count 0 2006.162.07:54:42.91#ibcon#enter sib2, iclass 11, count 0 2006.162.07:54:42.91#ibcon#flushed, iclass 11, count 0 2006.162.07:54:42.91#ibcon#about to write, iclass 11, count 0 2006.162.07:54:42.91#ibcon#wrote, iclass 11, count 0 2006.162.07:54:42.91#ibcon#about to read 3, iclass 11, count 0 2006.162.07:54:42.93#ibcon#read 3, iclass 11, count 0 2006.162.07:54:42.93#ibcon#about to read 4, iclass 11, count 0 2006.162.07:54:42.93#ibcon#read 4, iclass 11, count 0 2006.162.07:54:42.93#ibcon#about to read 5, iclass 11, count 0 2006.162.07:54:42.93#ibcon#read 5, iclass 11, count 0 2006.162.07:54:42.93#ibcon#about to read 6, iclass 11, count 0 2006.162.07:54:42.93#ibcon#read 6, iclass 11, count 0 2006.162.07:54:42.93#ibcon#end of sib2, iclass 11, count 0 2006.162.07:54:42.93#ibcon#*mode == 0, iclass 11, count 0 2006.162.07:54:42.93#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.162.07:54:42.93#ibcon#[27=USB\r\n] 2006.162.07:54:42.93#ibcon#*before write, iclass 11, count 0 2006.162.07:54:42.93#ibcon#enter sib2, iclass 11, count 0 2006.162.07:54:42.93#ibcon#flushed, iclass 11, count 0 2006.162.07:54:42.93#ibcon#about to write, iclass 11, count 0 2006.162.07:54:42.93#ibcon#wrote, iclass 11, count 0 2006.162.07:54:42.93#ibcon#about to read 3, iclass 11, count 0 2006.162.07:54:42.96#ibcon#read 3, iclass 11, count 0 2006.162.07:54:42.96#ibcon#about to read 4, iclass 11, count 0 2006.162.07:54:42.96#ibcon#read 4, iclass 11, count 0 2006.162.07:54:42.96#ibcon#about to read 5, iclass 11, count 0 2006.162.07:54:42.96#ibcon#read 5, iclass 11, count 0 2006.162.07:54:42.96#ibcon#about to read 6, iclass 11, count 0 2006.162.07:54:42.96#ibcon#read 6, iclass 11, count 0 2006.162.07:54:42.96#ibcon#end of sib2, iclass 11, count 0 2006.162.07:54:42.96#ibcon#*after write, iclass 11, count 0 2006.162.07:54:42.96#ibcon#*before return 0, iclass 11, count 0 2006.162.07:54:42.96#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:54:42.96#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.162.07:54:42.96#ibcon#about to clear, iclass 11 cls_cnt 0 2006.162.07:54:42.96#ibcon#cleared, iclass 11 cls_cnt 0 2006.162.07:54:42.96$vc4f8/vblo=4,712.99 2006.162.07:54:42.97#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.162.07:54:42.97#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.162.07:54:42.97#ibcon#ireg 17 cls_cnt 0 2006.162.07:54:42.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:54:42.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:54:42.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:54:42.97#ibcon#enter wrdev, iclass 13, count 0 2006.162.07:54:42.97#ibcon#first serial, iclass 13, count 0 2006.162.07:54:42.97#ibcon#enter sib2, iclass 13, count 0 2006.162.07:54:42.97#ibcon#flushed, iclass 13, count 0 2006.162.07:54:42.97#ibcon#about to write, iclass 13, count 0 2006.162.07:54:42.97#ibcon#wrote, iclass 13, count 0 2006.162.07:54:42.97#ibcon#about to read 3, iclass 13, count 0 2006.162.07:54:42.98#ibcon#read 3, iclass 13, count 0 2006.162.07:54:42.98#ibcon#about to read 4, iclass 13, count 0 2006.162.07:54:42.98#ibcon#read 4, iclass 13, count 0 2006.162.07:54:42.98#ibcon#about to read 5, iclass 13, count 0 2006.162.07:54:42.98#ibcon#read 5, iclass 13, count 0 2006.162.07:54:42.98#ibcon#about to read 6, iclass 13, count 0 2006.162.07:54:42.98#ibcon#read 6, iclass 13, count 0 2006.162.07:54:42.98#ibcon#end of sib2, iclass 13, count 0 2006.162.07:54:42.98#ibcon#*mode == 0, iclass 13, count 0 2006.162.07:54:42.98#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.162.07:54:42.98#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.07:54:42.98#ibcon#*before write, iclass 13, count 0 2006.162.07:54:42.98#ibcon#enter sib2, iclass 13, count 0 2006.162.07:54:42.98#ibcon#flushed, iclass 13, count 0 2006.162.07:54:42.98#ibcon#about to write, iclass 13, count 0 2006.162.07:54:42.98#ibcon#wrote, iclass 13, count 0 2006.162.07:54:42.98#ibcon#about to read 3, iclass 13, count 0 2006.162.07:54:43.02#ibcon#read 3, iclass 13, count 0 2006.162.07:54:43.02#ibcon#about to read 4, iclass 13, count 0 2006.162.07:54:43.02#ibcon#read 4, iclass 13, count 0 2006.162.07:54:43.02#ibcon#about to read 5, iclass 13, count 0 2006.162.07:54:43.02#ibcon#read 5, iclass 13, count 0 2006.162.07:54:43.02#ibcon#about to read 6, iclass 13, count 0 2006.162.07:54:43.02#ibcon#read 6, iclass 13, count 0 2006.162.07:54:43.02#ibcon#end of sib2, iclass 13, count 0 2006.162.07:54:43.02#ibcon#*after write, iclass 13, count 0 2006.162.07:54:43.02#ibcon#*before return 0, iclass 13, count 0 2006.162.07:54:43.02#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:54:43.02#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.162.07:54:43.02#ibcon#about to clear, iclass 13 cls_cnt 0 2006.162.07:54:43.02#ibcon#cleared, iclass 13 cls_cnt 0 2006.162.07:54:43.02$vc4f8/vb=4,4 2006.162.07:54:43.03#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.162.07:54:43.03#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.162.07:54:43.03#ibcon#ireg 11 cls_cnt 2 2006.162.07:54:43.03#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:54:43.07#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:54:43.07#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:54:43.07#ibcon#enter wrdev, iclass 15, count 2 2006.162.07:54:43.07#ibcon#first serial, iclass 15, count 2 2006.162.07:54:43.07#ibcon#enter sib2, iclass 15, count 2 2006.162.07:54:43.07#ibcon#flushed, iclass 15, count 2 2006.162.07:54:43.07#ibcon#about to write, iclass 15, count 2 2006.162.07:54:43.07#ibcon#wrote, iclass 15, count 2 2006.162.07:54:43.07#ibcon#about to read 3, iclass 15, count 2 2006.162.07:54:43.09#ibcon#read 3, iclass 15, count 2 2006.162.07:54:43.09#ibcon#about to read 4, iclass 15, count 2 2006.162.07:54:43.09#ibcon#read 4, iclass 15, count 2 2006.162.07:54:43.09#ibcon#about to read 5, iclass 15, count 2 2006.162.07:54:43.09#ibcon#read 5, iclass 15, count 2 2006.162.07:54:43.09#ibcon#about to read 6, iclass 15, count 2 2006.162.07:54:43.09#ibcon#read 6, iclass 15, count 2 2006.162.07:54:43.09#ibcon#end of sib2, iclass 15, count 2 2006.162.07:54:43.09#ibcon#*mode == 0, iclass 15, count 2 2006.162.07:54:43.09#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.162.07:54:43.09#ibcon#[27=AT04-04\r\n] 2006.162.07:54:43.09#ibcon#*before write, iclass 15, count 2 2006.162.07:54:43.09#ibcon#enter sib2, iclass 15, count 2 2006.162.07:54:43.09#ibcon#flushed, iclass 15, count 2 2006.162.07:54:43.09#ibcon#about to write, iclass 15, count 2 2006.162.07:54:43.09#ibcon#wrote, iclass 15, count 2 2006.162.07:54:43.09#ibcon#about to read 3, iclass 15, count 2 2006.162.07:54:43.12#ibcon#read 3, iclass 15, count 2 2006.162.07:54:43.12#ibcon#about to read 4, iclass 15, count 2 2006.162.07:54:43.12#ibcon#read 4, iclass 15, count 2 2006.162.07:54:43.12#ibcon#about to read 5, iclass 15, count 2 2006.162.07:54:43.12#ibcon#read 5, iclass 15, count 2 2006.162.07:54:43.12#ibcon#about to read 6, iclass 15, count 2 2006.162.07:54:43.12#ibcon#read 6, iclass 15, count 2 2006.162.07:54:43.12#ibcon#end of sib2, iclass 15, count 2 2006.162.07:54:43.12#ibcon#*after write, iclass 15, count 2 2006.162.07:54:43.12#ibcon#*before return 0, iclass 15, count 2 2006.162.07:54:43.12#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:54:43.12#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.162.07:54:43.12#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.162.07:54:43.12#ibcon#ireg 7 cls_cnt 0 2006.162.07:54:43.12#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:54:43.24#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:54:43.24#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:54:43.24#ibcon#enter wrdev, iclass 15, count 0 2006.162.07:54:43.24#ibcon#first serial, iclass 15, count 0 2006.162.07:54:43.24#ibcon#enter sib2, iclass 15, count 0 2006.162.07:54:43.24#ibcon#flushed, iclass 15, count 0 2006.162.07:54:43.24#ibcon#about to write, iclass 15, count 0 2006.162.07:54:43.24#ibcon#wrote, iclass 15, count 0 2006.162.07:54:43.24#ibcon#about to read 3, iclass 15, count 0 2006.162.07:54:43.26#ibcon#read 3, iclass 15, count 0 2006.162.07:54:43.26#ibcon#about to read 4, iclass 15, count 0 2006.162.07:54:43.26#ibcon#read 4, iclass 15, count 0 2006.162.07:54:43.26#ibcon#about to read 5, iclass 15, count 0 2006.162.07:54:43.26#ibcon#read 5, iclass 15, count 0 2006.162.07:54:43.26#ibcon#about to read 6, iclass 15, count 0 2006.162.07:54:43.26#ibcon#read 6, iclass 15, count 0 2006.162.07:54:43.26#ibcon#end of sib2, iclass 15, count 0 2006.162.07:54:43.26#ibcon#*mode == 0, iclass 15, count 0 2006.162.07:54:43.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.162.07:54:43.26#ibcon#[27=USB\r\n] 2006.162.07:54:43.26#ibcon#*before write, iclass 15, count 0 2006.162.07:54:43.26#ibcon#enter sib2, iclass 15, count 0 2006.162.07:54:43.26#ibcon#flushed, iclass 15, count 0 2006.162.07:54:43.26#ibcon#about to write, iclass 15, count 0 2006.162.07:54:43.26#ibcon#wrote, iclass 15, count 0 2006.162.07:54:43.26#ibcon#about to read 3, iclass 15, count 0 2006.162.07:54:43.29#ibcon#read 3, iclass 15, count 0 2006.162.07:54:43.29#ibcon#about to read 4, iclass 15, count 0 2006.162.07:54:43.29#ibcon#read 4, iclass 15, count 0 2006.162.07:54:43.29#ibcon#about to read 5, iclass 15, count 0 2006.162.07:54:43.29#ibcon#read 5, iclass 15, count 0 2006.162.07:54:43.29#ibcon#about to read 6, iclass 15, count 0 2006.162.07:54:43.29#ibcon#read 6, iclass 15, count 0 2006.162.07:54:43.29#ibcon#end of sib2, iclass 15, count 0 2006.162.07:54:43.29#ibcon#*after write, iclass 15, count 0 2006.162.07:54:43.29#ibcon#*before return 0, iclass 15, count 0 2006.162.07:54:43.29#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:54:43.29#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.162.07:54:43.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.162.07:54:43.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.162.07:54:43.29$vc4f8/vblo=5,744.99 2006.162.07:54:43.30#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.162.07:54:43.30#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.162.07:54:43.30#ibcon#ireg 17 cls_cnt 0 2006.162.07:54:43.30#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:54:43.30#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:54:43.30#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:54:43.30#ibcon#enter wrdev, iclass 17, count 0 2006.162.07:54:43.30#ibcon#first serial, iclass 17, count 0 2006.162.07:54:43.30#ibcon#enter sib2, iclass 17, count 0 2006.162.07:54:43.30#ibcon#flushed, iclass 17, count 0 2006.162.07:54:43.30#ibcon#about to write, iclass 17, count 0 2006.162.07:54:43.30#ibcon#wrote, iclass 17, count 0 2006.162.07:54:43.30#ibcon#about to read 3, iclass 17, count 0 2006.162.07:54:43.31#ibcon#read 3, iclass 17, count 0 2006.162.07:54:43.31#ibcon#about to read 4, iclass 17, count 0 2006.162.07:54:43.31#ibcon#read 4, iclass 17, count 0 2006.162.07:54:43.31#ibcon#about to read 5, iclass 17, count 0 2006.162.07:54:43.31#ibcon#read 5, iclass 17, count 0 2006.162.07:54:43.31#ibcon#about to read 6, iclass 17, count 0 2006.162.07:54:43.31#ibcon#read 6, iclass 17, count 0 2006.162.07:54:43.31#ibcon#end of sib2, iclass 17, count 0 2006.162.07:54:43.31#ibcon#*mode == 0, iclass 17, count 0 2006.162.07:54:43.31#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.162.07:54:43.31#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.07:54:43.31#ibcon#*before write, iclass 17, count 0 2006.162.07:54:43.31#ibcon#enter sib2, iclass 17, count 0 2006.162.07:54:43.31#ibcon#flushed, iclass 17, count 0 2006.162.07:54:43.31#ibcon#about to write, iclass 17, count 0 2006.162.07:54:43.31#ibcon#wrote, iclass 17, count 0 2006.162.07:54:43.31#ibcon#about to read 3, iclass 17, count 0 2006.162.07:54:43.35#ibcon#read 3, iclass 17, count 0 2006.162.07:54:43.35#ibcon#about to read 4, iclass 17, count 0 2006.162.07:54:43.35#ibcon#read 4, iclass 17, count 0 2006.162.07:54:43.35#ibcon#about to read 5, iclass 17, count 0 2006.162.07:54:43.35#ibcon#read 5, iclass 17, count 0 2006.162.07:54:43.35#ibcon#about to read 6, iclass 17, count 0 2006.162.07:54:43.35#ibcon#read 6, iclass 17, count 0 2006.162.07:54:43.35#ibcon#end of sib2, iclass 17, count 0 2006.162.07:54:43.35#ibcon#*after write, iclass 17, count 0 2006.162.07:54:43.35#ibcon#*before return 0, iclass 17, count 0 2006.162.07:54:43.35#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:54:43.35#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.162.07:54:43.35#ibcon#about to clear, iclass 17 cls_cnt 0 2006.162.07:54:43.35#ibcon#cleared, iclass 17 cls_cnt 0 2006.162.07:54:43.35$vc4f8/vb=5,4 2006.162.07:54:43.36#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.162.07:54:43.36#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.162.07:54:43.36#ibcon#ireg 11 cls_cnt 2 2006.162.07:54:43.36#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:54:43.40#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:54:43.40#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:54:43.40#ibcon#enter wrdev, iclass 19, count 2 2006.162.07:54:43.40#ibcon#first serial, iclass 19, count 2 2006.162.07:54:43.40#ibcon#enter sib2, iclass 19, count 2 2006.162.07:54:43.40#ibcon#flushed, iclass 19, count 2 2006.162.07:54:43.40#ibcon#about to write, iclass 19, count 2 2006.162.07:54:43.40#ibcon#wrote, iclass 19, count 2 2006.162.07:54:43.40#ibcon#about to read 3, iclass 19, count 2 2006.162.07:54:43.42#ibcon#read 3, iclass 19, count 2 2006.162.07:54:43.42#ibcon#about to read 4, iclass 19, count 2 2006.162.07:54:43.42#ibcon#read 4, iclass 19, count 2 2006.162.07:54:43.42#ibcon#about to read 5, iclass 19, count 2 2006.162.07:54:43.42#ibcon#read 5, iclass 19, count 2 2006.162.07:54:43.42#ibcon#about to read 6, iclass 19, count 2 2006.162.07:54:43.42#ibcon#read 6, iclass 19, count 2 2006.162.07:54:43.42#ibcon#end of sib2, iclass 19, count 2 2006.162.07:54:43.42#ibcon#*mode == 0, iclass 19, count 2 2006.162.07:54:43.42#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.162.07:54:43.42#ibcon#[27=AT05-04\r\n] 2006.162.07:54:43.42#ibcon#*before write, iclass 19, count 2 2006.162.07:54:43.42#ibcon#enter sib2, iclass 19, count 2 2006.162.07:54:43.42#ibcon#flushed, iclass 19, count 2 2006.162.07:54:43.42#ibcon#about to write, iclass 19, count 2 2006.162.07:54:43.42#ibcon#wrote, iclass 19, count 2 2006.162.07:54:43.42#ibcon#about to read 3, iclass 19, count 2 2006.162.07:54:43.46#ibcon#read 3, iclass 19, count 2 2006.162.07:54:43.46#ibcon#about to read 4, iclass 19, count 2 2006.162.07:54:43.46#ibcon#read 4, iclass 19, count 2 2006.162.07:54:43.46#ibcon#about to read 5, iclass 19, count 2 2006.162.07:54:43.46#ibcon#read 5, iclass 19, count 2 2006.162.07:54:43.46#ibcon#about to read 6, iclass 19, count 2 2006.162.07:54:43.46#ibcon#read 6, iclass 19, count 2 2006.162.07:54:43.46#ibcon#end of sib2, iclass 19, count 2 2006.162.07:54:43.46#ibcon#*after write, iclass 19, count 2 2006.162.07:54:43.46#ibcon#*before return 0, iclass 19, count 2 2006.162.07:54:43.46#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:54:43.46#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.162.07:54:43.46#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.162.07:54:43.46#ibcon#ireg 7 cls_cnt 0 2006.162.07:54:43.46#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:54:43.57#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:54:43.57#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:54:43.57#ibcon#enter wrdev, iclass 19, count 0 2006.162.07:54:43.57#ibcon#first serial, iclass 19, count 0 2006.162.07:54:43.57#ibcon#enter sib2, iclass 19, count 0 2006.162.07:54:43.57#ibcon#flushed, iclass 19, count 0 2006.162.07:54:43.57#ibcon#about to write, iclass 19, count 0 2006.162.07:54:43.57#ibcon#wrote, iclass 19, count 0 2006.162.07:54:43.57#ibcon#about to read 3, iclass 19, count 0 2006.162.07:54:43.59#ibcon#read 3, iclass 19, count 0 2006.162.07:54:43.59#ibcon#about to read 4, iclass 19, count 0 2006.162.07:54:43.59#ibcon#read 4, iclass 19, count 0 2006.162.07:54:43.59#ibcon#about to read 5, iclass 19, count 0 2006.162.07:54:43.59#ibcon#read 5, iclass 19, count 0 2006.162.07:54:43.59#ibcon#about to read 6, iclass 19, count 0 2006.162.07:54:43.59#ibcon#read 6, iclass 19, count 0 2006.162.07:54:43.59#ibcon#end of sib2, iclass 19, count 0 2006.162.07:54:43.59#ibcon#*mode == 0, iclass 19, count 0 2006.162.07:54:43.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.162.07:54:43.59#ibcon#[27=USB\r\n] 2006.162.07:54:43.59#ibcon#*before write, iclass 19, count 0 2006.162.07:54:43.59#ibcon#enter sib2, iclass 19, count 0 2006.162.07:54:43.59#ibcon#flushed, iclass 19, count 0 2006.162.07:54:43.59#ibcon#about to write, iclass 19, count 0 2006.162.07:54:43.59#ibcon#wrote, iclass 19, count 0 2006.162.07:54:43.59#ibcon#about to read 3, iclass 19, count 0 2006.162.07:54:43.62#ibcon#read 3, iclass 19, count 0 2006.162.07:54:43.62#ibcon#about to read 4, iclass 19, count 0 2006.162.07:54:43.62#ibcon#read 4, iclass 19, count 0 2006.162.07:54:43.62#ibcon#about to read 5, iclass 19, count 0 2006.162.07:54:43.62#ibcon#read 5, iclass 19, count 0 2006.162.07:54:43.62#ibcon#about to read 6, iclass 19, count 0 2006.162.07:54:43.62#ibcon#read 6, iclass 19, count 0 2006.162.07:54:43.62#ibcon#end of sib2, iclass 19, count 0 2006.162.07:54:43.62#ibcon#*after write, iclass 19, count 0 2006.162.07:54:43.62#ibcon#*before return 0, iclass 19, count 0 2006.162.07:54:43.62#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:54:43.62#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.162.07:54:43.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.162.07:54:43.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.162.07:54:43.62$vc4f8/vblo=6,752.99 2006.162.07:54:43.63#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.162.07:54:43.63#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.162.07:54:43.63#ibcon#ireg 17 cls_cnt 0 2006.162.07:54:43.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:54:43.63#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:54:43.63#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:54:43.63#ibcon#enter wrdev, iclass 21, count 0 2006.162.07:54:43.63#ibcon#first serial, iclass 21, count 0 2006.162.07:54:43.63#ibcon#enter sib2, iclass 21, count 0 2006.162.07:54:43.63#ibcon#flushed, iclass 21, count 0 2006.162.07:54:43.63#ibcon#about to write, iclass 21, count 0 2006.162.07:54:43.63#ibcon#wrote, iclass 21, count 0 2006.162.07:54:43.63#ibcon#about to read 3, iclass 21, count 0 2006.162.07:54:43.64#ibcon#read 3, iclass 21, count 0 2006.162.07:54:43.64#ibcon#about to read 4, iclass 21, count 0 2006.162.07:54:43.64#ibcon#read 4, iclass 21, count 0 2006.162.07:54:43.64#ibcon#about to read 5, iclass 21, count 0 2006.162.07:54:43.64#ibcon#read 5, iclass 21, count 0 2006.162.07:54:43.64#ibcon#about to read 6, iclass 21, count 0 2006.162.07:54:43.64#ibcon#read 6, iclass 21, count 0 2006.162.07:54:43.64#ibcon#end of sib2, iclass 21, count 0 2006.162.07:54:43.64#ibcon#*mode == 0, iclass 21, count 0 2006.162.07:54:43.64#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.162.07:54:43.64#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.07:54:43.64#ibcon#*before write, iclass 21, count 0 2006.162.07:54:43.64#ibcon#enter sib2, iclass 21, count 0 2006.162.07:54:43.64#ibcon#flushed, iclass 21, count 0 2006.162.07:54:43.64#ibcon#about to write, iclass 21, count 0 2006.162.07:54:43.64#ibcon#wrote, iclass 21, count 0 2006.162.07:54:43.64#ibcon#about to read 3, iclass 21, count 0 2006.162.07:54:43.68#ibcon#read 3, iclass 21, count 0 2006.162.07:54:43.68#ibcon#about to read 4, iclass 21, count 0 2006.162.07:54:43.68#ibcon#read 4, iclass 21, count 0 2006.162.07:54:43.68#ibcon#about to read 5, iclass 21, count 0 2006.162.07:54:43.68#ibcon#read 5, iclass 21, count 0 2006.162.07:54:43.68#ibcon#about to read 6, iclass 21, count 0 2006.162.07:54:43.68#ibcon#read 6, iclass 21, count 0 2006.162.07:54:43.68#ibcon#end of sib2, iclass 21, count 0 2006.162.07:54:43.68#ibcon#*after write, iclass 21, count 0 2006.162.07:54:43.68#ibcon#*before return 0, iclass 21, count 0 2006.162.07:54:43.68#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:54:43.68#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.162.07:54:43.68#ibcon#about to clear, iclass 21 cls_cnt 0 2006.162.07:54:43.68#ibcon#cleared, iclass 21 cls_cnt 0 2006.162.07:54:43.68$vc4f8/vb=6,4 2006.162.07:54:43.69#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.162.07:54:43.69#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.162.07:54:43.69#ibcon#ireg 11 cls_cnt 2 2006.162.07:54:43.69#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.162.07:54:43.73#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.162.07:54:43.73#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.162.07:54:43.73#ibcon#enter wrdev, iclass 23, count 2 2006.162.07:54:43.73#ibcon#first serial, iclass 23, count 2 2006.162.07:54:43.73#ibcon#enter sib2, iclass 23, count 2 2006.162.07:54:43.73#ibcon#flushed, iclass 23, count 2 2006.162.07:54:43.73#ibcon#about to write, iclass 23, count 2 2006.162.07:54:43.73#ibcon#wrote, iclass 23, count 2 2006.162.07:54:43.73#ibcon#about to read 3, iclass 23, count 2 2006.162.07:54:43.75#ibcon#read 3, iclass 23, count 2 2006.162.07:54:43.75#ibcon#about to read 4, iclass 23, count 2 2006.162.07:54:43.75#ibcon#read 4, iclass 23, count 2 2006.162.07:54:43.75#ibcon#about to read 5, iclass 23, count 2 2006.162.07:54:43.75#ibcon#read 5, iclass 23, count 2 2006.162.07:54:43.75#ibcon#about to read 6, iclass 23, count 2 2006.162.07:54:43.75#ibcon#read 6, iclass 23, count 2 2006.162.07:54:43.75#ibcon#end of sib2, iclass 23, count 2 2006.162.07:54:43.75#ibcon#*mode == 0, iclass 23, count 2 2006.162.07:54:43.75#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.162.07:54:43.75#ibcon#[27=AT06-04\r\n] 2006.162.07:54:43.75#ibcon#*before write, iclass 23, count 2 2006.162.07:54:43.75#ibcon#enter sib2, iclass 23, count 2 2006.162.07:54:43.75#ibcon#flushed, iclass 23, count 2 2006.162.07:54:43.75#ibcon#about to write, iclass 23, count 2 2006.162.07:54:43.75#ibcon#wrote, iclass 23, count 2 2006.162.07:54:43.75#ibcon#about to read 3, iclass 23, count 2 2006.162.07:54:43.78#ibcon#read 3, iclass 23, count 2 2006.162.07:54:43.78#ibcon#about to read 4, iclass 23, count 2 2006.162.07:54:43.78#ibcon#read 4, iclass 23, count 2 2006.162.07:54:43.78#ibcon#about to read 5, iclass 23, count 2 2006.162.07:54:43.78#ibcon#read 5, iclass 23, count 2 2006.162.07:54:43.78#ibcon#about to read 6, iclass 23, count 2 2006.162.07:54:43.78#ibcon#read 6, iclass 23, count 2 2006.162.07:54:43.78#ibcon#end of sib2, iclass 23, count 2 2006.162.07:54:43.78#ibcon#*after write, iclass 23, count 2 2006.162.07:54:43.78#ibcon#*before return 0, iclass 23, count 2 2006.162.07:54:43.78#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.162.07:54:43.78#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.162.07:54:43.78#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.162.07:54:43.78#ibcon#ireg 7 cls_cnt 0 2006.162.07:54:43.78#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.162.07:54:43.90#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.162.07:54:43.90#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.162.07:54:43.90#ibcon#enter wrdev, iclass 23, count 0 2006.162.07:54:43.90#ibcon#first serial, iclass 23, count 0 2006.162.07:54:43.90#ibcon#enter sib2, iclass 23, count 0 2006.162.07:54:43.90#ibcon#flushed, iclass 23, count 0 2006.162.07:54:43.90#ibcon#about to write, iclass 23, count 0 2006.162.07:54:43.90#ibcon#wrote, iclass 23, count 0 2006.162.07:54:43.90#ibcon#about to read 3, iclass 23, count 0 2006.162.07:54:43.92#ibcon#read 3, iclass 23, count 0 2006.162.07:54:43.92#ibcon#about to read 4, iclass 23, count 0 2006.162.07:54:43.92#ibcon#read 4, iclass 23, count 0 2006.162.07:54:43.92#ibcon#about to read 5, iclass 23, count 0 2006.162.07:54:43.92#ibcon#read 5, iclass 23, count 0 2006.162.07:54:43.92#ibcon#about to read 6, iclass 23, count 0 2006.162.07:54:43.92#ibcon#read 6, iclass 23, count 0 2006.162.07:54:43.92#ibcon#end of sib2, iclass 23, count 0 2006.162.07:54:43.92#ibcon#*mode == 0, iclass 23, count 0 2006.162.07:54:43.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.162.07:54:43.92#ibcon#[27=USB\r\n] 2006.162.07:54:43.92#ibcon#*before write, iclass 23, count 0 2006.162.07:54:43.92#ibcon#enter sib2, iclass 23, count 0 2006.162.07:54:43.92#ibcon#flushed, iclass 23, count 0 2006.162.07:54:43.92#ibcon#about to write, iclass 23, count 0 2006.162.07:54:43.92#ibcon#wrote, iclass 23, count 0 2006.162.07:54:43.92#ibcon#about to read 3, iclass 23, count 0 2006.162.07:54:43.95#ibcon#read 3, iclass 23, count 0 2006.162.07:54:43.95#ibcon#about to read 4, iclass 23, count 0 2006.162.07:54:43.95#ibcon#read 4, iclass 23, count 0 2006.162.07:54:43.95#ibcon#about to read 5, iclass 23, count 0 2006.162.07:54:43.95#ibcon#read 5, iclass 23, count 0 2006.162.07:54:43.95#ibcon#about to read 6, iclass 23, count 0 2006.162.07:54:43.95#ibcon#read 6, iclass 23, count 0 2006.162.07:54:43.95#ibcon#end of sib2, iclass 23, count 0 2006.162.07:54:43.95#ibcon#*after write, iclass 23, count 0 2006.162.07:54:43.95#ibcon#*before return 0, iclass 23, count 0 2006.162.07:54:43.95#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.162.07:54:43.95#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.162.07:54:43.95#ibcon#about to clear, iclass 23 cls_cnt 0 2006.162.07:54:43.95#ibcon#cleared, iclass 23 cls_cnt 0 2006.162.07:54:43.95$vc4f8/vabw=wide 2006.162.07:54:43.96#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.162.07:54:43.96#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.162.07:54:43.96#ibcon#ireg 8 cls_cnt 0 2006.162.07:54:43.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:54:43.96#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:54:43.96#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:54:43.96#ibcon#enter wrdev, iclass 25, count 0 2006.162.07:54:43.96#ibcon#first serial, iclass 25, count 0 2006.162.07:54:43.96#ibcon#enter sib2, iclass 25, count 0 2006.162.07:54:43.96#ibcon#flushed, iclass 25, count 0 2006.162.07:54:43.96#ibcon#about to write, iclass 25, count 0 2006.162.07:54:43.96#ibcon#wrote, iclass 25, count 0 2006.162.07:54:43.96#ibcon#about to read 3, iclass 25, count 0 2006.162.07:54:43.97#ibcon#read 3, iclass 25, count 0 2006.162.07:54:43.97#ibcon#about to read 4, iclass 25, count 0 2006.162.07:54:43.97#ibcon#read 4, iclass 25, count 0 2006.162.07:54:43.97#ibcon#about to read 5, iclass 25, count 0 2006.162.07:54:43.97#ibcon#read 5, iclass 25, count 0 2006.162.07:54:43.97#ibcon#about to read 6, iclass 25, count 0 2006.162.07:54:43.97#ibcon#read 6, iclass 25, count 0 2006.162.07:54:43.97#ibcon#end of sib2, iclass 25, count 0 2006.162.07:54:43.97#ibcon#*mode == 0, iclass 25, count 0 2006.162.07:54:43.97#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.162.07:54:43.97#ibcon#[25=BW32\r\n] 2006.162.07:54:43.97#ibcon#*before write, iclass 25, count 0 2006.162.07:54:43.97#ibcon#enter sib2, iclass 25, count 0 2006.162.07:54:43.97#ibcon#flushed, iclass 25, count 0 2006.162.07:54:43.97#ibcon#about to write, iclass 25, count 0 2006.162.07:54:43.97#ibcon#wrote, iclass 25, count 0 2006.162.07:54:43.97#ibcon#about to read 3, iclass 25, count 0 2006.162.07:54:44.00#ibcon#read 3, iclass 25, count 0 2006.162.07:54:44.00#ibcon#about to read 4, iclass 25, count 0 2006.162.07:54:44.00#ibcon#read 4, iclass 25, count 0 2006.162.07:54:44.00#ibcon#about to read 5, iclass 25, count 0 2006.162.07:54:44.00#ibcon#read 5, iclass 25, count 0 2006.162.07:54:44.00#ibcon#about to read 6, iclass 25, count 0 2006.162.07:54:44.00#ibcon#read 6, iclass 25, count 0 2006.162.07:54:44.00#ibcon#end of sib2, iclass 25, count 0 2006.162.07:54:44.00#ibcon#*after write, iclass 25, count 0 2006.162.07:54:44.00#ibcon#*before return 0, iclass 25, count 0 2006.162.07:54:44.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:54:44.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.162.07:54:44.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.162.07:54:44.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.162.07:54:44.00$vc4f8/vbbw=wide 2006.162.07:54:44.01#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.162.07:54:44.01#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.162.07:54:44.01#ibcon#ireg 8 cls_cnt 0 2006.162.07:54:44.01#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:54:44.06#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:54:44.06#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:54:44.06#ibcon#enter wrdev, iclass 27, count 0 2006.162.07:54:44.06#ibcon#first serial, iclass 27, count 0 2006.162.07:54:44.06#ibcon#enter sib2, iclass 27, count 0 2006.162.07:54:44.06#ibcon#flushed, iclass 27, count 0 2006.162.07:54:44.06#ibcon#about to write, iclass 27, count 0 2006.162.07:54:44.06#ibcon#wrote, iclass 27, count 0 2006.162.07:54:44.06#ibcon#about to read 3, iclass 27, count 0 2006.162.07:54:44.08#ibcon#read 3, iclass 27, count 0 2006.162.07:54:44.08#ibcon#about to read 4, iclass 27, count 0 2006.162.07:54:44.08#ibcon#read 4, iclass 27, count 0 2006.162.07:54:44.08#ibcon#about to read 5, iclass 27, count 0 2006.162.07:54:44.08#ibcon#read 5, iclass 27, count 0 2006.162.07:54:44.08#ibcon#about to read 6, iclass 27, count 0 2006.162.07:54:44.08#ibcon#read 6, iclass 27, count 0 2006.162.07:54:44.08#ibcon#end of sib2, iclass 27, count 0 2006.162.07:54:44.08#ibcon#*mode == 0, iclass 27, count 0 2006.162.07:54:44.08#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.162.07:54:44.08#ibcon#[27=BW32\r\n] 2006.162.07:54:44.08#ibcon#*before write, iclass 27, count 0 2006.162.07:54:44.08#ibcon#enter sib2, iclass 27, count 0 2006.162.07:54:44.08#ibcon#flushed, iclass 27, count 0 2006.162.07:54:44.08#ibcon#about to write, iclass 27, count 0 2006.162.07:54:44.08#ibcon#wrote, iclass 27, count 0 2006.162.07:54:44.08#ibcon#about to read 3, iclass 27, count 0 2006.162.07:54:44.11#ibcon#read 3, iclass 27, count 0 2006.162.07:54:44.11#ibcon#about to read 4, iclass 27, count 0 2006.162.07:54:44.11#ibcon#read 4, iclass 27, count 0 2006.162.07:54:44.11#ibcon#about to read 5, iclass 27, count 0 2006.162.07:54:44.11#ibcon#read 5, iclass 27, count 0 2006.162.07:54:44.11#ibcon#about to read 6, iclass 27, count 0 2006.162.07:54:44.11#ibcon#read 6, iclass 27, count 0 2006.162.07:54:44.11#ibcon#end of sib2, iclass 27, count 0 2006.162.07:54:44.11#ibcon#*after write, iclass 27, count 0 2006.162.07:54:44.11#ibcon#*before return 0, iclass 27, count 0 2006.162.07:54:44.11#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:54:44.11#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.162.07:54:44.11#ibcon#about to clear, iclass 27 cls_cnt 0 2006.162.07:54:44.11#ibcon#cleared, iclass 27 cls_cnt 0 2006.162.07:54:44.11$4f8m12a/ifd4f 2006.162.07:54:44.12$ifd4f/lo= 2006.162.07:54:44.12$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.07:54:44.12$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.07:54:44.12$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.07:54:44.12$ifd4f/patch= 2006.162.07:54:44.12$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.07:54:44.12$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.07:54:44.12$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.07:54:44.12$4f8m12a/"form=m,16.000,1:2 2006.162.07:54:44.12$4f8m12a/"tpicd 2006.162.07:54:44.12$4f8m12a/echo=off 2006.162.07:54:44.12$4f8m12a/xlog=off 2006.162.07:54:44.12:!2006.162.07:56:50 2006.162.07:54:54.14#trakl#Source acquired 2006.162.07:54:55.14#flagr#flagr/antenna,acquired 2006.162.07:56:50.01:preob 2006.162.07:56:51.14/onsource/TRACKING 2006.162.07:56:51.14:!2006.162.07:57:00 2006.162.07:57:00.00:data_valid=on 2006.162.07:57:00.00:midob 2006.162.07:57:00.14/onsource/TRACKING 2006.162.07:57:00.14/wx/17.83,1007.0,100 2006.162.07:57:00.29/cable/+6.5333E-03 2006.162.07:57:01.38/va/01,08,usb,yes,37,39 2006.162.07:57:01.38/va/02,07,usb,yes,38,39 2006.162.07:57:01.38/va/03,06,usb,yes,40,40 2006.162.07:57:01.38/va/04,07,usb,yes,39,41 2006.162.07:57:01.38/va/05,07,usb,yes,41,43 2006.162.07:57:01.38/va/06,06,usb,yes,40,40 2006.162.07:57:01.38/va/07,06,usb,yes,41,41 2006.162.07:57:01.38/va/08,07,usb,yes,39,38 2006.162.07:57:01.61/valo/01,532.99,yes,locked 2006.162.07:57:01.61/valo/02,572.99,yes,locked 2006.162.07:57:01.61/valo/03,672.99,yes,locked 2006.162.07:57:01.61/valo/04,832.99,yes,locked 2006.162.07:57:01.61/valo/05,652.99,yes,locked 2006.162.07:57:01.61/valo/06,772.99,yes,locked 2006.162.07:57:01.61/valo/07,832.99,yes,locked 2006.162.07:57:01.61/valo/08,852.99,yes,locked 2006.162.07:57:02.70/vb/01,04,usb,yes,29,28 2006.162.07:57:02.70/vb/02,04,usb,yes,31,32 2006.162.07:57:02.70/vb/03,04,usb,yes,27,31 2006.162.07:57:02.70/vb/04,04,usb,yes,28,28 2006.162.07:57:02.70/vb/05,04,usb,yes,26,30 2006.162.07:57:02.70/vb/06,04,usb,yes,27,30 2006.162.07:57:02.70/vb/07,04,usb,yes,29,29 2006.162.07:57:02.70/vb/08,04,usb,yes,27,30 2006.162.07:57:02.93/vblo/01,632.99,yes,locked 2006.162.07:57:02.93/vblo/02,640.99,yes,locked 2006.162.07:57:02.93/vblo/03,656.99,yes,locked 2006.162.07:57:02.93/vblo/04,712.99,yes,locked 2006.162.07:57:02.93/vblo/05,744.99,yes,locked 2006.162.07:57:02.93/vblo/06,752.99,yes,locked 2006.162.07:57:02.93/vblo/07,734.99,yes,locked 2006.162.07:57:02.93/vblo/08,744.99,yes,locked 2006.162.07:57:03.08/vabw/8 2006.162.07:57:03.23/vbbw/8 2006.162.07:57:03.32/xfe/off,on,14.7 2006.162.07:57:03.69/ifatt/23,28,28,28 2006.162.07:57:04.07/fmout-gps/S +4.49E-07 2006.162.07:57:04.15:!2006.162.07:58:00 2006.162.07:58:00.01:data_valid=off 2006.162.07:58:00.02:postob 2006.162.07:58:00.16/cable/+6.5353E-03 2006.162.07:58:00.17/wx/17.84,1007.0,100 2006.162.07:58:01.07/fmout-gps/S +4.49E-07 2006.162.07:58:01.08:scan_name=162-0759,k06162,60 2006.162.07:58:01.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.162.07:58:02.13#flagr#flagr/antenna,new-source 2006.162.07:58:02.14:checkk5 2006.162.07:58:02.57/chk_autoobs//k5ts1/ autoobs is running! 2006.162.07:58:02.97/chk_autoobs//k5ts2/ autoobs is running! 2006.162.07:58:03.40/chk_autoobs//k5ts3/ autoobs is running! 2006.162.07:58:03.84/chk_autoobs//k5ts4/ autoobs is running! 2006.162.07:58:04.28/chk_obsdata//k5ts1/T1620757??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:58:04.70/chk_obsdata//k5ts2/T1620757??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:58:05.38/chk_obsdata//k5ts3/T1620757??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:58:05.82/chk_obsdata//k5ts4/T1620757??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.07:58:06.62/k5log//k5ts1_log_newline 2006.162.07:58:07.41/k5log//k5ts2_log_newline 2006.162.07:58:08.19/k5log//k5ts3_log_newline 2006.162.07:58:08.96/k5log//k5ts4_log_newline 2006.162.07:58:08.98/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.07:58:08.98:4f8m12a=2 2006.162.07:58:08.98$4f8m12a/echo=on 2006.162.07:58:08.98$4f8m12a/pcalon 2006.162.07:58:08.98$pcalon/"no phase cal control is implemented here 2006.162.07:58:08.98$4f8m12a/"tpicd=stop 2006.162.07:58:08.98$4f8m12a/vc4f8 2006.162.07:58:08.98$vc4f8/valo=1,532.99 2006.162.07:58:08.99#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.162.07:58:08.99#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.162.07:58:08.99#ibcon#ireg 17 cls_cnt 0 2006.162.07:58:08.99#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.162.07:58:08.99#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.162.07:58:08.99#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.162.07:58:08.99#ibcon#enter wrdev, iclass 38, count 0 2006.162.07:58:08.99#ibcon#first serial, iclass 38, count 0 2006.162.07:58:08.99#ibcon#enter sib2, iclass 38, count 0 2006.162.07:58:08.99#ibcon#flushed, iclass 38, count 0 2006.162.07:58:08.99#ibcon#about to write, iclass 38, count 0 2006.162.07:58:08.99#ibcon#wrote, iclass 38, count 0 2006.162.07:58:08.99#ibcon#about to read 3, iclass 38, count 0 2006.162.07:58:09.03#ibcon#read 3, iclass 38, count 0 2006.162.07:58:09.03#ibcon#about to read 4, iclass 38, count 0 2006.162.07:58:09.03#ibcon#read 4, iclass 38, count 0 2006.162.07:58:09.03#ibcon#about to read 5, iclass 38, count 0 2006.162.07:58:09.03#ibcon#read 5, iclass 38, count 0 2006.162.07:58:09.03#ibcon#about to read 6, iclass 38, count 0 2006.162.07:58:09.03#ibcon#read 6, iclass 38, count 0 2006.162.07:58:09.03#ibcon#end of sib2, iclass 38, count 0 2006.162.07:58:09.03#ibcon#*mode == 0, iclass 38, count 0 2006.162.07:58:09.03#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.162.07:58:09.03#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.07:58:09.03#ibcon#*before write, iclass 38, count 0 2006.162.07:58:09.03#ibcon#enter sib2, iclass 38, count 0 2006.162.07:58:09.03#ibcon#flushed, iclass 38, count 0 2006.162.07:58:09.03#ibcon#about to write, iclass 38, count 0 2006.162.07:58:09.03#ibcon#wrote, iclass 38, count 0 2006.162.07:58:09.03#ibcon#about to read 3, iclass 38, count 0 2006.162.07:58:09.07#ibcon#read 3, iclass 38, count 0 2006.162.07:58:09.07#ibcon#about to read 4, iclass 38, count 0 2006.162.07:58:09.07#ibcon#read 4, iclass 38, count 0 2006.162.07:58:09.07#ibcon#about to read 5, iclass 38, count 0 2006.162.07:58:09.07#ibcon#read 5, iclass 38, count 0 2006.162.07:58:09.07#ibcon#about to read 6, iclass 38, count 0 2006.162.07:58:09.07#ibcon#read 6, iclass 38, count 0 2006.162.07:58:09.07#ibcon#end of sib2, iclass 38, count 0 2006.162.07:58:09.07#ibcon#*after write, iclass 38, count 0 2006.162.07:58:09.07#ibcon#*before return 0, iclass 38, count 0 2006.162.07:58:09.07#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.162.07:58:09.07#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.162.07:58:09.07#ibcon#about to clear, iclass 38 cls_cnt 0 2006.162.07:58:09.07#ibcon#cleared, iclass 38 cls_cnt 0 2006.162.07:58:09.07$vc4f8/va=1,8 2006.162.07:58:09.07#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.162.07:58:09.07#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.162.07:58:09.07#ibcon#ireg 11 cls_cnt 2 2006.162.07:58:09.07#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.162.07:58:09.07#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.162.07:58:09.07#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.162.07:58:09.07#ibcon#enter wrdev, iclass 40, count 2 2006.162.07:58:09.07#ibcon#first serial, iclass 40, count 2 2006.162.07:58:09.07#ibcon#enter sib2, iclass 40, count 2 2006.162.07:58:09.07#ibcon#flushed, iclass 40, count 2 2006.162.07:58:09.07#ibcon#about to write, iclass 40, count 2 2006.162.07:58:09.07#ibcon#wrote, iclass 40, count 2 2006.162.07:58:09.07#ibcon#about to read 3, iclass 40, count 2 2006.162.07:58:09.09#ibcon#read 3, iclass 40, count 2 2006.162.07:58:09.09#ibcon#about to read 4, iclass 40, count 2 2006.162.07:58:09.09#ibcon#read 4, iclass 40, count 2 2006.162.07:58:09.09#ibcon#about to read 5, iclass 40, count 2 2006.162.07:58:09.09#ibcon#read 5, iclass 40, count 2 2006.162.07:58:09.09#ibcon#about to read 6, iclass 40, count 2 2006.162.07:58:09.09#ibcon#read 6, iclass 40, count 2 2006.162.07:58:09.09#ibcon#end of sib2, iclass 40, count 2 2006.162.07:58:09.09#ibcon#*mode == 0, iclass 40, count 2 2006.162.07:58:09.09#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.162.07:58:09.09#ibcon#[25=AT01-08\r\n] 2006.162.07:58:09.09#ibcon#*before write, iclass 40, count 2 2006.162.07:58:09.09#ibcon#enter sib2, iclass 40, count 2 2006.162.07:58:09.09#ibcon#flushed, iclass 40, count 2 2006.162.07:58:09.09#ibcon#about to write, iclass 40, count 2 2006.162.07:58:09.09#ibcon#wrote, iclass 40, count 2 2006.162.07:58:09.09#ibcon#about to read 3, iclass 40, count 2 2006.162.07:58:09.12#ibcon#read 3, iclass 40, count 2 2006.162.07:58:09.12#ibcon#about to read 4, iclass 40, count 2 2006.162.07:58:09.12#ibcon#read 4, iclass 40, count 2 2006.162.07:58:09.12#ibcon#about to read 5, iclass 40, count 2 2006.162.07:58:09.12#ibcon#read 5, iclass 40, count 2 2006.162.07:58:09.12#ibcon#about to read 6, iclass 40, count 2 2006.162.07:58:09.12#ibcon#read 6, iclass 40, count 2 2006.162.07:58:09.12#ibcon#end of sib2, iclass 40, count 2 2006.162.07:58:09.12#ibcon#*after write, iclass 40, count 2 2006.162.07:58:09.12#ibcon#*before return 0, iclass 40, count 2 2006.162.07:58:09.12#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.162.07:58:09.12#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.162.07:58:09.12#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.162.07:58:09.12#ibcon#ireg 7 cls_cnt 0 2006.162.07:58:09.12#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.162.07:58:09.24#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.162.07:58:09.24#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.162.07:58:09.24#ibcon#enter wrdev, iclass 40, count 0 2006.162.07:58:09.24#ibcon#first serial, iclass 40, count 0 2006.162.07:58:09.24#ibcon#enter sib2, iclass 40, count 0 2006.162.07:58:09.24#ibcon#flushed, iclass 40, count 0 2006.162.07:58:09.24#ibcon#about to write, iclass 40, count 0 2006.162.07:58:09.24#ibcon#wrote, iclass 40, count 0 2006.162.07:58:09.24#ibcon#about to read 3, iclass 40, count 0 2006.162.07:58:09.26#ibcon#read 3, iclass 40, count 0 2006.162.07:58:09.26#ibcon#about to read 4, iclass 40, count 0 2006.162.07:58:09.26#ibcon#read 4, iclass 40, count 0 2006.162.07:58:09.26#ibcon#about to read 5, iclass 40, count 0 2006.162.07:58:09.26#ibcon#read 5, iclass 40, count 0 2006.162.07:58:09.26#ibcon#about to read 6, iclass 40, count 0 2006.162.07:58:09.26#ibcon#read 6, iclass 40, count 0 2006.162.07:58:09.26#ibcon#end of sib2, iclass 40, count 0 2006.162.07:58:09.26#ibcon#*mode == 0, iclass 40, count 0 2006.162.07:58:09.26#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.162.07:58:09.26#ibcon#[25=USB\r\n] 2006.162.07:58:09.26#ibcon#*before write, iclass 40, count 0 2006.162.07:58:09.26#ibcon#enter sib2, iclass 40, count 0 2006.162.07:58:09.26#ibcon#flushed, iclass 40, count 0 2006.162.07:58:09.26#ibcon#about to write, iclass 40, count 0 2006.162.07:58:09.26#ibcon#wrote, iclass 40, count 0 2006.162.07:58:09.26#ibcon#about to read 3, iclass 40, count 0 2006.162.07:58:09.29#ibcon#read 3, iclass 40, count 0 2006.162.07:58:09.29#ibcon#about to read 4, iclass 40, count 0 2006.162.07:58:09.29#ibcon#read 4, iclass 40, count 0 2006.162.07:58:09.29#ibcon#about to read 5, iclass 40, count 0 2006.162.07:58:09.29#ibcon#read 5, iclass 40, count 0 2006.162.07:58:09.29#ibcon#about to read 6, iclass 40, count 0 2006.162.07:58:09.29#ibcon#read 6, iclass 40, count 0 2006.162.07:58:09.29#ibcon#end of sib2, iclass 40, count 0 2006.162.07:58:09.29#ibcon#*after write, iclass 40, count 0 2006.162.07:58:09.29#ibcon#*before return 0, iclass 40, count 0 2006.162.07:58:09.29#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.162.07:58:09.29#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.162.07:58:09.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.162.07:58:09.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.162.07:58:09.29$vc4f8/valo=2,572.99 2006.162.07:58:09.29#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.162.07:58:09.29#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.162.07:58:09.29#ibcon#ireg 17 cls_cnt 0 2006.162.07:58:09.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.162.07:58:09.29#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.162.07:58:09.29#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.162.07:58:09.29#ibcon#enter wrdev, iclass 4, count 0 2006.162.07:58:09.29#ibcon#first serial, iclass 4, count 0 2006.162.07:58:09.29#ibcon#enter sib2, iclass 4, count 0 2006.162.07:58:09.29#ibcon#flushed, iclass 4, count 0 2006.162.07:58:09.29#ibcon#about to write, iclass 4, count 0 2006.162.07:58:09.29#ibcon#wrote, iclass 4, count 0 2006.162.07:58:09.29#ibcon#about to read 3, iclass 4, count 0 2006.162.07:58:09.32#ibcon#read 3, iclass 4, count 0 2006.162.07:58:09.32#ibcon#about to read 4, iclass 4, count 0 2006.162.07:58:09.32#ibcon#read 4, iclass 4, count 0 2006.162.07:58:09.32#ibcon#about to read 5, iclass 4, count 0 2006.162.07:58:09.32#ibcon#read 5, iclass 4, count 0 2006.162.07:58:09.32#ibcon#about to read 6, iclass 4, count 0 2006.162.07:58:09.32#ibcon#read 6, iclass 4, count 0 2006.162.07:58:09.32#ibcon#end of sib2, iclass 4, count 0 2006.162.07:58:09.32#ibcon#*mode == 0, iclass 4, count 0 2006.162.07:58:09.32#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.162.07:58:09.32#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.07:58:09.32#ibcon#*before write, iclass 4, count 0 2006.162.07:58:09.32#ibcon#enter sib2, iclass 4, count 0 2006.162.07:58:09.32#ibcon#flushed, iclass 4, count 0 2006.162.07:58:09.32#ibcon#about to write, iclass 4, count 0 2006.162.07:58:09.32#ibcon#wrote, iclass 4, count 0 2006.162.07:58:09.32#ibcon#about to read 3, iclass 4, count 0 2006.162.07:58:09.36#ibcon#read 3, iclass 4, count 0 2006.162.07:58:09.36#ibcon#about to read 4, iclass 4, count 0 2006.162.07:58:09.36#ibcon#read 4, iclass 4, count 0 2006.162.07:58:09.36#ibcon#about to read 5, iclass 4, count 0 2006.162.07:58:09.36#ibcon#read 5, iclass 4, count 0 2006.162.07:58:09.36#ibcon#about to read 6, iclass 4, count 0 2006.162.07:58:09.36#ibcon#read 6, iclass 4, count 0 2006.162.07:58:09.36#ibcon#end of sib2, iclass 4, count 0 2006.162.07:58:09.36#ibcon#*after write, iclass 4, count 0 2006.162.07:58:09.36#ibcon#*before return 0, iclass 4, count 0 2006.162.07:58:09.36#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.162.07:58:09.36#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.162.07:58:09.36#ibcon#about to clear, iclass 4 cls_cnt 0 2006.162.07:58:09.36#ibcon#cleared, iclass 4 cls_cnt 0 2006.162.07:58:09.36$vc4f8/va=2,7 2006.162.07:58:09.36#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.162.07:58:09.36#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.162.07:58:09.36#ibcon#ireg 11 cls_cnt 2 2006.162.07:58:09.36#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.162.07:58:09.41#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.162.07:58:09.41#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.162.07:58:09.41#ibcon#enter wrdev, iclass 6, count 2 2006.162.07:58:09.41#ibcon#first serial, iclass 6, count 2 2006.162.07:58:09.41#ibcon#enter sib2, iclass 6, count 2 2006.162.07:58:09.41#ibcon#flushed, iclass 6, count 2 2006.162.07:58:09.41#ibcon#about to write, iclass 6, count 2 2006.162.07:58:09.41#ibcon#wrote, iclass 6, count 2 2006.162.07:58:09.41#ibcon#about to read 3, iclass 6, count 2 2006.162.07:58:09.44#ibcon#read 3, iclass 6, count 2 2006.162.07:58:09.44#ibcon#about to read 4, iclass 6, count 2 2006.162.07:58:09.44#ibcon#read 4, iclass 6, count 2 2006.162.07:58:09.44#ibcon#about to read 5, iclass 6, count 2 2006.162.07:58:09.44#ibcon#read 5, iclass 6, count 2 2006.162.07:58:09.44#ibcon#about to read 6, iclass 6, count 2 2006.162.07:58:09.44#ibcon#read 6, iclass 6, count 2 2006.162.07:58:09.44#ibcon#end of sib2, iclass 6, count 2 2006.162.07:58:09.44#ibcon#*mode == 0, iclass 6, count 2 2006.162.07:58:09.44#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.162.07:58:09.44#ibcon#[25=AT02-07\r\n] 2006.162.07:58:09.44#ibcon#*before write, iclass 6, count 2 2006.162.07:58:09.44#ibcon#enter sib2, iclass 6, count 2 2006.162.07:58:09.44#ibcon#flushed, iclass 6, count 2 2006.162.07:58:09.44#ibcon#about to write, iclass 6, count 2 2006.162.07:58:09.44#ibcon#wrote, iclass 6, count 2 2006.162.07:58:09.44#ibcon#about to read 3, iclass 6, count 2 2006.162.07:58:09.47#ibcon#read 3, iclass 6, count 2 2006.162.07:58:09.47#ibcon#about to read 4, iclass 6, count 2 2006.162.07:58:09.47#ibcon#read 4, iclass 6, count 2 2006.162.07:58:09.47#ibcon#about to read 5, iclass 6, count 2 2006.162.07:58:09.47#ibcon#read 5, iclass 6, count 2 2006.162.07:58:09.47#ibcon#about to read 6, iclass 6, count 2 2006.162.07:58:09.47#ibcon#read 6, iclass 6, count 2 2006.162.07:58:09.47#ibcon#end of sib2, iclass 6, count 2 2006.162.07:58:09.47#ibcon#*after write, iclass 6, count 2 2006.162.07:58:09.47#ibcon#*before return 0, iclass 6, count 2 2006.162.07:58:09.47#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.162.07:58:09.47#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.162.07:58:09.47#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.162.07:58:09.47#ibcon#ireg 7 cls_cnt 0 2006.162.07:58:09.47#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.162.07:58:09.53#abcon#<5=/03 1.7 3.4 17.841001007.0\r\n> 2006.162.07:58:09.54#abcon#{5=INTERFACE CLEAR} 2006.162.07:58:09.59#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.162.07:58:09.59#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.162.07:58:09.59#ibcon#enter wrdev, iclass 6, count 0 2006.162.07:58:09.59#ibcon#first serial, iclass 6, count 0 2006.162.07:58:09.59#ibcon#enter sib2, iclass 6, count 0 2006.162.07:58:09.59#ibcon#flushed, iclass 6, count 0 2006.162.07:58:09.59#ibcon#about to write, iclass 6, count 0 2006.162.07:58:09.59#ibcon#wrote, iclass 6, count 0 2006.162.07:58:09.59#ibcon#about to read 3, iclass 6, count 0 2006.162.07:58:09.63#ibcon#read 3, iclass 6, count 0 2006.162.07:58:09.63#ibcon#about to read 4, iclass 6, count 0 2006.162.07:58:09.63#ibcon#read 4, iclass 6, count 0 2006.162.07:58:09.63#ibcon#about to read 5, iclass 6, count 0 2006.162.07:58:09.63#ibcon#read 5, iclass 6, count 0 2006.162.07:58:09.63#ibcon#about to read 6, iclass 6, count 0 2006.162.07:58:09.63#ibcon#read 6, iclass 6, count 0 2006.162.07:58:09.63#ibcon#end of sib2, iclass 6, count 0 2006.162.07:58:09.63#ibcon#*mode == 0, iclass 6, count 0 2006.162.07:58:09.63#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.162.07:58:09.63#ibcon#[25=USB\r\n] 2006.162.07:58:09.63#ibcon#*before write, iclass 6, count 0 2006.162.07:58:09.63#ibcon#enter sib2, iclass 6, count 0 2006.162.07:58:09.63#ibcon#flushed, iclass 6, count 0 2006.162.07:58:09.63#ibcon#about to write, iclass 6, count 0 2006.162.07:58:09.63#ibcon#wrote, iclass 6, count 0 2006.162.07:58:09.63#ibcon#about to read 3, iclass 6, count 0 2006.162.07:58:09.63#abcon#[5=S1D000X0/0*\r\n] 2006.162.07:58:09.66#ibcon#read 3, iclass 6, count 0 2006.162.07:58:09.66#ibcon#about to read 4, iclass 6, count 0 2006.162.07:58:09.66#ibcon#read 4, iclass 6, count 0 2006.162.07:58:09.66#ibcon#about to read 5, iclass 6, count 0 2006.162.07:58:09.66#ibcon#read 5, iclass 6, count 0 2006.162.07:58:09.66#ibcon#about to read 6, iclass 6, count 0 2006.162.07:58:09.66#ibcon#read 6, iclass 6, count 0 2006.162.07:58:09.66#ibcon#end of sib2, iclass 6, count 0 2006.162.07:58:09.66#ibcon#*after write, iclass 6, count 0 2006.162.07:58:09.66#ibcon#*before return 0, iclass 6, count 0 2006.162.07:58:09.66#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.162.07:58:09.66#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.162.07:58:09.66#ibcon#about to clear, iclass 6 cls_cnt 0 2006.162.07:58:09.66#ibcon#cleared, iclass 6 cls_cnt 0 2006.162.07:58:09.66$vc4f8/valo=3,672.99 2006.162.07:58:09.66#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.162.07:58:09.66#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.162.07:58:09.66#ibcon#ireg 17 cls_cnt 0 2006.162.07:58:09.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.07:58:09.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.07:58:09.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.07:58:09.66#ibcon#enter wrdev, iclass 14, count 0 2006.162.07:58:09.66#ibcon#first serial, iclass 14, count 0 2006.162.07:58:09.66#ibcon#enter sib2, iclass 14, count 0 2006.162.07:58:09.66#ibcon#flushed, iclass 14, count 0 2006.162.07:58:09.66#ibcon#about to write, iclass 14, count 0 2006.162.07:58:09.66#ibcon#wrote, iclass 14, count 0 2006.162.07:58:09.66#ibcon#about to read 3, iclass 14, count 0 2006.162.07:58:09.68#ibcon#read 3, iclass 14, count 0 2006.162.07:58:09.68#ibcon#about to read 4, iclass 14, count 0 2006.162.07:58:09.68#ibcon#read 4, iclass 14, count 0 2006.162.07:58:09.68#ibcon#about to read 5, iclass 14, count 0 2006.162.07:58:09.68#ibcon#read 5, iclass 14, count 0 2006.162.07:58:09.68#ibcon#about to read 6, iclass 14, count 0 2006.162.07:58:09.68#ibcon#read 6, iclass 14, count 0 2006.162.07:58:09.68#ibcon#end of sib2, iclass 14, count 0 2006.162.07:58:09.68#ibcon#*mode == 0, iclass 14, count 0 2006.162.07:58:09.68#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.07:58:09.68#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.07:58:09.68#ibcon#*before write, iclass 14, count 0 2006.162.07:58:09.68#ibcon#enter sib2, iclass 14, count 0 2006.162.07:58:09.68#ibcon#flushed, iclass 14, count 0 2006.162.07:58:09.68#ibcon#about to write, iclass 14, count 0 2006.162.07:58:09.68#ibcon#wrote, iclass 14, count 0 2006.162.07:58:09.68#ibcon#about to read 3, iclass 14, count 0 2006.162.07:58:09.72#ibcon#read 3, iclass 14, count 0 2006.162.07:58:09.72#ibcon#about to read 4, iclass 14, count 0 2006.162.07:58:09.72#ibcon#read 4, iclass 14, count 0 2006.162.07:58:09.72#ibcon#about to read 5, iclass 14, count 0 2006.162.07:58:09.72#ibcon#read 5, iclass 14, count 0 2006.162.07:58:09.72#ibcon#about to read 6, iclass 14, count 0 2006.162.07:58:09.72#ibcon#read 6, iclass 14, count 0 2006.162.07:58:09.73#ibcon#end of sib2, iclass 14, count 0 2006.162.07:58:09.73#ibcon#*after write, iclass 14, count 0 2006.162.07:58:09.73#ibcon#*before return 0, iclass 14, count 0 2006.162.07:58:09.73#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.07:58:09.73#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.162.07:58:09.73#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.07:58:09.73#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.07:58:09.73$vc4f8/va=3,6 2006.162.07:58:09.73#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.162.07:58:09.73#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.162.07:58:09.73#ibcon#ireg 11 cls_cnt 2 2006.162.07:58:09.73#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.162.07:58:09.77#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.162.07:58:09.77#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.162.07:58:09.77#ibcon#enter wrdev, iclass 16, count 2 2006.162.07:58:09.77#ibcon#first serial, iclass 16, count 2 2006.162.07:58:09.77#ibcon#enter sib2, iclass 16, count 2 2006.162.07:58:09.77#ibcon#flushed, iclass 16, count 2 2006.162.07:58:09.77#ibcon#about to write, iclass 16, count 2 2006.162.07:58:09.77#ibcon#wrote, iclass 16, count 2 2006.162.07:58:09.77#ibcon#about to read 3, iclass 16, count 2 2006.162.07:58:09.79#ibcon#read 3, iclass 16, count 2 2006.162.07:58:09.79#ibcon#about to read 4, iclass 16, count 2 2006.162.07:58:09.79#ibcon#read 4, iclass 16, count 2 2006.162.07:58:09.79#ibcon#about to read 5, iclass 16, count 2 2006.162.07:58:09.79#ibcon#read 5, iclass 16, count 2 2006.162.07:58:09.79#ibcon#about to read 6, iclass 16, count 2 2006.162.07:58:09.79#ibcon#read 6, iclass 16, count 2 2006.162.07:58:09.79#ibcon#end of sib2, iclass 16, count 2 2006.162.07:58:09.79#ibcon#*mode == 0, iclass 16, count 2 2006.162.07:58:09.79#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.162.07:58:09.79#ibcon#[25=AT03-06\r\n] 2006.162.07:58:09.79#ibcon#*before write, iclass 16, count 2 2006.162.07:58:09.79#ibcon#enter sib2, iclass 16, count 2 2006.162.07:58:09.79#ibcon#flushed, iclass 16, count 2 2006.162.07:58:09.79#ibcon#about to write, iclass 16, count 2 2006.162.07:58:09.79#ibcon#wrote, iclass 16, count 2 2006.162.07:58:09.79#ibcon#about to read 3, iclass 16, count 2 2006.162.07:58:09.82#ibcon#read 3, iclass 16, count 2 2006.162.07:58:09.82#ibcon#about to read 4, iclass 16, count 2 2006.162.07:58:09.82#ibcon#read 4, iclass 16, count 2 2006.162.07:58:09.82#ibcon#about to read 5, iclass 16, count 2 2006.162.07:58:09.82#ibcon#read 5, iclass 16, count 2 2006.162.07:58:09.82#ibcon#about to read 6, iclass 16, count 2 2006.162.07:58:09.82#ibcon#read 6, iclass 16, count 2 2006.162.07:58:09.82#ibcon#end of sib2, iclass 16, count 2 2006.162.07:58:09.82#ibcon#*after write, iclass 16, count 2 2006.162.07:58:09.82#ibcon#*before return 0, iclass 16, count 2 2006.162.07:58:09.82#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.162.07:58:09.82#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.162.07:58:09.82#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.162.07:58:09.82#ibcon#ireg 7 cls_cnt 0 2006.162.07:58:09.82#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.162.07:58:09.94#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.162.07:58:09.94#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.162.07:58:09.94#ibcon#enter wrdev, iclass 16, count 0 2006.162.07:58:09.94#ibcon#first serial, iclass 16, count 0 2006.162.07:58:09.94#ibcon#enter sib2, iclass 16, count 0 2006.162.07:58:09.94#ibcon#flushed, iclass 16, count 0 2006.162.07:58:09.94#ibcon#about to write, iclass 16, count 0 2006.162.07:58:09.94#ibcon#wrote, iclass 16, count 0 2006.162.07:58:09.94#ibcon#about to read 3, iclass 16, count 0 2006.162.07:58:09.96#ibcon#read 3, iclass 16, count 0 2006.162.07:58:09.96#ibcon#about to read 4, iclass 16, count 0 2006.162.07:58:09.96#ibcon#read 4, iclass 16, count 0 2006.162.07:58:09.96#ibcon#about to read 5, iclass 16, count 0 2006.162.07:58:09.96#ibcon#read 5, iclass 16, count 0 2006.162.07:58:09.96#ibcon#about to read 6, iclass 16, count 0 2006.162.07:58:09.96#ibcon#read 6, iclass 16, count 0 2006.162.07:58:09.96#ibcon#end of sib2, iclass 16, count 0 2006.162.07:58:09.96#ibcon#*mode == 0, iclass 16, count 0 2006.162.07:58:09.96#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.162.07:58:09.96#ibcon#[25=USB\r\n] 2006.162.07:58:09.96#ibcon#*before write, iclass 16, count 0 2006.162.07:58:09.96#ibcon#enter sib2, iclass 16, count 0 2006.162.07:58:09.96#ibcon#flushed, iclass 16, count 0 2006.162.07:58:09.96#ibcon#about to write, iclass 16, count 0 2006.162.07:58:09.96#ibcon#wrote, iclass 16, count 0 2006.162.07:58:09.96#ibcon#about to read 3, iclass 16, count 0 2006.162.07:58:09.99#ibcon#read 3, iclass 16, count 0 2006.162.07:58:09.99#ibcon#about to read 4, iclass 16, count 0 2006.162.07:58:09.99#ibcon#read 4, iclass 16, count 0 2006.162.07:58:09.99#ibcon#about to read 5, iclass 16, count 0 2006.162.07:58:09.99#ibcon#read 5, iclass 16, count 0 2006.162.07:58:09.99#ibcon#about to read 6, iclass 16, count 0 2006.162.07:58:09.99#ibcon#read 6, iclass 16, count 0 2006.162.07:58:09.99#ibcon#end of sib2, iclass 16, count 0 2006.162.07:58:09.99#ibcon#*after write, iclass 16, count 0 2006.162.07:58:09.99#ibcon#*before return 0, iclass 16, count 0 2006.162.07:58:09.99#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.162.07:58:09.99#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.162.07:58:09.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.162.07:58:09.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.162.07:58:09.99$vc4f8/valo=4,832.99 2006.162.07:58:09.99#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.162.07:58:09.99#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.162.07:58:09.99#ibcon#ireg 17 cls_cnt 0 2006.162.07:58:09.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:58:09.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:58:09.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:58:09.99#ibcon#enter wrdev, iclass 18, count 0 2006.162.07:58:09.99#ibcon#first serial, iclass 18, count 0 2006.162.07:58:09.99#ibcon#enter sib2, iclass 18, count 0 2006.162.07:58:09.99#ibcon#flushed, iclass 18, count 0 2006.162.07:58:09.99#ibcon#about to write, iclass 18, count 0 2006.162.07:58:09.99#ibcon#wrote, iclass 18, count 0 2006.162.07:58:09.99#ibcon#about to read 3, iclass 18, count 0 2006.162.07:58:10.01#ibcon#read 3, iclass 18, count 0 2006.162.07:58:10.01#ibcon#about to read 4, iclass 18, count 0 2006.162.07:58:10.01#ibcon#read 4, iclass 18, count 0 2006.162.07:58:10.01#ibcon#about to read 5, iclass 18, count 0 2006.162.07:58:10.01#ibcon#read 5, iclass 18, count 0 2006.162.07:58:10.01#ibcon#about to read 6, iclass 18, count 0 2006.162.07:58:10.01#ibcon#read 6, iclass 18, count 0 2006.162.07:58:10.01#ibcon#end of sib2, iclass 18, count 0 2006.162.07:58:10.01#ibcon#*mode == 0, iclass 18, count 0 2006.162.07:58:10.01#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.162.07:58:10.01#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.07:58:10.01#ibcon#*before write, iclass 18, count 0 2006.162.07:58:10.01#ibcon#enter sib2, iclass 18, count 0 2006.162.07:58:10.01#ibcon#flushed, iclass 18, count 0 2006.162.07:58:10.01#ibcon#about to write, iclass 18, count 0 2006.162.07:58:10.01#ibcon#wrote, iclass 18, count 0 2006.162.07:58:10.01#ibcon#about to read 3, iclass 18, count 0 2006.162.07:58:10.05#ibcon#read 3, iclass 18, count 0 2006.162.07:58:10.05#ibcon#about to read 4, iclass 18, count 0 2006.162.07:58:10.05#ibcon#read 4, iclass 18, count 0 2006.162.07:58:10.05#ibcon#about to read 5, iclass 18, count 0 2006.162.07:58:10.05#ibcon#read 5, iclass 18, count 0 2006.162.07:58:10.05#ibcon#about to read 6, iclass 18, count 0 2006.162.07:58:10.05#ibcon#read 6, iclass 18, count 0 2006.162.07:58:10.05#ibcon#end of sib2, iclass 18, count 0 2006.162.07:58:10.05#ibcon#*after write, iclass 18, count 0 2006.162.07:58:10.05#ibcon#*before return 0, iclass 18, count 0 2006.162.07:58:10.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:58:10.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:58:10.05#ibcon#about to clear, iclass 18 cls_cnt 0 2006.162.07:58:10.05#ibcon#cleared, iclass 18 cls_cnt 0 2006.162.07:58:10.05$vc4f8/va=4,7 2006.162.07:58:10.05#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.162.07:58:10.05#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.162.07:58:10.05#ibcon#ireg 11 cls_cnt 2 2006.162.07:58:10.05#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:58:10.11#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:58:10.11#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:58:10.11#ibcon#enter wrdev, iclass 20, count 2 2006.162.07:58:10.11#ibcon#first serial, iclass 20, count 2 2006.162.07:58:10.11#ibcon#enter sib2, iclass 20, count 2 2006.162.07:58:10.11#ibcon#flushed, iclass 20, count 2 2006.162.07:58:10.11#ibcon#about to write, iclass 20, count 2 2006.162.07:58:10.11#ibcon#wrote, iclass 20, count 2 2006.162.07:58:10.11#ibcon#about to read 3, iclass 20, count 2 2006.162.07:58:10.13#ibcon#read 3, iclass 20, count 2 2006.162.07:58:10.13#ibcon#about to read 4, iclass 20, count 2 2006.162.07:58:10.13#ibcon#read 4, iclass 20, count 2 2006.162.07:58:10.13#ibcon#about to read 5, iclass 20, count 2 2006.162.07:58:10.13#ibcon#read 5, iclass 20, count 2 2006.162.07:58:10.13#ibcon#about to read 6, iclass 20, count 2 2006.162.07:58:10.13#ibcon#read 6, iclass 20, count 2 2006.162.07:58:10.13#ibcon#end of sib2, iclass 20, count 2 2006.162.07:58:10.13#ibcon#*mode == 0, iclass 20, count 2 2006.162.07:58:10.13#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.162.07:58:10.13#ibcon#[25=AT04-07\r\n] 2006.162.07:58:10.13#ibcon#*before write, iclass 20, count 2 2006.162.07:58:10.13#ibcon#enter sib2, iclass 20, count 2 2006.162.07:58:10.13#ibcon#flushed, iclass 20, count 2 2006.162.07:58:10.13#ibcon#about to write, iclass 20, count 2 2006.162.07:58:10.13#ibcon#wrote, iclass 20, count 2 2006.162.07:58:10.13#ibcon#about to read 3, iclass 20, count 2 2006.162.07:58:10.16#ibcon#read 3, iclass 20, count 2 2006.162.07:58:10.16#ibcon#about to read 4, iclass 20, count 2 2006.162.07:58:10.16#ibcon#read 4, iclass 20, count 2 2006.162.07:58:10.16#ibcon#about to read 5, iclass 20, count 2 2006.162.07:58:10.16#ibcon#read 5, iclass 20, count 2 2006.162.07:58:10.16#ibcon#about to read 6, iclass 20, count 2 2006.162.07:58:10.16#ibcon#read 6, iclass 20, count 2 2006.162.07:58:10.16#ibcon#end of sib2, iclass 20, count 2 2006.162.07:58:10.16#ibcon#*after write, iclass 20, count 2 2006.162.07:58:10.16#ibcon#*before return 0, iclass 20, count 2 2006.162.07:58:10.16#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:58:10.16#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:58:10.16#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.162.07:58:10.16#ibcon#ireg 7 cls_cnt 0 2006.162.07:58:10.16#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:58:10.28#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:58:10.28#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:58:10.28#ibcon#enter wrdev, iclass 20, count 0 2006.162.07:58:10.28#ibcon#first serial, iclass 20, count 0 2006.162.07:58:10.28#ibcon#enter sib2, iclass 20, count 0 2006.162.07:58:10.28#ibcon#flushed, iclass 20, count 0 2006.162.07:58:10.28#ibcon#about to write, iclass 20, count 0 2006.162.07:58:10.28#ibcon#wrote, iclass 20, count 0 2006.162.07:58:10.28#ibcon#about to read 3, iclass 20, count 0 2006.162.07:58:10.30#ibcon#read 3, iclass 20, count 0 2006.162.07:58:10.30#ibcon#about to read 4, iclass 20, count 0 2006.162.07:58:10.30#ibcon#read 4, iclass 20, count 0 2006.162.07:58:10.30#ibcon#about to read 5, iclass 20, count 0 2006.162.07:58:10.30#ibcon#read 5, iclass 20, count 0 2006.162.07:58:10.30#ibcon#about to read 6, iclass 20, count 0 2006.162.07:58:10.30#ibcon#read 6, iclass 20, count 0 2006.162.07:58:10.30#ibcon#end of sib2, iclass 20, count 0 2006.162.07:58:10.30#ibcon#*mode == 0, iclass 20, count 0 2006.162.07:58:10.30#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.07:58:10.30#ibcon#[25=USB\r\n] 2006.162.07:58:10.30#ibcon#*before write, iclass 20, count 0 2006.162.07:58:10.30#ibcon#enter sib2, iclass 20, count 0 2006.162.07:58:10.30#ibcon#flushed, iclass 20, count 0 2006.162.07:58:10.30#ibcon#about to write, iclass 20, count 0 2006.162.07:58:10.30#ibcon#wrote, iclass 20, count 0 2006.162.07:58:10.30#ibcon#about to read 3, iclass 20, count 0 2006.162.07:58:10.33#ibcon#read 3, iclass 20, count 0 2006.162.07:58:10.33#ibcon#about to read 4, iclass 20, count 0 2006.162.07:58:10.33#ibcon#read 4, iclass 20, count 0 2006.162.07:58:10.33#ibcon#about to read 5, iclass 20, count 0 2006.162.07:58:10.33#ibcon#read 5, iclass 20, count 0 2006.162.07:58:10.33#ibcon#about to read 6, iclass 20, count 0 2006.162.07:58:10.33#ibcon#read 6, iclass 20, count 0 2006.162.07:58:10.33#ibcon#end of sib2, iclass 20, count 0 2006.162.07:58:10.33#ibcon#*after write, iclass 20, count 0 2006.162.07:58:10.33#ibcon#*before return 0, iclass 20, count 0 2006.162.07:58:10.33#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:58:10.33#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:58:10.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.07:58:10.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.07:58:10.33$vc4f8/valo=5,652.99 2006.162.07:58:10.33#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.162.07:58:10.33#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.162.07:58:10.33#ibcon#ireg 17 cls_cnt 0 2006.162.07:58:10.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:58:10.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:58:10.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:58:10.33#ibcon#enter wrdev, iclass 22, count 0 2006.162.07:58:10.33#ibcon#first serial, iclass 22, count 0 2006.162.07:58:10.33#ibcon#enter sib2, iclass 22, count 0 2006.162.07:58:10.33#ibcon#flushed, iclass 22, count 0 2006.162.07:58:10.33#ibcon#about to write, iclass 22, count 0 2006.162.07:58:10.33#ibcon#wrote, iclass 22, count 0 2006.162.07:58:10.33#ibcon#about to read 3, iclass 22, count 0 2006.162.07:58:10.35#ibcon#read 3, iclass 22, count 0 2006.162.07:58:10.35#ibcon#about to read 4, iclass 22, count 0 2006.162.07:58:10.35#ibcon#read 4, iclass 22, count 0 2006.162.07:58:10.35#ibcon#about to read 5, iclass 22, count 0 2006.162.07:58:10.35#ibcon#read 5, iclass 22, count 0 2006.162.07:58:10.35#ibcon#about to read 6, iclass 22, count 0 2006.162.07:58:10.35#ibcon#read 6, iclass 22, count 0 2006.162.07:58:10.35#ibcon#end of sib2, iclass 22, count 0 2006.162.07:58:10.35#ibcon#*mode == 0, iclass 22, count 0 2006.162.07:58:10.35#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.07:58:10.35#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.07:58:10.35#ibcon#*before write, iclass 22, count 0 2006.162.07:58:10.35#ibcon#enter sib2, iclass 22, count 0 2006.162.07:58:10.35#ibcon#flushed, iclass 22, count 0 2006.162.07:58:10.35#ibcon#about to write, iclass 22, count 0 2006.162.07:58:10.35#ibcon#wrote, iclass 22, count 0 2006.162.07:58:10.35#ibcon#about to read 3, iclass 22, count 0 2006.162.07:58:10.39#ibcon#read 3, iclass 22, count 0 2006.162.07:58:10.39#ibcon#about to read 4, iclass 22, count 0 2006.162.07:58:10.39#ibcon#read 4, iclass 22, count 0 2006.162.07:58:10.39#ibcon#about to read 5, iclass 22, count 0 2006.162.07:58:10.39#ibcon#read 5, iclass 22, count 0 2006.162.07:58:10.39#ibcon#about to read 6, iclass 22, count 0 2006.162.07:58:10.39#ibcon#read 6, iclass 22, count 0 2006.162.07:58:10.39#ibcon#end of sib2, iclass 22, count 0 2006.162.07:58:10.39#ibcon#*after write, iclass 22, count 0 2006.162.07:58:10.39#ibcon#*before return 0, iclass 22, count 0 2006.162.07:58:10.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:58:10.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:58:10.39#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.07:58:10.39#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.07:58:10.39$vc4f8/va=5,7 2006.162.07:58:10.39#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.162.07:58:10.39#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.162.07:58:10.39#ibcon#ireg 11 cls_cnt 2 2006.162.07:58:10.39#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:58:10.45#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:58:10.45#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:58:10.45#ibcon#enter wrdev, iclass 24, count 2 2006.162.07:58:10.45#ibcon#first serial, iclass 24, count 2 2006.162.07:58:10.45#ibcon#enter sib2, iclass 24, count 2 2006.162.07:58:10.45#ibcon#flushed, iclass 24, count 2 2006.162.07:58:10.45#ibcon#about to write, iclass 24, count 2 2006.162.07:58:10.45#ibcon#wrote, iclass 24, count 2 2006.162.07:58:10.45#ibcon#about to read 3, iclass 24, count 2 2006.162.07:58:10.48#ibcon#read 3, iclass 24, count 2 2006.162.07:58:10.48#ibcon#about to read 4, iclass 24, count 2 2006.162.07:58:10.48#ibcon#read 4, iclass 24, count 2 2006.162.07:58:10.48#ibcon#about to read 5, iclass 24, count 2 2006.162.07:58:10.48#ibcon#read 5, iclass 24, count 2 2006.162.07:58:10.48#ibcon#about to read 6, iclass 24, count 2 2006.162.07:58:10.48#ibcon#read 6, iclass 24, count 2 2006.162.07:58:10.48#ibcon#end of sib2, iclass 24, count 2 2006.162.07:58:10.48#ibcon#*mode == 0, iclass 24, count 2 2006.162.07:58:10.48#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.162.07:58:10.48#ibcon#[25=AT05-07\r\n] 2006.162.07:58:10.48#ibcon#*before write, iclass 24, count 2 2006.162.07:58:10.48#ibcon#enter sib2, iclass 24, count 2 2006.162.07:58:10.48#ibcon#flushed, iclass 24, count 2 2006.162.07:58:10.48#ibcon#about to write, iclass 24, count 2 2006.162.07:58:10.48#ibcon#wrote, iclass 24, count 2 2006.162.07:58:10.48#ibcon#about to read 3, iclass 24, count 2 2006.162.07:58:10.50#ibcon#read 3, iclass 24, count 2 2006.162.07:58:10.50#ibcon#about to read 4, iclass 24, count 2 2006.162.07:58:10.50#ibcon#read 4, iclass 24, count 2 2006.162.07:58:10.50#ibcon#about to read 5, iclass 24, count 2 2006.162.07:58:10.50#ibcon#read 5, iclass 24, count 2 2006.162.07:58:10.50#ibcon#about to read 6, iclass 24, count 2 2006.162.07:58:10.50#ibcon#read 6, iclass 24, count 2 2006.162.07:58:10.50#ibcon#end of sib2, iclass 24, count 2 2006.162.07:58:10.50#ibcon#*after write, iclass 24, count 2 2006.162.07:58:10.50#ibcon#*before return 0, iclass 24, count 2 2006.162.07:58:10.50#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:58:10.50#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:58:10.50#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.162.07:58:10.50#ibcon#ireg 7 cls_cnt 0 2006.162.07:58:10.50#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:58:10.62#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:58:10.62#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:58:10.62#ibcon#enter wrdev, iclass 24, count 0 2006.162.07:58:10.62#ibcon#first serial, iclass 24, count 0 2006.162.07:58:10.62#ibcon#enter sib2, iclass 24, count 0 2006.162.07:58:10.62#ibcon#flushed, iclass 24, count 0 2006.162.07:58:10.62#ibcon#about to write, iclass 24, count 0 2006.162.07:58:10.62#ibcon#wrote, iclass 24, count 0 2006.162.07:58:10.62#ibcon#about to read 3, iclass 24, count 0 2006.162.07:58:10.64#ibcon#read 3, iclass 24, count 0 2006.162.07:58:10.64#ibcon#about to read 4, iclass 24, count 0 2006.162.07:58:10.64#ibcon#read 4, iclass 24, count 0 2006.162.07:58:10.64#ibcon#about to read 5, iclass 24, count 0 2006.162.07:58:10.64#ibcon#read 5, iclass 24, count 0 2006.162.07:58:10.64#ibcon#about to read 6, iclass 24, count 0 2006.162.07:58:10.64#ibcon#read 6, iclass 24, count 0 2006.162.07:58:10.64#ibcon#end of sib2, iclass 24, count 0 2006.162.07:58:10.64#ibcon#*mode == 0, iclass 24, count 0 2006.162.07:58:10.64#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.07:58:10.64#ibcon#[25=USB\r\n] 2006.162.07:58:10.64#ibcon#*before write, iclass 24, count 0 2006.162.07:58:10.64#ibcon#enter sib2, iclass 24, count 0 2006.162.07:58:10.64#ibcon#flushed, iclass 24, count 0 2006.162.07:58:10.64#ibcon#about to write, iclass 24, count 0 2006.162.07:58:10.64#ibcon#wrote, iclass 24, count 0 2006.162.07:58:10.64#ibcon#about to read 3, iclass 24, count 0 2006.162.07:58:10.67#ibcon#read 3, iclass 24, count 0 2006.162.07:58:10.67#ibcon#about to read 4, iclass 24, count 0 2006.162.07:58:10.67#ibcon#read 4, iclass 24, count 0 2006.162.07:58:10.67#ibcon#about to read 5, iclass 24, count 0 2006.162.07:58:10.67#ibcon#read 5, iclass 24, count 0 2006.162.07:58:10.67#ibcon#about to read 6, iclass 24, count 0 2006.162.07:58:10.67#ibcon#read 6, iclass 24, count 0 2006.162.07:58:10.67#ibcon#end of sib2, iclass 24, count 0 2006.162.07:58:10.67#ibcon#*after write, iclass 24, count 0 2006.162.07:58:10.67#ibcon#*before return 0, iclass 24, count 0 2006.162.07:58:10.67#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:58:10.67#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:58:10.67#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.07:58:10.67#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.07:58:10.67$vc4f8/valo=6,772.99 2006.162.07:58:10.67#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.162.07:58:10.67#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.162.07:58:10.67#ibcon#ireg 17 cls_cnt 0 2006.162.07:58:10.67#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:58:10.67#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:58:10.67#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:58:10.67#ibcon#enter wrdev, iclass 26, count 0 2006.162.07:58:10.67#ibcon#first serial, iclass 26, count 0 2006.162.07:58:10.67#ibcon#enter sib2, iclass 26, count 0 2006.162.07:58:10.67#ibcon#flushed, iclass 26, count 0 2006.162.07:58:10.67#ibcon#about to write, iclass 26, count 0 2006.162.07:58:10.67#ibcon#wrote, iclass 26, count 0 2006.162.07:58:10.67#ibcon#about to read 3, iclass 26, count 0 2006.162.07:58:10.70#ibcon#read 3, iclass 26, count 0 2006.162.07:58:10.70#ibcon#about to read 4, iclass 26, count 0 2006.162.07:58:10.70#ibcon#read 4, iclass 26, count 0 2006.162.07:58:10.70#ibcon#about to read 5, iclass 26, count 0 2006.162.07:58:10.70#ibcon#read 5, iclass 26, count 0 2006.162.07:58:10.70#ibcon#about to read 6, iclass 26, count 0 2006.162.07:58:10.70#ibcon#read 6, iclass 26, count 0 2006.162.07:58:10.70#ibcon#end of sib2, iclass 26, count 0 2006.162.07:58:10.70#ibcon#*mode == 0, iclass 26, count 0 2006.162.07:58:10.70#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.162.07:58:10.70#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.07:58:10.70#ibcon#*before write, iclass 26, count 0 2006.162.07:58:10.70#ibcon#enter sib2, iclass 26, count 0 2006.162.07:58:10.70#ibcon#flushed, iclass 26, count 0 2006.162.07:58:10.70#ibcon#about to write, iclass 26, count 0 2006.162.07:58:10.70#ibcon#wrote, iclass 26, count 0 2006.162.07:58:10.70#ibcon#about to read 3, iclass 26, count 0 2006.162.07:58:10.74#ibcon#read 3, iclass 26, count 0 2006.162.07:58:10.74#ibcon#about to read 4, iclass 26, count 0 2006.162.07:58:10.74#ibcon#read 4, iclass 26, count 0 2006.162.07:58:10.74#ibcon#about to read 5, iclass 26, count 0 2006.162.07:58:10.74#ibcon#read 5, iclass 26, count 0 2006.162.07:58:10.74#ibcon#about to read 6, iclass 26, count 0 2006.162.07:58:10.74#ibcon#read 6, iclass 26, count 0 2006.162.07:58:10.74#ibcon#end of sib2, iclass 26, count 0 2006.162.07:58:10.74#ibcon#*after write, iclass 26, count 0 2006.162.07:58:10.74#ibcon#*before return 0, iclass 26, count 0 2006.162.07:58:10.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:58:10.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:58:10.74#ibcon#about to clear, iclass 26 cls_cnt 0 2006.162.07:58:10.74#ibcon#cleared, iclass 26 cls_cnt 0 2006.162.07:58:10.74$vc4f8/va=6,6 2006.162.07:58:10.74#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.162.07:58:10.74#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.162.07:58:10.74#ibcon#ireg 11 cls_cnt 2 2006.162.07:58:10.74#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.162.07:58:10.79#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.162.07:58:10.79#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.162.07:58:10.79#ibcon#enter wrdev, iclass 28, count 2 2006.162.07:58:10.79#ibcon#first serial, iclass 28, count 2 2006.162.07:58:10.79#ibcon#enter sib2, iclass 28, count 2 2006.162.07:58:10.79#ibcon#flushed, iclass 28, count 2 2006.162.07:58:10.79#ibcon#about to write, iclass 28, count 2 2006.162.07:58:10.79#ibcon#wrote, iclass 28, count 2 2006.162.07:58:10.79#ibcon#about to read 3, iclass 28, count 2 2006.162.07:58:10.81#ibcon#read 3, iclass 28, count 2 2006.162.07:58:10.81#ibcon#about to read 4, iclass 28, count 2 2006.162.07:58:10.81#ibcon#read 4, iclass 28, count 2 2006.162.07:58:10.81#ibcon#about to read 5, iclass 28, count 2 2006.162.07:58:10.81#ibcon#read 5, iclass 28, count 2 2006.162.07:58:10.81#ibcon#about to read 6, iclass 28, count 2 2006.162.07:58:10.81#ibcon#read 6, iclass 28, count 2 2006.162.07:58:10.81#ibcon#end of sib2, iclass 28, count 2 2006.162.07:58:10.81#ibcon#*mode == 0, iclass 28, count 2 2006.162.07:58:10.81#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.162.07:58:10.81#ibcon#[25=AT06-06\r\n] 2006.162.07:58:10.81#ibcon#*before write, iclass 28, count 2 2006.162.07:58:10.81#ibcon#enter sib2, iclass 28, count 2 2006.162.07:58:10.81#ibcon#flushed, iclass 28, count 2 2006.162.07:58:10.81#ibcon#about to write, iclass 28, count 2 2006.162.07:58:10.81#ibcon#wrote, iclass 28, count 2 2006.162.07:58:10.81#ibcon#about to read 3, iclass 28, count 2 2006.162.07:58:10.84#ibcon#read 3, iclass 28, count 2 2006.162.07:58:10.84#ibcon#about to read 4, iclass 28, count 2 2006.162.07:58:10.84#ibcon#read 4, iclass 28, count 2 2006.162.07:58:10.84#ibcon#about to read 5, iclass 28, count 2 2006.162.07:58:10.84#ibcon#read 5, iclass 28, count 2 2006.162.07:58:10.84#ibcon#about to read 6, iclass 28, count 2 2006.162.07:58:10.84#ibcon#read 6, iclass 28, count 2 2006.162.07:58:10.84#ibcon#end of sib2, iclass 28, count 2 2006.162.07:58:10.84#ibcon#*after write, iclass 28, count 2 2006.162.07:58:10.84#ibcon#*before return 0, iclass 28, count 2 2006.162.07:58:10.84#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.162.07:58:10.84#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.162.07:58:10.84#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.162.07:58:10.84#ibcon#ireg 7 cls_cnt 0 2006.162.07:58:10.84#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.162.07:58:10.96#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.162.07:58:10.96#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.162.07:58:10.96#ibcon#enter wrdev, iclass 28, count 0 2006.162.07:58:10.96#ibcon#first serial, iclass 28, count 0 2006.162.07:58:10.96#ibcon#enter sib2, iclass 28, count 0 2006.162.07:58:10.96#ibcon#flushed, iclass 28, count 0 2006.162.07:58:10.96#ibcon#about to write, iclass 28, count 0 2006.162.07:58:10.96#ibcon#wrote, iclass 28, count 0 2006.162.07:58:10.96#ibcon#about to read 3, iclass 28, count 0 2006.162.07:58:10.98#ibcon#read 3, iclass 28, count 0 2006.162.07:58:10.98#ibcon#about to read 4, iclass 28, count 0 2006.162.07:58:10.98#ibcon#read 4, iclass 28, count 0 2006.162.07:58:10.98#ibcon#about to read 5, iclass 28, count 0 2006.162.07:58:10.98#ibcon#read 5, iclass 28, count 0 2006.162.07:58:10.98#ibcon#about to read 6, iclass 28, count 0 2006.162.07:58:10.98#ibcon#read 6, iclass 28, count 0 2006.162.07:58:10.98#ibcon#end of sib2, iclass 28, count 0 2006.162.07:58:10.98#ibcon#*mode == 0, iclass 28, count 0 2006.162.07:58:10.98#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.162.07:58:10.98#ibcon#[25=USB\r\n] 2006.162.07:58:10.98#ibcon#*before write, iclass 28, count 0 2006.162.07:58:10.98#ibcon#enter sib2, iclass 28, count 0 2006.162.07:58:10.98#ibcon#flushed, iclass 28, count 0 2006.162.07:58:10.98#ibcon#about to write, iclass 28, count 0 2006.162.07:58:10.98#ibcon#wrote, iclass 28, count 0 2006.162.07:58:10.98#ibcon#about to read 3, iclass 28, count 0 2006.162.07:58:11.01#ibcon#read 3, iclass 28, count 0 2006.162.07:58:11.01#ibcon#about to read 4, iclass 28, count 0 2006.162.07:58:11.01#ibcon#read 4, iclass 28, count 0 2006.162.07:58:11.01#ibcon#about to read 5, iclass 28, count 0 2006.162.07:58:11.01#ibcon#read 5, iclass 28, count 0 2006.162.07:58:11.01#ibcon#about to read 6, iclass 28, count 0 2006.162.07:58:11.01#ibcon#read 6, iclass 28, count 0 2006.162.07:58:11.01#ibcon#end of sib2, iclass 28, count 0 2006.162.07:58:11.01#ibcon#*after write, iclass 28, count 0 2006.162.07:58:11.01#ibcon#*before return 0, iclass 28, count 0 2006.162.07:58:11.01#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.162.07:58:11.01#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.162.07:58:11.01#ibcon#about to clear, iclass 28 cls_cnt 0 2006.162.07:58:11.01#ibcon#cleared, iclass 28 cls_cnt 0 2006.162.07:58:11.01$vc4f8/valo=7,832.99 2006.162.07:58:11.01#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.162.07:58:11.01#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.162.07:58:11.01#ibcon#ireg 17 cls_cnt 0 2006.162.07:58:11.01#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.162.07:58:11.01#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.162.07:58:11.01#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.162.07:58:11.01#ibcon#enter wrdev, iclass 30, count 0 2006.162.07:58:11.01#ibcon#first serial, iclass 30, count 0 2006.162.07:58:11.01#ibcon#enter sib2, iclass 30, count 0 2006.162.07:58:11.01#ibcon#flushed, iclass 30, count 0 2006.162.07:58:11.01#ibcon#about to write, iclass 30, count 0 2006.162.07:58:11.01#ibcon#wrote, iclass 30, count 0 2006.162.07:58:11.01#ibcon#about to read 3, iclass 30, count 0 2006.162.07:58:11.03#ibcon#read 3, iclass 30, count 0 2006.162.07:58:11.03#ibcon#about to read 4, iclass 30, count 0 2006.162.07:58:11.03#ibcon#read 4, iclass 30, count 0 2006.162.07:58:11.03#ibcon#about to read 5, iclass 30, count 0 2006.162.07:58:11.03#ibcon#read 5, iclass 30, count 0 2006.162.07:58:11.03#ibcon#about to read 6, iclass 30, count 0 2006.162.07:58:11.03#ibcon#read 6, iclass 30, count 0 2006.162.07:58:11.03#ibcon#end of sib2, iclass 30, count 0 2006.162.07:58:11.03#ibcon#*mode == 0, iclass 30, count 0 2006.162.07:58:11.03#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.162.07:58:11.03#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.07:58:11.03#ibcon#*before write, iclass 30, count 0 2006.162.07:58:11.03#ibcon#enter sib2, iclass 30, count 0 2006.162.07:58:11.03#ibcon#flushed, iclass 30, count 0 2006.162.07:58:11.03#ibcon#about to write, iclass 30, count 0 2006.162.07:58:11.03#ibcon#wrote, iclass 30, count 0 2006.162.07:58:11.03#ibcon#about to read 3, iclass 30, count 0 2006.162.07:58:11.07#ibcon#read 3, iclass 30, count 0 2006.162.07:58:11.07#ibcon#about to read 4, iclass 30, count 0 2006.162.07:58:11.07#ibcon#read 4, iclass 30, count 0 2006.162.07:58:11.07#ibcon#about to read 5, iclass 30, count 0 2006.162.07:58:11.07#ibcon#read 5, iclass 30, count 0 2006.162.07:58:11.07#ibcon#about to read 6, iclass 30, count 0 2006.162.07:58:11.07#ibcon#read 6, iclass 30, count 0 2006.162.07:58:11.07#ibcon#end of sib2, iclass 30, count 0 2006.162.07:58:11.07#ibcon#*after write, iclass 30, count 0 2006.162.07:58:11.07#ibcon#*before return 0, iclass 30, count 0 2006.162.07:58:11.07#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.162.07:58:11.07#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.162.07:58:11.07#ibcon#about to clear, iclass 30 cls_cnt 0 2006.162.07:58:11.07#ibcon#cleared, iclass 30 cls_cnt 0 2006.162.07:58:11.07$vc4f8/va=7,6 2006.162.07:58:11.07#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.162.07:58:11.07#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.162.07:58:11.07#ibcon#ireg 11 cls_cnt 2 2006.162.07:58:11.07#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.162.07:58:11.13#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.162.07:58:11.13#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.162.07:58:11.13#ibcon#enter wrdev, iclass 32, count 2 2006.162.07:58:11.13#ibcon#first serial, iclass 32, count 2 2006.162.07:58:11.13#ibcon#enter sib2, iclass 32, count 2 2006.162.07:58:11.13#ibcon#flushed, iclass 32, count 2 2006.162.07:58:11.13#ibcon#about to write, iclass 32, count 2 2006.162.07:58:11.13#ibcon#wrote, iclass 32, count 2 2006.162.07:58:11.13#ibcon#about to read 3, iclass 32, count 2 2006.162.07:58:11.15#ibcon#read 3, iclass 32, count 2 2006.162.07:58:11.15#ibcon#about to read 4, iclass 32, count 2 2006.162.07:58:11.15#ibcon#read 4, iclass 32, count 2 2006.162.07:58:11.15#ibcon#about to read 5, iclass 32, count 2 2006.162.07:58:11.15#ibcon#read 5, iclass 32, count 2 2006.162.07:58:11.15#ibcon#about to read 6, iclass 32, count 2 2006.162.07:58:11.15#ibcon#read 6, iclass 32, count 2 2006.162.07:58:11.15#ibcon#end of sib2, iclass 32, count 2 2006.162.07:58:11.15#ibcon#*mode == 0, iclass 32, count 2 2006.162.07:58:11.15#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.162.07:58:11.15#ibcon#[25=AT07-06\r\n] 2006.162.07:58:11.15#ibcon#*before write, iclass 32, count 2 2006.162.07:58:11.15#ibcon#enter sib2, iclass 32, count 2 2006.162.07:58:11.15#ibcon#flushed, iclass 32, count 2 2006.162.07:58:11.15#ibcon#about to write, iclass 32, count 2 2006.162.07:58:11.15#ibcon#wrote, iclass 32, count 2 2006.162.07:58:11.15#ibcon#about to read 3, iclass 32, count 2 2006.162.07:58:11.18#ibcon#read 3, iclass 32, count 2 2006.162.07:58:11.18#ibcon#about to read 4, iclass 32, count 2 2006.162.07:58:11.18#ibcon#read 4, iclass 32, count 2 2006.162.07:58:11.18#ibcon#about to read 5, iclass 32, count 2 2006.162.07:58:11.18#ibcon#read 5, iclass 32, count 2 2006.162.07:58:11.18#ibcon#about to read 6, iclass 32, count 2 2006.162.07:58:11.18#ibcon#read 6, iclass 32, count 2 2006.162.07:58:11.18#ibcon#end of sib2, iclass 32, count 2 2006.162.07:58:11.18#ibcon#*after write, iclass 32, count 2 2006.162.07:58:11.18#ibcon#*before return 0, iclass 32, count 2 2006.162.07:58:11.18#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.162.07:58:11.18#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.162.07:58:11.18#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.162.07:58:11.18#ibcon#ireg 7 cls_cnt 0 2006.162.07:58:11.18#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.162.07:58:11.30#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.162.07:58:11.30#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.162.07:58:11.30#ibcon#enter wrdev, iclass 32, count 0 2006.162.07:58:11.30#ibcon#first serial, iclass 32, count 0 2006.162.07:58:11.30#ibcon#enter sib2, iclass 32, count 0 2006.162.07:58:11.30#ibcon#flushed, iclass 32, count 0 2006.162.07:58:11.30#ibcon#about to write, iclass 32, count 0 2006.162.07:58:11.30#ibcon#wrote, iclass 32, count 0 2006.162.07:58:11.30#ibcon#about to read 3, iclass 32, count 0 2006.162.07:58:11.32#ibcon#read 3, iclass 32, count 0 2006.162.07:58:11.32#ibcon#about to read 4, iclass 32, count 0 2006.162.07:58:11.32#ibcon#read 4, iclass 32, count 0 2006.162.07:58:11.32#ibcon#about to read 5, iclass 32, count 0 2006.162.07:58:11.32#ibcon#read 5, iclass 32, count 0 2006.162.07:58:11.32#ibcon#about to read 6, iclass 32, count 0 2006.162.07:58:11.32#ibcon#read 6, iclass 32, count 0 2006.162.07:58:11.32#ibcon#end of sib2, iclass 32, count 0 2006.162.07:58:11.32#ibcon#*mode == 0, iclass 32, count 0 2006.162.07:58:11.32#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.162.07:58:11.32#ibcon#[25=USB\r\n] 2006.162.07:58:11.32#ibcon#*before write, iclass 32, count 0 2006.162.07:58:11.32#ibcon#enter sib2, iclass 32, count 0 2006.162.07:58:11.32#ibcon#flushed, iclass 32, count 0 2006.162.07:58:11.32#ibcon#about to write, iclass 32, count 0 2006.162.07:58:11.32#ibcon#wrote, iclass 32, count 0 2006.162.07:58:11.32#ibcon#about to read 3, iclass 32, count 0 2006.162.07:58:11.35#ibcon#read 3, iclass 32, count 0 2006.162.07:58:11.35#ibcon#about to read 4, iclass 32, count 0 2006.162.07:58:11.35#ibcon#read 4, iclass 32, count 0 2006.162.07:58:11.35#ibcon#about to read 5, iclass 32, count 0 2006.162.07:58:11.35#ibcon#read 5, iclass 32, count 0 2006.162.07:58:11.35#ibcon#about to read 6, iclass 32, count 0 2006.162.07:58:11.35#ibcon#read 6, iclass 32, count 0 2006.162.07:58:11.35#ibcon#end of sib2, iclass 32, count 0 2006.162.07:58:11.35#ibcon#*after write, iclass 32, count 0 2006.162.07:58:11.35#ibcon#*before return 0, iclass 32, count 0 2006.162.07:58:11.35#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.162.07:58:11.35#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.162.07:58:11.35#ibcon#about to clear, iclass 32 cls_cnt 0 2006.162.07:58:11.35#ibcon#cleared, iclass 32 cls_cnt 0 2006.162.07:58:11.35$vc4f8/valo=8,852.99 2006.162.07:58:11.35#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.162.07:58:11.35#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.162.07:58:11.35#ibcon#ireg 17 cls_cnt 0 2006.162.07:58:11.35#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.162.07:58:11.35#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.162.07:58:11.35#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.162.07:58:11.35#ibcon#enter wrdev, iclass 34, count 0 2006.162.07:58:11.35#ibcon#first serial, iclass 34, count 0 2006.162.07:58:11.35#ibcon#enter sib2, iclass 34, count 0 2006.162.07:58:11.35#ibcon#flushed, iclass 34, count 0 2006.162.07:58:11.35#ibcon#about to write, iclass 34, count 0 2006.162.07:58:11.35#ibcon#wrote, iclass 34, count 0 2006.162.07:58:11.35#ibcon#about to read 3, iclass 34, count 0 2006.162.07:58:11.38#ibcon#read 3, iclass 34, count 0 2006.162.07:58:11.38#ibcon#about to read 4, iclass 34, count 0 2006.162.07:58:11.38#ibcon#read 4, iclass 34, count 0 2006.162.07:58:11.38#ibcon#about to read 5, iclass 34, count 0 2006.162.07:58:11.38#ibcon#read 5, iclass 34, count 0 2006.162.07:58:11.38#ibcon#about to read 6, iclass 34, count 0 2006.162.07:58:11.38#ibcon#read 6, iclass 34, count 0 2006.162.07:58:11.38#ibcon#end of sib2, iclass 34, count 0 2006.162.07:58:11.38#ibcon#*mode == 0, iclass 34, count 0 2006.162.07:58:11.38#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.162.07:58:11.38#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.07:58:11.38#ibcon#*before write, iclass 34, count 0 2006.162.07:58:11.38#ibcon#enter sib2, iclass 34, count 0 2006.162.07:58:11.38#ibcon#flushed, iclass 34, count 0 2006.162.07:58:11.38#ibcon#about to write, iclass 34, count 0 2006.162.07:58:11.38#ibcon#wrote, iclass 34, count 0 2006.162.07:58:11.38#ibcon#about to read 3, iclass 34, count 0 2006.162.07:58:11.42#ibcon#read 3, iclass 34, count 0 2006.162.07:58:11.42#ibcon#about to read 4, iclass 34, count 0 2006.162.07:58:11.42#ibcon#read 4, iclass 34, count 0 2006.162.07:58:11.42#ibcon#about to read 5, iclass 34, count 0 2006.162.07:58:11.42#ibcon#read 5, iclass 34, count 0 2006.162.07:58:11.42#ibcon#about to read 6, iclass 34, count 0 2006.162.07:58:11.42#ibcon#read 6, iclass 34, count 0 2006.162.07:58:11.42#ibcon#end of sib2, iclass 34, count 0 2006.162.07:58:11.42#ibcon#*after write, iclass 34, count 0 2006.162.07:58:11.42#ibcon#*before return 0, iclass 34, count 0 2006.162.07:58:11.42#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.162.07:58:11.42#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.162.07:58:11.42#ibcon#about to clear, iclass 34 cls_cnt 0 2006.162.07:58:11.42#ibcon#cleared, iclass 34 cls_cnt 0 2006.162.07:58:11.42$vc4f8/va=8,7 2006.162.07:58:11.42#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.162.07:58:11.42#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.162.07:58:11.42#ibcon#ireg 11 cls_cnt 2 2006.162.07:58:11.42#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.162.07:58:11.47#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.162.07:58:11.47#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.162.07:58:11.47#ibcon#enter wrdev, iclass 36, count 2 2006.162.07:58:11.47#ibcon#first serial, iclass 36, count 2 2006.162.07:58:11.47#ibcon#enter sib2, iclass 36, count 2 2006.162.07:58:11.47#ibcon#flushed, iclass 36, count 2 2006.162.07:58:11.47#ibcon#about to write, iclass 36, count 2 2006.162.07:58:11.47#ibcon#wrote, iclass 36, count 2 2006.162.07:58:11.47#ibcon#about to read 3, iclass 36, count 2 2006.162.07:58:11.49#ibcon#read 3, iclass 36, count 2 2006.162.07:58:11.49#ibcon#about to read 4, iclass 36, count 2 2006.162.07:58:11.49#ibcon#read 4, iclass 36, count 2 2006.162.07:58:11.49#ibcon#about to read 5, iclass 36, count 2 2006.162.07:58:11.49#ibcon#read 5, iclass 36, count 2 2006.162.07:58:11.49#ibcon#about to read 6, iclass 36, count 2 2006.162.07:58:11.49#ibcon#read 6, iclass 36, count 2 2006.162.07:58:11.49#ibcon#end of sib2, iclass 36, count 2 2006.162.07:58:11.49#ibcon#*mode == 0, iclass 36, count 2 2006.162.07:58:11.49#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.162.07:58:11.49#ibcon#[25=AT08-07\r\n] 2006.162.07:58:11.49#ibcon#*before write, iclass 36, count 2 2006.162.07:58:11.49#ibcon#enter sib2, iclass 36, count 2 2006.162.07:58:11.49#ibcon#flushed, iclass 36, count 2 2006.162.07:58:11.49#ibcon#about to write, iclass 36, count 2 2006.162.07:58:11.49#ibcon#wrote, iclass 36, count 2 2006.162.07:58:11.49#ibcon#about to read 3, iclass 36, count 2 2006.162.07:58:11.52#ibcon#read 3, iclass 36, count 2 2006.162.07:58:11.52#ibcon#about to read 4, iclass 36, count 2 2006.162.07:58:11.52#ibcon#read 4, iclass 36, count 2 2006.162.07:58:11.52#ibcon#about to read 5, iclass 36, count 2 2006.162.07:58:11.52#ibcon#read 5, iclass 36, count 2 2006.162.07:58:11.52#ibcon#about to read 6, iclass 36, count 2 2006.162.07:58:11.52#ibcon#read 6, iclass 36, count 2 2006.162.07:58:11.52#ibcon#end of sib2, iclass 36, count 2 2006.162.07:58:11.52#ibcon#*after write, iclass 36, count 2 2006.162.07:58:11.52#ibcon#*before return 0, iclass 36, count 2 2006.162.07:58:11.52#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.162.07:58:11.52#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.162.07:58:11.52#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.162.07:58:11.52#ibcon#ireg 7 cls_cnt 0 2006.162.07:58:11.52#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.162.07:58:11.64#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.162.07:58:11.64#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.162.07:58:11.64#ibcon#enter wrdev, iclass 36, count 0 2006.162.07:58:11.64#ibcon#first serial, iclass 36, count 0 2006.162.07:58:11.64#ibcon#enter sib2, iclass 36, count 0 2006.162.07:58:11.64#ibcon#flushed, iclass 36, count 0 2006.162.07:58:11.64#ibcon#about to write, iclass 36, count 0 2006.162.07:58:11.64#ibcon#wrote, iclass 36, count 0 2006.162.07:58:11.64#ibcon#about to read 3, iclass 36, count 0 2006.162.07:58:11.66#ibcon#read 3, iclass 36, count 0 2006.162.07:58:11.66#ibcon#about to read 4, iclass 36, count 0 2006.162.07:58:11.66#ibcon#read 4, iclass 36, count 0 2006.162.07:58:11.66#ibcon#about to read 5, iclass 36, count 0 2006.162.07:58:11.66#ibcon#read 5, iclass 36, count 0 2006.162.07:58:11.66#ibcon#about to read 6, iclass 36, count 0 2006.162.07:58:11.66#ibcon#read 6, iclass 36, count 0 2006.162.07:58:11.66#ibcon#end of sib2, iclass 36, count 0 2006.162.07:58:11.66#ibcon#*mode == 0, iclass 36, count 0 2006.162.07:58:11.66#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.162.07:58:11.66#ibcon#[25=USB\r\n] 2006.162.07:58:11.66#ibcon#*before write, iclass 36, count 0 2006.162.07:58:11.66#ibcon#enter sib2, iclass 36, count 0 2006.162.07:58:11.66#ibcon#flushed, iclass 36, count 0 2006.162.07:58:11.66#ibcon#about to write, iclass 36, count 0 2006.162.07:58:11.66#ibcon#wrote, iclass 36, count 0 2006.162.07:58:11.66#ibcon#about to read 3, iclass 36, count 0 2006.162.07:58:11.69#ibcon#read 3, iclass 36, count 0 2006.162.07:58:11.69#ibcon#about to read 4, iclass 36, count 0 2006.162.07:58:11.69#ibcon#read 4, iclass 36, count 0 2006.162.07:58:11.69#ibcon#about to read 5, iclass 36, count 0 2006.162.07:58:11.69#ibcon#read 5, iclass 36, count 0 2006.162.07:58:11.69#ibcon#about to read 6, iclass 36, count 0 2006.162.07:58:11.69#ibcon#read 6, iclass 36, count 0 2006.162.07:58:11.69#ibcon#end of sib2, iclass 36, count 0 2006.162.07:58:11.69#ibcon#*after write, iclass 36, count 0 2006.162.07:58:11.69#ibcon#*before return 0, iclass 36, count 0 2006.162.07:58:11.69#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.162.07:58:11.69#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.162.07:58:11.69#ibcon#about to clear, iclass 36 cls_cnt 0 2006.162.07:58:11.69#ibcon#cleared, iclass 36 cls_cnt 0 2006.162.07:58:11.69$vc4f8/vblo=1,632.99 2006.162.07:58:11.69#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.162.07:58:11.69#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.162.07:58:11.69#ibcon#ireg 17 cls_cnt 0 2006.162.07:58:11.69#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.162.07:58:11.69#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.162.07:58:11.69#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.162.07:58:11.69#ibcon#enter wrdev, iclass 38, count 0 2006.162.07:58:11.69#ibcon#first serial, iclass 38, count 0 2006.162.07:58:11.69#ibcon#enter sib2, iclass 38, count 0 2006.162.07:58:11.69#ibcon#flushed, iclass 38, count 0 2006.162.07:58:11.69#ibcon#about to write, iclass 38, count 0 2006.162.07:58:11.69#ibcon#wrote, iclass 38, count 0 2006.162.07:58:11.69#ibcon#about to read 3, iclass 38, count 0 2006.162.07:58:11.71#ibcon#read 3, iclass 38, count 0 2006.162.07:58:11.71#ibcon#about to read 4, iclass 38, count 0 2006.162.07:58:11.71#ibcon#read 4, iclass 38, count 0 2006.162.07:58:11.71#ibcon#about to read 5, iclass 38, count 0 2006.162.07:58:11.71#ibcon#read 5, iclass 38, count 0 2006.162.07:58:11.71#ibcon#about to read 6, iclass 38, count 0 2006.162.07:58:11.71#ibcon#read 6, iclass 38, count 0 2006.162.07:58:11.71#ibcon#end of sib2, iclass 38, count 0 2006.162.07:58:11.71#ibcon#*mode == 0, iclass 38, count 0 2006.162.07:58:11.71#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.162.07:58:11.71#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.07:58:11.71#ibcon#*before write, iclass 38, count 0 2006.162.07:58:11.71#ibcon#enter sib2, iclass 38, count 0 2006.162.07:58:11.71#ibcon#flushed, iclass 38, count 0 2006.162.07:58:11.71#ibcon#about to write, iclass 38, count 0 2006.162.07:58:11.71#ibcon#wrote, iclass 38, count 0 2006.162.07:58:11.71#ibcon#about to read 3, iclass 38, count 0 2006.162.07:58:11.75#ibcon#read 3, iclass 38, count 0 2006.162.07:58:11.75#ibcon#about to read 4, iclass 38, count 0 2006.162.07:58:11.75#ibcon#read 4, iclass 38, count 0 2006.162.07:58:11.75#ibcon#about to read 5, iclass 38, count 0 2006.162.07:58:11.75#ibcon#read 5, iclass 38, count 0 2006.162.07:58:11.75#ibcon#about to read 6, iclass 38, count 0 2006.162.07:58:11.75#ibcon#read 6, iclass 38, count 0 2006.162.07:58:11.75#ibcon#end of sib2, iclass 38, count 0 2006.162.07:58:11.75#ibcon#*after write, iclass 38, count 0 2006.162.07:58:11.75#ibcon#*before return 0, iclass 38, count 0 2006.162.07:58:11.75#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.162.07:58:11.75#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.162.07:58:11.75#ibcon#about to clear, iclass 38 cls_cnt 0 2006.162.07:58:11.75#ibcon#cleared, iclass 38 cls_cnt 0 2006.162.07:58:11.75$vc4f8/vb=1,4 2006.162.07:58:11.75#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.162.07:58:11.75#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.162.07:58:11.75#ibcon#ireg 11 cls_cnt 2 2006.162.07:58:11.75#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.162.07:58:11.75#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.162.07:58:11.75#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.162.07:58:11.75#ibcon#enter wrdev, iclass 40, count 2 2006.162.07:58:11.75#ibcon#first serial, iclass 40, count 2 2006.162.07:58:11.75#ibcon#enter sib2, iclass 40, count 2 2006.162.07:58:11.75#ibcon#flushed, iclass 40, count 2 2006.162.07:58:11.75#ibcon#about to write, iclass 40, count 2 2006.162.07:58:11.75#ibcon#wrote, iclass 40, count 2 2006.162.07:58:11.75#ibcon#about to read 3, iclass 40, count 2 2006.162.07:58:11.77#ibcon#read 3, iclass 40, count 2 2006.162.07:58:11.77#ibcon#about to read 4, iclass 40, count 2 2006.162.07:58:11.77#ibcon#read 4, iclass 40, count 2 2006.162.07:58:11.77#ibcon#about to read 5, iclass 40, count 2 2006.162.07:58:11.77#ibcon#read 5, iclass 40, count 2 2006.162.07:58:11.77#ibcon#about to read 6, iclass 40, count 2 2006.162.07:58:11.77#ibcon#read 6, iclass 40, count 2 2006.162.07:58:11.77#ibcon#end of sib2, iclass 40, count 2 2006.162.07:58:11.77#ibcon#*mode == 0, iclass 40, count 2 2006.162.07:58:11.77#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.162.07:58:11.77#ibcon#[27=AT01-04\r\n] 2006.162.07:58:11.77#ibcon#*before write, iclass 40, count 2 2006.162.07:58:11.77#ibcon#enter sib2, iclass 40, count 2 2006.162.07:58:11.77#ibcon#flushed, iclass 40, count 2 2006.162.07:58:11.77#ibcon#about to write, iclass 40, count 2 2006.162.07:58:11.77#ibcon#wrote, iclass 40, count 2 2006.162.07:58:11.77#ibcon#about to read 3, iclass 40, count 2 2006.162.07:58:11.80#ibcon#read 3, iclass 40, count 2 2006.162.07:58:11.80#ibcon#about to read 4, iclass 40, count 2 2006.162.07:58:11.80#ibcon#read 4, iclass 40, count 2 2006.162.07:58:11.80#ibcon#about to read 5, iclass 40, count 2 2006.162.07:58:11.80#ibcon#read 5, iclass 40, count 2 2006.162.07:58:11.80#ibcon#about to read 6, iclass 40, count 2 2006.162.07:58:11.80#ibcon#read 6, iclass 40, count 2 2006.162.07:58:11.80#ibcon#end of sib2, iclass 40, count 2 2006.162.07:58:11.80#ibcon#*after write, iclass 40, count 2 2006.162.07:58:11.80#ibcon#*before return 0, iclass 40, count 2 2006.162.07:58:11.80#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.162.07:58:11.80#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.162.07:58:11.80#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.162.07:58:11.80#ibcon#ireg 7 cls_cnt 0 2006.162.07:58:11.80#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.162.07:58:11.92#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.162.07:58:11.92#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.162.07:58:11.92#ibcon#enter wrdev, iclass 40, count 0 2006.162.07:58:11.92#ibcon#first serial, iclass 40, count 0 2006.162.07:58:11.92#ibcon#enter sib2, iclass 40, count 0 2006.162.07:58:11.92#ibcon#flushed, iclass 40, count 0 2006.162.07:58:11.92#ibcon#about to write, iclass 40, count 0 2006.162.07:58:11.92#ibcon#wrote, iclass 40, count 0 2006.162.07:58:11.92#ibcon#about to read 3, iclass 40, count 0 2006.162.07:58:11.94#ibcon#read 3, iclass 40, count 0 2006.162.07:58:11.94#ibcon#about to read 4, iclass 40, count 0 2006.162.07:58:11.94#ibcon#read 4, iclass 40, count 0 2006.162.07:58:11.94#ibcon#about to read 5, iclass 40, count 0 2006.162.07:58:11.94#ibcon#read 5, iclass 40, count 0 2006.162.07:58:11.94#ibcon#about to read 6, iclass 40, count 0 2006.162.07:58:11.94#ibcon#read 6, iclass 40, count 0 2006.162.07:58:11.94#ibcon#end of sib2, iclass 40, count 0 2006.162.07:58:11.94#ibcon#*mode == 0, iclass 40, count 0 2006.162.07:58:11.94#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.162.07:58:11.94#ibcon#[27=USB\r\n] 2006.162.07:58:11.94#ibcon#*before write, iclass 40, count 0 2006.162.07:58:11.94#ibcon#enter sib2, iclass 40, count 0 2006.162.07:58:11.94#ibcon#flushed, iclass 40, count 0 2006.162.07:58:11.94#ibcon#about to write, iclass 40, count 0 2006.162.07:58:11.94#ibcon#wrote, iclass 40, count 0 2006.162.07:58:11.94#ibcon#about to read 3, iclass 40, count 0 2006.162.07:58:11.97#ibcon#read 3, iclass 40, count 0 2006.162.07:58:11.97#ibcon#about to read 4, iclass 40, count 0 2006.162.07:58:11.97#ibcon#read 4, iclass 40, count 0 2006.162.07:58:11.97#ibcon#about to read 5, iclass 40, count 0 2006.162.07:58:11.97#ibcon#read 5, iclass 40, count 0 2006.162.07:58:11.97#ibcon#about to read 6, iclass 40, count 0 2006.162.07:58:11.97#ibcon#read 6, iclass 40, count 0 2006.162.07:58:11.97#ibcon#end of sib2, iclass 40, count 0 2006.162.07:58:11.97#ibcon#*after write, iclass 40, count 0 2006.162.07:58:11.97#ibcon#*before return 0, iclass 40, count 0 2006.162.07:58:11.97#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.162.07:58:11.97#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.162.07:58:11.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.162.07:58:11.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.162.07:58:11.97$vc4f8/vblo=2,640.99 2006.162.07:58:11.97#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.162.07:58:11.97#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.162.07:58:11.97#ibcon#ireg 17 cls_cnt 0 2006.162.07:58:11.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.162.07:58:11.97#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.162.07:58:11.97#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.162.07:58:11.97#ibcon#enter wrdev, iclass 4, count 0 2006.162.07:58:11.97#ibcon#first serial, iclass 4, count 0 2006.162.07:58:11.97#ibcon#enter sib2, iclass 4, count 0 2006.162.07:58:11.97#ibcon#flushed, iclass 4, count 0 2006.162.07:58:11.97#ibcon#about to write, iclass 4, count 0 2006.162.07:58:11.97#ibcon#wrote, iclass 4, count 0 2006.162.07:58:11.97#ibcon#about to read 3, iclass 4, count 0 2006.162.07:58:11.99#ibcon#read 3, iclass 4, count 0 2006.162.07:58:11.99#ibcon#about to read 4, iclass 4, count 0 2006.162.07:58:11.99#ibcon#read 4, iclass 4, count 0 2006.162.07:58:11.99#ibcon#about to read 5, iclass 4, count 0 2006.162.07:58:11.99#ibcon#read 5, iclass 4, count 0 2006.162.07:58:11.99#ibcon#about to read 6, iclass 4, count 0 2006.162.07:58:11.99#ibcon#read 6, iclass 4, count 0 2006.162.07:58:11.99#ibcon#end of sib2, iclass 4, count 0 2006.162.07:58:11.99#ibcon#*mode == 0, iclass 4, count 0 2006.162.07:58:11.99#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.162.07:58:11.99#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.07:58:11.99#ibcon#*before write, iclass 4, count 0 2006.162.07:58:11.99#ibcon#enter sib2, iclass 4, count 0 2006.162.07:58:11.99#ibcon#flushed, iclass 4, count 0 2006.162.07:58:11.99#ibcon#about to write, iclass 4, count 0 2006.162.07:58:11.99#ibcon#wrote, iclass 4, count 0 2006.162.07:58:11.99#ibcon#about to read 3, iclass 4, count 0 2006.162.07:58:12.03#ibcon#read 3, iclass 4, count 0 2006.162.07:58:12.03#ibcon#about to read 4, iclass 4, count 0 2006.162.07:58:12.03#ibcon#read 4, iclass 4, count 0 2006.162.07:58:12.03#ibcon#about to read 5, iclass 4, count 0 2006.162.07:58:12.03#ibcon#read 5, iclass 4, count 0 2006.162.07:58:12.03#ibcon#about to read 6, iclass 4, count 0 2006.162.07:58:12.03#ibcon#read 6, iclass 4, count 0 2006.162.07:58:12.03#ibcon#end of sib2, iclass 4, count 0 2006.162.07:58:12.03#ibcon#*after write, iclass 4, count 0 2006.162.07:58:12.03#ibcon#*before return 0, iclass 4, count 0 2006.162.07:58:12.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.162.07:58:12.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.162.07:58:12.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.162.07:58:12.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.162.07:58:12.03$vc4f8/vb=2,4 2006.162.07:58:12.03#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.162.07:58:12.03#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.162.07:58:12.03#ibcon#ireg 11 cls_cnt 2 2006.162.07:58:12.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.162.07:58:12.09#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.162.07:58:12.09#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.162.07:58:12.09#ibcon#enter wrdev, iclass 6, count 2 2006.162.07:58:12.09#ibcon#first serial, iclass 6, count 2 2006.162.07:58:12.09#ibcon#enter sib2, iclass 6, count 2 2006.162.07:58:12.09#ibcon#flushed, iclass 6, count 2 2006.162.07:58:12.09#ibcon#about to write, iclass 6, count 2 2006.162.07:58:12.09#ibcon#wrote, iclass 6, count 2 2006.162.07:58:12.09#ibcon#about to read 3, iclass 6, count 2 2006.162.07:58:12.11#ibcon#read 3, iclass 6, count 2 2006.162.07:58:12.11#ibcon#about to read 4, iclass 6, count 2 2006.162.07:58:12.11#ibcon#read 4, iclass 6, count 2 2006.162.07:58:12.11#ibcon#about to read 5, iclass 6, count 2 2006.162.07:58:12.11#ibcon#read 5, iclass 6, count 2 2006.162.07:58:12.11#ibcon#about to read 6, iclass 6, count 2 2006.162.07:58:12.11#ibcon#read 6, iclass 6, count 2 2006.162.07:58:12.11#ibcon#end of sib2, iclass 6, count 2 2006.162.07:58:12.11#ibcon#*mode == 0, iclass 6, count 2 2006.162.07:58:12.11#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.162.07:58:12.11#ibcon#[27=AT02-04\r\n] 2006.162.07:58:12.11#ibcon#*before write, iclass 6, count 2 2006.162.07:58:12.11#ibcon#enter sib2, iclass 6, count 2 2006.162.07:58:12.11#ibcon#flushed, iclass 6, count 2 2006.162.07:58:12.11#ibcon#about to write, iclass 6, count 2 2006.162.07:58:12.11#ibcon#wrote, iclass 6, count 2 2006.162.07:58:12.11#ibcon#about to read 3, iclass 6, count 2 2006.162.07:58:12.14#ibcon#read 3, iclass 6, count 2 2006.162.07:58:12.14#ibcon#about to read 4, iclass 6, count 2 2006.162.07:58:12.14#ibcon#read 4, iclass 6, count 2 2006.162.07:58:12.14#ibcon#about to read 5, iclass 6, count 2 2006.162.07:58:12.14#ibcon#read 5, iclass 6, count 2 2006.162.07:58:12.14#ibcon#about to read 6, iclass 6, count 2 2006.162.07:58:12.14#ibcon#read 6, iclass 6, count 2 2006.162.07:58:12.14#ibcon#end of sib2, iclass 6, count 2 2006.162.07:58:12.14#ibcon#*after write, iclass 6, count 2 2006.162.07:58:12.14#ibcon#*before return 0, iclass 6, count 2 2006.162.07:58:12.14#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.162.07:58:12.14#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.162.07:58:12.14#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.162.07:58:12.14#ibcon#ireg 7 cls_cnt 0 2006.162.07:58:12.14#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.162.07:58:12.26#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.162.07:58:12.26#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.162.07:58:12.26#ibcon#enter wrdev, iclass 6, count 0 2006.162.07:58:12.26#ibcon#first serial, iclass 6, count 0 2006.162.07:58:12.26#ibcon#enter sib2, iclass 6, count 0 2006.162.07:58:12.26#ibcon#flushed, iclass 6, count 0 2006.162.07:58:12.26#ibcon#about to write, iclass 6, count 0 2006.162.07:58:12.26#ibcon#wrote, iclass 6, count 0 2006.162.07:58:12.26#ibcon#about to read 3, iclass 6, count 0 2006.162.07:58:12.28#ibcon#read 3, iclass 6, count 0 2006.162.07:58:12.28#ibcon#about to read 4, iclass 6, count 0 2006.162.07:58:12.28#ibcon#read 4, iclass 6, count 0 2006.162.07:58:12.28#ibcon#about to read 5, iclass 6, count 0 2006.162.07:58:12.28#ibcon#read 5, iclass 6, count 0 2006.162.07:58:12.28#ibcon#about to read 6, iclass 6, count 0 2006.162.07:58:12.28#ibcon#read 6, iclass 6, count 0 2006.162.07:58:12.28#ibcon#end of sib2, iclass 6, count 0 2006.162.07:58:12.28#ibcon#*mode == 0, iclass 6, count 0 2006.162.07:58:12.28#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.162.07:58:12.28#ibcon#[27=USB\r\n] 2006.162.07:58:12.28#ibcon#*before write, iclass 6, count 0 2006.162.07:58:12.28#ibcon#enter sib2, iclass 6, count 0 2006.162.07:58:12.28#ibcon#flushed, iclass 6, count 0 2006.162.07:58:12.28#ibcon#about to write, iclass 6, count 0 2006.162.07:58:12.28#ibcon#wrote, iclass 6, count 0 2006.162.07:58:12.28#ibcon#about to read 3, iclass 6, count 0 2006.162.07:58:12.31#ibcon#read 3, iclass 6, count 0 2006.162.07:58:12.31#ibcon#about to read 4, iclass 6, count 0 2006.162.07:58:12.31#ibcon#read 4, iclass 6, count 0 2006.162.07:58:12.31#ibcon#about to read 5, iclass 6, count 0 2006.162.07:58:12.31#ibcon#read 5, iclass 6, count 0 2006.162.07:58:12.31#ibcon#about to read 6, iclass 6, count 0 2006.162.07:58:12.31#ibcon#read 6, iclass 6, count 0 2006.162.07:58:12.31#ibcon#end of sib2, iclass 6, count 0 2006.162.07:58:12.31#ibcon#*after write, iclass 6, count 0 2006.162.07:58:12.31#ibcon#*before return 0, iclass 6, count 0 2006.162.07:58:12.31#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.162.07:58:12.31#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.162.07:58:12.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.162.07:58:12.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.162.07:58:12.31$vc4f8/vblo=3,656.99 2006.162.07:58:12.31#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.162.07:58:12.31#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.162.07:58:12.31#ibcon#ireg 17 cls_cnt 0 2006.162.07:58:12.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.162.07:58:12.31#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.162.07:58:12.31#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.162.07:58:12.31#ibcon#enter wrdev, iclass 10, count 0 2006.162.07:58:12.31#ibcon#first serial, iclass 10, count 0 2006.162.07:58:12.31#ibcon#enter sib2, iclass 10, count 0 2006.162.07:58:12.31#ibcon#flushed, iclass 10, count 0 2006.162.07:58:12.31#ibcon#about to write, iclass 10, count 0 2006.162.07:58:12.31#ibcon#wrote, iclass 10, count 0 2006.162.07:58:12.31#ibcon#about to read 3, iclass 10, count 0 2006.162.07:58:12.33#ibcon#read 3, iclass 10, count 0 2006.162.07:58:12.33#ibcon#about to read 4, iclass 10, count 0 2006.162.07:58:12.33#ibcon#read 4, iclass 10, count 0 2006.162.07:58:12.33#ibcon#about to read 5, iclass 10, count 0 2006.162.07:58:12.33#ibcon#read 5, iclass 10, count 0 2006.162.07:58:12.33#ibcon#about to read 6, iclass 10, count 0 2006.162.07:58:12.33#ibcon#read 6, iclass 10, count 0 2006.162.07:58:12.33#ibcon#end of sib2, iclass 10, count 0 2006.162.07:58:12.33#ibcon#*mode == 0, iclass 10, count 0 2006.162.07:58:12.33#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.162.07:58:12.33#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.07:58:12.33#ibcon#*before write, iclass 10, count 0 2006.162.07:58:12.33#ibcon#enter sib2, iclass 10, count 0 2006.162.07:58:12.33#ibcon#flushed, iclass 10, count 0 2006.162.07:58:12.33#ibcon#about to write, iclass 10, count 0 2006.162.07:58:12.33#ibcon#wrote, iclass 10, count 0 2006.162.07:58:12.33#ibcon#about to read 3, iclass 10, count 0 2006.162.07:58:12.37#ibcon#read 3, iclass 10, count 0 2006.162.07:58:12.37#ibcon#about to read 4, iclass 10, count 0 2006.162.07:58:12.37#ibcon#read 4, iclass 10, count 0 2006.162.07:58:12.37#ibcon#about to read 5, iclass 10, count 0 2006.162.07:58:12.37#ibcon#read 5, iclass 10, count 0 2006.162.07:58:12.37#ibcon#about to read 6, iclass 10, count 0 2006.162.07:58:12.37#ibcon#read 6, iclass 10, count 0 2006.162.07:58:12.37#ibcon#end of sib2, iclass 10, count 0 2006.162.07:58:12.37#ibcon#*after write, iclass 10, count 0 2006.162.07:58:12.37#ibcon#*before return 0, iclass 10, count 0 2006.162.07:58:12.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.162.07:58:12.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.162.07:58:12.37#ibcon#about to clear, iclass 10 cls_cnt 0 2006.162.07:58:12.37#ibcon#cleared, iclass 10 cls_cnt 0 2006.162.07:58:12.37$vc4f8/vb=3,4 2006.162.07:58:12.37#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.162.07:58:12.37#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.162.07:58:12.37#ibcon#ireg 11 cls_cnt 2 2006.162.07:58:12.37#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.162.07:58:12.43#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.162.07:58:12.43#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.162.07:58:12.43#ibcon#enter wrdev, iclass 12, count 2 2006.162.07:58:12.43#ibcon#first serial, iclass 12, count 2 2006.162.07:58:12.43#ibcon#enter sib2, iclass 12, count 2 2006.162.07:58:12.43#ibcon#flushed, iclass 12, count 2 2006.162.07:58:12.43#ibcon#about to write, iclass 12, count 2 2006.162.07:58:12.43#ibcon#wrote, iclass 12, count 2 2006.162.07:58:12.43#ibcon#about to read 3, iclass 12, count 2 2006.162.07:58:12.45#ibcon#read 3, iclass 12, count 2 2006.162.07:58:12.45#ibcon#about to read 4, iclass 12, count 2 2006.162.07:58:12.45#ibcon#read 4, iclass 12, count 2 2006.162.07:58:12.45#ibcon#about to read 5, iclass 12, count 2 2006.162.07:58:12.45#ibcon#read 5, iclass 12, count 2 2006.162.07:58:12.45#ibcon#about to read 6, iclass 12, count 2 2006.162.07:58:12.45#ibcon#read 6, iclass 12, count 2 2006.162.07:58:12.45#ibcon#end of sib2, iclass 12, count 2 2006.162.07:58:12.45#ibcon#*mode == 0, iclass 12, count 2 2006.162.07:58:12.45#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.162.07:58:12.45#ibcon#[27=AT03-04\r\n] 2006.162.07:58:12.45#ibcon#*before write, iclass 12, count 2 2006.162.07:58:12.45#ibcon#enter sib2, iclass 12, count 2 2006.162.07:58:12.45#ibcon#flushed, iclass 12, count 2 2006.162.07:58:12.45#ibcon#about to write, iclass 12, count 2 2006.162.07:58:12.45#ibcon#wrote, iclass 12, count 2 2006.162.07:58:12.45#ibcon#about to read 3, iclass 12, count 2 2006.162.07:58:12.48#ibcon#read 3, iclass 12, count 2 2006.162.07:58:12.48#ibcon#about to read 4, iclass 12, count 2 2006.162.07:58:12.48#ibcon#read 4, iclass 12, count 2 2006.162.07:58:12.48#ibcon#about to read 5, iclass 12, count 2 2006.162.07:58:12.48#ibcon#read 5, iclass 12, count 2 2006.162.07:58:12.48#ibcon#about to read 6, iclass 12, count 2 2006.162.07:58:12.48#ibcon#read 6, iclass 12, count 2 2006.162.07:58:12.48#ibcon#end of sib2, iclass 12, count 2 2006.162.07:58:12.48#ibcon#*after write, iclass 12, count 2 2006.162.07:58:12.48#ibcon#*before return 0, iclass 12, count 2 2006.162.07:58:12.48#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.162.07:58:12.48#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.162.07:58:12.48#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.162.07:58:12.48#ibcon#ireg 7 cls_cnt 0 2006.162.07:58:12.48#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.162.07:58:12.60#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.162.07:58:12.60#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.162.07:58:12.60#ibcon#enter wrdev, iclass 12, count 0 2006.162.07:58:12.60#ibcon#first serial, iclass 12, count 0 2006.162.07:58:12.60#ibcon#enter sib2, iclass 12, count 0 2006.162.07:58:12.60#ibcon#flushed, iclass 12, count 0 2006.162.07:58:12.60#ibcon#about to write, iclass 12, count 0 2006.162.07:58:12.60#ibcon#wrote, iclass 12, count 0 2006.162.07:58:12.60#ibcon#about to read 3, iclass 12, count 0 2006.162.07:58:12.62#ibcon#read 3, iclass 12, count 0 2006.162.07:58:12.62#ibcon#about to read 4, iclass 12, count 0 2006.162.07:58:12.62#ibcon#read 4, iclass 12, count 0 2006.162.07:58:12.62#ibcon#about to read 5, iclass 12, count 0 2006.162.07:58:12.62#ibcon#read 5, iclass 12, count 0 2006.162.07:58:12.62#ibcon#about to read 6, iclass 12, count 0 2006.162.07:58:12.62#ibcon#read 6, iclass 12, count 0 2006.162.07:58:12.62#ibcon#end of sib2, iclass 12, count 0 2006.162.07:58:12.62#ibcon#*mode == 0, iclass 12, count 0 2006.162.07:58:12.62#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.162.07:58:12.62#ibcon#[27=USB\r\n] 2006.162.07:58:12.62#ibcon#*before write, iclass 12, count 0 2006.162.07:58:12.62#ibcon#enter sib2, iclass 12, count 0 2006.162.07:58:12.62#ibcon#flushed, iclass 12, count 0 2006.162.07:58:12.62#ibcon#about to write, iclass 12, count 0 2006.162.07:58:12.62#ibcon#wrote, iclass 12, count 0 2006.162.07:58:12.62#ibcon#about to read 3, iclass 12, count 0 2006.162.07:58:12.65#ibcon#read 3, iclass 12, count 0 2006.162.07:58:12.65#ibcon#about to read 4, iclass 12, count 0 2006.162.07:58:12.65#ibcon#read 4, iclass 12, count 0 2006.162.07:58:12.65#ibcon#about to read 5, iclass 12, count 0 2006.162.07:58:12.65#ibcon#read 5, iclass 12, count 0 2006.162.07:58:12.65#ibcon#about to read 6, iclass 12, count 0 2006.162.07:58:12.65#ibcon#read 6, iclass 12, count 0 2006.162.07:58:12.65#ibcon#end of sib2, iclass 12, count 0 2006.162.07:58:12.65#ibcon#*after write, iclass 12, count 0 2006.162.07:58:12.65#ibcon#*before return 0, iclass 12, count 0 2006.162.07:58:12.65#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.162.07:58:12.65#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.162.07:58:12.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.162.07:58:12.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.162.07:58:12.65$vc4f8/vblo=4,712.99 2006.162.07:58:12.65#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.162.07:58:12.65#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.162.07:58:12.65#ibcon#ireg 17 cls_cnt 0 2006.162.07:58:12.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.07:58:12.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.07:58:12.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.07:58:12.65#ibcon#enter wrdev, iclass 14, count 0 2006.162.07:58:12.65#ibcon#first serial, iclass 14, count 0 2006.162.07:58:12.65#ibcon#enter sib2, iclass 14, count 0 2006.162.07:58:12.65#ibcon#flushed, iclass 14, count 0 2006.162.07:58:12.65#ibcon#about to write, iclass 14, count 0 2006.162.07:58:12.65#ibcon#wrote, iclass 14, count 0 2006.162.07:58:12.65#ibcon#about to read 3, iclass 14, count 0 2006.162.07:58:12.67#ibcon#read 3, iclass 14, count 0 2006.162.07:58:12.67#ibcon#about to read 4, iclass 14, count 0 2006.162.07:58:12.67#ibcon#read 4, iclass 14, count 0 2006.162.07:58:12.67#ibcon#about to read 5, iclass 14, count 0 2006.162.07:58:12.67#ibcon#read 5, iclass 14, count 0 2006.162.07:58:12.67#ibcon#about to read 6, iclass 14, count 0 2006.162.07:58:12.67#ibcon#read 6, iclass 14, count 0 2006.162.07:58:12.67#ibcon#end of sib2, iclass 14, count 0 2006.162.07:58:12.67#ibcon#*mode == 0, iclass 14, count 0 2006.162.07:58:12.67#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.07:58:12.67#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.07:58:12.67#ibcon#*before write, iclass 14, count 0 2006.162.07:58:12.67#ibcon#enter sib2, iclass 14, count 0 2006.162.07:58:12.67#ibcon#flushed, iclass 14, count 0 2006.162.07:58:12.67#ibcon#about to write, iclass 14, count 0 2006.162.07:58:12.67#ibcon#wrote, iclass 14, count 0 2006.162.07:58:12.67#ibcon#about to read 3, iclass 14, count 0 2006.162.07:58:12.71#ibcon#read 3, iclass 14, count 0 2006.162.07:58:12.71#ibcon#about to read 4, iclass 14, count 0 2006.162.07:58:12.71#ibcon#read 4, iclass 14, count 0 2006.162.07:58:12.71#ibcon#about to read 5, iclass 14, count 0 2006.162.07:58:12.71#ibcon#read 5, iclass 14, count 0 2006.162.07:58:12.71#ibcon#about to read 6, iclass 14, count 0 2006.162.07:58:12.71#ibcon#read 6, iclass 14, count 0 2006.162.07:58:12.71#ibcon#end of sib2, iclass 14, count 0 2006.162.07:58:12.71#ibcon#*after write, iclass 14, count 0 2006.162.07:58:12.71#ibcon#*before return 0, iclass 14, count 0 2006.162.07:58:12.71#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.07:58:12.71#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.162.07:58:12.71#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.07:58:12.71#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.07:58:12.71$vc4f8/vb=4,4 2006.162.07:58:12.71#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.162.07:58:12.71#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.162.07:58:12.71#ibcon#ireg 11 cls_cnt 2 2006.162.07:58:12.71#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.162.07:58:12.77#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.162.07:58:12.77#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.162.07:58:12.77#ibcon#enter wrdev, iclass 16, count 2 2006.162.07:58:12.77#ibcon#first serial, iclass 16, count 2 2006.162.07:58:12.77#ibcon#enter sib2, iclass 16, count 2 2006.162.07:58:12.77#ibcon#flushed, iclass 16, count 2 2006.162.07:58:12.77#ibcon#about to write, iclass 16, count 2 2006.162.07:58:12.77#ibcon#wrote, iclass 16, count 2 2006.162.07:58:12.77#ibcon#about to read 3, iclass 16, count 2 2006.162.07:58:12.79#ibcon#read 3, iclass 16, count 2 2006.162.07:58:12.79#ibcon#about to read 4, iclass 16, count 2 2006.162.07:58:12.79#ibcon#read 4, iclass 16, count 2 2006.162.07:58:12.79#ibcon#about to read 5, iclass 16, count 2 2006.162.07:58:12.79#ibcon#read 5, iclass 16, count 2 2006.162.07:58:12.79#ibcon#about to read 6, iclass 16, count 2 2006.162.07:58:12.79#ibcon#read 6, iclass 16, count 2 2006.162.07:58:12.79#ibcon#end of sib2, iclass 16, count 2 2006.162.07:58:12.79#ibcon#*mode == 0, iclass 16, count 2 2006.162.07:58:12.79#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.162.07:58:12.79#ibcon#[27=AT04-04\r\n] 2006.162.07:58:12.79#ibcon#*before write, iclass 16, count 2 2006.162.07:58:12.79#ibcon#enter sib2, iclass 16, count 2 2006.162.07:58:12.79#ibcon#flushed, iclass 16, count 2 2006.162.07:58:12.79#ibcon#about to write, iclass 16, count 2 2006.162.07:58:12.79#ibcon#wrote, iclass 16, count 2 2006.162.07:58:12.79#ibcon#about to read 3, iclass 16, count 2 2006.162.07:58:12.82#ibcon#read 3, iclass 16, count 2 2006.162.07:58:12.82#ibcon#about to read 4, iclass 16, count 2 2006.162.07:58:12.82#ibcon#read 4, iclass 16, count 2 2006.162.07:58:12.82#ibcon#about to read 5, iclass 16, count 2 2006.162.07:58:12.82#ibcon#read 5, iclass 16, count 2 2006.162.07:58:12.82#ibcon#about to read 6, iclass 16, count 2 2006.162.07:58:12.82#ibcon#read 6, iclass 16, count 2 2006.162.07:58:12.82#ibcon#end of sib2, iclass 16, count 2 2006.162.07:58:12.82#ibcon#*after write, iclass 16, count 2 2006.162.07:58:12.82#ibcon#*before return 0, iclass 16, count 2 2006.162.07:58:12.82#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.162.07:58:12.82#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.162.07:58:12.82#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.162.07:58:12.82#ibcon#ireg 7 cls_cnt 0 2006.162.07:58:12.82#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.162.07:58:12.94#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.162.07:58:12.94#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.162.07:58:12.94#ibcon#enter wrdev, iclass 16, count 0 2006.162.07:58:12.94#ibcon#first serial, iclass 16, count 0 2006.162.07:58:12.94#ibcon#enter sib2, iclass 16, count 0 2006.162.07:58:12.94#ibcon#flushed, iclass 16, count 0 2006.162.07:58:12.94#ibcon#about to write, iclass 16, count 0 2006.162.07:58:12.94#ibcon#wrote, iclass 16, count 0 2006.162.07:58:12.94#ibcon#about to read 3, iclass 16, count 0 2006.162.07:58:12.96#ibcon#read 3, iclass 16, count 0 2006.162.07:58:12.96#ibcon#about to read 4, iclass 16, count 0 2006.162.07:58:12.96#ibcon#read 4, iclass 16, count 0 2006.162.07:58:12.96#ibcon#about to read 5, iclass 16, count 0 2006.162.07:58:12.96#ibcon#read 5, iclass 16, count 0 2006.162.07:58:12.96#ibcon#about to read 6, iclass 16, count 0 2006.162.07:58:12.96#ibcon#read 6, iclass 16, count 0 2006.162.07:58:12.96#ibcon#end of sib2, iclass 16, count 0 2006.162.07:58:12.96#ibcon#*mode == 0, iclass 16, count 0 2006.162.07:58:12.96#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.162.07:58:12.96#ibcon#[27=USB\r\n] 2006.162.07:58:12.96#ibcon#*before write, iclass 16, count 0 2006.162.07:58:12.96#ibcon#enter sib2, iclass 16, count 0 2006.162.07:58:12.96#ibcon#flushed, iclass 16, count 0 2006.162.07:58:12.96#ibcon#about to write, iclass 16, count 0 2006.162.07:58:12.96#ibcon#wrote, iclass 16, count 0 2006.162.07:58:12.96#ibcon#about to read 3, iclass 16, count 0 2006.162.07:58:12.99#ibcon#read 3, iclass 16, count 0 2006.162.07:58:12.99#ibcon#about to read 4, iclass 16, count 0 2006.162.07:58:12.99#ibcon#read 4, iclass 16, count 0 2006.162.07:58:12.99#ibcon#about to read 5, iclass 16, count 0 2006.162.07:58:12.99#ibcon#read 5, iclass 16, count 0 2006.162.07:58:12.99#ibcon#about to read 6, iclass 16, count 0 2006.162.07:58:12.99#ibcon#read 6, iclass 16, count 0 2006.162.07:58:12.99#ibcon#end of sib2, iclass 16, count 0 2006.162.07:58:12.99#ibcon#*after write, iclass 16, count 0 2006.162.07:58:12.99#ibcon#*before return 0, iclass 16, count 0 2006.162.07:58:12.99#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.162.07:58:12.99#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.162.07:58:12.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.162.07:58:12.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.162.07:58:12.99$vc4f8/vblo=5,744.99 2006.162.07:58:12.99#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.162.07:58:12.99#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.162.07:58:12.99#ibcon#ireg 17 cls_cnt 0 2006.162.07:58:12.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:58:12.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:58:12.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:58:12.99#ibcon#enter wrdev, iclass 18, count 0 2006.162.07:58:12.99#ibcon#first serial, iclass 18, count 0 2006.162.07:58:12.99#ibcon#enter sib2, iclass 18, count 0 2006.162.07:58:12.99#ibcon#flushed, iclass 18, count 0 2006.162.07:58:12.99#ibcon#about to write, iclass 18, count 0 2006.162.07:58:12.99#ibcon#wrote, iclass 18, count 0 2006.162.07:58:12.99#ibcon#about to read 3, iclass 18, count 0 2006.162.07:58:13.01#ibcon#read 3, iclass 18, count 0 2006.162.07:58:13.01#ibcon#about to read 4, iclass 18, count 0 2006.162.07:58:13.01#ibcon#read 4, iclass 18, count 0 2006.162.07:58:13.01#ibcon#about to read 5, iclass 18, count 0 2006.162.07:58:13.01#ibcon#read 5, iclass 18, count 0 2006.162.07:58:13.01#ibcon#about to read 6, iclass 18, count 0 2006.162.07:58:13.01#ibcon#read 6, iclass 18, count 0 2006.162.07:58:13.01#ibcon#end of sib2, iclass 18, count 0 2006.162.07:58:13.01#ibcon#*mode == 0, iclass 18, count 0 2006.162.07:58:13.01#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.162.07:58:13.01#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.07:58:13.01#ibcon#*before write, iclass 18, count 0 2006.162.07:58:13.01#ibcon#enter sib2, iclass 18, count 0 2006.162.07:58:13.01#ibcon#flushed, iclass 18, count 0 2006.162.07:58:13.01#ibcon#about to write, iclass 18, count 0 2006.162.07:58:13.01#ibcon#wrote, iclass 18, count 0 2006.162.07:58:13.01#ibcon#about to read 3, iclass 18, count 0 2006.162.07:58:13.05#ibcon#read 3, iclass 18, count 0 2006.162.07:58:13.05#ibcon#about to read 4, iclass 18, count 0 2006.162.07:58:13.05#ibcon#read 4, iclass 18, count 0 2006.162.07:58:13.05#ibcon#about to read 5, iclass 18, count 0 2006.162.07:58:13.05#ibcon#read 5, iclass 18, count 0 2006.162.07:58:13.05#ibcon#about to read 6, iclass 18, count 0 2006.162.07:58:13.05#ibcon#read 6, iclass 18, count 0 2006.162.07:58:13.05#ibcon#end of sib2, iclass 18, count 0 2006.162.07:58:13.05#ibcon#*after write, iclass 18, count 0 2006.162.07:58:13.05#ibcon#*before return 0, iclass 18, count 0 2006.162.07:58:13.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:58:13.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.162.07:58:13.05#ibcon#about to clear, iclass 18 cls_cnt 0 2006.162.07:58:13.05#ibcon#cleared, iclass 18 cls_cnt 0 2006.162.07:58:13.05$vc4f8/vb=5,4 2006.162.07:58:13.05#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.162.07:58:13.05#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.162.07:58:13.05#ibcon#ireg 11 cls_cnt 2 2006.162.07:58:13.05#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:58:13.11#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:58:13.11#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:58:13.11#ibcon#enter wrdev, iclass 20, count 2 2006.162.07:58:13.11#ibcon#first serial, iclass 20, count 2 2006.162.07:58:13.11#ibcon#enter sib2, iclass 20, count 2 2006.162.07:58:13.11#ibcon#flushed, iclass 20, count 2 2006.162.07:58:13.11#ibcon#about to write, iclass 20, count 2 2006.162.07:58:13.11#ibcon#wrote, iclass 20, count 2 2006.162.07:58:13.11#ibcon#about to read 3, iclass 20, count 2 2006.162.07:58:13.13#ibcon#read 3, iclass 20, count 2 2006.162.07:58:13.13#ibcon#about to read 4, iclass 20, count 2 2006.162.07:58:13.13#ibcon#read 4, iclass 20, count 2 2006.162.07:58:13.13#ibcon#about to read 5, iclass 20, count 2 2006.162.07:58:13.13#ibcon#read 5, iclass 20, count 2 2006.162.07:58:13.13#ibcon#about to read 6, iclass 20, count 2 2006.162.07:58:13.13#ibcon#read 6, iclass 20, count 2 2006.162.07:58:13.13#ibcon#end of sib2, iclass 20, count 2 2006.162.07:58:13.13#ibcon#*mode == 0, iclass 20, count 2 2006.162.07:58:13.13#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.162.07:58:13.13#ibcon#[27=AT05-04\r\n] 2006.162.07:58:13.13#ibcon#*before write, iclass 20, count 2 2006.162.07:58:13.13#ibcon#enter sib2, iclass 20, count 2 2006.162.07:58:13.13#ibcon#flushed, iclass 20, count 2 2006.162.07:58:13.13#ibcon#about to write, iclass 20, count 2 2006.162.07:58:13.13#ibcon#wrote, iclass 20, count 2 2006.162.07:58:13.13#ibcon#about to read 3, iclass 20, count 2 2006.162.07:58:13.16#ibcon#read 3, iclass 20, count 2 2006.162.07:58:13.16#ibcon#about to read 4, iclass 20, count 2 2006.162.07:58:13.16#ibcon#read 4, iclass 20, count 2 2006.162.07:58:13.16#ibcon#about to read 5, iclass 20, count 2 2006.162.07:58:13.16#ibcon#read 5, iclass 20, count 2 2006.162.07:58:13.16#ibcon#about to read 6, iclass 20, count 2 2006.162.07:58:13.16#ibcon#read 6, iclass 20, count 2 2006.162.07:58:13.16#ibcon#end of sib2, iclass 20, count 2 2006.162.07:58:13.16#ibcon#*after write, iclass 20, count 2 2006.162.07:58:13.16#ibcon#*before return 0, iclass 20, count 2 2006.162.07:58:13.16#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:58:13.16#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.162.07:58:13.16#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.162.07:58:13.16#ibcon#ireg 7 cls_cnt 0 2006.162.07:58:13.16#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:58:13.28#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:58:13.28#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:58:13.28#ibcon#enter wrdev, iclass 20, count 0 2006.162.07:58:13.28#ibcon#first serial, iclass 20, count 0 2006.162.07:58:13.28#ibcon#enter sib2, iclass 20, count 0 2006.162.07:58:13.28#ibcon#flushed, iclass 20, count 0 2006.162.07:58:13.28#ibcon#about to write, iclass 20, count 0 2006.162.07:58:13.28#ibcon#wrote, iclass 20, count 0 2006.162.07:58:13.28#ibcon#about to read 3, iclass 20, count 0 2006.162.07:58:13.30#ibcon#read 3, iclass 20, count 0 2006.162.07:58:13.30#ibcon#about to read 4, iclass 20, count 0 2006.162.07:58:13.30#ibcon#read 4, iclass 20, count 0 2006.162.07:58:13.30#ibcon#about to read 5, iclass 20, count 0 2006.162.07:58:13.30#ibcon#read 5, iclass 20, count 0 2006.162.07:58:13.30#ibcon#about to read 6, iclass 20, count 0 2006.162.07:58:13.30#ibcon#read 6, iclass 20, count 0 2006.162.07:58:13.30#ibcon#end of sib2, iclass 20, count 0 2006.162.07:58:13.30#ibcon#*mode == 0, iclass 20, count 0 2006.162.07:58:13.30#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.07:58:13.30#ibcon#[27=USB\r\n] 2006.162.07:58:13.30#ibcon#*before write, iclass 20, count 0 2006.162.07:58:13.30#ibcon#enter sib2, iclass 20, count 0 2006.162.07:58:13.30#ibcon#flushed, iclass 20, count 0 2006.162.07:58:13.30#ibcon#about to write, iclass 20, count 0 2006.162.07:58:13.30#ibcon#wrote, iclass 20, count 0 2006.162.07:58:13.30#ibcon#about to read 3, iclass 20, count 0 2006.162.07:58:13.33#ibcon#read 3, iclass 20, count 0 2006.162.07:58:13.33#ibcon#about to read 4, iclass 20, count 0 2006.162.07:58:13.33#ibcon#read 4, iclass 20, count 0 2006.162.07:58:13.33#ibcon#about to read 5, iclass 20, count 0 2006.162.07:58:13.33#ibcon#read 5, iclass 20, count 0 2006.162.07:58:13.33#ibcon#about to read 6, iclass 20, count 0 2006.162.07:58:13.33#ibcon#read 6, iclass 20, count 0 2006.162.07:58:13.33#ibcon#end of sib2, iclass 20, count 0 2006.162.07:58:13.33#ibcon#*after write, iclass 20, count 0 2006.162.07:58:13.33#ibcon#*before return 0, iclass 20, count 0 2006.162.07:58:13.33#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:58:13.33#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.162.07:58:13.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.07:58:13.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.07:58:13.33$vc4f8/vblo=6,752.99 2006.162.07:58:13.33#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.162.07:58:13.33#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.162.07:58:13.33#ibcon#ireg 17 cls_cnt 0 2006.162.07:58:13.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:58:13.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:58:13.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:58:13.33#ibcon#enter wrdev, iclass 22, count 0 2006.162.07:58:13.33#ibcon#first serial, iclass 22, count 0 2006.162.07:58:13.33#ibcon#enter sib2, iclass 22, count 0 2006.162.07:58:13.33#ibcon#flushed, iclass 22, count 0 2006.162.07:58:13.33#ibcon#about to write, iclass 22, count 0 2006.162.07:58:13.33#ibcon#wrote, iclass 22, count 0 2006.162.07:58:13.33#ibcon#about to read 3, iclass 22, count 0 2006.162.07:58:13.35#ibcon#read 3, iclass 22, count 0 2006.162.07:58:13.35#ibcon#about to read 4, iclass 22, count 0 2006.162.07:58:13.35#ibcon#read 4, iclass 22, count 0 2006.162.07:58:13.35#ibcon#about to read 5, iclass 22, count 0 2006.162.07:58:13.35#ibcon#read 5, iclass 22, count 0 2006.162.07:58:13.35#ibcon#about to read 6, iclass 22, count 0 2006.162.07:58:13.35#ibcon#read 6, iclass 22, count 0 2006.162.07:58:13.35#ibcon#end of sib2, iclass 22, count 0 2006.162.07:58:13.35#ibcon#*mode == 0, iclass 22, count 0 2006.162.07:58:13.35#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.07:58:13.35#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.07:58:13.35#ibcon#*before write, iclass 22, count 0 2006.162.07:58:13.35#ibcon#enter sib2, iclass 22, count 0 2006.162.07:58:13.35#ibcon#flushed, iclass 22, count 0 2006.162.07:58:13.35#ibcon#about to write, iclass 22, count 0 2006.162.07:58:13.35#ibcon#wrote, iclass 22, count 0 2006.162.07:58:13.35#ibcon#about to read 3, iclass 22, count 0 2006.162.07:58:13.39#ibcon#read 3, iclass 22, count 0 2006.162.07:58:13.39#ibcon#about to read 4, iclass 22, count 0 2006.162.07:58:13.39#ibcon#read 4, iclass 22, count 0 2006.162.07:58:13.39#ibcon#about to read 5, iclass 22, count 0 2006.162.07:58:13.39#ibcon#read 5, iclass 22, count 0 2006.162.07:58:13.39#ibcon#about to read 6, iclass 22, count 0 2006.162.07:58:13.39#ibcon#read 6, iclass 22, count 0 2006.162.07:58:13.39#ibcon#end of sib2, iclass 22, count 0 2006.162.07:58:13.39#ibcon#*after write, iclass 22, count 0 2006.162.07:58:13.39#ibcon#*before return 0, iclass 22, count 0 2006.162.07:58:13.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:58:13.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.162.07:58:13.39#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.07:58:13.39#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.07:58:13.39$vc4f8/vb=6,4 2006.162.07:58:13.39#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.162.07:58:13.39#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.162.07:58:13.39#ibcon#ireg 11 cls_cnt 2 2006.162.07:58:13.39#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:58:13.45#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:58:13.45#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:58:13.45#ibcon#enter wrdev, iclass 24, count 2 2006.162.07:58:13.45#ibcon#first serial, iclass 24, count 2 2006.162.07:58:13.45#ibcon#enter sib2, iclass 24, count 2 2006.162.07:58:13.45#ibcon#flushed, iclass 24, count 2 2006.162.07:58:13.45#ibcon#about to write, iclass 24, count 2 2006.162.07:58:13.45#ibcon#wrote, iclass 24, count 2 2006.162.07:58:13.45#ibcon#about to read 3, iclass 24, count 2 2006.162.07:58:13.47#ibcon#read 3, iclass 24, count 2 2006.162.07:58:13.47#ibcon#about to read 4, iclass 24, count 2 2006.162.07:58:13.47#ibcon#read 4, iclass 24, count 2 2006.162.07:58:13.47#ibcon#about to read 5, iclass 24, count 2 2006.162.07:58:13.47#ibcon#read 5, iclass 24, count 2 2006.162.07:58:13.47#ibcon#about to read 6, iclass 24, count 2 2006.162.07:58:13.47#ibcon#read 6, iclass 24, count 2 2006.162.07:58:13.47#ibcon#end of sib2, iclass 24, count 2 2006.162.07:58:13.47#ibcon#*mode == 0, iclass 24, count 2 2006.162.07:58:13.47#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.162.07:58:13.47#ibcon#[27=AT06-04\r\n] 2006.162.07:58:13.47#ibcon#*before write, iclass 24, count 2 2006.162.07:58:13.47#ibcon#enter sib2, iclass 24, count 2 2006.162.07:58:13.47#ibcon#flushed, iclass 24, count 2 2006.162.07:58:13.47#ibcon#about to write, iclass 24, count 2 2006.162.07:58:13.47#ibcon#wrote, iclass 24, count 2 2006.162.07:58:13.47#ibcon#about to read 3, iclass 24, count 2 2006.162.07:58:13.50#ibcon#read 3, iclass 24, count 2 2006.162.07:58:13.50#ibcon#about to read 4, iclass 24, count 2 2006.162.07:58:13.50#ibcon#read 4, iclass 24, count 2 2006.162.07:58:13.50#ibcon#about to read 5, iclass 24, count 2 2006.162.07:58:13.50#ibcon#read 5, iclass 24, count 2 2006.162.07:58:13.50#ibcon#about to read 6, iclass 24, count 2 2006.162.07:58:13.50#ibcon#read 6, iclass 24, count 2 2006.162.07:58:13.50#ibcon#end of sib2, iclass 24, count 2 2006.162.07:58:13.50#ibcon#*after write, iclass 24, count 2 2006.162.07:58:13.50#ibcon#*before return 0, iclass 24, count 2 2006.162.07:58:13.50#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:58:13.50#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.162.07:58:13.50#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.162.07:58:13.50#ibcon#ireg 7 cls_cnt 0 2006.162.07:58:13.50#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:58:13.62#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:58:13.62#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:58:13.62#ibcon#enter wrdev, iclass 24, count 0 2006.162.07:58:13.62#ibcon#first serial, iclass 24, count 0 2006.162.07:58:13.62#ibcon#enter sib2, iclass 24, count 0 2006.162.07:58:13.62#ibcon#flushed, iclass 24, count 0 2006.162.07:58:13.62#ibcon#about to write, iclass 24, count 0 2006.162.07:58:13.62#ibcon#wrote, iclass 24, count 0 2006.162.07:58:13.62#ibcon#about to read 3, iclass 24, count 0 2006.162.07:58:13.64#ibcon#read 3, iclass 24, count 0 2006.162.07:58:13.64#ibcon#about to read 4, iclass 24, count 0 2006.162.07:58:13.64#ibcon#read 4, iclass 24, count 0 2006.162.07:58:13.64#ibcon#about to read 5, iclass 24, count 0 2006.162.07:58:13.64#ibcon#read 5, iclass 24, count 0 2006.162.07:58:13.64#ibcon#about to read 6, iclass 24, count 0 2006.162.07:58:13.64#ibcon#read 6, iclass 24, count 0 2006.162.07:58:13.64#ibcon#end of sib2, iclass 24, count 0 2006.162.07:58:13.64#ibcon#*mode == 0, iclass 24, count 0 2006.162.07:58:13.64#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.07:58:13.64#ibcon#[27=USB\r\n] 2006.162.07:58:13.64#ibcon#*before write, iclass 24, count 0 2006.162.07:58:13.64#ibcon#enter sib2, iclass 24, count 0 2006.162.07:58:13.64#ibcon#flushed, iclass 24, count 0 2006.162.07:58:13.64#ibcon#about to write, iclass 24, count 0 2006.162.07:58:13.64#ibcon#wrote, iclass 24, count 0 2006.162.07:58:13.64#ibcon#about to read 3, iclass 24, count 0 2006.162.07:58:13.67#ibcon#read 3, iclass 24, count 0 2006.162.07:58:13.67#ibcon#about to read 4, iclass 24, count 0 2006.162.07:58:13.67#ibcon#read 4, iclass 24, count 0 2006.162.07:58:13.67#ibcon#about to read 5, iclass 24, count 0 2006.162.07:58:13.67#ibcon#read 5, iclass 24, count 0 2006.162.07:58:13.67#ibcon#about to read 6, iclass 24, count 0 2006.162.07:58:13.67#ibcon#read 6, iclass 24, count 0 2006.162.07:58:13.67#ibcon#end of sib2, iclass 24, count 0 2006.162.07:58:13.67#ibcon#*after write, iclass 24, count 0 2006.162.07:58:13.67#ibcon#*before return 0, iclass 24, count 0 2006.162.07:58:13.67#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:58:13.67#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.162.07:58:13.67#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.07:58:13.67#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.07:58:13.67$vc4f8/vabw=wide 2006.162.07:58:13.67#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.162.07:58:13.67#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.162.07:58:13.67#ibcon#ireg 8 cls_cnt 0 2006.162.07:58:13.67#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:58:13.67#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:58:13.67#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:58:13.67#ibcon#enter wrdev, iclass 26, count 0 2006.162.07:58:13.67#ibcon#first serial, iclass 26, count 0 2006.162.07:58:13.67#ibcon#enter sib2, iclass 26, count 0 2006.162.07:58:13.67#ibcon#flushed, iclass 26, count 0 2006.162.07:58:13.67#ibcon#about to write, iclass 26, count 0 2006.162.07:58:13.67#ibcon#wrote, iclass 26, count 0 2006.162.07:58:13.67#ibcon#about to read 3, iclass 26, count 0 2006.162.07:58:13.69#ibcon#read 3, iclass 26, count 0 2006.162.07:58:13.69#ibcon#about to read 4, iclass 26, count 0 2006.162.07:58:13.69#ibcon#read 4, iclass 26, count 0 2006.162.07:58:13.69#ibcon#about to read 5, iclass 26, count 0 2006.162.07:58:13.69#ibcon#read 5, iclass 26, count 0 2006.162.07:58:13.69#ibcon#about to read 6, iclass 26, count 0 2006.162.07:58:13.69#ibcon#read 6, iclass 26, count 0 2006.162.07:58:13.69#ibcon#end of sib2, iclass 26, count 0 2006.162.07:58:13.69#ibcon#*mode == 0, iclass 26, count 0 2006.162.07:58:13.69#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.162.07:58:13.69#ibcon#[25=BW32\r\n] 2006.162.07:58:13.69#ibcon#*before write, iclass 26, count 0 2006.162.07:58:13.69#ibcon#enter sib2, iclass 26, count 0 2006.162.07:58:13.69#ibcon#flushed, iclass 26, count 0 2006.162.07:58:13.69#ibcon#about to write, iclass 26, count 0 2006.162.07:58:13.69#ibcon#wrote, iclass 26, count 0 2006.162.07:58:13.69#ibcon#about to read 3, iclass 26, count 0 2006.162.07:58:13.72#ibcon#read 3, iclass 26, count 0 2006.162.07:58:13.72#ibcon#about to read 4, iclass 26, count 0 2006.162.07:58:13.72#ibcon#read 4, iclass 26, count 0 2006.162.07:58:13.72#ibcon#about to read 5, iclass 26, count 0 2006.162.07:58:13.72#ibcon#read 5, iclass 26, count 0 2006.162.07:58:13.72#ibcon#about to read 6, iclass 26, count 0 2006.162.07:58:13.72#ibcon#read 6, iclass 26, count 0 2006.162.07:58:13.72#ibcon#end of sib2, iclass 26, count 0 2006.162.07:58:13.72#ibcon#*after write, iclass 26, count 0 2006.162.07:58:13.72#ibcon#*before return 0, iclass 26, count 0 2006.162.07:58:13.72#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:58:13.72#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.162.07:58:13.72#ibcon#about to clear, iclass 26 cls_cnt 0 2006.162.07:58:13.72#ibcon#cleared, iclass 26 cls_cnt 0 2006.162.07:58:13.72$vc4f8/vbbw=wide 2006.162.07:58:13.72#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.162.07:58:13.72#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.162.07:58:13.72#ibcon#ireg 8 cls_cnt 0 2006.162.07:58:13.72#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:58:13.79#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:58:13.79#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:58:13.79#ibcon#enter wrdev, iclass 28, count 0 2006.162.07:58:13.79#ibcon#first serial, iclass 28, count 0 2006.162.07:58:13.79#ibcon#enter sib2, iclass 28, count 0 2006.162.07:58:13.79#ibcon#flushed, iclass 28, count 0 2006.162.07:58:13.79#ibcon#about to write, iclass 28, count 0 2006.162.07:58:13.79#ibcon#wrote, iclass 28, count 0 2006.162.07:58:13.79#ibcon#about to read 3, iclass 28, count 0 2006.162.07:58:13.81#ibcon#read 3, iclass 28, count 0 2006.162.07:58:13.81#ibcon#about to read 4, iclass 28, count 0 2006.162.07:58:13.81#ibcon#read 4, iclass 28, count 0 2006.162.07:58:13.81#ibcon#about to read 5, iclass 28, count 0 2006.162.07:58:13.81#ibcon#read 5, iclass 28, count 0 2006.162.07:58:13.81#ibcon#about to read 6, iclass 28, count 0 2006.162.07:58:13.81#ibcon#read 6, iclass 28, count 0 2006.162.07:58:13.81#ibcon#end of sib2, iclass 28, count 0 2006.162.07:58:13.81#ibcon#*mode == 0, iclass 28, count 0 2006.162.07:58:13.81#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.162.07:58:13.81#ibcon#[27=BW32\r\n] 2006.162.07:58:13.81#ibcon#*before write, iclass 28, count 0 2006.162.07:58:13.81#ibcon#enter sib2, iclass 28, count 0 2006.162.07:58:13.81#ibcon#flushed, iclass 28, count 0 2006.162.07:58:13.81#ibcon#about to write, iclass 28, count 0 2006.162.07:58:13.81#ibcon#wrote, iclass 28, count 0 2006.162.07:58:13.81#ibcon#about to read 3, iclass 28, count 0 2006.162.07:58:13.84#ibcon#read 3, iclass 28, count 0 2006.162.07:58:13.84#ibcon#about to read 4, iclass 28, count 0 2006.162.07:58:13.84#ibcon#read 4, iclass 28, count 0 2006.162.07:58:13.84#ibcon#about to read 5, iclass 28, count 0 2006.162.07:58:13.84#ibcon#read 5, iclass 28, count 0 2006.162.07:58:13.84#ibcon#about to read 6, iclass 28, count 0 2006.162.07:58:13.84#ibcon#read 6, iclass 28, count 0 2006.162.07:58:13.84#ibcon#end of sib2, iclass 28, count 0 2006.162.07:58:13.84#ibcon#*after write, iclass 28, count 0 2006.162.07:58:13.84#ibcon#*before return 0, iclass 28, count 0 2006.162.07:58:13.84#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:58:13.84#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.162.07:58:13.84#ibcon#about to clear, iclass 28 cls_cnt 0 2006.162.07:58:13.84#ibcon#cleared, iclass 28 cls_cnt 0 2006.162.07:58:13.84$4f8m12a/ifd4f 2006.162.07:58:13.84$ifd4f/lo= 2006.162.07:58:13.84$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.07:58:13.84$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.07:58:13.84$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.07:58:13.84$ifd4f/patch= 2006.162.07:58:13.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.07:58:13.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.07:58:13.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.07:58:13.85$4f8m12a/"form=m,16.000,1:2 2006.162.07:58:13.85$4f8m12a/"tpicd 2006.162.07:58:13.85$4f8m12a/echo=off 2006.162.07:58:13.85$4f8m12a/xlog=off 2006.162.07:58:13.85:!2006.162.07:58:50 2006.162.07:58:32.13#trakl#Source acquired 2006.162.07:58:33.13#flagr#flagr/antenna,acquired 2006.162.07:58:50.01:preob 2006.162.07:58:51.13/onsource/TRACKING 2006.162.07:58:51.13:!2006.162.07:59:00 2006.162.07:59:00.00:data_valid=on 2006.162.07:59:00.00:midob 2006.162.07:59:00.13/onsource/TRACKING 2006.162.07:59:00.13/wx/17.85,1007.0,100 2006.162.07:59:00.20/cable/+6.5360E-03 2006.162.07:59:01.29/va/01,08,usb,yes,39,41 2006.162.07:59:01.29/va/02,07,usb,yes,39,41 2006.162.07:59:01.29/va/03,06,usb,yes,41,41 2006.162.07:59:01.29/va/04,07,usb,yes,40,43 2006.162.07:59:01.29/va/05,07,usb,yes,43,46 2006.162.07:59:01.29/va/06,06,usb,yes,43,42 2006.162.07:59:01.29/va/07,06,usb,yes,43,43 2006.162.07:59:01.29/va/08,07,usb,yes,41,40 2006.162.07:59:01.52/valo/01,532.99,yes,locked 2006.162.07:59:01.52/valo/02,572.99,yes,locked 2006.162.07:59:01.52/valo/03,672.99,yes,locked 2006.162.07:59:01.52/valo/04,832.99,yes,locked 2006.162.07:59:01.52/valo/05,652.99,yes,locked 2006.162.07:59:01.52/valo/06,772.99,yes,locked 2006.162.07:59:01.52/valo/07,832.99,yes,locked 2006.162.07:59:01.52/valo/08,852.99,yes,locked 2006.162.07:59:02.61/vb/01,04,usb,yes,30,29 2006.162.07:59:02.61/vb/02,04,usb,yes,32,34 2006.162.07:59:02.61/vb/03,04,usb,yes,28,32 2006.162.07:59:02.61/vb/04,04,usb,yes,29,30 2006.162.07:59:02.61/vb/05,04,usb,yes,28,32 2006.162.07:59:02.61/vb/06,04,usb,yes,29,32 2006.162.07:59:02.61/vb/07,04,usb,yes,31,31 2006.162.07:59:02.61/vb/08,04,usb,yes,28,32 2006.162.07:59:02.84/vblo/01,632.99,yes,locked 2006.162.07:59:02.84/vblo/02,640.99,yes,locked 2006.162.07:59:02.84/vblo/03,656.99,yes,locked 2006.162.07:59:02.84/vblo/04,712.99,yes,locked 2006.162.07:59:02.84/vblo/05,744.99,yes,locked 2006.162.07:59:02.84/vblo/06,752.99,yes,locked 2006.162.07:59:02.84/vblo/07,734.99,yes,locked 2006.162.07:59:02.84/vblo/08,744.99,yes,locked 2006.162.07:59:02.99/vabw/8 2006.162.07:59:03.14/vbbw/8 2006.162.07:59:03.28/xfe/off,on,15.0 2006.162.07:59:03.67/ifatt/23,28,28,28 2006.162.07:59:04.08/fmout-gps/S +4.48E-07 2006.162.07:59:04.13:!2006.162.08:00:00 2006.162.08:00:00.01:data_valid=off 2006.162.08:00:00.02:postob 2006.162.08:00:00.17/cable/+6.5355E-03 2006.162.08:00:00.18/wx/17.87,1007.0,100 2006.162.08:00:01.08/fmout-gps/S +4.49E-07 2006.162.08:00:01.09:scan_name=162-0801,k06162,60 2006.162.08:00:01.09:source=0748+126,075052.05,123104.8,2000.0,ccw 2006.162.08:00:02.14#flagr#flagr/antenna,new-source 2006.162.08:00:02.15:checkk5 2006.162.08:00:02.54/chk_autoobs//k5ts1/ autoobs is running! 2006.162.08:00:02.92/chk_autoobs//k5ts2/ autoobs is running! 2006.162.08:00:03.33/chk_autoobs//k5ts3/ autoobs is running! 2006.162.08:00:03.79/chk_autoobs//k5ts4/ autoobs is running! 2006.162.08:00:04.21/chk_obsdata//k5ts1/T1620759??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.162.08:00:04.61/chk_obsdata//k5ts2/T1620759??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.162.08:00:05.30/chk_obsdata//k5ts3/T1620759??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.162.08:00:05.71/chk_obsdata//k5ts4/T1620759??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.162.08:00:06.79/k5log//k5ts1_log_newline 2006.162.08:00:07.59/k5log//k5ts2_log_newline 2006.162.08:00:08.32/k5log//k5ts3_log_newline 2006.162.08:00:09.16/k5log//k5ts4_log_newline 2006.162.08:00:09.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.08:00:09.18:4f8m12a=2 2006.162.08:00:09.18$4f8m12a/echo=on 2006.162.08:00:09.18$4f8m12a/pcalon 2006.162.08:00:09.18$pcalon/"no phase cal control is implemented here 2006.162.08:00:09.18$4f8m12a/"tpicd=stop 2006.162.08:00:09.18$4f8m12a/vc4f8 2006.162.08:00:09.18$vc4f8/valo=1,532.99 2006.162.08:00:09.22#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.162.08:00:09.22#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.162.08:00:09.22#ibcon#ireg 17 cls_cnt 0 2006.162.08:00:09.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:00:09.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:00:09.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:00:09.22#ibcon#enter wrdev, iclass 39, count 0 2006.162.08:00:09.22#ibcon#first serial, iclass 39, count 0 2006.162.08:00:09.22#ibcon#enter sib2, iclass 39, count 0 2006.162.08:00:09.22#ibcon#flushed, iclass 39, count 0 2006.162.08:00:09.22#ibcon#about to write, iclass 39, count 0 2006.162.08:00:09.23#ibcon#wrote, iclass 39, count 0 2006.162.08:00:09.23#ibcon#about to read 3, iclass 39, count 0 2006.162.08:00:09.24#ibcon#read 3, iclass 39, count 0 2006.162.08:00:09.24#ibcon#about to read 4, iclass 39, count 0 2006.162.08:00:09.24#ibcon#read 4, iclass 39, count 0 2006.162.08:00:09.24#ibcon#about to read 5, iclass 39, count 0 2006.162.08:00:09.24#ibcon#read 5, iclass 39, count 0 2006.162.08:00:09.24#ibcon#about to read 6, iclass 39, count 0 2006.162.08:00:09.24#ibcon#read 6, iclass 39, count 0 2006.162.08:00:09.24#ibcon#end of sib2, iclass 39, count 0 2006.162.08:00:09.24#ibcon#*mode == 0, iclass 39, count 0 2006.162.08:00:09.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.162.08:00:09.24#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.08:00:09.24#ibcon#*before write, iclass 39, count 0 2006.162.08:00:09.24#ibcon#enter sib2, iclass 39, count 0 2006.162.08:00:09.24#ibcon#flushed, iclass 39, count 0 2006.162.08:00:09.24#ibcon#about to write, iclass 39, count 0 2006.162.08:00:09.24#ibcon#wrote, iclass 39, count 0 2006.162.08:00:09.24#ibcon#about to read 3, iclass 39, count 0 2006.162.08:00:09.29#ibcon#read 3, iclass 39, count 0 2006.162.08:00:09.29#ibcon#about to read 4, iclass 39, count 0 2006.162.08:00:09.29#ibcon#read 4, iclass 39, count 0 2006.162.08:00:09.29#ibcon#about to read 5, iclass 39, count 0 2006.162.08:00:09.29#ibcon#read 5, iclass 39, count 0 2006.162.08:00:09.29#ibcon#about to read 6, iclass 39, count 0 2006.162.08:00:09.29#ibcon#read 6, iclass 39, count 0 2006.162.08:00:09.29#ibcon#end of sib2, iclass 39, count 0 2006.162.08:00:09.29#ibcon#*after write, iclass 39, count 0 2006.162.08:00:09.29#ibcon#*before return 0, iclass 39, count 0 2006.162.08:00:09.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:00:09.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:00:09.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.162.08:00:09.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.162.08:00:09.29$vc4f8/va=1,8 2006.162.08:00:09.29#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.162.08:00:09.29#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.162.08:00:09.29#ibcon#ireg 11 cls_cnt 2 2006.162.08:00:09.29#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:00:09.29#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:00:09.29#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:00:09.29#ibcon#enter wrdev, iclass 3, count 2 2006.162.08:00:09.29#ibcon#first serial, iclass 3, count 2 2006.162.08:00:09.29#ibcon#enter sib2, iclass 3, count 2 2006.162.08:00:09.29#ibcon#flushed, iclass 3, count 2 2006.162.08:00:09.29#ibcon#about to write, iclass 3, count 2 2006.162.08:00:09.29#ibcon#wrote, iclass 3, count 2 2006.162.08:00:09.29#ibcon#about to read 3, iclass 3, count 2 2006.162.08:00:09.31#ibcon#read 3, iclass 3, count 2 2006.162.08:00:09.31#ibcon#about to read 4, iclass 3, count 2 2006.162.08:00:09.31#ibcon#read 4, iclass 3, count 2 2006.162.08:00:09.31#ibcon#about to read 5, iclass 3, count 2 2006.162.08:00:09.31#ibcon#read 5, iclass 3, count 2 2006.162.08:00:09.31#ibcon#about to read 6, iclass 3, count 2 2006.162.08:00:09.31#ibcon#read 6, iclass 3, count 2 2006.162.08:00:09.31#ibcon#end of sib2, iclass 3, count 2 2006.162.08:00:09.31#ibcon#*mode == 0, iclass 3, count 2 2006.162.08:00:09.31#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.162.08:00:09.31#ibcon#[25=AT01-08\r\n] 2006.162.08:00:09.31#ibcon#*before write, iclass 3, count 2 2006.162.08:00:09.31#ibcon#enter sib2, iclass 3, count 2 2006.162.08:00:09.31#ibcon#flushed, iclass 3, count 2 2006.162.08:00:09.31#ibcon#about to write, iclass 3, count 2 2006.162.08:00:09.31#ibcon#wrote, iclass 3, count 2 2006.162.08:00:09.31#ibcon#about to read 3, iclass 3, count 2 2006.162.08:00:09.34#ibcon#read 3, iclass 3, count 2 2006.162.08:00:09.34#ibcon#about to read 4, iclass 3, count 2 2006.162.08:00:09.34#ibcon#read 4, iclass 3, count 2 2006.162.08:00:09.34#ibcon#about to read 5, iclass 3, count 2 2006.162.08:00:09.34#ibcon#read 5, iclass 3, count 2 2006.162.08:00:09.34#ibcon#about to read 6, iclass 3, count 2 2006.162.08:00:09.34#ibcon#read 6, iclass 3, count 2 2006.162.08:00:09.34#ibcon#end of sib2, iclass 3, count 2 2006.162.08:00:09.34#ibcon#*after write, iclass 3, count 2 2006.162.08:00:09.34#ibcon#*before return 0, iclass 3, count 2 2006.162.08:00:09.34#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:00:09.34#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:00:09.34#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.162.08:00:09.34#ibcon#ireg 7 cls_cnt 0 2006.162.08:00:09.34#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:00:09.46#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:00:09.46#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:00:09.46#ibcon#enter wrdev, iclass 3, count 0 2006.162.08:00:09.46#ibcon#first serial, iclass 3, count 0 2006.162.08:00:09.46#ibcon#enter sib2, iclass 3, count 0 2006.162.08:00:09.46#ibcon#flushed, iclass 3, count 0 2006.162.08:00:09.46#ibcon#about to write, iclass 3, count 0 2006.162.08:00:09.46#ibcon#wrote, iclass 3, count 0 2006.162.08:00:09.46#ibcon#about to read 3, iclass 3, count 0 2006.162.08:00:09.48#ibcon#read 3, iclass 3, count 0 2006.162.08:00:09.48#ibcon#about to read 4, iclass 3, count 0 2006.162.08:00:09.48#ibcon#read 4, iclass 3, count 0 2006.162.08:00:09.48#ibcon#about to read 5, iclass 3, count 0 2006.162.08:00:09.48#ibcon#read 5, iclass 3, count 0 2006.162.08:00:09.48#ibcon#about to read 6, iclass 3, count 0 2006.162.08:00:09.48#ibcon#read 6, iclass 3, count 0 2006.162.08:00:09.48#ibcon#end of sib2, iclass 3, count 0 2006.162.08:00:09.48#ibcon#*mode == 0, iclass 3, count 0 2006.162.08:00:09.48#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.162.08:00:09.48#ibcon#[25=USB\r\n] 2006.162.08:00:09.48#ibcon#*before write, iclass 3, count 0 2006.162.08:00:09.48#ibcon#enter sib2, iclass 3, count 0 2006.162.08:00:09.48#ibcon#flushed, iclass 3, count 0 2006.162.08:00:09.48#ibcon#about to write, iclass 3, count 0 2006.162.08:00:09.48#ibcon#wrote, iclass 3, count 0 2006.162.08:00:09.48#ibcon#about to read 3, iclass 3, count 0 2006.162.08:00:09.51#ibcon#read 3, iclass 3, count 0 2006.162.08:00:09.51#ibcon#about to read 4, iclass 3, count 0 2006.162.08:00:09.51#ibcon#read 4, iclass 3, count 0 2006.162.08:00:09.51#ibcon#about to read 5, iclass 3, count 0 2006.162.08:00:09.51#ibcon#read 5, iclass 3, count 0 2006.162.08:00:09.51#ibcon#about to read 6, iclass 3, count 0 2006.162.08:00:09.51#ibcon#read 6, iclass 3, count 0 2006.162.08:00:09.51#ibcon#end of sib2, iclass 3, count 0 2006.162.08:00:09.51#ibcon#*after write, iclass 3, count 0 2006.162.08:00:09.51#ibcon#*before return 0, iclass 3, count 0 2006.162.08:00:09.51#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:00:09.51#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:00:09.51#ibcon#about to clear, iclass 3 cls_cnt 0 2006.162.08:00:09.51#ibcon#cleared, iclass 3 cls_cnt 0 2006.162.08:00:09.51$vc4f8/valo=2,572.99 2006.162.08:00:09.51#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.162.08:00:09.51#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.162.08:00:09.51#ibcon#ireg 17 cls_cnt 0 2006.162.08:00:09.51#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:00:09.51#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:00:09.51#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:00:09.51#ibcon#enter wrdev, iclass 5, count 0 2006.162.08:00:09.51#ibcon#first serial, iclass 5, count 0 2006.162.08:00:09.51#ibcon#enter sib2, iclass 5, count 0 2006.162.08:00:09.51#ibcon#flushed, iclass 5, count 0 2006.162.08:00:09.51#ibcon#about to write, iclass 5, count 0 2006.162.08:00:09.51#ibcon#wrote, iclass 5, count 0 2006.162.08:00:09.51#ibcon#about to read 3, iclass 5, count 0 2006.162.08:00:09.53#ibcon#read 3, iclass 5, count 0 2006.162.08:00:09.53#ibcon#about to read 4, iclass 5, count 0 2006.162.08:00:09.53#ibcon#read 4, iclass 5, count 0 2006.162.08:00:09.53#ibcon#about to read 5, iclass 5, count 0 2006.162.08:00:09.53#ibcon#read 5, iclass 5, count 0 2006.162.08:00:09.53#ibcon#about to read 6, iclass 5, count 0 2006.162.08:00:09.53#ibcon#read 6, iclass 5, count 0 2006.162.08:00:09.53#ibcon#end of sib2, iclass 5, count 0 2006.162.08:00:09.53#ibcon#*mode == 0, iclass 5, count 0 2006.162.08:00:09.53#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.162.08:00:09.53#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.08:00:09.53#ibcon#*before write, iclass 5, count 0 2006.162.08:00:09.53#ibcon#enter sib2, iclass 5, count 0 2006.162.08:00:09.53#ibcon#flushed, iclass 5, count 0 2006.162.08:00:09.53#ibcon#about to write, iclass 5, count 0 2006.162.08:00:09.53#ibcon#wrote, iclass 5, count 0 2006.162.08:00:09.53#ibcon#about to read 3, iclass 5, count 0 2006.162.08:00:09.57#ibcon#read 3, iclass 5, count 0 2006.162.08:00:09.57#ibcon#about to read 4, iclass 5, count 0 2006.162.08:00:09.57#ibcon#read 4, iclass 5, count 0 2006.162.08:00:09.57#ibcon#about to read 5, iclass 5, count 0 2006.162.08:00:09.57#ibcon#read 5, iclass 5, count 0 2006.162.08:00:09.57#ibcon#about to read 6, iclass 5, count 0 2006.162.08:00:09.57#ibcon#read 6, iclass 5, count 0 2006.162.08:00:09.57#ibcon#end of sib2, iclass 5, count 0 2006.162.08:00:09.57#ibcon#*after write, iclass 5, count 0 2006.162.08:00:09.57#ibcon#*before return 0, iclass 5, count 0 2006.162.08:00:09.57#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:00:09.57#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:00:09.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.162.08:00:09.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.162.08:00:09.57$vc4f8/va=2,7 2006.162.08:00:09.57#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.162.08:00:09.57#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.162.08:00:09.57#ibcon#ireg 11 cls_cnt 2 2006.162.08:00:09.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:00:09.63#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:00:09.63#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:00:09.63#ibcon#enter wrdev, iclass 7, count 2 2006.162.08:00:09.63#ibcon#first serial, iclass 7, count 2 2006.162.08:00:09.63#ibcon#enter sib2, iclass 7, count 2 2006.162.08:00:09.63#ibcon#flushed, iclass 7, count 2 2006.162.08:00:09.63#ibcon#about to write, iclass 7, count 2 2006.162.08:00:09.63#ibcon#wrote, iclass 7, count 2 2006.162.08:00:09.63#ibcon#about to read 3, iclass 7, count 2 2006.162.08:00:09.66#ibcon#read 3, iclass 7, count 2 2006.162.08:00:09.66#ibcon#about to read 4, iclass 7, count 2 2006.162.08:00:09.66#ibcon#read 4, iclass 7, count 2 2006.162.08:00:09.66#ibcon#about to read 5, iclass 7, count 2 2006.162.08:00:09.66#ibcon#read 5, iclass 7, count 2 2006.162.08:00:09.66#ibcon#about to read 6, iclass 7, count 2 2006.162.08:00:09.66#ibcon#read 6, iclass 7, count 2 2006.162.08:00:09.66#ibcon#end of sib2, iclass 7, count 2 2006.162.08:00:09.66#ibcon#*mode == 0, iclass 7, count 2 2006.162.08:00:09.66#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.162.08:00:09.66#ibcon#[25=AT02-07\r\n] 2006.162.08:00:09.66#ibcon#*before write, iclass 7, count 2 2006.162.08:00:09.66#ibcon#enter sib2, iclass 7, count 2 2006.162.08:00:09.66#ibcon#flushed, iclass 7, count 2 2006.162.08:00:09.66#ibcon#about to write, iclass 7, count 2 2006.162.08:00:09.66#ibcon#wrote, iclass 7, count 2 2006.162.08:00:09.66#ibcon#about to read 3, iclass 7, count 2 2006.162.08:00:09.69#ibcon#read 3, iclass 7, count 2 2006.162.08:00:09.69#ibcon#about to read 4, iclass 7, count 2 2006.162.08:00:09.69#ibcon#read 4, iclass 7, count 2 2006.162.08:00:09.69#ibcon#about to read 5, iclass 7, count 2 2006.162.08:00:09.69#ibcon#read 5, iclass 7, count 2 2006.162.08:00:09.69#ibcon#about to read 6, iclass 7, count 2 2006.162.08:00:09.69#ibcon#read 6, iclass 7, count 2 2006.162.08:00:09.69#ibcon#end of sib2, iclass 7, count 2 2006.162.08:00:09.69#ibcon#*after write, iclass 7, count 2 2006.162.08:00:09.69#ibcon#*before return 0, iclass 7, count 2 2006.162.08:00:09.69#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:00:09.69#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:00:09.69#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.162.08:00:09.69#ibcon#ireg 7 cls_cnt 0 2006.162.08:00:09.69#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:00:09.81#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:00:09.81#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:00:09.81#ibcon#enter wrdev, iclass 7, count 0 2006.162.08:00:09.81#ibcon#first serial, iclass 7, count 0 2006.162.08:00:09.81#ibcon#enter sib2, iclass 7, count 0 2006.162.08:00:09.81#ibcon#flushed, iclass 7, count 0 2006.162.08:00:09.81#ibcon#about to write, iclass 7, count 0 2006.162.08:00:09.81#ibcon#wrote, iclass 7, count 0 2006.162.08:00:09.81#ibcon#about to read 3, iclass 7, count 0 2006.162.08:00:09.83#ibcon#read 3, iclass 7, count 0 2006.162.08:00:09.83#ibcon#about to read 4, iclass 7, count 0 2006.162.08:00:09.83#ibcon#read 4, iclass 7, count 0 2006.162.08:00:09.83#ibcon#about to read 5, iclass 7, count 0 2006.162.08:00:09.83#ibcon#read 5, iclass 7, count 0 2006.162.08:00:09.83#ibcon#about to read 6, iclass 7, count 0 2006.162.08:00:09.83#ibcon#read 6, iclass 7, count 0 2006.162.08:00:09.83#ibcon#end of sib2, iclass 7, count 0 2006.162.08:00:09.83#ibcon#*mode == 0, iclass 7, count 0 2006.162.08:00:09.83#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.162.08:00:09.83#ibcon#[25=USB\r\n] 2006.162.08:00:09.83#ibcon#*before write, iclass 7, count 0 2006.162.08:00:09.83#ibcon#enter sib2, iclass 7, count 0 2006.162.08:00:09.83#ibcon#flushed, iclass 7, count 0 2006.162.08:00:09.83#ibcon#about to write, iclass 7, count 0 2006.162.08:00:09.83#ibcon#wrote, iclass 7, count 0 2006.162.08:00:09.83#ibcon#about to read 3, iclass 7, count 0 2006.162.08:00:09.86#ibcon#read 3, iclass 7, count 0 2006.162.08:00:09.86#ibcon#about to read 4, iclass 7, count 0 2006.162.08:00:09.86#ibcon#read 4, iclass 7, count 0 2006.162.08:00:09.86#ibcon#about to read 5, iclass 7, count 0 2006.162.08:00:09.86#ibcon#read 5, iclass 7, count 0 2006.162.08:00:09.86#ibcon#about to read 6, iclass 7, count 0 2006.162.08:00:09.86#ibcon#read 6, iclass 7, count 0 2006.162.08:00:09.86#ibcon#end of sib2, iclass 7, count 0 2006.162.08:00:09.86#ibcon#*after write, iclass 7, count 0 2006.162.08:00:09.86#ibcon#*before return 0, iclass 7, count 0 2006.162.08:00:09.86#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:00:09.86#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:00:09.86#ibcon#about to clear, iclass 7 cls_cnt 0 2006.162.08:00:09.86#ibcon#cleared, iclass 7 cls_cnt 0 2006.162.08:00:09.86$vc4f8/valo=3,672.99 2006.162.08:00:09.86#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.162.08:00:09.86#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.162.08:00:09.86#ibcon#ireg 17 cls_cnt 0 2006.162.08:00:09.86#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:00:09.86#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:00:09.86#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:00:09.86#ibcon#enter wrdev, iclass 11, count 0 2006.162.08:00:09.86#ibcon#first serial, iclass 11, count 0 2006.162.08:00:09.86#ibcon#enter sib2, iclass 11, count 0 2006.162.08:00:09.86#ibcon#flushed, iclass 11, count 0 2006.162.08:00:09.86#ibcon#about to write, iclass 11, count 0 2006.162.08:00:09.86#ibcon#wrote, iclass 11, count 0 2006.162.08:00:09.86#ibcon#about to read 3, iclass 11, count 0 2006.162.08:00:09.88#ibcon#read 3, iclass 11, count 0 2006.162.08:00:09.88#ibcon#about to read 4, iclass 11, count 0 2006.162.08:00:09.88#ibcon#read 4, iclass 11, count 0 2006.162.08:00:09.88#ibcon#about to read 5, iclass 11, count 0 2006.162.08:00:09.88#ibcon#read 5, iclass 11, count 0 2006.162.08:00:09.88#ibcon#about to read 6, iclass 11, count 0 2006.162.08:00:09.88#ibcon#read 6, iclass 11, count 0 2006.162.08:00:09.88#ibcon#end of sib2, iclass 11, count 0 2006.162.08:00:09.88#ibcon#*mode == 0, iclass 11, count 0 2006.162.08:00:09.88#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.162.08:00:09.88#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.08:00:09.88#ibcon#*before write, iclass 11, count 0 2006.162.08:00:09.88#ibcon#enter sib2, iclass 11, count 0 2006.162.08:00:09.88#ibcon#flushed, iclass 11, count 0 2006.162.08:00:09.88#ibcon#about to write, iclass 11, count 0 2006.162.08:00:09.88#ibcon#wrote, iclass 11, count 0 2006.162.08:00:09.88#ibcon#about to read 3, iclass 11, count 0 2006.162.08:00:09.92#ibcon#read 3, iclass 11, count 0 2006.162.08:00:09.92#ibcon#about to read 4, iclass 11, count 0 2006.162.08:00:09.92#ibcon#read 4, iclass 11, count 0 2006.162.08:00:09.92#ibcon#about to read 5, iclass 11, count 0 2006.162.08:00:09.92#ibcon#read 5, iclass 11, count 0 2006.162.08:00:09.92#ibcon#about to read 6, iclass 11, count 0 2006.162.08:00:09.92#ibcon#read 6, iclass 11, count 0 2006.162.08:00:09.92#ibcon#end of sib2, iclass 11, count 0 2006.162.08:00:09.92#ibcon#*after write, iclass 11, count 0 2006.162.08:00:09.92#ibcon#*before return 0, iclass 11, count 0 2006.162.08:00:09.92#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:00:09.92#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:00:09.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.162.08:00:09.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.162.08:00:09.92$vc4f8/va=3,6 2006.162.08:00:09.92#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.162.08:00:09.92#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.162.08:00:09.92#ibcon#ireg 11 cls_cnt 2 2006.162.08:00:09.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:00:09.98#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:00:09.98#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:00:09.98#ibcon#enter wrdev, iclass 13, count 2 2006.162.08:00:09.98#ibcon#first serial, iclass 13, count 2 2006.162.08:00:09.98#ibcon#enter sib2, iclass 13, count 2 2006.162.08:00:09.98#ibcon#flushed, iclass 13, count 2 2006.162.08:00:09.98#ibcon#about to write, iclass 13, count 2 2006.162.08:00:09.98#ibcon#wrote, iclass 13, count 2 2006.162.08:00:09.98#ibcon#about to read 3, iclass 13, count 2 2006.162.08:00:10.01#ibcon#read 3, iclass 13, count 2 2006.162.08:00:10.01#ibcon#about to read 4, iclass 13, count 2 2006.162.08:00:10.01#ibcon#read 4, iclass 13, count 2 2006.162.08:00:10.01#ibcon#about to read 5, iclass 13, count 2 2006.162.08:00:10.01#ibcon#read 5, iclass 13, count 2 2006.162.08:00:10.01#ibcon#about to read 6, iclass 13, count 2 2006.162.08:00:10.01#ibcon#read 6, iclass 13, count 2 2006.162.08:00:10.01#ibcon#end of sib2, iclass 13, count 2 2006.162.08:00:10.01#ibcon#*mode == 0, iclass 13, count 2 2006.162.08:00:10.01#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.162.08:00:10.01#ibcon#[25=AT03-06\r\n] 2006.162.08:00:10.01#ibcon#*before write, iclass 13, count 2 2006.162.08:00:10.01#ibcon#enter sib2, iclass 13, count 2 2006.162.08:00:10.01#ibcon#flushed, iclass 13, count 2 2006.162.08:00:10.01#ibcon#about to write, iclass 13, count 2 2006.162.08:00:10.01#ibcon#wrote, iclass 13, count 2 2006.162.08:00:10.01#ibcon#about to read 3, iclass 13, count 2 2006.162.08:00:10.04#ibcon#read 3, iclass 13, count 2 2006.162.08:00:10.04#ibcon#about to read 4, iclass 13, count 2 2006.162.08:00:10.04#ibcon#read 4, iclass 13, count 2 2006.162.08:00:10.04#ibcon#about to read 5, iclass 13, count 2 2006.162.08:00:10.04#ibcon#read 5, iclass 13, count 2 2006.162.08:00:10.04#ibcon#about to read 6, iclass 13, count 2 2006.162.08:00:10.04#ibcon#read 6, iclass 13, count 2 2006.162.08:00:10.04#ibcon#end of sib2, iclass 13, count 2 2006.162.08:00:10.04#ibcon#*after write, iclass 13, count 2 2006.162.08:00:10.04#ibcon#*before return 0, iclass 13, count 2 2006.162.08:00:10.04#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:00:10.04#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:00:10.04#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.162.08:00:10.04#ibcon#ireg 7 cls_cnt 0 2006.162.08:00:10.04#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:00:10.16#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:00:10.16#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:00:10.16#ibcon#enter wrdev, iclass 13, count 0 2006.162.08:00:10.16#ibcon#first serial, iclass 13, count 0 2006.162.08:00:10.16#ibcon#enter sib2, iclass 13, count 0 2006.162.08:00:10.16#ibcon#flushed, iclass 13, count 0 2006.162.08:00:10.16#ibcon#about to write, iclass 13, count 0 2006.162.08:00:10.16#ibcon#wrote, iclass 13, count 0 2006.162.08:00:10.16#ibcon#about to read 3, iclass 13, count 0 2006.162.08:00:10.18#ibcon#read 3, iclass 13, count 0 2006.162.08:00:10.18#ibcon#about to read 4, iclass 13, count 0 2006.162.08:00:10.18#ibcon#read 4, iclass 13, count 0 2006.162.08:00:10.18#ibcon#about to read 5, iclass 13, count 0 2006.162.08:00:10.18#ibcon#read 5, iclass 13, count 0 2006.162.08:00:10.18#ibcon#about to read 6, iclass 13, count 0 2006.162.08:00:10.18#ibcon#read 6, iclass 13, count 0 2006.162.08:00:10.18#ibcon#end of sib2, iclass 13, count 0 2006.162.08:00:10.18#ibcon#*mode == 0, iclass 13, count 0 2006.162.08:00:10.18#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.162.08:00:10.18#ibcon#[25=USB\r\n] 2006.162.08:00:10.18#ibcon#*before write, iclass 13, count 0 2006.162.08:00:10.18#ibcon#enter sib2, iclass 13, count 0 2006.162.08:00:10.18#ibcon#flushed, iclass 13, count 0 2006.162.08:00:10.18#ibcon#about to write, iclass 13, count 0 2006.162.08:00:10.18#ibcon#wrote, iclass 13, count 0 2006.162.08:00:10.18#ibcon#about to read 3, iclass 13, count 0 2006.162.08:00:10.21#ibcon#read 3, iclass 13, count 0 2006.162.08:00:10.21#ibcon#about to read 4, iclass 13, count 0 2006.162.08:00:10.21#ibcon#read 4, iclass 13, count 0 2006.162.08:00:10.21#ibcon#about to read 5, iclass 13, count 0 2006.162.08:00:10.21#ibcon#read 5, iclass 13, count 0 2006.162.08:00:10.21#ibcon#about to read 6, iclass 13, count 0 2006.162.08:00:10.21#ibcon#read 6, iclass 13, count 0 2006.162.08:00:10.21#ibcon#end of sib2, iclass 13, count 0 2006.162.08:00:10.21#ibcon#*after write, iclass 13, count 0 2006.162.08:00:10.21#ibcon#*before return 0, iclass 13, count 0 2006.162.08:00:10.21#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:00:10.21#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:00:10.21#ibcon#about to clear, iclass 13 cls_cnt 0 2006.162.08:00:10.21#ibcon#cleared, iclass 13 cls_cnt 0 2006.162.08:00:10.21$vc4f8/valo=4,832.99 2006.162.08:00:10.21#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.162.08:00:10.21#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.162.08:00:10.21#ibcon#ireg 17 cls_cnt 0 2006.162.08:00:10.21#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:00:10.21#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:00:10.21#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:00:10.21#ibcon#enter wrdev, iclass 15, count 0 2006.162.08:00:10.21#ibcon#first serial, iclass 15, count 0 2006.162.08:00:10.21#ibcon#enter sib2, iclass 15, count 0 2006.162.08:00:10.21#ibcon#flushed, iclass 15, count 0 2006.162.08:00:10.21#ibcon#about to write, iclass 15, count 0 2006.162.08:00:10.21#ibcon#wrote, iclass 15, count 0 2006.162.08:00:10.21#ibcon#about to read 3, iclass 15, count 0 2006.162.08:00:10.23#ibcon#read 3, iclass 15, count 0 2006.162.08:00:10.23#ibcon#about to read 4, iclass 15, count 0 2006.162.08:00:10.23#ibcon#read 4, iclass 15, count 0 2006.162.08:00:10.23#ibcon#about to read 5, iclass 15, count 0 2006.162.08:00:10.23#ibcon#read 5, iclass 15, count 0 2006.162.08:00:10.23#ibcon#about to read 6, iclass 15, count 0 2006.162.08:00:10.23#ibcon#read 6, iclass 15, count 0 2006.162.08:00:10.23#ibcon#end of sib2, iclass 15, count 0 2006.162.08:00:10.23#ibcon#*mode == 0, iclass 15, count 0 2006.162.08:00:10.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.162.08:00:10.23#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.08:00:10.23#ibcon#*before write, iclass 15, count 0 2006.162.08:00:10.23#ibcon#enter sib2, iclass 15, count 0 2006.162.08:00:10.23#ibcon#flushed, iclass 15, count 0 2006.162.08:00:10.23#ibcon#about to write, iclass 15, count 0 2006.162.08:00:10.23#ibcon#wrote, iclass 15, count 0 2006.162.08:00:10.23#ibcon#about to read 3, iclass 15, count 0 2006.162.08:00:10.27#ibcon#read 3, iclass 15, count 0 2006.162.08:00:10.27#ibcon#about to read 4, iclass 15, count 0 2006.162.08:00:10.27#ibcon#read 4, iclass 15, count 0 2006.162.08:00:10.27#ibcon#about to read 5, iclass 15, count 0 2006.162.08:00:10.27#ibcon#read 5, iclass 15, count 0 2006.162.08:00:10.27#ibcon#about to read 6, iclass 15, count 0 2006.162.08:00:10.27#ibcon#read 6, iclass 15, count 0 2006.162.08:00:10.27#ibcon#end of sib2, iclass 15, count 0 2006.162.08:00:10.27#ibcon#*after write, iclass 15, count 0 2006.162.08:00:10.27#ibcon#*before return 0, iclass 15, count 0 2006.162.08:00:10.27#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:00:10.27#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:00:10.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.162.08:00:10.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.162.08:00:10.27$vc4f8/va=4,7 2006.162.08:00:10.27#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.162.08:00:10.27#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.162.08:00:10.27#ibcon#ireg 11 cls_cnt 2 2006.162.08:00:10.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:00:10.33#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:00:10.33#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:00:10.33#ibcon#enter wrdev, iclass 17, count 2 2006.162.08:00:10.33#ibcon#first serial, iclass 17, count 2 2006.162.08:00:10.33#ibcon#enter sib2, iclass 17, count 2 2006.162.08:00:10.33#ibcon#flushed, iclass 17, count 2 2006.162.08:00:10.33#ibcon#about to write, iclass 17, count 2 2006.162.08:00:10.33#ibcon#wrote, iclass 17, count 2 2006.162.08:00:10.33#ibcon#about to read 3, iclass 17, count 2 2006.162.08:00:10.35#ibcon#read 3, iclass 17, count 2 2006.162.08:00:10.35#ibcon#about to read 4, iclass 17, count 2 2006.162.08:00:10.35#ibcon#read 4, iclass 17, count 2 2006.162.08:00:10.35#ibcon#about to read 5, iclass 17, count 2 2006.162.08:00:10.35#ibcon#read 5, iclass 17, count 2 2006.162.08:00:10.35#ibcon#about to read 6, iclass 17, count 2 2006.162.08:00:10.35#ibcon#read 6, iclass 17, count 2 2006.162.08:00:10.35#ibcon#end of sib2, iclass 17, count 2 2006.162.08:00:10.35#ibcon#*mode == 0, iclass 17, count 2 2006.162.08:00:10.35#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.162.08:00:10.35#ibcon#[25=AT04-07\r\n] 2006.162.08:00:10.35#ibcon#*before write, iclass 17, count 2 2006.162.08:00:10.35#ibcon#enter sib2, iclass 17, count 2 2006.162.08:00:10.35#ibcon#flushed, iclass 17, count 2 2006.162.08:00:10.35#ibcon#about to write, iclass 17, count 2 2006.162.08:00:10.35#ibcon#wrote, iclass 17, count 2 2006.162.08:00:10.35#ibcon#about to read 3, iclass 17, count 2 2006.162.08:00:10.38#ibcon#read 3, iclass 17, count 2 2006.162.08:00:10.38#ibcon#about to read 4, iclass 17, count 2 2006.162.08:00:10.38#ibcon#read 4, iclass 17, count 2 2006.162.08:00:10.38#ibcon#about to read 5, iclass 17, count 2 2006.162.08:00:10.38#ibcon#read 5, iclass 17, count 2 2006.162.08:00:10.38#ibcon#about to read 6, iclass 17, count 2 2006.162.08:00:10.38#ibcon#read 6, iclass 17, count 2 2006.162.08:00:10.38#ibcon#end of sib2, iclass 17, count 2 2006.162.08:00:10.38#ibcon#*after write, iclass 17, count 2 2006.162.08:00:10.38#ibcon#*before return 0, iclass 17, count 2 2006.162.08:00:10.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:00:10.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:00:10.38#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.162.08:00:10.38#ibcon#ireg 7 cls_cnt 0 2006.162.08:00:10.38#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:00:10.50#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:00:10.50#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:00:10.50#ibcon#enter wrdev, iclass 17, count 0 2006.162.08:00:10.50#ibcon#first serial, iclass 17, count 0 2006.162.08:00:10.50#ibcon#enter sib2, iclass 17, count 0 2006.162.08:00:10.50#ibcon#flushed, iclass 17, count 0 2006.162.08:00:10.50#ibcon#about to write, iclass 17, count 0 2006.162.08:00:10.50#ibcon#wrote, iclass 17, count 0 2006.162.08:00:10.50#ibcon#about to read 3, iclass 17, count 0 2006.162.08:00:10.52#ibcon#read 3, iclass 17, count 0 2006.162.08:00:10.52#ibcon#about to read 4, iclass 17, count 0 2006.162.08:00:10.52#ibcon#read 4, iclass 17, count 0 2006.162.08:00:10.52#ibcon#about to read 5, iclass 17, count 0 2006.162.08:00:10.52#ibcon#read 5, iclass 17, count 0 2006.162.08:00:10.52#ibcon#about to read 6, iclass 17, count 0 2006.162.08:00:10.52#ibcon#read 6, iclass 17, count 0 2006.162.08:00:10.52#ibcon#end of sib2, iclass 17, count 0 2006.162.08:00:10.52#ibcon#*mode == 0, iclass 17, count 0 2006.162.08:00:10.52#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.162.08:00:10.52#ibcon#[25=USB\r\n] 2006.162.08:00:10.52#ibcon#*before write, iclass 17, count 0 2006.162.08:00:10.52#ibcon#enter sib2, iclass 17, count 0 2006.162.08:00:10.52#ibcon#flushed, iclass 17, count 0 2006.162.08:00:10.52#ibcon#about to write, iclass 17, count 0 2006.162.08:00:10.52#ibcon#wrote, iclass 17, count 0 2006.162.08:00:10.52#ibcon#about to read 3, iclass 17, count 0 2006.162.08:00:10.55#ibcon#read 3, iclass 17, count 0 2006.162.08:00:10.55#ibcon#about to read 4, iclass 17, count 0 2006.162.08:00:10.55#ibcon#read 4, iclass 17, count 0 2006.162.08:00:10.55#ibcon#about to read 5, iclass 17, count 0 2006.162.08:00:10.55#ibcon#read 5, iclass 17, count 0 2006.162.08:00:10.55#ibcon#about to read 6, iclass 17, count 0 2006.162.08:00:10.55#ibcon#read 6, iclass 17, count 0 2006.162.08:00:10.55#ibcon#end of sib2, iclass 17, count 0 2006.162.08:00:10.55#ibcon#*after write, iclass 17, count 0 2006.162.08:00:10.55#ibcon#*before return 0, iclass 17, count 0 2006.162.08:00:10.55#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:00:10.55#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:00:10.55#ibcon#about to clear, iclass 17 cls_cnt 0 2006.162.08:00:10.55#ibcon#cleared, iclass 17 cls_cnt 0 2006.162.08:00:10.55$vc4f8/valo=5,652.99 2006.162.08:00:10.55#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.162.08:00:10.55#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.162.08:00:10.55#ibcon#ireg 17 cls_cnt 0 2006.162.08:00:10.55#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:00:10.55#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:00:10.55#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:00:10.55#ibcon#enter wrdev, iclass 19, count 0 2006.162.08:00:10.55#ibcon#first serial, iclass 19, count 0 2006.162.08:00:10.55#ibcon#enter sib2, iclass 19, count 0 2006.162.08:00:10.55#ibcon#flushed, iclass 19, count 0 2006.162.08:00:10.55#ibcon#about to write, iclass 19, count 0 2006.162.08:00:10.55#ibcon#wrote, iclass 19, count 0 2006.162.08:00:10.55#ibcon#about to read 3, iclass 19, count 0 2006.162.08:00:10.57#ibcon#read 3, iclass 19, count 0 2006.162.08:00:10.57#ibcon#about to read 4, iclass 19, count 0 2006.162.08:00:10.57#ibcon#read 4, iclass 19, count 0 2006.162.08:00:10.57#ibcon#about to read 5, iclass 19, count 0 2006.162.08:00:10.57#ibcon#read 5, iclass 19, count 0 2006.162.08:00:10.57#ibcon#about to read 6, iclass 19, count 0 2006.162.08:00:10.57#ibcon#read 6, iclass 19, count 0 2006.162.08:00:10.57#ibcon#end of sib2, iclass 19, count 0 2006.162.08:00:10.57#ibcon#*mode == 0, iclass 19, count 0 2006.162.08:00:10.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.162.08:00:10.57#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.08:00:10.57#ibcon#*before write, iclass 19, count 0 2006.162.08:00:10.57#ibcon#enter sib2, iclass 19, count 0 2006.162.08:00:10.57#ibcon#flushed, iclass 19, count 0 2006.162.08:00:10.57#ibcon#about to write, iclass 19, count 0 2006.162.08:00:10.57#ibcon#wrote, iclass 19, count 0 2006.162.08:00:10.57#ibcon#about to read 3, iclass 19, count 0 2006.162.08:00:10.61#ibcon#read 3, iclass 19, count 0 2006.162.08:00:10.61#ibcon#about to read 4, iclass 19, count 0 2006.162.08:00:10.61#ibcon#read 4, iclass 19, count 0 2006.162.08:00:10.61#ibcon#about to read 5, iclass 19, count 0 2006.162.08:00:10.61#ibcon#read 5, iclass 19, count 0 2006.162.08:00:10.61#ibcon#about to read 6, iclass 19, count 0 2006.162.08:00:10.61#ibcon#read 6, iclass 19, count 0 2006.162.08:00:10.61#ibcon#end of sib2, iclass 19, count 0 2006.162.08:00:10.61#ibcon#*after write, iclass 19, count 0 2006.162.08:00:10.61#ibcon#*before return 0, iclass 19, count 0 2006.162.08:00:10.61#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:00:10.61#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:00:10.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.162.08:00:10.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.162.08:00:10.61$vc4f8/va=5,7 2006.162.08:00:10.61#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.162.08:00:10.61#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.162.08:00:10.61#ibcon#ireg 11 cls_cnt 2 2006.162.08:00:10.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.162.08:00:10.67#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.162.08:00:10.67#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.162.08:00:10.67#ibcon#enter wrdev, iclass 21, count 2 2006.162.08:00:10.67#ibcon#first serial, iclass 21, count 2 2006.162.08:00:10.67#ibcon#enter sib2, iclass 21, count 2 2006.162.08:00:10.67#ibcon#flushed, iclass 21, count 2 2006.162.08:00:10.67#ibcon#about to write, iclass 21, count 2 2006.162.08:00:10.67#ibcon#wrote, iclass 21, count 2 2006.162.08:00:10.67#ibcon#about to read 3, iclass 21, count 2 2006.162.08:00:10.69#ibcon#read 3, iclass 21, count 2 2006.162.08:00:10.69#ibcon#about to read 4, iclass 21, count 2 2006.162.08:00:10.69#ibcon#read 4, iclass 21, count 2 2006.162.08:00:10.69#ibcon#about to read 5, iclass 21, count 2 2006.162.08:00:10.69#ibcon#read 5, iclass 21, count 2 2006.162.08:00:10.69#ibcon#about to read 6, iclass 21, count 2 2006.162.08:00:10.69#ibcon#read 6, iclass 21, count 2 2006.162.08:00:10.69#ibcon#end of sib2, iclass 21, count 2 2006.162.08:00:10.69#ibcon#*mode == 0, iclass 21, count 2 2006.162.08:00:10.69#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.162.08:00:10.69#ibcon#[25=AT05-07\r\n] 2006.162.08:00:10.69#ibcon#*before write, iclass 21, count 2 2006.162.08:00:10.69#ibcon#enter sib2, iclass 21, count 2 2006.162.08:00:10.69#ibcon#flushed, iclass 21, count 2 2006.162.08:00:10.69#ibcon#about to write, iclass 21, count 2 2006.162.08:00:10.69#ibcon#wrote, iclass 21, count 2 2006.162.08:00:10.69#ibcon#about to read 3, iclass 21, count 2 2006.162.08:00:10.72#ibcon#read 3, iclass 21, count 2 2006.162.08:00:10.72#ibcon#about to read 4, iclass 21, count 2 2006.162.08:00:10.72#ibcon#read 4, iclass 21, count 2 2006.162.08:00:10.72#ibcon#about to read 5, iclass 21, count 2 2006.162.08:00:10.72#ibcon#read 5, iclass 21, count 2 2006.162.08:00:10.72#ibcon#about to read 6, iclass 21, count 2 2006.162.08:00:10.72#ibcon#read 6, iclass 21, count 2 2006.162.08:00:10.72#ibcon#end of sib2, iclass 21, count 2 2006.162.08:00:10.72#ibcon#*after write, iclass 21, count 2 2006.162.08:00:10.72#ibcon#*before return 0, iclass 21, count 2 2006.162.08:00:10.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.162.08:00:10.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.162.08:00:10.72#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.162.08:00:10.72#ibcon#ireg 7 cls_cnt 0 2006.162.08:00:10.72#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.162.08:00:10.84#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.162.08:00:10.84#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.162.08:00:10.84#ibcon#enter wrdev, iclass 21, count 0 2006.162.08:00:10.84#ibcon#first serial, iclass 21, count 0 2006.162.08:00:10.84#ibcon#enter sib2, iclass 21, count 0 2006.162.08:00:10.84#ibcon#flushed, iclass 21, count 0 2006.162.08:00:10.84#ibcon#about to write, iclass 21, count 0 2006.162.08:00:10.84#ibcon#wrote, iclass 21, count 0 2006.162.08:00:10.84#ibcon#about to read 3, iclass 21, count 0 2006.162.08:00:10.86#ibcon#read 3, iclass 21, count 0 2006.162.08:00:10.86#ibcon#about to read 4, iclass 21, count 0 2006.162.08:00:10.86#ibcon#read 4, iclass 21, count 0 2006.162.08:00:10.86#ibcon#about to read 5, iclass 21, count 0 2006.162.08:00:10.86#ibcon#read 5, iclass 21, count 0 2006.162.08:00:10.86#ibcon#about to read 6, iclass 21, count 0 2006.162.08:00:10.86#ibcon#read 6, iclass 21, count 0 2006.162.08:00:10.86#ibcon#end of sib2, iclass 21, count 0 2006.162.08:00:10.86#ibcon#*mode == 0, iclass 21, count 0 2006.162.08:00:10.86#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.162.08:00:10.86#ibcon#[25=USB\r\n] 2006.162.08:00:10.86#ibcon#*before write, iclass 21, count 0 2006.162.08:00:10.86#ibcon#enter sib2, iclass 21, count 0 2006.162.08:00:10.86#ibcon#flushed, iclass 21, count 0 2006.162.08:00:10.86#ibcon#about to write, iclass 21, count 0 2006.162.08:00:10.86#ibcon#wrote, iclass 21, count 0 2006.162.08:00:10.86#ibcon#about to read 3, iclass 21, count 0 2006.162.08:00:10.89#ibcon#read 3, iclass 21, count 0 2006.162.08:00:10.89#ibcon#about to read 4, iclass 21, count 0 2006.162.08:00:10.89#ibcon#read 4, iclass 21, count 0 2006.162.08:00:10.89#ibcon#about to read 5, iclass 21, count 0 2006.162.08:00:10.89#ibcon#read 5, iclass 21, count 0 2006.162.08:00:10.89#ibcon#about to read 6, iclass 21, count 0 2006.162.08:00:10.89#ibcon#read 6, iclass 21, count 0 2006.162.08:00:10.89#ibcon#end of sib2, iclass 21, count 0 2006.162.08:00:10.89#ibcon#*after write, iclass 21, count 0 2006.162.08:00:10.89#ibcon#*before return 0, iclass 21, count 0 2006.162.08:00:10.89#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.162.08:00:10.89#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.162.08:00:10.89#ibcon#about to clear, iclass 21 cls_cnt 0 2006.162.08:00:10.89#ibcon#cleared, iclass 21 cls_cnt 0 2006.162.08:00:10.89$vc4f8/valo=6,772.99 2006.162.08:00:10.89#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.162.08:00:10.89#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.162.08:00:10.89#ibcon#ireg 17 cls_cnt 0 2006.162.08:00:10.89#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.162.08:00:10.89#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.162.08:00:10.89#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.162.08:00:10.89#ibcon#enter wrdev, iclass 23, count 0 2006.162.08:00:10.89#ibcon#first serial, iclass 23, count 0 2006.162.08:00:10.89#ibcon#enter sib2, iclass 23, count 0 2006.162.08:00:10.89#ibcon#flushed, iclass 23, count 0 2006.162.08:00:10.89#ibcon#about to write, iclass 23, count 0 2006.162.08:00:10.89#ibcon#wrote, iclass 23, count 0 2006.162.08:00:10.89#ibcon#about to read 3, iclass 23, count 0 2006.162.08:00:10.91#ibcon#read 3, iclass 23, count 0 2006.162.08:00:10.91#ibcon#about to read 4, iclass 23, count 0 2006.162.08:00:10.91#ibcon#read 4, iclass 23, count 0 2006.162.08:00:10.91#ibcon#about to read 5, iclass 23, count 0 2006.162.08:00:10.91#ibcon#read 5, iclass 23, count 0 2006.162.08:00:10.91#ibcon#about to read 6, iclass 23, count 0 2006.162.08:00:10.91#ibcon#read 6, iclass 23, count 0 2006.162.08:00:10.91#ibcon#end of sib2, iclass 23, count 0 2006.162.08:00:10.91#ibcon#*mode == 0, iclass 23, count 0 2006.162.08:00:10.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.162.08:00:10.91#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.08:00:10.91#ibcon#*before write, iclass 23, count 0 2006.162.08:00:10.91#ibcon#enter sib2, iclass 23, count 0 2006.162.08:00:10.91#ibcon#flushed, iclass 23, count 0 2006.162.08:00:10.91#ibcon#about to write, iclass 23, count 0 2006.162.08:00:10.91#ibcon#wrote, iclass 23, count 0 2006.162.08:00:10.91#ibcon#about to read 3, iclass 23, count 0 2006.162.08:00:10.95#ibcon#read 3, iclass 23, count 0 2006.162.08:00:10.95#ibcon#about to read 4, iclass 23, count 0 2006.162.08:00:10.95#ibcon#read 4, iclass 23, count 0 2006.162.08:00:10.95#ibcon#about to read 5, iclass 23, count 0 2006.162.08:00:10.95#ibcon#read 5, iclass 23, count 0 2006.162.08:00:10.95#ibcon#about to read 6, iclass 23, count 0 2006.162.08:00:10.95#ibcon#read 6, iclass 23, count 0 2006.162.08:00:10.95#ibcon#end of sib2, iclass 23, count 0 2006.162.08:00:10.95#ibcon#*after write, iclass 23, count 0 2006.162.08:00:10.95#ibcon#*before return 0, iclass 23, count 0 2006.162.08:00:10.95#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.162.08:00:10.95#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.162.08:00:10.95#ibcon#about to clear, iclass 23 cls_cnt 0 2006.162.08:00:10.95#ibcon#cleared, iclass 23 cls_cnt 0 2006.162.08:00:10.95$vc4f8/va=6,6 2006.162.08:00:10.95#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.162.08:00:10.95#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.162.08:00:10.95#ibcon#ireg 11 cls_cnt 2 2006.162.08:00:10.95#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.162.08:00:11.01#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.162.08:00:11.01#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.162.08:00:11.01#ibcon#enter wrdev, iclass 25, count 2 2006.162.08:00:11.01#ibcon#first serial, iclass 25, count 2 2006.162.08:00:11.01#ibcon#enter sib2, iclass 25, count 2 2006.162.08:00:11.01#ibcon#flushed, iclass 25, count 2 2006.162.08:00:11.01#ibcon#about to write, iclass 25, count 2 2006.162.08:00:11.01#ibcon#wrote, iclass 25, count 2 2006.162.08:00:11.01#ibcon#about to read 3, iclass 25, count 2 2006.162.08:00:11.03#ibcon#read 3, iclass 25, count 2 2006.162.08:00:11.03#ibcon#about to read 4, iclass 25, count 2 2006.162.08:00:11.03#ibcon#read 4, iclass 25, count 2 2006.162.08:00:11.03#ibcon#about to read 5, iclass 25, count 2 2006.162.08:00:11.03#ibcon#read 5, iclass 25, count 2 2006.162.08:00:11.03#ibcon#about to read 6, iclass 25, count 2 2006.162.08:00:11.03#ibcon#read 6, iclass 25, count 2 2006.162.08:00:11.03#ibcon#end of sib2, iclass 25, count 2 2006.162.08:00:11.03#ibcon#*mode == 0, iclass 25, count 2 2006.162.08:00:11.03#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.162.08:00:11.03#ibcon#[25=AT06-06\r\n] 2006.162.08:00:11.03#ibcon#*before write, iclass 25, count 2 2006.162.08:00:11.03#ibcon#enter sib2, iclass 25, count 2 2006.162.08:00:11.03#ibcon#flushed, iclass 25, count 2 2006.162.08:00:11.03#ibcon#about to write, iclass 25, count 2 2006.162.08:00:11.03#ibcon#wrote, iclass 25, count 2 2006.162.08:00:11.03#ibcon#about to read 3, iclass 25, count 2 2006.162.08:00:11.06#ibcon#read 3, iclass 25, count 2 2006.162.08:00:11.06#ibcon#about to read 4, iclass 25, count 2 2006.162.08:00:11.06#ibcon#read 4, iclass 25, count 2 2006.162.08:00:11.06#ibcon#about to read 5, iclass 25, count 2 2006.162.08:00:11.06#ibcon#read 5, iclass 25, count 2 2006.162.08:00:11.06#ibcon#about to read 6, iclass 25, count 2 2006.162.08:00:11.06#ibcon#read 6, iclass 25, count 2 2006.162.08:00:11.06#ibcon#end of sib2, iclass 25, count 2 2006.162.08:00:11.06#ibcon#*after write, iclass 25, count 2 2006.162.08:00:11.06#ibcon#*before return 0, iclass 25, count 2 2006.162.08:00:11.06#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.162.08:00:11.06#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.162.08:00:11.06#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.162.08:00:11.06#ibcon#ireg 7 cls_cnt 0 2006.162.08:00:11.06#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.162.08:00:11.18#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.162.08:00:11.18#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.162.08:00:11.18#ibcon#enter wrdev, iclass 25, count 0 2006.162.08:00:11.18#ibcon#first serial, iclass 25, count 0 2006.162.08:00:11.18#ibcon#enter sib2, iclass 25, count 0 2006.162.08:00:11.18#ibcon#flushed, iclass 25, count 0 2006.162.08:00:11.18#ibcon#about to write, iclass 25, count 0 2006.162.08:00:11.18#ibcon#wrote, iclass 25, count 0 2006.162.08:00:11.18#ibcon#about to read 3, iclass 25, count 0 2006.162.08:00:11.20#ibcon#read 3, iclass 25, count 0 2006.162.08:00:11.20#ibcon#about to read 4, iclass 25, count 0 2006.162.08:00:11.20#ibcon#read 4, iclass 25, count 0 2006.162.08:00:11.20#ibcon#about to read 5, iclass 25, count 0 2006.162.08:00:11.20#ibcon#read 5, iclass 25, count 0 2006.162.08:00:11.20#ibcon#about to read 6, iclass 25, count 0 2006.162.08:00:11.20#ibcon#read 6, iclass 25, count 0 2006.162.08:00:11.20#ibcon#end of sib2, iclass 25, count 0 2006.162.08:00:11.20#ibcon#*mode == 0, iclass 25, count 0 2006.162.08:00:11.20#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.162.08:00:11.20#ibcon#[25=USB\r\n] 2006.162.08:00:11.20#ibcon#*before write, iclass 25, count 0 2006.162.08:00:11.20#ibcon#enter sib2, iclass 25, count 0 2006.162.08:00:11.20#ibcon#flushed, iclass 25, count 0 2006.162.08:00:11.20#ibcon#about to write, iclass 25, count 0 2006.162.08:00:11.20#ibcon#wrote, iclass 25, count 0 2006.162.08:00:11.20#ibcon#about to read 3, iclass 25, count 0 2006.162.08:00:11.23#ibcon#read 3, iclass 25, count 0 2006.162.08:00:11.23#ibcon#about to read 4, iclass 25, count 0 2006.162.08:00:11.23#ibcon#read 4, iclass 25, count 0 2006.162.08:00:11.23#ibcon#about to read 5, iclass 25, count 0 2006.162.08:00:11.23#ibcon#read 5, iclass 25, count 0 2006.162.08:00:11.23#ibcon#about to read 6, iclass 25, count 0 2006.162.08:00:11.23#ibcon#read 6, iclass 25, count 0 2006.162.08:00:11.23#ibcon#end of sib2, iclass 25, count 0 2006.162.08:00:11.23#ibcon#*after write, iclass 25, count 0 2006.162.08:00:11.23#ibcon#*before return 0, iclass 25, count 0 2006.162.08:00:11.23#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.162.08:00:11.23#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.162.08:00:11.23#ibcon#about to clear, iclass 25 cls_cnt 0 2006.162.08:00:11.23#ibcon#cleared, iclass 25 cls_cnt 0 2006.162.08:00:11.23$vc4f8/valo=7,832.99 2006.162.08:00:11.23#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.162.08:00:11.23#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.162.08:00:11.23#ibcon#ireg 17 cls_cnt 0 2006.162.08:00:11.23#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.162.08:00:11.23#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.162.08:00:11.23#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.162.08:00:11.23#ibcon#enter wrdev, iclass 27, count 0 2006.162.08:00:11.23#ibcon#first serial, iclass 27, count 0 2006.162.08:00:11.23#ibcon#enter sib2, iclass 27, count 0 2006.162.08:00:11.23#ibcon#flushed, iclass 27, count 0 2006.162.08:00:11.23#ibcon#about to write, iclass 27, count 0 2006.162.08:00:11.23#ibcon#wrote, iclass 27, count 0 2006.162.08:00:11.23#ibcon#about to read 3, iclass 27, count 0 2006.162.08:00:11.25#ibcon#read 3, iclass 27, count 0 2006.162.08:00:11.25#ibcon#about to read 4, iclass 27, count 0 2006.162.08:00:11.25#ibcon#read 4, iclass 27, count 0 2006.162.08:00:11.25#ibcon#about to read 5, iclass 27, count 0 2006.162.08:00:11.25#ibcon#read 5, iclass 27, count 0 2006.162.08:00:11.25#ibcon#about to read 6, iclass 27, count 0 2006.162.08:00:11.25#ibcon#read 6, iclass 27, count 0 2006.162.08:00:11.25#ibcon#end of sib2, iclass 27, count 0 2006.162.08:00:11.25#ibcon#*mode == 0, iclass 27, count 0 2006.162.08:00:11.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.162.08:00:11.25#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.08:00:11.25#ibcon#*before write, iclass 27, count 0 2006.162.08:00:11.25#ibcon#enter sib2, iclass 27, count 0 2006.162.08:00:11.25#ibcon#flushed, iclass 27, count 0 2006.162.08:00:11.25#ibcon#about to write, iclass 27, count 0 2006.162.08:00:11.25#ibcon#wrote, iclass 27, count 0 2006.162.08:00:11.25#ibcon#about to read 3, iclass 27, count 0 2006.162.08:00:11.29#ibcon#read 3, iclass 27, count 0 2006.162.08:00:11.29#ibcon#about to read 4, iclass 27, count 0 2006.162.08:00:11.29#ibcon#read 4, iclass 27, count 0 2006.162.08:00:11.29#ibcon#about to read 5, iclass 27, count 0 2006.162.08:00:11.29#ibcon#read 5, iclass 27, count 0 2006.162.08:00:11.29#ibcon#about to read 6, iclass 27, count 0 2006.162.08:00:11.29#ibcon#read 6, iclass 27, count 0 2006.162.08:00:11.29#ibcon#end of sib2, iclass 27, count 0 2006.162.08:00:11.29#ibcon#*after write, iclass 27, count 0 2006.162.08:00:11.29#ibcon#*before return 0, iclass 27, count 0 2006.162.08:00:11.29#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.162.08:00:11.29#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.162.08:00:11.29#ibcon#about to clear, iclass 27 cls_cnt 0 2006.162.08:00:11.29#ibcon#cleared, iclass 27 cls_cnt 0 2006.162.08:00:11.29$vc4f8/va=7,6 2006.162.08:00:11.29#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.162.08:00:11.29#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.162.08:00:11.29#ibcon#ireg 11 cls_cnt 2 2006.162.08:00:11.29#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.162.08:00:11.35#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.162.08:00:11.35#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.162.08:00:11.35#ibcon#enter wrdev, iclass 29, count 2 2006.162.08:00:11.35#ibcon#first serial, iclass 29, count 2 2006.162.08:00:11.35#ibcon#enter sib2, iclass 29, count 2 2006.162.08:00:11.35#ibcon#flushed, iclass 29, count 2 2006.162.08:00:11.35#ibcon#about to write, iclass 29, count 2 2006.162.08:00:11.35#ibcon#wrote, iclass 29, count 2 2006.162.08:00:11.35#ibcon#about to read 3, iclass 29, count 2 2006.162.08:00:11.37#ibcon#read 3, iclass 29, count 2 2006.162.08:00:11.37#ibcon#about to read 4, iclass 29, count 2 2006.162.08:00:11.37#ibcon#read 4, iclass 29, count 2 2006.162.08:00:11.37#ibcon#about to read 5, iclass 29, count 2 2006.162.08:00:11.37#ibcon#read 5, iclass 29, count 2 2006.162.08:00:11.37#ibcon#about to read 6, iclass 29, count 2 2006.162.08:00:11.37#ibcon#read 6, iclass 29, count 2 2006.162.08:00:11.37#ibcon#end of sib2, iclass 29, count 2 2006.162.08:00:11.37#ibcon#*mode == 0, iclass 29, count 2 2006.162.08:00:11.37#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.162.08:00:11.37#ibcon#[25=AT07-06\r\n] 2006.162.08:00:11.37#ibcon#*before write, iclass 29, count 2 2006.162.08:00:11.37#ibcon#enter sib2, iclass 29, count 2 2006.162.08:00:11.37#ibcon#flushed, iclass 29, count 2 2006.162.08:00:11.37#ibcon#about to write, iclass 29, count 2 2006.162.08:00:11.37#ibcon#wrote, iclass 29, count 2 2006.162.08:00:11.37#ibcon#about to read 3, iclass 29, count 2 2006.162.08:00:11.40#ibcon#read 3, iclass 29, count 2 2006.162.08:00:11.40#ibcon#about to read 4, iclass 29, count 2 2006.162.08:00:11.40#ibcon#read 4, iclass 29, count 2 2006.162.08:00:11.40#ibcon#about to read 5, iclass 29, count 2 2006.162.08:00:11.40#ibcon#read 5, iclass 29, count 2 2006.162.08:00:11.40#ibcon#about to read 6, iclass 29, count 2 2006.162.08:00:11.40#ibcon#read 6, iclass 29, count 2 2006.162.08:00:11.40#ibcon#end of sib2, iclass 29, count 2 2006.162.08:00:11.40#ibcon#*after write, iclass 29, count 2 2006.162.08:00:11.40#ibcon#*before return 0, iclass 29, count 2 2006.162.08:00:11.40#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.162.08:00:11.40#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.162.08:00:11.40#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.162.08:00:11.40#ibcon#ireg 7 cls_cnt 0 2006.162.08:00:11.40#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.162.08:00:11.52#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.162.08:00:11.52#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.162.08:00:11.52#ibcon#enter wrdev, iclass 29, count 0 2006.162.08:00:11.52#ibcon#first serial, iclass 29, count 0 2006.162.08:00:11.52#ibcon#enter sib2, iclass 29, count 0 2006.162.08:00:11.52#ibcon#flushed, iclass 29, count 0 2006.162.08:00:11.52#ibcon#about to write, iclass 29, count 0 2006.162.08:00:11.52#ibcon#wrote, iclass 29, count 0 2006.162.08:00:11.52#ibcon#about to read 3, iclass 29, count 0 2006.162.08:00:11.55#ibcon#read 3, iclass 29, count 0 2006.162.08:00:11.55#ibcon#about to read 4, iclass 29, count 0 2006.162.08:00:11.55#ibcon#read 4, iclass 29, count 0 2006.162.08:00:11.55#ibcon#about to read 5, iclass 29, count 0 2006.162.08:00:11.55#ibcon#read 5, iclass 29, count 0 2006.162.08:00:11.55#ibcon#about to read 6, iclass 29, count 0 2006.162.08:00:11.55#ibcon#read 6, iclass 29, count 0 2006.162.08:00:11.55#ibcon#end of sib2, iclass 29, count 0 2006.162.08:00:11.55#ibcon#*mode == 0, iclass 29, count 0 2006.162.08:00:11.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.162.08:00:11.55#ibcon#[25=USB\r\n] 2006.162.08:00:11.55#ibcon#*before write, iclass 29, count 0 2006.162.08:00:11.55#ibcon#enter sib2, iclass 29, count 0 2006.162.08:00:11.55#ibcon#flushed, iclass 29, count 0 2006.162.08:00:11.55#ibcon#about to write, iclass 29, count 0 2006.162.08:00:11.55#ibcon#wrote, iclass 29, count 0 2006.162.08:00:11.55#ibcon#about to read 3, iclass 29, count 0 2006.162.08:00:11.58#ibcon#read 3, iclass 29, count 0 2006.162.08:00:11.58#ibcon#about to read 4, iclass 29, count 0 2006.162.08:00:11.58#ibcon#read 4, iclass 29, count 0 2006.162.08:00:11.58#ibcon#about to read 5, iclass 29, count 0 2006.162.08:00:11.58#ibcon#read 5, iclass 29, count 0 2006.162.08:00:11.58#ibcon#about to read 6, iclass 29, count 0 2006.162.08:00:11.58#ibcon#read 6, iclass 29, count 0 2006.162.08:00:11.58#ibcon#end of sib2, iclass 29, count 0 2006.162.08:00:11.58#ibcon#*after write, iclass 29, count 0 2006.162.08:00:11.58#ibcon#*before return 0, iclass 29, count 0 2006.162.08:00:11.58#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.162.08:00:11.58#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.162.08:00:11.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.162.08:00:11.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.162.08:00:11.58$vc4f8/valo=8,852.99 2006.162.08:00:11.58#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.162.08:00:11.58#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.162.08:00:11.58#ibcon#ireg 17 cls_cnt 0 2006.162.08:00:11.58#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:00:11.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:00:11.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:00:11.58#ibcon#enter wrdev, iclass 32, count 0 2006.162.08:00:11.58#ibcon#first serial, iclass 32, count 0 2006.162.08:00:11.58#ibcon#enter sib2, iclass 32, count 0 2006.162.08:00:11.58#ibcon#flushed, iclass 32, count 0 2006.162.08:00:11.58#ibcon#about to write, iclass 32, count 0 2006.162.08:00:11.58#ibcon#wrote, iclass 32, count 0 2006.162.08:00:11.58#ibcon#about to read 3, iclass 32, count 0 2006.162.08:00:11.59#abcon#<5=/03 1.6 3.0 17.871001006.9\r\n> 2006.162.08:00:11.60#ibcon#read 3, iclass 32, count 0 2006.162.08:00:11.60#ibcon#about to read 4, iclass 32, count 0 2006.162.08:00:11.60#ibcon#read 4, iclass 32, count 0 2006.162.08:00:11.60#ibcon#about to read 5, iclass 32, count 0 2006.162.08:00:11.60#ibcon#read 5, iclass 32, count 0 2006.162.08:00:11.60#ibcon#about to read 6, iclass 32, count 0 2006.162.08:00:11.60#ibcon#read 6, iclass 32, count 0 2006.162.08:00:11.60#ibcon#end of sib2, iclass 32, count 0 2006.162.08:00:11.60#ibcon#*mode == 0, iclass 32, count 0 2006.162.08:00:11.60#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.162.08:00:11.60#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.08:00:11.60#ibcon#*before write, iclass 32, count 0 2006.162.08:00:11.60#ibcon#enter sib2, iclass 32, count 0 2006.162.08:00:11.60#ibcon#flushed, iclass 32, count 0 2006.162.08:00:11.60#ibcon#about to write, iclass 32, count 0 2006.162.08:00:11.60#ibcon#wrote, iclass 32, count 0 2006.162.08:00:11.60#ibcon#about to read 3, iclass 32, count 0 2006.162.08:00:11.61#abcon#{5=INTERFACE CLEAR} 2006.162.08:00:11.64#ibcon#read 3, iclass 32, count 0 2006.162.08:00:11.64#ibcon#about to read 4, iclass 32, count 0 2006.162.08:00:11.64#ibcon#read 4, iclass 32, count 0 2006.162.08:00:11.64#ibcon#about to read 5, iclass 32, count 0 2006.162.08:00:11.64#ibcon#read 5, iclass 32, count 0 2006.162.08:00:11.64#ibcon#about to read 6, iclass 32, count 0 2006.162.08:00:11.64#ibcon#read 6, iclass 32, count 0 2006.162.08:00:11.64#ibcon#end of sib2, iclass 32, count 0 2006.162.08:00:11.64#ibcon#*after write, iclass 32, count 0 2006.162.08:00:11.64#ibcon#*before return 0, iclass 32, count 0 2006.162.08:00:11.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:00:11.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:00:11.64#ibcon#about to clear, iclass 32 cls_cnt 0 2006.162.08:00:11.64#ibcon#cleared, iclass 32 cls_cnt 0 2006.162.08:00:11.64$vc4f8/va=8,7 2006.162.08:00:11.64#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.162.08:00:11.64#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.162.08:00:11.64#ibcon#ireg 11 cls_cnt 2 2006.162.08:00:11.64#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:00:11.67#abcon#[5=S1D000X0/0*\r\n] 2006.162.08:00:11.70#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:00:11.70#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:00:11.70#ibcon#enter wrdev, iclass 36, count 2 2006.162.08:00:11.70#ibcon#first serial, iclass 36, count 2 2006.162.08:00:11.70#ibcon#enter sib2, iclass 36, count 2 2006.162.08:00:11.70#ibcon#flushed, iclass 36, count 2 2006.162.08:00:11.70#ibcon#about to write, iclass 36, count 2 2006.162.08:00:11.70#ibcon#wrote, iclass 36, count 2 2006.162.08:00:11.70#ibcon#about to read 3, iclass 36, count 2 2006.162.08:00:11.72#ibcon#read 3, iclass 36, count 2 2006.162.08:00:11.72#ibcon#about to read 4, iclass 36, count 2 2006.162.08:00:11.72#ibcon#read 4, iclass 36, count 2 2006.162.08:00:11.72#ibcon#about to read 5, iclass 36, count 2 2006.162.08:00:11.72#ibcon#read 5, iclass 36, count 2 2006.162.08:00:11.72#ibcon#about to read 6, iclass 36, count 2 2006.162.08:00:11.72#ibcon#read 6, iclass 36, count 2 2006.162.08:00:11.72#ibcon#end of sib2, iclass 36, count 2 2006.162.08:00:11.72#ibcon#*mode == 0, iclass 36, count 2 2006.162.08:00:11.72#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.162.08:00:11.72#ibcon#[25=AT08-07\r\n] 2006.162.08:00:11.72#ibcon#*before write, iclass 36, count 2 2006.162.08:00:11.72#ibcon#enter sib2, iclass 36, count 2 2006.162.08:00:11.72#ibcon#flushed, iclass 36, count 2 2006.162.08:00:11.72#ibcon#about to write, iclass 36, count 2 2006.162.08:00:11.72#ibcon#wrote, iclass 36, count 2 2006.162.08:00:11.72#ibcon#about to read 3, iclass 36, count 2 2006.162.08:00:11.75#ibcon#read 3, iclass 36, count 2 2006.162.08:00:11.75#ibcon#about to read 4, iclass 36, count 2 2006.162.08:00:11.75#ibcon#read 4, iclass 36, count 2 2006.162.08:00:11.75#ibcon#about to read 5, iclass 36, count 2 2006.162.08:00:11.75#ibcon#read 5, iclass 36, count 2 2006.162.08:00:11.75#ibcon#about to read 6, iclass 36, count 2 2006.162.08:00:11.75#ibcon#read 6, iclass 36, count 2 2006.162.08:00:11.75#ibcon#end of sib2, iclass 36, count 2 2006.162.08:00:11.75#ibcon#*after write, iclass 36, count 2 2006.162.08:00:11.75#ibcon#*before return 0, iclass 36, count 2 2006.162.08:00:11.75#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:00:11.75#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:00:11.75#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.162.08:00:11.75#ibcon#ireg 7 cls_cnt 0 2006.162.08:00:11.75#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:00:11.87#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:00:11.87#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:00:11.87#ibcon#enter wrdev, iclass 36, count 0 2006.162.08:00:11.87#ibcon#first serial, iclass 36, count 0 2006.162.08:00:11.87#ibcon#enter sib2, iclass 36, count 0 2006.162.08:00:11.87#ibcon#flushed, iclass 36, count 0 2006.162.08:00:11.87#ibcon#about to write, iclass 36, count 0 2006.162.08:00:11.87#ibcon#wrote, iclass 36, count 0 2006.162.08:00:11.87#ibcon#about to read 3, iclass 36, count 0 2006.162.08:00:11.89#ibcon#read 3, iclass 36, count 0 2006.162.08:00:11.89#ibcon#about to read 4, iclass 36, count 0 2006.162.08:00:11.89#ibcon#read 4, iclass 36, count 0 2006.162.08:00:11.89#ibcon#about to read 5, iclass 36, count 0 2006.162.08:00:11.89#ibcon#read 5, iclass 36, count 0 2006.162.08:00:11.89#ibcon#about to read 6, iclass 36, count 0 2006.162.08:00:11.89#ibcon#read 6, iclass 36, count 0 2006.162.08:00:11.89#ibcon#end of sib2, iclass 36, count 0 2006.162.08:00:11.89#ibcon#*mode == 0, iclass 36, count 0 2006.162.08:00:11.89#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.162.08:00:11.89#ibcon#[25=USB\r\n] 2006.162.08:00:11.89#ibcon#*before write, iclass 36, count 0 2006.162.08:00:11.89#ibcon#enter sib2, iclass 36, count 0 2006.162.08:00:11.89#ibcon#flushed, iclass 36, count 0 2006.162.08:00:11.89#ibcon#about to write, iclass 36, count 0 2006.162.08:00:11.89#ibcon#wrote, iclass 36, count 0 2006.162.08:00:11.89#ibcon#about to read 3, iclass 36, count 0 2006.162.08:00:11.92#ibcon#read 3, iclass 36, count 0 2006.162.08:00:11.92#ibcon#about to read 4, iclass 36, count 0 2006.162.08:00:11.92#ibcon#read 4, iclass 36, count 0 2006.162.08:00:11.92#ibcon#about to read 5, iclass 36, count 0 2006.162.08:00:11.92#ibcon#read 5, iclass 36, count 0 2006.162.08:00:11.92#ibcon#about to read 6, iclass 36, count 0 2006.162.08:00:11.92#ibcon#read 6, iclass 36, count 0 2006.162.08:00:11.92#ibcon#end of sib2, iclass 36, count 0 2006.162.08:00:11.92#ibcon#*after write, iclass 36, count 0 2006.162.08:00:11.92#ibcon#*before return 0, iclass 36, count 0 2006.162.08:00:11.92#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:00:11.92#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:00:11.92#ibcon#about to clear, iclass 36 cls_cnt 0 2006.162.08:00:11.92#ibcon#cleared, iclass 36 cls_cnt 0 2006.162.08:00:11.92$vc4f8/vblo=1,632.99 2006.162.08:00:11.92#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.162.08:00:11.92#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.162.08:00:11.92#ibcon#ireg 17 cls_cnt 0 2006.162.08:00:11.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:00:11.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:00:11.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:00:11.92#ibcon#enter wrdev, iclass 39, count 0 2006.162.08:00:11.92#ibcon#first serial, iclass 39, count 0 2006.162.08:00:11.92#ibcon#enter sib2, iclass 39, count 0 2006.162.08:00:11.92#ibcon#flushed, iclass 39, count 0 2006.162.08:00:11.92#ibcon#about to write, iclass 39, count 0 2006.162.08:00:11.92#ibcon#wrote, iclass 39, count 0 2006.162.08:00:11.92#ibcon#about to read 3, iclass 39, count 0 2006.162.08:00:11.94#ibcon#read 3, iclass 39, count 0 2006.162.08:00:11.94#ibcon#about to read 4, iclass 39, count 0 2006.162.08:00:11.94#ibcon#read 4, iclass 39, count 0 2006.162.08:00:11.94#ibcon#about to read 5, iclass 39, count 0 2006.162.08:00:11.94#ibcon#read 5, iclass 39, count 0 2006.162.08:00:11.94#ibcon#about to read 6, iclass 39, count 0 2006.162.08:00:11.94#ibcon#read 6, iclass 39, count 0 2006.162.08:00:11.94#ibcon#end of sib2, iclass 39, count 0 2006.162.08:00:11.94#ibcon#*mode == 0, iclass 39, count 0 2006.162.08:00:11.94#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.162.08:00:11.94#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.08:00:11.94#ibcon#*before write, iclass 39, count 0 2006.162.08:00:11.94#ibcon#enter sib2, iclass 39, count 0 2006.162.08:00:11.94#ibcon#flushed, iclass 39, count 0 2006.162.08:00:11.94#ibcon#about to write, iclass 39, count 0 2006.162.08:00:11.94#ibcon#wrote, iclass 39, count 0 2006.162.08:00:11.94#ibcon#about to read 3, iclass 39, count 0 2006.162.08:00:11.98#ibcon#read 3, iclass 39, count 0 2006.162.08:00:11.98#ibcon#about to read 4, iclass 39, count 0 2006.162.08:00:11.98#ibcon#read 4, iclass 39, count 0 2006.162.08:00:11.98#ibcon#about to read 5, iclass 39, count 0 2006.162.08:00:11.98#ibcon#read 5, iclass 39, count 0 2006.162.08:00:11.98#ibcon#about to read 6, iclass 39, count 0 2006.162.08:00:11.98#ibcon#read 6, iclass 39, count 0 2006.162.08:00:11.98#ibcon#end of sib2, iclass 39, count 0 2006.162.08:00:11.98#ibcon#*after write, iclass 39, count 0 2006.162.08:00:11.98#ibcon#*before return 0, iclass 39, count 0 2006.162.08:00:11.98#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:00:11.98#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:00:11.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.162.08:00:11.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.162.08:00:11.98$vc4f8/vb=1,4 2006.162.08:00:11.98#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.162.08:00:11.98#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.162.08:00:11.98#ibcon#ireg 11 cls_cnt 2 2006.162.08:00:11.98#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:00:11.98#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:00:11.98#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:00:11.98#ibcon#enter wrdev, iclass 3, count 2 2006.162.08:00:11.98#ibcon#first serial, iclass 3, count 2 2006.162.08:00:11.98#ibcon#enter sib2, iclass 3, count 2 2006.162.08:00:11.98#ibcon#flushed, iclass 3, count 2 2006.162.08:00:11.98#ibcon#about to write, iclass 3, count 2 2006.162.08:00:11.98#ibcon#wrote, iclass 3, count 2 2006.162.08:00:11.98#ibcon#about to read 3, iclass 3, count 2 2006.162.08:00:12.00#ibcon#read 3, iclass 3, count 2 2006.162.08:00:12.00#ibcon#about to read 4, iclass 3, count 2 2006.162.08:00:12.00#ibcon#read 4, iclass 3, count 2 2006.162.08:00:12.00#ibcon#about to read 5, iclass 3, count 2 2006.162.08:00:12.00#ibcon#read 5, iclass 3, count 2 2006.162.08:00:12.00#ibcon#about to read 6, iclass 3, count 2 2006.162.08:00:12.00#ibcon#read 6, iclass 3, count 2 2006.162.08:00:12.00#ibcon#end of sib2, iclass 3, count 2 2006.162.08:00:12.00#ibcon#*mode == 0, iclass 3, count 2 2006.162.08:00:12.00#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.162.08:00:12.00#ibcon#[27=AT01-04\r\n] 2006.162.08:00:12.00#ibcon#*before write, iclass 3, count 2 2006.162.08:00:12.00#ibcon#enter sib2, iclass 3, count 2 2006.162.08:00:12.00#ibcon#flushed, iclass 3, count 2 2006.162.08:00:12.00#ibcon#about to write, iclass 3, count 2 2006.162.08:00:12.00#ibcon#wrote, iclass 3, count 2 2006.162.08:00:12.00#ibcon#about to read 3, iclass 3, count 2 2006.162.08:00:12.03#ibcon#read 3, iclass 3, count 2 2006.162.08:00:12.03#ibcon#about to read 4, iclass 3, count 2 2006.162.08:00:12.03#ibcon#read 4, iclass 3, count 2 2006.162.08:00:12.03#ibcon#about to read 5, iclass 3, count 2 2006.162.08:00:12.03#ibcon#read 5, iclass 3, count 2 2006.162.08:00:12.03#ibcon#about to read 6, iclass 3, count 2 2006.162.08:00:12.03#ibcon#read 6, iclass 3, count 2 2006.162.08:00:12.03#ibcon#end of sib2, iclass 3, count 2 2006.162.08:00:12.03#ibcon#*after write, iclass 3, count 2 2006.162.08:00:12.03#ibcon#*before return 0, iclass 3, count 2 2006.162.08:00:12.03#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:00:12.03#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:00:12.03#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.162.08:00:12.03#ibcon#ireg 7 cls_cnt 0 2006.162.08:00:12.03#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:00:12.15#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:00:12.15#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:00:12.15#ibcon#enter wrdev, iclass 3, count 0 2006.162.08:00:12.15#ibcon#first serial, iclass 3, count 0 2006.162.08:00:12.15#ibcon#enter sib2, iclass 3, count 0 2006.162.08:00:12.15#ibcon#flushed, iclass 3, count 0 2006.162.08:00:12.15#ibcon#about to write, iclass 3, count 0 2006.162.08:00:12.15#ibcon#wrote, iclass 3, count 0 2006.162.08:00:12.15#ibcon#about to read 3, iclass 3, count 0 2006.162.08:00:12.17#ibcon#read 3, iclass 3, count 0 2006.162.08:00:12.17#ibcon#about to read 4, iclass 3, count 0 2006.162.08:00:12.17#ibcon#read 4, iclass 3, count 0 2006.162.08:00:12.17#ibcon#about to read 5, iclass 3, count 0 2006.162.08:00:12.17#ibcon#read 5, iclass 3, count 0 2006.162.08:00:12.17#ibcon#about to read 6, iclass 3, count 0 2006.162.08:00:12.17#ibcon#read 6, iclass 3, count 0 2006.162.08:00:12.17#ibcon#end of sib2, iclass 3, count 0 2006.162.08:00:12.17#ibcon#*mode == 0, iclass 3, count 0 2006.162.08:00:12.17#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.162.08:00:12.17#ibcon#[27=USB\r\n] 2006.162.08:00:12.17#ibcon#*before write, iclass 3, count 0 2006.162.08:00:12.17#ibcon#enter sib2, iclass 3, count 0 2006.162.08:00:12.17#ibcon#flushed, iclass 3, count 0 2006.162.08:00:12.17#ibcon#about to write, iclass 3, count 0 2006.162.08:00:12.17#ibcon#wrote, iclass 3, count 0 2006.162.08:00:12.17#ibcon#about to read 3, iclass 3, count 0 2006.162.08:00:12.20#ibcon#read 3, iclass 3, count 0 2006.162.08:00:12.20#ibcon#about to read 4, iclass 3, count 0 2006.162.08:00:12.20#ibcon#read 4, iclass 3, count 0 2006.162.08:00:12.20#ibcon#about to read 5, iclass 3, count 0 2006.162.08:00:12.20#ibcon#read 5, iclass 3, count 0 2006.162.08:00:12.20#ibcon#about to read 6, iclass 3, count 0 2006.162.08:00:12.20#ibcon#read 6, iclass 3, count 0 2006.162.08:00:12.20#ibcon#end of sib2, iclass 3, count 0 2006.162.08:00:12.20#ibcon#*after write, iclass 3, count 0 2006.162.08:00:12.20#ibcon#*before return 0, iclass 3, count 0 2006.162.08:00:12.20#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:00:12.20#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:00:12.20#ibcon#about to clear, iclass 3 cls_cnt 0 2006.162.08:00:12.20#ibcon#cleared, iclass 3 cls_cnt 0 2006.162.08:00:12.20$vc4f8/vblo=2,640.99 2006.162.08:00:12.20#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.162.08:00:12.20#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.162.08:00:12.20#ibcon#ireg 17 cls_cnt 0 2006.162.08:00:12.20#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:00:12.20#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:00:12.20#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:00:12.20#ibcon#enter wrdev, iclass 5, count 0 2006.162.08:00:12.20#ibcon#first serial, iclass 5, count 0 2006.162.08:00:12.20#ibcon#enter sib2, iclass 5, count 0 2006.162.08:00:12.20#ibcon#flushed, iclass 5, count 0 2006.162.08:00:12.20#ibcon#about to write, iclass 5, count 0 2006.162.08:00:12.20#ibcon#wrote, iclass 5, count 0 2006.162.08:00:12.20#ibcon#about to read 3, iclass 5, count 0 2006.162.08:00:12.22#ibcon#read 3, iclass 5, count 0 2006.162.08:00:12.22#ibcon#about to read 4, iclass 5, count 0 2006.162.08:00:12.22#ibcon#read 4, iclass 5, count 0 2006.162.08:00:12.22#ibcon#about to read 5, iclass 5, count 0 2006.162.08:00:12.22#ibcon#read 5, iclass 5, count 0 2006.162.08:00:12.22#ibcon#about to read 6, iclass 5, count 0 2006.162.08:00:12.22#ibcon#read 6, iclass 5, count 0 2006.162.08:00:12.22#ibcon#end of sib2, iclass 5, count 0 2006.162.08:00:12.22#ibcon#*mode == 0, iclass 5, count 0 2006.162.08:00:12.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.162.08:00:12.22#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.08:00:12.22#ibcon#*before write, iclass 5, count 0 2006.162.08:00:12.22#ibcon#enter sib2, iclass 5, count 0 2006.162.08:00:12.22#ibcon#flushed, iclass 5, count 0 2006.162.08:00:12.22#ibcon#about to write, iclass 5, count 0 2006.162.08:00:12.22#ibcon#wrote, iclass 5, count 0 2006.162.08:00:12.22#ibcon#about to read 3, iclass 5, count 0 2006.162.08:00:12.26#ibcon#read 3, iclass 5, count 0 2006.162.08:00:12.26#ibcon#about to read 4, iclass 5, count 0 2006.162.08:00:12.26#ibcon#read 4, iclass 5, count 0 2006.162.08:00:12.26#ibcon#about to read 5, iclass 5, count 0 2006.162.08:00:12.26#ibcon#read 5, iclass 5, count 0 2006.162.08:00:12.26#ibcon#about to read 6, iclass 5, count 0 2006.162.08:00:12.26#ibcon#read 6, iclass 5, count 0 2006.162.08:00:12.26#ibcon#end of sib2, iclass 5, count 0 2006.162.08:00:12.26#ibcon#*after write, iclass 5, count 0 2006.162.08:00:12.26#ibcon#*before return 0, iclass 5, count 0 2006.162.08:00:12.26#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:00:12.26#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:00:12.26#ibcon#about to clear, iclass 5 cls_cnt 0 2006.162.08:00:12.26#ibcon#cleared, iclass 5 cls_cnt 0 2006.162.08:00:12.26$vc4f8/vb=2,4 2006.162.08:00:12.26#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.162.08:00:12.26#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.162.08:00:12.26#ibcon#ireg 11 cls_cnt 2 2006.162.08:00:12.26#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:00:12.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:00:12.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:00:12.32#ibcon#enter wrdev, iclass 7, count 2 2006.162.08:00:12.32#ibcon#first serial, iclass 7, count 2 2006.162.08:00:12.32#ibcon#enter sib2, iclass 7, count 2 2006.162.08:00:12.32#ibcon#flushed, iclass 7, count 2 2006.162.08:00:12.32#ibcon#about to write, iclass 7, count 2 2006.162.08:00:12.32#ibcon#wrote, iclass 7, count 2 2006.162.08:00:12.32#ibcon#about to read 3, iclass 7, count 2 2006.162.08:00:12.34#ibcon#read 3, iclass 7, count 2 2006.162.08:00:12.34#ibcon#about to read 4, iclass 7, count 2 2006.162.08:00:12.34#ibcon#read 4, iclass 7, count 2 2006.162.08:00:12.34#ibcon#about to read 5, iclass 7, count 2 2006.162.08:00:12.34#ibcon#read 5, iclass 7, count 2 2006.162.08:00:12.34#ibcon#about to read 6, iclass 7, count 2 2006.162.08:00:12.34#ibcon#read 6, iclass 7, count 2 2006.162.08:00:12.34#ibcon#end of sib2, iclass 7, count 2 2006.162.08:00:12.34#ibcon#*mode == 0, iclass 7, count 2 2006.162.08:00:12.34#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.162.08:00:12.34#ibcon#[27=AT02-04\r\n] 2006.162.08:00:12.34#ibcon#*before write, iclass 7, count 2 2006.162.08:00:12.34#ibcon#enter sib2, iclass 7, count 2 2006.162.08:00:12.34#ibcon#flushed, iclass 7, count 2 2006.162.08:00:12.34#ibcon#about to write, iclass 7, count 2 2006.162.08:00:12.34#ibcon#wrote, iclass 7, count 2 2006.162.08:00:12.34#ibcon#about to read 3, iclass 7, count 2 2006.162.08:00:12.37#ibcon#read 3, iclass 7, count 2 2006.162.08:00:12.37#ibcon#about to read 4, iclass 7, count 2 2006.162.08:00:12.37#ibcon#read 4, iclass 7, count 2 2006.162.08:00:12.37#ibcon#about to read 5, iclass 7, count 2 2006.162.08:00:12.37#ibcon#read 5, iclass 7, count 2 2006.162.08:00:12.37#ibcon#about to read 6, iclass 7, count 2 2006.162.08:00:12.37#ibcon#read 6, iclass 7, count 2 2006.162.08:00:12.37#ibcon#end of sib2, iclass 7, count 2 2006.162.08:00:12.37#ibcon#*after write, iclass 7, count 2 2006.162.08:00:12.37#ibcon#*before return 0, iclass 7, count 2 2006.162.08:00:12.37#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:00:12.37#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:00:12.37#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.162.08:00:12.37#ibcon#ireg 7 cls_cnt 0 2006.162.08:00:12.37#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:00:12.49#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:00:12.49#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:00:12.49#ibcon#enter wrdev, iclass 7, count 0 2006.162.08:00:12.49#ibcon#first serial, iclass 7, count 0 2006.162.08:00:12.49#ibcon#enter sib2, iclass 7, count 0 2006.162.08:00:12.49#ibcon#flushed, iclass 7, count 0 2006.162.08:00:12.49#ibcon#about to write, iclass 7, count 0 2006.162.08:00:12.49#ibcon#wrote, iclass 7, count 0 2006.162.08:00:12.49#ibcon#about to read 3, iclass 7, count 0 2006.162.08:00:12.51#ibcon#read 3, iclass 7, count 0 2006.162.08:00:12.51#ibcon#about to read 4, iclass 7, count 0 2006.162.08:00:12.51#ibcon#read 4, iclass 7, count 0 2006.162.08:00:12.51#ibcon#about to read 5, iclass 7, count 0 2006.162.08:00:12.51#ibcon#read 5, iclass 7, count 0 2006.162.08:00:12.51#ibcon#about to read 6, iclass 7, count 0 2006.162.08:00:12.51#ibcon#read 6, iclass 7, count 0 2006.162.08:00:12.51#ibcon#end of sib2, iclass 7, count 0 2006.162.08:00:12.51#ibcon#*mode == 0, iclass 7, count 0 2006.162.08:00:12.51#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.162.08:00:12.51#ibcon#[27=USB\r\n] 2006.162.08:00:12.51#ibcon#*before write, iclass 7, count 0 2006.162.08:00:12.51#ibcon#enter sib2, iclass 7, count 0 2006.162.08:00:12.51#ibcon#flushed, iclass 7, count 0 2006.162.08:00:12.51#ibcon#about to write, iclass 7, count 0 2006.162.08:00:12.51#ibcon#wrote, iclass 7, count 0 2006.162.08:00:12.51#ibcon#about to read 3, iclass 7, count 0 2006.162.08:00:12.54#ibcon#read 3, iclass 7, count 0 2006.162.08:00:12.54#ibcon#about to read 4, iclass 7, count 0 2006.162.08:00:12.54#ibcon#read 4, iclass 7, count 0 2006.162.08:00:12.54#ibcon#about to read 5, iclass 7, count 0 2006.162.08:00:12.54#ibcon#read 5, iclass 7, count 0 2006.162.08:00:12.54#ibcon#about to read 6, iclass 7, count 0 2006.162.08:00:12.54#ibcon#read 6, iclass 7, count 0 2006.162.08:00:12.54#ibcon#end of sib2, iclass 7, count 0 2006.162.08:00:12.54#ibcon#*after write, iclass 7, count 0 2006.162.08:00:12.54#ibcon#*before return 0, iclass 7, count 0 2006.162.08:00:12.54#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:00:12.54#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:00:12.54#ibcon#about to clear, iclass 7 cls_cnt 0 2006.162.08:00:12.54#ibcon#cleared, iclass 7 cls_cnt 0 2006.162.08:00:12.54$vc4f8/vblo=3,656.99 2006.162.08:00:12.54#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.162.08:00:12.54#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.162.08:00:12.54#ibcon#ireg 17 cls_cnt 0 2006.162.08:00:12.54#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:00:12.54#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:00:12.54#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:00:12.54#ibcon#enter wrdev, iclass 11, count 0 2006.162.08:00:12.54#ibcon#first serial, iclass 11, count 0 2006.162.08:00:12.54#ibcon#enter sib2, iclass 11, count 0 2006.162.08:00:12.54#ibcon#flushed, iclass 11, count 0 2006.162.08:00:12.54#ibcon#about to write, iclass 11, count 0 2006.162.08:00:12.54#ibcon#wrote, iclass 11, count 0 2006.162.08:00:12.54#ibcon#about to read 3, iclass 11, count 0 2006.162.08:00:12.56#ibcon#read 3, iclass 11, count 0 2006.162.08:00:12.56#ibcon#about to read 4, iclass 11, count 0 2006.162.08:00:12.56#ibcon#read 4, iclass 11, count 0 2006.162.08:00:12.56#ibcon#about to read 5, iclass 11, count 0 2006.162.08:00:12.56#ibcon#read 5, iclass 11, count 0 2006.162.08:00:12.56#ibcon#about to read 6, iclass 11, count 0 2006.162.08:00:12.56#ibcon#read 6, iclass 11, count 0 2006.162.08:00:12.56#ibcon#end of sib2, iclass 11, count 0 2006.162.08:00:12.56#ibcon#*mode == 0, iclass 11, count 0 2006.162.08:00:12.56#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.162.08:00:12.56#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.08:00:12.56#ibcon#*before write, iclass 11, count 0 2006.162.08:00:12.56#ibcon#enter sib2, iclass 11, count 0 2006.162.08:00:12.56#ibcon#flushed, iclass 11, count 0 2006.162.08:00:12.56#ibcon#about to write, iclass 11, count 0 2006.162.08:00:12.56#ibcon#wrote, iclass 11, count 0 2006.162.08:00:12.56#ibcon#about to read 3, iclass 11, count 0 2006.162.08:00:12.60#ibcon#read 3, iclass 11, count 0 2006.162.08:00:12.60#ibcon#about to read 4, iclass 11, count 0 2006.162.08:00:12.60#ibcon#read 4, iclass 11, count 0 2006.162.08:00:12.60#ibcon#about to read 5, iclass 11, count 0 2006.162.08:00:12.60#ibcon#read 5, iclass 11, count 0 2006.162.08:00:12.60#ibcon#about to read 6, iclass 11, count 0 2006.162.08:00:12.60#ibcon#read 6, iclass 11, count 0 2006.162.08:00:12.60#ibcon#end of sib2, iclass 11, count 0 2006.162.08:00:12.60#ibcon#*after write, iclass 11, count 0 2006.162.08:00:12.60#ibcon#*before return 0, iclass 11, count 0 2006.162.08:00:12.60#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:00:12.60#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:00:12.60#ibcon#about to clear, iclass 11 cls_cnt 0 2006.162.08:00:12.60#ibcon#cleared, iclass 11 cls_cnt 0 2006.162.08:00:12.60$vc4f8/vb=3,4 2006.162.08:00:12.60#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.162.08:00:12.60#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.162.08:00:12.60#ibcon#ireg 11 cls_cnt 2 2006.162.08:00:12.60#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:00:12.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:00:12.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:00:12.66#ibcon#enter wrdev, iclass 13, count 2 2006.162.08:00:12.66#ibcon#first serial, iclass 13, count 2 2006.162.08:00:12.66#ibcon#enter sib2, iclass 13, count 2 2006.162.08:00:12.66#ibcon#flushed, iclass 13, count 2 2006.162.08:00:12.66#ibcon#about to write, iclass 13, count 2 2006.162.08:00:12.66#ibcon#wrote, iclass 13, count 2 2006.162.08:00:12.66#ibcon#about to read 3, iclass 13, count 2 2006.162.08:00:12.68#ibcon#read 3, iclass 13, count 2 2006.162.08:00:12.68#ibcon#about to read 4, iclass 13, count 2 2006.162.08:00:12.68#ibcon#read 4, iclass 13, count 2 2006.162.08:00:12.68#ibcon#about to read 5, iclass 13, count 2 2006.162.08:00:12.68#ibcon#read 5, iclass 13, count 2 2006.162.08:00:12.68#ibcon#about to read 6, iclass 13, count 2 2006.162.08:00:12.68#ibcon#read 6, iclass 13, count 2 2006.162.08:00:12.68#ibcon#end of sib2, iclass 13, count 2 2006.162.08:00:12.68#ibcon#*mode == 0, iclass 13, count 2 2006.162.08:00:12.68#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.162.08:00:12.68#ibcon#[27=AT03-04\r\n] 2006.162.08:00:12.68#ibcon#*before write, iclass 13, count 2 2006.162.08:00:12.68#ibcon#enter sib2, iclass 13, count 2 2006.162.08:00:12.68#ibcon#flushed, iclass 13, count 2 2006.162.08:00:12.68#ibcon#about to write, iclass 13, count 2 2006.162.08:00:12.68#ibcon#wrote, iclass 13, count 2 2006.162.08:00:12.68#ibcon#about to read 3, iclass 13, count 2 2006.162.08:00:12.71#ibcon#read 3, iclass 13, count 2 2006.162.08:00:12.71#ibcon#about to read 4, iclass 13, count 2 2006.162.08:00:12.71#ibcon#read 4, iclass 13, count 2 2006.162.08:00:12.71#ibcon#about to read 5, iclass 13, count 2 2006.162.08:00:12.71#ibcon#read 5, iclass 13, count 2 2006.162.08:00:12.71#ibcon#about to read 6, iclass 13, count 2 2006.162.08:00:12.71#ibcon#read 6, iclass 13, count 2 2006.162.08:00:12.71#ibcon#end of sib2, iclass 13, count 2 2006.162.08:00:12.71#ibcon#*after write, iclass 13, count 2 2006.162.08:00:12.71#ibcon#*before return 0, iclass 13, count 2 2006.162.08:00:12.71#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:00:12.71#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:00:12.71#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.162.08:00:12.71#ibcon#ireg 7 cls_cnt 0 2006.162.08:00:12.71#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:00:12.83#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:00:12.83#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:00:12.83#ibcon#enter wrdev, iclass 13, count 0 2006.162.08:00:12.83#ibcon#first serial, iclass 13, count 0 2006.162.08:00:12.83#ibcon#enter sib2, iclass 13, count 0 2006.162.08:00:12.83#ibcon#flushed, iclass 13, count 0 2006.162.08:00:12.83#ibcon#about to write, iclass 13, count 0 2006.162.08:00:12.83#ibcon#wrote, iclass 13, count 0 2006.162.08:00:12.83#ibcon#about to read 3, iclass 13, count 0 2006.162.08:00:12.85#ibcon#read 3, iclass 13, count 0 2006.162.08:00:12.85#ibcon#about to read 4, iclass 13, count 0 2006.162.08:00:12.85#ibcon#read 4, iclass 13, count 0 2006.162.08:00:12.85#ibcon#about to read 5, iclass 13, count 0 2006.162.08:00:12.85#ibcon#read 5, iclass 13, count 0 2006.162.08:00:12.85#ibcon#about to read 6, iclass 13, count 0 2006.162.08:00:12.85#ibcon#read 6, iclass 13, count 0 2006.162.08:00:12.85#ibcon#end of sib2, iclass 13, count 0 2006.162.08:00:12.85#ibcon#*mode == 0, iclass 13, count 0 2006.162.08:00:12.85#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.162.08:00:12.85#ibcon#[27=USB\r\n] 2006.162.08:00:12.85#ibcon#*before write, iclass 13, count 0 2006.162.08:00:12.85#ibcon#enter sib2, iclass 13, count 0 2006.162.08:00:12.85#ibcon#flushed, iclass 13, count 0 2006.162.08:00:12.85#ibcon#about to write, iclass 13, count 0 2006.162.08:00:12.85#ibcon#wrote, iclass 13, count 0 2006.162.08:00:12.85#ibcon#about to read 3, iclass 13, count 0 2006.162.08:00:12.88#ibcon#read 3, iclass 13, count 0 2006.162.08:00:12.88#ibcon#about to read 4, iclass 13, count 0 2006.162.08:00:12.88#ibcon#read 4, iclass 13, count 0 2006.162.08:00:12.88#ibcon#about to read 5, iclass 13, count 0 2006.162.08:00:12.88#ibcon#read 5, iclass 13, count 0 2006.162.08:00:12.88#ibcon#about to read 6, iclass 13, count 0 2006.162.08:00:12.88#ibcon#read 6, iclass 13, count 0 2006.162.08:00:12.88#ibcon#end of sib2, iclass 13, count 0 2006.162.08:00:12.88#ibcon#*after write, iclass 13, count 0 2006.162.08:00:12.88#ibcon#*before return 0, iclass 13, count 0 2006.162.08:00:12.88#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:00:12.88#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:00:12.88#ibcon#about to clear, iclass 13 cls_cnt 0 2006.162.08:00:12.88#ibcon#cleared, iclass 13 cls_cnt 0 2006.162.08:00:12.88$vc4f8/vblo=4,712.99 2006.162.08:00:12.88#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.162.08:00:12.88#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.162.08:00:12.88#ibcon#ireg 17 cls_cnt 0 2006.162.08:00:12.88#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:00:12.88#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:00:12.88#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:00:12.88#ibcon#enter wrdev, iclass 15, count 0 2006.162.08:00:12.88#ibcon#first serial, iclass 15, count 0 2006.162.08:00:12.88#ibcon#enter sib2, iclass 15, count 0 2006.162.08:00:12.88#ibcon#flushed, iclass 15, count 0 2006.162.08:00:12.88#ibcon#about to write, iclass 15, count 0 2006.162.08:00:12.88#ibcon#wrote, iclass 15, count 0 2006.162.08:00:12.88#ibcon#about to read 3, iclass 15, count 0 2006.162.08:00:12.90#ibcon#read 3, iclass 15, count 0 2006.162.08:00:12.90#ibcon#about to read 4, iclass 15, count 0 2006.162.08:00:12.90#ibcon#read 4, iclass 15, count 0 2006.162.08:00:12.90#ibcon#about to read 5, iclass 15, count 0 2006.162.08:00:12.90#ibcon#read 5, iclass 15, count 0 2006.162.08:00:12.90#ibcon#about to read 6, iclass 15, count 0 2006.162.08:00:12.90#ibcon#read 6, iclass 15, count 0 2006.162.08:00:12.90#ibcon#end of sib2, iclass 15, count 0 2006.162.08:00:12.90#ibcon#*mode == 0, iclass 15, count 0 2006.162.08:00:12.90#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.162.08:00:12.90#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.08:00:12.90#ibcon#*before write, iclass 15, count 0 2006.162.08:00:12.90#ibcon#enter sib2, iclass 15, count 0 2006.162.08:00:12.90#ibcon#flushed, iclass 15, count 0 2006.162.08:00:12.90#ibcon#about to write, iclass 15, count 0 2006.162.08:00:12.90#ibcon#wrote, iclass 15, count 0 2006.162.08:00:12.90#ibcon#about to read 3, iclass 15, count 0 2006.162.08:00:12.94#ibcon#read 3, iclass 15, count 0 2006.162.08:00:12.94#ibcon#about to read 4, iclass 15, count 0 2006.162.08:00:12.94#ibcon#read 4, iclass 15, count 0 2006.162.08:00:12.94#ibcon#about to read 5, iclass 15, count 0 2006.162.08:00:12.94#ibcon#read 5, iclass 15, count 0 2006.162.08:00:12.94#ibcon#about to read 6, iclass 15, count 0 2006.162.08:00:12.94#ibcon#read 6, iclass 15, count 0 2006.162.08:00:12.94#ibcon#end of sib2, iclass 15, count 0 2006.162.08:00:12.94#ibcon#*after write, iclass 15, count 0 2006.162.08:00:12.94#ibcon#*before return 0, iclass 15, count 0 2006.162.08:00:12.94#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:00:12.94#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:00:12.94#ibcon#about to clear, iclass 15 cls_cnt 0 2006.162.08:00:12.94#ibcon#cleared, iclass 15 cls_cnt 0 2006.162.08:00:12.94$vc4f8/vb=4,4 2006.162.08:00:12.94#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.162.08:00:12.94#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.162.08:00:12.94#ibcon#ireg 11 cls_cnt 2 2006.162.08:00:12.94#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:00:13.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:00:13.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:00:13.00#ibcon#enter wrdev, iclass 17, count 2 2006.162.08:00:13.00#ibcon#first serial, iclass 17, count 2 2006.162.08:00:13.00#ibcon#enter sib2, iclass 17, count 2 2006.162.08:00:13.00#ibcon#flushed, iclass 17, count 2 2006.162.08:00:13.00#ibcon#about to write, iclass 17, count 2 2006.162.08:00:13.00#ibcon#wrote, iclass 17, count 2 2006.162.08:00:13.00#ibcon#about to read 3, iclass 17, count 2 2006.162.08:00:13.02#ibcon#read 3, iclass 17, count 2 2006.162.08:00:13.02#ibcon#about to read 4, iclass 17, count 2 2006.162.08:00:13.02#ibcon#read 4, iclass 17, count 2 2006.162.08:00:13.02#ibcon#about to read 5, iclass 17, count 2 2006.162.08:00:13.02#ibcon#read 5, iclass 17, count 2 2006.162.08:00:13.02#ibcon#about to read 6, iclass 17, count 2 2006.162.08:00:13.02#ibcon#read 6, iclass 17, count 2 2006.162.08:00:13.02#ibcon#end of sib2, iclass 17, count 2 2006.162.08:00:13.02#ibcon#*mode == 0, iclass 17, count 2 2006.162.08:00:13.02#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.162.08:00:13.02#ibcon#[27=AT04-04\r\n] 2006.162.08:00:13.02#ibcon#*before write, iclass 17, count 2 2006.162.08:00:13.02#ibcon#enter sib2, iclass 17, count 2 2006.162.08:00:13.02#ibcon#flushed, iclass 17, count 2 2006.162.08:00:13.02#ibcon#about to write, iclass 17, count 2 2006.162.08:00:13.02#ibcon#wrote, iclass 17, count 2 2006.162.08:00:13.02#ibcon#about to read 3, iclass 17, count 2 2006.162.08:00:13.05#ibcon#read 3, iclass 17, count 2 2006.162.08:00:13.05#ibcon#about to read 4, iclass 17, count 2 2006.162.08:00:13.05#ibcon#read 4, iclass 17, count 2 2006.162.08:00:13.05#ibcon#about to read 5, iclass 17, count 2 2006.162.08:00:13.05#ibcon#read 5, iclass 17, count 2 2006.162.08:00:13.05#ibcon#about to read 6, iclass 17, count 2 2006.162.08:00:13.05#ibcon#read 6, iclass 17, count 2 2006.162.08:00:13.05#ibcon#end of sib2, iclass 17, count 2 2006.162.08:00:13.05#ibcon#*after write, iclass 17, count 2 2006.162.08:00:13.05#ibcon#*before return 0, iclass 17, count 2 2006.162.08:00:13.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:00:13.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:00:13.05#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.162.08:00:13.05#ibcon#ireg 7 cls_cnt 0 2006.162.08:00:13.05#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:00:13.17#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:00:13.17#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:00:13.17#ibcon#enter wrdev, iclass 17, count 0 2006.162.08:00:13.17#ibcon#first serial, iclass 17, count 0 2006.162.08:00:13.17#ibcon#enter sib2, iclass 17, count 0 2006.162.08:00:13.17#ibcon#flushed, iclass 17, count 0 2006.162.08:00:13.17#ibcon#about to write, iclass 17, count 0 2006.162.08:00:13.17#ibcon#wrote, iclass 17, count 0 2006.162.08:00:13.17#ibcon#about to read 3, iclass 17, count 0 2006.162.08:00:13.19#ibcon#read 3, iclass 17, count 0 2006.162.08:00:13.19#ibcon#about to read 4, iclass 17, count 0 2006.162.08:00:13.19#ibcon#read 4, iclass 17, count 0 2006.162.08:00:13.19#ibcon#about to read 5, iclass 17, count 0 2006.162.08:00:13.19#ibcon#read 5, iclass 17, count 0 2006.162.08:00:13.19#ibcon#about to read 6, iclass 17, count 0 2006.162.08:00:13.19#ibcon#read 6, iclass 17, count 0 2006.162.08:00:13.19#ibcon#end of sib2, iclass 17, count 0 2006.162.08:00:13.19#ibcon#*mode == 0, iclass 17, count 0 2006.162.08:00:13.19#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.162.08:00:13.19#ibcon#[27=USB\r\n] 2006.162.08:00:13.19#ibcon#*before write, iclass 17, count 0 2006.162.08:00:13.19#ibcon#enter sib2, iclass 17, count 0 2006.162.08:00:13.19#ibcon#flushed, iclass 17, count 0 2006.162.08:00:13.19#ibcon#about to write, iclass 17, count 0 2006.162.08:00:13.19#ibcon#wrote, iclass 17, count 0 2006.162.08:00:13.19#ibcon#about to read 3, iclass 17, count 0 2006.162.08:00:13.22#ibcon#read 3, iclass 17, count 0 2006.162.08:00:13.22#ibcon#about to read 4, iclass 17, count 0 2006.162.08:00:13.22#ibcon#read 4, iclass 17, count 0 2006.162.08:00:13.22#ibcon#about to read 5, iclass 17, count 0 2006.162.08:00:13.22#ibcon#read 5, iclass 17, count 0 2006.162.08:00:13.22#ibcon#about to read 6, iclass 17, count 0 2006.162.08:00:13.22#ibcon#read 6, iclass 17, count 0 2006.162.08:00:13.22#ibcon#end of sib2, iclass 17, count 0 2006.162.08:00:13.22#ibcon#*after write, iclass 17, count 0 2006.162.08:00:13.22#ibcon#*before return 0, iclass 17, count 0 2006.162.08:00:13.22#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:00:13.22#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:00:13.22#ibcon#about to clear, iclass 17 cls_cnt 0 2006.162.08:00:13.22#ibcon#cleared, iclass 17 cls_cnt 0 2006.162.08:00:13.22$vc4f8/vblo=5,744.99 2006.162.08:00:13.22#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.162.08:00:13.22#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.162.08:00:13.22#ibcon#ireg 17 cls_cnt 0 2006.162.08:00:13.22#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:00:13.22#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:00:13.22#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:00:13.22#ibcon#enter wrdev, iclass 19, count 0 2006.162.08:00:13.22#ibcon#first serial, iclass 19, count 0 2006.162.08:00:13.22#ibcon#enter sib2, iclass 19, count 0 2006.162.08:00:13.22#ibcon#flushed, iclass 19, count 0 2006.162.08:00:13.22#ibcon#about to write, iclass 19, count 0 2006.162.08:00:13.22#ibcon#wrote, iclass 19, count 0 2006.162.08:00:13.22#ibcon#about to read 3, iclass 19, count 0 2006.162.08:00:13.24#ibcon#read 3, iclass 19, count 0 2006.162.08:00:13.24#ibcon#about to read 4, iclass 19, count 0 2006.162.08:00:13.24#ibcon#read 4, iclass 19, count 0 2006.162.08:00:13.24#ibcon#about to read 5, iclass 19, count 0 2006.162.08:00:13.24#ibcon#read 5, iclass 19, count 0 2006.162.08:00:13.24#ibcon#about to read 6, iclass 19, count 0 2006.162.08:00:13.24#ibcon#read 6, iclass 19, count 0 2006.162.08:00:13.24#ibcon#end of sib2, iclass 19, count 0 2006.162.08:00:13.24#ibcon#*mode == 0, iclass 19, count 0 2006.162.08:00:13.24#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.162.08:00:13.24#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.08:00:13.24#ibcon#*before write, iclass 19, count 0 2006.162.08:00:13.24#ibcon#enter sib2, iclass 19, count 0 2006.162.08:00:13.24#ibcon#flushed, iclass 19, count 0 2006.162.08:00:13.24#ibcon#about to write, iclass 19, count 0 2006.162.08:00:13.24#ibcon#wrote, iclass 19, count 0 2006.162.08:00:13.24#ibcon#about to read 3, iclass 19, count 0 2006.162.08:00:13.28#ibcon#read 3, iclass 19, count 0 2006.162.08:00:13.28#ibcon#about to read 4, iclass 19, count 0 2006.162.08:00:13.28#ibcon#read 4, iclass 19, count 0 2006.162.08:00:13.28#ibcon#about to read 5, iclass 19, count 0 2006.162.08:00:13.28#ibcon#read 5, iclass 19, count 0 2006.162.08:00:13.28#ibcon#about to read 6, iclass 19, count 0 2006.162.08:00:13.28#ibcon#read 6, iclass 19, count 0 2006.162.08:00:13.28#ibcon#end of sib2, iclass 19, count 0 2006.162.08:00:13.28#ibcon#*after write, iclass 19, count 0 2006.162.08:00:13.28#ibcon#*before return 0, iclass 19, count 0 2006.162.08:00:13.28#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:00:13.28#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:00:13.28#ibcon#about to clear, iclass 19 cls_cnt 0 2006.162.08:00:13.28#ibcon#cleared, iclass 19 cls_cnt 0 2006.162.08:00:13.28$vc4f8/vb=5,4 2006.162.08:00:13.28#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.162.08:00:13.28#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.162.08:00:13.28#ibcon#ireg 11 cls_cnt 2 2006.162.08:00:13.28#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.162.08:00:13.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.162.08:00:13.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.162.08:00:13.34#ibcon#enter wrdev, iclass 21, count 2 2006.162.08:00:13.34#ibcon#first serial, iclass 21, count 2 2006.162.08:00:13.34#ibcon#enter sib2, iclass 21, count 2 2006.162.08:00:13.34#ibcon#flushed, iclass 21, count 2 2006.162.08:00:13.34#ibcon#about to write, iclass 21, count 2 2006.162.08:00:13.34#ibcon#wrote, iclass 21, count 2 2006.162.08:00:13.34#ibcon#about to read 3, iclass 21, count 2 2006.162.08:00:13.36#ibcon#read 3, iclass 21, count 2 2006.162.08:00:13.36#ibcon#about to read 4, iclass 21, count 2 2006.162.08:00:13.36#ibcon#read 4, iclass 21, count 2 2006.162.08:00:13.36#ibcon#about to read 5, iclass 21, count 2 2006.162.08:00:13.36#ibcon#read 5, iclass 21, count 2 2006.162.08:00:13.36#ibcon#about to read 6, iclass 21, count 2 2006.162.08:00:13.36#ibcon#read 6, iclass 21, count 2 2006.162.08:00:13.36#ibcon#end of sib2, iclass 21, count 2 2006.162.08:00:13.36#ibcon#*mode == 0, iclass 21, count 2 2006.162.08:00:13.36#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.162.08:00:13.36#ibcon#[27=AT05-04\r\n] 2006.162.08:00:13.36#ibcon#*before write, iclass 21, count 2 2006.162.08:00:13.36#ibcon#enter sib2, iclass 21, count 2 2006.162.08:00:13.36#ibcon#flushed, iclass 21, count 2 2006.162.08:00:13.36#ibcon#about to write, iclass 21, count 2 2006.162.08:00:13.36#ibcon#wrote, iclass 21, count 2 2006.162.08:00:13.36#ibcon#about to read 3, iclass 21, count 2 2006.162.08:00:13.39#ibcon#read 3, iclass 21, count 2 2006.162.08:00:13.39#ibcon#about to read 4, iclass 21, count 2 2006.162.08:00:13.39#ibcon#read 4, iclass 21, count 2 2006.162.08:00:13.39#ibcon#about to read 5, iclass 21, count 2 2006.162.08:00:13.39#ibcon#read 5, iclass 21, count 2 2006.162.08:00:13.39#ibcon#about to read 6, iclass 21, count 2 2006.162.08:00:13.39#ibcon#read 6, iclass 21, count 2 2006.162.08:00:13.39#ibcon#end of sib2, iclass 21, count 2 2006.162.08:00:13.39#ibcon#*after write, iclass 21, count 2 2006.162.08:00:13.39#ibcon#*before return 0, iclass 21, count 2 2006.162.08:00:13.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.162.08:00:13.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.162.08:00:13.39#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.162.08:00:13.39#ibcon#ireg 7 cls_cnt 0 2006.162.08:00:13.39#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.162.08:00:13.51#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.162.08:00:13.51#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.162.08:00:13.51#ibcon#enter wrdev, iclass 21, count 0 2006.162.08:00:13.51#ibcon#first serial, iclass 21, count 0 2006.162.08:00:13.51#ibcon#enter sib2, iclass 21, count 0 2006.162.08:00:13.51#ibcon#flushed, iclass 21, count 0 2006.162.08:00:13.51#ibcon#about to write, iclass 21, count 0 2006.162.08:00:13.51#ibcon#wrote, iclass 21, count 0 2006.162.08:00:13.51#ibcon#about to read 3, iclass 21, count 0 2006.162.08:00:13.53#ibcon#read 3, iclass 21, count 0 2006.162.08:00:13.53#ibcon#about to read 4, iclass 21, count 0 2006.162.08:00:13.53#ibcon#read 4, iclass 21, count 0 2006.162.08:00:13.53#ibcon#about to read 5, iclass 21, count 0 2006.162.08:00:13.53#ibcon#read 5, iclass 21, count 0 2006.162.08:00:13.53#ibcon#about to read 6, iclass 21, count 0 2006.162.08:00:13.53#ibcon#read 6, iclass 21, count 0 2006.162.08:00:13.53#ibcon#end of sib2, iclass 21, count 0 2006.162.08:00:13.53#ibcon#*mode == 0, iclass 21, count 0 2006.162.08:00:13.53#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.162.08:00:13.53#ibcon#[27=USB\r\n] 2006.162.08:00:13.53#ibcon#*before write, iclass 21, count 0 2006.162.08:00:13.53#ibcon#enter sib2, iclass 21, count 0 2006.162.08:00:13.53#ibcon#flushed, iclass 21, count 0 2006.162.08:00:13.53#ibcon#about to write, iclass 21, count 0 2006.162.08:00:13.53#ibcon#wrote, iclass 21, count 0 2006.162.08:00:13.53#ibcon#about to read 3, iclass 21, count 0 2006.162.08:00:13.56#ibcon#read 3, iclass 21, count 0 2006.162.08:00:13.56#ibcon#about to read 4, iclass 21, count 0 2006.162.08:00:13.56#ibcon#read 4, iclass 21, count 0 2006.162.08:00:13.56#ibcon#about to read 5, iclass 21, count 0 2006.162.08:00:13.56#ibcon#read 5, iclass 21, count 0 2006.162.08:00:13.56#ibcon#about to read 6, iclass 21, count 0 2006.162.08:00:13.56#ibcon#read 6, iclass 21, count 0 2006.162.08:00:13.56#ibcon#end of sib2, iclass 21, count 0 2006.162.08:00:13.56#ibcon#*after write, iclass 21, count 0 2006.162.08:00:13.56#ibcon#*before return 0, iclass 21, count 0 2006.162.08:00:13.56#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.162.08:00:13.56#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.162.08:00:13.56#ibcon#about to clear, iclass 21 cls_cnt 0 2006.162.08:00:13.56#ibcon#cleared, iclass 21 cls_cnt 0 2006.162.08:00:13.56$vc4f8/vblo=6,752.99 2006.162.08:00:13.56#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.162.08:00:13.56#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.162.08:00:13.56#ibcon#ireg 17 cls_cnt 0 2006.162.08:00:13.56#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.162.08:00:13.56#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.162.08:00:13.56#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.162.08:00:13.56#ibcon#enter wrdev, iclass 23, count 0 2006.162.08:00:13.56#ibcon#first serial, iclass 23, count 0 2006.162.08:00:13.56#ibcon#enter sib2, iclass 23, count 0 2006.162.08:00:13.56#ibcon#flushed, iclass 23, count 0 2006.162.08:00:13.56#ibcon#about to write, iclass 23, count 0 2006.162.08:00:13.56#ibcon#wrote, iclass 23, count 0 2006.162.08:00:13.56#ibcon#about to read 3, iclass 23, count 0 2006.162.08:00:13.58#ibcon#read 3, iclass 23, count 0 2006.162.08:00:13.58#ibcon#about to read 4, iclass 23, count 0 2006.162.08:00:13.58#ibcon#read 4, iclass 23, count 0 2006.162.08:00:13.58#ibcon#about to read 5, iclass 23, count 0 2006.162.08:00:13.58#ibcon#read 5, iclass 23, count 0 2006.162.08:00:13.58#ibcon#about to read 6, iclass 23, count 0 2006.162.08:00:13.58#ibcon#read 6, iclass 23, count 0 2006.162.08:00:13.58#ibcon#end of sib2, iclass 23, count 0 2006.162.08:00:13.58#ibcon#*mode == 0, iclass 23, count 0 2006.162.08:00:13.58#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.162.08:00:13.58#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.08:00:13.58#ibcon#*before write, iclass 23, count 0 2006.162.08:00:13.58#ibcon#enter sib2, iclass 23, count 0 2006.162.08:00:13.58#ibcon#flushed, iclass 23, count 0 2006.162.08:00:13.58#ibcon#about to write, iclass 23, count 0 2006.162.08:00:13.58#ibcon#wrote, iclass 23, count 0 2006.162.08:00:13.58#ibcon#about to read 3, iclass 23, count 0 2006.162.08:00:13.62#ibcon#read 3, iclass 23, count 0 2006.162.08:00:13.62#ibcon#about to read 4, iclass 23, count 0 2006.162.08:00:13.62#ibcon#read 4, iclass 23, count 0 2006.162.08:00:13.62#ibcon#about to read 5, iclass 23, count 0 2006.162.08:00:13.62#ibcon#read 5, iclass 23, count 0 2006.162.08:00:13.62#ibcon#about to read 6, iclass 23, count 0 2006.162.08:00:13.62#ibcon#read 6, iclass 23, count 0 2006.162.08:00:13.62#ibcon#end of sib2, iclass 23, count 0 2006.162.08:00:13.62#ibcon#*after write, iclass 23, count 0 2006.162.08:00:13.62#ibcon#*before return 0, iclass 23, count 0 2006.162.08:00:13.62#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.162.08:00:13.62#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.162.08:00:13.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.162.08:00:13.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.162.08:00:13.62$vc4f8/vb=6,4 2006.162.08:00:13.62#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.162.08:00:13.62#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.162.08:00:13.62#ibcon#ireg 11 cls_cnt 2 2006.162.08:00:13.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.162.08:00:13.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.162.08:00:13.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.162.08:00:13.68#ibcon#enter wrdev, iclass 25, count 2 2006.162.08:00:13.68#ibcon#first serial, iclass 25, count 2 2006.162.08:00:13.68#ibcon#enter sib2, iclass 25, count 2 2006.162.08:00:13.68#ibcon#flushed, iclass 25, count 2 2006.162.08:00:13.68#ibcon#about to write, iclass 25, count 2 2006.162.08:00:13.68#ibcon#wrote, iclass 25, count 2 2006.162.08:00:13.68#ibcon#about to read 3, iclass 25, count 2 2006.162.08:00:13.70#ibcon#read 3, iclass 25, count 2 2006.162.08:00:13.70#ibcon#about to read 4, iclass 25, count 2 2006.162.08:00:13.70#ibcon#read 4, iclass 25, count 2 2006.162.08:00:13.70#ibcon#about to read 5, iclass 25, count 2 2006.162.08:00:13.70#ibcon#read 5, iclass 25, count 2 2006.162.08:00:13.70#ibcon#about to read 6, iclass 25, count 2 2006.162.08:00:13.70#ibcon#read 6, iclass 25, count 2 2006.162.08:00:13.70#ibcon#end of sib2, iclass 25, count 2 2006.162.08:00:13.70#ibcon#*mode == 0, iclass 25, count 2 2006.162.08:00:13.70#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.162.08:00:13.70#ibcon#[27=AT06-04\r\n] 2006.162.08:00:13.70#ibcon#*before write, iclass 25, count 2 2006.162.08:00:13.70#ibcon#enter sib2, iclass 25, count 2 2006.162.08:00:13.70#ibcon#flushed, iclass 25, count 2 2006.162.08:00:13.70#ibcon#about to write, iclass 25, count 2 2006.162.08:00:13.70#ibcon#wrote, iclass 25, count 2 2006.162.08:00:13.70#ibcon#about to read 3, iclass 25, count 2 2006.162.08:00:13.73#ibcon#read 3, iclass 25, count 2 2006.162.08:00:13.73#ibcon#about to read 4, iclass 25, count 2 2006.162.08:00:13.73#ibcon#read 4, iclass 25, count 2 2006.162.08:00:13.73#ibcon#about to read 5, iclass 25, count 2 2006.162.08:00:13.73#ibcon#read 5, iclass 25, count 2 2006.162.08:00:13.73#ibcon#about to read 6, iclass 25, count 2 2006.162.08:00:13.73#ibcon#read 6, iclass 25, count 2 2006.162.08:00:13.73#ibcon#end of sib2, iclass 25, count 2 2006.162.08:00:13.73#ibcon#*after write, iclass 25, count 2 2006.162.08:00:13.73#ibcon#*before return 0, iclass 25, count 2 2006.162.08:00:13.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.162.08:00:13.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.162.08:00:13.73#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.162.08:00:13.73#ibcon#ireg 7 cls_cnt 0 2006.162.08:00:13.73#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.162.08:00:13.85#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.162.08:00:13.85#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.162.08:00:13.85#ibcon#enter wrdev, iclass 25, count 0 2006.162.08:00:13.85#ibcon#first serial, iclass 25, count 0 2006.162.08:00:13.85#ibcon#enter sib2, iclass 25, count 0 2006.162.08:00:13.85#ibcon#flushed, iclass 25, count 0 2006.162.08:00:13.85#ibcon#about to write, iclass 25, count 0 2006.162.08:00:13.85#ibcon#wrote, iclass 25, count 0 2006.162.08:00:13.85#ibcon#about to read 3, iclass 25, count 0 2006.162.08:00:13.87#ibcon#read 3, iclass 25, count 0 2006.162.08:00:13.87#ibcon#about to read 4, iclass 25, count 0 2006.162.08:00:13.87#ibcon#read 4, iclass 25, count 0 2006.162.08:00:13.87#ibcon#about to read 5, iclass 25, count 0 2006.162.08:00:13.87#ibcon#read 5, iclass 25, count 0 2006.162.08:00:13.87#ibcon#about to read 6, iclass 25, count 0 2006.162.08:00:13.87#ibcon#read 6, iclass 25, count 0 2006.162.08:00:13.87#ibcon#end of sib2, iclass 25, count 0 2006.162.08:00:13.87#ibcon#*mode == 0, iclass 25, count 0 2006.162.08:00:13.87#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.162.08:00:13.87#ibcon#[27=USB\r\n] 2006.162.08:00:13.87#ibcon#*before write, iclass 25, count 0 2006.162.08:00:13.87#ibcon#enter sib2, iclass 25, count 0 2006.162.08:00:13.87#ibcon#flushed, iclass 25, count 0 2006.162.08:00:13.87#ibcon#about to write, iclass 25, count 0 2006.162.08:00:13.87#ibcon#wrote, iclass 25, count 0 2006.162.08:00:13.87#ibcon#about to read 3, iclass 25, count 0 2006.162.08:00:13.90#ibcon#read 3, iclass 25, count 0 2006.162.08:00:13.90#ibcon#about to read 4, iclass 25, count 0 2006.162.08:00:13.90#ibcon#read 4, iclass 25, count 0 2006.162.08:00:13.90#ibcon#about to read 5, iclass 25, count 0 2006.162.08:00:13.90#ibcon#read 5, iclass 25, count 0 2006.162.08:00:13.90#ibcon#about to read 6, iclass 25, count 0 2006.162.08:00:13.90#ibcon#read 6, iclass 25, count 0 2006.162.08:00:13.90#ibcon#end of sib2, iclass 25, count 0 2006.162.08:00:13.90#ibcon#*after write, iclass 25, count 0 2006.162.08:00:13.90#ibcon#*before return 0, iclass 25, count 0 2006.162.08:00:13.90#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.162.08:00:13.90#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.162.08:00:13.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.162.08:00:13.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.162.08:00:13.90$vc4f8/vabw=wide 2006.162.08:00:13.90#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.162.08:00:13.90#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.162.08:00:13.90#ibcon#ireg 8 cls_cnt 0 2006.162.08:00:13.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.162.08:00:13.90#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.162.08:00:13.90#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.162.08:00:13.90#ibcon#enter wrdev, iclass 27, count 0 2006.162.08:00:13.90#ibcon#first serial, iclass 27, count 0 2006.162.08:00:13.90#ibcon#enter sib2, iclass 27, count 0 2006.162.08:00:13.90#ibcon#flushed, iclass 27, count 0 2006.162.08:00:13.90#ibcon#about to write, iclass 27, count 0 2006.162.08:00:13.90#ibcon#wrote, iclass 27, count 0 2006.162.08:00:13.90#ibcon#about to read 3, iclass 27, count 0 2006.162.08:00:13.92#ibcon#read 3, iclass 27, count 0 2006.162.08:00:13.92#ibcon#about to read 4, iclass 27, count 0 2006.162.08:00:13.92#ibcon#read 4, iclass 27, count 0 2006.162.08:00:13.92#ibcon#about to read 5, iclass 27, count 0 2006.162.08:00:13.92#ibcon#read 5, iclass 27, count 0 2006.162.08:00:13.92#ibcon#about to read 6, iclass 27, count 0 2006.162.08:00:13.92#ibcon#read 6, iclass 27, count 0 2006.162.08:00:13.92#ibcon#end of sib2, iclass 27, count 0 2006.162.08:00:13.92#ibcon#*mode == 0, iclass 27, count 0 2006.162.08:00:13.92#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.162.08:00:13.92#ibcon#[25=BW32\r\n] 2006.162.08:00:13.92#ibcon#*before write, iclass 27, count 0 2006.162.08:00:13.92#ibcon#enter sib2, iclass 27, count 0 2006.162.08:00:13.92#ibcon#flushed, iclass 27, count 0 2006.162.08:00:13.92#ibcon#about to write, iclass 27, count 0 2006.162.08:00:13.92#ibcon#wrote, iclass 27, count 0 2006.162.08:00:13.92#ibcon#about to read 3, iclass 27, count 0 2006.162.08:00:13.95#ibcon#read 3, iclass 27, count 0 2006.162.08:00:13.95#ibcon#about to read 4, iclass 27, count 0 2006.162.08:00:13.95#ibcon#read 4, iclass 27, count 0 2006.162.08:00:13.95#ibcon#about to read 5, iclass 27, count 0 2006.162.08:00:13.95#ibcon#read 5, iclass 27, count 0 2006.162.08:00:13.95#ibcon#about to read 6, iclass 27, count 0 2006.162.08:00:13.95#ibcon#read 6, iclass 27, count 0 2006.162.08:00:13.95#ibcon#end of sib2, iclass 27, count 0 2006.162.08:00:13.95#ibcon#*after write, iclass 27, count 0 2006.162.08:00:13.95#ibcon#*before return 0, iclass 27, count 0 2006.162.08:00:13.95#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.162.08:00:13.95#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.162.08:00:13.95#ibcon#about to clear, iclass 27 cls_cnt 0 2006.162.08:00:13.95#ibcon#cleared, iclass 27 cls_cnt 0 2006.162.08:00:13.95$vc4f8/vbbw=wide 2006.162.08:00:13.95#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.162.08:00:13.95#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.162.08:00:13.95#ibcon#ireg 8 cls_cnt 0 2006.162.08:00:13.95#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:00:14.02#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:00:14.02#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:00:14.02#ibcon#enter wrdev, iclass 29, count 0 2006.162.08:00:14.02#ibcon#first serial, iclass 29, count 0 2006.162.08:00:14.02#ibcon#enter sib2, iclass 29, count 0 2006.162.08:00:14.02#ibcon#flushed, iclass 29, count 0 2006.162.08:00:14.02#ibcon#about to write, iclass 29, count 0 2006.162.08:00:14.02#ibcon#wrote, iclass 29, count 0 2006.162.08:00:14.02#ibcon#about to read 3, iclass 29, count 0 2006.162.08:00:14.04#ibcon#read 3, iclass 29, count 0 2006.162.08:00:14.04#ibcon#about to read 4, iclass 29, count 0 2006.162.08:00:14.04#ibcon#read 4, iclass 29, count 0 2006.162.08:00:14.04#ibcon#about to read 5, iclass 29, count 0 2006.162.08:00:14.04#ibcon#read 5, iclass 29, count 0 2006.162.08:00:14.04#ibcon#about to read 6, iclass 29, count 0 2006.162.08:00:14.04#ibcon#read 6, iclass 29, count 0 2006.162.08:00:14.04#ibcon#end of sib2, iclass 29, count 0 2006.162.08:00:14.04#ibcon#*mode == 0, iclass 29, count 0 2006.162.08:00:14.04#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.162.08:00:14.04#ibcon#[27=BW32\r\n] 2006.162.08:00:14.04#ibcon#*before write, iclass 29, count 0 2006.162.08:00:14.04#ibcon#enter sib2, iclass 29, count 0 2006.162.08:00:14.04#ibcon#flushed, iclass 29, count 0 2006.162.08:00:14.04#ibcon#about to write, iclass 29, count 0 2006.162.08:00:14.04#ibcon#wrote, iclass 29, count 0 2006.162.08:00:14.04#ibcon#about to read 3, iclass 29, count 0 2006.162.08:00:14.07#ibcon#read 3, iclass 29, count 0 2006.162.08:00:14.07#ibcon#about to read 4, iclass 29, count 0 2006.162.08:00:14.07#ibcon#read 4, iclass 29, count 0 2006.162.08:00:14.07#ibcon#about to read 5, iclass 29, count 0 2006.162.08:00:14.07#ibcon#read 5, iclass 29, count 0 2006.162.08:00:14.07#ibcon#about to read 6, iclass 29, count 0 2006.162.08:00:14.07#ibcon#read 6, iclass 29, count 0 2006.162.08:00:14.07#ibcon#end of sib2, iclass 29, count 0 2006.162.08:00:14.07#ibcon#*after write, iclass 29, count 0 2006.162.08:00:14.07#ibcon#*before return 0, iclass 29, count 0 2006.162.08:00:14.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:00:14.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:00:14.07#ibcon#about to clear, iclass 29 cls_cnt 0 2006.162.08:00:14.07#ibcon#cleared, iclass 29 cls_cnt 0 2006.162.08:00:14.07$4f8m12a/ifd4f 2006.162.08:00:14.07$ifd4f/lo= 2006.162.08:00:14.07$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.08:00:14.07$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.08:00:14.07$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.08:00:14.07$ifd4f/patch= 2006.162.08:00:14.07$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.08:00:14.07$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.08:00:14.07$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.08:00:14.08$4f8m12a/"form=m,16.000,1:2 2006.162.08:00:14.08$4f8m12a/"tpicd 2006.162.08:00:14.08$4f8m12a/echo=off 2006.162.08:00:14.08$4f8m12a/xlog=off 2006.162.08:00:14.08:!2006.162.08:01:20 2006.162.08:00:58.14#trakl#Source acquired 2006.162.08:01:00.14#flagr#flagr/antenna,acquired 2006.162.08:01:20.01:preob 2006.162.08:01:21.14/onsource/TRACKING 2006.162.08:01:21.14:!2006.162.08:01:30 2006.162.08:01:30.00:data_valid=on 2006.162.08:01:30.00:midob 2006.162.08:01:30.14/onsource/TRACKING 2006.162.08:01:30.14/wx/17.87,1007.0,100 2006.162.08:01:30.36/cable/+6.5370E-03 2006.162.08:01:31.45/va/01,08,usb,yes,36,38 2006.162.08:01:31.45/va/02,07,usb,yes,36,38 2006.162.08:01:31.45/va/03,06,usb,yes,38,38 2006.162.08:01:31.45/va/04,07,usb,yes,37,40 2006.162.08:01:31.45/va/05,07,usb,yes,39,41 2006.162.08:01:31.45/va/06,06,usb,yes,39,38 2006.162.08:01:31.45/va/07,06,usb,yes,39,39 2006.162.08:01:31.45/va/08,07,usb,yes,37,36 2006.162.08:01:31.68/valo/01,532.99,yes,locked 2006.162.08:01:31.68/valo/02,572.99,yes,locked 2006.162.08:01:31.68/valo/03,672.99,yes,locked 2006.162.08:01:31.68/valo/04,832.99,yes,locked 2006.162.08:01:31.68/valo/05,652.99,yes,locked 2006.162.08:01:31.68/valo/06,772.99,yes,locked 2006.162.08:01:31.68/valo/07,832.99,yes,locked 2006.162.08:01:31.68/valo/08,852.99,yes,locked 2006.162.08:01:32.77/vb/01,04,usb,yes,29,28 2006.162.08:01:32.77/vb/02,04,usb,yes,31,32 2006.162.08:01:32.77/vb/03,04,usb,yes,27,31 2006.162.08:01:32.77/vb/04,04,usb,yes,28,28 2006.162.08:01:32.77/vb/05,04,usb,yes,27,30 2006.162.08:01:32.77/vb/06,04,usb,yes,28,30 2006.162.08:01:32.77/vb/07,04,usb,yes,29,29 2006.162.08:01:32.77/vb/08,04,usb,yes,27,30 2006.162.08:01:33.01/vblo/01,632.99,yes,locked 2006.162.08:01:33.01/vblo/02,640.99,yes,locked 2006.162.08:01:33.01/vblo/03,656.99,yes,locked 2006.162.08:01:33.01/vblo/04,712.99,yes,locked 2006.162.08:01:33.01/vblo/05,744.99,yes,locked 2006.162.08:01:33.01/vblo/06,752.99,yes,locked 2006.162.08:01:33.01/vblo/07,734.99,yes,locked 2006.162.08:01:33.01/vblo/08,744.99,yes,locked 2006.162.08:01:33.16/vabw/8 2006.162.08:01:33.31/vbbw/8 2006.162.08:01:33.40/xfe/off,on,14.7 2006.162.08:01:33.78/ifatt/23,28,28,28 2006.162.08:01:34.08/fmout-gps/S +4.49E-07 2006.162.08:01:34.12:!2006.162.08:02:30 2006.162.08:02:30.01:data_valid=off 2006.162.08:02:30.02:postob 2006.162.08:02:30.09/cable/+6.5370E-03 2006.162.08:02:30.09/wx/17.86,1007.0,100 2006.162.08:02:31.08/fmout-gps/S +4.48E-07 2006.162.08:02:31.09:scan_name=162-0803,k06162,60 2006.162.08:02:31.09:source=0743+259,074625.87,254902.1,2000.0,ccw 2006.162.08:02:32.14#flagr#flagr/antenna,new-source 2006.162.08:02:32.14:checkk5 2006.162.08:02:32.57/chk_autoobs//k5ts1/ autoobs is running! 2006.162.08:02:33.01/chk_autoobs//k5ts2/ autoobs is running! 2006.162.08:02:33.68/chk_autoobs//k5ts3/ autoobs is running! 2006.162.08:02:34.11/chk_autoobs//k5ts4/ autoobs is running! 2006.162.08:02:34.53/chk_obsdata//k5ts1/T1620801??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:02:34.90/chk_obsdata//k5ts2/T1620801??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:02:35.31/chk_obsdata//k5ts3/T1620801??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:02:35.75/chk_obsdata//k5ts4/T1620801??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:02:37.00/k5log//k5ts1_log_newline 2006.162.08:02:38.05/k5log//k5ts2_log_newline 2006.162.08:02:41.85/k5log//k5ts3_log_newline 2006.162.08:02:42.61/k5log//k5ts4_log_newline 2006.162.08:02:42.64/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.08:02:42.64:4f8m12a=2 2006.162.08:02:42.64$4f8m12a/echo=on 2006.162.08:02:42.64$4f8m12a/pcalon 2006.162.08:02:42.64$pcalon/"no phase cal control is implemented here 2006.162.08:02:42.64$4f8m12a/"tpicd=stop 2006.162.08:02:42.64$4f8m12a/vc4f8 2006.162.08:02:42.64$vc4f8/valo=1,532.99 2006.162.08:02:42.65#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.162.08:02:42.65#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.162.08:02:42.65#ibcon#ireg 17 cls_cnt 0 2006.162.08:02:42.65#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:02:42.65#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:02:42.65#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:02:42.65#ibcon#enter wrdev, iclass 16, count 0 2006.162.08:02:42.65#ibcon#first serial, iclass 16, count 0 2006.162.08:02:42.65#ibcon#enter sib2, iclass 16, count 0 2006.162.08:02:42.65#ibcon#flushed, iclass 16, count 0 2006.162.08:02:42.65#ibcon#about to write, iclass 16, count 0 2006.162.08:02:42.65#ibcon#wrote, iclass 16, count 0 2006.162.08:02:42.65#ibcon#about to read 3, iclass 16, count 0 2006.162.08:02:42.68#ibcon#read 3, iclass 16, count 0 2006.162.08:02:42.68#ibcon#about to read 4, iclass 16, count 0 2006.162.08:02:42.68#ibcon#read 4, iclass 16, count 0 2006.162.08:02:42.68#ibcon#about to read 5, iclass 16, count 0 2006.162.08:02:42.68#ibcon#read 5, iclass 16, count 0 2006.162.08:02:42.68#ibcon#about to read 6, iclass 16, count 0 2006.162.08:02:42.68#ibcon#read 6, iclass 16, count 0 2006.162.08:02:42.68#ibcon#end of sib2, iclass 16, count 0 2006.162.08:02:42.68#ibcon#*mode == 0, iclass 16, count 0 2006.162.08:02:42.68#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.162.08:02:42.68#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.08:02:42.68#ibcon#*before write, iclass 16, count 0 2006.162.08:02:42.68#ibcon#enter sib2, iclass 16, count 0 2006.162.08:02:42.68#ibcon#flushed, iclass 16, count 0 2006.162.08:02:42.69#ibcon#about to write, iclass 16, count 0 2006.162.08:02:42.69#ibcon#wrote, iclass 16, count 0 2006.162.08:02:42.69#ibcon#about to read 3, iclass 16, count 0 2006.162.08:02:42.73#ibcon#read 3, iclass 16, count 0 2006.162.08:02:42.73#ibcon#about to read 4, iclass 16, count 0 2006.162.08:02:42.73#ibcon#read 4, iclass 16, count 0 2006.162.08:02:42.73#ibcon#about to read 5, iclass 16, count 0 2006.162.08:02:42.73#ibcon#read 5, iclass 16, count 0 2006.162.08:02:42.73#ibcon#about to read 6, iclass 16, count 0 2006.162.08:02:42.73#ibcon#read 6, iclass 16, count 0 2006.162.08:02:42.73#ibcon#end of sib2, iclass 16, count 0 2006.162.08:02:42.73#ibcon#*after write, iclass 16, count 0 2006.162.08:02:42.73#ibcon#*before return 0, iclass 16, count 0 2006.162.08:02:42.73#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:02:42.73#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:02:42.73#ibcon#about to clear, iclass 16 cls_cnt 0 2006.162.08:02:42.73#ibcon#cleared, iclass 16 cls_cnt 0 2006.162.08:02:42.73$vc4f8/va=1,8 2006.162.08:02:42.73#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.162.08:02:42.73#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.162.08:02:42.73#ibcon#ireg 11 cls_cnt 2 2006.162.08:02:42.73#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:02:42.73#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:02:42.73#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:02:42.73#ibcon#enter wrdev, iclass 18, count 2 2006.162.08:02:42.73#ibcon#first serial, iclass 18, count 2 2006.162.08:02:42.73#ibcon#enter sib2, iclass 18, count 2 2006.162.08:02:42.73#ibcon#flushed, iclass 18, count 2 2006.162.08:02:42.73#ibcon#about to write, iclass 18, count 2 2006.162.08:02:42.73#ibcon#wrote, iclass 18, count 2 2006.162.08:02:42.73#ibcon#about to read 3, iclass 18, count 2 2006.162.08:02:42.76#ibcon#read 3, iclass 18, count 2 2006.162.08:02:42.76#ibcon#about to read 4, iclass 18, count 2 2006.162.08:02:42.76#ibcon#read 4, iclass 18, count 2 2006.162.08:02:42.76#ibcon#about to read 5, iclass 18, count 2 2006.162.08:02:42.76#ibcon#read 5, iclass 18, count 2 2006.162.08:02:42.76#ibcon#about to read 6, iclass 18, count 2 2006.162.08:02:42.76#ibcon#read 6, iclass 18, count 2 2006.162.08:02:42.76#ibcon#end of sib2, iclass 18, count 2 2006.162.08:02:42.76#ibcon#*mode == 0, iclass 18, count 2 2006.162.08:02:42.76#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.162.08:02:42.76#ibcon#[25=AT01-08\r\n] 2006.162.08:02:42.76#ibcon#*before write, iclass 18, count 2 2006.162.08:02:42.76#ibcon#enter sib2, iclass 18, count 2 2006.162.08:02:42.76#ibcon#flushed, iclass 18, count 2 2006.162.08:02:42.76#ibcon#about to write, iclass 18, count 2 2006.162.08:02:42.76#ibcon#wrote, iclass 18, count 2 2006.162.08:02:42.76#ibcon#about to read 3, iclass 18, count 2 2006.162.08:02:42.79#ibcon#read 3, iclass 18, count 2 2006.162.08:02:42.79#ibcon#about to read 4, iclass 18, count 2 2006.162.08:02:42.79#ibcon#read 4, iclass 18, count 2 2006.162.08:02:42.79#ibcon#about to read 5, iclass 18, count 2 2006.162.08:02:42.79#ibcon#read 5, iclass 18, count 2 2006.162.08:02:42.79#ibcon#about to read 6, iclass 18, count 2 2006.162.08:02:42.79#ibcon#read 6, iclass 18, count 2 2006.162.08:02:42.79#ibcon#end of sib2, iclass 18, count 2 2006.162.08:02:42.79#ibcon#*after write, iclass 18, count 2 2006.162.08:02:42.79#ibcon#*before return 0, iclass 18, count 2 2006.162.08:02:42.79#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:02:42.79#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:02:42.79#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.162.08:02:42.79#ibcon#ireg 7 cls_cnt 0 2006.162.08:02:42.79#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:02:42.91#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:02:42.91#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:02:42.91#ibcon#enter wrdev, iclass 18, count 0 2006.162.08:02:42.91#ibcon#first serial, iclass 18, count 0 2006.162.08:02:42.91#ibcon#enter sib2, iclass 18, count 0 2006.162.08:02:42.91#ibcon#flushed, iclass 18, count 0 2006.162.08:02:42.91#ibcon#about to write, iclass 18, count 0 2006.162.08:02:42.91#ibcon#wrote, iclass 18, count 0 2006.162.08:02:42.91#ibcon#about to read 3, iclass 18, count 0 2006.162.08:02:42.93#ibcon#read 3, iclass 18, count 0 2006.162.08:02:42.93#ibcon#about to read 4, iclass 18, count 0 2006.162.08:02:42.93#ibcon#read 4, iclass 18, count 0 2006.162.08:02:42.93#ibcon#about to read 5, iclass 18, count 0 2006.162.08:02:42.93#ibcon#read 5, iclass 18, count 0 2006.162.08:02:42.93#ibcon#about to read 6, iclass 18, count 0 2006.162.08:02:42.93#ibcon#read 6, iclass 18, count 0 2006.162.08:02:42.93#ibcon#end of sib2, iclass 18, count 0 2006.162.08:02:42.93#ibcon#*mode == 0, iclass 18, count 0 2006.162.08:02:42.93#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.162.08:02:42.93#ibcon#[25=USB\r\n] 2006.162.08:02:42.93#ibcon#*before write, iclass 18, count 0 2006.162.08:02:42.93#ibcon#enter sib2, iclass 18, count 0 2006.162.08:02:42.93#ibcon#flushed, iclass 18, count 0 2006.162.08:02:42.93#ibcon#about to write, iclass 18, count 0 2006.162.08:02:42.93#ibcon#wrote, iclass 18, count 0 2006.162.08:02:42.93#ibcon#about to read 3, iclass 18, count 0 2006.162.08:02:42.96#ibcon#read 3, iclass 18, count 0 2006.162.08:02:42.96#ibcon#about to read 4, iclass 18, count 0 2006.162.08:02:42.96#ibcon#read 4, iclass 18, count 0 2006.162.08:02:42.96#ibcon#about to read 5, iclass 18, count 0 2006.162.08:02:42.96#ibcon#read 5, iclass 18, count 0 2006.162.08:02:42.96#ibcon#about to read 6, iclass 18, count 0 2006.162.08:02:42.96#ibcon#read 6, iclass 18, count 0 2006.162.08:02:42.96#ibcon#end of sib2, iclass 18, count 0 2006.162.08:02:42.96#ibcon#*after write, iclass 18, count 0 2006.162.08:02:42.96#ibcon#*before return 0, iclass 18, count 0 2006.162.08:02:42.96#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:02:42.96#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:02:42.96#ibcon#about to clear, iclass 18 cls_cnt 0 2006.162.08:02:42.96#ibcon#cleared, iclass 18 cls_cnt 0 2006.162.08:02:42.96$vc4f8/valo=2,572.99 2006.162.08:02:42.96#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.162.08:02:42.96#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.162.08:02:42.96#ibcon#ireg 17 cls_cnt 0 2006.162.08:02:42.96#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:02:42.96#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:02:42.96#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:02:42.96#ibcon#enter wrdev, iclass 20, count 0 2006.162.08:02:42.96#ibcon#first serial, iclass 20, count 0 2006.162.08:02:42.96#ibcon#enter sib2, iclass 20, count 0 2006.162.08:02:42.96#ibcon#flushed, iclass 20, count 0 2006.162.08:02:42.96#ibcon#about to write, iclass 20, count 0 2006.162.08:02:42.96#ibcon#wrote, iclass 20, count 0 2006.162.08:02:42.96#ibcon#about to read 3, iclass 20, count 0 2006.162.08:02:42.98#ibcon#read 3, iclass 20, count 0 2006.162.08:02:42.98#ibcon#about to read 4, iclass 20, count 0 2006.162.08:02:42.98#ibcon#read 4, iclass 20, count 0 2006.162.08:02:42.98#ibcon#about to read 5, iclass 20, count 0 2006.162.08:02:42.98#ibcon#read 5, iclass 20, count 0 2006.162.08:02:42.98#ibcon#about to read 6, iclass 20, count 0 2006.162.08:02:42.98#ibcon#read 6, iclass 20, count 0 2006.162.08:02:42.98#ibcon#end of sib2, iclass 20, count 0 2006.162.08:02:42.98#ibcon#*mode == 0, iclass 20, count 0 2006.162.08:02:42.98#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.08:02:42.98#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.08:02:42.98#ibcon#*before write, iclass 20, count 0 2006.162.08:02:42.98#ibcon#enter sib2, iclass 20, count 0 2006.162.08:02:42.98#ibcon#flushed, iclass 20, count 0 2006.162.08:02:42.98#ibcon#about to write, iclass 20, count 0 2006.162.08:02:42.98#ibcon#wrote, iclass 20, count 0 2006.162.08:02:42.98#ibcon#about to read 3, iclass 20, count 0 2006.162.08:02:43.02#ibcon#read 3, iclass 20, count 0 2006.162.08:02:43.02#ibcon#about to read 4, iclass 20, count 0 2006.162.08:02:43.02#ibcon#read 4, iclass 20, count 0 2006.162.08:02:43.02#ibcon#about to read 5, iclass 20, count 0 2006.162.08:02:43.02#ibcon#read 5, iclass 20, count 0 2006.162.08:02:43.02#ibcon#about to read 6, iclass 20, count 0 2006.162.08:02:43.02#ibcon#read 6, iclass 20, count 0 2006.162.08:02:43.02#ibcon#end of sib2, iclass 20, count 0 2006.162.08:02:43.02#ibcon#*after write, iclass 20, count 0 2006.162.08:02:43.02#ibcon#*before return 0, iclass 20, count 0 2006.162.08:02:43.02#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:02:43.02#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:02:43.02#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.08:02:43.02#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.08:02:43.02$vc4f8/va=2,7 2006.162.08:02:43.02#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.162.08:02:43.02#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.162.08:02:43.02#ibcon#ireg 11 cls_cnt 2 2006.162.08:02:43.02#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:02:43.09#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:02:43.09#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:02:43.09#ibcon#enter wrdev, iclass 22, count 2 2006.162.08:02:43.09#ibcon#first serial, iclass 22, count 2 2006.162.08:02:43.09#ibcon#enter sib2, iclass 22, count 2 2006.162.08:02:43.09#ibcon#flushed, iclass 22, count 2 2006.162.08:02:43.09#ibcon#about to write, iclass 22, count 2 2006.162.08:02:43.09#ibcon#wrote, iclass 22, count 2 2006.162.08:02:43.09#ibcon#about to read 3, iclass 22, count 2 2006.162.08:02:43.11#ibcon#read 3, iclass 22, count 2 2006.162.08:02:43.11#ibcon#about to read 4, iclass 22, count 2 2006.162.08:02:43.11#ibcon#read 4, iclass 22, count 2 2006.162.08:02:43.11#ibcon#about to read 5, iclass 22, count 2 2006.162.08:02:43.11#ibcon#read 5, iclass 22, count 2 2006.162.08:02:43.11#ibcon#about to read 6, iclass 22, count 2 2006.162.08:02:43.11#ibcon#read 6, iclass 22, count 2 2006.162.08:02:43.11#ibcon#end of sib2, iclass 22, count 2 2006.162.08:02:43.11#ibcon#*mode == 0, iclass 22, count 2 2006.162.08:02:43.11#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.162.08:02:43.11#ibcon#[25=AT02-07\r\n] 2006.162.08:02:43.11#ibcon#*before write, iclass 22, count 2 2006.162.08:02:43.11#ibcon#enter sib2, iclass 22, count 2 2006.162.08:02:43.11#ibcon#flushed, iclass 22, count 2 2006.162.08:02:43.11#ibcon#about to write, iclass 22, count 2 2006.162.08:02:43.11#ibcon#wrote, iclass 22, count 2 2006.162.08:02:43.11#ibcon#about to read 3, iclass 22, count 2 2006.162.08:02:43.13#ibcon#read 3, iclass 22, count 2 2006.162.08:02:43.13#ibcon#about to read 4, iclass 22, count 2 2006.162.08:02:43.13#ibcon#read 4, iclass 22, count 2 2006.162.08:02:43.13#ibcon#about to read 5, iclass 22, count 2 2006.162.08:02:43.13#ibcon#read 5, iclass 22, count 2 2006.162.08:02:43.13#ibcon#about to read 6, iclass 22, count 2 2006.162.08:02:43.13#ibcon#read 6, iclass 22, count 2 2006.162.08:02:43.13#ibcon#end of sib2, iclass 22, count 2 2006.162.08:02:43.13#ibcon#*after write, iclass 22, count 2 2006.162.08:02:43.13#ibcon#*before return 0, iclass 22, count 2 2006.162.08:02:43.13#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:02:43.13#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:02:43.13#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.162.08:02:43.13#ibcon#ireg 7 cls_cnt 0 2006.162.08:02:43.13#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:02:43.25#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:02:43.25#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:02:43.25#ibcon#enter wrdev, iclass 22, count 0 2006.162.08:02:43.25#ibcon#first serial, iclass 22, count 0 2006.162.08:02:43.25#ibcon#enter sib2, iclass 22, count 0 2006.162.08:02:43.25#ibcon#flushed, iclass 22, count 0 2006.162.08:02:43.25#ibcon#about to write, iclass 22, count 0 2006.162.08:02:43.25#ibcon#wrote, iclass 22, count 0 2006.162.08:02:43.25#ibcon#about to read 3, iclass 22, count 0 2006.162.08:02:43.27#ibcon#read 3, iclass 22, count 0 2006.162.08:02:43.27#ibcon#about to read 4, iclass 22, count 0 2006.162.08:02:43.27#ibcon#read 4, iclass 22, count 0 2006.162.08:02:43.27#ibcon#about to read 5, iclass 22, count 0 2006.162.08:02:43.27#ibcon#read 5, iclass 22, count 0 2006.162.08:02:43.27#ibcon#about to read 6, iclass 22, count 0 2006.162.08:02:43.27#ibcon#read 6, iclass 22, count 0 2006.162.08:02:43.27#ibcon#end of sib2, iclass 22, count 0 2006.162.08:02:43.27#ibcon#*mode == 0, iclass 22, count 0 2006.162.08:02:43.27#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.08:02:43.27#ibcon#[25=USB\r\n] 2006.162.08:02:43.27#ibcon#*before write, iclass 22, count 0 2006.162.08:02:43.27#ibcon#enter sib2, iclass 22, count 0 2006.162.08:02:43.27#ibcon#flushed, iclass 22, count 0 2006.162.08:02:43.27#ibcon#about to write, iclass 22, count 0 2006.162.08:02:43.27#ibcon#wrote, iclass 22, count 0 2006.162.08:02:43.27#ibcon#about to read 3, iclass 22, count 0 2006.162.08:02:43.30#ibcon#read 3, iclass 22, count 0 2006.162.08:02:43.30#ibcon#about to read 4, iclass 22, count 0 2006.162.08:02:43.30#ibcon#read 4, iclass 22, count 0 2006.162.08:02:43.30#ibcon#about to read 5, iclass 22, count 0 2006.162.08:02:43.30#ibcon#read 5, iclass 22, count 0 2006.162.08:02:43.30#ibcon#about to read 6, iclass 22, count 0 2006.162.08:02:43.30#ibcon#read 6, iclass 22, count 0 2006.162.08:02:43.30#ibcon#end of sib2, iclass 22, count 0 2006.162.08:02:43.30#ibcon#*after write, iclass 22, count 0 2006.162.08:02:43.30#ibcon#*before return 0, iclass 22, count 0 2006.162.08:02:43.30#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:02:43.30#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:02:43.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.08:02:43.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.08:02:43.30$vc4f8/valo=3,672.99 2006.162.08:02:43.30#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.162.08:02:43.30#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.162.08:02:43.30#ibcon#ireg 17 cls_cnt 0 2006.162.08:02:43.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:02:43.30#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:02:43.30#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:02:43.30#ibcon#enter wrdev, iclass 24, count 0 2006.162.08:02:43.30#ibcon#first serial, iclass 24, count 0 2006.162.08:02:43.30#ibcon#enter sib2, iclass 24, count 0 2006.162.08:02:43.30#ibcon#flushed, iclass 24, count 0 2006.162.08:02:43.30#ibcon#about to write, iclass 24, count 0 2006.162.08:02:43.30#ibcon#wrote, iclass 24, count 0 2006.162.08:02:43.30#ibcon#about to read 3, iclass 24, count 0 2006.162.08:02:43.32#ibcon#read 3, iclass 24, count 0 2006.162.08:02:43.32#ibcon#about to read 4, iclass 24, count 0 2006.162.08:02:43.32#ibcon#read 4, iclass 24, count 0 2006.162.08:02:43.32#ibcon#about to read 5, iclass 24, count 0 2006.162.08:02:43.32#ibcon#read 5, iclass 24, count 0 2006.162.08:02:43.32#ibcon#about to read 6, iclass 24, count 0 2006.162.08:02:43.32#ibcon#read 6, iclass 24, count 0 2006.162.08:02:43.32#ibcon#end of sib2, iclass 24, count 0 2006.162.08:02:43.32#ibcon#*mode == 0, iclass 24, count 0 2006.162.08:02:43.32#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.08:02:43.32#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.08:02:43.32#ibcon#*before write, iclass 24, count 0 2006.162.08:02:43.32#ibcon#enter sib2, iclass 24, count 0 2006.162.08:02:43.32#ibcon#flushed, iclass 24, count 0 2006.162.08:02:43.32#ibcon#about to write, iclass 24, count 0 2006.162.08:02:43.32#ibcon#wrote, iclass 24, count 0 2006.162.08:02:43.32#ibcon#about to read 3, iclass 24, count 0 2006.162.08:02:43.36#ibcon#read 3, iclass 24, count 0 2006.162.08:02:43.36#ibcon#about to read 4, iclass 24, count 0 2006.162.08:02:43.36#ibcon#read 4, iclass 24, count 0 2006.162.08:02:43.36#ibcon#about to read 5, iclass 24, count 0 2006.162.08:02:43.36#ibcon#read 5, iclass 24, count 0 2006.162.08:02:43.36#ibcon#about to read 6, iclass 24, count 0 2006.162.08:02:43.36#ibcon#read 6, iclass 24, count 0 2006.162.08:02:43.36#ibcon#end of sib2, iclass 24, count 0 2006.162.08:02:43.36#ibcon#*after write, iclass 24, count 0 2006.162.08:02:43.36#ibcon#*before return 0, iclass 24, count 0 2006.162.08:02:43.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:02:43.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:02:43.36#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.08:02:43.36#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.08:02:43.36$vc4f8/va=3,6 2006.162.08:02:43.36#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.162.08:02:43.36#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.162.08:02:43.36#ibcon#ireg 11 cls_cnt 2 2006.162.08:02:43.36#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:02:43.43#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:02:43.43#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:02:43.43#ibcon#enter wrdev, iclass 26, count 2 2006.162.08:02:43.43#ibcon#first serial, iclass 26, count 2 2006.162.08:02:43.43#ibcon#enter sib2, iclass 26, count 2 2006.162.08:02:43.43#ibcon#flushed, iclass 26, count 2 2006.162.08:02:43.43#ibcon#about to write, iclass 26, count 2 2006.162.08:02:43.43#ibcon#wrote, iclass 26, count 2 2006.162.08:02:43.43#ibcon#about to read 3, iclass 26, count 2 2006.162.08:02:43.44#ibcon#read 3, iclass 26, count 2 2006.162.08:02:43.44#ibcon#about to read 4, iclass 26, count 2 2006.162.08:02:43.44#ibcon#read 4, iclass 26, count 2 2006.162.08:02:43.44#ibcon#about to read 5, iclass 26, count 2 2006.162.08:02:43.44#ibcon#read 5, iclass 26, count 2 2006.162.08:02:43.44#ibcon#about to read 6, iclass 26, count 2 2006.162.08:02:43.44#ibcon#read 6, iclass 26, count 2 2006.162.08:02:43.44#ibcon#end of sib2, iclass 26, count 2 2006.162.08:02:43.44#ibcon#*mode == 0, iclass 26, count 2 2006.162.08:02:43.44#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.162.08:02:43.44#ibcon#[25=AT03-06\r\n] 2006.162.08:02:43.44#ibcon#*before write, iclass 26, count 2 2006.162.08:02:43.44#ibcon#enter sib2, iclass 26, count 2 2006.162.08:02:43.44#ibcon#flushed, iclass 26, count 2 2006.162.08:02:43.44#ibcon#about to write, iclass 26, count 2 2006.162.08:02:43.44#ibcon#wrote, iclass 26, count 2 2006.162.08:02:43.44#ibcon#about to read 3, iclass 26, count 2 2006.162.08:02:43.47#ibcon#read 3, iclass 26, count 2 2006.162.08:02:43.47#ibcon#about to read 4, iclass 26, count 2 2006.162.08:02:43.47#ibcon#read 4, iclass 26, count 2 2006.162.08:02:43.47#ibcon#about to read 5, iclass 26, count 2 2006.162.08:02:43.47#ibcon#read 5, iclass 26, count 2 2006.162.08:02:43.47#ibcon#about to read 6, iclass 26, count 2 2006.162.08:02:43.47#ibcon#read 6, iclass 26, count 2 2006.162.08:02:43.47#ibcon#end of sib2, iclass 26, count 2 2006.162.08:02:43.47#ibcon#*after write, iclass 26, count 2 2006.162.08:02:43.47#ibcon#*before return 0, iclass 26, count 2 2006.162.08:02:43.47#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:02:43.47#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:02:43.47#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.162.08:02:43.47#ibcon#ireg 7 cls_cnt 0 2006.162.08:02:43.47#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:02:43.59#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:02:43.59#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:02:43.59#ibcon#enter wrdev, iclass 26, count 0 2006.162.08:02:43.59#ibcon#first serial, iclass 26, count 0 2006.162.08:02:43.59#ibcon#enter sib2, iclass 26, count 0 2006.162.08:02:43.59#ibcon#flushed, iclass 26, count 0 2006.162.08:02:43.59#ibcon#about to write, iclass 26, count 0 2006.162.08:02:43.59#ibcon#wrote, iclass 26, count 0 2006.162.08:02:43.59#ibcon#about to read 3, iclass 26, count 0 2006.162.08:02:43.61#ibcon#read 3, iclass 26, count 0 2006.162.08:02:43.61#ibcon#about to read 4, iclass 26, count 0 2006.162.08:02:43.61#ibcon#read 4, iclass 26, count 0 2006.162.08:02:43.61#ibcon#about to read 5, iclass 26, count 0 2006.162.08:02:43.61#ibcon#read 5, iclass 26, count 0 2006.162.08:02:43.61#ibcon#about to read 6, iclass 26, count 0 2006.162.08:02:43.61#ibcon#read 6, iclass 26, count 0 2006.162.08:02:43.61#ibcon#end of sib2, iclass 26, count 0 2006.162.08:02:43.61#ibcon#*mode == 0, iclass 26, count 0 2006.162.08:02:43.61#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.162.08:02:43.61#ibcon#[25=USB\r\n] 2006.162.08:02:43.61#ibcon#*before write, iclass 26, count 0 2006.162.08:02:43.61#ibcon#enter sib2, iclass 26, count 0 2006.162.08:02:43.61#ibcon#flushed, iclass 26, count 0 2006.162.08:02:43.61#ibcon#about to write, iclass 26, count 0 2006.162.08:02:43.61#ibcon#wrote, iclass 26, count 0 2006.162.08:02:43.61#ibcon#about to read 3, iclass 26, count 0 2006.162.08:02:43.64#ibcon#read 3, iclass 26, count 0 2006.162.08:02:43.64#ibcon#about to read 4, iclass 26, count 0 2006.162.08:02:43.64#ibcon#read 4, iclass 26, count 0 2006.162.08:02:43.64#ibcon#about to read 5, iclass 26, count 0 2006.162.08:02:43.64#ibcon#read 5, iclass 26, count 0 2006.162.08:02:43.64#ibcon#about to read 6, iclass 26, count 0 2006.162.08:02:43.64#ibcon#read 6, iclass 26, count 0 2006.162.08:02:43.64#ibcon#end of sib2, iclass 26, count 0 2006.162.08:02:43.64#ibcon#*after write, iclass 26, count 0 2006.162.08:02:43.64#ibcon#*before return 0, iclass 26, count 0 2006.162.08:02:43.64#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:02:43.64#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:02:43.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.162.08:02:43.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.162.08:02:43.64$vc4f8/valo=4,832.99 2006.162.08:02:43.64#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.162.08:02:43.64#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.162.08:02:43.64#ibcon#ireg 17 cls_cnt 0 2006.162.08:02:43.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:02:43.64#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:02:43.64#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:02:43.64#ibcon#enter wrdev, iclass 28, count 0 2006.162.08:02:43.64#ibcon#first serial, iclass 28, count 0 2006.162.08:02:43.64#ibcon#enter sib2, iclass 28, count 0 2006.162.08:02:43.64#ibcon#flushed, iclass 28, count 0 2006.162.08:02:43.64#ibcon#about to write, iclass 28, count 0 2006.162.08:02:43.64#ibcon#wrote, iclass 28, count 0 2006.162.08:02:43.64#ibcon#about to read 3, iclass 28, count 0 2006.162.08:02:43.66#ibcon#read 3, iclass 28, count 0 2006.162.08:02:43.66#ibcon#about to read 4, iclass 28, count 0 2006.162.08:02:43.66#ibcon#read 4, iclass 28, count 0 2006.162.08:02:43.66#ibcon#about to read 5, iclass 28, count 0 2006.162.08:02:43.66#ibcon#read 5, iclass 28, count 0 2006.162.08:02:43.66#ibcon#about to read 6, iclass 28, count 0 2006.162.08:02:43.66#ibcon#read 6, iclass 28, count 0 2006.162.08:02:43.66#ibcon#end of sib2, iclass 28, count 0 2006.162.08:02:43.66#ibcon#*mode == 0, iclass 28, count 0 2006.162.08:02:43.66#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.162.08:02:43.66#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.08:02:43.66#ibcon#*before write, iclass 28, count 0 2006.162.08:02:43.66#ibcon#enter sib2, iclass 28, count 0 2006.162.08:02:43.66#ibcon#flushed, iclass 28, count 0 2006.162.08:02:43.66#ibcon#about to write, iclass 28, count 0 2006.162.08:02:43.66#ibcon#wrote, iclass 28, count 0 2006.162.08:02:43.66#ibcon#about to read 3, iclass 28, count 0 2006.162.08:02:43.70#ibcon#read 3, iclass 28, count 0 2006.162.08:02:43.70#ibcon#about to read 4, iclass 28, count 0 2006.162.08:02:43.70#ibcon#read 4, iclass 28, count 0 2006.162.08:02:43.70#ibcon#about to read 5, iclass 28, count 0 2006.162.08:02:43.70#ibcon#read 5, iclass 28, count 0 2006.162.08:02:43.70#ibcon#about to read 6, iclass 28, count 0 2006.162.08:02:43.70#ibcon#read 6, iclass 28, count 0 2006.162.08:02:43.70#ibcon#end of sib2, iclass 28, count 0 2006.162.08:02:43.70#ibcon#*after write, iclass 28, count 0 2006.162.08:02:43.70#ibcon#*before return 0, iclass 28, count 0 2006.162.08:02:43.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:02:43.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:02:43.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.162.08:02:43.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.162.08:02:43.70$vc4f8/va=4,7 2006.162.08:02:43.70#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.162.08:02:43.70#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.162.08:02:43.70#ibcon#ireg 11 cls_cnt 2 2006.162.08:02:43.70#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:02:43.76#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:02:43.76#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:02:43.76#ibcon#enter wrdev, iclass 30, count 2 2006.162.08:02:43.76#ibcon#first serial, iclass 30, count 2 2006.162.08:02:43.76#ibcon#enter sib2, iclass 30, count 2 2006.162.08:02:43.76#ibcon#flushed, iclass 30, count 2 2006.162.08:02:43.76#ibcon#about to write, iclass 30, count 2 2006.162.08:02:43.76#ibcon#wrote, iclass 30, count 2 2006.162.08:02:43.76#ibcon#about to read 3, iclass 30, count 2 2006.162.08:02:43.78#ibcon#read 3, iclass 30, count 2 2006.162.08:02:43.78#ibcon#about to read 4, iclass 30, count 2 2006.162.08:02:43.78#ibcon#read 4, iclass 30, count 2 2006.162.08:02:43.78#ibcon#about to read 5, iclass 30, count 2 2006.162.08:02:43.78#ibcon#read 5, iclass 30, count 2 2006.162.08:02:43.78#ibcon#about to read 6, iclass 30, count 2 2006.162.08:02:43.78#ibcon#read 6, iclass 30, count 2 2006.162.08:02:43.78#ibcon#end of sib2, iclass 30, count 2 2006.162.08:02:43.78#ibcon#*mode == 0, iclass 30, count 2 2006.162.08:02:43.78#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.162.08:02:43.78#ibcon#[25=AT04-07\r\n] 2006.162.08:02:43.78#ibcon#*before write, iclass 30, count 2 2006.162.08:02:43.78#ibcon#enter sib2, iclass 30, count 2 2006.162.08:02:43.78#ibcon#flushed, iclass 30, count 2 2006.162.08:02:43.78#ibcon#about to write, iclass 30, count 2 2006.162.08:02:43.78#ibcon#wrote, iclass 30, count 2 2006.162.08:02:43.78#ibcon#about to read 3, iclass 30, count 2 2006.162.08:02:43.81#ibcon#read 3, iclass 30, count 2 2006.162.08:02:43.81#ibcon#about to read 4, iclass 30, count 2 2006.162.08:02:43.81#ibcon#read 4, iclass 30, count 2 2006.162.08:02:43.81#ibcon#about to read 5, iclass 30, count 2 2006.162.08:02:43.81#ibcon#read 5, iclass 30, count 2 2006.162.08:02:43.81#ibcon#about to read 6, iclass 30, count 2 2006.162.08:02:43.81#ibcon#read 6, iclass 30, count 2 2006.162.08:02:43.81#ibcon#end of sib2, iclass 30, count 2 2006.162.08:02:43.81#ibcon#*after write, iclass 30, count 2 2006.162.08:02:43.81#ibcon#*before return 0, iclass 30, count 2 2006.162.08:02:43.81#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:02:43.81#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:02:43.81#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.162.08:02:43.81#ibcon#ireg 7 cls_cnt 0 2006.162.08:02:43.81#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:02:43.93#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:02:43.93#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:02:43.93#ibcon#enter wrdev, iclass 30, count 0 2006.162.08:02:43.93#ibcon#first serial, iclass 30, count 0 2006.162.08:02:43.93#ibcon#enter sib2, iclass 30, count 0 2006.162.08:02:43.93#ibcon#flushed, iclass 30, count 0 2006.162.08:02:43.93#ibcon#about to write, iclass 30, count 0 2006.162.08:02:43.93#ibcon#wrote, iclass 30, count 0 2006.162.08:02:43.93#ibcon#about to read 3, iclass 30, count 0 2006.162.08:02:43.95#ibcon#read 3, iclass 30, count 0 2006.162.08:02:43.95#ibcon#about to read 4, iclass 30, count 0 2006.162.08:02:43.95#ibcon#read 4, iclass 30, count 0 2006.162.08:02:43.95#ibcon#about to read 5, iclass 30, count 0 2006.162.08:02:43.95#ibcon#read 5, iclass 30, count 0 2006.162.08:02:43.95#ibcon#about to read 6, iclass 30, count 0 2006.162.08:02:43.95#ibcon#read 6, iclass 30, count 0 2006.162.08:02:43.95#ibcon#end of sib2, iclass 30, count 0 2006.162.08:02:43.95#ibcon#*mode == 0, iclass 30, count 0 2006.162.08:02:43.95#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.162.08:02:43.95#ibcon#[25=USB\r\n] 2006.162.08:02:43.95#ibcon#*before write, iclass 30, count 0 2006.162.08:02:43.95#ibcon#enter sib2, iclass 30, count 0 2006.162.08:02:43.95#ibcon#flushed, iclass 30, count 0 2006.162.08:02:43.95#ibcon#about to write, iclass 30, count 0 2006.162.08:02:43.95#ibcon#wrote, iclass 30, count 0 2006.162.08:02:43.95#ibcon#about to read 3, iclass 30, count 0 2006.162.08:02:43.98#ibcon#read 3, iclass 30, count 0 2006.162.08:02:43.98#ibcon#about to read 4, iclass 30, count 0 2006.162.08:02:43.98#ibcon#read 4, iclass 30, count 0 2006.162.08:02:43.98#ibcon#about to read 5, iclass 30, count 0 2006.162.08:02:43.98#ibcon#read 5, iclass 30, count 0 2006.162.08:02:43.98#ibcon#about to read 6, iclass 30, count 0 2006.162.08:02:43.98#ibcon#read 6, iclass 30, count 0 2006.162.08:02:43.98#ibcon#end of sib2, iclass 30, count 0 2006.162.08:02:43.98#ibcon#*after write, iclass 30, count 0 2006.162.08:02:43.98#ibcon#*before return 0, iclass 30, count 0 2006.162.08:02:43.98#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:02:43.98#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:02:43.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.162.08:02:43.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.162.08:02:43.98$vc4f8/valo=5,652.99 2006.162.08:02:43.98#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.162.08:02:43.98#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.162.08:02:43.98#ibcon#ireg 17 cls_cnt 0 2006.162.08:02:43.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:02:43.98#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:02:43.98#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:02:43.98#ibcon#enter wrdev, iclass 32, count 0 2006.162.08:02:43.98#ibcon#first serial, iclass 32, count 0 2006.162.08:02:43.98#ibcon#enter sib2, iclass 32, count 0 2006.162.08:02:43.98#ibcon#flushed, iclass 32, count 0 2006.162.08:02:43.98#ibcon#about to write, iclass 32, count 0 2006.162.08:02:43.98#ibcon#wrote, iclass 32, count 0 2006.162.08:02:43.98#ibcon#about to read 3, iclass 32, count 0 2006.162.08:02:44.00#ibcon#read 3, iclass 32, count 0 2006.162.08:02:44.00#ibcon#about to read 4, iclass 32, count 0 2006.162.08:02:44.00#ibcon#read 4, iclass 32, count 0 2006.162.08:02:44.00#ibcon#about to read 5, iclass 32, count 0 2006.162.08:02:44.00#ibcon#read 5, iclass 32, count 0 2006.162.08:02:44.00#ibcon#about to read 6, iclass 32, count 0 2006.162.08:02:44.00#ibcon#read 6, iclass 32, count 0 2006.162.08:02:44.00#ibcon#end of sib2, iclass 32, count 0 2006.162.08:02:44.00#ibcon#*mode == 0, iclass 32, count 0 2006.162.08:02:44.00#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.162.08:02:44.00#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.08:02:44.00#ibcon#*before write, iclass 32, count 0 2006.162.08:02:44.00#ibcon#enter sib2, iclass 32, count 0 2006.162.08:02:44.00#ibcon#flushed, iclass 32, count 0 2006.162.08:02:44.00#ibcon#about to write, iclass 32, count 0 2006.162.08:02:44.00#ibcon#wrote, iclass 32, count 0 2006.162.08:02:44.00#ibcon#about to read 3, iclass 32, count 0 2006.162.08:02:44.04#ibcon#read 3, iclass 32, count 0 2006.162.08:02:44.04#ibcon#about to read 4, iclass 32, count 0 2006.162.08:02:44.04#ibcon#read 4, iclass 32, count 0 2006.162.08:02:44.04#ibcon#about to read 5, iclass 32, count 0 2006.162.08:02:44.04#ibcon#read 5, iclass 32, count 0 2006.162.08:02:44.04#ibcon#about to read 6, iclass 32, count 0 2006.162.08:02:44.04#ibcon#read 6, iclass 32, count 0 2006.162.08:02:44.04#ibcon#end of sib2, iclass 32, count 0 2006.162.08:02:44.04#ibcon#*after write, iclass 32, count 0 2006.162.08:02:44.04#ibcon#*before return 0, iclass 32, count 0 2006.162.08:02:44.04#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:02:44.04#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:02:44.04#ibcon#about to clear, iclass 32 cls_cnt 0 2006.162.08:02:44.04#ibcon#cleared, iclass 32 cls_cnt 0 2006.162.08:02:44.04$vc4f8/va=5,7 2006.162.08:02:44.04#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.162.08:02:44.04#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.162.08:02:44.04#ibcon#ireg 11 cls_cnt 2 2006.162.08:02:44.04#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:02:44.11#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:02:44.11#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:02:44.11#ibcon#enter wrdev, iclass 34, count 2 2006.162.08:02:44.11#ibcon#first serial, iclass 34, count 2 2006.162.08:02:44.11#ibcon#enter sib2, iclass 34, count 2 2006.162.08:02:44.11#ibcon#flushed, iclass 34, count 2 2006.162.08:02:44.11#ibcon#about to write, iclass 34, count 2 2006.162.08:02:44.11#ibcon#wrote, iclass 34, count 2 2006.162.08:02:44.11#ibcon#about to read 3, iclass 34, count 2 2006.162.08:02:44.13#ibcon#read 3, iclass 34, count 2 2006.162.08:02:44.13#ibcon#about to read 4, iclass 34, count 2 2006.162.08:02:44.13#ibcon#read 4, iclass 34, count 2 2006.162.08:02:44.13#ibcon#about to read 5, iclass 34, count 2 2006.162.08:02:44.13#ibcon#read 5, iclass 34, count 2 2006.162.08:02:44.13#ibcon#about to read 6, iclass 34, count 2 2006.162.08:02:44.13#ibcon#read 6, iclass 34, count 2 2006.162.08:02:44.13#ibcon#end of sib2, iclass 34, count 2 2006.162.08:02:44.13#ibcon#*mode == 0, iclass 34, count 2 2006.162.08:02:44.13#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.162.08:02:44.13#ibcon#[25=AT05-07\r\n] 2006.162.08:02:44.13#ibcon#*before write, iclass 34, count 2 2006.162.08:02:44.13#ibcon#enter sib2, iclass 34, count 2 2006.162.08:02:44.13#ibcon#flushed, iclass 34, count 2 2006.162.08:02:44.13#ibcon#about to write, iclass 34, count 2 2006.162.08:02:44.13#ibcon#wrote, iclass 34, count 2 2006.162.08:02:44.13#ibcon#about to read 3, iclass 34, count 2 2006.162.08:02:44.14#abcon#<5=/03 1.7 3.6 17.851001007.0\r\n> 2006.162.08:02:44.15#ibcon#read 3, iclass 34, count 2 2006.162.08:02:44.15#ibcon#about to read 4, iclass 34, count 2 2006.162.08:02:44.15#ibcon#read 4, iclass 34, count 2 2006.162.08:02:44.15#ibcon#about to read 5, iclass 34, count 2 2006.162.08:02:44.15#ibcon#read 5, iclass 34, count 2 2006.162.08:02:44.15#ibcon#about to read 6, iclass 34, count 2 2006.162.08:02:44.15#ibcon#read 6, iclass 34, count 2 2006.162.08:02:44.15#ibcon#end of sib2, iclass 34, count 2 2006.162.08:02:44.15#ibcon#*after write, iclass 34, count 2 2006.162.08:02:44.15#ibcon#*before return 0, iclass 34, count 2 2006.162.08:02:44.15#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:02:44.15#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:02:44.15#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.162.08:02:44.15#ibcon#ireg 7 cls_cnt 0 2006.162.08:02:44.15#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:02:44.16#abcon#{5=INTERFACE CLEAR} 2006.162.08:02:44.22#abcon#[5=S1D000X0/0*\r\n] 2006.162.08:02:44.27#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:02:44.27#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:02:44.27#ibcon#enter wrdev, iclass 34, count 0 2006.162.08:02:44.27#ibcon#first serial, iclass 34, count 0 2006.162.08:02:44.27#ibcon#enter sib2, iclass 34, count 0 2006.162.08:02:44.27#ibcon#flushed, iclass 34, count 0 2006.162.08:02:44.27#ibcon#about to write, iclass 34, count 0 2006.162.08:02:44.27#ibcon#wrote, iclass 34, count 0 2006.162.08:02:44.27#ibcon#about to read 3, iclass 34, count 0 2006.162.08:02:44.31#ibcon#read 3, iclass 34, count 0 2006.162.08:02:44.31#ibcon#about to read 4, iclass 34, count 0 2006.162.08:02:44.31#ibcon#read 4, iclass 34, count 0 2006.162.08:02:44.31#ibcon#about to read 5, iclass 34, count 0 2006.162.08:02:44.31#ibcon#read 5, iclass 34, count 0 2006.162.08:02:44.31#ibcon#about to read 6, iclass 34, count 0 2006.162.08:02:44.31#ibcon#read 6, iclass 34, count 0 2006.162.08:02:44.31#ibcon#end of sib2, iclass 34, count 0 2006.162.08:02:44.31#ibcon#*mode == 0, iclass 34, count 0 2006.162.08:02:44.31#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.162.08:02:44.31#ibcon#[25=USB\r\n] 2006.162.08:02:44.31#ibcon#*before write, iclass 34, count 0 2006.162.08:02:44.31#ibcon#enter sib2, iclass 34, count 0 2006.162.08:02:44.31#ibcon#flushed, iclass 34, count 0 2006.162.08:02:44.31#ibcon#about to write, iclass 34, count 0 2006.162.08:02:44.31#ibcon#wrote, iclass 34, count 0 2006.162.08:02:44.31#ibcon#about to read 3, iclass 34, count 0 2006.162.08:02:44.34#ibcon#read 3, iclass 34, count 0 2006.162.08:02:44.34#ibcon#about to read 4, iclass 34, count 0 2006.162.08:02:44.34#ibcon#read 4, iclass 34, count 0 2006.162.08:02:44.34#ibcon#about to read 5, iclass 34, count 0 2006.162.08:02:44.34#ibcon#read 5, iclass 34, count 0 2006.162.08:02:44.34#ibcon#about to read 6, iclass 34, count 0 2006.162.08:02:44.34#ibcon#read 6, iclass 34, count 0 2006.162.08:02:44.34#ibcon#end of sib2, iclass 34, count 0 2006.162.08:02:44.34#ibcon#*after write, iclass 34, count 0 2006.162.08:02:44.34#ibcon#*before return 0, iclass 34, count 0 2006.162.08:02:44.34#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:02:44.34#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:02:44.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.162.08:02:44.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.162.08:02:44.34$vc4f8/valo=6,772.99 2006.162.08:02:44.34#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.162.08:02:44.34#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.162.08:02:44.34#ibcon#ireg 17 cls_cnt 0 2006.162.08:02:44.34#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:02:44.34#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:02:44.34#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:02:44.34#ibcon#enter wrdev, iclass 40, count 0 2006.162.08:02:44.34#ibcon#first serial, iclass 40, count 0 2006.162.08:02:44.34#ibcon#enter sib2, iclass 40, count 0 2006.162.08:02:44.34#ibcon#flushed, iclass 40, count 0 2006.162.08:02:44.34#ibcon#about to write, iclass 40, count 0 2006.162.08:02:44.34#ibcon#wrote, iclass 40, count 0 2006.162.08:02:44.34#ibcon#about to read 3, iclass 40, count 0 2006.162.08:02:44.36#ibcon#read 3, iclass 40, count 0 2006.162.08:02:44.36#ibcon#about to read 4, iclass 40, count 0 2006.162.08:02:44.36#ibcon#read 4, iclass 40, count 0 2006.162.08:02:44.36#ibcon#about to read 5, iclass 40, count 0 2006.162.08:02:44.36#ibcon#read 5, iclass 40, count 0 2006.162.08:02:44.36#ibcon#about to read 6, iclass 40, count 0 2006.162.08:02:44.36#ibcon#read 6, iclass 40, count 0 2006.162.08:02:44.36#ibcon#end of sib2, iclass 40, count 0 2006.162.08:02:44.36#ibcon#*mode == 0, iclass 40, count 0 2006.162.08:02:44.36#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.162.08:02:44.36#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.08:02:44.36#ibcon#*before write, iclass 40, count 0 2006.162.08:02:44.36#ibcon#enter sib2, iclass 40, count 0 2006.162.08:02:44.36#ibcon#flushed, iclass 40, count 0 2006.162.08:02:44.36#ibcon#about to write, iclass 40, count 0 2006.162.08:02:44.36#ibcon#wrote, iclass 40, count 0 2006.162.08:02:44.36#ibcon#about to read 3, iclass 40, count 0 2006.162.08:02:44.40#ibcon#read 3, iclass 40, count 0 2006.162.08:02:44.40#ibcon#about to read 4, iclass 40, count 0 2006.162.08:02:44.40#ibcon#read 4, iclass 40, count 0 2006.162.08:02:44.40#ibcon#about to read 5, iclass 40, count 0 2006.162.08:02:44.40#ibcon#read 5, iclass 40, count 0 2006.162.08:02:44.40#ibcon#about to read 6, iclass 40, count 0 2006.162.08:02:44.40#ibcon#read 6, iclass 40, count 0 2006.162.08:02:44.40#ibcon#end of sib2, iclass 40, count 0 2006.162.08:02:44.40#ibcon#*after write, iclass 40, count 0 2006.162.08:02:44.40#ibcon#*before return 0, iclass 40, count 0 2006.162.08:02:44.40#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:02:44.40#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:02:44.40#ibcon#about to clear, iclass 40 cls_cnt 0 2006.162.08:02:44.40#ibcon#cleared, iclass 40 cls_cnt 0 2006.162.08:02:44.40$vc4f8/va=6,6 2006.162.08:02:44.40#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.162.08:02:44.40#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.162.08:02:44.40#ibcon#ireg 11 cls_cnt 2 2006.162.08:02:44.40#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:02:44.46#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:02:44.46#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:02:44.46#ibcon#enter wrdev, iclass 4, count 2 2006.162.08:02:44.46#ibcon#first serial, iclass 4, count 2 2006.162.08:02:44.46#ibcon#enter sib2, iclass 4, count 2 2006.162.08:02:44.46#ibcon#flushed, iclass 4, count 2 2006.162.08:02:44.46#ibcon#about to write, iclass 4, count 2 2006.162.08:02:44.46#ibcon#wrote, iclass 4, count 2 2006.162.08:02:44.46#ibcon#about to read 3, iclass 4, count 2 2006.162.08:02:44.48#ibcon#read 3, iclass 4, count 2 2006.162.08:02:44.48#ibcon#about to read 4, iclass 4, count 2 2006.162.08:02:44.48#ibcon#read 4, iclass 4, count 2 2006.162.08:02:44.48#ibcon#about to read 5, iclass 4, count 2 2006.162.08:02:44.48#ibcon#read 5, iclass 4, count 2 2006.162.08:02:44.48#ibcon#about to read 6, iclass 4, count 2 2006.162.08:02:44.48#ibcon#read 6, iclass 4, count 2 2006.162.08:02:44.48#ibcon#end of sib2, iclass 4, count 2 2006.162.08:02:44.48#ibcon#*mode == 0, iclass 4, count 2 2006.162.08:02:44.48#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.162.08:02:44.48#ibcon#[25=AT06-06\r\n] 2006.162.08:02:44.48#ibcon#*before write, iclass 4, count 2 2006.162.08:02:44.48#ibcon#enter sib2, iclass 4, count 2 2006.162.08:02:44.48#ibcon#flushed, iclass 4, count 2 2006.162.08:02:44.48#ibcon#about to write, iclass 4, count 2 2006.162.08:02:44.48#ibcon#wrote, iclass 4, count 2 2006.162.08:02:44.48#ibcon#about to read 3, iclass 4, count 2 2006.162.08:02:44.51#ibcon#read 3, iclass 4, count 2 2006.162.08:02:44.51#ibcon#about to read 4, iclass 4, count 2 2006.162.08:02:44.51#ibcon#read 4, iclass 4, count 2 2006.162.08:02:44.51#ibcon#about to read 5, iclass 4, count 2 2006.162.08:02:44.51#ibcon#read 5, iclass 4, count 2 2006.162.08:02:44.51#ibcon#about to read 6, iclass 4, count 2 2006.162.08:02:44.51#ibcon#read 6, iclass 4, count 2 2006.162.08:02:44.51#ibcon#end of sib2, iclass 4, count 2 2006.162.08:02:44.51#ibcon#*after write, iclass 4, count 2 2006.162.08:02:44.51#ibcon#*before return 0, iclass 4, count 2 2006.162.08:02:44.51#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:02:44.51#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:02:44.51#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.162.08:02:44.51#ibcon#ireg 7 cls_cnt 0 2006.162.08:02:44.51#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:02:44.63#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:02:44.63#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:02:44.63#ibcon#enter wrdev, iclass 4, count 0 2006.162.08:02:44.63#ibcon#first serial, iclass 4, count 0 2006.162.08:02:44.63#ibcon#enter sib2, iclass 4, count 0 2006.162.08:02:44.63#ibcon#flushed, iclass 4, count 0 2006.162.08:02:44.63#ibcon#about to write, iclass 4, count 0 2006.162.08:02:44.63#ibcon#wrote, iclass 4, count 0 2006.162.08:02:44.63#ibcon#about to read 3, iclass 4, count 0 2006.162.08:02:44.65#ibcon#read 3, iclass 4, count 0 2006.162.08:02:44.65#ibcon#about to read 4, iclass 4, count 0 2006.162.08:02:44.65#ibcon#read 4, iclass 4, count 0 2006.162.08:02:44.65#ibcon#about to read 5, iclass 4, count 0 2006.162.08:02:44.65#ibcon#read 5, iclass 4, count 0 2006.162.08:02:44.65#ibcon#about to read 6, iclass 4, count 0 2006.162.08:02:44.65#ibcon#read 6, iclass 4, count 0 2006.162.08:02:44.65#ibcon#end of sib2, iclass 4, count 0 2006.162.08:02:44.65#ibcon#*mode == 0, iclass 4, count 0 2006.162.08:02:44.65#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.162.08:02:44.65#ibcon#[25=USB\r\n] 2006.162.08:02:44.65#ibcon#*before write, iclass 4, count 0 2006.162.08:02:44.65#ibcon#enter sib2, iclass 4, count 0 2006.162.08:02:44.65#ibcon#flushed, iclass 4, count 0 2006.162.08:02:44.65#ibcon#about to write, iclass 4, count 0 2006.162.08:02:44.65#ibcon#wrote, iclass 4, count 0 2006.162.08:02:44.65#ibcon#about to read 3, iclass 4, count 0 2006.162.08:02:44.68#ibcon#read 3, iclass 4, count 0 2006.162.08:02:44.68#ibcon#about to read 4, iclass 4, count 0 2006.162.08:02:44.68#ibcon#read 4, iclass 4, count 0 2006.162.08:02:44.68#ibcon#about to read 5, iclass 4, count 0 2006.162.08:02:44.68#ibcon#read 5, iclass 4, count 0 2006.162.08:02:44.68#ibcon#about to read 6, iclass 4, count 0 2006.162.08:02:44.68#ibcon#read 6, iclass 4, count 0 2006.162.08:02:44.68#ibcon#end of sib2, iclass 4, count 0 2006.162.08:02:44.68#ibcon#*after write, iclass 4, count 0 2006.162.08:02:44.68#ibcon#*before return 0, iclass 4, count 0 2006.162.08:02:44.68#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:02:44.68#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:02:44.68#ibcon#about to clear, iclass 4 cls_cnt 0 2006.162.08:02:44.68#ibcon#cleared, iclass 4 cls_cnt 0 2006.162.08:02:44.68$vc4f8/valo=7,832.99 2006.162.08:02:44.68#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.162.08:02:44.68#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.162.08:02:44.68#ibcon#ireg 17 cls_cnt 0 2006.162.08:02:44.68#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:02:44.68#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:02:44.68#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:02:44.68#ibcon#enter wrdev, iclass 6, count 0 2006.162.08:02:44.68#ibcon#first serial, iclass 6, count 0 2006.162.08:02:44.68#ibcon#enter sib2, iclass 6, count 0 2006.162.08:02:44.68#ibcon#flushed, iclass 6, count 0 2006.162.08:02:44.68#ibcon#about to write, iclass 6, count 0 2006.162.08:02:44.68#ibcon#wrote, iclass 6, count 0 2006.162.08:02:44.68#ibcon#about to read 3, iclass 6, count 0 2006.162.08:02:44.70#ibcon#read 3, iclass 6, count 0 2006.162.08:02:44.70#ibcon#about to read 4, iclass 6, count 0 2006.162.08:02:44.70#ibcon#read 4, iclass 6, count 0 2006.162.08:02:44.70#ibcon#about to read 5, iclass 6, count 0 2006.162.08:02:44.70#ibcon#read 5, iclass 6, count 0 2006.162.08:02:44.70#ibcon#about to read 6, iclass 6, count 0 2006.162.08:02:44.70#ibcon#read 6, iclass 6, count 0 2006.162.08:02:44.70#ibcon#end of sib2, iclass 6, count 0 2006.162.08:02:44.70#ibcon#*mode == 0, iclass 6, count 0 2006.162.08:02:44.70#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.162.08:02:44.70#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.08:02:44.70#ibcon#*before write, iclass 6, count 0 2006.162.08:02:44.70#ibcon#enter sib2, iclass 6, count 0 2006.162.08:02:44.70#ibcon#flushed, iclass 6, count 0 2006.162.08:02:44.70#ibcon#about to write, iclass 6, count 0 2006.162.08:02:44.70#ibcon#wrote, iclass 6, count 0 2006.162.08:02:44.70#ibcon#about to read 3, iclass 6, count 0 2006.162.08:02:44.74#ibcon#read 3, iclass 6, count 0 2006.162.08:02:44.74#ibcon#about to read 4, iclass 6, count 0 2006.162.08:02:44.74#ibcon#read 4, iclass 6, count 0 2006.162.08:02:44.74#ibcon#about to read 5, iclass 6, count 0 2006.162.08:02:44.74#ibcon#read 5, iclass 6, count 0 2006.162.08:02:44.74#ibcon#about to read 6, iclass 6, count 0 2006.162.08:02:44.74#ibcon#read 6, iclass 6, count 0 2006.162.08:02:44.74#ibcon#end of sib2, iclass 6, count 0 2006.162.08:02:44.74#ibcon#*after write, iclass 6, count 0 2006.162.08:02:44.74#ibcon#*before return 0, iclass 6, count 0 2006.162.08:02:44.74#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:02:44.74#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:02:44.74#ibcon#about to clear, iclass 6 cls_cnt 0 2006.162.08:02:44.74#ibcon#cleared, iclass 6 cls_cnt 0 2006.162.08:02:44.74$vc4f8/va=7,6 2006.162.08:02:44.74#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.162.08:02:44.74#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.162.08:02:44.74#ibcon#ireg 11 cls_cnt 2 2006.162.08:02:44.74#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:02:44.81#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:02:44.81#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:02:44.81#ibcon#enter wrdev, iclass 10, count 2 2006.162.08:02:44.81#ibcon#first serial, iclass 10, count 2 2006.162.08:02:44.81#ibcon#enter sib2, iclass 10, count 2 2006.162.08:02:44.81#ibcon#flushed, iclass 10, count 2 2006.162.08:02:44.81#ibcon#about to write, iclass 10, count 2 2006.162.08:02:44.81#ibcon#wrote, iclass 10, count 2 2006.162.08:02:44.81#ibcon#about to read 3, iclass 10, count 2 2006.162.08:02:44.82#ibcon#read 3, iclass 10, count 2 2006.162.08:02:44.82#ibcon#about to read 4, iclass 10, count 2 2006.162.08:02:44.82#ibcon#read 4, iclass 10, count 2 2006.162.08:02:44.82#ibcon#about to read 5, iclass 10, count 2 2006.162.08:02:44.82#ibcon#read 5, iclass 10, count 2 2006.162.08:02:44.82#ibcon#about to read 6, iclass 10, count 2 2006.162.08:02:44.82#ibcon#read 6, iclass 10, count 2 2006.162.08:02:44.82#ibcon#end of sib2, iclass 10, count 2 2006.162.08:02:44.82#ibcon#*mode == 0, iclass 10, count 2 2006.162.08:02:44.82#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.162.08:02:44.82#ibcon#[25=AT07-06\r\n] 2006.162.08:02:44.82#ibcon#*before write, iclass 10, count 2 2006.162.08:02:44.82#ibcon#enter sib2, iclass 10, count 2 2006.162.08:02:44.82#ibcon#flushed, iclass 10, count 2 2006.162.08:02:44.83#ibcon#about to write, iclass 10, count 2 2006.162.08:02:44.83#ibcon#wrote, iclass 10, count 2 2006.162.08:02:44.83#ibcon#about to read 3, iclass 10, count 2 2006.162.08:02:44.85#ibcon#read 3, iclass 10, count 2 2006.162.08:02:44.85#ibcon#about to read 4, iclass 10, count 2 2006.162.08:02:44.85#ibcon#read 4, iclass 10, count 2 2006.162.08:02:44.85#ibcon#about to read 5, iclass 10, count 2 2006.162.08:02:44.85#ibcon#read 5, iclass 10, count 2 2006.162.08:02:44.85#ibcon#about to read 6, iclass 10, count 2 2006.162.08:02:44.85#ibcon#read 6, iclass 10, count 2 2006.162.08:02:44.85#ibcon#end of sib2, iclass 10, count 2 2006.162.08:02:44.85#ibcon#*after write, iclass 10, count 2 2006.162.08:02:44.85#ibcon#*before return 0, iclass 10, count 2 2006.162.08:02:44.85#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:02:44.85#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:02:44.85#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.162.08:02:44.85#ibcon#ireg 7 cls_cnt 0 2006.162.08:02:44.85#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:02:44.97#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:02:44.97#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:02:44.97#ibcon#enter wrdev, iclass 10, count 0 2006.162.08:02:44.97#ibcon#first serial, iclass 10, count 0 2006.162.08:02:44.97#ibcon#enter sib2, iclass 10, count 0 2006.162.08:02:44.97#ibcon#flushed, iclass 10, count 0 2006.162.08:02:44.97#ibcon#about to write, iclass 10, count 0 2006.162.08:02:44.97#ibcon#wrote, iclass 10, count 0 2006.162.08:02:44.97#ibcon#about to read 3, iclass 10, count 0 2006.162.08:02:44.99#ibcon#read 3, iclass 10, count 0 2006.162.08:02:44.99#ibcon#about to read 4, iclass 10, count 0 2006.162.08:02:44.99#ibcon#read 4, iclass 10, count 0 2006.162.08:02:44.99#ibcon#about to read 5, iclass 10, count 0 2006.162.08:02:44.99#ibcon#read 5, iclass 10, count 0 2006.162.08:02:44.99#ibcon#about to read 6, iclass 10, count 0 2006.162.08:02:44.99#ibcon#read 6, iclass 10, count 0 2006.162.08:02:44.99#ibcon#end of sib2, iclass 10, count 0 2006.162.08:02:44.99#ibcon#*mode == 0, iclass 10, count 0 2006.162.08:02:44.99#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.162.08:02:44.99#ibcon#[25=USB\r\n] 2006.162.08:02:44.99#ibcon#*before write, iclass 10, count 0 2006.162.08:02:44.99#ibcon#enter sib2, iclass 10, count 0 2006.162.08:02:44.99#ibcon#flushed, iclass 10, count 0 2006.162.08:02:44.99#ibcon#about to write, iclass 10, count 0 2006.162.08:02:44.99#ibcon#wrote, iclass 10, count 0 2006.162.08:02:44.99#ibcon#about to read 3, iclass 10, count 0 2006.162.08:02:45.02#ibcon#read 3, iclass 10, count 0 2006.162.08:02:45.02#ibcon#about to read 4, iclass 10, count 0 2006.162.08:02:45.02#ibcon#read 4, iclass 10, count 0 2006.162.08:02:45.02#ibcon#about to read 5, iclass 10, count 0 2006.162.08:02:45.02#ibcon#read 5, iclass 10, count 0 2006.162.08:02:45.02#ibcon#about to read 6, iclass 10, count 0 2006.162.08:02:45.02#ibcon#read 6, iclass 10, count 0 2006.162.08:02:45.02#ibcon#end of sib2, iclass 10, count 0 2006.162.08:02:45.02#ibcon#*after write, iclass 10, count 0 2006.162.08:02:45.02#ibcon#*before return 0, iclass 10, count 0 2006.162.08:02:45.02#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:02:45.02#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:02:45.02#ibcon#about to clear, iclass 10 cls_cnt 0 2006.162.08:02:45.02#ibcon#cleared, iclass 10 cls_cnt 0 2006.162.08:02:45.02$vc4f8/valo=8,852.99 2006.162.08:02:45.02#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.162.08:02:45.02#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.162.08:02:45.02#ibcon#ireg 17 cls_cnt 0 2006.162.08:02:45.02#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:02:45.02#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:02:45.02#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:02:45.02#ibcon#enter wrdev, iclass 12, count 0 2006.162.08:02:45.02#ibcon#first serial, iclass 12, count 0 2006.162.08:02:45.02#ibcon#enter sib2, iclass 12, count 0 2006.162.08:02:45.02#ibcon#flushed, iclass 12, count 0 2006.162.08:02:45.02#ibcon#about to write, iclass 12, count 0 2006.162.08:02:45.02#ibcon#wrote, iclass 12, count 0 2006.162.08:02:45.02#ibcon#about to read 3, iclass 12, count 0 2006.162.08:02:45.04#ibcon#read 3, iclass 12, count 0 2006.162.08:02:45.04#ibcon#about to read 4, iclass 12, count 0 2006.162.08:02:45.04#ibcon#read 4, iclass 12, count 0 2006.162.08:02:45.04#ibcon#about to read 5, iclass 12, count 0 2006.162.08:02:45.04#ibcon#read 5, iclass 12, count 0 2006.162.08:02:45.04#ibcon#about to read 6, iclass 12, count 0 2006.162.08:02:45.04#ibcon#read 6, iclass 12, count 0 2006.162.08:02:45.04#ibcon#end of sib2, iclass 12, count 0 2006.162.08:02:45.04#ibcon#*mode == 0, iclass 12, count 0 2006.162.08:02:45.04#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.162.08:02:45.04#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.08:02:45.04#ibcon#*before write, iclass 12, count 0 2006.162.08:02:45.04#ibcon#enter sib2, iclass 12, count 0 2006.162.08:02:45.04#ibcon#flushed, iclass 12, count 0 2006.162.08:02:45.04#ibcon#about to write, iclass 12, count 0 2006.162.08:02:45.04#ibcon#wrote, iclass 12, count 0 2006.162.08:02:45.04#ibcon#about to read 3, iclass 12, count 0 2006.162.08:02:45.08#ibcon#read 3, iclass 12, count 0 2006.162.08:02:45.08#ibcon#about to read 4, iclass 12, count 0 2006.162.08:02:45.08#ibcon#read 4, iclass 12, count 0 2006.162.08:02:45.08#ibcon#about to read 5, iclass 12, count 0 2006.162.08:02:45.08#ibcon#read 5, iclass 12, count 0 2006.162.08:02:45.08#ibcon#about to read 6, iclass 12, count 0 2006.162.08:02:45.08#ibcon#read 6, iclass 12, count 0 2006.162.08:02:45.08#ibcon#end of sib2, iclass 12, count 0 2006.162.08:02:45.08#ibcon#*after write, iclass 12, count 0 2006.162.08:02:45.08#ibcon#*before return 0, iclass 12, count 0 2006.162.08:02:45.08#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:02:45.08#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:02:45.08#ibcon#about to clear, iclass 12 cls_cnt 0 2006.162.08:02:45.08#ibcon#cleared, iclass 12 cls_cnt 0 2006.162.08:02:45.08$vc4f8/va=8,7 2006.162.08:02:45.08#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.162.08:02:45.08#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.162.08:02:45.08#ibcon#ireg 11 cls_cnt 2 2006.162.08:02:45.08#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.162.08:02:45.14#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.162.08:02:45.14#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.162.08:02:45.14#ibcon#enter wrdev, iclass 14, count 2 2006.162.08:02:45.14#ibcon#first serial, iclass 14, count 2 2006.162.08:02:45.14#ibcon#enter sib2, iclass 14, count 2 2006.162.08:02:45.14#ibcon#flushed, iclass 14, count 2 2006.162.08:02:45.14#ibcon#about to write, iclass 14, count 2 2006.162.08:02:45.14#ibcon#wrote, iclass 14, count 2 2006.162.08:02:45.14#ibcon#about to read 3, iclass 14, count 2 2006.162.08:02:45.16#ibcon#read 3, iclass 14, count 2 2006.162.08:02:45.16#ibcon#about to read 4, iclass 14, count 2 2006.162.08:02:45.16#ibcon#read 4, iclass 14, count 2 2006.162.08:02:45.16#ibcon#about to read 5, iclass 14, count 2 2006.162.08:02:45.16#ibcon#read 5, iclass 14, count 2 2006.162.08:02:45.16#ibcon#about to read 6, iclass 14, count 2 2006.162.08:02:45.16#ibcon#read 6, iclass 14, count 2 2006.162.08:02:45.16#ibcon#end of sib2, iclass 14, count 2 2006.162.08:02:45.16#ibcon#*mode == 0, iclass 14, count 2 2006.162.08:02:45.16#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.162.08:02:45.16#ibcon#[25=AT08-07\r\n] 2006.162.08:02:45.16#ibcon#*before write, iclass 14, count 2 2006.162.08:02:45.16#ibcon#enter sib2, iclass 14, count 2 2006.162.08:02:45.16#ibcon#flushed, iclass 14, count 2 2006.162.08:02:45.16#ibcon#about to write, iclass 14, count 2 2006.162.08:02:45.16#ibcon#wrote, iclass 14, count 2 2006.162.08:02:45.16#ibcon#about to read 3, iclass 14, count 2 2006.162.08:02:45.19#ibcon#read 3, iclass 14, count 2 2006.162.08:02:45.19#ibcon#about to read 4, iclass 14, count 2 2006.162.08:02:45.19#ibcon#read 4, iclass 14, count 2 2006.162.08:02:45.19#ibcon#about to read 5, iclass 14, count 2 2006.162.08:02:45.19#ibcon#read 5, iclass 14, count 2 2006.162.08:02:45.19#ibcon#about to read 6, iclass 14, count 2 2006.162.08:02:45.19#ibcon#read 6, iclass 14, count 2 2006.162.08:02:45.19#ibcon#end of sib2, iclass 14, count 2 2006.162.08:02:45.19#ibcon#*after write, iclass 14, count 2 2006.162.08:02:45.19#ibcon#*before return 0, iclass 14, count 2 2006.162.08:02:45.19#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.162.08:02:45.19#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.162.08:02:45.19#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.162.08:02:45.19#ibcon#ireg 7 cls_cnt 0 2006.162.08:02:45.19#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.162.08:02:45.31#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.162.08:02:45.31#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.162.08:02:45.31#ibcon#enter wrdev, iclass 14, count 0 2006.162.08:02:45.31#ibcon#first serial, iclass 14, count 0 2006.162.08:02:45.31#ibcon#enter sib2, iclass 14, count 0 2006.162.08:02:45.31#ibcon#flushed, iclass 14, count 0 2006.162.08:02:45.31#ibcon#about to write, iclass 14, count 0 2006.162.08:02:45.31#ibcon#wrote, iclass 14, count 0 2006.162.08:02:45.31#ibcon#about to read 3, iclass 14, count 0 2006.162.08:02:45.33#ibcon#read 3, iclass 14, count 0 2006.162.08:02:45.33#ibcon#about to read 4, iclass 14, count 0 2006.162.08:02:45.33#ibcon#read 4, iclass 14, count 0 2006.162.08:02:45.33#ibcon#about to read 5, iclass 14, count 0 2006.162.08:02:45.33#ibcon#read 5, iclass 14, count 0 2006.162.08:02:45.33#ibcon#about to read 6, iclass 14, count 0 2006.162.08:02:45.33#ibcon#read 6, iclass 14, count 0 2006.162.08:02:45.33#ibcon#end of sib2, iclass 14, count 0 2006.162.08:02:45.33#ibcon#*mode == 0, iclass 14, count 0 2006.162.08:02:45.33#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.08:02:45.33#ibcon#[25=USB\r\n] 2006.162.08:02:45.33#ibcon#*before write, iclass 14, count 0 2006.162.08:02:45.33#ibcon#enter sib2, iclass 14, count 0 2006.162.08:02:45.33#ibcon#flushed, iclass 14, count 0 2006.162.08:02:45.33#ibcon#about to write, iclass 14, count 0 2006.162.08:02:45.33#ibcon#wrote, iclass 14, count 0 2006.162.08:02:45.33#ibcon#about to read 3, iclass 14, count 0 2006.162.08:02:45.36#ibcon#read 3, iclass 14, count 0 2006.162.08:02:45.36#ibcon#about to read 4, iclass 14, count 0 2006.162.08:02:45.36#ibcon#read 4, iclass 14, count 0 2006.162.08:02:45.36#ibcon#about to read 5, iclass 14, count 0 2006.162.08:02:45.36#ibcon#read 5, iclass 14, count 0 2006.162.08:02:45.36#ibcon#about to read 6, iclass 14, count 0 2006.162.08:02:45.36#ibcon#read 6, iclass 14, count 0 2006.162.08:02:45.36#ibcon#end of sib2, iclass 14, count 0 2006.162.08:02:45.36#ibcon#*after write, iclass 14, count 0 2006.162.08:02:45.36#ibcon#*before return 0, iclass 14, count 0 2006.162.08:02:45.36#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.162.08:02:45.36#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.162.08:02:45.36#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.08:02:45.36#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.08:02:45.36$vc4f8/vblo=1,632.99 2006.162.08:02:45.36#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.162.08:02:45.36#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.162.08:02:45.36#ibcon#ireg 17 cls_cnt 0 2006.162.08:02:45.36#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:02:45.36#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:02:45.36#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:02:45.36#ibcon#enter wrdev, iclass 16, count 0 2006.162.08:02:45.36#ibcon#first serial, iclass 16, count 0 2006.162.08:02:45.36#ibcon#enter sib2, iclass 16, count 0 2006.162.08:02:45.36#ibcon#flushed, iclass 16, count 0 2006.162.08:02:45.36#ibcon#about to write, iclass 16, count 0 2006.162.08:02:45.36#ibcon#wrote, iclass 16, count 0 2006.162.08:02:45.36#ibcon#about to read 3, iclass 16, count 0 2006.162.08:02:45.38#ibcon#read 3, iclass 16, count 0 2006.162.08:02:45.38#ibcon#about to read 4, iclass 16, count 0 2006.162.08:02:45.38#ibcon#read 4, iclass 16, count 0 2006.162.08:02:45.38#ibcon#about to read 5, iclass 16, count 0 2006.162.08:02:45.38#ibcon#read 5, iclass 16, count 0 2006.162.08:02:45.38#ibcon#about to read 6, iclass 16, count 0 2006.162.08:02:45.38#ibcon#read 6, iclass 16, count 0 2006.162.08:02:45.38#ibcon#end of sib2, iclass 16, count 0 2006.162.08:02:45.38#ibcon#*mode == 0, iclass 16, count 0 2006.162.08:02:45.38#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.162.08:02:45.38#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.08:02:45.38#ibcon#*before write, iclass 16, count 0 2006.162.08:02:45.38#ibcon#enter sib2, iclass 16, count 0 2006.162.08:02:45.38#ibcon#flushed, iclass 16, count 0 2006.162.08:02:45.38#ibcon#about to write, iclass 16, count 0 2006.162.08:02:45.38#ibcon#wrote, iclass 16, count 0 2006.162.08:02:45.38#ibcon#about to read 3, iclass 16, count 0 2006.162.08:02:45.42#ibcon#read 3, iclass 16, count 0 2006.162.08:02:45.42#ibcon#about to read 4, iclass 16, count 0 2006.162.08:02:45.42#ibcon#read 4, iclass 16, count 0 2006.162.08:02:45.42#ibcon#about to read 5, iclass 16, count 0 2006.162.08:02:45.42#ibcon#read 5, iclass 16, count 0 2006.162.08:02:45.42#ibcon#about to read 6, iclass 16, count 0 2006.162.08:02:45.42#ibcon#read 6, iclass 16, count 0 2006.162.08:02:45.42#ibcon#end of sib2, iclass 16, count 0 2006.162.08:02:45.42#ibcon#*after write, iclass 16, count 0 2006.162.08:02:45.42#ibcon#*before return 0, iclass 16, count 0 2006.162.08:02:45.42#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:02:45.42#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:02:45.42#ibcon#about to clear, iclass 16 cls_cnt 0 2006.162.08:02:45.42#ibcon#cleared, iclass 16 cls_cnt 0 2006.162.08:02:45.42$vc4f8/vb=1,4 2006.162.08:02:45.42#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.162.08:02:45.42#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.162.08:02:45.42#ibcon#ireg 11 cls_cnt 2 2006.162.08:02:45.42#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:02:45.42#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:02:45.42#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:02:45.42#ibcon#enter wrdev, iclass 18, count 2 2006.162.08:02:45.42#ibcon#first serial, iclass 18, count 2 2006.162.08:02:45.42#ibcon#enter sib2, iclass 18, count 2 2006.162.08:02:45.42#ibcon#flushed, iclass 18, count 2 2006.162.08:02:45.42#ibcon#about to write, iclass 18, count 2 2006.162.08:02:45.42#ibcon#wrote, iclass 18, count 2 2006.162.08:02:45.42#ibcon#about to read 3, iclass 18, count 2 2006.162.08:02:45.44#ibcon#read 3, iclass 18, count 2 2006.162.08:02:45.44#ibcon#about to read 4, iclass 18, count 2 2006.162.08:02:45.44#ibcon#read 4, iclass 18, count 2 2006.162.08:02:45.44#ibcon#about to read 5, iclass 18, count 2 2006.162.08:02:45.44#ibcon#read 5, iclass 18, count 2 2006.162.08:02:45.44#ibcon#about to read 6, iclass 18, count 2 2006.162.08:02:45.44#ibcon#read 6, iclass 18, count 2 2006.162.08:02:45.44#ibcon#end of sib2, iclass 18, count 2 2006.162.08:02:45.44#ibcon#*mode == 0, iclass 18, count 2 2006.162.08:02:45.44#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.162.08:02:45.44#ibcon#[27=AT01-04\r\n] 2006.162.08:02:45.44#ibcon#*before write, iclass 18, count 2 2006.162.08:02:45.44#ibcon#enter sib2, iclass 18, count 2 2006.162.08:02:45.44#ibcon#flushed, iclass 18, count 2 2006.162.08:02:45.44#ibcon#about to write, iclass 18, count 2 2006.162.08:02:45.44#ibcon#wrote, iclass 18, count 2 2006.162.08:02:45.44#ibcon#about to read 3, iclass 18, count 2 2006.162.08:02:45.47#ibcon#read 3, iclass 18, count 2 2006.162.08:02:45.47#ibcon#about to read 4, iclass 18, count 2 2006.162.08:02:45.47#ibcon#read 4, iclass 18, count 2 2006.162.08:02:45.47#ibcon#about to read 5, iclass 18, count 2 2006.162.08:02:45.47#ibcon#read 5, iclass 18, count 2 2006.162.08:02:45.47#ibcon#about to read 6, iclass 18, count 2 2006.162.08:02:45.47#ibcon#read 6, iclass 18, count 2 2006.162.08:02:45.47#ibcon#end of sib2, iclass 18, count 2 2006.162.08:02:45.47#ibcon#*after write, iclass 18, count 2 2006.162.08:02:45.47#ibcon#*before return 0, iclass 18, count 2 2006.162.08:02:45.47#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:02:45.47#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:02:45.47#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.162.08:02:45.47#ibcon#ireg 7 cls_cnt 0 2006.162.08:02:45.47#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:02:45.59#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:02:45.59#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:02:45.59#ibcon#enter wrdev, iclass 18, count 0 2006.162.08:02:45.59#ibcon#first serial, iclass 18, count 0 2006.162.08:02:45.59#ibcon#enter sib2, iclass 18, count 0 2006.162.08:02:45.59#ibcon#flushed, iclass 18, count 0 2006.162.08:02:45.59#ibcon#about to write, iclass 18, count 0 2006.162.08:02:45.59#ibcon#wrote, iclass 18, count 0 2006.162.08:02:45.59#ibcon#about to read 3, iclass 18, count 0 2006.162.08:02:45.61#ibcon#read 3, iclass 18, count 0 2006.162.08:02:45.61#ibcon#about to read 4, iclass 18, count 0 2006.162.08:02:45.61#ibcon#read 4, iclass 18, count 0 2006.162.08:02:45.61#ibcon#about to read 5, iclass 18, count 0 2006.162.08:02:45.61#ibcon#read 5, iclass 18, count 0 2006.162.08:02:45.61#ibcon#about to read 6, iclass 18, count 0 2006.162.08:02:45.61#ibcon#read 6, iclass 18, count 0 2006.162.08:02:45.61#ibcon#end of sib2, iclass 18, count 0 2006.162.08:02:45.61#ibcon#*mode == 0, iclass 18, count 0 2006.162.08:02:45.61#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.162.08:02:45.61#ibcon#[27=USB\r\n] 2006.162.08:02:45.61#ibcon#*before write, iclass 18, count 0 2006.162.08:02:45.61#ibcon#enter sib2, iclass 18, count 0 2006.162.08:02:45.61#ibcon#flushed, iclass 18, count 0 2006.162.08:02:45.61#ibcon#about to write, iclass 18, count 0 2006.162.08:02:45.61#ibcon#wrote, iclass 18, count 0 2006.162.08:02:45.61#ibcon#about to read 3, iclass 18, count 0 2006.162.08:02:45.64#ibcon#read 3, iclass 18, count 0 2006.162.08:02:45.64#ibcon#about to read 4, iclass 18, count 0 2006.162.08:02:45.64#ibcon#read 4, iclass 18, count 0 2006.162.08:02:45.64#ibcon#about to read 5, iclass 18, count 0 2006.162.08:02:45.64#ibcon#read 5, iclass 18, count 0 2006.162.08:02:45.64#ibcon#about to read 6, iclass 18, count 0 2006.162.08:02:45.64#ibcon#read 6, iclass 18, count 0 2006.162.08:02:45.64#ibcon#end of sib2, iclass 18, count 0 2006.162.08:02:45.64#ibcon#*after write, iclass 18, count 0 2006.162.08:02:45.64#ibcon#*before return 0, iclass 18, count 0 2006.162.08:02:45.64#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:02:45.64#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:02:45.64#ibcon#about to clear, iclass 18 cls_cnt 0 2006.162.08:02:45.64#ibcon#cleared, iclass 18 cls_cnt 0 2006.162.08:02:45.64$vc4f8/vblo=2,640.99 2006.162.08:02:45.64#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.162.08:02:45.64#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.162.08:02:45.64#ibcon#ireg 17 cls_cnt 0 2006.162.08:02:45.64#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:02:45.64#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:02:45.64#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:02:45.64#ibcon#enter wrdev, iclass 20, count 0 2006.162.08:02:45.64#ibcon#first serial, iclass 20, count 0 2006.162.08:02:45.64#ibcon#enter sib2, iclass 20, count 0 2006.162.08:02:45.64#ibcon#flushed, iclass 20, count 0 2006.162.08:02:45.64#ibcon#about to write, iclass 20, count 0 2006.162.08:02:45.64#ibcon#wrote, iclass 20, count 0 2006.162.08:02:45.64#ibcon#about to read 3, iclass 20, count 0 2006.162.08:02:45.66#ibcon#read 3, iclass 20, count 0 2006.162.08:02:45.66#ibcon#about to read 4, iclass 20, count 0 2006.162.08:02:45.66#ibcon#read 4, iclass 20, count 0 2006.162.08:02:45.66#ibcon#about to read 5, iclass 20, count 0 2006.162.08:02:45.66#ibcon#read 5, iclass 20, count 0 2006.162.08:02:45.66#ibcon#about to read 6, iclass 20, count 0 2006.162.08:02:45.66#ibcon#read 6, iclass 20, count 0 2006.162.08:02:45.66#ibcon#end of sib2, iclass 20, count 0 2006.162.08:02:45.66#ibcon#*mode == 0, iclass 20, count 0 2006.162.08:02:45.66#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.08:02:45.66#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.08:02:45.66#ibcon#*before write, iclass 20, count 0 2006.162.08:02:45.66#ibcon#enter sib2, iclass 20, count 0 2006.162.08:02:45.66#ibcon#flushed, iclass 20, count 0 2006.162.08:02:45.66#ibcon#about to write, iclass 20, count 0 2006.162.08:02:45.66#ibcon#wrote, iclass 20, count 0 2006.162.08:02:45.66#ibcon#about to read 3, iclass 20, count 0 2006.162.08:02:45.70#ibcon#read 3, iclass 20, count 0 2006.162.08:02:45.70#ibcon#about to read 4, iclass 20, count 0 2006.162.08:02:45.70#ibcon#read 4, iclass 20, count 0 2006.162.08:02:45.70#ibcon#about to read 5, iclass 20, count 0 2006.162.08:02:45.70#ibcon#read 5, iclass 20, count 0 2006.162.08:02:45.70#ibcon#about to read 6, iclass 20, count 0 2006.162.08:02:45.70#ibcon#read 6, iclass 20, count 0 2006.162.08:02:45.70#ibcon#end of sib2, iclass 20, count 0 2006.162.08:02:45.70#ibcon#*after write, iclass 20, count 0 2006.162.08:02:45.70#ibcon#*before return 0, iclass 20, count 0 2006.162.08:02:45.70#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:02:45.70#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:02:45.70#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.08:02:45.70#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.08:02:45.70$vc4f8/vb=2,4 2006.162.08:02:45.70#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.162.08:02:45.70#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.162.08:02:45.70#ibcon#ireg 11 cls_cnt 2 2006.162.08:02:45.70#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:02:45.76#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:02:45.76#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:02:45.76#ibcon#enter wrdev, iclass 22, count 2 2006.162.08:02:45.76#ibcon#first serial, iclass 22, count 2 2006.162.08:02:45.76#ibcon#enter sib2, iclass 22, count 2 2006.162.08:02:45.76#ibcon#flushed, iclass 22, count 2 2006.162.08:02:45.76#ibcon#about to write, iclass 22, count 2 2006.162.08:02:45.76#ibcon#wrote, iclass 22, count 2 2006.162.08:02:45.76#ibcon#about to read 3, iclass 22, count 2 2006.162.08:02:45.78#ibcon#read 3, iclass 22, count 2 2006.162.08:02:45.78#ibcon#about to read 4, iclass 22, count 2 2006.162.08:02:45.78#ibcon#read 4, iclass 22, count 2 2006.162.08:02:45.78#ibcon#about to read 5, iclass 22, count 2 2006.162.08:02:45.78#ibcon#read 5, iclass 22, count 2 2006.162.08:02:45.78#ibcon#about to read 6, iclass 22, count 2 2006.162.08:02:45.78#ibcon#read 6, iclass 22, count 2 2006.162.08:02:45.78#ibcon#end of sib2, iclass 22, count 2 2006.162.08:02:45.78#ibcon#*mode == 0, iclass 22, count 2 2006.162.08:02:45.78#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.162.08:02:45.78#ibcon#[27=AT02-04\r\n] 2006.162.08:02:45.78#ibcon#*before write, iclass 22, count 2 2006.162.08:02:45.78#ibcon#enter sib2, iclass 22, count 2 2006.162.08:02:45.78#ibcon#flushed, iclass 22, count 2 2006.162.08:02:45.78#ibcon#about to write, iclass 22, count 2 2006.162.08:02:45.78#ibcon#wrote, iclass 22, count 2 2006.162.08:02:45.78#ibcon#about to read 3, iclass 22, count 2 2006.162.08:02:45.81#ibcon#read 3, iclass 22, count 2 2006.162.08:02:45.81#ibcon#about to read 4, iclass 22, count 2 2006.162.08:02:45.81#ibcon#read 4, iclass 22, count 2 2006.162.08:02:45.81#ibcon#about to read 5, iclass 22, count 2 2006.162.08:02:45.81#ibcon#read 5, iclass 22, count 2 2006.162.08:02:45.81#ibcon#about to read 6, iclass 22, count 2 2006.162.08:02:45.81#ibcon#read 6, iclass 22, count 2 2006.162.08:02:45.81#ibcon#end of sib2, iclass 22, count 2 2006.162.08:02:45.81#ibcon#*after write, iclass 22, count 2 2006.162.08:02:45.81#ibcon#*before return 0, iclass 22, count 2 2006.162.08:02:45.81#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:02:45.81#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:02:45.81#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.162.08:02:45.81#ibcon#ireg 7 cls_cnt 0 2006.162.08:02:45.81#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:02:45.93#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:02:45.93#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:02:45.93#ibcon#enter wrdev, iclass 22, count 0 2006.162.08:02:45.93#ibcon#first serial, iclass 22, count 0 2006.162.08:02:45.93#ibcon#enter sib2, iclass 22, count 0 2006.162.08:02:45.93#ibcon#flushed, iclass 22, count 0 2006.162.08:02:45.93#ibcon#about to write, iclass 22, count 0 2006.162.08:02:45.93#ibcon#wrote, iclass 22, count 0 2006.162.08:02:45.93#ibcon#about to read 3, iclass 22, count 0 2006.162.08:02:45.95#ibcon#read 3, iclass 22, count 0 2006.162.08:02:45.95#ibcon#about to read 4, iclass 22, count 0 2006.162.08:02:45.95#ibcon#read 4, iclass 22, count 0 2006.162.08:02:45.95#ibcon#about to read 5, iclass 22, count 0 2006.162.08:02:45.95#ibcon#read 5, iclass 22, count 0 2006.162.08:02:45.95#ibcon#about to read 6, iclass 22, count 0 2006.162.08:02:45.95#ibcon#read 6, iclass 22, count 0 2006.162.08:02:45.95#ibcon#end of sib2, iclass 22, count 0 2006.162.08:02:45.95#ibcon#*mode == 0, iclass 22, count 0 2006.162.08:02:45.95#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.08:02:45.95#ibcon#[27=USB\r\n] 2006.162.08:02:45.95#ibcon#*before write, iclass 22, count 0 2006.162.08:02:45.95#ibcon#enter sib2, iclass 22, count 0 2006.162.08:02:45.95#ibcon#flushed, iclass 22, count 0 2006.162.08:02:45.95#ibcon#about to write, iclass 22, count 0 2006.162.08:02:45.95#ibcon#wrote, iclass 22, count 0 2006.162.08:02:45.95#ibcon#about to read 3, iclass 22, count 0 2006.162.08:02:45.98#ibcon#read 3, iclass 22, count 0 2006.162.08:02:45.98#ibcon#about to read 4, iclass 22, count 0 2006.162.08:02:45.98#ibcon#read 4, iclass 22, count 0 2006.162.08:02:45.98#ibcon#about to read 5, iclass 22, count 0 2006.162.08:02:45.98#ibcon#read 5, iclass 22, count 0 2006.162.08:02:45.98#ibcon#about to read 6, iclass 22, count 0 2006.162.08:02:45.98#ibcon#read 6, iclass 22, count 0 2006.162.08:02:45.98#ibcon#end of sib2, iclass 22, count 0 2006.162.08:02:45.98#ibcon#*after write, iclass 22, count 0 2006.162.08:02:45.98#ibcon#*before return 0, iclass 22, count 0 2006.162.08:02:45.98#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:02:45.98#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:02:45.98#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.08:02:45.98#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.08:02:45.98$vc4f8/vblo=3,656.99 2006.162.08:02:45.98#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.162.08:02:45.98#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.162.08:02:45.98#ibcon#ireg 17 cls_cnt 0 2006.162.08:02:45.98#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:02:45.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:02:45.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:02:45.98#ibcon#enter wrdev, iclass 24, count 0 2006.162.08:02:45.98#ibcon#first serial, iclass 24, count 0 2006.162.08:02:45.98#ibcon#enter sib2, iclass 24, count 0 2006.162.08:02:45.98#ibcon#flushed, iclass 24, count 0 2006.162.08:02:45.98#ibcon#about to write, iclass 24, count 0 2006.162.08:02:45.98#ibcon#wrote, iclass 24, count 0 2006.162.08:02:45.98#ibcon#about to read 3, iclass 24, count 0 2006.162.08:02:46.00#ibcon#read 3, iclass 24, count 0 2006.162.08:02:46.00#ibcon#about to read 4, iclass 24, count 0 2006.162.08:02:46.00#ibcon#read 4, iclass 24, count 0 2006.162.08:02:46.00#ibcon#about to read 5, iclass 24, count 0 2006.162.08:02:46.00#ibcon#read 5, iclass 24, count 0 2006.162.08:02:46.00#ibcon#about to read 6, iclass 24, count 0 2006.162.08:02:46.00#ibcon#read 6, iclass 24, count 0 2006.162.08:02:46.00#ibcon#end of sib2, iclass 24, count 0 2006.162.08:02:46.00#ibcon#*mode == 0, iclass 24, count 0 2006.162.08:02:46.00#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.08:02:46.00#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.08:02:46.00#ibcon#*before write, iclass 24, count 0 2006.162.08:02:46.00#ibcon#enter sib2, iclass 24, count 0 2006.162.08:02:46.00#ibcon#flushed, iclass 24, count 0 2006.162.08:02:46.00#ibcon#about to write, iclass 24, count 0 2006.162.08:02:46.00#ibcon#wrote, iclass 24, count 0 2006.162.08:02:46.00#ibcon#about to read 3, iclass 24, count 0 2006.162.08:02:46.04#ibcon#read 3, iclass 24, count 0 2006.162.08:02:46.04#ibcon#about to read 4, iclass 24, count 0 2006.162.08:02:46.04#ibcon#read 4, iclass 24, count 0 2006.162.08:02:46.04#ibcon#about to read 5, iclass 24, count 0 2006.162.08:02:46.04#ibcon#read 5, iclass 24, count 0 2006.162.08:02:46.04#ibcon#about to read 6, iclass 24, count 0 2006.162.08:02:46.04#ibcon#read 6, iclass 24, count 0 2006.162.08:02:46.04#ibcon#end of sib2, iclass 24, count 0 2006.162.08:02:46.04#ibcon#*after write, iclass 24, count 0 2006.162.08:02:46.04#ibcon#*before return 0, iclass 24, count 0 2006.162.08:02:46.04#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:02:46.04#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:02:46.04#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.08:02:46.04#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.08:02:46.04$vc4f8/vb=3,4 2006.162.08:02:46.04#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.162.08:02:46.04#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.162.08:02:46.04#ibcon#ireg 11 cls_cnt 2 2006.162.08:02:46.04#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:02:46.11#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:02:46.11#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:02:46.11#ibcon#enter wrdev, iclass 26, count 2 2006.162.08:02:46.11#ibcon#first serial, iclass 26, count 2 2006.162.08:02:46.11#ibcon#enter sib2, iclass 26, count 2 2006.162.08:02:46.11#ibcon#flushed, iclass 26, count 2 2006.162.08:02:46.11#ibcon#about to write, iclass 26, count 2 2006.162.08:02:46.11#ibcon#wrote, iclass 26, count 2 2006.162.08:02:46.11#ibcon#about to read 3, iclass 26, count 2 2006.162.08:02:46.12#ibcon#read 3, iclass 26, count 2 2006.162.08:02:46.12#ibcon#about to read 4, iclass 26, count 2 2006.162.08:02:46.12#ibcon#read 4, iclass 26, count 2 2006.162.08:02:46.12#ibcon#about to read 5, iclass 26, count 2 2006.162.08:02:46.12#ibcon#read 5, iclass 26, count 2 2006.162.08:02:46.12#ibcon#about to read 6, iclass 26, count 2 2006.162.08:02:46.12#ibcon#read 6, iclass 26, count 2 2006.162.08:02:46.12#ibcon#end of sib2, iclass 26, count 2 2006.162.08:02:46.12#ibcon#*mode == 0, iclass 26, count 2 2006.162.08:02:46.12#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.162.08:02:46.12#ibcon#[27=AT03-04\r\n] 2006.162.08:02:46.12#ibcon#*before write, iclass 26, count 2 2006.162.08:02:46.12#ibcon#enter sib2, iclass 26, count 2 2006.162.08:02:46.12#ibcon#flushed, iclass 26, count 2 2006.162.08:02:46.12#ibcon#about to write, iclass 26, count 2 2006.162.08:02:46.12#ibcon#wrote, iclass 26, count 2 2006.162.08:02:46.12#ibcon#about to read 3, iclass 26, count 2 2006.162.08:02:46.15#ibcon#read 3, iclass 26, count 2 2006.162.08:02:46.15#ibcon#about to read 4, iclass 26, count 2 2006.162.08:02:46.15#ibcon#read 4, iclass 26, count 2 2006.162.08:02:46.15#ibcon#about to read 5, iclass 26, count 2 2006.162.08:02:46.15#ibcon#read 5, iclass 26, count 2 2006.162.08:02:46.15#ibcon#about to read 6, iclass 26, count 2 2006.162.08:02:46.15#ibcon#read 6, iclass 26, count 2 2006.162.08:02:46.15#ibcon#end of sib2, iclass 26, count 2 2006.162.08:02:46.15#ibcon#*after write, iclass 26, count 2 2006.162.08:02:46.15#ibcon#*before return 0, iclass 26, count 2 2006.162.08:02:46.15#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:02:46.15#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:02:46.15#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.162.08:02:46.15#ibcon#ireg 7 cls_cnt 0 2006.162.08:02:46.15#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:02:46.27#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:02:46.27#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:02:46.27#ibcon#enter wrdev, iclass 26, count 0 2006.162.08:02:46.27#ibcon#first serial, iclass 26, count 0 2006.162.08:02:46.27#ibcon#enter sib2, iclass 26, count 0 2006.162.08:02:46.27#ibcon#flushed, iclass 26, count 0 2006.162.08:02:46.27#ibcon#about to write, iclass 26, count 0 2006.162.08:02:46.27#ibcon#wrote, iclass 26, count 0 2006.162.08:02:46.27#ibcon#about to read 3, iclass 26, count 0 2006.162.08:02:46.29#ibcon#read 3, iclass 26, count 0 2006.162.08:02:46.29#ibcon#about to read 4, iclass 26, count 0 2006.162.08:02:46.29#ibcon#read 4, iclass 26, count 0 2006.162.08:02:46.29#ibcon#about to read 5, iclass 26, count 0 2006.162.08:02:46.29#ibcon#read 5, iclass 26, count 0 2006.162.08:02:46.29#ibcon#about to read 6, iclass 26, count 0 2006.162.08:02:46.29#ibcon#read 6, iclass 26, count 0 2006.162.08:02:46.29#ibcon#end of sib2, iclass 26, count 0 2006.162.08:02:46.29#ibcon#*mode == 0, iclass 26, count 0 2006.162.08:02:46.29#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.162.08:02:46.29#ibcon#[27=USB\r\n] 2006.162.08:02:46.29#ibcon#*before write, iclass 26, count 0 2006.162.08:02:46.29#ibcon#enter sib2, iclass 26, count 0 2006.162.08:02:46.29#ibcon#flushed, iclass 26, count 0 2006.162.08:02:46.29#ibcon#about to write, iclass 26, count 0 2006.162.08:02:46.29#ibcon#wrote, iclass 26, count 0 2006.162.08:02:46.29#ibcon#about to read 3, iclass 26, count 0 2006.162.08:02:46.32#ibcon#read 3, iclass 26, count 0 2006.162.08:02:46.32#ibcon#about to read 4, iclass 26, count 0 2006.162.08:02:46.32#ibcon#read 4, iclass 26, count 0 2006.162.08:02:46.32#ibcon#about to read 5, iclass 26, count 0 2006.162.08:02:46.32#ibcon#read 5, iclass 26, count 0 2006.162.08:02:46.32#ibcon#about to read 6, iclass 26, count 0 2006.162.08:02:46.32#ibcon#read 6, iclass 26, count 0 2006.162.08:02:46.32#ibcon#end of sib2, iclass 26, count 0 2006.162.08:02:46.32#ibcon#*after write, iclass 26, count 0 2006.162.08:02:46.32#ibcon#*before return 0, iclass 26, count 0 2006.162.08:02:46.32#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:02:46.32#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:02:46.32#ibcon#about to clear, iclass 26 cls_cnt 0 2006.162.08:02:46.32#ibcon#cleared, iclass 26 cls_cnt 0 2006.162.08:02:46.32$vc4f8/vblo=4,712.99 2006.162.08:02:46.32#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.162.08:02:46.32#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.162.08:02:46.32#ibcon#ireg 17 cls_cnt 0 2006.162.08:02:46.32#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:02:46.32#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:02:46.32#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:02:46.32#ibcon#enter wrdev, iclass 28, count 0 2006.162.08:02:46.32#ibcon#first serial, iclass 28, count 0 2006.162.08:02:46.32#ibcon#enter sib2, iclass 28, count 0 2006.162.08:02:46.32#ibcon#flushed, iclass 28, count 0 2006.162.08:02:46.32#ibcon#about to write, iclass 28, count 0 2006.162.08:02:46.32#ibcon#wrote, iclass 28, count 0 2006.162.08:02:46.32#ibcon#about to read 3, iclass 28, count 0 2006.162.08:02:46.34#ibcon#read 3, iclass 28, count 0 2006.162.08:02:46.34#ibcon#about to read 4, iclass 28, count 0 2006.162.08:02:46.34#ibcon#read 4, iclass 28, count 0 2006.162.08:02:46.34#ibcon#about to read 5, iclass 28, count 0 2006.162.08:02:46.34#ibcon#read 5, iclass 28, count 0 2006.162.08:02:46.34#ibcon#about to read 6, iclass 28, count 0 2006.162.08:02:46.34#ibcon#read 6, iclass 28, count 0 2006.162.08:02:46.34#ibcon#end of sib2, iclass 28, count 0 2006.162.08:02:46.34#ibcon#*mode == 0, iclass 28, count 0 2006.162.08:02:46.34#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.162.08:02:46.34#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.08:02:46.34#ibcon#*before write, iclass 28, count 0 2006.162.08:02:46.34#ibcon#enter sib2, iclass 28, count 0 2006.162.08:02:46.34#ibcon#flushed, iclass 28, count 0 2006.162.08:02:46.34#ibcon#about to write, iclass 28, count 0 2006.162.08:02:46.34#ibcon#wrote, iclass 28, count 0 2006.162.08:02:46.34#ibcon#about to read 3, iclass 28, count 0 2006.162.08:02:46.38#ibcon#read 3, iclass 28, count 0 2006.162.08:02:46.38#ibcon#about to read 4, iclass 28, count 0 2006.162.08:02:46.38#ibcon#read 4, iclass 28, count 0 2006.162.08:02:46.38#ibcon#about to read 5, iclass 28, count 0 2006.162.08:02:46.38#ibcon#read 5, iclass 28, count 0 2006.162.08:02:46.38#ibcon#about to read 6, iclass 28, count 0 2006.162.08:02:46.38#ibcon#read 6, iclass 28, count 0 2006.162.08:02:46.38#ibcon#end of sib2, iclass 28, count 0 2006.162.08:02:46.38#ibcon#*after write, iclass 28, count 0 2006.162.08:02:46.38#ibcon#*before return 0, iclass 28, count 0 2006.162.08:02:46.38#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:02:46.38#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:02:46.38#ibcon#about to clear, iclass 28 cls_cnt 0 2006.162.08:02:46.38#ibcon#cleared, iclass 28 cls_cnt 0 2006.162.08:02:46.38$vc4f8/vb=4,4 2006.162.08:02:46.38#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.162.08:02:46.38#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.162.08:02:46.38#ibcon#ireg 11 cls_cnt 2 2006.162.08:02:46.38#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:02:46.44#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:02:46.44#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:02:46.44#ibcon#enter wrdev, iclass 30, count 2 2006.162.08:02:46.44#ibcon#first serial, iclass 30, count 2 2006.162.08:02:46.44#ibcon#enter sib2, iclass 30, count 2 2006.162.08:02:46.44#ibcon#flushed, iclass 30, count 2 2006.162.08:02:46.44#ibcon#about to write, iclass 30, count 2 2006.162.08:02:46.44#ibcon#wrote, iclass 30, count 2 2006.162.08:02:46.44#ibcon#about to read 3, iclass 30, count 2 2006.162.08:02:46.46#ibcon#read 3, iclass 30, count 2 2006.162.08:02:46.46#ibcon#about to read 4, iclass 30, count 2 2006.162.08:02:46.46#ibcon#read 4, iclass 30, count 2 2006.162.08:02:46.46#ibcon#about to read 5, iclass 30, count 2 2006.162.08:02:46.46#ibcon#read 5, iclass 30, count 2 2006.162.08:02:46.46#ibcon#about to read 6, iclass 30, count 2 2006.162.08:02:46.46#ibcon#read 6, iclass 30, count 2 2006.162.08:02:46.46#ibcon#end of sib2, iclass 30, count 2 2006.162.08:02:46.46#ibcon#*mode == 0, iclass 30, count 2 2006.162.08:02:46.46#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.162.08:02:46.46#ibcon#[27=AT04-04\r\n] 2006.162.08:02:46.46#ibcon#*before write, iclass 30, count 2 2006.162.08:02:46.46#ibcon#enter sib2, iclass 30, count 2 2006.162.08:02:46.46#ibcon#flushed, iclass 30, count 2 2006.162.08:02:46.46#ibcon#about to write, iclass 30, count 2 2006.162.08:02:46.46#ibcon#wrote, iclass 30, count 2 2006.162.08:02:46.46#ibcon#about to read 3, iclass 30, count 2 2006.162.08:02:46.49#ibcon#read 3, iclass 30, count 2 2006.162.08:02:46.49#ibcon#about to read 4, iclass 30, count 2 2006.162.08:02:46.49#ibcon#read 4, iclass 30, count 2 2006.162.08:02:46.49#ibcon#about to read 5, iclass 30, count 2 2006.162.08:02:46.49#ibcon#read 5, iclass 30, count 2 2006.162.08:02:46.49#ibcon#about to read 6, iclass 30, count 2 2006.162.08:02:46.49#ibcon#read 6, iclass 30, count 2 2006.162.08:02:46.49#ibcon#end of sib2, iclass 30, count 2 2006.162.08:02:46.49#ibcon#*after write, iclass 30, count 2 2006.162.08:02:46.49#ibcon#*before return 0, iclass 30, count 2 2006.162.08:02:46.49#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:02:46.49#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:02:46.49#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.162.08:02:46.49#ibcon#ireg 7 cls_cnt 0 2006.162.08:02:46.49#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:02:46.61#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:02:46.61#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:02:46.61#ibcon#enter wrdev, iclass 30, count 0 2006.162.08:02:46.61#ibcon#first serial, iclass 30, count 0 2006.162.08:02:46.61#ibcon#enter sib2, iclass 30, count 0 2006.162.08:02:46.61#ibcon#flushed, iclass 30, count 0 2006.162.08:02:46.61#ibcon#about to write, iclass 30, count 0 2006.162.08:02:46.61#ibcon#wrote, iclass 30, count 0 2006.162.08:02:46.61#ibcon#about to read 3, iclass 30, count 0 2006.162.08:02:46.63#ibcon#read 3, iclass 30, count 0 2006.162.08:02:46.63#ibcon#about to read 4, iclass 30, count 0 2006.162.08:02:46.63#ibcon#read 4, iclass 30, count 0 2006.162.08:02:46.63#ibcon#about to read 5, iclass 30, count 0 2006.162.08:02:46.63#ibcon#read 5, iclass 30, count 0 2006.162.08:02:46.63#ibcon#about to read 6, iclass 30, count 0 2006.162.08:02:46.63#ibcon#read 6, iclass 30, count 0 2006.162.08:02:46.63#ibcon#end of sib2, iclass 30, count 0 2006.162.08:02:46.63#ibcon#*mode == 0, iclass 30, count 0 2006.162.08:02:46.63#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.162.08:02:46.63#ibcon#[27=USB\r\n] 2006.162.08:02:46.63#ibcon#*before write, iclass 30, count 0 2006.162.08:02:46.63#ibcon#enter sib2, iclass 30, count 0 2006.162.08:02:46.63#ibcon#flushed, iclass 30, count 0 2006.162.08:02:46.63#ibcon#about to write, iclass 30, count 0 2006.162.08:02:46.63#ibcon#wrote, iclass 30, count 0 2006.162.08:02:46.63#ibcon#about to read 3, iclass 30, count 0 2006.162.08:02:46.66#ibcon#read 3, iclass 30, count 0 2006.162.08:02:46.66#ibcon#about to read 4, iclass 30, count 0 2006.162.08:02:46.66#ibcon#read 4, iclass 30, count 0 2006.162.08:02:46.66#ibcon#about to read 5, iclass 30, count 0 2006.162.08:02:46.66#ibcon#read 5, iclass 30, count 0 2006.162.08:02:46.66#ibcon#about to read 6, iclass 30, count 0 2006.162.08:02:46.66#ibcon#read 6, iclass 30, count 0 2006.162.08:02:46.66#ibcon#end of sib2, iclass 30, count 0 2006.162.08:02:46.66#ibcon#*after write, iclass 30, count 0 2006.162.08:02:46.66#ibcon#*before return 0, iclass 30, count 0 2006.162.08:02:46.66#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:02:46.66#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:02:46.66#ibcon#about to clear, iclass 30 cls_cnt 0 2006.162.08:02:46.66#ibcon#cleared, iclass 30 cls_cnt 0 2006.162.08:02:46.66$vc4f8/vblo=5,744.99 2006.162.08:02:46.66#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.162.08:02:46.66#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.162.08:02:46.66#ibcon#ireg 17 cls_cnt 0 2006.162.08:02:46.66#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:02:46.66#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:02:46.66#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:02:46.66#ibcon#enter wrdev, iclass 32, count 0 2006.162.08:02:46.66#ibcon#first serial, iclass 32, count 0 2006.162.08:02:46.66#ibcon#enter sib2, iclass 32, count 0 2006.162.08:02:46.66#ibcon#flushed, iclass 32, count 0 2006.162.08:02:46.66#ibcon#about to write, iclass 32, count 0 2006.162.08:02:46.66#ibcon#wrote, iclass 32, count 0 2006.162.08:02:46.66#ibcon#about to read 3, iclass 32, count 0 2006.162.08:02:46.68#ibcon#read 3, iclass 32, count 0 2006.162.08:02:46.68#ibcon#about to read 4, iclass 32, count 0 2006.162.08:02:46.68#ibcon#read 4, iclass 32, count 0 2006.162.08:02:46.68#ibcon#about to read 5, iclass 32, count 0 2006.162.08:02:46.68#ibcon#read 5, iclass 32, count 0 2006.162.08:02:46.68#ibcon#about to read 6, iclass 32, count 0 2006.162.08:02:46.68#ibcon#read 6, iclass 32, count 0 2006.162.08:02:46.68#ibcon#end of sib2, iclass 32, count 0 2006.162.08:02:46.68#ibcon#*mode == 0, iclass 32, count 0 2006.162.08:02:46.68#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.162.08:02:46.68#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.08:02:46.68#ibcon#*before write, iclass 32, count 0 2006.162.08:02:46.68#ibcon#enter sib2, iclass 32, count 0 2006.162.08:02:46.68#ibcon#flushed, iclass 32, count 0 2006.162.08:02:46.68#ibcon#about to write, iclass 32, count 0 2006.162.08:02:46.68#ibcon#wrote, iclass 32, count 0 2006.162.08:02:46.68#ibcon#about to read 3, iclass 32, count 0 2006.162.08:02:46.72#ibcon#read 3, iclass 32, count 0 2006.162.08:02:46.72#ibcon#about to read 4, iclass 32, count 0 2006.162.08:02:46.72#ibcon#read 4, iclass 32, count 0 2006.162.08:02:46.72#ibcon#about to read 5, iclass 32, count 0 2006.162.08:02:46.72#ibcon#read 5, iclass 32, count 0 2006.162.08:02:46.72#ibcon#about to read 6, iclass 32, count 0 2006.162.08:02:46.72#ibcon#read 6, iclass 32, count 0 2006.162.08:02:46.72#ibcon#end of sib2, iclass 32, count 0 2006.162.08:02:46.72#ibcon#*after write, iclass 32, count 0 2006.162.08:02:46.72#ibcon#*before return 0, iclass 32, count 0 2006.162.08:02:46.72#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:02:46.72#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:02:46.72#ibcon#about to clear, iclass 32 cls_cnt 0 2006.162.08:02:46.72#ibcon#cleared, iclass 32 cls_cnt 0 2006.162.08:02:46.72$vc4f8/vb=5,4 2006.162.08:02:46.72#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.162.08:02:46.72#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.162.08:02:46.72#ibcon#ireg 11 cls_cnt 2 2006.162.08:02:46.72#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:02:46.79#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:02:46.79#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:02:46.79#ibcon#enter wrdev, iclass 34, count 2 2006.162.08:02:46.79#ibcon#first serial, iclass 34, count 2 2006.162.08:02:46.79#ibcon#enter sib2, iclass 34, count 2 2006.162.08:02:46.79#ibcon#flushed, iclass 34, count 2 2006.162.08:02:46.79#ibcon#about to write, iclass 34, count 2 2006.162.08:02:46.79#ibcon#wrote, iclass 34, count 2 2006.162.08:02:46.79#ibcon#about to read 3, iclass 34, count 2 2006.162.08:02:46.80#ibcon#read 3, iclass 34, count 2 2006.162.08:02:46.80#ibcon#about to read 4, iclass 34, count 2 2006.162.08:02:46.80#ibcon#read 4, iclass 34, count 2 2006.162.08:02:46.80#ibcon#about to read 5, iclass 34, count 2 2006.162.08:02:46.80#ibcon#read 5, iclass 34, count 2 2006.162.08:02:46.80#ibcon#about to read 6, iclass 34, count 2 2006.162.08:02:46.80#ibcon#read 6, iclass 34, count 2 2006.162.08:02:46.80#ibcon#end of sib2, iclass 34, count 2 2006.162.08:02:46.80#ibcon#*mode == 0, iclass 34, count 2 2006.162.08:02:46.80#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.162.08:02:46.80#ibcon#[27=AT05-04\r\n] 2006.162.08:02:46.80#ibcon#*before write, iclass 34, count 2 2006.162.08:02:46.80#ibcon#enter sib2, iclass 34, count 2 2006.162.08:02:46.80#ibcon#flushed, iclass 34, count 2 2006.162.08:02:46.80#ibcon#about to write, iclass 34, count 2 2006.162.08:02:46.80#ibcon#wrote, iclass 34, count 2 2006.162.08:02:46.80#ibcon#about to read 3, iclass 34, count 2 2006.162.08:02:46.83#ibcon#read 3, iclass 34, count 2 2006.162.08:02:46.83#ibcon#about to read 4, iclass 34, count 2 2006.162.08:02:46.83#ibcon#read 4, iclass 34, count 2 2006.162.08:02:46.83#ibcon#about to read 5, iclass 34, count 2 2006.162.08:02:46.83#ibcon#read 5, iclass 34, count 2 2006.162.08:02:46.83#ibcon#about to read 6, iclass 34, count 2 2006.162.08:02:46.83#ibcon#read 6, iclass 34, count 2 2006.162.08:02:46.83#ibcon#end of sib2, iclass 34, count 2 2006.162.08:02:46.83#ibcon#*after write, iclass 34, count 2 2006.162.08:02:46.83#ibcon#*before return 0, iclass 34, count 2 2006.162.08:02:46.83#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:02:46.83#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:02:46.83#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.162.08:02:46.83#ibcon#ireg 7 cls_cnt 0 2006.162.08:02:46.83#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:02:46.95#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:02:46.95#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:02:46.95#ibcon#enter wrdev, iclass 34, count 0 2006.162.08:02:46.95#ibcon#first serial, iclass 34, count 0 2006.162.08:02:46.95#ibcon#enter sib2, iclass 34, count 0 2006.162.08:02:46.95#ibcon#flushed, iclass 34, count 0 2006.162.08:02:46.95#ibcon#about to write, iclass 34, count 0 2006.162.08:02:46.95#ibcon#wrote, iclass 34, count 0 2006.162.08:02:46.95#ibcon#about to read 3, iclass 34, count 0 2006.162.08:02:46.97#ibcon#read 3, iclass 34, count 0 2006.162.08:02:46.97#ibcon#about to read 4, iclass 34, count 0 2006.162.08:02:46.97#ibcon#read 4, iclass 34, count 0 2006.162.08:02:46.97#ibcon#about to read 5, iclass 34, count 0 2006.162.08:02:46.97#ibcon#read 5, iclass 34, count 0 2006.162.08:02:46.97#ibcon#about to read 6, iclass 34, count 0 2006.162.08:02:46.97#ibcon#read 6, iclass 34, count 0 2006.162.08:02:46.97#ibcon#end of sib2, iclass 34, count 0 2006.162.08:02:46.97#ibcon#*mode == 0, iclass 34, count 0 2006.162.08:02:46.97#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.162.08:02:46.97#ibcon#[27=USB\r\n] 2006.162.08:02:46.97#ibcon#*before write, iclass 34, count 0 2006.162.08:02:46.97#ibcon#enter sib2, iclass 34, count 0 2006.162.08:02:46.97#ibcon#flushed, iclass 34, count 0 2006.162.08:02:46.97#ibcon#about to write, iclass 34, count 0 2006.162.08:02:46.97#ibcon#wrote, iclass 34, count 0 2006.162.08:02:46.97#ibcon#about to read 3, iclass 34, count 0 2006.162.08:02:47.00#ibcon#read 3, iclass 34, count 0 2006.162.08:02:47.00#ibcon#about to read 4, iclass 34, count 0 2006.162.08:02:47.00#ibcon#read 4, iclass 34, count 0 2006.162.08:02:47.00#ibcon#about to read 5, iclass 34, count 0 2006.162.08:02:47.00#ibcon#read 5, iclass 34, count 0 2006.162.08:02:47.00#ibcon#about to read 6, iclass 34, count 0 2006.162.08:02:47.00#ibcon#read 6, iclass 34, count 0 2006.162.08:02:47.00#ibcon#end of sib2, iclass 34, count 0 2006.162.08:02:47.00#ibcon#*after write, iclass 34, count 0 2006.162.08:02:47.00#ibcon#*before return 0, iclass 34, count 0 2006.162.08:02:47.00#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:02:47.00#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:02:47.00#ibcon#about to clear, iclass 34 cls_cnt 0 2006.162.08:02:47.00#ibcon#cleared, iclass 34 cls_cnt 0 2006.162.08:02:47.00$vc4f8/vblo=6,752.99 2006.162.08:02:47.00#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.162.08:02:47.00#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.162.08:02:47.00#ibcon#ireg 17 cls_cnt 0 2006.162.08:02:47.00#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:02:47.00#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:02:47.00#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:02:47.00#ibcon#enter wrdev, iclass 36, count 0 2006.162.08:02:47.00#ibcon#first serial, iclass 36, count 0 2006.162.08:02:47.00#ibcon#enter sib2, iclass 36, count 0 2006.162.08:02:47.00#ibcon#flushed, iclass 36, count 0 2006.162.08:02:47.00#ibcon#about to write, iclass 36, count 0 2006.162.08:02:47.00#ibcon#wrote, iclass 36, count 0 2006.162.08:02:47.00#ibcon#about to read 3, iclass 36, count 0 2006.162.08:02:47.02#ibcon#read 3, iclass 36, count 0 2006.162.08:02:47.02#ibcon#about to read 4, iclass 36, count 0 2006.162.08:02:47.02#ibcon#read 4, iclass 36, count 0 2006.162.08:02:47.02#ibcon#about to read 5, iclass 36, count 0 2006.162.08:02:47.02#ibcon#read 5, iclass 36, count 0 2006.162.08:02:47.02#ibcon#about to read 6, iclass 36, count 0 2006.162.08:02:47.02#ibcon#read 6, iclass 36, count 0 2006.162.08:02:47.02#ibcon#end of sib2, iclass 36, count 0 2006.162.08:02:47.02#ibcon#*mode == 0, iclass 36, count 0 2006.162.08:02:47.02#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.162.08:02:47.02#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.08:02:47.02#ibcon#*before write, iclass 36, count 0 2006.162.08:02:47.02#ibcon#enter sib2, iclass 36, count 0 2006.162.08:02:47.02#ibcon#flushed, iclass 36, count 0 2006.162.08:02:47.02#ibcon#about to write, iclass 36, count 0 2006.162.08:02:47.02#ibcon#wrote, iclass 36, count 0 2006.162.08:02:47.02#ibcon#about to read 3, iclass 36, count 0 2006.162.08:02:47.06#ibcon#read 3, iclass 36, count 0 2006.162.08:02:47.06#ibcon#about to read 4, iclass 36, count 0 2006.162.08:02:47.06#ibcon#read 4, iclass 36, count 0 2006.162.08:02:47.06#ibcon#about to read 5, iclass 36, count 0 2006.162.08:02:47.06#ibcon#read 5, iclass 36, count 0 2006.162.08:02:47.06#ibcon#about to read 6, iclass 36, count 0 2006.162.08:02:47.06#ibcon#read 6, iclass 36, count 0 2006.162.08:02:47.06#ibcon#end of sib2, iclass 36, count 0 2006.162.08:02:47.06#ibcon#*after write, iclass 36, count 0 2006.162.08:02:47.06#ibcon#*before return 0, iclass 36, count 0 2006.162.08:02:47.06#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:02:47.06#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:02:47.06#ibcon#about to clear, iclass 36 cls_cnt 0 2006.162.08:02:47.06#ibcon#cleared, iclass 36 cls_cnt 0 2006.162.08:02:47.06$vc4f8/vb=6,4 2006.162.08:02:47.06#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.162.08:02:47.06#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.162.08:02:47.06#ibcon#ireg 11 cls_cnt 2 2006.162.08:02:47.06#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.162.08:02:47.12#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.162.08:02:47.12#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.162.08:02:47.12#ibcon#enter wrdev, iclass 38, count 2 2006.162.08:02:47.12#ibcon#first serial, iclass 38, count 2 2006.162.08:02:47.12#ibcon#enter sib2, iclass 38, count 2 2006.162.08:02:47.12#ibcon#flushed, iclass 38, count 2 2006.162.08:02:47.12#ibcon#about to write, iclass 38, count 2 2006.162.08:02:47.12#ibcon#wrote, iclass 38, count 2 2006.162.08:02:47.12#ibcon#about to read 3, iclass 38, count 2 2006.162.08:02:47.14#ibcon#read 3, iclass 38, count 2 2006.162.08:02:47.14#ibcon#about to read 4, iclass 38, count 2 2006.162.08:02:47.14#ibcon#read 4, iclass 38, count 2 2006.162.08:02:47.14#ibcon#about to read 5, iclass 38, count 2 2006.162.08:02:47.14#ibcon#read 5, iclass 38, count 2 2006.162.08:02:47.14#ibcon#about to read 6, iclass 38, count 2 2006.162.08:02:47.14#ibcon#read 6, iclass 38, count 2 2006.162.08:02:47.14#ibcon#end of sib2, iclass 38, count 2 2006.162.08:02:47.14#ibcon#*mode == 0, iclass 38, count 2 2006.162.08:02:47.14#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.162.08:02:47.14#ibcon#[27=AT06-04\r\n] 2006.162.08:02:47.14#ibcon#*before write, iclass 38, count 2 2006.162.08:02:47.14#ibcon#enter sib2, iclass 38, count 2 2006.162.08:02:47.14#ibcon#flushed, iclass 38, count 2 2006.162.08:02:47.14#ibcon#about to write, iclass 38, count 2 2006.162.08:02:47.14#ibcon#wrote, iclass 38, count 2 2006.162.08:02:47.14#ibcon#about to read 3, iclass 38, count 2 2006.162.08:02:47.17#ibcon#read 3, iclass 38, count 2 2006.162.08:02:47.17#ibcon#about to read 4, iclass 38, count 2 2006.162.08:02:47.17#ibcon#read 4, iclass 38, count 2 2006.162.08:02:47.17#ibcon#about to read 5, iclass 38, count 2 2006.162.08:02:47.17#ibcon#read 5, iclass 38, count 2 2006.162.08:02:47.17#ibcon#about to read 6, iclass 38, count 2 2006.162.08:02:47.17#ibcon#read 6, iclass 38, count 2 2006.162.08:02:47.17#ibcon#end of sib2, iclass 38, count 2 2006.162.08:02:47.17#ibcon#*after write, iclass 38, count 2 2006.162.08:02:47.17#ibcon#*before return 0, iclass 38, count 2 2006.162.08:02:47.17#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.162.08:02:47.17#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.162.08:02:47.17#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.162.08:02:47.17#ibcon#ireg 7 cls_cnt 0 2006.162.08:02:47.17#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.162.08:02:47.29#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.162.08:02:47.29#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.162.08:02:47.29#ibcon#enter wrdev, iclass 38, count 0 2006.162.08:02:47.29#ibcon#first serial, iclass 38, count 0 2006.162.08:02:47.29#ibcon#enter sib2, iclass 38, count 0 2006.162.08:02:47.29#ibcon#flushed, iclass 38, count 0 2006.162.08:02:47.29#ibcon#about to write, iclass 38, count 0 2006.162.08:02:47.29#ibcon#wrote, iclass 38, count 0 2006.162.08:02:47.29#ibcon#about to read 3, iclass 38, count 0 2006.162.08:02:47.31#ibcon#read 3, iclass 38, count 0 2006.162.08:02:47.31#ibcon#about to read 4, iclass 38, count 0 2006.162.08:02:47.31#ibcon#read 4, iclass 38, count 0 2006.162.08:02:47.31#ibcon#about to read 5, iclass 38, count 0 2006.162.08:02:47.31#ibcon#read 5, iclass 38, count 0 2006.162.08:02:47.31#ibcon#about to read 6, iclass 38, count 0 2006.162.08:02:47.31#ibcon#read 6, iclass 38, count 0 2006.162.08:02:47.31#ibcon#end of sib2, iclass 38, count 0 2006.162.08:02:47.31#ibcon#*mode == 0, iclass 38, count 0 2006.162.08:02:47.31#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.162.08:02:47.31#ibcon#[27=USB\r\n] 2006.162.08:02:47.31#ibcon#*before write, iclass 38, count 0 2006.162.08:02:47.31#ibcon#enter sib2, iclass 38, count 0 2006.162.08:02:47.31#ibcon#flushed, iclass 38, count 0 2006.162.08:02:47.31#ibcon#about to write, iclass 38, count 0 2006.162.08:02:47.31#ibcon#wrote, iclass 38, count 0 2006.162.08:02:47.31#ibcon#about to read 3, iclass 38, count 0 2006.162.08:02:47.34#ibcon#read 3, iclass 38, count 0 2006.162.08:02:47.34#ibcon#about to read 4, iclass 38, count 0 2006.162.08:02:47.34#ibcon#read 4, iclass 38, count 0 2006.162.08:02:47.34#ibcon#about to read 5, iclass 38, count 0 2006.162.08:02:47.34#ibcon#read 5, iclass 38, count 0 2006.162.08:02:47.34#ibcon#about to read 6, iclass 38, count 0 2006.162.08:02:47.34#ibcon#read 6, iclass 38, count 0 2006.162.08:02:47.34#ibcon#end of sib2, iclass 38, count 0 2006.162.08:02:47.34#ibcon#*after write, iclass 38, count 0 2006.162.08:02:47.34#ibcon#*before return 0, iclass 38, count 0 2006.162.08:02:47.34#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.162.08:02:47.34#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.162.08:02:47.34#ibcon#about to clear, iclass 38 cls_cnt 0 2006.162.08:02:47.34#ibcon#cleared, iclass 38 cls_cnt 0 2006.162.08:02:47.34$vc4f8/vabw=wide 2006.162.08:02:47.34#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.162.08:02:47.34#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.162.08:02:47.34#ibcon#ireg 8 cls_cnt 0 2006.162.08:02:47.34#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:02:47.34#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:02:47.34#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:02:47.34#ibcon#enter wrdev, iclass 40, count 0 2006.162.08:02:47.34#ibcon#first serial, iclass 40, count 0 2006.162.08:02:47.34#ibcon#enter sib2, iclass 40, count 0 2006.162.08:02:47.34#ibcon#flushed, iclass 40, count 0 2006.162.08:02:47.34#ibcon#about to write, iclass 40, count 0 2006.162.08:02:47.34#ibcon#wrote, iclass 40, count 0 2006.162.08:02:47.34#ibcon#about to read 3, iclass 40, count 0 2006.162.08:02:47.36#ibcon#read 3, iclass 40, count 0 2006.162.08:02:47.36#ibcon#about to read 4, iclass 40, count 0 2006.162.08:02:47.36#ibcon#read 4, iclass 40, count 0 2006.162.08:02:47.36#ibcon#about to read 5, iclass 40, count 0 2006.162.08:02:47.36#ibcon#read 5, iclass 40, count 0 2006.162.08:02:47.36#ibcon#about to read 6, iclass 40, count 0 2006.162.08:02:47.36#ibcon#read 6, iclass 40, count 0 2006.162.08:02:47.36#ibcon#end of sib2, iclass 40, count 0 2006.162.08:02:47.36#ibcon#*mode == 0, iclass 40, count 0 2006.162.08:02:47.36#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.162.08:02:47.36#ibcon#[25=BW32\r\n] 2006.162.08:02:47.36#ibcon#*before write, iclass 40, count 0 2006.162.08:02:47.36#ibcon#enter sib2, iclass 40, count 0 2006.162.08:02:47.36#ibcon#flushed, iclass 40, count 0 2006.162.08:02:47.36#ibcon#about to write, iclass 40, count 0 2006.162.08:02:47.36#ibcon#wrote, iclass 40, count 0 2006.162.08:02:47.36#ibcon#about to read 3, iclass 40, count 0 2006.162.08:02:47.39#ibcon#read 3, iclass 40, count 0 2006.162.08:02:47.39#ibcon#about to read 4, iclass 40, count 0 2006.162.08:02:47.39#ibcon#read 4, iclass 40, count 0 2006.162.08:02:47.39#ibcon#about to read 5, iclass 40, count 0 2006.162.08:02:47.39#ibcon#read 5, iclass 40, count 0 2006.162.08:02:47.39#ibcon#about to read 6, iclass 40, count 0 2006.162.08:02:47.39#ibcon#read 6, iclass 40, count 0 2006.162.08:02:47.39#ibcon#end of sib2, iclass 40, count 0 2006.162.08:02:47.39#ibcon#*after write, iclass 40, count 0 2006.162.08:02:47.39#ibcon#*before return 0, iclass 40, count 0 2006.162.08:02:47.39#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:02:47.39#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:02:47.39#ibcon#about to clear, iclass 40 cls_cnt 0 2006.162.08:02:47.39#ibcon#cleared, iclass 40 cls_cnt 0 2006.162.08:02:47.39$vc4f8/vbbw=wide 2006.162.08:02:47.39#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.162.08:02:47.39#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.162.08:02:47.39#ibcon#ireg 8 cls_cnt 0 2006.162.08:02:47.39#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:02:47.47#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:02:47.47#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:02:47.47#ibcon#enter wrdev, iclass 4, count 0 2006.162.08:02:47.47#ibcon#first serial, iclass 4, count 0 2006.162.08:02:47.47#ibcon#enter sib2, iclass 4, count 0 2006.162.08:02:47.47#ibcon#flushed, iclass 4, count 0 2006.162.08:02:47.47#ibcon#about to write, iclass 4, count 0 2006.162.08:02:47.47#ibcon#wrote, iclass 4, count 0 2006.162.08:02:47.47#ibcon#about to read 3, iclass 4, count 0 2006.162.08:02:47.48#ibcon#read 3, iclass 4, count 0 2006.162.08:02:47.48#ibcon#about to read 4, iclass 4, count 0 2006.162.08:02:47.48#ibcon#read 4, iclass 4, count 0 2006.162.08:02:47.48#ibcon#about to read 5, iclass 4, count 0 2006.162.08:02:47.48#ibcon#read 5, iclass 4, count 0 2006.162.08:02:47.48#ibcon#about to read 6, iclass 4, count 0 2006.162.08:02:47.48#ibcon#read 6, iclass 4, count 0 2006.162.08:02:47.48#ibcon#end of sib2, iclass 4, count 0 2006.162.08:02:47.48#ibcon#*mode == 0, iclass 4, count 0 2006.162.08:02:47.48#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.162.08:02:47.48#ibcon#[27=BW32\r\n] 2006.162.08:02:47.48#ibcon#*before write, iclass 4, count 0 2006.162.08:02:47.48#ibcon#enter sib2, iclass 4, count 0 2006.162.08:02:47.48#ibcon#flushed, iclass 4, count 0 2006.162.08:02:47.48#ibcon#about to write, iclass 4, count 0 2006.162.08:02:47.48#ibcon#wrote, iclass 4, count 0 2006.162.08:02:47.48#ibcon#about to read 3, iclass 4, count 0 2006.162.08:02:47.51#ibcon#read 3, iclass 4, count 0 2006.162.08:02:47.51#ibcon#about to read 4, iclass 4, count 0 2006.162.08:02:47.51#ibcon#read 4, iclass 4, count 0 2006.162.08:02:47.51#ibcon#about to read 5, iclass 4, count 0 2006.162.08:02:47.51#ibcon#read 5, iclass 4, count 0 2006.162.08:02:47.51#ibcon#about to read 6, iclass 4, count 0 2006.162.08:02:47.51#ibcon#read 6, iclass 4, count 0 2006.162.08:02:47.51#ibcon#end of sib2, iclass 4, count 0 2006.162.08:02:47.51#ibcon#*after write, iclass 4, count 0 2006.162.08:02:47.51#ibcon#*before return 0, iclass 4, count 0 2006.162.08:02:47.51#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:02:47.51#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:02:47.51#ibcon#about to clear, iclass 4 cls_cnt 0 2006.162.08:02:47.51#ibcon#cleared, iclass 4 cls_cnt 0 2006.162.08:02:47.51$4f8m12a/ifd4f 2006.162.08:02:47.51$ifd4f/lo= 2006.162.08:02:47.51$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.08:02:47.51$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.08:02:47.51$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.08:02:47.51$ifd4f/patch= 2006.162.08:02:47.51$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.08:02:47.51$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.08:02:47.51$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.08:02:47.51$4f8m12a/"form=m,16.000,1:2 2006.162.08:02:47.51$4f8m12a/"tpicd 2006.162.08:02:47.51$4f8m12a/echo=off 2006.162.08:02:47.51$4f8m12a/xlog=off 2006.162.08:02:47.51:!2006.162.08:03:10 2006.162.08:02:48.14#trakl#Source acquired 2006.162.08:02:48.14#flagr#flagr/antenna,acquired 2006.162.08:03:10.00:preob 2006.162.08:03:10.14/onsource/TRACKING 2006.162.08:03:10.14:!2006.162.08:03:20 2006.162.08:03:20.00:data_valid=on 2006.162.08:03:20.00:midob 2006.162.08:03:21.14/onsource/TRACKING 2006.162.08:03:21.14/wx/17.85,1007.0,100 2006.162.08:03:21.21/cable/+6.5370E-03 2006.162.08:03:22.30/va/01,08,usb,yes,35,37 2006.162.08:03:22.30/va/02,07,usb,yes,36,37 2006.162.08:03:22.30/va/03,06,usb,yes,37,38 2006.162.08:03:22.30/va/04,07,usb,yes,36,39 2006.162.08:03:22.30/va/05,07,usb,yes,38,41 2006.162.08:03:22.30/va/06,06,usb,yes,38,37 2006.162.08:03:22.30/va/07,06,usb,yes,38,38 2006.162.08:03:22.30/va/08,07,usb,yes,36,36 2006.162.08:03:22.53/valo/01,532.99,yes,locked 2006.162.08:03:22.53/valo/02,572.99,yes,locked 2006.162.08:03:22.53/valo/03,672.99,yes,locked 2006.162.08:03:22.53/valo/04,832.99,yes,locked 2006.162.08:03:22.53/valo/05,652.99,yes,locked 2006.162.08:03:22.53/valo/06,772.99,yes,locked 2006.162.08:03:22.53/valo/07,832.99,yes,locked 2006.162.08:03:22.53/valo/08,852.99,yes,locked 2006.162.08:03:23.62/vb/01,04,usb,yes,29,27 2006.162.08:03:23.62/vb/02,04,usb,yes,31,32 2006.162.08:03:23.62/vb/03,04,usb,yes,27,31 2006.162.08:03:23.62/vb/04,04,usb,yes,28,28 2006.162.08:03:23.62/vb/05,04,usb,yes,26,30 2006.162.08:03:23.62/vb/06,04,usb,yes,27,30 2006.162.08:03:23.62/vb/07,04,usb,yes,29,29 2006.162.08:03:23.62/vb/08,04,usb,yes,27,30 2006.162.08:03:23.85/vblo/01,632.99,yes,locked 2006.162.08:03:23.85/vblo/02,640.99,yes,locked 2006.162.08:03:23.85/vblo/03,656.99,yes,locked 2006.162.08:03:23.85/vblo/04,712.99,yes,locked 2006.162.08:03:23.85/vblo/05,744.99,yes,locked 2006.162.08:03:23.85/vblo/06,752.99,yes,locked 2006.162.08:03:23.85/vblo/07,734.99,yes,locked 2006.162.08:03:23.85/vblo/08,744.99,yes,locked 2006.162.08:03:24.00/vabw/8 2006.162.08:03:24.15/vbbw/8 2006.162.08:03:24.30/xfe/off,on,15.0 2006.162.08:03:24.68/ifatt/23,28,28,28 2006.162.08:03:25.08/fmout-gps/S +4.49E-07 2006.162.08:03:25.16:!2006.162.08:04:20 2006.162.08:04:20.01:data_valid=off 2006.162.08:04:20.02:postob 2006.162.08:04:20.20/cable/+6.5382E-03 2006.162.08:04:20.21/wx/17.86,1007.0,100 2006.162.08:04:21.07/fmout-gps/S +4.50E-07 2006.162.08:04:21.08:scan_name=162-0805,k06162,60 2006.162.08:04:21.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.162.08:04:21.14#flagr#flagr/antenna,new-source 2006.162.08:04:22.14:checkk5 2006.162.08:04:22.53/chk_autoobs//k5ts1/ autoobs is running! 2006.162.08:04:22.96/chk_autoobs//k5ts2/ autoobs is running! 2006.162.08:04:23.37/chk_autoobs//k5ts3/ autoobs is running! 2006.162.08:04:23.85/chk_autoobs//k5ts4/ autoobs is running! 2006.162.08:04:24.24/chk_obsdata//k5ts1/T1620803??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:04:24.62/chk_obsdata//k5ts2/T1620803??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:04:25.07/chk_obsdata//k5ts3/T1620803??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:04:25.52/chk_obsdata//k5ts4/T1620803??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:04:26.29/k5log//k5ts1_log_newline 2006.162.08:04:27.32/k5log//k5ts2_log_newline 2006.162.08:04:28.06/k5log//k5ts3_log_newline 2006.162.08:04:28.86/k5log//k5ts4_log_newline 2006.162.08:04:28.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.08:04:28.89:4f8m12a=2 2006.162.08:04:28.89$4f8m12a/echo=on 2006.162.08:04:28.89$4f8m12a/pcalon 2006.162.08:04:28.89$pcalon/"no phase cal control is implemented here 2006.162.08:04:28.89$4f8m12a/"tpicd=stop 2006.162.08:04:28.89$4f8m12a/vc4f8 2006.162.08:04:28.89$vc4f8/valo=1,532.99 2006.162.08:04:28.89#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.162.08:04:28.89#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.162.08:04:28.89#ibcon#ireg 17 cls_cnt 0 2006.162.08:04:28.89#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.162.08:04:28.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.162.08:04:28.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.162.08:04:28.89#ibcon#enter wrdev, iclass 13, count 0 2006.162.08:04:28.89#ibcon#first serial, iclass 13, count 0 2006.162.08:04:28.89#ibcon#enter sib2, iclass 13, count 0 2006.162.08:04:28.89#ibcon#flushed, iclass 13, count 0 2006.162.08:04:28.89#ibcon#about to write, iclass 13, count 0 2006.162.08:04:28.89#ibcon#wrote, iclass 13, count 0 2006.162.08:04:28.89#ibcon#about to read 3, iclass 13, count 0 2006.162.08:04:28.94#ibcon#read 3, iclass 13, count 0 2006.162.08:04:28.94#ibcon#about to read 4, iclass 13, count 0 2006.162.08:04:28.94#ibcon#read 4, iclass 13, count 0 2006.162.08:04:28.94#ibcon#about to read 5, iclass 13, count 0 2006.162.08:04:28.94#ibcon#read 5, iclass 13, count 0 2006.162.08:04:28.94#ibcon#about to read 6, iclass 13, count 0 2006.162.08:04:28.94#ibcon#read 6, iclass 13, count 0 2006.162.08:04:28.94#ibcon#end of sib2, iclass 13, count 0 2006.162.08:04:28.94#ibcon#*mode == 0, iclass 13, count 0 2006.162.08:04:28.94#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.162.08:04:28.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.08:04:28.94#ibcon#*before write, iclass 13, count 0 2006.162.08:04:28.94#ibcon#enter sib2, iclass 13, count 0 2006.162.08:04:28.94#ibcon#flushed, iclass 13, count 0 2006.162.08:04:28.94#ibcon#about to write, iclass 13, count 0 2006.162.08:04:28.94#ibcon#wrote, iclass 13, count 0 2006.162.08:04:28.94#ibcon#about to read 3, iclass 13, count 0 2006.162.08:04:28.98#ibcon#read 3, iclass 13, count 0 2006.162.08:04:28.98#ibcon#about to read 4, iclass 13, count 0 2006.162.08:04:28.98#ibcon#read 4, iclass 13, count 0 2006.162.08:04:28.98#ibcon#about to read 5, iclass 13, count 0 2006.162.08:04:28.98#ibcon#read 5, iclass 13, count 0 2006.162.08:04:28.98#ibcon#about to read 6, iclass 13, count 0 2006.162.08:04:28.98#ibcon#read 6, iclass 13, count 0 2006.162.08:04:28.98#ibcon#end of sib2, iclass 13, count 0 2006.162.08:04:28.98#ibcon#*after write, iclass 13, count 0 2006.162.08:04:28.98#ibcon#*before return 0, iclass 13, count 0 2006.162.08:04:28.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.162.08:04:28.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.162.08:04:28.98#ibcon#about to clear, iclass 13 cls_cnt 0 2006.162.08:04:28.98#ibcon#cleared, iclass 13 cls_cnt 0 2006.162.08:04:28.98$vc4f8/va=1,8 2006.162.08:04:28.98#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.162.08:04:28.98#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.162.08:04:28.98#ibcon#ireg 11 cls_cnt 2 2006.162.08:04:28.98#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.162.08:04:28.98#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.162.08:04:28.98#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.162.08:04:28.98#ibcon#enter wrdev, iclass 15, count 2 2006.162.08:04:28.98#ibcon#first serial, iclass 15, count 2 2006.162.08:04:28.98#ibcon#enter sib2, iclass 15, count 2 2006.162.08:04:28.98#ibcon#flushed, iclass 15, count 2 2006.162.08:04:28.98#ibcon#about to write, iclass 15, count 2 2006.162.08:04:28.98#ibcon#wrote, iclass 15, count 2 2006.162.08:04:28.98#ibcon#about to read 3, iclass 15, count 2 2006.162.08:04:29.00#ibcon#read 3, iclass 15, count 2 2006.162.08:04:29.00#ibcon#about to read 4, iclass 15, count 2 2006.162.08:04:29.00#ibcon#read 4, iclass 15, count 2 2006.162.08:04:29.00#ibcon#about to read 5, iclass 15, count 2 2006.162.08:04:29.00#ibcon#read 5, iclass 15, count 2 2006.162.08:04:29.00#ibcon#about to read 6, iclass 15, count 2 2006.162.08:04:29.00#ibcon#read 6, iclass 15, count 2 2006.162.08:04:29.00#ibcon#end of sib2, iclass 15, count 2 2006.162.08:04:29.00#ibcon#*mode == 0, iclass 15, count 2 2006.162.08:04:29.00#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.162.08:04:29.00#ibcon#[25=AT01-08\r\n] 2006.162.08:04:29.00#ibcon#*before write, iclass 15, count 2 2006.162.08:04:29.00#ibcon#enter sib2, iclass 15, count 2 2006.162.08:04:29.00#ibcon#flushed, iclass 15, count 2 2006.162.08:04:29.00#ibcon#about to write, iclass 15, count 2 2006.162.08:04:29.00#ibcon#wrote, iclass 15, count 2 2006.162.08:04:29.00#ibcon#about to read 3, iclass 15, count 2 2006.162.08:04:29.03#ibcon#read 3, iclass 15, count 2 2006.162.08:04:29.03#ibcon#about to read 4, iclass 15, count 2 2006.162.08:04:29.03#ibcon#read 4, iclass 15, count 2 2006.162.08:04:29.03#ibcon#about to read 5, iclass 15, count 2 2006.162.08:04:29.03#ibcon#read 5, iclass 15, count 2 2006.162.08:04:29.03#ibcon#about to read 6, iclass 15, count 2 2006.162.08:04:29.03#ibcon#read 6, iclass 15, count 2 2006.162.08:04:29.03#ibcon#end of sib2, iclass 15, count 2 2006.162.08:04:29.03#ibcon#*after write, iclass 15, count 2 2006.162.08:04:29.03#ibcon#*before return 0, iclass 15, count 2 2006.162.08:04:29.03#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.162.08:04:29.03#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.162.08:04:29.03#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.162.08:04:29.03#ibcon#ireg 7 cls_cnt 0 2006.162.08:04:29.03#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.162.08:04:29.15#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.162.08:04:29.15#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.162.08:04:29.15#ibcon#enter wrdev, iclass 15, count 0 2006.162.08:04:29.15#ibcon#first serial, iclass 15, count 0 2006.162.08:04:29.15#ibcon#enter sib2, iclass 15, count 0 2006.162.08:04:29.15#ibcon#flushed, iclass 15, count 0 2006.162.08:04:29.15#ibcon#about to write, iclass 15, count 0 2006.162.08:04:29.15#ibcon#wrote, iclass 15, count 0 2006.162.08:04:29.15#ibcon#about to read 3, iclass 15, count 0 2006.162.08:04:29.17#ibcon#read 3, iclass 15, count 0 2006.162.08:04:29.17#ibcon#about to read 4, iclass 15, count 0 2006.162.08:04:29.17#ibcon#read 4, iclass 15, count 0 2006.162.08:04:29.17#ibcon#about to read 5, iclass 15, count 0 2006.162.08:04:29.17#ibcon#read 5, iclass 15, count 0 2006.162.08:04:29.17#ibcon#about to read 6, iclass 15, count 0 2006.162.08:04:29.17#ibcon#read 6, iclass 15, count 0 2006.162.08:04:29.17#ibcon#end of sib2, iclass 15, count 0 2006.162.08:04:29.17#ibcon#*mode == 0, iclass 15, count 0 2006.162.08:04:29.17#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.162.08:04:29.17#ibcon#[25=USB\r\n] 2006.162.08:04:29.17#ibcon#*before write, iclass 15, count 0 2006.162.08:04:29.17#ibcon#enter sib2, iclass 15, count 0 2006.162.08:04:29.17#ibcon#flushed, iclass 15, count 0 2006.162.08:04:29.17#ibcon#about to write, iclass 15, count 0 2006.162.08:04:29.17#ibcon#wrote, iclass 15, count 0 2006.162.08:04:29.17#ibcon#about to read 3, iclass 15, count 0 2006.162.08:04:29.20#ibcon#read 3, iclass 15, count 0 2006.162.08:04:29.20#ibcon#about to read 4, iclass 15, count 0 2006.162.08:04:29.20#ibcon#read 4, iclass 15, count 0 2006.162.08:04:29.20#ibcon#about to read 5, iclass 15, count 0 2006.162.08:04:29.20#ibcon#read 5, iclass 15, count 0 2006.162.08:04:29.20#ibcon#about to read 6, iclass 15, count 0 2006.162.08:04:29.20#ibcon#read 6, iclass 15, count 0 2006.162.08:04:29.20#ibcon#end of sib2, iclass 15, count 0 2006.162.08:04:29.20#ibcon#*after write, iclass 15, count 0 2006.162.08:04:29.20#ibcon#*before return 0, iclass 15, count 0 2006.162.08:04:29.20#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.162.08:04:29.20#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.162.08:04:29.20#ibcon#about to clear, iclass 15 cls_cnt 0 2006.162.08:04:29.20#ibcon#cleared, iclass 15 cls_cnt 0 2006.162.08:04:29.20$vc4f8/valo=2,572.99 2006.162.08:04:29.20#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.162.08:04:29.20#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.162.08:04:29.20#ibcon#ireg 17 cls_cnt 0 2006.162.08:04:29.20#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.162.08:04:29.20#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.162.08:04:29.20#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.162.08:04:29.20#ibcon#enter wrdev, iclass 17, count 0 2006.162.08:04:29.20#ibcon#first serial, iclass 17, count 0 2006.162.08:04:29.20#ibcon#enter sib2, iclass 17, count 0 2006.162.08:04:29.20#ibcon#flushed, iclass 17, count 0 2006.162.08:04:29.20#ibcon#about to write, iclass 17, count 0 2006.162.08:04:29.20#ibcon#wrote, iclass 17, count 0 2006.162.08:04:29.20#ibcon#about to read 3, iclass 17, count 0 2006.162.08:04:29.22#ibcon#read 3, iclass 17, count 0 2006.162.08:04:29.22#ibcon#about to read 4, iclass 17, count 0 2006.162.08:04:29.22#ibcon#read 4, iclass 17, count 0 2006.162.08:04:29.22#ibcon#about to read 5, iclass 17, count 0 2006.162.08:04:29.22#ibcon#read 5, iclass 17, count 0 2006.162.08:04:29.22#ibcon#about to read 6, iclass 17, count 0 2006.162.08:04:29.22#ibcon#read 6, iclass 17, count 0 2006.162.08:04:29.22#ibcon#end of sib2, iclass 17, count 0 2006.162.08:04:29.22#ibcon#*mode == 0, iclass 17, count 0 2006.162.08:04:29.22#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.162.08:04:29.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.08:04:29.22#ibcon#*before write, iclass 17, count 0 2006.162.08:04:29.22#ibcon#enter sib2, iclass 17, count 0 2006.162.08:04:29.22#ibcon#flushed, iclass 17, count 0 2006.162.08:04:29.22#ibcon#about to write, iclass 17, count 0 2006.162.08:04:29.22#ibcon#wrote, iclass 17, count 0 2006.162.08:04:29.22#ibcon#about to read 3, iclass 17, count 0 2006.162.08:04:29.26#ibcon#read 3, iclass 17, count 0 2006.162.08:04:29.26#ibcon#about to read 4, iclass 17, count 0 2006.162.08:04:29.26#ibcon#read 4, iclass 17, count 0 2006.162.08:04:29.26#ibcon#about to read 5, iclass 17, count 0 2006.162.08:04:29.26#ibcon#read 5, iclass 17, count 0 2006.162.08:04:29.26#ibcon#about to read 6, iclass 17, count 0 2006.162.08:04:29.26#ibcon#read 6, iclass 17, count 0 2006.162.08:04:29.26#ibcon#end of sib2, iclass 17, count 0 2006.162.08:04:29.26#ibcon#*after write, iclass 17, count 0 2006.162.08:04:29.26#ibcon#*before return 0, iclass 17, count 0 2006.162.08:04:29.26#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.162.08:04:29.26#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.162.08:04:29.26#ibcon#about to clear, iclass 17 cls_cnt 0 2006.162.08:04:29.26#ibcon#cleared, iclass 17 cls_cnt 0 2006.162.08:04:29.26$vc4f8/va=2,7 2006.162.08:04:29.26#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.162.08:04:29.26#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.162.08:04:29.26#ibcon#ireg 11 cls_cnt 2 2006.162.08:04:29.26#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.162.08:04:29.33#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.162.08:04:29.33#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.162.08:04:29.33#ibcon#enter wrdev, iclass 19, count 2 2006.162.08:04:29.33#ibcon#first serial, iclass 19, count 2 2006.162.08:04:29.33#ibcon#enter sib2, iclass 19, count 2 2006.162.08:04:29.33#ibcon#flushed, iclass 19, count 2 2006.162.08:04:29.33#ibcon#about to write, iclass 19, count 2 2006.162.08:04:29.33#ibcon#wrote, iclass 19, count 2 2006.162.08:04:29.33#ibcon#about to read 3, iclass 19, count 2 2006.162.08:04:29.34#ibcon#read 3, iclass 19, count 2 2006.162.08:04:29.34#ibcon#about to read 4, iclass 19, count 2 2006.162.08:04:29.34#ibcon#read 4, iclass 19, count 2 2006.162.08:04:29.34#ibcon#about to read 5, iclass 19, count 2 2006.162.08:04:29.34#ibcon#read 5, iclass 19, count 2 2006.162.08:04:29.34#ibcon#about to read 6, iclass 19, count 2 2006.162.08:04:29.34#ibcon#read 6, iclass 19, count 2 2006.162.08:04:29.34#ibcon#end of sib2, iclass 19, count 2 2006.162.08:04:29.34#ibcon#*mode == 0, iclass 19, count 2 2006.162.08:04:29.34#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.162.08:04:29.34#ibcon#[25=AT02-07\r\n] 2006.162.08:04:29.34#ibcon#*before write, iclass 19, count 2 2006.162.08:04:29.34#ibcon#enter sib2, iclass 19, count 2 2006.162.08:04:29.34#ibcon#flushed, iclass 19, count 2 2006.162.08:04:29.34#ibcon#about to write, iclass 19, count 2 2006.162.08:04:29.34#ibcon#wrote, iclass 19, count 2 2006.162.08:04:29.34#ibcon#about to read 3, iclass 19, count 2 2006.162.08:04:29.37#ibcon#read 3, iclass 19, count 2 2006.162.08:04:29.37#ibcon#about to read 4, iclass 19, count 2 2006.162.08:04:29.37#ibcon#read 4, iclass 19, count 2 2006.162.08:04:29.37#ibcon#about to read 5, iclass 19, count 2 2006.162.08:04:29.37#ibcon#read 5, iclass 19, count 2 2006.162.08:04:29.37#ibcon#about to read 6, iclass 19, count 2 2006.162.08:04:29.37#ibcon#read 6, iclass 19, count 2 2006.162.08:04:29.37#ibcon#end of sib2, iclass 19, count 2 2006.162.08:04:29.37#ibcon#*after write, iclass 19, count 2 2006.162.08:04:29.37#ibcon#*before return 0, iclass 19, count 2 2006.162.08:04:29.37#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.162.08:04:29.37#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.162.08:04:29.37#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.162.08:04:29.37#ibcon#ireg 7 cls_cnt 0 2006.162.08:04:29.37#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.162.08:04:29.49#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.162.08:04:29.49#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.162.08:04:29.49#ibcon#enter wrdev, iclass 19, count 0 2006.162.08:04:29.49#ibcon#first serial, iclass 19, count 0 2006.162.08:04:29.49#ibcon#enter sib2, iclass 19, count 0 2006.162.08:04:29.49#ibcon#flushed, iclass 19, count 0 2006.162.08:04:29.49#ibcon#about to write, iclass 19, count 0 2006.162.08:04:29.49#ibcon#wrote, iclass 19, count 0 2006.162.08:04:29.49#ibcon#about to read 3, iclass 19, count 0 2006.162.08:04:29.51#ibcon#read 3, iclass 19, count 0 2006.162.08:04:29.51#ibcon#about to read 4, iclass 19, count 0 2006.162.08:04:29.51#ibcon#read 4, iclass 19, count 0 2006.162.08:04:29.51#ibcon#about to read 5, iclass 19, count 0 2006.162.08:04:29.51#ibcon#read 5, iclass 19, count 0 2006.162.08:04:29.51#ibcon#about to read 6, iclass 19, count 0 2006.162.08:04:29.51#ibcon#read 6, iclass 19, count 0 2006.162.08:04:29.51#ibcon#end of sib2, iclass 19, count 0 2006.162.08:04:29.51#ibcon#*mode == 0, iclass 19, count 0 2006.162.08:04:29.51#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.162.08:04:29.51#ibcon#[25=USB\r\n] 2006.162.08:04:29.51#ibcon#*before write, iclass 19, count 0 2006.162.08:04:29.51#ibcon#enter sib2, iclass 19, count 0 2006.162.08:04:29.51#ibcon#flushed, iclass 19, count 0 2006.162.08:04:29.51#ibcon#about to write, iclass 19, count 0 2006.162.08:04:29.51#ibcon#wrote, iclass 19, count 0 2006.162.08:04:29.51#ibcon#about to read 3, iclass 19, count 0 2006.162.08:04:29.54#ibcon#read 3, iclass 19, count 0 2006.162.08:04:29.54#ibcon#about to read 4, iclass 19, count 0 2006.162.08:04:29.54#ibcon#read 4, iclass 19, count 0 2006.162.08:04:29.54#ibcon#about to read 5, iclass 19, count 0 2006.162.08:04:29.54#ibcon#read 5, iclass 19, count 0 2006.162.08:04:29.54#ibcon#about to read 6, iclass 19, count 0 2006.162.08:04:29.54#ibcon#read 6, iclass 19, count 0 2006.162.08:04:29.54#ibcon#end of sib2, iclass 19, count 0 2006.162.08:04:29.54#ibcon#*after write, iclass 19, count 0 2006.162.08:04:29.54#ibcon#*before return 0, iclass 19, count 0 2006.162.08:04:29.54#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.162.08:04:29.54#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.162.08:04:29.54#ibcon#about to clear, iclass 19 cls_cnt 0 2006.162.08:04:29.54#ibcon#cleared, iclass 19 cls_cnt 0 2006.162.08:04:29.54$vc4f8/valo=3,672.99 2006.162.08:04:29.54#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.162.08:04:29.54#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.162.08:04:29.54#ibcon#ireg 17 cls_cnt 0 2006.162.08:04:29.54#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:04:29.54#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:04:29.54#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:04:29.54#ibcon#enter wrdev, iclass 21, count 0 2006.162.08:04:29.54#ibcon#first serial, iclass 21, count 0 2006.162.08:04:29.54#ibcon#enter sib2, iclass 21, count 0 2006.162.08:04:29.54#ibcon#flushed, iclass 21, count 0 2006.162.08:04:29.54#ibcon#about to write, iclass 21, count 0 2006.162.08:04:29.54#ibcon#wrote, iclass 21, count 0 2006.162.08:04:29.54#ibcon#about to read 3, iclass 21, count 0 2006.162.08:04:29.56#ibcon#read 3, iclass 21, count 0 2006.162.08:04:29.56#ibcon#about to read 4, iclass 21, count 0 2006.162.08:04:29.56#ibcon#read 4, iclass 21, count 0 2006.162.08:04:29.56#ibcon#about to read 5, iclass 21, count 0 2006.162.08:04:29.56#ibcon#read 5, iclass 21, count 0 2006.162.08:04:29.56#ibcon#about to read 6, iclass 21, count 0 2006.162.08:04:29.56#ibcon#read 6, iclass 21, count 0 2006.162.08:04:29.56#ibcon#end of sib2, iclass 21, count 0 2006.162.08:04:29.56#ibcon#*mode == 0, iclass 21, count 0 2006.162.08:04:29.56#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.162.08:04:29.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.08:04:29.56#ibcon#*before write, iclass 21, count 0 2006.162.08:04:29.56#ibcon#enter sib2, iclass 21, count 0 2006.162.08:04:29.56#ibcon#flushed, iclass 21, count 0 2006.162.08:04:29.56#ibcon#about to write, iclass 21, count 0 2006.162.08:04:29.56#ibcon#wrote, iclass 21, count 0 2006.162.08:04:29.56#ibcon#about to read 3, iclass 21, count 0 2006.162.08:04:29.60#ibcon#read 3, iclass 21, count 0 2006.162.08:04:29.60#ibcon#about to read 4, iclass 21, count 0 2006.162.08:04:29.60#ibcon#read 4, iclass 21, count 0 2006.162.08:04:29.60#ibcon#about to read 5, iclass 21, count 0 2006.162.08:04:29.60#ibcon#read 5, iclass 21, count 0 2006.162.08:04:29.60#ibcon#about to read 6, iclass 21, count 0 2006.162.08:04:29.60#ibcon#read 6, iclass 21, count 0 2006.162.08:04:29.60#ibcon#end of sib2, iclass 21, count 0 2006.162.08:04:29.60#ibcon#*after write, iclass 21, count 0 2006.162.08:04:29.60#ibcon#*before return 0, iclass 21, count 0 2006.162.08:04:29.60#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:04:29.60#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:04:29.60#ibcon#about to clear, iclass 21 cls_cnt 0 2006.162.08:04:29.60#ibcon#cleared, iclass 21 cls_cnt 0 2006.162.08:04:29.60$vc4f8/va=3,6 2006.162.08:04:29.60#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.162.08:04:29.60#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.162.08:04:29.60#ibcon#ireg 11 cls_cnt 2 2006.162.08:04:29.60#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:04:29.66#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:04:29.66#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:04:29.66#ibcon#enter wrdev, iclass 23, count 2 2006.162.08:04:29.66#ibcon#first serial, iclass 23, count 2 2006.162.08:04:29.66#ibcon#enter sib2, iclass 23, count 2 2006.162.08:04:29.66#ibcon#flushed, iclass 23, count 2 2006.162.08:04:29.66#ibcon#about to write, iclass 23, count 2 2006.162.08:04:29.66#ibcon#wrote, iclass 23, count 2 2006.162.08:04:29.66#ibcon#about to read 3, iclass 23, count 2 2006.162.08:04:29.69#ibcon#read 3, iclass 23, count 2 2006.162.08:04:29.69#ibcon#about to read 4, iclass 23, count 2 2006.162.08:04:29.69#ibcon#read 4, iclass 23, count 2 2006.162.08:04:29.69#ibcon#about to read 5, iclass 23, count 2 2006.162.08:04:29.69#ibcon#read 5, iclass 23, count 2 2006.162.08:04:29.69#ibcon#about to read 6, iclass 23, count 2 2006.162.08:04:29.69#ibcon#read 6, iclass 23, count 2 2006.162.08:04:29.69#ibcon#end of sib2, iclass 23, count 2 2006.162.08:04:29.69#ibcon#*mode == 0, iclass 23, count 2 2006.162.08:04:29.69#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.162.08:04:29.69#ibcon#[25=AT03-06\r\n] 2006.162.08:04:29.69#ibcon#*before write, iclass 23, count 2 2006.162.08:04:29.69#ibcon#enter sib2, iclass 23, count 2 2006.162.08:04:29.69#ibcon#flushed, iclass 23, count 2 2006.162.08:04:29.69#ibcon#about to write, iclass 23, count 2 2006.162.08:04:29.69#ibcon#wrote, iclass 23, count 2 2006.162.08:04:29.69#ibcon#about to read 3, iclass 23, count 2 2006.162.08:04:29.72#ibcon#read 3, iclass 23, count 2 2006.162.08:04:29.72#ibcon#about to read 4, iclass 23, count 2 2006.162.08:04:29.72#ibcon#read 4, iclass 23, count 2 2006.162.08:04:29.72#ibcon#about to read 5, iclass 23, count 2 2006.162.08:04:29.72#ibcon#read 5, iclass 23, count 2 2006.162.08:04:29.72#ibcon#about to read 6, iclass 23, count 2 2006.162.08:04:29.72#ibcon#read 6, iclass 23, count 2 2006.162.08:04:29.72#ibcon#end of sib2, iclass 23, count 2 2006.162.08:04:29.72#ibcon#*after write, iclass 23, count 2 2006.162.08:04:29.72#ibcon#*before return 0, iclass 23, count 2 2006.162.08:04:29.72#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:04:29.72#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:04:29.72#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.162.08:04:29.72#ibcon#ireg 7 cls_cnt 0 2006.162.08:04:29.72#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:04:29.84#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:04:29.84#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:04:29.84#ibcon#enter wrdev, iclass 23, count 0 2006.162.08:04:29.84#ibcon#first serial, iclass 23, count 0 2006.162.08:04:29.84#ibcon#enter sib2, iclass 23, count 0 2006.162.08:04:29.84#ibcon#flushed, iclass 23, count 0 2006.162.08:04:29.84#ibcon#about to write, iclass 23, count 0 2006.162.08:04:29.84#ibcon#wrote, iclass 23, count 0 2006.162.08:04:29.84#ibcon#about to read 3, iclass 23, count 0 2006.162.08:04:29.86#ibcon#read 3, iclass 23, count 0 2006.162.08:04:29.86#ibcon#about to read 4, iclass 23, count 0 2006.162.08:04:29.86#ibcon#read 4, iclass 23, count 0 2006.162.08:04:29.86#ibcon#about to read 5, iclass 23, count 0 2006.162.08:04:29.86#ibcon#read 5, iclass 23, count 0 2006.162.08:04:29.86#ibcon#about to read 6, iclass 23, count 0 2006.162.08:04:29.86#ibcon#read 6, iclass 23, count 0 2006.162.08:04:29.86#ibcon#end of sib2, iclass 23, count 0 2006.162.08:04:29.86#ibcon#*mode == 0, iclass 23, count 0 2006.162.08:04:29.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.162.08:04:29.86#ibcon#[25=USB\r\n] 2006.162.08:04:29.86#ibcon#*before write, iclass 23, count 0 2006.162.08:04:29.86#ibcon#enter sib2, iclass 23, count 0 2006.162.08:04:29.86#ibcon#flushed, iclass 23, count 0 2006.162.08:04:29.86#ibcon#about to write, iclass 23, count 0 2006.162.08:04:29.86#ibcon#wrote, iclass 23, count 0 2006.162.08:04:29.86#ibcon#about to read 3, iclass 23, count 0 2006.162.08:04:29.89#ibcon#read 3, iclass 23, count 0 2006.162.08:04:29.89#ibcon#about to read 4, iclass 23, count 0 2006.162.08:04:29.89#ibcon#read 4, iclass 23, count 0 2006.162.08:04:29.89#ibcon#about to read 5, iclass 23, count 0 2006.162.08:04:29.89#ibcon#read 5, iclass 23, count 0 2006.162.08:04:29.89#ibcon#about to read 6, iclass 23, count 0 2006.162.08:04:29.89#ibcon#read 6, iclass 23, count 0 2006.162.08:04:29.89#ibcon#end of sib2, iclass 23, count 0 2006.162.08:04:29.89#ibcon#*after write, iclass 23, count 0 2006.162.08:04:29.89#ibcon#*before return 0, iclass 23, count 0 2006.162.08:04:29.89#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:04:29.89#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:04:29.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.162.08:04:29.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.162.08:04:29.89$vc4f8/valo=4,832.99 2006.162.08:04:29.89#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.162.08:04:29.89#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.162.08:04:29.89#ibcon#ireg 17 cls_cnt 0 2006.162.08:04:29.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:04:29.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:04:29.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:04:29.89#ibcon#enter wrdev, iclass 25, count 0 2006.162.08:04:29.89#ibcon#first serial, iclass 25, count 0 2006.162.08:04:29.89#ibcon#enter sib2, iclass 25, count 0 2006.162.08:04:29.89#ibcon#flushed, iclass 25, count 0 2006.162.08:04:29.89#ibcon#about to write, iclass 25, count 0 2006.162.08:04:29.89#ibcon#wrote, iclass 25, count 0 2006.162.08:04:29.89#ibcon#about to read 3, iclass 25, count 0 2006.162.08:04:29.91#ibcon#read 3, iclass 25, count 0 2006.162.08:04:29.91#ibcon#about to read 4, iclass 25, count 0 2006.162.08:04:29.91#ibcon#read 4, iclass 25, count 0 2006.162.08:04:29.91#ibcon#about to read 5, iclass 25, count 0 2006.162.08:04:29.91#ibcon#read 5, iclass 25, count 0 2006.162.08:04:29.91#ibcon#about to read 6, iclass 25, count 0 2006.162.08:04:29.91#ibcon#read 6, iclass 25, count 0 2006.162.08:04:29.91#ibcon#end of sib2, iclass 25, count 0 2006.162.08:04:29.91#ibcon#*mode == 0, iclass 25, count 0 2006.162.08:04:29.91#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.162.08:04:29.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.08:04:29.91#ibcon#*before write, iclass 25, count 0 2006.162.08:04:29.91#ibcon#enter sib2, iclass 25, count 0 2006.162.08:04:29.91#ibcon#flushed, iclass 25, count 0 2006.162.08:04:29.91#ibcon#about to write, iclass 25, count 0 2006.162.08:04:29.91#ibcon#wrote, iclass 25, count 0 2006.162.08:04:29.91#ibcon#about to read 3, iclass 25, count 0 2006.162.08:04:29.95#ibcon#read 3, iclass 25, count 0 2006.162.08:04:29.95#ibcon#about to read 4, iclass 25, count 0 2006.162.08:04:29.95#ibcon#read 4, iclass 25, count 0 2006.162.08:04:29.95#ibcon#about to read 5, iclass 25, count 0 2006.162.08:04:29.95#ibcon#read 5, iclass 25, count 0 2006.162.08:04:29.95#ibcon#about to read 6, iclass 25, count 0 2006.162.08:04:29.95#ibcon#read 6, iclass 25, count 0 2006.162.08:04:29.95#ibcon#end of sib2, iclass 25, count 0 2006.162.08:04:29.95#ibcon#*after write, iclass 25, count 0 2006.162.08:04:29.95#ibcon#*before return 0, iclass 25, count 0 2006.162.08:04:29.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:04:29.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:04:29.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.162.08:04:29.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.162.08:04:29.95$vc4f8/va=4,7 2006.162.08:04:29.95#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.162.08:04:29.95#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.162.08:04:29.95#ibcon#ireg 11 cls_cnt 2 2006.162.08:04:29.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:04:30.01#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:04:30.01#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:04:30.01#ibcon#enter wrdev, iclass 27, count 2 2006.162.08:04:30.01#ibcon#first serial, iclass 27, count 2 2006.162.08:04:30.01#ibcon#enter sib2, iclass 27, count 2 2006.162.08:04:30.01#ibcon#flushed, iclass 27, count 2 2006.162.08:04:30.01#ibcon#about to write, iclass 27, count 2 2006.162.08:04:30.01#ibcon#wrote, iclass 27, count 2 2006.162.08:04:30.01#ibcon#about to read 3, iclass 27, count 2 2006.162.08:04:30.03#ibcon#read 3, iclass 27, count 2 2006.162.08:04:30.03#ibcon#about to read 4, iclass 27, count 2 2006.162.08:04:30.03#ibcon#read 4, iclass 27, count 2 2006.162.08:04:30.03#ibcon#about to read 5, iclass 27, count 2 2006.162.08:04:30.03#ibcon#read 5, iclass 27, count 2 2006.162.08:04:30.03#ibcon#about to read 6, iclass 27, count 2 2006.162.08:04:30.03#ibcon#read 6, iclass 27, count 2 2006.162.08:04:30.03#ibcon#end of sib2, iclass 27, count 2 2006.162.08:04:30.03#ibcon#*mode == 0, iclass 27, count 2 2006.162.08:04:30.03#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.162.08:04:30.03#ibcon#[25=AT04-07\r\n] 2006.162.08:04:30.03#ibcon#*before write, iclass 27, count 2 2006.162.08:04:30.03#ibcon#enter sib2, iclass 27, count 2 2006.162.08:04:30.03#ibcon#flushed, iclass 27, count 2 2006.162.08:04:30.03#ibcon#about to write, iclass 27, count 2 2006.162.08:04:30.03#ibcon#wrote, iclass 27, count 2 2006.162.08:04:30.03#ibcon#about to read 3, iclass 27, count 2 2006.162.08:04:30.06#ibcon#read 3, iclass 27, count 2 2006.162.08:04:30.06#ibcon#about to read 4, iclass 27, count 2 2006.162.08:04:30.06#ibcon#read 4, iclass 27, count 2 2006.162.08:04:30.06#ibcon#about to read 5, iclass 27, count 2 2006.162.08:04:30.06#ibcon#read 5, iclass 27, count 2 2006.162.08:04:30.06#ibcon#about to read 6, iclass 27, count 2 2006.162.08:04:30.06#ibcon#read 6, iclass 27, count 2 2006.162.08:04:30.06#ibcon#end of sib2, iclass 27, count 2 2006.162.08:04:30.06#ibcon#*after write, iclass 27, count 2 2006.162.08:04:30.06#ibcon#*before return 0, iclass 27, count 2 2006.162.08:04:30.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:04:30.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:04:30.06#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.162.08:04:30.06#ibcon#ireg 7 cls_cnt 0 2006.162.08:04:30.06#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:04:30.18#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:04:30.18#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:04:30.18#ibcon#enter wrdev, iclass 27, count 0 2006.162.08:04:30.18#ibcon#first serial, iclass 27, count 0 2006.162.08:04:30.18#ibcon#enter sib2, iclass 27, count 0 2006.162.08:04:30.18#ibcon#flushed, iclass 27, count 0 2006.162.08:04:30.18#ibcon#about to write, iclass 27, count 0 2006.162.08:04:30.18#ibcon#wrote, iclass 27, count 0 2006.162.08:04:30.18#ibcon#about to read 3, iclass 27, count 0 2006.162.08:04:30.20#ibcon#read 3, iclass 27, count 0 2006.162.08:04:30.20#ibcon#about to read 4, iclass 27, count 0 2006.162.08:04:30.20#ibcon#read 4, iclass 27, count 0 2006.162.08:04:30.20#ibcon#about to read 5, iclass 27, count 0 2006.162.08:04:30.20#ibcon#read 5, iclass 27, count 0 2006.162.08:04:30.20#ibcon#about to read 6, iclass 27, count 0 2006.162.08:04:30.20#ibcon#read 6, iclass 27, count 0 2006.162.08:04:30.20#ibcon#end of sib2, iclass 27, count 0 2006.162.08:04:30.20#ibcon#*mode == 0, iclass 27, count 0 2006.162.08:04:30.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.162.08:04:30.20#ibcon#[25=USB\r\n] 2006.162.08:04:30.20#ibcon#*before write, iclass 27, count 0 2006.162.08:04:30.20#ibcon#enter sib2, iclass 27, count 0 2006.162.08:04:30.20#ibcon#flushed, iclass 27, count 0 2006.162.08:04:30.20#ibcon#about to write, iclass 27, count 0 2006.162.08:04:30.20#ibcon#wrote, iclass 27, count 0 2006.162.08:04:30.20#ibcon#about to read 3, iclass 27, count 0 2006.162.08:04:30.23#ibcon#read 3, iclass 27, count 0 2006.162.08:04:30.23#ibcon#about to read 4, iclass 27, count 0 2006.162.08:04:30.23#ibcon#read 4, iclass 27, count 0 2006.162.08:04:30.23#ibcon#about to read 5, iclass 27, count 0 2006.162.08:04:30.23#ibcon#read 5, iclass 27, count 0 2006.162.08:04:30.23#ibcon#about to read 6, iclass 27, count 0 2006.162.08:04:30.23#ibcon#read 6, iclass 27, count 0 2006.162.08:04:30.23#ibcon#end of sib2, iclass 27, count 0 2006.162.08:04:30.23#ibcon#*after write, iclass 27, count 0 2006.162.08:04:30.23#ibcon#*before return 0, iclass 27, count 0 2006.162.08:04:30.23#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:04:30.23#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:04:30.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.162.08:04:30.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.162.08:04:30.23$vc4f8/valo=5,652.99 2006.162.08:04:30.23#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.162.08:04:30.23#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.162.08:04:30.23#ibcon#ireg 17 cls_cnt 0 2006.162.08:04:30.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:04:30.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:04:30.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:04:30.23#ibcon#enter wrdev, iclass 29, count 0 2006.162.08:04:30.23#ibcon#first serial, iclass 29, count 0 2006.162.08:04:30.23#ibcon#enter sib2, iclass 29, count 0 2006.162.08:04:30.23#ibcon#flushed, iclass 29, count 0 2006.162.08:04:30.23#ibcon#about to write, iclass 29, count 0 2006.162.08:04:30.23#ibcon#wrote, iclass 29, count 0 2006.162.08:04:30.23#ibcon#about to read 3, iclass 29, count 0 2006.162.08:04:30.25#ibcon#read 3, iclass 29, count 0 2006.162.08:04:30.25#ibcon#about to read 4, iclass 29, count 0 2006.162.08:04:30.25#ibcon#read 4, iclass 29, count 0 2006.162.08:04:30.25#ibcon#about to read 5, iclass 29, count 0 2006.162.08:04:30.25#ibcon#read 5, iclass 29, count 0 2006.162.08:04:30.25#ibcon#about to read 6, iclass 29, count 0 2006.162.08:04:30.25#ibcon#read 6, iclass 29, count 0 2006.162.08:04:30.25#ibcon#end of sib2, iclass 29, count 0 2006.162.08:04:30.25#ibcon#*mode == 0, iclass 29, count 0 2006.162.08:04:30.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.162.08:04:30.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.08:04:30.25#ibcon#*before write, iclass 29, count 0 2006.162.08:04:30.25#ibcon#enter sib2, iclass 29, count 0 2006.162.08:04:30.25#ibcon#flushed, iclass 29, count 0 2006.162.08:04:30.25#ibcon#about to write, iclass 29, count 0 2006.162.08:04:30.25#ibcon#wrote, iclass 29, count 0 2006.162.08:04:30.25#ibcon#about to read 3, iclass 29, count 0 2006.162.08:04:30.29#ibcon#read 3, iclass 29, count 0 2006.162.08:04:30.29#ibcon#about to read 4, iclass 29, count 0 2006.162.08:04:30.29#ibcon#read 4, iclass 29, count 0 2006.162.08:04:30.29#ibcon#about to read 5, iclass 29, count 0 2006.162.08:04:30.29#ibcon#read 5, iclass 29, count 0 2006.162.08:04:30.29#ibcon#about to read 6, iclass 29, count 0 2006.162.08:04:30.29#ibcon#read 6, iclass 29, count 0 2006.162.08:04:30.29#ibcon#end of sib2, iclass 29, count 0 2006.162.08:04:30.29#ibcon#*after write, iclass 29, count 0 2006.162.08:04:30.29#ibcon#*before return 0, iclass 29, count 0 2006.162.08:04:30.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:04:30.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:04:30.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.162.08:04:30.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.162.08:04:30.29$vc4f8/va=5,7 2006.162.08:04:30.29#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.162.08:04:30.29#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.162.08:04:30.29#ibcon#ireg 11 cls_cnt 2 2006.162.08:04:30.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:04:30.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:04:30.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:04:30.35#ibcon#enter wrdev, iclass 31, count 2 2006.162.08:04:30.35#ibcon#first serial, iclass 31, count 2 2006.162.08:04:30.35#ibcon#enter sib2, iclass 31, count 2 2006.162.08:04:30.35#ibcon#flushed, iclass 31, count 2 2006.162.08:04:30.35#ibcon#about to write, iclass 31, count 2 2006.162.08:04:30.35#ibcon#wrote, iclass 31, count 2 2006.162.08:04:30.35#ibcon#about to read 3, iclass 31, count 2 2006.162.08:04:30.37#ibcon#read 3, iclass 31, count 2 2006.162.08:04:30.37#ibcon#about to read 4, iclass 31, count 2 2006.162.08:04:30.37#ibcon#read 4, iclass 31, count 2 2006.162.08:04:30.37#ibcon#about to read 5, iclass 31, count 2 2006.162.08:04:30.37#ibcon#read 5, iclass 31, count 2 2006.162.08:04:30.37#ibcon#about to read 6, iclass 31, count 2 2006.162.08:04:30.37#ibcon#read 6, iclass 31, count 2 2006.162.08:04:30.37#ibcon#end of sib2, iclass 31, count 2 2006.162.08:04:30.37#ibcon#*mode == 0, iclass 31, count 2 2006.162.08:04:30.37#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.162.08:04:30.37#ibcon#[25=AT05-07\r\n] 2006.162.08:04:30.37#ibcon#*before write, iclass 31, count 2 2006.162.08:04:30.37#ibcon#enter sib2, iclass 31, count 2 2006.162.08:04:30.37#ibcon#flushed, iclass 31, count 2 2006.162.08:04:30.37#ibcon#about to write, iclass 31, count 2 2006.162.08:04:30.37#ibcon#wrote, iclass 31, count 2 2006.162.08:04:30.37#ibcon#about to read 3, iclass 31, count 2 2006.162.08:04:30.40#ibcon#read 3, iclass 31, count 2 2006.162.08:04:30.40#ibcon#about to read 4, iclass 31, count 2 2006.162.08:04:30.40#ibcon#read 4, iclass 31, count 2 2006.162.08:04:30.40#ibcon#about to read 5, iclass 31, count 2 2006.162.08:04:30.40#ibcon#read 5, iclass 31, count 2 2006.162.08:04:30.40#ibcon#about to read 6, iclass 31, count 2 2006.162.08:04:30.40#ibcon#read 6, iclass 31, count 2 2006.162.08:04:30.40#ibcon#end of sib2, iclass 31, count 2 2006.162.08:04:30.40#ibcon#*after write, iclass 31, count 2 2006.162.08:04:30.40#ibcon#*before return 0, iclass 31, count 2 2006.162.08:04:30.40#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:04:30.40#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:04:30.40#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.162.08:04:30.40#ibcon#ireg 7 cls_cnt 0 2006.162.08:04:30.40#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:04:30.52#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:04:30.52#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:04:30.52#ibcon#enter wrdev, iclass 31, count 0 2006.162.08:04:30.52#ibcon#first serial, iclass 31, count 0 2006.162.08:04:30.52#ibcon#enter sib2, iclass 31, count 0 2006.162.08:04:30.52#ibcon#flushed, iclass 31, count 0 2006.162.08:04:30.52#ibcon#about to write, iclass 31, count 0 2006.162.08:04:30.52#ibcon#wrote, iclass 31, count 0 2006.162.08:04:30.52#ibcon#about to read 3, iclass 31, count 0 2006.162.08:04:30.54#ibcon#read 3, iclass 31, count 0 2006.162.08:04:30.54#ibcon#about to read 4, iclass 31, count 0 2006.162.08:04:30.54#ibcon#read 4, iclass 31, count 0 2006.162.08:04:30.54#ibcon#about to read 5, iclass 31, count 0 2006.162.08:04:30.54#ibcon#read 5, iclass 31, count 0 2006.162.08:04:30.54#ibcon#about to read 6, iclass 31, count 0 2006.162.08:04:30.54#ibcon#read 6, iclass 31, count 0 2006.162.08:04:30.54#ibcon#end of sib2, iclass 31, count 0 2006.162.08:04:30.54#ibcon#*mode == 0, iclass 31, count 0 2006.162.08:04:30.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.162.08:04:30.54#ibcon#[25=USB\r\n] 2006.162.08:04:30.54#ibcon#*before write, iclass 31, count 0 2006.162.08:04:30.54#ibcon#enter sib2, iclass 31, count 0 2006.162.08:04:30.54#ibcon#flushed, iclass 31, count 0 2006.162.08:04:30.54#ibcon#about to write, iclass 31, count 0 2006.162.08:04:30.54#ibcon#wrote, iclass 31, count 0 2006.162.08:04:30.54#ibcon#about to read 3, iclass 31, count 0 2006.162.08:04:30.57#ibcon#read 3, iclass 31, count 0 2006.162.08:04:30.57#ibcon#about to read 4, iclass 31, count 0 2006.162.08:04:30.57#ibcon#read 4, iclass 31, count 0 2006.162.08:04:30.57#ibcon#about to read 5, iclass 31, count 0 2006.162.08:04:30.57#ibcon#read 5, iclass 31, count 0 2006.162.08:04:30.57#ibcon#about to read 6, iclass 31, count 0 2006.162.08:04:30.57#ibcon#read 6, iclass 31, count 0 2006.162.08:04:30.57#ibcon#end of sib2, iclass 31, count 0 2006.162.08:04:30.57#ibcon#*after write, iclass 31, count 0 2006.162.08:04:30.57#ibcon#*before return 0, iclass 31, count 0 2006.162.08:04:30.57#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:04:30.57#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:04:30.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.162.08:04:30.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.162.08:04:30.57$vc4f8/valo=6,772.99 2006.162.08:04:30.57#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.162.08:04:30.57#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.162.08:04:30.57#ibcon#ireg 17 cls_cnt 0 2006.162.08:04:30.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:04:30.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:04:30.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:04:30.57#ibcon#enter wrdev, iclass 33, count 0 2006.162.08:04:30.57#ibcon#first serial, iclass 33, count 0 2006.162.08:04:30.57#ibcon#enter sib2, iclass 33, count 0 2006.162.08:04:30.57#ibcon#flushed, iclass 33, count 0 2006.162.08:04:30.57#ibcon#about to write, iclass 33, count 0 2006.162.08:04:30.57#ibcon#wrote, iclass 33, count 0 2006.162.08:04:30.57#ibcon#about to read 3, iclass 33, count 0 2006.162.08:04:30.59#ibcon#read 3, iclass 33, count 0 2006.162.08:04:30.59#ibcon#about to read 4, iclass 33, count 0 2006.162.08:04:30.59#ibcon#read 4, iclass 33, count 0 2006.162.08:04:30.59#ibcon#about to read 5, iclass 33, count 0 2006.162.08:04:30.59#ibcon#read 5, iclass 33, count 0 2006.162.08:04:30.59#ibcon#about to read 6, iclass 33, count 0 2006.162.08:04:30.59#ibcon#read 6, iclass 33, count 0 2006.162.08:04:30.59#ibcon#end of sib2, iclass 33, count 0 2006.162.08:04:30.59#ibcon#*mode == 0, iclass 33, count 0 2006.162.08:04:30.59#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.162.08:04:30.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.08:04:30.59#ibcon#*before write, iclass 33, count 0 2006.162.08:04:30.59#ibcon#enter sib2, iclass 33, count 0 2006.162.08:04:30.59#ibcon#flushed, iclass 33, count 0 2006.162.08:04:30.59#ibcon#about to write, iclass 33, count 0 2006.162.08:04:30.59#ibcon#wrote, iclass 33, count 0 2006.162.08:04:30.59#ibcon#about to read 3, iclass 33, count 0 2006.162.08:04:30.63#ibcon#read 3, iclass 33, count 0 2006.162.08:04:30.63#ibcon#about to read 4, iclass 33, count 0 2006.162.08:04:30.63#ibcon#read 4, iclass 33, count 0 2006.162.08:04:30.63#ibcon#about to read 5, iclass 33, count 0 2006.162.08:04:30.63#ibcon#read 5, iclass 33, count 0 2006.162.08:04:30.63#ibcon#about to read 6, iclass 33, count 0 2006.162.08:04:30.63#ibcon#read 6, iclass 33, count 0 2006.162.08:04:30.63#ibcon#end of sib2, iclass 33, count 0 2006.162.08:04:30.63#ibcon#*after write, iclass 33, count 0 2006.162.08:04:30.63#ibcon#*before return 0, iclass 33, count 0 2006.162.08:04:30.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:04:30.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:04:30.63#ibcon#about to clear, iclass 33 cls_cnt 0 2006.162.08:04:30.63#ibcon#cleared, iclass 33 cls_cnt 0 2006.162.08:04:30.63$vc4f8/va=6,6 2006.162.08:04:30.63#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.162.08:04:30.63#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.162.08:04:30.63#ibcon#ireg 11 cls_cnt 2 2006.162.08:04:30.63#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.162.08:04:30.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.162.08:04:30.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.162.08:04:30.69#ibcon#enter wrdev, iclass 35, count 2 2006.162.08:04:30.69#ibcon#first serial, iclass 35, count 2 2006.162.08:04:30.69#ibcon#enter sib2, iclass 35, count 2 2006.162.08:04:30.69#ibcon#flushed, iclass 35, count 2 2006.162.08:04:30.69#ibcon#about to write, iclass 35, count 2 2006.162.08:04:30.69#ibcon#wrote, iclass 35, count 2 2006.162.08:04:30.69#ibcon#about to read 3, iclass 35, count 2 2006.162.08:04:30.71#ibcon#read 3, iclass 35, count 2 2006.162.08:04:30.71#ibcon#about to read 4, iclass 35, count 2 2006.162.08:04:30.71#ibcon#read 4, iclass 35, count 2 2006.162.08:04:30.71#ibcon#about to read 5, iclass 35, count 2 2006.162.08:04:30.71#ibcon#read 5, iclass 35, count 2 2006.162.08:04:30.71#ibcon#about to read 6, iclass 35, count 2 2006.162.08:04:30.71#ibcon#read 6, iclass 35, count 2 2006.162.08:04:30.71#ibcon#end of sib2, iclass 35, count 2 2006.162.08:04:30.71#ibcon#*mode == 0, iclass 35, count 2 2006.162.08:04:30.71#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.162.08:04:30.71#ibcon#[25=AT06-06\r\n] 2006.162.08:04:30.71#ibcon#*before write, iclass 35, count 2 2006.162.08:04:30.71#ibcon#enter sib2, iclass 35, count 2 2006.162.08:04:30.71#ibcon#flushed, iclass 35, count 2 2006.162.08:04:30.71#ibcon#about to write, iclass 35, count 2 2006.162.08:04:30.71#ibcon#wrote, iclass 35, count 2 2006.162.08:04:30.71#ibcon#about to read 3, iclass 35, count 2 2006.162.08:04:30.74#ibcon#read 3, iclass 35, count 2 2006.162.08:04:30.74#ibcon#about to read 4, iclass 35, count 2 2006.162.08:04:30.74#ibcon#read 4, iclass 35, count 2 2006.162.08:04:30.74#ibcon#about to read 5, iclass 35, count 2 2006.162.08:04:30.74#ibcon#read 5, iclass 35, count 2 2006.162.08:04:30.74#ibcon#about to read 6, iclass 35, count 2 2006.162.08:04:30.74#ibcon#read 6, iclass 35, count 2 2006.162.08:04:30.74#ibcon#end of sib2, iclass 35, count 2 2006.162.08:04:30.74#ibcon#*after write, iclass 35, count 2 2006.162.08:04:30.74#ibcon#*before return 0, iclass 35, count 2 2006.162.08:04:30.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.162.08:04:30.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.162.08:04:30.74#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.162.08:04:30.74#ibcon#ireg 7 cls_cnt 0 2006.162.08:04:30.74#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.162.08:04:30.86#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.162.08:04:30.86#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.162.08:04:30.86#ibcon#enter wrdev, iclass 35, count 0 2006.162.08:04:30.86#ibcon#first serial, iclass 35, count 0 2006.162.08:04:30.86#ibcon#enter sib2, iclass 35, count 0 2006.162.08:04:30.86#ibcon#flushed, iclass 35, count 0 2006.162.08:04:30.86#ibcon#about to write, iclass 35, count 0 2006.162.08:04:30.86#ibcon#wrote, iclass 35, count 0 2006.162.08:04:30.86#ibcon#about to read 3, iclass 35, count 0 2006.162.08:04:30.88#ibcon#read 3, iclass 35, count 0 2006.162.08:04:30.88#ibcon#about to read 4, iclass 35, count 0 2006.162.08:04:30.88#ibcon#read 4, iclass 35, count 0 2006.162.08:04:30.88#ibcon#about to read 5, iclass 35, count 0 2006.162.08:04:30.88#ibcon#read 5, iclass 35, count 0 2006.162.08:04:30.88#ibcon#about to read 6, iclass 35, count 0 2006.162.08:04:30.88#ibcon#read 6, iclass 35, count 0 2006.162.08:04:30.88#ibcon#end of sib2, iclass 35, count 0 2006.162.08:04:30.88#ibcon#*mode == 0, iclass 35, count 0 2006.162.08:04:30.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.162.08:04:30.88#ibcon#[25=USB\r\n] 2006.162.08:04:30.88#ibcon#*before write, iclass 35, count 0 2006.162.08:04:30.88#ibcon#enter sib2, iclass 35, count 0 2006.162.08:04:30.88#ibcon#flushed, iclass 35, count 0 2006.162.08:04:30.88#ibcon#about to write, iclass 35, count 0 2006.162.08:04:30.88#ibcon#wrote, iclass 35, count 0 2006.162.08:04:30.88#ibcon#about to read 3, iclass 35, count 0 2006.162.08:04:30.91#ibcon#read 3, iclass 35, count 0 2006.162.08:04:30.91#ibcon#about to read 4, iclass 35, count 0 2006.162.08:04:30.91#ibcon#read 4, iclass 35, count 0 2006.162.08:04:30.91#ibcon#about to read 5, iclass 35, count 0 2006.162.08:04:30.91#ibcon#read 5, iclass 35, count 0 2006.162.08:04:30.91#ibcon#about to read 6, iclass 35, count 0 2006.162.08:04:30.91#ibcon#read 6, iclass 35, count 0 2006.162.08:04:30.91#ibcon#end of sib2, iclass 35, count 0 2006.162.08:04:30.91#ibcon#*after write, iclass 35, count 0 2006.162.08:04:30.91#ibcon#*before return 0, iclass 35, count 0 2006.162.08:04:30.91#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.162.08:04:30.91#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.162.08:04:30.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.162.08:04:30.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.162.08:04:30.91$vc4f8/valo=7,832.99 2006.162.08:04:30.91#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.162.08:04:30.91#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.162.08:04:30.91#ibcon#ireg 17 cls_cnt 0 2006.162.08:04:30.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.162.08:04:30.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.162.08:04:30.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.162.08:04:30.91#ibcon#enter wrdev, iclass 37, count 0 2006.162.08:04:30.91#ibcon#first serial, iclass 37, count 0 2006.162.08:04:30.91#ibcon#enter sib2, iclass 37, count 0 2006.162.08:04:30.91#ibcon#flushed, iclass 37, count 0 2006.162.08:04:30.91#ibcon#about to write, iclass 37, count 0 2006.162.08:04:30.91#ibcon#wrote, iclass 37, count 0 2006.162.08:04:30.91#ibcon#about to read 3, iclass 37, count 0 2006.162.08:04:30.93#ibcon#read 3, iclass 37, count 0 2006.162.08:04:30.93#ibcon#about to read 4, iclass 37, count 0 2006.162.08:04:30.93#ibcon#read 4, iclass 37, count 0 2006.162.08:04:30.93#ibcon#about to read 5, iclass 37, count 0 2006.162.08:04:30.93#ibcon#read 5, iclass 37, count 0 2006.162.08:04:30.93#ibcon#about to read 6, iclass 37, count 0 2006.162.08:04:30.93#ibcon#read 6, iclass 37, count 0 2006.162.08:04:30.93#ibcon#end of sib2, iclass 37, count 0 2006.162.08:04:30.93#ibcon#*mode == 0, iclass 37, count 0 2006.162.08:04:30.93#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.162.08:04:30.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.08:04:30.93#ibcon#*before write, iclass 37, count 0 2006.162.08:04:30.93#ibcon#enter sib2, iclass 37, count 0 2006.162.08:04:30.93#ibcon#flushed, iclass 37, count 0 2006.162.08:04:30.93#ibcon#about to write, iclass 37, count 0 2006.162.08:04:30.93#ibcon#wrote, iclass 37, count 0 2006.162.08:04:30.93#ibcon#about to read 3, iclass 37, count 0 2006.162.08:04:30.97#ibcon#read 3, iclass 37, count 0 2006.162.08:04:30.97#ibcon#about to read 4, iclass 37, count 0 2006.162.08:04:30.97#ibcon#read 4, iclass 37, count 0 2006.162.08:04:30.97#ibcon#about to read 5, iclass 37, count 0 2006.162.08:04:30.97#ibcon#read 5, iclass 37, count 0 2006.162.08:04:30.97#ibcon#about to read 6, iclass 37, count 0 2006.162.08:04:30.97#ibcon#read 6, iclass 37, count 0 2006.162.08:04:30.97#ibcon#end of sib2, iclass 37, count 0 2006.162.08:04:30.97#ibcon#*after write, iclass 37, count 0 2006.162.08:04:30.97#ibcon#*before return 0, iclass 37, count 0 2006.162.08:04:30.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.162.08:04:30.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.162.08:04:30.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.162.08:04:30.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.162.08:04:30.97$vc4f8/va=7,6 2006.162.08:04:30.97#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.162.08:04:30.97#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.162.08:04:30.97#ibcon#ireg 11 cls_cnt 2 2006.162.08:04:30.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.162.08:04:31.03#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.162.08:04:31.03#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.162.08:04:31.03#ibcon#enter wrdev, iclass 39, count 2 2006.162.08:04:31.03#ibcon#first serial, iclass 39, count 2 2006.162.08:04:31.03#ibcon#enter sib2, iclass 39, count 2 2006.162.08:04:31.03#ibcon#flushed, iclass 39, count 2 2006.162.08:04:31.03#ibcon#about to write, iclass 39, count 2 2006.162.08:04:31.03#ibcon#wrote, iclass 39, count 2 2006.162.08:04:31.03#ibcon#about to read 3, iclass 39, count 2 2006.162.08:04:31.05#ibcon#read 3, iclass 39, count 2 2006.162.08:04:31.05#ibcon#about to read 4, iclass 39, count 2 2006.162.08:04:31.05#ibcon#read 4, iclass 39, count 2 2006.162.08:04:31.05#ibcon#about to read 5, iclass 39, count 2 2006.162.08:04:31.05#ibcon#read 5, iclass 39, count 2 2006.162.08:04:31.05#ibcon#about to read 6, iclass 39, count 2 2006.162.08:04:31.05#ibcon#read 6, iclass 39, count 2 2006.162.08:04:31.05#ibcon#end of sib2, iclass 39, count 2 2006.162.08:04:31.05#ibcon#*mode == 0, iclass 39, count 2 2006.162.08:04:31.05#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.162.08:04:31.05#ibcon#[25=AT07-06\r\n] 2006.162.08:04:31.05#ibcon#*before write, iclass 39, count 2 2006.162.08:04:31.05#ibcon#enter sib2, iclass 39, count 2 2006.162.08:04:31.05#ibcon#flushed, iclass 39, count 2 2006.162.08:04:31.05#ibcon#about to write, iclass 39, count 2 2006.162.08:04:31.05#ibcon#wrote, iclass 39, count 2 2006.162.08:04:31.05#ibcon#about to read 3, iclass 39, count 2 2006.162.08:04:31.08#ibcon#read 3, iclass 39, count 2 2006.162.08:04:31.08#ibcon#about to read 4, iclass 39, count 2 2006.162.08:04:31.08#ibcon#read 4, iclass 39, count 2 2006.162.08:04:31.08#ibcon#about to read 5, iclass 39, count 2 2006.162.08:04:31.08#ibcon#read 5, iclass 39, count 2 2006.162.08:04:31.08#ibcon#about to read 6, iclass 39, count 2 2006.162.08:04:31.08#ibcon#read 6, iclass 39, count 2 2006.162.08:04:31.08#ibcon#end of sib2, iclass 39, count 2 2006.162.08:04:31.08#ibcon#*after write, iclass 39, count 2 2006.162.08:04:31.08#ibcon#*before return 0, iclass 39, count 2 2006.162.08:04:31.08#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.162.08:04:31.08#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.162.08:04:31.08#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.162.08:04:31.08#ibcon#ireg 7 cls_cnt 0 2006.162.08:04:31.08#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.162.08:04:31.20#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.162.08:04:31.20#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.162.08:04:31.20#ibcon#enter wrdev, iclass 39, count 0 2006.162.08:04:31.20#ibcon#first serial, iclass 39, count 0 2006.162.08:04:31.20#ibcon#enter sib2, iclass 39, count 0 2006.162.08:04:31.20#ibcon#flushed, iclass 39, count 0 2006.162.08:04:31.20#ibcon#about to write, iclass 39, count 0 2006.162.08:04:31.20#ibcon#wrote, iclass 39, count 0 2006.162.08:04:31.20#ibcon#about to read 3, iclass 39, count 0 2006.162.08:04:31.22#ibcon#read 3, iclass 39, count 0 2006.162.08:04:31.22#ibcon#about to read 4, iclass 39, count 0 2006.162.08:04:31.22#ibcon#read 4, iclass 39, count 0 2006.162.08:04:31.22#ibcon#about to read 5, iclass 39, count 0 2006.162.08:04:31.22#ibcon#read 5, iclass 39, count 0 2006.162.08:04:31.22#ibcon#about to read 6, iclass 39, count 0 2006.162.08:04:31.22#ibcon#read 6, iclass 39, count 0 2006.162.08:04:31.22#ibcon#end of sib2, iclass 39, count 0 2006.162.08:04:31.22#ibcon#*mode == 0, iclass 39, count 0 2006.162.08:04:31.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.162.08:04:31.22#ibcon#[25=USB\r\n] 2006.162.08:04:31.22#ibcon#*before write, iclass 39, count 0 2006.162.08:04:31.22#ibcon#enter sib2, iclass 39, count 0 2006.162.08:04:31.22#ibcon#flushed, iclass 39, count 0 2006.162.08:04:31.22#ibcon#about to write, iclass 39, count 0 2006.162.08:04:31.22#ibcon#wrote, iclass 39, count 0 2006.162.08:04:31.22#ibcon#about to read 3, iclass 39, count 0 2006.162.08:04:31.25#ibcon#read 3, iclass 39, count 0 2006.162.08:04:31.25#ibcon#about to read 4, iclass 39, count 0 2006.162.08:04:31.25#ibcon#read 4, iclass 39, count 0 2006.162.08:04:31.25#ibcon#about to read 5, iclass 39, count 0 2006.162.08:04:31.25#ibcon#read 5, iclass 39, count 0 2006.162.08:04:31.25#ibcon#about to read 6, iclass 39, count 0 2006.162.08:04:31.25#ibcon#read 6, iclass 39, count 0 2006.162.08:04:31.25#ibcon#end of sib2, iclass 39, count 0 2006.162.08:04:31.25#ibcon#*after write, iclass 39, count 0 2006.162.08:04:31.25#ibcon#*before return 0, iclass 39, count 0 2006.162.08:04:31.25#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.162.08:04:31.25#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.162.08:04:31.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.162.08:04:31.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.162.08:04:31.25$vc4f8/valo=8,852.99 2006.162.08:04:31.25#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.162.08:04:31.25#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.162.08:04:31.25#ibcon#ireg 17 cls_cnt 0 2006.162.08:04:31.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.162.08:04:31.25#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.162.08:04:31.25#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.162.08:04:31.25#ibcon#enter wrdev, iclass 3, count 0 2006.162.08:04:31.25#ibcon#first serial, iclass 3, count 0 2006.162.08:04:31.25#ibcon#enter sib2, iclass 3, count 0 2006.162.08:04:31.25#ibcon#flushed, iclass 3, count 0 2006.162.08:04:31.25#ibcon#about to write, iclass 3, count 0 2006.162.08:04:31.25#ibcon#wrote, iclass 3, count 0 2006.162.08:04:31.25#ibcon#about to read 3, iclass 3, count 0 2006.162.08:04:31.27#ibcon#read 3, iclass 3, count 0 2006.162.08:04:31.27#ibcon#about to read 4, iclass 3, count 0 2006.162.08:04:31.27#ibcon#read 4, iclass 3, count 0 2006.162.08:04:31.27#ibcon#about to read 5, iclass 3, count 0 2006.162.08:04:31.27#ibcon#read 5, iclass 3, count 0 2006.162.08:04:31.27#ibcon#about to read 6, iclass 3, count 0 2006.162.08:04:31.27#ibcon#read 6, iclass 3, count 0 2006.162.08:04:31.27#ibcon#end of sib2, iclass 3, count 0 2006.162.08:04:31.27#ibcon#*mode == 0, iclass 3, count 0 2006.162.08:04:31.27#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.162.08:04:31.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.08:04:31.27#ibcon#*before write, iclass 3, count 0 2006.162.08:04:31.27#ibcon#enter sib2, iclass 3, count 0 2006.162.08:04:31.27#ibcon#flushed, iclass 3, count 0 2006.162.08:04:31.27#ibcon#about to write, iclass 3, count 0 2006.162.08:04:31.27#ibcon#wrote, iclass 3, count 0 2006.162.08:04:31.27#ibcon#about to read 3, iclass 3, count 0 2006.162.08:04:31.31#ibcon#read 3, iclass 3, count 0 2006.162.08:04:31.31#ibcon#about to read 4, iclass 3, count 0 2006.162.08:04:31.31#ibcon#read 4, iclass 3, count 0 2006.162.08:04:31.31#ibcon#about to read 5, iclass 3, count 0 2006.162.08:04:31.31#ibcon#read 5, iclass 3, count 0 2006.162.08:04:31.31#ibcon#about to read 6, iclass 3, count 0 2006.162.08:04:31.31#ibcon#read 6, iclass 3, count 0 2006.162.08:04:31.31#ibcon#end of sib2, iclass 3, count 0 2006.162.08:04:31.31#ibcon#*after write, iclass 3, count 0 2006.162.08:04:31.31#ibcon#*before return 0, iclass 3, count 0 2006.162.08:04:31.31#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.162.08:04:31.31#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.162.08:04:31.31#ibcon#about to clear, iclass 3 cls_cnt 0 2006.162.08:04:31.31#ibcon#cleared, iclass 3 cls_cnt 0 2006.162.08:04:31.31$vc4f8/va=8,7 2006.162.08:04:31.31#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.162.08:04:31.31#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.162.08:04:31.31#ibcon#ireg 11 cls_cnt 2 2006.162.08:04:31.31#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.162.08:04:31.37#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.162.08:04:31.37#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.162.08:04:31.37#ibcon#enter wrdev, iclass 5, count 2 2006.162.08:04:31.37#ibcon#first serial, iclass 5, count 2 2006.162.08:04:31.37#ibcon#enter sib2, iclass 5, count 2 2006.162.08:04:31.37#ibcon#flushed, iclass 5, count 2 2006.162.08:04:31.37#ibcon#about to write, iclass 5, count 2 2006.162.08:04:31.37#ibcon#wrote, iclass 5, count 2 2006.162.08:04:31.37#ibcon#about to read 3, iclass 5, count 2 2006.162.08:04:31.39#ibcon#read 3, iclass 5, count 2 2006.162.08:04:31.39#ibcon#about to read 4, iclass 5, count 2 2006.162.08:04:31.39#ibcon#read 4, iclass 5, count 2 2006.162.08:04:31.39#ibcon#about to read 5, iclass 5, count 2 2006.162.08:04:31.39#ibcon#read 5, iclass 5, count 2 2006.162.08:04:31.39#ibcon#about to read 6, iclass 5, count 2 2006.162.08:04:31.39#ibcon#read 6, iclass 5, count 2 2006.162.08:04:31.39#ibcon#end of sib2, iclass 5, count 2 2006.162.08:04:31.39#ibcon#*mode == 0, iclass 5, count 2 2006.162.08:04:31.39#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.162.08:04:31.39#ibcon#[25=AT08-07\r\n] 2006.162.08:04:31.39#ibcon#*before write, iclass 5, count 2 2006.162.08:04:31.39#ibcon#enter sib2, iclass 5, count 2 2006.162.08:04:31.39#ibcon#flushed, iclass 5, count 2 2006.162.08:04:31.39#ibcon#about to write, iclass 5, count 2 2006.162.08:04:31.39#ibcon#wrote, iclass 5, count 2 2006.162.08:04:31.39#ibcon#about to read 3, iclass 5, count 2 2006.162.08:04:31.42#ibcon#read 3, iclass 5, count 2 2006.162.08:04:31.42#ibcon#about to read 4, iclass 5, count 2 2006.162.08:04:31.42#ibcon#read 4, iclass 5, count 2 2006.162.08:04:31.42#ibcon#about to read 5, iclass 5, count 2 2006.162.08:04:31.42#ibcon#read 5, iclass 5, count 2 2006.162.08:04:31.42#ibcon#about to read 6, iclass 5, count 2 2006.162.08:04:31.42#ibcon#read 6, iclass 5, count 2 2006.162.08:04:31.42#ibcon#end of sib2, iclass 5, count 2 2006.162.08:04:31.42#ibcon#*after write, iclass 5, count 2 2006.162.08:04:31.42#ibcon#*before return 0, iclass 5, count 2 2006.162.08:04:31.42#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.162.08:04:31.42#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.162.08:04:31.42#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.162.08:04:31.42#ibcon#ireg 7 cls_cnt 0 2006.162.08:04:31.42#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.162.08:04:31.54#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.162.08:04:31.54#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.162.08:04:31.54#ibcon#enter wrdev, iclass 5, count 0 2006.162.08:04:31.54#ibcon#first serial, iclass 5, count 0 2006.162.08:04:31.54#ibcon#enter sib2, iclass 5, count 0 2006.162.08:04:31.54#ibcon#flushed, iclass 5, count 0 2006.162.08:04:31.54#ibcon#about to write, iclass 5, count 0 2006.162.08:04:31.54#ibcon#wrote, iclass 5, count 0 2006.162.08:04:31.54#ibcon#about to read 3, iclass 5, count 0 2006.162.08:04:31.56#ibcon#read 3, iclass 5, count 0 2006.162.08:04:31.56#ibcon#about to read 4, iclass 5, count 0 2006.162.08:04:31.56#ibcon#read 4, iclass 5, count 0 2006.162.08:04:31.56#ibcon#about to read 5, iclass 5, count 0 2006.162.08:04:31.56#ibcon#read 5, iclass 5, count 0 2006.162.08:04:31.56#ibcon#about to read 6, iclass 5, count 0 2006.162.08:04:31.56#ibcon#read 6, iclass 5, count 0 2006.162.08:04:31.56#ibcon#end of sib2, iclass 5, count 0 2006.162.08:04:31.56#ibcon#*mode == 0, iclass 5, count 0 2006.162.08:04:31.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.162.08:04:31.56#ibcon#[25=USB\r\n] 2006.162.08:04:31.56#ibcon#*before write, iclass 5, count 0 2006.162.08:04:31.56#ibcon#enter sib2, iclass 5, count 0 2006.162.08:04:31.56#ibcon#flushed, iclass 5, count 0 2006.162.08:04:31.56#ibcon#about to write, iclass 5, count 0 2006.162.08:04:31.56#ibcon#wrote, iclass 5, count 0 2006.162.08:04:31.56#ibcon#about to read 3, iclass 5, count 0 2006.162.08:04:31.59#ibcon#read 3, iclass 5, count 0 2006.162.08:04:31.59#ibcon#about to read 4, iclass 5, count 0 2006.162.08:04:31.59#ibcon#read 4, iclass 5, count 0 2006.162.08:04:31.59#ibcon#about to read 5, iclass 5, count 0 2006.162.08:04:31.59#ibcon#read 5, iclass 5, count 0 2006.162.08:04:31.59#ibcon#about to read 6, iclass 5, count 0 2006.162.08:04:31.59#ibcon#read 6, iclass 5, count 0 2006.162.08:04:31.59#ibcon#end of sib2, iclass 5, count 0 2006.162.08:04:31.59#ibcon#*after write, iclass 5, count 0 2006.162.08:04:31.59#ibcon#*before return 0, iclass 5, count 0 2006.162.08:04:31.59#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.162.08:04:31.59#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.162.08:04:31.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.162.08:04:31.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.162.08:04:31.59$vc4f8/vblo=1,632.99 2006.162.08:04:31.59#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.162.08:04:31.59#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.162.08:04:31.59#ibcon#ireg 17 cls_cnt 0 2006.162.08:04:31.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.162.08:04:31.59#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.162.08:04:31.59#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.162.08:04:31.59#ibcon#enter wrdev, iclass 7, count 0 2006.162.08:04:31.59#ibcon#first serial, iclass 7, count 0 2006.162.08:04:31.59#ibcon#enter sib2, iclass 7, count 0 2006.162.08:04:31.59#ibcon#flushed, iclass 7, count 0 2006.162.08:04:31.59#ibcon#about to write, iclass 7, count 0 2006.162.08:04:31.59#ibcon#wrote, iclass 7, count 0 2006.162.08:04:31.59#ibcon#about to read 3, iclass 7, count 0 2006.162.08:04:31.61#ibcon#read 3, iclass 7, count 0 2006.162.08:04:31.61#ibcon#about to read 4, iclass 7, count 0 2006.162.08:04:31.61#ibcon#read 4, iclass 7, count 0 2006.162.08:04:31.61#ibcon#about to read 5, iclass 7, count 0 2006.162.08:04:31.61#ibcon#read 5, iclass 7, count 0 2006.162.08:04:31.61#ibcon#about to read 6, iclass 7, count 0 2006.162.08:04:31.61#ibcon#read 6, iclass 7, count 0 2006.162.08:04:31.61#ibcon#end of sib2, iclass 7, count 0 2006.162.08:04:31.61#ibcon#*mode == 0, iclass 7, count 0 2006.162.08:04:31.61#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.162.08:04:31.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.08:04:31.61#ibcon#*before write, iclass 7, count 0 2006.162.08:04:31.61#ibcon#enter sib2, iclass 7, count 0 2006.162.08:04:31.61#ibcon#flushed, iclass 7, count 0 2006.162.08:04:31.61#ibcon#about to write, iclass 7, count 0 2006.162.08:04:31.61#ibcon#wrote, iclass 7, count 0 2006.162.08:04:31.61#ibcon#about to read 3, iclass 7, count 0 2006.162.08:04:31.65#ibcon#read 3, iclass 7, count 0 2006.162.08:04:31.65#ibcon#about to read 4, iclass 7, count 0 2006.162.08:04:31.65#ibcon#read 4, iclass 7, count 0 2006.162.08:04:31.65#ibcon#about to read 5, iclass 7, count 0 2006.162.08:04:31.65#ibcon#read 5, iclass 7, count 0 2006.162.08:04:31.65#ibcon#about to read 6, iclass 7, count 0 2006.162.08:04:31.65#ibcon#read 6, iclass 7, count 0 2006.162.08:04:31.65#ibcon#end of sib2, iclass 7, count 0 2006.162.08:04:31.65#ibcon#*after write, iclass 7, count 0 2006.162.08:04:31.65#ibcon#*before return 0, iclass 7, count 0 2006.162.08:04:31.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.162.08:04:31.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.162.08:04:31.65#ibcon#about to clear, iclass 7 cls_cnt 0 2006.162.08:04:31.65#ibcon#cleared, iclass 7 cls_cnt 0 2006.162.08:04:31.65$vc4f8/vb=1,4 2006.162.08:04:31.65#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.162.08:04:31.65#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.162.08:04:31.65#ibcon#ireg 11 cls_cnt 2 2006.162.08:04:31.65#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.162.08:04:31.65#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.162.08:04:31.65#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.162.08:04:31.65#ibcon#enter wrdev, iclass 11, count 2 2006.162.08:04:31.65#ibcon#first serial, iclass 11, count 2 2006.162.08:04:31.65#ibcon#enter sib2, iclass 11, count 2 2006.162.08:04:31.65#ibcon#flushed, iclass 11, count 2 2006.162.08:04:31.65#ibcon#about to write, iclass 11, count 2 2006.162.08:04:31.65#ibcon#wrote, iclass 11, count 2 2006.162.08:04:31.65#ibcon#about to read 3, iclass 11, count 2 2006.162.08:04:31.67#ibcon#read 3, iclass 11, count 2 2006.162.08:04:31.67#ibcon#about to read 4, iclass 11, count 2 2006.162.08:04:31.67#ibcon#read 4, iclass 11, count 2 2006.162.08:04:31.67#ibcon#about to read 5, iclass 11, count 2 2006.162.08:04:31.67#ibcon#read 5, iclass 11, count 2 2006.162.08:04:31.67#ibcon#about to read 6, iclass 11, count 2 2006.162.08:04:31.67#ibcon#read 6, iclass 11, count 2 2006.162.08:04:31.67#ibcon#end of sib2, iclass 11, count 2 2006.162.08:04:31.67#ibcon#*mode == 0, iclass 11, count 2 2006.162.08:04:31.67#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.162.08:04:31.67#ibcon#[27=AT01-04\r\n] 2006.162.08:04:31.67#ibcon#*before write, iclass 11, count 2 2006.162.08:04:31.67#ibcon#enter sib2, iclass 11, count 2 2006.162.08:04:31.67#ibcon#flushed, iclass 11, count 2 2006.162.08:04:31.67#ibcon#about to write, iclass 11, count 2 2006.162.08:04:31.67#ibcon#wrote, iclass 11, count 2 2006.162.08:04:31.67#ibcon#about to read 3, iclass 11, count 2 2006.162.08:04:31.70#ibcon#read 3, iclass 11, count 2 2006.162.08:04:31.70#ibcon#about to read 4, iclass 11, count 2 2006.162.08:04:31.70#ibcon#read 4, iclass 11, count 2 2006.162.08:04:31.70#ibcon#about to read 5, iclass 11, count 2 2006.162.08:04:31.70#ibcon#read 5, iclass 11, count 2 2006.162.08:04:31.70#ibcon#about to read 6, iclass 11, count 2 2006.162.08:04:31.70#ibcon#read 6, iclass 11, count 2 2006.162.08:04:31.70#ibcon#end of sib2, iclass 11, count 2 2006.162.08:04:31.70#ibcon#*after write, iclass 11, count 2 2006.162.08:04:31.70#ibcon#*before return 0, iclass 11, count 2 2006.162.08:04:31.70#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.162.08:04:31.70#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.162.08:04:31.70#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.162.08:04:31.70#ibcon#ireg 7 cls_cnt 0 2006.162.08:04:31.70#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.162.08:04:31.82#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.162.08:04:31.82#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.162.08:04:31.82#ibcon#enter wrdev, iclass 11, count 0 2006.162.08:04:31.82#ibcon#first serial, iclass 11, count 0 2006.162.08:04:31.82#ibcon#enter sib2, iclass 11, count 0 2006.162.08:04:31.82#ibcon#flushed, iclass 11, count 0 2006.162.08:04:31.82#ibcon#about to write, iclass 11, count 0 2006.162.08:04:31.82#ibcon#wrote, iclass 11, count 0 2006.162.08:04:31.82#ibcon#about to read 3, iclass 11, count 0 2006.162.08:04:31.84#ibcon#read 3, iclass 11, count 0 2006.162.08:04:31.84#ibcon#about to read 4, iclass 11, count 0 2006.162.08:04:31.84#ibcon#read 4, iclass 11, count 0 2006.162.08:04:31.84#ibcon#about to read 5, iclass 11, count 0 2006.162.08:04:31.84#ibcon#read 5, iclass 11, count 0 2006.162.08:04:31.84#ibcon#about to read 6, iclass 11, count 0 2006.162.08:04:31.84#ibcon#read 6, iclass 11, count 0 2006.162.08:04:31.84#ibcon#end of sib2, iclass 11, count 0 2006.162.08:04:31.84#ibcon#*mode == 0, iclass 11, count 0 2006.162.08:04:31.84#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.162.08:04:31.84#ibcon#[27=USB\r\n] 2006.162.08:04:31.84#ibcon#*before write, iclass 11, count 0 2006.162.08:04:31.84#ibcon#enter sib2, iclass 11, count 0 2006.162.08:04:31.84#ibcon#flushed, iclass 11, count 0 2006.162.08:04:31.84#ibcon#about to write, iclass 11, count 0 2006.162.08:04:31.84#ibcon#wrote, iclass 11, count 0 2006.162.08:04:31.84#ibcon#about to read 3, iclass 11, count 0 2006.162.08:04:31.87#ibcon#read 3, iclass 11, count 0 2006.162.08:04:31.87#ibcon#about to read 4, iclass 11, count 0 2006.162.08:04:31.87#ibcon#read 4, iclass 11, count 0 2006.162.08:04:31.87#ibcon#about to read 5, iclass 11, count 0 2006.162.08:04:31.87#ibcon#read 5, iclass 11, count 0 2006.162.08:04:31.87#ibcon#about to read 6, iclass 11, count 0 2006.162.08:04:31.87#ibcon#read 6, iclass 11, count 0 2006.162.08:04:31.87#ibcon#end of sib2, iclass 11, count 0 2006.162.08:04:31.87#ibcon#*after write, iclass 11, count 0 2006.162.08:04:31.87#ibcon#*before return 0, iclass 11, count 0 2006.162.08:04:31.87#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.162.08:04:31.87#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.162.08:04:31.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.162.08:04:31.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.162.08:04:31.87$vc4f8/vblo=2,640.99 2006.162.08:04:31.87#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.162.08:04:31.87#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.162.08:04:31.87#ibcon#ireg 17 cls_cnt 0 2006.162.08:04:31.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.162.08:04:31.87#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.162.08:04:31.87#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.162.08:04:31.87#ibcon#enter wrdev, iclass 13, count 0 2006.162.08:04:31.87#ibcon#first serial, iclass 13, count 0 2006.162.08:04:31.87#ibcon#enter sib2, iclass 13, count 0 2006.162.08:04:31.87#ibcon#flushed, iclass 13, count 0 2006.162.08:04:31.87#ibcon#about to write, iclass 13, count 0 2006.162.08:04:31.87#ibcon#wrote, iclass 13, count 0 2006.162.08:04:31.87#ibcon#about to read 3, iclass 13, count 0 2006.162.08:04:31.89#ibcon#read 3, iclass 13, count 0 2006.162.08:04:31.89#ibcon#about to read 4, iclass 13, count 0 2006.162.08:04:31.89#ibcon#read 4, iclass 13, count 0 2006.162.08:04:31.89#ibcon#about to read 5, iclass 13, count 0 2006.162.08:04:31.89#ibcon#read 5, iclass 13, count 0 2006.162.08:04:31.89#ibcon#about to read 6, iclass 13, count 0 2006.162.08:04:31.89#ibcon#read 6, iclass 13, count 0 2006.162.08:04:31.89#ibcon#end of sib2, iclass 13, count 0 2006.162.08:04:31.89#ibcon#*mode == 0, iclass 13, count 0 2006.162.08:04:31.89#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.162.08:04:31.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.08:04:31.89#ibcon#*before write, iclass 13, count 0 2006.162.08:04:31.89#ibcon#enter sib2, iclass 13, count 0 2006.162.08:04:31.89#ibcon#flushed, iclass 13, count 0 2006.162.08:04:31.89#ibcon#about to write, iclass 13, count 0 2006.162.08:04:31.89#ibcon#wrote, iclass 13, count 0 2006.162.08:04:31.89#ibcon#about to read 3, iclass 13, count 0 2006.162.08:04:31.93#ibcon#read 3, iclass 13, count 0 2006.162.08:04:31.93#ibcon#about to read 4, iclass 13, count 0 2006.162.08:04:31.93#ibcon#read 4, iclass 13, count 0 2006.162.08:04:31.93#ibcon#about to read 5, iclass 13, count 0 2006.162.08:04:31.93#ibcon#read 5, iclass 13, count 0 2006.162.08:04:31.93#ibcon#about to read 6, iclass 13, count 0 2006.162.08:04:31.93#ibcon#read 6, iclass 13, count 0 2006.162.08:04:31.93#ibcon#end of sib2, iclass 13, count 0 2006.162.08:04:31.93#ibcon#*after write, iclass 13, count 0 2006.162.08:04:31.93#ibcon#*before return 0, iclass 13, count 0 2006.162.08:04:31.93#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.162.08:04:31.93#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.162.08:04:31.93#ibcon#about to clear, iclass 13 cls_cnt 0 2006.162.08:04:31.93#ibcon#cleared, iclass 13 cls_cnt 0 2006.162.08:04:31.93$vc4f8/vb=2,4 2006.162.08:04:31.93#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.162.08:04:31.93#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.162.08:04:31.93#ibcon#ireg 11 cls_cnt 2 2006.162.08:04:31.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.162.08:04:31.99#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.162.08:04:31.99#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.162.08:04:31.99#ibcon#enter wrdev, iclass 15, count 2 2006.162.08:04:31.99#ibcon#first serial, iclass 15, count 2 2006.162.08:04:31.99#ibcon#enter sib2, iclass 15, count 2 2006.162.08:04:31.99#ibcon#flushed, iclass 15, count 2 2006.162.08:04:31.99#ibcon#about to write, iclass 15, count 2 2006.162.08:04:31.99#ibcon#wrote, iclass 15, count 2 2006.162.08:04:31.99#ibcon#about to read 3, iclass 15, count 2 2006.162.08:04:32.01#ibcon#read 3, iclass 15, count 2 2006.162.08:04:32.01#ibcon#about to read 4, iclass 15, count 2 2006.162.08:04:32.01#ibcon#read 4, iclass 15, count 2 2006.162.08:04:32.01#ibcon#about to read 5, iclass 15, count 2 2006.162.08:04:32.01#ibcon#read 5, iclass 15, count 2 2006.162.08:04:32.01#ibcon#about to read 6, iclass 15, count 2 2006.162.08:04:32.01#ibcon#read 6, iclass 15, count 2 2006.162.08:04:32.01#ibcon#end of sib2, iclass 15, count 2 2006.162.08:04:32.01#ibcon#*mode == 0, iclass 15, count 2 2006.162.08:04:32.01#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.162.08:04:32.01#ibcon#[27=AT02-04\r\n] 2006.162.08:04:32.01#ibcon#*before write, iclass 15, count 2 2006.162.08:04:32.01#ibcon#enter sib2, iclass 15, count 2 2006.162.08:04:32.01#ibcon#flushed, iclass 15, count 2 2006.162.08:04:32.01#ibcon#about to write, iclass 15, count 2 2006.162.08:04:32.01#ibcon#wrote, iclass 15, count 2 2006.162.08:04:32.01#ibcon#about to read 3, iclass 15, count 2 2006.162.08:04:32.04#ibcon#read 3, iclass 15, count 2 2006.162.08:04:32.04#ibcon#about to read 4, iclass 15, count 2 2006.162.08:04:32.04#ibcon#read 4, iclass 15, count 2 2006.162.08:04:32.04#ibcon#about to read 5, iclass 15, count 2 2006.162.08:04:32.04#ibcon#read 5, iclass 15, count 2 2006.162.08:04:32.04#ibcon#about to read 6, iclass 15, count 2 2006.162.08:04:32.04#ibcon#read 6, iclass 15, count 2 2006.162.08:04:32.04#ibcon#end of sib2, iclass 15, count 2 2006.162.08:04:32.04#ibcon#*after write, iclass 15, count 2 2006.162.08:04:32.04#ibcon#*before return 0, iclass 15, count 2 2006.162.08:04:32.04#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.162.08:04:32.04#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.162.08:04:32.04#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.162.08:04:32.04#ibcon#ireg 7 cls_cnt 0 2006.162.08:04:32.04#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.162.08:04:32.16#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.162.08:04:32.16#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.162.08:04:32.16#ibcon#enter wrdev, iclass 15, count 0 2006.162.08:04:32.16#ibcon#first serial, iclass 15, count 0 2006.162.08:04:32.16#ibcon#enter sib2, iclass 15, count 0 2006.162.08:04:32.16#ibcon#flushed, iclass 15, count 0 2006.162.08:04:32.16#ibcon#about to write, iclass 15, count 0 2006.162.08:04:32.16#ibcon#wrote, iclass 15, count 0 2006.162.08:04:32.16#ibcon#about to read 3, iclass 15, count 0 2006.162.08:04:32.18#ibcon#read 3, iclass 15, count 0 2006.162.08:04:32.18#ibcon#about to read 4, iclass 15, count 0 2006.162.08:04:32.18#ibcon#read 4, iclass 15, count 0 2006.162.08:04:32.18#ibcon#about to read 5, iclass 15, count 0 2006.162.08:04:32.18#ibcon#read 5, iclass 15, count 0 2006.162.08:04:32.18#ibcon#about to read 6, iclass 15, count 0 2006.162.08:04:32.18#ibcon#read 6, iclass 15, count 0 2006.162.08:04:32.18#ibcon#end of sib2, iclass 15, count 0 2006.162.08:04:32.18#ibcon#*mode == 0, iclass 15, count 0 2006.162.08:04:32.18#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.162.08:04:32.18#ibcon#[27=USB\r\n] 2006.162.08:04:32.18#ibcon#*before write, iclass 15, count 0 2006.162.08:04:32.18#ibcon#enter sib2, iclass 15, count 0 2006.162.08:04:32.18#ibcon#flushed, iclass 15, count 0 2006.162.08:04:32.18#ibcon#about to write, iclass 15, count 0 2006.162.08:04:32.18#ibcon#wrote, iclass 15, count 0 2006.162.08:04:32.18#ibcon#about to read 3, iclass 15, count 0 2006.162.08:04:32.21#ibcon#read 3, iclass 15, count 0 2006.162.08:04:32.21#ibcon#about to read 4, iclass 15, count 0 2006.162.08:04:32.21#ibcon#read 4, iclass 15, count 0 2006.162.08:04:32.21#ibcon#about to read 5, iclass 15, count 0 2006.162.08:04:32.21#ibcon#read 5, iclass 15, count 0 2006.162.08:04:32.21#ibcon#about to read 6, iclass 15, count 0 2006.162.08:04:32.21#ibcon#read 6, iclass 15, count 0 2006.162.08:04:32.21#ibcon#end of sib2, iclass 15, count 0 2006.162.08:04:32.21#ibcon#*after write, iclass 15, count 0 2006.162.08:04:32.21#ibcon#*before return 0, iclass 15, count 0 2006.162.08:04:32.21#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.162.08:04:32.21#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.162.08:04:32.21#ibcon#about to clear, iclass 15 cls_cnt 0 2006.162.08:04:32.21#ibcon#cleared, iclass 15 cls_cnt 0 2006.162.08:04:32.21$vc4f8/vblo=3,656.99 2006.162.08:04:32.21#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.162.08:04:32.21#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.162.08:04:32.21#ibcon#ireg 17 cls_cnt 0 2006.162.08:04:32.21#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.162.08:04:32.21#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.162.08:04:32.21#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.162.08:04:32.21#ibcon#enter wrdev, iclass 17, count 0 2006.162.08:04:32.21#ibcon#first serial, iclass 17, count 0 2006.162.08:04:32.21#ibcon#enter sib2, iclass 17, count 0 2006.162.08:04:32.21#ibcon#flushed, iclass 17, count 0 2006.162.08:04:32.21#ibcon#about to write, iclass 17, count 0 2006.162.08:04:32.21#ibcon#wrote, iclass 17, count 0 2006.162.08:04:32.21#ibcon#about to read 3, iclass 17, count 0 2006.162.08:04:32.23#ibcon#read 3, iclass 17, count 0 2006.162.08:04:32.23#ibcon#about to read 4, iclass 17, count 0 2006.162.08:04:32.23#ibcon#read 4, iclass 17, count 0 2006.162.08:04:32.23#ibcon#about to read 5, iclass 17, count 0 2006.162.08:04:32.23#ibcon#read 5, iclass 17, count 0 2006.162.08:04:32.23#ibcon#about to read 6, iclass 17, count 0 2006.162.08:04:32.23#ibcon#read 6, iclass 17, count 0 2006.162.08:04:32.23#ibcon#end of sib2, iclass 17, count 0 2006.162.08:04:32.23#ibcon#*mode == 0, iclass 17, count 0 2006.162.08:04:32.23#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.162.08:04:32.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.08:04:32.23#ibcon#*before write, iclass 17, count 0 2006.162.08:04:32.23#ibcon#enter sib2, iclass 17, count 0 2006.162.08:04:32.23#ibcon#flushed, iclass 17, count 0 2006.162.08:04:32.23#ibcon#about to write, iclass 17, count 0 2006.162.08:04:32.23#ibcon#wrote, iclass 17, count 0 2006.162.08:04:32.23#ibcon#about to read 3, iclass 17, count 0 2006.162.08:04:32.27#ibcon#read 3, iclass 17, count 0 2006.162.08:04:32.27#ibcon#about to read 4, iclass 17, count 0 2006.162.08:04:32.27#ibcon#read 4, iclass 17, count 0 2006.162.08:04:32.27#ibcon#about to read 5, iclass 17, count 0 2006.162.08:04:32.27#ibcon#read 5, iclass 17, count 0 2006.162.08:04:32.27#ibcon#about to read 6, iclass 17, count 0 2006.162.08:04:32.27#ibcon#read 6, iclass 17, count 0 2006.162.08:04:32.27#ibcon#end of sib2, iclass 17, count 0 2006.162.08:04:32.27#ibcon#*after write, iclass 17, count 0 2006.162.08:04:32.27#ibcon#*before return 0, iclass 17, count 0 2006.162.08:04:32.27#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.162.08:04:32.27#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.162.08:04:32.27#ibcon#about to clear, iclass 17 cls_cnt 0 2006.162.08:04:32.27#ibcon#cleared, iclass 17 cls_cnt 0 2006.162.08:04:32.27$vc4f8/vb=3,4 2006.162.08:04:32.27#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.162.08:04:32.27#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.162.08:04:32.27#ibcon#ireg 11 cls_cnt 2 2006.162.08:04:32.27#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.162.08:04:32.33#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.162.08:04:32.33#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.162.08:04:32.33#ibcon#enter wrdev, iclass 19, count 2 2006.162.08:04:32.33#ibcon#first serial, iclass 19, count 2 2006.162.08:04:32.33#ibcon#enter sib2, iclass 19, count 2 2006.162.08:04:32.33#ibcon#flushed, iclass 19, count 2 2006.162.08:04:32.33#ibcon#about to write, iclass 19, count 2 2006.162.08:04:32.33#ibcon#wrote, iclass 19, count 2 2006.162.08:04:32.33#ibcon#about to read 3, iclass 19, count 2 2006.162.08:04:32.35#ibcon#read 3, iclass 19, count 2 2006.162.08:04:32.35#ibcon#about to read 4, iclass 19, count 2 2006.162.08:04:32.35#ibcon#read 4, iclass 19, count 2 2006.162.08:04:32.35#ibcon#about to read 5, iclass 19, count 2 2006.162.08:04:32.35#ibcon#read 5, iclass 19, count 2 2006.162.08:04:32.35#ibcon#about to read 6, iclass 19, count 2 2006.162.08:04:32.35#ibcon#read 6, iclass 19, count 2 2006.162.08:04:32.35#ibcon#end of sib2, iclass 19, count 2 2006.162.08:04:32.35#ibcon#*mode == 0, iclass 19, count 2 2006.162.08:04:32.35#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.162.08:04:32.35#ibcon#[27=AT03-04\r\n] 2006.162.08:04:32.35#ibcon#*before write, iclass 19, count 2 2006.162.08:04:32.35#ibcon#enter sib2, iclass 19, count 2 2006.162.08:04:32.35#ibcon#flushed, iclass 19, count 2 2006.162.08:04:32.35#ibcon#about to write, iclass 19, count 2 2006.162.08:04:32.35#ibcon#wrote, iclass 19, count 2 2006.162.08:04:32.35#ibcon#about to read 3, iclass 19, count 2 2006.162.08:04:32.38#ibcon#read 3, iclass 19, count 2 2006.162.08:04:32.38#ibcon#about to read 4, iclass 19, count 2 2006.162.08:04:32.38#ibcon#read 4, iclass 19, count 2 2006.162.08:04:32.38#ibcon#about to read 5, iclass 19, count 2 2006.162.08:04:32.38#ibcon#read 5, iclass 19, count 2 2006.162.08:04:32.38#ibcon#about to read 6, iclass 19, count 2 2006.162.08:04:32.38#ibcon#read 6, iclass 19, count 2 2006.162.08:04:32.38#ibcon#end of sib2, iclass 19, count 2 2006.162.08:04:32.38#ibcon#*after write, iclass 19, count 2 2006.162.08:04:32.38#ibcon#*before return 0, iclass 19, count 2 2006.162.08:04:32.38#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.162.08:04:32.38#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.162.08:04:32.38#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.162.08:04:32.38#ibcon#ireg 7 cls_cnt 0 2006.162.08:04:32.38#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.162.08:04:32.50#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.162.08:04:32.50#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.162.08:04:32.50#ibcon#enter wrdev, iclass 19, count 0 2006.162.08:04:32.50#ibcon#first serial, iclass 19, count 0 2006.162.08:04:32.50#ibcon#enter sib2, iclass 19, count 0 2006.162.08:04:32.50#ibcon#flushed, iclass 19, count 0 2006.162.08:04:32.50#ibcon#about to write, iclass 19, count 0 2006.162.08:04:32.50#ibcon#wrote, iclass 19, count 0 2006.162.08:04:32.50#ibcon#about to read 3, iclass 19, count 0 2006.162.08:04:32.52#ibcon#read 3, iclass 19, count 0 2006.162.08:04:32.52#ibcon#about to read 4, iclass 19, count 0 2006.162.08:04:32.52#ibcon#read 4, iclass 19, count 0 2006.162.08:04:32.52#ibcon#about to read 5, iclass 19, count 0 2006.162.08:04:32.52#ibcon#read 5, iclass 19, count 0 2006.162.08:04:32.52#ibcon#about to read 6, iclass 19, count 0 2006.162.08:04:32.52#ibcon#read 6, iclass 19, count 0 2006.162.08:04:32.52#ibcon#end of sib2, iclass 19, count 0 2006.162.08:04:32.52#ibcon#*mode == 0, iclass 19, count 0 2006.162.08:04:32.52#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.162.08:04:32.52#ibcon#[27=USB\r\n] 2006.162.08:04:32.52#ibcon#*before write, iclass 19, count 0 2006.162.08:04:32.52#ibcon#enter sib2, iclass 19, count 0 2006.162.08:04:32.52#ibcon#flushed, iclass 19, count 0 2006.162.08:04:32.52#ibcon#about to write, iclass 19, count 0 2006.162.08:04:32.52#ibcon#wrote, iclass 19, count 0 2006.162.08:04:32.52#ibcon#about to read 3, iclass 19, count 0 2006.162.08:04:32.55#ibcon#read 3, iclass 19, count 0 2006.162.08:04:32.55#ibcon#about to read 4, iclass 19, count 0 2006.162.08:04:32.55#ibcon#read 4, iclass 19, count 0 2006.162.08:04:32.55#ibcon#about to read 5, iclass 19, count 0 2006.162.08:04:32.55#ibcon#read 5, iclass 19, count 0 2006.162.08:04:32.55#ibcon#about to read 6, iclass 19, count 0 2006.162.08:04:32.55#ibcon#read 6, iclass 19, count 0 2006.162.08:04:32.55#ibcon#end of sib2, iclass 19, count 0 2006.162.08:04:32.55#ibcon#*after write, iclass 19, count 0 2006.162.08:04:32.55#ibcon#*before return 0, iclass 19, count 0 2006.162.08:04:32.55#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.162.08:04:32.55#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.162.08:04:32.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.162.08:04:32.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.162.08:04:32.55$vc4f8/vblo=4,712.99 2006.162.08:04:32.55#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.162.08:04:32.55#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.162.08:04:32.55#ibcon#ireg 17 cls_cnt 0 2006.162.08:04:32.55#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:04:32.55#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:04:32.55#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:04:32.55#ibcon#enter wrdev, iclass 21, count 0 2006.162.08:04:32.55#ibcon#first serial, iclass 21, count 0 2006.162.08:04:32.55#ibcon#enter sib2, iclass 21, count 0 2006.162.08:04:32.55#ibcon#flushed, iclass 21, count 0 2006.162.08:04:32.55#ibcon#about to write, iclass 21, count 0 2006.162.08:04:32.55#ibcon#wrote, iclass 21, count 0 2006.162.08:04:32.55#ibcon#about to read 3, iclass 21, count 0 2006.162.08:04:32.57#ibcon#read 3, iclass 21, count 0 2006.162.08:04:32.57#ibcon#about to read 4, iclass 21, count 0 2006.162.08:04:32.57#ibcon#read 4, iclass 21, count 0 2006.162.08:04:32.57#ibcon#about to read 5, iclass 21, count 0 2006.162.08:04:32.57#ibcon#read 5, iclass 21, count 0 2006.162.08:04:32.57#ibcon#about to read 6, iclass 21, count 0 2006.162.08:04:32.57#ibcon#read 6, iclass 21, count 0 2006.162.08:04:32.57#ibcon#end of sib2, iclass 21, count 0 2006.162.08:04:32.57#ibcon#*mode == 0, iclass 21, count 0 2006.162.08:04:32.57#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.162.08:04:32.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.08:04:32.57#ibcon#*before write, iclass 21, count 0 2006.162.08:04:32.57#ibcon#enter sib2, iclass 21, count 0 2006.162.08:04:32.57#ibcon#flushed, iclass 21, count 0 2006.162.08:04:32.57#ibcon#about to write, iclass 21, count 0 2006.162.08:04:32.57#ibcon#wrote, iclass 21, count 0 2006.162.08:04:32.57#ibcon#about to read 3, iclass 21, count 0 2006.162.08:04:32.61#ibcon#read 3, iclass 21, count 0 2006.162.08:04:32.61#ibcon#about to read 4, iclass 21, count 0 2006.162.08:04:32.61#ibcon#read 4, iclass 21, count 0 2006.162.08:04:32.61#ibcon#about to read 5, iclass 21, count 0 2006.162.08:04:32.61#ibcon#read 5, iclass 21, count 0 2006.162.08:04:32.61#ibcon#about to read 6, iclass 21, count 0 2006.162.08:04:32.61#ibcon#read 6, iclass 21, count 0 2006.162.08:04:32.61#ibcon#end of sib2, iclass 21, count 0 2006.162.08:04:32.61#ibcon#*after write, iclass 21, count 0 2006.162.08:04:32.61#ibcon#*before return 0, iclass 21, count 0 2006.162.08:04:32.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:04:32.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:04:32.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.162.08:04:32.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.162.08:04:32.61$vc4f8/vb=4,4 2006.162.08:04:32.61#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.162.08:04:32.61#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.162.08:04:32.61#ibcon#ireg 11 cls_cnt 2 2006.162.08:04:32.61#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:04:32.67#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:04:32.67#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:04:32.67#ibcon#enter wrdev, iclass 23, count 2 2006.162.08:04:32.67#ibcon#first serial, iclass 23, count 2 2006.162.08:04:32.67#ibcon#enter sib2, iclass 23, count 2 2006.162.08:04:32.67#ibcon#flushed, iclass 23, count 2 2006.162.08:04:32.67#ibcon#about to write, iclass 23, count 2 2006.162.08:04:32.67#ibcon#wrote, iclass 23, count 2 2006.162.08:04:32.67#ibcon#about to read 3, iclass 23, count 2 2006.162.08:04:32.69#ibcon#read 3, iclass 23, count 2 2006.162.08:04:32.69#ibcon#about to read 4, iclass 23, count 2 2006.162.08:04:32.69#ibcon#read 4, iclass 23, count 2 2006.162.08:04:32.69#ibcon#about to read 5, iclass 23, count 2 2006.162.08:04:32.69#ibcon#read 5, iclass 23, count 2 2006.162.08:04:32.69#ibcon#about to read 6, iclass 23, count 2 2006.162.08:04:32.69#ibcon#read 6, iclass 23, count 2 2006.162.08:04:32.69#ibcon#end of sib2, iclass 23, count 2 2006.162.08:04:32.69#ibcon#*mode == 0, iclass 23, count 2 2006.162.08:04:32.69#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.162.08:04:32.69#ibcon#[27=AT04-04\r\n] 2006.162.08:04:32.69#ibcon#*before write, iclass 23, count 2 2006.162.08:04:32.69#ibcon#enter sib2, iclass 23, count 2 2006.162.08:04:32.69#ibcon#flushed, iclass 23, count 2 2006.162.08:04:32.69#ibcon#about to write, iclass 23, count 2 2006.162.08:04:32.69#ibcon#wrote, iclass 23, count 2 2006.162.08:04:32.69#ibcon#about to read 3, iclass 23, count 2 2006.162.08:04:32.72#ibcon#read 3, iclass 23, count 2 2006.162.08:04:32.72#ibcon#about to read 4, iclass 23, count 2 2006.162.08:04:32.72#ibcon#read 4, iclass 23, count 2 2006.162.08:04:32.72#ibcon#about to read 5, iclass 23, count 2 2006.162.08:04:32.72#ibcon#read 5, iclass 23, count 2 2006.162.08:04:32.72#ibcon#about to read 6, iclass 23, count 2 2006.162.08:04:32.72#ibcon#read 6, iclass 23, count 2 2006.162.08:04:32.72#ibcon#end of sib2, iclass 23, count 2 2006.162.08:04:32.72#ibcon#*after write, iclass 23, count 2 2006.162.08:04:32.72#ibcon#*before return 0, iclass 23, count 2 2006.162.08:04:32.72#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:04:32.72#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:04:32.72#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.162.08:04:32.72#ibcon#ireg 7 cls_cnt 0 2006.162.08:04:32.72#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:04:32.84#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:04:32.84#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:04:32.84#ibcon#enter wrdev, iclass 23, count 0 2006.162.08:04:32.84#ibcon#first serial, iclass 23, count 0 2006.162.08:04:32.84#ibcon#enter sib2, iclass 23, count 0 2006.162.08:04:32.84#ibcon#flushed, iclass 23, count 0 2006.162.08:04:32.84#ibcon#about to write, iclass 23, count 0 2006.162.08:04:32.84#ibcon#wrote, iclass 23, count 0 2006.162.08:04:32.84#ibcon#about to read 3, iclass 23, count 0 2006.162.08:04:32.86#ibcon#read 3, iclass 23, count 0 2006.162.08:04:32.86#ibcon#about to read 4, iclass 23, count 0 2006.162.08:04:32.86#ibcon#read 4, iclass 23, count 0 2006.162.08:04:32.86#ibcon#about to read 5, iclass 23, count 0 2006.162.08:04:32.86#ibcon#read 5, iclass 23, count 0 2006.162.08:04:32.86#ibcon#about to read 6, iclass 23, count 0 2006.162.08:04:32.86#ibcon#read 6, iclass 23, count 0 2006.162.08:04:32.86#ibcon#end of sib2, iclass 23, count 0 2006.162.08:04:32.86#ibcon#*mode == 0, iclass 23, count 0 2006.162.08:04:32.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.162.08:04:32.86#ibcon#[27=USB\r\n] 2006.162.08:04:32.86#ibcon#*before write, iclass 23, count 0 2006.162.08:04:32.86#ibcon#enter sib2, iclass 23, count 0 2006.162.08:04:32.86#ibcon#flushed, iclass 23, count 0 2006.162.08:04:32.86#ibcon#about to write, iclass 23, count 0 2006.162.08:04:32.86#ibcon#wrote, iclass 23, count 0 2006.162.08:04:32.86#ibcon#about to read 3, iclass 23, count 0 2006.162.08:04:32.89#ibcon#read 3, iclass 23, count 0 2006.162.08:04:32.89#ibcon#about to read 4, iclass 23, count 0 2006.162.08:04:32.89#ibcon#read 4, iclass 23, count 0 2006.162.08:04:32.89#ibcon#about to read 5, iclass 23, count 0 2006.162.08:04:32.89#ibcon#read 5, iclass 23, count 0 2006.162.08:04:32.89#ibcon#about to read 6, iclass 23, count 0 2006.162.08:04:32.89#ibcon#read 6, iclass 23, count 0 2006.162.08:04:32.89#ibcon#end of sib2, iclass 23, count 0 2006.162.08:04:32.89#ibcon#*after write, iclass 23, count 0 2006.162.08:04:32.89#ibcon#*before return 0, iclass 23, count 0 2006.162.08:04:32.89#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:04:32.89#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:04:32.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.162.08:04:32.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.162.08:04:32.89$vc4f8/vblo=5,744.99 2006.162.08:04:32.89#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.162.08:04:32.89#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.162.08:04:32.89#ibcon#ireg 17 cls_cnt 0 2006.162.08:04:32.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:04:32.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:04:32.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:04:32.89#ibcon#enter wrdev, iclass 25, count 0 2006.162.08:04:32.89#ibcon#first serial, iclass 25, count 0 2006.162.08:04:32.89#ibcon#enter sib2, iclass 25, count 0 2006.162.08:04:32.89#ibcon#flushed, iclass 25, count 0 2006.162.08:04:32.89#ibcon#about to write, iclass 25, count 0 2006.162.08:04:32.89#ibcon#wrote, iclass 25, count 0 2006.162.08:04:32.89#ibcon#about to read 3, iclass 25, count 0 2006.162.08:04:32.91#ibcon#read 3, iclass 25, count 0 2006.162.08:04:32.91#ibcon#about to read 4, iclass 25, count 0 2006.162.08:04:32.91#ibcon#read 4, iclass 25, count 0 2006.162.08:04:32.91#ibcon#about to read 5, iclass 25, count 0 2006.162.08:04:32.91#ibcon#read 5, iclass 25, count 0 2006.162.08:04:32.91#ibcon#about to read 6, iclass 25, count 0 2006.162.08:04:32.91#ibcon#read 6, iclass 25, count 0 2006.162.08:04:32.91#ibcon#end of sib2, iclass 25, count 0 2006.162.08:04:32.91#ibcon#*mode == 0, iclass 25, count 0 2006.162.08:04:32.91#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.162.08:04:32.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.08:04:32.91#ibcon#*before write, iclass 25, count 0 2006.162.08:04:32.91#ibcon#enter sib2, iclass 25, count 0 2006.162.08:04:32.91#ibcon#flushed, iclass 25, count 0 2006.162.08:04:32.91#ibcon#about to write, iclass 25, count 0 2006.162.08:04:32.91#ibcon#wrote, iclass 25, count 0 2006.162.08:04:32.91#ibcon#about to read 3, iclass 25, count 0 2006.162.08:04:32.95#ibcon#read 3, iclass 25, count 0 2006.162.08:04:32.95#ibcon#about to read 4, iclass 25, count 0 2006.162.08:04:32.95#ibcon#read 4, iclass 25, count 0 2006.162.08:04:32.95#ibcon#about to read 5, iclass 25, count 0 2006.162.08:04:32.95#ibcon#read 5, iclass 25, count 0 2006.162.08:04:32.95#ibcon#about to read 6, iclass 25, count 0 2006.162.08:04:32.95#ibcon#read 6, iclass 25, count 0 2006.162.08:04:32.95#ibcon#end of sib2, iclass 25, count 0 2006.162.08:04:32.95#ibcon#*after write, iclass 25, count 0 2006.162.08:04:32.95#ibcon#*before return 0, iclass 25, count 0 2006.162.08:04:32.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:04:32.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:04:32.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.162.08:04:32.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.162.08:04:32.95$vc4f8/vb=5,4 2006.162.08:04:32.95#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.162.08:04:32.95#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.162.08:04:32.95#ibcon#ireg 11 cls_cnt 2 2006.162.08:04:32.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:04:33.01#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:04:33.01#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:04:33.01#ibcon#enter wrdev, iclass 27, count 2 2006.162.08:04:33.01#ibcon#first serial, iclass 27, count 2 2006.162.08:04:33.01#ibcon#enter sib2, iclass 27, count 2 2006.162.08:04:33.01#ibcon#flushed, iclass 27, count 2 2006.162.08:04:33.01#ibcon#about to write, iclass 27, count 2 2006.162.08:04:33.01#ibcon#wrote, iclass 27, count 2 2006.162.08:04:33.01#ibcon#about to read 3, iclass 27, count 2 2006.162.08:04:33.03#ibcon#read 3, iclass 27, count 2 2006.162.08:04:33.03#ibcon#about to read 4, iclass 27, count 2 2006.162.08:04:33.03#ibcon#read 4, iclass 27, count 2 2006.162.08:04:33.03#ibcon#about to read 5, iclass 27, count 2 2006.162.08:04:33.03#ibcon#read 5, iclass 27, count 2 2006.162.08:04:33.03#ibcon#about to read 6, iclass 27, count 2 2006.162.08:04:33.03#ibcon#read 6, iclass 27, count 2 2006.162.08:04:33.03#ibcon#end of sib2, iclass 27, count 2 2006.162.08:04:33.03#ibcon#*mode == 0, iclass 27, count 2 2006.162.08:04:33.03#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.162.08:04:33.03#ibcon#[27=AT05-04\r\n] 2006.162.08:04:33.03#ibcon#*before write, iclass 27, count 2 2006.162.08:04:33.03#ibcon#enter sib2, iclass 27, count 2 2006.162.08:04:33.03#ibcon#flushed, iclass 27, count 2 2006.162.08:04:33.03#ibcon#about to write, iclass 27, count 2 2006.162.08:04:33.03#ibcon#wrote, iclass 27, count 2 2006.162.08:04:33.03#ibcon#about to read 3, iclass 27, count 2 2006.162.08:04:33.06#ibcon#read 3, iclass 27, count 2 2006.162.08:04:33.06#ibcon#about to read 4, iclass 27, count 2 2006.162.08:04:33.06#ibcon#read 4, iclass 27, count 2 2006.162.08:04:33.06#ibcon#about to read 5, iclass 27, count 2 2006.162.08:04:33.06#ibcon#read 5, iclass 27, count 2 2006.162.08:04:33.06#ibcon#about to read 6, iclass 27, count 2 2006.162.08:04:33.06#ibcon#read 6, iclass 27, count 2 2006.162.08:04:33.06#ibcon#end of sib2, iclass 27, count 2 2006.162.08:04:33.06#ibcon#*after write, iclass 27, count 2 2006.162.08:04:33.06#ibcon#*before return 0, iclass 27, count 2 2006.162.08:04:33.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:04:33.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:04:33.06#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.162.08:04:33.06#ibcon#ireg 7 cls_cnt 0 2006.162.08:04:33.06#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:04:33.18#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:04:33.18#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:04:33.18#ibcon#enter wrdev, iclass 27, count 0 2006.162.08:04:33.18#ibcon#first serial, iclass 27, count 0 2006.162.08:04:33.18#ibcon#enter sib2, iclass 27, count 0 2006.162.08:04:33.18#ibcon#flushed, iclass 27, count 0 2006.162.08:04:33.18#ibcon#about to write, iclass 27, count 0 2006.162.08:04:33.18#ibcon#wrote, iclass 27, count 0 2006.162.08:04:33.18#ibcon#about to read 3, iclass 27, count 0 2006.162.08:04:33.20#ibcon#read 3, iclass 27, count 0 2006.162.08:04:33.20#ibcon#about to read 4, iclass 27, count 0 2006.162.08:04:33.20#ibcon#read 4, iclass 27, count 0 2006.162.08:04:33.20#ibcon#about to read 5, iclass 27, count 0 2006.162.08:04:33.20#ibcon#read 5, iclass 27, count 0 2006.162.08:04:33.20#ibcon#about to read 6, iclass 27, count 0 2006.162.08:04:33.20#ibcon#read 6, iclass 27, count 0 2006.162.08:04:33.20#ibcon#end of sib2, iclass 27, count 0 2006.162.08:04:33.20#ibcon#*mode == 0, iclass 27, count 0 2006.162.08:04:33.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.162.08:04:33.20#ibcon#[27=USB\r\n] 2006.162.08:04:33.20#ibcon#*before write, iclass 27, count 0 2006.162.08:04:33.20#ibcon#enter sib2, iclass 27, count 0 2006.162.08:04:33.20#ibcon#flushed, iclass 27, count 0 2006.162.08:04:33.20#ibcon#about to write, iclass 27, count 0 2006.162.08:04:33.20#ibcon#wrote, iclass 27, count 0 2006.162.08:04:33.20#ibcon#about to read 3, iclass 27, count 0 2006.162.08:04:33.23#ibcon#read 3, iclass 27, count 0 2006.162.08:04:33.23#ibcon#about to read 4, iclass 27, count 0 2006.162.08:04:33.23#ibcon#read 4, iclass 27, count 0 2006.162.08:04:33.23#ibcon#about to read 5, iclass 27, count 0 2006.162.08:04:33.23#ibcon#read 5, iclass 27, count 0 2006.162.08:04:33.23#ibcon#about to read 6, iclass 27, count 0 2006.162.08:04:33.23#ibcon#read 6, iclass 27, count 0 2006.162.08:04:33.23#ibcon#end of sib2, iclass 27, count 0 2006.162.08:04:33.23#ibcon#*after write, iclass 27, count 0 2006.162.08:04:33.23#ibcon#*before return 0, iclass 27, count 0 2006.162.08:04:33.23#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:04:33.23#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:04:33.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.162.08:04:33.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.162.08:04:33.23$vc4f8/vblo=6,752.99 2006.162.08:04:33.23#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.162.08:04:33.23#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.162.08:04:33.23#ibcon#ireg 17 cls_cnt 0 2006.162.08:04:33.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:04:33.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:04:33.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:04:33.23#ibcon#enter wrdev, iclass 29, count 0 2006.162.08:04:33.23#ibcon#first serial, iclass 29, count 0 2006.162.08:04:33.23#ibcon#enter sib2, iclass 29, count 0 2006.162.08:04:33.23#ibcon#flushed, iclass 29, count 0 2006.162.08:04:33.23#ibcon#about to write, iclass 29, count 0 2006.162.08:04:33.23#ibcon#wrote, iclass 29, count 0 2006.162.08:04:33.23#ibcon#about to read 3, iclass 29, count 0 2006.162.08:04:33.25#ibcon#read 3, iclass 29, count 0 2006.162.08:04:33.25#ibcon#about to read 4, iclass 29, count 0 2006.162.08:04:33.25#ibcon#read 4, iclass 29, count 0 2006.162.08:04:33.25#ibcon#about to read 5, iclass 29, count 0 2006.162.08:04:33.25#ibcon#read 5, iclass 29, count 0 2006.162.08:04:33.25#ibcon#about to read 6, iclass 29, count 0 2006.162.08:04:33.25#ibcon#read 6, iclass 29, count 0 2006.162.08:04:33.25#ibcon#end of sib2, iclass 29, count 0 2006.162.08:04:33.25#ibcon#*mode == 0, iclass 29, count 0 2006.162.08:04:33.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.162.08:04:33.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.08:04:33.25#ibcon#*before write, iclass 29, count 0 2006.162.08:04:33.25#ibcon#enter sib2, iclass 29, count 0 2006.162.08:04:33.25#ibcon#flushed, iclass 29, count 0 2006.162.08:04:33.25#ibcon#about to write, iclass 29, count 0 2006.162.08:04:33.25#ibcon#wrote, iclass 29, count 0 2006.162.08:04:33.25#ibcon#about to read 3, iclass 29, count 0 2006.162.08:04:33.29#ibcon#read 3, iclass 29, count 0 2006.162.08:04:33.29#ibcon#about to read 4, iclass 29, count 0 2006.162.08:04:33.29#ibcon#read 4, iclass 29, count 0 2006.162.08:04:33.29#ibcon#about to read 5, iclass 29, count 0 2006.162.08:04:33.29#ibcon#read 5, iclass 29, count 0 2006.162.08:04:33.29#ibcon#about to read 6, iclass 29, count 0 2006.162.08:04:33.29#ibcon#read 6, iclass 29, count 0 2006.162.08:04:33.29#ibcon#end of sib2, iclass 29, count 0 2006.162.08:04:33.29#ibcon#*after write, iclass 29, count 0 2006.162.08:04:33.29#ibcon#*before return 0, iclass 29, count 0 2006.162.08:04:33.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:04:33.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:04:33.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.162.08:04:33.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.162.08:04:33.29$vc4f8/vb=6,4 2006.162.08:04:33.29#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.162.08:04:33.29#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.162.08:04:33.29#ibcon#ireg 11 cls_cnt 2 2006.162.08:04:33.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:04:33.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:04:33.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:04:33.35#ibcon#enter wrdev, iclass 31, count 2 2006.162.08:04:33.35#ibcon#first serial, iclass 31, count 2 2006.162.08:04:33.35#ibcon#enter sib2, iclass 31, count 2 2006.162.08:04:33.35#ibcon#flushed, iclass 31, count 2 2006.162.08:04:33.35#ibcon#about to write, iclass 31, count 2 2006.162.08:04:33.35#ibcon#wrote, iclass 31, count 2 2006.162.08:04:33.35#ibcon#about to read 3, iclass 31, count 2 2006.162.08:04:33.37#ibcon#read 3, iclass 31, count 2 2006.162.08:04:33.37#ibcon#about to read 4, iclass 31, count 2 2006.162.08:04:33.37#ibcon#read 4, iclass 31, count 2 2006.162.08:04:33.37#ibcon#about to read 5, iclass 31, count 2 2006.162.08:04:33.37#ibcon#read 5, iclass 31, count 2 2006.162.08:04:33.37#ibcon#about to read 6, iclass 31, count 2 2006.162.08:04:33.37#ibcon#read 6, iclass 31, count 2 2006.162.08:04:33.37#ibcon#end of sib2, iclass 31, count 2 2006.162.08:04:33.37#ibcon#*mode == 0, iclass 31, count 2 2006.162.08:04:33.37#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.162.08:04:33.37#ibcon#[27=AT06-04\r\n] 2006.162.08:04:33.37#ibcon#*before write, iclass 31, count 2 2006.162.08:04:33.37#ibcon#enter sib2, iclass 31, count 2 2006.162.08:04:33.37#ibcon#flushed, iclass 31, count 2 2006.162.08:04:33.37#ibcon#about to write, iclass 31, count 2 2006.162.08:04:33.37#ibcon#wrote, iclass 31, count 2 2006.162.08:04:33.37#ibcon#about to read 3, iclass 31, count 2 2006.162.08:04:33.40#ibcon#read 3, iclass 31, count 2 2006.162.08:04:33.40#ibcon#about to read 4, iclass 31, count 2 2006.162.08:04:33.40#ibcon#read 4, iclass 31, count 2 2006.162.08:04:33.40#ibcon#about to read 5, iclass 31, count 2 2006.162.08:04:33.40#ibcon#read 5, iclass 31, count 2 2006.162.08:04:33.40#ibcon#about to read 6, iclass 31, count 2 2006.162.08:04:33.40#ibcon#read 6, iclass 31, count 2 2006.162.08:04:33.40#ibcon#end of sib2, iclass 31, count 2 2006.162.08:04:33.40#ibcon#*after write, iclass 31, count 2 2006.162.08:04:33.40#ibcon#*before return 0, iclass 31, count 2 2006.162.08:04:33.40#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:04:33.40#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:04:33.40#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.162.08:04:33.40#ibcon#ireg 7 cls_cnt 0 2006.162.08:04:33.40#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:04:33.52#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:04:33.52#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:04:33.52#ibcon#enter wrdev, iclass 31, count 0 2006.162.08:04:33.52#ibcon#first serial, iclass 31, count 0 2006.162.08:04:33.52#ibcon#enter sib2, iclass 31, count 0 2006.162.08:04:33.52#ibcon#flushed, iclass 31, count 0 2006.162.08:04:33.52#ibcon#about to write, iclass 31, count 0 2006.162.08:04:33.52#ibcon#wrote, iclass 31, count 0 2006.162.08:04:33.52#ibcon#about to read 3, iclass 31, count 0 2006.162.08:04:33.54#ibcon#read 3, iclass 31, count 0 2006.162.08:04:33.54#ibcon#about to read 4, iclass 31, count 0 2006.162.08:04:33.54#ibcon#read 4, iclass 31, count 0 2006.162.08:04:33.54#ibcon#about to read 5, iclass 31, count 0 2006.162.08:04:33.54#ibcon#read 5, iclass 31, count 0 2006.162.08:04:33.54#ibcon#about to read 6, iclass 31, count 0 2006.162.08:04:33.54#ibcon#read 6, iclass 31, count 0 2006.162.08:04:33.54#ibcon#end of sib2, iclass 31, count 0 2006.162.08:04:33.54#ibcon#*mode == 0, iclass 31, count 0 2006.162.08:04:33.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.162.08:04:33.54#ibcon#[27=USB\r\n] 2006.162.08:04:33.54#ibcon#*before write, iclass 31, count 0 2006.162.08:04:33.54#ibcon#enter sib2, iclass 31, count 0 2006.162.08:04:33.54#ibcon#flushed, iclass 31, count 0 2006.162.08:04:33.54#ibcon#about to write, iclass 31, count 0 2006.162.08:04:33.54#ibcon#wrote, iclass 31, count 0 2006.162.08:04:33.54#ibcon#about to read 3, iclass 31, count 0 2006.162.08:04:33.57#ibcon#read 3, iclass 31, count 0 2006.162.08:04:33.57#ibcon#about to read 4, iclass 31, count 0 2006.162.08:04:33.57#ibcon#read 4, iclass 31, count 0 2006.162.08:04:33.57#ibcon#about to read 5, iclass 31, count 0 2006.162.08:04:33.57#ibcon#read 5, iclass 31, count 0 2006.162.08:04:33.57#ibcon#about to read 6, iclass 31, count 0 2006.162.08:04:33.57#ibcon#read 6, iclass 31, count 0 2006.162.08:04:33.57#ibcon#end of sib2, iclass 31, count 0 2006.162.08:04:33.57#ibcon#*after write, iclass 31, count 0 2006.162.08:04:33.57#ibcon#*before return 0, iclass 31, count 0 2006.162.08:04:33.57#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:04:33.57#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:04:33.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.162.08:04:33.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.162.08:04:33.57$vc4f8/vabw=wide 2006.162.08:04:33.57#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.162.08:04:33.57#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.162.08:04:33.57#ibcon#ireg 8 cls_cnt 0 2006.162.08:04:33.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:04:33.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:04:33.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:04:33.57#ibcon#enter wrdev, iclass 33, count 0 2006.162.08:04:33.57#ibcon#first serial, iclass 33, count 0 2006.162.08:04:33.57#ibcon#enter sib2, iclass 33, count 0 2006.162.08:04:33.57#ibcon#flushed, iclass 33, count 0 2006.162.08:04:33.57#ibcon#about to write, iclass 33, count 0 2006.162.08:04:33.57#ibcon#wrote, iclass 33, count 0 2006.162.08:04:33.57#ibcon#about to read 3, iclass 33, count 0 2006.162.08:04:33.59#ibcon#read 3, iclass 33, count 0 2006.162.08:04:33.59#ibcon#about to read 4, iclass 33, count 0 2006.162.08:04:33.59#ibcon#read 4, iclass 33, count 0 2006.162.08:04:33.59#ibcon#about to read 5, iclass 33, count 0 2006.162.08:04:33.59#ibcon#read 5, iclass 33, count 0 2006.162.08:04:33.59#ibcon#about to read 6, iclass 33, count 0 2006.162.08:04:33.59#ibcon#read 6, iclass 33, count 0 2006.162.08:04:33.59#ibcon#end of sib2, iclass 33, count 0 2006.162.08:04:33.59#ibcon#*mode == 0, iclass 33, count 0 2006.162.08:04:33.59#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.162.08:04:33.59#ibcon#[25=BW32\r\n] 2006.162.08:04:33.59#ibcon#*before write, iclass 33, count 0 2006.162.08:04:33.59#ibcon#enter sib2, iclass 33, count 0 2006.162.08:04:33.59#ibcon#flushed, iclass 33, count 0 2006.162.08:04:33.59#ibcon#about to write, iclass 33, count 0 2006.162.08:04:33.59#ibcon#wrote, iclass 33, count 0 2006.162.08:04:33.59#ibcon#about to read 3, iclass 33, count 0 2006.162.08:04:33.62#ibcon#read 3, iclass 33, count 0 2006.162.08:04:33.62#ibcon#about to read 4, iclass 33, count 0 2006.162.08:04:33.62#ibcon#read 4, iclass 33, count 0 2006.162.08:04:33.62#ibcon#about to read 5, iclass 33, count 0 2006.162.08:04:33.62#ibcon#read 5, iclass 33, count 0 2006.162.08:04:33.62#ibcon#about to read 6, iclass 33, count 0 2006.162.08:04:33.62#ibcon#read 6, iclass 33, count 0 2006.162.08:04:33.62#ibcon#end of sib2, iclass 33, count 0 2006.162.08:04:33.62#ibcon#*after write, iclass 33, count 0 2006.162.08:04:33.62#ibcon#*before return 0, iclass 33, count 0 2006.162.08:04:33.62#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:04:33.62#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:04:33.62#ibcon#about to clear, iclass 33 cls_cnt 0 2006.162.08:04:33.62#ibcon#cleared, iclass 33 cls_cnt 0 2006.162.08:04:33.62$vc4f8/vbbw=wide 2006.162.08:04:33.62#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.162.08:04:33.62#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.162.08:04:33.62#ibcon#ireg 8 cls_cnt 0 2006.162.08:04:33.62#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.162.08:04:33.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.162.08:04:33.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.162.08:04:33.69#ibcon#enter wrdev, iclass 35, count 0 2006.162.08:04:33.69#ibcon#first serial, iclass 35, count 0 2006.162.08:04:33.69#ibcon#enter sib2, iclass 35, count 0 2006.162.08:04:33.69#ibcon#flushed, iclass 35, count 0 2006.162.08:04:33.69#ibcon#about to write, iclass 35, count 0 2006.162.08:04:33.69#ibcon#wrote, iclass 35, count 0 2006.162.08:04:33.69#ibcon#about to read 3, iclass 35, count 0 2006.162.08:04:33.71#ibcon#read 3, iclass 35, count 0 2006.162.08:04:33.71#ibcon#about to read 4, iclass 35, count 0 2006.162.08:04:33.71#ibcon#read 4, iclass 35, count 0 2006.162.08:04:33.71#ibcon#about to read 5, iclass 35, count 0 2006.162.08:04:33.71#ibcon#read 5, iclass 35, count 0 2006.162.08:04:33.71#ibcon#about to read 6, iclass 35, count 0 2006.162.08:04:33.71#ibcon#read 6, iclass 35, count 0 2006.162.08:04:33.71#ibcon#end of sib2, iclass 35, count 0 2006.162.08:04:33.71#ibcon#*mode == 0, iclass 35, count 0 2006.162.08:04:33.71#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.162.08:04:33.71#ibcon#[27=BW32\r\n] 2006.162.08:04:33.71#ibcon#*before write, iclass 35, count 0 2006.162.08:04:33.71#ibcon#enter sib2, iclass 35, count 0 2006.162.08:04:33.71#ibcon#flushed, iclass 35, count 0 2006.162.08:04:33.71#ibcon#about to write, iclass 35, count 0 2006.162.08:04:33.71#ibcon#wrote, iclass 35, count 0 2006.162.08:04:33.71#ibcon#about to read 3, iclass 35, count 0 2006.162.08:04:33.74#ibcon#read 3, iclass 35, count 0 2006.162.08:04:33.74#ibcon#about to read 4, iclass 35, count 0 2006.162.08:04:33.74#ibcon#read 4, iclass 35, count 0 2006.162.08:04:33.74#ibcon#about to read 5, iclass 35, count 0 2006.162.08:04:33.74#ibcon#read 5, iclass 35, count 0 2006.162.08:04:33.74#ibcon#about to read 6, iclass 35, count 0 2006.162.08:04:33.74#ibcon#read 6, iclass 35, count 0 2006.162.08:04:33.74#ibcon#end of sib2, iclass 35, count 0 2006.162.08:04:33.74#ibcon#*after write, iclass 35, count 0 2006.162.08:04:33.74#ibcon#*before return 0, iclass 35, count 0 2006.162.08:04:33.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.162.08:04:33.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.162.08:04:33.74#ibcon#about to clear, iclass 35 cls_cnt 0 2006.162.08:04:33.74#ibcon#cleared, iclass 35 cls_cnt 0 2006.162.08:04:33.74$4f8m12a/ifd4f 2006.162.08:04:33.74$ifd4f/lo= 2006.162.08:04:33.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.08:04:33.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.08:04:33.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.08:04:33.74$ifd4f/patch= 2006.162.08:04:33.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.08:04:33.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.08:04:33.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.08:04:33.74$4f8m12a/"form=m,16.000,1:2 2006.162.08:04:33.74$4f8m12a/"tpicd 2006.162.08:04:33.74$4f8m12a/echo=off 2006.162.08:04:33.74$4f8m12a/xlog=off 2006.162.08:04:33.74:!2006.162.08:05:00 2006.162.08:04:42.14#trakl#Source acquired 2006.162.08:04:42.14#flagr#flagr/antenna,acquired 2006.162.08:05:00.00:preob 2006.162.08:05:01.14/onsource/TRACKING 2006.162.08:05:01.14:!2006.162.08:05:10 2006.162.08:05:10.00:data_valid=on 2006.162.08:05:10.00:midob 2006.162.08:05:10.14/onsource/TRACKING 2006.162.08:05:10.14/wx/17.86,1007.0,100 2006.162.08:05:10.24/cable/+6.5372E-03 2006.162.08:05:11.33/va/01,08,usb,yes,36,38 2006.162.08:05:11.33/va/02,07,usb,yes,36,38 2006.162.08:05:11.33/va/03,06,usb,yes,38,39 2006.162.08:05:11.33/va/04,07,usb,yes,37,40 2006.162.08:05:11.33/va/05,07,usb,yes,40,42 2006.162.08:05:11.33/va/06,06,usb,yes,39,39 2006.162.08:05:11.33/va/07,06,usb,yes,39,39 2006.162.08:05:11.33/va/08,07,usb,yes,37,37 2006.162.08:05:11.56/valo/01,532.99,yes,locked 2006.162.08:05:11.56/valo/02,572.99,yes,locked 2006.162.08:05:11.56/valo/03,672.99,yes,locked 2006.162.08:05:11.56/valo/04,832.99,yes,locked 2006.162.08:05:11.56/valo/05,652.99,yes,locked 2006.162.08:05:11.56/valo/06,772.99,yes,locked 2006.162.08:05:11.56/valo/07,832.99,yes,locked 2006.162.08:05:11.56/valo/08,852.99,yes,locked 2006.162.08:05:12.65/vb/01,04,usb,yes,29,28 2006.162.08:05:12.65/vb/02,04,usb,yes,31,32 2006.162.08:05:12.65/vb/03,04,usb,yes,27,31 2006.162.08:05:12.65/vb/04,04,usb,yes,28,28 2006.162.08:05:12.65/vb/05,04,usb,yes,27,31 2006.162.08:05:12.65/vb/06,04,usb,yes,28,30 2006.162.08:05:12.65/vb/07,04,usb,yes,30,30 2006.162.08:05:12.65/vb/08,04,usb,yes,27,31 2006.162.08:05:12.89/vblo/01,632.99,yes,locked 2006.162.08:05:12.89/vblo/02,640.99,yes,locked 2006.162.08:05:12.89/vblo/03,656.99,yes,locked 2006.162.08:05:12.89/vblo/04,712.99,yes,locked 2006.162.08:05:12.89/vblo/05,744.99,yes,locked 2006.162.08:05:12.89/vblo/06,752.99,yes,locked 2006.162.08:05:12.89/vblo/07,734.99,yes,locked 2006.162.08:05:12.89/vblo/08,744.99,yes,locked 2006.162.08:05:13.04/vabw/8 2006.162.08:05:13.19/vbbw/8 2006.162.08:05:13.40/xfe/off,on,15.2 2006.162.08:05:13.80/ifatt/23,28,28,28 2006.162.08:05:14.08/fmout-gps/S +4.50E-07 2006.162.08:05:14.12:!2006.162.08:06:10 2006.162.08:06:10.01:data_valid=off 2006.162.08:06:10.02:postob 2006.162.08:06:10.24/cable/+6.5371E-03 2006.162.08:06:10.25/wx/17.85,1007.1,100 2006.162.08:06:11.07/fmout-gps/S +4.50E-07 2006.162.08:06:11.08:scan_name=162-0807,k06162,60 2006.162.08:06:11.08:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.162.08:06:11.13#flagr#flagr/antenna,new-source 2006.162.08:06:12.13:checkk5 2006.162.08:06:12.63/chk_autoobs//k5ts1/ autoobs is running! 2006.162.08:06:13.02/chk_autoobs//k5ts2/ autoobs is running! 2006.162.08:06:13.44/chk_autoobs//k5ts3/ autoobs is running! 2006.162.08:06:13.87/chk_autoobs//k5ts4/ autoobs is running! 2006.162.08:06:14.52/chk_obsdata//k5ts1/T1620805??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:06:14.93/chk_obsdata//k5ts2/T1620805??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:06:15.34/chk_obsdata//k5ts3/T1620805??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:06:15.81/chk_obsdata//k5ts4/T1620805??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:06:16.72/k5log//k5ts1_log_newline 2006.162.08:06:17.51/k5log//k5ts2_log_newline 2006.162.08:06:18.26/k5log//k5ts3_log_newline 2006.162.08:06:19.20/k5log//k5ts4_log_newline 2006.162.08:06:19.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.08:06:19.22:4f8m12a=2 2006.162.08:06:19.22$4f8m12a/echo=on 2006.162.08:06:19.22$4f8m12a/pcalon 2006.162.08:06:19.22$pcalon/"no phase cal control is implemented here 2006.162.08:06:19.22$4f8m12a/"tpicd=stop 2006.162.08:06:19.22$4f8m12a/vc4f8 2006.162.08:06:19.22$vc4f8/valo=1,532.99 2006.162.08:06:19.23#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.162.08:06:19.23#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.162.08:06:19.23#ibcon#ireg 17 cls_cnt 0 2006.162.08:06:19.23#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:06:19.23#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:06:19.23#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:06:19.23#ibcon#enter wrdev, iclass 10, count 0 2006.162.08:06:19.23#ibcon#first serial, iclass 10, count 0 2006.162.08:06:19.23#ibcon#enter sib2, iclass 10, count 0 2006.162.08:06:19.23#ibcon#flushed, iclass 10, count 0 2006.162.08:06:19.23#ibcon#about to write, iclass 10, count 0 2006.162.08:06:19.23#ibcon#wrote, iclass 10, count 0 2006.162.08:06:19.23#ibcon#about to read 3, iclass 10, count 0 2006.162.08:06:19.27#ibcon#read 3, iclass 10, count 0 2006.162.08:06:19.27#ibcon#about to read 4, iclass 10, count 0 2006.162.08:06:19.27#ibcon#read 4, iclass 10, count 0 2006.162.08:06:19.27#ibcon#about to read 5, iclass 10, count 0 2006.162.08:06:19.27#ibcon#read 5, iclass 10, count 0 2006.162.08:06:19.27#ibcon#about to read 6, iclass 10, count 0 2006.162.08:06:19.27#ibcon#read 6, iclass 10, count 0 2006.162.08:06:19.27#ibcon#end of sib2, iclass 10, count 0 2006.162.08:06:19.27#ibcon#*mode == 0, iclass 10, count 0 2006.162.08:06:19.27#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.162.08:06:19.27#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.08:06:19.27#ibcon#*before write, iclass 10, count 0 2006.162.08:06:19.27#ibcon#enter sib2, iclass 10, count 0 2006.162.08:06:19.27#ibcon#flushed, iclass 10, count 0 2006.162.08:06:19.27#ibcon#about to write, iclass 10, count 0 2006.162.08:06:19.27#ibcon#wrote, iclass 10, count 0 2006.162.08:06:19.27#ibcon#about to read 3, iclass 10, count 0 2006.162.08:06:19.32#ibcon#read 3, iclass 10, count 0 2006.162.08:06:19.32#ibcon#about to read 4, iclass 10, count 0 2006.162.08:06:19.32#ibcon#read 4, iclass 10, count 0 2006.162.08:06:19.32#ibcon#about to read 5, iclass 10, count 0 2006.162.08:06:19.32#ibcon#read 5, iclass 10, count 0 2006.162.08:06:19.32#ibcon#about to read 6, iclass 10, count 0 2006.162.08:06:19.32#ibcon#read 6, iclass 10, count 0 2006.162.08:06:19.32#ibcon#end of sib2, iclass 10, count 0 2006.162.08:06:19.32#ibcon#*after write, iclass 10, count 0 2006.162.08:06:19.32#ibcon#*before return 0, iclass 10, count 0 2006.162.08:06:19.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:06:19.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:06:19.32#ibcon#about to clear, iclass 10 cls_cnt 0 2006.162.08:06:19.32#ibcon#cleared, iclass 10 cls_cnt 0 2006.162.08:06:19.32$vc4f8/va=1,8 2006.162.08:06:19.32#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.162.08:06:19.32#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.162.08:06:19.32#ibcon#ireg 11 cls_cnt 2 2006.162.08:06:19.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:06:19.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:06:19.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:06:19.32#ibcon#enter wrdev, iclass 12, count 2 2006.162.08:06:19.32#ibcon#first serial, iclass 12, count 2 2006.162.08:06:19.32#ibcon#enter sib2, iclass 12, count 2 2006.162.08:06:19.32#ibcon#flushed, iclass 12, count 2 2006.162.08:06:19.32#ibcon#about to write, iclass 12, count 2 2006.162.08:06:19.32#ibcon#wrote, iclass 12, count 2 2006.162.08:06:19.32#ibcon#about to read 3, iclass 12, count 2 2006.162.08:06:19.35#ibcon#read 3, iclass 12, count 2 2006.162.08:06:19.35#ibcon#about to read 4, iclass 12, count 2 2006.162.08:06:19.35#ibcon#read 4, iclass 12, count 2 2006.162.08:06:19.35#ibcon#about to read 5, iclass 12, count 2 2006.162.08:06:19.35#ibcon#read 5, iclass 12, count 2 2006.162.08:06:19.35#ibcon#about to read 6, iclass 12, count 2 2006.162.08:06:19.35#ibcon#read 6, iclass 12, count 2 2006.162.08:06:19.35#ibcon#end of sib2, iclass 12, count 2 2006.162.08:06:19.35#ibcon#*mode == 0, iclass 12, count 2 2006.162.08:06:19.35#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.162.08:06:19.35#ibcon#[25=AT01-08\r\n] 2006.162.08:06:19.35#ibcon#*before write, iclass 12, count 2 2006.162.08:06:19.35#ibcon#enter sib2, iclass 12, count 2 2006.162.08:06:19.35#ibcon#flushed, iclass 12, count 2 2006.162.08:06:19.35#ibcon#about to write, iclass 12, count 2 2006.162.08:06:19.35#ibcon#wrote, iclass 12, count 2 2006.162.08:06:19.35#ibcon#about to read 3, iclass 12, count 2 2006.162.08:06:19.38#ibcon#read 3, iclass 12, count 2 2006.162.08:06:19.38#ibcon#about to read 4, iclass 12, count 2 2006.162.08:06:19.38#ibcon#read 4, iclass 12, count 2 2006.162.08:06:19.38#ibcon#about to read 5, iclass 12, count 2 2006.162.08:06:19.38#ibcon#read 5, iclass 12, count 2 2006.162.08:06:19.38#ibcon#about to read 6, iclass 12, count 2 2006.162.08:06:19.38#ibcon#read 6, iclass 12, count 2 2006.162.08:06:19.38#ibcon#end of sib2, iclass 12, count 2 2006.162.08:06:19.38#ibcon#*after write, iclass 12, count 2 2006.162.08:06:19.38#ibcon#*before return 0, iclass 12, count 2 2006.162.08:06:19.38#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:06:19.38#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:06:19.38#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.162.08:06:19.38#ibcon#ireg 7 cls_cnt 0 2006.162.08:06:19.38#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:06:19.50#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:06:19.50#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:06:19.50#ibcon#enter wrdev, iclass 12, count 0 2006.162.08:06:19.50#ibcon#first serial, iclass 12, count 0 2006.162.08:06:19.50#ibcon#enter sib2, iclass 12, count 0 2006.162.08:06:19.50#ibcon#flushed, iclass 12, count 0 2006.162.08:06:19.50#ibcon#about to write, iclass 12, count 0 2006.162.08:06:19.50#ibcon#wrote, iclass 12, count 0 2006.162.08:06:19.50#ibcon#about to read 3, iclass 12, count 0 2006.162.08:06:19.52#ibcon#read 3, iclass 12, count 0 2006.162.08:06:19.52#ibcon#about to read 4, iclass 12, count 0 2006.162.08:06:19.52#ibcon#read 4, iclass 12, count 0 2006.162.08:06:19.52#ibcon#about to read 5, iclass 12, count 0 2006.162.08:06:19.52#ibcon#read 5, iclass 12, count 0 2006.162.08:06:19.52#ibcon#about to read 6, iclass 12, count 0 2006.162.08:06:19.52#ibcon#read 6, iclass 12, count 0 2006.162.08:06:19.52#ibcon#end of sib2, iclass 12, count 0 2006.162.08:06:19.52#ibcon#*mode == 0, iclass 12, count 0 2006.162.08:06:19.52#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.162.08:06:19.52#ibcon#[25=USB\r\n] 2006.162.08:06:19.52#ibcon#*before write, iclass 12, count 0 2006.162.08:06:19.52#ibcon#enter sib2, iclass 12, count 0 2006.162.08:06:19.52#ibcon#flushed, iclass 12, count 0 2006.162.08:06:19.52#ibcon#about to write, iclass 12, count 0 2006.162.08:06:19.52#ibcon#wrote, iclass 12, count 0 2006.162.08:06:19.52#ibcon#about to read 3, iclass 12, count 0 2006.162.08:06:19.55#ibcon#read 3, iclass 12, count 0 2006.162.08:06:19.55#ibcon#about to read 4, iclass 12, count 0 2006.162.08:06:19.55#ibcon#read 4, iclass 12, count 0 2006.162.08:06:19.55#ibcon#about to read 5, iclass 12, count 0 2006.162.08:06:19.55#ibcon#read 5, iclass 12, count 0 2006.162.08:06:19.55#ibcon#about to read 6, iclass 12, count 0 2006.162.08:06:19.55#ibcon#read 6, iclass 12, count 0 2006.162.08:06:19.55#ibcon#end of sib2, iclass 12, count 0 2006.162.08:06:19.55#ibcon#*after write, iclass 12, count 0 2006.162.08:06:19.55#ibcon#*before return 0, iclass 12, count 0 2006.162.08:06:19.55#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:06:19.55#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:06:19.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.162.08:06:19.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.162.08:06:19.55$vc4f8/valo=2,572.99 2006.162.08:06:19.55#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.162.08:06:19.55#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.162.08:06:19.55#ibcon#ireg 17 cls_cnt 0 2006.162.08:06:19.55#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:06:19.55#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:06:19.55#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:06:19.55#ibcon#enter wrdev, iclass 14, count 0 2006.162.08:06:19.55#ibcon#first serial, iclass 14, count 0 2006.162.08:06:19.55#ibcon#enter sib2, iclass 14, count 0 2006.162.08:06:19.55#ibcon#flushed, iclass 14, count 0 2006.162.08:06:19.55#ibcon#about to write, iclass 14, count 0 2006.162.08:06:19.55#ibcon#wrote, iclass 14, count 0 2006.162.08:06:19.55#ibcon#about to read 3, iclass 14, count 0 2006.162.08:06:19.57#ibcon#read 3, iclass 14, count 0 2006.162.08:06:19.57#ibcon#about to read 4, iclass 14, count 0 2006.162.08:06:19.57#ibcon#read 4, iclass 14, count 0 2006.162.08:06:19.57#ibcon#about to read 5, iclass 14, count 0 2006.162.08:06:19.57#ibcon#read 5, iclass 14, count 0 2006.162.08:06:19.57#ibcon#about to read 6, iclass 14, count 0 2006.162.08:06:19.57#ibcon#read 6, iclass 14, count 0 2006.162.08:06:19.57#ibcon#end of sib2, iclass 14, count 0 2006.162.08:06:19.57#ibcon#*mode == 0, iclass 14, count 0 2006.162.08:06:19.57#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.08:06:19.57#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.08:06:19.57#ibcon#*before write, iclass 14, count 0 2006.162.08:06:19.57#ibcon#enter sib2, iclass 14, count 0 2006.162.08:06:19.57#ibcon#flushed, iclass 14, count 0 2006.162.08:06:19.57#ibcon#about to write, iclass 14, count 0 2006.162.08:06:19.57#ibcon#wrote, iclass 14, count 0 2006.162.08:06:19.57#ibcon#about to read 3, iclass 14, count 0 2006.162.08:06:19.61#ibcon#read 3, iclass 14, count 0 2006.162.08:06:19.61#ibcon#about to read 4, iclass 14, count 0 2006.162.08:06:19.61#ibcon#read 4, iclass 14, count 0 2006.162.08:06:19.61#ibcon#about to read 5, iclass 14, count 0 2006.162.08:06:19.61#ibcon#read 5, iclass 14, count 0 2006.162.08:06:19.61#ibcon#about to read 6, iclass 14, count 0 2006.162.08:06:19.61#ibcon#read 6, iclass 14, count 0 2006.162.08:06:19.61#ibcon#end of sib2, iclass 14, count 0 2006.162.08:06:19.61#ibcon#*after write, iclass 14, count 0 2006.162.08:06:19.61#ibcon#*before return 0, iclass 14, count 0 2006.162.08:06:19.61#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:06:19.61#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:06:19.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.08:06:19.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.08:06:19.61$vc4f8/va=2,7 2006.162.08:06:19.61#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.162.08:06:19.61#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.162.08:06:19.61#ibcon#ireg 11 cls_cnt 2 2006.162.08:06:19.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:06:19.68#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:06:19.68#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:06:19.68#ibcon#enter wrdev, iclass 16, count 2 2006.162.08:06:19.68#ibcon#first serial, iclass 16, count 2 2006.162.08:06:19.68#ibcon#enter sib2, iclass 16, count 2 2006.162.08:06:19.68#ibcon#flushed, iclass 16, count 2 2006.162.08:06:19.68#ibcon#about to write, iclass 16, count 2 2006.162.08:06:19.68#ibcon#wrote, iclass 16, count 2 2006.162.08:06:19.68#ibcon#about to read 3, iclass 16, count 2 2006.162.08:06:19.69#ibcon#read 3, iclass 16, count 2 2006.162.08:06:19.69#ibcon#about to read 4, iclass 16, count 2 2006.162.08:06:19.69#ibcon#read 4, iclass 16, count 2 2006.162.08:06:19.69#ibcon#about to read 5, iclass 16, count 2 2006.162.08:06:19.69#ibcon#read 5, iclass 16, count 2 2006.162.08:06:19.69#ibcon#about to read 6, iclass 16, count 2 2006.162.08:06:19.69#ibcon#read 6, iclass 16, count 2 2006.162.08:06:19.69#ibcon#end of sib2, iclass 16, count 2 2006.162.08:06:19.69#ibcon#*mode == 0, iclass 16, count 2 2006.162.08:06:19.69#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.162.08:06:19.69#ibcon#[25=AT02-07\r\n] 2006.162.08:06:19.69#ibcon#*before write, iclass 16, count 2 2006.162.08:06:19.69#ibcon#enter sib2, iclass 16, count 2 2006.162.08:06:19.69#ibcon#flushed, iclass 16, count 2 2006.162.08:06:19.69#ibcon#about to write, iclass 16, count 2 2006.162.08:06:19.69#ibcon#wrote, iclass 16, count 2 2006.162.08:06:19.69#ibcon#about to read 3, iclass 16, count 2 2006.162.08:06:19.72#ibcon#read 3, iclass 16, count 2 2006.162.08:06:19.72#ibcon#about to read 4, iclass 16, count 2 2006.162.08:06:19.72#ibcon#read 4, iclass 16, count 2 2006.162.08:06:19.72#ibcon#about to read 5, iclass 16, count 2 2006.162.08:06:19.72#ibcon#read 5, iclass 16, count 2 2006.162.08:06:19.72#ibcon#about to read 6, iclass 16, count 2 2006.162.08:06:19.72#ibcon#read 6, iclass 16, count 2 2006.162.08:06:19.72#ibcon#end of sib2, iclass 16, count 2 2006.162.08:06:19.72#ibcon#*after write, iclass 16, count 2 2006.162.08:06:19.72#ibcon#*before return 0, iclass 16, count 2 2006.162.08:06:19.72#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:06:19.72#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:06:19.72#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.162.08:06:19.72#ibcon#ireg 7 cls_cnt 0 2006.162.08:06:19.72#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:06:19.84#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:06:19.84#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:06:19.84#ibcon#enter wrdev, iclass 16, count 0 2006.162.08:06:19.84#ibcon#first serial, iclass 16, count 0 2006.162.08:06:19.84#ibcon#enter sib2, iclass 16, count 0 2006.162.08:06:19.84#ibcon#flushed, iclass 16, count 0 2006.162.08:06:19.84#ibcon#about to write, iclass 16, count 0 2006.162.08:06:19.84#ibcon#wrote, iclass 16, count 0 2006.162.08:06:19.84#ibcon#about to read 3, iclass 16, count 0 2006.162.08:06:19.86#ibcon#read 3, iclass 16, count 0 2006.162.08:06:19.86#ibcon#about to read 4, iclass 16, count 0 2006.162.08:06:19.86#ibcon#read 4, iclass 16, count 0 2006.162.08:06:19.86#ibcon#about to read 5, iclass 16, count 0 2006.162.08:06:19.86#ibcon#read 5, iclass 16, count 0 2006.162.08:06:19.86#ibcon#about to read 6, iclass 16, count 0 2006.162.08:06:19.86#ibcon#read 6, iclass 16, count 0 2006.162.08:06:19.86#ibcon#end of sib2, iclass 16, count 0 2006.162.08:06:19.86#ibcon#*mode == 0, iclass 16, count 0 2006.162.08:06:19.86#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.162.08:06:19.86#ibcon#[25=USB\r\n] 2006.162.08:06:19.86#ibcon#*before write, iclass 16, count 0 2006.162.08:06:19.86#ibcon#enter sib2, iclass 16, count 0 2006.162.08:06:19.86#ibcon#flushed, iclass 16, count 0 2006.162.08:06:19.86#ibcon#about to write, iclass 16, count 0 2006.162.08:06:19.86#ibcon#wrote, iclass 16, count 0 2006.162.08:06:19.86#ibcon#about to read 3, iclass 16, count 0 2006.162.08:06:19.89#ibcon#read 3, iclass 16, count 0 2006.162.08:06:19.89#ibcon#about to read 4, iclass 16, count 0 2006.162.08:06:19.89#ibcon#read 4, iclass 16, count 0 2006.162.08:06:19.89#ibcon#about to read 5, iclass 16, count 0 2006.162.08:06:19.89#ibcon#read 5, iclass 16, count 0 2006.162.08:06:19.89#ibcon#about to read 6, iclass 16, count 0 2006.162.08:06:19.89#ibcon#read 6, iclass 16, count 0 2006.162.08:06:19.89#ibcon#end of sib2, iclass 16, count 0 2006.162.08:06:19.89#ibcon#*after write, iclass 16, count 0 2006.162.08:06:19.89#ibcon#*before return 0, iclass 16, count 0 2006.162.08:06:19.89#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:06:19.89#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:06:19.89#ibcon#about to clear, iclass 16 cls_cnt 0 2006.162.08:06:19.89#ibcon#cleared, iclass 16 cls_cnt 0 2006.162.08:06:19.89$vc4f8/valo=3,672.99 2006.162.08:06:19.89#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.162.08:06:19.89#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.162.08:06:19.89#ibcon#ireg 17 cls_cnt 0 2006.162.08:06:19.89#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:06:19.89#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:06:19.89#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:06:19.89#ibcon#enter wrdev, iclass 18, count 0 2006.162.08:06:19.89#ibcon#first serial, iclass 18, count 0 2006.162.08:06:19.89#ibcon#enter sib2, iclass 18, count 0 2006.162.08:06:19.89#ibcon#flushed, iclass 18, count 0 2006.162.08:06:19.89#ibcon#about to write, iclass 18, count 0 2006.162.08:06:19.89#ibcon#wrote, iclass 18, count 0 2006.162.08:06:19.89#ibcon#about to read 3, iclass 18, count 0 2006.162.08:06:19.91#ibcon#read 3, iclass 18, count 0 2006.162.08:06:19.91#ibcon#about to read 4, iclass 18, count 0 2006.162.08:06:19.91#ibcon#read 4, iclass 18, count 0 2006.162.08:06:19.91#ibcon#about to read 5, iclass 18, count 0 2006.162.08:06:19.91#ibcon#read 5, iclass 18, count 0 2006.162.08:06:19.91#ibcon#about to read 6, iclass 18, count 0 2006.162.08:06:19.91#ibcon#read 6, iclass 18, count 0 2006.162.08:06:19.91#ibcon#end of sib2, iclass 18, count 0 2006.162.08:06:19.91#ibcon#*mode == 0, iclass 18, count 0 2006.162.08:06:19.91#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.162.08:06:19.91#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.08:06:19.91#ibcon#*before write, iclass 18, count 0 2006.162.08:06:19.91#ibcon#enter sib2, iclass 18, count 0 2006.162.08:06:19.91#ibcon#flushed, iclass 18, count 0 2006.162.08:06:19.91#ibcon#about to write, iclass 18, count 0 2006.162.08:06:19.91#ibcon#wrote, iclass 18, count 0 2006.162.08:06:19.91#ibcon#about to read 3, iclass 18, count 0 2006.162.08:06:19.95#ibcon#read 3, iclass 18, count 0 2006.162.08:06:19.95#ibcon#about to read 4, iclass 18, count 0 2006.162.08:06:19.95#ibcon#read 4, iclass 18, count 0 2006.162.08:06:19.95#ibcon#about to read 5, iclass 18, count 0 2006.162.08:06:19.95#ibcon#read 5, iclass 18, count 0 2006.162.08:06:19.95#ibcon#about to read 6, iclass 18, count 0 2006.162.08:06:19.95#ibcon#read 6, iclass 18, count 0 2006.162.08:06:19.95#ibcon#end of sib2, iclass 18, count 0 2006.162.08:06:19.95#ibcon#*after write, iclass 18, count 0 2006.162.08:06:19.95#ibcon#*before return 0, iclass 18, count 0 2006.162.08:06:19.95#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:06:19.95#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:06:19.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.162.08:06:19.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.162.08:06:19.95$vc4f8/va=3,6 2006.162.08:06:19.95#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.162.08:06:19.95#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.162.08:06:19.95#ibcon#ireg 11 cls_cnt 2 2006.162.08:06:19.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:06:20.02#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:06:20.02#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:06:20.02#ibcon#enter wrdev, iclass 20, count 2 2006.162.08:06:20.02#ibcon#first serial, iclass 20, count 2 2006.162.08:06:20.02#ibcon#enter sib2, iclass 20, count 2 2006.162.08:06:20.02#ibcon#flushed, iclass 20, count 2 2006.162.08:06:20.02#ibcon#about to write, iclass 20, count 2 2006.162.08:06:20.02#ibcon#wrote, iclass 20, count 2 2006.162.08:06:20.02#ibcon#about to read 3, iclass 20, count 2 2006.162.08:06:20.03#ibcon#read 3, iclass 20, count 2 2006.162.08:06:20.03#ibcon#about to read 4, iclass 20, count 2 2006.162.08:06:20.03#ibcon#read 4, iclass 20, count 2 2006.162.08:06:20.03#ibcon#about to read 5, iclass 20, count 2 2006.162.08:06:20.03#ibcon#read 5, iclass 20, count 2 2006.162.08:06:20.03#ibcon#about to read 6, iclass 20, count 2 2006.162.08:06:20.03#ibcon#read 6, iclass 20, count 2 2006.162.08:06:20.03#ibcon#end of sib2, iclass 20, count 2 2006.162.08:06:20.03#ibcon#*mode == 0, iclass 20, count 2 2006.162.08:06:20.03#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.162.08:06:20.03#ibcon#[25=AT03-06\r\n] 2006.162.08:06:20.03#ibcon#*before write, iclass 20, count 2 2006.162.08:06:20.03#ibcon#enter sib2, iclass 20, count 2 2006.162.08:06:20.03#ibcon#flushed, iclass 20, count 2 2006.162.08:06:20.03#ibcon#about to write, iclass 20, count 2 2006.162.08:06:20.03#ibcon#wrote, iclass 20, count 2 2006.162.08:06:20.03#ibcon#about to read 3, iclass 20, count 2 2006.162.08:06:20.06#ibcon#read 3, iclass 20, count 2 2006.162.08:06:20.06#ibcon#about to read 4, iclass 20, count 2 2006.162.08:06:20.06#ibcon#read 4, iclass 20, count 2 2006.162.08:06:20.06#ibcon#about to read 5, iclass 20, count 2 2006.162.08:06:20.06#ibcon#read 5, iclass 20, count 2 2006.162.08:06:20.06#ibcon#about to read 6, iclass 20, count 2 2006.162.08:06:20.06#ibcon#read 6, iclass 20, count 2 2006.162.08:06:20.06#ibcon#end of sib2, iclass 20, count 2 2006.162.08:06:20.06#ibcon#*after write, iclass 20, count 2 2006.162.08:06:20.06#ibcon#*before return 0, iclass 20, count 2 2006.162.08:06:20.06#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:06:20.06#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:06:20.06#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.162.08:06:20.06#ibcon#ireg 7 cls_cnt 0 2006.162.08:06:20.06#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:06:20.18#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:06:20.18#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:06:20.18#ibcon#enter wrdev, iclass 20, count 0 2006.162.08:06:20.18#ibcon#first serial, iclass 20, count 0 2006.162.08:06:20.18#ibcon#enter sib2, iclass 20, count 0 2006.162.08:06:20.18#ibcon#flushed, iclass 20, count 0 2006.162.08:06:20.18#ibcon#about to write, iclass 20, count 0 2006.162.08:06:20.18#ibcon#wrote, iclass 20, count 0 2006.162.08:06:20.18#ibcon#about to read 3, iclass 20, count 0 2006.162.08:06:20.20#ibcon#read 3, iclass 20, count 0 2006.162.08:06:20.20#ibcon#about to read 4, iclass 20, count 0 2006.162.08:06:20.20#ibcon#read 4, iclass 20, count 0 2006.162.08:06:20.20#ibcon#about to read 5, iclass 20, count 0 2006.162.08:06:20.20#ibcon#read 5, iclass 20, count 0 2006.162.08:06:20.20#ibcon#about to read 6, iclass 20, count 0 2006.162.08:06:20.20#ibcon#read 6, iclass 20, count 0 2006.162.08:06:20.20#ibcon#end of sib2, iclass 20, count 0 2006.162.08:06:20.20#ibcon#*mode == 0, iclass 20, count 0 2006.162.08:06:20.20#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.08:06:20.20#ibcon#[25=USB\r\n] 2006.162.08:06:20.20#ibcon#*before write, iclass 20, count 0 2006.162.08:06:20.20#ibcon#enter sib2, iclass 20, count 0 2006.162.08:06:20.20#ibcon#flushed, iclass 20, count 0 2006.162.08:06:20.20#ibcon#about to write, iclass 20, count 0 2006.162.08:06:20.20#ibcon#wrote, iclass 20, count 0 2006.162.08:06:20.20#ibcon#about to read 3, iclass 20, count 0 2006.162.08:06:20.23#ibcon#read 3, iclass 20, count 0 2006.162.08:06:20.23#ibcon#about to read 4, iclass 20, count 0 2006.162.08:06:20.23#ibcon#read 4, iclass 20, count 0 2006.162.08:06:20.23#ibcon#about to read 5, iclass 20, count 0 2006.162.08:06:20.23#ibcon#read 5, iclass 20, count 0 2006.162.08:06:20.23#ibcon#about to read 6, iclass 20, count 0 2006.162.08:06:20.23#ibcon#read 6, iclass 20, count 0 2006.162.08:06:20.23#ibcon#end of sib2, iclass 20, count 0 2006.162.08:06:20.23#ibcon#*after write, iclass 20, count 0 2006.162.08:06:20.23#ibcon#*before return 0, iclass 20, count 0 2006.162.08:06:20.23#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:06:20.23#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:06:20.23#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.08:06:20.23#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.08:06:20.23$vc4f8/valo=4,832.99 2006.162.08:06:20.23#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.162.08:06:20.23#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.162.08:06:20.23#ibcon#ireg 17 cls_cnt 0 2006.162.08:06:20.23#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:06:20.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:06:20.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:06:20.23#ibcon#enter wrdev, iclass 22, count 0 2006.162.08:06:20.23#ibcon#first serial, iclass 22, count 0 2006.162.08:06:20.23#ibcon#enter sib2, iclass 22, count 0 2006.162.08:06:20.23#ibcon#flushed, iclass 22, count 0 2006.162.08:06:20.23#ibcon#about to write, iclass 22, count 0 2006.162.08:06:20.23#ibcon#wrote, iclass 22, count 0 2006.162.08:06:20.23#ibcon#about to read 3, iclass 22, count 0 2006.162.08:06:20.25#ibcon#read 3, iclass 22, count 0 2006.162.08:06:20.25#ibcon#about to read 4, iclass 22, count 0 2006.162.08:06:20.25#ibcon#read 4, iclass 22, count 0 2006.162.08:06:20.25#ibcon#about to read 5, iclass 22, count 0 2006.162.08:06:20.25#ibcon#read 5, iclass 22, count 0 2006.162.08:06:20.25#ibcon#about to read 6, iclass 22, count 0 2006.162.08:06:20.25#ibcon#read 6, iclass 22, count 0 2006.162.08:06:20.25#ibcon#end of sib2, iclass 22, count 0 2006.162.08:06:20.25#ibcon#*mode == 0, iclass 22, count 0 2006.162.08:06:20.25#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.08:06:20.25#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.08:06:20.25#ibcon#*before write, iclass 22, count 0 2006.162.08:06:20.25#ibcon#enter sib2, iclass 22, count 0 2006.162.08:06:20.25#ibcon#flushed, iclass 22, count 0 2006.162.08:06:20.25#ibcon#about to write, iclass 22, count 0 2006.162.08:06:20.25#ibcon#wrote, iclass 22, count 0 2006.162.08:06:20.25#ibcon#about to read 3, iclass 22, count 0 2006.162.08:06:20.29#ibcon#read 3, iclass 22, count 0 2006.162.08:06:20.29#ibcon#about to read 4, iclass 22, count 0 2006.162.08:06:20.29#ibcon#read 4, iclass 22, count 0 2006.162.08:06:20.29#ibcon#about to read 5, iclass 22, count 0 2006.162.08:06:20.29#ibcon#read 5, iclass 22, count 0 2006.162.08:06:20.29#ibcon#about to read 6, iclass 22, count 0 2006.162.08:06:20.29#ibcon#read 6, iclass 22, count 0 2006.162.08:06:20.29#ibcon#end of sib2, iclass 22, count 0 2006.162.08:06:20.29#ibcon#*after write, iclass 22, count 0 2006.162.08:06:20.29#ibcon#*before return 0, iclass 22, count 0 2006.162.08:06:20.29#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:06:20.29#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:06:20.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.08:06:20.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.08:06:20.29$vc4f8/va=4,7 2006.162.08:06:20.29#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.162.08:06:20.29#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.162.08:06:20.29#ibcon#ireg 11 cls_cnt 2 2006.162.08:06:20.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:06:20.35#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:06:20.35#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:06:20.35#ibcon#enter wrdev, iclass 24, count 2 2006.162.08:06:20.35#ibcon#first serial, iclass 24, count 2 2006.162.08:06:20.35#ibcon#enter sib2, iclass 24, count 2 2006.162.08:06:20.35#ibcon#flushed, iclass 24, count 2 2006.162.08:06:20.35#ibcon#about to write, iclass 24, count 2 2006.162.08:06:20.35#ibcon#wrote, iclass 24, count 2 2006.162.08:06:20.35#ibcon#about to read 3, iclass 24, count 2 2006.162.08:06:20.37#ibcon#read 3, iclass 24, count 2 2006.162.08:06:20.37#ibcon#about to read 4, iclass 24, count 2 2006.162.08:06:20.37#ibcon#read 4, iclass 24, count 2 2006.162.08:06:20.37#ibcon#about to read 5, iclass 24, count 2 2006.162.08:06:20.37#ibcon#read 5, iclass 24, count 2 2006.162.08:06:20.37#ibcon#about to read 6, iclass 24, count 2 2006.162.08:06:20.37#ibcon#read 6, iclass 24, count 2 2006.162.08:06:20.37#ibcon#end of sib2, iclass 24, count 2 2006.162.08:06:20.37#ibcon#*mode == 0, iclass 24, count 2 2006.162.08:06:20.37#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.162.08:06:20.37#ibcon#[25=AT04-07\r\n] 2006.162.08:06:20.37#ibcon#*before write, iclass 24, count 2 2006.162.08:06:20.37#ibcon#enter sib2, iclass 24, count 2 2006.162.08:06:20.37#ibcon#flushed, iclass 24, count 2 2006.162.08:06:20.37#ibcon#about to write, iclass 24, count 2 2006.162.08:06:20.37#ibcon#wrote, iclass 24, count 2 2006.162.08:06:20.37#ibcon#about to read 3, iclass 24, count 2 2006.162.08:06:20.40#ibcon#read 3, iclass 24, count 2 2006.162.08:06:20.40#ibcon#about to read 4, iclass 24, count 2 2006.162.08:06:20.40#ibcon#read 4, iclass 24, count 2 2006.162.08:06:20.40#ibcon#about to read 5, iclass 24, count 2 2006.162.08:06:20.40#ibcon#read 5, iclass 24, count 2 2006.162.08:06:20.40#ibcon#about to read 6, iclass 24, count 2 2006.162.08:06:20.40#ibcon#read 6, iclass 24, count 2 2006.162.08:06:20.40#ibcon#end of sib2, iclass 24, count 2 2006.162.08:06:20.40#ibcon#*after write, iclass 24, count 2 2006.162.08:06:20.40#ibcon#*before return 0, iclass 24, count 2 2006.162.08:06:20.40#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:06:20.40#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:06:20.40#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.162.08:06:20.40#ibcon#ireg 7 cls_cnt 0 2006.162.08:06:20.40#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:06:20.52#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:06:20.52#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:06:20.52#ibcon#enter wrdev, iclass 24, count 0 2006.162.08:06:20.52#ibcon#first serial, iclass 24, count 0 2006.162.08:06:20.52#ibcon#enter sib2, iclass 24, count 0 2006.162.08:06:20.52#ibcon#flushed, iclass 24, count 0 2006.162.08:06:20.52#ibcon#about to write, iclass 24, count 0 2006.162.08:06:20.52#ibcon#wrote, iclass 24, count 0 2006.162.08:06:20.52#ibcon#about to read 3, iclass 24, count 0 2006.162.08:06:20.54#ibcon#read 3, iclass 24, count 0 2006.162.08:06:20.54#ibcon#about to read 4, iclass 24, count 0 2006.162.08:06:20.54#ibcon#read 4, iclass 24, count 0 2006.162.08:06:20.54#ibcon#about to read 5, iclass 24, count 0 2006.162.08:06:20.54#ibcon#read 5, iclass 24, count 0 2006.162.08:06:20.54#ibcon#about to read 6, iclass 24, count 0 2006.162.08:06:20.54#ibcon#read 6, iclass 24, count 0 2006.162.08:06:20.54#ibcon#end of sib2, iclass 24, count 0 2006.162.08:06:20.54#ibcon#*mode == 0, iclass 24, count 0 2006.162.08:06:20.54#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.08:06:20.54#ibcon#[25=USB\r\n] 2006.162.08:06:20.54#ibcon#*before write, iclass 24, count 0 2006.162.08:06:20.54#ibcon#enter sib2, iclass 24, count 0 2006.162.08:06:20.54#ibcon#flushed, iclass 24, count 0 2006.162.08:06:20.54#ibcon#about to write, iclass 24, count 0 2006.162.08:06:20.54#ibcon#wrote, iclass 24, count 0 2006.162.08:06:20.54#ibcon#about to read 3, iclass 24, count 0 2006.162.08:06:20.57#ibcon#read 3, iclass 24, count 0 2006.162.08:06:20.57#ibcon#about to read 4, iclass 24, count 0 2006.162.08:06:20.57#ibcon#read 4, iclass 24, count 0 2006.162.08:06:20.57#ibcon#about to read 5, iclass 24, count 0 2006.162.08:06:20.57#ibcon#read 5, iclass 24, count 0 2006.162.08:06:20.57#ibcon#about to read 6, iclass 24, count 0 2006.162.08:06:20.57#ibcon#read 6, iclass 24, count 0 2006.162.08:06:20.57#ibcon#end of sib2, iclass 24, count 0 2006.162.08:06:20.57#ibcon#*after write, iclass 24, count 0 2006.162.08:06:20.57#ibcon#*before return 0, iclass 24, count 0 2006.162.08:06:20.57#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:06:20.57#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:06:20.57#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.08:06:20.57#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.08:06:20.57$vc4f8/valo=5,652.99 2006.162.08:06:20.57#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.162.08:06:20.57#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.162.08:06:20.57#ibcon#ireg 17 cls_cnt 0 2006.162.08:06:20.57#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:06:20.57#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:06:20.57#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:06:20.57#ibcon#enter wrdev, iclass 26, count 0 2006.162.08:06:20.57#ibcon#first serial, iclass 26, count 0 2006.162.08:06:20.57#ibcon#enter sib2, iclass 26, count 0 2006.162.08:06:20.57#ibcon#flushed, iclass 26, count 0 2006.162.08:06:20.57#ibcon#about to write, iclass 26, count 0 2006.162.08:06:20.57#ibcon#wrote, iclass 26, count 0 2006.162.08:06:20.57#ibcon#about to read 3, iclass 26, count 0 2006.162.08:06:20.59#ibcon#read 3, iclass 26, count 0 2006.162.08:06:20.59#ibcon#about to read 4, iclass 26, count 0 2006.162.08:06:20.59#ibcon#read 4, iclass 26, count 0 2006.162.08:06:20.59#ibcon#about to read 5, iclass 26, count 0 2006.162.08:06:20.59#ibcon#read 5, iclass 26, count 0 2006.162.08:06:20.59#ibcon#about to read 6, iclass 26, count 0 2006.162.08:06:20.59#ibcon#read 6, iclass 26, count 0 2006.162.08:06:20.59#ibcon#end of sib2, iclass 26, count 0 2006.162.08:06:20.59#ibcon#*mode == 0, iclass 26, count 0 2006.162.08:06:20.59#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.162.08:06:20.59#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.08:06:20.59#ibcon#*before write, iclass 26, count 0 2006.162.08:06:20.59#ibcon#enter sib2, iclass 26, count 0 2006.162.08:06:20.59#ibcon#flushed, iclass 26, count 0 2006.162.08:06:20.59#ibcon#about to write, iclass 26, count 0 2006.162.08:06:20.59#ibcon#wrote, iclass 26, count 0 2006.162.08:06:20.59#ibcon#about to read 3, iclass 26, count 0 2006.162.08:06:20.63#ibcon#read 3, iclass 26, count 0 2006.162.08:06:20.63#ibcon#about to read 4, iclass 26, count 0 2006.162.08:06:20.63#ibcon#read 4, iclass 26, count 0 2006.162.08:06:20.63#ibcon#about to read 5, iclass 26, count 0 2006.162.08:06:20.63#ibcon#read 5, iclass 26, count 0 2006.162.08:06:20.63#ibcon#about to read 6, iclass 26, count 0 2006.162.08:06:20.63#ibcon#read 6, iclass 26, count 0 2006.162.08:06:20.63#ibcon#end of sib2, iclass 26, count 0 2006.162.08:06:20.63#ibcon#*after write, iclass 26, count 0 2006.162.08:06:20.63#ibcon#*before return 0, iclass 26, count 0 2006.162.08:06:20.63#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:06:20.63#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:06:20.63#ibcon#about to clear, iclass 26 cls_cnt 0 2006.162.08:06:20.63#ibcon#cleared, iclass 26 cls_cnt 0 2006.162.08:06:20.63$vc4f8/va=5,7 2006.162.08:06:20.63#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.162.08:06:20.63#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.162.08:06:20.63#ibcon#ireg 11 cls_cnt 2 2006.162.08:06:20.63#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:06:20.69#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:06:20.69#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:06:20.69#ibcon#enter wrdev, iclass 28, count 2 2006.162.08:06:20.69#ibcon#first serial, iclass 28, count 2 2006.162.08:06:20.69#ibcon#enter sib2, iclass 28, count 2 2006.162.08:06:20.69#ibcon#flushed, iclass 28, count 2 2006.162.08:06:20.69#ibcon#about to write, iclass 28, count 2 2006.162.08:06:20.69#ibcon#wrote, iclass 28, count 2 2006.162.08:06:20.69#ibcon#about to read 3, iclass 28, count 2 2006.162.08:06:20.72#ibcon#read 3, iclass 28, count 2 2006.162.08:06:20.72#ibcon#about to read 4, iclass 28, count 2 2006.162.08:06:20.72#ibcon#read 4, iclass 28, count 2 2006.162.08:06:20.72#ibcon#about to read 5, iclass 28, count 2 2006.162.08:06:20.72#ibcon#read 5, iclass 28, count 2 2006.162.08:06:20.72#ibcon#about to read 6, iclass 28, count 2 2006.162.08:06:20.72#ibcon#read 6, iclass 28, count 2 2006.162.08:06:20.72#ibcon#end of sib2, iclass 28, count 2 2006.162.08:06:20.72#ibcon#*mode == 0, iclass 28, count 2 2006.162.08:06:20.72#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.162.08:06:20.72#ibcon#[25=AT05-07\r\n] 2006.162.08:06:20.72#ibcon#*before write, iclass 28, count 2 2006.162.08:06:20.72#ibcon#enter sib2, iclass 28, count 2 2006.162.08:06:20.72#ibcon#flushed, iclass 28, count 2 2006.162.08:06:20.72#ibcon#about to write, iclass 28, count 2 2006.162.08:06:20.72#ibcon#wrote, iclass 28, count 2 2006.162.08:06:20.72#ibcon#about to read 3, iclass 28, count 2 2006.162.08:06:20.75#ibcon#read 3, iclass 28, count 2 2006.162.08:06:20.75#ibcon#about to read 4, iclass 28, count 2 2006.162.08:06:20.75#ibcon#read 4, iclass 28, count 2 2006.162.08:06:20.75#ibcon#about to read 5, iclass 28, count 2 2006.162.08:06:20.75#ibcon#read 5, iclass 28, count 2 2006.162.08:06:20.75#ibcon#about to read 6, iclass 28, count 2 2006.162.08:06:20.75#ibcon#read 6, iclass 28, count 2 2006.162.08:06:20.75#ibcon#end of sib2, iclass 28, count 2 2006.162.08:06:20.75#ibcon#*after write, iclass 28, count 2 2006.162.08:06:20.75#ibcon#*before return 0, iclass 28, count 2 2006.162.08:06:20.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:06:20.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:06:20.75#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.162.08:06:20.75#ibcon#ireg 7 cls_cnt 0 2006.162.08:06:20.75#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:06:20.87#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:06:20.87#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:06:20.87#ibcon#enter wrdev, iclass 28, count 0 2006.162.08:06:20.87#ibcon#first serial, iclass 28, count 0 2006.162.08:06:20.87#ibcon#enter sib2, iclass 28, count 0 2006.162.08:06:20.87#ibcon#flushed, iclass 28, count 0 2006.162.08:06:20.87#ibcon#about to write, iclass 28, count 0 2006.162.08:06:20.87#ibcon#wrote, iclass 28, count 0 2006.162.08:06:20.87#ibcon#about to read 3, iclass 28, count 0 2006.162.08:06:20.89#ibcon#read 3, iclass 28, count 0 2006.162.08:06:20.89#ibcon#about to read 4, iclass 28, count 0 2006.162.08:06:20.89#ibcon#read 4, iclass 28, count 0 2006.162.08:06:20.89#ibcon#about to read 5, iclass 28, count 0 2006.162.08:06:20.89#ibcon#read 5, iclass 28, count 0 2006.162.08:06:20.89#ibcon#about to read 6, iclass 28, count 0 2006.162.08:06:20.89#ibcon#read 6, iclass 28, count 0 2006.162.08:06:20.89#ibcon#end of sib2, iclass 28, count 0 2006.162.08:06:20.89#ibcon#*mode == 0, iclass 28, count 0 2006.162.08:06:20.89#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.162.08:06:20.89#ibcon#[25=USB\r\n] 2006.162.08:06:20.89#ibcon#*before write, iclass 28, count 0 2006.162.08:06:20.89#ibcon#enter sib2, iclass 28, count 0 2006.162.08:06:20.89#ibcon#flushed, iclass 28, count 0 2006.162.08:06:20.89#ibcon#about to write, iclass 28, count 0 2006.162.08:06:20.89#ibcon#wrote, iclass 28, count 0 2006.162.08:06:20.89#ibcon#about to read 3, iclass 28, count 0 2006.162.08:06:20.92#ibcon#read 3, iclass 28, count 0 2006.162.08:06:20.92#ibcon#about to read 4, iclass 28, count 0 2006.162.08:06:20.92#ibcon#read 4, iclass 28, count 0 2006.162.08:06:20.92#ibcon#about to read 5, iclass 28, count 0 2006.162.08:06:20.92#ibcon#read 5, iclass 28, count 0 2006.162.08:06:20.92#ibcon#about to read 6, iclass 28, count 0 2006.162.08:06:20.92#ibcon#read 6, iclass 28, count 0 2006.162.08:06:20.92#ibcon#end of sib2, iclass 28, count 0 2006.162.08:06:20.92#ibcon#*after write, iclass 28, count 0 2006.162.08:06:20.92#ibcon#*before return 0, iclass 28, count 0 2006.162.08:06:20.92#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:06:20.92#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:06:20.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.162.08:06:20.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.162.08:06:20.92$vc4f8/valo=6,772.99 2006.162.08:06:20.92#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.162.08:06:20.92#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.162.08:06:20.92#ibcon#ireg 17 cls_cnt 0 2006.162.08:06:20.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:06:20.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:06:20.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:06:20.92#ibcon#enter wrdev, iclass 30, count 0 2006.162.08:06:20.92#ibcon#first serial, iclass 30, count 0 2006.162.08:06:20.92#ibcon#enter sib2, iclass 30, count 0 2006.162.08:06:20.92#ibcon#flushed, iclass 30, count 0 2006.162.08:06:20.92#ibcon#about to write, iclass 30, count 0 2006.162.08:06:20.92#ibcon#wrote, iclass 30, count 0 2006.162.08:06:20.92#ibcon#about to read 3, iclass 30, count 0 2006.162.08:06:20.94#ibcon#read 3, iclass 30, count 0 2006.162.08:06:20.94#ibcon#about to read 4, iclass 30, count 0 2006.162.08:06:20.94#ibcon#read 4, iclass 30, count 0 2006.162.08:06:20.94#ibcon#about to read 5, iclass 30, count 0 2006.162.08:06:20.94#ibcon#read 5, iclass 30, count 0 2006.162.08:06:20.94#ibcon#about to read 6, iclass 30, count 0 2006.162.08:06:20.94#ibcon#read 6, iclass 30, count 0 2006.162.08:06:20.94#ibcon#end of sib2, iclass 30, count 0 2006.162.08:06:20.94#ibcon#*mode == 0, iclass 30, count 0 2006.162.08:06:20.94#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.162.08:06:20.94#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.08:06:20.94#ibcon#*before write, iclass 30, count 0 2006.162.08:06:20.94#ibcon#enter sib2, iclass 30, count 0 2006.162.08:06:20.94#ibcon#flushed, iclass 30, count 0 2006.162.08:06:20.94#ibcon#about to write, iclass 30, count 0 2006.162.08:06:20.94#ibcon#wrote, iclass 30, count 0 2006.162.08:06:20.94#ibcon#about to read 3, iclass 30, count 0 2006.162.08:06:20.98#ibcon#read 3, iclass 30, count 0 2006.162.08:06:20.98#ibcon#about to read 4, iclass 30, count 0 2006.162.08:06:20.98#ibcon#read 4, iclass 30, count 0 2006.162.08:06:20.98#ibcon#about to read 5, iclass 30, count 0 2006.162.08:06:20.98#ibcon#read 5, iclass 30, count 0 2006.162.08:06:20.98#ibcon#about to read 6, iclass 30, count 0 2006.162.08:06:20.98#ibcon#read 6, iclass 30, count 0 2006.162.08:06:20.98#ibcon#end of sib2, iclass 30, count 0 2006.162.08:06:20.98#ibcon#*after write, iclass 30, count 0 2006.162.08:06:20.98#ibcon#*before return 0, iclass 30, count 0 2006.162.08:06:20.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:06:20.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:06:20.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.162.08:06:20.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.162.08:06:20.98$vc4f8/va=6,6 2006.162.08:06:20.98#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.162.08:06:20.98#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.162.08:06:20.98#ibcon#ireg 11 cls_cnt 2 2006.162.08:06:20.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.162.08:06:21.04#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.162.08:06:21.04#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.162.08:06:21.04#ibcon#enter wrdev, iclass 32, count 2 2006.162.08:06:21.04#ibcon#first serial, iclass 32, count 2 2006.162.08:06:21.04#ibcon#enter sib2, iclass 32, count 2 2006.162.08:06:21.04#ibcon#flushed, iclass 32, count 2 2006.162.08:06:21.04#ibcon#about to write, iclass 32, count 2 2006.162.08:06:21.04#ibcon#wrote, iclass 32, count 2 2006.162.08:06:21.04#ibcon#about to read 3, iclass 32, count 2 2006.162.08:06:21.06#ibcon#read 3, iclass 32, count 2 2006.162.08:06:21.06#ibcon#about to read 4, iclass 32, count 2 2006.162.08:06:21.06#ibcon#read 4, iclass 32, count 2 2006.162.08:06:21.06#ibcon#about to read 5, iclass 32, count 2 2006.162.08:06:21.06#ibcon#read 5, iclass 32, count 2 2006.162.08:06:21.06#ibcon#about to read 6, iclass 32, count 2 2006.162.08:06:21.06#ibcon#read 6, iclass 32, count 2 2006.162.08:06:21.06#ibcon#end of sib2, iclass 32, count 2 2006.162.08:06:21.06#ibcon#*mode == 0, iclass 32, count 2 2006.162.08:06:21.06#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.162.08:06:21.06#ibcon#[25=AT06-06\r\n] 2006.162.08:06:21.06#ibcon#*before write, iclass 32, count 2 2006.162.08:06:21.06#ibcon#enter sib2, iclass 32, count 2 2006.162.08:06:21.06#ibcon#flushed, iclass 32, count 2 2006.162.08:06:21.06#ibcon#about to write, iclass 32, count 2 2006.162.08:06:21.06#ibcon#wrote, iclass 32, count 2 2006.162.08:06:21.06#ibcon#about to read 3, iclass 32, count 2 2006.162.08:06:21.09#ibcon#read 3, iclass 32, count 2 2006.162.08:06:21.09#ibcon#about to read 4, iclass 32, count 2 2006.162.08:06:21.09#ibcon#read 4, iclass 32, count 2 2006.162.08:06:21.09#ibcon#about to read 5, iclass 32, count 2 2006.162.08:06:21.09#ibcon#read 5, iclass 32, count 2 2006.162.08:06:21.09#ibcon#about to read 6, iclass 32, count 2 2006.162.08:06:21.09#ibcon#read 6, iclass 32, count 2 2006.162.08:06:21.09#ibcon#end of sib2, iclass 32, count 2 2006.162.08:06:21.09#ibcon#*after write, iclass 32, count 2 2006.162.08:06:21.09#ibcon#*before return 0, iclass 32, count 2 2006.162.08:06:21.09#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.162.08:06:21.09#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.162.08:06:21.09#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.162.08:06:21.09#ibcon#ireg 7 cls_cnt 0 2006.162.08:06:21.09#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.162.08:06:21.21#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.162.08:06:21.21#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.162.08:06:21.21#ibcon#enter wrdev, iclass 32, count 0 2006.162.08:06:21.21#ibcon#first serial, iclass 32, count 0 2006.162.08:06:21.21#ibcon#enter sib2, iclass 32, count 0 2006.162.08:06:21.21#ibcon#flushed, iclass 32, count 0 2006.162.08:06:21.21#ibcon#about to write, iclass 32, count 0 2006.162.08:06:21.21#ibcon#wrote, iclass 32, count 0 2006.162.08:06:21.21#ibcon#about to read 3, iclass 32, count 0 2006.162.08:06:21.23#ibcon#read 3, iclass 32, count 0 2006.162.08:06:21.23#ibcon#about to read 4, iclass 32, count 0 2006.162.08:06:21.23#ibcon#read 4, iclass 32, count 0 2006.162.08:06:21.23#ibcon#about to read 5, iclass 32, count 0 2006.162.08:06:21.23#ibcon#read 5, iclass 32, count 0 2006.162.08:06:21.23#ibcon#about to read 6, iclass 32, count 0 2006.162.08:06:21.23#ibcon#read 6, iclass 32, count 0 2006.162.08:06:21.23#ibcon#end of sib2, iclass 32, count 0 2006.162.08:06:21.23#ibcon#*mode == 0, iclass 32, count 0 2006.162.08:06:21.23#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.162.08:06:21.23#ibcon#[25=USB\r\n] 2006.162.08:06:21.23#ibcon#*before write, iclass 32, count 0 2006.162.08:06:21.23#ibcon#enter sib2, iclass 32, count 0 2006.162.08:06:21.23#ibcon#flushed, iclass 32, count 0 2006.162.08:06:21.23#ibcon#about to write, iclass 32, count 0 2006.162.08:06:21.23#ibcon#wrote, iclass 32, count 0 2006.162.08:06:21.23#ibcon#about to read 3, iclass 32, count 0 2006.162.08:06:21.26#ibcon#read 3, iclass 32, count 0 2006.162.08:06:21.26#ibcon#about to read 4, iclass 32, count 0 2006.162.08:06:21.26#ibcon#read 4, iclass 32, count 0 2006.162.08:06:21.26#ibcon#about to read 5, iclass 32, count 0 2006.162.08:06:21.26#ibcon#read 5, iclass 32, count 0 2006.162.08:06:21.26#ibcon#about to read 6, iclass 32, count 0 2006.162.08:06:21.26#ibcon#read 6, iclass 32, count 0 2006.162.08:06:21.26#ibcon#end of sib2, iclass 32, count 0 2006.162.08:06:21.26#ibcon#*after write, iclass 32, count 0 2006.162.08:06:21.26#ibcon#*before return 0, iclass 32, count 0 2006.162.08:06:21.26#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.162.08:06:21.26#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.162.08:06:21.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.162.08:06:21.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.162.08:06:21.26$vc4f8/valo=7,832.99 2006.162.08:06:21.26#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.162.08:06:21.26#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.162.08:06:21.26#ibcon#ireg 17 cls_cnt 0 2006.162.08:06:21.26#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:06:21.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:06:21.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:06:21.26#ibcon#enter wrdev, iclass 34, count 0 2006.162.08:06:21.26#ibcon#first serial, iclass 34, count 0 2006.162.08:06:21.26#ibcon#enter sib2, iclass 34, count 0 2006.162.08:06:21.26#ibcon#flushed, iclass 34, count 0 2006.162.08:06:21.26#ibcon#about to write, iclass 34, count 0 2006.162.08:06:21.26#ibcon#wrote, iclass 34, count 0 2006.162.08:06:21.26#ibcon#about to read 3, iclass 34, count 0 2006.162.08:06:21.28#ibcon#read 3, iclass 34, count 0 2006.162.08:06:21.28#ibcon#about to read 4, iclass 34, count 0 2006.162.08:06:21.28#ibcon#read 4, iclass 34, count 0 2006.162.08:06:21.28#ibcon#about to read 5, iclass 34, count 0 2006.162.08:06:21.28#ibcon#read 5, iclass 34, count 0 2006.162.08:06:21.28#ibcon#about to read 6, iclass 34, count 0 2006.162.08:06:21.28#ibcon#read 6, iclass 34, count 0 2006.162.08:06:21.28#ibcon#end of sib2, iclass 34, count 0 2006.162.08:06:21.28#ibcon#*mode == 0, iclass 34, count 0 2006.162.08:06:21.28#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.162.08:06:21.28#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.08:06:21.28#ibcon#*before write, iclass 34, count 0 2006.162.08:06:21.28#ibcon#enter sib2, iclass 34, count 0 2006.162.08:06:21.28#ibcon#flushed, iclass 34, count 0 2006.162.08:06:21.28#ibcon#about to write, iclass 34, count 0 2006.162.08:06:21.28#ibcon#wrote, iclass 34, count 0 2006.162.08:06:21.28#ibcon#about to read 3, iclass 34, count 0 2006.162.08:06:21.32#ibcon#read 3, iclass 34, count 0 2006.162.08:06:21.32#ibcon#about to read 4, iclass 34, count 0 2006.162.08:06:21.32#ibcon#read 4, iclass 34, count 0 2006.162.08:06:21.32#ibcon#about to read 5, iclass 34, count 0 2006.162.08:06:21.32#ibcon#read 5, iclass 34, count 0 2006.162.08:06:21.32#ibcon#about to read 6, iclass 34, count 0 2006.162.08:06:21.32#ibcon#read 6, iclass 34, count 0 2006.162.08:06:21.32#ibcon#end of sib2, iclass 34, count 0 2006.162.08:06:21.32#ibcon#*after write, iclass 34, count 0 2006.162.08:06:21.32#ibcon#*before return 0, iclass 34, count 0 2006.162.08:06:21.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:06:21.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:06:21.32#ibcon#about to clear, iclass 34 cls_cnt 0 2006.162.08:06:21.32#ibcon#cleared, iclass 34 cls_cnt 0 2006.162.08:06:21.32$vc4f8/va=7,6 2006.162.08:06:21.32#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.162.08:06:21.32#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.162.08:06:21.32#ibcon#ireg 11 cls_cnt 2 2006.162.08:06:21.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:06:21.38#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:06:21.38#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:06:21.38#ibcon#enter wrdev, iclass 36, count 2 2006.162.08:06:21.38#ibcon#first serial, iclass 36, count 2 2006.162.08:06:21.38#ibcon#enter sib2, iclass 36, count 2 2006.162.08:06:21.38#ibcon#flushed, iclass 36, count 2 2006.162.08:06:21.38#ibcon#about to write, iclass 36, count 2 2006.162.08:06:21.38#ibcon#wrote, iclass 36, count 2 2006.162.08:06:21.38#ibcon#about to read 3, iclass 36, count 2 2006.162.08:06:21.40#ibcon#read 3, iclass 36, count 2 2006.162.08:06:21.40#ibcon#about to read 4, iclass 36, count 2 2006.162.08:06:21.40#ibcon#read 4, iclass 36, count 2 2006.162.08:06:21.40#ibcon#about to read 5, iclass 36, count 2 2006.162.08:06:21.40#ibcon#read 5, iclass 36, count 2 2006.162.08:06:21.40#ibcon#about to read 6, iclass 36, count 2 2006.162.08:06:21.40#ibcon#read 6, iclass 36, count 2 2006.162.08:06:21.40#ibcon#end of sib2, iclass 36, count 2 2006.162.08:06:21.40#ibcon#*mode == 0, iclass 36, count 2 2006.162.08:06:21.40#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.162.08:06:21.40#ibcon#[25=AT07-06\r\n] 2006.162.08:06:21.40#ibcon#*before write, iclass 36, count 2 2006.162.08:06:21.40#ibcon#enter sib2, iclass 36, count 2 2006.162.08:06:21.40#ibcon#flushed, iclass 36, count 2 2006.162.08:06:21.40#ibcon#about to write, iclass 36, count 2 2006.162.08:06:21.40#ibcon#wrote, iclass 36, count 2 2006.162.08:06:21.40#ibcon#about to read 3, iclass 36, count 2 2006.162.08:06:21.43#ibcon#read 3, iclass 36, count 2 2006.162.08:06:21.43#ibcon#about to read 4, iclass 36, count 2 2006.162.08:06:21.43#ibcon#read 4, iclass 36, count 2 2006.162.08:06:21.43#ibcon#about to read 5, iclass 36, count 2 2006.162.08:06:21.43#ibcon#read 5, iclass 36, count 2 2006.162.08:06:21.43#ibcon#about to read 6, iclass 36, count 2 2006.162.08:06:21.43#ibcon#read 6, iclass 36, count 2 2006.162.08:06:21.43#ibcon#end of sib2, iclass 36, count 2 2006.162.08:06:21.43#ibcon#*after write, iclass 36, count 2 2006.162.08:06:21.43#ibcon#*before return 0, iclass 36, count 2 2006.162.08:06:21.43#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:06:21.43#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:06:21.43#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.162.08:06:21.43#ibcon#ireg 7 cls_cnt 0 2006.162.08:06:21.43#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:06:21.55#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:06:21.55#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:06:21.55#ibcon#enter wrdev, iclass 36, count 0 2006.162.08:06:21.55#ibcon#first serial, iclass 36, count 0 2006.162.08:06:21.55#ibcon#enter sib2, iclass 36, count 0 2006.162.08:06:21.55#ibcon#flushed, iclass 36, count 0 2006.162.08:06:21.55#ibcon#about to write, iclass 36, count 0 2006.162.08:06:21.55#ibcon#wrote, iclass 36, count 0 2006.162.08:06:21.55#ibcon#about to read 3, iclass 36, count 0 2006.162.08:06:21.57#ibcon#read 3, iclass 36, count 0 2006.162.08:06:21.57#ibcon#about to read 4, iclass 36, count 0 2006.162.08:06:21.57#ibcon#read 4, iclass 36, count 0 2006.162.08:06:21.57#ibcon#about to read 5, iclass 36, count 0 2006.162.08:06:21.57#ibcon#read 5, iclass 36, count 0 2006.162.08:06:21.57#ibcon#about to read 6, iclass 36, count 0 2006.162.08:06:21.57#ibcon#read 6, iclass 36, count 0 2006.162.08:06:21.57#ibcon#end of sib2, iclass 36, count 0 2006.162.08:06:21.57#ibcon#*mode == 0, iclass 36, count 0 2006.162.08:06:21.57#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.162.08:06:21.57#ibcon#[25=USB\r\n] 2006.162.08:06:21.57#ibcon#*before write, iclass 36, count 0 2006.162.08:06:21.57#ibcon#enter sib2, iclass 36, count 0 2006.162.08:06:21.57#ibcon#flushed, iclass 36, count 0 2006.162.08:06:21.57#ibcon#about to write, iclass 36, count 0 2006.162.08:06:21.57#ibcon#wrote, iclass 36, count 0 2006.162.08:06:21.57#ibcon#about to read 3, iclass 36, count 0 2006.162.08:06:21.60#ibcon#read 3, iclass 36, count 0 2006.162.08:06:21.60#ibcon#about to read 4, iclass 36, count 0 2006.162.08:06:21.60#ibcon#read 4, iclass 36, count 0 2006.162.08:06:21.60#ibcon#about to read 5, iclass 36, count 0 2006.162.08:06:21.60#ibcon#read 5, iclass 36, count 0 2006.162.08:06:21.60#ibcon#about to read 6, iclass 36, count 0 2006.162.08:06:21.60#ibcon#read 6, iclass 36, count 0 2006.162.08:06:21.60#ibcon#end of sib2, iclass 36, count 0 2006.162.08:06:21.60#ibcon#*after write, iclass 36, count 0 2006.162.08:06:21.60#ibcon#*before return 0, iclass 36, count 0 2006.162.08:06:21.60#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:06:21.60#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:06:21.60#ibcon#about to clear, iclass 36 cls_cnt 0 2006.162.08:06:21.60#ibcon#cleared, iclass 36 cls_cnt 0 2006.162.08:06:21.60$vc4f8/valo=8,852.99 2006.162.08:06:21.60#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.162.08:06:21.60#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.162.08:06:21.60#ibcon#ireg 17 cls_cnt 0 2006.162.08:06:21.60#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.162.08:06:21.60#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.162.08:06:21.60#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.162.08:06:21.60#ibcon#enter wrdev, iclass 38, count 0 2006.162.08:06:21.60#ibcon#first serial, iclass 38, count 0 2006.162.08:06:21.60#ibcon#enter sib2, iclass 38, count 0 2006.162.08:06:21.60#ibcon#flushed, iclass 38, count 0 2006.162.08:06:21.60#ibcon#about to write, iclass 38, count 0 2006.162.08:06:21.60#ibcon#wrote, iclass 38, count 0 2006.162.08:06:21.60#ibcon#about to read 3, iclass 38, count 0 2006.162.08:06:21.62#ibcon#read 3, iclass 38, count 0 2006.162.08:06:21.62#ibcon#about to read 4, iclass 38, count 0 2006.162.08:06:21.62#ibcon#read 4, iclass 38, count 0 2006.162.08:06:21.62#ibcon#about to read 5, iclass 38, count 0 2006.162.08:06:21.62#ibcon#read 5, iclass 38, count 0 2006.162.08:06:21.62#ibcon#about to read 6, iclass 38, count 0 2006.162.08:06:21.62#ibcon#read 6, iclass 38, count 0 2006.162.08:06:21.62#ibcon#end of sib2, iclass 38, count 0 2006.162.08:06:21.62#ibcon#*mode == 0, iclass 38, count 0 2006.162.08:06:21.62#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.162.08:06:21.62#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.08:06:21.62#ibcon#*before write, iclass 38, count 0 2006.162.08:06:21.62#ibcon#enter sib2, iclass 38, count 0 2006.162.08:06:21.62#ibcon#flushed, iclass 38, count 0 2006.162.08:06:21.62#ibcon#about to write, iclass 38, count 0 2006.162.08:06:21.62#ibcon#wrote, iclass 38, count 0 2006.162.08:06:21.62#ibcon#about to read 3, iclass 38, count 0 2006.162.08:06:21.66#ibcon#read 3, iclass 38, count 0 2006.162.08:06:21.66#ibcon#about to read 4, iclass 38, count 0 2006.162.08:06:21.66#ibcon#read 4, iclass 38, count 0 2006.162.08:06:21.66#ibcon#about to read 5, iclass 38, count 0 2006.162.08:06:21.66#ibcon#read 5, iclass 38, count 0 2006.162.08:06:21.66#ibcon#about to read 6, iclass 38, count 0 2006.162.08:06:21.66#ibcon#read 6, iclass 38, count 0 2006.162.08:06:21.66#ibcon#end of sib2, iclass 38, count 0 2006.162.08:06:21.66#ibcon#*after write, iclass 38, count 0 2006.162.08:06:21.66#ibcon#*before return 0, iclass 38, count 0 2006.162.08:06:21.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.162.08:06:21.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.162.08:06:21.66#ibcon#about to clear, iclass 38 cls_cnt 0 2006.162.08:06:21.66#ibcon#cleared, iclass 38 cls_cnt 0 2006.162.08:06:21.66$vc4f8/va=8,7 2006.162.08:06:21.66#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.162.08:06:21.66#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.162.08:06:21.66#ibcon#ireg 11 cls_cnt 2 2006.162.08:06:21.66#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.162.08:06:21.72#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.162.08:06:21.72#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.162.08:06:21.72#ibcon#enter wrdev, iclass 40, count 2 2006.162.08:06:21.72#ibcon#first serial, iclass 40, count 2 2006.162.08:06:21.72#ibcon#enter sib2, iclass 40, count 2 2006.162.08:06:21.72#ibcon#flushed, iclass 40, count 2 2006.162.08:06:21.72#ibcon#about to write, iclass 40, count 2 2006.162.08:06:21.72#ibcon#wrote, iclass 40, count 2 2006.162.08:06:21.72#ibcon#about to read 3, iclass 40, count 2 2006.162.08:06:21.74#ibcon#read 3, iclass 40, count 2 2006.162.08:06:21.74#ibcon#about to read 4, iclass 40, count 2 2006.162.08:06:21.74#ibcon#read 4, iclass 40, count 2 2006.162.08:06:21.74#ibcon#about to read 5, iclass 40, count 2 2006.162.08:06:21.74#ibcon#read 5, iclass 40, count 2 2006.162.08:06:21.74#ibcon#about to read 6, iclass 40, count 2 2006.162.08:06:21.74#ibcon#read 6, iclass 40, count 2 2006.162.08:06:21.74#ibcon#end of sib2, iclass 40, count 2 2006.162.08:06:21.74#ibcon#*mode == 0, iclass 40, count 2 2006.162.08:06:21.74#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.162.08:06:21.74#ibcon#[25=AT08-07\r\n] 2006.162.08:06:21.74#ibcon#*before write, iclass 40, count 2 2006.162.08:06:21.74#ibcon#enter sib2, iclass 40, count 2 2006.162.08:06:21.74#ibcon#flushed, iclass 40, count 2 2006.162.08:06:21.74#ibcon#about to write, iclass 40, count 2 2006.162.08:06:21.74#ibcon#wrote, iclass 40, count 2 2006.162.08:06:21.74#ibcon#about to read 3, iclass 40, count 2 2006.162.08:06:21.77#ibcon#read 3, iclass 40, count 2 2006.162.08:06:21.77#ibcon#about to read 4, iclass 40, count 2 2006.162.08:06:21.77#ibcon#read 4, iclass 40, count 2 2006.162.08:06:21.77#ibcon#about to read 5, iclass 40, count 2 2006.162.08:06:21.77#ibcon#read 5, iclass 40, count 2 2006.162.08:06:21.77#ibcon#about to read 6, iclass 40, count 2 2006.162.08:06:21.77#ibcon#read 6, iclass 40, count 2 2006.162.08:06:21.77#ibcon#end of sib2, iclass 40, count 2 2006.162.08:06:21.77#ibcon#*after write, iclass 40, count 2 2006.162.08:06:21.77#ibcon#*before return 0, iclass 40, count 2 2006.162.08:06:21.77#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.162.08:06:21.77#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.162.08:06:21.77#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.162.08:06:21.77#ibcon#ireg 7 cls_cnt 0 2006.162.08:06:21.77#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.162.08:06:21.89#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.162.08:06:21.89#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.162.08:06:21.89#ibcon#enter wrdev, iclass 40, count 0 2006.162.08:06:21.89#ibcon#first serial, iclass 40, count 0 2006.162.08:06:21.89#ibcon#enter sib2, iclass 40, count 0 2006.162.08:06:21.89#ibcon#flushed, iclass 40, count 0 2006.162.08:06:21.89#ibcon#about to write, iclass 40, count 0 2006.162.08:06:21.89#ibcon#wrote, iclass 40, count 0 2006.162.08:06:21.89#ibcon#about to read 3, iclass 40, count 0 2006.162.08:06:21.91#ibcon#read 3, iclass 40, count 0 2006.162.08:06:21.91#ibcon#about to read 4, iclass 40, count 0 2006.162.08:06:21.91#ibcon#read 4, iclass 40, count 0 2006.162.08:06:21.91#ibcon#about to read 5, iclass 40, count 0 2006.162.08:06:21.91#ibcon#read 5, iclass 40, count 0 2006.162.08:06:21.91#ibcon#about to read 6, iclass 40, count 0 2006.162.08:06:21.91#ibcon#read 6, iclass 40, count 0 2006.162.08:06:21.91#ibcon#end of sib2, iclass 40, count 0 2006.162.08:06:21.91#ibcon#*mode == 0, iclass 40, count 0 2006.162.08:06:21.91#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.162.08:06:21.91#ibcon#[25=USB\r\n] 2006.162.08:06:21.91#ibcon#*before write, iclass 40, count 0 2006.162.08:06:21.91#ibcon#enter sib2, iclass 40, count 0 2006.162.08:06:21.91#ibcon#flushed, iclass 40, count 0 2006.162.08:06:21.91#ibcon#about to write, iclass 40, count 0 2006.162.08:06:21.91#ibcon#wrote, iclass 40, count 0 2006.162.08:06:21.91#ibcon#about to read 3, iclass 40, count 0 2006.162.08:06:21.94#ibcon#read 3, iclass 40, count 0 2006.162.08:06:21.94#ibcon#about to read 4, iclass 40, count 0 2006.162.08:06:21.94#ibcon#read 4, iclass 40, count 0 2006.162.08:06:21.94#ibcon#about to read 5, iclass 40, count 0 2006.162.08:06:21.94#ibcon#read 5, iclass 40, count 0 2006.162.08:06:21.94#ibcon#about to read 6, iclass 40, count 0 2006.162.08:06:21.94#ibcon#read 6, iclass 40, count 0 2006.162.08:06:21.94#ibcon#end of sib2, iclass 40, count 0 2006.162.08:06:21.94#ibcon#*after write, iclass 40, count 0 2006.162.08:06:21.94#ibcon#*before return 0, iclass 40, count 0 2006.162.08:06:21.94#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.162.08:06:21.94#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.162.08:06:21.94#ibcon#about to clear, iclass 40 cls_cnt 0 2006.162.08:06:21.94#ibcon#cleared, iclass 40 cls_cnt 0 2006.162.08:06:21.94$vc4f8/vblo=1,632.99 2006.162.08:06:21.94#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.162.08:06:21.94#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.162.08:06:21.94#ibcon#ireg 17 cls_cnt 0 2006.162.08:06:21.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:06:21.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:06:21.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:06:21.94#ibcon#enter wrdev, iclass 4, count 0 2006.162.08:06:21.94#ibcon#first serial, iclass 4, count 0 2006.162.08:06:21.94#ibcon#enter sib2, iclass 4, count 0 2006.162.08:06:21.94#ibcon#flushed, iclass 4, count 0 2006.162.08:06:21.94#ibcon#about to write, iclass 4, count 0 2006.162.08:06:21.94#ibcon#wrote, iclass 4, count 0 2006.162.08:06:21.94#ibcon#about to read 3, iclass 4, count 0 2006.162.08:06:21.96#ibcon#read 3, iclass 4, count 0 2006.162.08:06:21.96#ibcon#about to read 4, iclass 4, count 0 2006.162.08:06:21.96#ibcon#read 4, iclass 4, count 0 2006.162.08:06:21.96#ibcon#about to read 5, iclass 4, count 0 2006.162.08:06:21.96#ibcon#read 5, iclass 4, count 0 2006.162.08:06:21.96#ibcon#about to read 6, iclass 4, count 0 2006.162.08:06:21.96#ibcon#read 6, iclass 4, count 0 2006.162.08:06:21.96#ibcon#end of sib2, iclass 4, count 0 2006.162.08:06:21.96#ibcon#*mode == 0, iclass 4, count 0 2006.162.08:06:21.96#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.162.08:06:21.96#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.08:06:21.96#ibcon#*before write, iclass 4, count 0 2006.162.08:06:21.96#ibcon#enter sib2, iclass 4, count 0 2006.162.08:06:21.96#ibcon#flushed, iclass 4, count 0 2006.162.08:06:21.96#ibcon#about to write, iclass 4, count 0 2006.162.08:06:21.96#ibcon#wrote, iclass 4, count 0 2006.162.08:06:21.96#ibcon#about to read 3, iclass 4, count 0 2006.162.08:06:22.00#ibcon#read 3, iclass 4, count 0 2006.162.08:06:22.00#ibcon#about to read 4, iclass 4, count 0 2006.162.08:06:22.00#ibcon#read 4, iclass 4, count 0 2006.162.08:06:22.00#ibcon#about to read 5, iclass 4, count 0 2006.162.08:06:22.00#ibcon#read 5, iclass 4, count 0 2006.162.08:06:22.00#ibcon#about to read 6, iclass 4, count 0 2006.162.08:06:22.00#ibcon#read 6, iclass 4, count 0 2006.162.08:06:22.00#ibcon#end of sib2, iclass 4, count 0 2006.162.08:06:22.00#ibcon#*after write, iclass 4, count 0 2006.162.08:06:22.00#ibcon#*before return 0, iclass 4, count 0 2006.162.08:06:22.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:06:22.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:06:22.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.162.08:06:22.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.162.08:06:22.00$vc4f8/vb=1,4 2006.162.08:06:22.00#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.162.08:06:22.00#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.162.08:06:22.00#ibcon#ireg 11 cls_cnt 2 2006.162.08:06:22.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.162.08:06:22.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.162.08:06:22.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.162.08:06:22.00#ibcon#enter wrdev, iclass 6, count 2 2006.162.08:06:22.00#ibcon#first serial, iclass 6, count 2 2006.162.08:06:22.00#ibcon#enter sib2, iclass 6, count 2 2006.162.08:06:22.00#ibcon#flushed, iclass 6, count 2 2006.162.08:06:22.00#ibcon#about to write, iclass 6, count 2 2006.162.08:06:22.00#ibcon#wrote, iclass 6, count 2 2006.162.08:06:22.00#ibcon#about to read 3, iclass 6, count 2 2006.162.08:06:22.02#ibcon#read 3, iclass 6, count 2 2006.162.08:06:22.02#ibcon#about to read 4, iclass 6, count 2 2006.162.08:06:22.02#ibcon#read 4, iclass 6, count 2 2006.162.08:06:22.02#ibcon#about to read 5, iclass 6, count 2 2006.162.08:06:22.02#ibcon#read 5, iclass 6, count 2 2006.162.08:06:22.02#ibcon#about to read 6, iclass 6, count 2 2006.162.08:06:22.02#ibcon#read 6, iclass 6, count 2 2006.162.08:06:22.02#ibcon#end of sib2, iclass 6, count 2 2006.162.08:06:22.02#ibcon#*mode == 0, iclass 6, count 2 2006.162.08:06:22.02#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.162.08:06:22.02#ibcon#[27=AT01-04\r\n] 2006.162.08:06:22.02#ibcon#*before write, iclass 6, count 2 2006.162.08:06:22.02#ibcon#enter sib2, iclass 6, count 2 2006.162.08:06:22.02#ibcon#flushed, iclass 6, count 2 2006.162.08:06:22.02#ibcon#about to write, iclass 6, count 2 2006.162.08:06:22.02#ibcon#wrote, iclass 6, count 2 2006.162.08:06:22.02#ibcon#about to read 3, iclass 6, count 2 2006.162.08:06:22.05#ibcon#read 3, iclass 6, count 2 2006.162.08:06:22.05#ibcon#about to read 4, iclass 6, count 2 2006.162.08:06:22.05#ibcon#read 4, iclass 6, count 2 2006.162.08:06:22.05#ibcon#about to read 5, iclass 6, count 2 2006.162.08:06:22.05#ibcon#read 5, iclass 6, count 2 2006.162.08:06:22.05#ibcon#about to read 6, iclass 6, count 2 2006.162.08:06:22.05#ibcon#read 6, iclass 6, count 2 2006.162.08:06:22.05#ibcon#end of sib2, iclass 6, count 2 2006.162.08:06:22.05#ibcon#*after write, iclass 6, count 2 2006.162.08:06:22.05#ibcon#*before return 0, iclass 6, count 2 2006.162.08:06:22.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.162.08:06:22.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.162.08:06:22.05#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.162.08:06:22.05#ibcon#ireg 7 cls_cnt 0 2006.162.08:06:22.05#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.162.08:06:22.17#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.162.08:06:22.17#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.162.08:06:22.17#ibcon#enter wrdev, iclass 6, count 0 2006.162.08:06:22.17#ibcon#first serial, iclass 6, count 0 2006.162.08:06:22.17#ibcon#enter sib2, iclass 6, count 0 2006.162.08:06:22.17#ibcon#flushed, iclass 6, count 0 2006.162.08:06:22.17#ibcon#about to write, iclass 6, count 0 2006.162.08:06:22.17#ibcon#wrote, iclass 6, count 0 2006.162.08:06:22.17#ibcon#about to read 3, iclass 6, count 0 2006.162.08:06:22.19#ibcon#read 3, iclass 6, count 0 2006.162.08:06:22.19#ibcon#about to read 4, iclass 6, count 0 2006.162.08:06:22.19#ibcon#read 4, iclass 6, count 0 2006.162.08:06:22.19#ibcon#about to read 5, iclass 6, count 0 2006.162.08:06:22.19#ibcon#read 5, iclass 6, count 0 2006.162.08:06:22.19#ibcon#about to read 6, iclass 6, count 0 2006.162.08:06:22.19#ibcon#read 6, iclass 6, count 0 2006.162.08:06:22.19#ibcon#end of sib2, iclass 6, count 0 2006.162.08:06:22.19#ibcon#*mode == 0, iclass 6, count 0 2006.162.08:06:22.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.162.08:06:22.19#ibcon#[27=USB\r\n] 2006.162.08:06:22.19#ibcon#*before write, iclass 6, count 0 2006.162.08:06:22.19#ibcon#enter sib2, iclass 6, count 0 2006.162.08:06:22.19#ibcon#flushed, iclass 6, count 0 2006.162.08:06:22.19#ibcon#about to write, iclass 6, count 0 2006.162.08:06:22.19#ibcon#wrote, iclass 6, count 0 2006.162.08:06:22.19#ibcon#about to read 3, iclass 6, count 0 2006.162.08:06:22.22#ibcon#read 3, iclass 6, count 0 2006.162.08:06:22.22#ibcon#about to read 4, iclass 6, count 0 2006.162.08:06:22.22#ibcon#read 4, iclass 6, count 0 2006.162.08:06:22.22#ibcon#about to read 5, iclass 6, count 0 2006.162.08:06:22.22#ibcon#read 5, iclass 6, count 0 2006.162.08:06:22.22#ibcon#about to read 6, iclass 6, count 0 2006.162.08:06:22.22#ibcon#read 6, iclass 6, count 0 2006.162.08:06:22.22#ibcon#end of sib2, iclass 6, count 0 2006.162.08:06:22.22#ibcon#*after write, iclass 6, count 0 2006.162.08:06:22.22#ibcon#*before return 0, iclass 6, count 0 2006.162.08:06:22.22#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.162.08:06:22.22#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.162.08:06:22.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.162.08:06:22.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.162.08:06:22.22$vc4f8/vblo=2,640.99 2006.162.08:06:22.22#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.162.08:06:22.22#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.162.08:06:22.22#ibcon#ireg 17 cls_cnt 0 2006.162.08:06:22.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:06:22.22#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:06:22.22#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:06:22.22#ibcon#enter wrdev, iclass 10, count 0 2006.162.08:06:22.22#ibcon#first serial, iclass 10, count 0 2006.162.08:06:22.22#ibcon#enter sib2, iclass 10, count 0 2006.162.08:06:22.22#ibcon#flushed, iclass 10, count 0 2006.162.08:06:22.22#ibcon#about to write, iclass 10, count 0 2006.162.08:06:22.22#ibcon#wrote, iclass 10, count 0 2006.162.08:06:22.22#ibcon#about to read 3, iclass 10, count 0 2006.162.08:06:22.24#ibcon#read 3, iclass 10, count 0 2006.162.08:06:22.24#ibcon#about to read 4, iclass 10, count 0 2006.162.08:06:22.24#ibcon#read 4, iclass 10, count 0 2006.162.08:06:22.24#ibcon#about to read 5, iclass 10, count 0 2006.162.08:06:22.24#ibcon#read 5, iclass 10, count 0 2006.162.08:06:22.24#ibcon#about to read 6, iclass 10, count 0 2006.162.08:06:22.24#ibcon#read 6, iclass 10, count 0 2006.162.08:06:22.24#ibcon#end of sib2, iclass 10, count 0 2006.162.08:06:22.24#ibcon#*mode == 0, iclass 10, count 0 2006.162.08:06:22.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.162.08:06:22.24#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.08:06:22.24#ibcon#*before write, iclass 10, count 0 2006.162.08:06:22.24#ibcon#enter sib2, iclass 10, count 0 2006.162.08:06:22.24#ibcon#flushed, iclass 10, count 0 2006.162.08:06:22.24#ibcon#about to write, iclass 10, count 0 2006.162.08:06:22.24#ibcon#wrote, iclass 10, count 0 2006.162.08:06:22.24#ibcon#about to read 3, iclass 10, count 0 2006.162.08:06:22.28#ibcon#read 3, iclass 10, count 0 2006.162.08:06:22.28#ibcon#about to read 4, iclass 10, count 0 2006.162.08:06:22.28#ibcon#read 4, iclass 10, count 0 2006.162.08:06:22.28#ibcon#about to read 5, iclass 10, count 0 2006.162.08:06:22.28#ibcon#read 5, iclass 10, count 0 2006.162.08:06:22.28#ibcon#about to read 6, iclass 10, count 0 2006.162.08:06:22.28#ibcon#read 6, iclass 10, count 0 2006.162.08:06:22.28#ibcon#end of sib2, iclass 10, count 0 2006.162.08:06:22.28#ibcon#*after write, iclass 10, count 0 2006.162.08:06:22.28#ibcon#*before return 0, iclass 10, count 0 2006.162.08:06:22.28#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:06:22.28#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:06:22.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.162.08:06:22.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.162.08:06:22.28$vc4f8/vb=2,4 2006.162.08:06:22.28#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.162.08:06:22.28#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.162.08:06:22.28#ibcon#ireg 11 cls_cnt 2 2006.162.08:06:22.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:06:22.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:06:22.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:06:22.34#ibcon#enter wrdev, iclass 12, count 2 2006.162.08:06:22.34#ibcon#first serial, iclass 12, count 2 2006.162.08:06:22.34#ibcon#enter sib2, iclass 12, count 2 2006.162.08:06:22.34#ibcon#flushed, iclass 12, count 2 2006.162.08:06:22.34#ibcon#about to write, iclass 12, count 2 2006.162.08:06:22.34#ibcon#wrote, iclass 12, count 2 2006.162.08:06:22.34#ibcon#about to read 3, iclass 12, count 2 2006.162.08:06:22.36#ibcon#read 3, iclass 12, count 2 2006.162.08:06:22.36#ibcon#about to read 4, iclass 12, count 2 2006.162.08:06:22.36#ibcon#read 4, iclass 12, count 2 2006.162.08:06:22.36#ibcon#about to read 5, iclass 12, count 2 2006.162.08:06:22.36#ibcon#read 5, iclass 12, count 2 2006.162.08:06:22.36#ibcon#about to read 6, iclass 12, count 2 2006.162.08:06:22.36#ibcon#read 6, iclass 12, count 2 2006.162.08:06:22.36#ibcon#end of sib2, iclass 12, count 2 2006.162.08:06:22.36#ibcon#*mode == 0, iclass 12, count 2 2006.162.08:06:22.36#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.162.08:06:22.36#ibcon#[27=AT02-04\r\n] 2006.162.08:06:22.36#ibcon#*before write, iclass 12, count 2 2006.162.08:06:22.36#ibcon#enter sib2, iclass 12, count 2 2006.162.08:06:22.36#ibcon#flushed, iclass 12, count 2 2006.162.08:06:22.36#ibcon#about to write, iclass 12, count 2 2006.162.08:06:22.36#ibcon#wrote, iclass 12, count 2 2006.162.08:06:22.36#ibcon#about to read 3, iclass 12, count 2 2006.162.08:06:22.39#ibcon#read 3, iclass 12, count 2 2006.162.08:06:22.39#ibcon#about to read 4, iclass 12, count 2 2006.162.08:06:22.39#ibcon#read 4, iclass 12, count 2 2006.162.08:06:22.39#ibcon#about to read 5, iclass 12, count 2 2006.162.08:06:22.39#ibcon#read 5, iclass 12, count 2 2006.162.08:06:22.39#ibcon#about to read 6, iclass 12, count 2 2006.162.08:06:22.39#ibcon#read 6, iclass 12, count 2 2006.162.08:06:22.39#ibcon#end of sib2, iclass 12, count 2 2006.162.08:06:22.39#ibcon#*after write, iclass 12, count 2 2006.162.08:06:22.39#ibcon#*before return 0, iclass 12, count 2 2006.162.08:06:22.39#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:06:22.39#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:06:22.39#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.162.08:06:22.39#ibcon#ireg 7 cls_cnt 0 2006.162.08:06:22.39#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:06:22.51#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:06:22.51#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:06:22.51#ibcon#enter wrdev, iclass 12, count 0 2006.162.08:06:22.51#ibcon#first serial, iclass 12, count 0 2006.162.08:06:22.51#ibcon#enter sib2, iclass 12, count 0 2006.162.08:06:22.51#ibcon#flushed, iclass 12, count 0 2006.162.08:06:22.51#ibcon#about to write, iclass 12, count 0 2006.162.08:06:22.51#ibcon#wrote, iclass 12, count 0 2006.162.08:06:22.51#ibcon#about to read 3, iclass 12, count 0 2006.162.08:06:22.53#ibcon#read 3, iclass 12, count 0 2006.162.08:06:22.53#ibcon#about to read 4, iclass 12, count 0 2006.162.08:06:22.53#ibcon#read 4, iclass 12, count 0 2006.162.08:06:22.53#ibcon#about to read 5, iclass 12, count 0 2006.162.08:06:22.53#ibcon#read 5, iclass 12, count 0 2006.162.08:06:22.53#ibcon#about to read 6, iclass 12, count 0 2006.162.08:06:22.53#ibcon#read 6, iclass 12, count 0 2006.162.08:06:22.53#ibcon#end of sib2, iclass 12, count 0 2006.162.08:06:22.53#ibcon#*mode == 0, iclass 12, count 0 2006.162.08:06:22.53#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.162.08:06:22.53#ibcon#[27=USB\r\n] 2006.162.08:06:22.53#ibcon#*before write, iclass 12, count 0 2006.162.08:06:22.53#ibcon#enter sib2, iclass 12, count 0 2006.162.08:06:22.53#ibcon#flushed, iclass 12, count 0 2006.162.08:06:22.53#ibcon#about to write, iclass 12, count 0 2006.162.08:06:22.53#ibcon#wrote, iclass 12, count 0 2006.162.08:06:22.53#ibcon#about to read 3, iclass 12, count 0 2006.162.08:06:22.56#ibcon#read 3, iclass 12, count 0 2006.162.08:06:22.56#ibcon#about to read 4, iclass 12, count 0 2006.162.08:06:22.56#ibcon#read 4, iclass 12, count 0 2006.162.08:06:22.56#ibcon#about to read 5, iclass 12, count 0 2006.162.08:06:22.56#ibcon#read 5, iclass 12, count 0 2006.162.08:06:22.56#ibcon#about to read 6, iclass 12, count 0 2006.162.08:06:22.56#ibcon#read 6, iclass 12, count 0 2006.162.08:06:22.56#ibcon#end of sib2, iclass 12, count 0 2006.162.08:06:22.56#ibcon#*after write, iclass 12, count 0 2006.162.08:06:22.56#ibcon#*before return 0, iclass 12, count 0 2006.162.08:06:22.56#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:06:22.56#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:06:22.56#ibcon#about to clear, iclass 12 cls_cnt 0 2006.162.08:06:22.56#ibcon#cleared, iclass 12 cls_cnt 0 2006.162.08:06:22.56$vc4f8/vblo=3,656.99 2006.162.08:06:22.56#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.162.08:06:22.56#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.162.08:06:22.56#ibcon#ireg 17 cls_cnt 0 2006.162.08:06:22.56#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:06:22.56#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:06:22.56#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:06:22.56#ibcon#enter wrdev, iclass 14, count 0 2006.162.08:06:22.56#ibcon#first serial, iclass 14, count 0 2006.162.08:06:22.56#ibcon#enter sib2, iclass 14, count 0 2006.162.08:06:22.56#ibcon#flushed, iclass 14, count 0 2006.162.08:06:22.56#ibcon#about to write, iclass 14, count 0 2006.162.08:06:22.56#ibcon#wrote, iclass 14, count 0 2006.162.08:06:22.56#ibcon#about to read 3, iclass 14, count 0 2006.162.08:06:22.58#ibcon#read 3, iclass 14, count 0 2006.162.08:06:22.58#ibcon#about to read 4, iclass 14, count 0 2006.162.08:06:22.58#ibcon#read 4, iclass 14, count 0 2006.162.08:06:22.58#ibcon#about to read 5, iclass 14, count 0 2006.162.08:06:22.58#ibcon#read 5, iclass 14, count 0 2006.162.08:06:22.58#ibcon#about to read 6, iclass 14, count 0 2006.162.08:06:22.58#ibcon#read 6, iclass 14, count 0 2006.162.08:06:22.58#ibcon#end of sib2, iclass 14, count 0 2006.162.08:06:22.58#ibcon#*mode == 0, iclass 14, count 0 2006.162.08:06:22.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.08:06:22.58#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.08:06:22.58#ibcon#*before write, iclass 14, count 0 2006.162.08:06:22.58#ibcon#enter sib2, iclass 14, count 0 2006.162.08:06:22.58#ibcon#flushed, iclass 14, count 0 2006.162.08:06:22.58#ibcon#about to write, iclass 14, count 0 2006.162.08:06:22.58#ibcon#wrote, iclass 14, count 0 2006.162.08:06:22.58#ibcon#about to read 3, iclass 14, count 0 2006.162.08:06:22.62#ibcon#read 3, iclass 14, count 0 2006.162.08:06:22.62#ibcon#about to read 4, iclass 14, count 0 2006.162.08:06:22.62#ibcon#read 4, iclass 14, count 0 2006.162.08:06:22.62#ibcon#about to read 5, iclass 14, count 0 2006.162.08:06:22.62#ibcon#read 5, iclass 14, count 0 2006.162.08:06:22.62#ibcon#about to read 6, iclass 14, count 0 2006.162.08:06:22.62#ibcon#read 6, iclass 14, count 0 2006.162.08:06:22.62#ibcon#end of sib2, iclass 14, count 0 2006.162.08:06:22.62#ibcon#*after write, iclass 14, count 0 2006.162.08:06:22.62#ibcon#*before return 0, iclass 14, count 0 2006.162.08:06:22.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:06:22.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:06:22.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.08:06:22.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.08:06:22.62$vc4f8/vb=3,4 2006.162.08:06:22.62#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.162.08:06:22.62#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.162.08:06:22.62#ibcon#ireg 11 cls_cnt 2 2006.162.08:06:22.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:06:22.68#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:06:22.68#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:06:22.68#ibcon#enter wrdev, iclass 16, count 2 2006.162.08:06:22.68#ibcon#first serial, iclass 16, count 2 2006.162.08:06:22.68#ibcon#enter sib2, iclass 16, count 2 2006.162.08:06:22.68#ibcon#flushed, iclass 16, count 2 2006.162.08:06:22.68#ibcon#about to write, iclass 16, count 2 2006.162.08:06:22.68#ibcon#wrote, iclass 16, count 2 2006.162.08:06:22.68#ibcon#about to read 3, iclass 16, count 2 2006.162.08:06:22.70#ibcon#read 3, iclass 16, count 2 2006.162.08:06:22.70#ibcon#about to read 4, iclass 16, count 2 2006.162.08:06:22.70#ibcon#read 4, iclass 16, count 2 2006.162.08:06:22.70#ibcon#about to read 5, iclass 16, count 2 2006.162.08:06:22.70#ibcon#read 5, iclass 16, count 2 2006.162.08:06:22.70#ibcon#about to read 6, iclass 16, count 2 2006.162.08:06:22.70#ibcon#read 6, iclass 16, count 2 2006.162.08:06:22.70#ibcon#end of sib2, iclass 16, count 2 2006.162.08:06:22.70#ibcon#*mode == 0, iclass 16, count 2 2006.162.08:06:22.70#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.162.08:06:22.70#ibcon#[27=AT03-04\r\n] 2006.162.08:06:22.70#ibcon#*before write, iclass 16, count 2 2006.162.08:06:22.70#ibcon#enter sib2, iclass 16, count 2 2006.162.08:06:22.70#ibcon#flushed, iclass 16, count 2 2006.162.08:06:22.70#ibcon#about to write, iclass 16, count 2 2006.162.08:06:22.70#ibcon#wrote, iclass 16, count 2 2006.162.08:06:22.70#ibcon#about to read 3, iclass 16, count 2 2006.162.08:06:22.73#ibcon#read 3, iclass 16, count 2 2006.162.08:06:22.73#ibcon#about to read 4, iclass 16, count 2 2006.162.08:06:22.73#ibcon#read 4, iclass 16, count 2 2006.162.08:06:22.73#ibcon#about to read 5, iclass 16, count 2 2006.162.08:06:22.73#ibcon#read 5, iclass 16, count 2 2006.162.08:06:22.73#ibcon#about to read 6, iclass 16, count 2 2006.162.08:06:22.73#ibcon#read 6, iclass 16, count 2 2006.162.08:06:22.73#ibcon#end of sib2, iclass 16, count 2 2006.162.08:06:22.73#ibcon#*after write, iclass 16, count 2 2006.162.08:06:22.73#ibcon#*before return 0, iclass 16, count 2 2006.162.08:06:22.73#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:06:22.73#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:06:22.73#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.162.08:06:22.73#ibcon#ireg 7 cls_cnt 0 2006.162.08:06:22.73#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:06:22.85#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:06:22.85#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:06:22.85#ibcon#enter wrdev, iclass 16, count 0 2006.162.08:06:22.85#ibcon#first serial, iclass 16, count 0 2006.162.08:06:22.85#ibcon#enter sib2, iclass 16, count 0 2006.162.08:06:22.85#ibcon#flushed, iclass 16, count 0 2006.162.08:06:22.85#ibcon#about to write, iclass 16, count 0 2006.162.08:06:22.85#ibcon#wrote, iclass 16, count 0 2006.162.08:06:22.85#ibcon#about to read 3, iclass 16, count 0 2006.162.08:06:22.87#ibcon#read 3, iclass 16, count 0 2006.162.08:06:22.87#ibcon#about to read 4, iclass 16, count 0 2006.162.08:06:22.87#ibcon#read 4, iclass 16, count 0 2006.162.08:06:22.87#ibcon#about to read 5, iclass 16, count 0 2006.162.08:06:22.87#ibcon#read 5, iclass 16, count 0 2006.162.08:06:22.87#ibcon#about to read 6, iclass 16, count 0 2006.162.08:06:22.87#ibcon#read 6, iclass 16, count 0 2006.162.08:06:22.87#ibcon#end of sib2, iclass 16, count 0 2006.162.08:06:22.87#ibcon#*mode == 0, iclass 16, count 0 2006.162.08:06:22.87#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.162.08:06:22.87#ibcon#[27=USB\r\n] 2006.162.08:06:22.87#ibcon#*before write, iclass 16, count 0 2006.162.08:06:22.87#ibcon#enter sib2, iclass 16, count 0 2006.162.08:06:22.87#ibcon#flushed, iclass 16, count 0 2006.162.08:06:22.87#ibcon#about to write, iclass 16, count 0 2006.162.08:06:22.87#ibcon#wrote, iclass 16, count 0 2006.162.08:06:22.87#ibcon#about to read 3, iclass 16, count 0 2006.162.08:06:22.90#ibcon#read 3, iclass 16, count 0 2006.162.08:06:22.90#ibcon#about to read 4, iclass 16, count 0 2006.162.08:06:22.90#ibcon#read 4, iclass 16, count 0 2006.162.08:06:22.90#ibcon#about to read 5, iclass 16, count 0 2006.162.08:06:22.90#ibcon#read 5, iclass 16, count 0 2006.162.08:06:22.90#ibcon#about to read 6, iclass 16, count 0 2006.162.08:06:22.90#ibcon#read 6, iclass 16, count 0 2006.162.08:06:22.90#ibcon#end of sib2, iclass 16, count 0 2006.162.08:06:22.90#ibcon#*after write, iclass 16, count 0 2006.162.08:06:22.90#ibcon#*before return 0, iclass 16, count 0 2006.162.08:06:22.90#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:06:22.90#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:06:22.90#ibcon#about to clear, iclass 16 cls_cnt 0 2006.162.08:06:22.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.162.08:06:22.90$vc4f8/vblo=4,712.99 2006.162.08:06:22.90#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.162.08:06:22.90#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.162.08:06:22.90#ibcon#ireg 17 cls_cnt 0 2006.162.08:06:22.90#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:06:22.90#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:06:22.90#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:06:22.90#ibcon#enter wrdev, iclass 18, count 0 2006.162.08:06:22.90#ibcon#first serial, iclass 18, count 0 2006.162.08:06:22.90#ibcon#enter sib2, iclass 18, count 0 2006.162.08:06:22.90#ibcon#flushed, iclass 18, count 0 2006.162.08:06:22.90#ibcon#about to write, iclass 18, count 0 2006.162.08:06:22.90#ibcon#wrote, iclass 18, count 0 2006.162.08:06:22.90#ibcon#about to read 3, iclass 18, count 0 2006.162.08:06:22.92#ibcon#read 3, iclass 18, count 0 2006.162.08:06:22.92#ibcon#about to read 4, iclass 18, count 0 2006.162.08:06:22.92#ibcon#read 4, iclass 18, count 0 2006.162.08:06:22.92#ibcon#about to read 5, iclass 18, count 0 2006.162.08:06:22.92#ibcon#read 5, iclass 18, count 0 2006.162.08:06:22.92#ibcon#about to read 6, iclass 18, count 0 2006.162.08:06:22.92#ibcon#read 6, iclass 18, count 0 2006.162.08:06:22.92#ibcon#end of sib2, iclass 18, count 0 2006.162.08:06:22.92#ibcon#*mode == 0, iclass 18, count 0 2006.162.08:06:22.92#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.162.08:06:22.92#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.08:06:22.92#ibcon#*before write, iclass 18, count 0 2006.162.08:06:22.92#ibcon#enter sib2, iclass 18, count 0 2006.162.08:06:22.92#ibcon#flushed, iclass 18, count 0 2006.162.08:06:22.92#ibcon#about to write, iclass 18, count 0 2006.162.08:06:22.92#ibcon#wrote, iclass 18, count 0 2006.162.08:06:22.92#ibcon#about to read 3, iclass 18, count 0 2006.162.08:06:22.96#ibcon#read 3, iclass 18, count 0 2006.162.08:06:22.96#ibcon#about to read 4, iclass 18, count 0 2006.162.08:06:22.96#ibcon#read 4, iclass 18, count 0 2006.162.08:06:22.96#ibcon#about to read 5, iclass 18, count 0 2006.162.08:06:22.96#ibcon#read 5, iclass 18, count 0 2006.162.08:06:22.96#ibcon#about to read 6, iclass 18, count 0 2006.162.08:06:22.96#ibcon#read 6, iclass 18, count 0 2006.162.08:06:22.96#ibcon#end of sib2, iclass 18, count 0 2006.162.08:06:22.96#ibcon#*after write, iclass 18, count 0 2006.162.08:06:22.96#ibcon#*before return 0, iclass 18, count 0 2006.162.08:06:22.96#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:06:22.96#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:06:22.96#ibcon#about to clear, iclass 18 cls_cnt 0 2006.162.08:06:22.96#ibcon#cleared, iclass 18 cls_cnt 0 2006.162.08:06:22.96$vc4f8/vb=4,4 2006.162.08:06:22.96#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.162.08:06:22.96#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.162.08:06:22.96#ibcon#ireg 11 cls_cnt 2 2006.162.08:06:22.96#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:06:23.03#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:06:23.03#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:06:23.03#ibcon#enter wrdev, iclass 20, count 2 2006.162.08:06:23.03#ibcon#first serial, iclass 20, count 2 2006.162.08:06:23.03#ibcon#enter sib2, iclass 20, count 2 2006.162.08:06:23.03#ibcon#flushed, iclass 20, count 2 2006.162.08:06:23.03#ibcon#about to write, iclass 20, count 2 2006.162.08:06:23.03#ibcon#wrote, iclass 20, count 2 2006.162.08:06:23.03#ibcon#about to read 3, iclass 20, count 2 2006.162.08:06:23.04#ibcon#read 3, iclass 20, count 2 2006.162.08:06:23.04#ibcon#about to read 4, iclass 20, count 2 2006.162.08:06:23.04#ibcon#read 4, iclass 20, count 2 2006.162.08:06:23.04#ibcon#about to read 5, iclass 20, count 2 2006.162.08:06:23.04#ibcon#read 5, iclass 20, count 2 2006.162.08:06:23.04#ibcon#about to read 6, iclass 20, count 2 2006.162.08:06:23.04#ibcon#read 6, iclass 20, count 2 2006.162.08:06:23.04#ibcon#end of sib2, iclass 20, count 2 2006.162.08:06:23.04#ibcon#*mode == 0, iclass 20, count 2 2006.162.08:06:23.04#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.162.08:06:23.04#ibcon#[27=AT04-04\r\n] 2006.162.08:06:23.04#ibcon#*before write, iclass 20, count 2 2006.162.08:06:23.04#ibcon#enter sib2, iclass 20, count 2 2006.162.08:06:23.04#ibcon#flushed, iclass 20, count 2 2006.162.08:06:23.04#ibcon#about to write, iclass 20, count 2 2006.162.08:06:23.04#ibcon#wrote, iclass 20, count 2 2006.162.08:06:23.04#ibcon#about to read 3, iclass 20, count 2 2006.162.08:06:23.07#ibcon#read 3, iclass 20, count 2 2006.162.08:06:23.07#ibcon#about to read 4, iclass 20, count 2 2006.162.08:06:23.07#ibcon#read 4, iclass 20, count 2 2006.162.08:06:23.07#ibcon#about to read 5, iclass 20, count 2 2006.162.08:06:23.07#ibcon#read 5, iclass 20, count 2 2006.162.08:06:23.07#ibcon#about to read 6, iclass 20, count 2 2006.162.08:06:23.07#ibcon#read 6, iclass 20, count 2 2006.162.08:06:23.07#ibcon#end of sib2, iclass 20, count 2 2006.162.08:06:23.07#ibcon#*after write, iclass 20, count 2 2006.162.08:06:23.07#ibcon#*before return 0, iclass 20, count 2 2006.162.08:06:23.07#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:06:23.07#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:06:23.07#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.162.08:06:23.07#ibcon#ireg 7 cls_cnt 0 2006.162.08:06:23.07#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:06:23.19#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:06:23.19#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:06:23.19#ibcon#enter wrdev, iclass 20, count 0 2006.162.08:06:23.19#ibcon#first serial, iclass 20, count 0 2006.162.08:06:23.19#ibcon#enter sib2, iclass 20, count 0 2006.162.08:06:23.19#ibcon#flushed, iclass 20, count 0 2006.162.08:06:23.19#ibcon#about to write, iclass 20, count 0 2006.162.08:06:23.19#ibcon#wrote, iclass 20, count 0 2006.162.08:06:23.19#ibcon#about to read 3, iclass 20, count 0 2006.162.08:06:23.21#ibcon#read 3, iclass 20, count 0 2006.162.08:06:23.21#ibcon#about to read 4, iclass 20, count 0 2006.162.08:06:23.21#ibcon#read 4, iclass 20, count 0 2006.162.08:06:23.21#ibcon#about to read 5, iclass 20, count 0 2006.162.08:06:23.21#ibcon#read 5, iclass 20, count 0 2006.162.08:06:23.21#ibcon#about to read 6, iclass 20, count 0 2006.162.08:06:23.21#ibcon#read 6, iclass 20, count 0 2006.162.08:06:23.21#ibcon#end of sib2, iclass 20, count 0 2006.162.08:06:23.21#ibcon#*mode == 0, iclass 20, count 0 2006.162.08:06:23.21#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.08:06:23.21#ibcon#[27=USB\r\n] 2006.162.08:06:23.21#ibcon#*before write, iclass 20, count 0 2006.162.08:06:23.21#ibcon#enter sib2, iclass 20, count 0 2006.162.08:06:23.21#ibcon#flushed, iclass 20, count 0 2006.162.08:06:23.21#ibcon#about to write, iclass 20, count 0 2006.162.08:06:23.21#ibcon#wrote, iclass 20, count 0 2006.162.08:06:23.21#ibcon#about to read 3, iclass 20, count 0 2006.162.08:06:23.24#ibcon#read 3, iclass 20, count 0 2006.162.08:06:23.24#ibcon#about to read 4, iclass 20, count 0 2006.162.08:06:23.24#ibcon#read 4, iclass 20, count 0 2006.162.08:06:23.24#ibcon#about to read 5, iclass 20, count 0 2006.162.08:06:23.24#ibcon#read 5, iclass 20, count 0 2006.162.08:06:23.24#ibcon#about to read 6, iclass 20, count 0 2006.162.08:06:23.24#ibcon#read 6, iclass 20, count 0 2006.162.08:06:23.24#ibcon#end of sib2, iclass 20, count 0 2006.162.08:06:23.24#ibcon#*after write, iclass 20, count 0 2006.162.08:06:23.24#ibcon#*before return 0, iclass 20, count 0 2006.162.08:06:23.24#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:06:23.24#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:06:23.24#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.08:06:23.24#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.08:06:23.24$vc4f8/vblo=5,744.99 2006.162.08:06:23.24#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.162.08:06:23.24#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.162.08:06:23.24#ibcon#ireg 17 cls_cnt 0 2006.162.08:06:23.24#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:06:23.24#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:06:23.24#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:06:23.24#ibcon#enter wrdev, iclass 22, count 0 2006.162.08:06:23.24#ibcon#first serial, iclass 22, count 0 2006.162.08:06:23.24#ibcon#enter sib2, iclass 22, count 0 2006.162.08:06:23.24#ibcon#flushed, iclass 22, count 0 2006.162.08:06:23.24#ibcon#about to write, iclass 22, count 0 2006.162.08:06:23.24#ibcon#wrote, iclass 22, count 0 2006.162.08:06:23.24#ibcon#about to read 3, iclass 22, count 0 2006.162.08:06:23.26#ibcon#read 3, iclass 22, count 0 2006.162.08:06:23.26#ibcon#about to read 4, iclass 22, count 0 2006.162.08:06:23.26#ibcon#read 4, iclass 22, count 0 2006.162.08:06:23.26#ibcon#about to read 5, iclass 22, count 0 2006.162.08:06:23.26#ibcon#read 5, iclass 22, count 0 2006.162.08:06:23.26#ibcon#about to read 6, iclass 22, count 0 2006.162.08:06:23.26#ibcon#read 6, iclass 22, count 0 2006.162.08:06:23.26#ibcon#end of sib2, iclass 22, count 0 2006.162.08:06:23.26#ibcon#*mode == 0, iclass 22, count 0 2006.162.08:06:23.26#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.08:06:23.26#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.08:06:23.26#ibcon#*before write, iclass 22, count 0 2006.162.08:06:23.26#ibcon#enter sib2, iclass 22, count 0 2006.162.08:06:23.26#ibcon#flushed, iclass 22, count 0 2006.162.08:06:23.26#ibcon#about to write, iclass 22, count 0 2006.162.08:06:23.26#ibcon#wrote, iclass 22, count 0 2006.162.08:06:23.26#ibcon#about to read 3, iclass 22, count 0 2006.162.08:06:23.30#ibcon#read 3, iclass 22, count 0 2006.162.08:06:23.30#ibcon#about to read 4, iclass 22, count 0 2006.162.08:06:23.30#ibcon#read 4, iclass 22, count 0 2006.162.08:06:23.30#ibcon#about to read 5, iclass 22, count 0 2006.162.08:06:23.30#ibcon#read 5, iclass 22, count 0 2006.162.08:06:23.30#ibcon#about to read 6, iclass 22, count 0 2006.162.08:06:23.30#ibcon#read 6, iclass 22, count 0 2006.162.08:06:23.30#ibcon#end of sib2, iclass 22, count 0 2006.162.08:06:23.30#ibcon#*after write, iclass 22, count 0 2006.162.08:06:23.30#ibcon#*before return 0, iclass 22, count 0 2006.162.08:06:23.30#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:06:23.30#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:06:23.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.08:06:23.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.08:06:23.30$vc4f8/vb=5,4 2006.162.08:06:23.30#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.162.08:06:23.30#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.162.08:06:23.30#ibcon#ireg 11 cls_cnt 2 2006.162.08:06:23.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:06:23.36#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:06:23.36#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:06:23.36#ibcon#enter wrdev, iclass 24, count 2 2006.162.08:06:23.36#ibcon#first serial, iclass 24, count 2 2006.162.08:06:23.36#ibcon#enter sib2, iclass 24, count 2 2006.162.08:06:23.36#ibcon#flushed, iclass 24, count 2 2006.162.08:06:23.36#ibcon#about to write, iclass 24, count 2 2006.162.08:06:23.36#ibcon#wrote, iclass 24, count 2 2006.162.08:06:23.36#ibcon#about to read 3, iclass 24, count 2 2006.162.08:06:23.38#ibcon#read 3, iclass 24, count 2 2006.162.08:06:23.38#ibcon#about to read 4, iclass 24, count 2 2006.162.08:06:23.38#ibcon#read 4, iclass 24, count 2 2006.162.08:06:23.38#ibcon#about to read 5, iclass 24, count 2 2006.162.08:06:23.38#ibcon#read 5, iclass 24, count 2 2006.162.08:06:23.38#ibcon#about to read 6, iclass 24, count 2 2006.162.08:06:23.38#ibcon#read 6, iclass 24, count 2 2006.162.08:06:23.38#ibcon#end of sib2, iclass 24, count 2 2006.162.08:06:23.38#ibcon#*mode == 0, iclass 24, count 2 2006.162.08:06:23.38#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.162.08:06:23.38#ibcon#[27=AT05-04\r\n] 2006.162.08:06:23.38#ibcon#*before write, iclass 24, count 2 2006.162.08:06:23.38#ibcon#enter sib2, iclass 24, count 2 2006.162.08:06:23.38#ibcon#flushed, iclass 24, count 2 2006.162.08:06:23.38#ibcon#about to write, iclass 24, count 2 2006.162.08:06:23.38#ibcon#wrote, iclass 24, count 2 2006.162.08:06:23.38#ibcon#about to read 3, iclass 24, count 2 2006.162.08:06:23.41#ibcon#read 3, iclass 24, count 2 2006.162.08:06:23.41#ibcon#about to read 4, iclass 24, count 2 2006.162.08:06:23.41#ibcon#read 4, iclass 24, count 2 2006.162.08:06:23.41#ibcon#about to read 5, iclass 24, count 2 2006.162.08:06:23.41#ibcon#read 5, iclass 24, count 2 2006.162.08:06:23.41#ibcon#about to read 6, iclass 24, count 2 2006.162.08:06:23.41#ibcon#read 6, iclass 24, count 2 2006.162.08:06:23.41#ibcon#end of sib2, iclass 24, count 2 2006.162.08:06:23.41#ibcon#*after write, iclass 24, count 2 2006.162.08:06:23.41#ibcon#*before return 0, iclass 24, count 2 2006.162.08:06:23.41#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:06:23.41#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:06:23.41#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.162.08:06:23.41#ibcon#ireg 7 cls_cnt 0 2006.162.08:06:23.41#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:06:23.53#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:06:23.53#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:06:23.53#ibcon#enter wrdev, iclass 24, count 0 2006.162.08:06:23.53#ibcon#first serial, iclass 24, count 0 2006.162.08:06:23.53#ibcon#enter sib2, iclass 24, count 0 2006.162.08:06:23.53#ibcon#flushed, iclass 24, count 0 2006.162.08:06:23.53#ibcon#about to write, iclass 24, count 0 2006.162.08:06:23.53#ibcon#wrote, iclass 24, count 0 2006.162.08:06:23.53#ibcon#about to read 3, iclass 24, count 0 2006.162.08:06:23.55#ibcon#read 3, iclass 24, count 0 2006.162.08:06:23.55#ibcon#about to read 4, iclass 24, count 0 2006.162.08:06:23.55#ibcon#read 4, iclass 24, count 0 2006.162.08:06:23.55#ibcon#about to read 5, iclass 24, count 0 2006.162.08:06:23.55#ibcon#read 5, iclass 24, count 0 2006.162.08:06:23.55#ibcon#about to read 6, iclass 24, count 0 2006.162.08:06:23.55#ibcon#read 6, iclass 24, count 0 2006.162.08:06:23.55#ibcon#end of sib2, iclass 24, count 0 2006.162.08:06:23.55#ibcon#*mode == 0, iclass 24, count 0 2006.162.08:06:23.55#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.08:06:23.55#ibcon#[27=USB\r\n] 2006.162.08:06:23.55#ibcon#*before write, iclass 24, count 0 2006.162.08:06:23.55#ibcon#enter sib2, iclass 24, count 0 2006.162.08:06:23.55#ibcon#flushed, iclass 24, count 0 2006.162.08:06:23.55#ibcon#about to write, iclass 24, count 0 2006.162.08:06:23.55#ibcon#wrote, iclass 24, count 0 2006.162.08:06:23.55#ibcon#about to read 3, iclass 24, count 0 2006.162.08:06:23.58#ibcon#read 3, iclass 24, count 0 2006.162.08:06:23.58#ibcon#about to read 4, iclass 24, count 0 2006.162.08:06:23.58#ibcon#read 4, iclass 24, count 0 2006.162.08:06:23.58#ibcon#about to read 5, iclass 24, count 0 2006.162.08:06:23.58#ibcon#read 5, iclass 24, count 0 2006.162.08:06:23.58#ibcon#about to read 6, iclass 24, count 0 2006.162.08:06:23.58#ibcon#read 6, iclass 24, count 0 2006.162.08:06:23.58#ibcon#end of sib2, iclass 24, count 0 2006.162.08:06:23.58#ibcon#*after write, iclass 24, count 0 2006.162.08:06:23.58#ibcon#*before return 0, iclass 24, count 0 2006.162.08:06:23.58#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:06:23.58#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:06:23.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.08:06:23.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.08:06:23.58$vc4f8/vblo=6,752.99 2006.162.08:06:23.58#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.162.08:06:23.58#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.162.08:06:23.58#ibcon#ireg 17 cls_cnt 0 2006.162.08:06:23.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:06:23.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:06:23.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:06:23.58#ibcon#enter wrdev, iclass 26, count 0 2006.162.08:06:23.58#ibcon#first serial, iclass 26, count 0 2006.162.08:06:23.58#ibcon#enter sib2, iclass 26, count 0 2006.162.08:06:23.58#ibcon#flushed, iclass 26, count 0 2006.162.08:06:23.58#ibcon#about to write, iclass 26, count 0 2006.162.08:06:23.58#ibcon#wrote, iclass 26, count 0 2006.162.08:06:23.58#ibcon#about to read 3, iclass 26, count 0 2006.162.08:06:23.60#ibcon#read 3, iclass 26, count 0 2006.162.08:06:23.60#ibcon#about to read 4, iclass 26, count 0 2006.162.08:06:23.60#ibcon#read 4, iclass 26, count 0 2006.162.08:06:23.60#ibcon#about to read 5, iclass 26, count 0 2006.162.08:06:23.60#ibcon#read 5, iclass 26, count 0 2006.162.08:06:23.60#ibcon#about to read 6, iclass 26, count 0 2006.162.08:06:23.60#ibcon#read 6, iclass 26, count 0 2006.162.08:06:23.60#ibcon#end of sib2, iclass 26, count 0 2006.162.08:06:23.60#ibcon#*mode == 0, iclass 26, count 0 2006.162.08:06:23.60#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.162.08:06:23.60#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.08:06:23.60#ibcon#*before write, iclass 26, count 0 2006.162.08:06:23.60#ibcon#enter sib2, iclass 26, count 0 2006.162.08:06:23.60#ibcon#flushed, iclass 26, count 0 2006.162.08:06:23.60#ibcon#about to write, iclass 26, count 0 2006.162.08:06:23.60#ibcon#wrote, iclass 26, count 0 2006.162.08:06:23.60#ibcon#about to read 3, iclass 26, count 0 2006.162.08:06:23.64#ibcon#read 3, iclass 26, count 0 2006.162.08:06:23.64#ibcon#about to read 4, iclass 26, count 0 2006.162.08:06:23.64#ibcon#read 4, iclass 26, count 0 2006.162.08:06:23.64#ibcon#about to read 5, iclass 26, count 0 2006.162.08:06:23.64#ibcon#read 5, iclass 26, count 0 2006.162.08:06:23.64#ibcon#about to read 6, iclass 26, count 0 2006.162.08:06:23.64#ibcon#read 6, iclass 26, count 0 2006.162.08:06:23.64#ibcon#end of sib2, iclass 26, count 0 2006.162.08:06:23.64#ibcon#*after write, iclass 26, count 0 2006.162.08:06:23.64#ibcon#*before return 0, iclass 26, count 0 2006.162.08:06:23.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:06:23.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:06:23.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.162.08:06:23.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.162.08:06:23.64$vc4f8/vb=6,4 2006.162.08:06:23.64#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.162.08:06:23.64#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.162.08:06:23.64#ibcon#ireg 11 cls_cnt 2 2006.162.08:06:23.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:06:23.70#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:06:23.70#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:06:23.70#ibcon#enter wrdev, iclass 28, count 2 2006.162.08:06:23.70#ibcon#first serial, iclass 28, count 2 2006.162.08:06:23.70#ibcon#enter sib2, iclass 28, count 2 2006.162.08:06:23.70#ibcon#flushed, iclass 28, count 2 2006.162.08:06:23.70#ibcon#about to write, iclass 28, count 2 2006.162.08:06:23.70#ibcon#wrote, iclass 28, count 2 2006.162.08:06:23.70#ibcon#about to read 3, iclass 28, count 2 2006.162.08:06:23.72#ibcon#read 3, iclass 28, count 2 2006.162.08:06:23.72#ibcon#about to read 4, iclass 28, count 2 2006.162.08:06:23.72#ibcon#read 4, iclass 28, count 2 2006.162.08:06:23.72#ibcon#about to read 5, iclass 28, count 2 2006.162.08:06:23.72#ibcon#read 5, iclass 28, count 2 2006.162.08:06:23.72#ibcon#about to read 6, iclass 28, count 2 2006.162.08:06:23.72#ibcon#read 6, iclass 28, count 2 2006.162.08:06:23.72#ibcon#end of sib2, iclass 28, count 2 2006.162.08:06:23.72#ibcon#*mode == 0, iclass 28, count 2 2006.162.08:06:23.72#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.162.08:06:23.72#ibcon#[27=AT06-04\r\n] 2006.162.08:06:23.72#ibcon#*before write, iclass 28, count 2 2006.162.08:06:23.72#ibcon#enter sib2, iclass 28, count 2 2006.162.08:06:23.72#ibcon#flushed, iclass 28, count 2 2006.162.08:06:23.72#ibcon#about to write, iclass 28, count 2 2006.162.08:06:23.72#ibcon#wrote, iclass 28, count 2 2006.162.08:06:23.72#ibcon#about to read 3, iclass 28, count 2 2006.162.08:06:23.75#ibcon#read 3, iclass 28, count 2 2006.162.08:06:23.75#ibcon#about to read 4, iclass 28, count 2 2006.162.08:06:23.75#ibcon#read 4, iclass 28, count 2 2006.162.08:06:23.75#ibcon#about to read 5, iclass 28, count 2 2006.162.08:06:23.75#ibcon#read 5, iclass 28, count 2 2006.162.08:06:23.75#ibcon#about to read 6, iclass 28, count 2 2006.162.08:06:23.75#ibcon#read 6, iclass 28, count 2 2006.162.08:06:23.75#ibcon#end of sib2, iclass 28, count 2 2006.162.08:06:23.75#ibcon#*after write, iclass 28, count 2 2006.162.08:06:23.75#ibcon#*before return 0, iclass 28, count 2 2006.162.08:06:23.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:06:23.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:06:23.75#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.162.08:06:23.75#ibcon#ireg 7 cls_cnt 0 2006.162.08:06:23.75#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:06:23.87#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:06:23.87#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:06:23.87#ibcon#enter wrdev, iclass 28, count 0 2006.162.08:06:23.87#ibcon#first serial, iclass 28, count 0 2006.162.08:06:23.87#ibcon#enter sib2, iclass 28, count 0 2006.162.08:06:23.87#ibcon#flushed, iclass 28, count 0 2006.162.08:06:23.87#ibcon#about to write, iclass 28, count 0 2006.162.08:06:23.87#ibcon#wrote, iclass 28, count 0 2006.162.08:06:23.87#ibcon#about to read 3, iclass 28, count 0 2006.162.08:06:23.89#ibcon#read 3, iclass 28, count 0 2006.162.08:06:23.89#ibcon#about to read 4, iclass 28, count 0 2006.162.08:06:23.89#ibcon#read 4, iclass 28, count 0 2006.162.08:06:23.89#ibcon#about to read 5, iclass 28, count 0 2006.162.08:06:23.89#ibcon#read 5, iclass 28, count 0 2006.162.08:06:23.89#ibcon#about to read 6, iclass 28, count 0 2006.162.08:06:23.89#ibcon#read 6, iclass 28, count 0 2006.162.08:06:23.89#ibcon#end of sib2, iclass 28, count 0 2006.162.08:06:23.89#ibcon#*mode == 0, iclass 28, count 0 2006.162.08:06:23.89#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.162.08:06:23.89#ibcon#[27=USB\r\n] 2006.162.08:06:23.89#ibcon#*before write, iclass 28, count 0 2006.162.08:06:23.89#ibcon#enter sib2, iclass 28, count 0 2006.162.08:06:23.89#ibcon#flushed, iclass 28, count 0 2006.162.08:06:23.89#ibcon#about to write, iclass 28, count 0 2006.162.08:06:23.89#ibcon#wrote, iclass 28, count 0 2006.162.08:06:23.89#ibcon#about to read 3, iclass 28, count 0 2006.162.08:06:23.92#ibcon#read 3, iclass 28, count 0 2006.162.08:06:23.92#ibcon#about to read 4, iclass 28, count 0 2006.162.08:06:23.92#ibcon#read 4, iclass 28, count 0 2006.162.08:06:23.92#ibcon#about to read 5, iclass 28, count 0 2006.162.08:06:23.92#ibcon#read 5, iclass 28, count 0 2006.162.08:06:23.92#ibcon#about to read 6, iclass 28, count 0 2006.162.08:06:23.92#ibcon#read 6, iclass 28, count 0 2006.162.08:06:23.92#ibcon#end of sib2, iclass 28, count 0 2006.162.08:06:23.92#ibcon#*after write, iclass 28, count 0 2006.162.08:06:23.92#ibcon#*before return 0, iclass 28, count 0 2006.162.08:06:23.92#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:06:23.92#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:06:23.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.162.08:06:23.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.162.08:06:23.92$vc4f8/vabw=wide 2006.162.08:06:23.92#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.162.08:06:23.92#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.162.08:06:23.92#ibcon#ireg 8 cls_cnt 0 2006.162.08:06:23.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:06:23.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:06:23.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:06:23.92#ibcon#enter wrdev, iclass 30, count 0 2006.162.08:06:23.92#ibcon#first serial, iclass 30, count 0 2006.162.08:06:23.92#ibcon#enter sib2, iclass 30, count 0 2006.162.08:06:23.92#ibcon#flushed, iclass 30, count 0 2006.162.08:06:23.92#ibcon#about to write, iclass 30, count 0 2006.162.08:06:23.92#ibcon#wrote, iclass 30, count 0 2006.162.08:06:23.92#ibcon#about to read 3, iclass 30, count 0 2006.162.08:06:23.94#ibcon#read 3, iclass 30, count 0 2006.162.08:06:23.94#ibcon#about to read 4, iclass 30, count 0 2006.162.08:06:23.94#ibcon#read 4, iclass 30, count 0 2006.162.08:06:23.94#ibcon#about to read 5, iclass 30, count 0 2006.162.08:06:23.94#ibcon#read 5, iclass 30, count 0 2006.162.08:06:23.94#ibcon#about to read 6, iclass 30, count 0 2006.162.08:06:23.94#ibcon#read 6, iclass 30, count 0 2006.162.08:06:23.94#ibcon#end of sib2, iclass 30, count 0 2006.162.08:06:23.94#ibcon#*mode == 0, iclass 30, count 0 2006.162.08:06:23.94#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.162.08:06:23.94#ibcon#[25=BW32\r\n] 2006.162.08:06:23.94#ibcon#*before write, iclass 30, count 0 2006.162.08:06:23.94#ibcon#enter sib2, iclass 30, count 0 2006.162.08:06:23.94#ibcon#flushed, iclass 30, count 0 2006.162.08:06:23.94#ibcon#about to write, iclass 30, count 0 2006.162.08:06:23.94#ibcon#wrote, iclass 30, count 0 2006.162.08:06:23.94#ibcon#about to read 3, iclass 30, count 0 2006.162.08:06:23.97#ibcon#read 3, iclass 30, count 0 2006.162.08:06:23.97#ibcon#about to read 4, iclass 30, count 0 2006.162.08:06:23.97#ibcon#read 4, iclass 30, count 0 2006.162.08:06:23.97#ibcon#about to read 5, iclass 30, count 0 2006.162.08:06:23.97#ibcon#read 5, iclass 30, count 0 2006.162.08:06:23.97#ibcon#about to read 6, iclass 30, count 0 2006.162.08:06:23.97#ibcon#read 6, iclass 30, count 0 2006.162.08:06:23.97#ibcon#end of sib2, iclass 30, count 0 2006.162.08:06:23.97#ibcon#*after write, iclass 30, count 0 2006.162.08:06:23.97#ibcon#*before return 0, iclass 30, count 0 2006.162.08:06:23.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:06:23.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:06:23.97#ibcon#about to clear, iclass 30 cls_cnt 0 2006.162.08:06:23.97#ibcon#cleared, iclass 30 cls_cnt 0 2006.162.08:06:23.97$vc4f8/vbbw=wide 2006.162.08:06:23.97#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.162.08:06:23.97#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.162.08:06:23.97#ibcon#ireg 8 cls_cnt 0 2006.162.08:06:23.97#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:06:24.04#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:06:24.04#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:06:24.04#ibcon#enter wrdev, iclass 32, count 0 2006.162.08:06:24.04#ibcon#first serial, iclass 32, count 0 2006.162.08:06:24.04#ibcon#enter sib2, iclass 32, count 0 2006.162.08:06:24.04#ibcon#flushed, iclass 32, count 0 2006.162.08:06:24.04#ibcon#about to write, iclass 32, count 0 2006.162.08:06:24.04#ibcon#wrote, iclass 32, count 0 2006.162.08:06:24.04#ibcon#about to read 3, iclass 32, count 0 2006.162.08:06:24.06#ibcon#read 3, iclass 32, count 0 2006.162.08:06:24.06#ibcon#about to read 4, iclass 32, count 0 2006.162.08:06:24.06#ibcon#read 4, iclass 32, count 0 2006.162.08:06:24.06#ibcon#about to read 5, iclass 32, count 0 2006.162.08:06:24.06#ibcon#read 5, iclass 32, count 0 2006.162.08:06:24.06#ibcon#about to read 6, iclass 32, count 0 2006.162.08:06:24.06#ibcon#read 6, iclass 32, count 0 2006.162.08:06:24.06#ibcon#end of sib2, iclass 32, count 0 2006.162.08:06:24.06#ibcon#*mode == 0, iclass 32, count 0 2006.162.08:06:24.06#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.162.08:06:24.06#ibcon#[27=BW32\r\n] 2006.162.08:06:24.06#ibcon#*before write, iclass 32, count 0 2006.162.08:06:24.06#ibcon#enter sib2, iclass 32, count 0 2006.162.08:06:24.06#ibcon#flushed, iclass 32, count 0 2006.162.08:06:24.06#ibcon#about to write, iclass 32, count 0 2006.162.08:06:24.06#ibcon#wrote, iclass 32, count 0 2006.162.08:06:24.06#ibcon#about to read 3, iclass 32, count 0 2006.162.08:06:24.09#ibcon#read 3, iclass 32, count 0 2006.162.08:06:24.09#ibcon#about to read 4, iclass 32, count 0 2006.162.08:06:24.09#ibcon#read 4, iclass 32, count 0 2006.162.08:06:24.09#ibcon#about to read 5, iclass 32, count 0 2006.162.08:06:24.09#ibcon#read 5, iclass 32, count 0 2006.162.08:06:24.09#ibcon#about to read 6, iclass 32, count 0 2006.162.08:06:24.09#ibcon#read 6, iclass 32, count 0 2006.162.08:06:24.09#ibcon#end of sib2, iclass 32, count 0 2006.162.08:06:24.09#ibcon#*after write, iclass 32, count 0 2006.162.08:06:24.09#ibcon#*before return 0, iclass 32, count 0 2006.162.08:06:24.09#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:06:24.09#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:06:24.09#ibcon#about to clear, iclass 32 cls_cnt 0 2006.162.08:06:24.09#ibcon#cleared, iclass 32 cls_cnt 0 2006.162.08:06:24.09$4f8m12a/ifd4f 2006.162.08:06:24.09$ifd4f/lo= 2006.162.08:06:24.09$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.08:06:24.09$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.08:06:24.09$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.08:06:24.09$ifd4f/patch= 2006.162.08:06:24.09$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.08:06:24.09$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.08:06:24.09$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.08:06:24.09$4f8m12a/"form=m,16.000,1:2 2006.162.08:06:24.09$4f8m12a/"tpicd 2006.162.08:06:24.09$4f8m12a/echo=off 2006.162.08:06:24.09$4f8m12a/xlog=off 2006.162.08:06:24.09:!2006.162.08:06:50 2006.162.08:06:37.13#trakl#Source acquired 2006.162.08:06:38.13#flagr#flagr/antenna,acquired 2006.162.08:06:50.00:preob 2006.162.08:06:51.13/onsource/TRACKING 2006.162.08:06:51.13:!2006.162.08:07:00 2006.162.08:07:00.00:data_valid=on 2006.162.08:07:00.00:midob 2006.162.08:07:00.13/onsource/TRACKING 2006.162.08:07:00.13/wx/17.85,1007.1,100 2006.162.08:07:00.28/cable/+6.5355E-03 2006.162.08:07:01.37/va/01,08,usb,yes,35,37 2006.162.08:07:01.37/va/02,07,usb,yes,35,37 2006.162.08:07:01.37/va/03,06,usb,yes,37,37 2006.162.08:07:01.37/va/04,07,usb,yes,36,39 2006.162.08:07:01.37/va/05,07,usb,yes,38,41 2006.162.08:07:01.37/va/06,06,usb,yes,38,37 2006.162.08:07:01.37/va/07,06,usb,yes,38,38 2006.162.08:07:01.37/va/08,07,usb,yes,36,36 2006.162.08:07:01.60/valo/01,532.99,yes,locked 2006.162.08:07:01.60/valo/02,572.99,yes,locked 2006.162.08:07:01.60/valo/03,672.99,yes,locked 2006.162.08:07:01.60/valo/04,832.99,yes,locked 2006.162.08:07:01.60/valo/05,652.99,yes,locked 2006.162.08:07:01.60/valo/06,772.99,yes,locked 2006.162.08:07:01.60/valo/07,832.99,yes,locked 2006.162.08:07:01.60/valo/08,852.99,yes,locked 2006.162.08:07:02.69/vb/01,04,usb,yes,29,27 2006.162.08:07:02.69/vb/02,04,usb,yes,30,32 2006.162.08:07:02.69/vb/03,04,usb,yes,27,30 2006.162.08:07:02.69/vb/04,04,usb,yes,28,28 2006.162.08:07:02.69/vb/05,04,usb,yes,26,30 2006.162.08:07:02.69/vb/06,04,usb,yes,27,30 2006.162.08:07:02.69/vb/07,04,usb,yes,29,29 2006.162.08:07:02.69/vb/08,04,usb,yes,27,30 2006.162.08:07:02.92/vblo/01,632.99,yes,locked 2006.162.08:07:02.92/vblo/02,640.99,yes,locked 2006.162.08:07:02.92/vblo/03,656.99,yes,locked 2006.162.08:07:02.92/vblo/04,712.99,yes,locked 2006.162.08:07:02.92/vblo/05,744.99,yes,locked 2006.162.08:07:02.92/vblo/06,752.99,yes,locked 2006.162.08:07:02.92/vblo/07,734.99,yes,locked 2006.162.08:07:02.92/vblo/08,744.99,yes,locked 2006.162.08:07:03.07/vabw/8 2006.162.08:07:03.22/vbbw/8 2006.162.08:07:03.31/xfe/off,on,15.0 2006.162.08:07:03.68/ifatt/23,28,28,28 2006.162.08:07:04.08/fmout-gps/S +4.49E-07 2006.162.08:07:04.16:!2006.162.08:08:00 2006.162.08:08:00.00:data_valid=off 2006.162.08:08:00.01:postob 2006.162.08:08:00.24/cable/+6.5355E-03 2006.162.08:08:00.25/wx/17.85,1007.1,100 2006.162.08:08:01.08/fmout-gps/S +4.49E-07 2006.162.08:08:01.08:scan_name=162-0808,k06162,60 2006.162.08:08:01.09:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.162.08:08:01.13#flagr#flagr/antenna,new-source 2006.162.08:08:02.13:checkk5 2006.162.08:08:02.56/chk_autoobs//k5ts1/ autoobs is running! 2006.162.08:08:02.97/chk_autoobs//k5ts2/ autoobs is running! 2006.162.08:08:03.39/chk_autoobs//k5ts3/ autoobs is running! 2006.162.08:08:03.82/chk_autoobs//k5ts4/ autoobs is running! 2006.162.08:08:04.21/chk_obsdata//k5ts1/T1620807??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:08:04.61/chk_obsdata//k5ts2/T1620807??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:08:05.16/chk_obsdata//k5ts3/T1620807??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:08:05.78/chk_obsdata//k5ts4/T1620807??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:08:06.54/k5log//k5ts1_log_newline 2006.162.08:08:07.34/k5log//k5ts2_log_newline 2006.162.08:08:08.07/k5log//k5ts3_log_newline 2006.162.08:08:09.00/k5log//k5ts4_log_newline 2006.162.08:08:09.02/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.08:08:09.02:4f8m12a=2 2006.162.08:08:09.02$4f8m12a/echo=on 2006.162.08:08:09.02$4f8m12a/pcalon 2006.162.08:08:09.02$pcalon/"no phase cal control is implemented here 2006.162.08:08:09.02$4f8m12a/"tpicd=stop 2006.162.08:08:09.02$4f8m12a/vc4f8 2006.162.08:08:09.02$vc4f8/valo=1,532.99 2006.162.08:08:09.03#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.162.08:08:09.03#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.162.08:08:09.03#ibcon#ireg 17 cls_cnt 0 2006.162.08:08:09.03#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:08:09.03#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:08:09.03#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:08:09.03#ibcon#enter wrdev, iclass 34, count 0 2006.162.08:08:09.03#ibcon#first serial, iclass 34, count 0 2006.162.08:08:09.03#ibcon#enter sib2, iclass 34, count 0 2006.162.08:08:09.03#ibcon#flushed, iclass 34, count 0 2006.162.08:08:09.03#ibcon#about to write, iclass 34, count 0 2006.162.08:08:09.03#ibcon#wrote, iclass 34, count 0 2006.162.08:08:09.03#ibcon#about to read 3, iclass 34, count 0 2006.162.08:08:09.07#ibcon#read 3, iclass 34, count 0 2006.162.08:08:09.07#ibcon#about to read 4, iclass 34, count 0 2006.162.08:08:09.07#ibcon#read 4, iclass 34, count 0 2006.162.08:08:09.07#ibcon#about to read 5, iclass 34, count 0 2006.162.08:08:09.07#ibcon#read 5, iclass 34, count 0 2006.162.08:08:09.07#ibcon#about to read 6, iclass 34, count 0 2006.162.08:08:09.07#ibcon#read 6, iclass 34, count 0 2006.162.08:08:09.07#ibcon#end of sib2, iclass 34, count 0 2006.162.08:08:09.07#ibcon#*mode == 0, iclass 34, count 0 2006.162.08:08:09.07#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.162.08:08:09.07#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.08:08:09.07#ibcon#*before write, iclass 34, count 0 2006.162.08:08:09.07#ibcon#enter sib2, iclass 34, count 0 2006.162.08:08:09.07#ibcon#flushed, iclass 34, count 0 2006.162.08:08:09.07#ibcon#about to write, iclass 34, count 0 2006.162.08:08:09.07#ibcon#wrote, iclass 34, count 0 2006.162.08:08:09.07#ibcon#about to read 3, iclass 34, count 0 2006.162.08:08:09.11#ibcon#read 3, iclass 34, count 0 2006.162.08:08:09.11#ibcon#about to read 4, iclass 34, count 0 2006.162.08:08:09.11#ibcon#read 4, iclass 34, count 0 2006.162.08:08:09.11#ibcon#about to read 5, iclass 34, count 0 2006.162.08:08:09.11#ibcon#read 5, iclass 34, count 0 2006.162.08:08:09.11#ibcon#about to read 6, iclass 34, count 0 2006.162.08:08:09.11#ibcon#read 6, iclass 34, count 0 2006.162.08:08:09.11#ibcon#end of sib2, iclass 34, count 0 2006.162.08:08:09.11#ibcon#*after write, iclass 34, count 0 2006.162.08:08:09.11#ibcon#*before return 0, iclass 34, count 0 2006.162.08:08:09.11#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:08:09.11#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:08:09.11#ibcon#about to clear, iclass 34 cls_cnt 0 2006.162.08:08:09.11#ibcon#cleared, iclass 34 cls_cnt 0 2006.162.08:08:09.11$vc4f8/va=1,8 2006.162.08:08:09.11#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.162.08:08:09.11#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.162.08:08:09.11#ibcon#ireg 11 cls_cnt 2 2006.162.08:08:09.11#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:08:09.11#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:08:09.11#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:08:09.11#ibcon#enter wrdev, iclass 36, count 2 2006.162.08:08:09.11#ibcon#first serial, iclass 36, count 2 2006.162.08:08:09.11#ibcon#enter sib2, iclass 36, count 2 2006.162.08:08:09.11#ibcon#flushed, iclass 36, count 2 2006.162.08:08:09.11#ibcon#about to write, iclass 36, count 2 2006.162.08:08:09.11#ibcon#wrote, iclass 36, count 2 2006.162.08:08:09.11#ibcon#about to read 3, iclass 36, count 2 2006.162.08:08:09.13#ibcon#read 3, iclass 36, count 2 2006.162.08:08:09.13#ibcon#about to read 4, iclass 36, count 2 2006.162.08:08:09.13#ibcon#read 4, iclass 36, count 2 2006.162.08:08:09.13#ibcon#about to read 5, iclass 36, count 2 2006.162.08:08:09.13#ibcon#read 5, iclass 36, count 2 2006.162.08:08:09.13#ibcon#about to read 6, iclass 36, count 2 2006.162.08:08:09.13#ibcon#read 6, iclass 36, count 2 2006.162.08:08:09.13#ibcon#end of sib2, iclass 36, count 2 2006.162.08:08:09.13#ibcon#*mode == 0, iclass 36, count 2 2006.162.08:08:09.13#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.162.08:08:09.13#ibcon#[25=AT01-08\r\n] 2006.162.08:08:09.13#ibcon#*before write, iclass 36, count 2 2006.162.08:08:09.13#ibcon#enter sib2, iclass 36, count 2 2006.162.08:08:09.13#ibcon#flushed, iclass 36, count 2 2006.162.08:08:09.13#ibcon#about to write, iclass 36, count 2 2006.162.08:08:09.13#ibcon#wrote, iclass 36, count 2 2006.162.08:08:09.13#ibcon#about to read 3, iclass 36, count 2 2006.162.08:08:09.16#ibcon#read 3, iclass 36, count 2 2006.162.08:08:09.16#ibcon#about to read 4, iclass 36, count 2 2006.162.08:08:09.16#ibcon#read 4, iclass 36, count 2 2006.162.08:08:09.16#ibcon#about to read 5, iclass 36, count 2 2006.162.08:08:09.16#ibcon#read 5, iclass 36, count 2 2006.162.08:08:09.16#ibcon#about to read 6, iclass 36, count 2 2006.162.08:08:09.16#ibcon#read 6, iclass 36, count 2 2006.162.08:08:09.16#ibcon#end of sib2, iclass 36, count 2 2006.162.08:08:09.16#ibcon#*after write, iclass 36, count 2 2006.162.08:08:09.16#ibcon#*before return 0, iclass 36, count 2 2006.162.08:08:09.16#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:08:09.16#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:08:09.16#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.162.08:08:09.16#ibcon#ireg 7 cls_cnt 0 2006.162.08:08:09.16#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:08:09.28#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:08:09.28#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:08:09.28#ibcon#enter wrdev, iclass 36, count 0 2006.162.08:08:09.28#ibcon#first serial, iclass 36, count 0 2006.162.08:08:09.28#ibcon#enter sib2, iclass 36, count 0 2006.162.08:08:09.28#ibcon#flushed, iclass 36, count 0 2006.162.08:08:09.28#ibcon#about to write, iclass 36, count 0 2006.162.08:08:09.28#ibcon#wrote, iclass 36, count 0 2006.162.08:08:09.28#ibcon#about to read 3, iclass 36, count 0 2006.162.08:08:09.30#ibcon#read 3, iclass 36, count 0 2006.162.08:08:09.30#ibcon#about to read 4, iclass 36, count 0 2006.162.08:08:09.30#ibcon#read 4, iclass 36, count 0 2006.162.08:08:09.30#ibcon#about to read 5, iclass 36, count 0 2006.162.08:08:09.30#ibcon#read 5, iclass 36, count 0 2006.162.08:08:09.30#ibcon#about to read 6, iclass 36, count 0 2006.162.08:08:09.30#ibcon#read 6, iclass 36, count 0 2006.162.08:08:09.30#ibcon#end of sib2, iclass 36, count 0 2006.162.08:08:09.30#ibcon#*mode == 0, iclass 36, count 0 2006.162.08:08:09.30#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.162.08:08:09.30#ibcon#[25=USB\r\n] 2006.162.08:08:09.30#ibcon#*before write, iclass 36, count 0 2006.162.08:08:09.30#ibcon#enter sib2, iclass 36, count 0 2006.162.08:08:09.30#ibcon#flushed, iclass 36, count 0 2006.162.08:08:09.30#ibcon#about to write, iclass 36, count 0 2006.162.08:08:09.30#ibcon#wrote, iclass 36, count 0 2006.162.08:08:09.30#ibcon#about to read 3, iclass 36, count 0 2006.162.08:08:09.33#ibcon#read 3, iclass 36, count 0 2006.162.08:08:09.33#ibcon#about to read 4, iclass 36, count 0 2006.162.08:08:09.33#ibcon#read 4, iclass 36, count 0 2006.162.08:08:09.33#ibcon#about to read 5, iclass 36, count 0 2006.162.08:08:09.33#ibcon#read 5, iclass 36, count 0 2006.162.08:08:09.33#ibcon#about to read 6, iclass 36, count 0 2006.162.08:08:09.33#ibcon#read 6, iclass 36, count 0 2006.162.08:08:09.33#ibcon#end of sib2, iclass 36, count 0 2006.162.08:08:09.33#ibcon#*after write, iclass 36, count 0 2006.162.08:08:09.33#ibcon#*before return 0, iclass 36, count 0 2006.162.08:08:09.33#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:08:09.33#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:08:09.33#ibcon#about to clear, iclass 36 cls_cnt 0 2006.162.08:08:09.33#ibcon#cleared, iclass 36 cls_cnt 0 2006.162.08:08:09.33$vc4f8/valo=2,572.99 2006.162.08:08:09.33#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.162.08:08:09.33#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.162.08:08:09.33#ibcon#ireg 17 cls_cnt 0 2006.162.08:08:09.33#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.162.08:08:09.33#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.162.08:08:09.33#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.162.08:08:09.33#ibcon#enter wrdev, iclass 38, count 0 2006.162.08:08:09.33#ibcon#first serial, iclass 38, count 0 2006.162.08:08:09.33#ibcon#enter sib2, iclass 38, count 0 2006.162.08:08:09.33#ibcon#flushed, iclass 38, count 0 2006.162.08:08:09.33#ibcon#about to write, iclass 38, count 0 2006.162.08:08:09.33#ibcon#wrote, iclass 38, count 0 2006.162.08:08:09.33#ibcon#about to read 3, iclass 38, count 0 2006.162.08:08:09.35#ibcon#read 3, iclass 38, count 0 2006.162.08:08:09.35#ibcon#about to read 4, iclass 38, count 0 2006.162.08:08:09.35#ibcon#read 4, iclass 38, count 0 2006.162.08:08:09.35#ibcon#about to read 5, iclass 38, count 0 2006.162.08:08:09.35#ibcon#read 5, iclass 38, count 0 2006.162.08:08:09.35#ibcon#about to read 6, iclass 38, count 0 2006.162.08:08:09.35#ibcon#read 6, iclass 38, count 0 2006.162.08:08:09.35#ibcon#end of sib2, iclass 38, count 0 2006.162.08:08:09.35#ibcon#*mode == 0, iclass 38, count 0 2006.162.08:08:09.35#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.162.08:08:09.35#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.08:08:09.35#ibcon#*before write, iclass 38, count 0 2006.162.08:08:09.35#ibcon#enter sib2, iclass 38, count 0 2006.162.08:08:09.35#ibcon#flushed, iclass 38, count 0 2006.162.08:08:09.35#ibcon#about to write, iclass 38, count 0 2006.162.08:08:09.35#ibcon#wrote, iclass 38, count 0 2006.162.08:08:09.35#ibcon#about to read 3, iclass 38, count 0 2006.162.08:08:09.39#ibcon#read 3, iclass 38, count 0 2006.162.08:08:09.39#ibcon#about to read 4, iclass 38, count 0 2006.162.08:08:09.39#ibcon#read 4, iclass 38, count 0 2006.162.08:08:09.39#ibcon#about to read 5, iclass 38, count 0 2006.162.08:08:09.39#ibcon#read 5, iclass 38, count 0 2006.162.08:08:09.39#ibcon#about to read 6, iclass 38, count 0 2006.162.08:08:09.39#ibcon#read 6, iclass 38, count 0 2006.162.08:08:09.39#ibcon#end of sib2, iclass 38, count 0 2006.162.08:08:09.39#ibcon#*after write, iclass 38, count 0 2006.162.08:08:09.39#ibcon#*before return 0, iclass 38, count 0 2006.162.08:08:09.39#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.162.08:08:09.39#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.162.08:08:09.39#ibcon#about to clear, iclass 38 cls_cnt 0 2006.162.08:08:09.39#ibcon#cleared, iclass 38 cls_cnt 0 2006.162.08:08:09.39$vc4f8/va=2,7 2006.162.08:08:09.39#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.162.08:08:09.39#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.162.08:08:09.39#ibcon#ireg 11 cls_cnt 2 2006.162.08:08:09.39#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.162.08:08:09.45#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.162.08:08:09.45#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.162.08:08:09.45#ibcon#enter wrdev, iclass 40, count 2 2006.162.08:08:09.45#ibcon#first serial, iclass 40, count 2 2006.162.08:08:09.45#ibcon#enter sib2, iclass 40, count 2 2006.162.08:08:09.45#ibcon#flushed, iclass 40, count 2 2006.162.08:08:09.45#ibcon#about to write, iclass 40, count 2 2006.162.08:08:09.45#ibcon#wrote, iclass 40, count 2 2006.162.08:08:09.45#ibcon#about to read 3, iclass 40, count 2 2006.162.08:08:09.48#ibcon#read 3, iclass 40, count 2 2006.162.08:08:09.48#ibcon#about to read 4, iclass 40, count 2 2006.162.08:08:09.48#ibcon#read 4, iclass 40, count 2 2006.162.08:08:09.48#ibcon#about to read 5, iclass 40, count 2 2006.162.08:08:09.48#ibcon#read 5, iclass 40, count 2 2006.162.08:08:09.48#ibcon#about to read 6, iclass 40, count 2 2006.162.08:08:09.48#ibcon#read 6, iclass 40, count 2 2006.162.08:08:09.48#ibcon#end of sib2, iclass 40, count 2 2006.162.08:08:09.48#ibcon#*mode == 0, iclass 40, count 2 2006.162.08:08:09.48#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.162.08:08:09.48#ibcon#[25=AT02-07\r\n] 2006.162.08:08:09.48#ibcon#*before write, iclass 40, count 2 2006.162.08:08:09.48#ibcon#enter sib2, iclass 40, count 2 2006.162.08:08:09.48#ibcon#flushed, iclass 40, count 2 2006.162.08:08:09.48#ibcon#about to write, iclass 40, count 2 2006.162.08:08:09.48#ibcon#wrote, iclass 40, count 2 2006.162.08:08:09.48#ibcon#about to read 3, iclass 40, count 2 2006.162.08:08:09.51#ibcon#read 3, iclass 40, count 2 2006.162.08:08:09.51#ibcon#about to read 4, iclass 40, count 2 2006.162.08:08:09.51#ibcon#read 4, iclass 40, count 2 2006.162.08:08:09.51#ibcon#about to read 5, iclass 40, count 2 2006.162.08:08:09.51#ibcon#read 5, iclass 40, count 2 2006.162.08:08:09.51#ibcon#about to read 6, iclass 40, count 2 2006.162.08:08:09.51#ibcon#read 6, iclass 40, count 2 2006.162.08:08:09.51#ibcon#end of sib2, iclass 40, count 2 2006.162.08:08:09.51#ibcon#*after write, iclass 40, count 2 2006.162.08:08:09.51#ibcon#*before return 0, iclass 40, count 2 2006.162.08:08:09.51#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.162.08:08:09.51#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.162.08:08:09.51#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.162.08:08:09.51#ibcon#ireg 7 cls_cnt 0 2006.162.08:08:09.51#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.162.08:08:09.63#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.162.08:08:09.63#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.162.08:08:09.63#ibcon#enter wrdev, iclass 40, count 0 2006.162.08:08:09.63#ibcon#first serial, iclass 40, count 0 2006.162.08:08:09.63#ibcon#enter sib2, iclass 40, count 0 2006.162.08:08:09.63#ibcon#flushed, iclass 40, count 0 2006.162.08:08:09.63#ibcon#about to write, iclass 40, count 0 2006.162.08:08:09.63#ibcon#wrote, iclass 40, count 0 2006.162.08:08:09.63#ibcon#about to read 3, iclass 40, count 0 2006.162.08:08:09.65#ibcon#read 3, iclass 40, count 0 2006.162.08:08:09.65#ibcon#about to read 4, iclass 40, count 0 2006.162.08:08:09.65#ibcon#read 4, iclass 40, count 0 2006.162.08:08:09.65#ibcon#about to read 5, iclass 40, count 0 2006.162.08:08:09.65#ibcon#read 5, iclass 40, count 0 2006.162.08:08:09.65#ibcon#about to read 6, iclass 40, count 0 2006.162.08:08:09.65#ibcon#read 6, iclass 40, count 0 2006.162.08:08:09.65#ibcon#end of sib2, iclass 40, count 0 2006.162.08:08:09.65#ibcon#*mode == 0, iclass 40, count 0 2006.162.08:08:09.65#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.162.08:08:09.65#ibcon#[25=USB\r\n] 2006.162.08:08:09.65#ibcon#*before write, iclass 40, count 0 2006.162.08:08:09.65#ibcon#enter sib2, iclass 40, count 0 2006.162.08:08:09.65#ibcon#flushed, iclass 40, count 0 2006.162.08:08:09.65#ibcon#about to write, iclass 40, count 0 2006.162.08:08:09.65#ibcon#wrote, iclass 40, count 0 2006.162.08:08:09.65#ibcon#about to read 3, iclass 40, count 0 2006.162.08:08:09.68#ibcon#read 3, iclass 40, count 0 2006.162.08:08:09.68#ibcon#about to read 4, iclass 40, count 0 2006.162.08:08:09.68#ibcon#read 4, iclass 40, count 0 2006.162.08:08:09.68#ibcon#about to read 5, iclass 40, count 0 2006.162.08:08:09.68#ibcon#read 5, iclass 40, count 0 2006.162.08:08:09.68#ibcon#about to read 6, iclass 40, count 0 2006.162.08:08:09.68#ibcon#read 6, iclass 40, count 0 2006.162.08:08:09.68#ibcon#end of sib2, iclass 40, count 0 2006.162.08:08:09.68#ibcon#*after write, iclass 40, count 0 2006.162.08:08:09.68#ibcon#*before return 0, iclass 40, count 0 2006.162.08:08:09.68#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.162.08:08:09.68#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.162.08:08:09.68#ibcon#about to clear, iclass 40 cls_cnt 0 2006.162.08:08:09.68#ibcon#cleared, iclass 40 cls_cnt 0 2006.162.08:08:09.68$vc4f8/valo=3,672.99 2006.162.08:08:09.68#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.162.08:08:09.68#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.162.08:08:09.68#ibcon#ireg 17 cls_cnt 0 2006.162.08:08:09.68#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:08:09.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:08:09.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:08:09.68#ibcon#enter wrdev, iclass 4, count 0 2006.162.08:08:09.68#ibcon#first serial, iclass 4, count 0 2006.162.08:08:09.68#ibcon#enter sib2, iclass 4, count 0 2006.162.08:08:09.68#ibcon#flushed, iclass 4, count 0 2006.162.08:08:09.68#ibcon#about to write, iclass 4, count 0 2006.162.08:08:09.68#ibcon#wrote, iclass 4, count 0 2006.162.08:08:09.68#ibcon#about to read 3, iclass 4, count 0 2006.162.08:08:09.71#ibcon#read 3, iclass 4, count 0 2006.162.08:08:09.71#ibcon#about to read 4, iclass 4, count 0 2006.162.08:08:09.71#ibcon#read 4, iclass 4, count 0 2006.162.08:08:09.71#ibcon#about to read 5, iclass 4, count 0 2006.162.08:08:09.71#ibcon#read 5, iclass 4, count 0 2006.162.08:08:09.71#ibcon#about to read 6, iclass 4, count 0 2006.162.08:08:09.71#ibcon#read 6, iclass 4, count 0 2006.162.08:08:09.71#ibcon#end of sib2, iclass 4, count 0 2006.162.08:08:09.71#ibcon#*mode == 0, iclass 4, count 0 2006.162.08:08:09.71#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.162.08:08:09.71#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.08:08:09.71#ibcon#*before write, iclass 4, count 0 2006.162.08:08:09.71#ibcon#enter sib2, iclass 4, count 0 2006.162.08:08:09.71#ibcon#flushed, iclass 4, count 0 2006.162.08:08:09.71#ibcon#about to write, iclass 4, count 0 2006.162.08:08:09.71#ibcon#wrote, iclass 4, count 0 2006.162.08:08:09.71#ibcon#about to read 3, iclass 4, count 0 2006.162.08:08:09.75#ibcon#read 3, iclass 4, count 0 2006.162.08:08:09.75#ibcon#about to read 4, iclass 4, count 0 2006.162.08:08:09.75#ibcon#read 4, iclass 4, count 0 2006.162.08:08:09.75#ibcon#about to read 5, iclass 4, count 0 2006.162.08:08:09.75#ibcon#read 5, iclass 4, count 0 2006.162.08:08:09.75#ibcon#about to read 6, iclass 4, count 0 2006.162.08:08:09.75#ibcon#read 6, iclass 4, count 0 2006.162.08:08:09.75#ibcon#end of sib2, iclass 4, count 0 2006.162.08:08:09.75#ibcon#*after write, iclass 4, count 0 2006.162.08:08:09.75#ibcon#*before return 0, iclass 4, count 0 2006.162.08:08:09.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:08:09.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:08:09.75#ibcon#about to clear, iclass 4 cls_cnt 0 2006.162.08:08:09.75#ibcon#cleared, iclass 4 cls_cnt 0 2006.162.08:08:09.75$vc4f8/va=3,6 2006.162.08:08:09.75#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.162.08:08:09.75#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.162.08:08:09.75#ibcon#ireg 11 cls_cnt 2 2006.162.08:08:09.75#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.162.08:08:09.80#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.162.08:08:09.80#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.162.08:08:09.80#ibcon#enter wrdev, iclass 6, count 2 2006.162.08:08:09.80#ibcon#first serial, iclass 6, count 2 2006.162.08:08:09.80#ibcon#enter sib2, iclass 6, count 2 2006.162.08:08:09.80#ibcon#flushed, iclass 6, count 2 2006.162.08:08:09.80#ibcon#about to write, iclass 6, count 2 2006.162.08:08:09.80#ibcon#wrote, iclass 6, count 2 2006.162.08:08:09.80#ibcon#about to read 3, iclass 6, count 2 2006.162.08:08:09.83#ibcon#read 3, iclass 6, count 2 2006.162.08:08:09.83#ibcon#about to read 4, iclass 6, count 2 2006.162.08:08:09.83#ibcon#read 4, iclass 6, count 2 2006.162.08:08:09.83#ibcon#about to read 5, iclass 6, count 2 2006.162.08:08:09.83#ibcon#read 5, iclass 6, count 2 2006.162.08:08:09.83#ibcon#about to read 6, iclass 6, count 2 2006.162.08:08:09.83#ibcon#read 6, iclass 6, count 2 2006.162.08:08:09.83#ibcon#end of sib2, iclass 6, count 2 2006.162.08:08:09.83#ibcon#*mode == 0, iclass 6, count 2 2006.162.08:08:09.83#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.162.08:08:09.83#ibcon#[25=AT03-06\r\n] 2006.162.08:08:09.83#ibcon#*before write, iclass 6, count 2 2006.162.08:08:09.83#ibcon#enter sib2, iclass 6, count 2 2006.162.08:08:09.83#ibcon#flushed, iclass 6, count 2 2006.162.08:08:09.83#ibcon#about to write, iclass 6, count 2 2006.162.08:08:09.83#ibcon#wrote, iclass 6, count 2 2006.162.08:08:09.83#ibcon#about to read 3, iclass 6, count 2 2006.162.08:08:09.86#ibcon#read 3, iclass 6, count 2 2006.162.08:08:09.86#ibcon#about to read 4, iclass 6, count 2 2006.162.08:08:09.86#ibcon#read 4, iclass 6, count 2 2006.162.08:08:09.86#ibcon#about to read 5, iclass 6, count 2 2006.162.08:08:09.86#ibcon#read 5, iclass 6, count 2 2006.162.08:08:09.86#ibcon#about to read 6, iclass 6, count 2 2006.162.08:08:09.86#ibcon#read 6, iclass 6, count 2 2006.162.08:08:09.86#ibcon#end of sib2, iclass 6, count 2 2006.162.08:08:09.86#ibcon#*after write, iclass 6, count 2 2006.162.08:08:09.86#ibcon#*before return 0, iclass 6, count 2 2006.162.08:08:09.86#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.162.08:08:09.86#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.162.08:08:09.86#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.162.08:08:09.86#ibcon#ireg 7 cls_cnt 0 2006.162.08:08:09.86#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.162.08:08:09.98#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.162.08:08:09.98#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.162.08:08:09.98#ibcon#enter wrdev, iclass 6, count 0 2006.162.08:08:09.98#ibcon#first serial, iclass 6, count 0 2006.162.08:08:09.98#ibcon#enter sib2, iclass 6, count 0 2006.162.08:08:09.98#ibcon#flushed, iclass 6, count 0 2006.162.08:08:09.98#ibcon#about to write, iclass 6, count 0 2006.162.08:08:09.98#ibcon#wrote, iclass 6, count 0 2006.162.08:08:09.98#ibcon#about to read 3, iclass 6, count 0 2006.162.08:08:10.00#ibcon#read 3, iclass 6, count 0 2006.162.08:08:10.00#ibcon#about to read 4, iclass 6, count 0 2006.162.08:08:10.00#ibcon#read 4, iclass 6, count 0 2006.162.08:08:10.00#ibcon#about to read 5, iclass 6, count 0 2006.162.08:08:10.00#ibcon#read 5, iclass 6, count 0 2006.162.08:08:10.00#ibcon#about to read 6, iclass 6, count 0 2006.162.08:08:10.00#ibcon#read 6, iclass 6, count 0 2006.162.08:08:10.00#ibcon#end of sib2, iclass 6, count 0 2006.162.08:08:10.00#ibcon#*mode == 0, iclass 6, count 0 2006.162.08:08:10.00#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.162.08:08:10.00#ibcon#[25=USB\r\n] 2006.162.08:08:10.00#ibcon#*before write, iclass 6, count 0 2006.162.08:08:10.00#ibcon#enter sib2, iclass 6, count 0 2006.162.08:08:10.00#ibcon#flushed, iclass 6, count 0 2006.162.08:08:10.00#ibcon#about to write, iclass 6, count 0 2006.162.08:08:10.00#ibcon#wrote, iclass 6, count 0 2006.162.08:08:10.00#ibcon#about to read 3, iclass 6, count 0 2006.162.08:08:10.03#ibcon#read 3, iclass 6, count 0 2006.162.08:08:10.03#ibcon#about to read 4, iclass 6, count 0 2006.162.08:08:10.03#ibcon#read 4, iclass 6, count 0 2006.162.08:08:10.03#ibcon#about to read 5, iclass 6, count 0 2006.162.08:08:10.03#ibcon#read 5, iclass 6, count 0 2006.162.08:08:10.03#ibcon#about to read 6, iclass 6, count 0 2006.162.08:08:10.03#ibcon#read 6, iclass 6, count 0 2006.162.08:08:10.03#ibcon#end of sib2, iclass 6, count 0 2006.162.08:08:10.03#ibcon#*after write, iclass 6, count 0 2006.162.08:08:10.03#ibcon#*before return 0, iclass 6, count 0 2006.162.08:08:10.03#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.162.08:08:10.03#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.162.08:08:10.03#ibcon#about to clear, iclass 6 cls_cnt 0 2006.162.08:08:10.03#ibcon#cleared, iclass 6 cls_cnt 0 2006.162.08:08:10.03$vc4f8/valo=4,832.99 2006.162.08:08:10.03#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.162.08:08:10.03#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.162.08:08:10.03#ibcon#ireg 17 cls_cnt 0 2006.162.08:08:10.03#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:08:10.03#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:08:10.03#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:08:10.03#ibcon#enter wrdev, iclass 10, count 0 2006.162.08:08:10.03#ibcon#first serial, iclass 10, count 0 2006.162.08:08:10.03#ibcon#enter sib2, iclass 10, count 0 2006.162.08:08:10.03#ibcon#flushed, iclass 10, count 0 2006.162.08:08:10.03#ibcon#about to write, iclass 10, count 0 2006.162.08:08:10.03#ibcon#wrote, iclass 10, count 0 2006.162.08:08:10.03#ibcon#about to read 3, iclass 10, count 0 2006.162.08:08:10.05#ibcon#read 3, iclass 10, count 0 2006.162.08:08:10.05#ibcon#about to read 4, iclass 10, count 0 2006.162.08:08:10.05#ibcon#read 4, iclass 10, count 0 2006.162.08:08:10.05#ibcon#about to read 5, iclass 10, count 0 2006.162.08:08:10.05#ibcon#read 5, iclass 10, count 0 2006.162.08:08:10.05#ibcon#about to read 6, iclass 10, count 0 2006.162.08:08:10.05#ibcon#read 6, iclass 10, count 0 2006.162.08:08:10.05#ibcon#end of sib2, iclass 10, count 0 2006.162.08:08:10.05#ibcon#*mode == 0, iclass 10, count 0 2006.162.08:08:10.05#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.162.08:08:10.05#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.08:08:10.05#ibcon#*before write, iclass 10, count 0 2006.162.08:08:10.05#ibcon#enter sib2, iclass 10, count 0 2006.162.08:08:10.05#ibcon#flushed, iclass 10, count 0 2006.162.08:08:10.05#ibcon#about to write, iclass 10, count 0 2006.162.08:08:10.05#ibcon#wrote, iclass 10, count 0 2006.162.08:08:10.05#ibcon#about to read 3, iclass 10, count 0 2006.162.08:08:10.09#ibcon#read 3, iclass 10, count 0 2006.162.08:08:10.09#ibcon#about to read 4, iclass 10, count 0 2006.162.08:08:10.09#ibcon#read 4, iclass 10, count 0 2006.162.08:08:10.09#ibcon#about to read 5, iclass 10, count 0 2006.162.08:08:10.09#ibcon#read 5, iclass 10, count 0 2006.162.08:08:10.09#ibcon#about to read 6, iclass 10, count 0 2006.162.08:08:10.09#ibcon#read 6, iclass 10, count 0 2006.162.08:08:10.09#ibcon#end of sib2, iclass 10, count 0 2006.162.08:08:10.09#ibcon#*after write, iclass 10, count 0 2006.162.08:08:10.09#ibcon#*before return 0, iclass 10, count 0 2006.162.08:08:10.09#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:08:10.09#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:08:10.09#ibcon#about to clear, iclass 10 cls_cnt 0 2006.162.08:08:10.09#ibcon#cleared, iclass 10 cls_cnt 0 2006.162.08:08:10.09$vc4f8/va=4,7 2006.162.08:08:10.09#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.162.08:08:10.09#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.162.08:08:10.09#ibcon#ireg 11 cls_cnt 2 2006.162.08:08:10.09#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:08:10.15#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:08:10.15#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:08:10.15#ibcon#enter wrdev, iclass 12, count 2 2006.162.08:08:10.15#ibcon#first serial, iclass 12, count 2 2006.162.08:08:10.15#ibcon#enter sib2, iclass 12, count 2 2006.162.08:08:10.15#ibcon#flushed, iclass 12, count 2 2006.162.08:08:10.15#ibcon#about to write, iclass 12, count 2 2006.162.08:08:10.15#ibcon#wrote, iclass 12, count 2 2006.162.08:08:10.15#ibcon#about to read 3, iclass 12, count 2 2006.162.08:08:10.17#ibcon#read 3, iclass 12, count 2 2006.162.08:08:10.17#ibcon#about to read 4, iclass 12, count 2 2006.162.08:08:10.17#ibcon#read 4, iclass 12, count 2 2006.162.08:08:10.17#ibcon#about to read 5, iclass 12, count 2 2006.162.08:08:10.17#ibcon#read 5, iclass 12, count 2 2006.162.08:08:10.17#ibcon#about to read 6, iclass 12, count 2 2006.162.08:08:10.17#ibcon#read 6, iclass 12, count 2 2006.162.08:08:10.17#ibcon#end of sib2, iclass 12, count 2 2006.162.08:08:10.17#ibcon#*mode == 0, iclass 12, count 2 2006.162.08:08:10.17#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.162.08:08:10.17#ibcon#[25=AT04-07\r\n] 2006.162.08:08:10.17#ibcon#*before write, iclass 12, count 2 2006.162.08:08:10.17#ibcon#enter sib2, iclass 12, count 2 2006.162.08:08:10.17#ibcon#flushed, iclass 12, count 2 2006.162.08:08:10.17#ibcon#about to write, iclass 12, count 2 2006.162.08:08:10.17#ibcon#wrote, iclass 12, count 2 2006.162.08:08:10.17#ibcon#about to read 3, iclass 12, count 2 2006.162.08:08:10.20#ibcon#read 3, iclass 12, count 2 2006.162.08:08:10.20#ibcon#about to read 4, iclass 12, count 2 2006.162.08:08:10.20#ibcon#read 4, iclass 12, count 2 2006.162.08:08:10.20#ibcon#about to read 5, iclass 12, count 2 2006.162.08:08:10.20#ibcon#read 5, iclass 12, count 2 2006.162.08:08:10.20#ibcon#about to read 6, iclass 12, count 2 2006.162.08:08:10.20#ibcon#read 6, iclass 12, count 2 2006.162.08:08:10.20#ibcon#end of sib2, iclass 12, count 2 2006.162.08:08:10.20#ibcon#*after write, iclass 12, count 2 2006.162.08:08:10.20#ibcon#*before return 0, iclass 12, count 2 2006.162.08:08:10.20#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:08:10.20#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:08:10.20#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.162.08:08:10.20#ibcon#ireg 7 cls_cnt 0 2006.162.08:08:10.20#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:08:10.32#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:08:10.32#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:08:10.32#ibcon#enter wrdev, iclass 12, count 0 2006.162.08:08:10.32#ibcon#first serial, iclass 12, count 0 2006.162.08:08:10.32#ibcon#enter sib2, iclass 12, count 0 2006.162.08:08:10.32#ibcon#flushed, iclass 12, count 0 2006.162.08:08:10.32#ibcon#about to write, iclass 12, count 0 2006.162.08:08:10.32#ibcon#wrote, iclass 12, count 0 2006.162.08:08:10.32#ibcon#about to read 3, iclass 12, count 0 2006.162.08:08:10.34#ibcon#read 3, iclass 12, count 0 2006.162.08:08:10.34#ibcon#about to read 4, iclass 12, count 0 2006.162.08:08:10.34#ibcon#read 4, iclass 12, count 0 2006.162.08:08:10.34#ibcon#about to read 5, iclass 12, count 0 2006.162.08:08:10.34#ibcon#read 5, iclass 12, count 0 2006.162.08:08:10.34#ibcon#about to read 6, iclass 12, count 0 2006.162.08:08:10.34#ibcon#read 6, iclass 12, count 0 2006.162.08:08:10.34#ibcon#end of sib2, iclass 12, count 0 2006.162.08:08:10.34#ibcon#*mode == 0, iclass 12, count 0 2006.162.08:08:10.34#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.162.08:08:10.34#ibcon#[25=USB\r\n] 2006.162.08:08:10.34#ibcon#*before write, iclass 12, count 0 2006.162.08:08:10.34#ibcon#enter sib2, iclass 12, count 0 2006.162.08:08:10.34#ibcon#flushed, iclass 12, count 0 2006.162.08:08:10.34#ibcon#about to write, iclass 12, count 0 2006.162.08:08:10.34#ibcon#wrote, iclass 12, count 0 2006.162.08:08:10.34#ibcon#about to read 3, iclass 12, count 0 2006.162.08:08:10.37#ibcon#read 3, iclass 12, count 0 2006.162.08:08:10.37#ibcon#about to read 4, iclass 12, count 0 2006.162.08:08:10.37#ibcon#read 4, iclass 12, count 0 2006.162.08:08:10.37#ibcon#about to read 5, iclass 12, count 0 2006.162.08:08:10.37#ibcon#read 5, iclass 12, count 0 2006.162.08:08:10.37#ibcon#about to read 6, iclass 12, count 0 2006.162.08:08:10.37#ibcon#read 6, iclass 12, count 0 2006.162.08:08:10.37#ibcon#end of sib2, iclass 12, count 0 2006.162.08:08:10.37#ibcon#*after write, iclass 12, count 0 2006.162.08:08:10.37#ibcon#*before return 0, iclass 12, count 0 2006.162.08:08:10.37#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:08:10.37#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:08:10.37#ibcon#about to clear, iclass 12 cls_cnt 0 2006.162.08:08:10.37#ibcon#cleared, iclass 12 cls_cnt 0 2006.162.08:08:10.37$vc4f8/valo=5,652.99 2006.162.08:08:10.37#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.162.08:08:10.37#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.162.08:08:10.37#ibcon#ireg 17 cls_cnt 0 2006.162.08:08:10.37#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:08:10.37#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:08:10.37#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:08:10.37#ibcon#enter wrdev, iclass 14, count 0 2006.162.08:08:10.37#ibcon#first serial, iclass 14, count 0 2006.162.08:08:10.37#ibcon#enter sib2, iclass 14, count 0 2006.162.08:08:10.37#ibcon#flushed, iclass 14, count 0 2006.162.08:08:10.37#ibcon#about to write, iclass 14, count 0 2006.162.08:08:10.37#ibcon#wrote, iclass 14, count 0 2006.162.08:08:10.37#ibcon#about to read 3, iclass 14, count 0 2006.162.08:08:10.40#ibcon#read 3, iclass 14, count 0 2006.162.08:08:10.40#ibcon#about to read 4, iclass 14, count 0 2006.162.08:08:10.40#ibcon#read 4, iclass 14, count 0 2006.162.08:08:10.40#ibcon#about to read 5, iclass 14, count 0 2006.162.08:08:10.40#ibcon#read 5, iclass 14, count 0 2006.162.08:08:10.40#ibcon#about to read 6, iclass 14, count 0 2006.162.08:08:10.40#ibcon#read 6, iclass 14, count 0 2006.162.08:08:10.40#ibcon#end of sib2, iclass 14, count 0 2006.162.08:08:10.40#ibcon#*mode == 0, iclass 14, count 0 2006.162.08:08:10.40#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.08:08:10.40#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.08:08:10.40#ibcon#*before write, iclass 14, count 0 2006.162.08:08:10.40#ibcon#enter sib2, iclass 14, count 0 2006.162.08:08:10.40#ibcon#flushed, iclass 14, count 0 2006.162.08:08:10.40#ibcon#about to write, iclass 14, count 0 2006.162.08:08:10.40#ibcon#wrote, iclass 14, count 0 2006.162.08:08:10.40#ibcon#about to read 3, iclass 14, count 0 2006.162.08:08:10.44#ibcon#read 3, iclass 14, count 0 2006.162.08:08:10.44#ibcon#about to read 4, iclass 14, count 0 2006.162.08:08:10.44#ibcon#read 4, iclass 14, count 0 2006.162.08:08:10.44#ibcon#about to read 5, iclass 14, count 0 2006.162.08:08:10.44#ibcon#read 5, iclass 14, count 0 2006.162.08:08:10.44#ibcon#about to read 6, iclass 14, count 0 2006.162.08:08:10.44#ibcon#read 6, iclass 14, count 0 2006.162.08:08:10.44#ibcon#end of sib2, iclass 14, count 0 2006.162.08:08:10.44#ibcon#*after write, iclass 14, count 0 2006.162.08:08:10.44#ibcon#*before return 0, iclass 14, count 0 2006.162.08:08:10.44#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:08:10.44#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:08:10.44#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.08:08:10.44#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.08:08:10.44$vc4f8/va=5,7 2006.162.08:08:10.44#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.162.08:08:10.44#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.162.08:08:10.44#ibcon#ireg 11 cls_cnt 2 2006.162.08:08:10.44#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:08:10.49#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:08:10.49#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:08:10.49#ibcon#enter wrdev, iclass 16, count 2 2006.162.08:08:10.49#ibcon#first serial, iclass 16, count 2 2006.162.08:08:10.49#ibcon#enter sib2, iclass 16, count 2 2006.162.08:08:10.49#ibcon#flushed, iclass 16, count 2 2006.162.08:08:10.49#ibcon#about to write, iclass 16, count 2 2006.162.08:08:10.49#ibcon#wrote, iclass 16, count 2 2006.162.08:08:10.49#ibcon#about to read 3, iclass 16, count 2 2006.162.08:08:10.52#ibcon#read 3, iclass 16, count 2 2006.162.08:08:10.52#ibcon#about to read 4, iclass 16, count 2 2006.162.08:08:10.52#ibcon#read 4, iclass 16, count 2 2006.162.08:08:10.52#ibcon#about to read 5, iclass 16, count 2 2006.162.08:08:10.52#ibcon#read 5, iclass 16, count 2 2006.162.08:08:10.52#ibcon#about to read 6, iclass 16, count 2 2006.162.08:08:10.52#ibcon#read 6, iclass 16, count 2 2006.162.08:08:10.52#ibcon#end of sib2, iclass 16, count 2 2006.162.08:08:10.52#ibcon#*mode == 0, iclass 16, count 2 2006.162.08:08:10.52#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.162.08:08:10.52#ibcon#[25=AT05-07\r\n] 2006.162.08:08:10.52#ibcon#*before write, iclass 16, count 2 2006.162.08:08:10.52#ibcon#enter sib2, iclass 16, count 2 2006.162.08:08:10.52#ibcon#flushed, iclass 16, count 2 2006.162.08:08:10.52#ibcon#about to write, iclass 16, count 2 2006.162.08:08:10.52#ibcon#wrote, iclass 16, count 2 2006.162.08:08:10.52#ibcon#about to read 3, iclass 16, count 2 2006.162.08:08:10.55#ibcon#read 3, iclass 16, count 2 2006.162.08:08:10.55#ibcon#about to read 4, iclass 16, count 2 2006.162.08:08:10.55#ibcon#read 4, iclass 16, count 2 2006.162.08:08:10.55#ibcon#about to read 5, iclass 16, count 2 2006.162.08:08:10.55#ibcon#read 5, iclass 16, count 2 2006.162.08:08:10.55#ibcon#about to read 6, iclass 16, count 2 2006.162.08:08:10.55#ibcon#read 6, iclass 16, count 2 2006.162.08:08:10.55#ibcon#end of sib2, iclass 16, count 2 2006.162.08:08:10.55#ibcon#*after write, iclass 16, count 2 2006.162.08:08:10.55#ibcon#*before return 0, iclass 16, count 2 2006.162.08:08:10.55#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:08:10.55#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:08:10.55#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.162.08:08:10.55#ibcon#ireg 7 cls_cnt 0 2006.162.08:08:10.55#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:08:10.67#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:08:10.67#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:08:10.67#ibcon#enter wrdev, iclass 16, count 0 2006.162.08:08:10.67#ibcon#first serial, iclass 16, count 0 2006.162.08:08:10.67#ibcon#enter sib2, iclass 16, count 0 2006.162.08:08:10.67#ibcon#flushed, iclass 16, count 0 2006.162.08:08:10.67#ibcon#about to write, iclass 16, count 0 2006.162.08:08:10.67#ibcon#wrote, iclass 16, count 0 2006.162.08:08:10.67#ibcon#about to read 3, iclass 16, count 0 2006.162.08:08:10.69#ibcon#read 3, iclass 16, count 0 2006.162.08:08:10.69#ibcon#about to read 4, iclass 16, count 0 2006.162.08:08:10.69#ibcon#read 4, iclass 16, count 0 2006.162.08:08:10.69#ibcon#about to read 5, iclass 16, count 0 2006.162.08:08:10.69#ibcon#read 5, iclass 16, count 0 2006.162.08:08:10.69#ibcon#about to read 6, iclass 16, count 0 2006.162.08:08:10.69#ibcon#read 6, iclass 16, count 0 2006.162.08:08:10.69#ibcon#end of sib2, iclass 16, count 0 2006.162.08:08:10.69#ibcon#*mode == 0, iclass 16, count 0 2006.162.08:08:10.69#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.162.08:08:10.69#ibcon#[25=USB\r\n] 2006.162.08:08:10.69#ibcon#*before write, iclass 16, count 0 2006.162.08:08:10.69#ibcon#enter sib2, iclass 16, count 0 2006.162.08:08:10.69#ibcon#flushed, iclass 16, count 0 2006.162.08:08:10.69#ibcon#about to write, iclass 16, count 0 2006.162.08:08:10.69#ibcon#wrote, iclass 16, count 0 2006.162.08:08:10.69#ibcon#about to read 3, iclass 16, count 0 2006.162.08:08:10.72#ibcon#read 3, iclass 16, count 0 2006.162.08:08:10.72#ibcon#about to read 4, iclass 16, count 0 2006.162.08:08:10.72#ibcon#read 4, iclass 16, count 0 2006.162.08:08:10.72#ibcon#about to read 5, iclass 16, count 0 2006.162.08:08:10.72#ibcon#read 5, iclass 16, count 0 2006.162.08:08:10.72#ibcon#about to read 6, iclass 16, count 0 2006.162.08:08:10.72#ibcon#read 6, iclass 16, count 0 2006.162.08:08:10.72#ibcon#end of sib2, iclass 16, count 0 2006.162.08:08:10.72#ibcon#*after write, iclass 16, count 0 2006.162.08:08:10.72#ibcon#*before return 0, iclass 16, count 0 2006.162.08:08:10.72#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:08:10.72#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:08:10.72#ibcon#about to clear, iclass 16 cls_cnt 0 2006.162.08:08:10.72#ibcon#cleared, iclass 16 cls_cnt 0 2006.162.08:08:10.72$vc4f8/valo=6,772.99 2006.162.08:08:10.72#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.162.08:08:10.72#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.162.08:08:10.72#ibcon#ireg 17 cls_cnt 0 2006.162.08:08:10.72#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:08:10.72#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:08:10.72#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:08:10.72#ibcon#enter wrdev, iclass 18, count 0 2006.162.08:08:10.72#ibcon#first serial, iclass 18, count 0 2006.162.08:08:10.72#ibcon#enter sib2, iclass 18, count 0 2006.162.08:08:10.72#ibcon#flushed, iclass 18, count 0 2006.162.08:08:10.72#ibcon#about to write, iclass 18, count 0 2006.162.08:08:10.72#ibcon#wrote, iclass 18, count 0 2006.162.08:08:10.72#ibcon#about to read 3, iclass 18, count 0 2006.162.08:08:10.74#ibcon#read 3, iclass 18, count 0 2006.162.08:08:10.74#ibcon#about to read 4, iclass 18, count 0 2006.162.08:08:10.74#ibcon#read 4, iclass 18, count 0 2006.162.08:08:10.74#ibcon#about to read 5, iclass 18, count 0 2006.162.08:08:10.74#ibcon#read 5, iclass 18, count 0 2006.162.08:08:10.74#ibcon#about to read 6, iclass 18, count 0 2006.162.08:08:10.74#ibcon#read 6, iclass 18, count 0 2006.162.08:08:10.74#ibcon#end of sib2, iclass 18, count 0 2006.162.08:08:10.74#ibcon#*mode == 0, iclass 18, count 0 2006.162.08:08:10.74#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.162.08:08:10.74#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.08:08:10.74#ibcon#*before write, iclass 18, count 0 2006.162.08:08:10.74#ibcon#enter sib2, iclass 18, count 0 2006.162.08:08:10.74#ibcon#flushed, iclass 18, count 0 2006.162.08:08:10.74#ibcon#about to write, iclass 18, count 0 2006.162.08:08:10.74#ibcon#wrote, iclass 18, count 0 2006.162.08:08:10.74#ibcon#about to read 3, iclass 18, count 0 2006.162.08:08:10.78#ibcon#read 3, iclass 18, count 0 2006.162.08:08:10.78#ibcon#about to read 4, iclass 18, count 0 2006.162.08:08:10.78#ibcon#read 4, iclass 18, count 0 2006.162.08:08:10.78#ibcon#about to read 5, iclass 18, count 0 2006.162.08:08:10.78#ibcon#read 5, iclass 18, count 0 2006.162.08:08:10.78#ibcon#about to read 6, iclass 18, count 0 2006.162.08:08:10.78#ibcon#read 6, iclass 18, count 0 2006.162.08:08:10.78#ibcon#end of sib2, iclass 18, count 0 2006.162.08:08:10.78#ibcon#*after write, iclass 18, count 0 2006.162.08:08:10.78#ibcon#*before return 0, iclass 18, count 0 2006.162.08:08:10.78#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:08:10.78#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:08:10.78#ibcon#about to clear, iclass 18 cls_cnt 0 2006.162.08:08:10.78#ibcon#cleared, iclass 18 cls_cnt 0 2006.162.08:08:10.78$vc4f8/va=6,6 2006.162.08:08:10.78#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.162.08:08:10.78#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.162.08:08:10.78#ibcon#ireg 11 cls_cnt 2 2006.162.08:08:10.78#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:08:10.84#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:08:10.84#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:08:10.84#ibcon#enter wrdev, iclass 20, count 2 2006.162.08:08:10.84#ibcon#first serial, iclass 20, count 2 2006.162.08:08:10.84#ibcon#enter sib2, iclass 20, count 2 2006.162.08:08:10.84#ibcon#flushed, iclass 20, count 2 2006.162.08:08:10.84#ibcon#about to write, iclass 20, count 2 2006.162.08:08:10.84#ibcon#wrote, iclass 20, count 2 2006.162.08:08:10.84#ibcon#about to read 3, iclass 20, count 2 2006.162.08:08:10.86#ibcon#read 3, iclass 20, count 2 2006.162.08:08:10.86#ibcon#about to read 4, iclass 20, count 2 2006.162.08:08:10.86#ibcon#read 4, iclass 20, count 2 2006.162.08:08:10.86#ibcon#about to read 5, iclass 20, count 2 2006.162.08:08:10.86#ibcon#read 5, iclass 20, count 2 2006.162.08:08:10.86#ibcon#about to read 6, iclass 20, count 2 2006.162.08:08:10.86#ibcon#read 6, iclass 20, count 2 2006.162.08:08:10.86#ibcon#end of sib2, iclass 20, count 2 2006.162.08:08:10.86#ibcon#*mode == 0, iclass 20, count 2 2006.162.08:08:10.86#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.162.08:08:10.86#ibcon#[25=AT06-06\r\n] 2006.162.08:08:10.86#ibcon#*before write, iclass 20, count 2 2006.162.08:08:10.86#ibcon#enter sib2, iclass 20, count 2 2006.162.08:08:10.86#ibcon#flushed, iclass 20, count 2 2006.162.08:08:10.86#ibcon#about to write, iclass 20, count 2 2006.162.08:08:10.86#ibcon#wrote, iclass 20, count 2 2006.162.08:08:10.86#ibcon#about to read 3, iclass 20, count 2 2006.162.08:08:10.89#ibcon#read 3, iclass 20, count 2 2006.162.08:08:10.89#ibcon#about to read 4, iclass 20, count 2 2006.162.08:08:10.89#ibcon#read 4, iclass 20, count 2 2006.162.08:08:10.89#ibcon#about to read 5, iclass 20, count 2 2006.162.08:08:10.89#ibcon#read 5, iclass 20, count 2 2006.162.08:08:10.89#ibcon#about to read 6, iclass 20, count 2 2006.162.08:08:10.89#ibcon#read 6, iclass 20, count 2 2006.162.08:08:10.89#ibcon#end of sib2, iclass 20, count 2 2006.162.08:08:10.89#ibcon#*after write, iclass 20, count 2 2006.162.08:08:10.89#ibcon#*before return 0, iclass 20, count 2 2006.162.08:08:10.89#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:08:10.89#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:08:10.89#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.162.08:08:10.89#ibcon#ireg 7 cls_cnt 0 2006.162.08:08:10.89#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:08:11.01#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:08:11.01#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:08:11.01#ibcon#enter wrdev, iclass 20, count 0 2006.162.08:08:11.01#ibcon#first serial, iclass 20, count 0 2006.162.08:08:11.01#ibcon#enter sib2, iclass 20, count 0 2006.162.08:08:11.01#ibcon#flushed, iclass 20, count 0 2006.162.08:08:11.01#ibcon#about to write, iclass 20, count 0 2006.162.08:08:11.01#ibcon#wrote, iclass 20, count 0 2006.162.08:08:11.01#ibcon#about to read 3, iclass 20, count 0 2006.162.08:08:11.03#ibcon#read 3, iclass 20, count 0 2006.162.08:08:11.03#ibcon#about to read 4, iclass 20, count 0 2006.162.08:08:11.03#ibcon#read 4, iclass 20, count 0 2006.162.08:08:11.03#ibcon#about to read 5, iclass 20, count 0 2006.162.08:08:11.03#ibcon#read 5, iclass 20, count 0 2006.162.08:08:11.03#ibcon#about to read 6, iclass 20, count 0 2006.162.08:08:11.03#ibcon#read 6, iclass 20, count 0 2006.162.08:08:11.03#ibcon#end of sib2, iclass 20, count 0 2006.162.08:08:11.03#ibcon#*mode == 0, iclass 20, count 0 2006.162.08:08:11.03#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.08:08:11.03#ibcon#[25=USB\r\n] 2006.162.08:08:11.03#ibcon#*before write, iclass 20, count 0 2006.162.08:08:11.03#ibcon#enter sib2, iclass 20, count 0 2006.162.08:08:11.03#ibcon#flushed, iclass 20, count 0 2006.162.08:08:11.03#ibcon#about to write, iclass 20, count 0 2006.162.08:08:11.03#ibcon#wrote, iclass 20, count 0 2006.162.08:08:11.03#ibcon#about to read 3, iclass 20, count 0 2006.162.08:08:11.06#ibcon#read 3, iclass 20, count 0 2006.162.08:08:11.06#ibcon#about to read 4, iclass 20, count 0 2006.162.08:08:11.06#ibcon#read 4, iclass 20, count 0 2006.162.08:08:11.06#ibcon#about to read 5, iclass 20, count 0 2006.162.08:08:11.06#ibcon#read 5, iclass 20, count 0 2006.162.08:08:11.06#ibcon#about to read 6, iclass 20, count 0 2006.162.08:08:11.06#ibcon#read 6, iclass 20, count 0 2006.162.08:08:11.06#ibcon#end of sib2, iclass 20, count 0 2006.162.08:08:11.06#ibcon#*after write, iclass 20, count 0 2006.162.08:08:11.06#ibcon#*before return 0, iclass 20, count 0 2006.162.08:08:11.06#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:08:11.06#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:08:11.06#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.08:08:11.06#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.08:08:11.06$vc4f8/valo=7,832.99 2006.162.08:08:11.06#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.162.08:08:11.06#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.162.08:08:11.06#ibcon#ireg 17 cls_cnt 0 2006.162.08:08:11.06#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:08:11.06#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:08:11.06#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:08:11.06#ibcon#enter wrdev, iclass 22, count 0 2006.162.08:08:11.06#ibcon#first serial, iclass 22, count 0 2006.162.08:08:11.06#ibcon#enter sib2, iclass 22, count 0 2006.162.08:08:11.06#ibcon#flushed, iclass 22, count 0 2006.162.08:08:11.06#ibcon#about to write, iclass 22, count 0 2006.162.08:08:11.06#ibcon#wrote, iclass 22, count 0 2006.162.08:08:11.06#ibcon#about to read 3, iclass 22, count 0 2006.162.08:08:11.08#ibcon#read 3, iclass 22, count 0 2006.162.08:08:11.08#ibcon#about to read 4, iclass 22, count 0 2006.162.08:08:11.08#ibcon#read 4, iclass 22, count 0 2006.162.08:08:11.08#ibcon#about to read 5, iclass 22, count 0 2006.162.08:08:11.08#ibcon#read 5, iclass 22, count 0 2006.162.08:08:11.08#ibcon#about to read 6, iclass 22, count 0 2006.162.08:08:11.08#ibcon#read 6, iclass 22, count 0 2006.162.08:08:11.08#ibcon#end of sib2, iclass 22, count 0 2006.162.08:08:11.08#ibcon#*mode == 0, iclass 22, count 0 2006.162.08:08:11.08#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.08:08:11.08#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.08:08:11.08#ibcon#*before write, iclass 22, count 0 2006.162.08:08:11.08#ibcon#enter sib2, iclass 22, count 0 2006.162.08:08:11.08#ibcon#flushed, iclass 22, count 0 2006.162.08:08:11.08#ibcon#about to write, iclass 22, count 0 2006.162.08:08:11.08#ibcon#wrote, iclass 22, count 0 2006.162.08:08:11.08#ibcon#about to read 3, iclass 22, count 0 2006.162.08:08:11.12#ibcon#read 3, iclass 22, count 0 2006.162.08:08:11.12#ibcon#about to read 4, iclass 22, count 0 2006.162.08:08:11.12#ibcon#read 4, iclass 22, count 0 2006.162.08:08:11.12#ibcon#about to read 5, iclass 22, count 0 2006.162.08:08:11.12#ibcon#read 5, iclass 22, count 0 2006.162.08:08:11.12#ibcon#about to read 6, iclass 22, count 0 2006.162.08:08:11.12#ibcon#read 6, iclass 22, count 0 2006.162.08:08:11.12#ibcon#end of sib2, iclass 22, count 0 2006.162.08:08:11.12#ibcon#*after write, iclass 22, count 0 2006.162.08:08:11.12#ibcon#*before return 0, iclass 22, count 0 2006.162.08:08:11.12#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:08:11.12#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:08:11.12#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.08:08:11.12#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.08:08:11.12$vc4f8/va=7,6 2006.162.08:08:11.12#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.162.08:08:11.12#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.162.08:08:11.12#ibcon#ireg 11 cls_cnt 2 2006.162.08:08:11.12#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:08:11.18#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:08:11.18#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:08:11.18#ibcon#enter wrdev, iclass 24, count 2 2006.162.08:08:11.18#ibcon#first serial, iclass 24, count 2 2006.162.08:08:11.18#ibcon#enter sib2, iclass 24, count 2 2006.162.08:08:11.18#ibcon#flushed, iclass 24, count 2 2006.162.08:08:11.18#ibcon#about to write, iclass 24, count 2 2006.162.08:08:11.18#ibcon#wrote, iclass 24, count 2 2006.162.08:08:11.18#ibcon#about to read 3, iclass 24, count 2 2006.162.08:08:11.20#ibcon#read 3, iclass 24, count 2 2006.162.08:08:11.20#ibcon#about to read 4, iclass 24, count 2 2006.162.08:08:11.20#ibcon#read 4, iclass 24, count 2 2006.162.08:08:11.20#ibcon#about to read 5, iclass 24, count 2 2006.162.08:08:11.20#ibcon#read 5, iclass 24, count 2 2006.162.08:08:11.20#ibcon#about to read 6, iclass 24, count 2 2006.162.08:08:11.20#ibcon#read 6, iclass 24, count 2 2006.162.08:08:11.20#ibcon#end of sib2, iclass 24, count 2 2006.162.08:08:11.20#ibcon#*mode == 0, iclass 24, count 2 2006.162.08:08:11.20#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.162.08:08:11.20#ibcon#[25=AT07-06\r\n] 2006.162.08:08:11.20#ibcon#*before write, iclass 24, count 2 2006.162.08:08:11.20#ibcon#enter sib2, iclass 24, count 2 2006.162.08:08:11.20#ibcon#flushed, iclass 24, count 2 2006.162.08:08:11.20#ibcon#about to write, iclass 24, count 2 2006.162.08:08:11.20#ibcon#wrote, iclass 24, count 2 2006.162.08:08:11.20#ibcon#about to read 3, iclass 24, count 2 2006.162.08:08:11.23#ibcon#read 3, iclass 24, count 2 2006.162.08:08:11.23#ibcon#about to read 4, iclass 24, count 2 2006.162.08:08:11.23#ibcon#read 4, iclass 24, count 2 2006.162.08:08:11.23#ibcon#about to read 5, iclass 24, count 2 2006.162.08:08:11.23#ibcon#read 5, iclass 24, count 2 2006.162.08:08:11.23#ibcon#about to read 6, iclass 24, count 2 2006.162.08:08:11.23#ibcon#read 6, iclass 24, count 2 2006.162.08:08:11.23#ibcon#end of sib2, iclass 24, count 2 2006.162.08:08:11.23#ibcon#*after write, iclass 24, count 2 2006.162.08:08:11.23#ibcon#*before return 0, iclass 24, count 2 2006.162.08:08:11.23#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:08:11.23#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:08:11.23#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.162.08:08:11.23#ibcon#ireg 7 cls_cnt 0 2006.162.08:08:11.23#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:08:11.35#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:08:11.35#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:08:11.35#ibcon#enter wrdev, iclass 24, count 0 2006.162.08:08:11.35#ibcon#first serial, iclass 24, count 0 2006.162.08:08:11.35#ibcon#enter sib2, iclass 24, count 0 2006.162.08:08:11.35#ibcon#flushed, iclass 24, count 0 2006.162.08:08:11.35#ibcon#about to write, iclass 24, count 0 2006.162.08:08:11.35#ibcon#wrote, iclass 24, count 0 2006.162.08:08:11.35#ibcon#about to read 3, iclass 24, count 0 2006.162.08:08:11.37#ibcon#read 3, iclass 24, count 0 2006.162.08:08:11.37#ibcon#about to read 4, iclass 24, count 0 2006.162.08:08:11.37#ibcon#read 4, iclass 24, count 0 2006.162.08:08:11.37#ibcon#about to read 5, iclass 24, count 0 2006.162.08:08:11.37#ibcon#read 5, iclass 24, count 0 2006.162.08:08:11.37#ibcon#about to read 6, iclass 24, count 0 2006.162.08:08:11.37#ibcon#read 6, iclass 24, count 0 2006.162.08:08:11.37#ibcon#end of sib2, iclass 24, count 0 2006.162.08:08:11.37#ibcon#*mode == 0, iclass 24, count 0 2006.162.08:08:11.37#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.08:08:11.37#ibcon#[25=USB\r\n] 2006.162.08:08:11.37#ibcon#*before write, iclass 24, count 0 2006.162.08:08:11.37#ibcon#enter sib2, iclass 24, count 0 2006.162.08:08:11.37#ibcon#flushed, iclass 24, count 0 2006.162.08:08:11.37#ibcon#about to write, iclass 24, count 0 2006.162.08:08:11.37#ibcon#wrote, iclass 24, count 0 2006.162.08:08:11.37#ibcon#about to read 3, iclass 24, count 0 2006.162.08:08:11.40#ibcon#read 3, iclass 24, count 0 2006.162.08:08:11.40#ibcon#about to read 4, iclass 24, count 0 2006.162.08:08:11.40#ibcon#read 4, iclass 24, count 0 2006.162.08:08:11.40#ibcon#about to read 5, iclass 24, count 0 2006.162.08:08:11.40#ibcon#read 5, iclass 24, count 0 2006.162.08:08:11.40#ibcon#about to read 6, iclass 24, count 0 2006.162.08:08:11.40#ibcon#read 6, iclass 24, count 0 2006.162.08:08:11.40#ibcon#end of sib2, iclass 24, count 0 2006.162.08:08:11.40#ibcon#*after write, iclass 24, count 0 2006.162.08:08:11.40#ibcon#*before return 0, iclass 24, count 0 2006.162.08:08:11.40#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:08:11.40#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:08:11.40#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.08:08:11.40#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.08:08:11.40$vc4f8/valo=8,852.99 2006.162.08:08:11.40#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.162.08:08:11.40#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.162.08:08:11.40#ibcon#ireg 17 cls_cnt 0 2006.162.08:08:11.40#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:08:11.40#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:08:11.40#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:08:11.40#ibcon#enter wrdev, iclass 26, count 0 2006.162.08:08:11.40#ibcon#first serial, iclass 26, count 0 2006.162.08:08:11.40#ibcon#enter sib2, iclass 26, count 0 2006.162.08:08:11.40#ibcon#flushed, iclass 26, count 0 2006.162.08:08:11.40#ibcon#about to write, iclass 26, count 0 2006.162.08:08:11.40#ibcon#wrote, iclass 26, count 0 2006.162.08:08:11.40#ibcon#about to read 3, iclass 26, count 0 2006.162.08:08:11.43#ibcon#read 3, iclass 26, count 0 2006.162.08:08:11.43#ibcon#about to read 4, iclass 26, count 0 2006.162.08:08:11.43#ibcon#read 4, iclass 26, count 0 2006.162.08:08:11.43#ibcon#about to read 5, iclass 26, count 0 2006.162.08:08:11.43#ibcon#read 5, iclass 26, count 0 2006.162.08:08:11.43#ibcon#about to read 6, iclass 26, count 0 2006.162.08:08:11.43#ibcon#read 6, iclass 26, count 0 2006.162.08:08:11.43#ibcon#end of sib2, iclass 26, count 0 2006.162.08:08:11.43#ibcon#*mode == 0, iclass 26, count 0 2006.162.08:08:11.43#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.162.08:08:11.43#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.08:08:11.43#ibcon#*before write, iclass 26, count 0 2006.162.08:08:11.43#ibcon#enter sib2, iclass 26, count 0 2006.162.08:08:11.43#ibcon#flushed, iclass 26, count 0 2006.162.08:08:11.43#ibcon#about to write, iclass 26, count 0 2006.162.08:08:11.43#ibcon#wrote, iclass 26, count 0 2006.162.08:08:11.43#ibcon#about to read 3, iclass 26, count 0 2006.162.08:08:11.47#ibcon#read 3, iclass 26, count 0 2006.162.08:08:11.47#ibcon#about to read 4, iclass 26, count 0 2006.162.08:08:11.47#ibcon#read 4, iclass 26, count 0 2006.162.08:08:11.47#ibcon#about to read 5, iclass 26, count 0 2006.162.08:08:11.47#ibcon#read 5, iclass 26, count 0 2006.162.08:08:11.47#ibcon#about to read 6, iclass 26, count 0 2006.162.08:08:11.47#ibcon#read 6, iclass 26, count 0 2006.162.08:08:11.47#ibcon#end of sib2, iclass 26, count 0 2006.162.08:08:11.47#ibcon#*after write, iclass 26, count 0 2006.162.08:08:11.47#ibcon#*before return 0, iclass 26, count 0 2006.162.08:08:11.47#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:08:11.47#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:08:11.47#ibcon#about to clear, iclass 26 cls_cnt 0 2006.162.08:08:11.47#ibcon#cleared, iclass 26 cls_cnt 0 2006.162.08:08:11.47$vc4f8/va=8,7 2006.162.08:08:11.47#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.162.08:08:11.47#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.162.08:08:11.47#ibcon#ireg 11 cls_cnt 2 2006.162.08:08:11.47#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:08:11.52#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:08:11.52#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:08:11.52#ibcon#enter wrdev, iclass 28, count 2 2006.162.08:08:11.52#ibcon#first serial, iclass 28, count 2 2006.162.08:08:11.52#ibcon#enter sib2, iclass 28, count 2 2006.162.08:08:11.52#ibcon#flushed, iclass 28, count 2 2006.162.08:08:11.52#ibcon#about to write, iclass 28, count 2 2006.162.08:08:11.52#ibcon#wrote, iclass 28, count 2 2006.162.08:08:11.52#ibcon#about to read 3, iclass 28, count 2 2006.162.08:08:11.54#ibcon#read 3, iclass 28, count 2 2006.162.08:08:11.54#ibcon#about to read 4, iclass 28, count 2 2006.162.08:08:11.54#ibcon#read 4, iclass 28, count 2 2006.162.08:08:11.54#ibcon#about to read 5, iclass 28, count 2 2006.162.08:08:11.54#ibcon#read 5, iclass 28, count 2 2006.162.08:08:11.54#ibcon#about to read 6, iclass 28, count 2 2006.162.08:08:11.54#ibcon#read 6, iclass 28, count 2 2006.162.08:08:11.54#ibcon#end of sib2, iclass 28, count 2 2006.162.08:08:11.54#ibcon#*mode == 0, iclass 28, count 2 2006.162.08:08:11.54#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.162.08:08:11.54#ibcon#[25=AT08-07\r\n] 2006.162.08:08:11.54#ibcon#*before write, iclass 28, count 2 2006.162.08:08:11.54#ibcon#enter sib2, iclass 28, count 2 2006.162.08:08:11.54#ibcon#flushed, iclass 28, count 2 2006.162.08:08:11.54#ibcon#about to write, iclass 28, count 2 2006.162.08:08:11.54#ibcon#wrote, iclass 28, count 2 2006.162.08:08:11.54#ibcon#about to read 3, iclass 28, count 2 2006.162.08:08:11.57#ibcon#read 3, iclass 28, count 2 2006.162.08:08:11.57#ibcon#about to read 4, iclass 28, count 2 2006.162.08:08:11.57#ibcon#read 4, iclass 28, count 2 2006.162.08:08:11.57#ibcon#about to read 5, iclass 28, count 2 2006.162.08:08:11.57#ibcon#read 5, iclass 28, count 2 2006.162.08:08:11.57#ibcon#about to read 6, iclass 28, count 2 2006.162.08:08:11.57#ibcon#read 6, iclass 28, count 2 2006.162.08:08:11.57#ibcon#end of sib2, iclass 28, count 2 2006.162.08:08:11.57#ibcon#*after write, iclass 28, count 2 2006.162.08:08:11.57#ibcon#*before return 0, iclass 28, count 2 2006.162.08:08:11.57#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:08:11.57#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:08:11.57#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.162.08:08:11.57#ibcon#ireg 7 cls_cnt 0 2006.162.08:08:11.57#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:08:11.69#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:08:11.69#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:08:11.69#ibcon#enter wrdev, iclass 28, count 0 2006.162.08:08:11.69#ibcon#first serial, iclass 28, count 0 2006.162.08:08:11.69#ibcon#enter sib2, iclass 28, count 0 2006.162.08:08:11.69#ibcon#flushed, iclass 28, count 0 2006.162.08:08:11.69#ibcon#about to write, iclass 28, count 0 2006.162.08:08:11.69#ibcon#wrote, iclass 28, count 0 2006.162.08:08:11.69#ibcon#about to read 3, iclass 28, count 0 2006.162.08:08:11.71#ibcon#read 3, iclass 28, count 0 2006.162.08:08:11.71#ibcon#about to read 4, iclass 28, count 0 2006.162.08:08:11.71#ibcon#read 4, iclass 28, count 0 2006.162.08:08:11.71#ibcon#about to read 5, iclass 28, count 0 2006.162.08:08:11.71#ibcon#read 5, iclass 28, count 0 2006.162.08:08:11.71#ibcon#about to read 6, iclass 28, count 0 2006.162.08:08:11.71#ibcon#read 6, iclass 28, count 0 2006.162.08:08:11.71#ibcon#end of sib2, iclass 28, count 0 2006.162.08:08:11.71#ibcon#*mode == 0, iclass 28, count 0 2006.162.08:08:11.71#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.162.08:08:11.71#ibcon#[25=USB\r\n] 2006.162.08:08:11.71#ibcon#*before write, iclass 28, count 0 2006.162.08:08:11.71#ibcon#enter sib2, iclass 28, count 0 2006.162.08:08:11.71#ibcon#flushed, iclass 28, count 0 2006.162.08:08:11.71#ibcon#about to write, iclass 28, count 0 2006.162.08:08:11.71#ibcon#wrote, iclass 28, count 0 2006.162.08:08:11.71#ibcon#about to read 3, iclass 28, count 0 2006.162.08:08:11.74#ibcon#read 3, iclass 28, count 0 2006.162.08:08:11.74#ibcon#about to read 4, iclass 28, count 0 2006.162.08:08:11.74#ibcon#read 4, iclass 28, count 0 2006.162.08:08:11.74#ibcon#about to read 5, iclass 28, count 0 2006.162.08:08:11.74#ibcon#read 5, iclass 28, count 0 2006.162.08:08:11.74#ibcon#about to read 6, iclass 28, count 0 2006.162.08:08:11.74#ibcon#read 6, iclass 28, count 0 2006.162.08:08:11.74#ibcon#end of sib2, iclass 28, count 0 2006.162.08:08:11.74#ibcon#*after write, iclass 28, count 0 2006.162.08:08:11.74#ibcon#*before return 0, iclass 28, count 0 2006.162.08:08:11.74#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:08:11.74#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:08:11.74#ibcon#about to clear, iclass 28 cls_cnt 0 2006.162.08:08:11.74#ibcon#cleared, iclass 28 cls_cnt 0 2006.162.08:08:11.74$vc4f8/vblo=1,632.99 2006.162.08:08:11.74#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.162.08:08:11.74#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.162.08:08:11.74#ibcon#ireg 17 cls_cnt 0 2006.162.08:08:11.74#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:08:11.74#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:08:11.74#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:08:11.74#ibcon#enter wrdev, iclass 30, count 0 2006.162.08:08:11.74#ibcon#first serial, iclass 30, count 0 2006.162.08:08:11.74#ibcon#enter sib2, iclass 30, count 0 2006.162.08:08:11.74#ibcon#flushed, iclass 30, count 0 2006.162.08:08:11.74#ibcon#about to write, iclass 30, count 0 2006.162.08:08:11.74#ibcon#wrote, iclass 30, count 0 2006.162.08:08:11.74#ibcon#about to read 3, iclass 30, count 0 2006.162.08:08:11.76#ibcon#read 3, iclass 30, count 0 2006.162.08:08:11.76#ibcon#about to read 4, iclass 30, count 0 2006.162.08:08:11.76#ibcon#read 4, iclass 30, count 0 2006.162.08:08:11.76#ibcon#about to read 5, iclass 30, count 0 2006.162.08:08:11.76#ibcon#read 5, iclass 30, count 0 2006.162.08:08:11.76#ibcon#about to read 6, iclass 30, count 0 2006.162.08:08:11.76#ibcon#read 6, iclass 30, count 0 2006.162.08:08:11.76#ibcon#end of sib2, iclass 30, count 0 2006.162.08:08:11.76#ibcon#*mode == 0, iclass 30, count 0 2006.162.08:08:11.76#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.162.08:08:11.76#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.08:08:11.76#ibcon#*before write, iclass 30, count 0 2006.162.08:08:11.76#ibcon#enter sib2, iclass 30, count 0 2006.162.08:08:11.76#ibcon#flushed, iclass 30, count 0 2006.162.08:08:11.76#ibcon#about to write, iclass 30, count 0 2006.162.08:08:11.76#ibcon#wrote, iclass 30, count 0 2006.162.08:08:11.76#ibcon#about to read 3, iclass 30, count 0 2006.162.08:08:11.80#ibcon#read 3, iclass 30, count 0 2006.162.08:08:11.80#ibcon#about to read 4, iclass 30, count 0 2006.162.08:08:11.80#ibcon#read 4, iclass 30, count 0 2006.162.08:08:11.80#ibcon#about to read 5, iclass 30, count 0 2006.162.08:08:11.80#ibcon#read 5, iclass 30, count 0 2006.162.08:08:11.80#ibcon#about to read 6, iclass 30, count 0 2006.162.08:08:11.80#ibcon#read 6, iclass 30, count 0 2006.162.08:08:11.80#ibcon#end of sib2, iclass 30, count 0 2006.162.08:08:11.80#ibcon#*after write, iclass 30, count 0 2006.162.08:08:11.80#ibcon#*before return 0, iclass 30, count 0 2006.162.08:08:11.80#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:08:11.80#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:08:11.80#ibcon#about to clear, iclass 30 cls_cnt 0 2006.162.08:08:11.80#ibcon#cleared, iclass 30 cls_cnt 0 2006.162.08:08:11.80$vc4f8/vb=1,4 2006.162.08:08:11.80#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.162.08:08:11.80#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.162.08:08:11.80#ibcon#ireg 11 cls_cnt 2 2006.162.08:08:11.80#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.162.08:08:11.80#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.162.08:08:11.80#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.162.08:08:11.80#ibcon#enter wrdev, iclass 32, count 2 2006.162.08:08:11.80#ibcon#first serial, iclass 32, count 2 2006.162.08:08:11.80#ibcon#enter sib2, iclass 32, count 2 2006.162.08:08:11.80#ibcon#flushed, iclass 32, count 2 2006.162.08:08:11.80#ibcon#about to write, iclass 32, count 2 2006.162.08:08:11.80#ibcon#wrote, iclass 32, count 2 2006.162.08:08:11.80#ibcon#about to read 3, iclass 32, count 2 2006.162.08:08:11.82#ibcon#read 3, iclass 32, count 2 2006.162.08:08:11.82#ibcon#about to read 4, iclass 32, count 2 2006.162.08:08:11.82#ibcon#read 4, iclass 32, count 2 2006.162.08:08:11.82#ibcon#about to read 5, iclass 32, count 2 2006.162.08:08:11.82#ibcon#read 5, iclass 32, count 2 2006.162.08:08:11.82#ibcon#about to read 6, iclass 32, count 2 2006.162.08:08:11.82#ibcon#read 6, iclass 32, count 2 2006.162.08:08:11.82#ibcon#end of sib2, iclass 32, count 2 2006.162.08:08:11.82#ibcon#*mode == 0, iclass 32, count 2 2006.162.08:08:11.82#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.162.08:08:11.82#ibcon#[27=AT01-04\r\n] 2006.162.08:08:11.82#ibcon#*before write, iclass 32, count 2 2006.162.08:08:11.82#ibcon#enter sib2, iclass 32, count 2 2006.162.08:08:11.82#ibcon#flushed, iclass 32, count 2 2006.162.08:08:11.82#ibcon#about to write, iclass 32, count 2 2006.162.08:08:11.82#ibcon#wrote, iclass 32, count 2 2006.162.08:08:11.82#ibcon#about to read 3, iclass 32, count 2 2006.162.08:08:11.85#ibcon#read 3, iclass 32, count 2 2006.162.08:08:11.85#ibcon#about to read 4, iclass 32, count 2 2006.162.08:08:11.85#ibcon#read 4, iclass 32, count 2 2006.162.08:08:11.85#ibcon#about to read 5, iclass 32, count 2 2006.162.08:08:11.85#ibcon#read 5, iclass 32, count 2 2006.162.08:08:11.85#ibcon#about to read 6, iclass 32, count 2 2006.162.08:08:11.85#ibcon#read 6, iclass 32, count 2 2006.162.08:08:11.85#ibcon#end of sib2, iclass 32, count 2 2006.162.08:08:11.85#ibcon#*after write, iclass 32, count 2 2006.162.08:08:11.85#ibcon#*before return 0, iclass 32, count 2 2006.162.08:08:11.85#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.162.08:08:11.85#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.162.08:08:11.85#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.162.08:08:11.85#ibcon#ireg 7 cls_cnt 0 2006.162.08:08:11.85#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.162.08:08:11.97#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.162.08:08:11.97#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.162.08:08:11.97#ibcon#enter wrdev, iclass 32, count 0 2006.162.08:08:11.97#ibcon#first serial, iclass 32, count 0 2006.162.08:08:11.97#ibcon#enter sib2, iclass 32, count 0 2006.162.08:08:11.97#ibcon#flushed, iclass 32, count 0 2006.162.08:08:11.97#ibcon#about to write, iclass 32, count 0 2006.162.08:08:11.97#ibcon#wrote, iclass 32, count 0 2006.162.08:08:11.97#ibcon#about to read 3, iclass 32, count 0 2006.162.08:08:11.99#ibcon#read 3, iclass 32, count 0 2006.162.08:08:11.99#ibcon#about to read 4, iclass 32, count 0 2006.162.08:08:11.99#ibcon#read 4, iclass 32, count 0 2006.162.08:08:11.99#ibcon#about to read 5, iclass 32, count 0 2006.162.08:08:11.99#ibcon#read 5, iclass 32, count 0 2006.162.08:08:11.99#ibcon#about to read 6, iclass 32, count 0 2006.162.08:08:11.99#ibcon#read 6, iclass 32, count 0 2006.162.08:08:11.99#ibcon#end of sib2, iclass 32, count 0 2006.162.08:08:11.99#ibcon#*mode == 0, iclass 32, count 0 2006.162.08:08:11.99#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.162.08:08:11.99#ibcon#[27=USB\r\n] 2006.162.08:08:11.99#ibcon#*before write, iclass 32, count 0 2006.162.08:08:11.99#ibcon#enter sib2, iclass 32, count 0 2006.162.08:08:11.99#ibcon#flushed, iclass 32, count 0 2006.162.08:08:11.99#ibcon#about to write, iclass 32, count 0 2006.162.08:08:11.99#ibcon#wrote, iclass 32, count 0 2006.162.08:08:11.99#ibcon#about to read 3, iclass 32, count 0 2006.162.08:08:12.02#ibcon#read 3, iclass 32, count 0 2006.162.08:08:12.02#ibcon#about to read 4, iclass 32, count 0 2006.162.08:08:12.02#ibcon#read 4, iclass 32, count 0 2006.162.08:08:12.02#ibcon#about to read 5, iclass 32, count 0 2006.162.08:08:12.02#ibcon#read 5, iclass 32, count 0 2006.162.08:08:12.02#ibcon#about to read 6, iclass 32, count 0 2006.162.08:08:12.02#ibcon#read 6, iclass 32, count 0 2006.162.08:08:12.02#ibcon#end of sib2, iclass 32, count 0 2006.162.08:08:12.02#ibcon#*after write, iclass 32, count 0 2006.162.08:08:12.02#ibcon#*before return 0, iclass 32, count 0 2006.162.08:08:12.02#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.162.08:08:12.02#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.162.08:08:12.02#ibcon#about to clear, iclass 32 cls_cnt 0 2006.162.08:08:12.02#ibcon#cleared, iclass 32 cls_cnt 0 2006.162.08:08:12.02$vc4f8/vblo=2,640.99 2006.162.08:08:12.02#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.162.08:08:12.02#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.162.08:08:12.02#ibcon#ireg 17 cls_cnt 0 2006.162.08:08:12.02#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:08:12.02#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:08:12.02#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:08:12.02#ibcon#enter wrdev, iclass 34, count 0 2006.162.08:08:12.02#ibcon#first serial, iclass 34, count 0 2006.162.08:08:12.02#ibcon#enter sib2, iclass 34, count 0 2006.162.08:08:12.02#ibcon#flushed, iclass 34, count 0 2006.162.08:08:12.02#ibcon#about to write, iclass 34, count 0 2006.162.08:08:12.02#ibcon#wrote, iclass 34, count 0 2006.162.08:08:12.02#ibcon#about to read 3, iclass 34, count 0 2006.162.08:08:12.04#ibcon#read 3, iclass 34, count 0 2006.162.08:08:12.04#ibcon#about to read 4, iclass 34, count 0 2006.162.08:08:12.04#ibcon#read 4, iclass 34, count 0 2006.162.08:08:12.04#ibcon#about to read 5, iclass 34, count 0 2006.162.08:08:12.04#ibcon#read 5, iclass 34, count 0 2006.162.08:08:12.04#ibcon#about to read 6, iclass 34, count 0 2006.162.08:08:12.04#ibcon#read 6, iclass 34, count 0 2006.162.08:08:12.04#ibcon#end of sib2, iclass 34, count 0 2006.162.08:08:12.04#ibcon#*mode == 0, iclass 34, count 0 2006.162.08:08:12.04#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.162.08:08:12.04#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.08:08:12.04#ibcon#*before write, iclass 34, count 0 2006.162.08:08:12.04#ibcon#enter sib2, iclass 34, count 0 2006.162.08:08:12.04#ibcon#flushed, iclass 34, count 0 2006.162.08:08:12.04#ibcon#about to write, iclass 34, count 0 2006.162.08:08:12.04#ibcon#wrote, iclass 34, count 0 2006.162.08:08:12.04#ibcon#about to read 3, iclass 34, count 0 2006.162.08:08:12.08#ibcon#read 3, iclass 34, count 0 2006.162.08:08:12.08#ibcon#about to read 4, iclass 34, count 0 2006.162.08:08:12.08#ibcon#read 4, iclass 34, count 0 2006.162.08:08:12.08#ibcon#about to read 5, iclass 34, count 0 2006.162.08:08:12.08#ibcon#read 5, iclass 34, count 0 2006.162.08:08:12.08#ibcon#about to read 6, iclass 34, count 0 2006.162.08:08:12.08#ibcon#read 6, iclass 34, count 0 2006.162.08:08:12.08#ibcon#end of sib2, iclass 34, count 0 2006.162.08:08:12.08#ibcon#*after write, iclass 34, count 0 2006.162.08:08:12.08#ibcon#*before return 0, iclass 34, count 0 2006.162.08:08:12.08#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:08:12.08#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:08:12.08#ibcon#about to clear, iclass 34 cls_cnt 0 2006.162.08:08:12.08#ibcon#cleared, iclass 34 cls_cnt 0 2006.162.08:08:12.08$vc4f8/vb=2,4 2006.162.08:08:12.08#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.162.08:08:12.08#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.162.08:08:12.08#ibcon#ireg 11 cls_cnt 2 2006.162.08:08:12.08#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:08:12.14#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:08:12.14#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:08:12.14#ibcon#enter wrdev, iclass 36, count 2 2006.162.08:08:12.14#ibcon#first serial, iclass 36, count 2 2006.162.08:08:12.14#ibcon#enter sib2, iclass 36, count 2 2006.162.08:08:12.14#ibcon#flushed, iclass 36, count 2 2006.162.08:08:12.14#ibcon#about to write, iclass 36, count 2 2006.162.08:08:12.14#ibcon#wrote, iclass 36, count 2 2006.162.08:08:12.14#ibcon#about to read 3, iclass 36, count 2 2006.162.08:08:12.16#ibcon#read 3, iclass 36, count 2 2006.162.08:08:12.16#ibcon#about to read 4, iclass 36, count 2 2006.162.08:08:12.16#ibcon#read 4, iclass 36, count 2 2006.162.08:08:12.16#ibcon#about to read 5, iclass 36, count 2 2006.162.08:08:12.16#ibcon#read 5, iclass 36, count 2 2006.162.08:08:12.16#ibcon#about to read 6, iclass 36, count 2 2006.162.08:08:12.16#ibcon#read 6, iclass 36, count 2 2006.162.08:08:12.16#ibcon#end of sib2, iclass 36, count 2 2006.162.08:08:12.16#ibcon#*mode == 0, iclass 36, count 2 2006.162.08:08:12.16#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.162.08:08:12.16#ibcon#[27=AT02-04\r\n] 2006.162.08:08:12.16#ibcon#*before write, iclass 36, count 2 2006.162.08:08:12.16#ibcon#enter sib2, iclass 36, count 2 2006.162.08:08:12.16#ibcon#flushed, iclass 36, count 2 2006.162.08:08:12.16#ibcon#about to write, iclass 36, count 2 2006.162.08:08:12.16#ibcon#wrote, iclass 36, count 2 2006.162.08:08:12.16#ibcon#about to read 3, iclass 36, count 2 2006.162.08:08:12.19#ibcon#read 3, iclass 36, count 2 2006.162.08:08:12.19#ibcon#about to read 4, iclass 36, count 2 2006.162.08:08:12.19#ibcon#read 4, iclass 36, count 2 2006.162.08:08:12.19#ibcon#about to read 5, iclass 36, count 2 2006.162.08:08:12.19#ibcon#read 5, iclass 36, count 2 2006.162.08:08:12.19#ibcon#about to read 6, iclass 36, count 2 2006.162.08:08:12.19#ibcon#read 6, iclass 36, count 2 2006.162.08:08:12.19#ibcon#end of sib2, iclass 36, count 2 2006.162.08:08:12.19#ibcon#*after write, iclass 36, count 2 2006.162.08:08:12.19#ibcon#*before return 0, iclass 36, count 2 2006.162.08:08:12.19#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:08:12.19#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:08:12.19#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.162.08:08:12.19#ibcon#ireg 7 cls_cnt 0 2006.162.08:08:12.19#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:08:12.31#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:08:12.31#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:08:12.31#ibcon#enter wrdev, iclass 36, count 0 2006.162.08:08:12.31#ibcon#first serial, iclass 36, count 0 2006.162.08:08:12.31#ibcon#enter sib2, iclass 36, count 0 2006.162.08:08:12.31#ibcon#flushed, iclass 36, count 0 2006.162.08:08:12.31#ibcon#about to write, iclass 36, count 0 2006.162.08:08:12.31#ibcon#wrote, iclass 36, count 0 2006.162.08:08:12.31#ibcon#about to read 3, iclass 36, count 0 2006.162.08:08:12.33#ibcon#read 3, iclass 36, count 0 2006.162.08:08:12.33#ibcon#about to read 4, iclass 36, count 0 2006.162.08:08:12.33#ibcon#read 4, iclass 36, count 0 2006.162.08:08:12.33#ibcon#about to read 5, iclass 36, count 0 2006.162.08:08:12.33#ibcon#read 5, iclass 36, count 0 2006.162.08:08:12.33#ibcon#about to read 6, iclass 36, count 0 2006.162.08:08:12.33#ibcon#read 6, iclass 36, count 0 2006.162.08:08:12.33#ibcon#end of sib2, iclass 36, count 0 2006.162.08:08:12.33#ibcon#*mode == 0, iclass 36, count 0 2006.162.08:08:12.33#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.162.08:08:12.33#ibcon#[27=USB\r\n] 2006.162.08:08:12.33#ibcon#*before write, iclass 36, count 0 2006.162.08:08:12.33#ibcon#enter sib2, iclass 36, count 0 2006.162.08:08:12.33#ibcon#flushed, iclass 36, count 0 2006.162.08:08:12.33#ibcon#about to write, iclass 36, count 0 2006.162.08:08:12.33#ibcon#wrote, iclass 36, count 0 2006.162.08:08:12.33#ibcon#about to read 3, iclass 36, count 0 2006.162.08:08:12.36#ibcon#read 3, iclass 36, count 0 2006.162.08:08:12.36#ibcon#about to read 4, iclass 36, count 0 2006.162.08:08:12.36#ibcon#read 4, iclass 36, count 0 2006.162.08:08:12.36#ibcon#about to read 5, iclass 36, count 0 2006.162.08:08:12.36#ibcon#read 5, iclass 36, count 0 2006.162.08:08:12.36#ibcon#about to read 6, iclass 36, count 0 2006.162.08:08:12.36#ibcon#read 6, iclass 36, count 0 2006.162.08:08:12.36#ibcon#end of sib2, iclass 36, count 0 2006.162.08:08:12.36#ibcon#*after write, iclass 36, count 0 2006.162.08:08:12.36#ibcon#*before return 0, iclass 36, count 0 2006.162.08:08:12.36#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:08:12.36#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:08:12.36#ibcon#about to clear, iclass 36 cls_cnt 0 2006.162.08:08:12.36#ibcon#cleared, iclass 36 cls_cnt 0 2006.162.08:08:12.36$vc4f8/vblo=3,656.99 2006.162.08:08:12.36#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.162.08:08:12.36#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.162.08:08:12.36#ibcon#ireg 17 cls_cnt 0 2006.162.08:08:12.36#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.162.08:08:12.36#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.162.08:08:12.36#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.162.08:08:12.36#ibcon#enter wrdev, iclass 38, count 0 2006.162.08:08:12.36#ibcon#first serial, iclass 38, count 0 2006.162.08:08:12.36#ibcon#enter sib2, iclass 38, count 0 2006.162.08:08:12.36#ibcon#flushed, iclass 38, count 0 2006.162.08:08:12.36#ibcon#about to write, iclass 38, count 0 2006.162.08:08:12.36#ibcon#wrote, iclass 38, count 0 2006.162.08:08:12.36#ibcon#about to read 3, iclass 38, count 0 2006.162.08:08:12.38#ibcon#read 3, iclass 38, count 0 2006.162.08:08:12.38#ibcon#about to read 4, iclass 38, count 0 2006.162.08:08:12.38#ibcon#read 4, iclass 38, count 0 2006.162.08:08:12.38#ibcon#about to read 5, iclass 38, count 0 2006.162.08:08:12.38#ibcon#read 5, iclass 38, count 0 2006.162.08:08:12.38#ibcon#about to read 6, iclass 38, count 0 2006.162.08:08:12.38#ibcon#read 6, iclass 38, count 0 2006.162.08:08:12.38#ibcon#end of sib2, iclass 38, count 0 2006.162.08:08:12.38#ibcon#*mode == 0, iclass 38, count 0 2006.162.08:08:12.38#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.162.08:08:12.38#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.08:08:12.38#ibcon#*before write, iclass 38, count 0 2006.162.08:08:12.38#ibcon#enter sib2, iclass 38, count 0 2006.162.08:08:12.38#ibcon#flushed, iclass 38, count 0 2006.162.08:08:12.38#ibcon#about to write, iclass 38, count 0 2006.162.08:08:12.38#ibcon#wrote, iclass 38, count 0 2006.162.08:08:12.38#ibcon#about to read 3, iclass 38, count 0 2006.162.08:08:12.42#abcon#<5=/03 1.8 3.6 17.841001007.1\r\n> 2006.162.08:08:12.42#ibcon#read 3, iclass 38, count 0 2006.162.08:08:12.42#ibcon#about to read 4, iclass 38, count 0 2006.162.08:08:12.42#ibcon#read 4, iclass 38, count 0 2006.162.08:08:12.42#ibcon#about to read 5, iclass 38, count 0 2006.162.08:08:12.42#ibcon#read 5, iclass 38, count 0 2006.162.08:08:12.42#ibcon#about to read 6, iclass 38, count 0 2006.162.08:08:12.42#ibcon#read 6, iclass 38, count 0 2006.162.08:08:12.42#ibcon#end of sib2, iclass 38, count 0 2006.162.08:08:12.42#ibcon#*after write, iclass 38, count 0 2006.162.08:08:12.42#ibcon#*before return 0, iclass 38, count 0 2006.162.08:08:12.42#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.162.08:08:12.42#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.162.08:08:12.42#ibcon#about to clear, iclass 38 cls_cnt 0 2006.162.08:08:12.42#ibcon#cleared, iclass 38 cls_cnt 0 2006.162.08:08:12.42$vc4f8/vb=3,4 2006.162.08:08:12.42#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.162.08:08:12.42#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.162.08:08:12.42#ibcon#ireg 11 cls_cnt 2 2006.162.08:08:12.42#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.162.08:08:12.44#abcon#{5=INTERFACE CLEAR} 2006.162.08:08:12.48#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.162.08:08:12.48#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.162.08:08:12.48#ibcon#enter wrdev, iclass 5, count 2 2006.162.08:08:12.48#ibcon#first serial, iclass 5, count 2 2006.162.08:08:12.48#ibcon#enter sib2, iclass 5, count 2 2006.162.08:08:12.48#ibcon#flushed, iclass 5, count 2 2006.162.08:08:12.48#ibcon#about to write, iclass 5, count 2 2006.162.08:08:12.48#ibcon#wrote, iclass 5, count 2 2006.162.08:08:12.48#ibcon#about to read 3, iclass 5, count 2 2006.162.08:08:12.50#ibcon#read 3, iclass 5, count 2 2006.162.08:08:12.50#ibcon#about to read 4, iclass 5, count 2 2006.162.08:08:12.50#ibcon#read 4, iclass 5, count 2 2006.162.08:08:12.50#ibcon#about to read 5, iclass 5, count 2 2006.162.08:08:12.50#ibcon#read 5, iclass 5, count 2 2006.162.08:08:12.50#ibcon#about to read 6, iclass 5, count 2 2006.162.08:08:12.50#ibcon#read 6, iclass 5, count 2 2006.162.08:08:12.50#ibcon#end of sib2, iclass 5, count 2 2006.162.08:08:12.50#ibcon#*mode == 0, iclass 5, count 2 2006.162.08:08:12.50#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.162.08:08:12.50#ibcon#[27=AT03-04\r\n] 2006.162.08:08:12.50#ibcon#*before write, iclass 5, count 2 2006.162.08:08:12.50#ibcon#enter sib2, iclass 5, count 2 2006.162.08:08:12.50#ibcon#flushed, iclass 5, count 2 2006.162.08:08:12.50#ibcon#about to write, iclass 5, count 2 2006.162.08:08:12.50#ibcon#wrote, iclass 5, count 2 2006.162.08:08:12.50#ibcon#about to read 3, iclass 5, count 2 2006.162.08:08:12.50#abcon#[5=S1D000X0/0*\r\n] 2006.162.08:08:12.53#ibcon#read 3, iclass 5, count 2 2006.162.08:08:12.53#ibcon#about to read 4, iclass 5, count 2 2006.162.08:08:12.53#ibcon#read 4, iclass 5, count 2 2006.162.08:08:12.53#ibcon#about to read 5, iclass 5, count 2 2006.162.08:08:12.53#ibcon#read 5, iclass 5, count 2 2006.162.08:08:12.53#ibcon#about to read 6, iclass 5, count 2 2006.162.08:08:12.53#ibcon#read 6, iclass 5, count 2 2006.162.08:08:12.53#ibcon#end of sib2, iclass 5, count 2 2006.162.08:08:12.53#ibcon#*after write, iclass 5, count 2 2006.162.08:08:12.53#ibcon#*before return 0, iclass 5, count 2 2006.162.08:08:12.53#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.162.08:08:12.53#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.162.08:08:12.53#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.162.08:08:12.53#ibcon#ireg 7 cls_cnt 0 2006.162.08:08:12.53#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.162.08:08:12.65#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.162.08:08:12.65#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.162.08:08:12.65#ibcon#enter wrdev, iclass 5, count 0 2006.162.08:08:12.65#ibcon#first serial, iclass 5, count 0 2006.162.08:08:12.65#ibcon#enter sib2, iclass 5, count 0 2006.162.08:08:12.65#ibcon#flushed, iclass 5, count 0 2006.162.08:08:12.65#ibcon#about to write, iclass 5, count 0 2006.162.08:08:12.65#ibcon#wrote, iclass 5, count 0 2006.162.08:08:12.65#ibcon#about to read 3, iclass 5, count 0 2006.162.08:08:12.67#ibcon#read 3, iclass 5, count 0 2006.162.08:08:12.67#ibcon#about to read 4, iclass 5, count 0 2006.162.08:08:12.67#ibcon#read 4, iclass 5, count 0 2006.162.08:08:12.67#ibcon#about to read 5, iclass 5, count 0 2006.162.08:08:12.67#ibcon#read 5, iclass 5, count 0 2006.162.08:08:12.67#ibcon#about to read 6, iclass 5, count 0 2006.162.08:08:12.67#ibcon#read 6, iclass 5, count 0 2006.162.08:08:12.67#ibcon#end of sib2, iclass 5, count 0 2006.162.08:08:12.67#ibcon#*mode == 0, iclass 5, count 0 2006.162.08:08:12.67#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.162.08:08:12.67#ibcon#[27=USB\r\n] 2006.162.08:08:12.67#ibcon#*before write, iclass 5, count 0 2006.162.08:08:12.67#ibcon#enter sib2, iclass 5, count 0 2006.162.08:08:12.67#ibcon#flushed, iclass 5, count 0 2006.162.08:08:12.67#ibcon#about to write, iclass 5, count 0 2006.162.08:08:12.67#ibcon#wrote, iclass 5, count 0 2006.162.08:08:12.67#ibcon#about to read 3, iclass 5, count 0 2006.162.08:08:12.70#ibcon#read 3, iclass 5, count 0 2006.162.08:08:12.70#ibcon#about to read 4, iclass 5, count 0 2006.162.08:08:12.70#ibcon#read 4, iclass 5, count 0 2006.162.08:08:12.70#ibcon#about to read 5, iclass 5, count 0 2006.162.08:08:12.70#ibcon#read 5, iclass 5, count 0 2006.162.08:08:12.70#ibcon#about to read 6, iclass 5, count 0 2006.162.08:08:12.70#ibcon#read 6, iclass 5, count 0 2006.162.08:08:12.70#ibcon#end of sib2, iclass 5, count 0 2006.162.08:08:12.70#ibcon#*after write, iclass 5, count 0 2006.162.08:08:12.70#ibcon#*before return 0, iclass 5, count 0 2006.162.08:08:12.70#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.162.08:08:12.70#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.162.08:08:12.70#ibcon#about to clear, iclass 5 cls_cnt 0 2006.162.08:08:12.70#ibcon#cleared, iclass 5 cls_cnt 0 2006.162.08:08:12.70$vc4f8/vblo=4,712.99 2006.162.08:08:12.70#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.162.08:08:12.70#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.162.08:08:12.70#ibcon#ireg 17 cls_cnt 0 2006.162.08:08:12.70#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:08:12.70#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:08:12.70#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:08:12.70#ibcon#enter wrdev, iclass 10, count 0 2006.162.08:08:12.70#ibcon#first serial, iclass 10, count 0 2006.162.08:08:12.70#ibcon#enter sib2, iclass 10, count 0 2006.162.08:08:12.70#ibcon#flushed, iclass 10, count 0 2006.162.08:08:12.70#ibcon#about to write, iclass 10, count 0 2006.162.08:08:12.70#ibcon#wrote, iclass 10, count 0 2006.162.08:08:12.70#ibcon#about to read 3, iclass 10, count 0 2006.162.08:08:12.72#ibcon#read 3, iclass 10, count 0 2006.162.08:08:12.72#ibcon#about to read 4, iclass 10, count 0 2006.162.08:08:12.72#ibcon#read 4, iclass 10, count 0 2006.162.08:08:12.72#ibcon#about to read 5, iclass 10, count 0 2006.162.08:08:12.72#ibcon#read 5, iclass 10, count 0 2006.162.08:08:12.72#ibcon#about to read 6, iclass 10, count 0 2006.162.08:08:12.72#ibcon#read 6, iclass 10, count 0 2006.162.08:08:12.72#ibcon#end of sib2, iclass 10, count 0 2006.162.08:08:12.72#ibcon#*mode == 0, iclass 10, count 0 2006.162.08:08:12.72#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.162.08:08:12.72#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.08:08:12.72#ibcon#*before write, iclass 10, count 0 2006.162.08:08:12.72#ibcon#enter sib2, iclass 10, count 0 2006.162.08:08:12.72#ibcon#flushed, iclass 10, count 0 2006.162.08:08:12.72#ibcon#about to write, iclass 10, count 0 2006.162.08:08:12.72#ibcon#wrote, iclass 10, count 0 2006.162.08:08:12.72#ibcon#about to read 3, iclass 10, count 0 2006.162.08:08:12.76#ibcon#read 3, iclass 10, count 0 2006.162.08:08:12.76#ibcon#about to read 4, iclass 10, count 0 2006.162.08:08:12.76#ibcon#read 4, iclass 10, count 0 2006.162.08:08:12.76#ibcon#about to read 5, iclass 10, count 0 2006.162.08:08:12.76#ibcon#read 5, iclass 10, count 0 2006.162.08:08:12.76#ibcon#about to read 6, iclass 10, count 0 2006.162.08:08:12.76#ibcon#read 6, iclass 10, count 0 2006.162.08:08:12.76#ibcon#end of sib2, iclass 10, count 0 2006.162.08:08:12.76#ibcon#*after write, iclass 10, count 0 2006.162.08:08:12.76#ibcon#*before return 0, iclass 10, count 0 2006.162.08:08:12.76#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:08:12.76#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:08:12.76#ibcon#about to clear, iclass 10 cls_cnt 0 2006.162.08:08:12.76#ibcon#cleared, iclass 10 cls_cnt 0 2006.162.08:08:12.76$vc4f8/vb=4,4 2006.162.08:08:12.76#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.162.08:08:12.76#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.162.08:08:12.76#ibcon#ireg 11 cls_cnt 2 2006.162.08:08:12.76#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:08:12.82#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:08:12.82#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:08:12.82#ibcon#enter wrdev, iclass 12, count 2 2006.162.08:08:12.82#ibcon#first serial, iclass 12, count 2 2006.162.08:08:12.82#ibcon#enter sib2, iclass 12, count 2 2006.162.08:08:12.82#ibcon#flushed, iclass 12, count 2 2006.162.08:08:12.82#ibcon#about to write, iclass 12, count 2 2006.162.08:08:12.82#ibcon#wrote, iclass 12, count 2 2006.162.08:08:12.82#ibcon#about to read 3, iclass 12, count 2 2006.162.08:08:12.84#ibcon#read 3, iclass 12, count 2 2006.162.08:08:12.84#ibcon#about to read 4, iclass 12, count 2 2006.162.08:08:12.84#ibcon#read 4, iclass 12, count 2 2006.162.08:08:12.84#ibcon#about to read 5, iclass 12, count 2 2006.162.08:08:12.84#ibcon#read 5, iclass 12, count 2 2006.162.08:08:12.84#ibcon#about to read 6, iclass 12, count 2 2006.162.08:08:12.84#ibcon#read 6, iclass 12, count 2 2006.162.08:08:12.84#ibcon#end of sib2, iclass 12, count 2 2006.162.08:08:12.84#ibcon#*mode == 0, iclass 12, count 2 2006.162.08:08:12.84#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.162.08:08:12.84#ibcon#[27=AT04-04\r\n] 2006.162.08:08:12.84#ibcon#*before write, iclass 12, count 2 2006.162.08:08:12.84#ibcon#enter sib2, iclass 12, count 2 2006.162.08:08:12.84#ibcon#flushed, iclass 12, count 2 2006.162.08:08:12.84#ibcon#about to write, iclass 12, count 2 2006.162.08:08:12.84#ibcon#wrote, iclass 12, count 2 2006.162.08:08:12.84#ibcon#about to read 3, iclass 12, count 2 2006.162.08:08:12.87#ibcon#read 3, iclass 12, count 2 2006.162.08:08:12.87#ibcon#about to read 4, iclass 12, count 2 2006.162.08:08:12.87#ibcon#read 4, iclass 12, count 2 2006.162.08:08:12.87#ibcon#about to read 5, iclass 12, count 2 2006.162.08:08:12.87#ibcon#read 5, iclass 12, count 2 2006.162.08:08:12.87#ibcon#about to read 6, iclass 12, count 2 2006.162.08:08:12.87#ibcon#read 6, iclass 12, count 2 2006.162.08:08:12.87#ibcon#end of sib2, iclass 12, count 2 2006.162.08:08:12.87#ibcon#*after write, iclass 12, count 2 2006.162.08:08:12.87#ibcon#*before return 0, iclass 12, count 2 2006.162.08:08:12.87#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:08:12.87#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:08:12.87#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.162.08:08:12.87#ibcon#ireg 7 cls_cnt 0 2006.162.08:08:12.87#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:08:12.99#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:08:12.99#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:08:12.99#ibcon#enter wrdev, iclass 12, count 0 2006.162.08:08:12.99#ibcon#first serial, iclass 12, count 0 2006.162.08:08:12.99#ibcon#enter sib2, iclass 12, count 0 2006.162.08:08:12.99#ibcon#flushed, iclass 12, count 0 2006.162.08:08:12.99#ibcon#about to write, iclass 12, count 0 2006.162.08:08:12.99#ibcon#wrote, iclass 12, count 0 2006.162.08:08:12.99#ibcon#about to read 3, iclass 12, count 0 2006.162.08:08:13.01#ibcon#read 3, iclass 12, count 0 2006.162.08:08:13.01#ibcon#about to read 4, iclass 12, count 0 2006.162.08:08:13.01#ibcon#read 4, iclass 12, count 0 2006.162.08:08:13.01#ibcon#about to read 5, iclass 12, count 0 2006.162.08:08:13.01#ibcon#read 5, iclass 12, count 0 2006.162.08:08:13.01#ibcon#about to read 6, iclass 12, count 0 2006.162.08:08:13.01#ibcon#read 6, iclass 12, count 0 2006.162.08:08:13.01#ibcon#end of sib2, iclass 12, count 0 2006.162.08:08:13.01#ibcon#*mode == 0, iclass 12, count 0 2006.162.08:08:13.01#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.162.08:08:13.01#ibcon#[27=USB\r\n] 2006.162.08:08:13.01#ibcon#*before write, iclass 12, count 0 2006.162.08:08:13.01#ibcon#enter sib2, iclass 12, count 0 2006.162.08:08:13.01#ibcon#flushed, iclass 12, count 0 2006.162.08:08:13.01#ibcon#about to write, iclass 12, count 0 2006.162.08:08:13.01#ibcon#wrote, iclass 12, count 0 2006.162.08:08:13.01#ibcon#about to read 3, iclass 12, count 0 2006.162.08:08:13.04#ibcon#read 3, iclass 12, count 0 2006.162.08:08:13.04#ibcon#about to read 4, iclass 12, count 0 2006.162.08:08:13.04#ibcon#read 4, iclass 12, count 0 2006.162.08:08:13.04#ibcon#about to read 5, iclass 12, count 0 2006.162.08:08:13.04#ibcon#read 5, iclass 12, count 0 2006.162.08:08:13.04#ibcon#about to read 6, iclass 12, count 0 2006.162.08:08:13.04#ibcon#read 6, iclass 12, count 0 2006.162.08:08:13.04#ibcon#end of sib2, iclass 12, count 0 2006.162.08:08:13.04#ibcon#*after write, iclass 12, count 0 2006.162.08:08:13.04#ibcon#*before return 0, iclass 12, count 0 2006.162.08:08:13.04#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:08:13.04#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:08:13.04#ibcon#about to clear, iclass 12 cls_cnt 0 2006.162.08:08:13.04#ibcon#cleared, iclass 12 cls_cnt 0 2006.162.08:08:13.04$vc4f8/vblo=5,744.99 2006.162.08:08:13.04#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.162.08:08:13.04#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.162.08:08:13.04#ibcon#ireg 17 cls_cnt 0 2006.162.08:08:13.04#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:08:13.04#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:08:13.04#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:08:13.04#ibcon#enter wrdev, iclass 14, count 0 2006.162.08:08:13.04#ibcon#first serial, iclass 14, count 0 2006.162.08:08:13.04#ibcon#enter sib2, iclass 14, count 0 2006.162.08:08:13.04#ibcon#flushed, iclass 14, count 0 2006.162.08:08:13.04#ibcon#about to write, iclass 14, count 0 2006.162.08:08:13.04#ibcon#wrote, iclass 14, count 0 2006.162.08:08:13.04#ibcon#about to read 3, iclass 14, count 0 2006.162.08:08:13.06#ibcon#read 3, iclass 14, count 0 2006.162.08:08:13.06#ibcon#about to read 4, iclass 14, count 0 2006.162.08:08:13.06#ibcon#read 4, iclass 14, count 0 2006.162.08:08:13.06#ibcon#about to read 5, iclass 14, count 0 2006.162.08:08:13.06#ibcon#read 5, iclass 14, count 0 2006.162.08:08:13.06#ibcon#about to read 6, iclass 14, count 0 2006.162.08:08:13.06#ibcon#read 6, iclass 14, count 0 2006.162.08:08:13.06#ibcon#end of sib2, iclass 14, count 0 2006.162.08:08:13.06#ibcon#*mode == 0, iclass 14, count 0 2006.162.08:08:13.06#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.08:08:13.06#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.08:08:13.06#ibcon#*before write, iclass 14, count 0 2006.162.08:08:13.06#ibcon#enter sib2, iclass 14, count 0 2006.162.08:08:13.06#ibcon#flushed, iclass 14, count 0 2006.162.08:08:13.06#ibcon#about to write, iclass 14, count 0 2006.162.08:08:13.06#ibcon#wrote, iclass 14, count 0 2006.162.08:08:13.06#ibcon#about to read 3, iclass 14, count 0 2006.162.08:08:13.10#ibcon#read 3, iclass 14, count 0 2006.162.08:08:13.10#ibcon#about to read 4, iclass 14, count 0 2006.162.08:08:13.10#ibcon#read 4, iclass 14, count 0 2006.162.08:08:13.10#ibcon#about to read 5, iclass 14, count 0 2006.162.08:08:13.10#ibcon#read 5, iclass 14, count 0 2006.162.08:08:13.10#ibcon#about to read 6, iclass 14, count 0 2006.162.08:08:13.10#ibcon#read 6, iclass 14, count 0 2006.162.08:08:13.10#ibcon#end of sib2, iclass 14, count 0 2006.162.08:08:13.10#ibcon#*after write, iclass 14, count 0 2006.162.08:08:13.10#ibcon#*before return 0, iclass 14, count 0 2006.162.08:08:13.10#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:08:13.10#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:08:13.10#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.08:08:13.10#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.08:08:13.10$vc4f8/vb=5,4 2006.162.08:08:13.10#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.162.08:08:13.10#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.162.08:08:13.10#ibcon#ireg 11 cls_cnt 2 2006.162.08:08:13.10#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:08:13.16#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:08:13.16#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:08:13.16#ibcon#enter wrdev, iclass 16, count 2 2006.162.08:08:13.16#ibcon#first serial, iclass 16, count 2 2006.162.08:08:13.16#ibcon#enter sib2, iclass 16, count 2 2006.162.08:08:13.16#ibcon#flushed, iclass 16, count 2 2006.162.08:08:13.16#ibcon#about to write, iclass 16, count 2 2006.162.08:08:13.16#ibcon#wrote, iclass 16, count 2 2006.162.08:08:13.16#ibcon#about to read 3, iclass 16, count 2 2006.162.08:08:13.18#ibcon#read 3, iclass 16, count 2 2006.162.08:08:13.18#ibcon#about to read 4, iclass 16, count 2 2006.162.08:08:13.18#ibcon#read 4, iclass 16, count 2 2006.162.08:08:13.18#ibcon#about to read 5, iclass 16, count 2 2006.162.08:08:13.18#ibcon#read 5, iclass 16, count 2 2006.162.08:08:13.18#ibcon#about to read 6, iclass 16, count 2 2006.162.08:08:13.18#ibcon#read 6, iclass 16, count 2 2006.162.08:08:13.18#ibcon#end of sib2, iclass 16, count 2 2006.162.08:08:13.18#ibcon#*mode == 0, iclass 16, count 2 2006.162.08:08:13.18#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.162.08:08:13.18#ibcon#[27=AT05-04\r\n] 2006.162.08:08:13.18#ibcon#*before write, iclass 16, count 2 2006.162.08:08:13.18#ibcon#enter sib2, iclass 16, count 2 2006.162.08:08:13.18#ibcon#flushed, iclass 16, count 2 2006.162.08:08:13.18#ibcon#about to write, iclass 16, count 2 2006.162.08:08:13.18#ibcon#wrote, iclass 16, count 2 2006.162.08:08:13.18#ibcon#about to read 3, iclass 16, count 2 2006.162.08:08:13.21#ibcon#read 3, iclass 16, count 2 2006.162.08:08:13.21#ibcon#about to read 4, iclass 16, count 2 2006.162.08:08:13.21#ibcon#read 4, iclass 16, count 2 2006.162.08:08:13.21#ibcon#about to read 5, iclass 16, count 2 2006.162.08:08:13.21#ibcon#read 5, iclass 16, count 2 2006.162.08:08:13.21#ibcon#about to read 6, iclass 16, count 2 2006.162.08:08:13.21#ibcon#read 6, iclass 16, count 2 2006.162.08:08:13.21#ibcon#end of sib2, iclass 16, count 2 2006.162.08:08:13.21#ibcon#*after write, iclass 16, count 2 2006.162.08:08:13.21#ibcon#*before return 0, iclass 16, count 2 2006.162.08:08:13.21#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:08:13.21#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:08:13.21#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.162.08:08:13.21#ibcon#ireg 7 cls_cnt 0 2006.162.08:08:13.21#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:08:13.33#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:08:13.33#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:08:13.33#ibcon#enter wrdev, iclass 16, count 0 2006.162.08:08:13.33#ibcon#first serial, iclass 16, count 0 2006.162.08:08:13.33#ibcon#enter sib2, iclass 16, count 0 2006.162.08:08:13.33#ibcon#flushed, iclass 16, count 0 2006.162.08:08:13.33#ibcon#about to write, iclass 16, count 0 2006.162.08:08:13.33#ibcon#wrote, iclass 16, count 0 2006.162.08:08:13.33#ibcon#about to read 3, iclass 16, count 0 2006.162.08:08:13.35#ibcon#read 3, iclass 16, count 0 2006.162.08:08:13.35#ibcon#about to read 4, iclass 16, count 0 2006.162.08:08:13.35#ibcon#read 4, iclass 16, count 0 2006.162.08:08:13.35#ibcon#about to read 5, iclass 16, count 0 2006.162.08:08:13.35#ibcon#read 5, iclass 16, count 0 2006.162.08:08:13.35#ibcon#about to read 6, iclass 16, count 0 2006.162.08:08:13.35#ibcon#read 6, iclass 16, count 0 2006.162.08:08:13.35#ibcon#end of sib2, iclass 16, count 0 2006.162.08:08:13.35#ibcon#*mode == 0, iclass 16, count 0 2006.162.08:08:13.35#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.162.08:08:13.35#ibcon#[27=USB\r\n] 2006.162.08:08:13.35#ibcon#*before write, iclass 16, count 0 2006.162.08:08:13.35#ibcon#enter sib2, iclass 16, count 0 2006.162.08:08:13.35#ibcon#flushed, iclass 16, count 0 2006.162.08:08:13.35#ibcon#about to write, iclass 16, count 0 2006.162.08:08:13.35#ibcon#wrote, iclass 16, count 0 2006.162.08:08:13.35#ibcon#about to read 3, iclass 16, count 0 2006.162.08:08:13.38#ibcon#read 3, iclass 16, count 0 2006.162.08:08:13.38#ibcon#about to read 4, iclass 16, count 0 2006.162.08:08:13.38#ibcon#read 4, iclass 16, count 0 2006.162.08:08:13.38#ibcon#about to read 5, iclass 16, count 0 2006.162.08:08:13.38#ibcon#read 5, iclass 16, count 0 2006.162.08:08:13.38#ibcon#about to read 6, iclass 16, count 0 2006.162.08:08:13.38#ibcon#read 6, iclass 16, count 0 2006.162.08:08:13.38#ibcon#end of sib2, iclass 16, count 0 2006.162.08:08:13.38#ibcon#*after write, iclass 16, count 0 2006.162.08:08:13.38#ibcon#*before return 0, iclass 16, count 0 2006.162.08:08:13.38#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:08:13.38#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:08:13.38#ibcon#about to clear, iclass 16 cls_cnt 0 2006.162.08:08:13.38#ibcon#cleared, iclass 16 cls_cnt 0 2006.162.08:08:13.38$vc4f8/vblo=6,752.99 2006.162.08:08:13.38#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.162.08:08:13.38#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.162.08:08:13.38#ibcon#ireg 17 cls_cnt 0 2006.162.08:08:13.38#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:08:13.38#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:08:13.38#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:08:13.38#ibcon#enter wrdev, iclass 18, count 0 2006.162.08:08:13.38#ibcon#first serial, iclass 18, count 0 2006.162.08:08:13.38#ibcon#enter sib2, iclass 18, count 0 2006.162.08:08:13.38#ibcon#flushed, iclass 18, count 0 2006.162.08:08:13.38#ibcon#about to write, iclass 18, count 0 2006.162.08:08:13.38#ibcon#wrote, iclass 18, count 0 2006.162.08:08:13.38#ibcon#about to read 3, iclass 18, count 0 2006.162.08:08:13.40#ibcon#read 3, iclass 18, count 0 2006.162.08:08:13.40#ibcon#about to read 4, iclass 18, count 0 2006.162.08:08:13.40#ibcon#read 4, iclass 18, count 0 2006.162.08:08:13.40#ibcon#about to read 5, iclass 18, count 0 2006.162.08:08:13.40#ibcon#read 5, iclass 18, count 0 2006.162.08:08:13.40#ibcon#about to read 6, iclass 18, count 0 2006.162.08:08:13.40#ibcon#read 6, iclass 18, count 0 2006.162.08:08:13.40#ibcon#end of sib2, iclass 18, count 0 2006.162.08:08:13.40#ibcon#*mode == 0, iclass 18, count 0 2006.162.08:08:13.40#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.162.08:08:13.40#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.08:08:13.40#ibcon#*before write, iclass 18, count 0 2006.162.08:08:13.40#ibcon#enter sib2, iclass 18, count 0 2006.162.08:08:13.40#ibcon#flushed, iclass 18, count 0 2006.162.08:08:13.40#ibcon#about to write, iclass 18, count 0 2006.162.08:08:13.40#ibcon#wrote, iclass 18, count 0 2006.162.08:08:13.40#ibcon#about to read 3, iclass 18, count 0 2006.162.08:08:13.44#ibcon#read 3, iclass 18, count 0 2006.162.08:08:13.44#ibcon#about to read 4, iclass 18, count 0 2006.162.08:08:13.44#ibcon#read 4, iclass 18, count 0 2006.162.08:08:13.44#ibcon#about to read 5, iclass 18, count 0 2006.162.08:08:13.44#ibcon#read 5, iclass 18, count 0 2006.162.08:08:13.44#ibcon#about to read 6, iclass 18, count 0 2006.162.08:08:13.44#ibcon#read 6, iclass 18, count 0 2006.162.08:08:13.44#ibcon#end of sib2, iclass 18, count 0 2006.162.08:08:13.44#ibcon#*after write, iclass 18, count 0 2006.162.08:08:13.44#ibcon#*before return 0, iclass 18, count 0 2006.162.08:08:13.44#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:08:13.44#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:08:13.44#ibcon#about to clear, iclass 18 cls_cnt 0 2006.162.08:08:13.44#ibcon#cleared, iclass 18 cls_cnt 0 2006.162.08:08:13.44$vc4f8/vb=6,4 2006.162.08:08:13.44#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.162.08:08:13.44#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.162.08:08:13.44#ibcon#ireg 11 cls_cnt 2 2006.162.08:08:13.44#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:08:13.50#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:08:13.50#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:08:13.50#ibcon#enter wrdev, iclass 20, count 2 2006.162.08:08:13.50#ibcon#first serial, iclass 20, count 2 2006.162.08:08:13.50#ibcon#enter sib2, iclass 20, count 2 2006.162.08:08:13.50#ibcon#flushed, iclass 20, count 2 2006.162.08:08:13.50#ibcon#about to write, iclass 20, count 2 2006.162.08:08:13.50#ibcon#wrote, iclass 20, count 2 2006.162.08:08:13.50#ibcon#about to read 3, iclass 20, count 2 2006.162.08:08:13.52#ibcon#read 3, iclass 20, count 2 2006.162.08:08:13.52#ibcon#about to read 4, iclass 20, count 2 2006.162.08:08:13.52#ibcon#read 4, iclass 20, count 2 2006.162.08:08:13.52#ibcon#about to read 5, iclass 20, count 2 2006.162.08:08:13.52#ibcon#read 5, iclass 20, count 2 2006.162.08:08:13.52#ibcon#about to read 6, iclass 20, count 2 2006.162.08:08:13.52#ibcon#read 6, iclass 20, count 2 2006.162.08:08:13.52#ibcon#end of sib2, iclass 20, count 2 2006.162.08:08:13.52#ibcon#*mode == 0, iclass 20, count 2 2006.162.08:08:13.52#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.162.08:08:13.52#ibcon#[27=AT06-04\r\n] 2006.162.08:08:13.52#ibcon#*before write, iclass 20, count 2 2006.162.08:08:13.52#ibcon#enter sib2, iclass 20, count 2 2006.162.08:08:13.52#ibcon#flushed, iclass 20, count 2 2006.162.08:08:13.52#ibcon#about to write, iclass 20, count 2 2006.162.08:08:13.52#ibcon#wrote, iclass 20, count 2 2006.162.08:08:13.52#ibcon#about to read 3, iclass 20, count 2 2006.162.08:08:13.55#ibcon#read 3, iclass 20, count 2 2006.162.08:08:13.55#ibcon#about to read 4, iclass 20, count 2 2006.162.08:08:13.55#ibcon#read 4, iclass 20, count 2 2006.162.08:08:13.55#ibcon#about to read 5, iclass 20, count 2 2006.162.08:08:13.55#ibcon#read 5, iclass 20, count 2 2006.162.08:08:13.55#ibcon#about to read 6, iclass 20, count 2 2006.162.08:08:13.55#ibcon#read 6, iclass 20, count 2 2006.162.08:08:13.55#ibcon#end of sib2, iclass 20, count 2 2006.162.08:08:13.55#ibcon#*after write, iclass 20, count 2 2006.162.08:08:13.55#ibcon#*before return 0, iclass 20, count 2 2006.162.08:08:13.55#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:08:13.55#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:08:13.55#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.162.08:08:13.55#ibcon#ireg 7 cls_cnt 0 2006.162.08:08:13.55#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:08:13.67#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:08:13.67#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:08:13.67#ibcon#enter wrdev, iclass 20, count 0 2006.162.08:08:13.67#ibcon#first serial, iclass 20, count 0 2006.162.08:08:13.67#ibcon#enter sib2, iclass 20, count 0 2006.162.08:08:13.67#ibcon#flushed, iclass 20, count 0 2006.162.08:08:13.67#ibcon#about to write, iclass 20, count 0 2006.162.08:08:13.67#ibcon#wrote, iclass 20, count 0 2006.162.08:08:13.67#ibcon#about to read 3, iclass 20, count 0 2006.162.08:08:13.69#ibcon#read 3, iclass 20, count 0 2006.162.08:08:13.69#ibcon#about to read 4, iclass 20, count 0 2006.162.08:08:13.69#ibcon#read 4, iclass 20, count 0 2006.162.08:08:13.69#ibcon#about to read 5, iclass 20, count 0 2006.162.08:08:13.69#ibcon#read 5, iclass 20, count 0 2006.162.08:08:13.69#ibcon#about to read 6, iclass 20, count 0 2006.162.08:08:13.69#ibcon#read 6, iclass 20, count 0 2006.162.08:08:13.69#ibcon#end of sib2, iclass 20, count 0 2006.162.08:08:13.69#ibcon#*mode == 0, iclass 20, count 0 2006.162.08:08:13.69#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.08:08:13.69#ibcon#[27=USB\r\n] 2006.162.08:08:13.69#ibcon#*before write, iclass 20, count 0 2006.162.08:08:13.69#ibcon#enter sib2, iclass 20, count 0 2006.162.08:08:13.69#ibcon#flushed, iclass 20, count 0 2006.162.08:08:13.69#ibcon#about to write, iclass 20, count 0 2006.162.08:08:13.69#ibcon#wrote, iclass 20, count 0 2006.162.08:08:13.69#ibcon#about to read 3, iclass 20, count 0 2006.162.08:08:13.72#ibcon#read 3, iclass 20, count 0 2006.162.08:08:13.72#ibcon#about to read 4, iclass 20, count 0 2006.162.08:08:13.72#ibcon#read 4, iclass 20, count 0 2006.162.08:08:13.72#ibcon#about to read 5, iclass 20, count 0 2006.162.08:08:13.72#ibcon#read 5, iclass 20, count 0 2006.162.08:08:13.72#ibcon#about to read 6, iclass 20, count 0 2006.162.08:08:13.72#ibcon#read 6, iclass 20, count 0 2006.162.08:08:13.72#ibcon#end of sib2, iclass 20, count 0 2006.162.08:08:13.72#ibcon#*after write, iclass 20, count 0 2006.162.08:08:13.72#ibcon#*before return 0, iclass 20, count 0 2006.162.08:08:13.72#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:08:13.72#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:08:13.72#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.08:08:13.72#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.08:08:13.72$vc4f8/vabw=wide 2006.162.08:08:13.72#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.162.08:08:13.72#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.162.08:08:13.72#ibcon#ireg 8 cls_cnt 0 2006.162.08:08:13.72#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:08:13.72#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:08:13.72#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:08:13.72#ibcon#enter wrdev, iclass 22, count 0 2006.162.08:08:13.72#ibcon#first serial, iclass 22, count 0 2006.162.08:08:13.72#ibcon#enter sib2, iclass 22, count 0 2006.162.08:08:13.72#ibcon#flushed, iclass 22, count 0 2006.162.08:08:13.72#ibcon#about to write, iclass 22, count 0 2006.162.08:08:13.72#ibcon#wrote, iclass 22, count 0 2006.162.08:08:13.72#ibcon#about to read 3, iclass 22, count 0 2006.162.08:08:13.74#ibcon#read 3, iclass 22, count 0 2006.162.08:08:13.74#ibcon#about to read 4, iclass 22, count 0 2006.162.08:08:13.74#ibcon#read 4, iclass 22, count 0 2006.162.08:08:13.74#ibcon#about to read 5, iclass 22, count 0 2006.162.08:08:13.74#ibcon#read 5, iclass 22, count 0 2006.162.08:08:13.74#ibcon#about to read 6, iclass 22, count 0 2006.162.08:08:13.74#ibcon#read 6, iclass 22, count 0 2006.162.08:08:13.74#ibcon#end of sib2, iclass 22, count 0 2006.162.08:08:13.74#ibcon#*mode == 0, iclass 22, count 0 2006.162.08:08:13.74#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.08:08:13.74#ibcon#[25=BW32\r\n] 2006.162.08:08:13.74#ibcon#*before write, iclass 22, count 0 2006.162.08:08:13.74#ibcon#enter sib2, iclass 22, count 0 2006.162.08:08:13.74#ibcon#flushed, iclass 22, count 0 2006.162.08:08:13.74#ibcon#about to write, iclass 22, count 0 2006.162.08:08:13.74#ibcon#wrote, iclass 22, count 0 2006.162.08:08:13.74#ibcon#about to read 3, iclass 22, count 0 2006.162.08:08:13.77#ibcon#read 3, iclass 22, count 0 2006.162.08:08:13.77#ibcon#about to read 4, iclass 22, count 0 2006.162.08:08:13.77#ibcon#read 4, iclass 22, count 0 2006.162.08:08:13.77#ibcon#about to read 5, iclass 22, count 0 2006.162.08:08:13.77#ibcon#read 5, iclass 22, count 0 2006.162.08:08:13.77#ibcon#about to read 6, iclass 22, count 0 2006.162.08:08:13.77#ibcon#read 6, iclass 22, count 0 2006.162.08:08:13.77#ibcon#end of sib2, iclass 22, count 0 2006.162.08:08:13.77#ibcon#*after write, iclass 22, count 0 2006.162.08:08:13.77#ibcon#*before return 0, iclass 22, count 0 2006.162.08:08:13.77#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:08:13.77#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:08:13.77#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.08:08:13.77#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.08:08:13.77$vc4f8/vbbw=wide 2006.162.08:08:13.77#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.162.08:08:13.77#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.162.08:08:13.77#ibcon#ireg 8 cls_cnt 0 2006.162.08:08:13.77#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:08:13.84#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:08:13.84#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:08:13.84#ibcon#enter wrdev, iclass 24, count 0 2006.162.08:08:13.84#ibcon#first serial, iclass 24, count 0 2006.162.08:08:13.84#ibcon#enter sib2, iclass 24, count 0 2006.162.08:08:13.84#ibcon#flushed, iclass 24, count 0 2006.162.08:08:13.84#ibcon#about to write, iclass 24, count 0 2006.162.08:08:13.84#ibcon#wrote, iclass 24, count 0 2006.162.08:08:13.84#ibcon#about to read 3, iclass 24, count 0 2006.162.08:08:13.86#ibcon#read 3, iclass 24, count 0 2006.162.08:08:13.86#ibcon#about to read 4, iclass 24, count 0 2006.162.08:08:13.86#ibcon#read 4, iclass 24, count 0 2006.162.08:08:13.86#ibcon#about to read 5, iclass 24, count 0 2006.162.08:08:13.86#ibcon#read 5, iclass 24, count 0 2006.162.08:08:13.86#ibcon#about to read 6, iclass 24, count 0 2006.162.08:08:13.86#ibcon#read 6, iclass 24, count 0 2006.162.08:08:13.86#ibcon#end of sib2, iclass 24, count 0 2006.162.08:08:13.86#ibcon#*mode == 0, iclass 24, count 0 2006.162.08:08:13.86#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.08:08:13.86#ibcon#[27=BW32\r\n] 2006.162.08:08:13.86#ibcon#*before write, iclass 24, count 0 2006.162.08:08:13.86#ibcon#enter sib2, iclass 24, count 0 2006.162.08:08:13.86#ibcon#flushed, iclass 24, count 0 2006.162.08:08:13.86#ibcon#about to write, iclass 24, count 0 2006.162.08:08:13.86#ibcon#wrote, iclass 24, count 0 2006.162.08:08:13.86#ibcon#about to read 3, iclass 24, count 0 2006.162.08:08:13.89#ibcon#read 3, iclass 24, count 0 2006.162.08:08:13.89#ibcon#about to read 4, iclass 24, count 0 2006.162.08:08:13.89#ibcon#read 4, iclass 24, count 0 2006.162.08:08:13.89#ibcon#about to read 5, iclass 24, count 0 2006.162.08:08:13.89#ibcon#read 5, iclass 24, count 0 2006.162.08:08:13.89#ibcon#about to read 6, iclass 24, count 0 2006.162.08:08:13.89#ibcon#read 6, iclass 24, count 0 2006.162.08:08:13.89#ibcon#end of sib2, iclass 24, count 0 2006.162.08:08:13.89#ibcon#*after write, iclass 24, count 0 2006.162.08:08:13.89#ibcon#*before return 0, iclass 24, count 0 2006.162.08:08:13.89#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:08:13.89#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:08:13.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.08:08:13.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.08:08:13.89$4f8m12a/ifd4f 2006.162.08:08:13.89$ifd4f/lo= 2006.162.08:08:13.89$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.08:08:13.89$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.08:08:13.89$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.08:08:13.89$ifd4f/patch= 2006.162.08:08:13.89$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.08:08:13.89$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.08:08:13.89$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.08:08:13.89$4f8m12a/"form=m,16.000,1:2 2006.162.08:08:13.89$4f8m12a/"tpicd 2006.162.08:08:13.89$4f8m12a/echo=off 2006.162.08:08:13.89$4f8m12a/xlog=off 2006.162.08:08:13.89:!2006.162.08:08:40 2006.162.08:08:25.14#trakl#Source acquired 2006.162.08:08:25.14#flagr#flagr/antenna,acquired 2006.162.08:08:40.00:preob 2006.162.08:08:41.14/onsource/TRACKING 2006.162.08:08:41.14:!2006.162.08:08:50 2006.162.08:08:50.00:data_valid=on 2006.162.08:08:50.00:midob 2006.162.08:08:50.14/onsource/TRACKING 2006.162.08:08:50.14/wx/17.84,1007.0,100 2006.162.08:08:50.28/cable/+6.5376E-03 2006.162.08:08:51.37/va/01,08,usb,yes,35,37 2006.162.08:08:51.37/va/02,07,usb,yes,35,37 2006.162.08:08:51.37/va/03,06,usb,yes,37,38 2006.162.08:08:51.37/va/04,07,usb,yes,36,39 2006.162.08:08:51.37/va/05,07,usb,yes,39,41 2006.162.08:08:51.37/va/06,06,usb,yes,38,37 2006.162.08:08:51.37/va/07,06,usb,yes,38,38 2006.162.08:08:51.37/va/08,07,usb,yes,36,36 2006.162.08:08:51.60/valo/01,532.99,yes,locked 2006.162.08:08:51.60/valo/02,572.99,yes,locked 2006.162.08:08:51.60/valo/03,672.99,yes,locked 2006.162.08:08:51.60/valo/04,832.99,yes,locked 2006.162.08:08:51.60/valo/05,652.99,yes,locked 2006.162.08:08:51.60/valo/06,772.99,yes,locked 2006.162.08:08:51.60/valo/07,832.99,yes,locked 2006.162.08:08:51.60/valo/08,852.99,yes,locked 2006.162.08:08:52.69/vb/01,04,usb,yes,29,28 2006.162.08:08:52.69/vb/02,04,usb,yes,31,32 2006.162.08:08:52.69/vb/03,04,usb,yes,27,31 2006.162.08:08:52.69/vb/04,04,usb,yes,28,28 2006.162.08:08:52.69/vb/05,04,usb,yes,27,31 2006.162.08:08:52.69/vb/06,04,usb,yes,28,30 2006.162.08:08:52.69/vb/07,04,usb,yes,30,29 2006.162.08:08:52.69/vb/08,04,usb,yes,27,30 2006.162.08:08:52.92/vblo/01,632.99,yes,locked 2006.162.08:08:52.92/vblo/02,640.99,yes,locked 2006.162.08:08:52.92/vblo/03,656.99,yes,locked 2006.162.08:08:52.92/vblo/04,712.99,yes,locked 2006.162.08:08:52.92/vblo/05,744.99,yes,locked 2006.162.08:08:52.92/vblo/06,752.99,yes,locked 2006.162.08:08:52.92/vblo/07,734.99,yes,locked 2006.162.08:08:52.92/vblo/08,744.99,yes,locked 2006.162.08:08:53.07/vabw/8 2006.162.08:08:53.22/vbbw/8 2006.162.08:08:53.31/xfe/off,on,15.0 2006.162.08:08:53.68/ifatt/23,28,28,28 2006.162.08:08:54.08/fmout-gps/S +4.48E-07 2006.162.08:08:54.12:!2006.162.08:09:50 2006.162.08:09:50.01:data_valid=off 2006.162.08:09:50.02:postob 2006.162.08:09:50.24/cable/+6.5349E-03 2006.162.08:09:50.24/wx/17.83,1007.1,100 2006.162.08:09:51.08/fmout-gps/S +4.50E-07 2006.162.08:09:51.08:scan_name=162-0811,k06162,130 2006.162.08:09:51.09:source=0722+145,072516.81,142513.7,2000.0,ccw 2006.162.08:09:51.14#flagr#flagr/antenna,new-source 2006.162.08:09:52.14:checkk5 2006.162.08:09:52.59/chk_autoobs//k5ts1/ autoobs is running! 2006.162.08:09:53.06/chk_autoobs//k5ts2/ autoobs is running! 2006.162.08:09:53.49/chk_autoobs//k5ts3/ autoobs is running! 2006.162.08:09:53.92/chk_autoobs//k5ts4/ autoobs is running! 2006.162.08:09:54.35/chk_obsdata//k5ts1/T1620808??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:09:54.78/chk_obsdata//k5ts2/T1620808??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:09:55.25/chk_obsdata//k5ts3/T1620808??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:09:55.69/chk_obsdata//k5ts4/T1620808??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:09:56.53/k5log//k5ts1_log_newline 2006.162.08:09:57.31/k5log//k5ts2_log_newline 2006.162.08:09:58.26/k5log//k5ts3_log_newline 2006.162.08:10:02.00/k5log//k5ts4_log_newline 2006.162.08:10:02.02/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.08:10:02.02:4f8m12a=2 2006.162.08:10:02.02$4f8m12a/echo=on 2006.162.08:10:02.02$4f8m12a/pcalon 2006.162.08:10:02.02$pcalon/"no phase cal control is implemented here 2006.162.08:10:02.02$4f8m12a/"tpicd=stop 2006.162.08:10:02.02$4f8m12a/vc4f8 2006.162.08:10:02.02$vc4f8/valo=1,532.99 2006.162.08:10:02.03#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.162.08:10:02.03#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.162.08:10:02.03#ibcon#ireg 17 cls_cnt 0 2006.162.08:10:02.03#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.162.08:10:02.03#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.162.08:10:02.03#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.162.08:10:02.03#ibcon#enter wrdev, iclass 31, count 0 2006.162.08:10:02.03#ibcon#first serial, iclass 31, count 0 2006.162.08:10:02.03#ibcon#enter sib2, iclass 31, count 0 2006.162.08:10:02.03#ibcon#flushed, iclass 31, count 0 2006.162.08:10:02.03#ibcon#about to write, iclass 31, count 0 2006.162.08:10:02.03#ibcon#wrote, iclass 31, count 0 2006.162.08:10:02.03#ibcon#about to read 3, iclass 31, count 0 2006.162.08:10:02.07#ibcon#read 3, iclass 31, count 0 2006.162.08:10:02.07#ibcon#about to read 4, iclass 31, count 0 2006.162.08:10:02.07#ibcon#read 4, iclass 31, count 0 2006.162.08:10:02.07#ibcon#about to read 5, iclass 31, count 0 2006.162.08:10:02.07#ibcon#read 5, iclass 31, count 0 2006.162.08:10:02.07#ibcon#about to read 6, iclass 31, count 0 2006.162.08:10:02.07#ibcon#read 6, iclass 31, count 0 2006.162.08:10:02.07#ibcon#end of sib2, iclass 31, count 0 2006.162.08:10:02.07#ibcon#*mode == 0, iclass 31, count 0 2006.162.08:10:02.07#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.162.08:10:02.07#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.08:10:02.07#ibcon#*before write, iclass 31, count 0 2006.162.08:10:02.07#ibcon#enter sib2, iclass 31, count 0 2006.162.08:10:02.07#ibcon#flushed, iclass 31, count 0 2006.162.08:10:02.07#ibcon#about to write, iclass 31, count 0 2006.162.08:10:02.07#ibcon#wrote, iclass 31, count 0 2006.162.08:10:02.07#ibcon#about to read 3, iclass 31, count 0 2006.162.08:10:02.11#ibcon#read 3, iclass 31, count 0 2006.162.08:10:02.11#ibcon#about to read 4, iclass 31, count 0 2006.162.08:10:02.11#ibcon#read 4, iclass 31, count 0 2006.162.08:10:02.11#ibcon#about to read 5, iclass 31, count 0 2006.162.08:10:02.11#ibcon#read 5, iclass 31, count 0 2006.162.08:10:02.11#ibcon#about to read 6, iclass 31, count 0 2006.162.08:10:02.11#ibcon#read 6, iclass 31, count 0 2006.162.08:10:02.11#ibcon#end of sib2, iclass 31, count 0 2006.162.08:10:02.11#ibcon#*after write, iclass 31, count 0 2006.162.08:10:02.11#ibcon#*before return 0, iclass 31, count 0 2006.162.08:10:02.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.162.08:10:02.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.162.08:10:02.11#ibcon#about to clear, iclass 31 cls_cnt 0 2006.162.08:10:02.11#ibcon#cleared, iclass 31 cls_cnt 0 2006.162.08:10:02.11$vc4f8/va=1,8 2006.162.08:10:02.11#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.162.08:10:02.11#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.162.08:10:02.11#ibcon#ireg 11 cls_cnt 2 2006.162.08:10:02.11#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.162.08:10:02.11#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.162.08:10:02.11#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.162.08:10:02.11#ibcon#enter wrdev, iclass 33, count 2 2006.162.08:10:02.11#ibcon#first serial, iclass 33, count 2 2006.162.08:10:02.11#ibcon#enter sib2, iclass 33, count 2 2006.162.08:10:02.11#ibcon#flushed, iclass 33, count 2 2006.162.08:10:02.11#ibcon#about to write, iclass 33, count 2 2006.162.08:10:02.11#ibcon#wrote, iclass 33, count 2 2006.162.08:10:02.11#ibcon#about to read 3, iclass 33, count 2 2006.162.08:10:02.13#ibcon#read 3, iclass 33, count 2 2006.162.08:10:02.13#ibcon#about to read 4, iclass 33, count 2 2006.162.08:10:02.13#ibcon#read 4, iclass 33, count 2 2006.162.08:10:02.13#ibcon#about to read 5, iclass 33, count 2 2006.162.08:10:02.13#ibcon#read 5, iclass 33, count 2 2006.162.08:10:02.13#ibcon#about to read 6, iclass 33, count 2 2006.162.08:10:02.13#ibcon#read 6, iclass 33, count 2 2006.162.08:10:02.13#ibcon#end of sib2, iclass 33, count 2 2006.162.08:10:02.13#ibcon#*mode == 0, iclass 33, count 2 2006.162.08:10:02.13#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.162.08:10:02.13#ibcon#[25=AT01-08\r\n] 2006.162.08:10:02.13#ibcon#*before write, iclass 33, count 2 2006.162.08:10:02.13#ibcon#enter sib2, iclass 33, count 2 2006.162.08:10:02.13#ibcon#flushed, iclass 33, count 2 2006.162.08:10:02.13#ibcon#about to write, iclass 33, count 2 2006.162.08:10:02.13#ibcon#wrote, iclass 33, count 2 2006.162.08:10:02.13#ibcon#about to read 3, iclass 33, count 2 2006.162.08:10:02.16#ibcon#read 3, iclass 33, count 2 2006.162.08:10:02.16#ibcon#about to read 4, iclass 33, count 2 2006.162.08:10:02.16#ibcon#read 4, iclass 33, count 2 2006.162.08:10:02.16#ibcon#about to read 5, iclass 33, count 2 2006.162.08:10:02.16#ibcon#read 5, iclass 33, count 2 2006.162.08:10:02.16#ibcon#about to read 6, iclass 33, count 2 2006.162.08:10:02.16#ibcon#read 6, iclass 33, count 2 2006.162.08:10:02.16#ibcon#end of sib2, iclass 33, count 2 2006.162.08:10:02.16#ibcon#*after write, iclass 33, count 2 2006.162.08:10:02.16#ibcon#*before return 0, iclass 33, count 2 2006.162.08:10:02.16#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.162.08:10:02.16#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.162.08:10:02.16#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.162.08:10:02.16#ibcon#ireg 7 cls_cnt 0 2006.162.08:10:02.16#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.162.08:10:02.28#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.162.08:10:02.28#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.162.08:10:02.28#ibcon#enter wrdev, iclass 33, count 0 2006.162.08:10:02.28#ibcon#first serial, iclass 33, count 0 2006.162.08:10:02.28#ibcon#enter sib2, iclass 33, count 0 2006.162.08:10:02.28#ibcon#flushed, iclass 33, count 0 2006.162.08:10:02.28#ibcon#about to write, iclass 33, count 0 2006.162.08:10:02.28#ibcon#wrote, iclass 33, count 0 2006.162.08:10:02.28#ibcon#about to read 3, iclass 33, count 0 2006.162.08:10:02.30#ibcon#read 3, iclass 33, count 0 2006.162.08:10:02.30#ibcon#about to read 4, iclass 33, count 0 2006.162.08:10:02.30#ibcon#read 4, iclass 33, count 0 2006.162.08:10:02.30#ibcon#about to read 5, iclass 33, count 0 2006.162.08:10:02.30#ibcon#read 5, iclass 33, count 0 2006.162.08:10:02.30#ibcon#about to read 6, iclass 33, count 0 2006.162.08:10:02.30#ibcon#read 6, iclass 33, count 0 2006.162.08:10:02.30#ibcon#end of sib2, iclass 33, count 0 2006.162.08:10:02.30#ibcon#*mode == 0, iclass 33, count 0 2006.162.08:10:02.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.162.08:10:02.30#ibcon#[25=USB\r\n] 2006.162.08:10:02.30#ibcon#*before write, iclass 33, count 0 2006.162.08:10:02.30#ibcon#enter sib2, iclass 33, count 0 2006.162.08:10:02.30#ibcon#flushed, iclass 33, count 0 2006.162.08:10:02.30#ibcon#about to write, iclass 33, count 0 2006.162.08:10:02.30#ibcon#wrote, iclass 33, count 0 2006.162.08:10:02.30#ibcon#about to read 3, iclass 33, count 0 2006.162.08:10:02.33#ibcon#read 3, iclass 33, count 0 2006.162.08:10:02.33#ibcon#about to read 4, iclass 33, count 0 2006.162.08:10:02.33#ibcon#read 4, iclass 33, count 0 2006.162.08:10:02.33#ibcon#about to read 5, iclass 33, count 0 2006.162.08:10:02.33#ibcon#read 5, iclass 33, count 0 2006.162.08:10:02.33#ibcon#about to read 6, iclass 33, count 0 2006.162.08:10:02.33#ibcon#read 6, iclass 33, count 0 2006.162.08:10:02.33#ibcon#end of sib2, iclass 33, count 0 2006.162.08:10:02.33#ibcon#*after write, iclass 33, count 0 2006.162.08:10:02.33#ibcon#*before return 0, iclass 33, count 0 2006.162.08:10:02.33#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.162.08:10:02.33#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.162.08:10:02.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.162.08:10:02.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.162.08:10:02.33$vc4f8/valo=2,572.99 2006.162.08:10:02.33#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.162.08:10:02.33#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.162.08:10:02.33#ibcon#ireg 17 cls_cnt 0 2006.162.08:10:02.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.162.08:10:02.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.162.08:10:02.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.162.08:10:02.33#ibcon#enter wrdev, iclass 35, count 0 2006.162.08:10:02.33#ibcon#first serial, iclass 35, count 0 2006.162.08:10:02.33#ibcon#enter sib2, iclass 35, count 0 2006.162.08:10:02.33#ibcon#flushed, iclass 35, count 0 2006.162.08:10:02.33#ibcon#about to write, iclass 35, count 0 2006.162.08:10:02.33#ibcon#wrote, iclass 35, count 0 2006.162.08:10:02.33#ibcon#about to read 3, iclass 35, count 0 2006.162.08:10:02.35#ibcon#read 3, iclass 35, count 0 2006.162.08:10:02.35#ibcon#about to read 4, iclass 35, count 0 2006.162.08:10:02.35#ibcon#read 4, iclass 35, count 0 2006.162.08:10:02.35#ibcon#about to read 5, iclass 35, count 0 2006.162.08:10:02.35#ibcon#read 5, iclass 35, count 0 2006.162.08:10:02.35#ibcon#about to read 6, iclass 35, count 0 2006.162.08:10:02.35#ibcon#read 6, iclass 35, count 0 2006.162.08:10:02.35#ibcon#end of sib2, iclass 35, count 0 2006.162.08:10:02.35#ibcon#*mode == 0, iclass 35, count 0 2006.162.08:10:02.35#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.162.08:10:02.35#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.08:10:02.35#ibcon#*before write, iclass 35, count 0 2006.162.08:10:02.35#ibcon#enter sib2, iclass 35, count 0 2006.162.08:10:02.35#ibcon#flushed, iclass 35, count 0 2006.162.08:10:02.35#ibcon#about to write, iclass 35, count 0 2006.162.08:10:02.35#ibcon#wrote, iclass 35, count 0 2006.162.08:10:02.35#ibcon#about to read 3, iclass 35, count 0 2006.162.08:10:02.39#ibcon#read 3, iclass 35, count 0 2006.162.08:10:02.39#ibcon#about to read 4, iclass 35, count 0 2006.162.08:10:02.39#ibcon#read 4, iclass 35, count 0 2006.162.08:10:02.39#ibcon#about to read 5, iclass 35, count 0 2006.162.08:10:02.39#ibcon#read 5, iclass 35, count 0 2006.162.08:10:02.39#ibcon#about to read 6, iclass 35, count 0 2006.162.08:10:02.39#ibcon#read 6, iclass 35, count 0 2006.162.08:10:02.39#ibcon#end of sib2, iclass 35, count 0 2006.162.08:10:02.39#ibcon#*after write, iclass 35, count 0 2006.162.08:10:02.39#ibcon#*before return 0, iclass 35, count 0 2006.162.08:10:02.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.162.08:10:02.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.162.08:10:02.39#ibcon#about to clear, iclass 35 cls_cnt 0 2006.162.08:10:02.39#ibcon#cleared, iclass 35 cls_cnt 0 2006.162.08:10:02.39$vc4f8/va=2,7 2006.162.08:10:02.39#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.162.08:10:02.39#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.162.08:10:02.39#ibcon#ireg 11 cls_cnt 2 2006.162.08:10:02.39#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.162.08:10:02.46#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.162.08:10:02.46#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.162.08:10:02.46#ibcon#enter wrdev, iclass 37, count 2 2006.162.08:10:02.46#ibcon#first serial, iclass 37, count 2 2006.162.08:10:02.46#ibcon#enter sib2, iclass 37, count 2 2006.162.08:10:02.46#ibcon#flushed, iclass 37, count 2 2006.162.08:10:02.46#ibcon#about to write, iclass 37, count 2 2006.162.08:10:02.46#ibcon#wrote, iclass 37, count 2 2006.162.08:10:02.46#ibcon#about to read 3, iclass 37, count 2 2006.162.08:10:02.47#ibcon#read 3, iclass 37, count 2 2006.162.08:10:02.47#ibcon#about to read 4, iclass 37, count 2 2006.162.08:10:02.47#ibcon#read 4, iclass 37, count 2 2006.162.08:10:02.47#ibcon#about to read 5, iclass 37, count 2 2006.162.08:10:02.47#ibcon#read 5, iclass 37, count 2 2006.162.08:10:02.47#ibcon#about to read 6, iclass 37, count 2 2006.162.08:10:02.47#ibcon#read 6, iclass 37, count 2 2006.162.08:10:02.47#ibcon#end of sib2, iclass 37, count 2 2006.162.08:10:02.47#ibcon#*mode == 0, iclass 37, count 2 2006.162.08:10:02.47#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.162.08:10:02.47#ibcon#[25=AT02-07\r\n] 2006.162.08:10:02.47#ibcon#*before write, iclass 37, count 2 2006.162.08:10:02.47#ibcon#enter sib2, iclass 37, count 2 2006.162.08:10:02.47#ibcon#flushed, iclass 37, count 2 2006.162.08:10:02.47#ibcon#about to write, iclass 37, count 2 2006.162.08:10:02.47#ibcon#wrote, iclass 37, count 2 2006.162.08:10:02.47#ibcon#about to read 3, iclass 37, count 2 2006.162.08:10:02.50#ibcon#read 3, iclass 37, count 2 2006.162.08:10:02.50#ibcon#about to read 4, iclass 37, count 2 2006.162.08:10:02.50#ibcon#read 4, iclass 37, count 2 2006.162.08:10:02.50#ibcon#about to read 5, iclass 37, count 2 2006.162.08:10:02.50#ibcon#read 5, iclass 37, count 2 2006.162.08:10:02.50#ibcon#about to read 6, iclass 37, count 2 2006.162.08:10:02.50#ibcon#read 6, iclass 37, count 2 2006.162.08:10:02.50#ibcon#end of sib2, iclass 37, count 2 2006.162.08:10:02.50#ibcon#*after write, iclass 37, count 2 2006.162.08:10:02.50#ibcon#*before return 0, iclass 37, count 2 2006.162.08:10:02.50#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.162.08:10:02.50#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.162.08:10:02.50#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.162.08:10:02.50#ibcon#ireg 7 cls_cnt 0 2006.162.08:10:02.50#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.162.08:10:02.62#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.162.08:10:02.62#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.162.08:10:02.62#ibcon#enter wrdev, iclass 37, count 0 2006.162.08:10:02.62#ibcon#first serial, iclass 37, count 0 2006.162.08:10:02.62#ibcon#enter sib2, iclass 37, count 0 2006.162.08:10:02.62#ibcon#flushed, iclass 37, count 0 2006.162.08:10:02.62#ibcon#about to write, iclass 37, count 0 2006.162.08:10:02.62#ibcon#wrote, iclass 37, count 0 2006.162.08:10:02.62#ibcon#about to read 3, iclass 37, count 0 2006.162.08:10:02.64#ibcon#read 3, iclass 37, count 0 2006.162.08:10:02.64#ibcon#about to read 4, iclass 37, count 0 2006.162.08:10:02.64#ibcon#read 4, iclass 37, count 0 2006.162.08:10:02.64#ibcon#about to read 5, iclass 37, count 0 2006.162.08:10:02.64#ibcon#read 5, iclass 37, count 0 2006.162.08:10:02.64#ibcon#about to read 6, iclass 37, count 0 2006.162.08:10:02.64#ibcon#read 6, iclass 37, count 0 2006.162.08:10:02.64#ibcon#end of sib2, iclass 37, count 0 2006.162.08:10:02.64#ibcon#*mode == 0, iclass 37, count 0 2006.162.08:10:02.64#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.162.08:10:02.64#ibcon#[25=USB\r\n] 2006.162.08:10:02.64#ibcon#*before write, iclass 37, count 0 2006.162.08:10:02.64#ibcon#enter sib2, iclass 37, count 0 2006.162.08:10:02.64#ibcon#flushed, iclass 37, count 0 2006.162.08:10:02.64#ibcon#about to write, iclass 37, count 0 2006.162.08:10:02.64#ibcon#wrote, iclass 37, count 0 2006.162.08:10:02.64#ibcon#about to read 3, iclass 37, count 0 2006.162.08:10:02.67#ibcon#read 3, iclass 37, count 0 2006.162.08:10:02.67#ibcon#about to read 4, iclass 37, count 0 2006.162.08:10:02.67#ibcon#read 4, iclass 37, count 0 2006.162.08:10:02.67#ibcon#about to read 5, iclass 37, count 0 2006.162.08:10:02.67#ibcon#read 5, iclass 37, count 0 2006.162.08:10:02.67#ibcon#about to read 6, iclass 37, count 0 2006.162.08:10:02.67#ibcon#read 6, iclass 37, count 0 2006.162.08:10:02.67#ibcon#end of sib2, iclass 37, count 0 2006.162.08:10:02.67#ibcon#*after write, iclass 37, count 0 2006.162.08:10:02.67#ibcon#*before return 0, iclass 37, count 0 2006.162.08:10:02.67#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.162.08:10:02.67#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.162.08:10:02.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.162.08:10:02.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.162.08:10:02.67$vc4f8/valo=3,672.99 2006.162.08:10:02.67#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.162.08:10:02.67#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.162.08:10:02.67#ibcon#ireg 17 cls_cnt 0 2006.162.08:10:02.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:10:02.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:10:02.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:10:02.67#ibcon#enter wrdev, iclass 39, count 0 2006.162.08:10:02.67#ibcon#first serial, iclass 39, count 0 2006.162.08:10:02.67#ibcon#enter sib2, iclass 39, count 0 2006.162.08:10:02.67#ibcon#flushed, iclass 39, count 0 2006.162.08:10:02.67#ibcon#about to write, iclass 39, count 0 2006.162.08:10:02.67#ibcon#wrote, iclass 39, count 0 2006.162.08:10:02.67#ibcon#about to read 3, iclass 39, count 0 2006.162.08:10:02.69#ibcon#read 3, iclass 39, count 0 2006.162.08:10:02.69#ibcon#about to read 4, iclass 39, count 0 2006.162.08:10:02.69#ibcon#read 4, iclass 39, count 0 2006.162.08:10:02.69#ibcon#about to read 5, iclass 39, count 0 2006.162.08:10:02.69#ibcon#read 5, iclass 39, count 0 2006.162.08:10:02.69#ibcon#about to read 6, iclass 39, count 0 2006.162.08:10:02.69#ibcon#read 6, iclass 39, count 0 2006.162.08:10:02.69#ibcon#end of sib2, iclass 39, count 0 2006.162.08:10:02.69#ibcon#*mode == 0, iclass 39, count 0 2006.162.08:10:02.69#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.162.08:10:02.69#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.08:10:02.69#ibcon#*before write, iclass 39, count 0 2006.162.08:10:02.69#ibcon#enter sib2, iclass 39, count 0 2006.162.08:10:02.69#ibcon#flushed, iclass 39, count 0 2006.162.08:10:02.69#ibcon#about to write, iclass 39, count 0 2006.162.08:10:02.69#ibcon#wrote, iclass 39, count 0 2006.162.08:10:02.69#ibcon#about to read 3, iclass 39, count 0 2006.162.08:10:02.73#ibcon#read 3, iclass 39, count 0 2006.162.08:10:02.73#ibcon#about to read 4, iclass 39, count 0 2006.162.08:10:02.73#ibcon#read 4, iclass 39, count 0 2006.162.08:10:02.73#ibcon#about to read 5, iclass 39, count 0 2006.162.08:10:02.73#ibcon#read 5, iclass 39, count 0 2006.162.08:10:02.73#ibcon#about to read 6, iclass 39, count 0 2006.162.08:10:02.73#ibcon#read 6, iclass 39, count 0 2006.162.08:10:02.73#ibcon#end of sib2, iclass 39, count 0 2006.162.08:10:02.73#ibcon#*after write, iclass 39, count 0 2006.162.08:10:02.73#ibcon#*before return 0, iclass 39, count 0 2006.162.08:10:02.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:10:02.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:10:02.73#ibcon#about to clear, iclass 39 cls_cnt 0 2006.162.08:10:02.73#ibcon#cleared, iclass 39 cls_cnt 0 2006.162.08:10:02.73$vc4f8/va=3,6 2006.162.08:10:02.73#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.162.08:10:02.73#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.162.08:10:02.73#ibcon#ireg 11 cls_cnt 2 2006.162.08:10:02.73#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:10:02.80#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:10:02.80#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:10:02.80#ibcon#enter wrdev, iclass 3, count 2 2006.162.08:10:02.80#ibcon#first serial, iclass 3, count 2 2006.162.08:10:02.80#ibcon#enter sib2, iclass 3, count 2 2006.162.08:10:02.80#ibcon#flushed, iclass 3, count 2 2006.162.08:10:02.80#ibcon#about to write, iclass 3, count 2 2006.162.08:10:02.80#ibcon#wrote, iclass 3, count 2 2006.162.08:10:02.80#ibcon#about to read 3, iclass 3, count 2 2006.162.08:10:02.81#ibcon#read 3, iclass 3, count 2 2006.162.08:10:02.81#ibcon#about to read 4, iclass 3, count 2 2006.162.08:10:02.81#ibcon#read 4, iclass 3, count 2 2006.162.08:10:02.81#ibcon#about to read 5, iclass 3, count 2 2006.162.08:10:02.81#ibcon#read 5, iclass 3, count 2 2006.162.08:10:02.81#ibcon#about to read 6, iclass 3, count 2 2006.162.08:10:02.81#ibcon#read 6, iclass 3, count 2 2006.162.08:10:02.81#ibcon#end of sib2, iclass 3, count 2 2006.162.08:10:02.81#ibcon#*mode == 0, iclass 3, count 2 2006.162.08:10:02.81#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.162.08:10:02.81#ibcon#[25=AT03-06\r\n] 2006.162.08:10:02.81#ibcon#*before write, iclass 3, count 2 2006.162.08:10:02.81#ibcon#enter sib2, iclass 3, count 2 2006.162.08:10:02.81#ibcon#flushed, iclass 3, count 2 2006.162.08:10:02.81#ibcon#about to write, iclass 3, count 2 2006.162.08:10:02.81#ibcon#wrote, iclass 3, count 2 2006.162.08:10:02.81#ibcon#about to read 3, iclass 3, count 2 2006.162.08:10:02.84#ibcon#read 3, iclass 3, count 2 2006.162.08:10:02.84#ibcon#about to read 4, iclass 3, count 2 2006.162.08:10:02.84#ibcon#read 4, iclass 3, count 2 2006.162.08:10:02.84#ibcon#about to read 5, iclass 3, count 2 2006.162.08:10:02.84#ibcon#read 5, iclass 3, count 2 2006.162.08:10:02.84#ibcon#about to read 6, iclass 3, count 2 2006.162.08:10:02.84#ibcon#read 6, iclass 3, count 2 2006.162.08:10:02.84#ibcon#end of sib2, iclass 3, count 2 2006.162.08:10:02.84#ibcon#*after write, iclass 3, count 2 2006.162.08:10:02.84#ibcon#*before return 0, iclass 3, count 2 2006.162.08:10:02.84#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:10:02.84#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:10:02.84#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.162.08:10:02.84#ibcon#ireg 7 cls_cnt 0 2006.162.08:10:02.84#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:10:02.96#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:10:02.96#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:10:02.96#ibcon#enter wrdev, iclass 3, count 0 2006.162.08:10:02.96#ibcon#first serial, iclass 3, count 0 2006.162.08:10:02.96#ibcon#enter sib2, iclass 3, count 0 2006.162.08:10:02.96#ibcon#flushed, iclass 3, count 0 2006.162.08:10:02.96#ibcon#about to write, iclass 3, count 0 2006.162.08:10:02.96#ibcon#wrote, iclass 3, count 0 2006.162.08:10:02.96#ibcon#about to read 3, iclass 3, count 0 2006.162.08:10:02.98#ibcon#read 3, iclass 3, count 0 2006.162.08:10:02.98#ibcon#about to read 4, iclass 3, count 0 2006.162.08:10:02.98#ibcon#read 4, iclass 3, count 0 2006.162.08:10:02.98#ibcon#about to read 5, iclass 3, count 0 2006.162.08:10:02.98#ibcon#read 5, iclass 3, count 0 2006.162.08:10:02.98#ibcon#about to read 6, iclass 3, count 0 2006.162.08:10:02.98#ibcon#read 6, iclass 3, count 0 2006.162.08:10:02.98#ibcon#end of sib2, iclass 3, count 0 2006.162.08:10:02.98#ibcon#*mode == 0, iclass 3, count 0 2006.162.08:10:02.98#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.162.08:10:02.98#ibcon#[25=USB\r\n] 2006.162.08:10:02.98#ibcon#*before write, iclass 3, count 0 2006.162.08:10:02.98#ibcon#enter sib2, iclass 3, count 0 2006.162.08:10:02.98#ibcon#flushed, iclass 3, count 0 2006.162.08:10:02.98#ibcon#about to write, iclass 3, count 0 2006.162.08:10:02.98#ibcon#wrote, iclass 3, count 0 2006.162.08:10:02.98#ibcon#about to read 3, iclass 3, count 0 2006.162.08:10:03.01#ibcon#read 3, iclass 3, count 0 2006.162.08:10:03.01#ibcon#about to read 4, iclass 3, count 0 2006.162.08:10:03.01#ibcon#read 4, iclass 3, count 0 2006.162.08:10:03.01#ibcon#about to read 5, iclass 3, count 0 2006.162.08:10:03.01#ibcon#read 5, iclass 3, count 0 2006.162.08:10:03.01#ibcon#about to read 6, iclass 3, count 0 2006.162.08:10:03.01#ibcon#read 6, iclass 3, count 0 2006.162.08:10:03.01#ibcon#end of sib2, iclass 3, count 0 2006.162.08:10:03.01#ibcon#*after write, iclass 3, count 0 2006.162.08:10:03.01#ibcon#*before return 0, iclass 3, count 0 2006.162.08:10:03.01#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:10:03.01#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:10:03.01#ibcon#about to clear, iclass 3 cls_cnt 0 2006.162.08:10:03.01#ibcon#cleared, iclass 3 cls_cnt 0 2006.162.08:10:03.01$vc4f8/valo=4,832.99 2006.162.08:10:03.01#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.162.08:10:03.01#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.162.08:10:03.01#ibcon#ireg 17 cls_cnt 0 2006.162.08:10:03.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:10:03.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:10:03.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:10:03.01#ibcon#enter wrdev, iclass 5, count 0 2006.162.08:10:03.01#ibcon#first serial, iclass 5, count 0 2006.162.08:10:03.01#ibcon#enter sib2, iclass 5, count 0 2006.162.08:10:03.01#ibcon#flushed, iclass 5, count 0 2006.162.08:10:03.01#ibcon#about to write, iclass 5, count 0 2006.162.08:10:03.01#ibcon#wrote, iclass 5, count 0 2006.162.08:10:03.01#ibcon#about to read 3, iclass 5, count 0 2006.162.08:10:03.03#ibcon#read 3, iclass 5, count 0 2006.162.08:10:03.03#ibcon#about to read 4, iclass 5, count 0 2006.162.08:10:03.03#ibcon#read 4, iclass 5, count 0 2006.162.08:10:03.03#ibcon#about to read 5, iclass 5, count 0 2006.162.08:10:03.03#ibcon#read 5, iclass 5, count 0 2006.162.08:10:03.03#ibcon#about to read 6, iclass 5, count 0 2006.162.08:10:03.03#ibcon#read 6, iclass 5, count 0 2006.162.08:10:03.03#ibcon#end of sib2, iclass 5, count 0 2006.162.08:10:03.03#ibcon#*mode == 0, iclass 5, count 0 2006.162.08:10:03.03#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.162.08:10:03.03#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.08:10:03.03#ibcon#*before write, iclass 5, count 0 2006.162.08:10:03.03#ibcon#enter sib2, iclass 5, count 0 2006.162.08:10:03.03#ibcon#flushed, iclass 5, count 0 2006.162.08:10:03.03#ibcon#about to write, iclass 5, count 0 2006.162.08:10:03.03#ibcon#wrote, iclass 5, count 0 2006.162.08:10:03.03#ibcon#about to read 3, iclass 5, count 0 2006.162.08:10:03.07#ibcon#read 3, iclass 5, count 0 2006.162.08:10:03.07#ibcon#about to read 4, iclass 5, count 0 2006.162.08:10:03.07#ibcon#read 4, iclass 5, count 0 2006.162.08:10:03.07#ibcon#about to read 5, iclass 5, count 0 2006.162.08:10:03.07#ibcon#read 5, iclass 5, count 0 2006.162.08:10:03.07#ibcon#about to read 6, iclass 5, count 0 2006.162.08:10:03.07#ibcon#read 6, iclass 5, count 0 2006.162.08:10:03.07#ibcon#end of sib2, iclass 5, count 0 2006.162.08:10:03.07#ibcon#*after write, iclass 5, count 0 2006.162.08:10:03.07#ibcon#*before return 0, iclass 5, count 0 2006.162.08:10:03.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:10:03.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:10:03.07#ibcon#about to clear, iclass 5 cls_cnt 0 2006.162.08:10:03.07#ibcon#cleared, iclass 5 cls_cnt 0 2006.162.08:10:03.07$vc4f8/va=4,7 2006.162.08:10:03.07#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.162.08:10:03.07#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.162.08:10:03.07#ibcon#ireg 11 cls_cnt 2 2006.162.08:10:03.07#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:10:03.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:10:03.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:10:03.13#ibcon#enter wrdev, iclass 7, count 2 2006.162.08:10:03.13#ibcon#first serial, iclass 7, count 2 2006.162.08:10:03.13#ibcon#enter sib2, iclass 7, count 2 2006.162.08:10:03.13#ibcon#flushed, iclass 7, count 2 2006.162.08:10:03.13#ibcon#about to write, iclass 7, count 2 2006.162.08:10:03.13#ibcon#wrote, iclass 7, count 2 2006.162.08:10:03.13#ibcon#about to read 3, iclass 7, count 2 2006.162.08:10:03.15#ibcon#read 3, iclass 7, count 2 2006.162.08:10:03.15#ibcon#about to read 4, iclass 7, count 2 2006.162.08:10:03.15#ibcon#read 4, iclass 7, count 2 2006.162.08:10:03.15#ibcon#about to read 5, iclass 7, count 2 2006.162.08:10:03.15#ibcon#read 5, iclass 7, count 2 2006.162.08:10:03.15#ibcon#about to read 6, iclass 7, count 2 2006.162.08:10:03.15#ibcon#read 6, iclass 7, count 2 2006.162.08:10:03.15#ibcon#end of sib2, iclass 7, count 2 2006.162.08:10:03.15#ibcon#*mode == 0, iclass 7, count 2 2006.162.08:10:03.15#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.162.08:10:03.15#ibcon#[25=AT04-07\r\n] 2006.162.08:10:03.15#ibcon#*before write, iclass 7, count 2 2006.162.08:10:03.15#ibcon#enter sib2, iclass 7, count 2 2006.162.08:10:03.15#ibcon#flushed, iclass 7, count 2 2006.162.08:10:03.15#ibcon#about to write, iclass 7, count 2 2006.162.08:10:03.15#ibcon#wrote, iclass 7, count 2 2006.162.08:10:03.15#ibcon#about to read 3, iclass 7, count 2 2006.162.08:10:03.18#ibcon#read 3, iclass 7, count 2 2006.162.08:10:03.18#ibcon#about to read 4, iclass 7, count 2 2006.162.08:10:03.18#ibcon#read 4, iclass 7, count 2 2006.162.08:10:03.18#ibcon#about to read 5, iclass 7, count 2 2006.162.08:10:03.18#ibcon#read 5, iclass 7, count 2 2006.162.08:10:03.18#ibcon#about to read 6, iclass 7, count 2 2006.162.08:10:03.18#ibcon#read 6, iclass 7, count 2 2006.162.08:10:03.18#ibcon#end of sib2, iclass 7, count 2 2006.162.08:10:03.18#ibcon#*after write, iclass 7, count 2 2006.162.08:10:03.18#ibcon#*before return 0, iclass 7, count 2 2006.162.08:10:03.18#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:10:03.18#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:10:03.18#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.162.08:10:03.18#ibcon#ireg 7 cls_cnt 0 2006.162.08:10:03.18#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:10:03.30#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:10:03.30#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:10:03.30#ibcon#enter wrdev, iclass 7, count 0 2006.162.08:10:03.30#ibcon#first serial, iclass 7, count 0 2006.162.08:10:03.30#ibcon#enter sib2, iclass 7, count 0 2006.162.08:10:03.30#ibcon#flushed, iclass 7, count 0 2006.162.08:10:03.30#ibcon#about to write, iclass 7, count 0 2006.162.08:10:03.30#ibcon#wrote, iclass 7, count 0 2006.162.08:10:03.30#ibcon#about to read 3, iclass 7, count 0 2006.162.08:10:03.32#ibcon#read 3, iclass 7, count 0 2006.162.08:10:03.32#ibcon#about to read 4, iclass 7, count 0 2006.162.08:10:03.32#ibcon#read 4, iclass 7, count 0 2006.162.08:10:03.32#ibcon#about to read 5, iclass 7, count 0 2006.162.08:10:03.32#ibcon#read 5, iclass 7, count 0 2006.162.08:10:03.32#ibcon#about to read 6, iclass 7, count 0 2006.162.08:10:03.32#ibcon#read 6, iclass 7, count 0 2006.162.08:10:03.32#ibcon#end of sib2, iclass 7, count 0 2006.162.08:10:03.32#ibcon#*mode == 0, iclass 7, count 0 2006.162.08:10:03.32#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.162.08:10:03.32#ibcon#[25=USB\r\n] 2006.162.08:10:03.32#ibcon#*before write, iclass 7, count 0 2006.162.08:10:03.32#ibcon#enter sib2, iclass 7, count 0 2006.162.08:10:03.32#ibcon#flushed, iclass 7, count 0 2006.162.08:10:03.32#ibcon#about to write, iclass 7, count 0 2006.162.08:10:03.32#ibcon#wrote, iclass 7, count 0 2006.162.08:10:03.32#ibcon#about to read 3, iclass 7, count 0 2006.162.08:10:03.35#ibcon#read 3, iclass 7, count 0 2006.162.08:10:03.35#ibcon#about to read 4, iclass 7, count 0 2006.162.08:10:03.35#ibcon#read 4, iclass 7, count 0 2006.162.08:10:03.35#ibcon#about to read 5, iclass 7, count 0 2006.162.08:10:03.35#ibcon#read 5, iclass 7, count 0 2006.162.08:10:03.35#ibcon#about to read 6, iclass 7, count 0 2006.162.08:10:03.35#ibcon#read 6, iclass 7, count 0 2006.162.08:10:03.35#ibcon#end of sib2, iclass 7, count 0 2006.162.08:10:03.35#ibcon#*after write, iclass 7, count 0 2006.162.08:10:03.35#ibcon#*before return 0, iclass 7, count 0 2006.162.08:10:03.35#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:10:03.35#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:10:03.35#ibcon#about to clear, iclass 7 cls_cnt 0 2006.162.08:10:03.35#ibcon#cleared, iclass 7 cls_cnt 0 2006.162.08:10:03.35$vc4f8/valo=5,652.99 2006.162.08:10:03.35#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.162.08:10:03.35#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.162.08:10:03.35#ibcon#ireg 17 cls_cnt 0 2006.162.08:10:03.35#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:10:03.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:10:03.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:10:03.35#ibcon#enter wrdev, iclass 11, count 0 2006.162.08:10:03.35#ibcon#first serial, iclass 11, count 0 2006.162.08:10:03.35#ibcon#enter sib2, iclass 11, count 0 2006.162.08:10:03.35#ibcon#flushed, iclass 11, count 0 2006.162.08:10:03.35#ibcon#about to write, iclass 11, count 0 2006.162.08:10:03.35#ibcon#wrote, iclass 11, count 0 2006.162.08:10:03.35#ibcon#about to read 3, iclass 11, count 0 2006.162.08:10:03.37#ibcon#read 3, iclass 11, count 0 2006.162.08:10:03.37#ibcon#about to read 4, iclass 11, count 0 2006.162.08:10:03.37#ibcon#read 4, iclass 11, count 0 2006.162.08:10:03.37#ibcon#about to read 5, iclass 11, count 0 2006.162.08:10:03.37#ibcon#read 5, iclass 11, count 0 2006.162.08:10:03.37#ibcon#about to read 6, iclass 11, count 0 2006.162.08:10:03.37#ibcon#read 6, iclass 11, count 0 2006.162.08:10:03.37#ibcon#end of sib2, iclass 11, count 0 2006.162.08:10:03.37#ibcon#*mode == 0, iclass 11, count 0 2006.162.08:10:03.37#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.162.08:10:03.37#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.08:10:03.37#ibcon#*before write, iclass 11, count 0 2006.162.08:10:03.37#ibcon#enter sib2, iclass 11, count 0 2006.162.08:10:03.37#ibcon#flushed, iclass 11, count 0 2006.162.08:10:03.37#ibcon#about to write, iclass 11, count 0 2006.162.08:10:03.37#ibcon#wrote, iclass 11, count 0 2006.162.08:10:03.37#ibcon#about to read 3, iclass 11, count 0 2006.162.08:10:03.41#ibcon#read 3, iclass 11, count 0 2006.162.08:10:03.41#ibcon#about to read 4, iclass 11, count 0 2006.162.08:10:03.41#ibcon#read 4, iclass 11, count 0 2006.162.08:10:03.41#ibcon#about to read 5, iclass 11, count 0 2006.162.08:10:03.41#ibcon#read 5, iclass 11, count 0 2006.162.08:10:03.41#ibcon#about to read 6, iclass 11, count 0 2006.162.08:10:03.41#ibcon#read 6, iclass 11, count 0 2006.162.08:10:03.41#ibcon#end of sib2, iclass 11, count 0 2006.162.08:10:03.41#ibcon#*after write, iclass 11, count 0 2006.162.08:10:03.41#ibcon#*before return 0, iclass 11, count 0 2006.162.08:10:03.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:10:03.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:10:03.41#ibcon#about to clear, iclass 11 cls_cnt 0 2006.162.08:10:03.41#ibcon#cleared, iclass 11 cls_cnt 0 2006.162.08:10:03.41$vc4f8/va=5,7 2006.162.08:10:03.41#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.162.08:10:03.41#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.162.08:10:03.41#ibcon#ireg 11 cls_cnt 2 2006.162.08:10:03.41#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:10:03.48#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:10:03.48#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:10:03.48#ibcon#enter wrdev, iclass 13, count 2 2006.162.08:10:03.48#ibcon#first serial, iclass 13, count 2 2006.162.08:10:03.48#ibcon#enter sib2, iclass 13, count 2 2006.162.08:10:03.48#ibcon#flushed, iclass 13, count 2 2006.162.08:10:03.48#ibcon#about to write, iclass 13, count 2 2006.162.08:10:03.48#ibcon#wrote, iclass 13, count 2 2006.162.08:10:03.48#ibcon#about to read 3, iclass 13, count 2 2006.162.08:10:03.49#ibcon#read 3, iclass 13, count 2 2006.162.08:10:03.49#ibcon#about to read 4, iclass 13, count 2 2006.162.08:10:03.49#ibcon#read 4, iclass 13, count 2 2006.162.08:10:03.49#ibcon#about to read 5, iclass 13, count 2 2006.162.08:10:03.49#ibcon#read 5, iclass 13, count 2 2006.162.08:10:03.49#ibcon#about to read 6, iclass 13, count 2 2006.162.08:10:03.49#ibcon#read 6, iclass 13, count 2 2006.162.08:10:03.49#ibcon#end of sib2, iclass 13, count 2 2006.162.08:10:03.49#ibcon#*mode == 0, iclass 13, count 2 2006.162.08:10:03.49#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.162.08:10:03.49#ibcon#[25=AT05-07\r\n] 2006.162.08:10:03.49#ibcon#*before write, iclass 13, count 2 2006.162.08:10:03.49#ibcon#enter sib2, iclass 13, count 2 2006.162.08:10:03.49#ibcon#flushed, iclass 13, count 2 2006.162.08:10:03.49#ibcon#about to write, iclass 13, count 2 2006.162.08:10:03.49#ibcon#wrote, iclass 13, count 2 2006.162.08:10:03.49#ibcon#about to read 3, iclass 13, count 2 2006.162.08:10:03.52#ibcon#read 3, iclass 13, count 2 2006.162.08:10:03.52#ibcon#about to read 4, iclass 13, count 2 2006.162.08:10:03.52#ibcon#read 4, iclass 13, count 2 2006.162.08:10:03.52#ibcon#about to read 5, iclass 13, count 2 2006.162.08:10:03.52#ibcon#read 5, iclass 13, count 2 2006.162.08:10:03.52#ibcon#about to read 6, iclass 13, count 2 2006.162.08:10:03.52#ibcon#read 6, iclass 13, count 2 2006.162.08:10:03.52#ibcon#end of sib2, iclass 13, count 2 2006.162.08:10:03.52#ibcon#*after write, iclass 13, count 2 2006.162.08:10:03.52#ibcon#*before return 0, iclass 13, count 2 2006.162.08:10:03.52#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:10:03.52#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:10:03.52#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.162.08:10:03.52#ibcon#ireg 7 cls_cnt 0 2006.162.08:10:03.52#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:10:03.64#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:10:03.64#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:10:03.64#ibcon#enter wrdev, iclass 13, count 0 2006.162.08:10:03.64#ibcon#first serial, iclass 13, count 0 2006.162.08:10:03.64#ibcon#enter sib2, iclass 13, count 0 2006.162.08:10:03.64#ibcon#flushed, iclass 13, count 0 2006.162.08:10:03.64#ibcon#about to write, iclass 13, count 0 2006.162.08:10:03.64#ibcon#wrote, iclass 13, count 0 2006.162.08:10:03.64#ibcon#about to read 3, iclass 13, count 0 2006.162.08:10:03.66#ibcon#read 3, iclass 13, count 0 2006.162.08:10:03.66#ibcon#about to read 4, iclass 13, count 0 2006.162.08:10:03.66#ibcon#read 4, iclass 13, count 0 2006.162.08:10:03.66#ibcon#about to read 5, iclass 13, count 0 2006.162.08:10:03.66#ibcon#read 5, iclass 13, count 0 2006.162.08:10:03.66#ibcon#about to read 6, iclass 13, count 0 2006.162.08:10:03.66#ibcon#read 6, iclass 13, count 0 2006.162.08:10:03.66#ibcon#end of sib2, iclass 13, count 0 2006.162.08:10:03.66#ibcon#*mode == 0, iclass 13, count 0 2006.162.08:10:03.66#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.162.08:10:03.66#ibcon#[25=USB\r\n] 2006.162.08:10:03.66#ibcon#*before write, iclass 13, count 0 2006.162.08:10:03.66#ibcon#enter sib2, iclass 13, count 0 2006.162.08:10:03.66#ibcon#flushed, iclass 13, count 0 2006.162.08:10:03.66#ibcon#about to write, iclass 13, count 0 2006.162.08:10:03.66#ibcon#wrote, iclass 13, count 0 2006.162.08:10:03.66#ibcon#about to read 3, iclass 13, count 0 2006.162.08:10:03.69#ibcon#read 3, iclass 13, count 0 2006.162.08:10:03.69#ibcon#about to read 4, iclass 13, count 0 2006.162.08:10:03.69#ibcon#read 4, iclass 13, count 0 2006.162.08:10:03.69#ibcon#about to read 5, iclass 13, count 0 2006.162.08:10:03.69#ibcon#read 5, iclass 13, count 0 2006.162.08:10:03.69#ibcon#about to read 6, iclass 13, count 0 2006.162.08:10:03.69#ibcon#read 6, iclass 13, count 0 2006.162.08:10:03.69#ibcon#end of sib2, iclass 13, count 0 2006.162.08:10:03.69#ibcon#*after write, iclass 13, count 0 2006.162.08:10:03.69#ibcon#*before return 0, iclass 13, count 0 2006.162.08:10:03.69#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:10:03.69#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:10:03.69#ibcon#about to clear, iclass 13 cls_cnt 0 2006.162.08:10:03.69#ibcon#cleared, iclass 13 cls_cnt 0 2006.162.08:10:03.69$vc4f8/valo=6,772.99 2006.162.08:10:03.69#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.162.08:10:03.69#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.162.08:10:03.69#ibcon#ireg 17 cls_cnt 0 2006.162.08:10:03.69#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:10:03.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:10:03.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:10:03.69#ibcon#enter wrdev, iclass 15, count 0 2006.162.08:10:03.69#ibcon#first serial, iclass 15, count 0 2006.162.08:10:03.69#ibcon#enter sib2, iclass 15, count 0 2006.162.08:10:03.69#ibcon#flushed, iclass 15, count 0 2006.162.08:10:03.69#ibcon#about to write, iclass 15, count 0 2006.162.08:10:03.69#ibcon#wrote, iclass 15, count 0 2006.162.08:10:03.69#ibcon#about to read 3, iclass 15, count 0 2006.162.08:10:03.71#ibcon#read 3, iclass 15, count 0 2006.162.08:10:03.71#ibcon#about to read 4, iclass 15, count 0 2006.162.08:10:03.71#ibcon#read 4, iclass 15, count 0 2006.162.08:10:03.71#ibcon#about to read 5, iclass 15, count 0 2006.162.08:10:03.71#ibcon#read 5, iclass 15, count 0 2006.162.08:10:03.71#ibcon#about to read 6, iclass 15, count 0 2006.162.08:10:03.71#ibcon#read 6, iclass 15, count 0 2006.162.08:10:03.71#ibcon#end of sib2, iclass 15, count 0 2006.162.08:10:03.71#ibcon#*mode == 0, iclass 15, count 0 2006.162.08:10:03.71#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.162.08:10:03.71#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.08:10:03.71#ibcon#*before write, iclass 15, count 0 2006.162.08:10:03.71#ibcon#enter sib2, iclass 15, count 0 2006.162.08:10:03.71#ibcon#flushed, iclass 15, count 0 2006.162.08:10:03.71#ibcon#about to write, iclass 15, count 0 2006.162.08:10:03.71#ibcon#wrote, iclass 15, count 0 2006.162.08:10:03.71#ibcon#about to read 3, iclass 15, count 0 2006.162.08:10:03.75#ibcon#read 3, iclass 15, count 0 2006.162.08:10:03.75#ibcon#about to read 4, iclass 15, count 0 2006.162.08:10:03.75#ibcon#read 4, iclass 15, count 0 2006.162.08:10:03.75#ibcon#about to read 5, iclass 15, count 0 2006.162.08:10:03.75#ibcon#read 5, iclass 15, count 0 2006.162.08:10:03.75#ibcon#about to read 6, iclass 15, count 0 2006.162.08:10:03.75#ibcon#read 6, iclass 15, count 0 2006.162.08:10:03.75#ibcon#end of sib2, iclass 15, count 0 2006.162.08:10:03.75#ibcon#*after write, iclass 15, count 0 2006.162.08:10:03.75#ibcon#*before return 0, iclass 15, count 0 2006.162.08:10:03.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:10:03.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:10:03.75#ibcon#about to clear, iclass 15 cls_cnt 0 2006.162.08:10:03.75#ibcon#cleared, iclass 15 cls_cnt 0 2006.162.08:10:03.75$vc4f8/va=6,6 2006.162.08:10:03.75#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.162.08:10:03.75#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.162.08:10:03.75#ibcon#ireg 11 cls_cnt 2 2006.162.08:10:03.75#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:10:03.82#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:10:03.82#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:10:03.82#ibcon#enter wrdev, iclass 17, count 2 2006.162.08:10:03.82#ibcon#first serial, iclass 17, count 2 2006.162.08:10:03.82#ibcon#enter sib2, iclass 17, count 2 2006.162.08:10:03.82#ibcon#flushed, iclass 17, count 2 2006.162.08:10:03.82#ibcon#about to write, iclass 17, count 2 2006.162.08:10:03.82#ibcon#wrote, iclass 17, count 2 2006.162.08:10:03.82#ibcon#about to read 3, iclass 17, count 2 2006.162.08:10:03.83#ibcon#read 3, iclass 17, count 2 2006.162.08:10:03.83#ibcon#about to read 4, iclass 17, count 2 2006.162.08:10:03.83#ibcon#read 4, iclass 17, count 2 2006.162.08:10:03.83#ibcon#about to read 5, iclass 17, count 2 2006.162.08:10:03.83#ibcon#read 5, iclass 17, count 2 2006.162.08:10:03.83#ibcon#about to read 6, iclass 17, count 2 2006.162.08:10:03.83#ibcon#read 6, iclass 17, count 2 2006.162.08:10:03.83#ibcon#end of sib2, iclass 17, count 2 2006.162.08:10:03.83#ibcon#*mode == 0, iclass 17, count 2 2006.162.08:10:03.83#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.162.08:10:03.83#ibcon#[25=AT06-06\r\n] 2006.162.08:10:03.83#ibcon#*before write, iclass 17, count 2 2006.162.08:10:03.83#ibcon#enter sib2, iclass 17, count 2 2006.162.08:10:03.83#ibcon#flushed, iclass 17, count 2 2006.162.08:10:03.83#ibcon#about to write, iclass 17, count 2 2006.162.08:10:03.83#ibcon#wrote, iclass 17, count 2 2006.162.08:10:03.83#ibcon#about to read 3, iclass 17, count 2 2006.162.08:10:03.86#ibcon#read 3, iclass 17, count 2 2006.162.08:10:03.86#ibcon#about to read 4, iclass 17, count 2 2006.162.08:10:03.86#ibcon#read 4, iclass 17, count 2 2006.162.08:10:03.86#ibcon#about to read 5, iclass 17, count 2 2006.162.08:10:03.86#ibcon#read 5, iclass 17, count 2 2006.162.08:10:03.86#ibcon#about to read 6, iclass 17, count 2 2006.162.08:10:03.86#ibcon#read 6, iclass 17, count 2 2006.162.08:10:03.86#ibcon#end of sib2, iclass 17, count 2 2006.162.08:10:03.86#ibcon#*after write, iclass 17, count 2 2006.162.08:10:03.86#ibcon#*before return 0, iclass 17, count 2 2006.162.08:10:03.86#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:10:03.86#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:10:03.86#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.162.08:10:03.86#ibcon#ireg 7 cls_cnt 0 2006.162.08:10:03.86#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:10:03.98#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:10:03.98#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:10:03.98#ibcon#enter wrdev, iclass 17, count 0 2006.162.08:10:03.98#ibcon#first serial, iclass 17, count 0 2006.162.08:10:03.98#ibcon#enter sib2, iclass 17, count 0 2006.162.08:10:03.98#ibcon#flushed, iclass 17, count 0 2006.162.08:10:03.98#ibcon#about to write, iclass 17, count 0 2006.162.08:10:03.98#ibcon#wrote, iclass 17, count 0 2006.162.08:10:03.98#ibcon#about to read 3, iclass 17, count 0 2006.162.08:10:04.00#ibcon#read 3, iclass 17, count 0 2006.162.08:10:04.00#ibcon#about to read 4, iclass 17, count 0 2006.162.08:10:04.00#ibcon#read 4, iclass 17, count 0 2006.162.08:10:04.00#ibcon#about to read 5, iclass 17, count 0 2006.162.08:10:04.00#ibcon#read 5, iclass 17, count 0 2006.162.08:10:04.00#ibcon#about to read 6, iclass 17, count 0 2006.162.08:10:04.00#ibcon#read 6, iclass 17, count 0 2006.162.08:10:04.00#ibcon#end of sib2, iclass 17, count 0 2006.162.08:10:04.00#ibcon#*mode == 0, iclass 17, count 0 2006.162.08:10:04.00#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.162.08:10:04.00#ibcon#[25=USB\r\n] 2006.162.08:10:04.00#ibcon#*before write, iclass 17, count 0 2006.162.08:10:04.00#ibcon#enter sib2, iclass 17, count 0 2006.162.08:10:04.00#ibcon#flushed, iclass 17, count 0 2006.162.08:10:04.00#ibcon#about to write, iclass 17, count 0 2006.162.08:10:04.00#ibcon#wrote, iclass 17, count 0 2006.162.08:10:04.00#ibcon#about to read 3, iclass 17, count 0 2006.162.08:10:04.03#ibcon#read 3, iclass 17, count 0 2006.162.08:10:04.03#ibcon#about to read 4, iclass 17, count 0 2006.162.08:10:04.03#ibcon#read 4, iclass 17, count 0 2006.162.08:10:04.03#ibcon#about to read 5, iclass 17, count 0 2006.162.08:10:04.03#ibcon#read 5, iclass 17, count 0 2006.162.08:10:04.03#ibcon#about to read 6, iclass 17, count 0 2006.162.08:10:04.03#ibcon#read 6, iclass 17, count 0 2006.162.08:10:04.03#ibcon#end of sib2, iclass 17, count 0 2006.162.08:10:04.03#ibcon#*after write, iclass 17, count 0 2006.162.08:10:04.03#ibcon#*before return 0, iclass 17, count 0 2006.162.08:10:04.03#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:10:04.03#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:10:04.03#ibcon#about to clear, iclass 17 cls_cnt 0 2006.162.08:10:04.03#ibcon#cleared, iclass 17 cls_cnt 0 2006.162.08:10:04.03$vc4f8/valo=7,832.99 2006.162.08:10:04.03#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.162.08:10:04.03#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.162.08:10:04.03#ibcon#ireg 17 cls_cnt 0 2006.162.08:10:04.03#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:10:04.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:10:04.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:10:04.03#ibcon#enter wrdev, iclass 19, count 0 2006.162.08:10:04.03#ibcon#first serial, iclass 19, count 0 2006.162.08:10:04.03#ibcon#enter sib2, iclass 19, count 0 2006.162.08:10:04.03#ibcon#flushed, iclass 19, count 0 2006.162.08:10:04.03#ibcon#about to write, iclass 19, count 0 2006.162.08:10:04.03#ibcon#wrote, iclass 19, count 0 2006.162.08:10:04.03#ibcon#about to read 3, iclass 19, count 0 2006.162.08:10:04.05#ibcon#read 3, iclass 19, count 0 2006.162.08:10:04.05#ibcon#about to read 4, iclass 19, count 0 2006.162.08:10:04.05#ibcon#read 4, iclass 19, count 0 2006.162.08:10:04.05#ibcon#about to read 5, iclass 19, count 0 2006.162.08:10:04.05#ibcon#read 5, iclass 19, count 0 2006.162.08:10:04.05#ibcon#about to read 6, iclass 19, count 0 2006.162.08:10:04.05#ibcon#read 6, iclass 19, count 0 2006.162.08:10:04.05#ibcon#end of sib2, iclass 19, count 0 2006.162.08:10:04.05#ibcon#*mode == 0, iclass 19, count 0 2006.162.08:10:04.05#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.162.08:10:04.05#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.08:10:04.05#ibcon#*before write, iclass 19, count 0 2006.162.08:10:04.05#ibcon#enter sib2, iclass 19, count 0 2006.162.08:10:04.05#ibcon#flushed, iclass 19, count 0 2006.162.08:10:04.05#ibcon#about to write, iclass 19, count 0 2006.162.08:10:04.05#ibcon#wrote, iclass 19, count 0 2006.162.08:10:04.05#ibcon#about to read 3, iclass 19, count 0 2006.162.08:10:04.09#ibcon#read 3, iclass 19, count 0 2006.162.08:10:04.09#ibcon#about to read 4, iclass 19, count 0 2006.162.08:10:04.09#ibcon#read 4, iclass 19, count 0 2006.162.08:10:04.09#ibcon#about to read 5, iclass 19, count 0 2006.162.08:10:04.09#ibcon#read 5, iclass 19, count 0 2006.162.08:10:04.09#ibcon#about to read 6, iclass 19, count 0 2006.162.08:10:04.09#ibcon#read 6, iclass 19, count 0 2006.162.08:10:04.09#ibcon#end of sib2, iclass 19, count 0 2006.162.08:10:04.09#ibcon#*after write, iclass 19, count 0 2006.162.08:10:04.09#ibcon#*before return 0, iclass 19, count 0 2006.162.08:10:04.09#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:10:04.09#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:10:04.09#ibcon#about to clear, iclass 19 cls_cnt 0 2006.162.08:10:04.09#ibcon#cleared, iclass 19 cls_cnt 0 2006.162.08:10:04.09$vc4f8/va=7,6 2006.162.08:10:04.09#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.162.08:10:04.09#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.162.08:10:04.09#ibcon#ireg 11 cls_cnt 2 2006.162.08:10:04.09#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.162.08:10:04.16#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.162.08:10:04.16#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.162.08:10:04.16#ibcon#enter wrdev, iclass 21, count 2 2006.162.08:10:04.16#ibcon#first serial, iclass 21, count 2 2006.162.08:10:04.16#ibcon#enter sib2, iclass 21, count 2 2006.162.08:10:04.16#ibcon#flushed, iclass 21, count 2 2006.162.08:10:04.16#ibcon#about to write, iclass 21, count 2 2006.162.08:10:04.16#ibcon#wrote, iclass 21, count 2 2006.162.08:10:04.16#ibcon#about to read 3, iclass 21, count 2 2006.162.08:10:04.17#ibcon#read 3, iclass 21, count 2 2006.162.08:10:04.17#ibcon#about to read 4, iclass 21, count 2 2006.162.08:10:04.17#ibcon#read 4, iclass 21, count 2 2006.162.08:10:04.17#ibcon#about to read 5, iclass 21, count 2 2006.162.08:10:04.17#ibcon#read 5, iclass 21, count 2 2006.162.08:10:04.17#ibcon#about to read 6, iclass 21, count 2 2006.162.08:10:04.17#ibcon#read 6, iclass 21, count 2 2006.162.08:10:04.17#ibcon#end of sib2, iclass 21, count 2 2006.162.08:10:04.17#ibcon#*mode == 0, iclass 21, count 2 2006.162.08:10:04.17#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.162.08:10:04.17#ibcon#[25=AT07-06\r\n] 2006.162.08:10:04.17#ibcon#*before write, iclass 21, count 2 2006.162.08:10:04.17#ibcon#enter sib2, iclass 21, count 2 2006.162.08:10:04.17#ibcon#flushed, iclass 21, count 2 2006.162.08:10:04.17#ibcon#about to write, iclass 21, count 2 2006.162.08:10:04.17#ibcon#wrote, iclass 21, count 2 2006.162.08:10:04.17#ibcon#about to read 3, iclass 21, count 2 2006.162.08:10:04.20#ibcon#read 3, iclass 21, count 2 2006.162.08:10:04.20#ibcon#about to read 4, iclass 21, count 2 2006.162.08:10:04.20#ibcon#read 4, iclass 21, count 2 2006.162.08:10:04.20#ibcon#about to read 5, iclass 21, count 2 2006.162.08:10:04.20#ibcon#read 5, iclass 21, count 2 2006.162.08:10:04.20#ibcon#about to read 6, iclass 21, count 2 2006.162.08:10:04.20#ibcon#read 6, iclass 21, count 2 2006.162.08:10:04.20#ibcon#end of sib2, iclass 21, count 2 2006.162.08:10:04.20#ibcon#*after write, iclass 21, count 2 2006.162.08:10:04.20#ibcon#*before return 0, iclass 21, count 2 2006.162.08:10:04.20#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.162.08:10:04.20#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.162.08:10:04.20#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.162.08:10:04.20#ibcon#ireg 7 cls_cnt 0 2006.162.08:10:04.20#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.162.08:10:04.29#abcon#<5=/03 1.8 3.6 17.831001007.1\r\n> 2006.162.08:10:04.31#abcon#{5=INTERFACE CLEAR} 2006.162.08:10:04.32#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.162.08:10:04.32#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.162.08:10:04.32#ibcon#enter wrdev, iclass 21, count 0 2006.162.08:10:04.32#ibcon#first serial, iclass 21, count 0 2006.162.08:10:04.32#ibcon#enter sib2, iclass 21, count 0 2006.162.08:10:04.32#ibcon#flushed, iclass 21, count 0 2006.162.08:10:04.32#ibcon#about to write, iclass 21, count 0 2006.162.08:10:04.32#ibcon#wrote, iclass 21, count 0 2006.162.08:10:04.32#ibcon#about to read 3, iclass 21, count 0 2006.162.08:10:04.34#ibcon#read 3, iclass 21, count 0 2006.162.08:10:04.34#ibcon#about to read 4, iclass 21, count 0 2006.162.08:10:04.34#ibcon#read 4, iclass 21, count 0 2006.162.08:10:04.34#ibcon#about to read 5, iclass 21, count 0 2006.162.08:10:04.34#ibcon#read 5, iclass 21, count 0 2006.162.08:10:04.34#ibcon#about to read 6, iclass 21, count 0 2006.162.08:10:04.34#ibcon#read 6, iclass 21, count 0 2006.162.08:10:04.34#ibcon#end of sib2, iclass 21, count 0 2006.162.08:10:04.34#ibcon#*mode == 0, iclass 21, count 0 2006.162.08:10:04.34#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.162.08:10:04.34#ibcon#[25=USB\r\n] 2006.162.08:10:04.34#ibcon#*before write, iclass 21, count 0 2006.162.08:10:04.34#ibcon#enter sib2, iclass 21, count 0 2006.162.08:10:04.34#ibcon#flushed, iclass 21, count 0 2006.162.08:10:04.34#ibcon#about to write, iclass 21, count 0 2006.162.08:10:04.34#ibcon#wrote, iclass 21, count 0 2006.162.08:10:04.34#ibcon#about to read 3, iclass 21, count 0 2006.162.08:10:04.37#abcon#[5=S1D000X0/0*\r\n] 2006.162.08:10:04.37#ibcon#read 3, iclass 21, count 0 2006.162.08:10:04.37#ibcon#about to read 4, iclass 21, count 0 2006.162.08:10:04.37#ibcon#read 4, iclass 21, count 0 2006.162.08:10:04.37#ibcon#about to read 5, iclass 21, count 0 2006.162.08:10:04.37#ibcon#read 5, iclass 21, count 0 2006.162.08:10:04.37#ibcon#about to read 6, iclass 21, count 0 2006.162.08:10:04.37#ibcon#read 6, iclass 21, count 0 2006.162.08:10:04.37#ibcon#end of sib2, iclass 21, count 0 2006.162.08:10:04.37#ibcon#*after write, iclass 21, count 0 2006.162.08:10:04.37#ibcon#*before return 0, iclass 21, count 0 2006.162.08:10:04.37#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.162.08:10:04.37#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.162.08:10:04.37#ibcon#about to clear, iclass 21 cls_cnt 0 2006.162.08:10:04.37#ibcon#cleared, iclass 21 cls_cnt 0 2006.162.08:10:04.37$vc4f8/valo=8,852.99 2006.162.08:10:04.37#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.162.08:10:04.37#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.162.08:10:04.37#ibcon#ireg 17 cls_cnt 0 2006.162.08:10:04.37#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.162.08:10:04.37#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.162.08:10:04.37#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.162.08:10:04.37#ibcon#enter wrdev, iclass 27, count 0 2006.162.08:10:04.37#ibcon#first serial, iclass 27, count 0 2006.162.08:10:04.37#ibcon#enter sib2, iclass 27, count 0 2006.162.08:10:04.37#ibcon#flushed, iclass 27, count 0 2006.162.08:10:04.37#ibcon#about to write, iclass 27, count 0 2006.162.08:10:04.37#ibcon#wrote, iclass 27, count 0 2006.162.08:10:04.37#ibcon#about to read 3, iclass 27, count 0 2006.162.08:10:04.39#ibcon#read 3, iclass 27, count 0 2006.162.08:10:04.39#ibcon#about to read 4, iclass 27, count 0 2006.162.08:10:04.39#ibcon#read 4, iclass 27, count 0 2006.162.08:10:04.39#ibcon#about to read 5, iclass 27, count 0 2006.162.08:10:04.39#ibcon#read 5, iclass 27, count 0 2006.162.08:10:04.39#ibcon#about to read 6, iclass 27, count 0 2006.162.08:10:04.39#ibcon#read 6, iclass 27, count 0 2006.162.08:10:04.39#ibcon#end of sib2, iclass 27, count 0 2006.162.08:10:04.39#ibcon#*mode == 0, iclass 27, count 0 2006.162.08:10:04.39#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.162.08:10:04.39#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.08:10:04.39#ibcon#*before write, iclass 27, count 0 2006.162.08:10:04.39#ibcon#enter sib2, iclass 27, count 0 2006.162.08:10:04.39#ibcon#flushed, iclass 27, count 0 2006.162.08:10:04.39#ibcon#about to write, iclass 27, count 0 2006.162.08:10:04.39#ibcon#wrote, iclass 27, count 0 2006.162.08:10:04.39#ibcon#about to read 3, iclass 27, count 0 2006.162.08:10:04.43#ibcon#read 3, iclass 27, count 0 2006.162.08:10:04.43#ibcon#about to read 4, iclass 27, count 0 2006.162.08:10:04.43#ibcon#read 4, iclass 27, count 0 2006.162.08:10:04.43#ibcon#about to read 5, iclass 27, count 0 2006.162.08:10:04.43#ibcon#read 5, iclass 27, count 0 2006.162.08:10:04.43#ibcon#about to read 6, iclass 27, count 0 2006.162.08:10:04.43#ibcon#read 6, iclass 27, count 0 2006.162.08:10:04.43#ibcon#end of sib2, iclass 27, count 0 2006.162.08:10:04.43#ibcon#*after write, iclass 27, count 0 2006.162.08:10:04.43#ibcon#*before return 0, iclass 27, count 0 2006.162.08:10:04.43#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.162.08:10:04.43#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.162.08:10:04.43#ibcon#about to clear, iclass 27 cls_cnt 0 2006.162.08:10:04.43#ibcon#cleared, iclass 27 cls_cnt 0 2006.162.08:10:04.43$vc4f8/va=8,7 2006.162.08:10:04.43#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.162.08:10:04.43#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.162.08:10:04.43#ibcon#ireg 11 cls_cnt 2 2006.162.08:10:04.43#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.162.08:10:04.49#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.162.08:10:04.49#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.162.08:10:04.49#ibcon#enter wrdev, iclass 29, count 2 2006.162.08:10:04.49#ibcon#first serial, iclass 29, count 2 2006.162.08:10:04.49#ibcon#enter sib2, iclass 29, count 2 2006.162.08:10:04.49#ibcon#flushed, iclass 29, count 2 2006.162.08:10:04.49#ibcon#about to write, iclass 29, count 2 2006.162.08:10:04.49#ibcon#wrote, iclass 29, count 2 2006.162.08:10:04.49#ibcon#about to read 3, iclass 29, count 2 2006.162.08:10:04.51#ibcon#read 3, iclass 29, count 2 2006.162.08:10:04.51#ibcon#about to read 4, iclass 29, count 2 2006.162.08:10:04.51#ibcon#read 4, iclass 29, count 2 2006.162.08:10:04.51#ibcon#about to read 5, iclass 29, count 2 2006.162.08:10:04.51#ibcon#read 5, iclass 29, count 2 2006.162.08:10:04.51#ibcon#about to read 6, iclass 29, count 2 2006.162.08:10:04.51#ibcon#read 6, iclass 29, count 2 2006.162.08:10:04.51#ibcon#end of sib2, iclass 29, count 2 2006.162.08:10:04.51#ibcon#*mode == 0, iclass 29, count 2 2006.162.08:10:04.51#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.162.08:10:04.51#ibcon#[25=AT08-07\r\n] 2006.162.08:10:04.51#ibcon#*before write, iclass 29, count 2 2006.162.08:10:04.51#ibcon#enter sib2, iclass 29, count 2 2006.162.08:10:04.51#ibcon#flushed, iclass 29, count 2 2006.162.08:10:04.51#ibcon#about to write, iclass 29, count 2 2006.162.08:10:04.51#ibcon#wrote, iclass 29, count 2 2006.162.08:10:04.51#ibcon#about to read 3, iclass 29, count 2 2006.162.08:10:04.54#ibcon#read 3, iclass 29, count 2 2006.162.08:10:04.54#ibcon#about to read 4, iclass 29, count 2 2006.162.08:10:04.54#ibcon#read 4, iclass 29, count 2 2006.162.08:10:04.54#ibcon#about to read 5, iclass 29, count 2 2006.162.08:10:04.54#ibcon#read 5, iclass 29, count 2 2006.162.08:10:04.54#ibcon#about to read 6, iclass 29, count 2 2006.162.08:10:04.54#ibcon#read 6, iclass 29, count 2 2006.162.08:10:04.54#ibcon#end of sib2, iclass 29, count 2 2006.162.08:10:04.54#ibcon#*after write, iclass 29, count 2 2006.162.08:10:04.54#ibcon#*before return 0, iclass 29, count 2 2006.162.08:10:04.54#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.162.08:10:04.54#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.162.08:10:04.54#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.162.08:10:04.54#ibcon#ireg 7 cls_cnt 0 2006.162.08:10:04.54#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.162.08:10:04.66#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.162.08:10:04.66#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.162.08:10:04.66#ibcon#enter wrdev, iclass 29, count 0 2006.162.08:10:04.66#ibcon#first serial, iclass 29, count 0 2006.162.08:10:04.66#ibcon#enter sib2, iclass 29, count 0 2006.162.08:10:04.66#ibcon#flushed, iclass 29, count 0 2006.162.08:10:04.66#ibcon#about to write, iclass 29, count 0 2006.162.08:10:04.66#ibcon#wrote, iclass 29, count 0 2006.162.08:10:04.66#ibcon#about to read 3, iclass 29, count 0 2006.162.08:10:04.68#ibcon#read 3, iclass 29, count 0 2006.162.08:10:04.68#ibcon#about to read 4, iclass 29, count 0 2006.162.08:10:04.68#ibcon#read 4, iclass 29, count 0 2006.162.08:10:04.68#ibcon#about to read 5, iclass 29, count 0 2006.162.08:10:04.68#ibcon#read 5, iclass 29, count 0 2006.162.08:10:04.68#ibcon#about to read 6, iclass 29, count 0 2006.162.08:10:04.68#ibcon#read 6, iclass 29, count 0 2006.162.08:10:04.68#ibcon#end of sib2, iclass 29, count 0 2006.162.08:10:04.68#ibcon#*mode == 0, iclass 29, count 0 2006.162.08:10:04.68#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.162.08:10:04.68#ibcon#[25=USB\r\n] 2006.162.08:10:04.68#ibcon#*before write, iclass 29, count 0 2006.162.08:10:04.68#ibcon#enter sib2, iclass 29, count 0 2006.162.08:10:04.68#ibcon#flushed, iclass 29, count 0 2006.162.08:10:04.68#ibcon#about to write, iclass 29, count 0 2006.162.08:10:04.68#ibcon#wrote, iclass 29, count 0 2006.162.08:10:04.68#ibcon#about to read 3, iclass 29, count 0 2006.162.08:10:04.71#ibcon#read 3, iclass 29, count 0 2006.162.08:10:04.71#ibcon#about to read 4, iclass 29, count 0 2006.162.08:10:04.71#ibcon#read 4, iclass 29, count 0 2006.162.08:10:04.71#ibcon#about to read 5, iclass 29, count 0 2006.162.08:10:04.71#ibcon#read 5, iclass 29, count 0 2006.162.08:10:04.71#ibcon#about to read 6, iclass 29, count 0 2006.162.08:10:04.71#ibcon#read 6, iclass 29, count 0 2006.162.08:10:04.71#ibcon#end of sib2, iclass 29, count 0 2006.162.08:10:04.71#ibcon#*after write, iclass 29, count 0 2006.162.08:10:04.71#ibcon#*before return 0, iclass 29, count 0 2006.162.08:10:04.71#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.162.08:10:04.71#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.162.08:10:04.71#ibcon#about to clear, iclass 29 cls_cnt 0 2006.162.08:10:04.71#ibcon#cleared, iclass 29 cls_cnt 0 2006.162.08:10:04.71$vc4f8/vblo=1,632.99 2006.162.08:10:04.71#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.162.08:10:04.71#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.162.08:10:04.71#ibcon#ireg 17 cls_cnt 0 2006.162.08:10:04.71#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.162.08:10:04.71#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.162.08:10:04.71#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.162.08:10:04.71#ibcon#enter wrdev, iclass 31, count 0 2006.162.08:10:04.71#ibcon#first serial, iclass 31, count 0 2006.162.08:10:04.71#ibcon#enter sib2, iclass 31, count 0 2006.162.08:10:04.71#ibcon#flushed, iclass 31, count 0 2006.162.08:10:04.71#ibcon#about to write, iclass 31, count 0 2006.162.08:10:04.71#ibcon#wrote, iclass 31, count 0 2006.162.08:10:04.71#ibcon#about to read 3, iclass 31, count 0 2006.162.08:10:04.73#ibcon#read 3, iclass 31, count 0 2006.162.08:10:04.73#ibcon#about to read 4, iclass 31, count 0 2006.162.08:10:04.73#ibcon#read 4, iclass 31, count 0 2006.162.08:10:04.73#ibcon#about to read 5, iclass 31, count 0 2006.162.08:10:04.73#ibcon#read 5, iclass 31, count 0 2006.162.08:10:04.73#ibcon#about to read 6, iclass 31, count 0 2006.162.08:10:04.73#ibcon#read 6, iclass 31, count 0 2006.162.08:10:04.73#ibcon#end of sib2, iclass 31, count 0 2006.162.08:10:04.73#ibcon#*mode == 0, iclass 31, count 0 2006.162.08:10:04.73#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.162.08:10:04.73#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.08:10:04.73#ibcon#*before write, iclass 31, count 0 2006.162.08:10:04.73#ibcon#enter sib2, iclass 31, count 0 2006.162.08:10:04.73#ibcon#flushed, iclass 31, count 0 2006.162.08:10:04.73#ibcon#about to write, iclass 31, count 0 2006.162.08:10:04.73#ibcon#wrote, iclass 31, count 0 2006.162.08:10:04.73#ibcon#about to read 3, iclass 31, count 0 2006.162.08:10:04.77#ibcon#read 3, iclass 31, count 0 2006.162.08:10:04.77#ibcon#about to read 4, iclass 31, count 0 2006.162.08:10:04.77#ibcon#read 4, iclass 31, count 0 2006.162.08:10:04.77#ibcon#about to read 5, iclass 31, count 0 2006.162.08:10:04.77#ibcon#read 5, iclass 31, count 0 2006.162.08:10:04.77#ibcon#about to read 6, iclass 31, count 0 2006.162.08:10:04.77#ibcon#read 6, iclass 31, count 0 2006.162.08:10:04.77#ibcon#end of sib2, iclass 31, count 0 2006.162.08:10:04.77#ibcon#*after write, iclass 31, count 0 2006.162.08:10:04.77#ibcon#*before return 0, iclass 31, count 0 2006.162.08:10:04.77#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.162.08:10:04.77#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.162.08:10:04.77#ibcon#about to clear, iclass 31 cls_cnt 0 2006.162.08:10:04.77#ibcon#cleared, iclass 31 cls_cnt 0 2006.162.08:10:04.77$vc4f8/vb=1,4 2006.162.08:10:04.77#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.162.08:10:04.77#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.162.08:10:04.77#ibcon#ireg 11 cls_cnt 2 2006.162.08:10:04.77#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.162.08:10:04.77#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.162.08:10:04.77#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.162.08:10:04.77#ibcon#enter wrdev, iclass 33, count 2 2006.162.08:10:04.77#ibcon#first serial, iclass 33, count 2 2006.162.08:10:04.77#ibcon#enter sib2, iclass 33, count 2 2006.162.08:10:04.77#ibcon#flushed, iclass 33, count 2 2006.162.08:10:04.77#ibcon#about to write, iclass 33, count 2 2006.162.08:10:04.77#ibcon#wrote, iclass 33, count 2 2006.162.08:10:04.77#ibcon#about to read 3, iclass 33, count 2 2006.162.08:10:04.79#ibcon#read 3, iclass 33, count 2 2006.162.08:10:04.79#ibcon#about to read 4, iclass 33, count 2 2006.162.08:10:04.79#ibcon#read 4, iclass 33, count 2 2006.162.08:10:04.79#ibcon#about to read 5, iclass 33, count 2 2006.162.08:10:04.79#ibcon#read 5, iclass 33, count 2 2006.162.08:10:04.79#ibcon#about to read 6, iclass 33, count 2 2006.162.08:10:04.79#ibcon#read 6, iclass 33, count 2 2006.162.08:10:04.79#ibcon#end of sib2, iclass 33, count 2 2006.162.08:10:04.79#ibcon#*mode == 0, iclass 33, count 2 2006.162.08:10:04.79#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.162.08:10:04.79#ibcon#[27=AT01-04\r\n] 2006.162.08:10:04.79#ibcon#*before write, iclass 33, count 2 2006.162.08:10:04.79#ibcon#enter sib2, iclass 33, count 2 2006.162.08:10:04.79#ibcon#flushed, iclass 33, count 2 2006.162.08:10:04.79#ibcon#about to write, iclass 33, count 2 2006.162.08:10:04.79#ibcon#wrote, iclass 33, count 2 2006.162.08:10:04.79#ibcon#about to read 3, iclass 33, count 2 2006.162.08:10:04.82#ibcon#read 3, iclass 33, count 2 2006.162.08:10:04.82#ibcon#about to read 4, iclass 33, count 2 2006.162.08:10:04.82#ibcon#read 4, iclass 33, count 2 2006.162.08:10:04.82#ibcon#about to read 5, iclass 33, count 2 2006.162.08:10:04.82#ibcon#read 5, iclass 33, count 2 2006.162.08:10:04.82#ibcon#about to read 6, iclass 33, count 2 2006.162.08:10:04.82#ibcon#read 6, iclass 33, count 2 2006.162.08:10:04.82#ibcon#end of sib2, iclass 33, count 2 2006.162.08:10:04.82#ibcon#*after write, iclass 33, count 2 2006.162.08:10:04.82#ibcon#*before return 0, iclass 33, count 2 2006.162.08:10:04.82#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.162.08:10:04.82#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.162.08:10:04.82#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.162.08:10:04.82#ibcon#ireg 7 cls_cnt 0 2006.162.08:10:04.82#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.162.08:10:04.94#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.162.08:10:04.94#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.162.08:10:04.94#ibcon#enter wrdev, iclass 33, count 0 2006.162.08:10:04.94#ibcon#first serial, iclass 33, count 0 2006.162.08:10:04.94#ibcon#enter sib2, iclass 33, count 0 2006.162.08:10:04.94#ibcon#flushed, iclass 33, count 0 2006.162.08:10:04.94#ibcon#about to write, iclass 33, count 0 2006.162.08:10:04.94#ibcon#wrote, iclass 33, count 0 2006.162.08:10:04.94#ibcon#about to read 3, iclass 33, count 0 2006.162.08:10:04.96#ibcon#read 3, iclass 33, count 0 2006.162.08:10:04.96#ibcon#about to read 4, iclass 33, count 0 2006.162.08:10:04.96#ibcon#read 4, iclass 33, count 0 2006.162.08:10:04.96#ibcon#about to read 5, iclass 33, count 0 2006.162.08:10:04.96#ibcon#read 5, iclass 33, count 0 2006.162.08:10:04.96#ibcon#about to read 6, iclass 33, count 0 2006.162.08:10:04.96#ibcon#read 6, iclass 33, count 0 2006.162.08:10:04.96#ibcon#end of sib2, iclass 33, count 0 2006.162.08:10:04.96#ibcon#*mode == 0, iclass 33, count 0 2006.162.08:10:04.96#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.162.08:10:04.96#ibcon#[27=USB\r\n] 2006.162.08:10:04.96#ibcon#*before write, iclass 33, count 0 2006.162.08:10:04.96#ibcon#enter sib2, iclass 33, count 0 2006.162.08:10:04.96#ibcon#flushed, iclass 33, count 0 2006.162.08:10:04.96#ibcon#about to write, iclass 33, count 0 2006.162.08:10:04.96#ibcon#wrote, iclass 33, count 0 2006.162.08:10:04.96#ibcon#about to read 3, iclass 33, count 0 2006.162.08:10:04.99#ibcon#read 3, iclass 33, count 0 2006.162.08:10:04.99#ibcon#about to read 4, iclass 33, count 0 2006.162.08:10:04.99#ibcon#read 4, iclass 33, count 0 2006.162.08:10:04.99#ibcon#about to read 5, iclass 33, count 0 2006.162.08:10:04.99#ibcon#read 5, iclass 33, count 0 2006.162.08:10:04.99#ibcon#about to read 6, iclass 33, count 0 2006.162.08:10:04.99#ibcon#read 6, iclass 33, count 0 2006.162.08:10:04.99#ibcon#end of sib2, iclass 33, count 0 2006.162.08:10:04.99#ibcon#*after write, iclass 33, count 0 2006.162.08:10:04.99#ibcon#*before return 0, iclass 33, count 0 2006.162.08:10:04.99#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.162.08:10:04.99#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.162.08:10:04.99#ibcon#about to clear, iclass 33 cls_cnt 0 2006.162.08:10:04.99#ibcon#cleared, iclass 33 cls_cnt 0 2006.162.08:10:04.99$vc4f8/vblo=2,640.99 2006.162.08:10:04.99#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.162.08:10:04.99#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.162.08:10:04.99#ibcon#ireg 17 cls_cnt 0 2006.162.08:10:04.99#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.162.08:10:04.99#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.162.08:10:04.99#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.162.08:10:04.99#ibcon#enter wrdev, iclass 35, count 0 2006.162.08:10:04.99#ibcon#first serial, iclass 35, count 0 2006.162.08:10:04.99#ibcon#enter sib2, iclass 35, count 0 2006.162.08:10:04.99#ibcon#flushed, iclass 35, count 0 2006.162.08:10:04.99#ibcon#about to write, iclass 35, count 0 2006.162.08:10:04.99#ibcon#wrote, iclass 35, count 0 2006.162.08:10:04.99#ibcon#about to read 3, iclass 35, count 0 2006.162.08:10:05.01#ibcon#read 3, iclass 35, count 0 2006.162.08:10:05.01#ibcon#about to read 4, iclass 35, count 0 2006.162.08:10:05.01#ibcon#read 4, iclass 35, count 0 2006.162.08:10:05.01#ibcon#about to read 5, iclass 35, count 0 2006.162.08:10:05.01#ibcon#read 5, iclass 35, count 0 2006.162.08:10:05.01#ibcon#about to read 6, iclass 35, count 0 2006.162.08:10:05.01#ibcon#read 6, iclass 35, count 0 2006.162.08:10:05.01#ibcon#end of sib2, iclass 35, count 0 2006.162.08:10:05.01#ibcon#*mode == 0, iclass 35, count 0 2006.162.08:10:05.01#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.162.08:10:05.01#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.08:10:05.01#ibcon#*before write, iclass 35, count 0 2006.162.08:10:05.01#ibcon#enter sib2, iclass 35, count 0 2006.162.08:10:05.01#ibcon#flushed, iclass 35, count 0 2006.162.08:10:05.01#ibcon#about to write, iclass 35, count 0 2006.162.08:10:05.01#ibcon#wrote, iclass 35, count 0 2006.162.08:10:05.01#ibcon#about to read 3, iclass 35, count 0 2006.162.08:10:05.05#ibcon#read 3, iclass 35, count 0 2006.162.08:10:05.05#ibcon#about to read 4, iclass 35, count 0 2006.162.08:10:05.05#ibcon#read 4, iclass 35, count 0 2006.162.08:10:05.05#ibcon#about to read 5, iclass 35, count 0 2006.162.08:10:05.05#ibcon#read 5, iclass 35, count 0 2006.162.08:10:05.05#ibcon#about to read 6, iclass 35, count 0 2006.162.08:10:05.05#ibcon#read 6, iclass 35, count 0 2006.162.08:10:05.05#ibcon#end of sib2, iclass 35, count 0 2006.162.08:10:05.05#ibcon#*after write, iclass 35, count 0 2006.162.08:10:05.05#ibcon#*before return 0, iclass 35, count 0 2006.162.08:10:05.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.162.08:10:05.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.162.08:10:05.05#ibcon#about to clear, iclass 35 cls_cnt 0 2006.162.08:10:05.05#ibcon#cleared, iclass 35 cls_cnt 0 2006.162.08:10:05.05$vc4f8/vb=2,4 2006.162.08:10:05.05#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.162.08:10:05.05#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.162.08:10:05.05#ibcon#ireg 11 cls_cnt 2 2006.162.08:10:05.05#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.162.08:10:05.11#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.162.08:10:05.11#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.162.08:10:05.11#ibcon#enter wrdev, iclass 37, count 2 2006.162.08:10:05.11#ibcon#first serial, iclass 37, count 2 2006.162.08:10:05.11#ibcon#enter sib2, iclass 37, count 2 2006.162.08:10:05.11#ibcon#flushed, iclass 37, count 2 2006.162.08:10:05.11#ibcon#about to write, iclass 37, count 2 2006.162.08:10:05.11#ibcon#wrote, iclass 37, count 2 2006.162.08:10:05.11#ibcon#about to read 3, iclass 37, count 2 2006.162.08:10:05.13#ibcon#read 3, iclass 37, count 2 2006.162.08:10:05.13#ibcon#about to read 4, iclass 37, count 2 2006.162.08:10:05.13#ibcon#read 4, iclass 37, count 2 2006.162.08:10:05.13#ibcon#about to read 5, iclass 37, count 2 2006.162.08:10:05.13#ibcon#read 5, iclass 37, count 2 2006.162.08:10:05.13#ibcon#about to read 6, iclass 37, count 2 2006.162.08:10:05.13#ibcon#read 6, iclass 37, count 2 2006.162.08:10:05.13#ibcon#end of sib2, iclass 37, count 2 2006.162.08:10:05.13#ibcon#*mode == 0, iclass 37, count 2 2006.162.08:10:05.13#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.162.08:10:05.13#ibcon#[27=AT02-04\r\n] 2006.162.08:10:05.13#ibcon#*before write, iclass 37, count 2 2006.162.08:10:05.13#ibcon#enter sib2, iclass 37, count 2 2006.162.08:10:05.13#ibcon#flushed, iclass 37, count 2 2006.162.08:10:05.13#ibcon#about to write, iclass 37, count 2 2006.162.08:10:05.13#ibcon#wrote, iclass 37, count 2 2006.162.08:10:05.13#ibcon#about to read 3, iclass 37, count 2 2006.162.08:10:05.16#ibcon#read 3, iclass 37, count 2 2006.162.08:10:05.16#ibcon#about to read 4, iclass 37, count 2 2006.162.08:10:05.16#ibcon#read 4, iclass 37, count 2 2006.162.08:10:05.16#ibcon#about to read 5, iclass 37, count 2 2006.162.08:10:05.16#ibcon#read 5, iclass 37, count 2 2006.162.08:10:05.16#ibcon#about to read 6, iclass 37, count 2 2006.162.08:10:05.16#ibcon#read 6, iclass 37, count 2 2006.162.08:10:05.16#ibcon#end of sib2, iclass 37, count 2 2006.162.08:10:05.16#ibcon#*after write, iclass 37, count 2 2006.162.08:10:05.16#ibcon#*before return 0, iclass 37, count 2 2006.162.08:10:05.16#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.162.08:10:05.16#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.162.08:10:05.16#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.162.08:10:05.16#ibcon#ireg 7 cls_cnt 0 2006.162.08:10:05.16#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.162.08:10:05.28#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.162.08:10:05.28#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.162.08:10:05.28#ibcon#enter wrdev, iclass 37, count 0 2006.162.08:10:05.28#ibcon#first serial, iclass 37, count 0 2006.162.08:10:05.28#ibcon#enter sib2, iclass 37, count 0 2006.162.08:10:05.28#ibcon#flushed, iclass 37, count 0 2006.162.08:10:05.28#ibcon#about to write, iclass 37, count 0 2006.162.08:10:05.28#ibcon#wrote, iclass 37, count 0 2006.162.08:10:05.28#ibcon#about to read 3, iclass 37, count 0 2006.162.08:10:05.30#ibcon#read 3, iclass 37, count 0 2006.162.08:10:05.30#ibcon#about to read 4, iclass 37, count 0 2006.162.08:10:05.30#ibcon#read 4, iclass 37, count 0 2006.162.08:10:05.30#ibcon#about to read 5, iclass 37, count 0 2006.162.08:10:05.30#ibcon#read 5, iclass 37, count 0 2006.162.08:10:05.30#ibcon#about to read 6, iclass 37, count 0 2006.162.08:10:05.30#ibcon#read 6, iclass 37, count 0 2006.162.08:10:05.30#ibcon#end of sib2, iclass 37, count 0 2006.162.08:10:05.30#ibcon#*mode == 0, iclass 37, count 0 2006.162.08:10:05.30#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.162.08:10:05.30#ibcon#[27=USB\r\n] 2006.162.08:10:05.30#ibcon#*before write, iclass 37, count 0 2006.162.08:10:05.30#ibcon#enter sib2, iclass 37, count 0 2006.162.08:10:05.30#ibcon#flushed, iclass 37, count 0 2006.162.08:10:05.30#ibcon#about to write, iclass 37, count 0 2006.162.08:10:05.30#ibcon#wrote, iclass 37, count 0 2006.162.08:10:05.30#ibcon#about to read 3, iclass 37, count 0 2006.162.08:10:05.33#ibcon#read 3, iclass 37, count 0 2006.162.08:10:05.33#ibcon#about to read 4, iclass 37, count 0 2006.162.08:10:05.33#ibcon#read 4, iclass 37, count 0 2006.162.08:10:05.33#ibcon#about to read 5, iclass 37, count 0 2006.162.08:10:05.33#ibcon#read 5, iclass 37, count 0 2006.162.08:10:05.33#ibcon#about to read 6, iclass 37, count 0 2006.162.08:10:05.33#ibcon#read 6, iclass 37, count 0 2006.162.08:10:05.33#ibcon#end of sib2, iclass 37, count 0 2006.162.08:10:05.33#ibcon#*after write, iclass 37, count 0 2006.162.08:10:05.33#ibcon#*before return 0, iclass 37, count 0 2006.162.08:10:05.33#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.162.08:10:05.33#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.162.08:10:05.33#ibcon#about to clear, iclass 37 cls_cnt 0 2006.162.08:10:05.33#ibcon#cleared, iclass 37 cls_cnt 0 2006.162.08:10:05.33$vc4f8/vblo=3,656.99 2006.162.08:10:05.33#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.162.08:10:05.33#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.162.08:10:05.33#ibcon#ireg 17 cls_cnt 0 2006.162.08:10:05.33#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:10:05.33#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:10:05.33#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:10:05.33#ibcon#enter wrdev, iclass 39, count 0 2006.162.08:10:05.33#ibcon#first serial, iclass 39, count 0 2006.162.08:10:05.33#ibcon#enter sib2, iclass 39, count 0 2006.162.08:10:05.33#ibcon#flushed, iclass 39, count 0 2006.162.08:10:05.33#ibcon#about to write, iclass 39, count 0 2006.162.08:10:05.33#ibcon#wrote, iclass 39, count 0 2006.162.08:10:05.33#ibcon#about to read 3, iclass 39, count 0 2006.162.08:10:05.35#ibcon#read 3, iclass 39, count 0 2006.162.08:10:05.35#ibcon#about to read 4, iclass 39, count 0 2006.162.08:10:05.35#ibcon#read 4, iclass 39, count 0 2006.162.08:10:05.35#ibcon#about to read 5, iclass 39, count 0 2006.162.08:10:05.35#ibcon#read 5, iclass 39, count 0 2006.162.08:10:05.35#ibcon#about to read 6, iclass 39, count 0 2006.162.08:10:05.35#ibcon#read 6, iclass 39, count 0 2006.162.08:10:05.35#ibcon#end of sib2, iclass 39, count 0 2006.162.08:10:05.35#ibcon#*mode == 0, iclass 39, count 0 2006.162.08:10:05.35#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.162.08:10:05.35#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.08:10:05.35#ibcon#*before write, iclass 39, count 0 2006.162.08:10:05.35#ibcon#enter sib2, iclass 39, count 0 2006.162.08:10:05.35#ibcon#flushed, iclass 39, count 0 2006.162.08:10:05.35#ibcon#about to write, iclass 39, count 0 2006.162.08:10:05.35#ibcon#wrote, iclass 39, count 0 2006.162.08:10:05.35#ibcon#about to read 3, iclass 39, count 0 2006.162.08:10:05.39#ibcon#read 3, iclass 39, count 0 2006.162.08:10:05.39#ibcon#about to read 4, iclass 39, count 0 2006.162.08:10:05.39#ibcon#read 4, iclass 39, count 0 2006.162.08:10:05.39#ibcon#about to read 5, iclass 39, count 0 2006.162.08:10:05.39#ibcon#read 5, iclass 39, count 0 2006.162.08:10:05.39#ibcon#about to read 6, iclass 39, count 0 2006.162.08:10:05.39#ibcon#read 6, iclass 39, count 0 2006.162.08:10:05.39#ibcon#end of sib2, iclass 39, count 0 2006.162.08:10:05.39#ibcon#*after write, iclass 39, count 0 2006.162.08:10:05.39#ibcon#*before return 0, iclass 39, count 0 2006.162.08:10:05.39#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:10:05.39#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:10:05.39#ibcon#about to clear, iclass 39 cls_cnt 0 2006.162.08:10:05.39#ibcon#cleared, iclass 39 cls_cnt 0 2006.162.08:10:05.39$vc4f8/vb=3,4 2006.162.08:10:05.39#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.162.08:10:05.39#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.162.08:10:05.39#ibcon#ireg 11 cls_cnt 2 2006.162.08:10:05.39#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:10:05.45#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:10:05.45#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:10:05.45#ibcon#enter wrdev, iclass 3, count 2 2006.162.08:10:05.45#ibcon#first serial, iclass 3, count 2 2006.162.08:10:05.45#ibcon#enter sib2, iclass 3, count 2 2006.162.08:10:05.45#ibcon#flushed, iclass 3, count 2 2006.162.08:10:05.45#ibcon#about to write, iclass 3, count 2 2006.162.08:10:05.45#ibcon#wrote, iclass 3, count 2 2006.162.08:10:05.45#ibcon#about to read 3, iclass 3, count 2 2006.162.08:10:05.47#ibcon#read 3, iclass 3, count 2 2006.162.08:10:05.47#ibcon#about to read 4, iclass 3, count 2 2006.162.08:10:05.47#ibcon#read 4, iclass 3, count 2 2006.162.08:10:05.47#ibcon#about to read 5, iclass 3, count 2 2006.162.08:10:05.47#ibcon#read 5, iclass 3, count 2 2006.162.08:10:05.47#ibcon#about to read 6, iclass 3, count 2 2006.162.08:10:05.47#ibcon#read 6, iclass 3, count 2 2006.162.08:10:05.47#ibcon#end of sib2, iclass 3, count 2 2006.162.08:10:05.47#ibcon#*mode == 0, iclass 3, count 2 2006.162.08:10:05.47#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.162.08:10:05.47#ibcon#[27=AT03-04\r\n] 2006.162.08:10:05.47#ibcon#*before write, iclass 3, count 2 2006.162.08:10:05.47#ibcon#enter sib2, iclass 3, count 2 2006.162.08:10:05.47#ibcon#flushed, iclass 3, count 2 2006.162.08:10:05.47#ibcon#about to write, iclass 3, count 2 2006.162.08:10:05.47#ibcon#wrote, iclass 3, count 2 2006.162.08:10:05.47#ibcon#about to read 3, iclass 3, count 2 2006.162.08:10:05.50#ibcon#read 3, iclass 3, count 2 2006.162.08:10:05.50#ibcon#about to read 4, iclass 3, count 2 2006.162.08:10:05.50#ibcon#read 4, iclass 3, count 2 2006.162.08:10:05.50#ibcon#about to read 5, iclass 3, count 2 2006.162.08:10:05.50#ibcon#read 5, iclass 3, count 2 2006.162.08:10:05.50#ibcon#about to read 6, iclass 3, count 2 2006.162.08:10:05.50#ibcon#read 6, iclass 3, count 2 2006.162.08:10:05.50#ibcon#end of sib2, iclass 3, count 2 2006.162.08:10:05.50#ibcon#*after write, iclass 3, count 2 2006.162.08:10:05.50#ibcon#*before return 0, iclass 3, count 2 2006.162.08:10:05.50#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:10:05.50#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:10:05.50#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.162.08:10:05.50#ibcon#ireg 7 cls_cnt 0 2006.162.08:10:05.50#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:10:05.62#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:10:05.62#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:10:05.62#ibcon#enter wrdev, iclass 3, count 0 2006.162.08:10:05.62#ibcon#first serial, iclass 3, count 0 2006.162.08:10:05.62#ibcon#enter sib2, iclass 3, count 0 2006.162.08:10:05.62#ibcon#flushed, iclass 3, count 0 2006.162.08:10:05.62#ibcon#about to write, iclass 3, count 0 2006.162.08:10:05.62#ibcon#wrote, iclass 3, count 0 2006.162.08:10:05.62#ibcon#about to read 3, iclass 3, count 0 2006.162.08:10:05.64#ibcon#read 3, iclass 3, count 0 2006.162.08:10:05.64#ibcon#about to read 4, iclass 3, count 0 2006.162.08:10:05.64#ibcon#read 4, iclass 3, count 0 2006.162.08:10:05.64#ibcon#about to read 5, iclass 3, count 0 2006.162.08:10:05.64#ibcon#read 5, iclass 3, count 0 2006.162.08:10:05.64#ibcon#about to read 6, iclass 3, count 0 2006.162.08:10:05.64#ibcon#read 6, iclass 3, count 0 2006.162.08:10:05.64#ibcon#end of sib2, iclass 3, count 0 2006.162.08:10:05.64#ibcon#*mode == 0, iclass 3, count 0 2006.162.08:10:05.64#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.162.08:10:05.64#ibcon#[27=USB\r\n] 2006.162.08:10:05.64#ibcon#*before write, iclass 3, count 0 2006.162.08:10:05.64#ibcon#enter sib2, iclass 3, count 0 2006.162.08:10:05.64#ibcon#flushed, iclass 3, count 0 2006.162.08:10:05.64#ibcon#about to write, iclass 3, count 0 2006.162.08:10:05.64#ibcon#wrote, iclass 3, count 0 2006.162.08:10:05.64#ibcon#about to read 3, iclass 3, count 0 2006.162.08:10:05.67#ibcon#read 3, iclass 3, count 0 2006.162.08:10:05.67#ibcon#about to read 4, iclass 3, count 0 2006.162.08:10:05.67#ibcon#read 4, iclass 3, count 0 2006.162.08:10:05.67#ibcon#about to read 5, iclass 3, count 0 2006.162.08:10:05.67#ibcon#read 5, iclass 3, count 0 2006.162.08:10:05.67#ibcon#about to read 6, iclass 3, count 0 2006.162.08:10:05.67#ibcon#read 6, iclass 3, count 0 2006.162.08:10:05.67#ibcon#end of sib2, iclass 3, count 0 2006.162.08:10:05.67#ibcon#*after write, iclass 3, count 0 2006.162.08:10:05.67#ibcon#*before return 0, iclass 3, count 0 2006.162.08:10:05.67#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:10:05.67#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:10:05.67#ibcon#about to clear, iclass 3 cls_cnt 0 2006.162.08:10:05.67#ibcon#cleared, iclass 3 cls_cnt 0 2006.162.08:10:05.67$vc4f8/vblo=4,712.99 2006.162.08:10:05.67#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.162.08:10:05.67#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.162.08:10:05.67#ibcon#ireg 17 cls_cnt 0 2006.162.08:10:05.67#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:10:05.67#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:10:05.67#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:10:05.67#ibcon#enter wrdev, iclass 5, count 0 2006.162.08:10:05.67#ibcon#first serial, iclass 5, count 0 2006.162.08:10:05.67#ibcon#enter sib2, iclass 5, count 0 2006.162.08:10:05.67#ibcon#flushed, iclass 5, count 0 2006.162.08:10:05.67#ibcon#about to write, iclass 5, count 0 2006.162.08:10:05.67#ibcon#wrote, iclass 5, count 0 2006.162.08:10:05.67#ibcon#about to read 3, iclass 5, count 0 2006.162.08:10:05.69#ibcon#read 3, iclass 5, count 0 2006.162.08:10:05.69#ibcon#about to read 4, iclass 5, count 0 2006.162.08:10:05.69#ibcon#read 4, iclass 5, count 0 2006.162.08:10:05.69#ibcon#about to read 5, iclass 5, count 0 2006.162.08:10:05.69#ibcon#read 5, iclass 5, count 0 2006.162.08:10:05.69#ibcon#about to read 6, iclass 5, count 0 2006.162.08:10:05.69#ibcon#read 6, iclass 5, count 0 2006.162.08:10:05.69#ibcon#end of sib2, iclass 5, count 0 2006.162.08:10:05.69#ibcon#*mode == 0, iclass 5, count 0 2006.162.08:10:05.69#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.162.08:10:05.69#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.08:10:05.69#ibcon#*before write, iclass 5, count 0 2006.162.08:10:05.69#ibcon#enter sib2, iclass 5, count 0 2006.162.08:10:05.69#ibcon#flushed, iclass 5, count 0 2006.162.08:10:05.69#ibcon#about to write, iclass 5, count 0 2006.162.08:10:05.69#ibcon#wrote, iclass 5, count 0 2006.162.08:10:05.69#ibcon#about to read 3, iclass 5, count 0 2006.162.08:10:05.73#ibcon#read 3, iclass 5, count 0 2006.162.08:10:05.73#ibcon#about to read 4, iclass 5, count 0 2006.162.08:10:05.73#ibcon#read 4, iclass 5, count 0 2006.162.08:10:05.73#ibcon#about to read 5, iclass 5, count 0 2006.162.08:10:05.73#ibcon#read 5, iclass 5, count 0 2006.162.08:10:05.73#ibcon#about to read 6, iclass 5, count 0 2006.162.08:10:05.73#ibcon#read 6, iclass 5, count 0 2006.162.08:10:05.73#ibcon#end of sib2, iclass 5, count 0 2006.162.08:10:05.73#ibcon#*after write, iclass 5, count 0 2006.162.08:10:05.73#ibcon#*before return 0, iclass 5, count 0 2006.162.08:10:05.73#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:10:05.73#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:10:05.73#ibcon#about to clear, iclass 5 cls_cnt 0 2006.162.08:10:05.73#ibcon#cleared, iclass 5 cls_cnt 0 2006.162.08:10:05.73$vc4f8/vb=4,4 2006.162.08:10:05.73#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.162.08:10:05.73#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.162.08:10:05.73#ibcon#ireg 11 cls_cnt 2 2006.162.08:10:05.73#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:10:05.79#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:10:05.79#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:10:05.79#ibcon#enter wrdev, iclass 7, count 2 2006.162.08:10:05.79#ibcon#first serial, iclass 7, count 2 2006.162.08:10:05.79#ibcon#enter sib2, iclass 7, count 2 2006.162.08:10:05.79#ibcon#flushed, iclass 7, count 2 2006.162.08:10:05.79#ibcon#about to write, iclass 7, count 2 2006.162.08:10:05.79#ibcon#wrote, iclass 7, count 2 2006.162.08:10:05.79#ibcon#about to read 3, iclass 7, count 2 2006.162.08:10:05.81#ibcon#read 3, iclass 7, count 2 2006.162.08:10:05.81#ibcon#about to read 4, iclass 7, count 2 2006.162.08:10:05.81#ibcon#read 4, iclass 7, count 2 2006.162.08:10:05.81#ibcon#about to read 5, iclass 7, count 2 2006.162.08:10:05.81#ibcon#read 5, iclass 7, count 2 2006.162.08:10:05.81#ibcon#about to read 6, iclass 7, count 2 2006.162.08:10:05.81#ibcon#read 6, iclass 7, count 2 2006.162.08:10:05.81#ibcon#end of sib2, iclass 7, count 2 2006.162.08:10:05.81#ibcon#*mode == 0, iclass 7, count 2 2006.162.08:10:05.81#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.162.08:10:05.81#ibcon#[27=AT04-04\r\n] 2006.162.08:10:05.81#ibcon#*before write, iclass 7, count 2 2006.162.08:10:05.81#ibcon#enter sib2, iclass 7, count 2 2006.162.08:10:05.81#ibcon#flushed, iclass 7, count 2 2006.162.08:10:05.81#ibcon#about to write, iclass 7, count 2 2006.162.08:10:05.81#ibcon#wrote, iclass 7, count 2 2006.162.08:10:05.81#ibcon#about to read 3, iclass 7, count 2 2006.162.08:10:05.84#ibcon#read 3, iclass 7, count 2 2006.162.08:10:05.84#ibcon#about to read 4, iclass 7, count 2 2006.162.08:10:05.84#ibcon#read 4, iclass 7, count 2 2006.162.08:10:05.84#ibcon#about to read 5, iclass 7, count 2 2006.162.08:10:05.84#ibcon#read 5, iclass 7, count 2 2006.162.08:10:05.84#ibcon#about to read 6, iclass 7, count 2 2006.162.08:10:05.84#ibcon#read 6, iclass 7, count 2 2006.162.08:10:05.84#ibcon#end of sib2, iclass 7, count 2 2006.162.08:10:05.84#ibcon#*after write, iclass 7, count 2 2006.162.08:10:05.84#ibcon#*before return 0, iclass 7, count 2 2006.162.08:10:05.84#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:10:05.84#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:10:05.84#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.162.08:10:05.84#ibcon#ireg 7 cls_cnt 0 2006.162.08:10:05.84#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:10:05.96#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:10:05.96#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:10:05.96#ibcon#enter wrdev, iclass 7, count 0 2006.162.08:10:05.96#ibcon#first serial, iclass 7, count 0 2006.162.08:10:05.96#ibcon#enter sib2, iclass 7, count 0 2006.162.08:10:05.96#ibcon#flushed, iclass 7, count 0 2006.162.08:10:05.96#ibcon#about to write, iclass 7, count 0 2006.162.08:10:05.96#ibcon#wrote, iclass 7, count 0 2006.162.08:10:05.96#ibcon#about to read 3, iclass 7, count 0 2006.162.08:10:05.98#ibcon#read 3, iclass 7, count 0 2006.162.08:10:05.98#ibcon#about to read 4, iclass 7, count 0 2006.162.08:10:05.98#ibcon#read 4, iclass 7, count 0 2006.162.08:10:05.98#ibcon#about to read 5, iclass 7, count 0 2006.162.08:10:05.98#ibcon#read 5, iclass 7, count 0 2006.162.08:10:05.98#ibcon#about to read 6, iclass 7, count 0 2006.162.08:10:05.98#ibcon#read 6, iclass 7, count 0 2006.162.08:10:05.98#ibcon#end of sib2, iclass 7, count 0 2006.162.08:10:05.98#ibcon#*mode == 0, iclass 7, count 0 2006.162.08:10:05.98#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.162.08:10:05.98#ibcon#[27=USB\r\n] 2006.162.08:10:05.98#ibcon#*before write, iclass 7, count 0 2006.162.08:10:05.98#ibcon#enter sib2, iclass 7, count 0 2006.162.08:10:05.98#ibcon#flushed, iclass 7, count 0 2006.162.08:10:05.98#ibcon#about to write, iclass 7, count 0 2006.162.08:10:05.98#ibcon#wrote, iclass 7, count 0 2006.162.08:10:05.98#ibcon#about to read 3, iclass 7, count 0 2006.162.08:10:06.01#ibcon#read 3, iclass 7, count 0 2006.162.08:10:06.01#ibcon#about to read 4, iclass 7, count 0 2006.162.08:10:06.01#ibcon#read 4, iclass 7, count 0 2006.162.08:10:06.01#ibcon#about to read 5, iclass 7, count 0 2006.162.08:10:06.01#ibcon#read 5, iclass 7, count 0 2006.162.08:10:06.01#ibcon#about to read 6, iclass 7, count 0 2006.162.08:10:06.01#ibcon#read 6, iclass 7, count 0 2006.162.08:10:06.01#ibcon#end of sib2, iclass 7, count 0 2006.162.08:10:06.01#ibcon#*after write, iclass 7, count 0 2006.162.08:10:06.01#ibcon#*before return 0, iclass 7, count 0 2006.162.08:10:06.01#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:10:06.01#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:10:06.01#ibcon#about to clear, iclass 7 cls_cnt 0 2006.162.08:10:06.01#ibcon#cleared, iclass 7 cls_cnt 0 2006.162.08:10:06.01$vc4f8/vblo=5,744.99 2006.162.08:10:06.01#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.162.08:10:06.01#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.162.08:10:06.01#ibcon#ireg 17 cls_cnt 0 2006.162.08:10:06.01#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:10:06.01#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:10:06.01#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:10:06.01#ibcon#enter wrdev, iclass 11, count 0 2006.162.08:10:06.01#ibcon#first serial, iclass 11, count 0 2006.162.08:10:06.01#ibcon#enter sib2, iclass 11, count 0 2006.162.08:10:06.01#ibcon#flushed, iclass 11, count 0 2006.162.08:10:06.01#ibcon#about to write, iclass 11, count 0 2006.162.08:10:06.01#ibcon#wrote, iclass 11, count 0 2006.162.08:10:06.01#ibcon#about to read 3, iclass 11, count 0 2006.162.08:10:06.03#ibcon#read 3, iclass 11, count 0 2006.162.08:10:06.03#ibcon#about to read 4, iclass 11, count 0 2006.162.08:10:06.03#ibcon#read 4, iclass 11, count 0 2006.162.08:10:06.03#ibcon#about to read 5, iclass 11, count 0 2006.162.08:10:06.03#ibcon#read 5, iclass 11, count 0 2006.162.08:10:06.03#ibcon#about to read 6, iclass 11, count 0 2006.162.08:10:06.03#ibcon#read 6, iclass 11, count 0 2006.162.08:10:06.03#ibcon#end of sib2, iclass 11, count 0 2006.162.08:10:06.03#ibcon#*mode == 0, iclass 11, count 0 2006.162.08:10:06.03#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.162.08:10:06.03#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.08:10:06.03#ibcon#*before write, iclass 11, count 0 2006.162.08:10:06.03#ibcon#enter sib2, iclass 11, count 0 2006.162.08:10:06.03#ibcon#flushed, iclass 11, count 0 2006.162.08:10:06.03#ibcon#about to write, iclass 11, count 0 2006.162.08:10:06.03#ibcon#wrote, iclass 11, count 0 2006.162.08:10:06.03#ibcon#about to read 3, iclass 11, count 0 2006.162.08:10:06.07#ibcon#read 3, iclass 11, count 0 2006.162.08:10:06.07#ibcon#about to read 4, iclass 11, count 0 2006.162.08:10:06.07#ibcon#read 4, iclass 11, count 0 2006.162.08:10:06.07#ibcon#about to read 5, iclass 11, count 0 2006.162.08:10:06.07#ibcon#read 5, iclass 11, count 0 2006.162.08:10:06.07#ibcon#about to read 6, iclass 11, count 0 2006.162.08:10:06.07#ibcon#read 6, iclass 11, count 0 2006.162.08:10:06.07#ibcon#end of sib2, iclass 11, count 0 2006.162.08:10:06.07#ibcon#*after write, iclass 11, count 0 2006.162.08:10:06.07#ibcon#*before return 0, iclass 11, count 0 2006.162.08:10:06.07#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:10:06.07#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:10:06.07#ibcon#about to clear, iclass 11 cls_cnt 0 2006.162.08:10:06.07#ibcon#cleared, iclass 11 cls_cnt 0 2006.162.08:10:06.07$vc4f8/vb=5,4 2006.162.08:10:06.07#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.162.08:10:06.07#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.162.08:10:06.07#ibcon#ireg 11 cls_cnt 2 2006.162.08:10:06.07#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:10:06.14#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:10:06.14#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:10:06.14#ibcon#enter wrdev, iclass 13, count 2 2006.162.08:10:06.14#ibcon#first serial, iclass 13, count 2 2006.162.08:10:06.14#ibcon#enter sib2, iclass 13, count 2 2006.162.08:10:06.14#ibcon#flushed, iclass 13, count 2 2006.162.08:10:06.14#ibcon#about to write, iclass 13, count 2 2006.162.08:10:06.14#ibcon#wrote, iclass 13, count 2 2006.162.08:10:06.14#ibcon#about to read 3, iclass 13, count 2 2006.162.08:10:06.15#ibcon#read 3, iclass 13, count 2 2006.162.08:10:06.15#ibcon#about to read 4, iclass 13, count 2 2006.162.08:10:06.15#ibcon#read 4, iclass 13, count 2 2006.162.08:10:06.15#ibcon#about to read 5, iclass 13, count 2 2006.162.08:10:06.15#ibcon#read 5, iclass 13, count 2 2006.162.08:10:06.15#ibcon#about to read 6, iclass 13, count 2 2006.162.08:10:06.15#ibcon#read 6, iclass 13, count 2 2006.162.08:10:06.15#ibcon#end of sib2, iclass 13, count 2 2006.162.08:10:06.15#ibcon#*mode == 0, iclass 13, count 2 2006.162.08:10:06.15#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.162.08:10:06.15#ibcon#[27=AT05-04\r\n] 2006.162.08:10:06.15#ibcon#*before write, iclass 13, count 2 2006.162.08:10:06.15#ibcon#enter sib2, iclass 13, count 2 2006.162.08:10:06.15#ibcon#flushed, iclass 13, count 2 2006.162.08:10:06.15#ibcon#about to write, iclass 13, count 2 2006.162.08:10:06.15#ibcon#wrote, iclass 13, count 2 2006.162.08:10:06.15#ibcon#about to read 3, iclass 13, count 2 2006.162.08:10:06.18#ibcon#read 3, iclass 13, count 2 2006.162.08:10:06.18#ibcon#about to read 4, iclass 13, count 2 2006.162.08:10:06.18#ibcon#read 4, iclass 13, count 2 2006.162.08:10:06.18#ibcon#about to read 5, iclass 13, count 2 2006.162.08:10:06.18#ibcon#read 5, iclass 13, count 2 2006.162.08:10:06.18#ibcon#about to read 6, iclass 13, count 2 2006.162.08:10:06.18#ibcon#read 6, iclass 13, count 2 2006.162.08:10:06.18#ibcon#end of sib2, iclass 13, count 2 2006.162.08:10:06.18#ibcon#*after write, iclass 13, count 2 2006.162.08:10:06.18#ibcon#*before return 0, iclass 13, count 2 2006.162.08:10:06.18#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:10:06.18#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:10:06.18#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.162.08:10:06.18#ibcon#ireg 7 cls_cnt 0 2006.162.08:10:06.18#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:10:06.30#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:10:06.30#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:10:06.30#ibcon#enter wrdev, iclass 13, count 0 2006.162.08:10:06.30#ibcon#first serial, iclass 13, count 0 2006.162.08:10:06.30#ibcon#enter sib2, iclass 13, count 0 2006.162.08:10:06.30#ibcon#flushed, iclass 13, count 0 2006.162.08:10:06.30#ibcon#about to write, iclass 13, count 0 2006.162.08:10:06.30#ibcon#wrote, iclass 13, count 0 2006.162.08:10:06.30#ibcon#about to read 3, iclass 13, count 0 2006.162.08:10:06.32#ibcon#read 3, iclass 13, count 0 2006.162.08:10:06.32#ibcon#about to read 4, iclass 13, count 0 2006.162.08:10:06.32#ibcon#read 4, iclass 13, count 0 2006.162.08:10:06.32#ibcon#about to read 5, iclass 13, count 0 2006.162.08:10:06.32#ibcon#read 5, iclass 13, count 0 2006.162.08:10:06.32#ibcon#about to read 6, iclass 13, count 0 2006.162.08:10:06.32#ibcon#read 6, iclass 13, count 0 2006.162.08:10:06.32#ibcon#end of sib2, iclass 13, count 0 2006.162.08:10:06.32#ibcon#*mode == 0, iclass 13, count 0 2006.162.08:10:06.32#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.162.08:10:06.32#ibcon#[27=USB\r\n] 2006.162.08:10:06.32#ibcon#*before write, iclass 13, count 0 2006.162.08:10:06.32#ibcon#enter sib2, iclass 13, count 0 2006.162.08:10:06.32#ibcon#flushed, iclass 13, count 0 2006.162.08:10:06.32#ibcon#about to write, iclass 13, count 0 2006.162.08:10:06.32#ibcon#wrote, iclass 13, count 0 2006.162.08:10:06.32#ibcon#about to read 3, iclass 13, count 0 2006.162.08:10:06.35#ibcon#read 3, iclass 13, count 0 2006.162.08:10:06.35#ibcon#about to read 4, iclass 13, count 0 2006.162.08:10:06.35#ibcon#read 4, iclass 13, count 0 2006.162.08:10:06.35#ibcon#about to read 5, iclass 13, count 0 2006.162.08:10:06.35#ibcon#read 5, iclass 13, count 0 2006.162.08:10:06.35#ibcon#about to read 6, iclass 13, count 0 2006.162.08:10:06.35#ibcon#read 6, iclass 13, count 0 2006.162.08:10:06.35#ibcon#end of sib2, iclass 13, count 0 2006.162.08:10:06.35#ibcon#*after write, iclass 13, count 0 2006.162.08:10:06.35#ibcon#*before return 0, iclass 13, count 0 2006.162.08:10:06.35#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:10:06.35#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:10:06.35#ibcon#about to clear, iclass 13 cls_cnt 0 2006.162.08:10:06.35#ibcon#cleared, iclass 13 cls_cnt 0 2006.162.08:10:06.35$vc4f8/vblo=6,752.99 2006.162.08:10:06.35#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.162.08:10:06.35#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.162.08:10:06.35#ibcon#ireg 17 cls_cnt 0 2006.162.08:10:06.35#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:10:06.35#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:10:06.35#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:10:06.35#ibcon#enter wrdev, iclass 15, count 0 2006.162.08:10:06.35#ibcon#first serial, iclass 15, count 0 2006.162.08:10:06.35#ibcon#enter sib2, iclass 15, count 0 2006.162.08:10:06.35#ibcon#flushed, iclass 15, count 0 2006.162.08:10:06.35#ibcon#about to write, iclass 15, count 0 2006.162.08:10:06.35#ibcon#wrote, iclass 15, count 0 2006.162.08:10:06.35#ibcon#about to read 3, iclass 15, count 0 2006.162.08:10:06.37#ibcon#read 3, iclass 15, count 0 2006.162.08:10:06.37#ibcon#about to read 4, iclass 15, count 0 2006.162.08:10:06.37#ibcon#read 4, iclass 15, count 0 2006.162.08:10:06.37#ibcon#about to read 5, iclass 15, count 0 2006.162.08:10:06.37#ibcon#read 5, iclass 15, count 0 2006.162.08:10:06.37#ibcon#about to read 6, iclass 15, count 0 2006.162.08:10:06.37#ibcon#read 6, iclass 15, count 0 2006.162.08:10:06.37#ibcon#end of sib2, iclass 15, count 0 2006.162.08:10:06.37#ibcon#*mode == 0, iclass 15, count 0 2006.162.08:10:06.37#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.162.08:10:06.37#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.08:10:06.37#ibcon#*before write, iclass 15, count 0 2006.162.08:10:06.37#ibcon#enter sib2, iclass 15, count 0 2006.162.08:10:06.37#ibcon#flushed, iclass 15, count 0 2006.162.08:10:06.37#ibcon#about to write, iclass 15, count 0 2006.162.08:10:06.37#ibcon#wrote, iclass 15, count 0 2006.162.08:10:06.37#ibcon#about to read 3, iclass 15, count 0 2006.162.08:10:06.41#ibcon#read 3, iclass 15, count 0 2006.162.08:10:06.41#ibcon#about to read 4, iclass 15, count 0 2006.162.08:10:06.41#ibcon#read 4, iclass 15, count 0 2006.162.08:10:06.41#ibcon#about to read 5, iclass 15, count 0 2006.162.08:10:06.41#ibcon#read 5, iclass 15, count 0 2006.162.08:10:06.41#ibcon#about to read 6, iclass 15, count 0 2006.162.08:10:06.41#ibcon#read 6, iclass 15, count 0 2006.162.08:10:06.41#ibcon#end of sib2, iclass 15, count 0 2006.162.08:10:06.41#ibcon#*after write, iclass 15, count 0 2006.162.08:10:06.41#ibcon#*before return 0, iclass 15, count 0 2006.162.08:10:06.41#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:10:06.41#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:10:06.41#ibcon#about to clear, iclass 15 cls_cnt 0 2006.162.08:10:06.41#ibcon#cleared, iclass 15 cls_cnt 0 2006.162.08:10:06.41$vc4f8/vb=6,4 2006.162.08:10:06.41#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.162.08:10:06.41#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.162.08:10:06.41#ibcon#ireg 11 cls_cnt 2 2006.162.08:10:06.41#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:10:06.47#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:10:06.47#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:10:06.47#ibcon#enter wrdev, iclass 17, count 2 2006.162.08:10:06.47#ibcon#first serial, iclass 17, count 2 2006.162.08:10:06.47#ibcon#enter sib2, iclass 17, count 2 2006.162.08:10:06.47#ibcon#flushed, iclass 17, count 2 2006.162.08:10:06.47#ibcon#about to write, iclass 17, count 2 2006.162.08:10:06.47#ibcon#wrote, iclass 17, count 2 2006.162.08:10:06.47#ibcon#about to read 3, iclass 17, count 2 2006.162.08:10:06.49#ibcon#read 3, iclass 17, count 2 2006.162.08:10:06.49#ibcon#about to read 4, iclass 17, count 2 2006.162.08:10:06.49#ibcon#read 4, iclass 17, count 2 2006.162.08:10:06.49#ibcon#about to read 5, iclass 17, count 2 2006.162.08:10:06.49#ibcon#read 5, iclass 17, count 2 2006.162.08:10:06.49#ibcon#about to read 6, iclass 17, count 2 2006.162.08:10:06.49#ibcon#read 6, iclass 17, count 2 2006.162.08:10:06.49#ibcon#end of sib2, iclass 17, count 2 2006.162.08:10:06.49#ibcon#*mode == 0, iclass 17, count 2 2006.162.08:10:06.49#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.162.08:10:06.49#ibcon#[27=AT06-04\r\n] 2006.162.08:10:06.49#ibcon#*before write, iclass 17, count 2 2006.162.08:10:06.49#ibcon#enter sib2, iclass 17, count 2 2006.162.08:10:06.49#ibcon#flushed, iclass 17, count 2 2006.162.08:10:06.49#ibcon#about to write, iclass 17, count 2 2006.162.08:10:06.49#ibcon#wrote, iclass 17, count 2 2006.162.08:10:06.49#ibcon#about to read 3, iclass 17, count 2 2006.162.08:10:06.52#ibcon#read 3, iclass 17, count 2 2006.162.08:10:06.52#ibcon#about to read 4, iclass 17, count 2 2006.162.08:10:06.52#ibcon#read 4, iclass 17, count 2 2006.162.08:10:06.52#ibcon#about to read 5, iclass 17, count 2 2006.162.08:10:06.52#ibcon#read 5, iclass 17, count 2 2006.162.08:10:06.52#ibcon#about to read 6, iclass 17, count 2 2006.162.08:10:06.52#ibcon#read 6, iclass 17, count 2 2006.162.08:10:06.52#ibcon#end of sib2, iclass 17, count 2 2006.162.08:10:06.52#ibcon#*after write, iclass 17, count 2 2006.162.08:10:06.52#ibcon#*before return 0, iclass 17, count 2 2006.162.08:10:06.52#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:10:06.52#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:10:06.52#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.162.08:10:06.52#ibcon#ireg 7 cls_cnt 0 2006.162.08:10:06.52#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:10:06.64#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:10:06.64#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:10:06.64#ibcon#enter wrdev, iclass 17, count 0 2006.162.08:10:06.64#ibcon#first serial, iclass 17, count 0 2006.162.08:10:06.64#ibcon#enter sib2, iclass 17, count 0 2006.162.08:10:06.64#ibcon#flushed, iclass 17, count 0 2006.162.08:10:06.64#ibcon#about to write, iclass 17, count 0 2006.162.08:10:06.64#ibcon#wrote, iclass 17, count 0 2006.162.08:10:06.64#ibcon#about to read 3, iclass 17, count 0 2006.162.08:10:06.66#ibcon#read 3, iclass 17, count 0 2006.162.08:10:06.66#ibcon#about to read 4, iclass 17, count 0 2006.162.08:10:06.66#ibcon#read 4, iclass 17, count 0 2006.162.08:10:06.66#ibcon#about to read 5, iclass 17, count 0 2006.162.08:10:06.66#ibcon#read 5, iclass 17, count 0 2006.162.08:10:06.66#ibcon#about to read 6, iclass 17, count 0 2006.162.08:10:06.66#ibcon#read 6, iclass 17, count 0 2006.162.08:10:06.66#ibcon#end of sib2, iclass 17, count 0 2006.162.08:10:06.66#ibcon#*mode == 0, iclass 17, count 0 2006.162.08:10:06.66#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.162.08:10:06.66#ibcon#[27=USB\r\n] 2006.162.08:10:06.66#ibcon#*before write, iclass 17, count 0 2006.162.08:10:06.66#ibcon#enter sib2, iclass 17, count 0 2006.162.08:10:06.66#ibcon#flushed, iclass 17, count 0 2006.162.08:10:06.66#ibcon#about to write, iclass 17, count 0 2006.162.08:10:06.66#ibcon#wrote, iclass 17, count 0 2006.162.08:10:06.66#ibcon#about to read 3, iclass 17, count 0 2006.162.08:10:06.69#ibcon#read 3, iclass 17, count 0 2006.162.08:10:06.69#ibcon#about to read 4, iclass 17, count 0 2006.162.08:10:06.69#ibcon#read 4, iclass 17, count 0 2006.162.08:10:06.69#ibcon#about to read 5, iclass 17, count 0 2006.162.08:10:06.69#ibcon#read 5, iclass 17, count 0 2006.162.08:10:06.69#ibcon#about to read 6, iclass 17, count 0 2006.162.08:10:06.69#ibcon#read 6, iclass 17, count 0 2006.162.08:10:06.69#ibcon#end of sib2, iclass 17, count 0 2006.162.08:10:06.69#ibcon#*after write, iclass 17, count 0 2006.162.08:10:06.69#ibcon#*before return 0, iclass 17, count 0 2006.162.08:10:06.69#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:10:06.69#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:10:06.69#ibcon#about to clear, iclass 17 cls_cnt 0 2006.162.08:10:06.69#ibcon#cleared, iclass 17 cls_cnt 0 2006.162.08:10:06.69$vc4f8/vabw=wide 2006.162.08:10:06.69#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.162.08:10:06.69#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.162.08:10:06.69#ibcon#ireg 8 cls_cnt 0 2006.162.08:10:06.69#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:10:06.69#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:10:06.69#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:10:06.69#ibcon#enter wrdev, iclass 19, count 0 2006.162.08:10:06.69#ibcon#first serial, iclass 19, count 0 2006.162.08:10:06.69#ibcon#enter sib2, iclass 19, count 0 2006.162.08:10:06.69#ibcon#flushed, iclass 19, count 0 2006.162.08:10:06.69#ibcon#about to write, iclass 19, count 0 2006.162.08:10:06.69#ibcon#wrote, iclass 19, count 0 2006.162.08:10:06.69#ibcon#about to read 3, iclass 19, count 0 2006.162.08:10:06.71#ibcon#read 3, iclass 19, count 0 2006.162.08:10:06.71#ibcon#about to read 4, iclass 19, count 0 2006.162.08:10:06.71#ibcon#read 4, iclass 19, count 0 2006.162.08:10:06.71#ibcon#about to read 5, iclass 19, count 0 2006.162.08:10:06.71#ibcon#read 5, iclass 19, count 0 2006.162.08:10:06.71#ibcon#about to read 6, iclass 19, count 0 2006.162.08:10:06.71#ibcon#read 6, iclass 19, count 0 2006.162.08:10:06.71#ibcon#end of sib2, iclass 19, count 0 2006.162.08:10:06.71#ibcon#*mode == 0, iclass 19, count 0 2006.162.08:10:06.71#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.162.08:10:06.71#ibcon#[25=BW32\r\n] 2006.162.08:10:06.71#ibcon#*before write, iclass 19, count 0 2006.162.08:10:06.71#ibcon#enter sib2, iclass 19, count 0 2006.162.08:10:06.71#ibcon#flushed, iclass 19, count 0 2006.162.08:10:06.71#ibcon#about to write, iclass 19, count 0 2006.162.08:10:06.71#ibcon#wrote, iclass 19, count 0 2006.162.08:10:06.71#ibcon#about to read 3, iclass 19, count 0 2006.162.08:10:06.74#ibcon#read 3, iclass 19, count 0 2006.162.08:10:06.74#ibcon#about to read 4, iclass 19, count 0 2006.162.08:10:06.74#ibcon#read 4, iclass 19, count 0 2006.162.08:10:06.74#ibcon#about to read 5, iclass 19, count 0 2006.162.08:10:06.74#ibcon#read 5, iclass 19, count 0 2006.162.08:10:06.74#ibcon#about to read 6, iclass 19, count 0 2006.162.08:10:06.74#ibcon#read 6, iclass 19, count 0 2006.162.08:10:06.74#ibcon#end of sib2, iclass 19, count 0 2006.162.08:10:06.74#ibcon#*after write, iclass 19, count 0 2006.162.08:10:06.74#ibcon#*before return 0, iclass 19, count 0 2006.162.08:10:06.74#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:10:06.74#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:10:06.74#ibcon#about to clear, iclass 19 cls_cnt 0 2006.162.08:10:06.74#ibcon#cleared, iclass 19 cls_cnt 0 2006.162.08:10:06.74$vc4f8/vbbw=wide 2006.162.08:10:06.74#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.162.08:10:06.74#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.162.08:10:06.74#ibcon#ireg 8 cls_cnt 0 2006.162.08:10:06.74#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:10:06.82#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:10:06.82#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:10:06.82#ibcon#enter wrdev, iclass 21, count 0 2006.162.08:10:06.82#ibcon#first serial, iclass 21, count 0 2006.162.08:10:06.82#ibcon#enter sib2, iclass 21, count 0 2006.162.08:10:06.82#ibcon#flushed, iclass 21, count 0 2006.162.08:10:06.82#ibcon#about to write, iclass 21, count 0 2006.162.08:10:06.82#ibcon#wrote, iclass 21, count 0 2006.162.08:10:06.82#ibcon#about to read 3, iclass 21, count 0 2006.162.08:10:06.83#ibcon#read 3, iclass 21, count 0 2006.162.08:10:06.83#ibcon#about to read 4, iclass 21, count 0 2006.162.08:10:06.83#ibcon#read 4, iclass 21, count 0 2006.162.08:10:06.83#ibcon#about to read 5, iclass 21, count 0 2006.162.08:10:06.83#ibcon#read 5, iclass 21, count 0 2006.162.08:10:06.83#ibcon#about to read 6, iclass 21, count 0 2006.162.08:10:06.83#ibcon#read 6, iclass 21, count 0 2006.162.08:10:06.83#ibcon#end of sib2, iclass 21, count 0 2006.162.08:10:06.83#ibcon#*mode == 0, iclass 21, count 0 2006.162.08:10:06.83#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.162.08:10:06.83#ibcon#[27=BW32\r\n] 2006.162.08:10:06.83#ibcon#*before write, iclass 21, count 0 2006.162.08:10:06.83#ibcon#enter sib2, iclass 21, count 0 2006.162.08:10:06.83#ibcon#flushed, iclass 21, count 0 2006.162.08:10:06.83#ibcon#about to write, iclass 21, count 0 2006.162.08:10:06.83#ibcon#wrote, iclass 21, count 0 2006.162.08:10:06.83#ibcon#about to read 3, iclass 21, count 0 2006.162.08:10:06.86#ibcon#read 3, iclass 21, count 0 2006.162.08:10:06.86#ibcon#about to read 4, iclass 21, count 0 2006.162.08:10:06.86#ibcon#read 4, iclass 21, count 0 2006.162.08:10:06.86#ibcon#about to read 5, iclass 21, count 0 2006.162.08:10:06.86#ibcon#read 5, iclass 21, count 0 2006.162.08:10:06.86#ibcon#about to read 6, iclass 21, count 0 2006.162.08:10:06.86#ibcon#read 6, iclass 21, count 0 2006.162.08:10:06.86#ibcon#end of sib2, iclass 21, count 0 2006.162.08:10:06.86#ibcon#*after write, iclass 21, count 0 2006.162.08:10:06.86#ibcon#*before return 0, iclass 21, count 0 2006.162.08:10:06.86#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:10:06.86#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:10:06.86#ibcon#about to clear, iclass 21 cls_cnt 0 2006.162.08:10:06.86#ibcon#cleared, iclass 21 cls_cnt 0 2006.162.08:10:06.86$4f8m12a/ifd4f 2006.162.08:10:06.86$ifd4f/lo= 2006.162.08:10:06.86$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.08:10:06.86$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.08:10:06.86$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.08:10:06.86$ifd4f/patch= 2006.162.08:10:06.86$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.08:10:06.86$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.08:10:06.86$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.08:10:06.86$4f8m12a/"form=m,16.000,1:2 2006.162.08:10:06.86$4f8m12a/"tpicd 2006.162.08:10:06.86$4f8m12a/echo=off 2006.162.08:10:06.86$4f8m12a/xlog=off 2006.162.08:10:06.86:!2006.162.08:10:50 2006.162.08:10:25.14#trakl#Source acquired 2006.162.08:10:27.14#flagr#flagr/antenna,acquired 2006.162.08:10:50.00:preob 2006.162.08:10:50.14/onsource/TRACKING 2006.162.08:10:50.14:!2006.162.08:11:00 2006.162.08:11:00.00:data_valid=on 2006.162.08:11:00.00:midob 2006.162.08:11:00.14/onsource/TRACKING 2006.162.08:11:00.14/wx/17.83,1007.0,100 2006.162.08:11:00.20/cable/+6.5352E-03 2006.162.08:11:01.29/va/01,08,usb,yes,34,36 2006.162.08:11:01.29/va/02,07,usb,yes,35,36 2006.162.08:11:01.29/va/03,06,usb,yes,37,37 2006.162.08:11:01.29/va/04,07,usb,yes,36,38 2006.162.08:11:01.29/va/05,07,usb,yes,38,40 2006.162.08:11:01.29/va/06,06,usb,yes,37,37 2006.162.08:11:01.29/va/07,06,usb,yes,37,37 2006.162.08:11:01.29/va/08,07,usb,yes,35,35 2006.162.08:11:01.52/valo/01,532.99,yes,locked 2006.162.08:11:01.52/valo/02,572.99,yes,locked 2006.162.08:11:01.52/valo/03,672.99,yes,locked 2006.162.08:11:01.52/valo/04,832.99,yes,locked 2006.162.08:11:01.52/valo/05,652.99,yes,locked 2006.162.08:11:01.52/valo/06,772.99,yes,locked 2006.162.08:11:01.52/valo/07,832.99,yes,locked 2006.162.08:11:01.52/valo/08,852.99,yes,locked 2006.162.08:11:02.61/vb/01,04,usb,yes,29,27 2006.162.08:11:02.61/vb/02,04,usb,yes,30,32 2006.162.08:11:02.61/vb/03,04,usb,yes,27,30 2006.162.08:11:02.61/vb/04,04,usb,yes,28,28 2006.162.08:11:02.61/vb/05,04,usb,yes,26,30 2006.162.08:11:02.61/vb/06,04,usb,yes,27,30 2006.162.08:11:02.61/vb/07,04,usb,yes,29,29 2006.162.08:11:02.61/vb/08,04,usb,yes,27,30 2006.162.08:11:02.84/vblo/01,632.99,yes,locked 2006.162.08:11:02.84/vblo/02,640.99,yes,locked 2006.162.08:11:02.84/vblo/03,656.99,yes,locked 2006.162.08:11:02.84/vblo/04,712.99,yes,locked 2006.162.08:11:02.84/vblo/05,744.99,yes,locked 2006.162.08:11:02.84/vblo/06,752.99,yes,locked 2006.162.08:11:02.84/vblo/07,734.99,yes,locked 2006.162.08:11:02.84/vblo/08,744.99,yes,locked 2006.162.08:11:02.99/vabw/8 2006.162.08:11:03.14/vbbw/8 2006.162.08:11:03.23/xfe/off,on,14.7 2006.162.08:11:03.61/ifatt/23,28,28,28 2006.162.08:11:04.08/fmout-gps/S +4.49E-07 2006.162.08:11:04.16:!2006.162.08:13:10 2006.162.08:13:10.00:data_valid=off 2006.162.08:13:10.00:postob 2006.162.08:13:10.16/cable/+6.5356E-03 2006.162.08:13:10.16/wx/17.86,1007.1,100 2006.162.08:13:11.08/fmout-gps/S +4.50E-07 2006.162.08:13:11.08:scan_name=162-0814,k06162,60 2006.162.08:13:11.09:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.162.08:13:12.14#flagr#flagr/antenna,new-source 2006.162.08:13:12.14:checkk5 2006.162.08:13:12.57/chk_autoobs//k5ts1/ autoobs is running! 2006.162.08:13:13.00/chk_autoobs//k5ts2/ autoobs is running! 2006.162.08:13:13.39/chk_autoobs//k5ts3/ autoobs is running! 2006.162.08:13:13.80/chk_autoobs//k5ts4/ autoobs is running! 2006.162.08:13:14.20/chk_obsdata//k5ts1/T1620811??a.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.162.08:13:14.64/chk_obsdata//k5ts2/T1620811??b.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.162.08:13:15.02/chk_obsdata//k5ts3/T1620811??c.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.162.08:13:15.43/chk_obsdata//k5ts4/T1620811??d.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.162.08:13:16.42/k5log//k5ts1_log_newline 2006.162.08:13:17.49/k5log//k5ts2_log_newline 2006.162.08:13:18.31/k5log//k5ts3_log_newline 2006.162.08:13:19.76/k5log//k5ts4_log_newline 2006.162.08:13:19.79/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.08:13:19.79:4f8m12a=2 2006.162.08:13:19.79$4f8m12a/echo=on 2006.162.08:13:19.79$4f8m12a/pcalon 2006.162.08:13:19.79$pcalon/"no phase cal control is implemented here 2006.162.08:13:19.79$4f8m12a/"tpicd=stop 2006.162.08:13:19.79$4f8m12a/vc4f8 2006.162.08:13:19.79$vc4f8/valo=1,532.99 2006.162.08:13:19.79#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.162.08:13:19.79#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.162.08:13:19.79#ibcon#ireg 17 cls_cnt 0 2006.162.08:13:19.79#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:13:19.79#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:13:19.79#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:13:19.79#ibcon#enter wrdev, iclass 28, count 0 2006.162.08:13:19.79#ibcon#first serial, iclass 28, count 0 2006.162.08:13:19.79#ibcon#enter sib2, iclass 28, count 0 2006.162.08:13:19.79#ibcon#flushed, iclass 28, count 0 2006.162.08:13:19.79#ibcon#about to write, iclass 28, count 0 2006.162.08:13:19.79#ibcon#wrote, iclass 28, count 0 2006.162.08:13:19.79#ibcon#about to read 3, iclass 28, count 0 2006.162.08:13:19.83#ibcon#read 3, iclass 28, count 0 2006.162.08:13:19.83#ibcon#about to read 4, iclass 28, count 0 2006.162.08:13:19.83#ibcon#read 4, iclass 28, count 0 2006.162.08:13:19.83#ibcon#about to read 5, iclass 28, count 0 2006.162.08:13:19.83#ibcon#read 5, iclass 28, count 0 2006.162.08:13:19.83#ibcon#about to read 6, iclass 28, count 0 2006.162.08:13:19.83#ibcon#read 6, iclass 28, count 0 2006.162.08:13:19.83#ibcon#end of sib2, iclass 28, count 0 2006.162.08:13:19.83#ibcon#*mode == 0, iclass 28, count 0 2006.162.08:13:19.83#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.162.08:13:19.84#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.08:13:19.84#ibcon#*before write, iclass 28, count 0 2006.162.08:13:19.84#ibcon#enter sib2, iclass 28, count 0 2006.162.08:13:19.84#ibcon#flushed, iclass 28, count 0 2006.162.08:13:19.84#ibcon#about to write, iclass 28, count 0 2006.162.08:13:19.84#ibcon#wrote, iclass 28, count 0 2006.162.08:13:19.84#ibcon#about to read 3, iclass 28, count 0 2006.162.08:13:19.88#ibcon#read 3, iclass 28, count 0 2006.162.08:13:19.88#ibcon#about to read 4, iclass 28, count 0 2006.162.08:13:19.88#ibcon#read 4, iclass 28, count 0 2006.162.08:13:19.88#ibcon#about to read 5, iclass 28, count 0 2006.162.08:13:19.88#ibcon#read 5, iclass 28, count 0 2006.162.08:13:19.88#ibcon#about to read 6, iclass 28, count 0 2006.162.08:13:19.88#ibcon#read 6, iclass 28, count 0 2006.162.08:13:19.88#ibcon#end of sib2, iclass 28, count 0 2006.162.08:13:19.88#ibcon#*after write, iclass 28, count 0 2006.162.08:13:19.88#ibcon#*before return 0, iclass 28, count 0 2006.162.08:13:19.88#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:13:19.88#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:13:19.88#ibcon#about to clear, iclass 28 cls_cnt 0 2006.162.08:13:19.88#ibcon#cleared, iclass 28 cls_cnt 0 2006.162.08:13:19.88$vc4f8/va=1,8 2006.162.08:13:19.88#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.162.08:13:19.88#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.162.08:13:19.88#ibcon#ireg 11 cls_cnt 2 2006.162.08:13:19.88#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:13:19.88#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:13:19.88#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:13:19.88#ibcon#enter wrdev, iclass 30, count 2 2006.162.08:13:19.88#ibcon#first serial, iclass 30, count 2 2006.162.08:13:19.88#ibcon#enter sib2, iclass 30, count 2 2006.162.08:13:19.88#ibcon#flushed, iclass 30, count 2 2006.162.08:13:19.88#ibcon#about to write, iclass 30, count 2 2006.162.08:13:19.88#ibcon#wrote, iclass 30, count 2 2006.162.08:13:19.88#ibcon#about to read 3, iclass 30, count 2 2006.162.08:13:19.90#ibcon#read 3, iclass 30, count 2 2006.162.08:13:19.90#ibcon#about to read 4, iclass 30, count 2 2006.162.08:13:19.90#ibcon#read 4, iclass 30, count 2 2006.162.08:13:19.90#ibcon#about to read 5, iclass 30, count 2 2006.162.08:13:19.90#ibcon#read 5, iclass 30, count 2 2006.162.08:13:19.90#ibcon#about to read 6, iclass 30, count 2 2006.162.08:13:19.90#ibcon#read 6, iclass 30, count 2 2006.162.08:13:19.90#ibcon#end of sib2, iclass 30, count 2 2006.162.08:13:19.90#ibcon#*mode == 0, iclass 30, count 2 2006.162.08:13:19.90#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.162.08:13:19.90#ibcon#[25=AT01-08\r\n] 2006.162.08:13:19.90#ibcon#*before write, iclass 30, count 2 2006.162.08:13:19.90#ibcon#enter sib2, iclass 30, count 2 2006.162.08:13:19.90#ibcon#flushed, iclass 30, count 2 2006.162.08:13:19.90#ibcon#about to write, iclass 30, count 2 2006.162.08:13:19.90#ibcon#wrote, iclass 30, count 2 2006.162.08:13:19.90#ibcon#about to read 3, iclass 30, count 2 2006.162.08:13:19.93#ibcon#read 3, iclass 30, count 2 2006.162.08:13:19.93#ibcon#about to read 4, iclass 30, count 2 2006.162.08:13:19.93#ibcon#read 4, iclass 30, count 2 2006.162.08:13:19.93#ibcon#about to read 5, iclass 30, count 2 2006.162.08:13:19.93#ibcon#read 5, iclass 30, count 2 2006.162.08:13:19.93#ibcon#about to read 6, iclass 30, count 2 2006.162.08:13:19.93#ibcon#read 6, iclass 30, count 2 2006.162.08:13:19.93#ibcon#end of sib2, iclass 30, count 2 2006.162.08:13:19.93#ibcon#*after write, iclass 30, count 2 2006.162.08:13:19.93#ibcon#*before return 0, iclass 30, count 2 2006.162.08:13:19.93#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:13:19.93#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:13:19.93#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.162.08:13:19.93#ibcon#ireg 7 cls_cnt 0 2006.162.08:13:19.93#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:13:20.05#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:13:20.05#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:13:20.05#ibcon#enter wrdev, iclass 30, count 0 2006.162.08:13:20.05#ibcon#first serial, iclass 30, count 0 2006.162.08:13:20.05#ibcon#enter sib2, iclass 30, count 0 2006.162.08:13:20.05#ibcon#flushed, iclass 30, count 0 2006.162.08:13:20.05#ibcon#about to write, iclass 30, count 0 2006.162.08:13:20.05#ibcon#wrote, iclass 30, count 0 2006.162.08:13:20.05#ibcon#about to read 3, iclass 30, count 0 2006.162.08:13:20.07#ibcon#read 3, iclass 30, count 0 2006.162.08:13:20.07#ibcon#about to read 4, iclass 30, count 0 2006.162.08:13:20.07#ibcon#read 4, iclass 30, count 0 2006.162.08:13:20.07#ibcon#about to read 5, iclass 30, count 0 2006.162.08:13:20.07#ibcon#read 5, iclass 30, count 0 2006.162.08:13:20.07#ibcon#about to read 6, iclass 30, count 0 2006.162.08:13:20.07#ibcon#read 6, iclass 30, count 0 2006.162.08:13:20.07#ibcon#end of sib2, iclass 30, count 0 2006.162.08:13:20.07#ibcon#*mode == 0, iclass 30, count 0 2006.162.08:13:20.07#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.162.08:13:20.07#ibcon#[25=USB\r\n] 2006.162.08:13:20.07#ibcon#*before write, iclass 30, count 0 2006.162.08:13:20.07#ibcon#enter sib2, iclass 30, count 0 2006.162.08:13:20.07#ibcon#flushed, iclass 30, count 0 2006.162.08:13:20.07#ibcon#about to write, iclass 30, count 0 2006.162.08:13:20.07#ibcon#wrote, iclass 30, count 0 2006.162.08:13:20.07#ibcon#about to read 3, iclass 30, count 0 2006.162.08:13:20.10#ibcon#read 3, iclass 30, count 0 2006.162.08:13:20.10#ibcon#about to read 4, iclass 30, count 0 2006.162.08:13:20.10#ibcon#read 4, iclass 30, count 0 2006.162.08:13:20.10#ibcon#about to read 5, iclass 30, count 0 2006.162.08:13:20.10#ibcon#read 5, iclass 30, count 0 2006.162.08:13:20.10#ibcon#about to read 6, iclass 30, count 0 2006.162.08:13:20.10#ibcon#read 6, iclass 30, count 0 2006.162.08:13:20.10#ibcon#end of sib2, iclass 30, count 0 2006.162.08:13:20.10#ibcon#*after write, iclass 30, count 0 2006.162.08:13:20.10#ibcon#*before return 0, iclass 30, count 0 2006.162.08:13:20.10#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:13:20.10#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:13:20.10#ibcon#about to clear, iclass 30 cls_cnt 0 2006.162.08:13:20.10#ibcon#cleared, iclass 30 cls_cnt 0 2006.162.08:13:20.10$vc4f8/valo=2,572.99 2006.162.08:13:20.10#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.162.08:13:20.10#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.162.08:13:20.10#ibcon#ireg 17 cls_cnt 0 2006.162.08:13:20.10#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:13:20.10#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:13:20.10#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:13:20.10#ibcon#enter wrdev, iclass 32, count 0 2006.162.08:13:20.10#ibcon#first serial, iclass 32, count 0 2006.162.08:13:20.10#ibcon#enter sib2, iclass 32, count 0 2006.162.08:13:20.10#ibcon#flushed, iclass 32, count 0 2006.162.08:13:20.10#ibcon#about to write, iclass 32, count 0 2006.162.08:13:20.10#ibcon#wrote, iclass 32, count 0 2006.162.08:13:20.10#ibcon#about to read 3, iclass 32, count 0 2006.162.08:13:20.12#ibcon#read 3, iclass 32, count 0 2006.162.08:13:20.12#ibcon#about to read 4, iclass 32, count 0 2006.162.08:13:20.12#ibcon#read 4, iclass 32, count 0 2006.162.08:13:20.12#ibcon#about to read 5, iclass 32, count 0 2006.162.08:13:20.12#ibcon#read 5, iclass 32, count 0 2006.162.08:13:20.12#ibcon#about to read 6, iclass 32, count 0 2006.162.08:13:20.12#ibcon#read 6, iclass 32, count 0 2006.162.08:13:20.12#ibcon#end of sib2, iclass 32, count 0 2006.162.08:13:20.12#ibcon#*mode == 0, iclass 32, count 0 2006.162.08:13:20.12#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.162.08:13:20.12#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.08:13:20.12#ibcon#*before write, iclass 32, count 0 2006.162.08:13:20.12#ibcon#enter sib2, iclass 32, count 0 2006.162.08:13:20.12#ibcon#flushed, iclass 32, count 0 2006.162.08:13:20.12#ibcon#about to write, iclass 32, count 0 2006.162.08:13:20.12#ibcon#wrote, iclass 32, count 0 2006.162.08:13:20.12#ibcon#about to read 3, iclass 32, count 0 2006.162.08:13:20.16#ibcon#read 3, iclass 32, count 0 2006.162.08:13:20.16#ibcon#about to read 4, iclass 32, count 0 2006.162.08:13:20.16#ibcon#read 4, iclass 32, count 0 2006.162.08:13:20.16#ibcon#about to read 5, iclass 32, count 0 2006.162.08:13:20.16#ibcon#read 5, iclass 32, count 0 2006.162.08:13:20.16#ibcon#about to read 6, iclass 32, count 0 2006.162.08:13:20.16#ibcon#read 6, iclass 32, count 0 2006.162.08:13:20.16#ibcon#end of sib2, iclass 32, count 0 2006.162.08:13:20.16#ibcon#*after write, iclass 32, count 0 2006.162.08:13:20.16#ibcon#*before return 0, iclass 32, count 0 2006.162.08:13:20.16#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:13:20.16#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:13:20.16#ibcon#about to clear, iclass 32 cls_cnt 0 2006.162.08:13:20.16#ibcon#cleared, iclass 32 cls_cnt 0 2006.162.08:13:20.16$vc4f8/va=2,7 2006.162.08:13:20.16#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.162.08:13:20.16#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.162.08:13:20.16#ibcon#ireg 11 cls_cnt 2 2006.162.08:13:20.16#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:13:20.22#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:13:20.22#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:13:20.22#ibcon#enter wrdev, iclass 34, count 2 2006.162.08:13:20.22#ibcon#first serial, iclass 34, count 2 2006.162.08:13:20.22#ibcon#enter sib2, iclass 34, count 2 2006.162.08:13:20.22#ibcon#flushed, iclass 34, count 2 2006.162.08:13:20.22#ibcon#about to write, iclass 34, count 2 2006.162.08:13:20.22#ibcon#wrote, iclass 34, count 2 2006.162.08:13:20.22#ibcon#about to read 3, iclass 34, count 2 2006.162.08:13:20.24#ibcon#read 3, iclass 34, count 2 2006.162.08:13:20.24#ibcon#about to read 4, iclass 34, count 2 2006.162.08:13:20.24#ibcon#read 4, iclass 34, count 2 2006.162.08:13:20.24#ibcon#about to read 5, iclass 34, count 2 2006.162.08:13:20.24#ibcon#read 5, iclass 34, count 2 2006.162.08:13:20.24#ibcon#about to read 6, iclass 34, count 2 2006.162.08:13:20.24#ibcon#read 6, iclass 34, count 2 2006.162.08:13:20.24#ibcon#end of sib2, iclass 34, count 2 2006.162.08:13:20.24#ibcon#*mode == 0, iclass 34, count 2 2006.162.08:13:20.24#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.162.08:13:20.24#ibcon#[25=AT02-07\r\n] 2006.162.08:13:20.24#ibcon#*before write, iclass 34, count 2 2006.162.08:13:20.24#ibcon#enter sib2, iclass 34, count 2 2006.162.08:13:20.24#ibcon#flushed, iclass 34, count 2 2006.162.08:13:20.24#ibcon#about to write, iclass 34, count 2 2006.162.08:13:20.24#ibcon#wrote, iclass 34, count 2 2006.162.08:13:20.24#ibcon#about to read 3, iclass 34, count 2 2006.162.08:13:20.27#ibcon#read 3, iclass 34, count 2 2006.162.08:13:20.27#ibcon#about to read 4, iclass 34, count 2 2006.162.08:13:20.27#ibcon#read 4, iclass 34, count 2 2006.162.08:13:20.27#ibcon#about to read 5, iclass 34, count 2 2006.162.08:13:20.27#ibcon#read 5, iclass 34, count 2 2006.162.08:13:20.27#ibcon#about to read 6, iclass 34, count 2 2006.162.08:13:20.27#ibcon#read 6, iclass 34, count 2 2006.162.08:13:20.27#ibcon#end of sib2, iclass 34, count 2 2006.162.08:13:20.27#ibcon#*after write, iclass 34, count 2 2006.162.08:13:20.27#ibcon#*before return 0, iclass 34, count 2 2006.162.08:13:20.27#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:13:20.27#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:13:20.27#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.162.08:13:20.27#ibcon#ireg 7 cls_cnt 0 2006.162.08:13:20.27#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:13:20.39#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:13:20.39#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:13:20.39#ibcon#enter wrdev, iclass 34, count 0 2006.162.08:13:20.39#ibcon#first serial, iclass 34, count 0 2006.162.08:13:20.39#ibcon#enter sib2, iclass 34, count 0 2006.162.08:13:20.39#ibcon#flushed, iclass 34, count 0 2006.162.08:13:20.39#ibcon#about to write, iclass 34, count 0 2006.162.08:13:20.39#ibcon#wrote, iclass 34, count 0 2006.162.08:13:20.39#ibcon#about to read 3, iclass 34, count 0 2006.162.08:13:20.41#ibcon#read 3, iclass 34, count 0 2006.162.08:13:20.41#ibcon#about to read 4, iclass 34, count 0 2006.162.08:13:20.41#ibcon#read 4, iclass 34, count 0 2006.162.08:13:20.41#ibcon#about to read 5, iclass 34, count 0 2006.162.08:13:20.41#ibcon#read 5, iclass 34, count 0 2006.162.08:13:20.41#ibcon#about to read 6, iclass 34, count 0 2006.162.08:13:20.41#ibcon#read 6, iclass 34, count 0 2006.162.08:13:20.41#ibcon#end of sib2, iclass 34, count 0 2006.162.08:13:20.41#ibcon#*mode == 0, iclass 34, count 0 2006.162.08:13:20.41#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.162.08:13:20.41#ibcon#[25=USB\r\n] 2006.162.08:13:20.41#ibcon#*before write, iclass 34, count 0 2006.162.08:13:20.41#ibcon#enter sib2, iclass 34, count 0 2006.162.08:13:20.41#ibcon#flushed, iclass 34, count 0 2006.162.08:13:20.41#ibcon#about to write, iclass 34, count 0 2006.162.08:13:20.41#ibcon#wrote, iclass 34, count 0 2006.162.08:13:20.41#ibcon#about to read 3, iclass 34, count 0 2006.162.08:13:20.44#ibcon#read 3, iclass 34, count 0 2006.162.08:13:20.44#ibcon#about to read 4, iclass 34, count 0 2006.162.08:13:20.44#ibcon#read 4, iclass 34, count 0 2006.162.08:13:20.44#ibcon#about to read 5, iclass 34, count 0 2006.162.08:13:20.44#ibcon#read 5, iclass 34, count 0 2006.162.08:13:20.44#ibcon#about to read 6, iclass 34, count 0 2006.162.08:13:20.44#ibcon#read 6, iclass 34, count 0 2006.162.08:13:20.44#ibcon#end of sib2, iclass 34, count 0 2006.162.08:13:20.44#ibcon#*after write, iclass 34, count 0 2006.162.08:13:20.44#ibcon#*before return 0, iclass 34, count 0 2006.162.08:13:20.44#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:13:20.44#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:13:20.44#ibcon#about to clear, iclass 34 cls_cnt 0 2006.162.08:13:20.44#ibcon#cleared, iclass 34 cls_cnt 0 2006.162.08:13:20.44$vc4f8/valo=3,672.99 2006.162.08:13:20.44#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.162.08:13:20.44#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.162.08:13:20.44#ibcon#ireg 17 cls_cnt 0 2006.162.08:13:20.44#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:13:20.44#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:13:20.44#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:13:20.44#ibcon#enter wrdev, iclass 36, count 0 2006.162.08:13:20.44#ibcon#first serial, iclass 36, count 0 2006.162.08:13:20.44#ibcon#enter sib2, iclass 36, count 0 2006.162.08:13:20.44#ibcon#flushed, iclass 36, count 0 2006.162.08:13:20.44#ibcon#about to write, iclass 36, count 0 2006.162.08:13:20.44#ibcon#wrote, iclass 36, count 0 2006.162.08:13:20.44#ibcon#about to read 3, iclass 36, count 0 2006.162.08:13:20.46#ibcon#read 3, iclass 36, count 0 2006.162.08:13:20.46#ibcon#about to read 4, iclass 36, count 0 2006.162.08:13:20.46#ibcon#read 4, iclass 36, count 0 2006.162.08:13:20.46#ibcon#about to read 5, iclass 36, count 0 2006.162.08:13:20.46#ibcon#read 5, iclass 36, count 0 2006.162.08:13:20.46#ibcon#about to read 6, iclass 36, count 0 2006.162.08:13:20.46#ibcon#read 6, iclass 36, count 0 2006.162.08:13:20.46#ibcon#end of sib2, iclass 36, count 0 2006.162.08:13:20.46#ibcon#*mode == 0, iclass 36, count 0 2006.162.08:13:20.46#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.162.08:13:20.46#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.08:13:20.46#ibcon#*before write, iclass 36, count 0 2006.162.08:13:20.46#ibcon#enter sib2, iclass 36, count 0 2006.162.08:13:20.46#ibcon#flushed, iclass 36, count 0 2006.162.08:13:20.46#ibcon#about to write, iclass 36, count 0 2006.162.08:13:20.46#ibcon#wrote, iclass 36, count 0 2006.162.08:13:20.46#ibcon#about to read 3, iclass 36, count 0 2006.162.08:13:20.50#ibcon#read 3, iclass 36, count 0 2006.162.08:13:20.50#ibcon#about to read 4, iclass 36, count 0 2006.162.08:13:20.50#ibcon#read 4, iclass 36, count 0 2006.162.08:13:20.50#ibcon#about to read 5, iclass 36, count 0 2006.162.08:13:20.50#ibcon#read 5, iclass 36, count 0 2006.162.08:13:20.50#ibcon#about to read 6, iclass 36, count 0 2006.162.08:13:20.50#ibcon#read 6, iclass 36, count 0 2006.162.08:13:20.50#ibcon#end of sib2, iclass 36, count 0 2006.162.08:13:20.50#ibcon#*after write, iclass 36, count 0 2006.162.08:13:20.50#ibcon#*before return 0, iclass 36, count 0 2006.162.08:13:20.50#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:13:20.50#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:13:20.50#ibcon#about to clear, iclass 36 cls_cnt 0 2006.162.08:13:20.50#ibcon#cleared, iclass 36 cls_cnt 0 2006.162.08:13:20.50$vc4f8/va=3,6 2006.162.08:13:20.50#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.162.08:13:20.50#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.162.08:13:20.50#ibcon#ireg 11 cls_cnt 2 2006.162.08:13:20.50#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.162.08:13:20.57#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.162.08:13:20.57#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.162.08:13:20.57#ibcon#enter wrdev, iclass 38, count 2 2006.162.08:13:20.57#ibcon#first serial, iclass 38, count 2 2006.162.08:13:20.57#ibcon#enter sib2, iclass 38, count 2 2006.162.08:13:20.57#ibcon#flushed, iclass 38, count 2 2006.162.08:13:20.57#ibcon#about to write, iclass 38, count 2 2006.162.08:13:20.57#ibcon#wrote, iclass 38, count 2 2006.162.08:13:20.57#ibcon#about to read 3, iclass 38, count 2 2006.162.08:13:20.58#ibcon#read 3, iclass 38, count 2 2006.162.08:13:20.58#ibcon#about to read 4, iclass 38, count 2 2006.162.08:13:20.58#ibcon#read 4, iclass 38, count 2 2006.162.08:13:20.58#ibcon#about to read 5, iclass 38, count 2 2006.162.08:13:20.58#ibcon#read 5, iclass 38, count 2 2006.162.08:13:20.58#ibcon#about to read 6, iclass 38, count 2 2006.162.08:13:20.58#ibcon#read 6, iclass 38, count 2 2006.162.08:13:20.58#ibcon#end of sib2, iclass 38, count 2 2006.162.08:13:20.58#ibcon#*mode == 0, iclass 38, count 2 2006.162.08:13:20.58#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.162.08:13:20.58#ibcon#[25=AT03-06\r\n] 2006.162.08:13:20.58#ibcon#*before write, iclass 38, count 2 2006.162.08:13:20.58#ibcon#enter sib2, iclass 38, count 2 2006.162.08:13:20.58#ibcon#flushed, iclass 38, count 2 2006.162.08:13:20.58#ibcon#about to write, iclass 38, count 2 2006.162.08:13:20.58#ibcon#wrote, iclass 38, count 2 2006.162.08:13:20.58#ibcon#about to read 3, iclass 38, count 2 2006.162.08:13:20.61#ibcon#read 3, iclass 38, count 2 2006.162.08:13:20.61#ibcon#about to read 4, iclass 38, count 2 2006.162.08:13:20.61#ibcon#read 4, iclass 38, count 2 2006.162.08:13:20.61#ibcon#about to read 5, iclass 38, count 2 2006.162.08:13:20.61#ibcon#read 5, iclass 38, count 2 2006.162.08:13:20.61#ibcon#about to read 6, iclass 38, count 2 2006.162.08:13:20.61#ibcon#read 6, iclass 38, count 2 2006.162.08:13:20.61#ibcon#end of sib2, iclass 38, count 2 2006.162.08:13:20.61#ibcon#*after write, iclass 38, count 2 2006.162.08:13:20.61#ibcon#*before return 0, iclass 38, count 2 2006.162.08:13:20.61#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.162.08:13:20.61#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.162.08:13:20.61#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.162.08:13:20.61#ibcon#ireg 7 cls_cnt 0 2006.162.08:13:20.61#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.162.08:13:20.73#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.162.08:13:20.73#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.162.08:13:20.73#ibcon#enter wrdev, iclass 38, count 0 2006.162.08:13:20.73#ibcon#first serial, iclass 38, count 0 2006.162.08:13:20.73#ibcon#enter sib2, iclass 38, count 0 2006.162.08:13:20.73#ibcon#flushed, iclass 38, count 0 2006.162.08:13:20.73#ibcon#about to write, iclass 38, count 0 2006.162.08:13:20.73#ibcon#wrote, iclass 38, count 0 2006.162.08:13:20.73#ibcon#about to read 3, iclass 38, count 0 2006.162.08:13:20.75#ibcon#read 3, iclass 38, count 0 2006.162.08:13:20.75#ibcon#about to read 4, iclass 38, count 0 2006.162.08:13:20.75#ibcon#read 4, iclass 38, count 0 2006.162.08:13:20.75#ibcon#about to read 5, iclass 38, count 0 2006.162.08:13:20.75#ibcon#read 5, iclass 38, count 0 2006.162.08:13:20.75#ibcon#about to read 6, iclass 38, count 0 2006.162.08:13:20.75#ibcon#read 6, iclass 38, count 0 2006.162.08:13:20.75#ibcon#end of sib2, iclass 38, count 0 2006.162.08:13:20.75#ibcon#*mode == 0, iclass 38, count 0 2006.162.08:13:20.75#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.162.08:13:20.75#ibcon#[25=USB\r\n] 2006.162.08:13:20.75#ibcon#*before write, iclass 38, count 0 2006.162.08:13:20.75#ibcon#enter sib2, iclass 38, count 0 2006.162.08:13:20.75#ibcon#flushed, iclass 38, count 0 2006.162.08:13:20.75#ibcon#about to write, iclass 38, count 0 2006.162.08:13:20.75#ibcon#wrote, iclass 38, count 0 2006.162.08:13:20.75#ibcon#about to read 3, iclass 38, count 0 2006.162.08:13:20.78#ibcon#read 3, iclass 38, count 0 2006.162.08:13:20.78#ibcon#about to read 4, iclass 38, count 0 2006.162.08:13:20.78#ibcon#read 4, iclass 38, count 0 2006.162.08:13:20.78#ibcon#about to read 5, iclass 38, count 0 2006.162.08:13:20.78#ibcon#read 5, iclass 38, count 0 2006.162.08:13:20.78#ibcon#about to read 6, iclass 38, count 0 2006.162.08:13:20.78#ibcon#read 6, iclass 38, count 0 2006.162.08:13:20.78#ibcon#end of sib2, iclass 38, count 0 2006.162.08:13:20.78#ibcon#*after write, iclass 38, count 0 2006.162.08:13:20.78#ibcon#*before return 0, iclass 38, count 0 2006.162.08:13:20.78#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.162.08:13:20.78#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.162.08:13:20.78#ibcon#about to clear, iclass 38 cls_cnt 0 2006.162.08:13:20.78#ibcon#cleared, iclass 38 cls_cnt 0 2006.162.08:13:20.78$vc4f8/valo=4,832.99 2006.162.08:13:20.78#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.162.08:13:20.78#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.162.08:13:20.78#ibcon#ireg 17 cls_cnt 0 2006.162.08:13:20.78#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:13:20.78#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:13:20.78#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:13:20.78#ibcon#enter wrdev, iclass 40, count 0 2006.162.08:13:20.78#ibcon#first serial, iclass 40, count 0 2006.162.08:13:20.78#ibcon#enter sib2, iclass 40, count 0 2006.162.08:13:20.78#ibcon#flushed, iclass 40, count 0 2006.162.08:13:20.78#ibcon#about to write, iclass 40, count 0 2006.162.08:13:20.78#ibcon#wrote, iclass 40, count 0 2006.162.08:13:20.78#ibcon#about to read 3, iclass 40, count 0 2006.162.08:13:20.80#ibcon#read 3, iclass 40, count 0 2006.162.08:13:20.80#ibcon#about to read 4, iclass 40, count 0 2006.162.08:13:20.80#ibcon#read 4, iclass 40, count 0 2006.162.08:13:20.80#ibcon#about to read 5, iclass 40, count 0 2006.162.08:13:20.80#ibcon#read 5, iclass 40, count 0 2006.162.08:13:20.80#ibcon#about to read 6, iclass 40, count 0 2006.162.08:13:20.80#ibcon#read 6, iclass 40, count 0 2006.162.08:13:20.80#ibcon#end of sib2, iclass 40, count 0 2006.162.08:13:20.80#ibcon#*mode == 0, iclass 40, count 0 2006.162.08:13:20.80#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.162.08:13:20.80#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.08:13:20.80#ibcon#*before write, iclass 40, count 0 2006.162.08:13:20.80#ibcon#enter sib2, iclass 40, count 0 2006.162.08:13:20.80#ibcon#flushed, iclass 40, count 0 2006.162.08:13:20.80#ibcon#about to write, iclass 40, count 0 2006.162.08:13:20.80#ibcon#wrote, iclass 40, count 0 2006.162.08:13:20.80#ibcon#about to read 3, iclass 40, count 0 2006.162.08:13:20.84#ibcon#read 3, iclass 40, count 0 2006.162.08:13:20.84#ibcon#about to read 4, iclass 40, count 0 2006.162.08:13:20.84#ibcon#read 4, iclass 40, count 0 2006.162.08:13:20.84#ibcon#about to read 5, iclass 40, count 0 2006.162.08:13:20.84#ibcon#read 5, iclass 40, count 0 2006.162.08:13:20.84#ibcon#about to read 6, iclass 40, count 0 2006.162.08:13:20.84#ibcon#read 6, iclass 40, count 0 2006.162.08:13:20.84#ibcon#end of sib2, iclass 40, count 0 2006.162.08:13:20.84#ibcon#*after write, iclass 40, count 0 2006.162.08:13:20.84#ibcon#*before return 0, iclass 40, count 0 2006.162.08:13:20.84#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:13:20.84#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:13:20.84#ibcon#about to clear, iclass 40 cls_cnt 0 2006.162.08:13:20.84#ibcon#cleared, iclass 40 cls_cnt 0 2006.162.08:13:20.84$vc4f8/va=4,7 2006.162.08:13:20.84#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.162.08:13:20.84#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.162.08:13:20.84#ibcon#ireg 11 cls_cnt 2 2006.162.08:13:20.84#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:13:20.90#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:13:20.90#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:13:20.90#ibcon#enter wrdev, iclass 4, count 2 2006.162.08:13:20.90#ibcon#first serial, iclass 4, count 2 2006.162.08:13:20.90#ibcon#enter sib2, iclass 4, count 2 2006.162.08:13:20.90#ibcon#flushed, iclass 4, count 2 2006.162.08:13:20.90#ibcon#about to write, iclass 4, count 2 2006.162.08:13:20.90#ibcon#wrote, iclass 4, count 2 2006.162.08:13:20.90#ibcon#about to read 3, iclass 4, count 2 2006.162.08:13:20.92#ibcon#read 3, iclass 4, count 2 2006.162.08:13:20.92#ibcon#about to read 4, iclass 4, count 2 2006.162.08:13:20.92#ibcon#read 4, iclass 4, count 2 2006.162.08:13:20.92#ibcon#about to read 5, iclass 4, count 2 2006.162.08:13:20.92#ibcon#read 5, iclass 4, count 2 2006.162.08:13:20.92#ibcon#about to read 6, iclass 4, count 2 2006.162.08:13:20.92#ibcon#read 6, iclass 4, count 2 2006.162.08:13:20.92#ibcon#end of sib2, iclass 4, count 2 2006.162.08:13:20.92#ibcon#*mode == 0, iclass 4, count 2 2006.162.08:13:20.92#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.162.08:13:20.92#ibcon#[25=AT04-07\r\n] 2006.162.08:13:20.92#ibcon#*before write, iclass 4, count 2 2006.162.08:13:20.92#ibcon#enter sib2, iclass 4, count 2 2006.162.08:13:20.92#ibcon#flushed, iclass 4, count 2 2006.162.08:13:20.92#ibcon#about to write, iclass 4, count 2 2006.162.08:13:20.92#ibcon#wrote, iclass 4, count 2 2006.162.08:13:20.92#ibcon#about to read 3, iclass 4, count 2 2006.162.08:13:20.95#ibcon#read 3, iclass 4, count 2 2006.162.08:13:20.95#ibcon#about to read 4, iclass 4, count 2 2006.162.08:13:20.95#ibcon#read 4, iclass 4, count 2 2006.162.08:13:20.95#ibcon#about to read 5, iclass 4, count 2 2006.162.08:13:20.95#ibcon#read 5, iclass 4, count 2 2006.162.08:13:20.95#ibcon#about to read 6, iclass 4, count 2 2006.162.08:13:20.95#ibcon#read 6, iclass 4, count 2 2006.162.08:13:20.95#ibcon#end of sib2, iclass 4, count 2 2006.162.08:13:20.95#ibcon#*after write, iclass 4, count 2 2006.162.08:13:20.95#ibcon#*before return 0, iclass 4, count 2 2006.162.08:13:20.95#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:13:20.95#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:13:20.95#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.162.08:13:20.95#ibcon#ireg 7 cls_cnt 0 2006.162.08:13:20.95#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:13:21.07#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:13:21.07#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:13:21.07#ibcon#enter wrdev, iclass 4, count 0 2006.162.08:13:21.07#ibcon#first serial, iclass 4, count 0 2006.162.08:13:21.07#ibcon#enter sib2, iclass 4, count 0 2006.162.08:13:21.07#ibcon#flushed, iclass 4, count 0 2006.162.08:13:21.07#ibcon#about to write, iclass 4, count 0 2006.162.08:13:21.07#ibcon#wrote, iclass 4, count 0 2006.162.08:13:21.07#ibcon#about to read 3, iclass 4, count 0 2006.162.08:13:21.11#ibcon#read 3, iclass 4, count 0 2006.162.08:13:21.11#ibcon#about to read 4, iclass 4, count 0 2006.162.08:13:21.11#ibcon#read 4, iclass 4, count 0 2006.162.08:13:21.11#ibcon#about to read 5, iclass 4, count 0 2006.162.08:13:21.11#ibcon#read 5, iclass 4, count 0 2006.162.08:13:21.11#ibcon#about to read 6, iclass 4, count 0 2006.162.08:13:21.11#ibcon#read 6, iclass 4, count 0 2006.162.08:13:21.11#ibcon#end of sib2, iclass 4, count 0 2006.162.08:13:21.11#ibcon#*mode == 0, iclass 4, count 0 2006.162.08:13:21.11#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.162.08:13:21.11#ibcon#[25=USB\r\n] 2006.162.08:13:21.11#ibcon#*before write, iclass 4, count 0 2006.162.08:13:21.11#ibcon#enter sib2, iclass 4, count 0 2006.162.08:13:21.11#ibcon#flushed, iclass 4, count 0 2006.162.08:13:21.11#ibcon#about to write, iclass 4, count 0 2006.162.08:13:21.11#ibcon#wrote, iclass 4, count 0 2006.162.08:13:21.11#ibcon#about to read 3, iclass 4, count 0 2006.162.08:13:21.14#ibcon#read 3, iclass 4, count 0 2006.162.08:13:21.14#ibcon#about to read 4, iclass 4, count 0 2006.162.08:13:21.14#ibcon#read 4, iclass 4, count 0 2006.162.08:13:21.14#ibcon#about to read 5, iclass 4, count 0 2006.162.08:13:21.14#ibcon#read 5, iclass 4, count 0 2006.162.08:13:21.14#ibcon#about to read 6, iclass 4, count 0 2006.162.08:13:21.14#ibcon#read 6, iclass 4, count 0 2006.162.08:13:21.14#ibcon#end of sib2, iclass 4, count 0 2006.162.08:13:21.14#ibcon#*after write, iclass 4, count 0 2006.162.08:13:21.14#ibcon#*before return 0, iclass 4, count 0 2006.162.08:13:21.14#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:13:21.14#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:13:21.14#ibcon#about to clear, iclass 4 cls_cnt 0 2006.162.08:13:21.14#ibcon#cleared, iclass 4 cls_cnt 0 2006.162.08:13:21.14$vc4f8/valo=5,652.99 2006.162.08:13:21.14#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.162.08:13:21.14#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.162.08:13:21.14#ibcon#ireg 17 cls_cnt 0 2006.162.08:13:21.14#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:13:21.14#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:13:21.14#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:13:21.14#ibcon#enter wrdev, iclass 6, count 0 2006.162.08:13:21.14#ibcon#first serial, iclass 6, count 0 2006.162.08:13:21.14#ibcon#enter sib2, iclass 6, count 0 2006.162.08:13:21.14#ibcon#flushed, iclass 6, count 0 2006.162.08:13:21.14#ibcon#about to write, iclass 6, count 0 2006.162.08:13:21.14#ibcon#wrote, iclass 6, count 0 2006.162.08:13:21.14#ibcon#about to read 3, iclass 6, count 0 2006.162.08:13:21.16#ibcon#read 3, iclass 6, count 0 2006.162.08:13:21.16#ibcon#about to read 4, iclass 6, count 0 2006.162.08:13:21.16#ibcon#read 4, iclass 6, count 0 2006.162.08:13:21.16#ibcon#about to read 5, iclass 6, count 0 2006.162.08:13:21.16#ibcon#read 5, iclass 6, count 0 2006.162.08:13:21.16#ibcon#about to read 6, iclass 6, count 0 2006.162.08:13:21.16#ibcon#read 6, iclass 6, count 0 2006.162.08:13:21.16#ibcon#end of sib2, iclass 6, count 0 2006.162.08:13:21.16#ibcon#*mode == 0, iclass 6, count 0 2006.162.08:13:21.16#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.162.08:13:21.16#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.08:13:21.16#ibcon#*before write, iclass 6, count 0 2006.162.08:13:21.16#ibcon#enter sib2, iclass 6, count 0 2006.162.08:13:21.16#ibcon#flushed, iclass 6, count 0 2006.162.08:13:21.16#ibcon#about to write, iclass 6, count 0 2006.162.08:13:21.16#ibcon#wrote, iclass 6, count 0 2006.162.08:13:21.16#ibcon#about to read 3, iclass 6, count 0 2006.162.08:13:21.20#ibcon#read 3, iclass 6, count 0 2006.162.08:13:21.20#ibcon#about to read 4, iclass 6, count 0 2006.162.08:13:21.20#ibcon#read 4, iclass 6, count 0 2006.162.08:13:21.20#ibcon#about to read 5, iclass 6, count 0 2006.162.08:13:21.20#ibcon#read 5, iclass 6, count 0 2006.162.08:13:21.20#ibcon#about to read 6, iclass 6, count 0 2006.162.08:13:21.20#ibcon#read 6, iclass 6, count 0 2006.162.08:13:21.20#ibcon#end of sib2, iclass 6, count 0 2006.162.08:13:21.20#ibcon#*after write, iclass 6, count 0 2006.162.08:13:21.20#ibcon#*before return 0, iclass 6, count 0 2006.162.08:13:21.20#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:13:21.20#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:13:21.20#ibcon#about to clear, iclass 6 cls_cnt 0 2006.162.08:13:21.20#ibcon#cleared, iclass 6 cls_cnt 0 2006.162.08:13:21.20$vc4f8/va=5,7 2006.162.08:13:21.20#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.162.08:13:21.20#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.162.08:13:21.20#ibcon#ireg 11 cls_cnt 2 2006.162.08:13:21.20#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:13:21.26#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:13:21.26#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:13:21.26#ibcon#enter wrdev, iclass 10, count 2 2006.162.08:13:21.26#ibcon#first serial, iclass 10, count 2 2006.162.08:13:21.26#ibcon#enter sib2, iclass 10, count 2 2006.162.08:13:21.26#ibcon#flushed, iclass 10, count 2 2006.162.08:13:21.26#ibcon#about to write, iclass 10, count 2 2006.162.08:13:21.26#ibcon#wrote, iclass 10, count 2 2006.162.08:13:21.26#ibcon#about to read 3, iclass 10, count 2 2006.162.08:13:21.29#ibcon#read 3, iclass 10, count 2 2006.162.08:13:21.29#ibcon#about to read 4, iclass 10, count 2 2006.162.08:13:21.29#ibcon#read 4, iclass 10, count 2 2006.162.08:13:21.29#ibcon#about to read 5, iclass 10, count 2 2006.162.08:13:21.29#ibcon#read 5, iclass 10, count 2 2006.162.08:13:21.29#ibcon#about to read 6, iclass 10, count 2 2006.162.08:13:21.29#ibcon#read 6, iclass 10, count 2 2006.162.08:13:21.29#ibcon#end of sib2, iclass 10, count 2 2006.162.08:13:21.29#ibcon#*mode == 0, iclass 10, count 2 2006.162.08:13:21.29#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.162.08:13:21.29#ibcon#[25=AT05-07\r\n] 2006.162.08:13:21.29#ibcon#*before write, iclass 10, count 2 2006.162.08:13:21.29#ibcon#enter sib2, iclass 10, count 2 2006.162.08:13:21.29#ibcon#flushed, iclass 10, count 2 2006.162.08:13:21.29#ibcon#about to write, iclass 10, count 2 2006.162.08:13:21.29#ibcon#wrote, iclass 10, count 2 2006.162.08:13:21.29#ibcon#about to read 3, iclass 10, count 2 2006.162.08:13:21.32#ibcon#read 3, iclass 10, count 2 2006.162.08:13:21.32#ibcon#about to read 4, iclass 10, count 2 2006.162.08:13:21.32#ibcon#read 4, iclass 10, count 2 2006.162.08:13:21.32#ibcon#about to read 5, iclass 10, count 2 2006.162.08:13:21.32#ibcon#read 5, iclass 10, count 2 2006.162.08:13:21.32#ibcon#about to read 6, iclass 10, count 2 2006.162.08:13:21.32#ibcon#read 6, iclass 10, count 2 2006.162.08:13:21.32#ibcon#end of sib2, iclass 10, count 2 2006.162.08:13:21.32#ibcon#*after write, iclass 10, count 2 2006.162.08:13:21.32#ibcon#*before return 0, iclass 10, count 2 2006.162.08:13:21.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:13:21.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:13:21.32#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.162.08:13:21.32#ibcon#ireg 7 cls_cnt 0 2006.162.08:13:21.32#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:13:21.44#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:13:21.44#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:13:21.44#ibcon#enter wrdev, iclass 10, count 0 2006.162.08:13:21.44#ibcon#first serial, iclass 10, count 0 2006.162.08:13:21.44#ibcon#enter sib2, iclass 10, count 0 2006.162.08:13:21.44#ibcon#flushed, iclass 10, count 0 2006.162.08:13:21.44#ibcon#about to write, iclass 10, count 0 2006.162.08:13:21.44#ibcon#wrote, iclass 10, count 0 2006.162.08:13:21.44#ibcon#about to read 3, iclass 10, count 0 2006.162.08:13:21.46#ibcon#read 3, iclass 10, count 0 2006.162.08:13:21.46#ibcon#about to read 4, iclass 10, count 0 2006.162.08:13:21.46#ibcon#read 4, iclass 10, count 0 2006.162.08:13:21.46#ibcon#about to read 5, iclass 10, count 0 2006.162.08:13:21.46#ibcon#read 5, iclass 10, count 0 2006.162.08:13:21.46#ibcon#about to read 6, iclass 10, count 0 2006.162.08:13:21.46#ibcon#read 6, iclass 10, count 0 2006.162.08:13:21.46#ibcon#end of sib2, iclass 10, count 0 2006.162.08:13:21.46#ibcon#*mode == 0, iclass 10, count 0 2006.162.08:13:21.46#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.162.08:13:21.46#ibcon#[25=USB\r\n] 2006.162.08:13:21.46#ibcon#*before write, iclass 10, count 0 2006.162.08:13:21.46#ibcon#enter sib2, iclass 10, count 0 2006.162.08:13:21.46#ibcon#flushed, iclass 10, count 0 2006.162.08:13:21.46#ibcon#about to write, iclass 10, count 0 2006.162.08:13:21.46#ibcon#wrote, iclass 10, count 0 2006.162.08:13:21.46#ibcon#about to read 3, iclass 10, count 0 2006.162.08:13:21.49#ibcon#read 3, iclass 10, count 0 2006.162.08:13:21.49#ibcon#about to read 4, iclass 10, count 0 2006.162.08:13:21.49#ibcon#read 4, iclass 10, count 0 2006.162.08:13:21.49#ibcon#about to read 5, iclass 10, count 0 2006.162.08:13:21.49#ibcon#read 5, iclass 10, count 0 2006.162.08:13:21.49#ibcon#about to read 6, iclass 10, count 0 2006.162.08:13:21.49#ibcon#read 6, iclass 10, count 0 2006.162.08:13:21.49#ibcon#end of sib2, iclass 10, count 0 2006.162.08:13:21.49#ibcon#*after write, iclass 10, count 0 2006.162.08:13:21.49#ibcon#*before return 0, iclass 10, count 0 2006.162.08:13:21.49#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:13:21.49#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:13:21.49#ibcon#about to clear, iclass 10 cls_cnt 0 2006.162.08:13:21.49#ibcon#cleared, iclass 10 cls_cnt 0 2006.162.08:13:21.49$vc4f8/valo=6,772.99 2006.162.08:13:21.49#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.162.08:13:21.49#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.162.08:13:21.49#ibcon#ireg 17 cls_cnt 0 2006.162.08:13:21.49#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:13:21.49#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:13:21.49#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:13:21.49#ibcon#enter wrdev, iclass 12, count 0 2006.162.08:13:21.49#ibcon#first serial, iclass 12, count 0 2006.162.08:13:21.49#ibcon#enter sib2, iclass 12, count 0 2006.162.08:13:21.49#ibcon#flushed, iclass 12, count 0 2006.162.08:13:21.49#ibcon#about to write, iclass 12, count 0 2006.162.08:13:21.49#ibcon#wrote, iclass 12, count 0 2006.162.08:13:21.49#ibcon#about to read 3, iclass 12, count 0 2006.162.08:13:21.51#ibcon#read 3, iclass 12, count 0 2006.162.08:13:21.51#ibcon#about to read 4, iclass 12, count 0 2006.162.08:13:21.51#ibcon#read 4, iclass 12, count 0 2006.162.08:13:21.51#ibcon#about to read 5, iclass 12, count 0 2006.162.08:13:21.51#ibcon#read 5, iclass 12, count 0 2006.162.08:13:21.51#ibcon#about to read 6, iclass 12, count 0 2006.162.08:13:21.51#ibcon#read 6, iclass 12, count 0 2006.162.08:13:21.51#ibcon#end of sib2, iclass 12, count 0 2006.162.08:13:21.51#ibcon#*mode == 0, iclass 12, count 0 2006.162.08:13:21.51#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.162.08:13:21.51#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.08:13:21.51#ibcon#*before write, iclass 12, count 0 2006.162.08:13:21.51#ibcon#enter sib2, iclass 12, count 0 2006.162.08:13:21.51#ibcon#flushed, iclass 12, count 0 2006.162.08:13:21.51#ibcon#about to write, iclass 12, count 0 2006.162.08:13:21.51#ibcon#wrote, iclass 12, count 0 2006.162.08:13:21.51#ibcon#about to read 3, iclass 12, count 0 2006.162.08:13:21.55#ibcon#read 3, iclass 12, count 0 2006.162.08:13:21.55#ibcon#about to read 4, iclass 12, count 0 2006.162.08:13:21.55#ibcon#read 4, iclass 12, count 0 2006.162.08:13:21.55#ibcon#about to read 5, iclass 12, count 0 2006.162.08:13:21.55#ibcon#read 5, iclass 12, count 0 2006.162.08:13:21.55#ibcon#about to read 6, iclass 12, count 0 2006.162.08:13:21.55#ibcon#read 6, iclass 12, count 0 2006.162.08:13:21.55#ibcon#end of sib2, iclass 12, count 0 2006.162.08:13:21.55#ibcon#*after write, iclass 12, count 0 2006.162.08:13:21.55#ibcon#*before return 0, iclass 12, count 0 2006.162.08:13:21.55#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:13:21.55#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:13:21.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.162.08:13:21.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.162.08:13:21.55$vc4f8/va=6,6 2006.162.08:13:21.55#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.162.08:13:21.55#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.162.08:13:21.55#ibcon#ireg 11 cls_cnt 2 2006.162.08:13:21.55#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.162.08:13:21.61#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.162.08:13:21.61#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.162.08:13:21.61#ibcon#enter wrdev, iclass 14, count 2 2006.162.08:13:21.61#ibcon#first serial, iclass 14, count 2 2006.162.08:13:21.61#ibcon#enter sib2, iclass 14, count 2 2006.162.08:13:21.61#ibcon#flushed, iclass 14, count 2 2006.162.08:13:21.61#ibcon#about to write, iclass 14, count 2 2006.162.08:13:21.61#ibcon#wrote, iclass 14, count 2 2006.162.08:13:21.61#ibcon#about to read 3, iclass 14, count 2 2006.162.08:13:21.63#ibcon#read 3, iclass 14, count 2 2006.162.08:13:21.63#ibcon#about to read 4, iclass 14, count 2 2006.162.08:13:21.63#ibcon#read 4, iclass 14, count 2 2006.162.08:13:21.63#ibcon#about to read 5, iclass 14, count 2 2006.162.08:13:21.63#ibcon#read 5, iclass 14, count 2 2006.162.08:13:21.63#ibcon#about to read 6, iclass 14, count 2 2006.162.08:13:21.63#ibcon#read 6, iclass 14, count 2 2006.162.08:13:21.63#ibcon#end of sib2, iclass 14, count 2 2006.162.08:13:21.63#ibcon#*mode == 0, iclass 14, count 2 2006.162.08:13:21.63#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.162.08:13:21.63#ibcon#[25=AT06-06\r\n] 2006.162.08:13:21.63#ibcon#*before write, iclass 14, count 2 2006.162.08:13:21.63#ibcon#enter sib2, iclass 14, count 2 2006.162.08:13:21.63#ibcon#flushed, iclass 14, count 2 2006.162.08:13:21.63#ibcon#about to write, iclass 14, count 2 2006.162.08:13:21.63#ibcon#wrote, iclass 14, count 2 2006.162.08:13:21.63#ibcon#about to read 3, iclass 14, count 2 2006.162.08:13:21.66#ibcon#read 3, iclass 14, count 2 2006.162.08:13:21.66#ibcon#about to read 4, iclass 14, count 2 2006.162.08:13:21.66#ibcon#read 4, iclass 14, count 2 2006.162.08:13:21.66#ibcon#about to read 5, iclass 14, count 2 2006.162.08:13:21.66#ibcon#read 5, iclass 14, count 2 2006.162.08:13:21.66#ibcon#about to read 6, iclass 14, count 2 2006.162.08:13:21.66#ibcon#read 6, iclass 14, count 2 2006.162.08:13:21.66#ibcon#end of sib2, iclass 14, count 2 2006.162.08:13:21.66#ibcon#*after write, iclass 14, count 2 2006.162.08:13:21.66#ibcon#*before return 0, iclass 14, count 2 2006.162.08:13:21.66#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.162.08:13:21.66#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.162.08:13:21.66#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.162.08:13:21.66#ibcon#ireg 7 cls_cnt 0 2006.162.08:13:21.66#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.162.08:13:21.78#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.162.08:13:21.78#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.162.08:13:21.78#ibcon#enter wrdev, iclass 14, count 0 2006.162.08:13:21.78#ibcon#first serial, iclass 14, count 0 2006.162.08:13:21.78#ibcon#enter sib2, iclass 14, count 0 2006.162.08:13:21.78#ibcon#flushed, iclass 14, count 0 2006.162.08:13:21.78#ibcon#about to write, iclass 14, count 0 2006.162.08:13:21.78#ibcon#wrote, iclass 14, count 0 2006.162.08:13:21.78#ibcon#about to read 3, iclass 14, count 0 2006.162.08:13:21.80#ibcon#read 3, iclass 14, count 0 2006.162.08:13:21.80#ibcon#about to read 4, iclass 14, count 0 2006.162.08:13:21.80#ibcon#read 4, iclass 14, count 0 2006.162.08:13:21.80#ibcon#about to read 5, iclass 14, count 0 2006.162.08:13:21.80#ibcon#read 5, iclass 14, count 0 2006.162.08:13:21.80#ibcon#about to read 6, iclass 14, count 0 2006.162.08:13:21.80#ibcon#read 6, iclass 14, count 0 2006.162.08:13:21.80#ibcon#end of sib2, iclass 14, count 0 2006.162.08:13:21.80#ibcon#*mode == 0, iclass 14, count 0 2006.162.08:13:21.80#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.08:13:21.80#ibcon#[25=USB\r\n] 2006.162.08:13:21.80#ibcon#*before write, iclass 14, count 0 2006.162.08:13:21.80#ibcon#enter sib2, iclass 14, count 0 2006.162.08:13:21.80#ibcon#flushed, iclass 14, count 0 2006.162.08:13:21.80#ibcon#about to write, iclass 14, count 0 2006.162.08:13:21.80#ibcon#wrote, iclass 14, count 0 2006.162.08:13:21.80#ibcon#about to read 3, iclass 14, count 0 2006.162.08:13:21.83#ibcon#read 3, iclass 14, count 0 2006.162.08:13:21.83#ibcon#about to read 4, iclass 14, count 0 2006.162.08:13:21.83#ibcon#read 4, iclass 14, count 0 2006.162.08:13:21.83#ibcon#about to read 5, iclass 14, count 0 2006.162.08:13:21.83#ibcon#read 5, iclass 14, count 0 2006.162.08:13:21.83#ibcon#about to read 6, iclass 14, count 0 2006.162.08:13:21.83#ibcon#read 6, iclass 14, count 0 2006.162.08:13:21.83#ibcon#end of sib2, iclass 14, count 0 2006.162.08:13:21.83#ibcon#*after write, iclass 14, count 0 2006.162.08:13:21.83#ibcon#*before return 0, iclass 14, count 0 2006.162.08:13:21.83#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.162.08:13:21.83#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.162.08:13:21.83#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.08:13:21.83#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.08:13:21.83$vc4f8/valo=7,832.99 2006.162.08:13:21.83#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.162.08:13:21.83#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.162.08:13:21.83#ibcon#ireg 17 cls_cnt 0 2006.162.08:13:21.83#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:13:21.83#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:13:21.83#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:13:21.83#ibcon#enter wrdev, iclass 16, count 0 2006.162.08:13:21.83#ibcon#first serial, iclass 16, count 0 2006.162.08:13:21.83#ibcon#enter sib2, iclass 16, count 0 2006.162.08:13:21.83#ibcon#flushed, iclass 16, count 0 2006.162.08:13:21.83#ibcon#about to write, iclass 16, count 0 2006.162.08:13:21.83#ibcon#wrote, iclass 16, count 0 2006.162.08:13:21.83#ibcon#about to read 3, iclass 16, count 0 2006.162.08:13:21.85#ibcon#read 3, iclass 16, count 0 2006.162.08:13:21.85#ibcon#about to read 4, iclass 16, count 0 2006.162.08:13:21.85#ibcon#read 4, iclass 16, count 0 2006.162.08:13:21.85#ibcon#about to read 5, iclass 16, count 0 2006.162.08:13:21.85#ibcon#read 5, iclass 16, count 0 2006.162.08:13:21.85#ibcon#about to read 6, iclass 16, count 0 2006.162.08:13:21.85#ibcon#read 6, iclass 16, count 0 2006.162.08:13:21.85#ibcon#end of sib2, iclass 16, count 0 2006.162.08:13:21.85#ibcon#*mode == 0, iclass 16, count 0 2006.162.08:13:21.85#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.162.08:13:21.85#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.08:13:21.85#ibcon#*before write, iclass 16, count 0 2006.162.08:13:21.85#ibcon#enter sib2, iclass 16, count 0 2006.162.08:13:21.85#ibcon#flushed, iclass 16, count 0 2006.162.08:13:21.85#ibcon#about to write, iclass 16, count 0 2006.162.08:13:21.85#ibcon#wrote, iclass 16, count 0 2006.162.08:13:21.85#ibcon#about to read 3, iclass 16, count 0 2006.162.08:13:21.89#ibcon#read 3, iclass 16, count 0 2006.162.08:13:21.89#ibcon#about to read 4, iclass 16, count 0 2006.162.08:13:21.89#ibcon#read 4, iclass 16, count 0 2006.162.08:13:21.89#ibcon#about to read 5, iclass 16, count 0 2006.162.08:13:21.89#ibcon#read 5, iclass 16, count 0 2006.162.08:13:21.89#ibcon#about to read 6, iclass 16, count 0 2006.162.08:13:21.89#ibcon#read 6, iclass 16, count 0 2006.162.08:13:21.89#ibcon#end of sib2, iclass 16, count 0 2006.162.08:13:21.89#ibcon#*after write, iclass 16, count 0 2006.162.08:13:21.89#ibcon#*before return 0, iclass 16, count 0 2006.162.08:13:21.89#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:13:21.89#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:13:21.89#ibcon#about to clear, iclass 16 cls_cnt 0 2006.162.08:13:21.89#ibcon#cleared, iclass 16 cls_cnt 0 2006.162.08:13:21.89$vc4f8/va=7,6 2006.162.08:13:21.89#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.162.08:13:21.89#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.162.08:13:21.89#ibcon#ireg 11 cls_cnt 2 2006.162.08:13:21.89#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:13:21.96#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:13:21.96#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:13:21.96#ibcon#enter wrdev, iclass 18, count 2 2006.162.08:13:21.96#ibcon#first serial, iclass 18, count 2 2006.162.08:13:21.96#ibcon#enter sib2, iclass 18, count 2 2006.162.08:13:21.96#ibcon#flushed, iclass 18, count 2 2006.162.08:13:21.96#ibcon#about to write, iclass 18, count 2 2006.162.08:13:21.96#ibcon#wrote, iclass 18, count 2 2006.162.08:13:21.96#ibcon#about to read 3, iclass 18, count 2 2006.162.08:13:21.97#ibcon#read 3, iclass 18, count 2 2006.162.08:13:21.97#ibcon#about to read 4, iclass 18, count 2 2006.162.08:13:21.97#ibcon#read 4, iclass 18, count 2 2006.162.08:13:21.97#ibcon#about to read 5, iclass 18, count 2 2006.162.08:13:21.97#ibcon#read 5, iclass 18, count 2 2006.162.08:13:21.97#ibcon#about to read 6, iclass 18, count 2 2006.162.08:13:21.97#ibcon#read 6, iclass 18, count 2 2006.162.08:13:21.97#ibcon#end of sib2, iclass 18, count 2 2006.162.08:13:21.97#ibcon#*mode == 0, iclass 18, count 2 2006.162.08:13:21.97#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.162.08:13:21.97#ibcon#[25=AT07-06\r\n] 2006.162.08:13:21.97#ibcon#*before write, iclass 18, count 2 2006.162.08:13:21.97#ibcon#enter sib2, iclass 18, count 2 2006.162.08:13:21.97#ibcon#flushed, iclass 18, count 2 2006.162.08:13:21.97#ibcon#about to write, iclass 18, count 2 2006.162.08:13:21.97#ibcon#wrote, iclass 18, count 2 2006.162.08:13:21.97#ibcon#about to read 3, iclass 18, count 2 2006.162.08:13:22.00#ibcon#read 3, iclass 18, count 2 2006.162.08:13:22.00#ibcon#about to read 4, iclass 18, count 2 2006.162.08:13:22.00#ibcon#read 4, iclass 18, count 2 2006.162.08:13:22.00#ibcon#about to read 5, iclass 18, count 2 2006.162.08:13:22.00#ibcon#read 5, iclass 18, count 2 2006.162.08:13:22.00#ibcon#about to read 6, iclass 18, count 2 2006.162.08:13:22.00#ibcon#read 6, iclass 18, count 2 2006.162.08:13:22.00#ibcon#end of sib2, iclass 18, count 2 2006.162.08:13:22.00#ibcon#*after write, iclass 18, count 2 2006.162.08:13:22.00#ibcon#*before return 0, iclass 18, count 2 2006.162.08:13:22.00#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:13:22.00#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:13:22.00#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.162.08:13:22.00#ibcon#ireg 7 cls_cnt 0 2006.162.08:13:22.00#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:13:22.12#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:13:22.12#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:13:22.12#ibcon#enter wrdev, iclass 18, count 0 2006.162.08:13:22.12#ibcon#first serial, iclass 18, count 0 2006.162.08:13:22.12#ibcon#enter sib2, iclass 18, count 0 2006.162.08:13:22.12#ibcon#flushed, iclass 18, count 0 2006.162.08:13:22.12#ibcon#about to write, iclass 18, count 0 2006.162.08:13:22.12#ibcon#wrote, iclass 18, count 0 2006.162.08:13:22.12#ibcon#about to read 3, iclass 18, count 0 2006.162.08:13:22.14#ibcon#read 3, iclass 18, count 0 2006.162.08:13:22.14#ibcon#about to read 4, iclass 18, count 0 2006.162.08:13:22.14#ibcon#read 4, iclass 18, count 0 2006.162.08:13:22.14#ibcon#about to read 5, iclass 18, count 0 2006.162.08:13:22.14#ibcon#read 5, iclass 18, count 0 2006.162.08:13:22.14#ibcon#about to read 6, iclass 18, count 0 2006.162.08:13:22.14#ibcon#read 6, iclass 18, count 0 2006.162.08:13:22.14#ibcon#end of sib2, iclass 18, count 0 2006.162.08:13:22.14#ibcon#*mode == 0, iclass 18, count 0 2006.162.08:13:22.14#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.162.08:13:22.14#ibcon#[25=USB\r\n] 2006.162.08:13:22.14#ibcon#*before write, iclass 18, count 0 2006.162.08:13:22.14#ibcon#enter sib2, iclass 18, count 0 2006.162.08:13:22.14#ibcon#flushed, iclass 18, count 0 2006.162.08:13:22.14#ibcon#about to write, iclass 18, count 0 2006.162.08:13:22.14#ibcon#wrote, iclass 18, count 0 2006.162.08:13:22.14#ibcon#about to read 3, iclass 18, count 0 2006.162.08:13:22.17#ibcon#read 3, iclass 18, count 0 2006.162.08:13:22.17#ibcon#about to read 4, iclass 18, count 0 2006.162.08:13:22.17#ibcon#read 4, iclass 18, count 0 2006.162.08:13:22.17#ibcon#about to read 5, iclass 18, count 0 2006.162.08:13:22.17#ibcon#read 5, iclass 18, count 0 2006.162.08:13:22.17#ibcon#about to read 6, iclass 18, count 0 2006.162.08:13:22.17#ibcon#read 6, iclass 18, count 0 2006.162.08:13:22.17#ibcon#end of sib2, iclass 18, count 0 2006.162.08:13:22.17#ibcon#*after write, iclass 18, count 0 2006.162.08:13:22.17#ibcon#*before return 0, iclass 18, count 0 2006.162.08:13:22.17#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:13:22.17#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:13:22.17#ibcon#about to clear, iclass 18 cls_cnt 0 2006.162.08:13:22.17#ibcon#cleared, iclass 18 cls_cnt 0 2006.162.08:13:22.17$vc4f8/valo=8,852.99 2006.162.08:13:22.17#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.162.08:13:22.17#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.162.08:13:22.17#ibcon#ireg 17 cls_cnt 0 2006.162.08:13:22.17#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:13:22.17#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:13:22.17#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:13:22.17#ibcon#enter wrdev, iclass 20, count 0 2006.162.08:13:22.17#ibcon#first serial, iclass 20, count 0 2006.162.08:13:22.17#ibcon#enter sib2, iclass 20, count 0 2006.162.08:13:22.17#ibcon#flushed, iclass 20, count 0 2006.162.08:13:22.17#ibcon#about to write, iclass 20, count 0 2006.162.08:13:22.17#ibcon#wrote, iclass 20, count 0 2006.162.08:13:22.17#ibcon#about to read 3, iclass 20, count 0 2006.162.08:13:22.19#ibcon#read 3, iclass 20, count 0 2006.162.08:13:22.19#ibcon#about to read 4, iclass 20, count 0 2006.162.08:13:22.19#ibcon#read 4, iclass 20, count 0 2006.162.08:13:22.19#ibcon#about to read 5, iclass 20, count 0 2006.162.08:13:22.19#ibcon#read 5, iclass 20, count 0 2006.162.08:13:22.19#ibcon#about to read 6, iclass 20, count 0 2006.162.08:13:22.19#ibcon#read 6, iclass 20, count 0 2006.162.08:13:22.19#ibcon#end of sib2, iclass 20, count 0 2006.162.08:13:22.19#ibcon#*mode == 0, iclass 20, count 0 2006.162.08:13:22.19#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.08:13:22.19#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.08:13:22.19#ibcon#*before write, iclass 20, count 0 2006.162.08:13:22.19#ibcon#enter sib2, iclass 20, count 0 2006.162.08:13:22.19#ibcon#flushed, iclass 20, count 0 2006.162.08:13:22.19#ibcon#about to write, iclass 20, count 0 2006.162.08:13:22.19#ibcon#wrote, iclass 20, count 0 2006.162.08:13:22.19#ibcon#about to read 3, iclass 20, count 0 2006.162.08:13:22.23#ibcon#read 3, iclass 20, count 0 2006.162.08:13:22.23#ibcon#about to read 4, iclass 20, count 0 2006.162.08:13:22.23#ibcon#read 4, iclass 20, count 0 2006.162.08:13:22.23#ibcon#about to read 5, iclass 20, count 0 2006.162.08:13:22.23#ibcon#read 5, iclass 20, count 0 2006.162.08:13:22.23#ibcon#about to read 6, iclass 20, count 0 2006.162.08:13:22.23#ibcon#read 6, iclass 20, count 0 2006.162.08:13:22.23#ibcon#end of sib2, iclass 20, count 0 2006.162.08:13:22.23#ibcon#*after write, iclass 20, count 0 2006.162.08:13:22.23#ibcon#*before return 0, iclass 20, count 0 2006.162.08:13:22.23#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:13:22.23#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:13:22.23#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.08:13:22.23#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.08:13:22.23$vc4f8/va=8,7 2006.162.08:13:22.23#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.162.08:13:22.23#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.162.08:13:22.23#ibcon#ireg 11 cls_cnt 2 2006.162.08:13:22.23#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:13:22.29#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:13:22.29#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:13:22.29#ibcon#enter wrdev, iclass 22, count 2 2006.162.08:13:22.29#ibcon#first serial, iclass 22, count 2 2006.162.08:13:22.29#ibcon#enter sib2, iclass 22, count 2 2006.162.08:13:22.29#ibcon#flushed, iclass 22, count 2 2006.162.08:13:22.29#ibcon#about to write, iclass 22, count 2 2006.162.08:13:22.29#ibcon#wrote, iclass 22, count 2 2006.162.08:13:22.29#ibcon#about to read 3, iclass 22, count 2 2006.162.08:13:22.31#ibcon#read 3, iclass 22, count 2 2006.162.08:13:22.31#ibcon#about to read 4, iclass 22, count 2 2006.162.08:13:22.31#ibcon#read 4, iclass 22, count 2 2006.162.08:13:22.31#ibcon#about to read 5, iclass 22, count 2 2006.162.08:13:22.31#ibcon#read 5, iclass 22, count 2 2006.162.08:13:22.31#ibcon#about to read 6, iclass 22, count 2 2006.162.08:13:22.31#ibcon#read 6, iclass 22, count 2 2006.162.08:13:22.31#ibcon#end of sib2, iclass 22, count 2 2006.162.08:13:22.31#ibcon#*mode == 0, iclass 22, count 2 2006.162.08:13:22.31#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.162.08:13:22.31#ibcon#[25=AT08-07\r\n] 2006.162.08:13:22.31#ibcon#*before write, iclass 22, count 2 2006.162.08:13:22.31#ibcon#enter sib2, iclass 22, count 2 2006.162.08:13:22.31#ibcon#flushed, iclass 22, count 2 2006.162.08:13:22.31#ibcon#about to write, iclass 22, count 2 2006.162.08:13:22.31#ibcon#wrote, iclass 22, count 2 2006.162.08:13:22.31#ibcon#about to read 3, iclass 22, count 2 2006.162.08:13:22.34#ibcon#read 3, iclass 22, count 2 2006.162.08:13:22.34#ibcon#about to read 4, iclass 22, count 2 2006.162.08:13:22.34#ibcon#read 4, iclass 22, count 2 2006.162.08:13:22.34#ibcon#about to read 5, iclass 22, count 2 2006.162.08:13:22.34#ibcon#read 5, iclass 22, count 2 2006.162.08:13:22.34#ibcon#about to read 6, iclass 22, count 2 2006.162.08:13:22.34#ibcon#read 6, iclass 22, count 2 2006.162.08:13:22.34#ibcon#end of sib2, iclass 22, count 2 2006.162.08:13:22.34#ibcon#*after write, iclass 22, count 2 2006.162.08:13:22.34#ibcon#*before return 0, iclass 22, count 2 2006.162.08:13:22.34#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:13:22.34#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:13:22.34#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.162.08:13:22.34#ibcon#ireg 7 cls_cnt 0 2006.162.08:13:22.34#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:13:22.46#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:13:22.46#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:13:22.46#ibcon#enter wrdev, iclass 22, count 0 2006.162.08:13:22.46#ibcon#first serial, iclass 22, count 0 2006.162.08:13:22.46#ibcon#enter sib2, iclass 22, count 0 2006.162.08:13:22.46#ibcon#flushed, iclass 22, count 0 2006.162.08:13:22.46#ibcon#about to write, iclass 22, count 0 2006.162.08:13:22.46#ibcon#wrote, iclass 22, count 0 2006.162.08:13:22.46#ibcon#about to read 3, iclass 22, count 0 2006.162.08:13:22.48#ibcon#read 3, iclass 22, count 0 2006.162.08:13:22.48#ibcon#about to read 4, iclass 22, count 0 2006.162.08:13:22.48#ibcon#read 4, iclass 22, count 0 2006.162.08:13:22.48#ibcon#about to read 5, iclass 22, count 0 2006.162.08:13:22.48#ibcon#read 5, iclass 22, count 0 2006.162.08:13:22.48#ibcon#about to read 6, iclass 22, count 0 2006.162.08:13:22.48#ibcon#read 6, iclass 22, count 0 2006.162.08:13:22.48#ibcon#end of sib2, iclass 22, count 0 2006.162.08:13:22.48#ibcon#*mode == 0, iclass 22, count 0 2006.162.08:13:22.48#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.08:13:22.48#ibcon#[25=USB\r\n] 2006.162.08:13:22.48#ibcon#*before write, iclass 22, count 0 2006.162.08:13:22.48#ibcon#enter sib2, iclass 22, count 0 2006.162.08:13:22.48#ibcon#flushed, iclass 22, count 0 2006.162.08:13:22.48#ibcon#about to write, iclass 22, count 0 2006.162.08:13:22.48#ibcon#wrote, iclass 22, count 0 2006.162.08:13:22.48#ibcon#about to read 3, iclass 22, count 0 2006.162.08:13:22.51#ibcon#read 3, iclass 22, count 0 2006.162.08:13:22.51#ibcon#about to read 4, iclass 22, count 0 2006.162.08:13:22.51#ibcon#read 4, iclass 22, count 0 2006.162.08:13:22.51#ibcon#about to read 5, iclass 22, count 0 2006.162.08:13:22.51#ibcon#read 5, iclass 22, count 0 2006.162.08:13:22.51#ibcon#about to read 6, iclass 22, count 0 2006.162.08:13:22.51#ibcon#read 6, iclass 22, count 0 2006.162.08:13:22.51#ibcon#end of sib2, iclass 22, count 0 2006.162.08:13:22.51#ibcon#*after write, iclass 22, count 0 2006.162.08:13:22.51#ibcon#*before return 0, iclass 22, count 0 2006.162.08:13:22.51#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:13:22.51#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:13:22.51#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.08:13:22.51#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.08:13:22.51$vc4f8/vblo=1,632.99 2006.162.08:13:22.51#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.162.08:13:22.51#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.162.08:13:22.51#ibcon#ireg 17 cls_cnt 0 2006.162.08:13:22.51#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:13:22.51#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:13:22.51#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:13:22.51#ibcon#enter wrdev, iclass 24, count 0 2006.162.08:13:22.51#ibcon#first serial, iclass 24, count 0 2006.162.08:13:22.51#ibcon#enter sib2, iclass 24, count 0 2006.162.08:13:22.51#ibcon#flushed, iclass 24, count 0 2006.162.08:13:22.51#ibcon#about to write, iclass 24, count 0 2006.162.08:13:22.51#ibcon#wrote, iclass 24, count 0 2006.162.08:13:22.51#ibcon#about to read 3, iclass 24, count 0 2006.162.08:13:22.53#ibcon#read 3, iclass 24, count 0 2006.162.08:13:22.53#ibcon#about to read 4, iclass 24, count 0 2006.162.08:13:22.53#ibcon#read 4, iclass 24, count 0 2006.162.08:13:22.53#ibcon#about to read 5, iclass 24, count 0 2006.162.08:13:22.53#ibcon#read 5, iclass 24, count 0 2006.162.08:13:22.53#ibcon#about to read 6, iclass 24, count 0 2006.162.08:13:22.53#ibcon#read 6, iclass 24, count 0 2006.162.08:13:22.53#ibcon#end of sib2, iclass 24, count 0 2006.162.08:13:22.53#ibcon#*mode == 0, iclass 24, count 0 2006.162.08:13:22.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.08:13:22.53#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.08:13:22.53#ibcon#*before write, iclass 24, count 0 2006.162.08:13:22.53#ibcon#enter sib2, iclass 24, count 0 2006.162.08:13:22.53#ibcon#flushed, iclass 24, count 0 2006.162.08:13:22.53#ibcon#about to write, iclass 24, count 0 2006.162.08:13:22.53#ibcon#wrote, iclass 24, count 0 2006.162.08:13:22.53#ibcon#about to read 3, iclass 24, count 0 2006.162.08:13:22.57#ibcon#read 3, iclass 24, count 0 2006.162.08:13:22.57#ibcon#about to read 4, iclass 24, count 0 2006.162.08:13:22.57#ibcon#read 4, iclass 24, count 0 2006.162.08:13:22.57#ibcon#about to read 5, iclass 24, count 0 2006.162.08:13:22.57#ibcon#read 5, iclass 24, count 0 2006.162.08:13:22.57#ibcon#about to read 6, iclass 24, count 0 2006.162.08:13:22.57#ibcon#read 6, iclass 24, count 0 2006.162.08:13:22.57#ibcon#end of sib2, iclass 24, count 0 2006.162.08:13:22.57#ibcon#*after write, iclass 24, count 0 2006.162.08:13:22.57#ibcon#*before return 0, iclass 24, count 0 2006.162.08:13:22.57#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:13:22.57#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:13:22.57#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.08:13:22.57#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.08:13:22.57$vc4f8/vb=1,4 2006.162.08:13:22.57#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.162.08:13:22.57#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.162.08:13:22.57#ibcon#ireg 11 cls_cnt 2 2006.162.08:13:22.57#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:13:22.57#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:13:22.57#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:13:22.57#ibcon#enter wrdev, iclass 26, count 2 2006.162.08:13:22.57#ibcon#first serial, iclass 26, count 2 2006.162.08:13:22.57#ibcon#enter sib2, iclass 26, count 2 2006.162.08:13:22.57#ibcon#flushed, iclass 26, count 2 2006.162.08:13:22.57#ibcon#about to write, iclass 26, count 2 2006.162.08:13:22.57#ibcon#wrote, iclass 26, count 2 2006.162.08:13:22.57#ibcon#about to read 3, iclass 26, count 2 2006.162.08:13:22.59#ibcon#read 3, iclass 26, count 2 2006.162.08:13:22.59#ibcon#about to read 4, iclass 26, count 2 2006.162.08:13:22.59#ibcon#read 4, iclass 26, count 2 2006.162.08:13:22.59#ibcon#about to read 5, iclass 26, count 2 2006.162.08:13:22.59#ibcon#read 5, iclass 26, count 2 2006.162.08:13:22.59#ibcon#about to read 6, iclass 26, count 2 2006.162.08:13:22.59#ibcon#read 6, iclass 26, count 2 2006.162.08:13:22.59#ibcon#end of sib2, iclass 26, count 2 2006.162.08:13:22.59#ibcon#*mode == 0, iclass 26, count 2 2006.162.08:13:22.59#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.162.08:13:22.59#ibcon#[27=AT01-04\r\n] 2006.162.08:13:22.59#ibcon#*before write, iclass 26, count 2 2006.162.08:13:22.59#ibcon#enter sib2, iclass 26, count 2 2006.162.08:13:22.59#ibcon#flushed, iclass 26, count 2 2006.162.08:13:22.59#ibcon#about to write, iclass 26, count 2 2006.162.08:13:22.59#ibcon#wrote, iclass 26, count 2 2006.162.08:13:22.59#ibcon#about to read 3, iclass 26, count 2 2006.162.08:13:22.62#ibcon#read 3, iclass 26, count 2 2006.162.08:13:22.62#ibcon#about to read 4, iclass 26, count 2 2006.162.08:13:22.62#ibcon#read 4, iclass 26, count 2 2006.162.08:13:22.62#ibcon#about to read 5, iclass 26, count 2 2006.162.08:13:22.62#ibcon#read 5, iclass 26, count 2 2006.162.08:13:22.62#ibcon#about to read 6, iclass 26, count 2 2006.162.08:13:22.62#ibcon#read 6, iclass 26, count 2 2006.162.08:13:22.62#ibcon#end of sib2, iclass 26, count 2 2006.162.08:13:22.62#ibcon#*after write, iclass 26, count 2 2006.162.08:13:22.62#ibcon#*before return 0, iclass 26, count 2 2006.162.08:13:22.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:13:22.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:13:22.62#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.162.08:13:22.62#ibcon#ireg 7 cls_cnt 0 2006.162.08:13:22.62#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:13:22.74#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:13:22.74#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:13:22.74#ibcon#enter wrdev, iclass 26, count 0 2006.162.08:13:22.74#ibcon#first serial, iclass 26, count 0 2006.162.08:13:22.74#ibcon#enter sib2, iclass 26, count 0 2006.162.08:13:22.74#ibcon#flushed, iclass 26, count 0 2006.162.08:13:22.74#ibcon#about to write, iclass 26, count 0 2006.162.08:13:22.74#ibcon#wrote, iclass 26, count 0 2006.162.08:13:22.74#ibcon#about to read 3, iclass 26, count 0 2006.162.08:13:22.76#ibcon#read 3, iclass 26, count 0 2006.162.08:13:22.76#ibcon#about to read 4, iclass 26, count 0 2006.162.08:13:22.76#ibcon#read 4, iclass 26, count 0 2006.162.08:13:22.76#ibcon#about to read 5, iclass 26, count 0 2006.162.08:13:22.76#ibcon#read 5, iclass 26, count 0 2006.162.08:13:22.76#ibcon#about to read 6, iclass 26, count 0 2006.162.08:13:22.76#ibcon#read 6, iclass 26, count 0 2006.162.08:13:22.76#ibcon#end of sib2, iclass 26, count 0 2006.162.08:13:22.76#ibcon#*mode == 0, iclass 26, count 0 2006.162.08:13:22.76#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.162.08:13:22.76#ibcon#[27=USB\r\n] 2006.162.08:13:22.76#ibcon#*before write, iclass 26, count 0 2006.162.08:13:22.76#ibcon#enter sib2, iclass 26, count 0 2006.162.08:13:22.76#ibcon#flushed, iclass 26, count 0 2006.162.08:13:22.76#ibcon#about to write, iclass 26, count 0 2006.162.08:13:22.76#ibcon#wrote, iclass 26, count 0 2006.162.08:13:22.76#ibcon#about to read 3, iclass 26, count 0 2006.162.08:13:22.79#ibcon#read 3, iclass 26, count 0 2006.162.08:13:22.79#ibcon#about to read 4, iclass 26, count 0 2006.162.08:13:22.79#ibcon#read 4, iclass 26, count 0 2006.162.08:13:22.79#ibcon#about to read 5, iclass 26, count 0 2006.162.08:13:22.79#ibcon#read 5, iclass 26, count 0 2006.162.08:13:22.79#ibcon#about to read 6, iclass 26, count 0 2006.162.08:13:22.79#ibcon#read 6, iclass 26, count 0 2006.162.08:13:22.79#ibcon#end of sib2, iclass 26, count 0 2006.162.08:13:22.79#ibcon#*after write, iclass 26, count 0 2006.162.08:13:22.79#ibcon#*before return 0, iclass 26, count 0 2006.162.08:13:22.79#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:13:22.79#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:13:22.79#ibcon#about to clear, iclass 26 cls_cnt 0 2006.162.08:13:22.79#ibcon#cleared, iclass 26 cls_cnt 0 2006.162.08:13:22.79$vc4f8/vblo=2,640.99 2006.162.08:13:22.79#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.162.08:13:22.79#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.162.08:13:22.79#ibcon#ireg 17 cls_cnt 0 2006.162.08:13:22.79#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:13:22.79#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:13:22.79#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:13:22.79#ibcon#enter wrdev, iclass 28, count 0 2006.162.08:13:22.79#ibcon#first serial, iclass 28, count 0 2006.162.08:13:22.79#ibcon#enter sib2, iclass 28, count 0 2006.162.08:13:22.79#ibcon#flushed, iclass 28, count 0 2006.162.08:13:22.79#ibcon#about to write, iclass 28, count 0 2006.162.08:13:22.79#ibcon#wrote, iclass 28, count 0 2006.162.08:13:22.79#ibcon#about to read 3, iclass 28, count 0 2006.162.08:13:22.81#ibcon#read 3, iclass 28, count 0 2006.162.08:13:22.81#ibcon#about to read 4, iclass 28, count 0 2006.162.08:13:22.81#ibcon#read 4, iclass 28, count 0 2006.162.08:13:22.81#ibcon#about to read 5, iclass 28, count 0 2006.162.08:13:22.81#ibcon#read 5, iclass 28, count 0 2006.162.08:13:22.81#ibcon#about to read 6, iclass 28, count 0 2006.162.08:13:22.81#ibcon#read 6, iclass 28, count 0 2006.162.08:13:22.81#ibcon#end of sib2, iclass 28, count 0 2006.162.08:13:22.81#ibcon#*mode == 0, iclass 28, count 0 2006.162.08:13:22.81#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.162.08:13:22.81#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.08:13:22.81#ibcon#*before write, iclass 28, count 0 2006.162.08:13:22.81#ibcon#enter sib2, iclass 28, count 0 2006.162.08:13:22.81#ibcon#flushed, iclass 28, count 0 2006.162.08:13:22.81#ibcon#about to write, iclass 28, count 0 2006.162.08:13:22.81#ibcon#wrote, iclass 28, count 0 2006.162.08:13:22.81#ibcon#about to read 3, iclass 28, count 0 2006.162.08:13:22.85#ibcon#read 3, iclass 28, count 0 2006.162.08:13:22.85#ibcon#about to read 4, iclass 28, count 0 2006.162.08:13:22.85#ibcon#read 4, iclass 28, count 0 2006.162.08:13:22.85#ibcon#about to read 5, iclass 28, count 0 2006.162.08:13:22.85#ibcon#read 5, iclass 28, count 0 2006.162.08:13:22.85#ibcon#about to read 6, iclass 28, count 0 2006.162.08:13:22.85#ibcon#read 6, iclass 28, count 0 2006.162.08:13:22.85#ibcon#end of sib2, iclass 28, count 0 2006.162.08:13:22.85#ibcon#*after write, iclass 28, count 0 2006.162.08:13:22.85#ibcon#*before return 0, iclass 28, count 0 2006.162.08:13:22.85#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:13:22.85#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:13:22.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.162.08:13:22.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.162.08:13:22.85$vc4f8/vb=2,4 2006.162.08:13:22.85#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.162.08:13:22.85#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.162.08:13:22.85#ibcon#ireg 11 cls_cnt 2 2006.162.08:13:22.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:13:22.91#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:13:22.91#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:13:22.91#ibcon#enter wrdev, iclass 30, count 2 2006.162.08:13:22.91#ibcon#first serial, iclass 30, count 2 2006.162.08:13:22.91#ibcon#enter sib2, iclass 30, count 2 2006.162.08:13:22.91#ibcon#flushed, iclass 30, count 2 2006.162.08:13:22.91#ibcon#about to write, iclass 30, count 2 2006.162.08:13:22.91#ibcon#wrote, iclass 30, count 2 2006.162.08:13:22.91#ibcon#about to read 3, iclass 30, count 2 2006.162.08:13:22.93#ibcon#read 3, iclass 30, count 2 2006.162.08:13:22.93#ibcon#about to read 4, iclass 30, count 2 2006.162.08:13:22.93#ibcon#read 4, iclass 30, count 2 2006.162.08:13:22.93#ibcon#about to read 5, iclass 30, count 2 2006.162.08:13:22.93#ibcon#read 5, iclass 30, count 2 2006.162.08:13:22.93#ibcon#about to read 6, iclass 30, count 2 2006.162.08:13:22.93#ibcon#read 6, iclass 30, count 2 2006.162.08:13:22.93#ibcon#end of sib2, iclass 30, count 2 2006.162.08:13:22.93#ibcon#*mode == 0, iclass 30, count 2 2006.162.08:13:22.93#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.162.08:13:22.93#ibcon#[27=AT02-04\r\n] 2006.162.08:13:22.93#ibcon#*before write, iclass 30, count 2 2006.162.08:13:22.93#ibcon#enter sib2, iclass 30, count 2 2006.162.08:13:22.93#ibcon#flushed, iclass 30, count 2 2006.162.08:13:22.93#ibcon#about to write, iclass 30, count 2 2006.162.08:13:22.93#ibcon#wrote, iclass 30, count 2 2006.162.08:13:22.93#ibcon#about to read 3, iclass 30, count 2 2006.162.08:13:22.96#ibcon#read 3, iclass 30, count 2 2006.162.08:13:22.96#ibcon#about to read 4, iclass 30, count 2 2006.162.08:13:22.96#ibcon#read 4, iclass 30, count 2 2006.162.08:13:22.96#ibcon#about to read 5, iclass 30, count 2 2006.162.08:13:22.96#ibcon#read 5, iclass 30, count 2 2006.162.08:13:22.96#ibcon#about to read 6, iclass 30, count 2 2006.162.08:13:22.96#ibcon#read 6, iclass 30, count 2 2006.162.08:13:22.96#ibcon#end of sib2, iclass 30, count 2 2006.162.08:13:22.96#ibcon#*after write, iclass 30, count 2 2006.162.08:13:22.96#ibcon#*before return 0, iclass 30, count 2 2006.162.08:13:22.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:13:22.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:13:22.96#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.162.08:13:22.96#ibcon#ireg 7 cls_cnt 0 2006.162.08:13:22.96#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:13:23.08#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:13:23.08#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:13:23.08#ibcon#enter wrdev, iclass 30, count 0 2006.162.08:13:23.08#ibcon#first serial, iclass 30, count 0 2006.162.08:13:23.08#ibcon#enter sib2, iclass 30, count 0 2006.162.08:13:23.08#ibcon#flushed, iclass 30, count 0 2006.162.08:13:23.08#ibcon#about to write, iclass 30, count 0 2006.162.08:13:23.08#ibcon#wrote, iclass 30, count 0 2006.162.08:13:23.08#ibcon#about to read 3, iclass 30, count 0 2006.162.08:13:23.10#ibcon#read 3, iclass 30, count 0 2006.162.08:13:23.10#ibcon#about to read 4, iclass 30, count 0 2006.162.08:13:23.10#ibcon#read 4, iclass 30, count 0 2006.162.08:13:23.10#ibcon#about to read 5, iclass 30, count 0 2006.162.08:13:23.10#ibcon#read 5, iclass 30, count 0 2006.162.08:13:23.10#ibcon#about to read 6, iclass 30, count 0 2006.162.08:13:23.10#ibcon#read 6, iclass 30, count 0 2006.162.08:13:23.10#ibcon#end of sib2, iclass 30, count 0 2006.162.08:13:23.10#ibcon#*mode == 0, iclass 30, count 0 2006.162.08:13:23.10#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.162.08:13:23.10#ibcon#[27=USB\r\n] 2006.162.08:13:23.10#ibcon#*before write, iclass 30, count 0 2006.162.08:13:23.10#ibcon#enter sib2, iclass 30, count 0 2006.162.08:13:23.10#ibcon#flushed, iclass 30, count 0 2006.162.08:13:23.10#ibcon#about to write, iclass 30, count 0 2006.162.08:13:23.10#ibcon#wrote, iclass 30, count 0 2006.162.08:13:23.10#ibcon#about to read 3, iclass 30, count 0 2006.162.08:13:23.13#ibcon#read 3, iclass 30, count 0 2006.162.08:13:23.13#ibcon#about to read 4, iclass 30, count 0 2006.162.08:13:23.13#ibcon#read 4, iclass 30, count 0 2006.162.08:13:23.13#ibcon#about to read 5, iclass 30, count 0 2006.162.08:13:23.13#ibcon#read 5, iclass 30, count 0 2006.162.08:13:23.13#ibcon#about to read 6, iclass 30, count 0 2006.162.08:13:23.13#ibcon#read 6, iclass 30, count 0 2006.162.08:13:23.13#ibcon#end of sib2, iclass 30, count 0 2006.162.08:13:23.13#ibcon#*after write, iclass 30, count 0 2006.162.08:13:23.13#ibcon#*before return 0, iclass 30, count 0 2006.162.08:13:23.13#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:13:23.13#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:13:23.13#ibcon#about to clear, iclass 30 cls_cnt 0 2006.162.08:13:23.13#ibcon#cleared, iclass 30 cls_cnt 0 2006.162.08:13:23.13$vc4f8/vblo=3,656.99 2006.162.08:13:23.13#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.162.08:13:23.13#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.162.08:13:23.13#ibcon#ireg 17 cls_cnt 0 2006.162.08:13:23.13#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:13:23.13#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:13:23.13#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:13:23.13#ibcon#enter wrdev, iclass 32, count 0 2006.162.08:13:23.13#ibcon#first serial, iclass 32, count 0 2006.162.08:13:23.13#ibcon#enter sib2, iclass 32, count 0 2006.162.08:13:23.13#ibcon#flushed, iclass 32, count 0 2006.162.08:13:23.13#ibcon#about to write, iclass 32, count 0 2006.162.08:13:23.13#ibcon#wrote, iclass 32, count 0 2006.162.08:13:23.13#ibcon#about to read 3, iclass 32, count 0 2006.162.08:13:23.15#ibcon#read 3, iclass 32, count 0 2006.162.08:13:23.15#ibcon#about to read 4, iclass 32, count 0 2006.162.08:13:23.15#ibcon#read 4, iclass 32, count 0 2006.162.08:13:23.15#ibcon#about to read 5, iclass 32, count 0 2006.162.08:13:23.15#ibcon#read 5, iclass 32, count 0 2006.162.08:13:23.15#ibcon#about to read 6, iclass 32, count 0 2006.162.08:13:23.15#ibcon#read 6, iclass 32, count 0 2006.162.08:13:23.15#ibcon#end of sib2, iclass 32, count 0 2006.162.08:13:23.15#ibcon#*mode == 0, iclass 32, count 0 2006.162.08:13:23.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.162.08:13:23.15#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.08:13:23.15#ibcon#*before write, iclass 32, count 0 2006.162.08:13:23.15#ibcon#enter sib2, iclass 32, count 0 2006.162.08:13:23.15#ibcon#flushed, iclass 32, count 0 2006.162.08:13:23.15#ibcon#about to write, iclass 32, count 0 2006.162.08:13:23.15#ibcon#wrote, iclass 32, count 0 2006.162.08:13:23.15#ibcon#about to read 3, iclass 32, count 0 2006.162.08:13:23.19#ibcon#read 3, iclass 32, count 0 2006.162.08:13:23.19#ibcon#about to read 4, iclass 32, count 0 2006.162.08:13:23.19#ibcon#read 4, iclass 32, count 0 2006.162.08:13:23.19#ibcon#about to read 5, iclass 32, count 0 2006.162.08:13:23.19#ibcon#read 5, iclass 32, count 0 2006.162.08:13:23.19#ibcon#about to read 6, iclass 32, count 0 2006.162.08:13:23.19#ibcon#read 6, iclass 32, count 0 2006.162.08:13:23.19#ibcon#end of sib2, iclass 32, count 0 2006.162.08:13:23.19#ibcon#*after write, iclass 32, count 0 2006.162.08:13:23.19#ibcon#*before return 0, iclass 32, count 0 2006.162.08:13:23.19#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:13:23.19#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:13:23.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.162.08:13:23.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.162.08:13:23.19$vc4f8/vb=3,4 2006.162.08:13:23.19#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.162.08:13:23.19#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.162.08:13:23.19#ibcon#ireg 11 cls_cnt 2 2006.162.08:13:23.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:13:23.25#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:13:23.25#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:13:23.25#ibcon#enter wrdev, iclass 34, count 2 2006.162.08:13:23.25#ibcon#first serial, iclass 34, count 2 2006.162.08:13:23.25#ibcon#enter sib2, iclass 34, count 2 2006.162.08:13:23.25#ibcon#flushed, iclass 34, count 2 2006.162.08:13:23.25#ibcon#about to write, iclass 34, count 2 2006.162.08:13:23.25#ibcon#wrote, iclass 34, count 2 2006.162.08:13:23.25#ibcon#about to read 3, iclass 34, count 2 2006.162.08:13:23.27#ibcon#read 3, iclass 34, count 2 2006.162.08:13:23.27#ibcon#about to read 4, iclass 34, count 2 2006.162.08:13:23.27#ibcon#read 4, iclass 34, count 2 2006.162.08:13:23.27#ibcon#about to read 5, iclass 34, count 2 2006.162.08:13:23.27#ibcon#read 5, iclass 34, count 2 2006.162.08:13:23.27#ibcon#about to read 6, iclass 34, count 2 2006.162.08:13:23.27#ibcon#read 6, iclass 34, count 2 2006.162.08:13:23.27#ibcon#end of sib2, iclass 34, count 2 2006.162.08:13:23.27#ibcon#*mode == 0, iclass 34, count 2 2006.162.08:13:23.27#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.162.08:13:23.27#ibcon#[27=AT03-04\r\n] 2006.162.08:13:23.27#ibcon#*before write, iclass 34, count 2 2006.162.08:13:23.27#ibcon#enter sib2, iclass 34, count 2 2006.162.08:13:23.27#ibcon#flushed, iclass 34, count 2 2006.162.08:13:23.27#ibcon#about to write, iclass 34, count 2 2006.162.08:13:23.27#ibcon#wrote, iclass 34, count 2 2006.162.08:13:23.27#ibcon#about to read 3, iclass 34, count 2 2006.162.08:13:23.30#ibcon#read 3, iclass 34, count 2 2006.162.08:13:23.30#ibcon#about to read 4, iclass 34, count 2 2006.162.08:13:23.30#ibcon#read 4, iclass 34, count 2 2006.162.08:13:23.30#ibcon#about to read 5, iclass 34, count 2 2006.162.08:13:23.30#ibcon#read 5, iclass 34, count 2 2006.162.08:13:23.30#ibcon#about to read 6, iclass 34, count 2 2006.162.08:13:23.30#ibcon#read 6, iclass 34, count 2 2006.162.08:13:23.30#ibcon#end of sib2, iclass 34, count 2 2006.162.08:13:23.30#ibcon#*after write, iclass 34, count 2 2006.162.08:13:23.30#ibcon#*before return 0, iclass 34, count 2 2006.162.08:13:23.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:13:23.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:13:23.30#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.162.08:13:23.30#ibcon#ireg 7 cls_cnt 0 2006.162.08:13:23.30#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:13:23.42#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:13:23.42#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:13:23.42#ibcon#enter wrdev, iclass 34, count 0 2006.162.08:13:23.42#ibcon#first serial, iclass 34, count 0 2006.162.08:13:23.42#ibcon#enter sib2, iclass 34, count 0 2006.162.08:13:23.42#ibcon#flushed, iclass 34, count 0 2006.162.08:13:23.42#ibcon#about to write, iclass 34, count 0 2006.162.08:13:23.42#ibcon#wrote, iclass 34, count 0 2006.162.08:13:23.42#ibcon#about to read 3, iclass 34, count 0 2006.162.08:13:23.44#ibcon#read 3, iclass 34, count 0 2006.162.08:13:23.44#ibcon#about to read 4, iclass 34, count 0 2006.162.08:13:23.44#ibcon#read 4, iclass 34, count 0 2006.162.08:13:23.44#ibcon#about to read 5, iclass 34, count 0 2006.162.08:13:23.44#ibcon#read 5, iclass 34, count 0 2006.162.08:13:23.44#ibcon#about to read 6, iclass 34, count 0 2006.162.08:13:23.44#ibcon#read 6, iclass 34, count 0 2006.162.08:13:23.44#ibcon#end of sib2, iclass 34, count 0 2006.162.08:13:23.44#ibcon#*mode == 0, iclass 34, count 0 2006.162.08:13:23.44#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.162.08:13:23.44#ibcon#[27=USB\r\n] 2006.162.08:13:23.44#ibcon#*before write, iclass 34, count 0 2006.162.08:13:23.44#ibcon#enter sib2, iclass 34, count 0 2006.162.08:13:23.44#ibcon#flushed, iclass 34, count 0 2006.162.08:13:23.44#ibcon#about to write, iclass 34, count 0 2006.162.08:13:23.44#ibcon#wrote, iclass 34, count 0 2006.162.08:13:23.44#ibcon#about to read 3, iclass 34, count 0 2006.162.08:13:23.47#ibcon#read 3, iclass 34, count 0 2006.162.08:13:23.47#ibcon#about to read 4, iclass 34, count 0 2006.162.08:13:23.47#ibcon#read 4, iclass 34, count 0 2006.162.08:13:23.47#ibcon#about to read 5, iclass 34, count 0 2006.162.08:13:23.47#ibcon#read 5, iclass 34, count 0 2006.162.08:13:23.47#ibcon#about to read 6, iclass 34, count 0 2006.162.08:13:23.47#ibcon#read 6, iclass 34, count 0 2006.162.08:13:23.47#ibcon#end of sib2, iclass 34, count 0 2006.162.08:13:23.47#ibcon#*after write, iclass 34, count 0 2006.162.08:13:23.47#ibcon#*before return 0, iclass 34, count 0 2006.162.08:13:23.47#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:13:23.47#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:13:23.47#ibcon#about to clear, iclass 34 cls_cnt 0 2006.162.08:13:23.47#ibcon#cleared, iclass 34 cls_cnt 0 2006.162.08:13:23.47$vc4f8/vblo=4,712.99 2006.162.08:13:23.47#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.162.08:13:23.47#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.162.08:13:23.47#ibcon#ireg 17 cls_cnt 0 2006.162.08:13:23.47#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:13:23.47#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:13:23.47#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:13:23.47#ibcon#enter wrdev, iclass 36, count 0 2006.162.08:13:23.47#ibcon#first serial, iclass 36, count 0 2006.162.08:13:23.47#ibcon#enter sib2, iclass 36, count 0 2006.162.08:13:23.47#ibcon#flushed, iclass 36, count 0 2006.162.08:13:23.47#ibcon#about to write, iclass 36, count 0 2006.162.08:13:23.47#ibcon#wrote, iclass 36, count 0 2006.162.08:13:23.47#ibcon#about to read 3, iclass 36, count 0 2006.162.08:13:23.49#ibcon#read 3, iclass 36, count 0 2006.162.08:13:23.49#ibcon#about to read 4, iclass 36, count 0 2006.162.08:13:23.49#ibcon#read 4, iclass 36, count 0 2006.162.08:13:23.49#ibcon#about to read 5, iclass 36, count 0 2006.162.08:13:23.49#ibcon#read 5, iclass 36, count 0 2006.162.08:13:23.49#ibcon#about to read 6, iclass 36, count 0 2006.162.08:13:23.49#ibcon#read 6, iclass 36, count 0 2006.162.08:13:23.49#ibcon#end of sib2, iclass 36, count 0 2006.162.08:13:23.49#ibcon#*mode == 0, iclass 36, count 0 2006.162.08:13:23.49#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.162.08:13:23.49#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.08:13:23.49#ibcon#*before write, iclass 36, count 0 2006.162.08:13:23.49#ibcon#enter sib2, iclass 36, count 0 2006.162.08:13:23.49#ibcon#flushed, iclass 36, count 0 2006.162.08:13:23.49#ibcon#about to write, iclass 36, count 0 2006.162.08:13:23.49#ibcon#wrote, iclass 36, count 0 2006.162.08:13:23.49#ibcon#about to read 3, iclass 36, count 0 2006.162.08:13:23.53#ibcon#read 3, iclass 36, count 0 2006.162.08:13:23.53#ibcon#about to read 4, iclass 36, count 0 2006.162.08:13:23.53#ibcon#read 4, iclass 36, count 0 2006.162.08:13:23.53#ibcon#about to read 5, iclass 36, count 0 2006.162.08:13:23.53#ibcon#read 5, iclass 36, count 0 2006.162.08:13:23.53#ibcon#about to read 6, iclass 36, count 0 2006.162.08:13:23.53#ibcon#read 6, iclass 36, count 0 2006.162.08:13:23.53#ibcon#end of sib2, iclass 36, count 0 2006.162.08:13:23.53#ibcon#*after write, iclass 36, count 0 2006.162.08:13:23.53#ibcon#*before return 0, iclass 36, count 0 2006.162.08:13:23.53#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:13:23.53#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:13:23.53#ibcon#about to clear, iclass 36 cls_cnt 0 2006.162.08:13:23.53#ibcon#cleared, iclass 36 cls_cnt 0 2006.162.08:13:23.53$vc4f8/vb=4,4 2006.162.08:13:23.53#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.162.08:13:23.53#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.162.08:13:23.53#ibcon#ireg 11 cls_cnt 2 2006.162.08:13:23.53#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.162.08:13:23.59#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.162.08:13:23.59#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.162.08:13:23.59#ibcon#enter wrdev, iclass 38, count 2 2006.162.08:13:23.59#ibcon#first serial, iclass 38, count 2 2006.162.08:13:23.59#ibcon#enter sib2, iclass 38, count 2 2006.162.08:13:23.59#ibcon#flushed, iclass 38, count 2 2006.162.08:13:23.59#ibcon#about to write, iclass 38, count 2 2006.162.08:13:23.59#ibcon#wrote, iclass 38, count 2 2006.162.08:13:23.59#ibcon#about to read 3, iclass 38, count 2 2006.162.08:13:23.61#ibcon#read 3, iclass 38, count 2 2006.162.08:13:23.61#ibcon#about to read 4, iclass 38, count 2 2006.162.08:13:23.61#ibcon#read 4, iclass 38, count 2 2006.162.08:13:23.61#ibcon#about to read 5, iclass 38, count 2 2006.162.08:13:23.61#ibcon#read 5, iclass 38, count 2 2006.162.08:13:23.61#ibcon#about to read 6, iclass 38, count 2 2006.162.08:13:23.61#ibcon#read 6, iclass 38, count 2 2006.162.08:13:23.61#ibcon#end of sib2, iclass 38, count 2 2006.162.08:13:23.61#ibcon#*mode == 0, iclass 38, count 2 2006.162.08:13:23.61#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.162.08:13:23.61#ibcon#[27=AT04-04\r\n] 2006.162.08:13:23.61#ibcon#*before write, iclass 38, count 2 2006.162.08:13:23.61#ibcon#enter sib2, iclass 38, count 2 2006.162.08:13:23.61#ibcon#flushed, iclass 38, count 2 2006.162.08:13:23.61#ibcon#about to write, iclass 38, count 2 2006.162.08:13:23.61#ibcon#wrote, iclass 38, count 2 2006.162.08:13:23.61#ibcon#about to read 3, iclass 38, count 2 2006.162.08:13:23.64#ibcon#read 3, iclass 38, count 2 2006.162.08:13:23.64#ibcon#about to read 4, iclass 38, count 2 2006.162.08:13:23.64#ibcon#read 4, iclass 38, count 2 2006.162.08:13:23.64#ibcon#about to read 5, iclass 38, count 2 2006.162.08:13:23.64#ibcon#read 5, iclass 38, count 2 2006.162.08:13:23.64#ibcon#about to read 6, iclass 38, count 2 2006.162.08:13:23.64#ibcon#read 6, iclass 38, count 2 2006.162.08:13:23.64#ibcon#end of sib2, iclass 38, count 2 2006.162.08:13:23.64#ibcon#*after write, iclass 38, count 2 2006.162.08:13:23.64#ibcon#*before return 0, iclass 38, count 2 2006.162.08:13:23.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.162.08:13:23.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.162.08:13:23.64#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.162.08:13:23.64#ibcon#ireg 7 cls_cnt 0 2006.162.08:13:23.64#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.162.08:13:23.76#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.162.08:13:23.76#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.162.08:13:23.76#ibcon#enter wrdev, iclass 38, count 0 2006.162.08:13:23.76#ibcon#first serial, iclass 38, count 0 2006.162.08:13:23.76#ibcon#enter sib2, iclass 38, count 0 2006.162.08:13:23.76#ibcon#flushed, iclass 38, count 0 2006.162.08:13:23.76#ibcon#about to write, iclass 38, count 0 2006.162.08:13:23.76#ibcon#wrote, iclass 38, count 0 2006.162.08:13:23.76#ibcon#about to read 3, iclass 38, count 0 2006.162.08:13:23.78#ibcon#read 3, iclass 38, count 0 2006.162.08:13:23.78#ibcon#about to read 4, iclass 38, count 0 2006.162.08:13:23.78#ibcon#read 4, iclass 38, count 0 2006.162.08:13:23.78#ibcon#about to read 5, iclass 38, count 0 2006.162.08:13:23.78#ibcon#read 5, iclass 38, count 0 2006.162.08:13:23.78#ibcon#about to read 6, iclass 38, count 0 2006.162.08:13:23.78#ibcon#read 6, iclass 38, count 0 2006.162.08:13:23.78#ibcon#end of sib2, iclass 38, count 0 2006.162.08:13:23.78#ibcon#*mode == 0, iclass 38, count 0 2006.162.08:13:23.78#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.162.08:13:23.78#ibcon#[27=USB\r\n] 2006.162.08:13:23.78#ibcon#*before write, iclass 38, count 0 2006.162.08:13:23.78#ibcon#enter sib2, iclass 38, count 0 2006.162.08:13:23.78#ibcon#flushed, iclass 38, count 0 2006.162.08:13:23.78#ibcon#about to write, iclass 38, count 0 2006.162.08:13:23.78#ibcon#wrote, iclass 38, count 0 2006.162.08:13:23.78#ibcon#about to read 3, iclass 38, count 0 2006.162.08:13:23.81#ibcon#read 3, iclass 38, count 0 2006.162.08:13:23.81#ibcon#about to read 4, iclass 38, count 0 2006.162.08:13:23.81#ibcon#read 4, iclass 38, count 0 2006.162.08:13:23.81#ibcon#about to read 5, iclass 38, count 0 2006.162.08:13:23.81#ibcon#read 5, iclass 38, count 0 2006.162.08:13:23.81#ibcon#about to read 6, iclass 38, count 0 2006.162.08:13:23.81#ibcon#read 6, iclass 38, count 0 2006.162.08:13:23.81#ibcon#end of sib2, iclass 38, count 0 2006.162.08:13:23.81#ibcon#*after write, iclass 38, count 0 2006.162.08:13:23.81#ibcon#*before return 0, iclass 38, count 0 2006.162.08:13:23.81#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.162.08:13:23.81#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.162.08:13:23.81#ibcon#about to clear, iclass 38 cls_cnt 0 2006.162.08:13:23.81#ibcon#cleared, iclass 38 cls_cnt 0 2006.162.08:13:23.81$vc4f8/vblo=5,744.99 2006.162.08:13:23.81#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.162.08:13:23.81#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.162.08:13:23.81#ibcon#ireg 17 cls_cnt 0 2006.162.08:13:23.81#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:13:23.81#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:13:23.81#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:13:23.81#ibcon#enter wrdev, iclass 40, count 0 2006.162.08:13:23.81#ibcon#first serial, iclass 40, count 0 2006.162.08:13:23.81#ibcon#enter sib2, iclass 40, count 0 2006.162.08:13:23.81#ibcon#flushed, iclass 40, count 0 2006.162.08:13:23.81#ibcon#about to write, iclass 40, count 0 2006.162.08:13:23.81#ibcon#wrote, iclass 40, count 0 2006.162.08:13:23.81#ibcon#about to read 3, iclass 40, count 0 2006.162.08:13:23.83#ibcon#read 3, iclass 40, count 0 2006.162.08:13:23.83#ibcon#about to read 4, iclass 40, count 0 2006.162.08:13:23.83#ibcon#read 4, iclass 40, count 0 2006.162.08:13:23.83#ibcon#about to read 5, iclass 40, count 0 2006.162.08:13:23.83#ibcon#read 5, iclass 40, count 0 2006.162.08:13:23.83#ibcon#about to read 6, iclass 40, count 0 2006.162.08:13:23.83#ibcon#read 6, iclass 40, count 0 2006.162.08:13:23.83#ibcon#end of sib2, iclass 40, count 0 2006.162.08:13:23.83#ibcon#*mode == 0, iclass 40, count 0 2006.162.08:13:23.83#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.162.08:13:23.83#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.08:13:23.83#ibcon#*before write, iclass 40, count 0 2006.162.08:13:23.83#ibcon#enter sib2, iclass 40, count 0 2006.162.08:13:23.83#ibcon#flushed, iclass 40, count 0 2006.162.08:13:23.83#ibcon#about to write, iclass 40, count 0 2006.162.08:13:23.83#ibcon#wrote, iclass 40, count 0 2006.162.08:13:23.83#ibcon#about to read 3, iclass 40, count 0 2006.162.08:13:23.87#ibcon#read 3, iclass 40, count 0 2006.162.08:13:23.87#ibcon#about to read 4, iclass 40, count 0 2006.162.08:13:23.87#ibcon#read 4, iclass 40, count 0 2006.162.08:13:23.87#ibcon#about to read 5, iclass 40, count 0 2006.162.08:13:23.87#ibcon#read 5, iclass 40, count 0 2006.162.08:13:23.87#ibcon#about to read 6, iclass 40, count 0 2006.162.08:13:23.87#ibcon#read 6, iclass 40, count 0 2006.162.08:13:23.87#ibcon#end of sib2, iclass 40, count 0 2006.162.08:13:23.87#ibcon#*after write, iclass 40, count 0 2006.162.08:13:23.87#ibcon#*before return 0, iclass 40, count 0 2006.162.08:13:23.87#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:13:23.87#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:13:23.87#ibcon#about to clear, iclass 40 cls_cnt 0 2006.162.08:13:23.87#ibcon#cleared, iclass 40 cls_cnt 0 2006.162.08:13:23.87$vc4f8/vb=5,4 2006.162.08:13:23.87#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.162.08:13:23.87#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.162.08:13:23.87#ibcon#ireg 11 cls_cnt 2 2006.162.08:13:23.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:13:23.93#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:13:23.93#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:13:23.93#ibcon#enter wrdev, iclass 4, count 2 2006.162.08:13:23.93#ibcon#first serial, iclass 4, count 2 2006.162.08:13:23.93#ibcon#enter sib2, iclass 4, count 2 2006.162.08:13:23.93#ibcon#flushed, iclass 4, count 2 2006.162.08:13:23.93#ibcon#about to write, iclass 4, count 2 2006.162.08:13:23.93#ibcon#wrote, iclass 4, count 2 2006.162.08:13:23.93#ibcon#about to read 3, iclass 4, count 2 2006.162.08:13:23.95#ibcon#read 3, iclass 4, count 2 2006.162.08:13:23.95#ibcon#about to read 4, iclass 4, count 2 2006.162.08:13:23.95#ibcon#read 4, iclass 4, count 2 2006.162.08:13:23.95#ibcon#about to read 5, iclass 4, count 2 2006.162.08:13:23.95#ibcon#read 5, iclass 4, count 2 2006.162.08:13:23.95#ibcon#about to read 6, iclass 4, count 2 2006.162.08:13:23.95#ibcon#read 6, iclass 4, count 2 2006.162.08:13:23.95#ibcon#end of sib2, iclass 4, count 2 2006.162.08:13:23.95#ibcon#*mode == 0, iclass 4, count 2 2006.162.08:13:23.95#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.162.08:13:23.95#ibcon#[27=AT05-04\r\n] 2006.162.08:13:23.95#ibcon#*before write, iclass 4, count 2 2006.162.08:13:23.95#ibcon#enter sib2, iclass 4, count 2 2006.162.08:13:23.95#ibcon#flushed, iclass 4, count 2 2006.162.08:13:23.95#ibcon#about to write, iclass 4, count 2 2006.162.08:13:23.95#ibcon#wrote, iclass 4, count 2 2006.162.08:13:23.95#ibcon#about to read 3, iclass 4, count 2 2006.162.08:13:23.98#ibcon#read 3, iclass 4, count 2 2006.162.08:13:23.98#ibcon#about to read 4, iclass 4, count 2 2006.162.08:13:23.98#ibcon#read 4, iclass 4, count 2 2006.162.08:13:23.98#ibcon#about to read 5, iclass 4, count 2 2006.162.08:13:23.98#ibcon#read 5, iclass 4, count 2 2006.162.08:13:23.98#ibcon#about to read 6, iclass 4, count 2 2006.162.08:13:23.98#ibcon#read 6, iclass 4, count 2 2006.162.08:13:23.98#ibcon#end of sib2, iclass 4, count 2 2006.162.08:13:23.98#ibcon#*after write, iclass 4, count 2 2006.162.08:13:23.98#ibcon#*before return 0, iclass 4, count 2 2006.162.08:13:23.98#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:13:23.98#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:13:23.98#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.162.08:13:23.98#ibcon#ireg 7 cls_cnt 0 2006.162.08:13:23.98#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:13:24.10#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:13:24.10#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:13:24.10#ibcon#enter wrdev, iclass 4, count 0 2006.162.08:13:24.10#ibcon#first serial, iclass 4, count 0 2006.162.08:13:24.10#ibcon#enter sib2, iclass 4, count 0 2006.162.08:13:24.10#ibcon#flushed, iclass 4, count 0 2006.162.08:13:24.10#ibcon#about to write, iclass 4, count 0 2006.162.08:13:24.10#ibcon#wrote, iclass 4, count 0 2006.162.08:13:24.10#ibcon#about to read 3, iclass 4, count 0 2006.162.08:13:24.12#ibcon#read 3, iclass 4, count 0 2006.162.08:13:24.12#ibcon#about to read 4, iclass 4, count 0 2006.162.08:13:24.12#ibcon#read 4, iclass 4, count 0 2006.162.08:13:24.12#ibcon#about to read 5, iclass 4, count 0 2006.162.08:13:24.12#ibcon#read 5, iclass 4, count 0 2006.162.08:13:24.12#ibcon#about to read 6, iclass 4, count 0 2006.162.08:13:24.12#ibcon#read 6, iclass 4, count 0 2006.162.08:13:24.12#ibcon#end of sib2, iclass 4, count 0 2006.162.08:13:24.12#ibcon#*mode == 0, iclass 4, count 0 2006.162.08:13:24.12#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.162.08:13:24.12#ibcon#[27=USB\r\n] 2006.162.08:13:24.12#ibcon#*before write, iclass 4, count 0 2006.162.08:13:24.12#ibcon#enter sib2, iclass 4, count 0 2006.162.08:13:24.12#ibcon#flushed, iclass 4, count 0 2006.162.08:13:24.12#ibcon#about to write, iclass 4, count 0 2006.162.08:13:24.12#ibcon#wrote, iclass 4, count 0 2006.162.08:13:24.12#ibcon#about to read 3, iclass 4, count 0 2006.162.08:13:24.15#ibcon#read 3, iclass 4, count 0 2006.162.08:13:24.15#ibcon#about to read 4, iclass 4, count 0 2006.162.08:13:24.15#ibcon#read 4, iclass 4, count 0 2006.162.08:13:24.15#ibcon#about to read 5, iclass 4, count 0 2006.162.08:13:24.15#ibcon#read 5, iclass 4, count 0 2006.162.08:13:24.15#ibcon#about to read 6, iclass 4, count 0 2006.162.08:13:24.15#ibcon#read 6, iclass 4, count 0 2006.162.08:13:24.15#ibcon#end of sib2, iclass 4, count 0 2006.162.08:13:24.15#ibcon#*after write, iclass 4, count 0 2006.162.08:13:24.15#ibcon#*before return 0, iclass 4, count 0 2006.162.08:13:24.15#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:13:24.15#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:13:24.15#ibcon#about to clear, iclass 4 cls_cnt 0 2006.162.08:13:24.15#ibcon#cleared, iclass 4 cls_cnt 0 2006.162.08:13:24.15$vc4f8/vblo=6,752.99 2006.162.08:13:24.15#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.162.08:13:24.15#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.162.08:13:24.15#ibcon#ireg 17 cls_cnt 0 2006.162.08:13:24.15#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:13:24.15#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:13:24.15#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:13:24.15#ibcon#enter wrdev, iclass 6, count 0 2006.162.08:13:24.15#ibcon#first serial, iclass 6, count 0 2006.162.08:13:24.15#ibcon#enter sib2, iclass 6, count 0 2006.162.08:13:24.15#ibcon#flushed, iclass 6, count 0 2006.162.08:13:24.15#ibcon#about to write, iclass 6, count 0 2006.162.08:13:24.15#ibcon#wrote, iclass 6, count 0 2006.162.08:13:24.15#ibcon#about to read 3, iclass 6, count 0 2006.162.08:13:24.17#ibcon#read 3, iclass 6, count 0 2006.162.08:13:24.17#ibcon#about to read 4, iclass 6, count 0 2006.162.08:13:24.17#ibcon#read 4, iclass 6, count 0 2006.162.08:13:24.17#ibcon#about to read 5, iclass 6, count 0 2006.162.08:13:24.17#ibcon#read 5, iclass 6, count 0 2006.162.08:13:24.17#ibcon#about to read 6, iclass 6, count 0 2006.162.08:13:24.17#ibcon#read 6, iclass 6, count 0 2006.162.08:13:24.17#ibcon#end of sib2, iclass 6, count 0 2006.162.08:13:24.17#ibcon#*mode == 0, iclass 6, count 0 2006.162.08:13:24.17#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.162.08:13:24.17#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.08:13:24.17#ibcon#*before write, iclass 6, count 0 2006.162.08:13:24.17#ibcon#enter sib2, iclass 6, count 0 2006.162.08:13:24.17#ibcon#flushed, iclass 6, count 0 2006.162.08:13:24.17#ibcon#about to write, iclass 6, count 0 2006.162.08:13:24.17#ibcon#wrote, iclass 6, count 0 2006.162.08:13:24.17#ibcon#about to read 3, iclass 6, count 0 2006.162.08:13:24.21#ibcon#read 3, iclass 6, count 0 2006.162.08:13:24.21#ibcon#about to read 4, iclass 6, count 0 2006.162.08:13:24.21#ibcon#read 4, iclass 6, count 0 2006.162.08:13:24.21#ibcon#about to read 5, iclass 6, count 0 2006.162.08:13:24.21#ibcon#read 5, iclass 6, count 0 2006.162.08:13:24.21#ibcon#about to read 6, iclass 6, count 0 2006.162.08:13:24.21#ibcon#read 6, iclass 6, count 0 2006.162.08:13:24.21#ibcon#end of sib2, iclass 6, count 0 2006.162.08:13:24.21#ibcon#*after write, iclass 6, count 0 2006.162.08:13:24.21#ibcon#*before return 0, iclass 6, count 0 2006.162.08:13:24.21#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:13:24.21#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:13:24.21#ibcon#about to clear, iclass 6 cls_cnt 0 2006.162.08:13:24.21#ibcon#cleared, iclass 6 cls_cnt 0 2006.162.08:13:24.21$vc4f8/vb=6,4 2006.162.08:13:24.21#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.162.08:13:24.21#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.162.08:13:24.21#ibcon#ireg 11 cls_cnt 2 2006.162.08:13:24.21#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:13:24.27#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:13:24.27#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:13:24.27#ibcon#enter wrdev, iclass 10, count 2 2006.162.08:13:24.27#ibcon#first serial, iclass 10, count 2 2006.162.08:13:24.27#ibcon#enter sib2, iclass 10, count 2 2006.162.08:13:24.27#ibcon#flushed, iclass 10, count 2 2006.162.08:13:24.27#ibcon#about to write, iclass 10, count 2 2006.162.08:13:24.27#ibcon#wrote, iclass 10, count 2 2006.162.08:13:24.27#ibcon#about to read 3, iclass 10, count 2 2006.162.08:13:24.29#ibcon#read 3, iclass 10, count 2 2006.162.08:13:24.29#ibcon#about to read 4, iclass 10, count 2 2006.162.08:13:24.29#ibcon#read 4, iclass 10, count 2 2006.162.08:13:24.29#ibcon#about to read 5, iclass 10, count 2 2006.162.08:13:24.29#ibcon#read 5, iclass 10, count 2 2006.162.08:13:24.29#ibcon#about to read 6, iclass 10, count 2 2006.162.08:13:24.29#ibcon#read 6, iclass 10, count 2 2006.162.08:13:24.29#ibcon#end of sib2, iclass 10, count 2 2006.162.08:13:24.29#ibcon#*mode == 0, iclass 10, count 2 2006.162.08:13:24.29#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.162.08:13:24.29#ibcon#[27=AT06-04\r\n] 2006.162.08:13:24.29#ibcon#*before write, iclass 10, count 2 2006.162.08:13:24.29#ibcon#enter sib2, iclass 10, count 2 2006.162.08:13:24.29#ibcon#flushed, iclass 10, count 2 2006.162.08:13:24.29#ibcon#about to write, iclass 10, count 2 2006.162.08:13:24.29#ibcon#wrote, iclass 10, count 2 2006.162.08:13:24.29#ibcon#about to read 3, iclass 10, count 2 2006.162.08:13:24.32#ibcon#read 3, iclass 10, count 2 2006.162.08:13:24.32#ibcon#about to read 4, iclass 10, count 2 2006.162.08:13:24.32#ibcon#read 4, iclass 10, count 2 2006.162.08:13:24.32#ibcon#about to read 5, iclass 10, count 2 2006.162.08:13:24.32#ibcon#read 5, iclass 10, count 2 2006.162.08:13:24.32#ibcon#about to read 6, iclass 10, count 2 2006.162.08:13:24.32#ibcon#read 6, iclass 10, count 2 2006.162.08:13:24.32#ibcon#end of sib2, iclass 10, count 2 2006.162.08:13:24.32#ibcon#*after write, iclass 10, count 2 2006.162.08:13:24.32#ibcon#*before return 0, iclass 10, count 2 2006.162.08:13:24.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:13:24.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:13:24.32#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.162.08:13:24.32#ibcon#ireg 7 cls_cnt 0 2006.162.08:13:24.32#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:13:24.44#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:13:24.44#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:13:24.44#ibcon#enter wrdev, iclass 10, count 0 2006.162.08:13:24.44#ibcon#first serial, iclass 10, count 0 2006.162.08:13:24.44#ibcon#enter sib2, iclass 10, count 0 2006.162.08:13:24.44#ibcon#flushed, iclass 10, count 0 2006.162.08:13:24.44#ibcon#about to write, iclass 10, count 0 2006.162.08:13:24.44#ibcon#wrote, iclass 10, count 0 2006.162.08:13:24.44#ibcon#about to read 3, iclass 10, count 0 2006.162.08:13:24.46#ibcon#read 3, iclass 10, count 0 2006.162.08:13:24.46#ibcon#about to read 4, iclass 10, count 0 2006.162.08:13:24.46#ibcon#read 4, iclass 10, count 0 2006.162.08:13:24.46#ibcon#about to read 5, iclass 10, count 0 2006.162.08:13:24.46#ibcon#read 5, iclass 10, count 0 2006.162.08:13:24.46#ibcon#about to read 6, iclass 10, count 0 2006.162.08:13:24.46#ibcon#read 6, iclass 10, count 0 2006.162.08:13:24.46#ibcon#end of sib2, iclass 10, count 0 2006.162.08:13:24.46#ibcon#*mode == 0, iclass 10, count 0 2006.162.08:13:24.46#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.162.08:13:24.46#ibcon#[27=USB\r\n] 2006.162.08:13:24.46#ibcon#*before write, iclass 10, count 0 2006.162.08:13:24.46#ibcon#enter sib2, iclass 10, count 0 2006.162.08:13:24.46#ibcon#flushed, iclass 10, count 0 2006.162.08:13:24.46#ibcon#about to write, iclass 10, count 0 2006.162.08:13:24.46#ibcon#wrote, iclass 10, count 0 2006.162.08:13:24.46#ibcon#about to read 3, iclass 10, count 0 2006.162.08:13:24.49#ibcon#read 3, iclass 10, count 0 2006.162.08:13:24.49#ibcon#about to read 4, iclass 10, count 0 2006.162.08:13:24.49#ibcon#read 4, iclass 10, count 0 2006.162.08:13:24.49#ibcon#about to read 5, iclass 10, count 0 2006.162.08:13:24.49#ibcon#read 5, iclass 10, count 0 2006.162.08:13:24.49#ibcon#about to read 6, iclass 10, count 0 2006.162.08:13:24.49#ibcon#read 6, iclass 10, count 0 2006.162.08:13:24.49#ibcon#end of sib2, iclass 10, count 0 2006.162.08:13:24.49#ibcon#*after write, iclass 10, count 0 2006.162.08:13:24.49#ibcon#*before return 0, iclass 10, count 0 2006.162.08:13:24.49#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:13:24.49#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:13:24.49#ibcon#about to clear, iclass 10 cls_cnt 0 2006.162.08:13:24.49#ibcon#cleared, iclass 10 cls_cnt 0 2006.162.08:13:24.49$vc4f8/vabw=wide 2006.162.08:13:24.49#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.162.08:13:24.49#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.162.08:13:24.49#ibcon#ireg 8 cls_cnt 0 2006.162.08:13:24.49#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:13:24.49#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:13:24.49#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:13:24.49#ibcon#enter wrdev, iclass 12, count 0 2006.162.08:13:24.49#ibcon#first serial, iclass 12, count 0 2006.162.08:13:24.49#ibcon#enter sib2, iclass 12, count 0 2006.162.08:13:24.49#ibcon#flushed, iclass 12, count 0 2006.162.08:13:24.49#ibcon#about to write, iclass 12, count 0 2006.162.08:13:24.49#ibcon#wrote, iclass 12, count 0 2006.162.08:13:24.49#ibcon#about to read 3, iclass 12, count 0 2006.162.08:13:24.51#ibcon#read 3, iclass 12, count 0 2006.162.08:13:24.51#ibcon#about to read 4, iclass 12, count 0 2006.162.08:13:24.51#ibcon#read 4, iclass 12, count 0 2006.162.08:13:24.51#ibcon#about to read 5, iclass 12, count 0 2006.162.08:13:24.51#ibcon#read 5, iclass 12, count 0 2006.162.08:13:24.51#ibcon#about to read 6, iclass 12, count 0 2006.162.08:13:24.51#ibcon#read 6, iclass 12, count 0 2006.162.08:13:24.51#ibcon#end of sib2, iclass 12, count 0 2006.162.08:13:24.51#ibcon#*mode == 0, iclass 12, count 0 2006.162.08:13:24.51#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.162.08:13:24.51#ibcon#[25=BW32\r\n] 2006.162.08:13:24.51#ibcon#*before write, iclass 12, count 0 2006.162.08:13:24.51#ibcon#enter sib2, iclass 12, count 0 2006.162.08:13:24.51#ibcon#flushed, iclass 12, count 0 2006.162.08:13:24.51#ibcon#about to write, iclass 12, count 0 2006.162.08:13:24.51#ibcon#wrote, iclass 12, count 0 2006.162.08:13:24.51#ibcon#about to read 3, iclass 12, count 0 2006.162.08:13:24.54#ibcon#read 3, iclass 12, count 0 2006.162.08:13:24.54#ibcon#about to read 4, iclass 12, count 0 2006.162.08:13:24.54#ibcon#read 4, iclass 12, count 0 2006.162.08:13:24.54#ibcon#about to read 5, iclass 12, count 0 2006.162.08:13:24.54#ibcon#read 5, iclass 12, count 0 2006.162.08:13:24.54#ibcon#about to read 6, iclass 12, count 0 2006.162.08:13:24.54#ibcon#read 6, iclass 12, count 0 2006.162.08:13:24.54#ibcon#end of sib2, iclass 12, count 0 2006.162.08:13:24.54#ibcon#*after write, iclass 12, count 0 2006.162.08:13:24.54#ibcon#*before return 0, iclass 12, count 0 2006.162.08:13:24.54#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:13:24.54#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:13:24.54#ibcon#about to clear, iclass 12 cls_cnt 0 2006.162.08:13:24.54#ibcon#cleared, iclass 12 cls_cnt 0 2006.162.08:13:24.54$vc4f8/vbbw=wide 2006.162.08:13:24.54#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.162.08:13:24.54#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.162.08:13:24.54#ibcon#ireg 8 cls_cnt 0 2006.162.08:13:24.54#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:13:24.61#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:13:24.61#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:13:24.61#ibcon#enter wrdev, iclass 14, count 0 2006.162.08:13:24.61#ibcon#first serial, iclass 14, count 0 2006.162.08:13:24.61#ibcon#enter sib2, iclass 14, count 0 2006.162.08:13:24.61#ibcon#flushed, iclass 14, count 0 2006.162.08:13:24.61#ibcon#about to write, iclass 14, count 0 2006.162.08:13:24.61#ibcon#wrote, iclass 14, count 0 2006.162.08:13:24.61#ibcon#about to read 3, iclass 14, count 0 2006.162.08:13:24.63#ibcon#read 3, iclass 14, count 0 2006.162.08:13:24.63#ibcon#about to read 4, iclass 14, count 0 2006.162.08:13:24.63#ibcon#read 4, iclass 14, count 0 2006.162.08:13:24.63#ibcon#about to read 5, iclass 14, count 0 2006.162.08:13:24.63#ibcon#read 5, iclass 14, count 0 2006.162.08:13:24.63#ibcon#about to read 6, iclass 14, count 0 2006.162.08:13:24.63#ibcon#read 6, iclass 14, count 0 2006.162.08:13:24.63#ibcon#end of sib2, iclass 14, count 0 2006.162.08:13:24.63#ibcon#*mode == 0, iclass 14, count 0 2006.162.08:13:24.63#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.08:13:24.63#ibcon#[27=BW32\r\n] 2006.162.08:13:24.63#ibcon#*before write, iclass 14, count 0 2006.162.08:13:24.63#ibcon#enter sib2, iclass 14, count 0 2006.162.08:13:24.63#ibcon#flushed, iclass 14, count 0 2006.162.08:13:24.63#ibcon#about to write, iclass 14, count 0 2006.162.08:13:24.63#ibcon#wrote, iclass 14, count 0 2006.162.08:13:24.63#ibcon#about to read 3, iclass 14, count 0 2006.162.08:13:24.66#ibcon#read 3, iclass 14, count 0 2006.162.08:13:24.66#ibcon#about to read 4, iclass 14, count 0 2006.162.08:13:24.66#ibcon#read 4, iclass 14, count 0 2006.162.08:13:24.66#ibcon#about to read 5, iclass 14, count 0 2006.162.08:13:24.66#ibcon#read 5, iclass 14, count 0 2006.162.08:13:24.66#ibcon#about to read 6, iclass 14, count 0 2006.162.08:13:24.66#ibcon#read 6, iclass 14, count 0 2006.162.08:13:24.66#ibcon#end of sib2, iclass 14, count 0 2006.162.08:13:24.66#ibcon#*after write, iclass 14, count 0 2006.162.08:13:24.66#ibcon#*before return 0, iclass 14, count 0 2006.162.08:13:24.66#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:13:24.66#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:13:24.66#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.08:13:24.66#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.08:13:24.66$4f8m12a/ifd4f 2006.162.08:13:24.66$ifd4f/lo= 2006.162.08:13:24.66$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.08:13:24.66$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.08:13:24.66$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.08:13:24.66$ifd4f/patch= 2006.162.08:13:24.66$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.08:13:24.66$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.08:13:24.66$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.08:13:24.66$4f8m12a/"form=m,16.000,1:2 2006.162.08:13:24.66$4f8m12a/"tpicd 2006.162.08:13:24.66$4f8m12a/echo=off 2006.162.08:13:24.66$4f8m12a/xlog=off 2006.162.08:13:24.66:!2006.162.08:14:10 2006.162.08:13:49.14#trakl#Source acquired 2006.162.08:13:49.14#flagr#flagr/antenna,acquired 2006.162.08:14:10.00:preob 2006.162.08:14:11.14/onsource/TRACKING 2006.162.08:14:11.14:!2006.162.08:14:20 2006.162.08:14:20.00:data_valid=on 2006.162.08:14:20.00:midob 2006.162.08:14:20.14/onsource/TRACKING 2006.162.08:14:20.14/wx/17.89,1007.1,100 2006.162.08:14:20.21/cable/+6.5356E-03 2006.162.08:14:21.30/va/01,08,usb,yes,43,45 2006.162.08:14:21.30/va/02,07,usb,yes,44,45 2006.162.08:14:21.30/va/03,06,usb,yes,46,46 2006.162.08:14:21.30/va/04,07,usb,yes,45,48 2006.162.08:14:21.30/va/05,07,usb,yes,48,51 2006.162.08:14:21.30/va/06,06,usb,yes,47,47 2006.162.08:14:21.30/va/07,06,usb,yes,48,47 2006.162.08:14:21.30/va/08,07,usb,yes,45,45 2006.162.08:14:21.53/valo/01,532.99,yes,locked 2006.162.08:14:21.53/valo/02,572.99,yes,locked 2006.162.08:14:21.53/valo/03,672.99,yes,locked 2006.162.08:14:21.53/valo/04,832.99,yes,locked 2006.162.08:14:21.53/valo/05,652.99,yes,locked 2006.162.08:14:21.53/valo/06,772.99,yes,locked 2006.162.08:14:21.53/valo/07,832.99,yes,locked 2006.162.08:14:21.53/valo/08,852.99,yes,locked 2006.162.08:14:22.62/vb/01,04,usb,yes,33,31 2006.162.08:14:22.62/vb/02,04,usb,yes,35,36 2006.162.08:14:22.62/vb/03,04,usb,yes,31,35 2006.162.08:14:22.62/vb/04,04,usb,yes,32,32 2006.162.08:14:22.62/vb/05,04,usb,yes,30,35 2006.162.08:14:22.62/vb/06,04,usb,yes,32,35 2006.162.08:14:22.62/vb/07,04,usb,yes,34,34 2006.162.08:14:22.62/vb/08,04,usb,yes,31,35 2006.162.08:14:22.85/vblo/01,632.99,yes,locked 2006.162.08:14:22.85/vblo/02,640.99,yes,locked 2006.162.08:14:22.85/vblo/03,656.99,yes,locked 2006.162.08:14:22.85/vblo/04,712.99,yes,locked 2006.162.08:14:22.85/vblo/05,744.99,yes,locked 2006.162.08:14:22.85/vblo/06,752.99,yes,locked 2006.162.08:14:22.85/vblo/07,734.99,yes,locked 2006.162.08:14:22.85/vblo/08,744.99,yes,locked 2006.162.08:14:23.00/vabw/8 2006.162.08:14:23.15/vbbw/8 2006.162.08:14:23.24/xfe/off,on,15.2 2006.162.08:14:23.61/ifatt/23,28,28,28 2006.162.08:14:24.08/fmout-gps/S +4.50E-07 2006.162.08:14:24.12:!2006.162.08:15:20 2006.162.08:15:20.00:data_valid=off 2006.162.08:15:20.00:postob 2006.162.08:15:20.13/cable/+6.5356E-03 2006.162.08:15:20.13/wx/17.91,1007.0,100 2006.162.08:15:21.07/fmout-gps/S +4.50E-07 2006.162.08:15:21.07:scan_name=162-0816,k06162,60 2006.162.08:15:21.07:source=3c371,180650.68,694928.1,2000.0,cw 2006.162.08:15:21.13#flagr#flagr/antenna,new-source 2006.162.08:15:22.13:checkk5 2006.162.08:15:22.57/chk_autoobs//k5ts1/ autoobs is running! 2006.162.08:15:23.02/chk_autoobs//k5ts2/ autoobs is running! 2006.162.08:15:23.45/chk_autoobs//k5ts3/ autoobs is running! 2006.162.08:15:23.89/chk_autoobs//k5ts4/ autoobs is running! 2006.162.08:15:24.32/chk_obsdata//k5ts1/T1620814??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:15:24.76/chk_obsdata//k5ts2/T1620814??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:15:25.20/chk_obsdata//k5ts3/T1620814??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:15:25.67/chk_obsdata//k5ts4/T1620814??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:15:26.57/k5log//k5ts1_log_newline 2006.162.08:15:27.32/k5log//k5ts2_log_newline 2006.162.08:15:28.13/k5log//k5ts3_log_newline 2006.162.08:15:28.89/k5log//k5ts4_log_newline 2006.162.08:15:28.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.08:15:28.92:4f8m12a=2 2006.162.08:15:28.92$4f8m12a/echo=on 2006.162.08:15:28.92$4f8m12a/pcalon 2006.162.08:15:28.92$pcalon/"no phase cal control is implemented here 2006.162.08:15:28.92$4f8m12a/"tpicd=stop 2006.162.08:15:28.92$4f8m12a/vc4f8 2006.162.08:15:28.92$vc4f8/valo=1,532.99 2006.162.08:15:28.93#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.162.08:15:28.93#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.162.08:15:28.93#ibcon#ireg 17 cls_cnt 0 2006.162.08:15:28.93#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:15:28.93#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:15:28.93#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:15:28.93#ibcon#enter wrdev, iclass 24, count 0 2006.162.08:15:28.93#ibcon#first serial, iclass 24, count 0 2006.162.08:15:28.93#ibcon#enter sib2, iclass 24, count 0 2006.162.08:15:28.93#ibcon#flushed, iclass 24, count 0 2006.162.08:15:28.93#ibcon#about to write, iclass 24, count 0 2006.162.08:15:28.93#ibcon#wrote, iclass 24, count 0 2006.162.08:15:28.93#ibcon#about to read 3, iclass 24, count 0 2006.162.08:15:28.97#ibcon#read 3, iclass 24, count 0 2006.162.08:15:28.97#ibcon#about to read 4, iclass 24, count 0 2006.162.08:15:28.97#ibcon#read 4, iclass 24, count 0 2006.162.08:15:28.97#ibcon#about to read 5, iclass 24, count 0 2006.162.08:15:28.97#ibcon#read 5, iclass 24, count 0 2006.162.08:15:28.97#ibcon#about to read 6, iclass 24, count 0 2006.162.08:15:28.97#ibcon#read 6, iclass 24, count 0 2006.162.08:15:28.97#ibcon#end of sib2, iclass 24, count 0 2006.162.08:15:28.97#ibcon#*mode == 0, iclass 24, count 0 2006.162.08:15:28.97#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.08:15:28.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.08:15:28.97#ibcon#*before write, iclass 24, count 0 2006.162.08:15:28.97#ibcon#enter sib2, iclass 24, count 0 2006.162.08:15:28.97#ibcon#flushed, iclass 24, count 0 2006.162.08:15:28.97#ibcon#about to write, iclass 24, count 0 2006.162.08:15:28.97#ibcon#wrote, iclass 24, count 0 2006.162.08:15:28.97#ibcon#about to read 3, iclass 24, count 0 2006.162.08:15:29.01#ibcon#read 3, iclass 24, count 0 2006.162.08:15:29.01#ibcon#about to read 4, iclass 24, count 0 2006.162.08:15:29.01#ibcon#read 4, iclass 24, count 0 2006.162.08:15:29.01#ibcon#about to read 5, iclass 24, count 0 2006.162.08:15:29.01#ibcon#read 5, iclass 24, count 0 2006.162.08:15:29.01#ibcon#about to read 6, iclass 24, count 0 2006.162.08:15:29.01#ibcon#read 6, iclass 24, count 0 2006.162.08:15:29.01#ibcon#end of sib2, iclass 24, count 0 2006.162.08:15:29.01#ibcon#*after write, iclass 24, count 0 2006.162.08:15:29.01#ibcon#*before return 0, iclass 24, count 0 2006.162.08:15:29.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:15:29.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:15:29.01#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.08:15:29.01#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.08:15:29.01$vc4f8/va=1,8 2006.162.08:15:29.01#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.162.08:15:29.01#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.162.08:15:29.01#ibcon#ireg 11 cls_cnt 2 2006.162.08:15:29.01#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:15:29.01#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:15:29.01#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:15:29.01#ibcon#enter wrdev, iclass 26, count 2 2006.162.08:15:29.01#ibcon#first serial, iclass 26, count 2 2006.162.08:15:29.01#ibcon#enter sib2, iclass 26, count 2 2006.162.08:15:29.01#ibcon#flushed, iclass 26, count 2 2006.162.08:15:29.01#ibcon#about to write, iclass 26, count 2 2006.162.08:15:29.01#ibcon#wrote, iclass 26, count 2 2006.162.08:15:29.01#ibcon#about to read 3, iclass 26, count 2 2006.162.08:15:29.03#ibcon#read 3, iclass 26, count 2 2006.162.08:15:29.03#ibcon#about to read 4, iclass 26, count 2 2006.162.08:15:29.03#ibcon#read 4, iclass 26, count 2 2006.162.08:15:29.03#ibcon#about to read 5, iclass 26, count 2 2006.162.08:15:29.03#ibcon#read 5, iclass 26, count 2 2006.162.08:15:29.03#ibcon#about to read 6, iclass 26, count 2 2006.162.08:15:29.03#ibcon#read 6, iclass 26, count 2 2006.162.08:15:29.03#ibcon#end of sib2, iclass 26, count 2 2006.162.08:15:29.03#ibcon#*mode == 0, iclass 26, count 2 2006.162.08:15:29.03#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.162.08:15:29.03#ibcon#[25=AT01-08\r\n] 2006.162.08:15:29.03#ibcon#*before write, iclass 26, count 2 2006.162.08:15:29.03#ibcon#enter sib2, iclass 26, count 2 2006.162.08:15:29.03#ibcon#flushed, iclass 26, count 2 2006.162.08:15:29.03#ibcon#about to write, iclass 26, count 2 2006.162.08:15:29.03#ibcon#wrote, iclass 26, count 2 2006.162.08:15:29.03#ibcon#about to read 3, iclass 26, count 2 2006.162.08:15:29.06#ibcon#read 3, iclass 26, count 2 2006.162.08:15:29.06#ibcon#about to read 4, iclass 26, count 2 2006.162.08:15:29.06#ibcon#read 4, iclass 26, count 2 2006.162.08:15:29.06#ibcon#about to read 5, iclass 26, count 2 2006.162.08:15:29.06#ibcon#read 5, iclass 26, count 2 2006.162.08:15:29.06#ibcon#about to read 6, iclass 26, count 2 2006.162.08:15:29.06#ibcon#read 6, iclass 26, count 2 2006.162.08:15:29.06#ibcon#end of sib2, iclass 26, count 2 2006.162.08:15:29.06#ibcon#*after write, iclass 26, count 2 2006.162.08:15:29.06#ibcon#*before return 0, iclass 26, count 2 2006.162.08:15:29.06#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:15:29.06#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:15:29.06#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.162.08:15:29.06#ibcon#ireg 7 cls_cnt 0 2006.162.08:15:29.06#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:15:29.18#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:15:29.18#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:15:29.18#ibcon#enter wrdev, iclass 26, count 0 2006.162.08:15:29.18#ibcon#first serial, iclass 26, count 0 2006.162.08:15:29.18#ibcon#enter sib2, iclass 26, count 0 2006.162.08:15:29.18#ibcon#flushed, iclass 26, count 0 2006.162.08:15:29.18#ibcon#about to write, iclass 26, count 0 2006.162.08:15:29.18#ibcon#wrote, iclass 26, count 0 2006.162.08:15:29.18#ibcon#about to read 3, iclass 26, count 0 2006.162.08:15:29.20#ibcon#read 3, iclass 26, count 0 2006.162.08:15:29.20#ibcon#about to read 4, iclass 26, count 0 2006.162.08:15:29.20#ibcon#read 4, iclass 26, count 0 2006.162.08:15:29.20#ibcon#about to read 5, iclass 26, count 0 2006.162.08:15:29.20#ibcon#read 5, iclass 26, count 0 2006.162.08:15:29.20#ibcon#about to read 6, iclass 26, count 0 2006.162.08:15:29.20#ibcon#read 6, iclass 26, count 0 2006.162.08:15:29.20#ibcon#end of sib2, iclass 26, count 0 2006.162.08:15:29.20#ibcon#*mode == 0, iclass 26, count 0 2006.162.08:15:29.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.162.08:15:29.20#ibcon#[25=USB\r\n] 2006.162.08:15:29.20#ibcon#*before write, iclass 26, count 0 2006.162.08:15:29.20#ibcon#enter sib2, iclass 26, count 0 2006.162.08:15:29.20#ibcon#flushed, iclass 26, count 0 2006.162.08:15:29.20#ibcon#about to write, iclass 26, count 0 2006.162.08:15:29.20#ibcon#wrote, iclass 26, count 0 2006.162.08:15:29.20#ibcon#about to read 3, iclass 26, count 0 2006.162.08:15:29.23#ibcon#read 3, iclass 26, count 0 2006.162.08:15:29.23#ibcon#about to read 4, iclass 26, count 0 2006.162.08:15:29.23#ibcon#read 4, iclass 26, count 0 2006.162.08:15:29.23#ibcon#about to read 5, iclass 26, count 0 2006.162.08:15:29.23#ibcon#read 5, iclass 26, count 0 2006.162.08:15:29.23#ibcon#about to read 6, iclass 26, count 0 2006.162.08:15:29.23#ibcon#read 6, iclass 26, count 0 2006.162.08:15:29.23#ibcon#end of sib2, iclass 26, count 0 2006.162.08:15:29.23#ibcon#*after write, iclass 26, count 0 2006.162.08:15:29.23#ibcon#*before return 0, iclass 26, count 0 2006.162.08:15:29.23#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:15:29.23#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:15:29.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.162.08:15:29.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.162.08:15:29.23$vc4f8/valo=2,572.99 2006.162.08:15:29.23#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.162.08:15:29.23#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.162.08:15:29.23#ibcon#ireg 17 cls_cnt 0 2006.162.08:15:29.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:15:29.23#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:15:29.23#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:15:29.23#ibcon#enter wrdev, iclass 28, count 0 2006.162.08:15:29.23#ibcon#first serial, iclass 28, count 0 2006.162.08:15:29.23#ibcon#enter sib2, iclass 28, count 0 2006.162.08:15:29.23#ibcon#flushed, iclass 28, count 0 2006.162.08:15:29.23#ibcon#about to write, iclass 28, count 0 2006.162.08:15:29.23#ibcon#wrote, iclass 28, count 0 2006.162.08:15:29.23#ibcon#about to read 3, iclass 28, count 0 2006.162.08:15:29.26#ibcon#read 3, iclass 28, count 0 2006.162.08:15:29.26#ibcon#about to read 4, iclass 28, count 0 2006.162.08:15:29.26#ibcon#read 4, iclass 28, count 0 2006.162.08:15:29.26#ibcon#about to read 5, iclass 28, count 0 2006.162.08:15:29.26#ibcon#read 5, iclass 28, count 0 2006.162.08:15:29.26#ibcon#about to read 6, iclass 28, count 0 2006.162.08:15:29.26#ibcon#read 6, iclass 28, count 0 2006.162.08:15:29.26#ibcon#end of sib2, iclass 28, count 0 2006.162.08:15:29.26#ibcon#*mode == 0, iclass 28, count 0 2006.162.08:15:29.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.162.08:15:29.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.08:15:29.26#ibcon#*before write, iclass 28, count 0 2006.162.08:15:29.26#ibcon#enter sib2, iclass 28, count 0 2006.162.08:15:29.26#ibcon#flushed, iclass 28, count 0 2006.162.08:15:29.26#ibcon#about to write, iclass 28, count 0 2006.162.08:15:29.26#ibcon#wrote, iclass 28, count 0 2006.162.08:15:29.26#ibcon#about to read 3, iclass 28, count 0 2006.162.08:15:29.30#ibcon#read 3, iclass 28, count 0 2006.162.08:15:29.30#ibcon#about to read 4, iclass 28, count 0 2006.162.08:15:29.30#ibcon#read 4, iclass 28, count 0 2006.162.08:15:29.30#ibcon#about to read 5, iclass 28, count 0 2006.162.08:15:29.30#ibcon#read 5, iclass 28, count 0 2006.162.08:15:29.30#ibcon#about to read 6, iclass 28, count 0 2006.162.08:15:29.30#ibcon#read 6, iclass 28, count 0 2006.162.08:15:29.30#ibcon#end of sib2, iclass 28, count 0 2006.162.08:15:29.30#ibcon#*after write, iclass 28, count 0 2006.162.08:15:29.30#ibcon#*before return 0, iclass 28, count 0 2006.162.08:15:29.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:15:29.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:15:29.30#ibcon#about to clear, iclass 28 cls_cnt 0 2006.162.08:15:29.30#ibcon#cleared, iclass 28 cls_cnt 0 2006.162.08:15:29.30$vc4f8/va=2,7 2006.162.08:15:29.30#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.162.08:15:29.30#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.162.08:15:29.30#ibcon#ireg 11 cls_cnt 2 2006.162.08:15:29.30#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:15:29.35#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:15:29.35#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:15:29.35#ibcon#enter wrdev, iclass 30, count 2 2006.162.08:15:29.35#ibcon#first serial, iclass 30, count 2 2006.162.08:15:29.35#ibcon#enter sib2, iclass 30, count 2 2006.162.08:15:29.35#ibcon#flushed, iclass 30, count 2 2006.162.08:15:29.35#ibcon#about to write, iclass 30, count 2 2006.162.08:15:29.35#ibcon#wrote, iclass 30, count 2 2006.162.08:15:29.35#ibcon#about to read 3, iclass 30, count 2 2006.162.08:15:29.38#ibcon#read 3, iclass 30, count 2 2006.162.08:15:29.38#ibcon#about to read 4, iclass 30, count 2 2006.162.08:15:29.38#ibcon#read 4, iclass 30, count 2 2006.162.08:15:29.38#ibcon#about to read 5, iclass 30, count 2 2006.162.08:15:29.38#ibcon#read 5, iclass 30, count 2 2006.162.08:15:29.38#ibcon#about to read 6, iclass 30, count 2 2006.162.08:15:29.38#ibcon#read 6, iclass 30, count 2 2006.162.08:15:29.38#ibcon#end of sib2, iclass 30, count 2 2006.162.08:15:29.38#ibcon#*mode == 0, iclass 30, count 2 2006.162.08:15:29.38#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.162.08:15:29.38#ibcon#[25=AT02-07\r\n] 2006.162.08:15:29.38#ibcon#*before write, iclass 30, count 2 2006.162.08:15:29.38#ibcon#enter sib2, iclass 30, count 2 2006.162.08:15:29.38#ibcon#flushed, iclass 30, count 2 2006.162.08:15:29.38#ibcon#about to write, iclass 30, count 2 2006.162.08:15:29.38#ibcon#wrote, iclass 30, count 2 2006.162.08:15:29.38#ibcon#about to read 3, iclass 30, count 2 2006.162.08:15:29.41#ibcon#read 3, iclass 30, count 2 2006.162.08:15:29.41#ibcon#about to read 4, iclass 30, count 2 2006.162.08:15:29.41#ibcon#read 4, iclass 30, count 2 2006.162.08:15:29.41#ibcon#about to read 5, iclass 30, count 2 2006.162.08:15:29.41#ibcon#read 5, iclass 30, count 2 2006.162.08:15:29.41#ibcon#about to read 6, iclass 30, count 2 2006.162.08:15:29.41#ibcon#read 6, iclass 30, count 2 2006.162.08:15:29.41#ibcon#end of sib2, iclass 30, count 2 2006.162.08:15:29.41#ibcon#*after write, iclass 30, count 2 2006.162.08:15:29.41#ibcon#*before return 0, iclass 30, count 2 2006.162.08:15:29.41#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:15:29.41#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:15:29.41#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.162.08:15:29.41#ibcon#ireg 7 cls_cnt 0 2006.162.08:15:29.41#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:15:29.53#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:15:29.53#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:15:29.53#ibcon#enter wrdev, iclass 30, count 0 2006.162.08:15:29.53#ibcon#first serial, iclass 30, count 0 2006.162.08:15:29.53#ibcon#enter sib2, iclass 30, count 0 2006.162.08:15:29.53#ibcon#flushed, iclass 30, count 0 2006.162.08:15:29.53#ibcon#about to write, iclass 30, count 0 2006.162.08:15:29.53#ibcon#wrote, iclass 30, count 0 2006.162.08:15:29.53#ibcon#about to read 3, iclass 30, count 0 2006.162.08:15:29.55#ibcon#read 3, iclass 30, count 0 2006.162.08:15:29.55#ibcon#about to read 4, iclass 30, count 0 2006.162.08:15:29.55#ibcon#read 4, iclass 30, count 0 2006.162.08:15:29.55#ibcon#about to read 5, iclass 30, count 0 2006.162.08:15:29.55#ibcon#read 5, iclass 30, count 0 2006.162.08:15:29.55#ibcon#about to read 6, iclass 30, count 0 2006.162.08:15:29.55#ibcon#read 6, iclass 30, count 0 2006.162.08:15:29.55#ibcon#end of sib2, iclass 30, count 0 2006.162.08:15:29.55#ibcon#*mode == 0, iclass 30, count 0 2006.162.08:15:29.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.162.08:15:29.55#ibcon#[25=USB\r\n] 2006.162.08:15:29.55#ibcon#*before write, iclass 30, count 0 2006.162.08:15:29.55#ibcon#enter sib2, iclass 30, count 0 2006.162.08:15:29.55#ibcon#flushed, iclass 30, count 0 2006.162.08:15:29.55#ibcon#about to write, iclass 30, count 0 2006.162.08:15:29.55#ibcon#wrote, iclass 30, count 0 2006.162.08:15:29.55#ibcon#about to read 3, iclass 30, count 0 2006.162.08:15:29.58#ibcon#read 3, iclass 30, count 0 2006.162.08:15:29.58#ibcon#about to read 4, iclass 30, count 0 2006.162.08:15:29.58#ibcon#read 4, iclass 30, count 0 2006.162.08:15:29.58#ibcon#about to read 5, iclass 30, count 0 2006.162.08:15:29.58#ibcon#read 5, iclass 30, count 0 2006.162.08:15:29.58#ibcon#about to read 6, iclass 30, count 0 2006.162.08:15:29.58#ibcon#read 6, iclass 30, count 0 2006.162.08:15:29.58#ibcon#end of sib2, iclass 30, count 0 2006.162.08:15:29.58#ibcon#*after write, iclass 30, count 0 2006.162.08:15:29.58#ibcon#*before return 0, iclass 30, count 0 2006.162.08:15:29.58#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:15:29.58#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:15:29.58#ibcon#about to clear, iclass 30 cls_cnt 0 2006.162.08:15:29.58#ibcon#cleared, iclass 30 cls_cnt 0 2006.162.08:15:29.58$vc4f8/valo=3,672.99 2006.162.08:15:29.58#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.162.08:15:29.58#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.162.08:15:29.58#ibcon#ireg 17 cls_cnt 0 2006.162.08:15:29.58#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:15:29.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:15:29.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:15:29.58#ibcon#enter wrdev, iclass 32, count 0 2006.162.08:15:29.58#ibcon#first serial, iclass 32, count 0 2006.162.08:15:29.58#ibcon#enter sib2, iclass 32, count 0 2006.162.08:15:29.58#ibcon#flushed, iclass 32, count 0 2006.162.08:15:29.58#ibcon#about to write, iclass 32, count 0 2006.162.08:15:29.58#ibcon#wrote, iclass 32, count 0 2006.162.08:15:29.58#ibcon#about to read 3, iclass 32, count 0 2006.162.08:15:29.60#ibcon#read 3, iclass 32, count 0 2006.162.08:15:29.60#ibcon#about to read 4, iclass 32, count 0 2006.162.08:15:29.60#ibcon#read 4, iclass 32, count 0 2006.162.08:15:29.60#ibcon#about to read 5, iclass 32, count 0 2006.162.08:15:29.60#ibcon#read 5, iclass 32, count 0 2006.162.08:15:29.60#ibcon#about to read 6, iclass 32, count 0 2006.162.08:15:29.60#ibcon#read 6, iclass 32, count 0 2006.162.08:15:29.60#ibcon#end of sib2, iclass 32, count 0 2006.162.08:15:29.60#ibcon#*mode == 0, iclass 32, count 0 2006.162.08:15:29.60#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.162.08:15:29.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.08:15:29.60#ibcon#*before write, iclass 32, count 0 2006.162.08:15:29.60#ibcon#enter sib2, iclass 32, count 0 2006.162.08:15:29.60#ibcon#flushed, iclass 32, count 0 2006.162.08:15:29.60#ibcon#about to write, iclass 32, count 0 2006.162.08:15:29.60#ibcon#wrote, iclass 32, count 0 2006.162.08:15:29.60#ibcon#about to read 3, iclass 32, count 0 2006.162.08:15:29.64#ibcon#read 3, iclass 32, count 0 2006.162.08:15:29.64#ibcon#about to read 4, iclass 32, count 0 2006.162.08:15:29.64#ibcon#read 4, iclass 32, count 0 2006.162.08:15:29.64#ibcon#about to read 5, iclass 32, count 0 2006.162.08:15:29.64#ibcon#read 5, iclass 32, count 0 2006.162.08:15:29.64#ibcon#about to read 6, iclass 32, count 0 2006.162.08:15:29.64#ibcon#read 6, iclass 32, count 0 2006.162.08:15:29.64#ibcon#end of sib2, iclass 32, count 0 2006.162.08:15:29.64#ibcon#*after write, iclass 32, count 0 2006.162.08:15:29.64#ibcon#*before return 0, iclass 32, count 0 2006.162.08:15:29.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:15:29.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:15:29.64#ibcon#about to clear, iclass 32 cls_cnt 0 2006.162.08:15:29.64#ibcon#cleared, iclass 32 cls_cnt 0 2006.162.08:15:29.64$vc4f8/va=3,6 2006.162.08:15:29.64#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.162.08:15:29.64#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.162.08:15:29.64#ibcon#ireg 11 cls_cnt 2 2006.162.08:15:29.64#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:15:29.70#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:15:29.70#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:15:29.70#ibcon#enter wrdev, iclass 34, count 2 2006.162.08:15:29.70#ibcon#first serial, iclass 34, count 2 2006.162.08:15:29.70#ibcon#enter sib2, iclass 34, count 2 2006.162.08:15:29.70#ibcon#flushed, iclass 34, count 2 2006.162.08:15:29.70#ibcon#about to write, iclass 34, count 2 2006.162.08:15:29.70#ibcon#wrote, iclass 34, count 2 2006.162.08:15:29.70#ibcon#about to read 3, iclass 34, count 2 2006.162.08:15:29.73#ibcon#read 3, iclass 34, count 2 2006.162.08:15:29.73#ibcon#about to read 4, iclass 34, count 2 2006.162.08:15:29.73#ibcon#read 4, iclass 34, count 2 2006.162.08:15:29.73#ibcon#about to read 5, iclass 34, count 2 2006.162.08:15:29.73#ibcon#read 5, iclass 34, count 2 2006.162.08:15:29.73#ibcon#about to read 6, iclass 34, count 2 2006.162.08:15:29.73#ibcon#read 6, iclass 34, count 2 2006.162.08:15:29.73#ibcon#end of sib2, iclass 34, count 2 2006.162.08:15:29.73#ibcon#*mode == 0, iclass 34, count 2 2006.162.08:15:29.73#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.162.08:15:29.73#ibcon#[25=AT03-06\r\n] 2006.162.08:15:29.73#ibcon#*before write, iclass 34, count 2 2006.162.08:15:29.73#ibcon#enter sib2, iclass 34, count 2 2006.162.08:15:29.73#ibcon#flushed, iclass 34, count 2 2006.162.08:15:29.73#ibcon#about to write, iclass 34, count 2 2006.162.08:15:29.73#ibcon#wrote, iclass 34, count 2 2006.162.08:15:29.73#ibcon#about to read 3, iclass 34, count 2 2006.162.08:15:29.76#ibcon#read 3, iclass 34, count 2 2006.162.08:15:29.76#ibcon#about to read 4, iclass 34, count 2 2006.162.08:15:29.76#ibcon#read 4, iclass 34, count 2 2006.162.08:15:29.76#ibcon#about to read 5, iclass 34, count 2 2006.162.08:15:29.76#ibcon#read 5, iclass 34, count 2 2006.162.08:15:29.76#ibcon#about to read 6, iclass 34, count 2 2006.162.08:15:29.76#ibcon#read 6, iclass 34, count 2 2006.162.08:15:29.76#ibcon#end of sib2, iclass 34, count 2 2006.162.08:15:29.76#ibcon#*after write, iclass 34, count 2 2006.162.08:15:29.76#ibcon#*before return 0, iclass 34, count 2 2006.162.08:15:29.76#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:15:29.76#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:15:29.76#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.162.08:15:29.76#ibcon#ireg 7 cls_cnt 0 2006.162.08:15:29.76#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:15:29.88#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:15:29.88#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:15:29.88#ibcon#enter wrdev, iclass 34, count 0 2006.162.08:15:29.88#ibcon#first serial, iclass 34, count 0 2006.162.08:15:29.88#ibcon#enter sib2, iclass 34, count 0 2006.162.08:15:29.88#ibcon#flushed, iclass 34, count 0 2006.162.08:15:29.88#ibcon#about to write, iclass 34, count 0 2006.162.08:15:29.88#ibcon#wrote, iclass 34, count 0 2006.162.08:15:29.88#ibcon#about to read 3, iclass 34, count 0 2006.162.08:15:29.90#ibcon#read 3, iclass 34, count 0 2006.162.08:15:29.90#ibcon#about to read 4, iclass 34, count 0 2006.162.08:15:29.90#ibcon#read 4, iclass 34, count 0 2006.162.08:15:29.90#ibcon#about to read 5, iclass 34, count 0 2006.162.08:15:29.90#ibcon#read 5, iclass 34, count 0 2006.162.08:15:29.90#ibcon#about to read 6, iclass 34, count 0 2006.162.08:15:29.90#ibcon#read 6, iclass 34, count 0 2006.162.08:15:29.90#ibcon#end of sib2, iclass 34, count 0 2006.162.08:15:29.90#ibcon#*mode == 0, iclass 34, count 0 2006.162.08:15:29.90#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.162.08:15:29.90#ibcon#[25=USB\r\n] 2006.162.08:15:29.90#ibcon#*before write, iclass 34, count 0 2006.162.08:15:29.90#ibcon#enter sib2, iclass 34, count 0 2006.162.08:15:29.90#ibcon#flushed, iclass 34, count 0 2006.162.08:15:29.90#ibcon#about to write, iclass 34, count 0 2006.162.08:15:29.90#ibcon#wrote, iclass 34, count 0 2006.162.08:15:29.90#ibcon#about to read 3, iclass 34, count 0 2006.162.08:15:29.93#ibcon#read 3, iclass 34, count 0 2006.162.08:15:29.93#ibcon#about to read 4, iclass 34, count 0 2006.162.08:15:29.93#ibcon#read 4, iclass 34, count 0 2006.162.08:15:29.93#ibcon#about to read 5, iclass 34, count 0 2006.162.08:15:29.93#ibcon#read 5, iclass 34, count 0 2006.162.08:15:29.93#ibcon#about to read 6, iclass 34, count 0 2006.162.08:15:29.93#ibcon#read 6, iclass 34, count 0 2006.162.08:15:29.93#ibcon#end of sib2, iclass 34, count 0 2006.162.08:15:29.93#ibcon#*after write, iclass 34, count 0 2006.162.08:15:29.93#ibcon#*before return 0, iclass 34, count 0 2006.162.08:15:29.93#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:15:29.93#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:15:29.93#ibcon#about to clear, iclass 34 cls_cnt 0 2006.162.08:15:29.93#ibcon#cleared, iclass 34 cls_cnt 0 2006.162.08:15:29.93$vc4f8/valo=4,832.99 2006.162.08:15:29.93#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.162.08:15:29.93#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.162.08:15:29.93#ibcon#ireg 17 cls_cnt 0 2006.162.08:15:29.93#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:15:29.93#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:15:29.93#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:15:29.93#ibcon#enter wrdev, iclass 36, count 0 2006.162.08:15:29.93#ibcon#first serial, iclass 36, count 0 2006.162.08:15:29.93#ibcon#enter sib2, iclass 36, count 0 2006.162.08:15:29.93#ibcon#flushed, iclass 36, count 0 2006.162.08:15:29.93#ibcon#about to write, iclass 36, count 0 2006.162.08:15:29.93#ibcon#wrote, iclass 36, count 0 2006.162.08:15:29.93#ibcon#about to read 3, iclass 36, count 0 2006.162.08:15:29.95#ibcon#read 3, iclass 36, count 0 2006.162.08:15:29.95#ibcon#about to read 4, iclass 36, count 0 2006.162.08:15:29.95#ibcon#read 4, iclass 36, count 0 2006.162.08:15:29.95#ibcon#about to read 5, iclass 36, count 0 2006.162.08:15:29.95#ibcon#read 5, iclass 36, count 0 2006.162.08:15:29.95#ibcon#about to read 6, iclass 36, count 0 2006.162.08:15:29.95#ibcon#read 6, iclass 36, count 0 2006.162.08:15:29.95#ibcon#end of sib2, iclass 36, count 0 2006.162.08:15:29.95#ibcon#*mode == 0, iclass 36, count 0 2006.162.08:15:29.95#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.162.08:15:29.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.08:15:29.95#ibcon#*before write, iclass 36, count 0 2006.162.08:15:29.95#ibcon#enter sib2, iclass 36, count 0 2006.162.08:15:29.95#ibcon#flushed, iclass 36, count 0 2006.162.08:15:29.95#ibcon#about to write, iclass 36, count 0 2006.162.08:15:29.95#ibcon#wrote, iclass 36, count 0 2006.162.08:15:29.95#ibcon#about to read 3, iclass 36, count 0 2006.162.08:15:29.99#ibcon#read 3, iclass 36, count 0 2006.162.08:15:29.99#ibcon#about to read 4, iclass 36, count 0 2006.162.08:15:29.99#ibcon#read 4, iclass 36, count 0 2006.162.08:15:29.99#ibcon#about to read 5, iclass 36, count 0 2006.162.08:15:29.99#ibcon#read 5, iclass 36, count 0 2006.162.08:15:29.99#ibcon#about to read 6, iclass 36, count 0 2006.162.08:15:29.99#ibcon#read 6, iclass 36, count 0 2006.162.08:15:29.99#ibcon#end of sib2, iclass 36, count 0 2006.162.08:15:29.99#ibcon#*after write, iclass 36, count 0 2006.162.08:15:29.99#ibcon#*before return 0, iclass 36, count 0 2006.162.08:15:29.99#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:15:29.99#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:15:29.99#ibcon#about to clear, iclass 36 cls_cnt 0 2006.162.08:15:29.99#ibcon#cleared, iclass 36 cls_cnt 0 2006.162.08:15:29.99$vc4f8/va=4,7 2006.162.08:15:29.99#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.162.08:15:29.99#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.162.08:15:29.99#ibcon#ireg 11 cls_cnt 2 2006.162.08:15:29.99#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.162.08:15:30.05#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.162.08:15:30.05#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.162.08:15:30.05#ibcon#enter wrdev, iclass 38, count 2 2006.162.08:15:30.05#ibcon#first serial, iclass 38, count 2 2006.162.08:15:30.05#ibcon#enter sib2, iclass 38, count 2 2006.162.08:15:30.05#ibcon#flushed, iclass 38, count 2 2006.162.08:15:30.05#ibcon#about to write, iclass 38, count 2 2006.162.08:15:30.05#ibcon#wrote, iclass 38, count 2 2006.162.08:15:30.05#ibcon#about to read 3, iclass 38, count 2 2006.162.08:15:30.07#ibcon#read 3, iclass 38, count 2 2006.162.08:15:30.07#ibcon#about to read 4, iclass 38, count 2 2006.162.08:15:30.07#ibcon#read 4, iclass 38, count 2 2006.162.08:15:30.07#ibcon#about to read 5, iclass 38, count 2 2006.162.08:15:30.07#ibcon#read 5, iclass 38, count 2 2006.162.08:15:30.07#ibcon#about to read 6, iclass 38, count 2 2006.162.08:15:30.07#ibcon#read 6, iclass 38, count 2 2006.162.08:15:30.07#ibcon#end of sib2, iclass 38, count 2 2006.162.08:15:30.07#ibcon#*mode == 0, iclass 38, count 2 2006.162.08:15:30.07#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.162.08:15:30.07#ibcon#[25=AT04-07\r\n] 2006.162.08:15:30.07#ibcon#*before write, iclass 38, count 2 2006.162.08:15:30.07#ibcon#enter sib2, iclass 38, count 2 2006.162.08:15:30.07#ibcon#flushed, iclass 38, count 2 2006.162.08:15:30.07#ibcon#about to write, iclass 38, count 2 2006.162.08:15:30.07#ibcon#wrote, iclass 38, count 2 2006.162.08:15:30.07#ibcon#about to read 3, iclass 38, count 2 2006.162.08:15:30.10#ibcon#read 3, iclass 38, count 2 2006.162.08:15:30.10#ibcon#about to read 4, iclass 38, count 2 2006.162.08:15:30.10#ibcon#read 4, iclass 38, count 2 2006.162.08:15:30.10#ibcon#about to read 5, iclass 38, count 2 2006.162.08:15:30.10#ibcon#read 5, iclass 38, count 2 2006.162.08:15:30.10#ibcon#about to read 6, iclass 38, count 2 2006.162.08:15:30.10#ibcon#read 6, iclass 38, count 2 2006.162.08:15:30.10#ibcon#end of sib2, iclass 38, count 2 2006.162.08:15:30.10#ibcon#*after write, iclass 38, count 2 2006.162.08:15:30.10#ibcon#*before return 0, iclass 38, count 2 2006.162.08:15:30.10#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.162.08:15:30.10#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.162.08:15:30.10#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.162.08:15:30.10#ibcon#ireg 7 cls_cnt 0 2006.162.08:15:30.10#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.162.08:15:30.22#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.162.08:15:30.22#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.162.08:15:30.22#ibcon#enter wrdev, iclass 38, count 0 2006.162.08:15:30.22#ibcon#first serial, iclass 38, count 0 2006.162.08:15:30.22#ibcon#enter sib2, iclass 38, count 0 2006.162.08:15:30.22#ibcon#flushed, iclass 38, count 0 2006.162.08:15:30.22#ibcon#about to write, iclass 38, count 0 2006.162.08:15:30.22#ibcon#wrote, iclass 38, count 0 2006.162.08:15:30.22#ibcon#about to read 3, iclass 38, count 0 2006.162.08:15:30.24#ibcon#read 3, iclass 38, count 0 2006.162.08:15:30.24#ibcon#about to read 4, iclass 38, count 0 2006.162.08:15:30.24#ibcon#read 4, iclass 38, count 0 2006.162.08:15:30.24#ibcon#about to read 5, iclass 38, count 0 2006.162.08:15:30.24#ibcon#read 5, iclass 38, count 0 2006.162.08:15:30.24#ibcon#about to read 6, iclass 38, count 0 2006.162.08:15:30.24#ibcon#read 6, iclass 38, count 0 2006.162.08:15:30.24#ibcon#end of sib2, iclass 38, count 0 2006.162.08:15:30.24#ibcon#*mode == 0, iclass 38, count 0 2006.162.08:15:30.24#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.162.08:15:30.24#ibcon#[25=USB\r\n] 2006.162.08:15:30.24#ibcon#*before write, iclass 38, count 0 2006.162.08:15:30.24#ibcon#enter sib2, iclass 38, count 0 2006.162.08:15:30.24#ibcon#flushed, iclass 38, count 0 2006.162.08:15:30.24#ibcon#about to write, iclass 38, count 0 2006.162.08:15:30.24#ibcon#wrote, iclass 38, count 0 2006.162.08:15:30.24#ibcon#about to read 3, iclass 38, count 0 2006.162.08:15:30.27#ibcon#read 3, iclass 38, count 0 2006.162.08:15:30.27#ibcon#about to read 4, iclass 38, count 0 2006.162.08:15:30.27#ibcon#read 4, iclass 38, count 0 2006.162.08:15:30.27#ibcon#about to read 5, iclass 38, count 0 2006.162.08:15:30.27#ibcon#read 5, iclass 38, count 0 2006.162.08:15:30.27#ibcon#about to read 6, iclass 38, count 0 2006.162.08:15:30.27#ibcon#read 6, iclass 38, count 0 2006.162.08:15:30.27#ibcon#end of sib2, iclass 38, count 0 2006.162.08:15:30.27#ibcon#*after write, iclass 38, count 0 2006.162.08:15:30.27#ibcon#*before return 0, iclass 38, count 0 2006.162.08:15:30.27#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.162.08:15:30.27#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.162.08:15:30.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.162.08:15:30.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.162.08:15:30.27$vc4f8/valo=5,652.99 2006.162.08:15:30.27#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.162.08:15:30.27#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.162.08:15:30.27#ibcon#ireg 17 cls_cnt 0 2006.162.08:15:30.27#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:15:30.27#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:15:30.27#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:15:30.27#ibcon#enter wrdev, iclass 40, count 0 2006.162.08:15:30.27#ibcon#first serial, iclass 40, count 0 2006.162.08:15:30.27#ibcon#enter sib2, iclass 40, count 0 2006.162.08:15:30.27#ibcon#flushed, iclass 40, count 0 2006.162.08:15:30.27#ibcon#about to write, iclass 40, count 0 2006.162.08:15:30.27#ibcon#wrote, iclass 40, count 0 2006.162.08:15:30.27#ibcon#about to read 3, iclass 40, count 0 2006.162.08:15:30.29#ibcon#read 3, iclass 40, count 0 2006.162.08:15:30.29#ibcon#about to read 4, iclass 40, count 0 2006.162.08:15:30.29#ibcon#read 4, iclass 40, count 0 2006.162.08:15:30.29#ibcon#about to read 5, iclass 40, count 0 2006.162.08:15:30.29#ibcon#read 5, iclass 40, count 0 2006.162.08:15:30.29#ibcon#about to read 6, iclass 40, count 0 2006.162.08:15:30.29#ibcon#read 6, iclass 40, count 0 2006.162.08:15:30.29#ibcon#end of sib2, iclass 40, count 0 2006.162.08:15:30.29#ibcon#*mode == 0, iclass 40, count 0 2006.162.08:15:30.29#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.162.08:15:30.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.08:15:30.29#ibcon#*before write, iclass 40, count 0 2006.162.08:15:30.29#ibcon#enter sib2, iclass 40, count 0 2006.162.08:15:30.29#ibcon#flushed, iclass 40, count 0 2006.162.08:15:30.29#ibcon#about to write, iclass 40, count 0 2006.162.08:15:30.29#ibcon#wrote, iclass 40, count 0 2006.162.08:15:30.29#ibcon#about to read 3, iclass 40, count 0 2006.162.08:15:30.33#ibcon#read 3, iclass 40, count 0 2006.162.08:15:30.33#ibcon#about to read 4, iclass 40, count 0 2006.162.08:15:30.33#ibcon#read 4, iclass 40, count 0 2006.162.08:15:30.33#ibcon#about to read 5, iclass 40, count 0 2006.162.08:15:30.33#ibcon#read 5, iclass 40, count 0 2006.162.08:15:30.33#ibcon#about to read 6, iclass 40, count 0 2006.162.08:15:30.33#ibcon#read 6, iclass 40, count 0 2006.162.08:15:30.33#ibcon#end of sib2, iclass 40, count 0 2006.162.08:15:30.33#ibcon#*after write, iclass 40, count 0 2006.162.08:15:30.33#ibcon#*before return 0, iclass 40, count 0 2006.162.08:15:30.33#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:15:30.33#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:15:30.33#ibcon#about to clear, iclass 40 cls_cnt 0 2006.162.08:15:30.33#ibcon#cleared, iclass 40 cls_cnt 0 2006.162.08:15:30.33$vc4f8/va=5,7 2006.162.08:15:30.33#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.162.08:15:30.33#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.162.08:15:30.33#ibcon#ireg 11 cls_cnt 2 2006.162.08:15:30.33#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:15:30.39#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:15:30.39#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:15:30.39#ibcon#enter wrdev, iclass 4, count 2 2006.162.08:15:30.39#ibcon#first serial, iclass 4, count 2 2006.162.08:15:30.39#ibcon#enter sib2, iclass 4, count 2 2006.162.08:15:30.39#ibcon#flushed, iclass 4, count 2 2006.162.08:15:30.39#ibcon#about to write, iclass 4, count 2 2006.162.08:15:30.39#ibcon#wrote, iclass 4, count 2 2006.162.08:15:30.39#ibcon#about to read 3, iclass 4, count 2 2006.162.08:15:30.41#ibcon#read 3, iclass 4, count 2 2006.162.08:15:30.41#ibcon#about to read 4, iclass 4, count 2 2006.162.08:15:30.41#ibcon#read 4, iclass 4, count 2 2006.162.08:15:30.41#ibcon#about to read 5, iclass 4, count 2 2006.162.08:15:30.41#ibcon#read 5, iclass 4, count 2 2006.162.08:15:30.41#ibcon#about to read 6, iclass 4, count 2 2006.162.08:15:30.41#ibcon#read 6, iclass 4, count 2 2006.162.08:15:30.41#ibcon#end of sib2, iclass 4, count 2 2006.162.08:15:30.41#ibcon#*mode == 0, iclass 4, count 2 2006.162.08:15:30.41#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.162.08:15:30.41#ibcon#[25=AT05-07\r\n] 2006.162.08:15:30.41#ibcon#*before write, iclass 4, count 2 2006.162.08:15:30.41#ibcon#enter sib2, iclass 4, count 2 2006.162.08:15:30.41#ibcon#flushed, iclass 4, count 2 2006.162.08:15:30.41#ibcon#about to write, iclass 4, count 2 2006.162.08:15:30.41#ibcon#wrote, iclass 4, count 2 2006.162.08:15:30.41#ibcon#about to read 3, iclass 4, count 2 2006.162.08:15:30.44#ibcon#read 3, iclass 4, count 2 2006.162.08:15:30.44#ibcon#about to read 4, iclass 4, count 2 2006.162.08:15:30.44#ibcon#read 4, iclass 4, count 2 2006.162.08:15:30.44#ibcon#about to read 5, iclass 4, count 2 2006.162.08:15:30.44#ibcon#read 5, iclass 4, count 2 2006.162.08:15:30.44#ibcon#about to read 6, iclass 4, count 2 2006.162.08:15:30.44#ibcon#read 6, iclass 4, count 2 2006.162.08:15:30.44#ibcon#end of sib2, iclass 4, count 2 2006.162.08:15:30.44#ibcon#*after write, iclass 4, count 2 2006.162.08:15:30.44#ibcon#*before return 0, iclass 4, count 2 2006.162.08:15:30.44#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:15:30.44#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:15:30.44#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.162.08:15:30.44#ibcon#ireg 7 cls_cnt 0 2006.162.08:15:30.44#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:15:30.56#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:15:30.56#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:15:30.56#ibcon#enter wrdev, iclass 4, count 0 2006.162.08:15:30.56#ibcon#first serial, iclass 4, count 0 2006.162.08:15:30.56#ibcon#enter sib2, iclass 4, count 0 2006.162.08:15:30.56#ibcon#flushed, iclass 4, count 0 2006.162.08:15:30.56#ibcon#about to write, iclass 4, count 0 2006.162.08:15:30.56#ibcon#wrote, iclass 4, count 0 2006.162.08:15:30.56#ibcon#about to read 3, iclass 4, count 0 2006.162.08:15:30.58#ibcon#read 3, iclass 4, count 0 2006.162.08:15:30.58#ibcon#about to read 4, iclass 4, count 0 2006.162.08:15:30.58#ibcon#read 4, iclass 4, count 0 2006.162.08:15:30.58#ibcon#about to read 5, iclass 4, count 0 2006.162.08:15:30.58#ibcon#read 5, iclass 4, count 0 2006.162.08:15:30.58#ibcon#about to read 6, iclass 4, count 0 2006.162.08:15:30.58#ibcon#read 6, iclass 4, count 0 2006.162.08:15:30.58#ibcon#end of sib2, iclass 4, count 0 2006.162.08:15:30.58#ibcon#*mode == 0, iclass 4, count 0 2006.162.08:15:30.58#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.162.08:15:30.58#ibcon#[25=USB\r\n] 2006.162.08:15:30.58#ibcon#*before write, iclass 4, count 0 2006.162.08:15:30.58#ibcon#enter sib2, iclass 4, count 0 2006.162.08:15:30.58#ibcon#flushed, iclass 4, count 0 2006.162.08:15:30.58#ibcon#about to write, iclass 4, count 0 2006.162.08:15:30.58#ibcon#wrote, iclass 4, count 0 2006.162.08:15:30.58#ibcon#about to read 3, iclass 4, count 0 2006.162.08:15:30.61#ibcon#read 3, iclass 4, count 0 2006.162.08:15:30.61#ibcon#about to read 4, iclass 4, count 0 2006.162.08:15:30.61#ibcon#read 4, iclass 4, count 0 2006.162.08:15:30.61#ibcon#about to read 5, iclass 4, count 0 2006.162.08:15:30.61#ibcon#read 5, iclass 4, count 0 2006.162.08:15:30.61#ibcon#about to read 6, iclass 4, count 0 2006.162.08:15:30.61#ibcon#read 6, iclass 4, count 0 2006.162.08:15:30.61#ibcon#end of sib2, iclass 4, count 0 2006.162.08:15:30.61#ibcon#*after write, iclass 4, count 0 2006.162.08:15:30.61#ibcon#*before return 0, iclass 4, count 0 2006.162.08:15:30.61#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:15:30.61#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:15:30.61#ibcon#about to clear, iclass 4 cls_cnt 0 2006.162.08:15:30.61#ibcon#cleared, iclass 4 cls_cnt 0 2006.162.08:15:30.61$vc4f8/valo=6,772.99 2006.162.08:15:30.61#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.162.08:15:30.61#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.162.08:15:30.61#ibcon#ireg 17 cls_cnt 0 2006.162.08:15:30.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:15:30.61#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:15:30.61#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:15:30.61#ibcon#enter wrdev, iclass 6, count 0 2006.162.08:15:30.61#ibcon#first serial, iclass 6, count 0 2006.162.08:15:30.61#ibcon#enter sib2, iclass 6, count 0 2006.162.08:15:30.61#ibcon#flushed, iclass 6, count 0 2006.162.08:15:30.61#ibcon#about to write, iclass 6, count 0 2006.162.08:15:30.61#ibcon#wrote, iclass 6, count 0 2006.162.08:15:30.61#ibcon#about to read 3, iclass 6, count 0 2006.162.08:15:30.63#ibcon#read 3, iclass 6, count 0 2006.162.08:15:30.63#ibcon#about to read 4, iclass 6, count 0 2006.162.08:15:30.63#ibcon#read 4, iclass 6, count 0 2006.162.08:15:30.63#ibcon#about to read 5, iclass 6, count 0 2006.162.08:15:30.63#ibcon#read 5, iclass 6, count 0 2006.162.08:15:30.63#ibcon#about to read 6, iclass 6, count 0 2006.162.08:15:30.63#ibcon#read 6, iclass 6, count 0 2006.162.08:15:30.63#ibcon#end of sib2, iclass 6, count 0 2006.162.08:15:30.63#ibcon#*mode == 0, iclass 6, count 0 2006.162.08:15:30.63#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.162.08:15:30.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.08:15:30.63#ibcon#*before write, iclass 6, count 0 2006.162.08:15:30.63#ibcon#enter sib2, iclass 6, count 0 2006.162.08:15:30.63#ibcon#flushed, iclass 6, count 0 2006.162.08:15:30.63#ibcon#about to write, iclass 6, count 0 2006.162.08:15:30.63#ibcon#wrote, iclass 6, count 0 2006.162.08:15:30.63#ibcon#about to read 3, iclass 6, count 0 2006.162.08:15:30.67#ibcon#read 3, iclass 6, count 0 2006.162.08:15:30.67#ibcon#about to read 4, iclass 6, count 0 2006.162.08:15:30.67#ibcon#read 4, iclass 6, count 0 2006.162.08:15:30.67#ibcon#about to read 5, iclass 6, count 0 2006.162.08:15:30.67#ibcon#read 5, iclass 6, count 0 2006.162.08:15:30.67#ibcon#about to read 6, iclass 6, count 0 2006.162.08:15:30.67#ibcon#read 6, iclass 6, count 0 2006.162.08:15:30.67#ibcon#end of sib2, iclass 6, count 0 2006.162.08:15:30.67#ibcon#*after write, iclass 6, count 0 2006.162.08:15:30.67#ibcon#*before return 0, iclass 6, count 0 2006.162.08:15:30.67#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:15:30.67#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:15:30.67#ibcon#about to clear, iclass 6 cls_cnt 0 2006.162.08:15:30.67#ibcon#cleared, iclass 6 cls_cnt 0 2006.162.08:15:30.67$vc4f8/va=6,6 2006.162.08:15:30.67#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.162.08:15:30.67#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.162.08:15:30.67#ibcon#ireg 11 cls_cnt 2 2006.162.08:15:30.67#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:15:30.73#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:15:30.73#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:15:30.73#ibcon#enter wrdev, iclass 10, count 2 2006.162.08:15:30.73#ibcon#first serial, iclass 10, count 2 2006.162.08:15:30.73#ibcon#enter sib2, iclass 10, count 2 2006.162.08:15:30.73#ibcon#flushed, iclass 10, count 2 2006.162.08:15:30.73#ibcon#about to write, iclass 10, count 2 2006.162.08:15:30.73#ibcon#wrote, iclass 10, count 2 2006.162.08:15:30.73#ibcon#about to read 3, iclass 10, count 2 2006.162.08:15:30.75#ibcon#read 3, iclass 10, count 2 2006.162.08:15:30.75#ibcon#about to read 4, iclass 10, count 2 2006.162.08:15:30.75#ibcon#read 4, iclass 10, count 2 2006.162.08:15:30.75#ibcon#about to read 5, iclass 10, count 2 2006.162.08:15:30.75#ibcon#read 5, iclass 10, count 2 2006.162.08:15:30.75#ibcon#about to read 6, iclass 10, count 2 2006.162.08:15:30.75#ibcon#read 6, iclass 10, count 2 2006.162.08:15:30.75#ibcon#end of sib2, iclass 10, count 2 2006.162.08:15:30.75#ibcon#*mode == 0, iclass 10, count 2 2006.162.08:15:30.75#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.162.08:15:30.75#ibcon#[25=AT06-06\r\n] 2006.162.08:15:30.75#ibcon#*before write, iclass 10, count 2 2006.162.08:15:30.75#ibcon#enter sib2, iclass 10, count 2 2006.162.08:15:30.75#ibcon#flushed, iclass 10, count 2 2006.162.08:15:30.75#ibcon#about to write, iclass 10, count 2 2006.162.08:15:30.75#ibcon#wrote, iclass 10, count 2 2006.162.08:15:30.75#ibcon#about to read 3, iclass 10, count 2 2006.162.08:15:30.78#ibcon#read 3, iclass 10, count 2 2006.162.08:15:30.78#ibcon#about to read 4, iclass 10, count 2 2006.162.08:15:30.78#ibcon#read 4, iclass 10, count 2 2006.162.08:15:30.78#ibcon#about to read 5, iclass 10, count 2 2006.162.08:15:30.78#ibcon#read 5, iclass 10, count 2 2006.162.08:15:30.78#ibcon#about to read 6, iclass 10, count 2 2006.162.08:15:30.78#ibcon#read 6, iclass 10, count 2 2006.162.08:15:30.78#ibcon#end of sib2, iclass 10, count 2 2006.162.08:15:30.78#ibcon#*after write, iclass 10, count 2 2006.162.08:15:30.78#ibcon#*before return 0, iclass 10, count 2 2006.162.08:15:30.78#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:15:30.78#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:15:30.78#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.162.08:15:30.78#ibcon#ireg 7 cls_cnt 0 2006.162.08:15:30.78#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:15:30.90#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:15:30.90#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:15:30.90#ibcon#enter wrdev, iclass 10, count 0 2006.162.08:15:30.90#ibcon#first serial, iclass 10, count 0 2006.162.08:15:30.90#ibcon#enter sib2, iclass 10, count 0 2006.162.08:15:30.90#ibcon#flushed, iclass 10, count 0 2006.162.08:15:30.90#ibcon#about to write, iclass 10, count 0 2006.162.08:15:30.90#ibcon#wrote, iclass 10, count 0 2006.162.08:15:30.90#ibcon#about to read 3, iclass 10, count 0 2006.162.08:15:30.92#ibcon#read 3, iclass 10, count 0 2006.162.08:15:30.92#ibcon#about to read 4, iclass 10, count 0 2006.162.08:15:30.92#ibcon#read 4, iclass 10, count 0 2006.162.08:15:30.92#ibcon#about to read 5, iclass 10, count 0 2006.162.08:15:30.92#ibcon#read 5, iclass 10, count 0 2006.162.08:15:30.92#ibcon#about to read 6, iclass 10, count 0 2006.162.08:15:30.92#ibcon#read 6, iclass 10, count 0 2006.162.08:15:30.92#ibcon#end of sib2, iclass 10, count 0 2006.162.08:15:30.92#ibcon#*mode == 0, iclass 10, count 0 2006.162.08:15:30.92#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.162.08:15:30.92#ibcon#[25=USB\r\n] 2006.162.08:15:30.92#ibcon#*before write, iclass 10, count 0 2006.162.08:15:30.92#ibcon#enter sib2, iclass 10, count 0 2006.162.08:15:30.92#ibcon#flushed, iclass 10, count 0 2006.162.08:15:30.92#ibcon#about to write, iclass 10, count 0 2006.162.08:15:30.92#ibcon#wrote, iclass 10, count 0 2006.162.08:15:30.92#ibcon#about to read 3, iclass 10, count 0 2006.162.08:15:30.95#ibcon#read 3, iclass 10, count 0 2006.162.08:15:30.95#ibcon#about to read 4, iclass 10, count 0 2006.162.08:15:30.95#ibcon#read 4, iclass 10, count 0 2006.162.08:15:30.95#ibcon#about to read 5, iclass 10, count 0 2006.162.08:15:30.95#ibcon#read 5, iclass 10, count 0 2006.162.08:15:30.95#ibcon#about to read 6, iclass 10, count 0 2006.162.08:15:30.95#ibcon#read 6, iclass 10, count 0 2006.162.08:15:30.95#ibcon#end of sib2, iclass 10, count 0 2006.162.08:15:30.95#ibcon#*after write, iclass 10, count 0 2006.162.08:15:30.95#ibcon#*before return 0, iclass 10, count 0 2006.162.08:15:30.95#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:15:30.95#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:15:30.95#ibcon#about to clear, iclass 10 cls_cnt 0 2006.162.08:15:30.95#ibcon#cleared, iclass 10 cls_cnt 0 2006.162.08:15:30.95$vc4f8/valo=7,832.99 2006.162.08:15:30.95#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.162.08:15:30.95#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.162.08:15:30.95#ibcon#ireg 17 cls_cnt 0 2006.162.08:15:30.95#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:15:30.95#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:15:30.95#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:15:30.95#ibcon#enter wrdev, iclass 12, count 0 2006.162.08:15:30.95#ibcon#first serial, iclass 12, count 0 2006.162.08:15:30.95#ibcon#enter sib2, iclass 12, count 0 2006.162.08:15:30.95#ibcon#flushed, iclass 12, count 0 2006.162.08:15:30.95#ibcon#about to write, iclass 12, count 0 2006.162.08:15:30.95#ibcon#wrote, iclass 12, count 0 2006.162.08:15:30.95#ibcon#about to read 3, iclass 12, count 0 2006.162.08:15:30.97#ibcon#read 3, iclass 12, count 0 2006.162.08:15:30.97#ibcon#about to read 4, iclass 12, count 0 2006.162.08:15:30.97#ibcon#read 4, iclass 12, count 0 2006.162.08:15:30.97#ibcon#about to read 5, iclass 12, count 0 2006.162.08:15:30.97#ibcon#read 5, iclass 12, count 0 2006.162.08:15:30.97#ibcon#about to read 6, iclass 12, count 0 2006.162.08:15:30.97#ibcon#read 6, iclass 12, count 0 2006.162.08:15:30.97#ibcon#end of sib2, iclass 12, count 0 2006.162.08:15:30.97#ibcon#*mode == 0, iclass 12, count 0 2006.162.08:15:30.97#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.162.08:15:30.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.08:15:30.97#ibcon#*before write, iclass 12, count 0 2006.162.08:15:30.97#ibcon#enter sib2, iclass 12, count 0 2006.162.08:15:30.97#ibcon#flushed, iclass 12, count 0 2006.162.08:15:30.97#ibcon#about to write, iclass 12, count 0 2006.162.08:15:30.97#ibcon#wrote, iclass 12, count 0 2006.162.08:15:30.97#ibcon#about to read 3, iclass 12, count 0 2006.162.08:15:31.01#ibcon#read 3, iclass 12, count 0 2006.162.08:15:31.01#ibcon#about to read 4, iclass 12, count 0 2006.162.08:15:31.01#ibcon#read 4, iclass 12, count 0 2006.162.08:15:31.01#ibcon#about to read 5, iclass 12, count 0 2006.162.08:15:31.01#ibcon#read 5, iclass 12, count 0 2006.162.08:15:31.01#ibcon#about to read 6, iclass 12, count 0 2006.162.08:15:31.01#ibcon#read 6, iclass 12, count 0 2006.162.08:15:31.01#ibcon#end of sib2, iclass 12, count 0 2006.162.08:15:31.01#ibcon#*after write, iclass 12, count 0 2006.162.08:15:31.01#ibcon#*before return 0, iclass 12, count 0 2006.162.08:15:31.01#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:15:31.01#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:15:31.01#ibcon#about to clear, iclass 12 cls_cnt 0 2006.162.08:15:31.01#ibcon#cleared, iclass 12 cls_cnt 0 2006.162.08:15:31.01$vc4f8/va=7,6 2006.162.08:15:31.01#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.162.08:15:31.01#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.162.08:15:31.01#ibcon#ireg 11 cls_cnt 2 2006.162.08:15:31.01#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.162.08:15:31.07#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.162.08:15:31.07#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.162.08:15:31.07#ibcon#enter wrdev, iclass 14, count 2 2006.162.08:15:31.07#ibcon#first serial, iclass 14, count 2 2006.162.08:15:31.07#ibcon#enter sib2, iclass 14, count 2 2006.162.08:15:31.07#ibcon#flushed, iclass 14, count 2 2006.162.08:15:31.07#ibcon#about to write, iclass 14, count 2 2006.162.08:15:31.07#ibcon#wrote, iclass 14, count 2 2006.162.08:15:31.07#ibcon#about to read 3, iclass 14, count 2 2006.162.08:15:31.09#ibcon#read 3, iclass 14, count 2 2006.162.08:15:31.09#ibcon#about to read 4, iclass 14, count 2 2006.162.08:15:31.09#ibcon#read 4, iclass 14, count 2 2006.162.08:15:31.09#ibcon#about to read 5, iclass 14, count 2 2006.162.08:15:31.09#ibcon#read 5, iclass 14, count 2 2006.162.08:15:31.09#ibcon#about to read 6, iclass 14, count 2 2006.162.08:15:31.09#ibcon#read 6, iclass 14, count 2 2006.162.08:15:31.09#ibcon#end of sib2, iclass 14, count 2 2006.162.08:15:31.09#ibcon#*mode == 0, iclass 14, count 2 2006.162.08:15:31.09#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.162.08:15:31.09#ibcon#[25=AT07-06\r\n] 2006.162.08:15:31.09#ibcon#*before write, iclass 14, count 2 2006.162.08:15:31.09#ibcon#enter sib2, iclass 14, count 2 2006.162.08:15:31.09#ibcon#flushed, iclass 14, count 2 2006.162.08:15:31.09#ibcon#about to write, iclass 14, count 2 2006.162.08:15:31.09#ibcon#wrote, iclass 14, count 2 2006.162.08:15:31.09#ibcon#about to read 3, iclass 14, count 2 2006.162.08:15:31.12#ibcon#read 3, iclass 14, count 2 2006.162.08:15:31.12#ibcon#about to read 4, iclass 14, count 2 2006.162.08:15:31.12#ibcon#read 4, iclass 14, count 2 2006.162.08:15:31.12#ibcon#about to read 5, iclass 14, count 2 2006.162.08:15:31.12#ibcon#read 5, iclass 14, count 2 2006.162.08:15:31.12#ibcon#about to read 6, iclass 14, count 2 2006.162.08:15:31.12#ibcon#read 6, iclass 14, count 2 2006.162.08:15:31.12#ibcon#end of sib2, iclass 14, count 2 2006.162.08:15:31.12#ibcon#*after write, iclass 14, count 2 2006.162.08:15:31.12#ibcon#*before return 0, iclass 14, count 2 2006.162.08:15:31.12#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.162.08:15:31.12#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.162.08:15:31.12#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.162.08:15:31.12#ibcon#ireg 7 cls_cnt 0 2006.162.08:15:31.12#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.162.08:15:31.24#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.162.08:15:31.24#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.162.08:15:31.24#ibcon#enter wrdev, iclass 14, count 0 2006.162.08:15:31.24#ibcon#first serial, iclass 14, count 0 2006.162.08:15:31.24#ibcon#enter sib2, iclass 14, count 0 2006.162.08:15:31.24#ibcon#flushed, iclass 14, count 0 2006.162.08:15:31.24#ibcon#about to write, iclass 14, count 0 2006.162.08:15:31.24#ibcon#wrote, iclass 14, count 0 2006.162.08:15:31.24#ibcon#about to read 3, iclass 14, count 0 2006.162.08:15:31.26#ibcon#read 3, iclass 14, count 0 2006.162.08:15:31.26#ibcon#about to read 4, iclass 14, count 0 2006.162.08:15:31.26#ibcon#read 4, iclass 14, count 0 2006.162.08:15:31.26#ibcon#about to read 5, iclass 14, count 0 2006.162.08:15:31.26#ibcon#read 5, iclass 14, count 0 2006.162.08:15:31.26#ibcon#about to read 6, iclass 14, count 0 2006.162.08:15:31.26#ibcon#read 6, iclass 14, count 0 2006.162.08:15:31.26#ibcon#end of sib2, iclass 14, count 0 2006.162.08:15:31.26#ibcon#*mode == 0, iclass 14, count 0 2006.162.08:15:31.26#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.08:15:31.26#ibcon#[25=USB\r\n] 2006.162.08:15:31.26#ibcon#*before write, iclass 14, count 0 2006.162.08:15:31.26#ibcon#enter sib2, iclass 14, count 0 2006.162.08:15:31.26#ibcon#flushed, iclass 14, count 0 2006.162.08:15:31.26#ibcon#about to write, iclass 14, count 0 2006.162.08:15:31.26#ibcon#wrote, iclass 14, count 0 2006.162.08:15:31.26#ibcon#about to read 3, iclass 14, count 0 2006.162.08:15:31.29#ibcon#read 3, iclass 14, count 0 2006.162.08:15:31.29#ibcon#about to read 4, iclass 14, count 0 2006.162.08:15:31.29#ibcon#read 4, iclass 14, count 0 2006.162.08:15:31.29#ibcon#about to read 5, iclass 14, count 0 2006.162.08:15:31.29#ibcon#read 5, iclass 14, count 0 2006.162.08:15:31.29#ibcon#about to read 6, iclass 14, count 0 2006.162.08:15:31.29#ibcon#read 6, iclass 14, count 0 2006.162.08:15:31.29#ibcon#end of sib2, iclass 14, count 0 2006.162.08:15:31.29#ibcon#*after write, iclass 14, count 0 2006.162.08:15:31.29#ibcon#*before return 0, iclass 14, count 0 2006.162.08:15:31.29#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.162.08:15:31.29#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.162.08:15:31.29#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.08:15:31.29#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.08:15:31.29$vc4f8/valo=8,852.99 2006.162.08:15:31.29#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.162.08:15:31.29#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.162.08:15:31.29#ibcon#ireg 17 cls_cnt 0 2006.162.08:15:31.29#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:15:31.29#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:15:31.29#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:15:31.29#ibcon#enter wrdev, iclass 16, count 0 2006.162.08:15:31.29#ibcon#first serial, iclass 16, count 0 2006.162.08:15:31.29#ibcon#enter sib2, iclass 16, count 0 2006.162.08:15:31.29#ibcon#flushed, iclass 16, count 0 2006.162.08:15:31.29#ibcon#about to write, iclass 16, count 0 2006.162.08:15:31.29#ibcon#wrote, iclass 16, count 0 2006.162.08:15:31.29#ibcon#about to read 3, iclass 16, count 0 2006.162.08:15:31.31#ibcon#read 3, iclass 16, count 0 2006.162.08:15:31.31#ibcon#about to read 4, iclass 16, count 0 2006.162.08:15:31.31#ibcon#read 4, iclass 16, count 0 2006.162.08:15:31.31#ibcon#about to read 5, iclass 16, count 0 2006.162.08:15:31.31#ibcon#read 5, iclass 16, count 0 2006.162.08:15:31.31#ibcon#about to read 6, iclass 16, count 0 2006.162.08:15:31.31#ibcon#read 6, iclass 16, count 0 2006.162.08:15:31.31#ibcon#end of sib2, iclass 16, count 0 2006.162.08:15:31.31#ibcon#*mode == 0, iclass 16, count 0 2006.162.08:15:31.31#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.162.08:15:31.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.08:15:31.31#ibcon#*before write, iclass 16, count 0 2006.162.08:15:31.31#ibcon#enter sib2, iclass 16, count 0 2006.162.08:15:31.31#ibcon#flushed, iclass 16, count 0 2006.162.08:15:31.31#ibcon#about to write, iclass 16, count 0 2006.162.08:15:31.31#ibcon#wrote, iclass 16, count 0 2006.162.08:15:31.31#ibcon#about to read 3, iclass 16, count 0 2006.162.08:15:31.35#ibcon#read 3, iclass 16, count 0 2006.162.08:15:31.35#ibcon#about to read 4, iclass 16, count 0 2006.162.08:15:31.35#ibcon#read 4, iclass 16, count 0 2006.162.08:15:31.35#ibcon#about to read 5, iclass 16, count 0 2006.162.08:15:31.35#ibcon#read 5, iclass 16, count 0 2006.162.08:15:31.35#ibcon#about to read 6, iclass 16, count 0 2006.162.08:15:31.35#ibcon#read 6, iclass 16, count 0 2006.162.08:15:31.35#ibcon#end of sib2, iclass 16, count 0 2006.162.08:15:31.35#ibcon#*after write, iclass 16, count 0 2006.162.08:15:31.35#ibcon#*before return 0, iclass 16, count 0 2006.162.08:15:31.35#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:15:31.35#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:15:31.35#ibcon#about to clear, iclass 16 cls_cnt 0 2006.162.08:15:31.35#ibcon#cleared, iclass 16 cls_cnt 0 2006.162.08:15:31.35$vc4f8/va=8,7 2006.162.08:15:31.35#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.162.08:15:31.35#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.162.08:15:31.35#ibcon#ireg 11 cls_cnt 2 2006.162.08:15:31.35#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:15:31.41#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:15:31.41#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:15:31.41#ibcon#enter wrdev, iclass 18, count 2 2006.162.08:15:31.41#ibcon#first serial, iclass 18, count 2 2006.162.08:15:31.41#ibcon#enter sib2, iclass 18, count 2 2006.162.08:15:31.41#ibcon#flushed, iclass 18, count 2 2006.162.08:15:31.41#ibcon#about to write, iclass 18, count 2 2006.162.08:15:31.41#ibcon#wrote, iclass 18, count 2 2006.162.08:15:31.41#ibcon#about to read 3, iclass 18, count 2 2006.162.08:15:31.43#ibcon#read 3, iclass 18, count 2 2006.162.08:15:31.43#ibcon#about to read 4, iclass 18, count 2 2006.162.08:15:31.43#ibcon#read 4, iclass 18, count 2 2006.162.08:15:31.43#ibcon#about to read 5, iclass 18, count 2 2006.162.08:15:31.43#ibcon#read 5, iclass 18, count 2 2006.162.08:15:31.43#ibcon#about to read 6, iclass 18, count 2 2006.162.08:15:31.43#ibcon#read 6, iclass 18, count 2 2006.162.08:15:31.43#ibcon#end of sib2, iclass 18, count 2 2006.162.08:15:31.43#ibcon#*mode == 0, iclass 18, count 2 2006.162.08:15:31.43#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.162.08:15:31.43#ibcon#[25=AT08-07\r\n] 2006.162.08:15:31.43#ibcon#*before write, iclass 18, count 2 2006.162.08:15:31.43#ibcon#enter sib2, iclass 18, count 2 2006.162.08:15:31.43#ibcon#flushed, iclass 18, count 2 2006.162.08:15:31.43#ibcon#about to write, iclass 18, count 2 2006.162.08:15:31.43#ibcon#wrote, iclass 18, count 2 2006.162.08:15:31.43#ibcon#about to read 3, iclass 18, count 2 2006.162.08:15:31.46#ibcon#read 3, iclass 18, count 2 2006.162.08:15:31.46#ibcon#about to read 4, iclass 18, count 2 2006.162.08:15:31.46#ibcon#read 4, iclass 18, count 2 2006.162.08:15:31.46#ibcon#about to read 5, iclass 18, count 2 2006.162.08:15:31.46#ibcon#read 5, iclass 18, count 2 2006.162.08:15:31.46#ibcon#about to read 6, iclass 18, count 2 2006.162.08:15:31.46#ibcon#read 6, iclass 18, count 2 2006.162.08:15:31.46#ibcon#end of sib2, iclass 18, count 2 2006.162.08:15:31.46#ibcon#*after write, iclass 18, count 2 2006.162.08:15:31.46#ibcon#*before return 0, iclass 18, count 2 2006.162.08:15:31.46#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:15:31.46#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:15:31.46#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.162.08:15:31.46#ibcon#ireg 7 cls_cnt 0 2006.162.08:15:31.46#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:15:31.58#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:15:31.58#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:15:31.58#ibcon#enter wrdev, iclass 18, count 0 2006.162.08:15:31.58#ibcon#first serial, iclass 18, count 0 2006.162.08:15:31.58#ibcon#enter sib2, iclass 18, count 0 2006.162.08:15:31.58#ibcon#flushed, iclass 18, count 0 2006.162.08:15:31.58#ibcon#about to write, iclass 18, count 0 2006.162.08:15:31.58#ibcon#wrote, iclass 18, count 0 2006.162.08:15:31.58#ibcon#about to read 3, iclass 18, count 0 2006.162.08:15:31.60#ibcon#read 3, iclass 18, count 0 2006.162.08:15:31.60#ibcon#about to read 4, iclass 18, count 0 2006.162.08:15:31.60#ibcon#read 4, iclass 18, count 0 2006.162.08:15:31.60#ibcon#about to read 5, iclass 18, count 0 2006.162.08:15:31.60#ibcon#read 5, iclass 18, count 0 2006.162.08:15:31.60#ibcon#about to read 6, iclass 18, count 0 2006.162.08:15:31.60#ibcon#read 6, iclass 18, count 0 2006.162.08:15:31.60#ibcon#end of sib2, iclass 18, count 0 2006.162.08:15:31.60#ibcon#*mode == 0, iclass 18, count 0 2006.162.08:15:31.60#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.162.08:15:31.60#ibcon#[25=USB\r\n] 2006.162.08:15:31.60#ibcon#*before write, iclass 18, count 0 2006.162.08:15:31.60#ibcon#enter sib2, iclass 18, count 0 2006.162.08:15:31.60#ibcon#flushed, iclass 18, count 0 2006.162.08:15:31.60#ibcon#about to write, iclass 18, count 0 2006.162.08:15:31.60#ibcon#wrote, iclass 18, count 0 2006.162.08:15:31.60#ibcon#about to read 3, iclass 18, count 0 2006.162.08:15:31.63#ibcon#read 3, iclass 18, count 0 2006.162.08:15:31.63#ibcon#about to read 4, iclass 18, count 0 2006.162.08:15:31.63#ibcon#read 4, iclass 18, count 0 2006.162.08:15:31.63#ibcon#about to read 5, iclass 18, count 0 2006.162.08:15:31.63#ibcon#read 5, iclass 18, count 0 2006.162.08:15:31.63#ibcon#about to read 6, iclass 18, count 0 2006.162.08:15:31.63#ibcon#read 6, iclass 18, count 0 2006.162.08:15:31.63#ibcon#end of sib2, iclass 18, count 0 2006.162.08:15:31.63#ibcon#*after write, iclass 18, count 0 2006.162.08:15:31.63#ibcon#*before return 0, iclass 18, count 0 2006.162.08:15:31.63#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:15:31.63#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:15:31.63#ibcon#about to clear, iclass 18 cls_cnt 0 2006.162.08:15:31.63#ibcon#cleared, iclass 18 cls_cnt 0 2006.162.08:15:31.63$vc4f8/vblo=1,632.99 2006.162.08:15:31.63#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.162.08:15:31.63#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.162.08:15:31.63#ibcon#ireg 17 cls_cnt 0 2006.162.08:15:31.63#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:15:31.63#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:15:31.63#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:15:31.63#ibcon#enter wrdev, iclass 20, count 0 2006.162.08:15:31.63#ibcon#first serial, iclass 20, count 0 2006.162.08:15:31.63#ibcon#enter sib2, iclass 20, count 0 2006.162.08:15:31.63#ibcon#flushed, iclass 20, count 0 2006.162.08:15:31.63#ibcon#about to write, iclass 20, count 0 2006.162.08:15:31.63#ibcon#wrote, iclass 20, count 0 2006.162.08:15:31.63#ibcon#about to read 3, iclass 20, count 0 2006.162.08:15:31.65#ibcon#read 3, iclass 20, count 0 2006.162.08:15:31.65#ibcon#about to read 4, iclass 20, count 0 2006.162.08:15:31.65#ibcon#read 4, iclass 20, count 0 2006.162.08:15:31.65#ibcon#about to read 5, iclass 20, count 0 2006.162.08:15:31.65#ibcon#read 5, iclass 20, count 0 2006.162.08:15:31.65#ibcon#about to read 6, iclass 20, count 0 2006.162.08:15:31.65#ibcon#read 6, iclass 20, count 0 2006.162.08:15:31.65#ibcon#end of sib2, iclass 20, count 0 2006.162.08:15:31.65#ibcon#*mode == 0, iclass 20, count 0 2006.162.08:15:31.65#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.08:15:31.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.08:15:31.65#ibcon#*before write, iclass 20, count 0 2006.162.08:15:31.65#ibcon#enter sib2, iclass 20, count 0 2006.162.08:15:31.65#ibcon#flushed, iclass 20, count 0 2006.162.08:15:31.65#ibcon#about to write, iclass 20, count 0 2006.162.08:15:31.65#ibcon#wrote, iclass 20, count 0 2006.162.08:15:31.65#ibcon#about to read 3, iclass 20, count 0 2006.162.08:15:31.69#ibcon#read 3, iclass 20, count 0 2006.162.08:15:31.69#ibcon#about to read 4, iclass 20, count 0 2006.162.08:15:31.69#ibcon#read 4, iclass 20, count 0 2006.162.08:15:31.69#ibcon#about to read 5, iclass 20, count 0 2006.162.08:15:31.69#ibcon#read 5, iclass 20, count 0 2006.162.08:15:31.69#ibcon#about to read 6, iclass 20, count 0 2006.162.08:15:31.69#ibcon#read 6, iclass 20, count 0 2006.162.08:15:31.69#ibcon#end of sib2, iclass 20, count 0 2006.162.08:15:31.69#ibcon#*after write, iclass 20, count 0 2006.162.08:15:31.69#ibcon#*before return 0, iclass 20, count 0 2006.162.08:15:31.69#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:15:31.69#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:15:31.69#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.08:15:31.69#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.08:15:31.69$vc4f8/vb=1,4 2006.162.08:15:31.69#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.162.08:15:31.69#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.162.08:15:31.69#ibcon#ireg 11 cls_cnt 2 2006.162.08:15:31.69#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:15:31.69#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:15:31.69#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:15:31.69#ibcon#enter wrdev, iclass 22, count 2 2006.162.08:15:31.69#ibcon#first serial, iclass 22, count 2 2006.162.08:15:31.69#ibcon#enter sib2, iclass 22, count 2 2006.162.08:15:31.69#ibcon#flushed, iclass 22, count 2 2006.162.08:15:31.69#ibcon#about to write, iclass 22, count 2 2006.162.08:15:31.69#ibcon#wrote, iclass 22, count 2 2006.162.08:15:31.69#ibcon#about to read 3, iclass 22, count 2 2006.162.08:15:31.71#ibcon#read 3, iclass 22, count 2 2006.162.08:15:31.71#ibcon#about to read 4, iclass 22, count 2 2006.162.08:15:31.71#ibcon#read 4, iclass 22, count 2 2006.162.08:15:31.71#ibcon#about to read 5, iclass 22, count 2 2006.162.08:15:31.71#ibcon#read 5, iclass 22, count 2 2006.162.08:15:31.71#ibcon#about to read 6, iclass 22, count 2 2006.162.08:15:31.71#ibcon#read 6, iclass 22, count 2 2006.162.08:15:31.71#ibcon#end of sib2, iclass 22, count 2 2006.162.08:15:31.71#ibcon#*mode == 0, iclass 22, count 2 2006.162.08:15:31.71#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.162.08:15:31.71#ibcon#[27=AT01-04\r\n] 2006.162.08:15:31.71#ibcon#*before write, iclass 22, count 2 2006.162.08:15:31.71#ibcon#enter sib2, iclass 22, count 2 2006.162.08:15:31.71#ibcon#flushed, iclass 22, count 2 2006.162.08:15:31.71#ibcon#about to write, iclass 22, count 2 2006.162.08:15:31.71#ibcon#wrote, iclass 22, count 2 2006.162.08:15:31.71#ibcon#about to read 3, iclass 22, count 2 2006.162.08:15:31.74#ibcon#read 3, iclass 22, count 2 2006.162.08:15:31.74#ibcon#about to read 4, iclass 22, count 2 2006.162.08:15:31.74#ibcon#read 4, iclass 22, count 2 2006.162.08:15:31.74#ibcon#about to read 5, iclass 22, count 2 2006.162.08:15:31.74#ibcon#read 5, iclass 22, count 2 2006.162.08:15:31.74#ibcon#about to read 6, iclass 22, count 2 2006.162.08:15:31.74#ibcon#read 6, iclass 22, count 2 2006.162.08:15:31.74#ibcon#end of sib2, iclass 22, count 2 2006.162.08:15:31.74#ibcon#*after write, iclass 22, count 2 2006.162.08:15:31.74#ibcon#*before return 0, iclass 22, count 2 2006.162.08:15:31.74#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:15:31.74#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:15:31.74#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.162.08:15:31.74#ibcon#ireg 7 cls_cnt 0 2006.162.08:15:31.74#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:15:31.86#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:15:31.86#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:15:31.86#ibcon#enter wrdev, iclass 22, count 0 2006.162.08:15:31.86#ibcon#first serial, iclass 22, count 0 2006.162.08:15:31.86#ibcon#enter sib2, iclass 22, count 0 2006.162.08:15:31.86#ibcon#flushed, iclass 22, count 0 2006.162.08:15:31.86#ibcon#about to write, iclass 22, count 0 2006.162.08:15:31.86#ibcon#wrote, iclass 22, count 0 2006.162.08:15:31.86#ibcon#about to read 3, iclass 22, count 0 2006.162.08:15:31.88#ibcon#read 3, iclass 22, count 0 2006.162.08:15:31.88#ibcon#about to read 4, iclass 22, count 0 2006.162.08:15:31.88#ibcon#read 4, iclass 22, count 0 2006.162.08:15:31.88#ibcon#about to read 5, iclass 22, count 0 2006.162.08:15:31.88#ibcon#read 5, iclass 22, count 0 2006.162.08:15:31.88#ibcon#about to read 6, iclass 22, count 0 2006.162.08:15:31.88#ibcon#read 6, iclass 22, count 0 2006.162.08:15:31.88#ibcon#end of sib2, iclass 22, count 0 2006.162.08:15:31.88#ibcon#*mode == 0, iclass 22, count 0 2006.162.08:15:31.88#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.08:15:31.88#ibcon#[27=USB\r\n] 2006.162.08:15:31.88#ibcon#*before write, iclass 22, count 0 2006.162.08:15:31.88#ibcon#enter sib2, iclass 22, count 0 2006.162.08:15:31.88#ibcon#flushed, iclass 22, count 0 2006.162.08:15:31.88#ibcon#about to write, iclass 22, count 0 2006.162.08:15:31.88#ibcon#wrote, iclass 22, count 0 2006.162.08:15:31.88#ibcon#about to read 3, iclass 22, count 0 2006.162.08:15:31.91#ibcon#read 3, iclass 22, count 0 2006.162.08:15:31.91#ibcon#about to read 4, iclass 22, count 0 2006.162.08:15:31.91#ibcon#read 4, iclass 22, count 0 2006.162.08:15:31.91#ibcon#about to read 5, iclass 22, count 0 2006.162.08:15:31.91#ibcon#read 5, iclass 22, count 0 2006.162.08:15:31.91#ibcon#about to read 6, iclass 22, count 0 2006.162.08:15:31.91#ibcon#read 6, iclass 22, count 0 2006.162.08:15:31.91#ibcon#end of sib2, iclass 22, count 0 2006.162.08:15:31.91#ibcon#*after write, iclass 22, count 0 2006.162.08:15:31.91#ibcon#*before return 0, iclass 22, count 0 2006.162.08:15:31.91#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:15:31.91#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:15:31.91#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.08:15:31.91#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.08:15:31.91$vc4f8/vblo=2,640.99 2006.162.08:15:31.91#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.162.08:15:31.91#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.162.08:15:31.91#ibcon#ireg 17 cls_cnt 0 2006.162.08:15:31.91#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:15:31.91#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:15:31.91#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:15:31.91#ibcon#enter wrdev, iclass 24, count 0 2006.162.08:15:31.91#ibcon#first serial, iclass 24, count 0 2006.162.08:15:31.91#ibcon#enter sib2, iclass 24, count 0 2006.162.08:15:31.91#ibcon#flushed, iclass 24, count 0 2006.162.08:15:31.91#ibcon#about to write, iclass 24, count 0 2006.162.08:15:31.91#ibcon#wrote, iclass 24, count 0 2006.162.08:15:31.91#ibcon#about to read 3, iclass 24, count 0 2006.162.08:15:31.93#ibcon#read 3, iclass 24, count 0 2006.162.08:15:31.93#ibcon#about to read 4, iclass 24, count 0 2006.162.08:15:31.93#ibcon#read 4, iclass 24, count 0 2006.162.08:15:31.93#ibcon#about to read 5, iclass 24, count 0 2006.162.08:15:31.93#ibcon#read 5, iclass 24, count 0 2006.162.08:15:31.93#ibcon#about to read 6, iclass 24, count 0 2006.162.08:15:31.93#ibcon#read 6, iclass 24, count 0 2006.162.08:15:31.93#ibcon#end of sib2, iclass 24, count 0 2006.162.08:15:31.93#ibcon#*mode == 0, iclass 24, count 0 2006.162.08:15:31.93#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.08:15:31.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.08:15:31.93#ibcon#*before write, iclass 24, count 0 2006.162.08:15:31.93#ibcon#enter sib2, iclass 24, count 0 2006.162.08:15:31.93#ibcon#flushed, iclass 24, count 0 2006.162.08:15:31.93#ibcon#about to write, iclass 24, count 0 2006.162.08:15:31.93#ibcon#wrote, iclass 24, count 0 2006.162.08:15:31.93#ibcon#about to read 3, iclass 24, count 0 2006.162.08:15:31.97#ibcon#read 3, iclass 24, count 0 2006.162.08:15:31.97#ibcon#about to read 4, iclass 24, count 0 2006.162.08:15:31.97#ibcon#read 4, iclass 24, count 0 2006.162.08:15:31.97#ibcon#about to read 5, iclass 24, count 0 2006.162.08:15:31.97#ibcon#read 5, iclass 24, count 0 2006.162.08:15:31.97#ibcon#about to read 6, iclass 24, count 0 2006.162.08:15:31.97#ibcon#read 6, iclass 24, count 0 2006.162.08:15:31.97#ibcon#end of sib2, iclass 24, count 0 2006.162.08:15:31.97#ibcon#*after write, iclass 24, count 0 2006.162.08:15:31.97#ibcon#*before return 0, iclass 24, count 0 2006.162.08:15:31.97#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:15:31.97#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:15:31.97#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.08:15:31.97#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.08:15:31.97$vc4f8/vb=2,4 2006.162.08:15:31.97#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.162.08:15:31.97#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.162.08:15:31.97#ibcon#ireg 11 cls_cnt 2 2006.162.08:15:31.97#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:15:32.03#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:15:32.03#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:15:32.03#ibcon#enter wrdev, iclass 26, count 2 2006.162.08:15:32.03#ibcon#first serial, iclass 26, count 2 2006.162.08:15:32.03#ibcon#enter sib2, iclass 26, count 2 2006.162.08:15:32.03#ibcon#flushed, iclass 26, count 2 2006.162.08:15:32.03#ibcon#about to write, iclass 26, count 2 2006.162.08:15:32.03#ibcon#wrote, iclass 26, count 2 2006.162.08:15:32.03#ibcon#about to read 3, iclass 26, count 2 2006.162.08:15:32.05#ibcon#read 3, iclass 26, count 2 2006.162.08:15:32.05#ibcon#about to read 4, iclass 26, count 2 2006.162.08:15:32.05#ibcon#read 4, iclass 26, count 2 2006.162.08:15:32.05#ibcon#about to read 5, iclass 26, count 2 2006.162.08:15:32.05#ibcon#read 5, iclass 26, count 2 2006.162.08:15:32.05#ibcon#about to read 6, iclass 26, count 2 2006.162.08:15:32.05#ibcon#read 6, iclass 26, count 2 2006.162.08:15:32.05#ibcon#end of sib2, iclass 26, count 2 2006.162.08:15:32.05#ibcon#*mode == 0, iclass 26, count 2 2006.162.08:15:32.05#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.162.08:15:32.05#ibcon#[27=AT02-04\r\n] 2006.162.08:15:32.05#ibcon#*before write, iclass 26, count 2 2006.162.08:15:32.05#ibcon#enter sib2, iclass 26, count 2 2006.162.08:15:32.05#ibcon#flushed, iclass 26, count 2 2006.162.08:15:32.05#ibcon#about to write, iclass 26, count 2 2006.162.08:15:32.05#ibcon#wrote, iclass 26, count 2 2006.162.08:15:32.05#ibcon#about to read 3, iclass 26, count 2 2006.162.08:15:32.08#ibcon#read 3, iclass 26, count 2 2006.162.08:15:32.08#ibcon#about to read 4, iclass 26, count 2 2006.162.08:15:32.08#ibcon#read 4, iclass 26, count 2 2006.162.08:15:32.08#ibcon#about to read 5, iclass 26, count 2 2006.162.08:15:32.08#ibcon#read 5, iclass 26, count 2 2006.162.08:15:32.08#ibcon#about to read 6, iclass 26, count 2 2006.162.08:15:32.08#ibcon#read 6, iclass 26, count 2 2006.162.08:15:32.08#ibcon#end of sib2, iclass 26, count 2 2006.162.08:15:32.08#ibcon#*after write, iclass 26, count 2 2006.162.08:15:32.08#ibcon#*before return 0, iclass 26, count 2 2006.162.08:15:32.08#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:15:32.08#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:15:32.08#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.162.08:15:32.08#ibcon#ireg 7 cls_cnt 0 2006.162.08:15:32.08#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:15:32.20#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:15:32.20#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:15:32.20#ibcon#enter wrdev, iclass 26, count 0 2006.162.08:15:32.20#ibcon#first serial, iclass 26, count 0 2006.162.08:15:32.20#ibcon#enter sib2, iclass 26, count 0 2006.162.08:15:32.20#ibcon#flushed, iclass 26, count 0 2006.162.08:15:32.20#ibcon#about to write, iclass 26, count 0 2006.162.08:15:32.20#ibcon#wrote, iclass 26, count 0 2006.162.08:15:32.20#ibcon#about to read 3, iclass 26, count 0 2006.162.08:15:32.22#ibcon#read 3, iclass 26, count 0 2006.162.08:15:32.22#ibcon#about to read 4, iclass 26, count 0 2006.162.08:15:32.22#ibcon#read 4, iclass 26, count 0 2006.162.08:15:32.22#ibcon#about to read 5, iclass 26, count 0 2006.162.08:15:32.22#ibcon#read 5, iclass 26, count 0 2006.162.08:15:32.22#ibcon#about to read 6, iclass 26, count 0 2006.162.08:15:32.22#ibcon#read 6, iclass 26, count 0 2006.162.08:15:32.22#ibcon#end of sib2, iclass 26, count 0 2006.162.08:15:32.22#ibcon#*mode == 0, iclass 26, count 0 2006.162.08:15:32.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.162.08:15:32.22#ibcon#[27=USB\r\n] 2006.162.08:15:32.22#ibcon#*before write, iclass 26, count 0 2006.162.08:15:32.22#ibcon#enter sib2, iclass 26, count 0 2006.162.08:15:32.22#ibcon#flushed, iclass 26, count 0 2006.162.08:15:32.22#ibcon#about to write, iclass 26, count 0 2006.162.08:15:32.22#ibcon#wrote, iclass 26, count 0 2006.162.08:15:32.22#ibcon#about to read 3, iclass 26, count 0 2006.162.08:15:32.25#ibcon#read 3, iclass 26, count 0 2006.162.08:15:32.25#ibcon#about to read 4, iclass 26, count 0 2006.162.08:15:32.25#ibcon#read 4, iclass 26, count 0 2006.162.08:15:32.25#ibcon#about to read 5, iclass 26, count 0 2006.162.08:15:32.25#ibcon#read 5, iclass 26, count 0 2006.162.08:15:32.25#ibcon#about to read 6, iclass 26, count 0 2006.162.08:15:32.25#ibcon#read 6, iclass 26, count 0 2006.162.08:15:32.25#ibcon#end of sib2, iclass 26, count 0 2006.162.08:15:32.25#ibcon#*after write, iclass 26, count 0 2006.162.08:15:32.25#ibcon#*before return 0, iclass 26, count 0 2006.162.08:15:32.25#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:15:32.25#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:15:32.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.162.08:15:32.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.162.08:15:32.25$vc4f8/vblo=3,656.99 2006.162.08:15:32.25#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.162.08:15:32.25#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.162.08:15:32.25#ibcon#ireg 17 cls_cnt 0 2006.162.08:15:32.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:15:32.25#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:15:32.25#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:15:32.25#ibcon#enter wrdev, iclass 28, count 0 2006.162.08:15:32.25#ibcon#first serial, iclass 28, count 0 2006.162.08:15:32.25#ibcon#enter sib2, iclass 28, count 0 2006.162.08:15:32.25#ibcon#flushed, iclass 28, count 0 2006.162.08:15:32.25#ibcon#about to write, iclass 28, count 0 2006.162.08:15:32.25#ibcon#wrote, iclass 28, count 0 2006.162.08:15:32.25#ibcon#about to read 3, iclass 28, count 0 2006.162.08:15:32.28#ibcon#read 3, iclass 28, count 0 2006.162.08:15:32.28#ibcon#about to read 4, iclass 28, count 0 2006.162.08:15:32.28#ibcon#read 4, iclass 28, count 0 2006.162.08:15:32.28#ibcon#about to read 5, iclass 28, count 0 2006.162.08:15:32.28#ibcon#read 5, iclass 28, count 0 2006.162.08:15:32.28#ibcon#about to read 6, iclass 28, count 0 2006.162.08:15:32.28#ibcon#read 6, iclass 28, count 0 2006.162.08:15:32.28#ibcon#end of sib2, iclass 28, count 0 2006.162.08:15:32.28#ibcon#*mode == 0, iclass 28, count 0 2006.162.08:15:32.28#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.162.08:15:32.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.08:15:32.28#ibcon#*before write, iclass 28, count 0 2006.162.08:15:32.28#ibcon#enter sib2, iclass 28, count 0 2006.162.08:15:32.28#ibcon#flushed, iclass 28, count 0 2006.162.08:15:32.28#ibcon#about to write, iclass 28, count 0 2006.162.08:15:32.28#ibcon#wrote, iclass 28, count 0 2006.162.08:15:32.28#ibcon#about to read 3, iclass 28, count 0 2006.162.08:15:32.32#ibcon#read 3, iclass 28, count 0 2006.162.08:15:32.32#ibcon#about to read 4, iclass 28, count 0 2006.162.08:15:32.32#ibcon#read 4, iclass 28, count 0 2006.162.08:15:32.32#ibcon#about to read 5, iclass 28, count 0 2006.162.08:15:32.32#ibcon#read 5, iclass 28, count 0 2006.162.08:15:32.32#ibcon#about to read 6, iclass 28, count 0 2006.162.08:15:32.32#ibcon#read 6, iclass 28, count 0 2006.162.08:15:32.32#ibcon#end of sib2, iclass 28, count 0 2006.162.08:15:32.32#ibcon#*after write, iclass 28, count 0 2006.162.08:15:32.32#ibcon#*before return 0, iclass 28, count 0 2006.162.08:15:32.32#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:15:32.32#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:15:32.32#ibcon#about to clear, iclass 28 cls_cnt 0 2006.162.08:15:32.32#ibcon#cleared, iclass 28 cls_cnt 0 2006.162.08:15:32.32$vc4f8/vb=3,4 2006.162.08:15:32.32#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.162.08:15:32.32#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.162.08:15:32.32#ibcon#ireg 11 cls_cnt 2 2006.162.08:15:32.32#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:15:32.37#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:15:32.37#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:15:32.37#ibcon#enter wrdev, iclass 30, count 2 2006.162.08:15:32.37#ibcon#first serial, iclass 30, count 2 2006.162.08:15:32.37#ibcon#enter sib2, iclass 30, count 2 2006.162.08:15:32.37#ibcon#flushed, iclass 30, count 2 2006.162.08:15:32.37#ibcon#about to write, iclass 30, count 2 2006.162.08:15:32.37#ibcon#wrote, iclass 30, count 2 2006.162.08:15:32.37#ibcon#about to read 3, iclass 30, count 2 2006.162.08:15:32.39#ibcon#read 3, iclass 30, count 2 2006.162.08:15:32.39#ibcon#about to read 4, iclass 30, count 2 2006.162.08:15:32.39#ibcon#read 4, iclass 30, count 2 2006.162.08:15:32.39#ibcon#about to read 5, iclass 30, count 2 2006.162.08:15:32.39#ibcon#read 5, iclass 30, count 2 2006.162.08:15:32.39#ibcon#about to read 6, iclass 30, count 2 2006.162.08:15:32.39#ibcon#read 6, iclass 30, count 2 2006.162.08:15:32.39#ibcon#end of sib2, iclass 30, count 2 2006.162.08:15:32.39#ibcon#*mode == 0, iclass 30, count 2 2006.162.08:15:32.39#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.162.08:15:32.39#ibcon#[27=AT03-04\r\n] 2006.162.08:15:32.39#ibcon#*before write, iclass 30, count 2 2006.162.08:15:32.39#ibcon#enter sib2, iclass 30, count 2 2006.162.08:15:32.39#ibcon#flushed, iclass 30, count 2 2006.162.08:15:32.39#ibcon#about to write, iclass 30, count 2 2006.162.08:15:32.39#ibcon#wrote, iclass 30, count 2 2006.162.08:15:32.39#ibcon#about to read 3, iclass 30, count 2 2006.162.08:15:32.42#ibcon#read 3, iclass 30, count 2 2006.162.08:15:32.42#ibcon#about to read 4, iclass 30, count 2 2006.162.08:15:32.42#ibcon#read 4, iclass 30, count 2 2006.162.08:15:32.42#ibcon#about to read 5, iclass 30, count 2 2006.162.08:15:32.42#ibcon#read 5, iclass 30, count 2 2006.162.08:15:32.42#ibcon#about to read 6, iclass 30, count 2 2006.162.08:15:32.42#ibcon#read 6, iclass 30, count 2 2006.162.08:15:32.42#ibcon#end of sib2, iclass 30, count 2 2006.162.08:15:32.42#ibcon#*after write, iclass 30, count 2 2006.162.08:15:32.42#ibcon#*before return 0, iclass 30, count 2 2006.162.08:15:32.42#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:15:32.42#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:15:32.42#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.162.08:15:32.42#ibcon#ireg 7 cls_cnt 0 2006.162.08:15:32.42#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:15:32.54#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:15:32.54#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:15:32.54#ibcon#enter wrdev, iclass 30, count 0 2006.162.08:15:32.54#ibcon#first serial, iclass 30, count 0 2006.162.08:15:32.54#ibcon#enter sib2, iclass 30, count 0 2006.162.08:15:32.54#ibcon#flushed, iclass 30, count 0 2006.162.08:15:32.54#ibcon#about to write, iclass 30, count 0 2006.162.08:15:32.54#ibcon#wrote, iclass 30, count 0 2006.162.08:15:32.54#ibcon#about to read 3, iclass 30, count 0 2006.162.08:15:32.56#ibcon#read 3, iclass 30, count 0 2006.162.08:15:32.56#ibcon#about to read 4, iclass 30, count 0 2006.162.08:15:32.56#ibcon#read 4, iclass 30, count 0 2006.162.08:15:32.56#ibcon#about to read 5, iclass 30, count 0 2006.162.08:15:32.56#ibcon#read 5, iclass 30, count 0 2006.162.08:15:32.56#ibcon#about to read 6, iclass 30, count 0 2006.162.08:15:32.56#ibcon#read 6, iclass 30, count 0 2006.162.08:15:32.56#ibcon#end of sib2, iclass 30, count 0 2006.162.08:15:32.56#ibcon#*mode == 0, iclass 30, count 0 2006.162.08:15:32.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.162.08:15:32.56#ibcon#[27=USB\r\n] 2006.162.08:15:32.56#ibcon#*before write, iclass 30, count 0 2006.162.08:15:32.56#ibcon#enter sib2, iclass 30, count 0 2006.162.08:15:32.56#ibcon#flushed, iclass 30, count 0 2006.162.08:15:32.56#ibcon#about to write, iclass 30, count 0 2006.162.08:15:32.56#ibcon#wrote, iclass 30, count 0 2006.162.08:15:32.56#ibcon#about to read 3, iclass 30, count 0 2006.162.08:15:32.59#ibcon#read 3, iclass 30, count 0 2006.162.08:15:32.59#ibcon#about to read 4, iclass 30, count 0 2006.162.08:15:32.59#ibcon#read 4, iclass 30, count 0 2006.162.08:15:32.59#ibcon#about to read 5, iclass 30, count 0 2006.162.08:15:32.59#ibcon#read 5, iclass 30, count 0 2006.162.08:15:32.59#ibcon#about to read 6, iclass 30, count 0 2006.162.08:15:32.59#ibcon#read 6, iclass 30, count 0 2006.162.08:15:32.59#ibcon#end of sib2, iclass 30, count 0 2006.162.08:15:32.59#ibcon#*after write, iclass 30, count 0 2006.162.08:15:32.59#ibcon#*before return 0, iclass 30, count 0 2006.162.08:15:32.59#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:15:32.59#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:15:32.59#ibcon#about to clear, iclass 30 cls_cnt 0 2006.162.08:15:32.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.162.08:15:32.59$vc4f8/vblo=4,712.99 2006.162.08:15:32.59#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.162.08:15:32.59#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.162.08:15:32.59#ibcon#ireg 17 cls_cnt 0 2006.162.08:15:32.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:15:32.59#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:15:32.59#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:15:32.59#ibcon#enter wrdev, iclass 33, count 0 2006.162.08:15:32.59#ibcon#first serial, iclass 33, count 0 2006.162.08:15:32.59#ibcon#enter sib2, iclass 33, count 0 2006.162.08:15:32.59#ibcon#flushed, iclass 33, count 0 2006.162.08:15:32.59#ibcon#about to write, iclass 33, count 0 2006.162.08:15:32.59#ibcon#wrote, iclass 33, count 0 2006.162.08:15:32.59#ibcon#about to read 3, iclass 33, count 0 2006.162.08:15:32.61#ibcon#read 3, iclass 33, count 0 2006.162.08:15:32.61#ibcon#about to read 4, iclass 33, count 0 2006.162.08:15:32.61#ibcon#read 4, iclass 33, count 0 2006.162.08:15:32.61#ibcon#about to read 5, iclass 33, count 0 2006.162.08:15:32.61#ibcon#read 5, iclass 33, count 0 2006.162.08:15:32.61#ibcon#about to read 6, iclass 33, count 0 2006.162.08:15:32.61#ibcon#read 6, iclass 33, count 0 2006.162.08:15:32.61#ibcon#end of sib2, iclass 33, count 0 2006.162.08:15:32.61#ibcon#*mode == 0, iclass 33, count 0 2006.162.08:15:32.61#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.162.08:15:32.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.08:15:32.61#ibcon#*before write, iclass 33, count 0 2006.162.08:15:32.61#ibcon#enter sib2, iclass 33, count 0 2006.162.08:15:32.61#ibcon#flushed, iclass 33, count 0 2006.162.08:15:32.61#ibcon#about to write, iclass 33, count 0 2006.162.08:15:32.61#ibcon#wrote, iclass 33, count 0 2006.162.08:15:32.61#ibcon#about to read 3, iclass 33, count 0 2006.162.08:15:32.61#abcon#<5=/03 1.3 3.5 17.911001007.0\r\n> 2006.162.08:15:32.63#abcon#{5=INTERFACE CLEAR} 2006.162.08:15:32.65#ibcon#read 3, iclass 33, count 0 2006.162.08:15:32.65#ibcon#about to read 4, iclass 33, count 0 2006.162.08:15:32.65#ibcon#read 4, iclass 33, count 0 2006.162.08:15:32.65#ibcon#about to read 5, iclass 33, count 0 2006.162.08:15:32.65#ibcon#read 5, iclass 33, count 0 2006.162.08:15:32.65#ibcon#about to read 6, iclass 33, count 0 2006.162.08:15:32.65#ibcon#read 6, iclass 33, count 0 2006.162.08:15:32.65#ibcon#end of sib2, iclass 33, count 0 2006.162.08:15:32.65#ibcon#*after write, iclass 33, count 0 2006.162.08:15:32.65#ibcon#*before return 0, iclass 33, count 0 2006.162.08:15:32.65#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:15:32.65#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:15:32.65#ibcon#about to clear, iclass 33 cls_cnt 0 2006.162.08:15:32.65#ibcon#cleared, iclass 33 cls_cnt 0 2006.162.08:15:32.65$vc4f8/vb=4,4 2006.162.08:15:32.65#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.162.08:15:32.65#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.162.08:15:32.65#ibcon#ireg 11 cls_cnt 2 2006.162.08:15:32.65#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.162.08:15:32.69#abcon#[5=S1D000X0/0*\r\n] 2006.162.08:15:32.71#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.162.08:15:32.71#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.162.08:15:32.71#ibcon#enter wrdev, iclass 37, count 2 2006.162.08:15:32.71#ibcon#first serial, iclass 37, count 2 2006.162.08:15:32.71#ibcon#enter sib2, iclass 37, count 2 2006.162.08:15:32.71#ibcon#flushed, iclass 37, count 2 2006.162.08:15:32.71#ibcon#about to write, iclass 37, count 2 2006.162.08:15:32.71#ibcon#wrote, iclass 37, count 2 2006.162.08:15:32.71#ibcon#about to read 3, iclass 37, count 2 2006.162.08:15:32.73#ibcon#read 3, iclass 37, count 2 2006.162.08:15:32.73#ibcon#about to read 4, iclass 37, count 2 2006.162.08:15:32.73#ibcon#read 4, iclass 37, count 2 2006.162.08:15:32.73#ibcon#about to read 5, iclass 37, count 2 2006.162.08:15:32.73#ibcon#read 5, iclass 37, count 2 2006.162.08:15:32.73#ibcon#about to read 6, iclass 37, count 2 2006.162.08:15:32.73#ibcon#read 6, iclass 37, count 2 2006.162.08:15:32.73#ibcon#end of sib2, iclass 37, count 2 2006.162.08:15:32.73#ibcon#*mode == 0, iclass 37, count 2 2006.162.08:15:32.73#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.162.08:15:32.73#ibcon#[27=AT04-04\r\n] 2006.162.08:15:32.73#ibcon#*before write, iclass 37, count 2 2006.162.08:15:32.73#ibcon#enter sib2, iclass 37, count 2 2006.162.08:15:32.73#ibcon#flushed, iclass 37, count 2 2006.162.08:15:32.73#ibcon#about to write, iclass 37, count 2 2006.162.08:15:32.73#ibcon#wrote, iclass 37, count 2 2006.162.08:15:32.73#ibcon#about to read 3, iclass 37, count 2 2006.162.08:15:32.76#ibcon#read 3, iclass 37, count 2 2006.162.08:15:32.76#ibcon#about to read 4, iclass 37, count 2 2006.162.08:15:32.76#ibcon#read 4, iclass 37, count 2 2006.162.08:15:32.76#ibcon#about to read 5, iclass 37, count 2 2006.162.08:15:32.76#ibcon#read 5, iclass 37, count 2 2006.162.08:15:32.76#ibcon#about to read 6, iclass 37, count 2 2006.162.08:15:32.76#ibcon#read 6, iclass 37, count 2 2006.162.08:15:32.76#ibcon#end of sib2, iclass 37, count 2 2006.162.08:15:32.76#ibcon#*after write, iclass 37, count 2 2006.162.08:15:32.76#ibcon#*before return 0, iclass 37, count 2 2006.162.08:15:32.76#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.162.08:15:32.76#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.162.08:15:32.76#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.162.08:15:32.76#ibcon#ireg 7 cls_cnt 0 2006.162.08:15:32.76#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.162.08:15:32.88#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.162.08:15:32.88#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.162.08:15:32.88#ibcon#enter wrdev, iclass 37, count 0 2006.162.08:15:32.88#ibcon#first serial, iclass 37, count 0 2006.162.08:15:32.88#ibcon#enter sib2, iclass 37, count 0 2006.162.08:15:32.88#ibcon#flushed, iclass 37, count 0 2006.162.08:15:32.88#ibcon#about to write, iclass 37, count 0 2006.162.08:15:32.88#ibcon#wrote, iclass 37, count 0 2006.162.08:15:32.88#ibcon#about to read 3, iclass 37, count 0 2006.162.08:15:32.90#ibcon#read 3, iclass 37, count 0 2006.162.08:15:32.90#ibcon#about to read 4, iclass 37, count 0 2006.162.08:15:32.90#ibcon#read 4, iclass 37, count 0 2006.162.08:15:32.90#ibcon#about to read 5, iclass 37, count 0 2006.162.08:15:32.90#ibcon#read 5, iclass 37, count 0 2006.162.08:15:32.90#ibcon#about to read 6, iclass 37, count 0 2006.162.08:15:32.90#ibcon#read 6, iclass 37, count 0 2006.162.08:15:32.90#ibcon#end of sib2, iclass 37, count 0 2006.162.08:15:32.90#ibcon#*mode == 0, iclass 37, count 0 2006.162.08:15:32.90#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.162.08:15:32.90#ibcon#[27=USB\r\n] 2006.162.08:15:32.90#ibcon#*before write, iclass 37, count 0 2006.162.08:15:32.90#ibcon#enter sib2, iclass 37, count 0 2006.162.08:15:32.90#ibcon#flushed, iclass 37, count 0 2006.162.08:15:32.90#ibcon#about to write, iclass 37, count 0 2006.162.08:15:32.90#ibcon#wrote, iclass 37, count 0 2006.162.08:15:32.90#ibcon#about to read 3, iclass 37, count 0 2006.162.08:15:32.93#ibcon#read 3, iclass 37, count 0 2006.162.08:15:32.93#ibcon#about to read 4, iclass 37, count 0 2006.162.08:15:32.93#ibcon#read 4, iclass 37, count 0 2006.162.08:15:32.93#ibcon#about to read 5, iclass 37, count 0 2006.162.08:15:32.93#ibcon#read 5, iclass 37, count 0 2006.162.08:15:32.93#ibcon#about to read 6, iclass 37, count 0 2006.162.08:15:32.93#ibcon#read 6, iclass 37, count 0 2006.162.08:15:32.93#ibcon#end of sib2, iclass 37, count 0 2006.162.08:15:32.93#ibcon#*after write, iclass 37, count 0 2006.162.08:15:32.93#ibcon#*before return 0, iclass 37, count 0 2006.162.08:15:32.93#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.162.08:15:32.93#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.162.08:15:32.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.162.08:15:32.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.162.08:15:32.93$vc4f8/vblo=5,744.99 2006.162.08:15:32.93#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.162.08:15:32.93#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.162.08:15:32.93#ibcon#ireg 17 cls_cnt 0 2006.162.08:15:32.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:15:32.93#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:15:32.93#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:15:32.93#ibcon#enter wrdev, iclass 40, count 0 2006.162.08:15:32.93#ibcon#first serial, iclass 40, count 0 2006.162.08:15:32.93#ibcon#enter sib2, iclass 40, count 0 2006.162.08:15:32.93#ibcon#flushed, iclass 40, count 0 2006.162.08:15:32.93#ibcon#about to write, iclass 40, count 0 2006.162.08:15:32.93#ibcon#wrote, iclass 40, count 0 2006.162.08:15:32.93#ibcon#about to read 3, iclass 40, count 0 2006.162.08:15:32.95#ibcon#read 3, iclass 40, count 0 2006.162.08:15:32.95#ibcon#about to read 4, iclass 40, count 0 2006.162.08:15:32.95#ibcon#read 4, iclass 40, count 0 2006.162.08:15:32.95#ibcon#about to read 5, iclass 40, count 0 2006.162.08:15:32.95#ibcon#read 5, iclass 40, count 0 2006.162.08:15:32.95#ibcon#about to read 6, iclass 40, count 0 2006.162.08:15:32.95#ibcon#read 6, iclass 40, count 0 2006.162.08:15:32.95#ibcon#end of sib2, iclass 40, count 0 2006.162.08:15:32.95#ibcon#*mode == 0, iclass 40, count 0 2006.162.08:15:32.95#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.162.08:15:32.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.08:15:32.95#ibcon#*before write, iclass 40, count 0 2006.162.08:15:32.95#ibcon#enter sib2, iclass 40, count 0 2006.162.08:15:32.95#ibcon#flushed, iclass 40, count 0 2006.162.08:15:32.95#ibcon#about to write, iclass 40, count 0 2006.162.08:15:32.95#ibcon#wrote, iclass 40, count 0 2006.162.08:15:32.95#ibcon#about to read 3, iclass 40, count 0 2006.162.08:15:32.99#ibcon#read 3, iclass 40, count 0 2006.162.08:15:32.99#ibcon#about to read 4, iclass 40, count 0 2006.162.08:15:32.99#ibcon#read 4, iclass 40, count 0 2006.162.08:15:32.99#ibcon#about to read 5, iclass 40, count 0 2006.162.08:15:32.99#ibcon#read 5, iclass 40, count 0 2006.162.08:15:32.99#ibcon#about to read 6, iclass 40, count 0 2006.162.08:15:32.99#ibcon#read 6, iclass 40, count 0 2006.162.08:15:32.99#ibcon#end of sib2, iclass 40, count 0 2006.162.08:15:32.99#ibcon#*after write, iclass 40, count 0 2006.162.08:15:32.99#ibcon#*before return 0, iclass 40, count 0 2006.162.08:15:32.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:15:32.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:15:32.99#ibcon#about to clear, iclass 40 cls_cnt 0 2006.162.08:15:32.99#ibcon#cleared, iclass 40 cls_cnt 0 2006.162.08:15:32.99$vc4f8/vb=5,4 2006.162.08:15:32.99#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.162.08:15:32.99#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.162.08:15:32.99#ibcon#ireg 11 cls_cnt 2 2006.162.08:15:32.99#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:15:33.05#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:15:33.05#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:15:33.05#ibcon#enter wrdev, iclass 4, count 2 2006.162.08:15:33.05#ibcon#first serial, iclass 4, count 2 2006.162.08:15:33.05#ibcon#enter sib2, iclass 4, count 2 2006.162.08:15:33.05#ibcon#flushed, iclass 4, count 2 2006.162.08:15:33.05#ibcon#about to write, iclass 4, count 2 2006.162.08:15:33.05#ibcon#wrote, iclass 4, count 2 2006.162.08:15:33.05#ibcon#about to read 3, iclass 4, count 2 2006.162.08:15:33.07#ibcon#read 3, iclass 4, count 2 2006.162.08:15:33.07#ibcon#about to read 4, iclass 4, count 2 2006.162.08:15:33.07#ibcon#read 4, iclass 4, count 2 2006.162.08:15:33.07#ibcon#about to read 5, iclass 4, count 2 2006.162.08:15:33.07#ibcon#read 5, iclass 4, count 2 2006.162.08:15:33.07#ibcon#about to read 6, iclass 4, count 2 2006.162.08:15:33.07#ibcon#read 6, iclass 4, count 2 2006.162.08:15:33.07#ibcon#end of sib2, iclass 4, count 2 2006.162.08:15:33.07#ibcon#*mode == 0, iclass 4, count 2 2006.162.08:15:33.07#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.162.08:15:33.07#ibcon#[27=AT05-04\r\n] 2006.162.08:15:33.07#ibcon#*before write, iclass 4, count 2 2006.162.08:15:33.07#ibcon#enter sib2, iclass 4, count 2 2006.162.08:15:33.07#ibcon#flushed, iclass 4, count 2 2006.162.08:15:33.07#ibcon#about to write, iclass 4, count 2 2006.162.08:15:33.07#ibcon#wrote, iclass 4, count 2 2006.162.08:15:33.07#ibcon#about to read 3, iclass 4, count 2 2006.162.08:15:33.10#ibcon#read 3, iclass 4, count 2 2006.162.08:15:33.10#ibcon#about to read 4, iclass 4, count 2 2006.162.08:15:33.10#ibcon#read 4, iclass 4, count 2 2006.162.08:15:33.10#ibcon#about to read 5, iclass 4, count 2 2006.162.08:15:33.10#ibcon#read 5, iclass 4, count 2 2006.162.08:15:33.10#ibcon#about to read 6, iclass 4, count 2 2006.162.08:15:33.10#ibcon#read 6, iclass 4, count 2 2006.162.08:15:33.10#ibcon#end of sib2, iclass 4, count 2 2006.162.08:15:33.10#ibcon#*after write, iclass 4, count 2 2006.162.08:15:33.10#ibcon#*before return 0, iclass 4, count 2 2006.162.08:15:33.10#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:15:33.10#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:15:33.10#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.162.08:15:33.10#ibcon#ireg 7 cls_cnt 0 2006.162.08:15:33.10#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:15:33.22#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:15:33.22#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:15:33.22#ibcon#enter wrdev, iclass 4, count 0 2006.162.08:15:33.22#ibcon#first serial, iclass 4, count 0 2006.162.08:15:33.22#ibcon#enter sib2, iclass 4, count 0 2006.162.08:15:33.22#ibcon#flushed, iclass 4, count 0 2006.162.08:15:33.22#ibcon#about to write, iclass 4, count 0 2006.162.08:15:33.22#ibcon#wrote, iclass 4, count 0 2006.162.08:15:33.22#ibcon#about to read 3, iclass 4, count 0 2006.162.08:15:33.24#ibcon#read 3, iclass 4, count 0 2006.162.08:15:33.24#ibcon#about to read 4, iclass 4, count 0 2006.162.08:15:33.24#ibcon#read 4, iclass 4, count 0 2006.162.08:15:33.24#ibcon#about to read 5, iclass 4, count 0 2006.162.08:15:33.24#ibcon#read 5, iclass 4, count 0 2006.162.08:15:33.24#ibcon#about to read 6, iclass 4, count 0 2006.162.08:15:33.24#ibcon#read 6, iclass 4, count 0 2006.162.08:15:33.24#ibcon#end of sib2, iclass 4, count 0 2006.162.08:15:33.24#ibcon#*mode == 0, iclass 4, count 0 2006.162.08:15:33.24#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.162.08:15:33.24#ibcon#[27=USB\r\n] 2006.162.08:15:33.24#ibcon#*before write, iclass 4, count 0 2006.162.08:15:33.24#ibcon#enter sib2, iclass 4, count 0 2006.162.08:15:33.24#ibcon#flushed, iclass 4, count 0 2006.162.08:15:33.24#ibcon#about to write, iclass 4, count 0 2006.162.08:15:33.24#ibcon#wrote, iclass 4, count 0 2006.162.08:15:33.24#ibcon#about to read 3, iclass 4, count 0 2006.162.08:15:33.27#ibcon#read 3, iclass 4, count 0 2006.162.08:15:33.27#ibcon#about to read 4, iclass 4, count 0 2006.162.08:15:33.27#ibcon#read 4, iclass 4, count 0 2006.162.08:15:33.27#ibcon#about to read 5, iclass 4, count 0 2006.162.08:15:33.27#ibcon#read 5, iclass 4, count 0 2006.162.08:15:33.27#ibcon#about to read 6, iclass 4, count 0 2006.162.08:15:33.27#ibcon#read 6, iclass 4, count 0 2006.162.08:15:33.27#ibcon#end of sib2, iclass 4, count 0 2006.162.08:15:33.27#ibcon#*after write, iclass 4, count 0 2006.162.08:15:33.27#ibcon#*before return 0, iclass 4, count 0 2006.162.08:15:33.27#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:15:33.27#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:15:33.27#ibcon#about to clear, iclass 4 cls_cnt 0 2006.162.08:15:33.27#ibcon#cleared, iclass 4 cls_cnt 0 2006.162.08:15:33.27$vc4f8/vblo=6,752.99 2006.162.08:15:33.27#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.162.08:15:33.27#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.162.08:15:33.27#ibcon#ireg 17 cls_cnt 0 2006.162.08:15:33.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:15:33.27#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:15:33.27#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:15:33.27#ibcon#enter wrdev, iclass 6, count 0 2006.162.08:15:33.27#ibcon#first serial, iclass 6, count 0 2006.162.08:15:33.27#ibcon#enter sib2, iclass 6, count 0 2006.162.08:15:33.27#ibcon#flushed, iclass 6, count 0 2006.162.08:15:33.27#ibcon#about to write, iclass 6, count 0 2006.162.08:15:33.27#ibcon#wrote, iclass 6, count 0 2006.162.08:15:33.27#ibcon#about to read 3, iclass 6, count 0 2006.162.08:15:33.29#ibcon#read 3, iclass 6, count 0 2006.162.08:15:33.29#ibcon#about to read 4, iclass 6, count 0 2006.162.08:15:33.29#ibcon#read 4, iclass 6, count 0 2006.162.08:15:33.29#ibcon#about to read 5, iclass 6, count 0 2006.162.08:15:33.29#ibcon#read 5, iclass 6, count 0 2006.162.08:15:33.29#ibcon#about to read 6, iclass 6, count 0 2006.162.08:15:33.29#ibcon#read 6, iclass 6, count 0 2006.162.08:15:33.29#ibcon#end of sib2, iclass 6, count 0 2006.162.08:15:33.29#ibcon#*mode == 0, iclass 6, count 0 2006.162.08:15:33.29#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.162.08:15:33.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.08:15:33.29#ibcon#*before write, iclass 6, count 0 2006.162.08:15:33.29#ibcon#enter sib2, iclass 6, count 0 2006.162.08:15:33.29#ibcon#flushed, iclass 6, count 0 2006.162.08:15:33.29#ibcon#about to write, iclass 6, count 0 2006.162.08:15:33.29#ibcon#wrote, iclass 6, count 0 2006.162.08:15:33.29#ibcon#about to read 3, iclass 6, count 0 2006.162.08:15:33.33#ibcon#read 3, iclass 6, count 0 2006.162.08:15:33.33#ibcon#about to read 4, iclass 6, count 0 2006.162.08:15:33.33#ibcon#read 4, iclass 6, count 0 2006.162.08:15:33.33#ibcon#about to read 5, iclass 6, count 0 2006.162.08:15:33.33#ibcon#read 5, iclass 6, count 0 2006.162.08:15:33.33#ibcon#about to read 6, iclass 6, count 0 2006.162.08:15:33.33#ibcon#read 6, iclass 6, count 0 2006.162.08:15:33.33#ibcon#end of sib2, iclass 6, count 0 2006.162.08:15:33.33#ibcon#*after write, iclass 6, count 0 2006.162.08:15:33.33#ibcon#*before return 0, iclass 6, count 0 2006.162.08:15:33.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:15:33.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:15:33.33#ibcon#about to clear, iclass 6 cls_cnt 0 2006.162.08:15:33.33#ibcon#cleared, iclass 6 cls_cnt 0 2006.162.08:15:33.33$vc4f8/vb=6,4 2006.162.08:15:33.33#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.162.08:15:33.33#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.162.08:15:33.33#ibcon#ireg 11 cls_cnt 2 2006.162.08:15:33.33#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:15:33.39#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:15:33.39#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:15:33.39#ibcon#enter wrdev, iclass 10, count 2 2006.162.08:15:33.39#ibcon#first serial, iclass 10, count 2 2006.162.08:15:33.39#ibcon#enter sib2, iclass 10, count 2 2006.162.08:15:33.39#ibcon#flushed, iclass 10, count 2 2006.162.08:15:33.39#ibcon#about to write, iclass 10, count 2 2006.162.08:15:33.39#ibcon#wrote, iclass 10, count 2 2006.162.08:15:33.39#ibcon#about to read 3, iclass 10, count 2 2006.162.08:15:33.41#ibcon#read 3, iclass 10, count 2 2006.162.08:15:33.41#ibcon#about to read 4, iclass 10, count 2 2006.162.08:15:33.41#ibcon#read 4, iclass 10, count 2 2006.162.08:15:33.41#ibcon#about to read 5, iclass 10, count 2 2006.162.08:15:33.41#ibcon#read 5, iclass 10, count 2 2006.162.08:15:33.41#ibcon#about to read 6, iclass 10, count 2 2006.162.08:15:33.41#ibcon#read 6, iclass 10, count 2 2006.162.08:15:33.41#ibcon#end of sib2, iclass 10, count 2 2006.162.08:15:33.41#ibcon#*mode == 0, iclass 10, count 2 2006.162.08:15:33.41#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.162.08:15:33.41#ibcon#[27=AT06-04\r\n] 2006.162.08:15:33.41#ibcon#*before write, iclass 10, count 2 2006.162.08:15:33.41#ibcon#enter sib2, iclass 10, count 2 2006.162.08:15:33.41#ibcon#flushed, iclass 10, count 2 2006.162.08:15:33.41#ibcon#about to write, iclass 10, count 2 2006.162.08:15:33.41#ibcon#wrote, iclass 10, count 2 2006.162.08:15:33.41#ibcon#about to read 3, iclass 10, count 2 2006.162.08:15:33.44#ibcon#read 3, iclass 10, count 2 2006.162.08:15:33.44#ibcon#about to read 4, iclass 10, count 2 2006.162.08:15:33.44#ibcon#read 4, iclass 10, count 2 2006.162.08:15:33.44#ibcon#about to read 5, iclass 10, count 2 2006.162.08:15:33.44#ibcon#read 5, iclass 10, count 2 2006.162.08:15:33.44#ibcon#about to read 6, iclass 10, count 2 2006.162.08:15:33.44#ibcon#read 6, iclass 10, count 2 2006.162.08:15:33.44#ibcon#end of sib2, iclass 10, count 2 2006.162.08:15:33.44#ibcon#*after write, iclass 10, count 2 2006.162.08:15:33.44#ibcon#*before return 0, iclass 10, count 2 2006.162.08:15:33.44#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:15:33.44#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:15:33.44#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.162.08:15:33.44#ibcon#ireg 7 cls_cnt 0 2006.162.08:15:33.44#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:15:33.56#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:15:33.56#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:15:33.56#ibcon#enter wrdev, iclass 10, count 0 2006.162.08:15:33.56#ibcon#first serial, iclass 10, count 0 2006.162.08:15:33.56#ibcon#enter sib2, iclass 10, count 0 2006.162.08:15:33.56#ibcon#flushed, iclass 10, count 0 2006.162.08:15:33.56#ibcon#about to write, iclass 10, count 0 2006.162.08:15:33.56#ibcon#wrote, iclass 10, count 0 2006.162.08:15:33.56#ibcon#about to read 3, iclass 10, count 0 2006.162.08:15:33.58#ibcon#read 3, iclass 10, count 0 2006.162.08:15:33.58#ibcon#about to read 4, iclass 10, count 0 2006.162.08:15:33.58#ibcon#read 4, iclass 10, count 0 2006.162.08:15:33.58#ibcon#about to read 5, iclass 10, count 0 2006.162.08:15:33.58#ibcon#read 5, iclass 10, count 0 2006.162.08:15:33.58#ibcon#about to read 6, iclass 10, count 0 2006.162.08:15:33.58#ibcon#read 6, iclass 10, count 0 2006.162.08:15:33.58#ibcon#end of sib2, iclass 10, count 0 2006.162.08:15:33.58#ibcon#*mode == 0, iclass 10, count 0 2006.162.08:15:33.58#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.162.08:15:33.58#ibcon#[27=USB\r\n] 2006.162.08:15:33.58#ibcon#*before write, iclass 10, count 0 2006.162.08:15:33.58#ibcon#enter sib2, iclass 10, count 0 2006.162.08:15:33.58#ibcon#flushed, iclass 10, count 0 2006.162.08:15:33.58#ibcon#about to write, iclass 10, count 0 2006.162.08:15:33.58#ibcon#wrote, iclass 10, count 0 2006.162.08:15:33.58#ibcon#about to read 3, iclass 10, count 0 2006.162.08:15:33.61#ibcon#read 3, iclass 10, count 0 2006.162.08:15:33.61#ibcon#about to read 4, iclass 10, count 0 2006.162.08:15:33.61#ibcon#read 4, iclass 10, count 0 2006.162.08:15:33.61#ibcon#about to read 5, iclass 10, count 0 2006.162.08:15:33.61#ibcon#read 5, iclass 10, count 0 2006.162.08:15:33.61#ibcon#about to read 6, iclass 10, count 0 2006.162.08:15:33.61#ibcon#read 6, iclass 10, count 0 2006.162.08:15:33.61#ibcon#end of sib2, iclass 10, count 0 2006.162.08:15:33.61#ibcon#*after write, iclass 10, count 0 2006.162.08:15:33.61#ibcon#*before return 0, iclass 10, count 0 2006.162.08:15:33.61#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:15:33.61#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:15:33.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.162.08:15:33.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.162.08:15:33.61$vc4f8/vabw=wide 2006.162.08:15:33.61#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.162.08:15:33.61#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.162.08:15:33.61#ibcon#ireg 8 cls_cnt 0 2006.162.08:15:33.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:15:33.61#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:15:33.61#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:15:33.61#ibcon#enter wrdev, iclass 12, count 0 2006.162.08:15:33.61#ibcon#first serial, iclass 12, count 0 2006.162.08:15:33.61#ibcon#enter sib2, iclass 12, count 0 2006.162.08:15:33.61#ibcon#flushed, iclass 12, count 0 2006.162.08:15:33.61#ibcon#about to write, iclass 12, count 0 2006.162.08:15:33.61#ibcon#wrote, iclass 12, count 0 2006.162.08:15:33.61#ibcon#about to read 3, iclass 12, count 0 2006.162.08:15:33.63#ibcon#read 3, iclass 12, count 0 2006.162.08:15:33.63#ibcon#about to read 4, iclass 12, count 0 2006.162.08:15:33.63#ibcon#read 4, iclass 12, count 0 2006.162.08:15:33.63#ibcon#about to read 5, iclass 12, count 0 2006.162.08:15:33.63#ibcon#read 5, iclass 12, count 0 2006.162.08:15:33.63#ibcon#about to read 6, iclass 12, count 0 2006.162.08:15:33.63#ibcon#read 6, iclass 12, count 0 2006.162.08:15:33.63#ibcon#end of sib2, iclass 12, count 0 2006.162.08:15:33.63#ibcon#*mode == 0, iclass 12, count 0 2006.162.08:15:33.63#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.162.08:15:33.63#ibcon#[25=BW32\r\n] 2006.162.08:15:33.63#ibcon#*before write, iclass 12, count 0 2006.162.08:15:33.63#ibcon#enter sib2, iclass 12, count 0 2006.162.08:15:33.63#ibcon#flushed, iclass 12, count 0 2006.162.08:15:33.63#ibcon#about to write, iclass 12, count 0 2006.162.08:15:33.63#ibcon#wrote, iclass 12, count 0 2006.162.08:15:33.63#ibcon#about to read 3, iclass 12, count 0 2006.162.08:15:33.66#ibcon#read 3, iclass 12, count 0 2006.162.08:15:33.66#ibcon#about to read 4, iclass 12, count 0 2006.162.08:15:33.66#ibcon#read 4, iclass 12, count 0 2006.162.08:15:33.66#ibcon#about to read 5, iclass 12, count 0 2006.162.08:15:33.66#ibcon#read 5, iclass 12, count 0 2006.162.08:15:33.66#ibcon#about to read 6, iclass 12, count 0 2006.162.08:15:33.66#ibcon#read 6, iclass 12, count 0 2006.162.08:15:33.66#ibcon#end of sib2, iclass 12, count 0 2006.162.08:15:33.66#ibcon#*after write, iclass 12, count 0 2006.162.08:15:33.66#ibcon#*before return 0, iclass 12, count 0 2006.162.08:15:33.66#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:15:33.66#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:15:33.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.162.08:15:33.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.162.08:15:33.66$vc4f8/vbbw=wide 2006.162.08:15:33.66#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.162.08:15:33.66#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.162.08:15:33.66#ibcon#ireg 8 cls_cnt 0 2006.162.08:15:33.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:15:33.73#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:15:33.73#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:15:33.73#ibcon#enter wrdev, iclass 14, count 0 2006.162.08:15:33.73#ibcon#first serial, iclass 14, count 0 2006.162.08:15:33.73#ibcon#enter sib2, iclass 14, count 0 2006.162.08:15:33.73#ibcon#flushed, iclass 14, count 0 2006.162.08:15:33.73#ibcon#about to write, iclass 14, count 0 2006.162.08:15:33.73#ibcon#wrote, iclass 14, count 0 2006.162.08:15:33.73#ibcon#about to read 3, iclass 14, count 0 2006.162.08:15:33.75#ibcon#read 3, iclass 14, count 0 2006.162.08:15:33.75#ibcon#about to read 4, iclass 14, count 0 2006.162.08:15:33.75#ibcon#read 4, iclass 14, count 0 2006.162.08:15:33.75#ibcon#about to read 5, iclass 14, count 0 2006.162.08:15:33.75#ibcon#read 5, iclass 14, count 0 2006.162.08:15:33.75#ibcon#about to read 6, iclass 14, count 0 2006.162.08:15:33.75#ibcon#read 6, iclass 14, count 0 2006.162.08:15:33.75#ibcon#end of sib2, iclass 14, count 0 2006.162.08:15:33.75#ibcon#*mode == 0, iclass 14, count 0 2006.162.08:15:33.75#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.08:15:33.75#ibcon#[27=BW32\r\n] 2006.162.08:15:33.75#ibcon#*before write, iclass 14, count 0 2006.162.08:15:33.75#ibcon#enter sib2, iclass 14, count 0 2006.162.08:15:33.75#ibcon#flushed, iclass 14, count 0 2006.162.08:15:33.75#ibcon#about to write, iclass 14, count 0 2006.162.08:15:33.75#ibcon#wrote, iclass 14, count 0 2006.162.08:15:33.75#ibcon#about to read 3, iclass 14, count 0 2006.162.08:15:33.78#ibcon#read 3, iclass 14, count 0 2006.162.08:15:33.78#ibcon#about to read 4, iclass 14, count 0 2006.162.08:15:33.78#ibcon#read 4, iclass 14, count 0 2006.162.08:15:33.78#ibcon#about to read 5, iclass 14, count 0 2006.162.08:15:33.78#ibcon#read 5, iclass 14, count 0 2006.162.08:15:33.78#ibcon#about to read 6, iclass 14, count 0 2006.162.08:15:33.78#ibcon#read 6, iclass 14, count 0 2006.162.08:15:33.78#ibcon#end of sib2, iclass 14, count 0 2006.162.08:15:33.78#ibcon#*after write, iclass 14, count 0 2006.162.08:15:33.78#ibcon#*before return 0, iclass 14, count 0 2006.162.08:15:33.78#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:15:33.78#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:15:33.78#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.08:15:33.78#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.08:15:33.78$4f8m12a/ifd4f 2006.162.08:15:33.78$ifd4f/lo= 2006.162.08:15:33.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.08:15:33.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.08:15:33.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.08:15:33.78$ifd4f/patch= 2006.162.08:15:33.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.08:15:33.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.08:15:33.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.08:15:33.78$4f8m12a/"form=m,16.000,1:2 2006.162.08:15:33.78$4f8m12a/"tpicd 2006.162.08:15:33.78$4f8m12a/echo=off 2006.162.08:15:33.78$4f8m12a/xlog=off 2006.162.08:15:33.78:!2006.162.08:16:00 2006.162.08:15:43.13#trakl#Source acquired 2006.162.08:15:45.13#flagr#flagr/antenna,acquired 2006.162.08:16:00.00:preob 2006.162.08:16:01.13/onsource/TRACKING 2006.162.08:16:01.13:!2006.162.08:16:10 2006.162.08:16:10.00:data_valid=on 2006.162.08:16:10.00:midob 2006.162.08:16:10.13/onsource/TRACKING 2006.162.08:16:10.13/wx/17.91,1007.0,100 2006.162.08:16:10.28/cable/+6.5359E-03 2006.162.08:16:11.37/va/01,08,usb,yes,35,36 2006.162.08:16:11.37/va/02,07,usb,yes,35,36 2006.162.08:16:11.37/va/03,06,usb,yes,37,37 2006.162.08:16:11.37/va/04,07,usb,yes,36,38 2006.162.08:16:11.37/va/05,07,usb,yes,38,40 2006.162.08:16:11.37/va/06,06,usb,yes,38,37 2006.162.08:16:11.37/va/07,06,usb,yes,38,38 2006.162.08:16:11.37/va/08,07,usb,yes,36,35 2006.162.08:16:11.60/valo/01,532.99,yes,locked 2006.162.08:16:11.60/valo/02,572.99,yes,locked 2006.162.08:16:11.60/valo/03,672.99,yes,locked 2006.162.08:16:11.60/valo/04,832.99,yes,locked 2006.162.08:16:11.60/valo/05,652.99,yes,locked 2006.162.08:16:11.60/valo/06,772.99,yes,locked 2006.162.08:16:11.60/valo/07,832.99,yes,locked 2006.162.08:16:11.60/valo/08,852.99,yes,locked 2006.162.08:16:12.69/vb/01,04,usb,yes,29,28 2006.162.08:16:12.69/vb/02,04,usb,yes,31,33 2006.162.08:16:12.69/vb/03,04,usb,yes,28,31 2006.162.08:16:12.69/vb/04,04,usb,yes,29,29 2006.162.08:16:12.69/vb/05,04,usb,yes,27,31 2006.162.08:16:12.69/vb/06,04,usb,yes,28,31 2006.162.08:16:12.69/vb/07,04,usb,yes,30,30 2006.162.08:16:12.69/vb/08,04,usb,yes,28,31 2006.162.08:16:12.92/vblo/01,632.99,yes,locked 2006.162.08:16:12.92/vblo/02,640.99,yes,locked 2006.162.08:16:12.92/vblo/03,656.99,yes,locked 2006.162.08:16:12.92/vblo/04,712.99,yes,locked 2006.162.08:16:12.92/vblo/05,744.99,yes,locked 2006.162.08:16:12.92/vblo/06,752.99,yes,locked 2006.162.08:16:12.92/vblo/07,734.99,yes,locked 2006.162.08:16:12.92/vblo/08,744.99,yes,locked 2006.162.08:16:13.07/vabw/8 2006.162.08:16:13.22/vbbw/8 2006.162.08:16:13.33/xfe/off,on,14.7 2006.162.08:16:13.75/ifatt/23,28,28,28 2006.162.08:16:14.08/fmout-gps/S +4.50E-07 2006.162.08:16:14.12:!2006.162.08:17:10 2006.162.08:17:10.00:data_valid=off 2006.162.08:17:10.00:postob 2006.162.08:17:10.09/cable/+6.5356E-03 2006.162.08:17:10.09/wx/17.89,1007.0,100 2006.162.08:17:11.08/fmout-gps/S +4.50E-07 2006.162.08:17:11.08:scan_name=162-0819,k06162,60 2006.162.08:17:11.09:source=1739+522,174036.98,521143.4,2000.0,cw 2006.162.08:17:11.14#flagr#flagr/antenna,new-source 2006.162.08:17:12.14:checkk5 2006.162.08:17:12.85/chk_autoobs//k5ts1/ autoobs is running! 2006.162.08:17:13.25/chk_autoobs//k5ts2/ autoobs is running! 2006.162.08:17:13.66/chk_autoobs//k5ts3/ autoobs is running! 2006.162.08:17:14.13/chk_autoobs//k5ts4/ autoobs is running! 2006.162.08:17:14.53/chk_obsdata//k5ts1/T1620816??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.162.08:17:15.15/chk_obsdata//k5ts2/T1620816??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.162.08:17:15.58/chk_obsdata//k5ts3/T1620816??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.162.08:17:16.00/chk_obsdata//k5ts4/T1620816??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.162.08:17:16.80/k5log//k5ts1_log_newline 2006.162.08:17:17.98/k5log//k5ts2_log_newline 2006.162.08:17:18.77/k5log//k5ts3_log_newline 2006.162.08:17:19.63/k5log//k5ts4_log_newline 2006.162.08:17:19.66/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.08:17:19.66:4f8m12a=3 2006.162.08:17:19.66$4f8m12a/echo=on 2006.162.08:17:19.66$4f8m12a/pcalon 2006.162.08:17:19.66$pcalon/"no phase cal control is implemented here 2006.162.08:17:19.66$4f8m12a/"tpicd=stop 2006.162.08:17:19.66$4f8m12a/vc4f8 2006.162.08:17:19.66$vc4f8/valo=1,532.99 2006.162.08:17:19.66#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.162.08:17:19.66#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.162.08:17:19.66#ibcon#ireg 17 cls_cnt 0 2006.162.08:17:19.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:17:19.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:17:19.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:17:19.66#ibcon#enter wrdev, iclass 21, count 0 2006.162.08:17:19.66#ibcon#first serial, iclass 21, count 0 2006.162.08:17:19.66#ibcon#enter sib2, iclass 21, count 0 2006.162.08:17:19.66#ibcon#flushed, iclass 21, count 0 2006.162.08:17:19.66#ibcon#about to write, iclass 21, count 0 2006.162.08:17:19.66#ibcon#wrote, iclass 21, count 0 2006.162.08:17:19.66#ibcon#about to read 3, iclass 21, count 0 2006.162.08:17:19.71#ibcon#read 3, iclass 21, count 0 2006.162.08:17:19.71#ibcon#about to read 4, iclass 21, count 0 2006.162.08:17:19.71#ibcon#read 4, iclass 21, count 0 2006.162.08:17:19.71#ibcon#about to read 5, iclass 21, count 0 2006.162.08:17:19.71#ibcon#read 5, iclass 21, count 0 2006.162.08:17:19.71#ibcon#about to read 6, iclass 21, count 0 2006.162.08:17:19.71#ibcon#read 6, iclass 21, count 0 2006.162.08:17:19.71#ibcon#end of sib2, iclass 21, count 0 2006.162.08:17:19.71#ibcon#*mode == 0, iclass 21, count 0 2006.162.08:17:19.71#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.162.08:17:19.71#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.08:17:19.71#ibcon#*before write, iclass 21, count 0 2006.162.08:17:19.71#ibcon#enter sib2, iclass 21, count 0 2006.162.08:17:19.71#ibcon#flushed, iclass 21, count 0 2006.162.08:17:19.71#ibcon#about to write, iclass 21, count 0 2006.162.08:17:19.71#ibcon#wrote, iclass 21, count 0 2006.162.08:17:19.71#ibcon#about to read 3, iclass 21, count 0 2006.162.08:17:19.75#ibcon#read 3, iclass 21, count 0 2006.162.08:17:19.75#ibcon#about to read 4, iclass 21, count 0 2006.162.08:17:19.75#ibcon#read 4, iclass 21, count 0 2006.162.08:17:19.75#ibcon#about to read 5, iclass 21, count 0 2006.162.08:17:19.75#ibcon#read 5, iclass 21, count 0 2006.162.08:17:19.75#ibcon#about to read 6, iclass 21, count 0 2006.162.08:17:19.75#ibcon#read 6, iclass 21, count 0 2006.162.08:17:19.75#ibcon#end of sib2, iclass 21, count 0 2006.162.08:17:19.75#ibcon#*after write, iclass 21, count 0 2006.162.08:17:19.75#ibcon#*before return 0, iclass 21, count 0 2006.162.08:17:19.75#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:17:19.75#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:17:19.75#ibcon#about to clear, iclass 21 cls_cnt 0 2006.162.08:17:19.75#ibcon#cleared, iclass 21 cls_cnt 0 2006.162.08:17:19.75$vc4f8/va=1,8 2006.162.08:17:19.75#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.162.08:17:19.75#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.162.08:17:19.75#ibcon#ireg 11 cls_cnt 2 2006.162.08:17:19.75#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:17:19.75#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:17:19.75#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:17:19.75#ibcon#enter wrdev, iclass 23, count 2 2006.162.08:17:19.75#ibcon#first serial, iclass 23, count 2 2006.162.08:17:19.75#ibcon#enter sib2, iclass 23, count 2 2006.162.08:17:19.75#ibcon#flushed, iclass 23, count 2 2006.162.08:17:19.75#ibcon#about to write, iclass 23, count 2 2006.162.08:17:19.75#ibcon#wrote, iclass 23, count 2 2006.162.08:17:19.75#ibcon#about to read 3, iclass 23, count 2 2006.162.08:17:19.77#ibcon#read 3, iclass 23, count 2 2006.162.08:17:19.77#ibcon#about to read 4, iclass 23, count 2 2006.162.08:17:19.77#ibcon#read 4, iclass 23, count 2 2006.162.08:17:19.77#ibcon#about to read 5, iclass 23, count 2 2006.162.08:17:19.77#ibcon#read 5, iclass 23, count 2 2006.162.08:17:19.77#ibcon#about to read 6, iclass 23, count 2 2006.162.08:17:19.77#ibcon#read 6, iclass 23, count 2 2006.162.08:17:19.77#ibcon#end of sib2, iclass 23, count 2 2006.162.08:17:19.77#ibcon#*mode == 0, iclass 23, count 2 2006.162.08:17:19.77#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.162.08:17:19.77#ibcon#[25=AT01-08\r\n] 2006.162.08:17:19.77#ibcon#*before write, iclass 23, count 2 2006.162.08:17:19.77#ibcon#enter sib2, iclass 23, count 2 2006.162.08:17:19.77#ibcon#flushed, iclass 23, count 2 2006.162.08:17:19.77#ibcon#about to write, iclass 23, count 2 2006.162.08:17:19.77#ibcon#wrote, iclass 23, count 2 2006.162.08:17:19.77#ibcon#about to read 3, iclass 23, count 2 2006.162.08:17:19.80#ibcon#read 3, iclass 23, count 2 2006.162.08:17:19.80#ibcon#about to read 4, iclass 23, count 2 2006.162.08:17:19.80#ibcon#read 4, iclass 23, count 2 2006.162.08:17:19.80#ibcon#about to read 5, iclass 23, count 2 2006.162.08:17:19.80#ibcon#read 5, iclass 23, count 2 2006.162.08:17:19.80#ibcon#about to read 6, iclass 23, count 2 2006.162.08:17:19.80#ibcon#read 6, iclass 23, count 2 2006.162.08:17:19.80#ibcon#end of sib2, iclass 23, count 2 2006.162.08:17:19.80#ibcon#*after write, iclass 23, count 2 2006.162.08:17:19.80#ibcon#*before return 0, iclass 23, count 2 2006.162.08:17:19.80#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:17:19.80#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:17:19.80#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.162.08:17:19.80#ibcon#ireg 7 cls_cnt 0 2006.162.08:17:19.80#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:17:19.92#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:17:19.92#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:17:19.92#ibcon#enter wrdev, iclass 23, count 0 2006.162.08:17:19.92#ibcon#first serial, iclass 23, count 0 2006.162.08:17:19.92#ibcon#enter sib2, iclass 23, count 0 2006.162.08:17:19.92#ibcon#flushed, iclass 23, count 0 2006.162.08:17:19.92#ibcon#about to write, iclass 23, count 0 2006.162.08:17:19.92#ibcon#wrote, iclass 23, count 0 2006.162.08:17:19.92#ibcon#about to read 3, iclass 23, count 0 2006.162.08:17:19.94#ibcon#read 3, iclass 23, count 0 2006.162.08:17:19.94#ibcon#about to read 4, iclass 23, count 0 2006.162.08:17:19.94#ibcon#read 4, iclass 23, count 0 2006.162.08:17:19.94#ibcon#about to read 5, iclass 23, count 0 2006.162.08:17:19.94#ibcon#read 5, iclass 23, count 0 2006.162.08:17:19.94#ibcon#about to read 6, iclass 23, count 0 2006.162.08:17:19.94#ibcon#read 6, iclass 23, count 0 2006.162.08:17:19.94#ibcon#end of sib2, iclass 23, count 0 2006.162.08:17:19.94#ibcon#*mode == 0, iclass 23, count 0 2006.162.08:17:19.94#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.162.08:17:19.94#ibcon#[25=USB\r\n] 2006.162.08:17:19.94#ibcon#*before write, iclass 23, count 0 2006.162.08:17:19.94#ibcon#enter sib2, iclass 23, count 0 2006.162.08:17:19.94#ibcon#flushed, iclass 23, count 0 2006.162.08:17:19.94#ibcon#about to write, iclass 23, count 0 2006.162.08:17:19.94#ibcon#wrote, iclass 23, count 0 2006.162.08:17:19.94#ibcon#about to read 3, iclass 23, count 0 2006.162.08:17:19.97#ibcon#read 3, iclass 23, count 0 2006.162.08:17:19.97#ibcon#about to read 4, iclass 23, count 0 2006.162.08:17:19.97#ibcon#read 4, iclass 23, count 0 2006.162.08:17:19.97#ibcon#about to read 5, iclass 23, count 0 2006.162.08:17:19.97#ibcon#read 5, iclass 23, count 0 2006.162.08:17:19.97#ibcon#about to read 6, iclass 23, count 0 2006.162.08:17:19.97#ibcon#read 6, iclass 23, count 0 2006.162.08:17:19.97#ibcon#end of sib2, iclass 23, count 0 2006.162.08:17:19.97#ibcon#*after write, iclass 23, count 0 2006.162.08:17:19.97#ibcon#*before return 0, iclass 23, count 0 2006.162.08:17:19.97#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:17:19.97#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:17:19.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.162.08:17:19.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.162.08:17:19.97$vc4f8/valo=2,572.99 2006.162.08:17:19.97#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.162.08:17:19.97#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.162.08:17:19.97#ibcon#ireg 17 cls_cnt 0 2006.162.08:17:19.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:17:19.97#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:17:19.97#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:17:19.97#ibcon#enter wrdev, iclass 25, count 0 2006.162.08:17:19.97#ibcon#first serial, iclass 25, count 0 2006.162.08:17:19.97#ibcon#enter sib2, iclass 25, count 0 2006.162.08:17:19.97#ibcon#flushed, iclass 25, count 0 2006.162.08:17:19.97#ibcon#about to write, iclass 25, count 0 2006.162.08:17:19.97#ibcon#wrote, iclass 25, count 0 2006.162.08:17:19.97#ibcon#about to read 3, iclass 25, count 0 2006.162.08:17:19.99#ibcon#read 3, iclass 25, count 0 2006.162.08:17:19.99#ibcon#about to read 4, iclass 25, count 0 2006.162.08:17:19.99#ibcon#read 4, iclass 25, count 0 2006.162.08:17:19.99#ibcon#about to read 5, iclass 25, count 0 2006.162.08:17:19.99#ibcon#read 5, iclass 25, count 0 2006.162.08:17:19.99#ibcon#about to read 6, iclass 25, count 0 2006.162.08:17:19.99#ibcon#read 6, iclass 25, count 0 2006.162.08:17:19.99#ibcon#end of sib2, iclass 25, count 0 2006.162.08:17:19.99#ibcon#*mode == 0, iclass 25, count 0 2006.162.08:17:19.99#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.162.08:17:19.99#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.08:17:19.99#ibcon#*before write, iclass 25, count 0 2006.162.08:17:19.99#ibcon#enter sib2, iclass 25, count 0 2006.162.08:17:19.99#ibcon#flushed, iclass 25, count 0 2006.162.08:17:19.99#ibcon#about to write, iclass 25, count 0 2006.162.08:17:19.99#ibcon#wrote, iclass 25, count 0 2006.162.08:17:19.99#ibcon#about to read 3, iclass 25, count 0 2006.162.08:17:20.03#ibcon#read 3, iclass 25, count 0 2006.162.08:17:20.03#ibcon#about to read 4, iclass 25, count 0 2006.162.08:17:20.03#ibcon#read 4, iclass 25, count 0 2006.162.08:17:20.03#ibcon#about to read 5, iclass 25, count 0 2006.162.08:17:20.03#ibcon#read 5, iclass 25, count 0 2006.162.08:17:20.03#ibcon#about to read 6, iclass 25, count 0 2006.162.08:17:20.03#ibcon#read 6, iclass 25, count 0 2006.162.08:17:20.03#ibcon#end of sib2, iclass 25, count 0 2006.162.08:17:20.03#ibcon#*after write, iclass 25, count 0 2006.162.08:17:20.03#ibcon#*before return 0, iclass 25, count 0 2006.162.08:17:20.03#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:17:20.03#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:17:20.03#ibcon#about to clear, iclass 25 cls_cnt 0 2006.162.08:17:20.03#ibcon#cleared, iclass 25 cls_cnt 0 2006.162.08:17:20.03$vc4f8/va=2,7 2006.162.08:17:20.03#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.162.08:17:20.03#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.162.08:17:20.03#ibcon#ireg 11 cls_cnt 2 2006.162.08:17:20.03#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:17:20.09#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:17:20.09#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:17:20.09#ibcon#enter wrdev, iclass 27, count 2 2006.162.08:17:20.09#ibcon#first serial, iclass 27, count 2 2006.162.08:17:20.09#ibcon#enter sib2, iclass 27, count 2 2006.162.08:17:20.09#ibcon#flushed, iclass 27, count 2 2006.162.08:17:20.09#ibcon#about to write, iclass 27, count 2 2006.162.08:17:20.09#ibcon#wrote, iclass 27, count 2 2006.162.08:17:20.09#ibcon#about to read 3, iclass 27, count 2 2006.162.08:17:20.12#ibcon#read 3, iclass 27, count 2 2006.162.08:17:20.12#ibcon#about to read 4, iclass 27, count 2 2006.162.08:17:20.12#ibcon#read 4, iclass 27, count 2 2006.162.08:17:20.12#ibcon#about to read 5, iclass 27, count 2 2006.162.08:17:20.12#ibcon#read 5, iclass 27, count 2 2006.162.08:17:20.12#ibcon#about to read 6, iclass 27, count 2 2006.162.08:17:20.12#ibcon#read 6, iclass 27, count 2 2006.162.08:17:20.12#ibcon#end of sib2, iclass 27, count 2 2006.162.08:17:20.12#ibcon#*mode == 0, iclass 27, count 2 2006.162.08:17:20.12#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.162.08:17:20.12#ibcon#[25=AT02-07\r\n] 2006.162.08:17:20.12#ibcon#*before write, iclass 27, count 2 2006.162.08:17:20.12#ibcon#enter sib2, iclass 27, count 2 2006.162.08:17:20.12#ibcon#flushed, iclass 27, count 2 2006.162.08:17:20.12#ibcon#about to write, iclass 27, count 2 2006.162.08:17:20.12#ibcon#wrote, iclass 27, count 2 2006.162.08:17:20.12#ibcon#about to read 3, iclass 27, count 2 2006.162.08:17:20.15#ibcon#read 3, iclass 27, count 2 2006.162.08:17:20.15#ibcon#about to read 4, iclass 27, count 2 2006.162.08:17:20.15#ibcon#read 4, iclass 27, count 2 2006.162.08:17:20.15#ibcon#about to read 5, iclass 27, count 2 2006.162.08:17:20.15#ibcon#read 5, iclass 27, count 2 2006.162.08:17:20.15#ibcon#about to read 6, iclass 27, count 2 2006.162.08:17:20.15#ibcon#read 6, iclass 27, count 2 2006.162.08:17:20.15#ibcon#end of sib2, iclass 27, count 2 2006.162.08:17:20.15#ibcon#*after write, iclass 27, count 2 2006.162.08:17:20.15#ibcon#*before return 0, iclass 27, count 2 2006.162.08:17:20.15#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:17:20.15#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:17:20.15#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.162.08:17:20.15#ibcon#ireg 7 cls_cnt 0 2006.162.08:17:20.15#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:17:20.27#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:17:20.27#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:17:20.27#ibcon#enter wrdev, iclass 27, count 0 2006.162.08:17:20.27#ibcon#first serial, iclass 27, count 0 2006.162.08:17:20.27#ibcon#enter sib2, iclass 27, count 0 2006.162.08:17:20.27#ibcon#flushed, iclass 27, count 0 2006.162.08:17:20.27#ibcon#about to write, iclass 27, count 0 2006.162.08:17:20.27#ibcon#wrote, iclass 27, count 0 2006.162.08:17:20.27#ibcon#about to read 3, iclass 27, count 0 2006.162.08:17:20.29#ibcon#read 3, iclass 27, count 0 2006.162.08:17:20.29#ibcon#about to read 4, iclass 27, count 0 2006.162.08:17:20.29#ibcon#read 4, iclass 27, count 0 2006.162.08:17:20.29#ibcon#about to read 5, iclass 27, count 0 2006.162.08:17:20.29#ibcon#read 5, iclass 27, count 0 2006.162.08:17:20.29#ibcon#about to read 6, iclass 27, count 0 2006.162.08:17:20.29#ibcon#read 6, iclass 27, count 0 2006.162.08:17:20.29#ibcon#end of sib2, iclass 27, count 0 2006.162.08:17:20.29#ibcon#*mode == 0, iclass 27, count 0 2006.162.08:17:20.29#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.162.08:17:20.29#ibcon#[25=USB\r\n] 2006.162.08:17:20.29#ibcon#*before write, iclass 27, count 0 2006.162.08:17:20.29#ibcon#enter sib2, iclass 27, count 0 2006.162.08:17:20.29#ibcon#flushed, iclass 27, count 0 2006.162.08:17:20.29#ibcon#about to write, iclass 27, count 0 2006.162.08:17:20.29#ibcon#wrote, iclass 27, count 0 2006.162.08:17:20.29#ibcon#about to read 3, iclass 27, count 0 2006.162.08:17:20.32#ibcon#read 3, iclass 27, count 0 2006.162.08:17:20.32#ibcon#about to read 4, iclass 27, count 0 2006.162.08:17:20.32#ibcon#read 4, iclass 27, count 0 2006.162.08:17:20.32#ibcon#about to read 5, iclass 27, count 0 2006.162.08:17:20.32#ibcon#read 5, iclass 27, count 0 2006.162.08:17:20.32#ibcon#about to read 6, iclass 27, count 0 2006.162.08:17:20.32#ibcon#read 6, iclass 27, count 0 2006.162.08:17:20.32#ibcon#end of sib2, iclass 27, count 0 2006.162.08:17:20.32#ibcon#*after write, iclass 27, count 0 2006.162.08:17:20.32#ibcon#*before return 0, iclass 27, count 0 2006.162.08:17:20.32#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:17:20.32#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:17:20.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.162.08:17:20.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.162.08:17:20.32$vc4f8/valo=3,672.99 2006.162.08:17:20.32#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.162.08:17:20.32#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.162.08:17:20.32#ibcon#ireg 17 cls_cnt 0 2006.162.08:17:20.32#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:17:20.32#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:17:20.32#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:17:20.32#ibcon#enter wrdev, iclass 29, count 0 2006.162.08:17:20.32#ibcon#first serial, iclass 29, count 0 2006.162.08:17:20.32#ibcon#enter sib2, iclass 29, count 0 2006.162.08:17:20.32#ibcon#flushed, iclass 29, count 0 2006.162.08:17:20.32#ibcon#about to write, iclass 29, count 0 2006.162.08:17:20.32#ibcon#wrote, iclass 29, count 0 2006.162.08:17:20.32#ibcon#about to read 3, iclass 29, count 0 2006.162.08:17:20.34#ibcon#read 3, iclass 29, count 0 2006.162.08:17:20.34#ibcon#about to read 4, iclass 29, count 0 2006.162.08:17:20.34#ibcon#read 4, iclass 29, count 0 2006.162.08:17:20.34#ibcon#about to read 5, iclass 29, count 0 2006.162.08:17:20.34#ibcon#read 5, iclass 29, count 0 2006.162.08:17:20.34#ibcon#about to read 6, iclass 29, count 0 2006.162.08:17:20.34#ibcon#read 6, iclass 29, count 0 2006.162.08:17:20.34#ibcon#end of sib2, iclass 29, count 0 2006.162.08:17:20.34#ibcon#*mode == 0, iclass 29, count 0 2006.162.08:17:20.34#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.162.08:17:20.34#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.08:17:20.34#ibcon#*before write, iclass 29, count 0 2006.162.08:17:20.34#ibcon#enter sib2, iclass 29, count 0 2006.162.08:17:20.34#ibcon#flushed, iclass 29, count 0 2006.162.08:17:20.34#ibcon#about to write, iclass 29, count 0 2006.162.08:17:20.34#ibcon#wrote, iclass 29, count 0 2006.162.08:17:20.34#ibcon#about to read 3, iclass 29, count 0 2006.162.08:17:20.38#ibcon#read 3, iclass 29, count 0 2006.162.08:17:20.38#ibcon#about to read 4, iclass 29, count 0 2006.162.08:17:20.38#ibcon#read 4, iclass 29, count 0 2006.162.08:17:20.38#ibcon#about to read 5, iclass 29, count 0 2006.162.08:17:20.38#ibcon#read 5, iclass 29, count 0 2006.162.08:17:20.38#ibcon#about to read 6, iclass 29, count 0 2006.162.08:17:20.38#ibcon#read 6, iclass 29, count 0 2006.162.08:17:20.38#ibcon#end of sib2, iclass 29, count 0 2006.162.08:17:20.38#ibcon#*after write, iclass 29, count 0 2006.162.08:17:20.38#ibcon#*before return 0, iclass 29, count 0 2006.162.08:17:20.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:17:20.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:17:20.38#ibcon#about to clear, iclass 29 cls_cnt 0 2006.162.08:17:20.38#ibcon#cleared, iclass 29 cls_cnt 0 2006.162.08:17:20.38$vc4f8/va=3,6 2006.162.08:17:20.38#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.162.08:17:20.38#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.162.08:17:20.38#ibcon#ireg 11 cls_cnt 2 2006.162.08:17:20.38#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:17:20.44#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:17:20.44#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:17:20.44#ibcon#enter wrdev, iclass 31, count 2 2006.162.08:17:20.44#ibcon#first serial, iclass 31, count 2 2006.162.08:17:20.44#ibcon#enter sib2, iclass 31, count 2 2006.162.08:17:20.44#ibcon#flushed, iclass 31, count 2 2006.162.08:17:20.44#ibcon#about to write, iclass 31, count 2 2006.162.08:17:20.44#ibcon#wrote, iclass 31, count 2 2006.162.08:17:20.44#ibcon#about to read 3, iclass 31, count 2 2006.162.08:17:20.46#ibcon#read 3, iclass 31, count 2 2006.162.08:17:20.46#ibcon#about to read 4, iclass 31, count 2 2006.162.08:17:20.46#ibcon#read 4, iclass 31, count 2 2006.162.08:17:20.46#ibcon#about to read 5, iclass 31, count 2 2006.162.08:17:20.46#ibcon#read 5, iclass 31, count 2 2006.162.08:17:20.46#ibcon#about to read 6, iclass 31, count 2 2006.162.08:17:20.46#ibcon#read 6, iclass 31, count 2 2006.162.08:17:20.46#ibcon#end of sib2, iclass 31, count 2 2006.162.08:17:20.46#ibcon#*mode == 0, iclass 31, count 2 2006.162.08:17:20.46#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.162.08:17:20.46#ibcon#[25=AT03-06\r\n] 2006.162.08:17:20.46#ibcon#*before write, iclass 31, count 2 2006.162.08:17:20.46#ibcon#enter sib2, iclass 31, count 2 2006.162.08:17:20.46#ibcon#flushed, iclass 31, count 2 2006.162.08:17:20.46#ibcon#about to write, iclass 31, count 2 2006.162.08:17:20.46#ibcon#wrote, iclass 31, count 2 2006.162.08:17:20.46#ibcon#about to read 3, iclass 31, count 2 2006.162.08:17:20.49#ibcon#read 3, iclass 31, count 2 2006.162.08:17:20.49#ibcon#about to read 4, iclass 31, count 2 2006.162.08:17:20.49#ibcon#read 4, iclass 31, count 2 2006.162.08:17:20.49#ibcon#about to read 5, iclass 31, count 2 2006.162.08:17:20.49#ibcon#read 5, iclass 31, count 2 2006.162.08:17:20.49#ibcon#about to read 6, iclass 31, count 2 2006.162.08:17:20.49#ibcon#read 6, iclass 31, count 2 2006.162.08:17:20.49#ibcon#end of sib2, iclass 31, count 2 2006.162.08:17:20.49#ibcon#*after write, iclass 31, count 2 2006.162.08:17:20.49#ibcon#*before return 0, iclass 31, count 2 2006.162.08:17:20.49#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:17:20.49#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:17:20.49#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.162.08:17:20.49#ibcon#ireg 7 cls_cnt 0 2006.162.08:17:20.49#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:17:20.61#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:17:20.61#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:17:20.61#ibcon#enter wrdev, iclass 31, count 0 2006.162.08:17:20.61#ibcon#first serial, iclass 31, count 0 2006.162.08:17:20.61#ibcon#enter sib2, iclass 31, count 0 2006.162.08:17:20.61#ibcon#flushed, iclass 31, count 0 2006.162.08:17:20.61#ibcon#about to write, iclass 31, count 0 2006.162.08:17:20.61#ibcon#wrote, iclass 31, count 0 2006.162.08:17:20.61#ibcon#about to read 3, iclass 31, count 0 2006.162.08:17:20.63#ibcon#read 3, iclass 31, count 0 2006.162.08:17:20.63#ibcon#about to read 4, iclass 31, count 0 2006.162.08:17:20.63#ibcon#read 4, iclass 31, count 0 2006.162.08:17:20.63#ibcon#about to read 5, iclass 31, count 0 2006.162.08:17:20.63#ibcon#read 5, iclass 31, count 0 2006.162.08:17:20.63#ibcon#about to read 6, iclass 31, count 0 2006.162.08:17:20.63#ibcon#read 6, iclass 31, count 0 2006.162.08:17:20.63#ibcon#end of sib2, iclass 31, count 0 2006.162.08:17:20.63#ibcon#*mode == 0, iclass 31, count 0 2006.162.08:17:20.63#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.162.08:17:20.63#ibcon#[25=USB\r\n] 2006.162.08:17:20.63#ibcon#*before write, iclass 31, count 0 2006.162.08:17:20.63#ibcon#enter sib2, iclass 31, count 0 2006.162.08:17:20.63#ibcon#flushed, iclass 31, count 0 2006.162.08:17:20.63#ibcon#about to write, iclass 31, count 0 2006.162.08:17:20.63#ibcon#wrote, iclass 31, count 0 2006.162.08:17:20.63#ibcon#about to read 3, iclass 31, count 0 2006.162.08:17:20.66#ibcon#read 3, iclass 31, count 0 2006.162.08:17:20.66#ibcon#about to read 4, iclass 31, count 0 2006.162.08:17:20.66#ibcon#read 4, iclass 31, count 0 2006.162.08:17:20.66#ibcon#about to read 5, iclass 31, count 0 2006.162.08:17:20.66#ibcon#read 5, iclass 31, count 0 2006.162.08:17:20.66#ibcon#about to read 6, iclass 31, count 0 2006.162.08:17:20.66#ibcon#read 6, iclass 31, count 0 2006.162.08:17:20.66#ibcon#end of sib2, iclass 31, count 0 2006.162.08:17:20.66#ibcon#*after write, iclass 31, count 0 2006.162.08:17:20.66#ibcon#*before return 0, iclass 31, count 0 2006.162.08:17:20.66#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:17:20.66#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:17:20.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.162.08:17:20.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.162.08:17:20.66$vc4f8/valo=4,832.99 2006.162.08:17:20.66#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.162.08:17:20.66#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.162.08:17:20.66#ibcon#ireg 17 cls_cnt 0 2006.162.08:17:20.66#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:17:20.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:17:20.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:17:20.66#ibcon#enter wrdev, iclass 33, count 0 2006.162.08:17:20.66#ibcon#first serial, iclass 33, count 0 2006.162.08:17:20.66#ibcon#enter sib2, iclass 33, count 0 2006.162.08:17:20.66#ibcon#flushed, iclass 33, count 0 2006.162.08:17:20.66#ibcon#about to write, iclass 33, count 0 2006.162.08:17:20.66#ibcon#wrote, iclass 33, count 0 2006.162.08:17:20.66#ibcon#about to read 3, iclass 33, count 0 2006.162.08:17:20.68#ibcon#read 3, iclass 33, count 0 2006.162.08:17:20.68#ibcon#about to read 4, iclass 33, count 0 2006.162.08:17:20.68#ibcon#read 4, iclass 33, count 0 2006.162.08:17:20.68#ibcon#about to read 5, iclass 33, count 0 2006.162.08:17:20.68#ibcon#read 5, iclass 33, count 0 2006.162.08:17:20.68#ibcon#about to read 6, iclass 33, count 0 2006.162.08:17:20.68#ibcon#read 6, iclass 33, count 0 2006.162.08:17:20.68#ibcon#end of sib2, iclass 33, count 0 2006.162.08:17:20.68#ibcon#*mode == 0, iclass 33, count 0 2006.162.08:17:20.68#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.162.08:17:20.68#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.08:17:20.68#ibcon#*before write, iclass 33, count 0 2006.162.08:17:20.68#ibcon#enter sib2, iclass 33, count 0 2006.162.08:17:20.68#ibcon#flushed, iclass 33, count 0 2006.162.08:17:20.68#ibcon#about to write, iclass 33, count 0 2006.162.08:17:20.68#ibcon#wrote, iclass 33, count 0 2006.162.08:17:20.68#ibcon#about to read 3, iclass 33, count 0 2006.162.08:17:20.72#ibcon#read 3, iclass 33, count 0 2006.162.08:17:20.72#ibcon#about to read 4, iclass 33, count 0 2006.162.08:17:20.72#ibcon#read 4, iclass 33, count 0 2006.162.08:17:20.72#ibcon#about to read 5, iclass 33, count 0 2006.162.08:17:20.72#ibcon#read 5, iclass 33, count 0 2006.162.08:17:20.72#ibcon#about to read 6, iclass 33, count 0 2006.162.08:17:20.72#ibcon#read 6, iclass 33, count 0 2006.162.08:17:20.72#ibcon#end of sib2, iclass 33, count 0 2006.162.08:17:20.72#ibcon#*after write, iclass 33, count 0 2006.162.08:17:20.72#ibcon#*before return 0, iclass 33, count 0 2006.162.08:17:20.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:17:20.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:17:20.72#ibcon#about to clear, iclass 33 cls_cnt 0 2006.162.08:17:20.72#ibcon#cleared, iclass 33 cls_cnt 0 2006.162.08:17:20.72$vc4f8/va=4,7 2006.162.08:17:20.72#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.162.08:17:20.72#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.162.08:17:20.72#ibcon#ireg 11 cls_cnt 2 2006.162.08:17:20.72#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.162.08:17:20.78#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.162.08:17:20.78#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.162.08:17:20.78#ibcon#enter wrdev, iclass 35, count 2 2006.162.08:17:20.78#ibcon#first serial, iclass 35, count 2 2006.162.08:17:20.78#ibcon#enter sib2, iclass 35, count 2 2006.162.08:17:20.78#ibcon#flushed, iclass 35, count 2 2006.162.08:17:20.78#ibcon#about to write, iclass 35, count 2 2006.162.08:17:20.78#ibcon#wrote, iclass 35, count 2 2006.162.08:17:20.78#ibcon#about to read 3, iclass 35, count 2 2006.162.08:17:20.80#ibcon#read 3, iclass 35, count 2 2006.162.08:17:20.80#ibcon#about to read 4, iclass 35, count 2 2006.162.08:17:20.80#ibcon#read 4, iclass 35, count 2 2006.162.08:17:20.80#ibcon#about to read 5, iclass 35, count 2 2006.162.08:17:20.80#ibcon#read 5, iclass 35, count 2 2006.162.08:17:20.80#ibcon#about to read 6, iclass 35, count 2 2006.162.08:17:20.80#ibcon#read 6, iclass 35, count 2 2006.162.08:17:20.80#ibcon#end of sib2, iclass 35, count 2 2006.162.08:17:20.80#ibcon#*mode == 0, iclass 35, count 2 2006.162.08:17:20.80#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.162.08:17:20.80#ibcon#[25=AT04-07\r\n] 2006.162.08:17:20.80#ibcon#*before write, iclass 35, count 2 2006.162.08:17:20.80#ibcon#enter sib2, iclass 35, count 2 2006.162.08:17:20.80#ibcon#flushed, iclass 35, count 2 2006.162.08:17:20.80#ibcon#about to write, iclass 35, count 2 2006.162.08:17:20.80#ibcon#wrote, iclass 35, count 2 2006.162.08:17:20.80#ibcon#about to read 3, iclass 35, count 2 2006.162.08:17:20.83#ibcon#read 3, iclass 35, count 2 2006.162.08:17:20.83#ibcon#about to read 4, iclass 35, count 2 2006.162.08:17:20.83#ibcon#read 4, iclass 35, count 2 2006.162.08:17:20.83#ibcon#about to read 5, iclass 35, count 2 2006.162.08:17:20.83#ibcon#read 5, iclass 35, count 2 2006.162.08:17:20.83#ibcon#about to read 6, iclass 35, count 2 2006.162.08:17:20.83#ibcon#read 6, iclass 35, count 2 2006.162.08:17:20.83#ibcon#end of sib2, iclass 35, count 2 2006.162.08:17:20.83#ibcon#*after write, iclass 35, count 2 2006.162.08:17:20.83#ibcon#*before return 0, iclass 35, count 2 2006.162.08:17:20.83#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.162.08:17:20.83#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.162.08:17:20.83#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.162.08:17:20.83#ibcon#ireg 7 cls_cnt 0 2006.162.08:17:20.83#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.162.08:17:20.95#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.162.08:17:20.95#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.162.08:17:20.95#ibcon#enter wrdev, iclass 35, count 0 2006.162.08:17:20.95#ibcon#first serial, iclass 35, count 0 2006.162.08:17:20.95#ibcon#enter sib2, iclass 35, count 0 2006.162.08:17:20.95#ibcon#flushed, iclass 35, count 0 2006.162.08:17:20.95#ibcon#about to write, iclass 35, count 0 2006.162.08:17:20.95#ibcon#wrote, iclass 35, count 0 2006.162.08:17:20.95#ibcon#about to read 3, iclass 35, count 0 2006.162.08:17:20.97#ibcon#read 3, iclass 35, count 0 2006.162.08:17:20.97#ibcon#about to read 4, iclass 35, count 0 2006.162.08:17:20.97#ibcon#read 4, iclass 35, count 0 2006.162.08:17:20.97#ibcon#about to read 5, iclass 35, count 0 2006.162.08:17:20.97#ibcon#read 5, iclass 35, count 0 2006.162.08:17:20.97#ibcon#about to read 6, iclass 35, count 0 2006.162.08:17:20.97#ibcon#read 6, iclass 35, count 0 2006.162.08:17:20.97#ibcon#end of sib2, iclass 35, count 0 2006.162.08:17:20.97#ibcon#*mode == 0, iclass 35, count 0 2006.162.08:17:20.97#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.162.08:17:20.97#ibcon#[25=USB\r\n] 2006.162.08:17:20.97#ibcon#*before write, iclass 35, count 0 2006.162.08:17:20.97#ibcon#enter sib2, iclass 35, count 0 2006.162.08:17:20.97#ibcon#flushed, iclass 35, count 0 2006.162.08:17:20.97#ibcon#about to write, iclass 35, count 0 2006.162.08:17:20.97#ibcon#wrote, iclass 35, count 0 2006.162.08:17:20.97#ibcon#about to read 3, iclass 35, count 0 2006.162.08:17:21.00#ibcon#read 3, iclass 35, count 0 2006.162.08:17:21.00#ibcon#about to read 4, iclass 35, count 0 2006.162.08:17:21.00#ibcon#read 4, iclass 35, count 0 2006.162.08:17:21.00#ibcon#about to read 5, iclass 35, count 0 2006.162.08:17:21.00#ibcon#read 5, iclass 35, count 0 2006.162.08:17:21.00#ibcon#about to read 6, iclass 35, count 0 2006.162.08:17:21.00#ibcon#read 6, iclass 35, count 0 2006.162.08:17:21.00#ibcon#end of sib2, iclass 35, count 0 2006.162.08:17:21.00#ibcon#*after write, iclass 35, count 0 2006.162.08:17:21.00#ibcon#*before return 0, iclass 35, count 0 2006.162.08:17:21.00#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.162.08:17:21.00#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.162.08:17:21.00#ibcon#about to clear, iclass 35 cls_cnt 0 2006.162.08:17:21.00#ibcon#cleared, iclass 35 cls_cnt 0 2006.162.08:17:21.00$vc4f8/valo=5,652.99 2006.162.08:17:21.00#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.162.08:17:21.00#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.162.08:17:21.00#ibcon#ireg 17 cls_cnt 0 2006.162.08:17:21.00#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.162.08:17:21.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.162.08:17:21.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.162.08:17:21.00#ibcon#enter wrdev, iclass 37, count 0 2006.162.08:17:21.00#ibcon#first serial, iclass 37, count 0 2006.162.08:17:21.00#ibcon#enter sib2, iclass 37, count 0 2006.162.08:17:21.00#ibcon#flushed, iclass 37, count 0 2006.162.08:17:21.00#ibcon#about to write, iclass 37, count 0 2006.162.08:17:21.00#ibcon#wrote, iclass 37, count 0 2006.162.08:17:21.00#ibcon#about to read 3, iclass 37, count 0 2006.162.08:17:21.02#ibcon#read 3, iclass 37, count 0 2006.162.08:17:21.02#ibcon#about to read 4, iclass 37, count 0 2006.162.08:17:21.02#ibcon#read 4, iclass 37, count 0 2006.162.08:17:21.02#ibcon#about to read 5, iclass 37, count 0 2006.162.08:17:21.02#ibcon#read 5, iclass 37, count 0 2006.162.08:17:21.02#ibcon#about to read 6, iclass 37, count 0 2006.162.08:17:21.02#ibcon#read 6, iclass 37, count 0 2006.162.08:17:21.02#ibcon#end of sib2, iclass 37, count 0 2006.162.08:17:21.02#ibcon#*mode == 0, iclass 37, count 0 2006.162.08:17:21.02#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.162.08:17:21.02#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.08:17:21.02#ibcon#*before write, iclass 37, count 0 2006.162.08:17:21.02#ibcon#enter sib2, iclass 37, count 0 2006.162.08:17:21.02#ibcon#flushed, iclass 37, count 0 2006.162.08:17:21.02#ibcon#about to write, iclass 37, count 0 2006.162.08:17:21.02#ibcon#wrote, iclass 37, count 0 2006.162.08:17:21.02#ibcon#about to read 3, iclass 37, count 0 2006.162.08:17:21.06#ibcon#read 3, iclass 37, count 0 2006.162.08:17:21.06#ibcon#about to read 4, iclass 37, count 0 2006.162.08:17:21.06#ibcon#read 4, iclass 37, count 0 2006.162.08:17:21.06#ibcon#about to read 5, iclass 37, count 0 2006.162.08:17:21.06#ibcon#read 5, iclass 37, count 0 2006.162.08:17:21.06#ibcon#about to read 6, iclass 37, count 0 2006.162.08:17:21.06#ibcon#read 6, iclass 37, count 0 2006.162.08:17:21.06#ibcon#end of sib2, iclass 37, count 0 2006.162.08:17:21.06#ibcon#*after write, iclass 37, count 0 2006.162.08:17:21.06#ibcon#*before return 0, iclass 37, count 0 2006.162.08:17:21.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.162.08:17:21.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.162.08:17:21.06#ibcon#about to clear, iclass 37 cls_cnt 0 2006.162.08:17:21.06#ibcon#cleared, iclass 37 cls_cnt 0 2006.162.08:17:21.06$vc4f8/va=5,7 2006.162.08:17:21.06#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.162.08:17:21.06#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.162.08:17:21.06#ibcon#ireg 11 cls_cnt 2 2006.162.08:17:21.06#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.162.08:17:21.12#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.162.08:17:21.12#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.162.08:17:21.13#ibcon#enter wrdev, iclass 39, count 2 2006.162.08:17:21.13#ibcon#first serial, iclass 39, count 2 2006.162.08:17:21.13#ibcon#enter sib2, iclass 39, count 2 2006.162.08:17:21.13#ibcon#flushed, iclass 39, count 2 2006.162.08:17:21.13#ibcon#about to write, iclass 39, count 2 2006.162.08:17:21.13#ibcon#wrote, iclass 39, count 2 2006.162.08:17:21.13#ibcon#about to read 3, iclass 39, count 2 2006.162.08:17:21.14#ibcon#read 3, iclass 39, count 2 2006.162.08:17:21.14#ibcon#about to read 4, iclass 39, count 2 2006.162.08:17:21.14#ibcon#read 4, iclass 39, count 2 2006.162.08:17:21.14#ibcon#about to read 5, iclass 39, count 2 2006.162.08:17:21.14#ibcon#read 5, iclass 39, count 2 2006.162.08:17:21.14#ibcon#about to read 6, iclass 39, count 2 2006.162.08:17:21.14#ibcon#read 6, iclass 39, count 2 2006.162.08:17:21.14#ibcon#end of sib2, iclass 39, count 2 2006.162.08:17:21.14#ibcon#*mode == 0, iclass 39, count 2 2006.162.08:17:21.14#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.162.08:17:21.14#ibcon#[25=AT05-07\r\n] 2006.162.08:17:21.14#ibcon#*before write, iclass 39, count 2 2006.162.08:17:21.14#ibcon#enter sib2, iclass 39, count 2 2006.162.08:17:21.14#ibcon#flushed, iclass 39, count 2 2006.162.08:17:21.14#ibcon#about to write, iclass 39, count 2 2006.162.08:17:21.14#ibcon#wrote, iclass 39, count 2 2006.162.08:17:21.14#ibcon#about to read 3, iclass 39, count 2 2006.162.08:17:21.17#ibcon#read 3, iclass 39, count 2 2006.162.08:17:21.17#ibcon#about to read 4, iclass 39, count 2 2006.162.08:17:21.17#ibcon#read 4, iclass 39, count 2 2006.162.08:17:21.17#ibcon#about to read 5, iclass 39, count 2 2006.162.08:17:21.17#ibcon#read 5, iclass 39, count 2 2006.162.08:17:21.17#ibcon#about to read 6, iclass 39, count 2 2006.162.08:17:21.17#ibcon#read 6, iclass 39, count 2 2006.162.08:17:21.17#ibcon#end of sib2, iclass 39, count 2 2006.162.08:17:21.17#ibcon#*after write, iclass 39, count 2 2006.162.08:17:21.17#ibcon#*before return 0, iclass 39, count 2 2006.162.08:17:21.17#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.162.08:17:21.17#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.162.08:17:21.17#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.162.08:17:21.17#ibcon#ireg 7 cls_cnt 0 2006.162.08:17:21.17#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.162.08:17:21.29#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.162.08:17:21.29#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.162.08:17:21.29#ibcon#enter wrdev, iclass 39, count 0 2006.162.08:17:21.29#ibcon#first serial, iclass 39, count 0 2006.162.08:17:21.29#ibcon#enter sib2, iclass 39, count 0 2006.162.08:17:21.29#ibcon#flushed, iclass 39, count 0 2006.162.08:17:21.29#ibcon#about to write, iclass 39, count 0 2006.162.08:17:21.29#ibcon#wrote, iclass 39, count 0 2006.162.08:17:21.29#ibcon#about to read 3, iclass 39, count 0 2006.162.08:17:21.31#ibcon#read 3, iclass 39, count 0 2006.162.08:17:21.31#ibcon#about to read 4, iclass 39, count 0 2006.162.08:17:21.31#ibcon#read 4, iclass 39, count 0 2006.162.08:17:21.31#ibcon#about to read 5, iclass 39, count 0 2006.162.08:17:21.31#ibcon#read 5, iclass 39, count 0 2006.162.08:17:21.31#ibcon#about to read 6, iclass 39, count 0 2006.162.08:17:21.31#ibcon#read 6, iclass 39, count 0 2006.162.08:17:21.31#ibcon#end of sib2, iclass 39, count 0 2006.162.08:17:21.31#ibcon#*mode == 0, iclass 39, count 0 2006.162.08:17:21.31#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.162.08:17:21.31#ibcon#[25=USB\r\n] 2006.162.08:17:21.31#ibcon#*before write, iclass 39, count 0 2006.162.08:17:21.31#ibcon#enter sib2, iclass 39, count 0 2006.162.08:17:21.31#ibcon#flushed, iclass 39, count 0 2006.162.08:17:21.31#ibcon#about to write, iclass 39, count 0 2006.162.08:17:21.31#ibcon#wrote, iclass 39, count 0 2006.162.08:17:21.31#ibcon#about to read 3, iclass 39, count 0 2006.162.08:17:21.34#ibcon#read 3, iclass 39, count 0 2006.162.08:17:21.34#ibcon#about to read 4, iclass 39, count 0 2006.162.08:17:21.34#ibcon#read 4, iclass 39, count 0 2006.162.08:17:21.34#ibcon#about to read 5, iclass 39, count 0 2006.162.08:17:21.34#ibcon#read 5, iclass 39, count 0 2006.162.08:17:21.34#ibcon#about to read 6, iclass 39, count 0 2006.162.08:17:21.34#ibcon#read 6, iclass 39, count 0 2006.162.08:17:21.34#ibcon#end of sib2, iclass 39, count 0 2006.162.08:17:21.34#ibcon#*after write, iclass 39, count 0 2006.162.08:17:21.34#ibcon#*before return 0, iclass 39, count 0 2006.162.08:17:21.34#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.162.08:17:21.34#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.162.08:17:21.34#ibcon#about to clear, iclass 39 cls_cnt 0 2006.162.08:17:21.34#ibcon#cleared, iclass 39 cls_cnt 0 2006.162.08:17:21.34$vc4f8/valo=6,772.99 2006.162.08:17:21.34#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.162.08:17:21.34#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.162.08:17:21.34#ibcon#ireg 17 cls_cnt 0 2006.162.08:17:21.34#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.162.08:17:21.34#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.162.08:17:21.34#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.162.08:17:21.34#ibcon#enter wrdev, iclass 3, count 0 2006.162.08:17:21.34#ibcon#first serial, iclass 3, count 0 2006.162.08:17:21.34#ibcon#enter sib2, iclass 3, count 0 2006.162.08:17:21.34#ibcon#flushed, iclass 3, count 0 2006.162.08:17:21.34#ibcon#about to write, iclass 3, count 0 2006.162.08:17:21.34#ibcon#wrote, iclass 3, count 0 2006.162.08:17:21.34#ibcon#about to read 3, iclass 3, count 0 2006.162.08:17:21.36#ibcon#read 3, iclass 3, count 0 2006.162.08:17:21.36#ibcon#about to read 4, iclass 3, count 0 2006.162.08:17:21.36#ibcon#read 4, iclass 3, count 0 2006.162.08:17:21.36#ibcon#about to read 5, iclass 3, count 0 2006.162.08:17:21.36#ibcon#read 5, iclass 3, count 0 2006.162.08:17:21.36#ibcon#about to read 6, iclass 3, count 0 2006.162.08:17:21.36#ibcon#read 6, iclass 3, count 0 2006.162.08:17:21.36#ibcon#end of sib2, iclass 3, count 0 2006.162.08:17:21.36#ibcon#*mode == 0, iclass 3, count 0 2006.162.08:17:21.36#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.162.08:17:21.36#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.08:17:21.36#ibcon#*before write, iclass 3, count 0 2006.162.08:17:21.36#ibcon#enter sib2, iclass 3, count 0 2006.162.08:17:21.36#ibcon#flushed, iclass 3, count 0 2006.162.08:17:21.36#ibcon#about to write, iclass 3, count 0 2006.162.08:17:21.36#ibcon#wrote, iclass 3, count 0 2006.162.08:17:21.36#ibcon#about to read 3, iclass 3, count 0 2006.162.08:17:21.40#ibcon#read 3, iclass 3, count 0 2006.162.08:17:21.40#ibcon#about to read 4, iclass 3, count 0 2006.162.08:17:21.40#ibcon#read 4, iclass 3, count 0 2006.162.08:17:21.40#ibcon#about to read 5, iclass 3, count 0 2006.162.08:17:21.40#ibcon#read 5, iclass 3, count 0 2006.162.08:17:21.40#ibcon#about to read 6, iclass 3, count 0 2006.162.08:17:21.40#ibcon#read 6, iclass 3, count 0 2006.162.08:17:21.40#ibcon#end of sib2, iclass 3, count 0 2006.162.08:17:21.40#ibcon#*after write, iclass 3, count 0 2006.162.08:17:21.40#ibcon#*before return 0, iclass 3, count 0 2006.162.08:17:21.40#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.162.08:17:21.40#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.162.08:17:21.40#ibcon#about to clear, iclass 3 cls_cnt 0 2006.162.08:17:21.40#ibcon#cleared, iclass 3 cls_cnt 0 2006.162.08:17:21.40$vc4f8/va=6,6 2006.162.08:17:21.40#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.162.08:17:21.40#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.162.08:17:21.40#ibcon#ireg 11 cls_cnt 2 2006.162.08:17:21.40#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.162.08:17:21.46#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.162.08:17:21.46#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.162.08:17:21.46#ibcon#enter wrdev, iclass 5, count 2 2006.162.08:17:21.46#ibcon#first serial, iclass 5, count 2 2006.162.08:17:21.46#ibcon#enter sib2, iclass 5, count 2 2006.162.08:17:21.46#ibcon#flushed, iclass 5, count 2 2006.162.08:17:21.46#ibcon#about to write, iclass 5, count 2 2006.162.08:17:21.46#ibcon#wrote, iclass 5, count 2 2006.162.08:17:21.46#ibcon#about to read 3, iclass 5, count 2 2006.162.08:17:21.48#ibcon#read 3, iclass 5, count 2 2006.162.08:17:21.48#ibcon#about to read 4, iclass 5, count 2 2006.162.08:17:21.48#ibcon#read 4, iclass 5, count 2 2006.162.08:17:21.48#ibcon#about to read 5, iclass 5, count 2 2006.162.08:17:21.48#ibcon#read 5, iclass 5, count 2 2006.162.08:17:21.48#ibcon#about to read 6, iclass 5, count 2 2006.162.08:17:21.48#ibcon#read 6, iclass 5, count 2 2006.162.08:17:21.48#ibcon#end of sib2, iclass 5, count 2 2006.162.08:17:21.48#ibcon#*mode == 0, iclass 5, count 2 2006.162.08:17:21.48#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.162.08:17:21.48#ibcon#[25=AT06-06\r\n] 2006.162.08:17:21.48#ibcon#*before write, iclass 5, count 2 2006.162.08:17:21.48#ibcon#enter sib2, iclass 5, count 2 2006.162.08:17:21.48#ibcon#flushed, iclass 5, count 2 2006.162.08:17:21.48#ibcon#about to write, iclass 5, count 2 2006.162.08:17:21.48#ibcon#wrote, iclass 5, count 2 2006.162.08:17:21.48#ibcon#about to read 3, iclass 5, count 2 2006.162.08:17:21.51#ibcon#read 3, iclass 5, count 2 2006.162.08:17:21.51#ibcon#about to read 4, iclass 5, count 2 2006.162.08:17:21.51#ibcon#read 4, iclass 5, count 2 2006.162.08:17:21.51#ibcon#about to read 5, iclass 5, count 2 2006.162.08:17:21.51#ibcon#read 5, iclass 5, count 2 2006.162.08:17:21.51#ibcon#about to read 6, iclass 5, count 2 2006.162.08:17:21.51#ibcon#read 6, iclass 5, count 2 2006.162.08:17:21.51#ibcon#end of sib2, iclass 5, count 2 2006.162.08:17:21.51#ibcon#*after write, iclass 5, count 2 2006.162.08:17:21.51#ibcon#*before return 0, iclass 5, count 2 2006.162.08:17:21.51#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.162.08:17:21.51#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.162.08:17:21.51#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.162.08:17:21.51#ibcon#ireg 7 cls_cnt 0 2006.162.08:17:21.51#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.162.08:17:21.63#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.162.08:17:21.63#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.162.08:17:21.63#ibcon#enter wrdev, iclass 5, count 0 2006.162.08:17:21.63#ibcon#first serial, iclass 5, count 0 2006.162.08:17:21.63#ibcon#enter sib2, iclass 5, count 0 2006.162.08:17:21.63#ibcon#flushed, iclass 5, count 0 2006.162.08:17:21.63#ibcon#about to write, iclass 5, count 0 2006.162.08:17:21.63#ibcon#wrote, iclass 5, count 0 2006.162.08:17:21.63#ibcon#about to read 3, iclass 5, count 0 2006.162.08:17:21.65#ibcon#read 3, iclass 5, count 0 2006.162.08:17:21.65#ibcon#about to read 4, iclass 5, count 0 2006.162.08:17:21.65#ibcon#read 4, iclass 5, count 0 2006.162.08:17:21.65#ibcon#about to read 5, iclass 5, count 0 2006.162.08:17:21.65#ibcon#read 5, iclass 5, count 0 2006.162.08:17:21.65#ibcon#about to read 6, iclass 5, count 0 2006.162.08:17:21.65#ibcon#read 6, iclass 5, count 0 2006.162.08:17:21.65#ibcon#end of sib2, iclass 5, count 0 2006.162.08:17:21.65#ibcon#*mode == 0, iclass 5, count 0 2006.162.08:17:21.65#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.162.08:17:21.65#ibcon#[25=USB\r\n] 2006.162.08:17:21.65#ibcon#*before write, iclass 5, count 0 2006.162.08:17:21.65#ibcon#enter sib2, iclass 5, count 0 2006.162.08:17:21.65#ibcon#flushed, iclass 5, count 0 2006.162.08:17:21.65#ibcon#about to write, iclass 5, count 0 2006.162.08:17:21.65#ibcon#wrote, iclass 5, count 0 2006.162.08:17:21.65#ibcon#about to read 3, iclass 5, count 0 2006.162.08:17:21.68#ibcon#read 3, iclass 5, count 0 2006.162.08:17:21.68#ibcon#about to read 4, iclass 5, count 0 2006.162.08:17:21.68#ibcon#read 4, iclass 5, count 0 2006.162.08:17:21.68#ibcon#about to read 5, iclass 5, count 0 2006.162.08:17:21.68#ibcon#read 5, iclass 5, count 0 2006.162.08:17:21.68#ibcon#about to read 6, iclass 5, count 0 2006.162.08:17:21.68#ibcon#read 6, iclass 5, count 0 2006.162.08:17:21.68#ibcon#end of sib2, iclass 5, count 0 2006.162.08:17:21.68#ibcon#*after write, iclass 5, count 0 2006.162.08:17:21.68#ibcon#*before return 0, iclass 5, count 0 2006.162.08:17:21.68#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.162.08:17:21.68#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.162.08:17:21.68#ibcon#about to clear, iclass 5 cls_cnt 0 2006.162.08:17:21.68#ibcon#cleared, iclass 5 cls_cnt 0 2006.162.08:17:21.68$vc4f8/valo=7,832.99 2006.162.08:17:21.68#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.162.08:17:21.68#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.162.08:17:21.68#ibcon#ireg 17 cls_cnt 0 2006.162.08:17:21.68#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.162.08:17:21.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.162.08:17:21.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.162.08:17:21.68#ibcon#enter wrdev, iclass 7, count 0 2006.162.08:17:21.68#ibcon#first serial, iclass 7, count 0 2006.162.08:17:21.68#ibcon#enter sib2, iclass 7, count 0 2006.162.08:17:21.68#ibcon#flushed, iclass 7, count 0 2006.162.08:17:21.68#ibcon#about to write, iclass 7, count 0 2006.162.08:17:21.68#ibcon#wrote, iclass 7, count 0 2006.162.08:17:21.68#ibcon#about to read 3, iclass 7, count 0 2006.162.08:17:21.70#ibcon#read 3, iclass 7, count 0 2006.162.08:17:21.70#ibcon#about to read 4, iclass 7, count 0 2006.162.08:17:21.70#ibcon#read 4, iclass 7, count 0 2006.162.08:17:21.70#ibcon#about to read 5, iclass 7, count 0 2006.162.08:17:21.70#ibcon#read 5, iclass 7, count 0 2006.162.08:17:21.70#ibcon#about to read 6, iclass 7, count 0 2006.162.08:17:21.70#ibcon#read 6, iclass 7, count 0 2006.162.08:17:21.70#ibcon#end of sib2, iclass 7, count 0 2006.162.08:17:21.70#ibcon#*mode == 0, iclass 7, count 0 2006.162.08:17:21.70#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.162.08:17:21.70#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.08:17:21.70#ibcon#*before write, iclass 7, count 0 2006.162.08:17:21.70#ibcon#enter sib2, iclass 7, count 0 2006.162.08:17:21.70#ibcon#flushed, iclass 7, count 0 2006.162.08:17:21.70#ibcon#about to write, iclass 7, count 0 2006.162.08:17:21.70#ibcon#wrote, iclass 7, count 0 2006.162.08:17:21.70#ibcon#about to read 3, iclass 7, count 0 2006.162.08:17:21.74#ibcon#read 3, iclass 7, count 0 2006.162.08:17:21.74#ibcon#about to read 4, iclass 7, count 0 2006.162.08:17:21.74#ibcon#read 4, iclass 7, count 0 2006.162.08:17:21.74#ibcon#about to read 5, iclass 7, count 0 2006.162.08:17:21.74#ibcon#read 5, iclass 7, count 0 2006.162.08:17:21.74#ibcon#about to read 6, iclass 7, count 0 2006.162.08:17:21.74#ibcon#read 6, iclass 7, count 0 2006.162.08:17:21.74#ibcon#end of sib2, iclass 7, count 0 2006.162.08:17:21.74#ibcon#*after write, iclass 7, count 0 2006.162.08:17:21.74#ibcon#*before return 0, iclass 7, count 0 2006.162.08:17:21.74#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.162.08:17:21.74#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.162.08:17:21.74#ibcon#about to clear, iclass 7 cls_cnt 0 2006.162.08:17:21.74#ibcon#cleared, iclass 7 cls_cnt 0 2006.162.08:17:21.74$vc4f8/va=7,6 2006.162.08:17:21.74#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.162.08:17:21.74#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.162.08:17:21.74#ibcon#ireg 11 cls_cnt 2 2006.162.08:17:21.74#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.162.08:17:21.80#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.162.08:17:21.80#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.162.08:17:21.80#ibcon#enter wrdev, iclass 11, count 2 2006.162.08:17:21.80#ibcon#first serial, iclass 11, count 2 2006.162.08:17:21.80#ibcon#enter sib2, iclass 11, count 2 2006.162.08:17:21.80#ibcon#flushed, iclass 11, count 2 2006.162.08:17:21.80#ibcon#about to write, iclass 11, count 2 2006.162.08:17:21.80#ibcon#wrote, iclass 11, count 2 2006.162.08:17:21.80#ibcon#about to read 3, iclass 11, count 2 2006.162.08:17:21.82#ibcon#read 3, iclass 11, count 2 2006.162.08:17:21.82#ibcon#about to read 4, iclass 11, count 2 2006.162.08:17:21.82#ibcon#read 4, iclass 11, count 2 2006.162.08:17:21.82#ibcon#about to read 5, iclass 11, count 2 2006.162.08:17:21.82#ibcon#read 5, iclass 11, count 2 2006.162.08:17:21.82#ibcon#about to read 6, iclass 11, count 2 2006.162.08:17:21.82#ibcon#read 6, iclass 11, count 2 2006.162.08:17:21.82#ibcon#end of sib2, iclass 11, count 2 2006.162.08:17:21.82#ibcon#*mode == 0, iclass 11, count 2 2006.162.08:17:21.82#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.162.08:17:21.82#ibcon#[25=AT07-06\r\n] 2006.162.08:17:21.82#ibcon#*before write, iclass 11, count 2 2006.162.08:17:21.82#ibcon#enter sib2, iclass 11, count 2 2006.162.08:17:21.82#ibcon#flushed, iclass 11, count 2 2006.162.08:17:21.82#ibcon#about to write, iclass 11, count 2 2006.162.08:17:21.82#ibcon#wrote, iclass 11, count 2 2006.162.08:17:21.82#ibcon#about to read 3, iclass 11, count 2 2006.162.08:17:21.85#ibcon#read 3, iclass 11, count 2 2006.162.08:17:21.85#ibcon#about to read 4, iclass 11, count 2 2006.162.08:17:21.85#ibcon#read 4, iclass 11, count 2 2006.162.08:17:21.85#ibcon#about to read 5, iclass 11, count 2 2006.162.08:17:21.85#ibcon#read 5, iclass 11, count 2 2006.162.08:17:21.85#ibcon#about to read 6, iclass 11, count 2 2006.162.08:17:21.85#ibcon#read 6, iclass 11, count 2 2006.162.08:17:21.85#ibcon#end of sib2, iclass 11, count 2 2006.162.08:17:21.85#ibcon#*after write, iclass 11, count 2 2006.162.08:17:21.85#ibcon#*before return 0, iclass 11, count 2 2006.162.08:17:21.85#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.162.08:17:21.85#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.162.08:17:21.85#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.162.08:17:21.85#ibcon#ireg 7 cls_cnt 0 2006.162.08:17:21.85#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.162.08:17:21.97#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.162.08:17:21.97#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.162.08:17:21.97#ibcon#enter wrdev, iclass 11, count 0 2006.162.08:17:21.97#ibcon#first serial, iclass 11, count 0 2006.162.08:17:21.97#ibcon#enter sib2, iclass 11, count 0 2006.162.08:17:21.97#ibcon#flushed, iclass 11, count 0 2006.162.08:17:21.97#ibcon#about to write, iclass 11, count 0 2006.162.08:17:21.97#ibcon#wrote, iclass 11, count 0 2006.162.08:17:21.97#ibcon#about to read 3, iclass 11, count 0 2006.162.08:17:21.99#ibcon#read 3, iclass 11, count 0 2006.162.08:17:21.99#ibcon#about to read 4, iclass 11, count 0 2006.162.08:17:21.99#ibcon#read 4, iclass 11, count 0 2006.162.08:17:21.99#ibcon#about to read 5, iclass 11, count 0 2006.162.08:17:21.99#ibcon#read 5, iclass 11, count 0 2006.162.08:17:21.99#ibcon#about to read 6, iclass 11, count 0 2006.162.08:17:21.99#ibcon#read 6, iclass 11, count 0 2006.162.08:17:21.99#ibcon#end of sib2, iclass 11, count 0 2006.162.08:17:21.99#ibcon#*mode == 0, iclass 11, count 0 2006.162.08:17:21.99#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.162.08:17:21.99#ibcon#[25=USB\r\n] 2006.162.08:17:21.99#ibcon#*before write, iclass 11, count 0 2006.162.08:17:21.99#ibcon#enter sib2, iclass 11, count 0 2006.162.08:17:21.99#ibcon#flushed, iclass 11, count 0 2006.162.08:17:21.99#ibcon#about to write, iclass 11, count 0 2006.162.08:17:21.99#ibcon#wrote, iclass 11, count 0 2006.162.08:17:21.99#ibcon#about to read 3, iclass 11, count 0 2006.162.08:17:22.02#ibcon#read 3, iclass 11, count 0 2006.162.08:17:22.02#ibcon#about to read 4, iclass 11, count 0 2006.162.08:17:22.02#ibcon#read 4, iclass 11, count 0 2006.162.08:17:22.02#ibcon#about to read 5, iclass 11, count 0 2006.162.08:17:22.02#ibcon#read 5, iclass 11, count 0 2006.162.08:17:22.02#ibcon#about to read 6, iclass 11, count 0 2006.162.08:17:22.02#ibcon#read 6, iclass 11, count 0 2006.162.08:17:22.02#ibcon#end of sib2, iclass 11, count 0 2006.162.08:17:22.02#ibcon#*after write, iclass 11, count 0 2006.162.08:17:22.02#ibcon#*before return 0, iclass 11, count 0 2006.162.08:17:22.02#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.162.08:17:22.02#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.162.08:17:22.02#ibcon#about to clear, iclass 11 cls_cnt 0 2006.162.08:17:22.02#ibcon#cleared, iclass 11 cls_cnt 0 2006.162.08:17:22.02$vc4f8/valo=8,852.99 2006.162.08:17:22.02#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.162.08:17:22.02#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.162.08:17:22.02#ibcon#ireg 17 cls_cnt 0 2006.162.08:17:22.02#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.162.08:17:22.02#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.162.08:17:22.02#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.162.08:17:22.02#ibcon#enter wrdev, iclass 13, count 0 2006.162.08:17:22.02#ibcon#first serial, iclass 13, count 0 2006.162.08:17:22.02#ibcon#enter sib2, iclass 13, count 0 2006.162.08:17:22.02#ibcon#flushed, iclass 13, count 0 2006.162.08:17:22.02#ibcon#about to write, iclass 13, count 0 2006.162.08:17:22.02#ibcon#wrote, iclass 13, count 0 2006.162.08:17:22.02#ibcon#about to read 3, iclass 13, count 0 2006.162.08:17:22.04#ibcon#read 3, iclass 13, count 0 2006.162.08:17:22.04#ibcon#about to read 4, iclass 13, count 0 2006.162.08:17:22.04#ibcon#read 4, iclass 13, count 0 2006.162.08:17:22.04#ibcon#about to read 5, iclass 13, count 0 2006.162.08:17:22.04#ibcon#read 5, iclass 13, count 0 2006.162.08:17:22.04#ibcon#about to read 6, iclass 13, count 0 2006.162.08:17:22.04#ibcon#read 6, iclass 13, count 0 2006.162.08:17:22.04#ibcon#end of sib2, iclass 13, count 0 2006.162.08:17:22.04#ibcon#*mode == 0, iclass 13, count 0 2006.162.08:17:22.04#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.162.08:17:22.04#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.08:17:22.04#ibcon#*before write, iclass 13, count 0 2006.162.08:17:22.04#ibcon#enter sib2, iclass 13, count 0 2006.162.08:17:22.04#ibcon#flushed, iclass 13, count 0 2006.162.08:17:22.04#ibcon#about to write, iclass 13, count 0 2006.162.08:17:22.04#ibcon#wrote, iclass 13, count 0 2006.162.08:17:22.04#ibcon#about to read 3, iclass 13, count 0 2006.162.08:17:22.08#ibcon#read 3, iclass 13, count 0 2006.162.08:17:22.08#ibcon#about to read 4, iclass 13, count 0 2006.162.08:17:22.08#ibcon#read 4, iclass 13, count 0 2006.162.08:17:22.08#ibcon#about to read 5, iclass 13, count 0 2006.162.08:17:22.08#ibcon#read 5, iclass 13, count 0 2006.162.08:17:22.08#ibcon#about to read 6, iclass 13, count 0 2006.162.08:17:22.08#ibcon#read 6, iclass 13, count 0 2006.162.08:17:22.08#ibcon#end of sib2, iclass 13, count 0 2006.162.08:17:22.08#ibcon#*after write, iclass 13, count 0 2006.162.08:17:22.08#ibcon#*before return 0, iclass 13, count 0 2006.162.08:17:22.08#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.162.08:17:22.08#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.162.08:17:22.08#ibcon#about to clear, iclass 13 cls_cnt 0 2006.162.08:17:22.08#ibcon#cleared, iclass 13 cls_cnt 0 2006.162.08:17:22.08$vc4f8/va=8,7 2006.162.08:17:22.08#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.162.08:17:22.08#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.162.08:17:22.08#ibcon#ireg 11 cls_cnt 2 2006.162.08:17:22.08#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.162.08:17:22.15#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.162.08:17:22.15#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.162.08:17:22.15#ibcon#enter wrdev, iclass 15, count 2 2006.162.08:17:22.15#ibcon#first serial, iclass 15, count 2 2006.162.08:17:22.15#ibcon#enter sib2, iclass 15, count 2 2006.162.08:17:22.15#ibcon#flushed, iclass 15, count 2 2006.162.08:17:22.15#ibcon#about to write, iclass 15, count 2 2006.162.08:17:22.15#ibcon#wrote, iclass 15, count 2 2006.162.08:17:22.15#ibcon#about to read 3, iclass 15, count 2 2006.162.08:17:22.16#ibcon#read 3, iclass 15, count 2 2006.162.08:17:22.16#ibcon#about to read 4, iclass 15, count 2 2006.162.08:17:22.16#ibcon#read 4, iclass 15, count 2 2006.162.08:17:22.16#ibcon#about to read 5, iclass 15, count 2 2006.162.08:17:22.16#ibcon#read 5, iclass 15, count 2 2006.162.08:17:22.16#ibcon#about to read 6, iclass 15, count 2 2006.162.08:17:22.16#ibcon#read 6, iclass 15, count 2 2006.162.08:17:22.16#ibcon#end of sib2, iclass 15, count 2 2006.162.08:17:22.16#ibcon#*mode == 0, iclass 15, count 2 2006.162.08:17:22.16#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.162.08:17:22.16#ibcon#[25=AT08-07\r\n] 2006.162.08:17:22.16#ibcon#*before write, iclass 15, count 2 2006.162.08:17:22.16#ibcon#enter sib2, iclass 15, count 2 2006.162.08:17:22.16#ibcon#flushed, iclass 15, count 2 2006.162.08:17:22.16#ibcon#about to write, iclass 15, count 2 2006.162.08:17:22.16#ibcon#wrote, iclass 15, count 2 2006.162.08:17:22.16#ibcon#about to read 3, iclass 15, count 2 2006.162.08:17:22.19#ibcon#read 3, iclass 15, count 2 2006.162.08:17:22.19#ibcon#about to read 4, iclass 15, count 2 2006.162.08:17:22.19#ibcon#read 4, iclass 15, count 2 2006.162.08:17:22.19#ibcon#about to read 5, iclass 15, count 2 2006.162.08:17:22.19#ibcon#read 5, iclass 15, count 2 2006.162.08:17:22.19#ibcon#about to read 6, iclass 15, count 2 2006.162.08:17:22.19#ibcon#read 6, iclass 15, count 2 2006.162.08:17:22.19#ibcon#end of sib2, iclass 15, count 2 2006.162.08:17:22.19#ibcon#*after write, iclass 15, count 2 2006.162.08:17:22.19#ibcon#*before return 0, iclass 15, count 2 2006.162.08:17:22.19#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.162.08:17:22.19#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.162.08:17:22.19#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.162.08:17:22.19#ibcon#ireg 7 cls_cnt 0 2006.162.08:17:22.19#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.162.08:17:22.31#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.162.08:17:22.31#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.162.08:17:22.31#ibcon#enter wrdev, iclass 15, count 0 2006.162.08:17:22.31#ibcon#first serial, iclass 15, count 0 2006.162.08:17:22.31#ibcon#enter sib2, iclass 15, count 0 2006.162.08:17:22.31#ibcon#flushed, iclass 15, count 0 2006.162.08:17:22.31#ibcon#about to write, iclass 15, count 0 2006.162.08:17:22.31#ibcon#wrote, iclass 15, count 0 2006.162.08:17:22.31#ibcon#about to read 3, iclass 15, count 0 2006.162.08:17:22.33#ibcon#read 3, iclass 15, count 0 2006.162.08:17:22.33#ibcon#about to read 4, iclass 15, count 0 2006.162.08:17:22.33#ibcon#read 4, iclass 15, count 0 2006.162.08:17:22.33#ibcon#about to read 5, iclass 15, count 0 2006.162.08:17:22.33#ibcon#read 5, iclass 15, count 0 2006.162.08:17:22.33#ibcon#about to read 6, iclass 15, count 0 2006.162.08:17:22.33#ibcon#read 6, iclass 15, count 0 2006.162.08:17:22.33#ibcon#end of sib2, iclass 15, count 0 2006.162.08:17:22.33#ibcon#*mode == 0, iclass 15, count 0 2006.162.08:17:22.33#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.162.08:17:22.33#ibcon#[25=USB\r\n] 2006.162.08:17:22.33#ibcon#*before write, iclass 15, count 0 2006.162.08:17:22.33#ibcon#enter sib2, iclass 15, count 0 2006.162.08:17:22.33#ibcon#flushed, iclass 15, count 0 2006.162.08:17:22.33#ibcon#about to write, iclass 15, count 0 2006.162.08:17:22.33#ibcon#wrote, iclass 15, count 0 2006.162.08:17:22.33#ibcon#about to read 3, iclass 15, count 0 2006.162.08:17:22.36#ibcon#read 3, iclass 15, count 0 2006.162.08:17:22.36#ibcon#about to read 4, iclass 15, count 0 2006.162.08:17:22.36#ibcon#read 4, iclass 15, count 0 2006.162.08:17:22.36#ibcon#about to read 5, iclass 15, count 0 2006.162.08:17:22.36#ibcon#read 5, iclass 15, count 0 2006.162.08:17:22.36#ibcon#about to read 6, iclass 15, count 0 2006.162.08:17:22.36#ibcon#read 6, iclass 15, count 0 2006.162.08:17:22.36#ibcon#end of sib2, iclass 15, count 0 2006.162.08:17:22.36#ibcon#*after write, iclass 15, count 0 2006.162.08:17:22.36#ibcon#*before return 0, iclass 15, count 0 2006.162.08:17:22.36#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.162.08:17:22.36#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.162.08:17:22.36#ibcon#about to clear, iclass 15 cls_cnt 0 2006.162.08:17:22.36#ibcon#cleared, iclass 15 cls_cnt 0 2006.162.08:17:22.36$vc4f8/vblo=1,632.99 2006.162.08:17:22.36#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.162.08:17:22.36#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.162.08:17:22.36#ibcon#ireg 17 cls_cnt 0 2006.162.08:17:22.36#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.162.08:17:22.36#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.162.08:17:22.36#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.162.08:17:22.36#ibcon#enter wrdev, iclass 17, count 0 2006.162.08:17:22.36#ibcon#first serial, iclass 17, count 0 2006.162.08:17:22.36#ibcon#enter sib2, iclass 17, count 0 2006.162.08:17:22.36#ibcon#flushed, iclass 17, count 0 2006.162.08:17:22.36#ibcon#about to write, iclass 17, count 0 2006.162.08:17:22.36#ibcon#wrote, iclass 17, count 0 2006.162.08:17:22.36#ibcon#about to read 3, iclass 17, count 0 2006.162.08:17:22.38#ibcon#read 3, iclass 17, count 0 2006.162.08:17:22.38#ibcon#about to read 4, iclass 17, count 0 2006.162.08:17:22.38#ibcon#read 4, iclass 17, count 0 2006.162.08:17:22.38#ibcon#about to read 5, iclass 17, count 0 2006.162.08:17:22.38#ibcon#read 5, iclass 17, count 0 2006.162.08:17:22.38#ibcon#about to read 6, iclass 17, count 0 2006.162.08:17:22.38#ibcon#read 6, iclass 17, count 0 2006.162.08:17:22.38#ibcon#end of sib2, iclass 17, count 0 2006.162.08:17:22.38#ibcon#*mode == 0, iclass 17, count 0 2006.162.08:17:22.38#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.162.08:17:22.38#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.08:17:22.38#ibcon#*before write, iclass 17, count 0 2006.162.08:17:22.38#ibcon#enter sib2, iclass 17, count 0 2006.162.08:17:22.38#ibcon#flushed, iclass 17, count 0 2006.162.08:17:22.38#ibcon#about to write, iclass 17, count 0 2006.162.08:17:22.38#ibcon#wrote, iclass 17, count 0 2006.162.08:17:22.38#ibcon#about to read 3, iclass 17, count 0 2006.162.08:17:22.42#ibcon#read 3, iclass 17, count 0 2006.162.08:17:22.42#ibcon#about to read 4, iclass 17, count 0 2006.162.08:17:22.42#ibcon#read 4, iclass 17, count 0 2006.162.08:17:22.42#ibcon#about to read 5, iclass 17, count 0 2006.162.08:17:22.42#ibcon#read 5, iclass 17, count 0 2006.162.08:17:22.42#ibcon#about to read 6, iclass 17, count 0 2006.162.08:17:22.42#ibcon#read 6, iclass 17, count 0 2006.162.08:17:22.42#ibcon#end of sib2, iclass 17, count 0 2006.162.08:17:22.42#ibcon#*after write, iclass 17, count 0 2006.162.08:17:22.42#ibcon#*before return 0, iclass 17, count 0 2006.162.08:17:22.42#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.162.08:17:22.42#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.162.08:17:22.42#ibcon#about to clear, iclass 17 cls_cnt 0 2006.162.08:17:22.42#ibcon#cleared, iclass 17 cls_cnt 0 2006.162.08:17:22.42$vc4f8/vb=1,4 2006.162.08:17:22.42#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.162.08:17:22.42#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.162.08:17:22.42#ibcon#ireg 11 cls_cnt 2 2006.162.08:17:22.42#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.162.08:17:22.42#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.162.08:17:22.42#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.162.08:17:22.42#ibcon#enter wrdev, iclass 19, count 2 2006.162.08:17:22.42#ibcon#first serial, iclass 19, count 2 2006.162.08:17:22.42#ibcon#enter sib2, iclass 19, count 2 2006.162.08:17:22.42#ibcon#flushed, iclass 19, count 2 2006.162.08:17:22.42#ibcon#about to write, iclass 19, count 2 2006.162.08:17:22.42#ibcon#wrote, iclass 19, count 2 2006.162.08:17:22.42#ibcon#about to read 3, iclass 19, count 2 2006.162.08:17:22.44#ibcon#read 3, iclass 19, count 2 2006.162.08:17:22.44#ibcon#about to read 4, iclass 19, count 2 2006.162.08:17:22.44#ibcon#read 4, iclass 19, count 2 2006.162.08:17:22.44#ibcon#about to read 5, iclass 19, count 2 2006.162.08:17:22.44#ibcon#read 5, iclass 19, count 2 2006.162.08:17:22.44#ibcon#about to read 6, iclass 19, count 2 2006.162.08:17:22.44#ibcon#read 6, iclass 19, count 2 2006.162.08:17:22.44#ibcon#end of sib2, iclass 19, count 2 2006.162.08:17:22.44#ibcon#*mode == 0, iclass 19, count 2 2006.162.08:17:22.44#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.162.08:17:22.44#ibcon#[27=AT01-04\r\n] 2006.162.08:17:22.44#ibcon#*before write, iclass 19, count 2 2006.162.08:17:22.44#ibcon#enter sib2, iclass 19, count 2 2006.162.08:17:22.44#ibcon#flushed, iclass 19, count 2 2006.162.08:17:22.44#ibcon#about to write, iclass 19, count 2 2006.162.08:17:22.44#ibcon#wrote, iclass 19, count 2 2006.162.08:17:22.44#ibcon#about to read 3, iclass 19, count 2 2006.162.08:17:22.47#ibcon#read 3, iclass 19, count 2 2006.162.08:17:22.47#ibcon#about to read 4, iclass 19, count 2 2006.162.08:17:22.47#ibcon#read 4, iclass 19, count 2 2006.162.08:17:22.47#ibcon#about to read 5, iclass 19, count 2 2006.162.08:17:22.47#ibcon#read 5, iclass 19, count 2 2006.162.08:17:22.47#ibcon#about to read 6, iclass 19, count 2 2006.162.08:17:22.47#ibcon#read 6, iclass 19, count 2 2006.162.08:17:22.47#ibcon#end of sib2, iclass 19, count 2 2006.162.08:17:22.47#ibcon#*after write, iclass 19, count 2 2006.162.08:17:22.47#ibcon#*before return 0, iclass 19, count 2 2006.162.08:17:22.47#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.162.08:17:22.47#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.162.08:17:22.47#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.162.08:17:22.47#ibcon#ireg 7 cls_cnt 0 2006.162.08:17:22.47#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.162.08:17:22.59#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.162.08:17:22.59#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.162.08:17:22.59#ibcon#enter wrdev, iclass 19, count 0 2006.162.08:17:22.59#ibcon#first serial, iclass 19, count 0 2006.162.08:17:22.59#ibcon#enter sib2, iclass 19, count 0 2006.162.08:17:22.59#ibcon#flushed, iclass 19, count 0 2006.162.08:17:22.59#ibcon#about to write, iclass 19, count 0 2006.162.08:17:22.59#ibcon#wrote, iclass 19, count 0 2006.162.08:17:22.59#ibcon#about to read 3, iclass 19, count 0 2006.162.08:17:22.61#ibcon#read 3, iclass 19, count 0 2006.162.08:17:22.61#ibcon#about to read 4, iclass 19, count 0 2006.162.08:17:22.61#ibcon#read 4, iclass 19, count 0 2006.162.08:17:22.61#ibcon#about to read 5, iclass 19, count 0 2006.162.08:17:22.61#ibcon#read 5, iclass 19, count 0 2006.162.08:17:22.61#ibcon#about to read 6, iclass 19, count 0 2006.162.08:17:22.61#ibcon#read 6, iclass 19, count 0 2006.162.08:17:22.61#ibcon#end of sib2, iclass 19, count 0 2006.162.08:17:22.61#ibcon#*mode == 0, iclass 19, count 0 2006.162.08:17:22.61#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.162.08:17:22.61#ibcon#[27=USB\r\n] 2006.162.08:17:22.61#ibcon#*before write, iclass 19, count 0 2006.162.08:17:22.61#ibcon#enter sib2, iclass 19, count 0 2006.162.08:17:22.61#ibcon#flushed, iclass 19, count 0 2006.162.08:17:22.61#ibcon#about to write, iclass 19, count 0 2006.162.08:17:22.61#ibcon#wrote, iclass 19, count 0 2006.162.08:17:22.61#ibcon#about to read 3, iclass 19, count 0 2006.162.08:17:22.64#ibcon#read 3, iclass 19, count 0 2006.162.08:17:22.64#ibcon#about to read 4, iclass 19, count 0 2006.162.08:17:22.64#ibcon#read 4, iclass 19, count 0 2006.162.08:17:22.64#ibcon#about to read 5, iclass 19, count 0 2006.162.08:17:22.64#ibcon#read 5, iclass 19, count 0 2006.162.08:17:22.64#ibcon#about to read 6, iclass 19, count 0 2006.162.08:17:22.64#ibcon#read 6, iclass 19, count 0 2006.162.08:17:22.64#ibcon#end of sib2, iclass 19, count 0 2006.162.08:17:22.64#ibcon#*after write, iclass 19, count 0 2006.162.08:17:22.64#ibcon#*before return 0, iclass 19, count 0 2006.162.08:17:22.64#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.162.08:17:22.64#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.162.08:17:22.64#ibcon#about to clear, iclass 19 cls_cnt 0 2006.162.08:17:22.64#ibcon#cleared, iclass 19 cls_cnt 0 2006.162.08:17:22.64$vc4f8/vblo=2,640.99 2006.162.08:17:22.64#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.162.08:17:22.64#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.162.08:17:22.64#ibcon#ireg 17 cls_cnt 0 2006.162.08:17:22.64#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:17:22.64#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:17:22.64#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:17:22.64#ibcon#enter wrdev, iclass 21, count 0 2006.162.08:17:22.64#ibcon#first serial, iclass 21, count 0 2006.162.08:17:22.64#ibcon#enter sib2, iclass 21, count 0 2006.162.08:17:22.64#ibcon#flushed, iclass 21, count 0 2006.162.08:17:22.64#ibcon#about to write, iclass 21, count 0 2006.162.08:17:22.64#ibcon#wrote, iclass 21, count 0 2006.162.08:17:22.64#ibcon#about to read 3, iclass 21, count 0 2006.162.08:17:22.66#ibcon#read 3, iclass 21, count 0 2006.162.08:17:22.66#ibcon#about to read 4, iclass 21, count 0 2006.162.08:17:22.66#ibcon#read 4, iclass 21, count 0 2006.162.08:17:22.66#ibcon#about to read 5, iclass 21, count 0 2006.162.08:17:22.66#ibcon#read 5, iclass 21, count 0 2006.162.08:17:22.66#ibcon#about to read 6, iclass 21, count 0 2006.162.08:17:22.66#ibcon#read 6, iclass 21, count 0 2006.162.08:17:22.66#ibcon#end of sib2, iclass 21, count 0 2006.162.08:17:22.66#ibcon#*mode == 0, iclass 21, count 0 2006.162.08:17:22.66#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.162.08:17:22.66#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.08:17:22.66#ibcon#*before write, iclass 21, count 0 2006.162.08:17:22.66#ibcon#enter sib2, iclass 21, count 0 2006.162.08:17:22.66#ibcon#flushed, iclass 21, count 0 2006.162.08:17:22.66#ibcon#about to write, iclass 21, count 0 2006.162.08:17:22.66#ibcon#wrote, iclass 21, count 0 2006.162.08:17:22.66#ibcon#about to read 3, iclass 21, count 0 2006.162.08:17:22.70#ibcon#read 3, iclass 21, count 0 2006.162.08:17:22.70#ibcon#about to read 4, iclass 21, count 0 2006.162.08:17:22.70#ibcon#read 4, iclass 21, count 0 2006.162.08:17:22.70#ibcon#about to read 5, iclass 21, count 0 2006.162.08:17:22.70#ibcon#read 5, iclass 21, count 0 2006.162.08:17:22.70#ibcon#about to read 6, iclass 21, count 0 2006.162.08:17:22.70#ibcon#read 6, iclass 21, count 0 2006.162.08:17:22.70#ibcon#end of sib2, iclass 21, count 0 2006.162.08:17:22.70#ibcon#*after write, iclass 21, count 0 2006.162.08:17:22.70#ibcon#*before return 0, iclass 21, count 0 2006.162.08:17:22.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:17:22.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:17:22.70#ibcon#about to clear, iclass 21 cls_cnt 0 2006.162.08:17:22.70#ibcon#cleared, iclass 21 cls_cnt 0 2006.162.08:17:22.70$vc4f8/vb=2,4 2006.162.08:17:22.70#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.162.08:17:22.70#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.162.08:17:22.70#ibcon#ireg 11 cls_cnt 2 2006.162.08:17:22.70#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:17:22.76#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:17:22.76#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:17:22.76#ibcon#enter wrdev, iclass 23, count 2 2006.162.08:17:22.76#ibcon#first serial, iclass 23, count 2 2006.162.08:17:22.76#ibcon#enter sib2, iclass 23, count 2 2006.162.08:17:22.76#ibcon#flushed, iclass 23, count 2 2006.162.08:17:22.76#ibcon#about to write, iclass 23, count 2 2006.162.08:17:22.76#ibcon#wrote, iclass 23, count 2 2006.162.08:17:22.76#ibcon#about to read 3, iclass 23, count 2 2006.162.08:17:22.78#ibcon#read 3, iclass 23, count 2 2006.162.08:17:22.78#ibcon#about to read 4, iclass 23, count 2 2006.162.08:17:22.78#ibcon#read 4, iclass 23, count 2 2006.162.08:17:22.78#ibcon#about to read 5, iclass 23, count 2 2006.162.08:17:22.78#ibcon#read 5, iclass 23, count 2 2006.162.08:17:22.78#ibcon#about to read 6, iclass 23, count 2 2006.162.08:17:22.78#ibcon#read 6, iclass 23, count 2 2006.162.08:17:22.78#ibcon#end of sib2, iclass 23, count 2 2006.162.08:17:22.78#ibcon#*mode == 0, iclass 23, count 2 2006.162.08:17:22.78#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.162.08:17:22.78#ibcon#[27=AT02-04\r\n] 2006.162.08:17:22.78#ibcon#*before write, iclass 23, count 2 2006.162.08:17:22.78#ibcon#enter sib2, iclass 23, count 2 2006.162.08:17:22.78#ibcon#flushed, iclass 23, count 2 2006.162.08:17:22.78#ibcon#about to write, iclass 23, count 2 2006.162.08:17:22.78#ibcon#wrote, iclass 23, count 2 2006.162.08:17:22.78#ibcon#about to read 3, iclass 23, count 2 2006.162.08:17:22.81#ibcon#read 3, iclass 23, count 2 2006.162.08:17:22.81#ibcon#about to read 4, iclass 23, count 2 2006.162.08:17:22.81#ibcon#read 4, iclass 23, count 2 2006.162.08:17:22.81#ibcon#about to read 5, iclass 23, count 2 2006.162.08:17:22.81#ibcon#read 5, iclass 23, count 2 2006.162.08:17:22.81#ibcon#about to read 6, iclass 23, count 2 2006.162.08:17:22.81#ibcon#read 6, iclass 23, count 2 2006.162.08:17:22.81#ibcon#end of sib2, iclass 23, count 2 2006.162.08:17:22.81#ibcon#*after write, iclass 23, count 2 2006.162.08:17:22.81#ibcon#*before return 0, iclass 23, count 2 2006.162.08:17:22.81#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:17:22.81#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:17:22.81#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.162.08:17:22.81#ibcon#ireg 7 cls_cnt 0 2006.162.08:17:22.81#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:17:22.93#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:17:22.93#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:17:22.93#ibcon#enter wrdev, iclass 23, count 0 2006.162.08:17:22.93#ibcon#first serial, iclass 23, count 0 2006.162.08:17:22.93#ibcon#enter sib2, iclass 23, count 0 2006.162.08:17:22.93#ibcon#flushed, iclass 23, count 0 2006.162.08:17:22.93#ibcon#about to write, iclass 23, count 0 2006.162.08:17:22.93#ibcon#wrote, iclass 23, count 0 2006.162.08:17:22.93#ibcon#about to read 3, iclass 23, count 0 2006.162.08:17:22.95#ibcon#read 3, iclass 23, count 0 2006.162.08:17:22.95#ibcon#about to read 4, iclass 23, count 0 2006.162.08:17:22.95#ibcon#read 4, iclass 23, count 0 2006.162.08:17:22.95#ibcon#about to read 5, iclass 23, count 0 2006.162.08:17:22.95#ibcon#read 5, iclass 23, count 0 2006.162.08:17:22.95#ibcon#about to read 6, iclass 23, count 0 2006.162.08:17:22.95#ibcon#read 6, iclass 23, count 0 2006.162.08:17:22.95#ibcon#end of sib2, iclass 23, count 0 2006.162.08:17:22.95#ibcon#*mode == 0, iclass 23, count 0 2006.162.08:17:22.95#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.162.08:17:22.95#ibcon#[27=USB\r\n] 2006.162.08:17:22.95#ibcon#*before write, iclass 23, count 0 2006.162.08:17:22.95#ibcon#enter sib2, iclass 23, count 0 2006.162.08:17:22.95#ibcon#flushed, iclass 23, count 0 2006.162.08:17:22.95#ibcon#about to write, iclass 23, count 0 2006.162.08:17:22.95#ibcon#wrote, iclass 23, count 0 2006.162.08:17:22.95#ibcon#about to read 3, iclass 23, count 0 2006.162.08:17:22.98#ibcon#read 3, iclass 23, count 0 2006.162.08:17:22.98#ibcon#about to read 4, iclass 23, count 0 2006.162.08:17:22.98#ibcon#read 4, iclass 23, count 0 2006.162.08:17:22.98#ibcon#about to read 5, iclass 23, count 0 2006.162.08:17:22.98#ibcon#read 5, iclass 23, count 0 2006.162.08:17:22.98#ibcon#about to read 6, iclass 23, count 0 2006.162.08:17:22.98#ibcon#read 6, iclass 23, count 0 2006.162.08:17:22.98#ibcon#end of sib2, iclass 23, count 0 2006.162.08:17:22.98#ibcon#*after write, iclass 23, count 0 2006.162.08:17:22.98#ibcon#*before return 0, iclass 23, count 0 2006.162.08:17:22.98#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:17:22.98#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:17:22.98#ibcon#about to clear, iclass 23 cls_cnt 0 2006.162.08:17:22.98#ibcon#cleared, iclass 23 cls_cnt 0 2006.162.08:17:22.98$vc4f8/vblo=3,656.99 2006.162.08:17:22.98#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.162.08:17:22.98#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.162.08:17:22.98#ibcon#ireg 17 cls_cnt 0 2006.162.08:17:22.98#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:17:22.98#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:17:22.98#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:17:22.98#ibcon#enter wrdev, iclass 25, count 0 2006.162.08:17:22.98#ibcon#first serial, iclass 25, count 0 2006.162.08:17:22.98#ibcon#enter sib2, iclass 25, count 0 2006.162.08:17:22.98#ibcon#flushed, iclass 25, count 0 2006.162.08:17:22.98#ibcon#about to write, iclass 25, count 0 2006.162.08:17:22.98#ibcon#wrote, iclass 25, count 0 2006.162.08:17:22.98#ibcon#about to read 3, iclass 25, count 0 2006.162.08:17:23.00#ibcon#read 3, iclass 25, count 0 2006.162.08:17:23.00#ibcon#about to read 4, iclass 25, count 0 2006.162.08:17:23.00#ibcon#read 4, iclass 25, count 0 2006.162.08:17:23.00#ibcon#about to read 5, iclass 25, count 0 2006.162.08:17:23.00#ibcon#read 5, iclass 25, count 0 2006.162.08:17:23.00#ibcon#about to read 6, iclass 25, count 0 2006.162.08:17:23.00#ibcon#read 6, iclass 25, count 0 2006.162.08:17:23.00#ibcon#end of sib2, iclass 25, count 0 2006.162.08:17:23.00#ibcon#*mode == 0, iclass 25, count 0 2006.162.08:17:23.00#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.162.08:17:23.00#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.08:17:23.00#ibcon#*before write, iclass 25, count 0 2006.162.08:17:23.00#ibcon#enter sib2, iclass 25, count 0 2006.162.08:17:23.00#ibcon#flushed, iclass 25, count 0 2006.162.08:17:23.00#ibcon#about to write, iclass 25, count 0 2006.162.08:17:23.00#ibcon#wrote, iclass 25, count 0 2006.162.08:17:23.00#ibcon#about to read 3, iclass 25, count 0 2006.162.08:17:23.04#ibcon#read 3, iclass 25, count 0 2006.162.08:17:23.04#ibcon#about to read 4, iclass 25, count 0 2006.162.08:17:23.04#ibcon#read 4, iclass 25, count 0 2006.162.08:17:23.04#ibcon#about to read 5, iclass 25, count 0 2006.162.08:17:23.04#ibcon#read 5, iclass 25, count 0 2006.162.08:17:23.04#ibcon#about to read 6, iclass 25, count 0 2006.162.08:17:23.04#ibcon#read 6, iclass 25, count 0 2006.162.08:17:23.04#ibcon#end of sib2, iclass 25, count 0 2006.162.08:17:23.04#ibcon#*after write, iclass 25, count 0 2006.162.08:17:23.04#ibcon#*before return 0, iclass 25, count 0 2006.162.08:17:23.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:17:23.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:17:23.04#ibcon#about to clear, iclass 25 cls_cnt 0 2006.162.08:17:23.04#ibcon#cleared, iclass 25 cls_cnt 0 2006.162.08:17:23.04$vc4f8/vb=3,4 2006.162.08:17:23.04#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.162.08:17:23.04#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.162.08:17:23.04#ibcon#ireg 11 cls_cnt 2 2006.162.08:17:23.04#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:17:23.10#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:17:23.10#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:17:23.10#ibcon#enter wrdev, iclass 27, count 2 2006.162.08:17:23.10#ibcon#first serial, iclass 27, count 2 2006.162.08:17:23.10#ibcon#enter sib2, iclass 27, count 2 2006.162.08:17:23.10#ibcon#flushed, iclass 27, count 2 2006.162.08:17:23.10#ibcon#about to write, iclass 27, count 2 2006.162.08:17:23.10#ibcon#wrote, iclass 27, count 2 2006.162.08:17:23.10#ibcon#about to read 3, iclass 27, count 2 2006.162.08:17:23.12#ibcon#read 3, iclass 27, count 2 2006.162.08:17:23.12#ibcon#about to read 4, iclass 27, count 2 2006.162.08:17:23.12#ibcon#read 4, iclass 27, count 2 2006.162.08:17:23.12#ibcon#about to read 5, iclass 27, count 2 2006.162.08:17:23.12#ibcon#read 5, iclass 27, count 2 2006.162.08:17:23.12#ibcon#about to read 6, iclass 27, count 2 2006.162.08:17:23.12#ibcon#read 6, iclass 27, count 2 2006.162.08:17:23.12#ibcon#end of sib2, iclass 27, count 2 2006.162.08:17:23.12#ibcon#*mode == 0, iclass 27, count 2 2006.162.08:17:23.12#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.162.08:17:23.12#ibcon#[27=AT03-04\r\n] 2006.162.08:17:23.12#ibcon#*before write, iclass 27, count 2 2006.162.08:17:23.12#ibcon#enter sib2, iclass 27, count 2 2006.162.08:17:23.12#ibcon#flushed, iclass 27, count 2 2006.162.08:17:23.12#ibcon#about to write, iclass 27, count 2 2006.162.08:17:23.12#ibcon#wrote, iclass 27, count 2 2006.162.08:17:23.12#ibcon#about to read 3, iclass 27, count 2 2006.162.08:17:23.15#ibcon#read 3, iclass 27, count 2 2006.162.08:17:23.15#ibcon#about to read 4, iclass 27, count 2 2006.162.08:17:23.15#ibcon#read 4, iclass 27, count 2 2006.162.08:17:23.15#ibcon#about to read 5, iclass 27, count 2 2006.162.08:17:23.15#ibcon#read 5, iclass 27, count 2 2006.162.08:17:23.15#ibcon#about to read 6, iclass 27, count 2 2006.162.08:17:23.15#ibcon#read 6, iclass 27, count 2 2006.162.08:17:23.15#ibcon#end of sib2, iclass 27, count 2 2006.162.08:17:23.15#ibcon#*after write, iclass 27, count 2 2006.162.08:17:23.15#ibcon#*before return 0, iclass 27, count 2 2006.162.08:17:23.15#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:17:23.15#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:17:23.15#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.162.08:17:23.15#ibcon#ireg 7 cls_cnt 0 2006.162.08:17:23.15#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:17:23.27#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:17:23.27#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:17:23.27#ibcon#enter wrdev, iclass 27, count 0 2006.162.08:17:23.27#ibcon#first serial, iclass 27, count 0 2006.162.08:17:23.27#ibcon#enter sib2, iclass 27, count 0 2006.162.08:17:23.27#ibcon#flushed, iclass 27, count 0 2006.162.08:17:23.27#ibcon#about to write, iclass 27, count 0 2006.162.08:17:23.27#ibcon#wrote, iclass 27, count 0 2006.162.08:17:23.27#ibcon#about to read 3, iclass 27, count 0 2006.162.08:17:23.29#ibcon#read 3, iclass 27, count 0 2006.162.08:17:23.29#ibcon#about to read 4, iclass 27, count 0 2006.162.08:17:23.29#ibcon#read 4, iclass 27, count 0 2006.162.08:17:23.29#ibcon#about to read 5, iclass 27, count 0 2006.162.08:17:23.29#ibcon#read 5, iclass 27, count 0 2006.162.08:17:23.29#ibcon#about to read 6, iclass 27, count 0 2006.162.08:17:23.29#ibcon#read 6, iclass 27, count 0 2006.162.08:17:23.29#ibcon#end of sib2, iclass 27, count 0 2006.162.08:17:23.29#ibcon#*mode == 0, iclass 27, count 0 2006.162.08:17:23.29#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.162.08:17:23.29#ibcon#[27=USB\r\n] 2006.162.08:17:23.29#ibcon#*before write, iclass 27, count 0 2006.162.08:17:23.29#ibcon#enter sib2, iclass 27, count 0 2006.162.08:17:23.29#ibcon#flushed, iclass 27, count 0 2006.162.08:17:23.29#ibcon#about to write, iclass 27, count 0 2006.162.08:17:23.29#ibcon#wrote, iclass 27, count 0 2006.162.08:17:23.29#ibcon#about to read 3, iclass 27, count 0 2006.162.08:17:23.32#ibcon#read 3, iclass 27, count 0 2006.162.08:17:23.32#ibcon#about to read 4, iclass 27, count 0 2006.162.08:17:23.32#ibcon#read 4, iclass 27, count 0 2006.162.08:17:23.32#ibcon#about to read 5, iclass 27, count 0 2006.162.08:17:23.32#ibcon#read 5, iclass 27, count 0 2006.162.08:17:23.32#ibcon#about to read 6, iclass 27, count 0 2006.162.08:17:23.32#ibcon#read 6, iclass 27, count 0 2006.162.08:17:23.32#ibcon#end of sib2, iclass 27, count 0 2006.162.08:17:23.32#ibcon#*after write, iclass 27, count 0 2006.162.08:17:23.32#ibcon#*before return 0, iclass 27, count 0 2006.162.08:17:23.32#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:17:23.32#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:17:23.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.162.08:17:23.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.162.08:17:23.32$vc4f8/vblo=4,712.99 2006.162.08:17:23.32#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.162.08:17:23.32#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.162.08:17:23.32#ibcon#ireg 17 cls_cnt 0 2006.162.08:17:23.32#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:17:23.32#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:17:23.32#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:17:23.32#ibcon#enter wrdev, iclass 29, count 0 2006.162.08:17:23.32#ibcon#first serial, iclass 29, count 0 2006.162.08:17:23.32#ibcon#enter sib2, iclass 29, count 0 2006.162.08:17:23.32#ibcon#flushed, iclass 29, count 0 2006.162.08:17:23.32#ibcon#about to write, iclass 29, count 0 2006.162.08:17:23.32#ibcon#wrote, iclass 29, count 0 2006.162.08:17:23.32#ibcon#about to read 3, iclass 29, count 0 2006.162.08:17:23.34#ibcon#read 3, iclass 29, count 0 2006.162.08:17:23.34#ibcon#about to read 4, iclass 29, count 0 2006.162.08:17:23.34#ibcon#read 4, iclass 29, count 0 2006.162.08:17:23.34#ibcon#about to read 5, iclass 29, count 0 2006.162.08:17:23.34#ibcon#read 5, iclass 29, count 0 2006.162.08:17:23.34#ibcon#about to read 6, iclass 29, count 0 2006.162.08:17:23.34#ibcon#read 6, iclass 29, count 0 2006.162.08:17:23.34#ibcon#end of sib2, iclass 29, count 0 2006.162.08:17:23.34#ibcon#*mode == 0, iclass 29, count 0 2006.162.08:17:23.34#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.162.08:17:23.34#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.08:17:23.34#ibcon#*before write, iclass 29, count 0 2006.162.08:17:23.34#ibcon#enter sib2, iclass 29, count 0 2006.162.08:17:23.34#ibcon#flushed, iclass 29, count 0 2006.162.08:17:23.34#ibcon#about to write, iclass 29, count 0 2006.162.08:17:23.34#ibcon#wrote, iclass 29, count 0 2006.162.08:17:23.34#ibcon#about to read 3, iclass 29, count 0 2006.162.08:17:23.38#ibcon#read 3, iclass 29, count 0 2006.162.08:17:23.38#ibcon#about to read 4, iclass 29, count 0 2006.162.08:17:23.38#ibcon#read 4, iclass 29, count 0 2006.162.08:17:23.38#ibcon#about to read 5, iclass 29, count 0 2006.162.08:17:23.38#ibcon#read 5, iclass 29, count 0 2006.162.08:17:23.38#ibcon#about to read 6, iclass 29, count 0 2006.162.08:17:23.38#ibcon#read 6, iclass 29, count 0 2006.162.08:17:23.38#ibcon#end of sib2, iclass 29, count 0 2006.162.08:17:23.38#ibcon#*after write, iclass 29, count 0 2006.162.08:17:23.38#ibcon#*before return 0, iclass 29, count 0 2006.162.08:17:23.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:17:23.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:17:23.38#ibcon#about to clear, iclass 29 cls_cnt 0 2006.162.08:17:23.38#ibcon#cleared, iclass 29 cls_cnt 0 2006.162.08:17:23.38$vc4f8/vb=4,4 2006.162.08:17:23.38#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.162.08:17:23.38#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.162.08:17:23.38#ibcon#ireg 11 cls_cnt 2 2006.162.08:17:23.38#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:17:23.44#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:17:23.44#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:17:23.44#ibcon#enter wrdev, iclass 31, count 2 2006.162.08:17:23.44#ibcon#first serial, iclass 31, count 2 2006.162.08:17:23.44#ibcon#enter sib2, iclass 31, count 2 2006.162.08:17:23.44#ibcon#flushed, iclass 31, count 2 2006.162.08:17:23.44#ibcon#about to write, iclass 31, count 2 2006.162.08:17:23.44#ibcon#wrote, iclass 31, count 2 2006.162.08:17:23.44#ibcon#about to read 3, iclass 31, count 2 2006.162.08:17:23.46#ibcon#read 3, iclass 31, count 2 2006.162.08:17:23.46#ibcon#about to read 4, iclass 31, count 2 2006.162.08:17:23.46#ibcon#read 4, iclass 31, count 2 2006.162.08:17:23.46#ibcon#about to read 5, iclass 31, count 2 2006.162.08:17:23.46#ibcon#read 5, iclass 31, count 2 2006.162.08:17:23.46#ibcon#about to read 6, iclass 31, count 2 2006.162.08:17:23.46#ibcon#read 6, iclass 31, count 2 2006.162.08:17:23.46#ibcon#end of sib2, iclass 31, count 2 2006.162.08:17:23.46#ibcon#*mode == 0, iclass 31, count 2 2006.162.08:17:23.46#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.162.08:17:23.46#ibcon#[27=AT04-04\r\n] 2006.162.08:17:23.46#ibcon#*before write, iclass 31, count 2 2006.162.08:17:23.46#ibcon#enter sib2, iclass 31, count 2 2006.162.08:17:23.46#ibcon#flushed, iclass 31, count 2 2006.162.08:17:23.46#ibcon#about to write, iclass 31, count 2 2006.162.08:17:23.46#ibcon#wrote, iclass 31, count 2 2006.162.08:17:23.46#ibcon#about to read 3, iclass 31, count 2 2006.162.08:17:23.49#ibcon#read 3, iclass 31, count 2 2006.162.08:17:23.49#ibcon#about to read 4, iclass 31, count 2 2006.162.08:17:23.49#ibcon#read 4, iclass 31, count 2 2006.162.08:17:23.49#ibcon#about to read 5, iclass 31, count 2 2006.162.08:17:23.49#ibcon#read 5, iclass 31, count 2 2006.162.08:17:23.49#ibcon#about to read 6, iclass 31, count 2 2006.162.08:17:23.49#ibcon#read 6, iclass 31, count 2 2006.162.08:17:23.49#ibcon#end of sib2, iclass 31, count 2 2006.162.08:17:23.49#ibcon#*after write, iclass 31, count 2 2006.162.08:17:23.49#ibcon#*before return 0, iclass 31, count 2 2006.162.08:17:23.49#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:17:23.49#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:17:23.49#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.162.08:17:23.49#ibcon#ireg 7 cls_cnt 0 2006.162.08:17:23.49#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:17:23.61#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:17:23.61#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:17:23.61#ibcon#enter wrdev, iclass 31, count 0 2006.162.08:17:23.61#ibcon#first serial, iclass 31, count 0 2006.162.08:17:23.61#ibcon#enter sib2, iclass 31, count 0 2006.162.08:17:23.61#ibcon#flushed, iclass 31, count 0 2006.162.08:17:23.61#ibcon#about to write, iclass 31, count 0 2006.162.08:17:23.61#ibcon#wrote, iclass 31, count 0 2006.162.08:17:23.61#ibcon#about to read 3, iclass 31, count 0 2006.162.08:17:23.63#ibcon#read 3, iclass 31, count 0 2006.162.08:17:23.63#ibcon#about to read 4, iclass 31, count 0 2006.162.08:17:23.63#ibcon#read 4, iclass 31, count 0 2006.162.08:17:23.63#ibcon#about to read 5, iclass 31, count 0 2006.162.08:17:23.63#ibcon#read 5, iclass 31, count 0 2006.162.08:17:23.63#ibcon#about to read 6, iclass 31, count 0 2006.162.08:17:23.63#ibcon#read 6, iclass 31, count 0 2006.162.08:17:23.63#ibcon#end of sib2, iclass 31, count 0 2006.162.08:17:23.63#ibcon#*mode == 0, iclass 31, count 0 2006.162.08:17:23.63#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.162.08:17:23.63#ibcon#[27=USB\r\n] 2006.162.08:17:23.63#ibcon#*before write, iclass 31, count 0 2006.162.08:17:23.63#ibcon#enter sib2, iclass 31, count 0 2006.162.08:17:23.63#ibcon#flushed, iclass 31, count 0 2006.162.08:17:23.63#ibcon#about to write, iclass 31, count 0 2006.162.08:17:23.63#ibcon#wrote, iclass 31, count 0 2006.162.08:17:23.63#ibcon#about to read 3, iclass 31, count 0 2006.162.08:17:23.66#ibcon#read 3, iclass 31, count 0 2006.162.08:17:23.66#ibcon#about to read 4, iclass 31, count 0 2006.162.08:17:23.66#ibcon#read 4, iclass 31, count 0 2006.162.08:17:23.66#ibcon#about to read 5, iclass 31, count 0 2006.162.08:17:23.66#ibcon#read 5, iclass 31, count 0 2006.162.08:17:23.66#ibcon#about to read 6, iclass 31, count 0 2006.162.08:17:23.66#ibcon#read 6, iclass 31, count 0 2006.162.08:17:23.66#ibcon#end of sib2, iclass 31, count 0 2006.162.08:17:23.66#ibcon#*after write, iclass 31, count 0 2006.162.08:17:23.66#ibcon#*before return 0, iclass 31, count 0 2006.162.08:17:23.66#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:17:23.66#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:17:23.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.162.08:17:23.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.162.08:17:23.66$vc4f8/vblo=5,744.99 2006.162.08:17:23.66#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.162.08:17:23.66#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.162.08:17:23.66#ibcon#ireg 17 cls_cnt 0 2006.162.08:17:23.66#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:17:23.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:17:23.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:17:23.66#ibcon#enter wrdev, iclass 33, count 0 2006.162.08:17:23.66#ibcon#first serial, iclass 33, count 0 2006.162.08:17:23.66#ibcon#enter sib2, iclass 33, count 0 2006.162.08:17:23.66#ibcon#flushed, iclass 33, count 0 2006.162.08:17:23.66#ibcon#about to write, iclass 33, count 0 2006.162.08:17:23.66#ibcon#wrote, iclass 33, count 0 2006.162.08:17:23.66#ibcon#about to read 3, iclass 33, count 0 2006.162.08:17:23.68#ibcon#read 3, iclass 33, count 0 2006.162.08:17:23.68#ibcon#about to read 4, iclass 33, count 0 2006.162.08:17:23.68#ibcon#read 4, iclass 33, count 0 2006.162.08:17:23.68#ibcon#about to read 5, iclass 33, count 0 2006.162.08:17:23.68#ibcon#read 5, iclass 33, count 0 2006.162.08:17:23.68#ibcon#about to read 6, iclass 33, count 0 2006.162.08:17:23.68#ibcon#read 6, iclass 33, count 0 2006.162.08:17:23.68#ibcon#end of sib2, iclass 33, count 0 2006.162.08:17:23.68#ibcon#*mode == 0, iclass 33, count 0 2006.162.08:17:23.68#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.162.08:17:23.68#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.08:17:23.68#ibcon#*before write, iclass 33, count 0 2006.162.08:17:23.68#ibcon#enter sib2, iclass 33, count 0 2006.162.08:17:23.68#ibcon#flushed, iclass 33, count 0 2006.162.08:17:23.68#ibcon#about to write, iclass 33, count 0 2006.162.08:17:23.68#ibcon#wrote, iclass 33, count 0 2006.162.08:17:23.68#ibcon#about to read 3, iclass 33, count 0 2006.162.08:17:23.72#ibcon#read 3, iclass 33, count 0 2006.162.08:17:23.72#ibcon#about to read 4, iclass 33, count 0 2006.162.08:17:23.72#ibcon#read 4, iclass 33, count 0 2006.162.08:17:23.72#ibcon#about to read 5, iclass 33, count 0 2006.162.08:17:23.72#ibcon#read 5, iclass 33, count 0 2006.162.08:17:23.72#ibcon#about to read 6, iclass 33, count 0 2006.162.08:17:23.72#ibcon#read 6, iclass 33, count 0 2006.162.08:17:23.72#ibcon#end of sib2, iclass 33, count 0 2006.162.08:17:23.72#ibcon#*after write, iclass 33, count 0 2006.162.08:17:23.72#ibcon#*before return 0, iclass 33, count 0 2006.162.08:17:23.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:17:23.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:17:23.72#ibcon#about to clear, iclass 33 cls_cnt 0 2006.162.08:17:23.72#ibcon#cleared, iclass 33 cls_cnt 0 2006.162.08:17:23.72$vc4f8/vb=5,4 2006.162.08:17:23.72#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.162.08:17:23.72#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.162.08:17:23.72#ibcon#ireg 11 cls_cnt 2 2006.162.08:17:23.72#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.162.08:17:23.78#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.162.08:17:23.78#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.162.08:17:23.78#ibcon#enter wrdev, iclass 35, count 2 2006.162.08:17:23.78#ibcon#first serial, iclass 35, count 2 2006.162.08:17:23.78#ibcon#enter sib2, iclass 35, count 2 2006.162.08:17:23.78#ibcon#flushed, iclass 35, count 2 2006.162.08:17:23.78#ibcon#about to write, iclass 35, count 2 2006.162.08:17:23.78#ibcon#wrote, iclass 35, count 2 2006.162.08:17:23.78#ibcon#about to read 3, iclass 35, count 2 2006.162.08:17:23.80#ibcon#read 3, iclass 35, count 2 2006.162.08:17:23.80#ibcon#about to read 4, iclass 35, count 2 2006.162.08:17:23.80#ibcon#read 4, iclass 35, count 2 2006.162.08:17:23.80#ibcon#about to read 5, iclass 35, count 2 2006.162.08:17:23.80#ibcon#read 5, iclass 35, count 2 2006.162.08:17:23.80#ibcon#about to read 6, iclass 35, count 2 2006.162.08:17:23.80#ibcon#read 6, iclass 35, count 2 2006.162.08:17:23.80#ibcon#end of sib2, iclass 35, count 2 2006.162.08:17:23.80#ibcon#*mode == 0, iclass 35, count 2 2006.162.08:17:23.80#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.162.08:17:23.80#ibcon#[27=AT05-04\r\n] 2006.162.08:17:23.80#ibcon#*before write, iclass 35, count 2 2006.162.08:17:23.80#ibcon#enter sib2, iclass 35, count 2 2006.162.08:17:23.80#ibcon#flushed, iclass 35, count 2 2006.162.08:17:23.80#ibcon#about to write, iclass 35, count 2 2006.162.08:17:23.80#ibcon#wrote, iclass 35, count 2 2006.162.08:17:23.80#ibcon#about to read 3, iclass 35, count 2 2006.162.08:17:23.83#ibcon#read 3, iclass 35, count 2 2006.162.08:17:23.83#ibcon#about to read 4, iclass 35, count 2 2006.162.08:17:23.83#ibcon#read 4, iclass 35, count 2 2006.162.08:17:23.83#ibcon#about to read 5, iclass 35, count 2 2006.162.08:17:23.83#ibcon#read 5, iclass 35, count 2 2006.162.08:17:23.83#ibcon#about to read 6, iclass 35, count 2 2006.162.08:17:23.83#ibcon#read 6, iclass 35, count 2 2006.162.08:17:23.83#ibcon#end of sib2, iclass 35, count 2 2006.162.08:17:23.83#ibcon#*after write, iclass 35, count 2 2006.162.08:17:23.83#ibcon#*before return 0, iclass 35, count 2 2006.162.08:17:23.83#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.162.08:17:23.83#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.162.08:17:23.83#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.162.08:17:23.83#ibcon#ireg 7 cls_cnt 0 2006.162.08:17:23.83#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.162.08:17:23.95#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.162.08:17:23.95#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.162.08:17:23.95#ibcon#enter wrdev, iclass 35, count 0 2006.162.08:17:23.95#ibcon#first serial, iclass 35, count 0 2006.162.08:17:23.95#ibcon#enter sib2, iclass 35, count 0 2006.162.08:17:23.95#ibcon#flushed, iclass 35, count 0 2006.162.08:17:23.95#ibcon#about to write, iclass 35, count 0 2006.162.08:17:23.95#ibcon#wrote, iclass 35, count 0 2006.162.08:17:23.95#ibcon#about to read 3, iclass 35, count 0 2006.162.08:17:23.97#ibcon#read 3, iclass 35, count 0 2006.162.08:17:23.97#ibcon#about to read 4, iclass 35, count 0 2006.162.08:17:23.97#ibcon#read 4, iclass 35, count 0 2006.162.08:17:23.97#ibcon#about to read 5, iclass 35, count 0 2006.162.08:17:23.97#ibcon#read 5, iclass 35, count 0 2006.162.08:17:23.97#ibcon#about to read 6, iclass 35, count 0 2006.162.08:17:23.97#ibcon#read 6, iclass 35, count 0 2006.162.08:17:23.97#ibcon#end of sib2, iclass 35, count 0 2006.162.08:17:23.97#ibcon#*mode == 0, iclass 35, count 0 2006.162.08:17:23.97#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.162.08:17:23.97#ibcon#[27=USB\r\n] 2006.162.08:17:23.97#ibcon#*before write, iclass 35, count 0 2006.162.08:17:23.97#ibcon#enter sib2, iclass 35, count 0 2006.162.08:17:23.97#ibcon#flushed, iclass 35, count 0 2006.162.08:17:23.97#ibcon#about to write, iclass 35, count 0 2006.162.08:17:23.97#ibcon#wrote, iclass 35, count 0 2006.162.08:17:23.97#ibcon#about to read 3, iclass 35, count 0 2006.162.08:17:24.00#ibcon#read 3, iclass 35, count 0 2006.162.08:17:24.00#ibcon#about to read 4, iclass 35, count 0 2006.162.08:17:24.00#ibcon#read 4, iclass 35, count 0 2006.162.08:17:24.00#ibcon#about to read 5, iclass 35, count 0 2006.162.08:17:24.00#ibcon#read 5, iclass 35, count 0 2006.162.08:17:24.00#ibcon#about to read 6, iclass 35, count 0 2006.162.08:17:24.00#ibcon#read 6, iclass 35, count 0 2006.162.08:17:24.00#ibcon#end of sib2, iclass 35, count 0 2006.162.08:17:24.00#ibcon#*after write, iclass 35, count 0 2006.162.08:17:24.00#ibcon#*before return 0, iclass 35, count 0 2006.162.08:17:24.00#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.162.08:17:24.00#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.162.08:17:24.00#ibcon#about to clear, iclass 35 cls_cnt 0 2006.162.08:17:24.00#ibcon#cleared, iclass 35 cls_cnt 0 2006.162.08:17:24.00$vc4f8/vblo=6,752.99 2006.162.08:17:24.00#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.162.08:17:24.00#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.162.08:17:24.00#ibcon#ireg 17 cls_cnt 0 2006.162.08:17:24.00#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.162.08:17:24.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.162.08:17:24.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.162.08:17:24.00#ibcon#enter wrdev, iclass 37, count 0 2006.162.08:17:24.00#ibcon#first serial, iclass 37, count 0 2006.162.08:17:24.00#ibcon#enter sib2, iclass 37, count 0 2006.162.08:17:24.00#ibcon#flushed, iclass 37, count 0 2006.162.08:17:24.00#ibcon#about to write, iclass 37, count 0 2006.162.08:17:24.00#ibcon#wrote, iclass 37, count 0 2006.162.08:17:24.00#ibcon#about to read 3, iclass 37, count 0 2006.162.08:17:24.02#ibcon#read 3, iclass 37, count 0 2006.162.08:17:24.02#ibcon#about to read 4, iclass 37, count 0 2006.162.08:17:24.02#ibcon#read 4, iclass 37, count 0 2006.162.08:17:24.02#ibcon#about to read 5, iclass 37, count 0 2006.162.08:17:24.02#ibcon#read 5, iclass 37, count 0 2006.162.08:17:24.02#ibcon#about to read 6, iclass 37, count 0 2006.162.08:17:24.02#ibcon#read 6, iclass 37, count 0 2006.162.08:17:24.02#ibcon#end of sib2, iclass 37, count 0 2006.162.08:17:24.02#ibcon#*mode == 0, iclass 37, count 0 2006.162.08:17:24.02#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.162.08:17:24.02#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.08:17:24.02#ibcon#*before write, iclass 37, count 0 2006.162.08:17:24.02#ibcon#enter sib2, iclass 37, count 0 2006.162.08:17:24.02#ibcon#flushed, iclass 37, count 0 2006.162.08:17:24.02#ibcon#about to write, iclass 37, count 0 2006.162.08:17:24.02#ibcon#wrote, iclass 37, count 0 2006.162.08:17:24.02#ibcon#about to read 3, iclass 37, count 0 2006.162.08:17:24.06#ibcon#read 3, iclass 37, count 0 2006.162.08:17:24.06#ibcon#about to read 4, iclass 37, count 0 2006.162.08:17:24.06#ibcon#read 4, iclass 37, count 0 2006.162.08:17:24.06#ibcon#about to read 5, iclass 37, count 0 2006.162.08:17:24.06#ibcon#read 5, iclass 37, count 0 2006.162.08:17:24.06#ibcon#about to read 6, iclass 37, count 0 2006.162.08:17:24.06#ibcon#read 6, iclass 37, count 0 2006.162.08:17:24.06#ibcon#end of sib2, iclass 37, count 0 2006.162.08:17:24.06#ibcon#*after write, iclass 37, count 0 2006.162.08:17:24.06#ibcon#*before return 0, iclass 37, count 0 2006.162.08:17:24.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.162.08:17:24.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.162.08:17:24.06#ibcon#about to clear, iclass 37 cls_cnt 0 2006.162.08:17:24.06#ibcon#cleared, iclass 37 cls_cnt 0 2006.162.08:17:24.06$vc4f8/vb=6,4 2006.162.08:17:24.06#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.162.08:17:24.06#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.162.08:17:24.06#ibcon#ireg 11 cls_cnt 2 2006.162.08:17:24.06#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.162.08:17:24.12#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.162.08:17:24.12#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.162.08:17:24.13#ibcon#enter wrdev, iclass 39, count 2 2006.162.08:17:24.13#ibcon#first serial, iclass 39, count 2 2006.162.08:17:24.13#ibcon#enter sib2, iclass 39, count 2 2006.162.08:17:24.13#ibcon#flushed, iclass 39, count 2 2006.162.08:17:24.13#ibcon#about to write, iclass 39, count 2 2006.162.08:17:24.13#ibcon#wrote, iclass 39, count 2 2006.162.08:17:24.13#ibcon#about to read 3, iclass 39, count 2 2006.162.08:17:24.14#ibcon#read 3, iclass 39, count 2 2006.162.08:17:24.14#ibcon#about to read 4, iclass 39, count 2 2006.162.08:17:24.14#ibcon#read 4, iclass 39, count 2 2006.162.08:17:24.14#ibcon#about to read 5, iclass 39, count 2 2006.162.08:17:24.14#ibcon#read 5, iclass 39, count 2 2006.162.08:17:24.14#ibcon#about to read 6, iclass 39, count 2 2006.162.08:17:24.14#ibcon#read 6, iclass 39, count 2 2006.162.08:17:24.14#ibcon#end of sib2, iclass 39, count 2 2006.162.08:17:24.14#ibcon#*mode == 0, iclass 39, count 2 2006.162.08:17:24.14#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.162.08:17:24.14#ibcon#[27=AT06-04\r\n] 2006.162.08:17:24.14#ibcon#*before write, iclass 39, count 2 2006.162.08:17:24.14#ibcon#enter sib2, iclass 39, count 2 2006.162.08:17:24.14#ibcon#flushed, iclass 39, count 2 2006.162.08:17:24.14#ibcon#about to write, iclass 39, count 2 2006.162.08:17:24.14#ibcon#wrote, iclass 39, count 2 2006.162.08:17:24.14#ibcon#about to read 3, iclass 39, count 2 2006.162.08:17:24.17#ibcon#read 3, iclass 39, count 2 2006.162.08:17:24.17#ibcon#about to read 4, iclass 39, count 2 2006.162.08:17:24.17#ibcon#read 4, iclass 39, count 2 2006.162.08:17:24.17#ibcon#about to read 5, iclass 39, count 2 2006.162.08:17:24.17#ibcon#read 5, iclass 39, count 2 2006.162.08:17:24.17#ibcon#about to read 6, iclass 39, count 2 2006.162.08:17:24.17#ibcon#read 6, iclass 39, count 2 2006.162.08:17:24.17#ibcon#end of sib2, iclass 39, count 2 2006.162.08:17:24.17#ibcon#*after write, iclass 39, count 2 2006.162.08:17:24.17#ibcon#*before return 0, iclass 39, count 2 2006.162.08:17:24.17#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.162.08:17:24.17#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.162.08:17:24.17#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.162.08:17:24.17#ibcon#ireg 7 cls_cnt 0 2006.162.08:17:24.17#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.162.08:17:24.29#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.162.08:17:24.29#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.162.08:17:24.29#ibcon#enter wrdev, iclass 39, count 0 2006.162.08:17:24.29#ibcon#first serial, iclass 39, count 0 2006.162.08:17:24.29#ibcon#enter sib2, iclass 39, count 0 2006.162.08:17:24.29#ibcon#flushed, iclass 39, count 0 2006.162.08:17:24.29#ibcon#about to write, iclass 39, count 0 2006.162.08:17:24.29#ibcon#wrote, iclass 39, count 0 2006.162.08:17:24.29#ibcon#about to read 3, iclass 39, count 0 2006.162.08:17:24.31#ibcon#read 3, iclass 39, count 0 2006.162.08:17:24.31#ibcon#about to read 4, iclass 39, count 0 2006.162.08:17:24.31#ibcon#read 4, iclass 39, count 0 2006.162.08:17:24.31#ibcon#about to read 5, iclass 39, count 0 2006.162.08:17:24.31#ibcon#read 5, iclass 39, count 0 2006.162.08:17:24.31#ibcon#about to read 6, iclass 39, count 0 2006.162.08:17:24.31#ibcon#read 6, iclass 39, count 0 2006.162.08:17:24.31#ibcon#end of sib2, iclass 39, count 0 2006.162.08:17:24.31#ibcon#*mode == 0, iclass 39, count 0 2006.162.08:17:24.31#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.162.08:17:24.31#ibcon#[27=USB\r\n] 2006.162.08:17:24.31#ibcon#*before write, iclass 39, count 0 2006.162.08:17:24.31#ibcon#enter sib2, iclass 39, count 0 2006.162.08:17:24.31#ibcon#flushed, iclass 39, count 0 2006.162.08:17:24.31#ibcon#about to write, iclass 39, count 0 2006.162.08:17:24.31#ibcon#wrote, iclass 39, count 0 2006.162.08:17:24.31#ibcon#about to read 3, iclass 39, count 0 2006.162.08:17:24.34#ibcon#read 3, iclass 39, count 0 2006.162.08:17:24.34#ibcon#about to read 4, iclass 39, count 0 2006.162.08:17:24.34#ibcon#read 4, iclass 39, count 0 2006.162.08:17:24.34#ibcon#about to read 5, iclass 39, count 0 2006.162.08:17:24.34#ibcon#read 5, iclass 39, count 0 2006.162.08:17:24.34#ibcon#about to read 6, iclass 39, count 0 2006.162.08:17:24.34#ibcon#read 6, iclass 39, count 0 2006.162.08:17:24.34#ibcon#end of sib2, iclass 39, count 0 2006.162.08:17:24.34#ibcon#*after write, iclass 39, count 0 2006.162.08:17:24.34#ibcon#*before return 0, iclass 39, count 0 2006.162.08:17:24.34#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.162.08:17:24.34#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.162.08:17:24.34#ibcon#about to clear, iclass 39 cls_cnt 0 2006.162.08:17:24.34#ibcon#cleared, iclass 39 cls_cnt 0 2006.162.08:17:24.34$vc4f8/vabw=wide 2006.162.08:17:24.34#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.162.08:17:24.34#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.162.08:17:24.34#ibcon#ireg 8 cls_cnt 0 2006.162.08:17:24.34#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.162.08:17:24.34#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.162.08:17:24.34#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.162.08:17:24.34#ibcon#enter wrdev, iclass 3, count 0 2006.162.08:17:24.34#ibcon#first serial, iclass 3, count 0 2006.162.08:17:24.34#ibcon#enter sib2, iclass 3, count 0 2006.162.08:17:24.34#ibcon#flushed, iclass 3, count 0 2006.162.08:17:24.34#ibcon#about to write, iclass 3, count 0 2006.162.08:17:24.34#ibcon#wrote, iclass 3, count 0 2006.162.08:17:24.34#ibcon#about to read 3, iclass 3, count 0 2006.162.08:17:24.36#ibcon#read 3, iclass 3, count 0 2006.162.08:17:24.36#ibcon#about to read 4, iclass 3, count 0 2006.162.08:17:24.36#ibcon#read 4, iclass 3, count 0 2006.162.08:17:24.36#ibcon#about to read 5, iclass 3, count 0 2006.162.08:17:24.36#ibcon#read 5, iclass 3, count 0 2006.162.08:17:24.36#ibcon#about to read 6, iclass 3, count 0 2006.162.08:17:24.36#ibcon#read 6, iclass 3, count 0 2006.162.08:17:24.36#ibcon#end of sib2, iclass 3, count 0 2006.162.08:17:24.36#ibcon#*mode == 0, iclass 3, count 0 2006.162.08:17:24.36#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.162.08:17:24.36#ibcon#[25=BW32\r\n] 2006.162.08:17:24.36#ibcon#*before write, iclass 3, count 0 2006.162.08:17:24.36#ibcon#enter sib2, iclass 3, count 0 2006.162.08:17:24.36#ibcon#flushed, iclass 3, count 0 2006.162.08:17:24.36#ibcon#about to write, iclass 3, count 0 2006.162.08:17:24.36#ibcon#wrote, iclass 3, count 0 2006.162.08:17:24.36#ibcon#about to read 3, iclass 3, count 0 2006.162.08:17:24.39#ibcon#read 3, iclass 3, count 0 2006.162.08:17:24.39#ibcon#about to read 4, iclass 3, count 0 2006.162.08:17:24.39#ibcon#read 4, iclass 3, count 0 2006.162.08:17:24.39#ibcon#about to read 5, iclass 3, count 0 2006.162.08:17:24.39#ibcon#read 5, iclass 3, count 0 2006.162.08:17:24.39#ibcon#about to read 6, iclass 3, count 0 2006.162.08:17:24.39#ibcon#read 6, iclass 3, count 0 2006.162.08:17:24.39#ibcon#end of sib2, iclass 3, count 0 2006.162.08:17:24.39#ibcon#*after write, iclass 3, count 0 2006.162.08:17:24.39#ibcon#*before return 0, iclass 3, count 0 2006.162.08:17:24.39#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.162.08:17:24.39#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.162.08:17:24.39#ibcon#about to clear, iclass 3 cls_cnt 0 2006.162.08:17:24.39#ibcon#cleared, iclass 3 cls_cnt 0 2006.162.08:17:24.39$vc4f8/vbbw=wide 2006.162.08:17:24.39#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.162.08:17:24.39#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.162.08:17:24.39#ibcon#ireg 8 cls_cnt 0 2006.162.08:17:24.39#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:17:24.46#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:17:24.46#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:17:24.46#ibcon#enter wrdev, iclass 5, count 0 2006.162.08:17:24.46#ibcon#first serial, iclass 5, count 0 2006.162.08:17:24.46#ibcon#enter sib2, iclass 5, count 0 2006.162.08:17:24.46#ibcon#flushed, iclass 5, count 0 2006.162.08:17:24.46#ibcon#about to write, iclass 5, count 0 2006.162.08:17:24.46#ibcon#wrote, iclass 5, count 0 2006.162.08:17:24.46#ibcon#about to read 3, iclass 5, count 0 2006.162.08:17:24.48#ibcon#read 3, iclass 5, count 0 2006.162.08:17:24.48#ibcon#about to read 4, iclass 5, count 0 2006.162.08:17:24.48#ibcon#read 4, iclass 5, count 0 2006.162.08:17:24.48#ibcon#about to read 5, iclass 5, count 0 2006.162.08:17:24.48#ibcon#read 5, iclass 5, count 0 2006.162.08:17:24.48#ibcon#about to read 6, iclass 5, count 0 2006.162.08:17:24.48#ibcon#read 6, iclass 5, count 0 2006.162.08:17:24.48#ibcon#end of sib2, iclass 5, count 0 2006.162.08:17:24.48#ibcon#*mode == 0, iclass 5, count 0 2006.162.08:17:24.48#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.162.08:17:24.48#ibcon#[27=BW32\r\n] 2006.162.08:17:24.48#ibcon#*before write, iclass 5, count 0 2006.162.08:17:24.48#ibcon#enter sib2, iclass 5, count 0 2006.162.08:17:24.48#ibcon#flushed, iclass 5, count 0 2006.162.08:17:24.48#ibcon#about to write, iclass 5, count 0 2006.162.08:17:24.48#ibcon#wrote, iclass 5, count 0 2006.162.08:17:24.48#ibcon#about to read 3, iclass 5, count 0 2006.162.08:17:24.51#ibcon#read 3, iclass 5, count 0 2006.162.08:17:24.51#ibcon#about to read 4, iclass 5, count 0 2006.162.08:17:24.51#ibcon#read 4, iclass 5, count 0 2006.162.08:17:24.51#ibcon#about to read 5, iclass 5, count 0 2006.162.08:17:24.51#ibcon#read 5, iclass 5, count 0 2006.162.08:17:24.51#ibcon#about to read 6, iclass 5, count 0 2006.162.08:17:24.51#ibcon#read 6, iclass 5, count 0 2006.162.08:17:24.51#ibcon#end of sib2, iclass 5, count 0 2006.162.08:17:24.51#ibcon#*after write, iclass 5, count 0 2006.162.08:17:24.51#ibcon#*before return 0, iclass 5, count 0 2006.162.08:17:24.51#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:17:24.51#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:17:24.51#ibcon#about to clear, iclass 5 cls_cnt 0 2006.162.08:17:24.51#ibcon#cleared, iclass 5 cls_cnt 0 2006.162.08:17:24.51$4f8m12a/ifd4f 2006.162.08:17:24.51$ifd4f/lo= 2006.162.08:17:24.51$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.08:17:24.51$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.08:17:24.51$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.08:17:24.51$ifd4f/patch= 2006.162.08:17:24.51$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.08:17:24.51$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.08:17:24.51$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.08:17:24.51$4f8m12a/"form=m,16.000,1:2 2006.162.08:17:24.51$4f8m12a/"tpicd 2006.162.08:17:24.51$4f8m12a/echo=off 2006.162.08:17:24.51$4f8m12a/xlog=off 2006.162.08:17:24.51:!2006.162.08:18:50 2006.162.08:17:27.14#trakl#Source acquired 2006.162.08:17:29.14#flagr#flagr/antenna,acquired 2006.162.08:18:50.00:preob 2006.162.08:18:51.14/onsource/TRACKING 2006.162.08:18:51.14:!2006.162.08:19:00 2006.162.08:19:00.00:data_valid=on 2006.162.08:19:00.00:midob 2006.162.08:19:00.14/onsource/TRACKING 2006.162.08:19:00.14/wx/17.87,1007.0,100 2006.162.08:19:00.33/cable/+6.5355E-03 2006.162.08:19:01.42/va/01,08,usb,yes,35,37 2006.162.08:19:01.42/va/02,07,usb,yes,35,37 2006.162.08:19:01.42/va/03,06,usb,yes,37,37 2006.162.08:19:01.42/va/04,07,usb,yes,36,39 2006.162.08:19:01.42/va/05,07,usb,yes,39,41 2006.162.08:19:01.42/va/06,06,usb,yes,38,38 2006.162.08:19:01.42/va/07,06,usb,yes,38,38 2006.162.08:19:01.42/va/08,07,usb,yes,37,36 2006.162.08:19:01.65/valo/01,532.99,yes,locked 2006.162.08:19:01.65/valo/02,572.99,yes,locked 2006.162.08:19:01.65/valo/03,672.99,yes,locked 2006.162.08:19:01.65/valo/04,832.99,yes,locked 2006.162.08:19:01.65/valo/05,652.99,yes,locked 2006.162.08:19:01.65/valo/06,772.99,yes,locked 2006.162.08:19:01.65/valo/07,832.99,yes,locked 2006.162.08:19:01.65/valo/08,852.99,yes,locked 2006.162.08:19:02.74/vb/01,04,usb,yes,30,28 2006.162.08:19:02.74/vb/02,04,usb,yes,32,33 2006.162.08:19:02.74/vb/03,04,usb,yes,28,32 2006.162.08:19:02.74/vb/04,04,usb,yes,29,29 2006.162.08:19:02.74/vb/05,04,usb,yes,27,31 2006.162.08:19:02.74/vb/06,04,usb,yes,28,31 2006.162.08:19:02.74/vb/07,04,usb,yes,30,30 2006.162.08:19:02.74/vb/08,04,usb,yes,28,31 2006.162.08:19:02.97/vblo/01,632.99,yes,locked 2006.162.08:19:02.97/vblo/02,640.99,yes,locked 2006.162.08:19:02.97/vblo/03,656.99,yes,locked 2006.162.08:19:02.97/vblo/04,712.99,yes,locked 2006.162.08:19:02.97/vblo/05,744.99,yes,locked 2006.162.08:19:02.97/vblo/06,752.99,yes,locked 2006.162.08:19:02.97/vblo/07,734.99,yes,locked 2006.162.08:19:02.97/vblo/08,744.99,yes,locked 2006.162.08:19:03.12/vabw/8 2006.162.08:19:03.27/vbbw/8 2006.162.08:19:03.38/xfe/off,on,15.0 2006.162.08:19:03.75/ifatt/23,28,28,28 2006.162.08:19:04.08/fmout-gps/S +4.50E-07 2006.162.08:19:04.16:!2006.162.08:20:00 2006.162.08:20:00.00:data_valid=off 2006.162.08:20:00.00:postob 2006.162.08:20:00.24/cable/+6.5364E-03 2006.162.08:20:00.24/wx/17.88,1006.9,100 2006.162.08:20:01.08/fmout-gps/S +4.51E-07 2006.162.08:20:01.08:scan_name=162-0822,k06162,60 2006.162.08:20:01.09:source=1300+580,130252.47,574837.6,2000.0,cw 2006.162.08:20:01.14#flagr#flagr/antenna,new-source 2006.162.08:20:02.14:checkk5 2006.162.08:20:02.55/chk_autoobs//k5ts1/ autoobs is running! 2006.162.08:20:03.18/chk_autoobs//k5ts2/ autoobs is running! 2006.162.08:20:03.58/chk_autoobs//k5ts3/ autoobs is running! 2006.162.08:20:04.07/chk_autoobs//k5ts4/ autoobs is running! 2006.162.08:20:04.49/chk_obsdata//k5ts1/T1620819??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.162.08:20:04.91/chk_obsdata//k5ts2/T1620819??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.162.08:20:05.30/chk_obsdata//k5ts3/T1620819??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.162.08:20:05.74/chk_obsdata//k5ts4/T1620819??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.162.08:20:06.46/k5log//k5ts1_log_newline 2006.162.08:20:07.40/k5log//k5ts2_log_newline 2006.162.08:20:08.20/k5log//k5ts3_log_newline 2006.162.08:20:09.12/k5log//k5ts4_log_newline 2006.162.08:20:09.14/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.08:20:09.14:4f8m12a=3 2006.162.08:20:09.14$4f8m12a/echo=on 2006.162.08:20:09.14$4f8m12a/pcalon 2006.162.08:20:09.14$pcalon/"no phase cal control is implemented here 2006.162.08:20:09.14$4f8m12a/"tpicd=stop 2006.162.08:20:09.14$4f8m12a/vc4f8 2006.162.08:20:09.14$vc4f8/valo=1,532.99 2006.162.08:20:09.14#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.162.08:20:09.14#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.162.08:20:09.14#ibcon#ireg 17 cls_cnt 0 2006.162.08:20:09.14#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:20:09.14#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:20:09.14#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:20:09.14#ibcon#enter wrdev, iclass 4, count 0 2006.162.08:20:09.14#ibcon#first serial, iclass 4, count 0 2006.162.08:20:09.14#ibcon#enter sib2, iclass 4, count 0 2006.162.08:20:09.14#ibcon#flushed, iclass 4, count 0 2006.162.08:20:09.14#ibcon#about to write, iclass 4, count 0 2006.162.08:20:09.14#ibcon#wrote, iclass 4, count 0 2006.162.08:20:09.14#ibcon#about to read 3, iclass 4, count 0 2006.162.08:20:09.16#ibcon#read 3, iclass 4, count 0 2006.162.08:20:09.16#ibcon#about to read 4, iclass 4, count 0 2006.162.08:20:09.16#ibcon#read 4, iclass 4, count 0 2006.162.08:20:09.16#ibcon#about to read 5, iclass 4, count 0 2006.162.08:20:09.16#ibcon#read 5, iclass 4, count 0 2006.162.08:20:09.16#ibcon#about to read 6, iclass 4, count 0 2006.162.08:20:09.16#ibcon#read 6, iclass 4, count 0 2006.162.08:20:09.16#ibcon#end of sib2, iclass 4, count 0 2006.162.08:20:09.16#ibcon#*mode == 0, iclass 4, count 0 2006.162.08:20:09.16#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.162.08:20:09.16#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.08:20:09.16#ibcon#*before write, iclass 4, count 0 2006.162.08:20:09.16#ibcon#enter sib2, iclass 4, count 0 2006.162.08:20:09.16#ibcon#flushed, iclass 4, count 0 2006.162.08:20:09.16#ibcon#about to write, iclass 4, count 0 2006.162.08:20:09.16#ibcon#wrote, iclass 4, count 0 2006.162.08:20:09.16#ibcon#about to read 3, iclass 4, count 0 2006.162.08:20:09.21#ibcon#read 3, iclass 4, count 0 2006.162.08:20:09.21#ibcon#about to read 4, iclass 4, count 0 2006.162.08:20:09.21#ibcon#read 4, iclass 4, count 0 2006.162.08:20:09.21#ibcon#about to read 5, iclass 4, count 0 2006.162.08:20:09.21#ibcon#read 5, iclass 4, count 0 2006.162.08:20:09.21#ibcon#about to read 6, iclass 4, count 0 2006.162.08:20:09.21#ibcon#read 6, iclass 4, count 0 2006.162.08:20:09.21#ibcon#end of sib2, iclass 4, count 0 2006.162.08:20:09.21#ibcon#*after write, iclass 4, count 0 2006.162.08:20:09.21#ibcon#*before return 0, iclass 4, count 0 2006.162.08:20:09.21#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:20:09.21#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:20:09.21#ibcon#about to clear, iclass 4 cls_cnt 0 2006.162.08:20:09.21#ibcon#cleared, iclass 4 cls_cnt 0 2006.162.08:20:09.21$vc4f8/va=1,8 2006.162.08:20:09.21#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.162.08:20:09.21#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.162.08:20:09.21#ibcon#ireg 11 cls_cnt 2 2006.162.08:20:09.21#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.162.08:20:09.21#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.162.08:20:09.21#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.162.08:20:09.21#ibcon#enter wrdev, iclass 6, count 2 2006.162.08:20:09.21#ibcon#first serial, iclass 6, count 2 2006.162.08:20:09.21#ibcon#enter sib2, iclass 6, count 2 2006.162.08:20:09.21#ibcon#flushed, iclass 6, count 2 2006.162.08:20:09.21#ibcon#about to write, iclass 6, count 2 2006.162.08:20:09.21#ibcon#wrote, iclass 6, count 2 2006.162.08:20:09.21#ibcon#about to read 3, iclass 6, count 2 2006.162.08:20:09.23#ibcon#read 3, iclass 6, count 2 2006.162.08:20:09.23#ibcon#about to read 4, iclass 6, count 2 2006.162.08:20:09.23#ibcon#read 4, iclass 6, count 2 2006.162.08:20:09.23#ibcon#about to read 5, iclass 6, count 2 2006.162.08:20:09.23#ibcon#read 5, iclass 6, count 2 2006.162.08:20:09.23#ibcon#about to read 6, iclass 6, count 2 2006.162.08:20:09.23#ibcon#read 6, iclass 6, count 2 2006.162.08:20:09.23#ibcon#end of sib2, iclass 6, count 2 2006.162.08:20:09.23#ibcon#*mode == 0, iclass 6, count 2 2006.162.08:20:09.23#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.162.08:20:09.23#ibcon#[25=AT01-08\r\n] 2006.162.08:20:09.23#ibcon#*before write, iclass 6, count 2 2006.162.08:20:09.23#ibcon#enter sib2, iclass 6, count 2 2006.162.08:20:09.23#ibcon#flushed, iclass 6, count 2 2006.162.08:20:09.23#ibcon#about to write, iclass 6, count 2 2006.162.08:20:09.23#ibcon#wrote, iclass 6, count 2 2006.162.08:20:09.23#ibcon#about to read 3, iclass 6, count 2 2006.162.08:20:09.26#ibcon#read 3, iclass 6, count 2 2006.162.08:20:09.26#ibcon#about to read 4, iclass 6, count 2 2006.162.08:20:09.26#ibcon#read 4, iclass 6, count 2 2006.162.08:20:09.26#ibcon#about to read 5, iclass 6, count 2 2006.162.08:20:09.26#ibcon#read 5, iclass 6, count 2 2006.162.08:20:09.26#ibcon#about to read 6, iclass 6, count 2 2006.162.08:20:09.26#ibcon#read 6, iclass 6, count 2 2006.162.08:20:09.26#ibcon#end of sib2, iclass 6, count 2 2006.162.08:20:09.26#ibcon#*after write, iclass 6, count 2 2006.162.08:20:09.26#ibcon#*before return 0, iclass 6, count 2 2006.162.08:20:09.26#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.162.08:20:09.26#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.162.08:20:09.26#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.162.08:20:09.26#ibcon#ireg 7 cls_cnt 0 2006.162.08:20:09.26#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.162.08:20:09.38#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.162.08:20:09.38#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.162.08:20:09.38#ibcon#enter wrdev, iclass 6, count 0 2006.162.08:20:09.38#ibcon#first serial, iclass 6, count 0 2006.162.08:20:09.38#ibcon#enter sib2, iclass 6, count 0 2006.162.08:20:09.38#ibcon#flushed, iclass 6, count 0 2006.162.08:20:09.38#ibcon#about to write, iclass 6, count 0 2006.162.08:20:09.38#ibcon#wrote, iclass 6, count 0 2006.162.08:20:09.38#ibcon#about to read 3, iclass 6, count 0 2006.162.08:20:09.40#ibcon#read 3, iclass 6, count 0 2006.162.08:20:09.40#ibcon#about to read 4, iclass 6, count 0 2006.162.08:20:09.40#ibcon#read 4, iclass 6, count 0 2006.162.08:20:09.40#ibcon#about to read 5, iclass 6, count 0 2006.162.08:20:09.40#ibcon#read 5, iclass 6, count 0 2006.162.08:20:09.40#ibcon#about to read 6, iclass 6, count 0 2006.162.08:20:09.40#ibcon#read 6, iclass 6, count 0 2006.162.08:20:09.40#ibcon#end of sib2, iclass 6, count 0 2006.162.08:20:09.40#ibcon#*mode == 0, iclass 6, count 0 2006.162.08:20:09.40#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.162.08:20:09.40#ibcon#[25=USB\r\n] 2006.162.08:20:09.40#ibcon#*before write, iclass 6, count 0 2006.162.08:20:09.40#ibcon#enter sib2, iclass 6, count 0 2006.162.08:20:09.40#ibcon#flushed, iclass 6, count 0 2006.162.08:20:09.40#ibcon#about to write, iclass 6, count 0 2006.162.08:20:09.40#ibcon#wrote, iclass 6, count 0 2006.162.08:20:09.40#ibcon#about to read 3, iclass 6, count 0 2006.162.08:20:09.43#ibcon#read 3, iclass 6, count 0 2006.162.08:20:09.43#ibcon#about to read 4, iclass 6, count 0 2006.162.08:20:09.43#ibcon#read 4, iclass 6, count 0 2006.162.08:20:09.43#ibcon#about to read 5, iclass 6, count 0 2006.162.08:20:09.43#ibcon#read 5, iclass 6, count 0 2006.162.08:20:09.43#ibcon#about to read 6, iclass 6, count 0 2006.162.08:20:09.43#ibcon#read 6, iclass 6, count 0 2006.162.08:20:09.43#ibcon#end of sib2, iclass 6, count 0 2006.162.08:20:09.43#ibcon#*after write, iclass 6, count 0 2006.162.08:20:09.43#ibcon#*before return 0, iclass 6, count 0 2006.162.08:20:09.43#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.162.08:20:09.43#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.162.08:20:09.43#ibcon#about to clear, iclass 6 cls_cnt 0 2006.162.08:20:09.43#ibcon#cleared, iclass 6 cls_cnt 0 2006.162.08:20:09.43$vc4f8/valo=2,572.99 2006.162.08:20:09.43#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.162.08:20:09.43#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.162.08:20:09.43#ibcon#ireg 17 cls_cnt 0 2006.162.08:20:09.43#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:20:09.43#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:20:09.43#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:20:09.43#ibcon#enter wrdev, iclass 10, count 0 2006.162.08:20:09.43#ibcon#first serial, iclass 10, count 0 2006.162.08:20:09.43#ibcon#enter sib2, iclass 10, count 0 2006.162.08:20:09.43#ibcon#flushed, iclass 10, count 0 2006.162.08:20:09.43#ibcon#about to write, iclass 10, count 0 2006.162.08:20:09.43#ibcon#wrote, iclass 10, count 0 2006.162.08:20:09.43#ibcon#about to read 3, iclass 10, count 0 2006.162.08:20:09.45#ibcon#read 3, iclass 10, count 0 2006.162.08:20:09.45#ibcon#about to read 4, iclass 10, count 0 2006.162.08:20:09.45#ibcon#read 4, iclass 10, count 0 2006.162.08:20:09.45#ibcon#about to read 5, iclass 10, count 0 2006.162.08:20:09.45#ibcon#read 5, iclass 10, count 0 2006.162.08:20:09.45#ibcon#about to read 6, iclass 10, count 0 2006.162.08:20:09.45#ibcon#read 6, iclass 10, count 0 2006.162.08:20:09.45#ibcon#end of sib2, iclass 10, count 0 2006.162.08:20:09.45#ibcon#*mode == 0, iclass 10, count 0 2006.162.08:20:09.45#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.162.08:20:09.45#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.08:20:09.45#ibcon#*before write, iclass 10, count 0 2006.162.08:20:09.45#ibcon#enter sib2, iclass 10, count 0 2006.162.08:20:09.45#ibcon#flushed, iclass 10, count 0 2006.162.08:20:09.45#ibcon#about to write, iclass 10, count 0 2006.162.08:20:09.45#ibcon#wrote, iclass 10, count 0 2006.162.08:20:09.45#ibcon#about to read 3, iclass 10, count 0 2006.162.08:20:09.49#ibcon#read 3, iclass 10, count 0 2006.162.08:20:09.49#ibcon#about to read 4, iclass 10, count 0 2006.162.08:20:09.49#ibcon#read 4, iclass 10, count 0 2006.162.08:20:09.49#ibcon#about to read 5, iclass 10, count 0 2006.162.08:20:09.49#ibcon#read 5, iclass 10, count 0 2006.162.08:20:09.49#ibcon#about to read 6, iclass 10, count 0 2006.162.08:20:09.49#ibcon#read 6, iclass 10, count 0 2006.162.08:20:09.49#ibcon#end of sib2, iclass 10, count 0 2006.162.08:20:09.49#ibcon#*after write, iclass 10, count 0 2006.162.08:20:09.49#ibcon#*before return 0, iclass 10, count 0 2006.162.08:20:09.49#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:20:09.49#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:20:09.49#ibcon#about to clear, iclass 10 cls_cnt 0 2006.162.08:20:09.49#ibcon#cleared, iclass 10 cls_cnt 0 2006.162.08:20:09.49$vc4f8/va=2,7 2006.162.08:20:09.49#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.162.08:20:09.49#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.162.08:20:09.49#ibcon#ireg 11 cls_cnt 2 2006.162.08:20:09.49#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:20:09.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:20:09.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:20:09.55#ibcon#enter wrdev, iclass 12, count 2 2006.162.08:20:09.55#ibcon#first serial, iclass 12, count 2 2006.162.08:20:09.55#ibcon#enter sib2, iclass 12, count 2 2006.162.08:20:09.55#ibcon#flushed, iclass 12, count 2 2006.162.08:20:09.55#ibcon#about to write, iclass 12, count 2 2006.162.08:20:09.55#ibcon#wrote, iclass 12, count 2 2006.162.08:20:09.55#ibcon#about to read 3, iclass 12, count 2 2006.162.08:20:09.58#ibcon#read 3, iclass 12, count 2 2006.162.08:20:09.58#ibcon#about to read 4, iclass 12, count 2 2006.162.08:20:09.58#ibcon#read 4, iclass 12, count 2 2006.162.08:20:09.58#ibcon#about to read 5, iclass 12, count 2 2006.162.08:20:09.58#ibcon#read 5, iclass 12, count 2 2006.162.08:20:09.58#ibcon#about to read 6, iclass 12, count 2 2006.162.08:20:09.58#ibcon#read 6, iclass 12, count 2 2006.162.08:20:09.58#ibcon#end of sib2, iclass 12, count 2 2006.162.08:20:09.58#ibcon#*mode == 0, iclass 12, count 2 2006.162.08:20:09.58#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.162.08:20:09.58#ibcon#[25=AT02-07\r\n] 2006.162.08:20:09.58#ibcon#*before write, iclass 12, count 2 2006.162.08:20:09.58#ibcon#enter sib2, iclass 12, count 2 2006.162.08:20:09.58#ibcon#flushed, iclass 12, count 2 2006.162.08:20:09.58#ibcon#about to write, iclass 12, count 2 2006.162.08:20:09.58#ibcon#wrote, iclass 12, count 2 2006.162.08:20:09.58#ibcon#about to read 3, iclass 12, count 2 2006.162.08:20:09.61#ibcon#read 3, iclass 12, count 2 2006.162.08:20:09.61#ibcon#about to read 4, iclass 12, count 2 2006.162.08:20:09.61#ibcon#read 4, iclass 12, count 2 2006.162.08:20:09.61#ibcon#about to read 5, iclass 12, count 2 2006.162.08:20:09.61#ibcon#read 5, iclass 12, count 2 2006.162.08:20:09.61#ibcon#about to read 6, iclass 12, count 2 2006.162.08:20:09.61#ibcon#read 6, iclass 12, count 2 2006.162.08:20:09.61#ibcon#end of sib2, iclass 12, count 2 2006.162.08:20:09.61#ibcon#*after write, iclass 12, count 2 2006.162.08:20:09.61#ibcon#*before return 0, iclass 12, count 2 2006.162.08:20:09.61#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:20:09.61#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:20:09.61#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.162.08:20:09.61#ibcon#ireg 7 cls_cnt 0 2006.162.08:20:09.61#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:20:09.73#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:20:09.73#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:20:09.73#ibcon#enter wrdev, iclass 12, count 0 2006.162.08:20:09.73#ibcon#first serial, iclass 12, count 0 2006.162.08:20:09.73#ibcon#enter sib2, iclass 12, count 0 2006.162.08:20:09.73#ibcon#flushed, iclass 12, count 0 2006.162.08:20:09.73#ibcon#about to write, iclass 12, count 0 2006.162.08:20:09.73#ibcon#wrote, iclass 12, count 0 2006.162.08:20:09.73#ibcon#about to read 3, iclass 12, count 0 2006.162.08:20:09.75#ibcon#read 3, iclass 12, count 0 2006.162.08:20:09.75#ibcon#about to read 4, iclass 12, count 0 2006.162.08:20:09.75#ibcon#read 4, iclass 12, count 0 2006.162.08:20:09.75#ibcon#about to read 5, iclass 12, count 0 2006.162.08:20:09.75#ibcon#read 5, iclass 12, count 0 2006.162.08:20:09.75#ibcon#about to read 6, iclass 12, count 0 2006.162.08:20:09.75#ibcon#read 6, iclass 12, count 0 2006.162.08:20:09.75#ibcon#end of sib2, iclass 12, count 0 2006.162.08:20:09.75#ibcon#*mode == 0, iclass 12, count 0 2006.162.08:20:09.75#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.162.08:20:09.75#ibcon#[25=USB\r\n] 2006.162.08:20:09.75#ibcon#*before write, iclass 12, count 0 2006.162.08:20:09.75#ibcon#enter sib2, iclass 12, count 0 2006.162.08:20:09.75#ibcon#flushed, iclass 12, count 0 2006.162.08:20:09.75#ibcon#about to write, iclass 12, count 0 2006.162.08:20:09.75#ibcon#wrote, iclass 12, count 0 2006.162.08:20:09.75#ibcon#about to read 3, iclass 12, count 0 2006.162.08:20:09.78#ibcon#read 3, iclass 12, count 0 2006.162.08:20:09.78#ibcon#about to read 4, iclass 12, count 0 2006.162.08:20:09.78#ibcon#read 4, iclass 12, count 0 2006.162.08:20:09.78#ibcon#about to read 5, iclass 12, count 0 2006.162.08:20:09.78#ibcon#read 5, iclass 12, count 0 2006.162.08:20:09.78#ibcon#about to read 6, iclass 12, count 0 2006.162.08:20:09.78#ibcon#read 6, iclass 12, count 0 2006.162.08:20:09.78#ibcon#end of sib2, iclass 12, count 0 2006.162.08:20:09.78#ibcon#*after write, iclass 12, count 0 2006.162.08:20:09.78#ibcon#*before return 0, iclass 12, count 0 2006.162.08:20:09.78#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:20:09.78#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:20:09.78#ibcon#about to clear, iclass 12 cls_cnt 0 2006.162.08:20:09.78#ibcon#cleared, iclass 12 cls_cnt 0 2006.162.08:20:09.78$vc4f8/valo=3,672.99 2006.162.08:20:09.78#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.162.08:20:09.78#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.162.08:20:09.78#ibcon#ireg 17 cls_cnt 0 2006.162.08:20:09.78#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:20:09.78#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:20:09.78#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:20:09.78#ibcon#enter wrdev, iclass 14, count 0 2006.162.08:20:09.78#ibcon#first serial, iclass 14, count 0 2006.162.08:20:09.78#ibcon#enter sib2, iclass 14, count 0 2006.162.08:20:09.78#ibcon#flushed, iclass 14, count 0 2006.162.08:20:09.78#ibcon#about to write, iclass 14, count 0 2006.162.08:20:09.78#ibcon#wrote, iclass 14, count 0 2006.162.08:20:09.78#ibcon#about to read 3, iclass 14, count 0 2006.162.08:20:09.81#ibcon#read 3, iclass 14, count 0 2006.162.08:20:09.81#ibcon#about to read 4, iclass 14, count 0 2006.162.08:20:09.81#ibcon#read 4, iclass 14, count 0 2006.162.08:20:09.81#ibcon#about to read 5, iclass 14, count 0 2006.162.08:20:09.81#ibcon#read 5, iclass 14, count 0 2006.162.08:20:09.81#ibcon#about to read 6, iclass 14, count 0 2006.162.08:20:09.81#ibcon#read 6, iclass 14, count 0 2006.162.08:20:09.81#ibcon#end of sib2, iclass 14, count 0 2006.162.08:20:09.81#ibcon#*mode == 0, iclass 14, count 0 2006.162.08:20:09.81#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.08:20:09.81#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.08:20:09.81#ibcon#*before write, iclass 14, count 0 2006.162.08:20:09.81#ibcon#enter sib2, iclass 14, count 0 2006.162.08:20:09.81#ibcon#flushed, iclass 14, count 0 2006.162.08:20:09.81#ibcon#about to write, iclass 14, count 0 2006.162.08:20:09.81#ibcon#wrote, iclass 14, count 0 2006.162.08:20:09.81#ibcon#about to read 3, iclass 14, count 0 2006.162.08:20:09.85#ibcon#read 3, iclass 14, count 0 2006.162.08:20:09.85#ibcon#about to read 4, iclass 14, count 0 2006.162.08:20:09.85#ibcon#read 4, iclass 14, count 0 2006.162.08:20:09.85#ibcon#about to read 5, iclass 14, count 0 2006.162.08:20:09.85#ibcon#read 5, iclass 14, count 0 2006.162.08:20:09.85#ibcon#about to read 6, iclass 14, count 0 2006.162.08:20:09.85#ibcon#read 6, iclass 14, count 0 2006.162.08:20:09.85#ibcon#end of sib2, iclass 14, count 0 2006.162.08:20:09.85#ibcon#*after write, iclass 14, count 0 2006.162.08:20:09.85#ibcon#*before return 0, iclass 14, count 0 2006.162.08:20:09.85#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:20:09.85#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:20:09.85#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.08:20:09.85#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.08:20:09.85$vc4f8/va=3,6 2006.162.08:20:09.85#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.162.08:20:09.85#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.162.08:20:09.85#ibcon#ireg 11 cls_cnt 2 2006.162.08:20:09.85#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:20:09.90#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:20:09.90#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:20:09.90#ibcon#enter wrdev, iclass 16, count 2 2006.162.08:20:09.90#ibcon#first serial, iclass 16, count 2 2006.162.08:20:09.90#ibcon#enter sib2, iclass 16, count 2 2006.162.08:20:09.90#ibcon#flushed, iclass 16, count 2 2006.162.08:20:09.90#ibcon#about to write, iclass 16, count 2 2006.162.08:20:09.90#ibcon#wrote, iclass 16, count 2 2006.162.08:20:09.90#ibcon#about to read 3, iclass 16, count 2 2006.162.08:20:09.93#ibcon#read 3, iclass 16, count 2 2006.162.08:20:09.93#ibcon#about to read 4, iclass 16, count 2 2006.162.08:20:09.93#ibcon#read 4, iclass 16, count 2 2006.162.08:20:09.93#ibcon#about to read 5, iclass 16, count 2 2006.162.08:20:09.93#ibcon#read 5, iclass 16, count 2 2006.162.08:20:09.93#ibcon#about to read 6, iclass 16, count 2 2006.162.08:20:09.93#ibcon#read 6, iclass 16, count 2 2006.162.08:20:09.93#ibcon#end of sib2, iclass 16, count 2 2006.162.08:20:09.93#ibcon#*mode == 0, iclass 16, count 2 2006.162.08:20:09.93#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.162.08:20:09.93#ibcon#[25=AT03-06\r\n] 2006.162.08:20:09.93#ibcon#*before write, iclass 16, count 2 2006.162.08:20:09.93#ibcon#enter sib2, iclass 16, count 2 2006.162.08:20:09.93#ibcon#flushed, iclass 16, count 2 2006.162.08:20:09.93#ibcon#about to write, iclass 16, count 2 2006.162.08:20:09.93#ibcon#wrote, iclass 16, count 2 2006.162.08:20:09.93#ibcon#about to read 3, iclass 16, count 2 2006.162.08:20:09.96#ibcon#read 3, iclass 16, count 2 2006.162.08:20:09.96#ibcon#about to read 4, iclass 16, count 2 2006.162.08:20:09.96#ibcon#read 4, iclass 16, count 2 2006.162.08:20:09.96#ibcon#about to read 5, iclass 16, count 2 2006.162.08:20:09.96#ibcon#read 5, iclass 16, count 2 2006.162.08:20:09.96#ibcon#about to read 6, iclass 16, count 2 2006.162.08:20:09.96#ibcon#read 6, iclass 16, count 2 2006.162.08:20:09.96#ibcon#end of sib2, iclass 16, count 2 2006.162.08:20:09.96#ibcon#*after write, iclass 16, count 2 2006.162.08:20:09.96#ibcon#*before return 0, iclass 16, count 2 2006.162.08:20:09.96#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:20:09.96#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:20:09.96#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.162.08:20:09.96#ibcon#ireg 7 cls_cnt 0 2006.162.08:20:09.96#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:20:10.08#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:20:10.08#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:20:10.08#ibcon#enter wrdev, iclass 16, count 0 2006.162.08:20:10.08#ibcon#first serial, iclass 16, count 0 2006.162.08:20:10.08#ibcon#enter sib2, iclass 16, count 0 2006.162.08:20:10.08#ibcon#flushed, iclass 16, count 0 2006.162.08:20:10.08#ibcon#about to write, iclass 16, count 0 2006.162.08:20:10.08#ibcon#wrote, iclass 16, count 0 2006.162.08:20:10.08#ibcon#about to read 3, iclass 16, count 0 2006.162.08:20:10.10#ibcon#read 3, iclass 16, count 0 2006.162.08:20:10.10#ibcon#about to read 4, iclass 16, count 0 2006.162.08:20:10.10#ibcon#read 4, iclass 16, count 0 2006.162.08:20:10.10#ibcon#about to read 5, iclass 16, count 0 2006.162.08:20:10.10#ibcon#read 5, iclass 16, count 0 2006.162.08:20:10.10#ibcon#about to read 6, iclass 16, count 0 2006.162.08:20:10.10#ibcon#read 6, iclass 16, count 0 2006.162.08:20:10.10#ibcon#end of sib2, iclass 16, count 0 2006.162.08:20:10.10#ibcon#*mode == 0, iclass 16, count 0 2006.162.08:20:10.10#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.162.08:20:10.10#ibcon#[25=USB\r\n] 2006.162.08:20:10.10#ibcon#*before write, iclass 16, count 0 2006.162.08:20:10.10#ibcon#enter sib2, iclass 16, count 0 2006.162.08:20:10.10#ibcon#flushed, iclass 16, count 0 2006.162.08:20:10.10#ibcon#about to write, iclass 16, count 0 2006.162.08:20:10.10#ibcon#wrote, iclass 16, count 0 2006.162.08:20:10.10#ibcon#about to read 3, iclass 16, count 0 2006.162.08:20:10.13#ibcon#read 3, iclass 16, count 0 2006.162.08:20:10.13#ibcon#about to read 4, iclass 16, count 0 2006.162.08:20:10.13#ibcon#read 4, iclass 16, count 0 2006.162.08:20:10.13#ibcon#about to read 5, iclass 16, count 0 2006.162.08:20:10.13#ibcon#read 5, iclass 16, count 0 2006.162.08:20:10.13#ibcon#about to read 6, iclass 16, count 0 2006.162.08:20:10.13#ibcon#read 6, iclass 16, count 0 2006.162.08:20:10.13#ibcon#end of sib2, iclass 16, count 0 2006.162.08:20:10.13#ibcon#*after write, iclass 16, count 0 2006.162.08:20:10.13#ibcon#*before return 0, iclass 16, count 0 2006.162.08:20:10.13#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:20:10.13#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:20:10.13#ibcon#about to clear, iclass 16 cls_cnt 0 2006.162.08:20:10.13#ibcon#cleared, iclass 16 cls_cnt 0 2006.162.08:20:10.13$vc4f8/valo=4,832.99 2006.162.08:20:10.13#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.162.08:20:10.13#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.162.08:20:10.13#ibcon#ireg 17 cls_cnt 0 2006.162.08:20:10.13#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:20:10.13#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:20:10.13#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:20:10.13#ibcon#enter wrdev, iclass 18, count 0 2006.162.08:20:10.13#ibcon#first serial, iclass 18, count 0 2006.162.08:20:10.13#ibcon#enter sib2, iclass 18, count 0 2006.162.08:20:10.13#ibcon#flushed, iclass 18, count 0 2006.162.08:20:10.13#ibcon#about to write, iclass 18, count 0 2006.162.08:20:10.13#ibcon#wrote, iclass 18, count 0 2006.162.08:20:10.13#ibcon#about to read 3, iclass 18, count 0 2006.162.08:20:10.15#ibcon#read 3, iclass 18, count 0 2006.162.08:20:10.15#ibcon#about to read 4, iclass 18, count 0 2006.162.08:20:10.15#ibcon#read 4, iclass 18, count 0 2006.162.08:20:10.15#ibcon#about to read 5, iclass 18, count 0 2006.162.08:20:10.15#ibcon#read 5, iclass 18, count 0 2006.162.08:20:10.15#ibcon#about to read 6, iclass 18, count 0 2006.162.08:20:10.15#ibcon#read 6, iclass 18, count 0 2006.162.08:20:10.15#ibcon#end of sib2, iclass 18, count 0 2006.162.08:20:10.15#ibcon#*mode == 0, iclass 18, count 0 2006.162.08:20:10.15#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.162.08:20:10.15#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.08:20:10.15#ibcon#*before write, iclass 18, count 0 2006.162.08:20:10.15#ibcon#enter sib2, iclass 18, count 0 2006.162.08:20:10.15#ibcon#flushed, iclass 18, count 0 2006.162.08:20:10.15#ibcon#about to write, iclass 18, count 0 2006.162.08:20:10.15#ibcon#wrote, iclass 18, count 0 2006.162.08:20:10.15#ibcon#about to read 3, iclass 18, count 0 2006.162.08:20:10.19#ibcon#read 3, iclass 18, count 0 2006.162.08:20:10.19#ibcon#about to read 4, iclass 18, count 0 2006.162.08:20:10.19#ibcon#read 4, iclass 18, count 0 2006.162.08:20:10.19#ibcon#about to read 5, iclass 18, count 0 2006.162.08:20:10.19#ibcon#read 5, iclass 18, count 0 2006.162.08:20:10.19#ibcon#about to read 6, iclass 18, count 0 2006.162.08:20:10.19#ibcon#read 6, iclass 18, count 0 2006.162.08:20:10.19#ibcon#end of sib2, iclass 18, count 0 2006.162.08:20:10.19#ibcon#*after write, iclass 18, count 0 2006.162.08:20:10.19#ibcon#*before return 0, iclass 18, count 0 2006.162.08:20:10.19#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:20:10.19#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:20:10.19#ibcon#about to clear, iclass 18 cls_cnt 0 2006.162.08:20:10.19#ibcon#cleared, iclass 18 cls_cnt 0 2006.162.08:20:10.19$vc4f8/va=4,7 2006.162.08:20:10.19#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.162.08:20:10.19#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.162.08:20:10.19#ibcon#ireg 11 cls_cnt 2 2006.162.08:20:10.19#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:20:10.25#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:20:10.25#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:20:10.25#ibcon#enter wrdev, iclass 20, count 2 2006.162.08:20:10.25#ibcon#first serial, iclass 20, count 2 2006.162.08:20:10.25#ibcon#enter sib2, iclass 20, count 2 2006.162.08:20:10.25#ibcon#flushed, iclass 20, count 2 2006.162.08:20:10.25#ibcon#about to write, iclass 20, count 2 2006.162.08:20:10.25#ibcon#wrote, iclass 20, count 2 2006.162.08:20:10.25#ibcon#about to read 3, iclass 20, count 2 2006.162.08:20:10.27#ibcon#read 3, iclass 20, count 2 2006.162.08:20:10.27#ibcon#about to read 4, iclass 20, count 2 2006.162.08:20:10.27#ibcon#read 4, iclass 20, count 2 2006.162.08:20:10.27#ibcon#about to read 5, iclass 20, count 2 2006.162.08:20:10.27#ibcon#read 5, iclass 20, count 2 2006.162.08:20:10.27#ibcon#about to read 6, iclass 20, count 2 2006.162.08:20:10.27#ibcon#read 6, iclass 20, count 2 2006.162.08:20:10.27#ibcon#end of sib2, iclass 20, count 2 2006.162.08:20:10.27#ibcon#*mode == 0, iclass 20, count 2 2006.162.08:20:10.27#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.162.08:20:10.27#ibcon#[25=AT04-07\r\n] 2006.162.08:20:10.27#ibcon#*before write, iclass 20, count 2 2006.162.08:20:10.27#ibcon#enter sib2, iclass 20, count 2 2006.162.08:20:10.27#ibcon#flushed, iclass 20, count 2 2006.162.08:20:10.27#ibcon#about to write, iclass 20, count 2 2006.162.08:20:10.27#ibcon#wrote, iclass 20, count 2 2006.162.08:20:10.27#ibcon#about to read 3, iclass 20, count 2 2006.162.08:20:10.30#ibcon#read 3, iclass 20, count 2 2006.162.08:20:10.30#ibcon#about to read 4, iclass 20, count 2 2006.162.08:20:10.30#ibcon#read 4, iclass 20, count 2 2006.162.08:20:10.30#ibcon#about to read 5, iclass 20, count 2 2006.162.08:20:10.30#ibcon#read 5, iclass 20, count 2 2006.162.08:20:10.30#ibcon#about to read 6, iclass 20, count 2 2006.162.08:20:10.30#ibcon#read 6, iclass 20, count 2 2006.162.08:20:10.30#ibcon#end of sib2, iclass 20, count 2 2006.162.08:20:10.30#ibcon#*after write, iclass 20, count 2 2006.162.08:20:10.30#ibcon#*before return 0, iclass 20, count 2 2006.162.08:20:10.30#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:20:10.30#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:20:10.30#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.162.08:20:10.30#ibcon#ireg 7 cls_cnt 0 2006.162.08:20:10.30#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:20:10.42#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:20:10.42#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:20:10.42#ibcon#enter wrdev, iclass 20, count 0 2006.162.08:20:10.42#ibcon#first serial, iclass 20, count 0 2006.162.08:20:10.42#ibcon#enter sib2, iclass 20, count 0 2006.162.08:20:10.42#ibcon#flushed, iclass 20, count 0 2006.162.08:20:10.42#ibcon#about to write, iclass 20, count 0 2006.162.08:20:10.42#ibcon#wrote, iclass 20, count 0 2006.162.08:20:10.42#ibcon#about to read 3, iclass 20, count 0 2006.162.08:20:10.44#ibcon#read 3, iclass 20, count 0 2006.162.08:20:10.44#ibcon#about to read 4, iclass 20, count 0 2006.162.08:20:10.44#ibcon#read 4, iclass 20, count 0 2006.162.08:20:10.44#ibcon#about to read 5, iclass 20, count 0 2006.162.08:20:10.44#ibcon#read 5, iclass 20, count 0 2006.162.08:20:10.44#ibcon#about to read 6, iclass 20, count 0 2006.162.08:20:10.44#ibcon#read 6, iclass 20, count 0 2006.162.08:20:10.44#ibcon#end of sib2, iclass 20, count 0 2006.162.08:20:10.44#ibcon#*mode == 0, iclass 20, count 0 2006.162.08:20:10.44#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.08:20:10.44#ibcon#[25=USB\r\n] 2006.162.08:20:10.44#ibcon#*before write, iclass 20, count 0 2006.162.08:20:10.44#ibcon#enter sib2, iclass 20, count 0 2006.162.08:20:10.44#ibcon#flushed, iclass 20, count 0 2006.162.08:20:10.44#ibcon#about to write, iclass 20, count 0 2006.162.08:20:10.44#ibcon#wrote, iclass 20, count 0 2006.162.08:20:10.44#ibcon#about to read 3, iclass 20, count 0 2006.162.08:20:10.47#ibcon#read 3, iclass 20, count 0 2006.162.08:20:10.47#ibcon#about to read 4, iclass 20, count 0 2006.162.08:20:10.47#ibcon#read 4, iclass 20, count 0 2006.162.08:20:10.47#ibcon#about to read 5, iclass 20, count 0 2006.162.08:20:10.47#ibcon#read 5, iclass 20, count 0 2006.162.08:20:10.47#ibcon#about to read 6, iclass 20, count 0 2006.162.08:20:10.47#ibcon#read 6, iclass 20, count 0 2006.162.08:20:10.47#ibcon#end of sib2, iclass 20, count 0 2006.162.08:20:10.47#ibcon#*after write, iclass 20, count 0 2006.162.08:20:10.47#ibcon#*before return 0, iclass 20, count 0 2006.162.08:20:10.47#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:20:10.47#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:20:10.47#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.08:20:10.47#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.08:20:10.47$vc4f8/valo=5,652.99 2006.162.08:20:10.47#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.162.08:20:10.47#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.162.08:20:10.47#ibcon#ireg 17 cls_cnt 0 2006.162.08:20:10.47#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:20:10.47#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:20:10.47#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:20:10.47#ibcon#enter wrdev, iclass 22, count 0 2006.162.08:20:10.47#ibcon#first serial, iclass 22, count 0 2006.162.08:20:10.47#ibcon#enter sib2, iclass 22, count 0 2006.162.08:20:10.47#ibcon#flushed, iclass 22, count 0 2006.162.08:20:10.47#ibcon#about to write, iclass 22, count 0 2006.162.08:20:10.47#ibcon#wrote, iclass 22, count 0 2006.162.08:20:10.47#ibcon#about to read 3, iclass 22, count 0 2006.162.08:20:10.49#ibcon#read 3, iclass 22, count 0 2006.162.08:20:10.49#ibcon#about to read 4, iclass 22, count 0 2006.162.08:20:10.49#ibcon#read 4, iclass 22, count 0 2006.162.08:20:10.49#ibcon#about to read 5, iclass 22, count 0 2006.162.08:20:10.49#ibcon#read 5, iclass 22, count 0 2006.162.08:20:10.49#ibcon#about to read 6, iclass 22, count 0 2006.162.08:20:10.49#ibcon#read 6, iclass 22, count 0 2006.162.08:20:10.49#ibcon#end of sib2, iclass 22, count 0 2006.162.08:20:10.49#ibcon#*mode == 0, iclass 22, count 0 2006.162.08:20:10.49#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.08:20:10.49#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.08:20:10.49#ibcon#*before write, iclass 22, count 0 2006.162.08:20:10.49#ibcon#enter sib2, iclass 22, count 0 2006.162.08:20:10.49#ibcon#flushed, iclass 22, count 0 2006.162.08:20:10.49#ibcon#about to write, iclass 22, count 0 2006.162.08:20:10.49#ibcon#wrote, iclass 22, count 0 2006.162.08:20:10.49#ibcon#about to read 3, iclass 22, count 0 2006.162.08:20:10.53#ibcon#read 3, iclass 22, count 0 2006.162.08:20:10.53#ibcon#about to read 4, iclass 22, count 0 2006.162.08:20:10.53#ibcon#read 4, iclass 22, count 0 2006.162.08:20:10.53#ibcon#about to read 5, iclass 22, count 0 2006.162.08:20:10.53#ibcon#read 5, iclass 22, count 0 2006.162.08:20:10.53#ibcon#about to read 6, iclass 22, count 0 2006.162.08:20:10.53#ibcon#read 6, iclass 22, count 0 2006.162.08:20:10.53#ibcon#end of sib2, iclass 22, count 0 2006.162.08:20:10.53#ibcon#*after write, iclass 22, count 0 2006.162.08:20:10.53#ibcon#*before return 0, iclass 22, count 0 2006.162.08:20:10.53#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:20:10.53#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:20:10.53#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.08:20:10.53#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.08:20:10.53$vc4f8/va=5,7 2006.162.08:20:10.53#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.162.08:20:10.53#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.162.08:20:10.53#ibcon#ireg 11 cls_cnt 2 2006.162.08:20:10.53#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:20:10.59#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:20:10.59#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:20:10.59#ibcon#enter wrdev, iclass 24, count 2 2006.162.08:20:10.59#ibcon#first serial, iclass 24, count 2 2006.162.08:20:10.59#ibcon#enter sib2, iclass 24, count 2 2006.162.08:20:10.59#ibcon#flushed, iclass 24, count 2 2006.162.08:20:10.59#ibcon#about to write, iclass 24, count 2 2006.162.08:20:10.59#ibcon#wrote, iclass 24, count 2 2006.162.08:20:10.59#ibcon#about to read 3, iclass 24, count 2 2006.162.08:20:10.62#ibcon#read 3, iclass 24, count 2 2006.162.08:20:10.62#ibcon#about to read 4, iclass 24, count 2 2006.162.08:20:10.62#ibcon#read 4, iclass 24, count 2 2006.162.08:20:10.62#ibcon#about to read 5, iclass 24, count 2 2006.162.08:20:10.62#ibcon#read 5, iclass 24, count 2 2006.162.08:20:10.62#ibcon#about to read 6, iclass 24, count 2 2006.162.08:20:10.62#ibcon#read 6, iclass 24, count 2 2006.162.08:20:10.62#ibcon#end of sib2, iclass 24, count 2 2006.162.08:20:10.62#ibcon#*mode == 0, iclass 24, count 2 2006.162.08:20:10.62#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.162.08:20:10.62#ibcon#[25=AT05-07\r\n] 2006.162.08:20:10.62#ibcon#*before write, iclass 24, count 2 2006.162.08:20:10.62#ibcon#enter sib2, iclass 24, count 2 2006.162.08:20:10.62#ibcon#flushed, iclass 24, count 2 2006.162.08:20:10.62#ibcon#about to write, iclass 24, count 2 2006.162.08:20:10.62#ibcon#wrote, iclass 24, count 2 2006.162.08:20:10.62#ibcon#about to read 3, iclass 24, count 2 2006.162.08:20:10.65#ibcon#read 3, iclass 24, count 2 2006.162.08:20:10.65#ibcon#about to read 4, iclass 24, count 2 2006.162.08:20:10.65#ibcon#read 4, iclass 24, count 2 2006.162.08:20:10.65#ibcon#about to read 5, iclass 24, count 2 2006.162.08:20:10.65#ibcon#read 5, iclass 24, count 2 2006.162.08:20:10.65#ibcon#about to read 6, iclass 24, count 2 2006.162.08:20:10.65#ibcon#read 6, iclass 24, count 2 2006.162.08:20:10.65#ibcon#end of sib2, iclass 24, count 2 2006.162.08:20:10.65#ibcon#*after write, iclass 24, count 2 2006.162.08:20:10.65#ibcon#*before return 0, iclass 24, count 2 2006.162.08:20:10.65#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:20:10.65#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:20:10.65#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.162.08:20:10.65#ibcon#ireg 7 cls_cnt 0 2006.162.08:20:10.65#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:20:10.77#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:20:10.77#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:20:10.77#ibcon#enter wrdev, iclass 24, count 0 2006.162.08:20:10.77#ibcon#first serial, iclass 24, count 0 2006.162.08:20:10.77#ibcon#enter sib2, iclass 24, count 0 2006.162.08:20:10.77#ibcon#flushed, iclass 24, count 0 2006.162.08:20:10.77#ibcon#about to write, iclass 24, count 0 2006.162.08:20:10.77#ibcon#wrote, iclass 24, count 0 2006.162.08:20:10.77#ibcon#about to read 3, iclass 24, count 0 2006.162.08:20:10.79#ibcon#read 3, iclass 24, count 0 2006.162.08:20:10.79#ibcon#about to read 4, iclass 24, count 0 2006.162.08:20:10.79#ibcon#read 4, iclass 24, count 0 2006.162.08:20:10.79#ibcon#about to read 5, iclass 24, count 0 2006.162.08:20:10.79#ibcon#read 5, iclass 24, count 0 2006.162.08:20:10.79#ibcon#about to read 6, iclass 24, count 0 2006.162.08:20:10.79#ibcon#read 6, iclass 24, count 0 2006.162.08:20:10.79#ibcon#end of sib2, iclass 24, count 0 2006.162.08:20:10.79#ibcon#*mode == 0, iclass 24, count 0 2006.162.08:20:10.79#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.08:20:10.79#ibcon#[25=USB\r\n] 2006.162.08:20:10.79#ibcon#*before write, iclass 24, count 0 2006.162.08:20:10.79#ibcon#enter sib2, iclass 24, count 0 2006.162.08:20:10.79#ibcon#flushed, iclass 24, count 0 2006.162.08:20:10.79#ibcon#about to write, iclass 24, count 0 2006.162.08:20:10.79#ibcon#wrote, iclass 24, count 0 2006.162.08:20:10.79#ibcon#about to read 3, iclass 24, count 0 2006.162.08:20:10.82#ibcon#read 3, iclass 24, count 0 2006.162.08:20:10.82#ibcon#about to read 4, iclass 24, count 0 2006.162.08:20:10.82#ibcon#read 4, iclass 24, count 0 2006.162.08:20:10.82#ibcon#about to read 5, iclass 24, count 0 2006.162.08:20:10.82#ibcon#read 5, iclass 24, count 0 2006.162.08:20:10.82#ibcon#about to read 6, iclass 24, count 0 2006.162.08:20:10.82#ibcon#read 6, iclass 24, count 0 2006.162.08:20:10.82#ibcon#end of sib2, iclass 24, count 0 2006.162.08:20:10.82#ibcon#*after write, iclass 24, count 0 2006.162.08:20:10.82#ibcon#*before return 0, iclass 24, count 0 2006.162.08:20:10.82#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:20:10.82#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:20:10.82#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.08:20:10.82#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.08:20:10.82$vc4f8/valo=6,772.99 2006.162.08:20:10.82#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.162.08:20:10.82#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.162.08:20:10.82#ibcon#ireg 17 cls_cnt 0 2006.162.08:20:10.82#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:20:10.82#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:20:10.82#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:20:10.82#ibcon#enter wrdev, iclass 26, count 0 2006.162.08:20:10.82#ibcon#first serial, iclass 26, count 0 2006.162.08:20:10.82#ibcon#enter sib2, iclass 26, count 0 2006.162.08:20:10.82#ibcon#flushed, iclass 26, count 0 2006.162.08:20:10.82#ibcon#about to write, iclass 26, count 0 2006.162.08:20:10.82#ibcon#wrote, iclass 26, count 0 2006.162.08:20:10.82#ibcon#about to read 3, iclass 26, count 0 2006.162.08:20:10.84#ibcon#read 3, iclass 26, count 0 2006.162.08:20:10.84#ibcon#about to read 4, iclass 26, count 0 2006.162.08:20:10.84#ibcon#read 4, iclass 26, count 0 2006.162.08:20:10.84#ibcon#about to read 5, iclass 26, count 0 2006.162.08:20:10.84#ibcon#read 5, iclass 26, count 0 2006.162.08:20:10.84#ibcon#about to read 6, iclass 26, count 0 2006.162.08:20:10.84#ibcon#read 6, iclass 26, count 0 2006.162.08:20:10.84#ibcon#end of sib2, iclass 26, count 0 2006.162.08:20:10.84#ibcon#*mode == 0, iclass 26, count 0 2006.162.08:20:10.84#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.162.08:20:10.84#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.08:20:10.84#ibcon#*before write, iclass 26, count 0 2006.162.08:20:10.84#ibcon#enter sib2, iclass 26, count 0 2006.162.08:20:10.84#ibcon#flushed, iclass 26, count 0 2006.162.08:20:10.84#ibcon#about to write, iclass 26, count 0 2006.162.08:20:10.84#ibcon#wrote, iclass 26, count 0 2006.162.08:20:10.84#ibcon#about to read 3, iclass 26, count 0 2006.162.08:20:10.88#ibcon#read 3, iclass 26, count 0 2006.162.08:20:10.88#ibcon#about to read 4, iclass 26, count 0 2006.162.08:20:10.88#ibcon#read 4, iclass 26, count 0 2006.162.08:20:10.88#ibcon#about to read 5, iclass 26, count 0 2006.162.08:20:10.88#ibcon#read 5, iclass 26, count 0 2006.162.08:20:10.88#ibcon#about to read 6, iclass 26, count 0 2006.162.08:20:10.88#ibcon#read 6, iclass 26, count 0 2006.162.08:20:10.88#ibcon#end of sib2, iclass 26, count 0 2006.162.08:20:10.88#ibcon#*after write, iclass 26, count 0 2006.162.08:20:10.88#ibcon#*before return 0, iclass 26, count 0 2006.162.08:20:10.88#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:20:10.88#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:20:10.88#ibcon#about to clear, iclass 26 cls_cnt 0 2006.162.08:20:10.88#ibcon#cleared, iclass 26 cls_cnt 0 2006.162.08:20:10.88$vc4f8/va=6,6 2006.162.08:20:10.88#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.162.08:20:10.88#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.162.08:20:10.88#ibcon#ireg 11 cls_cnt 2 2006.162.08:20:10.88#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:20:10.94#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:20:10.94#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:20:10.94#ibcon#enter wrdev, iclass 28, count 2 2006.162.08:20:10.94#ibcon#first serial, iclass 28, count 2 2006.162.08:20:10.94#ibcon#enter sib2, iclass 28, count 2 2006.162.08:20:10.94#ibcon#flushed, iclass 28, count 2 2006.162.08:20:10.94#ibcon#about to write, iclass 28, count 2 2006.162.08:20:10.94#ibcon#wrote, iclass 28, count 2 2006.162.08:20:10.94#ibcon#about to read 3, iclass 28, count 2 2006.162.08:20:10.96#ibcon#read 3, iclass 28, count 2 2006.162.08:20:10.96#ibcon#about to read 4, iclass 28, count 2 2006.162.08:20:10.96#ibcon#read 4, iclass 28, count 2 2006.162.08:20:10.96#ibcon#about to read 5, iclass 28, count 2 2006.162.08:20:10.96#ibcon#read 5, iclass 28, count 2 2006.162.08:20:10.96#ibcon#about to read 6, iclass 28, count 2 2006.162.08:20:10.96#ibcon#read 6, iclass 28, count 2 2006.162.08:20:10.96#ibcon#end of sib2, iclass 28, count 2 2006.162.08:20:10.96#ibcon#*mode == 0, iclass 28, count 2 2006.162.08:20:10.96#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.162.08:20:10.96#ibcon#[25=AT06-06\r\n] 2006.162.08:20:10.96#ibcon#*before write, iclass 28, count 2 2006.162.08:20:10.96#ibcon#enter sib2, iclass 28, count 2 2006.162.08:20:10.96#ibcon#flushed, iclass 28, count 2 2006.162.08:20:10.96#ibcon#about to write, iclass 28, count 2 2006.162.08:20:10.96#ibcon#wrote, iclass 28, count 2 2006.162.08:20:10.96#ibcon#about to read 3, iclass 28, count 2 2006.162.08:20:10.99#ibcon#read 3, iclass 28, count 2 2006.162.08:20:10.99#ibcon#about to read 4, iclass 28, count 2 2006.162.08:20:10.99#ibcon#read 4, iclass 28, count 2 2006.162.08:20:10.99#ibcon#about to read 5, iclass 28, count 2 2006.162.08:20:10.99#ibcon#read 5, iclass 28, count 2 2006.162.08:20:10.99#ibcon#about to read 6, iclass 28, count 2 2006.162.08:20:10.99#ibcon#read 6, iclass 28, count 2 2006.162.08:20:10.99#ibcon#end of sib2, iclass 28, count 2 2006.162.08:20:10.99#ibcon#*after write, iclass 28, count 2 2006.162.08:20:10.99#ibcon#*before return 0, iclass 28, count 2 2006.162.08:20:10.99#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:20:10.99#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:20:10.99#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.162.08:20:10.99#ibcon#ireg 7 cls_cnt 0 2006.162.08:20:10.99#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:20:11.11#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:20:11.11#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:20:11.11#ibcon#enter wrdev, iclass 28, count 0 2006.162.08:20:11.11#ibcon#first serial, iclass 28, count 0 2006.162.08:20:11.11#ibcon#enter sib2, iclass 28, count 0 2006.162.08:20:11.11#ibcon#flushed, iclass 28, count 0 2006.162.08:20:11.11#ibcon#about to write, iclass 28, count 0 2006.162.08:20:11.11#ibcon#wrote, iclass 28, count 0 2006.162.08:20:11.11#ibcon#about to read 3, iclass 28, count 0 2006.162.08:20:11.13#ibcon#read 3, iclass 28, count 0 2006.162.08:20:11.13#ibcon#about to read 4, iclass 28, count 0 2006.162.08:20:11.13#ibcon#read 4, iclass 28, count 0 2006.162.08:20:11.13#ibcon#about to read 5, iclass 28, count 0 2006.162.08:20:11.13#ibcon#read 5, iclass 28, count 0 2006.162.08:20:11.13#ibcon#about to read 6, iclass 28, count 0 2006.162.08:20:11.13#ibcon#read 6, iclass 28, count 0 2006.162.08:20:11.13#ibcon#end of sib2, iclass 28, count 0 2006.162.08:20:11.13#ibcon#*mode == 0, iclass 28, count 0 2006.162.08:20:11.13#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.162.08:20:11.13#ibcon#[25=USB\r\n] 2006.162.08:20:11.13#ibcon#*before write, iclass 28, count 0 2006.162.08:20:11.13#ibcon#enter sib2, iclass 28, count 0 2006.162.08:20:11.13#ibcon#flushed, iclass 28, count 0 2006.162.08:20:11.13#ibcon#about to write, iclass 28, count 0 2006.162.08:20:11.13#ibcon#wrote, iclass 28, count 0 2006.162.08:20:11.13#ibcon#about to read 3, iclass 28, count 0 2006.162.08:20:11.16#ibcon#read 3, iclass 28, count 0 2006.162.08:20:11.16#ibcon#about to read 4, iclass 28, count 0 2006.162.08:20:11.16#ibcon#read 4, iclass 28, count 0 2006.162.08:20:11.16#ibcon#about to read 5, iclass 28, count 0 2006.162.08:20:11.16#ibcon#read 5, iclass 28, count 0 2006.162.08:20:11.16#ibcon#about to read 6, iclass 28, count 0 2006.162.08:20:11.16#ibcon#read 6, iclass 28, count 0 2006.162.08:20:11.16#ibcon#end of sib2, iclass 28, count 0 2006.162.08:20:11.16#ibcon#*after write, iclass 28, count 0 2006.162.08:20:11.16#ibcon#*before return 0, iclass 28, count 0 2006.162.08:20:11.16#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:20:11.16#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:20:11.16#ibcon#about to clear, iclass 28 cls_cnt 0 2006.162.08:20:11.16#ibcon#cleared, iclass 28 cls_cnt 0 2006.162.08:20:11.16$vc4f8/valo=7,832.99 2006.162.08:20:11.16#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.162.08:20:11.16#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.162.08:20:11.16#ibcon#ireg 17 cls_cnt 0 2006.162.08:20:11.16#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:20:11.16#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:20:11.16#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:20:11.16#ibcon#enter wrdev, iclass 30, count 0 2006.162.08:20:11.16#ibcon#first serial, iclass 30, count 0 2006.162.08:20:11.16#ibcon#enter sib2, iclass 30, count 0 2006.162.08:20:11.16#ibcon#flushed, iclass 30, count 0 2006.162.08:20:11.16#ibcon#about to write, iclass 30, count 0 2006.162.08:20:11.16#ibcon#wrote, iclass 30, count 0 2006.162.08:20:11.16#ibcon#about to read 3, iclass 30, count 0 2006.162.08:20:11.18#ibcon#read 3, iclass 30, count 0 2006.162.08:20:11.18#ibcon#about to read 4, iclass 30, count 0 2006.162.08:20:11.18#ibcon#read 4, iclass 30, count 0 2006.162.08:20:11.18#ibcon#about to read 5, iclass 30, count 0 2006.162.08:20:11.18#ibcon#read 5, iclass 30, count 0 2006.162.08:20:11.18#ibcon#about to read 6, iclass 30, count 0 2006.162.08:20:11.18#ibcon#read 6, iclass 30, count 0 2006.162.08:20:11.18#ibcon#end of sib2, iclass 30, count 0 2006.162.08:20:11.18#ibcon#*mode == 0, iclass 30, count 0 2006.162.08:20:11.18#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.162.08:20:11.18#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.08:20:11.18#ibcon#*before write, iclass 30, count 0 2006.162.08:20:11.18#ibcon#enter sib2, iclass 30, count 0 2006.162.08:20:11.18#ibcon#flushed, iclass 30, count 0 2006.162.08:20:11.18#ibcon#about to write, iclass 30, count 0 2006.162.08:20:11.18#ibcon#wrote, iclass 30, count 0 2006.162.08:20:11.18#ibcon#about to read 3, iclass 30, count 0 2006.162.08:20:11.22#ibcon#read 3, iclass 30, count 0 2006.162.08:20:11.22#ibcon#about to read 4, iclass 30, count 0 2006.162.08:20:11.22#ibcon#read 4, iclass 30, count 0 2006.162.08:20:11.22#ibcon#about to read 5, iclass 30, count 0 2006.162.08:20:11.22#ibcon#read 5, iclass 30, count 0 2006.162.08:20:11.22#ibcon#about to read 6, iclass 30, count 0 2006.162.08:20:11.22#ibcon#read 6, iclass 30, count 0 2006.162.08:20:11.22#ibcon#end of sib2, iclass 30, count 0 2006.162.08:20:11.22#ibcon#*after write, iclass 30, count 0 2006.162.08:20:11.22#ibcon#*before return 0, iclass 30, count 0 2006.162.08:20:11.22#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:20:11.22#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:20:11.22#ibcon#about to clear, iclass 30 cls_cnt 0 2006.162.08:20:11.22#ibcon#cleared, iclass 30 cls_cnt 0 2006.162.08:20:11.22$vc4f8/va=7,6 2006.162.08:20:11.22#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.162.08:20:11.22#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.162.08:20:11.22#ibcon#ireg 11 cls_cnt 2 2006.162.08:20:11.22#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.162.08:20:11.28#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.162.08:20:11.28#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.162.08:20:11.28#ibcon#enter wrdev, iclass 32, count 2 2006.162.08:20:11.28#ibcon#first serial, iclass 32, count 2 2006.162.08:20:11.28#ibcon#enter sib2, iclass 32, count 2 2006.162.08:20:11.28#ibcon#flushed, iclass 32, count 2 2006.162.08:20:11.28#ibcon#about to write, iclass 32, count 2 2006.162.08:20:11.28#ibcon#wrote, iclass 32, count 2 2006.162.08:20:11.28#ibcon#about to read 3, iclass 32, count 2 2006.162.08:20:11.31#ibcon#read 3, iclass 32, count 2 2006.162.08:20:11.31#ibcon#about to read 4, iclass 32, count 2 2006.162.08:20:11.31#ibcon#read 4, iclass 32, count 2 2006.162.08:20:11.31#ibcon#about to read 5, iclass 32, count 2 2006.162.08:20:11.31#ibcon#read 5, iclass 32, count 2 2006.162.08:20:11.31#ibcon#about to read 6, iclass 32, count 2 2006.162.08:20:11.31#ibcon#read 6, iclass 32, count 2 2006.162.08:20:11.31#ibcon#end of sib2, iclass 32, count 2 2006.162.08:20:11.31#ibcon#*mode == 0, iclass 32, count 2 2006.162.08:20:11.31#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.162.08:20:11.31#ibcon#[25=AT07-06\r\n] 2006.162.08:20:11.31#ibcon#*before write, iclass 32, count 2 2006.162.08:20:11.31#ibcon#enter sib2, iclass 32, count 2 2006.162.08:20:11.31#ibcon#flushed, iclass 32, count 2 2006.162.08:20:11.31#ibcon#about to write, iclass 32, count 2 2006.162.08:20:11.31#ibcon#wrote, iclass 32, count 2 2006.162.08:20:11.31#ibcon#about to read 3, iclass 32, count 2 2006.162.08:20:11.34#ibcon#read 3, iclass 32, count 2 2006.162.08:20:11.34#ibcon#about to read 4, iclass 32, count 2 2006.162.08:20:11.34#ibcon#read 4, iclass 32, count 2 2006.162.08:20:11.34#ibcon#about to read 5, iclass 32, count 2 2006.162.08:20:11.34#ibcon#read 5, iclass 32, count 2 2006.162.08:20:11.34#ibcon#about to read 6, iclass 32, count 2 2006.162.08:20:11.34#ibcon#read 6, iclass 32, count 2 2006.162.08:20:11.34#ibcon#end of sib2, iclass 32, count 2 2006.162.08:20:11.34#ibcon#*after write, iclass 32, count 2 2006.162.08:20:11.34#ibcon#*before return 0, iclass 32, count 2 2006.162.08:20:11.34#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.162.08:20:11.34#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.162.08:20:11.34#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.162.08:20:11.34#ibcon#ireg 7 cls_cnt 0 2006.162.08:20:11.34#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.162.08:20:11.46#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.162.08:20:11.46#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.162.08:20:11.46#ibcon#enter wrdev, iclass 32, count 0 2006.162.08:20:11.46#ibcon#first serial, iclass 32, count 0 2006.162.08:20:11.46#ibcon#enter sib2, iclass 32, count 0 2006.162.08:20:11.46#ibcon#flushed, iclass 32, count 0 2006.162.08:20:11.46#ibcon#about to write, iclass 32, count 0 2006.162.08:20:11.46#ibcon#wrote, iclass 32, count 0 2006.162.08:20:11.46#ibcon#about to read 3, iclass 32, count 0 2006.162.08:20:11.48#ibcon#read 3, iclass 32, count 0 2006.162.08:20:11.48#ibcon#about to read 4, iclass 32, count 0 2006.162.08:20:11.48#ibcon#read 4, iclass 32, count 0 2006.162.08:20:11.48#ibcon#about to read 5, iclass 32, count 0 2006.162.08:20:11.48#ibcon#read 5, iclass 32, count 0 2006.162.08:20:11.48#ibcon#about to read 6, iclass 32, count 0 2006.162.08:20:11.48#ibcon#read 6, iclass 32, count 0 2006.162.08:20:11.48#ibcon#end of sib2, iclass 32, count 0 2006.162.08:20:11.48#ibcon#*mode == 0, iclass 32, count 0 2006.162.08:20:11.48#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.162.08:20:11.48#ibcon#[25=USB\r\n] 2006.162.08:20:11.48#ibcon#*before write, iclass 32, count 0 2006.162.08:20:11.48#ibcon#enter sib2, iclass 32, count 0 2006.162.08:20:11.48#ibcon#flushed, iclass 32, count 0 2006.162.08:20:11.48#ibcon#about to write, iclass 32, count 0 2006.162.08:20:11.48#ibcon#wrote, iclass 32, count 0 2006.162.08:20:11.48#ibcon#about to read 3, iclass 32, count 0 2006.162.08:20:11.51#ibcon#read 3, iclass 32, count 0 2006.162.08:20:11.51#ibcon#about to read 4, iclass 32, count 0 2006.162.08:20:11.51#ibcon#read 4, iclass 32, count 0 2006.162.08:20:11.51#ibcon#about to read 5, iclass 32, count 0 2006.162.08:20:11.51#ibcon#read 5, iclass 32, count 0 2006.162.08:20:11.51#ibcon#about to read 6, iclass 32, count 0 2006.162.08:20:11.51#ibcon#read 6, iclass 32, count 0 2006.162.08:20:11.51#ibcon#end of sib2, iclass 32, count 0 2006.162.08:20:11.51#ibcon#*after write, iclass 32, count 0 2006.162.08:20:11.51#ibcon#*before return 0, iclass 32, count 0 2006.162.08:20:11.51#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.162.08:20:11.51#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.162.08:20:11.51#ibcon#about to clear, iclass 32 cls_cnt 0 2006.162.08:20:11.51#ibcon#cleared, iclass 32 cls_cnt 0 2006.162.08:20:11.51$vc4f8/valo=8,852.99 2006.162.08:20:11.51#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.162.08:20:11.51#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.162.08:20:11.51#ibcon#ireg 17 cls_cnt 0 2006.162.08:20:11.51#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:20:11.51#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:20:11.51#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:20:11.51#ibcon#enter wrdev, iclass 34, count 0 2006.162.08:20:11.51#ibcon#first serial, iclass 34, count 0 2006.162.08:20:11.51#ibcon#enter sib2, iclass 34, count 0 2006.162.08:20:11.51#ibcon#flushed, iclass 34, count 0 2006.162.08:20:11.51#ibcon#about to write, iclass 34, count 0 2006.162.08:20:11.51#ibcon#wrote, iclass 34, count 0 2006.162.08:20:11.51#ibcon#about to read 3, iclass 34, count 0 2006.162.08:20:11.53#ibcon#read 3, iclass 34, count 0 2006.162.08:20:11.53#ibcon#about to read 4, iclass 34, count 0 2006.162.08:20:11.53#ibcon#read 4, iclass 34, count 0 2006.162.08:20:11.53#ibcon#about to read 5, iclass 34, count 0 2006.162.08:20:11.53#ibcon#read 5, iclass 34, count 0 2006.162.08:20:11.53#ibcon#about to read 6, iclass 34, count 0 2006.162.08:20:11.53#ibcon#read 6, iclass 34, count 0 2006.162.08:20:11.53#ibcon#end of sib2, iclass 34, count 0 2006.162.08:20:11.53#ibcon#*mode == 0, iclass 34, count 0 2006.162.08:20:11.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.162.08:20:11.53#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.08:20:11.53#ibcon#*before write, iclass 34, count 0 2006.162.08:20:11.53#ibcon#enter sib2, iclass 34, count 0 2006.162.08:20:11.53#ibcon#flushed, iclass 34, count 0 2006.162.08:20:11.53#ibcon#about to write, iclass 34, count 0 2006.162.08:20:11.53#ibcon#wrote, iclass 34, count 0 2006.162.08:20:11.53#ibcon#about to read 3, iclass 34, count 0 2006.162.08:20:11.57#ibcon#read 3, iclass 34, count 0 2006.162.08:20:11.57#ibcon#about to read 4, iclass 34, count 0 2006.162.08:20:11.57#ibcon#read 4, iclass 34, count 0 2006.162.08:20:11.57#ibcon#about to read 5, iclass 34, count 0 2006.162.08:20:11.57#ibcon#read 5, iclass 34, count 0 2006.162.08:20:11.57#ibcon#about to read 6, iclass 34, count 0 2006.162.08:20:11.57#ibcon#read 6, iclass 34, count 0 2006.162.08:20:11.57#ibcon#end of sib2, iclass 34, count 0 2006.162.08:20:11.57#ibcon#*after write, iclass 34, count 0 2006.162.08:20:11.57#ibcon#*before return 0, iclass 34, count 0 2006.162.08:20:11.57#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:20:11.57#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:20:11.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.162.08:20:11.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.162.08:20:11.57$vc4f8/va=8,7 2006.162.08:20:11.57#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.162.08:20:11.57#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.162.08:20:11.57#ibcon#ireg 11 cls_cnt 2 2006.162.08:20:11.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:20:11.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:20:11.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:20:11.63#ibcon#enter wrdev, iclass 36, count 2 2006.162.08:20:11.63#ibcon#first serial, iclass 36, count 2 2006.162.08:20:11.63#ibcon#enter sib2, iclass 36, count 2 2006.162.08:20:11.63#ibcon#flushed, iclass 36, count 2 2006.162.08:20:11.63#ibcon#about to write, iclass 36, count 2 2006.162.08:20:11.63#ibcon#wrote, iclass 36, count 2 2006.162.08:20:11.63#ibcon#about to read 3, iclass 36, count 2 2006.162.08:20:11.65#ibcon#read 3, iclass 36, count 2 2006.162.08:20:11.65#ibcon#about to read 4, iclass 36, count 2 2006.162.08:20:11.65#ibcon#read 4, iclass 36, count 2 2006.162.08:20:11.65#ibcon#about to read 5, iclass 36, count 2 2006.162.08:20:11.65#ibcon#read 5, iclass 36, count 2 2006.162.08:20:11.65#ibcon#about to read 6, iclass 36, count 2 2006.162.08:20:11.65#ibcon#read 6, iclass 36, count 2 2006.162.08:20:11.65#ibcon#end of sib2, iclass 36, count 2 2006.162.08:20:11.65#ibcon#*mode == 0, iclass 36, count 2 2006.162.08:20:11.65#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.162.08:20:11.65#ibcon#[25=AT08-07\r\n] 2006.162.08:20:11.65#ibcon#*before write, iclass 36, count 2 2006.162.08:20:11.65#ibcon#enter sib2, iclass 36, count 2 2006.162.08:20:11.65#ibcon#flushed, iclass 36, count 2 2006.162.08:20:11.65#ibcon#about to write, iclass 36, count 2 2006.162.08:20:11.65#ibcon#wrote, iclass 36, count 2 2006.162.08:20:11.65#ibcon#about to read 3, iclass 36, count 2 2006.162.08:20:11.68#ibcon#read 3, iclass 36, count 2 2006.162.08:20:11.68#ibcon#about to read 4, iclass 36, count 2 2006.162.08:20:11.68#ibcon#read 4, iclass 36, count 2 2006.162.08:20:11.68#ibcon#about to read 5, iclass 36, count 2 2006.162.08:20:11.68#ibcon#read 5, iclass 36, count 2 2006.162.08:20:11.68#ibcon#about to read 6, iclass 36, count 2 2006.162.08:20:11.68#ibcon#read 6, iclass 36, count 2 2006.162.08:20:11.68#ibcon#end of sib2, iclass 36, count 2 2006.162.08:20:11.68#ibcon#*after write, iclass 36, count 2 2006.162.08:20:11.68#ibcon#*before return 0, iclass 36, count 2 2006.162.08:20:11.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:20:11.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:20:11.68#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.162.08:20:11.68#ibcon#ireg 7 cls_cnt 0 2006.162.08:20:11.68#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:20:11.80#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:20:11.80#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:20:11.80#ibcon#enter wrdev, iclass 36, count 0 2006.162.08:20:11.80#ibcon#first serial, iclass 36, count 0 2006.162.08:20:11.80#ibcon#enter sib2, iclass 36, count 0 2006.162.08:20:11.80#ibcon#flushed, iclass 36, count 0 2006.162.08:20:11.80#ibcon#about to write, iclass 36, count 0 2006.162.08:20:11.80#ibcon#wrote, iclass 36, count 0 2006.162.08:20:11.80#ibcon#about to read 3, iclass 36, count 0 2006.162.08:20:11.82#ibcon#read 3, iclass 36, count 0 2006.162.08:20:11.82#ibcon#about to read 4, iclass 36, count 0 2006.162.08:20:11.82#ibcon#read 4, iclass 36, count 0 2006.162.08:20:11.82#ibcon#about to read 5, iclass 36, count 0 2006.162.08:20:11.82#ibcon#read 5, iclass 36, count 0 2006.162.08:20:11.82#ibcon#about to read 6, iclass 36, count 0 2006.162.08:20:11.82#ibcon#read 6, iclass 36, count 0 2006.162.08:20:11.82#ibcon#end of sib2, iclass 36, count 0 2006.162.08:20:11.82#ibcon#*mode == 0, iclass 36, count 0 2006.162.08:20:11.82#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.162.08:20:11.82#ibcon#[25=USB\r\n] 2006.162.08:20:11.82#ibcon#*before write, iclass 36, count 0 2006.162.08:20:11.82#ibcon#enter sib2, iclass 36, count 0 2006.162.08:20:11.82#ibcon#flushed, iclass 36, count 0 2006.162.08:20:11.82#ibcon#about to write, iclass 36, count 0 2006.162.08:20:11.82#ibcon#wrote, iclass 36, count 0 2006.162.08:20:11.82#ibcon#about to read 3, iclass 36, count 0 2006.162.08:20:11.85#ibcon#read 3, iclass 36, count 0 2006.162.08:20:11.85#ibcon#about to read 4, iclass 36, count 0 2006.162.08:20:11.85#ibcon#read 4, iclass 36, count 0 2006.162.08:20:11.85#ibcon#about to read 5, iclass 36, count 0 2006.162.08:20:11.85#ibcon#read 5, iclass 36, count 0 2006.162.08:20:11.85#ibcon#about to read 6, iclass 36, count 0 2006.162.08:20:11.85#ibcon#read 6, iclass 36, count 0 2006.162.08:20:11.85#ibcon#end of sib2, iclass 36, count 0 2006.162.08:20:11.85#ibcon#*after write, iclass 36, count 0 2006.162.08:20:11.85#ibcon#*before return 0, iclass 36, count 0 2006.162.08:20:11.85#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:20:11.85#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:20:11.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.162.08:20:11.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.162.08:20:11.85$vc4f8/vblo=1,632.99 2006.162.08:20:11.85#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.162.08:20:11.85#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.162.08:20:11.85#ibcon#ireg 17 cls_cnt 0 2006.162.08:20:11.85#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.162.08:20:11.85#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.162.08:20:11.85#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.162.08:20:11.85#ibcon#enter wrdev, iclass 38, count 0 2006.162.08:20:11.85#ibcon#first serial, iclass 38, count 0 2006.162.08:20:11.85#ibcon#enter sib2, iclass 38, count 0 2006.162.08:20:11.85#ibcon#flushed, iclass 38, count 0 2006.162.08:20:11.85#ibcon#about to write, iclass 38, count 0 2006.162.08:20:11.85#ibcon#wrote, iclass 38, count 0 2006.162.08:20:11.85#ibcon#about to read 3, iclass 38, count 0 2006.162.08:20:11.87#ibcon#read 3, iclass 38, count 0 2006.162.08:20:11.87#ibcon#about to read 4, iclass 38, count 0 2006.162.08:20:11.87#ibcon#read 4, iclass 38, count 0 2006.162.08:20:11.87#ibcon#about to read 5, iclass 38, count 0 2006.162.08:20:11.87#ibcon#read 5, iclass 38, count 0 2006.162.08:20:11.87#ibcon#about to read 6, iclass 38, count 0 2006.162.08:20:11.87#ibcon#read 6, iclass 38, count 0 2006.162.08:20:11.87#ibcon#end of sib2, iclass 38, count 0 2006.162.08:20:11.87#ibcon#*mode == 0, iclass 38, count 0 2006.162.08:20:11.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.162.08:20:11.87#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.08:20:11.87#ibcon#*before write, iclass 38, count 0 2006.162.08:20:11.87#ibcon#enter sib2, iclass 38, count 0 2006.162.08:20:11.87#ibcon#flushed, iclass 38, count 0 2006.162.08:20:11.87#ibcon#about to write, iclass 38, count 0 2006.162.08:20:11.87#ibcon#wrote, iclass 38, count 0 2006.162.08:20:11.87#ibcon#about to read 3, iclass 38, count 0 2006.162.08:20:11.91#ibcon#read 3, iclass 38, count 0 2006.162.08:20:11.91#ibcon#about to read 4, iclass 38, count 0 2006.162.08:20:11.91#ibcon#read 4, iclass 38, count 0 2006.162.08:20:11.91#ibcon#about to read 5, iclass 38, count 0 2006.162.08:20:11.91#ibcon#read 5, iclass 38, count 0 2006.162.08:20:11.91#ibcon#about to read 6, iclass 38, count 0 2006.162.08:20:11.91#ibcon#read 6, iclass 38, count 0 2006.162.08:20:11.91#ibcon#end of sib2, iclass 38, count 0 2006.162.08:20:11.91#ibcon#*after write, iclass 38, count 0 2006.162.08:20:11.91#ibcon#*before return 0, iclass 38, count 0 2006.162.08:20:11.91#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.162.08:20:11.91#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.162.08:20:11.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.162.08:20:11.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.162.08:20:11.91$vc4f8/vb=1,4 2006.162.08:20:11.91#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.162.08:20:11.91#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.162.08:20:11.91#ibcon#ireg 11 cls_cnt 2 2006.162.08:20:11.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.162.08:20:11.91#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.162.08:20:11.91#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.162.08:20:11.91#ibcon#enter wrdev, iclass 40, count 2 2006.162.08:20:11.91#ibcon#first serial, iclass 40, count 2 2006.162.08:20:11.91#ibcon#enter sib2, iclass 40, count 2 2006.162.08:20:11.91#ibcon#flushed, iclass 40, count 2 2006.162.08:20:11.91#ibcon#about to write, iclass 40, count 2 2006.162.08:20:11.91#ibcon#wrote, iclass 40, count 2 2006.162.08:20:11.91#ibcon#about to read 3, iclass 40, count 2 2006.162.08:20:11.93#ibcon#read 3, iclass 40, count 2 2006.162.08:20:11.93#ibcon#about to read 4, iclass 40, count 2 2006.162.08:20:11.93#ibcon#read 4, iclass 40, count 2 2006.162.08:20:11.93#ibcon#about to read 5, iclass 40, count 2 2006.162.08:20:11.93#ibcon#read 5, iclass 40, count 2 2006.162.08:20:11.93#ibcon#about to read 6, iclass 40, count 2 2006.162.08:20:11.93#ibcon#read 6, iclass 40, count 2 2006.162.08:20:11.93#ibcon#end of sib2, iclass 40, count 2 2006.162.08:20:11.93#ibcon#*mode == 0, iclass 40, count 2 2006.162.08:20:11.93#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.162.08:20:11.93#ibcon#[27=AT01-04\r\n] 2006.162.08:20:11.93#ibcon#*before write, iclass 40, count 2 2006.162.08:20:11.93#ibcon#enter sib2, iclass 40, count 2 2006.162.08:20:11.93#ibcon#flushed, iclass 40, count 2 2006.162.08:20:11.93#ibcon#about to write, iclass 40, count 2 2006.162.08:20:11.93#ibcon#wrote, iclass 40, count 2 2006.162.08:20:11.93#ibcon#about to read 3, iclass 40, count 2 2006.162.08:20:11.96#ibcon#read 3, iclass 40, count 2 2006.162.08:20:11.96#ibcon#about to read 4, iclass 40, count 2 2006.162.08:20:11.96#ibcon#read 4, iclass 40, count 2 2006.162.08:20:11.96#ibcon#about to read 5, iclass 40, count 2 2006.162.08:20:11.96#ibcon#read 5, iclass 40, count 2 2006.162.08:20:11.96#ibcon#about to read 6, iclass 40, count 2 2006.162.08:20:11.96#ibcon#read 6, iclass 40, count 2 2006.162.08:20:11.96#ibcon#end of sib2, iclass 40, count 2 2006.162.08:20:11.96#ibcon#*after write, iclass 40, count 2 2006.162.08:20:11.96#ibcon#*before return 0, iclass 40, count 2 2006.162.08:20:11.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.162.08:20:11.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.162.08:20:11.96#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.162.08:20:11.96#ibcon#ireg 7 cls_cnt 0 2006.162.08:20:11.96#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.162.08:20:12.08#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.162.08:20:12.08#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.162.08:20:12.08#ibcon#enter wrdev, iclass 40, count 0 2006.162.08:20:12.08#ibcon#first serial, iclass 40, count 0 2006.162.08:20:12.08#ibcon#enter sib2, iclass 40, count 0 2006.162.08:20:12.08#ibcon#flushed, iclass 40, count 0 2006.162.08:20:12.08#ibcon#about to write, iclass 40, count 0 2006.162.08:20:12.08#ibcon#wrote, iclass 40, count 0 2006.162.08:20:12.08#ibcon#about to read 3, iclass 40, count 0 2006.162.08:20:12.10#ibcon#read 3, iclass 40, count 0 2006.162.08:20:12.10#ibcon#about to read 4, iclass 40, count 0 2006.162.08:20:12.10#ibcon#read 4, iclass 40, count 0 2006.162.08:20:12.10#ibcon#about to read 5, iclass 40, count 0 2006.162.08:20:12.10#ibcon#read 5, iclass 40, count 0 2006.162.08:20:12.10#ibcon#about to read 6, iclass 40, count 0 2006.162.08:20:12.10#ibcon#read 6, iclass 40, count 0 2006.162.08:20:12.10#ibcon#end of sib2, iclass 40, count 0 2006.162.08:20:12.10#ibcon#*mode == 0, iclass 40, count 0 2006.162.08:20:12.10#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.162.08:20:12.10#ibcon#[27=USB\r\n] 2006.162.08:20:12.10#ibcon#*before write, iclass 40, count 0 2006.162.08:20:12.10#ibcon#enter sib2, iclass 40, count 0 2006.162.08:20:12.10#ibcon#flushed, iclass 40, count 0 2006.162.08:20:12.10#ibcon#about to write, iclass 40, count 0 2006.162.08:20:12.10#ibcon#wrote, iclass 40, count 0 2006.162.08:20:12.10#ibcon#about to read 3, iclass 40, count 0 2006.162.08:20:12.13#ibcon#read 3, iclass 40, count 0 2006.162.08:20:12.13#ibcon#about to read 4, iclass 40, count 0 2006.162.08:20:12.13#ibcon#read 4, iclass 40, count 0 2006.162.08:20:12.13#ibcon#about to read 5, iclass 40, count 0 2006.162.08:20:12.13#ibcon#read 5, iclass 40, count 0 2006.162.08:20:12.13#ibcon#about to read 6, iclass 40, count 0 2006.162.08:20:12.13#ibcon#read 6, iclass 40, count 0 2006.162.08:20:12.13#ibcon#end of sib2, iclass 40, count 0 2006.162.08:20:12.13#ibcon#*after write, iclass 40, count 0 2006.162.08:20:12.13#ibcon#*before return 0, iclass 40, count 0 2006.162.08:20:12.13#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.162.08:20:12.13#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.162.08:20:12.13#ibcon#about to clear, iclass 40 cls_cnt 0 2006.162.08:20:12.13#ibcon#cleared, iclass 40 cls_cnt 0 2006.162.08:20:12.13$vc4f8/vblo=2,640.99 2006.162.08:20:12.13#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.162.08:20:12.13#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.162.08:20:12.13#ibcon#ireg 17 cls_cnt 0 2006.162.08:20:12.13#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:20:12.13#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:20:12.13#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:20:12.13#ibcon#enter wrdev, iclass 4, count 0 2006.162.08:20:12.13#ibcon#first serial, iclass 4, count 0 2006.162.08:20:12.13#ibcon#enter sib2, iclass 4, count 0 2006.162.08:20:12.13#ibcon#flushed, iclass 4, count 0 2006.162.08:20:12.13#ibcon#about to write, iclass 4, count 0 2006.162.08:20:12.13#ibcon#wrote, iclass 4, count 0 2006.162.08:20:12.13#ibcon#about to read 3, iclass 4, count 0 2006.162.08:20:12.15#ibcon#read 3, iclass 4, count 0 2006.162.08:20:12.15#ibcon#about to read 4, iclass 4, count 0 2006.162.08:20:12.15#ibcon#read 4, iclass 4, count 0 2006.162.08:20:12.15#ibcon#about to read 5, iclass 4, count 0 2006.162.08:20:12.15#ibcon#read 5, iclass 4, count 0 2006.162.08:20:12.15#ibcon#about to read 6, iclass 4, count 0 2006.162.08:20:12.15#ibcon#read 6, iclass 4, count 0 2006.162.08:20:12.15#ibcon#end of sib2, iclass 4, count 0 2006.162.08:20:12.15#ibcon#*mode == 0, iclass 4, count 0 2006.162.08:20:12.15#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.162.08:20:12.15#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.08:20:12.15#ibcon#*before write, iclass 4, count 0 2006.162.08:20:12.15#ibcon#enter sib2, iclass 4, count 0 2006.162.08:20:12.15#ibcon#flushed, iclass 4, count 0 2006.162.08:20:12.15#ibcon#about to write, iclass 4, count 0 2006.162.08:20:12.15#ibcon#wrote, iclass 4, count 0 2006.162.08:20:12.15#ibcon#about to read 3, iclass 4, count 0 2006.162.08:20:12.19#ibcon#read 3, iclass 4, count 0 2006.162.08:20:12.19#ibcon#about to read 4, iclass 4, count 0 2006.162.08:20:12.19#ibcon#read 4, iclass 4, count 0 2006.162.08:20:12.19#ibcon#about to read 5, iclass 4, count 0 2006.162.08:20:12.19#ibcon#read 5, iclass 4, count 0 2006.162.08:20:12.19#ibcon#about to read 6, iclass 4, count 0 2006.162.08:20:12.19#ibcon#read 6, iclass 4, count 0 2006.162.08:20:12.19#ibcon#end of sib2, iclass 4, count 0 2006.162.08:20:12.19#ibcon#*after write, iclass 4, count 0 2006.162.08:20:12.19#ibcon#*before return 0, iclass 4, count 0 2006.162.08:20:12.19#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:20:12.19#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:20:12.19#ibcon#about to clear, iclass 4 cls_cnt 0 2006.162.08:20:12.19#ibcon#cleared, iclass 4 cls_cnt 0 2006.162.08:20:12.19$vc4f8/vb=2,4 2006.162.08:20:12.19#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.162.08:20:12.19#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.162.08:20:12.19#ibcon#ireg 11 cls_cnt 2 2006.162.08:20:12.19#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.162.08:20:12.25#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.162.08:20:12.25#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.162.08:20:12.25#ibcon#enter wrdev, iclass 6, count 2 2006.162.08:20:12.25#ibcon#first serial, iclass 6, count 2 2006.162.08:20:12.25#ibcon#enter sib2, iclass 6, count 2 2006.162.08:20:12.25#ibcon#flushed, iclass 6, count 2 2006.162.08:20:12.25#ibcon#about to write, iclass 6, count 2 2006.162.08:20:12.25#ibcon#wrote, iclass 6, count 2 2006.162.08:20:12.25#ibcon#about to read 3, iclass 6, count 2 2006.162.08:20:12.27#ibcon#read 3, iclass 6, count 2 2006.162.08:20:12.27#ibcon#about to read 4, iclass 6, count 2 2006.162.08:20:12.27#ibcon#read 4, iclass 6, count 2 2006.162.08:20:12.27#ibcon#about to read 5, iclass 6, count 2 2006.162.08:20:12.27#ibcon#read 5, iclass 6, count 2 2006.162.08:20:12.27#ibcon#about to read 6, iclass 6, count 2 2006.162.08:20:12.27#ibcon#read 6, iclass 6, count 2 2006.162.08:20:12.27#ibcon#end of sib2, iclass 6, count 2 2006.162.08:20:12.27#ibcon#*mode == 0, iclass 6, count 2 2006.162.08:20:12.27#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.162.08:20:12.27#ibcon#[27=AT02-04\r\n] 2006.162.08:20:12.27#ibcon#*before write, iclass 6, count 2 2006.162.08:20:12.27#ibcon#enter sib2, iclass 6, count 2 2006.162.08:20:12.27#ibcon#flushed, iclass 6, count 2 2006.162.08:20:12.27#ibcon#about to write, iclass 6, count 2 2006.162.08:20:12.27#ibcon#wrote, iclass 6, count 2 2006.162.08:20:12.27#ibcon#about to read 3, iclass 6, count 2 2006.162.08:20:12.30#ibcon#read 3, iclass 6, count 2 2006.162.08:20:12.30#ibcon#about to read 4, iclass 6, count 2 2006.162.08:20:12.30#ibcon#read 4, iclass 6, count 2 2006.162.08:20:12.30#ibcon#about to read 5, iclass 6, count 2 2006.162.08:20:12.30#ibcon#read 5, iclass 6, count 2 2006.162.08:20:12.30#ibcon#about to read 6, iclass 6, count 2 2006.162.08:20:12.30#ibcon#read 6, iclass 6, count 2 2006.162.08:20:12.30#ibcon#end of sib2, iclass 6, count 2 2006.162.08:20:12.30#ibcon#*after write, iclass 6, count 2 2006.162.08:20:12.30#ibcon#*before return 0, iclass 6, count 2 2006.162.08:20:12.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.162.08:20:12.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.162.08:20:12.30#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.162.08:20:12.30#ibcon#ireg 7 cls_cnt 0 2006.162.08:20:12.30#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.162.08:20:12.42#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.162.08:20:12.42#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.162.08:20:12.42#ibcon#enter wrdev, iclass 6, count 0 2006.162.08:20:12.42#ibcon#first serial, iclass 6, count 0 2006.162.08:20:12.42#ibcon#enter sib2, iclass 6, count 0 2006.162.08:20:12.42#ibcon#flushed, iclass 6, count 0 2006.162.08:20:12.42#ibcon#about to write, iclass 6, count 0 2006.162.08:20:12.42#ibcon#wrote, iclass 6, count 0 2006.162.08:20:12.42#ibcon#about to read 3, iclass 6, count 0 2006.162.08:20:12.44#ibcon#read 3, iclass 6, count 0 2006.162.08:20:12.44#ibcon#about to read 4, iclass 6, count 0 2006.162.08:20:12.44#ibcon#read 4, iclass 6, count 0 2006.162.08:20:12.44#ibcon#about to read 5, iclass 6, count 0 2006.162.08:20:12.44#ibcon#read 5, iclass 6, count 0 2006.162.08:20:12.44#ibcon#about to read 6, iclass 6, count 0 2006.162.08:20:12.44#ibcon#read 6, iclass 6, count 0 2006.162.08:20:12.44#ibcon#end of sib2, iclass 6, count 0 2006.162.08:20:12.44#ibcon#*mode == 0, iclass 6, count 0 2006.162.08:20:12.44#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.162.08:20:12.44#ibcon#[27=USB\r\n] 2006.162.08:20:12.44#ibcon#*before write, iclass 6, count 0 2006.162.08:20:12.44#ibcon#enter sib2, iclass 6, count 0 2006.162.08:20:12.44#ibcon#flushed, iclass 6, count 0 2006.162.08:20:12.44#ibcon#about to write, iclass 6, count 0 2006.162.08:20:12.44#ibcon#wrote, iclass 6, count 0 2006.162.08:20:12.44#ibcon#about to read 3, iclass 6, count 0 2006.162.08:20:12.47#ibcon#read 3, iclass 6, count 0 2006.162.08:20:12.47#ibcon#about to read 4, iclass 6, count 0 2006.162.08:20:12.47#ibcon#read 4, iclass 6, count 0 2006.162.08:20:12.47#ibcon#about to read 5, iclass 6, count 0 2006.162.08:20:12.47#ibcon#read 5, iclass 6, count 0 2006.162.08:20:12.47#ibcon#about to read 6, iclass 6, count 0 2006.162.08:20:12.47#ibcon#read 6, iclass 6, count 0 2006.162.08:20:12.47#ibcon#end of sib2, iclass 6, count 0 2006.162.08:20:12.47#ibcon#*after write, iclass 6, count 0 2006.162.08:20:12.47#ibcon#*before return 0, iclass 6, count 0 2006.162.08:20:12.47#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.162.08:20:12.47#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.162.08:20:12.47#ibcon#about to clear, iclass 6 cls_cnt 0 2006.162.08:20:12.47#ibcon#cleared, iclass 6 cls_cnt 0 2006.162.08:20:12.47$vc4f8/vblo=3,656.99 2006.162.08:20:12.47#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.162.08:20:12.47#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.162.08:20:12.47#ibcon#ireg 17 cls_cnt 0 2006.162.08:20:12.47#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:20:12.47#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:20:12.47#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:20:12.47#ibcon#enter wrdev, iclass 10, count 0 2006.162.08:20:12.47#ibcon#first serial, iclass 10, count 0 2006.162.08:20:12.47#ibcon#enter sib2, iclass 10, count 0 2006.162.08:20:12.47#ibcon#flushed, iclass 10, count 0 2006.162.08:20:12.47#ibcon#about to write, iclass 10, count 0 2006.162.08:20:12.47#ibcon#wrote, iclass 10, count 0 2006.162.08:20:12.47#ibcon#about to read 3, iclass 10, count 0 2006.162.08:20:12.49#ibcon#read 3, iclass 10, count 0 2006.162.08:20:12.49#ibcon#about to read 4, iclass 10, count 0 2006.162.08:20:12.49#ibcon#read 4, iclass 10, count 0 2006.162.08:20:12.49#ibcon#about to read 5, iclass 10, count 0 2006.162.08:20:12.49#ibcon#read 5, iclass 10, count 0 2006.162.08:20:12.49#ibcon#about to read 6, iclass 10, count 0 2006.162.08:20:12.49#ibcon#read 6, iclass 10, count 0 2006.162.08:20:12.49#ibcon#end of sib2, iclass 10, count 0 2006.162.08:20:12.49#ibcon#*mode == 0, iclass 10, count 0 2006.162.08:20:12.49#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.162.08:20:12.49#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.08:20:12.49#ibcon#*before write, iclass 10, count 0 2006.162.08:20:12.49#ibcon#enter sib2, iclass 10, count 0 2006.162.08:20:12.49#ibcon#flushed, iclass 10, count 0 2006.162.08:20:12.49#ibcon#about to write, iclass 10, count 0 2006.162.08:20:12.49#ibcon#wrote, iclass 10, count 0 2006.162.08:20:12.49#ibcon#about to read 3, iclass 10, count 0 2006.162.08:20:12.53#ibcon#read 3, iclass 10, count 0 2006.162.08:20:12.53#ibcon#about to read 4, iclass 10, count 0 2006.162.08:20:12.53#ibcon#read 4, iclass 10, count 0 2006.162.08:20:12.53#ibcon#about to read 5, iclass 10, count 0 2006.162.08:20:12.53#ibcon#read 5, iclass 10, count 0 2006.162.08:20:12.53#ibcon#about to read 6, iclass 10, count 0 2006.162.08:20:12.53#ibcon#read 6, iclass 10, count 0 2006.162.08:20:12.53#ibcon#end of sib2, iclass 10, count 0 2006.162.08:20:12.53#ibcon#*after write, iclass 10, count 0 2006.162.08:20:12.53#ibcon#*before return 0, iclass 10, count 0 2006.162.08:20:12.53#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:20:12.53#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:20:12.53#ibcon#about to clear, iclass 10 cls_cnt 0 2006.162.08:20:12.53#ibcon#cleared, iclass 10 cls_cnt 0 2006.162.08:20:12.53$vc4f8/vb=3,4 2006.162.08:20:12.53#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.162.08:20:12.53#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.162.08:20:12.53#ibcon#ireg 11 cls_cnt 2 2006.162.08:20:12.53#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:20:12.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:20:12.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:20:12.59#ibcon#enter wrdev, iclass 12, count 2 2006.162.08:20:12.59#ibcon#first serial, iclass 12, count 2 2006.162.08:20:12.59#ibcon#enter sib2, iclass 12, count 2 2006.162.08:20:12.59#ibcon#flushed, iclass 12, count 2 2006.162.08:20:12.59#ibcon#about to write, iclass 12, count 2 2006.162.08:20:12.59#ibcon#wrote, iclass 12, count 2 2006.162.08:20:12.59#ibcon#about to read 3, iclass 12, count 2 2006.162.08:20:12.61#ibcon#read 3, iclass 12, count 2 2006.162.08:20:12.61#ibcon#about to read 4, iclass 12, count 2 2006.162.08:20:12.61#ibcon#read 4, iclass 12, count 2 2006.162.08:20:12.61#ibcon#about to read 5, iclass 12, count 2 2006.162.08:20:12.61#ibcon#read 5, iclass 12, count 2 2006.162.08:20:12.61#ibcon#about to read 6, iclass 12, count 2 2006.162.08:20:12.61#ibcon#read 6, iclass 12, count 2 2006.162.08:20:12.61#ibcon#end of sib2, iclass 12, count 2 2006.162.08:20:12.61#ibcon#*mode == 0, iclass 12, count 2 2006.162.08:20:12.61#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.162.08:20:12.61#ibcon#[27=AT03-04\r\n] 2006.162.08:20:12.61#ibcon#*before write, iclass 12, count 2 2006.162.08:20:12.61#ibcon#enter sib2, iclass 12, count 2 2006.162.08:20:12.61#ibcon#flushed, iclass 12, count 2 2006.162.08:20:12.61#ibcon#about to write, iclass 12, count 2 2006.162.08:20:12.61#ibcon#wrote, iclass 12, count 2 2006.162.08:20:12.61#ibcon#about to read 3, iclass 12, count 2 2006.162.08:20:12.64#ibcon#read 3, iclass 12, count 2 2006.162.08:20:12.64#ibcon#about to read 4, iclass 12, count 2 2006.162.08:20:12.64#ibcon#read 4, iclass 12, count 2 2006.162.08:20:12.64#ibcon#about to read 5, iclass 12, count 2 2006.162.08:20:12.64#ibcon#read 5, iclass 12, count 2 2006.162.08:20:12.64#ibcon#about to read 6, iclass 12, count 2 2006.162.08:20:12.64#ibcon#read 6, iclass 12, count 2 2006.162.08:20:12.64#ibcon#end of sib2, iclass 12, count 2 2006.162.08:20:12.64#ibcon#*after write, iclass 12, count 2 2006.162.08:20:12.64#ibcon#*before return 0, iclass 12, count 2 2006.162.08:20:12.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:20:12.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:20:12.64#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.162.08:20:12.64#ibcon#ireg 7 cls_cnt 0 2006.162.08:20:12.64#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:20:12.76#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:20:12.76#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:20:12.76#ibcon#enter wrdev, iclass 12, count 0 2006.162.08:20:12.76#ibcon#first serial, iclass 12, count 0 2006.162.08:20:12.76#ibcon#enter sib2, iclass 12, count 0 2006.162.08:20:12.76#ibcon#flushed, iclass 12, count 0 2006.162.08:20:12.76#ibcon#about to write, iclass 12, count 0 2006.162.08:20:12.76#ibcon#wrote, iclass 12, count 0 2006.162.08:20:12.76#ibcon#about to read 3, iclass 12, count 0 2006.162.08:20:12.78#ibcon#read 3, iclass 12, count 0 2006.162.08:20:12.78#ibcon#about to read 4, iclass 12, count 0 2006.162.08:20:12.78#ibcon#read 4, iclass 12, count 0 2006.162.08:20:12.78#ibcon#about to read 5, iclass 12, count 0 2006.162.08:20:12.78#ibcon#read 5, iclass 12, count 0 2006.162.08:20:12.78#ibcon#about to read 6, iclass 12, count 0 2006.162.08:20:12.78#ibcon#read 6, iclass 12, count 0 2006.162.08:20:12.78#ibcon#end of sib2, iclass 12, count 0 2006.162.08:20:12.78#ibcon#*mode == 0, iclass 12, count 0 2006.162.08:20:12.78#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.162.08:20:12.78#ibcon#[27=USB\r\n] 2006.162.08:20:12.78#ibcon#*before write, iclass 12, count 0 2006.162.08:20:12.78#ibcon#enter sib2, iclass 12, count 0 2006.162.08:20:12.78#ibcon#flushed, iclass 12, count 0 2006.162.08:20:12.78#ibcon#about to write, iclass 12, count 0 2006.162.08:20:12.78#ibcon#wrote, iclass 12, count 0 2006.162.08:20:12.78#ibcon#about to read 3, iclass 12, count 0 2006.162.08:20:12.81#ibcon#read 3, iclass 12, count 0 2006.162.08:20:12.81#ibcon#about to read 4, iclass 12, count 0 2006.162.08:20:12.81#ibcon#read 4, iclass 12, count 0 2006.162.08:20:12.81#ibcon#about to read 5, iclass 12, count 0 2006.162.08:20:12.81#ibcon#read 5, iclass 12, count 0 2006.162.08:20:12.81#ibcon#about to read 6, iclass 12, count 0 2006.162.08:20:12.81#ibcon#read 6, iclass 12, count 0 2006.162.08:20:12.81#ibcon#end of sib2, iclass 12, count 0 2006.162.08:20:12.81#ibcon#*after write, iclass 12, count 0 2006.162.08:20:12.81#ibcon#*before return 0, iclass 12, count 0 2006.162.08:20:12.81#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:20:12.81#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:20:12.81#ibcon#about to clear, iclass 12 cls_cnt 0 2006.162.08:20:12.81#ibcon#cleared, iclass 12 cls_cnt 0 2006.162.08:20:12.81$vc4f8/vblo=4,712.99 2006.162.08:20:12.81#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.162.08:20:12.81#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.162.08:20:12.81#ibcon#ireg 17 cls_cnt 0 2006.162.08:20:12.81#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:20:12.81#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:20:12.81#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:20:12.81#ibcon#enter wrdev, iclass 14, count 0 2006.162.08:20:12.81#ibcon#first serial, iclass 14, count 0 2006.162.08:20:12.81#ibcon#enter sib2, iclass 14, count 0 2006.162.08:20:12.81#ibcon#flushed, iclass 14, count 0 2006.162.08:20:12.81#ibcon#about to write, iclass 14, count 0 2006.162.08:20:12.81#ibcon#wrote, iclass 14, count 0 2006.162.08:20:12.81#ibcon#about to read 3, iclass 14, count 0 2006.162.08:20:12.84#ibcon#read 3, iclass 14, count 0 2006.162.08:20:12.84#ibcon#about to read 4, iclass 14, count 0 2006.162.08:20:12.84#ibcon#read 4, iclass 14, count 0 2006.162.08:20:12.84#ibcon#about to read 5, iclass 14, count 0 2006.162.08:20:12.84#ibcon#read 5, iclass 14, count 0 2006.162.08:20:12.84#ibcon#about to read 6, iclass 14, count 0 2006.162.08:20:12.84#ibcon#read 6, iclass 14, count 0 2006.162.08:20:12.84#ibcon#end of sib2, iclass 14, count 0 2006.162.08:20:12.84#ibcon#*mode == 0, iclass 14, count 0 2006.162.08:20:12.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.08:20:12.84#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.08:20:12.84#ibcon#*before write, iclass 14, count 0 2006.162.08:20:12.84#ibcon#enter sib2, iclass 14, count 0 2006.162.08:20:12.84#ibcon#flushed, iclass 14, count 0 2006.162.08:20:12.84#ibcon#about to write, iclass 14, count 0 2006.162.08:20:12.84#ibcon#wrote, iclass 14, count 0 2006.162.08:20:12.84#ibcon#about to read 3, iclass 14, count 0 2006.162.08:20:12.88#ibcon#read 3, iclass 14, count 0 2006.162.08:20:12.88#ibcon#about to read 4, iclass 14, count 0 2006.162.08:20:12.88#ibcon#read 4, iclass 14, count 0 2006.162.08:20:12.88#ibcon#about to read 5, iclass 14, count 0 2006.162.08:20:12.88#ibcon#read 5, iclass 14, count 0 2006.162.08:20:12.88#ibcon#about to read 6, iclass 14, count 0 2006.162.08:20:12.88#ibcon#read 6, iclass 14, count 0 2006.162.08:20:12.88#ibcon#end of sib2, iclass 14, count 0 2006.162.08:20:12.88#ibcon#*after write, iclass 14, count 0 2006.162.08:20:12.88#ibcon#*before return 0, iclass 14, count 0 2006.162.08:20:12.88#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:20:12.88#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:20:12.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.08:20:12.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.08:20:12.88$vc4f8/vb=4,4 2006.162.08:20:12.88#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.162.08:20:12.88#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.162.08:20:12.88#ibcon#ireg 11 cls_cnt 2 2006.162.08:20:12.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:20:12.93#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:20:12.93#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:20:12.93#ibcon#enter wrdev, iclass 16, count 2 2006.162.08:20:12.93#ibcon#first serial, iclass 16, count 2 2006.162.08:20:12.93#ibcon#enter sib2, iclass 16, count 2 2006.162.08:20:12.93#ibcon#flushed, iclass 16, count 2 2006.162.08:20:12.93#ibcon#about to write, iclass 16, count 2 2006.162.08:20:12.93#ibcon#wrote, iclass 16, count 2 2006.162.08:20:12.93#ibcon#about to read 3, iclass 16, count 2 2006.162.08:20:12.95#ibcon#read 3, iclass 16, count 2 2006.162.08:20:12.95#ibcon#about to read 4, iclass 16, count 2 2006.162.08:20:12.95#ibcon#read 4, iclass 16, count 2 2006.162.08:20:12.95#ibcon#about to read 5, iclass 16, count 2 2006.162.08:20:12.95#ibcon#read 5, iclass 16, count 2 2006.162.08:20:12.95#ibcon#about to read 6, iclass 16, count 2 2006.162.08:20:12.95#ibcon#read 6, iclass 16, count 2 2006.162.08:20:12.95#ibcon#end of sib2, iclass 16, count 2 2006.162.08:20:12.95#ibcon#*mode == 0, iclass 16, count 2 2006.162.08:20:12.95#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.162.08:20:12.95#ibcon#[27=AT04-04\r\n] 2006.162.08:20:12.95#ibcon#*before write, iclass 16, count 2 2006.162.08:20:12.95#ibcon#enter sib2, iclass 16, count 2 2006.162.08:20:12.95#ibcon#flushed, iclass 16, count 2 2006.162.08:20:12.95#ibcon#about to write, iclass 16, count 2 2006.162.08:20:12.95#ibcon#wrote, iclass 16, count 2 2006.162.08:20:12.95#ibcon#about to read 3, iclass 16, count 2 2006.162.08:20:12.98#ibcon#read 3, iclass 16, count 2 2006.162.08:20:12.98#ibcon#about to read 4, iclass 16, count 2 2006.162.08:20:12.98#ibcon#read 4, iclass 16, count 2 2006.162.08:20:12.98#ibcon#about to read 5, iclass 16, count 2 2006.162.08:20:12.98#ibcon#read 5, iclass 16, count 2 2006.162.08:20:12.98#ibcon#about to read 6, iclass 16, count 2 2006.162.08:20:12.98#ibcon#read 6, iclass 16, count 2 2006.162.08:20:12.98#ibcon#end of sib2, iclass 16, count 2 2006.162.08:20:12.98#ibcon#*after write, iclass 16, count 2 2006.162.08:20:12.98#ibcon#*before return 0, iclass 16, count 2 2006.162.08:20:12.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:20:12.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:20:12.98#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.162.08:20:12.98#ibcon#ireg 7 cls_cnt 0 2006.162.08:20:12.98#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:20:13.10#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:20:13.10#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:20:13.10#ibcon#enter wrdev, iclass 16, count 0 2006.162.08:20:13.10#ibcon#first serial, iclass 16, count 0 2006.162.08:20:13.10#ibcon#enter sib2, iclass 16, count 0 2006.162.08:20:13.10#ibcon#flushed, iclass 16, count 0 2006.162.08:20:13.10#ibcon#about to write, iclass 16, count 0 2006.162.08:20:13.10#ibcon#wrote, iclass 16, count 0 2006.162.08:20:13.10#ibcon#about to read 3, iclass 16, count 0 2006.162.08:20:13.12#ibcon#read 3, iclass 16, count 0 2006.162.08:20:13.12#ibcon#about to read 4, iclass 16, count 0 2006.162.08:20:13.12#ibcon#read 4, iclass 16, count 0 2006.162.08:20:13.12#ibcon#about to read 5, iclass 16, count 0 2006.162.08:20:13.12#ibcon#read 5, iclass 16, count 0 2006.162.08:20:13.12#ibcon#about to read 6, iclass 16, count 0 2006.162.08:20:13.12#ibcon#read 6, iclass 16, count 0 2006.162.08:20:13.12#ibcon#end of sib2, iclass 16, count 0 2006.162.08:20:13.12#ibcon#*mode == 0, iclass 16, count 0 2006.162.08:20:13.12#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.162.08:20:13.12#ibcon#[27=USB\r\n] 2006.162.08:20:13.12#ibcon#*before write, iclass 16, count 0 2006.162.08:20:13.12#ibcon#enter sib2, iclass 16, count 0 2006.162.08:20:13.12#ibcon#flushed, iclass 16, count 0 2006.162.08:20:13.12#ibcon#about to write, iclass 16, count 0 2006.162.08:20:13.12#ibcon#wrote, iclass 16, count 0 2006.162.08:20:13.12#ibcon#about to read 3, iclass 16, count 0 2006.162.08:20:13.15#ibcon#read 3, iclass 16, count 0 2006.162.08:20:13.15#ibcon#about to read 4, iclass 16, count 0 2006.162.08:20:13.15#ibcon#read 4, iclass 16, count 0 2006.162.08:20:13.15#ibcon#about to read 5, iclass 16, count 0 2006.162.08:20:13.15#ibcon#read 5, iclass 16, count 0 2006.162.08:20:13.15#ibcon#about to read 6, iclass 16, count 0 2006.162.08:20:13.15#ibcon#read 6, iclass 16, count 0 2006.162.08:20:13.15#ibcon#end of sib2, iclass 16, count 0 2006.162.08:20:13.15#ibcon#*after write, iclass 16, count 0 2006.162.08:20:13.15#ibcon#*before return 0, iclass 16, count 0 2006.162.08:20:13.15#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:20:13.15#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:20:13.15#ibcon#about to clear, iclass 16 cls_cnt 0 2006.162.08:20:13.15#ibcon#cleared, iclass 16 cls_cnt 0 2006.162.08:20:13.15$vc4f8/vblo=5,744.99 2006.162.08:20:13.15#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.162.08:20:13.15#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.162.08:20:13.15#ibcon#ireg 17 cls_cnt 0 2006.162.08:20:13.15#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:20:13.15#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:20:13.15#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:20:13.15#ibcon#enter wrdev, iclass 18, count 0 2006.162.08:20:13.15#ibcon#first serial, iclass 18, count 0 2006.162.08:20:13.15#ibcon#enter sib2, iclass 18, count 0 2006.162.08:20:13.15#ibcon#flushed, iclass 18, count 0 2006.162.08:20:13.15#ibcon#about to write, iclass 18, count 0 2006.162.08:20:13.15#ibcon#wrote, iclass 18, count 0 2006.162.08:20:13.15#ibcon#about to read 3, iclass 18, count 0 2006.162.08:20:13.17#ibcon#read 3, iclass 18, count 0 2006.162.08:20:13.17#ibcon#about to read 4, iclass 18, count 0 2006.162.08:20:13.17#ibcon#read 4, iclass 18, count 0 2006.162.08:20:13.17#ibcon#about to read 5, iclass 18, count 0 2006.162.08:20:13.17#ibcon#read 5, iclass 18, count 0 2006.162.08:20:13.17#ibcon#about to read 6, iclass 18, count 0 2006.162.08:20:13.17#ibcon#read 6, iclass 18, count 0 2006.162.08:20:13.17#ibcon#end of sib2, iclass 18, count 0 2006.162.08:20:13.17#ibcon#*mode == 0, iclass 18, count 0 2006.162.08:20:13.17#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.162.08:20:13.17#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.08:20:13.17#ibcon#*before write, iclass 18, count 0 2006.162.08:20:13.17#ibcon#enter sib2, iclass 18, count 0 2006.162.08:20:13.17#ibcon#flushed, iclass 18, count 0 2006.162.08:20:13.17#ibcon#about to write, iclass 18, count 0 2006.162.08:20:13.17#ibcon#wrote, iclass 18, count 0 2006.162.08:20:13.17#ibcon#about to read 3, iclass 18, count 0 2006.162.08:20:13.21#ibcon#read 3, iclass 18, count 0 2006.162.08:20:13.21#ibcon#about to read 4, iclass 18, count 0 2006.162.08:20:13.21#ibcon#read 4, iclass 18, count 0 2006.162.08:20:13.21#ibcon#about to read 5, iclass 18, count 0 2006.162.08:20:13.21#ibcon#read 5, iclass 18, count 0 2006.162.08:20:13.21#ibcon#about to read 6, iclass 18, count 0 2006.162.08:20:13.21#ibcon#read 6, iclass 18, count 0 2006.162.08:20:13.21#ibcon#end of sib2, iclass 18, count 0 2006.162.08:20:13.21#ibcon#*after write, iclass 18, count 0 2006.162.08:20:13.21#ibcon#*before return 0, iclass 18, count 0 2006.162.08:20:13.21#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:20:13.21#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:20:13.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.162.08:20:13.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.162.08:20:13.21$vc4f8/vb=5,4 2006.162.08:20:13.21#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.162.08:20:13.21#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.162.08:20:13.21#ibcon#ireg 11 cls_cnt 2 2006.162.08:20:13.21#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:20:13.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:20:13.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:20:13.27#ibcon#enter wrdev, iclass 20, count 2 2006.162.08:20:13.27#ibcon#first serial, iclass 20, count 2 2006.162.08:20:13.27#ibcon#enter sib2, iclass 20, count 2 2006.162.08:20:13.27#ibcon#flushed, iclass 20, count 2 2006.162.08:20:13.27#ibcon#about to write, iclass 20, count 2 2006.162.08:20:13.27#ibcon#wrote, iclass 20, count 2 2006.162.08:20:13.27#ibcon#about to read 3, iclass 20, count 2 2006.162.08:20:13.29#ibcon#read 3, iclass 20, count 2 2006.162.08:20:13.29#ibcon#about to read 4, iclass 20, count 2 2006.162.08:20:13.29#ibcon#read 4, iclass 20, count 2 2006.162.08:20:13.29#ibcon#about to read 5, iclass 20, count 2 2006.162.08:20:13.29#ibcon#read 5, iclass 20, count 2 2006.162.08:20:13.29#ibcon#about to read 6, iclass 20, count 2 2006.162.08:20:13.29#ibcon#read 6, iclass 20, count 2 2006.162.08:20:13.29#ibcon#end of sib2, iclass 20, count 2 2006.162.08:20:13.29#ibcon#*mode == 0, iclass 20, count 2 2006.162.08:20:13.29#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.162.08:20:13.29#ibcon#[27=AT05-04\r\n] 2006.162.08:20:13.29#ibcon#*before write, iclass 20, count 2 2006.162.08:20:13.29#ibcon#enter sib2, iclass 20, count 2 2006.162.08:20:13.29#ibcon#flushed, iclass 20, count 2 2006.162.08:20:13.29#ibcon#about to write, iclass 20, count 2 2006.162.08:20:13.29#ibcon#wrote, iclass 20, count 2 2006.162.08:20:13.29#ibcon#about to read 3, iclass 20, count 2 2006.162.08:20:13.32#ibcon#read 3, iclass 20, count 2 2006.162.08:20:13.32#ibcon#about to read 4, iclass 20, count 2 2006.162.08:20:13.32#ibcon#read 4, iclass 20, count 2 2006.162.08:20:13.32#ibcon#about to read 5, iclass 20, count 2 2006.162.08:20:13.32#ibcon#read 5, iclass 20, count 2 2006.162.08:20:13.32#ibcon#about to read 6, iclass 20, count 2 2006.162.08:20:13.32#ibcon#read 6, iclass 20, count 2 2006.162.08:20:13.32#ibcon#end of sib2, iclass 20, count 2 2006.162.08:20:13.32#ibcon#*after write, iclass 20, count 2 2006.162.08:20:13.32#ibcon#*before return 0, iclass 20, count 2 2006.162.08:20:13.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:20:13.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:20:13.32#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.162.08:20:13.32#ibcon#ireg 7 cls_cnt 0 2006.162.08:20:13.32#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:20:13.44#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:20:13.44#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:20:13.44#ibcon#enter wrdev, iclass 20, count 0 2006.162.08:20:13.44#ibcon#first serial, iclass 20, count 0 2006.162.08:20:13.44#ibcon#enter sib2, iclass 20, count 0 2006.162.08:20:13.44#ibcon#flushed, iclass 20, count 0 2006.162.08:20:13.44#ibcon#about to write, iclass 20, count 0 2006.162.08:20:13.44#ibcon#wrote, iclass 20, count 0 2006.162.08:20:13.44#ibcon#about to read 3, iclass 20, count 0 2006.162.08:20:13.46#ibcon#read 3, iclass 20, count 0 2006.162.08:20:13.46#ibcon#about to read 4, iclass 20, count 0 2006.162.08:20:13.46#ibcon#read 4, iclass 20, count 0 2006.162.08:20:13.46#ibcon#about to read 5, iclass 20, count 0 2006.162.08:20:13.46#ibcon#read 5, iclass 20, count 0 2006.162.08:20:13.46#ibcon#about to read 6, iclass 20, count 0 2006.162.08:20:13.46#ibcon#read 6, iclass 20, count 0 2006.162.08:20:13.46#ibcon#end of sib2, iclass 20, count 0 2006.162.08:20:13.46#ibcon#*mode == 0, iclass 20, count 0 2006.162.08:20:13.46#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.08:20:13.46#ibcon#[27=USB\r\n] 2006.162.08:20:13.46#ibcon#*before write, iclass 20, count 0 2006.162.08:20:13.46#ibcon#enter sib2, iclass 20, count 0 2006.162.08:20:13.46#ibcon#flushed, iclass 20, count 0 2006.162.08:20:13.46#ibcon#about to write, iclass 20, count 0 2006.162.08:20:13.46#ibcon#wrote, iclass 20, count 0 2006.162.08:20:13.46#ibcon#about to read 3, iclass 20, count 0 2006.162.08:20:13.49#ibcon#read 3, iclass 20, count 0 2006.162.08:20:13.49#ibcon#about to read 4, iclass 20, count 0 2006.162.08:20:13.49#ibcon#read 4, iclass 20, count 0 2006.162.08:20:13.49#ibcon#about to read 5, iclass 20, count 0 2006.162.08:20:13.49#ibcon#read 5, iclass 20, count 0 2006.162.08:20:13.49#ibcon#about to read 6, iclass 20, count 0 2006.162.08:20:13.49#ibcon#read 6, iclass 20, count 0 2006.162.08:20:13.49#ibcon#end of sib2, iclass 20, count 0 2006.162.08:20:13.49#ibcon#*after write, iclass 20, count 0 2006.162.08:20:13.49#ibcon#*before return 0, iclass 20, count 0 2006.162.08:20:13.49#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:20:13.49#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:20:13.49#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.08:20:13.49#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.08:20:13.49$vc4f8/vblo=6,752.99 2006.162.08:20:13.49#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.162.08:20:13.49#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.162.08:20:13.49#ibcon#ireg 17 cls_cnt 0 2006.162.08:20:13.49#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:20:13.49#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:20:13.49#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:20:13.49#ibcon#enter wrdev, iclass 22, count 0 2006.162.08:20:13.49#ibcon#first serial, iclass 22, count 0 2006.162.08:20:13.49#ibcon#enter sib2, iclass 22, count 0 2006.162.08:20:13.49#ibcon#flushed, iclass 22, count 0 2006.162.08:20:13.49#ibcon#about to write, iclass 22, count 0 2006.162.08:20:13.49#ibcon#wrote, iclass 22, count 0 2006.162.08:20:13.49#ibcon#about to read 3, iclass 22, count 0 2006.162.08:20:13.51#ibcon#read 3, iclass 22, count 0 2006.162.08:20:13.51#ibcon#about to read 4, iclass 22, count 0 2006.162.08:20:13.51#ibcon#read 4, iclass 22, count 0 2006.162.08:20:13.51#ibcon#about to read 5, iclass 22, count 0 2006.162.08:20:13.51#ibcon#read 5, iclass 22, count 0 2006.162.08:20:13.51#ibcon#about to read 6, iclass 22, count 0 2006.162.08:20:13.51#ibcon#read 6, iclass 22, count 0 2006.162.08:20:13.51#ibcon#end of sib2, iclass 22, count 0 2006.162.08:20:13.51#ibcon#*mode == 0, iclass 22, count 0 2006.162.08:20:13.51#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.08:20:13.51#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.08:20:13.51#ibcon#*before write, iclass 22, count 0 2006.162.08:20:13.51#ibcon#enter sib2, iclass 22, count 0 2006.162.08:20:13.51#ibcon#flushed, iclass 22, count 0 2006.162.08:20:13.51#ibcon#about to write, iclass 22, count 0 2006.162.08:20:13.51#ibcon#wrote, iclass 22, count 0 2006.162.08:20:13.51#ibcon#about to read 3, iclass 22, count 0 2006.162.08:20:13.55#ibcon#read 3, iclass 22, count 0 2006.162.08:20:13.55#ibcon#about to read 4, iclass 22, count 0 2006.162.08:20:13.55#ibcon#read 4, iclass 22, count 0 2006.162.08:20:13.55#ibcon#about to read 5, iclass 22, count 0 2006.162.08:20:13.55#ibcon#read 5, iclass 22, count 0 2006.162.08:20:13.55#ibcon#about to read 6, iclass 22, count 0 2006.162.08:20:13.55#ibcon#read 6, iclass 22, count 0 2006.162.08:20:13.55#ibcon#end of sib2, iclass 22, count 0 2006.162.08:20:13.55#ibcon#*after write, iclass 22, count 0 2006.162.08:20:13.55#ibcon#*before return 0, iclass 22, count 0 2006.162.08:20:13.55#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:20:13.55#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:20:13.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.08:20:13.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.08:20:13.55$vc4f8/vb=6,4 2006.162.08:20:13.55#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.162.08:20:13.55#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.162.08:20:13.55#ibcon#ireg 11 cls_cnt 2 2006.162.08:20:13.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:20:13.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:20:13.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:20:13.61#ibcon#enter wrdev, iclass 24, count 2 2006.162.08:20:13.61#ibcon#first serial, iclass 24, count 2 2006.162.08:20:13.61#ibcon#enter sib2, iclass 24, count 2 2006.162.08:20:13.61#ibcon#flushed, iclass 24, count 2 2006.162.08:20:13.61#ibcon#about to write, iclass 24, count 2 2006.162.08:20:13.61#ibcon#wrote, iclass 24, count 2 2006.162.08:20:13.61#ibcon#about to read 3, iclass 24, count 2 2006.162.08:20:13.63#ibcon#read 3, iclass 24, count 2 2006.162.08:20:13.63#ibcon#about to read 4, iclass 24, count 2 2006.162.08:20:13.63#ibcon#read 4, iclass 24, count 2 2006.162.08:20:13.63#ibcon#about to read 5, iclass 24, count 2 2006.162.08:20:13.63#ibcon#read 5, iclass 24, count 2 2006.162.08:20:13.63#ibcon#about to read 6, iclass 24, count 2 2006.162.08:20:13.63#ibcon#read 6, iclass 24, count 2 2006.162.08:20:13.63#ibcon#end of sib2, iclass 24, count 2 2006.162.08:20:13.63#ibcon#*mode == 0, iclass 24, count 2 2006.162.08:20:13.63#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.162.08:20:13.63#ibcon#[27=AT06-04\r\n] 2006.162.08:20:13.63#ibcon#*before write, iclass 24, count 2 2006.162.08:20:13.63#ibcon#enter sib2, iclass 24, count 2 2006.162.08:20:13.63#ibcon#flushed, iclass 24, count 2 2006.162.08:20:13.63#ibcon#about to write, iclass 24, count 2 2006.162.08:20:13.63#ibcon#wrote, iclass 24, count 2 2006.162.08:20:13.63#ibcon#about to read 3, iclass 24, count 2 2006.162.08:20:13.66#ibcon#read 3, iclass 24, count 2 2006.162.08:20:13.66#ibcon#about to read 4, iclass 24, count 2 2006.162.08:20:13.66#ibcon#read 4, iclass 24, count 2 2006.162.08:20:13.66#ibcon#about to read 5, iclass 24, count 2 2006.162.08:20:13.66#ibcon#read 5, iclass 24, count 2 2006.162.08:20:13.66#ibcon#about to read 6, iclass 24, count 2 2006.162.08:20:13.66#ibcon#read 6, iclass 24, count 2 2006.162.08:20:13.66#ibcon#end of sib2, iclass 24, count 2 2006.162.08:20:13.66#ibcon#*after write, iclass 24, count 2 2006.162.08:20:13.66#ibcon#*before return 0, iclass 24, count 2 2006.162.08:20:13.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:20:13.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:20:13.66#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.162.08:20:13.66#ibcon#ireg 7 cls_cnt 0 2006.162.08:20:13.66#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:20:13.78#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:20:13.78#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:20:13.78#ibcon#enter wrdev, iclass 24, count 0 2006.162.08:20:13.78#ibcon#first serial, iclass 24, count 0 2006.162.08:20:13.78#ibcon#enter sib2, iclass 24, count 0 2006.162.08:20:13.78#ibcon#flushed, iclass 24, count 0 2006.162.08:20:13.78#ibcon#about to write, iclass 24, count 0 2006.162.08:20:13.78#ibcon#wrote, iclass 24, count 0 2006.162.08:20:13.78#ibcon#about to read 3, iclass 24, count 0 2006.162.08:20:13.80#ibcon#read 3, iclass 24, count 0 2006.162.08:20:13.80#ibcon#about to read 4, iclass 24, count 0 2006.162.08:20:13.80#ibcon#read 4, iclass 24, count 0 2006.162.08:20:13.80#ibcon#about to read 5, iclass 24, count 0 2006.162.08:20:13.80#ibcon#read 5, iclass 24, count 0 2006.162.08:20:13.80#ibcon#about to read 6, iclass 24, count 0 2006.162.08:20:13.80#ibcon#read 6, iclass 24, count 0 2006.162.08:20:13.80#ibcon#end of sib2, iclass 24, count 0 2006.162.08:20:13.80#ibcon#*mode == 0, iclass 24, count 0 2006.162.08:20:13.80#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.08:20:13.80#ibcon#[27=USB\r\n] 2006.162.08:20:13.80#ibcon#*before write, iclass 24, count 0 2006.162.08:20:13.80#ibcon#enter sib2, iclass 24, count 0 2006.162.08:20:13.80#ibcon#flushed, iclass 24, count 0 2006.162.08:20:13.80#ibcon#about to write, iclass 24, count 0 2006.162.08:20:13.80#ibcon#wrote, iclass 24, count 0 2006.162.08:20:13.80#ibcon#about to read 3, iclass 24, count 0 2006.162.08:20:13.83#ibcon#read 3, iclass 24, count 0 2006.162.08:20:13.83#ibcon#about to read 4, iclass 24, count 0 2006.162.08:20:13.83#ibcon#read 4, iclass 24, count 0 2006.162.08:20:13.83#ibcon#about to read 5, iclass 24, count 0 2006.162.08:20:13.83#ibcon#read 5, iclass 24, count 0 2006.162.08:20:13.83#ibcon#about to read 6, iclass 24, count 0 2006.162.08:20:13.83#ibcon#read 6, iclass 24, count 0 2006.162.08:20:13.83#ibcon#end of sib2, iclass 24, count 0 2006.162.08:20:13.83#ibcon#*after write, iclass 24, count 0 2006.162.08:20:13.83#ibcon#*before return 0, iclass 24, count 0 2006.162.08:20:13.83#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:20:13.83#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:20:13.83#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.08:20:13.83#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.08:20:13.83$vc4f8/vabw=wide 2006.162.08:20:13.83#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.162.08:20:13.83#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.162.08:20:13.83#ibcon#ireg 8 cls_cnt 0 2006.162.08:20:13.83#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:20:13.83#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:20:13.83#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:20:13.83#ibcon#enter wrdev, iclass 26, count 0 2006.162.08:20:13.83#ibcon#first serial, iclass 26, count 0 2006.162.08:20:13.83#ibcon#enter sib2, iclass 26, count 0 2006.162.08:20:13.83#ibcon#flushed, iclass 26, count 0 2006.162.08:20:13.83#ibcon#about to write, iclass 26, count 0 2006.162.08:20:13.83#ibcon#wrote, iclass 26, count 0 2006.162.08:20:13.83#ibcon#about to read 3, iclass 26, count 0 2006.162.08:20:13.85#ibcon#read 3, iclass 26, count 0 2006.162.08:20:13.85#ibcon#about to read 4, iclass 26, count 0 2006.162.08:20:13.85#ibcon#read 4, iclass 26, count 0 2006.162.08:20:13.85#ibcon#about to read 5, iclass 26, count 0 2006.162.08:20:13.85#ibcon#read 5, iclass 26, count 0 2006.162.08:20:13.85#ibcon#about to read 6, iclass 26, count 0 2006.162.08:20:13.85#ibcon#read 6, iclass 26, count 0 2006.162.08:20:13.85#ibcon#end of sib2, iclass 26, count 0 2006.162.08:20:13.85#ibcon#*mode == 0, iclass 26, count 0 2006.162.08:20:13.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.162.08:20:13.85#ibcon#[25=BW32\r\n] 2006.162.08:20:13.85#ibcon#*before write, iclass 26, count 0 2006.162.08:20:13.85#ibcon#enter sib2, iclass 26, count 0 2006.162.08:20:13.85#ibcon#flushed, iclass 26, count 0 2006.162.08:20:13.85#ibcon#about to write, iclass 26, count 0 2006.162.08:20:13.85#ibcon#wrote, iclass 26, count 0 2006.162.08:20:13.85#ibcon#about to read 3, iclass 26, count 0 2006.162.08:20:13.88#ibcon#read 3, iclass 26, count 0 2006.162.08:20:13.88#ibcon#about to read 4, iclass 26, count 0 2006.162.08:20:13.88#ibcon#read 4, iclass 26, count 0 2006.162.08:20:13.88#ibcon#about to read 5, iclass 26, count 0 2006.162.08:20:13.88#ibcon#read 5, iclass 26, count 0 2006.162.08:20:13.88#ibcon#about to read 6, iclass 26, count 0 2006.162.08:20:13.88#ibcon#read 6, iclass 26, count 0 2006.162.08:20:13.88#ibcon#end of sib2, iclass 26, count 0 2006.162.08:20:13.88#ibcon#*after write, iclass 26, count 0 2006.162.08:20:13.88#ibcon#*before return 0, iclass 26, count 0 2006.162.08:20:13.88#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:20:13.88#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:20:13.88#ibcon#about to clear, iclass 26 cls_cnt 0 2006.162.08:20:13.88#ibcon#cleared, iclass 26 cls_cnt 0 2006.162.08:20:13.88$vc4f8/vbbw=wide 2006.162.08:20:13.88#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.162.08:20:13.88#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.162.08:20:13.88#ibcon#ireg 8 cls_cnt 0 2006.162.08:20:13.88#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:20:13.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:20:13.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:20:13.95#ibcon#enter wrdev, iclass 28, count 0 2006.162.08:20:13.95#ibcon#first serial, iclass 28, count 0 2006.162.08:20:13.95#ibcon#enter sib2, iclass 28, count 0 2006.162.08:20:13.95#ibcon#flushed, iclass 28, count 0 2006.162.08:20:13.95#ibcon#about to write, iclass 28, count 0 2006.162.08:20:13.95#ibcon#wrote, iclass 28, count 0 2006.162.08:20:13.95#ibcon#about to read 3, iclass 28, count 0 2006.162.08:20:13.97#ibcon#read 3, iclass 28, count 0 2006.162.08:20:13.97#ibcon#about to read 4, iclass 28, count 0 2006.162.08:20:13.97#ibcon#read 4, iclass 28, count 0 2006.162.08:20:13.97#ibcon#about to read 5, iclass 28, count 0 2006.162.08:20:13.97#ibcon#read 5, iclass 28, count 0 2006.162.08:20:13.97#ibcon#about to read 6, iclass 28, count 0 2006.162.08:20:13.97#ibcon#read 6, iclass 28, count 0 2006.162.08:20:13.97#ibcon#end of sib2, iclass 28, count 0 2006.162.08:20:13.97#ibcon#*mode == 0, iclass 28, count 0 2006.162.08:20:13.97#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.162.08:20:13.97#ibcon#[27=BW32\r\n] 2006.162.08:20:13.97#ibcon#*before write, iclass 28, count 0 2006.162.08:20:13.97#ibcon#enter sib2, iclass 28, count 0 2006.162.08:20:13.97#ibcon#flushed, iclass 28, count 0 2006.162.08:20:13.97#ibcon#about to write, iclass 28, count 0 2006.162.08:20:13.97#ibcon#wrote, iclass 28, count 0 2006.162.08:20:13.97#ibcon#about to read 3, iclass 28, count 0 2006.162.08:20:14.00#ibcon#read 3, iclass 28, count 0 2006.162.08:20:14.00#ibcon#about to read 4, iclass 28, count 0 2006.162.08:20:14.00#ibcon#read 4, iclass 28, count 0 2006.162.08:20:14.00#ibcon#about to read 5, iclass 28, count 0 2006.162.08:20:14.00#ibcon#read 5, iclass 28, count 0 2006.162.08:20:14.00#ibcon#about to read 6, iclass 28, count 0 2006.162.08:20:14.00#ibcon#read 6, iclass 28, count 0 2006.162.08:20:14.00#ibcon#end of sib2, iclass 28, count 0 2006.162.08:20:14.00#ibcon#*after write, iclass 28, count 0 2006.162.08:20:14.00#ibcon#*before return 0, iclass 28, count 0 2006.162.08:20:14.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:20:14.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:20:14.00#ibcon#about to clear, iclass 28 cls_cnt 0 2006.162.08:20:14.00#ibcon#cleared, iclass 28 cls_cnt 0 2006.162.08:20:14.00$4f8m12a/ifd4f 2006.162.08:20:14.00$ifd4f/lo= 2006.162.08:20:14.00$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.08:20:14.00$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.08:20:14.00$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.08:20:14.00$ifd4f/patch= 2006.162.08:20:14.00$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.08:20:14.00$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.08:20:14.00$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.08:20:14.00$4f8m12a/"form=m,16.000,1:2 2006.162.08:20:14.00$4f8m12a/"tpicd 2006.162.08:20:14.00$4f8m12a/echo=off 2006.162.08:20:14.00$4f8m12a/xlog=off 2006.162.08:20:14.00:!2006.162.08:22:20 2006.162.08:20:27.14#trakl#Source acquired 2006.162.08:20:28.14#flagr#flagr/antenna,acquired 2006.162.08:22:20.00:preob 2006.162.08:22:20.14/onsource/TRACKING 2006.162.08:22:20.14:!2006.162.08:22:30 2006.162.08:22:30.00:data_valid=on 2006.162.08:22:30.00:midob 2006.162.08:22:31.14/onsource/TRACKING 2006.162.08:22:31.14/wx/17.84,1006.8,100 2006.162.08:22:31.20/cable/+6.5357E-03 2006.162.08:22:32.29/va/01,08,usb,yes,32,34 2006.162.08:22:32.29/va/02,07,usb,yes,33,34 2006.162.08:22:32.29/va/03,06,usb,yes,34,35 2006.162.08:22:32.29/va/04,07,usb,yes,34,36 2006.162.08:22:32.29/va/05,07,usb,yes,36,38 2006.162.08:22:32.29/va/06,06,usb,yes,35,35 2006.162.08:22:32.29/va/07,06,usb,yes,35,35 2006.162.08:22:32.29/va/08,07,usb,yes,34,33 2006.162.08:22:32.52/valo/01,532.99,yes,locked 2006.162.08:22:32.52/valo/02,572.99,yes,locked 2006.162.08:22:32.52/valo/03,672.99,yes,locked 2006.162.08:22:32.52/valo/04,832.99,yes,locked 2006.162.08:22:32.52/valo/05,652.99,yes,locked 2006.162.08:22:32.52/valo/06,772.99,yes,locked 2006.162.08:22:32.52/valo/07,832.99,yes,locked 2006.162.08:22:32.52/valo/08,852.99,yes,locked 2006.162.08:22:33.61/vb/01,04,usb,yes,28,27 2006.162.08:22:33.61/vb/02,04,usb,yes,30,32 2006.162.08:22:33.61/vb/03,04,usb,yes,27,30 2006.162.08:22:33.61/vb/04,04,usb,yes,27,28 2006.162.08:22:33.61/vb/05,04,usb,yes,26,30 2006.162.08:22:33.61/vb/06,04,usb,yes,27,30 2006.162.08:22:33.61/vb/07,04,usb,yes,29,29 2006.162.08:22:33.61/vb/08,04,usb,yes,27,30 2006.162.08:22:33.85/vblo/01,632.99,yes,locked 2006.162.08:22:33.85/vblo/02,640.99,yes,locked 2006.162.08:22:33.85/vblo/03,656.99,yes,locked 2006.162.08:22:33.85/vblo/04,712.99,yes,locked 2006.162.08:22:33.85/vblo/05,744.99,yes,locked 2006.162.08:22:33.85/vblo/06,752.99,yes,locked 2006.162.08:22:33.85/vblo/07,734.99,yes,locked 2006.162.08:22:33.85/vblo/08,744.99,yes,locked 2006.162.08:22:34.00/vabw/8 2006.162.08:22:34.15/vbbw/8 2006.162.08:22:34.24/xfe/off,on,14.5 2006.162.08:22:34.62/ifatt/23,28,28,28 2006.162.08:22:35.08/fmout-gps/S +4.51E-07 2006.162.08:22:35.16:!2006.162.08:23:30 2006.162.08:23:30.00:data_valid=off 2006.162.08:23:30.00:postob 2006.162.08:23:30.09/cable/+6.5367E-03 2006.162.08:23:30.09/wx/17.83,1006.9,100 2006.162.08:23:31.08/fmout-gps/S +4.51E-07 2006.162.08:23:31.08:scan_name=162-0824,k06162,70 2006.162.08:23:31.08:source=1053+815,105811.54,811432.7,2000.0,neutral 2006.162.08:23:31.13#flagr#flagr/antenna,new-source 2006.162.08:23:32.13:checkk5 2006.162.08:23:32.57/chk_autoobs//k5ts1/ autoobs is running! 2006.162.08:23:33.21/chk_autoobs//k5ts2/ autoobs is running! 2006.162.08:23:33.66/chk_autoobs//k5ts3/ autoobs is running! 2006.162.08:23:34.09/chk_autoobs//k5ts4/ autoobs is running! 2006.162.08:23:34.50/chk_obsdata//k5ts1/T1620822??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:23:34.93/chk_obsdata//k5ts2/T1620822??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:23:35.58/chk_obsdata//k5ts3/T1620822??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:23:35.98/chk_obsdata//k5ts4/T1620822??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:23:36.78/k5log//k5ts1_log_newline 2006.162.08:23:37.76/k5log//k5ts2_log_newline 2006.162.08:23:38.51/k5log//k5ts3_log_newline 2006.162.08:23:39.37/k5log//k5ts4_log_newline 2006.162.08:23:39.40/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.08:23:39.40:4f8m12a=3 2006.162.08:23:39.40$4f8m12a/echo=on 2006.162.08:23:39.40$4f8m12a/pcalon 2006.162.08:23:39.40$pcalon/"no phase cal control is implemented here 2006.162.08:23:39.40$4f8m12a/"tpicd=stop 2006.162.08:23:39.40$4f8m12a/vc4f8 2006.162.08:23:39.40$vc4f8/valo=1,532.99 2006.162.08:23:39.40#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.162.08:23:39.40#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.162.08:23:39.40#ibcon#ireg 17 cls_cnt 0 2006.162.08:23:39.40#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:23:39.40#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:23:39.40#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:23:39.40#ibcon#enter wrdev, iclass 39, count 0 2006.162.08:23:39.40#ibcon#first serial, iclass 39, count 0 2006.162.08:23:39.40#ibcon#enter sib2, iclass 39, count 0 2006.162.08:23:39.40#ibcon#flushed, iclass 39, count 0 2006.162.08:23:39.40#ibcon#about to write, iclass 39, count 0 2006.162.08:23:39.40#ibcon#wrote, iclass 39, count 0 2006.162.08:23:39.40#ibcon#about to read 3, iclass 39, count 0 2006.162.08:23:39.44#ibcon#read 3, iclass 39, count 0 2006.162.08:23:39.44#ibcon#about to read 4, iclass 39, count 0 2006.162.08:23:39.44#ibcon#read 4, iclass 39, count 0 2006.162.08:23:39.44#ibcon#about to read 5, iclass 39, count 0 2006.162.08:23:39.44#ibcon#read 5, iclass 39, count 0 2006.162.08:23:39.44#ibcon#about to read 6, iclass 39, count 0 2006.162.08:23:39.44#ibcon#read 6, iclass 39, count 0 2006.162.08:23:39.44#ibcon#end of sib2, iclass 39, count 0 2006.162.08:23:39.44#ibcon#*mode == 0, iclass 39, count 0 2006.162.08:23:39.44#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.162.08:23:39.44#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.08:23:39.44#ibcon#*before write, iclass 39, count 0 2006.162.08:23:39.44#ibcon#enter sib2, iclass 39, count 0 2006.162.08:23:39.44#ibcon#flushed, iclass 39, count 0 2006.162.08:23:39.44#ibcon#about to write, iclass 39, count 0 2006.162.08:23:39.44#ibcon#wrote, iclass 39, count 0 2006.162.08:23:39.44#ibcon#about to read 3, iclass 39, count 0 2006.162.08:23:39.49#ibcon#read 3, iclass 39, count 0 2006.162.08:23:39.49#ibcon#about to read 4, iclass 39, count 0 2006.162.08:23:39.49#ibcon#read 4, iclass 39, count 0 2006.162.08:23:39.49#ibcon#about to read 5, iclass 39, count 0 2006.162.08:23:39.49#ibcon#read 5, iclass 39, count 0 2006.162.08:23:39.49#ibcon#about to read 6, iclass 39, count 0 2006.162.08:23:39.49#ibcon#read 6, iclass 39, count 0 2006.162.08:23:39.49#ibcon#end of sib2, iclass 39, count 0 2006.162.08:23:39.49#ibcon#*after write, iclass 39, count 0 2006.162.08:23:39.49#ibcon#*before return 0, iclass 39, count 0 2006.162.08:23:39.49#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:23:39.49#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:23:39.49#ibcon#about to clear, iclass 39 cls_cnt 0 2006.162.08:23:39.49#ibcon#cleared, iclass 39 cls_cnt 0 2006.162.08:23:39.49$vc4f8/va=1,8 2006.162.08:23:39.49#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.162.08:23:39.49#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.162.08:23:39.49#ibcon#ireg 11 cls_cnt 2 2006.162.08:23:39.49#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:23:39.49#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:23:39.49#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:23:39.49#ibcon#enter wrdev, iclass 3, count 2 2006.162.08:23:39.49#ibcon#first serial, iclass 3, count 2 2006.162.08:23:39.49#ibcon#enter sib2, iclass 3, count 2 2006.162.08:23:39.49#ibcon#flushed, iclass 3, count 2 2006.162.08:23:39.49#ibcon#about to write, iclass 3, count 2 2006.162.08:23:39.49#ibcon#wrote, iclass 3, count 2 2006.162.08:23:39.49#ibcon#about to read 3, iclass 3, count 2 2006.162.08:23:39.51#ibcon#read 3, iclass 3, count 2 2006.162.08:23:39.51#ibcon#about to read 4, iclass 3, count 2 2006.162.08:23:39.51#ibcon#read 4, iclass 3, count 2 2006.162.08:23:39.51#ibcon#about to read 5, iclass 3, count 2 2006.162.08:23:39.51#ibcon#read 5, iclass 3, count 2 2006.162.08:23:39.51#ibcon#about to read 6, iclass 3, count 2 2006.162.08:23:39.51#ibcon#read 6, iclass 3, count 2 2006.162.08:23:39.51#ibcon#end of sib2, iclass 3, count 2 2006.162.08:23:39.51#ibcon#*mode == 0, iclass 3, count 2 2006.162.08:23:39.51#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.162.08:23:39.51#ibcon#[25=AT01-08\r\n] 2006.162.08:23:39.51#ibcon#*before write, iclass 3, count 2 2006.162.08:23:39.51#ibcon#enter sib2, iclass 3, count 2 2006.162.08:23:39.51#ibcon#flushed, iclass 3, count 2 2006.162.08:23:39.51#ibcon#about to write, iclass 3, count 2 2006.162.08:23:39.51#ibcon#wrote, iclass 3, count 2 2006.162.08:23:39.51#ibcon#about to read 3, iclass 3, count 2 2006.162.08:23:39.54#ibcon#read 3, iclass 3, count 2 2006.162.08:23:39.54#ibcon#about to read 4, iclass 3, count 2 2006.162.08:23:39.54#ibcon#read 4, iclass 3, count 2 2006.162.08:23:39.54#ibcon#about to read 5, iclass 3, count 2 2006.162.08:23:39.54#ibcon#read 5, iclass 3, count 2 2006.162.08:23:39.54#ibcon#about to read 6, iclass 3, count 2 2006.162.08:23:39.54#ibcon#read 6, iclass 3, count 2 2006.162.08:23:39.54#ibcon#end of sib2, iclass 3, count 2 2006.162.08:23:39.54#ibcon#*after write, iclass 3, count 2 2006.162.08:23:39.54#ibcon#*before return 0, iclass 3, count 2 2006.162.08:23:39.54#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:23:39.54#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:23:39.54#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.162.08:23:39.54#ibcon#ireg 7 cls_cnt 0 2006.162.08:23:39.54#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:23:39.66#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:23:39.66#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:23:39.66#ibcon#enter wrdev, iclass 3, count 0 2006.162.08:23:39.66#ibcon#first serial, iclass 3, count 0 2006.162.08:23:39.66#ibcon#enter sib2, iclass 3, count 0 2006.162.08:23:39.66#ibcon#flushed, iclass 3, count 0 2006.162.08:23:39.66#ibcon#about to write, iclass 3, count 0 2006.162.08:23:39.66#ibcon#wrote, iclass 3, count 0 2006.162.08:23:39.66#ibcon#about to read 3, iclass 3, count 0 2006.162.08:23:39.68#ibcon#read 3, iclass 3, count 0 2006.162.08:23:39.68#ibcon#about to read 4, iclass 3, count 0 2006.162.08:23:39.68#ibcon#read 4, iclass 3, count 0 2006.162.08:23:39.68#ibcon#about to read 5, iclass 3, count 0 2006.162.08:23:39.68#ibcon#read 5, iclass 3, count 0 2006.162.08:23:39.68#ibcon#about to read 6, iclass 3, count 0 2006.162.08:23:39.68#ibcon#read 6, iclass 3, count 0 2006.162.08:23:39.68#ibcon#end of sib2, iclass 3, count 0 2006.162.08:23:39.68#ibcon#*mode == 0, iclass 3, count 0 2006.162.08:23:39.68#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.162.08:23:39.68#ibcon#[25=USB\r\n] 2006.162.08:23:39.68#ibcon#*before write, iclass 3, count 0 2006.162.08:23:39.68#ibcon#enter sib2, iclass 3, count 0 2006.162.08:23:39.68#ibcon#flushed, iclass 3, count 0 2006.162.08:23:39.68#ibcon#about to write, iclass 3, count 0 2006.162.08:23:39.68#ibcon#wrote, iclass 3, count 0 2006.162.08:23:39.68#ibcon#about to read 3, iclass 3, count 0 2006.162.08:23:39.71#ibcon#read 3, iclass 3, count 0 2006.162.08:23:39.71#ibcon#about to read 4, iclass 3, count 0 2006.162.08:23:39.71#ibcon#read 4, iclass 3, count 0 2006.162.08:23:39.71#ibcon#about to read 5, iclass 3, count 0 2006.162.08:23:39.71#ibcon#read 5, iclass 3, count 0 2006.162.08:23:39.71#ibcon#about to read 6, iclass 3, count 0 2006.162.08:23:39.71#ibcon#read 6, iclass 3, count 0 2006.162.08:23:39.71#ibcon#end of sib2, iclass 3, count 0 2006.162.08:23:39.71#ibcon#*after write, iclass 3, count 0 2006.162.08:23:39.71#ibcon#*before return 0, iclass 3, count 0 2006.162.08:23:39.71#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:23:39.71#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:23:39.71#ibcon#about to clear, iclass 3 cls_cnt 0 2006.162.08:23:39.71#ibcon#cleared, iclass 3 cls_cnt 0 2006.162.08:23:39.71$vc4f8/valo=2,572.99 2006.162.08:23:39.71#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.162.08:23:39.71#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.162.08:23:39.71#ibcon#ireg 17 cls_cnt 0 2006.162.08:23:39.71#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:23:39.71#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:23:39.71#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:23:39.71#ibcon#enter wrdev, iclass 5, count 0 2006.162.08:23:39.71#ibcon#first serial, iclass 5, count 0 2006.162.08:23:39.71#ibcon#enter sib2, iclass 5, count 0 2006.162.08:23:39.71#ibcon#flushed, iclass 5, count 0 2006.162.08:23:39.71#ibcon#about to write, iclass 5, count 0 2006.162.08:23:39.71#ibcon#wrote, iclass 5, count 0 2006.162.08:23:39.71#ibcon#about to read 3, iclass 5, count 0 2006.162.08:23:39.73#ibcon#read 3, iclass 5, count 0 2006.162.08:23:39.73#ibcon#about to read 4, iclass 5, count 0 2006.162.08:23:39.73#ibcon#read 4, iclass 5, count 0 2006.162.08:23:39.73#ibcon#about to read 5, iclass 5, count 0 2006.162.08:23:39.73#ibcon#read 5, iclass 5, count 0 2006.162.08:23:39.73#ibcon#about to read 6, iclass 5, count 0 2006.162.08:23:39.73#ibcon#read 6, iclass 5, count 0 2006.162.08:23:39.73#ibcon#end of sib2, iclass 5, count 0 2006.162.08:23:39.73#ibcon#*mode == 0, iclass 5, count 0 2006.162.08:23:39.73#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.162.08:23:39.73#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.08:23:39.73#ibcon#*before write, iclass 5, count 0 2006.162.08:23:39.73#ibcon#enter sib2, iclass 5, count 0 2006.162.08:23:39.73#ibcon#flushed, iclass 5, count 0 2006.162.08:23:39.73#ibcon#about to write, iclass 5, count 0 2006.162.08:23:39.73#ibcon#wrote, iclass 5, count 0 2006.162.08:23:39.73#ibcon#about to read 3, iclass 5, count 0 2006.162.08:23:39.77#ibcon#read 3, iclass 5, count 0 2006.162.08:23:39.77#ibcon#about to read 4, iclass 5, count 0 2006.162.08:23:39.77#ibcon#read 4, iclass 5, count 0 2006.162.08:23:39.77#ibcon#about to read 5, iclass 5, count 0 2006.162.08:23:39.77#ibcon#read 5, iclass 5, count 0 2006.162.08:23:39.77#ibcon#about to read 6, iclass 5, count 0 2006.162.08:23:39.77#ibcon#read 6, iclass 5, count 0 2006.162.08:23:39.77#ibcon#end of sib2, iclass 5, count 0 2006.162.08:23:39.77#ibcon#*after write, iclass 5, count 0 2006.162.08:23:39.77#ibcon#*before return 0, iclass 5, count 0 2006.162.08:23:39.77#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:23:39.77#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:23:39.77#ibcon#about to clear, iclass 5 cls_cnt 0 2006.162.08:23:39.77#ibcon#cleared, iclass 5 cls_cnt 0 2006.162.08:23:39.77$vc4f8/va=2,7 2006.162.08:23:39.77#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.162.08:23:39.77#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.162.08:23:39.77#ibcon#ireg 11 cls_cnt 2 2006.162.08:23:39.77#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:23:39.83#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:23:39.83#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:23:39.83#ibcon#enter wrdev, iclass 7, count 2 2006.162.08:23:39.83#ibcon#first serial, iclass 7, count 2 2006.162.08:23:39.83#ibcon#enter sib2, iclass 7, count 2 2006.162.08:23:39.83#ibcon#flushed, iclass 7, count 2 2006.162.08:23:39.83#ibcon#about to write, iclass 7, count 2 2006.162.08:23:39.83#ibcon#wrote, iclass 7, count 2 2006.162.08:23:39.83#ibcon#about to read 3, iclass 7, count 2 2006.162.08:23:39.85#ibcon#read 3, iclass 7, count 2 2006.162.08:23:39.85#ibcon#about to read 4, iclass 7, count 2 2006.162.08:23:39.85#ibcon#read 4, iclass 7, count 2 2006.162.08:23:39.85#ibcon#about to read 5, iclass 7, count 2 2006.162.08:23:39.85#ibcon#read 5, iclass 7, count 2 2006.162.08:23:39.85#ibcon#about to read 6, iclass 7, count 2 2006.162.08:23:39.85#ibcon#read 6, iclass 7, count 2 2006.162.08:23:39.85#ibcon#end of sib2, iclass 7, count 2 2006.162.08:23:39.85#ibcon#*mode == 0, iclass 7, count 2 2006.162.08:23:39.85#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.162.08:23:39.85#ibcon#[25=AT02-07\r\n] 2006.162.08:23:39.85#ibcon#*before write, iclass 7, count 2 2006.162.08:23:39.85#ibcon#enter sib2, iclass 7, count 2 2006.162.08:23:39.85#ibcon#flushed, iclass 7, count 2 2006.162.08:23:39.85#ibcon#about to write, iclass 7, count 2 2006.162.08:23:39.85#ibcon#wrote, iclass 7, count 2 2006.162.08:23:39.85#ibcon#about to read 3, iclass 7, count 2 2006.162.08:23:39.89#ibcon#read 3, iclass 7, count 2 2006.162.08:23:39.89#ibcon#about to read 4, iclass 7, count 2 2006.162.08:23:39.89#ibcon#read 4, iclass 7, count 2 2006.162.08:23:39.89#ibcon#about to read 5, iclass 7, count 2 2006.162.08:23:39.89#ibcon#read 5, iclass 7, count 2 2006.162.08:23:39.89#ibcon#about to read 6, iclass 7, count 2 2006.162.08:23:39.89#ibcon#read 6, iclass 7, count 2 2006.162.08:23:39.89#ibcon#end of sib2, iclass 7, count 2 2006.162.08:23:39.89#ibcon#*after write, iclass 7, count 2 2006.162.08:23:39.89#ibcon#*before return 0, iclass 7, count 2 2006.162.08:23:39.89#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:23:39.89#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:23:39.89#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.162.08:23:39.89#ibcon#ireg 7 cls_cnt 0 2006.162.08:23:39.89#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:23:40.01#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:23:40.01#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:23:40.01#ibcon#enter wrdev, iclass 7, count 0 2006.162.08:23:40.01#ibcon#first serial, iclass 7, count 0 2006.162.08:23:40.01#ibcon#enter sib2, iclass 7, count 0 2006.162.08:23:40.01#ibcon#flushed, iclass 7, count 0 2006.162.08:23:40.01#ibcon#about to write, iclass 7, count 0 2006.162.08:23:40.01#ibcon#wrote, iclass 7, count 0 2006.162.08:23:40.01#ibcon#about to read 3, iclass 7, count 0 2006.162.08:23:40.03#ibcon#read 3, iclass 7, count 0 2006.162.08:23:40.03#ibcon#about to read 4, iclass 7, count 0 2006.162.08:23:40.03#ibcon#read 4, iclass 7, count 0 2006.162.08:23:40.03#ibcon#about to read 5, iclass 7, count 0 2006.162.08:23:40.03#ibcon#read 5, iclass 7, count 0 2006.162.08:23:40.03#ibcon#about to read 6, iclass 7, count 0 2006.162.08:23:40.03#ibcon#read 6, iclass 7, count 0 2006.162.08:23:40.03#ibcon#end of sib2, iclass 7, count 0 2006.162.08:23:40.03#ibcon#*mode == 0, iclass 7, count 0 2006.162.08:23:40.03#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.162.08:23:40.03#ibcon#[25=USB\r\n] 2006.162.08:23:40.03#ibcon#*before write, iclass 7, count 0 2006.162.08:23:40.03#ibcon#enter sib2, iclass 7, count 0 2006.162.08:23:40.03#ibcon#flushed, iclass 7, count 0 2006.162.08:23:40.03#ibcon#about to write, iclass 7, count 0 2006.162.08:23:40.03#ibcon#wrote, iclass 7, count 0 2006.162.08:23:40.03#ibcon#about to read 3, iclass 7, count 0 2006.162.08:23:40.06#ibcon#read 3, iclass 7, count 0 2006.162.08:23:40.06#ibcon#about to read 4, iclass 7, count 0 2006.162.08:23:40.06#ibcon#read 4, iclass 7, count 0 2006.162.08:23:40.06#ibcon#about to read 5, iclass 7, count 0 2006.162.08:23:40.06#ibcon#read 5, iclass 7, count 0 2006.162.08:23:40.06#ibcon#about to read 6, iclass 7, count 0 2006.162.08:23:40.06#ibcon#read 6, iclass 7, count 0 2006.162.08:23:40.06#ibcon#end of sib2, iclass 7, count 0 2006.162.08:23:40.06#ibcon#*after write, iclass 7, count 0 2006.162.08:23:40.06#ibcon#*before return 0, iclass 7, count 0 2006.162.08:23:40.06#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:23:40.06#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:23:40.06#ibcon#about to clear, iclass 7 cls_cnt 0 2006.162.08:23:40.06#ibcon#cleared, iclass 7 cls_cnt 0 2006.162.08:23:40.06$vc4f8/valo=3,672.99 2006.162.08:23:40.06#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.162.08:23:40.06#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.162.08:23:40.06#ibcon#ireg 17 cls_cnt 0 2006.162.08:23:40.06#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:23:40.06#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:23:40.06#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:23:40.06#ibcon#enter wrdev, iclass 11, count 0 2006.162.08:23:40.06#ibcon#first serial, iclass 11, count 0 2006.162.08:23:40.06#ibcon#enter sib2, iclass 11, count 0 2006.162.08:23:40.06#ibcon#flushed, iclass 11, count 0 2006.162.08:23:40.06#ibcon#about to write, iclass 11, count 0 2006.162.08:23:40.06#ibcon#wrote, iclass 11, count 0 2006.162.08:23:40.06#ibcon#about to read 3, iclass 11, count 0 2006.162.08:23:40.08#ibcon#read 3, iclass 11, count 0 2006.162.08:23:40.08#ibcon#about to read 4, iclass 11, count 0 2006.162.08:23:40.08#ibcon#read 4, iclass 11, count 0 2006.162.08:23:40.08#ibcon#about to read 5, iclass 11, count 0 2006.162.08:23:40.08#ibcon#read 5, iclass 11, count 0 2006.162.08:23:40.08#ibcon#about to read 6, iclass 11, count 0 2006.162.08:23:40.08#ibcon#read 6, iclass 11, count 0 2006.162.08:23:40.08#ibcon#end of sib2, iclass 11, count 0 2006.162.08:23:40.08#ibcon#*mode == 0, iclass 11, count 0 2006.162.08:23:40.08#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.162.08:23:40.08#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.08:23:40.08#ibcon#*before write, iclass 11, count 0 2006.162.08:23:40.08#ibcon#enter sib2, iclass 11, count 0 2006.162.08:23:40.08#ibcon#flushed, iclass 11, count 0 2006.162.08:23:40.08#ibcon#about to write, iclass 11, count 0 2006.162.08:23:40.08#ibcon#wrote, iclass 11, count 0 2006.162.08:23:40.08#ibcon#about to read 3, iclass 11, count 0 2006.162.08:23:40.12#ibcon#read 3, iclass 11, count 0 2006.162.08:23:40.12#ibcon#about to read 4, iclass 11, count 0 2006.162.08:23:40.12#ibcon#read 4, iclass 11, count 0 2006.162.08:23:40.12#ibcon#about to read 5, iclass 11, count 0 2006.162.08:23:40.12#ibcon#read 5, iclass 11, count 0 2006.162.08:23:40.12#ibcon#about to read 6, iclass 11, count 0 2006.162.08:23:40.12#ibcon#read 6, iclass 11, count 0 2006.162.08:23:40.12#ibcon#end of sib2, iclass 11, count 0 2006.162.08:23:40.12#ibcon#*after write, iclass 11, count 0 2006.162.08:23:40.12#ibcon#*before return 0, iclass 11, count 0 2006.162.08:23:40.12#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:23:40.12#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:23:40.12#ibcon#about to clear, iclass 11 cls_cnt 0 2006.162.08:23:40.12#ibcon#cleared, iclass 11 cls_cnt 0 2006.162.08:23:40.12$vc4f8/va=3,6 2006.162.08:23:40.12#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.162.08:23:40.12#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.162.08:23:40.12#ibcon#ireg 11 cls_cnt 2 2006.162.08:23:40.12#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:23:40.18#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:23:40.18#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:23:40.18#ibcon#enter wrdev, iclass 13, count 2 2006.162.08:23:40.18#ibcon#first serial, iclass 13, count 2 2006.162.08:23:40.18#ibcon#enter sib2, iclass 13, count 2 2006.162.08:23:40.18#ibcon#flushed, iclass 13, count 2 2006.162.08:23:40.18#ibcon#about to write, iclass 13, count 2 2006.162.08:23:40.18#ibcon#wrote, iclass 13, count 2 2006.162.08:23:40.18#ibcon#about to read 3, iclass 13, count 2 2006.162.08:23:40.20#ibcon#read 3, iclass 13, count 2 2006.162.08:23:40.20#ibcon#about to read 4, iclass 13, count 2 2006.162.08:23:40.20#ibcon#read 4, iclass 13, count 2 2006.162.08:23:40.20#ibcon#about to read 5, iclass 13, count 2 2006.162.08:23:40.20#ibcon#read 5, iclass 13, count 2 2006.162.08:23:40.20#ibcon#about to read 6, iclass 13, count 2 2006.162.08:23:40.20#ibcon#read 6, iclass 13, count 2 2006.162.08:23:40.20#ibcon#end of sib2, iclass 13, count 2 2006.162.08:23:40.20#ibcon#*mode == 0, iclass 13, count 2 2006.162.08:23:40.20#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.162.08:23:40.20#ibcon#[25=AT03-06\r\n] 2006.162.08:23:40.20#ibcon#*before write, iclass 13, count 2 2006.162.08:23:40.20#ibcon#enter sib2, iclass 13, count 2 2006.162.08:23:40.20#ibcon#flushed, iclass 13, count 2 2006.162.08:23:40.20#ibcon#about to write, iclass 13, count 2 2006.162.08:23:40.20#ibcon#wrote, iclass 13, count 2 2006.162.08:23:40.20#ibcon#about to read 3, iclass 13, count 2 2006.162.08:23:40.23#ibcon#read 3, iclass 13, count 2 2006.162.08:23:40.23#ibcon#about to read 4, iclass 13, count 2 2006.162.08:23:40.23#ibcon#read 4, iclass 13, count 2 2006.162.08:23:40.23#ibcon#about to read 5, iclass 13, count 2 2006.162.08:23:40.23#ibcon#read 5, iclass 13, count 2 2006.162.08:23:40.23#ibcon#about to read 6, iclass 13, count 2 2006.162.08:23:40.23#ibcon#read 6, iclass 13, count 2 2006.162.08:23:40.23#ibcon#end of sib2, iclass 13, count 2 2006.162.08:23:40.23#ibcon#*after write, iclass 13, count 2 2006.162.08:23:40.23#ibcon#*before return 0, iclass 13, count 2 2006.162.08:23:40.23#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:23:40.23#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:23:40.23#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.162.08:23:40.23#ibcon#ireg 7 cls_cnt 0 2006.162.08:23:40.23#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:23:40.35#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:23:40.35#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:23:40.35#ibcon#enter wrdev, iclass 13, count 0 2006.162.08:23:40.35#ibcon#first serial, iclass 13, count 0 2006.162.08:23:40.35#ibcon#enter sib2, iclass 13, count 0 2006.162.08:23:40.35#ibcon#flushed, iclass 13, count 0 2006.162.08:23:40.35#ibcon#about to write, iclass 13, count 0 2006.162.08:23:40.35#ibcon#wrote, iclass 13, count 0 2006.162.08:23:40.35#ibcon#about to read 3, iclass 13, count 0 2006.162.08:23:40.37#ibcon#read 3, iclass 13, count 0 2006.162.08:23:40.37#ibcon#about to read 4, iclass 13, count 0 2006.162.08:23:40.37#ibcon#read 4, iclass 13, count 0 2006.162.08:23:40.37#ibcon#about to read 5, iclass 13, count 0 2006.162.08:23:40.37#ibcon#read 5, iclass 13, count 0 2006.162.08:23:40.37#ibcon#about to read 6, iclass 13, count 0 2006.162.08:23:40.37#ibcon#read 6, iclass 13, count 0 2006.162.08:23:40.37#ibcon#end of sib2, iclass 13, count 0 2006.162.08:23:40.37#ibcon#*mode == 0, iclass 13, count 0 2006.162.08:23:40.37#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.162.08:23:40.37#ibcon#[25=USB\r\n] 2006.162.08:23:40.37#ibcon#*before write, iclass 13, count 0 2006.162.08:23:40.37#ibcon#enter sib2, iclass 13, count 0 2006.162.08:23:40.37#ibcon#flushed, iclass 13, count 0 2006.162.08:23:40.37#ibcon#about to write, iclass 13, count 0 2006.162.08:23:40.37#ibcon#wrote, iclass 13, count 0 2006.162.08:23:40.37#ibcon#about to read 3, iclass 13, count 0 2006.162.08:23:40.40#ibcon#read 3, iclass 13, count 0 2006.162.08:23:40.40#ibcon#about to read 4, iclass 13, count 0 2006.162.08:23:40.40#ibcon#read 4, iclass 13, count 0 2006.162.08:23:40.40#ibcon#about to read 5, iclass 13, count 0 2006.162.08:23:40.40#ibcon#read 5, iclass 13, count 0 2006.162.08:23:40.40#ibcon#about to read 6, iclass 13, count 0 2006.162.08:23:40.40#ibcon#read 6, iclass 13, count 0 2006.162.08:23:40.40#ibcon#end of sib2, iclass 13, count 0 2006.162.08:23:40.40#ibcon#*after write, iclass 13, count 0 2006.162.08:23:40.40#ibcon#*before return 0, iclass 13, count 0 2006.162.08:23:40.40#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:23:40.40#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:23:40.40#ibcon#about to clear, iclass 13 cls_cnt 0 2006.162.08:23:40.40#ibcon#cleared, iclass 13 cls_cnt 0 2006.162.08:23:40.40$vc4f8/valo=4,832.99 2006.162.08:23:40.40#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.162.08:23:40.40#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.162.08:23:40.40#ibcon#ireg 17 cls_cnt 0 2006.162.08:23:40.40#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:23:40.40#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:23:40.40#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:23:40.40#ibcon#enter wrdev, iclass 15, count 0 2006.162.08:23:40.40#ibcon#first serial, iclass 15, count 0 2006.162.08:23:40.40#ibcon#enter sib2, iclass 15, count 0 2006.162.08:23:40.40#ibcon#flushed, iclass 15, count 0 2006.162.08:23:40.40#ibcon#about to write, iclass 15, count 0 2006.162.08:23:40.40#ibcon#wrote, iclass 15, count 0 2006.162.08:23:40.40#ibcon#about to read 3, iclass 15, count 0 2006.162.08:23:40.42#ibcon#read 3, iclass 15, count 0 2006.162.08:23:40.42#ibcon#about to read 4, iclass 15, count 0 2006.162.08:23:40.42#ibcon#read 4, iclass 15, count 0 2006.162.08:23:40.42#ibcon#about to read 5, iclass 15, count 0 2006.162.08:23:40.42#ibcon#read 5, iclass 15, count 0 2006.162.08:23:40.42#ibcon#about to read 6, iclass 15, count 0 2006.162.08:23:40.42#ibcon#read 6, iclass 15, count 0 2006.162.08:23:40.42#ibcon#end of sib2, iclass 15, count 0 2006.162.08:23:40.42#ibcon#*mode == 0, iclass 15, count 0 2006.162.08:23:40.42#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.162.08:23:40.42#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.08:23:40.42#ibcon#*before write, iclass 15, count 0 2006.162.08:23:40.42#ibcon#enter sib2, iclass 15, count 0 2006.162.08:23:40.42#ibcon#flushed, iclass 15, count 0 2006.162.08:23:40.42#ibcon#about to write, iclass 15, count 0 2006.162.08:23:40.42#ibcon#wrote, iclass 15, count 0 2006.162.08:23:40.42#ibcon#about to read 3, iclass 15, count 0 2006.162.08:23:40.46#ibcon#read 3, iclass 15, count 0 2006.162.08:23:40.46#ibcon#about to read 4, iclass 15, count 0 2006.162.08:23:40.46#ibcon#read 4, iclass 15, count 0 2006.162.08:23:40.46#ibcon#about to read 5, iclass 15, count 0 2006.162.08:23:40.46#ibcon#read 5, iclass 15, count 0 2006.162.08:23:40.46#ibcon#about to read 6, iclass 15, count 0 2006.162.08:23:40.46#ibcon#read 6, iclass 15, count 0 2006.162.08:23:40.46#ibcon#end of sib2, iclass 15, count 0 2006.162.08:23:40.46#ibcon#*after write, iclass 15, count 0 2006.162.08:23:40.46#ibcon#*before return 0, iclass 15, count 0 2006.162.08:23:40.46#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:23:40.46#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:23:40.46#ibcon#about to clear, iclass 15 cls_cnt 0 2006.162.08:23:40.46#ibcon#cleared, iclass 15 cls_cnt 0 2006.162.08:23:40.46$vc4f8/va=4,7 2006.162.08:23:40.46#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.162.08:23:40.46#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.162.08:23:40.46#ibcon#ireg 11 cls_cnt 2 2006.162.08:23:40.46#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:23:40.52#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:23:40.52#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:23:40.52#ibcon#enter wrdev, iclass 17, count 2 2006.162.08:23:40.52#ibcon#first serial, iclass 17, count 2 2006.162.08:23:40.52#ibcon#enter sib2, iclass 17, count 2 2006.162.08:23:40.52#ibcon#flushed, iclass 17, count 2 2006.162.08:23:40.52#ibcon#about to write, iclass 17, count 2 2006.162.08:23:40.52#ibcon#wrote, iclass 17, count 2 2006.162.08:23:40.52#ibcon#about to read 3, iclass 17, count 2 2006.162.08:23:40.54#ibcon#read 3, iclass 17, count 2 2006.162.08:23:40.54#ibcon#about to read 4, iclass 17, count 2 2006.162.08:23:40.54#ibcon#read 4, iclass 17, count 2 2006.162.08:23:40.54#ibcon#about to read 5, iclass 17, count 2 2006.162.08:23:40.54#ibcon#read 5, iclass 17, count 2 2006.162.08:23:40.54#ibcon#about to read 6, iclass 17, count 2 2006.162.08:23:40.54#ibcon#read 6, iclass 17, count 2 2006.162.08:23:40.54#ibcon#end of sib2, iclass 17, count 2 2006.162.08:23:40.54#ibcon#*mode == 0, iclass 17, count 2 2006.162.08:23:40.54#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.162.08:23:40.54#ibcon#[25=AT04-07\r\n] 2006.162.08:23:40.54#ibcon#*before write, iclass 17, count 2 2006.162.08:23:40.54#ibcon#enter sib2, iclass 17, count 2 2006.162.08:23:40.54#ibcon#flushed, iclass 17, count 2 2006.162.08:23:40.54#ibcon#about to write, iclass 17, count 2 2006.162.08:23:40.54#ibcon#wrote, iclass 17, count 2 2006.162.08:23:40.54#ibcon#about to read 3, iclass 17, count 2 2006.162.08:23:40.57#ibcon#read 3, iclass 17, count 2 2006.162.08:23:40.57#ibcon#about to read 4, iclass 17, count 2 2006.162.08:23:40.57#ibcon#read 4, iclass 17, count 2 2006.162.08:23:40.57#ibcon#about to read 5, iclass 17, count 2 2006.162.08:23:40.57#ibcon#read 5, iclass 17, count 2 2006.162.08:23:40.57#ibcon#about to read 6, iclass 17, count 2 2006.162.08:23:40.57#ibcon#read 6, iclass 17, count 2 2006.162.08:23:40.57#ibcon#end of sib2, iclass 17, count 2 2006.162.08:23:40.57#ibcon#*after write, iclass 17, count 2 2006.162.08:23:40.57#ibcon#*before return 0, iclass 17, count 2 2006.162.08:23:40.57#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:23:40.57#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:23:40.57#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.162.08:23:40.57#ibcon#ireg 7 cls_cnt 0 2006.162.08:23:40.57#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:23:40.69#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:23:40.69#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:23:40.69#ibcon#enter wrdev, iclass 17, count 0 2006.162.08:23:40.69#ibcon#first serial, iclass 17, count 0 2006.162.08:23:40.69#ibcon#enter sib2, iclass 17, count 0 2006.162.08:23:40.69#ibcon#flushed, iclass 17, count 0 2006.162.08:23:40.69#ibcon#about to write, iclass 17, count 0 2006.162.08:23:40.69#ibcon#wrote, iclass 17, count 0 2006.162.08:23:40.69#ibcon#about to read 3, iclass 17, count 0 2006.162.08:23:40.71#ibcon#read 3, iclass 17, count 0 2006.162.08:23:40.71#ibcon#about to read 4, iclass 17, count 0 2006.162.08:23:40.71#ibcon#read 4, iclass 17, count 0 2006.162.08:23:40.71#ibcon#about to read 5, iclass 17, count 0 2006.162.08:23:40.71#ibcon#read 5, iclass 17, count 0 2006.162.08:23:40.71#ibcon#about to read 6, iclass 17, count 0 2006.162.08:23:40.71#ibcon#read 6, iclass 17, count 0 2006.162.08:23:40.71#ibcon#end of sib2, iclass 17, count 0 2006.162.08:23:40.71#ibcon#*mode == 0, iclass 17, count 0 2006.162.08:23:40.71#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.162.08:23:40.71#ibcon#[25=USB\r\n] 2006.162.08:23:40.71#ibcon#*before write, iclass 17, count 0 2006.162.08:23:40.71#ibcon#enter sib2, iclass 17, count 0 2006.162.08:23:40.71#ibcon#flushed, iclass 17, count 0 2006.162.08:23:40.71#ibcon#about to write, iclass 17, count 0 2006.162.08:23:40.71#ibcon#wrote, iclass 17, count 0 2006.162.08:23:40.71#ibcon#about to read 3, iclass 17, count 0 2006.162.08:23:40.74#ibcon#read 3, iclass 17, count 0 2006.162.08:23:40.74#ibcon#about to read 4, iclass 17, count 0 2006.162.08:23:40.74#ibcon#read 4, iclass 17, count 0 2006.162.08:23:40.74#ibcon#about to read 5, iclass 17, count 0 2006.162.08:23:40.74#ibcon#read 5, iclass 17, count 0 2006.162.08:23:40.74#ibcon#about to read 6, iclass 17, count 0 2006.162.08:23:40.74#ibcon#read 6, iclass 17, count 0 2006.162.08:23:40.74#ibcon#end of sib2, iclass 17, count 0 2006.162.08:23:40.74#ibcon#*after write, iclass 17, count 0 2006.162.08:23:40.74#ibcon#*before return 0, iclass 17, count 0 2006.162.08:23:40.74#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:23:40.74#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:23:40.74#ibcon#about to clear, iclass 17 cls_cnt 0 2006.162.08:23:40.74#ibcon#cleared, iclass 17 cls_cnt 0 2006.162.08:23:40.74$vc4f8/valo=5,652.99 2006.162.08:23:40.74#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.162.08:23:40.74#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.162.08:23:40.74#ibcon#ireg 17 cls_cnt 0 2006.162.08:23:40.74#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:23:40.74#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:23:40.74#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:23:40.74#ibcon#enter wrdev, iclass 19, count 0 2006.162.08:23:40.74#ibcon#first serial, iclass 19, count 0 2006.162.08:23:40.74#ibcon#enter sib2, iclass 19, count 0 2006.162.08:23:40.74#ibcon#flushed, iclass 19, count 0 2006.162.08:23:40.74#ibcon#about to write, iclass 19, count 0 2006.162.08:23:40.74#ibcon#wrote, iclass 19, count 0 2006.162.08:23:40.74#ibcon#about to read 3, iclass 19, count 0 2006.162.08:23:40.76#ibcon#read 3, iclass 19, count 0 2006.162.08:23:40.76#ibcon#about to read 4, iclass 19, count 0 2006.162.08:23:40.76#ibcon#read 4, iclass 19, count 0 2006.162.08:23:40.76#ibcon#about to read 5, iclass 19, count 0 2006.162.08:23:40.76#ibcon#read 5, iclass 19, count 0 2006.162.08:23:40.76#ibcon#about to read 6, iclass 19, count 0 2006.162.08:23:40.76#ibcon#read 6, iclass 19, count 0 2006.162.08:23:40.76#ibcon#end of sib2, iclass 19, count 0 2006.162.08:23:40.76#ibcon#*mode == 0, iclass 19, count 0 2006.162.08:23:40.76#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.162.08:23:40.76#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.08:23:40.76#ibcon#*before write, iclass 19, count 0 2006.162.08:23:40.76#ibcon#enter sib2, iclass 19, count 0 2006.162.08:23:40.76#ibcon#flushed, iclass 19, count 0 2006.162.08:23:40.76#ibcon#about to write, iclass 19, count 0 2006.162.08:23:40.76#ibcon#wrote, iclass 19, count 0 2006.162.08:23:40.76#ibcon#about to read 3, iclass 19, count 0 2006.162.08:23:40.80#ibcon#read 3, iclass 19, count 0 2006.162.08:23:40.80#ibcon#about to read 4, iclass 19, count 0 2006.162.08:23:40.80#ibcon#read 4, iclass 19, count 0 2006.162.08:23:40.80#ibcon#about to read 5, iclass 19, count 0 2006.162.08:23:40.80#ibcon#read 5, iclass 19, count 0 2006.162.08:23:40.80#ibcon#about to read 6, iclass 19, count 0 2006.162.08:23:40.80#ibcon#read 6, iclass 19, count 0 2006.162.08:23:40.80#ibcon#end of sib2, iclass 19, count 0 2006.162.08:23:40.80#ibcon#*after write, iclass 19, count 0 2006.162.08:23:40.80#ibcon#*before return 0, iclass 19, count 0 2006.162.08:23:40.80#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:23:40.80#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:23:40.80#ibcon#about to clear, iclass 19 cls_cnt 0 2006.162.08:23:40.80#ibcon#cleared, iclass 19 cls_cnt 0 2006.162.08:23:40.80$vc4f8/va=5,7 2006.162.08:23:40.80#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.162.08:23:40.80#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.162.08:23:40.80#ibcon#ireg 11 cls_cnt 2 2006.162.08:23:40.80#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.162.08:23:40.86#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.162.08:23:40.86#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.162.08:23:40.86#ibcon#enter wrdev, iclass 21, count 2 2006.162.08:23:40.86#ibcon#first serial, iclass 21, count 2 2006.162.08:23:40.86#ibcon#enter sib2, iclass 21, count 2 2006.162.08:23:40.86#ibcon#flushed, iclass 21, count 2 2006.162.08:23:40.86#ibcon#about to write, iclass 21, count 2 2006.162.08:23:40.86#ibcon#wrote, iclass 21, count 2 2006.162.08:23:40.86#ibcon#about to read 3, iclass 21, count 2 2006.162.08:23:40.88#ibcon#read 3, iclass 21, count 2 2006.162.08:23:40.88#ibcon#about to read 4, iclass 21, count 2 2006.162.08:23:40.88#ibcon#read 4, iclass 21, count 2 2006.162.08:23:40.88#ibcon#about to read 5, iclass 21, count 2 2006.162.08:23:40.88#ibcon#read 5, iclass 21, count 2 2006.162.08:23:40.88#ibcon#about to read 6, iclass 21, count 2 2006.162.08:23:40.88#ibcon#read 6, iclass 21, count 2 2006.162.08:23:40.88#ibcon#end of sib2, iclass 21, count 2 2006.162.08:23:40.88#ibcon#*mode == 0, iclass 21, count 2 2006.162.08:23:40.88#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.162.08:23:40.88#ibcon#[25=AT05-07\r\n] 2006.162.08:23:40.88#ibcon#*before write, iclass 21, count 2 2006.162.08:23:40.88#ibcon#enter sib2, iclass 21, count 2 2006.162.08:23:40.88#ibcon#flushed, iclass 21, count 2 2006.162.08:23:40.88#ibcon#about to write, iclass 21, count 2 2006.162.08:23:40.88#ibcon#wrote, iclass 21, count 2 2006.162.08:23:40.88#ibcon#about to read 3, iclass 21, count 2 2006.162.08:23:40.91#ibcon#read 3, iclass 21, count 2 2006.162.08:23:40.91#ibcon#about to read 4, iclass 21, count 2 2006.162.08:23:40.91#ibcon#read 4, iclass 21, count 2 2006.162.08:23:40.91#ibcon#about to read 5, iclass 21, count 2 2006.162.08:23:40.91#ibcon#read 5, iclass 21, count 2 2006.162.08:23:40.91#ibcon#about to read 6, iclass 21, count 2 2006.162.08:23:40.91#ibcon#read 6, iclass 21, count 2 2006.162.08:23:40.91#ibcon#end of sib2, iclass 21, count 2 2006.162.08:23:40.91#ibcon#*after write, iclass 21, count 2 2006.162.08:23:40.91#ibcon#*before return 0, iclass 21, count 2 2006.162.08:23:40.91#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.162.08:23:40.91#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.162.08:23:40.91#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.162.08:23:40.91#ibcon#ireg 7 cls_cnt 0 2006.162.08:23:40.91#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.162.08:23:41.03#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.162.08:23:41.03#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.162.08:23:41.03#ibcon#enter wrdev, iclass 21, count 0 2006.162.08:23:41.03#ibcon#first serial, iclass 21, count 0 2006.162.08:23:41.03#ibcon#enter sib2, iclass 21, count 0 2006.162.08:23:41.03#ibcon#flushed, iclass 21, count 0 2006.162.08:23:41.03#ibcon#about to write, iclass 21, count 0 2006.162.08:23:41.03#ibcon#wrote, iclass 21, count 0 2006.162.08:23:41.03#ibcon#about to read 3, iclass 21, count 0 2006.162.08:23:41.05#ibcon#read 3, iclass 21, count 0 2006.162.08:23:41.05#ibcon#about to read 4, iclass 21, count 0 2006.162.08:23:41.05#ibcon#read 4, iclass 21, count 0 2006.162.08:23:41.05#ibcon#about to read 5, iclass 21, count 0 2006.162.08:23:41.05#ibcon#read 5, iclass 21, count 0 2006.162.08:23:41.05#ibcon#about to read 6, iclass 21, count 0 2006.162.08:23:41.05#ibcon#read 6, iclass 21, count 0 2006.162.08:23:41.05#ibcon#end of sib2, iclass 21, count 0 2006.162.08:23:41.05#ibcon#*mode == 0, iclass 21, count 0 2006.162.08:23:41.05#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.162.08:23:41.05#ibcon#[25=USB\r\n] 2006.162.08:23:41.05#ibcon#*before write, iclass 21, count 0 2006.162.08:23:41.05#ibcon#enter sib2, iclass 21, count 0 2006.162.08:23:41.05#ibcon#flushed, iclass 21, count 0 2006.162.08:23:41.05#ibcon#about to write, iclass 21, count 0 2006.162.08:23:41.05#ibcon#wrote, iclass 21, count 0 2006.162.08:23:41.05#ibcon#about to read 3, iclass 21, count 0 2006.162.08:23:41.08#ibcon#read 3, iclass 21, count 0 2006.162.08:23:41.08#ibcon#about to read 4, iclass 21, count 0 2006.162.08:23:41.08#ibcon#read 4, iclass 21, count 0 2006.162.08:23:41.08#ibcon#about to read 5, iclass 21, count 0 2006.162.08:23:41.08#ibcon#read 5, iclass 21, count 0 2006.162.08:23:41.08#ibcon#about to read 6, iclass 21, count 0 2006.162.08:23:41.08#ibcon#read 6, iclass 21, count 0 2006.162.08:23:41.08#ibcon#end of sib2, iclass 21, count 0 2006.162.08:23:41.08#ibcon#*after write, iclass 21, count 0 2006.162.08:23:41.08#ibcon#*before return 0, iclass 21, count 0 2006.162.08:23:41.08#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.162.08:23:41.08#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.162.08:23:41.08#ibcon#about to clear, iclass 21 cls_cnt 0 2006.162.08:23:41.08#ibcon#cleared, iclass 21 cls_cnt 0 2006.162.08:23:41.08$vc4f8/valo=6,772.99 2006.162.08:23:41.08#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.162.08:23:41.08#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.162.08:23:41.08#ibcon#ireg 17 cls_cnt 0 2006.162.08:23:41.08#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.162.08:23:41.08#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.162.08:23:41.08#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.162.08:23:41.08#ibcon#enter wrdev, iclass 23, count 0 2006.162.08:23:41.08#ibcon#first serial, iclass 23, count 0 2006.162.08:23:41.08#ibcon#enter sib2, iclass 23, count 0 2006.162.08:23:41.08#ibcon#flushed, iclass 23, count 0 2006.162.08:23:41.08#ibcon#about to write, iclass 23, count 0 2006.162.08:23:41.08#ibcon#wrote, iclass 23, count 0 2006.162.08:23:41.08#ibcon#about to read 3, iclass 23, count 0 2006.162.08:23:41.10#ibcon#read 3, iclass 23, count 0 2006.162.08:23:41.10#ibcon#about to read 4, iclass 23, count 0 2006.162.08:23:41.10#ibcon#read 4, iclass 23, count 0 2006.162.08:23:41.10#ibcon#about to read 5, iclass 23, count 0 2006.162.08:23:41.10#ibcon#read 5, iclass 23, count 0 2006.162.08:23:41.10#ibcon#about to read 6, iclass 23, count 0 2006.162.08:23:41.10#ibcon#read 6, iclass 23, count 0 2006.162.08:23:41.10#ibcon#end of sib2, iclass 23, count 0 2006.162.08:23:41.10#ibcon#*mode == 0, iclass 23, count 0 2006.162.08:23:41.10#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.162.08:23:41.10#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.08:23:41.10#ibcon#*before write, iclass 23, count 0 2006.162.08:23:41.10#ibcon#enter sib2, iclass 23, count 0 2006.162.08:23:41.10#ibcon#flushed, iclass 23, count 0 2006.162.08:23:41.10#ibcon#about to write, iclass 23, count 0 2006.162.08:23:41.10#ibcon#wrote, iclass 23, count 0 2006.162.08:23:41.10#ibcon#about to read 3, iclass 23, count 0 2006.162.08:23:41.14#ibcon#read 3, iclass 23, count 0 2006.162.08:23:41.14#ibcon#about to read 4, iclass 23, count 0 2006.162.08:23:41.14#ibcon#read 4, iclass 23, count 0 2006.162.08:23:41.14#ibcon#about to read 5, iclass 23, count 0 2006.162.08:23:41.14#ibcon#read 5, iclass 23, count 0 2006.162.08:23:41.14#ibcon#about to read 6, iclass 23, count 0 2006.162.08:23:41.14#ibcon#read 6, iclass 23, count 0 2006.162.08:23:41.14#ibcon#end of sib2, iclass 23, count 0 2006.162.08:23:41.14#ibcon#*after write, iclass 23, count 0 2006.162.08:23:41.14#ibcon#*before return 0, iclass 23, count 0 2006.162.08:23:41.14#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.162.08:23:41.14#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.162.08:23:41.14#ibcon#about to clear, iclass 23 cls_cnt 0 2006.162.08:23:41.14#ibcon#cleared, iclass 23 cls_cnt 0 2006.162.08:23:41.14$vc4f8/va=6,6 2006.162.08:23:41.14#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.162.08:23:41.14#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.162.08:23:41.14#ibcon#ireg 11 cls_cnt 2 2006.162.08:23:41.14#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.162.08:23:41.20#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.162.08:23:41.20#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.162.08:23:41.20#ibcon#enter wrdev, iclass 25, count 2 2006.162.08:23:41.20#ibcon#first serial, iclass 25, count 2 2006.162.08:23:41.20#ibcon#enter sib2, iclass 25, count 2 2006.162.08:23:41.20#ibcon#flushed, iclass 25, count 2 2006.162.08:23:41.20#ibcon#about to write, iclass 25, count 2 2006.162.08:23:41.20#ibcon#wrote, iclass 25, count 2 2006.162.08:23:41.20#ibcon#about to read 3, iclass 25, count 2 2006.162.08:23:41.22#ibcon#read 3, iclass 25, count 2 2006.162.08:23:41.22#ibcon#about to read 4, iclass 25, count 2 2006.162.08:23:41.22#ibcon#read 4, iclass 25, count 2 2006.162.08:23:41.22#ibcon#about to read 5, iclass 25, count 2 2006.162.08:23:41.22#ibcon#read 5, iclass 25, count 2 2006.162.08:23:41.22#ibcon#about to read 6, iclass 25, count 2 2006.162.08:23:41.22#ibcon#read 6, iclass 25, count 2 2006.162.08:23:41.22#ibcon#end of sib2, iclass 25, count 2 2006.162.08:23:41.22#ibcon#*mode == 0, iclass 25, count 2 2006.162.08:23:41.22#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.162.08:23:41.22#ibcon#[25=AT06-06\r\n] 2006.162.08:23:41.22#ibcon#*before write, iclass 25, count 2 2006.162.08:23:41.22#ibcon#enter sib2, iclass 25, count 2 2006.162.08:23:41.22#ibcon#flushed, iclass 25, count 2 2006.162.08:23:41.22#ibcon#about to write, iclass 25, count 2 2006.162.08:23:41.22#ibcon#wrote, iclass 25, count 2 2006.162.08:23:41.22#ibcon#about to read 3, iclass 25, count 2 2006.162.08:23:41.25#ibcon#read 3, iclass 25, count 2 2006.162.08:23:41.25#ibcon#about to read 4, iclass 25, count 2 2006.162.08:23:41.25#ibcon#read 4, iclass 25, count 2 2006.162.08:23:41.25#ibcon#about to read 5, iclass 25, count 2 2006.162.08:23:41.25#ibcon#read 5, iclass 25, count 2 2006.162.08:23:41.25#ibcon#about to read 6, iclass 25, count 2 2006.162.08:23:41.25#ibcon#read 6, iclass 25, count 2 2006.162.08:23:41.25#ibcon#end of sib2, iclass 25, count 2 2006.162.08:23:41.25#ibcon#*after write, iclass 25, count 2 2006.162.08:23:41.25#ibcon#*before return 0, iclass 25, count 2 2006.162.08:23:41.25#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.162.08:23:41.25#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.162.08:23:41.25#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.162.08:23:41.25#ibcon#ireg 7 cls_cnt 0 2006.162.08:23:41.25#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.162.08:23:41.37#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.162.08:23:41.37#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.162.08:23:41.37#ibcon#enter wrdev, iclass 25, count 0 2006.162.08:23:41.37#ibcon#first serial, iclass 25, count 0 2006.162.08:23:41.37#ibcon#enter sib2, iclass 25, count 0 2006.162.08:23:41.37#ibcon#flushed, iclass 25, count 0 2006.162.08:23:41.37#ibcon#about to write, iclass 25, count 0 2006.162.08:23:41.37#ibcon#wrote, iclass 25, count 0 2006.162.08:23:41.37#ibcon#about to read 3, iclass 25, count 0 2006.162.08:23:41.39#ibcon#read 3, iclass 25, count 0 2006.162.08:23:41.39#ibcon#about to read 4, iclass 25, count 0 2006.162.08:23:41.39#ibcon#read 4, iclass 25, count 0 2006.162.08:23:41.39#ibcon#about to read 5, iclass 25, count 0 2006.162.08:23:41.39#ibcon#read 5, iclass 25, count 0 2006.162.08:23:41.39#ibcon#about to read 6, iclass 25, count 0 2006.162.08:23:41.39#ibcon#read 6, iclass 25, count 0 2006.162.08:23:41.39#ibcon#end of sib2, iclass 25, count 0 2006.162.08:23:41.39#ibcon#*mode == 0, iclass 25, count 0 2006.162.08:23:41.39#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.162.08:23:41.39#ibcon#[25=USB\r\n] 2006.162.08:23:41.39#ibcon#*before write, iclass 25, count 0 2006.162.08:23:41.39#ibcon#enter sib2, iclass 25, count 0 2006.162.08:23:41.39#ibcon#flushed, iclass 25, count 0 2006.162.08:23:41.39#ibcon#about to write, iclass 25, count 0 2006.162.08:23:41.39#ibcon#wrote, iclass 25, count 0 2006.162.08:23:41.39#ibcon#about to read 3, iclass 25, count 0 2006.162.08:23:41.39#abcon#<5=/03 2.2 4.8 17.831001006.9\r\n> 2006.162.08:23:41.41#abcon#{5=INTERFACE CLEAR} 2006.162.08:23:41.42#ibcon#read 3, iclass 25, count 0 2006.162.08:23:41.42#ibcon#about to read 4, iclass 25, count 0 2006.162.08:23:41.42#ibcon#read 4, iclass 25, count 0 2006.162.08:23:41.42#ibcon#about to read 5, iclass 25, count 0 2006.162.08:23:41.42#ibcon#read 5, iclass 25, count 0 2006.162.08:23:41.42#ibcon#about to read 6, iclass 25, count 0 2006.162.08:23:41.42#ibcon#read 6, iclass 25, count 0 2006.162.08:23:41.42#ibcon#end of sib2, iclass 25, count 0 2006.162.08:23:41.42#ibcon#*after write, iclass 25, count 0 2006.162.08:23:41.42#ibcon#*before return 0, iclass 25, count 0 2006.162.08:23:41.42#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.162.08:23:41.42#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.162.08:23:41.42#ibcon#about to clear, iclass 25 cls_cnt 0 2006.162.08:23:41.42#ibcon#cleared, iclass 25 cls_cnt 0 2006.162.08:23:41.42$vc4f8/valo=7,832.99 2006.162.08:23:41.42#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.162.08:23:41.42#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.162.08:23:41.42#ibcon#ireg 17 cls_cnt 0 2006.162.08:23:41.42#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:23:41.42#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:23:41.42#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:23:41.42#ibcon#enter wrdev, iclass 30, count 0 2006.162.08:23:41.42#ibcon#first serial, iclass 30, count 0 2006.162.08:23:41.42#ibcon#enter sib2, iclass 30, count 0 2006.162.08:23:41.42#ibcon#flushed, iclass 30, count 0 2006.162.08:23:41.42#ibcon#about to write, iclass 30, count 0 2006.162.08:23:41.42#ibcon#wrote, iclass 30, count 0 2006.162.08:23:41.42#ibcon#about to read 3, iclass 30, count 0 2006.162.08:23:41.44#ibcon#read 3, iclass 30, count 0 2006.162.08:23:41.44#ibcon#about to read 4, iclass 30, count 0 2006.162.08:23:41.44#ibcon#read 4, iclass 30, count 0 2006.162.08:23:41.44#ibcon#about to read 5, iclass 30, count 0 2006.162.08:23:41.44#ibcon#read 5, iclass 30, count 0 2006.162.08:23:41.44#ibcon#about to read 6, iclass 30, count 0 2006.162.08:23:41.44#ibcon#read 6, iclass 30, count 0 2006.162.08:23:41.44#ibcon#end of sib2, iclass 30, count 0 2006.162.08:23:41.44#ibcon#*mode == 0, iclass 30, count 0 2006.162.08:23:41.44#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.162.08:23:41.44#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.08:23:41.44#ibcon#*before write, iclass 30, count 0 2006.162.08:23:41.44#ibcon#enter sib2, iclass 30, count 0 2006.162.08:23:41.44#ibcon#flushed, iclass 30, count 0 2006.162.08:23:41.44#ibcon#about to write, iclass 30, count 0 2006.162.08:23:41.44#ibcon#wrote, iclass 30, count 0 2006.162.08:23:41.44#ibcon#about to read 3, iclass 30, count 0 2006.162.08:23:41.47#abcon#[5=S1D000X0/0*\r\n] 2006.162.08:23:41.48#ibcon#read 3, iclass 30, count 0 2006.162.08:23:41.48#ibcon#about to read 4, iclass 30, count 0 2006.162.08:23:41.48#ibcon#read 4, iclass 30, count 0 2006.162.08:23:41.48#ibcon#about to read 5, iclass 30, count 0 2006.162.08:23:41.48#ibcon#read 5, iclass 30, count 0 2006.162.08:23:41.48#ibcon#about to read 6, iclass 30, count 0 2006.162.08:23:41.48#ibcon#read 6, iclass 30, count 0 2006.162.08:23:41.48#ibcon#end of sib2, iclass 30, count 0 2006.162.08:23:41.48#ibcon#*after write, iclass 30, count 0 2006.162.08:23:41.48#ibcon#*before return 0, iclass 30, count 0 2006.162.08:23:41.48#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:23:41.48#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:23:41.48#ibcon#about to clear, iclass 30 cls_cnt 0 2006.162.08:23:41.48#ibcon#cleared, iclass 30 cls_cnt 0 2006.162.08:23:41.48$vc4f8/va=7,6 2006.162.08:23:41.48#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.162.08:23:41.48#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.162.08:23:41.48#ibcon#ireg 11 cls_cnt 2 2006.162.08:23:41.48#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.162.08:23:41.54#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.162.08:23:41.54#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.162.08:23:41.54#ibcon#enter wrdev, iclass 33, count 2 2006.162.08:23:41.54#ibcon#first serial, iclass 33, count 2 2006.162.08:23:41.54#ibcon#enter sib2, iclass 33, count 2 2006.162.08:23:41.54#ibcon#flushed, iclass 33, count 2 2006.162.08:23:41.54#ibcon#about to write, iclass 33, count 2 2006.162.08:23:41.54#ibcon#wrote, iclass 33, count 2 2006.162.08:23:41.54#ibcon#about to read 3, iclass 33, count 2 2006.162.08:23:41.56#ibcon#read 3, iclass 33, count 2 2006.162.08:23:41.56#ibcon#about to read 4, iclass 33, count 2 2006.162.08:23:41.56#ibcon#read 4, iclass 33, count 2 2006.162.08:23:41.56#ibcon#about to read 5, iclass 33, count 2 2006.162.08:23:41.56#ibcon#read 5, iclass 33, count 2 2006.162.08:23:41.56#ibcon#about to read 6, iclass 33, count 2 2006.162.08:23:41.56#ibcon#read 6, iclass 33, count 2 2006.162.08:23:41.56#ibcon#end of sib2, iclass 33, count 2 2006.162.08:23:41.56#ibcon#*mode == 0, iclass 33, count 2 2006.162.08:23:41.56#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.162.08:23:41.56#ibcon#[25=AT07-06\r\n] 2006.162.08:23:41.56#ibcon#*before write, iclass 33, count 2 2006.162.08:23:41.56#ibcon#enter sib2, iclass 33, count 2 2006.162.08:23:41.56#ibcon#flushed, iclass 33, count 2 2006.162.08:23:41.56#ibcon#about to write, iclass 33, count 2 2006.162.08:23:41.56#ibcon#wrote, iclass 33, count 2 2006.162.08:23:41.56#ibcon#about to read 3, iclass 33, count 2 2006.162.08:23:41.59#ibcon#read 3, iclass 33, count 2 2006.162.08:23:41.59#ibcon#about to read 4, iclass 33, count 2 2006.162.08:23:41.59#ibcon#read 4, iclass 33, count 2 2006.162.08:23:41.59#ibcon#about to read 5, iclass 33, count 2 2006.162.08:23:41.59#ibcon#read 5, iclass 33, count 2 2006.162.08:23:41.59#ibcon#about to read 6, iclass 33, count 2 2006.162.08:23:41.59#ibcon#read 6, iclass 33, count 2 2006.162.08:23:41.59#ibcon#end of sib2, iclass 33, count 2 2006.162.08:23:41.59#ibcon#*after write, iclass 33, count 2 2006.162.08:23:41.59#ibcon#*before return 0, iclass 33, count 2 2006.162.08:23:41.59#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.162.08:23:41.59#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.162.08:23:41.59#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.162.08:23:41.59#ibcon#ireg 7 cls_cnt 0 2006.162.08:23:41.59#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.162.08:23:41.71#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.162.08:23:41.71#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.162.08:23:41.71#ibcon#enter wrdev, iclass 33, count 0 2006.162.08:23:41.71#ibcon#first serial, iclass 33, count 0 2006.162.08:23:41.71#ibcon#enter sib2, iclass 33, count 0 2006.162.08:23:41.71#ibcon#flushed, iclass 33, count 0 2006.162.08:23:41.71#ibcon#about to write, iclass 33, count 0 2006.162.08:23:41.71#ibcon#wrote, iclass 33, count 0 2006.162.08:23:41.71#ibcon#about to read 3, iclass 33, count 0 2006.162.08:23:41.73#ibcon#read 3, iclass 33, count 0 2006.162.08:23:41.73#ibcon#about to read 4, iclass 33, count 0 2006.162.08:23:41.73#ibcon#read 4, iclass 33, count 0 2006.162.08:23:41.73#ibcon#about to read 5, iclass 33, count 0 2006.162.08:23:41.73#ibcon#read 5, iclass 33, count 0 2006.162.08:23:41.73#ibcon#about to read 6, iclass 33, count 0 2006.162.08:23:41.73#ibcon#read 6, iclass 33, count 0 2006.162.08:23:41.73#ibcon#end of sib2, iclass 33, count 0 2006.162.08:23:41.73#ibcon#*mode == 0, iclass 33, count 0 2006.162.08:23:41.73#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.162.08:23:41.73#ibcon#[25=USB\r\n] 2006.162.08:23:41.73#ibcon#*before write, iclass 33, count 0 2006.162.08:23:41.73#ibcon#enter sib2, iclass 33, count 0 2006.162.08:23:41.73#ibcon#flushed, iclass 33, count 0 2006.162.08:23:41.73#ibcon#about to write, iclass 33, count 0 2006.162.08:23:41.73#ibcon#wrote, iclass 33, count 0 2006.162.08:23:41.73#ibcon#about to read 3, iclass 33, count 0 2006.162.08:23:41.76#ibcon#read 3, iclass 33, count 0 2006.162.08:23:41.76#ibcon#about to read 4, iclass 33, count 0 2006.162.08:23:41.76#ibcon#read 4, iclass 33, count 0 2006.162.08:23:41.76#ibcon#about to read 5, iclass 33, count 0 2006.162.08:23:41.76#ibcon#read 5, iclass 33, count 0 2006.162.08:23:41.76#ibcon#about to read 6, iclass 33, count 0 2006.162.08:23:41.76#ibcon#read 6, iclass 33, count 0 2006.162.08:23:41.76#ibcon#end of sib2, iclass 33, count 0 2006.162.08:23:41.76#ibcon#*after write, iclass 33, count 0 2006.162.08:23:41.76#ibcon#*before return 0, iclass 33, count 0 2006.162.08:23:41.76#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.162.08:23:41.76#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.162.08:23:41.76#ibcon#about to clear, iclass 33 cls_cnt 0 2006.162.08:23:41.76#ibcon#cleared, iclass 33 cls_cnt 0 2006.162.08:23:41.76$vc4f8/valo=8,852.99 2006.162.08:23:41.76#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.162.08:23:41.76#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.162.08:23:41.76#ibcon#ireg 17 cls_cnt 0 2006.162.08:23:41.76#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.162.08:23:41.76#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.162.08:23:41.76#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.162.08:23:41.76#ibcon#enter wrdev, iclass 35, count 0 2006.162.08:23:41.76#ibcon#first serial, iclass 35, count 0 2006.162.08:23:41.76#ibcon#enter sib2, iclass 35, count 0 2006.162.08:23:41.76#ibcon#flushed, iclass 35, count 0 2006.162.08:23:41.76#ibcon#about to write, iclass 35, count 0 2006.162.08:23:41.76#ibcon#wrote, iclass 35, count 0 2006.162.08:23:41.76#ibcon#about to read 3, iclass 35, count 0 2006.162.08:23:41.78#ibcon#read 3, iclass 35, count 0 2006.162.08:23:41.78#ibcon#about to read 4, iclass 35, count 0 2006.162.08:23:41.78#ibcon#read 4, iclass 35, count 0 2006.162.08:23:41.78#ibcon#about to read 5, iclass 35, count 0 2006.162.08:23:41.78#ibcon#read 5, iclass 35, count 0 2006.162.08:23:41.78#ibcon#about to read 6, iclass 35, count 0 2006.162.08:23:41.78#ibcon#read 6, iclass 35, count 0 2006.162.08:23:41.78#ibcon#end of sib2, iclass 35, count 0 2006.162.08:23:41.78#ibcon#*mode == 0, iclass 35, count 0 2006.162.08:23:41.78#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.162.08:23:41.78#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.08:23:41.78#ibcon#*before write, iclass 35, count 0 2006.162.08:23:41.78#ibcon#enter sib2, iclass 35, count 0 2006.162.08:23:41.78#ibcon#flushed, iclass 35, count 0 2006.162.08:23:41.78#ibcon#about to write, iclass 35, count 0 2006.162.08:23:41.78#ibcon#wrote, iclass 35, count 0 2006.162.08:23:41.78#ibcon#about to read 3, iclass 35, count 0 2006.162.08:23:41.82#ibcon#read 3, iclass 35, count 0 2006.162.08:23:41.82#ibcon#about to read 4, iclass 35, count 0 2006.162.08:23:41.82#ibcon#read 4, iclass 35, count 0 2006.162.08:23:41.82#ibcon#about to read 5, iclass 35, count 0 2006.162.08:23:41.82#ibcon#read 5, iclass 35, count 0 2006.162.08:23:41.82#ibcon#about to read 6, iclass 35, count 0 2006.162.08:23:41.82#ibcon#read 6, iclass 35, count 0 2006.162.08:23:41.82#ibcon#end of sib2, iclass 35, count 0 2006.162.08:23:41.82#ibcon#*after write, iclass 35, count 0 2006.162.08:23:41.82#ibcon#*before return 0, iclass 35, count 0 2006.162.08:23:41.82#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.162.08:23:41.82#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.162.08:23:41.82#ibcon#about to clear, iclass 35 cls_cnt 0 2006.162.08:23:41.82#ibcon#cleared, iclass 35 cls_cnt 0 2006.162.08:23:41.82$vc4f8/va=8,7 2006.162.08:23:41.82#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.162.08:23:41.82#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.162.08:23:41.82#ibcon#ireg 11 cls_cnt 2 2006.162.08:23:41.82#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.162.08:23:41.88#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.162.08:23:41.88#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.162.08:23:41.88#ibcon#enter wrdev, iclass 37, count 2 2006.162.08:23:41.88#ibcon#first serial, iclass 37, count 2 2006.162.08:23:41.88#ibcon#enter sib2, iclass 37, count 2 2006.162.08:23:41.88#ibcon#flushed, iclass 37, count 2 2006.162.08:23:41.88#ibcon#about to write, iclass 37, count 2 2006.162.08:23:41.88#ibcon#wrote, iclass 37, count 2 2006.162.08:23:41.88#ibcon#about to read 3, iclass 37, count 2 2006.162.08:23:41.90#ibcon#read 3, iclass 37, count 2 2006.162.08:23:41.90#ibcon#about to read 4, iclass 37, count 2 2006.162.08:23:41.90#ibcon#read 4, iclass 37, count 2 2006.162.08:23:41.90#ibcon#about to read 5, iclass 37, count 2 2006.162.08:23:41.90#ibcon#read 5, iclass 37, count 2 2006.162.08:23:41.90#ibcon#about to read 6, iclass 37, count 2 2006.162.08:23:41.90#ibcon#read 6, iclass 37, count 2 2006.162.08:23:41.90#ibcon#end of sib2, iclass 37, count 2 2006.162.08:23:41.90#ibcon#*mode == 0, iclass 37, count 2 2006.162.08:23:41.90#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.162.08:23:41.90#ibcon#[25=AT08-07\r\n] 2006.162.08:23:41.90#ibcon#*before write, iclass 37, count 2 2006.162.08:23:41.90#ibcon#enter sib2, iclass 37, count 2 2006.162.08:23:41.90#ibcon#flushed, iclass 37, count 2 2006.162.08:23:41.90#ibcon#about to write, iclass 37, count 2 2006.162.08:23:41.90#ibcon#wrote, iclass 37, count 2 2006.162.08:23:41.90#ibcon#about to read 3, iclass 37, count 2 2006.162.08:23:41.93#ibcon#read 3, iclass 37, count 2 2006.162.08:23:41.93#ibcon#about to read 4, iclass 37, count 2 2006.162.08:23:41.93#ibcon#read 4, iclass 37, count 2 2006.162.08:23:41.93#ibcon#about to read 5, iclass 37, count 2 2006.162.08:23:41.93#ibcon#read 5, iclass 37, count 2 2006.162.08:23:41.93#ibcon#about to read 6, iclass 37, count 2 2006.162.08:23:41.93#ibcon#read 6, iclass 37, count 2 2006.162.08:23:41.93#ibcon#end of sib2, iclass 37, count 2 2006.162.08:23:41.93#ibcon#*after write, iclass 37, count 2 2006.162.08:23:41.93#ibcon#*before return 0, iclass 37, count 2 2006.162.08:23:41.93#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.162.08:23:41.93#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.162.08:23:41.93#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.162.08:23:41.93#ibcon#ireg 7 cls_cnt 0 2006.162.08:23:41.93#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.162.08:23:42.05#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.162.08:23:42.05#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.162.08:23:42.05#ibcon#enter wrdev, iclass 37, count 0 2006.162.08:23:42.05#ibcon#first serial, iclass 37, count 0 2006.162.08:23:42.05#ibcon#enter sib2, iclass 37, count 0 2006.162.08:23:42.05#ibcon#flushed, iclass 37, count 0 2006.162.08:23:42.05#ibcon#about to write, iclass 37, count 0 2006.162.08:23:42.05#ibcon#wrote, iclass 37, count 0 2006.162.08:23:42.05#ibcon#about to read 3, iclass 37, count 0 2006.162.08:23:42.07#ibcon#read 3, iclass 37, count 0 2006.162.08:23:42.07#ibcon#about to read 4, iclass 37, count 0 2006.162.08:23:42.07#ibcon#read 4, iclass 37, count 0 2006.162.08:23:42.07#ibcon#about to read 5, iclass 37, count 0 2006.162.08:23:42.07#ibcon#read 5, iclass 37, count 0 2006.162.08:23:42.07#ibcon#about to read 6, iclass 37, count 0 2006.162.08:23:42.07#ibcon#read 6, iclass 37, count 0 2006.162.08:23:42.07#ibcon#end of sib2, iclass 37, count 0 2006.162.08:23:42.07#ibcon#*mode == 0, iclass 37, count 0 2006.162.08:23:42.07#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.162.08:23:42.07#ibcon#[25=USB\r\n] 2006.162.08:23:42.07#ibcon#*before write, iclass 37, count 0 2006.162.08:23:42.07#ibcon#enter sib2, iclass 37, count 0 2006.162.08:23:42.07#ibcon#flushed, iclass 37, count 0 2006.162.08:23:42.07#ibcon#about to write, iclass 37, count 0 2006.162.08:23:42.07#ibcon#wrote, iclass 37, count 0 2006.162.08:23:42.07#ibcon#about to read 3, iclass 37, count 0 2006.162.08:23:42.10#ibcon#read 3, iclass 37, count 0 2006.162.08:23:42.10#ibcon#about to read 4, iclass 37, count 0 2006.162.08:23:42.10#ibcon#read 4, iclass 37, count 0 2006.162.08:23:42.10#ibcon#about to read 5, iclass 37, count 0 2006.162.08:23:42.10#ibcon#read 5, iclass 37, count 0 2006.162.08:23:42.10#ibcon#about to read 6, iclass 37, count 0 2006.162.08:23:42.10#ibcon#read 6, iclass 37, count 0 2006.162.08:23:42.10#ibcon#end of sib2, iclass 37, count 0 2006.162.08:23:42.10#ibcon#*after write, iclass 37, count 0 2006.162.08:23:42.10#ibcon#*before return 0, iclass 37, count 0 2006.162.08:23:42.10#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.162.08:23:42.10#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.162.08:23:42.10#ibcon#about to clear, iclass 37 cls_cnt 0 2006.162.08:23:42.10#ibcon#cleared, iclass 37 cls_cnt 0 2006.162.08:23:42.10$vc4f8/vblo=1,632.99 2006.162.08:23:42.10#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.162.08:23:42.10#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.162.08:23:42.10#ibcon#ireg 17 cls_cnt 0 2006.162.08:23:42.10#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:23:42.10#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:23:42.10#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:23:42.10#ibcon#enter wrdev, iclass 39, count 0 2006.162.08:23:42.10#ibcon#first serial, iclass 39, count 0 2006.162.08:23:42.10#ibcon#enter sib2, iclass 39, count 0 2006.162.08:23:42.10#ibcon#flushed, iclass 39, count 0 2006.162.08:23:42.10#ibcon#about to write, iclass 39, count 0 2006.162.08:23:42.10#ibcon#wrote, iclass 39, count 0 2006.162.08:23:42.10#ibcon#about to read 3, iclass 39, count 0 2006.162.08:23:42.12#ibcon#read 3, iclass 39, count 0 2006.162.08:23:42.12#ibcon#about to read 4, iclass 39, count 0 2006.162.08:23:42.12#ibcon#read 4, iclass 39, count 0 2006.162.08:23:42.12#ibcon#about to read 5, iclass 39, count 0 2006.162.08:23:42.12#ibcon#read 5, iclass 39, count 0 2006.162.08:23:42.12#ibcon#about to read 6, iclass 39, count 0 2006.162.08:23:42.12#ibcon#read 6, iclass 39, count 0 2006.162.08:23:42.12#ibcon#end of sib2, iclass 39, count 0 2006.162.08:23:42.12#ibcon#*mode == 0, iclass 39, count 0 2006.162.08:23:42.12#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.162.08:23:42.12#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.08:23:42.12#ibcon#*before write, iclass 39, count 0 2006.162.08:23:42.12#ibcon#enter sib2, iclass 39, count 0 2006.162.08:23:42.12#ibcon#flushed, iclass 39, count 0 2006.162.08:23:42.12#ibcon#about to write, iclass 39, count 0 2006.162.08:23:42.12#ibcon#wrote, iclass 39, count 0 2006.162.08:23:42.12#ibcon#about to read 3, iclass 39, count 0 2006.162.08:23:42.16#ibcon#read 3, iclass 39, count 0 2006.162.08:23:42.16#ibcon#about to read 4, iclass 39, count 0 2006.162.08:23:42.16#ibcon#read 4, iclass 39, count 0 2006.162.08:23:42.16#ibcon#about to read 5, iclass 39, count 0 2006.162.08:23:42.16#ibcon#read 5, iclass 39, count 0 2006.162.08:23:42.16#ibcon#about to read 6, iclass 39, count 0 2006.162.08:23:42.16#ibcon#read 6, iclass 39, count 0 2006.162.08:23:42.16#ibcon#end of sib2, iclass 39, count 0 2006.162.08:23:42.16#ibcon#*after write, iclass 39, count 0 2006.162.08:23:42.16#ibcon#*before return 0, iclass 39, count 0 2006.162.08:23:42.16#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:23:42.16#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.162.08:23:42.16#ibcon#about to clear, iclass 39 cls_cnt 0 2006.162.08:23:42.16#ibcon#cleared, iclass 39 cls_cnt 0 2006.162.08:23:42.16$vc4f8/vb=1,4 2006.162.08:23:42.16#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.162.08:23:42.16#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.162.08:23:42.16#ibcon#ireg 11 cls_cnt 2 2006.162.08:23:42.16#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:23:42.16#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:23:42.16#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:23:42.16#ibcon#enter wrdev, iclass 3, count 2 2006.162.08:23:42.16#ibcon#first serial, iclass 3, count 2 2006.162.08:23:42.16#ibcon#enter sib2, iclass 3, count 2 2006.162.08:23:42.16#ibcon#flushed, iclass 3, count 2 2006.162.08:23:42.16#ibcon#about to write, iclass 3, count 2 2006.162.08:23:42.16#ibcon#wrote, iclass 3, count 2 2006.162.08:23:42.16#ibcon#about to read 3, iclass 3, count 2 2006.162.08:23:42.18#ibcon#read 3, iclass 3, count 2 2006.162.08:23:42.18#ibcon#about to read 4, iclass 3, count 2 2006.162.08:23:42.18#ibcon#read 4, iclass 3, count 2 2006.162.08:23:42.18#ibcon#about to read 5, iclass 3, count 2 2006.162.08:23:42.18#ibcon#read 5, iclass 3, count 2 2006.162.08:23:42.18#ibcon#about to read 6, iclass 3, count 2 2006.162.08:23:42.18#ibcon#read 6, iclass 3, count 2 2006.162.08:23:42.18#ibcon#end of sib2, iclass 3, count 2 2006.162.08:23:42.18#ibcon#*mode == 0, iclass 3, count 2 2006.162.08:23:42.18#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.162.08:23:42.18#ibcon#[27=AT01-04\r\n] 2006.162.08:23:42.18#ibcon#*before write, iclass 3, count 2 2006.162.08:23:42.18#ibcon#enter sib2, iclass 3, count 2 2006.162.08:23:42.18#ibcon#flushed, iclass 3, count 2 2006.162.08:23:42.18#ibcon#about to write, iclass 3, count 2 2006.162.08:23:42.18#ibcon#wrote, iclass 3, count 2 2006.162.08:23:42.18#ibcon#about to read 3, iclass 3, count 2 2006.162.08:23:42.21#ibcon#read 3, iclass 3, count 2 2006.162.08:23:42.21#ibcon#about to read 4, iclass 3, count 2 2006.162.08:23:42.21#ibcon#read 4, iclass 3, count 2 2006.162.08:23:42.21#ibcon#about to read 5, iclass 3, count 2 2006.162.08:23:42.21#ibcon#read 5, iclass 3, count 2 2006.162.08:23:42.21#ibcon#about to read 6, iclass 3, count 2 2006.162.08:23:42.21#ibcon#read 6, iclass 3, count 2 2006.162.08:23:42.21#ibcon#end of sib2, iclass 3, count 2 2006.162.08:23:42.21#ibcon#*after write, iclass 3, count 2 2006.162.08:23:42.21#ibcon#*before return 0, iclass 3, count 2 2006.162.08:23:42.21#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:23:42.21#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.162.08:23:42.21#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.162.08:23:42.21#ibcon#ireg 7 cls_cnt 0 2006.162.08:23:42.21#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:23:42.33#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:23:42.33#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:23:42.33#ibcon#enter wrdev, iclass 3, count 0 2006.162.08:23:42.33#ibcon#first serial, iclass 3, count 0 2006.162.08:23:42.33#ibcon#enter sib2, iclass 3, count 0 2006.162.08:23:42.33#ibcon#flushed, iclass 3, count 0 2006.162.08:23:42.33#ibcon#about to write, iclass 3, count 0 2006.162.08:23:42.33#ibcon#wrote, iclass 3, count 0 2006.162.08:23:42.33#ibcon#about to read 3, iclass 3, count 0 2006.162.08:23:42.35#ibcon#read 3, iclass 3, count 0 2006.162.08:23:42.35#ibcon#about to read 4, iclass 3, count 0 2006.162.08:23:42.35#ibcon#read 4, iclass 3, count 0 2006.162.08:23:42.35#ibcon#about to read 5, iclass 3, count 0 2006.162.08:23:42.35#ibcon#read 5, iclass 3, count 0 2006.162.08:23:42.35#ibcon#about to read 6, iclass 3, count 0 2006.162.08:23:42.35#ibcon#read 6, iclass 3, count 0 2006.162.08:23:42.35#ibcon#end of sib2, iclass 3, count 0 2006.162.08:23:42.35#ibcon#*mode == 0, iclass 3, count 0 2006.162.08:23:42.35#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.162.08:23:42.35#ibcon#[27=USB\r\n] 2006.162.08:23:42.35#ibcon#*before write, iclass 3, count 0 2006.162.08:23:42.35#ibcon#enter sib2, iclass 3, count 0 2006.162.08:23:42.35#ibcon#flushed, iclass 3, count 0 2006.162.08:23:42.35#ibcon#about to write, iclass 3, count 0 2006.162.08:23:42.35#ibcon#wrote, iclass 3, count 0 2006.162.08:23:42.35#ibcon#about to read 3, iclass 3, count 0 2006.162.08:23:42.38#ibcon#read 3, iclass 3, count 0 2006.162.08:23:42.38#ibcon#about to read 4, iclass 3, count 0 2006.162.08:23:42.38#ibcon#read 4, iclass 3, count 0 2006.162.08:23:42.38#ibcon#about to read 5, iclass 3, count 0 2006.162.08:23:42.38#ibcon#read 5, iclass 3, count 0 2006.162.08:23:42.38#ibcon#about to read 6, iclass 3, count 0 2006.162.08:23:42.38#ibcon#read 6, iclass 3, count 0 2006.162.08:23:42.38#ibcon#end of sib2, iclass 3, count 0 2006.162.08:23:42.38#ibcon#*after write, iclass 3, count 0 2006.162.08:23:42.38#ibcon#*before return 0, iclass 3, count 0 2006.162.08:23:42.38#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:23:42.38#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.162.08:23:42.38#ibcon#about to clear, iclass 3 cls_cnt 0 2006.162.08:23:42.38#ibcon#cleared, iclass 3 cls_cnt 0 2006.162.08:23:42.38$vc4f8/vblo=2,640.99 2006.162.08:23:42.38#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.162.08:23:42.38#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.162.08:23:42.38#ibcon#ireg 17 cls_cnt 0 2006.162.08:23:42.38#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:23:42.38#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:23:42.38#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:23:42.38#ibcon#enter wrdev, iclass 5, count 0 2006.162.08:23:42.38#ibcon#first serial, iclass 5, count 0 2006.162.08:23:42.38#ibcon#enter sib2, iclass 5, count 0 2006.162.08:23:42.38#ibcon#flushed, iclass 5, count 0 2006.162.08:23:42.38#ibcon#about to write, iclass 5, count 0 2006.162.08:23:42.38#ibcon#wrote, iclass 5, count 0 2006.162.08:23:42.38#ibcon#about to read 3, iclass 5, count 0 2006.162.08:23:42.40#ibcon#read 3, iclass 5, count 0 2006.162.08:23:42.40#ibcon#about to read 4, iclass 5, count 0 2006.162.08:23:42.40#ibcon#read 4, iclass 5, count 0 2006.162.08:23:42.40#ibcon#about to read 5, iclass 5, count 0 2006.162.08:23:42.40#ibcon#read 5, iclass 5, count 0 2006.162.08:23:42.40#ibcon#about to read 6, iclass 5, count 0 2006.162.08:23:42.40#ibcon#read 6, iclass 5, count 0 2006.162.08:23:42.40#ibcon#end of sib2, iclass 5, count 0 2006.162.08:23:42.40#ibcon#*mode == 0, iclass 5, count 0 2006.162.08:23:42.40#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.162.08:23:42.40#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.08:23:42.40#ibcon#*before write, iclass 5, count 0 2006.162.08:23:42.40#ibcon#enter sib2, iclass 5, count 0 2006.162.08:23:42.40#ibcon#flushed, iclass 5, count 0 2006.162.08:23:42.40#ibcon#about to write, iclass 5, count 0 2006.162.08:23:42.40#ibcon#wrote, iclass 5, count 0 2006.162.08:23:42.40#ibcon#about to read 3, iclass 5, count 0 2006.162.08:23:42.44#ibcon#read 3, iclass 5, count 0 2006.162.08:23:42.44#ibcon#about to read 4, iclass 5, count 0 2006.162.08:23:42.44#ibcon#read 4, iclass 5, count 0 2006.162.08:23:42.44#ibcon#about to read 5, iclass 5, count 0 2006.162.08:23:42.44#ibcon#read 5, iclass 5, count 0 2006.162.08:23:42.44#ibcon#about to read 6, iclass 5, count 0 2006.162.08:23:42.44#ibcon#read 6, iclass 5, count 0 2006.162.08:23:42.44#ibcon#end of sib2, iclass 5, count 0 2006.162.08:23:42.44#ibcon#*after write, iclass 5, count 0 2006.162.08:23:42.44#ibcon#*before return 0, iclass 5, count 0 2006.162.08:23:42.44#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:23:42.44#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.162.08:23:42.44#ibcon#about to clear, iclass 5 cls_cnt 0 2006.162.08:23:42.44#ibcon#cleared, iclass 5 cls_cnt 0 2006.162.08:23:42.44$vc4f8/vb=2,4 2006.162.08:23:42.44#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.162.08:23:42.44#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.162.08:23:42.44#ibcon#ireg 11 cls_cnt 2 2006.162.08:23:42.44#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:23:42.50#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:23:42.50#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:23:42.50#ibcon#enter wrdev, iclass 7, count 2 2006.162.08:23:42.50#ibcon#first serial, iclass 7, count 2 2006.162.08:23:42.50#ibcon#enter sib2, iclass 7, count 2 2006.162.08:23:42.50#ibcon#flushed, iclass 7, count 2 2006.162.08:23:42.50#ibcon#about to write, iclass 7, count 2 2006.162.08:23:42.50#ibcon#wrote, iclass 7, count 2 2006.162.08:23:42.50#ibcon#about to read 3, iclass 7, count 2 2006.162.08:23:42.52#ibcon#read 3, iclass 7, count 2 2006.162.08:23:42.52#ibcon#about to read 4, iclass 7, count 2 2006.162.08:23:42.52#ibcon#read 4, iclass 7, count 2 2006.162.08:23:42.52#ibcon#about to read 5, iclass 7, count 2 2006.162.08:23:42.52#ibcon#read 5, iclass 7, count 2 2006.162.08:23:42.52#ibcon#about to read 6, iclass 7, count 2 2006.162.08:23:42.52#ibcon#read 6, iclass 7, count 2 2006.162.08:23:42.52#ibcon#end of sib2, iclass 7, count 2 2006.162.08:23:42.52#ibcon#*mode == 0, iclass 7, count 2 2006.162.08:23:42.52#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.162.08:23:42.52#ibcon#[27=AT02-04\r\n] 2006.162.08:23:42.52#ibcon#*before write, iclass 7, count 2 2006.162.08:23:42.52#ibcon#enter sib2, iclass 7, count 2 2006.162.08:23:42.52#ibcon#flushed, iclass 7, count 2 2006.162.08:23:42.52#ibcon#about to write, iclass 7, count 2 2006.162.08:23:42.52#ibcon#wrote, iclass 7, count 2 2006.162.08:23:42.52#ibcon#about to read 3, iclass 7, count 2 2006.162.08:23:42.55#ibcon#read 3, iclass 7, count 2 2006.162.08:23:42.55#ibcon#about to read 4, iclass 7, count 2 2006.162.08:23:42.55#ibcon#read 4, iclass 7, count 2 2006.162.08:23:42.55#ibcon#about to read 5, iclass 7, count 2 2006.162.08:23:42.55#ibcon#read 5, iclass 7, count 2 2006.162.08:23:42.55#ibcon#about to read 6, iclass 7, count 2 2006.162.08:23:42.55#ibcon#read 6, iclass 7, count 2 2006.162.08:23:42.55#ibcon#end of sib2, iclass 7, count 2 2006.162.08:23:42.55#ibcon#*after write, iclass 7, count 2 2006.162.08:23:42.55#ibcon#*before return 0, iclass 7, count 2 2006.162.08:23:42.55#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:23:42.55#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.162.08:23:42.55#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.162.08:23:42.55#ibcon#ireg 7 cls_cnt 0 2006.162.08:23:42.55#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:23:42.67#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:23:42.67#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:23:42.67#ibcon#enter wrdev, iclass 7, count 0 2006.162.08:23:42.67#ibcon#first serial, iclass 7, count 0 2006.162.08:23:42.67#ibcon#enter sib2, iclass 7, count 0 2006.162.08:23:42.67#ibcon#flushed, iclass 7, count 0 2006.162.08:23:42.67#ibcon#about to write, iclass 7, count 0 2006.162.08:23:42.67#ibcon#wrote, iclass 7, count 0 2006.162.08:23:42.67#ibcon#about to read 3, iclass 7, count 0 2006.162.08:23:42.69#ibcon#read 3, iclass 7, count 0 2006.162.08:23:42.69#ibcon#about to read 4, iclass 7, count 0 2006.162.08:23:42.69#ibcon#read 4, iclass 7, count 0 2006.162.08:23:42.69#ibcon#about to read 5, iclass 7, count 0 2006.162.08:23:42.69#ibcon#read 5, iclass 7, count 0 2006.162.08:23:42.69#ibcon#about to read 6, iclass 7, count 0 2006.162.08:23:42.69#ibcon#read 6, iclass 7, count 0 2006.162.08:23:42.69#ibcon#end of sib2, iclass 7, count 0 2006.162.08:23:42.69#ibcon#*mode == 0, iclass 7, count 0 2006.162.08:23:42.69#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.162.08:23:42.69#ibcon#[27=USB\r\n] 2006.162.08:23:42.69#ibcon#*before write, iclass 7, count 0 2006.162.08:23:42.69#ibcon#enter sib2, iclass 7, count 0 2006.162.08:23:42.69#ibcon#flushed, iclass 7, count 0 2006.162.08:23:42.69#ibcon#about to write, iclass 7, count 0 2006.162.08:23:42.69#ibcon#wrote, iclass 7, count 0 2006.162.08:23:42.69#ibcon#about to read 3, iclass 7, count 0 2006.162.08:23:42.72#ibcon#read 3, iclass 7, count 0 2006.162.08:23:42.72#ibcon#about to read 4, iclass 7, count 0 2006.162.08:23:42.72#ibcon#read 4, iclass 7, count 0 2006.162.08:23:42.72#ibcon#about to read 5, iclass 7, count 0 2006.162.08:23:42.72#ibcon#read 5, iclass 7, count 0 2006.162.08:23:42.72#ibcon#about to read 6, iclass 7, count 0 2006.162.08:23:42.72#ibcon#read 6, iclass 7, count 0 2006.162.08:23:42.72#ibcon#end of sib2, iclass 7, count 0 2006.162.08:23:42.72#ibcon#*after write, iclass 7, count 0 2006.162.08:23:42.72#ibcon#*before return 0, iclass 7, count 0 2006.162.08:23:42.72#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:23:42.72#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.162.08:23:42.72#ibcon#about to clear, iclass 7 cls_cnt 0 2006.162.08:23:42.72#ibcon#cleared, iclass 7 cls_cnt 0 2006.162.08:23:42.72$vc4f8/vblo=3,656.99 2006.162.08:23:42.72#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.162.08:23:42.72#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.162.08:23:42.72#ibcon#ireg 17 cls_cnt 0 2006.162.08:23:42.72#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:23:42.72#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:23:42.72#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:23:42.72#ibcon#enter wrdev, iclass 11, count 0 2006.162.08:23:42.72#ibcon#first serial, iclass 11, count 0 2006.162.08:23:42.72#ibcon#enter sib2, iclass 11, count 0 2006.162.08:23:42.72#ibcon#flushed, iclass 11, count 0 2006.162.08:23:42.72#ibcon#about to write, iclass 11, count 0 2006.162.08:23:42.72#ibcon#wrote, iclass 11, count 0 2006.162.08:23:42.72#ibcon#about to read 3, iclass 11, count 0 2006.162.08:23:42.74#ibcon#read 3, iclass 11, count 0 2006.162.08:23:42.74#ibcon#about to read 4, iclass 11, count 0 2006.162.08:23:42.74#ibcon#read 4, iclass 11, count 0 2006.162.08:23:42.74#ibcon#about to read 5, iclass 11, count 0 2006.162.08:23:42.74#ibcon#read 5, iclass 11, count 0 2006.162.08:23:42.74#ibcon#about to read 6, iclass 11, count 0 2006.162.08:23:42.74#ibcon#read 6, iclass 11, count 0 2006.162.08:23:42.74#ibcon#end of sib2, iclass 11, count 0 2006.162.08:23:42.74#ibcon#*mode == 0, iclass 11, count 0 2006.162.08:23:42.74#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.162.08:23:42.74#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.08:23:42.74#ibcon#*before write, iclass 11, count 0 2006.162.08:23:42.74#ibcon#enter sib2, iclass 11, count 0 2006.162.08:23:42.74#ibcon#flushed, iclass 11, count 0 2006.162.08:23:42.74#ibcon#about to write, iclass 11, count 0 2006.162.08:23:42.74#ibcon#wrote, iclass 11, count 0 2006.162.08:23:42.74#ibcon#about to read 3, iclass 11, count 0 2006.162.08:23:42.78#ibcon#read 3, iclass 11, count 0 2006.162.08:23:42.78#ibcon#about to read 4, iclass 11, count 0 2006.162.08:23:42.78#ibcon#read 4, iclass 11, count 0 2006.162.08:23:42.78#ibcon#about to read 5, iclass 11, count 0 2006.162.08:23:42.78#ibcon#read 5, iclass 11, count 0 2006.162.08:23:42.78#ibcon#about to read 6, iclass 11, count 0 2006.162.08:23:42.78#ibcon#read 6, iclass 11, count 0 2006.162.08:23:42.78#ibcon#end of sib2, iclass 11, count 0 2006.162.08:23:42.78#ibcon#*after write, iclass 11, count 0 2006.162.08:23:42.78#ibcon#*before return 0, iclass 11, count 0 2006.162.08:23:42.78#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:23:42.78#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.162.08:23:42.78#ibcon#about to clear, iclass 11 cls_cnt 0 2006.162.08:23:42.78#ibcon#cleared, iclass 11 cls_cnt 0 2006.162.08:23:42.78$vc4f8/vb=3,4 2006.162.08:23:42.78#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.162.08:23:42.78#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.162.08:23:42.78#ibcon#ireg 11 cls_cnt 2 2006.162.08:23:42.78#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:23:42.84#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:23:42.84#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:23:42.84#ibcon#enter wrdev, iclass 13, count 2 2006.162.08:23:42.84#ibcon#first serial, iclass 13, count 2 2006.162.08:23:42.84#ibcon#enter sib2, iclass 13, count 2 2006.162.08:23:42.84#ibcon#flushed, iclass 13, count 2 2006.162.08:23:42.84#ibcon#about to write, iclass 13, count 2 2006.162.08:23:42.84#ibcon#wrote, iclass 13, count 2 2006.162.08:23:42.84#ibcon#about to read 3, iclass 13, count 2 2006.162.08:23:42.86#ibcon#read 3, iclass 13, count 2 2006.162.08:23:42.86#ibcon#about to read 4, iclass 13, count 2 2006.162.08:23:42.86#ibcon#read 4, iclass 13, count 2 2006.162.08:23:42.86#ibcon#about to read 5, iclass 13, count 2 2006.162.08:23:42.86#ibcon#read 5, iclass 13, count 2 2006.162.08:23:42.86#ibcon#about to read 6, iclass 13, count 2 2006.162.08:23:42.86#ibcon#read 6, iclass 13, count 2 2006.162.08:23:42.86#ibcon#end of sib2, iclass 13, count 2 2006.162.08:23:42.86#ibcon#*mode == 0, iclass 13, count 2 2006.162.08:23:42.86#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.162.08:23:42.86#ibcon#[27=AT03-04\r\n] 2006.162.08:23:42.86#ibcon#*before write, iclass 13, count 2 2006.162.08:23:42.86#ibcon#enter sib2, iclass 13, count 2 2006.162.08:23:42.86#ibcon#flushed, iclass 13, count 2 2006.162.08:23:42.86#ibcon#about to write, iclass 13, count 2 2006.162.08:23:42.86#ibcon#wrote, iclass 13, count 2 2006.162.08:23:42.86#ibcon#about to read 3, iclass 13, count 2 2006.162.08:23:42.89#ibcon#read 3, iclass 13, count 2 2006.162.08:23:42.89#ibcon#about to read 4, iclass 13, count 2 2006.162.08:23:42.89#ibcon#read 4, iclass 13, count 2 2006.162.08:23:42.89#ibcon#about to read 5, iclass 13, count 2 2006.162.08:23:42.89#ibcon#read 5, iclass 13, count 2 2006.162.08:23:42.89#ibcon#about to read 6, iclass 13, count 2 2006.162.08:23:42.89#ibcon#read 6, iclass 13, count 2 2006.162.08:23:42.89#ibcon#end of sib2, iclass 13, count 2 2006.162.08:23:42.89#ibcon#*after write, iclass 13, count 2 2006.162.08:23:42.89#ibcon#*before return 0, iclass 13, count 2 2006.162.08:23:42.89#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:23:42.89#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.162.08:23:42.89#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.162.08:23:42.89#ibcon#ireg 7 cls_cnt 0 2006.162.08:23:42.89#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:23:43.01#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:23:43.01#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:23:43.01#ibcon#enter wrdev, iclass 13, count 0 2006.162.08:23:43.01#ibcon#first serial, iclass 13, count 0 2006.162.08:23:43.01#ibcon#enter sib2, iclass 13, count 0 2006.162.08:23:43.01#ibcon#flushed, iclass 13, count 0 2006.162.08:23:43.01#ibcon#about to write, iclass 13, count 0 2006.162.08:23:43.01#ibcon#wrote, iclass 13, count 0 2006.162.08:23:43.01#ibcon#about to read 3, iclass 13, count 0 2006.162.08:23:43.03#ibcon#read 3, iclass 13, count 0 2006.162.08:23:43.03#ibcon#about to read 4, iclass 13, count 0 2006.162.08:23:43.03#ibcon#read 4, iclass 13, count 0 2006.162.08:23:43.03#ibcon#about to read 5, iclass 13, count 0 2006.162.08:23:43.03#ibcon#read 5, iclass 13, count 0 2006.162.08:23:43.03#ibcon#about to read 6, iclass 13, count 0 2006.162.08:23:43.03#ibcon#read 6, iclass 13, count 0 2006.162.08:23:43.03#ibcon#end of sib2, iclass 13, count 0 2006.162.08:23:43.03#ibcon#*mode == 0, iclass 13, count 0 2006.162.08:23:43.03#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.162.08:23:43.03#ibcon#[27=USB\r\n] 2006.162.08:23:43.03#ibcon#*before write, iclass 13, count 0 2006.162.08:23:43.03#ibcon#enter sib2, iclass 13, count 0 2006.162.08:23:43.03#ibcon#flushed, iclass 13, count 0 2006.162.08:23:43.03#ibcon#about to write, iclass 13, count 0 2006.162.08:23:43.03#ibcon#wrote, iclass 13, count 0 2006.162.08:23:43.03#ibcon#about to read 3, iclass 13, count 0 2006.162.08:23:43.06#ibcon#read 3, iclass 13, count 0 2006.162.08:23:43.06#ibcon#about to read 4, iclass 13, count 0 2006.162.08:23:43.06#ibcon#read 4, iclass 13, count 0 2006.162.08:23:43.06#ibcon#about to read 5, iclass 13, count 0 2006.162.08:23:43.06#ibcon#read 5, iclass 13, count 0 2006.162.08:23:43.06#ibcon#about to read 6, iclass 13, count 0 2006.162.08:23:43.06#ibcon#read 6, iclass 13, count 0 2006.162.08:23:43.06#ibcon#end of sib2, iclass 13, count 0 2006.162.08:23:43.06#ibcon#*after write, iclass 13, count 0 2006.162.08:23:43.06#ibcon#*before return 0, iclass 13, count 0 2006.162.08:23:43.06#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:23:43.06#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.162.08:23:43.06#ibcon#about to clear, iclass 13 cls_cnt 0 2006.162.08:23:43.06#ibcon#cleared, iclass 13 cls_cnt 0 2006.162.08:23:43.06$vc4f8/vblo=4,712.99 2006.162.08:23:43.06#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.162.08:23:43.06#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.162.08:23:43.06#ibcon#ireg 17 cls_cnt 0 2006.162.08:23:43.06#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:23:43.06#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:23:43.06#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:23:43.06#ibcon#enter wrdev, iclass 15, count 0 2006.162.08:23:43.06#ibcon#first serial, iclass 15, count 0 2006.162.08:23:43.06#ibcon#enter sib2, iclass 15, count 0 2006.162.08:23:43.06#ibcon#flushed, iclass 15, count 0 2006.162.08:23:43.06#ibcon#about to write, iclass 15, count 0 2006.162.08:23:43.06#ibcon#wrote, iclass 15, count 0 2006.162.08:23:43.06#ibcon#about to read 3, iclass 15, count 0 2006.162.08:23:43.08#ibcon#read 3, iclass 15, count 0 2006.162.08:23:43.08#ibcon#about to read 4, iclass 15, count 0 2006.162.08:23:43.08#ibcon#read 4, iclass 15, count 0 2006.162.08:23:43.08#ibcon#about to read 5, iclass 15, count 0 2006.162.08:23:43.08#ibcon#read 5, iclass 15, count 0 2006.162.08:23:43.08#ibcon#about to read 6, iclass 15, count 0 2006.162.08:23:43.08#ibcon#read 6, iclass 15, count 0 2006.162.08:23:43.08#ibcon#end of sib2, iclass 15, count 0 2006.162.08:23:43.08#ibcon#*mode == 0, iclass 15, count 0 2006.162.08:23:43.08#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.162.08:23:43.08#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.08:23:43.08#ibcon#*before write, iclass 15, count 0 2006.162.08:23:43.08#ibcon#enter sib2, iclass 15, count 0 2006.162.08:23:43.08#ibcon#flushed, iclass 15, count 0 2006.162.08:23:43.08#ibcon#about to write, iclass 15, count 0 2006.162.08:23:43.08#ibcon#wrote, iclass 15, count 0 2006.162.08:23:43.08#ibcon#about to read 3, iclass 15, count 0 2006.162.08:23:43.12#ibcon#read 3, iclass 15, count 0 2006.162.08:23:43.12#ibcon#about to read 4, iclass 15, count 0 2006.162.08:23:43.12#ibcon#read 4, iclass 15, count 0 2006.162.08:23:43.12#ibcon#about to read 5, iclass 15, count 0 2006.162.08:23:43.12#ibcon#read 5, iclass 15, count 0 2006.162.08:23:43.12#ibcon#about to read 6, iclass 15, count 0 2006.162.08:23:43.12#ibcon#read 6, iclass 15, count 0 2006.162.08:23:43.12#ibcon#end of sib2, iclass 15, count 0 2006.162.08:23:43.12#ibcon#*after write, iclass 15, count 0 2006.162.08:23:43.12#ibcon#*before return 0, iclass 15, count 0 2006.162.08:23:43.12#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:23:43.12#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.162.08:23:43.12#ibcon#about to clear, iclass 15 cls_cnt 0 2006.162.08:23:43.12#ibcon#cleared, iclass 15 cls_cnt 0 2006.162.08:23:43.12$vc4f8/vb=4,4 2006.162.08:23:43.12#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.162.08:23:43.12#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.162.08:23:43.12#ibcon#ireg 11 cls_cnt 2 2006.162.08:23:43.12#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:23:43.18#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:23:43.18#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:23:43.18#ibcon#enter wrdev, iclass 17, count 2 2006.162.08:23:43.18#ibcon#first serial, iclass 17, count 2 2006.162.08:23:43.18#ibcon#enter sib2, iclass 17, count 2 2006.162.08:23:43.18#ibcon#flushed, iclass 17, count 2 2006.162.08:23:43.18#ibcon#about to write, iclass 17, count 2 2006.162.08:23:43.18#ibcon#wrote, iclass 17, count 2 2006.162.08:23:43.18#ibcon#about to read 3, iclass 17, count 2 2006.162.08:23:43.20#ibcon#read 3, iclass 17, count 2 2006.162.08:23:43.20#ibcon#about to read 4, iclass 17, count 2 2006.162.08:23:43.20#ibcon#read 4, iclass 17, count 2 2006.162.08:23:43.20#ibcon#about to read 5, iclass 17, count 2 2006.162.08:23:43.20#ibcon#read 5, iclass 17, count 2 2006.162.08:23:43.20#ibcon#about to read 6, iclass 17, count 2 2006.162.08:23:43.20#ibcon#read 6, iclass 17, count 2 2006.162.08:23:43.20#ibcon#end of sib2, iclass 17, count 2 2006.162.08:23:43.20#ibcon#*mode == 0, iclass 17, count 2 2006.162.08:23:43.20#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.162.08:23:43.20#ibcon#[27=AT04-04\r\n] 2006.162.08:23:43.20#ibcon#*before write, iclass 17, count 2 2006.162.08:23:43.20#ibcon#enter sib2, iclass 17, count 2 2006.162.08:23:43.20#ibcon#flushed, iclass 17, count 2 2006.162.08:23:43.20#ibcon#about to write, iclass 17, count 2 2006.162.08:23:43.20#ibcon#wrote, iclass 17, count 2 2006.162.08:23:43.20#ibcon#about to read 3, iclass 17, count 2 2006.162.08:23:43.23#ibcon#read 3, iclass 17, count 2 2006.162.08:23:43.23#ibcon#about to read 4, iclass 17, count 2 2006.162.08:23:43.23#ibcon#read 4, iclass 17, count 2 2006.162.08:23:43.23#ibcon#about to read 5, iclass 17, count 2 2006.162.08:23:43.23#ibcon#read 5, iclass 17, count 2 2006.162.08:23:43.23#ibcon#about to read 6, iclass 17, count 2 2006.162.08:23:43.23#ibcon#read 6, iclass 17, count 2 2006.162.08:23:43.23#ibcon#end of sib2, iclass 17, count 2 2006.162.08:23:43.23#ibcon#*after write, iclass 17, count 2 2006.162.08:23:43.23#ibcon#*before return 0, iclass 17, count 2 2006.162.08:23:43.23#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:23:43.23#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.162.08:23:43.23#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.162.08:23:43.23#ibcon#ireg 7 cls_cnt 0 2006.162.08:23:43.23#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:23:43.35#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:23:43.35#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:23:43.35#ibcon#enter wrdev, iclass 17, count 0 2006.162.08:23:43.35#ibcon#first serial, iclass 17, count 0 2006.162.08:23:43.35#ibcon#enter sib2, iclass 17, count 0 2006.162.08:23:43.35#ibcon#flushed, iclass 17, count 0 2006.162.08:23:43.35#ibcon#about to write, iclass 17, count 0 2006.162.08:23:43.35#ibcon#wrote, iclass 17, count 0 2006.162.08:23:43.35#ibcon#about to read 3, iclass 17, count 0 2006.162.08:23:43.37#ibcon#read 3, iclass 17, count 0 2006.162.08:23:43.37#ibcon#about to read 4, iclass 17, count 0 2006.162.08:23:43.37#ibcon#read 4, iclass 17, count 0 2006.162.08:23:43.37#ibcon#about to read 5, iclass 17, count 0 2006.162.08:23:43.37#ibcon#read 5, iclass 17, count 0 2006.162.08:23:43.37#ibcon#about to read 6, iclass 17, count 0 2006.162.08:23:43.37#ibcon#read 6, iclass 17, count 0 2006.162.08:23:43.37#ibcon#end of sib2, iclass 17, count 0 2006.162.08:23:43.37#ibcon#*mode == 0, iclass 17, count 0 2006.162.08:23:43.37#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.162.08:23:43.37#ibcon#[27=USB\r\n] 2006.162.08:23:43.37#ibcon#*before write, iclass 17, count 0 2006.162.08:23:43.37#ibcon#enter sib2, iclass 17, count 0 2006.162.08:23:43.37#ibcon#flushed, iclass 17, count 0 2006.162.08:23:43.37#ibcon#about to write, iclass 17, count 0 2006.162.08:23:43.37#ibcon#wrote, iclass 17, count 0 2006.162.08:23:43.37#ibcon#about to read 3, iclass 17, count 0 2006.162.08:23:43.40#ibcon#read 3, iclass 17, count 0 2006.162.08:23:43.40#ibcon#about to read 4, iclass 17, count 0 2006.162.08:23:43.40#ibcon#read 4, iclass 17, count 0 2006.162.08:23:43.40#ibcon#about to read 5, iclass 17, count 0 2006.162.08:23:43.40#ibcon#read 5, iclass 17, count 0 2006.162.08:23:43.40#ibcon#about to read 6, iclass 17, count 0 2006.162.08:23:43.40#ibcon#read 6, iclass 17, count 0 2006.162.08:23:43.40#ibcon#end of sib2, iclass 17, count 0 2006.162.08:23:43.40#ibcon#*after write, iclass 17, count 0 2006.162.08:23:43.40#ibcon#*before return 0, iclass 17, count 0 2006.162.08:23:43.40#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:23:43.40#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.162.08:23:43.40#ibcon#about to clear, iclass 17 cls_cnt 0 2006.162.08:23:43.40#ibcon#cleared, iclass 17 cls_cnt 0 2006.162.08:23:43.40$vc4f8/vblo=5,744.99 2006.162.08:23:43.40#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.162.08:23:43.40#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.162.08:23:43.40#ibcon#ireg 17 cls_cnt 0 2006.162.08:23:43.40#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:23:43.40#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:23:43.40#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:23:43.40#ibcon#enter wrdev, iclass 19, count 0 2006.162.08:23:43.40#ibcon#first serial, iclass 19, count 0 2006.162.08:23:43.40#ibcon#enter sib2, iclass 19, count 0 2006.162.08:23:43.40#ibcon#flushed, iclass 19, count 0 2006.162.08:23:43.40#ibcon#about to write, iclass 19, count 0 2006.162.08:23:43.40#ibcon#wrote, iclass 19, count 0 2006.162.08:23:43.40#ibcon#about to read 3, iclass 19, count 0 2006.162.08:23:43.42#ibcon#read 3, iclass 19, count 0 2006.162.08:23:43.42#ibcon#about to read 4, iclass 19, count 0 2006.162.08:23:43.42#ibcon#read 4, iclass 19, count 0 2006.162.08:23:43.42#ibcon#about to read 5, iclass 19, count 0 2006.162.08:23:43.42#ibcon#read 5, iclass 19, count 0 2006.162.08:23:43.42#ibcon#about to read 6, iclass 19, count 0 2006.162.08:23:43.42#ibcon#read 6, iclass 19, count 0 2006.162.08:23:43.42#ibcon#end of sib2, iclass 19, count 0 2006.162.08:23:43.42#ibcon#*mode == 0, iclass 19, count 0 2006.162.08:23:43.42#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.162.08:23:43.42#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.08:23:43.42#ibcon#*before write, iclass 19, count 0 2006.162.08:23:43.42#ibcon#enter sib2, iclass 19, count 0 2006.162.08:23:43.42#ibcon#flushed, iclass 19, count 0 2006.162.08:23:43.42#ibcon#about to write, iclass 19, count 0 2006.162.08:23:43.42#ibcon#wrote, iclass 19, count 0 2006.162.08:23:43.42#ibcon#about to read 3, iclass 19, count 0 2006.162.08:23:43.46#ibcon#read 3, iclass 19, count 0 2006.162.08:23:43.46#ibcon#about to read 4, iclass 19, count 0 2006.162.08:23:43.46#ibcon#read 4, iclass 19, count 0 2006.162.08:23:43.46#ibcon#about to read 5, iclass 19, count 0 2006.162.08:23:43.46#ibcon#read 5, iclass 19, count 0 2006.162.08:23:43.46#ibcon#about to read 6, iclass 19, count 0 2006.162.08:23:43.46#ibcon#read 6, iclass 19, count 0 2006.162.08:23:43.46#ibcon#end of sib2, iclass 19, count 0 2006.162.08:23:43.46#ibcon#*after write, iclass 19, count 0 2006.162.08:23:43.46#ibcon#*before return 0, iclass 19, count 0 2006.162.08:23:43.46#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:23:43.46#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.162.08:23:43.46#ibcon#about to clear, iclass 19 cls_cnt 0 2006.162.08:23:43.46#ibcon#cleared, iclass 19 cls_cnt 0 2006.162.08:23:43.46$vc4f8/vb=5,4 2006.162.08:23:43.46#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.162.08:23:43.46#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.162.08:23:43.46#ibcon#ireg 11 cls_cnt 2 2006.162.08:23:43.46#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.162.08:23:43.52#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.162.08:23:43.52#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.162.08:23:43.52#ibcon#enter wrdev, iclass 21, count 2 2006.162.08:23:43.52#ibcon#first serial, iclass 21, count 2 2006.162.08:23:43.52#ibcon#enter sib2, iclass 21, count 2 2006.162.08:23:43.52#ibcon#flushed, iclass 21, count 2 2006.162.08:23:43.52#ibcon#about to write, iclass 21, count 2 2006.162.08:23:43.52#ibcon#wrote, iclass 21, count 2 2006.162.08:23:43.52#ibcon#about to read 3, iclass 21, count 2 2006.162.08:23:43.54#ibcon#read 3, iclass 21, count 2 2006.162.08:23:43.54#ibcon#about to read 4, iclass 21, count 2 2006.162.08:23:43.54#ibcon#read 4, iclass 21, count 2 2006.162.08:23:43.54#ibcon#about to read 5, iclass 21, count 2 2006.162.08:23:43.54#ibcon#read 5, iclass 21, count 2 2006.162.08:23:43.54#ibcon#about to read 6, iclass 21, count 2 2006.162.08:23:43.54#ibcon#read 6, iclass 21, count 2 2006.162.08:23:43.54#ibcon#end of sib2, iclass 21, count 2 2006.162.08:23:43.54#ibcon#*mode == 0, iclass 21, count 2 2006.162.08:23:43.54#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.162.08:23:43.54#ibcon#[27=AT05-04\r\n] 2006.162.08:23:43.54#ibcon#*before write, iclass 21, count 2 2006.162.08:23:43.54#ibcon#enter sib2, iclass 21, count 2 2006.162.08:23:43.54#ibcon#flushed, iclass 21, count 2 2006.162.08:23:43.54#ibcon#about to write, iclass 21, count 2 2006.162.08:23:43.54#ibcon#wrote, iclass 21, count 2 2006.162.08:23:43.54#ibcon#about to read 3, iclass 21, count 2 2006.162.08:23:43.58#ibcon#read 3, iclass 21, count 2 2006.162.08:23:43.58#ibcon#about to read 4, iclass 21, count 2 2006.162.08:23:43.58#ibcon#read 4, iclass 21, count 2 2006.162.08:23:43.58#ibcon#about to read 5, iclass 21, count 2 2006.162.08:23:43.58#ibcon#read 5, iclass 21, count 2 2006.162.08:23:43.58#ibcon#about to read 6, iclass 21, count 2 2006.162.08:23:43.58#ibcon#read 6, iclass 21, count 2 2006.162.08:23:43.58#ibcon#end of sib2, iclass 21, count 2 2006.162.08:23:43.58#ibcon#*after write, iclass 21, count 2 2006.162.08:23:43.58#ibcon#*before return 0, iclass 21, count 2 2006.162.08:23:43.58#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.162.08:23:43.58#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.162.08:23:43.58#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.162.08:23:43.58#ibcon#ireg 7 cls_cnt 0 2006.162.08:23:43.58#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.162.08:23:43.70#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.162.08:23:43.70#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.162.08:23:43.70#ibcon#enter wrdev, iclass 21, count 0 2006.162.08:23:43.70#ibcon#first serial, iclass 21, count 0 2006.162.08:23:43.70#ibcon#enter sib2, iclass 21, count 0 2006.162.08:23:43.70#ibcon#flushed, iclass 21, count 0 2006.162.08:23:43.70#ibcon#about to write, iclass 21, count 0 2006.162.08:23:43.70#ibcon#wrote, iclass 21, count 0 2006.162.08:23:43.70#ibcon#about to read 3, iclass 21, count 0 2006.162.08:23:43.72#ibcon#read 3, iclass 21, count 0 2006.162.08:23:43.72#ibcon#about to read 4, iclass 21, count 0 2006.162.08:23:43.72#ibcon#read 4, iclass 21, count 0 2006.162.08:23:43.72#ibcon#about to read 5, iclass 21, count 0 2006.162.08:23:43.72#ibcon#read 5, iclass 21, count 0 2006.162.08:23:43.72#ibcon#about to read 6, iclass 21, count 0 2006.162.08:23:43.72#ibcon#read 6, iclass 21, count 0 2006.162.08:23:43.72#ibcon#end of sib2, iclass 21, count 0 2006.162.08:23:43.72#ibcon#*mode == 0, iclass 21, count 0 2006.162.08:23:43.72#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.162.08:23:43.72#ibcon#[27=USB\r\n] 2006.162.08:23:43.72#ibcon#*before write, iclass 21, count 0 2006.162.08:23:43.72#ibcon#enter sib2, iclass 21, count 0 2006.162.08:23:43.72#ibcon#flushed, iclass 21, count 0 2006.162.08:23:43.72#ibcon#about to write, iclass 21, count 0 2006.162.08:23:43.72#ibcon#wrote, iclass 21, count 0 2006.162.08:23:43.72#ibcon#about to read 3, iclass 21, count 0 2006.162.08:23:43.75#ibcon#read 3, iclass 21, count 0 2006.162.08:23:43.75#ibcon#about to read 4, iclass 21, count 0 2006.162.08:23:43.75#ibcon#read 4, iclass 21, count 0 2006.162.08:23:43.75#ibcon#about to read 5, iclass 21, count 0 2006.162.08:23:43.75#ibcon#read 5, iclass 21, count 0 2006.162.08:23:43.75#ibcon#about to read 6, iclass 21, count 0 2006.162.08:23:43.75#ibcon#read 6, iclass 21, count 0 2006.162.08:23:43.75#ibcon#end of sib2, iclass 21, count 0 2006.162.08:23:43.75#ibcon#*after write, iclass 21, count 0 2006.162.08:23:43.75#ibcon#*before return 0, iclass 21, count 0 2006.162.08:23:43.75#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.162.08:23:43.75#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.162.08:23:43.75#ibcon#about to clear, iclass 21 cls_cnt 0 2006.162.08:23:43.75#ibcon#cleared, iclass 21 cls_cnt 0 2006.162.08:23:43.75$vc4f8/vblo=6,752.99 2006.162.08:23:43.75#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.162.08:23:43.75#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.162.08:23:43.75#ibcon#ireg 17 cls_cnt 0 2006.162.08:23:43.75#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.162.08:23:43.75#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.162.08:23:43.75#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.162.08:23:43.75#ibcon#enter wrdev, iclass 23, count 0 2006.162.08:23:43.75#ibcon#first serial, iclass 23, count 0 2006.162.08:23:43.75#ibcon#enter sib2, iclass 23, count 0 2006.162.08:23:43.75#ibcon#flushed, iclass 23, count 0 2006.162.08:23:43.75#ibcon#about to write, iclass 23, count 0 2006.162.08:23:43.75#ibcon#wrote, iclass 23, count 0 2006.162.08:23:43.75#ibcon#about to read 3, iclass 23, count 0 2006.162.08:23:43.77#ibcon#read 3, iclass 23, count 0 2006.162.08:23:43.77#ibcon#about to read 4, iclass 23, count 0 2006.162.08:23:43.77#ibcon#read 4, iclass 23, count 0 2006.162.08:23:43.77#ibcon#about to read 5, iclass 23, count 0 2006.162.08:23:43.77#ibcon#read 5, iclass 23, count 0 2006.162.08:23:43.77#ibcon#about to read 6, iclass 23, count 0 2006.162.08:23:43.77#ibcon#read 6, iclass 23, count 0 2006.162.08:23:43.77#ibcon#end of sib2, iclass 23, count 0 2006.162.08:23:43.77#ibcon#*mode == 0, iclass 23, count 0 2006.162.08:23:43.77#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.162.08:23:43.77#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.08:23:43.77#ibcon#*before write, iclass 23, count 0 2006.162.08:23:43.77#ibcon#enter sib2, iclass 23, count 0 2006.162.08:23:43.77#ibcon#flushed, iclass 23, count 0 2006.162.08:23:43.77#ibcon#about to write, iclass 23, count 0 2006.162.08:23:43.77#ibcon#wrote, iclass 23, count 0 2006.162.08:23:43.77#ibcon#about to read 3, iclass 23, count 0 2006.162.08:23:43.81#ibcon#read 3, iclass 23, count 0 2006.162.08:23:43.81#ibcon#about to read 4, iclass 23, count 0 2006.162.08:23:43.81#ibcon#read 4, iclass 23, count 0 2006.162.08:23:43.81#ibcon#about to read 5, iclass 23, count 0 2006.162.08:23:43.81#ibcon#read 5, iclass 23, count 0 2006.162.08:23:43.81#ibcon#about to read 6, iclass 23, count 0 2006.162.08:23:43.81#ibcon#read 6, iclass 23, count 0 2006.162.08:23:43.81#ibcon#end of sib2, iclass 23, count 0 2006.162.08:23:43.81#ibcon#*after write, iclass 23, count 0 2006.162.08:23:43.81#ibcon#*before return 0, iclass 23, count 0 2006.162.08:23:43.81#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.162.08:23:43.81#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.162.08:23:43.81#ibcon#about to clear, iclass 23 cls_cnt 0 2006.162.08:23:43.81#ibcon#cleared, iclass 23 cls_cnt 0 2006.162.08:23:43.81$vc4f8/vb=6,4 2006.162.08:23:43.81#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.162.08:23:43.81#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.162.08:23:43.81#ibcon#ireg 11 cls_cnt 2 2006.162.08:23:43.81#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.162.08:23:43.87#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.162.08:23:43.87#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.162.08:23:43.87#ibcon#enter wrdev, iclass 25, count 2 2006.162.08:23:43.87#ibcon#first serial, iclass 25, count 2 2006.162.08:23:43.87#ibcon#enter sib2, iclass 25, count 2 2006.162.08:23:43.87#ibcon#flushed, iclass 25, count 2 2006.162.08:23:43.87#ibcon#about to write, iclass 25, count 2 2006.162.08:23:43.87#ibcon#wrote, iclass 25, count 2 2006.162.08:23:43.87#ibcon#about to read 3, iclass 25, count 2 2006.162.08:23:43.89#ibcon#read 3, iclass 25, count 2 2006.162.08:23:43.89#ibcon#about to read 4, iclass 25, count 2 2006.162.08:23:43.89#ibcon#read 4, iclass 25, count 2 2006.162.08:23:43.89#ibcon#about to read 5, iclass 25, count 2 2006.162.08:23:43.89#ibcon#read 5, iclass 25, count 2 2006.162.08:23:43.89#ibcon#about to read 6, iclass 25, count 2 2006.162.08:23:43.89#ibcon#read 6, iclass 25, count 2 2006.162.08:23:43.89#ibcon#end of sib2, iclass 25, count 2 2006.162.08:23:43.89#ibcon#*mode == 0, iclass 25, count 2 2006.162.08:23:43.89#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.162.08:23:43.89#ibcon#[27=AT06-04\r\n] 2006.162.08:23:43.89#ibcon#*before write, iclass 25, count 2 2006.162.08:23:43.89#ibcon#enter sib2, iclass 25, count 2 2006.162.08:23:43.89#ibcon#flushed, iclass 25, count 2 2006.162.08:23:43.89#ibcon#about to write, iclass 25, count 2 2006.162.08:23:43.89#ibcon#wrote, iclass 25, count 2 2006.162.08:23:43.89#ibcon#about to read 3, iclass 25, count 2 2006.162.08:23:43.92#ibcon#read 3, iclass 25, count 2 2006.162.08:23:43.92#ibcon#about to read 4, iclass 25, count 2 2006.162.08:23:43.92#ibcon#read 4, iclass 25, count 2 2006.162.08:23:43.92#ibcon#about to read 5, iclass 25, count 2 2006.162.08:23:43.92#ibcon#read 5, iclass 25, count 2 2006.162.08:23:43.92#ibcon#about to read 6, iclass 25, count 2 2006.162.08:23:43.92#ibcon#read 6, iclass 25, count 2 2006.162.08:23:43.92#ibcon#end of sib2, iclass 25, count 2 2006.162.08:23:43.92#ibcon#*after write, iclass 25, count 2 2006.162.08:23:43.92#ibcon#*before return 0, iclass 25, count 2 2006.162.08:23:43.92#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.162.08:23:43.92#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.162.08:23:43.92#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.162.08:23:43.92#ibcon#ireg 7 cls_cnt 0 2006.162.08:23:43.92#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.162.08:23:44.04#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.162.08:23:44.04#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.162.08:23:44.04#ibcon#enter wrdev, iclass 25, count 0 2006.162.08:23:44.04#ibcon#first serial, iclass 25, count 0 2006.162.08:23:44.04#ibcon#enter sib2, iclass 25, count 0 2006.162.08:23:44.04#ibcon#flushed, iclass 25, count 0 2006.162.08:23:44.04#ibcon#about to write, iclass 25, count 0 2006.162.08:23:44.04#ibcon#wrote, iclass 25, count 0 2006.162.08:23:44.04#ibcon#about to read 3, iclass 25, count 0 2006.162.08:23:44.06#ibcon#read 3, iclass 25, count 0 2006.162.08:23:44.06#ibcon#about to read 4, iclass 25, count 0 2006.162.08:23:44.06#ibcon#read 4, iclass 25, count 0 2006.162.08:23:44.06#ibcon#about to read 5, iclass 25, count 0 2006.162.08:23:44.06#ibcon#read 5, iclass 25, count 0 2006.162.08:23:44.06#ibcon#about to read 6, iclass 25, count 0 2006.162.08:23:44.06#ibcon#read 6, iclass 25, count 0 2006.162.08:23:44.06#ibcon#end of sib2, iclass 25, count 0 2006.162.08:23:44.06#ibcon#*mode == 0, iclass 25, count 0 2006.162.08:23:44.06#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.162.08:23:44.06#ibcon#[27=USB\r\n] 2006.162.08:23:44.06#ibcon#*before write, iclass 25, count 0 2006.162.08:23:44.06#ibcon#enter sib2, iclass 25, count 0 2006.162.08:23:44.06#ibcon#flushed, iclass 25, count 0 2006.162.08:23:44.06#ibcon#about to write, iclass 25, count 0 2006.162.08:23:44.06#ibcon#wrote, iclass 25, count 0 2006.162.08:23:44.06#ibcon#about to read 3, iclass 25, count 0 2006.162.08:23:44.09#ibcon#read 3, iclass 25, count 0 2006.162.08:23:44.09#ibcon#about to read 4, iclass 25, count 0 2006.162.08:23:44.09#ibcon#read 4, iclass 25, count 0 2006.162.08:23:44.09#ibcon#about to read 5, iclass 25, count 0 2006.162.08:23:44.09#ibcon#read 5, iclass 25, count 0 2006.162.08:23:44.09#ibcon#about to read 6, iclass 25, count 0 2006.162.08:23:44.09#ibcon#read 6, iclass 25, count 0 2006.162.08:23:44.09#ibcon#end of sib2, iclass 25, count 0 2006.162.08:23:44.09#ibcon#*after write, iclass 25, count 0 2006.162.08:23:44.09#ibcon#*before return 0, iclass 25, count 0 2006.162.08:23:44.09#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.162.08:23:44.09#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.162.08:23:44.09#ibcon#about to clear, iclass 25 cls_cnt 0 2006.162.08:23:44.09#ibcon#cleared, iclass 25 cls_cnt 0 2006.162.08:23:44.09$vc4f8/vabw=wide 2006.162.08:23:44.09#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.162.08:23:44.09#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.162.08:23:44.09#ibcon#ireg 8 cls_cnt 0 2006.162.08:23:44.09#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.162.08:23:44.09#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.162.08:23:44.09#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.162.08:23:44.09#ibcon#enter wrdev, iclass 27, count 0 2006.162.08:23:44.09#ibcon#first serial, iclass 27, count 0 2006.162.08:23:44.09#ibcon#enter sib2, iclass 27, count 0 2006.162.08:23:44.09#ibcon#flushed, iclass 27, count 0 2006.162.08:23:44.09#ibcon#about to write, iclass 27, count 0 2006.162.08:23:44.09#ibcon#wrote, iclass 27, count 0 2006.162.08:23:44.09#ibcon#about to read 3, iclass 27, count 0 2006.162.08:23:44.11#ibcon#read 3, iclass 27, count 0 2006.162.08:23:44.11#ibcon#about to read 4, iclass 27, count 0 2006.162.08:23:44.11#ibcon#read 4, iclass 27, count 0 2006.162.08:23:44.11#ibcon#about to read 5, iclass 27, count 0 2006.162.08:23:44.11#ibcon#read 5, iclass 27, count 0 2006.162.08:23:44.11#ibcon#about to read 6, iclass 27, count 0 2006.162.08:23:44.11#ibcon#read 6, iclass 27, count 0 2006.162.08:23:44.11#ibcon#end of sib2, iclass 27, count 0 2006.162.08:23:44.11#ibcon#*mode == 0, iclass 27, count 0 2006.162.08:23:44.11#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.162.08:23:44.11#ibcon#[25=BW32\r\n] 2006.162.08:23:44.11#ibcon#*before write, iclass 27, count 0 2006.162.08:23:44.11#ibcon#enter sib2, iclass 27, count 0 2006.162.08:23:44.11#ibcon#flushed, iclass 27, count 0 2006.162.08:23:44.11#ibcon#about to write, iclass 27, count 0 2006.162.08:23:44.11#ibcon#wrote, iclass 27, count 0 2006.162.08:23:44.11#ibcon#about to read 3, iclass 27, count 0 2006.162.08:23:44.14#ibcon#read 3, iclass 27, count 0 2006.162.08:23:44.14#ibcon#about to read 4, iclass 27, count 0 2006.162.08:23:44.14#ibcon#read 4, iclass 27, count 0 2006.162.08:23:44.14#ibcon#about to read 5, iclass 27, count 0 2006.162.08:23:44.14#ibcon#read 5, iclass 27, count 0 2006.162.08:23:44.14#ibcon#about to read 6, iclass 27, count 0 2006.162.08:23:44.14#ibcon#read 6, iclass 27, count 0 2006.162.08:23:44.14#ibcon#end of sib2, iclass 27, count 0 2006.162.08:23:44.14#ibcon#*after write, iclass 27, count 0 2006.162.08:23:44.14#ibcon#*before return 0, iclass 27, count 0 2006.162.08:23:44.14#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.162.08:23:44.14#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.162.08:23:44.14#ibcon#about to clear, iclass 27 cls_cnt 0 2006.162.08:23:44.14#ibcon#cleared, iclass 27 cls_cnt 0 2006.162.08:23:44.14$vc4f8/vbbw=wide 2006.162.08:23:44.14#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.162.08:23:44.14#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.162.08:23:44.14#ibcon#ireg 8 cls_cnt 0 2006.162.08:23:44.14#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:23:44.21#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:23:44.21#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:23:44.21#ibcon#enter wrdev, iclass 29, count 0 2006.162.08:23:44.21#ibcon#first serial, iclass 29, count 0 2006.162.08:23:44.21#ibcon#enter sib2, iclass 29, count 0 2006.162.08:23:44.21#ibcon#flushed, iclass 29, count 0 2006.162.08:23:44.21#ibcon#about to write, iclass 29, count 0 2006.162.08:23:44.21#ibcon#wrote, iclass 29, count 0 2006.162.08:23:44.21#ibcon#about to read 3, iclass 29, count 0 2006.162.08:23:44.23#ibcon#read 3, iclass 29, count 0 2006.162.08:23:44.23#ibcon#about to read 4, iclass 29, count 0 2006.162.08:23:44.23#ibcon#read 4, iclass 29, count 0 2006.162.08:23:44.23#ibcon#about to read 5, iclass 29, count 0 2006.162.08:23:44.23#ibcon#read 5, iclass 29, count 0 2006.162.08:23:44.23#ibcon#about to read 6, iclass 29, count 0 2006.162.08:23:44.23#ibcon#read 6, iclass 29, count 0 2006.162.08:23:44.23#ibcon#end of sib2, iclass 29, count 0 2006.162.08:23:44.23#ibcon#*mode == 0, iclass 29, count 0 2006.162.08:23:44.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.162.08:23:44.23#ibcon#[27=BW32\r\n] 2006.162.08:23:44.23#ibcon#*before write, iclass 29, count 0 2006.162.08:23:44.23#ibcon#enter sib2, iclass 29, count 0 2006.162.08:23:44.23#ibcon#flushed, iclass 29, count 0 2006.162.08:23:44.23#ibcon#about to write, iclass 29, count 0 2006.162.08:23:44.23#ibcon#wrote, iclass 29, count 0 2006.162.08:23:44.23#ibcon#about to read 3, iclass 29, count 0 2006.162.08:23:44.26#ibcon#read 3, iclass 29, count 0 2006.162.08:23:44.26#ibcon#about to read 4, iclass 29, count 0 2006.162.08:23:44.26#ibcon#read 4, iclass 29, count 0 2006.162.08:23:44.26#ibcon#about to read 5, iclass 29, count 0 2006.162.08:23:44.26#ibcon#read 5, iclass 29, count 0 2006.162.08:23:44.26#ibcon#about to read 6, iclass 29, count 0 2006.162.08:23:44.26#ibcon#read 6, iclass 29, count 0 2006.162.08:23:44.26#ibcon#end of sib2, iclass 29, count 0 2006.162.08:23:44.26#ibcon#*after write, iclass 29, count 0 2006.162.08:23:44.26#ibcon#*before return 0, iclass 29, count 0 2006.162.08:23:44.26#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:23:44.26#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:23:44.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.162.08:23:44.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.162.08:23:44.26$4f8m12a/ifd4f 2006.162.08:23:44.26$ifd4f/lo= 2006.162.08:23:44.26$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.08:23:44.26$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.08:23:44.26$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.08:23:44.26$ifd4f/patch= 2006.162.08:23:44.26$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.08:23:44.26$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.08:23:44.26$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.08:23:44.26$4f8m12a/"form=m,16.000,1:2 2006.162.08:23:44.26$4f8m12a/"tpicd 2006.162.08:23:44.26$4f8m12a/echo=off 2006.162.08:23:44.26$4f8m12a/xlog=off 2006.162.08:23:44.26:!2006.162.08:24:10 2006.162.08:23:53.13#trakl#Source acquired 2006.162.08:23:55.13#flagr#flagr/antenna,acquired 2006.162.08:24:10.00:preob 2006.162.08:24:11.13/onsource/TRACKING 2006.162.08:24:11.13:!2006.162.08:24:20 2006.162.08:24:20.00:data_valid=on 2006.162.08:24:20.00:midob 2006.162.08:24:20.13/onsource/TRACKING 2006.162.08:24:20.13/wx/17.82,1006.9,100 2006.162.08:24:20.33/cable/+6.5355E-03 2006.162.08:24:21.42/va/01,08,usb,yes,32,34 2006.162.08:24:21.42/va/02,07,usb,yes,33,34 2006.162.08:24:21.42/va/03,06,usb,yes,35,35 2006.162.08:24:21.42/va/04,07,usb,yes,34,36 2006.162.08:24:21.42/va/05,07,usb,yes,35,37 2006.162.08:24:21.42/va/06,06,usb,yes,35,34 2006.162.08:24:21.42/va/07,06,usb,yes,35,35 2006.162.08:24:21.42/va/08,07,usb,yes,33,33 2006.162.08:24:21.65/valo/01,532.99,yes,locked 2006.162.08:24:21.65/valo/02,572.99,yes,locked 2006.162.08:24:21.65/valo/03,672.99,yes,locked 2006.162.08:24:21.65/valo/04,832.99,yes,locked 2006.162.08:24:21.65/valo/05,652.99,yes,locked 2006.162.08:24:21.65/valo/06,772.99,yes,locked 2006.162.08:24:21.65/valo/07,832.99,yes,locked 2006.162.08:24:21.65/valo/08,852.99,yes,locked 2006.162.08:24:22.74/vb/01,04,usb,yes,28,27 2006.162.08:24:22.74/vb/02,04,usb,yes,30,32 2006.162.08:24:22.74/vb/03,04,usb,yes,27,30 2006.162.08:24:22.74/vb/04,04,usb,yes,27,28 2006.162.08:24:22.74/vb/05,04,usb,yes,26,30 2006.162.08:24:22.74/vb/06,04,usb,yes,27,30 2006.162.08:24:22.74/vb/07,04,usb,yes,29,29 2006.162.08:24:22.74/vb/08,04,usb,yes,27,30 2006.162.08:24:22.97/vblo/01,632.99,yes,locked 2006.162.08:24:22.97/vblo/02,640.99,yes,locked 2006.162.08:24:22.97/vblo/03,656.99,yes,locked 2006.162.08:24:22.97/vblo/04,712.99,yes,locked 2006.162.08:24:22.97/vblo/05,744.99,yes,locked 2006.162.08:24:22.97/vblo/06,752.99,yes,locked 2006.162.08:24:22.97/vblo/07,734.99,yes,locked 2006.162.08:24:22.97/vblo/08,744.99,yes,locked 2006.162.08:24:23.12/vabw/8 2006.162.08:24:23.27/vbbw/8 2006.162.08:24:23.36/xfe/off,on,14.2 2006.162.08:24:23.74/ifatt/23,28,28,28 2006.162.08:24:24.08/fmout-gps/S +4.51E-07 2006.162.08:24:24.12:!2006.162.08:25:30 2006.162.08:25:30.00:data_valid=off 2006.162.08:25:30.00:postob 2006.162.08:25:30.08/cable/+6.5372E-03 2006.162.08:25:30.08/wx/17.81,1006.8,100 2006.162.08:25:31.08/fmout-gps/S +4.52E-07 2006.162.08:25:31.08:scan_name=162-0826,k06162,60 2006.162.08:25:31.08:source=0748+126,075052.05,123104.8,2000.0,ccw 2006.162.08:25:32.14#flagr#flagr/antenna,new-source 2006.162.08:25:32.14:checkk5 2006.162.08:25:32.58/chk_autoobs//k5ts1/ autoobs is running! 2006.162.08:25:32.96/chk_autoobs//k5ts2/ autoobs is running! 2006.162.08:25:33.37/chk_autoobs//k5ts3/ autoobs is running! 2006.162.08:25:33.78/chk_autoobs//k5ts4/ autoobs is running! 2006.162.08:25:34.21/chk_obsdata//k5ts1/T1620824??a.dat file size is correct (nominal:560MB, actual:560MB). 2006.162.08:25:34.63/chk_obsdata//k5ts2/T1620824??b.dat file size is correct (nominal:560MB, actual:560MB). 2006.162.08:25:35.06/chk_obsdata//k5ts3/T1620824??c.dat file size is correct (nominal:560MB, actual:560MB). 2006.162.08:25:35.50/chk_obsdata//k5ts4/T1620824??d.dat file size is correct (nominal:560MB, actual:560MB). 2006.162.08:25:36.27/k5log//k5ts1_log_newline 2006.162.08:25:37.04/k5log//k5ts2_log_newline 2006.162.08:25:37.78/k5log//k5ts3_log_newline 2006.162.08:25:38.55/k5log//k5ts4_log_newline 2006.162.08:25:38.58/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.08:25:38.58:4f8m12a=3 2006.162.08:25:38.58$4f8m12a/echo=on 2006.162.08:25:38.58$4f8m12a/pcalon 2006.162.08:25:38.58$pcalon/"no phase cal control is implemented here 2006.162.08:25:38.58$4f8m12a/"tpicd=stop 2006.162.08:25:38.58$4f8m12a/vc4f8 2006.162.08:25:38.58$vc4f8/valo=1,532.99 2006.162.08:25:38.58#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.162.08:25:38.58#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.162.08:25:38.58#ibcon#ireg 17 cls_cnt 0 2006.162.08:25:38.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:25:38.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:25:38.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:25:38.58#ibcon#enter wrdev, iclass 40, count 0 2006.162.08:25:38.58#ibcon#first serial, iclass 40, count 0 2006.162.08:25:38.58#ibcon#enter sib2, iclass 40, count 0 2006.162.08:25:38.58#ibcon#flushed, iclass 40, count 0 2006.162.08:25:38.58#ibcon#about to write, iclass 40, count 0 2006.162.08:25:38.58#ibcon#wrote, iclass 40, count 0 2006.162.08:25:38.58#ibcon#about to read 3, iclass 40, count 0 2006.162.08:25:38.62#ibcon#read 3, iclass 40, count 0 2006.162.08:25:38.62#ibcon#about to read 4, iclass 40, count 0 2006.162.08:25:38.62#ibcon#read 4, iclass 40, count 0 2006.162.08:25:38.62#ibcon#about to read 5, iclass 40, count 0 2006.162.08:25:38.62#ibcon#read 5, iclass 40, count 0 2006.162.08:25:38.62#ibcon#about to read 6, iclass 40, count 0 2006.162.08:25:38.62#ibcon#read 6, iclass 40, count 0 2006.162.08:25:38.62#ibcon#end of sib2, iclass 40, count 0 2006.162.08:25:38.62#ibcon#*mode == 0, iclass 40, count 0 2006.162.08:25:38.62#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.162.08:25:38.62#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.08:25:38.62#ibcon#*before write, iclass 40, count 0 2006.162.08:25:38.62#ibcon#enter sib2, iclass 40, count 0 2006.162.08:25:38.62#ibcon#flushed, iclass 40, count 0 2006.162.08:25:38.62#ibcon#about to write, iclass 40, count 0 2006.162.08:25:38.62#ibcon#wrote, iclass 40, count 0 2006.162.08:25:38.62#ibcon#about to read 3, iclass 40, count 0 2006.162.08:25:38.67#ibcon#read 3, iclass 40, count 0 2006.162.08:25:38.67#ibcon#about to read 4, iclass 40, count 0 2006.162.08:25:38.67#ibcon#read 4, iclass 40, count 0 2006.162.08:25:38.67#ibcon#about to read 5, iclass 40, count 0 2006.162.08:25:38.67#ibcon#read 5, iclass 40, count 0 2006.162.08:25:38.67#ibcon#about to read 6, iclass 40, count 0 2006.162.08:25:38.67#ibcon#read 6, iclass 40, count 0 2006.162.08:25:38.67#ibcon#end of sib2, iclass 40, count 0 2006.162.08:25:38.67#ibcon#*after write, iclass 40, count 0 2006.162.08:25:38.67#ibcon#*before return 0, iclass 40, count 0 2006.162.08:25:38.67#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:25:38.67#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:25:38.67#ibcon#about to clear, iclass 40 cls_cnt 0 2006.162.08:25:38.67#ibcon#cleared, iclass 40 cls_cnt 0 2006.162.08:25:38.67$vc4f8/va=1,8 2006.162.08:25:38.67#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.162.08:25:38.67#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.162.08:25:38.67#ibcon#ireg 11 cls_cnt 2 2006.162.08:25:38.67#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:25:38.67#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:25:38.67#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:25:38.67#ibcon#enter wrdev, iclass 4, count 2 2006.162.08:25:38.67#ibcon#first serial, iclass 4, count 2 2006.162.08:25:38.67#ibcon#enter sib2, iclass 4, count 2 2006.162.08:25:38.67#ibcon#flushed, iclass 4, count 2 2006.162.08:25:38.67#ibcon#about to write, iclass 4, count 2 2006.162.08:25:38.67#ibcon#wrote, iclass 4, count 2 2006.162.08:25:38.67#ibcon#about to read 3, iclass 4, count 2 2006.162.08:25:38.69#ibcon#read 3, iclass 4, count 2 2006.162.08:25:38.69#ibcon#about to read 4, iclass 4, count 2 2006.162.08:25:38.69#ibcon#read 4, iclass 4, count 2 2006.162.08:25:38.69#ibcon#about to read 5, iclass 4, count 2 2006.162.08:25:38.69#ibcon#read 5, iclass 4, count 2 2006.162.08:25:38.69#ibcon#about to read 6, iclass 4, count 2 2006.162.08:25:38.69#ibcon#read 6, iclass 4, count 2 2006.162.08:25:38.69#ibcon#end of sib2, iclass 4, count 2 2006.162.08:25:38.69#ibcon#*mode == 0, iclass 4, count 2 2006.162.08:25:38.69#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.162.08:25:38.69#ibcon#[25=AT01-08\r\n] 2006.162.08:25:38.69#ibcon#*before write, iclass 4, count 2 2006.162.08:25:38.69#ibcon#enter sib2, iclass 4, count 2 2006.162.08:25:38.69#ibcon#flushed, iclass 4, count 2 2006.162.08:25:38.69#ibcon#about to write, iclass 4, count 2 2006.162.08:25:38.69#ibcon#wrote, iclass 4, count 2 2006.162.08:25:38.69#ibcon#about to read 3, iclass 4, count 2 2006.162.08:25:38.72#ibcon#read 3, iclass 4, count 2 2006.162.08:25:38.72#ibcon#about to read 4, iclass 4, count 2 2006.162.08:25:38.72#ibcon#read 4, iclass 4, count 2 2006.162.08:25:38.72#ibcon#about to read 5, iclass 4, count 2 2006.162.08:25:38.72#ibcon#read 5, iclass 4, count 2 2006.162.08:25:38.72#ibcon#about to read 6, iclass 4, count 2 2006.162.08:25:38.72#ibcon#read 6, iclass 4, count 2 2006.162.08:25:38.72#ibcon#end of sib2, iclass 4, count 2 2006.162.08:25:38.72#ibcon#*after write, iclass 4, count 2 2006.162.08:25:38.72#ibcon#*before return 0, iclass 4, count 2 2006.162.08:25:38.72#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:25:38.72#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:25:38.72#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.162.08:25:38.72#ibcon#ireg 7 cls_cnt 0 2006.162.08:25:38.72#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:25:38.84#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:25:38.84#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:25:38.84#ibcon#enter wrdev, iclass 4, count 0 2006.162.08:25:38.84#ibcon#first serial, iclass 4, count 0 2006.162.08:25:38.84#ibcon#enter sib2, iclass 4, count 0 2006.162.08:25:38.84#ibcon#flushed, iclass 4, count 0 2006.162.08:25:38.84#ibcon#about to write, iclass 4, count 0 2006.162.08:25:38.84#ibcon#wrote, iclass 4, count 0 2006.162.08:25:38.84#ibcon#about to read 3, iclass 4, count 0 2006.162.08:25:38.86#ibcon#read 3, iclass 4, count 0 2006.162.08:25:38.86#ibcon#about to read 4, iclass 4, count 0 2006.162.08:25:38.86#ibcon#read 4, iclass 4, count 0 2006.162.08:25:38.86#ibcon#about to read 5, iclass 4, count 0 2006.162.08:25:38.86#ibcon#read 5, iclass 4, count 0 2006.162.08:25:38.86#ibcon#about to read 6, iclass 4, count 0 2006.162.08:25:38.86#ibcon#read 6, iclass 4, count 0 2006.162.08:25:38.86#ibcon#end of sib2, iclass 4, count 0 2006.162.08:25:38.86#ibcon#*mode == 0, iclass 4, count 0 2006.162.08:25:38.86#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.162.08:25:38.86#ibcon#[25=USB\r\n] 2006.162.08:25:38.86#ibcon#*before write, iclass 4, count 0 2006.162.08:25:38.86#ibcon#enter sib2, iclass 4, count 0 2006.162.08:25:38.86#ibcon#flushed, iclass 4, count 0 2006.162.08:25:38.86#ibcon#about to write, iclass 4, count 0 2006.162.08:25:38.86#ibcon#wrote, iclass 4, count 0 2006.162.08:25:38.86#ibcon#about to read 3, iclass 4, count 0 2006.162.08:25:38.89#ibcon#read 3, iclass 4, count 0 2006.162.08:25:38.89#ibcon#about to read 4, iclass 4, count 0 2006.162.08:25:38.89#ibcon#read 4, iclass 4, count 0 2006.162.08:25:38.89#ibcon#about to read 5, iclass 4, count 0 2006.162.08:25:38.89#ibcon#read 5, iclass 4, count 0 2006.162.08:25:38.89#ibcon#about to read 6, iclass 4, count 0 2006.162.08:25:38.89#ibcon#read 6, iclass 4, count 0 2006.162.08:25:38.89#ibcon#end of sib2, iclass 4, count 0 2006.162.08:25:38.89#ibcon#*after write, iclass 4, count 0 2006.162.08:25:38.89#ibcon#*before return 0, iclass 4, count 0 2006.162.08:25:38.89#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:25:38.89#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:25:38.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.162.08:25:38.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.162.08:25:38.89$vc4f8/valo=2,572.99 2006.162.08:25:38.89#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.162.08:25:38.89#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.162.08:25:38.89#ibcon#ireg 17 cls_cnt 0 2006.162.08:25:38.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:25:38.89#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:25:38.89#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:25:38.89#ibcon#enter wrdev, iclass 6, count 0 2006.162.08:25:38.89#ibcon#first serial, iclass 6, count 0 2006.162.08:25:38.89#ibcon#enter sib2, iclass 6, count 0 2006.162.08:25:38.89#ibcon#flushed, iclass 6, count 0 2006.162.08:25:38.89#ibcon#about to write, iclass 6, count 0 2006.162.08:25:38.89#ibcon#wrote, iclass 6, count 0 2006.162.08:25:38.89#ibcon#about to read 3, iclass 6, count 0 2006.162.08:25:38.91#ibcon#read 3, iclass 6, count 0 2006.162.08:25:38.91#ibcon#about to read 4, iclass 6, count 0 2006.162.08:25:38.91#ibcon#read 4, iclass 6, count 0 2006.162.08:25:38.91#ibcon#about to read 5, iclass 6, count 0 2006.162.08:25:38.91#ibcon#read 5, iclass 6, count 0 2006.162.08:25:38.91#ibcon#about to read 6, iclass 6, count 0 2006.162.08:25:38.91#ibcon#read 6, iclass 6, count 0 2006.162.08:25:38.91#ibcon#end of sib2, iclass 6, count 0 2006.162.08:25:38.91#ibcon#*mode == 0, iclass 6, count 0 2006.162.08:25:38.91#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.162.08:25:38.91#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.08:25:38.91#ibcon#*before write, iclass 6, count 0 2006.162.08:25:38.91#ibcon#enter sib2, iclass 6, count 0 2006.162.08:25:38.91#ibcon#flushed, iclass 6, count 0 2006.162.08:25:38.91#ibcon#about to write, iclass 6, count 0 2006.162.08:25:38.91#ibcon#wrote, iclass 6, count 0 2006.162.08:25:38.91#ibcon#about to read 3, iclass 6, count 0 2006.162.08:25:38.96#ibcon#read 3, iclass 6, count 0 2006.162.08:25:38.96#ibcon#about to read 4, iclass 6, count 0 2006.162.08:25:38.96#ibcon#read 4, iclass 6, count 0 2006.162.08:25:38.96#ibcon#about to read 5, iclass 6, count 0 2006.162.08:25:38.96#ibcon#read 5, iclass 6, count 0 2006.162.08:25:38.96#ibcon#about to read 6, iclass 6, count 0 2006.162.08:25:38.96#ibcon#read 6, iclass 6, count 0 2006.162.08:25:38.96#ibcon#end of sib2, iclass 6, count 0 2006.162.08:25:38.96#ibcon#*after write, iclass 6, count 0 2006.162.08:25:38.96#ibcon#*before return 0, iclass 6, count 0 2006.162.08:25:38.96#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:25:38.96#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:25:38.96#ibcon#about to clear, iclass 6 cls_cnt 0 2006.162.08:25:38.96#ibcon#cleared, iclass 6 cls_cnt 0 2006.162.08:25:38.96$vc4f8/va=2,7 2006.162.08:25:38.96#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.162.08:25:38.96#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.162.08:25:38.96#ibcon#ireg 11 cls_cnt 2 2006.162.08:25:38.96#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:25:39.01#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:25:39.01#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:25:39.01#ibcon#enter wrdev, iclass 10, count 2 2006.162.08:25:39.01#ibcon#first serial, iclass 10, count 2 2006.162.08:25:39.01#ibcon#enter sib2, iclass 10, count 2 2006.162.08:25:39.01#ibcon#flushed, iclass 10, count 2 2006.162.08:25:39.01#ibcon#about to write, iclass 10, count 2 2006.162.08:25:39.01#ibcon#wrote, iclass 10, count 2 2006.162.08:25:39.01#ibcon#about to read 3, iclass 10, count 2 2006.162.08:25:39.03#ibcon#read 3, iclass 10, count 2 2006.162.08:25:39.03#ibcon#about to read 4, iclass 10, count 2 2006.162.08:25:39.03#ibcon#read 4, iclass 10, count 2 2006.162.08:25:39.03#ibcon#about to read 5, iclass 10, count 2 2006.162.08:25:39.03#ibcon#read 5, iclass 10, count 2 2006.162.08:25:39.03#ibcon#about to read 6, iclass 10, count 2 2006.162.08:25:39.03#ibcon#read 6, iclass 10, count 2 2006.162.08:25:39.03#ibcon#end of sib2, iclass 10, count 2 2006.162.08:25:39.03#ibcon#*mode == 0, iclass 10, count 2 2006.162.08:25:39.03#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.162.08:25:39.03#ibcon#[25=AT02-07\r\n] 2006.162.08:25:39.03#ibcon#*before write, iclass 10, count 2 2006.162.08:25:39.03#ibcon#enter sib2, iclass 10, count 2 2006.162.08:25:39.03#ibcon#flushed, iclass 10, count 2 2006.162.08:25:39.03#ibcon#about to write, iclass 10, count 2 2006.162.08:25:39.03#ibcon#wrote, iclass 10, count 2 2006.162.08:25:39.03#ibcon#about to read 3, iclass 10, count 2 2006.162.08:25:39.06#ibcon#read 3, iclass 10, count 2 2006.162.08:25:39.06#ibcon#about to read 4, iclass 10, count 2 2006.162.08:25:39.06#ibcon#read 4, iclass 10, count 2 2006.162.08:25:39.06#ibcon#about to read 5, iclass 10, count 2 2006.162.08:25:39.06#ibcon#read 5, iclass 10, count 2 2006.162.08:25:39.06#ibcon#about to read 6, iclass 10, count 2 2006.162.08:25:39.06#ibcon#read 6, iclass 10, count 2 2006.162.08:25:39.06#ibcon#end of sib2, iclass 10, count 2 2006.162.08:25:39.06#ibcon#*after write, iclass 10, count 2 2006.162.08:25:39.06#ibcon#*before return 0, iclass 10, count 2 2006.162.08:25:39.06#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:25:39.06#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:25:39.06#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.162.08:25:39.06#ibcon#ireg 7 cls_cnt 0 2006.162.08:25:39.06#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:25:39.18#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:25:39.18#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:25:39.18#ibcon#enter wrdev, iclass 10, count 0 2006.162.08:25:39.18#ibcon#first serial, iclass 10, count 0 2006.162.08:25:39.18#ibcon#enter sib2, iclass 10, count 0 2006.162.08:25:39.18#ibcon#flushed, iclass 10, count 0 2006.162.08:25:39.18#ibcon#about to write, iclass 10, count 0 2006.162.08:25:39.18#ibcon#wrote, iclass 10, count 0 2006.162.08:25:39.18#ibcon#about to read 3, iclass 10, count 0 2006.162.08:25:39.20#ibcon#read 3, iclass 10, count 0 2006.162.08:25:39.20#ibcon#about to read 4, iclass 10, count 0 2006.162.08:25:39.20#ibcon#read 4, iclass 10, count 0 2006.162.08:25:39.20#ibcon#about to read 5, iclass 10, count 0 2006.162.08:25:39.20#ibcon#read 5, iclass 10, count 0 2006.162.08:25:39.20#ibcon#about to read 6, iclass 10, count 0 2006.162.08:25:39.20#ibcon#read 6, iclass 10, count 0 2006.162.08:25:39.20#ibcon#end of sib2, iclass 10, count 0 2006.162.08:25:39.20#ibcon#*mode == 0, iclass 10, count 0 2006.162.08:25:39.20#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.162.08:25:39.20#ibcon#[25=USB\r\n] 2006.162.08:25:39.20#ibcon#*before write, iclass 10, count 0 2006.162.08:25:39.20#ibcon#enter sib2, iclass 10, count 0 2006.162.08:25:39.20#ibcon#flushed, iclass 10, count 0 2006.162.08:25:39.20#ibcon#about to write, iclass 10, count 0 2006.162.08:25:39.20#ibcon#wrote, iclass 10, count 0 2006.162.08:25:39.20#ibcon#about to read 3, iclass 10, count 0 2006.162.08:25:39.23#ibcon#read 3, iclass 10, count 0 2006.162.08:25:39.23#ibcon#about to read 4, iclass 10, count 0 2006.162.08:25:39.23#ibcon#read 4, iclass 10, count 0 2006.162.08:25:39.23#ibcon#about to read 5, iclass 10, count 0 2006.162.08:25:39.23#ibcon#read 5, iclass 10, count 0 2006.162.08:25:39.23#ibcon#about to read 6, iclass 10, count 0 2006.162.08:25:39.23#ibcon#read 6, iclass 10, count 0 2006.162.08:25:39.23#ibcon#end of sib2, iclass 10, count 0 2006.162.08:25:39.23#ibcon#*after write, iclass 10, count 0 2006.162.08:25:39.23#ibcon#*before return 0, iclass 10, count 0 2006.162.08:25:39.23#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:25:39.23#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:25:39.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.162.08:25:39.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.162.08:25:39.23$vc4f8/valo=3,672.99 2006.162.08:25:39.23#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.162.08:25:39.23#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.162.08:25:39.23#ibcon#ireg 17 cls_cnt 0 2006.162.08:25:39.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:25:39.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:25:39.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:25:39.23#ibcon#enter wrdev, iclass 12, count 0 2006.162.08:25:39.23#ibcon#first serial, iclass 12, count 0 2006.162.08:25:39.23#ibcon#enter sib2, iclass 12, count 0 2006.162.08:25:39.23#ibcon#flushed, iclass 12, count 0 2006.162.08:25:39.23#ibcon#about to write, iclass 12, count 0 2006.162.08:25:39.23#ibcon#wrote, iclass 12, count 0 2006.162.08:25:39.23#ibcon#about to read 3, iclass 12, count 0 2006.162.08:25:39.25#ibcon#read 3, iclass 12, count 0 2006.162.08:25:39.25#ibcon#about to read 4, iclass 12, count 0 2006.162.08:25:39.25#ibcon#read 4, iclass 12, count 0 2006.162.08:25:39.25#ibcon#about to read 5, iclass 12, count 0 2006.162.08:25:39.25#ibcon#read 5, iclass 12, count 0 2006.162.08:25:39.25#ibcon#about to read 6, iclass 12, count 0 2006.162.08:25:39.25#ibcon#read 6, iclass 12, count 0 2006.162.08:25:39.25#ibcon#end of sib2, iclass 12, count 0 2006.162.08:25:39.25#ibcon#*mode == 0, iclass 12, count 0 2006.162.08:25:39.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.162.08:25:39.25#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.08:25:39.25#ibcon#*before write, iclass 12, count 0 2006.162.08:25:39.25#ibcon#enter sib2, iclass 12, count 0 2006.162.08:25:39.25#ibcon#flushed, iclass 12, count 0 2006.162.08:25:39.25#ibcon#about to write, iclass 12, count 0 2006.162.08:25:39.25#ibcon#wrote, iclass 12, count 0 2006.162.08:25:39.25#ibcon#about to read 3, iclass 12, count 0 2006.162.08:25:39.29#ibcon#read 3, iclass 12, count 0 2006.162.08:25:39.29#ibcon#about to read 4, iclass 12, count 0 2006.162.08:25:39.29#ibcon#read 4, iclass 12, count 0 2006.162.08:25:39.29#ibcon#about to read 5, iclass 12, count 0 2006.162.08:25:39.29#ibcon#read 5, iclass 12, count 0 2006.162.08:25:39.29#ibcon#about to read 6, iclass 12, count 0 2006.162.08:25:39.29#ibcon#read 6, iclass 12, count 0 2006.162.08:25:39.29#ibcon#end of sib2, iclass 12, count 0 2006.162.08:25:39.29#ibcon#*after write, iclass 12, count 0 2006.162.08:25:39.29#ibcon#*before return 0, iclass 12, count 0 2006.162.08:25:39.29#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:25:39.29#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:25:39.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.162.08:25:39.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.162.08:25:39.29$vc4f8/va=3,6 2006.162.08:25:39.29#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.162.08:25:39.29#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.162.08:25:39.29#ibcon#ireg 11 cls_cnt 2 2006.162.08:25:39.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.162.08:25:39.35#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.162.08:25:39.35#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.162.08:25:39.35#ibcon#enter wrdev, iclass 14, count 2 2006.162.08:25:39.35#ibcon#first serial, iclass 14, count 2 2006.162.08:25:39.35#ibcon#enter sib2, iclass 14, count 2 2006.162.08:25:39.35#ibcon#flushed, iclass 14, count 2 2006.162.08:25:39.35#ibcon#about to write, iclass 14, count 2 2006.162.08:25:39.35#ibcon#wrote, iclass 14, count 2 2006.162.08:25:39.35#ibcon#about to read 3, iclass 14, count 2 2006.162.08:25:39.37#ibcon#read 3, iclass 14, count 2 2006.162.08:25:39.37#ibcon#about to read 4, iclass 14, count 2 2006.162.08:25:39.37#ibcon#read 4, iclass 14, count 2 2006.162.08:25:39.37#ibcon#about to read 5, iclass 14, count 2 2006.162.08:25:39.37#ibcon#read 5, iclass 14, count 2 2006.162.08:25:39.37#ibcon#about to read 6, iclass 14, count 2 2006.162.08:25:39.37#ibcon#read 6, iclass 14, count 2 2006.162.08:25:39.37#ibcon#end of sib2, iclass 14, count 2 2006.162.08:25:39.37#ibcon#*mode == 0, iclass 14, count 2 2006.162.08:25:39.37#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.162.08:25:39.37#ibcon#[25=AT03-06\r\n] 2006.162.08:25:39.37#ibcon#*before write, iclass 14, count 2 2006.162.08:25:39.37#ibcon#enter sib2, iclass 14, count 2 2006.162.08:25:39.37#ibcon#flushed, iclass 14, count 2 2006.162.08:25:39.37#ibcon#about to write, iclass 14, count 2 2006.162.08:25:39.37#ibcon#wrote, iclass 14, count 2 2006.162.08:25:39.37#ibcon#about to read 3, iclass 14, count 2 2006.162.08:25:39.40#ibcon#read 3, iclass 14, count 2 2006.162.08:25:39.40#ibcon#about to read 4, iclass 14, count 2 2006.162.08:25:39.40#ibcon#read 4, iclass 14, count 2 2006.162.08:25:39.40#ibcon#about to read 5, iclass 14, count 2 2006.162.08:25:39.40#ibcon#read 5, iclass 14, count 2 2006.162.08:25:39.40#ibcon#about to read 6, iclass 14, count 2 2006.162.08:25:39.40#ibcon#read 6, iclass 14, count 2 2006.162.08:25:39.40#ibcon#end of sib2, iclass 14, count 2 2006.162.08:25:39.40#ibcon#*after write, iclass 14, count 2 2006.162.08:25:39.40#ibcon#*before return 0, iclass 14, count 2 2006.162.08:25:39.40#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.162.08:25:39.40#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.162.08:25:39.40#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.162.08:25:39.40#ibcon#ireg 7 cls_cnt 0 2006.162.08:25:39.40#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.162.08:25:39.52#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.162.08:25:39.52#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.162.08:25:39.52#ibcon#enter wrdev, iclass 14, count 0 2006.162.08:25:39.52#ibcon#first serial, iclass 14, count 0 2006.162.08:25:39.52#ibcon#enter sib2, iclass 14, count 0 2006.162.08:25:39.52#ibcon#flushed, iclass 14, count 0 2006.162.08:25:39.52#ibcon#about to write, iclass 14, count 0 2006.162.08:25:39.52#ibcon#wrote, iclass 14, count 0 2006.162.08:25:39.52#ibcon#about to read 3, iclass 14, count 0 2006.162.08:25:39.54#ibcon#read 3, iclass 14, count 0 2006.162.08:25:39.54#ibcon#about to read 4, iclass 14, count 0 2006.162.08:25:39.54#ibcon#read 4, iclass 14, count 0 2006.162.08:25:39.54#ibcon#about to read 5, iclass 14, count 0 2006.162.08:25:39.54#ibcon#read 5, iclass 14, count 0 2006.162.08:25:39.54#ibcon#about to read 6, iclass 14, count 0 2006.162.08:25:39.54#ibcon#read 6, iclass 14, count 0 2006.162.08:25:39.54#ibcon#end of sib2, iclass 14, count 0 2006.162.08:25:39.54#ibcon#*mode == 0, iclass 14, count 0 2006.162.08:25:39.54#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.08:25:39.54#ibcon#[25=USB\r\n] 2006.162.08:25:39.54#ibcon#*before write, iclass 14, count 0 2006.162.08:25:39.54#ibcon#enter sib2, iclass 14, count 0 2006.162.08:25:39.54#ibcon#flushed, iclass 14, count 0 2006.162.08:25:39.54#ibcon#about to write, iclass 14, count 0 2006.162.08:25:39.54#ibcon#wrote, iclass 14, count 0 2006.162.08:25:39.54#ibcon#about to read 3, iclass 14, count 0 2006.162.08:25:39.57#ibcon#read 3, iclass 14, count 0 2006.162.08:25:39.57#ibcon#about to read 4, iclass 14, count 0 2006.162.08:25:39.57#ibcon#read 4, iclass 14, count 0 2006.162.08:25:39.57#ibcon#about to read 5, iclass 14, count 0 2006.162.08:25:39.57#ibcon#read 5, iclass 14, count 0 2006.162.08:25:39.57#ibcon#about to read 6, iclass 14, count 0 2006.162.08:25:39.57#ibcon#read 6, iclass 14, count 0 2006.162.08:25:39.57#ibcon#end of sib2, iclass 14, count 0 2006.162.08:25:39.57#ibcon#*after write, iclass 14, count 0 2006.162.08:25:39.57#ibcon#*before return 0, iclass 14, count 0 2006.162.08:25:39.57#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.162.08:25:39.57#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.162.08:25:39.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.08:25:39.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.08:25:39.57$vc4f8/valo=4,832.99 2006.162.08:25:39.57#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.162.08:25:39.57#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.162.08:25:39.57#ibcon#ireg 17 cls_cnt 0 2006.162.08:25:39.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:25:39.57#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:25:39.57#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:25:39.57#ibcon#enter wrdev, iclass 16, count 0 2006.162.08:25:39.57#ibcon#first serial, iclass 16, count 0 2006.162.08:25:39.57#ibcon#enter sib2, iclass 16, count 0 2006.162.08:25:39.57#ibcon#flushed, iclass 16, count 0 2006.162.08:25:39.57#ibcon#about to write, iclass 16, count 0 2006.162.08:25:39.57#ibcon#wrote, iclass 16, count 0 2006.162.08:25:39.57#ibcon#about to read 3, iclass 16, count 0 2006.162.08:25:39.59#ibcon#read 3, iclass 16, count 0 2006.162.08:25:39.59#ibcon#about to read 4, iclass 16, count 0 2006.162.08:25:39.59#ibcon#read 4, iclass 16, count 0 2006.162.08:25:39.59#ibcon#about to read 5, iclass 16, count 0 2006.162.08:25:39.59#ibcon#read 5, iclass 16, count 0 2006.162.08:25:39.59#ibcon#about to read 6, iclass 16, count 0 2006.162.08:25:39.59#ibcon#read 6, iclass 16, count 0 2006.162.08:25:39.59#ibcon#end of sib2, iclass 16, count 0 2006.162.08:25:39.59#ibcon#*mode == 0, iclass 16, count 0 2006.162.08:25:39.59#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.162.08:25:39.59#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.08:25:39.59#ibcon#*before write, iclass 16, count 0 2006.162.08:25:39.59#ibcon#enter sib2, iclass 16, count 0 2006.162.08:25:39.59#ibcon#flushed, iclass 16, count 0 2006.162.08:25:39.59#ibcon#about to write, iclass 16, count 0 2006.162.08:25:39.59#ibcon#wrote, iclass 16, count 0 2006.162.08:25:39.59#ibcon#about to read 3, iclass 16, count 0 2006.162.08:25:39.63#ibcon#read 3, iclass 16, count 0 2006.162.08:25:39.63#ibcon#about to read 4, iclass 16, count 0 2006.162.08:25:39.63#ibcon#read 4, iclass 16, count 0 2006.162.08:25:39.63#ibcon#about to read 5, iclass 16, count 0 2006.162.08:25:39.63#ibcon#read 5, iclass 16, count 0 2006.162.08:25:39.63#ibcon#about to read 6, iclass 16, count 0 2006.162.08:25:39.63#ibcon#read 6, iclass 16, count 0 2006.162.08:25:39.63#ibcon#end of sib2, iclass 16, count 0 2006.162.08:25:39.63#ibcon#*after write, iclass 16, count 0 2006.162.08:25:39.63#ibcon#*before return 0, iclass 16, count 0 2006.162.08:25:39.63#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:25:39.63#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:25:39.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.162.08:25:39.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.162.08:25:39.63$vc4f8/va=4,7 2006.162.08:25:39.63#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.162.08:25:39.63#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.162.08:25:39.63#ibcon#ireg 11 cls_cnt 2 2006.162.08:25:39.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:25:39.69#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:25:39.69#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:25:39.69#ibcon#enter wrdev, iclass 18, count 2 2006.162.08:25:39.69#ibcon#first serial, iclass 18, count 2 2006.162.08:25:39.69#ibcon#enter sib2, iclass 18, count 2 2006.162.08:25:39.69#ibcon#flushed, iclass 18, count 2 2006.162.08:25:39.69#ibcon#about to write, iclass 18, count 2 2006.162.08:25:39.69#ibcon#wrote, iclass 18, count 2 2006.162.08:25:39.69#ibcon#about to read 3, iclass 18, count 2 2006.162.08:25:39.71#ibcon#read 3, iclass 18, count 2 2006.162.08:25:39.71#ibcon#about to read 4, iclass 18, count 2 2006.162.08:25:39.71#ibcon#read 4, iclass 18, count 2 2006.162.08:25:39.71#ibcon#about to read 5, iclass 18, count 2 2006.162.08:25:39.71#ibcon#read 5, iclass 18, count 2 2006.162.08:25:39.71#ibcon#about to read 6, iclass 18, count 2 2006.162.08:25:39.71#ibcon#read 6, iclass 18, count 2 2006.162.08:25:39.71#ibcon#end of sib2, iclass 18, count 2 2006.162.08:25:39.71#ibcon#*mode == 0, iclass 18, count 2 2006.162.08:25:39.71#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.162.08:25:39.71#ibcon#[25=AT04-07\r\n] 2006.162.08:25:39.71#ibcon#*before write, iclass 18, count 2 2006.162.08:25:39.71#ibcon#enter sib2, iclass 18, count 2 2006.162.08:25:39.71#ibcon#flushed, iclass 18, count 2 2006.162.08:25:39.71#ibcon#about to write, iclass 18, count 2 2006.162.08:25:39.71#ibcon#wrote, iclass 18, count 2 2006.162.08:25:39.71#ibcon#about to read 3, iclass 18, count 2 2006.162.08:25:39.74#ibcon#read 3, iclass 18, count 2 2006.162.08:25:39.74#ibcon#about to read 4, iclass 18, count 2 2006.162.08:25:39.74#ibcon#read 4, iclass 18, count 2 2006.162.08:25:39.74#ibcon#about to read 5, iclass 18, count 2 2006.162.08:25:39.74#ibcon#read 5, iclass 18, count 2 2006.162.08:25:39.74#ibcon#about to read 6, iclass 18, count 2 2006.162.08:25:39.74#ibcon#read 6, iclass 18, count 2 2006.162.08:25:39.74#ibcon#end of sib2, iclass 18, count 2 2006.162.08:25:39.74#ibcon#*after write, iclass 18, count 2 2006.162.08:25:39.74#ibcon#*before return 0, iclass 18, count 2 2006.162.08:25:39.74#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:25:39.74#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:25:39.74#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.162.08:25:39.74#ibcon#ireg 7 cls_cnt 0 2006.162.08:25:39.74#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:25:39.86#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:25:39.86#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:25:39.86#ibcon#enter wrdev, iclass 18, count 0 2006.162.08:25:39.86#ibcon#first serial, iclass 18, count 0 2006.162.08:25:39.86#ibcon#enter sib2, iclass 18, count 0 2006.162.08:25:39.86#ibcon#flushed, iclass 18, count 0 2006.162.08:25:39.86#ibcon#about to write, iclass 18, count 0 2006.162.08:25:39.86#ibcon#wrote, iclass 18, count 0 2006.162.08:25:39.86#ibcon#about to read 3, iclass 18, count 0 2006.162.08:25:39.88#ibcon#read 3, iclass 18, count 0 2006.162.08:25:39.88#ibcon#about to read 4, iclass 18, count 0 2006.162.08:25:39.88#ibcon#read 4, iclass 18, count 0 2006.162.08:25:39.88#ibcon#about to read 5, iclass 18, count 0 2006.162.08:25:39.88#ibcon#read 5, iclass 18, count 0 2006.162.08:25:39.88#ibcon#about to read 6, iclass 18, count 0 2006.162.08:25:39.88#ibcon#read 6, iclass 18, count 0 2006.162.08:25:39.88#ibcon#end of sib2, iclass 18, count 0 2006.162.08:25:39.88#ibcon#*mode == 0, iclass 18, count 0 2006.162.08:25:39.88#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.162.08:25:39.88#ibcon#[25=USB\r\n] 2006.162.08:25:39.88#ibcon#*before write, iclass 18, count 0 2006.162.08:25:39.88#ibcon#enter sib2, iclass 18, count 0 2006.162.08:25:39.88#ibcon#flushed, iclass 18, count 0 2006.162.08:25:39.88#ibcon#about to write, iclass 18, count 0 2006.162.08:25:39.88#ibcon#wrote, iclass 18, count 0 2006.162.08:25:39.88#ibcon#about to read 3, iclass 18, count 0 2006.162.08:25:39.91#ibcon#read 3, iclass 18, count 0 2006.162.08:25:39.91#ibcon#about to read 4, iclass 18, count 0 2006.162.08:25:39.91#ibcon#read 4, iclass 18, count 0 2006.162.08:25:39.91#ibcon#about to read 5, iclass 18, count 0 2006.162.08:25:39.91#ibcon#read 5, iclass 18, count 0 2006.162.08:25:39.91#ibcon#about to read 6, iclass 18, count 0 2006.162.08:25:39.91#ibcon#read 6, iclass 18, count 0 2006.162.08:25:39.91#ibcon#end of sib2, iclass 18, count 0 2006.162.08:25:39.91#ibcon#*after write, iclass 18, count 0 2006.162.08:25:39.91#ibcon#*before return 0, iclass 18, count 0 2006.162.08:25:39.91#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:25:39.91#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:25:39.91#ibcon#about to clear, iclass 18 cls_cnt 0 2006.162.08:25:39.91#ibcon#cleared, iclass 18 cls_cnt 0 2006.162.08:25:39.91$vc4f8/valo=5,652.99 2006.162.08:25:39.91#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.162.08:25:39.91#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.162.08:25:39.91#ibcon#ireg 17 cls_cnt 0 2006.162.08:25:39.91#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:25:39.91#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:25:39.91#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:25:39.91#ibcon#enter wrdev, iclass 20, count 0 2006.162.08:25:39.91#ibcon#first serial, iclass 20, count 0 2006.162.08:25:39.91#ibcon#enter sib2, iclass 20, count 0 2006.162.08:25:39.91#ibcon#flushed, iclass 20, count 0 2006.162.08:25:39.91#ibcon#about to write, iclass 20, count 0 2006.162.08:25:39.91#ibcon#wrote, iclass 20, count 0 2006.162.08:25:39.91#ibcon#about to read 3, iclass 20, count 0 2006.162.08:25:39.93#ibcon#read 3, iclass 20, count 0 2006.162.08:25:39.93#ibcon#about to read 4, iclass 20, count 0 2006.162.08:25:39.93#ibcon#read 4, iclass 20, count 0 2006.162.08:25:39.93#ibcon#about to read 5, iclass 20, count 0 2006.162.08:25:39.93#ibcon#read 5, iclass 20, count 0 2006.162.08:25:39.93#ibcon#about to read 6, iclass 20, count 0 2006.162.08:25:39.93#ibcon#read 6, iclass 20, count 0 2006.162.08:25:39.93#ibcon#end of sib2, iclass 20, count 0 2006.162.08:25:39.93#ibcon#*mode == 0, iclass 20, count 0 2006.162.08:25:39.93#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.08:25:39.93#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.08:25:39.93#ibcon#*before write, iclass 20, count 0 2006.162.08:25:39.93#ibcon#enter sib2, iclass 20, count 0 2006.162.08:25:39.93#ibcon#flushed, iclass 20, count 0 2006.162.08:25:39.93#ibcon#about to write, iclass 20, count 0 2006.162.08:25:39.93#ibcon#wrote, iclass 20, count 0 2006.162.08:25:39.93#ibcon#about to read 3, iclass 20, count 0 2006.162.08:25:39.97#ibcon#read 3, iclass 20, count 0 2006.162.08:25:39.97#ibcon#about to read 4, iclass 20, count 0 2006.162.08:25:39.97#ibcon#read 4, iclass 20, count 0 2006.162.08:25:39.97#ibcon#about to read 5, iclass 20, count 0 2006.162.08:25:39.97#ibcon#read 5, iclass 20, count 0 2006.162.08:25:39.97#ibcon#about to read 6, iclass 20, count 0 2006.162.08:25:39.97#ibcon#read 6, iclass 20, count 0 2006.162.08:25:39.97#ibcon#end of sib2, iclass 20, count 0 2006.162.08:25:39.97#ibcon#*after write, iclass 20, count 0 2006.162.08:25:39.97#ibcon#*before return 0, iclass 20, count 0 2006.162.08:25:39.97#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:25:39.97#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:25:39.97#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.08:25:39.97#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.08:25:39.97$vc4f8/va=5,7 2006.162.08:25:39.97#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.162.08:25:39.97#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.162.08:25:39.97#ibcon#ireg 11 cls_cnt 2 2006.162.08:25:39.97#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:25:40.03#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:25:40.03#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:25:40.03#ibcon#enter wrdev, iclass 22, count 2 2006.162.08:25:40.03#ibcon#first serial, iclass 22, count 2 2006.162.08:25:40.03#ibcon#enter sib2, iclass 22, count 2 2006.162.08:25:40.03#ibcon#flushed, iclass 22, count 2 2006.162.08:25:40.03#ibcon#about to write, iclass 22, count 2 2006.162.08:25:40.03#ibcon#wrote, iclass 22, count 2 2006.162.08:25:40.03#ibcon#about to read 3, iclass 22, count 2 2006.162.08:25:40.05#ibcon#read 3, iclass 22, count 2 2006.162.08:25:40.05#ibcon#about to read 4, iclass 22, count 2 2006.162.08:25:40.05#ibcon#read 4, iclass 22, count 2 2006.162.08:25:40.05#ibcon#about to read 5, iclass 22, count 2 2006.162.08:25:40.05#ibcon#read 5, iclass 22, count 2 2006.162.08:25:40.05#ibcon#about to read 6, iclass 22, count 2 2006.162.08:25:40.05#ibcon#read 6, iclass 22, count 2 2006.162.08:25:40.05#ibcon#end of sib2, iclass 22, count 2 2006.162.08:25:40.05#ibcon#*mode == 0, iclass 22, count 2 2006.162.08:25:40.05#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.162.08:25:40.05#ibcon#[25=AT05-07\r\n] 2006.162.08:25:40.05#ibcon#*before write, iclass 22, count 2 2006.162.08:25:40.05#ibcon#enter sib2, iclass 22, count 2 2006.162.08:25:40.05#ibcon#flushed, iclass 22, count 2 2006.162.08:25:40.05#ibcon#about to write, iclass 22, count 2 2006.162.08:25:40.05#ibcon#wrote, iclass 22, count 2 2006.162.08:25:40.05#ibcon#about to read 3, iclass 22, count 2 2006.162.08:25:40.08#ibcon#read 3, iclass 22, count 2 2006.162.08:25:40.08#ibcon#about to read 4, iclass 22, count 2 2006.162.08:25:40.08#ibcon#read 4, iclass 22, count 2 2006.162.08:25:40.08#ibcon#about to read 5, iclass 22, count 2 2006.162.08:25:40.08#ibcon#read 5, iclass 22, count 2 2006.162.08:25:40.08#ibcon#about to read 6, iclass 22, count 2 2006.162.08:25:40.08#ibcon#read 6, iclass 22, count 2 2006.162.08:25:40.08#ibcon#end of sib2, iclass 22, count 2 2006.162.08:25:40.08#ibcon#*after write, iclass 22, count 2 2006.162.08:25:40.08#ibcon#*before return 0, iclass 22, count 2 2006.162.08:25:40.08#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:25:40.08#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:25:40.08#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.162.08:25:40.08#ibcon#ireg 7 cls_cnt 0 2006.162.08:25:40.08#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:25:40.20#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:25:40.20#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:25:40.20#ibcon#enter wrdev, iclass 22, count 0 2006.162.08:25:40.20#ibcon#first serial, iclass 22, count 0 2006.162.08:25:40.20#ibcon#enter sib2, iclass 22, count 0 2006.162.08:25:40.20#ibcon#flushed, iclass 22, count 0 2006.162.08:25:40.20#ibcon#about to write, iclass 22, count 0 2006.162.08:25:40.20#ibcon#wrote, iclass 22, count 0 2006.162.08:25:40.20#ibcon#about to read 3, iclass 22, count 0 2006.162.08:25:40.22#ibcon#read 3, iclass 22, count 0 2006.162.08:25:40.22#ibcon#about to read 4, iclass 22, count 0 2006.162.08:25:40.22#ibcon#read 4, iclass 22, count 0 2006.162.08:25:40.22#ibcon#about to read 5, iclass 22, count 0 2006.162.08:25:40.22#ibcon#read 5, iclass 22, count 0 2006.162.08:25:40.22#ibcon#about to read 6, iclass 22, count 0 2006.162.08:25:40.22#ibcon#read 6, iclass 22, count 0 2006.162.08:25:40.22#ibcon#end of sib2, iclass 22, count 0 2006.162.08:25:40.22#ibcon#*mode == 0, iclass 22, count 0 2006.162.08:25:40.22#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.08:25:40.22#ibcon#[25=USB\r\n] 2006.162.08:25:40.22#ibcon#*before write, iclass 22, count 0 2006.162.08:25:40.22#ibcon#enter sib2, iclass 22, count 0 2006.162.08:25:40.22#ibcon#flushed, iclass 22, count 0 2006.162.08:25:40.22#ibcon#about to write, iclass 22, count 0 2006.162.08:25:40.22#ibcon#wrote, iclass 22, count 0 2006.162.08:25:40.22#ibcon#about to read 3, iclass 22, count 0 2006.162.08:25:40.25#ibcon#read 3, iclass 22, count 0 2006.162.08:25:40.25#ibcon#about to read 4, iclass 22, count 0 2006.162.08:25:40.25#ibcon#read 4, iclass 22, count 0 2006.162.08:25:40.25#ibcon#about to read 5, iclass 22, count 0 2006.162.08:25:40.25#ibcon#read 5, iclass 22, count 0 2006.162.08:25:40.25#ibcon#about to read 6, iclass 22, count 0 2006.162.08:25:40.25#ibcon#read 6, iclass 22, count 0 2006.162.08:25:40.25#ibcon#end of sib2, iclass 22, count 0 2006.162.08:25:40.25#ibcon#*after write, iclass 22, count 0 2006.162.08:25:40.25#ibcon#*before return 0, iclass 22, count 0 2006.162.08:25:40.25#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:25:40.25#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:25:40.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.08:25:40.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.08:25:40.25$vc4f8/valo=6,772.99 2006.162.08:25:40.25#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.162.08:25:40.25#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.162.08:25:40.25#ibcon#ireg 17 cls_cnt 0 2006.162.08:25:40.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:25:40.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:25:40.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:25:40.25#ibcon#enter wrdev, iclass 24, count 0 2006.162.08:25:40.25#ibcon#first serial, iclass 24, count 0 2006.162.08:25:40.25#ibcon#enter sib2, iclass 24, count 0 2006.162.08:25:40.25#ibcon#flushed, iclass 24, count 0 2006.162.08:25:40.25#ibcon#about to write, iclass 24, count 0 2006.162.08:25:40.25#ibcon#wrote, iclass 24, count 0 2006.162.08:25:40.25#ibcon#about to read 3, iclass 24, count 0 2006.162.08:25:40.27#ibcon#read 3, iclass 24, count 0 2006.162.08:25:40.27#ibcon#about to read 4, iclass 24, count 0 2006.162.08:25:40.27#ibcon#read 4, iclass 24, count 0 2006.162.08:25:40.27#ibcon#about to read 5, iclass 24, count 0 2006.162.08:25:40.27#ibcon#read 5, iclass 24, count 0 2006.162.08:25:40.27#ibcon#about to read 6, iclass 24, count 0 2006.162.08:25:40.27#ibcon#read 6, iclass 24, count 0 2006.162.08:25:40.27#ibcon#end of sib2, iclass 24, count 0 2006.162.08:25:40.27#ibcon#*mode == 0, iclass 24, count 0 2006.162.08:25:40.27#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.08:25:40.27#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.08:25:40.27#ibcon#*before write, iclass 24, count 0 2006.162.08:25:40.27#ibcon#enter sib2, iclass 24, count 0 2006.162.08:25:40.27#ibcon#flushed, iclass 24, count 0 2006.162.08:25:40.27#ibcon#about to write, iclass 24, count 0 2006.162.08:25:40.27#ibcon#wrote, iclass 24, count 0 2006.162.08:25:40.27#ibcon#about to read 3, iclass 24, count 0 2006.162.08:25:40.31#ibcon#read 3, iclass 24, count 0 2006.162.08:25:40.31#ibcon#about to read 4, iclass 24, count 0 2006.162.08:25:40.31#ibcon#read 4, iclass 24, count 0 2006.162.08:25:40.31#ibcon#about to read 5, iclass 24, count 0 2006.162.08:25:40.31#ibcon#read 5, iclass 24, count 0 2006.162.08:25:40.31#ibcon#about to read 6, iclass 24, count 0 2006.162.08:25:40.31#ibcon#read 6, iclass 24, count 0 2006.162.08:25:40.31#ibcon#end of sib2, iclass 24, count 0 2006.162.08:25:40.31#ibcon#*after write, iclass 24, count 0 2006.162.08:25:40.31#ibcon#*before return 0, iclass 24, count 0 2006.162.08:25:40.31#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:25:40.31#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:25:40.31#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.08:25:40.31#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.08:25:40.31$vc4f8/va=6,6 2006.162.08:25:40.31#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.162.08:25:40.31#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.162.08:25:40.31#ibcon#ireg 11 cls_cnt 2 2006.162.08:25:40.31#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:25:40.37#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:25:40.37#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:25:40.37#ibcon#enter wrdev, iclass 26, count 2 2006.162.08:25:40.37#ibcon#first serial, iclass 26, count 2 2006.162.08:25:40.37#ibcon#enter sib2, iclass 26, count 2 2006.162.08:25:40.37#ibcon#flushed, iclass 26, count 2 2006.162.08:25:40.37#ibcon#about to write, iclass 26, count 2 2006.162.08:25:40.37#ibcon#wrote, iclass 26, count 2 2006.162.08:25:40.37#ibcon#about to read 3, iclass 26, count 2 2006.162.08:25:40.39#ibcon#read 3, iclass 26, count 2 2006.162.08:25:40.39#ibcon#about to read 4, iclass 26, count 2 2006.162.08:25:40.39#ibcon#read 4, iclass 26, count 2 2006.162.08:25:40.39#ibcon#about to read 5, iclass 26, count 2 2006.162.08:25:40.39#ibcon#read 5, iclass 26, count 2 2006.162.08:25:40.39#ibcon#about to read 6, iclass 26, count 2 2006.162.08:25:40.39#ibcon#read 6, iclass 26, count 2 2006.162.08:25:40.39#ibcon#end of sib2, iclass 26, count 2 2006.162.08:25:40.39#ibcon#*mode == 0, iclass 26, count 2 2006.162.08:25:40.39#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.162.08:25:40.39#ibcon#[25=AT06-06\r\n] 2006.162.08:25:40.39#ibcon#*before write, iclass 26, count 2 2006.162.08:25:40.39#ibcon#enter sib2, iclass 26, count 2 2006.162.08:25:40.39#ibcon#flushed, iclass 26, count 2 2006.162.08:25:40.39#ibcon#about to write, iclass 26, count 2 2006.162.08:25:40.39#ibcon#wrote, iclass 26, count 2 2006.162.08:25:40.39#ibcon#about to read 3, iclass 26, count 2 2006.162.08:25:40.42#ibcon#read 3, iclass 26, count 2 2006.162.08:25:40.42#ibcon#about to read 4, iclass 26, count 2 2006.162.08:25:40.42#ibcon#read 4, iclass 26, count 2 2006.162.08:25:40.42#ibcon#about to read 5, iclass 26, count 2 2006.162.08:25:40.42#ibcon#read 5, iclass 26, count 2 2006.162.08:25:40.42#ibcon#about to read 6, iclass 26, count 2 2006.162.08:25:40.42#ibcon#read 6, iclass 26, count 2 2006.162.08:25:40.42#ibcon#end of sib2, iclass 26, count 2 2006.162.08:25:40.42#ibcon#*after write, iclass 26, count 2 2006.162.08:25:40.42#ibcon#*before return 0, iclass 26, count 2 2006.162.08:25:40.42#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:25:40.42#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.162.08:25:40.42#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.162.08:25:40.42#ibcon#ireg 7 cls_cnt 0 2006.162.08:25:40.42#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:25:40.54#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:25:40.54#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:25:40.54#ibcon#enter wrdev, iclass 26, count 0 2006.162.08:25:40.54#ibcon#first serial, iclass 26, count 0 2006.162.08:25:40.54#ibcon#enter sib2, iclass 26, count 0 2006.162.08:25:40.54#ibcon#flushed, iclass 26, count 0 2006.162.08:25:40.54#ibcon#about to write, iclass 26, count 0 2006.162.08:25:40.54#ibcon#wrote, iclass 26, count 0 2006.162.08:25:40.54#ibcon#about to read 3, iclass 26, count 0 2006.162.08:25:40.56#ibcon#read 3, iclass 26, count 0 2006.162.08:25:40.56#ibcon#about to read 4, iclass 26, count 0 2006.162.08:25:40.56#ibcon#read 4, iclass 26, count 0 2006.162.08:25:40.56#ibcon#about to read 5, iclass 26, count 0 2006.162.08:25:40.56#ibcon#read 5, iclass 26, count 0 2006.162.08:25:40.56#ibcon#about to read 6, iclass 26, count 0 2006.162.08:25:40.56#ibcon#read 6, iclass 26, count 0 2006.162.08:25:40.56#ibcon#end of sib2, iclass 26, count 0 2006.162.08:25:40.56#ibcon#*mode == 0, iclass 26, count 0 2006.162.08:25:40.56#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.162.08:25:40.56#ibcon#[25=USB\r\n] 2006.162.08:25:40.56#ibcon#*before write, iclass 26, count 0 2006.162.08:25:40.56#ibcon#enter sib2, iclass 26, count 0 2006.162.08:25:40.56#ibcon#flushed, iclass 26, count 0 2006.162.08:25:40.56#ibcon#about to write, iclass 26, count 0 2006.162.08:25:40.56#ibcon#wrote, iclass 26, count 0 2006.162.08:25:40.56#ibcon#about to read 3, iclass 26, count 0 2006.162.08:25:40.59#ibcon#read 3, iclass 26, count 0 2006.162.08:25:40.59#ibcon#about to read 4, iclass 26, count 0 2006.162.08:25:40.59#ibcon#read 4, iclass 26, count 0 2006.162.08:25:40.59#ibcon#about to read 5, iclass 26, count 0 2006.162.08:25:40.59#ibcon#read 5, iclass 26, count 0 2006.162.08:25:40.59#ibcon#about to read 6, iclass 26, count 0 2006.162.08:25:40.59#ibcon#read 6, iclass 26, count 0 2006.162.08:25:40.59#ibcon#end of sib2, iclass 26, count 0 2006.162.08:25:40.59#ibcon#*after write, iclass 26, count 0 2006.162.08:25:40.59#ibcon#*before return 0, iclass 26, count 0 2006.162.08:25:40.59#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:25:40.59#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.162.08:25:40.59#ibcon#about to clear, iclass 26 cls_cnt 0 2006.162.08:25:40.59#ibcon#cleared, iclass 26 cls_cnt 0 2006.162.08:25:40.59$vc4f8/valo=7,832.99 2006.162.08:25:40.59#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.162.08:25:40.59#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.162.08:25:40.59#ibcon#ireg 17 cls_cnt 0 2006.162.08:25:40.59#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:25:40.59#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:25:40.59#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:25:40.59#ibcon#enter wrdev, iclass 28, count 0 2006.162.08:25:40.59#ibcon#first serial, iclass 28, count 0 2006.162.08:25:40.59#ibcon#enter sib2, iclass 28, count 0 2006.162.08:25:40.59#ibcon#flushed, iclass 28, count 0 2006.162.08:25:40.59#ibcon#about to write, iclass 28, count 0 2006.162.08:25:40.59#ibcon#wrote, iclass 28, count 0 2006.162.08:25:40.59#ibcon#about to read 3, iclass 28, count 0 2006.162.08:25:40.61#ibcon#read 3, iclass 28, count 0 2006.162.08:25:40.61#ibcon#about to read 4, iclass 28, count 0 2006.162.08:25:40.61#ibcon#read 4, iclass 28, count 0 2006.162.08:25:40.61#ibcon#about to read 5, iclass 28, count 0 2006.162.08:25:40.61#ibcon#read 5, iclass 28, count 0 2006.162.08:25:40.61#ibcon#about to read 6, iclass 28, count 0 2006.162.08:25:40.61#ibcon#read 6, iclass 28, count 0 2006.162.08:25:40.61#ibcon#end of sib2, iclass 28, count 0 2006.162.08:25:40.61#ibcon#*mode == 0, iclass 28, count 0 2006.162.08:25:40.61#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.162.08:25:40.61#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.08:25:40.61#ibcon#*before write, iclass 28, count 0 2006.162.08:25:40.61#ibcon#enter sib2, iclass 28, count 0 2006.162.08:25:40.61#ibcon#flushed, iclass 28, count 0 2006.162.08:25:40.61#ibcon#about to write, iclass 28, count 0 2006.162.08:25:40.61#ibcon#wrote, iclass 28, count 0 2006.162.08:25:40.61#ibcon#about to read 3, iclass 28, count 0 2006.162.08:25:40.65#ibcon#read 3, iclass 28, count 0 2006.162.08:25:40.65#ibcon#about to read 4, iclass 28, count 0 2006.162.08:25:40.65#ibcon#read 4, iclass 28, count 0 2006.162.08:25:40.65#ibcon#about to read 5, iclass 28, count 0 2006.162.08:25:40.65#ibcon#read 5, iclass 28, count 0 2006.162.08:25:40.65#ibcon#about to read 6, iclass 28, count 0 2006.162.08:25:40.65#ibcon#read 6, iclass 28, count 0 2006.162.08:25:40.65#ibcon#end of sib2, iclass 28, count 0 2006.162.08:25:40.65#ibcon#*after write, iclass 28, count 0 2006.162.08:25:40.65#ibcon#*before return 0, iclass 28, count 0 2006.162.08:25:40.65#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:25:40.65#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.162.08:25:40.65#ibcon#about to clear, iclass 28 cls_cnt 0 2006.162.08:25:40.65#ibcon#cleared, iclass 28 cls_cnt 0 2006.162.08:25:40.65$vc4f8/va=7,6 2006.162.08:25:40.65#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.162.08:25:40.65#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.162.08:25:40.65#ibcon#ireg 11 cls_cnt 2 2006.162.08:25:40.65#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:25:40.71#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:25:40.71#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:25:40.71#ibcon#enter wrdev, iclass 30, count 2 2006.162.08:25:40.71#ibcon#first serial, iclass 30, count 2 2006.162.08:25:40.71#ibcon#enter sib2, iclass 30, count 2 2006.162.08:25:40.71#ibcon#flushed, iclass 30, count 2 2006.162.08:25:40.71#ibcon#about to write, iclass 30, count 2 2006.162.08:25:40.71#ibcon#wrote, iclass 30, count 2 2006.162.08:25:40.71#ibcon#about to read 3, iclass 30, count 2 2006.162.08:25:40.73#ibcon#read 3, iclass 30, count 2 2006.162.08:25:40.73#ibcon#about to read 4, iclass 30, count 2 2006.162.08:25:40.73#ibcon#read 4, iclass 30, count 2 2006.162.08:25:40.73#ibcon#about to read 5, iclass 30, count 2 2006.162.08:25:40.73#ibcon#read 5, iclass 30, count 2 2006.162.08:25:40.73#ibcon#about to read 6, iclass 30, count 2 2006.162.08:25:40.73#ibcon#read 6, iclass 30, count 2 2006.162.08:25:40.73#ibcon#end of sib2, iclass 30, count 2 2006.162.08:25:40.73#ibcon#*mode == 0, iclass 30, count 2 2006.162.08:25:40.73#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.162.08:25:40.73#ibcon#[25=AT07-06\r\n] 2006.162.08:25:40.73#ibcon#*before write, iclass 30, count 2 2006.162.08:25:40.73#ibcon#enter sib2, iclass 30, count 2 2006.162.08:25:40.73#ibcon#flushed, iclass 30, count 2 2006.162.08:25:40.73#ibcon#about to write, iclass 30, count 2 2006.162.08:25:40.73#ibcon#wrote, iclass 30, count 2 2006.162.08:25:40.73#ibcon#about to read 3, iclass 30, count 2 2006.162.08:25:40.76#ibcon#read 3, iclass 30, count 2 2006.162.08:25:40.76#ibcon#about to read 4, iclass 30, count 2 2006.162.08:25:40.76#ibcon#read 4, iclass 30, count 2 2006.162.08:25:40.76#ibcon#about to read 5, iclass 30, count 2 2006.162.08:25:40.76#ibcon#read 5, iclass 30, count 2 2006.162.08:25:40.76#ibcon#about to read 6, iclass 30, count 2 2006.162.08:25:40.76#ibcon#read 6, iclass 30, count 2 2006.162.08:25:40.76#ibcon#end of sib2, iclass 30, count 2 2006.162.08:25:40.76#ibcon#*after write, iclass 30, count 2 2006.162.08:25:40.76#ibcon#*before return 0, iclass 30, count 2 2006.162.08:25:40.76#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:25:40.76#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.162.08:25:40.76#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.162.08:25:40.76#ibcon#ireg 7 cls_cnt 0 2006.162.08:25:40.76#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:25:40.88#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:25:40.88#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:25:40.88#ibcon#enter wrdev, iclass 30, count 0 2006.162.08:25:40.88#ibcon#first serial, iclass 30, count 0 2006.162.08:25:40.88#ibcon#enter sib2, iclass 30, count 0 2006.162.08:25:40.88#ibcon#flushed, iclass 30, count 0 2006.162.08:25:40.88#ibcon#about to write, iclass 30, count 0 2006.162.08:25:40.88#ibcon#wrote, iclass 30, count 0 2006.162.08:25:40.88#ibcon#about to read 3, iclass 30, count 0 2006.162.08:25:40.90#ibcon#read 3, iclass 30, count 0 2006.162.08:25:40.90#ibcon#about to read 4, iclass 30, count 0 2006.162.08:25:40.90#ibcon#read 4, iclass 30, count 0 2006.162.08:25:40.90#ibcon#about to read 5, iclass 30, count 0 2006.162.08:25:40.90#ibcon#read 5, iclass 30, count 0 2006.162.08:25:40.90#ibcon#about to read 6, iclass 30, count 0 2006.162.08:25:40.90#ibcon#read 6, iclass 30, count 0 2006.162.08:25:40.90#ibcon#end of sib2, iclass 30, count 0 2006.162.08:25:40.90#ibcon#*mode == 0, iclass 30, count 0 2006.162.08:25:40.90#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.162.08:25:40.90#ibcon#[25=USB\r\n] 2006.162.08:25:40.90#ibcon#*before write, iclass 30, count 0 2006.162.08:25:40.90#ibcon#enter sib2, iclass 30, count 0 2006.162.08:25:40.90#ibcon#flushed, iclass 30, count 0 2006.162.08:25:40.90#ibcon#about to write, iclass 30, count 0 2006.162.08:25:40.90#ibcon#wrote, iclass 30, count 0 2006.162.08:25:40.90#ibcon#about to read 3, iclass 30, count 0 2006.162.08:25:40.93#ibcon#read 3, iclass 30, count 0 2006.162.08:25:40.93#ibcon#about to read 4, iclass 30, count 0 2006.162.08:25:40.93#ibcon#read 4, iclass 30, count 0 2006.162.08:25:40.93#ibcon#about to read 5, iclass 30, count 0 2006.162.08:25:40.93#ibcon#read 5, iclass 30, count 0 2006.162.08:25:40.93#ibcon#about to read 6, iclass 30, count 0 2006.162.08:25:40.93#ibcon#read 6, iclass 30, count 0 2006.162.08:25:40.93#ibcon#end of sib2, iclass 30, count 0 2006.162.08:25:40.93#ibcon#*after write, iclass 30, count 0 2006.162.08:25:40.93#ibcon#*before return 0, iclass 30, count 0 2006.162.08:25:40.93#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:25:40.93#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.162.08:25:40.93#ibcon#about to clear, iclass 30 cls_cnt 0 2006.162.08:25:40.93#ibcon#cleared, iclass 30 cls_cnt 0 2006.162.08:25:40.93$vc4f8/valo=8,852.99 2006.162.08:25:40.93#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.162.08:25:40.93#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.162.08:25:40.93#ibcon#ireg 17 cls_cnt 0 2006.162.08:25:40.93#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:25:40.93#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:25:40.93#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:25:40.93#ibcon#enter wrdev, iclass 32, count 0 2006.162.08:25:40.93#ibcon#first serial, iclass 32, count 0 2006.162.08:25:40.93#ibcon#enter sib2, iclass 32, count 0 2006.162.08:25:40.93#ibcon#flushed, iclass 32, count 0 2006.162.08:25:40.93#ibcon#about to write, iclass 32, count 0 2006.162.08:25:40.93#ibcon#wrote, iclass 32, count 0 2006.162.08:25:40.93#ibcon#about to read 3, iclass 32, count 0 2006.162.08:25:40.95#ibcon#read 3, iclass 32, count 0 2006.162.08:25:40.95#ibcon#about to read 4, iclass 32, count 0 2006.162.08:25:40.95#ibcon#read 4, iclass 32, count 0 2006.162.08:25:40.95#ibcon#about to read 5, iclass 32, count 0 2006.162.08:25:40.95#ibcon#read 5, iclass 32, count 0 2006.162.08:25:40.95#ibcon#about to read 6, iclass 32, count 0 2006.162.08:25:40.95#ibcon#read 6, iclass 32, count 0 2006.162.08:25:40.95#ibcon#end of sib2, iclass 32, count 0 2006.162.08:25:40.95#ibcon#*mode == 0, iclass 32, count 0 2006.162.08:25:40.95#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.162.08:25:40.95#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.08:25:40.95#ibcon#*before write, iclass 32, count 0 2006.162.08:25:40.95#ibcon#enter sib2, iclass 32, count 0 2006.162.08:25:40.95#ibcon#flushed, iclass 32, count 0 2006.162.08:25:40.95#ibcon#about to write, iclass 32, count 0 2006.162.08:25:40.95#ibcon#wrote, iclass 32, count 0 2006.162.08:25:40.95#ibcon#about to read 3, iclass 32, count 0 2006.162.08:25:40.99#ibcon#read 3, iclass 32, count 0 2006.162.08:25:40.99#ibcon#about to read 4, iclass 32, count 0 2006.162.08:25:40.99#ibcon#read 4, iclass 32, count 0 2006.162.08:25:40.99#ibcon#about to read 5, iclass 32, count 0 2006.162.08:25:40.99#ibcon#read 5, iclass 32, count 0 2006.162.08:25:40.99#ibcon#about to read 6, iclass 32, count 0 2006.162.08:25:40.99#ibcon#read 6, iclass 32, count 0 2006.162.08:25:40.99#ibcon#end of sib2, iclass 32, count 0 2006.162.08:25:40.99#ibcon#*after write, iclass 32, count 0 2006.162.08:25:40.99#ibcon#*before return 0, iclass 32, count 0 2006.162.08:25:40.99#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:25:40.99#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.162.08:25:40.99#ibcon#about to clear, iclass 32 cls_cnt 0 2006.162.08:25:40.99#ibcon#cleared, iclass 32 cls_cnt 0 2006.162.08:25:40.99$vc4f8/va=8,7 2006.162.08:25:40.99#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.162.08:25:40.99#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.162.08:25:40.99#ibcon#ireg 11 cls_cnt 2 2006.162.08:25:40.99#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:25:41.05#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:25:41.05#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:25:41.05#ibcon#enter wrdev, iclass 34, count 2 2006.162.08:25:41.05#ibcon#first serial, iclass 34, count 2 2006.162.08:25:41.05#ibcon#enter sib2, iclass 34, count 2 2006.162.08:25:41.05#ibcon#flushed, iclass 34, count 2 2006.162.08:25:41.05#ibcon#about to write, iclass 34, count 2 2006.162.08:25:41.05#ibcon#wrote, iclass 34, count 2 2006.162.08:25:41.05#ibcon#about to read 3, iclass 34, count 2 2006.162.08:25:41.07#ibcon#read 3, iclass 34, count 2 2006.162.08:25:41.07#ibcon#about to read 4, iclass 34, count 2 2006.162.08:25:41.07#ibcon#read 4, iclass 34, count 2 2006.162.08:25:41.07#ibcon#about to read 5, iclass 34, count 2 2006.162.08:25:41.07#ibcon#read 5, iclass 34, count 2 2006.162.08:25:41.07#ibcon#about to read 6, iclass 34, count 2 2006.162.08:25:41.07#ibcon#read 6, iclass 34, count 2 2006.162.08:25:41.07#ibcon#end of sib2, iclass 34, count 2 2006.162.08:25:41.07#ibcon#*mode == 0, iclass 34, count 2 2006.162.08:25:41.07#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.162.08:25:41.07#ibcon#[25=AT08-07\r\n] 2006.162.08:25:41.07#ibcon#*before write, iclass 34, count 2 2006.162.08:25:41.07#ibcon#enter sib2, iclass 34, count 2 2006.162.08:25:41.07#ibcon#flushed, iclass 34, count 2 2006.162.08:25:41.07#ibcon#about to write, iclass 34, count 2 2006.162.08:25:41.07#ibcon#wrote, iclass 34, count 2 2006.162.08:25:41.07#ibcon#about to read 3, iclass 34, count 2 2006.162.08:25:41.10#ibcon#read 3, iclass 34, count 2 2006.162.08:25:41.10#ibcon#about to read 4, iclass 34, count 2 2006.162.08:25:41.10#ibcon#read 4, iclass 34, count 2 2006.162.08:25:41.10#ibcon#about to read 5, iclass 34, count 2 2006.162.08:25:41.10#ibcon#read 5, iclass 34, count 2 2006.162.08:25:41.10#ibcon#about to read 6, iclass 34, count 2 2006.162.08:25:41.10#ibcon#read 6, iclass 34, count 2 2006.162.08:25:41.10#ibcon#end of sib2, iclass 34, count 2 2006.162.08:25:41.10#ibcon#*after write, iclass 34, count 2 2006.162.08:25:41.10#ibcon#*before return 0, iclass 34, count 2 2006.162.08:25:41.10#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:25:41.10#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.162.08:25:41.10#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.162.08:25:41.10#ibcon#ireg 7 cls_cnt 0 2006.162.08:25:41.10#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:25:41.22#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:25:41.22#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:25:41.22#ibcon#enter wrdev, iclass 34, count 0 2006.162.08:25:41.22#ibcon#first serial, iclass 34, count 0 2006.162.08:25:41.22#ibcon#enter sib2, iclass 34, count 0 2006.162.08:25:41.22#ibcon#flushed, iclass 34, count 0 2006.162.08:25:41.22#ibcon#about to write, iclass 34, count 0 2006.162.08:25:41.22#ibcon#wrote, iclass 34, count 0 2006.162.08:25:41.22#ibcon#about to read 3, iclass 34, count 0 2006.162.08:25:41.24#ibcon#read 3, iclass 34, count 0 2006.162.08:25:41.24#ibcon#about to read 4, iclass 34, count 0 2006.162.08:25:41.24#ibcon#read 4, iclass 34, count 0 2006.162.08:25:41.24#ibcon#about to read 5, iclass 34, count 0 2006.162.08:25:41.24#ibcon#read 5, iclass 34, count 0 2006.162.08:25:41.24#ibcon#about to read 6, iclass 34, count 0 2006.162.08:25:41.24#ibcon#read 6, iclass 34, count 0 2006.162.08:25:41.24#ibcon#end of sib2, iclass 34, count 0 2006.162.08:25:41.24#ibcon#*mode == 0, iclass 34, count 0 2006.162.08:25:41.24#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.162.08:25:41.24#ibcon#[25=USB\r\n] 2006.162.08:25:41.24#ibcon#*before write, iclass 34, count 0 2006.162.08:25:41.24#ibcon#enter sib2, iclass 34, count 0 2006.162.08:25:41.24#ibcon#flushed, iclass 34, count 0 2006.162.08:25:41.24#ibcon#about to write, iclass 34, count 0 2006.162.08:25:41.24#ibcon#wrote, iclass 34, count 0 2006.162.08:25:41.24#ibcon#about to read 3, iclass 34, count 0 2006.162.08:25:41.27#ibcon#read 3, iclass 34, count 0 2006.162.08:25:41.27#ibcon#about to read 4, iclass 34, count 0 2006.162.08:25:41.27#ibcon#read 4, iclass 34, count 0 2006.162.08:25:41.27#ibcon#about to read 5, iclass 34, count 0 2006.162.08:25:41.27#ibcon#read 5, iclass 34, count 0 2006.162.08:25:41.27#ibcon#about to read 6, iclass 34, count 0 2006.162.08:25:41.27#ibcon#read 6, iclass 34, count 0 2006.162.08:25:41.27#ibcon#end of sib2, iclass 34, count 0 2006.162.08:25:41.27#ibcon#*after write, iclass 34, count 0 2006.162.08:25:41.27#ibcon#*before return 0, iclass 34, count 0 2006.162.08:25:41.27#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:25:41.27#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.162.08:25:41.27#ibcon#about to clear, iclass 34 cls_cnt 0 2006.162.08:25:41.27#ibcon#cleared, iclass 34 cls_cnt 0 2006.162.08:25:41.27$vc4f8/vblo=1,632.99 2006.162.08:25:41.27#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.162.08:25:41.27#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.162.08:25:41.27#ibcon#ireg 17 cls_cnt 0 2006.162.08:25:41.27#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:25:41.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:25:41.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:25:41.27#ibcon#enter wrdev, iclass 36, count 0 2006.162.08:25:41.27#ibcon#first serial, iclass 36, count 0 2006.162.08:25:41.27#ibcon#enter sib2, iclass 36, count 0 2006.162.08:25:41.27#ibcon#flushed, iclass 36, count 0 2006.162.08:25:41.27#ibcon#about to write, iclass 36, count 0 2006.162.08:25:41.27#ibcon#wrote, iclass 36, count 0 2006.162.08:25:41.27#ibcon#about to read 3, iclass 36, count 0 2006.162.08:25:41.29#ibcon#read 3, iclass 36, count 0 2006.162.08:25:41.29#ibcon#about to read 4, iclass 36, count 0 2006.162.08:25:41.29#ibcon#read 4, iclass 36, count 0 2006.162.08:25:41.29#ibcon#about to read 5, iclass 36, count 0 2006.162.08:25:41.29#ibcon#read 5, iclass 36, count 0 2006.162.08:25:41.29#ibcon#about to read 6, iclass 36, count 0 2006.162.08:25:41.29#ibcon#read 6, iclass 36, count 0 2006.162.08:25:41.29#ibcon#end of sib2, iclass 36, count 0 2006.162.08:25:41.29#ibcon#*mode == 0, iclass 36, count 0 2006.162.08:25:41.29#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.162.08:25:41.29#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.08:25:41.29#ibcon#*before write, iclass 36, count 0 2006.162.08:25:41.29#ibcon#enter sib2, iclass 36, count 0 2006.162.08:25:41.29#ibcon#flushed, iclass 36, count 0 2006.162.08:25:41.29#ibcon#about to write, iclass 36, count 0 2006.162.08:25:41.29#ibcon#wrote, iclass 36, count 0 2006.162.08:25:41.29#ibcon#about to read 3, iclass 36, count 0 2006.162.08:25:41.33#ibcon#read 3, iclass 36, count 0 2006.162.08:25:41.33#ibcon#about to read 4, iclass 36, count 0 2006.162.08:25:41.33#ibcon#read 4, iclass 36, count 0 2006.162.08:25:41.33#ibcon#about to read 5, iclass 36, count 0 2006.162.08:25:41.33#ibcon#read 5, iclass 36, count 0 2006.162.08:25:41.33#ibcon#about to read 6, iclass 36, count 0 2006.162.08:25:41.33#ibcon#read 6, iclass 36, count 0 2006.162.08:25:41.33#ibcon#end of sib2, iclass 36, count 0 2006.162.08:25:41.33#ibcon#*after write, iclass 36, count 0 2006.162.08:25:41.33#ibcon#*before return 0, iclass 36, count 0 2006.162.08:25:41.33#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:25:41.33#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:25:41.33#ibcon#about to clear, iclass 36 cls_cnt 0 2006.162.08:25:41.33#ibcon#cleared, iclass 36 cls_cnt 0 2006.162.08:25:41.33$vc4f8/vb=1,4 2006.162.08:25:41.33#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.162.08:25:41.33#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.162.08:25:41.33#ibcon#ireg 11 cls_cnt 2 2006.162.08:25:41.33#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.162.08:25:41.33#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.162.08:25:41.33#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.162.08:25:41.33#ibcon#enter wrdev, iclass 38, count 2 2006.162.08:25:41.33#ibcon#first serial, iclass 38, count 2 2006.162.08:25:41.33#ibcon#enter sib2, iclass 38, count 2 2006.162.08:25:41.33#ibcon#flushed, iclass 38, count 2 2006.162.08:25:41.33#ibcon#about to write, iclass 38, count 2 2006.162.08:25:41.33#ibcon#wrote, iclass 38, count 2 2006.162.08:25:41.33#ibcon#about to read 3, iclass 38, count 2 2006.162.08:25:41.35#ibcon#read 3, iclass 38, count 2 2006.162.08:25:41.35#ibcon#about to read 4, iclass 38, count 2 2006.162.08:25:41.35#ibcon#read 4, iclass 38, count 2 2006.162.08:25:41.35#ibcon#about to read 5, iclass 38, count 2 2006.162.08:25:41.35#ibcon#read 5, iclass 38, count 2 2006.162.08:25:41.35#ibcon#about to read 6, iclass 38, count 2 2006.162.08:25:41.35#ibcon#read 6, iclass 38, count 2 2006.162.08:25:41.35#ibcon#end of sib2, iclass 38, count 2 2006.162.08:25:41.35#ibcon#*mode == 0, iclass 38, count 2 2006.162.08:25:41.35#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.162.08:25:41.35#ibcon#[27=AT01-04\r\n] 2006.162.08:25:41.35#ibcon#*before write, iclass 38, count 2 2006.162.08:25:41.35#ibcon#enter sib2, iclass 38, count 2 2006.162.08:25:41.35#ibcon#flushed, iclass 38, count 2 2006.162.08:25:41.35#ibcon#about to write, iclass 38, count 2 2006.162.08:25:41.35#ibcon#wrote, iclass 38, count 2 2006.162.08:25:41.35#ibcon#about to read 3, iclass 38, count 2 2006.162.08:25:41.38#ibcon#read 3, iclass 38, count 2 2006.162.08:25:41.38#ibcon#about to read 4, iclass 38, count 2 2006.162.08:25:41.38#ibcon#read 4, iclass 38, count 2 2006.162.08:25:41.38#ibcon#about to read 5, iclass 38, count 2 2006.162.08:25:41.38#ibcon#read 5, iclass 38, count 2 2006.162.08:25:41.38#ibcon#about to read 6, iclass 38, count 2 2006.162.08:25:41.38#ibcon#read 6, iclass 38, count 2 2006.162.08:25:41.38#ibcon#end of sib2, iclass 38, count 2 2006.162.08:25:41.38#ibcon#*after write, iclass 38, count 2 2006.162.08:25:41.38#ibcon#*before return 0, iclass 38, count 2 2006.162.08:25:41.38#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.162.08:25:41.38#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.162.08:25:41.38#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.162.08:25:41.38#ibcon#ireg 7 cls_cnt 0 2006.162.08:25:41.38#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.162.08:25:41.50#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.162.08:25:41.50#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.162.08:25:41.50#ibcon#enter wrdev, iclass 38, count 0 2006.162.08:25:41.50#ibcon#first serial, iclass 38, count 0 2006.162.08:25:41.50#ibcon#enter sib2, iclass 38, count 0 2006.162.08:25:41.50#ibcon#flushed, iclass 38, count 0 2006.162.08:25:41.50#ibcon#about to write, iclass 38, count 0 2006.162.08:25:41.50#ibcon#wrote, iclass 38, count 0 2006.162.08:25:41.50#ibcon#about to read 3, iclass 38, count 0 2006.162.08:25:41.52#ibcon#read 3, iclass 38, count 0 2006.162.08:25:41.52#ibcon#about to read 4, iclass 38, count 0 2006.162.08:25:41.52#ibcon#read 4, iclass 38, count 0 2006.162.08:25:41.52#ibcon#about to read 5, iclass 38, count 0 2006.162.08:25:41.52#ibcon#read 5, iclass 38, count 0 2006.162.08:25:41.52#ibcon#about to read 6, iclass 38, count 0 2006.162.08:25:41.52#ibcon#read 6, iclass 38, count 0 2006.162.08:25:41.52#ibcon#end of sib2, iclass 38, count 0 2006.162.08:25:41.52#ibcon#*mode == 0, iclass 38, count 0 2006.162.08:25:41.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.162.08:25:41.52#ibcon#[27=USB\r\n] 2006.162.08:25:41.52#ibcon#*before write, iclass 38, count 0 2006.162.08:25:41.52#ibcon#enter sib2, iclass 38, count 0 2006.162.08:25:41.52#ibcon#flushed, iclass 38, count 0 2006.162.08:25:41.52#ibcon#about to write, iclass 38, count 0 2006.162.08:25:41.52#ibcon#wrote, iclass 38, count 0 2006.162.08:25:41.52#ibcon#about to read 3, iclass 38, count 0 2006.162.08:25:41.55#ibcon#read 3, iclass 38, count 0 2006.162.08:25:41.55#ibcon#about to read 4, iclass 38, count 0 2006.162.08:25:41.55#ibcon#read 4, iclass 38, count 0 2006.162.08:25:41.55#ibcon#about to read 5, iclass 38, count 0 2006.162.08:25:41.55#ibcon#read 5, iclass 38, count 0 2006.162.08:25:41.55#ibcon#about to read 6, iclass 38, count 0 2006.162.08:25:41.55#ibcon#read 6, iclass 38, count 0 2006.162.08:25:41.55#ibcon#end of sib2, iclass 38, count 0 2006.162.08:25:41.55#ibcon#*after write, iclass 38, count 0 2006.162.08:25:41.55#ibcon#*before return 0, iclass 38, count 0 2006.162.08:25:41.55#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.162.08:25:41.55#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.162.08:25:41.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.162.08:25:41.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.162.08:25:41.55$vc4f8/vblo=2,640.99 2006.162.08:25:41.55#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.162.08:25:41.55#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.162.08:25:41.55#ibcon#ireg 17 cls_cnt 0 2006.162.08:25:41.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:25:41.55#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:25:41.55#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:25:41.55#ibcon#enter wrdev, iclass 40, count 0 2006.162.08:25:41.55#ibcon#first serial, iclass 40, count 0 2006.162.08:25:41.55#ibcon#enter sib2, iclass 40, count 0 2006.162.08:25:41.55#ibcon#flushed, iclass 40, count 0 2006.162.08:25:41.55#ibcon#about to write, iclass 40, count 0 2006.162.08:25:41.55#ibcon#wrote, iclass 40, count 0 2006.162.08:25:41.55#ibcon#about to read 3, iclass 40, count 0 2006.162.08:25:41.57#ibcon#read 3, iclass 40, count 0 2006.162.08:25:41.57#ibcon#about to read 4, iclass 40, count 0 2006.162.08:25:41.57#ibcon#read 4, iclass 40, count 0 2006.162.08:25:41.57#ibcon#about to read 5, iclass 40, count 0 2006.162.08:25:41.57#ibcon#read 5, iclass 40, count 0 2006.162.08:25:41.57#ibcon#about to read 6, iclass 40, count 0 2006.162.08:25:41.57#ibcon#read 6, iclass 40, count 0 2006.162.08:25:41.57#ibcon#end of sib2, iclass 40, count 0 2006.162.08:25:41.57#ibcon#*mode == 0, iclass 40, count 0 2006.162.08:25:41.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.162.08:25:41.57#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.08:25:41.57#ibcon#*before write, iclass 40, count 0 2006.162.08:25:41.57#ibcon#enter sib2, iclass 40, count 0 2006.162.08:25:41.57#ibcon#flushed, iclass 40, count 0 2006.162.08:25:41.57#ibcon#about to write, iclass 40, count 0 2006.162.08:25:41.57#ibcon#wrote, iclass 40, count 0 2006.162.08:25:41.57#ibcon#about to read 3, iclass 40, count 0 2006.162.08:25:41.61#ibcon#read 3, iclass 40, count 0 2006.162.08:25:41.61#ibcon#about to read 4, iclass 40, count 0 2006.162.08:25:41.61#ibcon#read 4, iclass 40, count 0 2006.162.08:25:41.61#ibcon#about to read 5, iclass 40, count 0 2006.162.08:25:41.61#ibcon#read 5, iclass 40, count 0 2006.162.08:25:41.61#ibcon#about to read 6, iclass 40, count 0 2006.162.08:25:41.61#ibcon#read 6, iclass 40, count 0 2006.162.08:25:41.61#ibcon#end of sib2, iclass 40, count 0 2006.162.08:25:41.61#ibcon#*after write, iclass 40, count 0 2006.162.08:25:41.61#ibcon#*before return 0, iclass 40, count 0 2006.162.08:25:41.61#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:25:41.61#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.162.08:25:41.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.162.08:25:41.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.162.08:25:41.61$vc4f8/vb=2,4 2006.162.08:25:41.61#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.162.08:25:41.61#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.162.08:25:41.61#ibcon#ireg 11 cls_cnt 2 2006.162.08:25:41.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:25:41.67#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:25:41.67#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:25:41.67#ibcon#enter wrdev, iclass 4, count 2 2006.162.08:25:41.67#ibcon#first serial, iclass 4, count 2 2006.162.08:25:41.67#ibcon#enter sib2, iclass 4, count 2 2006.162.08:25:41.67#ibcon#flushed, iclass 4, count 2 2006.162.08:25:41.67#ibcon#about to write, iclass 4, count 2 2006.162.08:25:41.67#ibcon#wrote, iclass 4, count 2 2006.162.08:25:41.67#ibcon#about to read 3, iclass 4, count 2 2006.162.08:25:41.69#ibcon#read 3, iclass 4, count 2 2006.162.08:25:41.69#ibcon#about to read 4, iclass 4, count 2 2006.162.08:25:41.69#ibcon#read 4, iclass 4, count 2 2006.162.08:25:41.69#ibcon#about to read 5, iclass 4, count 2 2006.162.08:25:41.69#ibcon#read 5, iclass 4, count 2 2006.162.08:25:41.69#ibcon#about to read 6, iclass 4, count 2 2006.162.08:25:41.69#ibcon#read 6, iclass 4, count 2 2006.162.08:25:41.69#ibcon#end of sib2, iclass 4, count 2 2006.162.08:25:41.69#ibcon#*mode == 0, iclass 4, count 2 2006.162.08:25:41.69#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.162.08:25:41.69#ibcon#[27=AT02-04\r\n] 2006.162.08:25:41.69#ibcon#*before write, iclass 4, count 2 2006.162.08:25:41.69#ibcon#enter sib2, iclass 4, count 2 2006.162.08:25:41.69#ibcon#flushed, iclass 4, count 2 2006.162.08:25:41.69#ibcon#about to write, iclass 4, count 2 2006.162.08:25:41.69#ibcon#wrote, iclass 4, count 2 2006.162.08:25:41.69#ibcon#about to read 3, iclass 4, count 2 2006.162.08:25:41.72#ibcon#read 3, iclass 4, count 2 2006.162.08:25:41.72#ibcon#about to read 4, iclass 4, count 2 2006.162.08:25:41.72#ibcon#read 4, iclass 4, count 2 2006.162.08:25:41.72#ibcon#about to read 5, iclass 4, count 2 2006.162.08:25:41.72#ibcon#read 5, iclass 4, count 2 2006.162.08:25:41.72#ibcon#about to read 6, iclass 4, count 2 2006.162.08:25:41.72#ibcon#read 6, iclass 4, count 2 2006.162.08:25:41.72#ibcon#end of sib2, iclass 4, count 2 2006.162.08:25:41.72#ibcon#*after write, iclass 4, count 2 2006.162.08:25:41.72#ibcon#*before return 0, iclass 4, count 2 2006.162.08:25:41.72#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:25:41.72#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.162.08:25:41.72#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.162.08:25:41.72#ibcon#ireg 7 cls_cnt 0 2006.162.08:25:41.72#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:25:41.84#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:25:41.84#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:25:41.84#ibcon#enter wrdev, iclass 4, count 0 2006.162.08:25:41.84#ibcon#first serial, iclass 4, count 0 2006.162.08:25:41.84#ibcon#enter sib2, iclass 4, count 0 2006.162.08:25:41.84#ibcon#flushed, iclass 4, count 0 2006.162.08:25:41.84#ibcon#about to write, iclass 4, count 0 2006.162.08:25:41.84#ibcon#wrote, iclass 4, count 0 2006.162.08:25:41.84#ibcon#about to read 3, iclass 4, count 0 2006.162.08:25:41.86#ibcon#read 3, iclass 4, count 0 2006.162.08:25:41.86#ibcon#about to read 4, iclass 4, count 0 2006.162.08:25:41.86#ibcon#read 4, iclass 4, count 0 2006.162.08:25:41.86#ibcon#about to read 5, iclass 4, count 0 2006.162.08:25:41.86#ibcon#read 5, iclass 4, count 0 2006.162.08:25:41.86#ibcon#about to read 6, iclass 4, count 0 2006.162.08:25:41.86#ibcon#read 6, iclass 4, count 0 2006.162.08:25:41.86#ibcon#end of sib2, iclass 4, count 0 2006.162.08:25:41.86#ibcon#*mode == 0, iclass 4, count 0 2006.162.08:25:41.86#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.162.08:25:41.86#ibcon#[27=USB\r\n] 2006.162.08:25:41.86#ibcon#*before write, iclass 4, count 0 2006.162.08:25:41.86#ibcon#enter sib2, iclass 4, count 0 2006.162.08:25:41.86#ibcon#flushed, iclass 4, count 0 2006.162.08:25:41.86#ibcon#about to write, iclass 4, count 0 2006.162.08:25:41.86#ibcon#wrote, iclass 4, count 0 2006.162.08:25:41.86#ibcon#about to read 3, iclass 4, count 0 2006.162.08:25:41.89#ibcon#read 3, iclass 4, count 0 2006.162.08:25:41.89#ibcon#about to read 4, iclass 4, count 0 2006.162.08:25:41.89#ibcon#read 4, iclass 4, count 0 2006.162.08:25:41.89#ibcon#about to read 5, iclass 4, count 0 2006.162.08:25:41.89#ibcon#read 5, iclass 4, count 0 2006.162.08:25:41.89#ibcon#about to read 6, iclass 4, count 0 2006.162.08:25:41.89#ibcon#read 6, iclass 4, count 0 2006.162.08:25:41.89#ibcon#end of sib2, iclass 4, count 0 2006.162.08:25:41.89#ibcon#*after write, iclass 4, count 0 2006.162.08:25:41.89#ibcon#*before return 0, iclass 4, count 0 2006.162.08:25:41.89#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:25:41.89#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.162.08:25:41.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.162.08:25:41.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.162.08:25:41.89$vc4f8/vblo=3,656.99 2006.162.08:25:41.89#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.162.08:25:41.89#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.162.08:25:41.89#ibcon#ireg 17 cls_cnt 0 2006.162.08:25:41.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:25:41.89#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:25:41.89#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:25:41.89#ibcon#enter wrdev, iclass 6, count 0 2006.162.08:25:41.89#ibcon#first serial, iclass 6, count 0 2006.162.08:25:41.89#ibcon#enter sib2, iclass 6, count 0 2006.162.08:25:41.89#ibcon#flushed, iclass 6, count 0 2006.162.08:25:41.89#ibcon#about to write, iclass 6, count 0 2006.162.08:25:41.89#ibcon#wrote, iclass 6, count 0 2006.162.08:25:41.89#ibcon#about to read 3, iclass 6, count 0 2006.162.08:25:41.91#ibcon#read 3, iclass 6, count 0 2006.162.08:25:41.91#ibcon#about to read 4, iclass 6, count 0 2006.162.08:25:41.91#ibcon#read 4, iclass 6, count 0 2006.162.08:25:41.91#ibcon#about to read 5, iclass 6, count 0 2006.162.08:25:41.91#ibcon#read 5, iclass 6, count 0 2006.162.08:25:41.91#ibcon#about to read 6, iclass 6, count 0 2006.162.08:25:41.91#ibcon#read 6, iclass 6, count 0 2006.162.08:25:41.91#ibcon#end of sib2, iclass 6, count 0 2006.162.08:25:41.91#ibcon#*mode == 0, iclass 6, count 0 2006.162.08:25:41.91#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.162.08:25:41.91#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.08:25:41.91#ibcon#*before write, iclass 6, count 0 2006.162.08:25:41.91#ibcon#enter sib2, iclass 6, count 0 2006.162.08:25:41.91#ibcon#flushed, iclass 6, count 0 2006.162.08:25:41.91#ibcon#about to write, iclass 6, count 0 2006.162.08:25:41.91#ibcon#wrote, iclass 6, count 0 2006.162.08:25:41.91#ibcon#about to read 3, iclass 6, count 0 2006.162.08:25:41.95#ibcon#read 3, iclass 6, count 0 2006.162.08:25:41.95#ibcon#about to read 4, iclass 6, count 0 2006.162.08:25:41.95#ibcon#read 4, iclass 6, count 0 2006.162.08:25:41.95#ibcon#about to read 5, iclass 6, count 0 2006.162.08:25:41.95#ibcon#read 5, iclass 6, count 0 2006.162.08:25:41.95#ibcon#about to read 6, iclass 6, count 0 2006.162.08:25:41.95#ibcon#read 6, iclass 6, count 0 2006.162.08:25:41.95#ibcon#end of sib2, iclass 6, count 0 2006.162.08:25:41.95#ibcon#*after write, iclass 6, count 0 2006.162.08:25:41.95#ibcon#*before return 0, iclass 6, count 0 2006.162.08:25:41.95#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:25:41.95#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.162.08:25:41.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.162.08:25:41.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.162.08:25:41.95$vc4f8/vb=3,4 2006.162.08:25:41.95#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.162.08:25:41.95#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.162.08:25:41.95#ibcon#ireg 11 cls_cnt 2 2006.162.08:25:41.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:25:42.01#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:25:42.01#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:25:42.01#ibcon#enter wrdev, iclass 10, count 2 2006.162.08:25:42.01#ibcon#first serial, iclass 10, count 2 2006.162.08:25:42.01#ibcon#enter sib2, iclass 10, count 2 2006.162.08:25:42.01#ibcon#flushed, iclass 10, count 2 2006.162.08:25:42.01#ibcon#about to write, iclass 10, count 2 2006.162.08:25:42.01#ibcon#wrote, iclass 10, count 2 2006.162.08:25:42.01#ibcon#about to read 3, iclass 10, count 2 2006.162.08:25:42.03#ibcon#read 3, iclass 10, count 2 2006.162.08:25:42.03#ibcon#about to read 4, iclass 10, count 2 2006.162.08:25:42.03#ibcon#read 4, iclass 10, count 2 2006.162.08:25:42.03#ibcon#about to read 5, iclass 10, count 2 2006.162.08:25:42.03#ibcon#read 5, iclass 10, count 2 2006.162.08:25:42.03#ibcon#about to read 6, iclass 10, count 2 2006.162.08:25:42.03#ibcon#read 6, iclass 10, count 2 2006.162.08:25:42.03#ibcon#end of sib2, iclass 10, count 2 2006.162.08:25:42.03#ibcon#*mode == 0, iclass 10, count 2 2006.162.08:25:42.03#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.162.08:25:42.03#ibcon#[27=AT03-04\r\n] 2006.162.08:25:42.03#ibcon#*before write, iclass 10, count 2 2006.162.08:25:42.03#ibcon#enter sib2, iclass 10, count 2 2006.162.08:25:42.03#ibcon#flushed, iclass 10, count 2 2006.162.08:25:42.03#ibcon#about to write, iclass 10, count 2 2006.162.08:25:42.03#ibcon#wrote, iclass 10, count 2 2006.162.08:25:42.03#ibcon#about to read 3, iclass 10, count 2 2006.162.08:25:42.06#ibcon#read 3, iclass 10, count 2 2006.162.08:25:42.06#ibcon#about to read 4, iclass 10, count 2 2006.162.08:25:42.06#ibcon#read 4, iclass 10, count 2 2006.162.08:25:42.06#ibcon#about to read 5, iclass 10, count 2 2006.162.08:25:42.06#ibcon#read 5, iclass 10, count 2 2006.162.08:25:42.06#ibcon#about to read 6, iclass 10, count 2 2006.162.08:25:42.06#ibcon#read 6, iclass 10, count 2 2006.162.08:25:42.06#ibcon#end of sib2, iclass 10, count 2 2006.162.08:25:42.06#ibcon#*after write, iclass 10, count 2 2006.162.08:25:42.06#ibcon#*before return 0, iclass 10, count 2 2006.162.08:25:42.06#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:25:42.06#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.162.08:25:42.06#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.162.08:25:42.06#ibcon#ireg 7 cls_cnt 0 2006.162.08:25:42.06#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:25:42.18#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:25:42.18#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:25:42.18#ibcon#enter wrdev, iclass 10, count 0 2006.162.08:25:42.18#ibcon#first serial, iclass 10, count 0 2006.162.08:25:42.18#ibcon#enter sib2, iclass 10, count 0 2006.162.08:25:42.18#ibcon#flushed, iclass 10, count 0 2006.162.08:25:42.18#ibcon#about to write, iclass 10, count 0 2006.162.08:25:42.18#ibcon#wrote, iclass 10, count 0 2006.162.08:25:42.18#ibcon#about to read 3, iclass 10, count 0 2006.162.08:25:42.20#ibcon#read 3, iclass 10, count 0 2006.162.08:25:42.20#ibcon#about to read 4, iclass 10, count 0 2006.162.08:25:42.20#ibcon#read 4, iclass 10, count 0 2006.162.08:25:42.20#ibcon#about to read 5, iclass 10, count 0 2006.162.08:25:42.20#ibcon#read 5, iclass 10, count 0 2006.162.08:25:42.20#ibcon#about to read 6, iclass 10, count 0 2006.162.08:25:42.20#ibcon#read 6, iclass 10, count 0 2006.162.08:25:42.20#ibcon#end of sib2, iclass 10, count 0 2006.162.08:25:42.20#ibcon#*mode == 0, iclass 10, count 0 2006.162.08:25:42.20#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.162.08:25:42.20#ibcon#[27=USB\r\n] 2006.162.08:25:42.20#ibcon#*before write, iclass 10, count 0 2006.162.08:25:42.20#ibcon#enter sib2, iclass 10, count 0 2006.162.08:25:42.20#ibcon#flushed, iclass 10, count 0 2006.162.08:25:42.20#ibcon#about to write, iclass 10, count 0 2006.162.08:25:42.20#ibcon#wrote, iclass 10, count 0 2006.162.08:25:42.20#ibcon#about to read 3, iclass 10, count 0 2006.162.08:25:42.23#ibcon#read 3, iclass 10, count 0 2006.162.08:25:42.23#ibcon#about to read 4, iclass 10, count 0 2006.162.08:25:42.23#ibcon#read 4, iclass 10, count 0 2006.162.08:25:42.23#ibcon#about to read 5, iclass 10, count 0 2006.162.08:25:42.23#ibcon#read 5, iclass 10, count 0 2006.162.08:25:42.23#ibcon#about to read 6, iclass 10, count 0 2006.162.08:25:42.23#ibcon#read 6, iclass 10, count 0 2006.162.08:25:42.23#ibcon#end of sib2, iclass 10, count 0 2006.162.08:25:42.23#ibcon#*after write, iclass 10, count 0 2006.162.08:25:42.23#ibcon#*before return 0, iclass 10, count 0 2006.162.08:25:42.23#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:25:42.23#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.162.08:25:42.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.162.08:25:42.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.162.08:25:42.23$vc4f8/vblo=4,712.99 2006.162.08:25:42.23#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.162.08:25:42.23#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.162.08:25:42.23#ibcon#ireg 17 cls_cnt 0 2006.162.08:25:42.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:25:42.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:25:42.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:25:42.23#ibcon#enter wrdev, iclass 12, count 0 2006.162.08:25:42.23#ibcon#first serial, iclass 12, count 0 2006.162.08:25:42.23#ibcon#enter sib2, iclass 12, count 0 2006.162.08:25:42.23#ibcon#flushed, iclass 12, count 0 2006.162.08:25:42.23#ibcon#about to write, iclass 12, count 0 2006.162.08:25:42.23#ibcon#wrote, iclass 12, count 0 2006.162.08:25:42.23#ibcon#about to read 3, iclass 12, count 0 2006.162.08:25:42.25#ibcon#read 3, iclass 12, count 0 2006.162.08:25:42.25#ibcon#about to read 4, iclass 12, count 0 2006.162.08:25:42.25#ibcon#read 4, iclass 12, count 0 2006.162.08:25:42.25#ibcon#about to read 5, iclass 12, count 0 2006.162.08:25:42.25#ibcon#read 5, iclass 12, count 0 2006.162.08:25:42.25#ibcon#about to read 6, iclass 12, count 0 2006.162.08:25:42.25#ibcon#read 6, iclass 12, count 0 2006.162.08:25:42.25#ibcon#end of sib2, iclass 12, count 0 2006.162.08:25:42.25#ibcon#*mode == 0, iclass 12, count 0 2006.162.08:25:42.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.162.08:25:42.25#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.08:25:42.25#ibcon#*before write, iclass 12, count 0 2006.162.08:25:42.25#ibcon#enter sib2, iclass 12, count 0 2006.162.08:25:42.25#ibcon#flushed, iclass 12, count 0 2006.162.08:25:42.25#ibcon#about to write, iclass 12, count 0 2006.162.08:25:42.25#ibcon#wrote, iclass 12, count 0 2006.162.08:25:42.25#ibcon#about to read 3, iclass 12, count 0 2006.162.08:25:42.29#ibcon#read 3, iclass 12, count 0 2006.162.08:25:42.29#ibcon#about to read 4, iclass 12, count 0 2006.162.08:25:42.29#ibcon#read 4, iclass 12, count 0 2006.162.08:25:42.29#ibcon#about to read 5, iclass 12, count 0 2006.162.08:25:42.29#ibcon#read 5, iclass 12, count 0 2006.162.08:25:42.29#ibcon#about to read 6, iclass 12, count 0 2006.162.08:25:42.29#ibcon#read 6, iclass 12, count 0 2006.162.08:25:42.29#ibcon#end of sib2, iclass 12, count 0 2006.162.08:25:42.29#ibcon#*after write, iclass 12, count 0 2006.162.08:25:42.29#ibcon#*before return 0, iclass 12, count 0 2006.162.08:25:42.29#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:25:42.29#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.162.08:25:42.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.162.08:25:42.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.162.08:25:42.29$vc4f8/vb=4,4 2006.162.08:25:42.29#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.162.08:25:42.29#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.162.08:25:42.29#ibcon#ireg 11 cls_cnt 2 2006.162.08:25:42.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.162.08:25:42.35#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.162.08:25:42.35#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.162.08:25:42.35#ibcon#enter wrdev, iclass 14, count 2 2006.162.08:25:42.35#ibcon#first serial, iclass 14, count 2 2006.162.08:25:42.35#ibcon#enter sib2, iclass 14, count 2 2006.162.08:25:42.35#ibcon#flushed, iclass 14, count 2 2006.162.08:25:42.35#ibcon#about to write, iclass 14, count 2 2006.162.08:25:42.35#ibcon#wrote, iclass 14, count 2 2006.162.08:25:42.35#ibcon#about to read 3, iclass 14, count 2 2006.162.08:25:42.37#ibcon#read 3, iclass 14, count 2 2006.162.08:25:42.37#ibcon#about to read 4, iclass 14, count 2 2006.162.08:25:42.37#ibcon#read 4, iclass 14, count 2 2006.162.08:25:42.37#ibcon#about to read 5, iclass 14, count 2 2006.162.08:25:42.37#ibcon#read 5, iclass 14, count 2 2006.162.08:25:42.37#ibcon#about to read 6, iclass 14, count 2 2006.162.08:25:42.37#ibcon#read 6, iclass 14, count 2 2006.162.08:25:42.37#ibcon#end of sib2, iclass 14, count 2 2006.162.08:25:42.37#ibcon#*mode == 0, iclass 14, count 2 2006.162.08:25:42.37#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.162.08:25:42.37#ibcon#[27=AT04-04\r\n] 2006.162.08:25:42.37#ibcon#*before write, iclass 14, count 2 2006.162.08:25:42.37#ibcon#enter sib2, iclass 14, count 2 2006.162.08:25:42.37#ibcon#flushed, iclass 14, count 2 2006.162.08:25:42.37#ibcon#about to write, iclass 14, count 2 2006.162.08:25:42.37#ibcon#wrote, iclass 14, count 2 2006.162.08:25:42.37#ibcon#about to read 3, iclass 14, count 2 2006.162.08:25:42.40#ibcon#read 3, iclass 14, count 2 2006.162.08:25:42.40#ibcon#about to read 4, iclass 14, count 2 2006.162.08:25:42.40#ibcon#read 4, iclass 14, count 2 2006.162.08:25:42.40#ibcon#about to read 5, iclass 14, count 2 2006.162.08:25:42.40#ibcon#read 5, iclass 14, count 2 2006.162.08:25:42.40#ibcon#about to read 6, iclass 14, count 2 2006.162.08:25:42.40#ibcon#read 6, iclass 14, count 2 2006.162.08:25:42.40#ibcon#end of sib2, iclass 14, count 2 2006.162.08:25:42.40#ibcon#*after write, iclass 14, count 2 2006.162.08:25:42.40#ibcon#*before return 0, iclass 14, count 2 2006.162.08:25:42.40#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.162.08:25:42.40#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.162.08:25:42.40#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.162.08:25:42.40#ibcon#ireg 7 cls_cnt 0 2006.162.08:25:42.40#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.162.08:25:42.52#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.162.08:25:42.52#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.162.08:25:42.52#ibcon#enter wrdev, iclass 14, count 0 2006.162.08:25:42.52#ibcon#first serial, iclass 14, count 0 2006.162.08:25:42.52#ibcon#enter sib2, iclass 14, count 0 2006.162.08:25:42.52#ibcon#flushed, iclass 14, count 0 2006.162.08:25:42.52#ibcon#about to write, iclass 14, count 0 2006.162.08:25:42.52#ibcon#wrote, iclass 14, count 0 2006.162.08:25:42.52#ibcon#about to read 3, iclass 14, count 0 2006.162.08:25:42.54#ibcon#read 3, iclass 14, count 0 2006.162.08:25:42.54#ibcon#about to read 4, iclass 14, count 0 2006.162.08:25:42.54#ibcon#read 4, iclass 14, count 0 2006.162.08:25:42.54#ibcon#about to read 5, iclass 14, count 0 2006.162.08:25:42.54#ibcon#read 5, iclass 14, count 0 2006.162.08:25:42.54#ibcon#about to read 6, iclass 14, count 0 2006.162.08:25:42.54#ibcon#read 6, iclass 14, count 0 2006.162.08:25:42.54#ibcon#end of sib2, iclass 14, count 0 2006.162.08:25:42.54#ibcon#*mode == 0, iclass 14, count 0 2006.162.08:25:42.54#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.08:25:42.54#ibcon#[27=USB\r\n] 2006.162.08:25:42.54#ibcon#*before write, iclass 14, count 0 2006.162.08:25:42.54#ibcon#enter sib2, iclass 14, count 0 2006.162.08:25:42.54#ibcon#flushed, iclass 14, count 0 2006.162.08:25:42.54#ibcon#about to write, iclass 14, count 0 2006.162.08:25:42.54#ibcon#wrote, iclass 14, count 0 2006.162.08:25:42.54#ibcon#about to read 3, iclass 14, count 0 2006.162.08:25:42.57#ibcon#read 3, iclass 14, count 0 2006.162.08:25:42.57#ibcon#about to read 4, iclass 14, count 0 2006.162.08:25:42.57#ibcon#read 4, iclass 14, count 0 2006.162.08:25:42.57#ibcon#about to read 5, iclass 14, count 0 2006.162.08:25:42.57#ibcon#read 5, iclass 14, count 0 2006.162.08:25:42.57#ibcon#about to read 6, iclass 14, count 0 2006.162.08:25:42.57#ibcon#read 6, iclass 14, count 0 2006.162.08:25:42.57#ibcon#end of sib2, iclass 14, count 0 2006.162.08:25:42.57#ibcon#*after write, iclass 14, count 0 2006.162.08:25:42.57#ibcon#*before return 0, iclass 14, count 0 2006.162.08:25:42.57#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.162.08:25:42.57#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.162.08:25:42.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.08:25:42.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.08:25:42.57$vc4f8/vblo=5,744.99 2006.162.08:25:42.57#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.162.08:25:42.57#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.162.08:25:42.57#ibcon#ireg 17 cls_cnt 0 2006.162.08:25:42.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:25:42.57#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:25:42.57#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:25:42.57#ibcon#enter wrdev, iclass 16, count 0 2006.162.08:25:42.57#ibcon#first serial, iclass 16, count 0 2006.162.08:25:42.57#ibcon#enter sib2, iclass 16, count 0 2006.162.08:25:42.57#ibcon#flushed, iclass 16, count 0 2006.162.08:25:42.57#ibcon#about to write, iclass 16, count 0 2006.162.08:25:42.57#ibcon#wrote, iclass 16, count 0 2006.162.08:25:42.57#ibcon#about to read 3, iclass 16, count 0 2006.162.08:25:42.59#ibcon#read 3, iclass 16, count 0 2006.162.08:25:42.59#ibcon#about to read 4, iclass 16, count 0 2006.162.08:25:42.59#ibcon#read 4, iclass 16, count 0 2006.162.08:25:42.59#ibcon#about to read 5, iclass 16, count 0 2006.162.08:25:42.59#ibcon#read 5, iclass 16, count 0 2006.162.08:25:42.59#ibcon#about to read 6, iclass 16, count 0 2006.162.08:25:42.59#ibcon#read 6, iclass 16, count 0 2006.162.08:25:42.59#ibcon#end of sib2, iclass 16, count 0 2006.162.08:25:42.59#ibcon#*mode == 0, iclass 16, count 0 2006.162.08:25:42.59#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.162.08:25:42.59#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.08:25:42.59#ibcon#*before write, iclass 16, count 0 2006.162.08:25:42.59#ibcon#enter sib2, iclass 16, count 0 2006.162.08:25:42.59#ibcon#flushed, iclass 16, count 0 2006.162.08:25:42.59#ibcon#about to write, iclass 16, count 0 2006.162.08:25:42.59#ibcon#wrote, iclass 16, count 0 2006.162.08:25:42.59#ibcon#about to read 3, iclass 16, count 0 2006.162.08:25:42.63#ibcon#read 3, iclass 16, count 0 2006.162.08:25:42.63#ibcon#about to read 4, iclass 16, count 0 2006.162.08:25:42.63#ibcon#read 4, iclass 16, count 0 2006.162.08:25:42.63#ibcon#about to read 5, iclass 16, count 0 2006.162.08:25:42.63#ibcon#read 5, iclass 16, count 0 2006.162.08:25:42.63#ibcon#about to read 6, iclass 16, count 0 2006.162.08:25:42.63#ibcon#read 6, iclass 16, count 0 2006.162.08:25:42.63#ibcon#end of sib2, iclass 16, count 0 2006.162.08:25:42.63#ibcon#*after write, iclass 16, count 0 2006.162.08:25:42.63#ibcon#*before return 0, iclass 16, count 0 2006.162.08:25:42.63#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:25:42.63#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.162.08:25:42.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.162.08:25:42.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.162.08:25:42.63$vc4f8/vb=5,4 2006.162.08:25:42.63#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.162.08:25:42.63#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.162.08:25:42.63#ibcon#ireg 11 cls_cnt 2 2006.162.08:25:42.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:25:42.69#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:25:42.69#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:25:42.69#ibcon#enter wrdev, iclass 18, count 2 2006.162.08:25:42.69#ibcon#first serial, iclass 18, count 2 2006.162.08:25:42.69#ibcon#enter sib2, iclass 18, count 2 2006.162.08:25:42.69#ibcon#flushed, iclass 18, count 2 2006.162.08:25:42.69#ibcon#about to write, iclass 18, count 2 2006.162.08:25:42.69#ibcon#wrote, iclass 18, count 2 2006.162.08:25:42.69#ibcon#about to read 3, iclass 18, count 2 2006.162.08:25:42.71#ibcon#read 3, iclass 18, count 2 2006.162.08:25:42.71#ibcon#about to read 4, iclass 18, count 2 2006.162.08:25:42.71#ibcon#read 4, iclass 18, count 2 2006.162.08:25:42.71#ibcon#about to read 5, iclass 18, count 2 2006.162.08:25:42.71#ibcon#read 5, iclass 18, count 2 2006.162.08:25:42.71#ibcon#about to read 6, iclass 18, count 2 2006.162.08:25:42.71#ibcon#read 6, iclass 18, count 2 2006.162.08:25:42.71#ibcon#end of sib2, iclass 18, count 2 2006.162.08:25:42.71#ibcon#*mode == 0, iclass 18, count 2 2006.162.08:25:42.71#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.162.08:25:42.71#ibcon#[27=AT05-04\r\n] 2006.162.08:25:42.71#ibcon#*before write, iclass 18, count 2 2006.162.08:25:42.71#ibcon#enter sib2, iclass 18, count 2 2006.162.08:25:42.71#ibcon#flushed, iclass 18, count 2 2006.162.08:25:42.71#ibcon#about to write, iclass 18, count 2 2006.162.08:25:42.71#ibcon#wrote, iclass 18, count 2 2006.162.08:25:42.71#ibcon#about to read 3, iclass 18, count 2 2006.162.08:25:42.74#ibcon#read 3, iclass 18, count 2 2006.162.08:25:42.74#ibcon#about to read 4, iclass 18, count 2 2006.162.08:25:42.74#ibcon#read 4, iclass 18, count 2 2006.162.08:25:42.74#ibcon#about to read 5, iclass 18, count 2 2006.162.08:25:42.74#ibcon#read 5, iclass 18, count 2 2006.162.08:25:42.74#ibcon#about to read 6, iclass 18, count 2 2006.162.08:25:42.74#ibcon#read 6, iclass 18, count 2 2006.162.08:25:42.74#ibcon#end of sib2, iclass 18, count 2 2006.162.08:25:42.74#ibcon#*after write, iclass 18, count 2 2006.162.08:25:42.74#ibcon#*before return 0, iclass 18, count 2 2006.162.08:25:42.74#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:25:42.74#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.162.08:25:42.74#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.162.08:25:42.74#ibcon#ireg 7 cls_cnt 0 2006.162.08:25:42.74#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:25:42.86#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:25:42.86#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:25:42.86#ibcon#enter wrdev, iclass 18, count 0 2006.162.08:25:42.86#ibcon#first serial, iclass 18, count 0 2006.162.08:25:42.86#ibcon#enter sib2, iclass 18, count 0 2006.162.08:25:42.86#ibcon#flushed, iclass 18, count 0 2006.162.08:25:42.86#ibcon#about to write, iclass 18, count 0 2006.162.08:25:42.86#ibcon#wrote, iclass 18, count 0 2006.162.08:25:42.86#ibcon#about to read 3, iclass 18, count 0 2006.162.08:25:42.88#ibcon#read 3, iclass 18, count 0 2006.162.08:25:42.88#ibcon#about to read 4, iclass 18, count 0 2006.162.08:25:42.88#ibcon#read 4, iclass 18, count 0 2006.162.08:25:42.88#ibcon#about to read 5, iclass 18, count 0 2006.162.08:25:42.88#ibcon#read 5, iclass 18, count 0 2006.162.08:25:42.88#ibcon#about to read 6, iclass 18, count 0 2006.162.08:25:42.88#ibcon#read 6, iclass 18, count 0 2006.162.08:25:42.88#ibcon#end of sib2, iclass 18, count 0 2006.162.08:25:42.88#ibcon#*mode == 0, iclass 18, count 0 2006.162.08:25:42.88#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.162.08:25:42.88#ibcon#[27=USB\r\n] 2006.162.08:25:42.88#ibcon#*before write, iclass 18, count 0 2006.162.08:25:42.88#ibcon#enter sib2, iclass 18, count 0 2006.162.08:25:42.88#ibcon#flushed, iclass 18, count 0 2006.162.08:25:42.88#ibcon#about to write, iclass 18, count 0 2006.162.08:25:42.88#ibcon#wrote, iclass 18, count 0 2006.162.08:25:42.88#ibcon#about to read 3, iclass 18, count 0 2006.162.08:25:42.91#ibcon#read 3, iclass 18, count 0 2006.162.08:25:42.91#ibcon#about to read 4, iclass 18, count 0 2006.162.08:25:42.91#ibcon#read 4, iclass 18, count 0 2006.162.08:25:42.91#ibcon#about to read 5, iclass 18, count 0 2006.162.08:25:42.91#ibcon#read 5, iclass 18, count 0 2006.162.08:25:42.91#ibcon#about to read 6, iclass 18, count 0 2006.162.08:25:42.91#ibcon#read 6, iclass 18, count 0 2006.162.08:25:42.91#ibcon#end of sib2, iclass 18, count 0 2006.162.08:25:42.91#ibcon#*after write, iclass 18, count 0 2006.162.08:25:42.91#ibcon#*before return 0, iclass 18, count 0 2006.162.08:25:42.91#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:25:42.91#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.162.08:25:42.91#ibcon#about to clear, iclass 18 cls_cnt 0 2006.162.08:25:42.91#ibcon#cleared, iclass 18 cls_cnt 0 2006.162.08:25:42.91$vc4f8/vblo=6,752.99 2006.162.08:25:42.91#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.162.08:25:42.91#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.162.08:25:42.91#ibcon#ireg 17 cls_cnt 0 2006.162.08:25:42.91#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:25:42.91#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:25:42.91#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:25:42.91#ibcon#enter wrdev, iclass 20, count 0 2006.162.08:25:42.91#ibcon#first serial, iclass 20, count 0 2006.162.08:25:42.91#ibcon#enter sib2, iclass 20, count 0 2006.162.08:25:42.91#ibcon#flushed, iclass 20, count 0 2006.162.08:25:42.91#ibcon#about to write, iclass 20, count 0 2006.162.08:25:42.91#ibcon#wrote, iclass 20, count 0 2006.162.08:25:42.91#ibcon#about to read 3, iclass 20, count 0 2006.162.08:25:42.93#ibcon#read 3, iclass 20, count 0 2006.162.08:25:42.93#ibcon#about to read 4, iclass 20, count 0 2006.162.08:25:42.93#ibcon#read 4, iclass 20, count 0 2006.162.08:25:42.93#ibcon#about to read 5, iclass 20, count 0 2006.162.08:25:42.93#ibcon#read 5, iclass 20, count 0 2006.162.08:25:42.93#ibcon#about to read 6, iclass 20, count 0 2006.162.08:25:42.93#ibcon#read 6, iclass 20, count 0 2006.162.08:25:42.93#ibcon#end of sib2, iclass 20, count 0 2006.162.08:25:42.93#ibcon#*mode == 0, iclass 20, count 0 2006.162.08:25:42.93#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.08:25:42.93#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.08:25:42.93#ibcon#*before write, iclass 20, count 0 2006.162.08:25:42.93#ibcon#enter sib2, iclass 20, count 0 2006.162.08:25:42.93#ibcon#flushed, iclass 20, count 0 2006.162.08:25:42.93#ibcon#about to write, iclass 20, count 0 2006.162.08:25:42.93#ibcon#wrote, iclass 20, count 0 2006.162.08:25:42.93#ibcon#about to read 3, iclass 20, count 0 2006.162.08:25:42.97#ibcon#read 3, iclass 20, count 0 2006.162.08:25:42.97#ibcon#about to read 4, iclass 20, count 0 2006.162.08:25:42.97#ibcon#read 4, iclass 20, count 0 2006.162.08:25:42.97#ibcon#about to read 5, iclass 20, count 0 2006.162.08:25:42.97#ibcon#read 5, iclass 20, count 0 2006.162.08:25:42.97#ibcon#about to read 6, iclass 20, count 0 2006.162.08:25:42.97#ibcon#read 6, iclass 20, count 0 2006.162.08:25:42.97#ibcon#end of sib2, iclass 20, count 0 2006.162.08:25:42.97#ibcon#*after write, iclass 20, count 0 2006.162.08:25:42.97#ibcon#*before return 0, iclass 20, count 0 2006.162.08:25:42.97#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:25:42.97#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.162.08:25:42.97#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.08:25:42.97#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.08:25:42.97$vc4f8/vb=6,4 2006.162.08:25:42.97#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.162.08:25:42.97#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.162.08:25:42.97#ibcon#ireg 11 cls_cnt 2 2006.162.08:25:42.97#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:25:43.03#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:25:43.03#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:25:43.03#ibcon#enter wrdev, iclass 22, count 2 2006.162.08:25:43.03#ibcon#first serial, iclass 22, count 2 2006.162.08:25:43.03#ibcon#enter sib2, iclass 22, count 2 2006.162.08:25:43.03#ibcon#flushed, iclass 22, count 2 2006.162.08:25:43.03#ibcon#about to write, iclass 22, count 2 2006.162.08:25:43.03#ibcon#wrote, iclass 22, count 2 2006.162.08:25:43.03#ibcon#about to read 3, iclass 22, count 2 2006.162.08:25:43.05#ibcon#read 3, iclass 22, count 2 2006.162.08:25:43.05#ibcon#about to read 4, iclass 22, count 2 2006.162.08:25:43.05#ibcon#read 4, iclass 22, count 2 2006.162.08:25:43.05#ibcon#about to read 5, iclass 22, count 2 2006.162.08:25:43.05#ibcon#read 5, iclass 22, count 2 2006.162.08:25:43.05#ibcon#about to read 6, iclass 22, count 2 2006.162.08:25:43.05#ibcon#read 6, iclass 22, count 2 2006.162.08:25:43.05#ibcon#end of sib2, iclass 22, count 2 2006.162.08:25:43.05#ibcon#*mode == 0, iclass 22, count 2 2006.162.08:25:43.05#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.162.08:25:43.05#ibcon#[27=AT06-04\r\n] 2006.162.08:25:43.05#ibcon#*before write, iclass 22, count 2 2006.162.08:25:43.05#ibcon#enter sib2, iclass 22, count 2 2006.162.08:25:43.05#ibcon#flushed, iclass 22, count 2 2006.162.08:25:43.05#ibcon#about to write, iclass 22, count 2 2006.162.08:25:43.05#ibcon#wrote, iclass 22, count 2 2006.162.08:25:43.05#ibcon#about to read 3, iclass 22, count 2 2006.162.08:25:43.08#ibcon#read 3, iclass 22, count 2 2006.162.08:25:43.08#ibcon#about to read 4, iclass 22, count 2 2006.162.08:25:43.08#ibcon#read 4, iclass 22, count 2 2006.162.08:25:43.08#ibcon#about to read 5, iclass 22, count 2 2006.162.08:25:43.08#ibcon#read 5, iclass 22, count 2 2006.162.08:25:43.08#ibcon#about to read 6, iclass 22, count 2 2006.162.08:25:43.08#ibcon#read 6, iclass 22, count 2 2006.162.08:25:43.08#ibcon#end of sib2, iclass 22, count 2 2006.162.08:25:43.08#ibcon#*after write, iclass 22, count 2 2006.162.08:25:43.08#ibcon#*before return 0, iclass 22, count 2 2006.162.08:25:43.08#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:25:43.08#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.162.08:25:43.08#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.162.08:25:43.08#ibcon#ireg 7 cls_cnt 0 2006.162.08:25:43.08#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:25:43.20#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:25:43.20#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:25:43.20#ibcon#enter wrdev, iclass 22, count 0 2006.162.08:25:43.20#ibcon#first serial, iclass 22, count 0 2006.162.08:25:43.20#ibcon#enter sib2, iclass 22, count 0 2006.162.08:25:43.20#ibcon#flushed, iclass 22, count 0 2006.162.08:25:43.20#ibcon#about to write, iclass 22, count 0 2006.162.08:25:43.20#ibcon#wrote, iclass 22, count 0 2006.162.08:25:43.20#ibcon#about to read 3, iclass 22, count 0 2006.162.08:25:43.22#ibcon#read 3, iclass 22, count 0 2006.162.08:25:43.22#ibcon#about to read 4, iclass 22, count 0 2006.162.08:25:43.22#ibcon#read 4, iclass 22, count 0 2006.162.08:25:43.22#ibcon#about to read 5, iclass 22, count 0 2006.162.08:25:43.22#ibcon#read 5, iclass 22, count 0 2006.162.08:25:43.22#ibcon#about to read 6, iclass 22, count 0 2006.162.08:25:43.22#ibcon#read 6, iclass 22, count 0 2006.162.08:25:43.22#ibcon#end of sib2, iclass 22, count 0 2006.162.08:25:43.22#ibcon#*mode == 0, iclass 22, count 0 2006.162.08:25:43.22#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.08:25:43.22#ibcon#[27=USB\r\n] 2006.162.08:25:43.22#ibcon#*before write, iclass 22, count 0 2006.162.08:25:43.22#ibcon#enter sib2, iclass 22, count 0 2006.162.08:25:43.22#ibcon#flushed, iclass 22, count 0 2006.162.08:25:43.22#ibcon#about to write, iclass 22, count 0 2006.162.08:25:43.22#ibcon#wrote, iclass 22, count 0 2006.162.08:25:43.22#ibcon#about to read 3, iclass 22, count 0 2006.162.08:25:43.25#ibcon#read 3, iclass 22, count 0 2006.162.08:25:43.25#ibcon#about to read 4, iclass 22, count 0 2006.162.08:25:43.25#ibcon#read 4, iclass 22, count 0 2006.162.08:25:43.25#ibcon#about to read 5, iclass 22, count 0 2006.162.08:25:43.25#ibcon#read 5, iclass 22, count 0 2006.162.08:25:43.25#ibcon#about to read 6, iclass 22, count 0 2006.162.08:25:43.25#ibcon#read 6, iclass 22, count 0 2006.162.08:25:43.25#ibcon#end of sib2, iclass 22, count 0 2006.162.08:25:43.25#ibcon#*after write, iclass 22, count 0 2006.162.08:25:43.25#ibcon#*before return 0, iclass 22, count 0 2006.162.08:25:43.25#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:25:43.25#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.162.08:25:43.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.08:25:43.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.08:25:43.25$vc4f8/vabw=wide 2006.162.08:25:43.25#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.162.08:25:43.25#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.162.08:25:43.25#ibcon#ireg 8 cls_cnt 0 2006.162.08:25:43.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:25:43.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:25:43.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:25:43.25#ibcon#enter wrdev, iclass 24, count 0 2006.162.08:25:43.25#ibcon#first serial, iclass 24, count 0 2006.162.08:25:43.25#ibcon#enter sib2, iclass 24, count 0 2006.162.08:25:43.25#ibcon#flushed, iclass 24, count 0 2006.162.08:25:43.25#ibcon#about to write, iclass 24, count 0 2006.162.08:25:43.25#ibcon#wrote, iclass 24, count 0 2006.162.08:25:43.25#ibcon#about to read 3, iclass 24, count 0 2006.162.08:25:43.27#ibcon#read 3, iclass 24, count 0 2006.162.08:25:43.27#ibcon#about to read 4, iclass 24, count 0 2006.162.08:25:43.27#ibcon#read 4, iclass 24, count 0 2006.162.08:25:43.27#ibcon#about to read 5, iclass 24, count 0 2006.162.08:25:43.27#ibcon#read 5, iclass 24, count 0 2006.162.08:25:43.27#ibcon#about to read 6, iclass 24, count 0 2006.162.08:25:43.27#ibcon#read 6, iclass 24, count 0 2006.162.08:25:43.27#ibcon#end of sib2, iclass 24, count 0 2006.162.08:25:43.27#ibcon#*mode == 0, iclass 24, count 0 2006.162.08:25:43.27#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.08:25:43.27#ibcon#[25=BW32\r\n] 2006.162.08:25:43.27#ibcon#*before write, iclass 24, count 0 2006.162.08:25:43.27#ibcon#enter sib2, iclass 24, count 0 2006.162.08:25:43.27#ibcon#flushed, iclass 24, count 0 2006.162.08:25:43.27#ibcon#about to write, iclass 24, count 0 2006.162.08:25:43.27#ibcon#wrote, iclass 24, count 0 2006.162.08:25:43.27#ibcon#about to read 3, iclass 24, count 0 2006.162.08:25:43.30#ibcon#read 3, iclass 24, count 0 2006.162.08:25:43.30#ibcon#about to read 4, iclass 24, count 0 2006.162.08:25:43.30#ibcon#read 4, iclass 24, count 0 2006.162.08:25:43.30#ibcon#about to read 5, iclass 24, count 0 2006.162.08:25:43.30#ibcon#read 5, iclass 24, count 0 2006.162.08:25:43.30#ibcon#about to read 6, iclass 24, count 0 2006.162.08:25:43.30#ibcon#read 6, iclass 24, count 0 2006.162.08:25:43.30#ibcon#end of sib2, iclass 24, count 0 2006.162.08:25:43.30#ibcon#*after write, iclass 24, count 0 2006.162.08:25:43.30#ibcon#*before return 0, iclass 24, count 0 2006.162.08:25:43.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:25:43.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.162.08:25:43.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.08:25:43.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.08:25:43.30$vc4f8/vbbw=wide 2006.162.08:25:43.30#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.162.08:25:43.30#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.162.08:25:43.30#ibcon#ireg 8 cls_cnt 0 2006.162.08:25:43.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:25:43.37#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:25:43.37#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:25:43.37#ibcon#enter wrdev, iclass 26, count 0 2006.162.08:25:43.37#ibcon#first serial, iclass 26, count 0 2006.162.08:25:43.37#ibcon#enter sib2, iclass 26, count 0 2006.162.08:25:43.37#ibcon#flushed, iclass 26, count 0 2006.162.08:25:43.37#ibcon#about to write, iclass 26, count 0 2006.162.08:25:43.37#ibcon#wrote, iclass 26, count 0 2006.162.08:25:43.37#ibcon#about to read 3, iclass 26, count 0 2006.162.08:25:43.39#ibcon#read 3, iclass 26, count 0 2006.162.08:25:43.39#ibcon#about to read 4, iclass 26, count 0 2006.162.08:25:43.39#ibcon#read 4, iclass 26, count 0 2006.162.08:25:43.39#ibcon#about to read 5, iclass 26, count 0 2006.162.08:25:43.39#ibcon#read 5, iclass 26, count 0 2006.162.08:25:43.39#ibcon#about to read 6, iclass 26, count 0 2006.162.08:25:43.39#ibcon#read 6, iclass 26, count 0 2006.162.08:25:43.39#ibcon#end of sib2, iclass 26, count 0 2006.162.08:25:43.39#ibcon#*mode == 0, iclass 26, count 0 2006.162.08:25:43.39#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.162.08:25:43.39#ibcon#[27=BW32\r\n] 2006.162.08:25:43.39#ibcon#*before write, iclass 26, count 0 2006.162.08:25:43.39#ibcon#enter sib2, iclass 26, count 0 2006.162.08:25:43.39#ibcon#flushed, iclass 26, count 0 2006.162.08:25:43.39#ibcon#about to write, iclass 26, count 0 2006.162.08:25:43.39#ibcon#wrote, iclass 26, count 0 2006.162.08:25:43.39#ibcon#about to read 3, iclass 26, count 0 2006.162.08:25:43.42#ibcon#read 3, iclass 26, count 0 2006.162.08:25:43.42#ibcon#about to read 4, iclass 26, count 0 2006.162.08:25:43.42#ibcon#read 4, iclass 26, count 0 2006.162.08:25:43.42#ibcon#about to read 5, iclass 26, count 0 2006.162.08:25:43.42#ibcon#read 5, iclass 26, count 0 2006.162.08:25:43.42#ibcon#about to read 6, iclass 26, count 0 2006.162.08:25:43.42#ibcon#read 6, iclass 26, count 0 2006.162.08:25:43.42#ibcon#end of sib2, iclass 26, count 0 2006.162.08:25:43.42#ibcon#*after write, iclass 26, count 0 2006.162.08:25:43.42#ibcon#*before return 0, iclass 26, count 0 2006.162.08:25:43.42#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:25:43.42#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:25:43.42#ibcon#about to clear, iclass 26 cls_cnt 0 2006.162.08:25:43.42#ibcon#cleared, iclass 26 cls_cnt 0 2006.162.08:25:43.42$4f8m12a/ifd4f 2006.162.08:25:43.42$ifd4f/lo= 2006.162.08:25:43.42$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.08:25:43.42$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.08:25:43.42$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.08:25:43.42$ifd4f/patch= 2006.162.08:25:43.42$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.08:25:43.42$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.08:25:43.42$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.08:25:43.42$4f8m12a/"form=m,16.000,1:2 2006.162.08:25:43.42$4f8m12a/"tpicd 2006.162.08:25:43.42$4f8m12a/echo=off 2006.162.08:25:43.42$4f8m12a/xlog=off 2006.162.08:25:43.42:!2006.162.08:26:40 2006.162.08:25:43.43#abcon#<5=/03 2.3 4.8 17.801001006.9\r\n> 2006.162.08:26:15.14#trakl#Source acquired 2006.162.08:26:15.14#flagr#flagr/antenna,acquired 2006.162.08:26:40.00:preob 2006.162.08:26:40.14/onsource/TRACKING 2006.162.08:26:40.14:!2006.162.08:26:50 2006.162.08:26:50.00:data_valid=on 2006.162.08:26:50.00:midob 2006.162.08:26:51.14/onsource/TRACKING 2006.162.08:26:51.14/wx/17.79,1006.9,100 2006.162.08:26:51.37/cable/+6.5369E-03 2006.162.08:26:52.46/va/01,08,usb,yes,33,35 2006.162.08:26:52.46/va/02,07,usb,yes,33,35 2006.162.08:26:52.46/va/03,06,usb,yes,35,35 2006.162.08:26:52.46/va/04,07,usb,yes,34,37 2006.162.08:26:52.46/va/05,07,usb,yes,36,38 2006.162.08:26:52.46/va/06,06,usb,yes,35,35 2006.162.08:26:52.46/va/07,06,usb,yes,36,36 2006.162.08:26:52.46/va/08,07,usb,yes,34,33 2006.162.08:26:52.69/valo/01,532.99,yes,locked 2006.162.08:26:52.69/valo/02,572.99,yes,locked 2006.162.08:26:52.69/valo/03,672.99,yes,locked 2006.162.08:26:52.69/valo/04,832.99,yes,locked 2006.162.08:26:52.69/valo/05,652.99,yes,locked 2006.162.08:26:52.69/valo/06,772.99,yes,locked 2006.162.08:26:52.69/valo/07,832.99,yes,locked 2006.162.08:26:52.69/valo/08,852.99,yes,locked 2006.162.08:26:53.78/vb/01,04,usb,yes,29,28 2006.162.08:26:53.78/vb/02,04,usb,yes,31,32 2006.162.08:26:53.78/vb/03,04,usb,yes,27,31 2006.162.08:26:53.78/vb/04,04,usb,yes,28,28 2006.162.08:26:53.78/vb/05,04,usb,yes,26,30 2006.162.08:26:53.78/vb/06,04,usb,yes,27,30 2006.162.08:26:53.78/vb/07,04,usb,yes,29,29 2006.162.08:26:53.78/vb/08,04,usb,yes,27,30 2006.162.08:26:54.01/vblo/01,632.99,yes,locked 2006.162.08:26:54.01/vblo/02,640.99,yes,locked 2006.162.08:26:54.01/vblo/03,656.99,yes,locked 2006.162.08:26:54.01/vblo/04,712.99,yes,locked 2006.162.08:26:54.01/vblo/05,744.99,yes,locked 2006.162.08:26:54.01/vblo/06,752.99,yes,locked 2006.162.08:26:54.01/vblo/07,734.99,yes,locked 2006.162.08:26:54.01/vblo/08,744.99,yes,locked 2006.162.08:26:54.16/vabw/8 2006.162.08:26:54.31/vbbw/8 2006.162.08:26:54.51/xfe/off,on,14.7 2006.162.08:26:54.90/ifatt/23,28,28,28 2006.162.08:26:55.08/fmout-gps/S +4.52E-07 2006.162.08:26:55.12:!2006.162.08:27:50 2006.162.08:27:50.00:data_valid=off 2006.162.08:27:50.00:postob 2006.162.08:27:50.22/cable/+6.5360E-03 2006.162.08:27:50.22/wx/17.78,1006.8,100 2006.162.08:27:51.08/fmout-gps/S +4.51E-07 2006.162.08:27:51.08:scan_name=162-0828,k06162,60 2006.162.08:27:51.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.162.08:27:51.14#flagr#flagr/antenna,new-source 2006.162.08:27:52.14:checkk5 2006.162.08:27:52.58/chk_autoobs//k5ts1/ autoobs is running! 2006.162.08:27:53.00/chk_autoobs//k5ts2/ autoobs is running! 2006.162.08:27:53.42/chk_autoobs//k5ts3/ autoobs is running! 2006.162.08:27:53.84/chk_autoobs//k5ts4/ autoobs is running! 2006.162.08:27:54.23/chk_obsdata//k5ts1/T1620826??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:27:54.63/chk_obsdata//k5ts2/T1620826??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:27:55.23/chk_obsdata//k5ts3/T1620826??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:27:55.86/chk_obsdata//k5ts4/T1620826??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:27:56.69/k5log//k5ts1_log_newline 2006.162.08:27:57.42/k5log//k5ts2_log_newline 2006.162.08:27:58.15/k5log//k5ts3_log_newline 2006.162.08:27:58.92/k5log//k5ts4_log_newline 2006.162.08:27:58.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.08:27:58.94:4f8m12a=3 2006.162.08:27:58.94$4f8m12a/echo=on 2006.162.08:27:58.94$4f8m12a/pcalon 2006.162.08:27:58.94$pcalon/"no phase cal control is implemented here 2006.162.08:27:58.94$4f8m12a/"tpicd=stop 2006.162.08:27:58.94$4f8m12a/vc4f8 2006.162.08:27:58.94$vc4f8/valo=1,532.99 2006.162.08:27:58.95#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.162.08:27:58.95#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.162.08:27:58.95#ibcon#ireg 17 cls_cnt 0 2006.162.08:27:58.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.162.08:27:58.95#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.162.08:27:58.95#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.162.08:27:58.95#ibcon#enter wrdev, iclass 13, count 0 2006.162.08:27:58.95#ibcon#first serial, iclass 13, count 0 2006.162.08:27:58.95#ibcon#enter sib2, iclass 13, count 0 2006.162.08:27:58.95#ibcon#flushed, iclass 13, count 0 2006.162.08:27:58.95#ibcon#about to write, iclass 13, count 0 2006.162.08:27:58.95#ibcon#wrote, iclass 13, count 0 2006.162.08:27:58.95#ibcon#about to read 3, iclass 13, count 0 2006.162.08:27:58.99#ibcon#read 3, iclass 13, count 0 2006.162.08:27:58.99#ibcon#about to read 4, iclass 13, count 0 2006.162.08:27:58.99#ibcon#read 4, iclass 13, count 0 2006.162.08:27:58.99#ibcon#about to read 5, iclass 13, count 0 2006.162.08:27:58.99#ibcon#read 5, iclass 13, count 0 2006.162.08:27:58.99#ibcon#about to read 6, iclass 13, count 0 2006.162.08:27:58.99#ibcon#read 6, iclass 13, count 0 2006.162.08:27:58.99#ibcon#end of sib2, iclass 13, count 0 2006.162.08:27:58.99#ibcon#*mode == 0, iclass 13, count 0 2006.162.08:27:58.99#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.162.08:27:58.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.08:27:58.99#ibcon#*before write, iclass 13, count 0 2006.162.08:27:58.99#ibcon#enter sib2, iclass 13, count 0 2006.162.08:27:58.99#ibcon#flushed, iclass 13, count 0 2006.162.08:27:58.99#ibcon#about to write, iclass 13, count 0 2006.162.08:27:58.99#ibcon#wrote, iclass 13, count 0 2006.162.08:27:58.99#ibcon#about to read 3, iclass 13, count 0 2006.162.08:27:59.04#ibcon#read 3, iclass 13, count 0 2006.162.08:27:59.04#ibcon#about to read 4, iclass 13, count 0 2006.162.08:27:59.04#ibcon#read 4, iclass 13, count 0 2006.162.08:27:59.04#ibcon#about to read 5, iclass 13, count 0 2006.162.08:27:59.04#ibcon#read 5, iclass 13, count 0 2006.162.08:27:59.04#ibcon#about to read 6, iclass 13, count 0 2006.162.08:27:59.04#ibcon#read 6, iclass 13, count 0 2006.162.08:27:59.04#ibcon#end of sib2, iclass 13, count 0 2006.162.08:27:59.04#ibcon#*after write, iclass 13, count 0 2006.162.08:27:59.04#ibcon#*before return 0, iclass 13, count 0 2006.162.08:27:59.04#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.162.08:27:59.04#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.162.08:27:59.04#ibcon#about to clear, iclass 13 cls_cnt 0 2006.162.08:27:59.04#ibcon#cleared, iclass 13 cls_cnt 0 2006.162.08:27:59.04$vc4f8/va=1,8 2006.162.08:27:59.04#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.162.08:27:59.04#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.162.08:27:59.04#ibcon#ireg 11 cls_cnt 2 2006.162.08:27:59.04#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.162.08:27:59.04#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.162.08:27:59.04#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.162.08:27:59.04#ibcon#enter wrdev, iclass 15, count 2 2006.162.08:27:59.04#ibcon#first serial, iclass 15, count 2 2006.162.08:27:59.04#ibcon#enter sib2, iclass 15, count 2 2006.162.08:27:59.04#ibcon#flushed, iclass 15, count 2 2006.162.08:27:59.04#ibcon#about to write, iclass 15, count 2 2006.162.08:27:59.04#ibcon#wrote, iclass 15, count 2 2006.162.08:27:59.04#ibcon#about to read 3, iclass 15, count 2 2006.162.08:27:59.06#ibcon#read 3, iclass 15, count 2 2006.162.08:27:59.06#ibcon#about to read 4, iclass 15, count 2 2006.162.08:27:59.06#ibcon#read 4, iclass 15, count 2 2006.162.08:27:59.06#ibcon#about to read 5, iclass 15, count 2 2006.162.08:27:59.06#ibcon#read 5, iclass 15, count 2 2006.162.08:27:59.06#ibcon#about to read 6, iclass 15, count 2 2006.162.08:27:59.06#ibcon#read 6, iclass 15, count 2 2006.162.08:27:59.06#ibcon#end of sib2, iclass 15, count 2 2006.162.08:27:59.06#ibcon#*mode == 0, iclass 15, count 2 2006.162.08:27:59.06#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.162.08:27:59.06#ibcon#[25=AT01-08\r\n] 2006.162.08:27:59.06#ibcon#*before write, iclass 15, count 2 2006.162.08:27:59.06#ibcon#enter sib2, iclass 15, count 2 2006.162.08:27:59.06#ibcon#flushed, iclass 15, count 2 2006.162.08:27:59.06#ibcon#about to write, iclass 15, count 2 2006.162.08:27:59.06#ibcon#wrote, iclass 15, count 2 2006.162.08:27:59.06#ibcon#about to read 3, iclass 15, count 2 2006.162.08:27:59.09#ibcon#read 3, iclass 15, count 2 2006.162.08:27:59.09#ibcon#about to read 4, iclass 15, count 2 2006.162.08:27:59.09#ibcon#read 4, iclass 15, count 2 2006.162.08:27:59.09#ibcon#about to read 5, iclass 15, count 2 2006.162.08:27:59.09#ibcon#read 5, iclass 15, count 2 2006.162.08:27:59.09#ibcon#about to read 6, iclass 15, count 2 2006.162.08:27:59.09#ibcon#read 6, iclass 15, count 2 2006.162.08:27:59.09#ibcon#end of sib2, iclass 15, count 2 2006.162.08:27:59.09#ibcon#*after write, iclass 15, count 2 2006.162.08:27:59.09#ibcon#*before return 0, iclass 15, count 2 2006.162.08:27:59.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.162.08:27:59.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.162.08:27:59.09#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.162.08:27:59.09#ibcon#ireg 7 cls_cnt 0 2006.162.08:27:59.09#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.162.08:27:59.21#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.162.08:27:59.21#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.162.08:27:59.21#ibcon#enter wrdev, iclass 15, count 0 2006.162.08:27:59.21#ibcon#first serial, iclass 15, count 0 2006.162.08:27:59.21#ibcon#enter sib2, iclass 15, count 0 2006.162.08:27:59.21#ibcon#flushed, iclass 15, count 0 2006.162.08:27:59.21#ibcon#about to write, iclass 15, count 0 2006.162.08:27:59.21#ibcon#wrote, iclass 15, count 0 2006.162.08:27:59.21#ibcon#about to read 3, iclass 15, count 0 2006.162.08:27:59.23#ibcon#read 3, iclass 15, count 0 2006.162.08:27:59.23#ibcon#about to read 4, iclass 15, count 0 2006.162.08:27:59.23#ibcon#read 4, iclass 15, count 0 2006.162.08:27:59.23#ibcon#about to read 5, iclass 15, count 0 2006.162.08:27:59.23#ibcon#read 5, iclass 15, count 0 2006.162.08:27:59.23#ibcon#about to read 6, iclass 15, count 0 2006.162.08:27:59.23#ibcon#read 6, iclass 15, count 0 2006.162.08:27:59.23#ibcon#end of sib2, iclass 15, count 0 2006.162.08:27:59.23#ibcon#*mode == 0, iclass 15, count 0 2006.162.08:27:59.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.162.08:27:59.23#ibcon#[25=USB\r\n] 2006.162.08:27:59.23#ibcon#*before write, iclass 15, count 0 2006.162.08:27:59.23#ibcon#enter sib2, iclass 15, count 0 2006.162.08:27:59.23#ibcon#flushed, iclass 15, count 0 2006.162.08:27:59.23#ibcon#about to write, iclass 15, count 0 2006.162.08:27:59.23#ibcon#wrote, iclass 15, count 0 2006.162.08:27:59.23#ibcon#about to read 3, iclass 15, count 0 2006.162.08:27:59.26#ibcon#read 3, iclass 15, count 0 2006.162.08:27:59.26#ibcon#about to read 4, iclass 15, count 0 2006.162.08:27:59.26#ibcon#read 4, iclass 15, count 0 2006.162.08:27:59.26#ibcon#about to read 5, iclass 15, count 0 2006.162.08:27:59.26#ibcon#read 5, iclass 15, count 0 2006.162.08:27:59.26#ibcon#about to read 6, iclass 15, count 0 2006.162.08:27:59.26#ibcon#read 6, iclass 15, count 0 2006.162.08:27:59.26#ibcon#end of sib2, iclass 15, count 0 2006.162.08:27:59.26#ibcon#*after write, iclass 15, count 0 2006.162.08:27:59.26#ibcon#*before return 0, iclass 15, count 0 2006.162.08:27:59.26#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.162.08:27:59.26#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.162.08:27:59.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.162.08:27:59.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.162.08:27:59.26$vc4f8/valo=2,572.99 2006.162.08:27:59.26#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.162.08:27:59.26#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.162.08:27:59.26#ibcon#ireg 17 cls_cnt 0 2006.162.08:27:59.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.162.08:27:59.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.162.08:27:59.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.162.08:27:59.26#ibcon#enter wrdev, iclass 17, count 0 2006.162.08:27:59.26#ibcon#first serial, iclass 17, count 0 2006.162.08:27:59.26#ibcon#enter sib2, iclass 17, count 0 2006.162.08:27:59.26#ibcon#flushed, iclass 17, count 0 2006.162.08:27:59.26#ibcon#about to write, iclass 17, count 0 2006.162.08:27:59.26#ibcon#wrote, iclass 17, count 0 2006.162.08:27:59.26#ibcon#about to read 3, iclass 17, count 0 2006.162.08:27:59.28#ibcon#read 3, iclass 17, count 0 2006.162.08:27:59.28#ibcon#about to read 4, iclass 17, count 0 2006.162.08:27:59.28#ibcon#read 4, iclass 17, count 0 2006.162.08:27:59.28#ibcon#about to read 5, iclass 17, count 0 2006.162.08:27:59.28#ibcon#read 5, iclass 17, count 0 2006.162.08:27:59.28#ibcon#about to read 6, iclass 17, count 0 2006.162.08:27:59.28#ibcon#read 6, iclass 17, count 0 2006.162.08:27:59.28#ibcon#end of sib2, iclass 17, count 0 2006.162.08:27:59.28#ibcon#*mode == 0, iclass 17, count 0 2006.162.08:27:59.28#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.162.08:27:59.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.08:27:59.28#ibcon#*before write, iclass 17, count 0 2006.162.08:27:59.28#ibcon#enter sib2, iclass 17, count 0 2006.162.08:27:59.28#ibcon#flushed, iclass 17, count 0 2006.162.08:27:59.28#ibcon#about to write, iclass 17, count 0 2006.162.08:27:59.28#ibcon#wrote, iclass 17, count 0 2006.162.08:27:59.28#ibcon#about to read 3, iclass 17, count 0 2006.162.08:27:59.32#ibcon#read 3, iclass 17, count 0 2006.162.08:27:59.32#ibcon#about to read 4, iclass 17, count 0 2006.162.08:27:59.32#ibcon#read 4, iclass 17, count 0 2006.162.08:27:59.32#ibcon#about to read 5, iclass 17, count 0 2006.162.08:27:59.32#ibcon#read 5, iclass 17, count 0 2006.162.08:27:59.32#ibcon#about to read 6, iclass 17, count 0 2006.162.08:27:59.32#ibcon#read 6, iclass 17, count 0 2006.162.08:27:59.32#ibcon#end of sib2, iclass 17, count 0 2006.162.08:27:59.32#ibcon#*after write, iclass 17, count 0 2006.162.08:27:59.32#ibcon#*before return 0, iclass 17, count 0 2006.162.08:27:59.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.162.08:27:59.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.162.08:27:59.32#ibcon#about to clear, iclass 17 cls_cnt 0 2006.162.08:27:59.32#ibcon#cleared, iclass 17 cls_cnt 0 2006.162.08:27:59.32$vc4f8/va=2,7 2006.162.08:27:59.32#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.162.08:27:59.32#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.162.08:27:59.32#ibcon#ireg 11 cls_cnt 2 2006.162.08:27:59.32#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.162.08:27:59.38#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.162.08:27:59.38#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.162.08:27:59.38#ibcon#enter wrdev, iclass 19, count 2 2006.162.08:27:59.38#ibcon#first serial, iclass 19, count 2 2006.162.08:27:59.38#ibcon#enter sib2, iclass 19, count 2 2006.162.08:27:59.38#ibcon#flushed, iclass 19, count 2 2006.162.08:27:59.38#ibcon#about to write, iclass 19, count 2 2006.162.08:27:59.38#ibcon#wrote, iclass 19, count 2 2006.162.08:27:59.38#ibcon#about to read 3, iclass 19, count 2 2006.162.08:27:59.40#ibcon#read 3, iclass 19, count 2 2006.162.08:27:59.40#ibcon#about to read 4, iclass 19, count 2 2006.162.08:27:59.40#ibcon#read 4, iclass 19, count 2 2006.162.08:27:59.40#ibcon#about to read 5, iclass 19, count 2 2006.162.08:27:59.40#ibcon#read 5, iclass 19, count 2 2006.162.08:27:59.40#ibcon#about to read 6, iclass 19, count 2 2006.162.08:27:59.40#ibcon#read 6, iclass 19, count 2 2006.162.08:27:59.40#ibcon#end of sib2, iclass 19, count 2 2006.162.08:27:59.40#ibcon#*mode == 0, iclass 19, count 2 2006.162.08:27:59.40#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.162.08:27:59.40#ibcon#[25=AT02-07\r\n] 2006.162.08:27:59.40#ibcon#*before write, iclass 19, count 2 2006.162.08:27:59.40#ibcon#enter sib2, iclass 19, count 2 2006.162.08:27:59.40#ibcon#flushed, iclass 19, count 2 2006.162.08:27:59.40#ibcon#about to write, iclass 19, count 2 2006.162.08:27:59.40#ibcon#wrote, iclass 19, count 2 2006.162.08:27:59.40#ibcon#about to read 3, iclass 19, count 2 2006.162.08:27:59.43#ibcon#read 3, iclass 19, count 2 2006.162.08:27:59.43#ibcon#about to read 4, iclass 19, count 2 2006.162.08:27:59.43#ibcon#read 4, iclass 19, count 2 2006.162.08:27:59.43#ibcon#about to read 5, iclass 19, count 2 2006.162.08:27:59.43#ibcon#read 5, iclass 19, count 2 2006.162.08:27:59.43#ibcon#about to read 6, iclass 19, count 2 2006.162.08:27:59.43#ibcon#read 6, iclass 19, count 2 2006.162.08:27:59.43#ibcon#end of sib2, iclass 19, count 2 2006.162.08:27:59.43#ibcon#*after write, iclass 19, count 2 2006.162.08:27:59.43#ibcon#*before return 0, iclass 19, count 2 2006.162.08:27:59.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.162.08:27:59.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.162.08:27:59.43#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.162.08:27:59.43#ibcon#ireg 7 cls_cnt 0 2006.162.08:27:59.43#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.162.08:27:59.55#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.162.08:27:59.55#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.162.08:27:59.55#ibcon#enter wrdev, iclass 19, count 0 2006.162.08:27:59.55#ibcon#first serial, iclass 19, count 0 2006.162.08:27:59.55#ibcon#enter sib2, iclass 19, count 0 2006.162.08:27:59.55#ibcon#flushed, iclass 19, count 0 2006.162.08:27:59.55#ibcon#about to write, iclass 19, count 0 2006.162.08:27:59.55#ibcon#wrote, iclass 19, count 0 2006.162.08:27:59.55#ibcon#about to read 3, iclass 19, count 0 2006.162.08:27:59.57#ibcon#read 3, iclass 19, count 0 2006.162.08:27:59.57#ibcon#about to read 4, iclass 19, count 0 2006.162.08:27:59.57#ibcon#read 4, iclass 19, count 0 2006.162.08:27:59.57#ibcon#about to read 5, iclass 19, count 0 2006.162.08:27:59.57#ibcon#read 5, iclass 19, count 0 2006.162.08:27:59.57#ibcon#about to read 6, iclass 19, count 0 2006.162.08:27:59.57#ibcon#read 6, iclass 19, count 0 2006.162.08:27:59.57#ibcon#end of sib2, iclass 19, count 0 2006.162.08:27:59.57#ibcon#*mode == 0, iclass 19, count 0 2006.162.08:27:59.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.162.08:27:59.57#ibcon#[25=USB\r\n] 2006.162.08:27:59.57#ibcon#*before write, iclass 19, count 0 2006.162.08:27:59.57#ibcon#enter sib2, iclass 19, count 0 2006.162.08:27:59.57#ibcon#flushed, iclass 19, count 0 2006.162.08:27:59.57#ibcon#about to write, iclass 19, count 0 2006.162.08:27:59.57#ibcon#wrote, iclass 19, count 0 2006.162.08:27:59.57#ibcon#about to read 3, iclass 19, count 0 2006.162.08:27:59.60#ibcon#read 3, iclass 19, count 0 2006.162.08:27:59.60#ibcon#about to read 4, iclass 19, count 0 2006.162.08:27:59.60#ibcon#read 4, iclass 19, count 0 2006.162.08:27:59.60#ibcon#about to read 5, iclass 19, count 0 2006.162.08:27:59.60#ibcon#read 5, iclass 19, count 0 2006.162.08:27:59.60#ibcon#about to read 6, iclass 19, count 0 2006.162.08:27:59.60#ibcon#read 6, iclass 19, count 0 2006.162.08:27:59.60#ibcon#end of sib2, iclass 19, count 0 2006.162.08:27:59.60#ibcon#*after write, iclass 19, count 0 2006.162.08:27:59.60#ibcon#*before return 0, iclass 19, count 0 2006.162.08:27:59.60#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.162.08:27:59.60#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.162.08:27:59.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.162.08:27:59.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.162.08:27:59.60$vc4f8/valo=3,672.99 2006.162.08:27:59.60#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.162.08:27:59.60#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.162.08:27:59.60#ibcon#ireg 17 cls_cnt 0 2006.162.08:27:59.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:27:59.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:27:59.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:27:59.60#ibcon#enter wrdev, iclass 21, count 0 2006.162.08:27:59.60#ibcon#first serial, iclass 21, count 0 2006.162.08:27:59.60#ibcon#enter sib2, iclass 21, count 0 2006.162.08:27:59.60#ibcon#flushed, iclass 21, count 0 2006.162.08:27:59.60#ibcon#about to write, iclass 21, count 0 2006.162.08:27:59.60#ibcon#wrote, iclass 21, count 0 2006.162.08:27:59.60#ibcon#about to read 3, iclass 21, count 0 2006.162.08:27:59.62#ibcon#read 3, iclass 21, count 0 2006.162.08:27:59.62#ibcon#about to read 4, iclass 21, count 0 2006.162.08:27:59.62#ibcon#read 4, iclass 21, count 0 2006.162.08:27:59.62#ibcon#about to read 5, iclass 21, count 0 2006.162.08:27:59.62#ibcon#read 5, iclass 21, count 0 2006.162.08:27:59.62#ibcon#about to read 6, iclass 21, count 0 2006.162.08:27:59.62#ibcon#read 6, iclass 21, count 0 2006.162.08:27:59.62#ibcon#end of sib2, iclass 21, count 0 2006.162.08:27:59.62#ibcon#*mode == 0, iclass 21, count 0 2006.162.08:27:59.62#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.162.08:27:59.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.08:27:59.62#ibcon#*before write, iclass 21, count 0 2006.162.08:27:59.62#ibcon#enter sib2, iclass 21, count 0 2006.162.08:27:59.62#ibcon#flushed, iclass 21, count 0 2006.162.08:27:59.62#ibcon#about to write, iclass 21, count 0 2006.162.08:27:59.62#ibcon#wrote, iclass 21, count 0 2006.162.08:27:59.62#ibcon#about to read 3, iclass 21, count 0 2006.162.08:27:59.66#ibcon#read 3, iclass 21, count 0 2006.162.08:27:59.66#ibcon#about to read 4, iclass 21, count 0 2006.162.08:27:59.66#ibcon#read 4, iclass 21, count 0 2006.162.08:27:59.66#ibcon#about to read 5, iclass 21, count 0 2006.162.08:27:59.66#ibcon#read 5, iclass 21, count 0 2006.162.08:27:59.66#ibcon#about to read 6, iclass 21, count 0 2006.162.08:27:59.66#ibcon#read 6, iclass 21, count 0 2006.162.08:27:59.66#ibcon#end of sib2, iclass 21, count 0 2006.162.08:27:59.66#ibcon#*after write, iclass 21, count 0 2006.162.08:27:59.66#ibcon#*before return 0, iclass 21, count 0 2006.162.08:27:59.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:27:59.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:27:59.66#ibcon#about to clear, iclass 21 cls_cnt 0 2006.162.08:27:59.66#ibcon#cleared, iclass 21 cls_cnt 0 2006.162.08:27:59.66$vc4f8/va=3,6 2006.162.08:27:59.66#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.162.08:27:59.66#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.162.08:27:59.66#ibcon#ireg 11 cls_cnt 2 2006.162.08:27:59.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:27:59.72#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:27:59.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:27:59.72#ibcon#enter wrdev, iclass 23, count 2 2006.162.08:27:59.72#ibcon#first serial, iclass 23, count 2 2006.162.08:27:59.72#ibcon#enter sib2, iclass 23, count 2 2006.162.08:27:59.72#ibcon#flushed, iclass 23, count 2 2006.162.08:27:59.72#ibcon#about to write, iclass 23, count 2 2006.162.08:27:59.72#ibcon#wrote, iclass 23, count 2 2006.162.08:27:59.72#ibcon#about to read 3, iclass 23, count 2 2006.162.08:27:59.74#ibcon#read 3, iclass 23, count 2 2006.162.08:27:59.74#ibcon#about to read 4, iclass 23, count 2 2006.162.08:27:59.74#ibcon#read 4, iclass 23, count 2 2006.162.08:27:59.74#ibcon#about to read 5, iclass 23, count 2 2006.162.08:27:59.74#ibcon#read 5, iclass 23, count 2 2006.162.08:27:59.74#ibcon#about to read 6, iclass 23, count 2 2006.162.08:27:59.74#ibcon#read 6, iclass 23, count 2 2006.162.08:27:59.74#ibcon#end of sib2, iclass 23, count 2 2006.162.08:27:59.74#ibcon#*mode == 0, iclass 23, count 2 2006.162.08:27:59.74#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.162.08:27:59.74#ibcon#[25=AT03-06\r\n] 2006.162.08:27:59.74#ibcon#*before write, iclass 23, count 2 2006.162.08:27:59.74#ibcon#enter sib2, iclass 23, count 2 2006.162.08:27:59.74#ibcon#flushed, iclass 23, count 2 2006.162.08:27:59.74#ibcon#about to write, iclass 23, count 2 2006.162.08:27:59.74#ibcon#wrote, iclass 23, count 2 2006.162.08:27:59.74#ibcon#about to read 3, iclass 23, count 2 2006.162.08:27:59.77#ibcon#read 3, iclass 23, count 2 2006.162.08:27:59.77#ibcon#about to read 4, iclass 23, count 2 2006.162.08:27:59.77#ibcon#read 4, iclass 23, count 2 2006.162.08:27:59.77#ibcon#about to read 5, iclass 23, count 2 2006.162.08:27:59.77#ibcon#read 5, iclass 23, count 2 2006.162.08:27:59.77#ibcon#about to read 6, iclass 23, count 2 2006.162.08:27:59.77#ibcon#read 6, iclass 23, count 2 2006.162.08:27:59.77#ibcon#end of sib2, iclass 23, count 2 2006.162.08:27:59.77#ibcon#*after write, iclass 23, count 2 2006.162.08:27:59.77#ibcon#*before return 0, iclass 23, count 2 2006.162.08:27:59.77#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:27:59.77#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:27:59.77#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.162.08:27:59.77#ibcon#ireg 7 cls_cnt 0 2006.162.08:27:59.77#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:27:59.89#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:27:59.89#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:27:59.89#ibcon#enter wrdev, iclass 23, count 0 2006.162.08:27:59.89#ibcon#first serial, iclass 23, count 0 2006.162.08:27:59.89#ibcon#enter sib2, iclass 23, count 0 2006.162.08:27:59.89#ibcon#flushed, iclass 23, count 0 2006.162.08:27:59.89#ibcon#about to write, iclass 23, count 0 2006.162.08:27:59.89#ibcon#wrote, iclass 23, count 0 2006.162.08:27:59.89#ibcon#about to read 3, iclass 23, count 0 2006.162.08:27:59.91#ibcon#read 3, iclass 23, count 0 2006.162.08:27:59.91#ibcon#about to read 4, iclass 23, count 0 2006.162.08:27:59.91#ibcon#read 4, iclass 23, count 0 2006.162.08:27:59.91#ibcon#about to read 5, iclass 23, count 0 2006.162.08:27:59.91#ibcon#read 5, iclass 23, count 0 2006.162.08:27:59.91#ibcon#about to read 6, iclass 23, count 0 2006.162.08:27:59.91#ibcon#read 6, iclass 23, count 0 2006.162.08:27:59.91#ibcon#end of sib2, iclass 23, count 0 2006.162.08:27:59.91#ibcon#*mode == 0, iclass 23, count 0 2006.162.08:27:59.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.162.08:27:59.91#ibcon#[25=USB\r\n] 2006.162.08:27:59.91#ibcon#*before write, iclass 23, count 0 2006.162.08:27:59.91#ibcon#enter sib2, iclass 23, count 0 2006.162.08:27:59.91#ibcon#flushed, iclass 23, count 0 2006.162.08:27:59.91#ibcon#about to write, iclass 23, count 0 2006.162.08:27:59.91#ibcon#wrote, iclass 23, count 0 2006.162.08:27:59.91#ibcon#about to read 3, iclass 23, count 0 2006.162.08:27:59.94#ibcon#read 3, iclass 23, count 0 2006.162.08:27:59.94#ibcon#about to read 4, iclass 23, count 0 2006.162.08:27:59.94#ibcon#read 4, iclass 23, count 0 2006.162.08:27:59.94#ibcon#about to read 5, iclass 23, count 0 2006.162.08:27:59.94#ibcon#read 5, iclass 23, count 0 2006.162.08:27:59.94#ibcon#about to read 6, iclass 23, count 0 2006.162.08:27:59.94#ibcon#read 6, iclass 23, count 0 2006.162.08:27:59.94#ibcon#end of sib2, iclass 23, count 0 2006.162.08:27:59.94#ibcon#*after write, iclass 23, count 0 2006.162.08:27:59.94#ibcon#*before return 0, iclass 23, count 0 2006.162.08:27:59.94#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:27:59.94#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:27:59.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.162.08:27:59.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.162.08:27:59.94$vc4f8/valo=4,832.99 2006.162.08:27:59.94#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.162.08:27:59.94#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.162.08:27:59.94#ibcon#ireg 17 cls_cnt 0 2006.162.08:27:59.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:27:59.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:27:59.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:27:59.94#ibcon#enter wrdev, iclass 25, count 0 2006.162.08:27:59.94#ibcon#first serial, iclass 25, count 0 2006.162.08:27:59.94#ibcon#enter sib2, iclass 25, count 0 2006.162.08:27:59.94#ibcon#flushed, iclass 25, count 0 2006.162.08:27:59.94#ibcon#about to write, iclass 25, count 0 2006.162.08:27:59.94#ibcon#wrote, iclass 25, count 0 2006.162.08:27:59.94#ibcon#about to read 3, iclass 25, count 0 2006.162.08:27:59.96#ibcon#read 3, iclass 25, count 0 2006.162.08:27:59.96#ibcon#about to read 4, iclass 25, count 0 2006.162.08:27:59.96#ibcon#read 4, iclass 25, count 0 2006.162.08:27:59.96#ibcon#about to read 5, iclass 25, count 0 2006.162.08:27:59.96#ibcon#read 5, iclass 25, count 0 2006.162.08:27:59.96#ibcon#about to read 6, iclass 25, count 0 2006.162.08:27:59.96#ibcon#read 6, iclass 25, count 0 2006.162.08:27:59.96#ibcon#end of sib2, iclass 25, count 0 2006.162.08:27:59.96#ibcon#*mode == 0, iclass 25, count 0 2006.162.08:27:59.96#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.162.08:27:59.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.08:27:59.96#ibcon#*before write, iclass 25, count 0 2006.162.08:27:59.96#ibcon#enter sib2, iclass 25, count 0 2006.162.08:27:59.96#ibcon#flushed, iclass 25, count 0 2006.162.08:27:59.96#ibcon#about to write, iclass 25, count 0 2006.162.08:27:59.96#ibcon#wrote, iclass 25, count 0 2006.162.08:27:59.96#ibcon#about to read 3, iclass 25, count 0 2006.162.08:28:00.00#ibcon#read 3, iclass 25, count 0 2006.162.08:28:00.00#ibcon#about to read 4, iclass 25, count 0 2006.162.08:28:00.00#ibcon#read 4, iclass 25, count 0 2006.162.08:28:00.00#ibcon#about to read 5, iclass 25, count 0 2006.162.08:28:00.00#ibcon#read 5, iclass 25, count 0 2006.162.08:28:00.00#ibcon#about to read 6, iclass 25, count 0 2006.162.08:28:00.00#ibcon#read 6, iclass 25, count 0 2006.162.08:28:00.00#ibcon#end of sib2, iclass 25, count 0 2006.162.08:28:00.00#ibcon#*after write, iclass 25, count 0 2006.162.08:28:00.00#ibcon#*before return 0, iclass 25, count 0 2006.162.08:28:00.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:28:00.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:28:00.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.162.08:28:00.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.162.08:28:00.00$vc4f8/va=4,7 2006.162.08:28:00.00#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.162.08:28:00.00#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.162.08:28:00.00#ibcon#ireg 11 cls_cnt 2 2006.162.08:28:00.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:28:00.06#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:28:00.06#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:28:00.06#ibcon#enter wrdev, iclass 27, count 2 2006.162.08:28:00.06#ibcon#first serial, iclass 27, count 2 2006.162.08:28:00.06#ibcon#enter sib2, iclass 27, count 2 2006.162.08:28:00.06#ibcon#flushed, iclass 27, count 2 2006.162.08:28:00.06#ibcon#about to write, iclass 27, count 2 2006.162.08:28:00.06#ibcon#wrote, iclass 27, count 2 2006.162.08:28:00.06#ibcon#about to read 3, iclass 27, count 2 2006.162.08:28:00.08#ibcon#read 3, iclass 27, count 2 2006.162.08:28:00.08#ibcon#about to read 4, iclass 27, count 2 2006.162.08:28:00.08#ibcon#read 4, iclass 27, count 2 2006.162.08:28:00.08#ibcon#about to read 5, iclass 27, count 2 2006.162.08:28:00.08#ibcon#read 5, iclass 27, count 2 2006.162.08:28:00.08#ibcon#about to read 6, iclass 27, count 2 2006.162.08:28:00.08#ibcon#read 6, iclass 27, count 2 2006.162.08:28:00.08#ibcon#end of sib2, iclass 27, count 2 2006.162.08:28:00.08#ibcon#*mode == 0, iclass 27, count 2 2006.162.08:28:00.08#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.162.08:28:00.08#ibcon#[25=AT04-07\r\n] 2006.162.08:28:00.08#ibcon#*before write, iclass 27, count 2 2006.162.08:28:00.08#ibcon#enter sib2, iclass 27, count 2 2006.162.08:28:00.08#ibcon#flushed, iclass 27, count 2 2006.162.08:28:00.08#ibcon#about to write, iclass 27, count 2 2006.162.08:28:00.08#ibcon#wrote, iclass 27, count 2 2006.162.08:28:00.08#ibcon#about to read 3, iclass 27, count 2 2006.162.08:28:00.11#ibcon#read 3, iclass 27, count 2 2006.162.08:28:00.11#ibcon#about to read 4, iclass 27, count 2 2006.162.08:28:00.11#ibcon#read 4, iclass 27, count 2 2006.162.08:28:00.11#ibcon#about to read 5, iclass 27, count 2 2006.162.08:28:00.11#ibcon#read 5, iclass 27, count 2 2006.162.08:28:00.11#ibcon#about to read 6, iclass 27, count 2 2006.162.08:28:00.11#ibcon#read 6, iclass 27, count 2 2006.162.08:28:00.11#ibcon#end of sib2, iclass 27, count 2 2006.162.08:28:00.11#ibcon#*after write, iclass 27, count 2 2006.162.08:28:00.11#ibcon#*before return 0, iclass 27, count 2 2006.162.08:28:00.11#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:28:00.11#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:28:00.11#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.162.08:28:00.11#ibcon#ireg 7 cls_cnt 0 2006.162.08:28:00.11#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:28:00.23#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:28:00.23#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:28:00.23#ibcon#enter wrdev, iclass 27, count 0 2006.162.08:28:00.23#ibcon#first serial, iclass 27, count 0 2006.162.08:28:00.23#ibcon#enter sib2, iclass 27, count 0 2006.162.08:28:00.23#ibcon#flushed, iclass 27, count 0 2006.162.08:28:00.23#ibcon#about to write, iclass 27, count 0 2006.162.08:28:00.23#ibcon#wrote, iclass 27, count 0 2006.162.08:28:00.23#ibcon#about to read 3, iclass 27, count 0 2006.162.08:28:00.26#ibcon#read 3, iclass 27, count 0 2006.162.08:28:00.26#ibcon#about to read 4, iclass 27, count 0 2006.162.08:28:00.26#ibcon#read 4, iclass 27, count 0 2006.162.08:28:00.26#ibcon#about to read 5, iclass 27, count 0 2006.162.08:28:00.26#ibcon#read 5, iclass 27, count 0 2006.162.08:28:00.26#ibcon#about to read 6, iclass 27, count 0 2006.162.08:28:00.26#ibcon#read 6, iclass 27, count 0 2006.162.08:28:00.26#ibcon#end of sib2, iclass 27, count 0 2006.162.08:28:00.26#ibcon#*mode == 0, iclass 27, count 0 2006.162.08:28:00.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.162.08:28:00.26#ibcon#[25=USB\r\n] 2006.162.08:28:00.26#ibcon#*before write, iclass 27, count 0 2006.162.08:28:00.26#ibcon#enter sib2, iclass 27, count 0 2006.162.08:28:00.26#ibcon#flushed, iclass 27, count 0 2006.162.08:28:00.26#ibcon#about to write, iclass 27, count 0 2006.162.08:28:00.26#ibcon#wrote, iclass 27, count 0 2006.162.08:28:00.26#ibcon#about to read 3, iclass 27, count 0 2006.162.08:28:00.30#ibcon#read 3, iclass 27, count 0 2006.162.08:28:00.30#ibcon#about to read 4, iclass 27, count 0 2006.162.08:28:00.30#ibcon#read 4, iclass 27, count 0 2006.162.08:28:00.30#ibcon#about to read 5, iclass 27, count 0 2006.162.08:28:00.30#ibcon#read 5, iclass 27, count 0 2006.162.08:28:00.30#ibcon#about to read 6, iclass 27, count 0 2006.162.08:28:00.30#ibcon#read 6, iclass 27, count 0 2006.162.08:28:00.30#ibcon#end of sib2, iclass 27, count 0 2006.162.08:28:00.30#ibcon#*after write, iclass 27, count 0 2006.162.08:28:00.30#ibcon#*before return 0, iclass 27, count 0 2006.162.08:28:00.30#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:28:00.30#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:28:00.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.162.08:28:00.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.162.08:28:00.30$vc4f8/valo=5,652.99 2006.162.08:28:00.30#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.162.08:28:00.30#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.162.08:28:00.30#ibcon#ireg 17 cls_cnt 0 2006.162.08:28:00.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:28:00.30#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:28:00.30#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:28:00.30#ibcon#enter wrdev, iclass 29, count 0 2006.162.08:28:00.30#ibcon#first serial, iclass 29, count 0 2006.162.08:28:00.30#ibcon#enter sib2, iclass 29, count 0 2006.162.08:28:00.30#ibcon#flushed, iclass 29, count 0 2006.162.08:28:00.30#ibcon#about to write, iclass 29, count 0 2006.162.08:28:00.30#ibcon#wrote, iclass 29, count 0 2006.162.08:28:00.30#ibcon#about to read 3, iclass 29, count 0 2006.162.08:28:00.32#ibcon#read 3, iclass 29, count 0 2006.162.08:28:00.32#ibcon#about to read 4, iclass 29, count 0 2006.162.08:28:00.32#ibcon#read 4, iclass 29, count 0 2006.162.08:28:00.32#ibcon#about to read 5, iclass 29, count 0 2006.162.08:28:00.32#ibcon#read 5, iclass 29, count 0 2006.162.08:28:00.32#ibcon#about to read 6, iclass 29, count 0 2006.162.08:28:00.32#ibcon#read 6, iclass 29, count 0 2006.162.08:28:00.32#ibcon#end of sib2, iclass 29, count 0 2006.162.08:28:00.32#ibcon#*mode == 0, iclass 29, count 0 2006.162.08:28:00.32#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.162.08:28:00.32#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.08:28:00.32#ibcon#*before write, iclass 29, count 0 2006.162.08:28:00.32#ibcon#enter sib2, iclass 29, count 0 2006.162.08:28:00.32#ibcon#flushed, iclass 29, count 0 2006.162.08:28:00.32#ibcon#about to write, iclass 29, count 0 2006.162.08:28:00.32#ibcon#wrote, iclass 29, count 0 2006.162.08:28:00.32#ibcon#about to read 3, iclass 29, count 0 2006.162.08:28:00.36#ibcon#read 3, iclass 29, count 0 2006.162.08:28:00.36#ibcon#about to read 4, iclass 29, count 0 2006.162.08:28:00.36#ibcon#read 4, iclass 29, count 0 2006.162.08:28:00.36#ibcon#about to read 5, iclass 29, count 0 2006.162.08:28:00.36#ibcon#read 5, iclass 29, count 0 2006.162.08:28:00.36#ibcon#about to read 6, iclass 29, count 0 2006.162.08:28:00.36#ibcon#read 6, iclass 29, count 0 2006.162.08:28:00.36#ibcon#end of sib2, iclass 29, count 0 2006.162.08:28:00.36#ibcon#*after write, iclass 29, count 0 2006.162.08:28:00.36#ibcon#*before return 0, iclass 29, count 0 2006.162.08:28:00.36#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:28:00.36#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:28:00.36#ibcon#about to clear, iclass 29 cls_cnt 0 2006.162.08:28:00.36#ibcon#cleared, iclass 29 cls_cnt 0 2006.162.08:28:00.36$vc4f8/va=5,7 2006.162.08:28:00.36#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.162.08:28:00.36#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.162.08:28:00.36#ibcon#ireg 11 cls_cnt 2 2006.162.08:28:00.36#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:28:00.42#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:28:00.42#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:28:00.42#ibcon#enter wrdev, iclass 31, count 2 2006.162.08:28:00.42#ibcon#first serial, iclass 31, count 2 2006.162.08:28:00.42#ibcon#enter sib2, iclass 31, count 2 2006.162.08:28:00.42#ibcon#flushed, iclass 31, count 2 2006.162.08:28:00.42#ibcon#about to write, iclass 31, count 2 2006.162.08:28:00.42#ibcon#wrote, iclass 31, count 2 2006.162.08:28:00.42#ibcon#about to read 3, iclass 31, count 2 2006.162.08:28:00.44#ibcon#read 3, iclass 31, count 2 2006.162.08:28:00.44#ibcon#about to read 4, iclass 31, count 2 2006.162.08:28:00.44#ibcon#read 4, iclass 31, count 2 2006.162.08:28:00.44#ibcon#about to read 5, iclass 31, count 2 2006.162.08:28:00.44#ibcon#read 5, iclass 31, count 2 2006.162.08:28:00.44#ibcon#about to read 6, iclass 31, count 2 2006.162.08:28:00.44#ibcon#read 6, iclass 31, count 2 2006.162.08:28:00.44#ibcon#end of sib2, iclass 31, count 2 2006.162.08:28:00.44#ibcon#*mode == 0, iclass 31, count 2 2006.162.08:28:00.44#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.162.08:28:00.44#ibcon#[25=AT05-07\r\n] 2006.162.08:28:00.44#ibcon#*before write, iclass 31, count 2 2006.162.08:28:00.44#ibcon#enter sib2, iclass 31, count 2 2006.162.08:28:00.44#ibcon#flushed, iclass 31, count 2 2006.162.08:28:00.44#ibcon#about to write, iclass 31, count 2 2006.162.08:28:00.44#ibcon#wrote, iclass 31, count 2 2006.162.08:28:00.44#ibcon#about to read 3, iclass 31, count 2 2006.162.08:28:00.48#ibcon#read 3, iclass 31, count 2 2006.162.08:28:00.48#ibcon#about to read 4, iclass 31, count 2 2006.162.08:28:00.48#ibcon#read 4, iclass 31, count 2 2006.162.08:28:00.48#ibcon#about to read 5, iclass 31, count 2 2006.162.08:28:00.48#ibcon#read 5, iclass 31, count 2 2006.162.08:28:00.48#ibcon#about to read 6, iclass 31, count 2 2006.162.08:28:00.48#ibcon#read 6, iclass 31, count 2 2006.162.08:28:00.48#ibcon#end of sib2, iclass 31, count 2 2006.162.08:28:00.48#ibcon#*after write, iclass 31, count 2 2006.162.08:28:00.48#ibcon#*before return 0, iclass 31, count 2 2006.162.08:28:00.48#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:28:00.48#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:28:00.48#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.162.08:28:00.48#ibcon#ireg 7 cls_cnt 0 2006.162.08:28:00.48#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:28:00.60#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:28:00.60#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:28:00.60#ibcon#enter wrdev, iclass 31, count 0 2006.162.08:28:00.60#ibcon#first serial, iclass 31, count 0 2006.162.08:28:00.60#ibcon#enter sib2, iclass 31, count 0 2006.162.08:28:00.60#ibcon#flushed, iclass 31, count 0 2006.162.08:28:00.60#ibcon#about to write, iclass 31, count 0 2006.162.08:28:00.60#ibcon#wrote, iclass 31, count 0 2006.162.08:28:00.60#ibcon#about to read 3, iclass 31, count 0 2006.162.08:28:00.62#ibcon#read 3, iclass 31, count 0 2006.162.08:28:00.62#ibcon#about to read 4, iclass 31, count 0 2006.162.08:28:00.62#ibcon#read 4, iclass 31, count 0 2006.162.08:28:00.62#ibcon#about to read 5, iclass 31, count 0 2006.162.08:28:00.62#ibcon#read 5, iclass 31, count 0 2006.162.08:28:00.62#ibcon#about to read 6, iclass 31, count 0 2006.162.08:28:00.62#ibcon#read 6, iclass 31, count 0 2006.162.08:28:00.62#ibcon#end of sib2, iclass 31, count 0 2006.162.08:28:00.62#ibcon#*mode == 0, iclass 31, count 0 2006.162.08:28:00.62#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.162.08:28:00.62#ibcon#[25=USB\r\n] 2006.162.08:28:00.62#ibcon#*before write, iclass 31, count 0 2006.162.08:28:00.62#ibcon#enter sib2, iclass 31, count 0 2006.162.08:28:00.62#ibcon#flushed, iclass 31, count 0 2006.162.08:28:00.62#ibcon#about to write, iclass 31, count 0 2006.162.08:28:00.62#ibcon#wrote, iclass 31, count 0 2006.162.08:28:00.62#ibcon#about to read 3, iclass 31, count 0 2006.162.08:28:00.65#ibcon#read 3, iclass 31, count 0 2006.162.08:28:00.65#ibcon#about to read 4, iclass 31, count 0 2006.162.08:28:00.65#ibcon#read 4, iclass 31, count 0 2006.162.08:28:00.65#ibcon#about to read 5, iclass 31, count 0 2006.162.08:28:00.65#ibcon#read 5, iclass 31, count 0 2006.162.08:28:00.65#ibcon#about to read 6, iclass 31, count 0 2006.162.08:28:00.65#ibcon#read 6, iclass 31, count 0 2006.162.08:28:00.65#ibcon#end of sib2, iclass 31, count 0 2006.162.08:28:00.65#ibcon#*after write, iclass 31, count 0 2006.162.08:28:00.65#ibcon#*before return 0, iclass 31, count 0 2006.162.08:28:00.65#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:28:00.65#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:28:00.65#ibcon#about to clear, iclass 31 cls_cnt 0 2006.162.08:28:00.65#ibcon#cleared, iclass 31 cls_cnt 0 2006.162.08:28:00.65$vc4f8/valo=6,772.99 2006.162.08:28:00.65#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.162.08:28:00.65#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.162.08:28:00.65#ibcon#ireg 17 cls_cnt 0 2006.162.08:28:00.65#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:28:00.65#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:28:00.65#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:28:00.65#ibcon#enter wrdev, iclass 33, count 0 2006.162.08:28:00.65#ibcon#first serial, iclass 33, count 0 2006.162.08:28:00.65#ibcon#enter sib2, iclass 33, count 0 2006.162.08:28:00.65#ibcon#flushed, iclass 33, count 0 2006.162.08:28:00.65#ibcon#about to write, iclass 33, count 0 2006.162.08:28:00.65#ibcon#wrote, iclass 33, count 0 2006.162.08:28:00.65#ibcon#about to read 3, iclass 33, count 0 2006.162.08:28:00.67#ibcon#read 3, iclass 33, count 0 2006.162.08:28:00.67#ibcon#about to read 4, iclass 33, count 0 2006.162.08:28:00.67#ibcon#read 4, iclass 33, count 0 2006.162.08:28:00.67#ibcon#about to read 5, iclass 33, count 0 2006.162.08:28:00.67#ibcon#read 5, iclass 33, count 0 2006.162.08:28:00.67#ibcon#about to read 6, iclass 33, count 0 2006.162.08:28:00.67#ibcon#read 6, iclass 33, count 0 2006.162.08:28:00.67#ibcon#end of sib2, iclass 33, count 0 2006.162.08:28:00.67#ibcon#*mode == 0, iclass 33, count 0 2006.162.08:28:00.67#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.162.08:28:00.67#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.08:28:00.67#ibcon#*before write, iclass 33, count 0 2006.162.08:28:00.67#ibcon#enter sib2, iclass 33, count 0 2006.162.08:28:00.67#ibcon#flushed, iclass 33, count 0 2006.162.08:28:00.67#ibcon#about to write, iclass 33, count 0 2006.162.08:28:00.67#ibcon#wrote, iclass 33, count 0 2006.162.08:28:00.67#ibcon#about to read 3, iclass 33, count 0 2006.162.08:28:00.71#ibcon#read 3, iclass 33, count 0 2006.162.08:28:00.71#ibcon#about to read 4, iclass 33, count 0 2006.162.08:28:00.71#ibcon#read 4, iclass 33, count 0 2006.162.08:28:00.71#ibcon#about to read 5, iclass 33, count 0 2006.162.08:28:00.71#ibcon#read 5, iclass 33, count 0 2006.162.08:28:00.71#ibcon#about to read 6, iclass 33, count 0 2006.162.08:28:00.71#ibcon#read 6, iclass 33, count 0 2006.162.08:28:00.71#ibcon#end of sib2, iclass 33, count 0 2006.162.08:28:00.71#ibcon#*after write, iclass 33, count 0 2006.162.08:28:00.71#ibcon#*before return 0, iclass 33, count 0 2006.162.08:28:00.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:28:00.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:28:00.71#ibcon#about to clear, iclass 33 cls_cnt 0 2006.162.08:28:00.71#ibcon#cleared, iclass 33 cls_cnt 0 2006.162.08:28:00.71$vc4f8/va=6,6 2006.162.08:28:00.71#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.162.08:28:00.71#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.162.08:28:00.71#ibcon#ireg 11 cls_cnt 2 2006.162.08:28:00.71#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.162.08:28:00.77#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.162.08:28:00.77#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.162.08:28:00.77#ibcon#enter wrdev, iclass 35, count 2 2006.162.08:28:00.77#ibcon#first serial, iclass 35, count 2 2006.162.08:28:00.77#ibcon#enter sib2, iclass 35, count 2 2006.162.08:28:00.77#ibcon#flushed, iclass 35, count 2 2006.162.08:28:00.77#ibcon#about to write, iclass 35, count 2 2006.162.08:28:00.77#ibcon#wrote, iclass 35, count 2 2006.162.08:28:00.77#ibcon#about to read 3, iclass 35, count 2 2006.162.08:28:00.79#ibcon#read 3, iclass 35, count 2 2006.162.08:28:00.79#ibcon#about to read 4, iclass 35, count 2 2006.162.08:28:00.79#ibcon#read 4, iclass 35, count 2 2006.162.08:28:00.79#ibcon#about to read 5, iclass 35, count 2 2006.162.08:28:00.79#ibcon#read 5, iclass 35, count 2 2006.162.08:28:00.79#ibcon#about to read 6, iclass 35, count 2 2006.162.08:28:00.79#ibcon#read 6, iclass 35, count 2 2006.162.08:28:00.79#ibcon#end of sib2, iclass 35, count 2 2006.162.08:28:00.79#ibcon#*mode == 0, iclass 35, count 2 2006.162.08:28:00.79#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.162.08:28:00.79#ibcon#[25=AT06-06\r\n] 2006.162.08:28:00.79#ibcon#*before write, iclass 35, count 2 2006.162.08:28:00.79#ibcon#enter sib2, iclass 35, count 2 2006.162.08:28:00.79#ibcon#flushed, iclass 35, count 2 2006.162.08:28:00.79#ibcon#about to write, iclass 35, count 2 2006.162.08:28:00.79#ibcon#wrote, iclass 35, count 2 2006.162.08:28:00.79#ibcon#about to read 3, iclass 35, count 2 2006.162.08:28:00.82#ibcon#read 3, iclass 35, count 2 2006.162.08:28:00.82#ibcon#about to read 4, iclass 35, count 2 2006.162.08:28:00.82#ibcon#read 4, iclass 35, count 2 2006.162.08:28:00.82#ibcon#about to read 5, iclass 35, count 2 2006.162.08:28:00.82#ibcon#read 5, iclass 35, count 2 2006.162.08:28:00.82#ibcon#about to read 6, iclass 35, count 2 2006.162.08:28:00.82#ibcon#read 6, iclass 35, count 2 2006.162.08:28:00.82#ibcon#end of sib2, iclass 35, count 2 2006.162.08:28:00.82#ibcon#*after write, iclass 35, count 2 2006.162.08:28:00.82#ibcon#*before return 0, iclass 35, count 2 2006.162.08:28:00.82#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.162.08:28:00.82#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.162.08:28:00.82#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.162.08:28:00.82#ibcon#ireg 7 cls_cnt 0 2006.162.08:28:00.82#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.162.08:28:00.94#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.162.08:28:00.94#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.162.08:28:00.94#ibcon#enter wrdev, iclass 35, count 0 2006.162.08:28:00.94#ibcon#first serial, iclass 35, count 0 2006.162.08:28:00.94#ibcon#enter sib2, iclass 35, count 0 2006.162.08:28:00.94#ibcon#flushed, iclass 35, count 0 2006.162.08:28:00.94#ibcon#about to write, iclass 35, count 0 2006.162.08:28:00.94#ibcon#wrote, iclass 35, count 0 2006.162.08:28:00.94#ibcon#about to read 3, iclass 35, count 0 2006.162.08:28:00.96#ibcon#read 3, iclass 35, count 0 2006.162.08:28:00.96#ibcon#about to read 4, iclass 35, count 0 2006.162.08:28:00.96#ibcon#read 4, iclass 35, count 0 2006.162.08:28:00.96#ibcon#about to read 5, iclass 35, count 0 2006.162.08:28:00.96#ibcon#read 5, iclass 35, count 0 2006.162.08:28:00.96#ibcon#about to read 6, iclass 35, count 0 2006.162.08:28:00.96#ibcon#read 6, iclass 35, count 0 2006.162.08:28:00.96#ibcon#end of sib2, iclass 35, count 0 2006.162.08:28:00.96#ibcon#*mode == 0, iclass 35, count 0 2006.162.08:28:00.96#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.162.08:28:00.96#ibcon#[25=USB\r\n] 2006.162.08:28:00.96#ibcon#*before write, iclass 35, count 0 2006.162.08:28:00.96#ibcon#enter sib2, iclass 35, count 0 2006.162.08:28:00.96#ibcon#flushed, iclass 35, count 0 2006.162.08:28:00.96#ibcon#about to write, iclass 35, count 0 2006.162.08:28:00.96#ibcon#wrote, iclass 35, count 0 2006.162.08:28:00.96#ibcon#about to read 3, iclass 35, count 0 2006.162.08:28:00.99#ibcon#read 3, iclass 35, count 0 2006.162.08:28:00.99#ibcon#about to read 4, iclass 35, count 0 2006.162.08:28:00.99#ibcon#read 4, iclass 35, count 0 2006.162.08:28:00.99#ibcon#about to read 5, iclass 35, count 0 2006.162.08:28:00.99#ibcon#read 5, iclass 35, count 0 2006.162.08:28:00.99#ibcon#about to read 6, iclass 35, count 0 2006.162.08:28:00.99#ibcon#read 6, iclass 35, count 0 2006.162.08:28:00.99#ibcon#end of sib2, iclass 35, count 0 2006.162.08:28:00.99#ibcon#*after write, iclass 35, count 0 2006.162.08:28:00.99#ibcon#*before return 0, iclass 35, count 0 2006.162.08:28:00.99#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.162.08:28:00.99#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.162.08:28:00.99#ibcon#about to clear, iclass 35 cls_cnt 0 2006.162.08:28:00.99#ibcon#cleared, iclass 35 cls_cnt 0 2006.162.08:28:00.99$vc4f8/valo=7,832.99 2006.162.08:28:00.99#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.162.08:28:00.99#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.162.08:28:00.99#ibcon#ireg 17 cls_cnt 0 2006.162.08:28:00.99#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.162.08:28:00.99#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.162.08:28:00.99#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.162.08:28:00.99#ibcon#enter wrdev, iclass 37, count 0 2006.162.08:28:00.99#ibcon#first serial, iclass 37, count 0 2006.162.08:28:00.99#ibcon#enter sib2, iclass 37, count 0 2006.162.08:28:00.99#ibcon#flushed, iclass 37, count 0 2006.162.08:28:00.99#ibcon#about to write, iclass 37, count 0 2006.162.08:28:00.99#ibcon#wrote, iclass 37, count 0 2006.162.08:28:00.99#ibcon#about to read 3, iclass 37, count 0 2006.162.08:28:01.01#ibcon#read 3, iclass 37, count 0 2006.162.08:28:01.01#ibcon#about to read 4, iclass 37, count 0 2006.162.08:28:01.01#ibcon#read 4, iclass 37, count 0 2006.162.08:28:01.01#ibcon#about to read 5, iclass 37, count 0 2006.162.08:28:01.01#ibcon#read 5, iclass 37, count 0 2006.162.08:28:01.01#ibcon#about to read 6, iclass 37, count 0 2006.162.08:28:01.01#ibcon#read 6, iclass 37, count 0 2006.162.08:28:01.01#ibcon#end of sib2, iclass 37, count 0 2006.162.08:28:01.01#ibcon#*mode == 0, iclass 37, count 0 2006.162.08:28:01.01#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.162.08:28:01.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.08:28:01.01#ibcon#*before write, iclass 37, count 0 2006.162.08:28:01.01#ibcon#enter sib2, iclass 37, count 0 2006.162.08:28:01.01#ibcon#flushed, iclass 37, count 0 2006.162.08:28:01.01#ibcon#about to write, iclass 37, count 0 2006.162.08:28:01.01#ibcon#wrote, iclass 37, count 0 2006.162.08:28:01.01#ibcon#about to read 3, iclass 37, count 0 2006.162.08:28:01.05#ibcon#read 3, iclass 37, count 0 2006.162.08:28:01.05#ibcon#about to read 4, iclass 37, count 0 2006.162.08:28:01.05#ibcon#read 4, iclass 37, count 0 2006.162.08:28:01.05#ibcon#about to read 5, iclass 37, count 0 2006.162.08:28:01.05#ibcon#read 5, iclass 37, count 0 2006.162.08:28:01.05#ibcon#about to read 6, iclass 37, count 0 2006.162.08:28:01.05#ibcon#read 6, iclass 37, count 0 2006.162.08:28:01.05#ibcon#end of sib2, iclass 37, count 0 2006.162.08:28:01.05#ibcon#*after write, iclass 37, count 0 2006.162.08:28:01.05#ibcon#*before return 0, iclass 37, count 0 2006.162.08:28:01.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.162.08:28:01.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.162.08:28:01.05#ibcon#about to clear, iclass 37 cls_cnt 0 2006.162.08:28:01.05#ibcon#cleared, iclass 37 cls_cnt 0 2006.162.08:28:01.05$vc4f8/va=7,6 2006.162.08:28:01.05#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.162.08:28:01.05#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.162.08:28:01.05#ibcon#ireg 11 cls_cnt 2 2006.162.08:28:01.05#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.162.08:28:01.11#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.162.08:28:01.11#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.162.08:28:01.11#ibcon#enter wrdev, iclass 39, count 2 2006.162.08:28:01.11#ibcon#first serial, iclass 39, count 2 2006.162.08:28:01.11#ibcon#enter sib2, iclass 39, count 2 2006.162.08:28:01.11#ibcon#flushed, iclass 39, count 2 2006.162.08:28:01.11#ibcon#about to write, iclass 39, count 2 2006.162.08:28:01.11#ibcon#wrote, iclass 39, count 2 2006.162.08:28:01.11#ibcon#about to read 3, iclass 39, count 2 2006.162.08:28:01.13#ibcon#read 3, iclass 39, count 2 2006.162.08:28:01.13#ibcon#about to read 4, iclass 39, count 2 2006.162.08:28:01.13#ibcon#read 4, iclass 39, count 2 2006.162.08:28:01.13#ibcon#about to read 5, iclass 39, count 2 2006.162.08:28:01.13#ibcon#read 5, iclass 39, count 2 2006.162.08:28:01.13#ibcon#about to read 6, iclass 39, count 2 2006.162.08:28:01.13#ibcon#read 6, iclass 39, count 2 2006.162.08:28:01.13#ibcon#end of sib2, iclass 39, count 2 2006.162.08:28:01.13#ibcon#*mode == 0, iclass 39, count 2 2006.162.08:28:01.13#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.162.08:28:01.13#ibcon#[25=AT07-06\r\n] 2006.162.08:28:01.13#ibcon#*before write, iclass 39, count 2 2006.162.08:28:01.13#ibcon#enter sib2, iclass 39, count 2 2006.162.08:28:01.13#ibcon#flushed, iclass 39, count 2 2006.162.08:28:01.13#ibcon#about to write, iclass 39, count 2 2006.162.08:28:01.13#ibcon#wrote, iclass 39, count 2 2006.162.08:28:01.13#ibcon#about to read 3, iclass 39, count 2 2006.162.08:28:01.16#ibcon#read 3, iclass 39, count 2 2006.162.08:28:01.16#ibcon#about to read 4, iclass 39, count 2 2006.162.08:28:01.16#ibcon#read 4, iclass 39, count 2 2006.162.08:28:01.16#ibcon#about to read 5, iclass 39, count 2 2006.162.08:28:01.16#ibcon#read 5, iclass 39, count 2 2006.162.08:28:01.16#ibcon#about to read 6, iclass 39, count 2 2006.162.08:28:01.16#ibcon#read 6, iclass 39, count 2 2006.162.08:28:01.16#ibcon#end of sib2, iclass 39, count 2 2006.162.08:28:01.16#ibcon#*after write, iclass 39, count 2 2006.162.08:28:01.16#ibcon#*before return 0, iclass 39, count 2 2006.162.08:28:01.16#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.162.08:28:01.16#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.162.08:28:01.16#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.162.08:28:01.16#ibcon#ireg 7 cls_cnt 0 2006.162.08:28:01.16#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.162.08:28:01.28#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.162.08:28:01.28#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.162.08:28:01.28#ibcon#enter wrdev, iclass 39, count 0 2006.162.08:28:01.28#ibcon#first serial, iclass 39, count 0 2006.162.08:28:01.28#ibcon#enter sib2, iclass 39, count 0 2006.162.08:28:01.28#ibcon#flushed, iclass 39, count 0 2006.162.08:28:01.28#ibcon#about to write, iclass 39, count 0 2006.162.08:28:01.28#ibcon#wrote, iclass 39, count 0 2006.162.08:28:01.28#ibcon#about to read 3, iclass 39, count 0 2006.162.08:28:01.30#ibcon#read 3, iclass 39, count 0 2006.162.08:28:01.30#ibcon#about to read 4, iclass 39, count 0 2006.162.08:28:01.30#ibcon#read 4, iclass 39, count 0 2006.162.08:28:01.30#ibcon#about to read 5, iclass 39, count 0 2006.162.08:28:01.30#ibcon#read 5, iclass 39, count 0 2006.162.08:28:01.30#ibcon#about to read 6, iclass 39, count 0 2006.162.08:28:01.30#ibcon#read 6, iclass 39, count 0 2006.162.08:28:01.30#ibcon#end of sib2, iclass 39, count 0 2006.162.08:28:01.30#ibcon#*mode == 0, iclass 39, count 0 2006.162.08:28:01.30#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.162.08:28:01.30#ibcon#[25=USB\r\n] 2006.162.08:28:01.30#ibcon#*before write, iclass 39, count 0 2006.162.08:28:01.30#ibcon#enter sib2, iclass 39, count 0 2006.162.08:28:01.30#ibcon#flushed, iclass 39, count 0 2006.162.08:28:01.30#ibcon#about to write, iclass 39, count 0 2006.162.08:28:01.30#ibcon#wrote, iclass 39, count 0 2006.162.08:28:01.30#ibcon#about to read 3, iclass 39, count 0 2006.162.08:28:01.33#ibcon#read 3, iclass 39, count 0 2006.162.08:28:01.33#ibcon#about to read 4, iclass 39, count 0 2006.162.08:28:01.33#ibcon#read 4, iclass 39, count 0 2006.162.08:28:01.33#ibcon#about to read 5, iclass 39, count 0 2006.162.08:28:01.33#ibcon#read 5, iclass 39, count 0 2006.162.08:28:01.33#ibcon#about to read 6, iclass 39, count 0 2006.162.08:28:01.33#ibcon#read 6, iclass 39, count 0 2006.162.08:28:01.33#ibcon#end of sib2, iclass 39, count 0 2006.162.08:28:01.33#ibcon#*after write, iclass 39, count 0 2006.162.08:28:01.33#ibcon#*before return 0, iclass 39, count 0 2006.162.08:28:01.33#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.162.08:28:01.33#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.162.08:28:01.33#ibcon#about to clear, iclass 39 cls_cnt 0 2006.162.08:28:01.33#ibcon#cleared, iclass 39 cls_cnt 0 2006.162.08:28:01.33$vc4f8/valo=8,852.99 2006.162.08:28:01.33#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.162.08:28:01.33#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.162.08:28:01.33#ibcon#ireg 17 cls_cnt 0 2006.162.08:28:01.33#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.162.08:28:01.33#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.162.08:28:01.33#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.162.08:28:01.33#ibcon#enter wrdev, iclass 3, count 0 2006.162.08:28:01.33#ibcon#first serial, iclass 3, count 0 2006.162.08:28:01.33#ibcon#enter sib2, iclass 3, count 0 2006.162.08:28:01.33#ibcon#flushed, iclass 3, count 0 2006.162.08:28:01.33#ibcon#about to write, iclass 3, count 0 2006.162.08:28:01.33#ibcon#wrote, iclass 3, count 0 2006.162.08:28:01.33#ibcon#about to read 3, iclass 3, count 0 2006.162.08:28:01.35#ibcon#read 3, iclass 3, count 0 2006.162.08:28:01.35#ibcon#about to read 4, iclass 3, count 0 2006.162.08:28:01.35#ibcon#read 4, iclass 3, count 0 2006.162.08:28:01.35#ibcon#about to read 5, iclass 3, count 0 2006.162.08:28:01.35#ibcon#read 5, iclass 3, count 0 2006.162.08:28:01.35#ibcon#about to read 6, iclass 3, count 0 2006.162.08:28:01.35#ibcon#read 6, iclass 3, count 0 2006.162.08:28:01.35#ibcon#end of sib2, iclass 3, count 0 2006.162.08:28:01.35#ibcon#*mode == 0, iclass 3, count 0 2006.162.08:28:01.35#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.162.08:28:01.35#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.08:28:01.35#ibcon#*before write, iclass 3, count 0 2006.162.08:28:01.35#ibcon#enter sib2, iclass 3, count 0 2006.162.08:28:01.35#ibcon#flushed, iclass 3, count 0 2006.162.08:28:01.35#ibcon#about to write, iclass 3, count 0 2006.162.08:28:01.35#ibcon#wrote, iclass 3, count 0 2006.162.08:28:01.35#ibcon#about to read 3, iclass 3, count 0 2006.162.08:28:01.39#ibcon#read 3, iclass 3, count 0 2006.162.08:28:01.39#ibcon#about to read 4, iclass 3, count 0 2006.162.08:28:01.39#ibcon#read 4, iclass 3, count 0 2006.162.08:28:01.39#ibcon#about to read 5, iclass 3, count 0 2006.162.08:28:01.39#ibcon#read 5, iclass 3, count 0 2006.162.08:28:01.39#ibcon#about to read 6, iclass 3, count 0 2006.162.08:28:01.39#ibcon#read 6, iclass 3, count 0 2006.162.08:28:01.39#ibcon#end of sib2, iclass 3, count 0 2006.162.08:28:01.39#ibcon#*after write, iclass 3, count 0 2006.162.08:28:01.39#ibcon#*before return 0, iclass 3, count 0 2006.162.08:28:01.39#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.162.08:28:01.39#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.162.08:28:01.39#ibcon#about to clear, iclass 3 cls_cnt 0 2006.162.08:28:01.39#ibcon#cleared, iclass 3 cls_cnt 0 2006.162.08:28:01.39$vc4f8/va=8,7 2006.162.08:28:01.39#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.162.08:28:01.39#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.162.08:28:01.39#ibcon#ireg 11 cls_cnt 2 2006.162.08:28:01.39#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.162.08:28:01.45#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.162.08:28:01.45#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.162.08:28:01.45#ibcon#enter wrdev, iclass 5, count 2 2006.162.08:28:01.45#ibcon#first serial, iclass 5, count 2 2006.162.08:28:01.45#ibcon#enter sib2, iclass 5, count 2 2006.162.08:28:01.45#ibcon#flushed, iclass 5, count 2 2006.162.08:28:01.45#ibcon#about to write, iclass 5, count 2 2006.162.08:28:01.45#ibcon#wrote, iclass 5, count 2 2006.162.08:28:01.45#ibcon#about to read 3, iclass 5, count 2 2006.162.08:28:01.47#ibcon#read 3, iclass 5, count 2 2006.162.08:28:01.47#ibcon#about to read 4, iclass 5, count 2 2006.162.08:28:01.47#ibcon#read 4, iclass 5, count 2 2006.162.08:28:01.47#ibcon#about to read 5, iclass 5, count 2 2006.162.08:28:01.47#ibcon#read 5, iclass 5, count 2 2006.162.08:28:01.47#ibcon#about to read 6, iclass 5, count 2 2006.162.08:28:01.47#ibcon#read 6, iclass 5, count 2 2006.162.08:28:01.47#ibcon#end of sib2, iclass 5, count 2 2006.162.08:28:01.47#ibcon#*mode == 0, iclass 5, count 2 2006.162.08:28:01.47#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.162.08:28:01.47#ibcon#[25=AT08-07\r\n] 2006.162.08:28:01.47#ibcon#*before write, iclass 5, count 2 2006.162.08:28:01.47#ibcon#enter sib2, iclass 5, count 2 2006.162.08:28:01.47#ibcon#flushed, iclass 5, count 2 2006.162.08:28:01.47#ibcon#about to write, iclass 5, count 2 2006.162.08:28:01.47#ibcon#wrote, iclass 5, count 2 2006.162.08:28:01.47#ibcon#about to read 3, iclass 5, count 2 2006.162.08:28:01.50#ibcon#read 3, iclass 5, count 2 2006.162.08:28:01.50#ibcon#about to read 4, iclass 5, count 2 2006.162.08:28:01.50#ibcon#read 4, iclass 5, count 2 2006.162.08:28:01.50#ibcon#about to read 5, iclass 5, count 2 2006.162.08:28:01.50#ibcon#read 5, iclass 5, count 2 2006.162.08:28:01.50#ibcon#about to read 6, iclass 5, count 2 2006.162.08:28:01.50#ibcon#read 6, iclass 5, count 2 2006.162.08:28:01.50#ibcon#end of sib2, iclass 5, count 2 2006.162.08:28:01.50#ibcon#*after write, iclass 5, count 2 2006.162.08:28:01.50#ibcon#*before return 0, iclass 5, count 2 2006.162.08:28:01.50#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.162.08:28:01.50#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.162.08:28:01.50#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.162.08:28:01.50#ibcon#ireg 7 cls_cnt 0 2006.162.08:28:01.50#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.162.08:28:01.62#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.162.08:28:01.62#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.162.08:28:01.62#ibcon#enter wrdev, iclass 5, count 0 2006.162.08:28:01.62#ibcon#first serial, iclass 5, count 0 2006.162.08:28:01.62#ibcon#enter sib2, iclass 5, count 0 2006.162.08:28:01.62#ibcon#flushed, iclass 5, count 0 2006.162.08:28:01.62#ibcon#about to write, iclass 5, count 0 2006.162.08:28:01.62#ibcon#wrote, iclass 5, count 0 2006.162.08:28:01.62#ibcon#about to read 3, iclass 5, count 0 2006.162.08:28:01.64#ibcon#read 3, iclass 5, count 0 2006.162.08:28:01.64#ibcon#about to read 4, iclass 5, count 0 2006.162.08:28:01.64#ibcon#read 4, iclass 5, count 0 2006.162.08:28:01.64#ibcon#about to read 5, iclass 5, count 0 2006.162.08:28:01.64#ibcon#read 5, iclass 5, count 0 2006.162.08:28:01.64#ibcon#about to read 6, iclass 5, count 0 2006.162.08:28:01.64#ibcon#read 6, iclass 5, count 0 2006.162.08:28:01.64#ibcon#end of sib2, iclass 5, count 0 2006.162.08:28:01.64#ibcon#*mode == 0, iclass 5, count 0 2006.162.08:28:01.64#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.162.08:28:01.64#ibcon#[25=USB\r\n] 2006.162.08:28:01.64#ibcon#*before write, iclass 5, count 0 2006.162.08:28:01.64#ibcon#enter sib2, iclass 5, count 0 2006.162.08:28:01.64#ibcon#flushed, iclass 5, count 0 2006.162.08:28:01.64#ibcon#about to write, iclass 5, count 0 2006.162.08:28:01.64#ibcon#wrote, iclass 5, count 0 2006.162.08:28:01.64#ibcon#about to read 3, iclass 5, count 0 2006.162.08:28:01.67#ibcon#read 3, iclass 5, count 0 2006.162.08:28:01.67#ibcon#about to read 4, iclass 5, count 0 2006.162.08:28:01.67#ibcon#read 4, iclass 5, count 0 2006.162.08:28:01.67#ibcon#about to read 5, iclass 5, count 0 2006.162.08:28:01.67#ibcon#read 5, iclass 5, count 0 2006.162.08:28:01.67#ibcon#about to read 6, iclass 5, count 0 2006.162.08:28:01.67#ibcon#read 6, iclass 5, count 0 2006.162.08:28:01.67#ibcon#end of sib2, iclass 5, count 0 2006.162.08:28:01.67#ibcon#*after write, iclass 5, count 0 2006.162.08:28:01.67#ibcon#*before return 0, iclass 5, count 0 2006.162.08:28:01.67#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.162.08:28:01.67#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.162.08:28:01.67#ibcon#about to clear, iclass 5 cls_cnt 0 2006.162.08:28:01.67#ibcon#cleared, iclass 5 cls_cnt 0 2006.162.08:28:01.67$vc4f8/vblo=1,632.99 2006.162.08:28:01.67#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.162.08:28:01.67#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.162.08:28:01.67#ibcon#ireg 17 cls_cnt 0 2006.162.08:28:01.67#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.162.08:28:01.67#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.162.08:28:01.67#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.162.08:28:01.67#ibcon#enter wrdev, iclass 7, count 0 2006.162.08:28:01.67#ibcon#first serial, iclass 7, count 0 2006.162.08:28:01.67#ibcon#enter sib2, iclass 7, count 0 2006.162.08:28:01.67#ibcon#flushed, iclass 7, count 0 2006.162.08:28:01.67#ibcon#about to write, iclass 7, count 0 2006.162.08:28:01.67#ibcon#wrote, iclass 7, count 0 2006.162.08:28:01.67#ibcon#about to read 3, iclass 7, count 0 2006.162.08:28:01.69#ibcon#read 3, iclass 7, count 0 2006.162.08:28:01.69#ibcon#about to read 4, iclass 7, count 0 2006.162.08:28:01.69#ibcon#read 4, iclass 7, count 0 2006.162.08:28:01.69#ibcon#about to read 5, iclass 7, count 0 2006.162.08:28:01.69#ibcon#read 5, iclass 7, count 0 2006.162.08:28:01.69#ibcon#about to read 6, iclass 7, count 0 2006.162.08:28:01.69#ibcon#read 6, iclass 7, count 0 2006.162.08:28:01.69#ibcon#end of sib2, iclass 7, count 0 2006.162.08:28:01.69#ibcon#*mode == 0, iclass 7, count 0 2006.162.08:28:01.69#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.162.08:28:01.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.08:28:01.69#ibcon#*before write, iclass 7, count 0 2006.162.08:28:01.69#ibcon#enter sib2, iclass 7, count 0 2006.162.08:28:01.69#ibcon#flushed, iclass 7, count 0 2006.162.08:28:01.69#ibcon#about to write, iclass 7, count 0 2006.162.08:28:01.69#ibcon#wrote, iclass 7, count 0 2006.162.08:28:01.69#ibcon#about to read 3, iclass 7, count 0 2006.162.08:28:01.73#ibcon#read 3, iclass 7, count 0 2006.162.08:28:01.73#ibcon#about to read 4, iclass 7, count 0 2006.162.08:28:01.73#ibcon#read 4, iclass 7, count 0 2006.162.08:28:01.73#ibcon#about to read 5, iclass 7, count 0 2006.162.08:28:01.73#ibcon#read 5, iclass 7, count 0 2006.162.08:28:01.73#ibcon#about to read 6, iclass 7, count 0 2006.162.08:28:01.73#ibcon#read 6, iclass 7, count 0 2006.162.08:28:01.73#ibcon#end of sib2, iclass 7, count 0 2006.162.08:28:01.73#ibcon#*after write, iclass 7, count 0 2006.162.08:28:01.73#ibcon#*before return 0, iclass 7, count 0 2006.162.08:28:01.73#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.162.08:28:01.73#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.162.08:28:01.73#ibcon#about to clear, iclass 7 cls_cnt 0 2006.162.08:28:01.73#ibcon#cleared, iclass 7 cls_cnt 0 2006.162.08:28:01.73$vc4f8/vb=1,4 2006.162.08:28:01.73#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.162.08:28:01.73#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.162.08:28:01.73#ibcon#ireg 11 cls_cnt 2 2006.162.08:28:01.73#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.162.08:28:01.73#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.162.08:28:01.73#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.162.08:28:01.73#ibcon#enter wrdev, iclass 11, count 2 2006.162.08:28:01.73#ibcon#first serial, iclass 11, count 2 2006.162.08:28:01.73#ibcon#enter sib2, iclass 11, count 2 2006.162.08:28:01.73#ibcon#flushed, iclass 11, count 2 2006.162.08:28:01.73#ibcon#about to write, iclass 11, count 2 2006.162.08:28:01.73#ibcon#wrote, iclass 11, count 2 2006.162.08:28:01.73#ibcon#about to read 3, iclass 11, count 2 2006.162.08:28:01.75#ibcon#read 3, iclass 11, count 2 2006.162.08:28:01.75#ibcon#about to read 4, iclass 11, count 2 2006.162.08:28:01.75#ibcon#read 4, iclass 11, count 2 2006.162.08:28:01.75#ibcon#about to read 5, iclass 11, count 2 2006.162.08:28:01.75#ibcon#read 5, iclass 11, count 2 2006.162.08:28:01.75#ibcon#about to read 6, iclass 11, count 2 2006.162.08:28:01.75#ibcon#read 6, iclass 11, count 2 2006.162.08:28:01.75#ibcon#end of sib2, iclass 11, count 2 2006.162.08:28:01.75#ibcon#*mode == 0, iclass 11, count 2 2006.162.08:28:01.75#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.162.08:28:01.75#ibcon#[27=AT01-04\r\n] 2006.162.08:28:01.75#ibcon#*before write, iclass 11, count 2 2006.162.08:28:01.75#ibcon#enter sib2, iclass 11, count 2 2006.162.08:28:01.75#ibcon#flushed, iclass 11, count 2 2006.162.08:28:01.75#ibcon#about to write, iclass 11, count 2 2006.162.08:28:01.75#ibcon#wrote, iclass 11, count 2 2006.162.08:28:01.75#ibcon#about to read 3, iclass 11, count 2 2006.162.08:28:01.78#ibcon#read 3, iclass 11, count 2 2006.162.08:28:01.78#ibcon#about to read 4, iclass 11, count 2 2006.162.08:28:01.78#ibcon#read 4, iclass 11, count 2 2006.162.08:28:01.78#ibcon#about to read 5, iclass 11, count 2 2006.162.08:28:01.78#ibcon#read 5, iclass 11, count 2 2006.162.08:28:01.78#ibcon#about to read 6, iclass 11, count 2 2006.162.08:28:01.78#ibcon#read 6, iclass 11, count 2 2006.162.08:28:01.78#ibcon#end of sib2, iclass 11, count 2 2006.162.08:28:01.78#ibcon#*after write, iclass 11, count 2 2006.162.08:28:01.78#ibcon#*before return 0, iclass 11, count 2 2006.162.08:28:01.78#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.162.08:28:01.78#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.162.08:28:01.78#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.162.08:28:01.78#ibcon#ireg 7 cls_cnt 0 2006.162.08:28:01.78#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.162.08:28:01.90#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.162.08:28:01.90#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.162.08:28:01.90#ibcon#enter wrdev, iclass 11, count 0 2006.162.08:28:01.90#ibcon#first serial, iclass 11, count 0 2006.162.08:28:01.90#ibcon#enter sib2, iclass 11, count 0 2006.162.08:28:01.90#ibcon#flushed, iclass 11, count 0 2006.162.08:28:01.90#ibcon#about to write, iclass 11, count 0 2006.162.08:28:01.90#ibcon#wrote, iclass 11, count 0 2006.162.08:28:01.90#ibcon#about to read 3, iclass 11, count 0 2006.162.08:28:01.92#ibcon#read 3, iclass 11, count 0 2006.162.08:28:01.92#ibcon#about to read 4, iclass 11, count 0 2006.162.08:28:01.92#ibcon#read 4, iclass 11, count 0 2006.162.08:28:01.92#ibcon#about to read 5, iclass 11, count 0 2006.162.08:28:01.92#ibcon#read 5, iclass 11, count 0 2006.162.08:28:01.92#ibcon#about to read 6, iclass 11, count 0 2006.162.08:28:01.92#ibcon#read 6, iclass 11, count 0 2006.162.08:28:01.92#ibcon#end of sib2, iclass 11, count 0 2006.162.08:28:01.92#ibcon#*mode == 0, iclass 11, count 0 2006.162.08:28:01.92#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.162.08:28:01.92#ibcon#[27=USB\r\n] 2006.162.08:28:01.92#ibcon#*before write, iclass 11, count 0 2006.162.08:28:01.92#ibcon#enter sib2, iclass 11, count 0 2006.162.08:28:01.92#ibcon#flushed, iclass 11, count 0 2006.162.08:28:01.92#ibcon#about to write, iclass 11, count 0 2006.162.08:28:01.92#ibcon#wrote, iclass 11, count 0 2006.162.08:28:01.92#ibcon#about to read 3, iclass 11, count 0 2006.162.08:28:01.95#ibcon#read 3, iclass 11, count 0 2006.162.08:28:01.95#ibcon#about to read 4, iclass 11, count 0 2006.162.08:28:01.95#ibcon#read 4, iclass 11, count 0 2006.162.08:28:01.95#ibcon#about to read 5, iclass 11, count 0 2006.162.08:28:01.95#ibcon#read 5, iclass 11, count 0 2006.162.08:28:01.95#ibcon#about to read 6, iclass 11, count 0 2006.162.08:28:01.95#ibcon#read 6, iclass 11, count 0 2006.162.08:28:01.95#ibcon#end of sib2, iclass 11, count 0 2006.162.08:28:01.95#ibcon#*after write, iclass 11, count 0 2006.162.08:28:01.95#ibcon#*before return 0, iclass 11, count 0 2006.162.08:28:01.95#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.162.08:28:01.95#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.162.08:28:01.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.162.08:28:01.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.162.08:28:01.95$vc4f8/vblo=2,640.99 2006.162.08:28:01.95#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.162.08:28:01.95#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.162.08:28:01.95#ibcon#ireg 17 cls_cnt 0 2006.162.08:28:01.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.162.08:28:01.95#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.162.08:28:01.95#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.162.08:28:01.95#ibcon#enter wrdev, iclass 13, count 0 2006.162.08:28:01.95#ibcon#first serial, iclass 13, count 0 2006.162.08:28:01.95#ibcon#enter sib2, iclass 13, count 0 2006.162.08:28:01.95#ibcon#flushed, iclass 13, count 0 2006.162.08:28:01.95#ibcon#about to write, iclass 13, count 0 2006.162.08:28:01.95#ibcon#wrote, iclass 13, count 0 2006.162.08:28:01.95#ibcon#about to read 3, iclass 13, count 0 2006.162.08:28:01.97#ibcon#read 3, iclass 13, count 0 2006.162.08:28:01.97#ibcon#about to read 4, iclass 13, count 0 2006.162.08:28:01.97#ibcon#read 4, iclass 13, count 0 2006.162.08:28:01.97#ibcon#about to read 5, iclass 13, count 0 2006.162.08:28:01.97#ibcon#read 5, iclass 13, count 0 2006.162.08:28:01.97#ibcon#about to read 6, iclass 13, count 0 2006.162.08:28:01.97#ibcon#read 6, iclass 13, count 0 2006.162.08:28:01.97#ibcon#end of sib2, iclass 13, count 0 2006.162.08:28:01.97#ibcon#*mode == 0, iclass 13, count 0 2006.162.08:28:01.97#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.162.08:28:01.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.08:28:01.97#ibcon#*before write, iclass 13, count 0 2006.162.08:28:01.97#ibcon#enter sib2, iclass 13, count 0 2006.162.08:28:01.97#ibcon#flushed, iclass 13, count 0 2006.162.08:28:01.97#ibcon#about to write, iclass 13, count 0 2006.162.08:28:01.97#ibcon#wrote, iclass 13, count 0 2006.162.08:28:01.97#ibcon#about to read 3, iclass 13, count 0 2006.162.08:28:02.01#ibcon#read 3, iclass 13, count 0 2006.162.08:28:02.01#ibcon#about to read 4, iclass 13, count 0 2006.162.08:28:02.01#ibcon#read 4, iclass 13, count 0 2006.162.08:28:02.01#ibcon#about to read 5, iclass 13, count 0 2006.162.08:28:02.01#ibcon#read 5, iclass 13, count 0 2006.162.08:28:02.01#ibcon#about to read 6, iclass 13, count 0 2006.162.08:28:02.01#ibcon#read 6, iclass 13, count 0 2006.162.08:28:02.01#ibcon#end of sib2, iclass 13, count 0 2006.162.08:28:02.01#ibcon#*after write, iclass 13, count 0 2006.162.08:28:02.01#ibcon#*before return 0, iclass 13, count 0 2006.162.08:28:02.01#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.162.08:28:02.01#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.162.08:28:02.01#ibcon#about to clear, iclass 13 cls_cnt 0 2006.162.08:28:02.01#ibcon#cleared, iclass 13 cls_cnt 0 2006.162.08:28:02.01$vc4f8/vb=2,4 2006.162.08:28:02.01#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.162.08:28:02.01#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.162.08:28:02.01#ibcon#ireg 11 cls_cnt 2 2006.162.08:28:02.01#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.162.08:28:02.07#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.162.08:28:02.07#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.162.08:28:02.07#ibcon#enter wrdev, iclass 15, count 2 2006.162.08:28:02.07#ibcon#first serial, iclass 15, count 2 2006.162.08:28:02.07#ibcon#enter sib2, iclass 15, count 2 2006.162.08:28:02.07#ibcon#flushed, iclass 15, count 2 2006.162.08:28:02.07#ibcon#about to write, iclass 15, count 2 2006.162.08:28:02.07#ibcon#wrote, iclass 15, count 2 2006.162.08:28:02.07#ibcon#about to read 3, iclass 15, count 2 2006.162.08:28:02.09#ibcon#read 3, iclass 15, count 2 2006.162.08:28:02.09#ibcon#about to read 4, iclass 15, count 2 2006.162.08:28:02.09#ibcon#read 4, iclass 15, count 2 2006.162.08:28:02.09#ibcon#about to read 5, iclass 15, count 2 2006.162.08:28:02.09#ibcon#read 5, iclass 15, count 2 2006.162.08:28:02.09#ibcon#about to read 6, iclass 15, count 2 2006.162.08:28:02.09#ibcon#read 6, iclass 15, count 2 2006.162.08:28:02.09#ibcon#end of sib2, iclass 15, count 2 2006.162.08:28:02.09#ibcon#*mode == 0, iclass 15, count 2 2006.162.08:28:02.09#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.162.08:28:02.09#ibcon#[27=AT02-04\r\n] 2006.162.08:28:02.09#ibcon#*before write, iclass 15, count 2 2006.162.08:28:02.09#ibcon#enter sib2, iclass 15, count 2 2006.162.08:28:02.09#ibcon#flushed, iclass 15, count 2 2006.162.08:28:02.09#ibcon#about to write, iclass 15, count 2 2006.162.08:28:02.09#ibcon#wrote, iclass 15, count 2 2006.162.08:28:02.09#ibcon#about to read 3, iclass 15, count 2 2006.162.08:28:02.12#ibcon#read 3, iclass 15, count 2 2006.162.08:28:02.12#ibcon#about to read 4, iclass 15, count 2 2006.162.08:28:02.12#ibcon#read 4, iclass 15, count 2 2006.162.08:28:02.12#ibcon#about to read 5, iclass 15, count 2 2006.162.08:28:02.12#ibcon#read 5, iclass 15, count 2 2006.162.08:28:02.12#ibcon#about to read 6, iclass 15, count 2 2006.162.08:28:02.12#ibcon#read 6, iclass 15, count 2 2006.162.08:28:02.12#ibcon#end of sib2, iclass 15, count 2 2006.162.08:28:02.12#ibcon#*after write, iclass 15, count 2 2006.162.08:28:02.12#ibcon#*before return 0, iclass 15, count 2 2006.162.08:28:02.12#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.162.08:28:02.12#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.162.08:28:02.12#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.162.08:28:02.12#ibcon#ireg 7 cls_cnt 0 2006.162.08:28:02.12#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.162.08:28:02.24#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.162.08:28:02.24#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.162.08:28:02.24#ibcon#enter wrdev, iclass 15, count 0 2006.162.08:28:02.24#ibcon#first serial, iclass 15, count 0 2006.162.08:28:02.24#ibcon#enter sib2, iclass 15, count 0 2006.162.08:28:02.24#ibcon#flushed, iclass 15, count 0 2006.162.08:28:02.24#ibcon#about to write, iclass 15, count 0 2006.162.08:28:02.24#ibcon#wrote, iclass 15, count 0 2006.162.08:28:02.24#ibcon#about to read 3, iclass 15, count 0 2006.162.08:28:02.26#ibcon#read 3, iclass 15, count 0 2006.162.08:28:02.26#ibcon#about to read 4, iclass 15, count 0 2006.162.08:28:02.26#ibcon#read 4, iclass 15, count 0 2006.162.08:28:02.26#ibcon#about to read 5, iclass 15, count 0 2006.162.08:28:02.26#ibcon#read 5, iclass 15, count 0 2006.162.08:28:02.26#ibcon#about to read 6, iclass 15, count 0 2006.162.08:28:02.26#ibcon#read 6, iclass 15, count 0 2006.162.08:28:02.26#ibcon#end of sib2, iclass 15, count 0 2006.162.08:28:02.26#ibcon#*mode == 0, iclass 15, count 0 2006.162.08:28:02.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.162.08:28:02.26#ibcon#[27=USB\r\n] 2006.162.08:28:02.26#ibcon#*before write, iclass 15, count 0 2006.162.08:28:02.26#ibcon#enter sib2, iclass 15, count 0 2006.162.08:28:02.26#ibcon#flushed, iclass 15, count 0 2006.162.08:28:02.26#ibcon#about to write, iclass 15, count 0 2006.162.08:28:02.26#ibcon#wrote, iclass 15, count 0 2006.162.08:28:02.26#ibcon#about to read 3, iclass 15, count 0 2006.162.08:28:02.29#ibcon#read 3, iclass 15, count 0 2006.162.08:28:02.29#ibcon#about to read 4, iclass 15, count 0 2006.162.08:28:02.29#ibcon#read 4, iclass 15, count 0 2006.162.08:28:02.29#ibcon#about to read 5, iclass 15, count 0 2006.162.08:28:02.29#ibcon#read 5, iclass 15, count 0 2006.162.08:28:02.29#ibcon#about to read 6, iclass 15, count 0 2006.162.08:28:02.29#ibcon#read 6, iclass 15, count 0 2006.162.08:28:02.29#ibcon#end of sib2, iclass 15, count 0 2006.162.08:28:02.29#ibcon#*after write, iclass 15, count 0 2006.162.08:28:02.29#ibcon#*before return 0, iclass 15, count 0 2006.162.08:28:02.29#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.162.08:28:02.29#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.162.08:28:02.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.162.08:28:02.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.162.08:28:02.29$vc4f8/vblo=3,656.99 2006.162.08:28:02.29#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.162.08:28:02.29#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.162.08:28:02.29#ibcon#ireg 17 cls_cnt 0 2006.162.08:28:02.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.162.08:28:02.29#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.162.08:28:02.29#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.162.08:28:02.29#ibcon#enter wrdev, iclass 17, count 0 2006.162.08:28:02.29#ibcon#first serial, iclass 17, count 0 2006.162.08:28:02.29#ibcon#enter sib2, iclass 17, count 0 2006.162.08:28:02.29#ibcon#flushed, iclass 17, count 0 2006.162.08:28:02.29#ibcon#about to write, iclass 17, count 0 2006.162.08:28:02.29#ibcon#wrote, iclass 17, count 0 2006.162.08:28:02.29#ibcon#about to read 3, iclass 17, count 0 2006.162.08:28:02.31#ibcon#read 3, iclass 17, count 0 2006.162.08:28:02.31#ibcon#about to read 4, iclass 17, count 0 2006.162.08:28:02.31#ibcon#read 4, iclass 17, count 0 2006.162.08:28:02.31#ibcon#about to read 5, iclass 17, count 0 2006.162.08:28:02.31#ibcon#read 5, iclass 17, count 0 2006.162.08:28:02.31#ibcon#about to read 6, iclass 17, count 0 2006.162.08:28:02.31#ibcon#read 6, iclass 17, count 0 2006.162.08:28:02.31#ibcon#end of sib2, iclass 17, count 0 2006.162.08:28:02.31#ibcon#*mode == 0, iclass 17, count 0 2006.162.08:28:02.31#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.162.08:28:02.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.08:28:02.31#ibcon#*before write, iclass 17, count 0 2006.162.08:28:02.31#ibcon#enter sib2, iclass 17, count 0 2006.162.08:28:02.31#ibcon#flushed, iclass 17, count 0 2006.162.08:28:02.31#ibcon#about to write, iclass 17, count 0 2006.162.08:28:02.31#ibcon#wrote, iclass 17, count 0 2006.162.08:28:02.31#ibcon#about to read 3, iclass 17, count 0 2006.162.08:28:02.35#ibcon#read 3, iclass 17, count 0 2006.162.08:28:02.35#ibcon#about to read 4, iclass 17, count 0 2006.162.08:28:02.35#ibcon#read 4, iclass 17, count 0 2006.162.08:28:02.35#ibcon#about to read 5, iclass 17, count 0 2006.162.08:28:02.35#ibcon#read 5, iclass 17, count 0 2006.162.08:28:02.35#ibcon#about to read 6, iclass 17, count 0 2006.162.08:28:02.35#ibcon#read 6, iclass 17, count 0 2006.162.08:28:02.35#ibcon#end of sib2, iclass 17, count 0 2006.162.08:28:02.35#ibcon#*after write, iclass 17, count 0 2006.162.08:28:02.35#ibcon#*before return 0, iclass 17, count 0 2006.162.08:28:02.35#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.162.08:28:02.35#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.162.08:28:02.35#ibcon#about to clear, iclass 17 cls_cnt 0 2006.162.08:28:02.35#ibcon#cleared, iclass 17 cls_cnt 0 2006.162.08:28:02.35$vc4f8/vb=3,4 2006.162.08:28:02.35#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.162.08:28:02.35#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.162.08:28:02.35#ibcon#ireg 11 cls_cnt 2 2006.162.08:28:02.35#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.162.08:28:02.41#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.162.08:28:02.41#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.162.08:28:02.41#ibcon#enter wrdev, iclass 19, count 2 2006.162.08:28:02.41#ibcon#first serial, iclass 19, count 2 2006.162.08:28:02.41#ibcon#enter sib2, iclass 19, count 2 2006.162.08:28:02.41#ibcon#flushed, iclass 19, count 2 2006.162.08:28:02.41#ibcon#about to write, iclass 19, count 2 2006.162.08:28:02.41#ibcon#wrote, iclass 19, count 2 2006.162.08:28:02.41#ibcon#about to read 3, iclass 19, count 2 2006.162.08:28:02.43#ibcon#read 3, iclass 19, count 2 2006.162.08:28:02.43#ibcon#about to read 4, iclass 19, count 2 2006.162.08:28:02.43#ibcon#read 4, iclass 19, count 2 2006.162.08:28:02.43#ibcon#about to read 5, iclass 19, count 2 2006.162.08:28:02.43#ibcon#read 5, iclass 19, count 2 2006.162.08:28:02.43#ibcon#about to read 6, iclass 19, count 2 2006.162.08:28:02.43#ibcon#read 6, iclass 19, count 2 2006.162.08:28:02.43#ibcon#end of sib2, iclass 19, count 2 2006.162.08:28:02.43#ibcon#*mode == 0, iclass 19, count 2 2006.162.08:28:02.43#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.162.08:28:02.43#ibcon#[27=AT03-04\r\n] 2006.162.08:28:02.43#ibcon#*before write, iclass 19, count 2 2006.162.08:28:02.43#ibcon#enter sib2, iclass 19, count 2 2006.162.08:28:02.43#ibcon#flushed, iclass 19, count 2 2006.162.08:28:02.43#ibcon#about to write, iclass 19, count 2 2006.162.08:28:02.43#ibcon#wrote, iclass 19, count 2 2006.162.08:28:02.43#ibcon#about to read 3, iclass 19, count 2 2006.162.08:28:02.46#ibcon#read 3, iclass 19, count 2 2006.162.08:28:02.46#ibcon#about to read 4, iclass 19, count 2 2006.162.08:28:02.46#ibcon#read 4, iclass 19, count 2 2006.162.08:28:02.46#ibcon#about to read 5, iclass 19, count 2 2006.162.08:28:02.46#ibcon#read 5, iclass 19, count 2 2006.162.08:28:02.46#ibcon#about to read 6, iclass 19, count 2 2006.162.08:28:02.46#ibcon#read 6, iclass 19, count 2 2006.162.08:28:02.46#ibcon#end of sib2, iclass 19, count 2 2006.162.08:28:02.46#ibcon#*after write, iclass 19, count 2 2006.162.08:28:02.46#ibcon#*before return 0, iclass 19, count 2 2006.162.08:28:02.46#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.162.08:28:02.46#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.162.08:28:02.46#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.162.08:28:02.46#ibcon#ireg 7 cls_cnt 0 2006.162.08:28:02.46#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.162.08:28:02.58#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.162.08:28:02.58#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.162.08:28:02.58#ibcon#enter wrdev, iclass 19, count 0 2006.162.08:28:02.58#ibcon#first serial, iclass 19, count 0 2006.162.08:28:02.58#ibcon#enter sib2, iclass 19, count 0 2006.162.08:28:02.58#ibcon#flushed, iclass 19, count 0 2006.162.08:28:02.58#ibcon#about to write, iclass 19, count 0 2006.162.08:28:02.58#ibcon#wrote, iclass 19, count 0 2006.162.08:28:02.58#ibcon#about to read 3, iclass 19, count 0 2006.162.08:28:02.61#ibcon#read 3, iclass 19, count 0 2006.162.08:28:02.61#ibcon#about to read 4, iclass 19, count 0 2006.162.08:28:02.61#ibcon#read 4, iclass 19, count 0 2006.162.08:28:02.61#ibcon#about to read 5, iclass 19, count 0 2006.162.08:28:02.61#ibcon#read 5, iclass 19, count 0 2006.162.08:28:02.61#ibcon#about to read 6, iclass 19, count 0 2006.162.08:28:02.61#ibcon#read 6, iclass 19, count 0 2006.162.08:28:02.61#ibcon#end of sib2, iclass 19, count 0 2006.162.08:28:02.61#ibcon#*mode == 0, iclass 19, count 0 2006.162.08:28:02.61#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.162.08:28:02.61#ibcon#[27=USB\r\n] 2006.162.08:28:02.61#ibcon#*before write, iclass 19, count 0 2006.162.08:28:02.61#ibcon#enter sib2, iclass 19, count 0 2006.162.08:28:02.61#ibcon#flushed, iclass 19, count 0 2006.162.08:28:02.61#ibcon#about to write, iclass 19, count 0 2006.162.08:28:02.61#ibcon#wrote, iclass 19, count 0 2006.162.08:28:02.61#ibcon#about to read 3, iclass 19, count 0 2006.162.08:28:02.65#ibcon#read 3, iclass 19, count 0 2006.162.08:28:02.65#ibcon#about to read 4, iclass 19, count 0 2006.162.08:28:02.65#ibcon#read 4, iclass 19, count 0 2006.162.08:28:02.65#ibcon#about to read 5, iclass 19, count 0 2006.162.08:28:02.65#ibcon#read 5, iclass 19, count 0 2006.162.08:28:02.65#ibcon#about to read 6, iclass 19, count 0 2006.162.08:28:02.65#ibcon#read 6, iclass 19, count 0 2006.162.08:28:02.65#ibcon#end of sib2, iclass 19, count 0 2006.162.08:28:02.65#ibcon#*after write, iclass 19, count 0 2006.162.08:28:02.65#ibcon#*before return 0, iclass 19, count 0 2006.162.08:28:02.65#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.162.08:28:02.65#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.162.08:28:02.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.162.08:28:02.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.162.08:28:02.65$vc4f8/vblo=4,712.99 2006.162.08:28:02.65#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.162.08:28:02.65#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.162.08:28:02.65#ibcon#ireg 17 cls_cnt 0 2006.162.08:28:02.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:28:02.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:28:02.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:28:02.65#ibcon#enter wrdev, iclass 21, count 0 2006.162.08:28:02.65#ibcon#first serial, iclass 21, count 0 2006.162.08:28:02.65#ibcon#enter sib2, iclass 21, count 0 2006.162.08:28:02.65#ibcon#flushed, iclass 21, count 0 2006.162.08:28:02.65#ibcon#about to write, iclass 21, count 0 2006.162.08:28:02.65#ibcon#wrote, iclass 21, count 0 2006.162.08:28:02.65#ibcon#about to read 3, iclass 21, count 0 2006.162.08:28:02.67#ibcon#read 3, iclass 21, count 0 2006.162.08:28:02.67#ibcon#about to read 4, iclass 21, count 0 2006.162.08:28:02.67#ibcon#read 4, iclass 21, count 0 2006.162.08:28:02.67#ibcon#about to read 5, iclass 21, count 0 2006.162.08:28:02.67#ibcon#read 5, iclass 21, count 0 2006.162.08:28:02.67#ibcon#about to read 6, iclass 21, count 0 2006.162.08:28:02.67#ibcon#read 6, iclass 21, count 0 2006.162.08:28:02.67#ibcon#end of sib2, iclass 21, count 0 2006.162.08:28:02.67#ibcon#*mode == 0, iclass 21, count 0 2006.162.08:28:02.67#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.162.08:28:02.67#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.08:28:02.67#ibcon#*before write, iclass 21, count 0 2006.162.08:28:02.67#ibcon#enter sib2, iclass 21, count 0 2006.162.08:28:02.67#ibcon#flushed, iclass 21, count 0 2006.162.08:28:02.67#ibcon#about to write, iclass 21, count 0 2006.162.08:28:02.67#ibcon#wrote, iclass 21, count 0 2006.162.08:28:02.67#ibcon#about to read 3, iclass 21, count 0 2006.162.08:28:02.71#ibcon#read 3, iclass 21, count 0 2006.162.08:28:02.71#ibcon#about to read 4, iclass 21, count 0 2006.162.08:28:02.71#ibcon#read 4, iclass 21, count 0 2006.162.08:28:02.71#ibcon#about to read 5, iclass 21, count 0 2006.162.08:28:02.71#ibcon#read 5, iclass 21, count 0 2006.162.08:28:02.71#ibcon#about to read 6, iclass 21, count 0 2006.162.08:28:02.71#ibcon#read 6, iclass 21, count 0 2006.162.08:28:02.71#ibcon#end of sib2, iclass 21, count 0 2006.162.08:28:02.71#ibcon#*after write, iclass 21, count 0 2006.162.08:28:02.71#ibcon#*before return 0, iclass 21, count 0 2006.162.08:28:02.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:28:02.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.162.08:28:02.71#ibcon#about to clear, iclass 21 cls_cnt 0 2006.162.08:28:02.71#ibcon#cleared, iclass 21 cls_cnt 0 2006.162.08:28:02.71$vc4f8/vb=4,4 2006.162.08:28:02.71#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.162.08:28:02.71#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.162.08:28:02.71#ibcon#ireg 11 cls_cnt 2 2006.162.08:28:02.71#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:28:02.77#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:28:02.77#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:28:02.77#ibcon#enter wrdev, iclass 23, count 2 2006.162.08:28:02.77#ibcon#first serial, iclass 23, count 2 2006.162.08:28:02.77#ibcon#enter sib2, iclass 23, count 2 2006.162.08:28:02.77#ibcon#flushed, iclass 23, count 2 2006.162.08:28:02.77#ibcon#about to write, iclass 23, count 2 2006.162.08:28:02.77#ibcon#wrote, iclass 23, count 2 2006.162.08:28:02.77#ibcon#about to read 3, iclass 23, count 2 2006.162.08:28:02.79#ibcon#read 3, iclass 23, count 2 2006.162.08:28:02.79#ibcon#about to read 4, iclass 23, count 2 2006.162.08:28:02.79#ibcon#read 4, iclass 23, count 2 2006.162.08:28:02.79#ibcon#about to read 5, iclass 23, count 2 2006.162.08:28:02.79#ibcon#read 5, iclass 23, count 2 2006.162.08:28:02.79#ibcon#about to read 6, iclass 23, count 2 2006.162.08:28:02.79#ibcon#read 6, iclass 23, count 2 2006.162.08:28:02.79#ibcon#end of sib2, iclass 23, count 2 2006.162.08:28:02.79#ibcon#*mode == 0, iclass 23, count 2 2006.162.08:28:02.79#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.162.08:28:02.79#ibcon#[27=AT04-04\r\n] 2006.162.08:28:02.79#ibcon#*before write, iclass 23, count 2 2006.162.08:28:02.79#ibcon#enter sib2, iclass 23, count 2 2006.162.08:28:02.79#ibcon#flushed, iclass 23, count 2 2006.162.08:28:02.79#ibcon#about to write, iclass 23, count 2 2006.162.08:28:02.79#ibcon#wrote, iclass 23, count 2 2006.162.08:28:02.79#ibcon#about to read 3, iclass 23, count 2 2006.162.08:28:02.82#ibcon#read 3, iclass 23, count 2 2006.162.08:28:02.82#ibcon#about to read 4, iclass 23, count 2 2006.162.08:28:02.82#ibcon#read 4, iclass 23, count 2 2006.162.08:28:02.82#ibcon#about to read 5, iclass 23, count 2 2006.162.08:28:02.82#ibcon#read 5, iclass 23, count 2 2006.162.08:28:02.82#ibcon#about to read 6, iclass 23, count 2 2006.162.08:28:02.82#ibcon#read 6, iclass 23, count 2 2006.162.08:28:02.82#ibcon#end of sib2, iclass 23, count 2 2006.162.08:28:02.82#ibcon#*after write, iclass 23, count 2 2006.162.08:28:02.82#ibcon#*before return 0, iclass 23, count 2 2006.162.08:28:02.82#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:28:02.82#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.162.08:28:02.82#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.162.08:28:02.82#ibcon#ireg 7 cls_cnt 0 2006.162.08:28:02.82#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:28:02.94#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:28:02.94#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:28:02.94#ibcon#enter wrdev, iclass 23, count 0 2006.162.08:28:02.94#ibcon#first serial, iclass 23, count 0 2006.162.08:28:02.94#ibcon#enter sib2, iclass 23, count 0 2006.162.08:28:02.94#ibcon#flushed, iclass 23, count 0 2006.162.08:28:02.94#ibcon#about to write, iclass 23, count 0 2006.162.08:28:02.94#ibcon#wrote, iclass 23, count 0 2006.162.08:28:02.94#ibcon#about to read 3, iclass 23, count 0 2006.162.08:28:02.96#ibcon#read 3, iclass 23, count 0 2006.162.08:28:02.96#ibcon#about to read 4, iclass 23, count 0 2006.162.08:28:02.96#ibcon#read 4, iclass 23, count 0 2006.162.08:28:02.96#ibcon#about to read 5, iclass 23, count 0 2006.162.08:28:02.96#ibcon#read 5, iclass 23, count 0 2006.162.08:28:02.96#ibcon#about to read 6, iclass 23, count 0 2006.162.08:28:02.96#ibcon#read 6, iclass 23, count 0 2006.162.08:28:02.96#ibcon#end of sib2, iclass 23, count 0 2006.162.08:28:02.96#ibcon#*mode == 0, iclass 23, count 0 2006.162.08:28:02.96#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.162.08:28:02.96#ibcon#[27=USB\r\n] 2006.162.08:28:02.96#ibcon#*before write, iclass 23, count 0 2006.162.08:28:02.96#ibcon#enter sib2, iclass 23, count 0 2006.162.08:28:02.96#ibcon#flushed, iclass 23, count 0 2006.162.08:28:02.96#ibcon#about to write, iclass 23, count 0 2006.162.08:28:02.96#ibcon#wrote, iclass 23, count 0 2006.162.08:28:02.96#ibcon#about to read 3, iclass 23, count 0 2006.162.08:28:02.99#ibcon#read 3, iclass 23, count 0 2006.162.08:28:02.99#ibcon#about to read 4, iclass 23, count 0 2006.162.08:28:02.99#ibcon#read 4, iclass 23, count 0 2006.162.08:28:02.99#ibcon#about to read 5, iclass 23, count 0 2006.162.08:28:02.99#ibcon#read 5, iclass 23, count 0 2006.162.08:28:02.99#ibcon#about to read 6, iclass 23, count 0 2006.162.08:28:02.99#ibcon#read 6, iclass 23, count 0 2006.162.08:28:02.99#ibcon#end of sib2, iclass 23, count 0 2006.162.08:28:02.99#ibcon#*after write, iclass 23, count 0 2006.162.08:28:02.99#ibcon#*before return 0, iclass 23, count 0 2006.162.08:28:02.99#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:28:02.99#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.162.08:28:02.99#ibcon#about to clear, iclass 23 cls_cnt 0 2006.162.08:28:02.99#ibcon#cleared, iclass 23 cls_cnt 0 2006.162.08:28:02.99$vc4f8/vblo=5,744.99 2006.162.08:28:02.99#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.162.08:28:02.99#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.162.08:28:02.99#ibcon#ireg 17 cls_cnt 0 2006.162.08:28:02.99#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:28:02.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:28:02.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:28:02.99#ibcon#enter wrdev, iclass 25, count 0 2006.162.08:28:02.99#ibcon#first serial, iclass 25, count 0 2006.162.08:28:02.99#ibcon#enter sib2, iclass 25, count 0 2006.162.08:28:02.99#ibcon#flushed, iclass 25, count 0 2006.162.08:28:02.99#ibcon#about to write, iclass 25, count 0 2006.162.08:28:02.99#ibcon#wrote, iclass 25, count 0 2006.162.08:28:02.99#ibcon#about to read 3, iclass 25, count 0 2006.162.08:28:03.01#ibcon#read 3, iclass 25, count 0 2006.162.08:28:03.01#ibcon#about to read 4, iclass 25, count 0 2006.162.08:28:03.01#ibcon#read 4, iclass 25, count 0 2006.162.08:28:03.01#ibcon#about to read 5, iclass 25, count 0 2006.162.08:28:03.01#ibcon#read 5, iclass 25, count 0 2006.162.08:28:03.01#ibcon#about to read 6, iclass 25, count 0 2006.162.08:28:03.01#ibcon#read 6, iclass 25, count 0 2006.162.08:28:03.01#ibcon#end of sib2, iclass 25, count 0 2006.162.08:28:03.01#ibcon#*mode == 0, iclass 25, count 0 2006.162.08:28:03.01#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.162.08:28:03.01#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.08:28:03.01#ibcon#*before write, iclass 25, count 0 2006.162.08:28:03.01#ibcon#enter sib2, iclass 25, count 0 2006.162.08:28:03.01#ibcon#flushed, iclass 25, count 0 2006.162.08:28:03.01#ibcon#about to write, iclass 25, count 0 2006.162.08:28:03.01#ibcon#wrote, iclass 25, count 0 2006.162.08:28:03.01#ibcon#about to read 3, iclass 25, count 0 2006.162.08:28:03.05#ibcon#read 3, iclass 25, count 0 2006.162.08:28:03.05#ibcon#about to read 4, iclass 25, count 0 2006.162.08:28:03.05#ibcon#read 4, iclass 25, count 0 2006.162.08:28:03.05#ibcon#about to read 5, iclass 25, count 0 2006.162.08:28:03.05#ibcon#read 5, iclass 25, count 0 2006.162.08:28:03.05#ibcon#about to read 6, iclass 25, count 0 2006.162.08:28:03.05#ibcon#read 6, iclass 25, count 0 2006.162.08:28:03.05#ibcon#end of sib2, iclass 25, count 0 2006.162.08:28:03.05#ibcon#*after write, iclass 25, count 0 2006.162.08:28:03.05#ibcon#*before return 0, iclass 25, count 0 2006.162.08:28:03.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:28:03.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.162.08:28:03.05#ibcon#about to clear, iclass 25 cls_cnt 0 2006.162.08:28:03.05#ibcon#cleared, iclass 25 cls_cnt 0 2006.162.08:28:03.05$vc4f8/vb=5,4 2006.162.08:28:03.05#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.162.08:28:03.05#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.162.08:28:03.05#ibcon#ireg 11 cls_cnt 2 2006.162.08:28:03.05#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:28:03.11#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:28:03.11#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:28:03.11#ibcon#enter wrdev, iclass 27, count 2 2006.162.08:28:03.11#ibcon#first serial, iclass 27, count 2 2006.162.08:28:03.11#ibcon#enter sib2, iclass 27, count 2 2006.162.08:28:03.11#ibcon#flushed, iclass 27, count 2 2006.162.08:28:03.11#ibcon#about to write, iclass 27, count 2 2006.162.08:28:03.11#ibcon#wrote, iclass 27, count 2 2006.162.08:28:03.11#ibcon#about to read 3, iclass 27, count 2 2006.162.08:28:03.13#ibcon#read 3, iclass 27, count 2 2006.162.08:28:03.13#ibcon#about to read 4, iclass 27, count 2 2006.162.08:28:03.13#ibcon#read 4, iclass 27, count 2 2006.162.08:28:03.13#ibcon#about to read 5, iclass 27, count 2 2006.162.08:28:03.13#ibcon#read 5, iclass 27, count 2 2006.162.08:28:03.13#ibcon#about to read 6, iclass 27, count 2 2006.162.08:28:03.13#ibcon#read 6, iclass 27, count 2 2006.162.08:28:03.13#ibcon#end of sib2, iclass 27, count 2 2006.162.08:28:03.13#ibcon#*mode == 0, iclass 27, count 2 2006.162.08:28:03.13#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.162.08:28:03.13#ibcon#[27=AT05-04\r\n] 2006.162.08:28:03.13#ibcon#*before write, iclass 27, count 2 2006.162.08:28:03.13#ibcon#enter sib2, iclass 27, count 2 2006.162.08:28:03.13#ibcon#flushed, iclass 27, count 2 2006.162.08:28:03.13#ibcon#about to write, iclass 27, count 2 2006.162.08:28:03.13#ibcon#wrote, iclass 27, count 2 2006.162.08:28:03.13#ibcon#about to read 3, iclass 27, count 2 2006.162.08:28:03.16#ibcon#read 3, iclass 27, count 2 2006.162.08:28:03.16#ibcon#about to read 4, iclass 27, count 2 2006.162.08:28:03.16#ibcon#read 4, iclass 27, count 2 2006.162.08:28:03.16#ibcon#about to read 5, iclass 27, count 2 2006.162.08:28:03.16#ibcon#read 5, iclass 27, count 2 2006.162.08:28:03.16#ibcon#about to read 6, iclass 27, count 2 2006.162.08:28:03.16#ibcon#read 6, iclass 27, count 2 2006.162.08:28:03.16#ibcon#end of sib2, iclass 27, count 2 2006.162.08:28:03.16#ibcon#*after write, iclass 27, count 2 2006.162.08:28:03.16#ibcon#*before return 0, iclass 27, count 2 2006.162.08:28:03.16#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:28:03.16#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.162.08:28:03.16#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.162.08:28:03.16#ibcon#ireg 7 cls_cnt 0 2006.162.08:28:03.16#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:28:03.28#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:28:03.28#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:28:03.28#ibcon#enter wrdev, iclass 27, count 0 2006.162.08:28:03.28#ibcon#first serial, iclass 27, count 0 2006.162.08:28:03.28#ibcon#enter sib2, iclass 27, count 0 2006.162.08:28:03.28#ibcon#flushed, iclass 27, count 0 2006.162.08:28:03.28#ibcon#about to write, iclass 27, count 0 2006.162.08:28:03.28#ibcon#wrote, iclass 27, count 0 2006.162.08:28:03.28#ibcon#about to read 3, iclass 27, count 0 2006.162.08:28:03.30#ibcon#read 3, iclass 27, count 0 2006.162.08:28:03.30#ibcon#about to read 4, iclass 27, count 0 2006.162.08:28:03.30#ibcon#read 4, iclass 27, count 0 2006.162.08:28:03.30#ibcon#about to read 5, iclass 27, count 0 2006.162.08:28:03.30#ibcon#read 5, iclass 27, count 0 2006.162.08:28:03.30#ibcon#about to read 6, iclass 27, count 0 2006.162.08:28:03.30#ibcon#read 6, iclass 27, count 0 2006.162.08:28:03.30#ibcon#end of sib2, iclass 27, count 0 2006.162.08:28:03.30#ibcon#*mode == 0, iclass 27, count 0 2006.162.08:28:03.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.162.08:28:03.30#ibcon#[27=USB\r\n] 2006.162.08:28:03.30#ibcon#*before write, iclass 27, count 0 2006.162.08:28:03.30#ibcon#enter sib2, iclass 27, count 0 2006.162.08:28:03.30#ibcon#flushed, iclass 27, count 0 2006.162.08:28:03.30#ibcon#about to write, iclass 27, count 0 2006.162.08:28:03.30#ibcon#wrote, iclass 27, count 0 2006.162.08:28:03.30#ibcon#about to read 3, iclass 27, count 0 2006.162.08:28:03.33#ibcon#read 3, iclass 27, count 0 2006.162.08:28:03.33#ibcon#about to read 4, iclass 27, count 0 2006.162.08:28:03.33#ibcon#read 4, iclass 27, count 0 2006.162.08:28:03.33#ibcon#about to read 5, iclass 27, count 0 2006.162.08:28:03.33#ibcon#read 5, iclass 27, count 0 2006.162.08:28:03.33#ibcon#about to read 6, iclass 27, count 0 2006.162.08:28:03.33#ibcon#read 6, iclass 27, count 0 2006.162.08:28:03.33#ibcon#end of sib2, iclass 27, count 0 2006.162.08:28:03.33#ibcon#*after write, iclass 27, count 0 2006.162.08:28:03.33#ibcon#*before return 0, iclass 27, count 0 2006.162.08:28:03.33#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:28:03.33#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.162.08:28:03.33#ibcon#about to clear, iclass 27 cls_cnt 0 2006.162.08:28:03.33#ibcon#cleared, iclass 27 cls_cnt 0 2006.162.08:28:03.33$vc4f8/vblo=6,752.99 2006.162.08:28:03.33#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.162.08:28:03.33#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.162.08:28:03.33#ibcon#ireg 17 cls_cnt 0 2006.162.08:28:03.33#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:28:03.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:28:03.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:28:03.33#ibcon#enter wrdev, iclass 29, count 0 2006.162.08:28:03.33#ibcon#first serial, iclass 29, count 0 2006.162.08:28:03.33#ibcon#enter sib2, iclass 29, count 0 2006.162.08:28:03.33#ibcon#flushed, iclass 29, count 0 2006.162.08:28:03.33#ibcon#about to write, iclass 29, count 0 2006.162.08:28:03.33#ibcon#wrote, iclass 29, count 0 2006.162.08:28:03.33#ibcon#about to read 3, iclass 29, count 0 2006.162.08:28:03.35#ibcon#read 3, iclass 29, count 0 2006.162.08:28:03.35#ibcon#about to read 4, iclass 29, count 0 2006.162.08:28:03.35#ibcon#read 4, iclass 29, count 0 2006.162.08:28:03.35#ibcon#about to read 5, iclass 29, count 0 2006.162.08:28:03.35#ibcon#read 5, iclass 29, count 0 2006.162.08:28:03.35#ibcon#about to read 6, iclass 29, count 0 2006.162.08:28:03.35#ibcon#read 6, iclass 29, count 0 2006.162.08:28:03.35#ibcon#end of sib2, iclass 29, count 0 2006.162.08:28:03.35#ibcon#*mode == 0, iclass 29, count 0 2006.162.08:28:03.35#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.162.08:28:03.35#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.08:28:03.35#ibcon#*before write, iclass 29, count 0 2006.162.08:28:03.35#ibcon#enter sib2, iclass 29, count 0 2006.162.08:28:03.35#ibcon#flushed, iclass 29, count 0 2006.162.08:28:03.35#ibcon#about to write, iclass 29, count 0 2006.162.08:28:03.35#ibcon#wrote, iclass 29, count 0 2006.162.08:28:03.35#ibcon#about to read 3, iclass 29, count 0 2006.162.08:28:03.39#ibcon#read 3, iclass 29, count 0 2006.162.08:28:03.39#ibcon#about to read 4, iclass 29, count 0 2006.162.08:28:03.39#ibcon#read 4, iclass 29, count 0 2006.162.08:28:03.39#ibcon#about to read 5, iclass 29, count 0 2006.162.08:28:03.39#ibcon#read 5, iclass 29, count 0 2006.162.08:28:03.39#ibcon#about to read 6, iclass 29, count 0 2006.162.08:28:03.39#ibcon#read 6, iclass 29, count 0 2006.162.08:28:03.39#ibcon#end of sib2, iclass 29, count 0 2006.162.08:28:03.39#ibcon#*after write, iclass 29, count 0 2006.162.08:28:03.39#ibcon#*before return 0, iclass 29, count 0 2006.162.08:28:03.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:28:03.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.162.08:28:03.39#ibcon#about to clear, iclass 29 cls_cnt 0 2006.162.08:28:03.39#ibcon#cleared, iclass 29 cls_cnt 0 2006.162.08:28:03.39$vc4f8/vb=6,4 2006.162.08:28:03.39#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.162.08:28:03.39#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.162.08:28:03.39#ibcon#ireg 11 cls_cnt 2 2006.162.08:28:03.39#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:28:03.45#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:28:03.45#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:28:03.45#ibcon#enter wrdev, iclass 31, count 2 2006.162.08:28:03.45#ibcon#first serial, iclass 31, count 2 2006.162.08:28:03.45#ibcon#enter sib2, iclass 31, count 2 2006.162.08:28:03.45#ibcon#flushed, iclass 31, count 2 2006.162.08:28:03.45#ibcon#about to write, iclass 31, count 2 2006.162.08:28:03.45#ibcon#wrote, iclass 31, count 2 2006.162.08:28:03.45#ibcon#about to read 3, iclass 31, count 2 2006.162.08:28:03.47#ibcon#read 3, iclass 31, count 2 2006.162.08:28:03.47#ibcon#about to read 4, iclass 31, count 2 2006.162.08:28:03.47#ibcon#read 4, iclass 31, count 2 2006.162.08:28:03.47#ibcon#about to read 5, iclass 31, count 2 2006.162.08:28:03.47#ibcon#read 5, iclass 31, count 2 2006.162.08:28:03.47#ibcon#about to read 6, iclass 31, count 2 2006.162.08:28:03.47#ibcon#read 6, iclass 31, count 2 2006.162.08:28:03.47#ibcon#end of sib2, iclass 31, count 2 2006.162.08:28:03.47#ibcon#*mode == 0, iclass 31, count 2 2006.162.08:28:03.47#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.162.08:28:03.47#ibcon#[27=AT06-04\r\n] 2006.162.08:28:03.47#ibcon#*before write, iclass 31, count 2 2006.162.08:28:03.47#ibcon#enter sib2, iclass 31, count 2 2006.162.08:28:03.47#ibcon#flushed, iclass 31, count 2 2006.162.08:28:03.47#ibcon#about to write, iclass 31, count 2 2006.162.08:28:03.47#ibcon#wrote, iclass 31, count 2 2006.162.08:28:03.47#ibcon#about to read 3, iclass 31, count 2 2006.162.08:28:03.50#ibcon#read 3, iclass 31, count 2 2006.162.08:28:03.50#ibcon#about to read 4, iclass 31, count 2 2006.162.08:28:03.50#ibcon#read 4, iclass 31, count 2 2006.162.08:28:03.50#ibcon#about to read 5, iclass 31, count 2 2006.162.08:28:03.50#ibcon#read 5, iclass 31, count 2 2006.162.08:28:03.50#ibcon#about to read 6, iclass 31, count 2 2006.162.08:28:03.50#ibcon#read 6, iclass 31, count 2 2006.162.08:28:03.50#ibcon#end of sib2, iclass 31, count 2 2006.162.08:28:03.50#ibcon#*after write, iclass 31, count 2 2006.162.08:28:03.50#ibcon#*before return 0, iclass 31, count 2 2006.162.08:28:03.50#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:28:03.50#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.162.08:28:03.50#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.162.08:28:03.50#ibcon#ireg 7 cls_cnt 0 2006.162.08:28:03.50#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:28:03.62#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:28:03.62#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:28:03.62#ibcon#enter wrdev, iclass 31, count 0 2006.162.08:28:03.62#ibcon#first serial, iclass 31, count 0 2006.162.08:28:03.62#ibcon#enter sib2, iclass 31, count 0 2006.162.08:28:03.62#ibcon#flushed, iclass 31, count 0 2006.162.08:28:03.62#ibcon#about to write, iclass 31, count 0 2006.162.08:28:03.62#ibcon#wrote, iclass 31, count 0 2006.162.08:28:03.62#ibcon#about to read 3, iclass 31, count 0 2006.162.08:28:03.64#ibcon#read 3, iclass 31, count 0 2006.162.08:28:03.64#ibcon#about to read 4, iclass 31, count 0 2006.162.08:28:03.64#ibcon#read 4, iclass 31, count 0 2006.162.08:28:03.64#ibcon#about to read 5, iclass 31, count 0 2006.162.08:28:03.64#ibcon#read 5, iclass 31, count 0 2006.162.08:28:03.64#ibcon#about to read 6, iclass 31, count 0 2006.162.08:28:03.64#ibcon#read 6, iclass 31, count 0 2006.162.08:28:03.64#ibcon#end of sib2, iclass 31, count 0 2006.162.08:28:03.64#ibcon#*mode == 0, iclass 31, count 0 2006.162.08:28:03.64#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.162.08:28:03.64#ibcon#[27=USB\r\n] 2006.162.08:28:03.64#ibcon#*before write, iclass 31, count 0 2006.162.08:28:03.64#ibcon#enter sib2, iclass 31, count 0 2006.162.08:28:03.64#ibcon#flushed, iclass 31, count 0 2006.162.08:28:03.64#ibcon#about to write, iclass 31, count 0 2006.162.08:28:03.64#ibcon#wrote, iclass 31, count 0 2006.162.08:28:03.64#ibcon#about to read 3, iclass 31, count 0 2006.162.08:28:03.67#ibcon#read 3, iclass 31, count 0 2006.162.08:28:03.67#ibcon#about to read 4, iclass 31, count 0 2006.162.08:28:03.67#ibcon#read 4, iclass 31, count 0 2006.162.08:28:03.67#ibcon#about to read 5, iclass 31, count 0 2006.162.08:28:03.67#ibcon#read 5, iclass 31, count 0 2006.162.08:28:03.67#ibcon#about to read 6, iclass 31, count 0 2006.162.08:28:03.67#ibcon#read 6, iclass 31, count 0 2006.162.08:28:03.67#ibcon#end of sib2, iclass 31, count 0 2006.162.08:28:03.67#ibcon#*after write, iclass 31, count 0 2006.162.08:28:03.67#ibcon#*before return 0, iclass 31, count 0 2006.162.08:28:03.67#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:28:03.67#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.162.08:28:03.67#ibcon#about to clear, iclass 31 cls_cnt 0 2006.162.08:28:03.67#ibcon#cleared, iclass 31 cls_cnt 0 2006.162.08:28:03.67$vc4f8/vabw=wide 2006.162.08:28:03.67#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.162.08:28:03.67#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.162.08:28:03.67#ibcon#ireg 8 cls_cnt 0 2006.162.08:28:03.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:28:03.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:28:03.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:28:03.67#ibcon#enter wrdev, iclass 33, count 0 2006.162.08:28:03.67#ibcon#first serial, iclass 33, count 0 2006.162.08:28:03.67#ibcon#enter sib2, iclass 33, count 0 2006.162.08:28:03.67#ibcon#flushed, iclass 33, count 0 2006.162.08:28:03.67#ibcon#about to write, iclass 33, count 0 2006.162.08:28:03.67#ibcon#wrote, iclass 33, count 0 2006.162.08:28:03.67#ibcon#about to read 3, iclass 33, count 0 2006.162.08:28:03.69#ibcon#read 3, iclass 33, count 0 2006.162.08:28:03.69#ibcon#about to read 4, iclass 33, count 0 2006.162.08:28:03.69#ibcon#read 4, iclass 33, count 0 2006.162.08:28:03.69#ibcon#about to read 5, iclass 33, count 0 2006.162.08:28:03.69#ibcon#read 5, iclass 33, count 0 2006.162.08:28:03.69#ibcon#about to read 6, iclass 33, count 0 2006.162.08:28:03.69#ibcon#read 6, iclass 33, count 0 2006.162.08:28:03.69#ibcon#end of sib2, iclass 33, count 0 2006.162.08:28:03.69#ibcon#*mode == 0, iclass 33, count 0 2006.162.08:28:03.69#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.162.08:28:03.69#ibcon#[25=BW32\r\n] 2006.162.08:28:03.69#ibcon#*before write, iclass 33, count 0 2006.162.08:28:03.69#ibcon#enter sib2, iclass 33, count 0 2006.162.08:28:03.69#ibcon#flushed, iclass 33, count 0 2006.162.08:28:03.69#ibcon#about to write, iclass 33, count 0 2006.162.08:28:03.69#ibcon#wrote, iclass 33, count 0 2006.162.08:28:03.69#ibcon#about to read 3, iclass 33, count 0 2006.162.08:28:03.72#ibcon#read 3, iclass 33, count 0 2006.162.08:28:03.72#ibcon#about to read 4, iclass 33, count 0 2006.162.08:28:03.72#ibcon#read 4, iclass 33, count 0 2006.162.08:28:03.72#ibcon#about to read 5, iclass 33, count 0 2006.162.08:28:03.72#ibcon#read 5, iclass 33, count 0 2006.162.08:28:03.72#ibcon#about to read 6, iclass 33, count 0 2006.162.08:28:03.72#ibcon#read 6, iclass 33, count 0 2006.162.08:28:03.72#ibcon#end of sib2, iclass 33, count 0 2006.162.08:28:03.72#ibcon#*after write, iclass 33, count 0 2006.162.08:28:03.72#ibcon#*before return 0, iclass 33, count 0 2006.162.08:28:03.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:28:03.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.162.08:28:03.72#ibcon#about to clear, iclass 33 cls_cnt 0 2006.162.08:28:03.72#ibcon#cleared, iclass 33 cls_cnt 0 2006.162.08:28:03.72$vc4f8/vbbw=wide 2006.162.08:28:03.72#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.162.08:28:03.72#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.162.08:28:03.72#ibcon#ireg 8 cls_cnt 0 2006.162.08:28:03.72#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.162.08:28:03.79#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.162.08:28:03.79#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.162.08:28:03.79#ibcon#enter wrdev, iclass 35, count 0 2006.162.08:28:03.79#ibcon#first serial, iclass 35, count 0 2006.162.08:28:03.79#ibcon#enter sib2, iclass 35, count 0 2006.162.08:28:03.79#ibcon#flushed, iclass 35, count 0 2006.162.08:28:03.79#ibcon#about to write, iclass 35, count 0 2006.162.08:28:03.79#ibcon#wrote, iclass 35, count 0 2006.162.08:28:03.79#ibcon#about to read 3, iclass 35, count 0 2006.162.08:28:03.81#ibcon#read 3, iclass 35, count 0 2006.162.08:28:03.81#ibcon#about to read 4, iclass 35, count 0 2006.162.08:28:03.81#ibcon#read 4, iclass 35, count 0 2006.162.08:28:03.81#ibcon#about to read 5, iclass 35, count 0 2006.162.08:28:03.81#ibcon#read 5, iclass 35, count 0 2006.162.08:28:03.81#ibcon#about to read 6, iclass 35, count 0 2006.162.08:28:03.81#ibcon#read 6, iclass 35, count 0 2006.162.08:28:03.81#ibcon#end of sib2, iclass 35, count 0 2006.162.08:28:03.81#ibcon#*mode == 0, iclass 35, count 0 2006.162.08:28:03.81#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.162.08:28:03.81#ibcon#[27=BW32\r\n] 2006.162.08:28:03.81#ibcon#*before write, iclass 35, count 0 2006.162.08:28:03.81#ibcon#enter sib2, iclass 35, count 0 2006.162.08:28:03.81#ibcon#flushed, iclass 35, count 0 2006.162.08:28:03.81#ibcon#about to write, iclass 35, count 0 2006.162.08:28:03.81#ibcon#wrote, iclass 35, count 0 2006.162.08:28:03.81#ibcon#about to read 3, iclass 35, count 0 2006.162.08:28:03.84#ibcon#read 3, iclass 35, count 0 2006.162.08:28:03.84#ibcon#about to read 4, iclass 35, count 0 2006.162.08:28:03.84#ibcon#read 4, iclass 35, count 0 2006.162.08:28:03.84#ibcon#about to read 5, iclass 35, count 0 2006.162.08:28:03.84#ibcon#read 5, iclass 35, count 0 2006.162.08:28:03.84#ibcon#about to read 6, iclass 35, count 0 2006.162.08:28:03.84#ibcon#read 6, iclass 35, count 0 2006.162.08:28:03.84#ibcon#end of sib2, iclass 35, count 0 2006.162.08:28:03.84#ibcon#*after write, iclass 35, count 0 2006.162.08:28:03.84#ibcon#*before return 0, iclass 35, count 0 2006.162.08:28:03.84#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.162.08:28:03.84#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.162.08:28:03.84#ibcon#about to clear, iclass 35 cls_cnt 0 2006.162.08:28:03.84#ibcon#cleared, iclass 35 cls_cnt 0 2006.162.08:28:03.84$4f8m12a/ifd4f 2006.162.08:28:03.84$ifd4f/lo= 2006.162.08:28:03.84$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.08:28:03.84$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.08:28:03.84$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.08:28:03.84$ifd4f/patch= 2006.162.08:28:03.84$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.08:28:03.84$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.08:28:03.84$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.08:28:03.84$4f8m12a/"form=m,16.000,1:2 2006.162.08:28:03.84$4f8m12a/"tpicd 2006.162.08:28:03.84$4f8m12a/echo=off 2006.162.08:28:03.84$4f8m12a/xlog=off 2006.162.08:28:03.84:!2006.162.08:28:40 2006.162.08:28:15.14#trakl#Source acquired 2006.162.08:28:15.14#flagr#flagr/antenna,acquired 2006.162.08:28:40.00:preob 2006.162.08:28:40.14/onsource/TRACKING 2006.162.08:28:40.14:!2006.162.08:28:50 2006.162.08:28:50.02:data_valid=on 2006.162.08:28:50.02:midob 2006.162.08:28:51.14/onsource/TRACKING 2006.162.08:28:51.14/wx/17.78,1006.9,100 2006.162.08:28:51.30/cable/+6.5354E-03 2006.162.08:28:52.39/va/01,08,usb,yes,33,35 2006.162.08:28:52.39/va/02,07,usb,yes,34,35 2006.162.08:28:52.39/va/03,06,usb,yes,36,36 2006.162.08:28:52.39/va/04,07,usb,yes,35,37 2006.162.08:28:52.39/va/05,07,usb,yes,37,39 2006.162.08:28:52.39/va/06,06,usb,yes,36,36 2006.162.08:28:52.39/va/07,06,usb,yes,36,36 2006.162.08:28:52.39/va/08,07,usb,yes,35,34 2006.162.08:28:52.62/valo/01,532.99,yes,locked 2006.162.08:28:52.62/valo/02,572.99,yes,locked 2006.162.08:28:52.62/valo/03,672.99,yes,locked 2006.162.08:28:52.62/valo/04,832.99,yes,locked 2006.162.08:28:52.62/valo/05,652.99,yes,locked 2006.162.08:28:52.62/valo/06,772.99,yes,locked 2006.162.08:28:52.62/valo/07,832.99,yes,locked 2006.162.08:28:52.62/valo/08,852.99,yes,locked 2006.162.08:28:53.70/vb/01,04,usb,yes,29,28 2006.162.08:28:53.70/vb/02,04,usb,yes,31,33 2006.162.08:28:53.70/vb/03,04,usb,yes,27,31 2006.162.08:28:53.70/vb/04,04,usb,yes,28,29 2006.162.08:28:53.70/vb/05,04,usb,yes,27,31 2006.162.08:28:53.70/vb/06,04,usb,yes,28,31 2006.162.08:28:53.70/vb/07,04,usb,yes,30,30 2006.162.08:28:53.70/vb/08,04,usb,yes,27,31 2006.162.08:28:53.94/vblo/01,632.99,yes,locked 2006.162.08:28:53.94/vblo/02,640.99,yes,locked 2006.162.08:28:53.94/vblo/03,656.99,yes,locked 2006.162.08:28:53.94/vblo/04,712.99,yes,locked 2006.162.08:28:53.94/vblo/05,744.99,yes,locked 2006.162.08:28:53.94/vblo/06,752.99,yes,locked 2006.162.08:28:53.94/vblo/07,734.99,yes,locked 2006.162.08:28:53.94/vblo/08,744.99,yes,locked 2006.162.08:28:54.09/vabw/8 2006.162.08:28:54.24/vbbw/8 2006.162.08:28:54.34/xfe/off,on,15.2 2006.162.08:28:54.73/ifatt/23,28,28,28 2006.162.08:28:55.08/fmout-gps/S +4.52E-07 2006.162.08:28:55.15:!2006.162.08:29:50 2006.162.08:29:50.02:data_valid=off 2006.162.08:29:50.02:postob 2006.162.08:29:50.13/cable/+6.5349E-03 2006.162.08:29:50.13/wx/17.78,1006.8,100 2006.162.08:29:51.08/fmout-gps/S +4.54E-07 2006.162.08:29:51.08:scan_name=162-0830,k06162,60 2006.162.08:29:51.08:source=0743+259,074625.87,254902.1,2000.0,ccw 2006.162.08:29:51.15#flagr#flagr/antenna,new-source 2006.162.08:29:52.15:checkk5 2006.162.08:29:52.54/chk_autoobs//k5ts1/ autoobs is running! 2006.162.08:29:53.05/chk_autoobs//k5ts2/ autoobs is running! 2006.162.08:29:53.70/chk_autoobs//k5ts3/ autoobs is running! 2006.162.08:29:54.14/chk_autoobs//k5ts4/ autoobs is running! 2006.162.08:29:54.56/chk_obsdata//k5ts1/T1620828??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:29:55.23/chk_obsdata//k5ts2/T1620828??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:29:55.66/chk_obsdata//k5ts3/T1620828??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:29:56.09/chk_obsdata//k5ts4/T1620828??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:29:56.89/k5log//k5ts1_log_newline 2006.162.08:29:57.64/k5log//k5ts2_log_newline 2006.162.08:29:58.39/k5log//k5ts3_log_newline 2006.162.08:29:59.45/k5log//k5ts4_log_newline 2006.162.08:29:59.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.08:29:59.48:4f8m12a=3 2006.162.08:29:59.48$4f8m12a/echo=on 2006.162.08:29:59.48$4f8m12a/pcalon 2006.162.08:29:59.48$pcalon/"no phase cal control is implemented here 2006.162.08:29:59.48$4f8m12a/"tpicd=stop 2006.162.08:29:59.48$4f8m12a/vc4f8 2006.162.08:29:59.48$vc4f8/valo=1,532.99 2006.162.08:29:59.48#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.162.08:29:59.48#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.162.08:29:59.48#ibcon#ireg 17 cls_cnt 0 2006.162.08:29:59.48#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:29:59.48#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:29:59.48#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:29:59.48#ibcon#enter wrdev, iclass 14, count 0 2006.162.08:29:59.48#ibcon#first serial, iclass 14, count 0 2006.162.08:29:59.48#ibcon#enter sib2, iclass 14, count 0 2006.162.08:29:59.48#ibcon#flushed, iclass 14, count 0 2006.162.08:29:59.48#ibcon#about to write, iclass 14, count 0 2006.162.08:29:59.48#ibcon#wrote, iclass 14, count 0 2006.162.08:29:59.48#ibcon#about to read 3, iclass 14, count 0 2006.162.08:29:59.49#ibcon#read 3, iclass 14, count 0 2006.162.08:29:59.49#ibcon#about to read 4, iclass 14, count 0 2006.162.08:29:59.49#ibcon#read 4, iclass 14, count 0 2006.162.08:29:59.49#ibcon#about to read 5, iclass 14, count 0 2006.162.08:29:59.49#ibcon#read 5, iclass 14, count 0 2006.162.08:29:59.49#ibcon#about to read 6, iclass 14, count 0 2006.162.08:29:59.49#ibcon#read 6, iclass 14, count 0 2006.162.08:29:59.49#ibcon#end of sib2, iclass 14, count 0 2006.162.08:29:59.49#ibcon#*mode == 0, iclass 14, count 0 2006.162.08:29:59.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.08:29:59.49#ibcon#[26=FRQ=01,532.99\r\n] 2006.162.08:29:59.49#ibcon#*before write, iclass 14, count 0 2006.162.08:29:59.49#ibcon#enter sib2, iclass 14, count 0 2006.162.08:29:59.49#ibcon#flushed, iclass 14, count 0 2006.162.08:29:59.49#ibcon#about to write, iclass 14, count 0 2006.162.08:29:59.50#ibcon#wrote, iclass 14, count 0 2006.162.08:29:59.50#ibcon#about to read 3, iclass 14, count 0 2006.162.08:29:59.54#ibcon#read 3, iclass 14, count 0 2006.162.08:29:59.54#ibcon#about to read 4, iclass 14, count 0 2006.162.08:29:59.54#ibcon#read 4, iclass 14, count 0 2006.162.08:29:59.54#ibcon#about to read 5, iclass 14, count 0 2006.162.08:29:59.54#ibcon#read 5, iclass 14, count 0 2006.162.08:29:59.54#ibcon#about to read 6, iclass 14, count 0 2006.162.08:29:59.54#ibcon#read 6, iclass 14, count 0 2006.162.08:29:59.54#ibcon#end of sib2, iclass 14, count 0 2006.162.08:29:59.54#ibcon#*after write, iclass 14, count 0 2006.162.08:29:59.54#ibcon#*before return 0, iclass 14, count 0 2006.162.08:29:59.55#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:29:59.55#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:29:59.55#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.08:29:59.55#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.08:29:59.55$vc4f8/va=1,8 2006.162.08:29:59.55#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.162.08:29:59.55#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.162.08:29:59.55#ibcon#ireg 11 cls_cnt 2 2006.162.08:29:59.55#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:29:59.55#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:29:59.55#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:29:59.55#ibcon#enter wrdev, iclass 16, count 2 2006.162.08:29:59.55#ibcon#first serial, iclass 16, count 2 2006.162.08:29:59.55#ibcon#enter sib2, iclass 16, count 2 2006.162.08:29:59.55#ibcon#flushed, iclass 16, count 2 2006.162.08:29:59.55#ibcon#about to write, iclass 16, count 2 2006.162.08:29:59.55#ibcon#wrote, iclass 16, count 2 2006.162.08:29:59.55#ibcon#about to read 3, iclass 16, count 2 2006.162.08:29:59.56#ibcon#read 3, iclass 16, count 2 2006.162.08:29:59.56#ibcon#about to read 4, iclass 16, count 2 2006.162.08:29:59.56#ibcon#read 4, iclass 16, count 2 2006.162.08:29:59.56#ibcon#about to read 5, iclass 16, count 2 2006.162.08:29:59.56#ibcon#read 5, iclass 16, count 2 2006.162.08:29:59.56#ibcon#about to read 6, iclass 16, count 2 2006.162.08:29:59.56#ibcon#read 6, iclass 16, count 2 2006.162.08:29:59.56#ibcon#end of sib2, iclass 16, count 2 2006.162.08:29:59.56#ibcon#*mode == 0, iclass 16, count 2 2006.162.08:29:59.56#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.162.08:29:59.56#ibcon#[25=AT01-08\r\n] 2006.162.08:29:59.56#ibcon#*before write, iclass 16, count 2 2006.162.08:29:59.56#ibcon#enter sib2, iclass 16, count 2 2006.162.08:29:59.56#ibcon#flushed, iclass 16, count 2 2006.162.08:29:59.56#ibcon#about to write, iclass 16, count 2 2006.162.08:29:59.57#ibcon#wrote, iclass 16, count 2 2006.162.08:29:59.57#ibcon#about to read 3, iclass 16, count 2 2006.162.08:29:59.59#ibcon#read 3, iclass 16, count 2 2006.162.08:29:59.59#ibcon#about to read 4, iclass 16, count 2 2006.162.08:29:59.59#ibcon#read 4, iclass 16, count 2 2006.162.08:29:59.59#ibcon#about to read 5, iclass 16, count 2 2006.162.08:29:59.59#ibcon#read 5, iclass 16, count 2 2006.162.08:29:59.59#ibcon#about to read 6, iclass 16, count 2 2006.162.08:29:59.59#ibcon#read 6, iclass 16, count 2 2006.162.08:29:59.59#ibcon#end of sib2, iclass 16, count 2 2006.162.08:29:59.59#ibcon#*after write, iclass 16, count 2 2006.162.08:29:59.59#ibcon#*before return 0, iclass 16, count 2 2006.162.08:29:59.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:29:59.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:29:59.59#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.162.08:29:59.59#ibcon#ireg 7 cls_cnt 0 2006.162.08:29:59.60#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:29:59.72#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:29:59.72#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:29:59.72#ibcon#enter wrdev, iclass 16, count 0 2006.162.08:29:59.72#ibcon#first serial, iclass 16, count 0 2006.162.08:29:59.72#ibcon#enter sib2, iclass 16, count 0 2006.162.08:29:59.72#ibcon#flushed, iclass 16, count 0 2006.162.08:29:59.72#ibcon#about to write, iclass 16, count 0 2006.162.08:29:59.72#ibcon#wrote, iclass 16, count 0 2006.162.08:29:59.72#ibcon#about to read 3, iclass 16, count 0 2006.162.08:29:59.73#ibcon#read 3, iclass 16, count 0 2006.162.08:29:59.73#ibcon#about to read 4, iclass 16, count 0 2006.162.08:29:59.73#ibcon#read 4, iclass 16, count 0 2006.162.08:29:59.73#ibcon#about to read 5, iclass 16, count 0 2006.162.08:29:59.73#ibcon#read 5, iclass 16, count 0 2006.162.08:29:59.73#ibcon#about to read 6, iclass 16, count 0 2006.162.08:29:59.73#ibcon#read 6, iclass 16, count 0 2006.162.08:29:59.73#ibcon#end of sib2, iclass 16, count 0 2006.162.08:29:59.73#ibcon#*mode == 0, iclass 16, count 0 2006.162.08:29:59.73#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.162.08:29:59.73#ibcon#[25=USB\r\n] 2006.162.08:29:59.73#ibcon#*before write, iclass 16, count 0 2006.162.08:29:59.73#ibcon#enter sib2, iclass 16, count 0 2006.162.08:29:59.73#ibcon#flushed, iclass 16, count 0 2006.162.08:29:59.73#ibcon#about to write, iclass 16, count 0 2006.162.08:29:59.74#ibcon#wrote, iclass 16, count 0 2006.162.08:29:59.74#ibcon#about to read 3, iclass 16, count 0 2006.162.08:29:59.76#ibcon#read 3, iclass 16, count 0 2006.162.08:29:59.76#ibcon#about to read 4, iclass 16, count 0 2006.162.08:29:59.76#ibcon#read 4, iclass 16, count 0 2006.162.08:29:59.76#ibcon#about to read 5, iclass 16, count 0 2006.162.08:29:59.76#ibcon#read 5, iclass 16, count 0 2006.162.08:29:59.76#ibcon#about to read 6, iclass 16, count 0 2006.162.08:29:59.76#ibcon#read 6, iclass 16, count 0 2006.162.08:29:59.76#ibcon#end of sib2, iclass 16, count 0 2006.162.08:29:59.76#ibcon#*after write, iclass 16, count 0 2006.162.08:29:59.76#ibcon#*before return 0, iclass 16, count 0 2006.162.08:29:59.76#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:29:59.76#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:29:59.76#ibcon#about to clear, iclass 16 cls_cnt 0 2006.162.08:29:59.76#ibcon#cleared, iclass 16 cls_cnt 0 2006.162.08:29:59.77$vc4f8/valo=2,572.99 2006.162.08:29:59.77#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.162.08:29:59.77#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.162.08:29:59.77#ibcon#ireg 17 cls_cnt 0 2006.162.08:29:59.77#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:29:59.77#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:29:59.77#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:29:59.77#ibcon#enter wrdev, iclass 18, count 0 2006.162.08:29:59.77#ibcon#first serial, iclass 18, count 0 2006.162.08:29:59.77#ibcon#enter sib2, iclass 18, count 0 2006.162.08:29:59.77#ibcon#flushed, iclass 18, count 0 2006.162.08:29:59.77#ibcon#about to write, iclass 18, count 0 2006.162.08:29:59.77#ibcon#wrote, iclass 18, count 0 2006.162.08:29:59.77#ibcon#about to read 3, iclass 18, count 0 2006.162.08:29:59.78#ibcon#read 3, iclass 18, count 0 2006.162.08:29:59.78#ibcon#about to read 4, iclass 18, count 0 2006.162.08:29:59.78#ibcon#read 4, iclass 18, count 0 2006.162.08:29:59.78#ibcon#about to read 5, iclass 18, count 0 2006.162.08:29:59.78#ibcon#read 5, iclass 18, count 0 2006.162.08:29:59.78#ibcon#about to read 6, iclass 18, count 0 2006.162.08:29:59.78#ibcon#read 6, iclass 18, count 0 2006.162.08:29:59.78#ibcon#end of sib2, iclass 18, count 0 2006.162.08:29:59.78#ibcon#*mode == 0, iclass 18, count 0 2006.162.08:29:59.78#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.162.08:29:59.78#ibcon#[26=FRQ=02,572.99\r\n] 2006.162.08:29:59.78#ibcon#*before write, iclass 18, count 0 2006.162.08:29:59.78#ibcon#enter sib2, iclass 18, count 0 2006.162.08:29:59.78#ibcon#flushed, iclass 18, count 0 2006.162.08:29:59.78#ibcon#about to write, iclass 18, count 0 2006.162.08:29:59.79#ibcon#wrote, iclass 18, count 0 2006.162.08:29:59.79#ibcon#about to read 3, iclass 18, count 0 2006.162.08:29:59.83#ibcon#read 3, iclass 18, count 0 2006.162.08:29:59.83#ibcon#about to read 4, iclass 18, count 0 2006.162.08:29:59.83#ibcon#read 4, iclass 18, count 0 2006.162.08:29:59.83#ibcon#about to read 5, iclass 18, count 0 2006.162.08:29:59.83#ibcon#read 5, iclass 18, count 0 2006.162.08:29:59.83#ibcon#about to read 6, iclass 18, count 0 2006.162.08:29:59.83#ibcon#read 6, iclass 18, count 0 2006.162.08:29:59.83#ibcon#end of sib2, iclass 18, count 0 2006.162.08:29:59.83#ibcon#*after write, iclass 18, count 0 2006.162.08:29:59.83#ibcon#*before return 0, iclass 18, count 0 2006.162.08:29:59.83#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:29:59.83#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:29:59.83#ibcon#about to clear, iclass 18 cls_cnt 0 2006.162.08:29:59.83#ibcon#cleared, iclass 18 cls_cnt 0 2006.162.08:29:59.83$vc4f8/va=2,7 2006.162.08:29:59.83#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.162.08:29:59.83#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.162.08:29:59.83#ibcon#ireg 11 cls_cnt 2 2006.162.08:29:59.83#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:29:59.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:29:59.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:29:59.87#ibcon#enter wrdev, iclass 20, count 2 2006.162.08:29:59.87#ibcon#first serial, iclass 20, count 2 2006.162.08:29:59.87#ibcon#enter sib2, iclass 20, count 2 2006.162.08:29:59.87#ibcon#flushed, iclass 20, count 2 2006.162.08:29:59.87#ibcon#about to write, iclass 20, count 2 2006.162.08:29:59.88#ibcon#wrote, iclass 20, count 2 2006.162.08:29:59.88#ibcon#about to read 3, iclass 20, count 2 2006.162.08:29:59.90#ibcon#read 3, iclass 20, count 2 2006.162.08:29:59.90#ibcon#about to read 4, iclass 20, count 2 2006.162.08:29:59.90#ibcon#read 4, iclass 20, count 2 2006.162.08:29:59.90#ibcon#about to read 5, iclass 20, count 2 2006.162.08:29:59.90#ibcon#read 5, iclass 20, count 2 2006.162.08:29:59.90#ibcon#about to read 6, iclass 20, count 2 2006.162.08:29:59.90#ibcon#read 6, iclass 20, count 2 2006.162.08:29:59.90#ibcon#end of sib2, iclass 20, count 2 2006.162.08:29:59.90#ibcon#*mode == 0, iclass 20, count 2 2006.162.08:29:59.90#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.162.08:29:59.90#ibcon#[25=AT02-07\r\n] 2006.162.08:29:59.90#ibcon#*before write, iclass 20, count 2 2006.162.08:29:59.90#ibcon#enter sib2, iclass 20, count 2 2006.162.08:29:59.90#ibcon#flushed, iclass 20, count 2 2006.162.08:29:59.90#ibcon#about to write, iclass 20, count 2 2006.162.08:29:59.90#ibcon#wrote, iclass 20, count 2 2006.162.08:29:59.90#ibcon#about to read 3, iclass 20, count 2 2006.162.08:29:59.93#ibcon#read 3, iclass 20, count 2 2006.162.08:29:59.93#ibcon#about to read 4, iclass 20, count 2 2006.162.08:29:59.93#ibcon#read 4, iclass 20, count 2 2006.162.08:29:59.93#ibcon#about to read 5, iclass 20, count 2 2006.162.08:29:59.93#ibcon#read 5, iclass 20, count 2 2006.162.08:29:59.93#ibcon#about to read 6, iclass 20, count 2 2006.162.08:29:59.93#ibcon#read 6, iclass 20, count 2 2006.162.08:29:59.93#ibcon#end of sib2, iclass 20, count 2 2006.162.08:29:59.93#ibcon#*after write, iclass 20, count 2 2006.162.08:29:59.93#ibcon#*before return 0, iclass 20, count 2 2006.162.08:29:59.94#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:29:59.94#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:29:59.94#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.162.08:29:59.94#ibcon#ireg 7 cls_cnt 0 2006.162.08:29:59.94#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:30:00.05#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:30:00.05#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:30:00.05#ibcon#enter wrdev, iclass 20, count 0 2006.162.08:30:00.05#ibcon#first serial, iclass 20, count 0 2006.162.08:30:00.05#ibcon#enter sib2, iclass 20, count 0 2006.162.08:30:00.05#ibcon#flushed, iclass 20, count 0 2006.162.08:30:00.05#ibcon#about to write, iclass 20, count 0 2006.162.08:30:00.05#ibcon#wrote, iclass 20, count 0 2006.162.08:30:00.05#ibcon#about to read 3, iclass 20, count 0 2006.162.08:30:00.07#ibcon#read 3, iclass 20, count 0 2006.162.08:30:00.07#ibcon#about to read 4, iclass 20, count 0 2006.162.08:30:00.07#ibcon#read 4, iclass 20, count 0 2006.162.08:30:00.07#ibcon#about to read 5, iclass 20, count 0 2006.162.08:30:00.07#ibcon#read 5, iclass 20, count 0 2006.162.08:30:00.07#ibcon#about to read 6, iclass 20, count 0 2006.162.08:30:00.07#ibcon#read 6, iclass 20, count 0 2006.162.08:30:00.07#ibcon#end of sib2, iclass 20, count 0 2006.162.08:30:00.07#ibcon#*mode == 0, iclass 20, count 0 2006.162.08:30:00.07#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.08:30:00.07#ibcon#[25=USB\r\n] 2006.162.08:30:00.07#ibcon#*before write, iclass 20, count 0 2006.162.08:30:00.07#ibcon#enter sib2, iclass 20, count 0 2006.162.08:30:00.07#ibcon#flushed, iclass 20, count 0 2006.162.08:30:00.07#ibcon#about to write, iclass 20, count 0 2006.162.08:30:00.08#ibcon#wrote, iclass 20, count 0 2006.162.08:30:00.08#ibcon#about to read 3, iclass 20, count 0 2006.162.08:30:00.11#ibcon#read 3, iclass 20, count 0 2006.162.08:30:00.11#ibcon#about to read 4, iclass 20, count 0 2006.162.08:30:00.11#ibcon#read 4, iclass 20, count 0 2006.162.08:30:00.11#ibcon#about to read 5, iclass 20, count 0 2006.162.08:30:00.11#ibcon#read 5, iclass 20, count 0 2006.162.08:30:00.11#ibcon#about to read 6, iclass 20, count 0 2006.162.08:30:00.11#ibcon#read 6, iclass 20, count 0 2006.162.08:30:00.11#ibcon#end of sib2, iclass 20, count 0 2006.162.08:30:00.11#ibcon#*after write, iclass 20, count 0 2006.162.08:30:00.11#ibcon#*before return 0, iclass 20, count 0 2006.162.08:30:00.11#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:30:00.11#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:30:00.11#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.08:30:00.11#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.08:30:00.11$vc4f8/valo=3,672.99 2006.162.08:30:00.11#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.162.08:30:00.11#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.162.08:30:00.11#ibcon#ireg 17 cls_cnt 0 2006.162.08:30:00.11#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:30:00.11#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:30:00.11#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:30:00.11#ibcon#enter wrdev, iclass 22, count 0 2006.162.08:30:00.11#ibcon#first serial, iclass 22, count 0 2006.162.08:30:00.11#ibcon#enter sib2, iclass 22, count 0 2006.162.08:30:00.11#ibcon#flushed, iclass 22, count 0 2006.162.08:30:00.11#ibcon#about to write, iclass 22, count 0 2006.162.08:30:00.11#ibcon#wrote, iclass 22, count 0 2006.162.08:30:00.11#ibcon#about to read 3, iclass 22, count 0 2006.162.08:30:00.12#ibcon#read 3, iclass 22, count 0 2006.162.08:30:00.12#ibcon#about to read 4, iclass 22, count 0 2006.162.08:30:00.12#ibcon#read 4, iclass 22, count 0 2006.162.08:30:00.12#ibcon#about to read 5, iclass 22, count 0 2006.162.08:30:00.12#ibcon#read 5, iclass 22, count 0 2006.162.08:30:00.12#ibcon#about to read 6, iclass 22, count 0 2006.162.08:30:00.12#ibcon#read 6, iclass 22, count 0 2006.162.08:30:00.12#ibcon#end of sib2, iclass 22, count 0 2006.162.08:30:00.13#ibcon#*mode == 0, iclass 22, count 0 2006.162.08:30:00.13#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.08:30:00.13#ibcon#[26=FRQ=03,672.99\r\n] 2006.162.08:30:00.13#ibcon#*before write, iclass 22, count 0 2006.162.08:30:00.13#ibcon#enter sib2, iclass 22, count 0 2006.162.08:30:00.13#ibcon#flushed, iclass 22, count 0 2006.162.08:30:00.13#ibcon#about to write, iclass 22, count 0 2006.162.08:30:00.13#ibcon#wrote, iclass 22, count 0 2006.162.08:30:00.13#ibcon#about to read 3, iclass 22, count 0 2006.162.08:30:00.16#ibcon#read 3, iclass 22, count 0 2006.162.08:30:00.16#ibcon#about to read 4, iclass 22, count 0 2006.162.08:30:00.16#ibcon#read 4, iclass 22, count 0 2006.162.08:30:00.16#ibcon#about to read 5, iclass 22, count 0 2006.162.08:30:00.16#ibcon#read 5, iclass 22, count 0 2006.162.08:30:00.16#ibcon#about to read 6, iclass 22, count 0 2006.162.08:30:00.16#ibcon#read 6, iclass 22, count 0 2006.162.08:30:00.16#ibcon#end of sib2, iclass 22, count 0 2006.162.08:30:00.16#ibcon#*after write, iclass 22, count 0 2006.162.08:30:00.16#ibcon#*before return 0, iclass 22, count 0 2006.162.08:30:00.16#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:30:00.16#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:30:00.16#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.08:30:00.16#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.08:30:00.17$vc4f8/va=3,6 2006.162.08:30:00.17#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.162.08:30:00.17#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.162.08:30:00.17#ibcon#ireg 11 cls_cnt 2 2006.162.08:30:00.17#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:30:00.23#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:30:00.23#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:30:00.23#ibcon#enter wrdev, iclass 24, count 2 2006.162.08:30:00.23#ibcon#first serial, iclass 24, count 2 2006.162.08:30:00.23#ibcon#enter sib2, iclass 24, count 2 2006.162.08:30:00.23#ibcon#flushed, iclass 24, count 2 2006.162.08:30:00.23#ibcon#about to write, iclass 24, count 2 2006.162.08:30:00.23#ibcon#wrote, iclass 24, count 2 2006.162.08:30:00.23#ibcon#about to read 3, iclass 24, count 2 2006.162.08:30:00.24#ibcon#read 3, iclass 24, count 2 2006.162.08:30:00.24#ibcon#about to read 4, iclass 24, count 2 2006.162.08:30:00.24#ibcon#read 4, iclass 24, count 2 2006.162.08:30:00.24#ibcon#about to read 5, iclass 24, count 2 2006.162.08:30:00.24#ibcon#read 5, iclass 24, count 2 2006.162.08:30:00.24#ibcon#about to read 6, iclass 24, count 2 2006.162.08:30:00.24#ibcon#read 6, iclass 24, count 2 2006.162.08:30:00.24#ibcon#end of sib2, iclass 24, count 2 2006.162.08:30:00.24#ibcon#*mode == 0, iclass 24, count 2 2006.162.08:30:00.24#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.162.08:30:00.24#ibcon#[25=AT03-06\r\n] 2006.162.08:30:00.24#ibcon#*before write, iclass 24, count 2 2006.162.08:30:00.25#ibcon#enter sib2, iclass 24, count 2 2006.162.08:30:00.25#ibcon#flushed, iclass 24, count 2 2006.162.08:30:00.25#ibcon#about to write, iclass 24, count 2 2006.162.08:30:00.25#ibcon#wrote, iclass 24, count 2 2006.162.08:30:00.25#ibcon#about to read 3, iclass 24, count 2 2006.162.08:30:00.27#ibcon#read 3, iclass 24, count 2 2006.162.08:30:00.27#ibcon#about to read 4, iclass 24, count 2 2006.162.08:30:00.27#ibcon#read 4, iclass 24, count 2 2006.162.08:30:00.27#ibcon#about to read 5, iclass 24, count 2 2006.162.08:30:00.27#ibcon#read 5, iclass 24, count 2 2006.162.08:30:00.27#ibcon#about to read 6, iclass 24, count 2 2006.162.08:30:00.27#ibcon#read 6, iclass 24, count 2 2006.162.08:30:00.27#ibcon#end of sib2, iclass 24, count 2 2006.162.08:30:00.27#ibcon#*after write, iclass 24, count 2 2006.162.08:30:00.27#ibcon#*before return 0, iclass 24, count 2 2006.162.08:30:00.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:30:00.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:30:00.27#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.162.08:30:00.27#ibcon#ireg 7 cls_cnt 0 2006.162.08:30:00.27#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:30:00.39#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:30:00.39#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:30:00.39#ibcon#enter wrdev, iclass 24, count 0 2006.162.08:30:00.39#ibcon#first serial, iclass 24, count 0 2006.162.08:30:00.39#ibcon#enter sib2, iclass 24, count 0 2006.162.08:30:00.39#ibcon#flushed, iclass 24, count 0 2006.162.08:30:00.39#ibcon#about to write, iclass 24, count 0 2006.162.08:30:00.39#ibcon#wrote, iclass 24, count 0 2006.162.08:30:00.39#ibcon#about to read 3, iclass 24, count 0 2006.162.08:30:00.41#ibcon#read 3, iclass 24, count 0 2006.162.08:30:00.41#ibcon#about to read 4, iclass 24, count 0 2006.162.08:30:00.41#ibcon#read 4, iclass 24, count 0 2006.162.08:30:00.41#ibcon#about to read 5, iclass 24, count 0 2006.162.08:30:00.41#ibcon#read 5, iclass 24, count 0 2006.162.08:30:00.41#ibcon#about to read 6, iclass 24, count 0 2006.162.08:30:00.41#ibcon#read 6, iclass 24, count 0 2006.162.08:30:00.41#ibcon#end of sib2, iclass 24, count 0 2006.162.08:30:00.41#ibcon#*mode == 0, iclass 24, count 0 2006.162.08:30:00.41#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.08:30:00.41#ibcon#[25=USB\r\n] 2006.162.08:30:00.41#ibcon#*before write, iclass 24, count 0 2006.162.08:30:00.41#ibcon#enter sib2, iclass 24, count 0 2006.162.08:30:00.41#ibcon#flushed, iclass 24, count 0 2006.162.08:30:00.41#ibcon#about to write, iclass 24, count 0 2006.162.08:30:00.41#ibcon#wrote, iclass 24, count 0 2006.162.08:30:00.42#ibcon#about to read 3, iclass 24, count 0 2006.162.08:30:00.44#ibcon#read 3, iclass 24, count 0 2006.162.08:30:00.44#ibcon#about to read 4, iclass 24, count 0 2006.162.08:30:00.44#ibcon#read 4, iclass 24, count 0 2006.162.08:30:00.44#ibcon#about to read 5, iclass 24, count 0 2006.162.08:30:00.44#ibcon#read 5, iclass 24, count 0 2006.162.08:30:00.44#ibcon#about to read 6, iclass 24, count 0 2006.162.08:30:00.44#ibcon#read 6, iclass 24, count 0 2006.162.08:30:00.44#ibcon#end of sib2, iclass 24, count 0 2006.162.08:30:00.44#ibcon#*after write, iclass 24, count 0 2006.162.08:30:00.44#ibcon#*before return 0, iclass 24, count 0 2006.162.08:30:00.44#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:30:00.44#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:30:00.45#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.08:30:00.45#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.08:30:00.45$vc4f8/valo=4,832.99 2006.162.08:30:00.45#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.162.08:30:00.45#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.162.08:30:00.45#ibcon#ireg 17 cls_cnt 0 2006.162.08:30:00.45#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:30:00.45#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:30:00.45#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:30:00.45#ibcon#enter wrdev, iclass 26, count 0 2006.162.08:30:00.45#ibcon#first serial, iclass 26, count 0 2006.162.08:30:00.45#ibcon#enter sib2, iclass 26, count 0 2006.162.08:30:00.45#ibcon#flushed, iclass 26, count 0 2006.162.08:30:00.45#ibcon#about to write, iclass 26, count 0 2006.162.08:30:00.45#ibcon#wrote, iclass 26, count 0 2006.162.08:30:00.45#ibcon#about to read 3, iclass 26, count 0 2006.162.08:30:00.46#ibcon#read 3, iclass 26, count 0 2006.162.08:30:00.46#ibcon#about to read 4, iclass 26, count 0 2006.162.08:30:00.46#ibcon#read 4, iclass 26, count 0 2006.162.08:30:00.46#ibcon#about to read 5, iclass 26, count 0 2006.162.08:30:00.46#ibcon#read 5, iclass 26, count 0 2006.162.08:30:00.46#ibcon#about to read 6, iclass 26, count 0 2006.162.08:30:00.46#ibcon#read 6, iclass 26, count 0 2006.162.08:30:00.46#ibcon#end of sib2, iclass 26, count 0 2006.162.08:30:00.46#ibcon#*mode == 0, iclass 26, count 0 2006.162.08:30:00.46#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.162.08:30:00.46#ibcon#[26=FRQ=04,832.99\r\n] 2006.162.08:30:00.46#ibcon#*before write, iclass 26, count 0 2006.162.08:30:00.46#ibcon#enter sib2, iclass 26, count 0 2006.162.08:30:00.46#ibcon#flushed, iclass 26, count 0 2006.162.08:30:00.46#ibcon#about to write, iclass 26, count 0 2006.162.08:30:00.47#ibcon#wrote, iclass 26, count 0 2006.162.08:30:00.47#ibcon#about to read 3, iclass 26, count 0 2006.162.08:30:00.50#ibcon#read 3, iclass 26, count 0 2006.162.08:30:00.50#ibcon#about to read 4, iclass 26, count 0 2006.162.08:30:00.50#ibcon#read 4, iclass 26, count 0 2006.162.08:30:00.50#ibcon#about to read 5, iclass 26, count 0 2006.162.08:30:00.50#ibcon#read 5, iclass 26, count 0 2006.162.08:30:00.50#ibcon#about to read 6, iclass 26, count 0 2006.162.08:30:00.50#ibcon#read 6, iclass 26, count 0 2006.162.08:30:00.50#ibcon#end of sib2, iclass 26, count 0 2006.162.08:30:00.50#ibcon#*after write, iclass 26, count 0 2006.162.08:30:00.50#ibcon#*before return 0, iclass 26, count 0 2006.162.08:30:00.50#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:30:00.50#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:30:00.50#ibcon#about to clear, iclass 26 cls_cnt 0 2006.162.08:30:00.50#ibcon#cleared, iclass 26 cls_cnt 0 2006.162.08:30:00.51$vc4f8/va=4,7 2006.162.08:30:00.51#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.162.08:30:00.51#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.162.08:30:00.51#ibcon#ireg 11 cls_cnt 2 2006.162.08:30:00.51#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:30:00.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:30:00.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:30:00.55#ibcon#enter wrdev, iclass 28, count 2 2006.162.08:30:00.55#ibcon#first serial, iclass 28, count 2 2006.162.08:30:00.55#ibcon#enter sib2, iclass 28, count 2 2006.162.08:30:00.55#ibcon#flushed, iclass 28, count 2 2006.162.08:30:00.55#ibcon#about to write, iclass 28, count 2 2006.162.08:30:00.55#ibcon#wrote, iclass 28, count 2 2006.162.08:30:00.55#ibcon#about to read 3, iclass 28, count 2 2006.162.08:30:00.57#ibcon#read 3, iclass 28, count 2 2006.162.08:30:00.57#ibcon#about to read 4, iclass 28, count 2 2006.162.08:30:00.57#ibcon#read 4, iclass 28, count 2 2006.162.08:30:00.57#ibcon#about to read 5, iclass 28, count 2 2006.162.08:30:00.57#ibcon#read 5, iclass 28, count 2 2006.162.08:30:00.57#ibcon#about to read 6, iclass 28, count 2 2006.162.08:30:00.57#ibcon#read 6, iclass 28, count 2 2006.162.08:30:00.57#ibcon#end of sib2, iclass 28, count 2 2006.162.08:30:00.57#ibcon#*mode == 0, iclass 28, count 2 2006.162.08:30:00.57#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.162.08:30:00.57#ibcon#[25=AT04-07\r\n] 2006.162.08:30:00.57#ibcon#*before write, iclass 28, count 2 2006.162.08:30:00.57#ibcon#enter sib2, iclass 28, count 2 2006.162.08:30:00.57#ibcon#flushed, iclass 28, count 2 2006.162.08:30:00.57#ibcon#about to write, iclass 28, count 2 2006.162.08:30:00.58#ibcon#wrote, iclass 28, count 2 2006.162.08:30:00.58#ibcon#about to read 3, iclass 28, count 2 2006.162.08:30:00.60#ibcon#read 3, iclass 28, count 2 2006.162.08:30:00.60#ibcon#about to read 4, iclass 28, count 2 2006.162.08:30:00.60#ibcon#read 4, iclass 28, count 2 2006.162.08:30:00.60#ibcon#about to read 5, iclass 28, count 2 2006.162.08:30:00.60#ibcon#read 5, iclass 28, count 2 2006.162.08:30:00.60#ibcon#about to read 6, iclass 28, count 2 2006.162.08:30:00.60#ibcon#read 6, iclass 28, count 2 2006.162.08:30:00.60#ibcon#end of sib2, iclass 28, count 2 2006.162.08:30:00.60#ibcon#*after write, iclass 28, count 2 2006.162.08:30:00.60#ibcon#*before return 0, iclass 28, count 2 2006.162.08:30:00.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:30:00.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:30:00.60#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.162.08:30:00.60#ibcon#ireg 7 cls_cnt 0 2006.162.08:30:00.61#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:30:00.72#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:30:00.72#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:30:00.72#ibcon#enter wrdev, iclass 28, count 0 2006.162.08:30:00.72#ibcon#first serial, iclass 28, count 0 2006.162.08:30:00.72#ibcon#enter sib2, iclass 28, count 0 2006.162.08:30:00.72#ibcon#flushed, iclass 28, count 0 2006.162.08:30:00.72#ibcon#about to write, iclass 28, count 0 2006.162.08:30:00.72#ibcon#wrote, iclass 28, count 0 2006.162.08:30:00.72#ibcon#about to read 3, iclass 28, count 0 2006.162.08:30:00.74#ibcon#read 3, iclass 28, count 0 2006.162.08:30:00.74#ibcon#about to read 4, iclass 28, count 0 2006.162.08:30:00.74#ibcon#read 4, iclass 28, count 0 2006.162.08:30:00.74#ibcon#about to read 5, iclass 28, count 0 2006.162.08:30:00.74#ibcon#read 5, iclass 28, count 0 2006.162.08:30:00.74#ibcon#about to read 6, iclass 28, count 0 2006.162.08:30:00.74#ibcon#read 6, iclass 28, count 0 2006.162.08:30:00.74#ibcon#end of sib2, iclass 28, count 0 2006.162.08:30:00.74#ibcon#*mode == 0, iclass 28, count 0 2006.162.08:30:00.74#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.162.08:30:00.74#ibcon#[25=USB\r\n] 2006.162.08:30:00.74#ibcon#*before write, iclass 28, count 0 2006.162.08:30:00.74#ibcon#enter sib2, iclass 28, count 0 2006.162.08:30:00.74#ibcon#flushed, iclass 28, count 0 2006.162.08:30:00.74#ibcon#about to write, iclass 28, count 0 2006.162.08:30:00.75#ibcon#wrote, iclass 28, count 0 2006.162.08:30:00.75#ibcon#about to read 3, iclass 28, count 0 2006.162.08:30:00.77#ibcon#read 3, iclass 28, count 0 2006.162.08:30:00.77#ibcon#about to read 4, iclass 28, count 0 2006.162.08:30:00.77#ibcon#read 4, iclass 28, count 0 2006.162.08:30:00.77#ibcon#about to read 5, iclass 28, count 0 2006.162.08:30:00.77#ibcon#read 5, iclass 28, count 0 2006.162.08:30:00.77#ibcon#about to read 6, iclass 28, count 0 2006.162.08:30:00.77#ibcon#read 6, iclass 28, count 0 2006.162.08:30:00.77#ibcon#end of sib2, iclass 28, count 0 2006.162.08:30:00.77#ibcon#*after write, iclass 28, count 0 2006.162.08:30:00.77#ibcon#*before return 0, iclass 28, count 0 2006.162.08:30:00.77#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:30:00.77#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:30:00.77#ibcon#about to clear, iclass 28 cls_cnt 0 2006.162.08:30:00.77#ibcon#cleared, iclass 28 cls_cnt 0 2006.162.08:30:00.78$vc4f8/valo=5,652.99 2006.162.08:30:00.78#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.162.08:30:00.78#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.162.08:30:00.78#ibcon#ireg 17 cls_cnt 0 2006.162.08:30:00.78#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:30:00.78#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:30:00.78#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:30:00.78#ibcon#enter wrdev, iclass 30, count 0 2006.162.08:30:00.78#ibcon#first serial, iclass 30, count 0 2006.162.08:30:00.78#ibcon#enter sib2, iclass 30, count 0 2006.162.08:30:00.78#ibcon#flushed, iclass 30, count 0 2006.162.08:30:00.78#ibcon#about to write, iclass 30, count 0 2006.162.08:30:00.78#ibcon#wrote, iclass 30, count 0 2006.162.08:30:00.78#ibcon#about to read 3, iclass 30, count 0 2006.162.08:30:00.79#ibcon#read 3, iclass 30, count 0 2006.162.08:30:00.79#ibcon#about to read 4, iclass 30, count 0 2006.162.08:30:00.79#ibcon#read 4, iclass 30, count 0 2006.162.08:30:00.79#ibcon#about to read 5, iclass 30, count 0 2006.162.08:30:00.79#ibcon#read 5, iclass 30, count 0 2006.162.08:30:00.79#ibcon#about to read 6, iclass 30, count 0 2006.162.08:30:00.79#ibcon#read 6, iclass 30, count 0 2006.162.08:30:00.79#ibcon#end of sib2, iclass 30, count 0 2006.162.08:30:00.79#ibcon#*mode == 0, iclass 30, count 0 2006.162.08:30:00.79#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.162.08:30:00.79#ibcon#[26=FRQ=05,652.99\r\n] 2006.162.08:30:00.79#ibcon#*before write, iclass 30, count 0 2006.162.08:30:00.79#ibcon#enter sib2, iclass 30, count 0 2006.162.08:30:00.79#ibcon#flushed, iclass 30, count 0 2006.162.08:30:00.79#ibcon#about to write, iclass 30, count 0 2006.162.08:30:00.80#ibcon#wrote, iclass 30, count 0 2006.162.08:30:00.80#ibcon#about to read 3, iclass 30, count 0 2006.162.08:30:00.83#ibcon#read 3, iclass 30, count 0 2006.162.08:30:00.83#ibcon#about to read 4, iclass 30, count 0 2006.162.08:30:00.83#ibcon#read 4, iclass 30, count 0 2006.162.08:30:00.83#ibcon#about to read 5, iclass 30, count 0 2006.162.08:30:00.83#ibcon#read 5, iclass 30, count 0 2006.162.08:30:00.83#ibcon#about to read 6, iclass 30, count 0 2006.162.08:30:00.83#ibcon#read 6, iclass 30, count 0 2006.162.08:30:00.83#ibcon#end of sib2, iclass 30, count 0 2006.162.08:30:00.83#ibcon#*after write, iclass 30, count 0 2006.162.08:30:00.83#ibcon#*before return 0, iclass 30, count 0 2006.162.08:30:00.83#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:30:00.83#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:30:00.83#ibcon#about to clear, iclass 30 cls_cnt 0 2006.162.08:30:00.83#ibcon#cleared, iclass 30 cls_cnt 0 2006.162.08:30:00.84$vc4f8/va=5,7 2006.162.08:30:00.84#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.162.08:30:00.84#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.162.08:30:00.84#ibcon#ireg 11 cls_cnt 2 2006.162.08:30:00.84#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.162.08:30:00.88#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.162.08:30:00.88#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.162.08:30:00.88#ibcon#enter wrdev, iclass 32, count 2 2006.162.08:30:00.88#ibcon#first serial, iclass 32, count 2 2006.162.08:30:00.88#ibcon#enter sib2, iclass 32, count 2 2006.162.08:30:00.88#ibcon#flushed, iclass 32, count 2 2006.162.08:30:00.88#ibcon#about to write, iclass 32, count 2 2006.162.08:30:00.88#ibcon#wrote, iclass 32, count 2 2006.162.08:30:00.88#ibcon#about to read 3, iclass 32, count 2 2006.162.08:30:00.90#ibcon#read 3, iclass 32, count 2 2006.162.08:30:00.90#ibcon#about to read 4, iclass 32, count 2 2006.162.08:30:00.90#ibcon#read 4, iclass 32, count 2 2006.162.08:30:00.90#ibcon#about to read 5, iclass 32, count 2 2006.162.08:30:00.90#ibcon#read 5, iclass 32, count 2 2006.162.08:30:00.90#ibcon#about to read 6, iclass 32, count 2 2006.162.08:30:00.90#ibcon#read 6, iclass 32, count 2 2006.162.08:30:00.90#ibcon#end of sib2, iclass 32, count 2 2006.162.08:30:00.90#ibcon#*mode == 0, iclass 32, count 2 2006.162.08:30:00.90#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.162.08:30:00.90#ibcon#[25=AT05-07\r\n] 2006.162.08:30:00.90#ibcon#*before write, iclass 32, count 2 2006.162.08:30:00.90#ibcon#enter sib2, iclass 32, count 2 2006.162.08:30:00.90#ibcon#flushed, iclass 32, count 2 2006.162.08:30:00.90#ibcon#about to write, iclass 32, count 2 2006.162.08:30:00.91#ibcon#wrote, iclass 32, count 2 2006.162.08:30:00.91#ibcon#about to read 3, iclass 32, count 2 2006.162.08:30:00.94#ibcon#read 3, iclass 32, count 2 2006.162.08:30:00.94#ibcon#about to read 4, iclass 32, count 2 2006.162.08:30:00.94#ibcon#read 4, iclass 32, count 2 2006.162.08:30:00.94#ibcon#about to read 5, iclass 32, count 2 2006.162.08:30:00.94#ibcon#read 5, iclass 32, count 2 2006.162.08:30:00.94#ibcon#about to read 6, iclass 32, count 2 2006.162.08:30:00.94#ibcon#read 6, iclass 32, count 2 2006.162.08:30:00.94#ibcon#end of sib2, iclass 32, count 2 2006.162.08:30:00.94#ibcon#*after write, iclass 32, count 2 2006.162.08:30:00.94#ibcon#*before return 0, iclass 32, count 2 2006.162.08:30:00.94#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.162.08:30:00.94#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.162.08:30:00.94#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.162.08:30:00.94#ibcon#ireg 7 cls_cnt 0 2006.162.08:30:00.94#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.162.08:30:01.05#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.162.08:30:01.05#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.162.08:30:01.05#ibcon#enter wrdev, iclass 32, count 0 2006.162.08:30:01.05#ibcon#first serial, iclass 32, count 0 2006.162.08:30:01.05#ibcon#enter sib2, iclass 32, count 0 2006.162.08:30:01.05#ibcon#flushed, iclass 32, count 0 2006.162.08:30:01.05#ibcon#about to write, iclass 32, count 0 2006.162.08:30:01.05#ibcon#wrote, iclass 32, count 0 2006.162.08:30:01.05#ibcon#about to read 3, iclass 32, count 0 2006.162.08:30:01.07#ibcon#read 3, iclass 32, count 0 2006.162.08:30:01.07#ibcon#about to read 4, iclass 32, count 0 2006.162.08:30:01.07#ibcon#read 4, iclass 32, count 0 2006.162.08:30:01.07#ibcon#about to read 5, iclass 32, count 0 2006.162.08:30:01.07#ibcon#read 5, iclass 32, count 0 2006.162.08:30:01.07#ibcon#about to read 6, iclass 32, count 0 2006.162.08:30:01.07#ibcon#read 6, iclass 32, count 0 2006.162.08:30:01.07#ibcon#end of sib2, iclass 32, count 0 2006.162.08:30:01.07#ibcon#*mode == 0, iclass 32, count 0 2006.162.08:30:01.07#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.162.08:30:01.07#ibcon#[25=USB\r\n] 2006.162.08:30:01.07#ibcon#*before write, iclass 32, count 0 2006.162.08:30:01.07#ibcon#enter sib2, iclass 32, count 0 2006.162.08:30:01.07#ibcon#flushed, iclass 32, count 0 2006.162.08:30:01.07#ibcon#about to write, iclass 32, count 0 2006.162.08:30:01.08#ibcon#wrote, iclass 32, count 0 2006.162.08:30:01.08#ibcon#about to read 3, iclass 32, count 0 2006.162.08:30:01.10#ibcon#read 3, iclass 32, count 0 2006.162.08:30:01.10#ibcon#about to read 4, iclass 32, count 0 2006.162.08:30:01.10#ibcon#read 4, iclass 32, count 0 2006.162.08:30:01.10#ibcon#about to read 5, iclass 32, count 0 2006.162.08:30:01.10#ibcon#read 5, iclass 32, count 0 2006.162.08:30:01.10#ibcon#about to read 6, iclass 32, count 0 2006.162.08:30:01.10#ibcon#read 6, iclass 32, count 0 2006.162.08:30:01.10#ibcon#end of sib2, iclass 32, count 0 2006.162.08:30:01.10#ibcon#*after write, iclass 32, count 0 2006.162.08:30:01.10#ibcon#*before return 0, iclass 32, count 0 2006.162.08:30:01.10#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.162.08:30:01.10#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.162.08:30:01.10#ibcon#about to clear, iclass 32 cls_cnt 0 2006.162.08:30:01.10#ibcon#cleared, iclass 32 cls_cnt 0 2006.162.08:30:01.11$vc4f8/valo=6,772.99 2006.162.08:30:01.11#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.162.08:30:01.11#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.162.08:30:01.11#ibcon#ireg 17 cls_cnt 0 2006.162.08:30:01.11#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:30:01.11#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:30:01.11#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:30:01.11#ibcon#enter wrdev, iclass 34, count 0 2006.162.08:30:01.11#ibcon#first serial, iclass 34, count 0 2006.162.08:30:01.11#ibcon#enter sib2, iclass 34, count 0 2006.162.08:30:01.11#ibcon#flushed, iclass 34, count 0 2006.162.08:30:01.11#ibcon#about to write, iclass 34, count 0 2006.162.08:30:01.11#ibcon#wrote, iclass 34, count 0 2006.162.08:30:01.11#ibcon#about to read 3, iclass 34, count 0 2006.162.08:30:01.12#ibcon#read 3, iclass 34, count 0 2006.162.08:30:01.12#ibcon#about to read 4, iclass 34, count 0 2006.162.08:30:01.12#ibcon#read 4, iclass 34, count 0 2006.162.08:30:01.12#ibcon#about to read 5, iclass 34, count 0 2006.162.08:30:01.12#ibcon#read 5, iclass 34, count 0 2006.162.08:30:01.12#ibcon#about to read 6, iclass 34, count 0 2006.162.08:30:01.12#ibcon#read 6, iclass 34, count 0 2006.162.08:30:01.12#ibcon#end of sib2, iclass 34, count 0 2006.162.08:30:01.12#ibcon#*mode == 0, iclass 34, count 0 2006.162.08:30:01.12#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.162.08:30:01.12#ibcon#[26=FRQ=06,772.99\r\n] 2006.162.08:30:01.12#ibcon#*before write, iclass 34, count 0 2006.162.08:30:01.12#ibcon#enter sib2, iclass 34, count 0 2006.162.08:30:01.12#ibcon#flushed, iclass 34, count 0 2006.162.08:30:01.12#ibcon#about to write, iclass 34, count 0 2006.162.08:30:01.13#ibcon#wrote, iclass 34, count 0 2006.162.08:30:01.13#ibcon#about to read 3, iclass 34, count 0 2006.162.08:30:01.16#ibcon#read 3, iclass 34, count 0 2006.162.08:30:01.16#ibcon#about to read 4, iclass 34, count 0 2006.162.08:30:01.16#ibcon#read 4, iclass 34, count 0 2006.162.08:30:01.16#ibcon#about to read 5, iclass 34, count 0 2006.162.08:30:01.16#ibcon#read 5, iclass 34, count 0 2006.162.08:30:01.16#ibcon#about to read 6, iclass 34, count 0 2006.162.08:30:01.16#ibcon#read 6, iclass 34, count 0 2006.162.08:30:01.16#ibcon#end of sib2, iclass 34, count 0 2006.162.08:30:01.16#ibcon#*after write, iclass 34, count 0 2006.162.08:30:01.16#ibcon#*before return 0, iclass 34, count 0 2006.162.08:30:01.16#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:30:01.17#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:30:01.17#ibcon#about to clear, iclass 34 cls_cnt 0 2006.162.08:30:01.17#ibcon#cleared, iclass 34 cls_cnt 0 2006.162.08:30:01.17$vc4f8/va=6,6 2006.162.08:30:01.17#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.162.08:30:01.17#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.162.08:30:01.17#ibcon#ireg 11 cls_cnt 2 2006.162.08:30:01.17#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:30:01.21#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:30:01.21#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:30:01.21#ibcon#enter wrdev, iclass 36, count 2 2006.162.08:30:01.21#ibcon#first serial, iclass 36, count 2 2006.162.08:30:01.21#ibcon#enter sib2, iclass 36, count 2 2006.162.08:30:01.21#ibcon#flushed, iclass 36, count 2 2006.162.08:30:01.21#ibcon#about to write, iclass 36, count 2 2006.162.08:30:01.21#ibcon#wrote, iclass 36, count 2 2006.162.08:30:01.21#ibcon#about to read 3, iclass 36, count 2 2006.162.08:30:01.23#ibcon#read 3, iclass 36, count 2 2006.162.08:30:01.23#ibcon#about to read 4, iclass 36, count 2 2006.162.08:30:01.23#ibcon#read 4, iclass 36, count 2 2006.162.08:30:01.23#ibcon#about to read 5, iclass 36, count 2 2006.162.08:30:01.23#ibcon#read 5, iclass 36, count 2 2006.162.08:30:01.23#ibcon#about to read 6, iclass 36, count 2 2006.162.08:30:01.23#ibcon#read 6, iclass 36, count 2 2006.162.08:30:01.23#ibcon#end of sib2, iclass 36, count 2 2006.162.08:30:01.23#ibcon#*mode == 0, iclass 36, count 2 2006.162.08:30:01.23#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.162.08:30:01.23#ibcon#[25=AT06-06\r\n] 2006.162.08:30:01.23#ibcon#*before write, iclass 36, count 2 2006.162.08:30:01.23#ibcon#enter sib2, iclass 36, count 2 2006.162.08:30:01.23#ibcon#flushed, iclass 36, count 2 2006.162.08:30:01.23#ibcon#about to write, iclass 36, count 2 2006.162.08:30:01.24#ibcon#wrote, iclass 36, count 2 2006.162.08:30:01.24#ibcon#about to read 3, iclass 36, count 2 2006.162.08:30:01.26#ibcon#read 3, iclass 36, count 2 2006.162.08:30:01.26#ibcon#about to read 4, iclass 36, count 2 2006.162.08:30:01.26#ibcon#read 4, iclass 36, count 2 2006.162.08:30:01.26#ibcon#about to read 5, iclass 36, count 2 2006.162.08:30:01.26#ibcon#read 5, iclass 36, count 2 2006.162.08:30:01.26#ibcon#about to read 6, iclass 36, count 2 2006.162.08:30:01.26#ibcon#read 6, iclass 36, count 2 2006.162.08:30:01.26#ibcon#end of sib2, iclass 36, count 2 2006.162.08:30:01.26#ibcon#*after write, iclass 36, count 2 2006.162.08:30:01.26#ibcon#*before return 0, iclass 36, count 2 2006.162.08:30:01.26#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:30:01.27#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.162.08:30:01.27#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.162.08:30:01.27#ibcon#ireg 7 cls_cnt 0 2006.162.08:30:01.27#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:30:01.38#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:30:01.38#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:30:01.38#ibcon#enter wrdev, iclass 36, count 0 2006.162.08:30:01.38#ibcon#first serial, iclass 36, count 0 2006.162.08:30:01.38#ibcon#enter sib2, iclass 36, count 0 2006.162.08:30:01.38#ibcon#flushed, iclass 36, count 0 2006.162.08:30:01.38#ibcon#about to write, iclass 36, count 0 2006.162.08:30:01.38#ibcon#wrote, iclass 36, count 0 2006.162.08:30:01.38#ibcon#about to read 3, iclass 36, count 0 2006.162.08:30:01.40#ibcon#read 3, iclass 36, count 0 2006.162.08:30:01.40#ibcon#about to read 4, iclass 36, count 0 2006.162.08:30:01.40#ibcon#read 4, iclass 36, count 0 2006.162.08:30:01.40#ibcon#about to read 5, iclass 36, count 0 2006.162.08:30:01.40#ibcon#read 5, iclass 36, count 0 2006.162.08:30:01.40#ibcon#about to read 6, iclass 36, count 0 2006.162.08:30:01.40#ibcon#read 6, iclass 36, count 0 2006.162.08:30:01.40#ibcon#end of sib2, iclass 36, count 0 2006.162.08:30:01.40#ibcon#*mode == 0, iclass 36, count 0 2006.162.08:30:01.40#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.162.08:30:01.40#ibcon#[25=USB\r\n] 2006.162.08:30:01.40#ibcon#*before write, iclass 36, count 0 2006.162.08:30:01.40#ibcon#enter sib2, iclass 36, count 0 2006.162.08:30:01.40#ibcon#flushed, iclass 36, count 0 2006.162.08:30:01.40#ibcon#about to write, iclass 36, count 0 2006.162.08:30:01.41#ibcon#wrote, iclass 36, count 0 2006.162.08:30:01.41#ibcon#about to read 3, iclass 36, count 0 2006.162.08:30:01.43#ibcon#read 3, iclass 36, count 0 2006.162.08:30:01.43#ibcon#about to read 4, iclass 36, count 0 2006.162.08:30:01.43#ibcon#read 4, iclass 36, count 0 2006.162.08:30:01.43#ibcon#about to read 5, iclass 36, count 0 2006.162.08:30:01.43#ibcon#read 5, iclass 36, count 0 2006.162.08:30:01.43#ibcon#about to read 6, iclass 36, count 0 2006.162.08:30:01.43#ibcon#read 6, iclass 36, count 0 2006.162.08:30:01.43#ibcon#end of sib2, iclass 36, count 0 2006.162.08:30:01.43#ibcon#*after write, iclass 36, count 0 2006.162.08:30:01.43#ibcon#*before return 0, iclass 36, count 0 2006.162.08:30:01.43#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:30:01.43#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.162.08:30:01.43#ibcon#about to clear, iclass 36 cls_cnt 0 2006.162.08:30:01.43#ibcon#cleared, iclass 36 cls_cnt 0 2006.162.08:30:01.44$vc4f8/valo=7,832.99 2006.162.08:30:01.44#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.162.08:30:01.44#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.162.08:30:01.44#ibcon#ireg 17 cls_cnt 0 2006.162.08:30:01.44#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.162.08:30:01.44#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.162.08:30:01.44#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.162.08:30:01.44#ibcon#enter wrdev, iclass 38, count 0 2006.162.08:30:01.44#ibcon#first serial, iclass 38, count 0 2006.162.08:30:01.44#ibcon#enter sib2, iclass 38, count 0 2006.162.08:30:01.44#ibcon#flushed, iclass 38, count 0 2006.162.08:30:01.44#ibcon#about to write, iclass 38, count 0 2006.162.08:30:01.44#ibcon#wrote, iclass 38, count 0 2006.162.08:30:01.44#ibcon#about to read 3, iclass 38, count 0 2006.162.08:30:01.45#ibcon#read 3, iclass 38, count 0 2006.162.08:30:01.45#ibcon#about to read 4, iclass 38, count 0 2006.162.08:30:01.45#ibcon#read 4, iclass 38, count 0 2006.162.08:30:01.45#ibcon#about to read 5, iclass 38, count 0 2006.162.08:30:01.45#ibcon#read 5, iclass 38, count 0 2006.162.08:30:01.45#ibcon#about to read 6, iclass 38, count 0 2006.162.08:30:01.45#ibcon#read 6, iclass 38, count 0 2006.162.08:30:01.45#ibcon#end of sib2, iclass 38, count 0 2006.162.08:30:01.45#ibcon#*mode == 0, iclass 38, count 0 2006.162.08:30:01.45#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.162.08:30:01.45#ibcon#[26=FRQ=07,832.99\r\n] 2006.162.08:30:01.45#ibcon#*before write, iclass 38, count 0 2006.162.08:30:01.45#ibcon#enter sib2, iclass 38, count 0 2006.162.08:30:01.45#ibcon#flushed, iclass 38, count 0 2006.162.08:30:01.45#ibcon#about to write, iclass 38, count 0 2006.162.08:30:01.45#ibcon#wrote, iclass 38, count 0 2006.162.08:30:01.46#ibcon#about to read 3, iclass 38, count 0 2006.162.08:30:01.49#ibcon#read 3, iclass 38, count 0 2006.162.08:30:01.49#ibcon#about to read 4, iclass 38, count 0 2006.162.08:30:01.49#ibcon#read 4, iclass 38, count 0 2006.162.08:30:01.49#ibcon#about to read 5, iclass 38, count 0 2006.162.08:30:01.49#ibcon#read 5, iclass 38, count 0 2006.162.08:30:01.49#ibcon#about to read 6, iclass 38, count 0 2006.162.08:30:01.49#ibcon#read 6, iclass 38, count 0 2006.162.08:30:01.49#ibcon#end of sib2, iclass 38, count 0 2006.162.08:30:01.49#ibcon#*after write, iclass 38, count 0 2006.162.08:30:01.49#ibcon#*before return 0, iclass 38, count 0 2006.162.08:30:01.49#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.162.08:30:01.49#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.162.08:30:01.49#ibcon#about to clear, iclass 38 cls_cnt 0 2006.162.08:30:01.49#ibcon#cleared, iclass 38 cls_cnt 0 2006.162.08:30:01.50$vc4f8/va=7,6 2006.162.08:30:01.50#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.162.08:30:01.50#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.162.08:30:01.50#ibcon#ireg 11 cls_cnt 2 2006.162.08:30:01.50#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.162.08:30:01.54#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.162.08:30:01.54#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.162.08:30:01.54#ibcon#enter wrdev, iclass 40, count 2 2006.162.08:30:01.54#ibcon#first serial, iclass 40, count 2 2006.162.08:30:01.54#ibcon#enter sib2, iclass 40, count 2 2006.162.08:30:01.54#ibcon#flushed, iclass 40, count 2 2006.162.08:30:01.54#ibcon#about to write, iclass 40, count 2 2006.162.08:30:01.54#ibcon#wrote, iclass 40, count 2 2006.162.08:30:01.54#ibcon#about to read 3, iclass 40, count 2 2006.162.08:30:01.56#ibcon#read 3, iclass 40, count 2 2006.162.08:30:01.56#ibcon#about to read 4, iclass 40, count 2 2006.162.08:30:01.56#ibcon#read 4, iclass 40, count 2 2006.162.08:30:01.56#ibcon#about to read 5, iclass 40, count 2 2006.162.08:30:01.56#ibcon#read 5, iclass 40, count 2 2006.162.08:30:01.56#ibcon#about to read 6, iclass 40, count 2 2006.162.08:30:01.56#ibcon#read 6, iclass 40, count 2 2006.162.08:30:01.56#ibcon#end of sib2, iclass 40, count 2 2006.162.08:30:01.56#ibcon#*mode == 0, iclass 40, count 2 2006.162.08:30:01.56#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.162.08:30:01.56#ibcon#[25=AT07-06\r\n] 2006.162.08:30:01.56#ibcon#*before write, iclass 40, count 2 2006.162.08:30:01.56#ibcon#enter sib2, iclass 40, count 2 2006.162.08:30:01.56#ibcon#flushed, iclass 40, count 2 2006.162.08:30:01.56#ibcon#about to write, iclass 40, count 2 2006.162.08:30:01.56#ibcon#wrote, iclass 40, count 2 2006.162.08:30:01.57#ibcon#about to read 3, iclass 40, count 2 2006.162.08:30:01.59#ibcon#read 3, iclass 40, count 2 2006.162.08:30:01.59#ibcon#about to read 4, iclass 40, count 2 2006.162.08:30:01.59#ibcon#read 4, iclass 40, count 2 2006.162.08:30:01.59#ibcon#about to read 5, iclass 40, count 2 2006.162.08:30:01.59#ibcon#read 5, iclass 40, count 2 2006.162.08:30:01.59#ibcon#about to read 6, iclass 40, count 2 2006.162.08:30:01.59#ibcon#read 6, iclass 40, count 2 2006.162.08:30:01.59#ibcon#end of sib2, iclass 40, count 2 2006.162.08:30:01.59#ibcon#*after write, iclass 40, count 2 2006.162.08:30:01.59#ibcon#*before return 0, iclass 40, count 2 2006.162.08:30:01.59#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.162.08:30:01.59#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.162.08:30:01.59#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.162.08:30:01.59#ibcon#ireg 7 cls_cnt 0 2006.162.08:30:01.59#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.162.08:30:01.71#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.162.08:30:01.71#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.162.08:30:01.71#ibcon#enter wrdev, iclass 40, count 0 2006.162.08:30:01.71#ibcon#first serial, iclass 40, count 0 2006.162.08:30:01.71#ibcon#enter sib2, iclass 40, count 0 2006.162.08:30:01.71#ibcon#flushed, iclass 40, count 0 2006.162.08:30:01.71#ibcon#about to write, iclass 40, count 0 2006.162.08:30:01.71#ibcon#wrote, iclass 40, count 0 2006.162.08:30:01.71#ibcon#about to read 3, iclass 40, count 0 2006.162.08:30:01.73#ibcon#read 3, iclass 40, count 0 2006.162.08:30:01.73#ibcon#about to read 4, iclass 40, count 0 2006.162.08:30:01.73#ibcon#read 4, iclass 40, count 0 2006.162.08:30:01.73#ibcon#about to read 5, iclass 40, count 0 2006.162.08:30:01.73#ibcon#read 5, iclass 40, count 0 2006.162.08:30:01.73#ibcon#about to read 6, iclass 40, count 0 2006.162.08:30:01.73#ibcon#read 6, iclass 40, count 0 2006.162.08:30:01.73#ibcon#end of sib2, iclass 40, count 0 2006.162.08:30:01.73#ibcon#*mode == 0, iclass 40, count 0 2006.162.08:30:01.73#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.162.08:30:01.73#ibcon#[25=USB\r\n] 2006.162.08:30:01.73#ibcon#*before write, iclass 40, count 0 2006.162.08:30:01.73#ibcon#enter sib2, iclass 40, count 0 2006.162.08:30:01.73#ibcon#flushed, iclass 40, count 0 2006.162.08:30:01.73#ibcon#about to write, iclass 40, count 0 2006.162.08:30:01.74#ibcon#wrote, iclass 40, count 0 2006.162.08:30:01.74#ibcon#about to read 3, iclass 40, count 0 2006.162.08:30:01.76#ibcon#read 3, iclass 40, count 0 2006.162.08:30:01.76#ibcon#about to read 4, iclass 40, count 0 2006.162.08:30:01.76#ibcon#read 4, iclass 40, count 0 2006.162.08:30:01.76#ibcon#about to read 5, iclass 40, count 0 2006.162.08:30:01.76#ibcon#read 5, iclass 40, count 0 2006.162.08:30:01.76#ibcon#about to read 6, iclass 40, count 0 2006.162.08:30:01.76#ibcon#read 6, iclass 40, count 0 2006.162.08:30:01.76#ibcon#end of sib2, iclass 40, count 0 2006.162.08:30:01.76#ibcon#*after write, iclass 40, count 0 2006.162.08:30:01.76#ibcon#*before return 0, iclass 40, count 0 2006.162.08:30:01.76#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.162.08:30:01.76#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.162.08:30:01.76#ibcon#about to clear, iclass 40 cls_cnt 0 2006.162.08:30:01.76#ibcon#cleared, iclass 40 cls_cnt 0 2006.162.08:30:01.77$vc4f8/valo=8,852.99 2006.162.08:30:01.77#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.162.08:30:01.77#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.162.08:30:01.77#ibcon#ireg 17 cls_cnt 0 2006.162.08:30:01.77#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:30:01.77#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:30:01.77#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:30:01.77#ibcon#enter wrdev, iclass 4, count 0 2006.162.08:30:01.77#ibcon#first serial, iclass 4, count 0 2006.162.08:30:01.77#ibcon#enter sib2, iclass 4, count 0 2006.162.08:30:01.77#ibcon#flushed, iclass 4, count 0 2006.162.08:30:01.77#ibcon#about to write, iclass 4, count 0 2006.162.08:30:01.77#ibcon#wrote, iclass 4, count 0 2006.162.08:30:01.77#ibcon#about to read 3, iclass 4, count 0 2006.162.08:30:01.78#ibcon#read 3, iclass 4, count 0 2006.162.08:30:01.78#ibcon#about to read 4, iclass 4, count 0 2006.162.08:30:01.78#ibcon#read 4, iclass 4, count 0 2006.162.08:30:01.78#ibcon#about to read 5, iclass 4, count 0 2006.162.08:30:01.78#ibcon#read 5, iclass 4, count 0 2006.162.08:30:01.78#ibcon#about to read 6, iclass 4, count 0 2006.162.08:30:01.78#ibcon#read 6, iclass 4, count 0 2006.162.08:30:01.78#ibcon#end of sib2, iclass 4, count 0 2006.162.08:30:01.78#ibcon#*mode == 0, iclass 4, count 0 2006.162.08:30:01.78#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.162.08:30:01.78#ibcon#[26=FRQ=08,852.99\r\n] 2006.162.08:30:01.78#ibcon#*before write, iclass 4, count 0 2006.162.08:30:01.78#ibcon#enter sib2, iclass 4, count 0 2006.162.08:30:01.78#ibcon#flushed, iclass 4, count 0 2006.162.08:30:01.78#ibcon#about to write, iclass 4, count 0 2006.162.08:30:01.78#ibcon#wrote, iclass 4, count 0 2006.162.08:30:01.79#ibcon#about to read 3, iclass 4, count 0 2006.162.08:30:01.82#ibcon#read 3, iclass 4, count 0 2006.162.08:30:01.82#ibcon#about to read 4, iclass 4, count 0 2006.162.08:30:01.82#ibcon#read 4, iclass 4, count 0 2006.162.08:30:01.82#ibcon#about to read 5, iclass 4, count 0 2006.162.08:30:01.82#ibcon#read 5, iclass 4, count 0 2006.162.08:30:01.82#ibcon#about to read 6, iclass 4, count 0 2006.162.08:30:01.82#ibcon#read 6, iclass 4, count 0 2006.162.08:30:01.82#ibcon#end of sib2, iclass 4, count 0 2006.162.08:30:01.82#ibcon#*after write, iclass 4, count 0 2006.162.08:30:01.82#ibcon#*before return 0, iclass 4, count 0 2006.162.08:30:01.82#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:30:01.82#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.162.08:30:01.82#ibcon#about to clear, iclass 4 cls_cnt 0 2006.162.08:30:01.82#ibcon#cleared, iclass 4 cls_cnt 0 2006.162.08:30:01.83$vc4f8/va=8,7 2006.162.08:30:01.83#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.162.08:30:01.83#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.162.08:30:01.83#ibcon#ireg 11 cls_cnt 2 2006.162.08:30:01.83#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.162.08:30:01.87#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.162.08:30:01.87#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.162.08:30:01.87#ibcon#enter wrdev, iclass 6, count 2 2006.162.08:30:01.87#ibcon#first serial, iclass 6, count 2 2006.162.08:30:01.87#ibcon#enter sib2, iclass 6, count 2 2006.162.08:30:01.87#ibcon#flushed, iclass 6, count 2 2006.162.08:30:01.87#ibcon#about to write, iclass 6, count 2 2006.162.08:30:01.88#ibcon#wrote, iclass 6, count 2 2006.162.08:30:01.88#ibcon#about to read 3, iclass 6, count 2 2006.162.08:30:01.90#ibcon#read 3, iclass 6, count 2 2006.162.08:30:01.90#ibcon#about to read 4, iclass 6, count 2 2006.162.08:30:01.90#ibcon#read 4, iclass 6, count 2 2006.162.08:30:01.90#ibcon#about to read 5, iclass 6, count 2 2006.162.08:30:01.90#ibcon#read 5, iclass 6, count 2 2006.162.08:30:01.90#ibcon#about to read 6, iclass 6, count 2 2006.162.08:30:01.90#ibcon#read 6, iclass 6, count 2 2006.162.08:30:01.90#ibcon#end of sib2, iclass 6, count 2 2006.162.08:30:01.90#ibcon#*mode == 0, iclass 6, count 2 2006.162.08:30:01.90#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.162.08:30:01.90#ibcon#[25=AT08-07\r\n] 2006.162.08:30:01.90#ibcon#*before write, iclass 6, count 2 2006.162.08:30:01.90#ibcon#enter sib2, iclass 6, count 2 2006.162.08:30:01.90#ibcon#flushed, iclass 6, count 2 2006.162.08:30:01.90#ibcon#about to write, iclass 6, count 2 2006.162.08:30:01.90#ibcon#wrote, iclass 6, count 2 2006.162.08:30:01.90#ibcon#about to read 3, iclass 6, count 2 2006.162.08:30:01.93#ibcon#read 3, iclass 6, count 2 2006.162.08:30:01.93#ibcon#about to read 4, iclass 6, count 2 2006.162.08:30:01.93#ibcon#read 4, iclass 6, count 2 2006.162.08:30:01.93#ibcon#about to read 5, iclass 6, count 2 2006.162.08:30:01.93#ibcon#read 5, iclass 6, count 2 2006.162.08:30:01.93#ibcon#about to read 6, iclass 6, count 2 2006.162.08:30:01.93#ibcon#read 6, iclass 6, count 2 2006.162.08:30:01.93#ibcon#end of sib2, iclass 6, count 2 2006.162.08:30:01.93#ibcon#*after write, iclass 6, count 2 2006.162.08:30:01.93#ibcon#*before return 0, iclass 6, count 2 2006.162.08:30:01.93#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.162.08:30:01.93#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.162.08:30:01.93#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.162.08:30:01.93#ibcon#ireg 7 cls_cnt 0 2006.162.08:30:01.93#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.162.08:30:02.05#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.162.08:30:02.05#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.162.08:30:02.05#ibcon#enter wrdev, iclass 6, count 0 2006.162.08:30:02.05#ibcon#first serial, iclass 6, count 0 2006.162.08:30:02.05#ibcon#enter sib2, iclass 6, count 0 2006.162.08:30:02.05#ibcon#flushed, iclass 6, count 0 2006.162.08:30:02.05#ibcon#about to write, iclass 6, count 0 2006.162.08:30:02.05#ibcon#wrote, iclass 6, count 0 2006.162.08:30:02.05#ibcon#about to read 3, iclass 6, count 0 2006.162.08:30:02.07#ibcon#read 3, iclass 6, count 0 2006.162.08:30:02.07#ibcon#about to read 4, iclass 6, count 0 2006.162.08:30:02.07#ibcon#read 4, iclass 6, count 0 2006.162.08:30:02.07#ibcon#about to read 5, iclass 6, count 0 2006.162.08:30:02.07#ibcon#read 5, iclass 6, count 0 2006.162.08:30:02.07#ibcon#about to read 6, iclass 6, count 0 2006.162.08:30:02.07#ibcon#read 6, iclass 6, count 0 2006.162.08:30:02.07#ibcon#end of sib2, iclass 6, count 0 2006.162.08:30:02.07#ibcon#*mode == 0, iclass 6, count 0 2006.162.08:30:02.07#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.162.08:30:02.07#ibcon#[25=USB\r\n] 2006.162.08:30:02.07#ibcon#*before write, iclass 6, count 0 2006.162.08:30:02.07#ibcon#enter sib2, iclass 6, count 0 2006.162.08:30:02.07#ibcon#flushed, iclass 6, count 0 2006.162.08:30:02.07#ibcon#about to write, iclass 6, count 0 2006.162.08:30:02.08#ibcon#wrote, iclass 6, count 0 2006.162.08:30:02.08#ibcon#about to read 3, iclass 6, count 0 2006.162.08:30:02.10#ibcon#read 3, iclass 6, count 0 2006.162.08:30:02.10#ibcon#about to read 4, iclass 6, count 0 2006.162.08:30:02.10#ibcon#read 4, iclass 6, count 0 2006.162.08:30:02.10#ibcon#about to read 5, iclass 6, count 0 2006.162.08:30:02.10#ibcon#read 5, iclass 6, count 0 2006.162.08:30:02.10#ibcon#about to read 6, iclass 6, count 0 2006.162.08:30:02.10#ibcon#read 6, iclass 6, count 0 2006.162.08:30:02.10#ibcon#end of sib2, iclass 6, count 0 2006.162.08:30:02.10#ibcon#*after write, iclass 6, count 0 2006.162.08:30:02.10#ibcon#*before return 0, iclass 6, count 0 2006.162.08:30:02.10#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.162.08:30:02.10#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.162.08:30:02.10#ibcon#about to clear, iclass 6 cls_cnt 0 2006.162.08:30:02.10#ibcon#cleared, iclass 6 cls_cnt 0 2006.162.08:30:02.11$vc4f8/vblo=1,632.99 2006.162.08:30:02.11#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.162.08:30:02.11#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.162.08:30:02.11#ibcon#ireg 17 cls_cnt 0 2006.162.08:30:02.11#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:30:02.11#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:30:02.11#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:30:02.11#ibcon#enter wrdev, iclass 10, count 0 2006.162.08:30:02.11#ibcon#first serial, iclass 10, count 0 2006.162.08:30:02.11#ibcon#enter sib2, iclass 10, count 0 2006.162.08:30:02.11#ibcon#flushed, iclass 10, count 0 2006.162.08:30:02.11#ibcon#about to write, iclass 10, count 0 2006.162.08:30:02.11#ibcon#wrote, iclass 10, count 0 2006.162.08:30:02.11#ibcon#about to read 3, iclass 10, count 0 2006.162.08:30:02.12#ibcon#read 3, iclass 10, count 0 2006.162.08:30:02.12#ibcon#about to read 4, iclass 10, count 0 2006.162.08:30:02.12#ibcon#read 4, iclass 10, count 0 2006.162.08:30:02.12#ibcon#about to read 5, iclass 10, count 0 2006.162.08:30:02.12#ibcon#read 5, iclass 10, count 0 2006.162.08:30:02.12#ibcon#about to read 6, iclass 10, count 0 2006.162.08:30:02.12#ibcon#read 6, iclass 10, count 0 2006.162.08:30:02.12#ibcon#end of sib2, iclass 10, count 0 2006.162.08:30:02.12#ibcon#*mode == 0, iclass 10, count 0 2006.162.08:30:02.12#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.162.08:30:02.12#ibcon#[28=FRQ=01,632.99\r\n] 2006.162.08:30:02.12#ibcon#*before write, iclass 10, count 0 2006.162.08:30:02.12#ibcon#enter sib2, iclass 10, count 0 2006.162.08:30:02.12#ibcon#flushed, iclass 10, count 0 2006.162.08:30:02.12#ibcon#about to write, iclass 10, count 0 2006.162.08:30:02.12#ibcon#wrote, iclass 10, count 0 2006.162.08:30:02.13#ibcon#about to read 3, iclass 10, count 0 2006.162.08:30:02.16#ibcon#read 3, iclass 10, count 0 2006.162.08:30:02.16#ibcon#about to read 4, iclass 10, count 0 2006.162.08:30:02.16#ibcon#read 4, iclass 10, count 0 2006.162.08:30:02.16#ibcon#about to read 5, iclass 10, count 0 2006.162.08:30:02.16#ibcon#read 5, iclass 10, count 0 2006.162.08:30:02.16#ibcon#about to read 6, iclass 10, count 0 2006.162.08:30:02.16#ibcon#read 6, iclass 10, count 0 2006.162.08:30:02.16#ibcon#end of sib2, iclass 10, count 0 2006.162.08:30:02.16#ibcon#*after write, iclass 10, count 0 2006.162.08:30:02.16#ibcon#*before return 0, iclass 10, count 0 2006.162.08:30:02.16#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:30:02.16#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.162.08:30:02.16#ibcon#about to clear, iclass 10 cls_cnt 0 2006.162.08:30:02.16#ibcon#cleared, iclass 10 cls_cnt 0 2006.162.08:30:02.17$vc4f8/vb=1,4 2006.162.08:30:02.17#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.162.08:30:02.17#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.162.08:30:02.17#ibcon#ireg 11 cls_cnt 2 2006.162.08:30:02.17#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:30:02.17#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:30:02.17#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:30:02.17#ibcon#enter wrdev, iclass 12, count 2 2006.162.08:30:02.17#ibcon#first serial, iclass 12, count 2 2006.162.08:30:02.17#ibcon#enter sib2, iclass 12, count 2 2006.162.08:30:02.17#ibcon#flushed, iclass 12, count 2 2006.162.08:30:02.17#ibcon#about to write, iclass 12, count 2 2006.162.08:30:02.17#ibcon#wrote, iclass 12, count 2 2006.162.08:30:02.17#ibcon#about to read 3, iclass 12, count 2 2006.162.08:30:02.18#ibcon#read 3, iclass 12, count 2 2006.162.08:30:02.18#ibcon#about to read 4, iclass 12, count 2 2006.162.08:30:02.18#ibcon#read 4, iclass 12, count 2 2006.162.08:30:02.18#ibcon#about to read 5, iclass 12, count 2 2006.162.08:30:02.18#ibcon#read 5, iclass 12, count 2 2006.162.08:30:02.18#ibcon#about to read 6, iclass 12, count 2 2006.162.08:30:02.18#ibcon#read 6, iclass 12, count 2 2006.162.08:30:02.18#ibcon#end of sib2, iclass 12, count 2 2006.162.08:30:02.18#ibcon#*mode == 0, iclass 12, count 2 2006.162.08:30:02.18#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.162.08:30:02.18#ibcon#[27=AT01-04\r\n] 2006.162.08:30:02.18#ibcon#*before write, iclass 12, count 2 2006.162.08:30:02.18#ibcon#enter sib2, iclass 12, count 2 2006.162.08:30:02.18#ibcon#flushed, iclass 12, count 2 2006.162.08:30:02.18#ibcon#about to write, iclass 12, count 2 2006.162.08:30:02.19#ibcon#wrote, iclass 12, count 2 2006.162.08:30:02.19#ibcon#about to read 3, iclass 12, count 2 2006.162.08:30:02.21#ibcon#read 3, iclass 12, count 2 2006.162.08:30:02.21#ibcon#about to read 4, iclass 12, count 2 2006.162.08:30:02.21#ibcon#read 4, iclass 12, count 2 2006.162.08:30:02.21#ibcon#about to read 5, iclass 12, count 2 2006.162.08:30:02.21#ibcon#read 5, iclass 12, count 2 2006.162.08:30:02.21#ibcon#about to read 6, iclass 12, count 2 2006.162.08:30:02.21#ibcon#read 6, iclass 12, count 2 2006.162.08:30:02.21#ibcon#end of sib2, iclass 12, count 2 2006.162.08:30:02.21#ibcon#*after write, iclass 12, count 2 2006.162.08:30:02.21#ibcon#*before return 0, iclass 12, count 2 2006.162.08:30:02.21#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:30:02.21#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.162.08:30:02.21#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.162.08:30:02.21#ibcon#ireg 7 cls_cnt 0 2006.162.08:30:02.21#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:30:02.33#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:30:02.33#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:30:02.33#ibcon#enter wrdev, iclass 12, count 0 2006.162.08:30:02.33#ibcon#first serial, iclass 12, count 0 2006.162.08:30:02.33#ibcon#enter sib2, iclass 12, count 0 2006.162.08:30:02.33#ibcon#flushed, iclass 12, count 0 2006.162.08:30:02.33#ibcon#about to write, iclass 12, count 0 2006.162.08:30:02.33#ibcon#wrote, iclass 12, count 0 2006.162.08:30:02.33#ibcon#about to read 3, iclass 12, count 0 2006.162.08:30:02.35#ibcon#read 3, iclass 12, count 0 2006.162.08:30:02.35#ibcon#about to read 4, iclass 12, count 0 2006.162.08:30:02.35#ibcon#read 4, iclass 12, count 0 2006.162.08:30:02.35#ibcon#about to read 5, iclass 12, count 0 2006.162.08:30:02.35#ibcon#read 5, iclass 12, count 0 2006.162.08:30:02.35#ibcon#about to read 6, iclass 12, count 0 2006.162.08:30:02.35#ibcon#read 6, iclass 12, count 0 2006.162.08:30:02.35#ibcon#end of sib2, iclass 12, count 0 2006.162.08:30:02.35#ibcon#*mode == 0, iclass 12, count 0 2006.162.08:30:02.35#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.162.08:30:02.35#ibcon#[27=USB\r\n] 2006.162.08:30:02.35#ibcon#*before write, iclass 12, count 0 2006.162.08:30:02.35#ibcon#enter sib2, iclass 12, count 0 2006.162.08:30:02.35#ibcon#flushed, iclass 12, count 0 2006.162.08:30:02.36#ibcon#about to write, iclass 12, count 0 2006.162.08:30:02.36#ibcon#wrote, iclass 12, count 0 2006.162.08:30:02.36#ibcon#about to read 3, iclass 12, count 0 2006.162.08:30:02.38#ibcon#read 3, iclass 12, count 0 2006.162.08:30:02.38#ibcon#about to read 4, iclass 12, count 0 2006.162.08:30:02.38#ibcon#read 4, iclass 12, count 0 2006.162.08:30:02.38#ibcon#about to read 5, iclass 12, count 0 2006.162.08:30:02.38#ibcon#read 5, iclass 12, count 0 2006.162.08:30:02.38#ibcon#about to read 6, iclass 12, count 0 2006.162.08:30:02.38#ibcon#read 6, iclass 12, count 0 2006.162.08:30:02.38#ibcon#end of sib2, iclass 12, count 0 2006.162.08:30:02.38#ibcon#*after write, iclass 12, count 0 2006.162.08:30:02.38#ibcon#*before return 0, iclass 12, count 0 2006.162.08:30:02.38#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:30:02.38#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.162.08:30:02.38#ibcon#about to clear, iclass 12 cls_cnt 0 2006.162.08:30:02.38#ibcon#cleared, iclass 12 cls_cnt 0 2006.162.08:30:02.39$vc4f8/vblo=2,640.99 2006.162.08:30:02.39#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.162.08:30:02.39#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.162.08:30:02.39#ibcon#ireg 17 cls_cnt 0 2006.162.08:30:02.39#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:30:02.39#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:30:02.39#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:30:02.39#ibcon#enter wrdev, iclass 14, count 0 2006.162.08:30:02.39#ibcon#first serial, iclass 14, count 0 2006.162.08:30:02.39#ibcon#enter sib2, iclass 14, count 0 2006.162.08:30:02.39#ibcon#flushed, iclass 14, count 0 2006.162.08:30:02.39#ibcon#about to write, iclass 14, count 0 2006.162.08:30:02.39#ibcon#wrote, iclass 14, count 0 2006.162.08:30:02.39#ibcon#about to read 3, iclass 14, count 0 2006.162.08:30:02.40#ibcon#read 3, iclass 14, count 0 2006.162.08:30:02.40#ibcon#about to read 4, iclass 14, count 0 2006.162.08:30:02.40#ibcon#read 4, iclass 14, count 0 2006.162.08:30:02.40#ibcon#about to read 5, iclass 14, count 0 2006.162.08:30:02.40#ibcon#read 5, iclass 14, count 0 2006.162.08:30:02.40#ibcon#about to read 6, iclass 14, count 0 2006.162.08:30:02.40#ibcon#read 6, iclass 14, count 0 2006.162.08:30:02.40#ibcon#end of sib2, iclass 14, count 0 2006.162.08:30:02.40#ibcon#*mode == 0, iclass 14, count 0 2006.162.08:30:02.40#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.162.08:30:02.40#ibcon#[28=FRQ=02,640.99\r\n] 2006.162.08:30:02.40#ibcon#*before write, iclass 14, count 0 2006.162.08:30:02.40#ibcon#enter sib2, iclass 14, count 0 2006.162.08:30:02.40#ibcon#flushed, iclass 14, count 0 2006.162.08:30:02.40#ibcon#about to write, iclass 14, count 0 2006.162.08:30:02.40#ibcon#wrote, iclass 14, count 0 2006.162.08:30:02.41#ibcon#about to read 3, iclass 14, count 0 2006.162.08:30:02.44#ibcon#read 3, iclass 14, count 0 2006.162.08:30:02.44#ibcon#about to read 4, iclass 14, count 0 2006.162.08:30:02.44#ibcon#read 4, iclass 14, count 0 2006.162.08:30:02.44#ibcon#about to read 5, iclass 14, count 0 2006.162.08:30:02.44#ibcon#read 5, iclass 14, count 0 2006.162.08:30:02.44#ibcon#about to read 6, iclass 14, count 0 2006.162.08:30:02.44#ibcon#read 6, iclass 14, count 0 2006.162.08:30:02.44#ibcon#end of sib2, iclass 14, count 0 2006.162.08:30:02.44#ibcon#*after write, iclass 14, count 0 2006.162.08:30:02.44#ibcon#*before return 0, iclass 14, count 0 2006.162.08:30:02.44#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:30:02.44#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.162.08:30:02.44#ibcon#about to clear, iclass 14 cls_cnt 0 2006.162.08:30:02.44#ibcon#cleared, iclass 14 cls_cnt 0 2006.162.08:30:02.45$vc4f8/vb=2,4 2006.162.08:30:02.45#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.162.08:30:02.45#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.162.08:30:02.45#ibcon#ireg 11 cls_cnt 2 2006.162.08:30:02.45#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:30:02.49#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:30:02.49#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:30:02.49#ibcon#enter wrdev, iclass 16, count 2 2006.162.08:30:02.49#ibcon#first serial, iclass 16, count 2 2006.162.08:30:02.49#ibcon#enter sib2, iclass 16, count 2 2006.162.08:30:02.49#ibcon#flushed, iclass 16, count 2 2006.162.08:30:02.49#ibcon#about to write, iclass 16, count 2 2006.162.08:30:02.49#ibcon#wrote, iclass 16, count 2 2006.162.08:30:02.49#ibcon#about to read 3, iclass 16, count 2 2006.162.08:30:02.51#ibcon#read 3, iclass 16, count 2 2006.162.08:30:02.51#ibcon#about to read 4, iclass 16, count 2 2006.162.08:30:02.51#ibcon#read 4, iclass 16, count 2 2006.162.08:30:02.51#ibcon#about to read 5, iclass 16, count 2 2006.162.08:30:02.51#ibcon#read 5, iclass 16, count 2 2006.162.08:30:02.51#ibcon#about to read 6, iclass 16, count 2 2006.162.08:30:02.51#ibcon#read 6, iclass 16, count 2 2006.162.08:30:02.51#ibcon#end of sib2, iclass 16, count 2 2006.162.08:30:02.51#ibcon#*mode == 0, iclass 16, count 2 2006.162.08:30:02.51#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.162.08:30:02.51#ibcon#[27=AT02-04\r\n] 2006.162.08:30:02.51#ibcon#*before write, iclass 16, count 2 2006.162.08:30:02.51#ibcon#enter sib2, iclass 16, count 2 2006.162.08:30:02.51#ibcon#flushed, iclass 16, count 2 2006.162.08:30:02.51#ibcon#about to write, iclass 16, count 2 2006.162.08:30:02.51#ibcon#wrote, iclass 16, count 2 2006.162.08:30:02.52#ibcon#about to read 3, iclass 16, count 2 2006.162.08:30:02.54#ibcon#read 3, iclass 16, count 2 2006.162.08:30:02.54#ibcon#about to read 4, iclass 16, count 2 2006.162.08:30:02.54#ibcon#read 4, iclass 16, count 2 2006.162.08:30:02.54#ibcon#about to read 5, iclass 16, count 2 2006.162.08:30:02.54#ibcon#read 5, iclass 16, count 2 2006.162.08:30:02.54#ibcon#about to read 6, iclass 16, count 2 2006.162.08:30:02.54#ibcon#read 6, iclass 16, count 2 2006.162.08:30:02.54#ibcon#end of sib2, iclass 16, count 2 2006.162.08:30:02.54#ibcon#*after write, iclass 16, count 2 2006.162.08:30:02.54#ibcon#*before return 0, iclass 16, count 2 2006.162.08:30:02.54#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:30:02.54#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.162.08:30:02.54#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.162.08:30:02.54#ibcon#ireg 7 cls_cnt 0 2006.162.08:30:02.54#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:30:02.66#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:30:02.66#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:30:02.66#ibcon#enter wrdev, iclass 16, count 0 2006.162.08:30:02.66#ibcon#first serial, iclass 16, count 0 2006.162.08:30:02.66#ibcon#enter sib2, iclass 16, count 0 2006.162.08:30:02.66#ibcon#flushed, iclass 16, count 0 2006.162.08:30:02.66#ibcon#about to write, iclass 16, count 0 2006.162.08:30:02.66#ibcon#wrote, iclass 16, count 0 2006.162.08:30:02.66#ibcon#about to read 3, iclass 16, count 0 2006.162.08:30:02.68#ibcon#read 3, iclass 16, count 0 2006.162.08:30:02.68#ibcon#about to read 4, iclass 16, count 0 2006.162.08:30:02.68#ibcon#read 4, iclass 16, count 0 2006.162.08:30:02.68#ibcon#about to read 5, iclass 16, count 0 2006.162.08:30:02.68#ibcon#read 5, iclass 16, count 0 2006.162.08:30:02.68#ibcon#about to read 6, iclass 16, count 0 2006.162.08:30:02.68#ibcon#read 6, iclass 16, count 0 2006.162.08:30:02.68#ibcon#end of sib2, iclass 16, count 0 2006.162.08:30:02.68#ibcon#*mode == 0, iclass 16, count 0 2006.162.08:30:02.68#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.162.08:30:02.68#ibcon#[27=USB\r\n] 2006.162.08:30:02.68#ibcon#*before write, iclass 16, count 0 2006.162.08:30:02.68#ibcon#enter sib2, iclass 16, count 0 2006.162.08:30:02.68#ibcon#flushed, iclass 16, count 0 2006.162.08:30:02.68#ibcon#about to write, iclass 16, count 0 2006.162.08:30:02.69#ibcon#wrote, iclass 16, count 0 2006.162.08:30:02.69#ibcon#about to read 3, iclass 16, count 0 2006.162.08:30:02.71#ibcon#read 3, iclass 16, count 0 2006.162.08:30:02.71#ibcon#about to read 4, iclass 16, count 0 2006.162.08:30:02.71#ibcon#read 4, iclass 16, count 0 2006.162.08:30:02.71#ibcon#about to read 5, iclass 16, count 0 2006.162.08:30:02.71#ibcon#read 5, iclass 16, count 0 2006.162.08:30:02.71#ibcon#about to read 6, iclass 16, count 0 2006.162.08:30:02.71#ibcon#read 6, iclass 16, count 0 2006.162.08:30:02.71#ibcon#end of sib2, iclass 16, count 0 2006.162.08:30:02.71#ibcon#*after write, iclass 16, count 0 2006.162.08:30:02.71#ibcon#*before return 0, iclass 16, count 0 2006.162.08:30:02.71#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:30:02.71#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.162.08:30:02.71#ibcon#about to clear, iclass 16 cls_cnt 0 2006.162.08:30:02.71#ibcon#cleared, iclass 16 cls_cnt 0 2006.162.08:30:02.72$vc4f8/vblo=3,656.99 2006.162.08:30:02.72#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.162.08:30:02.72#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.162.08:30:02.72#ibcon#ireg 17 cls_cnt 0 2006.162.08:30:02.72#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:30:02.72#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:30:02.72#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:30:02.72#ibcon#enter wrdev, iclass 18, count 0 2006.162.08:30:02.72#ibcon#first serial, iclass 18, count 0 2006.162.08:30:02.72#ibcon#enter sib2, iclass 18, count 0 2006.162.08:30:02.72#ibcon#flushed, iclass 18, count 0 2006.162.08:30:02.72#ibcon#about to write, iclass 18, count 0 2006.162.08:30:02.72#ibcon#wrote, iclass 18, count 0 2006.162.08:30:02.72#ibcon#about to read 3, iclass 18, count 0 2006.162.08:30:02.73#ibcon#read 3, iclass 18, count 0 2006.162.08:30:02.73#ibcon#about to read 4, iclass 18, count 0 2006.162.08:30:02.73#ibcon#read 4, iclass 18, count 0 2006.162.08:30:02.73#ibcon#about to read 5, iclass 18, count 0 2006.162.08:30:02.73#ibcon#read 5, iclass 18, count 0 2006.162.08:30:02.73#ibcon#about to read 6, iclass 18, count 0 2006.162.08:30:02.73#ibcon#read 6, iclass 18, count 0 2006.162.08:30:02.73#ibcon#end of sib2, iclass 18, count 0 2006.162.08:30:02.73#ibcon#*mode == 0, iclass 18, count 0 2006.162.08:30:02.73#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.162.08:30:02.73#ibcon#[28=FRQ=03,656.99\r\n] 2006.162.08:30:02.73#ibcon#*before write, iclass 18, count 0 2006.162.08:30:02.73#ibcon#enter sib2, iclass 18, count 0 2006.162.08:30:02.73#ibcon#flushed, iclass 18, count 0 2006.162.08:30:02.74#ibcon#about to write, iclass 18, count 0 2006.162.08:30:02.74#ibcon#wrote, iclass 18, count 0 2006.162.08:30:02.74#ibcon#about to read 3, iclass 18, count 0 2006.162.08:30:02.77#ibcon#read 3, iclass 18, count 0 2006.162.08:30:02.77#ibcon#about to read 4, iclass 18, count 0 2006.162.08:30:02.77#ibcon#read 4, iclass 18, count 0 2006.162.08:30:02.77#ibcon#about to read 5, iclass 18, count 0 2006.162.08:30:02.77#ibcon#read 5, iclass 18, count 0 2006.162.08:30:02.77#ibcon#about to read 6, iclass 18, count 0 2006.162.08:30:02.77#ibcon#read 6, iclass 18, count 0 2006.162.08:30:02.77#ibcon#end of sib2, iclass 18, count 0 2006.162.08:30:02.77#ibcon#*after write, iclass 18, count 0 2006.162.08:30:02.77#ibcon#*before return 0, iclass 18, count 0 2006.162.08:30:02.77#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:30:02.77#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.162.08:30:02.77#ibcon#about to clear, iclass 18 cls_cnt 0 2006.162.08:30:02.77#ibcon#cleared, iclass 18 cls_cnt 0 2006.162.08:30:02.78$vc4f8/vb=3,4 2006.162.08:30:02.78#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.162.08:30:02.78#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.162.08:30:02.78#ibcon#ireg 11 cls_cnt 2 2006.162.08:30:02.78#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:30:02.82#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:30:02.82#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:30:02.82#ibcon#enter wrdev, iclass 20, count 2 2006.162.08:30:02.82#ibcon#first serial, iclass 20, count 2 2006.162.08:30:02.82#ibcon#enter sib2, iclass 20, count 2 2006.162.08:30:02.82#ibcon#flushed, iclass 20, count 2 2006.162.08:30:02.82#ibcon#about to write, iclass 20, count 2 2006.162.08:30:02.82#ibcon#wrote, iclass 20, count 2 2006.162.08:30:02.82#ibcon#about to read 3, iclass 20, count 2 2006.162.08:30:02.84#ibcon#read 3, iclass 20, count 2 2006.162.08:30:02.84#ibcon#about to read 4, iclass 20, count 2 2006.162.08:30:02.84#ibcon#read 4, iclass 20, count 2 2006.162.08:30:02.84#ibcon#about to read 5, iclass 20, count 2 2006.162.08:30:02.84#ibcon#read 5, iclass 20, count 2 2006.162.08:30:02.84#ibcon#about to read 6, iclass 20, count 2 2006.162.08:30:02.84#ibcon#read 6, iclass 20, count 2 2006.162.08:30:02.84#ibcon#end of sib2, iclass 20, count 2 2006.162.08:30:02.84#ibcon#*mode == 0, iclass 20, count 2 2006.162.08:30:02.84#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.162.08:30:02.84#ibcon#[27=AT03-04\r\n] 2006.162.08:30:02.84#ibcon#*before write, iclass 20, count 2 2006.162.08:30:02.84#ibcon#enter sib2, iclass 20, count 2 2006.162.08:30:02.84#ibcon#flushed, iclass 20, count 2 2006.162.08:30:02.84#ibcon#about to write, iclass 20, count 2 2006.162.08:30:02.85#ibcon#wrote, iclass 20, count 2 2006.162.08:30:02.85#ibcon#about to read 3, iclass 20, count 2 2006.162.08:30:02.87#ibcon#read 3, iclass 20, count 2 2006.162.08:30:02.87#ibcon#about to read 4, iclass 20, count 2 2006.162.08:30:02.87#ibcon#read 4, iclass 20, count 2 2006.162.08:30:02.87#ibcon#about to read 5, iclass 20, count 2 2006.162.08:30:02.87#ibcon#read 5, iclass 20, count 2 2006.162.08:30:02.87#ibcon#about to read 6, iclass 20, count 2 2006.162.08:30:02.87#ibcon#read 6, iclass 20, count 2 2006.162.08:30:02.87#ibcon#end of sib2, iclass 20, count 2 2006.162.08:30:02.87#ibcon#*after write, iclass 20, count 2 2006.162.08:30:02.87#ibcon#*before return 0, iclass 20, count 2 2006.162.08:30:02.87#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:30:02.87#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.162.08:30:02.87#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.162.08:30:02.87#ibcon#ireg 7 cls_cnt 0 2006.162.08:30:02.87#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:30:02.99#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:30:02.99#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:30:02.99#ibcon#enter wrdev, iclass 20, count 0 2006.162.08:30:02.99#ibcon#first serial, iclass 20, count 0 2006.162.08:30:02.99#ibcon#enter sib2, iclass 20, count 0 2006.162.08:30:02.99#ibcon#flushed, iclass 20, count 0 2006.162.08:30:02.99#ibcon#about to write, iclass 20, count 0 2006.162.08:30:02.99#ibcon#wrote, iclass 20, count 0 2006.162.08:30:02.99#ibcon#about to read 3, iclass 20, count 0 2006.162.08:30:03.01#ibcon#read 3, iclass 20, count 0 2006.162.08:30:03.01#ibcon#about to read 4, iclass 20, count 0 2006.162.08:30:03.01#ibcon#read 4, iclass 20, count 0 2006.162.08:30:03.01#ibcon#about to read 5, iclass 20, count 0 2006.162.08:30:03.01#ibcon#read 5, iclass 20, count 0 2006.162.08:30:03.01#ibcon#about to read 6, iclass 20, count 0 2006.162.08:30:03.01#ibcon#read 6, iclass 20, count 0 2006.162.08:30:03.01#ibcon#end of sib2, iclass 20, count 0 2006.162.08:30:03.01#ibcon#*mode == 0, iclass 20, count 0 2006.162.08:30:03.01#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.162.08:30:03.01#ibcon#[27=USB\r\n] 2006.162.08:30:03.01#ibcon#*before write, iclass 20, count 0 2006.162.08:30:03.01#ibcon#enter sib2, iclass 20, count 0 2006.162.08:30:03.01#ibcon#flushed, iclass 20, count 0 2006.162.08:30:03.01#ibcon#about to write, iclass 20, count 0 2006.162.08:30:03.02#ibcon#wrote, iclass 20, count 0 2006.162.08:30:03.02#ibcon#about to read 3, iclass 20, count 0 2006.162.08:30:03.04#ibcon#read 3, iclass 20, count 0 2006.162.08:30:03.04#ibcon#about to read 4, iclass 20, count 0 2006.162.08:30:03.04#ibcon#read 4, iclass 20, count 0 2006.162.08:30:03.04#ibcon#about to read 5, iclass 20, count 0 2006.162.08:30:03.04#ibcon#read 5, iclass 20, count 0 2006.162.08:30:03.04#ibcon#about to read 6, iclass 20, count 0 2006.162.08:30:03.04#ibcon#read 6, iclass 20, count 0 2006.162.08:30:03.04#ibcon#end of sib2, iclass 20, count 0 2006.162.08:30:03.04#ibcon#*after write, iclass 20, count 0 2006.162.08:30:03.04#ibcon#*before return 0, iclass 20, count 0 2006.162.08:30:03.04#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:30:03.04#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.162.08:30:03.04#ibcon#about to clear, iclass 20 cls_cnt 0 2006.162.08:30:03.04#ibcon#cleared, iclass 20 cls_cnt 0 2006.162.08:30:03.05$vc4f8/vblo=4,712.99 2006.162.08:30:03.05#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.162.08:30:03.05#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.162.08:30:03.05#ibcon#ireg 17 cls_cnt 0 2006.162.08:30:03.05#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:30:03.05#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:30:03.05#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:30:03.05#ibcon#enter wrdev, iclass 22, count 0 2006.162.08:30:03.05#ibcon#first serial, iclass 22, count 0 2006.162.08:30:03.05#ibcon#enter sib2, iclass 22, count 0 2006.162.08:30:03.05#ibcon#flushed, iclass 22, count 0 2006.162.08:30:03.05#ibcon#about to write, iclass 22, count 0 2006.162.08:30:03.05#ibcon#wrote, iclass 22, count 0 2006.162.08:30:03.05#ibcon#about to read 3, iclass 22, count 0 2006.162.08:30:03.06#ibcon#read 3, iclass 22, count 0 2006.162.08:30:03.06#ibcon#about to read 4, iclass 22, count 0 2006.162.08:30:03.06#ibcon#read 4, iclass 22, count 0 2006.162.08:30:03.06#ibcon#about to read 5, iclass 22, count 0 2006.162.08:30:03.06#ibcon#read 5, iclass 22, count 0 2006.162.08:30:03.06#ibcon#about to read 6, iclass 22, count 0 2006.162.08:30:03.06#ibcon#read 6, iclass 22, count 0 2006.162.08:30:03.06#ibcon#end of sib2, iclass 22, count 0 2006.162.08:30:03.06#ibcon#*mode == 0, iclass 22, count 0 2006.162.08:30:03.06#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.162.08:30:03.06#ibcon#[28=FRQ=04,712.99\r\n] 2006.162.08:30:03.06#ibcon#*before write, iclass 22, count 0 2006.162.08:30:03.06#ibcon#enter sib2, iclass 22, count 0 2006.162.08:30:03.06#ibcon#flushed, iclass 22, count 0 2006.162.08:30:03.06#ibcon#about to write, iclass 22, count 0 2006.162.08:30:03.06#ibcon#wrote, iclass 22, count 0 2006.162.08:30:03.07#ibcon#about to read 3, iclass 22, count 0 2006.162.08:30:03.10#ibcon#read 3, iclass 22, count 0 2006.162.08:30:03.10#ibcon#about to read 4, iclass 22, count 0 2006.162.08:30:03.10#ibcon#read 4, iclass 22, count 0 2006.162.08:30:03.10#ibcon#about to read 5, iclass 22, count 0 2006.162.08:30:03.10#ibcon#read 5, iclass 22, count 0 2006.162.08:30:03.10#ibcon#about to read 6, iclass 22, count 0 2006.162.08:30:03.10#ibcon#read 6, iclass 22, count 0 2006.162.08:30:03.10#ibcon#end of sib2, iclass 22, count 0 2006.162.08:30:03.10#ibcon#*after write, iclass 22, count 0 2006.162.08:30:03.10#ibcon#*before return 0, iclass 22, count 0 2006.162.08:30:03.10#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:30:03.10#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.162.08:30:03.10#ibcon#about to clear, iclass 22 cls_cnt 0 2006.162.08:30:03.10#ibcon#cleared, iclass 22 cls_cnt 0 2006.162.08:30:03.11$vc4f8/vb=4,4 2006.162.08:30:03.11#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.162.08:30:03.11#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.162.08:30:03.11#ibcon#ireg 11 cls_cnt 2 2006.162.08:30:03.11#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:30:03.15#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:30:03.15#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:30:03.15#ibcon#enter wrdev, iclass 24, count 2 2006.162.08:30:03.15#ibcon#first serial, iclass 24, count 2 2006.162.08:30:03.15#ibcon#enter sib2, iclass 24, count 2 2006.162.08:30:03.15#ibcon#flushed, iclass 24, count 2 2006.162.08:30:03.15#ibcon#about to write, iclass 24, count 2 2006.162.08:30:03.15#ibcon#wrote, iclass 24, count 2 2006.162.08:30:03.15#ibcon#about to read 3, iclass 24, count 2 2006.162.08:30:03.17#ibcon#read 3, iclass 24, count 2 2006.162.08:30:03.17#ibcon#about to read 4, iclass 24, count 2 2006.162.08:30:03.17#ibcon#read 4, iclass 24, count 2 2006.162.08:30:03.17#ibcon#about to read 5, iclass 24, count 2 2006.162.08:30:03.17#ibcon#read 5, iclass 24, count 2 2006.162.08:30:03.17#ibcon#about to read 6, iclass 24, count 2 2006.162.08:30:03.17#ibcon#read 6, iclass 24, count 2 2006.162.08:30:03.17#ibcon#end of sib2, iclass 24, count 2 2006.162.08:30:03.17#ibcon#*mode == 0, iclass 24, count 2 2006.162.08:30:03.17#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.162.08:30:03.17#ibcon#[27=AT04-04\r\n] 2006.162.08:30:03.17#ibcon#*before write, iclass 24, count 2 2006.162.08:30:03.17#ibcon#enter sib2, iclass 24, count 2 2006.162.08:30:03.17#ibcon#flushed, iclass 24, count 2 2006.162.08:30:03.17#ibcon#about to write, iclass 24, count 2 2006.162.08:30:03.17#ibcon#wrote, iclass 24, count 2 2006.162.08:30:03.18#ibcon#about to read 3, iclass 24, count 2 2006.162.08:30:03.20#ibcon#read 3, iclass 24, count 2 2006.162.08:30:03.20#ibcon#about to read 4, iclass 24, count 2 2006.162.08:30:03.20#ibcon#read 4, iclass 24, count 2 2006.162.08:30:03.20#ibcon#about to read 5, iclass 24, count 2 2006.162.08:30:03.20#ibcon#read 5, iclass 24, count 2 2006.162.08:30:03.20#ibcon#about to read 6, iclass 24, count 2 2006.162.08:30:03.20#ibcon#read 6, iclass 24, count 2 2006.162.08:30:03.20#ibcon#end of sib2, iclass 24, count 2 2006.162.08:30:03.20#ibcon#*after write, iclass 24, count 2 2006.162.08:30:03.20#ibcon#*before return 0, iclass 24, count 2 2006.162.08:30:03.20#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:30:03.20#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.162.08:30:03.20#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.162.08:30:03.20#ibcon#ireg 7 cls_cnt 0 2006.162.08:30:03.20#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:30:03.32#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:30:03.32#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:30:03.32#ibcon#enter wrdev, iclass 24, count 0 2006.162.08:30:03.32#ibcon#first serial, iclass 24, count 0 2006.162.08:30:03.32#ibcon#enter sib2, iclass 24, count 0 2006.162.08:30:03.32#ibcon#flushed, iclass 24, count 0 2006.162.08:30:03.32#ibcon#about to write, iclass 24, count 0 2006.162.08:30:03.32#ibcon#wrote, iclass 24, count 0 2006.162.08:30:03.32#ibcon#about to read 3, iclass 24, count 0 2006.162.08:30:03.34#ibcon#read 3, iclass 24, count 0 2006.162.08:30:03.34#ibcon#about to read 4, iclass 24, count 0 2006.162.08:30:03.34#ibcon#read 4, iclass 24, count 0 2006.162.08:30:03.34#ibcon#about to read 5, iclass 24, count 0 2006.162.08:30:03.34#ibcon#read 5, iclass 24, count 0 2006.162.08:30:03.34#ibcon#about to read 6, iclass 24, count 0 2006.162.08:30:03.34#ibcon#read 6, iclass 24, count 0 2006.162.08:30:03.34#ibcon#end of sib2, iclass 24, count 0 2006.162.08:30:03.34#ibcon#*mode == 0, iclass 24, count 0 2006.162.08:30:03.34#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.162.08:30:03.34#ibcon#[27=USB\r\n] 2006.162.08:30:03.34#ibcon#*before write, iclass 24, count 0 2006.162.08:30:03.34#ibcon#enter sib2, iclass 24, count 0 2006.162.08:30:03.34#ibcon#flushed, iclass 24, count 0 2006.162.08:30:03.34#ibcon#about to write, iclass 24, count 0 2006.162.08:30:03.34#ibcon#wrote, iclass 24, count 0 2006.162.08:30:03.35#ibcon#about to read 3, iclass 24, count 0 2006.162.08:30:03.37#ibcon#read 3, iclass 24, count 0 2006.162.08:30:03.37#ibcon#about to read 4, iclass 24, count 0 2006.162.08:30:03.37#ibcon#read 4, iclass 24, count 0 2006.162.08:30:03.37#ibcon#about to read 5, iclass 24, count 0 2006.162.08:30:03.37#ibcon#read 5, iclass 24, count 0 2006.162.08:30:03.37#ibcon#about to read 6, iclass 24, count 0 2006.162.08:30:03.37#ibcon#read 6, iclass 24, count 0 2006.162.08:30:03.37#ibcon#end of sib2, iclass 24, count 0 2006.162.08:30:03.37#ibcon#*after write, iclass 24, count 0 2006.162.08:30:03.37#ibcon#*before return 0, iclass 24, count 0 2006.162.08:30:03.37#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:30:03.37#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.162.08:30:03.37#ibcon#about to clear, iclass 24 cls_cnt 0 2006.162.08:30:03.37#ibcon#cleared, iclass 24 cls_cnt 0 2006.162.08:30:03.38$vc4f8/vblo=5,744.99 2006.162.08:30:03.38#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.162.08:30:03.38#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.162.08:30:03.38#ibcon#ireg 17 cls_cnt 0 2006.162.08:30:03.38#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:30:03.38#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:30:03.38#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:30:03.38#ibcon#enter wrdev, iclass 26, count 0 2006.162.08:30:03.38#ibcon#first serial, iclass 26, count 0 2006.162.08:30:03.38#ibcon#enter sib2, iclass 26, count 0 2006.162.08:30:03.38#ibcon#flushed, iclass 26, count 0 2006.162.08:30:03.38#ibcon#about to write, iclass 26, count 0 2006.162.08:30:03.38#ibcon#wrote, iclass 26, count 0 2006.162.08:30:03.38#ibcon#about to read 3, iclass 26, count 0 2006.162.08:30:03.39#ibcon#read 3, iclass 26, count 0 2006.162.08:30:03.39#ibcon#about to read 4, iclass 26, count 0 2006.162.08:30:03.39#ibcon#read 4, iclass 26, count 0 2006.162.08:30:03.39#ibcon#about to read 5, iclass 26, count 0 2006.162.08:30:03.39#ibcon#read 5, iclass 26, count 0 2006.162.08:30:03.39#ibcon#about to read 6, iclass 26, count 0 2006.162.08:30:03.39#ibcon#read 6, iclass 26, count 0 2006.162.08:30:03.39#ibcon#end of sib2, iclass 26, count 0 2006.162.08:30:03.39#ibcon#*mode == 0, iclass 26, count 0 2006.162.08:30:03.39#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.162.08:30:03.39#ibcon#[28=FRQ=05,744.99\r\n] 2006.162.08:30:03.39#ibcon#*before write, iclass 26, count 0 2006.162.08:30:03.39#ibcon#enter sib2, iclass 26, count 0 2006.162.08:30:03.39#ibcon#flushed, iclass 26, count 0 2006.162.08:30:03.39#ibcon#about to write, iclass 26, count 0 2006.162.08:30:03.39#ibcon#wrote, iclass 26, count 0 2006.162.08:30:03.40#ibcon#about to read 3, iclass 26, count 0 2006.162.08:30:03.43#ibcon#read 3, iclass 26, count 0 2006.162.08:30:03.43#ibcon#about to read 4, iclass 26, count 0 2006.162.08:30:03.43#ibcon#read 4, iclass 26, count 0 2006.162.08:30:03.43#ibcon#about to read 5, iclass 26, count 0 2006.162.08:30:03.43#ibcon#read 5, iclass 26, count 0 2006.162.08:30:03.43#ibcon#about to read 6, iclass 26, count 0 2006.162.08:30:03.43#ibcon#read 6, iclass 26, count 0 2006.162.08:30:03.43#ibcon#end of sib2, iclass 26, count 0 2006.162.08:30:03.43#ibcon#*after write, iclass 26, count 0 2006.162.08:30:03.43#ibcon#*before return 0, iclass 26, count 0 2006.162.08:30:03.43#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:30:03.43#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.162.08:30:03.43#ibcon#about to clear, iclass 26 cls_cnt 0 2006.162.08:30:03.43#ibcon#cleared, iclass 26 cls_cnt 0 2006.162.08:30:03.44$vc4f8/vb=5,4 2006.162.08:30:03.44#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.162.08:30:03.44#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.162.08:30:03.44#ibcon#ireg 11 cls_cnt 2 2006.162.08:30:03.44#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:30:03.48#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:30:03.48#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:30:03.48#ibcon#enter wrdev, iclass 28, count 2 2006.162.08:30:03.48#ibcon#first serial, iclass 28, count 2 2006.162.08:30:03.48#ibcon#enter sib2, iclass 28, count 2 2006.162.08:30:03.48#ibcon#flushed, iclass 28, count 2 2006.162.08:30:03.48#ibcon#about to write, iclass 28, count 2 2006.162.08:30:03.48#ibcon#wrote, iclass 28, count 2 2006.162.08:30:03.48#ibcon#about to read 3, iclass 28, count 2 2006.162.08:30:03.51#ibcon#read 3, iclass 28, count 2 2006.162.08:30:03.51#ibcon#about to read 4, iclass 28, count 2 2006.162.08:30:03.51#ibcon#read 4, iclass 28, count 2 2006.162.08:30:03.51#ibcon#about to read 5, iclass 28, count 2 2006.162.08:30:03.51#ibcon#read 5, iclass 28, count 2 2006.162.08:30:03.51#ibcon#about to read 6, iclass 28, count 2 2006.162.08:30:03.51#ibcon#read 6, iclass 28, count 2 2006.162.08:30:03.51#ibcon#end of sib2, iclass 28, count 2 2006.162.08:30:03.51#ibcon#*mode == 0, iclass 28, count 2 2006.162.08:30:03.51#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.162.08:30:03.51#ibcon#[27=AT05-04\r\n] 2006.162.08:30:03.51#ibcon#*before write, iclass 28, count 2 2006.162.08:30:03.51#ibcon#enter sib2, iclass 28, count 2 2006.162.08:30:03.51#ibcon#flushed, iclass 28, count 2 2006.162.08:30:03.51#ibcon#about to write, iclass 28, count 2 2006.162.08:30:03.51#ibcon#wrote, iclass 28, count 2 2006.162.08:30:03.51#ibcon#about to read 3, iclass 28, count 2 2006.162.08:30:03.54#ibcon#read 3, iclass 28, count 2 2006.162.08:30:03.54#ibcon#about to read 4, iclass 28, count 2 2006.162.08:30:03.54#ibcon#read 4, iclass 28, count 2 2006.162.08:30:03.54#ibcon#about to read 5, iclass 28, count 2 2006.162.08:30:03.54#ibcon#read 5, iclass 28, count 2 2006.162.08:30:03.54#ibcon#about to read 6, iclass 28, count 2 2006.162.08:30:03.54#ibcon#read 6, iclass 28, count 2 2006.162.08:30:03.54#ibcon#end of sib2, iclass 28, count 2 2006.162.08:30:03.54#ibcon#*after write, iclass 28, count 2 2006.162.08:30:03.54#ibcon#*before return 0, iclass 28, count 2 2006.162.08:30:03.54#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:30:03.54#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.162.08:30:03.54#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.162.08:30:03.54#ibcon#ireg 7 cls_cnt 0 2006.162.08:30:03.54#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:30:03.66#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:30:03.66#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:30:03.66#ibcon#enter wrdev, iclass 28, count 0 2006.162.08:30:03.66#ibcon#first serial, iclass 28, count 0 2006.162.08:30:03.66#ibcon#enter sib2, iclass 28, count 0 2006.162.08:30:03.66#ibcon#flushed, iclass 28, count 0 2006.162.08:30:03.66#ibcon#about to write, iclass 28, count 0 2006.162.08:30:03.66#ibcon#wrote, iclass 28, count 0 2006.162.08:30:03.66#ibcon#about to read 3, iclass 28, count 0 2006.162.08:30:03.68#ibcon#read 3, iclass 28, count 0 2006.162.08:30:03.68#ibcon#about to read 4, iclass 28, count 0 2006.162.08:30:03.68#ibcon#read 4, iclass 28, count 0 2006.162.08:30:03.68#ibcon#about to read 5, iclass 28, count 0 2006.162.08:30:03.68#ibcon#read 5, iclass 28, count 0 2006.162.08:30:03.68#ibcon#about to read 6, iclass 28, count 0 2006.162.08:30:03.68#ibcon#read 6, iclass 28, count 0 2006.162.08:30:03.68#ibcon#end of sib2, iclass 28, count 0 2006.162.08:30:03.68#ibcon#*mode == 0, iclass 28, count 0 2006.162.08:30:03.68#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.162.08:30:03.68#ibcon#[27=USB\r\n] 2006.162.08:30:03.68#ibcon#*before write, iclass 28, count 0 2006.162.08:30:03.68#ibcon#enter sib2, iclass 28, count 0 2006.162.08:30:03.68#ibcon#flushed, iclass 28, count 0 2006.162.08:30:03.68#ibcon#about to write, iclass 28, count 0 2006.162.08:30:03.68#ibcon#wrote, iclass 28, count 0 2006.162.08:30:03.69#ibcon#about to read 3, iclass 28, count 0 2006.162.08:30:03.71#ibcon#read 3, iclass 28, count 0 2006.162.08:30:03.71#ibcon#about to read 4, iclass 28, count 0 2006.162.08:30:03.71#ibcon#read 4, iclass 28, count 0 2006.162.08:30:03.71#ibcon#about to read 5, iclass 28, count 0 2006.162.08:30:03.71#ibcon#read 5, iclass 28, count 0 2006.162.08:30:03.71#ibcon#about to read 6, iclass 28, count 0 2006.162.08:30:03.71#ibcon#read 6, iclass 28, count 0 2006.162.08:30:03.71#ibcon#end of sib2, iclass 28, count 0 2006.162.08:30:03.71#ibcon#*after write, iclass 28, count 0 2006.162.08:30:03.71#ibcon#*before return 0, iclass 28, count 0 2006.162.08:30:03.71#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:30:03.71#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.162.08:30:03.71#ibcon#about to clear, iclass 28 cls_cnt 0 2006.162.08:30:03.71#ibcon#cleared, iclass 28 cls_cnt 0 2006.162.08:30:03.72$vc4f8/vblo=6,752.99 2006.162.08:30:03.72#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.162.08:30:03.72#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.162.08:30:03.72#ibcon#ireg 17 cls_cnt 0 2006.162.08:30:03.72#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:30:03.72#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:30:03.72#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:30:03.72#ibcon#enter wrdev, iclass 30, count 0 2006.162.08:30:03.72#ibcon#first serial, iclass 30, count 0 2006.162.08:30:03.72#ibcon#enter sib2, iclass 30, count 0 2006.162.08:30:03.72#ibcon#flushed, iclass 30, count 0 2006.162.08:30:03.72#ibcon#about to write, iclass 30, count 0 2006.162.08:30:03.72#ibcon#wrote, iclass 30, count 0 2006.162.08:30:03.72#ibcon#about to read 3, iclass 30, count 0 2006.162.08:30:03.73#ibcon#read 3, iclass 30, count 0 2006.162.08:30:03.73#ibcon#about to read 4, iclass 30, count 0 2006.162.08:30:03.73#ibcon#read 4, iclass 30, count 0 2006.162.08:30:03.73#ibcon#about to read 5, iclass 30, count 0 2006.162.08:30:03.73#ibcon#read 5, iclass 30, count 0 2006.162.08:30:03.73#ibcon#about to read 6, iclass 30, count 0 2006.162.08:30:03.73#ibcon#read 6, iclass 30, count 0 2006.162.08:30:03.73#ibcon#end of sib2, iclass 30, count 0 2006.162.08:30:03.73#ibcon#*mode == 0, iclass 30, count 0 2006.162.08:30:03.73#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.162.08:30:03.73#ibcon#[28=FRQ=06,752.99\r\n] 2006.162.08:30:03.73#ibcon#*before write, iclass 30, count 0 2006.162.08:30:03.73#ibcon#enter sib2, iclass 30, count 0 2006.162.08:30:03.73#ibcon#flushed, iclass 30, count 0 2006.162.08:30:03.73#ibcon#about to write, iclass 30, count 0 2006.162.08:30:03.74#ibcon#wrote, iclass 30, count 0 2006.162.08:30:03.74#ibcon#about to read 3, iclass 30, count 0 2006.162.08:30:03.77#ibcon#read 3, iclass 30, count 0 2006.162.08:30:03.77#ibcon#about to read 4, iclass 30, count 0 2006.162.08:30:03.77#ibcon#read 4, iclass 30, count 0 2006.162.08:30:03.77#ibcon#about to read 5, iclass 30, count 0 2006.162.08:30:03.77#ibcon#read 5, iclass 30, count 0 2006.162.08:30:03.77#ibcon#about to read 6, iclass 30, count 0 2006.162.08:30:03.77#ibcon#read 6, iclass 30, count 0 2006.162.08:30:03.77#ibcon#end of sib2, iclass 30, count 0 2006.162.08:30:03.77#ibcon#*after write, iclass 30, count 0 2006.162.08:30:03.77#ibcon#*before return 0, iclass 30, count 0 2006.162.08:30:03.77#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:30:03.77#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.162.08:30:03.77#ibcon#about to clear, iclass 30 cls_cnt 0 2006.162.08:30:03.77#ibcon#cleared, iclass 30 cls_cnt 0 2006.162.08:30:03.78$vc4f8/vb=6,4 2006.162.08:30:03.78#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.162.08:30:03.78#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.162.08:30:03.78#ibcon#ireg 11 cls_cnt 2 2006.162.08:30:03.78#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.162.08:30:03.82#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.162.08:30:03.82#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.162.08:30:03.82#ibcon#enter wrdev, iclass 32, count 2 2006.162.08:30:03.82#ibcon#first serial, iclass 32, count 2 2006.162.08:30:03.82#ibcon#enter sib2, iclass 32, count 2 2006.162.08:30:03.82#ibcon#flushed, iclass 32, count 2 2006.162.08:30:03.82#ibcon#about to write, iclass 32, count 2 2006.162.08:30:03.82#ibcon#wrote, iclass 32, count 2 2006.162.08:30:03.82#ibcon#about to read 3, iclass 32, count 2 2006.162.08:30:03.84#ibcon#read 3, iclass 32, count 2 2006.162.08:30:03.84#ibcon#about to read 4, iclass 32, count 2 2006.162.08:30:03.84#ibcon#read 4, iclass 32, count 2 2006.162.08:30:03.84#ibcon#about to read 5, iclass 32, count 2 2006.162.08:30:03.84#ibcon#read 5, iclass 32, count 2 2006.162.08:30:03.84#ibcon#about to read 6, iclass 32, count 2 2006.162.08:30:03.84#ibcon#read 6, iclass 32, count 2 2006.162.08:30:03.84#ibcon#end of sib2, iclass 32, count 2 2006.162.08:30:03.84#ibcon#*mode == 0, iclass 32, count 2 2006.162.08:30:03.84#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.162.08:30:03.84#ibcon#[27=AT06-04\r\n] 2006.162.08:30:03.84#ibcon#*before write, iclass 32, count 2 2006.162.08:30:03.84#ibcon#enter sib2, iclass 32, count 2 2006.162.08:30:03.84#ibcon#flushed, iclass 32, count 2 2006.162.08:30:03.84#ibcon#about to write, iclass 32, count 2 2006.162.08:30:03.84#ibcon#wrote, iclass 32, count 2 2006.162.08:30:03.85#ibcon#about to read 3, iclass 32, count 2 2006.162.08:30:03.87#ibcon#read 3, iclass 32, count 2 2006.162.08:30:03.87#ibcon#about to read 4, iclass 32, count 2 2006.162.08:30:03.87#ibcon#read 4, iclass 32, count 2 2006.162.08:30:03.87#ibcon#about to read 5, iclass 32, count 2 2006.162.08:30:03.87#ibcon#read 5, iclass 32, count 2 2006.162.08:30:03.87#ibcon#about to read 6, iclass 32, count 2 2006.162.08:30:03.87#ibcon#read 6, iclass 32, count 2 2006.162.08:30:03.87#ibcon#end of sib2, iclass 32, count 2 2006.162.08:30:03.87#ibcon#*after write, iclass 32, count 2 2006.162.08:30:03.87#ibcon#*before return 0, iclass 32, count 2 2006.162.08:30:03.87#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.162.08:30:03.87#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.162.08:30:03.87#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.162.08:30:03.87#ibcon#ireg 7 cls_cnt 0 2006.162.08:30:03.87#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.162.08:30:03.99#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.162.08:30:03.99#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.162.08:30:03.99#ibcon#enter wrdev, iclass 32, count 0 2006.162.08:30:03.99#ibcon#first serial, iclass 32, count 0 2006.162.08:30:03.99#ibcon#enter sib2, iclass 32, count 0 2006.162.08:30:03.99#ibcon#flushed, iclass 32, count 0 2006.162.08:30:03.99#ibcon#about to write, iclass 32, count 0 2006.162.08:30:03.99#ibcon#wrote, iclass 32, count 0 2006.162.08:30:03.99#ibcon#about to read 3, iclass 32, count 0 2006.162.08:30:04.01#ibcon#read 3, iclass 32, count 0 2006.162.08:30:04.01#ibcon#about to read 4, iclass 32, count 0 2006.162.08:30:04.01#ibcon#read 4, iclass 32, count 0 2006.162.08:30:04.01#ibcon#about to read 5, iclass 32, count 0 2006.162.08:30:04.01#ibcon#read 5, iclass 32, count 0 2006.162.08:30:04.01#ibcon#about to read 6, iclass 32, count 0 2006.162.08:30:04.01#ibcon#read 6, iclass 32, count 0 2006.162.08:30:04.01#ibcon#end of sib2, iclass 32, count 0 2006.162.08:30:04.01#ibcon#*mode == 0, iclass 32, count 0 2006.162.08:30:04.01#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.162.08:30:04.01#ibcon#[27=USB\r\n] 2006.162.08:30:04.01#ibcon#*before write, iclass 32, count 0 2006.162.08:30:04.01#ibcon#enter sib2, iclass 32, count 0 2006.162.08:30:04.01#ibcon#flushed, iclass 32, count 0 2006.162.08:30:04.01#ibcon#about to write, iclass 32, count 0 2006.162.08:30:04.01#ibcon#wrote, iclass 32, count 0 2006.162.08:30:04.02#ibcon#about to read 3, iclass 32, count 0 2006.162.08:30:04.04#ibcon#read 3, iclass 32, count 0 2006.162.08:30:04.04#ibcon#about to read 4, iclass 32, count 0 2006.162.08:30:04.04#ibcon#read 4, iclass 32, count 0 2006.162.08:30:04.04#ibcon#about to read 5, iclass 32, count 0 2006.162.08:30:04.04#ibcon#read 5, iclass 32, count 0 2006.162.08:30:04.04#ibcon#about to read 6, iclass 32, count 0 2006.162.08:30:04.04#ibcon#read 6, iclass 32, count 0 2006.162.08:30:04.04#ibcon#end of sib2, iclass 32, count 0 2006.162.08:30:04.04#ibcon#*after write, iclass 32, count 0 2006.162.08:30:04.04#ibcon#*before return 0, iclass 32, count 0 2006.162.08:30:04.04#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.162.08:30:04.04#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.162.08:30:04.04#ibcon#about to clear, iclass 32 cls_cnt 0 2006.162.08:30:04.04#ibcon#cleared, iclass 32 cls_cnt 0 2006.162.08:30:04.05$vc4f8/vabw=wide 2006.162.08:30:04.05#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.162.08:30:04.05#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.162.08:30:04.05#ibcon#ireg 8 cls_cnt 0 2006.162.08:30:04.05#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:30:04.05#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:30:04.05#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:30:04.05#ibcon#enter wrdev, iclass 34, count 0 2006.162.08:30:04.05#ibcon#first serial, iclass 34, count 0 2006.162.08:30:04.05#ibcon#enter sib2, iclass 34, count 0 2006.162.08:30:04.05#ibcon#flushed, iclass 34, count 0 2006.162.08:30:04.05#ibcon#about to write, iclass 34, count 0 2006.162.08:30:04.05#ibcon#wrote, iclass 34, count 0 2006.162.08:30:04.05#ibcon#about to read 3, iclass 34, count 0 2006.162.08:30:04.06#ibcon#read 3, iclass 34, count 0 2006.162.08:30:04.06#ibcon#about to read 4, iclass 34, count 0 2006.162.08:30:04.06#ibcon#read 4, iclass 34, count 0 2006.162.08:30:04.06#ibcon#about to read 5, iclass 34, count 0 2006.162.08:30:04.06#ibcon#read 5, iclass 34, count 0 2006.162.08:30:04.06#ibcon#about to read 6, iclass 34, count 0 2006.162.08:30:04.06#ibcon#read 6, iclass 34, count 0 2006.162.08:30:04.06#ibcon#end of sib2, iclass 34, count 0 2006.162.08:30:04.06#ibcon#*mode == 0, iclass 34, count 0 2006.162.08:30:04.06#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.162.08:30:04.06#ibcon#[25=BW32\r\n] 2006.162.08:30:04.06#ibcon#*before write, iclass 34, count 0 2006.162.08:30:04.06#ibcon#enter sib2, iclass 34, count 0 2006.162.08:30:04.06#ibcon#flushed, iclass 34, count 0 2006.162.08:30:04.06#ibcon#about to write, iclass 34, count 0 2006.162.08:30:04.06#ibcon#wrote, iclass 34, count 0 2006.162.08:30:04.07#ibcon#about to read 3, iclass 34, count 0 2006.162.08:30:04.09#ibcon#read 3, iclass 34, count 0 2006.162.08:30:04.09#ibcon#about to read 4, iclass 34, count 0 2006.162.08:30:04.09#ibcon#read 4, iclass 34, count 0 2006.162.08:30:04.09#ibcon#about to read 5, iclass 34, count 0 2006.162.08:30:04.09#ibcon#read 5, iclass 34, count 0 2006.162.08:30:04.09#ibcon#about to read 6, iclass 34, count 0 2006.162.08:30:04.09#ibcon#read 6, iclass 34, count 0 2006.162.08:30:04.09#ibcon#end of sib2, iclass 34, count 0 2006.162.08:30:04.09#ibcon#*after write, iclass 34, count 0 2006.162.08:30:04.09#ibcon#*before return 0, iclass 34, count 0 2006.162.08:30:04.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:30:04.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.162.08:30:04.09#ibcon#about to clear, iclass 34 cls_cnt 0 2006.162.08:30:04.09#ibcon#cleared, iclass 34 cls_cnt 0 2006.162.08:30:04.10$vc4f8/vbbw=wide 2006.162.08:30:04.10#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.162.08:30:04.10#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.162.08:30:04.10#ibcon#ireg 8 cls_cnt 0 2006.162.08:30:04.10#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:30:04.15#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:30:04.15#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:30:04.15#ibcon#enter wrdev, iclass 36, count 0 2006.162.08:30:04.15#ibcon#first serial, iclass 36, count 0 2006.162.08:30:04.15#ibcon#enter sib2, iclass 36, count 0 2006.162.08:30:04.15#ibcon#flushed, iclass 36, count 0 2006.162.08:30:04.15#ibcon#about to write, iclass 36, count 0 2006.162.08:30:04.15#ibcon#wrote, iclass 36, count 0 2006.162.08:30:04.15#ibcon#about to read 3, iclass 36, count 0 2006.162.08:30:04.17#ibcon#read 3, iclass 36, count 0 2006.162.08:30:04.17#ibcon#about to read 4, iclass 36, count 0 2006.162.08:30:04.17#ibcon#read 4, iclass 36, count 0 2006.162.08:30:04.17#ibcon#about to read 5, iclass 36, count 0 2006.162.08:30:04.17#ibcon#read 5, iclass 36, count 0 2006.162.08:30:04.17#ibcon#about to read 6, iclass 36, count 0 2006.162.08:30:04.17#ibcon#read 6, iclass 36, count 0 2006.162.08:30:04.17#ibcon#end of sib2, iclass 36, count 0 2006.162.08:30:04.17#ibcon#*mode == 0, iclass 36, count 0 2006.162.08:30:04.17#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.162.08:30:04.17#ibcon#[27=BW32\r\n] 2006.162.08:30:04.17#ibcon#*before write, iclass 36, count 0 2006.162.08:30:04.17#ibcon#enter sib2, iclass 36, count 0 2006.162.08:30:04.17#ibcon#flushed, iclass 36, count 0 2006.162.08:30:04.17#ibcon#about to write, iclass 36, count 0 2006.162.08:30:04.17#ibcon#wrote, iclass 36, count 0 2006.162.08:30:04.18#ibcon#about to read 3, iclass 36, count 0 2006.162.08:30:04.21#ibcon#read 3, iclass 36, count 0 2006.162.08:30:04.21#ibcon#about to read 4, iclass 36, count 0 2006.162.08:30:04.21#ibcon#read 4, iclass 36, count 0 2006.162.08:30:04.21#ibcon#about to read 5, iclass 36, count 0 2006.162.08:30:04.21#ibcon#read 5, iclass 36, count 0 2006.162.08:30:04.21#ibcon#about to read 6, iclass 36, count 0 2006.162.08:30:04.21#ibcon#read 6, iclass 36, count 0 2006.162.08:30:04.21#ibcon#end of sib2, iclass 36, count 0 2006.162.08:30:04.21#ibcon#*after write, iclass 36, count 0 2006.162.08:30:04.21#ibcon#*before return 0, iclass 36, count 0 2006.162.08:30:04.21#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:30:04.21#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.162.08:30:04.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.162.08:30:04.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.162.08:30:04.21$4f8m12a/ifd4f 2006.162.08:30:04.21$ifd4f/lo= 2006.162.08:30:04.21$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.162.08:30:04.21$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.162.08:30:04.21$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.162.08:30:04.21$ifd4f/patch= 2006.162.08:30:04.21$ifd4f/patch=lo1,a1,a2,a3,a4 2006.162.08:30:04.21$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.162.08:30:04.21$ifd4f/patch=lo3,a5,a6,a7,a8 2006.162.08:30:04.21$4f8m12a/"form=m,16.000,1:2 2006.162.08:30:04.21$4f8m12a/"tpicd 2006.162.08:30:04.21$4f8m12a/echo=off 2006.162.08:30:04.21$4f8m12a/xlog=off 2006.162.08:30:04.21:!2006.162.08:30:30 2006.162.08:30:10.14#trakl#Source acquired 2006.162.08:30:12.15#flagr#flagr/antenna,acquired 2006.162.08:30:30.00:preob 2006.162.08:30:31.15/onsource/TRACKING 2006.162.08:30:31.15:!2006.162.08:30:40 2006.162.08:30:40.02:data_valid=on 2006.162.08:30:40.02:midob 2006.162.08:30:41.15/onsource/TRACKING 2006.162.08:30:41.15/wx/17.78,1006.8,100 2006.162.08:30:41.24/cable/+6.5365E-03 2006.162.08:30:42.33/va/01,08,usb,yes,32,34 2006.162.08:30:42.33/va/02,07,usb,yes,32,34 2006.162.08:30:42.33/va/03,06,usb,yes,34,34 2006.162.08:30:42.33/va/04,07,usb,yes,33,35 2006.162.08:30:42.33/va/05,07,usb,yes,35,37 2006.162.08:30:42.33/va/06,06,usb,yes,34,34 2006.162.08:30:42.33/va/07,06,usb,yes,34,34 2006.162.08:30:42.33/va/08,07,usb,yes,33,32 2006.162.08:30:42.56/valo/01,532.99,yes,locked 2006.162.08:30:42.56/valo/02,572.99,yes,locked 2006.162.08:30:42.56/valo/03,672.99,yes,locked 2006.162.08:30:42.56/valo/04,832.99,yes,locked 2006.162.08:30:42.56/valo/05,652.99,yes,locked 2006.162.08:30:42.56/valo/06,772.99,yes,locked 2006.162.08:30:42.56/valo/07,832.99,yes,locked 2006.162.08:30:42.56/valo/08,852.99,yes,locked 2006.162.08:30:43.65/vb/01,04,usb,yes,29,27 2006.162.08:30:43.65/vb/02,04,usb,yes,30,32 2006.162.08:30:43.65/vb/03,04,usb,yes,27,30 2006.162.08:30:43.65/vb/04,04,usb,yes,28,28 2006.162.08:30:43.65/vb/05,04,usb,yes,26,30 2006.162.08:30:43.65/vb/06,04,usb,yes,27,30 2006.162.08:30:43.65/vb/07,04,usb,yes,29,29 2006.162.08:30:43.65/vb/08,04,usb,yes,27,30 2006.162.08:30:43.88/vblo/01,632.99,yes,locked 2006.162.08:30:43.88/vblo/02,640.99,yes,locked 2006.162.08:30:43.88/vblo/03,656.99,yes,locked 2006.162.08:30:43.88/vblo/04,712.99,yes,locked 2006.162.08:30:43.88/vblo/05,744.99,yes,locked 2006.162.08:30:43.88/vblo/06,752.99,yes,locked 2006.162.08:30:43.88/vblo/07,734.99,yes,locked 2006.162.08:30:43.88/vblo/08,744.99,yes,locked 2006.162.08:30:44.03/vabw/8 2006.162.08:30:44.18/vbbw/8 2006.162.08:30:44.27/xfe/off,on,15.0 2006.162.08:30:44.67/ifatt/23,28,28,28 2006.162.08:30:45.07/fmout-gps/S +4.52E-07 2006.162.08:30:45.12:!2006.162.08:31:40 2006.162.08:31:40.02:data_valid=off 2006.162.08:31:40.02:postob 2006.162.08:31:40.21/cable/+6.5373E-03 2006.162.08:31:40.22/wx/17.78,1006.8,100 2006.162.08:31:41.07/fmout-gps/S +4.53E-07 2006.162.08:31:41.08:checkk5last 2006.162.08:31:41.08&checkk5last/chk_obsdata=1 2006.162.08:31:41.09&checkk5last/chk_obsdata=2 2006.162.08:31:41.09&checkk5last/chk_obsdata=3 2006.162.08:31:41.09&checkk5last/chk_obsdata=4 2006.162.08:31:41.10&checkk5last/k5log=1 2006.162.08:31:41.10&checkk5last/k5log=2 2006.162.08:31:41.10&checkk5last/k5log=3 2006.162.08:31:41.11&checkk5last/k5log=4 2006.162.08:31:41.11&checkk5last/obsinfo 2006.162.08:31:41.57/chk_obsdata//k5ts1/T1620830??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:31:42.02/chk_obsdata//k5ts2/T1620830??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:31:42.40/chk_obsdata//k5ts3/T1620830??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:31:42.84/chk_obsdata//k5ts4/T1620830??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.162.08:31:43.81/k5log//k5ts1_log_newline 2006.162.08:31:44.51/k5log//k5ts2_log_newline 2006.162.08:31:45.29/k5log//k5ts3_log_newline 2006.162.08:31:46.09/k5log//k5ts4_log_newline 2006.162.08:31:46.12/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.162.08:31:46.12:sched_end 2006.162.08:31:46.12&sched_end/stopcheck 2006.162.08:31:46.12&stopcheck/sy=killall check_fsrun.pl 2006.162.08:31:46.12&stopcheck/" sy=killall chmem.sh 2006.162.08:31:46.21:source=idle 2006.162.08:31:47.13#flagr#flagr/antenna,new-source 2006.162.08:31:47.14:stow 2006.162.08:31:47.14&stow/source=idle 2006.162.08:31:47.15&stow/"this is stow command. 2006.162.08:31:47.15&stow/antenna=m3 2006.162.08:31:51.02:!+10m 2006.162.08:41:51.03:standby 2006.162.08:41:51.04&standby/"this is standby command. 2006.162.08:41:51.04&standby/antenna=m0 2006.162.08:41:52.01:sy=cp /usr2/log/k06162ts.log /usr2/log_backup/ 2006.162.08:41:52.10:*end of schedule